1992_Cypress_Bi CMOS_CMOS_Data_Book 1992 Cypress Bi CMOS Data Book
User Manual: 1992_Cypress_BiCMOS_CMOS_Data_Book
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CYPRESS
SEMICONDUCTOR
CMOS/BiCMOS
Data Book
Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 9109970753, FAX: (408) 943-2741
~~PR£SS
~J,.
SEMICONDUCTOR
How To Use This Book
Key to Waveform Diagrams
Overall Organization
This book has been organized by product type, beginning with Product Information. The products are
next, starting with SRAMs, then PROMs, EPLDs,
FIFOs, Logic, RISC, Modules, EeL, and bus interface products. A section containing military information is next, followed by the Design and Programming
Tools section. Quality and Reliability aspects are
next, then Thermal Data and Packages. Within each
section, data sheets are arranged in order of part
number.
Rising edge of signal will
occur during this time.
Falling edge of signal will
occur during this time.
Signal may transition
during this time (don't
care condition).
Recommended Search Paths
To search by:
Use:
Product line
Table of Contents or flip
through the book using the
tabs on the right-hand pages.
Size
The Product Selector Guide
in section 1.
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
state during this time.
Numeric part number Numeric Device Index in
section 1. The book is also
arranged in order of part
number.
Other manufacturer's Thc Cross Reference Guide
part number
in section 1.
Military part number
The Military Selector Guide
in section 11.
Published March 1, 1992
© Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cyrrass Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than cirCUitry embodied in a Cypress SemiconductorCorporatlon product. Nor does it conveyor Imply any license under patentor other rights. Cypress Semiconductor does not authorize its products for use as critical components in Ufe-support systems where a malfunctiOh or failure the product may reasonably be expected to result in significant
Injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manlJfucturer assumesalilisk of such use and in so doing Indemnmes
Cypress Semiconductor against all damages.
0'
~
'~PRESS
--=-.'
Table of Contents
SEMICONDUCTOR
Page Number
Table of Contents
General Product Information
Cypress Semiconductor Background and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information ......................................................................................
Cypress Semiconductor Bulletin Board System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Notes Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-3
1-5
1-6
1-8
1-15
Static RAMs (Random Access Memory)
Device Number
CY2147
CY2148
CY21L48
CY2149
CY21L49
CY6116
CY6116A
CY6117A
CY7C101
CY7CI02
CY7C106
CY7C107
CY7CI08
CY7C109
CY7C122
CY7C123
CY7CI28
CY7C128A
CY7C130
CY7C131
CY7C140
CY7C141
CY7C132
CY7C136
CY7C142
CY7C146
CY7B134
CY7B135
CY7B1342
CY7B138
CY7B139
CY7B144
CY7C147
CY7C148
CY7C149
CY7C150
CY7B153
CY7B154
CY7C157A
CY7C158
CY7C159
Description
4096 x 1 Static R!W RAM ...................................................... .
1024 x 4 Static R!W RAM ...................................................... .
1024 x 4 Static R!W RAM, Low Power ............................................ .
1024 x 4 Static R!W RAM ...................................................... .
1024 x 4 Static R!W RAM, Low Power ............................................ .
2048 x 8 Static R!W RAM ..................................................... .
2048 x 8 Static R!W RAM ..................................................... .
2048 x 8 Static R!W RAM ..................................................... .
262,144 x 4 Static R!W RAM with Separate I/O ................................... .
262,144 x 4 Static R!W RAM with Separate I/O ................................... .
262,144 x 4 Static R!W RAM .................................................. .
1,048,576 x 1 Static R!W RAM ................................................. .
131,072 x 8 Static R!W RAM .................................................. .
131,072 x 8 Static R!W RAM .................................................. .
256 x 4 Static R!W RAM Separate I/O ........................................... .
256 x 4 Static R!W RAM Separate I/O ........................................... .
2048 x 8 Static R!W RAM ..................................................... .
2048 x 8 Static R!W RAM ..................................................... .
1024 x 8 Dual-Port Static RAM ................................................. .
1024 x 8 Dual-Port Static RAM ................................................. .
1024 x 8 Dual-Port Static RAM ................................................. .
1024 x 8 Dual-Port Static RAM ................................................. .
2048 x 8 Dual-Port Static RAM ................................................. .
2048 x 8 Dual-Port Static RAM ................................................. .
2048 x 8 Dual-Port Static RAM ................................................. .
2048 x 8 Dual-Port Static RAM ................................................. .
4Kx 8 Dual-Port Static RAM ................................................. .
4Kx 8 Dual-Port Static RAM ................................................. .
4Kx 8 Dual-Port Static RAM with Semaphores ................................... .
4K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY ..................... .
4Kx 8 Dual-Port Static RAM with Semaphores, llIi'T, and BUSY ..................... .
8K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY ..................... .
4096 x 1 Static RAM ........................................................ .
1024 x 4 Static RAM ........................................................ .
1024 x 4 Static RAM ........................................................ .
1024 x 4 Static R!W RAM .................................................... .
65,536 x 4 Expandable Static R!W RAM ........................................ .
65,536 x 4 Expandable Static R!W RAM ........................................ .
16,384 x 16 Static R!W Cache Storage Unit ...................................... .
Self-Timed Pipelined Static RAM .............................................. .
Self-Timed Pipelined Static RAM .............................................. .
2-1
2-6
2-6
2-6
2-6
2-12
2-19
2-19
2-26
2-26
2-32
2-38
2-44
2-44
2-51
2-57
2-63
2-70
2-78
2-78
2-78
2-78
2-91
2-91
2-91
2-91
2-104
2-104
2-104
2-114
2-114
2-128
2-142
2-149
2-149
2-156
2-164
2-164
2-171
2-177
2-178
j
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_ , SEMICONDUCIDR
Table of Contents
Static RAMs (Random Access Memory) (continued)
Device Number
CY7B161
CY7B162
CY7C161
CY7C162
CY7C161A
CY7C162A
CY7B163
CY7BI64
CY7B166
CY7CI64
CY7C166
CY7CI64A
CY7C166A
CY7C167
CY7C167A
CY7C168
CY7C169
CY7C168A
CY7C169A
CY7C170
CY7C170A
CY7CI71
CY7CI72
CY7CI71A
CY7CI72A
CY7B173
CY7B174
CY7B180
CY7B181
CY7C182
CY7C183
CY7C184
CY7B185
CY7B186
CY7C185
CY7C186
CY7C185A
CY7C186A
CY7C187
CY7C187A
CY7C189
CY7CI90
CY7B191
CY7B192
CY7C191
CY7C192
CY7B193
CY7B194
CY7B195
CY7B196
CY7C194
Page Number
Description
16,384 x 4 Static RAM Separate I/O ............................................ .
16,384 x 4 Static RAM Separate I/O ............................................ .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
Expandable 262,144 x 1 Static R/W RAM with Separate I/O ........................ .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM with Output Enable .................................. .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM with Output Enable .................................. .
16,384 x 1 Static R/W RAM .................................................. .
16,384 x 1 Static RAM ....................................................... .
4096 x 4 Static RAM ........................................................ .
4096 x 4 Static RAM ........................................................ .
4096 x 4 R/W RAM ......................................................... .
4096 x 4 R/W RAM ......................................................... .
4096 x 4 Static R/W RAM .................................................... .
4096 x 4 Static R/W RAM .................................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
32,768 x 9 Synchronous Cache R/W RAM ....................................... .
32,768 x 9 Synchronous Cache R/W RAM ....................................... .
4Kx 18 Cache Tag .......................................................... .
4Kx 18 Cache Tag .......................................................... .
8,192 x 9 Static R/W RAM ................................................... .
2 x 4096 x 16 Cache RAM ................•....................................
2 x 4096 x 16 Cache RAM .................................................... .
8,192 x 8 Static RAM ........................................................ .
8,192 x 8 Static RAM ........................................................ .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
65,536 x 1 Static R/W RAM .................................................. .
65,536 x 1 Static R/W RAM .................................................. .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
262,144 x 1 Static R/W RAM ................................................. .
65,536 x 4 Static R/W RAM .................................................. .
65,536 x 4 Static R/W RAM with Output Enable .................................. .
65,536 x 4 Static R/W RAM with Output Enable .................................. .
65,536 x 4 Static R/W RAM .................................................. .
2-179
2-179
2-185
2-185
2-194
2-194
2-202
2-208
2-208
2-214
2-214
2-223
2-223
2-231
2-238
2-245
2-245
2-252
2-252
2-261
2-266
2-271
2-271
2-277
2-277
2-285
2-285
2-294
2-294
2-313
2-320
2-320
2-328
2-328
2-333
2-333
2-342
2-342
2-351
2-360
2-368
2-368
2-374
2-374
2-380
2-380
2-388
2-394
2-394
2-394
2-402
:~
Table of Contents
~=CYPRESS
F
SEMlCONDUC1DR
Static RAMs (Random Access Memory) (continued)
Device Number
CY7C195
CY7C196
CY7B197
CY7C197
CY7C198
CY7C199
CY7B199
CY7C1001
CY7C1002
CY7C1006
CY7C1007
CY7C1009
CY7M194
CY7M199
CY74S189
CY27LS03
CY27S03
CY27S07
CY93422A
CY93L422A
CY93422
CY93L422
Page Number
Description
65,536 x 4 Static R/W RAM with Output Enable .................................. .
65,536 x 4 Static R/W RAM with Output Enable .................................. .
262,144 x 1 Static R/W RAM ................................................. .
262,144 x 1 Static R/W RAM ................................................. .
32,768 x 8 Static R/W RAM .................................................. .
32,768 x 8 Static R/W RAM .................................................. .
32,768 x 8 Static R/W RAM .................................................. .
256K x 4 Static R/W RAM with Separate I/O .................................... .
256K x 4 Static R/W RAM with Separate I/O .................................... .
256K x 4 Static R/W RAM .................................................... .
1M x 1 Static R/W RAM ..................................................... .
128K x 8 Static R/W RAM .................................................... .
64K x 4 Static RAM Module .................................................. .
32K x 8 Static RAM Module .................................................. .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
256 x 4 Static R/W RAM ..................................................... .
256 x 4 Static R/W RAM ..................................................... .
256 x 4 Static R/W RAM .................................................... ..
256 x 4 Static R/W RAM ..................................................... .
2-402
2-402
2-411
2-417
2-425
2-425
2-435
2-441
2-441
2-442
2-443
2-444
2-445
2-446
2-451
2-451
2-451
2-451
2-456
2-456
2-456
2-456
PROMs (Programmable Read Only Memory)
Introduction to PROMs ....................................................................................
Device Number
CY7B201
CY7B21O
CY7B211
CY7C225
CY7C235
CY7C245
CY7C245A
CY7C251
CY7C254
CY7C258
CY7C259
CY7C261
CY7C263
CY7C264
CY7C265
CY7C266
CY7C268
CY7C269
CY7C270
CY7C271
CY7C274
CY7C272
CY7C273
CY7C275
3-1
Description
128Kx 8 Reprogrammable Power-Down PROM ................................... . 3-4
64Kx 16 Reprogrammable Power-Down PROM ................................... . 3-9
ReprogrammabJe Registered PROM ........................................... .. 3-14
3-19
512 x 8 Registered PROM .................................................... ..
3-26
1024 x 8 Registered PROM ................................................... ..
2048 x 8 Reprogrammable Registered PROM .................................... .. 3-33
2048 x 8 ReprogrammabJe Registered PROM ..................................... . 3-34
16,384 x 8 Power-Switched and ReprogrammabJe PROM ........................... . 3-42
16,384 x 8 ReprogrammabJe PROM ............................................. . 3-42
2Kx 16 ReprogrammabJe State Machine PROM .................................. . 3-48
2Kx 16 ReprogrammabJe State Machine PROM .................................. . 3-48
8192 x 8 Power-Switched and Reprogrammable PROM ............................. . 3-59
8192x 8 ReprogrammabJe PROM ............................................. .. 3-59
8192 x 8 Reprogrammable PROM ............................................. .. 3-59
3-68
64K Registered PROM ....................................................... .
8192 x 8 Power-Switched and Reprogrammable PROM ............................. . 3-76
8192 Registered Diagnostic PROM ............................................. . 3-83
8192 Registered Diagnostic PROM ............................................ .. 3-83
16Kx 16 Processor-Specific PROM ............................................. . 3-96
32,768 x 8 Power Switched and Reprogrammable PROM ........................... . 3-106
32,768 x 8 Reprogrammable PROM ............................................ . 3-106
16Kx 16 Reprogrammable Registered PROM .................................. .. 3-114
16Kx 16 Power-Switched and Reprogrammable PROM ............................ . 3-121
16Kx 16 Reprogrammable Registered PROM .................................. .. 3-126
iii
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Table of Contents
~S-=CYPRFSS
~, SEMICONDUcroR
PROMs (Programmable Read Only Memory)
Device Number
(continued)
Page Number
Description
CY7Cl76
CY7Cl77
16Kx 16 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . .
32,768 x 8 Reprogrammable Registered PROM ...................................
CY7C279
32,768 x 8 Reprogrammable Registered PROM ...................................
1024 x 8 PROM .............................................................
CY7Cl81
CY7C282
1024 x 8 PROM ............................................................ .
CY7C285
65,536 x 8 Reprogrammable Fast Column Access PROM ........................... .
CY7C289
65,536 x 8 Reprogrammable Fast Column Access PROM ........................... .
CY7C286
65,536 x 8 Reprogrammable Registered PROM .................................. .
CY7C287
65,536 x 8 Reprogrammable Registered PROM .................................. .
CY7Cl91
2048 x 8 Reprogrammable PROM ............................................. .
CY7C292
2048 x 8 Reprogrammable PROM ............................................. .
CY7Cl91A
2048 x 8 Reprogrammable PROM ............................................. .
2048 x 8 Reprogrammable PROM ............................................. .
CY7C292A
CY7Cl93A
2048 x 8 Reprogrammable PROM ............................................. .
PROM Programming Information ......................................................................... .
3-133
3-138
3-138
3-147
3-147
3-153
3-153
3-162
3-162
3-169
3-169
3-170
3-170
3-170
3-178
PLDs (Programmable Logic Devices)
Introduction to Cypress PIDs .............................................................................. .
Device Number
PIDC18G8
PALClO Series
PAUO Series
PALC20GlO
PALC20GlOB
PALC20GlOC
PLDC20RAlO
PALC22VlO
PALCl2V10B
PAU2VlOC
PAL22VPlOC
PAU2V10D
CY7C325
CY7C330
CY7C331
CY7C332
CY7B333
CY7B335
CY7B336
CY7B337
CY7B338
CY7B339
CY7C340 EPLD Family
CY7C341
CY7C342
CY7C345
CY7C343
CY7C344
CY7C361
PLD610
PLD Programming Information
4-1
Description
CMOS Generic 20-Pin Programmable Logic Device ................................. . 4-6
Reprogrammable CMOS PAL C 16L8, 16R8, 16R6, 16R4 ........................... . 4-13
5-ns, Industry-Standard, 20-Pin PLDs ............................................ . 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. . 4-29
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. . 4-29
Generic 24-Pin PAL Device .................................................... .
4-37
Reprogrammable Asynchronous CMOS Logic Device .............................. . 4-47
Reprogrammable CMOS PAL Device ........................................... . 4-57
Reprogrammable CMOS PAL Device ........................................... . 4-67
4-77
Universal PAL Device ........................................................ .
Universal PAL Device ........................................................ .
4-77
Flash Erasable, Reprogrammable CMOS PAL Device .............................. . 4-88
4-95
Timing Control Unit ......................................................... .
CMOS Programmable Synchronous State Machine ................................ . 4-102
Asynchronous Registered EPID .............................................. . 4-113
Registered Combinatorial EPLD .............................................. . 4-126
General-Purpose Synchronous BiCMOS PLD .................................... . 4-136
Universal Synchronous EPLD ................................................. . 4-144
6-ns BiCMOS PAL with Input Registers ......................................... . 4-157
7-ns BiCMOS PAL with Input Registers ......................................... . 4-163
6-ns BiCMOS PAL with Output Latches ........................................ . 4-169
7-ns BiCMOS PAL with Output Latches ........................................ . 4-175
Multiple Array Matrix High-Density EPLDs ..................................... . 4-181
192-Macrocell MAX EPID .................................................. . 4-190
128-Macrocell MAX EPLD .................................................. . 4-201
128-Macrocell MAX EPLD .................................................. . 4-201
64-Macrocell MAX EPID ................................................... . 4-214
32-Macrocell MAX EPID ................................................... . 4-225
Ultra High Speed State Machine EPID ......................................... . 4-235
Multipurpose BiCMOS PID .................................................. . 4-249
........................................................................... .
4-257
iv
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_'= CYPRF.SS
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Table of Contents
SEMICONDUC'TOR
FIFOs
Device Number
CY3341
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C432
CY7C433
CY7C439
CY7C441
CY7C443
CY7C451
CY7C453
CY7C460
CY7C462
CY7C464
CY7C470
CY7C472
CY7C474
Page Number
Description
5-1
64 x 4 Serial MemOl), FIFO ..................................................... .
5-6
64 x 4 Cascadeable FIFO ....................................................... .
64 x 5 Cascadeable FIFO ....................................................... .
5-6
64 x 4 Cascadeable FIFO with Output Enable ...................................... . 5-6
64 x 5 Cascadeable FIFO with Output Enable ...................................... . 5-6
5-16
64 x 8 Cascadeable FIFO ...................................................... .
5-16
64 x 9 Cascadeable FIFO ...................................................... .
512 x 9 Cascadeable FIFO ..................................................... .
5-30
5-30
512 x 9 Cascadeable FIFO ..................................................... .
5-30
1024 x 9 Cascadeable FIFO .................................................... .
5-30
1024 x 9 Cascadeable FIFO .................................................... .
5-30
2048 x 9 Cascadeable FIFO .................................................... .
2048 x 9 Cascadeable FIFO .................................................... .
5-30
4096 x 9 Cascadeable FIFO .................................................... .
5-45
4096 x 9 Cascadeable FIFO .................................................... .
5-45
5-58
2048 x 9 Bidirectional FIFO ................................................... .
5-71
512 x 9 Synchronous FIFO .................................................... .
5-71
2K x 9 Synchronous FIFO ..................................................... .
512 x 9 Cascadeable Clocked FIFO ............................................. . 5-84
2K x 9 CascadeabH: Clocked FIFO .............................................. . 5-84
5-105
8K x 9 Cascadeable FIFO .................................................... .
5-105
16K x 9 Cascadeable FIFO ................................................... .
32Kx 9 Cascadeable FIFO ................................................... .
5-105
5-117
8Kx9F1FO ............................................................... .
5-117
16Kx9FIFO .............................................................. .
5-117
32Kx9FIFO .............................................................. .
LOGIC
Device Number
CY2901C
CY2909A
CY2911A
CY2910A
CY7C510
CY7C516
CY7C517
CY7C901
CY7C909
CY7C911
CY7C910
CY7C9101
CY7C9115
CY7C9116
CY7C9117
Description
CMOS 4-Bit Slice ............................................................. .
CMOS Microprogram Sequencers ............................................... .
CMOS Microprogram Sequencers ............................................... .
CMOS Microprogram Controller ............................................... .
16 x 16 Multiplier Accumulator ................................................. .
16 x 16 Multipliers ........................................................... .
16 x 16 Multipliers ........................................................... .
CMOS 4-Bit Slice ............................................................ .
CMOS Microprogram Sequencers .............................................. .
CMOS Microprogram Sequencers .............................................. .
CMOS Microprogram Controller ............................................... .
CMOS 16-Bit Slice ........................................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
v
6-1
6-8
6-8
6-12
6-17
6-27
6-27
6-38
6-52
6-52
6-62
6-73
6-90
6-90
6-90
Table of Contents
Communication Products
Page Number
Device Number
Description
cY7B921
7-1
HOTUnk 'fransmitter/Receiver
7-1
HOTUnk 'fransmitter/Receiver
7-1
HOTUnk 'fransmitter/Receiver
7-1
HOTLink Transmitter/Receiver
7-1
HdTLink Transmitter/Receiver
HOTLink Transmitter/Receiver ................................................. . 7-1
Programmable Skew Clock Buffer (PSCB) ........................................ . 7-26
Programmable Skew Clock Buffer (PSCB) ........................................ . 7-26
CY~922
CY7B923
CY7B931
CY7B932
CY7B933
CY7B991
CY7B992
RISC
8-1
Introduction to RISC
Device Number
Description
CY7C601A
CY7C602A
CY7C604A
CY7C605A
CY7C611A
CY7C613
CY7C614
CY7C615
CY7C616
CY7C617
CY7C618
CYM6001K
CYM6002K
CYM6003K
32-Bit RISC Processor ......................................................... .
Floating-Point Unit .......................................................... .
Cache Controller and Memory Management Unit ................................. .
Cache Controller and Memory Management Unit ................................. .
32-Bit RISC Controller ....................................................... .
MBus Memory Controller ..................................................... .
MBus Peripheral I/O Controller ................................................ .
Interrupt Controller .......................................................... .
MBus-to-SBus Interface Controller ............................................. .
MBus-to-Video Graphics Controller ............................................ .
SBus Controller ............................................................. .
SPARCore CPU Module ...................................................... .
SPARCore Dual-CPU Module ................................................. .
SPARCore CPU Module for Multiprocessing ..................................... .
8-6
8-14
8-20
8-29
8-39
8-46
8-47
8-48
8-49
8-50
8-51
8-52
8-58
8-65
Modules
9-1
Custom Module Capabilities
Device Number
Description
CYMl240
CYM1420
CYM1422
CYM1423
CYM1441
CYMl460
CYM1461
CYMl464
CYM1465
CYM1466
CYM1471
CYMl481
CYM1540
CYM1560
CYM1610
CYM1611
CYM1620
CYM1621
CYM1622
256K x 4 Static RAM Module ................................................... .
128K x 8 Static RAM Module ................................................... .
128K x 8 Static RAM Module .................................................. .
128K x 8 Static RAM Module .................................................. .
256K x 8 Static RAM Module .................................................. .
512Kx 8 Static RAM Module .................................................. .
512Kx 8 Static RAM Module .................................................. .
512Kx 8 Static RAM Module .................................................. .
512Kx8 Static RAM Module .................................................. .
512Kx 8 Static RAM Module .................................................. .
1024Kx 8 Static RAM Module ................................................. .
2048K x 8 Static RAM Module ... '.............................................. .
256K x 9 Buffered Static RAM Module with Separate I/O ........................... .
lO24K x 9 Buffered Static RAM Module with Separate I/O .......................... .
16Kx 16 Static RAM Module .................................................. .
16Kx 16 Static RAM Module .................................................. .
64Kx 16 Static RAM Module .................................................. .
64K x 16 Static RAM Module .................................................. .
64Kx 16 Static RAM Module .................................................. .
vi
9-5
9-6
9-11
9-16
9-17
9-18
9-23
9-29
9-35
9-40
9-47
9-47
9-53
9-58
9-63
9-64
9-70
9-75
9-76
Table of Contents
Page Number
Modules (continued)
Device Number
CYM1624
CYM1641
CYM1720
CYM1730
CYM1821
CYM1822
CYM1828
CYM1830
CYM1831
CYM1832
CYM1836
CYM1838
CYM1840
CYM1841
CYM1910
CYM1911
CYM4210
CYM4220
CYM4241
CYM7232
CYM7264
Description
64K x 16 Static RAM Module .................................................. .
256K x 16 Static RAM Module ................................................. .
32K x 24 Static RAM Module .................................................. .
64K x 24 Static RAM Module .................................................. .
16Kx32 Static RAM Module ................................................. .
16Kx 32 Static RAM Module with Separate I/O .................................. .
32K x 32 Static RAM Module ................................................. .
64K x 32 Static RAM Module ................................................. .
64K x 32 Static RAM Module ................................................. .
64K x 32 Static RAM Module ................................................. .
128K x 32 Static RAM Module ................................................ .
128K x 32 Static RAM Module ................................................ .
256K X 32 Static RAM Module ............................................... .
256K x 32 Static RAM Module ................................................ .
16K x 68 Static RAM Module ................................................. .
16Kx 68 Static RAM Module ................................................. .
Cascadeable 8K x 9 FIFO .................................................... .
Cascadeable 16Kx 9 FIFO ................................................... .
64Kx9FIFO .............................................................. .
DRAM Controller Module ................................................... .
DRAM Controller Module ................................................... .
9-81
9-86
9-91
9-96
9-101
9-108
9-115
9-121
9-126
9-131
9-136
9-141
9-146
9-152
9-158
9-159
9-160
9-160
9-169
9-175
9-175
Description
Combinatorial ECL 16P8 Programmable Logic Device ............................. .
Combinatorial ECL 16P8 Programmable Logic Devicc ............................. .
Combinatorial ECL 16P4 Programmable Logic Device ............................. .
Combinatorial ECL 16P4 Programmable Logic Device ............................. .
ECUITL 1tanslator and High-Speed Bus Driver ................................. .
ECUITL 1tanslator and High-Speed Bus Driver ................................. .
256 x 4 ECL Static RAM ..................................................... .
256 x 4 ECL Static RAM ..................................................... .
4096 x 1 ECL Static RAM .................................................... .
4096 x 1 ECL Static RAM .................................................... .
1024 x 4 ECL Static RAM .................................................... .
1024 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
16,384 x 4 ECL Static RAM .................................................. .
16,384 x 4 ECL Static RAM .................................................. .
16,384 x 4 ECL Static RAM .................................................. .
10-1
10-1
10-6
10-6
10-11
10-11
10-17
10-17
10-24
10-24
10-29
10-29
10-36
10-36
10-36
10-43
10-43
10-43
EeL
Device Number
CYlOE301
CY100E301
CYlOE302
CY100E302
CYlOE383
CY101E383
CYlOE422
CY100E422
CYlOE470
CY100E470
CY10E474
CY100E474
CYlOE484
CY100E484
CY101E484
CYlOE494
CY100E494
CY101E494
vii
Table of Contents
Bus Interface Products
Device Number
VIC068
VAC068
VIC64
CY7C964
Page Number
Description
VMEbus Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-16
VMEbus Interface Controller with D64 Functionality .............................. 11-27
Bus Interface Logic Circuit .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-39
Military Information
Military Overview ........................................................................................
Military Product Selector Guide. . . . ... . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . .
Military Ordering Information ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-2
12-7
Design and Programming Tools
Device Number
CY3101
CY3102
CY3200
CY3210
CY3220
CY3300
Description
13-1
PLD ToolKit ................................................................ .
13-3
WarpI PLD Compiler ........................................................ .
PLDS-MAX + PLUS Design System ............................................. . 13-5
PLS-EDIF Bidirectional Netlist Interface ...................................... . 13-10
MAX +PLUS II Design System ................................................ . 13-17
13-22
QuickPro II ................................................................ .
Quality and Reliability
Quality, Reliability, and Process Flows ...................................................................... .
Tape and Reel Specifications ............................................................................. .
14-1
14-16
Packages
Thermal Management and Component Reliability ............................................................. .
Package Diagrams ....................................................................................... .
Module Package Diagrams ............................................................................... .
Sales Representatives and Distributors
Direct Sales Offices
Nortb American Sales Representatives
International Sales Representatives
Distributors
viii
15-1
15-8
15-61
-=---.,~PRF.SS
..
-=-.,
Numeric Device Index
.
SEMICONDUCTOR
Device Number
Description
10E301
10E302
10E383
1OE422
1OE470
1OE474
1OE484
1OE494
100E301
100E302
100E422
100E470
100E474
100E484
100E494
1OIE383
1OIE484
1OIE494
2147
2148
2149
21L48
21L49
27LS03
27S03
27S07
2901C
2909A
2910A
2911A
3101
3102
3200
3210
3220
3300
3341
6116
6116A
6117A
74S189
7B134
7B135
7B138
7B139
7B144
7B153
7B154
7B161
7B162
7B163
7B164
7B166
7B173
Combinatorial ECL 16P8 Programmable Logic Device ..............................
Combinatorial ECL 16P4 Programmable Logic Device ..............................
ECUITL Translator and High-Speed Bus Driver ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
256 x 4 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4096 x 1 ECL Static RAM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .
1024 x 4 ECLStatic RAM ........ ........ ..................... .... ............
4096 x 4 ECLStatic RAM .....................................................
16,384 x 4 ECL Static RAM ...................................................
Combinatorial ECL 16P8 Programmable Logic Device ..............................
Combinatorial ECL 16P4 Programmable Logic Device ..............................
256 x 4 ECL Static RAM ..... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. . .. .. .. .
4096 x 1 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
1024 x 4 ECLStatic RAM .....................................................
4096 x 4 ECL Static RAM .. .. .. .. .. .. .. .. .. . .. .. .. . . .. . .. .. .. . .. . . .. .. .. .. .. ..
16,384 x 4 ECL Static RAM ...................................................
ECUITL Translator and High-Speed Bus Driver .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4096 x 4 ECLStatic RAM .....................................................
16,384 x 4 ECL Static RAM ...................................................
4096 x 1 Static R/W RAM .. .. .. . .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . ..
1024 x 4 Static R/W RAM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . .
1024x4Static RIWRAM .......................................................
1024 x 4 Static RIW RAM, Low Power. . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . .. . . . . . . . . .
1024 x 4 Static RIW RAM, Low. Power. . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . .. . . .
16 x 4 Static R/W RAM ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 x 4 Static RIW RAM ......... . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . .. . . . . . . .
16 x 4 Static RIW RAM ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS 4-Bit Slice. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Microprogram Sequencers ................................................
CMOS Microprogram Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
CMOS Microprogram Sequencers................................................
PLD ToolKit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wa1pl PLD Compiler .........................................................
PLDS-MAX+PLUS Design System..............................................
PLS- EDIF Bidirectional Netlist Interface .......................................
MAX + PLUS II Design System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . .
QuickPro II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64 x 4 Serial Memory FIFO.. .. .. . .. .. .. .. .. . .. .. . .. .. .. .. .. .. . .. .. . .. .. . .. .. .. ..
2048 x 8 Static RIW RAM .. .. .. . . .. . .. . .. .. .. .. .. .. .. . .. .. .. .. .. . .. .. .. .. .. . .. .
2048 x 8 Static R/W RAM ....... .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. ..
2048 x 8 Static R/W RAM ......................................................
16 x 4 Static RIW RAM .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4Kx 8 Dual-Port Static RAM ..................................................
4Kx8Dual-PortStaticRAM ................................................ ..
4K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY ..................... .
4Kx 8 Dual-Port Static RAM with Semaphores, INT, and BUSY ..................... .
8K x 8 Dual-Port Static RAM with Semaphores, !NT, and BUSY ..................... .
65,536 x 4 Expandable Static RIW RAM ........................................ .
65,536 x 4 Expandable Static RIW RAM ........................................ .
16,384 x 4 Static RAM Separate I/O ............................................ .
16,384 x 4 Static RAM Separate I/O ............................................ .
Expandable 262,144 x 1 Static RIW RAM with Separate I/O ........................ .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static RIW RAM .................................................. .
32,768 x 9 Synchronous Cache RIW RAM ....................................... .
Page Number
ix
10-1
10-6
10-11
10-17
10-24
10-29
10-36
10-43
10-1
10-6
10-17
10-24
10-29
10-36
10-43
10-11
10-36
10-43
2-1
2-6
2-6
2-6
2-6
2-451
2-451
2-451
6-1
6-8
6-12
6-8
13-1
13-3
13-5
13-10
13-17
13 - 22
5-1
2-12
2-19
2-19
2-451
2-104
2-104
2-114
2-114
2-128
2-164
2-164
2-179
2-179
2-202
2-208
2-208
2-285
~~CYPRESS
~, SEMICONDUClDR
Numeric Device Index
Device Number
Description
Page Number
7B174
7B180
7B181
7B185
7B186
7B191
7B192
7B193
7B194
7B195
7B196
7B197
7B199
7B201
7B210
7B211
7B333
7B335
7B336
7B337
7B338
7B339
7B921
7B922
7B923
7B931
7B932
7B933
7B991
7B992
7B1342
7C101
7CI02
7CI06
7C107
7C108
7CI09
7C122
7C123
7C128
7C128A
7C130
7C131
7C132
7C136
7C140
7C141
7C142
7C146
7C147
7C148
7C149
7C150
7C157A
7C158
32,768 x 9 Synchronous Cache RIW RAM . . . . . . . . . . . . . . . . .. . . . . .. .. . . . . . . . . . . . . . . 2-285
4Kx 18 Cache Thg ...........................................................
2-294
4Kx 18 Cache Thg ...........................................................
2-294
8,192 x 8 Static RAM ..................................................... ....
2-328
8,192 x 8 Static RAM . ......... ...................... ............. ....... .....
2-328
65,536 x 4 Static RIW RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 374
65,536 x 4 Static RIW RAM Separate I/O ........................................ 2- 374
262,144xlStaticRlWRAM .................................................. 2-388
65,536 x 4 Static R/W RAM ...................................................
2-394
65,536 x 4 Static RIW RAM with Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 394
65,536 x 4 Static R/W RAM with Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 394
262,144xlStaticR/WRAM .................................................. 2-411
32,768 x 8 Static RIW RAM ...................................................
2-435
128Kx 8 Reprogrammable Power·Down PROM .................................... 3-4
64Kx 16 ReprogrammabJe Power·Down PROM .................................... 3-9
Reprogrammable Registered PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 3-14
General·Purpose Synchronous BiCMOS PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
6·ns BiCMOS PAL with Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-157
7·ns BiCMOS PAL with Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
6·ns BiCMOS PAL with Output Latches ......................................... 4-169
7·ns BiCMOS PAL with Output Latches ......................................... 4-175
HOTLink ltansmitter/Receiver .................................................. 7-1
HOTLink Transmitter/Receiver .................................................. 7-1
HOTLink Transmitter/Receiver .................................................. 7-1
HOTLink Transmitter/Receiver .................................................. 7-1
HOTLink Transmitter/Receiver .................................................. 7-1
HOTLink ltansmitter/Receiver ................................................. . 7-1
Programmable Skew Clock Buffer (PSCB) ........................................ . 7-26
Programmable Skew Clock Buffer (PSCB) ........................................ . 7-26
4Kx 8 Dual·Port Static RAM with Semaphores ................................... . 2-104
262,144 x 4 Static R/W RAM with Separate I/O ................................... . 2-26
262,144 x 4 Static RIW RAM with Separate I/O ................................... . 2-26
262,144 x 4 Static RIW RAM .................................................. . 2-32
1,048,576 x 1 Static RIW RAM ................................................. . 2-38
131,072 x 8 Static R/W RAM .................................................. . 2-44
131,072 x 8 Static RIW RAM .................................................. . 2-44
256 x 4 Static RIW RAM Separate I/O ........................................... . 2-51
256 x 4 Static RIW RAM Separate I/O ........................................... . 2-57
2-63
2048 x 8 Static R/W RAM ..................................................... .
2048 x 8 Static RIW RAM ..................................................... .
2-70
1024 x 8 Dual·Port Static RAM ................................................. . 2-78
1024 x 8 Dual·Port Static RAM ................................................. . 2-78
2048 x 8 Dual·Port Static RAM ................................................. . 2-91
2048 x 8 Dual·Port Static RAM ................................................. . 2-91
1024 x 8 Dual·Port Static RAM ................................................. . 2-78
1024 x 8 Dual·Port Static RAM ................................................. . 2-78
2048 x 8 Dual·Port Static RAM ................................................. . 2-91
2048 x 8 Dual·Port Static RAM ................................................. . 2-91
4096 x 1 Static RAM ........................................................ .
2-142
2-149
1024 x 4 Static RAM ........................................................ .
2-149
1024 x 4 Static RAM ........................................................ .
1024x4StaticRlWRAM .................................................... . 2-156
16,384 x 16 Static RIW Cache Storage Unit ...................................... . 2-171
Self·Timed Pipelined Static RAM .............................................. . 2-177
x
Numeric Device Index
Device Number
Description
Page Number
7C159
7C161
7C161A
7C162
7C162A
7C164
7C164A
7C166
7C166A
7C167
7C167A
7C168
7C168A
7C169
7C169A
7C170
7C170A
7C171
7C171A
7C172
7C172A
7C182
7C183
7C184
7C185
7C185A
7C186
7C186A
7C187
7C187A
7C189
7C190
7C191
7C192
7C194
7C195
7C196
7C197
7C198
7C199
7C225
7C235
7C245
7C245A
7C251
7C254
7C258
7C259
7C261
7C263
7C264
7C265
7C266
7C268
7C269
Self-Timed Pipelined Static RAM .............................................. .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM Separate I/O ....................................... .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM .................................................. .
16,384 x 4 Static R/W RAM with Output Enable .................................. .
16,384 x 4 Static R/W RAM with Output Enable .................................. .
16,384 x 1 Static R/W RAM .................................................. .
16,384 x 1 Static RAM ....................................................... .
4096 x 4 Static RAM ........................................................ .
4096 x 4 R/W RAM ......................................................... .
4096 x 4 Static RAM ........................................................ .
4096 x 4 R/W RAM ......................................................... .
4096 x 4 Static R/W RAM .................................................... .
4096 x 4 Static R/W RAM .................................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
4096 x 4 Static R/W RAM Separate I/O ......................................... .
8,192 x 9 Static R/W RAM ................................................... .
2 x 4096 x 16 Cache RAM .................................................... .
2 x 4096 x 16 Cache RAM .................................................... .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
8,192 x 8 Static R/W RAM ................................................... .
65,536 x 1 Static R/W RAM .................................................. .
65,536 x 1 Static R/W RAM .................................................. .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
65,536 x 4 Static R/W RAM Separate I/O ....................................... .
65,536 x 4 Static R/W RAM .................................................. .
65,536 x 4 Static R/W RAM with Output Enable .................................. .
65,536 x 4 Static R/W RAM with Output Enable .................................. .
262,144 x 1 Static R/W RAM ................................................. .
32,768 x 8 Static R/W RAM .................................................. .
32,768 x 8 Static R/W RAM .................................................. .
512 x 8 Registered PROM ..................................................... .
1024 x 8 Registered PROM .................................................... .
2048 x 8 Reprogrammable Registered PROM ..................................... .
2048 x 8 Reprogrammable Registered PROM ..................................... .
16,384 x 8 Power-Switched and Reprogrammable PROM ........................... .
16,384 x 8 Reprogrammable PROM ............................................. .
2Kx 16 Reprogrammable State Machine PROM .................................. .
2Kx 16 Reprogrammable State Machine PROM .................................
8192 x 8 Power-Switched and Reprogrammable PROM ............................. .
8192 x 8 Reprogrammable PROM .............................................. .
8192 x 8 Reprogrammable PROM .............................................. .
64K Registered PROM ....................................................... .
8192 x 8 Power-Switched and Reprogrammable PROM ............................. .
8192 Registered Diagnostic PROM ............................................. .
8192 Registered Diagnostic PROM ............................................. .
».
xi
2-178
2-185
2-194
2-185
2-194
2-214
2-223
2-214
2-223
2-231
2-238
2-245
2-252
2-245
2-252
2-261
2-266
2-271
2-277
2-271
2-277
2-313
2-320
2-320
2-333
2-342
2-333
2-,:342
2-351
2-360
2-368
2-368
2-380
2-380
2-402
2-402
2-402
2-417
2-425
2-425
3-19
3-26
3-33
3-34
3-42
3-42
3-48
3-48
3-59
3-59
3-59
3-68
3-76
3-83
3-83
Numeric Device Index
Device Number
Description
Page Number
7C270
7C271
7C274
7C272
7C273
7C275
7C276
7C277
7C279
7C281
7C282
7C285
7C286
7C287
7C289
7C291
7C291A
7C292
7C292A
7C293A
7C325
7C330
7C331
7C332
7C340 EPLD Family
7C341
7C342
7C343
7C344
7C345
7C361
7C401
7C402
7C403
7C404
7C408A
7c409A
7C42Q
7t:421
7C424
7C425
7C428
7C429
7C432
7C433
7C439
7C441
7C443
7C451
7C453
7C460
7C462
7C464
7C470
7C472
16Kx 16 Processor-Specific PROM ............................................. . 3-96
32,768 x 8 Power Switched and Reprogrammable PROM ........................... . 3-106
32,768 x 8 Reprogrammable PROM ............................................ . 3-106
16Kx 16 Reprogrammable Registered PROM ................................... . 3-114
16K x 16 Power-Switched and Reprogrammable PROM ............................ . 3-121
16Kx 16 Reprogrammable Registered PROM ................................... . 3-126
16K x 16 Reprogrammable PROM ............................................. . 3-133
32,768 x 8 Reprogrammable Registered PROM .................................. . 3-138
32,768 x 8 Reprogrammable Registered PROM .................................. . 3-138
3-147
1024 x 8 PROM ............................................................ .
1024 x 8 PROM ............................................................ .
3-147
65,536 x 8 Reprogrammable Fast Column Access PROM ........................... . 3-153
65,536 x 8 Reprogrammable Registered PROM .................................. . 3-162
65,536 x 8 Reprogrammable Registered PROM .................................. . 3-162
65,536 x 8 Reprogrammable Fast Column Access PROM ........................... . 3-153
2048 x 8 Reprogrammable PROM ............................................. . 3-169
2048 x 8 Reprogrammable PROM ............................................. . 3-170
2048 x 8 Reprogrammable PROM ............................................. . 3-169
2048 x 8 Reprogrammable PROM ............................................. . 3-170
2048 x 8 Reprogrammable PROM ............................................. . 3-170
4-95
Timing Control Unit ......................................................... .
CMOS Programmable Synchronous State Machine ................................ . 4-102
Asynchronous Registered EPLD .............................................. . 4-113
Registered Combinatorial EPLD .............................................. . 4-126
Multiple Array Matrix High-Density EPLDs ..................................... . 4-181
192-Macrocell MAX EPLD .................................................. . 4-190
128-Macrocell MAX EPLD .................................................. . 4-201
4-214
64-Macrocell MAX EPLD ................................................... .
4-225
32-Macrocell MAX EPLD ................................................... .
4-201
128-Macrocell MAX EPLD .................................................. .
Ultra High Speed State Machine EPLD ......................................... . 4-235
5-6
64 x 4 Cascadeable FIFO ....................................................... .
5-6
64 x 5 Cascadeable FIFO ....................................................... .
64 x 4 Cascadeable FIFO with Output Enable ...................................... . 5-6
64 x 5 Cascadeable FIFO with Output Enable ...................................... . 5-6
5-16
64 x 8 Cascadeable FIFO ...................................................... .
5-16
64 x 9 Cascadeable FIFO ...................................................... .
5-30
512 x 9 Cascadeable FIFO ..................................................... .
5-30
512 x 9 Cascadeable FIFO ..................................................... .
1024 x 9 Cascadeable FIFO .................................................... . 5-30
1024 x 9 Cascadeable FIFO .................................................... .
5-30
5-30
2048 x 9 Cascadeable FIFO .................................................... .
5-30
2048 x 9 Cascadeable FIFO .................................................... .
5-45
4096 x 9 Cascadeable FIFO .................................................... .
5-45
4096 x 9 Cascadeable FIFO .................................................... .
2048 x 9 Bidirectional FIFO ................................................... . 5-58
512 x 9 Synchronous FIFO .................................................... . 5-71
5-71
2K x 9 Synchronous FIFO ..................................................... .
512 x 9 Cascadeable Clocked FIFO ............................................. . 5-84
2K x 9 Cascadeable Clocked FIFO .............................................. . 5-84
8Kx 9 Cascadeable FIFO .................................................... . 5-105
16Kx 9 Cascadeable FIFO ................................................... . 5-105
32K x 9 Cascadeable FIFO ................................................... . 5-105
8Kx9FIFO ............................................................... .
5-117
16Kx9FIFO .............................................................. .
5-117
xii
-=~~
=
= CYPRESS
- _ : SEMICONJ)UC'TOR
Numeric Device Index
Device Number
Description
7C474
7C51O
7C516
7C517
7C601A
7C602A
7C604A
7C605A
7C611A
7C613
7C614
7C615
7C616
7C617
7C618
7C901
7C909
7C91O
7C911
7C964
7C1001
7ClO02
7CI006
7ClO07
7C1009
7C9101
7C9115
7C9116
7C9117
7M194
7M199
93422
93422A
93L422
93L422A
M1240
M1420
M1422
M1423
M1441
M1460
M1461
M1464
M1465
M1466
M1471
M1481
M1540
M1560
M1610
M1611
M1620
M1621
M1622
M1624
32Kx9 FIFO .............................. _.......... _.................... .
16 x 16 Multiplier Accumulator ........... _..................................... .
16x 16 Multipliers ................. _... _... _................................. .
16 x 16 Multipliers ...................................................... _.... .
32-Bit RISC Processor ................. _................................... _... .
Floating-Point Unit .......................................................... .
Cache Controller and Memory Management Unit ................................. .
Cache Controller and Memory Management Unit ........................ _...... _..
32-Bit RISC Controller ................ _.................... _................. .
MBus Memory Controller ............................. _......... _. _........... .
MBus Peripheral I/O Controller .......... _...................... _............. __
Interrupt Controller ......................................... _................ .
MBus-to-SBus Interface Controller ... _.. _........................ _........... _..
MBus-to-Video Graphics Controller .............................. _............. .
SBus Controller ............................................................. .
CMOS 4-Bit Slice .................................................. __ ........ .
CMOS Microprogram Sequencers ................................ _............. .
CMOS Microprogram Controller ............................................... _
CMOS Microprogram Sequencers ................................ _............. .
Bus Interface Logic Circuit .............. _.............. _........... _......... .
256K x 4 Static R!W RAM with Separate I/O .. _............. _...... _.. _......... .
256K x 4 Static R!W RAM with Separate I/O .......................... _......... _
256K x 4 Static R!W RAM ............................. _.......... _......... _. _
1M x 1 Static R/W RAM ..................................................... .
128Kx 8 Static R/W RAM .................... _.................. _............ .
CMOS 16-Bit Slice .. _............. _... _... _............................. _.... .
CMOS 16-Bit Microprogrammed ALU ..... _. _.................................. .
CMOS 16-Bit Microprogrammed ALU ... _. _.................................... .
CMOS 16-Bit Microprogrammed ALU .................. _....................... .
64K x 4 Static RAM Module ............. _..................... _.............. .
32K x 8 Static RAM Module .......... _..... _....................... _... _..... .
256 x 4 Static R/W RAM ......... _..................................... _..... .
256 x 4 Static R!W RAM _. _...... _...... _........................ _........... .
256 x 4 Static R!W RAM _. _...... _...... _................... __ ............... .
256 x 4 Static R/W RAM ................ _............ _...... _................ .
256K x 4 Static RAM Module .................................................. _.
128K x 8 Static RAM Module ......... _............................. _.......... _.
128K x 8 Static RAM Module ...................................... _... _....... _
128K x 8 Static RAM Module .................................... _............. .
256K x 8 Static RAM Module .................................................. .
512Kx 8 Static RAM Module .................................... _....... _.... _.
512K x 8 Static RAM Module ........................... _.... _... _....... _.... _.
512K x 8 Static RAM Module ........................... _........ _....... _..... .
512Kx 8 Static RAM Module ........................... _........ _....... _.... _.
512Kx 8 Static RAM Module ................................. _.. __ ......... _. _.
1024Kx 8 Static RAM Module ................................... _............ __
2048K x 8 Static RAM Module ............................................ _.... _
256K x 9 Buffered Static RAM Module with Separate I/O ........................... .
1024K x 9 Buffered Static RAM Module with Separate I/O .......................... .
16K x 16 Static RAM Module ........................................... _...... .
16K x 16 Static RAM Module ... _......................... _............. _...... .
64Kx 16 Static RAM Module ........................ _. _....................... .
64Kx 16 Static RAM Module ...................... _........................... .
64Kx 16 Static RAM Module .................................................. .
64K x 16 Static RAM Module .................................... _............. .
Page Number
xiii
5-117
6-17
6-27
6-27
8-6
8-14
8-20
8-29
8-39
8-46
8-47
8-48
8-49
8-50
8-51
6-38
6-52
6-62
6-52
11-39
2-441
2-441
2-442
2-443
2-444
6-73
6-90
6-90
6-90
2-445
2-446
2-456
2-456
2-456
2-456
9-5
9-6
9-11
9-16
9-17
9-18
9-23
9-29
9-35
9-40
9-47
9-47
9-53
9-58
9-63
9-64
9-70
9-75
9-76
9-81
~~
Numeric Device Index
~=CYPRESS
- , SEMICONDUCTOR
Device Number
Description
M1641
M1720
M1730
M1821
M1822
M1828
M1830
M1831
M1832
M1836
M1838
M1840
M1841
M1910
M1911
M4210
M4220
M4241
M6001K
M6002K
M6003K
M7232
M7264
PA120 Series
PALC20 Series
PAL22VlOC
PAL22VlOD
PA122VP10C
PALC20GlO
PALC20GlOB
PALC20GlOC
PALC22VlO
PALC22VlOB
PLD610
PLDC18G8
PLDC20RA10
VAC068
VIC068
VIC64
256Kx 16 Static RAM Module.................................................. 9-86
32K x 24 Static RAM Module ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-91
64Kx 24 Static RAM Module................................................... 9-96
16Kx32 Static RAM Module .................................................. 9-101
16Kx 32 Static RAM Module with Separate I/O ....................... . . . . . . . . . . . . 9-108
32Kx 32 Static RAM Module .................................................. 9-115
64Kx 32 Static RAM Module.................................................. 9-121
64Kx 32 Static RAM Module. . .. .. . . . . . . .. . . . . . . . . .. .. .. . . . . .. . . . . .. . . . . . . . . . . 9-126
64Kx 32 Static RAM Module. . . . . . . . . . . . .. . . . . . . . . .. . . .. .. . . .. . . . . .. . . .. . . . . . . 9-131
128Kx32 Static RAM Module ...... .......... ................................. 9-136
128Kx32 Static RAM Module................................................. 9-141
256K X 32 Static RAM Module ................................................ 9-146
256Kx32 Static RAM Module ...... ............................... ............ 9-152
16Kx 68 Static RAM Module. . .. .. . . . . . . .. . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . 9-158
16Kx 68 Static RAM Module. . .. . . . . . . . . .. . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . 9-159
Cascadeable 8K x 9 FIFO .....................................................
9-160
Cascadeable16Kx9FIFO ....................................................
9-160
64K x 9 FIFO ...............................................................
9-169
SPARCore CPU Module .......................................................
8-52
SPARCore Dual-CPU Module .................................................. 8-58
SPARCore CPU Module for Multiprocessing ...................................... 8-65
DRAMControlierModule ................... ....................... .......... 9-175
DRAM Controller Module .................................................... 9-175
5-ns, Industry-Standard, 20-Pin PLDs . . . . . . . . . . . . . . . . . . .. .. . . . . . . .. . . . . . .. . . . . . . . . 4-28
Reprogrammable CMOS PAL C 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
UniversaiPALDevice .........................................................
4-77
Flash Erasable, Reprogrammable CMOS PAL Device ............................... 4-88
Universal PAL Device .........................................................
4-77
CMOS Generic 24-Pin Reprogrammable Logic Device .............................. 4-29
CMOS Generic 24-Pin Reprogrammable Logic Device .............................. 4-29
Generic 24-Pin PAL Device. . . . . . . . . . . . . . . . . .. . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . .. . . 4-37
Reprogrammable CMOS PAL Device ............................................ 4-57
Reprogrammable CMOS PAL Device ............................................ 4-67
Multipurpose BiCMOS PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
CMOS Generic 20-Pin Programmable Logic Device. .. .. .. . . . . . . . . . . . . . . . . .. . . . . . .. .. 4-6
Reprogrammable Asynchronous CMOS Logic Device ............................... 4-47
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
VMEbus Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
VMEbus Interface Controller with D64 Functionality .............................. 11-27
Page Number
xiv
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INFO
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SRAMs~~~~~~~~~~~~~
Rise ~~~~~~~~~~~~~~i:1
MODULES
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......:=.
:~PRESS
F
SEMICONDUC'TOR
General Product Information
Section Contents
Page Number
Cypress Semiconductor Background and Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cypress Semiconductor Bulletin Board System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
Application Notes Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-3
1-5
1-6
1-8
1-15
o
u..
Z
===--.
.~
~li!
~,
CYPRESS
SEMICONDUCTOR
Cypress Semiconductor Background
compiler, called WARP1, to provide high-level design support of
the worlds fastest state machine PLD, the 125-MHz CY7C361.
Cypress Semiconductor was founded in April 1983 with the stated
goal of serving the high-performance semiconductor market. This
market is served by producing the highest-performance integrated
circuits using state-of-the-art processes and circuit design. Cypress
is a complete semiconductor manufacturer, performing its own
process development, circuit design, wafer fabrication, assembly,
and test. The company went public in May 1986 and was listed on
the New York Stock Exchange in October 1988.
The initial semiconductor process, a CMOS process employing
1.2-micron geometries, was introduced in March 1984. This process is used in the manufacturing of Static RAMs and Logic circuits. In the third quarter of 1984, a 1.2-micron CMOS EPROM
process was introduced for the production of programmable products. At the time of introduction, these processes were the most
advanced production processes in the industry. Following the
1.2-micron processes, a D.8-micron CMOS SRAM process was implemented in the first quarter of 1986, and a O.8-micron EPROM
process in the third quarter of 1987. To stay at the forefront of process technology, Cypress's I-megabit SRAM is manufactured using its proprietary O.65-micron CMOS process.
In keeping with the strategy of serving the high-performance markets with state-of-the-art integrated circuits, Cypress introduced
two new processes in 1989. These were a bipolar submicron process, targeted for ECL circuits, and a BiCMOS process to be used
for most types of TTL and ECL circuits.
Logic products include circuits such as 4-bit and 16-bit slices, 16 x
16 multipliers and 16-bit microprogrammable ALUs, a family of
lK/2Kx 8 and 4K/8K x 8 dual-port SRAMS, as well as a family of
FIFOs that range from 64 x 4 to 32K x 9. Cypress also offers application-specific Fl FOs such as the 2K x 9 bidirectional FIFO and
the 512/2K x 9 clocked FIFO. FIFOs provide the interface between digital information paths of widely varying speeds. This allows the information source to operate at its own intrinsic speed,
while the results may be processed or distributed at a speed commensurate with nced.
Cypress's Datacom group has developed a family of 300-MHz
point-to-point transmitter/receivers. HOTLink@l is compliant
with the IBM ESCON@l and Fibre Channel computer network
standards, and will also have applications in military, graphics, and
instrumentation systems. The Datacom group is also responsible
for the Programmahle Skew Clock Buffer, which allows designers
to compensate for trace delays and load capacitance in high performance systems.
As a result of the acquisition of VTC's manufacturing facility in
Minnesota, Cypress has created a VME Bus Interface Products
group. Cypress will continue to manufacture VTC's VIC and VAC
VME devices on the 0.8-micron CMOS process.
Until 1988, all Cypress products were TTL I/O-compatible. In
1989, Cypress introduced ECL products having access times
(propagation delays) of less than 3.5 ns in either of the popular I/O
configurations, lOOK or lOK/lOKH. ECL RAMs include 256 x 4,
lKx4,4Kx4, and l6Kx4RAMfamilieswithbalancedreadlwrite
cycles. The ECL PLOs are combinatorial 16P8 and 16P4 devices
that can be programmed on QuickPro and other commercially
available programming tools. Both the RAMs and PLDs are offered in low-power versions, reducing operating power by 30 percent while achieving 5-ns access times (RAM) and 4-ns tpD (PLD).
The circuit design technology used by Cypress is also state of the
art. This design technology, along with advanced process technology, allows Cypress to introduce the fastest, highest-performance
circuits in the industry. Cypress's products fall into seven families:
high-speed Static RAMs, PROMS, Programmable Logic Devices,
Logic, RISC microprocessors, ECL SRAMs and Pills, and module products. Members of the CMOS Static RAM family include
devices in densities of 64 bits to 1 megabit, and performance from
7 ns to 35 ns. The various organizations, 16 x 4, 256 x 4 through 1
Mbit x 1, 256K x 4, and 128K x 8 provide optimal solutions for
applications such as large mainframes, high-speed controllers,
communications, and graphics display. Cypress's BiCMOS family
of 64K and 256K SRAMs in 16K x 4 and 32K x 8 configurations
offers speeds as fast as 8 ns. Cypress's cache RAMs include a 4Kx
18 cache tag RAM at 12 ns match, a 32K x 9 cache RAM with a
14-ns access time, and an 8Kx 16 cache RAM with a 25-ns access
time.
The module family consists of both standard and custom modules
incorporating circuits from the other six product families. This capability provides a fast, low-risk solution for designs requiring the
ultimate in system performance and density. SRAM and FIFO
module configurations are available depending on height and
board real estate constraints. Modules include Single-In-Line,
Dual-In-Line, Dual Single-in-line, Vertical Dual-In-Line, QuadIn-Line, and (Staggered) Zig-Zag-In-Line packages.
Cypress's CY7C600 family of RISC microprocessor products provides state-of-the-art high-performance computing for applications ranging from UNIX-based business computers and workstations to embeddcd controls. Based on the SPARC® RISC
architecture, the family provides a complete solution with Integer
Unit (IV), Floating-Point Unit (FPU), Cache Control and
Memory Management Unit (CMU), and Cache RAMs (CRAMs).
The family is functionally partitioned to provide a range of fea;
lures, performance, and price to suit each type of application. It
has also been expanded to provide full CPU modules for both
single-processor and multiprocessor applications. Additional
products have been developed that provide support for peripheral
devices in order to simplify workstation design.
Cypress's programmable products consist of high-speed CMOS
PROMs employing an EPROM programming element and Programmable Logic Devices (PLDs) based on CMOS EPROM,
CMOS FLASH, and BiCMOS Fuse technology. Like the highspeed Static RAM family, these products are the natural choice to
replace older devices because they provide superior performance
at one half of the power consumption. PROM densities range
from 4kilobits to 1 Mbit in byte-wide and x 16 organizations. PLD
products range from 20 pins to 84 pins with performance as fast as
5-ns propagation delay and 156-MHz operational frequency. To
support new programmable products, Cypress introduced the
QuickPro@l programming system (CY3000) for PLDs and
PROMs, and the PLD ToolKit for Pills. QuickPro is a development tool that includes a single, IBM PC® compatible add-on
board and a software utility program. The PLD ToolKit is a software design tool that assembles and simulates logic functions, generates JEDEC files, and reverse assembles to create source files.
Both QuickPro and the PLD ToolKit software are updated via
floppy disk, thereby allowing quick support of all Cypress programmable products. Cypress has also introduced a VHDL-based
Situated in California's Silicon Valley (San Jose), Round Rock
(Austin), Texas, and Bloomington, Minnesota, Cypress houses
R&D, design, wafer fabrication, assembly, and administration.
The facilities are designed to the most demanding technical and
environmental specifications in the industry. At the Texas and
Minnesota facilities, the entire wafer fabrication area is specified
to be a Class 1 environment. This means that the ambient air has
less than 1 particle of greater than 0.2 microns in diameter per cu-
1-1
~APRFSS
~...
SEMICaIDUCTOR
bic foot of air. Other environmental considerations are carefully
insured: temperature is controlled to a :to.1 degree Fahrenheit
tolerance; filtered air is completely exchanged more than 10 times
each minute throughout the fab; and critical equipment is situated
on isolated slabs to minimize vibration.
Attention to assembly is equally as critical. Cypress assembles
80% of its packages in the United States at its San Jose, California
plant. Assembly is completed in a clean room until the silicon die
is sealed in a package. Lead frames are handled in carriers or cassettes through the entire operation. Automated robots remove
and replace parts into cassettes. Using sophisticated automated
equipment, parts are assembled and tested in less than five days.
The Cypress assembly line is the most flexible, automated line in
the United States. It has also been expanded to provide full CPU
modules for both single- and multiprocessor applications. Additional products have been developed which provide support for
peripheral devices in order to simplify workstation design.
Cypress has added Thpe Automated Bonding (TAB) to it package
offering. TAB, a surface-mount packaging technology, provides
the densest lead and package footprint available for fully tested
die.
As a result of the acqnisition of VTC's manufacturing facility in
Minnesota, Cypress has created a VME Bus Intedace Products
group. Cypress will continue to manufacture VTC's VIC and
VAC VME devices on the 0.8 micron CMOS process.
The Cypress motto has always been "only the best-the best facilities, the best equipment, the best employees ... aU striving to make
the best CMOS, BiCMOS, and bipolar products.
Cypress Process Technology
In the last decade, there has been a tremendous need for high-performance semiconductor products manufactured with a balance
of SPEED, RELIABILITY, and POWER. Cypress Semiconductor has overcome the classically held perceptions that CMOS is a
moderate-pedormance technology.
Cypress initially introduced a 1.2-micron "N" well technology with
double-layer poly and a single-layer metal. The process employs
lightly doped extensions of the heavily doped source and drain regions for both "N" and "P" channel transistors for significant improvement in gate delays. Further improvements in performance,
through the use of substrate bias techniques, have added the benefit of eliminating the input and output latch-up characteristics associated with the older CMOS technologies.
Cypress pushed process development to new limits in the areas of
PROMs (Programmable Read Only Memory) and EPLDs (Eraseable Programmable Logic Devices). Both PROMs and EPLDs
have existed since the early 1970s in a bipolar process that
employed various fuse technologies and was the only viable highspeed nonvolatile process available. Cypress PROMs and EPLDs
use EPROM technology, which has also been in use in MOS (Metal Oxide Silicon) also since the early 1970s. EPROM technology
has traditionally emphasized density advantages while forsaking
pedormance. Through improved technology, Cypress has produced the first high-pedormance CMOS PROMs and EPLDs, replacing their bipolar counterparts.
To maintain our leadership position in CMOS technology, Cypress has introduced a sub-micron technology into production.
This 0.8 micron breakthrough makes Cypress's CMOS one of the
most advanced production processes in the world. The drive to
maintain leadership in process technology has not stopped with
the 0.8-micron devices. Cypress will bring a 0.65-micron process to
production in 1991 with the introduction of its I-megabyte
SRAM.
Th further enhance the technology from the reliability direction,
improvements have been incorporated in the process and design,
minimizing electrostatic discharge and input signal clipping problems.
Finally, although not a requirement in the high-pedormance arena, CMOS technology substantially reduces the power consumption for any device. This improves reliability by aUowing the device
to operate at a lower die temperature. Now higher levels of integration are possible without trading pedormance for power. For
instance, devices may now be delivered in plastic packages without
any impact on reliability.
While addressing the pedormance issues of CMOS technology,
Cypress has not ignored the quality and reliability aspects of technology development. Rather, the traditional failure mechanisms
of electrostatic discharge (ESD) and latch-up have been addressed and solved through process and design technology innovation.
ESD-induced failure has been a generic problem for many highperformance MOS and bipolar products. Although in its earliest
years, MOS technology experienced oxide reliability failures, this
problem has largely been eliminated through improved oxide
growth techniques and a better understanding of the ESD problem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits.
Focusing on these constraints, Cypress has developed ESD protection circuitry specific to 1.2- and 0.8-micron CMOS process
technology. Cypress products are designed to withstand voltage
and energy levels in excess of 2001 volts and 0.4 mi1li-joules.
Latch-up, a traditional problem with CMOS technologies, has
been eliminated through the use of substrate bias generation techniques, the elimination of the "P" MOS pull-ups in the output
drivers, the use of guardring structures and care in the physical layout of the products.
Cypress has also developed additional process innovations and enhancements: the use of multilayer metal interconnections, advanced metal deposition techniques, silicides, exclusive use of
plasma for etching and ashing process steps, and 100 percent stepper technology with the world's most advanced eqnipment.
A wholly owned subsidi.ary of Cypress, Aspen Semiconductor, has
developed a BiCMOS technology to augment the capabilities of
the Cypress CMOS processes. The new BiCMOS technology is
based on the Cypress 0.8-micron CMOS process for enhanced
manufacturability. like CMOS, the process is scalable, to take advantage of finer line lithography. Where speed is critical, Cypress
BiCMOS aUows increased transistor pedormance. It also allows
reduced power in the non-speed critical sections of the design to
optimize the speed/power balance. The BiCMOS process makes
memories and logic operating up to 400 MHz possible.
Cypress technologies have been carefully designed, creating products that are "only the best" in high-speed, excellent reliability,
and low power.
mM PC and mM ESCON are registered trademarks of International Business Corporation.
QuickPro and HOTLink are trademarks of Cypress Semiconductor Corporation.
SPARC is a registered trademark of SPARC International, Inc.
1-2
Ordering Information
In general, the codes for all products (except modules and VMEbus products) follow the format below.
PAL&PLD
PREFIX DEVICE
IpALC I ~
16R8
PALC
22VlO
PALC
20GlO
PLDC
7C330
CY
10E302
CY
CY
100E302
I -25
L-35
-25
-25
-33
-2.5
-2.5
o
II..
FAMILY
SUFFIX
P C I
P C
W C
WC
P C
D C
D C
Z
PAL 20
LOW POWER PAL 20
PAL 24 VARIABLE PRODUCT TERMS
GENERIC PLD 24
Pill SYNCHRONOUS STATE MACHINE
10K ECL PLD
l00KECLPLD
RAM, PROM, FIFO, !-IP, ECL
PREFIX
DEVICE
rcy-J
I 7C128 I I
CY
CY
CY
CY
CY
r7B185
7C245
7C404
7C901
10E415
100E415
B = BiCMOS
C = CMOS
SUFFIX
FAMILY
-45DMB I
-15V C
L-35P C
-25DMB
-23P C
-3 DC
-3 F C
L
CMOSSRAM
BiCMOSSRAM
PROM
FIFO
rtKECLSRAM
lOOK ECL SRAM
PROCESSING
B = MIL-STD-883C FOR MILITARY PRODUCT
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCT
T = SURFACE-MOUNTED DEVICES (V & S PACKAGE) TO
BE TAPE AND REELED
R = LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIAL (O°CTO +70°C)
I = INDUSTRIAL (-40°C TO +85°C)
M= MILlTARY(-55°CTO +125°C)
PACKAGE
B =
D =
E =
F =
G =
H =
J =
K =
L =
N =
P =
Q =
R =
S =
T =
U =
V =
W=
X =
Y =
PLASTIC PIN GRID ARRAY (PPGA)
CERAMIC DUAL IN-LINE PACKAGE (CERDIP)IBRAZED DIP
TAPE AUTOMATED BONDING (TAB)
FLATPACK(SOillER-SEALRD FtATPACKAGE)
PIN GRID ARRAY (pGA)
WINDOWED LEADED CHIP CARRIER
PLASTIC LEADED CHIP CARRIER (PLCC)
CERPACK (GLASS-SEALED PI AT PACKAGE)
LEADLESS CHIP CARRIER (LeC)
PLASTIC QUAD FLATPACK (PQFi')
PLASTIC DUAL IN-LINE (PDIP)
WINDOWED LEADLESS CllIP CARRIER (LeC)
WINDOWED PIN GRID ARRAY (PGA)
SOIC (GULL WING)
WINDOWED CERPACK
CERAMIC QUAD FLATPACK (CQFP)
SOlC(JLEAD)
WINDOWED CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
DICE (WAFFLE PACK)
CERAMIC LEADED CHIP CARRIER
SPEED (ns or MHz)
L = WW-POWER OPTION
A, B, C = REVISION LEVEL
e.g., CY7C128-35PC, PALC16R8L-25PC
Cypress FSCM #65786
1-3
~~
Ordering Information
~"'CYPRESS
~, SEMICONDUCTOR
The codes for module and VMEbus products follow the the formats below.
Modules
PREFIX
DEVICE
I CYM I
rwiji""ll L HD-120MB 1
6001
K -40
CYM
SUFFIX
PROCESSING
il
~ MIL-STD-883C
~
STANDARD
TEMPERATURE RANGE
~
~
M~
C
I
O'CTO +70'C
-40'C TO +85'C
-55'CTO +125'C
SPEED
CONFIGURATION
D ~
F ~
G ~
J ~
M~
N ~
Q ~
S ~
V ~
Z ~
DUAL-IN-LINE
FLAT SINGLE-IN-LINE
PIN GRID ARRAY
PLASTIC LEADED CHIP CARRIER (PLCq
SINGLE-IN-LINE MEMORY MODULE (SIMM)
SIMM FOR ANGLED SOCKETS
QUAD-IN-LINE
SINGLE-IN-LINE
VERTICAL DIP
ZIGZAG-IN-LINE
TYPE
H
K
P
S
~
~
~
~
HERMETIC
3.30" X 5.78" FORM FACTOR
PLASTIC
PLASTIC ON CERAMIC
DATA RETENTION
L
~
~
2.0V DATA RETENTION GUARANTEED
STANDARD
VMEbus Products
PREFIX
rviC1
DEVICE SUFFIX
I 068A I I BCB I
t
PROCESSING
B
~
~
MIL-STD-883C
STANDARD
TEMPERATURE RANGE
~
~
M~
C
I
O'CTO +70'C
-40'C TO +85'C
-55'CTO +125'C
PACKAGE
B
G
N
U
PLASTIC PIN GRID ARRAY (PPGA)
PIN GRID ARRAY (pGA)
PLASTIC QUAD FLATPACK (PQFP)
CERAMIC QUAD FLATPACK (CQFP)
Cypress FSCM #65786
1-4
~
~-::z
~.CYPRESS
_ , SEMICONDUC'TOR
Cypress Semiconductor
Bulletin Board System (BBS)
Announcement
Version 1.1
Cypress Semiconductor supports a 24-hour electronic Bulletin Board System (BBS) that allows Cypress
Applications to better serve our customers by allowing them to transfer files to and from the BBS.
The BBS is set up to serve in multiple ways. One of its purposes is to allow customers to receive the most
recent versions of the QuickPro programming software. Another is to allow the customers to send PLD programming files that they are having trouble with to the BBS. Cypress Applications can then find the errors
in the files, correct them, and place them back on the BBS for the customer to download. The customer may
also ask questions in our open forum message area. The sysop (system operator) will forward these questions
to the appropriate applications engineer for an answer. The answers then get posted back into the forum.
The BBS also allows the customer to communicate with their local FAE electronically.
Communications Set-Up
The BBS is attached to a US Robotics HST Dual Standard modem capable of 14.4-Kbaud rates without compression and rates upwards of 19.2-Kbaud with compression. It is compatible with CCITT Y.32 bis, Y.32, Y.22
(2400-baud), Bell 212A (1200-baud), CCITT Y.42, and CCITT Y.42 bis. It also handles MNP levels 2, 3, 4,
and 5.
Th call the BBS, set your communication package parameters as follows:
Baud Rate:
1200 baud to 19.2 Kbaud. Max. is determined by your modem.
Data Bits: 8
Parity: None (N)
Stop Bits: 1
The phone number for the BBS is (408) 943-2954 (data).
If you have any problems or questions regarding the BBS, please contact Cypress Applications at (408)
943-2821 (voice).
There is also a Japan BBS whose number is 81-423-69-8220.
1-5
~::~~
-=:?
Application Notes
SEMICONDUCTOR
Contact a Cypress representative to receive copies of the application notes listed here.
General Information
PLDs
System Design Considerations When Using Cypress CMOS
Circuits
CMOS PAL Basics
Power Characteristics of Cypress Products
Are Your PLDs Metastable?
Introduction to Programmable Logic
Tips for High-Speed Logic Design
PLD-Based Data Path For SCSI-2
Protection, Decoupling, and Filtering of Cypress CMOS Circuits
PAL Design Example: A GCR EncoderlDecoder
Modules
T2 Framing Circuitry
Choosing Packages in High-Density Module Designs
Using CUPL with Cypress PLDs
The Multichip Family of Universal JEDEC ZIP/SIMM Modules
Using ABEL to Program the Cypress 22V10
EeL and TTL BieMOS
Using ABEL to Program the CY7C330
Using ABEL 3.2 to Program the Cypress CY7C331
Noise Considerations in High-Speed Logic Systems
Using LoglIC to Program the CY7C330
Using ECL in Single +5V TIL Systems
State Machine Design Considerations and Methodologies
BiCMOS TIL and ECL SRAMs Improve High-Performance
Systems
Understanding the CY7C330 Synchronous EPLD
PLCC and CLCC Packaging for High-Speed Parts
Using the CY7C330 in Closed-Loop Servo Control
A New Generation of BiCMOS High-Speed TIL SRAMs
FDDI Physical Connection Management Using the CY7C330
Access Time vs. Load Capacitance for High-Speed BiCMOS TTL
SRAMs
Bus-Oriented Maskable Interrupt Controller
Using the CY7C330 as a Multichannel Mbus Arbiter
Memory and Support Logic for Next-Generation ECL Systems
Using the CY7C331 as a Waveform Generator
SRAMs
CY7C331 Application Example: Asynchronous, Self-Timed
VMEbus Requestor
Cypress IC I/O Characteristics
Understanding Dual-Port RAMs
Using Dual-Port RAMs Without Arbitration
Using Cypress SRAMs to Implement 386 Cache
Combining SRAMs Without an External Decoder
BiCMOS TIL SRAMs Improve MIPS R3000 and R3000A
Systems
Implementing Coherent Caches Using the CY7C180/181
PROMs
Pinout Compatibility Considerations of SRAMs and PROMs
Introduction to Diagnostic PROMs
Interfacing the CY7C289 to the AM29000
Understanding the CY7C361
Using the CY7C361 as an MBus Arbiter
TMS320C30/VME Signal Conditioner Using the CY7C361
DMA Control Using the CY7C342 MAX EPLD
Interfacing PROMs and RAMs to High-Speed DSP Using MAX
FIFO RAM Controller with Programmable Flags
Design Tips for Advanced MAX Users
One Hot State Encoding Using the CY7C344 MAX PLD
Event Generator Implemented in the CY7C361 PLD
Using the CY7C332 as a Mealy State Machine: A Priority
Encoder Example
Interfacing the CY7C289 to the CY7C601
Dual-Ported Memory Design Using Standard SRAMs and the
CY7C361PLD
Generating PROM Code Using C, Basic, and ABEL
Multiprocessor Interrupt Distribution Unit Using MAX
State Machine PROM Design Examples
Combinatorial Cross Bar Switch Implemented in MAX (written
in French)
Using PLD TholKit with the CY7C361
Designing Counters with the CY7C361 EPLD
Using PLD ToolKit with the CY7C361
CY7C361 Arbiter with Fairness and Priority Modes
Designing Counters with the CY7C361 EPLD
CY7C361 Arbiter with Fairness and Priority Modes
1-6
Application Notes
Logic
Synchronous Trap Identification for CY7C600 Systems
Understanding Small FIFOs
An Introduction to MBus
Understanding Large FlFOs
MUltiprocessing System Boot-Up
Designing with the CY7C439 Bidirectional FIFO (BIFO)
Porting UNIX to the CY7C604 or CY7C605
Microcoded System Performance
Getting Started with Real-Time Embedded System Development
Systems with CMOS 16-Bit Microprocessor ALUs
SPARC as a Real-Time Controller
System Architectures Using the CY7C439 Bidirectional FIFO
Memory Protection and Address Exception Logic for the
CY7C611 SPARC Controller
RIse
SPARC Software Advantages Over CISC
Using the CY7C611 for High-Performance Embedded
Applications
Register Windows
Discrete Cache System Design for the CY7C611 Processor
CY7C600 System Design Footnotes
Interfacing to the Mezzanine Bus: Emerging Standards for RISC
Processor Buses
The Impact of Memory on High-Performance RISC
Microprocessors
High-Speed CMOS SPARC Design
SPARC System Surface-Mount Design
Memory System Design for the CY7C601 SPARC Processor
Cache Memory Design
Bus Products
VIC068 Special Features and Tips
Interfacing the VIC068 to MC68020
Interfacing the 68040 Processor to VIC068A
Interfacing the t800 'fransputer to VIC068A Using the CY7C361
1-7
o
LL
Z
~---..
--
Product Selector Guide
• :_..ib.
CYPRESS
----6/1
~F
SEMICONDUCTOR
Static RAMs
Size
Organization
Pins
PartNumber
Speed (ns)
(mA@ns)
ICcJISB
Packages
Availability
64
64
64
64
64
64
1K
1K
lK
lK
4K
4K
4K
4K
4K
4K
4K
8K
8K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
32K
32K
32K
32K
32K
64K
64K
64K
64K
64K
16 x 4-Inverting
16 x 4-Non-Inverting
16 x 4-Inverting
16x4-Inverting
16 x4-Non-Inverting
16 x 4-Inverting Low Power
256x4
256x4
256x4
256x4
4Kx l-CS Power-Down
4Kx l-CS Power-Down
lKx4-CS Power-Down
lKx 4-CS Power-Down
lKx4
lKx4
lKx 4-Separate I/O, Reset
lKx8-DualPort Master
lKx8-Dual Port Slave
lKx8-DualPort Master
IKx8-Dual Port Slave
2Kx8--CS Power-Down
2Kx8-CSPower-Down
2Kx8-CS Power-Down
16K x 1-CS Power-Down
4Kx4-CS Power-Down
4Kx4
4Kx4-0utputEnable
4K x 4-Separate I/O
4Kx4-Separate I/O
2Kx8-DualPortMaster
2Kx 8-Dual Port Slave
2Kx 8-Dual Port Master
2Kx 8-Dual Port Slave
4Kx 8-Dual Port, No Arbitration
4Kx8-Dual Port, w/Semaph
4Kx 8-Dual Port, No Arbitration
4Kx 8-Dual Port, w/ Sernaph, Busy, Int
4Kx 9-Dual Port, w/ Sernaph, Busy, Int
8Kx 8-Dual Port, w/ Sernaph, Busy, Int
8Kx 9-DuaIPort, w/ Sernaph, Busy, Int
8Kx8-CS Power-Down
8Kx8-CSPower-Down
8Kx 8-CS Power-Down
16
16
16
16
16
16
22
24S
22
22
18
18
18
18
18
18
24S
48
48
52
52
24
24
32
20
20
20
22S
24S
24S
48
48
52
52
48
52
52
68
68
68
68
28S
28
28S
CY7C189
CY7C190
CY74S189
CY27S03A
CY27S07A
CY27LS03M
CY7C122
CY7C123
CY9122/91L22
CY93422A/93L422A
CY7C147
CY2147/21L47
CY7C148
CY2148/21L48
CY7C149
CY2149/21L49
CY7C150
CY7C130
CY7C140
CY7C131
CY7C141
CY7C128A
CY6116A
CY6117A
CY7C167A
CY7C168A
CY7C169A
CY7C170A
CY7Cl71A
CY7CI72A
CY7C132
CY7C142
CY7C136
CY7C146
CY7B134
CY7B1342
CY7B135
CY7B138
CY7B139
CY7Bl44
CY7BI45
CY7BI85
CY7B186
CY7C185
55@25
55@25
90@35
90@25
90@25
38@65
60@25
120@7
120@25
80@45
80/1O@35
125/25@35
80/10@35
120/20@35
80@35
120@35
90@12
170@25
170@25
170@25
170@25
90/20@55
80/20@55
80/20@55
50/15@45
70/15@45
70@45
90@45
90@45
90@45
170@25
170@25
170@25
170@25
240
240
240
260
260
260
260
150/50
140/40@12
120/20@15
D,L,P
D,L,P
D,P
D,L,P
D,L,P
D,L
D,L,P,S
D,L,p,V
D,P
D,L,P
D,L,p,S
D,P
D,L,p,S
D,P,S
D,L,P,S
D,P
D,L,p,S
D,L,P
D,L,P
J,L
J,L
D,L,p,V
D,L
L
D,L,p,V
D,L,p,V
D,L,p,V
D,L,p,V
D,L,p,V
D,L,p,V
D,L,P
D,L,P
J,L
J,L
D,J,L,P
J,L
J,L
G,J,L
G,J,L
G,J,L
G,J,L
D,P,V
D,P,V
D,L,p,V
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
2Q92
2Q92
2Q92
2Q92
2Q92
2Q92
2Q92
Now
Now
Now
64K
64K
64K
8Kx 8-CS Power-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
28
22S
22S
CY7C186
CY7B164
CY7CI64
120/20@15
140/50@8
115/40@20
D,P
D,p,V
D,L,P,V
Now
Now
Now
64K
64K
16Kx 4-Output Enable
16Kx 4-0utput Enable
24S
24S
CY7B166
CY7C166
140/50@8
115/40@15
D,p,V
D,L,P,V
Now
Now
64K
16Kx 4-Separate I/O, Transparent
Write
16Kx 4-Separate I/O
16Kx 4-Separate I/O, Transparent
Write
16Kx 4-Separate I/O
28S
CY7B161
tAA = 15, 25
tAA = 15,25
tAA=35
tAA =25,35
tAA =25,35
tAA= 65
tAA = 15,25,35
tAA = 7, 9, 10, 12, 15
tAA = 25,35,45
tAA = 35,45,60
tAA = 25, 35, 45
tAA = 35,45,55
tAA = 25,35,45
tAA = 35,45,55
tAA = 25, 35, 45
tAA = 35,45,55
tAA = 10,12,15,25,35
tAA = 25, 35, 45, 55
tAA = 25,35,45,55
tAA = 25, 35, 45, 55
tAA = 25, 35, 45, 55
tAA = 20,25,35,45,55
tAA = 20, 25, 35, 45, 55
tAA = 20, 25, 35, 45, 55
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 25,35,45,55
tAA = 25, 35, 45, 55
tAA = 25, 35, 45, 55
tAA = 25,35,45,55
tAA = 20,25,35
tAA = 20,25,35
tAA = 20,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 9, 10, 12, IS
tAA = 12,15
tAA = 10, 12, 15, 20, 25,
35,45
tAA = 12,15,20,25,35,45
tAA = 8, 10, 12
tAA = 10,12,15,20,25,
35,45
tAA = 8, 10, 12
tAA = 10,12,15,20,25,
35,45
tAA = 8, 10, 12
140/50@8
D,P,V
Now
28S
28S
CY7B162
CY7C161
140/50@8
115/40@15
D,P,V
D,L,P,V
Now
Now
28S
CY7C162
tAA = 8, 10, 12
tAA = 10,12,15,20,25,
35,45
tAA = 10, 12, 15,20,25,
35,45
115/40@15
D,L,p,V
Now
64K
64K
64K
1-8
Product Selector Guide
Static RAMs
(continued)
Speed (ns)
(mA@ns)
IccflsB
Packages
Availability
CY7CI87
CY7C182
CY7180
CY7181
CY7CI83
CY7C184
CY7CI57
CY7C198
CY7C199
CY7B199
CY7C194
CY7C196
CY7C191
tAA = 10, 12, 15,20,25,35,45
tAA = 12,15,20,25,35,45,55
tMATCH = 12,15,20
tMATCH = 12,15,20
tAA = 25,35,45
tAA = 25,35,45
tAA = 20, 24, 33
tAA = 25,35,45,55
tAA = 12, 15,20,25,35,45,55
tAA = 10,12,15
tAA = 12,15,20,25,35,45
tAA = 12, 15, 20, 25, 35, 45
tAA = 12,15,20,25,35,45
90/40@15
14O/35@25
250@12
250@12
220@25
2ZO@25
250
170/35@25
170/35@25
170@12
120/35@25
lZO/35@25
120!35@25
D,L,P,V
D,P,V
G,J,L
G,J,L
J
J
J,L
D,L,P
D,L,P,V
D,P,V
D,L,P,V
D,L,P,V
D,L,P,V
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
28S
28S
28S
28S
CY7C192
CY7B153
CY7B154
CY7B191
tAA = 12,15,20,25,35,45
tAA = 10,12,15
tAA = 10, 12, 15
tAA = 10,12,15
120/35@25
160
160
160
D,L,P,V
D,L,P,V
D,L,p,V
D,L,P,V
Now
Now
Now
Now
28S
24S
28S
28S
CY7Bl92
CY7B194
CY7B195
CY7B196
tAA =
tAA =
tAA =
tAA =
160
160
160
160
D,L,P,V
D,L,P,V
D,L,P,V
D,L,P,V
Now
Now
Now
Now
28S
24S
24S
24S
28S
44
44
32
32
32
28
28
32
CY7C195
CY7B193
CY7B197
CY7C197
CY7B163
CY7C173
CY7C174
CY7CI08
CY7Cl009
CY7C109
CY7ClO06
CY7C106
CY7C1001
tAA = 12, 15, 20, 25, 35, 45
tAA = 10,12,15
tAA = 10,12,15
tAA = 12, 15, ZO, 25, 35, 45
tAA = 10,12,15
tcov = 14, 18,21
tCDV = 14, 18,21
tAA = 25,35,45
tAA = 12,15,20
tAA = 25,35,45
tAA = 12,15,20
tAA = 25,35,45
tAA=12,15,20
120/35@25
130
130
100/35@25
130
200@14
ZOO@14
140@25
150@15
14O@25
150@15
130@25
150@15
D,L,p,V
D,L,P,V
D,L,P,V
D,L,P,V
D,L,P,V
J,L
J,L
L
D,L,V
D,V
D,L,V
D,L,V
D,L,V
Now
Now
Now
Now
lQ92
Now
Now
Now
4Q92
Now
4Q93
Now
1Q93
32
CY7C101
tAA = 25,35,45
130@25
D,L
Now
32
32
28
28
CY7CI002
CY7C102
CY7ClO07
CY7C107
tAA=12,15,20
tAA = 25,35,45
tAA = 12, 15,20
tAA = 25,35,45
150@15
130@25
150@15
130@25
D,L,V
D,L,V
D,L,V
D,L,V
1Q93
Now
1Q93
Now
Size
Organization
Pins
64K
12K
12K
12K
128K
128K
256K
256K
256K
256K
256K
256K
256K
64Kx l-CS Power-Down
8Kx9
4Kx IS-Cache Thg, Multiprocessing
4K x IS-Cache Tag, [;!lniprocessing
8Kx 16-Addresses Latched except A12
8Kx 16-Addresses Latched
16Kx 16-SPARCCache RAM
32Kx 8-CS Power-Dowo
32Kx8-CSPower-Dowo
32Kx 8-CS Power-Dowo
64Kx4-CSPower-Dowo
64Kx4-CSPowerDowowithOE
64Kx 4-Separate I/O, 'Itansparent
Write
64Kx 4--Separate I/O
64Kx4-Common I/O, Linear Decode
64Kx 4-Common I/O, Linear Decode
64Kx4--Separate I/O, 'Itansparent
Write
64Kx 4-Separate I/O
64Kx4-CS Power-Down
64Kx4-CSPower-Dowow/OE
64Kx4-CS Power-Downw/OE, Second
CS
64Kx4-CSPower-Downw/OE
256Kxl-CommonI/Ow/OE
256Kx l-CS Power-Down
256Kx l-CS Power-Dowo
256Kxl-LinearDecode
32K x 9-Cache, 486 Burst Mode
32K x 9-Cache, Linear Burst Mode
128KxS-CSPower-Dowo
128Kx8-CSPower-Dowo
128KxS-CS Power-Dowo
256Kx4-CSPower-Dowo
256Kx4-CSPower-Dowow/OE
256Kx4--Separate I/O, 'Itansparent
Write
256Kx4--Separate I/O, 'Itansparent
Write
256Kx4--Separate I/O
256Kx 4-Separate I/O
1Mx1-CSPower-Dowo
1Mx1-CSPower-Down
22S
28S
68
68
52
52
52
28
28S
28S
24S
28S
28S
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
288K
288K
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
Part Number
10,12,15
10,12,15
10, 12, 15
10,12,15
ECLSRAMs
Size
1K
1K
1K
lK
4K
4K
4K
4K
4K
4K
16K
16K
Organization
256x4-1OK/lOKH
256 x4-10K/10KH
256x4-1ooK
256 x 4-100K
4Kx1-lOK
4Kx1-100K
1024 x4-lOK/lO KH
lO24x4-lOK/lOKH
1024 x 4-100K
1024 x 4-100K
4Kx4-10K/IOKH
4Kx4-IOK/IOKH
Pins
24.4
24.4
24.4
24.4
18.3
18.3
24.4
24.4
24.4
24.4
28.4
28.4
PartNnmber
CY10E422
CYI0E422L
CY100E422
CY1OOE422L
CYlOE470
CYlooE470
CYI0E474
CYI0E474L
CY100E474
CY1ooE474L
CYIOE484
CY10E484L
Speed (ns)
tAA=4,5
tAA=5,7
tAA =3.5,5
tAA=5,7
tAA=5,7
tAA =5,7
tAA=4,5
tAA=5,7
tAA=3.5,5
tAA=5,7
tAA =4,5
tAA=7,1O
1-9
lEE
220
150
220
150
200
200
275
190
275
190
320
200
Packages
D,K,L, Y
D,J,K,L
D,K,L, Y
D,J,K,L
D
D
D,K,L,Y
D,J,K,L
D,K,L,Y
D,J,K,L
D,K,Y
D,J,K,V
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
~-:z
-=-,
Product Selector Guide
31ii!1i'rcYPRESS
SEMICONDUCTOR
EeL SHAMs (continued)
Size
16K
16K
16K
16K
64K
64K
64K
64K
64K
64K
Pins
Organization
28.4
28.4
28.4
28.4
28.4
28.4
28.4
28.4
28.4
28.4
4Kx4--100K
4Kx4--100K
4Kx4--100K
4Kx4--100K
16Kx4--1OK/lOKH
16Kx4--10K/10KH
16Kx4--100K
16Kx4--100K
16Kx4--100K
16Kx4--100K
PartNumber
CY100E484
CY100E484L
CY101E484
CY101E484L
CYlOE494
CY10E494L
CY101E494
CY101E494L
CY100E494
CYlOOE494L
Speed (ns)
tAA=4,5
tAA =7,10
tAA=4,5
tAA =7,10
tAA =7,8,10
tAA=12
tAA=7,8,10
tAA=12
tAA=8,10
tAA=12
Packages
lEE
320
200
320
200
190
135
190
135
190
135
D,K,V
D,J,K,V
D,K,Y
D,J,K, Y
D,K,V
D,K,V
D,K,V
D,K,V
D,K,V
D,K,V
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
SHAM Modules
Organization
Size
Pins
PartNumber
256K
256K
256K
64Kx4--JEDEC
32KxB-JEDEC
16Kxl6-JEDEC
24
28
40
CY7M194
CY7M199
CYM1610
256K
16Kx16
36
CYM1611
512K
16Kx32-JEDEC
64
CYM1821
512K
16Kx32
88
CYM1822
768K
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
l.5M
2M
2M
2M
2M
2.25M
4M
32Kx24
256Kx4--JEDEC
128KxB-JEDEC
128Kx8
128KxB-JEDEC
32Kx32
64Kx16-JEDEC
64Kx16
64Kx16
64Kx16-JEDEC
16Kx68-Registered Address
16Kx6B-Latched Address
64Kx24
256Kx8-JEDEC
64Kx32
64Kx32-JEDEC
64Kx32
256Kx9
512KxB-JEDEC
56
28
32
30
32
66
40
40
40
40
104
104
56
60
60
64
60
CYM1720
CYMl240
CYM1420
CYM1422
CYM1423
CYM1828
CYM1620
CYM1621
CYM1622
CYM1624
CYM1910
CYM1911
CYM1730
CYM1441
CYM1830
CYM1831
CYM1832
CYM1540
CYMl466
4M
4M
4M
4M
4M
4M
4M
8M
8M
8M
9M
16M
512Kx8
512Kx8
512KxB-JEDEC
512Kx8-JEDEC
256Kx16
128Kx32
128Kx32
256Kx32
256Kx32-JEDEC
IMx8
1Mx9
2Mx8
36
36
32
32
48
64
66
60
64
36
44
32
44
36
CYM1460
CYM1461
CYM1464
CYMl465
CYM1641
CYM1836
CYM1838
CYM1840
CYM1841
CYM1471
CYM1560
CYM1481
Speed (ns)
tAA=12,15
tAA=12,15
tAA =12,15
tAA =20,25,35,45,50
tAA = 12,15
tAA =20,25,30,35,45
tAA= 12,15
tAA =20,25,30,35,45
tAA= 12,15
tAA =20,25,30,35,45
tAA = 15,20,25,30,35
tAA = 25,30,35,45
tAA = 20,25,30,35,45,55
iAA =35,45,55
tAA=45,55,70
tAA =25,30,35,45,55, 70
tAA = 25, 30, 35,45, 55
tAA = 20,25,30,35,45
tAA=25,30,35,45
tAA = 25,35,45
tAA = 25,35,45
tAA = 25,35,45
tAA = 25,30,35
tAA=25,35,45
tAA =25,30,35,45,55
tAA =20,25,30,35,45
tAA=25,35,45,55
tAA=30,35,45
tAA = 35,45,55,70,85,
100,120
tAA = 35,45,55,70
tAA= 70,85, 100
tAA =20,25,30,35,45,55, 70
tAA = 70,85, 100, 120,150
tAA =25,30,35,45,55
tAA = 20, 25, 30, 35, 45
tAA = 25,30,35
tAA = 20,25,30,35,45,55
tAA = 20,25,30,35,45,55
tAA = 85, 100, 120
tAA=30,35,45
tAA = 85, 100, 120
1-10
ICc/ISu/ICCDR
(mA@ns)
325@1O
375@10
550@12
330@2O
550@12
330@2O
960@12
72O@25
960@12
720@25
330@25
480@25
210@30
200@35
210@45
400@45
340@25
1250@2O
400@25
500@25
1900@25
1900@25
510@25
960@25
880@25
720@2O
980@25
1125@30
350@35
184@55
84@100
625@35
150@70
300@35
110@85
1800@25
480@2O
720@25
1120@25
960@25
1l0@85
12OO@30
110@85
Packages
HD
HD
HD
HD
HV,PV
HV,PV
PM,PZ
PM,PZ
HV
HV
PZ
HD
HD,PD
PS
PD
HG
HD,PD
HD
HV
PV
PV
PV
PZ
PZ
HD
PM, PN, PZ
PZ
PF,PS
HD
PF,PS
PF,PS
PD
PD
HD
PM,PZ
HG
HD,PD
PM,PN,PZ
PS
PF,PS
PF,PS
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
·. ';~PRESS
Product Selector Guide
- _ : SEMICONDUCl'OR
PROMs
Size
Organization
Pins
PartNumber
Speed (ns)
Icc/ISB
(mA@ns)
D,L,P
D,L,P
D,L,P
Now
Now
Now
D,L,P
Now
D,L,P,Q,S,W
D,L,P,Q,S,W
Now
Now
D, L, P, Q, S, W
D,L,P,Q,S,W
Now
Now
D,P
D,L,P,Q,S,W
Now
Now
D,L,P,Q,S,W
Now
H,P,W
3Q92
Packages
Availability
4K
8K
8K
512 x 8-Registered
1024 x 8-Registered
lKx8
24S
24S
24S
CY7C225
CY7C235
CY7C281
tSA/CO ~ 25112, 30/15, 35/20, 45/25
tSA/CO ~ 25/12,30/15,40/20
8K
lKxS
24
CY7C282
tAA ~30,45
16K
16K
2Kx 8-Registered
2Kx 8-Rcgistcred
24S
24S
CY7C245/L
CY7C245A/L
tSA/CO
tSA/CO
16K
16K
2KxS
2Kx8
24S
24S
CY7C291/L
CY7C291A/L
tAA ~35,40
lAA ~ 20,25,30,35,50
16K
16K
2KxS
2Kx8
24
24
CY7C292/L
CY7C292A/L
lAA
lAA
16K
2Kx8-CSPower-Down
24S
CY7C293A/L
tAA ~ 20,25,30,35,50
16K
2Kx8-Reprogrammable Slate
MachmeProm
2Kx 8-Rcprogrammable State
Machine Prom
8Kx8-CS Power-Down
28
CY7C258
tAA ~ 12,15,18,25
90
90
90@45,
100@30
90@45,
100@30
90/60
120@15,
90/60@25
90/60
120/40@20,
90/30@25
90/60
120/40@20,
90/30@25,
60/15@35
120/40@20,
90/30@25
175
28
CY7C259
tAA ~ 12,15,18,25
200
H,P,W
3Q92
24S
CY7C261
tAA ~ 20,25,30, 35,4045,55
140/40@20,
100/30@25
140/40@20,
100/30@25
140/40@20,
100/30@25
140@15,
100@40
D,L,P,Q,S,W
Now
D,L,P,Q,S,W
Now
D,P
Now
D,L,P,Q,S,W
Now
16K
64K
tAA~30,45
~
~
25/12,35/15,45/25
15/10,18/12,25/12,35/15
~35,50
~20,25,30,35,50
64K
8Kx8
24S
CY7C263
tAA ~ 20,25,30, 35,40,45,55
64K
8Kx8
24
CY7C264
tAA ~ 20,25,30, 35,40,45,55
64K
8K x 8-Registered
28S
CY7C265
tSA/CO ~ 40/20, 15/12,25/20, 18115
64K
8Kx8-EPROMPinout
28
CY7C266
tAA~20,25
64K
8Kx 8-Registered, Diagnostic
28S
CY7C269
tSA/CO ~ 15/12,18/15,25/20,
40/20,50/25
64K
8Kx8-Registered, Diagnostic
32
CY7C268
tSA/CO ~ 40/20,50/25
128K
128K
256K
256K
16Kx8-CSPower-Down
16Kx8
Processor-Specific PROM
16Kx 16-Registered
EPROM Pinout
16Kx 16-Registered
16Kx 16
16Kx 16-Power-Down
EPROM Pinout
32Kx 8-CS Power-Down
32Kx 8-EPROM Pinout
32Kx 8-Registered
32Kx 8-Latchcd
64Kx8
64Kx8-Registered
64Kx8withALE
64Kx8 with ALE
64Kx 16-Power-Down
64Kx 16-Registered
128Kx8
28S
28
44
40
CY7C251
CY7C254
CY7C270
CY7C272
tAA ~ 45,55,65
tAA ~ 45,55,65
tAA/CKB ~ 35/24,40/30
tSA/CO ~ 25,30
44
44
40
CY7C275
CY7C276
CY7C273
tAS/CKO ~ 25/15,30/18
tAA ~30,35
28S
28
28S
28
28
28S
28S
32S
40
40
32
CY7C271
CY7C274
CY7C277
CY7C279
CY7C286
CY7C287
CY7C285
CY7C289
CY7B210
CY7B211
CY7B201
tAA ~ 35, 45,55
tAA ~ 35, 45, 55
tSA/CO ~ 40/20, 30/15, 50/25
tAA ~ 35, 45, 55
tAA ~ 50,60,70
256K
256K
256K
256K
256K
256K
256K
512K
512K
512K
512K
1M
1M
1M
tAA~40,45
tco~20
tAA ~ 65/20,75/25,85/35
tAA ~ 65/20,75/25,85/35
tAA~25,30
tSA/CO ~ 18/12,25/15
tAA~25,30
1-11
D,L,P,Q,W
Now
D,L,P,Q,S,W
Now
D,L,Q,W
Now
D,L,P,Q,W
D,P
Q
Q,W
Now
Now
2Q92
2Q92
250
250
250
Q
Q
Q,W
2Q92
2Q92
2Q92
120/30
120/30
120/30
120/30
120
150
180
180
180/25
180
180/25
D,L,P,Q,W
D,L,P,Q,W
D,L,P,Q,W
D,L,P,Q,W
Q,W
Q,W
Q,W
Q,W
Q,W
Q,W
Q,W
Now
Now
Now
Now
Now
Now
Now
Now
2Q92
2Q92
2Q92
190/15@20,
100/15@35
190@15,
100@40,
80@50
100@40,
80@50
100/30
100/30
250
250
o
u.
~
J; .~
Product Selector Guide
.'~NDucroR
PLDs
Size
Organization
Pins
IccflsB
Speed (ns)
ParlNumber
2Q92
2Q92
2Q92
2Q92
Now
Now
Now
Now
Now
Now
Now
190
190
90
55
70
190
80
130
130@50MHz
120@25ns
tpo=15
120@20ns
D,H,J,L,P,Q,W
Now
CY7B333
CY7C335
tPOIS/CO = 10{8{8
fMAXitIS = 83 MHzI2ns
130
140
D, J,K, L, P, Y
D,H,J,L,P,Q, W
Now
2Q92
28S
28S
28S
CY7B336
CY7B337
CY7B338
fMAXO = 156 MHz, teo = 6ns
fMAXO = 142 MHz,tco =7ns
fMAXO = 156MHz, tpo = 6ns
180
180
180
D,J, L, P, V
D,J,L, P, V
D, J, L, P, V
Now
Now
Now
28S
CY7B339
fMAXD = 142MHz, tpo = 7ns
180
D,J,L,P, V
Now
28S
CY7C361
fMAX = 125 MHz
140
D,H,J,L,P,Q,W
Now
28S
44
68
84
CY7C344
CY7C343
CY7C342
CY7C341
tPOIS/CO =
tPOIS/CO =
tPOIS/CO =
tPOIS/CO =
200{150
135{125
250{225
380{360
D,H,J,L,P'Q,W
H,J
G,H,J,L,R
H,J
Now
Now
Now
Now
16L8
16R8
16R6
16R4
16L8
16R8
16R6
16R4
18GS--Generic
22V10-Macrocell
22VIO-Macrocell
20
20
20
20
20
20
20
20
20
24S
24S
PALI6L8B
PAL16R8B
PALI6R6B
PAL16R4B
PALCI6L8{L
PALCI6R8{L
PALCI6R6{L
PALCI6R4{L
PLDC18G8
PALC22VI0{L
PALC22VlOB
tpo=5
ts/co = 4{4.5
tPOIS/CO = 5{4{4.5
tPOIS/CO = 5{4{4.5
tpo=20
ts/CO = 15{12
!POlS/CO = 20{20{15
tpOIS/CO = 20{20{15
tpOIS/CO = 12{8{10
tPOIS/CO = 25{15{15, 20{12{12
tPOIS/CO = 15{1O{1O
180
180
180
180
70,45
70,45
70,45
70,45
90no
90,55
90
PLD24
PLD24
PAL24
PLD24
PLD24
PLDB24
PLD24
PLD24
PLD28
PLD28
22VIO-Macrocell
22VPIO-Macrocell
22VIO-Macrocell
2OGIO-Generic
20G10-Generic
20GIO-Generic
20RAIO-Asynchronous
PLD610-16 Macrocell
7C330-State Machine
7C331-Asynchronous,
Registered
7C332-Input Registered,
Combinatorial
7B333-16 Macrocell
7C335-Universal
Synchronous
7B336-Input Reg., 2m
7B337-Input Reg., 4P'Th
7B338-Output Latcbed,
2P'Th
7B339-Output Latched,
4 P'Th
7C361-32 Macrocell State
Machine
7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
24S
24S
24
24S
24S
24S
24S
24S
28S
28S
PAL22VIOC
PAL22VPI0C
PALC22VI0D
PLDCZOGlO
PLDCZOGlOB
PLD20GlOC
PLD20RA10
CY7B326
CY7C330
CY7C331
tPOIS/CO = 7.5{3{6, 1O{3.6n.5
tPOIS/CO = 7.5{3{6, 1O{3.6n.5
tpo=7.5{10
tPOIS/CO = 25{15{15
tPOIS/CO = 15112{10
tPOIS/CO = 7.5{3{6.5, 1O{3.6n.5
tPOIS/CO = 15{1O{15
tpo=lO
fMAx, !:Is, tco= 66 MHz/3ns/12ns
tPOIS/CO = 20{12{20
28S
CY7C332
28S
28S
PLD28
PLD28
PLD28
PLD28
PLD28
PLD28
PLD28
MAX28
MAX44
MAX68
MAX84
AYailability
D,J,P
D,J,P
D,J,P
D,J,P
D,L,P'Q,V,W
D,L,P'Q,V,W
D,L,P,Q,V,W
D,L,P'Q,V,W
D,J,L,P,Q,v,w
D,J,K,L,P,Q,W
D,H,J,K,L,
P,Q,W
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P,Q,W
D,H,J,L,P,Q,W
D,J,L,P
D,H,J,L,P,Q,W
D,J,K,L,p,Y
D,H,J,L,P,Q,W
D,H,J,L,P'Q,W
PAL20
PAL20
PAL20
PAL20
PAL20
PAL20
PAL20
PAL20
PLD20
PLD24
PLD24
PLD28
Packages
(mA@ns)
20{12{12
25{15{14
25{15{14
30{20{16
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
ECLPLDs
Organization
16P8-10KH
16P8-10KH
16P8-100K
16P8-100K
16P4-lOKH
16P4-10KH
16P4-100K
16P4-100K
Pins
24
24
24
24
24
24
24
24
Speed (ns)
ParlNumber
CYI0E301
CYlOE301L
CY100E301
CY100E301L
CY10E302
CY10E302L
CYl00E302
CYI00E302L
lEE
(mA@ns)
240
170
240
170
220
170
220
170
tpo=3.5,4
tpo=6
tpo=3.5,4
tpo=6
tpo=3,4
tpo=4
tpo=3,4
tpn=4
Packages
D,K,Y
J,P
D,K,Y
J,P
D,K,Y
J,P
D,K,Y
JP
Availability
Now
Now
Now
Now
Now
Now
Now
Now
FIFOs
Organization
64x4
64x4
64x4-w{OE
Pins
16
16
16
CY3341
CY7C401
CY7C403
IccflsB
Speed
ParlNumber
1.2,2MHz
5,10, 15,25 MHz
10,15,25MHz
1-12
(mA@ns)
45
75
75
Packages
D,P
D,L,P
D,L,P
Availability
Now
Now
Now
.....:=-.
~~
Product Selector Guide
_'iECYPRESS
- I F SEMICONDUC'TOR
FIFOs (continued)
Pins
Organization
64x5
64x5-w/OE
64 x 8-w/OE and Almost Flags
64 x 9-w/Almost Flags
512 x 9-wIHalfFull Flag
512 x 9-wIHalfFull Flag
512 x 9-Clocked
512 x 9-Clockedw/Prog. Flags
1Kx9-w/HalfFull Flag
1Kx9-w/HalfFull Flag
2Kx9-w/HalfFull Flag
2Kx9-w/HalfFuIl Flag
2Kx 9-Bidirectional
2K x 9-Clocked
2K x 9-Clocked w/Prog. Flags
4Kx9-w/HalfFull Flag
4Kx9-wIHalfFull Flag
8K x 9-Module
8Kx 9--w/HalfFuIlFlag
8K x 9-w/ Prog. Flags
16K x 9-w/HalfFuliFlag
16K x 9-w/ Prog. Flags
16K x 9-Module
32Kx 9-w/HalfFuIlFlag
32K x 9-w/ Prog. Flags
64K x 9-Module
18
18
28S
28S
28
28S
28S
32
28
28S
28
28S
28S
28S
32
28
28S
28
28
28
28
28
28
28
28
28
PartNumber
CY7C402
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C441
CY7C451
CY7C424
CY7C425
CY7C428
CY7C429
CY7C439
CY7C443
CY7C453
CY7C432
CY7C433
CYM4210
CY7C460
CY7C470
CY7C462
CY7C472
CYM4220
CY7C464
CY7C474
CYM4241
IccfIsB
Speed
5, to, 15, 25 MHz
10, 15, 25 MHz
15, 25, 35 MHz
15,25,35MHz
20,25,30,40,65 ns
20, 25,30,40,65 ns
14, 20, 30ns'
14, 20, 30ns'
20, 25,30,40,65 ns
20, 25,30,40,65 ns
20, 25,30,40,65 ns
20, 25, 30,40, 65ns
30,40, 65ns
14,20,30ns'
14, 20, 30 ns'
25,30,40,65 ns
25,30,40,65 ns
30, 40, 50, 65 ns
15, 25, 40ns
15,25,40ns
15, 25, 40 ns
15, 25, 40 ns
30, 40, 50, 65 ns
15,25,4Ons
15,25,4Ons
85, lOOns
(mA@ns)
75
75
120
120
142/30
142/30
180
180
142/30
142/30
142/30
142/30
140/40
180
180
142/25
142/25
540/120
180
180
180
180
540/120
180
180
240@85
Packages
Availability
D,L,P
D,L,P
D,L,P,V
D,L,P,V
D,P
D,J,L,P,V
D,J,L,P, V
D,J,L
D,P
D,J,L,P
D,P
D,J,L,P,V
D,J,L,P,V
D,J,L,p,V
D,J,L
D,P
D,J,L,p,V
HD
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
HD
D,J,L,P
D,J,L,P
PD
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Logic
Organization
Programmable Skew Clock Buffer
(TIL Output)
prwammable Skew Clock Buffer
(C OS Output)
2901-4-Bit Slice
2901-4-Bit Slice
4x2901-16-BitSlice
29116-16-Bit Controller
29116-16-Bit Controller
29117-16-Bit Controller
2909-Sequencer
2911-Sequencer
ECl./ITL Translator-10KH
ECl./ITL Translator-lOOK
2909-Sequencer
2911-Sequencer
2910-Controller (17-word Stack)
2910-C0ntroller (9-word Stack)
16x16 Multiplier
16x 16 Multiplier
16 x 16 Multiplier/Accumulator
SPARC CasheStorage Unit
Pins
Part Number
IccfIsB
Speed (ns)
(mA@ns)
Packages
Availability
32
CY7B991
15-80 MHz
65
J,L
2Q92
32
CY7B992
15-BOMHz
65
J,L
2Q92
40
40
64
52
52
68
28
20
84
84
28
20
40
40
64
64
64
160
CY7C901
CY2901
CY7C9101
CY7C9116
CY7C9115
CY7C9117
CY7C909
CY7C911
CY10E383
CYI01E383
CY2909
CY2911
CY7C910
CY2910
CY7C516
CY7C517
CY7C510
CY7C611A
tCLK=23,31
C
tCLK = 30,40
tCLK = 35,45,53, 79, 100
tCLK = 35,45,53, 79, 100
tCLK =35,45,53,79, 100
tCLJ{=30,40
tCLJ{=30,40
tpD= 3/4ns
tpD= 3/4ns
A
A
tCLK = 40,50,93
A
tMc=38,45,55,75
tMc=38,45,55,75
tMc=45,55,65,75
Freq.=25MHz
70
140
60
145
145
145
55
55
255
255
70
70
100
170
100@10MHz
100@10MHz
100@10MHz
600
D,J,L,P
D,P
D,J,L,P
D,G,J,L
J
G,J,L
D,J,L,P
D,J,L,P
J
J
D,P
D,P
D,J,L,P
D,J,L,P
D,G,J,L,P
D,G,J,L,P
D,G,J,L,P
N
Now
Now
Now
Now
Now
Now
Now
Now
2Q91
2Q91
Now
Now
Now
Now
Now
Now
Now
Now
Note:
• Clocked FIFO [CY7C441/443/451/453] times are cycle times.
1-13
o
LL
Z
~r&PRFSS
~_.,
Product Selector Guide
SEMICONDucroR
RISC
Desc.
Organization
IV
FPU
SPARC 32-bit Integer Unit
Fioating-Point Unit
(Controller and Processor)
Cache-Controlled Memory
Management Unit
Cache Controller and Multiprocessing
Memory Management Unit
SPARC 32-bit Inte~er Unit for
Embedded Contro
SPARC Cache Storage Unit
Complete Uniprocessor SPARCCPU
Complete Multiprocessor SPARCDual CPU
Complete Multiprocessor SPARCSingle CPU
CMU
CMU
-MP
IV
CSU
CPU
CPU
CPU
Pins
ICcJISB
(mA@40MHz)
Packages
Freq. = 40, 33, 25
Freq. = 40, 33,25
675
350
G
G
Now
Now
CY7C604A
Freq. = 40, 33,25
750
G
Now
CY7C605A
Freq. = 40, 33, 25
850
G
Now
PartNnmber
Speed (MHz)
207
143
CY7C601A
CY7C602A
243
243
Availability
160
CY7C611A
Freq. =25
600
N
Now
52
MBusloo
MBusloo
MBusloo
CY7C157A
CYM6001K
CYM6002K
CYM6oo3K
Freq. =
Freq. =
Freq. =
Freq. =
250
2600
5200
2800
J
Now
Now
Now
Now
40,33,25
40,33,25
40,33,25
40,33,25
Design and Programming Thols
Part Name
PartNumber
'lYPe
QuickProII
Pill ToolKit
MAX+PLUS'"
QP2-MAX'" Pill Programmer
MAX+PLUSPLS-EDIF
Programmer
Design 'lbol
Design Tool
Programmer
Design tool
CY3300
CY3101
CY3201
CY3202
CY3210
VMEbus Interface Products
Organization
VME Interface Controller
VMEAddress Controller
64-BitVIC
Pins
144/160
144/160
144/160
Speed (MHz)
PartNumber
VIC068A
VAC068A
VIC64
64
Icc(mA)
250
150
300
50
64
Packages
B,G,N,U
B,G,N,U
B,G,N,U
Availability
Now
Now
Now
Communication Products
Organization
HotLink '!tansmitter
HotLink 1tansmitter
HotLink '!tansmitter
HotLink Receiver
HotLink Receiver
HotLink Receiver
Pins
28
28
28
28
28
28
Part Number
CY7B921
CY7B922
CY7B923
CY7B931
CY7B932
CY7B933
Speed (MHz)
130-170
170-240
240-310
130-170
170-240
240-310
lcc(mA)
70
70
70
100
100
100
Packages
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
Availability
3Q92
3Q92
3Q92
3Q92
3Q92
3Q92
Notes:
The above specifications are for the commercial temperature range ofOOC to 70°C. Military temperature range (-55°C to +125°C) product processed
to MIL-STD-883 Revision C is also available for most products. Speed and power selections may vary from those above. Contact your local sales office
for more information.
Commercial grade product is available in plastic, CERDIp, or LCC. Military grade product is available in CERDIP, LCC, or PGA. F, K, and T packages
are special order only.
All power supplies are V cc = 5V ± 10% (Vee = 5V ± 5% for RISC).
22S, 24S, 28S stands for 300 mil. 22-pin, 24-pin, 28-pin, respectively. 28.4 stands for 28-pin 400 mil, 24.4 stands for 24-pin 400 mil.
PLCC, SOl, and SOIC packages are available on some prodncts.
F, K, and T packages are special order only.
MAX and MAX + PLUS are registered trademarks of Altera Corporation.
Package Code:
R = WINDOWED PGA
B = PLASTIC PIN GRID ARRAY
S = SOIC
D = CERDIP
T = WINDOWED CERPAK
E = TAPE AUTOMATED BOND
U
= CERAMIC QUAD FLATPACK
(TAB)
V = SOJ
F = FLATPAK
W = WINDOWED CERDIP
G = PIN GRID ARRAY (PGA)
X = DICE
H = WINDOWED HERMETIC LCC
HD
= HERMETIC DIP
J = PLCC
HV
= HERMETIC VERTICAL DIP
K= CERPAK
PF = PLASTIC FLAT SIP
L = LEADED CHIP CARRIER (LCC)
PS = PLASTIC SIP
N = PLASTIC QUAD FLATPACK
PZ = PLASTIC ZIP
P = PLASTIC
Y = CERAMIC LCC
Q = WINDOWED LCC
1-14
~
~
~.CYPRESS
_ F SEMlCONDUC'TOR
at
CYPRESS
2147-3SC
2147-4SC
2147-4SC
2147-4SM+
2147-5SC
2147-SSM
2148-3SC
2148-35C
2148-3SM
2148-4SC
2148-4SC
2148-4SM
2148-4SM+
2148-SSC
2148-SSC
2148-SSM
2149-3SC
2149-3SC
2149-3SM
2149-4SC
2149-4SM
2149-4SM
2149-SSC
2149-SSC
2149-SSM
21IA8-3SC
21IA8-4SC
21IA8-4SC
21IAS-SSC
21IA9-3SC
21IA9-4SC
21IA9-4SC
21IA9-SSC
27S03AC
27S03AM
27S03C
27S03C
27S03M
27S03M
27S07AC
27S07AM
27S07C
27S07M
27S07M
2901CC
2901CM
2909AC
2909AM
2910AC
2910AM
2910C
2910M
2911AC
2911AM
3341-2C
3341-2M
3341C
3341M
S4S189M
6116-4SC
6116-SSC
6116-SSM
CYPRESS
7C147-3SC
2147-3SC
7C147-4SC
7C147-4SM+
2147-4SC
2147-4SM
21IAS-3SC
7C148-3SC
7C148-35M
2148-3SC
21IAS-4SC
2148-3SM
7C148-4SM+
2148-4SC
21IA8-SSC
2148-4SM
21IA9-3SC
7C149-3SC
7C149-3SM
21IA9-4SC
2149-3SM
7C149-4SM
2149-4SC
21IA9-SSC
2149-4SM
7C14S-3SC
21IAS-3SC
7C14S-4SC
21IAS-4SC
7C149-25C
21IA9-3SC
7C149-4SC
21IA9-4SC
7C189-25C
7C189-25M
27S03AC
74S189C
27S03AM
S4S189M
7Cl90-25C
7Cl90-25M
27S07AC
27S07AM
7C190-25M
7C901-31C
7C901-32M
7C909-40C
7C909-40M
7C91O-50C
7C910-S1M
2910AC
2910AM
7C911-40C
7C911-40M
7C401-SC+
7C401-lOM
3341-2C
3341-2M
27S03M
61l6-3SC
6116-45C
6116-4SM
Product Line Cross Reference
CYPRESS
74S189C
7C122-25C
7C122-3SC
7C122-3SM
7C123-12C
7Cl28-3SC
7C12S-4SC
7C128-4SM
7C12S-SSC
7C128-SSM
7C130-4SC
7C130-SSC
7C130-SSM
7C131-4SC
7C131-SSC
7C131-SSM
7C132-4SC
7C132-SSC
7C132-SSM
7C136-4SC
7C136-SSC
7C136-SSM
7C140-3SC
7C140-4SC
7Cl40-SSC
7C141-3SC
7C141-4SC
7C141-SSC
7C147-3SC
7C147-4SC
7C148-3SC
7C148-4SC
7C149-3SC
7C149-4SC
7C149-4SM
7ClS0-25C
7C1S0-3SC
7C1S0-3SM
7C167-3SC
7C167-4SM
7C168-35C
7C168-45M
7C169-3SC
7C169-40M
7C170-3SC
7C170-4SC
7C170-45M
7Cl71-35C
7Cl71-45M
7Cl72-3SC
7Cl72-45M
7C186L-4SM
7C189-25C
7Cl90-25C
7C191-45M
7Cl92-4SM
7C194-3SC
7C194-4SC
7C194-4SM
7C196-3SC
7C196-4SC
7C197-3SC
CYPRESS
27S03C
7C122-1SC+
7C122-25C
7C122-25M
7Cl23-7C
7Cl28-25C
7C128-3SC
7C128-3SM+
7C128-4SC+
7C128-4SM+
7C130-3SC
7C130-4SC
7C130-4SM
7C131-3SC
7C131-4SC
7C131-4SM
7C132-3SC
7C132-4SC
7C132-4SM
7C136-3SC
7C136-4SC
7C136-4SM
7C140-25C
7Cl40-3SC
7C140-4SC
7C141-25C
7C141-3SC
7C141-4SC
7C147-25C+
7C147-3SC
7C148-25C+
7Cl48-3SC
7C149-25C+
7C149-3SC
7C149-3SM
7C1S0-1SC
7C1S0-25C
7C1S0-25M
7C167-2SC
7C167-3SM+
7Cl68-25C
7C168-35M+
7C169-25C
7C169-35M+
7C170-25C
7C170-3SC
7C170-3SM
7Cl71-25C
7Cl71-35M+
7Cl72-25C
7Cl72-3SM+
7C186-45M
7C189-15C+
7C190-1SC+
7C191-3SM
7C192-3SM
7Cl94-25C
7C194-3SC+
7Cl94-35M
7C196-25C
7C196-3SC+
7C197-25C
1-15
CYPRESS
7Cl97-4SC
7C197-4SM
7C198-4SC
7C198-55C
7C198-SSM
7Cl99-4SC
7Cl99-SSC
7C199-SSM
7C225-30C
7C225-30M
7C225-40C
7C225-40M
7C23S-40C
7C24S-3SC
7C24S-4SC
7C24S-4SM
7C?ASA-25C
7C24SA-3SC
7C24SA-3SM
7C24SAL-3SC
7C24SL-3SC
7C24SL-4SC
7C251-SSC
7C251-6SC
7C251-6SC
7C251-65M
7C253-6SM
7C254-SSC
7C254-6SC
7C254-6SM
7C261-4SC
7C261-SSC
7C261-SSM
7C263-4SC
7C263-SSC
7C263-SSM
7C264-4SC
7C264-SSC
7C264-5SM
7C268-50C
7C268-60C
7C268-60M
7C269-S0C
7C269-60C
7C269-60M
7C281-45C
7C282-4SC
7C291-35C
7C291-5OC
7C291-S0M
7C291A-3SC
7C291A-3SM
7C291A-5OC
7C291A-SOM
7C291AL-35C
7C291AL-50C
7C291L-35C
7C291L-SOC
7C292-35C
7C292-S0C
7C292L-3SC
7C292L-50C
CYPRESS
7C197-3SC+
7C197-3SM
7C198-3SC
7C198-4SC+
7C198-4SM
7C199-3SC
7C199-4SC+
7C199-4SM
7C225-25C
7C225-25M
7C225-30C
7C225-3SM
7C23S-3OC
7C24S-2SC
7C24S-3SC
7C24S-3SM
7C24SA-18C
7C24SAL-3SC
7C24SA-2SM
7C24SA-2SC+
7C24S-3SC+
7C24SL-3SC
7C2S1-4SC
7C2S1-SSC
7C251-SSC
7C251-SSM
7C253-SSM
7C254-4SC
7C254-SSC
7C254-SSM
7C261-3SC
7C261-4SC
7C261-4SM
7C263-3SC
7C263-4SC
7C263-4SM
7C264-3SC
7C264-4SC
7C264-45M
7C26S-40C+
7C268-S0C
7C268-S0M+
7C269-40C+
7C269-50C
7C269-S0M+
7C281-3OC
7C282-30C+
7C291-25C+
7C291-3SC
7C291-3SM
7C291AL-3SC
7C291A-30M
7C291AL-50C
7C291A-35M
7C291A-25C+
7C291AL-3SC
7C291-3SC+
7C291L-3SC
7C292-2SC+
7C292-35C
7C292-3SC+
7C292L-3SC
•
0
LL
Z
Product Line Cross Reference.
CYPRESS
7CZ93A-35C
7CZ93A-35M
7CZ93A-5OC
7CZ93A-50M
7CZ93AL-35C
7CZ93AL-SOC
7C401-lOC
7C401-10M
7C401-5C
7C402-10C
7C402-10M
7C402-5C
7C403-10C
7C403-10M
7C403-15C
7C403-15M
7C404-10C
7C404-10M
7C404-15C
7C404-15M
7C40S-1SC
7C40S-15M
7C40S-25C
7C409-15C
7C409-15M
7C409-25C
7C420-40C
7C420-40M
7C420-65C
7C420-65M
7C421-40C
7C421-40M
7C421-65C
7C421-65M
7C424-40C
7C424-40M
7C424-65C
7C424-65M
7C425-40C
7C425-40M
7C425-65C
7C425-65M
7C42S-4OC
7C42S-40M
7C42S-65C
7C428-65M
7C429-40C
7C429-40M
7C429-65C
7C429-65M
7C51O-S5C
7C51O-65C
7C510-65M
7C51O-75C
7C510-75M
7C516-45C
7C516-S5C
7C516-55M
7C516-75C
7C516-75M
7C517-45C
7C517-55C
CYPRESS
7CZ93AL-35C
7CZ93A-'-30M
7CZ93AL-50C
7CZ93A-35M
7CZ93A-20C+
7C293AL-35C
7C401-15C
7C401-15M
7C401-lOC
7C402-15C
7C402-15M
7C402-lOC
7C403-15C
7C403-15M
7C403-25C
7C403-25M
7C404-15C
7C404-15M
7C404-25C
7C404-25M
7C40S-25C
7C408-25M
7C40S-35C
7C409-25C
7C409-25M
7C409-35C
7C420-30C
7C420-30M
7C420-40C
7C420-40M
7C421-30C
7C421-30M
7C421-40C
7C421-40M
7C424-30C
7C424-30M
7C424-4OC
7C424-40M
7C425-30C
7C425-30M
7C425-4OC
7C425-40M
7C428-3OC
7C428-30M
7C42S-40C
7C42S-40M
7C429-30C
7C429-30M
7C429-40C
7C429-40M
7C51O-45C
7C510-55C
7C510-55M
7C510-65C
7C510-65M
7C516-3SC
7C516-45C
7C516-42M
7C516-55C
7C516-55M
7C517-3SC
7C517-45C
CYPRESS
7C517-55M
7C517-75C
7C517-75M
7C901-31C
7C901-32M
7C909-40C
7C909-40M
7C91O-50C
7C91O-51M
7C91O-93C
7C910-99M
7C9101-4OC
7C9101-45M
7C91l-40C
7C91l-40M
9122-25C
9122-25C
9122-35C
9122-35C
9122-45C
91L22-25C
91L22-35C
91L22-45C
93422AC
93422AC
93422AM
93422C
93422M
93422M
93L422AC
93L422AC
93L422AM
93L422C
93L422M
Ml220HD-lOC
M1220HD-12C
M1220HD-15C
M1220HD-20C
M1220HD-12MB
M1220HD-15MB
M1220HD-20MB
M1400HD-lOC
M1400HD-12C
M1400HD-15C
Ml400HD-20C
M1400HD-12MB
M1400HD-15MB
Ml400HD-20MB
PALC16L8-25C
PALC16L8-30M
PALC16L8-35C
PALC16L8-40M
PALC16L8L-35C
PALC16R4-25C
PALC16R4-30M
PALC16R4-35C
PALC16R4-40M
PALC16R4L-35C
PALC16R6-25C
PALC16R6-30M
PALC16R6-35C
CYPRESS
7C517-42M
7C517-55C
7C517-55M
7C901-23C+
7C901-27M
7C909-30C
7C909-30M
7C910-4OC
7C910-46M
7C910-50C
7C910-51M
7C9101-3OC
7C9101-35M
7C91l-30C
7C91l-30M
7C122-15C
91L22-25C
9122-25C
91L22-35C
93L422C
7C122-25C
7Cl22-35C
93L422AC
7C122-35C
9122-35C
7C122-35M
93L422AC
93422AM
93L422AM
7C122-35C
91L22-45C
7Cl22-35M
93L422AC
93L422AM
7Ml94-10DC
7M194-12DC
7M194-15DC
7M194-20DC
7M194-12DMB
7M194-15DMB
7M194-20DMB
7M199-lODC
7M199-12DC
7M199-15DC
7M199-20DC
7M199-12DMB
7M199-15DMB
7M199-20DMB
PALC16L8L-25C
PALC16L8-20M
PALC16L8-25C
PALC16L8-30M
PALCl6L8L-25C
PALC16R4L-25C
PALC16R4-20M
PALC16R4-25C
PALC16R4-30M
PALC16R4L-25C
PALC16R6L-25C
PALC16R6-20M
PALC16R6-25C
CYPRESS
PALC16R6-40M
PALC16R6L-35C
PALC16RS-25C
PALC16RS-30M
PALC16R8-35C
PALC16R8-40M
PALC16R8L-35C
PALC22VI0-35C
PALCZ2VI0-40M
PALC22VI0L-25C
PALC22VI0L-35C
PLDCZOGlO-35C
PLDC20GlO-40M
CYPRESS
PALC16R6-30M
PALC16R6L-25C
PALC16RSL-25C
PALC16R8-20M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-25C
PALC22VI0-25C
PALC22VI0-30M
PALCZ2VI0-25C
PALC22VI0L- 25C
PLDC20GlO-25C
PLDCZOGlO-30M
ALTERA
PREFIX:EPM
PREFIX:EP
5032DC
5032DC-2
5032DM
50321C
50321C-2
50321M
5032LC
5032LC-2
5032PC
5032PC-2
5064JC
5064JC-2
5064JM
5128GC
5128GC-l
5128GC-2
5128GM
5128JC
5128JC-l
5128JC-2
5128JM
5128LC
5128LC-l
5128LC-2
610-25C
610-35M
610A-I0C
610A-12C
610A-15C
CYPRESS
PREFIX:CY
PREFIX:PLD
7C344-25WC
7C344-20WC
7C344-25WMB
7C344-25HC
7C344-20HC
7C344-25HMB
7C344-25JC
7C344-20JC
7C344-25PC
7C344-20PC
7C343-35HC
7C343-30HC
7C343-35HMB
7C342-35RC
7C342-25RC
7C342-30RC
7C342-35RMB
7C342-35HC
7C342-25HC
7C342-30HC
7C342-35HMB
7C342-35JC
7C342-25JC
7C342-30JC
610-25C
61O-25MB
610-10C
610-12C
610-15C
AMD
PREFIX:Am
PREFIX:SN
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
2130-100C
2130-120C
2130-55C
2130-55C
2130-55JC
2130-55JC
2130-70C
CYPRESS
PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
7C130-55C
7C130-55C
7C130-45C
7C130-55C
7C131-45C
7C131-55C
7C130-55C
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on Iss
+ = meets all performance specs but may not meet Icc or Iss
• - meets all performance specs except 2V data retention-may not meet Icc or Iss
functionally equivalent
t
SOiConly
:j: = 32-pin LCC crosses to the 7C198M
1-16
Product Line Cross Reference
AMD
2130-70JC
2130-70tBC
2140-55C
2140-55C
2140-55JC
2140-55JC
2140-70C
2140-70JC
2140-70tBC
2147-35C
2147-45C
2147-45M
2147-55C
2147-55M
2147-70C
2147-70M
2148-35C
2148-35M
2148-45C
2148-45M
2148-55C
2148-55M
2148-70C
2148-70M
2149-35C
2149-45C
2149-45M
2149-55C
2149-55M
2149-70C
2149-70M
2167-35C
2167-35M
2167-45C
2167-45M
2167-55C
2167-55M
2167-70C
2167-70M
2168-35C
2168-45C
2168-45M
2168-55C
2168-55M
2168-70C
2168-70M
2169-40C
2169-50C
2169-50M
2169-70C
2169-70M
21lA7-45C
21lA7-55C
21lA7-70C
21lA8-45C
21lA8-55C
21lA8-70C
21lA9-45C
21lA9-55C
21lA9-70C
27C64-120C
27C64-120M
CYPRESS
7C130-55C
7C130-55MB
7C140-45C
7C140-55C
7C141-45C
7C141-55C
7C140-55C
7C141-55C
7C140-55MB
2147-35C
2147-45C
2147-45M
2147-55C
2147-55M
2147-55C
2147-55M
2148-35C
2148-35M
2148-45C
2148-45M
2148-55C
2148-55M
2148-55C
2148-55M
2149-35C
2149-45C
2149-45M
2149-55C
2149-55M
2149-55C
2149-55M
7C167A-35C
7C167A-35M
7C167A-45C
7C167A-45M
7C167A-45C
7C167A-45M
7C167A-45C
7C167A-45M
7Cl68A-35C
7C168A-45C
7Cl68A-45M
7C168A-45C
7C168A-45M
7C168A-45C
7C168A-45M
7C169A-40C
7C169A-40C
7C169A-40M
7C169A-40C
7C169A-40M
7C147-45C
7C147-45C
7C147-45C
21lA8-45C
21lA8-55C
21lA8-55C
21lA9-45C
21lA9-55C
21lA9-55C
7C266-55C
7C266-55C
AMD
27C64-125C
27C64-150C
27C64-150M
27C64-155C
27C64-200C
27C64-200M
27C64-205C
27C64-250C
27C64-250M
27C64-255C
27C64-300C
27C64-300M
27C64-55C
27C64-70C
27C64-75C
27C64-90C
27C64-90M
27C64-95C
27C191-25C
27C191-35C
27C191-35C
27C191-35C
27C191-35C
27C191-35M
27C191-45M
27C256-170C
27C256-170M
27C256-175C
27C256-200C
27C256-ZOOM
27C256-205C
27C256-250C
27C256-250M
27C256-255C
27C256-30OC
27C291-25C
27C291-35C
27C291-45M
27C291A-30M
27HOlO-XX
27LS03C
27LS03M
27LS07C
27LS191C
27LS291C
27LS291M
27PS181AC
27PS181AM
27PS181C
27PS181M
27PS191AC
27PS191AM
27PS191C
27PS191M
27PS281AC
27PS281AM
27PS281C
27PS281M
27PS291AC
27PS291AM
27PS291C
27PS291M
CYPRESS
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C266-55C
7C292A-25C
7C291A-25C+
7C291A-35C
7C292A-35C
7C292AL-35C
7C292A-30M
7C291A-45M
7C274-55C
7C274-55M
7C274-55C
7C274-55C
7C274-55M
7C274-55C
7C274-55C
7C274-55M
7C274-55C
7C274-55C
7C291A-25C
7C291AL-35C
7C291A-35M
7C291A-30M
7B201-35XX
27LS03C
27LS03M+
27S07C+
7C292-35C
7C291-35C
7C291-35M
7C282-45C
7C282-45M+
7C282-45C
7C282-45M+
7C292-50C
7C292-50M+
7C292-50C
7C292-50M+
7C281-45C
7C281-45M+
7C281-45C
7C281-45M+
7C291-50C
7C291-50M+
7C291-50C
7C291-50M+
1-17
AMD
27S03AC
27S03AM
27S03C
27S03M
27S07AC
27S07AM
27S07C
27S07M
27S181AC
27S181AM
27S181C
27S181M
27S191AC
27S191AM
27S191C
27S191M
27S191SAC
27S25AC
27S25AM
27S25C
27S25M
27S25SAC
27S25SAM
27S281AC
27S281AM
27S281C
27S281M
27S291AC
27S291AM
27S291C
27S291M
27S291SAC
27S291SAM
27S35AC
27S35AM
27S35C
27S35M
27S45AC
27S45AM
27S45C
27S45M
27S45SAC
27S45SAM
27549-30M
27549-30M
27549-40
27549-40
27549-55
27549-55
27549-55M
27549-55M
27S51C
27S51M
2841AC
2841AM
2841C
2841M
290lBC
290lBM
2901CC
2901CM
2909AC
CYPRESS
27S03AC
27S03AM
27S03C
27S03M
27S07AC
27S07AM
27S07C
27S07M,
7C282-30C
7C282-45M
7C282-45C
7C282-45M
7C292-35C
7C292-50M
7C292-5OC
7C292-50M
7C292A-20C
7C225-30C
7C225-35M
7C225-40C
7C225-40M
7C225-25C
7C225-35M
7C281-30C
7C281-45M
7C281-45C
7C281-45M
7C291-35C
7C291-50M
7C291-50C
7C291-50M
7C291A-25C
7C291A-30M
7C235-3OC
7C235-40M
7C235-4OC
7C235-40M
7C245-35C
7C245-45M
7C245-45C
7C245-45M
7C245-25C
7C245A-25M7C264-30MB
7C263-30MB
7C264-40C
7C263-4OC
7C264-55
7C263-55
7C264-55MB
7C263-55MB
7C254-55C
7C254-65M
3341C
3341M
3341C
3341M
290lCC
2901CM
2901CC
2901CM
2909AC
Product Line Cross Reference
AMD
CYPRESS
AMD
CYPRESS
AMD
CYPRESS
2909AM
2909C
2909M
29l0-lC
291O-lM
2910AC
2910AM
2910C
2910M
29116AC
29116AM
29116C
29116M
29117C
29117M
2911AC
2911AM
2911C
2911M
29510C
295 10M
295l6AM
295l6C
29516M
29517AC
295l7C
295l7M
29701C
29701M
29703C
29703M
29COl-lC
29COlBA
29COlBC
29COlC
29COICC
29CIO-IC
29CI01C
29C101M
29ClOABA
29ClOAC
29ClOAC
29C116C
29C116M
29Cl17C
29L116AC
29L116AM
29L510C
29L5lOM
29L516C
29L516M
29L517C
29L517M
3341C
3341M
67C401-1O
67C401-15
67C401-25
67C402-1O
67C402-15
67C402-25
67C4023-10
2909AM
2909AC
2909M
2910C
2910M
2910AC
2910AM
2910C
2910M
7C9116AC
7C9116AM
7C9116AC
7C9116AM
7C9117AC
7C9117AM
2911AC
2911AM
29llAC
2911M
7C51O-75C
7C51O-75M
7C5l6-55M
7C5l6-55C
7C5l6-55M
7C5l7-38C
7C517-55C
7C517-55M
27S07C
27S07M
27S03C
27S03M
7C901-23C+
7C901-32M
7C901-3lC
7C901-3lC
7C901-31C
7C9l0-40C
7C9101-40C
7C9101-35M
7C91O-51M
7C91O-50C
7C910-93C
7C9116AC
7C9116AM
7C9117AC
7C9116AC
7C9l16AM
7C51O-75C
7C51O-75M
7C516-75C
7C516-75M
7C517-75C
7C517-75M
3341C
3341M
7C401-1O
7C401-15
7C401-25
7C402-10
7C402-15
7C402-25
7C404-10
67C4023-15
67C403-10
67C403-15
67C403-25
7201-25
7201-35
7201-50
7201-65
7201-80
7201-25R
7201-35R
720l-50R
720l-65R
720l-80R
7202-25
7202-35
7202-50
7202-65
7202-80
7202-25R
n02-35R
7202-50R
7202-65R
7202-80R
7203-25
7203-35
7203-50
7203-65
7203-80
7203-25R
7203-35R
7203-50R
7203-65R
7203-80R
7204-25
7204-35
7204-50
7204-65
7204-80
74S189C
9122-25C
9122-35C
9122-35M
9128-100C
9128-120M
9128-150C
9l2S-150M
9128-200C
9128-200M
9128-70C
9128-90M
9l50-20C
9150-25C
9150-25M
9150-35C
9150-35M
9150-45C
9150-45M
91L22-35C
91L22-35M
91L22-45C
91L22-45M
7C404-15
7C403-1O
7C403-15
7C403-25
7C420-25
7C420-30
7C420-40
7C420-65
7C420-65
7C421-25
7C42l-30
7C421-40
7C421-65
7C42l-65
7C424-25
7C424-30
7C424-40
7C424-65
7C424-65
7C425-25
7C425-30
7C425-40
7C425-65
7C425-65
7C428-25
7C428-30
7C428-40
7C428-65
7C428-65
7C429-25
7C429-30
7C429-40
7C429-65
7C429-65
7C432-25
7C432-30
7C432-40
7C432-65
7C432-65
74S189C
9122-25C
9122-35C
7C122-35M
6116A-55C
6116A-55M
6116A-55C
6116A-55M
6116A-55C
6116A-55M
6116A-55C
6116A-55M
7Cl50-l5C
7Cl50-25C
7C150-25M
7C150-35C
7C150-35M
7C150-35C
7C150-35M
91L22-35C
7C122-35M
91L22-45C
7C122-35M
91L22-60C
91L50-25C
91L50-35C
91L50-45C
93422AC
93422AM
93422C
93422M
93L422AC
93L422AM
93L422C
93L422M
99Cl64-35C
99Cl64-45C
99Cl64-45M
99Cl64-55C
99C164-S5M
99C164-70C
99Cl64-70M
99Cl65-35C
99C165-45C
99Cl65-45M
99Cl65-55C
99C165-55M
99C165-70C
99C165-70M
99C641-25C
99C641-35C
99C641-45C
99C641-45M
99C641-55C
99C64l-55M
99C641-70C
99C641-70M
99C68-35C
99C68-45C
99C68-45M
99C68-55C
99C68-55M
99C68-70C
99C68-70M
99C8SH-35C
99C8SH-45C
99C8SH-45M
99CSSH-55C
99C8SH-55M
99C88H-70C
99C88H-70M
99CL68-35C
99CL68-45C
99CL68-45M
99CL68-55C
99CL6855M
99CL68-70C
99CL68-70M
PAL16L8A-4C
PAL16L8A-4M
PAL16L8AC
PAL16L8ALC
PAL16L8ALM
PAL16L8AM
PAL16LSBM
7C122-35C+
7C150-25C
7C150-35C
7Cl50-35C
93422AC
93422AM
93422C
93422M
93L422AC
93L422AM
93L422C
93L422M
7C164-35C+
7C164-45C+
7Cl64-45M+
7C164-45C+
7C164-45M+
7Cl64-45C+
7C164-45M
7Cl66-35C+
7C166-45C+
7C166-45M+
7Cl66-45C+
7C166-45M+
7C166-45C+
7C166-45M+
7Cl87-25C
7Cl87-35C
7C187-45C
7C187-45M
7C187-45C
7Cl87-45M
7Cl87-45C
7C187-45M
7C168A-35C
7C168A-45C'
7Cl68A-45M*
7C168A -45C'
7Cl68A-45M*
7Cl68A-45C*
7Cl68A-45M*
7C186-35C
7Cl86-45C
7C186-45M
7C186-55C
7C186-55M
7C186-55C
7Cl86-55M
7Cl68A-35C
7Cl68A -45C*
7Cl68A-45M'
7Cl68A-45C*
7C168A-45M*
7C168A-45C*
7Cl68A-45M*
PALC16L8L- 35C
PALC16L8-40M
PALC16L8-25C
PALC16L8-25C
PALC16L8-30M
PALC16L8- 30M
PALC16L8-20M
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 mA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* = meets all performance specs except 2V data retention-may not meet Icc or ISB
t
:j: =
functionally equivalent
SOIConly
32-pin LCC crosses to the 7C198M
1-18
Product Line Cross Reference
AMD
PAL16L8C
PAL16L8LC
PAL16L8LM
PAL16L8M
PAL16L8QC
PAL16L8QM
PAL16R4A-4C
PAL16R4A-4M
PAL16R4ALC
PAL16R4ALM
PAL16R4AM
PAL16R4BM
PAL16R4C
PAL16R4LC
PAL16R4LM
PALl6R4M
PAL16R4QC
PAL16R4QM
PALI6R6A-4C
PALI6R6A-4M
PALl6R6AC
PALl6R6ALC
PALl6R6ALM
PALl6R6AM
PALl6R6BM
PALl6R6C
PALl6R6LC
PALl6R6LM
PALl6R6M
PALl6R6QC
PALl6R6QM
PAL16R8A-4C
PAL16R8A-4M
PALl6R8AC
PALl6R8ALC
PALl6R8ALM
PALl6R8AM
PALl6R8BM
PALl6R8C
PALl6R8LC
PALl6R8LM
PALl6R8M
PALl6R8QC
PALl6R8QM
PAL22VIO-7C
PAL22VIO-7C
PAL22VlO-IO
PAL22VIO-lOC
PAL22VlO-IOC
PAL22VIO-15
PAL22VIO-15/B
PAL22VlO-20/B
PAL22VIO- 25/B
PAL22VI0- 30/B
PAL22VIO-15C
PAL22VlO-15C
PAL22VIO-25C
PAL22VIO-25C
PAL22VlO/B
PAL22VlOA/B
PAL22VlOAC
PAL22VIOAC
CYPRESS
PALC16L8-35C
PALCI6L8-35C
PALC16L8-40M
PALC16L8-40M
PALC16L8L-35C
PALC16L8-40M
PALC16R4L-35C
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PALCI6R4-30M
PALCI6R4-20M
PALC16R4-35C
PALC16R4-35C
PALC16R4-40M
PALCI6R4-40M
PALCI6R4L-35C
PALC16R4-40M
PALCI6R6L-35C
PALCI6R6-40M
PALC16R6-25C
PALCI6R6-25C
PALCI6R6-30M
PALCI6R6-30M
PALCI6R6-2OM
PALCI6R6-35C
PALC16R6-35C
PALCI6R6-40M
PALCI6R6-40M
PALCI6R6L-35C
PALCI6R6-40M
PALC16R8L-35
PALCI6R8-40M
PALC16R8-25C
PALCI6R8-25C
PALCI6R8-30M
PALCI6R8-30M
PALCI6R8-20M
PALC16R8-35C
PALCI6R8-35C
PALCI6R8-40M
PALCI6R8-40M
PALC16R8L-35
PALCI6R8-40M
PALC22VIOD-7C
PAL22VIOC-7C
PAL22VIOC-1O
PALC22VIOD-IOC
PAL22VIOC-lOC
PAL22VlOC-15M
PAL22VIOC-15MB
PALC22VIO-20MB
PALC22VlO-25MB
PALC22VIO-30MB
PALC22VlOD-15C
PAL22VlOC-12C
PALC22VIO-25C
PALC22VIOL-25C
PALC22VIO-40MB
PALC22VIO-30MB
PALC22VIO-20C
PALC22VlO-25C
PAL22VIOAC
PAL22VlOAM
PAL22VIOC
PAL22VlOM
PALC22VlO
PALC22VlO
PALCEl6V8H -15C
PALCEl6V8H -15C
PALCEI6V8H-20/B
PALCEl6V8H -20/B
PALCEI6V8H-25/B
PALCEI6V8H-25C
PALCE22VIOH -15C
PALCE22VlOH -25/B
PALCE22VlOH - 25C
PALCE22VlOH - 25C
PALCE22VlOH - 25C
PALCE22VlOQ-25C
PALCE22VI0H-30/B
PALCE6lOH-15
PALCE61OH-25
CYPRESS
PALC22VlOL-25C
PALC22VIO-30M
PALC22VlO-35C
PALC22VIO-40M
PALC22VlO-35C
PALC22VIOL-35C
PLDC18G8-12C
PLDCI8G8-15C
PLDC18G8-15MB
PLDC18G8-20MB
PLDC18G8-20MB
PLDC18G8-20C
PALC22VIOB-15C
PALC22VIO-25MB
PALC22VlOL-25C
PALC22VIO-25C
PALC22VIOL-25C
PALC22VIOL-25C
PALC22VlO-30MB
PLD61O-15C
PLD610-25C
ANALOGDEV
PREFIX:ADSP
SUFFIX:883B
SUFFIX:D
SUFFIX:E
SUFFIX:F
SUFFIX:G
lOlOA
1010J
I010K
10lOS
1010T
7C901-27M
7C901-32M
CYPRESS
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:F
SUFFIX:G
7C510-65C+
7C510-75C+
7C510-75C+
7C5lO-75M+
7C51O-75M+
7C91O-32M
290lCM
AT&T
7C116-2O
7C116-25
7C166-10
7C166-12
7C166-15
7C166-2O
7CI66-25
7C185-lO
7C185-12
7C185-15
7C185-20
7C185-25
7C183-25
7C183-35
7C183-45
7C194-15
7C194-15
7C194-2O
7C194-25
7C199-12
7C199-15
7C199-2O
7C199-25
7C157-2O
CYPRESS
6116A-20C
6116A-25C
W166-10C
W166-12C
7Cl66-15C
7CI66-20C
7CI66-25C
W185-10C
7C185-12C
7Cl85-15C
7C185-20C
7CI85-25C
7C183-25C
7C183-35C
7C183-45C
W194-12C
W194-15C
7B194-20C
7Cl94-25C
7B199-12C
W199-15C
W199-20C
7CI99-25C
7C157A-18C
AMD
1-19
AT&T
7C157-2O
7C157-24
7C157-33
CYPRESS
7C157A-20C
7C157A-24C
7C157A-33C
ATMEL
PREFIX:AT
28HC191!L
28HC291!L
28HC642
22VlO
22VIO-15
CYPRESS
PREFIX:CY
7C292A
7C293A
7C261
PALC22VI0
PALC22VlOB
DALLAS
PREFIX:DS
2009
20lO
2011
CYPRESS
PREFIX:CY
7C420-PC
7C424-PC
7C428-PC
DENSEPAK
PREFIX:DPS
1027-25C
1027-25C
1027-35C
1027-35C
1027-45C
1027-55C
16X17-25C
16XI7-25C
16X17-35C
16X17-35C
16X17-45C
16X17-45C
16X17-55C
6432-45C
6432-55C
6432-55C
8M624-lOOC
8M624-85C
8M656-35C
8M656-70C
CYPRESS
PREFIX:CYM
1621HD-25C
16IHD-25C
1621HD-30C
162IHD-35C
162IHD-45C
1621HD-55C
1611HV-25C
1611HV-25C
1611HV-35C
1611HV-35C
1611HV-45C
1611HV-45C
161iHV-55C
1830HD-45C
1830HD-55C
1830HD-55C
1623HD-85C
1623HD-lOOC
1610HD-35C
1610HD-70C
EDI
PREFIX:ED
816HI6C-25
816H16C-35
816H16C-45
8464C-45
8F32256CXXMZC
8F3264CXXMZC
8F8512CXXBC
8F8512LPXXB6C
8F8512PXXB6C
8M16256C-25C9C
8M16256C-30C9C
8M16256C- 35C9C
8MI6256C-45C9C
8M16256C-55C9C
8M16256C-70C9C
8M16256C- 30C9MB
8M16256C-35C9MB
8M16256C-45C9MB
8M16256C-55C9MB
CYPRESS
PREFIX:CYM
1611HV-25C
1611HV-35C
1611HV-45C
7C194-45
M1841PZ-XXC
M183IPZ-XXC
1465PC-XXC
1465LPD-XXC
1465LPD-XXC
164IHD-25C
1641HD-3OC
164IHD-35C
1641HD-45C
1641HD-55C
1641HD-55C
1641HD-30MB
164IHD-35MB
1641HD-45MB
164IHD-55MB
o
u..
:!:
~
ry
'1= CYPRf.SS
Product Line Cross Reference
_ . F SEMICONDUCTOR
EDI
8M16256C-70C9MB
SM32256CXXC6B
8M32256CXXC6B
SM3264CXXC6B
8M3264CXXC6C
8M8128C-100
8M8128C-looCB
8M8128C-60CB
8M8128C-60CC
8M8128C-70
8M8512CXXC6B
8M8512CXXC6C
8M8512CXXM6C
8M8512LPXXC6B
8M8512PXXC6B
H816H16C-25CCH816H16C-35CCH816H16C-45CCH816HI6C-55CCH816H64C-35CC
H816H64C-35MHR
H816H64C-45CC
H816H64C-45MHR
H816H64C-55CC
H816H64C- 55MHR
H816H64C-70CC
H816H64C-70MHR
CYPRESS
1641HD-55MB
M1S40HD-XXMB
MI840HD-XXC
M1830HD-XXMB
M1830HD-XXC
1421HD-85C
1420HD-55MB
1420HD-55MB
1420HD-55C
1421HD-70C
1466HD-XXMB
1466HD-XXC
1464PD-XXC
1466LHD-XXMB
1466LHD-XXMB
161IHV-25C
161IHV-35C
1611HV-45C
1611HV-45C
162IHD-35C
1621HD-35MB
1621HD-45C
162IHD-45MB
1621HD-45C
162IHD-45MB
1621HD-45C
162IHD-45MB
FAIRCHILD
PREFIX:F
SUFFIX:D
SUFFIX:F
SUFFlX:L
SUFFlX:P
SUFFIX:QB
1ooE422-5
100E422-7
10E422-7
100E474-7
1OE474-7
16OOC45
16OOC55
1600C70
16ooM55
1600M70
1601C55
1620C35
1620M35
1620M45
1621C25
1622C25
1622C35
1622M35
1622M45
16L8A
16L8A
16P8A
16P8A
16R4A
16R4A
16R6A
CYPRESS
PREFIX:CY
SUFFIX:D
SUFFlX:F
SUFFlX:L
SUFFIX:P
SUFFIX:B
l00E422-5C
lOOE422-7C
lOE422-7C
lOOE474-7C
lOE474-7C
7C187-45C
7C187-45C
7C187-45C
7C187-45M
7C187-45M
7C187-45C
7C164-35C+
7C164-35M
7C164-45M
7C164-25C+
7C166-25C+
7C166-35C+
7C166-35M
7C166-45M
PALC16L8-20M
PALC16L8-25C
PALC16L8-20M
PALC16L8-25CPALC16R4-20M
PALC16R4-25C
PALC16R6-20M
FAIRCHILD
16R6A
16R8A
16R8A
16RP4A
16RP4A
16RP6A
16RP6A
16RP8A
16RP8A
3341AC
3341C
54F189
54F219
54F413
54S189M
74AC1010-40
74F189
74F219
74F413
74LS189
74S189
93422AC
93422AM
93422C
93422M
93475C
93L422AC
93L422AM
93L422C
93L422M
93Z451AC
93Z451AM
93Z451C
93Z451M
93Z511C
93Z511M
93Z565AC
93Z565AM
93Z565C
93Z565M
93Z611C
93Z611M
93Z665C
93Z665M
93Z667C
93Z667M
CYPRESS
PALCI6R6-25C
PALCI6R8-20M
PALCI6R8-25C
PALC16R4-20M
PALC16R4-25C
PALC16R6-20M
PALC16R6-25C
PALC16R8-20M
PALCI6R8-25C
3341C
3341C
7CI89-25M7C190-25M7C401-15M
54S189M
7C510-45C
7C189-25C7C190-25C7C401-15C
27LS03C
74S189C
93422AC
93422AM
93422C
93422M
2149-45C
93L422AC
93L422AM
93L422C
93L422M
7C282-30C
7C282-45M
7C282-30C
7C282-45M
7C292-35C
7C292-50M
7C264-45C
7C264-55M
7C264-55C
7C264-55M
7C292-25C
7C291A-30M
7C264-35C
7C264-45M
7C263-35C
7C261-45M
FUJITSU
PREFIX:MB
PREFlX:MBM
SUFFIX:F
SUFFIX:M
SUFFlX:Z
loo422A-5C
100422A-7C
100422AC
lO0470A-7
100470A-1O
100470A-15
100474A-3C
100474A-5C
100474A-7C
CYPRESS
PREFIX:CY
PREFIX:CY
SUFFIX:F
SUFFIX:P
SUFFlX:D
100E422-5C
100E422L-7C
looE422L-7C
l00E470-7C
lOOE470-7C
100E470-7C
lOOE474-3.5C
100E474-5C
lOOE474L-7C
FUJTISU
100474AC
100484A-1O
100484A-8
100484-15
1ooC494-15
101494-7
101494-8
101A484-5
10422A-5C
lO422A-7C
10422AC
10470A-7
10470A-lOC
10470A-15C
10470A-2OC
10474A-3C
10474A-5C
10474A-7C
10474AC
10484-15
10484A-8
10484A-1O
10484A-5
10494-7
1OC494-15
2147H-35
2147H-45
2147H-55
2147H-70
2148-55L
2148-70L
2149-45
2149-55L
2149-70L
27256-17C
27256-20C
27256-25C
27256A-15C
27256A-17C
27256A-20C
27256A-25C
27256H-lOC
27256H-12C
2764-20C
2764-25C
2764-30C
27C512-15C
27C512-17C
27C512-20C
27C512-25C
27C512-3OC
27C64-20C
27C64-25C
27C64-30C
7132E
7132E-SK
7132E-W
7132H
7132H-SK
7132Y
7132Y-SK
7138E
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
, = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
sorc only
t
:j: = 32-pin LCC crosses to the 7C198M
1-20
CYPRESS
1ooE474L-7C
100E484L-7C
100E484L-7C
100E484L-7C
100E494L-12C
101E494-7
101E494-8
101E484-5C
1OE422-5C
1OE422L-7C
1OE422L-7C
1OE470-7C
1OE470-7C
1OE470-7C
1OE470-7C
10E474-4C
lOE474-5C
1OE474L-7C
lOE474L-7C
10E484L-7C
lOE484L-7C
lOE484L-7C
1OE484-5C
lOE494-7C
10E494L-12C
2147-35C
2147-45C
2147-55C
2147-55C
21L4S-55C
21L48-55C
2149-45C
21L49-55C
21L49-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C266-55C
7C266-55C
7C266-55C
7C286-55C
7C286-55C
7C286-55C
7C286-55C
7C286-55C
7C266-55C
7C266-55C
7C266-55C
7C282-45C
7C281-45C
7C282-45M
7C282-45C
7C281-45C
7C282-30C
7C281-30C
7C292-50C
...:=...
.--':~
_=
- , CYPRESS
SEMICONDUCjOR
Product Line Cross Reference
FUJTISU
CYPRESS
HARRIS
CYPRESS
HITACHI
CYPRESS
7138E-SK
7138E-W
713SH
713SH-SK
7138Y
7138Y-SK
7144E
7144E-W
7144H
7144Y
7226RA-20
7226RA-25
7232RA-20
7232RA-25
7238RA-20
7238RA-25
8128- 10
8128-15
8167-70W
8167A-55
8167A-70
8168-55
8168-70
8168-70W
8171-55
8171-70
81C67-35
81C67-45
81C67-55W
81C68-45
81C68-55W
81C71-45
81C71-55
81C74-25
81C74-35
81C74-45
81C75-25
81C75-35
81C78-45
81C78-55
81C81A-35
8JC81A-45
81C84A-35
81C84A-45
81C86-70
8287-35
8287-45
8464L-100
8464L-70
7C291-50C
7C292-50M
7C292-35C
7C291-35C
7C292-35C
7C29J -35C
7C264-55C
7C264-55M
7C264-55C
7C264-45C
7C225-30C
7C225-30C
7C235-30C
7C235-30C
7C245-25C
7C245-35C
7C128A-55C
7C128A-55C
7C167A-45M
7C167A-45C
7C167A-45C
7C168A-45C
7C168A-45C
7C16SA-45M
7C187-45C
7C187-45C
7C167A-35C
7C167A-45C
7C167A-45M
7CJ68A-45C
7CI68A-45M+
7C187-45C
7C187-45C
7CI64-25C
7CI64-·35C+
7C164-45C
7C166-25C
7C166-35C
7C186-45C
7C186-55C
7C197-35
7CJ97-45
7C194-35
7C194-45
7C192-45C+
7C199-35
7CJ99-45
7CJ85-55C+
7CJ85-45C+
16RC4-8
16RC4-9
J6RC6-5
16RC6-S
16RC6-9
J6RCS-5
16RC8-8
16RC8-9
6-76161-2
6-76161-5
6-76161A-2
6-76161A-5
6-76161B-5
6-7681-5
6-7681A-5
65162-5
65162-8
65162-9
65162B-5
65162B-8
65162B-9
65162C-8
65162C-9
65162S-5
65162S-9
65262-8
65262-9
65262B-8
65252B-9
65262C-9
65262S-9
76161-2
76161A-2
76161A-5
76161B-5
76641-2
76641-5
76641A-5
7681-2
76S1-5
7681A-5
PALCI6R4-40M
PALCI6R4-40M
PALCI6R6L- 35C
PALCJ6R6-40M
PALCI6R6-40M
PALCI6RSL-35C
PALCI6R8-40M
PALC16RS-40M
7C291-50M
7C291-50C
7C291-50M
7C291-50C
7C291-35C
7C281-45C
7C281-45C
61J6A-55C*
61J6A-55M*
6116A-55M*
6116A-55C*
6116A-55M*
6116A-55M*
6116A-55M*
6116A-55M*
6116A-55C*
6116A-55M*
7CI67A-45M*
7CI67A-45M*
7CI67A-45M*
7CI67A-45M*
7CI67A-45M*
7CI67A-45M*
7C292-50M
7C292-50M
7C292-50C
7C292-35C
7C264-55M
7C264-55C
7C264-45C
7C282-45M
7C282-45C
7C282-45C
25089
250S9S
25169S
27256G-25C
27256G-30C
27512G-25C
27512G-30C
27C256G-17C
27C256G-20C
27C256G- 25C
27C256G-30C
27C256GHG-70C
27C256GHG-85C
4847
4847-2
4847-3
6116ALS-12
6116ALS-15
6116ALS-20
6116AS-12
61J6AS-15
6116AS-20
6J47
6147-3
6147H-35
6147H-45
6147H-55
6147HL-35
6147HL-45
6147HL-55
6148
6148H-35
6148H-45
6148H-55
6148HL-35
6148HL-45
6148HL-55
6148L
6167-6
6167-8
6167H-55
6167H-70
6167HL-55
6J67HL-70
6167L-6
6167L-8
6168H-45
6168H-55
6168H-70
6168HL-45
6168HL-55
6168HL-70
6207P-35
6207P-45
6208P-35
6208P-45
62256
624256-35C
624256-45C
624257-35C
624257-45C
6264-10
7C282-45C
7C282-45C
7C292-50C
7C274-55C
7C274-55C
7C286-70C
7C2S6-70C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
7C274-55C
2147-55C
2147-45C
2147-55C
6116A-55C*
6116A-55C*
61J6A-55C*
6116A-55C+
6116A-55C+
6J16A-55C+
7CI47-45C*
7CI47-45C*
7CI47-35C+
7CJ47-45C+
7CJ47-45C+
7CI47-35C*
7CI47-45C*
7CI47-55C*
7C148-45C
21L48-35C
7CI48-45C+
7C14845C+
21L48-35C*
7CI48-45C*
7CI48-45C*
7CI4S-45C*
7CI67A-45C+
7C167A-45C+
7CJ67A-45C
7C167A-45C
7CI67A-45C*
7CI67A-45C*
7C167A-45C*
7C167A-45C*
7CI68A-45C+
7C168A-45C+
7C168A-45C+
7C168A-45C'
7C168A -45C*
7C168A-45C'
7C197-35
7C197-45
7C194-35
7C194-45
7C198*
7C106-35C
7C106-45C
7C102-35C
7C102-45C
7C186-55C+
HARRIS
CYPRESS
PREFIX:HM
PREFIX:HPL
SUFFIX:8
PREFIX: 1
PREFIX:9
PREFIX:4
PREFIX:3
16LC8-5
16LC8-8
16LC8-9
16RC4-5
PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
PALC16L8L-35C
PALC16L8-40M
PALCI6L8-40M
PALCI6R4L- 35C
HITACHI
CYPRESS
PREFIX:HM
PREFIX:HN
SUFFIX:CG
SUFFIX:G
SUFFIX:P
lOO422C
100474-10C
100474-8C
100474C
100494-10
100494-12
101494-10
101494-12
10422C
10474-lOC
10474-8C
J0474C
10494-10
10494-12
PREFIX:CY
PREFIX:CY
SUFFIX:L
SUFFIX:D
SUFFIX:P
lOOE422L-7C
l00E474L-7C
100E474L-7C
lOOE474L-7C
lOIE494 - IOC
100E494L-12C
101E494-lOC
101E494L-10C
lOE422L-7C
100E474L-7C
JOE474L-7C
lOE474L-7C
lOE494-10C
10E494L-12C
1-21
0
LL
Z
---=-
~;~...b
Product Line Cross Reference
='=CYPRESS
-
JF
SEMICONDUCTOR
HITACHI
CYPRESS
IDT
CYPRESS
IDT
CYPRESS
6264-12
6264-15
6267-35
6267-45
6268-25
6268-35
62832H
62832
6287-45
6287-55
6287-70
6288-35
6288-45
6288-55
62A168-25
62A168-35
62A168-45
6707-20
6707-25
6707A-15
6707A-20
6707A-25
6708-20
6708-25
6708A-15
6708A-20
6708A-25
6709-20
6709-25
6709A-15
6709A-20
6709A-25
6716-25
6716-30
6787-30
6788-25
6788-30
6788HA-12
6789HA-12
7CI86-55C+
7CI86-55C+
7CI67A-35C+
7C167A-45C
7C168A-25C
7C168A-35C
7C199+
7C199
7C187-45C
7C187-45C
7C187-45C
7CI64-35C
7C164-45C
7C164-45C
7C183-25C
7C183-35C
7C183-45C
7C197-20C
7C197-25C
7B197-15C
7C197-20C
7C197-25C
7C194-20C
7C194-25C
7B194-15C
7C194-20C
7C194-25C
7C195-20C
7C195-25C
7B195-15C
7C195-20C
7C195-25C
7C128A-25C
7C128A-25C
7C187-25C
7Cl64-25C
7C164-25C
7Bl64-12C
7B166-12C
IDT
CYPRESS
PREFIX:lDT
PREFIX:lDT
SUFF1X:B
SUFF1X:D
SUFFIX:F
SUFFIX:L
SUFFIX:P
100484S7
100494S8
100494S1O
101484S7
101494S7
101494S8
101494S1O
10484S7
10494S7
10494S8
10494S1O
39COICB
39C01CC
39C01CM
PREFIX:CY
PREFIX:CYM
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFTX:L
SUFFTX:P
100E484L-7C
101E494-8C
101E494-lOC
100E484L-7C
101E494-7C
lOIE494-8C
101E494-lOC
1OE484L-7C
lOE494-7C
lOE494-8C
10E494-lOC
7C901-32M+
2901CC+
2901CM+
39COlDB
39COlDC
39C09A
39C09AB
39ClOB
39ClOBB
39CI1A
39CI1AB
49C401
49C401
6I16SA120B
6116SA150B
61 I 6SA25
6I16SA35
6116SA35
6116SA35B
6116SA35B
6116SA45
6116SA45
6116SA45B
6116SA45B
61 I6SA55B
6116SA55B
6116SA70B
6116SA90B
6I298SA25
61298SA25B
6I298SA35
6I298SA35B
6I298SA45
6I298SA45B
61298SA55
61298SA55B
61298SA70B
6I67SAI00B
6167SA25
6167SA35
6I67SA35B
6167SA4SB
6I67SA55B
6I67SA70B
6167SA85B
6168SAlOOB
6168SAI5
6168SA20
6168SA25
6168SA25B
6I68SA35
6168SA35B
6168SA45B
6168SA55B
6I68SA70B
6I68SA90B
6197SA25
6I97SA35
6I97SA35B
61 97SA45B
6I97SA55
6I97SA55B
6198SA15
6I98SA19
6198SA20
7C901-27M+
7C901-23C+
7C909-40C+
7C909-40M+
7C910-50C7C91O-51M
7C911-40C+
7C911-40M+
7C9101-40C7C9101-45M 7C128A-55MB
6116A-55MB
7C128A-25C
7C128A-35C
6116A-35C
7C128A-35MB
6116A-35MB
7C128A-45C
6I16A-45C
7C128A-45MB
6116A-45MB
7C128A-55MB
6116A-55MB
7C128A-55MB
6116A-55MB
7C196-25C
7C196-25MB
7C196-35C
7C196-35MB
7C196-45C
7C196-45MB
7C196-45
7C196-45MB
7C196-45MB
7C167A-45MB
7C167A-25C
7C167A-35C
7C167A-35MB
7C167A-45MB
7C167A-45MB
7C167A-45MB
7C167A-45MB
7C168A-45MB
7C168A-15C
7C168A-20C
7C168A-25C
7C168A-25MB
7C168A-35C
7C168A-35MB
7C168A-45MB
7C168A-45MB
7C168A-45MB
7C168A-45MB
7C170A-25C
7C170A-35C
7C170A-35MB
7C170A-45MB
7C170A-45C
7C170A-45MB
7C166-15C
7C166-15C
7C166-20C
6198SA20B
6198SAZ5
6I98SA25B
6198SA30
6I98SA30B
6198SA45
6I98SA45B
6198SA55B
6I98SA70B
6198SA85B
6lB298S12
61B298S15
6lB298S20
6IB298S15B
61B298S20B
7005S35
7005S35
7005S45B
71024LA25
71024LA30B
71024LA35
71024LA35B
71024LA45
71024LA45B
71024LA55
71024LA55B
71024SA25
71024SA30B
71024SA35
71024SA35B
71024SA45
71024SA45B
7I024SA55
71024SA55B
71024SA70
71024SA90
7I028LA25
7I028LA30B
71028LA35
71028LA35B
71028LA45
71028LA45B
71028LA55
71028LA55B
71028SAZ5
71028SA30B
71028SA35
71028SA35B
71028SA45
71028SA45B
71028SA55
71028SA55B
71256SAlOOB
7l256SA25
7I256SA30
7I256SA30B
7I256SA35
71256SA35B
71256SA45
71256SA45B
7I256SA55
71256SA55B
7CI66-AZOMB
7C166-25C
7C166-A25MB
7C166-25C
7C166-A25MB
7C166-45C
7C166-A45MB
7C166-A45MB
7C166-A45MB
7C166-A45MB
7B195-12C
7B195-15C
7C195-20C
?B195-15MB
7B195-20MB
7B144-25C
7B144-35C
7B144-35MB
7CI08-25C
7C108-25MB
7CI08-35C
7CI08-35MB
7C108-45C
7CI08-45MB
7C108-55C
7C108-45MB
7CIOS-25C
7C108-25MB
7C108-35C
7ClOS-35MB
7C10S-45C
7CI08-45MB
7C108-55C
7C108-45MB
7C108-45
7C108-45
7C106--25C
7C106-25MB
7Cl06-35C
7C106-35MB
7C106-45C
7C106-45MB
7C106-45C
7CI06-45MB
7C106-25C
7C106-25MB
7C106-3SC
7CI06-35MB
7CI06-45C
7CI06-45MB
7C106-45C
7CI06-45MB
7C198-55MB
7C198-25C
7C198-25C
7C!98-25MB
7C198-35C
7C198-35MB
7C198-45C
7C198-45MB
7C198-55C
7C198-55MB
Note: Unless otheIWise noted, product meets all performance specs and is within 10 mA on Tcc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
, = meets all performance specs except 2V data retention-may not meet Icc or TSB
functionally equivalent
t
sorc only
:} = 32-pin LCC crosses to the 7C198M
1-22
-.
~
---..."..
=====-~PRESS
~F
SEMICONDUC'TOR
IDT
71256SA70
71256SA70B
71256SA85B
71257SA25
71257SA25B
71257SA35
71257SA35B
71257SA45
71257SA45B
71257SA55
71257SA55B
71257SA70B
71258SA25
71258SA25B
71258SA35
71258SA35B
71258SA45
71258SA45B
71258SA55
71258SA55B
71258SA70B
71281SA25
71281SA25B
71281SA35
71281SA35B
71281SA45
71281SA45B
71281SA55
71281SA55B
71281SA70B
71282SA
71282SA
71282SA
71282SA
71282SA
71282SA
71282SA
71282SA
71282SA
7130LA25
7130LA25J52
7130LA251.52
7130LA30
7130LA30J52
7130LA301.52
7130LA35
7130LA35B
7130LA35J52
7130LA351.52
7130LA351.52B
7130LA45
7130LA45B
7130LA45J52
7130LA451.52
7130LA451.52B
7130LA55
7130LA55B
7130LA55J52
7130LA551.52
7130LA551.52B
7130LA70
7130LA70B
CYPRESS
7C198-55C
7C198-55MB
7C198-55MB
7C197-25C
7C197-25MB
7C197-35C
7C197-35MB
7C197-45C
7C197-45MB
7C197-45C
7C197-45MB
7C197-45MB
7C194-25C
7C194-25MB
7C194-35C
7C194-35MB
7C194-45C
7C194-45MB
7C194-45C
7C194-45MB
7C194-45MB
7C191-25C
7C191-25MB
7C191-35C
7C191-35MB
7C191-45C
7C191-45MB
7C191-45C
7C191-45MB
7C191-45MB
7C192-25C
7C192-25MB
7C192-35C
7C192-35MB
7C192-45C
7C192-45MB
7C192-45C
7C192-45MB
7C192-45MB
7C130-25C
7C131-25JC
7C131-25LC
7C130-30C
7C131-3OJC
7C131-30LC
7C130-35C
7C130-35MB
7C131-35JC
7C131-35LC
7C130-35LMB
7C130-45C
7C131-45MB
7C131-45JC
7C131-45LC
7C130-45LMB
7C130-55C
7C131-55MB
7C131-55JC
7C131-55LC
7C130-55LMB
7C130-55C
7C131-55MB
Product Line Cross Reference
lDT
7130LA7OJ52
7130LA701.52
7130LA701.52B
7130LA90J52
7130LA901.52
7130LA901.52B
7130SAl00
7130SAl00B
7130SAl001.52
7130SAl001.52B
7130SA25
7130SA251.52
7130SA30
7130SA301.52
7130SA25J52
7130SA30J52
7130SA35
7130SA35B
7130SA35J52
7130SA351.52
7130SA351.52B
7130SA45
7130SA45B
7130SA45J52
7130SA451.52
7130SA451.52B
7130SA55
7130SA55B
7130SA55J52
7130SA551.52
7130SA551.52B
7130SA70
7130SA70B
7130SA7OJ52
7130SA701.52
7130SA701.52B
7130SA90
7130SA90B
7130SA90J52
7130SA901.52
7130SA901.52B
71321LA25
71321LA30
71321LA35
71321LA35B
71321LA45
71321LA45B
71321LA55
71321LA55B
71321LA70
71321LA70B
71321LA9O
71321LA9OB
71321SA25
71321SA30
71321SA35
71321SA35B
71321SA45
71321SA45B
71321SA55
71321SA55B
71321SA70
CYPRESS
7C131-55JC
7C131-55LC
7C130-55LMB
7C130-55LC
7C131-55LC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55LC
7C131-55LMB
7C130-25C
7C131-25LC
7C130-25C
7C131-25LC
7C131-25JC
7C131-3OJC
7C130-35C
7C130-35MB
7C131-35JC
7C131-35LC
7C131-35LMB
7C130-45C
7C130-45MB
7C131-45JC
7C131-45LC
7C131-45LMB
7C130-55C
7C130-55M
7C131-55JC
7C131-55LC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55JC
7C131-55LC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55JC
7C131-55LC
7C131-55LMB
7C136-25C
7C136-30C
7C136-35C
7C136-35MB
7C136-45C
7C136-45MB
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C136-25C
7C136-30C
7C136-35C
7C136-35MB
7C136-45C
7C136-45MB
7C136-55C
7C136-55MB
7C136-55C
1-23
lDT
71321SA70B
71321SA90
71321SA90B
7132LA25
7132LA30
7132LA35
7132LA35B
7132LA45
7132LA45B
7132LA55
7132LA55B
7132LA70
7132LA70B
7132LA90
7132LA90B
7132LAlOO
7132LAlOOB
7132LA120B
7132SAI00
7132SAlOOB
7132SA120B
7132SA25
7132SA30
7132SA35
7132SA35B
7132SA45
7132SA45B
7132SA55B
7132SA55
7132SA70
7132SA70B
7132SA90
7132SA90B
71342S35
71342S35
71342S45B
7134S35
7134S35
7134S35J52
7134S35J52
7134S351.52
7134S351.52
7134S45B
7134S451.52B
7140LA25
7140LA25J52
7140LA251.52
7140LA30
7140LA3OJ52
7140LA301.52
7140LA35
7140LA35B
7140LA35J52
7140LA351.52
7140LA351.52B
7140LA45
7140LA45B
7140LA45J52
7140LA45L52
7140LA45L52B
7140LA55
7140LA55B
CYPRESS
7C136-55MB
7C136-55C
7C136-55MB
7CI32-25C
7C132-30C
7C132-35C
7C132-35MB
7C132-45C
7C132-45MB
7C132-55C*
7C132-55MB
7C132-55C'
7C132-55M*
7C132-55C'
7C132-55M*
7C132-55C'
7C132-55M*
7C132-55M*
7C132-55C+
7C132-55M+
7C132-55M+
7C132-25C
7C132-30C
7C132-35C
7C132-35MB
7C132-45C
7C132-45MB
7C132-55MB
7C132-55C+
7C132-55C+
7C132-55M+
7C132-55C+
7C132-55M+
7C1342-25C
7C1342-35C
7C1342-35MB
7B134-25C
7B134-35C
7B135-25JC
7B135-35JC
7B135-25LC
7B135-35LC
7B134-35MB
7B135-35LMB
7C140-25C
7C141-25JC
7C141-25LC
7C140-30C
7C141-3OJC
7C141-30LC
7Cl40-35C
7Cl40-35MB
7C141-35JC
7C141-35LC
7C141-35LMB
7Cl40-45C
7Cl40-45MB
7C141-45JC
7C141-45LC
7C141-45LMB
7Cl40-55C
7Cl40-55MB
o
u.
~
~
.-.~
_=
-=-F CYPRESS
SEMICONDUCTOR
IDT
7140LA55J52
7140LA55L52
7140LA55L52B
7140LA70
7140LA70B
7140LA7OJ52
7140LA70L52
7140LA70L52B
7140LA9OJ52
7140LA90L52
7140LA90L52B
7140SA100
7140SAlOOB
7140SA100L52
7140SAIOOL52B
7140SA25
7140SA25J52
7140SA25L52
7140SA30
7140SA30J52
7140SA30L52
7140SA35
7140SA35B
7140SA35J52
7140SA35L52
7140SA35L52B
7140SA45
7140SA45B
7140SA45J52
7140SA45L52
7140SA45L52B
7140SA55
7140SA55B
7140SA55J52
7140SA55L52
7140SA55L52B
7140SA70
7140SA70B
7140SA7OJ52
7140SA70L52
7140SA70L52B
7140SA90
7140SA90B
7140SA90J52
7140SA90L52
7140SA90L52B
71421LA25
71421LA30
71421LA35
71421LA35B
71421LA45
71421LA45B
71421LA55
71421LA55B
71421LA70
71421LA70B
71421LA90
71421LA90B
71421SA25
71421SA30
714215A35
714215A35B
CYPRESS
7C141-55JC
7C141-55LC
7C141-55LMB
7C140-55C
7C140-55MB
7C141-55JC
7C141-55LC
7C141-55LMB
7C141-55JC
7C141-55LC
7C141-55LMB
7C140-55C
7C140-55MB
7C141-55C
7C141-55MB
7C140-25C
7C141-25JC
7C141-25LC
7C140-30C
7C141-30JC
7C141-30LC
7C140-35C
7C140-35MB
7C141-35JC
7C141-35LC
7C141-35LMB
7C140-45C
7C140-45MB
7C141-45JC
7C141-45LC
7C141-45LMB
7C140-55C
7C140-55MB
7C141-55JC
7C141-55LC
7C141-55LMB
7C140-55C
7C140-55MB
7C141-55JC
7C141-55LC
7C141-55LMB
7C140-55C
7C140-55MB
7C141-55JC
7C141-55LC
7C141-55LMB
7C146-25C
7C146-30C
7C146-35C
7C146-35MB
7C146-45C
7C146-45MB
7C146-55C
7C146-55MB
7C146-55C
7C146-55MB
7C146-55C
7C146-55MB
7C146-25C
7C146-30C
7C146-35C
7C146-35MB
Product Line Cross Reference
IDT
71421SA45
71421SA45B
71421SA55
71421SA55B
71421SA70
71421SA70B
71421SA90
71421SA90B
7142LA25
7142LA30
7142LA35
7142LA35B
7142LA45
7142LA45B
7142LA55
7142LA55B
7142LA70
7142LA70B
7142SA25
7142SA30
7142SA35
7142SA35B
7142SA45
7142SA45B
7142SA55
7142SA55B
7142SA70
7142SA70B
7164SA20
7164SA20P
7164SA25
7164SA25B
7164SA25P
7164SA25PB
7164SA30
7164SA30B
7164SA30P
7164SA30PB
7164SA35
7164SA35B
7164SA35P
7164SA35PB
7164SA45
7164SA45B
7164SA45P
7164SA45PB
7164SA55B
7164SA55BP
7164SA70B
7164SA70BP
7164SA85B
7164SA85BP
71681SAlOOB
71681SA25
71681SA25B
716815A35
716815A35B
716815A45
716815A45B
71681SA55B
716815A70B
716815A85B
CYPRESS
7C146-45C
7C146-45MB
7C146-55C
7C146-55MB
7C146-55C
7C146-55MB
7C146-55C
7C146-55MB
7C142-25C
7C142-30C
7C142-35C
7C142-35MB
7C142-45C
7C142-45MB
7C142-55C
7C142-55MB
7C142-55C
7C142-55MB
7C142-25C
7C142-30C
7C142-35C
7C142-35MB
7C142-45C
7C142-45MB
7C142-55C
7C142-55MB
7C142-55C
7C142-55MB
7C185-20C
7C186-20C
7C185-25C
7C185A-25MB
7C186-25C
7C186A-25MB
7C185-25C
7C185A-25MB
7C186-25C
7C186A-25MB
7C185-35C
7C185A-35MB
7C186-35C
7C186A-35MB
7C185-45C
7C185A-45MB
7C186-45C
7C186A-45MB
7C185A-55MB
7C185A-55MB
7C186A-55MB
7C186A-55MB
7C185A-55MB
7C185A-55MB
7C170A-45MB
7C170A-25C
7C170A-25MB
7C170A-35C
7C170A-35MB
7C170A-45C
7C170A-45MB
7C170A-45MB
7C170A-45MB
7C170A-45MB
IDT
71682SAlOOB
71682SA25
71682SA25B
71682SA35
71682SA35B
71682SA45
71682SA45B
71682SA55B
71682SA70B
71682SA85B
7187SA15
7187SA20
7187SA25
7187SA25B
7187SA30
7187SA30B
7187SA35
7187SA35B
7187SA45
7187SA45B
7187SA55B
7187SA70B
7187SA85B
7188SA15
7188SA20
7188SA20B
7188SA25
7188SA25B
7188SA30
7188SA35
7188SA35B
7188SA45
7188SA45B
7188SA55B
7188SA70B
7188SA85B
71981S35
71981S35B
71981S45
71981S45B
71981S55
71981S55B
71981S70
71981S70B
71981S85B
71982S35
71982S35B
71982S45
71982S45B
71982555
71982555B
71982570
71982S70B
71982S85B
7198S35
7198535B
7198545
7198545B
7198555
7198555B
7198570
7198570B
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* -
t
:j: =
meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
SOlC only
32-pin LCC crosses to the 7C198M
1-24
CYPRESS
7Cl72A-45MB
7Cl72A-25C
7Cl72A-25MB
7Cl72A-35C
7Cl72A-35MB
7Cl72A-45C
7Cl72A-45MB
7Cl72A-45MB
7Cl72A-45MB
7Cl72A-45MB
7C187-15C
7C187-20C
7C187-25C
7C187A-25MB
7C187-25C
7C187A-25MB
7C187-35C
7C187A-35MB
7C187-45C
7C187A-45MB
7C187A-45MB
7C187A-45MB
7C187A-45MB
7C164-15C
7C164-20C
7C164A-20MB
7C164-25C
7Cl64A-25MB
7C164-25C
7C164-35C
7C164A-35MB
7C164-45C
7C164A-45MB
7C164A-45MB
7C164A-45MB
7C164A-45MB
7C161-35C
7C161A-35M
7C161-45C
7C161A-45M
7C161-45C
7C161A-45M
7C161-45C
7C161A-45M
7C161A-45M
7C162-35C
7C162A-35M
7C162-45C
7C162A-45M
7C162-45C
7C162A-45M
7C162-45C
7C162A-45M
7C162A-45M
7C166-35C
7C166A-35M
7C166-45C
7C166A-45M
7C166-45C
7C166A-45M
7C166-45C
7C166A-45M
Product Line Cross Reference
IDT
7198S85B
71B256S12
71B256S15
71B256S20
71B256S20B
71B258S12
71B258S15
71B258S20
71B258S15B
71B258S20B
7201LA120
7201LA120B
7201LA20
7201LA2OT
7201LA25
7201LA25T
7201LA30B
7201LA3OTB
7201LA35
7201LA35T
7201LA40B
7201LA4OTB
7201LASO
7201LASOB
7201LASOT
7201LASOTB
7201LA65
7201LA65B
7201LA65T
7201LA65TB
7201LABO
n01LABOB
nOlSA120
n01SA120B
7201SA2O
7201SA2OT
n01SA25
n01SA25T
7201SA30B
7201SA3OTB
7201SA35
7201SA35T
7201SA40B
7201SA4OTB
7201SASO
7201SASOB
7201SASOT
7201SASOTB
7201SA65
7201SA65B
7201SA65T
7201SA65TB
7201SA80
7201SASOB
7202LA120
7202LA120B
7202LA20
7202LA2OT
7202LA25
7202LA25T
7202LA30B
7202LA30TB
CYPRESS
7Cl66A-45M
7Bl99-12C
7B199-15C
7C199-20C
7B199-20MB
7B194-12C
7B194-15C
7C194-20C
7B194-15MB
7B194-2OMB
7C42O-65C+
7C420-65MB+
7C420-2OC
7C421-2OC
7C42O-25C
7C421-25C
7C420-30MB
7C421-30MB
7C420-30C+
7C421-30C
7C420-40MB+
7C421-40MB
7C420-40C+
7C420-40MB+
7C421-40C
7C421-40MB
7C420-65C+
7C420-65MB+
7C421-65C
7C421-65MB
7C420-65C+
7C42O-65MB+
7C420-65C
7C42O-65MB
7C42O-20C
7C421-20C
7C420-25C
7C421-25C
7C420-30MB
7C421-30MB
7C420-30C
7C421-30C
7C420-40MB
7C421-40MB
7C42O-40C
7C420-40MB
7C421-40C
7C421-40MB
7C42O-65C
7C42O-65MB
7C421-65C
7C421-65MB
7C420-65C
7C42O-65MB
7C424-65C+
7C424-65MB+
7C424-20C
7C425-2OC
7C424-25C
7C425-25C
7C424-30MB
7C425-30MB
IDT
7202LA35
7202LA35T
7202LA40B
7202LA4OTB
7202LA50
7202LA50B
7202LASOT
7202LASOTB
7202LA65
7202LA65B
7202LA65T
7202LA65TB
7202LA80
7202LA80B
7202SA120
7202SA120B
n02SA20
7202SA2OT
7202SA25
7202SA25T
7202SA30B
7202SA30TB
7202SA35
7202SA35T
7202SA40B
7202SA4OTB
7202SASO
7202SASOB
7202SASOT
7202SASOTB
7202SA65
7202SA65B
7202SA65T
7202SA65TB
n02SABO
7202SASOB
72031.20
7203120T
7203L25
7203L25B
n03L25T
n03L25TB
7203L30
7203L3OT
7203L35B
7203L35TB
7203L40
7203L4OT
7203L55B
7203L55TB
7203L65
7203L65B
7203L65T
7203L65TB
7203L80
7203L80B
7203L8OT
7203L8OTB
7203S2O
7203S2OT
7203S25
7203S25B
CYPRESS
7C424-30C+
7C425-30C
7C424-40MB+
7C425-40MB
7C424-40C+
7C424-40MB+
7C425-40C
7C425-40MB
7C424-65C+
7C424-65MB+
7C425-65C
7C425-65MB
7C424-65C+
7C424-65MB+
7C424-65C
7C424-65MB
7C424-2OC
7C425-20C
7C424-25C
7C425-25C
7C424-30MB
7C425-30MB
7C424-30C
7C425-30C
7C424-40MB
7C425-40MB
7C424-40C
7C424-40MB
7C425-40C
7C425-40MB
7C424-65C
7C424-65MB
7C425-65C
7C425-65MB
7C424-65C
7C424-65MB
7C428-20C
7C429-2OC
7C428-25C
7C428-25MB
7C429-25C
7C429-25MB
7C428-30C
7C429-30C
7C428-30MB
7C429-30MB
7C428-40C
7C429-40C
7C428-40MB
7C429-40MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C428-2OC
7C429-2OC
7C428-25C
7C428-25MB
1-25
IDT
7203S25T
7203S25TB
7203S30
n03S3OT
7203S35B
7203S35TB
7203S40
7203S4OT
7203S55B
7203S55TB
7203S65
7203S65B
7203S65T
7203S65TB
7203S80
7203S80B
7203S8OT
7203S8OTB
7204S25
7204S25T
7204S30
7204S3OT
7204S35B
7204S35TB
7204S40
7204S4OT
7204S55B
7204S55TB
7204865
7204S65B
7204S65T
7204S65TB
7204S80B
7204S8OTB
7205120
7205L25
7205L30B
7205L30B
7205L35
7205L50
7205L50B
7210-12OB
721O-200B
7210-55B
7210-65B
7210-75B
7210-85B
72IOL-45
7210LlOO
7210Ll65
721OL55
721OL65
7210L75
7216Ll2OB
7216Ll40
7216Ll85B
7216L55
7216L55B
7216L65
7216L65B
7216L75
7216L75B
CYPRESS
7C429-25C
7C429-25MB
7C428-30C
7C429-30C
7C428-30MB
7C429-30MB
7C428-40C
7C429-40C
7C428-40MB
7C429-40MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C432-25C
7C433-25C
7C432-30C
7C433-30C
7C432-30MB
7C433-30MB
7C432-4OC
7C433-4OC
7C432-40MB
7C433-40MB
7C432-65C
7C432-65MB
7C433-65C
7C433-65MB
7C432-65MB
7C433-65MB
7C460-15C
7C460-25C
7C460-15MB
7C460-25MB
7C460-25C
7C460-4OC
7C460-40MB
7C510-75M
7C510-75M+
7C510-55M
7C510-65M
7C510-75M
7C510-75M
7C510-45C+
7C510-75C+
7C51O-75C+
7C51O-55C+
7C510-65C+
7C510-75C+
7C516-75M+
7C516-75C+
7C516-75M+
7C516-55C+
7C516-55M+
7C516-65C+
7C516-65M
7C516-75C+
7C516-75M
-
. .~
~.CYPRFSS
~, SEMICONDOCTOR
IDT
7216L90
7216L90B
7217L12OB
7217L14O
7217L185B
7217IA5
7217L55
7217L55
7217L55B
7217L65
7217L65B
7217L75
7217L75B
7217L90
7217L90B
72401L10
72401L10B
72401L15
72401L15B
72401L25
72401L25B
72401135
72401135B
72401IA5
72402L10
72402L10B
72402L15
72402L15B
72402L25
72402L25B
72402135
72402135B
72402IA5
72403L10
72403L10B
72403L15
72403L15B
72403L25
72403L25B
72403135
72403135B
72403IA5
72404L10
72404L10B
72404L15
72404L15B
72404L25
72404L25B
72404135
72404135B
72404IA5
7M205S40C
7M205S40CB
7M205S5OC
7M205S50CB
7M205S7OC
7M205S7OCB
7M206S40C
7M206S40CB
7M206S50C
7M206S5OCB
7M206S7OC
CYPRESS
7C516-75C+
7C516-75M+
7C517-75M+
7C517-75C+
7C517-75M+
7C517-45C+
7C517-55C+
7C517-55C+
7C517-55M
7C517-65C+
7C517-65M
7C517-75C+
7C517-75M
7C517-75C+
7C517-75M+
7C401-lOC
7C401-10MB
7C401-15C
7C401-15MB
7C401-25C
7C401-25MB
7C401-25C
7C401-25MB
7C401-25C
7C402-lOC
7C402-10MB
7C402-15C
7C402-15MB
7C402-25C
7C402-25MB
7C402-25C
7C402-25MB
7C402-25C
7C403-10C
7C403-10MB
7C403-15C
7C403-15MB
7C403-25C
7C403-25MB
7C403-25C
7C403-25MB
7C403-25C
7C404-lOC
7C404-lOMB
7C404-15C
7C404-15MB
7C404-25C
7C404-25MB
7C404-25C
7C404-25MB
7C404-25C
M4210-40C
M4210-40MB
M421O-50C
M4210-S0MB
M421O-65C
M421O-65MB
M421O-40C
M4210-40MB
M4210-S0C
M4210-S0MB
M4210-65C
Product Line Cross Reference
IDT
7M206S70CB
7M4016S25C
7M4016S3SC
7M4016S35CB
7M4016S45C
7M4016S45CB
7M4016S55C
7M4016SS5CB
7M4016S70CB
7M4017S40C
7M4017SS0C
7M4017S5OCB
7M4017SS5C
7M4017S60C
7M4017S60CB
7M4017S70C
7M4017S70CB
7M4048SXXC
7M4048SXXCB
7M4048SXXP
7M624S30C
7M624S3SC
7M624S3SCB
7M624S4SC
7M624S45CB
7M624S55C
7M624SS5CB
7M624S65C
7M624S65CB
7MB4048SXXP
7MC4005S20CV
7MC4005S25CV
7MC4005S25CVB
7MC4005S3OCV
7MC4005S30CVB
7MC4005S35CV
7MC4005S35CVB
7MC4005S45CV
7MC4005S45CVB
7MC4005S55CV
7MC4005S55CVB
7MC4032S2OCV
7MC4032S25CV
7MC4032S30CV
7MC4032S4OCV
7MC4032S50CV
7MP4008L100S
7MP4008L7OS
7MP4008L85S
7MP4008S35S
7MP4008S45S
7MP4008S55S
7MP4008S70S
7MP4031SXX
7MP4036SXX
7MP4045SXX
7N4017S45C
8M624S100CB
8M624S35C
8M624S4OC
8M624S45C
8M624S50C
CYPRESS
M4210-65MB
1641HD-25C
1641HD-35C
1641HD-35MB
1641HD-45C
1641HD-45MB
1641HD-55C
1641HD-SSMB
1641HD-5SMB
1830HD-35C
1830HD-45C
1830HD-45MB
1830HD-55C
1830HD-5SC
1830HD-S5MB
1830HD-55C
1830HD-55MB
MI466HD-XXC
M1466HD-XXMB
M1464PD-XXC
1621HD-30C
1621HD-35C
1621HD-35MB
1621HD-45C
1621HD-45MB
1621HD-45C
1621HD-45MB
1621HD-45C
1621HD-45MB
MI464PD-XXC
1611HV-2OC
1611HV-25C
1611HV-25MB
1611HV-30C
1611HV-30MB
1611HV-35C
1611HV-35MB
1611HV-45C
1611HV-45MB
1611HV-45C
1611HV-45MB
1822HV-2OC
1822HV-25C
1822HV-3OC
1822HV-35C
1822HV-45C
1461PS-100C
1461PS-70C
1461PS-85C
1460PS-35C
1460PS-45C
1460PS-55C
1460PS-70C
M1821PZ-XXC
M1831PZ-XXC
Ml841PZ-XXC
1830HD-45C
162OHD-55MB
162OHD-35C
162OHD-35C
1620HD-45C
1620HD-4SC
IDT
8M624S5OCB
8M624S60C
8M624S60CB
8M624S70C
8M656S4OC
8M656S5OC
8M656S50CB
8M656S60C
8M656S60CB
8M656S70C
8M656S70CB
8M656S85C
8M656S85CB
8M824L100C
8M824L100N
8M824S100CB
8M824S35C
8M824S40C
8M824S45C
8M824S45CB
8M824S45N
8M824S50C
8M824S50CB
8M824S50N
8M824S60C
8M824S60CB
8M824S60N
8M824S70CB
8M824S70N
8M824S85CB
8M824S85N
8MP824S40S
8MP824S45S
8MP824S50S
8MP824S60S
8MP824S70S
8N624S70CB
8N624S85CB
CYPRESS
1620HD:-45MB
162OHD-55C
1620HD-55MB
1620HD-55C
1610HD-35C
1610HD-45C
161OHD-45MB
161OHD-45C
1610HD-45MB
1610HD-4SC
161OHD-45MB
161OHD-45C
161OHD-45MB
1421HD-85C
1421HD-85C
1420HD-55MB
1420HD-35C
1420HD-35C
1420HD-45C
1420HD-45MB
1423PD-45C
1420HD-45C
142OHD-45MB
1423PD-45C
142OHD-55C
142OHD-55MB
1423PD-55C
1420HD-55MB
1423PD-70C
142OHD-55MB
1421HD-85C
1422PS-35C
1422PS-45C
1422PS-45C
1422PS-S5C
1422PS-SSC
1620HD-55MB
1620HD-5SMB
INMOS
PREFIX:IMS
SUFFIX:B
SUFFIX:P
SUFFIX:S
SUFFIX:W
1203-25
1203-35
1203-45
1203M-35
CYPRESS
PREF1X:CY
SUFFIX:B
SUFFIX:P
SUFF1X:D
SUFF1X:L
7C147-25C+
7CI47-35C+
7C147-4SC+
7C147-35M+
INTEL
PREFIX:85C
PREFIX:85C
PREFIX:D
PREFIX:L
PREFIX:P
SUFFIX:/B
060-10
060-15
060-15
060-25
1223-25
CYPRESS
PREF1X:CY
PREFIX:PLD
SUFF1X:D
SUFFIX:L
SUFFIX:P
SUFFIX:B
61O-10C
610-12C
610-15C
610-25C
7C148-25C
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance spec., hut may not meet Icc or ISB
• - meets all performance specs except 2V data retention-may not meet Icc or IsB
functionally equivalent
t
SOIC only
:j: = 32·pin LCC crosses to the 7C198M
1-26
-,...z,
Product Line Cross Reference
~.
_'=C"YPRESS
-IF
INTEL
1223-35
1223-45
1223M-35
1223M-45
1400-35
1400-45
1400-55
1400M-45
1400M-55
1400M-70
1403-25
1403-35
1403-45
1403-55
1403LM-35
1403M-35
1403M-45
1403M-55
1403M-70
1420-45
1420-55
1420M-55
1420M-70
1421C-40
1423-25
1423-35
1423-40
1423M-35
1423M-45
1423M-55
1433-30
1433-35
1433-45
1433-55
1433M-35
1433M-45
1433M-55
1600-35
1600-45
1600-55
1600-70
1600M-45
1600M-55
1600M-70
1601LM-45
1601LM-55
1601LM-70
1620-35
1620-45
1620-55
1620-70
1620M-45
1620M-55
1620M-70
1624-35
1624-45
1624-55
1624-70
1624M-45
1624M-55
1624M-70
1625-25
SEMICONDUClOR
CYPRESS
7Cl48-35C
7Cl48-45C
7Cl48-25M+
7CI48-45M+
7C167A-35C
7C167A-45C
7C167A-45C
7C167A-45M
7C167A-45M
7C167A-45M
7CI67A-25C
7C167A-35C+
7CI67A-45C+
7CI67A-45C+
7CI67A-35M*
7CI67A-35M+
7CI67A-45M+
7CI67A-45M+
7CI67A-45M+
7Cl68A-35C
7CI68A-45C
7CI68A-45M+
7CI68A-45M
7C169A-4OC
7CI68A-25C+
7CI68A-35C+
7CI68A-45C+
7CI68A-35M*
7CI68A-45M*
7CI68A-45M*
7CI28A-25C+
7CI28A-35C+
7CI28A-45C+
7Cl28A-55C+
7CI28A-35M+
7CI28A-45M+
7CI28A-55M+
7C187-35C
7C187-45C
7C187-45C
7C187-45C
7C187A-45M+
7CI87A-45M+
7C187A-45M+
7CI87A-45M+
7CI87A-45M+
7CI87A-45M+
7CI64-35C
7CI64-45C+
7Cl64-45C+
7CI64-45C+
7Cl64A-45M
7Cl64A-45M
7Cl64A-45M
7C166-35C+
7CI66-45C+
7CI66-45C+
7CI66-45C+
7Cl66A-45M
7Cl66A-45M
7C166A-45M
7Cl64-25C
INTEL
1625-35
1625M-35
1625M-45
1630-45
1630-55
1630-70
1630LM-70
1630M-45
1630M-55
1630M-70
1800-30
1800-35
1800-45
1800M-35
1800M-45
1800P-35
1820-25
1820-35
1820-45
1820P-35
1820P-45
1830-45
2147H
2147H-1
2147H-2
2147H-3
2147HL
2148H
2148H-2
2148H-3
2148HL
2148HL-3
2149H
2149H-l
2149H-2
2149H-3
2149HL
22VI0-lOC
22VI0-10C
22V10-10C
22V10-10C
22V10-15C
22V10-15C
27256-1C
27256-2C
27512-17
27512-20
27512-25
27512-30
2764A-l
2764A-2
51C66-25
51C66-30
51C66-35
51C66-35L
51C67-30
51C67-35
51C67-35L
51C68-30
51C68-35
M2147H-3
M2148H
CYPRESS
7C164-35C
7C164A-45M
7C164A-45M
7C186-45C+
7C186-55C+
7CI86-55C+
7C186A-55M
7C186A-45M
7CI86A-55M+
7C186A-55M
7CI97-25C
7C197-35C
7C197-45C
7C197-35M
7C197-45M
7C194-35
7CI94-25C
7C194-35C
7C194-45C
7C194-35
7C194-45
7C198-45
2147-55C
2147-35C
2147-45C
2147-55C
7C147-45C
2148-55C
2148-45C
2148-55C
21L48-55C
21L48-55C
2149-55C
2149-35C
2149-45C
2149-55C
21L49-55C
PALC22VlOD-7C
PALC22VlOD-lOC
PAL22V1OC-7C+
PAL22V1OC-10C+
PALC22VI0B-15C
PALC22VI0D-15C
7C274-55C
7C274-55C
7C286-70C
7C286-70C
7C286-70C
7C286-70C
7C266-55C
7C266-55C
7C167A-25C7C167A-25C7CI67A-25C7C167A-25C7CI67A-25C+
7CI67A-35C+
7CI67A-35C+
7CI68A-25C+
7CI68A-35C+
7C169A-40M
2148-55M
1-27
INTEL
M2149H
M2149H-2
M2149H-3
CYPRESS
LATTICE
PREFIX:EE
PREFIX:GAL
PREFIX:ST
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
16K4-25
16K4-35
16K4-35M
16K4-45
16K4-45M
16K8-35
16K8-55
16V8-25
16V8-25
16V8-25
16V8-25
16V8-25L
16V8-25L
16V8-25L
16V8-25L
16V8-25Q
16V8-25Q
16V8-25Q
16V8-25Q
16V8-30
16V8-30
16V8-30
16V8-30
16V8-30L
16V8-30L
16V8-30L
16V8-30L
16V8-30Q
16V8-30Q
16V8-30Q
16V8-30Q
16V8-35
16V8-35
16V8-35
16V8-35
16V8-35L
16V8-35L
16V8-35L
16V8-35L
16V8-35Q
16V8-35Q
16V8-35Q
16V8-35Q
16V8A
16V8A
16V8A
16V8A
16V8A-15L
16V8A-15L
16V8A-25L
CYPRESS
2149-55M
2149-45M
2149-55M
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
7CI68A-25C
7C168A-35C
7C168A-35M
7C168A-45C
7C168A-45M
7CI28A-35C+
7C128A-45C+
PALC16L8-25C
PALC16R4-25C
PALC16R6-25C
PALC16R8-25C
PALC16L8-25C
PALC16R4-25C
PALCI6R6-25C
PALC16R8-25C
PALC16L8L-25C
PALCI6R4L-25
PALci6R6L-25
PALCI6R8L-25
PALCI6L8-30M
PALCI6R4-30M
PALCI6R6-30M
PALCI6R8-30M
PALCI6L8-30M
PALCI6R4-30M
PALCI6R6-30M
PALC16R8-30M
PALC16L8-30M
PALC16R4-30M
PALC16R6-30M
PALC16R8-30M
PALC16L8-35C
PALC16R4-35C
PALC16R6-35C
PALCI6R8-35C
PALC16L8-35C
PALC16R4-35C
PALC16R6-35C
PALC16R8-35C
PALC16L8L-35C
PALC16R4L-35C
PALC16R6L-35C
PALC16R8L-35C
PALC16L8
PALC16R4
PALC16R6
PALC16R8
PLDC18G8-12C
PLDC18G8-15C
PLDC18G8-20C
•
0
IL
Z
Product Line Cross Reference
LATTICE
16V8A-15U883
16V8A- 20U883
16V8A-30U883
16V8N883C
16V8N883C
16V8N883C
16V8N883C
20RA10
20RA10/883C
20V8-25
ZOV8-25L
ZOV8-25Q
ZOV8-35
ZOV8-35
ZOV8-35L
ZOV8-35L
ZOV8-35Q
ZOV8-35Q
ZOV8A
ZOV8N883C
22VlO
22VlO-15L
22VlO-20L
22V10-25L
22VlO-15U883
22V10-15U883
22VlO-ZOU883
22V10-25U883
22V10/883C
22V10B-1O
22V10B-10
22V10B-10
22V10B-1O
26CV12
26CVl2/883C
64E4-35
64E4-45
64E4-55
64Kl-35
64Kl-45
64Kl-45M
64Kl-55
64Kl-55M
64K4-35
64K4-45
64K4-45M
64K4-55
64K4-55M
64K8-35
64K8-45
64K8-45
64K8-45M
64K8-55
64K8-55
64K8-55M
64K8-70
LlOlO-45
LlOlO-65
LlOlO-65B
Ll010-9O
Ll010-9OB
CYPRESS
PLDC18G8-15MB
PLDC18G8-20MB
PLDC18G8-20MB
PALCl6L8-MB
PALC16R4- MB
PALC16R6-MB
PALC16R8-MB
PLDCZORA10
PLDCZORA10-MB
PLDCZOGlO-25C
PLDCZOGlO-25C
PLDCZOGlO-25C
PLDCZOGlO-30M
PLDCZOGlO-35C
PLDCZOGlO-30M
PLDCZOGlO-35C
PLDCZOGlO-30M
PLDCZOGlO-35C
PALCZOGlO
PALCZOGlO-MB
PAL22VlO
PALC22V10B-15C
PALC22V10-ZOC
PALC22V10-25C
PAL22V1OC-15MB+
PALC22VlOD-l5M
PALC22V10-ZOMB
PALC22V10-25MB
PAL22V10-MB
PALC22V10D-7C
PALC22V10D-1OC
PAL22V10C-7C+
PAL22VlOC-10C+
PAL22V10
PAL22V10-MB
7C166-35C
7C155-45C
7C166-45C
7C187-35C
7C187-45C
7C187A-45M
7C187-45C
7C187A-45M
7C164-35C
7Cl64-45C
7C164A-45M
7C164-45C
7C164A-45M
7C186-35C
7C186-45C
7CZ64-45C
7C186A-45M
7C186-55C
7CZ64-55C
7Cl86A-45M
7C264-55C
7C510-45C+
7C510-65C+
7C510-65M+
7C510-75C+
7C510-75M+
MICRON
PREFIX:MT
56C0816-25C
56C0816-35C
56C3816-25C
56C3816-35C
5C1001-25C
5C1001-35C
5C100l-45C
5C1005-25C
5C1005-35C
5ClOO5-45C
5C1008-25
5C1008-25
5C1008-35
5C1008-35
5C1008-45
5C1008-45
5Cl601-15
5Cl601-20C
5Cl601-25C
5Cl601-30
5Cl601-35C
5C1604-15
5Cl604-2OC
5C1604-25C
5Cl604-30
5C1604-35C
5C1605-15
5Cl605-2OC
5Cl605-25C
5Cl605-30
5C1605-35C
5Cl606-15
5Cl606-2OC
5C1606-25C
5C1606-30
5C1606-35C
5C1607-15
5C1607-ZOC
5C1607-25C
5C1607-30
5C1607-35C
5C1608-15
5C1608-ZOC
5C1608-30
5C1608-30M
5C1608-25C
5C1608-25M
5C1608-35C
5C1608-35M
5C2561-25
5C2561-25M
5C2561-30
5C2561-35
5C2561-35M
5C2561-45
5C2561-45M
5C2564-25
5C2564-25M
5C2564-30
5C2564-35
5C2564-35M
CYPRESS
PREFIX:CY
7C183-25C
7C183-35C
7C184-25C
7C184-35C
7C107-25C
7C107-35C
7C107-45C
7C106-25C
7C106-35C
7C106-45C
7C108-25C
7C109-25C
7C108-35C
7C109-35C
7C108-45C
7C109-45C
7C167A-15C
7C167A-ZOC
7C167A-25C
7C167A-25C
7C167A-35C
7C168A-15C
7C168A-ZOC
7C168A-25C
7C168A-25C
7C168A-35C
7C170A-15C
7C170A-20C
7C170A-25C
7C170A-25C
7C170A-35C
7Cl71A-15C
7Cl71A-2OC
7Cl71A-25C
7Cl71A-25C
7Cl71A-35C
7C172A-15C
7C172A-ZOC
7C172A-25C
7C172A-25C
7C172A-35C
7C128A-15C
7C128A-ZOC
7C128A-25C
7C128A-25M
7Cl28A-25C
7Cl28A-25M
7Cl28A-35C
7Cl28A-35M
7C197-25C
7C197-25MB
7C197-25C
7C197-35C
7C197-35MB
7C197-45C
7Cl97-45MB
7C194-25C
7C194-25MB
7Cl94-25C
7C194-35C
7C194-35MB
MICRON
5C2564-45
5C2564-45M
5C2565-25
5C2565-30
5C2565-35
5C2565-45
5C2568-25
5C2568-25M
5C2568-30
5C2568-35
SC2568-3SM
SC2568-45
SC2568-45B
5C2568CW-25
5C2568CW-25M
5C2568CW-30
5C2568CW-35
5C2568CW -35M
5C2568CW-45
5C2568CW-45B
5C2568W-25
5C2568W-25M
5C2568W-30
5C2568W-35
5C2568W-35M
SC2568W-45
5C2568W -45B
5C6401-15
5C6401-20
5C6401-2OC
5C640l-20M
5C6401-25
5C6401-25C
5C6401-25M
5C6401-30
5C6401-30M
5C6401-35
5C6401-35C
5C6401-35M
5C6401-45C
5C6404-12C
5C6404-15
5C6404-20
5C6404-'20M
5C6404-25
5C6404-25M
5C6404-30
5C6404-30M
5C6404-35
5C6404-35M
5C6405-12C
5C6405-15
5C6405-20C
5C6405-25C
5C640S-30
5C6405-35C
5C6406-12C
5C6406-15
5C6406-20
5C6406-25
5C6406-30
5C6406-35
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or IsB
• - meets all performance specs except 2V data retention-may not meet Icc or IsB
functionally equivalent
t
SOIC only
=I: = 32-pin LCC crosses to the 7C198M
1-28
CYPRESS
7C194-45C
7C194-45MB
7C196-25C
7C196-25C
7C196-35C
7C196-45C
7C199-25C
7Cl99-25MB
7Cl99-25C
7Cl99-35C
7C199-35MB
7C199-45C
7C199-45MB
7C198-25C
7C198-25MB
7C198-25C
7C198-35C
7C198-35MB
7C198-45C
7C198-45MB
7C198-25C
7C198-25MB
7C198-25C
7C198-35C
7C198-35MB
7C198-45C
7C198-45MB
7C187-15C
7C187-20C
7C187-2OC
7C187A-20MB
7C187-25C
7C187-25C
7C187A-25MB
7C187-25C
7C187A-25MB
7C187-35C
7C187-35C
7C187A-35MB
7C187-45C
7B164-12C
7C164-15C
7C164-20C
7C164A-20MB
7C164-25C
7C164A-25MB
7C164-25C
7C164A-25MB
7C164-35C
7Cl64A-35MB
7B166-12C
7C166-15C
7C166-2OC
7C166-25C
7C166-25C
7C166-35C
7B161-12C
7C161-15C
7C161-20C
7C161-25C
7C161-25C
7C161-35C
~
=
~
Product Line Cross Reference
)~NDucrOR
MICRON
5C6407-12C
5C6407-15
5C6407-20
5C6407-25
5C6407-30
5C6407-35
5C6408-12
5C6408-15
5C6408-20C
5C6408-20M
5C6408-25C
5C6408-25M
5C6408-30
5C6408-30M
5C6408-35C
5C6408-35M
85C1664-30C
85C1664-35C
85C1664-45C
85C3216-20
85C3216-25
85C3216-35
85C3264-20
85C3264-25
85C3264-35
85C8128-25
85C8128-35
85C8128-30C
85C8128-35C
85C8128-45C
85C8128-45C
8S1632Z-20
8S1632Z-25
8S1632Z-35
8S6432Z-20
8S6432Z-25
8S6432Z-35
CYPRESS
7B162-12C
7C162-15C
7C162-20C
7C162-25C
7C162-25C
7C162-35C
7B185-12C
7C185-15C
7C185-20C
7C185A-20MB
7C185-25C
7Cl85A-25M
7C185-25C
7C185A-25MB
7C185-35C
7C185A-35MB
1620HD-30C
1620HD-35C
1620HD-45C
M1821PZ-20C
M1821PZ-25C
M1821PZ-35C
M1831PZ-20C
M1831PZ-25C
M1831PZ-35C
M1420PD-25C
M1420PD-35C
1420HD-30C
1420HD-35C
1420HD-45C
1423PD-45C
M1821PZ-20C
M1821PZ-25C
M1821PZ-35C
M1831PZ-20C
M1831PZ-25C
M1831PZ-35C
MITSUBISHI
PREFIX:M5L
PREFIX:M5M
SUFFIX:AP
SUFFIX:FP
SUFFIX:K
SUFFIX:P
21C67P-35
21C67P-45
21C67P-55
21C68P-35
21C68P-45
21C68P-55
272112AK -10
272112AK -12
272112AK-15
272112K -17C
272112K-2C
272112K-I
27256K-12C
27256K-15C
27256K-2C
27256K-IC
5165L-100
CYPRESS
PREFIX:CY
PREFIX:CY
SUFFIX:L
SUFFIX:F
SUFFIX:D
SUFFIX:P
7C167A-35C
7C167A-45C
7C167A-45C
7C168A-35C
7C168A-45C
7C168A-45C
7C286-70C
7C286-70C
7C286-70C
7C286-70C
7C286-70C
7C286-70M
7C274-55C
7C274-5CM
7C274-55C
7C274-55M
7C186-55C+
MITSUBISHI
5165L-120
5165L-70
5165P-100
5165P-120
5165P-70
5178P-45
5178P-55
5187P-25
5187P-35
5187P-45
5187P-55
5188P-25
5188P-35
5188P-45
5188P-55
5257J-35
5257J-45
5257P-35
5257P-45
52581-45
5258P-35
5258P-45
CYPRESS
7C186-55C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-45C+
7C186-55C+
7C187-25C
7C187-35C
7C187-45C
7C187-45C
7C164-25C
7Cl64-35C
7C164-45C
7Cl64-45C
7C197-35C
7C197-45C
7C197-35C
7C197-45C
7C194-45C
7C194-35C
7C194-45C
MMI/AMD
CYPRESS
SUFFIX:B
SUFFIX:F
SUFFIX:D
SUFFIX:L
SUFFIX:P
SUFFIX:B
7C282-45M
7C282-45M
7C281-45M
7C281-45M
7C245-35M7C245-35M7C245-45M7C225-35M
7C225-40M
7C245-45M7C235-4OM
7C235-4OM7C292-50M
7C291-35M
7C291-50M
7C282-45M
7C282-45M
7C281-45M
7C281-45M
7C401-10M
7C401-1OM
7C402-10M
7C402-10M
7C282-45C
7C282-45C
7C281-45C
7C281-45C
7C245-35C7C245-35C7C225-25C
7C225-30C
7C245-35C-
SUFFIX:883B
SUFFIX:F
SUFFIX:J
SUFFIX:L
SUFFIX:N
SUFFIX:SHRP
5381-1
5381-2
5381S-1
5381S-2
53R1681AS
53RA1681AS
53RA1681S
53RA481AS
53RA481S
53RS1681S
53RS881AS
53RS881S
53S1681
53S1681AS
53S1681S
53S881
53S881A
53S881AS
53S881S
57401
57401A
57402
57402A
6381-1
6381-2
6381S-1
6381S-2
63RA1681AS
63RA1681S
63RA481AS
63RA481S
63RS168IAS
1-29
MMI/AMD
63RS1681S
63RS881AS
63RS881S
63S1681
63S1681A
63S1681AS
63S1681S
63S881
63S881
63S881A
63S881A
67401
67401A
6740lB
6740lD
67402
67402A
67402B
67402D
67411
67412
67L402
C57401
C57401A
C57402
C57402A
C67401A
C6740lB
C6740lD
C67402
C67402A
C67402B
C67402D
C67L401
PAL12L1OC
PAL12L10M
PAL14L8C
PAL14L8M
PAL16L6C
PAL16L6M
PAL16L8A-2C
PAL16L8A-2M
PAL16L8A-4C
PAL16LBA-4M
PAL16L8AC
PAL16L8AM
PAL16L8B-2C
PALl6L8B-2M
PAL16L8B-4C
PAL16L8B-4M
PAL16L8BM
PAL16L8C
PAL16L8D-4C
PAL16L8D-4M
PAL16L8M
PAL16R4A-2C
PAL16R4A-2M
PAL16R4A-4C
PAL16R4A-4M
PAL16R4AC
PAL16R4AM
PAL16R4B-2C
CYPRESS
7C245-35C7C235-30C7C235-30C7C292-50C
7C292-35C
7C291-35C
7C291-50C
7C281-45C
7C282-45C
7C281-30C
7C282-30C
7C401-lOC
7C401-15C
7C403-25C
7C403-25C
7C402-lOC
7C402-15C
7C402-25C
7C404-25C
7C403-25C
7C402-25C
7C402-1OC
7C401-1OM
7C401-10M
7C402-1OM
7C402-10M
7C401-15C
7C403-25C
7C401-15C
7C402-1OC
7C402-15C
7C404-25C
7C402-15C
7C401-5C
PLDC20GlO-35C
PLDC20GlO-4OM
PLDC2OG10-35C
PLD20GlO-4OM
PLD20G1O-35C
PLDC20GlO-4OM
PALC16L8-35C
PALC16L8-4OM
PALC16L8L-35C
PALC16L8-4OM
PALC16L8-25C
PALC16L8-30M
PALC16L8-35C
PALC16L8-30M
PALC16L8L-35C
PALC16L8-4OM
PALC16L8-20M
PALC16L8-35C
PALC16L8L-25C
PALC16L8-30M
PALC16L8-4OM
PALC16R4-35C
PALC16R4-40M
PALC16R4L-35C
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
0
I!..
:i!:
~
~~PRESS
~; SEMICONDUC1DR
MMIlAMD
PAL16R4B-2M
PAL16R4B-4C
PAL16R4B-4M
PAL16R4BM
PAL16R4C
PAL16R4D-4C
PAL16R4M
PAL16R6A-2C
PAL16R6A-2M
PAL16R6A-4C
PAL16R6A-4M
PAL16R6AC
PAL16R6AM
PAL16R6B-2C
PAL16R6B-2M
PAL16R6B-4C
PAL16R6B-4M
PAL16R6BM
PAL16R6C
PAL16R6D-4C
PAL16R6M
PAL16RBA-2C
PAL16RSA-2M
PAL16RBA-4C
PAL16R8A-4M
PAL16R8AC
PAL16R8AM
PAL16R8B-2C
PAL16R8B-2M
PAL16R8B-4C
PAL16R8B-4M
PAL16R8BM
PAL16R8C
PAL16R8D-4C
PAL16R8M
PAL18L4C
PAL18L4M
PAL2OLlOAC
PAL2OLlOAM
PAL2OLlOC
PAL20LlOM
PAL20L2C
PAL2OL2M
PAL20LBA-2C
PAL2OL8A-2M
PAL20LBAC
PAL2OL8AM
PAL20LBC
PAL20LBM
PAL20R4A-2C
PAL2OR4A-2M
PAL2OR4AC
PAL2OR4AM
PAL2OR4C
PAL2OR4M
PAL2OR6A-2C
PAL2OR6A-2M
PAL2OR6AC
PAL2OR6AM
PAL2OR6C
PAL20R6M
PAL2OR8A-2C
CYPRESS
PALC16R4-30M
PALC16R4L-35C
PALC16R4-40M
PALC16R4-2OM
PALC16R4-35C
PALC16R4L-25C
PALC16R4-40M
PALC16R6-35C
PALC16R6-40M
PALC16R6L-35C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-30M
PALC16R6L-35C
PALC16R6-40M
PALC16R6-2OM
PALC16R6-35C
PALC16R6L-25C
PALC16R6-40M
PALC16RB-35C
PALC16R8-40M
PALC16RBL-35C
PALC16R8-40M
PALC16RB-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-35C
PALC16R8-40M
PALC16R8-20M
PALC16R8-35C
PALCl648L-25C
PALC16R8-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20GIO-40M
PLDC2OGIO-35C
PLDC20GlO-40M
PLDC2OGlO-25C
PLDC20GIO-30M
PLDC2OGIO-35C
PLDC2OG10-40M
PLDC2OGlO-35C
PLDC2OG10-40M
PLDC20GlO-25C
PLDC2OG10-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC2OG10-35C
PLDC20GlO-40M
PLDC2OG10":25C
PLDC2OGlO-30M
PLDC20G10-35C
PLDC20GlO-40M
PLDC2OG10-35C
Product Line Cross Reference
MMI/AMD
PAL20RSA-2M
PAL20RSAC
PAL20R8AM
PAL2OR8C
PAL20R8M
PALC22V10/A
PLE10P8C
PLElOP8C
PLE10P8M
PLElOP8M
PLE10RBC
PLElOR8M
PLEllP8C
PLEllP8M
PLEllRA8C
PLEllRA8M
PLEllRS8C
PLEllRS8M
PLE9R8C
PLE9R8M
CYPRESS
PLDC20GlO-40M
PLDC2OGlO-25C
PLDC20GlO-30M
PLDC2OGlO-35C
PLDC20GlO-40M
PALC22V10-35C
7C2B1-30C
7C282-30C
7C2B1-45M
7C282-45M
7C235-30C7C235-40M7C291-35C
7C291-35M
7C245-35C7C245-35M7C245-35C7C245-35M7C225-30C
7C225-35M
MOSAIC
PREFIX:MS
BI2BSC-100
8128SC-100
8128SC-45
BI2BSC-55
8128SC-70
8128SC-70
CYPRESS
PREFIX:SYM
1420HD-85C
1421HD-85C
1420HD-45C
1420HD-55C
142OHD-70C
1421HD-70C
MOSTEK
PREFIX:ET
PREFIX:MK
PREFIX:TS
SUFFIX:N
SUFFIX:P
41H67-25
41H67-35
41H68-25
41H68-35
41H69-25
41H69-35
41L67-25
41L67-35
41L67-45
CYPRESS
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:P
SUFFIX:D
7CI67A-25C+
7CI67A-35+
7CI68A-25C+
7CI68A-35C+
7C169A-25
7C169A-35C
7CI67A-25C7C167A-357CI67A-35-
MOTOROLA
PREFIX:MCM
SUFFIX:BXAJC
SUFFIX:P
SUFFIX:S
SUFFIX:Z
10422-10C
1423-45
2016H-45
2016H-55
2016H-70
2018-35
2018-45
2167H-35
2167H-45
2167H-55
CYPRESS
PREFIX:CY
SUFFIX:MB
SUFFIX:P
SUFFIX:D
SUFFIX:L
10E422-7C
7CI6SA-45C+
6116A-45C
6116A-55C
6116A-55C
7C128A-35C
7C128A-45C
7C167A-35C
7C167A-45C
7C167A-45C
MOTOROLA
60256A-1O
60256A-12
60256A-85
6064-10
6064-12
6147-55
6147-70
6164-45
6164-55
6164-70
6168-35
6168-45
6168-55
6168-70
61L47-55
61L47-70
61L64-45
61L64-55
61L64-70
6206-35
6206-45
6206-45
6206-55
6206-70
6206P-45
6207-25
6207-25
6207-35
6208-25
6208-25
6208-35
6226-25C
6226-30C
6228-25C
6228-3OC
62486FN14
62486FN19
62486FN24
6264-15C
6264-25
6264-25
6264-30
6264-30
6264-35
6264-35
6264-45
6264-45
6264-55
6264-55
6268P2O
6268P25
6268P35
6268P40
6268P45
6268P45
6269P2O
6269P25
6269P35
6270-20
6270-25
6270-35
6270-45
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
• = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIC only
:j: = 32·pin LCC crosses to the 7C198M
1-30
CYPRESS
7C198-55C
7C198-55C
7C198-55C
7C186-55C
7C186-55C
7C147-45C·
7C147-45C·
7C186-45C
7C186-55C
7C186-55C
7C16SA-35C+
7C168A-45C+
7C16SA-45C+
7C168A-45C+
7CI47-45C'
7CI47-45C'
7C186-45C
7C186-55C
7C186-55C
7C198-35C
7C198-45
7C198-45C
7C198-55
7C198-55
7C198-45
7CI97-25
7CI987-25C
7C197-35
7C194-25
7CI94-25C
7C194-35
7C108-25C
7C10B-25C
7CI06-25C
7C106-25C
7B173-14C
7B173-18C
7B173-21C
7B185-15C
7CI85-25C
7CI86-25C
7CI85-25C
7CI86-25C
7C185-35C
7C186-35C
7C185-45C
7C186-45C
7C185-55C
7C186-55C
7C168A-2OC
7CI68A-25C
7C168A-35C
7C168A-40C
7C168A-45
7C16SA-45C
7C169A-2OC
7CI69A-25C
7C169A-35C
7C170A-2OC
7C170A-25C
7C170A-35C
7C170A-45C
~
-~-?
-=-_r
Product Line Cross Reference
g'CYPIlRSS
SEMICONDUCrOR
MOTOROLA
6287-12
6287-15
6287-20
6287-25
6287-35
6287-45
6288-12
6288-12
6288-15
6288-25
6288-30
6288-35
6288-45
6290-12
6290-12
6290-15
6290-20
6290-25
6290-35
6290-45
62940FN14
62940FN19
62940FN24
6706-12
6708-12
6709-12
7681
7681A
93422
93422
93422A
93422A
93L422
93L422
93L422A
93L422A
CYPRESS
7C187-12C
7C187-15C
7C187-2OC
7C187-25C
7C187-35C
7C187-45C
7BI64-12C
7CI64-12C
7Cl64-15C
7Cl64-25C
7Cl64-25C
7C164-35C
7C164-45C
7B166-12C
7C166-12C
7C166-15C
7C166-20C
7C166-25C
7C166-35C
7C166-45C
7B174-14C
7B174-18C
7B174-21C
7B199-12C
7B194-12C
7B195-12C
7C282-45C
7CZ82-45C
93422C
93422M
93422AC
93422AM
93L422C
93L422M
93L422AC
93L422AM
NATIONAL
PREFIX:DM
PREFIX:GAL
PREIFX:IDM
PREFIX:NM
PREFIX:NMC
SUFFIX:]
SUFFIX:N
100422-lOC
100422-5C
100422A-7C
100422AC
100474A-IOC
100474A-8C
100494-15
100494-18
10422-lOC
10422-5C
10422A-7C
10422AC
10474A-8C
1047A-IOC
10494-10
10494-12
10494-15
CYPRESS
PREFIX:CY
PREFIX:None
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:D
SUFFIX:P
100E422L-7C
100E422-5C
100E422L-7C
100E422L-7C
100E474L-7C
100E474L-7C
100E494L-12C
100E494L-12C
IOE422L-7C
1OE422-5C
1OE422L-7C
IOE422L-7C
10E474L-7C
1OE474L-7C
IOE494-10C
lOE494L-12C
10E494L-12C
NATIONAL
12L10C
14L8C
14L8M
16L6C
16L6M
16V8A-12LC
16V8A-12C
16V8A-15LC
16V8A-15C
16V8A-15LM
16V8A-15M
16V8A-20LM
16V8A-20M
18L4C
18L4M
20L2M
2147H
2147H
2147H-l
2147H-2
2147H-3
2147H-3
2147H-3L
2148H
2148H
2148H
2148H
2148H-2
2148H-3
2148H-3L
2148HL
2901A-IC
2901A-1M
2901A-2C
2901A-2M
2901AC
2901AM
2909AC
2909AM
2911AC
2911AM
54S189
54S189
54S189
54S189
54S189A
54S189A
54S189A
54S189A
54S189A
74S189
74S189
74S189
74S189
74S189A
74S189A
74S189A
74S189A
74S189A
74S289A
74S289A
74S289A
CYPRESS
PWC20GlO-35C
PWCZOGlO-35C
PWC20GlO-40M
PLDC20GlO-35C
PLDC20GlO-40M
PWC18G8-12C
PLDC18G8-12C
PLDCI8G8-15C
PLDC18G8-15C
PLDCI8G8-15MB
PLDCI8G8-15MB
PLDCI8G8-20MB
PLDCI8G8-20MB
PLDC2OGlO-35C
PLDC2OGlO-40M
PLDC2OGI0-40M
2147-55C
2147-55M
2147-35C
2147-45C
2147-55C
2147-55M
7C147-45C
2148-55C
7C148-C
2148-C
21L48-C
2148-45C
2148-55C
21L48-55C
21L48-55C
7C901-31C
7C901-32M
7C901-31C
7C901-32M
7C901-31C
7C901-32M
2909AC
2909M
2911AC
2911M
74S189M
7C189-M
27S03A-M
27LS03A-M
74S189M
7CI89-25M
7C189-M
27S03A-M
27LS03A-M
74S189C
7C189-C
27S03A-C
27LS03A-C
74S189C
27S03AC
7C189-C
27S03A-C
27LS03A-C
74S189C
7C189-C
27S03A-C
1-31
NATIONAL
74S289A
75S07
75S07A
77LS181
77S181
77S181A
77S191
77S191A
77S191B
77S281
77S281A
77S291
77S291A
77S291B
77S401
77S401A
77S402
77S402A
77SR181
77SR25
77SR25B
77SR476B
77ST476
85S07
85S07A
85S07A
87LS181
87S181
87S191
87S191A
87S191B
87S281
87S281A
87S291
87S291A
87S291B
87S401
87S401A
87S402
87S40ZA
87S625
87SR181
87SR25B
87SR476
87SR476B
93L42ZA
93L42ZA
93L42ZA
PAL10016P4-4C
PAL10016P4-6C
PALlOOI6P8-4C
PAL10016P8-6C
PALlOI6P4-4C
PALI016P4-6C
PAL1016P8-4C
PAL1016P8-6C
PAL164A2M
PAL16L8A2C
PALI6L8A2M
PAL16L8AC
PAL16L8AM
PALI6L8B2C
CYPRESS
27LS03A-C
7CI90-25M
27S07AM
7C282-45M
7C282-45M
7C282-45M
7C292-50M
7C292-50M
7C292-50M
7C281-45M
7C281-45M
7C291-50M
7C291-50M
7C291-50M
7C401-lOM
7C401-10M
7C402-10M
7C402-lOM
7C235-40M
7C225-40M
7C225-40M
7C225-40M7CZ25-40M27S07C
27S07AC
7C128-45C+
7CZ82-45C
7C282-45C
7C292-50C
7CZ92-35C
7CZ92-35C
7C281-45C
7CZ81-45C
7CZ91-50C
7CZ91-35C
7CZ91-35C
7C401-10C
7C401-15C
7C402-lOC
7C402-15C
7C225-40C
7C235-30C
7CZ25-3OC
7C225-40C7C225-30C7C122-C
9342ZA-C
93L422-C
100E302L-4C
100E302L-4C
l00E301-4C
100E301L-6C
lOE302L-4C
10E302L-4C
IOE301-4C
lOE301L-6C
PALC16R4-40M
PALCI6L8-35C
PALCI6L8-40M
PALCI6L8-25C
PALCI6L8-30M
PALCI6L8-25C
0
IL
~
~
~aPRF.SS
~; SEMlCCt
&2
=---;...,;b
Section Contents
~=CYPRESS
~, SEMlCONDUCIDR
Static RAMs (Random Access Memory) (continued)
Device Number
CY7ClO07
CY7ClO09
CY7M194
CY7M199
CY74S189
CY27LS03
CY27S03
CY27S07
CY93422A
CY93L422A
CY93422
CY93L422
Page Number
Description
1M x 1 Static R/W RAM ..................................................... .
128K x 8 Static R/W RAM .................................................... .
64K x 4 Static RAM Module .................................................. .
32K x 8 Static RAM Module .................................................. .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
16 x 4 Static R/W RAM ...................................................... .
16x4StaticR/WRAM ...................................................... .
256 x 4 Static R/W RAM ..................................................... .
256 x 4 Static R/W RAM ..................................................... .
256 x 4 Static R/W RAM ..................................................... .
256 x 4 Static R/W RAM ..................................................... .
2-443
2-444
2-445
2-446
2-451
2-451
2-451
2-451
2-456
2-456
2-456
2-456
•
II)
:E
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .............. . . . . . . . . . . . . . . > 200 rnA
StorageThmperature ................. - 65°C to + 150°C
Operating Range
Ambient Temperaturewith
Power Applied .. . .. . .. . .. . . . . . . . . . . .. - 55°C to + 125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to
DC Input Voltage ...................... - 3.0V to
Output Current ioto Outputs (Low) ................
Electrical Characteristics
+ 7.0V
Range
Commercial
+7.0V
+ 7.0V
Militaryll]
Ambient
Thmperature
Vee
O°Cto + 70°C
5V± 10%
- 55°C to + 125°C
5V± 10%
20 rnA
Over the Operatiog Rangel:2]
2147
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Min.
V cc = Mio., IOH = - 4.0 rnA
V cc = Mio., IOL = 12.0 rnA
2.0
-3.0
IJX
Input Load Current
GNDS VI S Vee
loz
Output LeakageCurrent
GNDS VaS Vee,
Output Disabled
los
Output Short
Circuit Current[3]
Vcc = Max., VOVT = GND
Icc
Vee Operatiog Supply Current
V cc = Max., lOUT = 0 rnA
ISB
Automatic CE
Power-DownCurrent[4]
Max. Vee, CE ~ VIH
Max.
Units
V
2.4
0.4
V
Vcc
0.8
+10
V
V
+50
!LA
!LA
-350
rnA
Com'l
Mil
125
140
rnA
Com'l
25
rnA
Mil
25
-10
-50
Capacitance [5]
Parameters
Description
CrN
InputCapacitance
CoVT
Output Capacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee=5.0V
Max.
Units
8
pF
8
pF
Notes:
1.
2.
3.
4.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
Duration of the short circuit should not exceed 30 seconds.
5.
A pull-up resistor to V cc on the CE input is required to keep the device deselected duringVccpower-up, otherwise ISBwillexceedvalues
given.
Thstedinitially and after any desigo or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R13290
R13290
5V<>------....,
5V<>-----_....,
OUTPUT<>----....- - t
OUTPUT <>----....- - t
30PFI
5PFI
R2
2020
INCWDING
JIGAND _
INCLUDING
JIG AND _
SCOPE -
SCOPE -
R2
2020
THEvENIN EQUIVALENT
----..J.o...
9O%=---~
GND _ _--"r
21474
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.OV
2147-3
1250
OUTPUT <>0---"""''''10_--..,0 1.9OV
2-2
R:'-!~PRESS
CY2147
-:e!!I!ii!iiI'.r SEMICONDUCJDR
Switching Characteristics
Over the Operating Range[2,6]
2147-35
Description
Parameters
Min.
Max.
2147-45
Min.
Max.
2147-55
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tM
Address to Data Valid
35
45
35
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tLZcE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power·Up
tpo
CE HIGH to Power·Down
55
45
5
5
5
45
35
5
5
30
0
5
0
ns
ns
30
0
ns
ns
20
20
ns
ns
55
30
20
ns
55
ns
WRITECYCLEI9]
twc
Write Cycle Time
35
45
55
ns
tSCE
CE LOW to Write End
35
45
45
ns
tAW
Address Set·Up to Write End
35
45
45
ns
tHA
Address Hold from Write End
0
0
10
ns
tSA
Address Set·Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
25
25
ns
tso
Data Set·Up to Write End
20
25
25
ns
tHO
Data Hold from Write End
10
10
10
tHZWE
WE LOW to High Z[7]
tLZWE
WE HIGH to Low zJ7, 8]
20
0
Notes:
6. Test conditions assume signal transition time of 5 nsor less, timing ref·
erence levels of LSY, input pulse levels of 0 to 3.0Y, and output loading
of the specified IOl}IOH and 30·pF load capacitance.
7. At any given temperature and voltage condition, 1Hz is less than tIZ
for all devices.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC
Test Loads. 'fransition is measured ±500 mV from steady state volt·
age.
9. The internal write time ofthe memory is defined by the overlap of CE
WW and WEWW. Both signals must be WWtoinitiateawrite and
25
0
10.
1L
12.
13.
ns
25
0
ns
ns
either signal can terminate awrite by going HIGH. The data input set·
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CE = V!L.
Address valid prior to or coincident with CE transition low.
IfCEgoesHIGHsimultaneouslywith WEHIGH, the output remains
in a high·impedance state.
Switching Waveforms
Read Cycle No.l[lO,H]
ADDRESS
€
------ ~
DATA OUT
PREVIOUS DATA V : :
tRC
1
tM
*-
JXX *::::::::::::::D:A:T:A:V:A:LI:D::::::::::=
2147-5
2-3
•
CY2147
Switching Waveforms (continued)
Read Cycle No. 2[10, 12)
CE
IRe
~~
:-]
lACE
ILZCE
HIGH IMPEDANCE
DATA OUT
//
~
DATA VALID
"))'1'
HIGH
IMPEDANC E
/
cJ~::m ______J~5-0%-------------------~:
-Ipu
I
I----IPO
2147-6
Write Cycle No.1 (WE Controlled)[9)
Iwe
ADDRESS
~E
--../
j(
IseE
;; Wffff~ W///m
~ ~ I"\.
lAW
IHA-
ISA
IPWE
~~
/f-
*
DATA IN
Iso
IHO ...
"'!~
DATA-IN VALID
I--
j
IHZWE
~
ILZWE--j
HIGH IMPEDANCE
DATAOUT _ _ _ _ _ _ _D_AT_A_U_N_D_E_FI_NE_D_ _ _ _ _ _ _J)~--------------~<~
________
2147-7
Write Cycle No.2 (CE Controlled)[9, 13)
~--------------------
ADDRESS
-------+--
'seE - - - - - + (
14--+----DATA IN -------------------~
DATA OUT
Iso
---~
DATA-IN VAUD
IHZWE~
-
HIGH IMPEDANCE
~---------------------2147-8
DATA UNDEFINED
2-4
.4¥
;'~PRESS
CY2147
_!I' SEMICONDUCTOR
Ordering Information
Speed
(ns)
35
45
55
Package
1YIJe
Operating
Range
CY2147-35PC
P3
Commercial
CY2147-35DC
D4
Ordering Code
CY2147-45PC
P3
CY2147-45DC
D4
CY2147-45DMB
D4
Military
CY2147-55PC
P3
Commercial
CY2147-55DC
D4
CY2147-55DMB
D4
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
1,2,3
Icc
1,2,3
ISBl
1,2,3
Parameters
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9,10,11
tOliA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tliA
7,8,9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7,8,9, 10, 11
tSD
7,8,9, 10, 11
tHD
7,8,9,10,11
Document#: 38-00023-B
2-5
CY2148/CY21IA8
CY2149/CY21IA9
CYPRESS
SEMICONDUcrOR
1,024 x 4 Static R/W RAM
Features
Functional Description
• Automated power-down when deselected (2148)
• CMOS for optimum speed/power
TheCY2148andCY2149arehigh-performance CMOS static RAMs organized as
1024 by 4 bits. Easy memory expansion is
Rrovided by an active LOW chip select
(CS) ioput and three-state outputs. The
CY2148 and CY2149 are identical except
that the CY2148 iocludes an automatic
(CS)power-downfeature. The CY2148 remains io a low-power mode as lon~ the
device remaios deselected, i.e., (CS) is
HIGH, thus reduciog the average power
r~uirementsof the device. The chip select
(CS) of the CY2149 does not affect the
power dissipation of the device.
An active LOW write enable signal (WE)
controls the writing/reading operation of
the memory. When the chip select (CS)
• Lowpower
- 660 mW (commercial)
-770 mW (military)
• 5-volt power supply ± 10% tolerance
both commercial and military
• 1TL-compatible inputs and outputs
and write enable (WE) ioputs are both
LOW, data on the four data ioput/output
pios (1/00 through 1/03) is written ioto the
memory location addressed bytbe address
present on the address pins (Ao through
~).
Readiogthe device is accomplished by selecting the device, (CS) active LOW, while
(WE) remaios ioactive or HIGH. Under
these conditions, the contents of the location addressed by the information on address pios (Ao through A9) is present on
the four data ioput/output pins (1/00
through 1/03).
The ioput/output pins (1/00 through 1/03)
remain io a high-impedance state unless
the chip is selected and write enable (WE)
is HIGH
Pin Configuration
Logic Block Diagram
STORAGE MATRIX
DIP
'fupView
vee
Iv;
~
A7
A..
Iv;
Aa
Ag
Ao
1/00
1/01
1/02
Al
A2,
CS
GND
I/Oa
8
VSS
CS-------Iool
2148-2
WE---------L~__~~~~~
2148-1
Selection Guide
(For higher performance and lower power refer to the CY7C148/9 data sheet)
MaximumAccess Time (ns)
Maximum Operating
Current(mA)
I Commercial
2148-35
2149-35
21IA8-35
21IA9-35
2148-45
2149-45
21IA8-45
21IA9-4S
2148-55
2149-55
21IA8-55
21IA9-55
35
35
45
45
55
55
140
120
140
120
140
120
I Military
140
2-6
140
CY2148/CY21IA8
CY2149/CY21IA9
. .~
~=CYPRESS
~_., SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. Ambient Temperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential
(Pin 18 to Pin 9) ........................
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
6S0Cto +IS0°C
Operating Range
Ambient
Thmperature
SSOCto +12SoC
Range
Commercial
Military!l]
- O.SV to +7.0V
- O.SVto +7.0V
O°Cto + 70°C
Vee
SV ± 10%
- S5°Cto + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
Parameters
IOH
IOL
VIR
VJL
IJX
Ioz
Icc
ISB
Ipo
los
2148
2149
Min. Max.
2.4
0.4
2.0
6.0
-3.0
0.8
-10 +10
-so +So
Description
Output HIGH Current
Output LOW Current
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Thst Conditions
Vee = Min., VOH = -O.4rnA
Vee = Min., VOL = 8.0 rnA
Vee Operating
Supply Current
Max. Vec,CSs VIL
Output Open
TA = O°Cto +70°C
140
TA = -SSOCto +125°C
140
AutomaticCS
Power-Down Current
Max. Vee, CS S VIL
(2148 only)
TA = O°Cto +70°C
30
TA = - 5S0Cto + 125°C
30
Peak Power-On
Currentl3]
Max. Vee,CSs VIL
(2148 only)
TA = O°Cto +70°C
SO
TA = - 5S0Cto + 125°C
so
Output Short
CircuitCurrent[4]
GNDsVosVee
TA = O°Cto +70°C
±275
TA = - 5S0Cto + 125°C
±350
VSssVJsVee
GNDsVoSVOH,
Output Disabled
TA = O°Cto +125°C
211A8
211A9
Min. Max.
0.4
6.0
0.8
Units
rnA
rnA
V
V
+10
+50
!J.A.
iJA
120
rnA
20
rnA
30
rnA
±27S
rnA
2.4
2.0
-3.0
-10
-so
Capacitance [5]
Description
InputCapacitance
Output Capacitance
Parameters
CIN
CoUT
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = S.OV
Max.
8
8
Units
pF
pF
Notes:
1. TA is the "instant on" case temperature.
2.
3.
4.
See the last page of this specification for Group A subgroup testing information.
A pull-up resistor to V cc on the CS input is required to keep the device
deseJectedduring V ccpowerup. Otherwise, currentwiI1 exceedvalues
give (CY2148 only).
5.
For test purposes, not more than 1 output at a time should he shorted.
Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl4810
5Vo----"""',
Rl48lO
5V 0 - - -......""""'..
OUTPUTo----1r---+
OUTPUTo----1r---+
R2
2550
=
Equivalent to:
5 pF
INCLUDING
I
J~~g=
(b)
ALL INPUT PULSES
R2
3.0V - - - -.J"""~---_'
2550
GND
=
2148-3
THEVENIN EQUIVALENT
167!J
OUTPUT 00.--_""''''_ _-00 1.73V
2-7
2148-4
•
CY2148/CY211A8
CY2149/CY211A9
Switching Characteristics
Over the Operating Rangel2]
2148-35
2149-35
Parameters
Min.
Description
Max.
2148-45
2149-45
Min.
Max.
2148-55
2149-55
Min.
Max.
Units
READ CYCLE
tRC
Address Valid to Address Do Not
Care Time (Read Cycle Time)
tAA
Address Valid to Data Out
Valid Delay (Address Access Time)
tACS1 16]
tACSz!7]
tACS
tul8]
35
45
35
Chip Select WW to Data Out Valid
(CY2148 only)
Chip Select WW to Data Out Valid
(CY2149 only)
Chip Select LOW to
Data Out Valid
2148
10
2149
5
tHzl8]
Chp Select HIGH to Data Out Off
0
toH
Address Unknown to Data Out
Unknown Time
0
tpo
Chip Select HIGH to
Power-Down Delay
2148
tpu
Chip Select WW to
Power-Up Delay
2149
55
ns
45
55
ns
35
45
55
ns
45
55
65
ns
15
20
25
ns
10
10
5
5
20
0
20
5
30
ns
0
20
5
30
ns
ns
30
ns
0
0
0
ns
WRITE CYCLE
twc
Address Valid to Address Do Not
Care (Write Cycle Time)
35
45
55
ns
twp l9]
Write Enable WW to
Write Enable HIGH
30
35
40
ns
tWR
Address Hold from Write End
5
5
5
ns
twzl8]
Write Enable WW to
Output in High Z
0
tow
Data-In Valid to Write Enable HIGH
20
20
20
ns
tOH
Data Hold Time
0
0
0
ns
tAS
Address Valid to
Write Enable WW
0
0
0
ns
tcwl9]
Chip Select LOW to
Write Enable HIGH
30
40
50
ns
towlS]
Write Enable HIGH to
Output in Low Z
0
0
0
ns
tAW
Address Valid to End of Write
30
35
50
ns
Noles:
6. Chip deselected greater than 55 ns prior to selection.
7. Chip deselected less than 55 ns prior to selection.
8. At any given temperature and voltage condition, tHZ is less than t{Zfor
all devices. Thansition is measured ±500 m V from steady state voltage
with specified loading in part (b) of AC 'lest Loads.
10
9.
2-8
0
15
0
20
ns
The internal write time of the memory is defined by the overlap of CS
WW and WEWW. Both signals mnstbeWW to initiate a write and
eithersignalcanterminateawritebygoingHIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
.
CY2148/CY21IA8
CY2149/CY21IA9
;~PRF.SS
-==:!!!!!!:.r
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. d lO, 11]
~~_IRC_------.*_
ADDRESS
1=IOHA~
J
DATA OUT
PREVIOUS DATA VALID
1
XX>K===============D=A=T=A=V=A=L1=D============
2148-5
Read Cycle No. 2[10, 12]
IRC
'~
~
lACS
f-
IL2
DATA OUT
HIGH IMPEDANCE
X)V
~Ipu
1HZ
=j
DATA VALID
HIGH
IMPEDANCE
/
I
~tpo
Vcc
~ CC
I
SUPPLY
CURRENT
50%
ISB
2148-6
Write Cycle No.1 (WE Controlled)
~-----------------------Iwc ------------------------~
ADDRESS
i--------Icw
---------1
~--------------------- ~w ------------------~~
14------ Iwp - - - - . {
~----tM ----~
,----------------
----~--------------~~~
loW
DATAI/O
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
DATA-IN VALID
Iwz=j
DATA 1/0 --------D-A-T-A-U-N-D-E-FI-N-ED-------
>
HIGH
IMPEDA~~Ei"'-------2148-7
Notes:
10. WE is HIGH for read cycle.
11. Deviceiscontinuouslyselected,CS = VILo
12. Address valid prior to or coincident with CS transition Ww.
13. lfCSgoesHIGHsimultaneouslywithWEHIGH,theoutputremains
in a high-impedance state.
2-9
•
CY2148/CY21IA8
CY2149/CY21IA9
~
1& ·~PRFSS
F
SEMICONDUC1OR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled) [13]
~----------------------- twe ------------------------~
ADDRESS
,-----------<~--------- tscs -----------""1 _----1-------+-----,
low
DATA IN
_
DATA OUT
DATA-IN VALID
_ _ _ _ _- - J
twz~
_
_ _
DATA UNDEFINED
HIGH IMPEDANCE
lI-----....:.-.,,;...-----------2148-8
Ordering Information
Speed
(ns)
35
45
55
Speed
(ns)
35
45
55
Package
lYPe
Operating
Range
CY214S-35PC
P3
Commercial
CY214S-35DC
D4
CY214S-45PC
P3
CY214S-45DC
D4
CY214S-45DMB
D4
Military
CY214S-55PC
P3
Commercial
CY214S-55DC
D4
CY214S-55DMB
D4
Ordering Code
Package
lYPe
Operating
Range
CY2149-35PC
P3
Commercial
CY2149-35DC
D4
Ordering Code
Speed
(ns)
35
Commercial
45
55
Speed
(ns)
Military
CY2149-45PC
P3
CY2149-45DC
D4
CY2149-45DMB
D4
Military
CY2149-55PC
P3
Commercial
CY214S-55DC
D4
CY214S-55DMB
D4
35
45
Commercial
55
Military
2-10
Package
lYPe
Operating
Range
CY21lAS-35PC
P3
Commercial
CY21lAS-35DC
D4
Ordering Code
CY21lAS-45PC
P3
CY21lAS-45DC
D4
CY21lAS-55PC
P3
CY21lAS-20DC
D4
Package
Commercial
Commercial
1YPe
Operating
Range
CY21lA9-35PC
P3
Commercial
CY21lA9-35DC
D4
Ordering Code
CY21lA9-45PC
P3
CY21lA9-45DC
D4
CY21lA9-55PC
P3
CY21lA9-55DC
D4
Commercial
Commercial
CY2148/CY21L48
CY2149/CY21L49
~~
_rcyPRFSS
-=-.F
SEMICONDUClDR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
•
DC Characteristics
Parameters
Subgroups
IOH
1,2,3
IOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB[14]
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9,10,11
tAA
7,8,9,10,11
tACSl[14]
7,8,9,10,11
tACS2[14]
7,8,9,10,11
tACS[15]
7,8,9,10,11
tOH
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
twp
7, 8, 9, 10, 11
tWR
7, 8, 9, 10, 11
tDW
7, 8, 9, 10, 11
tDH
7, 8, 9, 10, 11
tAS
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
Notes:
14. CY2148 only.
15. CY2149 only.
Document#: 38-00024-B
2-11
CY6116
CYPRESS
SEMICONDUCTOR
2,048 x 8 Static RIW RAM
Features
Functional Description
• Automatic power-down when
deselected
The CY6116 is ahigh-perfonnance CMOS
Static RAM organized as 2048 words by 8
bits. Easymemoryexpansiol!kProvided by
an active LOW chip enable (CE) and active
LOW output enable (OE) and three-state
drivers. The CY6116 has an automatic
power-down feature, reducing the power
consumptionby 83% when deselected.
An active LOW write enable signal (WE)
controls the writing/reading operation of
the memory. When the chip enable (CE)
and write enable (WE) inputs are both
LOW, data on the eight data input/output
pins (1100 through 1107) is written into the
• CMOS for optimum speed/power
• Highspeed
- 35ns
• Low active power
- 660mW
• Low standby power
-110mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater
than 2001V electrostatic discharge
memory location addressed by the address
present on the address pins (At! through
A10). Reading the device is accomplished by
selectin~device andenablin~outputs,
CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions,
the contents of the location addressed by the
infonnation on address pins is present on the
eight data input/output pins.
The input/output pins remain in ahigh-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is
HIGH.
The CY6116 utilizes a die coat to insure alphaimrnunity.
Logic Block Diagram
Pin Configurations
DIP/SOl
Top View
A7
1
Vee
As
As
As
As
Po.,
WE
As
OE
A,.
A,
A,
Ao
vOn
CE
1/07
1/0"
1/0.
8
vOn
vo,
vo"
vo,
vo,
VO.
GND
vo"
6116-2
LCC
vo.
Top View
vo,
~.!f.!fJ(-9JfJf
o
As
1/0.
OE - -........J
vo"
A,
NC
NC
A,
1/0,
As
VO.
4 3 2 )1)282726
25
WE
24
OE
23
A10
22
21
10
20
11
19
12131415161718
NC
NC
CE
CY6ll6
vo,
6116-3
6116-1
Selection Guide
MaximumAccess Time (ns)
CY6116-35
CY6116-45
35
45
CY6116-55
55
MaximumOperating
Current(mA)
Commercial
120
120
120
Military
130
130
MaximumStandby
Current(mA)
Commercial
20
130
20
Military
20
20
20
2-12
20
.sz~
CY6116
.J.:: CYPRESS
_ . , SEMICONDUCTOR
Maximum Ratings
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 200 rnA
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°Cto + 150°C
Ambient Thmperaturewith
Power Applied ....................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto + 7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
Operating Range
Range
Commercial
Militaryll]
Ambient
'Illmperature
Vee
O°Cto + 70°C
5V± 10%
- 55°Cto + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel2]
CY6116
Description
Parameters
'Illst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrentl3]
Vee Operating Supply Current
VOH
VOL
Vrn
VIL
IIX
Ioz
los
lee
Max.
2.0
-3.0
Vee
0.8
V
V
V
V
-10
+10
+10
!LA
!LA
-300
rnA
120
130
20
20
rnA
0.4
GNDsVISVee
GND S VIS Vee,
Output Disabled
Vee = Max., VOUT = GND
Com'l
Mil
Com'l
Mil
Vcc=Max.
lOUT = ornA
Max. Vee,
CE~Vrn
Units
2.4
Vcc = Min., IOH = - 4.0 rnA
Vee = Min.,IoL = 8.0 rnA
AutomaticCE
Power-Down Current
ISH
Min.
rnA
Capacitance [4]
Description
Parameters
CIN
InputCapacitance
COUT
OutputCapacitance
'Illst Conditions
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperatoIe.
2. See the last page of this specification for Group A subgroup testing informatiou.
3.
4.
Max.
Units
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl4810
<>------'--.,
OUTPUT <>---..----+
fN
fN
30
PF
I
<>------'R1481!J
__.,
R2
2550
5PFI
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
3.0V - - - -_ _
R2
2550
(b)
(a)
Equivalent to:
=-----..L.
ALL INPUT PULSES
----+
OUTPUTo---....
THEVENIN EQUIVALENT
611&4
1670:
OUTPUT_l.73V
2-13
GND
611EH;
•
.#~NDUCfOR
Switching Characteristics
CY6116
Over the Operating Rangel2,S]
CY6116-35
Parameters
Description
Min.
Max.
CY6116-45
Min.
Max.
CY6116-55
Min.
Max.
Units
55
DS
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
35
45
35
5
55
45
5
ns
5
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
35
45
55
tOOE
OE LOW to Data Valid
15
20
2S
tLZOE
OE LOW to Low Z
tHZOE
OE IDGH to High Z[6]
tUCE
CE LOW to Low Z[7]
tHZCE
CEIDGHto HighZ[6,7]
tpu
CE LOW to Power-Up
tpD
CE IDGH to Power-Down
0
0
15
5
0
15
5
0
0
ns
20
ns
20
DS
ns
0
2S
20
ns
DS
5
20
15
DS
ns
2S
ns
WRITECYCLEl8j
Write Cycle Time
35
45
tseE
CE LOW to Write End
30
40
40
ns
tAW
Address Set-Up to Write EDd
30
40
40
DS
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
20
2S
ns
tso
Data Set-Up to Write End
15
20
2S
DS
tHO
Data Hold from Write EDd
0
tHZWE
WE LOW to High Z[6]
tUWE
WEHIGHtoLowZ
twe
0
15
0
Notes:
5. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and outputloading
of the specified IoUIoH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. 1tansition is measured ±500 mV from steady state
voltage.
7. At any given temperature and voltage condition, lHZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate awritebygoingHIGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
9.
10.
11.
12.
55
0
15
0
ns
DS
20
0
DS
DS
WE is HIGH for read cycle.
Device is continuously selected. OE, CE = VIL.
Address valid prior to or coincident with CE transition LOW.
Data I/O pins enter high-impedance state, as shown, when OE is held
LOW during write.
13. IfCE goes IDGH simultaneously with WEIDGH, the output remains
in a high-impedance state.
2-14
~
~~
CY6116
=-ii!CYPRESS
"'"""'""'" F
SEMICONDUCI'OR
Switching Waveforms
Read Cycle No. d 9,1O]
~~-----~-------*--1=V:~~ JXX>K:::::::::::::::D:AT:A:V:A:U:D::::::::::=
1
ADDRESS
tM
DATA OUT
PREVIOUS DATA
6116-6
Read Cycle No. 2[9,11]
tRC
"""'~
~
tACE
~"
~
100E
-3
- - tHZCE
~tLZOE-
HIGH IMPEDANCE
DATA OUT
tLZCE
VCC
SUPPLY
CURRENT
I---
:\.
HIGH
,
....:. IMPEDANC E
"//
DATAVAUD
.\.. \..
_tpo
tpu
50%
~ CC
I
__________ ;r50%
ISB
6116-7
Write Cycle No.1 (WE Controlled)[9,12]
twc
ADDRESS
=:)r
)(
!sCE
~ ~ "-
/
W////ffi ~
tHA-
lAw
!sA
tPWE
~
~~
~r
DATA IN
)(
DATA-IN VAUD
~ tHzwE
DATA 1/0
tHO ....
!so
14-
tlZWE
j---l: .
_ _ _:1.
~ _______--K_
HIGH IMPEDANCE
DATA UNDEFINED
6116-8
2-15
•
II)
::!iE
---H-I-G-H-IM-P-E-D-AN-C-E--------____
_
DAIA I/O _ ______________________________________
DATA UNDEFINED
. 6116-9
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBffiNT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
3]1.2
Icc
jl1.0
V
c
~ 0.8
~
0.6
V
./
V
o
w
N
::J 0.6
0.2
5.0
5.5
w
~
0.4
Vee = 5.0V
V1N = 5.0V
ISB
0.0
-55
6.0
1.4
1.6
j
1.3
j1.4
cw
1.2
cw
1.0
............
r-....
0.9
0.8
4.0
"""-"'-
125
fil
40
~
20
5a
0
0.0
1.0
2.0
4.5
5.0
--
::J
1.2
« 140
/
«
::;;
TA = 25°C
a: 1.0
t--
5.5
SUPPLY VOLTAGE (V)
6.0
az
a:
0.6
-55
25
80
z
60
en
~ 40
~
o
125
AMBIENT TEMPERATURE (OC)
2-16
5
:.::
./
I,.;'
3.0
"
4.0
/7
~ 100
I'Vee= 5.0V
0.8
"
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
!z
/
Vee = 5.0V
TA = 25°C)
OUTPUT VOLTAGE (V)
.s 120
N
1.1
25
NORMALIZED ACCESS TIME
vs. AMBffiNT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
«
::;;
a:
az
~
AMBIENT TEMPERATURE (OC)
SUPPLY VOLTAGE (V)
~
60
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
:::l
0.2
I---
ISB
g 120
~ 100
w
a:
~ 80
~
0
«
::;;
a:
az
4.5
~
.2 0.8
c
a:
~ 0.4
0.0
4.0
1.2
III
.::: 1.0
~
20
II
/
oII
0.0
/
Vee = 5.0V
TA= 25°C
/
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
---===
CYPREEiS
F SEMICONDUCTOR
-.-;:;~
CY6116
~
1YPical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
30.0
2 .5
25.0
w 2.0
520.0
0
~
Cl
«
:2
~ 15.0
z
w
1.0
0.5
0.0
0.0
1.0
--
2.0
~
3.0
SUPPLY VOLTAGE
Cl
/
4.0
10.0
5.0
5.0
/
/
M
35
45
55
w
Operating
Range
CY6116-35PC
Pll
Commercial
CY6116-35DC
D12
CY6116-35LC
L64
CY6116- 35DMB
D12
CY6116-35LMB
L64
CY6116-45PC
P11
CY6116-45DC
D12
CY6116-45LC
L64
CY6116-45DMB
D12
CY6116-45LMB
L64
CY6116-55PC
P11
CY6116-55DC
D12
CY6116-55LC
L64
CY6116-55DMB
D12
CY6116-55LMB
L64
1.2
N
::J
«
:2
1.1
0:
0
z
Vee = 4.5V
TA=25"C
400
600
Military
Commercial
Military
Commercial
Military
2-17
-
I
800 1000
CAPACITANCE (pF)
Package
1YPe
Ordering Code
Cl
I
200
Vee = 5.0V
TA = 25"C
VIN = 0.5V
1.3
.2
/
Ordering Information
Speed
(ns)
0
/
/
:;:
1.5
0:
0
~
en
N
::J
NORMALIZED Icc vs. CYCLE TIME
1.4
1.0
0.9
0.8
---
~
~
o
10
20
30
CYCLE FREQUENCY (MHz)
40
•
.7,~DUCTOR
CY6116
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
1,2,3
ICC
1,2,3
ISB
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9,10,11
tAA
7, 8, 9, 10, 11
tOHA
7,8,9,10,11
tACE
7,8,9, 10, 11
tDOE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7,8,9, 10, 11
tSA
7,8,9,10,11
tPWE
7,8,9, 10, 11
tSD
7,8,9, 10, 11
tHD
7,8,9,10,11
Document#: 38-00055-D
2-18
CY6116A
CY6117A
CYPRESS
SEMICONDUCTOR
Features
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• Highspeed
- 20ns
• Low active power
- 550mW
• Low standby power
-110mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater
tban 2001V electrostatic discharge
2048 X 8 Static R/W RAM
Readingthe device is accomplished byta~
Functional Description
chip enable (CE) and output enable (OE)
TheCY6116AandCY6117Aarehigh-per- LOW while write enable (WE) remains
formanceCMOS static RAMs organized as HIGH. Under these conditions, the contents
2048 words by 8 bits. Easy memory expan- ofthe memeory location specified on the adsion iSEovided by an active LOW chip en- dress pins will appear on the I/O pins.
able (CE) and active LOW output enable
(OE), and three-state drivers. The The I/O pins remain in high-impedance state
CY6116Aand CY6117Ahave an automat- when E!!!P enable (CE) is HIGH or write enicpower-down feature, reducingtbe power able (WE) is LOW.
consumption by 83%when deselected.
The CY6116A and CY6117A utilize a die
Writing to the device is accomplished when coat to insure alpha immunity.
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the II
o pins (I/Oo through I/07) is written into
the memory location specified on the address pins (Ao thorugh AlO)·
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
LCC
Top View
Vee
-t~~<~~.'f
A,
Ag
4 3 2 1 11 282726
WE
Ol':
A2
VOa
CE
1/0,
1/06
1/0.
1/0.
VOa
VO,
Vo,
VO,
A,a
A,
Ao
9
S
6
Ag
A2
NC
NC
A,
-
~
9
10
11
Ao
VOo
25
24
8116A
~~
21
20
19
12131415161718
VOs
GND
1/0,
6116A-2
6116A-3
VOs
LCe
1/0.
<~~~~~~
Top View
43 2 ,1;323130
VO.
CE
A,S
WE
A3
A2
A,
29Aa
~~ ~
25
WE
OE
Ao
10
11
24
23
A10
CE
NC
12
22
va.,
1/00
13
2'
1/0.
lias
va.,
Ol':
-
~ ~
1/0.
Ao
6116A-1
A2
9
A1
26
6117A
~
g ~~ ~~ gg'
6116A-4
Selection Guide
6116A-20
6117A-20
MaximumAccessTime(ns)
MaximumOperating
Current(mA)
Commercial
Maximum Standby
Current(mA)
Commercial
6116A-25
6117A-25
6116A-35
6117A-35
6116A-45
6117A-45
6116A-55
6117A-55
55
20
25
35
45
100
100
100
100
80
125
100
100
100
20
20
20
20
40
20
20
20
Military
40/20
Military
2-19
CY6116A
CY6117A
~
.jiL~NDUCTOR
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°C to + 150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied ta Outputs
inHighZState ........................ - 0.5Vto + 7.0V
DClnputVoItage ...................... - 3.0Vto + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage........................ >2OO1V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
Range
Commercial
MilitaryllJ
O°Cto + 70°C
Vee
5V:t 10%
- 55°Cta + 125°C
5V:t 10%
Electrical Characteristics Over the Operating Rangel2]
6116A-20
6117A-20
Description
Parameters
VOH
VOL
VIH
VIL
IIX
loz
los
Icc
ISBl
ISB2
'lest Conditions
Min. Max.
OutputHIGHVoItage
Output LOW Voltage
Input HIGH Voltage
Input WW Voltagel3]
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[4]
Vee Operating
Supply Current
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Automatic CE
Power-Down Current
-ITLlnputs
Max. Vee,
AutomaticCE
Power-Down Current
- CMOS Inputs
Max. Vee,
CE~ VIH - 0.3v,
2.4
CE~VIH
f= fMAX
Min.
2.2
-0.5
-10
-10
Com'l
Max.
Vee
0.8
+10
+10
6116A-55
6117A-55
Min. Max. Units
2.4
2.4
0.4
GND .$. VI.$. Vee
GND.$. VI.$. Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.
lOUT = ornA
f = fMAX = litRe
6116A -25,35,45
6117A-25,35,45
0.4
2.2
-0.5
-10
-10
Vee
0.8
+10
+10
0.4
2.2
-0.5
-10
-10
V
V
V
V
Vee
0.8
+10
+10
!lA
!lA
-300
-300
-300
rnA
100
100
125
80
100
rnA
20
20
rnA
20
20
rnA
20
20
Mil 125
135,45
Com'l
40
Mill25
135,45,55
Com'l
20
100
20
40
20
VIN~Vee-O.3V
or VIN.$. 0.3v,
Mil
f= 0
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
'lest Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Units
10
pF
10
pF
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. VIL (min.) = - 3.0V for pulse durations less than 30 ns.
4.
Not more than 1 output should be shorted atone time. Duration of the
short circuit should not exceed 30 seconds.
5. Thsted initially and after any design orprocess changes that may affect
these parameters.
2-20
CY6116A
CY6117A
AC Test Loads and Waveforms
R148Hl
5Vo----_.....,
OUTPUT
R14810
5Vo----_....,
30PFI
ALL INPUT PULSES
---+
0---"",---+
OUTPUTo---.....
5PFI
R2
2550
INCLUDING
JIGAND _
INCLUDING
JIG AND _
SCOPE -
SCOPE -
(a)
3.OV ----_Jr=----~
R2
--
(b)
6116A-5
THEVENIN EQUIVALENT
Equivalent to:
GND
2550
6116A-6
16m
OUTPUT 0 0 - -.........""""....- - - 0 0 1.73V
Switching Characteristics
Over the Operating Rangel2, 6]
6116A-20
Parameters
Description
Min.
Max.
6116A-25
Min.
Max.
6116A-35
Min.
6116A-45
Max. Min.
6116A-55
Max. Min.
Max. Units
READ CYCLE
25
20
45
35
55
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
20
25
35
45
55
ns
tDOE
OE LOW to Data Valid
10
12
15
20
25
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High z[7]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
20
35
25
5
5
3
8
3
5
5
10
8
0
0
0
20
20
5
0
20
ns
20
ns
20
ns
5
15
ns
0
25
ns
ns
3
15
15
ns
55
5
3
12
10
5
5
5
3
45
ns
25
ns
WRITE CYCLEl9]
twc
Write Cycle Time
20
20
25
40
50
tSCE
CELOWtoWriteEnd
15
20
25
30
40
ns
tAW
Address Set-Up to Write End
15
20
25
30
40
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
15
15
20
20
25
ns
tSD
Data Set-Up to Write End
10
10
15
15
25
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
WE LOW to HighZ
tLZWE
WE HIGH to LowZ
7
7
5
5
Notes:
6. Iest conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, andoutputloading
of the specified IOI)lOH and 30-pF load capacitance.
7. tHZOE, tHzCE, and tHZWE are specified with CL = 5 pF as in part (h)
of AC Iest Loads. Transition is measured ±500 m V from steady state
voltage.
8. At any given temperatnre and voltage condition, tHZCE is less than
tLZCE for any given device.
9.
10.
11.
12.
13.
14.
2-21
15
10
5
5
ns
ns
20
5
ns
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE ww. Both signals must be WWto initiate awrite and
eithersignalcanterminateawritebygoingHIGH.The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
WE is HIGH for read cycle.
Deviceiscontinuouslyselected.OE,CE = VIL.
Address valid prior to or coincident with CE transition Ww.
DataI/O pins enter high-impedance state, as shown, when OE is held
WW dnring write.
IfCEgoesHIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
CY6116A
CY6117A
~~
~J
SEMlCONDUCfOR
Switching Waveforms
Read Cycle No. 1[10, 11]
t=
ADDRESS
DATA OUT
PREVIOUS DATA
V~;~
~ ~
--=*XX*===============D=AT=A=V.=A=LI=D===========
6116A-7
Read Cycle No. 2[10, 12]
IRC
~~
}~
lACE
}~
~
IHZOE
IHZCE
IOOE
-
-ItzOE - -
HIGH IMPEDANCE
DATA OUT
ILZCE
Vee
SUPPLY
CURRENT
_=f50%
///
j
HIGH
'-' IMPEDANCE
DATA VALID
!'.."-"-"-
/
i---
_Ipu
Ipo
~ CC
I
50%
ISB
6116A-6
Write Cycle No.1 (WE Controlled)[9, 13]
lwe
ADDRESS ~ (
)(
---./
ISCE
~~ ~ ~
/
W//~W//h:I
IHA-
lAW
!sA
IPWE
~~
~c..
Iso
DATA IN
*'
IHO ....
)K
DATA VALID
I--
IHZWE
j
f-
ILZWE
1
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _ _
DA_T_A_U_N_D_E_FI_N_ED_ _ _ _ _ _ _..J>).-------~<""
_____
6116A-9
2-22
CY6116A
CY6117A
~
=.
~
~=CYPRESS
~, SEMICONDUC'TOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [9, 13, 14]
ADDRESS
----_1.----- ISCE
CE
---1-----------....
----I
,---~~----
_____________ 14--+---- IsD - - -.........
DATA IN
DATA·IN VALID
IHZWE
----I
~_'~>-I-H-IG-H-IM-P-E-DA-N-C-E--_ _ __
/
____________
DATA I/O _ _ _ _ _ _ _ _DATA
UNDEFINED
6116A-10
'iypical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
VS. SUPPLY VOLTAGE
1.4
m1.2
Icc
J3 1.0
V
c
w 0.8
~
g
NO~ZEDACCESST~
TIME
1.4
c 1.2
w
N
::J
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ........................... . >200 rnA
Operating Range
DC Voltage Apillied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . . . . . . .
Military
VOH
VOL
VIH
VIL
IJX
Ioz
los
Icc
IsBI
ISB2
5V± 10%
- 55°C to + 125°C
5V± 10%
Over the Operating Rangel3]
7CIOl-25
7CI02-25
Parameters
Vee
O°Cto + 70°C
Commercial
- 0.5V to + 7.0V
DCInputVoltagel1J .................... - 0.5Vto +7.0V
Current into Outputs (Low) .. . . . . . . . . . . . . . . . . . . . .. 20 rnA
Electrical Characteristics
Ambient
Thmperaturel2]
Range
Description
Thst Conditions
Min.
Output HIGH
Voltage
Input Load Current
GNDSVISVee
GNDSVISVee,
Output Disabled
Min.
Max.
2.4
V
0.4
V
2.2 Vee + 0.3
-0.3
0.8
-10
+10
2.2 Vee + 0.3
-0.3
0.8
-10
+10
2.2 Vee + 0.3
-0.3
0.8
-10
+10
-10
-10
-10
+10
+10
Units
V
V
+10
!J.A
!J.A
-300
-300
-300
rnA
Com'l
150
125
115
rnA
Mil
150
125
115
30
25
25
35
30
30
Com'l
10
10
10
Mil
10
10
10
Automatic CE Power- Max. Vce.
Com'l
Down Current
CELVIH,
-TTLInputs
VINL VIHor
Mil
VIN S VIL f = fMAX
Automatic CE Power- Max. Vee,
Down Current
CE L Vee - 0.3v,
- CMOS Inputs
VIN L Vee - O.3V
orVIN SO.3V,f=O
Max.
0.4
0.4
Vee = Max., VOUT = GND
Vee = Max.
lOUT = 0mA,
f = fMAX = 1/tRC
Min.
2.4
2.4
Vee = Min.,
IOH = -4.0rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
Input LOW VoJtagel 1]
Output Leakage
Current
Output Short
Circuit Current[4]
V ccOperatingSupply
Current
Max.
7CIOl-35
7CI02-35
7CIOl-35
7CI02-35
rnA
rnA
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Notes:
1. VIL (min.) = - 2.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
Max.
Units
10
pF
12
pF
Not more than I output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
2-27
LJ~
~'~~R
AC Test Loads and Waveforms
sv 0------__.,
R14llO.fl
OUTPUT
svo----_......,
R1411O.fl
0---.,....---+
30PFI
CY7CIOl
CY7CI02
PRELIMINARY
ALL INPUT PULSES
OUTPUTo---.,....---+
5PFI
R2
255.fl
INCLUDING
JIGAND _
SCOPE -
~
10%
R2
255.fl
...
INCLUDING
JIGAND _
SCOPE -
(a)
.s.5ns
Cl01-5
(b)
Cl01-4
THEVENIN EQUIVALENT
Equivalent to:
167.fl
OUTPUT_l.73V
Switching Characteristics
Over the Operating Rangef2, 6]
7CIOl-25
7CI02-25
Parameters
Description
Min.
Max.
7CIOl-35
7CI02-35
Min.
Max.
7CIOl-45
7CI02-45
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CELOWtoPower-Up
25
5
25
0
45
35
5
0
0
35
25
ns
ns
20
15
ns
ns
5
5
10
ns
45
35
5
5
CE HIGH to Power-Down
tpo
WRITECYCLE[9]
45
35
25
ns
ns
45
ns
twc
Write Cycle Time
25
35
45
ns
tsCE
CE LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
20
25
30
ns
tso
Data Set-Up to Write End
15
20
25
ns
tHO
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
5
tHZWE
WE LOW to HighZ[7, 8]
15
20
25
ns
tOWE
WE LOW to Data Valid (7C101)
20
25
30
ns
tDCE
CE LOW to Data Valid (7C101)
25
35
45
ns
tADV
Data Valid to Output Valid (7C101)
20
25
30
ns
Notes:
6. Thstconditions assume signal transition timeof5 nsor less, timing reference levelsofl.5V, input pulse levels ofO to 3.0V, andoutputIoading
of the specified ImJIoH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tUCE and tHZWE is less than tuWE for any given device.
S. tHZCE, and IHZWE are specified with a load capacitance of 5 pF as in
part (h) of AC Thst Loads. 'fransition is measured ±500 mV from
steady state voltage.
9.
2-28
ns
5
5
The internal write time of the memory is defined hy the overlap of CE
and WE LOW. CE and WE must be LOW tu initiate a write, and the
transition of any of these signals can terminate the write. The input
data set-up and hold timing should be refereoced to the leadiog edge
of the signal that terminates the write.
CY7CIOl
CY7CI02
o;;:F
===---~
PRELIMINARY
~ jt('!yPFl'SS
~,
SEMICONDUClOR
Switching Waveforms
Read Cycle No. 1[10, 11]
~
AD"'"
~
DATA OUT - - - - P - R - E V - ' ! 2 V :
3><><
*~
In
:!:
rovided by an active LOW chip enable
(CE), an active LOW output enable (OE),
and three-state drivers. The device has an
automatic power-down feature that reduces power consumption by more than
70% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the four I/O
pins (1/00 through 1/03) is then written into
the location specified on the address pins
(Aothrough A17)·
Logic Block Diagram
Reading from the device is accomplished by
taking chip enable (CE) and output enable
(OE) LOW while forcing write enable (WE)
HIGH. Under these conditions, the contents
of the memory location specified by the address pins will appear on the four I/O pins.
The four input/output pins (1/00 through II
03) are placed in a high-impedance state
when the device is deselected (CE HIGH),
the outputs are disable.!!{OEHIGH), orduringa write operation (CE and WE LOW).
The CY7CI06 is available in 32-pin leadless
chip carriers and standard 28-pin, 400-milwide DIPs and SOJs.
Pin Configurations
DIP/SOl
Top View
Vee
An
A'B
A,.
A,.
A,.
A7
A'2
An
Ae
Ae
Vo"
NC
A,o
A1
A2
A3
1/0.
a:
w
c
~
0
I/O:!
A7
~a:
vo,
~
As
I/O:!
I/O,
CE
OE
&lc
C106-3
Lee
Top View
Ao
A,
As
1/00
WE
GND
As
As
Ao
Ae
Ae
1/00
CE
NC
A7
Ae
Ae
WE
OE
An
A'B
A,.
A14
A,.
A'2
9
10
11
24
NC
NC
23
An
A,o
'2
NC
13
14
15
16
CE
OE
C106-1
GND
Vee
32
31
3
30
29
28
27
7
28
87C106 25
22
21
20
19
18
17
NC
Vo"
Vo"
VO,
1/00
WE
C106-2
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
7CI06-25
25
150
150
30
35
Commercial
Military
Commercial
Military
2-32
7CI06-35
35
125
125
25
30
7CI06-4S
45
115
115
25
30
~::Z
~= CYPRF.SS
F SEMICONDUCTOR
PRELIMINARY
CY7CI06
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Static Discharge Voltage ...................... .
(per MIL-STD-883, Method 3015)
Storage Temperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage on Vee Relative toGND[l] . - 0.5Vto +7.0V
Latch-UpCurrent ........................... .
DC Voltage AP8lied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . . . . . ..
Ambient
Thmperature[2]
Vee
O°Cto +70°C
5V± 10%
- 55°Cto +125°C
5V± 10%
Range
Commercial
- 0.5V to +7 .OV
Military
Over the Operating Range[3]
7CI06-25
Parameters
VOH
VOL
VIH
Description
OutputHIGH Voltage
Output LOW Voltage
Input LOW Voltage[1]
Ioz
Output Leakage
Current
Output Short
CircuitCurrent[4]
Icc
ISB1
ISB2
Thst Conditions
Min.
Input Load Current
Max.
2.4
Vee = Min., IOH = - 4.0 rnA
7CI06-35
Min.
2.2
Max.
2.4
7CI06-45
Min.
Vee
+ 0.3
2.2
Max.
2.4
0.4
0.4
Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
VIL
IIJ{
los
>200 rnA
Operating Range
DC Input Voltage[1] .................... - 0.5V to + 7.0V
Current into Outputs (LOW) .. . . . . . . . . . . . . . . . . . . .. 20 rnA
Electrical Characteristics
>2001V
Vee
+ 0.3
2.2
Units
V
0.4
V
Vee
+ 0.3
V
- 0.3
0.8
- 0.3
0.8
- 0.3
0.8
V
GND < VI < Vee
-10
+10
-10
+10
-10
+10
GND~VI~Vee,
-10
+10
-10
+10
-10
+10
tJA
tJA
-300
rnA
rnA
OutputDisabled
-300
-300
Com'l
150
125
115
Mil
Com'l
150
125
115
30
25
25
35
30
30
Vee = Max., VOUT = GND
V ceOperatingSupply
Current
Vee = Max.• lOUT = ornA,
f = fMAX = lItRC
Automatic CE PowerDown Current
-TTLInputs
Max. Ven CE ~ VIH,
VIN ~ VIH or VIN ~ VIL,
f= fMAX
Mil
Automatic CE PowerDown Current
- CMOS Inputs
Max. Vee, CE
Com'l
10
10
10
Mil
10
10
10
~ Vee
- 0.3v, VIN ~ Vee - O.3V
orVIN ~O.3V,f=O
rnA
rnA
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
COUT
OutputCapacitance
Thst Conditions
TA =25°C,f= 1 MHz,
Vee=5.0V
Max.
Units
10
pF
12
pF
Notes:
1. V IL (min.) = - 2.0V for pulse durations ofiess than 20 ns.
2. TA is the "instant on" case temperature.
4.
3.
5.
See the last page ofthis specification for Group Asubgroup testing infonnation.
2-33
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
"Iested initially and after any design or process changes that may affect
these parameters.
:~PRESS
6
PRELIMINARY
'SEMICONDUCTOR
CY7C106
AC Test Loads and Waveforms
R14800
5Vo----_.....,
R14800
5VD----_.....,
OUTPUTO---......---i
OUTPUTD---......---i
FI
30 P
INCLUDING
JIG AND _
5PFI
R2
2550
R2
----_JI""=----'3L-
GND
2550
INCLUOING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V
C106-5
(b)
C106-4
THEVENIN EQUIVALENT
167Q
OUTPUT OO-----'\",.
..'\O---.()O 1.73V
Switching Characteristics
Over the Operating Rangel2,6]
7CI06-2S
Parameters
Description
Min.
Max.
7CI06-3S
Min.
Max.
7CI06-4S
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
25
35
45
ns
tDOE
OE LOW to Data Valid
10
15
20
ns
tLZOE
OE LOW to Low Z
tHZOE
OEHIGHtoHighZ[7]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
25
35
25
5
45
35
5
0
5
0
5
5
0
20
0
35
ns
ns
5
0
25
ns
20
15
10
ns
ns
0
15
10
ns
45
ns
ns
45
ns
WRITE CYCLW9,lO]
twc
Write Cycle Time
25
35
45
ns
tSCE
CE LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
20
25
30
ns
tso
Data Set-Up to Write End
15
20
25
ns
tHO
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
WE LOW to High Z[7,8]
5
5
5
tHZWE
15
Notes:
6. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading
of the specified IOI}lOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with aload capacitance of5 pF
as in part (b) ofACThst Loads. 1fansitionismeasured ±500mVfrom
steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than trzWE for any given device.
9.
20
ns
25
ns
The internal write time of the memory is defined by the overlap of CE
and WE Law. CE and WE must be WW to initiate a write, and the
transition of either of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE WW) is the sum of tHZWE and IsD.
2-34
~
=-...~
PRELIMINARY
== .;; ~NDUClDR
Switching Waveforms
Read Cycle No. 1[11, 12]
ADDRESS
€
----
DATA OUT
*- •
IRC
-I
~ IOHA ~
PREVIOUS DATA VALID
JXX
CY7CI06
*===============D=A=:r=A=VA=L=I=D===========
C106-6
Read Cycle No.2 (OE Controlled)[ll, 13]
ADDRESS
=x
K
IRC
~~
~
lACE
k'
'\..
-
DATA OUT
ILZOE--
HIGH IMPEDANCE
ILZCE
Vee
SUPPLY
CURRENT
~Ipu
IHZOE - -
I
IOOE
1////
~'\.'\.'\."
-
DATA VALID
HIGH
IMPEDANC E
/
~tpo-
....L.
11
tHZCE---
50%~
50%
~
ICC
~ ISB
C106-7
Write Cycle No.1 (CE Controlled)14,15]
~---------------------Iwc ------------------------~
ADDRESS
--+-----------"'" "'--- tsCE -----1_----+---~-----------------~w------------------~-
,........................................~,.....~ 1---------- IPWE ----------~
"'1___
; ------- Iso
DATA I/O
-------------------...r:"
Notes:
11. Device is continuously selected. OEand CE = Vn..
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition ww.
DATA VALID
.1.
IHO
j"'________
.)j
C106-8
14. IfCEgoesHIGHsimultaneouslywithWEgoingIDGH,theoutputremains in a high-impedance state.
15. DataI/O is high impedanceifOE = VIH.
2-35
~~
='~NDUClDR
PRELIMINARY
CY7CI06
Switching Waveforms
Write Cycle No.2 (WE Controlled, OE IDGH During Write)[14,15]
~----------------------Iwc----------------------~
ADDRESS
WE ----~------~----~~~,
1 4 - - - - IPWE - - - - - * I
,-----------------
DATA I/O
DATAVAUD
C10B-9
Write Cycle No.3 (WE Controlled, OE LOW)[1O,15]
ADDRESS
WE ----~------~~~
~---
DATA I/O
Iso
----~-~
DATAVAUD
C10B-10
Truth Thble
CE
OE
H
X
X
HighZ
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (Icc)
WE
Mode
1/00 -1/0 3
Power
L
X
L
Data In
Write
Active (Icd
L
H
H
HighZ
Selected, Outputs Disabled
Active (Icd
2-36
&
-.
i~
PRELIMINARY
~=CYPRESS
~jF SEMlCONDUcroR
Ordering Infonnation
Speed
(ns)
25
Package
lYPe
Operating
Range
CY7C106- 25DC
D41
Commercial
CY7C106-25LC
L75
Ordering Code
CY7C106-25PC
35
V28
CY7C106- 25DMB
D41
CY7C106- 25LMB
L75
CY7C106-35DC
D41
CY7C106-35PC
45
Commercial
P41
V28
CY7C106- 35DMB
D41
CY7C106- 35LMB
L75
CY7C106-45DC
D41
CY7CI06-45LC
L75
CY7C106-45PC
P41
CY7C106-45VC
V28
CY7C106-45LMB
Military
L75
CY7C106-35VC
CY7C106-45DMB
DC Characteristics
P41
CY7C106-25VC
CY7C106-35LC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
D41
Military
Commercial
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VJH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
IsB2
1,2,3
Switching Characteristics
Parameters
Snbgronps
READ CYCLE
Military
L75
tRC
7, 8, 9, 10, 11
tAA
7,8,9,10,11
tOHA
7,8,9,10,11
tACE
7, 8, 9, 10, 11
tOOE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7,8,9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7, 8, 9, 10, 11
Document#: 38-00149-B
2-37
CY7CI06
•
CY7CI07
PRELIMINARY
CYPRESS
SEMICONDUCTOR
1M X 1 Static RIW RAM
Features
Functional Description
• ffighspeed
- tAA=25ns
• CMOS for optimum speed/power
• Low active power
- 825mW
• Low standby power
-165mW
• Automatic power-down when
deselected
• 'ITL-compatible inputs and outputs
The CY7C107 is a high-performance
CMOS static RAM organized as 1,048,576
words by 1 bit. Easy memory expansion is
Rrovided by an active LOW chip enable
(CE) and three-state drivers. The device
has an automatic power-down feature that
reduces power consumption by more than
70% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location
specified on the address pins (Ao through
A19).
Logic Block Diagram
Reading from the device is accomplished by
taking c~enable (CE) LOW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified by the address pins will appear
on the data output (DOUT) pin.
The output pin (DOUT) is placed in a highimpedance state when the device is deselecte'!.i..CE HIGH) or during a write operation(CEandWELOW).
The CY7C107 is available in 32-pin leadless
chip carriers and standard 28-pin, 400-milwide DIPs and SOJs.
Pin Configurations
DIP/SOJ
Top View
D,N
Vee
......
......
A4
A7
Ao
A,
...As
......Ao
...
......
NC
A,
Dour
Ao
D,N
A7
CE
GND
Cl07-3
LCe
Top View
CE
A,o
Al1
A'2
WE
3
29
NC
A,.
A,.
A,.
Cl07-1
NC
A,.
A17
A,.
A,.
NC
Dour
WE
GND
32
31
30
28
27
7
26
87Cl07 25
9
10
11
12
13
14
15
18
24
23
22
21
20
19
18
17
Vec
......
......
A4
NC
A7
...
NC
A2
NC
A,
Ao
D,N
CE
Cl07-2
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
7CI07-25
25
150
150
30
35
Commercial
Military
Commercial
Military
2-38
7CI07-35
35
125
125
25
30
7CI07-45
45
115
115
25
30
~
=--
.~
~~
F
PRELIMINARY
CYPRF.SS
SEMICONDU(''TOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage on Vee Relative to GND!!] . - 0.5Vto +7.0V
DC Voltage ApR lied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . . . . . . . - O.5V to + 7.0V
DClnputVoltage[1] .................... - O.5Vto +7.0V
Current into Outputs (Low) .. . . . . . . . . . . . . . . . . . . . .. 20 rnA
CY7CI07
Static Discharge Voltage ....................... . >2oo1V
(per MIL-STD-883, Method 3015)
Latch-UpCUrrent ........................... . >200 rnA
Operating Range
Ambient
Thmperature[2]
Vee
O°Cto +70°C
5V± 10%
- 55°C to + 125°C
5V± 10%
Range
Commercial
Military
Electrical Characteristics!3] Over the Operating Range
7CI07-25
Parameters
Description
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IJX
Input LOW Voltage[1]
Thst Conditions
-0.3
-10
-10
GND~VI~Vee
ISB!
Automatic CE
Power-Down Current
-TTLInputs
Max.. Vee, CE ~ VIH,
VIN ~VIH or VIN ~ VIL,
f=fMAX
IsB2
AutomaticCE
Power-Down Current
- CMOS Inputs
Max. Vee,
Icc
7CI07-35
Min.
GND~VI~Vee,
Output Disabled
Vee = Max., VOUT = GND
Max.
2.4
0.4
2.2
Vee = Max., lOUT =
OrnA, f = fMAX = lItRe
los
Max.
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Input Load Current
Output Leakage
Current
Output Short
CircuitCUrrent[4]
Vee Operating
Supply CUrrent
Ioz
Min.
Vee
+ 0.3
0.8
+10
+10
7CI07-45
Min.
0.4
2.2
- 0.3
-10
-10
Max.
Units
0.4
V
V
V
2.4
Vee
+ 0.3
0.8
+10
+10
2.2
- 0.3
-10
-10
Vee
+0.3
0.8
+10
+10
V
!-IA
IlA
-300
-300
- 300
rnA
Com'l
Mil
Com'l
150
150
30
125
125
25
115
115
25
rnA
Mil
35
30
30
Com'l
10
10
10
Mil
10
10
10
rnA
rnA
CE~ Vee-0.3V,VIN~
Vee- O.3Vor
VIN ~ 0.3v, f=O
Capacitance [5]
Parameters
Thst Conditions
Description
CIN
InputCapacitance
CoUT
Output Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Units
10
pF
12
pF
Notes:
4.
1.
VIL (min.) = - 2.0V for pulse durations ofless than 20 ns.
2.
TA is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
5.
2-39
Not more than 1 output should be shorted atone time. Duration of the
short circuit should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
#~~PRffiS
PRELIMINARY
~_, SEMICOIDUCfOR
CY7CI07
AC Test Loads and Waveforms
R14BOIl
5Vo----_......,
R14800
5V 0 - - _......__,
OUTPUTo---......- - t
30PFI
5PFI
R2
25511
INCWDING
JIG AND _
SCOPE -
::~OO%
R2
25511
INCLUDING
JIG AND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo---......-~
(b)
C107-5
C107-6
THEvENIN EQUIVALENT
16711
OUTPUT 0-0---'1.."'
.........- - 0 0 1.73V
Switching Characteristics[2,61 Overtbe Operating Range
7CI07-25
Parameters
Min.
Description
Max.
7CI07-35
Min.
Max.
7CI07-45
Min.
Max.
Units
READ CYCLE
35
25
tRC
Read Cycle Time
tAA
Address to Data Valid
toHA
Data Hold from AddressChange
5
tACE
tIZCE
CE LOW to Data Valid
CE LOW to Low Z[71
5
IIlZCE
CE HIGH to High Z[7, 81
tl'U
CE LOW to Power-Up
5
5
0
45
15
0
ns
ns
20
0
ns
ns
45
35
25
ns
ns
5
5
10
ns
45
35
25
CE HIGH to Power-Down
tPD
WRITECYCLE[91
45
35
25
ns
twc
Write Cycle Time
25
35
45
ns
tSCE
CE LOW to Write End
25
Address Set-Up to Write End
tRA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Widtb
25
30
30
0
0
30
ns
tAW
tSD
Data Set-Up to Write End
20
20
0
0
20
15
20
25
ns
tHD
Data Hold from Write End
WE HIGH to Low Z[7]
0
5
ns
trzWE
0
5
tHzWE
WELOWtoHighZ[7,81
25
0
0
0
5
15
Notes:
6. 'lbst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperatore and voltage condition, lHZCE is less than
tlZCE and tHZWE is less than tlZWE for any given device.
8. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC 'lbst Loads. 'fransilion is measured ±SOO mV from
steady state voltage.
9.
2-40
20
ns
ns
ns
ns
ns
25
ns
The internal write time of the memory is defined by the overlap ofCE
WW and WE Ww. CE and WE must be LOWto initiate awrite, and
the transition of any of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
PRELIMINARY
Switching Waveforms
Read Cycle No. 1[10, II]
ADDRESS
€
IRC
--~
DATA OUT
PREVIOUS DATA
CY7C107
1M
V::~~ JXX
-I
*===============D=A=:r=A=V=A=U=D===========
C107-4
Read Cycle No. 2[11, 12]
)t'
ADDRESS
lAC
~~
/
lACE
I--DATA OUT
VCC
4.zCE
HIGH IMPEDANCE
/
DATA VALID
.'\..'\..'\..'\..
f---
--d
HIGH
IMPEDANCE
/
_Ipo __
Ipu-
}~
SUPPLY
CURRENT
50%~
50%
ICC
K - - I SB
C107-6
Write Cycle No.1 (CE Controlled)[13]
lwe
ADDRESS
~~
)K
lSA
!sCE
~~
}'r
IHA-
lAW
IPWE
~~~~~
///////////h
Iso
DATA IN
)(
DATA VALID
IHO ...
~t'
HIGH IMPEDANCE
DATAOUT----------------------------------------------------------------------C107-5
Notes:
10. Device is continuously selected. CE = VIL
11. WE is HIGH for read cycle.
12. Address valid prior to or coiocident with CE transition Ww.
13. IfCEgoesHIGHsimultaneouslywithWEgoiogHIGH,theoutputremaios in a high-impedance state.
2-41
~.~
CYPRESS
~.;,
,
PRELIMINARY
SEMlCGlDUcroR
CY7CI07
Switching Waveforms
Write Cycle No.2 (WE Controlled)[13]
twc
~E
ADDRESS
)(
~
lseE
~ ~~
ff/ffi W///#
tAW
tHA-
tSA
tPWE
~~t-..
/~
tHD ...
tSD
~,(
DATA IN
I--
tHZWE
-----------------j)
DATA OUT
~,(
DATA VALID
DATA UNDEFINED
.•
-
tLZWE
1r----
HIGH IMPEDANCE
C107-7
Truth Table
CE WE
H
X
L
L
DOUT
Mode
Power
HighZ
Power-Down
Standby (ISB)
H
Data Out
Read
Active (led
L
HighZ
Write
Active (led
2-42
~
;i=
CYPRF.SS
PRELIMINARY
CY7CI07
. ' SEMICONDUCTOR
Ordering Information
CY7C107-25DC
Package
lYPe
D41
CY7C107-45DC
Package
lYPe
D41
CY7C107 - 25LC
L75
CY7C107-45LC
L75
CY7C107-25PC
P41
CY7C107-45PC
P41
CY7C107-25VC
V28
CY7CI07-45VC
V28
CY7C107-25DMB
D41
CY7C107-45DMB
D41
CY7C107 -45LMB
L75
Speed
(ns)
25
35
Ordering Code
CY7C107-25LMB
L75
CY7C107-35DC
D41
CY7C107-35LC
L75
CY7CI07-35PC
P41
CY7CI07-35VC
V28
CY7C107-35DMB
D41
CY7C107 - 35LMB
L75
Operating
Range
Speed
(ns)
Commercial
45
Military
Ordering Code
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
VOH
1,2,3
Parameters
Subgroups
READ CYCLE
VOL
1,2,3
tRC
VIH
1,2,3
tM
7,8,9, 10, 11
VJLMax.
1,2,3
tOHA
7,8,9, 10, 11
IIX
1,2,3
tACE
7,8,9,10,11
7,8,9, 10, 11
Ioz
1,2,3
Icc
1,2,3
twc
ISBI
1,2,3
tSCE
7,8,9,10,11
ISB2
1,2,3
tAW
7,8,9, 10, 11
WRITE CYCLE
Document #: 38-00150-B
2-43
7,8,9, 10, 11
tHA
7,8,9,10,11
tSA
7,8,9, 10, 11
tPWE
7,8,9,10,11
tSD
7, 8, 9, 10, 11
tHD
7,8,9,10,11
Operating
Range
Commercial
Military
CY7CI08
CY7CI09
PRELIMINARY
CYPRESS
SEMICONDUCTOR
131,072 X 8 Static RIW RAM
Features
Functional Description
• Highspeed
- tAA=25ns
• CMOS for optimum speed/power
• Low active power
- 825mW
• Low standby power
-165mW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
• Easy meDlQ!l' expansion with CEl>
C~, and OE options
The CY7CI08 and CY7C109 are high-performanceCMOS static RAMsorganizedas
131,072 words by 8 bits. Easy memory expansion~rovided by an active WW chip
enable (CEI), an active HIGH chip enable
(C~), an active LOW output enable (OE),
and three-state drivers. Both devices have
an automatic power-down feature that reduces power consumption by more than
70% when deselected.
Writing to the device is accomplished by
takin~ enable one (CEI) and write enable (WE) inputs WW and chip enable
two (CEz) input HIGH. Data on the eight
I/O pins (1/00 through 1/07) is then written
into the location specified on the address
pins (An through AI6).
Reading from the device is accomplished by
takingE!!!p enable one (CEI) and output enable (OE) WW while forcing write enable
(WE) and chip enable two (CE2) HIGH. Under these conditions, the contents of the
memory location specified by the address
pins will appear on the I/O pins.
The eight input/output pins (1/00 through
I/~) are placed in a high-im~ance state
when the device is deselected (CEI HIGH or
CEz WW), the outputs are disabled (Q.E
HIGH), or during a write operation (CEI
Ww, CE2 HIGH, and WE LOW).
The CY7C108 is available in a 32-pin rectangular leadless chip carrier and standard
600-rnil-wide cerDIPs. The CY7C109 is
available in standard 400-mil-wide DIPs and
SOJs.
Logic Block Diagram
Pin Configurations
SOJ
DIP
ThpView
ThpView
vee
Vee
A7
Aa
Aa
Ao
VOO
A,.
A,
A,
A,
VO,
Ao
A,
1/02
~
!!
I/O.
~
A,.
A14
A'2
A7
Aa
Aa
Aa
Aa
A"
A,.
A,
A,
A,
eE,
Ao
1/07
va,
V02
I/O.
DE
A,.
CE1
I/~
VOo
va.
I/o"
va,
vo.
I/O,
I/Oa
GND
VOo
I/O.
CE1
CEo
I/~
WE
C108-1
A,.
CEo
WE
A,.
6
Aa
Aa
A"
DE
A,.
vOo
I/o"
VO,
GND
I/Oa
C108-4
C108-3
LCe
va,
A7
As
DE
5
6
A,.
CEo
WE
A13
ThpView
NC
A,.
A,.
A'2
A7
Aa
Aa
A,.
A,
Ao
A,
Ao
vOo
va,
I/O.
GND
1
Vee
32
31
30
A15
CEo
29
WE
28
27
7
26
8 7C108 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A'3
4
5
Aa
Aa
A"
DE
A,.
eEl
1/07
I/O.
VOS
VO,
va,
C108-2
2-44
CY7C108
CY7C109
~
:SiP
~
~ .Ij ~~DUCIDR
PRELIMINARY
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
7CI08-25
7CI09-25
25
150
150
30
35
Commercial
Military
Commercial
Military
7CI08-35
7CI09-35
35
125
125
25
30
•
7CI08-45
7CI09-45
45
115
115
25
30
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto + 125°C
Supply Voltage on Vee Relative to GND[1] - O.5V to + 7.0V
DC Voltage ApBlied to Outputs
in High ZState 1] ....................... - O.5Vto + 7.0V
DClnputVoltagel 1] .................... - O.5Vto + 7.0V
CurrentintoOutputs(Low) ....................... 20rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200mA
Operating Range
Ambient
Thmperature[2]
Range
Commercial
Military
Vee
W± 10%
5V± 10%
O°Cto + 70°C
- 55°C to + 125°C
Electrical Characteristics Over the Operating Rangel3]
7CI08-25
7CI09-25
Parameters
Description
Thst Conditions
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
Ilx
loz
Input LOW Voitagel 1J
Input Load Current
Output Leakage
Current
Output Short
Circuit Currentf4]
Vee Operating Supply
Current
los
lee
IsB1
ISB2
Min.
2.2
-0.3
-1
-5
GND <
IRC
~"
--.-../
~
~
~
lACE
~
14DATA OUT
V~
.
/'{.
IHZOElODE
ILZOE-
HIGH IMPEDANCE
-Ipu
=Jt
IHZCE -
DATAVAUD
."""
ILZCE
SUPPLY _ _ _ _ _ _ _
CURRENT
-
I+ILL/LL
~ Ipo
50%
HIGH
IMPEDANC E
"'
~ ICC
50%
ISB
C1OB-B
Write Cycle No.1 (CEI or CEl Controlled)[14, 15J
~------------------------- Iwc --------------------------~
ADDRESS
---+------------""' ""1---14-----CE2
lSA
-----~
DATA I/O
.1-----+-----
.,_ _ _ _ _ _ _,
---t-------------'
14---- IsCE - - - - I '------ir----~--------------~w--------------~~-~-------- IPWE
WE
ISCE - - - - t
-----------1
.. ..
~~uu~~~~~------------------~~~~~
"'\:1------- Iso - - -.......
~
~
----------------!(~-----D-A-JA-VA-L-ID----_ lI-------C1OB-9
Notes:
11. Device is continuously selected. OE, CEI = VIL CE2 = Vrn.
12. WE is mGH for read cycle.
13. Address valid prior to or coincident with CEI transition LOW and
~ transition HIGH.
14. DataI/O is high impedance ifOE = Vrn.
15. If eEl goes HIGH or CE2 goes LOW simultaneously with WE going
mGH, the output remains in a high-impedance state.
2-47
t[j~~NDUCTOR
CY7CI08
CY7CI09
PRELIMINARY
Switching Waveforms
Write Cycle No.2 (WE Controlled, OE IDGH During Write)[14,15]
~---------------------- twc----------~----------~
ADDRESS
WE
--...;....--....;;;.;,.....---.~~~
14----
1+-------_
DATA 1/0
C~~C:2~62.~t"--1'
tPWE ----~
tSD
,--------
-----1_-1
____-':D~A~T~A-~IN~Vv.:.A~U~D~_ _ _./I------C108-10
Write Cycle No.3 (WE Controlled, OE LOW) [10, 15]
ADDRESS
WE-----~~~~
~-----tPWE-------~
~---------
IsD
DATAI/O
DATAVAUD
C10B-11
2-48
~~PRESS
EZ F SEMICONDUCTOR
PRELIMINARY
Truth Table
1/0 0 -I/O,
CEI
CEz
OE
WE
H
X
X
X
HighZ
Power-Down
Mode
Standby (lSB)
Power
X
L
X
X
HighZ
Power-Down
Standby (lSB)
L
H
L
H
Data Out
Read
Active (led
L
H
X
L
Data In
Write
Active (led
L
H
H
H
HighZ
Selected,OutputsDisabled
Active (led
Ordering Information
Speed
(ns)
25
35
45
Speed
(ns)
25
35
45
Ordering Code
Package
'lYPe
Operating
Range
Commercial
CY7C108 - 25DC
D50
CY7C108-25LC
L75
CY7C108-25DMB
D50
CY7C108-25LMB
L75
CY7C108-35DC
D50
CY7C108-35LC
L75
CY7C108-35DMB
D50
CY7C108-35LMB
L75
CY7CI08-45DC
D50
CY7CI08-45LC
L75
CY7C108-45DMB
D50
CY7C108-45LMB
L75
Military
Commercial
Military
Commercial
Military
Package
'lYPe
Operating
Range
CY7CI09-25DC
D46
Commercial
CY7C109-25PC
P43
Ordering Code
CY7C109-25VC
V33
CY7CI09-25DMB
D46
Military
CY7C109-35DC
D46
Commercial
CY7CI09-35PC
P43
CY7CI09-35VC
V33
CY7C109-35DMB
D46
Military
CY7C109-45DC
D46
Commercial
CY7CI09-45PC
P43
CY7CI09-45VC
V33
CY7CI09-45DMB
D46
Military
2-49
CY7CI08
CY7CI09
•
.7.~NDUcroR
PRELIMINARY
NUlJTARYSPECnnCATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB!
1,2,3
IsB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9,10,11
tAA
7, 8, 9, 10, 11
toHA
7, 8, 9, 10, 11
tACE
7,8,9,10,11
tDOE
7,8,9,10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7, 8, 9, 10, 11
tAw
7,8,9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9, 10, 11
tPWE
7,8,9, 10, 11
tSD
7,8,9, 10, 11
tHO
7,8,9,10, 11
Document #: 38-00140-C
2-50
CY7CI08
CY7CI09
CY7C122
CYPRESS
SEMICONDUCTOR
256 X 4 Static R!W RAM
Features
Functional Description
• 256 x 4 static RAM for control store in
high-speed computers
• CMOS for optimum speed/power
• Highspeed
-15 ns (commercial)
- 25 ns (military)
The CY7C122 is a high-performance
CMOS static RAM organized as 256words
by 4 bits. Easy memory expansion is provided by an active LOW chip select one
(CS1) input, an active HIGH chip select
two (CS2) input, and three-state outputs.
An active WW write enable input (WE)
controls the writing/reading operation of
the memory. When the ~ select one
(CSt) and write enable (WE) inputs are
WW and the chip select two (CS2) input is
lllGH,the information on the four data inputs (Do to D3) is written into the addressed memory word and the output circuitry is preconditioned so that the correct
data is present at the outputs when the
write cycle is complete. This precondition-
• Lowpower
-330 mW (commercial)
-495 mW (military)
• Separate inputs and outputs
• 5-volt power supply::!: 111% tolerance,
both commercial and military
• Capable of withstanding greater than
2001V static discharge
• TTL-compatible inputs and outputs
ing operation insures minimum write recovery times by eliminating the "write recoveryglitch".
ReadiES is performed with the chip select
one (CSt) input is Ww, the chi~lect
two input (CS2) and write enable (WE) inputs are HIGH, and the output enable
(OE) input is LOW. The information
stored in the addressed word is read out on
the four non-inverting outputs (00 to 03).
The outputs of the memory go to an active
high-i!!!Pedancestate whenever chip select
one (CSt) is HIGH, chi~ect two (CS2)
is Ww, output enable (OE) is HIGH, or
during the writing operation when write
enable (WE) is LOW.
Pin Configurations
Logic Block Diagram
SOIC
DIP
Top View
Top View
Vee
Vee
CS2
CS,
WE
Ao
As
As
~
~
A2
A,
WE
CS,
WE
CS,
4
DE
DE
A,
A7
CS2
Oa
Oa
OND
Do
03
DE
CS2
Oa
03
Oa
00
0,
NC
02
00
0,
0,
C122·2
02
0,
NC
C122-2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
O°Cto +70°C
Vee
5V± 10%
- 55°Cto +125°C
5V± 10%
Over the Operating Rangef2]
Description
7C122-25
7C122-35
Min.
Max.
7C122-15
Min.
Max.
Thst Conditions
VOH
VOL
Output HIGH Voltage
Vee = Min., IOH = - 5.2 rnA
Output LOW Current
Vee = Min., IOL = 8.0 rnA
Vrn
Input HIGH Level
VlL
IIX
VCD
Input LOW Level
Input Load Current
Input Diode Clamp
Voltage
loz
Output Current (High Z)
VOL 5 VOUT 5 VOH,
Output Disabled
los
Output Short Circuit
Currentl4]
Vee = Max.,
VOUT= GND
Commercial
Military
Power Supply Current
Vee = Max.,
lOUT = ornA
Commercial
Military
Icc
Ambient
Thmperature
Range
Commercial
Militaryfl]
2.4
0.4
2.1
-3.0
GND5 Vr5 Vee
-10
Units
2.4
V
V
0.4
Vee
0.8
10
Note 3
2.1
-3.0
+10
-10
V
Vee
0.8
10
V
!lA-
Note 3
+10
!lA-
-70
-80
-70
rnA
- 80
rnA
90
60
rnA
90
rnA
Capacitance [5]
Parameters
Description
InputCapacitance
OutputCapacitance
erN
CoUT
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Max.
8
Units
pF
8
pF
Logic Table[6]
Inputs
OE
CSl
CSz
WE
Do-D3
X
H
X
X
X
HighZ
Not Selected
X
X
L
X
X
HighZ
Not Selected
L
L
H
H
X
00- 0 3
Read Stored Data
X
L
H
L
L
HighZ
Write "0"
X
L
H
L
H
HighZ
Write "1"
H
L
H
H
X
HighZ
OutputDisabled
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3. The CMOS process does not provide a clamp diode. However, the
CY7Cl22 is insensitive to - 3V DC input levels and - 5V undershoot
pulses ofless than 10 ns (measured at 50% point).
4.
5.
6.
2-52
Outputs
Mode
For test purposes, not more than 1 output at a time should be shorted.
Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
H = HIGH Voltage, L = LOW Voltage, X = Don't Care, and High Z
= High-Impedance
.~
.
CY7C122
i!!L....i, iE CYPRESS
SEMICONDUCfOR
AC Test Loads and Waveforms
R14701)
5V
OUTPUT
30pF
INCLUDING
JIG AND
SCOPE
•
R14701)
5V
ALL INPUT PULSES
OUTPUT
I
R2
5 pF
2241)
-=
3.0V - - - -__- - - - - " " -
INCLUDING
JIGAND
SCOPE
-=
(a)
I-=
(b)
R2
2241)
I II
:e
GND
CC
-=
a::
C122-6
C122·5
THEVENIN EQUIVALENT
Equivalent to:
1521)
OUTPUT 0.0.----'1....10---.00. 1.B2V
Switching Characteristics Over the Operating Rangel7, 8J
7C122-15
Parameters
Description
Min_
Max.
7C122-25
Min.
Max.
7C122-35
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
35
25
15
ns
tACS
Chip Select Time
8
15
25
ns
tZRCS
Chip Select to High Z[9J
12
20
30
ns
tAos
Output Enable Time
8
15
25
ns
tZROS
Output Enable to High Z[8J
12
20
30
ns
tAA
Address Access Time
15
25
35
ns
WRITE CYCLE
twc
Write Cycle Time
tzws
Write Disable to High zI8J
12
25
20
30
ns
tWR
Write Recovery Time
12
20
25
ns
tPWE
WE Pulse Width[6J
11
15
25
ns
tWSD
Data Set-Up Time Prior to Write
0
5
5
ns
tWHD
Data Hold Time After Write
2
5
5
ns
10
ns
15
35
ns
tWSA
Address Set-Up Timel6J
0
5
tWHA
Address Hold Time
4
5
5
ns
twscs
Chip Select Set-Up Time
0
5
5
ns
tWHCS
Chip Select Hold Time
2
5
5
ns
Notes:
7. tw measured at tWSA =min.; tWSA measured at tw =min.
8. Thst conditions assume signal transition times of 5 os or less for the
-15 product and 10 os or less for the - 25 and - 35 product. Timing
reference levels of 1.5Y.
9.
2-53
ltansitionismeasuredatsteadystateIDGHlevel-500mVorsteady
state LOW level +500 m Von the output from 1.5V level on the input
with load as shown in part (b) of AC Thst Loads.
(/)
CY7C122
Switching Waveforms
Read Cycle[lO]
....,*----
AD~E:$ _ _ _ _i,... . ------------------------------------iR-C----------------------------------------.
..
tM
~
'.!!"
~
..Ill'
-
DATA
OUTPUTS
00 - 03
-
tOAS
/./././
./
././
,,,'\.'\.'\.~'\.'\.~,,
./
l'\.
-
~
tZROS
NOTE9
~
DATA VALID
tACS
.r-
~
NOTE 9
toH - C122-7
Write Cycle[9, 11]
twe
Ao- A7
ADDRESS
'.!!t'
- -
-
tWSA
CS1 - CS2
CHIP SELECT
Do - 03
DATA IN
WE
WRITE ENABLE
~(
-
-
twscs
)(
-
+--
'.!!I(
twso
tWHA
)K
tWHCS
~
)K
tWHO
tPWE
~
..,Il'
I\..
I.
I
~
I--
~,.-------~-(
L
.r-
tzws
NOTE9
DATAOUTPUTS
.
0, - 0, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...;;;r
LOAD 1b
tWR
---
NOTE9
C122-l1
Note.:
10. Measurements are referenced to 1.5V unless otherwise stated.
11. The timing diagram represents one solution that results in an optimum cycle time. Timing may be changed in varous applications as long
as the worst-case limits are not violated.
2-54
~
= s. .
~PRESS
---:='.F
CY7C122
SEMICONDUCTOR
1Ypicai DC and AC Characteristics
NORMAl.JZEDIcc
vs. AMBIENT TEMPERATURE
NORMAl.JZEDIcc
vs. SUPPLY VOLTAGE
1.2
g 1.0
:::;;
a:
0
z
0.6
V
/
Cl
w
N
::J 0.8
«
V
0.4
4.0
/
I-
u
..9
Cl
W
N
~
:::;;
V
t....
1.2
~
i'--
-............
=5.0V
TA = 25°C
4.5
5.0
5.5
Vee = 5.0V
VIN =5.0V
0.6
-55
6.0
25
125
AMBIENT TEMPERATURE ("C)
M
J
Cl
Cl
~
---
Z
0.8
4.5
5.0
1.21----+------,;1
1.01------:1.-£-----1
6.0
_ _ _---L_ _ _ _ _...J
-55
25
125
Cl
o
vV
o
200
/
V
I-
,..-
/
JS
Cl
w
N
w
~ 100
o
75
1i5
5 50
o
25
o/
/
0.0
1.0
2.0
800
1000
CAPACITANCE (pF)
o
V
o
10
V
20
30
40
50
FREQUENCY (MHz)
2-55
.,
,
3.0
4.0
OUTPUT VOLTAGE M
1.2
~
-Vcc=5.0V
TA = 25°C
,/
/
4.0
J
/
./
1.0
'"
M
/
2
1.3
:::;; 1.1
a:
0
600
3.0
/
Z
1.4
Z
400
'"""~
2.0
NORMAl.JZED Icc vs. FREQUENCY
V~=4.5~
20
10
1.0
AMBIENT TEMPERATURE ("C)
TA = 25°C
!:jw
o
.s 125
1=
:::l
Vee = 5.0V
5.5
0
OUTPUT VOLTAGE
0.6~
ACCESS TIME CHANGE
vs. OUTPUT LOADING
Cii'
.s
10
:::l
SUPPLY VOLTAGE M
30
5
5o
"" '"
I
=5.0V
TA = 25°C
«150
oz
TA = 25°C
0.6
4.0
20
Vee
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.4
i'-.... .............
:::l
NORMAl.JZEDACCESSTrndE
vs. AMBIENT TEMPERATURE
J1.4
"-
~ 30
a:
g
•
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
o
z 0.8
VIN
50
a:
~ 40
0
1.6
a: 1.0
0
w
1.0
NORMAl.JZED ACCESS TIME
vs. SUPPLY VOLTAGE
«
:::;;
Z
a:
SUPPLY VOLTAGE
w
N 1.2
::J
~60
1.4
60 70
_
5.0
~
~~PRF.SS
~, SEMICONDUCTOR
CY7C122
Ordering Information
Speed
(ns)
15
25
35
Ordering Code
CY7C122-15PC
CY7C122-15DC
CY7C122-158C
CY7C122-25PC
CY7C122-25DC
CY7C122-258C
CY7C122-25LC
CY7C122-25DMB
CY7C122-35PC
CY7C122-358C
CY7C122-35DC
CY7C122-35LC
CY7C122-35DMB
CY7C122-35LMB
Package
'JYpe
P7
D8
813
P7
D8
813
L53
D8
P7
S13
D8
L53
D8
L53
Operating
Range
Commercial
Commercial
Military
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
VOH
VOL
Vm
VILMax.
Irx
Ioz
Icc
Parameters
Subgroups
Subgroups
READ CYCLE
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tRC
tACS
tocs
tAA
WRITE CYCLE
twc
tWR
tpWE
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9, 10, 11
Document #: 38-00025-B
2-56
CY7C123
CYPRESS
SEMICONDUCTOR
256 X 4 Static RIW RAM
Features
Functional Description
• 256 x 4 static RAM for control store in
high-speed computers
• CMOS for optimum speed/power
• Highspeed
-7ns (commercial)
-10 ns (military)
The CY7C123 is a high-performance
CMOS static RAM organized as256words
by 4 bits. Easy memory expansion is provided by an active LOW chip select one
(CSl) input, an active HIGH chip select
two (CS2) input, and three-state outputs.
Writingto the device is accomplished when
the chip select one (CSl) and write enable
(WE) inputs are both LOW and the chip
select two input is HIGH. Data on the four
data inputs (Do through D3) is written into
the memory location specified on the address pins (Ao through A7). The outputs
are preconditioned so that the write data is
present at the outputs when the write cycle
is complete. This precondition operation
ensures minimum write recovery times by
eliminatingthe "write recovery glitch."
• Lowpower
- 660 mW (commercial)
-825 mW (military)
• Separate inputs and outputs
• 5-volt power supply ±10% tolerance
both commercial and military
• TTL-compatible inputs and outputs
• 24pins
• 300-mil package
Readingthe device is acc~lished by taking the ~ select one (CSl) and output
enable ~ inputs LOW, while the write
enable (WE) and chip select two (CS2) inputs remain HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear
on the four output pins (00 through 03).
Theoutputpins remain in hi.8!!.-impedance
state when chip select one (CSl) or output
enable (OE) is HIGH,.2!. write enable
(WE) or chip select two (CS2) is LOW.
A die coat is used to insure alpha immunity.
Pin Configurations
Logic Block Diagram
SOJ
Top View
Ao
Ao
As
As
CS,
A,
A2
~
w
00
U
W
C
a
0,
~a:
02
CS,
D.
D,
00
C
Ao
As
As
oe
Vee
Do
D,
OE
a:
Ao
WE
CS,
A7
V••
WE
Ao
Vee
A,
""
cS2
0,
0.
V••
0,
C123-2
LCC
Top View
~~~g<
03
32 11 1 2423
22
21
6
20
7
'9
7C'23
8
18
9
17
10
16
1112131415
As 4
As 5
COLUMN
DECODER
A7
Vss
C123-1
Do
D,
A7
00
Ao
WE
~1
OE
Vee
CS,
D.
0;:'888
C123-3
Selection Guide
MaximumAccessTime(ns)
Commercial
Maximum Operating Current (mA)
Commercial
7C123-7
7CI23-9
7
9
120
120
Military
7CI23-10
12
15
120
150
2-57
7C123-15
12
10
Military
7CI23-12
150
150
•
~
~~PRFSS
~, SEMICONDUCI'OR
CY7C123
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested. )
Output Current into Outputs (Low) ................ 20 rnA
Latch-UpCurrent ............................ >200rnA
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pins 24 and 18 to Pins 7 and 12)[1) ........ - O.5V to +7.0V
Operating Range
Ambient
'lemperatunJ2)
Range
Commercial
g~~~g;t~~8¥~~.t~. ?~t~~t~ . . . . . . . . . . .
Military
_ O.5V to +7.0V
DC Input Voltagel1) .................... - O.5Vto + 7.0V
O°Cto + 70°C
Vee
5V± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel3)
Parameters
Description
'lest Conditions
Output HIGH Voltage
Output LOW Voltage
VOH
VOL
VIR
Vee = Min., IOH = - 5.2 rnA
Vee = Min.,IoL = 8.0 rnA
Input HIGH Voltage
Input LOW Voltagel1)
VIL
IJX
Ioz
Input Load Current
Output Current
(HighZ)
Vss < VI < Vee
Vss ~ VOUT ~ Vee,
Output Disabled
lee
Power Supply
Current
Vee = Max.,
IOUT=OmA,
f = fMAX = 1/tRC
7CI23-7
7C123-9
Min. Max.
2.4
0.4
7Cl23-10
7C123-15
Min. Max.
2.4
0.4
7Cl23-12
Min. Max.
2.4
0.4
2.2
-0.8
Vee
+0.8
2.2
-0.8
Vee
+0.8
2.2
-0.8
Vee
+0.8
V
V
-10
-10
+10
+10
-10
-10
+10
+10
-10
-10
+10
+10
!lA
!lA
120
rnA
150
rnA
ICommercial
IMilitary
120
150
Units
V
V
Capacitance [4)
Parameters
CIN
CoUT
Description
'lest Conditions
InputCapacitance
Output Capacitance
TA = 25°C,f= 1 MHz,
Vee=5.0V
Max.
Units
pF
pF
8
8
Logic Table[5)
Inputs
OE
CSI
CS2
WE
Do- D3
X
H
X
X
X
HighZ
Not Selected
X
X
L
X
X
HighZ
Not Selected
L
L
H
H
X
00- 0 3
Read Stored Data
X
L
H
L
L
HighZ
'Write "0"
X
L
H
L
H
HighZ
'Write "1"
H
L
H
H
X
HighZ
Output Disabled
Notes:
1. VIL(Min.) = -3.0V for pulse durations ofless than 20 us.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
information.
4.
5.
2-58
Outputs
Mode
Tested initially and after any desigo or process changes that may affect
these parameters.
H High Voltage, L Low Voltage, X Don't Care, and
High Z = High Impedance.
=
=
=
·
,~PRESS
-=E!!!f!iiffTF SEMICONDUCTOR
CY7C123
AC Test Loads and Waveforms
R1470U
R1470IJ
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
20 pF
INCLUDING
JIGAND
SCOPE
I=
R2
224IJ
3.0V - - - -__=----~
5 pF
INCLUDING
JIG AND
SCOPE
=
(a)
I=
R2
224IJ
GND
=
(b)
C123-4
C123-5
THEVENIN EQUIVALENT
Equivalent to:
152Q
OUTPUT OO----'\
..."'+.'Io---.()O 1.62V
Switching Characteristics
Over the Operating Rangd3]
7C123-7
Parameters
Description
Min.
7C123-9
Max.
Min.
Max.
7C123-10
Min.
Max.
7C123-12
Min.
Max.
7C123-15
Min.
Max.
Units
READ CYCLE
7
10
9
12
15
tRe
Read Cycle Time
tM
Address to Data Valid
7
9
10
12
15
ns
ns
tACS
Chip Select to Data Valid
7
8
8
8
10
ns
tDOE
OE LOW to Data Valid
7
8
8
8
10
ns
tHzes
Chip Select to High Z[6, 7]
5
6
6
6.5
8
ns
tHZOE
OE HIGH to High Z[6]
5
6
6
6.5
8
ns
tLZCS
Chip Select to Low Z[7]
2
2
2
2
2
ns
tLZOE
OE LOW to Low Z
2
2
2
2
2
ns
WRITE CYCLE
7
9
12
10
15
twe
Write Cycle Time
tHzWE
WE LOW to High Z[6]
tLZWE
WE HIGH to LowZ
2
2
2
2
2
ns
tpWE
WE Pulse Width
5
6.5
7
8
11
ns
tSD
Data Set-Up to Write End
5
6
7
8
11
ns
tHD
Data Hold from Write End
1
1
1
1
1
ns
tSA
Address Set-Up to Write Start
0.5
1
1
2
2
ns
tRA
Address Hold from Write End
1.5
1.5
2
2
2
ns
5
6.5
7
8
11
ns
5.5
7.5
8
10
13
ns
tses
CS LOW to Write End
tAW
Address Set-Up to Write End
5.5
6
Notes:
6. 'fransition is measured at steady state mGH level - 500 mV or steady
state LOW level + 500 mVon the output from 1.5V level on the input
with load shown in part (h) of AC Thst Loads.
7.
2-59
6
ns
8
7
ns
At any given temperature and voltage condition, tHZCS is less than
trzes for any given device.
CY7C123
Switching Waveforms
Read Cycle [8, 9]
ADDRESS
_~I--_-_-_-_-_-_-_t_RC===~~~~*
•
tAA
(
__
(
tACS
-
..... tHZCS -
tLZCS-
'!!
tlZOE -
DATA OUT
-
:;'f
~ tHZOE
I- 100E - -
i-
1//
/
/
"'
DATA VALID
'\.""""",
/
Cl 23-6
Write Cycle [7, 8]
twe
ADDRESS
)(
)E
lAw
CS1- CS2
t
tHA-
tscs
)l'
tSA
tPWE
l'
'311\,.
L
DATA IN
:*
tSD
I--
DATA OUT
tHZWE
tHD
~1I--------IC1,,---.. tlZWE
Cl23-7
Notes:
8. Measurements are referenced to l.5V unless otherwise stated.
9.
2-60
Timing diagram represents one solution that results in an optimum
cycle time. Timing may be changed in varous applications as long as
the worst case limits are not violated.
.
~
_ ' j g CYPRESS
-.r
CY7C123
SEMICONDUCTOR
1)rpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
----....
VS. AMBIENT TEMPERATURE
VS.
1.4
gJ 1.2
Icc
jll.0
V
o
~ 0.8
:J
~
a:
/"
0.6
/"
/'
1.2
'"
~
0
()
a:
z
0
w
0.0
5.0
5.5
ISB
25
NORMALIZED ACCESS TIME
NORMALIZED ACCESS TIME
VS. AMBIENT TEMPERATURE
j
1.3
r-.............
0.9
0.8
4.0
4.5
TA = 25°C
---
5.0
r--
5.5
~
a:
0
z
,/
1.0
,.....
0.8
/
.20
w
N
2.0
g:
«
::;:
1.5
~
.,/
~
3.0
4.0
SUPPLY VOLTAGE (V)
1.0
5.0
'-..
"-
2.0
3.0
"
4.0
~
240
180
I-
::::>
::::>
125
25
20
II
o
/
120
60
o/
0.0
200
/
/
1.0
2.0
Vcc=5.0V _
TA = 25°C
I
I
5.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED Icc vs. CYCLE TIME
1.1
V~=4.5~
o
/'
::::>
~
/
--
:f
()
~
z
Vcc= 5.0V
TA = 25°C
2.0
./'
TOTAL ACCESS TIME CHANGE
vs.OUTPUTWADING
30
1.0
o
en
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (OC)
2 .5
0.0
0.0
0
0.4
0.2 -
ISB
75
~ 60
1i?
I
90
a:
w
«
::;:
4.5
!zw
::::; 0.6
N
0.2
j
1
~
.2 0.8
0
~ 0.4
4.0
1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
V
~
Vcc= 5.0V
TA = 25°C
VIN= 0.5V
o
~
a:
oz
400
600
800
CAPACITANCE (pF)
2-61
1000
0.81·'-:0---2!c:0,.------:!3""0--.......J40
CYCLE FREQUENCY (MHz)
~
.iL~UCfOR
CY7C123
Ordering Information
Speed
Package
'JYpe
Operating
Range
CY7CI23-7PC
P13A
Commercial
CY7CI23-7VC
V13
CY7C123-7DC
D14
Ordering Code
(ns)
7
9
10
12
15
CY7CI23-7LC
1.53
CY7CI23-9PC
P13A
CY7C123-9VC
V13
CY7C123-9DC
D14
CY7CI23-9LC
L53
CY7CI23-1ODMB
D14
CY7C123-1OLMB
L53
CY7C123-1OKMB
K73
CY7C123-12PC
P13A
CY7C123-12VC
V13
CY7C123-12DC
D14
CY7C123-12LC
L53
CY7C123-12DMB
D14
CY7C123-12LMB
L53
CY7C123-12KMB
K73
CY7C123-15DMB
D14
CY7C12~-15LMB
L53
CY7C123-15KMB
K73
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VILMax.
IJX
Ioz
Icc
Commercial
Military
Commercial
Military
Military
Switching Characteristics
Subgroups
Parameters
1,2,3
1,2,3
1,2,3
1,2,3·
1,2,3
1,2,3
1,2,3
Subgroups
READ CYCLE
tRC
tAA
tACS
tDOE
WRITE CYCLE
twc
tpWE
tsD
tHD
tSA
tHA
tscs
tAW
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10, 11
Document #: 38-00060-E
2-62
CY7C128
CYPRESS
SEMICONDUCTOR
2048 X 8 Static R/W RAM
Features
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• Highspeed
-35ns
• Low active power
- 660 mW (commercial)
-825 mW (military)
• Low standby power
-llOmW
• TIL-compatible inputs and outputs
• Capable of withstanding greater
than 2001V electrostatic discharge
The CY7C128 is a high-performance
CMOS static RAM organized as 2048
words by 8 bits. Easy memory expansion is
Jlrovided by an active LOW chip enable
(CE), and active LOW output enable (DE)
and three-state drivers. The CY7Cl28 has
an automatic power-down feature, reducing the power consumption by 83% when
deselected.
\\Titing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the
eight 110 pins (1100 through 1/07) iswritten
into the memory location specified on the
address pins (Ao through AlO).
Logic Block Diagram
Readingthe device is accomplished byta~
chip enable (CE) and output enable (DE)
LOW while write enable (WE) remains
HIGH. Under these conditions, the contents
of the memory location specified on the address pins will appear on the eight 110 pins.
The 110 pins remain in high-impedance state
when chip enable (CE) or oU.!E!:!.t enable
(DE) is HIGH or write enable (WE) is low.
The 7C128 utilizes a die coat to ensure alpha
immunity.
Pin Configurations
DIP/SOJ
Top View
Vee
As
As
WE
DE
A2
A,
A10
CE
Vo.,
VOs
As
VCla
1/0.
1/0 ,
1/02
VO,
V0 5
VO.
110a
GND
uo,
C128-2
uOa
LCC
Top View
VO.
J?:n!;:Jf
V0 5
3 2,1,2423
22
0
uOs
A4
As
As
Uo.,
VO,
A,
I/~
~
21
20 DE
19 A10
18 CE
17 vo.,
10
16 VOs
1112131415
7C128
NO (0)'111' LO
g~ggg
C128-1
C128-3
Selection Guide
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
Commercial
Maximum Standby
Current(mA)
Commercial
7C128-35
7C128-45
7C128-55
35
45
55
120
120
90
130
100
Military
20
Military
2-63
20
20
20
20
•
:~PRESS
EJi
~,
CY7C128
SEMICOIDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0Vto + 7.0V
Output Current into Outputs (WW) ............... 20 rnA
Static Discharge Voltage. .. .. .. . .. . . . .. . . . . . . . . . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Commercial
Militaryll]
Ambient
Thmperature
Vee
O°Cto + 70°C
5V± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Range!2]
7C128
Parameters
Thst Conditions
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input WW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[3]
Vee Operating Supply
Current
VOH
VOL
Vrn
VIL
IJX
loz
los
Icc
2.0
-3.0
-10
-40
Com'l
AutomaticCE
Power-Down Current
CE~Vrn
V
V
V
V
Vcc
0.8
+10
+40
ItA
ItA
-300
rnA
120
90
130
100
20
20
rnA
35,45
55
45
55
Com'l
Mil
Max. Vee,
Units
0.4
GND.5. VI.5. Vee
GND .5. VI.5. Vcc,
Output Disabled
Vee = Max., VOUT = GND
Vcc=Max.
lOUT = ornA
Max.
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Mil
ISB
Min.
rnA
Capacitance [4]
Parameters
Description
CIN
InputCapacitance
CoUT
OutputCapacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
Max.
Units
10
pF
10
pF
3. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R14810
R148Hl
5V 00-_ _---'
__,
OUTPUTOo---P---.
OUTPUTOo---P---.
5V 0 0 - - - - - - '__,
FI
30 P
ALL INPUT PULSES
R2
2559
5PFI
INCLUDING
JIGAND _
INCLUDING
JIG AND _
SCOPE -
SCOPE -
(a)
Equivalent to:
THEVENIN EQUIVALENT
1am
OUTPUT oo--_
..·",
.._-~o 1.73V
3.0V - - - - . . , \__=----~
R2
2559
GND
(b)
C128-4
2-64
C128-5
-==------=-
=====CYPRESS
~:..«b
~.F
CY7C128
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel2, 5]
7C128-35
Description
Parameters
Min.
Max.
7C128-4S
Min.
Max.
7C128-55
Min.
Max.
Units
READ CYCLE
45
35
55
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
35
45
55
ns
tDOE
OE LOW to Data Valid
15
20
25
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6]
tizCE
CE LOW to Low Z[7]
tHZCE
CEHIGHtoHighZ[6,7]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
45
35
5
5
0
5
0
15
5
5
0
5
0
20
ns
20
20
ns
ns
20
0
ns
ns
25
25
ns
ns
0
15
15
ns
55
ns
WRlTECYCI EJ8J
Write Cycle Time
35
45
55
ns
tSCE
CE LOW to Write End
30
40
50
ns
tAW
Address Set-Up to Write End
30
40
50
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
20
25
ns
tSD
Data Set-Up to Write End
15
20
25
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[6]
tLZWE
WE HIGH to LowZ
twc
0
15
0
Notes:
5. Thst conditions assume signal transition time of 5 ns or less, timing ref·
erence levels of L5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOrflOH and 30-pF load capacitance.
6. tHzOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. 1tansition is measured ±500 m V from steady state
voltage.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminateawrite bygoingHIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
0
15
0
ns
20
0
ns
ns
WE is HIGH forread cycle.
Device is continuously selected. DE, CE = VIL.
Address valid prior to or coincident with CE transition LOW.
Data I/O pins enter high-impedance state, as shown, when DE is held
LOW during write.
13. IfCEgoesHlGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
9.
10.
1L
12.
2-65
~PRFSS
~nEMICONDucroR
CY7C128
Switching Waveforms
Read Cycle No. 119, 10]
*-
~
1
V::~~ JXX *=============D=A=TA==VA=L=ID==========
tRC
ADDRESS
-----
DATA OUT
~
tAA
PREVIOUS DATA
C128-6
Read Cycle No. 2[9, 11]
tRC
~
~£
~
tACE
£
~~
-~,
tDOE
I---
HIGH IMPEDANCE
DATA OUT
"~'"
I---
tpu
jt
SUPPLY _ _ _ _ _ _
CURRENT
-
tHzCE
DATAVAUD
/
tLZCE
V~
-
tLZOE - - - -
_tpD
HIGH
'-.: IMPEDANCE
~ CC
I
50%
50%
ISB
C128-7
Write Cycle No.1 (WE Controlled) [9, 12]
twc
ADDRESS
~L'
)(
---/
tsCE
/ ~ W////0
~~ ~ ~
tAW
tHA-
tSA
tPWE
~~
i~
tHD . .
IsD
~L'
DATA IN
I-DATAI/O
~(
DATA-IN VAUD
IHZWE
I--
tlZWE
HIGH IMPEDANCE
DATA UNDEFINED
C128-8
2-66
~
..s--~
=z
Ii;; CYPRESS
~.' SEMICONDUCTOR
CY7C128
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[9, 12, 13J
ADDRESS
----------~------- ~eE ------~
CE
----4---------------------,
ISD
DATA IN
,--------~--------
-------"0-
DATA-IN VALID
IHZWE
DATA 1/0
=j
HIGH IMPEDANCE
~----------------------
DATA UNDEFINED
C128-9
lYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
lJl1.2
Icc
31.0
c
I!:I 0.8
~
0.6
V
V
1/
V
..
~ 1.0
8
C
~
..J
~
a:
~ 0.4
gj
z
0.2
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
0.8
100
~
60
W
60
g
40
':i
20
a:
u
IS6
25
125
o~
'" '"
0
0.0
1.6
1.0
Vee = 5.0V
TA = 25°C)
"-
2.0
3.0
OUTPUT VOLTAGE
NO~ZEDACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
"
<,140
1.41--------+---------1
1.3
:::;
« 1.1
::;:
a:
1.0
.............
r--...
0.9
0.8
4.0
tl!
l~ 1.2
c 1.2
N
~
irl
TA = 25°C
............
t---
f-
z
aa:
-
~
Z
1.0
Ci5
c
':i
f!:
:J
o
4.5
5.0
5.5
SUPPLY VOLTAGE M
6.0
0~~-~------~2~5--------~125
AMBIENT TEMPERATURE (0C)
2-67
."V
100
80
60
40
/
oII
/
4.0
M
.§.. 120
w
z
!z
w
AMBIENT TEMPERATURE rC)
M
NO~EDACCESSTDdE
0
~
vcc- 5.OV
VIN= 5.0V
0.0
-55
6.0
1
1£
:J
0.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
0.6
vs. SUPPLY VOLTAGE
J
------
0.2
I---
IS6
1.2
Vcc= 5.0V
TA = 25°C
V
J
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE M
4.0
•
...::-....
·~PRFSS
.
~F
CY7C128
SEMICONDUCTOR
1YPical DC and AC Characteristics (continued)
TYPICALPOWER·ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
~
25.0
c 2.0
w
c
20.0
::J
~
15.0
z
10.0
2.5
~
~
N
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .. . . . . . . . . . . . . . . . . . .. . . . . . . . >200 rnA
Operating Range
Range
Commercial
Military!l]
Ambient
Thmperature
Vee
O°Cto + 70°C
5V± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
7C128A-15
Parameters
Description
Thst Conditions
7C128A-20
7C128A-25,
35,45
VOH
Output HIGH
Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW
Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH
Voltage
2.2
Vee
2.2
Vee
2.2
Vee
VIL
Input LOW
Voltagel3]
-0.5
0.8
-0.5
0.8
-0.5
IJX
Input Load
Current
GNDsVISVee
-10
+10
-10
+10
loz
Output Leakage
Current
GNDsVISVee
OutputDisabled
-10
+10
-10
+10
los
Output Short
Circuit Curren1l4]
Vee = Max., VOUT
= GND
Icc
Vee Operating
Supply Current
Vee = Max.
lOUT = ornA
Com'l
2.4
2.4
0.4
-300
120
MiI~
35,45
ISBl
ISB2
7C128A-55
Min. Max. Min. Max. Min. Max. Min. Max. Units
AutomaticCE
Power-Down
Current
Max. Vee,
CE~ VIH,
Min. Duty Cycle
=100%
Com'l
Automatic CE
Power-Down
Current
Max. Vee.
Com'l
40
MiI~
35,45
40
2.4
0.4
2.4
0.4
V
0.4
V
2.2
Vee
V
0.8
-0.5
0.8
V
-10
+10
-10
+10
J.tA.
-10
+10
-10
+10
J.tA.
-300
rnA
rnA
-300
-300
100
100
80
125
125
125
125
rwo
40
20
20
40
40
20
100
--:iO
r-zo
---w
20
20
20
20
20
20
rnA
rnA
CEl~Vee - 0.3v,
VIN ~ Vee -O.3V
orVINSO.3V
Mil
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3.
4.
2-71
VlLmin. = -3.0V for pulse durations less than 30 ns.
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
•
~
~~
CY7C128A
~.CYPRESS
~.iF' SEMICamuCTOR
Capacitance [5]
Description
Parameters
5.
CIN
InputCapacitance
COUT
Output Capacitance
'Thst Conditions
Max.
Units
10
pF
10
pF
TA = 25°C, f = 1 MHz,
Vcc=5.0V
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl481!l
5VD----""""...,
Rl481!l
__'
5VD---~
30PFI
ALL INPUT PULSES
OUTPUTD---f__--+
OUTPUTo-----1P----+
5PFI
R2
255!l
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
R2
~
10%
GND
255!l
~
,5.5ns ....
~5ns
(b)
(a)
THEvENIN EQUIVALENT
Equivalent to:
30V~00%
10%
C128A-5
C128A-4
167!l
OUTPUT O().---"I
......
t"_--oO 1.73V
Switching Characteristics Over the Operating Range!2,6]
7C128A-15
Parameters
Description
Min.
Max.
7C128A-20
Min.
Max.
7C128A-25
Min.
Max.
Units
25
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
15
20
15
5
25
20
5
ns
5
ns
tACE
CE LOW to Data Valid
15
20
25
ns
tDOE
OE LOW to Data Valid
10
10
12
ns
tUOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7]
10
ns
tUCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
3
3
8
5
3
8
5
8
0
5
8
0
15
ns
ns
10
0
ns
20
20
ns
ns
WRITECYCLEl'
twc
Write Cycle Time
15
20
20
ns
tsCE
CE LOW to Write End
12
15
20
ns
tAW
Address Set-Up to Write End
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
ns
tso
Data Set-Up to Write End
10
10
10
ns
tHO
Data Hold from Write End
0
0
0
tHZWE
WE LOW to High Z[1]
tuWE
WE HIGH to Low Z
7
7
5
2-72
5
ns
7
5
ns
ns
~
·~PRESS
CY7C128A
_.iF SEMICONDUCTOR
Switching Characteristics
Over the Operating Range (continued)
7C128A-3S
Parameters
Description
Min.
Max.
7C128A-4S
Min.
Max.
7C128A-SS
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
35
45
35
55
45
ns
55
ns
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
35
45
55
ns
tOOE
OE LOW to Data Valid
15
20
25
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7]
tLZCE
CE LOW to Low Z[B]
tHZCE
CE HIGH to High Z[7,B]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
5
5
3
5
3
12
5
3
15
5
15
0
ns
20
0
20
ns
ns
0
25
ns
ns
5
15
20
ns
25
ns
WRITECYCLEl!
Write Cycle Time
25
40
50
ns
tsCE
CE LOW to Write End
25
30
40
ns
tAW
Address Set-Up to Write End
25
30
40
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
20
20
25
ns
tso
Data Set-Up to Write End
15
15
25
ns
tHO
Data Hold from Write End
0
tHzwE
WE LOW to High Z[7]
tLZWE
WE HIGH to Low Z
twc
0
5
Notes:
6. Test conditions assume signal transition time of S ns or less, timing reference levels of LSV; input pulse levels of 0 to 3.0V; and output loading of the specified IOlJ10H and 30-pF load capacitance.
7. tHzOE, tHzCE, and tHZWE are specified with CL = S pF as in part (b)
of AC Thst Loads. nansition is measured ±SOO mV from steady state
voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
9. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate a write by goinglllGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
10.
11.
12.
13.
0
15
10
5
ns
20
5
ns
ns
WE is lllGH for read cycle.
Device is continuously selected. OE, CE = VIL.
Address valid prior to or coincident with CE transition LOW.
Data I/O pins enter higb-impedance state, as shown, when OE is held
LOW during write.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-73
•
.~cgp~UCfOR
CY7C128A
Switching Waveforms
Read Cycle No.lllO,H]
~
1
V~~; ~XX *=============D=A=TA=V=AL==ID==========
tRC
ADDRESS
----- ~
DATA OUT
tM
PREVIOUS DATA
C128A-6
Read Cycle No. 2[10, 12]
tRC
Ii"
"""'"
tACE
~~
~".
IHZOE ~ tHZCE-
lODE
I---
I[zOE - HIGH IMPEDANCE
DATA OUT
=1
1"Io.'\.
.'\.
I[zCE
V~
-tpu
SUPPLY _ _ _ _ _ _
CURRENT
-
HIGH
IMPEDANCE
DATAVAUD
I---
Ipo
~ CC
I
50%
50%
IS8
C128A-7
Write Cycle No.1 (WE Controlled) [9, 13]
IWC
ADDRESS ~£
--./
j(
'sCE
~~ ~ i'i-..
./Wffff.£ W///////
lAW
IHA-
!sA
tPWE
*
~~
DATA IN
~".
Iso
tHO -
DATA·IN VALID
)(
::j
I-1
D_A_TA_UN_D_E_FI_N_ED_______»--------« ...____
-
IHZWE
tlZWE
HIGH IMPEDANCE
DATAI/O _ _ _ _ _ _ _
C128A-8
2-74
~
.
~=CYPRESS
~_.F
CY7C128A
SEMICONDUClDR
Switching Waveforms (continued)
•
Write Cycle No.2 (CE Controlled)[9, 12, 14]
ADDRESS
en
------+0>----- tseE - - . - . I
:::E
-I-H-IG-H-IM-P-E-DA-N-C-E---_ _ __
__
_ _ _ _ _ _ _ _ _ _..../
DAIAI/O __ _ _ _ _ _ _DATA
UNDEFINED
C126A-9
typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMUUJZED SUPPLY CURRENT
SUPPLY VOLTAGE
VS.
1.4
3l1.2
lee
13 1.0
c
II;!
::J
~
V
0.8
V
0.6
1.2
V
~
8
II:
~ 0.4
o
0.8
~
0.6
gs
0.4
z
0.2
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
1.6
1- 1.3
.J.1.4
c 1.2
C
1.0
w
...........
r---....
0.9
0.8
4.0
VIN
~ 40
~
=5.0V
=5.0V
~
IS8
25
125
AMBIENT TEMPERATURE (0C)
5
'"
Vee = 5.0V
...........
0
0.0
4.5
--
5.0
~
TA = 25°C
t--
5.5
SUPPLY VOLTAGE M
«
:;
II:
az
1.0
0.8
0.6
6.0
/
/
......
-~
!z
/
1.0
2.0
~
80
Z
60
~
~ 40
~
::::l
a
~
2-75
/
100
a
Ci5
1~
AMBIENT TEMPERATURE (0C)
""
3.0
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
/
II:
Vee = 5.0V
'"
"
4.0
OUTPUT VOLTAGE M
. .....,b
~=CYPRESS
_ , SEMICONDUCIDR
CY7C128A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9, 10, 11
tOHA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
tOOE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9,10,11
tSA
7,8,9,10,11
tpWE
7,8,9, 10, 11
tso
7,8,9, 10, 11
tHO
7,8,9, 10, 11
Document#: 38-00094-B
2-77
CY7C130/CY7C131
CY7C140/CY7C141
CYPRESS
SEMICONDUCTOR
1024 X 8 Dual-Port
Static RAM
Features
Functional Description
• O.8-micron CMOS for optimum
speed/power
• Automatic power-down
• TTL compatible
• Capable oCwithstanding greater than
2001V electrostatic discharge
• Fully asynchronous operation
• Master CY7CI30/CY7C131 easily expands data bus width to 16 or more
bits using SlAVE CY7CI40/
CY7C141
• BUSY output ~ag on CY7C130/
CY7CI31; BU Y input on
CY7CI40/CY7CI41
• INT flag Cor port-to-port
communication
The
CY7C130/CY7C131/CY7C140/
CY7C141 are high-speed CMOS lK by 8
dual-port static RAMs. 1\vo ports are provided permitting independent access to any
location in memory. The CY7Cl30/
CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as
a master dual-port RAM in conjunction
with the CY7Cl40/CY7C141 slave dualport device in systems requiring 16-bit or
greater word widths. It is the solution to
applications requiring shared or buffered
data, such as cache memory for DSP, bitslice, or multiprocessor designs.
Each port has independent control pins; chip
enabl~' write enable (R,iW), and output
enable E . 1\v~sprovided on each
port, B Yand
U Y signals !hat the
port is trying to access the same location currently being accessed by the other port. INT
is an interrupt flag indicating that data has
been placed in a unique location (3FF for the
left port and 3FE for the right port). An automaticpower-downfeatureiscontrolledindeIJIlndently on each port by the chip enable
{CE)pins.
The CY7C130and CY7C140 are available in
both 48-pin DIP and 48-pin LCC. The
CY7C131 and CY7C141 are available in
both 52-pin LeC and PLCC.
Logic Block Diagram
Pin Configurations
AfRL
l:£t.
RiWR
t:E.,
llE'L
!lEA
AoL
AeR
A7\.
A7\.
110...
VOoR
1I07\.
110m
I!llSYR~1
I!llSYL'"
DIP
Top View
l:£t.
Voo
loa.
A'R
RiWL
BllSVL
IATL
llE',.,
AoL
A'L
t:E.,
RiWR
BllSV.
IATR
!lEA
AoR
AoL
AeR
As.
As.
"oR
A.m
AoL
AoR
As.
AeL
A7\.
A.,.
AeL
AoL
Am
IiOCL
IIO'L
IJOa
va...
110...
lIOn
va...
1I07L
GND
lRT,,121
C13D-1
Notes:
1. CY7C130/CY7C131 (Master~gW~Y is open drain output and requires pull-up resistor.
is input.
CY7Cl40/CY7C141 (Slave):
2. Open drain outputs: pull-up resistor required.
2-78
A.,.
AoR
AeR
Aen
110m
110..
IIOOR
110..
1I03R
110.,.
IIO'R
110..
C130-2
=.'.~PRFSS
CY7C130/CY7C131
CY7C140/CY7C141
~, SEMICaIDUCTOR
Pin Configurations (continued)
~I~I~I~"~~,? '1f~1~a:linlf
~1~~I~I~..~~,!3nf~ lia:li~
765432111525150494847
A'L
AoL
AoL
AoL
Aot.
Aot.
A'L
Aot.
Aot.
IJOaL
IIO'L
IlOa
11031.
•
46
4S
44
9
10
11
12
43
42
13
14
15
16
17
18
19
20
70131
70141
41
40
39
38
37
38
35
34
2122 23 24 25 26 27 28 29 30 3132 33
-'....1....1...100
g-g"'g"'gZ ~
•
48·Pin LCC/QFP
Top View
52·Pin LCCIPLCC
Top""....
rn;,.
A'L
)Ao.
41
40
39
38
37
36
35
34
A,.
A.,.
A3R
Aa.
A3I. 9
Aa. 10
AoL 11
AoR
A,.
A.,.
A..,
70130
12
70140
13
Aa. 14
Aa. 15
I/O... 16
33
32
IIO'L 17
110... 18
31
' - 1920 21 22 ~ 24 25 26 27 28 29 30
Aa.
"'"
A..,
A7L
AeR
Am
AeR
A..,
NO
Vo,.
t I)
6 5 4 3 211,484746 45 44 43
•
42
:e
2001 V
(per MIL·STD·883, Method 3015)
Latch·Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O·Cto +70·C
5V± 10%
Industrial
- 40·C to +85·C
5V ± 10%
Military[4j
- 55·Cto +125·C
5V± 10%
Range
Commercial
Notes:
3. 25·n. version available only in PLCC/LCC packages.
4.
2-79
TA is the t1instant on" case temperature.
CY7C130/CY7C131
CY7C 140/CY7C141
Electrical Characteristics Over the Operating RangelSI
7C130-25,30[3]
7C131-2S,30
7Cl40-2S,30
7C141-2S,30
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage Vex; = Min., IoH = - 4.0 mA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Max.
2.4
7C130-3S
7C131-35
7Cl40-3S
7C141-3S
Min.
IOL = 16.0 mA[61
Max.
Min.
0.4
0.5
2.2
0.5
Units
0.4
V
V
0.5
2.2
2.2
V
VIL
Input LOW Voltage
IIX
InputLeakageCurrent
GND~ VI~ Vex;
-5
+5
-5
+5
-5
+5
Ioz
Output Leakage
Current
GND ~ Vo~ Vee.
Output Disabled
-5
+5
-5
+5
-5
+5
J.IA
J.IA
los
Output Short
Circuit Current[? 81
Vex; = Max.,
Vour= GND
- 350
mA
Iec
Vee Operating
Supply Current
CE = VIlA
Outputs 0gfen,
f= fMAX[
mA
ISBl
ISB2
ISB3
ISB4
0.8
Max.
2.4
2.4
0.4
IOL= 4.0mA
7C130-4S,5S
7C131-45,55
7Cl40-4S,5S
7C141-4S,5S
-350
Com'l
170
Mil
Standby Current
Both Ports,
TTL Inputs
CfiLandCfiR~ VlH,
Standby Current
One Port,
TTL Inputs
Com'l
CELorCfiR~ VlH,
Active Port Outputs Open,
f= fMAX[9]
Mil
115
Standby Current
Both Ports,
CMOS Inputs
rnR ~ Vex; -
Both Ports eEL and
0.2Y,
VIN ~ Vee - 0.2Vor
VIN~0.2V, f = 0
15
Standby Current
One Port,
CMOS Inputs
rnR ~ Vex; -
Com'l
f= fMAX[9J
65
Mil
Com'l
Mil
One Port eEL or
0.2Y,
VIN ~ Vee - 0.2Vor
Com'l
VIN~0.2V,
Active Port Outputs Open,
f = fMAX[91
105
Mil
0.8
- 350
0.8
V
120
90
170
120
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
mA
mA
mA
mA
Capacitance[81
Parameters
Description
Thst Conditions
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
Cour
Output Capacitance
Vee =5.0V
Max.
Units
15
pF
10
pF
Notes:
5. See the last page of this specification for Oroup A subgroup testing
infonnation.
6. 'iTIJ'SY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. Thsted initially and after any design or process changes that may affect
these parameters.
9. At f=fMAJ(, address and data inputs are cycling at the maximum frequencyofread cycle oflltrc andusingACThst Waveforms input levels
ofONDt03Y.
10. AC Thst conditions use VOH = 1.6V and VOL = 1.4Y.
11. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0V and output
loading of the specified IOlJlOH, and 30·pF load capacitance.
12. AC Thst Conditions use VOH = 1.6V and VOL = 1.4Y.
13. tLZCEo tUWEo tHZOEo tLZOEo tHZCE and tHZwE are tested with CL =
5pFasin part (b) of AC Thst Loads. Thlnsitionis measured ±500mV
from steady state voltage.
14. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
15. The internal write time of the memory is defined by the overlap ofCS"
LOW and R/W LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going mOH. The data input
set-up and hold timing should be referened to the rising edge of the
signal that terminates the write.
2-80
CY7C130/CY7C131
CY7C 140/CY7C 141
~;r,~
AC Test Loads and Waveforms
5V
RI893n
5V :J1RI893.0.
0 -_ _- - ' _ ,
OUTPUTo---_--+
30PFI
1!IJSY-J5V 281n
OUTPUT
R2
347n
5pF
INCLUDING
JIGAND _
SCOPE -
OR
I
(a)
1RT
:7n
INCLUDING
JIGAND _
SCOPE -
~30pF
_
C13O-5
(b)
JiUSY Output Load
(CY7C130/CY7C131 ONLy)
C130-6
ALL INPUT PULSES
Equivalent to:
~
THEVENIN EQUIVALENT
2SDn
OUTPUT 0.0- -.....\1\0._ _-00 1.4OV
10%
.s.5ns
Switching Characteristics Over the Operating Range[S.H]
7CI30-2SLjJ
7C131-2S
7CI40-2S
7C141-2S
Parameters
Description
Min.
Max.
7C130-30
7C131-30
7CI40-30
7C141-30
Min.
Max.
7C130-3S
7C131-3S
7C140-3S
7C141-3S
Min.
Max.
7C130-4S
7C131-4S
7C140-4S
7C141-4S
Min.
Max.
7C130-SS
7C131-SS
7C140-SS
7C141-SS
Min.
Max. Units
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid[12]
tOHA
Data Hold from
Address Change
30
25
25
0
45
35
30
0
35
0
ns
55
45
0
55
ns
0
tACE
CE LOW to Data Valid[12]
25
30
35
45
55
tDOE
15
20
20
25
25
3
tHZOE
OE LOW to Data Valid[12]
OE LOW to Low Z
OE HIGH to High Z[13]
tLZCE
CE LOW to Low Z[13.14]
5
tHZCE
CE HIGH to High z[13.14]
tpu
CE LOW to Power·Up
tLZOE
3
15
15
5
0
0
25
3
5
20
0
25
0
35
ns
25
ns
ns
ns
0
35
ns
25
5
20
ns
ns
3
20
20
5
15
15
CE HIGH to Power·Down
tpD
WRITE CYCLE[lS]
3
ns
35
ns
twe
Write Cycle Time
25
30
35
45
55
ns
tSCE
CE LOW to Write End
20
25
30
35
40
ns
tAW
Address Set·Up to Write End
20
25
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R/W Pulse Width
15
25
25
30
30
ns
tSD
Data Set-Up to Write End
15
15
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
R/W LOW to High Z
R/W HIGH to Low Z
tLZWE
15
15
0
0
2-81
20
20
0
0
ns
25
0
ns
ns
CY7C130/CY7C131
CY7C140/CY7C141
'I;n~
~
SEMlCOlD\.JCTOR
Switching Characteristics Over the Operating Range[S,111(continued)
Parameters
Description
7Cl3O-Z5lJ j 7C130-30
7C131-30
7C131-Z5
7CI40-30
7C140-ZS
7C141-30
7C141-Z5
Min. Max. Min. Max.
7C130-35
7C131-35
7C140-35
7C141-35
Min·1Max.
7C130-45
7C131-45
7CI40-45
7C141-45
Min.
7C130-55
7C131-55
7CI40-55
7C141-55
Max.
Min.
I Max.
Units
BUSY/INTERRUPT TIMING
tElA
tBHA
tBLC
tBHe
tps
tWBlllj
tWH
tBDD
tDDD
tWDD
BUSY LOW fromAddress Match
BUSY mGH from
Address Mismatch[161
BUSY LOW from en LOW
BUSY HIGH from CE HIGHl16j
Port Set Up for Priority
IR/W LOW after BU-S-Y LOW
R/W HIGH after BUSY HIGH
BUSY mGH to Valid Data
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
20
20
20
20
20
25
20
25
30
30
ns
ns
20
20
20
20
20
20
25
25
30
30
25
Note
30
35
45
45
Note
Note
Note
Note
ns
ns
ns
ns
ns
ns
ns
Note
Note
Note
Note
Note
ns
25
25
25
25
25
25
25
25
25
35
35
35
45
45
45
ns
ns
ns
25
25
25
35
45
ns
25
25
25
35
45
ns
25
25
25
35
45
iIs
5
0
20
5
0
30
18
18
18
5
0
35
5
0
30
18
5
0
35
18
18
18
18
18
18
INTERRUPT TIMING
twiNS
tEINS
tINS
tolNR
tEINR
tINR
R/W to INTERRUPT Set Time
ICE to INTERRUPT Set Time
Address to INTbKKUY I'
Set Time
1m to INTERRUPT
Reset Timell6]
rn to INTERRUPT
Reset Timel l6]
Address to INTERRUPT
Reset Timel161
Notes:
16. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
17. CY7C140/CY7C1410nly.
18. A write operation on Port A, where PortA has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
fOlloBlJlY
A.
on Port B goes HIGH.
B. Port B's address is toggled.
C. auor Port B is toggled.
D. R/W for Port B is toggled during valid read.
19. R/W is HIGH for read cycle.
20. Device is continuously selected,
= VIL and OE = VIL.
21. Address valid prior to or coincident with
transition LOW
22. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tPWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD'
23. If the
LOW transition occurs simultaneously with or after the RI
W LOW transition, the outputs remain in the high-impedance state.
rn
rn
rn
Switching Waveforms
Read Cycle No. 1[19, 201
ADDRESS
DATA OUT
Either Port Address Access
~.DATAV:;txXX~
. -1AA-~-=-,-=--=-*_-_PREVIOUS
_ _ _ _ _ _D_I\_:rA_V_A_Ll_D_ _ _ _ __
0130-7
2-82
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Read Cycle No. 2[19.21]
Either Port CE/OE Access
cr
OE __-4~==~~====~tAC~E~========~------------~:::::~~~~~-+
DATA OUT
---1~------------~~~SS~~~
______D~A~~~A~V~A~LI~D
_____
l-______~~---
______
~O~
ICC
ISB
0130-8
Read Cycle No. 3[20]
Read with BUS\; Master: CY7C130 and CY7C131
IRc
)(
ADDRESSR
)(
ADDRESS MATCH
IPWE
R/WR
.]~
~
'I(
)E
- -
ADDRESSL
VALID
IHO
)(
ADDRESS MATCH
IpS
iot-leHA
-~BLA
IBOO-
)~
twoo
1000
C130-9
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)[15.22]
Either Port
~----------------------twc----------------------~
ADDRESS
R/W
ISO
DATAJN
DATA VALID
t~Ea
DOUT
»»»
HIGH IMPEDANCE
C130-10
2-83
II
CY7C 130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No.2 (RtWTbree-States nata I/Os - Either Port)[lS.23)
EltberPort
~---------------~C--------------------~
ADDRESS
'sCE
NW ______~__~__~~~~-------t~E------~~---------------DATAjN
DATAouT
)
)
)
)
)
)
)
)
)
)
)
)
~~~
) )
tuwE - , ..
~,..,.<..,.«..,..<.,..,~P""J<
HIGH IMPEDANCE
C130-11
Busy Timing Diagram No. 1 ~ Arbitration)
CEL Valid First:
ADDRESSL,R
X
~~b
t=t:L
CE'R
X
ADDRESS MATCH
t~~
BUS'i'R
t~)
C130-12
CER Valid First:
ADDRESSL,R
CE'R
t=t:L
WSVL
X
X
ADDRESS MATCH
~~b
t~~
t~1
C130-13
2-84
CY7C130/CY7C131
CY7C140/CY7C141
" c~
_".CYPRESS
~F SEMICONDUCTOR
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
II
Left Address Valid First:
f---
'?
ADDRESSL
IRe OR twc
ADDRESS MATCH
'?
ADDRESS MISMATCH
-tps-
~~
ADDRESSR
i+- tBLA
I---
tBHA
C130-14
Right Address Valid First:
-lReORtwc
ADDRESSR
~(
ADDRESS MATCH
) (
ADDRESS MISMATCH
_tps_
~I(
ADDRESSL
--1_1
.... tBLA
L
mJSY
-tBHA
C130-15
Busy Timing Diagram No.3
Write with BUSY (Slave: CY7Cl40/CY7C141)
~ ~~---------------------------------
---{_~J==_tPWE-f-----..l~l
C130-16
2-85
CY7C 130/CY7C131
CY7C140/CY7C141
~
~ ;;~PRESS
:zg'
SEMICONDUCTOR
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR
lwe
WRITE3FF
ADDRR
0130-17
~
Right Side Clears OOR
XXXXXXXXXXXXeX ____
:-I . .
IRO
REA_D_3F.,...F_"*""",""-_ _
'C"E'R
RiWR
OER
0130-18
Right Side Sets INTL
' - - - - - - - lwe - - - - - -__
WRITE3FE
0130-19
Left Side Clears INTL
ADO"
CE"L
XXXXXXXXXXXX~____
_*""'""-__
REA_I:_C3F.,...E
~~~~====~--0130-20
2-86
CY7C130/CY7C131
CY7C140/CY7C141
~
;~PRFSS
5
~,
SEMlcamUCI'OR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
III
j
1.0
N
<:
SUPPLY VOLTAGE (V)
() 2.5
1.5
20
0
!z
0.6
-55
6.0
~
~
~
Vee = 5.0V
TA= 25°C
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
./
1.0
0.8
5.5
40
~14O
-120
1.2
30.0
:J
125
1.4
3.0
cw
::>
g
25
c
tr
0 1.0
z
r--........
tr
1.6
1.1
tr
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
c
w 1.2
endently on each port by the
applications requiring shared or buffered chip enable (CE) pins.
data such as cache memory for DSp, bit- The CY7C132/CY7CI42 are available in
slice, or mUltiprocessor designs.
both 48-pin DIP and 48-pin LCC. The
Each port has independent control pins; CY7C136/CY7C146 are available in both
chip enable (CE), write enable (RiW), and 52-pin LCC and 52-pin PLCC.
Logic Block Diagram
Pin Configuration
RJWL
MVR
GEL
GER
DEL
OER
A 10L
AlOR
DIP
'lbpView
eEL
RJWL
BUSYL
A7L
A7R
IloOL
flOOR
I/o'L
I/0 7R
SUSYR{1j
BUSYL'"
AsL
AsR
AoL
AOR
A10L
DEL
AoL
A'L
AoL
AaL
il2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Range
Thmperature
O°Cto +70°C
Vee
5V± 10%
Industrial
- 40°C to +85°C
5V± 10%
Militaryl4]
- 55°Cto +125°C
5V± 10%
Commercial
Notes:
3.
25-ns version available in LCC and PLCC packages only.
4.
2-92
TA is the "instant on" case temperature
....::::::==...
CY7C132/CY7C136
CY7C142/CY7C146
,~PRF..'iS
.
_
IF
SEMICONDUCTOR
Electrical Characteristics
Overthe Operating RangerS]
7C1322S,30[3]
7C136·2S,30
7C142·2S,30
7C146.2S,30
Description
Parameter
Thst Conditions
Min.
VOH
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
IOL = 16.0 mA[7]
0.5
0.5
0.5
2.2
Input Load Current
GND.$. VI.$. Vee
GND.$. Vo.$. Vee,
Output Disabled
-5
los
Output Short
CircuitCurrent[8]
Vee = Max.,
VouT=GND
Icc
Vee Operating
Supply Current
CE=VIL,
Outputs0t8en,
f=fMAX[
ISB4
2.2
0.8
+5
+5
-5
+5
-5
+5
-5
Com'l
170
Mil
Com'l
CELandCER~ Vrn,
f=fMAX[6]
65
Mil
CELorCER~ Vrn,
Active Port Outputs Open,
f=fMAX[6]
Com'l
115
Mil
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2y,
VIN ~ Vee - 0.2Vor
VIN.$. 0.2y, f = 0
Com'l
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN.$. 0.2Y,
Active Port Outputs Open,
f=fMAX[6]
Com'!
15
Mil
105
Mil
V
2.2
0.8
-5
- 350
Units
V
0.4
Output Leakage
Current
ISB3
Max.
2.4
0.4
IIX
IsB2
Min.
Max.
2.4
0.4
loz
Standby Current
Both Ports,
ITLlnouts
Standby Current
One Port,
TTLlnouts
Min.
7C132·4S,SS
7C136-4S,SS
7C142·4S,SS
7Cl46-4S,SS
IOL=4.0rnA
-5
ISBl
Max.
2.4
7C132·3S
7C136·3S
7C142·3S
7C146·3S
-350
V
0.8
V
+5
+5
!JA
!JA
- 350
rnA
rnA
120
90
170
120
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
rnA
rnA
rnA
rnA
Capacitance [9]
Parameters
Thst Conditions
Description
CIN
InputCapacitance
GoUT
Output Capacitance
TA = 25°C,f= 1 MHz,
Vee=5.0V
Notes:
S. See the last page of this specification for Group A subgroup testing in·
formation.
6. At f=JMAx, address and data inputs are cycling at the maximum frequency of read cycle of lItre and using AC Thst Waveforms input levels
ofGNDt03Y.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. Thsted initially and after any design or process changes that may affect
these parameters.
10. Thst conditions assume signal transition times of S ns or less, timing
reference levels of I.Sy, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH, and 30-pF load capacitance.
Max.
Units
15
pF
10
pF
11. ACtestconditions use VOH = 1.6V and VOL = lAY.
12. tIZCE, trzwE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL =
SpF as in part (b) of AC Thst Load& 'ftansition is measured ±SOO mV
form steady state voltage.
13. At any giveu temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
14. The internal write time of the memory is dermed by the overlap of CE
LOW and RiW LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referencd to the rising edge of the signal that terminates the write.
2-93
--..
CY7C132/CY7C136
CY7C142/CY7C146
~~
.'~NDUCIDR
AC Test Loads and Waveforms
5V
R1 B931;)
0------_.,
5V
OUTPlrrO-----jt---+
30PFI
B931;)
0-_____R1_.,
OUTPlrrO-----jt---+
5PFI
R2
3470
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
ljOSY
OR
R2
I30
PF
':'
C132-5
(b)
C132-6
BUSY Output Load
(CY7C132/CY7C136 ONLy)
ALL INPUT PULSES
:.::~~
2501;)
C).O--~'11\
••" ' - - _ O
2810
iNf
34m
THEvENIN EQUIVALENT
OUTPlrr
~5V
1.4V
~
Switching Characteristics Overthe Operating Raogd5,1O]
7C132-25LjJ
7C136-25
7C142-25
7C146-25
Parameters
Description
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
7C132-35
7C136-35
7C142-35
7Cl46-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7Cl46-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7Cl46-55
Min.
Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid[l1]
tOIlA
Data HoLd from
Address Change
tACE
CE LOW to Data Valid[ll]
25
30
35
45
55
ns
tOOE
OE LOW to Data Valid[ll]
15
20
20
25
25
ns
tUOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[12]
tUCE
CE LOW to Low Z[13]
tHZCE
CE HIGH to High Z[12,13]
tpu
CE LOW to Power-Up
30
25
0
0
3
5
15
15
CE HIGH to Power-Down
tpo
WRITE CYCLEi14]
25
20
0
0
20
5
0
ns
ns
25
ns
ns
0
35
35
25
ns
25
20
os
ns
3
5
5
ns
55
0
3
20
15
55
45
0
3
5
0
35
0
3
15
45
35
30
25
35
ns
twc
Write Cycle Time
25
30
35
45
55
ns
tsCE
CE LOW to Write End
20
25
30
35
40
ns
tAW
Address Set-Up to Write End
20
25
30
35
40
ns
tllA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R/WPuise Width
15
25
25
30
30
ns
tso
Data Set-Up to Write End
15
15
15
20
20
ns
tHO
Data HoLd from Write End
0
0
0
0
0
tHZWE
R/WLOW to High Z
tuWE
R/WHIGH to Low Z
15
0
15
0
2-94
20
0
20
0
ns
25
0
ns
ns
CY7C132/CY7C136
CY7C 142/CY7C146
~ :;~PRFSS
.......... ,
SEMlCONDlJCTOR
Switching Characteristics Over the Operating Rangel5,10] (continued)
7C132-25L3j
7C136-25
7C142-25
7C146-2S
Parameters
Description
Min.
Max.
7C132-30
7C136-30
7C142-30
7Cl46-30
Min.
Max.
7C132-35
7C136-3S
7C142-35
7C146-3S
Min.
Max.
7C132-45
7C136-4S
7C142-45
7Cl46-4S
Min.
7C132-55
7C136-SS
7C142-5S
7C146-5S
Max.
Min.
Max. Units
BUSY/lNfERRUPT TIMING
tBLA
tBHA
BUSYLOWfrom Address Match
BUSY HIGH from
Address Mismatch[15]
20
20
tBLC
tBHC
tps
BUSY LOW from CE LOW
BO'SY HIGH from CEHIGHL15j
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
20
20
tWB L1bj
tWH
tBoo
toDD
tWDD
20
20
20
20
5
0
20
20
20
25
25
30
30
ns
20
20
25
25
30
30
ns
5
0
30
5
0
30
5
0
35
ns
ns
5
0
35
ns
ns
ns
25
30
35
45
45
ns
Note
17
Note
17
Note
17
Note
17
Note
ns
Note
17
Note
17
Note
Note
17
Note
17
ns
17
25
25
25
25
25
25
25
25
25
35
35
35
45
45
45
ns
25
25
25
35
45
ns
25
25
25
35
45
ns
25
25
25
35
45
ns
17
INTERRUPT TIMING[18]
tWINS
tEINS
tINS
tOlNR
R/W to Il'l'TERltUpT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT
Set Time
OE to INTERRUPT
Reset Time[15]
tEINR
CE to INTERRUPT
tINR
Address to INTERRUPT
Reset Time[15]
Reset Time[15]
Notes:
15. These parameters are measured from the input signal changing, untiL
the output pin goes to a high-impedance state.
16. CY7C142/CY7Cl46 only.
17. A write operation on Port A, where Port A has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
foll°Bt&
A.
on Port B goes HIGH.
B. Port B's address toggled.
C. en for Port B is toggled.
D. R/W for Port B is toggled during valid read
18.
19.
20.
21.
22.
ns
ns
52-pin LCCIPLCC versions only.
R/W is HIGH for read cycle.
Device is continuously selected, "CE = V IL and OE = V IL.
Address valid prior to or coincident with
transition LOW
If OE is LOW during a RiW controlled write cycle, the write pulse
width must be the larger of tPWE or tHZWE + Iso to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required Iso.
23. If the
LOW transition occurs simultaneously with or after the R/W
WW transition, the outputs remain in a high-impedance state.
rn
rn
Switching Waveforms
Read Cycle No. 1[19,20]
ADDRESS
DATA OUT
=t
PREVIOUS
Either Port-Address Access
~~l.-----_~__D;:V:;txXX~
_ _ _ _ _ _ _D_A_:rA_VA_L_ID_ _ _ _ _ __
C132-7
2-95
•
CY7C132/CY7C136
CY7C142/CY7C146
e;~PRSS
~.L
SEMICONDUCTOR
Switcbing Waveforms (continued)
Read Cycle No. 2[19, 21]
CE
Either Port-CEIOE Access
~I'\.
~
j.-IH2CE-
!.-ILZOE~ILZCE
DATA OUT
Icc
-
IH20E
looE-
...,r-////////
tpu
..,1"
tACE
DATA VALID
...,,, """" ""
r-
-tpo
/I
ISB - - / ' .
C132-8
Read Cycle No.3
Read with BUSY Master: CY7C132 and 7CI36[20]
tRC
)K
ADDRESSR
tPWE
"I
~
~
a::
/
g: 10.0
/
V
1.25
~
@ 1.0
7
BO
TYPICAL ACCESS TIME CHANGE
n. OUTPUT LOADING
3.0
4.0
v
a::
5
Z
iii
"""
0.6
-55
6.0
f'......
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 100
l<:
Vee = 5.0V
'"
2.0
OUTPUT VOLTAGE (V)
1.6
/'
Vee = 5.0V
TA=25°C
f'......
S. 120
1.3
rr
i
faN
g
n. AMBIENT TEMPERATURE
1.4
~
~ 60
rr
NORMAUZED ACCESS TIME
NORMAUZED ACCESS TIME
vs. SUPPLY VOLTAGE
~
~
BO
AMBIENT TEMPERATURE ("C)
SUPPLY VOLTAGE (V)
fa
ffirr 100
O.BI-----1-----..:~
o
o 0.4
j
g, 120
1.2
.
Jl
lee,../
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
VI. AMBIENT TEMPERATURE
VI.
@0.751----bo"c;.--+~---1
Vee = 4.5V
TA = 25°C
"
_
I
200 400 600 BOO 1000
CAPACITANCE (PF)
2-100
0·501L.0---2.l.0---3.L0--.....J40
CYCLE FREQUENCY (MHZ)
CY7C132/CY7C136
CY7C142/CY7C146
~
.
'~PRFSS
F
SEMICONDUCIDR
Ordering Information
Speed
(ns)
Ordering Code
Package
tYPe
Operating
Range
Speed
(ns)
25
25
CY7C132-25LC
L68
Commercial
30
CY7C132-30DC
D26
Commercial
CY7C132-30LC
L68
35
45
55
30
Package
'iYpe
Operating
Range
CY7C136-25JC
J69
Commercial
CY7C136-25LC
L69
CY7C136-30JC
J69
Ordering Code
Commercial
CY7C136-30LC
L69
CY7C136- 30JI
J69
Industrial
CY7C136-35JC
J69
Commercial
CY7C136-35LC
L69
CY7C132-30PC
P25
CY7C132-30DI
D26
CY7C132-30PI
P25
CY7C132-35DC
D26
CY7C132-35LC
L68
CY7C136-35JI
J69
CY7C132-35PC
P25
CY7C136-35LMB
L69
Military
CY7C132-35DI
D26
CY7C136-45JC
J69
Commercial
CY7C136-45LC
L69
CY7C136-45JI
J69
CY7CI36-45LMB
L69
Military
CY7C136-55JC
J69
Commercial
CY7C136-55LC
L69
CY7C132-35PI
P25
CY7C132-35DMB
D26
Industrial
35
Commercial
45
Industrial
Military
Industrial
Industrial
CY7C132-35FMB
F78
CY7C132-35LMB
L68
CY7C132-45DC
D26
CY7C132-45LC
L68
CY7C136-55JI
J69
Industrial
CY7C132-45PC
P25
CY7C136-55LMB
L69
Military
CY7C132-45DI
D26
CY7C132-45PI
P25
CY7CI32-45DMB
D26
CY7C132-45FMB
F78
CY7C132-45LMB
L68
CY7C132-55DC
D26
CY7C132-55LC
L68
CY7C132-55PC
P25
CY7C132-55DI
D26
CY7C132-55PI
P25
CY7C132-55DMB
D26
CY7C132-55FMB
F78
CY7C132-55LMB
L68
55
Commercial
Industrial
Military
Commercial
Industrial
Military
2-101
•
CY7C132/CY7C136
CY7C142/CY7C146
.7,~NDUCR)R
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
tYPe
Operating
Range
Speed
25
(ns)
25
CY7C142-25LC
L68
Commercial
30
CY7C142-30DC
D26
Commercial
CY7C142-30LC
L68
35
45
55
30
Package
tYPe
Operating
Range
CY7C146-25JC
J69
Commercial
CY7C146-25LC
L69
CY7C146-30JC
J69
CY7C146-30LC
L69
CY7C146-30JI
J69
Industrial
CY7C146-35JC
J69
Commercial
CY7C146- 35LC
L69
Ordering Code
Commercial
CY7C142-30PC
P25
CY7C142- 30DI
D26
CY7C142-30PI
P25
CY7C142-35DC
D26
CY7C142-35LC
L68
CY7C146-35JI
J69
CY7C142-35PC
P25
CY7C146- 35LMB
L69
Military
CY7C142-35DI
D26
CY7C146-45JC
J69
Commercial
CY7C142-35PI
P25
CY7C146-45LC
L69
CY7C142-35DMB
D26
CY7C142-35FMB
F78
CY7C142-35LMB
L68
CY7C142-45DC
D26
CY7C142-45LC
L68
CY7C142-45PC
P25
CY7C142-45DI
D26
CY7C142-45PI
P25
CY7C142-45DMB
D26
CY7C142-45FMB
F78
CY7C142-45LMB
L68
CY7C142-55DC
D26
CY7C142-55LC
L68
CY7C142-55PC
P25
CY7C142- 55DI
D26
CY7C142- 55PI
P25
CY7C142-55DMB
D26
CY7C142-55FMB
F78
CY7C142-55LMB
L68
Industrial
35
Commercial
45
Industrial
Military
55
Commercial
Industrial
Military
Commercial
Industrial
Military
2-102
Industrial
CY7C146-45JI
J69
CY7C146-45LMB
L69
Industrial
Military
CY7C146-55JC
J69
Commercial
CY7C146-55LC
L69
CY7C146-55JI
J69
Industrial
CY7C146-55LMB
L69
Military
CY7C132/CY7C136
CY7C142/CY7C146
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
loz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
ISB3
1,2,3
ISB4
1,2,3
en
::E
Orr.z«
oCt:
7 6 5 4 3 2 !11 52 51 50 49 4847
A"
A:!L
AaL
!\oL
AaL
AsL
9
10
11
12
13
A7l
14
A7R
AaL
AsL
I/00L
AaL
I/OoL
AsR
AsR
1/0 2L
1/0"
110m
Vaal
15
16
17
18
19
20
I/0 2L
Vo"L
I/0 4L
VOsL
I/D6l
VOSR
1/0"
78135
45
44
43
42
41
AaR
A'R
A:!R
AaR
!\oR
AaR
40
39
38
37
36
35
34
AsR
AsR
NC
Vo,R
I/0 4R
1342-3
LCC/PLCC
ThpView
~
~~ ~I::; "....~"
o:tl::;
0 - W 1<:.II'w "lID"
ca:Elw
0 « 0 0 a:0> 0
6 5 4 3 211148 47 46 45 44 43
42
41
40
10
39
11
38
78134
12
37
13
36
14
35
15
34
16
33
17
32
18
31
1920 21 22 23 24 25 26 27 2B 29 30
AaR
A7R
AsR
AsR
V07R
va"
~L
V0 6R
a: a: a:. rr. a::. a:
g'5:~glrJ gCOg~ 'lgrl~gvrt
...J...J...J
0:
a: a:
W - 0
00<:<
7 6 5 4 3
A"
A:!L
AaL
!\oL
AaL
AsL
A7l
AsL
AgL
I/00L
AuR
AlA
A:!R
AaR
!\oR
AaR
Vo"L
OER
9
10
11
12
13
AuR
AlA
781342
41
14
15
16
17
18
ffi
20
A:!R
AaR
!\oR
~R
AsR
A7R
AgR
AgR
36
34
~
V07R
21 22 23 24 25 2B 27 28 29 30 31 32 33
...J...JC
1342-4
Pin Definitions
LeftPort
AoL-llL
CEL
OEL
RiWL
SEML
(CY7B1342
only)
Right Port
AoR-llR
CER
OER
RiWR
SEMR
(CY7B1342
only)
Description
Address Lines
Chip Enable
Output Enable
Read/\\1ite Enable
SemaphoreEnable. When asserted LOW, allows access to eight semaphores. The three least
significant bits of the address lines will determine which semaphore to write or read. The
1100 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into
the respective location.
2-105
en
::::i
2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ > 200 rnA
Operating Range
Ambient
Thmperature
O°Cto +70°C
Vee
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Militaryl~J
-55°C to +125°C
5V ± 10%
Range
Commercial
Over the Operating Rangef3]
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min.,loH = -4.0 rnA
VOL
Output LOW Voltage
V cc = Min., IOL = 4.0 rnA
Input HIGH Voltage
VlL
IIX
Input Load Current
loz
Output Leakage Current
Icc
Operating Current
Vee = Max.,
lOUT = ornA
Com'l
CELandCER~ V1H,
Com'l
ISB3
ISB4
78134-35
78135-35
781342-35
Min.
Min.
Min.
Max.
0.4
V
0.4
2.2
0.8
0.8
V
V
0.8
V
GND:S VI:S Vee
-10
+10
-10
+10
-10
+10
Outputs Disabled,
GND'""?"..,...,I_rr7..,....,"'T7'"T
lAW
--_14-----------IPWE
___1--_ _ _
------""-'~ ,,_ _ _ _ _ _ _ _ __
R/W
...t==
-----------------~
ISD
DATA VALID
. ' . IHD;t
• ~-------
HIGH IMPEDANCE
1342-13
Note:
15. CEL = CER =LOW; RiWL = mGH
16. The internal write tim~f the memory is defined by the overlap of CE
or SEM WW and RJWWW. Both signals must be LOW to initiate
a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
17. RiW must be mGH during all address transactions.
18. If DE is WW during a RiW controlled write cycle, the write pulse
width must be the larger of tpWE or (4IZWE + tSD) to allow the I/O
drivers~turn off and data to ~placed on the bus for the required
tSD. If DE is HIGH during a RJW controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
19. SEM only applies to CY7B1342
2-109
-n
~
CY7B134
CY7B135
CY7B1342
PRELIMINARY
PRESS
SEMlCONDUClDR
Switching Waveforms (continued)
Write Cycle No.2: RJW 'frj-States Data I/Os (Either Port)[17,20]
~------------------- twc ------------------------~
ADDRESS
tseE
SEl\)j[19] OR CE
___...!:==~.,;::=::j--- tPWE - - - - - I ,---------------
~
~
») ) ) ) ) ) ) » ) ) )
tHZNE
DATAoUT
tlZWE
HIGH IMPEDANCE
---L
--']"'(7""('7'"("'7'("'7'("7"'<
1342-14
Semaphore Read After Write Timing, Either Side (CY7B1342 only)[21]
1/00
.
-----l---l-..rDAr;!.;.VALiiD'i-------
AoL
60
59
58
57
56
AoL
AoL
Aa
A'l
Aol
ml
BDSYl
55
54
53
78138/9
OND
52
51
50
49
48
MIS
BDSYR
mR
AoR
A'R
""R
47
46
45
44
24
25
26
AoR
AoR
272629~~323334~38~383940~~43
!-.,
"'luf00 0 ~ S}}}}}
",]I!!"'~'"moZZ~Z«
19
NC!3}
C
8138-3
17
Vee 00,," V02R 1103R VO'" VO..
...J .....
9 8 7 6 5 4 3 2 168 6766 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
A11R
~ ~~ ",I!,! ~ ~~ ~.f;
8138-2
Notes:
3. f/OSR on the CY7B139.
4. f/OSL on the CY7B139.
Pin Definitions
Left Port
Right Port
Description
1I0 0L-7L(8L)
1I0 0R -7R(8R)
Data Bus Input/Output
AOL-llL
CEL
AoR-IlR
CER
Address lines
OEL
OOR
Output Enable
RiWL
SEML
RiWR
SEMR
Read/Write Enable
IN'fL
lNTR
Interrupt F1ag.'INTL is set when ri~rtwrites location FFE and is cleared
when left port reads location FFE. I R is set when left port writes location
FFF and is cleared when right port reads location FFE
lffiSYL
mJSYR
BusyF1ag
Chip Enable
Semaphore Enable. When asserted LOW, allows access to eight semahhores.
The three least significant bits of the address lines will determine whic semaphore to write or read. The 1100 pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
MIS
Master or Slave Select
Vee
GND
Power
Ground
Selection Guide
Maximum Access Time (ns)
Maximum ~erating
Current (rnA
Maximum Standby
Current for ISBt(mA)
Commercial
7B138-15
7B139-15
15
7B138-25
7B139-25
25
7B138-35
7B139-35
35
260
220
210
280
250
75
70
80
75
Military
Commercial
90
Military
2-115
•
II)
:::'IE
ct
a::
en
CY7B138
CY7B139
PRELIMINARY
Maximum -Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Thmperature ....•.••.....•... - 65·C to + 150·C
Ambient Thmperature with
Power Applied ...............•...... - 55·C to + 125·C
Supply Voltage to Ground Potential .•••... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ....•................... - O.SV to + 7.0V
DC Input VoltagelS) •••••••••••••••••••• - 3.5V to + 7.0V
Output Current into Outputs (LOW) ••............ 20 mA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..............••.•........• >2oomA
Operating Range
Ambient
Temperature
Vee
O·Cto + 70·C
5V± 10%
Range
Commercial
Industrial
-40·C to + SSoC
5V± 10%
Militaryl6)
- 55·Cto + 125·C
5V± 10%
Electrical Characteristics Over the Operating Rangel7]
Parameter
VOH
VOL
VIH
VIL
IJX
Ioz
lee
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
7B138 25
7B138 15
7B139-15
7B139-25
Test Conditions
Min. Max. Min. Max.
2.4
2..4
Vee = Min., IOH = -4.0 rnA
0.4
0.4
Vee - Min., IoL - 4.0 rnA
2.2
2.2
0.8
0.8
-10 +10 -10 +10
GND oS. VI oS. Vee
Output Disabled, GND oS. Va oS. Vee -10 +10 -10 +10
220
Corn'l
260
Vee = Max.,
lOUT = ornA,
Mil/lnd
280
Outputs Disabled
ISBl
Standby Current
(Both Ports TTL Levels)
CELandCER~ VIH,
ISBZ
Standby Current
(One Port TTL Level)
ISB3
ISB4
Standby Current
(BothPortsCMOSLevels)
Standby Current
(One Port CMOS Level)
CELandCER~ VIH,
Com'l
Mil/lnd
Corn'l
160
Both Ports
MillInd
Com'l
15
f= fMAX IS)
f= fMAXIS)
'CEand'CER~ Vee- 0.2Y,
VIN~ Vee - 0.2V
or VIN oS. 0.2Y, f = (18)
Mil/lnd
One Port
Corn'l
VIN ~ Vee - 0.2Vor
VIN oS. 0.2Y, Active
Port Outputs, f = fMAX IS)
Mil/lnd
'CELorrnR~ Vee - 0.2Y,
90
140
7B138-35
7B139-35
Min. Max.
2..4
0.4
2.2
0.8
-10 +10
-10 +10
210
Unit
V
V
V
V
J-IA
J-IA
rnA
250
75
80
140
180
15
70
75
130
160
15
30
30
120
110
150
130
rnA
rnA
rnA
rnA
Capacitance(9)
Parameters
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Note.:
5. Pulse width < 20 DB.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing information.
8.
9.
2-116
= 1 MHz,
Max.
10
15
Unit
pF
pF
fMAX = IltRC = All inputs cycling at f = I/tRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby IS83.
1bsted initially and after any design or process changes that may affect
these parameters.
;~PRESS
--=-.!F
CY7B138
CY7B139
PRELIMINARY
SEMICONDUCTOR
AC Test Loads and Waveforms
~-:~ ± i:::
OUTPU:
=::r'
R1 =893.0.
OUTPUT
1
. -b
(a) Normal Load (Load 1)
L
C=5pF
YlH-1.4V
I.
-=
R2-347.o.
(c) Three-State Delay (Load 3)
(b) Thevenin Equivalent (Load 1)
B138-4
OUTPUT
:rl •
5V
Rrn ~ 25O!l.
B138-5
B138-6
ALL INPUT PULSES
I
3'W~~
~
1~
GND
C=30pF
10%
.s,3ns
.s.3ns
Load (Load 2)
B138-7
B138-8
Switching Characteristics Over the Operating Rangel lO•ll ]
Parameters
READ CYCLE
Description
7B138-15
7B139-15
Min.
Max.
tRC
tAA
Read Cycle Time
Address to Data Valid[l2]
15
tOHA
Output Hold From Address Change
CE LOW to Data Valid[l2]
3
tACE
3
tHZOE[13]
tLZCE[l3]
"C:EWWtoLowZ
3
tHZCE[l3]
rn mGH to High Z
tpu
tpD
WRITE CYCLE
25
us
35
3
3
us
us
25
35
us
10
15
20
us
20
us
20
ns
15
3
3
0
15
0
us
ns
0
25
15
us
3
3
10
CE WW to Power-Up
35
Units
15
10
rn mGH to Power-Down
7B138-35
7B139-35
Min.
Max.
25
15
OE WW to Data Valid[l2]
OE Low to Low Z
OE HIGH to High Z
tDOE
tLZOE[l3]
78138-25
7BI39-25
Min.
Max.
35
us
twc
Write Cycle Time
15
25
35
ns
tSCE
rn WW to Write End
12
20
30
us
tAW
tHA
Address Set-Up to Write End
12
20
30
us
Address Hold From Write End
2
2
2
us
tSA
tpWE
Address Set-Up to Write Start
0
0
us
Write Pulse Width
0
12
20
25
us
tSD
Data Set-Up to Write End
10
15
15
us
tHD
tHZWE[l3]
Data Hold From Write End
0
0
0
us
tLZWE[l3]
R/W WW to High Z
R/W mGH to Low Z
3
tWDD[l4j
Write Pulse to Data Delay
30
50
60
tDDD[l4]
Write Data Valid to Read Data Valid
25
30
35
10
2-117
20
15
3
3
us
us
us
us
CY7B138
CY7B139
PRELIMINARY
Switching Characteristics Over the Operating Range[10. 11) (continued)
Parameters
BUSY TIMlNG[lS)
I
Description
tBLA
tBHA
tBLC
tBHC
tps
'BUSY LOW from Address Match
BmY HIGH from Address Mismatch
tWB
WE LOW after BUSY LOW
7B138-15
7B139-15
Min. I Max.
nmYLOW from rnLOW
BUSY HIGH from
HIGH
Port Set-Up for Priority
en
WE HIGH after BUSY HIGH
tWH
BUSY HIGH to Data Valid
tBOO
INTERRUPF TIMlNG[lS]
I
Notes:
10. See the last page ofthis specification for Group A subgroup testing information.
11. Thst conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, input pulse levels of 0 t03.0V, and output loading
of the specified IOIlIoH and 30-pF load capacitance.
12. AC test conditions use VOH 1.6V and VOL 1.4Y.
=
I
Units
20
20
DB
20
20
DB
20
20
20
20
DB
5
0
DB
13
20
25
5
0
30
35
25
DB
25
DB
I
15
15
10
5
5
I
7B138-35
78139-35
Min. I Max.
15
15
15
15
5
0
15
TIii'f Set Time
tINS
I TIii'f Reset Time
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE or SEM)
tsop
SEM Flag Write to Read Time
tSWRo
SEM Flag Contention Window
tsps
=
I
7B138 25
7BI39-25
Min. I Max.
I
10
5
5
25
25
15
5
5
DB
DB
DB
DB
DB
DB
DB
13. Thst conditions used are Load 3.
14. For information on part-to-part delay through RAM cells from writingport to reading port, refer to Read 'liming with Port-to-Port Delay
waveform.
IS. Thst conditions used are Load 2.
2-118
5
;~PRESS
-=-,
CY7B138
CY7B139
PRELIMINARY
SEMICONDUCTOR
*_ •
Switching Waveforms
Read Cycle No. 1[20,21]
~
_
Either Port Address Access
_ _
IRC _ _
4=D~~~V=ixxxXX~1 ""_-_-_-_-_-_-_-_-_-_-_-_D-A~!_'A-_V-A~L_I-D~~~~~~~~~~~_
ADDRESS
tAA
DATA OUT
PREVIOUS
....
B138-11
Read Cycle No. 2[18, 19, 20]
~orcr
Either Port CE/OE Access
~,
~~
-- IHZCE-
tACE
~
tHZOE
~lt..zOE-
tOOE - -
t12CE
DATA OUT
ICC
ISB
-
,L///////,
lpu
-'
DATA VALID
r-
i-lpo
/I
--../
•
Read Timing with Port-to-Port Delay (MIS' = L)[16,17]
twc
ADDRESSR
~~
~
MATCH
IPWE
~'"
/
_ISO
)(
DATAINR
ADDRESSL
VALID
f
MATCH
tO~~
)
DATAoUTL
~
twoo
-
Bl38 9
Notes:
16, BUSY = HIGH for the writing port,
17. CEL = CER = LOW.
18. Address valid prior to or coincident with
transition LOW.
19. eEL = L, SEM = H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
rn
20. R/W is HIGH for read cycle.
21. DeviceiscontinuouslyselectedCE = LOWandOE = LOW. Thiswaveform cannot be used for semaphore reads.
\
2-119
en
~
<-----------
8138-14
Notes:
26. I/OOR = I/OOL = LOW (request semaphore); eER = eEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
29.
2-121
rn = HIGH for the duration ofthe above timing (both write and read
cycle).
CY7B138
CY7B139
PRELIMINARY
Switching Waveforms (continued)
Timing Diagram of Read with 'iiUSY (M/S'=HIGH)[17)
twc
.,(
ADDRESSR
(
MATCH
tPWE
~~
;""
!ti~
~tso
)(
DATAINR
Ips
ADDRESSL
I-)f
4 - I-
VALID
MATCH
f - - - taHA
tBLA-=:1
tO~~
~tBOO_
)E
DATAoUTL
twoo
8138-16
Write Timing with Busy Input (MIS=WW)
8138-17
2-122
....L~
_ ; cYPRESS
-=-F
CY7B138
CY7B139
PRELIMINARY
SEMJCa.IDUCIOR
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[30)
eEL Valid First:
ADDRESSL,R
X
X
ADDRESS MATCH
~"b
CE"L
CE"R
iIDS'i'R
IB~~
t~1
I/)
:::E
200rnA
Operating Range
Supply Voltage to Ground Potential. . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .........................
DC Input Voltage!5] .....................
> 2001V
2.4
78144-25
78145-25
Min. Max.
78144-35
78145-35
Min. Max.
2..4
2..4
0.4
2.2
0.4
2.2
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
V
V
+10
I4A
I4A
220
210
rnA
280
250
75
70
80
75
140
130
180
160
15
15
30
30
120
110
150
130
-10
+10
-10
+10
-10
+10
-10
+10
-10
260
90
Mil/Ind
160
MilIInd
Com'l
V
0.8
+10
Mil/lnd
CEandCER~ Vee-
0.8
-10
Com'l
Both Ports
V
0.4
2.2
0.8
Unit
15
rnA
rnA
rnA
02Y,
VIN > Vee - 0.2V
or VIN 5 0.2Y, f = 0[8]
MilJlnd
One Port
Com'l
CELorCER~ Vee-0.2Y,
VIN ~ Vee - 0.2Vor
VIN 5 0.2Y, Active
Port Outputs, f = fMAX[8]
Mil/Ind
140
rnA
Capacitance [9]
Parameters
CIN
CoUT
Description
'lest Conditions
Max.
Unit
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
10
pF
Vee=5.0V
15
pF
Notes:
5. Pulse width < 20 DS.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing information.
8.
9.
2-130
fMAX = litRe = All inputs cycling at f = litRe(except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3.
Thstedinitially and after any design or process changes that may affect
these parameters.
=r'--'
-== ~PRESS
F
CY7B144
CY7B145
PRELIMINARY
SEMICONDUCTOR
AC Test Loads and Waveforms
I::: •
5V
our::"l
1::~~
RTH =2500
OUTPUT~
(a) Normal Load (Load 1)
C=30pF
I
1
0",::"
VTH = 1.4V
(b) Thevenin Equivalent (Load 1)
B144-4
f
(c) Three-State Delay (Load3)
8144-5
8144-6
ALL INPUT PULSES
OUTPUT~
I
~
10%
C=30pF
--
Load (Load 2)
53ns
8144-7
8144-8
Switching Characteristics Over the Operating RangdlO,llj
Parameters
READ CYCLE
tRC
tAA
tOHA
tACE
Description
7B144-15
7B145-15
Min. Max.
Read Cycle Time
Address to Data Valid[12j
15
Output Hold From AddressChange
CE LOW to Data Valid[12j
3
tDOE
tLZOE[13j
OE LOW to Data Valid[12j
tHZOE[13j
tLZCE[13j
OE HIGH to High Z
OE Low to Low Z
7B144-25
7B145-25
Min. Max.
25
15
7B144-35
7B145-35
Min. Max.
35
25
ns
35
3
3
25
35
10
15
20
3
3
15
10
ns
ns
15
3
Units
ns
ns
ns
20
ns
ns
20
ns
3
tHZCE[13j
CE LOW to Low Z
CE HIGH to High Z
tpu
CELOWtoPower-Up
0
tpD
WRITE CYCLE
CE HIGH to Power-Down
twc
Write Cycle Time
15
25
35
ns
tSCE
CE LOW to Write End
12
20
30
ns
tAW
Address Set-Up to Write End
12
20
30
ns
tHA
tSA
tpWE
Address Hold From Write End
2
2
ns
Address Set-Up to Write Start
Write Pulse Width
2
0
12
0
20
0
25
ns
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
tHZWE[13j
tLZWE[13j
Data Hold From Write End
0
0
0
3
15
10
25
10
tWDD
R/WHIGH to Low Z
Write Pulse to Data Delay
3
30
tDDD
Write Data Valid to Read Data Valid
25
2-131
0
0
15
R/WLOW to High Z
3
15
3
ns
35
ns
ns
20
3
ns
ns
50
60
ns
30
35
ns
CY7B144
CY7B145
PRELIMINARY
Switching Characteristics Over the Operating Rangel10,1l] (continued)
Parameters
BUSYTIMlNGlJ "J
7B144-15
7B145-15
Min. Max.
Description
78144-25
78145-25
Min. Max.
78144-35
78145-35
Min. Max.
Units
20
ns
20
ns
15
20
20
20
20
ns
BUSY HIGH from CE HIGH
15
20
20
ns
Port Set·Up for Priority
5
5
5
ns
0
0
ns
20
30
ns
35
ns
tBlA
BUSY LOW from Address Match
15
tBRA
BUSY HIGH from AddressMismatch
15
tBLC
BUSY LOW from CE LOW
tBHe
tps
tWB
WE LOW after BUSY LOW
0
tWH
WE HIGH after BUSY HIGH
13
15
25
BUSY HIGH to Data Valid
tBDD
INTERRUPTTIMINGll4J
tINS
INT Set Time
15
25
25
ns
tJNR
INT Reset Time
15
25
25
ns
SEMAPHORETIMING
SEM Flag Update Pulse (OE or SEM)
tsop
SEM Flag Write to Read Time
tSWRD
SEM Flag Contention Window
tsps
Notes:
10. See the last page of this specification for Group A subgroup testing infonnation.
11. Thst conditions assume signal transition time of3 ns or less, timing referencelevelsof1.SV,inputpulselevelsofOto3.0V,andoutputloading
of the specified ImlIoH and 30 pF load capacitance.
10
10
15
ns
5
5
5
5
5
5
ns
ns
12. AC test conditions use VOH = 1.6V and VOL = lAY.
13. Thst conditions used are Load 3.
14. Thst conditions used are Load 2.
2-132
;~PRESS
my
F
CY7B144
CY7B145
PRELIMINARY
SEMICONDUCTOR
*_ •
Switching Waveforms
Read Cycle No. d 19, 20]
---t=_ _ _
~;:V;bXXXX*.-._-_-___-_-_-_-_-_-_-_-_D-A~J_A-_V-A~L_I-D~ ~ ~ ~ ~ ~_
Either Port Address Access
IRC
ADDRESS
DATA OUT
_ _
8144-11
Read Cycle No. 2[17,18, 19]
SEMarCE ~
Either Port CE/OE Access
:;'f
\.
~
I-
lACE
~llZOEIL2CE
DATA OUT
ICC
-
Ipu
..,
IHZOE
IOOE-
'// / / / / / /
-'
DATA VALID
.....""'\c"'-, ~"'-"-,
r-
IHZCE -
-=:i
-
/I
Ipo
ISB~'
Read Timing with Port-to-Port Delay (MIS
=L)[15, 16]
twe
ADDRESSR
)(
),
MATCH
tPWE
~
/
_tso
tHO
VALID
ADDRESSL
MATCH
1000
)E
DATAoUTL
lwoo
-
8144 9
Notes:
15. BUSY = mOH far the writing port.
16. CEL = CER = LOW.
17. Address valid priar to or coincident with CE transition LOW.
18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
19. RiW is mOH for read cycle.
20. Device is continuously selected CE = LOW and OE = LOW. This
waveform cannot be used for semaphore reads.
2-133
&
~~CYPRESS
~, SEMICONDUCTOR
PRELIMINARY
CY7B144
CY7B145
Switching Waveforms (continued)
Write Cycle No.1: OE Three-State Data I/Os (Either Port)[21, 22, 24]
~------------------------twc------------------------~~
ADDRESS
/sCE
____-+______
DATA IN
~--~I~----------tPWE ------------~~
j;::=tso
------------------------------~~
DATA VALID
__________~_____
.1. tHO.?:
~-------------
HIGH IMPEDANCE
8144-12
Write Cycle No.2: RiW Three-State Data I/Os (Either Port)[21, 23, 24]
~------------------twc ------------------------~
ADDRESS
SEMORCE
NW
--------------~~~,
DATA IN
DATA OUT
8144-13
Notes:
21. The internal write tim-",-of the memory is dermed by the overlap ofCE
or SEM LOW aod R/W LOW. Both signals must be LOW to initiate
a write, aod either signal can terminate a write by going mGH. The
data input set-up aod hold timing should be referenced to the rising
edge of the signal that terminates the write.
22. If OE is LOW during a RiW controlled write cycle, the write pulse
width must be the larger of tPWE or (tHZWE + tsD) to allow the I/O
drivers..!Q.turn off and data to ~placed on the bus for the required
tSD. If OE is mGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
23. Data I/O pins enter high impedaoce when OE is held LOW during
write.
24. RiW must be mGH during all address traositions.
2-134
~
~ i~PRESS
PRELIMINARY
~., SEMICONDUCTOR
CY7B144
CY7B145
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[28]
1/0 0
DATA-OUT VALID
8144-15
SemaphoreContention[25, 26, 27]
~L-~L ____________________M_A_rC_H
____________________-J»(~
___________________
MATCH
RIWR
SEMR
-::0
It'
----------------------'
It'
----------------------'
-::0
8144-14
Notes:
25. IIOoR = IIOOL = WW (request semaphore); eER = eEL = mGH
26. Semaphores are reset (available to both ports) at cycle start.
27. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
28. CE = HIGH for the duration of the above timing (both write and read
cycle).
2-135
p~
CY7B144
CY7B145
PRELIMINARY
~=CYPRESS
~, SEMlCONDUCfOR
Switching Waveforms (continued)
Read with BUSY (MIS=IDGH)[16j
Iwe
.IK
.II(
MATCH
tPWE
R/WR
~Ir-
)~
~tso
~~
DATAINR
tps
ADDRESSL
tHO
VALID
I--
)
MATCH
_tBLA
- tBHA
toDD
~
tBOO---ll
)
DATAourL
twoo
~
8144-16
Write Timing with Busy Input (M/S=LOW)
2-136
=.
~
PRELIMINARY
_ - CYPRESS
. , SEMICONDUCTOR
CY7B144
CY7B145
Switching Waveforms (continued)
•
Busy Timing Diagram No.1 (CE Arbitration)[29]
CEL Valid First:
X
ADDRESSL,R
X
ADDRESS MATCH
CER
IBLC~
BUSYR
CER Valid First:
X
ADDRESSL,R
CEL
IBLC
~L
a::
(/)
8144-20
X
ADDRESS MATCH
~"b =t
CER
c:(
t~'1
t~b
CEL
II)
:E
t~~
8144-21
Busy Timing Diagram No.2 (Address Arbitration)[29]
Left Address Valid First:
IRCor Iwc
(
ADDRESSL
)(
ADDRESS MATCH
ADDRESS MISMATCH
_Ips-
~t'
ADDRESSR
~R----1
-
IBLA
__=f----f--
IBHA
•
Right Address Valid First:
8144-18
IRCorlWC
ADDRESSR
~{
ADDRESS MATCH
)(
ADDRESS MISMATCH
_IpsADDRESSL
~t'
f--
IBHA
-----j_-1,--
IBLA
i'
--1
Note:
29, If tps is violated, the busy signal will be asserted on one side or the other, but there is no gnarantee on which side BUSY will be asserted
30. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
8144-19
31. tINS or tJNR depends on which enable pin (CEL or R/WL) is asserted
last.
2-137
~~PRFSS
~_
,
PRELIMINARY
CY7B144
CY7B145
SEMICONDUCIDR
Switching Waveforms (continued)
Interrupt TIming Diagrams
Left Side Sets INTR:
twe
ADDRESSL
INTR
WRlTE1FFF
f
XXXXXXXXXXXXXX
tINS[31]
- - - l " -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Right Side Clears INTR:
ADDRESSR
CER
8144-22
iRc
READ1FFF
.oK
~NR[31]
/
////~
OER
'\.
"""~
f\.
INTR
8144-23
Right Side Sets INTV
1<1------ twe
ADDRESSR
WRITE 1FFE
14---
tINS[31]
----11"-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
-*---
8144-24
Left Side Clears INTL
C
x x x x x x x x x x x x x x f , - - R _ E A _ :_1FF_E
-
K
eEL
R/WL////V
L
~
Oi:
" ' ""
INTL
----------------------------------------'
"
"
2-138
8144-25
~
PRELIMINARY
~ircyPRESS
.
,
CY7B144
CY7B145
SEMICONDUCTOR
Architecture
The CY7B144/5 consists of a an array of 8K words of 8/9 bits each
of du!!!:port ~ cells, 110 and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port.1Wointerrupt (INT) pins can be utilizedforport-to-portcommunication.1Wo semaphore (SEM) cOEtrol pins are used for allocating shared resources. With the MIS pin, the CY7B144/5 can
function as a Master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B144/5 has an automatic power-down
feature controlled by CEo Each port is provided with its own output
enable control (OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
RiW in order to guarantee a valid write. A write operation is con-
trolle2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
- O.5V to + 7.0V
Range
Commercial
Militaryfl]
-O.5Vto +7.0V
- 3.0Vto +7.0V
O°Cto + 70°C
Vee
5V± 10%
- 55°C to + 125°C
5V± 10%
Over the Operating Rangel2]
7C147-25
Parameters
Description
Thst Conditions
VOH
Output High Voltage
VOL
VIR
Output Low Voltage
Input High Voltage
VIL
Input Low Voltage
IIX
Ioz
Input Load Current
Output Leakage
Current
GND.$. VI.$. Vcc
loS
Output Short
CircuitCurrent[3]
Vcc = Max., VOUT = GND
Icc
V cc Operating
Supply Current
VCC=Max.,
lOUT = ornA
AutomaticCEL4J
Power-DownCurrent
Max. Vee,
CE.<::. Vrn
ISB
Vcc= Min.,loH = -4.0rnA
V cc = Min., IOL = 12.0 rnA
Min.
2.4
2.0
7C147-35,45
Min.
2.4
Max.
Units
Max.
V
0.4
0.4
6.0
V
V
2.0
-3.0
6.0
0.8
0.8
V
+10
+50
-10
-50
+10
+50
!lA
!lA
-350
-350
rnA
Com'l
90
80
110
rnA
Mil
Com'l
15
10
rnA
-3.0
-10
-50
GND.$. Vo.$. Vee
Output Disabled
Hi
Mil
Capacitance [5]
Parameters
CIN
CoUT
Description
Thst Conditions
Inputcapacitance
Output Capacitance
TA=25°C,f=1MHz,
Vcc= 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
infonnatiou.
3. Duration of the short circuit should not exceed 30 seconds.
Max.
8
8
Units
pF
pF
A pull·up resistor to V cc on the CE input is required to keep the device deselected during vee power-up, otherwise IsB will exceed values
given.
5. Tested initially and after any design or process changes that may af·
feet these parameters.
4.
2-143
a=~
~=CYPRESS
~.iF'
CY7C147
SEMlCONDUCfOR
AC Test Loads and Waveforms
R13290
5V<>----_.....,
RI329D
5V<>----_....,
--+
FI
30 P
INCLUDING
JIGAND _
OUTPUT<>---......
5PFI
R2
255
o
R2
GND
255
o
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
All INPUT PULSES
3.OV:=?1
--+
OUTPUT < > - - -......
90%
10%
.s,5ns ___
I.-
SCOPE -
(a)
THEvENIN EQUIVALENT
C147-5
(b)
C1474
1250
OUTPUT
OO--~'.",·~...----OO
Switching Characteristics
1.9OV
Over the Operating Rangel:6]
7C147-25
Description
Parameters
Min.
Max.
7C147-35
Mio.
Max.
7C147-45
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
tlZCE
CE LOW to Low Z[7]·
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpD
CE HIOH to Power-Down
35
25
3
45
5
25
5
5
35
5
20
0
5
0
ns
ns
30
0
20
ns
ns
45
30
20
ns
45
35
25
ns
ns
20
ns
WRITECYCLE[91
twc
Write Cycle Time
25
35
45
ns
tsCE
CE LOW to Write End
25
35
45
ns
tAW
Address Set-Up to Write End
25
35
45
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
15
20
25
ns
tHD
Data Hold from Write End
0
10
10
ns
tLZWE
WE HIGH to Low Z[7]
0
tHZWE
WE LOW to High Z[7,8]
0
15
Noles:
6. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 3O-pF load capacitance.
7. At any given temperature and voltage Condition, tHZ is less than tIZ
for all devices.
8. tHZCE and tHzWE are tested with CL = 5 pF as in part (b) of AC Thst
Loads. 1ransition is measured ±500 mV from steady state vQltage.
9.
2-144
0
20
ns
25
ns
The internal write time of the memory is defined by the overlap of CE
WW and WE LOW. Both signals mnst beLOW to intiate a write and
either signal can teminate a write by going fiGH. The data input setup and hold timing shoUld be referenced to the rising edge of the signal that terminates the write:
~
·~PRfSS
CY7C147
.
_ , SEMlCONDUCfOR
Switching Waveforms
Read Cycle No.1[IO, 11]
ADDRESS
~
-----1=
DATA OUT
tRC
tOHA
PREVIOUS DATA VALID
-----------.1*_---
"'~~I-)(--)(~)k~1------------D-A-~-V-A-LlD--------C147-6
Read Cycle No. 2[10, 12]
tRC
~~
jf:
tACE
~
~ tLZCE
YIGH IMPEDANCE
DATA OUT
"/
.'\.
//
'\.'\.
Vee
i~
,
HIGH
IMPEDANCE
I---tpD -
_tpu_
SUPPLY
CURRENT
tHZCE:j
DATA VALID
ICC
50%~
50%
' - - IS8
C147-7
Write Cycle No.1 (WE Controlled) [9]
ADDRESS
twe
-
~(
)(
IsCE
~ ~ l\.
/
W##ffi W///&
tAw
tHA-
tSA
tPWE
~~~
~
tHD ...
Iso
DATA IN
)~
)(
DATA-IN VALID
r-- tHZWE j
-
tLZWE
----j
HIGH IMPEDANCE
DATAOUT _______________
D_A1_A_U_N_D_E_FI_N_ED
______________-J)~----------------«,
_________
C147-8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL-
12. Address valid prior to or coincident with CE transition LOW
2-145
•
j
~~
CY7C147
-'-CYPRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [9, 13]
~-----------------------twc------------------------~
ADDRESS
------1------
tSCE - - - - - -.......-1
tso - - - - - -...
14----1"-----DATA IN
--------------~
DATA·IN VALID
tHZWE
DATA OUT
---I
---------------------------------~~----------H-IG-H--IM-P-E-DA-N-e-E----------DATA UNDEFINED
~
C147-9
Notes:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
'!Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vo. AMBffiNTTEMPERATURE
NORMALIZED SUPPLY CURRENT
vo. SUPPLY VOLTAGE
1.4
1.2
.-'"
!ll1.2
~
Icc
1.0
V
Cl
I!:I
0.8
~
0.6
~
0.4
V
./""
"' 1.0
:::
0
V1N = 5.0V
TA = 25°e
II:
.!:? 0.8
Cl
-
ISB
4.5
5.0
5.5
J
1.3
J
1.2
Cl
~
II:
z
1.0
0
ISB
25
125
AMBIENT TEMPERATURE (Oe)
'"
w
N
f'-..
0.8
4.0
~
f5
TA = 25°e
...............
0.9
5.0
r--
5.5
SUPPLY VOLTAGE M
40
20
0
0.0
6.0
1.0
0.8
!--
I-
./
1.2
1.0
3.0
<-160
1.4
Z
"""'"
2.0
~
-~
./
~
1~
120
!§
100
~
80
Ci5
60
~
'3
o
AMBIENT TEMPERATURE (0C)
2-146
inII:
z
VCC= 5.0V
4.0
OUTPUT VOLTAGE M
.5. 140
0.6
4.5
g
'3
o~
Vcc= 5.0V
TA = 25°e
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.6
Cl
~
:::>
Vcc-5.0V
VIN =5.0V
NORMALIZEDACCESSTDdE
vo. AMBffiNTTEMPERATURE
1.4
""
II:
!§ so
w
M
NORMALIZED ACCESS TIME
vo. SUPPLY VOLTAGE
1.1
!zw 100
~ 60
0.0
-55
6.0
§. 120
OUTPUT SOURCE CURRENT
vo.OUTPUTVOLTAGE
<..l
0.2
SUPPLY VOLTAGE
::J
----......
Z
0.0
4.0
N
Icc
w
N
::J 0.6
«
::;;
II:
0 0.4
0.2
w
l----
_
40
20
o
V
/
)
--
VCC= 5.0V
TA = 25°e
/
/
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE M
4.0
.;jj!-~
~_CYPRESS
CY7C147
~, SEMlCONDUCfOR
'iYpical DC and AC Characteristics (continued)
TYPICALPOWER·ON CURRENT
vs. SUPPLY VOLTAGE (7Cl48)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
.
c
0
30.0
2.5
TA = 25'C
lKQCSPULL-UP
RESISTOR TO Vee
w 2.0
::J
1.5
N
z
-
13
~
II:
0
rn
~
0.5
0.0
0.0
1.0
--
2.0
/'
20.0
~
3.0
SUPPLY VOLTAGE
../
15.0
/
4.0
5.0
c 10.0
5.0
/
1/
200
M
11-
25
35
45
600
BOO 1000
CAPACITANCE (pF)
Package
'JYpe
Operating
Range
CY7C147-25PC
P3
Commercial
CY7C147-25DC
D4
CY7C147-25LC
LSO
Ordering Code
CY7C147-35PC
P3
CY7C147-35DC
D4
CY7C147-35LC
LSO
CY7C147-35DMB
D4
CY7C147-35KMB
K70
CY7C147-35LMB
LSO
CY7C147-45PC
P3
CY7C147-45DC
D4
CY7C147-45LC
LSO
CY7C147-45DMB
D4
CY7C147-45KMB
K70
CY7C147-45LMB
LSO
Commercial
Military
Commercial
Military
2-147
c
w
r-r-1.2
1.3
.J
J
Vee = 5.0V
TA = 25'C
VIN = O.SV
::J
<
::;:
1.1
0
1.0
II:
Vee=4.5V TA = 25'C
400
8
N
"
Ordering Information
Speed
(ns)
-
/
w
ISB
1.0
25.0
NORMALIZED Icc vs. CYCLE TIME
1.4
z
0.9
O.B
V
o
.....10
,/
20
,."
30
-
40
CYCLE FREQUENCY (MHz)
50
CY7C147
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VILMax.
IIX
loz
Icc
ISB
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tOHA
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
tACE
7,8,9,10,11
tRC
tAA
WRITE CYCLE
twc
tSCE
7,8,9,10,11
7,8,9,10,11
tHA
7,8,9,10,11
7,8,9,10,11
tSA
7,8,9,10,11
tpWE
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
tAW
tSD
tHD
Document #: 38-00030-B
2-148
CY7C148
CY7C149
CYPRESS
SEMICONDUCTOR
1024 X 4 Static RAM
Features
Functional Description
• Automatic power-down when deselected (7CI48)
• CMOS for optimum speed/power
• 25-ns access time
• Low active power
- 440 mW (commercial)
- 605 mW (military)
• Low standby power (7CI48)
- 82.5 mW (25-ns version)
- 55 mW (all others)
• 5-volt power supply ± 10% tolerance,
both commercial and military
• TTL-compatible inputs and outputs
The CY7C148 and CY7C149 arehigh-performance CMOS static RAMs organized
as 1024 by 4 bits. Easy memory expansion
is-12!0vided by an active LOW chip select
(CS) input and three-state outputs. The
CY7C148 remains in a low-power mode as
l~ as the device remains unselected; i.e.,
(CS) is HIGH, thus reducing the average
power requirements of the device. The
chip select (CS) of the CY7C149 does not
affectthe power dissipation of the device.
Writingto the device is accomplished when
the chip select (CS) and write enable (WE)
inputs are both LOW. Data on the I/O pins
(1/00 through 1/03) is written into the
Logic Block Diagram
memory locations specified on the address
pins (Ao through A9).
Reading the device is accomplished by
takingc!!!I!..select (CS) LOW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the location
specified on the address pins will appear
on the four data I/O pins.
The I/O pins remain in al!!gh-impedance
state when c~elect (CS) is HIGH or
write enable (WE) is LOW.
Pin Configurations
DIP
Top View
vee
Aa
Aa
A7
'"
Aa
Aa
A,
1/01
Ao
Ao
1/°0
1/00
A2
I/O.
cs
V0 3
WE
GND
1/°1
C148·2
1/°2
Lee
Top View
1/°3
£:'~ct
CS
'"
A'3
A10
A"
A'2
WE
Aa
A,
VOo
vo,
7
1/02
8 91011
C148-1
1~~I~g
C148-3
Selection Guide
Maximum Access Time (ns)
MaximumOperating
Current(mA)
Maximum Standby
Current(mA)
Commercial
7C148-25
7C148-35
7C148-45
7C149-25
7C149-35
7C149-45
25
35
45
25
35
45
90
80
80
90
80
80
110
110
110
110
10
10
10
10
Military
Commercial
Military
15
2-149
•
CY7C148
CY7C149
.:It~ND~
M~imum
Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
not tested.)
Storag~Temperature ................. Ambient Thmperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential
(Pin 18 t() Pin 9) ........................
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
Electrical Characteristics
6S 0 Cto
+1.~O°C
SSOCto +125°C
Output Current into Outputs (Low) ................ 20 rnA
StaticDischargeyoltage........................ >2001V
(per MIL-SID-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
- O.5Vto +7.0V
Range
Commercial
Military£l]
- O.5Vto +7.0V
- 3.0V to + 7.0V
Ambient
Thmperature
O°Cto + 70°C
Vee
SV± 10%
- 55°C to + 125°C
SV ± 10%
Over the Operating Rangel.2]
7Cl4819-2S
Parameters
IOH
IOL
VIH
VIL
IJX
Ioz
lee
ISB
Ipo
los
Description
Thst Conditions
Output High Current
Output Low Current
Input High Voltage
Min.
2.4
Vee = Min., IOH = -4.0 rnA
Input Low Voltage
butput LeakageCurrent
Vee Operating
Supply Current
GND.$.VI.$.Vee
GND.$. Vo.$. Vee Output Disabled
Com'l
Max. Vee,CS.$. VIL
Output Open
Mil
AutomaticCS
Power-Down Current
Max.Vee, CS2 VIH
Peak Power-On
Currentf3]
Max.Vee, CS2Vrn
Output Short
CircuitCurrent[4]
GND.$.Vo5. V
7C148
only
7C148
only
ec
7C14819-3S,45
Min.
Com'l
Mil
Com'l
Mil
Com'l
Max.
Units
2.4
0.4
Vee = Min., IOL = 8.0 rnA
Input Load Current
Max.
2.0
6.0
-3.0
-10
-50
0.8
V
0.4
2.0
-3.0
-10
-50
10
50
90
V
V
6.0
0.8
10
V
50
IlA
IlA
80
rnA
110
10
15
rnA
10
15
10
rnA
10
±275
Mil
±27S
±3S0
rnA
Capacitance [5]
Par~eters
CIN
CoUT
Description
Thst Conditions
ll).putCapacitance
Output Capacitance
TA = 2soC,f= 1 MHz,
Vee=S.OV
Max.
Units
8
pF
8
pF
Notes:
4.
1.
TA is the "instant on" case temperature.
2.
See the last page of this specification for Group A subgroup testing
information.
A pull-up resistor to Vee on the CS input is required to keep the
device deselected during Vee power-up. Otherwise current will exceed values given (CY7C148 only).
3.
5.
2-150
For test purposes, not more than 1 output should be shorted at one
time. Duration of the short circuit should not exceed 30 seconds.
'Iested initially and after any design or process changes that may affect these parameters.
CY7C148
CY7C149
~
=--.~
'IE CYPRESS
iF SEMJCONDUCTOR
AC Test Loads and Waveforms
R1481.il
5V
FI
30 P
INCLUDING
JIGAND _
5V
0-----'_.,
ALL INPUT PULSES
OUTPUTo---"""---i
3.0V
5PFI
R2
255.il
R2
GND
255.il
~ 10ns ___
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
=f1
R1481.il
0-----"'-,
OUTPUTo---..---+
SCOPE -
(a)
THEVENIN EQUIVALENT
10~
I.-
en
~
C148-5
C148-4
(b)
167.il
OUTPUT ()O---".,..'"---.OO l.73V
Switching Characteristics
Over the Operating Rangel2]
7C148-25
7C149-25
Parameters
Description
Min.
Max.
7C148-35
7C149-35
Min.
Max.
7C148-45
7C149-45
Min.
Max.
Units
READ CYCLE
tRC
Address Valid to Address Do Not Care Time
(Read Cycle Time)
tAA
Address Valid to Data Out Valid Delay
(Address Access Time)
tACS!
tACS2
Chip Select LOW to Data Out Valid (7CI480nly)
tACS
Chip Select LOW to Data Out Valid (7C149 only)
tl2[8]
Chip Select LOW to Data Out On
tHZ[8]
Chip Select HIGH to Data Out Off
tOH
Address Unknown to Data Out Unknown Time
tpo
Chip Select IDGH to Power-Down Delay
tpu
Chip Select LOW to Power-Up Delay
25
I 7C148
I 7C149
35
45
ns
25[6]
35
45
ns
30[7]
35
45
ns
15
15
20
10
10
5
0
20
0
20
5
0
20
ns
ns
5
5
15
0
I 7CI48
I 7C148
ns
25
8
0
45
35
30
ns
ns
30
ns
0
0
0
ns
Address Valid to Address Do Not Care
(Write Cycle Time)
25
35
45
ns
twp[9]
Write Enable LOW to Write Enable HIGH
20
30
35
ns
tWR
Address Hold from Write End
5
5
5
ns
tWZ[8]
Write Enable to Output in High Z
0
tow
Data in Valid to Write Enable HIGH
12
20
20
ns
tOH
Data Hold Time
0
0
0
ns
tAS
Address Valid to Write Enable LOW
0
0
0
ns
tCW[9]
Chip Select LOW to Write Enable IDGH
20
30
40
ns
toW[8]
Write Enable HIGH to Output in Low Z
0
0
0
ns
tAW
Address Valid. to End of Write
20
30
35
WRITE CYCLE
twc
I-----H-IG-H-IM-P-E-D-A-N-GE
_ _ _ _ __
DATA UNDEFINED
/
C148-9
Notes:
13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
'JYpical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
./
III 1.2
Icc
jl1.0
V
Cl
w 0.8
~
«
::iii
V
0.6
./'
.,
VIN= 5.0V
TA = 25°G
a:
---
1.2
::: 1.0
-
0 0.4
z
~
3!
!§
5.0
5.5
Vcc= 5.0V
VIN= 5.0V
ISB
1.4
1.3
J.1.4
w
N
::l
~
a:
1.1
z
1.0
0
"-
"'-
4.5
--
5.0
~
TA = 25°G
20
0
0.0
0
5.5
SUPPLY VOLTAGE (V)
6.0
z
0.8
0.6
-55
1.0
2.0
'"
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
.§. 120
/
1.2
a: 1.0
!---
.....
40
VCC= 5.0V
TA = 25°G
«'140
Cl
0.9
0.8
4.0
25
125
AMBIENT TEMPERATURE (oG)
g
5
o~
vs. AMBIENT TEMPERATURE
1.6
Cl 1.2
80
NO~ZEDACCESST~
NO~ZEDACCESS~E
vs. SUPPLY VOLTAGE
" '"" "-
a:
a:
i3
::l
0.4
0.0
-55
6.0
......
~ 60
SUPPLY VOLTAGE (V)
J.
~
!zw 100
0.6
0.2
4.5
Icc
w
ISB
0.0
4.0
l120
~
8 0.8
z
0.2
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
vs. AMBIENT TEMPERATURE
vo. SUPPLY VOLTAGE
1.4
./
1/
!zw
/
~
i3
l<:
Vcc= 5.0V
25
125
AMBIENT TEMPERATURE (oG)
2-153
100
... V
80
Z
iii
60
5
~
o
40
20
oV
0.0
/
I-Vcc= 5.0V
TA = 25°C
I
/
I
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C148
CY7C149
&;nPRESS
~
SEMICONDUCIDR
'lYPical DC and AC Characteristics
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE (7Cl48)
TYPICAL ACCESS TllWE CIIANGE
vs.OUTPUTWADlNG
3.0
0
2 .5
~
~
a:
g
TA = 25°C
1K Q CS PULL-UP
RESISTOR TO Vee
~
cw
2.0
1.5
:!
20.0
13
15.0
C
0.5
./
V
1.0
25.0
/
/
w
ISB
0 1.0
z
0.0
0.0
-
30.0
- '3.0
2.0
4.0
5.0
10.0
5.0
V
V
/
200
SUPPLY VOLTAGE (V)
,-
Vee=4.5V TA = 25°C
,
400
600
800 1000
NORMALIZED Icc vs. ACCESS TIME
1.4
u
1.3
cw
1.2
.2
~
«
:;
1.1
0
1.0
a:
Z
'"
f'....
0.9
0.8
10
~
30
40
50
00
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
Ordering Information
Speed
(ns)
25
35
45
Ordering Code
CY7C148-25PC
CY7C148-25DC
CY7C148-25LC
CY7C148-35PC
CY7C148-35DC
CY7C148-35LC
CY7C148-35DMB
CY7C148-35KMB
CY7C148-35LMB
CY7C148-45PC
CY7C148-45DC
CY7C148-45LC
CY7C148-45DMB
CY7Cl48-45KMB
CY7C148-45LMB
Package
lYPe
P3
Operating
Range
Speed
(ns)
Commercial
25
Commercial
35
D4
LSO
P3
D4
LSO
D4
K70
Military
LSO
P3
D4
Commercial
45
LSO
D4
K70
Military
LSO
2-154
Package
Ordering Code
1YPe
CY7C149-25PC
CY7C149-25DC
CY7C149-25LC
CY7C149-35PC
CY7C149-35DC
CY7C149-35LC
CY7C149-35DMB
CY7C149-35KMB
CY7C149-35LMB
CY7C149-45PC
CY7C149-45DC
CY7C149-45LC
CY7C149-45DMB
CY7C149-45KMB
CY7C149-45LMB
P3
D4
L50
P3
D4
Operating
Range
Commercial
Commercial
LSO
D4
K70
Military
LSO
P3
D4
Commercial
LSO
D4
K70
LSO
Military
CY7C148
CY7C149
~~PRFSS
~,
SEMICONDUCfOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
IOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IOL
VIR
VILMax.
IIX
Ioz
Icc
ISB[14]
Parameters
Subgroups
READ CYCLE
tRC
tAA
tACS1[14]
tACS2[14]
tACS[15]
tOH
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9,10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
WRITE CYCLE
Document #: 38-00031- B
twc
twp
tWR
tDW
tDH
tAS
tAW
Notes:
14. 7C148 only.
15. 7C149 only.
2-155
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
CY7C150
CYPRESS
SEMICONDUCTOR
1024 X 4 Static RIW RAM
Features
Functional Description
• Memory reset function
• 1024 x 4 static RAM for control store
in high-speed computers
• CMOS for optimum speed/power
The CY7C150 is a high-perfonnance
CMOS static RAM designed for use in
cache memory, high-speed graphics, and
data-acquisition
applications.
The
CY7C150 has a memory reset feature that
allows the entire memory to be reset in two
memory cycles.
Separate I/O paths eliminates the need to
multiplex data in and data out, providing
for simpler board layout and faster system
performance.Outputs are tri-stated during
write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy
memoryexpansion.
Reset is initiated by selecting the device
(CS = WW) and taking the reset (RS) input Ww. Within two memory cycles all
bits are internally cleared to zero. Since
chip select must be LOW for the device to
be reset, a global reset signal can be em-
• Highspeed
-10 ns (commercial)
-12 ns (military)
• Lowpower
-495 mW (commercial)
-550 mW (military)
• Separate inputs and outputs
• 5-volt power supply :1:10% tolerance
in both commercial and military
• Capable of withstanding greater than
2001V static discharge
• TIL-compatible inputs and outputs
Logic Block Diagram
ployed, with only selected devices being
cleared at any given time.
Writingtothe device is accomplishedwhen
the chip select (CS) and write enable (WE)
inputs are both Ww. Data on the four
data inputs (Do-D3) is written into the
memory location specified on the address
pins (Ao through A9).
Readingthe device is accomplished by taki~chip select (CS) and output enable
(OE) LOW while write enable (WE) remains HIGH. Under these conditions, the
contents of the memory location specified
on the address pins will appear on the four
output pins (00 through 03).
Theoutputpinsremaininhigh-impedance
state when chip enable (CE) or output enable (~HIGH, or write enable (WE)
or reset (RS) is LOW.
A die coat is used to insure alpha inununity.
Pin Configurations
"RS
WE
Ao
1
~
cs
As
As
Do
0,
O2
00
WE
OE
D.
D.
0,
GND
.uSi~~
Vee
Ao
AS
A7
0,
Top View
A2
A,
A,;
A,;
00
Lee
DIP
Top View
~
Os
Os
A,;
A,;
A7
As
NC
As
Do
0,
00
4
5
6
7
8
9
10
11
12
32~,2827
7C150
26
25
24
23
22
21
A,
Ao
AS
cs
NC
WE
20
OE
19
18
1314151617
OS
00
D.
l.) CIoIC')
~zoo
03
C150-3
C150-2
C150·1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
7C150-10
7C150-12
7C150-15
7C150-25
7C150-35
10
12
12
15
25
35
15
25
35
90
90
90
90
100
100
100
100
Military
Commercial
90
Military
2-156
-.- -----=-
;~
CY7C150
~=CYPRF.SS
~_'J SEMICONDUC'TOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (Low) ................ 20 rnA
Electrical Characteristics
Parameters
Operating Range
Range
Commercial
Military(1]
Ambient
Thmperature
O°Cto + 70°C
Vee
5V ± 10%
- 55°Cto + 125°C
5V ± 10%
Over the Operating Rangel2]
7C150
Min.
Max.
Thst Conditions
Description
VOH
VOL
VIH
VjL
Static Discharge Voltage ....................... . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ........................... . >200 rnA
Output HIGH Voltage
Vee = Min., IOH = - 0.4 rnA
Output LOW Current
Input HIGH Level
Vee = Min., IOL = 12 rnA
V
V
0.4
2.0
lJX
Input LOW Level
Input Load Current
-3.0
-10
loz
Output Current (High Z)
VOL.s VOUT.s VOH,
Output Disabled
los
Icc
Output Short Circuit Current[3]
Vee = Max., VOUT = GND
I Commercial
Vee = Max.,
lOUT = ornA
I Military
GND.s Vj.s Vee
Vee Operating Supply Current
Units
2.4
-50
Vee
0.8
V
+10
t-tA
V
+50
t-tA
-300
rnA
90
100
rnA
rnA
Capacitancd4]
Parameters
CIN
COUT
Deseription
Thst Conditions
Max.
Units
InputCapacitance
Output Capacitance
TA = 25°C,f= 1 MHz,
10
pF
Vee=S.OV
10
pF
AC Test Loads and Waveforms
R13290
5Vo----_"....,
R13290
5Vo_---_"....,
OUTPUTo---....-~
30pF
I
INCLUDING
JIG AND -
=
SCOPE -
5pF
3.0V
R2
I
----,111""::::::"----.....
2020
GND
INCLUDING
JIGAND _
=
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
O~P~O---....-~
R2
2020
(b)
C15(}4
--
C1S(H)
THEVENIN EQUIVALENT
1250
OUTPUT 00----".,.._._--.00 1.9V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than 1 output should be shorted at a time. Duration of the
short circoit should not exceed 30 seconds.
4.
5.
2-157
Tested initially and after any desigo or process changes that may affect
these parameters.
Thst conditions assume sigoal transition times of 5 ns or less, timing referenece levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lorJIoH and 30-pF load capacitance.
.il~NDU~
Switching Characteristics
CY7C150
Over the Operating Rangel2, 5]
7C150-10
Parameters
Description
READ CYCLE
Read Cycle Time
tRC
7C150-12
Min. Max. Min.
12
10
7C150-15
Max. Min.
Max.
7C150-25
25
15
7C150-35
Min. Max. Min.
Max. Units
35
25
ns
ns
tAA
Address to Data Valid
tORA
OutputHoldfromAddressChange
tACS
tLZCS
CS LOW to Data Valid
CS LOW to Low ZLbJ
tHZCS
CS HIGH to High ZL6, IJ
6
8
11
20
25
ns
tDOE
OE LOW to Data Valid
6
8
10
15
20
ns
tLZOE
OE LOW to Low ZL6J
25
ns
12
10
2
2
8
2
0
0
0
0
20
ns
ns
0
0
9
8
6
ns
20
15
0
0
0
35
2
2
12
10
0
OE HIGH to High ZL~,/J
tHZOE
WRITECYCLEl8J
15
ns
twc
Write Cycle Time
10
12
15
25
35
tscs
CS LOW to Write End
6
8
11
15
20
ns
tAW
Address Set-Up to Write End
8
10
13
20
30
ns
tHA
Address Hold from Write End
2
2
2
5
5
ns
tSA
Address Set-up to Write Start
2
2
2
5
5
ns
tpWE
WE Pulse Width
6
8
11
15
20
ns
tSD
Data Set-up to Write End
6
8
11
15
20
ns
tHD
Data Hold from Write End
2
2
2
5
5
hs
tLZWE
WE HIGH to LOWZLbJ
0
0
0
0
0
WE LOW to HighZL6, 7J
tHZWE
RESET CYCLE
6
ns
25
20
12
8
ns
lIS
tRRC
Reset Cycle Time
20
24
30
50
70
ns
tSAR
Address Valid to Beginning of
Reset
0
0
0
0
0
ns
tSWER
Write Enable HIGH to Beginning
of Reset
0
0
0
0
0
ns
tSCSR
Chip Select LOW to Beginning of
Reset
0
0
0
0
0
ns
tpRS
Reset Pulse Width
10
12
15
20
30
ns
tHCSR
Chip Select Hold After End of
Reset
0
0
0
0
0
ns
tHWER
Write Enable Hold After End of
Reset
8
12
15
30
40
ns
tBAR
Address Hold After End of Reset
10
12
15
30
40
ns
tLZRS
Reset HIGH to'Output in LowZ LbJ
0
0
0
0
0
ns
tHzRS
Reset LOW to Output in
Highz[6,7]
8
6
Notes:
6. At any given temperature and voltage condition, tHZ is less than tufor
any given device.
7. tHZCS, tHZClE. t!fZR, and tHzWE are tested with CL = 5 pF as in part
(b) of AC Thst Loads. 'fransition is measured ±SOO mV from steady
state voltage.
8.
2-158
12
20
25
ns
The internal write time of the memory is defIned by the overlap of CS
WW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be reference to the rising edge of the signal
that terminates the write.
.....::=lIlIIII
1s r.~NDUODR
CY7C150
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC
~~
ADDRESS
(
tM
-tDHA~
DATA OUT
*XX~ (
PREVIOUS DATA VALID
DATA VALID
C150-6
Read Cycle No. 2[10, 11]
tRC
~I\..
)~
tACS
*'
",,HIGH IMPEDANCE
DATA OUT
tLZCS
tHZDE I--- tHZCS -
I
loDE
-tLZDE-
'///
,"'
DATA VALID
'"''''''
HIGH
IMPEDANCE
Cl50-7
Write Cycle No.1 (WE Controlled)[8]
twe
ADDRESS ~~
-
(
tscs
~~ ~ ~
./ W////~ W//////
tAW
tHA-
!sA
tPWE
~~~
~".
tHD ...
tSD
)(
DATA IN
I---ItiZWE
DATA 1/0
)(
DATA-IN VALID
j
I--
tLZWE
HIGH IMPEDANCE
--J
------------------------}----------« ~----DATA UNDEFINED
Cl50-8
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS and OE = VJL.
11. Address prior to or coincident with CS transition LOW.
2-159
CY7C150
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[8, 12]
ADDRESS
-----0j4----- tscs
1--+----DATA IN --------------------~
Iso
----I
------<....
DATA-IN VALID
tHZWE
--I
--'" I
HIGH IMPEDANCE
--')>--------------
DATA I/O _ _ _ _ _ _ _ _
DA_T_A_U_N_D_E_FI_N_ED
_______
C150-9
Reset Cycle[13]
~------- tRRC
-------------.j
ADDRESS
tsAR
1+----
DATAI/O
HIGH
IMPEDANCE
tHAR
-----I
OUTPUT VALID ZERO
C150-10
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a highimpedance state.
13. Reset cycle is defined by the overlap of RS andCS for the minimum reset pulse width.
2-160
---
-.
~
~iECYPRESS
_
F
CY7ClSO
SEMICONDUCTOR
'iYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORNUUUZEDSUPPLYCURRENT
SUPPLY VOLTAGE
VS.
1.4
ID
en
1.2
Icc
J3 1.0
V
c
w O.S
N
::J
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature[2]
Vee
O°Cto + 70°C
5V ± 10%
- 55°Cto + 125°C
5V± 10%
Range
Commercial
Military
Electrical Characteristics[3] Over the Operating Range
7BI53-15,20
7B154-15,20
7B153-12
7B154-12
Parameters
VOH
VOL
Vru
VIL
Ilx
Ioz
los
Description
Min.
Thst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel1]
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[4]
Max.
Min.
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
0.4
2.2
-0.3
-10
-10
GND < VI 5 Vee
GND5 VI5 Vee,
Output Disab!ed
Vee = Max., VOUT = GND
Max.
Units
2.4
V
V
V
V
0.4
2.2
-0.3
-10
-10
Vee
0.8
+10
+10
Vee
0.8
+10
+10
~
~
-300
-300
rnA
Icc
Vee Operating
Supply Current
Vee = Max., lOUT = ornA,
f = fMAX = lItRe
Com'l
Mil
135
135
145
rnA
ISB!
AutomaticCE
Power-Down Current
-TIL Inputs
Max. V CD CE1,2,3 ~ Vru,
CE4,S 5 VIL VIN ~ Vru or
VIN 5 VIlA f = fMAX
Com'l
50
50
rnA
Mil
AutomaticCE
Power-DownCurrent
-CMOS Inputs
Max. Vee, CE1,2,3 ~ Vee - 0.3v,
CE4,S50.3V, VIN ~ Vee - O.3V
orVIN 50.3V,f = 0
ISB2
Com'!
60
30
30
rnA
40
Mil
Capacitance[S]
Parameters
Description
qN
InputCapacitance
CoUT
OutputCapacitance
Thst Conditions
TA=25°C,f=1MHz,
Vee = 5.0V
Notes:
1. VIL(min.) = - 2.0V for pulse durations oflcss than W ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
information.
4.
Max.
Units
10
pF
10
pF
Not more than I output should he shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
2-165
•
CY7B153
CY7B154
ADVANCED INFORMATION
AC Test Loads and Waveforms
0------__.,
5VC>---~w..,
OUTPUTo---1r--"
OUTPUTC>---r--"
5V
Rl4810
FI
20 P
INCLUDING
JIGAND _
Rl4810
5PFI
R2
2550
R2
GND
2550
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.OV ----...J~~---~
(b)
THEvENIN EQUIVALENT
8153-7
8153-6
1670
OUTPUT O().--_'V','\/\,'_---OO 1.73V
Switching Characteristics[3,6] Over the Operating Range
7BlS3-12
7BlS4-12
Parameters
Min,
Description
Max.
7BlS3-1S
7BlS4-lS
Min.
Max.
7BlS3-20
7BlS3-20
Min.
Max.
Units
READ CYCLE
tRe
Read Cycle Time
tM
Address to Data Valid
12
15
12
3
20
3
ns
20
15
ns
ns
3
tOHA
Data Hold from AddressChange
tACE
CEl,2,3 LOW and CE4,S HIGH to Data Valid
12
15
20
ns
tOOE
OE LOW to Data Valid
7
10
12
ns
trzOE
OE LOW to Low Z[7]
tHZOE
OE HIGH to High Z[7, 8]
trzCE
CEl,2,3 LOW and CB4,s HIGH to Low Z[7]
tHzCE
CE1,2,3, HIGH or CE4,S LOW to High Z[7,8]
7
8
10
ns
tpu
CE1,2,3 LOW and CE4,S HIGH to Power-Up
0
0
0
ns
tpo
CE1,2,3,HIGHorCE4,sLOWtoPower-Down
12
15
20
ns
2
2
7
3
ns
2
10
8
3
3
ris
ns
WRITE CYCLElY,lUJ
twe
Write Cycle Time
12
15
20
ns
tsCE
CEl,2,3 LOW and CB4,s HIGH to Write End
9
10
15
ns
tAW
Address Set-Up to Write End
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
9
10
15
ns
tso
Data Set-Up to Write End
7
8
10
ns
tHO
Data Hold from Write End
0
0
0
ns
trzWE
WE HIGH to Low Z[7]
2
2
2
tHzWE
WE LOW to High z[7,8]
7
Notes:
6. Thstconditions assume signal transition timeof3 ns or less, timing ref. erence levels of l.Sv, input pulse levels of 0 to 3.0V, and output loading of the specified IOu'lOH and 2O-pF load capacitance.
7. tHroE. 4izcE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC Thst Loads. 1tansition is measured ±SOO m V
from steady state voltage.
8. At any given temperature and voltage condition, IHzCE is less than
trzCE, IHWE is less than tIZOE, and tHZWE is less than taWE for any
given device.
7
ns
10
ns
The internal write time of the memory is defined bY the overlap of
CE1,2,3 Law, CE4,S mOH, and WE Law. All signals must be appropriately set to initiate a write and any of these signals can terminate a
write. The input data set-up and hold timing should be referenced to
the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
OE LOW) is the sum oftHZWE and tSD.
9.
2-166
~~
~=CYPRESS
CY7B153
CY7B154
ADVANCED INFORMATION
~, SEMICONDUCTOR
Switching Waveforms
Read Cycle No.
tP 1,12]
~
ADDRESS
IRC
--~
DATA OUT
PREVIOUS DATA
1M
V:~~ -=-*XX
1
*===============D=A=T=A=V=AL=I=D==========
B153-8
Read Cycle No.2 (OE Controlled) [12, 13]
ADDRESS
y
)K
IRC
---...~
C~,5
)?
-../~
)~
),
lACE
)'Il'
IHZOE
IOOE
~ IHZCE-
- - I[zOE---
DATA OUT
HIGH IMPEDANCE
..
_Ipu
=t
DATA VALID
.. 1'-"""
I[zCE
VCC
SUPPLY
CURRENT - - - - - -
I///LL
~Ipo
50%
HIGH
IMPEDAN CE
~ ICC
50%
ISB
B153-10
Write Cycle No.1 (CEb CE2. CE:J. CE4. or CEs ControlIed)[14,15]
~------------IWC ------------~~
ADDRESS
CE1,2,3
---+------------"' ..,>----
ISCE
----t
.,-----t-----
1------ lSA -------1.,_______,
ISCE
CE4,5
lAW
IPWE
WE
Iso
DATAI/O
K
DATA VALID
Notes:
11. Device is continuously selected. OE, CEl,2,3 = VIL C~,5 = Vrn.
12. WE is mGH for read cycle.
13. Address valid prior to or coincident with CEI 2 3 transition LOW and
~,5 transition mGH.
' ,
14. Datal/a is high impedance ifOE = Vrn.
15. If any of CEl,2,3 go mGH or ~,5 goes LOW simultaneously with
WE mGH, the output remains in a high-impedance state.
2-167
ADVANCED INFORMATION
CY7B153
CY7B154
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE IDGH During Write)[14,15]
~----------------------twc----------------------~
ADDRESS
WE
----------~~--~~~,
~-----t~------~~
,----------------
r;::::::::~t~so~::::::::~::~tHo
DATAI/O
DATAVAUD
8153-11
Write Cycle No.3 (WE Controlled, OE LOW)[lO,15]
ADDRESS
WE
----------""'t"t~~
~---------t~E------------~
1+------ Iso
DATA 1/0
.----------------
------+--~
DATA VALID
8153-12
2-168
CY7B153
CY7B154
ADVANCED INFORMATION
CY7B153 Truth Table
CEI
CE2
CE4
CEs
OE
WE
H
X
X
X
X
X
1/00 - 1/03
HighZ
Power-Down
Standby (Iss)
Mode
Power
X
H
X
X
X
X
HighZ
Power-Down
Standby (Iss)
X
X
L
X
X
X
HighZ
Power-Down
Standby (Iss)
X
X
X
L
X
X
HighZ
Power-Down
Standby (Iss)
L
L
H
H
L
H
Data Out
Read
Active (Icd
a::
L
H
H
X
L
Data In
Write
Active (Icd
L
L
H
H
H
H
HighZ
Selected
Active (Icd
1/00 - 1/03
HighZ
Power-Down
Standby (Iss)
CY7B154 Truth Table
CE2
CE3
CE4
OE
WE
H
X
X
X
X
X
Mode
Power
X
H
X
X
X
X
HighZ
Power-Down
Standby (Iss)
X
X
H
X
X
X
HighZ
Power-Down
Standby (Iss) .
X
X
X
L
X
X
HighZ
Power-Down
Standby (Iss)
L
L
L
H
L
H
Data Out
Read
Active (Icd
L
L
L
H
X
L
Data In
Write
Active (Icd
L
L
L
H
H
H
HighZ
Selected
Active (Icd
Ordering Information
Speed
(ns)
12
15
20
Ordering Code
CY7Bl54-12PC
Package
lYPe
P21
D22
CY7B154-12DC
D22
CY7B153-12LC
L55
CY7B154-12LC
L55
CY7B153-12VC
V21
CY7B154-12VC
V21
Ordering Code
CY7B153-12PC
Package
lYPe
P21
CY7B153-12DC
Operating
Range
Commercial
Speed
(ns)
12
CY7B153 -15PC
P21
CY7B154-15PC
P21
CY7B153-15DC
D22
CY7B154-15DC
D22
CY7B153-15LC
L55
CY7B154-15LC
L55
CY7B153-15VC
V21
CY7B154-15VC
V21
CY7B153-15DMB
D22
CY7B154-15DMB
D22
CY7B153-15LMB
L55
CY7B154-15LMB
L55
15
Commercial
Military
CY7B153-20PC
P21
CY7Bl54-20PC
P21
CY7B153-20DC
D22
CY7B154-20DC
D22
Commercial
20
CY7B153-20LC
L55
CY7B154-20LC
L55
CY7B153-20VC
V21
CY7B154-20VC
V21
CY7B153-20DMB
D22
CY7BI54-20DMB
D22
CY7BI53-20LMB
L55
CY7BI54-20LMB
L55
Military
2-169
I/)
::::E
,
Voso
Vsso
36
VO.
35
Vsso
34
Vsso
21 22 23 24 25 26 27 28 29 30 31 32 33
~
Ii >o>u
8 8 I~ >iii >iii >iii d >(»o
8 8 Ii ~
C157-2
Selection Guide
Maximum Clock to Output (ns)
Maximum Output Enable to Output
Time (ns)
Maximum Current (rnA)
7C157A-18
7C157A-20
7C157A 24
7C157A-33
18
20
7
8
24
24
10
350
325
10
300
33
33
15
15
250
325
275
Commercial
Military
Commercial
Military
Commercial
Military
Maximum Ratings
(Above which the useful life may be impaired_ Foruserguidelines,
not tested_)
Storage Temperature ___________________ -65°Cto +150°C
Ambient Temperature with
PowerApplied ______ : _________________ -55°Cto +125°C
Static Discharge Voltage ________________________ >2001V
(per MIL--STD-883, Method 3015)
Latch-UpCurrent ____ ____________________ ___ >200rnA
Operating Range
Supply Voltage to Ground PotentiaL ________ -O.5Vto +7_0V
Range
Commercial
DC Voltage Applied to Outputs
inHighZState _________________________ -O.5Vto +7_0V
DC Input Voltage!l] _____________________ -O.5Vto +7_0V
Military!2]
Ambient
Thmperatnre
O°Cto +70°C
Vee
5V± 10%
- 55°Cto +125°C
5V ± 10%
Output Current into Outputs (LOW) _______________ 50 rnA
Note.:
1_
VIL (min_) = - 3_0V for pulse durations ofless than 20 ns_
2. TA is the "instant on" case temperature
2-172
-,.,K.
'g
--=-.:
CY7C157A
CYPRESS
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range[3]
Parameters
Description
Test Conditions
Output HIGH
Voltage
Vee = Min" IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltagefl]
IIX
Input Load Current
GND~VI~Vee
loz
Output Leakage
Current
GND ~ Vo ~ Vee, Output Disabled
los
Output Short
CircuitCurrentl4]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max., lOUT = 0 rnA
VOH
7C157A-18
7C157A-20
Min.
Min.
Max.
2.4
Units
V
0.4
0.4
V
Vee
V
Vee
2.2
-0.3
0,8
-0.3
0.8
V
-10
+10
-10
+10
f-IA
-10
+10
-10
+10
f.IA
-350
-350
rnA
350
325
rnA
2.2
I Corn'I
I Mil
Description
lest Conditions
Min.
VOH
Output HIGH
Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = KOrnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
GND~VI~Vee
loz
Output Leakage
Current
GND ~ Vo ~ Vee, Output Disabled
los
Output Short
CircuitCurrent[4]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee =Max., lOUT =
Max.
2.4
7C157A-33
Min.
Max.
Units
2.4
0.4
2.2
ornA
V
0.4
V
Vee
V
Vee
2.2
-0.3
0.8
-0.3
0.8
V
-10
+10
-10
+10
-10
+10
-10
+10
f.IA
f.IA
-350
-350
rnA
I Corn' I
300
250
rnA
LMil
325
275
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
lest Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
3. See the last page ofthis specification for Group A subgroup testing information.
4. Not more than 1 output should be shorted at a time. Duration of the
short circuit should not exceed 30 seconds,
5,
2-173
•
I I)
::!!:
7C157A-24
Parameters
Max.
2.4
Max.
Units
5
pF
8
pF
Testcd initially and after any design or process changes that may affect
these parameters.
<
II:
(J)
.il~CWUcroR
CY7C157A
AC Test Loads and Waveforms
4810
4810
OUTP:~ ~
._~~:Fl~ -=
1
INCLUDING
JIG AND
SCOPE
2550
OUTP:~ ~
~:Fl~ -=
90%
1
._ ..
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
3.0V---
(b)
GND
2550
C157-3
C157-4
THEVENIN EQUIVALENT
1670
OUTPUT
o-----wv-----o 1.73V
Switching Characteristics
Over the Operating Rangel6]
7C157A-18
Parameters
Description
Min.
Max.
7C157A-20
Min.
Max.
7C157A-24
Min.
Max.
7C157A-33
Min.
Max.
Units
READ CYCLE[7,8]
tCHCH
Clock Cycle Time
22
25
30
40
ns
tCH
Clock HIGH Time
10
11
13
18
ns
teL
Cjock LOW Time
10
11
13
18
tCHQV
Clock HIGH to Output Valid
tCHQX
Output Data Hold
5
2
18
24
20
5
5
ns
33
5
ns
ns
tWHCH
WE" HIGH to Next Clock HIGH
laLQV
OE LOW to Output Valid
7
8
10
15
ns
tGHQZ
OE HIGH to Output Thstatel9]
7
8
10
15
ns
tGHCH
OE HIGH to Next Clock HIGH
7
7
7
7
ns
tAVCH
AddressSet-Up
2
2
2
3
ns
tCHAX
Address Hold
5
6
6
6
ns
2
2
3
ns
WRITE CYCLEll(}]
ImCH
Clock Cycle Timelll ]
22
25
30
40
ns
1m
Clock HIGH Time
10
11
13
18
ns
teL
Clock LOW Time
10
tGHQZ
OE HIGlf to Output Thstatel9]
tGUCH
OE HIGH to Next Clock HIGH
7
7
11
7
18
13
10
8
ns
15
ns
7
7
ns
toVCL
Data in Set-Up to Clock
5
6
6
7
ns
iCLox
Data in Hold from Clock
2
2
2
2
ns
tWLCL
2
2
2
3
ns
tCLWH
WE" LOW to Clock LOW[12,13]
Clock LOW to WE" HIGW12,13]
4
6
6
7
ns
tAvCH
AddressSet-Up
2
2
2
3
ns
ICHAX
Address Hold
5
6
6
6
ns
2-174
~~
_'a
"'=!!!!!!!!!!:"
CY7C157A
CYPRF.SS
SEMICONDUCTOR
Switching Waveforms
Read Cycle
CLOCK
ADDRESS
Q(N+1)
C157-5
Write Cycle
C157-6
Notes:
6. Thst conditions assume signal transition times of 5 ns or less, timimg
reference levels of 1.5 V, inputpulselevelsofO to 3.0V, and output loading of the specified IOrJIOH and 75-pF load capacitance.
7. WE is IDGH forread cycle.
8. OE is selected (LOW).
9. At any giveu temperature and voltage condition, tGHQZ is less than
tGl.QV for any given device.
10. OE must be IDGH for data-in to propagate to latch.
11. tGHqzis testedwilhCL = 5pFasinpart (b) ofAC Test Loads. Transition IS measured ± 500mV from steady-state voltage.
12. Self-timed write is triggered on falling edge of registered WE{) or WEI
signals.
13. X = 0 or 1 for low byte and high byte, respectively.
2-175
=~PRF.SS
CY7C157A
~, ~CONDUClDR
Truth Table
OE
\¥Eo
L
Operation
WEI
Inputs/Outputs
L
L
Invalid
Invalid
L
L
H
Invalid
Invalid
L
H
L
Invalid
Invalid
L
H
H
Read
Data Out (IIOo - II01S)
H
L
L
Write
Data In (IIOo - 1/015)
H
L
H
Low Byte Write
Data In (IIOo - II07)
H
H
L
High Byte Write
Data In (IIOg - II01S)
H
H
H
Disabled
HighZ
Ordering Information
Ordering Code
'!YPe
Operating
Range
CY7C157A-18LC
L69
Commercial
CY7C157A-18JC
J69
CY7C157A-20LC
L69
CY7C157A-20JC
J69
CY7C157A-24LC
L69
CY7C157A-24JC
J69
Speed
(ns)
18
20
24
33
Package
CY7C157A-24LMB
L69
CY7C157A-24YMB
Y59
CY7C157A-33LC
L69
CY7C157A-33JC
J69
CY7C157A-33LMB
L69
CY7C157A-33YMB
Y59
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
los
Icc
1,2,3
Commercial
Commercial
Military
Commercial
Military
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tCHCH
tCHQV
tGHQZ
tCHQX
tGHQV
WRITE CYCLE
trnCH
tOVCL
tAVCH
1,2,3
1,2,3
tcHAX
tCLDX
tovWL
tWLDX
7,8,9,10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
Document#: 38-R-10007-C
2-176
CY7B158
ADVANCED INFORMATION
CYPRESS
SEMICONDUCTOR
Features
• 64Kx4
• Separate I/O
• Fully registered
-Address
-Data in
-Data out
-CE,WE
• Asynchronous output enable
• Self-timed write
• Transparent write and write passthrough features
• 167-MHz operation
- 2 ns set-up time
-6 ns cycle time
- 5 ns c1oc1t to output
• 44-pin package
-PLCC,SOJ
• TTL-compatible inputs and outputs
Functional Description
The CY7B158 is a fully registered (pipelined) high-performance BiCMOS static
Self-Timed Pipelined
Static RAM
RAM orgatrized to be 65,536 words by 4
bits. Memory expansion is easily accomplished using the active LOW chip enable
(CE) input. An asynchronous output enable signal (OE) is provided to control the
three-state data outputs. Pipelined RAMs
are used in writable control store, DSp,
data acquisition, and graphics applications
where cycle time and throughput are the
critical parameters. The CY7B158can also
be used in cache applications that utilize
separate input and output buses.
ReadlWrite Operation
The operation of these devices is complet~synchronous with the exception of
the OE signal. All data, address, and control signals are sampled on each LOW-toHIGH transition of the clock. When the
is LOW during this transition, the device is selected for operation. The type of
~ation is determined by the state of the
WE signal during the same transition.
LOW causes a write operation while
HIGH causes a read operation. The data
input and data output as well as the address register are also loaded on each
rn
wn
wn
LOW-to-HIGH transition of the clock.
The outputs, however, are not enabled for
the address loaded on the current cycle.
The state of the outputs are controlled by
the pipelined
and WE data from the
previous cycle and the state of the UE signal. The data loaded into the output register is also from the previous cycle and is in
phase with the output control information.
This feature causes a single-cycle latency
for the frrstread or write cycle, but allows a
word of data to be read or written every 6
nanoseconds. The transparent write feature of the CY7B158 causes written data
to pass through to the output register on
the next cycle.
rn
Write-Through Operation
A third mode, called write-through, is possible when
is HIGH and
is LOW.
It will pass the data from the input register
to the output register without changing the
memory array. The data can then be accessed from the outputs if rrn is LOW.
Thisfeatureprovidesaneasy-to-usebuffer
between the input data bus and the output
data bus.
rn
wn
Logic Block Diagram
elK
C::>--+-I DATA 1---------..----,
IN
RAM
ARRAY
64Kx4
DATA
OUT
>---<::::1
000
-
003
8158-1
Document #: 38-00191
2-177
CY7B159
ADVANCED INFORMATION
CYPRESS
SEMICONDUcrOR
Features
• 32Kx8
• Separate I/O
• Fully registered
-Address
-Data In
-Data out
-CE,WE
• Asynchronous output enable
• Self-timed write
• 'fi'ansparent Write and write passtbrougb features
• 167-MHz operation
-2 ns set-up time
- 6 ns cycle time
- 5 ns clock to output
• 44-pin package
-PLCC,SOJ
• TTL-compatible Inputs and outputs
Functional Description
The CY7B159 is a fully registered (pipelined) high-performance BiCMOS static
Self-Timed Pipelined
Static RAM
RAM organized to be 32,768 words by 8
bits. Memo!), expansion is easily accomplished using the active LOW chip enable
(CE) input. An asynchronous output enable signal (OE) is provided to control the
three-state data outputs. Pipelined RAMs
are used in writable control store, DSp,
data acquisition, and graphics applications
where cycle time and throughput are the
critical parameters. The CY7B159can also
be used in cache applications that utilize
separate input and output buses.
ReadlWrite Operation
The operation of these devices is complet~synchronous with the exception of
the "DE signal. All data, address, and control signals are sampled on each LOW-toHIGH transition of the clock. When the
rn is LOW during this transition, the device is selected for operation. The type of
~ation is determined by the state of the
WE signal during the same transition. WE
LOW causes a write operation while WE
HIGH causes a read operation. The data
input and data output as well as the address register are also loaded on each
LOW-to-HIGH transition of the clock.
The outputs, however, are not enabled for
the address loaded on the current cycle.
The state of the outputs are controlled by
the pipelined
and WE data from the
previous cycle and the state of the UP; signal. The data loaded into the output register is also from the previous cycle and is in
phase with the output control information.
This feature causes a single-cycle latency
for the ftrst read or write cycle, but allows a
word of data to be read or written eve!), 6
nanoseconds. The transparent write feature of the CY7B159 causes written data
to pass through to the output register on
the next cycle.
rn
Write-Through Operation
A third mode, called write-through, is possiblewhenrnis HIGH andWEis LOW. It
will pass the data from the input register to
the output register without changing the
memo!), array. The data can then be accessedfrom theoutputsif~is LOW. This
feature provides an easy-to-use buffer between the input data bus and the output
data bus.
Logic Block Diagram
elK
C:::>--I--I DATA \ - - - - - - - -....- - - - ,
IN
RAM
ARRAY
32Kx8
DATA
OUT
>---<:::J 000 - 007
815!H
Document #: 38-00192
2-178
CY7B161
CY7B162
CYPRESS
16,384 X 4 Static RAM
Separate I/O
SEMICONDUCTOR
Features
Functional Description
• Ultra high speed
-8nstAA
• Low active power
-700mW
• Low standby power
- 2S0mW
• Transparent write (7B161)
• BieMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge.
The CY7B161 and CY7B162 are highperformance BiCMOS static RAMs organized as 16,384 by 4 bits with separate I/O.
Easy memory expansion isJ?!!lvided by active LOW chip enables (eEl>
2) and
three-state drivers. They have a rn powerdown feature, reducing the power consumption by 67% when deselected.
Writing to the device is accomplished when
the c~nable (eEl> ~) and write enable (WE) inputs are all LOW. Data on the
four input pins (10 through 13) is written
rn
Logic Block Diagram
into the memory location specified on the
address pins (AI) through AI3).
Reading the device is accom@edbytaking the chip enables (eEl> ~) and
LOW; while write enable (WE) remains
mOR Under these conditions, the contents of the memory location specified on
the address pins will appear on the four
data output pins (00 through 03).
The output pins remain in hi.8!!:.impedance
state when write enable (WE) is LOW
~62 only), or one of the chip enables
(rnl> CBl) is mOH, or un is mOHo
em
Pin Configurations
D1P/SOJ
ThpView
Lee
,..
Vee
Top ,,"lOW
~~~~c'"
Ao
Ao
A,
A,O
-'1,
A12
A13
10
I,
eE,
llE
GND
Ao
Ia
I.
O.
O.
0,
00
WE
l:E'.
B161-2
B161-1
Selection Guide
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Shaded area contains preliminal)' information.
2-179
Ao
A~
Al1
A,.
A,.
10
I,
eE,
4 3 2~128~
5
25
6
24
7
23
8 7Bl61 22
9 78162 21
10
20
11
19
12
18
1314151617
~::
A,
Ao
Ia
II
Oa
a.
0,
li:!lil~l~oO
Bl61-3
CY7B161
CY7B162
~
tzVl~
Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolutemaximumratedconditionsforextendedperiodsmayaffectdevice reliability. For user guidelines, not tested.)
Storage Temperature ................. Ambient Temperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltagel1] ....................
Electrical Characteristics
Parameters
VOH
Description
Output HIGH Voltage
Automatic CE
Power-Down Current
ISB
Operating Range
55°Cto +125°C
- 0.5V to + 7.0V
Range
Ambient
lemperature
- 0.5Vto +7.0V
- 3.0Vto +7.0V
Commercial
MilililIyl-tJ
- 55°Cto +125°C
Vee
-8
I -10,-12
5V ± 5% 5V ± 10%
5V± 10%
I
O°Cto +70°C
Over the Operating Rangel3]
Output LOW Voltage
Input HIGH Level
Input LOW Voltagel11
Input Load Current
Output Leakage Current
VccOperating
Supply Current
VOL
Vrn
VIL
IJX
loz
Icc
65°Cto +150°C
OutputCurrentintoOutputs(Low) ................ 20rnA
Latch-UpCurrent ............................ > 200 rnA
Static Discharge Voltage ........................ > 2001V
(per MIL-STD-883, Method 3015)
lest Conditions
I IoH = - 4.0 rnA
POH- -2.0rnA
Vee - Min., IOL - 8.0 rnA
Vee = Min.
Com'l
Mil
GND~Vr~Vee
GND ~ Vr ~ Vcc, Output Disabled
Com'l
Vee = Max.,
lOUT = 0 rnA, f = fmax.
Mil
CE~ Vrn,
lOUT = ornA
7B161-8
7B162-8
Min.
Max.
2.4
2.4
0.4
2.2
Vee
- 0.5
0.8
-10
+10
-10
+10
140
7B161-10
7B162-10
Min.
Max.
2.4
2.4
0.4
2.2
Vee
-0.5
0.8
-10
+10
-10
+10
130
Units
V
V
V
V
!JA
!JA
rnA
145
Com'l
Mil
50
40
60
rnA
Shaded area contains preliminary information.
Parameters
VOH
VOL
VIH
VIL
IJX
loz
Icc
ISB
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW VoltagellJ
Input Load Current
Output LeakageCurrent
Vee Operating
Supply Current
AutomaticCE
Power-Down Current
lest Conditions
Vee- Min.
I IOH -
- 4.0 rnA
IIOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Com'l
Mil
GNDO---'l*.NV\O_--'OO 1.73V
Switching Characteristics Over the Operating Rangel3, 6, 7]
7B161-8
7B162-8
Parameters
Description
Min.
Max.
7B161-10
7B162-10
Min.
Max.
7B161-12
7B162-12
Min.
Max.
7B161-15
7B162-15
Min.
Max.
Units
15
ns
15
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from AddressChange
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low ZIKI
tHZOE
OE IDGH to HighZI9j
tLZCE
CE LOW to LowZIKj
8
12
10
8
3
2.5
8
3
10
4.2
1.5
4
CE IDGH to High ZIK, 9j
tHZCE
WRITECYCLEllUj
6
2
5
2
4
ns
8
3
6
2
5
ns
3
12
5
2
2
15
12
10
7
3
6
ns
ns
ns
ns
7
ns
twc
Write Cycle Time
8
10
12
15
tSCE
CE LOW to Write End
7
8
8
10
ns
tAW
Address Set-Up to Write End
7
8
8
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
6.5
8
8
10
ns
tSD
Data Set-Up to Write End
4
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low ZIOJ (7BI62)
2
2
2
3
tHZWE
WELOWtoHighZIO,"J (7BI62)
4
5
6
7
ns
tAWE
WE LOW to Data Valid (7BI61)
8
10
12
15
ns
tADV
Data Valid to Output Valid (7BI61)
8
10
12
15
ns
Notes:
6. Thst conditions assume signal transition time of3 nsor less, timing reference levels of 1.5V, inpnt pulse levels of 0 to 3.0V, and output loading
of the specified IOl)IOH and CL = 20 pF.
7. Both CEI and CEz are represented by CEl in the Switching Characteristics and Waveforms section.
8. At any given temperature and voltage condition, tHZ is less than trzfor
any given device. This parameter is guaranteed and not 100% tested.
ns
ns
lHzCE, tHZOE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ± 200 m V from steady state
voltage. This parameter is gnaranteed and not 100% tested.
10. The intc!_nal write time of the memory is defined bytheoverlapofCEl
LOW,CEzLOW,andWEWW.BothsignaIsmustbeWWtoinitiate
a write and either signal can terminate a write bYgoingHIGH. The data
input sct-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
9.
2-181
•
CY7B161
CV7B162
~
.'~NDUClOR
Switching Waveforms[7J
Read Cycle No. till, 12]
ADDRESS
€=
-----
DATA OUT
~
*-
IRC
IOHA
PREVIOUS DATA VALID
1
~
J
XX)j(===============DA=T=A=V=AL=I=D===========
6161-8
Read Cycle No. 2[11, 13]
Cl:
RC
~~
~
lACE
~~
/ft:
I--
IOOE
ILZOE ----
HIGH IMPEDANCE
DATA OUT
ILZCE
4--
1////
IHZOE IHZCE-
"-'"
HIGH
"- IMPEDANCE
DATAVAUD
/
6161-7
Write Cycle No.1 (WE Controlled)[lO]
lwe
ADDRESS
=:)r
)t'"
IsCE
~ ~~
/ ~ W///&
lAW
IHA-
lSA
IPWE
~~
/fIso
~K'
DATA IN
I--DATA OUT
IHZWE
DATA UNDEFINED
(76162)
IHO
DATA-IN VALID
..::::J
f-
ILZWE~lv
HIGH IMPEDANCE
I'
./I
-IAcV
DATA OUT
(76161)
::::j "
DATA UNDEFINED
DATA VALID
----------------JK-------------
6161-8
Notes:
11. WE is mGH for read cycle.
13. Addressvalid prior to orcoincidentwith CEI and CE2 transition LOW.
12. Device is continuously selected, CE!, CEz 5. VIL. OE 5. VIL also.
2-182
CY7B161
CY7B162
--==---~
~:..,.ib
_'iECYPRESS
=--F
SEMlCONDUCI'OR
Switching Waveforms [7] (continued)
Write Cycle No.2 (CE ControlJed)[10,14]
~------------------------twc------------------------~~
ADDRESS
- - - - - - - - -.....- - - - - tSCE - - - - - . j
CE --r---------~
DATA IN --r-------~
DATA OUT
(7B162)
~--+------
~---
,----~----
IsD ----------...
HIGH IMPEDANCE
DATA UNDEFINED
--+------------tl.==~~~~-----*
DATA OUT ---------D-AT-A-U-N-D-E-F-IN-E-D----------------------------(7B161)
_
---D-AT-A-V-A-U-D-----------_
6161-9
Note:
14, IfeE goes HIGH simultaneouslywith WEIDGH, the output remains
in a high-impedance state (7B162 only),
7B161 Truth Table
CEI
H
X
L
L
L
L
C~
WE
X
H
L
L
L
L
X
X
H
L
L
H
OE
X
X
L
L
H
H
Outputs
HighZ
HighZ
Data Out
Data In
HighZ
HighZ
Inputs
X
X
X
Data In
Data In
X
Mode
Deselectlfuwer-Down
Deselectlfuwer-Down
Read
Write
Write
Deselect
Outputs
HighZ
HighZ
Data Out
HighZ
HighZ
Inputs
X
X
X
Data In
X
Mode
DeselectlPower-Down
DeselectlPower-Down
Read
Write
Deselect
7B162 Truth Table
CEI
H
X
L
L
L
C~
WE
OE
X
H
L
L
L
X
X
H
L
H
X
X
L
X
H
2-183
•
CY7B161
CY7B162
::~PRFSS
JP
-
SEMICONDUCI'OR
Ordering Information
Speed
(ns)
8
10
12
15
Ordering Code
CY7B161-8DC
CY7BI61-8PC
CY7BI61-8YC
CY7BI61-lODC
CY7BI61-lOPC
CY7BI61-lOYC
CY7B161-lODMB
CY7BI61-lOLMB
CY7B161-12DC
CY7B161-12PC
CY7B161-12YC
CY7B161-12DMB
CY7BI61-12LMB
CY7BI61-15DMB
CY7BI61-15LMB
Package
lYPe
D22
P21
Y21
D22
P21
Y21
D22
L54
D22
P21
Y21
D22
L54
D22
L54
Shaded area contams prehmmary mformatlOn.
Operating
Range
Commercial
Speed
(ns)
8
Commercial
10
Military
12
Commercial
Military
15
Military
Ordering Code
CY7B162-8DC
CY7BI62-8PC
CY7BI62-8YC
CY7BI62-lODC
CY7BI62-lOPC
CY7BI62-lOYC
CY7BI62-lODMB
CY7BI62-lOLMB
CY7B162-12DC
CY7B162-12PC
CY7B162-12YC
CY7B162-12DMB
CY7BI62-12LMB
CY7BI62-15DMB
CY7BI62-15LMB
..
Shaded area con tams prelImmary mformatlon.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
YaH
VOL
YIH
YrLMax.
Irx
Ioz
Icc
ISB
Switching Characteristics
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Package
lYpe
D22
P21
Y21
D22
P21
Y21
D22
L54
D22
P21
Y21
D22
L54
D22
L54
Parameters
Subgroups
READ CYCLE
tAA
tOHA
tACE
tDOE
WRITE CYCLE
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tAWE L15J
tADylDJ
Note:
15. 7B161 only.
Document#: 38-A-00014-D
2-184
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
CY7C161
CY7C162
CYPRESS
SEMICONDUCTOR
Features
• Automatic power-down when
deselected
• Transparent write (7CI61)
• CMOS for optimum speed/power
• High speed
- 15 nstAA
• Low active power
- 633mW
• Low standby power
- 220mW
• TTL compatible inputs and outputs
16,384 X 4 Static R/W RAM
Separate I/O
• Capable of withstanding greater than
2001V electrostatic discharge.
Functional Description
The CY7C161 and CY7C162 are highperfonnance CMOS static RAMs organized as 16,384 by 4 bits with separate I/O.
Easy memory expansion is.,Lrovided by active LOW chip enables (CBlo ~) and
three-state drivers. They have an automaticpower-down feature, reducing the power
consumption by 65% when deselected.
Writing to the device is accomplished when
the c~nable (eEl> "EEz) and write enable (WE) inputs are both LOW. Data on
the four input pins (10 through 13) is written
Logic Block Diagram
into the memory location specified on the
address pins (Ao through AI3).
Reading the device is acco~shed by
taking the chip enables (0310 C~) LOW
while write enable (Wi!) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in hi~in1pedance
state when write enable (WE) is LOW
CZQ62 only), or one of the chip enables
(eEl> ~) are mGH.
A die coat is used to insure alpha immunity.
Pin Configurations
r--------------4Q----~
DIP
ThpView
10
A7
Ao
to,.
~
A2
A3
A4
A5
A6
A7
At.
An
At.
O.
At.
Ot
Do
Oa
4
5
6
WE
llE"
CI62·1
Selection Guide!l]
Shaded areas
Note:
1. Formilitaryspeci£u:ations, see the CY7C161NCY7C162Adatasheet.
2-185
ThpVU!W
~U~;
""-
At
As
I,
I.
O.
I.
I,
Do
t:E:,
llE"
GND
O.
0,
WE
eE.
CI62·2
eE,
eE.
Lee
Vee
A"
As
Ao
Ao
fa
As 4
A" 5
Ao 6
~
7
8
3 2~,282~
25
24
23
7C1Sl
22
As 9 70162 21
20
10 10
I,
eE,
11
19
12
18
1314151617
At.
An
At.
to,.
fa
10
Oa
Do
0,
1~~I§I~oO
CI62-3
CY7C161
CY7C162
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
Storage Temperature ................. Ambient Thmperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .......................
DC Voltage Applied to Outputs '
inHighZState ........................
DC Input Voltage ......................
65°Cto +150°C
55°Cto +l25°C
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
- O.5Vto +7.0V
- 0.5Vto +7.0V
- 3.0V to + 7.0V
Ambient
Thmperature
Range
Commercial
Vee
5V± 10%
O°Cto + 70°C
Electrical Characteristics Over the Operating Range
7C161':"16
: '7Cl(j2-10
Parameters
Description
Thst Conditions
'MUt:
7Cl61-12
7CUil-12
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min.,
IoH= -4.0rnA
VOL
Output LOW Voltage
Vee = Min.,
IoL= 8.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltagef2)
IIX
Input Load Current
GND~VI~Vee
-:-10
Ioz
Output Leakage
Current
GND~ VI~Vee,
~10
Output Disabled
los
Output Short
CircuitCurrent[3j
Vee = Max.,
VOUT= GND
- 350
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
IsBI
AutomaticCEI
Power-DownCurrent
Max. Vee,
CEI~ VlH
Min. Duty Cycle = 100%
IsB2
AutomaticCEI
Power-Down Current
Max. Vee,
CEI ~ Vee - 0.3y,
VIN ~ Vee - O.3Vor
Max.
Min.
0.4
0.4
Max.
2.4
2.4
2.4
7C161-15
7C162-15
Units
V
0.4
V
I
2.2
2.2
Vee
2.2
Vee
V
-- 0.5
0.8
-3.0
0.8
V
+10,
,,::10
,+10
-10
+10
+10
-10
+10
-10
+10
!lA
!lA
-350
-350
rnA
160
160
115
rnA
40
40
40
rnA
20
20
rnA
Vee
-:-,0.5 ',,0,8
VIN~0.3V
Shaded areas mdicate advanced information.
2-186
,
'
I,
'~
"
.
CY7C161
CY7C162
ij;~6mucroR
Electrical Characteristics Over the Operating Range( continued)
7C161-20
7C162-20
Description
Pammeters
Thst Conditions
Min.
7C161-25,35
7C162-25,35
Max.
Min.
2.4
Max.
VOH
Output HIGH Voltage
Vee = Min.,
IOH = - 4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min.,
IOL=8.0rnA
Vrn
Input HIGH Voltage
2.2
Vee
2.2
Vee
VIL
Input LOW Voltagel2]
-3.0
0.8
-3.0
0.8
IIX
Input Load Current
GND.5 VI.5 Vee
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND.5 VI.5 Vee,
OutputDisabled
-10
+10
-10
+10
los
Output Short
CircuitCurrend3]
Vee = Max.,
VOUT=GND
-350
Ice
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
ISBl
AutomaticCEl
Power-Down Current
Max. Vee,
7C161-45
7C162-45
Min.
Max.
Units
V
2.4
0.4
V
2.2
Vee
V
-3.0
0.8
V
-10
+10
-10
+10
JAA
JAA
-350
-350
rnA
80
70
50
rnA
40
20
20
rnA
20
20
20
rnA
0.4
0.4
CEl~Vrn
Min. Duty Cycle = 100%
AutomaticCEl
Power-Down Current
ISB2
Max. Vee,
CEl ~ Vee - 0.3v,
VIN ~ Vee - O.3Vor
VIN.50.3V
Capacitance[4]
Description
Pammeters
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
Max.
Units
10
pF
10
pF
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
2. VIL min. = - 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4. Thstedinitially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl481.o.
5V
OUTPl/T
30 pF
R2
255.0.
I
Jk~~~ -=-
INCLUDING
R1481.o.
5V
Ol/TPUT
ALL INPUT PULSES
5 PF
INCWDING
-=-
J~~~
(0)
Equivalent to:
1
-=(h)
R2
255.0.
-=-
3'OV~90%
GND
10%
.5.5ns
Cl62-4
THEVENIN EQUIVALENT
167.0.
OUTPUT 0.0---'11,111,_-- eEz = VIL.
DATA VALID
C182-8
12. Address valid prior to or coincident with eEl. CEz transition LOW,
2-190
CY7C161
CY7C162
'-~PRFSS
---=-.F
SEMICONDUCTOR
Switching Waveforms [8] (continued)
Write Cycle No.2 (CE Controlled) [9, 13]
~------------------------twe --------------------------~
ADDRESS
---------ok------Isce-------.j
CE
----+-----------------~
14------DATA IN ------------------~
r-------+--------
Iso -------I....
DATA-IN VAUD
+-________~---------
DATA OUT _________
H_IG_H_I_M_P_ED_A_N_C_E____________________________
(7C162)
DATA OUT ______________________________________
-<
",-~....:.o~
(7C161)
e162·g
Note:
13. If CE goes HIGH simultaneouslywith WE HIGH, the output remains
in a high-impedance state (7C162 only).
lYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
'vs. AMBIENT TEMPERATURE
NO~EDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
!ll
1.2
~
1.0
Icc
V
0
w 0.8
N
:J
«
::;;
0.6
0
0.4
V
./
V
!5z
0.2
4.5
5.0
6.0
j1.4
1.2
0
1.1
~
1.0
w
............
r---......
0.9
0.8
4.0
@ 40
~
n. 20
25
125
4.5
5.0
--
SUPPLY VOLTAGE
1.0
./
a: 1.0
t--6.0
z
0.8
2.0
~
0.6
-55
./
~
125
II
60
o~ 20 I
o
0.0
4.0
I
80
~ 40
AMBIENT TEMPERATURE (OC)
2-191
i3
'"
M
V
a:
Z
(jj
Vee = 5.0V
25
3.0
OUTPUT VOLTAGE
~ 100
./
1.2
0
M
0
0.0
«'140
.§.. 120
~
z
::;;
TA=25°C
5.5
5
'" " ""
Vcc= 5.0V
TA = 25°C
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.6
j
z
~ 80
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
0
0
a:
o
AMBIENT TEMPERATURE (OC)
M
1.3
a:
~
Vee -5.0V
VIN= 5.0V
ISB
0.0
-55
1.4
«
zw 100
~ 60
a:
0.4
NO~EDACCESSTIME
::;;
120
~
:::J
vs. SUPPLY VOLTAGE
w
N
:J
1
~
5.5
SUPPLY VOLTAGE
------
0.2 -
ISB
0.0
4.0
1.0
o8 0.8
~ 0.6
a:
z
1.2
m
~
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
I
/
Vee =; 5.0V
TA = 25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C161
CY7C162
~
~~PRESS
~; SEMICONDUCTOR
lYPical DC and AC Characteristics (continued)
TYPICALPOWER·ON CURRENT
VB. SUPPLY VOLTAGE
0
30.0
2.5
IJ. 25.0
.E:-
o 2.0
w
fil
~
N
:::J
«
:; 1.5
II:
az
TYPICALACCESS TIME CHANGE
1.25
~
20.0
/
15.0
II:
1.0
0.5
0.0
0.0
1.0
---
2.0
~
3.0
SUPPLY VOLTAGE
./
4.0
5.0
M
az
10.0
5.0
V
V
200
/
Name
Address
Function
AS
X3
A6
A7
X4
AS
A3
X6
X7
YO
Yl
Y5
Y4
Y3
Y2
XO
Xl
A4
X2
A9
AlO
All
A12
A13
AO
Al
A2
X5
/
Jl
,-
Vcc=4.5V TA = 25°C
,
400
600
800 1000
CAPACITANCE (pF)
Address Designators
Address
NORMALIZED Icc vs. CYCLE TIME
VS. OUTPUT LOADING
3.0
Pin
Number
1
2
3
4
5
6
7
8
9
23
24
25
26
27
2-192
Vcc= 5.0V
TA = 25°C
Vcc= 0.5V
~
II:
az
0.501'='0-----!:2""0---:3~0-----!40
CYCLE FREQUENCY (MHz)
CY7C161
CY7C162
..z;~
~~PRESS
~.iP'
SEMICONDUCTOR
Ordering Information
Speed
(ns)
10
12
15
20
25
35
45
Package
1YIJe
Operating
Range
Speed
(ns)
CY7CI61-lOPC
P21
Commercial
10
CY7C161-10VC
V21
CY7CI61-lODC
D22
CY7C161-10LC
154
CY7C161-12PC
P21
CY7C161-12VC
Ordering Code
Package
type
Operating
Range
CY7C162-lOPC
P21
Commercial
CY7C162-1OVC
V21
CY7C162-lODC
D22
CY7C162-10LC
154
Ordering Code
CY7C162-12PC
P21
V21
CY7C162-12VC
V21
CY7C161-12DC
D22
CY7C162-12DC
D22
CY7C161-12LC
154
CY7C162-12LC
154
CY7C161-15PC
P21
CY7C162-15PC
P21
CY7C161-15VC
V21
CY7C162-15VC
V21
CY7C161-15DC
D22
CY7C162-15DC
D22
CY7C161-15LC
154
CY7C162-15LC
L54
CY7C161-20PC
P21
CY7C161-20VC
Commercial
12
15
Commercial
CY7C162-20PC
P21
V21
CY7C162-20VC
V21
CY7C161-20DC
D22
CY7C162-20DC
D22
CY7C161-20LC
154
CY7C162-20LC
L54
20
Commercial
CY7C161-25PC
P21
CY7CI62-25PC
P21
CY7C161-25VC
V21
CY7C162-25VC
V21
CY7C161-25DC
D22
CY7C162-25DC
D22
CY7C161-25LC
154
CY7C161-25LC
L54
CY7C161- 35PC
P21
CY7C161-35VC
V21
CY7C161-35DC
CY7C161-35LC
CY7C161-45PC
P21
CY7C161-45VC
V21
CY7C161-45DC
CY7C161-45LC
Shaded areas indicate advanced information.
25
Commercial
CY7C162-35PC
P21
CY7C162-35VC
V21
D22
CY7C162-35DC
D22
154
CY7C162-35LC
L54
35
Commercial
CY7C162-45PC
P21
CY7C162-45VC
V21
D22
CY7C162-45DC
D22
154
CY7C162-45LC
L54
45
Commercial
Shaded areas indicate advanced information.
Document #: 38-00029-G
2-193
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C161A
CY7C162A
CYPRESS
SEMICONDUCTOR
Features
• Automatic power-down wben deselected
• Transparent write (7C161A)
• CMOS for optimum speed/power
• High speed
- 12 ns tAA
• Low active power
- \l3SmW
• Low standby power
- 220mW
• TTL-compatible inputs and outputs
16,384 X 4 Static RIW RAM
Separate I/O
• Capable ofwitbstanding greater than
2OO1V electrostatic discharge.
is written into the memory location specified on the address pins (Ao tbroughAI3)·
Functional Description
Reading the device is accoml!!!shed by
taking the chip enables (ml, CEV LOW
while write enable (WE) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The CY7C161A and CY7C162A are highperfonnance CMOS static RAMs organizes as 16,384 by 4 bits with separate I/O.
Easy memory expansion isJ!..,rovided by active LOW chip enables (eEl> ~) and
tbree-state drivers. They have an automaticpower-downfeature, reducing the power
consumption by 60% when deselected.
Writing to the device is acco"!!!plished
when the chUnable (eEl> C~) and
write enable (WE) inputs are both LOW.
Data on the four input pins (10 through h)
Logic Block Diagram
The output pins stay in hi~inlpedance
state when write enable (WE) is LOW
(19.62A only), or one of the cbip enables
(eEl> ~) are HIGH.
A die coat is used to insure alpha immunity.
Pin Configurations
r-------------~Q----~
DIP
ThpView
10
LCC
ThpYJew
Vee
Ia
~
~c~~;
AI
Ao
A,
Au
A,
A2
A3
~
~
Oa
A,.
Au
A12
A,.
I.
I,
00
CE,
OE
00
0,
GND
Ao
9
Ia
10
00
Oa
0,
00
WE
CEo
AI
::
•5 3 2~,28~25
6
7
8
9
Ae
A7
Ae
10 '0
I,
CE,
2.
23
7C'6'A 22
7C182A 21
20
,9
11
18
12
,3"'5,817
A12
Al1
A,.
Ae
b
I:!
00
Oa
0,
II!! ~Ilfl~cf
C181A-3
C161M!
CE,
CE.
WE
'OE
C161A·1
Selection Guide[l]
Note:
1. Forcommerciaispecifications,seetheCY7C161/CY7C162datasheet.
2-194
CY7C161A
CY7C162A
$ ;~PRESS
~.' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... -55°Cto+125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Operating Range
Ambient
lemperature
Range
Militaryl2]
Vee
5V± 10%
- 55°Cto +125°C
Electrical Characteristics Over the Operating Rangd3]
Parameters
Description
lest Conditions
7C161A-12
7C162A-12
7C161A-lS
7C162A-lS
7C161A-20
7C162A-20
Min.
Min.
Min.
Max.
2.4
Max.
2.4
Max.
2.4
Units
VOH
Output HIGH Voltage
Vee = Min., IoH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IoL = 8.0 rnA
VIH
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltage[4]
-0.5
0.8
-0.5
0.8
-3.0
0.8
V
IJX
Input Load Current
GNDSVIsVee
-10
+10
-10
+10
-10
+10
-10
+10
-10
+10
-10
+10
t-tA
t-tA
loz
Output Leakage
Current
GNDSVISVee,
Output Disabled
los
Output Short
CircuitCurrent[5]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max.
IoUT = ornA
ISBl
ISB2
0.4
0.4
V
0.4
V
-350
-35(}
-350
rnA
Military
170
160
100
rnA
AutomaticCE
Power-Down Current
Military
Max. Vco CE 2:. V IH,
Min. Duty Cycle = 100%
40
40
40
rnA
Automatic CE
Power-Down Current
Max. Vro
CEl 2:. Vee - 0.3V,
VIN 2:. Vee - 03V
orVINs03V
Military
20
20
20
rnA
Shaded area contruns advanced information.
Notes:
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
2-195
VIL min. = - 3.0V for pulse durations less than 30 ns.
Not more than 1 output should be shorted at one time. Duration ofthc
short circuit should not exceed 30 seconds.
•
CY7C161A
CY7C162A
2Vl~DUCfOR
Electrical Characteristics Over the Operating Rangel3] (continued)
Description
Parameters
Thst Conditions
= Min.,IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
7C16IA-25
7Cl62A-25
7C16IA-35,45
7C162A-35,45
Min.
Min.
Max.
VOH
Output HIGH Voltage
2.4
VOL
Output WW Voltage
Vrn
Input HIGH Voltage
2.2
Vee
VIL
Input WW Voltage[4]
-3.0
IIX
Input Load Current
GND.$. VI.$. Vee
-10
loz
Output LeakageCurrent
GND.$. VI.$. Vee, Output Disabled
-10
los
Output Short
CircuitCurrent[S]
Vee
lee
Vee Operating
Supply Current
Vee = Max., lOUT
IsBl
AutomaticCE
Power-DownCurrent
ISB2
AutomaticCE
Power-DownCurrent
Vee
Units
Max.
2.4
V
0.4
0.4
V
2.2
Vee
V
0.8
-3.0
0.8
V
+10
-10
+10
+10
-10
+10
tAA
tAA
-350
-350
rnA
Military
100
100
rnA
Max. Vee, CE ~ Vrn,
Min. Duty Cycle = 100%
Military
40
30
rnA
Max. Vee,
Military
20
20
rnA
= Max., VOUT = GND
= 0 rnA
CEl ~ Vee - 0.3v,
VIN ~ Vee - O.3V
or VIN .$. 0.3V
Capacitance [6]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
Units
10
pF
10
pF
Note:
6. 'Iested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
5V
OUTPUT
30pF
I
R2
2550
INCLUDING
JIG AND
SCOPE (a)
-=
Equivalent to:
-=
R14Bl0
5V
OUTPUT
ALL INPUT PULSES
I
5pF
INCLUDING
JIG AND
SCOPE (b)
-=
R2
2550
-=
3AN~
GND
10%
5.5 ns
C161A-4
THEVENIN EQUIVALENT
1670
OUTPUT ().O- _...."'
. ." ' - - - 0 0 1.73V
2-196
90%
fe::
10%
-
5.5 ns
C161A-5
CY7C161A
CY7C162A
~.~
~=CYPRESS
~_, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel2, 7, 8]
7C16IA-12 7C16IA-15
7C162A-12 7C162A-15
Parameters
Description
Min.
READ CYCLE
Read Cycle Tune
tRC
tAA
Address to Data Valid
tOHA
Output Hold from
Address Change
Max. Min.
12
Max. Min.
3
Max.
20
15
12
7C161A-20
7C162A-20
Min.
Max. Min.
25
5
5
7C16IA-45
7C162A-45
Max. Min.
35
25
20
15
3
7C16IA-25 7C161A-35
7C162A-25 7C162A-35
Max. Units
45
ns
45
35
5
5
ns
ns
tACE
CE LOW to Data Valid
12
15
20
25
35
45
ns
tOOE
OELOWtoDataVaiid
6.
7
10
12
15
20
ns
tLZOE
OE LOW to LOW Z
tHZOE
OE IDGH to IDGH Z
tLZCE
CE LOW to Low ZI9 1
tHZCE
CE IDGH to
High Z[9, 10]
tpu
CE LOW to Power-Up
0
8
7
3
3
0
10
8
0
12
0
5
0
20
ns
15
15
10
20
15
3
5
5
5
0
12
CE IDGH to
Power-Down
WRITECYCLELllJ
3
3
8
8
7
tpo
3
0
ns
15
ns
ns
0
25
20
ns
ns
40
ns
30
ns
20
25
25
25
30
ns
0
0
0
0
ns
0
0
0
0
0
ns
8
10
15
15
20
20
ns
6
7
10
10
15
15
ns
Data Hold from
WHteEnd
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
Low z[9] (7CI62A)
3
3
5
5
5
5
ns
tHZWE
WE LOW to
High z[9, 10] (7CI62A)
6
7
7
7
10
15
ns
tAWE
WE LOW to
Data Valid (7CI61A)
12
15
20
25
30
35
ns
tADV
Data Valid to Output
Valid (7CI61A)
12
15
20
20
30
35
ns
tocE
CE LOW to Data Valid
(7C161A)
12
15
20
25
30
35
ns
twc
WHte Cycle Tune
12
15
20
20
tsCE
CE LOW to Write End
8
10
15
20
tAW
Address Set-Up to
WHteEnd
9
10
15
tHA
Address Hold from
WHteEnd
0
0
tSA
Address Set-Up to
WHte Start
0
tpWE
WE Pulse Width
tso
Data Set-Up to
WHteEnd
tHO
Shaded area contams advanced mformation.
Notes:
7. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V; input pulse levels of 0 to 3.0V; and output loading
of the specified IOrJIOH and 30-pF load capacitance.
8. Both CEI and CEz are represented by CE in the Switching Characteristics and Waveforms sections.
9. At anygiven temperature and voltage condition, tHZ is less than tIZ for
any given device.
10. tHzCEandtHZwEarespecifiedwithCL=5pFasinpart(b)ofACThst
Loads and Waveforms. 'fransition is measured ±500 mV from steady
state voltage.
11. The internal write time of the memory is defined by the overlap ofCEI
LOW, CEzWW, and WE LOW Both signals must be WW to initiate
awriteandeithersignalcanterminateawritebygoingIDGH. The data
input set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
2-197
CY7C161A
CY7C162A
~
.AL~NDOCTOR
Switching Waveforms[8]
Read Cycle No. 1[12, 13]
IRc
)1{'
~I{'
ADDRESS
1M
I-'--IoHA~
DATA OUT
PREVIOUS DATA VALID
JfXXXXX)(
DATAVALIb
C161Ml
Read Cycle No. 2[12, 14]
IRC
~~
.J~
lACE
~
/
IHZOE -
IDOE
_ _ I!ZOE -------
HIGH IMPEDANCE
DATA OUT
f4////
"-
,~'\.'\
HIGH
IMPEDANCE
/
I!ZCE
Vee
IHZCE -
DATA VALID
I---
_Ipu
IpD
~ CC
I
SUPPLY
CURRENT
50%
ISB
C161A-7
Write Cycle No.1 (WE Controlled) [11]
~----------------------- lwe ------------------------~
ADDRESS
___
..t===~I~SA~===~~~,
"'---- IPWE
----~
,___________
DATA IN
DATA
OUT _ _ _ _ _ _ _DATA
UNDEFINED
(7C162A)
__
____
+_~--~
DATA
OUT _ _ _ _ _ _ _DATA
UNDEFINED
(7C161A)
__
_ _ _ _ _ _ __
DATA VALID
C161A-8
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected, CEl. CE2 = VIL.
14. Address valid prior to or coincident with CEl. CE2 transition LOW.
2-198
CY7C161A
CY7C162A
;~PRESS
.
~.F SEMICONDUCTOR
Switching Waveforms (continued)
•
Write Cycle No.2 (CE Controlled) [11, 15]
twc
ADDRESS
~
jK:
I(
tSA
tSCE
~,
~
tHA-
tAW
L
tPWE
..
~~~~~
)
tHD
IsD
)~
DATA IN
DATA OUT
(7C162A)
~
DATA-IN VALID
HIGH IMPEDANCE
I--
leCE
(XXX.,I r\.
DATA OUT
(7C161A)
tHZCE .....
"'
DATA VALID
/
C161A-
tADV
Notes:
15. IfCE goes HIGH simultaneously with WEIDGH, the output remaios
in a high-impedance state (7C162A only).
'JYpical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
1.4
!ll1.2
Icc
..? 1.0
c
w
N 0.8
::J
..:
::;:
0.6
V
V
f7
1/
z
~
C
~
1.0
~
0.8
ISB
4.5
5.0
SUPPLY VOLTAGE
i-------'5.5
M
6.0
~ 100
~
~
::>
U
0.2
~
::>
I-
g
5"-
VCC-·5.0V
VIN= 5.0V
ISB
I-
0.0
80
~ 60
0.6
z
0.2
§. 120
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
I-
w
~ 0.4
0.4
0.0
4.0
1.2
ID
8
II:
0
~
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
-55
25
125
AMBIENT TEMPERATURE (OC)
2-199
5
40
'"""
20
0
0.0
1.0
2.0
Vcc= 5.0V
TA = 25°C
"
3.0
OUTPUT VOLTAGE
"
M
4.0
CY7C161A
CY7C162A
~
fs~~DUCfOR
lYPical DC and AC Characteristics (continued)
NO~ZEDACCESSTUKE
NO~DACCESST~
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.6
1.4
j
1.3
j
c 1.2
w
c
N
::J
«
::;
1.1
..........
a:
0
z
1.0
TA= 25°C
I'.......
--...
0.9
0.8
4.0
4.5
5.0
---
5.5
0.8
-55
0
1.0
0.0
0.0
./
_V
1.0
2.0
3.0
4.0
5.0
SUPPLY VOLTAGE (V)
/'
/
Pin
Number
AS
X3
X4
I
2
3
4
A6
A7
X5
A3
X6
X7
YO
YI
Y5
Y4
Y3
Y2
XO
Xl
A4
X2
AS
A9
AlO
All
Al2
A13
AO
Al
A2
o
I
0.0
/
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NO~ZEDlcc vs.
CYCLE TIME
V
V
0.0 0
Vcc- 4.5V
TA = 25°C
1 1-
200
8
Vcc= 5.0V
TA = 25°C
Vee = 0.5V
fil
a:
400
Address Designators
Address
Function
20
/
Vcc= 5.0V
TA = 25°C
~
/
600
800 1000
CAPACITANCE (pF)
Address
Name
!5o
..,-
« 15.0
!j
~ 10.0
5.0
40
/
V
1.25
:l:
0.5
80
!:i
125
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTWADING
a:
z
25
TYPICALPOWER·ON CURRENT
vs. SUPPLY VOLTAGE
N
100
a
a:
"
AMBIENT TEMPERATURE (0C)
:[ 20.0
M!
I
V
z 60
SUPPLY VOLTAGE (V)
.2c 2.0
w
120
Cii
Vee = 5.0V
0.6
25.0
1.5
/
/
z
2.5
::J
./
0
6.0
.5.
!z
1.4
30.0
«
::;
<,140
w
N 1.2
::J
«
::;
a: 1.0
3.0
0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
5
6
7
8
9
23
24
25
26
27
2-200
oz
o.5o1·l:::o-----,2~0,.-----:!370----l40
CYCLE FREQUENCY (MHz)
CY7C161A
CY7C162A
·-~PRFSS
=.'
SElvIlCONDUCTOR
Ordering Information
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Speed
(ns)
Ordering Code
Package
'J.Ype
12
CY7C161A-12DMB
D22
CY7C161A -12LMB
L54
CY7C161A-15DMB
022
15
CY7C161A -15LMB
L54
CY7C161A-20DMB
D22
CY7C161A - 20LMB
L54
CY7C161A-25DMB
D22
CY7C161A-25LMB
L54
CY7C161A- 35DMB
D22
CY7C161A - 35LMB
L54
CY7C161A -45DMB
D22
CY7C161A -45LMB
L54
Speed
(ns)
Ordering Code
Package
'J.Ype
12
CY7C162A-12DMB
D22
20
25
35
45
15
20
25
35
45
Operating
Range
DC Characteristics
Military
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
1,2,3
los
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Military
Military
Military
Military
Military
Operating
Range
Switching Characteristics
Parameters
Military
Subgroups
READ CYCLE
CY7C162A -12KMB
K74
tRC
7,8,9, 10, 11
CY7C162A-12LMB
L54
tM
7,8,9, 10, 11
CY7CI62A-15DMB
022
toHA
7,8,9, 10, 11
CY7C162A-15KMB
K74
tACE
7,8,9, 10, 11
CY7C162A-15LMB
L54
tDOE
7,8,9,10,11
CY7C162A-20DMB
022
CY7C162A-20KMB
K74
twc
7,8,9, 10, 11
CY7C162A -20LMB
L54
tsCE
7, 8, 9, 10, 11
Military
Military
WRITE CYCLE
CY7C162A-25DMB
D22
tAW
7,8,9, 10, 11
CY7CI62A-25KMB
K74
tHA
7, 8, 9, 10, 11
CY7C162A-25LMB
L54
tSA
7,8,9, 10, 11
CY7CI62A-35DMB
022
tpWE
7,8,9, 10, 11
CY7C162A-35KMB
K74
tSD
7,8,9, 10, 11
tHD
7,8,9,10,11
tAWE[l6]
7,8,9,10,11
tADv[lS]
7, 8, 9, 10, 11
CY7C162A-35LMB
L54
CY7C162A-45DMB
D22
CY7C162A-45KMB
K74
CY7C162A-45LMB
L54
Shaded area contams advanced mformation.
Military
Military
Military
Notes:
16. 7C161A only.
Document#: 38-00116-A
2-201
•
CY7B163
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Expandable 256K x 1 Static
RIW RAM with Separate I/O
Features
Functional Description
• Highspeed
- tAA
IOns
• Five chip enables (CEb203 and CE.!,s)
to expand memory
• BiCMOS for optimum speed/power
• Low active power
-770mW
• Low standby power
- 330mW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
The CY7B163 is a high-performance
BiCMOS static RAM organi2ed as 256K
words by 1 bit. Easy memory expansion is
jJrovided five chip enables for each part
(CEl> C~, CE3, CE4> and CEs). The active HIGH and active LOW chip enables
provide on-chip address decoding, eliminating the need for external decoder logic.
The CY7B163 has an automatic powerdown feature, reducing the power consumption by more than 50% when deselected by any CE input.
Writingto the device is accomplished when
CEl>2,3 and WE are LOW; and CE4,S are
HIGH Data on the input pin (DIN) is
=
Logic Block Diagram
written into the memory location specified
on the address pins (Ao throughA17).
Readingthe device is accomplished by taking chip enables CEt,2,3 LOW while WE
and chip enables CE4>sremainHIGH. Under these conditions, the contents of the
memory location specified by the address
pins will appear on the data output pin
(DOUT)'
The output pin (DoUT) is in ahigh-impedance state when the device is deselected
(any of: CEl 2 3 HIGH or CE4S L0..w, or
during a write' operation (WE IIDd CEl 2,3
LOW and CE4,S HIGH).
'
The CY7B163 is available in leadless chip
carriers and space-saving 300-mil-wide
DIPs and SOJs.
Pin Configurations
DIP/SOJ
LCe
Top View
Top View
~<~~y~;
Vee
A,
A,.
A17
A,s
A,.
A'4
CE,;
As
Ao
A7
A'3
A'2
CEo
A11
A,o
9
CEo
As
Dour
WE
4 3
As
ctAs
As
A7
CEo
NC
As
As
A,.
A,.
CE,;
NC
A'3
A'2
CEo
A11
AlO
5IWCUIW~~
D,N
B~~Zuc
CE,
GND
2~11323130
29
5
28
6
27
7
28
8
25
7B163
9
24
10
23
11
22
12
21
13
14151617181920
B163-3
B163-2
B163-1
Selection Guide
7BUi3 10
7B163-l2
7B163-l5
7B163-20
10
12
15
20
150
130
125
130
125
30
30
40
40
MaximumAccess Time (ns)
Maximum Operating
Current(mA)
Commercial
Maximum Standby
Current(mA)
Commercial
Military
Military
.·30
..
Shaded area contams
. advanced information.
2-202
120
40
B-~
PRELIMINARY
~=CYPRESS
~_IF
CY7B163
SEMICONDUCIOR
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Thmperature ................ . - 65°C to + 150°C
Ambient Thmperaturewith
Power Applied ...................... . - 55°C to + 125°C
Supply Voltage on Vee relative to GND[ll
- 0.5Vto +7.0V
Static Discharge Voltage........................ >2oo1V
(per MIL-STD·883, Method 3015)
Latch·UpCurrent ............................ >2oornA
Operating Range
~C yoltage Ap8lied to Outputs
Vee
O°Cto +70°C
5V± 10%
- 55°Cto +l25°C
5V± 10%
Commercial
In High
Z State ]....................... - O.5V to + 7.0V
DC Input Voltage[1] .................... -0.5Vto+7.0V
Current into Outputs (LOW) ., . . . . . . . . . . . . . . . . . . .. 20 rnA
Electrical Characteristics
Ambient
Thmperature[2]
Range
Military
Over the Operating Rangef3]
7B163-10
Description
Parameters
Thst Conditions
Min.
Max.
2A
7B163-12
Min.
Max.
2A
7B163-15, 20
Min.
Max.
Units
0.4
V
2A
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 0.8 rnA
VlH
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltagefl]
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
IIX
Input Load Current
GND5VI5 Vee
-10
+10
-10
+10
-10
+10
loz
Output Leakage
Current
GND5 Vo5 Vee,
OutputDisabled
-10
+10
-10
+10
-10
+10
flA
flA
los
Output Short Circuit
Currentl4]
Vee = Max., VOUT = GND
Icc
Vee Operating Supply
Current
Vee = Max., lOUT =
f = fMAX = lItRe
Automatic CE Power·
Down Current
-CMOS Inputs
Max. V CO CE1,2,3 ~ Vee
- 0.3v, or CE4,5 50.3V,
VIN ~ Vee - O.3Vor
VIN 50.3V, f=O
ISB
OA
ornA
Com'l
Mil
V
-300
-300
-300
rnA
150
130
125
rnA
130
125
30
30
40
40
Mil
Com'l
OA
40
rnA
Shaded area contams advanced mformation.
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
OutputCapacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Notes:
1. VIL (Min) = - 3.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing in·
formation.
4.
Max.
Units
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
2-203
•
g i~PRESS
F
PRELIMINARY
CY7B163
SEMICONDUCTOR
AC Test Loads and Waveforms
R1481Q
R1481Q
OUTP~~31
OUTPUT
5V31
20pF
R2
255Q
I _
INCLUDING
JIG AND SCOPE
5pF
I
(a)
Equivalent to:
'''~
10%
~
90%
10%
GND
R2
INCLUDING _
JIG AND SCOPE
-
ALL INPUT PULSES
.....
.5.3ns .....
_ 255Q
-
.5.3ns
Bl63-5
Bl63-4
(b)
THEVENIN EQUIVALENT
167Q
OUTPUT
OD---¥
..",,---oo
1.73V
Switching Characteristics Over the Operating Rangel3, 6]
7B163-10
Parameters
Description
7B163-12
78163-15
78163-20
Min.Mu. Min. Max. Min. Mu. Min. Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CEl,2,3 WW and CE4,5 HIGH to Data Valid
12
10
10
3
15
12
3
3
12
10
3
ns
20
15
20
20
15
3
ns
ns
3
ns
tLZCE
CEl,2,3 WW and CE4,5 HIGH to Low z!7]
IHZCE
CEl,2,3 HIGH or CE4,5 LOW to High Z[7, 8]
6
7
8
10
ns
tpu
CEl,2,3 LOW and CE4,5 HIGH to Power-Up
0
0
0
0
ns
tpD
CEl,2,3 HIGH or CE4,5 LOW to Power-Down
10
12
15
20
ns
3
ns
3
WRITECYCLEl9]
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CEl,2,3 LOW and CE4,5 HIGH to Write End
8
9
10
15
ns.
tAW
Address Set-Up to Write End
8
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
8
9
10
15
ns
tSD
Data Set-Up to Write End
6
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
2
tHZWE
WE LOW to High Z[7, 8]
2
5
Shaded area contams advanced information.
Notes:
6. Thstconditions assume signal transition time of3 nsor less, timing reference levelS of1.SV, input pulse levels of 0 to 3.0V, and outputloading
of the specified IorJIOH and 20 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tIZCE and lHzWE is less than trzWE for any given device.
8. tHZCE and lHzWE are specified with a load capacitance of S pF as in
part (b) in AC Thst Loads and Waveforms. Transition is measured
±SOO m V from steady state voltage.
9.
2-204
2
7
ns
2
7
10
ns
The internal write time of the memory is defined by the overlap of
CEl,2,3 Law, CE!,5 IDGH, and WE LOW. All signals must be asserted to initiate a write, and by being deasserted, any signal can terminate a write. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
·
'~PRESS
PRELIMINARY
CY7B163
~JF SEMICONDUCTOR
Switching Waveforms
Read Cycle No.
trw, 11]
IRC
-""E
ADDRESS
') (
II)
~
1M
_IOHA~
DATA OUT
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ........................... . >200mA
StorageThmperature ................. - 65°Cto + 150°C
Ambient Temperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 125° C
Supply Voltage to Ground Potential ........ - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DC Input Voltage/l] .................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) ............... 20 mA
Operating Range
Range
Ambient
Thmperature
Commercial
O°Cto + 70°C
Vee
I 5V±5%
-8
-to, -12
Militaryl2]
I 5V ±to%
5V±to%
- 55°Cto + 125°C
Electrical Characteristics Over the Operating Rangel3]
78164-8
78166-8
Parameters
Description
Thst Conditions
I IoH= -4.0mA
I IoH = -2.0mA
VOH
Output HIGH Voltage
Vee = Min.
VOL
Vrn
VII.
IIX
loz
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel1]
Input Load Current
Output Leakage
Current
Vcc Operating Supply
Current
Vcc = Min., IOL = 8.0 mA
lee
IsB
CE Power-DownCurrent
GND5VI5 Vcc
GND5 Vo5 Vee,
Output Disabled
Vcc = Max., loUT = 0 rnA,
f=fmax.
CE.<::. Vrn,
IoUT=OmA
Min.
Com'l
Mil
Max.
VOH
Description
Output HIGH Voltage
0.4
2.2
-0.5
-10
-10
Com'l
Mil
Com'l
Mil
Thst Conditions
Vcc=Min.
I IoH = -4.0mA
I
VOL
Vrn
VII.
IIX
Ioz
Icc
ISB
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel1]
Input Load Current
Output Leakage
Current
Vee Operating Supply
Current
CE Power-DownCurrent
IOH = -2.0mA
Vee = Min., IOL = 8.0mA
GND< VI < Vee
GND5Vo 5 Vee,
Output Disabled
Vcc = Max., lOUT = 0 rnA,
f = fmax.
CE.<::. Vrn,
IOUT=OmA
Min.
Vee
0.8
+10
+10
Max.
2.4
Min.
Com'l
Mil
Com'l
Mil
Max.
2.4
Vee
0.8
+10
+10
120
140
!-IA
!-IA
mA
mA
0.4
2.2
-0.5
-10
-10
Units
V
Vee
0.8
+10
+10
V
V
V
!-IA
!-IA
mA
135
mA
40
55
V
V
V
78164-15
78166-15
0.4
2.2
-0.5
-10
-10
Vee
0.8
+10
+10
130
145
40
60
50
Units
V
0.4
2.2
-0.5
-10
-10
140
Min.
Com'l
Mil
Max.
2.4
2.4
78164-12
78166-12
Parameters
78164-10
78166-10
50
Shaded area contains preliminary infonnation.
Notes:
1. VIL(min.) = -3.0Vfor pulse width <20ns.
2. TA is the "instant on" case temperature.
3.
2-209
See the last page ofthis specification for Group Asubgroup testing in·
fonnation.
CY7B164
CY7B166
~~
~.E CYPRESS
~,
SEMlCONDUClDR
Capacitance [4]
Parameters
Description
InputCapacitance
uutputcapaCltanee
ClN
CoUT
MaxPJ
6
6
Thst Conditions
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
Units
pF
pF
AC Test Loads and Waveforms
R14B1n
5V <>------'WIo-,
R1481n
5V < > - - - - - - . . . ,
OUTPUT <>---.,...---t
OUTPUT<>---""'---i
ell
5PFI
R2
255n
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
R2
GND
255,n
_....;.;=r
.s3ns
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.CW - - - - -lr-:.~---~
81fl4.8
8164·7
THEvENIN EQUIVALENT
167n
OUTPUT
oo----".,.........--.()o 1.73V
Switching Characteristics Overthe Operating Rangel:3, 6]
7B164-8
7B166-8
Parameters
READ CYCLE
Description
Min.
Read Cycle Time
Address to Data Valid
tORA
tACE
tOOE
Output Hold from AddressChange
CE WW to Data Valid
OE LOW to Data Valid
7B166
OE LOW to Low Zl8J
7B166
OE HIGH to High Zl7J
CE LOW to Low ZlOJ
CE HIGH to High Zl7, OJ
tHzCE
WRITECYCLEl"J
Write Cycle Time
twc
tHZOE
tLZCE
tSCE
CE LOW to Write End
tAW
tRA
tSA
tpWE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
tso
tHO
tLZWE
Data Hold from Write End
WE HIGH to LowZloJ
tHZWE
WE LOW to High Zl/J
=
Max.
2
2
2
4
8
7
7
0
0
6.5
4
0
2
4
8.
9.
2-210
ns
ns
ns
15
6
ns
ns
7
ns
ns
7
ns
ns
3
2
5
6
Units
15
2
6
5
Max.
3
12
5
5
4
Min.
15
3
2
1.5
Max.
7BI64-15
7B166-15
12
10
8
4.2
7B166
Min.
12
3
2.5
7B164-12
7B166-12
10
8
Notes:
4. Thsted initially and after any design or process changes that may affect
these parameters.
5. For all packages except CEROIP (D10,D14),which has maximums of
CIN 9.5 pF, CoUT 8 pF.
6. 'lest conditions assume signal transition time of3 us or less, timing reference levels of1.5V, input pulse levels of 0 to 3.0V, and outputloading
of the specified IOI)lOH, and CL = 20 pF.
7. tlJZCE, lHzWE> and tHZOE are specified with CL = 5 pF as in part (b)
in AC Thst Loads. 'fransition is measured ±200 m V from steady state
voltage. This parameter is gnaranteed and not 100% tested.
=
Min.
10
8
tRC
tAA
tLZOE
Max.
7B164-10
7B166-10
10
12
15
ns
8
8
0
0
8
5
0
2
0
8
8
0
0
8
6
0
2
10
10
ns
ns
0
0
ns
ns
10
ns
ns
5
0
7
0
3
6
0
7
ns
ns
ns
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. These parameters are gnaranteed and not
100% tested.
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate awritebygoing IDGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
CY7B164
CY7B166
Switching Waveforms
Read Cycle No. 1[10, 11]
IRC
'V
~Il'
ADDRESS
U)
:a:
lAA
-IoHA--=-!
DATA OUT
(
)(
ISCE
/W//////j W///////
~ ~,
IHA-
lAW
lSA
IPWE
~~
7L.
IHO .....
Iso
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA-IN VALID
DATA IN
_IHZWEj
-
IlZWE--j
HI GH IMPEDANCE
DATAoUT-------------«~__________N_O_T_E_15__________J»----~------~~wer-Down
H
X
X
HighZ
H
Data Out
Read
L
H
L
Data Out
Read
L
Data In
Write
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
Inputs/Outputs
Mode
Deselectlfuwer-Down
Ordering Information
Speed
(ns)
8
Ordering Code
CY7B164-8DC
CY7B164-8PC
10
12
15
Package
'JYpe
Operating
Range
Speed
(ns)
DIO
Commercial
8
P9
CY7B164-8VC
Vl3
CY7B164-1ODC
D10
CY7B164-1OPC
P9
CY7B164-1OVC
Vl3
CY7B164-100MB
010
CY7B164-1OLMB
L52
CY7Bl64-12DC
DIO
CY7B164-12PC
P9
CY7B164-12VC
Vl3
CY7B164-12DMB
D10
CY7B164-12LMB
L52
CY7B164-15DMB
D10
CY7B164-15LMB
L52
Shaded area contains preliminary information.
Commercial
10
Military
Commercial
12
Military
Military
15
CY7B166-8DC
Package
1Ype
DI4
CY7B166-8PC
P13
Ordering Code
CY7B166-8VC
Vl3
CY7B166-10DC
D14
CY7B166-1OPC
Pl3
CY7B166-1OVC
Vl3
CY7B166-10DMB
014
CY'7a166-10LMB
L54
CY7B166-12DC
DI4
CY7B166-12PC
Pl3
CY7B166-12VC
V13
CY7B166-12DMB
D14
CY7B166-12LMB
L54
CY7B166-15DMB
D14
CY7B166-15LMB
L54
Shaded area contains preliminary information.
2-212
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
CY7B164
CY7B166
MILITARY SPECIFICATIONS
•
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tAA
7,8,9, 10, 11
tOHA
7,8,9, 10, 11
tACE
7, 8, 9, 10, 11
tOOE[l7]
7,8,9,10, 11
WRITE CYCLE
tSCE
7,8,9,10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7,8,9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7,8,9, 10, 11
Note:
17. 7B166 only.
Document # 38-A-00015-F
2-213
CY7C164
CY7C166
CYPRESS
SEMICONDUCTOR
16,384 X 4 Static RIW RAM
Data on the four input/output pins (1100
through 1103) is written into the memory
location specified on the address pins(Ao
throughA 13)·
Features
Functional Description
• Automatic power-down when
deselected
• Output Enable (OE) feature (7CI66)
• CMOS for optimum speed/power
• Highspeed
-'- tAA = 10 ns
• Low active power
- 880mW
• Low standby power
- 220mW
• TIL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
TheCY7C164 andCY7C166 arehigh-performance CMOS static RAMs organized
as 16,384 by 4 bits. Easy memory expansionis.£!!>vided by an active LOW chip enable (CE) and three-state drivers. The
CY7C166 has an active low output enable
(OE) feature. Both devices have an automatic power-down feature, reducing the
power consumption by 65% when deselected.
Readingthe device is accomplished bytakingchipenable(CE) LOW (and OELOW
for 7CI66), while write enable (WE) remains IDGH. Under these conditions the
contents of the memory location specified
on the address pins will appear on the four
data 110 pins.
Writingto the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW (and the output enable (OE) is LOW for the 7CI66).
The 110 pins stay in high-impedance state
when ch~nable (CE) is IDGH, or write
enable (OE) is IDGH for 7CI66). A die
coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
SOJ
Top View
DIP
Top View
Vee
""'-
As
As
Vee
1
""'As
A7
As
As
Ao
A,
As
Ao
A,.
A"
NC
A.
A,
Ao
7
NC
1/0.
1/0.
1/0,
1/0.
1/0.
vo,
GND
C164·2
vOo
DE
VOo
WE
GND
WE
C1644
C164-3
A1
A2
1/°3
~
~
A7
LCe
Lee
Top View
1/°2
Top View
.:r!i!i~
0
:f:? ;1>',,'1/°1
As
A7
1/0 0
As
As
A,.
A"
A,.
A13
CE
3 2 ~1222120
4
5
6
7
B
9
~)
19
18
7C164 17
16
15
14
10111213
1~~i!H
(7C166 ONLy)
As
As
A.
A,
A7
As
As
Ao
A,.
Al1
A12
A,.
vo"
vo.
vo,
CE
C164-5
32,1 , 2827
26
25
6
24
7
23
B
7C166 22
9
21
10
20
11
19
12
18
. 1314151617
4
5
I~~~I~
g
NC
""'AsA.
A,
A.
Vo"
Vo.
VO,
C164-6
C164-1
Selection Guide[!]
7CI64-10 7Cl64-12
7CI66-1il 7CI66-12
7CI64-15
7CHi6-l5
7CI64-25
7C166-25
7C164-35 7CI64-45
7C166-35 7CI66-45
MaximumAccess Time (ns)
10
12
15
20
25
35
45
Maximum Operating Current (rnA)
160
160
115
80
70
70
40/20
40/20
40/20
40/20
20/20
20/20
50
20/20
Maximum Standby Current (rnA)
. .
Shaded area contams prehmmary information.
Note:
1.
7CI64-20
7C166-20
For military specifications, see the CY6C164NCY7C166Adatasheet.
2-214
CY7C164
CY7C166
~
~~PRESS
_ . ' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. Ambient Thmperaturewith
Power Applied ....................... Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
in High Z State ........................
DC Input Voltage ......................
65°C to +150°C
55°C to +125°C
- O.5V to + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 200 rnA
Operating Range
- O.5V to + 7.0V
- 3.0Vto +7.0V
Range
Commercial
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
Electrical Characteristics Over the Operating Range
7C164-10
7CI66-10
Parameters
Description
Thst Conditions
Min.
Max.
9. 4
7CI64-U
7CI66-U
Min.
Max.
2.4
7CI64-15
7C166-15
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min.,
IOL=8.0rnA
Vm
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW VOltagel2]
-3.0
0.8
-3.1)
0.8
-3.0
0.8
V
0.4
2.4
Units
0.4
V
0.4
V
IIX
Input Load Current
GNDsVIsVee
-10
+10
-10
+10
-10
+10
Ioz
Output Leakage
Current
GNDsVosVee,
Output Disabled
~1O
+10
-10
+10
-10
+10
IlA
IlA
los
Output Short
CircuitCurrent[3]
Vee = Max.,
VOUT = GND
-350
':"3.50
-350
rnA
Icc
Vee Operating Supply
Current
Vee = Max.,
lOUT = ornA
160
160
115
rnA
ISBI
AutomaticCE
Power-DownCurrentl4]
Max. Vee,CE;:::. Vm,
Min. Duty Cycle = 100%
40
40
40
rnA
AutomaticCE
Power-DownCurrent[4]
Max. Vee,
20
20
rnA
CE;:::. Vee - 0.3y,
ISB2
VIN;:::' Vee - O.3V
orVIN S O.3V
Shaded area contams advanced informatIOn.
2-215
..
..
20
•
CY7C164
CY7C166
Electrical Characteristics Over the Operating Range(continued)
7Cl64-20
7C166-20
Description
Parameters
'Thst Conditions
VOH
Output HIGH Voltage
Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min.,
IoL= 8.0 rnA
Vrn
VIL
Input HIGH Voltage
Input LOW Voltagel3)
IIX
Input Load Current
Ipz
Min.
7Cl64-25,35
7C166-25,35
Max.
2.4
Min.
Max.
7Cl64-45
7Cl66-45
Min.
0.4
0.4
Max.
Units
2.4
2.4
V
0.4
V
V
2.2
Vee
2.2
Vee
2.2
Vee
-3.0
0.8
-3.0
0.8
-3.0
0.8
V
GND 5. VI 5. Vee
-10
+10
-10
+10
-10
+10
Output Leakage
Current
GND 5. Va 5. Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
!1A
!1A
los
Output Short
CircuitCurrent[3)
Vee = Max.,
Vour = GND
-350
-350
-350
rnA
Icc
Vee Operating Supply
Current
Vee = Max.,
lour = ornA
80
70
50
rnA
IsBl
AutomaticCE
Power-DownCurrent[4)
Max. Vee, CE ~ VIH,
Min. Duty Cycle = 100%
40
20
20
rnA
ISBl
AutomaticCE
Power-DownCurrent!4)
Max. Vee,
CE~ Vee - 0.3V;
VIN ~ Vee - O.3V
or VIN 5. 0.3V
20
20
20
rnA
Capacitance [5)
Description
Parameters
CIN
InputCapacitance
Caur
OutputCapacitance
'Thst Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Notes:
2. VIL min. = -3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4. A pull·up resistor to V cc on the CE input is required to keep the device deselected during Vee power-up, otherwise ISBwill exceed valnes
given.
5.
Max.
Units
10
pF
10
pF
Testedinitiallyand after any design or process changes that may affect
these paramc!ters.
AC Test Loads and Waveforms
5V<>-----....,
R14BHl
R14B1n.
5V 0 0 - - - - - '__,
ALL INPUT PULSES
OUTPUT
OUTPUT
30pF
I
R2
255n.
INCLUDING
JIGAND _
SCOPE -
-=
5PFI
INCWDING
JIGAND _
SCOPE -
(a)
Equivalent to:
3,OV
R2
255n.
-=
C164-7
(b)
THEvENIN EQUIVALENT
167.0.
OUTPUT 00---"',""1''0---000 l.73V
2-216
----._=-----.L
GND _....;;10;';;%;:1("
C164-B
CY7C164
CY7C166
~~PR£SS
.iF SEMICONDUCTOR
Switching Characteristics
Parameters
Over the Operating Rangel6]
7CI64-10
7C166-10
Description
Min.
READ CYCLE
Read Cycle Time
tRC
Max.
10
tAA
Address to Data Valid
tOHA
Output Hold
Change
from
7CI64-12
7CI66-12
Min.
3
Min.
Max.
15
12
12
10
Address
Max.
7CI64-IS
7CI66-IS
Min.
Max.
20
Units
ns
20
15
3
3
7CI64-20
7C166-20
5
ns
ns
tACE
CE LOW to Data Valid
10
12
15
20
ns
tOOE
OE WW to Data Valid 7C166
5
6
10
10
ns
tLZOE
OE WW to LowZ
7Cl66
tHZOE
OE HIGH to High Z
7C166
tLZCE
CE LOW to Low Z(7)
tHzCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
3
0
0
5
7
3
2
5
8
3
7
0
0
10
8
5
8
0
12
ns
3
8
ns
ns
0
20
15
ns
ns
ns
WRITECYCLEl'J
twc
Write Cycle Time
10
12
15
20
ns
tsCE
CE WW to Write End
8
15
ns
tAW
Address Set-Up to Write End
8
8
12
9
12
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
8
0
8
12
15
ns
tso
Data Set-Up to Write End
5
6
10
10
ns
tHO
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z(7)
2
tHZWE
WE WW to High Z[7, 8]
3
6
Shaded area contams advanced information.
2-217
5
6
5
7
DS
7
ns
•
CY7C164
CY7C166
&;~PRK§
~I SEMICONDUCTOR
Switching Characteristics
Parameters
Over the Operating Range!6]
7Cl64-25
7Cl66-25
Description
Min.
READ CYCLE
Read Cycle Time
tRC
7Cl64-35
7C166-35
Max.
25
Min.
7Cl64-45
7C166-45
Max.
Max.
Units
45
ns
45
35
25
Min.
ns
tAA
Address to Data Valid
tOHA
Output Hold from Address
Change
tACE
CE LOW to Data Valid
25
35
45
ns
tOOE
OE LOW to Data Valid 7C166
12
15
20
ns
tLZOE
OE LOW to Low Z
7C166
tHZOE
OEHIGHtoHighZ
7C166
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
35
5
5
3
5
3
10
5
5
0
15
15
20
15
ns
ns
0
25
20
ns
ns
5
0
CE HIGH to Power-Down
tpD
WRITECYCLEIYJ
ns
3
12
10
ns
ns
Write Cycle Time
20
25
40
ns
tsCE
CE LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
15
20
20
ns
tso
Data Set-Up to Write End
10
15
15
ns
tHO
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
5
tHZWE
WE LOW to High Z[7, 8]
twc
5
7
Notes:
6. Thst conditions assume signal transition time of 5 ns or less, tirningreference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading
of the specified IOlJlOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC
Thst Loads. 'fransition is measured ±500 mV from steady state voltage.
9.
2-218
ns
5
10
15
ns
The internal write time of the memory is defined by the overlap of CE
WW and WE Ww. Both signals must be LOW to initiate awrite and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
CY7C164
CY7C166
£
~~PRF.SS
~, SEMlCONDUCfOR
Switching Waveforms
€
Read Cycle No. 1[10, 11]
ADDRESS
IRC
1
V:;~ JXX *===============D=A=T=A=V=A=LI=D===========~
--~
DATA OUT
PREVIOUS DATA
lAA
C164-9
Read Cycle No. 2[10, 12]
IRC
~
/1(
~
lACE
OE
7CI66
)~
or'
100E
- - ILZOE--
HIGH IMPEDANCE
DATA OUT
ILZCE
Voc
SUPPLY
CURRENT
-1I---
f./////
IHZCE
~
DATA VALID
.'"
'-3
HIGH
IMPEDANCE
/
I---
Ipu
IpD
~ CC
I
50%
ISB
C164-10
Write Cycle No.1 (WE ControIled)[9, 13]
Iwc
ADDRESS
=:)~
)(
tsCE
~ ~ "-
/ W~ o/////m
lAW
IHA-
tPWE
lSA
)~
/~
!sD
DATA IN
";E
IHO
DATA-IN VALID
_IHZWEj
I--
ILZWE
--1
..J»--------« . . _____
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _ _
DA_T_A_U_N_D_E_FI_N_ED
_______
C164-11
Notes:
10.
11.
12.
13.
WE is HIGH for read cycle.
Device is contiuuously selected,CE ; VIL. (7C166: OE; VILalso).
Address valid prior to or coiucident with CE transition Ww.
7C1660uIy: Data IJOwill be high impedance ifOE; Vrn.
14. If CE goes HIGH simuItaneouslywith WE HIGH, theoutputremain,
ina high-impedance state.
2-219
•
CY7C164
CY7C166
~
~~PRESS
.....,., SEMlCCtIDUCTOR
Switching Waveforms
(continued)
Write Cycle No.2 (CE Controlled)[9,13,14)
lwe
--------------.;~
ADDRESS
- - -..1------- Isee
-----~
ct ----+-----------~
~
,-------~--------
ISO
DATAIN _ _ _ _ _ _ _ _ _
.1.....
DATA-IN VAUD
*_____
DATAI/O _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _:.,,:H;,:IG:;,.H:.,,:IM::;..PE=D;:A::,.N;,,:C;,:E:....._ _ _ _ _ __
C164-12
1YIJical DC and AC Characteristics
NO~EDSUPPLYCURRENT
VB. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
3]1.2
Icc
jl1.0
V
c
~ O.B
::;
:Ii
0.6
V
1.2
/
V
"'
.::: 1.0
w
::J
0 0.4
Vcc- 5.OV
VIN =5.0V
z
0.2
f---
0.0
ISB
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
-55
6.0
M
J
1.3
J
0
1.2
w
N
r--....
0.9
4.5
5.0
0
--
!z
1.4
SUPPLY VOLTAGE
a: 1.0
r-M
1.2
«
:;:
TA = 25°C
5.5
1.0
6.0
2.0
0
z
O.B 1/
0.6
-55
/'
/'
./
25
a
~
~
a
125
3.0
"
4.0
M
140
v
100
a:
Z
AMBIENT TEMPERATURE (OC)
2-220
M!
iii
Vcc= 5.0V
""
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.s 120
0
::;
............. ~
20
0.0
Vee = 5.0V
TA = 25°C
OUTPUT VOLTAGE
<"
1.6
...........
'"
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
O.B
4.0
125
40
NO~EDACCESSTIME
1.4
1.1
25
1il
5
o~
AMBIENT TEMPERATURE ("C)
NO~ZEDACCESS~
:;:
a:
0 1.0
z
80
~ 60
:Iia:
ISB
M!
§
w
::; 0.6
0.2
~120
!z 100
U
N
~ 0.4
~
~
8
c O.B
a:
w
~
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
80
II
60
/
Vcc= 5.0V
TA = 25°C
/
40
20
/
II
o
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C164
CY7C166
,~
~iE CYPRESS
.
-===-,
SEMICONDUCTOR
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTWADING
vs_ SUPPLY VOLTAGE
0
~
3.0
30.0
2.5
25.0
j
c 2.0
w
N
::::;
1.5
~ 15.0
z
1.0
~ 10.0
0
./
0.5
0.0
0.0
L--1.0
2.0
-----
3.0
SUPPLY VOLTAGE
4.0
5.0
5.0
WE
H
X
HighZ
L
H
L
L
/'
/
/
/
M
/
1.001----+-----ir-----::I
N
i
~ 0.751----t-:-:7"-"----ir-----i
Vcc=4.5V TA = 25°C
400
600
800 1000
0.501'-0---2'"'0,..----'3""0----'40
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
CY7C166 Truth Table
Mode
CE
WE
OE
Deselect!Power-Down
H
X
X
HighZ
Data Out
Read
L
H
L
Data Out
Read
Data In
Write
L
L
H
Data In
Write
L
H
H
HighZ
Write
Inputs/Outputs
Address Designators
Address
Name
Address
Function
CY7C164Pin
Number
CY7C166 Pin
Number
AS
X3
A6
A7
A8
A9
AI0
All
A12
A13
AO
Al
X4
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
X5
A3
X6
X7
Y5
Y4
YO
Yl
Y2
Y3
XO
Xl
20
9
19
20
21
22
A4
X2
21
23
A2
Jl
fil
1 1-
200
CY7Cl64 Truth Table
CE
VCC=5.0V
TA = 25°C
VIN= 0.5V
~
20.0
~
a:
NORMALIZED Icc vs_ CYCLE TIME
1.25
17
18
19
8
2-221
Inputs/Outputs
Mode
Deselect!lbwer-Down
•
CY7C164
CY7C166
.A~UCfOR
Ordering Information
Speed
(ns)
10
12
15
20
25
35
45
Ordering Code
Package
'JYpe
Operating
Range
Speed
(ns)
.Commercial
10
Ordering Code
Package
'J.Ype
Operating
Range
Commercial
CY7Cl64-:-:10DC
D10
CY7Cl66,..10DC
D14·
CY7Cl(l4-10LC
1.52
CY7Cl66-10LC
1.54
. CY7CI64":'10PC
P9
··CY7C166-1OPC
CY7C164-.10VC
VI3
CY7Cl66-1ovc
V13
CY7C164-12DC
D10
CY1C166-12DC
D14
CY7Cl64-12LC
1.52
cy7CI66,;;,12LC
1.54
Commercial
12
PI3 ..
CY7C164 ....12PC
P9
CY7Cl66...,I2PC
P13
CY7C164-12VC
Vl;!
CY7Cl66-12VC
V13
CY7C164-15DC
D10
CY7C166-15DC
D14
CY7C164-15LC
1.52
CY7C166-15LC
L54
CY7C164-15PC
P9
CY7C166-15PC
P13
CY7Cl64-15VC
V13
CY7C166-15VC
V13
CY7C164-20DC
DI0
CY7C166-20DC
D14
CY7C164-20LC
1.52
CY7C16~-20LC
L54
CY7Cl64-20PC
P9
CY7C166-20PC
P13
CY7Cl64-20VC
V13
CY7Cl64-25DC
DI0
CY7Cl64-25LC
Commercial
15
Commercial
20
CY7C166-;WVC
V13
CY7CI66-25DC
014
1.52
CY7C166-25LC
L54
CY7Cl64-25PC
P9
CY7C166-25PC
P13
CY7C164-25VC
V13
CY7C166-25VC
V13
CY7C164-35DC
DI0
CV7C166-35DC
D14
CY7C164-35LC
1.52
CY7C166-35LC
L54
CY7C164-35PC
P9
CY7C166-35PC
P13
CY7Cl64-35VC
V13
CY7CI66-35VC
V13
CY7Cl64-45DC
DI0
CY7C166-45DC
014
CY7C164-45LC
1.52
CY7C166-45LC
L54
CY7C164-45PC
P9
CY7C166-45PC
P13
CY7C164-45VC
V13
CY7C166-45VC
V13
Shaded area contains advanced information.
Commercial
25
Commercial
35
Commercial
45
Shaded area contains advanced information.
Document #: 38-00032-G
2-222
CommerCial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C164A
CY7C166A
CYPRESS
SEMICONDUCTOR
16,384 X 4 Static R!W RAM
Features
Functional Description
• Automatic power-down when
deselected
• Output Enable (OE) feature
(7C166A)
• CMOS for optimum speed/power
• High speed
-tAA=12ns
• Low active power
-93SmW
• Low standby power
-220mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C164A and CY7C166A are highperformance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion~ovided by an active LOW chip
enable (CE) and three-state drivers. The
CY7C166A has an active low output enable
(OE) feature. Both devices have an automatic power-down feature, reducing the
power consumption by 60% when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs arebothLOW(and the output
enable (DE) is LOW for the 7C166A).
Data on the four input/output pins (I/Oa
Logic Block Diagram
through I/03) is written into the memory
location specified on the address pins (Ao
through A13).
Reading the device is accomplished by taking chip enable (CE) LOW (and OE LOW
for 7C166A), while write enable (WE) remains HIGH. Under these conditions the
contents of the memory location specified
on the address pins will appear on the four
data I/O pins.
The I/O pins stay ~h-impedance state
when ch~nable (CE) is HIGH, or write
enable (OE) is HIGH for 7C166A).
A die coat is used to insure alpha immunity.
Pin Configurations
DIP
Top View
DIP
lbpView
Vee
Ao
As
A1
As
As
Po,.
A,
A,.
A"
A,.
A13
Ae
110.
110.
110,
110.
t:E
WE
GND
IlOo
Vee
Ao
A.
A.
A1
A.
As
Po,.
A,
As
A,.
A"
A,.
A,.
Ae
NO
I/O.
t:E
llE
110.
110,
110.
GND
WE
0164A-3
0164A-2
ua.
LeC
Top View
LeC
Top View
UO,
.f~~~
~~$<,
uo.
A1
As
A~
t:E
A"
A,.
A,.
WE
(llE)
(70166A ONLy)
3 2 ~,22212
4
5
6
7
8
9
As
1 Po,.
1 A,
70164A 17 Ae
1
110.
15 110.
14 110,
10111213
I~ ~ I~!f
0164A-4
0164A-l
Selection Guide[l]
Note:
For commercial specifications, see the CY7Cl64/CY7Cl66 datasheet
1.
2-223
3 2 ~,282~
NO
5
25 Ao
24 As
6
7
23 Po,.
8 70166A 22 A,
9
21 Ae
10
20
11
19
12
18
1;! 14 !.S1617
As 4
A1
As
As
A,.
A"
A,.
A,.
t:E
uo.
uo.
uo,
1~~!;1I~ !f
0164A-5
•
CY7C164A
CY7C166A
Si
~~PRF.SS
~, SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. - 65°C to +150 oo C
Ambient Thmperaturewith
Power Applied ........................ - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .........................
DClnputVoltage .......................
Output Current into Outputs (Low) ................. 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . .
(per MIL-SID-883, Method 3015)
> 2001 V
Latch-upCurrent. ... .. . .. .. . . . . . . . . . . . . . . . . . . .
>200 rnA
Operating Range
Ambient
Thmperature
Vee
- 55°C to +125°C
5V ± 10%
Range
- O.5V to + 7.0V
-3.0Vto+7.0V
Militaryl2)
Electrical Characteristics Over the Operating Rangef3)
7Cl64A-12
7C166A-12
Parameters
Description
.Mi....
Thst Conditions
7C164A~lS
7C166A-lS
7C164A-20
7C166A-20
Max. Min; Max. Min.
VOH
Output HIGH Voltage
V ce = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
V ce = Min., IOL = 8.0 rnA
VJH
Input HIGH Voltage
2.2
Vce
2.2
Vee
VIL
Input LOW Voltagef4)
-3.0
0.8
-3.0
IIX
Input Load Current
GND:5. VI:5. Vee
-10
+10
loz
Output Leakage
Current
GND :5. Vo:5. V ce,
Output Disabled
-10
+10
los
Output Short
CircuitCurrent(5)
Vee = Max., VOUT = GND
Icc
Vee Operating Supply
Current
Vce=Max.,
lOUT = ornA
ISBl
Automatic CE (6)
Power Down Current
IsB2
AutomaticCE(6)
Power Down Current
2.4
2.4
Max. Units
2.4
0.4
V
0.4
V
2.2
Vce
V
0.8
-3.0
0.8
V
.-10
+10
-10
+10
-10
.+10
-10
+10
ItA
ItA
0.4
-350
-350
-350
rnA
Military
170
160
100
rnA
Max. V ce, CE ~ VIH
Min. Duty Cycle = 100%
Military •
40
35
40
rnA
Max. Vee,
CE~ VIH - O.3V
VIN ~ Vee - 0.3Vor
VIN :5.0.3V
Military
20
20
20
rnA
i.
Shaded area contams advanced mformation.
Notes:
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
information.
4. VIL min; = - 3.0V for pulse durations less than 30 ns.
5.
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
6. A pull-up resistor to Vcc on the CE input is required to keep the device deselected during Vccpower-up, otherwise ISBWill exceed values
given.
2-224
CY7C164A
CY7C166A
=---.~
~iECYPRESS
"=Ji!JJ!!!ffii.'
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range(3)(continued)
7Cl64A-25
7C166A-25
Parameters
Description
Min.
Thst Conditions
Vee = Min., IOH
= - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
7Cl64A-35,45
7C166A-35,45
Max.
Units
0.4
V
2.2
Vee
V
-3.0
0.8
V
+10
Min.
Max.
VOH
Output HIGH Voltage
2.4
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltagef4)
-3.0
0.8
IIX
Input Load Current
GND S VI S Vee
-10
+10
-10
-10
+10
-10
0.4
+10
-350
-350
rnA
Military
100
100
rnA
Military
40
30
rnA
Military
20
20
rnA
Ioz
Output LeakageCurrent
GND S Vo s Vee, Output Disabled
Output Short
CircuitCurrentl5)
Vee = Max., VOUT = GND
Icc
Vee Operating Supply
Current
Vee = Max., lOUT = 0 rnA
ISB!
AutomaticCE[6)
Power Down Current
Max.VcoCE~Vrn
Automatic CE [6)
Power Down Current
ISB2
= 100%
Max. Vee,
CE~ Vrn - O.3V
VIN ~ Vee - 0.3Vor
VINSO.3V
V
fIA
fIA
los
Min. Duty Cycle
2.4
Capacitance [7)
Parameters
Description
CIN
InputCapacitance
CoUT
OutputCapacitance
Thst Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
Units
10
pF
10
pF
Note:
7. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
SV 0 - - -__" "
R1481Q
OUTPUTo---~~--~
30pF
I-=
INCLUDING
JIGAND
SCOPE (a)
Equivalent to:
5V~
OUTPUT
SpF
R2
25SQ
I-=
INCLUDING
JIGAND
SCOPE (b)
-=
R2
2SSQ
C164A-6
THEvENIN EQUIVALENT
16m
OUTPUT Oo---l\Ih""---oO 1.73V
2-225
C164A-7
•
CY7C164A
CY7C166A
Switching Characteristics
Over the Operating Rangel:3, 8)
'1CIMA~12 7Clfi4A,"'"1S 7Cl64A-20 7Cl64A-25 7Cl64A-35 7Cl64A-4S
1Cl6tiA-12 7C16tiA-lS 7C166A-20 7Cl66A-2S 7Cl66A-35 7Cl66A-4S
Parameters
Description
MIi;
Max.
Max.
Mia.
Min. Max. Min. Max. Mia. Max. Min. Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
AddressChange
12
3
12
tOOE
OE WW to Data Valid
(7CI66A)
6
tLZOE
OE LOW to Low Z
(7CI66A)
tHzOE
OE HIGH to High Z
(7CI66A)
CE LOW to Low Z[9)
tHZCE
CE HIGH to
High Z[9, 10)
tpu
CE LOW to Power-Up
tpo
CE HIGH to
Power-Down
....
45
ns
45
35
3
3
ns
ns
..
15
20
25
35
45
ns
7
10
12
15
20
ns
I' 0
0
35
25
3
3
'
CE WW to Data Valid
25
20
15
,3
tACE
tLZCE
20
15
12
3
3
3
3
ns
.
7
.
8
8
12
10
15
ns
1
;3
3
5
7
0
12
0
,
0
'.
0
5
15
10
20
15
5
5
8
8
0
0
20
20
ns
15
ns
ns
25
ns
."
WRITECYCLELllJ
twc
Write Cycle Time
i2
,,15'
20
20
25
40
ns
tsCE
CE WW to Write End
8
. 10
15
20
25
30
ns
15
20
25
30
ns
0
0
0
0
ns
0
0
0
0
ns
15
15
20
20
ns
10
10
15
15
ns
0
0
0
0
ns
tAW
Address Set·Up to
Write End
tHA
Address Hold from
Write End
tSA
Address Set-Up to
Write Start
9
'
., 0
0
0
0
.,
tPWE
WE Pulse Width
8
tso
Data Set-Up to
Write End
6
Data Hold from
Write End
0
tUWE
WE HIGH to Low Z[9)
;3
tHzWE
WEWWto HighZ[9, 10)
tHO'
10 '
.
.
.
l~<
',JO, L'·"
7
,
()
;3
6
'.'
7
5
5
5
,.
7
7
5
10
ns
15
ns
Shaded area contains advanced information.
Notes:
8. Thst conditions assume signal transition time of S ns or less, timing ref·
erence levels of 1.SV, input pulse levels of 0 to 3.0V, and output load·
ing of the specified IOl/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tIZCE for any given device. These parameters are guaranteed and not
100% tested.
10. tHZCE and tHZWE are specified with CL = S pF as in part (b) in AC
Thst Loads. Transition is measured ±SOO mV from steady state volt·
age.
11. The internal write time of the memory is defmed by the overlap of CE
WW and WE WW Both signals must beWW to initiate a write and
either signal can terminate a write by going mOH. The data input set·
up and hold timing should be referenced to the rising edge of the sig·
nal that terminates the write.
2-226
CY7C164A
CY7C166A
~
-.
~
~;CYPRF.SS
~, SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[12, 13]
ADDRESS
t
--~
DATA OUT
*- •
IRC
1
tM
PREVIOUS DATA V::
==*xx
*==============D=A=T=A=V=AL=I=D===========
Cl64A-8
Read Cycle No. 2[12, 14]
tRC
~I'\.
~
tACE
OE
"'-"
7C166
/1{
-
tLZCE
VCC
- - tHzCE
tLZOE--
HIGH IMPEDANCE
DATA OUT
~~~
IOOE
1////
~'\.'\.'\."
DATA VALID
HIGH
IMPEDANCE
/
_tpo
~tpu
~ CC
I
SUPPLY
CURRENT
50%
ISB
Cl64A-9
Write Cycle No.1 (WE Controlled)[ll, 15]
twe
ADDRESS
~~
)(
--/
!sCE
~ ~ t\.
/
~~
tAW
tHA-
tSA
tPWE
~~~
./'"
tHO ....
!so
DATA IN
~,(
)
DATA·IN VALID
f4--
tHZWE
j
-
tLZWE--1
HIGH IMPEDANCE
-.J)>----------«
. . _____
DATA 110 _ _ _ _ _ _ _ _
DA_I_A_U_N_D_E_FI_NE_D_ _ _ _ _ _ _
Cl64A-10
Notes:
12. WE is mGH for read cycle.
13. Device is continuously selected, CE = V IL. (7C166A OE = V IL also).
14. Address valid prior to or coincident with CE transition LOW.
15. 7C166A only: Data I/O will be high impedance if DE = Vrn.
2-227
CY7C164A
CY7C166A
£:~PRFSS
.~,
SEMlcnIDUClDR
Swit~hing Waveforms (continued)
Write Cycle No.2 (CE Controlled) [11, 15, 16]
~------------------------twc--------------------------~
ADDRESS
------_1----------- tSCE --------------.1
DE ----4-----------~
,-------~--------
WE
~
DATA IN
HIGH IMPEDANCE
DATAI/O
Cl64A-ll
Note:
16. IfCEgoesIDGHsimultaneousIywithWEIDGH,theoulputremaius
in a high-impedance state.
'iYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs.AMBffiNT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs.SUPPLYVOLTAGE
1.4
5l
Icc
13 1.0
V
Cl
~ 0.8
::;
~ 0.6
./
.
1.2
V
V
~
8
C
~
II:
!i
1.2
1.0
-
IS6
0.8
4.0
4.5
5.0
5.5
w
~
I- IS6
25
vs. SUPPLY VOLTAGE
VB.
1.3
1.1
N
I'---...
0.9
0.8
4~
4~
5~
--
TA = 25°C)
t---
~5
SUPPLY VOLTAGE (V)
6.0
z
0.8
0.6
-55
2.0
"'"
3.0
"
4.0
~14O
1 120
J1.4
w 1.2
::;
«
::;; 1.0
II:
0
1.0
OUTPUT VOLTAGE (V)
AMBffiNT TEMPERATURE
Cl
..............
0.0
VCC= 5.0V
TA = 25°C
...........
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.6
Cl 1.2
w
N
II:
125
'"
g 40
5 20
~
o o
NO~ZEDACCESSTDdE
1.4
~
Vcc-5.0V
V1N = 5.0V
AMBIENT TEMPERATURE (OC)
NORMALlZEDACCESS~
0 1.0
z
60
:J
SUPPLY VOLTAGE (V)
::;
~ 80
0.6
0.0
-55
6.0
100
II:
()
0.2
0.0
!zw
~
Z
0.2
J
l120
~
~ 0.4
0.4
OUTPUT SOURCE CURRENT
VB. OUTPUT VOLTAGE
./
/
./
{3
80
Z
Cii
60
5
40
o~
125
AMBIENT TEMPERATURE ("C)
2-228
100
~
l<:
VCC= 5.0V
25
ffi
I
II
o
... v
/
V
VCC= 5.0V
TA= 25°C
/
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C164A
CY7C166A
==-.:~
---'=
CYPRF..SS
,
SEMICONDUCfOR
'JYpical DC and AC Characteristics (continued)
1YPICALPOWER-ON CURRENT
vs. SUPPLY VOLTAGE
0
1YPICALACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
2.5
25.0
/
Cil
~
<::
c 2.0
w
~
:l:
N
::J
200
.
«
::;;
1.5
~ 15.0
az
1.0
w
c 10.0
a:
0.5
0.0
0.0
I..-1.0
2.0
,../'
3.0
./
4.0
5.0
5.0
/
Vcc=4.5V TA= 25°C
/
V
0.0 0
1 1-
200
400
WE
X
L
H
L
L
600
BOO 1000
0.501·"=0---2~0:------:!370-----'4O
CAPACITANCE (pF)
CY7C164A Truth Table
H
Vee = 5.0V
TA = 25°C
VIN =0.5V
/
SUPPLY VOLTAGE (V)
CE
...--
NORMALIZED Icc vs. CYCLE TIME
1.25
CYCLE FREQUENCY (MHz)
CY7C166A Truth Table
Inputs/Outputs
Mode
Mode
CE
WE
OE
Deselect!R>wer-Down
H
X
X
HighZ
Data Out
Read
L
H
L
Data Out
Read
Data In
Write
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
HighZ
Address Designators
Address
Name
Address
Function
A5
X3
1
1
A6
X4
2
2
3
CY7Cl64A
Pin Number
CY7C166A
Pin Number
A7
X5
3
A8
X6
4
4
A9
X7
5
5
AI0
Y5
6
6
A11
Y4
7
7
A12
YO
8
8
A13
Y1
9
9
AO
Y2
17
19
Al
Y3
18
20
A2
XO
19
21
A3
Xl
20
22
A4
X2
21
23
2-229
Inputs/Outputs
DeselectlPower-Down
CY7C164A
CY7C166A
£
_~PRF$
-=,
SEMIc::aIDucroR
Ordering Information
Speed
(ns)
12
1~
Ordering Code
Package
tYpe
cY7C164A-12DMB
010
CY7Cl64A...,12KMB
K73.
cY7Cl64A-12LMB
cY7Cl64A-l5DMB
L52
010·
CY7Cl64A-:-15KMB
K73
.CY7C164A-15LMB
1$2
CY7C164A-20DMB
010
CY7Cl64A-20KMB
K73
20
25
35
45
CY7C164A-20LMB
L52
CY7Cl64A-25DMB
010
CY7Cl64A-25KMB
K73
CY7C164A-25LMB
L52
CY7C164A-35DMB
010
CY7C164A-35KMB
K73
CY7C164A-35LMB
L52
CY7C164A -45DMB
010
CY7C164A-45KMB
CY7C164A-45LMB
Operating
Range
Speed
(ns)
Package
12
Military
15
Military
Military
cY1C166A-15DMB
D14
CY7C166A-15KMB
K73
cY7C166A.,..15LMB
L54
014
·cY7C.166A-15KMB
K73
25
Military
tYpe
·CY7C166A-15DMB
20
Military
Ordering Code
35
CY7C166A-15LMB
L54
CY7C166A-20DMB
014
CY7C166A-20KMB
K73
CY7C166A-20LMB
L54
CY7C166A-25DMB
D14
CY7C166A-25KMB
K73
CY7C166A-25LMB
L54
CY7C166A-35DMB
D14
CY7C166A-35KMB
K73
CY7C166A-35LMB
L54
CY7C166A-45DMB
014
K73
CY7C166A-45KMB
K73
L52
CY7C166A-45LMB
L54
Military
45
Shaded area contains advanced information.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
VOL
1,2,3
tRC
7,8,9, 10, 11
Vrn
1,2,3
tAA
7,8,9, 10, 11
VILMax.
1,2,3
tOHA
7,8,9, 10,11
tACE
tOOE[l7]
7,8,9, 10, 11
IJX
1,2,3
Ioz
1,2,3
los
1,2,3
WRITE CYCLE
Icc
1,2,3
twc
7,8,9, 10, 11
IsBl
1,2,3
tsCE
7,8,9,10,11
IsBl
1,2,3
tAW
7, 8, 9, 10, 11
tHA
7,8,9,10,11
tSA
7,8,9, 10, 11
tpWE
7,8,9,10,11
tso
7,8,9, 10, 11
tHO
7,8,9,10,11
Document#: 38-00113-A
Note:
17. 7C166Aonly.
2-230
7,8,9,10,11
Operating
Range
Military
Military
Military
Military
Military
Military
CY7C167
CYPRESS
SEMICONDUCTOR
16,384 X 1 Static R/W RAM
Features
Functional Description
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Highspeed
- 25ns
• Low active power
-275mW
• Low standby power
-83mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C167 is a high-performance
CMOS static RAM organized as 16,384
words by 1 bit. Easy memory expansion is
llrovided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C167 has an automatic power-down
feature, reducing the power consumption
by 67% when deselected.
Writingto the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the
input pin (D I) is written into the memory
location specified on the address pins (Ao
through A13).
Logic Block Diagram
Readingthe device is accomplished by takingthec!!!2..enable (CE) LOWwhilewrite
enable (WE) remains HIGH. Under these
conditions, the contents of the memory 10cationspecified on the address pins will appear on the data output (DO) pin.
The output pin stays in .!!!gIl-impedance
state when chi~nable (CE) is HIGH or
write enable (WE) is Law.
The 7C167 utilizes a die coat to insure aiphaimmunity.
Pin Configurations
DIP
LCe
Top View
'IbpView
~oo'"
e (ns)
MaximumOperating
Current(mA)
I Commercial
I Military
2-231
7C167-25
7C167-35
25
35
7C167-45
45
60
60
50
60
50
II)
:E
2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
-0.5Vto+7.0V
Range
Commercial
Military(1]
- O.5V to + 7.0V
- 3.0V to + 7.0V
Ambient
lemperature
O°Cto +70°C
Vee
5V± 10%
- 55°Cto +125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
7C167-25
Description
Parameters
lest Conditions
Min.
VOH
Output HIGH Voltage Vcc = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Max.
2.4
Vcc=Min.lloL = 12.0rnA Com'l
Mil
jIOL= 8.0 rnA
7C167-35
Min.
Max.
7C167-45
Min.
Max. Units
2.4
2.4
V
0.4
0.4
0.4
V
0.4
0.4
0.4
V
V
VIH
Input HIGH Voltage
2.0
Vee
2.0
Vee
2.0
Vcc
VIL
Input LOW Voltage
-3.0
0.8
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GND.sVI.sVee
-10
+10
-10
+10
-10
+10
loz
Output Leakage
Current
GND.sVo.sVcc,
Output Disabled
-50
+50
-50
+50
-50
+50
!lA
!lA
los
Output Short
CircuitCurrentl3]
Vee = Max., VOUT = GND
-350
rnA
Icc
Vee Operating
Supply Current
Vcc= Max.
lOUT = ornA
Com'l
50
rnA
AutomaticCEl4J
Power Down Current
Max. Vee,
Com'l
ISB
-350
-350
60
60
Mil
CE~VIH
50
20
20
15
rnA
20
Mil
Capacitance l5]
CIN
CoUT
Description
InputCapacitance
Output Capacitance
CoUT
Chip Enable Capacitance
Parameters
lest Conditions
TA = 25°C,f= 1 MHz,
Vcc= 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing informatioo.
3. Duration of the short circuit should not exceed 30 seconds.
4.
5.
2-232
Max.
10
10
5
Units
pF
pF
pF
A pull-up resistor to V cc on the CE input is requited to keep the device deselected duringVccpower-up, otherwise IsBwi\lexceedvalues
given.
Tested initially and after any design or process changes that may affect
these parameters.
=;-
jiPRFSS
~
CY7C167
SEMJCC:WUCTOR
AC Test Loads and Waveforms
Rl 329Q
0UTP~O--30-pf
Rl 329
~
~:,~ l~j:.
_ _(48DO_
..MIL,
INCLUDING
J~~=
(a)
Equivalent to:
=
(256Q MIL)
INCLUDING
ALL INPUT PULSES
3'W~00%
GND
(2550 MR.)
Jr~~=
(b)
=
~
10%
S.5ns
SSns
CI67-4
C167-5
THEvENIN EQUIVALENT
1250
OUTPUT 0 0 - -............- - _ 0 1.9OV
1670
OUTPUT 00--""'''.''''..'''---00 1.73Y
Military
Commercial
Switching Characteristics Over the Operating Range[2. 6]
7C167-25
Parameters
Description
Min.
Max.
7C167-35
Min.
7C167-45
Max.
Units
30
40
ns
ns
ns
35
40
ns
Max.
Min.
READ CYCLE
tRC
Read Cycle Time
25
25
Com'l
Mil
tM
Address to Data Valid
30
40
35
40
25
Com'l
Mil
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
tHZCE
tpu
tpD
3
3
25
rn LOW to Low Z[7J
rn HIGH to High Z [7.8]
rn LOW to Power Up
rn HIGH to Power Down
5
45
35
5
0
25
ns
ns
0
25
20
ns
ns
5
20
15
0
ns
3
30
ns
WRITE CYCLE[9]
twc
Write Cycle Time
25
30
40
ns
tsCE
rn LOW to Write End
25
30
40
ns
tAW
Address Set-Up to Write End
25
30
40
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
15
20
20
ns
tSD
Data Set-Up to Write End
15
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z [7. 8]
WE HIGH to Low Z [7]
0
tLZWE
20
15
Notes:
6. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of I.sv, input pulse levels of 0 to 3.0V and output
loading of the specified IOJIIoH and JO..pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCB for any given device.
8. tHZCE and tHZWB are specified with CL = 5 pF as in part (b) of AC
Thst Loads. 'transition is measured :!:SOO mV from steady state
voltage.
0
9.
10.
11.
12.
13.
2-233
20
ns
ns
0
The internal write time of the memory is defined by the overlap ofCE
LOW and Wi:i LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input set·
up and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
Wt; is HIGH for read cycle.
Device is continuously selected,
= VIL'
Address valid prior to or coincident with
transition LOW.
IfCEgoesHIGHsimultaneouslywith Wi:iHIGH, the output remains
in a high-impedance state.
rn
rn
en
:E
________
HIGH
IMPED~E
i,----C167-6
2-234
CY7C167
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [9, 13]
~------------------------ twe ------------------------~~
ADDRESS
tsCE ------~
------0-1-------
CE
DATA IN
----~----------~
,-------4---------
----------.. '---+----------- Iso ------------......
DATA-IN VALID
IHZWE
--I
~~~~I-----------H-IG-H-I-M-P-ED-A-N-C-E-____________
~
DATAOUT ______________________________
DATA UNDEFINED
C167-9
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
'"
(J)
1.2
Icc
jl1.0
V
Cl
~
O.B
:::J
~ 0.6
V
V
./
1.2
~
8
C
1.0
O.B
~
-----
0.0
4.0
4.5
5.0
0.2 I- ISB
f----5.5
0.0
-55
6.0
1.4
1.3
J.
Cl
w 1.2
Cl
N
1.1
z
1.0
0
.............
r---.......
0.9
0.8
4.0
4.5
5.0
TA = 25°C
-.... r-5.5
SUPPLY VOLTAGE (V)
40
25
125
g
20
!:i
10
o~
""
0
0.0
6.0
~ 150
1.4
!Z
~
125
z
O.B 17
/
a:
a
/'
BO
~
z 75
125
AMBIENT TEMPERATURE (0C)
2-235
3.0
"
4.0
I
/
VCC= 5.0V
TA = 25°C
1ii
Vcc= 5.0V
25
2.0
/
~ 100
L
w
N 1.2
:::J
«
::;;
a: 1.0
0
"i'..
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.6
0.6
-55
1.0
VCC= 5.0V
~A=25°C
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
~
a:
gj
o
r-....
AMBIENT TEMPERATURE rC)
SUPPLY VOLTAGE (V)
:::J
Vcc- 5.0V
VIN=5.0V
z
ISB
50
a:
:;)
~ 0.4
0.2
!Zw
w
~ 30
~ 0.6
a:
~ 0.4
J
~
<60
.s
OUTPUT SOURCE CURRENT
vS.OUTPUTVOLTAGE
~
50
!:i
o
25
I
II
o
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
4.0
f:t;z
CY7C167
- CYPRF.SS
~"
SEMlcaIDucroR
1YPical DC and AC Characteristics (continued)
TYPICALPOWER·ON CURRENT
VS. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTWADING
3.0
.,.s
2 .5
0
...!!0
~
2.0
25.0
g 15.0
0.5
I.--- -"
0.0
0.0
1.0
2.0
3.0
./
4.0
(os)
(mA)
25
60
35
45
60
50
o
~
j
1000
5.0
0.81·'=0--~2=0--~3~0:---~40
CYCLE FREQUENCY (MHz)
Package
'JYpe
Operating
Range
CY7CI67·25PC
P5
Commercial
CY7CI67·25DC
D16
CY7CI67·25LC
LSI
CY7CI67·25VC
V5
CY7C167·35PC
P5
Ordering Code
Vee = 5.0V
TA = 25°C
Vee =0.5V
az
~ 10.01----f-7--+
SUPPLY VOLTAGE (V)
Ord'
enn~ I n Iionnat'Ion
Speed
Icc
1.1
Jl
20.01---+...,...-+--+rJC--+---1
~
:::; 1.5
a:
az 1.0
NORMALIZED Icc VI. CYCLE TIME
30.0 r---.---.---,---.---,
CY7C167·35DC
D6
CY7C167·35LC
LSI
CY7C167·35VC
V5
CY7C167-45PC
P5
CY7C167·45DC
D6
CY7C167-45LC
LSI
CY7C167·45VC
V5
CY7CI67·45DMB
D6
CY7C167·45LMB
LSI
Commercial
Commercial
Military
2-236
·
~
~=CYPRESS
_ . F SEMICONDUcrOR
CY7C167
MILITARY SPECIFICATIONS
Group A Subgroup Testing
•
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IJX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISH
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9,10,11
toHA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7,8,9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7,8,9, 10, 11
tSD
7,8,9, 10, 11
tHD
7, 8, 9, 10, 11
Document#: 38-00033-D
2-237
CY7C167A
CYPRESS
SEMICONDUCTOR
16,384 X 1 Static RAM
Features
Functional Description
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Highspeed
-15ns
• Low active power
-275mW
The CY7C167A is a high-performance
CMOS static RAM organized as 16,384
words by 1 bit. Easy memory expansion is
llrovided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C167Ahas an automatic power-down
feature, reducing the power consumption
by 67% when deselected.
Writingto the device is accomplished when
the chip select (CE) andwriteenable (WE)
inputs are both LOW. Data on the input
pin (DI) is written into the memory location specified on the address pins (Ao
through A 13).
• Low standby power
-83mW
• TTL-compatible inputs and outputs
• Capable ofwithstanding greater than
2001V electrostatic discharge
Readingthe device is accomplished bytak~the chip enable (CE) LOW, while
(WE) remains HIGH. Under these condintions,the contents of the locationspecified on the address pins will appear on the
data output (DO) pin.
The output pin remains in a high-impedance state when chip enable is HIGH, or
write enable (WE) is LOW.
A die coat is used to insure alpha immunity.
• VIHofl.2V
Logic Block Diagram
Pin Configurations
DIP
Top View
Vec
A.
01
Ao
Al
A2
00
Ao
A..
A,
A'3
A.
A"
A,
A11
Po"
A,.
A,;
A,;
A,;
A,;
DO
A7
WE
01
GNO
CE
~
C167A-2
LCe
As
Top View
<~~;
CE
Ao
WE
A,
Po"
"""
(0
en
0
....
('II
A,;
A,;
(I')
ct:<2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
(Above which the useful life may be impaired. Foruser guidelines,
not tested.)
Storage Temperature ................. Ambient Temperaturewith
Power Applied ....................... Supply Voltage to Ground Potential
(Pin 20 to Pin 10) . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Outputs
in High ZState ........................
DC Input Voltage ......................
Electrical Characteristics
Parameters
65°Cto +150°C
55°Cto +125°C
Operating Range
- O.5V to + 7.0V
Range
Commercial
Militaryll]
- O.5V to +7.0V
- 3.0V to + 7.0V
Ambient
temperature
Vee
O°Cto +70°C
5V± 10%
- 55°Cto +125°C
5V± 10%
Over the Operating Rangel2]
Description
test Conditions
VOH
Output High Voltage
Vee = Min.,loH
= -4.0 rnA
VOL
Output Low Voltage
Vee = Min.,
IoL = 12.0 rnA, 8.0 rnA Mil
Vrn
Input High Voltage
VIL
Input Low Voltagel3]
7C167A-15
7C167A-20
7C167A-25
Min.
Min.
Min.
Max.
2..4
Max.
2.. 4
0.4
2.2
Max.
Units
0.4
V
V
2.. 4
V
0.4
Vee
0.8
2.2
Vee
2.2
- 0.5
-0.5
0.8
- 0.5
Vee
0.8
V
IIX
Input Load Current
GND.:5.VI.:5.Vee
-10
+10
-10
+10
-10
+10
loz
Output Leakage
Current
GND.:5.Vo.:5.Vee
Output Disabled
-10
+10
-10
+10
-10
+10
tAA
tAA
los
Output Short
CircuitCurrend4]
Vee = Max., VOUT = GND
-350
-350
rnA
Icc
Vee Operating
Supply Current
Vcc=Max.,
lOUT = ornA
Com'l
rnA
AutomaticCE
Power-DownCurrent[5]
Max. Vee,
CE~ Vrn
Com'l
IsB
-350
90
Mil
40
Mil
7C167A-35
Parameters
Description
test Conditions
Min.
VOH
Output High Voltage
Vee = Min., IOH
= -4.0 rnA
VOL
Output Low Voltage
Vee = Min.,
IOL = 12.0 rnA, 8.0 rnA Mil
Vrn
Input High Voltage
VIL
Input Low Voltagel3]
Max.
2.. 4
80
60
80
70
40
20
40
20
7C167A-45
Min.
Max.
Units
0.4
V
V
2 .. 4
0.4
2.2
rnA
2.2
V
- 0.5
Vee
0.8
-0.5
Vee
0.8
V
IIX
Input Load Current
GND.:5.VI.:5.Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GND.:5.Vo.:5.Vee
Output Disabled
-10
+10
-10
+10
tAA
tAA
los
Output Short
CircuitCurrentl4]
Vee = Max., VOUT
-350
rnA
Icc
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
Com'l
60
50
rnA
Mil
60
50
AutomaticCE
Power-DownCurrent[5]
Max. Vee,
Com'l
20
15
CE~ Vrn
Mil
20
20
ISB
= GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. VJLmin. = -3.0V for pulse durations less than 30 ns.
4.
5.
2-239
-350
rnA
Duration of the short circuit should not exceed 30 seconds.
A pull-up resistor to Vcc on the CE inpnt is required to keep the device dcselectedduringVccpower-np, otherwise ISBWiII exceed values
given.
:i.APRFss
~..
CY7C167A
SEMICONDUCTOR
Capacitance [6]
Parameters
ClN
CoUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Vee=5.0V
Max.
Units
10
10
pF
pF
pF
Chip Enable Capacitance
CcE
AC Test Loads and Waveforms
Rl329!l
(481!lMIL)
R1329!l
(48HIMIL)
5V
5Vo---~_.,
OUTPUT
6
ALL INPUT PULSES
3'~~~
10%
OUTPUT
GND
R2
30pF I
INCLUDING
JIGAND _
SCOPE -
5PFI
INCWDING
JIGAND _
SCOPE -
202!l
(255!lMIL)
-=
(a)
Equivalent to:
R2
202!l
(255!lMIL)
..s.5ns
-=
Cl67A-5
Cl67A-4
(b)
THEVENIN EQUIVALENT
125!l
OUTPUT 00----"'+"'
..._._--000 1.9V
OUTPUT
167!l
a.O---'Yy•.,.,'_ _--ao 1.73V
Military
Commercial
Switching Characteristics
Over the Operating RangeJ:2, 7]
7C167A-15
Parameters
Description
Min.
Max.
7C167A-20
7C167A-25
7C167A-35
7C167A-45
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max. Units
READ CYCLE
Read Cycle Time
Com'l
tM
Address to Data Valid
Mil
Com'l
tOHA
Mil
Data Hold from AddressChange
tRe
tACE
tLZCE
tHzCE
tpu
CE LOW to Power-Up
0
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
tHZWE
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WEWWto HighZ[8, 9]
tLZWE
WE HIGH to Low Z[8]
tSD
tHD
5
8
25
0
15
35
0
20
0
20
ns
45
ns
ns
5
15
15
ns
ns
ns
25
ns
0
20
ns
ns
40
5
5
10
ns
40
35
5
5
8
40
40
30
25
5
20
15
30
35
25
20
5
5
5
Write Cycle Time
20
15
CE LOW to Data Valid
CE LOW to Low Z[8]
CE HIGH to High Z[8, 9]
CE WW to Write End
25
25
20
CE HIGH to Power-Down
tPD
WRITE CYCLE[lO)
twe
tSCE
tAW
tHA
tSA
tpWE
20
15
15
12
12
20
20
20
20
25
40
ns
15
15
25
25
30
30
0
0
12
10
0
0
0
15
10
0
0
0
15
10
0
0
0
20
15
0
0
0
20
15
0
ns
ns
ns
7
7
5
5
7
5
ns
ns
ns
15
10
5
ns
5
ns
ns
Note.:
6.
7.
8.
Thsted initially and after any design or process changes that may affect
these parameters.
Thst conditions assume sigoal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
At any given temperature and voltage condition, tHZ is less than ILZ
for any given device.
tHZCE and tHZWE are tested with CL = 5 pF as io part (b) of AC Thst
Loads. Thansition is measured ±500 m V from steady state voltage.
10. The internal write time of the memOlY is defined by the overlap of CE
LOW and WE
Both sigoal must be WW to initiate a write and
either signal can terminate awrite by goinglllGH. The data input setupandholdtimingshouldbereferencedtotherisingedgeofthesigoal
that terminates the write.
9.
2-240
ww.
·
'~PRESS
CY7C167A
*
- . F SEMICONDUCfOR
Switching Waveforms
~
Read Cycle No. 1[11, 12]
tRC
ADDRESS
---~
tAA
----------.j _---
--l'"
•
•
------------~-H-A--~I
+'~x~x~- .~--------------------DATA OUT
PREVIOUS DATA VALID
DATA VALID
..
--------------------~~~~
--------------------------
C167A-6
Read Cycle No. 2[11, 13]
tRC
~,
~
tACE
-tLZCE-
HIGH IMPEDANCE
DATA OUT
_
Vee
tpu_
SUPPLY
CURRENT
-
1////
tHZCE-
DATA VALID
I"'"
HIGH
IMPEDAN CE
-tpo _
~ Ii" 50%
50%~
f - - - I CC
~I SB
C167A-7
Write Cycle No.1 (WE Controlled) [10]
twc
ADDRESS
: )~
{
tsCE
~~ ~'"
/ ~ W///&
tAW
tHA-
tSA
tPWE
~~
~
tso
DATA IN
~{
tHO -
)(
DATA-IN VALID
--j
»---------« . ._____
_tHZWE_1
I--
tlZWE
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _ _D_A_T_A_U_N_D_E_FI_N_E_D_ _ _ _ _ _ _ _
C167A-B
Notes:
11. WE is high for read cycle.
12. Device is continuously selected, CE ~ VII.'
13. Address valid prior to or coincident with CE transition LOW.
14. IfCEgoesffiGHsimultaneouslywithWEHIGH,theoutputremains
in a high-impedance state.
2-241
'APRESS
~
CY7C167A
SEMICONDUCTOR
Switching Waveforms
(continued)
Write Cycle No.2 (CE Controned) [10, 14]
i4------------twc----------'----.i
ADDRESS
---.~----~~-----~
CE
----+-------------~
14----1----DATA IN
--------------~
ISD - - - - - -. .
DATA-IN VALID
IHZWE
DATA I/O
,-------~--------
---I
--------------------...)1
HIGH IMPEDANCE
DATA
>--------------UNDEFINE~
C167A-9
'JYpicaJ DC and AC Characteristics
NORNUUAZEDSUPPLYCURRENT
NORNUUAZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
!l! 1.2
lee
jl1.0
V
o
~ 0.8
::::i
~ 0.6
V
V
./
vs. AMBIENT TEMPERATURE
1.2
ID
.::: 1.0
0.2
w
~ 30
4.5
5.0
5.5
SUPPLY VOLTAGE
158
25
125
AMBIENT TEMPERATURE (0C)
M
~
10
o
0
"- t\..
o
1.0
j
0
1.2
w
1.2
:::J
«
::;:
~«
::;:
«' 150
a:
0
z
I-
1.4
c
.....
N
1.1
1.0
0.9
0.8
4.0
"'
t......
4.5
TA = 25°C
........ t--
5.0
a: 1.0
5.5
SUPPLY VOLTAGE M
6.0
0
z
0.8 ~
0.6
-55
"
4.0
M
VS.
§.
1.3
3.0
OUTPUT SINK CURRENT
OUTPUT VOLTAGE
VS. AMBIENT TEMPERATURE
1.6
j
2.0
OUTPUT VOLTAGE
NORNUUAZED ACCESS TIME
NORNUUAZEDACCESSTDKE
SUPPLY VOLTAGE
VS.
1.4
Vee=5.0V
~A=25°C
@ 20
Vcc- 5.0V
VIN= 5.0V
0.0
-55
6.0
~
::J
0.4
0.2
158
50
U
~
z
i'...
----- "
!z
~
~ 40
:::J 0.6
o~
~60
Icc
o8 0.8
a:
~ 0.4
0.0
4.0
I----
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
/
zw
~ 100
~
G
~
Vee = 5.0V
I::J
z
Cil
~
o
25
125
AMBIENT TEMPERATURE (0C)
2-242
125
/
75
50
25
Vcc= 5.0V
TA = 25°C
/
oII
0.0
v
1.0
2.0
I
I
3.0
4.0
OUTPUT VOLTAGE M
5.0
·-
,~PRFSS
~F
CY7C167A
SEMICONDUClDR
lYPical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
VS. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING
0
2.5
.s
Jl
~w
~
(jj'
.2-
::: 20.0 I--t--t-~""--+----!
0
w 2.0
::J
N
<
CE
As
A7
As
As
WE
A'D
Al1
Cl681
19
2 L'
3
18
4
17
5 7Cl68 16
67018915
7
14
13
B
C1682
A2
A,
As
1/00
1/0,
1100
9101112
C1663
1~~I~g
Selection Guide
7CI68-25
7C169-25
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
25
I Commercial
I Military
90
2-245
7CI68-35
7C169-35
35
90
90
7C169-40
40
70
7C168-45
45
70
70
70
•
CY7C168
CY7C169
~CYPRESS
===..
-:;;;;;;;;,...
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. Ambient Thmperaturewith
PowerApplied....................... Supply Voltage to Ground Potential
(Pin 28 to Pin 14) . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
65°Cto +150°C
55°Cto +125°C
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ....................... . . . .. > 200 rnA
Operating Range
Ambient
Thmperature
- O.5V to + 7.0V
Range
Commercial
Militaryl!]
- O.5Vto +7.0V
- 3.0V to + 7.0V
O°Cto + 70°C
Vee
5V± 10%
- 55°Cto + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
Parameters
Description
Thst Conditions
VOH
Output High Voltage
Vee = Min., IOH = -4.0 rnA
VOL
VIH
Output Low Voltage
Input High Voltage
Vee = Min., IOL = 8.0 rnA
VIL
Ill{
Input Low Voltage
Input Load Current
Ioz
Output Leakage
Current
los
Output Short
CircuitCurrent[3]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
ISB!
AutomaticCE
Power-Down Current
Max. Vee,
CE2VIH
AutomaticCE
Power-DownCurrent
Max. Vee,
CE2 Vee - 0.3 V
ISB2
7C168-2S
7C169-2S
Min.
Max.
2.4
7C168-3S
7C169-3S
Min.
Max.
2.4
0.4
2.0
-3.0
7C168-4S
7C169-24S
Min.
Max.
0.4
Vee
0.8
2.0
-3.0
Units
2.4
Vee
0.8
2.0
-3.0
V
0.4
V
Vee
0.8
V
V
GND~VI~Vee
-10
10
-10
10
-10
10
GND~Vo~Vcc,
-50
50
-50
50
-50
50
J.IA.
J.IA.
Output Disabled
-350
-350
-350
rnA
Com'l
Mil
90
70
90
70
70
rnA
Com'l
20
20
15
rnA
20
20
Mil
Com'l
11
Mil
11
11
20
20
rnA
Capacitance [4]
Parameters
CIN
CoUT
Description
Thst Conditions
Max.
Units
InputCapacitance
Output Capacitance
TA = 25°C,f= 1 MHz,
10
pF
Vee=5.0V
10
pF
Notes:
1. TAisthe "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3.
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect
these parameters.
2-246
CY7C168
CY7C169
~~
--=-,
.
-:~PRESS
SEMICONDUCTOR
AC Test Loads and Waveforms
Rl48HJ
5Vo----_....,
Rl481Q
5Vo----_....,
OUTPUTo---.....---t
OUTPUTo---.....---t
FI
30 P
5PFI
R2
255!J
INCLUDING
JIGAND _
SCOPE -
R2
255!J
GND
90%
10%
.5.5n8......
INCLUDING
JIGAND _
SCOPE -
(a)
THEvENIN EQUIVALENT
Equivalent to:
ALL INPUT PULSES
3.0V~
J.Cl685
Cl684
(b)
16m
OUTPUT Oo----'l.N.Io---.()O 1.73V
Switching Characteristics
Over the Operating Rangel2,5]
7C168-25
7C169-25
Description
Parameters
Min.
Max.
7Cl68-35
7C169-35
Min.
Max.
7C169-40
Min.
Max.
7C168-45
Min.
Max.
Units
45
ns
45
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
35
25
40
45
40
35
3
ns
tOHA
Output Hold from AddressChange
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[6]
tHZCE
CE HIGH to High Z[6,7]
tpu
CE LOW to Power-Up (7C168)
tpD
CE HIGH to Power-Down(7C168)
tRCS
Read Command Set-Up
0
0
0
0
ns
tRcH
Read Command Hold
0
0
0
0
ns
3
3
25
17C168
25
15
17C169
5
5
15
ns
5
ns
25
20
20
25
ns
25
5
0
0
3
35
0
0
25
ns
ns
30
ns
WRITE CYCLEl:8]
twc
Write Cycle Time
25
35
40
40
ns
tSCE
CE LOW to Write End
25
30
30
35
ns
tAW
Address Set-Up to Write End
20
30
40
35
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpwE
WE Pulse Width
20
30
35
35
ns
tSD
Data Set-Up to Write End
10
15
15
15
ns
tHD
Data Hold from Write End
0
0
3
3
ns
tLZWE
WE HIGH to Low Z[6]
6
(,
6
6
ns
tHZWE
WE LOW to High Z[6,7j
10
Noles:
S. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of l.SV; input pulse levels of 0 to 3.0V; and output
loading of the specified IOrJIOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tIZ
for any given device.
7. tHZCE and tHZwEare tested with CL = 5 pF as in part (b) ofACTest
Loads. 'fransition is measured ±SOO m V from steady state voltage.
8.
2-247
15
20
20
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals mnst be LOW to initiate awriteand
eithersignalcantcrminateawritebygoingIDGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C168
CY7C169
.J:l~NDucroR
Switching Waveforms
Read Cycle No. 119, 10]
t=
ADDRESS
DATA OUT
tRC
---------*-1.._---
==~~-----~!~~~~~H~A~=~~i·~,:x~;x~l·,--------------------PREVIOUS DATA VALID
DATA VALID
-----------~~~~
--------------
Gl686
Read Cycle[9, 11]
IRc
~~
~
tACE
I---tLZ
~tHZ:j
,
HIGH IMPEDANCE
DATA OUT
//
."'-"'-
,",-
I-Vee
,
DATAVAUD
I---
tpu
tpo_
ICC
SUPPLY
CURRENT
50%~~1
50%
---l~
-
HIGH
IMPEDANCE
SB
~
I---
f4-
tRCS
tRCH __
Gl 687
Write Cycle No.1 (WE Controlled)[8]
twe
ADDRESS
==:)£
)(
tSCE
~ ~ K.
L ~~
lAw
tSA
~~~
~".
Iso
DATA IN
tHA-
tPWE
)(
DATA-IN VALID
I--
tHZWE j
tHO ...
)(
~ tLZWE ---1
HIGH IMPEDANCE
)>---------«
. . _____
DATAI/O _ _ _ _ _ _ _ _
DA_I_A_U_N_D_E_FI_N_ED_ _ _ _ _ _ _ _
Gl688
Notes:
9. WE is high for read cycle.
10. Device is continuously selected, CE = VILlI. Address valid prior to or coincident with CE transition low.
12. IfCEgoesHIGH simultaneousIywith WEHlGH, the output remains
in a high-impedance state.
2-248
CY7C168
CY7C169
-~
.
;~ CYPRESS
~.F SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[8, 12]
~------------------------twc --------------------------~
ADDRESS
-------Moo--------CE
tSCE
-------+1
----4---------------~
~--------~--------
Iso
DATA IN
DATA·IN VALID
tHZWE
DATA I/O
------I
-----------------~
HIGH IMPEDANCE
/>---------....;.;.,;;;,.-----
DATA UNDEFINED
C1689
'JYpical DC and AC Characteristics
NO~DSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
VS. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.4
lee
jll.0
V
0
w 0.8
~
«
::;:
V
0.6
0
0.4
0.2
"'
8
.::: 1.0
V
VIN= 5.0V
TA = 25°C
a:
z
1.2
[/
!ll1.2
-
~
0.6
gs
0.4
5.5
w
z
.J.l.4
1.2
0
0.0
1.0
2.0
./
w
..........
t'-.......
«
::;:
TA=25°C
a:
z
0
r--
1.0
0.8
/
./
0.6
4.5
5.0
5.5
SUPPLY VOLTAGE
M
6.0
-55
/'
~
5
80
~
60
~
40
:::l
20
f=
o
25
125
AMBIENT TEMPERATURE (0G)
2-249
4.0
140
w 100
(jj
Vee = 5.0V
'"
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
::::; 1.2
3.0
OUTPUT VOLTAGE
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
- O.5V to + 7.0V
Range
Commercial
Militaryll]
- O.5Vto +7.0V
- 3.0V to + 7.0V
O°Cto +70°C
Vee
5V± 10%
- 55°Cto +125°C
5V± 10%
Electrical Characteristics Overtbe Operating Rangel2]
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
VIR
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel3]
Vee = Min., IOL = 8.0 rnA
VIL
IIX
7Cl68A-lS
7C169A-lS
Min.
Max.
2.4
7Cl68A-20
7C169A-20
Min.
Max.
2.4
0.4
0.4
Units
V
Vee
0.8
V
V
V
+10
+10
t-tA
t-tA
-350
-350
rnA
115
90
90
rnA
2.2
-0.5
-10
Vee
0.8
+10
2.2
-0.5
-10
-10
+10
-10
Input Load Current
GND.$. VI.$. Vee
Ioz
Output Leakage
Current
GND .$. Vo.$. Vee,
Output Disabled
los
Output Short
CircuitCurrend4]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
AutomaticCS
Power-Down Current
Max. Vee,
Com'l
40
AutomaticCE
Power-Down Current
Max. Vee,
CE ~ VCC - .0.3 V
Mil
Com'l
Mil
40
40
rnA
CE~VIR
20
20
20
rnA
ISBI
IsB2
Com'l
Mil
Notes:
1.
2.
TA is the "instant on" case temperature.
See the last page of this specification for Group Asubgroup testing information.
3.
4.
2-253
VILmin. = -3.0V for pulse durations less than 30ns.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
CY7C168A
CY7C169A
~
-::z
IE
•
CYPRF.SS
F
SEMICONDUCTOR
Electrical Characteristics
Parameters
Over the Operating Rangel:2] (continued)
7C168A-25
7C169A-25
Min.
Max.
Description
Thst Conditions
VOH
VOL
Vrn
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Vee = Min.,IOH = -4.0 rnA
Input HIGH Voltage
Input LOW Voltagel3]
Input Load Current
GNDsVrsVee
loz
Output Leakage
Current
GNDsVosVee
OutputDisabled
los
Output Short
CircuitCurrend4]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
AutomaticCS
Power-Down Current
Max. Vee,
CE~ Vrn
AutomaticCE
Power-DownCurrent
Max. Vee,
CE~ VCC - .0.3 V
ISBI
IsB2
2.4
7Cl68A-35
7C169A-35
Min.
Max.
2.4
2.4
0.4
Vee = Min.,loL = 8.0 rnA
7Cl68A-45
7C169A-40
Min.
Max.
0.4
0.4
V
V
Vee
0.8
V
V
Vee
0.8
2.2
-0.5
-10
10
-10
10
-50
50
-50
50
!JA.
!JA.
2.2
-0.5
Vee
0.8
2.2
-0.5
-10
-10
+10
+10
-350
-350
-350
rnA
70
80
20
70
70
50
70
20
rnA
Mil
Com'l
Mil
Com'l
20
20
Mil
20
Com'l
20
20
rnA
20
20
20
20
rnA
20
Capacitance [5]
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Parameters
CIN
CoUT
Max.
Units
pF
10
10
Vee=5.0V
pF
AC Test Loads and Waveforms
R148111
R148111
5V 0 -_ _---'''''''".,
5V
OUTPUTo----1~--+
0------'.,.,...,
FI
5PFI
R2
2550
30 P
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
Equivalent to:
ALL INPUT PULSES
OUTPUTo---p---+
(a)
THEVENIN EQUIVALENT
--_·.,Yv.'__-oo
OUTPUT ().o
1670
(b)
3'W~
R2
2550
GND
.s.5ns ...
C168A-4
90%
10%
I.-
+~~5ns
10%
C168A-5
1.73V
Noles:
5. -rested initially and after any design or process changes that may affect
these parameters.
6.
2-254
-rest conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
CY7C168A
CY7C169A
.:~
~=
'~.F
CYPRESS
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel3, 6J
7C168A-15
7C169A-15
Parameters
Min.
Description
Max.
7C168A-20
7C169A-20
Min.
Max.
7C168A-25
7C169A-25
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from AddressChange
tACE
Power Supply Current
15
I 7C169A
ns
25
20
5
5
I 7C168A
25
20
15
5
ns
ns
15
20
25
10
12
15
ns
ns
tuCE
CE WW to Low Z[7. 8J
tHZCE
CE HIGH to High Z[7, 9J
tpu
CE WW to Power Up (7CI68)
tpD
CEHIGH to Power-Down(7CI68)
tRCS
Read Command Set-Up
0
0
0
ns
tRCH
WRITE CYCLEllOJ
Read Command Hold
0
0
0
ns
twc
Write Cycle Time
15
20
20
ns
tscE
CE WW to Write End
12
15
20
ns
5
5
8
0
5
8
0
10
0
20
15
ns
ns
ns
20
ns
tAW
Address Set-Up to Write End
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
ns
tSD
DataSet-Up to Write End
10
10
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tuWE
WE HIGH to Low Z[7]
7
7
7
tHZWE
WE LOW to HighZ[7, 9J
5
Notes:
7. At any given temperature and voltage condition, THZ is less than tIZ
for all devices. "fransition is measured ±500 mV from steady state
voltage with specified loading in part (b) of AC Thst Loads and Waveforms.
8. 3-ns minimum for the CY7C169A
9. tHZCE and tHZWE are tested with CL = 5 pF as in part (a) of Thst
Loads and Waveforms. "fransition is measured ±500 m V from steady
state voltage.
5
ns
5
ns
10. The internal write time of the memory is defined by the overlap ofCE
LOW and WE LOW. Both signal must be WW to initiate a write and
either signal can terminate a write by going high. The data input setup
and hold timing should be referenced to the rising edge of the signal
that terminates the write.
11. WE is IDGH for read cycle.
12. Device is conrulUously selected, CE = V n,.
13. Addrcss valid prior to or coincident with CE transition low.
14. IfCE goes IDGH simuJtaneouslywith WEIDGH, the output remains
in a high-impedance state.
2-255
=.
CY7C168A
CY7C169A
~
~=CYPRESS
~, SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangel3, 6] (continued)
7Cl68A-35
7C169A-35
Description
Parameters
Min.
Max.
7C169A-40
Min.
Max.
7C168A-45
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
35
40
45
toHA
Output Hold from AddressChange
tACE
Power Supply Current
tLZCE
CE LOW to Low Z[7. 8]
tHZCE
CE HIGH to High Z[7, 9]
tpu
CE LOW to Power Up (7CI68)
tpD
CEmGH to Power-Down(7CI68)
tRCS
Read Command Set-Up
0
0
0
ns
tRCH
WRITE CYCLEllO]
Read Command Hold
0
0
0
ns
twc
Write Cycle Time
25
35
40
ns
tSCE
CE LOW to Write End
25
30
30
ns
tAW
Address Set-Up to Write End
25
30
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
20
20
ns
tSD
Data Set-Up to Write End
15
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE mGH to Low Z[7]
5
5
5
tHzwE
WE LOW to High Z[7, 9]
40
35
5
5
I 7C168A
I 7C169A
5
25
15
10
ns
15
20
ns
ns
5
0
0
45
25
5
5
ns
ns
40
35
ns
45
15
0
ns
ns
20
25
ns
ns
15
15
ns
Switching Waveforms
Read Cycle No. d ll 12]
IRe
ADDRESS
~IOHA
DATA OUT
)(
~I{"
PREVIOUS DATA VALID
lAA
*XX~ (
DATA VALID
Cl68A-6
2-256
CY7C168A
CY7C169A
-~
~~CYPRESS
JF
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle[11, 13]
4lc
CE
..... ~
<-
lACE
I-- ILZCE
... IHZCE-
HIGH IMPEDANCE
DATA OUT
I--
.....
DATA VALID
""
Ipu_
Vcc
SUPPLY
CURRENT
1///
,/
-tpo_
50%~
:;'{ 50%
-
WE - - . /
_
I+--
HIGH
IMPEDANCE
-ICC
~ISB
IRCH
IRCS
C168A-7
Write Cycle No.1 (WE Controlled) [10]
IWC
ADDRESS
~l'
ISCE
~~ ~ t\..
/
~ W////h
lAw
ItiA-
lSA
IPWE
~~~
/'{.
IHO ...
Iso
)l'
DATA IN
)(
DATA-IN VALID
I--
IHZWE
j
f-
ILZWE-j
HIGH IMPEDANCE
)>----------«
..._____
DATA I/O _ _ _ _ _ _ _ _
DA_I_A_U_N_D_E_FI_N_ED_ _ _ _ _ _ _ _ _
C168A-8
WrIte Cycle No.2 (CS Controlled) [10, 14]
~-----------------------twc------------------------~
ADDRESS
--4--------,
-----0014------- isCE ------------+f
CE
14--+----DATA IN
DATA I/O
Iso
--------------~
,----+-----
-------+f.DATA-IN VALID
tHZWE - - I
--------------------'" I
HIGH IMPEDANCE
DATA UNDEFINED
,,>---------------!'
C168A-9
2-257
CY7C168A
CY7C169A
.1in~DOC7OR
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBffiNT TEMPERATURE
NORMAUZEDSUPPLYCURRENT
SUPPLY VOLTAGE
V8.
1.4
3l1.2
Icc
jll.0
V
o
~ 0.8
~
:;
V
0.6
z~
0.4
./
./
1.2
III
~ 1.0
8
C
-
VIN= 5.0V
TA = 25°C
~
~
5.5
25
125
AMBIENT TEMPERATURE (OC)
1.4
1.6
1.3
jl.4
..............
40
1.0
II:
........
1.0
I'-.....
TA = 25°C
4.5
5.0
II:
0
-
I"---
O. 9
O. 8
4.0
~
<
:;
5.5
z
0.6
-55
~
25
125
25.0
.s
-
/
20.0
/
:i
N
:::;
< 1.5
:;
~ 15.0
II:
w
---
2.0
./
3.0
4.0
SUPPLY VOLTAGE M
5.0
o 10.0
5.0
V
1/
200
V
60
40
20
"
4.0
/
0.0
-
/
Vcc= 5.0V
TA = 25°C
/
I
V
o
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE M
TYPICAL ACCESS TIME CHANGE
OUTPUT LOADING
YO.
"iii'
1.0
~
80
AMBIENT TEMPERATURE (OC)
2.5
V
iii
Vcc= 5.0V
o
ow 2.0
0.5
5
~
30.0
0 1.0
z
~
./
/
./
0.8
3.0
0.0
0.0
w 100
1.0
TYPICAL POWER·ON CURRENT
VS. SUPPLY VOLTAGE
V
z
1.2
SUPPLY VOLTAGE M
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
I-
z
6.0
"""
<,140
0
w
'"
2.0
.s 120
2
w 1.
N
:::;
< 1. 1 .....
:;
Vee = 5.0V
TA = 25°C
OUTPUT VOLTAGE M
NORMALIZED ACCESS TIME
vs. AMBffiNT TEMPERATURE
0
0
~
!:i
I!: 20
::J
o
o 0.0
ISB
M
NORMALIZED ACCESS TIME
SUPPLY VOLTAGE
..e-
lil
Vcc- 5.OV
VIN =5.0V
0.0
-55
6.0
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
::J
V8.
z
~ 60
ISB
SUPPLY VOLTAGE
0
w
:::; 0.6
0.2
5.0
'Z 100
~
'5 60
U
~
0.8
Z
0.0 I - - 4.0
4.5
g120
Icc
o 0.4
0.2
j
~
~
NORMALIZED Icc vs. CYCLE TIME
1.1
,...----r----.------,
2"
0
w
1.0
N
:::;
<
:;
/
II:
Vcc=4.5V TA = 25°C
0
z
0.9
I 1-
400
600
800 1000
CAPACITANCE (pF)
2-258
20
30
CYCLE FREQUENCY (MHz)
40
CY7C168A
CY7C169A
.:=iF
lb ~PRFSS
"
SEMICONDUCIOR
Ordering Information
Speed Icc
(ns)
(mA)
15
115
CY7CI68A-15PC
CY7C168A-15DC
CY7C168A-15VC
20
90
CY7CI68A - 20PC
CY7CI68A-20DC
CY7C168A-20VC
CY7CI68A-20DMB
CY7CI68A-20LMB
CY7C168A-20FMB
CY7C168A-20KMB
CY7CI68A-25PC
CY7CI68A-25DC
25
70
80
35
45
70
50
70
Ordering Code
CY7CI68A-25LC
CY7CI68A-25VC
CY7CI68A-25DMB
CY7CI68A-25LMB
CY7CI68A-25FMB
CY7CI68A-25KMB
CY7CI68A-35PC
CY7C168A-35DC
CY7C168A-35LC
CY7C168A-35VC
CY7CI68A-35DMB
CY7C168A-35LMB
CY7CI68A - 35FMB
CY7C168A-35KMB
CY7C168A -45PC
CY7C168A-45DC
CY7C168A-45LC
CY7C168A-45VC
CY7C168A-45DMB
CY7C168A-45LMB
CY7C168A -45FMB
CY7C168A -45KMB
Package
1YPe
P5
D6
V5
P5
D6
V5
D6
LSI
F71
K71
P5
D6
LSI
V5
D6
LSI
F71
K71
P5
D6
LSI
V5
D6
LSI
F71
K71
P5
D6
LSI
V5
D6
LSI
F71
K71
Operating
Range
Speed Icc
(ns) (mA)
Commercial
15
115
Commercial
20
90
Military
Commercial
25
Military
70
80
Commercial
35
70
Military
Commercial
Military
45
50
70
Ordering Code
CY7CI69A-15PC
CY7C169A -15DC
CY7C169A -15VC
CY7CI69A-20PC
CY7CI69A-20DC
CY7C169A - 20VC
CY7CI69A-20DMB
CY7CI69A-20LMB
CY7CI69A-20FMB
CY7CI69A-20KMB
CY7CI69A - 25PC
CY7C169A-25DC
CY7C169A - 25LC
CY7C169A - 25VC
CY7CI69A-25DMB
CY7CI69A-25LMB
CY7CI69A-25FMB
CY7CI69A-25KMB
CY7C169A - 35PC
CY7C169A - 35DC
CY7C169A - 35LC
CY7C169A - 35VC
CY7CI69A-35DMB
CY7CI69A-35LMB
CY7CI69A-35FMB
CY7CI69A-35KMB
CY7CI69A-45PC
CY7C169A -45DC
CY7C169A -45LC
CY7CI69A-45VC
CY7CI69A-45DMB
CY7C169A-45LMB
CY7CI69A-45FMB
CY7CI69A-45KMB
2-259
Package
'JYpe
Operating
Range
P5
D6
V5
P5
D6
V5
D6
LSI
F71
K71
P5
D6
LSI
V5
D6
LSI
F71
K71
P5
D6
LSI
V5
Commercial
D6
LSI
F71
K71
P5
D6
LSI
V5
D6
LSI
F71
K71
Military
Commercial
Military
Commercial
Military
Commercial
Commercial
Military
•
·
CY7C168A
CY7C169A
.~CYPRES'3
::sa F
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOH
VOL
Vrn
VILMax.
IIX
Ioz
ICC
ISB1[15]
ISB2[15]
Note:
15. 7C168 only.
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
tM
tOHA
tACE
tRCS
tRCH
WRITE CYCLE
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
twc
tSCE
tAW
tRA
tSA
tpWE
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSD
tHD
Document#: 38-00095-D
2-260
CY7C170
CYPRESS
SEMICONDUCTOR
4096 X 4 Static R/W RAM
Features
Functional Description
• CMOS for optimum speed/power
• Highspeed
-tAA 25ns
-tACS = 15ns
• Low active power
-495 mW (commercial)
- 660 mW (military)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
• Output enable
The CY7C170 is a high-performance
CMOS static RAM organized as 4096
words by 4 bits. Easy memory expansion is
Jlrovided by an active LOW chip select
(CS), an active LOW output enable (OE),
and three-state drivers.
Writing to the device is accomplished when
the chip select (CS) and write enable (WE)
inputs are both LOW. Data on the four 110
pins (1100 through 1103) is written into the
memory location specified on the address
pins (Ao through Au).
=
Logic Block Diagram
Readingthe device is accomplished byt~
chip select (CS) and output enable (OE)
LOW, while write enable (WE) remains
HIGH. Under these conditions the contents
of the memory location specified on the address pins will appear on the 110 pins.
The 110 pins staYi!l high-impedance state
when chip select (CS) or o~t enable (OE)
is HIGH, or write enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Pin Configurations
DIP
Top View
A.,
1
Vee
Ao
Ao
Ag
Ag
A,
A7
Ag
NC
Ag
As
A,.
Al1
VOo
7
vo,
vo.
vo.
cs
Ao
A1
A2
WE
VOo
ff
'w"
~
<
A.,
U)
As
As
U)
C170-2
SOJ
Top View
I/O,
vo.
zw
1/03
A.,
vee
Ao
As
Ag
Ag
A7
A,
Ag
NC
Ag
NC
NC
As
VOo
AlO
Al1
I/O,
I/O.
cs
vo.
DE
WE
GND
C170-3
C170-1
Selection Guide
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
I
Commercial
I
Military
2-261
7C170-25
7C170-35
7C170-45
25
35
45
90
90
90
120
120
en
::::iii:
2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
55°Cto +125°C
- O.5V to +7.0V
- O.5Vto +7.0V
- 3.0Vto +7.0V
Range
Ambient
Thmperature
Vcc
Commercial
O°Cto +70°C
5V± 10%
Militaryll]
- 55°Cto +125°C
5V ± 10%
Output Current into Outputs (Low) ................ 20 rnA
Electrh:al qlaracteristics
Over the Operating Range£2]
7C170
Description
Parameters
Thst Conditions
Min.
VOB
VOL
Vrn
Output HIGH Voltage
VlL
Input LOW Voltage
IJX
Input Load Current
Output LeakageCurrent
Output Short Circuit Currend3]
Vee = Max., VOUT= GND
Vee Operating Supply
Current
Vee = Max.
loUT = ornA
Output LOW Voltage
Input HIGH Voltage
loz
los
Icc
Max.
Units
0.4
V
2.0
-3.0
Vee
0.8
V
-10
-50
+10
2.4
Vee = Min., lOB = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
GND< VI t+....-
A"
llS
OE:
vo.
GND
5I-++--c>-t;-t~ vo,
I H+--t.;::....p.- va.
HH--i:>-2001V
(per MIL-STD-883, Method 3015)
Latch-upCurrent............................. >200rnA
StorageThmperature ................. - 65°C to +150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 21) ....................... - O.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
Operating Range
Range
Ambient
Thmperature
Vee
Commercial
O°Cto +70°C
5V± 10%
Militaryll]
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Overthe Operating Range[2]
7C170A-15
Parameters
Description
Thst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[3]
Vee Operating Supply
Current
VOH
VOL
Vrn
VlL
Irx
Ioz
los
Ice
Min.
Vee = Min., IOH = - 4.0 rnA
Vcc = Min., IOL = 8.0 rnA
GNDSVISVCC
GNDsVosVee,
Output Disabled
Vee = Max., VOUT = GND
I
I
Vcc=Max.
IoUT=OrnA
Max.
2.4
7C170A-20, 25, 35, 45
Min.
Max.
2.4
0.4
2.2
-3.0
-10
-10
Vee
0.8
+10
+10
0.4
2.2
-3.0
-10
-10
Units
V
V
V
V
Vee
0.8
+10
+10
iJA
iJA
-350
-350
rnA
115
90
120
rnA
rnA
Com'l
Mil
Capacitance [4]
Parameters
Description
CIN
Inputcapacitance
CoUT
OutputCapacitance
Thst Conditions
TA=25°C,f=lMHz,
Vcc= 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of tbis specification for Group A subgroup testing
information.
Max.
Units
10
pF
10
pF
3. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R148Hl
Rl48Hl
OUTPUTC>---P---+
OUTPUTC>---1P---+
sv C>------''''''''~
30PFI
INCLUDING
JIGAND _
SCOPE -
Equivalent 10:
5V
R2
255!l
C>-------"""'~
SPFI
ALL INPUT PULSES
::
R2
255!l
-~-s-ns-l:--m
~~
INCLUDING
JIGAND _
SCOPE -
(a)
THEVENIN EQUIVALENT
(b)
C170A-4
16m
OUTPUT_l.73V
2-267
C170A-S
II
~
~~PRESS
-=:J!!!!lT., SEMlCONDUCfOR
CY7C170A
Switching Characteristics
Over the Operating Rangel!, 5]
7C170A-15
Description
Parameters
READ CYCLE
Read Cycle Time
tRC
Min.
7CI70A-20 7C170A-25
7C170A-35
7C170A-45
Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
15
2S
20
15
35
2S
45
35
ns
45
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACS
CS LOW to Data Valid
10
15
15
2S
30
ns
tDOE
OE LOW to Data Valid
10
10
12
15
20
ns
tLZOE
OE LOW to Low Z
tHZOE
OEHIGH to HighZ16]
tLZCS
CS LOW to Low ZI7]
tHZCS
CS HIGH to HighZI6, 7]
5
20
5
3
5
3
3
8
8
5
5
8
5
3
12
5
ns
ns
3
10
8
ns
5
5
15
ns
15
ns
5
15
10
ns
WRITECYCLEL~j
twc
Write Cycle Time
15
20
20
2S
40
ns
tscs
CS LOW to Write End
12
15
20
2S
30
ns
tAW
Address Set-Up to Write End
12
15
20
2S
30
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
WE HIGH to High Z
tLZWE
WE HIGH to Low Z
7
7
5
5
Notes:
5. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0V and output
loading of the specified ImlIoH, and 30-pF load capacitance.
6. tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test
Loads. ltansition is measured ±SOO m V from steady state voltage.
7. At any given temperature and voltage condition, tHZes is less than
tues for any given device. These parameters are sampled and not
100% tested.
8. The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate awriteand
either signal can terminate awrite bygoingHIGH. The data inpnt setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
9.
10.
11.
12.
13.
7
5
5
Switching Waveforms
DATA OUT
::f=t:
~
t'::::1~....--vAUD¢XXXXX>j<________
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..•........................ >200 rnA
Operating Range
Range
Ambient
Temperature
Vee
Commercial
O°Cto +70°C
5V± 10%
Military!l]
- 55°C to +125°C
5V± 10%
7Cl71-2S
7Cl72-2S
Parameters
Description
Test Conditions
Min.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Currentl3]
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
lee
Vee Operating
Supply Current
Vee = Max.
IoUT= ornA
ISBl
Automatic 'CE
Power-Down Current
Max. Vee,
CE~ VIR
ISB2
Automatic 'CE
Power-Down Current
Max. Vee,
CE~ Vee - 0.3V
VOH
VOL
VIR
VIL
IJX
Ioz
los
Max.
2.4
Min.
7C171-4S
7Cl72-4S
Max.
2.4
Min.
0.4
0.8
+10
+50
2.2
- 3.0
-10
-50
Max.
Units
2.4
0.4
2.2
- 3.0
-10
- 50
GND.s. VI < Vee
GND.s. Vo.s. Vee.
Output Disabled
Vee = Max., VOUT = GND
7Cl71-3S
7Cl72-3S
V
V
V
V
0.4
0.8
+10
+50
2.2
- 3.0
-10
- 50
0.8
+10
+50
flA
flA
-350
- 350
- 350
rnA
90
90
20
40
15
40
90
90
20
20
15
20
70
70
15
20
15
20
rnA
rnA
Com'l
Mil
Com'l
Mil
Com'l
Mil
rnA
mA
rnA
rnA
Capacitance!4]
Parameters
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
Max.
10
10
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page ofthis specification for Group A subgroup testing information.
Units
pF
pF
3.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4. Thsted initially and after any design orprooess changes that may affect
these parameters
AC Test Loads and Waveforms
_-----w._,
R14810
Rl4810
5V_---_..,
OUTPUT-----1P---~
OUTPUT---1P----+
5V
30PFI
5PFI
R2
2550
INCLUDING
JIGAND _
SCOPE -
3.DV~00%
R2
2550
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
GND
10%
S5ns
(b)
THEvENIN EQUIVALENT
Cl71-4
1670
OUTPUT 0 0 - -__\/\,_ _--o01.73V
2-272
C171-5
CY7Cl71
CY7Cl72
~
=t: fii~
~
SEMJCCt.lDUCTOR
Switching Characteristics Over the Operating Range[2, 5]
7C171-2S
7C172-2S
Parameters
Description
Min.
I
Max.
7Cl71-3S
7Cl72-3S
Min.
Max.
7C171-4S
7CI72-4S
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
25
25
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CE WW to Data Valid
tLZCE
CE WW to Low Z[6]
tHZCE
CE HIGH to High zt6, 7J
tpu
CE WW to Power-Up
tpo
CE HIGH to Power-Down
tRCS
Read Command Set-Up
3
10
0
20
25
ns
ns
0
0
ns
ns
5
20
25
Read Command Hold
tRCH
WRITE CYCLEtHJ
45
35
ns
ns
3
5
5
45
35
3
25
ns
45
35
30
ns
0
0
0
ns
0
0
0
ns
twc
Write Cycle Time
25
35
40
ns
tSCE
CE WW to Write End
25
30
35
ns
tAW
Address Set-Up to Write End
20
30
35
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
25
30
ns
tso
Data Set-Up to Write End
10
15
15
ns
tHO
Data Hold from Write End
0
0
3
ns
tLZWE
0
0
0
tHZWE
WE HIGH to Low Z[6] (7C172)
WE: WW to High Z[6, 7] (7C172)
ns
10
5
20
ns
tAWE
WE WW to Data Valid (7CI71)
25
30
35
ns
tADY
Data Valid to Output Valid (7C171)
25
30
35
ns
Notes:
S. lest conditions assume signal transition times of 5 ns or less, timing
reference levels of l.Sv, input pulse levels of 0 to 3.0Y and output
loading of the specified Io,IIoH, and 30-pF load capacitance.
6. At any given temperature and voltage condition, 1HZ is less than ILZ
for any given device.
7. tHzCEand tHZWEare tested with Cl. = SpFas in part (b) ofACThst
Loads. 1l"ansition is measured ±SOO mY from steady state voltage.
8.
The internal write time of the memory is defmed by the overlap ofrE"
LOW andWI!LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going IDGH. The data input setup and hold timing should be referencd to the rising edge of the signal
that terminates the write.
9. WI! is HIGH for read cycle.
10. Device is continuously selected, 'CE = V IL.
Switching Waveforms
Read Cycle No. 119, 10]
ADDRESS
~
--~
DATA OUT
PREVIOUS DATA
lAC
1
1M
v:: JXX
2-273
C171-6
*===============D=A=:C=A=V=A=Ll=D=========::
•
r;
CY7Cl71
CY7Cl72
:I~PRESS
:sa'
SEMJCCM)1JCI'()R
Switching Waveforms
Read Cycle No. 2[9. 11]
~
DATA OUT
DATA VALID
Vee
SUPPLY
CURRENT
50%
Write Cycle No.1 (WE Controlled)[8]
~------------------------twc ------------------------~~
ADDRESS
___J:~===~t~SA~===::;k~~ . .
1----
WE
tPWE
- - - - . j ,,_ _ _ _ _ _ _ _ ___
DATA IN
DATA OUT
(7C172)
DATA OUT
(7C171)
DATA UNDEFINED
DATA UNDEFINED
DATA VALID
C171-8
Write Cycle No.2 (CE Controlled)[8, 12]
Iwc
ADDRESS
__~~::::~ISA~::::~~-----------I~E ----------~I,----~----Iso
DATA IN
DATA OUT
(7C172)
DATA OUT
(7C171)
DATA-IN VALID
DATA UNDEFINED
DATA UNDEFINED
HIGH IMPEDANCE
'.
3+c----D-A-~-A-V-AL-ID------Q171-9
11. Address valid prior to or coincident with
rn transition LOW.
12. Ift:Egoes HIGH simultaneouslywith WI!HIGH, the output remains
in a high-impedance state (7CI72).
2-274
CY7Cl71
CY7Cl72
&9lPRSS
~
SEMlCCWI.JCI'OR
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
VS.
1.4
!ll1.2
lee
Ji 1.0
V
o
~ 0.8
~
0.6
V-
'/
V
1.2
~
II)
~ 1.0
II:
w
~ 60
0.6
0.2
ISB
0.0
4.0
4.5
5.0
5.5
0.0
-55
6.0
SUPPLY VOLTAGE M
j
1.3
j
1.2
~
«
fil
N
1.1
::;:
...........
II:
z
1.0
0.9
0.8
4.0
TA = 25 D C
""- --....
r--
4.5
5.0
5.5
SUPPLY VOLTAGE
~
1.2
0.8
25.0
~
2.0
~
-,
0.5
0.0
-
./
V
0.0
1.0
2.0
3.0
SUPPLY VOLTAGE
4.0
M
iii
~
~
125
5.0
5.0
V
V
0.00
200
/
600
800 1000
CAPACITANCE (pF)
2-275
1.0
2.0
3.0
4.0
Vee = 5.0V
TA = 25 D C
VIN= 0.5V
1.01---+--......,1----::;0/
~
Vee=4.5V _
TA=25"C
II
400
/
o II
0.0
J
NORMALIZED Icc VS. CYCLE TIME
o
~
/
V
60
40
20
Vee = 5.0V
TA=25 DC
1.1
..?
/
20.0
4.0
M
OUTPUT VOLTAGE M
,-
J
f!; 15.0
m
O 10.0
1.5
~ 1.0
Z
25
/
80
TYPICAL ACCESS TIME CHANGE
vs. OUTPUf LOADING
~ 2.5
~
~
AMBIENT TEMPERATURE (DC)
30.0
II:
5
o
M
3.0
/v
~ 100
Vee = 5.0V
0.6
-55
""
vs. OUfPUf VOLTAGE
II:
/
L
Z
3.0
2.0
!z
L
~ 1.0
6.0
1.0
.....
OUTPUT VOLTAGE
<" 140
.5. 120
1.4
TYPICAL POWER·ON CURRENT
Vi. SUPPLY VOLTAGE
fil
0.0
"'
Vee = 5.0V
TA=25 DC
OUTPUT SINK CURRENT
1.6
0
0
i 2:
25
125
AMBIENT TEMPERATURE (DC)
VS. AMBIENT TEMPERATURE
1.4
............
40
NORMALIZED ACCESS TIME
NORMALIZED ACCESS TIME
SUPPLY VOLTAGE
VS.
w
~
Vee = 5.0V
VIN= 5.OV
Z
0.2
~
=> 80
(J
~ 0.4
~ 0.4
OUfPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
!zw 100
~
o8 0.8
~
~
g, 120
§
0.91---+--::;"c........,1----I
20
30
CYCLE FREQUENCY (MHz)
40
CY7C171
CY7Cl72
Ordering Information
Speed
(ns)
25
35
45
Ordering Code
Package
lYPe
Operating
Range
Srn;ed
ns)
Commercial
25
Package
Ordering Code
1YPe
Operating
Range
Commercial
CY7C171-25PC
P13
CY7Cl72-25PC
P13
CY7Cl71-25DC
D14
CY7Cl72-25DC
014
CY7Cl71-25LC
L64
CY7Cl72-25LC
L64
CY7Cl71-25VC
V13
CY7CI72-25VC
V13
CY7Cl71-35PC
P13
CY7Cl71-35DC
Commercial
CY7Cl72-35PC
P13
D14
CY7Cl72-35DC
014
CY7Cl71-35LC
L64
CY7CI72-35LC
L64
CY7Cl71-35VC
V13
CY7CI72-35VC
V13
CY7Cl71-35DMB
D14
CY7CI72-35DMB
D14
CY7Cl71-35LMB
L64
CY7CI72-35LMB
L64
CY7Cl71-45PC
P13
CY7C172-45PC
P13
CY7Cl71-45DC
D14
CY7Cl72-45DC
014
CY7Cl71-45LC
L64
CY7CI72-45LC
L64
CY7Cl71-45VC
V13
CY7CI72-45VC
V13
CY7Cl71-45DMB
D14
CY7C172-45DMB
D14
CY7Cl71-45LMB
L64
CY7CI72-45LMB
L64
MILITARY SPECIFICATIONS
Group A Subgroup Testing
35
Military
Commercial
45
Military
Switching Characteristics
Parameters
Subgroups
READ CYCLE
DC Characteristics
Subgroups
tRC
7,8, 9, 10, 11
1,2,3
tAA
7, 8, 9, 10, 11
1,2,3
laHA
7, 8, 9, 10, 11
VIH
1,2,3
tACE
7,8,9,10,11
VILMax.
1,2,3
Parameters
VOH
VOL
IlX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBI
1,2,3
ISB2
1,2,3
tRes
7,8, 9, 10, 11
tRCH
7,8,9,10,11
WRITE CYCLE
twc
7,8,9,10,11
tSCE
7,8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7,8, 9, 10, 11
tSA
7,8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7,8,9,10,11
tAWEI13J
tADyluJ
7,8, 9, 10, 11
7,8,9,10,11
Nole:
13. 7Cl71 only.
Document #: 38-00036-E
2-276
Commercial
Military
Commercial
Military
CY7C171A
CY7C172A
CYPRESS
SEMICONDUCTOR
4096 x 4 Static R/W RAM
Separate I/O
Features
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• Higbspeed
- tAA = 15ns
• 'lhmsparent write (7C17IA)
• Low active power
- 375mW
• Low standby power
-93mW
• TIL-compatible inputs and outputs
• Capable of withstanding greater than
2001Velectrostatic discharge
The CY7CI71A and CY7CI72A are highperformance CMOS static RAMs organized as 4096 by 4 bits with separate IJO.
Easy memory expansion isKovided by an
active LOW chip enable (CE) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 77% when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the
four input/output pins (10 through 13) is
written into the memory location specified
on the address pins (Ao through An).
Logic Block Diagram
Readingthe device is accomplished by taking
c!!!E.. enable (CE) LOW, while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear on
the four data output pins.
The output pins remain in a hi&'!:impedance
state when write enable (WE) is LOW
(7CI72Aonly), or chip enable is HIGH.
A die coat is used to insure alpha immunity.
Pin Configurations
DIP/SOJ
TopVJew
A"
As
As
Vee
1
As
A,
A,
A7
A.
As
I.
I,
As
A,.
Al1
13
00
0,
9
0,
0,
WE
GND
C171A·2
4 3 2 111 282726
As
-
As
~g
25
24
A,
21
20
NC
11
As
~g~: ~c
A10
A11
10
13
11
19
12131415161718
00
~1~~I~c5'a'o
C171A-3
Selection Guide
7Cl71A-20
7Cl72A-20
7C17IA-25
7Cl72A-25
7C171A-35
7C172A-35
7C17IA-45
7C172A-45
15
20
25
35
45
115
80
70
70
50
90
80
70
70
7C17IA-15
7Cl72A-15
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
I
Commercial
I
Military
2-277
•
CY7Cl71A
CY7Cl72A
Maximum Ratings
(Above which the useful life may be impaired. ForuserguideIines,
not tested.)
Storage Temperature ................ - 65°Cto +150 oo C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.OV
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.OV
DCInputVoltage ...................... - 3.0Vto +7.OV
Output Current into Outputs (Low) ................ 20 rnA
Electrical Characteristics
Parameters
VOH
VOL
Vrn
VlL
IIX
Ioz
los
lee
IsBl
IsB2
Static Discharge Voltage..... . .. .. . .. .. . . . .. . .. . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Ambient
Thmperature
Vee
Commercial
O°Cto +70°C
5V± 10%
- 55°C to +125°C
5V± 10%
Militaryll]
Over the Operating Rangel2]
Description
Thst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent!3]
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee Operating Supply
Current
Vee = Max.
lOUT = ornA
Automatic CE
Power-Down Current
Max. Vee,CE~ Vrn
Min. DutyCycIe = 100%
Automatic CE
Power-Down Current
Max. Vee,
CE~ Vrn - 0.3y,
VIN ~ Vee - O.3Vor
7C171A-15
7Cl72A-15
7C17IA-20
7C172A-20
7Cl71A-25
7Cl72A-25
Min.
Min.
Min.
Max.
2.4
GND~VI~Vee
GND~Vo~Vee,
Output Disabled
Vee = Max.,
VOUT=GND
Vee
0.8
+10
+10
VIN~O.3V
Notes:
1. TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testiug information.
Mil
3.
2.
4.
2-278
Vee
0.8
+10
+10
2.2
-3.0
-10
-10
V
V
V
V
iJA
iJA
-350
-350
rnA
115
80
40
90
40
70
80
20
rnA
rnA
rnA
40
20
20
20
20
20
20
Mil
Com'l
0.4
Vee
0.8
+10
+10
-350
Com'l
Mil
Com'l
2.2
-3.0
-10
-10
Max. Units
2.4
0.4
0.4
2.2
-3.0
-10
-10
Max.
2.4
rnA
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
'Iested initially and after any design or process changes that may affect
these parameters
CY7Cl71A
CY7C172A
~
i~PRFSS
.
==:!!!!!!!:F
SEMICONDUCTOR
Electrical Characteristics
Over the Operating Rangel2] (continued)
7C17IA-3S
7Cl72A-3S
Description
Parameters
lest Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
VIH
Output WW Voltage
Input HIGH Voltage
Input LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIL
IIX
Vee = Max.,
VOUT= GND
Vee Operating Supply
Current
Vee = Max.
lOUT = ornA
ISBI
AutomaticCE
Power-Down Current
Max.Vee,CE~ VIH
Min. Duty Cycle = 100%
ISB2
AutomaticCE
Power-DownCurrent
Max. Vee,
CE~ VIH - O.3V
VIN~ Vee - O.3V
los
lee
2.4
Min.
Max.
V
0.4
V
Vee
0.8
V
V
+10
+10
f.IA
f.IA
-350
-350
rnA
70
70
20
50
70
20
rnA
rnA
rnA
Mil
Com'l
20
20
20
20
Mil
20
20
GND ~ Vo~ Vee,
Output Disabled
2.2
-3.0
-10
Vee
0,8
+10
2.2
-3.0
-10
-10
+10
-10
Com'l
Mil
Com'l
orVIN~O.3V
Units
2.4
0.4
GND~VI~Vee
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrend3]
Ioz
Max.
7C171A-4S
7Cl72A-4S
rnA
Capacitance [4]
Parameters
lest Conditions
Description
CIN
InputCapacitance
TA = 25°C,f= 1 MHz,
CoUT
OutputCapacitance
Vee=5.0V
\Jnits
Mllx.
10
pI'
10
pF
AC Test Loads and Waveforms
R14810
R14810
5VO----_....,
5Vo---~1IIo-,
OUTPUTO-----1r---.
OUTPUTo-----1r---.
30PFI
5PFI
R2
2550
INCLUDIN~
JIGAND
INCLUDING
JIGAND _
SCOPE -
::::?c~
R2
2550
_~
_
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
(b)
C171A-4
THEVENIN EQUIVALENT
1670
OUTPUT
"O---"""\I\~_--oO
1.73V
2-279
C171A-5
CY7Cl71A
CY7Cl72A
_~PRFSS
--=,
SEMlCONDUcroR
Switching Characteristics Over the Operating Rangel2,5]
7C17IA-15
7Cl72A-15
Description
Parameters
15
tAA
Address to Data Valid
toHA
Output Hold from
AddressChange
CE WW to Data Valid
CEWWtoWWZLOJ
CE HIGH to HIGH Zlo, IJ
tHzCE
tpu
tpo
CE WW to Power Up
8
0
15
20
0
0
0
0
35
10
0
15
0
20
25
25
25
30
30
0
0
0
0
20
20
15
0
15
0
5
5
tAW
Address Set-Up to Write End
Address Hold from Write End
0
0
0
Address Set-Up to Write Start
WE Pulse Width
0
12
10
0
5
0
15
10
0
5
0
5
tHZWE
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low ZloJ (7CI72A)
WEWWtoHigh Zl6, 7J(7CI72A)
0
15
10
tAWE
tADY
20
ns
ns
15
ns
ns
ns
ns
25
20
0
0
20
20
45
0
0
0
20
15
15
ns
ns
5
0
0
12
12
ns
40
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
10
15
ns
ns
WE WW to Data Valid (7CI71A)
15
20
25
30
35
ns
Data Valid to Output Valid
(7CI71A)
15
20
25
30
35
ns
Notes:
8.
8
0
ns
45
5
5
5
15
tIZWE
7.
25
20
5
CE LOW to Write End
tso
tHD
6.
15
5
35
5
5
Write Cycle Time
ISA
S.
5
twe
tsCE
tpwE
7C17IA-45
7C172A-45
45
35
25
20
5
CE HIGH to Power Down
25
20
15
Read Command Set-up
tRCS
Read Command Hold
tRCH
WRITECYCLEl"J
IliA
7C17IA-35
7C172A-35
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ CYCLE
Read Cycle Time
tRe
tACE
tlZCE
7C17IA-20 7C17IA-25
7C172A-20 7Cl72A-25
.
Testconditions assume signal transition times ofS nsorless, timing reference levels of l.SY, input pulse levels ofO to 3.0V and output loading
of the specified ImlloH and 30-pF load capacitance.
At any given temperature and voltage condition, tHZ is less than tLZ for
any given device.
tHZCE and tHZWE are tested with CL = SpF as in part (b) of AC Thst
Loads. 'fransition is measured ±SOO mV from steady state voltage.
The internal write time of the memory is defined by the overlap of CE
and WE LOW. Both signals must be
to initiate awrite and
ww
ww
either signal can terminate a write by going HIGH. The data input set·
up and hold timing should be referencd to the rising edge of the signal
that terminates the write.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = V IL.
11. Address valid prior to or coincident with CE transition Ww.
12. If CE goes HIGH simultaneousIywith WE HIGH, the output remains
in a high-impedance state (7C172A).
Switching Waveforms
Read Cycle No. 1[9, 101
*_
~.---_ _ _
lRC_ _ _ _
ADDRESS
DATA OUT
,.Ev: 3xx ~--------DA-I-A-'l-A-LlD----------------------C171A-6
2-280
CY7Cl71A
CY7Cl72A
;J~PRESS
J!'
SEMlCONDUCI'OR
Switching Waveforms
•
Read Cycle No. 2[9,11)
CE
~--------------------~CE --------------------~~---------------
DATA VALID
Vee
SUPPLY
CURRENT
----L;=4::::::::~~~--------------------------------J-------:
ICC
'---ISB
Write Cycle No.1 (WE Controlled)[8)
~------------------------ twc --------------------------~
ADDRESS
tSCE
WE
_____~:::::::2I~SA~:::::::;~~~~~--- tPWE ------~
,------------------
DATA IN
--------------------------~--------~~--~~~~~~~'---------+__________..;'
DATA OUT
(7CI72A) ________......_____D_AT_A_U_N_D_E_F_IN_E_D__
----------------------------~--~
DATA OUT
(7CI71A) ________________
DA_T_A_U_N_D_E_F_IN_E_D_________
DATA VALID
C171A-8
Write Cycle No.2 (CEControlled)18, 12]
twc
ADDRESS
CE ____-l::::==-.::tS~A-===:1-----------
tSCE -----------+/ ~--------+----------
ISD
DATA OUT
(7C172A) ____-1-__________./ , __f--------------DA-T-A---VA-L-ID----------~
HIGH IMPEDANCE
DATA UNDEFINED
-_:::~:::========j';:.:....=_=_=_=~_=_=_~_'.:...~_---.::.IA=WE::",_
--_-_-_-:---.1*_______
DATA OUT
(7CI71A) _________
D_AT_A_U_N_D_E_F_IN_E_D______________________________....
~
DATA VALID
C171A-9
2-281
CY7C171A
CY7Cl72A
Typical DC and AC Characteristics
1.4
!ll1.2
lee
jll.0
./
c
~ 0.8
:::J
~ 0.6
V
/'
./
1.2
III
~ 1.0
0
.2 0.8
c
w
!::l
«
:;:
a:
~ 0.4
-----
4.5
5.0
5.5
w
0.6
~ 60
Vee- 5.OV
VIN= 5.0V
SUPPLY VOLTAGE (V)
1.6
1.4
1.3
J
c 1.2
w
c
!::l«
:;:
a:
0
z
w
1.1
-........
1.0
0.9
0.8
4.0
r-... -...
:-TA = 25°C)
4.5
5.0
5.5
!::l
«
1.4
0
Z
0.8
6.0
c 2.0
w
:[ 20.0
N
:::
a:
!:i
~
:;: 1.5
,0:
1.0
--
2.0
3.0
./
4.0
SUPPLY VOLTAGE (V)
20
o
0
0.0
5.0
!!l
1.0
2.0
140
!zw
100
~
125
V
Z
iil
60
5
40
6
20
o
/
/
Vee = 5.0V
TA = 25°C
I
/
0.0
/
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED lee vs. CYCLE ~E
1.1
~
/
/
10.0
Vee=4.5V TA = 25°C
/
V
Vee=S.OV
TA= 25°C
V1N = 0.5V
1.0 i----+-----i-----:..t
/
15.0
5.0
"
4.0
1
G 80
1=
25
3.0
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
<"
!><:
Vee = 5.0V
"
OUTPUT VOLTAGE (V)
TYPICAL ACCESS ~ CHANGE
vs. OUTPUT LOADING
25.0
V""
~
AMBIENT TEMPERATURE (OC)
~ 2.5
0.0
0.0
V"
/
0.6
-55
30.0
0.5
/
:;:
a: 1.0
TYPICALPOWER·ON CURRENT
vs. SUPPLY VOLTAGE
1.0
/'
1.2
3.0
z
40
Vee = 5.0V
TA = 25°C)
.............
.s 120
SUPPLYVOLTAGE (V)
0
25
125
AMBIENT TEMPERATURE (0C)
g
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NO~ZEDACCESST~E
vs. SUPPLY VOLTAGE
~
~
0.0
-55
6.0
a:
~ 80
()
0.2
ISB
!zw 100
~
Z
0.0
4.0
J
!120
a: 0.4
0
0.2
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.9f---+-:;;;J.e---ir----j
1 1-
200
400
600
800 1000
CAPACITANCE (pF)
2-282
20
30
CYCLE FREQUENCY (MHz)
40
CY7C171A
CY7Cl72A
~
.:::or
:~PRESS
~_., SEMICONDUClDR
Ordering Information
Speed
(ns)
15
20
25
35
45
Package
'.tYpe
Operating
Range
CY7C172A-15PC
P13
Commercial
CY7C172A-15DC
D14
Package
'.tYpe
Operating
Range
Speed
CY7CI71A-15PC
P13
Commercial
15
CY7CI71A-15DC
D14
CY7CI71A-15LC
L64
CY7C172A-15LC
L64
CY7CI71A-15VC
V13
CY7CI72A-15VC
V13
Ordering Code
CY7CI71A-20PC
P13
CY7CI71A-20DC
D14
(ns)
Commercial
20
Ordering Code
CY7C172A-20PC
P13
CY7CI72A-20DC
D14
CY7CI71A-20LC
L64
CY7CI72A-20LC
L64
CY7Cl71A-20VC
V13
CY7C172A-20VC
V13
CY7CI71A-DMB
D14
CY7CI72A-20DMB
D14
CY7CI71A-LMB
L64
CY7CI72A-20LMB
L64
CY7Cl71A-KMB
K73
CY7CI72A-20KMB
K73
CY7Cl71A-25PC
P13
CY7CI71A-25DC
Military
CY7CI72A-25PC
P13
D14
CY7CI72A-25DC
D14
CY7Cl71A-25LC
L64
CY7C172A-25LC
L64
CY7Cl71A-25CC
V13
CY7C172A-25VC
V13
CY7Cl71A-25DMB
D14
CY7C172A-25DMB
D14
CY7Cl71A-25LMB
L64
CY7C172A-25LMB
L64
CY7CI71A-25KMB
K73
CY7C172A-25KMB
K73
CY7CI71A-35PC
P13
CY7CI71A-35DC
CY7CI71A-35LC
Commercial
25
Military
CY7Cl72A-35PC
P13
D14
CY7Cl72A-35DC
D14
L64
CY7C172A-35LC
L64
CY7CI71A-35VC
V13
CY7Cl71A-35DMB
D14
CY7CI71A-35LMB
L64
CY7Cl71A-35KMB
K73
CY7Cl71A-45PC
P13
CY7Cl71A-45DC
Commercial
35
Military
Commercial
CY7C172A-35VC
V13
CY7Cl72A-35DMB
D14
CY7C172A-35LMB
L64
CY7C172A-35KMB
K73
CY7C172A-45PC
P13
D14
CY7C172A-45DC
D14
45
CY7Cl71A-45LC
L64
CY7C172A-45LC
L64
CY7Cl71A-45VC
V13
CY7CI72A-45VC
V13
CY7CI71A-45DMB
D14
CY7C172A-45DMB
D14
CY7Cl71A-45LMB
L64
CY7CI72A-45LMB
L64
CY7Cl71A-45KMB
K73
CY7C172A-45KMB
K73
Military
2-283
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
CY7Cl71A
CY7Cl72A
-=--.
=sa ~PRESS
,
SEMlCCtIDUCTOR
MIUTARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2, 3
VlH
1,2, 3
VILMax.
1,2, 3
lIX
1,2,3
10z
1,2,3
los
1,2,3
Icc
1,2,3
ISBI
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9, 10, 11
tOHA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
tRCS
7,8,9, 10, 11
tRCH
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9,10,11
tSCE
7, 8, 9, 10, 11
tAW
7,8,9,10,11
tHA
7,8,9,10,11
tSA
7,8,9, 10, 11
tpWE
7,8,9, 10, 11
tSD
7,8,9, 10, 11
tHO
7,8,9, 10, 11
tAWE[13)
7,8,9, 10, 11
tADyl13)
7,8, 9, 10, 11
Note:
13. 7CI71A only.
Document #: 38-00104-B
2-284
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
•
•
•
•
•
•
•
•
•
Supports 50-MHz cache systems
32K by 9 common I/O
BiCMOS for optimum speed/power
14-ns access delay (clock to output)
1\vo-bit wraparound counter supporting the 486 burst sequence (78173)
1\vo-bit wraparound counter supporting the linear burst sequence (78174)
Separate address strobes from processor and from cache controller
Synchronous self-timed write
Direct interface with the processor
and external cache controller
CY7B173
CY:7B174
32,768 X 9 Synchronous
Cache R/W RAM
• 1\vo complementary synchronous chip
selects
• Asynchronous output enable
Functional Description
The CY7B173 and CY7B174 are 32K by 9
synchronous cache RAMs designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access
delay from clock rise is 14 ns. A 2-bit onchip counter captures the first address in a
burst and increments the address automatically for the rest of the burst access.
The CY7B173 is designed for Intel
i486-based systems; its counter follows the
burst sequence of the i486. The CY7B174
is architected for other processors with linear burst sequences. Burst accesses can be
initiated with the processor address strobe
(ADSP) or the cache controller address
strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADY) input.
A synchronous self-timed write mechanismis provided to simplify the write interface. Tho complementary synchronous
chip select inputs are provided to support
two banks of memory (256 Kbytes) with no
extemallogic. These signals, in conjunction with the asynchronous output enable
(OE) signal, greatly simplify memory bank
selection.
Logic Block Diagram
Pin Configurations
LCc/pLCC
'fupVlew
>11Il1!l; '"
l)
0
..-oOCO....lur--CO(1l.
1
<<«o('C(..:«<
"" - A'4
--'-+-1
ADDRESS
REGISTER
Ao
6 5 4 3 2 1114443 42 41 40
39
A,
38
A12
37
36
35
34
Ai3
A14
Vss
~
A,;
At!
32Kx9
Vss
Do
01
VSSQ
Vcce
02
RAM
CORE
CLK----4H>
ADV---t-I
ADV.
LOGIC
WE~C~~
-+
CSo
cs, _++---1
ADSP-__r-~
ADSC
•
TIMING
CONTROL
10
11
12
13
78173
7B174
A11
Dr
33
06
14
15
16
32
VSSQ
Vcca
Os
17
29
1819202122 23242528 27 28
31
30
04
B173-2
' - - - - - - 1 " ) -....- - . Do - D.
r--------~r_J---------~
OE-----------I
8173-1
Selector Guide
78173-14
78174-14
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
I Commercial
I Military
2-285
78173-18
78174-18
78173-21
78174-21
14
18
21
210
210
210
230
230
CY7B173
CY7B174
PRELIMINARY
Functional Description (continued)
Single Write Accesses Initiated by i\'fi'SlJ
This aa:ess is initiated when the following conditions are satisfied at
clock rise: (1) a10 = 1 and ~l = 0 and (2) A'I5SP is LOW, A'I5SPtriggered write cycles are a>mpIeted in two cloCk periods. The address
at Ao through Al4 is loaded into the address advancement logic and
delivered to the RAM core. The write signal is ignored in this cycle
because the cache tag or other external 10gic use this clock period to
perfonn address comparisons or protection checks. If the write is allowed to proceed, the wrilc?input to the CY7B173 and CY7B174 will
be pulled LDW before the next cIock rise.
If WE is LOW at the next clock rise, infonnation presented at Do
through Ds will be stored into the location specified by the address
advancement logic. Because the CY7B173 and CY7B174 are commonl/O devices, the output enable signal (trn) mustbe deasserted
before data from the CPU is delivered to Do through Ds- As asafety precaution, the data lines (Do through Ds) are three-stated in
the cycle where WE is sampled LOW, regardless of the state of the
OEinput.
Single Write Aceesses Initiated by ~
This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1)
1 and"CSl
0, (2)
ADSC is LOW, and (3) WI! is LOW. ADS'C trigger accesses are
completed in a single clock cycle.
<:so =
Al4 is stored into the address advancement logic and delivered to
the RAM core. If the output enable (l:m) signal is asserted
(LOW), data will be available at DO through Ds a maximum of 14
ns after clock rise.
Burst Sequences
The CY7B173 provides a 2-bitwraparoundcounter implementing
the Intel 80486 sequence (see Thble 1). Note that the burst se,
quence depends on the location of the first burst address.
Table 1. Counter Implementation for the Intel 80486 Sequence
First
Address
Az
AX+l
Second
Address
Ax
AX+l
0
1
0
0
0
1
0
0
1
1
0
1
1
0
1
Third
Address
Az
AX+l
1
0
1
1
0
0
1
0
1
Fourth
Address
AX+l
1
1
0
0
As
1
0
1
0
The CY7B174 provides a two-bit wraparound counter implementing a linear sequence (see Table 2).
=
Table 2. Counter Implementation for a Linear Sequence
Second
Address
Ax
AX+l
1
0
1
0
1
1
First
Address
Ax
AX+l
Tbird
Address
Ax
AX+l
1
0
1
1
Fourth
Address
Ax
AX+l
1
1
The address atAo through Al4 is loaded into the address advancement logic and delivered to the RAM core. Infonnation presented
at Do through Ds will be stored into the location specified by the
address advancement logic. Since the CY7B173 and CY7B174 are
common I/O devices, the output enable signal (UP:) must be deasserted before data from the cache controller is delivered to Do
through Ds. As a safety precaution, the data lines (Do through
OS) are three-stated in the~where WI!is sampledLOWregardless of the state of the "DE input.
Application Example
Single Read Accesses
Figure 1 shows a 128-Kbyte secondary cache for the i486 using four
A single read access is initiated when the following conditions are
satisfied at clock rise: (1)
= 1 and 'CSl = 0, (2) AI5SP or
AI5SC is LOW, and (3) WE is HIGH. The address at Ao through
<:so
I
osc
0
0
0
1
1
0
0
1
ClK
ADR
DATA
AOR
DATA
ADSI
~
MATCH
0
WE
liii~
I
CLK lIDSC 7ilN
~
DATA I---
1
78173
7ilN
llE
r
CO
1
--
~
1486
ADR
0
0
0
0
0
1281(8
I--
CLK
0
0
1
CY7B173 cache RAMs and a CY7B181 cache tag. Address from
the i486 is checked by the cache tag at the beginning of each access.
Match reset is delivered to the cache controller after 12 ns.
CLK
78'81
1
llE WEo WE, wq WE'a
ADR
DATA
~
co~I1KeR
MATCH
DIRTY
DIRTY
VALlO
VAUO
Figure 1. Cache Using Four CY7B173s
2-286
-
INTERFACE TO
MAIN MEMORY
PRELIMINARY
CY7B173
CY7B174
Pin Definitions
Signal Name
Ao -
Addresslnputs
CLK
I
Clock
WE
I
Write Enable
OE
I
Output Enable
CSo,CS1
I
Chip Select
ADV
I
AddressAdvance
ADSP
I
ProcessorAddressStrobe
ADSC
I
Cache Controller Address Strobe
Do-D8
Vee
Vss
VeeQ
VSSQ
RESV
•
Description
I/O
I
A14
I/O
DataI/O
-
Ground
+5V Power Supply
Output Buffer (Driver) Power Supply
-
Output Buffer (Driver) Ground
-
Reserved
Pin Descriptions
Input Signals
CLK
Clock signal used as the reference for most on-chip operations.
ADSP
Address strobe signal from the processor: ADSP is asserted when the processor address is valid. IfADSP is LOW at
clock rise, the address at Ao through A 14 will be loaded into the address register and the address advancement logic.
The write signal, WE, is ignored in the clock cycle where ADSP is asserted. Ifboth ADSP or ADSC are active at clock
rise, only ADSPwill be recognized.
ADSC
Address strobe signal from the cache controller: ADSC is asserted when a new address generated by the cache controller is ready to be strobed into the CY7B173/4. The write signal, WE, is recognized in the clock cycle where ADSC
is asserted. If both ADSP and ADSC are active at clock rise, only ADSP will be recognized.
Ao -A14
Address lines: These address inputs are loaded into the address register and the address advancement logic at clock
rise ifADSP or ADSC is LOW. They are used to select one of the 32K locations.
WE
Write Enable: This signal is sampled at the rising edge of the clock signal. If WE = 0, a self-timed write operation will
be initiated and data on Do - D8 will be stored into the selected memory location. The only exception occurs ifboth
ADSP and WE are LOW at clock rise.ln this case, the write signal is ignored.
ADV
Address Advance input: ADV is sampled at the rising edge of the clock. In the case of the CY7B173, LOWatthis
input will advance the address in the advancement logic according to the lntel80486 burst sequence. In the case of
the CY7B174, the addresses will be advanced linearly. This input is ignored if ADSP or ADSC is active (LOW).
CSo - CSt
Chip Select inputs: CSo is active mGH and CSt is active LOW. Both inputs are sampled at clock rise if ADSP or
ADSC is LOW. The RAM is selected if CSo = 1 and CSl = O.
OE
Output Enable - OE is an asynchronous signal that disables all output drivers (Do - Ds) when it is deasserted. OE
should be deasserted during write cycles because the CY7B173,/4 is a common I/O device and three-state conflict
may occur at the data pins.
RESV
Reserved
Bidirectional Signals
Do-D8
Data I/O lines: During a read cycle, if OE is asserted, data in the selected location will appear at these pins. During a
write cycle, data presented at these pins is captured at clock rise and stored into the selected RAM location if WE is
LOW. All nine outputs will be placed in a three-state condition when OE is deasserted, when the RAM is deselected
via the chip select inputs, or during a write cycle.
2-287
JL~
~-CYPRESS
~,
CY7B173
CY7B174
PRELIMINARY
SEMICONDUCIDR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
Static Discharge Voltage......................... >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
Storage Temperature .................. - 6S 0 Cto +1S0°C
Operating Range
Ambient Thmperaturewith
PowerAppJied ........................ - SSOCto +12SoC
Supply Voltage on Vee Relative to GND .... - O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ..................... - O.5V to Vee + O.SV
DC Input Voltagel1] ................. - O.5V to Vee + O.SV
CurrentintoOutputs(LOW) ....................... 20rnA
Ambient
Thmperature[2]
Vee
O°Cto +70°C
SV± 10%
- 55°C to +125°C
SV± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operating Range
7B173-14
7B174-14
Parameters
Description
Thst Conditions
Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
Input LOWVoltagel) ]
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrend3]
Vee Operating
Supply Current
VOH
VOL
VIR
VlL
Irx
loz
los
lee
Min.
Max.
Min.
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
GND.$. VI.$. Vee
GND.$. VI.$. Vee,
Output Disabled
Vee = Max., VOUT = GND
I
Com'l
Units
2.4
0.4
2.2
-0.5
-10
-100
Vee = Max., lOUT = 0mA,
f = fMAX = litRe
7B173-18,21
78174-18,21
V
V
V
V
0.4
2.2
-0.5
-10
-100
Vee
0.8
+10
+100
Vee
0.8
+10
+100
JlA
JlA
-300
-300
rnA
210
210
230
rnA
I Mil
Capacitance [4]
Parameters
Description
Thst Conditions
InputCapacitance
CIN: Addresses
TA=25°C,f=1MHz,
Vee=S.OV
CIN: Other Inputs
Output Capacitance
CoUT
Notes:
1. VIL (min.) = - 1.5V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. Not more than 1 output should he shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Max.
Units
4.5
pF
6
pF
13
pF
4. Thsted initially and after any design or process changes that may affect
these parameters (PLCC package).
AC Test Loads and Waveforms
OUTP~~31R1481Q
R1481Q
5V31
OUTPUT
85pF
I _2550
R2
INCLUDING
JIG AND SCOPE
-
5 PF
,OV~
10%
90%
R2
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
_ 255Q
-
GND
,;;3ns
J'e.:
10%
__
,;;3n8
8173-3
8173-4
(b)
THEvENIN EQUIVALENT
16nl
OUTPUT 00-_ _....._ _--00 1.73V
2-288
~---~
=----:~
~=CYPRESS
~F SEMICONDUCTOR
Switching Characteristics
Over the Operating Range[S]
7B173-14
7B174-14
Description
Parameters
CY7B173
CY7B174
PRELIMINARY
teYC
Clock Cycle Time
fMAX
MaximurnFrequency
Min.
Max.
20
7B173-18
7B174-18
Min.
Max.
7B173-21
7B173-21
Min.
40
50
Max.
30
25
Units
ns
33
MHz
tCH
Clock HIGH
8
10
12
ns
tCL
ClockWW
8
10
12
ns
tAS
Address Set-Up Before CLK Rise
2
4
5
ns
tAR
Address Hold After CLKRise
2
3
4
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
tADS
tADH
tWES
14
18
ns
21
ns
3
3
3
ns
ADSp, ADSC Set-Up Before CLK Rise
3
4
5
ns
ADSp, ADSC Hold After CLK Rise
2
3
4
ns
WE Set-Up Before CLKRise
3
4
5
ns
tWEH
WE Hold After CLK Rise
2
3
4
ns
tADVS
ADVSet-UpBeforeCLKRise
3
4
5
ns
tADVH
ADV Hold After CLK Rise
2
3
4
ns
tDS
Data Input Set-Up Before CLK Rise
3
4
5
ns
tDH
Data Input Hold Aftcr CLKRise
2
3
4
ns
tcss
Chip Select Set-Up
3
4
5
ns
tCSH
Chip Select Hold AfterCLKRise
2
3
4
tcsoz
Chip Select Sampled to Output High Z[6, 7]
tcsov
Chip Select Sampled to Output Valid
tEOZ
OEHIGH to Output High Z[6]
7
9
11
ns
tEOV
OE LOW to Output Valid
7
9
11
ns
tWEOZ
WE Sampled LOW to Output High Z[6]
tWEOV
WE Sampled III C; II to Output Valid
10
3
14
12
3
10
3
14
18
3
12
3
18
3
ns
14
ns
21
ns
14
ns
21
ns
Notes:
5.
6.
TestconditionsassumesignaJ transili"n time of3 nsoriess, timing reference levels ofl.5V, input pulse levels of() to 3.0V, andoutputloading
of the specified ImJIoH and 85-pF load capacitance.
tcsoz, tEOZO and tWEOZ are specified with a load capacitance of 5 pF
as in part (b) ofACThstLoads. 'Ibtnsition is measured ± 500mVfrom
steady state voltage.
7.
2-289
AI any given voltage and temperature, tcsoz (tWEOZ) min. is less than
tcsov (tWEOV) min.
•
di-n
.....-:..
PRELIMINARY
PRESS
SEMICONDUCTOR
CY7B173
CY7B174
Switching Waveforms
Single Read
ClK
CHIP
SElECTS~~~~~~~~~~~
'-----4-----J
,'-~~~~~~~~~~~~~
ADDRESS
DATA OUT
8173-6
Single 486 Write
ClK
CHIP
SELECTS ~~.;:J '------I-----.J ,~"""'~.c..;::.L~::....:::""'-~~"'_~
DATA IN
DATA OUT
8173-5
2-290
g;-~
~~CYPRESS
~
JF
PRELIMINARY
CY7B173
CY7B174
SEMlCONDUClDR
Switching Waveforms (continued)
Single Cache Controller Write
II
ClK
CHIP ..,....,,....,.....~....,.~""
SELECTS ~'--~""""''--~~
DATA IN
DATA OUT
8173-7
Burst Read Sequence with Four Accesses
ClK
CHIP
SELECTS
ADDRESS
ADSPor
ADSC
DATA OUT
8173-8
2-291
~
~~CYPRF.SS
~; SEMICONDUCTOR
PRELIMINARY
CY7B173
CY7B174
Switching Waveforms (continued)
Cache Controller Burst Write Sequence with Four Accesses Followed by a Single Read Cycle
CLK
CHIP
SELECTS
ADDRESS
ADSC
tADVS
ADV
WE
DATA IN
OE
DATA OUT
8173-9
Output (Controlled by OE)
~AO:_><_X_X_X_X_ _F~ ~
=f_____
t_tEO_"
8173-10
2-292
B~
, CYPRESS
•
CY7B173
CY7B174
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
•
Output Timing (Controlled by CS)
ClK
II)
::::E
«
a:
CHIP
SELECTS
U)
DATA OUT
CHIP SELECTS
ASSERTED
B173-11
Output Timing (Controlled by WE)
ClK
WE
tWEOV
DATA OUT
8173-12
Ordering Information
Speed
(ns)
14
18
21
Ordering Code
CY7B173-14JC
Package
lYPe
Operating
Range
Speed
J67
Commercial
14
(ns)
Ordering Code
CY7B174-14JC
Package
lYPe
Operating
Range
J67
Commercial
CY7B173-14LC
L67
CY7B174-14LC
L67
CY7B173-14YC
Y67
CY7B174-14YC
Y67
CY7B173-18JC
J67
CY7B173-18LC
L67
CY7B173-18YC
Y67
CY7B173-18LMB
L67
CY7B173-18YMB
Y67
CY7B173-21JC
J67
CY7B173-21LC
L67
CY7B173-21YC
Y67
CY7B173-21LMB
L67
CY7B173-21YMB
Y67
18
Commercial
Military
Commercial
21
Military
Document#: 38-001S4-A
2-293
CY7B174-18JC
J67
CY7B174-18LC
L67
CY7B174-18YC
Y67
CY7B174-18LMB
L67
CY7B174-18YMB
Y67
CY7B174-21JC
J67
CY7B174-21LC
L67
CY7B174-21 YC
Y67
CY7B174-21LMB
L67
CY7B174-21YMB
Y67
Commercial
Military
Commercial
Military
CY7B180
CY7B181
PRELIMINARY
CYPRESS
SEMICONDUCfOR
4K X 18 Cache Thg
Features
• Can be used as 4K x 18 SRAM
• Supports 50-MHz cache for aU mllJor
high-speed processors
• 4K x 18 tag organization
• BieMOS for optimum speed/power
Functional Description
• Highspeed
-12-n5 match delay
-IS-ns tag SRAM access
• Selectable clock and latch modes
• Input address and data latches
• Supports multiprocessing (CY7Bl80)
with two cache status bits per entry
• Supports dirty and valid bits
(CY7B181)
- Dirty-bit set on write hit
-1Wo cycles to invalidate entire tag
array
- Match qualified by valid bit
• Write output to cache RAM asserted
during write hit
• Cascadeable
- up to four cache tags with no externallogic
The CY7B180 and CY7B181 are high-performance BiCMOS cache tag RAMs organized as 4096 words by 18 bits. Each word
contains a 16-bit address tag field and a
2-bit status field. Because the CY7B180 is
optimized for multiprocessor applications
where cache coherency is important, the
two status bits are unassigned and can be
used to store multiprocessing cache status
information. Uniprocessor applications
implementing write-through or copy-back
cache policies are best supported by the
CY7B181. The two status bits are assigned
as the valid bit and the dirty bit. 1b simplify
the cache controller logic, the dirty bit is set
automatically during a write hit. The tag
field and the status field can be 10aded separately via a dedicated I/O data port.
The twelve address lines select one of the
4096 words in the tag RAM. The 16-bit tag
address is matched against data presented
at the Compare Data inputs. In the
CY7B181, the match output is qualified by
the valid bit of the chosen word Match is
asserted only if the comparison is successful and the valid bit is set. The contents of
the tag and status fields in the selected
entry are available to extemallogic as direct output pins.
In many cache systems, generating the
write signal to the cache RAMs is a timeconsuming process because the write signal must be qualified with the match signal
from the cache tag. The CY7BI80/
CY7B181 incorporates this function
on-chip by asserting the write output
(WO) whenever a write hit is detected.
Tag invalidation in the CY7B181 is controlled by the INVAL input. Holding this
input LOW for two consecutive cycles will
invalidate the entire tag RAM. Individual
entries can be invalidated by writing a zero
into the valid bit of that entry.
With a match delay of 12 ns and selectable
clock or latch mode, the CY7B180 and
CY7B181 can be used with all major
high-speed microprocessors currently offered The IS-ns address access of these
parts also allows them to be used as 4K by
18 cache data RAMs.
Logic Block Diagrams
MODE
CLII/LE
MODE
CLII/LE
-;u....
CY7B180
;::11
CY7B181
DATA
REG!
LATCH
r----
.--
I~:&I--
ISoUI---
'il~
L-
11-- wo
....
MATCH
78180-1
I
MATCH LOGIC
-
I>-wo
...
0
SWR
l==a.
....
V
1WR
~
LOGIC
....
DATA
REG!
LATCH
i
MATCH
7Bl80-2
=--.
~
CY7B180
CY7B181
PRELIMINARY
~iEcyPRESS
- , F SEMICONDUCTOR
Pin Configurations
•
LCC & PLCC
Top View
9 8 7 6
A7
10
Ao
Ao
Ai0
11
12
13
A11
14
COo
15
I I)
5 4 3 2 1 6B 6766 85 54 53 62 61
:::E
cr:
a::
60
59
58
57
56
55
54
53
02
DIRlY/S,
MATCH
Do
04
Ds
06
0-,
(/)
CD1
16
C02
CD.
CD4
CD.
17
18
52
Vss
19
20
51
50
WO
CDe
21
49
Vss
CD7
22
48
VALID/So
Os
CD.
CDg
CD10
23
24
25
47
Do
46
010
CD11
26
45
44
011
012
V~~OO~~~M~M~M$~~~~
.--.- .-.-;:; 01...J4I1"''''OI~I!!'IW
I~ 0
N(,)
¢Il)WW
8888
a~i
(IJ
»
(J
UJ
7B180-3
............. (I)
00
It)vC')
000
>
PGA
Top View
51
C012
53
C010
55
CD.
57
CD.
59
52
CD11
65
67
Ao
68
~
Vss
41
TWR
40
SWR
39
DE
M
0,.
37
0,.
M
0,.
35
Vss
~
0'0
30
08
~
58
60
CD.
AlO
49
47
45
C014 f;LK/LE INVAL*
Vee
56
61
63
~
44
fS
CD7
CO.
COo
48
46
C015 MODE
54
CD.
CO_
CO2
50
C013
WO
7B180/1
CPGA
26
Vss
24
62
34
0'2
33
011
31
Do
29
VALIDI
So
27
Vss
25
DIRTYI MATCH
CD,
5,
64
22
23
A11
D.
07
66
Ag
20
D_
O.
137
139
141
A7
Ao
Ao
Ag
•
138
Ag
A3
1~
1~
A,
1~
Ao
144
Vee
145
Vss
146
Cs"
147
CS.
148
OS,
149
OSO
150
Vee
151
Do
152
0,
18
D.
21
19
Do
17
vss
78180-4
• Note: The INVAL input is only available on the CY78181
Selection Guide
7BI80-12
7B181-U
12
275
Match Time (ns)
Maximum Operating Current (rnA)
I
I
Commercial
Military
2-295
7B180-15
7B181-15
15
275
290
7B180-20
7B181-20
20
275
290
-=-:~
_
F' .
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Functional Description (continued)
Clock Mode
The CLOCK mode is selected when the MODE input is LOW. The
address, compare data, chip select, and tag select are sampled at
the rising edge ofCLK. Write data is sampled on the falling edge of
CLK. The tag write and status write inputs are different in thatthey
arelevelsampled by CLK. If CLKis HIGH, the input latches associated with the tag write and status write inputs are transparent,
and these inputs are allowed to ripple into the CY7B180/
CY7B181. These inputs are latched when CLKgoes LOW.
Latch Mode
The LATCH mode is selected when the MODE input is HIGH. All
inputs are level sampled by LE. If LE is high, the input latches are
transparent and the inputs are allowed to ripple into the
CY7B180/CY7B181. When LE goes LOW, the inputs are latched
and are no longer sampled.
ThgStorage
The CY7B180/CY7B181 provides 4096 cache tag entries. Each
7B181 entry contains a 16-bit cache tag address, a valid (V) bit, and
a dirty (D) bit. The same two bits in the CY7B180 are generic status bits, and their meanings must be interpreted and controlled by
the external processor.
On the CY7B181, the valid bit specifies the validity of the tag entry.
A match is detected only when the 16-bit tag of the selected entry
matches the 16 compare inputs and the valid bit is set. The dirty bit
on the CY7B181 indicates whether the cache line associated with
the tag entry has been modified and its value is available to external
logic as the DIRTY output. The D bit in a selected entry on the
CY7B181 is set if the current access is a write and a hit is detected.
The valid bit in the selected entry is also available as the VALID
output so that external logic can determine the cause of a miss:
• If the V bit is HIGH, then the miss is caused by tag mismatch.
• If the V bit is LOW, then the miss is caused by either a tag
mismatch or an invalid, or both.
The cache tag entry format is shown in Figure 1.
ThgCompare
A tag compare cycle is initiated if tag select (TS) is HIGH. TS is
sampled at the rising edge of CLK (in the clock mode) or captured
by the positive level of LE (in the latch mode). Once a tag entry is
selected by Ao through All, its 16-bit tag address is compared
against CDo through CDlS. The compare result is delivered to the
match logic.
The match output of the CY7B180 is driven HIGH ifthe compare
is successful. For the CY7B181, the compare result is qualified by
CY7B180
CY7B181
the state ofthevalid (V) bit in the selected entry. MATCH is driven
HIGH only when the compare is successful and the valid bit is set.
In addition, the write output (WO) of the CY7B180/CY7B181 is
assertedwhenever a match is detected in a CPU write cycle (TS =
1 and TWR = 0). In some applications, this signal may be connected directly to the write input of the cache RAM.
Tag Access
The tag access cycle is initiated by asserting the tag select (TS) input. Reading and writing is controlled by the tag write (TWR) and
statuswrite (SWR) inputs. In both clock and latch modes, the state
of TWR and SWR are captured by the positive level of the CLK!
LE input. The MATCH and WO outputs remain HIGH during tag
access cycles.
IfTWR is HIGH, the tag address field ofthe selected entry is driven onto data lines Do through DIS provided output enable (OE) is
LOW. For the CY7B180, the state ofthe two generic status bits are
available at the So and SI outputs if SWR is HIGH. For the
CY7B181, the valid and dirty bits of the chosen entry are driven
onto the valid and dirty outputs if SWR is HIGH.
Changing the tag content is accomplished by asserting the TWR
and SWR inputs. TWR controls theloading ofthe tag address field
while SWR controls the loading of the status field (So, SI in the
CY7B180, valid and dirty in the CY7B11l1l Because the
CY7B180/CY7B181 are common I/O devices, OE must be driven
HIGH before data is placed on the data inputs and the status inputs.
Cascade Operation
Up to four CY7B180/CY7B181s can be used in a system by connecting appropriate address lines to the four chip select inputs. A
cache tag is selected only if CSo = CSI = 0 and CS2 = CS3 =1.
Once selected, the CY7B180/CY7B181 will either execute a tag
com~ison cycle or a tag access cycle (depending on the state of
the TS input). If a cache tag is deselected, it disables the comparisonlogicand three-states match, valid, dirty, WO, and Disthrough
Do outputs.
The four chip selects are sampled at the positive edge of CLK (in
clock mode ) or sampled by the positive level ofLE (in latch mode).
By connecting the chip selects to the appropriate address bits or
logiclevels (see Table 1 and Figure 2), four CY7B180/lscan be cascaded to provide 16,384 tag entries with no external logic.
Pin Descriptions
The cache tag RAM is packaged in a 68-pin PGA, PLCC, and LCe.
The following sections are brief descriptions of the pin functions:
Supplies
Vcc-3 pins, connected to the +5V power supply.
GND-6 pins, connected to ground.
Input Signals
Tag Address-16 bits
Tag Address-16 bits
7B180-5
Figure 1. Cache Thg Entry Format
Au - Ao--Address from the processor, 12 pins. These inputs are
registered/latched and are controlled by CLK/LE. In the clock
mode, the register is positive-edge triggered. In the LATCH mode,
the latch is positive-level triggered. While in LATCH mode, if the
LE input is HIGH, the latch is transparent and the addresses are
allowed to ripple into the CY7B180/CY7B181 to start a new access. These 12 address inputs are used to select one of the 4096
cache tag entries.
2-296
CY7B180
CY7B181
PRELIMINARY
Table 1. Cbip Select Connections for Caseading Four Caebe Tags
Tag 1
Tag 2
CS3
H
CSz
H
CSl
Adr
X+l
~
Adr
X
CS3
H
CSl
Tag 3
Signal
CSo
CSl
Adr
X
Pin Summary
CS3
CSz
~l
H
Adr
X+l
L
~
Adr
X
All-
~l
~O
CLK/LE
I
1
L
L
MODE
I
1
Mode Select
CDlS-CDO
I
16
Compare Data
Chip Selects 1 & 0
= ll.
rna
I
2
CS3 - CS2
I
2
Chip Selects 3 & 2
TS
TWR:
I
1
'ThgSelect
I
1
'Thg Write Signal
~
I
1
Status Write Signal
JliWAL
I
1
'Thf, Invalidate (CY7BI81
ony)
MATCH
0
0
1
Cache Match
1
Cache Write Match
'CSl
= I.H
= HI..
= HH
MATCH
VALID
DIRTY
-
WO
VALID/SO
I/O
1
Valid/Status Bit 0
DIRTY/SI
I/O
1
Dirty/Status Bit 1
"CSo
DIS - Do
I/O
16
Processor Data
"CS",
00
I
1
Output Enable
TAG3
"CS"o
"CS",
CS2
CS3
TAG4
"CS"o
"CS",
Ax
Qock/Latch
CSl
CS2
CS3
+,
'ThgAddress
Adr
X
TAG2
Ax
Ground
12
CS3
TAG1
CS2
CS3
6
I
Adr
X+l
'Thg 1 is selected when Adr X +1. Adr X
'Thg 2 is selected when Adr X +1. Adr X
'Thg 3 is selected when Adr X + 1. Adr X
'Thg 4 is selected when Adr X + 1. Adr X
"CS"o
"CS",
Description
+SV
Ao
GND
Tag 4
#of
Pins
3
Vee
Adr
X+l
L
Dir.
CS2
CS3
Figure 2. Cascading the CY7BI80 and CY7BI81
Pin Descriptions (continued)
MODE-Mode select. 1 pin. The clock mode is selected by strapping the MODE input LOW. The latch mode is selected by strapping this input HIGH.
CLKILE--Qock/Latch input, 1 pin. This input controls all input
registers and latches.
CD15 - CDo-Compare data. 16 pins. These inputs are registered!Iatched by CLK/LE. In the clock mode. the register is positive-edge triggered. In the latch mode. the latch is positive-level
triggered. While in the latch mode. if the LE input is HIGH, the
latch is transparent and the compare data is allowed to ripple into
the CY7BI80/CY7B181 to the comparison logic. The contents of
the compare register!1atch are compared with the 16-bit tag address in the selected tag entry.
CSo - ~l-Chip select 0 - 1. active LOW, 2 pins. These input~
are registered!latched by CLK/LE. In the clock mode. the register
is positive-edge triggered. In the LATCH mode. the latch is positive-level triggered. While in the LATCH mode. if the LE input is
HIGI t. the latch is transparent and the chip select '!!puts are allowed to ripple into the CY7B180/CY7B181. If CSt> ~ are
LOW and CSz. CS3 are HIGH. the comparison logic and output
drivers are enabled, otherwise. the comparison logic will be disabled and all output drivers will be three-stated.
CS1, CS3-Chip select 2 - 3, active HIGH, 2 pins. These inpul~
are registered/latched CLK/LE. In the clock mode. the register is
positive-edge triggered. In the latch mode, the latch is positive-level triggered. While in the latch mode. if the LEinput is HIGH. the
latch is transparent and the chip select inputs are allowed to riJ:lQ!.c
into the CY7B180/CY7B181. IfC~. CS3 are HIGH and CSt> CSo
2-297
•
CY7B180
CY7B181
PRELIMINARY
are LOW, the comparison logic and output drivers are enabled,
otherwise, the comparison logic will be disabled and all output
drivers will be three-stated.
~'Thgselect, active LOW, 1 pin. This input is registered/latched
by CLK/LE. In the clock mode, the register is positive-edge triggered In the latch mode, the latch is positive-level triggered
While in the latch mode, if LE is HIGH, the latch is transparent
and the 1'8 is allowed to ripple into the CY7B180/CY7B181. IfTS
is LOW, extemallogic is allowed to modify (read or write) the tag
entries. If TS is HIGH, the tag entries are available only for address comparisons.
lWR-'Thgwrite indicator, active LOW, 1 pin. This inputislatched
and is controlled by CLK/LE. In both the clock and latch modes,
the latch is positive-level tr~d While CLKILE is HIGH, the
latch is transparent and
is allowed to ripple into the
CY7B180/CY7B181. TWIr is handled according to the access
mode: .!!!B access mode or tag compare mode. In the tag access
mode (TS = 0), TWIr controls the access direction of the tag: a
HIGH indicates areadwhile a LOWindicates a write. Assertionof
TWR will store data on 015 through Do into the 16-bit tag address
field of the selected entry. In the tag compare mode (TS = 1) ofthe
CY7B181, TWR determines the setting of the dirty bit in the se·
lected tag entIyLtile 0 bit is set if a tag match is detected and TWR
is LOW. The'l'WR: input of the CY7B180 is ignored in the tag compare mode; the status bits So and SI are not modified.
SWR~tatus write indicator, active LOW, 1 pin. This input is
latched by CLK/LE. In both the clock and latch modes, the latch is
positive-lev~ered. While CLK/LEisHIGH, thelatchis transparent and
is allowed to ripple into the CY7B180/CY7B181.
SWR is handled according to the accessmode:!!!6 access mode or
tag compare mode. In the tag access mode (TS = 0), SWR: controls the access direction of the status bits in the selected tag: a
HIGH indicates a read while aLOWindicates awrite. Assertion of
~ will store the data presented at the status inputs into the status bits of the selected entry. In the tag compare mode (TS = 1),
the state of~ is ignored.
IiWAL-'Thg invalidate input, active LOW, 1 pin. This input is only
available in the CY7B181. It is registered at the rising edge of
CLK/LE. Assertion ofrnvAL overrides all other operations and
clears all of the valid bits in the tag storage. The CY7B181 does
not have to be selected to do an invalidation. An invalidation reo
quires two cycles to complete; therefore, theINVALinputmustbe
held for two rising edges of the CLK or LE.!!8!tal. If the INVAL
input is asserted, MATCH is forced LOW, WO is forced HIGH,
VALID is forced LOW, DIRTY goes to an unknown state, and the
data outputs (Do through 015) go to an unknown state. The INVAL input must be asserted during power-up to ensure that all of
the valid bits in the tag are cleared. The contents of the tag may be
modified as a result of invalidation.
UE-output enable, 1 pin. When "OIl: is HIGH, all outputs except
match will be placed in a three-state condition. This pin must be asserted before the beginning of a tagwrite cycle to allow the external
processor to drive data into the CY7B180/CY7B181.
Output Signals
O)iNV£
This output is HIGH duri~ access cycles (TS =
on the CY7B181 when the INVAI: input is asserted. Ifthe
input on the CY7B181 is asserted, the match output is forced
LOW. Match is placedina three-state condition when the tag is de·
selected via the chip select signals. 'DE has no effect on the match
output.
Wl>-Cache write match signal, active LOW, one pin. A LOW at
this pin indicates a cache hit during a memory write. A HIGH indi·
cates a cache miss during a me~ write. the rnvAL input 0!l
the CY7B181 is asserted, the WO output 18 forced HIGH. Th18
output is HIGH during all tag access cycles (TS = 0). WO is placed
in a three-state condition when the tag is deselected via the chip se·
lect signals or when "OIl: is HIGH.
Input/Output Signals
I!
D15-Do-Data lines to/from th~ocessor,16 pins. Thes~ns
are used during both tag access (TS = 0) and tag compare (TS =
1) cycles. During tag reads or tag compares, the tag address fiel~ of
the selected tag entry is driven onto these lines. If the 'iN"V'AL m·
put on the CY7B181 is asserted, the data outputs will go to an unknown state. During tag writes, the 'DE input must be deasserted
to three·state the output drivers so that these pins may be driven
by the external processor. The data inputs are registered/latched
by the CY7B180/CY7B181. In the clock mode, th~ regis~~r is neg·
ative-edge triggered. In the latch mode, the latch 18 posltlVe·lev~1
triggered. While in the latch mode, if LE is HIGH, the latch 18
transparent and the data is allowed to ripple into the CY7B180/
CY7B181. All 16 outputs will be placed in a three-state condition
if the "OIl: input is deasserted (HIGH) or when the cache tag is de·
selected via the four chip select inputs.
VALID/So-Valid bit (active HIGH) in CY7B181, status bit So i.n
CY7B180,1 pin. Duringtagcomparisonandstatus read cycles, thIS
pin reflects the state of the Valid bit (in CY7B181) or status bit..§)
(in CY7B180) of the selected entry. During status write cycles (TS
andSWR"LOW), data presented atthis pin is registered/latched. In
the clock mode, the register is negative-edge triggered. In the latc;h
mode, the latch is positive-level triggered. This pin can be placed. m
a three·state condition via the chip select and output enable signals. If the INVALinputofthe CY7B181 is asserted, the VALID
output is forced LOW.
DIR1Y/SI-Dirty bit (active HIGH) in CY7B181, status bit SI in
CY7B180, 1 pin. During tag comparison and status read cycles,
this pin reflects the state of the Dirty bit (in CY7B181) or status
bit SI (in CY7B180) of the selected entry. In copy-back caches using the CY7B181, the cache ~ntrollercan examine this outpu~ to
determine whether the cache Ime to be replaced should be co~
back to the main memory. During status write cycles (TSand
LOW), data presented at this pin is registered/latched. In the clock
mode, the register is negative-edge triggered. In the latch m~de,
the latch is positive-level triggered. This pin can be placed m a
three-state condition via the chip select and output enable signals.
If the JIiroAL input of the CY7B181 is asserted, the Dirty output
will enter an unknown state.
MATCH-Cache match signal, active HIGH, 1 pin. A HIGH at
this pin indicates a cache hit while a LOW indicates a cache miss.
2-298
PRELIMINARY
CY7B180
CY7B181
Application Examples
Figure 3
A 128-Kbyte cache for a single 68040 using
four CY7B174 cache RAMs and a CY7B181
cache tag. Thecomplexity ofthe cache controller is reduced because the CY7B181 generates
the write enable signal to the RAM automatically during write hits.
128KB
J
OSC
CY7B174
CLK
ADR
DATA
CLK
ADR
DATA
ADSP
--rOE
fS
WE
ADSC
wr
68040
WE
----,
ADSC ADV
CLK
A
CD
~
OE
DATA
I
DE
CLK
ADR
DATA
ADSP
r-
11
WEo
WE,
WE. WE;,
CACHE
CONTROLLER
DE
MATCH
MATCH
DIRTY
CY7B181
WE
VAliD
t
7B180-7
MAIN MEMORY BUS
128KB
Figure 4
A 128-Kbyte secondary cache for a single i486
using four CY7B173 cache RAMs and a
CY7B181 Cache Tag. Address from the i486 is
checked by the cache tag at the beginning of
each access. Match result is delivered to the
cache controller after 12 ns.
I
OSC
CY7B173
CLK
ADR
DATA
ADS
CLK
ADR
DATA
ADSP
-[OE
m~
,.!'E
ADSC
i486
----,
ADSC ADV
CLK
A
CD
DATA
OE
MATCH
DIRTY
CY7B181
VAliD
~
CLK
ADR
DATA
ADSP
DE
MATCH
WE
I
OE
i1
WE"
WE,
WE. WE.
CACHE
CONTROLLER
t
MAIN MEMORY BUS
2-299
7B180-8
•
CY7B180
CY7B181
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelioes,
nottested.)
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied....................... - 55°Cto +125°C
Supply Voltage on Vee Relative to GND ... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .................... - O.5V to Vee + O.5V
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .......................... . . >200 rnA
Operating Range
Ambient
Thmperature[2j
Range
O°Cto +70°C
Vee
5V± 10%
- 55°Cto +l25°C
5V± 10%
Commercial
Military
DClnputVoitagel1j .............. - O.5Vto +Vee + 0.5V
Current into Outputs (LOW) ...................... 20 rnA
Electrical Characteristics Overthe Operating Raoge
7B180-12
7B181-12
Parameter
Description
Thst Conditions
Min.
Max.
7B180-1S,20
7B181-15,20
Min.
Max.
Units
VOH
Output HIGH Voltage
Vee = Min., IOH = -2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 4.0 rnA
VIH
Input HIGH Voltage
2.2
VIL
Input LOWVoitagel1j
-0.5
0.8
IJX
Input Load Current
GND.$. VI.$. Vee
-10
+10
IOH
Output HIGH Current
Vee = Min., VOH = 2.4V
-2.0
-2.0
rnA
IOL
Output LOW Current
Vee = Max., VOL = O.4V
4.0
4.0
rnA
loz
los
Output Leakage Current
GND.$. VI.$. Vee, Output Disabled
-10
Output Short Circuit Current[3]
Vee = Max, VOUT = GND
Icc
Vee Operating Supply
Currentl4]
Vee = Max.,
!mrrMATCH= 0mA,
OE HIGH, f = fMAX = 1/tcye
2.4
0.4
I Com'l
V
2.4
0.4
V
-0.5
0.8
V
-10
+10
rnA
2.2
-10
V
+10
rnA
-300
-300
rnA
275
275
rnA
+10
I Mil
290
Capacitance [5]
qN
Parameters
Description
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 4.5V
Notes:
1. Vo:. (min.) = - 1.5V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. Not more than one output should be shorted at a time. Duration of the
short circuit should not exceed 30 seconds.
4.
5.
2-300
Max.
6.5
Units
pF
10
pF
Assumes 67% read cycles and 33% write cycles (50% cache hit rate).
Tested initially and after any design or process changes that may affect
these parameters.
==-ioo=:~
-'=
CY7B180
CY7B181
PRELIMINARY
CYPRF.SS
.F SEMICONDUCIDR
AC Test Loads and Waveforms
R19621l
5V <>------'w..,
3330
35PFI
-=
SCOPE -
GND
INCLUDING
JIGAND _
7B180-8
SCOPE -
Jt~:
10%
.s.3ns-.
7B180-9
7B180-10
(b) Three-State Delay Load
(a)
Equivalent to:
3'OV~00%
5PFI
R2
51 Oil
INCLUDING
JIG AND _
ALL INPUT PULSES
OUTPUT()'O--~I"""'''''''''··;·~ Vx
OllTPllT<>---P__-1
3331l
OUTPUT 0.0- - N.. V.,---o01.73V
Over the Operating Rangel6]
7B180-12
7B181-12
Parameters
Description
Min_
Max.
7B180-1S
78181-15
Min.
Max.
7Bl80-20
7B181-20
Min.
Max.
Units
tcyc
Clock Cycle Time
20
24
33
ns
tCH
ClockIDGH
8
10
13
ns
teL
Clock LOW
8
tOEDZ
OE IDGH to Output High Z[7]
7
9
12
ns
tOEDV
OE LOW to Output Valid[8]
9
11
13
ns
CWCKMODE (RE = Rising Edge, FE
10
13
ns
= FailingEdge)
tMCH
Match Valid After CLK RE
tMHID
Match Hold After CLK RE
tCSD
Status Valid After CLK RE
tSHID
Status Hold After CLK RE
tTWRwo
Write Output Valid AfterTWR LOW
12
2
15
2
12
2
20
2
15
2
20
2
11
9
12
15
ns
os
os
ns
13
ns
20
ns
two
Write Output Valid After CLK RE
tWOHID
Write Match Hold After CLK RE
tAD
Access Delay from CLK RE
tDOH
Output Data Hold After CLKRE
3
3
3
ns
tDIS
Input Data Set-Up Before CLK FE
4
5
6
ns
tDIH
Input Data Hold After CLK FE
2
3
4
ns
tTSS
TS Set-Up Before CLK RE
3
4
5
ns
tTSH
TS Hold After CLK RE
3
4
5
ns
tAS
Address Set-Up Before CLKRE
3
4
5
ns
tAlI
Address Hold After CLK RE
3
4
5
ns
tCDS
Compare Data Set-Up Before CLK RE
3
4
5
ns
tCDH
Compare Data Hold After CLK RE
3
4
5
ns
tcss
Chip Select Set-Up Before CLK RE
3
4
5
ns
3
tCSH
Chip Select Hold After CLK RE
tCSHZ
Output High Z After CLK RE
(chip deselected via CS inputs)p, 9]
tcsLZ
Output Low Z After CLK RE
(chip deselected via CS inputs)[8, 9]
2
2
15
2-301
2
5
4
11
2
ns
25
18
9
2
( /)
::E
--------
¥
r --
----------------~'
7B180-14
Chip Select TIming in Clock Mode
CLK
Chip Selects
Selecting
76180/76181
WOo 015 - Do
MATCH
So. S1 (78180)
V.D(76181)
Chip Deselect Timing in Clock Mode
ClK
Chip Selects
Deselecting
76180/76181
WO.D1S- Do
MATCH
So. S1 (76180)
V.D(76181)
7B181 'Thg Invalidation in Clock Mode
ClK
MATCH
VALID
7B180-17
2-307
fin
- - . CYPRESS
~
SEMICOND1JC1OR
CY7B180
PRELIMINARY
CY7B181
===================~~~~
Switching Waveforms (continued)
Thg Match Timing in Latch Mode (Showing a Hit)
tLRLR
tLW
tLFLR
~
LE
~
K.
tASLC
tAHLC -
XXX ~~
~VXXX
tCSLC
tcHLC -
> I~ [{"
tcOMCH
tTSMCH
tCSMCH
tLOMX
tAMCH
tLOMCH
MATCH
)(X'"')("k < >()()()0()
XXX
~~XX
It'
tTSSV
tcssv
tASV
tLOSX
tLOSV
So, S1 (7B180)
V,0(7B181)
XXX" I<
I"-
XXXX)K
KXXXX)
)
Kxx
tcsov
tAOv
tLOoX
ILOOV
)(X'"')("k < >()()()0()
IWSLC
>(XXXi\
'-I
XXX)~
!----
XX)()0~
IWHLC J
"I~XX
*>0< ~XXX XXXXX
ITWRWO
ICDWO
tTSWO
tcswo
IAWO
tLOWOX
ILOWO
XXX
KXXXX>
RX"XX'X'
IWHLC -
~
~
XXX RX"XX'X'
icsov
IADV
015 - Do,
So, 51 (7B 180)
V,D(7B181)
lLOOX
twov
XXX" 2001V
(per MIL-STD-883, Method 3015.2)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
Thmperature!2]
O°Cto + 70°C
- 55°C to + 125°C
Range
Commercial
Military
Vee
5V± 10%
5V± 10%
Electrical Characteristics Over the Operating Range
7Cl82-U
Min; Mal.
VOH
Description
Output HIGH Voltage
VeeMin.,IoH = - 4.0 rnA.
VOL
Output LOW Voltage
Vee Min., IOL = 8.0 rnA
VIH
VIL
Input HIGH Voltage
Input LOWVoitagel1J
IIX
Input Load Current
GND.!5. VIN.!5. Veo GND < VOUT < Vee,
Output Disabled
..
-10
Parameters
Thst Conditions
2.4
7Cl82-15
Min. Max. Units
2.4
V
0.4
2.2
0.4
V
-'0.5
Vee
0.8
V
+10
-10
+10
JAA
+10
-10
-0.5
Vee
0.8
-10
2.2
V
+10
JAA
~350
-350
rnA
ICom'l
170
160
rnA
IMil
180
170
MaxVee,CE1~ VIH,CE2.!5. VIL
VIN ~ VIH or VIN.!5. VII" f = fMAX
40
35
rnA
Max Vee, CEl ~ Vee - 0.3y, CEz.!5. 0.3y,
VIN ~ Vee - O.3VorVIN .!5.0.3y, f = 0
20
20
rnA
Ioz
Output LeakageCurrent
Vee - Max., VOUT - GND
los
Output Short Circuit
CurrentI3]
Vee - Max., VOUT - GND
Icc
Vee Operating Circuit
Current
Vee Max., Output Current - 0 rnA,
f = Max., VIN = Vee or GND
ISBl
Automatic Power-Down
Current - TTL Inputs
ISB2
Automatic Power-Down
Current - CMOS Inputs
Shaded area contams advanced information.
Notes:
1. Vn. (min.) = - 3.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3.
2-314
Duration of the short circuit should not exceed 30 seconds. Not more
than one output should be shorted at one time.
-~
:j;; CYPRESS
CY7C182
R7
.IF SEMICONDUCTOR
Electrical Characteristics Over the Operating Range (continued)
7Cl82~20
Description
Output HIGH Voltage
Vee Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee Min., IOL = 8.0 rnA
VIH
VIL
Input HIGH Voltage
Input LOW Voltagel 1J
IJX
Input Load Current
Ioz
Parameters
VOH
Thst Conditions
7C182-25, 35, 45, 55
Min. Max.
2.4
Min.
2.4
Max.
Units
V
0.4
V
2.2
V
iAA
0.4
2.2
-0.5
Vee
0.8
-0.5
Vee
0.8
GND~ VIN~ Vee,GND < VOUT< Vee,
Output Disabled
-10
+10
-10
+10
Output LeakageCurrent
Vee - Max., VOUT - GND
-10
+10
-10
los
Output Short
CircuitCurrent[3]
Vee- Max., VOUT - GND
Icc
Vee Operating Circuit
Current
ISBl
Automatic Power-Down
Current- TIL Inputs
CEz ~ VIL VIN ~ VIH or
IsB2
Automatic Power-Down
Current - CMOS Inputs
V
+10
iAA
-350
-300
rnA
VeeMax.,OutputCurrent-OmA, Com'l
f=Max.,VIN=Veeo rGND
lMil
150
140
rnA
160
150
Max Vee, CEl ~ VIH,
35
35
rnA
20
20
rnA
I
VIN ~ VIL, f = fMAX
MaxVee,CEl~ Vee CEz~0.3V, VIN ~ Vee
VIN~0.3V, f = 0
0.3v,
- O.3Vor
Shaded area contams advanced information.
Capacitance [4]
Description
Thst Conditions
CoUT
Output Capacitance
qN
InputCapacitance
TA=25°C,f= 1 MHz,
Vee = 5.0V
Parameters
Units
Max.
10
pF
10
pF
Note:
4. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
R1481Q
OUTP~~31
5V~
OUTPUT
30pF
INCWDING
JIG AND
SCOPE
R2
255Q
I _
-
-
5pF
.OV~90%
R2
255Q
INCLUDING _
JIG AND SCOPE
_
Cl82-4
(b)
(a)
Equivalent to:
I
ALL INPUT PULSES
10%
THEvENIN EQUIVALENT
16m
OUTPUToo--_¥",;_ _-QO 1.73V
2-315
GND
s5ns ....
~
10%
....
s5ns
Cl82·5
•
'.~PRFSS
~
CY7C182
SEMlCONDUCTOR
Switching Characteristics Over the Operating Range
7C182"';i2
Parameters
DesCription
Min.
Max.
7Cl82-15
'Max.
Min.
7Cl82-20
Min;
Max.
Units
READ CYCLE[S)
12
15
tRC
Read Cycle Time
tM
Address to Data Valid
tOHA
Address Valid to Low Z
tACEI
CEI Access Time
12
tACE2
C~ Access Time
12
tLZCEI
CEI LOW to Low Z
3
3
20
,12
15
3
3
ns
20
5
,
ns
ns
15
20
ns
15
20
ns
3
3
ns
tLZCE2
C~HlGHtoLowZ
tHZCEl
CEI HIGH to High Z[6)
7
8
8
tHZCE2
CE2 LOW to High Z[6)
7
8
8
tpu
CEI LOW to Power-Up
tpo
CEI HIGH to Power-Down
12
15
20
ns
tOOE
OE Access Time
6
7
10
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High z[6]
3
0
0
0
0
0
7
ns
3
ns
3
8
ns
ns
8
ns
WRITECYCLE[7)
twc
Write Cycle Time
12
15
20
ns
tSA
Address Set-Up Time
0
0
0
ns
tAW
Address Valid to End of Write
9
10
15
ns
tso
DataSet-UpTime
6
7
10
ns
tSCEI
CEI LOW to Write End
8
10
15
ns
tSCE2
CE2 HIGH to Write End
8
10
15
ns
tpWE
WE Pulse Width
8
10
15
ns
tRA
Address Hold from End of Write
0
0
0
ns
tHO
Data Hold Time
0
0
0
ns
tLZWE
Write HIGH to Low Z[8]
3
tHZWE
Write LOW to High Z[6,8,9]
3
6
5
7
ns
7
ns
Shaded area contams advanced mformatlOn.
Note.:
5.
6.
7.
WE is mGH for read cycle.
tHZCE and lHZWE are specified with CL = 5 pF. Transitionismeasured
± 500 mV from steady state volt age.
Theintemalwritetimeoftheml'moryisdefinedbytheoveriapofCEl
LOW, ~ mGH, and WE LOW, All three signals must be asserted
to initiate a write and any signa) can terminate a write by being deas-
8.
9.
2-316
serted. The data input set-up and hold timing should be referenced to
the rising edge of the signal that terminates the write.
At any given temperature and voltage condition, tLZWE is less than
tHZWE for any given device. These parameters are sampled and not
100% tested.
Address valid prior to or coincident with CE transition LOW and C~
transition HIGH.
~
--=-.IF,~PRESS
CY7C182
.
SEMICONDUCTOR
Switching Characteristics
Over the Operating Range ( continued)
7C182-25
Parameters
Description
Min.
Max.
7C182-35
Min.
Max.
7C182-45
Min.
Max.
7C182-55
Min.
Max.
I
LUnits
READ CYCLEl5J
tRC
Read Cycle Time
tM
Address to Data Valid
tOHA
Address Valid to Low Z
tACEl
eEl Access Time
25
35
45
55
ns
tACE2
eE2 Access Time
25
25
45
55
ns
tLZCEl
eEl WW to Low Z
5
5
5
5
ns
tLZCE2
eE2 HIGH to Low Z
5
5
5
5
ns
tHZCEl
eEl HIGH to High Z[6J
20
20
25
25
tHzcE2
CEz LOW to High Z[6J
20
20
25
25
tpu
eEl LOW to Power-Up
tpD
eEl mGH to Power-Down
tDOE
OE Access Time
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6J
25
35
25
3
45
35
3
0
20
55
20
3
20
ns
ns
25
ns
25
ns
ns
3
30
25
ns
ns
0
25
20
3
ns
3
0
20
20
3
45
3
0
20
55
ns
WRITE CYCW7J
twc
Write Cycle Time
25
35
45
50
ns
tSA
Address Set-UpTime
0
0
0
0
ns
tAW
Address Valid to End of Write
20
30
40
50
ns
tSD
Data Set-Up Time
18
20
25
30
ns
tSCEl
eEl WW to Write End
20
30
40
50
ns
tSCE2
eE2 mGH to Write End
20
30
40
50
ns
tPWE
WE Pulse Width
20
25
30
35
ns
tHA
Address Hold from End of Write
5
5
5
5
ns
tHD
Data Hold Time
0
()
0
0
ns
tLZWE
Write HIGH to Low Z[8]
3
tHzwE
Write WW to High Z[6, 8, 9J
3
13
2-317
3
15
ns
3
20
25
ns
II
CY7C182
Switching Waveforms
Read Cycle No. d5, 10]
ADDRESS
€
--~
DATA OUT
PREVIOUS DATA
*-
IRC
1
lAA
v:; ==-* X
x)I(===============DA=:r:=A=V=AL=I=D=========:
C182-6
Read Cycle No. 2[5,11]
CE1
IRC
~~
~~
~
~
IACE1
IACE2
~'(.
~
IHZOE
IDOE
-
DATA OUT
HIGH IMPEDANCE
V~
Ipu
=1
SUPPLY _ _ _ _ _ _ _
CURRENT
-
1/////
IHZCE-
DATA VALID
I" " " " "
ILZCE
I---
-
ILZOE--
_lpD
50%
HIGH
IMPEDANCE
~ ICC
50%
ISS
C182-7
Write Cycle No.1 (WE Controlled)p]
1 4 - - - - - - - - - - - - - - Iwc - - - - - - - - - - - - -
ADDRESS
ISCE1
ISCE2
------------.J ' -.,..,...,...,..,......,..,"7"J....,..,..,...,...,..,..
~-----------------~w-------------------~-14------ ISA -----~
IPWE -------~
WE---------------~~~,
""1-------
,------------------
~-+----- ISD
DATA IN
------------------~
-----"*-.-J
DATAVAUD
,------------
ILZWE
DATAI/O
HIGH IMPEDANCE
DATA UNDEFINED
-1.---1'=========
C182-8
Noles:
10_ Device is continuously selectcd_ OE, CEI = VIL- CE2 = VIH_
11_ If eEl goes mGH and CE2 goes LOW simultaneously with WE
HIGH, the output remains in a high-impedance state_
2-318
~~PRFSS
~,
CY7C182
SEMICONDUcra<
Switching Waveforms (continued)
•
Write Cycle No.2 (CE ControlIed)[7, 11]
1+------------ twc - - - - - - - - - - - - - 1
ADDRESS
en
:!:
8~~~~~<
-"' >"' I~ I~
1/°15
1/0 14
1/0 13
7C1831
7C184
1/0,2
Vss
1/0.
I/O"
1/05
1/0 10
I/Og
Vo.
1/0,
1/0.
NC
19 20 21 22 23 24 25 26 27 26 29 30
>()
Vss
NC
21 22 23 24 25 26 27 28 29 30 31 32 33
..... W O U
11j
§>() >()
C183-3
C183-4
Selection Guide
MaximumAddressAccess Time (ns)
Commercial
7Cl83-20
7Cl84-20
7Cl83-25
7Cl84-25
7Cl83·35
7Cl84·35
7Cl83-45
7C184·45
20
25
35
45
35
45
14
16
Military
Maximum Output Enable Access Time (ns)
8
Commercial
10
Military
Maximum Operating Current (rnA)
..
250
Commercial
220
Military
14
16
170
140
200
160
Shaded area contams preJmunary mformation.
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ........................ - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to + 7.0V
DC Input Voltagd1j .............................. +7.0V
Output Current into Outputs (LOW) ................ 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
Range
Commercial
Militaryl2J
temperature
Vee
O°Cto +70°C
5V:t: 10%
- 55°Cto +125°C
5V:t: 10%
Notes:
1. VIL (min.) = - 3.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
2-321
•
CY7C183
CY7C184
-.£Z
. .~
~-CYPR&SS
~;
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangel3]
7Cl83~20
7Cl$4-20
Parameters
7Cl83-35
7Cl84-35
7Cl83-45
7Cl84-45
Min. Mu. Min. Max. Min. Max. Min. Max. Units
Thst Conditions
Description
2.4
VOL
Output HIGH Voltage Vee = Min·,IoH = -4.0rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
Vrn
Input HIGH Voltage
2.2
VIL
InputLOWVoltagel l J
VOH
7Cl83-25
7C184-25
2.4
2.4
0.4
-0.5
Vee
0.8
2.4
0.4
2.2
-0.5
Vee
0.8
0.4
2.2
2.2
V
0.4
V
V
-0.5
Vee
0.8
-0.5
Vee
0.8
V
lIX
Input Load Current
GND.::;. VI'::;' Vee
-10
+10
-10
+10
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND.::;. VI'::;' Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
-10
+10
f.tA
f.tA
los
Output Short
CircuitCurrent[4]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max.
loUT = ornA
Read CycldS]
Duty Cycle = 45%
Com'l
-350
-350
-350
-350
rnA
250
220
170
140
rnA
200
160
Mil
Shaded area contams prellDllllOllY information.
Capacitance [6]
Parameters
Description
InputCapacitance
OutputCapacitance
CIN
CoUT
Thst Conditions
Max.
10
10
TA = 25°C,f= 1 MHz,
Vee = 5.0V
Units
pF
pF
AC Test Loads and Waveforms
Rl48112
5V
OUTPUT
85pF
INCLUDING
JIGAND
SCOPE
r
=
R1481g
5V
5 PF
R2
25512
INCLUDING
JIGAND
SCOPE
=
r
=
3.0V
R2
255g
GND
=
10%
~5ns
C183-5
(b)
(a)
Equivalentto:
::5too%
ALL INPUT PULSES
OUTPUT
-~
Cl83.e
THEVENIN EQUIVALENT
167g
OUTPUT C>O_ _..JYy"'.-"_ _--oo 1.73V
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. At a given duty cycle, Write Cycle Icc is equal to 1.4 times Read Cycle
Icc·
6.
7.
2-322
Thsted initially and after any design or process changes that may affect
these parameters.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levelsofOt03.0V,andoutputioading
of the specified IOu'IOH and 30-pF load capacitance.
.
-
CY7C183
CY7C184
.~pRE.SS
F
SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangel3,7]
7Cl83-20
7C184-20
Parameters
Description
Min.
7C183-25
7CI84-25
Max.
Min.
Max.
7CI83-35
7C184-35
Min.
Max.
7CI83-45
7Cl84-45
Min.
Max.
Units
READ CYCLE[8]
tRC
Read Cycle Time
tAA
Address to Data Valid
20
25
tAA A 12[9]
Address to Data Valid A12
IS
17
tCE
Chip Enable to Data Valid
10
tcs
Chip Select to Data Valid
tOE
OE,,: LOW to Data Valid
tOHA
Output Hold from AddressChange
20
35
25
45
ns
35
45
ns
25
35
ns
12
15
20
ns
10
12
15
20
ns
8
10
14
16
ns
3
3
3
3
ns
tOHL
Output Hold from ALE HIGH
3
3
3
3
ns
tLZCE
CE, CSx LOW to Low Z
3
3
3
3
ns
tLZOE
OE,,: LOW to Low Z
0
0
0
0
tHZCE
CE, CSx HIGH to High Z
12
15
25
30
ns
tHZOE
OE,,: HIGH to High Z
8
9
10
12
ns
tPALE
ALE Pulse Width
8
8
10
12
ns
tSALE
Address Set-Up to ALE Low
3
4
6
8
ns
tHALE
Address Hold from ALE Low
4
4
4
4
ns
ns
WRITE CYCU;llO]
twc
Write Cycle Time
20
25
35
45
ns
tAW
Address Set-Up to Write End
15
20
30
40
ns
tsCE
Chip Enable to Write End
15
20
25
30
ns
tscs
Chip Select to Write End
15
20
25
30
ns
tso
Data Set-Up to Write End
8
10
10
ns
tHO
Data Hold from Write End
0
0
0
0
ns
tpWE
Write Enable Pulse Width
15
20
25
30
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tLZWE
WE.: HIGH to Low Z
3
3
3
3
tHZWE
WE LOW to High Z
tPALE
ALE Pulse Width
8
8
10
12
ns
tSALE
Address Set-Up to ALE Low
4
4
6
8
ns
tHALE
Address Hold from ALE Low
4
4
4
4
ns
..
10
12
15
ns
20
15
ns
Shaded area contams prehmmary information.
Notes:
8. Both WEA and WEB must be mGH for read cycle.
9. CY7C183 only.
10. The internal write time of the memory is defined by the overlap of CE,
cs,., and WE,.. All signals must be WW to initiate a write and any signal can terminate a write by going mGH. The data input set-up and
hold timing shonld be referenced to the rising edge of the signal that
terminates the write.
2-323
CY7C183
CY7C184
=ss ·~PRFSS
F
SEMICONDUCTOR
Switching Waveforms
Read Cycle No.1 (ALE = CLOC ) [11]
~---------------------
ALE
ADDRESS
ADDRESSA12
~Cl~)
----------4---------------'
DATA
l:=w
_d~~~2(ME=~~
ADDRESS
CE,
XXXX
t
ADDRESS VALID
f
~' ~XXXXXXX¥=
cs --------------_.
DATA ---------------------~:_+~:_(
~~~
DATA VALID
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J
C1B3-B
Read Cycle No.3 (ALE = HIGH) [12, 13]
ALE
ADDRESS
/#///////
i
!-------------------
tRC
------------------~--I
I'--~:::;;---__
t-------
~HA
II '
CE, CS - - - - - - - - - - - - - "
DATA _ _ _ _ _ _ _ _ _ _ _ _ _
~~~~
DATA VALID
C1B3.g
Noles:
1 L Device is continuously selected, CE and CS are Ww.
12. Address valid prior to or coincident with CE transition LOW.
13. WE is IDGH for read cycle.
2-324
CY7C183
CY7C184
==:::: ::~
•
.- CYPRESS
"
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (ALE = CWCK, WE Controlled) [14]
1/==
ALE
-----IF-...-..,........,.......,..,-"
-
tpALE
!sALE
ADDRESS
twc
~
---~~+-.;
tHALE
ADDRESS VALID
........,.......,,.......,......-:.........,...14-----
tSGE, tSGS ----~
- 1 - - - 4>wE - - - - - I
----------------~
,----------------------
DATA
G183-10
_:N" "Am =g':- ['~"__t_wc
_ _ _ _ _ _ _ _ _ ___'
=
...-..,........,.......,..,-"
-
~.:..-
tSALE
ADDRESS
-ot---CE,CS
DATA
tHALE
ADDRESS VALID
IsCE,ISCS
----I
----------------~
K
-------------------i(
Iso
,---------------------lHo
~
DATA-IN VALID
)1-----------
Cl83-11
Write Cycle No.3 (ALE = IDGH, CEICS Controlled) [14)
ALE$00/ff
~---------Iwc -----------~
ADDRESS
ADDRESS VALID
-ot----
!seE, Iscs ---~~--- IHA - - - -....~I
CE,CS ----------------~
-------------------i(K
tSD
DATA
tHO
DATA-IN VALID
~
)1-----------Cl83-12
Note:
14. OEis deselected (HIGH).
2-325
CY7C183
CY7C184
_
J.::~
-= CYPRESS
_ . , SEMlCONDUCfOR
Truth Tables
1\vo-Way Mode (Mode = IDGH)
CE
CSo
CSl
OEA
OEB
WEA
WEB
Operation
H
X
X
X
X
X
X
Outputs High Z, Write Disabled
L
H
H
X
X
X
X
Outputs High Z, Write Disabled
X
X
X
H
H
X
X
Outputs High Z
X
X
X
L
L
X
X
Outputs High Z
L
L
H
L
H
H
H
Read 1100- I/~
BaokA
L
L
H
H
L
H
H
Read 1100- I/~
BaokB
Bank A
L
H
L
L
H
H
H
Read 1I0s-I/015
L
H
L
H
L
H
H
Read I/Os-I/015
BaokB
L
L
L
L
H
H
H
Read 1100-I/015
Bank A
L
L
L
H
L
H
H
Read 1100-I/015
BankB
L
L
H
X
X
L
H
Write I/Oo-II~
Bank A
L
L
H
X
X
H
L
Write I/Oo-II~
BankB
L
H
L
X
.X
L
H
Write 1I0s - 1/015
BaokA
L
H
L
X
X
H
L
Write 1I0s - I/015
BankB
L
L
L
X
X
L
H
Write 1100-I/015
BaokA
L
L
L
X
X
H
L
Write 1100 - I/015
L
L
H
X
X
L
L
Write 1100- I/~
BanksAandB
L
H
L
X
X
L
L
Write I/Os - I/015
BanksAandB
L
L
L
X
X
L
L
Write 11020-1/015
BanksAandB
Direct Mode (Mode
BaokB
=LOW)
CE
CSo
CSl
OEA
OEB
WEA
WEB
H
X
X
X
X
X
X
L
H
H
X
X
X
X
Outputs High Z, Write Disabled
X
X
X
H
H
X
X
Outputs High Z
Operation
Outputs HighZ, Write Disabled
L
L
H
L
L
H
H
Read 1100-I/07
L
H
L
L
L
H
H
Read 1I0s-I/015
L
L
L
L
L
H
H
Read 1100-I/015
L
L
H
X
X
L
L
Write 1100- I/~
L
H
L
X
X
L
L
Write I/Os - I/015
L
L
L
X
X
L
L
Write 1100 - I/015
2-326
CY7C183
CY7C184
-~~-~
- > j E CYPRESS
-
JF
SEMICONDUCTOR
Ordering Information
Speed
Ordering Code
(ns)
Package
lYpe
Operating
Range
Speed
Ordering Code
(ns)
Package
lYpe
Operating
Range
20
CY7C183 - 20JC
J69
Commercial
20
CY7CI84-2OJC
J69
Commercial
25
CY7C183-25JC
J69
Commercial
25
CY7C184-25JC
J69
Commercial
35
CY7C183-35JC
J69
Commercial
35
CY7C184-35JC
J69
Commercial
CY7CI83-35LMB
L68
Military
CY7CI84-35LMB
L68
Military
CY7C183-45JC
J69
Commercial
CY7C184-45JC
J69
Commercial
CY7CI83-45LMB
L68
Military
CY7CI84-45LMB
L68
Military
45
Shaded area contams prelimmary mformation.
45
Shaded area contams prelImmary mformatlOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7,8,9, 10, 11
VIH
1,2,3
tAA
7,8,9, 10, 11
VILMax.
1,2,3
tOHA
7,8,9, 10, 11
IIX
1,2,3
tACE
7,8,9, 10, 11
loz
1,2,3
tDOE
7,8,9, 10, 11
los
1,2,3
Icc
1,2,3
READ CYCLE
WRlTECYCLE
twc
7,8,9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
t]fA
7, 8, 9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7,8,9, 10, 11
Document #: 38-00090-B
2-327
CY7B185
CY7B186
CYPRESS
SEMICONDUcrOR
8K x 8 Static RAM
Features
FuncUonal~scription
• BICMOS for optimum speed/power
• Ultra high speed
-9ns
The CY7Bl85 and CY7Bl86 are highperformance BiCMOS static RAMs organized as 8K words by 8 bits. These RAMs
are developed by Aspen Semiconductor
Corporation, a subsidiary of Cypress
Semiconductor. Easy memory expansion
i!J!!ovided by an active LOW chip enable
(eEl), an active mGH chip enable
~, and active LOW output enable
(OE) and three-state drivers. Both devices have a power-down feature (rnl)
that reduces the power consumption by
67% when deselected. The CY7B185 is in
the space saving 300-mil-wide DIP and
SO] package and leadless chip carrier.
The CY7B186 is in the standard 600-milwide package.
• Low active power
-750mW
• Low standby power
-2S0mW
• TTL-rompatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
An active LOW write enable signal ~
controls the writing/reading ~ation of
the memory. When
l and WE inputs
are both LOW, data on the eight data input/output pins (1100 through yo,) is
written into the memory location addressed by (Au through AI2). Reading the
device is accomplished by selec~ the
device and enabling the outputs, CEI and
1:rn active LOW, ~ active mGH, while
WE remains HIGH. Under these conditions, the contents of the location addressed by the information on the address
pins is present on the eight data input/
output pins.
The input/output pins remain in a highimpedance state unless the chip is selected, outputs are enabled, and write enable (WE) is mGH.
rn
Pin Configurations
Logic Block Diagram
DIP/SO]
Top Vi....
NC
,..,..Ao
,..,..
A7
1/0 0
A,.
A"
A,.
1/01
1/00
1/0 2
110,
1/00
GND
110a
BI86-2
1/04
1/05
1/0 6
1/0,
NC
A7
,..Ae
A,.
A"
A,.
1/00
I/O,
BI86-1
SelecUon Guide
Shaded area contains preliminary information.
2-328
4
3 2~,262726
5
6
7
6
78185
25
24
23
22
21
9
10
20
11
19
12
18
1314151617
~~g'gg'
CE.
AI
At.
A,
llE
~,
IIOr
1/00
B185-3
CY7B185
CY7B186
Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended penods may affect
device reliability. For user guidelines, not tested)
Storage Thmperature ................. Ambient Thmperature with
Power Applied ............•...•..... Supply Voltage to Ground Potential .......
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . ..
Input Voltage!l] .......•...••.......••.
65°C to +150°C
55°C to +125°C
- 0.5V to +7.0V
Output Current into Outputs (Low) ...•........... 20 rnA
Static Discharge Voltage .•••.••.••............. > 2001 V
(Per MIlrSTD-883 Method 3015)
Latch-Up Current ............••...••........ > 200 rnA
Operating Range
- 05V to + 7.0V
- 3.0V to +7.0V
Ambient
Temperature
Range
Commercial
O°Cto +70°C
Vee
SV± 10%
Military12]
- SS·Cto +125·C
5V± 10%
Electrical Characteristics Over the Operating Range!3]
78185-9
Parameters
Description
Output HIGH Voltage
VOH
Output LOW Voltage
Input HIGH Level
Input LOW Voitagel1J
Input Load Current
Output Leakage Current
Vee Operating
Supply Current
VOL
VIH
VIL
IJX
loz
lee
ISB
~El
Power-Down
Current
!
Parameters
Description
Output HIGH Voltage
VOH
Test Conditions
Vee - Min. IIoH = - 4.0 rnA I Com'l
IIOH = - 2.0 rnA Mil
Vee = Min., IOL = 8.0 rnA
GND < VI< Vee
GND S VI S Vcc. Output Disabled
Com'l
Vee = Max., lOUT = 0 rnA
f = fmax.
Mil
~El~ VIH,
Com'l
Mil
IOH = rnA
Test Conditions
I IOH = - 4.0 rnA I Com'l
IIOH = - 2.0 rnA Mil
Vee - Min., IOL - 8.0 rnA
Vee = Min.
J
VOL
VIH
VIL
IIX
loz
lee
Output LOW Voltage
Input HIGH Level
Input LOW VoltagellJ
Input Load Current
Output Leakage Current
Vee Operating
Supply Current
I~El Power-Down
ISB
Current
GND < VIS Vee
GND < VI < \fcc, Output Disabled
Com'l
Vee - Max., lOUT = 0 rnA
f = fmax.
Mil
l~l~VIH,
IOH=rnA
Com'!
Mil
Min.
7Bl85-10
Max.
2.4
2.4
2.2
-05
-10
-10
0.4
Vee
0.8
+10
+10
150
50
Min.
2.4
2.4
2.2
-05
-10
-10
Max.
Units
V
0.4
Vee
0.8
+10
+10
145
V
V
V
IJA
!lA
rnA
}~'i}I
rnA
45
rnA
rnA
t::~Ptt
78185-12
78186-12
Min.
Max.
2.4
2.4
0.4
2.2
Vee
-05
0.8
-10
+10
-10
+10
140
150
40
55
7B185-15
7B186-15
Min.
Max.
2.4
2.4
0.4
2.2
Vee
-05
0.8
-10
+10
-10
+10
135
145
Units
V
40
50
V
V
V
!lA
!lA
rnA
rnA
rnA
rnA
Shaded area contains preliminary information.
Capacitance!4]
Parameters
CIN
CoUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Notes:
1. VIdmin.) = - 3.OV for pulse width < 20 us.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group Asuhgroup testing information.
Max.lS]
6
6
Units
pF
pF
4. Thsted initially and after any design or process changes that may affect
these parameters.
S. ForallpackagesexceptCERDIP(Dl6,D22),whichhasmaximumsof
qN = 9.5 pF, qoUT = 9 pH
2-329
CY7B185
CY7B186
t77L~NDUCfOR
AC Test lAIads and Waveforms
Rl48HI
rsv 0 -_ _---'
__,
rsv <>-------W¥--,
OUTl'lITo---......---t
ClI
5PFI
R2
255&1
INCLUDING
JIGAND _
3JN ----..jj'"'.:::::----~
R2
GND
2550
_....::=r
.s3ns
INCLUDING
JIGAND _
SCOPE (a)
Equivalent to:
ALL INPUT PULSES
Ol1TPlITO---~-~
SCOPE (b)
8185-4
81115-5
THEVENIN EQUIVALENT
1670
OUTPUT 0-0--~·~.",,·---oo 1.73V
Switching Characteristics
Over the Operating Rangel3,6)
7B18S-9
Description
Parameters
Min.
7BISS-IO
Max.
Min.
Max.
7BI8S-12
7BI86-12
Min.
Max.
7BI8S-IS
7B186-1S
Min.
Max.
Units
READ CYCLE
9
15
12
tRc
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACEl
SEl LOW to Data Valid
9
10
12
15
ns
9
10
12
15
ns
4.5
5
6
8
ns
tACE2
CEz HIGH to Data Valid
tDOE
OE LOW to Data Valid
tUOE
OE LOW to Low ZlIj
tHZOE
OE HIGH to High ZLtj
tlZCEl
CEl LOW to LowZL'j
tUCEZ
CEz HIGH to Low Z18]
tHZCE
CEl HIGH to High Z[7]
CEz LOW to High Z
10
9
12
10
2.5
3
3
2
1.5
4
2
2
2
2
ns
7
3
2
2
ns
ns
3
ns
7
6
ns
ns
3
6
5
4
3
2
5
ns
15
ns
WRITE CYCLEI9]
twc
Write Cycle Time
9
15
ns
CE1 LOW to Write End
8
10
8
12
tSCE1
8
10
ns
tSCEZ
CEz HIGH to Write End
8
8
8
10
ns
tAW
Address Set-Up to Write End
8
8
8
10
ns
tHA
Address Hold from Write End
0
0
ns
Address Set-Up to Write Start
0
0
0
tSA
0
0
tPWE
WE Pulse Width
7
tSD
Data Set-Up to Write End
4.5
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[7]
0
tlZWE
WE HIGH to Low ZLb,7j
2
8
0
8
10
ns
5
6
7
ns
0
4
0
2
Notes:
6. Thst conditions assume signal transition times of 3 ns or less, timing
reference levels of l.SY, input pulse levels of 0 to 3.0V and output
loading of the specified IOlJlOH. and CL = 20 pF.
7. tHZOEo tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
ofAC Thst Loads. 'fransition is measured ± 200 mV from steady-state
voltage. This parameter is gnaranteed and not 100% tested.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. This parameter is gnaranteed and not
100% tested.
9.
2-330
0
5
0
2
ns
0
6
0
3
ns
7
ns
ns
The internal write time of the memory is defined by the overiapofCEl
LOW, CEzillGH,andWE LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. All three signals must be active to initiate a write, and
either signal can terminate a write by going inactive.
.
CY7B185
CY7B186
,~PRESS
. ' SEMICONDUCTOR
Switching Waveforms
Read Cycle No 1 [10, 11]
IRC
~V
~I/
ADDRESS
lAA
: . - . - - tOHA
DATA OUT
~
PREVIOUS DATA VALID
)KXXXj~
DATAVAUD
Bla&~~tHZOE
~~
OE
IOOE
~ I[zOE--
HIGH IMPEDANCE
DATA OUT
g
- - tHzCE
1////
DATAVAUD
~'\.'\.'\.,
HIGH
IMPEDANCE
/
I[zCE
B185·7
Write Cycle No.1 (WE Controlled) [8, 13, 14]
~----------------------_IWC----------------------~
ADDRESS
14------------------- IsCE1 -------------------.t ~_r:'I"7"'T'7+.,....,..'T'7..".,,....,...,..,..,..
eE,
~~~----------------------------------~~~~~~~~~~
~---------Isc~ -------------------~
14------------~W ----------~~~
1+-----
ISA
-------10>/
WE------------------~~~,
DATA IN
DATAI/O
"'0-------
IPWE
----------I
~------------------
--------------------, 1+-+------- Iso ----------I.--.j ,-----------DATA VALID
NOTE15
ILZWE
HIGH IMPEDANCE
)
~
-
(
_NOTE 15
B185-8
Notes:
10. Device is continuously selected. OE, eEl = VIL. eEz = Vrn.
11. WE is HIGH for read cycle.
12. Address valid prior to or coinciden I wi th eli transition Ww.
13. DataI/O is HIGH impedance ifOE = VIII.
14. When data input is applied to the device I/O, the device output should
be in the high-impedance state.
15. During this period, the I/Os are in the output state and input signals
should not be applied.
16. IfCl,goesHIGHsimultaneouslywithWEHIGH,theoutputremains
in a high-impedance state.
2-331
CY7B185
CY7B186
-~~
~i=cyPRESS
-
F
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [8,12, 14, 16J
~------------------------twc ------------------------~~
ADDRESS
----+---------'" ..,1-------
CEl
tsCEl
----------I ~----+------
1 - - - - - - tSA - - - ' - - - - - I ~------""
CE2--~------------J'~----- tsc~ ----~~,----~-----
DATA IN
DATA
DATA VALID
HIGH IMPEDANCE
1/0----------------------------------
Cl85-9
Truth Table
CEl
H
X
L
L
L
CE2
X
OE Inputs/Outpnts
Mode
Deselect/fuwer-Down
X
HighZ
HighZ
L
Data Out
Read
L
X
Data In
Write
H
H
HighZ
Deselect
WE
X
X
L
X
H
H
H
H
Deselect
Ordering Information
Speed
(ns)
9
10
12
15
Ordering Code
CY7B185-9DC
CY7BI85-9PC
CY7BI85-9VC
CY7Bl85 -IODC
CY7BI85-lOPC
CY7B185-lOVC
CY7B185-10DMB
CY7B185-lOLMB
CY7B185-12DC
CY7B185-12PC
CY7B185-12V( .
CY7B185-12DMB
CY7B185-12LMB
CY7BI85-15D(,
CY7B185-15PC
CY7B185-15V(,
CY7B185-15DMB
CY7B185-15LMB
Package
type
D22
P21
V21
022
P21
V21
022
L54
D22
P21
V21
D22
L54
022
P21
V21
D22
L54
Operating
Range
Commercial
Commercial
Speed
(ns)
12
15
Ordering Code
CY7B186-12PC
CY7B186-15PC
CY7B186-15DMB
Document #: 38-A-OOOI6-C
Military
Commercial
Military
Commercial
Military
Shaded area contains preliminary information.
2-332
Package
'lYPe
PIS
PIS
D16
Operating
Range
Commercial
Commercial
Military
CY7C185
CY7C186
CYPRESS
SEMICONDUCTOR
8,192 x 8 Static RIW RAM
Features
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
The CY7C185 and CY7C186 are high-performanceCMOS static RAMs organized as
8192 words by 8 bits. Easy memory expansion is.E!:.ovided by an active LOW chip enable (CEl), an active HIGH chip enable
~), and active LOW output enable
(OE) and three-state drivers. Both devices
have an automatic power-down feature
(CEl), reducing the power consumption by
over 75% when deselected. The CY7C185
is in the space-saving 300-mil-wide DIP
package and leadless chip carrier. The
CY7C186 is in the standard 600-mil-wide
package.
An active LOW write enable signal (WE)
controls the writing/reading operation of
• Highspeed
- IOns
• Low active power
- 93SmW
• Low Standby Power
- 220mW
• TIL-compatible inputs and outputs
• Capable of withstanding greater than
200lV electrostatic discharge
the memory. When CEl and WE inputs are
both LOW and CEz is HIGH, data on the
eight data input/output pins (1/00 through II
tttltH~ 1/00
A'0
All
9
A'2
1/00
110,
I/O.
>11ttt-- 1/00
GND
~uJ5l~
>~--1I05
As
As
A,o
4
5
6
7
8
A"
A'2
~o
1100
11
NC
A7
>1t6---1I0s
eel ......_ "
><---110,
c;J rt-t..-.:L..J
C1B5-2
LCC
ThpView
>ttt-- vo,
vo,
OE
C1B5-1
3 2 111 2827
26CE2
25 As
24 As
23 A1
7C185
22 OE
7Cl86
~~~,
19
110,
12
18
1314151!117
I/Os
ClIO t":I 'It tn
g ~gg g
C1B6-3
Selection Guide[l]
7C18S 20 7C18S 2S 7C18S-3S 7C18S 4S 7C18S-SS
7C185-10 7CI85-12 7CI85-IS 7CI86-20 7C186-25 7C186-35 7C186-45 7CI86-55
MaximumAccess Time (ns)
20
25
35
20
25
35
45
55
Maximum 0serating
Current(mA
170
170
160
120
100
100
100
80
40120
40/20
40120
20/20
20/20
20/20
20/20
20/20
Maximum Standby
Current(mA)
Shaded areas contain advanced informatIon.
Note:
1. Formilitaryspecifications,seetheCY7C185NCY7C186Adatasheet.
2-333
CY7C185
CY7C186
.Ft~NDtCfOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. Ambient Thmperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
inHighZState ........................
DClnputVoltage ......................
65°C to +150°C
55°Cto +125°C
- O.5V to + 7.0V
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-SID-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
- 0.5V to +7.0V
- 3.0Vto +7.0V
Ambient
Thmperature
O°Cto +70°C
Range
Commercial
Vee
5V± 10%
Electrical Characteristics Over the Operating Range
7C18S-10
Parameters
Description
Thst Conditions
VOH
Output mGH Voltage Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vm
Input HIGH Voltage
VIL
Input WW Voltagel2j
IJX
Input Load Current
GND~VI~Vee
loz
Output Leakage
Current
OutputDisabled
los
Output Short
CircuitCurrend3j
lee
Vee Operating
Supply Current
ISB!
AutomaticCEl
Power-DownCurrent
Vee = Max.,
Vour=GND
Vee = Max.,
lOUT = ornA
Max. Vee, CEl ~ Vm,
Min. DutyCyc1e = 100%
IsB2
AutomaticCEl
Power-DownCurrent
VIN~ Vee
Min.
2.4
2.2
-3.0
Max. Vee,
-10
-10
CEl~ Vee - 0.3y,
- O.3VorVIN~O.3V
Shaded areas contam advanced mfonnation.
2-334
7C18S-12
Min.
Max.
2.4
Vee
0.8
+10
+10
7C18S-lS
Min.
2.2
Max.
2.4
0.4
0.4
Vee = Min., IOL = 8.0 rnA
GND~VI~Vee,
Max.
2.2
Units
V
0.4
V
V
-3.0
Vee
0.8
-3.0
Vee
0.8
-10
+10
-10
+10
-10
+10
-10
+10
IJA
IJA
V
-350
-350
-350
rnA
170
170
160
rnA
40
40
40
rnA
20
20
20
rnA
CY7C185
CY7C186
~
.
,~
_'=CYPRESS
-=-.iF
SEMICONDUc..'TOR
Electrical Characteristics Over the Operating Range (continued)
7C185-20
7C186-20
Parameters
Thst Conditions
Description
Min.
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
Input LOW Voltage[2]
VOH
VOL
VIH
VIL
IJX
Ioz
Min.
Max.
2.4
2.4
7C185-55
7C186-55
Min.
Max. Units
2.4
0.4
0.4
V
0.4
V
2.2
-3.0
Vee
0.8
2.2
-3.0
Vee
0.8
2.2
-3.0
Vce
0.8
V
V
Input Load Current
GND~VI~Vee
-10
+10
-10
+10
-10
+10
Output Leakage
Current
Output Short
CircuitCurrent[3]
GND~ VI~ Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
JIA
JIA
Ice
Vee Operating
Supply Current
ISBI
AutomaticCEI
Power-Down Current
Vee = Max.,
VouT=GND
Vee = Max.,
IOUT=OmA
Max. Vce, CEI ~ VIH,
Min. Duty Cyc1e = 100%
ISB2
AutomaticCEI
Power-Down Current
Max. Vee, CEI ~ Vee - 0.3v,
VIN ~ Vee - 0.3VorVIN~0.3V
los
Max.
7C185-25,35,45
7C186-25,35,45
-300
-300
-300
rnA
120
100
80
rnA
20
20
20
rnA
20
20
20
rnA
Capacitance [4]
Parameters
Description
InputCapacitance
OutputCapacitance
CIN
CoUT
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
2. VIL min. = - 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Max.
10
10
Units
pF
pF
4. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
5V
5V o-_ _~R1....48~1,0
o-_ _ _R:;;l""48i\,:l,O
OUTPUT
ALL INPUT PULSES
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
I=
3.OV ----.J~.,....---~
5pF
R2
2550
INCLUDING
JIGAND
SCOPE
=
(b)
(a)
Equivalent to:
I=
R2
2550
GND
=
Cl854
THEVENIN EQUIVALENT
1670
OUTPUT~1.73V
2-335
Cl8S-5
•
CY7C185
CY7C186
· .~
_'ii!CYPRESS
==-
F
SEMICONDUCTOR
Switching Characteristics
Over the Operating RangdS]
7C185-10
Parameters
Description
Max.
MIn.
7C185-12
Min.
Max.
7C185-15
Min.
Max.
Units
READ CYCLE
15
12
10
ns
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from
AddressChange
tACEI
CEI LOW to Data Valid
10
12
15
ns
tACEZ
CEz HIGH to Data Valid
10
12
15
ns
tOOE
OE LOW to Data Valid
5
6
10
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z[6]
tLZCEI
CEl LOW to Low Z[7]
2
2
tLZCEZ
CEz HIGH to Low Z
tHZCE
CEI HIGH to High Z[8, 9]
CEz LOW to High Z
tpu
CEI LOW to Power-Up
tpo
CEI HIGH to Power-Down
10
3
3
3
7
5
3
0
ns
8
0
0
12
ns
ns
3
7
10
ns
8
3
3
5
ns
ns
3
0
0
15
12
ns
ns
15
ns
WRITE CYCLE[8]
12
15
ns
8
8
12
ns
CEz HIGH to Write End
8
8
12
ns
Address Set-Up to
Write End
8
9
12
ns
Address Hold from
Write End
0
0
0
ns
Address Set-Up to
Write Start
0
0
0
ns
twc
Write Cycle Time
tSCEI
CEI LOW to Write End
tSCEZ
tAW
IHA
tSA
10
tpWE
WE Pulse Width
8
8
12
ns
tso
Data Set-Up to Write End
5
6
10
ns
tHO
Data Hold from Write End
0
0
0
tHzWE
WE LOW to High Z[8]
tLZWE
WE HIGH to Low Z
6
2
6
3
ns
7
3
ns
ns
Shaded areas contain advanced information.
Notes:
5. Test conditions assume signal transition time of 5 nSOf less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IorJIOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHzWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 m V from steady state
voltage.
7.
8.
2-336
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
The internal write time ofthe memory is defined by the overlap of CE1
LOW, CE2 HIGH, and WE LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
-=..
CY7C185
CY7C186
~-'='"
.
~~PRESS
- , SEMICONDUCTOR
Switching Characteristics Over the Operating RangdS] (continued)
7C185-20
7C186-20
Parameters
Description
Min.
Max.
7C185-25
7C186-25
Min.
Max.
7C185-35
7C186-35
Min.
Max.
7C185-45
7C186-45
Min.
Max.
7C185-55
7C186-55
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
tOHA
Data Hold from
Address Change
tACE!
CEI LOW to Data Valid
20
25
35
45
20
20
55
45
35
5
5
5
45
35
25
ns
55
5
5
ns
ns
55
ns
tACEZ
CEz HIGH to Data Valid
20
25
25
30
40
ns
tDOE
OE LOW to Data Valid
10
12
15
20
25
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6]
tLZCEl
CE! LOW to Low Z[7]
5
5
5
5
5
ns
tLZCEZ
CEz HIGH to Low Z
3
3
3
3
3
ns
tHZCE
CEI HIGH to High Z[8, 9]
CEz LOW to High Z
tpu
CEI LOW to Power-Up
tpD
CEI HIGH to Power-Down
3
3
8
0
0
20
3
15
15
10
20
3
12
10
8
0
3
15
0
20
0
25
20
ns
20
ns
ns
ns
25
ns
WRITECYCLE[8]
twc
Write Cycle Time
20
20
25
40
50
ns
tSCEI
CEI LOW to Write End
15
20
25
30
40
ns
tSCEZ
CEz HIGH to Write End
15
20
20
25
30
ns
tAW
Address Set-Up to
Write End
15
20
25
30
40
ns
tHA
Address Hold from
Write End
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
15
15
20
20
25
ns
tSD
Data Set-Up to Write End
10
10
15
15
25
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
WE LOW to High Z[8]
tLzWE
WE HIGH to LowZ
7
5
5
2-337
15
10
7
5
5
ns
20
5
ns
ns
,..
·
CY7C185
CY7C186
.~PR5S
== F
SEMlCONDUCfOR
Switching Waveforms
Read Cycle No. 1[9, 10)
ADDRESS
€
1
--~IOHA~
DATA OUT
*-
IRC
PREVIOUS DATA VALID =iXxxxx>K===============D=A=T=A=V=A=LI=D=========::
C181>6
Read Cycle No. 2[11, 12]
CE,
IRC
~"-
.I'll"
..J~
~
lACE
.~~
I+-
"IOOE
~ ILZOE--
DATA OUT
IHZCE
HIGH IMPEDANCE
_Ipu
=1
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
DATA VALID
."'-
ILZCE
HIGH
IMPEDANCE
/"
I--- Ipo
50%
~ ICC
50%
IS8
C185-7
Write Cycle No.1 (WE Controlled)[lO, 12)
~----~-----------------Iwc ----------------------~
ADDRESS
~----------------~El ------------------~~~~~~~~~~~
~---------- 1~2 --------------------~
WE ------------....m~~
14------ IPWE ----------I
/"--------
1--+------- Iso ------------<+---1
DATA IN
------------------~
DATA-IN VALID
IHZWE
DATA I/O
----I
,-----------
IlZWE
-.J
V,.----. . ._____
~I
HIGH IMPEDANCE
________
DA_T_A_U_N_D_E_FI_N_ED
_ _ _ _ _ _J)>----------~,
C185-8
Notes:
9. Device is continuously selected. DE, CE =VIL. CEz = VIR.
10. Address valid prior to or coincident with CE transition LOW.
11. WE is HIGH for read cycle.
12. Data I/O is high impedance if DE = VIR.
2-338
-==--.
CY7C185
CY7C186
~~-
-
~rlPRESS
.5' SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [10,12, 13J
~------------------------- Iwc --------------------------~
ADDRESS
CE 1
----+------------... 1+-------- ISCEI
-------_~
,,------11-------
•
I I)
::::E
f----
5.5
100
~ 0.6
~ 0.4
ISB
zw
a::
()
Z
0.0
4.0
120
w
::;;
0.2
1
f-
N
a::
Z
1.2
'"
.:!!
8
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
YS.
/
Vee = 5.0V
TA = 25°C
J
/
V
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C185
CY7C186
-':~PRF.SS
·
_ , SEMICONDUCTOR
1Ypical'DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
12 2.5
25.0
~
/
Cii'
w 2.0
.s
20.0
::J
..::
::;: 1.5
13
15.0
0
o
0
a:
w
1.0
z
0,5
0.0
0,0
1.0
2.0
--
3.0
V
J
4.0
/
10.0
5.0
5.0
15
ow
/
:;:;
N
N
::;:
a:
200
400
600
800 1000
CAPACITANCE (pF)
Truth Table
CEl
CE2
WE
OE
H
X
X
X
HighZ
Deselectllbwer-Down
X
L
X
X
HighZ
Deselect
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
HighZ
Deselect
Mode
Address Designators
Address
Name
Address
Function
A4
X3
2
AS
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Yl
7
AlO
Y4
8
All
Y3
9
Al2
YO
10
AD
Y2
21
Al
XO
23
A2
Xl
24
A3
X2
25
-
1 1-
/
Vee ~ 5.0V
TA ~ 25°C
Vee ~ 0.5V
:;t
Vec~4,5V
TA~ 25°G
/
SUPPLY VOLTAGE (V)
Inputs/Outputs
NORMALIZED Icc vs. CYCLE TIME
1.25
Pin
Number
2-340
oz
o.5o1'::o----':-2o:----3~0:------'40
CYCLE FREQUENCY (MHz)
CY7C185
CY7C186
== :~
-.
---'a
F
CYPRF.SS
SEMlCONDUCIOR
Ordering Information
Speed
(ns)
10
12
15
20
25
35
45
55
Package
1Ype
Operating
Range
Speed
(ns)
CY7C185-10DC
D22
Commercial
20
CY7CI85-lOPC
P21
CY7C185-10VC
V21
CY7CI85 -12DC
D22
CY7CI85-12PC
P21
CY7C185-12VC
V21
CY7C185 -15DC
D22
CY7C185 -15PC
P21
Ordering Code
CY7C185 -15VC
V21
CY7C185-20DC
D22
CY7C185 - 20LC
L54
CY7C185-20PC
P21
CY7C185 - 20VC
V21
CY7C185-25DC
D22
CY7C185-25LC
L54
CY7C185-25PC
P21
CY7C185 - 25VC
V21
CY7C185-35DC
D22
CY7C185 - 35LC
L54
CY7C185-35PC
P21
CY7C185 - 35VC
V21
CY7C185-45DC
D22
CY7C185-45LC
L54
CY7C185-45PC
P21
CY7C185-45VC
V21
CY7C185 - 55DC
D22
CY7C185 - 55LC
L54
CY7C185-55PC
P21
CY7C185-55VC
V21
25
Commercial
35
45
Commercial
55
Commercial
Commercial
Commercial
Commercial
Commercial
Shaded areas contrun advanced mformation.
Document #: 38-00037-G
2-341
Package
'tYpe
Operating
Range
CY7CI86-20DC
016
Commercial
CY7CI86-20PC
P15
CY7CI86-25DC
D16
Ordering Code
CY7CI86-25PC
P15
CY7C186-35DC
016
CY7C186-35PC
P15
CY7C186-45DC
016
CY7C186-45PC
P15
CY7C186-55DC
016
CY7C186-55PC
P15
Commercial
Commercial
Commercial
Commercial
CY7C185A
CY7C186A
CYPRESS
SEMICONDUCTOR
Features
• Automatic: poweNlOWll when
deseleded
• CMOS .for optimum speed/power
• Hlgbspeed
- :ZOns
• Low adlve power
- 990mW
• Low standby Power
- :z:zo mW
• TTL-compatible Inputs and outputs
• Capable ofwltbstanding greater than
:ZOOlV electrostatic discharge
8,192 x 8 Static R/W RAM
enable (\"rn) inputs are both LOW, and the
Functional Description
chip enable two (CE:z) input is mOHo Data
The CY7Cl85A and CY7Cl86A are high- on the eight JlO pins (JlOo through I/o,) is
performance CMOS static RAMs orga- written into the memory location specified
nized as 8192 words by 8 bits. Easy on the address pins (Ao through Ali).
memory expansion ~vlded by an active Reading the device is accomplished by takLOW chip enable (CEI). an active mOH ing ~nable one (eEl) and output enchip enable (CE:z). an active LOW output able (OE) LOW. while taking write enable
enable (1m). and three-state drivers. Both (WE) and chip enable two (CEU HIGH.
devices have an automatic power-down Under these conditions, the contents of the
feature (C1!1), reducing the power con- memory location specified on the address
sumption by over 75% when deselected. pins will appear on the I/O pins.
The CY7C185A is in the space saving
3OO-mil-wide DIP package and Ieadless The I/O pins remain in ~-iolpedance
chip carrier. The CY7C186A is in the state when chip enable one (CEI) or output
enable (Of!) is mOH, or write enable
standard 600-mil-wide package.
(W1!J or chip enable two (CEz) is LOW.
Writing to the device is accomplished
when the chip enable one (eEl) and write A die coat is used to insure alpha iolmunity.
Logic Block Diagram
Pin Configurations
DIP
ThpView
NC
Vee
As
As
As
ceo
A7
VOo
VOl
V~
VC>a
As
As
.....
A"
.... a
110.
110,
lIOa
WE
As
As.
....
25
A,a
:
IJOo
110,
8 7Cl85A
9
10
22
21
20
11
19
12
18
1314151817
g'U'gg
CI85A-3
OND -..:.;:.....-;:;.r 110,
LCC
ThpVi....
U~~~I~~
VOs
C, __,
5
A,.
An
tIE
Ao
CE,
1107
110,
110.
110,
V04
V07
4 3 2,:1,282726
A7
~ ~
CI85A·2
Vas
NO
Ass
~
3 2,1,323130
-
A7 8
28
28
7
8
27
26
As
As
A,. 9
701_
25
A" 10
24
A'2 11
23
NC 12
22
110. 13
21
14161617181920
As
As.
A,
NO
tIE
Ao
CE,
1107
110.
CI85A-4
Selection Guide!l]
Notes:
1.
For commercial specifications, see the CY7C18S16 datasheet
2-342
CY7C185A
CY7C186A
~
-==
.
'~PRESS
F
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Output Current into Outputs (Low) ................. 20 rnA
Static Discharge Voltage. . .. . . . . . . . . . .. . . . . . . . . . . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200 rnA
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ........................
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................
DC Voltage Applied to Outputs
in High Z State .........................
DCInputVoltage .......................
Electrical Characteristics
Parameters
- 55°Cto +l25°C
Operating Range
-O.5Vto +7.0V
Range
MilitarylLJ
- 0.5Vto +7.0V
Ambient
'Thmperature
Vee
- 55°Cto +125°C
5V± 10%
- 3.0Vto +7.0V
Over the Operating Rangel3]
Description
'Thst Conditions
VOH
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA
VOL
Output WW Voltage
VIH
VIL
Input HIGH Voltage
Input WW Voitagel4J
I,x
Input Load Current
loz
7Cl85A-12
7Cl86A-12
7Cl85A-15
7Cl86A-15
7C185A-20
7C186A-20
Min.
Min.
Min.
Max.
2.4
0.4
Vee = Min., IOL = 8.0 rnA
2.2
Max.
0.4
2.2
Max.
Units
0.4
V
2.4
2.4
2.2
V
Vee
0.8
-0.5
Vee
0.8
-3.0
Vee
0.8
V
-0.5
GND.:5.V,.:5.Vee
-10
+10
-10
+10
-10
+10
Output Leakage
Current
GND.:5. V,.:5. Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
ItA
ItA
los
Output Short
CircuitCurrent[5]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max.
lOUT = ornA
ISBl
ISB2
V
-350
-350
-300
rnA
Military
180
170
135
rnA
AutomaticCEl
Power-DownCurrent
Military
Max. Vee, CEl ~ VIH,
Min. Duty Cycle = 100%
40
40
40
rnA
AutomaticCEl
Power-Down Current
Max. Vee,
CEl ~ Vee -O.3V
VIN ~ Vee -O.3V
Military
20
20
20
rnA
orVIN~O.3V
Shaded area contams advanced informalton.
Notes:
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group Asubgroup testing information.
4.
5.
2-343
VU,(min,) = - 3.0Yforpulse durations less than 30ns.
Not more than 1 output should be shorted at one time. Duration oftbe
short circuit should not exceed 30 seconds.
•
CY7C185A
CY7C186A
s.;~
~'~C!OR
Electrical Characteristics
Over the Operating Rangel3] (continued)
7C185A-25
7Cl86A-25
Parameters
Thst Conditions·
Description
Min.
Vee = Min.,IoH
= - 4.0 rnA
VCc = Min., IOL = 8.0 rnA
VOH
Output HIGH Voltage
VOL
Output WWVoltage
VIH
Input HIGH Voltage
2.2
VIL
Input LOWVoitagel4J
IIX
Input Load Current
Ioz
7Cl85A-35, 45, 55
7C186A -35,45,55
Max.
Min.
2.4
Max.
Units
2.4
V
0.4
0.4
V
2.2
Vee
V
-3.0
Vee
0.8
-3.0
0.8
V
GND~VI~Vee
-10
+10
-10
+10
Output LeakageCurrent
GND ~ VI ~ Vee, Output Disabled
-10
+10
-10
+10
fLA
fLA
los
Output Short
CircuitCurrend5]
Vee = Max., VOUT = GND
-300
-300
rnA
lee
Vee Operating Supply
Current
Vee =Max.,IoUT =ornA Military
125
125
rnA
ISB!
Automatic CEl
Power·DownCurrent
Max. Vee, eEl ~ VIH,
Min. Duty Cycle = 100%
Military
40
30
rnA
IsB2
Automatic CEl
Power-Down Current
Max. Vee
CEl ~ Vee -O.3V
VIN ~ Vee -O.3V
Military
20
20
rnA
orVIN~O.3V
Capacitance [6]
Parameters
Description
CIN
Inputcapacitance
CoUT
Outputcapacitance
Thst Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Units
10
pF
10
pF
Note.:
6.
Thsted initially and after may design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl481Q
R1481Q
5 V o - - -__.....,
5V~
OUTPUT
30pF
INCLUDING
JIG AND
SCOPE
5 PF
:5Q
I=
=
INCWDING
JIG AND
SCOPE
1
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo--_--4
R2
255Q
= =
'''~
10%
GND
55n8
C185A-5
(b)
THEVENIN EQUIVALENT
167Q
OUTPUT ().o--~",_,.,.--.....
o 1.73V
2-344
90%
J?:::
10%
55n8
C185A-6
CY7C185A
CY7C186A
~
~~pRF.SS
- . f F SEMICONDUCIOR
Switching Characteristics
Over the Operating Rangd2, 7]
7C185A-12
7Cl86A-12
Parameters
Description
Min.
Max.
7C185A-15
7Cl86A-15
Min.
Max.
7C185A-20
7C186A-20
7C185A-25
7C186A-25
Min.
Min.
Max.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
12
20
15
15
12
25
20
3
ns
25
ns
ns
tOHA
Data Hold from AddressChange
tACEl
CEl LOW to Data Valid
12
15
20
25
tACE2
CEz HIGH to Data Valid
12
15
20
25
ns
tOOE
OE LOW to Data Valid
6
7
10
12
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z[8]
tLZCEl
CEl LOW to Low Z[9]
3
3
tLZCE2
CEz HIGH to Low Z
tHZCE
CEl HIGH to High Z[8, 9]
CEz LOW to High Z
tpu
CEl LOW to Power-Up
tpo
CEl HIGH to Power-Down
3
3
0
3
0
8
7
3
0
8
10
ns
10
0
20
15
ns
ns
3
8
0
0
ns
5
3
8
12
3
5
3
7
ns
3
ns
ns
20
ns
WRITECYCLE[lO]
twc
Write Cycle Time
12
15
20
20
tSCEl
CEl LOW to Write End
8
10
15
20
ns
tSCE2
CE2 HIGH to Write End
8
10
15
20
ns
ns
ns
tAW
Address Set-Up to Write End
9
10
15
20
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
8
10
15
15
ns
tso
Data Set-Up to Write End
6
7
10
10
ns
tHO
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z
3
3
3
5
tHZWE
WE LOW to High ZIRI
6
7
7
ns
7
ns
Shaded area contaIDs advanced mformalton.
Notes:
7. Test conditions assume signal transition timcof5 nsorless, timing reference levels of1.5V, input pulse levels ofO to 3.0V, andoutputloading
of the specified IOrJIOH and 30-pP load capacitance.
S. tHZOE, tHzCE, and IHzWE are specified with CL = 5 pF as in part (b)
of AC lest Loads. Transition is measured ±500 mV from steady state
voltage.
9.
At any given temperature and voltage condition, tHZCE is less than
tI.Z('I'. for any given device.
10. Device is continuously selected. OE, eEl = VlL. eEz = VIH.
2-345
en
:::a:
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
~
~ 80
w
~ 60
0.2 "- 1SB
I----
ISB
0.0
::iii
a:
U
Z
4.0
!zw 100
~
~
0.2
w
l120
~
::J 0.6
a:
Z
1.2
on
OUTPUT SOURCE CURRENT
vo.OUTPUTVOLTAGE
II
80
40
/
V
o
/
Vcc= 5.0V
TA = 25°G
I
20
0.0
1.0
2.0
3.0
4.0
M
C185A-ll
OUTPUT VOLTAGE
CY7C185A
CY7C186A
~
~~PRFSS
-=:!!!!!!!:, SEMICONDUCTOR
'lYPical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
TYPICAL POWER-ON CURRENT
vs_ SUPPLY VOLTAGE
3.0
30.0
2 .5
25.0
2.0
g 20.0
< 1.5
:;:
:l!
« 15.0
!:i
0
...!!0
III
N
::::;
a:
0
1.0
z
-
0.5
0.0
0.0
./
V
1.0
2.0
3.0
4.0
5.0
Vcc= 5.0V
TA = 25°C
Vcc=0.5V
.r-
/
o 1.001---+---1----:.1
/
/
~ 10.0
5.0
NORMALIZED Icc vs. CYCLE TIME
1.25
SUPPLY VOLTAGE (V)
~
Vcc=4.5V TA = 25°C
/
~200
~
1 1-
400
600
800 1000
CAPACITANCE (pF)
~
z
0.751----+::7"""'--1----1
0·501·L::O---"'2~0'-----.:!30-::----!40
CYCLE FREQUENCY (MHz)
Cl85A·12
Truth Table
CEI
C~
WE
OE
H
X
X
X
HighZ
Deselect!lbwer-Down
HighZ
Deselect
Inputs/Outputs
Mode
X
L
X
X
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
HighZ
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
AS
X4
A6
A7
AS
A9
AIO
All
Al2
AO
Al
X5
2
3
4
A2
X6
X7
YI
Y4
Y3
YO
Y2
XO
Xl
5
6
7
S
9
10
21
23
24
2-349
CY7C185A
CY7C186A
.~~NDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
Package
'JYpe
12
CY7Cl85A-120MB
022
CY7C185A-12KMB
K74
CY7Cl85A-12LMB
L54
CY7Cl85A-15DMB
022
CY7C185A-15KMB
K74
CY7Cl85A-15LMB
L54
CY7C185A-200MB
022
CY7C185A-20KMB
K74
CY7C185A -20LMB
L54
CY7C185A-250MB
022
CY7C185A -25KMB
K74
CY7C185A - 25LMB
L54
CY7C185A-350MB
022
CY7C185A-35KMB
K74
15
20
25
35
45
55
CY7C185A - 35LMB
L54
CY7C185A-450MB
022
CY7C185A-45KMB
K74
CY7C185A-45LMB
L54
CY7C185A-550MB
022
CY7C185A -55KMB
Operating
Range
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Military
Military
Military
Military
Military
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IIJ(
1,2,3
Ioz
1,2,3
los
1,2,3
IcC
1,2,3
ISBI
1,2,3
IsB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
Military
Military
K74
CY7C185A - 55LMB
Parameters
L54
tRC
7,8,9, 10, 11
tM
7,8,9, 10, 11
toHA
7,8,9, 10, 11
tACEl
7,8,9, 10, 11
tACE2
7,8,9, 10, 11
tDOE
7,8,9, 10, 11
WRITE CYCLE
Speed
(ns)
Ordering Code
Package
'JYpe
12
CY7C186A-120MB
016
CY7C186A-12LMB
L55
CY7C186A-150MB
016
CY7C186A-15LMB
L55
CY7C186A-200MB
016
CY7C186A-20LMB
L55
CY7C186A-250MB
016
CY7C186A-25LMB
L55
CY7C186A-350MB
016
15
20
25
35
45
55
CY7C186A-35LMB
L55
CY7C186A-450MB
016
CY7C186A-45LMB
L55
CY7C186A-550MB
016
CY7C186A -55LMB
L55
Operating
Range
Military
Military
Military
Military
Military
twc
7, 8, 9, 10, 11
tSCEl
7,8,9, 10, 11
tSCE2
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Oocument#: 38-00114-A
Military
Military
Shaded area contains advanced information.
2-350
CY7C187
CYPRESS
SEMICONDUCTOR
65,536 X 1 Static R/W RAM
Features
Functional Description
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Highspeed
-15ns
• Low active power
- 495mW
• Low standby power
- 220mW
• TTL compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C187 is a high-performance
CMOS static RAM organized as 65,536
words x 1 bit. Easy memory expansion is
P!Qvided by an active LOW chip enable
{rn) and three-state drivers. The
CY7C187 has an automatic power-down
feature, reducing the power consumption
by 56% when deselected.
Writing to the device is accomplished
when the chip enable (CB) and write enable (WI!) inputs are both LOW. Data on
the input pin (01) is written into the
memory location specified on the address
pins (Ao through AlS).
Reading the device is accomplished by
taking the chi~able ~ LOW, while
write enable (WE) remains HIGH. Under these conditions, the contents of the
memory location specified on the address
pins will appear on the data output (00)
pin.
The output pin stays in !!gh-impedance
state when c~able (CE) is HIGH or
write enable (WE) is LOW.
The 7C187 utilizes a die coat to insure alpha immunity.
Pin Configurations
Logic Block Diagram
SOJ
DIP
TopV\ew
TopV\ew
r-----------~r_--------- ~
Ao
Vee
Ao
A,
A,.
A,.
A,.
A,
Ae
As
NO
Au
Ao
Ao
Ae
As
4
"'.
"'.
~
Ao
NC
Ao
As
At
A7
Dour
WE
">----00
DtN
llE
GND
Vee
A,.
A,.
A,.
A12
Au
A,.
~
Ar
As
Ao
DtN
llE
Dour
WE
GND
C187-8
C187-2
Lee
~ck
Top
ew
,-"....._ _ WE
0187-1
A,
~
Ao
As
A7
DOUT
WE
GND
Selection Guide!l]
Note:
1. For military specifications, see the CY7C187A datasbeet.
2-351
"'.
Ao
Ae
As
Top View
~~$;
Vee
NC
4
A,.
AIS
A,.
"',
NO
"'.
As
At
DtN
CE
Ae
As
3 2 L' ,222120
4
~
5
A7
8
Ao 8
As 7
DOUT 9
19
18
70187 17
16
15
14
10111213
1~~Il'l~
A,.
A13
A,.
Au
A,.
As
Ao
C187-5
•
CY7C187
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. Ambient Thmperaturewith
PowerApplied....................... SU'pply Voltage to Ground Potential
(Pin 22 to Pin 11) .. . . .. . .. .. . .. .. . . .. .. .
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
Electrical Characteristics
65°C to +150°C
55°C to +125°C
- O.sV to +7.0V
- 0.5Vto +7.0V
- 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 20 mA
Static Discharge Voltage........................ >2001V
(per MIL-SID-883, Method 3015)
Latch-UpCurrent ............................ >200mA
Operating Range
Ambient
Thmperature
Range
Commercial
Over the Operating Range
7C187-111
Parameters
Vee
5V± 10%
O°Cto +70°C
Description
Thst Conditions
Min.
Max.
7C187-12
Min.
Max.
7C187-15
Min.
Max.
Units
VOH
Output HIGH Voltage
Vee = Min.,
IOH = - 4.0mA
VOL
Output LOW Voltage
Vee = Min.,
IOL = 12.0mA
Vrn
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltagel2]
-3.0
0.8
-3.0
0.8
- 3.0
0.8
V
2.4
2.4
0.4
2.4
0.4
V
0.4
V
IJX
Input Load Current
GND5VI5 Vee
-10
+10
-10
+10
-10
+10
loz
Output Leakage
Current
GND5 Vo5 Vee,
OutputDisabled
-10
+10
-10
+10
-10
+10
!lA
!lA
los
Output Short
CircuitCurrent[3]
Vee = Max.,
VOUT= GND
-350
-350
-350
mA
Icc
Vee Operating
Supply Current
Vee-Max.,
IOUT=OmA
160
160
90
mA
IsBl
AutomaticCE PowerDown Currentl4]
Max. Vee, CE.;::, Vrn
40
40
40
mA
IsB2
AutomaticCE
Power-Down Current
Max. Vee,
CE.;::, Vcc - 0.3V;
VIN';::' Vee - O.3V
or VIN50.3V
20
20
20
mA
Shaded area mdicates advanced mformatlon.
2-352
-==--~
~:..eb
=a!i5 CYPRESS
=
_
F
CY7C187
SEMlCONDucroR
Electrical Characteristics Over the Operating Range (continued)
7C187-20
Parameters
Thst Conditions
Description
VOH
Output HIGH Voltage
Vee = Min.,
lOR = -4.0rnA
VOL
Output LOW Voltage
Vee = Min.,
IOL= 12.0mA
Min.
Max.
2.4
7C187-25,35
Min.
Max.
7C187-45
Min.
0.4
0.4
Max.
Units
2.4
2.4
V
0.4
V
VIR
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW VOltage!2]
-3.0
0.8
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GND~VI~Vee
-10
+10
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND~Vo~Vee,
-10
+10
-10
+10
-10
+10
OutputDisabled
!LA
!LA
los
Output Short
CircuitCurrent[3]
Vee = Max.,
VOUT = GND
-350
-350
-350
rnA
Icc
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
80
70
50
rnA
ISBI
AutomaticCE PowerDown Current[4[
Max. Vee, CE ~ Vrn
40
20
20
rnA
ISB2
AutomaticCE
Power-DownCurrcnt
Max. Vee.
CE~ Vee - 0.3v,
VIN ~ Vee - 0.3V
20
20
20
rnA
orVIN~O.3V
Capacitance [5]
Parameters
Description
InputCapacitance
Output Capacitance
qN
CoUT
Thst Conditions
TA = 25°C, f
Vee
= 5.0V
= 1 MHz,
Max.
10
10
Units
pF
pF
Notes:
2. VJLmin. = -3.0Vforpulsedurations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
4. A pull-up resistor to Vcc on the CE input is required to keep the device deselected during Vccpower-up, otherwise ISB will exceed values
given.
5. Thstedinitiallyandafteranydesignorprocesschangesthatmayaffect
these parameters.
AC Test Loads and Waveforms
AI329Jl
(480.o.Mll)
A132Q(l
(480.0. Mil)
5V
OUTPUT
5V
0---""",--+
30 pF
OUTPUT
A2
202.0
(Rl 255.l1. MIl)
I
INCLUDING
JIGAND _
SCOPE -
5 PF
1
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
0---""",--+
(b)
R2
202,(1
(AI 255.0. Mil)
::~%
C187-7
CI87-6
THEVENIN EQUIVALENT
125.0.
167.()
OUTPUT
OUTPUT~I.73V
Military
00---'1.,.,'---...
0 1.90V
Commercial
2-353
CY7C187
Switching Characteristics
Over the Operating Rangel:6]
7C187-10
Parameters
Description
Min,'
MItt.
7C187-U
Min.
MItt.
7C187-15
Min.
Max.
Units
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from AddressChange
tACE
CE LOW to Data Valid
tlZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[8, 9]
tpu
CELOW to Power Up
tpo
CEHIGH to Power Down
15
12
10
,'" 10
3
3
3
12
10
'2
5
15
0
0
10
ns
ns
15
12
ns
ns
8
7
ns
ns
3
3
()
ns
15
12
ns
WRITECYCLEl9]
twc
Write Cycle Time
10
12
15
ns
tsCE
CE LOw to Write End
8
8
12
ns
tAW
Address Set-up to Write End
8
9
12
ns
tRA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
8
8
12
ns
tso
Data Set-up to Write End
5
6
10
ns
tHO
Data Hold from Write End
0
(t
0
ns
tLZWE
WE HIGH to Low Z[9]
2
3
5
tHZWE
WE LOW to High zI9, 10]
6
Shaded area Indicates advanced Information.
2-354
,.'
'6 '
ns
7
ns
.~~
'= CYPRESS
CY7C187
~iF SEMlCONDUCfOR
Switching Characteristics
Over the Operating Rangel6] (continued)
7C187-20
Parameters
Description
Min.
Max.
7C187-25
Min.
Max.
7C187-35
Min.
Max.
7C187-45
Min.
Max.
Units
READ CYCLE
25
20
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from AddressChange
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[8, 9]
tpu
CE LOW to Power Up
tpo
CEHIGH to Power Down
20
5
5
20
8
0
15
0
0
20
ns
ns
15
ns
25
ns
0
20
ns
ns
45
5
5
10
20
5
35
25
ns
45
35
5
5
5
45
35
25
ns
WRITE CYCu;[9]
twc
Write Cycle Time
20
20
25
40
ns
tsCE
CE LOW to Write End
15
20
25
30
ns
tAW
Address Set-Up to Write End
15
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
15
15
20
20
ns
tso
Data Set-Up to Write End
10
10
15
15
ns
tHO
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Lowl9]
5
5
5
5
ns
tHzWE
WE LOW to High Z[9, 10]
7
Notes:
6. Thstconditions assume signal transition time ofS ns or less, timing referencelevels of l.Sv, input pulse levels of 0 to 3.0V, and outputloading
of the specified IOl)IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. tHZCE and tHZWE are specified with CL 5 pF as in part (b) of AC
Thst Loads. Transition is measured ±SOO m V from steady state
voltage.
=
7
10
15
ns
The internal write time of the memory is defined by the overlap of CE
WW and WE Ww. Both signals must be WWto initiate awriteand
either signal can terminate a writebygoingIDGH. The data input setupandhold timing should be referenced to the rising edge ofthe signal
that terminates the write.
10. WE is IDGH for read cycle.
9.
2-355
'±fil~UQDR
CY7C187
Switching Waveforms
Read Cycle No.t[1O, 11]
IRC
.....,E
ADDRESS
)(
1M
-toHA~
DATA OUT
mxxx""" E
PREVIOUS DATA VALID
DATA VALID
C187-8
Read Cycle No. 2[10, 12]
lAc
~~
~
lACE
ILZCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
1/////
I"\.'\.'\.'\.'\
I---
~ZCE:j
DATA VALID
HIGH
IMPEDANCE
/
_Ipo
tpu
~ CC
I
50%
ISB
C187·9
Write Cycle No. t (WE ControUed)[ll]
lwe
ADDRESS,~E
---./
(
.
tSCE
:~~ ~~
/
Wffff~ V///////
tHA_
tAW
!sA
tPWE
~I&..~
DATA IN
)
tso
*
I--- tHZWE
DATA OUT
DATA UNDEFINED
IHo
DATA VALID
-
ILZWE;1
HIGH IMPEDANCE
1/
"
C187·10
Notes:
11. Device is continuously selected, CE = VIL
12. Address valid prior to or coincident with CE transition LOW.
2-356
CY7C187
Switching Waveforms
(continued)
Write Cycle No.2 (CE Controlled) [11, 13]
lwe
--------------<0-1
ADDRESS
---*,~----- ~CE
CE
---~------------~
-------t
~------~~-------
~~~------~D
DATA IN
---------1'
DATA VAUD
DATA OUT _________________________________________~H~IG~H~IM~P~E~DA~N~C~E~____________
C187-11
Notes:
13. If CE goes HIGHsimultaneouslywith WEHIGH, the output remains
in a high-impedance state.
'.lypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
"'
'" 1.2
lee
jll.0
V
c
~ 0.8
:::;
~ 0.6
V
./
V
1.2
ID
.::: 1.0
~
I
II:
~ 60
0.6
::J
4.0
4.5
5.0
Vee = 5.0V
VIN= 5.0V
0.2
ISB
0.0
5.5
ISB
0.0
-55
6.0
1.4
1.6
1.3
.J. 1.4
c
c 1.2
w
w
N
N
II:
z
1.0
.............
t"-........
0.9
0.8
4.0
125
NORMALIZEDACCESSTUWE
vs. AMBIENT TEMPERATURE
NORMALIZEDACCESS~
vs. SUPPLY VOLTAGE
:::;
2001 V
(per MIlrSTD-883, Method 3015)
Lateh-UpCurrent ............................ >200rnA
Operating Range
- O.5Vto +7.0V
Range
Militaryl2]
- O.5Vto +7.0V
- 3.0V to + 7.0V
Ambient
Thmperature
Vee
5V± 10%
- 55°Cto +125°C
Electrical Characteristics Over the Operating Range[3]
Parameters
VOH
VOL
VIR
VIL
IJX
loz
los
Icc
ISBl
ISB2
Description
Thst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel4J
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[5]
Vee Operating
Supply Current
AutomatieCE PowerDownCurrent£6]
Vee - Min., IOH - - 4.0 rnA
Vee - Min., IOL - 12.0rnA
AutomatieCE PowcrDownCurrent£6]
7C187A-U
7C187A-15
7C187A-20
Min.
Min.
Min.
Max.
2.4
Mil
GND.sVI.sVce
GND .s Vo.s V ce, Output Disabled
0.4
2.2
- 3.0
-10
10
Vee
0.8
+10
+10
350
Vee - Max., VOUT - GND
Max.
0.4
2.2
- 3.0
-10
.,..10
Max.
2.4
2.4
Vce
0.8
+10
+10
350
0.4
2.2
- 3.0
-10
-10
Units
V
V
V
V
Vee
0.8
+10
+10
!JA
!JA
350
rnA
Vee - Max., lOUT - 0 rnA
Mil
170
160
90
rnA
Max. Vcc, CE ~ VIH
Mil
40
40
40
rnA
Max. Vee, CE ~ Vee - 0.3v,
VIN ~ Vee - O.3Vor
VIN .sO.3V
Mil
20
20
20
rnA
Shaded area contams advanced informatIon.
Notes:
2. TAis the "instant on" case temperature.
3. See the last page ofthls specification for Group A subgroup testing in·
fonnation.
4. VILmin. = -3.0V for pulse durations less than 30 ns.
5.
6.
2-361
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
A pull-up resistor to V cc on the CE input is required to keep the devicedeselectedduringVccpower-up, otherwise ISBwillexceedvalues
given.
CY7C187A
Electrical Characteristics Over the Operating Rangel3] (continued)
7C187A-25
Parameters
Description
Vee-Min.,IOH- -4.0rnA
Vee - Min., IOL - 8.0rnA
IsB!
AutomaticCE
Power Down Current[6]
Max. Vee. CE ~ Vrn
ISB2
AutomaticCE
Power Down Current[6]
lee
Min.
Test Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input WW VoltageLqJ
Input Load Current
Output Leakage Current
Output Short
CircuitCurrent[5]
Vee Operating
Supply Current
VOH
VOL
Vlll
VIL
IJX
loz
los
Max.
Mil
2.2
-3.0
10
-10
Min.
Max.
Units
2.4
2.4
GND.s VI.s Vee
GND.s Vo..:. Vee,OutputDisabled
Vee - Max., VOUT - GND
ornA
7C187A-35,45
0.4
Vee
0.8
+10
+10
-350
V
V
V
V
0.4
2.2
3.0
10
-10
Vee
0.8
+10
+10
-350
rnA
!lA
!lA
Mil
80
80
rnA
Mil
40
30
rnA
Mil
Max. Vee, CE~ Vee - 0.3y,
VIN ~ Vee - O.3V or VIN .s
O.3V
20
20
rnA
Vee - Max., lOUT -
Capacitance [7]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CoUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Max.
10
10
Units
pF
pF
Note:
7. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481.n
R1481.n
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
30 PF
INCLUDING
JIGAND
SCOPE
Equivalent to:
I
R2
5pF
255.)
=
(a)
INCLUDING
=
J~~~~
I
=
(b)
R2
255.n
GND
=
C187A-5
THEVENIN EQUIVALENT
OUTPUT
167.(1
oo--~.'\I\.
3.0V - - - --Ir-:=----~
_ _--00 1.73V
2-362
C187M1
...$::z
W, ~~NDUcroR
CY7C187A
Switching Characteristics Over the Operating Rangel3, 8]
7Cl87A-12 7C187A-15 7C187A-20 7C187A-25 7C187A-35 7C187A-45
Parameters
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Addressto Data Valid
tOHA
Output Hold from
AddressChange
tACE
CELOWto
Data Valid
tlZCE
CE LOW to Low Z[9]
tHZCE
CEHIGHto
High Z[9, 10]
tpu
CELOWto
Power-Up
tpo
CE HIGH to
Power-Down
12
20
15
12
3
3
3
12
3
3
0
0
5
10
45
15
ns
ns
0
20
20
ns
ns
5
15
0
0
20
15
35
ns
ns
3
3
5
ns
45
35
25
8
0
12
3
5
8
45
35
25
20
15
7
25
20
15
25
ns
WRITE CYCLEfll]
twc
Write Cycle Time
12
15
20
20
25
40
ns
tSCE
CE LOW to
Write End
8
10
15
20
25
30
ns
tAW
Address Set-Up to
Write End
8
10
15
20
25
30
ns
tHA
Address Hold from
Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tpWE
WE Pulse Width
8
10
15
15
20
20
ns
tso
Data Set-Up to
Write End
6
7
10
10
15
15
ns
tHO
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
LowZ[9]
3
3
5
5
5
5
ns
tHZWE
WE LOW to
HighZ[9,10]
6
7
7
7
10
15
ns
Shaded area contams advanced mformahon.
Notes:
8. Test conditions assume signal transition time of 5 ns or less, liming reference levels of 1.SV; input pulse levels of 0 to 3.0V; and outputIoading
of the specified IOrJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
10. tHZCE and tHzWE are specified with CL = 5 pF as in part (b) of AC
'Illst Loads. ltansilion is measured ±SOO m V from steady state
voltage.
11. The internal write time ofthe memory is defined by the overlap ofCE
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate a write by goingIDGH. The data input setup and hold liming should be refc renced to the rising edge of the signal
that terminates the write.
2-363
•
.n~NDucroR
CY7C187A
Switching Waveforms
Read Cycle No. d 12, 13]
tRC
~/
ADDRESS
~/
tAA
-
tOHA.--=-!
PREVIOUS DATA VALID
DATA OUT
*XX) {
DATA VALID
C187A-7
Read Cycle No. 2[12, 14]
tRC
~~
'" 1.2
vs.AMBffiNT TEMPERATURE
60
I
II
o
0.0
Vcc= 5.0V
TA=25°C
V
/
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
=;:::~
--
~NDUCTOR
,
CY7C187A
1YPical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
30.0
J
2.5
25.0
0
2.0
I!;J
~
a:
0
1.0
z
0.5
-
-"~
0.0
0.0
1.0
2.0
3.0
4.0
1.25
.r-
/
20.0
/
~
,:( 15.0
!j
~ 10.0
~
::;: 1.5
/
5.0
5.0
/
V
SUPPLY VOLTAGE (V)
200
/
Jl
,
400
600
o
,-
800 1000
CAPACITANCE (pF)
Address
Function
Pin
Number
AO
X3
1
Al
X4
2
A2
X5
A3
X6
3
4
A4
AS
X7
Y7
A6
Y6
5
6
7
A7
A8
A9
Y2
8
Y3
YI
14
15
AI0
All
YO
Y4
16
A12
Y5
A13
Al4
XO
Xl
18
19
20
A15
X2
21
17
Truth Table
CE
WE
H
X
HighZ
L
H
Data Out
Read
L
L
Data In
Write
Inputs/Outputs
Mode
Deselectlfuwer-Down
2-366
Vee = 5.0V
TA = 25°C
Vee = 0.5V
I!;J
Vcc=4.5V TA = 25°C
Address Designators
Address
Name
NORMALIZED Icc VB. CYCLE TIME
VS., OUTPUT LOADING
VS_
3.0
~
a:
oZ
o·501''=o----:2!:::o:----;!3~0-----:!40
CYCLE FREQUENCY (MHz)
-~
.
.};; CYPRESS
-
F
CY7C187A
SEMICONDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
Package
lYpe
12
CY7C187A-12DMB
010
CY7C187A-12KMB
K73
CY7C187A-12LMB
L52
CY7C187A -15DMB
010
CY7C187A-15KMB
K73
15
20
25
35
45
CY7C187A-15LMB
L52
CY7C187A-20DMB
010
CY7C187A-20KMB
K73
CY7C187A-20LMB
L52
CY7C187A-25DMB
D10
CY7C187A-25KMB
K73
CY7C187A-25LMB
L52
CY7C187A-35DMB
010
CY7C187A-35KMB
K73
CY7C187A-35LMB
L52
CY7C187A-45DMB
010
CY7C187A-45KMB
K73
CY7C187A-45LMB
L52
•
Operating
Range
Military
Military
Military
Military
Military
Military
Shaded area contams advanced informalion.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
tRe
7,8,9, 10, 11
VIR
1,2,3
tAA
7,8,9,10,11
VILMax.
1,2,3
tOHA
7,8,9, 10, 11
IJX
1,2,3
tACE
7,8,9, 10, 11
loz
1,2,3
los
1,2,3
twe
7, 8, 9, 10, 11
lee
1,2,3
tSCE
7,8,9,10,11
ISBl
1,2,3
tAW
7,8,9, 10, 11
ISB2
1,2,3
tHA
7,8,9,10,11
tSA
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tUD
7,8,9, 10, 11
READ CYCLE
WRITE CYCLE
Document#: 38-00115-A
2-367
CY7C189
CY7C190
CYPRESS
SEMICONDUCTOR
Features
16 X 4 Static R/W RAM
• 'Three-state outputs
• T'I'L-compatible Interface levels
• Fully decoded, 16 word x 4-blt higbspeed CMOS RAMs
• Inverting outputs CY7C189
• Non-Inverting outputs CY7Cl!1O
FUncUonalDe~ption
• Hlgbspeed
-15 ns and 25 ns (commerdal)
-25 ns (military)
• Lowpower
-303 mW at 25 ns
-495 mWat 15 ns
• Power supply 5V :i: lK
• Advanced higb-speed CMOS processiog for optimum speed/power product
• Capable ofwithstaoding greater than
2001V static discharge
'The CY7C189 and CY7C190 are extremely high performance 64-bit static
RAMs organized as 16 words by 4 bits.
Easy memory expansion is~ded by an
active LOW chip select (CS) input and
three-state outputs. 'The devices are provided with inverting (CY7C189) and non-
inverting (CY7Cl90) outputs.
Writing to the device is accomplished
when the chip select ~ and write enable ~ Inputs are both LOW. Data on
the four data ioputs (Do through DJ) is
written into the memory location specified 00 the address pins (Ao through A3).
'The outputs are preconditioned such that
the correct data is present at the data outputs (00 through 03) when the write cycle
is complete. 'Ibis precondition operation
insures minimum write recovery times by
eliminating the "write recovery glitch."
Reading the device is accomplished by
taking c~lect ~ LOW, while write
enable (WE) remains mOHo Under
these conditions, the cooteots of the
memory location specified on the address
pins will appear on the four output pins
(00 through 03) in inverted (CY7C189)
or non-inverted (CY7C19O) formal
The four output pins remain in ~im
pedance state when c~lect (CS) is
mOH or write enable (WE) is LOW.
Pin Configurations
Logic Block Diagram
C\'7Cl89
DIP
ThpView
C\'7C19O
Ao
Do
1
CI
WE
Do
(0'0)00
0,
(lJ,)O,
ClND
Do
Do
L..-_...J
0189-3
Ao
00
Ao
A,
0,
A,
Ao
0.
Ao
Ao
Do
CI
LCC
ThpView
!;ll~~~';
4
5
6
7
8
Ao
CI
WE
3 2~, 201~8
17
16
15
14
910111213
70189
70190
WE
0189-1
0189-4
0189-2
Selection Guide
Maximum Access Time (os)
Commercial
7CI89-15
7Cl90-15
7CI89-25
7Cl90-25
15
2S
2S
90
55
Military
Maximum Operating Curreot (rnA)
Commercial
Military
2-368
70
CY7C189
CY7C190
lz ~PRE&s
I'
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. Ambient Temperaturewith
PowerApplied....................... Supply Voltage to Ground Potential
(Pin 16 to Pin 8) . . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
Electrical Characteristics
Parameters
VOH
VOL
65°Cto +150°C
55°Cto +125°C
Output Current, into Outputs (Low) .......... . . . . .. 10 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . ........................... >200rnA
Operating Range
- O.5V to + 7.0V
Range
Commercial
- O.5V to +7.0V
- 3.0V to + 7.0V
Military/I]
Ambient
lemperatnre
O°Cto +70°C
Vee
5V± 10%
- 55°C to + 125°C
5V ± 10%
Over the Operating Range [2]
Description
Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
lest Conditions
Vee = Min., IOH = - 5.2 rnA
7C189-1S
7Cl90-1S
Min. Max.
2.4
GND:::; Vr:::; Vee
Output LeakagcCurrcnt
GND-- Oa
'lbp View
I--l-l--Il>-- Os
At
1
28
Va;
A7
2
27
""
""
3
28
Ao
5
24
'vi.
A"
67 78191 23
22
A,
A,.
A,.
A,.
8 78192 21 10
9
2010
10
19 O.
10
I,
llE
11
12
13
18
17
16
O.
0,
00
GND
14
15
WE
Ao425Ao
A,o
A12
8191-1
Selection Guide
2-374
Ao
8191-3
---.
:~
CY7B191
CY7B192
PRELIMINARY
- - i f ! CYPRESS
F SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied .......................
Static Discharge Voltage ....................... . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ........................... . >200 rnA
Operating Range
- 55°Cto +125°C
Supply Voltage on Vee Relative to GND[lJ . - O.5V to + 7.0V
DC Voltage APftlied to Outputs
in High Z State 1J .......................
DC Input Voltagef1 J ....................
Ambient
'lemperature[2J
Vee
O°Cto +70°C
5V± 10%
- 55°C to +125°C
5V ± 10%
Range
Commercial
- 0.5Vto +7.0V
- O.5V to + 7.0V
Military
Current into Outputs (LOW) ................. . . . .. 20 rnA
Electrical Characteristics Over the Operating Rangef3J
7B191-10
7B192-10
Description
Parameters
VOH
VOL
VIH
VIL
'lest Conditions
Min.
Output HIGH \tIltage Vee = Min., IOH = - 4.0 rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
0.4
Input HIGH Voltage
Input LOW Voitagef1J
2.2
IIX
Input Load Current
GND~VI~Vee
Ioz
Output Leakage
Current
Output Short
CircuitCurrent[4J
Vee Operating Supply
Current
GND~VI~Vee,
-10
Vee = Max., lOUT = 0 rnA
f = fMAX = litRe
AutomaticCE
Power-Down Current
- CMOS Inputs
Max. Vee, CE ~ Vee - 0.3y, COm'!
VIN ~ Vee - O.3Vor
Mil
VIN ~ 0.3y, f = 0
Icc
ISB
Min.
Max.
2.4
2.4
- 0.3
-10
los
Max.
7B191-12
7B192-12
Vee
0.8
+10
+10
7B191-15,20
7B192-15,20
Min.
0.4
2.2
- 0.3
-10
-10
Max.
Units
0.4
V
Vee
0.8
+10
+10
V
V
J.IA
J.IA
2.4
Vee
0.8
+10
+10
2.2
- 0.3
-10
-10
V
OutputDisab!ed
Vee = Max., VOUT = GND
COm'l
-300
-300
-300
rnA
170
160
150
160
rnA
170
30
30
rnA
40
40
Mil
30
Shaded area contams advanced mformatlOn.
Capacitance[5J
Parameters
Description
CIN
Input Capacitance
CoUT
Output Capacitance
'lest Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 2.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. Seethe last page of this specification for Group A subgroup testing information.
= 1 MHz,
Max.
Units
10
pF
10
pF
4. Not more than 1output should he shorted at one time. Duration of the
5.
2-375
short circuit should not exeeed 30 seconds.
Tested initially and after any design orproeess changes that may affect
these parameters.
CY7B191
CY7B192
PRELIMINARY
AC Test Loads and Waveforms
Rl481.o.
5V 0 -_ _- -Rl481.o.
'__.,
5Vo----"""'..,
ALL INPUT PULSES
ollTPurO----200lV
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ........................... . >200 rnA
Operating Range
Range
Commercial
Military
Ambient
Thmperature[l]
Vee
O°Cto +70°C
5V ± 10%
- 55°Cto +125°C
5V± 10%
DClnputVoltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Electrical Characteristics
Over the Operating Rangel2]
7C191-12
7Cl92-12
Parameters
Description
Min.
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
Max.
2.4
7C191-15
7C192-15
Min.
Units
0.4
V
Vee
V
2.4
0.4
2.2
Max.
Vee
2.2
V
VIL
Input LOW Voltage
-0.5
··0.8
-0.5
0.8
V
IJX
Input Load Current
GNDs VIS Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GNDsVosVee,
Output Disabled
-10
+10
-10
+10
IJA
IJA
los
Output Short
CircuitCurrent[3]
Vee = Max., VOUT = GND
-350
-350
rnA
Icc
Vee Operating
Supply Current
Vee = Max., loUT = 0 rnA,
f = fMAX = litRe
160
150
rnA
IsBl
AutomaticCE Power-Down
Current-lTLlnputs
Max. Vee,CE~ VIH,
VIN ~ VIH or VIN S VIL f = fMAX
40
40
ISB2
AutomaticCE Power-Down
Current-CMOS Inputs
Max. Vee, CE~ Vee - O.3V,
VIN ~ Vee - O.3VorVIN sO.3Y,f= 0
20
20
Shaded area contams advanced informalion.
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
I Com'l
I Mil
160
rnA
rnA
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4. Tested iuitially and after any design or process changes that may affect
these parameters.
2-381
CY7C191
CY7C192
1tVt~~CfOR
Electrical Characteristics Over the Operating Rangel2J (continued)
7C191-20
7Cl92-20
Description
Parameters
Thst Conditions
Min.
7C191-25, 35, 45
7C192-25, 35, 45
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage
-0.5
IIX
Input Load Current
GND.:5. Vr.:5. Vee
-10
Ioz
Output Leakage
Current
GND.:5.Vo.:5.Vee,
Output Disabled
los
Output Short
CircuitCurrentl3]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max., loUT = 0mA,
f = fMAX = litRe
AutomaticCE Power·Down
Current-TfLlnputs
Max. Vee, CE ~ VIH,
VIN~ VIHOrVIN.:5. VIL,f=
AutomaticCE Power-Down
Current-CMOSInputs
Max. Vec, CE ~ Vee - 0.3v,
VIN ~ Vee - O.3VorVIN .:5.0.3v, f= 0
ISBl
IsB2
2.4
Min.
I Com'l
fMAX
V
V
2.2
Vee
V
0.8
-3.0
0.8
V
+10
-10
+10
+10
-10
+10
J.tA.
J.tA.
-350
rnA
140
120
rnA
150
130
40
35
rnA
20
20
rnA
-350
I Mil
Units
0.4
0.4
-10
Max.
2.4
Shaded area contams advanced mformation.
Capacitance [4]
Description
Parameters
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Units
10
pF
10
pF
AC Test Loads and Waveforms
R1481.n.
R1481.n.
5VD----.,.,.,..,
5VD------_..,
OUTPUTD---1r--i
OUTPUTo--~r--"
30PFI
R2
255.n.
5PFI
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
(h)
ALL INPUT PULSES
R2
255.n.
C191-5
C1914
THEVENIN EQUIVALENT
167.n.
OUTPUT OO--_"'\I\.·~---OO 1.73V
2-382
CY7C191
CY7C192
~~PRE:SS
~_., SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangel2,S]
7C191-12
7C192-12
Parameters
Description
Min.
Max.
7C191-15
7C192-15
Min.
7C191-20
7C192-20
Max. Min.
Max.
7C191-25
7C192-25
Min.
Max.
7C191-35
7C192-35
Min.
Max.
7C191-45
7C192-45
Min.
Max. Units
READ CYCLE
tRC
tAA
tOHA
tACE
tLZCE
Read Cycle Time
Address to Data
Valid
Output Hold from
Address Change
CELOWto
Data Valid
CE LOW to
LowZ[6]
tHZCE
CEHIGHto
HighZ[6,7]
tpu
CELOWto
Power-Up
tpo
CEHIGHto
Power-Down
15
12
12
3
3
3
3
3
7
0
20
15
12
0
13
0
3
0
ns
ns
20
0
ns
ns
45
35
ns
ns
45
15
2S
20
15
3
3
3
ns
45
35
25
10
45
35
3
3
3
0
35
25
20
8
12
25
20
15
ns
WRITE CYCLEtH]
twc
Write Cycle Time
12
15
20
45
CE LOW to
Write End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to
Low Z (7CI92)[6]
9
10
15
2S
20
35
tsCE
30
40
ns
ns
9
10
15
20
2S
35
ns
0
0
0
0
0
0
ns
0
0
0
0
0
0
ns
tAW
tHA
tSA
tpWE
tso
tHO
tLZWE
9
10
15
20
8
10
15
2S
17
30
20
ns
7
0
0
0
0
0
0
ns
3
3
3
3
3
3
ns
ns
tHZWE
WE LOW to
High Z (7CI92)[6,7j
7
7
10
13
15
20
ns
tAWE
WE LOW to
Data Valid (7CI91)
12
15
20
2S
30
35
ns
tADV
Data Valid to
Output Valid
(7CI91)
12
15
20
20
30
35
ns
Shaded area contams advanced information.
Note.:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputIoading
of the specified Im)loH and 30-pF load capacitance.
6. At aoy given temperature aod voltage condition, tHZCE is less thao
tLZCE, tHZWE is less thao trzWE for any given device. These parameters are gnaraoteed aod not 100% tested.
7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC
Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals mnst be LOW to initiate awrite and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
9. WE is HIGH for read cycle.
10. Device is contiouously selected, CE = VIL.
11. Address valid prior to or coincident with CE traosition LOW.
12. liCE goosHIGH simultaneously with WEHIGH, the output remains
in a high-impedaoce state (7C192 only).
2-383
«:
~PRFSS
""""!!!!E''
CY7C191
CY7C192
SEMICONDUCTOR
Switching Waveforms
€
Read Cycle No. 1[9, 10]
ADDRESS
--~
DATA OUT
PREVIOUS DATA
*-
IRC
1M
V::~~ JXX
1
*==============D=Al=A=I.l=A=LI=D==========
C19HI
Read Cycle No. 2[9, 11]
IRC
,~
lACE
-
HIGH IMPEDANCE
DATA OUT
v~
_Ipu
=1
DATA VALID
1'\,."-"-
IL2CE
SUPPLY
CURRENT - - - - - -
//
!HZCE-
HIGH
IMPEDANCE
1/
I---IPO
~ CC
I
50%
50%
IS6
C191-7
Write Cycle No.1 (WE Controlled)[8]
!we
ADDRESS
=:)t'
V
'I..
!seE
&~ ~r-...
/
W~ ~
lAW
!HA-
lSA
IPWE
~ !\.
)
DATA IN
/
Iso
r
~IHZWEj
DATA OUT
(7C192)
IHO ....
)K
DATA VALID
'-.:
DATA UNDEFINED
,/
!.--
IADV
~/
4
DATAOUT _ _ _ _ _ _ _ _D_AT_A_U_N_D_E_FI_NE_D_ _ _ _ _ _
(7C191)
-
IL2WE-
HIGH IMPEDANCE
1/
"
_ _ _ _ _ _D_A_TA_V_A_L_ID_ _ _ ___
C191-8
2-384
CY7C191
CY7C192
~
.
~=CYPRESS
~
F
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE ControUed) [8, 12]
~------------------------ Iwe--------------------------~
ADDRESS
1-----------
lSA
----------+10---- !see
Iso
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___... 14---!------DATA IN
DATA OUT
(7CI92)
--------;-.1
------..-.jot-
DATA VALID
~~~~~~~~~~~~~~~~~~~
HIGH IMPEDANCE
DATA VALID
C191·9
14------- lADY - - - - - - .
'lYPical DC and AC Characteristics
NORNUUJZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORNUUJZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
ill 1.2
Icc
jll.0
V
o
I!J
0.8
~
0.6
a:
V
4.5
~
1.2
I.........
Icc
w 0.8
::J
<
::;: 0.6
--
5.5
SUPPLY VOLTAGE
~ 80
o
..............
~ 60
::J
M
40
~ 20
a.
~
ISB
0.0
-55
6.0
w
1il
Vcc=5.0V VIN= 5.0V
0.4
0.2
I
5.0
w
a:
a:
az
120
Z 100
~
0
1
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
I-
...............
jll.0
N
I
ISB
0.0
4.0
V
VIN = 5.0V
TA = 25°C
~ 0.4
0.2
V
1.4
25
125
AMBIENT TEMPERATURE (0C)
a
o
J
1.3
Jl.4
!z
1.2
0
W
N
a:
~
::;:
1.1
az
1.0
a:
::J
............
r--.......
--..I---
0.9
0.8
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE M
M!
1.2
~
<
::;:
TA = 25°C
6.0
a: 1.0
az
~
0.8
0.6
-55
3.0
"
4.0
~ 140
0
w
"""
OUTPUT VOLTAGE M
.s 120
N
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.6
1.4
1.0
0.0
NORNUUJZEDACCESS TIME
vs. AMBffiNT TEMPERATURE
NO~ZEDACCESSTDdE
vs. SUPPLY VOLTAGE
'"
Vee = 5.0V
TA = 25°C
~
Vcc= 5.0V
a
80
Z
60
~
40
a
20
It:
en
~
~
25
125
AMBIENT TEMPERATURE (OC)
2-385
v
100
/
V
o
0.0
/
1/
Vee =5.0V
TA = 25°C
j
I
1.0
2.0
3.0
OUTPUT VOLTAGE M
4.0
CY7C191
CY7C192
~PRESS
~
SEMICONDUCIOR
'JYpical DC and AC Characteristics (continued)
TYPICALACCESS~ECHANGE
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
.
0
3.0
30.0
2 .5
25.0
l
0
w 2.0
ex:
z 1.0
0
0.0
0.0
,.-
/
--
V
o 10.0
/
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
5.0
5.0
8
fil1.00
/
~ 15.0
w
1.5
0.5
1.25.-------r------.-----,
::: 20.0
N
::i!
::;;
NORMAUZED Icc vs. CYCLE TIME
vs. OUTPUT LOADING
V
200
~
ex:
/
1/
N
@0.751---+-~'£'--+-----l
Vcc=4.5V TA=25"C
400
600
800 1000
CAPACITANCE (pF)
20
30
40
CYCLE FREQUENCY (MHz)
Ordering Information
Speed
(ns)
12
15
20
Package
lYpe
Operating
Range
Speed
(ns)
CY7C191-12DC
D22
Commercial
25
CY7C191-"12LC
L54
CY7C191-12PC
P21
CY7C191-25PC
P21
CY7C191-12VC
V21
CY7C191-25VC
V21
CY7C191-15DC
D22
CY7C191-25DMB
D22
CY7C191-15LC
L54
CY7C191-25KMB
K74
Ordering Code
CY7C191-15PC
P21
CY7C191-15VC
V21
CY7C191-15DMB
D22
Commercial
35
MilitlilY
Package
'J.Ype
Operating
Range
CY7C191-25DC
D22
Commercial
CY7C191-25LC
L54
Ordering Code
CY7C191-25LMB
L54
CY7C191-35DC
D22
CY7C191-35LC
L54
CY7C191-15KMB
K74
CY7C191-35PC
P21
CY7C191-15LMB
L54
CY7C191-35VC
V21
CY7CI91-ZODC
D22
CY7C191-35DMB
D22
CY7C191- ZOLC
L54
CY7C191-35KMB
K74
Commercial
CY7C191- ZOPC
P21
CY7C191- ZOVC
V21
CY7CI91-ZODMB
D22
CY7C191-ZOKMB
K74
CY7C191-45PC
P21
CY7C191-20LMB
L54
CY7C191-45VC
V21
45
Military
Shaded area contains advanced information.
2-386
CY7C191- 35LMB
L54
CY7C191-45DC
D22
CY7C191-45LC
L54
CY7C191-45DMB
D22
CY7C191-45KMB
K74
CY7C191-45LMB
L54
Military
Commercial
Military
Commercial
Military
CY7C191
CY7C192
-4 :~
~:- CYPRESS
~I
SEMICONDUcrOR
Ordering Information (continued)
Speed
(ns)
12
Operating
Range
CY7C192-12DC
D22
Commercial
CY7C192-12LC
154
Ordering Code
CY7C192-12PC
15
20
V21
CY7C192-15DC
CY7C192-15LC
D22
154
CY7C192-15PC
P21
CY7C192-15VC
V21
CY7CI92-15DMB
D22
CY7C192-15KMB
CY7C192-15LMB
K74
154
CY7C192-20DC
D22
CY7C192-20LC
154
CY7CI91-200MB
35
154
CY7CI92-25DC
CY7CI92-25LC
D22
154
45
Military
Commercial
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJl(
1,2,3
Ioz
1,2,3
Icc
1,2,3
IsBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Military
Parameters
K74
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9,10,11
P21
tOHA
7,8,9, 10, 11
tAcE
7,8,9,10,11
CY7CI92-25VC
V21
CY7CI92-25DMB
022
CY7C192-25KMB
CY7CI92- 25LMB
K74
154
CY7C192-35DC
D22
154
CY7CI92-35LC
CY7C192-35PC
Commercial
Parameters
P21
V21
022
CY7C191-20KMB
CY7C191-20LMB
CY7CI92-25PC
DC Characteristics
P21
CY7C192-12VC
CY7C192-20PC
CY7C192-20VC
25
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Package
1YPe
Commercial
WRITE CYCLE
Military
Commercial
P21
twc
7,8,9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7,8,9,10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
tpWE
7, 8, 9, 10, 11
CY7C192-35VC
CY7CI92-35DMB
V21
D22
CY7CI92-35KMB
K74
tSD
7, 8, 9, 10, 11
CY7C192-35LMB
CY7C192-45DC
154
7,8,9,10,11
D22
tHD
tAWE[13]
CY7C192-45LC
CY7C192-45PC
154
P21
tADV[13]
7,8,9, 10, 11
CY7CI92-45VC
V21
CY7C192-45DMB
022
CY7CI92-45KMB
K74
CY7C192-45LMB
154
Military
Commercial
7,8,9,10,11
Note:
13. 7C191 only
Military
Document #: 38-00076-G
Shaded area contains advanced information.
2-387
•
CY7B193
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Highspeed
- tAA = 12ns
• BieMOS for optimum speed/power
• Low active power
- 605mW
• Low staodby power
-275mW
• Automatic power-down when
deselected
• TIL-compatible inputs and outputs
256K X 1 Static RIW RAM
Readingthe device is accomplished by ta!i!!g
chip enable @) and output enable (OE)
The CY7B193 is a high-performance LOW, while WE remains inactive or HIGH.
BiCMOS static RAM organized as 256K Under these conditions, the contents of the
words by 1 bit. Easy memory expansion is location specified on the address pins is presllrovided by an active LOW chip enable ent on the data input/output pin (I/O).
(CE), an active LOW output enable (OE),
and three-state drivers. The device has an The input/output (I/O) is in a high-im~
automatic power-down feature that re- dance when the device is deselected @
duces its power consumption by more than HIGH), the outputs are disabled (Q!!
HIGH), or during a write operation (WE
50% when it is deselected.
LOW).
An active LOW write enable signal (WE)
controls the writing.lreadin~eration of The CY7B193 is available in leadless chip
the memory. When CE and WE inputs are carriers and in space-saving 300-mil-wide
both LOW, data on the input/output pin is DIPs and SOJs.
written into the memory location specified
on the address pins (An throughA17).
Functional Description
Pin Configurations
Logic Block Diagram
DIP
SOJ
Top View
Top View
110
Vee
Vee
A17
A,s
A,.
A'4
A,.
A'2
All
A10
A17
A,s
A,.
Ao
GND
A'3
A'2
NC
All
As
A7
NC
As
OE
CE
110
'fiE
A'4
NC
NC
As
A,.
110
WE
GND
As
OE
CE
B193-2
B193-3
LCC
Top View
Au
A,
CE
As
As
A.
'fiE
OE
NC
Ao
As
A7
NC
As
B193-1
I/O
'fiE
GND
1
2
3
4
5
28
'Z1
28
25
24
23
6
7
8 7B'93
9
10
11
12
13
14
~
20
19
18
17
18
15
B193-4
Selection Guide
7Bln-10
78193-12
7BI93-15
7BI93-20
10
12
15
20
MaximumOperating
Current(mA)
Commercial
Military
140
130
130
125
125
125
MaximumStandby
Current(mA)
Commercial
30
30
30
40
40
MaximumAccess Time (ns)
Military
Shaded area contains advanced information.
2-388
40
-
·~~CYPRFSS
F
PRELIMINARY
CY7B193
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruser guidelines,
nottested. )
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . .
(per MIL-STD-883, Method 3015)
> 2001V
Storage Temperature ................. - 65°Cto+150°C
Latch-UpCurrent ............. . . . . . . . . . . . . . . .
>200 rnA
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage on Vee Relative to GND[l]
- O.5V to + 7.0V
Operating Range
DC Voltage Ap8lied to Outputs
inHighZState 1] .......................
DC Input Voltagel1] ....................
Ambient
Thmperature[2]
Vee
O°Cto +70°C
5V ± 10%
- 55°Cto +125°C
5V± 10%
Range
Commercial
-0.5Vto+7.0V
- O.5V to + 7.0V
Military
Current into Outputs (LOW) ................ . . . . .. 20 rnA
Electrical Characteristics
Over the Operating Rangel3]
7B193-10
Description
Parameters
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min.,IoH = - 4.0 rnA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
Input LOWVoltagel1]
Vee = Min.,IOL = 8.0 rnA
Input Load Current
GND-----.....,
5\1<>----_........
--+
20PFI
OUTPUT<>---....
3.0V~
5PFI
R2
255.0.
INCLUDING
JIG AND _
R2
255.0.
GND 5 . 3 " : :
90%
INCLUOING
JIGAND _
SCOPE (a)
Equivalent to:
ALL INPUT PULSES
--+
OUTPUT<>---....
SCOPE -
(b)
B193-5
THEvENIN EQUIVALENT
B193-6
167.0.
OUTPUT 00----'\..""
...10---00 1.73V
Switching Characteristics
Over the Operating Rangel3,6]
7B193-10
Parameters
Description
Min.
Max.
7BI93-12
Min.
Max.
78193-15
Min.
Max.
7BI93-20
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
12
10
3
20
15
12
10
3
15
3
ns
20
3
ns
IoHA
Data Hold from AddressChange
tACE
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
6
7
10
12
ns
tLZOE
OE LOW to Low Z[8]
tHZOE
OE mGH to High Z[7, 8]
tlZCE
CE LOW to Low Z[8]
tHZCE
CE mGH to High Z[7, 8]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
2
2
2
7
6
3
3
6
0
10
ns
2
3
ns
10
8
3
ns
ns
7
8
10
ns
0
0
0
ns
12
15
20
ns
WRITECYCLEl9,IUJ
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
15
ns
tAW
Address Set-Up to Write End
8
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
8
9
10
15
ns
tSD
Data Set-Up to Write End
6
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tlZWE
WE mGH to Low z[8]
2
2
2
2
tHZWE
WE LOW to HighZ[7,8]
5
Shaded area contains advanced information.
Notes:
6. lest conditions assume signal transition time of3 ns or less, timing referencelevelsof1.5V,inputpulselevelsofOt03.0V,andoutputloading
of the specified IOrJIOH and 20-pF load capacitance.
7. tHZOE, IHzCE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC lest Loads. 'fransition is measured ±500mV
from steady state voltage.
8. At any given temperature and voltage condition, tHzCE is less than
tIZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWEfor any
given device.
9.
7
7
ns
10
ns
The internal write time of the memory is defined by the overlap of CE
WW and WE Ww. Both signals must be LOW to initiate awrite and
eilber signal will terminate awrite bygoing HIGH. The input data setup and hold timing should be referenced to the rising edge of Ibe signal
Ibat terminates Ibe write.
10. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
OE WW) is Ibe sum of IHzWE and lsD.
2-390
~~
PRELIMINARY
-------.; iE CYPRF.SS
=.'
CY7B193
SEMICONDUCfOR
Switching Waveforms
1111,12]
Read Cycle No.
ADDRESS
€
--~
DATA OUT
PREVIOUS DATA
*- •
IRC
1
lAA
V:~~; JXX *===============D=A=:r=A=V='A=LI=D===========~
B193-7
Read Cycle No. 2[12,13]
ADDRESS
)K
IRC
~i'\.
~~
lACE
*'
K.
I
lDOE
14--
DATA I/O
ILZOE -
HIGH IMPEDANCE
J
,-""",,",,,
tLZCE
I+--
Ipu
SUPPLY ________
CURRENT
VCC
DATA VALID
'//
I--
HIGH
-~ IMPEDANC
IHZCE
E
,/
14--
Ipo
50%
~I~:
I
B193-8
Write Cycle No.1 (CE Controlled)[14, 15]
~-----------------------Iwc -----------------------~
ADDRESS
CE ----r------------~~~----I~E ------~~----_+----~-----------------~w------------------~-WE
~~~~~~~~------------------~~~~~~~~"
'""t:>------- Iso -------<~
DATA I/O -----------------------------K~...--------D-AT-A-V-'AU--D---------' »-------B193-9
Notes:
11. Device is continnously selected. 00, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition low.
14. Datal/OishighimpedanceifOE = Vrn.
15. IfCE goes HIGH simultaneously with WEHIGH, the ontpnt remains
in a high-impedance state.
2-391
-=--.
~~
."~DUCTOR
PRELIMINARY
CY7B193
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE mGH During Write)[14,15]
~----------------------twc----------------------~
ADDRESS
WE----~----~~----~~~
14----
tPWE
--------+I
,-----------------
tso
DATAI/O
DATA VALID
B193-10
Write Cycle No.3 (WE Controlled, OE LOW)[lO,15]
ADDRESS
1 - - - - !so ----.-~
B193-11
Truth Table
CE
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read
Active (Icd
L
L
X
Data In
Write
Active (Icd
L
H
H
HighZ
Selected, Output Disabled
Active (Icd
Mode
I/O
Power
Power-Down
Standby (ISB)
2-392
PRELIMINARY
CY7B193
Ordering Information
Speed
(ns)
10
12
Package
1YPe
Operating
Range
Speed
(ns)
CY7B193-10DC
D14
Commercial
15
CY7B193-10LC
TBD
CY7B193-1OPC
P13
Ordering Code
CY7B193-10VC
V21
CY7B193-12DC
D14
CY7B193-12LC
TBD
CY7B193-12PC
P13
CY7B193-12VC
V21
CY7B193-12DMB
D14
CY7B193-12LMB
TBD
Commercial
20
Package
1YPe
Operating
Range
CY7B193 -15DC
D14
Commercial
CY7B193 -15LC
TBD
CY7B193-15PC
P13
Ordering Code
CY7B193-15VC
V21
CY7B193-15DMB
D14
CY7B193-15LMB
TBD
CY7B193-20DMB
D14
CY7B193-20LMB
TBD
Militaty
Shaded area contams advanced mformation.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
Vrn
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
!aHA
7, 8, 9, 10, 11
IIx
1,2,3
tACE
7, 8, 9, 10, 11
loz
1,2,3
tOOE
7,8,9,10,11
Icc
1,2,3
ISB!
1,2,3
ISB2
1,2,3
Parameters
Subgroups
READ CYCLE
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9,10,11
tHD
7, 8, 9, 10, 11
Document#: 38-00157-B
2-393
Military
Military
CY7B194
CY7B195
CY7B196
PRELIMINARY
CYPRESS
SEMICONDUCTOR
• Highspeed
tAA
Reading from the device is accomplished by
takin!l..£.hip enable one (CEI), chip enable
The CY7B194, 7B195, and CY7B196 are two (CE2, CY7B196. only), and output enhigh-performance BiCMOS static RAMs able (OE) LOW, while forcing write enable
organized as 65,536 words by 4 bits. Easy (WE) HIGH. Under these conditions, the
memory expansion ~ovided by an active contents of the memory location specified by
LOW chip enable (CEl), an active LOW the address pins will appear on the I/O pins.
chip enable (CEz, CY7B196 only), an active LOW output enable (OE, CY7B195 The four input/output pins (1/00 through
and CY7B196 only), and three-state driv- 1/03) are placed in a high-inlpedance state
ers. Both devices have an automatic power- when the device is deselected (CEl HIGH,
down feature that reduces powerconsump- or CEz HIGH CY7B196 only), the outputs
are disabled.J9E HIGH), or during a write
tion by more than 60% when deselected.
~ration (CEt. CE2 CY7B196 only, and
Writing to the device is accomplished by WE LOW).
taking.£!!!p enable one (CEl) and write enable ~) inputs LOW and chip enable The CY7B194, CY7B195, and CY7B196 are
two (CEz, CY7B196 only) input LOW. available in leadless chip carriers and in
Data on the I/O pin (1/00 through 1/03) is 300-mil-wideDIPs, and SOJs.
then written into the location specified on
the address pins (Ao through AlS).
Functional Description
Features
-
65,536 X 4 Static RIW RAM
=IOns
• BiCMOS for optimum speed/power
• Low active power
- 825mW
• Low standby power
-330mW
• Automatic power-clown when
deselected
• Output enable (OE) feature
(CY7B195 and CY7Bl96 only)
• 1TL-compatible inputs and outputs
Pin Configurations
Logic Block Diagram
SOJ/SOIC
Top View
DIP
Top View
Vee
As
~
As
As
A,
As
NC
NC
vo.,
110.,
110.,
110,
1100
CE1
GND
6194-2
GND
WE
6194-4.
DIP/SOJ/SOIC
Top View
vo,
Vee
As
voo
~
As
As
A"
,....,~...L.L.
6194-1
As
A'2
A13
WE
'---J:F=== (OE) (76'95 and
76196 only)
A,
A"
Q§, (76' 96 ONLy)
CE,
A'4
A,.
CE,
DE
GND
9
~ CE2(76196)
vo., L
I/o.,
NC (76195)
110,
1/00
WE
6194-3
Selection Guide
7B194-l0
7B195-10
7B196-l0
10
MaximumAccess TlIDe (ns)
Maximum 0serating
Current(mA
Maximum Standby
Current(mA)
Commercial
Military
Commercial
Military
170
;lU
Shaded area contains advaneed mformation.
2-394
7B194-l2
7B195-12
7Bl96-12
12
160
17U
,,0
40
7B194-l5
7B195-l5
7B196-l5
15
150
16U
30
40
7Bl94-20
7B195-20
7B196-20
20
150
40
REt
:~
CY7B194
CY7B195
CY7B196
PRELIMINARY
~=CYPRESS
~F
SEMlCONDUClDR
Pin Configurations (continued)
•
LCC
Top View
NC
~
A7
~
Ao
A,.
A"
A'2
A'3
A,.
A,.
NC(7B194)~
OE (7B195, 7B196)..J GND
1
2
3
28
Vee
27
26
25
Ao
Ao
Aa
5
6
7
8
9
10
11
12
13
2.
A2
23
22
A,
21
~ ~
•
Ao
20
1/0..
1/0,
19
18
17
16
15
,.
(7B194, 7B195)
CE2
(7B196)
vo,
1/00
WE
B194-5
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ,., .. ,." .. , ..... - 65°Cto +150°C
Ambient Thmperaturewith
Power Applied , .. , .. " ... , .. , ....... , - 55°Cto +125°C
Supply Voltage on Vee Relative to GND[1] , - 0.5V to + 7.0V
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature[2]
Range
DC Voltage Ap8lied to Outputs
io HighZ State 1]....................... - 0.5Vto +7.0V
DC Input Voltagel1] .................... - O.5Vto +7.0V
CurrentiotoOutputs(LOW) ...................... 20rnA
O°Cto +70°C
Vee
5V± 10%
- 55°C to +125°C
5V± 10%
Commercial
Military
Electrical Characteristics[3] Over the Operatiog Range
7B194-10
7B195-10
7Bl%-10
Parameters
VOH
VOL
VIH
VIL
IIX
Ioz
los
lee
IsB
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW VoltagellJ
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrend4]
Vee Operatmg
Supply Current
AutomaticCE
Power-DownCurrent
Min.
2.4
Thst Conditions
Vee - Min., IOH - - 4.0 rnA
Vee - Min., IOL - 8.0 rnA
2.2
- 0.3
-10
-10
GND~VI~VCC
GND~VI~Vee,
Output Disabled
Vee - Max., VOUT - GND
Com'l
Mil
Com'l
Vee - Max., lOUT - 0 rnA,
f = fMAX = lItRC
Max. Vee, CE or CE2 ~
Vee - 0.3V; VIN ~
Vee - O.3V or VIN ~ 0.3V;
f=O
Mil
Max.
0.4
Vee
0.8
+10
+10
78194-12
78195-12
78196-12
Min.
2.4
2.2
- 0.3
-10
-10
Max.
0.4
Vee
0.8
+10
+10
78194-15,20
78195-15,20
78196-15,20
Min.
2.4
2.2
-0.3
-10
-10
Max. Units
V
0.4
V
V
Vee
0.8
V
+10
(lA
+10
(lA
-300
-300
-300
rnA
170
160
170
30
150
160
30
rnA
40
40
30
rnA
Shaded area contams advanced information.
Notes:
1. VIL (min.) = - 2.0V for pulse durations ofless than 20 ns.
4.
2. TAis the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
5.
2-395
Not more than 1 output should be shorted atone time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
·
-
-~~PRESS
JF
CY7B194
CY7B195
CY7B196
PRELIMINARY
SEMICONDUCTOR
Capacitance [5]
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
Parameters
CIN
COUT
Max.
Units
10
pF
10
pF
AC Test Loads and Waveforms
R1 481 n.
5V < > - - - - - ' "
R1481n
5VD-----_
OUTPUT<>---.....-~
OUTPUTD---.....-~
20 P
FI
R2
255n.
5PFI
INCLUDING
JIG AND _
INCLUDING
JIG AND _
SCOPE -
SCOPE -
R2
GND
255n.
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.0V - - - - _......- - - - -......
8194-7
8194-6
THEVENIN EQUIVALENT
167il
OUTPUT~1.73V
Switching Characteristics[3.6] Over the Operating Range
Parameters
Description
READ CYCLE
Read Cycle Time
tRC
Address to Data Valid
tAA
Data Hold from AddressChange
tOHA
CE LOW to Data Valid
tACE
OE LOW to Data Valid
tDOE
OE LOW to LowZL8J
tLZOE
OE HIGH to High Z17, 8J
tHZOE
CE LOW to LowZl8j
tLZCE
CE HIGH to High Z[7, 8]
tHzcE
7B194-10
7B195-10
7Bl96-10
Min.
Max.
12
10
Write Cycle Time
CE LOW 10 Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to LowZ l8j
WE LOW to High Z[7,81
3
15
2
7
0
12
6
0
10
8
8
0
0
8
6
0
2
9.
10
10
3
8
0
15
20
15
15
0
0
15
10
10
0
0
10
8
0
2
7
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
15
12
9
9
0
0
9
7
0
2
10
10
0
20
20
12
8
3
3
3
3
2
10
0
2
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
10
7
6
20
15
12
7
2
7B194-20
7B194-20
7B196-20
Min.
Max.
15
3
3
10
6
Shaded area contains advanced information.
Notes:
6. Test conditions assume signal transition time of 3 os or less, timing reference levels of l.Sv, input pulse levels of 0 to 3.0V, and outputloading
ofthe specified IOJjIOH and 20-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. Transition is measured ± 500 m V from
steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZwEfor any
given device.
7B194-15
7B195-15
7B196-15
Min.
Max.
12
10
CELOW to Power-Up
tpu
CE HIGH to Power-Down
IpD
WRITECYCLEI",lUj
twc
tsCE
tAW
tHA
tSA
tpwE
tSD
tHD
tLZWE
tHZWE
7B194-12
7B195-12
7B196-12
Min.
Max.
The internal write time of the memory is defined by the overlap of CEI
Law, CE2 LOW and WE Law. All signals must be LOW to initiate
a write and any signal will terminate a write by going HIGH. The input
data set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
OE LOW) is the sum of tHZWE and IsD.
2-396
g~
'4
iF
CY7B194
CY7B195
CY7B196
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Switching Waveforms
€
Read Cycle No. 1[11,12]
ADDRESS
tRC
1
V~~~ JXX *==============D=A=T=A=~=Al=ID============
--~
DATA OUT
PREVIOUS DATA
1M
B194-8
Read Cycle No. 2[12,13]
ADDRESS
x
Y
tRC
~~
CE1
CE2 (7BI96)
lACE
,k
~'"
DE (7B195 and
7BI96 only)
'DOE
- - '[zOE--
DATAI/O
V~
HIGH IMPEDANCE
J
1////
-~
- - tHZCE
DATA VALID
"-""""-
_t[zCE
_tpu
SUPPLY _ _ _ _ _ _
CURRENT
-
I
HIGH
IMPEDAN CE
/
_tpo
5~CC
;O%~ISB
I
50%
B194-9
Write Cycle No.1 (C:\£l or CEz Controlled)[14, 15]
~------------------------twc------------------------~~
ADDRESS
CE1 ----+-------------------------~~~----~CE----~~--------_+--------CE2 (7BI96)
~-------------------lAw ------------------~~--WE
DATA I/O
..
~~~~~~~~----------------------------r~~
1"'1.1------
~o ----...;. .
~~~~
--------------t~"------DA-T-A-~-A-Ll-D---- )1------B194-10
Notes:
11. Device is continuously selected. CEI (OE: 7B195 and 7B196, CE2:
7B196 only) = VlLo
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CEI and CE2 transition low.
14. Data I/O is high impedance if OE = VIH.
15. !fCEI (CE1 or CE20n the 7B196) goeslllGH simultaneously with
WE lllGH, the output remains in a high-impedance state.
2-397
•
- ., ~(W)UCIOR
=
. .~
CY7B194
CY7B195
CY7B196
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.2 (WE ControUed, OE mGH During Write for 7B195 and 78196 only)[14,15]
~------------t~------------~
ADDRESS
eEl
eE2 (76196)
......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--''"'''''"''"''T'-4''''''. ..L.I.'-'-'"
....:~~:o...:a.~
~----~----~------~~~
.....- - - tPWE
----~
,-----------------
OE (76195 and
76196 only)
""",",",,,",",,"""'-J
1+----DATA I/O
Iso -------r---+I
tHO
DATA VALID
8194-11
Write Cycle No.3 (WE Controlled, OE LOW)[1O,15]
ADDRESS
CEl
CE2 (76196)
"'~:>,+~~~
__________________________________-.1.~~,*LL~~~~4
1+---DATAI/O
Iso - - -....--r
DATA VALID
8194-12
2-398
~
~~
PRELIMINARY
_'iECYPRESS
-:::;;;;;;.' SEMlCONDUcroR
7B194 Truth Table
eEl
WE
H
X
L
H
L
L
Mode
1/00 - 1/0 3
HighZ
Power
Power-Down
Standby (ISB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icc)
7B195 Truth Table
eEl
WE
OE
H
X
X
HighZ
L
H
L
L
L
X
L
H
H
Mode
1/00 - 1/0 3
Power
Power-Down
Standby (ISB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icc)
HighZ
Selected, Output Disabled
Active (Icc)
7C196 Truth Table
eEl
eE2 WE
OE
H
X
X
X
X
H
L
L
L
X
H
X
L
L
L
L
L
X
H
H
Inputs/Outputs
HighZ
HighZ
Data Out
Data In
HighZ
Mode
Power-Down
Power-Down
Read
Write
Selected,OutputDisabled
2-399
Power
Standby (ISB)
Standby (ISB)
Active (Icc)
Active (Icc)
Active (Icc)
CY7B194
CY7B195
CY7B196
~
.'~NDUCfOR
CY7B194
CY7B195
CY7B196
PRELIMINARY
Ordering Information
Spetd
(os)
1Q
"
12
15
20
Package
'Jype
Operating
Range
Speed
(ns)
CY7B194-10DC
D14
Cominercial
10
CY7B194-10LC
TBD
CY7Bl94-10PC
CY7B194-10VC
CY7B194-12DC
014
CY7B194-12LC
CY7B194-12PC
CY7B194-12VC
Ordering Code
Package
lYPe
Operating
Range
CY7B195~10DC
D22
Comtriercial
CY7B195 """10LC
TBD
PI3
CY7BI95-lOPC
V21
CY7B195-10VC
P13
V21
CY7B195-12DC
D22
TBD
CY7B195-12LC
TBD
P13
CY7B195-12PC
P13
V21
CY7B195-12VC
V21
CY7B194-12DMB
D14
CY7B194-12LMB
TBD
Military
12
15
20
D22
CY7B195-12LMB
TBD
D14
CY7B195 -l5DC
D22
CY7B194-15LC
TBD
CY7B195-15LC
TBD
CY7B194-15PC
P13
CY7B195 -15PC
P13
CY7B194-15VC
V21
CY7B195 -15VC
V21
CY7BI94-15DMB
D14
CY7B194-15LMB
TBD
CY7B194-20DMB
014
CY7B194-20LMB
TBD
Speed
10
CY7B195-12DMB
CY7B194-15DC
Military
20
Military
CY7B195 -150MB
022
CY7B195.,..15LMB
TBD
CY7B195-200MB
022
CY7BI95-20LMB .
TBO
Shaded area contains advanced iiiformation.
CY7B196-10DC
Package
lYPe
D22
CY7B196-10LC
TBD
Ordering Code
15
Commercial
Shaded area contains advanced information.
(ns)
12
Commercial
Ordering Code
CY7B196-1pPC
PI3
CY7B196-10VC
V21
CY7B196-12DC
D22
CY7B196-12LC
TBD
CY7B196-12PC
P13
CY7B196-12VC
V21
CY7B196-12DMB
D22
CY7BI96-12LMB
TBD
CY7B196-15DC
D22
CY7B196-15LC
TBD
CY7B196-15PC
P13
CY7B196-15VC
V21
CY7B196-15DMB
022
CY7B196-15LMB
TBD
CY7BI96-20DMB
D22
CY7B196-20LMB
TBD
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
Shaded area contams advanced mformatIOn.
2-400
.'
Commercial
Military
Commercial
Military
Military
-m :~
=-=
CYPRESS
,
SEMlCONDUCfOR
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
•
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB!
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
tAA
7,8,9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7,8,9,10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
CY7B194
CY7B195
CY7B196
Document#: 38-00158-B
2-401
CY7C194
CY7C195
CY7C196
CYPRESS
SEMICONDUCTOR
Features
• Automatic power-down when
deselected
• Output Enable (OE) feature (7C195
and7Cl96)
• CMOS for optimum speed/power
• Highspeed
- tAA=25ns
• Low active power
- 880mW
• Low standby power
- 220mW
• TTL-compatible inputs and outputs
65,536 X 4 Static R/W RAM
• Capable of withstanding greater than
2001V electrostatic discharge
and CY7C195, CE1, CE2 on the CY7C196)
andwrite enable (WE) inputs are both LOW.
Data on the four input pins (1100 through
1/03) is written into the memory location,
specified on the address pins (Ao through
A15)·
Readingthedevice is accomplished by taking
the chip enable(s) @on the CY7C194 and
CY7C195, CEl, CE2 on the CY7C196)
LOW, while write enable (WE) remains
HIGH. Under these conditions the contents
of the memory location specified on the address pins will appear on the four data output
pins.
A die coat is used to ensure alpha immunity.
Functional Description
The CY7C194, CY7C195, and CY7C196
are high-performance CMOS static RAMs
organized as 65,536 by 4 bits. Easy memory
expansionis.B!:.ovided by active LOW chip
enable(s) ~E ~ the CY7C194 and
CY7C195, CEl, CE2 on the CY7C196) and
three-state drivers. They have an automatic
power-down feature, reducing the power
consumptionby 75% when deselected.
Writing to the device is accomplished when
the chip enable(s) (CE on tbe CY7C194
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
DIP/SOJ
Top View
Vee
Ao
Ao
Ao
A2
A,
~
CE2
- [ (70196)
Va.
Vo.
NC
(70195)
vo,
va.
VOo
WE
Vo.
0194-2
vo,
0194-3
LCC
Top View
LCC
Top View
<-.f~~
I/O.
<"~~Jl.l?
3 2,1,2827
As
As
C£, (7C196 only)
A,.
A"
A'2
A,.
A'4
A15
CE,
WE
(DE)
(70195 and
7C'96 ONLy)
0194-1
CE
NC
(70194)
DE
-
4
5
6
7
8
9
10
26 Ao
As
As
25 Ao
24 Ao
23 As
22 A,
70194
21 As
7C195
20
11
19 I/O.
12
18 I/O,
1314151617
A,.
A"
A'2
A,.
A'4
A,s
Va.
CE1
]-I ~~I~~
32 ,1,2827
26
4
5
25
24
6
7
23
8
22
7C196
21
9
10
20
19
11
12
18
1314151617
A2
A,
As
NO
CE2
va.
Vo.
1[!j~I~§g
0194-4
(7C195)
Ao
Ao
0194-5
Selection Guide
7C194-12
7C195-12
7Cl96-12
Maximum Access Time (ns)
MaximumOperating
Current(mA)
I
I
Commercial
Military
Maximum Standby Current (mA)
7Cl94-15
7C195-15
7C196-15
7Cl94-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7Cl94-45
7C195-45
7C196-45
12
15
20
25
35
45
160
150
140
120
120
120
160
150
130
130
130
40
40
35
35
35
40
Shaded area contams advanced information.
2-402
CY7C194
CY7C195
CY7C196
~
~PRFSS
~;..
SEMICONDOCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°Cto +150°C
Ambient'Thmperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Electrical Characteristics
Parameters
VOH
VOL
Vrn
VIL
IJX
loz
los
lee
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .................... . . . . . . . . >200 rnA
Operating Range
Range
Commercial
Military
Ambient
Thmperature[l]
Vee
O°Cto +70°C
5V ± 10%
- 55°Cto +125°C
5V ± 10%
Over the Operating Rangef2]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrend3]
Vee Operating
Supply Current
IsBI
AutomaticCE
Power-DownCurrent
-TTLlnputs[4]
ISB2
Automatic CE
Power-DownCurrent
-CMOSlnputs[4]
7Cl!J4-12
7C195-12
7Cl96-12
Min. Max.
Thst Conditions
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
GND < VI< Vee
GND.$. Vo.$. Vee,
Output Disabled
Vee = Max.,
VOUT=GND
Vee - Max., lOUT - 0mA,
f =fMAX =l/tRe
7Cl94-15
7C195-15
7Cl96-15
Min. Max.
Vee
0.8
2.2
-0.5
Vee
0.8
Units
V
V
V
V
+10
+10
-10
-10
+10
+10
f1A
f1A
-300
-300
rnA
160
rnA
40
150
160
40
20
20
rnA
2.4
2.4
0.4
0.4
2.2
-0.5
-10
-10
lCom'l
I Mil
Max. Vco CEI,2 ~ Vrn,
VIN ~ Vrn or VIN .$. Vn.,
f=fMAX
Max. Vee, CEI,2 ~ Vee - 0.3v,
VIN ~ Vee - 0.3Vor
VIN.$. 0.3v, f = 0
rnA
Shaded area contains advanced information.
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3.
4.
2-403
Not more than 1 output should be shorted at one time. Duratiou of the
short circuit should not exceed 30 seconds.
A pull-up resistor to Vcc on the CE input is required to keep the device
deselected during V cc power-up, othctwise IsB will exceed values given.
•
CY7C194
CY7C195
CY7C196
.7,~a@uCfOR
Electrical Characteristics Overthe Operating Rangel2J (continued)
7Cl94 20 7Cl94 25,35,45
7C195-20 7C195-25, 35, 45
7C196-20 7Cl96-25, 35, 45
Min. Max. Min.
Max.
2.4
2.4
0.4
0.4
2.2
2.2
Vee
Vee
-0.5 0.8
-3.0
0.8
-10 +10
-10
+10
-10 +10
-10
+10
Description
Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrent[3]
Vee Operating
Supply Current
'lest Conditions
Vee = Min., IOH = - 4.0 rnA
Vee - Min., IOL = 8.0 rnA
ISBl
AutomaticCE
Power-DownCurrent
- TIL Inputs[4]
ISB2
AutomaticCE
Power-DownCurrent
-CMOSlnputs[4]
Max. V co CEl,2 2:. VIH,
VIN 2:. VIH or
VIN S VIL f = fMAX
Max. Vee, CEl,2 2:. Vee - 0.3v,
VIN 2:. Vee - O.3Vor
VIN < O.3V,f= 0
Parameters
VOH
VOL
VIH
VIL
lIX
loz
los
Icc
GNDS VIS Vee
GNDS VOSVcc,
Output Disabled
Vee - Max.,
VOUT=GND
Vee = Max., lOUT = OrnA,
f =fMAx =l/tRe
I Com'l
I Mil
Units
V
V
V
V
!LA
!LA
-350
-350
rnA
140
150
40
120
130
35
rnA
20
20
rnA
rnA
Shaded area contains advanced infonnation.
Capacitance [5]
Parameters
eIN
CoUT
Description
'lest Conditions
Max.
Units
InputCapacitance
OutputCapacitance
TA = 25°C,f= 1 MHz,
10
pF
Vee=5.0V
10
pF
Note:
S. Thstedinitially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481n.
sv o-______
IM...,
Rl48Hl
5V
O---~W'o..,
ALL INPUT PULSES
OUTPUTo---p---+
30PFI
INCLUDING
JIGAND _
SCOPE
-
Ol1ll'UTo---P---+
SPFI
R2
25Sn.
SCOPE -
(a)
Equivalent to:
R2
255.0.
INCLUDING
JIGAND _
(b)
Cl94-6
THEvENIN EQUIVALENT
167.0.
OUTPUT 00---"'1'.",'---00 1.73V
2-404
C194-7
.
CY7C194
CY7C195
CY7C196
:~
'I= CYPRESS
,
SEMlCONDUClDR
Switching Characteristics
Over the Operating Rangel2,6]
7C194-12
7C195-12
7Cl96-12
Parameters
DescriptioD
7C194-20
7C19S-20
7C196-20
7C194-15
7C195-15
7C196-15
Min. Max. Min.
7Cl94-2S
7C19S-25
7Cl96-2S
7Cl94-3S
7C19S-3S
7Cl96-3S
7C194-45
7C19S-4S
7C196-4S
Max. MiD. Max. Min. Max. Min. Max. MiD. Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
AddressChange
tACE!.
tACE2
tDOE
CELOWto
Data Valid
tLZOE
OE LOW to
Data Valid
OELOWto
LowZ
tHZOE
OEHIGH
to High Z[8]
tLZCEh
tLZCE2
tHZCEh
tHZCE2
tpu
CELOWto
LowZ[7]
tpD
CEHIGHto
Power-Down
12
12
3
7C195,
7C196
7C195,
7C196
7C195,
7C196
CELOWto
Power-Up
25
20
15
45
35
25
3
3
3
35
ns
45
3
3
DS
DS
12
15
20
25
35
45
DS
6
8
10
15
20
20
DS
0
8
8
8
7
0
0
0
12
13
10
3
0
3
15
0
25
ns
20
15
13
20
15
3
3
3
3
3
3
3
0
0
7
CEHIGHto
HighZ[7,8]
20
15
ns
20
0
35
ns
DS
DS
45
DS
WRITECYCLEl9J
twc
Write Cycle Time
12
15
20
25
ns
CELOWtoWrite
End
9
10
15
20
35
30
45
tSCE
40
ns
tAW
Address Set-Up to
Write End
Address Hold from
Write End
9
10
15
20
25
35
ns
0
0
0
0
0
0
ns
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tPWE
WE Pulse Width
9
10
15
20
25
30
ns
tSD
DataSet-Up (0
Write End
Data Hold from
Write End
7
8
10
15
17
20
ns
0
0
()
0
0
0
ns
tLZWE
WE HIGH to
LowZ[7]
3
3
3
3
3
3
ns
tHZWE
WELOW!o
HighZ[7,8]
tHA
tSA
tHD
7
7
Notes:
6. Thstconditionsassumesignal transition time ofS nsoriess, timing reference levels ofl.5Y, input pu Ise Icve Is ofO to 3.0V, and output loading
ofthe specified IOrJIOH and )() pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and lHzWE is less than tr.ZWE for any given device.
8. tHZOE, tHZCE, and lHzwE arc specified with CL = S pF as in part (b)
of AC Test Loads. Transition is measured ±SOO mV from steady state
voltage.
10
9.
2-405
0
13
0
15
0
20
ns
'I'he internal write time of the memory is defined by the overiapofCEl
I,OW, CEz Ww, and WE LOW. All signals must be WW to initiate
a write and any signal can terminate a write by going HIGH. The data
input sct-up and hold timing should be referenced to the rising edge of
Ihe signal that terminates the write.
•
CY7C194
CY7C19S
CY7C196
&~
.'~C1DR
Switching Waveforms
Read Cycle No. 1[10, 11]
IRC
)(
~(
ADDRESS
I-DATA OUT
--=,
JKXX) (
lAA
toHA
PREVIOUS DATA VALID
DATA VALID
CI94-8
Read Cycle No. 2[10, 12]
.......
IRC
"
/'{
lACE
OE
(7C195 and
7C196)
~
/f100E
I--DATA OUT
I[zCE
Vee
SUPPLY
CURRENT
-1-
-3
I+- IHZCE
ILZOE - -
HIGH IMPEDANCE
//
DATA VALID
""
/
I---
-Ipu
HIGH
IMPEDAN CE
Ipo
~ ICC
50%
ISS
CI94-9
Write Cycle No.1 (CE Controlled) [9, 13, 14]
~------------------------IWC ------------------------~~
ADDRESS
eEl
eE2
(7C196)
--t------------"'" "'--- lsee -----<-1.,----+---1---------- lAw - - - - - - - - -....-
.t:---.
Iso - - - -.....
DATA I/O
---------------k~......----D-AT-A-V-'A-l1-D---- lI------C194-10
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected: CEI = VIL CEz = VIL(7C196), and
OE = VIL (7C195 and 7C196).
12. Address valid prior to or coincident with CEI and CEz transition
Ww.
13. Data I/O will be high impedance if OE = Vrn (7C195 and 7C196).
14. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE WW) is the sum oftHZWE and tsn.
2-406
CY7C194
CY7C195
CY7C196
-=-
~~
=-=CYPRESS
. ' SEMICONDUC'TOR
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OlE IDGH During Write for 7C195 and 7C196 only)[9, 13, 14)
twc
------------1
ADDRESS
GEl
CE2(7C1~)~~~~~~~------------------------------------~~~~~~~~~
WE
---....;...--......;;;..:---......h......."
DATA I/O
)1...---1(
14----
tPWE
----~
,r--------
~r:-=-=-:-:-:-=-=:.~ts~O~====~:::j tHO
)1----------
DATA VALID
L-~~~~L-~~
Cl94-12
Write Cycle No.3 (WE Controlled. OE LOW)[14, 15)
ADDRESS
GEl
CE2 (7G19S) ...:...:..~~~...:..;:1o.-__________________________________......."""~4"""~:£..J.~"""L.L
WE
-----------n-.. . .
'T'Io.
1*----
Iso ---.~~
Cl94-11
1YPical DC and AC Characteristics
NORMUUAZED SUPPLY CURRENT
AMBIENT TEMPERATURE
NORMUUAZED SUPPLY CURRENT
SUPPLY VOLTAGE
VS.
VS.
104
lJl1.2
Icc
13 1.0
V
c
~ 0.8
~
O.S
V
0.0
4.0
1.4
ID
~
-
5.0
0
SUPPLY VOLTAGE (V)
S.O
0.0
-55
~120
!Z 100
~
~
...............
:::>
~
o
80
~ SO
~
a:
:::>
lil
Vcc= 5.0V VIN = 5.0V
0.4
0.2
5.5
Icc
a:
I
4.5
............
w 0.8
N
::J
~ O.S
z
IS8
1.2
13
1.0
c
VIN= 5.0V
TA=25°C
a:
~ 004
0.2
V
L.?
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
:::>
125
AMBIENT TEMPERATURE ("G)
2-407
40
I-
IS8
25
~
5o
20
o
0.0
1.0
2.0
Vcc=5.0V
TA = 25°G
"'" ""
3.0
OUTPUT VOLTAGE M
4.0
CY7C194
CY7C195
CY7C196
1YPical DC and AC Characteristics (continued)
NO~ZEDACCESS~
NO~ACCESSTIME
vs. SUPPLY VOLTAGE
.... AMBIENT TEMPERATURE
~
« 1.1
"'-.
:;
a::
-- -
0.9
0.8
4.0
4.5
~
5.0
5.5
1.2
15~
TA = 25°C
I'......
1.0
z
I---------I--------~
1.0
0.81--------+----------1
0.6_1-:5",,5------""251.::----------,1""5
6.0
~
2.5
25.0
S
..!!-
/
~ 20.0
2.0
N
:::;
~ 1.5
0.0
0.0
ti
-
./
/
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE
60
40
/
15.0
~ 10.0
5.0
V
/
0.0 0
5.0
M
200
V
/
Vee =5.0V
J
§ V/
o
--
30.0
0.5
Z
!5
TA = 25°C
I
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
TYPICAL ACCESS TIME CHANGE
.... OUTPUT LOADING
3.0
a::
~ 1.0
80
AMBIENT TEMPERATURE (OC)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
fa
aa::
1ij
:it
r
~ 100
~
M
SUPPLY VOLTAGE
0
~12O
j 1.41-----11------1
1.3
c 1.2
w
0
~ 140
1.6
1.4
J.
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED Icc vs. CYCLE TIME
1.25
~
fa 1.00
N
~
a::
/
Vcc=4·9V TA- 25°C
400
600
~ 0.751------1--."."'--+-----1
800 1000
20
30
CYClE FREQUENCY (M~z)
CAPACITANCE (pF)
7C194 Truth Thble
CE
WE
H
X
H
L
L
L
Power
Mode
DataI/O
HighZ
OeselectlPower-Oown
Standby (ISB)
Data Out
Read
Write
Active (Icc)
Data In
Active (Icc)
7C195 Truth Thble
CEl
H
WE
X
L
L
H
L
H
OE
X
L
X
H
L
Data I/O
IIigh Z
Data Out
Data In
High Z
Mode
O!lSelectlPower-Oown
Read
Write
Deselect
Power
Standby (ISB)
Active (Icd
Active (Icd
Active (Icd
7C196 Truth Table
CEl
H
X
L
L
L
CEl··
X
H
L
L
L
WE
X
X
H
L
OJ<:
H
"
X
X
Mode
Data I/O
HighZ
4.0
M
Pm-.er
OeselectIPower-Down
Standby (ISB)
L
Data Out
Read
X
OataIn
HighZ
Write
Active (Icc)
Active (Icc)
Oes,elect
Active (Icc)
2-408
40
CY7C194
CY7C195
CY7C196
~
. :::Z
~=CYPRESS
~, SEMICONDUClDR
Ordering Information
Speed
(ns)
12
15
20
25
35
45
Ordering Code
CY7CI94-12DC
CY7C194-12LC
CY7C194-12PC
CY7C194-12VC
CY7C194-15DC
CY7C194-15LC
CY7C194-15PC
CY7C194-15VC
CY7C194-15DMB
CY7C194-15KMB
CY7C194-15LMB
CY7C194-20DC
CY7C194-20LC
CY7C194-20PC
CY7CI94-20VC
CY7C194-20DMB
CY7C194-20KMB
CY7C194-20LMB
CY7C194-25DC
CY7C194-25LC
CY7CI94-25PC
CY7CI94-25VC
CY7CI94-25DMB
CY7CI94-25KMB
CY7C194-25LMB
CY7C194-35DC
CY7C194-35LC
CY7C194-35PC
CY7C194-35VC
CY7C194-35DMB
CY7C194-35KMB
CY7C194-35LMB
CY7C194-45DC
CY7C194-45LC
CY7C194-45PC
CY7C194-45VC
CY7C194-45DMB
CY7C194-45KMB
CY7C194-45LMB
Shaded area contains advanced information.
Package
'iype
Operating
Range
Speed
(ns)
D14
154
P13
Vl3
D14
154
P13
Vl3
D14
K73
154
D14
154
P13
Vl3
D14
K73
154
D14
154
Pl3
Commercial
12
Vl3
D14
K73
154
D14
154
P13
V13
D14
K73
154
D14
154
Pl3
V13
D14
15
Commercial
Military
Commercial
20
Package
Ordering Code
CY7C195-12DC
CY7C195-12LC
CY7C195-12PC
CY7C195-12VC
CY7C195-15DC
CY7C195-15LC
CY7C195-15PC
CY7CI95-15VC
CY7C195-15DMB
CY7C195-15KMB
CY7CI95-15LMB
CY7C195-20DC
CY7C195-25LC
CY7C195-20PC
CY7CI95-20VC
. CY7C195-20DMB
Military
CY7CI95;....20KMB
Commercial
25
Military
Commercial
35
Military
45
Commercial
Military
K73
154
CY7CI95-20LMB
CY7C195-25DC
CY7C195-25LC
CY7C195-25PC
CY7C195-25VC
CY7C195-25DMB
CY7C195-25KMB
CY7C195-25LMB
CY7C195-35DC
CY7C195-35LC
CY7C195 - 35PC
CY7C195 - 35VC
CY7C195-35DMB
CY7C195-35KMB
CY7C195-35LMB
CY7C195-45DC
CY7C195-45LC
CY7C195-45PC
CY7C195-45VC
CY7C195-45DMB
CY7C195-45KMB
CY7C195-45LMB
Shaded area contains advanced information.
2-409
'!ype
022
154
P21
V21
D22
1.54
• P21
V21
D22
K74
154
D22
154
P21
V21
D22
K74
154
022
154
P21
V21
D22
K74
154
022
154
P21
V21
D22
K74
154
D22
154
P21
V21
D22
K74
154
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
•
CY7C194
CY7C195
CY7C196
:C;~PRFSS
~#'
SEMICONDUCTOR
Ordering Information (continued)
Speed
(ns)
12
15
20
25
Package
Ordering Code
1YPe
CY7C196-12DC
CY7C196-12LC
D22
L54
CY7C196-12PC
P21
CY7C196-12VC
V21
CY7C196""'15DC
CY7C196-15LC
CY7C196-15PC
D22
L54
35
45
Commercial
DC Characteristics
Commercial
P21
CY7C196-15VC
V21
CY7C196-15DMB
D22
CY7C196-15KMB
CY7C196-15LMB
CY7C196-20DC
K74
L54
D22
CY7C196-20LC
L54
CY7C196-20PC
P21
CY7C196-20VC
CY7C196-20DMB
V21
D22
CY7C196-20KMB
K74
CY7C196-20LMB
CY7C196- 25DC
D22
CY7C196-25LC
CY7C196-25PC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Operating
Range
Military
Commercial
V21
D22
CY7Cl96-25KMB
K74
CY7C196-25LMB
CY7C196-35DC
L54
D22
CY7C196-35LC
L54
CY7C196-35PC
P21
CY7C196-35VC
V21
CY7C196-35DMB
CY7C196-35KMB
D22
K74
CY7C196-35LMB
L54
CY7C196-45DC
D22
CY7C196-45LC
L54
CY7C196-45PC
CY7C196-45VC
P21
V21
CY7Cl96-45DMB
D22
CY7C196-45KMB
K74
CY7C196-45LMB
L54
VOH
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
los
1,2,3
Icc
1,2,3
ISB!
1,2,3
ISB2
1,2,3
1,2,3
Parameters
Subgroups
READ CYCLE
Commercial
L54
P21
CY7C196-25DMB
Subgroups
1,2,3
Switching Characteristics
Military
154
CY7C196-25VC
Parameters
Military
tRC
7, 8, 9, 10, 11
tAA
7,8,9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE,ACE2
tDOE[16]
7,8,9,10, 11
7,8,9,10, 11
WRITE CYCLE
Commercial
Military
Commercial
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7,8,9,10, 11
tpWE
7,8,9,10, 11
tSD
7,8,9, 10, 11
tHD
7,8,9, 10, 11
Note:
16. 7C195 and 7C196 only.
Document#: 38-00081-F
Military
Shaded area contains advanced mformation.
2-410
CY7B197
PRELIMINARY
CYPRESS
SEMICONDUCTOR
256K X 1 Static R/W RAM
Features
Functional Description
• Highspeed
- tAA
IOns
• BieMOS for optimum speed/power
• Low active power
-770mW
• Low standby power
-165mW
• Automatic power-down when
deselected
• TIL-compatible inputs and outputs
The CY7BI97 is a high-perfonnance BiCMOS static RAM organized as 256K
words by 1 bit. Easy memory expansion is
Qrovided by an active LOW chip enable
(CE) and three-state drivers. The
CY7B197 has an automatic power-down
feature, reducing the power consumption
by more than 50% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW: Data on the input pin
(DIN) is written into the memory location
specified on the address pins (Ao through
A17)·
=
Logic Block Diagram
Readingthe device is accomplished by taking
c!!!E.. enable (CE) LOW while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified by the address pins will appear on
the data output (DOUT) pin.
The output pin (DOUT) is placed in a highimpedance state when the device is deselecte~E HIGH) or during a write operation (WE LOW).
The CY7Bl97 is available in a leadless chip
carrier and space-saving 300-mil-wide DIPs
and SOJs. It utilizes a die coat to insure alpha
immunity.
Pin Configurations
DIP
ThpView
D,N
A,
A2
As
~
A,.
A,.
A,.
An
As
As
Dour
As
A,
WE
Dour
GND
As
4
SOJ
ThpY"ww
Vee
Vee
A17
A,.
A,.
A,.
A'3
A'2
All
AID
An
A,.
A,.
A,.
NC
A'3
A'2
NC
As
All
A,o
D,N
CE
As
D,N
8197-2
As
CE
GND
8197-3
LCe
Top View
E
As
28
27
A,
E
As
4
28
25
~
NC
5
6
7
24
23
22
NC
9
10
As
11
DOUT
12
13
20
'9
18
17
16
15
As
8197-1
As
As
A7
WE
GND
3
8 78197 21
"
Vee
A'7
A,.
A,.
A,.
NC
A'3
A'2
NC
All
AID
As
o,N
CE
8197-'
Selection Guide
MaximumAccess Time (ns)
Maximum Operating
Current(mA)
Commercial
MaximumStandby
Current(mA)
Commercial
7B197-10
7B197-12
78197-15
78197-20
10
12
15
20
140
130
125
130
125
30
30
40
40
Military
30
Military
Shaded area contams advanced mfonnatlOn.
2-411
125
40
•
PRELIMINARY
CY7B197
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
StorageThmperature ................. - 6s 0 Cto +1S0°C
Ambient Temperaturewith
PowerApplied ....................... - 55°C to +12soC
Supply Voltage on Vee relative to GND[l]
- O.5V to + 7.0V
DC Voltage A~lied to Outputs
inHighZState ].......................
DClnputVoltage£l] ....................
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Temperature[2]
Vee
O°Cto +70°C
SV± 10%
- 5s 0 Cto +125°C
5V± 10%
Range
Commercial
- O.5Vto +7.0V
- O.5Vto +7.0V
Military
Current into Outputs (LOW) .......... . . . . . . . . . . .. 20 rnA
Electrical Characteristics
Over the Operating Range£3]
7B197-10
Parameters
Description
Min.
lest Conditions
Max.
2.4
7B197-12
Min.
Max.
2.4
7B197 -15, 20
Min.
Max.
Units
0.4
V
2.4
VOH
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltage£l]
- 0.3
0.8
- 0.3
0.8
-0.3
0.8
V
+10
-10
+10
-10
+10
+10
-10
+10
-10
+10
I1A
I1A
0.4
Vee = Min., IOL = 0.8 rnA
IIX
Input Load Current
GNDs VIS Vee
-10
Ioz
Output Leakage
Current
GNDs VaS Vee.
Output Disabled
-10
los
Output Short Circuit
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
AutomaticCE
Power-Down Current
Max. Vee,
CE~ Vee - 3.0V,
VIN~ Vee - O.3Vor
VIN S 0.3V, f = 0
IsB
Curren~4]
0.4
V
- 300
-300
-300
rnA
Vee = Max., lOUT = 0 rnA Com'l
f = fMAX = litRe
Mil
140
130
125
rnA
130
125
Com'l
30
30
30
Mil
40
40
lest Conditions
Max.
Units
10
pF
10
pF
rnA
Shaded area contains advanced information.
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
TA=2soC,f=1MHz,
Vee = 5.0V
Notes:
1. VIL (Mjn)= - 2.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect
these parameters.
2-412
.::ss:-:;z
PRELIMINARY
~~CYPRESS
~F
CY7B197
SEMICONDUCTOR
AC Test Loads and Waveforms
R148Hl
s v < > - - - - -......
R148Hl
SV < > - - - - '__,
---+
FI
20 P
OUTPUTo---....
5PFI
R2
255n
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
R2
255.(1
8197-6
(b)
(a)
Equivalent to:
ALL INPUT PULSES
---+
OUTPUT<>---....
8197-5
THEVENIN EQUIVALENT
167.(1
OUTPUT 00---".""."'---00 1.73V
Switching Characteristics
Over the Operating RangeI3,6]
18197-12
18197-10
Parameters
Description
Min.
Max.
Min.
Max.
18197-15
Min.
Max.
7BI97-20
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from AddressChange
tACE
CE WW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
tpo
CE HIGH to Power-Down
15
12
10
12
10
3
3
3
12
10
3
3
0
ns
ns
20
15
ns
ns
10
8
ns
ns
20
3
0
12
10
3
3
0
20
15
7
5
0
ns
20
15
ns
WRITECYCLEl~j
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
15
ns
tAW
Address Set-Up to Write End
8
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
8
9
10
15
ns
tso
Data Set-Up to Write End
6
7
8
10
ns
tHO
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
2
2
2
2
tHzWE
WELOWtoHighZ[7,8j
7
5
7
ns
10
ns
Shaded area contains advanced information.
Note.:
6.
7.
8.
Thst conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputIoading
of the specified IorflOH and 20 pF load capacitance.
At any given temperature and voltage condition, tHZCE is less than
tIZCE and tHZWE is less than tlZWE for any given device.
tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) in AC Thst Loads and Waveforms. Transition is measured
±500 m V from steady state voltage.
9.
2-413
TheinternaI write time of the memory is defined by the overlap ofCE
LOW and WE LOW. Both signals must be LOW to initiate awriteand
either signal will terminate a write by goingillGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
.7,~ucroR
PRELIMINARY
CY7B197
Switching Wavefonns
Read Cycle No. 1[10, 11]
tAC
)~
ADDRESS
)(
lAA
I---toHA-4
DATA OUT
PREVIOUS DATA VAUD
*XX) E
DATA VALID
6197-7
Read Cycle No. 2[10, 12]
ADDRESS
CE
=><
---....
x
lAC
/~
~
lACE
I--
I---It..zCE
DATA OUT
HIGH IMPEDANCE
I---Ipu
=f
VCC _ _ _ _ _ _
SUPPLY
CURRENT
////
.'\.'\.'\.
IHZCE -
"-
DATAVAUD
~Ipo
HIGH
IMPEDANCE
~ CC
I
50%
50%
-
ISS
6197-8
Write Cycle No.1 (CE Controlled)[13]
~------------------------Iwc ----------------------~~
ADDRESS
------....>------------
DATAIN
-------->R
lseE
-----------1
Iso - - - - -........
DATA VAUD
tHO
W______
1"
DATA OUT ______~H~I~G~H~IM~P~E~D~AN~C~E_____________________________________________________
6197-9
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = Vn,.
12. Address Valid prior to or coincident with CE transition LOW.
13. IfCEgoesHlGH simultaneouslywith WEHlGH, the output remains
in a high-impedance state.
2-414
4:~
•
,
PRELIMINARY
·iI CYPRESS
CY7B197
SEMlCONDUCIDR
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled)[13]
twe
ADDRESS
~ K"
~
)(
.$ffi W///&
~"
tAW
ItiA-
!sA
\pwe
.i~
~~
Iso
)1{"
DATA IN
tHO -
)(
DATAVAUD
-
tHZWE
j
~ILZWE-j
HIGH IMPEDANCE
DATA OUT ________________D_A_TA
__
U_N_DE_F_IN_E_D______________J»----------------«~
_________
8197-10
7B197 Truth Table
CE
WE
H
X
HighZ
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
Write
Active (Icc)
Mode
Power
Deselect/Fbwer-Down
Standby (ISB)
DOUT
Ordering Information
Speed
(ns)
10
12
Package
Ordering Code
Operating
Range
Speed
type
Commercial
15
(ns)
Ordering Code
Package
type
Operating
Range
Commercial
CY7B197-10DC
D14
CY7B197-15DC
D14
CY7B197-10LC
THD
CY7B197-15LC
THD
CY7B197-10PC
P13
CY7B197 -15PC
P13
CY7B197-10VC
V21
CY7B197-12DC
D14
CY7B197 -12LC
THD
CY7B197-12PC
P13
CY7B197-12VC
V21
CY7B197-12DMB
1)14
CY7B197-12LMB
THD
Commercial
20
Military
Shaded area contains advanced information.
2-415
CY7B197-15VC
V21
CY7B197-15DMB
D14
CY7B197-15LMB
THD
CY7B197-20DMB
D14
CY7B197-20LMB
THD
Military
Military
~
~-CYPRESS
"ffi!!!!!!IiIT'
PRELIMINARY
SEMICONDUCIDR
NnLITARYSPECllITCATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IJX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHO
7, 8, 9, 10, 11
Document #: 38-00159-B
2-416
CY7B197
CY7C197
CYPRESS
SEMICONDUCTOR
256K X 1 Static R/W RAM
Features
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• Highspeed
- 20ns
• Low active power
- 880mW
• Low standby power
- 220mW
• TI'L-compatible imputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C197 is a high-performance
CMOS static RAM organized as 256K
words by 1 bit. Easy memory expansion is
l'rovided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C197 has an automatic power-down
feature, reducing the power consumption
by 75% when deselected.
Writing to the device is accomplished when
~chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (Au
throughA17)'
Logic Block Diagram
Readingthedevice is accomplished by taking
c!!!E. enable (CE) LOW while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear on
the data output (DOUT) pin.
The output pin stays in high-impedance state
when£!!!p enable (CE) is HIGH or write enable (WE) is LOW.
The 7C197 utilizes a die coat to insure alpha
immunity.
Pin Configurations
DI
LCC
DIP/sOJ
ThpView
A,
As
As
A4
Ae
Ae
A7
As
DO
ThpVlew
"t-
Vee
~<~::9<
A'7
A'B
A,.
A,.
A'3
A12
Al1
A,a
32 11:2827
26
4
25
5
24
B
7
23
8 7C197 22
21
9
20
10
11
19
12
18
1314151617
NC
~
Ae
Ae
A7
Ae
Dour
As
Dour
WE
GND
NC
D,N
CE
NC
A'B
A,.
A,.
A'3
A,.
Al1
A10
NC
I~~I~~~
C197-3
C197-2
'-t-+--WE
C197-1
Selection Guide
MaximumAccess Time (ns)
MaximumOperating
Current (rnA)
I
I
Commercial
7CI97-12
7C197-15
7CI97-20
7C197-2S
7C197-3S
12
15
20
25
35
45
160
150
140
100
100
100
160
150
110
110
110
40
40
35
35
35
Military
Maximum Standby Current (rnA)
40
Shaded area contains advanced information.
2-417
7CI97-45
~PPiss
~rs~CONDUCrOR
CY7C197
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 6S0Cto +1S0°C
Ambient Thmperaturewith
PowerApplied ....................... - SSOCto +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . - O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DClnputVoltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001V
(per MIL-STD-883, Method 301S)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature[l]
Vee
O°Cto +70°C
SV± 10%
- 5SoC to +125°C
SV± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operating Rangel2]
7C197-12
Parameters
Description
Thst Conditions
Min.
= Min.,IOH = - 4.0mA
Vee = Min. llOL = 12.0 rnA I Com'l
llOL = 8.0 rnA l Mil
2.4
VOH
Output HIGH Voltage
VOL
Output WW Voltage
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
Vee
Max.
7C197-15
Min.
Max.
Units
0.4
V
0.4
V
V
2.4
2.2
V
-0.5
Vee
0.8
-3.0
Vee
0.8
V
IJX
Input Load Current
GND.sVI.sVee
-10
+10
-10
+10
loz
Output LeakageCurrent
GND .s Vo.s Vec, Output Disabled
-10
-10
+10
!-IA
!-IA
los
Output Short
CircuitCurrent[3]
Vee = Max., VOUT = GND
+10
-3S0
-3S0
rnA
lee
Vee Operating
Supply Current
Vee = Max., lOUT = 0 rnA,
f = fMAX = litRe
ISO
rnA
ISB!
AutomaticCE Power-Down
Current-TILInputs[4]
IsB2
AutomaticCE Power-Down
Current-CMOSInputs[4]
Max. Vee, CE~ VIH, VIN ~ VIH or
VIN.s VIL f = fMAX
Max. Vee, CE ~ Vee - 0.3Y,
VIN > Vee - O.3VorVIN < 0.3V
ICom'l
IMil
160
160
40
40
rnA
20
20
rnA
Shaded area contams advanced information.
Notes:
1. TAis the "instant on" case temperature.
2. See the last page of this specification for Groop A subgroup testing information.
3. Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
4.
2-418
A pull-up resistor to V cc on the CE input is required to keep the device deselected during Vccpower-up, otherwise ISB will exceed values
given.
.}l~NDUCfOR
CY7C197
Electrical Characteristics Overthe Operating Rangel2] (continued)
7Cl97-20
Parameters
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 mA
VOL
Output LOW Voltage
Vee = Min. IOL = 8.0mA
VIH
Input HIGH Voltage
2.2
VIL
Input WW Voltage
-0.5
IJX
Input Load Current
GND.$. VI.$. Vee
-10
loz
Output Leakage Current
GND.$. VO.$. Vee, Output Disabled
-10
los
Output Short
CircuitCurrent[3]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max., lOUT = 0 rnA,
f = fMAX = litRe
IsB!
AutomaticCE PowerDown
Current-TILlnputs[4]
IsB2
AutomaticCE Power-Down
Current-CMOSlnputs(4)
Max.
7C197 -20,25,35,45
Min.
2.4
I
I Mil
I IOL = 12.0 mA I Com'l
Max.
Units
0.4
V
2.4
0.4
0.4
V
0.4
V
Vee
0.8
V
+10
+10
!JA
!JA
-350
-350
mA
140
100
mA
150
110
Max. Vee,CE~ VIH, VIN~ VIHor
VIN.$. VIL, f = fMAX
40
35
mA
Max. Vee, CE~ Vee - 0.3v,
VIN> Vee - O.3Vor VIN < O.3V
20
20
mA
I Com'l
IMil
Vee
0.8
+10
+10
2.2
-3.0
-10
-10
V
Shaded area contains advanced mfonnation.
Capacitance [5]
Max.
Units
CIN
Parameters
InputCapacitance
Description
TA = 25°C,f= 1 MHz,
10
pF
CoUT
Output Capacitance
Vee=5.0V
10
pF
Thst Conditions
Notes:
5.
Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
A1329.(1
(480.(1 MIl.)
A1329.(1
(480.(1 MIl.)
5V
5V
DUTPUTo---1~-"
30PFI
INCLUDING
JIGAND _
A2
202.(1
(255.(1MIL)
SCOPE -
5PFI
INCWDING
JIGAND _
A2
255.(1
(255.(1MIL)
SCOPE -
(b)
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTO---~--+
C197-5
C197-4
THEVENIN EQUIVALENT
125.(1
OUTPUT 0 0 - - _ " " , , _ - - 0 0 1.9OV
167.(1
OUTPUT 00_ _ _
'<1'''',;'_ _-00 1.73V
Commercial
Military
2-419
foF;~NDlnOR
CY7C197
Switching Characteristics Over the Operating Rangel2,6]
Description
Parameters
7C197-12
7Cm-IS
Min. Max.
Min. Max.. Min. Max.
7Cl97-20
7Cl97-2S
7CI97-3S
Min.
Min.
Max.
Max.
7CI97-4S
Min.
Max. Units
READ CYCLE
tRe
Read Cycle Time
tAA
Address to
Data Valid
tOHA
Output Hold from
AddressChange
tACE
CE LOW to
Data Valid
tLZCE
CELOWto
LowZ[7]
tHZCE
CE HIGH to
HighZ[7,8]
tpu
CE LOW to
Power-Up
tpo
CEHIGHto
Power-Down
12
20
15
12
15
20
3
3
3
3
15
12
0
0
0
0
12
0
0
3
15
20
0
ns
ns
20
0
ns
ns
30
25
ns
ns
45
35
0
0
20
15
3
3
13
ns
45
35
25
3
10
45
3
3
3
8
35
25
20
3
7
25
ns
WRITECYCLELYJ
twc
Write Cycle Time
12
15
20
25
35
45
ns
tSCE
CELOWto.
Write End
9
10
15
20
30
40
ns
tAW
Address Set-Up to
Write End
9
10
15
20
30
40
ns
tHA
Address Hold from
Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tpWE
WE Pulse Width
9
10
15
20
25
30
ns
tso
Data Set-Up to
Write End
7
8
10
15
17
20
ns
tHO
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
LowZ[7]
2
2
3
3
3
3
ns
tHzWE
WE WW to
HighZ[7,8]
7
0
7
10
0
13
0
15
0
20
ns
Shaded area contams advanced informallon.
Note.:
6.
7.
8.
Thst conditions assume signal transition timeof5 nsor less, timing reference levels of 1.5V; input pulse levels of 0 to 3.0V; and output loading
of the specified IOrfIOH and 30 pF load capacitance.
At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than IrzwE for any given device.
tHZCE and tHzWE are specified with CL = 5 pF as in part (b) in AC
Thst Loads and Waveforms. 'fransition is measured ± 500 m V from
steady state voltage.
9.
2-420
The internal write time ofthe memory is defmed by the overlap of CE
WW and WEWW: Both signals must he LOWtoinitiate awrite and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
~
:~
CY7C197
--=--,
' ; " CYPRESS
SEMICawer-Down
2-423
-
800 1000
CAPACITANCE (pF)
Mode
H
1.00
N
Vcc=4.5V
TA = 25°C
/
SUPPLY VOLTAGE (V)
7C197 Truth Table
CE WE Inputs/Outputs
~
fa
/
w
1.0
NORMALIZED Icc vs. CYCLE TIME
1.25,....------.-----,r-----,
~ 0.751----+-----::.,;L.....,~---i
20
30
CYCLE FREQUENCY (MHz)
40
~
~-CYPRESS
CY7C197
~_., SEMlCONDUCfOR
Ordering Information
Speed
(os)
12
15
CY7CI97-12DC
Package
1YPe
D14
CY7C197-12LC
LS4
Ordering Code
CY7CI97-12PC
P13
CY7Cl97 -12VC
V13
CY7C197:"'15DC
D14
CY7CI97-15LC
CY7C197 -15PC
20
25
CY7C197 -15DMB
D14
CY7C197 -15KMB
K73
CY7C197-15LMB
LS4
P13
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
..
Commercial
Military
Commercial
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
los
1,2,3
Icc
1,2,3
ISB!
1,2,3
ISB2
1,2,3
CY7C197 - 20VC
V13
CY7C197-2ODMB
D14
CY7C197-2OKMB
K73
Parameters
CY7C197-2OLMB
LS4
READ CYCLE
CY7C197 25DC
D14
1,2,3
Switching Characteristics
Military
Commercial
Subgroups
tRC
7,8,9, 10, 11
7,8,9, 10, 11
CY7CI97-25LC
LS4
tAA
CY7CI97-25PC
P13
taRA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
CY7CI97-25VC
V13
CY7C197-25DMB
014
CY7C197-25KMB
K73
twc
7,8,9, 10, 11
LS4
tSCE
7,8,9, 10, 11
014
tAW
7,8,9,10,11
7,8,9,10,11
CY7C197-35DC
WRITE CYCLE
Military
Commercial
CY7C197-35LC
LS4
tRA
CY7C197-35PC
P13
tSA
7,8,9,10,11
tpWE
7,8,9,10,11
tso
7,8,9, 10, 11
tHo
7,8,9, 10, 11
CY7C197-35VC
V13
CY7C197-35DMB
D14
CY7C197-35KMB
45
DC Characteristics
P13
V13
CY7C197-25LMB
35
Commercial
LS4
CY7C197-15VC
CY7C197-2OPC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Operatiog
Range
Military
K73
CY7C197-35LMB
LS4
CY7C197-45DC
014
CY7C197-45LC
LS4
CY7C197-45PC
P13
CY7CI97-45VC
V13
CY7C197-45DMB
D14
CY7C197-45KMB
K73
CY7CI97-45LMB
LS4
Commercial
Document #: 38-00078-1
Military
Shaded area contams advanced information.
2-424
CY7C198
CY7C199
CYPRESS
SEMICONDUcrOR
32,768 X 8 Static R!W RAM
Features
Functional Description
• Automatic powt!r-ciown when
deselected
• CMOS for optimum speed/power
• High speed
- 25ns
• Low active power
- 880mW
• Low standby power
- 220mW
• TTL-compatible Inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C198 and CY7Cl99 are highperformance CMOS static RAMs organized as 32,768 words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable (rn) and active
LOW output enable (OE) and three-state
drivers. Both devices have an automatic
power-down feature, reducing the power
consumption by 75% when deselected.
The CY7Cl99 is in the space-saving
3OO-mil-wide DIP package and leadless
chip carrier. The CY7C198 is in the standard 6OO-mil-wide package.
An active LOW write enable signal (WE)
controls the writing/readi~ration of
the memory. Whenl::B and WE inputs are
both LOW, data on the eight data input/
output pins (1100 through 1107) is written
into the memory location addressed by the
address present on the address pins (Ao
through A14). Reading the device is accomplished by selectinLthe device and enactive
abling the outJl11ts, CE and
LOW, while WI! remains inactive or
mGlL Under these conditions, the contents of the location addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a highimpedance state unless the chip is selected, outputs are enabled, and write enable (WE) is mGH. A die coat is used to
ensure alpha immunity.
un
Pin Configurations
Logic Block Diagram
DIP/SOl
'lbpVlew
As
As
A,
IlOo
110,
As
As
A,.
A"
1
Vee
WE
'"Ao
As
A,
AI
10
NC
11
12
Aa
110.
UE
Aa
IlOo
CE
!lOa
va.
00.
!lOa
00.
Ao 5
~ 8
Ao 7
Ao :
I/Or
LIOe
va.
Ct88-2
1/00
00,.
UE - -.......J
o
Nt')
...
-< -< -<-<-<
CI98-4
CI911-1
Selection Guide
2-425
•
CY7C198
CY7C199
~
~PRFSS
~;.. SEMICONDUCTOR
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature .................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied .. . . . .. .. . .. . . . . . .. . . ... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) . . . . .. .. .. .. .. . . . . . . . . . . - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to + 7.0V
DC Input Voltage ....................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ................ 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
- 55°Cto +125°C
5V± 10%
Range
Commercial
Militaryll]
Electrical Characteristics Over the Operating Rangd2]
7C198-12
7Cl99-U
Parameters
Description
7Cl98-lS
7Cl99-lS
7C198-20
7C199-20
Min. Max. Min. Max. Min. Max. Units
Thst Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VlL
Input LOW Voltage
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
Vee = Min., IOH = - 4.0 rnA
2.4
0.4
0.4
Vee = Min., IOL = 8.0 rnA
2.4
2.4
V
0.4
V
IIX
Input Load Current
GND.s. VI.s. Vee
-10
+10
~10
+10
-10
+10
loz
los
Output Leakage Current
GND .s. VI.s. Vee, Output Disabled
-10.
+10
-.10
+10
-10
+10
JlA
JlA
Output Short Circuit
Currentl3]
Vee = Max., VOUT = GND
-300
rnA
Vee Operating Supply
Current
Vee = Max., lOUT = 0 rnA,
f = fMAX = litRe
rnA
ISBI
AutomaticCE
Power-DownCurrentTILlnputs
Max. Vee, CE 2 Vrn, VIN 2 Vrn
or VIN.s. VIL f = fMAX
ISB2
Automatic CE
Power-DownCurrentCMOS Inputs
Max. Vee, CE2 Vee - O.3V
VIN 2 Vee - O.3VorVIN .s.0.3v,
f=O
Icc
-300
ICom'l
IMil
160
-300
160
160
180
180
40
40
40
rnA
20
20
20
rnA
Shaded area contams advanced information.
Notes:
1.
2.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be shorted atone time. Duration of
the short circuit should not exceed 30 seconds.
2-426
CY7C198
CY7C199
~
.=aa....-~
~=CYPRESS
~, SEMlCONDUcroR
Electrical Characteristics
Over the Operating Rangel2] (continued)
7Cl98-25
7Cl99-25
Description
Parameters
lest Conditions
Min.
7C198-35, 45, 55
7Cl99-35, 45, 55
Max.
Min.
2.4
Max.
Units
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Vrn
Input HIGH Voltage
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltage
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GNDS VIS Vee
-10
+10
-10
+10
-10
+10
-10
+10
t-tA
t-tA
-300
rnA
160
150
rnA
160
160
0.4
0.4
V
II)
V
:iii
J
twc
Write Cycle Time
25
35
45
50
ns
tSCE
CE LOW to Write End
20
30
40
50
ns
tAW
Address Set-Up to Write End
20
30
40
50
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
20
25
30
40
ns
tSD
Data Set·Up to Write End
15
17
20
25
ns
tHD
Data Hold from Write End
0
0
0
0
tHZWE
WE LOW to High Z[6]
tLZWE
WE HIGH to Low Z[7]
13
3
15
3
20
3
ns
25
3
ns
ns
Switching Wavefonns
Read Cycle No.l[lO, 11]
ADDRESS
~
--~
DATA OUT
PREVIOUS DATA
IRe
1M
v:~ JXX
Notes:
10. Device is continuously selected. ClE, CE = VJL.
1
*===============D=A=t=A=V=A=U=D============
C1S8-7
11. wl, is HIGH for read cycle.
2-429
*-
CY7C198
CY7C199
.r,~NDUcroR
Switching Waveforms (continued)
Read Cycle No. 2[11, 12J
CE:
lAC
~,
~~
lACE
~~
DATA OUT
IL2CE
Vee
~~
100E
~tL20EHIGH IMPEDANCE
////
DATA VALID
."- "-"-
-~
IHZCE
HIGH
IMPEDAN CE
/
-tpD
_Ipu
~ CC
I
SUPPLY
CURRENT
50%
ISB
Cl98·8
Write Cycle No.1 (WE Controlled)[8, 13, 14J
~-----------------------IWC----------------------~
ADDRESS
WE----~------~----~~~,
1+----- IPWE --------.j ,------------------
J - - - - - IsD
DATAI/O
-----"'*0---..1 4m
DATA-IN VALID
Cl98-9
Write Cycle No.2 (CE Controlled)[8, 13, 14J
~------------- IwC
--------------.j
ADDRESS
CE
----1-----------------------_. J - - - IsCE
-----t~
.,-----1------
1+----------- ~w ----------~----
1-:>----...
IsD
---------------(K......---D-A-T-A--IN-V-'A-L-ID--~-------<......
DATA I/O
Cl98·10
Note.:
12. Address valid prior to or coincident with CE transition Ww.
13. Data I/O is high impedance if OE ~ Vrn.
14. IfCEgoes HIGHsimultaneous!ywith WE HIGH, the output remains
in a high-impedance state.
2-430
CY7C198
CY7C199
-~
-
-
·~PF/E..SS
F
SEMICONDUcroR
Switching Waveforms (continued)
•
Write Cycle No.3 (WE Controlled, OE WW)[9, 14]
Iso
DATA-IN VALID
lYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
VS. SUPPLY VOLTAGE
1.4
3l 1.2
Icc
jl1.0
V
0
w 0.6
N
«
::;:
V
0.6
0
0.4
::J
z
0.2
V
~
-
4.5
5.0
1.2
I..........
5.5
0.6
J
1.3
J.1.4
0
1.2
0
1.1
~
::;;
~
ISB
25
125
AMBIENT TEMPERATURE (OC)
o~
w
20
0
0.0
1.0
2.0
II:
1.0
............
--
TA = 25°C
1'-.....
0.9
0.6
4.0
4.5
5.0
II:
0
r--
5.5
SUPPLY VOLTAGE M
6.0
z
1.0
« 140
~
0.6
0.6
-55
~
Vcc= 5.0V
!zw
100
a
60
~
60
iii
~
~
o
25
125
2-431
3.0
4.0
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
~ 40
AMBIENT TEMPERATURE (OC)
""
OUTPUT VOLTAGE M
~
1.2
Vcc= 5.0V
TA = 25°C
~
.§. 120
N
z
~
~ 40
NO~EDACCESS TllWE
vs. AMBIENT TEMPERATURE
1.6
60
w
~ 60
::l
0.0
-55
6.0
NO~ZEDACCESSTllWE
0
-............
Vcc= 5.0V VIN= 5.0V
0.2
VS. SUPPLY VOLTAGE
w
a~
~
~ 0.4
1.4
«
::;;
"'"
!zw 100
II:
SUPPLY VOLTAGE M
::J
l120
Icc
"" 0.6
I
ISB
0.0
4.0
~
jl1.0
VIN= 5.0V
TA = 25°C
II:
1.4
V
OUTPUT SOURCE CURRENT
vS.OUTPUTVOLTAGE
/
oV
v
/
1/
Vcc= 5.0V
TA = 25°C
/
I
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE M
4.0
CY7C198
CY7C199
~~
. , ~amucroR
'JYpicai DC and AC Characteristics (continued)
TYPICALPOWER·ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTLOADING
3.0
0
~
~
2.5
.5.
cw 2.0
N
~
:;
NORMALIZED Icc vs. CYCLE TIME
1.25,...----.----.,----,
30.0
1.5
a:
..,--
25.0
~
20.0
!:i
15.0
/
/
w
0
z 1.0
0.5
0.0
0.0
1.0
--
2.0
,/
3.0
./
4.0
5.0
c 10.0
5.0
V
/
N
Vcx;=4.5V TA = 25°C
1/
200 400
600 800 1000
CAPACITANCE (pF)
SUPPLY VOLTAGE M
Truth Table
CE
WE
OE
H
X
X
HighZ
Deselect/RJwer·Down
L
H
L
Data Out
Read
Active (IcC>
L
L
X
Data In
Write
Active (IcC>
L
H
H
HighZ
Deselect, Output Disabled
Active (IcC>
Inputs/Outputs
8
fil1.00
Mode
Power
Standby (lSB)
2-432
~
~ 0.751---+--.".""'--+----1
20
30
CYCLE FREQUENCY (MHz)
40
CY7C198
CY7C199
~-;:;z
-.
9III!iiiiiI
~,
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
12
15
20
25
35
45
55
Ordering Code
Package
'JYpe
Operating
Range
Speed
(ns)
D16
L55
P15
D16
L55
P15
D16
L55
D16
L55
P15
D16
L55
D16
L55
P15
D16
L55
P15
D16
L55
D16
L55
P15
DI6
L55
D16
L55
PI5
DI6
L55
Commercial
12
CY7CI98-12DC
CY7C198-12LC
CY7CI98-12PC
CY7C198-15DC
CY7CI98-15LC
CY7CI98-15PC
CY7CI98-15DMB
CY7CI98-15LMB
CY7C198-20DC
CY7C198-20LC
CY7C198-20PC
CY7CI98-20DMB
CY7CI98-2OLMB
CY7CI98-25DC
CY7CI98-25LC
CY7CI98-25PC
CY7C198-35DC
CY7C198-35LC
CY7C198-35PC
CY7C198-35DMB
CY7CI98-35LMB
CY7C198-45DC
CY7C198-45LC
CY7C198-45PC
CY7C198-45DMB
CY7C198-45LMB
CY7CI98-55DC
CY7C198-55LC
CY7C198-55PC
CY7C198-55DMB
CY7C198-55LMB
Commercial
15
Military
Commercial
Military
20
Commercial
Commercial
25
Military
Commercial
25
Military
35
Commercial
Military
Shaded area contains advanced information.
45
55
Ordering Code
Package
lYPe
Operating
Range
D22
L54
P21
V2I
D22
L54
P21
V21
D22
K74
L54
D22
L54
P21
V21
D22
K74
L54
D22
L54
P21
V21
D22
K74
L54
D22
L54
P21
V21
D22
K74
L54
D22
L54
P21
V21
D22
K74
L54
022
L54
P21
V21
D22
K74
L54
Commercial
CY7C199-I2DC
CY7C199-12LC
CY7CI99-12PC
CY7CI99-I2VC
CY7C199-I5DC
CY7C199-I5LC
CY7CI99-15PC
CY7CI99-15VC
CY7C199-15DMB
CY7CI99-15KMB
CY7C199-15LMB
CY7C199-2ODC
CY7C199-20LC
CY7C199-2OPC
CY7C199-2OVC
CY7C199-2ODMB
CY7CI99-2OKMB
CY7C199-2OLMB
CY7CI99-25DC
CY7CI99-25LC
CY7CI99-25PC
CY7C199-25VC
CY7C199-25DMB
CY7C199-25KMB
CY7C199-25L54
CY7C199-35DC
CY7C199-35LC
CY7C199-35PC
CY7C199-35VC
CY7C199-35DMB
CY7C199-35KMB
CY7C199-35LMB
CY7C199-45DC
CY7C199-45LC
CY7C199-45PC
CY7C199-45VC
CY7CI99-45DMB
CY7C199-45KMB
CY7C199-45LMB
CY7C199-55DC
CY7C199-55LC
CY7C199-55PC
CY7C199-55VC
CY7C199-55DMB
CY7C199-55KMB
CY7C199-55LMB
Shaded arca contains advanced information.
2-433
Commercial
Military
Commercial
Military
C..ommercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
•
CY7C198
CY7C199
MlUTARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameters
Subgroups
READ CYCLE
tRC
7,8,9,10,11
tAA
7, 8, 9, 10, 11
tolIA
7,8,9,10, 11
tACE
7,8,9, 10, 11
IOOE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8,9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7,8,9, 10, 11
tlIA
7, 8, 9, 10, 11
tSA
7,8,9, 10, 11
tPWE
7,8,9,10,11
tso
7,8,9,10,11
tHO
7,8,9,10, 11
Document#: 38-00077-1
2-434
CY7B199
PRELIMINARY
CYPRESS
SEMICONDUCTOR
32,768 X 8 Static RIW RAM
Features
Functional Description
• Highspeed
- tAA = IOns
• BieMOS Cor optimum speed/power
• Low active power
The and CY1B199 is a high-performance
BiCMOS static RAM organized as 32,768
words by 8 bits. Easy memory expansion is
llrovided by an active LOW chip enable
{rn). an active LOW output enable (OB).
and three-state drivers. The device has an
automatic power-down feature. reducing
the power consumption by more than 60%
when deselected
An active LOW write enable signal (WE)
controls the writing o~ration of the
memory. When
and
inputs are
both LOW, data on the eight data input!
output pins (lIOo through 1/07) is written
into the memory location specified on the
address pins (Au through AI4).
- 93SmW
• Low standby power
-l6SmW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
wn
rn
Logic Block Diagram
Reading the device is accomplished by tak~chip enable ern-! and output enable
(DE) LOW, while Wi! remains inactive or
HIGH. Under these conditions. the contents of the location specified on the address pins is present on the eight data input!
output pins.
The eight input/output pins (1/00 through
1/07) are placed in a high-impedance state
when the device is deselec~ HIGH).
the outputs are disabled
HIGH). or
during a write operation
LOW).
The CY7Bl99 is available in space-saving
300-mil-wide DIPs and SOJs.
Pin Configurations
DIPISOJ
'IbpVlI!W
Ao
Ao
Vee
1
WE
A7
1.0
Ao
Ao
Ao
Ao
1100
IIOt
AtO
An
At.
O'E
At.
eE
At
Ao
At.
va,
1/00
I'Oe
I'Oe
IIOt
IlOo
00.
IiOa
GNO
I/O.
110.
110.
'IbpV\ew
At.
Ao
A,
Ao
Ao
110.
1107
AtO
An
At.
Ata
At.
8199-1
8199-2
Lee
110.
1/00
IIOt
I/Os
GNO
28
27
28
25
24
28
1
2
8
4
5
8
~
78199
9
10
11
12
18
14
Vee
WE
1.0
Ao
Ao
At
~
O'E
20
19
18
17
18
15
eE
Ao
va,
I/Os
1/00
00.
1/00
8199-3
Selection Guide
Maximum Operating
CUrrent (rnA)
Maximum Standby
CUrrent (rnA)
Shaded area contains advanced information.
2-435
•
1iJ7~NDU~R
PRELIMINARY
CY7B199
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage on Vee Relative to GND[lJ . - 0.5V to + 7.0V
DC Voltage AP8lied to Outputs
inHighZState J....................... - 0.5Vto +7.0V
DCInputVoltage ...................... - O.5Vto +7.0V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Commercial
Military
Ambient
Thmperature[2J
Vee
O°Cto +70°C
5V± 10%
- 55°C to +125°C
5V± 10%
Electrical Characteristics[3J Over the Operating Range
7815151-10
Parameters
VOH
VOL
VIH
VIL
IJX
loz
los
Description
Thst Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voitagel1J
Input Load Current
Output Leakage
Current
Output Short
CircuitCurrentl4J
Min.
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
~10
GND5VI5 Vee
GND5VI5 Vee,
Output Disabled
Vee = Max., VOUT = GND
ornA,
Vee Operating
Supply Current
Vee - Max., lOUT f = fMAX = litRe
IsB
AutomaticCE
Power-Down Current
- CMOS Inputs
Max. Vee, CE~ Vee - 0.3Y,
VIN ~ Vee - 0.3V or VIN 5 0.3Y,
f=O
Min.
-10
."
Com'l
Units
V
V
V
V
0.4
Vee
0.8
+10
+10 '
2.2
-0.3
-10
-10
..,.30
Com'l
Mil
Max.
2.4
0.4
2.2
-.0.3
Icc
781!1!1-12,15,20
Max.
0
185
.30.
Mil
Vee
0.8
+10
+10
tJA
tJA
-300
rnA
170
170
rnA
30
rnA
40
Shaded area contains advanced information.
Capacitance [5J
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee=5.0V
Note.:
1. VIL (min.) = - 2.0V for pulse durations of less than 20 os.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
Max.
Units
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. Thsted initially and after any design or process changes that may affect
these parameters.
2-436
~
~~
---'= CYPRF.SS
PRELIMINARY
CY7B199
. ' SEMICONDUClDR
AC Test Loads and Waveforms
R1481.o.
---+
OUTPUTO---......
20PFI
INCLUDING
JIGAND _
SCOPE -
OUTPUT
ALL INPUT PULSES
0---",,---+
R2
255.0.
5PFI
3.0V - - - -__=----~
R2
GND
255.0.
en
INCLUDING
JIGAND _
-=
:E
<
x
IRC
~~
~CE
.I'll'
~
IOOE
-
DATAI/O
_tpu
J
SUPPLY _ _ _ _ _ _ _
CURRENT
---
1//
/
~~
tHZCE
DATA VALID
""""
tlZCE
V~
-
tLZOE--
HIGH IMPEDANCE
HIGH
IMPEDANCE
/
_tpo
I
50%
Write Cycle No.1 (CE Controlled)[14, 15]
~------------- twe ------------~
ADDRESS
CE
---t-----------""""" ....- - IsCE -----1,_----+----~--------------~w ------------------~~---
WE
~~~~~~~~------------~------------~--~~~~~~"
Iso ----0014-
141-;----
DATA 1/0
----------------k~----D-A-TA---IN-Il-A-Ll-D---- l I - - - - - - 6199-8
Notes:
11_ Device is continuously selected. OE, CE = VII..
12. WE is IDGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. DataI/OishighimpedanceifOE =VIH.
15. IfCE goes IDGH simultaneous1ywith WEIDGH, the output remains
in a high-impedance state.
2-438
.-
·~PRESS
PRELIMINARY
- . F SEMlCCtIDUCfOR
CY7B199
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE ruGH During Write)[14,15]
~------------twc-----------~
ADDRESS
WE ----~----~~----~~~
1 4 - - - - tPWE - - - - - - . . I
,-----------------
I.;::::::::~~~O~::::::::~::~
DATAI/O
tHO
DATA-IN VAUD
6199-9
Write Cycle No.3 (WE Controlled, OE LOW)[1O,15]
ADDRESS
WE ------------~~~
~----tso
DATA 1/0
DATA-IN VAUD
6199-10
Truth Table
CE
WE
OE
H
X
X
HighZ
L
H
L
L
L
X
L
H
H
Mode
1/00 -1/0 7
Power
Power-Down
Standby (lSB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icc)
HighZ
Selected, Output Disabled
Active (Icc)
2-439
PRELIMINARY
Ordering Information
Speed
(DS)
..
10
Package
lYPe
Ordering Code
,
CY7B199::-" lODC
•. ·P22
CY7B199~ 10Le
TBD
. CY7B199 ..... 10PC
cY7B199,...10VC
12
15
20
Operating
Range
Cmmp.ercial
P21
.
V21
CY7B199-12DC
D22
CY7B199-12LC
TBD
CY7B199-12PC
P21
CY7B199-12VC
V21
cY7B199 ..... 12DMB
D22
cY7B199-12LMB .
TBD
CY7B199-15DC
D22
CY7B199-15LC
TBD
CY7B199-15PC
P21
CY7B199-15VC
V21
CY7B199-15DMB
D22
CY7B199-15LMB
TBD
CY7B199-20DMB
D22
CY7B199-20LMB
TBD
.
..
Commercial
Military
Commercial
Military
Military
Shaded area contains advanced information.
MIUTARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameters
DC Characteristics
Parameters
Subgroups
READ CYCLE
Subgroups
VOH
1,2,3
tRC
7,8,9, 10, 11
VOL
1,2,3
tAA
7,8,9, 10, 11
Vrn
1,2,3
tOHA
7,8,9, 10, 11
VILMax.
1,2,3
tACE
7,8,9, 10, 11
IIX
1,2,3
tDOE
7,8,9, 10, 11
Ioz
1,2,3
Icc
1,2,3
twc
7,8,9, 10, 11
ISBl
1,2,3
tSCE
7,8,9, 10, 11
ISB2
1,2,3
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10, 11
tPWE
7,8,9,10, 11
tSD
7,8,9,10, 11
tHD
7,8,9, 10, 11
WRITE CYCLE
Document #: 38-00160-B
2-440
CY7B199
CY7CIOOl
CY7CI002
ADVANCED INFORMATION
CYPRESS
SEMICONDUCTOR
256K x 4 Static R/W RAM
with Separate I/O
Features
Functional Description
• ffighspeed
- tAA=l5ns
• lhmsparentwrite (7ClOOl)
• CMOS for optimum speed/power
• Low active power
- 800mW
• Low standby power
-250mW
• Low data-retention power
- lOOjJ.Wat2.0V
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
The CY7ClOOl and CY7Cl002 are highperformance CMOS static RAMs organized as 262,144 x 4 bits with separate I/O.
Easy memory expansion is provided by active WW chip enable (CE) and three-state
drivers. They have an automatic powerdown feature, reducing the power consumption by more than 65% when deselected.
Writing to the device is accomplished by
takin~th chip enable (CE) and write enable (WE) inputs LOW. Data on the four
input pins (10 through 13) is written into the
memory location specified on the address
pins (Ao throughA17)'
Readingthe device is accomplished by taking
c.!!!£ enable (CE) LOW while write enable
(WE) remains HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on
the four data output pins (00 through 03).
The data output pins on the CY7ClOOl and
the CY7ClO02 are placed in .a high-impedance state when the device is deselected
(CE HIGH). The CY7ClO02's outputs are
also placed in a higlI-impedance state during
a write operation (CE and WE WW). In a
write operation on the CY7ClO01, the output pins will track the inputs after a specified
delay.
TheCY7ClOOl andCY7Cl002 are available
in standard 3OO-mil-wide DIPs and SOJs.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
NC
A,.
A17
Ao
A,
Ao
A,.
A"
A'2
NC
10
11
A13
A14
00
Ao
Ia
0,
12
02
CE
03
GND '"t..!:~_"':':"'1'" WE
C1001-2
Selection Guide
Maximum Access Time (ns)
Maximum OperatingCurrent
MaximumStandbyCurrent(~)
7ClllOl-l5
7ClOO2-l5
15
145
Commercial
Military
Commercial
Military
45
Document #: 38-00200
2-441
7ClllOl-20
7ClOO2-20
20
145
150
45
50
7ClOOl-l2
7ClOO2-l2
25
145
150
45
50
•
en
~
CEz, and OE options
CY7CI009
Reading from the device is accomplished by
takin~p enable one (CEI) and output enable (DE) LOW while forcing write enable
(WE)andchipenablelwo(~)HIGH.Un
der these conditions, the contents of the
memory location specified by the address
pins will appear on the I/O pins.
The eight input/output pins (1/00 through 1/
~) are placed in a high-inl~ance state
when the device is deselected (CEI HIGH or
CEz LOW), the outputs are disabled (Q.E
HIGH), or during a write operation (CEI
LOW, CE2 HIGH, and WE LOW).
The CY7Cl009 is available in standard
3OO-rnil-wideDIPs and SOJs.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
Vee
A,s
CE2
WE
A,s
A.
As
An
OE
AlO
VOo
GE,
1/0,
VDs
VO,
liDs
110.
V0 2
"1...!.:,-----,c..r liDs
7Cl009-2
VDs
vo.
110s
VDs
Vo,
OE---2
1/04
GND -...._---'r.l/~
11189-1
Selection Guide
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Shaded area contains preliminary information.
2-446
11189-2
1r7t~~
CY7M199
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................. Ambient Temperaturewith
Power Applied ....................... Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
65°Cto +150°C
Output Current into Outputs (LOW) ............... 20rnA
55°Cto +125°C
- O.5V to + 7.0V
Operating Range
Ambient
Thinperature
Range
Commercial
- O.5Vto +7.0V
- 0.5Vto +7.0V
Military
O°Cto +70°C
Vee
5V± 10%
- 55°C to +125°C
5V± 10%
Electrical Characteristics Over the Operating Range
Parameters
VOH
Description
Output HIGH Voltage
7M199
Max.
'lest Conditions
I IoH = -
Vee = Min
4.0 rnA
I IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Min.
2.4
Com'l
Mil
2.4
VOL
Vlli
VIL
Irx
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel1j
Input Load Current
GND2oo1V
(per MIL-Sm-883, Method 3015)
Latch-UpCurrent .................. ;......... >200rnA
Operating Range
- O.5V to +7.0V
Range
Commercial
Military!lJ
- O.5Vto +7.0V
- 3.0V to + 7.0V
Ambient
Thmperature
O°Cto +70°C
Vee
5V± 10%
- 55°C to +125°C
5V± 10%
Electrical Characteristics Overthe Operating Rangel2J
Parameters
Description
Thst Conditions
VOL
Output HIGH Voltage
Output LOW Voltage
VIH
Va
Input HIGH Voltage
Input LOW Voltage
IIX
Input LeakageCurrent
Veo
Input Diode Clamp Voltage
Ioz
los
los
VOH
Vee = Min., IOH = - 5.2 rnA
Vee = Min., IOL = 16.0 rnA
74S189,
27S03,27S07
Min. Max.
2.4
27LS03
Min. Max.
Units
2.4
V
0.45
V
0.45
Vee = Min., IOL = 8.0 rnA
Vee
0.8
2.0
-3.0
Vee
0.8
V
V
V
+10
-10
+10
!lA
GND2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
'Thst Conditions
Vee = Min., IOH = - 5.2 rnA
Vee = Min., IOL = 8.0 rnA
Guaranteed Input LogicalHIGH
Voltage for all Inputs
Guaranteed Input Logical LOW
Voltage for all Inputs
93422
93422A
Min. Max.
204
0045
2.1
Vee = Max., VIN = OAV
Vee = Max., VIN = 4.5V
Vee = Max., VOUT = O.OV
All Inputs - GND
TA = 125°C
Vee = Max.
TA = 75°C
TA=O°C
lCEX
VOUT - 2AV
VOUT - 0.5Y, Vee - Max.
Units
V
V
V
0.8
0.8
V
-300
40
-90
110
-300
40
-90
70
iJA
iJA
110
70
120
80
130
90
See Note 5
50
-50 I
See Note 5
50
-50
TA= -55°C
Input Camp Voltage
Output Leakage Current
VCL
93L422
93L422A
Min. Max.
2.4
0.45
2.1
rnA
rnA
iJA
Capacitance [6]
Parameters
Description
InputCapacitance
UutputC3pacltance
CIN
CoUT
I
I
I
'Thst Conditions
TA = 25°C,f= 1 MHz,
Vee=5.0V
I
I
I
Max.
8
8
I
I
I
Units
pF
pF
Function Table[7]
CSz
L
X
H
H
H
H
CSt
X
H
L
L
L
L
Inputs
WE
X
X
H
H
L
L
Outputs
OE
X
X
H
L
X
X
Do
X
X
X
X
L
H
On
HighZ
HighZ
HighZ
Selected Data
HighZ
HighZ
Mode
Not Selected
Not Selected
Output Disable
Read Data
Write "0"
Write"l"
Notes:
3.
1.
TA is the "instant on" case temperature.
2.
See the last page of this specification for Group A subgroup testing information.
2-457
These are absolnte voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.
I
I
I
(1(93422AJ93L422A
(1(93422/93L422
~
==:::-
.~
~=CYPRFSS
-.::;;e;p F SEMICONDUCTOR
AC Test Loads and Waveforms
vcc~
ALL INPUT PULSES
3.OV - - - --"~~---.....
R2
GND
BOOSl.
OlJTPUTQ---......- -..
3.OV - -.....
R2
GND
12OOSl.
----l\....:.:::::...---J(
422A-4
=
422A-3
(a)
Commercial Switching Characteristics
Over the Operating Rangel8, 9]
93422A
Parameters
Description
Min.
93IA22A
93422
Max. Min. Max. Min.
93IA22
Max. Min.
Max. Units
tpUI(A)[lO]
tpHL(A)
Delay from Address to Output
(Address Access Time)
35
45
45
60
ns
tpZH ~l, CSz)
tPZH (CS1, CSz)
Delay from Chip Select to Active
Output and Correct Data
25
30
30
35
ns
tpZH~)
Delay from Write Enable to Active
Output and Correct Data (Write Recovery)
25
40
40
45
ns
tpZL(WE)
tpZH (QIl)
tpZL(OE)
Delay from Output Enable to Active
Output and Correct Data
25
30
30
35
ns
ts(A)
Set-Up TIlDe Address (Prior to Initiation of Write)
5
5
10
5
ns
th(A)
Hold Time Address (AfterThrminationofWrite)
5
5
5
5
ns
ts(DI)
Set-Up Time Data Input
(Prior to Initiation of Write)
5
5
5
5
ns
th (DI)
Hold Time Data Input
(After Termination of Write )
5
5
5
5
ns
ts (CSh CSz)
Set-Up Time Chip Select
(Prior to Initiation of Write)
5
5
5
5
ns
th (CSh CSz)
Hold Time Chip Select
(After Termination of Write )
5
5
5
5
ns
tpw(WE)
Minimum Write Enable Pulse
Width to Insure Write
20
40
30
45
ns
tPHZ (gl, CSz) Delay from Chip Select to
tpLZ (CS1, CSz) Inactive Output (High Z)
30
40
30
45
ns
tpHZ~)
Delay from Write Enable to
Inactive Output (High Z)
30
40
30
45
ns
tpLZ(WE)
tpHZ(QIl)
tpLZ(OE)
Delay from Output Enable to
Inactive Output (High Z)
30
40
30
45
ns
2-458
CY93422A/93L422A
CY93422/93L422
=-~
_ ' l E CYPRESS
F SEMICONDUCTOR
Military Switching Characteristics Over the Operating Rangel: S, 9]
93422A
Parameters
tpUI(A)[IO]
tpHL(A)
Description
Min.
Delay from Address to Output
(Address Access Time)
93422
93IA22A
Max. Min.
45
Max. Min.
55
93IA22
Max. Min.
60
Max. Units
75
ns
•
I I)
tpZH (gil, CS2) Delay from Chip Select to Active
tpZL (CS1, CSz) Output and Correct Data
35
40
45
45
ns
tpZH~)
40
45
50
50
ns
tPZL(WE)
Delay from Write Enable to Active
Output and Correct Data (Write Recovery)
tpZH (Q!!.)
tpzL(OE)
Delay from Output Enable to Active
Output and Correct Data
35
40
45
45
ns
ts(A)
Set-Up Time Address (Prior to Initiation of Write)
5
10
10
10
ns
theA)
Hold Time Address (After Termination of Write)
5
5
5
10
ns
ts (DI)
Set-Up Time Data Input
(Prior to Initiation of Write )
5
5
5
5
ns
th (DI)
Hold Time Data Input
(After Termination of Write)
5
5
5
5
ns
ts (CSh CS2)
Set-Up Time Chip Select
(Prior to Initiation of Write)
5
5
5
5
ns
th(CSh CS2)
Hold Time Chip Select
(After Termination of Write )
5
5
5
10
ns
tph(WE)
Minimum Write Enable Pulse
Width to Insure Write
35
40
40
45
ns
tpHZ (gil, CSz) Delay from Chip Select to
tpLZ (CS1, CSz) Inactive Output (High Z)
35
40
45
45
ns
tpHZ~)
Delay from Write Enable to
Inactive Output (High Z)
40
40
45
45
ns
tpLZ(WE)
tPHZ (Q!!.)
tpLZ(OE)
Delay from Output Enable to
Inactive Output (High Z)
35
40
45
45
ns
Notes:
4. Not more than one output should be shorted at a time. Duration of the
short circuit should not be more than one second.
S. The CMOS process does not provide a clamp diode. However, the
CY93422 is insensitive to - 3V DC input levels and - SV undershoot
pulses of less than 10 ns (measured at SO% point).
6. Tested initially and after any design or process changes that may affect
these parameters.
7. H = High Voltage Level, L = Low Voltage Level, X = Don't Care.
High Z implies outputs are disabled or off. This condition is dermed as
a high-impedance state for the CY93422.
8. Vee = SV ± 10% and TA = O°C to + 7SoC unless otherwise noted.
tPZH (WE), tpZH (CS!, CS2), and tpZII (OE) are measured with SI
open, CL = IS pF, and with both the input and output timing referenced to l.Sv. tPZL (WE), tPZL (CS!, CSz), and tPZL (DE) are measured with SI closed, CL = IS pF, and with both the input and output
timing referenced to l.Sv. tpHZ (WE). tpHZ (CSI, CSz), and tpHZ
(DE) are measured with SI open, CL < 5 pF, and are measured between the l.SV level on the input to the VOH-=200 m V level on the
output. tpLZ (WE), tpLZ (CSI, CSz), and tpLZ (DE) are measured with
Sl closed and CL < 5 pF, and are measured between the 1.5V level on
the input and the VOL +SOOmVlevel on the output.
10. tpLH(A) and tpHL(A) are tested with S1 closed and CL = 15 pF with
both mput and output timing referenced to l.Sv.
11. Switching delays from the address, output enable, and chip select inputs to the data output. The CY93422 disabled output in the "OFF"
condition is represented by a single cen ter line.
9.
2-459
:!:
for optimum speed!
power
The CY7B201 is a high-performance
I-megabit BiFAMOS PROM organized in
128 Kbytes. It is available in 32-pin,
6oo-milDIP and LCC packages. These devices offer high-density storage combined
with 40-MHz performance. The CY7B201
is available in windowed and opaque packages. Windowed packages allow the device
to be erased with UV light for 100% reprogrammability.
• iligh speed
=
=
•
•
•
•
•
-tAA 25 ns max. (commercial)
- tAA 30 ns max. (military)
Low-power stand-by mode
-1210'mWmax.
-275mWstand-by
Byte-wide memory organization
100% reprogrammable in the windowed package
Capable of withstanding >2001V
static discharge
User-programmable output enable
(OE)
• Available in
-32-pin, 600-mll plastic or hermetic
DIP
- 32-pin hermetic LCC
The CY7B201 is e~ped with a powerdown chip enable (CE) input and an output enable (DE/DE). When CE is deselected the device powers down to a lowpowe; stand-by mode. The DE/DE pin is
polarity programmable and three-st.ates. the
outputs without puttinlL!!!e deVice mto
stand-bL!!lode. While CE offers lower
power, DE/DE provides a more rapid transition to and from tbree-stated outputs.
Logic Block Diagram
The memory cells utilize proven EP~0.M
fioating-gatetechnology and byte-WIde mtelligent programming algorithms. The
EPROM cell requires only 12.SV for the
supervoltage and low programming current allows for gang programming. The
EPROM allows for each memory location
to be tested 100%, because each location is
written to, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for ACperformance to guarantee that the product will meet DC and
ACspecificationlimitsafiercustomerprogramming.
The CY7B201 is read by selecting both the
CE and DE/DE inputs. The contents of
the memory location selected by the addressoninputsA16 - Aowillappearatthe
outputs 07 - 00.
Pin Configurations
DIP
ThpView
00
Vee
A7
A,.
A,.
A,.
A,.
A,.
01
128Kx8
Vpp
PROGRAMMABLE
ARRAY
PGM
NC
As
As
6
As
As
A4
As
ADDRESS
DECODER
POWER DOWN
Al1
OEiOE
A.
0,
A,o
CE
0.
00
Os
0-
o.
GND
0.
MULTiPLEXER
A,
As
00
05
Oe
B201·2
LCe
ThpV\ew
~ ~~8:8~o
-< eC<»
CE - - L - - - - t OUTPUT ENABLE
DECODER
I-------~
OEl----I
OE
~----~
A7
5 43
~
!
A,
As
11
12
Do
13
Aag
As 10
8201·1
~z
2L\3231~c
0
A14
~ ~.
25A11
24 OE/OE
23 ~
22
CE
21
07
141516171B1~
...-NOC'l2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
Vee
O°Cto +70°C
5V±1O%
Industria:P]
- 40°C to +85°<:;
5V±1O%
Militaryl2]
- 55°C to +125°C
5V±1O%
Range
Commercial
Electrical Characteristicsl3, 4]
Parameter
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min.,IOH = -4.0 rnA
VOL
Output LOW Voltage
V cc = Min., IOL = 12.0 rnA
Vrn
Input HIGH Level
Guaranteedlnput Logical HIGH Voltage
for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
CY7B201-2S
CY7B201-30
Min.
Min.
Max.
2.4
Max.
Units
0.45
V
2.4
0.45
2.0
V
2.0
0.8
V
0.8
V
IIX
Input Leakage Current
GNDsVINsVee
-10
+10
-10
+10
loz
Output LeakageCurrent
VOL S VOUT S VOH, Output Disabled
-40
+40
-40
+40
tJA
tJA
los
Output Short Circuit Current
Vee = Max., VOUT = O.OvIS]
-20
-180
-20
-180
rnA
lee
Power Supply Current
Vee = Max., lOUT = 0.0 rnA
220
220
rnA
ISB
Stand-by Current
Vee = Max., CE = Vrn
50
50
rnA
I Commercial
I Military
60
Capacitance 14]
Parameters
CIN
Description
InputCapacitance
Output Capacitance
Thst Conditions
TA = 25°C, f
Vcc= 5.0V
CoUT
Notes:
1. Contact a Cypress representative for industriaJ temperature range
specification.
2.
3.
•
en
:::E
Maximum Ratings
TAis the "instant on" case temperature
See the last page of this specification for group A subgroup testing information.
= 1 MHz,
Max.
10
12
Units
pF
pF
See Introduction to CMOS PROMs in this Data Book for general information on testing.
5. For test purposes, not more than one output at a time should be
shortcd. Short circuit test duration should not exceed 30 seconds.
4.
3-5
oa::
a.
~
~-CYPRFSS
~,
PRELIMINARY
CY7B201
SEMICONDUClDR
AC Test Loads and Waveforms
3=t s:r=i
R1318.o.
OUTP~~
R1318.o.
OUTP:
R2
197.0.
30PF1
~~g~~NG
-=
-=
SCOPE
SPF
~~g~~NG
1
-=
90%
R2
197.0.
GND
-=
SCOPE
(a) Normal Load
ALL INPUT PULSES
3.0V----
8201-4
(b) HighZLoad
8201-5
I
Equivalent to:
THEVENIN EQUIVALENT
121.0.
OUTPUT 0----'IMr--0 1.91V
8201-13
Switching Characteristics Over the Operating Rangel}, 4]
CY78201-25
Parameters
Description
Min.
Max.
CY7B201-30
Max.
Units
tAA
Address to Output Valid
25
Min.
30
ns
tOE
OEIOE Active to Output Valid
15
15
ns
tHZOE
OEIOE Inactive to High Z
15
15
ns
tCE
CE Active to Output Valid
30
35
ns
tHZCE
CE Inactive to High Z
15
15
ns
tpu
CEActive to Power-Up
tpD
CE Inactive to Power-Down
0
0
30
ns
35
ns
Switching Waveform[4]
Icc
tpo
DATAB
8201-7
3-6
PRELIMINARY
Erasure Characteristics
Wavelengths of light less than 4000 AngstrolDS begin to erase the
7B201 in the windowed package. For this reason, an opaque label
should be placed over the window if the EPROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 AngstrolDS for a minimum dose (UY intensity
multiplied by exposure time) or 25 Wsec/crn2• For an ultraviolet
lamp with a 12 mW/cm2 power rating the exposure time would be
approximately 35 minutes. The 7B201 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
CY7B201
EPROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wseclcrn2 is the recommended maximum
dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Description
Ypp
Ipp
Programming Power Supply
Programming Supply Current
Programming Input Yoltage mGH
Programming Input Voltage LOW
YIHP
YILP
a.
MiD.
Max.
Units
12.5
13.0
100
rnA
Vee
0.4
Y
Y
3.0
Y
1lIbie 2. Mode Selection
Pin Function L6J
Mode
CE
'OE
~
Vpp
A14
A6
~
Au
VIL
VIH
X
X
X
X
A14
A14
X
As
A(,
Ao
Ao
X
As
X
An
An
X
X
X
YIHP
YILP
VIHP
VILP
YIL
VIL
YILP
YIHP
YILP
X
X
X
YIH
YIH
VIH
Vpp
Ypp
Ypp
A(,
Output OisableJ7J
Stand-by
Program Array
Program Verify
Program OEJOEHIGH
Program Verify OEJOE
Signature Read (MFG)
Signature Read (DEY)
YIL
YIL
YIH
YILP
YILP
YILP
YILP
YIL
YIL
A(,
As
An
An
Vpp
Ao
Ao
~
00
HighZ
HighZ
0,-00
~
<>7-00
X
X
X
X
Vpp
Vpp
00- YOH
34H
10H
ReadL7J
Notes:
6. X = can be VIL (VILP) or VIH (VIHP).
YIHP
YIH
VIH
A14
A14
X
Ypp
X
X
7.
A(,
AS
YIHP
X
X
X
VIHP
X
X
X
vpp
A"
A,.
A,.
A,
As
As
Ao
As
""A,Ao
00
0,
o.
GND
VIL
VIH
~""B:8h
.:CC»
I'mI
6
X
X
X
LCC
vee
3
At
NO
A,.
A,.
A,
5
An
llEJOE
A,.
4 3 2 L\323130
29
8
~
A,
25
9
24
10
23
11
22
12
21
13
14151617161920
7
Ao
Do
CE
0,
0
28
o&'!cor~~
Os
Os
0.
Os
8201-11
Figure 1. Programming Pinouts
3-7
A,.
26 -'I.
27 As
~
Ao 8
As
As
A,
~
~
UE/OE is assumed to be active LOW (default).
DIP
I I)
:::IE
oa::
1lIbie 1. Programming Electrical Cbaracterlstics
Parameter
•
As
~E
~
0,
8201-9
Data
<>7 -
HighZ
PRELIMINARY
Ordering Information[8]
Package
'JYpe
Operating
Range
CY7B201-25DC
D32
Commercial
CY7B201-25HC
H65
Speed (ns)
25
30
Ordering Code
CY7B201-25PC
P32
CY7B201-25WC
W32
CY7B201-30DC
D32
CY7B201-30HC
H65
CY7B201-30PC
P32
CY7B201-30WC
W32
CY7B201-30DMB
D32
CY7B201-30LMB
CY7B201-30QMB
L65
Q65
CY7B201-30WMB
W32
Commercial
Military
Note.:
B.
Most of the above products are available in indnstrial temperature
range. Contact a Cypressrepresentative for specifications and product
availability.
MILITARYSPECllnCATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IIX
Ioz
Icc
IsB
Switching Characteristics
Parameters
Subgroups
tAA
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
toE
tCE
Document#: 38-00147-B
3-8
CY7B201
CY7B210
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Reprogrammable 64Kx 16
Power-Down PROM
Features
Product Characteristics
• BiFAMOS® for optimum speed!
power
The CY7B21O is a high-performance
1-megabitBiFAMOS PROM organized in
64K words by 16 bits wide. It is available in
40-pin, 600-mil DIP and 44-pin LCCpackages. These devices offerhigh-densitystorage combined with 40-MHz perf0?Rance.
Windowed packages allow the deVIce to be
erased with UV light for 1OO%reprogrammability.
The CY7B21O is e'l!!!Pped with a powerdown chip enable (CE) input and an output enable (DE/DE). When CE is deselected the device powers down to a lowpowe; stand-by mode. The DE/DE pin is
polarity programmable. and thre~-st~tes
the outputs without putt1!!&..the devIce mto
stand-b1..!!1ode. While CE offers lower
power, DE/DE provides amore rapid transition to and from three-stated outputs.
• Highspeed
-tAA 25 ns max. (commercial)
-tAA = 30ns max. (military)
• Low-power stand-by mode
-1320 mW max.
- 275 mW stand-by
• Word-wide memory organization
• 100% reprogrammable in the windowed package
• Capable of withstanding >2001V
static discharge
• User-programmable output enable
(OE)
=
• Available in
- 4O-pin, 6OO-mil plastic or hermetic
DIP
- 44-pin hermetic LCC
Logic Block Diagram
The memory cells utilize proven EPROM
floating-gate technology and word-wide
intelligent programming algorithms. The
EPROM cell requires only 12.5V for the
supervoltage and low programming current allows gang programming. The
EPROM allows each memory location to
be tested 100%, because each location is
written to, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for ACperformance to guarantee that the product will meet DC and
ACspecificationlinIitsaftercustomerpro··
gramming.
The CY7B210 is read by selecting both the
CE and DE/DE inputs. The contents of
the memory location selected by the addresson inputs A15 - Ao will appear at the
outputs 015 - 00.
Pin Configurations
DIP
Vpp
Vee
CE
Ao
A1
A2
A.,
0,.
01
013
PGM
NC
0,.
A,.
A,.
A,a
A'2
A"
A,.
0,2
0"
02
64Kx 16
PROGRAMMABLE
ARRAY
Aa
00
0,.
03
A5
04
As
Og
Og
05
GND
06
As
07
0,
Og
Og
o.
A.
08
Da
~
Og
00
Aa
A2
A,
OEJOE
As
A7
As
ADDRESS
DECODER
POWER DOWN
As
MULTIPLEXER
AlO
A11
A12
A13
A14
A15
As
GND
A7
As
0,
09
010
011
8210-2
Lec
012
~ :! ~w !to
gEl!
0
~ :!
013
OOOIU>Z>~ZC«
01.
6 5 4 3
A,a
A'2
015
CE ---'-----I
OEI
OE
OUTPUT ENABLE 1-_ _ _ _ _ _---'
DECODER
8210-1
010
Og
08
GND
NC
9
10
11
12
13
0,
,.
Og
05
'5
04
16
17
o
A"
A1D
35
34
33
32
As
GND
NC
As
31
29
As
1819 2D 2122 23 24 25 26 27 28
BiFAMOS is a trademark of Cypress Semiconductor.
8210-3
3-9
•
U)
:::E
oa:
a.
.11L~UCTOR
PRELIMINARY
CY7B210
Selection Guide
CY7B210-2S
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
MaximumOperating
Current(mA)
Commercial
25
240
Military
Commercial
50
CY7B210-30
30
240
240
50
Military
60
Maximum Ratings
(Above which the useful life maybe impaired. Foruserguidelines,
nottested. )
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ........................ - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ......................... - O.5Vto +5.5V
DC Input Voltage ....................... - O.5V to + 7.0V
1tansientlnput Voltage. . . . . . . . . . . . . . . . .. - 2.0V for <20 ns
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.00V
UVErasure .............................. 7258Wsec/cm2
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . >2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200mA
Operating Range
Range
Commercial
Ambient
Thmperature
Vee
O°Cto +70°C
5V:t1O%
Industriai!]
- 40°C to +85°C
5V:t1O%
Militaryl2]
- 55°Cto +125°C
5V:tl0%
Electrical Characteristics[3, 4]
CY7B210-2S CY7B210-30
Parameter
Description
Thst Conditions
Min.
= - 4.0 mA ( - 3.0 mil)
Vcc = Min., IOL = 8.0 mA (6.0 mil)
2.4
Input HIGH Level
Guaranteedlnput Logical HIGH Voltagefor
AllInputs
2.0
Input LOW Level
GuaranteedInput Logical LOW Voltage for
All Inputs
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
V1H
VlL
Vcc = Min., IOH
Max.
Min.
Max.
Units
0.4
V
2.4
0.4
V
2.0
0.8
V
0.8
V
IIX
Input LeakageCurrent
GND !>. VIN !>. V cc
-10
+10
-10
+10
Ioz
Output LeakageCurrent
VOL!>. VOUT!>. VOH, Output Disabled
-40
+40
-40
+40
tAA
tAA
los
Icc
Output Short Circuit Current
Vee - Max., VOUT - O.OVLJJ
-20
-180
-20
-180
mA
Power Supply Current
Vee - Max., lOUT - O.OmA Commercial
240
mA
240
mA
50
mA
60
mA
240
Military
isH
Stand-by Supply Current
Vcc- Max.,CE - V1H
Commercial
50
Military
Capacitance [4]
Parameters
CIN
CoUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
10
12
Units
pF
pF
Note.:
1.
2.
3.
Contact a Cypress representative for industrial temperature range
specifications.
TA is the "instant on" case temperature.
See the last page of this specification for group A subgroup testing in·
fonnation.
4.
5.
3-10
See Introduction to CMOS PROMs in this Data Book for general infonnation on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
.z;::------...
---'= CYPRESS
PRELIMINARY
~~
,
CY7B210
SEMIC(:t.IDUCTOR
AC Test Loads and Waveforms [4]
R1480J'1
R1480J'1
ALL INPUT PULSES
OUTP~~ 3=t(641J'1
Mil) R2
OUTP~~ 5f1(641J'1
Mil) R2
255.a
255.a
30 pFI
(34OJ'1
5 pFI
(340J'1
INCLUDING
JIG AND
SCOPE
-
-
Mil)
INCWDING
JIG AND
SCOPE
(a) Nonnal Load
_
-
_
-
3.0V---
90%
GND
Mil)
821().4
B21Q-5
(b) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
l66J'1 (222J'1 Mil)
OUTPUT~ 1.73V
B21G-6
Switching Characteristics Over the Operating Rangef3, 4]
CY7B210-25
CY7B210-30
Max.
Units
tM
Address to Output Valid
25
30
ns
tOE
OEJOE Active to Output Valid
15
20
ns
tHZOE
OE/OE Inactive to High Z
15
20
ns
tCE
CE Active to Output Valid
30
35
ns
tHZCE
CE Inactive to High Z
15
20
ns
tpu
CE Active to Power Up
tpD
CE Inactive to Power Down
Parameters
Description
Min.
Max.
0
Min.
0
30
ns
35
ns
Switching Waveforms[4]
Icc
tpu
tpo
DATAB
8210-7
3-11
•
&
~~PRFSS
~, SEMICONDUCTOR
PRELIMINARY
Erasure Characteristics
CY7B210
lamp during erasure. Permanent damagemayresultifthe EPROM
is exposed to high-intensity UV light for an extended period of
Wavelengths of light less than 4000 Angstroms begin to erase the
7B210 in the windowed package. For this reason, an opaque label
should be placed overthewindow if the EPROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The re.commend«d dose of ultraviolet light for erasure is a wavelengthof2537 Angstroms for a minimum dose (UV intensitymultiplied by exposuretime) or 25Wsec/cm2• For an ultraviolet lamp
with a 12 mW/em2 power rating the exposure time would be approximately35 minutes. The ~210 needs to be within 1 inch of the
time. 7258 Wsec/cm2 is the recommended maximum dosage.
Programming Modes
Programmingsupport is available from Cypress as well as from a
number of third-party software vendors. For detailed programminginformation, including a listing of software packages, please
seethePROMProgramminglnformationlocatedattheendofthis
section. Programming algorithms can be obtained from any Cypressrepresentative.
'llIble I. Programming Electrical Characteristics
CY7B210-25
Parameter
Description
Vpp
ProgrammingPower Supply
Ipp
ProgrammingSupplyCurrent
VIHP
Programming Input Voltage HIGH
VILP
Programming Input Voltage LOW
CY7B210-35
Min.
Max.
Min.
Max.
12.5
13.0
12.5
13.0
V
100
rna
Vee
V
0.4
V
100
3.0
3.0
Vee
0.4
Units
'llIble 2. Mode Selection
Pin FunctionL6J
Mode
ReadL7J
CE
OE
Vpp
PGM
A,
A,
A15
A14
A3
VIL
VIL
VIH
X
~
A7
A15
A14
A3
VIH
X
~
X
X
A7
X
A15
VIH
Vpp
X
A14
X
A3
X
VILP
~
A7
AI5
AI4
A3
~
X
A7
X
A15
X
A14
X
Output DisableL7J
VIL
Stand-by Mode
VIH
VIH
X
ProgramArray
VILP
VIHP
Ao
Ao
Ao
Data
015 - 00
HighZ
X
HighZ
DI5 - Do
A3
Ao
Ao
X
X
Program Verify
VILP
VILP
Vpp
VIHP
Programlnhibit
VILP
VIHP
Vpp
VIHP
Program OE/OE Active HIGH
VILP
VIHP
Vpp
X
HighZ
VIH
X
Vpp
VIHP
X
X
VIHP
VIHP
X
Vpp
VILP
VILP
X
X
Verify OE/OE Active HIGH
X
X
Signature Read (MFG)
VIL
VIL
VIH
X
VPP
X
X
X
X
VIL
00 = VOH
0034H
Signature Read (DEY)
VIL
VIL
VIH
X
VPP
X
X
X
X
VIH
0011H
Notes:
6. X = can be V,L(VIlP)orVrn (VlliP).
7.
3-12
OE is assumed to be active WW (default).
015 - 00
HighZ
:fEiriPRE&S
~.!
PRELIMINARY
CY7B210
SEMICONDUCTOR
LCC,PLCC
DIP
Vpp
CE
0,.
(")..r1O
~~~tl
000
0,.
0,.
11.
o..()
01
()
>z>
()
It) 'It
~~
z«
6 5 4 3 2.1.4443424140
0,.
0,.
0"
0,0
010
0"
00
00
Os
Os
GND
GND
NC
0,
0,
Os
Os
00
0,
o.
O.
39
8
9
10
11
12
13
14
15
16
17
38
37
38
0
A,.
A,.
A"
A,o
35
34
Ag
33
NC
32
31
30
A,
29
GND
Ag
Ag
Ag
181920212223 24 25 26 27 28
Og
o.
CO)
('II
.....
ow 0
0
....
('II
CO)"
ecoc O z « « o (
0,
jg
00
OEiOE
8210-9
Figure 1. Programming Pinouts
Ordering Information[8]
Speed (ns)
25
30
Package
'Jype
Operating
Range
CY7B210-25DC
Di8
Commercial
CY7B21O-2SHC
H67
Ordering Code
MIUTARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
CY7B21O-25PC
P17
VOH
CY7B210-25WC
W18
VOL
CY7B210-30DC
D18
CY7B21O-30HC
H67
CY7B21O-30PC
P18
CY7B210-30WC
W18
CY7B21O-30DMB
D18
CY7B21O-30LMB
L67
CY7B210-30QMB
Q67
CY7B210-30WMB
W18
VIH
Commercial
VIL
IIX
Ioz
Icc
Military
ISB
Switching Characteristics
Notes:
8. Most of the above products are available in industrial tempreature
range. Contact a Cypressrepresentativefor specifications and product
availability.
Parameters
Subgroups
tAA
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
toE
teE
Document#: 38-00146-B
3-13
•
en
~
0
a:
Q.
CY7B211
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• Highspeed
-tSA = 18ns
-teo = Uns
• BIFAMOS(l!l) ror optimum speed!
power
• LowPower
-UI0mWmax.
• Ouwut register ror sync:hronous operatIOn
• User-programmable output enable
(OE)
• User-programmable INIT word ror
state mac:hine applications
• User-programmable Inltiallzation
c:ontroiline (INIT)
• EPROM technology ror 100% reprogrammability
• Capable orwitbstandlng >2001V static: discharge
Reprogrammable
Registered PROM
• Package options
- 4O-pln, 6OQ-mil plastic: or hermetic:
DIP
-44-pln piastic: or hermetic: LCC
Functional Description
The CY7B21lis a high-performance
I-megabit BiFAMOS Registered PROM
organized in 64K words. It is available in
4O-pin, 6OO-miJ DIP and 44-pin LCC
packages. These devices offer high-density
storage combined witb SO-MHz performance. The CY7B211 is available in windowed and opaque packages. Windowed
packages allow the device to be erased
with UV light for 100% reprogrammability.
The CY7B211 is equipped with an output
register for synchronous applications. A
16-bit, user programmable initialization
word is available for state machine applications or to set or reset the outputs. The
polarities of botb the INIT/INIT input
and the Output Enable (DIDOE) control
line are programmable.
Pin Configurations
Logic Block Diagram
,.------.
~
00
A,
0,
Ao
Ao
ARRAY
Ao
A"
A7
A"
A"
A,.
AODRESS
DECODER
PROGRAM·
III-BIT
MABLE
EOOE-
INITIALIZE
TRIGGERED
WORD
REGiSTER
A"
A,.
40
Vee
CLK
39
PIlQ
38
NC
A,.
A,.
A,.
A,.
An
A,.
0,.
0,.
0,.
Do
0,.
o.
0"
0,.
00
Os
GND
07
07
A"
Os
A7
0,
Ao
Ao
0"
00
0,.
A,.
0"
A,.
0,.
~
8211-2
I::
LCC
., ..... !S~ gl!l! ., ..
000 oll;!Il ::dr lU'';
8 5 4 3 2,1144-;424140
39
38
37
0,.
0,.
0"
0,.
00
0"
GND
NC
07
O.
o.
O.
BiFAMOS is a trademark of Cypress Semiconductor.
A,
~
0,.
8211-1
A"
A"
A"
o.
0,.
~K --------------------~
~---------------------------------------..J
OE
A"
GND
o.
o.
o.
o.
00
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
37
38
38
38
33
00
A,.
~
DIP
m/lNlT
00
&4Kx 18
PROGRAMMABLE
A"
The memOty cells utilize proven EPROM
floating-gate technology and word-wide
intelligent programming algorithms. The
EPROM cell requires only 12.5V for the
supervoltage and low programming current allows for gang programming. The
EPROM allows for eac:hmemory loc:ation
to be tested 100%, as each location is
written to, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that the product will meet DC and
AC specification limits after customer
programming.
The CY7B211 is read by selecting the
UIDOE input. On the rising edge of CLK,
the contents of the memory location selected by the address on inputs A 15 - Ao
will appear at the outputs 015 - 00.
When the lmT/INIT T~u+ is selected,
the user programmed
I /'INIT word
will appear on the outputs until the rising
edge of the CLK pulse after INIT/'INIT is
deselected
7
8
9
10
11
12
13
14
15
16
17
0
36
3S
34
33
32
31
30
29
18192021222324252827 28
o.,o"oooi!llcoc.[".['c"
3-14
At3
~.
A"
A,.
A"
GND
NC
A"
A7
A"
Ao
8211-3
"""'"":
~
PRELIMINARY
;~ CYPRESS
~F
CY7B211
SEMICONDUCfOR
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current (rnA)
CY7B211-18
CY7B211-25
18
12
220
25
15
220
220
I Commercial
I
Military
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature .................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ........................ - 55°Cto +l25°C
Supply Voltage to Ground Potential. . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ......................... - O.5Vto +5.5V
DC Input Voltage ....................... - 0.5Vto +7.0V
'Il"ansient Input Voltage. . . . . . . . . . . . . . . . .. - 3.0V for <20 ns
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.00V
UVErasure .............................. 725SWsec/cm2
Static Discharge Voltage. .. . . . .. . . . . . ... . . . . . . . . . >2001V
(per MIL-SID-SS3, Method 3015)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
temperature
Vee
O°Cto +70°C
5V±10%
Range
Commercial
Militaryfl]
- 55°Cto +l25°C
5V±1O%
Industria12]
- 40°C to +85°C
5V±10%
Electrical Characteristics[3, 4]
CY7B211-18
CY7B211-25
Parameters
Description
Min.
test Conditions
VOH
Output HIGH Voltage
Vee = Min.,IOH = - 4.0 rnA (3.0 mil)
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA (6.0 mil)
VIH
Input HIGH Level
GuamateedInputLogicaIIDGHVoltageforAII
Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs
Max.
Units
0.4
V
2.4
V
2.0
V
0.8
V
JlA
JlA
IIX
Input LeakageCurrent
GND.$. VIN.$. Vee
-10
+10
Ioz
Output LeakageCurrent
VOL.$. VOUT.$. VOH,OutputDisabled
-40
+40
los
Output Short Circuit Current
Vee - Max., VOUT - O.OVL'J
-20
-180
rnA
Icc
Power Supply Current
Vee - Max., lOUT - 0.0 rnA
220
rnA
Capacitance£4]
Parameters
CjN
COUT
Notes:
1.
2.
3.
Description
InputCapacitance
Output Capacitance
test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
TA is the "instant on" case temperature.
Contact a Cypress representative for industrial temperature range
specifications.
See the last page of this specification for group A subgroup testing information.
4.
5.
3-15
Max.
10
12
Units
pF
pF
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test dUration should not exceed 30 seconds.
tI)
::E
o
a::
a.
iC!!;l~PRFSS
PRELIMINARY
~; SEMICONDUCIDR
CY7B211
AC Test Loads and Waveforms[4]
R148Qa
R148Qa
All INPUT PULSES
OUTP~~~(641nMiQ R2 OUTP~~~(641nMiI)
2~
30 PF.l
INCLUDING
JIG AND
SCOPE
-
Mil)
R2
25~
(34Qa
-
3.0V---
5 PF.l
INCLUDING
JIG AND
SCOPE
(a) Standard Load
_
-
GND
(34Qa
_
-
Mil)
B211-4
(b) High Z Load
B211..s
I
Equivalent to:
THEVENIN EQUIVALENT
166n (222n Mil)
OUTPUT ~ 1.73V
B211-6
Switching Characteristics Over the Operating Rangel:3, 4]
CY7B211-18
Parameters
Description
Min.
Max.
CY7B211-25
Min.
Max.
Units
tSA
Address Set-Up to Rising Edge ofCLK
18
25
tHA
Address Hold from Rising Edge of CLK
0
0
teo
CLK to Output Valid
12
15
ns
tm
INIT/INIT to Output Valid
22
25
ns
tRI
INIT/lNITRecovery to CLK
12
12
ns
ns
15
ns
15
ns
tpw
INIT/lNITPuise Width
tOE
OE/OE deselected to Output Valid
15
20
ns
tHZOE
OE/OE selected to High Z
15
18
ns
Switching Waveforms[4]
Read Operation
ClK
z
B211-7
3-16
PRELIMINARY
CY7B211
Switching Waveformsl4] (continued)
Initialization Operation
eLK
•
(I)
:::E
oa::
A.
' - - - - - - B21HI
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
7B211 in the windowed package. For this reason, an opaque label
should be placed over the window if the EPROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) or 25 Wsec/cm2• For an ultraviolet
lamp with a 12 mW/cm2 power rating the exposure time would be
approximately 35 minutes. The 7B211 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
EPROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Thble 1. Pmgrammlng Electrical Cbaracterlstics
Parameter
Description
ProgrammingPowerSupp~
Vpp
Ipp
Max.
13.0
3.0
Vex
0.4
Units
V
ma
V
V
100
Programming Supply Current
Programming Input Voltage HIGH
Programming Input Voltage LOW
VIHP
VILP
Min.
12.5
Table 2. Mode Selection
Read
Other
Mode
Readl'J
Output Disablel ' J
Initialize
Program Array
Program Verify
Program Inhibit
Program OE Active HIGH
Verify OE Active HIGH
Program INIT Active HIGH
Verify !NIT Active HIGH
Program INIT Word
Verify INIT Word
Signature Read (MFG)
Signature Read (DEY)
CLK
CLK
OE
OE
VUJVIH
X
X
X
X
X
X
X
X
X
X
X
X
X
VIL
VIH
VIL
VIHP
VILP
VIHP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIL
VIL
Notes.
6. X = can be VIL (VIl.P) or VIH (VIHP).
NA
INIT
PGM
X
X
X
Vpp
VILP
VIHP
VIHP
VILP
X
VILP
X
VILP
X
X
X
VIH
VIH
VlL
Vpp
Vpp
Vpp
Vpp
VIHP
Vpp
VIHP
Vpp
VlL
VIH
VIH
7.
3-17
Pin FunctionlOJ
A3
At
A3
At
A3
Ao
A3
Ao
X
X
X
A3
A9 Ao
A3
A9 Ao
X
X
X
Vpp
X
X
X
X
X
Vpp
X
X
X
X
X
Vpp
X
X
X
X
X
Vpp VILP
X
Vpp VlHP
X
At
At
A9
A9
AI4
AI4
A14
AI4
X
Au
Au
A15
A15
X
A7
A7
A7
A7
X
A14
A14
X
A15
A15
X
VIHP
X
VIHP
X
VlHP
X
VILP
X
X
X
VII..P
X
A7
A7
X
X
Vpp
X
Vpp
X
X
X
X
VIHP
X
X
X
015 - O.
015 - Do
015 - 00
HighZ
INITWord
015- 0 0
015 - 00
HighZ
HighZ
Oo-VOH
HighZ
01 =VOH
015 - Do
015 - 00
0034H
OO12H
OE and INIT are assumed to be active LOW (defaUlt).
PRELIMINARY
LCe
DIP
Vpp
ClK
0,.
0,.
0,.
0,.
0"
0'0
Os
D.
GND
Vee
PGM
A,.
0"
010
A"
A,o
As
09
D.
GND
NC
GND
As
A7
0,
D.
D.
0,
As
As
Ao
As
As
Os
A,
6 5 4 ";';:-;; 44 43 42 41 40
0,.
A,.
A,.
Os
QEJOE
tf) 'lll'fJ)~ Il..
(J~ (,) "'
..
.... T""""-J 11.0 (,)
........
0000>2>
z1500V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to +150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°Cto +l25°C
Supply Voltage to Ground Potential
(Piii 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState .. ,..................... - 0.5Vto +7.0V
DClnputVoltage ...................... - 3.0Vto +7.0V
DC Program Voltage (Pins 7,18,20) ................. 14.0V
Electrical Characteristics
Parameters
Operating Range
Ambient
temperature
Range
Commercial
Industrial l ]
O°Cto +70°C
Vee
5V± 10%
- 40°C to +85°C
5V± 10%
Militaryl2]
- 55°C to +l25°C
5V± 10%
Over the Operating Rangel3, 4]
Description
test Conditions
Min.
Max.
Units
2.4
VOH
Output HIGH Voltage
Vee = Min.,loH = - 4.0 rnA
VIN = Vrn or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = Vrn or VIL
Vrn
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
VIL
Input LOW Level
Guaranteedlnput LogicaILOWVoltagefor All
Inputs
Irx
Input LeakageCurrent
GND 5. VIN 5. Vee
Ven
Input Clamp Diode Voltage
Note 4
loz
Output Leakage Current
GND 5. Vo 5. Vee Output Disabled[5]
-40
+40
!lA
los
Output Short Circuit Current
Vee = Max., VOUT = 0.OV[6]
-20
- 90
rnA
lee
Power Supply Current
GND < VIN < Vee
Vee =-MaxJ7f
90
rnA
Vpp
Programming Supply Voltage
Ipp
ProgrammingSupplyCurrent
Vrnp
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
V
0.4
V
2.0
V
-10
ICommercial
I Military
0.8
V
+10
!lA
120
13
14
V
50
rnA
3.0
V
0.4
V
Capacitance [4]
Parameters
Description
CIN
InputCapacitance
CoUT
OutputCapacitance
test Conditions
TA = 25°C, f = 1 MHz,
Vcc=5.0V
Max.
Units
10
pF
10
pF
Notes:
1. See the Ordering Information section for industrial temperaturerange
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
7. Due to the design of the differential cell in this device, Icc can only be
accurately measured on a programmed array.
3-20
CY7C225
AC Test Loads and Waveforms(4)
OUTP~31R1
5V31R12500
OUTPUT
50pF
R2
I
INCLUDING
JIG AND ':'
SCOPE
1670
':'
5pF
INCLUDING
JIG AND ':'
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
2500
.W~1~
GND
R2
1670
S5ns
I-
':'
Cl!25-4
0225-5
(b) High Z Load
THEvENIN EQUIVALENT
1000
OUTPUTOO--....\I\nllo---GO 2.0V
Cl!25-6
Operating Modes
The CY7C225 incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
ttchronous ~) imd asynchronous ~ output enables and
LEAR and PRESET inputs.
Upon power-up, the synchronous enable (I!s) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory location to the address inputs (Ao - As) and a logic WW to the
enable (I!s) input. The stored data is accessed and loaded into
the master flip-flops of the data register during the address set-up
time. At the next WW-to-HIGH transition of the clock (CP),
data is transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs (00 07) provided the asynchronous enable ~ is also Ww.
The outputs mar.!'e disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the
active state by switching the enable to a logic Ww.
Regardless of the condition of:E, the outputs will go to the OFF
or high-impedance state~on the next positive clock edge after
the synchronous enable (Es) input is switched to a HIGH level. If
the synchronous enable pin is switched to a logic Ww, the subsequent positive clock edge will return the output to the active state
if:E is Ww. Following a positive clock edge, the address and syn-
chronous enable inputs are free to change since no change.in the
output will occur until the next WW-to-InGH transition of the
clock. This unique feature aIlows the CY7C225 decoders and
sense amplifiers to access the next location while previously addressed data remainntable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers
available in the market.
The CY7C225 has buffered asynchronous "ClEAR and PlUlSBT
input (lmT). The initia1ize function is useful during power-up
and time-out sequences.
Applying a WW to the ~ input causes an immediate load
of all ones into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). Applying
a WW to the ~ input, resets the flip-flops to all zeros.
The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (l3) Ww.
When power is applied, the (internal) synchronous enable flipflop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur
and the :Es input pin must be WW at least a set-up time prior to
the clock WW-to-HIGH transition. The:E input may then be
used to enable the outputs.
3-21
•
&;~PRF$
~,
CY7C225
SEMICONDUCTOR
Switching Characteristics
Overthe Operating Rangel3, 4]
7C225-25
Description
Parameters
Min.
Max.
7C225-30
Min.
Max.
30
7C225-35
Min.
Max.
7C225-40
Min.
Max. Units
40
tSA
Address Set-Up to Clock HIGH
25
35
tHA
Address Hold from Clock HIGH
0
tco
Clock HIGH to Valid Output
tpwc
Clock Pulse Width
10
15
20
20
tsES
Es Setup to Clock HIGH
10
10
10
10
ns
tRES
Es Hold from Clock HIGH
0
5
5
5
ns
tOB toc
Delayfrom PRESET or CLEAR to Valid Output
tRB tRC
PRESET or CLEAR Recovery to Clock HIGH
15
20
20
20
tpWB tpwc
PRESET or CLEAR Pulse Width
15
20
20
20
teas
Valid Output from Clock HIGH[8]
20
20
25
30
ns
tHZC
Inactive Output from Clock HIGH[8]
20
20
25
30
ns
tOOE
Valid Output from E LOW
20
20
25
30
ns
tHZE
Inactive Output from E HIGH
20
20
25
30
ns
0
0
15
12
20
0
20
20
ns
ns
25
20
ns
ns
20
ns
ns
ns
Switching Waveforms [4]
~-A10 --------------------------~--~~~~--4_--~~~~~~~-----------
CP
00 - 07
--+-----'J''--+--LLIJ
E ____________+-~----------------------------------I'
PSorCLR
C225-7
Note.:
B.
Applies only when the synchronous (Es) function is used.
3-22
CY7C225
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function(9)
A, -At
A,-Ao
CP
Es
CLR
E
PS
0,-00
PGM
VFY
Vpp
E
PS
0,-0,
Read
A7-Ao
X
Va.
VIH
Va.
VIH
07- 0 0
Output Disable
A7-Ao
X
VIH
VIH
X
VIH
HighZ
Output Disable
A7-Ao
X
X
VIH
VIH
VIH
HighZ
Zeros
Read or Output Disable
Mode
Other
Clear
A7-Ao
X
Va.
Va.
Va.
VIH
Preset
A,-Ao
X
Va.
VIH
Va.
Va.
Ones
Program
A7-Ao
VIl.P
VIHP
Vpp
VIHP
VIHP
D7- D O
Program Verify
A7-Ao
VIHP
VILP
Vpp
VIHP
VIHP
07- 0 0
Program Inhibit
A7-Ao
VIHP
VIHP
Vpp
VIHP
VIHP
HighZ
Intelligent Program
A7-Ao
VU.P
VIHP
Vpp
VIHP
VIHP
D7- D O
Blank Check Ones
A7-Ao
Vpp
VIl.P
VIl.P
VIl.P
VIHP
Ones
Blank Check Zeros
A7-Ao
Vpp
VIHP
VU.P
VIl.P
VIHP
Zeros
Notes:
6. X = "don't care" but not to exceed Vee :1:5%.
LCCIPLCC
DIP
TopV\ew
TopVrew
~~ri~~1f
'"
5
AI 6
~ ~
4 3 2, \ 282728
25
CY7C225
~ ~o
D.
E
24
vpp
:
Pm.1
~
NC
fl1213141516171J9
VFY
g:
0225-9
0225-8
Figure 1. Programming Pinouts
3-23
•
~PRR§
~rs~CONDUCTOR
CY7C225
'lYpical DC and AC Characteristics
NORNUUUZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.6
CWCK TO OUTPUT TIME
w
vo.Vee
::iE
i= 1.6
5
jl1.4
/
o
~ 1.2
o~
o
z
1/
0.6
4.0
/
4.5
5.0
5.5
AMBIENTTEMPERATURE ("C)
SUPPLY VOLTAGE M
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
~
i= 1.6
~
~
§
o
o
~
O.B
~
'"
t-.!.
w
~
w
~
::iE
a:
25
125
tzw
50
a:
§
o
w
~ 30
"' '-
§
20
10
o
o
1.0
13
" '"
2.0
3.0
OUTPUT VOLTAGE M
0
w
:::::;
5.0
5.5
1.0
z
0.8
I-""
0.6
- 55
6.0
4.0
5.0
/
0.00
~ 125
/'
a
100
/
(ij
TA=25°C _
Vee = 4.5V
400
..... ~
z
a:
~
I
200
<,175
.s... 150
5
/
600
I
BOO 1000
CAPACITANCE (pF)
125
OUTPUT SINK CURRENT
vo. OUTPUT VOLTAGE
z 75
/v
~ 10.0
25
AMBIENTTEMPERATURE (OC)
-
L
15.0
--
1.2
c(
::iE
a:
0
/
l20.0
"-
6.0
1.4
TYPICAL ACCESS TIME CHANGE
VS. OUTPUT WADING
~
5.5
SUPPLY VOLTAGE M
SUPPLY VOLTAGE M
-
5.0
N
I
4.5
25.0
~
g
5
r".....
30.0
i'..
40
I
4.5
4.0
w
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
60
t-.!.
en
0.6
AMBIENTTEMPERATURE ("C)
.s
~
en O.B
0
z
~ - 55
<'
D..
0
a: 0.6
TA = 25°C
NORMALIZED SET·UP TIME
vs. TEMPERATURE
.........
~
./
r---
1.6
...............
D..
1.2
1.0
oz
1.2
w
::iE
i= 1.0
5 1.4
--
.............
~
a: 0.6
NORMALIZED SET·UPTIME
vs. SUPPLY VOLTAGE
5
o
...........
o
~ O.B
0~5~5----2~5~-----1~25
6.0
r-..
1.2
§o 1.0
z
I
o
~
a:
TA = 25°C
1= fMAX
I!:
~1.4
~
~
o
./
1.0
O.B
jl1.11----+-------l
I!:
~
o
50
25
oV
0.0
Vee = 5.0V
TA=25°C -
I
/
I
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE M
<:225-10
3-24
CY7C225
Ordering Information[10]
Speed
(ns)
tSA
25
30
teo
12
15
35
20
40
25
Ordering
Code
CY7C225-25DC
CY7C225-25JC
CY7C225-25LC
CY7C225-25PC
CY7C225-30DC
CY7C225-30JC
CY7C225-30LC
CY7C225-30PC
CY7C225-30DMB
CY7C225-30LMB
CY7C225-35DMB
CY7C225-35LMB
CY7C225 -40DC
CY7C225-4OJC
CY7C225-40LC
CY7C225-40PC
CY7C225-40DMB
CY7C225-40LMB
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Package
type
Operating
Range
014
J64
L64
P13
D14
J64
L64
P13
014
L64
014
L64
014
J64
L64
P13
014
L64
Commercial
DC Characteristics
Parameters
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOH
VOL
Vrn
VIL
Commercial
IIX
Ioz
Icc
Military
Switching Characteristics
Military
Parameters
Subgroups
tsA
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
tHA
teo
Commercial
top
tRP
SMD Cross Reference
Military
SMD
Number
Notes:
10. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
Suffix
5962-88518
OUX
CY7C225-30DMB
5962-88518
013X
CY7C225-30LMB
5962-88518
02LX
CY7C225-35DMB
5962-88518
023X
CY7C225-35LMB
5962-88518
03LX
CY7C225-40DMB
5962-88518
033X
CY7C225-40LMB
Document#: 38-00002-D
3-25
Cypress
Number
CY7C235
CYPRESS
SEMICONDUCTOR
Features
1024 x 8 Registered PROM
technology and byte-wide intelligent programming algorithms.
The CY7C235 replaces bipolar devices
pin for pin and offers the advantages of
lower power, superior perfonnance, and
high programming yield. The EPROM
cell requires only 13.5V for the supervoltage, and low corrent requirements allow
for gang programming. The EPROM cells
allow for each memory location to be
tested 100%, as each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each PROM is
also tested for AC perfonnance to guarantee that the product will meet AC spec:ification limits after customer programming.
• Slim, 300-mil, Upln plastic or hermetic DIP or 18-pln LeC and PLCC
• SV :10% Vee, commercIal and
military
• TTL-compatlble I/O
• Direcl replacement for bipolar
PROMs
• Capable of withstandinil greater than
1500V static discharge
• CMOS for optimum speedlpower
• Highspeed
-15 ns max set-up
-12 ns clock to output
• Lowpower
-495 mW (commercIal)
-660 mW (military)
• Sync:hronous and async:hronous
output enables
• On-cl1ip edge-triggered registers
• Programmable asynchronous
registers (iN'fi'>
• EPROM teclmology, 100%
programmable
FDnctionalDesorlption
The CY7C235 is a bigh-perfonnance
1024 word by 8 bit elec:tric:aJly programmable read only memory packaged in a
slim 3OO-mil plastic or hermetic DIP,
28-pin leadless chip carrier, or 28-pin
plastic leaded chip carrier. The memory
cells utilize proven EPROM floating-gate
Pin Configurations
Logic Block Diagram
DIP
'lbpView
m------~~.-----------------------~
Vee
A,
0.
~
~
~
~
~
~
ROW
DEOODER
Ao
At
Co
At
'Es
'"
CP
PRClGRAMMAllLE
ARRAY
A,
~
8-IlIT
EDGE-
As
11\IClOEREO
REGISlER
CIa
At
9
A,
0,
o.
O.
O.
Clz
COWMN
0,
08
o.
ONO
At
E
m
At>
00
0-
"-
4
Oa
0235-2
DEOODER
0,
At>
00
4 32c\
E
Ao 6
At 8
At 7
CP
A,
!Os
'flIT
!Os
CP
8
At> 9
NC
00
E
0235-1
NC
10
111213141518171819
ocS'~ !J.~i!~
0.
Oa
0235-3
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum 3.)erating
Current(mA
I
7C235-lS
lS
7C235-30
30
7C135-40
12
15
90
120
20
90
120
90
Commercial
r Militarv
3-26
40
CY7C235
Maximum Ratings
(Above which the useful life maybe impaired. Foruser guidelines,
not tested.)
Storage Thmperature ................. Ambient Thmperature with
Power Applied .•.................... Supply Voltage to Ground Potential
(pm 24 to Pin 12for DIP) ...............
DC Voltage Applied to Outputs
in High Z State .•......................
DC Input Voltage .....•................
DC Program Voltage (Pins 7, 18, 20 for DIP)
65° C to + 150° C
55 ° C to +125° C
Static Discharge Voltage ....•..•....•.•.....•... > 1500V
(per MIL-sTD-883, Method 3015)
Latch-Up Current ............•....•.......•. >200 rnA
Operating Range
- O.5V to +7.0V
- O.SV to + 7.0V
-3.0Vto +7.0V
......... 14.0V
Ambient
Temperature
Range
Commercial
IndustriaiL1]
O°Cto +70°C
Vee
5V±10%
-40°Cto +85°C
5V ±10%
Military[2]
-55°Cto +125°C
5V±1O%
Description
Thst Conditions
Min.
Max.
Units
2.4
V
VOH
Output mGH Voltage
Vee = Min., IOH = - 4.0 rnA
VIN = VIH or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VlH or VIL
VlH
Input mGH Level
Guaranteed Input Logical mGH Voltage for
AlIInputsl4]
VIL
Input LOW Level
GuaranteedInputLogicai LOW Voltage for All
Inputs[4]
Irx
Input Leakage Current
GND.s. VIN.s. Vee
Veo
Input Clamp Diode Voltage
NoteS
Ioz
Output Leakage Current
GND.s. Vo.s. Vee Output DisabledLS]
-40
+40
!LA
los
Output Short Circuit Current
Vee = Max., Your = 0.0y(6]
-20
-90
rnA
lee
Power Supply Currentl7]
GND.s. VIN.s. Vee,
Vee = Max.
90
rnA
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
0.4
V
2.0
-10
I Commercial
I Military
V
0.8
V
+10
!LA
120
13
14
V
50
rnA
3.0
V
0.4
V
Capacitance[S]
Parameters
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz, Vee =5.0V
Notes:
1. Contact a Cypress representative for industrial temperatnre range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page ohhis specification for Group A subgroup testing in-
formation.
4.
oa:
a...
Electrical Characteristics Over Operating Range[3]
Parameters
U)
::::E
5.
6.
7.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
3-27
Max.
Units
10
pF
10
pF
See Introduetion to CMOS PROMs in this Data Book for general information on testing.
For test PUlpOSCs, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Due to the design of the differential cell in this device, ICC can only be
accurately measured on a programmed array.
CY7C235
AC Test Loads and Waveformslsl
5V31
R12500
R12500
50 pF
INCWDING _
JIGAND SCOPE
OUTP:31
R2
1670
_
-
5pF
INCWDING _
JIGAND SCOPE
R2
1670
GND
.s.5ns
_
CZIS-4
I-
~
10%
.s. 5 ns
CZIS-5
(b) Hlgb Z Load
(a)
Equivalent to:
... ~1;:-
ALL INPUT PULSES
OUTPUT
THBtENIN EaUIVALENT
1000
OUTPUTo.o----lIIou...---GO 2.0V
CZIS-6
Operating Modes
The CY7C235 incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
synchronous (Us) and asynchronous (U) output enables and
asynchronous initialization (INIT).
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory location to the address input (Ao - Ag) and a logic WW to the
enable (P:s) input. The stored data is accessed and loaded into
the master flip-flops of the data register during the address set-up
time. At the next WW-to-HIGH transition of the clock (CP),
data is transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs (00 07), provided the asynchronous enable (E) is also Ww.
The outputs mar.t>e disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the
active state by switching the enable to a logic Ww.
Regardless of the condition of~, the outputs will go to the OFF
or high-impedance state.s'0n the next positive clock edge after
the synchronous enable (Es) input is switched to a HIGH level. If
the synchronous enable pin is switched to a logic Ww, the subsequent positive clock edge will return the output to the active state
if~ is Ww. Fol\owing a positive clock edge, the address and synchronous enable inputs are free to change since no change in the
output wil\ occur until the next WW-to-HIGH transition of the
clock This unique feature al\ows the CY7C235 decoders and
sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the sys-
tern clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers
available in the market.
The CY7C235 has an asynchronous initialize input (ImT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated
functions such as a bnilt-in "jump start" address. When activated
the initialize control input causes the contents of a user programmed 1025th 8-bit word to be loaded into the on-chip register. Each bit is programmable and the initialize function can be
used to load any desired combination oft's and O's into the register. In the unprogrammed state, activating liiIIT will generate a
register CLEAR (al\ outputs W'Yl:..!fal\ the bits of the initialize
word are programmed, activating INIT performs a register PRESET (all outputs HIGH).
Applying a WW to the mIT input causes an immediate load of
the programmed initialize word into the master and slave flipflops of the register, independent of all other inputs, including
the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous
enable (U) Ww.
When power is applied the (internal) synchronous enable flipflop wil\ be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur
and the ~ input pin must be LOW at least a set-up time prior to
the clock LOW-to-HIGH transition. The I!: input may then be
used to enable the outputs.
When the asynchronous initialize input, INIT, is Ww, the data in
the initialize byte will be asynchronously loaded into the output
register. It will not, however, appear on the output pins until they
are enabled, as described in the preceding paragraph.
3-28
C~)l~
~
CY7C235
SEMICONDUCTOR
Switching Characteristics Over Operating Rangel3. S1
7C23S-2S
Description
Parameters
Min.
Max.
7C23S-30
Min.
Max.
7C23S-40
Min.
tSA
Address Set-Up to Clock HIGH
25
30
40
tRA
Address Hold from Dock mGH
0
0
0
teo
Dock mGH to Valid Output
Max.
Units
ns
tpwc
Dock Pulse Width
12
15
20
tsES
Es Set-Up to Dock mGH
10
10
15
ns
tHES
Es Hold from Clock mGH
5
5
5
ns
•
ns
D.
15
12
25
ns
ns
20
ns
35
25
tDl
Delay from INIT to Valid Output
tRJ
INIT Recovery to Dock mGH
20
tPWJ
lm'f Pulse Width
20
teas
Inactive to Valid Output from Dock mGHI8j
20
20
25
tHZC
Inactive Output from Clock mGHI8]
20
20
25
ns
tOOE
Valid Output from 13 LOW
20
20
25
ns
tHZE
Inactive Output from P; mGH
20
20
25
ns
20
ns
20
25
20
ns
ns
Noles:
8. Applies only when the synchronous (Es) function is used.
Switching WaveformslS1
AO-Al0 ____________________________+_--~~~----+_--~~~~~~O-------------
CP
00 -
Or ---+-----"1'--+-...J.'"'l
IOOE
~ ----------~-+------------------------------II
C235-7
3-29
'"
:t
o
a::
CY7C235
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable
Mode
Other
Read
Ao.A3 -A,
Ao.A3 -A,
Al
A2
CP
ES
E
INIT
Al
A2
PGM
VFY
E
Vpp
D,-Do
Ao,A3 -A9
Al
Az
X
VIL
VlL
Vrn
0,-00
07-00
Output Disable
Ao,A3 -A9
Al
Az
X
Vrn
X
Vrn
Output Disable
Ao,A3 -A9
Al
AZ
X
X
VIH
VIH
HighZ
HighZ
Initialize
Ao,A3 -A9
Al
Az
X
X
VIL
VIL
lnit Byte
D,-Do
07- 0 0
Program
Ao,A3 -A9
Al
AZ
VILP
VIHP
VUIP
Vpp
Program Verify
Ao,A3 -A9
Al
Az
VIIIP
VILP
VUIP
Vpp
Program Inhibit
Ao,A3 -~
Al
Az
VIIIP
VIIIP
VIIIP
Vpp
HighZ
Intelligent Program
Ao,A3 -A9
Al
Az
VILP
VUIP
VUIP
Vpp
D,-Do
Program Initialize Byte
Ao,A3 -A9
Vpp
VILP
VILP
VUIP
VIIIP
Vpp
D,-Do
Blank Check Ones
Ao,A3 -A9
Al
Az
Vpp
VILP
VILP
VILP
Ones
Blank Check Zeros
Ao,A3 -A9
Al
Az
Vpp
VUIP
VILP
VILP
Zeros
Notes:
9. X = "don't care" but not to exceed Vee ±S%.
DIP
Top View
LCC/PLCC
Top View
:U~$:u
Vee
A.
4 3 2 L1. 282726
As
25
24
23
22
21
Iv.
As
E
~
A,
Vpp
vr:v
Ao
I'llf,l
07
NC
Do
D.
D.
D.
GND
D.
' - - - - . . . . C235-8
10
11
20
19
12131415161718
a8'~~&,~E
"
Figure 1. Programming Pinouts
3-30
E
Vpp
vr:v
I'llf,l
NC
D7
D.
C235-9
CY7C235
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE
NOR~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
VI.
1.2
1.6
~ 1.4
/
0
w
~
~
ex:
0
1.2
1.0
z
0.8
/'
0.6
4.0
w
N
./
/
4.5
~ 1.1
0
~
ex:
0
TA = 25 C
f = fMAl(
5.0
I
5.5
f?
l<:
u
§
Z
w
~
1
~
30
o
0.4
4.0
......
~
10
1.0
5.0
5.5
/
~ 10.0
"
3.0
OUTPUT VOLTAGE (V)
4.0
0.8
~
0.6
6.0
-
/
20.0
!:i
2.0
1.0
I
<=: 15.0
~
~
oZ
5.0
~
/
V
0.00
!Z
w 125
TA= 25 C _
Vee = 4.5V
400
600
I
800 1000
CAPACITANCE (pF)
r
~
a 100
;s:;
I
200
:cc 175
OUTPUT SINK CURRENT
OUTPUT VOLTAGE
VI.
g, 150
l<:
D
125
AMBIENT TEMPERATURE (DC)
i :~ I /
o
0.0
".---
/
75
CIl
V
25
- 55
SUPPLY VOLTAGE M
~
"-
~
TA = 25 D C
4.5
-
o 1.2
TYPICAL ACCESS TIME CHANGE
VI. OUTPUT WADING
~
1.4
Iii
CIl
ex:
2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . . . . . . . . . . . . . . . . . .. .. . . . . . . . >200rnA
Operating Range
Range
Commercial
IndustriaIl1]
Militaryf2]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±1O%
-40°Cto +85°C
5V±1O%
-55°Cto +l25°C
5V±1O%
7C245AL-35
7C245A -15, 18 7C245A-25,35,45 7C245AL-45
VOH
VOL
Vrn
VIL
Thst Conditions
Description
Output mGH Voltage Vee - Min.,IoH - - 4.0 rnA
VIN = Vrn orVIL
Output LOW Voltage Vee = Min., IOL = 16 rnA
VIN= VrnorVIL
Input HIGH Level
Guaranteed Input Logical
mGH Voltage for All Inputs
Input LOW Level
Min.
Max.
2.4
Min.
2.4
0.4
2.0
Guaranteed Input Logical
Vee
Max.
Min.
Max.
Units
V
0.4
V
Vee
V
0.8
V
-10
+10
!J.A.
2.4
0.4
2.0
0.8
Vee
2.0
0.8
WW Voltage for All Inputs
IIX
VCD
Input Leakage Current
Input Clamp Diode
Voltage
-10
GNDsVINsVee
+10
-10
Note 4
+10
Note 4
Ioz
Output Leakage
Current
GNDsVosV8f
Output Disabled
-10
+10
-10
+10
-10
+10
!J.A.
los
Output Short Circuit
Current
Power Supply Current
Vee - Max., VOUT -O.OVIO]
-20
-90
-20
-90
-20
-90
rnA
60
rnA
12
120
120
13
13
V
50
rnA
Icc
Vpp
Ipp
Vrnp
VILP
GND S VIN S Vee
Vee = Max.
I Com'l
IMil
PrograromingSupply
Vpltage
.. -PrograromingSupply
Current
InputmGH
ProgrammingVoltage
90
120
12
50
3.0
Input LOW
ProgrammingVoltage
13
50
3.0
0.4
12
3.0
0.4
V
0.4
V
Capacitance[4]
Parameters
qN
CoUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA=25°C,f=IMHz,
Vee = 5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
en
:E
o
a:
Il.
Electrical Characteristics Over the Operating Rangef3, 4]
Parameters
•
4.
S.
6.
3-35
Max.
Units
10
pF
10
pF
See the "!ntroduc!ionto CMOS PROMs" sec!ion of the Cypress Data
Book for general information on testing.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
CY7C245A
AC Test Loads and Waveforms[3.4)
R12500
R12500
5V~ o~31R2
ALL INPUT PULSES
OUTPUT
R2
50pF
1670
INCWDING _
JIGAND -
_
-
5pF
~~O%
~ ~
02451\-5
C!4SA-4
(b) High Z Load
end on the programmed state of the enable function (Bs or E). If the synchronous enable (Bs) has been programmed, the register will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. If the asynchronous enable (B) is being
used, the outputs will come up in the OFF or high-impedance
state only if the enable (B) input is at a mGH logic level. Data is
read by applying the memory location to the address inputs (Ao
- AlO) and a logic LOW to the enable input. The stored data is
accessed and loaded into the master flip-flops of the data register
during the address set-up time. At the next LOW-to-mGH transition of the clock (CP), data is transferred to the slave flip-flops,
which drive the output buffers, and the accessed data will appear
at the outputs (00 - 07).
If the asynchronous enable (B) is being used, the outputs may be
disabled at any time by switching the enable to a logic mGH,
and may be returned to the active state by switching the enable to
a logic LOW.
If the synchronous enable (Bs) is being used, the outputs will go
to the OFF or high-impedance state upon the next positive clock
edge after the synchronous enable input is switched to a mGH
level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the
active state. Following a positive clock edge, the address and synChronous enable inputs are free to change since no change in the
output will occur until the next LOW-to-mGH transition of the
clock.. This unique feature allows the CY7C245A .decoders and
sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
3-36
CY7C245A
Operating Modes (continued)
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers
available in the market.
The CY7C245A has an asynchronous initialize input (INIT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated
functions such as a bnilt-in "jump start" address. When activated,
the initialize control input causes the contents of a user-programmed 2049th 8-bit word to be loaded into the on-chip regis-
ter. Each bit is programmable and the initialize function can be
used to load any desired combination of 1's and O's into the register. In the unprogrammed state, activating I!ill'f will generate a
register CLEAR (all outputs LOW). If all the bits of the initialize
word are programmed, activating lNIT performs a register PRESET (all outputs HIGH).
Applying a LOW to the I!ill'f input causes an immediate load. of
the programmed initialize word into the master and slave fhpflops of the register, independent of all other inputs, including
the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous
enable (E) LOW.
II)
:E
o
a:
Switching Waveforms[4]
~-A10
•
11.
________________________~~--~~~--~--~~~~~~~----------
CP
!tize
tees
tDOE
C245A-7
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
7C245A. For this reason, an opaque label should be placed over
the window if the PROM is exposed to sunlight or fluorescent
lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2• For an ultraviolet lamp with a 12 mW/cm 2 power rating the exposure time would
be approximately 30 to 35 minutes. The 7C245A needs to be
within 1 inch of the lamp during erasure. Permanent damage may
result if the PROM is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm2 is the recommended
maximum dosage.
this section. Programming algorithms can be obtained from any
Cypress representative.
BitMap Data
Programmer Address
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
Decimal
Hex
RAM Data Contents
0
0
DATA
2047
2048
7FF
800
INITBYTE
2049
801
CONTROL BYTE
DATA
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
3-37
CY7C245A
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable
Mode
Otber
Rea~
Output Disable
Initialize
Program
Program Verify
Program Inhibit
Intelligent Program
Program Synchronous Enable
Program Initialization Byte
Blank Check Zeros
-A4
AIO -A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AlO - A4
AIO
A3
A2- Al
A3
A2- Al
A3
A2- Al
A3
A2- Al
A3
A2- Al
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
VIHP
A2- Al
Vpp
VILP
A2- Al
Vpp
A3
A2- Al
A3
A2- Al
A3
A2- Al
A3
A2- Al
A3
CP
E,Er;
INIT
PGM
VFY
Vpp
D7 - Do
VUJVIH
VIL
VIH
07 -00
X
VIH
VIH
HighZ
Init. Byte
X
VIL
VIL
VlI.P
VIHP
Vpp
D7- D O
VIHP
VILP
Vpp
07 -00
VIHP
VIHP
Vpp
HighZ
VILP
VIHP
Vpp
D7- D O
VILP
VIHP
Vpp
HighZ
VIHP
Vpp
D7- D O
VILP
Vpp
Zeros
VILP
Ao
A2- Al
VIHP
Note:
9. X = "don't care" but not to exceed Vee +5%.
DIP
Top View
LCClPLCC (Opaque only)
Top View
.rn~Jl~~
Vee
Ao
Ao
4 3 2,1,282726
A. 5
-
25
A,.
Vpp
...70
24
VI'Y
l'GM
"09
NC 10
21NC
0,
Do
A,.
0"
0.
~
6
Vpp
A,
8
23
22
VI'Y
Pm.l
20
07
111213141516171819
Ds
a8~ ~~Jr!f
"
0,
0"
C245A-8
Figure 1. Programming Pinouts
3-38
07- 00
C245A-9
~
CY7C245A
~=CYPRESS
~_.iF SEMICOIDUCTOR
'fYpical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
i= 1.6
1.2
1.6
CLOCK TO OUTPUT TIME
vs.Vee
UJ
::;;
5
01.4
/
.E
0
UJ
N
~
1.2
II:
1.0
V
z
0.8
o
V
~ 1.0
o
z 0.91----+------='"
f = fMAJ(
I
0.6
4.0
4.5
5.0
5.5
0~5~5---~2~5~-------~1~25
6.0
AMBIENTTEMPERATURE (OC)
SUPPLY VOLTAGE M
CWCK TO OUTPUT TIME
vs. TEMPERATURE
!!i!
I!:
:::J
q
~
~
1.2
UJ
o
I!:l
:J 0.8
z
r........
Q.
~
-----
0.6
- 55
Iiien
0
UJ
II:
~
50
II:
~ 40
U
30
........
5o
10
0
o
1.0
-
~
~
""
2.0
~
3.0
1.0
z 0.8
I
4.5
5.0
5.5
4.0
5.5
6.0
~
25
125
AMBIENTTEMPERATURE rC)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
:( 175
/
20.0
a
~
z
en
5
V
TA=25°C _
Vee = 4.5V
I
200
!z
400
600
~
~ 125
/v
V
.s 150
II:
/
15.0
5.0
5.0
----
0.6
- 55
6.0
,-
~ 10.0
OUTPUT VOLTAGE M
«
:::;:
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTWADING
~
20
:J
SUPPLY VOLTAGE M
I
"-
1.2
0
25.0
"-
0
N
II:
Z
125
1.4
UJ
........
30.0
:::J
g
5
"'-
TA = 25°C
0.4
4.0
I
4.5
SUPPLY VOLTAGE M
:::J
Iii
en
0.6
OUTPUT SOURCE CURRENT
vs.VOLTAGE
60
~
............
0.8
AMBIENTTEMPERATURE (0C)
1
z
TA = 25°C
0.6
4.0
1.6
0
25
j
o
Q.
~
«
::;;
o
a:
Q.
0.8
NORMALIZED SET-UP TIME
vs. TEMPERATURE
,
:::J
9
u 1.0
~
o
i= 1.0
1.4
II)
:::i1i
o
I!:l
NO~ZEDSET·UPTIME
::;;
1.2
~ 1.2
9 1.0 r-- I--
vs. SUPPLY VOLTAGE
i= 1.6
5
•
1.4
U
II:
TA = 25°C
5
~
I!:l
.,/
::;;
0
Jll.l P1c---+-------i
I
800 1000
CAPACITANCE (pF)
5o
100
/
75
50
25
I
Vcc= 5.0V
TA=25°C -
/
oV
0.0
/
I
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE M
C245A-10
3-39
iirA~O@U~R
CY7C245A
Ordering Information[lO)
Speed (ns)
Icc
tSA
teo
(mA)
15
10
120
18
12
120
25
15
90
120
35
20
60
90
120
45
25
60
90
120
Ordering
Code
CY7C245A -15JC
CY7C245A -15PC
CY7C245A 15WC
CY7C245A 18JC
CY7C245A -18PC
CY7C245A-18WC
CY7C245A-18DMB
CY7C245A -18LMB
CY7C245A 18QMB
CY7C245A -18TMB
CY7C245A -18WMB
CY7C245A-25JC
CY7C245A-25PC
CY7C245A - 25SC
CY7C245A 25WC
CY7C245A-25DMB
CY7C245A-25LMB
CY7C245A-25QMB
CY7C245A-25TMB
CY7C245A 25WMB
CY7C245AL 35PC
CY7C245AL-35WC
CY7C245A-35JC
CY7C245A-35PC
CY7C245A-35SC
CY7C245A 35WC
CY7C245A 35DMB
CY7C245A -35LMB
CY7C245A-35QMB
CY7C245A-35TMB
CY7C245A-35WMB
CY7C245A 45JC
CY7C245A 45PC
CY7C245A -45JC
CY7C245A -45PC
CY7C245A -45SC
CY7C245A-45WC
CY7C245A 45DMB
CY7C245A 45LMB
CY7C245A-45QMB
CY7C245A-25TMB
CY7C245A-25WMB
Package
'JYpe
J64
P13
W14
J64
P13
W14
D14
L64
Q64
T73
W14
J64
P13
S13
W14
D14
L64
Q64
T73
W14
P13
W14
J64
P13
S13
W14
D14
L64
Q64
T73
W14
J64
P13
J64
P13
S13
W14
D14
L64
Q64
T73
W14
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
Note:
10. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-40
-~
. .~
CY7C245A
~-CYPRESS
~, SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VJH
VIL
IIX
Ioz
Icc
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
•
II)
:i
oa:
a.
Switching Characteristics
Parameters
Subgroups
tSA
tIlA
teo
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
SMD Cross Reference
SMD
Number
SuffIX
Cypress
Number
5962-88735
OlKX
CY7C245A-45KMB
5962-88735
01LX
CY7C245A-45DMB
5962-88735
0l3X
CY7C245A-45LMB
5962-88735
02KX
CY7C245A-35KMB
5962-88735
02LX
CY7C245A-35DMB
5962-88735
023X
CY7C245A-35LMB
5962-88735
03KX
CY7C245A-35KMB
5962-88735
03LX
CY7C245A-35DMB
5962-88735
033X
CY7C245A-25LMB
5962-88735
04KX
CY7C245A-25KMB
5962-88735
04LX
CY7C245A-25DMB
5962-88735
043X
CY7C245A-25LMB
5962-87529
01KX
CY7C245A -45TMB
5962-87529
01LX
CY7C245A -45WMB
5962-87529
013X
CY7C245A-45QMB
5962-87529
02KX
CY7C245A-35TMB
5962-87529
02LX
CY7C245A-35WMB
5962-87529
023X
CY7C245A-35QMB
Document #: 38-00074-D
3-41
CY7C251
CY7C254
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammabllity
• Highspeed
-45ns
• Lowpower
-550mW (commercial)
- 660 mW (military)
• Super low standby power (7C251)
- Less tban 165 mW when
deselected
- Fast access: 50 ns
• EPROM technology 100%
programmable
• Slim 300·mll or standard 6OO.mll
packaging available
• 5V ±ID'l1> Vee, commerclaland
military
16,384 x 8 PROM Power
Switched and Reprogrammable
• TIL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable ofwltbstandlog > 2001V stat·
ic discbarge
Functional Description
The CY7051 and CY7054 are highperfonnance 16,384-word by S-bit CMOS
PROMs. When deselected, the CY7051
automatically powers down into a lowpower stand-by mode. It is packaged in a
3OO-mil-wide package. The 7054 is
packaged in a 6OO-mil-wide package and
does not power down when deselected.
The 7051 and 7054 are available in reprogrammable packages equipped with an
erasure windoW; when exposed to UV
light, these PROMs are erased and can
then be reprogrammed. The memory
cells utilize proven EPROM floating gate
technology and byte-wide intelligent programming algorithms.
Logic Block Diagram
The CY1051 and CY1054 are plug-in
replacements for bipolar devices and offer
the advantages of lower power, superior
performance, and high programming yield
The EPROM c:eIl requires only 12.5V for
the super voltage, and low current requirements allow for gang programming.
The EPROM cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation.
Each PROM is also tested for AC perfonnance to guarantee that after customer programming, the product will meet
DC and AC specification limits.
Reading is accomplished by placing all
four chip selects in their active states.
The contents of the memory location addressed by the address lines (At> - A13)
will become available on the output lines
(00 - 07).
Pin Configurations
DlP/Flatpack
Vee
A,.
A,
3
A"
Ae
Ae
A12
A,.
t:S,
Ae
Ao
~
os.
os.
Ao
A,
Ao
0,
08
O.
O.
00
0,
O.
ONO
O. 0251-2
LCC
J»~::$1i
Ae 5
Ae
6
At
78
~~
Ae
NO
00
t:S,
0,
~----~~~--------------------------~
.. 32,,323130
9
-
0
70251
28C A,.
~~ ~
~c~
25C
os.
os.
10
~l
11
7C254
23. NO
12
22C 0,
13
21C 08
14151617181920
0251-3
Selection Guide
Maximum Access Time (os)
Maximum ~erating
Current (rnA
Standby Current (mA)
(7051 only)
Commercial
Military
Commercial
MilitaIy
7C251-45,7Cl54-45
45
100
120
30
35
3-42
7C251-5S,7C254-SS
55
100
120
30
35
7ClSI-65,7ClS4-65
65
100
120
30
35
"
CY7C251
CY7C254
.~
_ " j g CYPRESS
-
F
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
Storage Temperature ."" .... """" .. " ... - 65°C to +150°C
Ambient Temperaturewith
PowerApplied ....................... -55°Cto +l25°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... -0.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ -O.5Vto +7.0V
DC Input Voltage ...................... -3.0Vto +7.0V
DC Program Voltage (Pin 22) . . . . . . . . . . . . . . . . . . . . . .. 13.5V
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
UVExposure ............................ 7258Wsec/cm2
Range
Commercial
O°Cto +70°C
Vee
5V±1O%
Industriafll
Militaryl2]
-40°Cto +85°C
5V±1O%
•
-55°Cto +125°C
5V±1O%
Il.
Operating Range
Ambient
Thmperature
Electrical Characteristics Over the Operating Rangel3, 4]
7C251-45, 55, 65
7C254-45, 55, 65
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA
Vrn
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
IIX
Input Current
GND ~ VIN ~ Vce
VCD
Input Diode Clamp Voltage
loz
Output LeakageCurrent
GND ~ VOUT ~ Vce, Output Disabled
-40
+40
IlA
loS
Output Short Circuit Current[5j
Vee = Max., VOUT = GND
- 20
- 90
rnA
lee
Power Supply Current
Vce = Max., lOUT = 0 rnA
Com'l
100
rnA
Mil
120
Com'l
30
Mil
35
ISB
Standby Supply Current
(7C251)
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
Min.
Max.
Units
0.5
V
2.4
V
2.0
V
-10
0.8
V
+10
IlA
Note 4
Y!;c=Max.,
CSl = Vrn, lOUT = 0 rnA
12
rnA
13
V
50
rnA
3.0
V
0.4
V
Capacitance [4]
Parameters
CIN
COUT
Description
InputCapacitance
Output CapaCitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee
Notes:
1. Contact a Cypress representative regarding industrial temperatnre
range specification.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
= 5.0V
4.
5.
3-43
Max.
10
10
Units
pF
pF
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
II)
~
o
a::
CY7C251
CY7C254
AC Test Loads and Waveforms [4]
OUTP~~31Rl235Q
SV31Rl23SQ
OUTPUT
30pF
SPFI
R2
lS9Q
I _
INCLUDING
JIGAND SCOPE
INCLUDING _
JIG AND SCOPE
-
_ 159Q
-
<=~
+
>
C258-3
Selection Guide
Notes:
1. This parameter is programmable.
3-49
Os
O.
0"
Vss
Vee
Do
0,
Do
Do
Vee
Vss
C258-4
•
-===-=-~
CY7C258
CY7C259
PRELIMINARY
~.if
CYPRESS
~, SEMlCONOOcroR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200mA
UVExposure ............................ 7258Wsec/cm2
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... - O.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
DC Program Voltage. .. .. . . . . . . . . . .. . . .. . . . . . . . ... 13.0V
Electrical Characteristics
Parameter
Operating Range
Ambient
Temperature
Range
Commercial
O°Cto +70°C
Vee
5V± 10%
Industria12]
- 40°C to +85°C
5V± 10%
Militaryl3]
- 55°Cto +125°C
5V± 10%
Overthe Operating Rangel4, 5,6]
Description
Test Conditions
VOH
Output mGH Voltage
Vee = Min.,IOH =- 2mA
VOL
Output LOW Voltage
Vee = Min.,loL= 8mA
Min.
Units
Max.
2.4
I Commercial
I Military
Vee-Min.,loL- 6mA
V
0.4
V
0.4
V
V
Vm
Input mGH Voltage
Guaranteedlnput Logical HIGH Voltage for all Inputs
2.0
6.0
VIL
Input LOW Voltage
GuaranteedInput Logical LOW Voltage for all Inputs
-3.0
0.8
V
IIX
Input Load Current
GND 5 VIN 5 Vee
-10
+10
loz
Output LeakageCurrent
GND 5 VOUT 5 Vee, Output Disabled
-40
+40
!lA
!lA
los
Output Short Circuit Current[7]
Vee = Max., VOUT = GND
- 20
- 90
mA
Icc
Maximum Operating Current
Vee = Max., lOUT = 0 mA
175
mA
200
mA
I Commercial
I Military
Vee - Max., lOUT - 0 mA
Capacitance[5]
Parameters
CIN
CoUT
Description
Test Conditions
InputCapacitance
Output Capacitance
TA = 25°C,f= 1 MHz,
Vee=5.0V
Notes:
2. Contact a Cypress representative for industrial temperature range
specification.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
6.
7.
Max.
Units
10
pF
10
pF
Data for 12-ns Commercial and 15-ns Military is advanced information.
For test purposes, not more than one ontput at a time should be
shorted. Short circnit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms[4]
500n
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5V 5 f } ( 6 5 8
Mil)
0OUTPUT
3330(4030- Mil)
I
50 pF
-
ALL INPUT PULSES
500n
~(658ll
Mil)
-
90%
GND
I
3330-
5 pF
INCLUDING
JIG AND
SCOPE
(a)
3.0V
-
(4030- Mil)
-
(h) ffigb Z wad
I
Equivalent to: THEVENIN EQUIVALENT
200n
(25()Jt Mil)
2 OV
OUTPUT~ (1.9VMiI)
3-50
C258-5
C258-6
-.
----...
.iiCYPRF.SS
,
PRELIMINARY
SEMICamUCTOR
Switching Characteristics
Over the Operating Rangel3,4]
Commercial
12ns
Parameters
Description
Military
15ns
18ns
15ns
18ns
25ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tcp
Clock Period
12
15
18
15
18
25
ns
tCH
Clock HIGH
5
6.5
8
6.5
8
11.5
ns
tCL
Clock LOW
5
6.5
8
6.5
8
11.5
ns
tAS
Address Set-Up to CLK
3/7
4/8
5/9
4/8
5/9
6/10
ns
tAR
Address hold from CLK
3/0
4/1
5/2
4/1
5/2
6/3
ns
tABS
Address Set-Up to CLK
with Input Bypassed
12
15
18
15
18
25
ns
tABH
Address Hold from CLK
with Input Bypassed
0
0
0
0
0
0
ns
tcss
Chip Select Set-Up to
CLK
3/7
4/8
5/9
4/8
5/9
6/10
ns
tCSH
Chip Select Hold from
CLK
3/0
4/1
5/2
4/1
5/2
6/3
ns
11
9
11
13
15
tCKO
CLK to Data Valid
tDH
Data Hold From CLK
tcov
CLK to Output Valid[7]
9
11
13
11
13
15
ns
tcoz
CLKtoHighZ
Output[8]
9
11
13
11
13
15
ns
tcsv
CS to Output Valid with
InputBypassedlHj
12
15
18
15
18
21
ns
tcsz
CS to High Z Output
with Input Bypassed [8]
12
15
18
15
18
21
ns
tOEV
OE to Output Valid[7]
9
11
13
11
13
15
ns
tOEZ
OE to High Z OutpuLl8]
15
ns
tIS
INITSet-Up to CLK
3/7
4/8
5/9
4/8
5/9
6/10
ns
tIH
INITHold from CLK
3/0
4/1
5/2
4/1
5/2
6/3
ns
tIBS
INITSet-Up to eLK
with Input Bypassed
12
15
18
15
18
25
ns
tIBH
INITHold from CLK
with Input Bypassed
0
0
0
0
0
0
ns
tpD
Propagation Dclaywith
Input and Output
Bypasscd
18
21
25
21
25
30
ns
tlCO
CLK to Output Valid
with Output Bypassed
18
21
25
21
25
30
ns
tIW
AsynchronouslNIT
Pulse Width
tIDY
AsynchronouslNIT to
Data Valid
tlCR
AsynchronouslNIT
Recovery to Clock
0
11
9
12
0
15
Notes:
See Output Waveform-Measurement Level
3-51
13
18
ns
25
25
ns
ns
25
18
15
15
0
18
15
18
18
15
13
0
11
13
18
15
12
12
0
0
Shaded area contams advanced mformation.
8.
CY7C258
CY7C259
ns
ns
II)
::!!E
o
a::
a.
-=-. F!r
PRELIMINARY
CYPRESS
CY7C258
CY7C259
SEMICa-IDUCTOR
Output Waveform-Measurement Level
;
O.sv
HigbZ
OUtput
VOH
Rth
'~.=1.5V
Pin~V.
CL= SpF
or7~.=2.6V
VOL
HiltZ
OU ut
Rth
Pino---J\.Nv----O V.
t
CL=SpF
333Q
~::!cr:
v.
O.OV
7~VOH
Pino-----JVVy--o V.
CL=SOpF
~::!cr:
SOOQ
V.
2.6V
1.SV
VOL
'~
Pin~v.
CL=SOpF
C258-7
3-52
54
.-;;z
~.E CYPRESS
-=.'
CY7C258
CY7C259
PRELIMINARY
SEMlCONDUCIDR
Switching Waveforms
Registered Input and Output (combined with INIT)
•
ClK
Ao -
en
A10
:E
-------1---'
o
a:
-+-__.J ,,_ _ _ _..1 ,,_ _ _ _..1 ,-_ _"';'::""'J '-_ _ __
0 0 - 0 7 (015) _ _ _ _ _ _ _.j....._ _ _ _
I N I T - - - -.......
IIH
1185
tlBH
(BYPASSEO INIT REG.)
CS, OE assumed active
C258 8
Bypassed Address and INIT Registers
ClK
Ao -
A10
0 0 - 0 7 (0 15)
---------'
------------------~
~r--------------------
CS, bE assumed active C258-9
AsynchronousINIT and OE
ClK
0 0 -07 (0 15)
~"....
-----<
___
,_------1--.. , __I_·to_EZ.......·1
INITOATA
HIGHZ
INIT
HIGHZ
--------~
~--IIW--·~~
tieR
CS assumed active
3-53
C258-10
Il.
i~~C1DR
PRELIMINARY
CY7C258
CY7C259
Switching Waveforms
Single- and Double-Registered Chip Select
ClK
CS _ _ _ _ _ _ _ _-'-_ _ _...J
(ACTIVE HIGH)
Do -
D7 (D15) _ _ _ _ _ _ _ _ _--:-::::::-:-:'-::-_ _ _ _ _ _
HIGHZ
~
HIGHZ
(DOUBLE REGISTERED)
OE assumed active
C258-11
Bypassed Output Registerl9j
CLK
Ao -A1O
-------1---'
INIT
\\....._-..J/
CS, OE assumed active
C258 12
Bypassed Input and Output Register (CS and Address)
CS
(ACTIVE HIGH)
Do -
D7 (D15)
_--,tL
~
Icsv
I'--IC-SZ-::j---------
----1(,
---------~HIG~H~Z~--~I~r------~r----~*;
,-_VA_l_ID_...J7'\
DATAl
I-
VAUD
)>---~H,..,IG".H,."Z"....-OE assumed active
Note:
9.
!NIT only sets output register even though register is bypassed (for
feedback purposes).
3-54
C258 13
~
~=CYPRESS
---:-
CY7C258
CY7C259
PRELIMINARY
~, SEMICONDUCTOR
Mode Table
LAT
(7C258-CLK)
VPP
(INIT)
PGM
(CS)
Latch High Byte
VIHP
Vpp
ProgramInhibit
VILP
Vpp
Program Enable
VILP
Program Verify
VILP
Mode
VFY
(OE)
Do- D1S (259)
Do-D7 (258)
VIHP
VIHP
VIHPNILP
VIHP
VIHP
HI-Z
Vpp
Vu'p
VIHP
VIHPNILP
Vpp
VIHP
VILP
VOHpNoLP
II)
::iii
Programming Pinouts
o
DIP
vpp
LCC/PLCC
VFY
As
PGM
A,
LAT
D.
0,
02
AI}.
AI}.
Ao
Vee
Vss
Vss
Vee
Vss
03
0,
Vee
Vss
As
As
A7
As
As
7C258
Vee
0,
02
Vss
Vee
Vss
03
0
Ao
Ao
Vee
Vss
As
Vss
As
A7
~~~68~J
Os
D?
A,.
Do
A7
d.
As
As
Il..
AI}.
Ao
Ao
Q.
il:1~1~~
>
2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200mA
UVExposure . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7258Wsec/cm2
Operating Range
Ambient
lemperature
Vee
O°Cto + 70°C
5V± 10%
Industriam
- 40°C to + 85°C
5V± 10%
Military!2]
- 55°C to + 125°C
5V± 10%
Range
Commercial
Electrical Characteristics Over the Operating Rangd3, 4]
7C261-20
7C263-20
7C264-20
Parameters
VOH
VOL
lest Conditions
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Vee = Min.,
IOH = -2.0mA
Com'l
Vee = Min.,
IOL= 8mA
(6 mA Mil)
Com'l
Max.
2.4
7C261-25
7C263-25
7C264-25
Min.
2.4
Mil
0.4
2.0
2.0
Input mGH Level
Input LOW Level
IIX
Input Current
VeD
Input Diode Clamp Voltage
loz
Output Leakage Current
VOL~ VOUT ~ VOH,
Output Disabled
- 40
+40
- 40
los
Output Short
Circuit Current[5]
Vee = Max.,
VOUT=GND
- 20
- 90
- 20
lee
Power Supply Current
Vee = Max.,
VIN = 2.0V
Com'l
Ycc =
Com'l
0.8
-10
Programming Supply Voltage
Ipp
Programming Supply
Current
VIHP
Input mGH Programming
Voltage
VILP
Input LOW Programming
Voltage
V
0.4
V
+10
2.0
0.8
-10
V
0.8
V
-10
+10
rtA
+40
- 40
+40
rtA
- 90
- 20
- 90
mA
120
mA
40
mA
+10
Note 4
120
120
Mil
Max.,
CS~ VIH
140
40
40
Mil
lOUT = OmA
Vpp
Units
0.4
VIL
Standby Supply
Current (7C261)
Max.
2.4
0.4
VIH
ISB
Min.
2.4
Mil
GND ~ VIN ~ Vee
Max.
7C261-30
7C263-30
7C264-30
50
12
13
12
50
3.0
13
13
V
50
mA
3.0
3.0
0.4
12
50
0.4
V
0.4
V
Notes:
1.
2.
3.
See tbe Ordering Information section regarding iodustrial temperature range specification.
TA is the "instant on" case temperature.
See tbe last page of this specification for Group A subgroup testing information.
4.
5.
3-60
See tbe "Introduction to CMOS PROMs" section ofthe Cypress Data
Book for general infromation on testiog.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
CY7C261
CY7C263/CY7C264
7M~PRF5S
F
SEMlCONDUClDR
Electrical Characteristics
Over the Operating Rangef3, 4](continued)
7C261-35
7C263-35
7C264-35
Parameters
VOH
VOL
Description
Min.
Test Conditions
Max.
Output HIGH
Voltage
Vee = Min.,
IoH = - 4.0 rnA
Com'l
2.4
Mil
2.4
Output LOW
Voltage
Vee = Min.,
IoL= 16 rnA
Com'l
0.4
Mil
0.4
Vrn
Input HlGH Level
VIL
Input LOW Level
7C261-40
7C263-40
7C264-40
Min.
Max.
7C261-45, 55
7C263-45,55
7C264-45, 55
Min.
Max.
2.4
2.4
Units
V
2.4
0.4
2.0
2.0
0.8
-10
0.4
V
0.4
2.0
0.8
-10
V
-10
+10
!JA
IIX
Input Current
Veo
Input Diode Clamp
Voltage
Ioz
Output Leakage
Current
VOL 5 VOUT 5 VOH,
Output Disabled
- 40
+40
-40
+40
- 40
+40
!JA
los
Output Short
Circuit Current[5]
Vee = Max.,
VOUT = GND
-20
-90
- 20
- 90
- 20
-90
rnA
Icc
Power Supply
Current
Vee = Max.,
VJN= 2.0V
100
rnA
Standby Supply
Current (7C261)
Vee = Max., CS ~ Vrn
lOUT = ornA
ISB
Vpp
GNDSVJNSVee
+10
+10
V
0.8
Note 4
Com'l
100
Mil
120
Com'l
30
Mil
30
12
Programming
13
100
120
30
rnA
30
30
12
13
12
13
V
50
rnA
Supply Voltage
Ipp
Programming
Supply Current
Vrnp
InputHlGH
Programming Voltage
VILP
Input LOW
Programming Voltage
50
3.0
50
3.0
0.4
3.0
0.4
V
0.4
V
Capacitance [4]
Parameters
Description
CJN
InputCapacitance
CoUT
Output Capacitance
Test Conditions
TA= 25 C,f= 1 MHz,
Vee=5.0V
D
3-61
Max.
Units
10
pF
10
pF
CY7C261
CY7C263/CY7C264
.il~NDUcmR
AC'Test Loads and Waveforms!4]
Th~t Load for
-20 through -30 speeds
R1500
R1500Q
5V 3 1 ( 6 5 0
MIL)
0
OUTPUT
5V 3 1 ( 6 5 0
MIL)
0
OUTPUT
30 pF
I
INCLUDING _
JIG AND SCOPE
R2333Q
(403Q MIL)
_
-
5 pF
I
INCLUDING _
JIG AND SCOPE
(a)
R2 333Q
(4030 MIL)
'.ov~10~%
~5ns-- I-
~
10%
GND
~5ns
--
_
-
C261-5
C261-4
(b) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
RTH200n
OUTPUT ~ 2500. MIL
Thst Load for -35 through -55 speeds
R1 250Q
R1 250Q
OUTP~~31
30
PFI
INCLUDING _
JIG AND SCOPE
OUTP~~31
R2167Q
5
_
-
PF I
INCLUDING _
JIG AND SCOPE
R2167Q
_
C261-6
(d) High Z Load
(e)
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics Overthe OperatingRangel2, 3, 4]
7C261-20
7C263-20
7C264-20
Parameters
7C261-25
7C263-25
7C264-25
7C261-30
7C263-30
7C264-30
7C261-35
7C263-35
7C264-35
Max.
Units
tAA
Addressto Output Valid
20
25
30
35
us
tHZCSl
Chip Select Inactive to High Z
12
15
20
20
us
tHZCS2
Chip Select Inactive to High Z (7C261)
20
25
35
35
us
tACSl
Chip Select Active to Output Valid
12
15
20
20
us
tACS2
Chip Select Active to Output Valid (7C261)
20
25
35
40
tpu
Chip Select Active to Power-Up (7C261)
tpD
Chip Select Inactive to Power-Down (7C261)
Description
Min.
Max.
0
Max.
Min.
Max.
0
0
20
3-62
Min.
25
Min.
0
30
us
ns
35
ns
CY7C261
CY7C263/CY7C264
-=r-
~~
~.CYPRESS
-=- J!' SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangd2, 3, 4] (continued)
7C261-45
7C263-45
7C264-45
7C261-40
7C263-40
7C264-40
Description
Parameters
Min.
Max.
Min.
7C261-55
7C263-55
7C264-55
Max.
Min.
Max.
Units
tAA
Address to Output Valid
40
45
55
ns
tHZCS!
Chip Select Inactive to High Z
25
30
35
ns
tHZCS2
Chip Select Inactive to High Z (7C261)
45
45
55
ns
tACS!
Chip Select Active to Output Valid
25
30
35
ns
tACS2
Chip Select Active to Output Valid (7C261)
tpu
Chip Select Active to Power-Up (7C261)
tpD
Chip Select Inactive to Power-Down (7C261)
45
45
0
55
0
0
40
45
ns
ns
55
ns
Switching Waveforms!4]
I--
Vee
Ao- A12
ADDRESS
I---
Ipo . .
Ipu
/~ 50%
K. 50%
SUPPLY
CURRENT
~~
~
7
14- 1M
1+
IHZCS
-1
I----
......
XX
_I
///'/
-¥-
" "
Erasure Characteristics
Operating Modes
Wavelengths of light less than 4000 angstroms begin to erase the
devices in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
Read
The recommended dose of ultraviolet light for erasure is a wavelengthof2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) or 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating. the exposure time would be approximately45 minutes. The 7C261 or 7C263 needs to be within 1
inch of the lamp during erasure. Permanent damage may result if
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
lACS
C261-7
Read is the normal operating mode for a programmed device. In
this mode, all signals are normal TIL levels. The PROM is addressedwith a 13-bitfield, a chip select, (active LOW), is applied to
the CS pin, and the contents of the addressed location appear on
the data out pins.
Program, Program Inhibit, Program VerilY
These modes are entered by placing a high voltage Vpp on pin 19,
with pins 18 and 20 setto VJLI' In this state, pin 21 becomes a latch
signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW.2!2&fam (PGM)
signal and pin 23 becomes an active LOWverify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The PROG RAM mode exists when PGM is LOW, and VFY is HIGH. The
verify mode exists when the reverse is true, PGM HIGH and VFY
LOWand the program inhibit mode is enteredwithboth PGMand
VFY HIGH. Programinhibit is specificaUyprovided to allow data
to be placed on and removed from the data pins without conflict.
3-63
en
:::E
o
a:
Q.
CY7C261
CY7C263/CY7C264
1lIble 1. Mode Selection
Pin Function[6,7]
Read or Output Disable
Mode
Program
Au
NA
Au
AIO
A,
Aa
CS
0,-00
Vpp
LATCH
PGM
VFY
CS
D, -Do
VIL
07- 0 0
Read
A12
Au
AIO
~
Output Disable
A12
Au
AlO
~
As
As
Vlli
HighZ
Program
VILP
VPP
VILP
VILP
VlliP
VILP
D7- DO
ProgramInhibit
VILP
Vpp
VILP
VlliP
VlliP
VILP
HighZ
Program Verify
VILP
Vpp
VILP
VlliP
VII.P
VILP
07- 0 0
BiankCheck
VILP
VPP
VILP
VlliP
VII.P
VILP
07- 0 0
Notes:
6. X = "don't care" but not to exceed Vcc ±S%.
7.
AddressesAs-Al2 must be latched through lines Ao- Ai in programmingmodes.
DIP/Flatpack
LCC/PLCC (Opaque only)
Top View
Top View
A.,
Vee
VFV
A.,
PGM
A7
81~1~
>: d.
"' .. >-0
..:(..:(..:(
z>
~A12
LATCH
A,lAl1
OS
A,,/A'2
AslA11
AojA,o
Vpp
~A10
A,IAs
NA
AoIA.,
Do
0,
D.
D,
D.
D:!
D,
GND
0.
4 3 2 1 11 282726
25
5
24
6
7C261
7
23
8
22
21
9
7C263
20
10
19
11
12131415161718
>
AoIA., >
NC
Do >
A,IAs
0
LATCH
OS
Vpp
NA
NC
0,
o.
C261-9
C281-8
Figure 1. Programming Pinouts
Programming Information
Programmingsupport is available from Cypress as well as from a
number of third-party software vendors. For detailed programminginformation, including a listing of software packages, please
see the PROM Programming Informationlocated attheendofthis
section. Programming algorithms can be obtained from any Cypressrepresentative.
3-64
CY7C261
CY7C263/CY7C264
~:~
~- CYPRESS
~,
SEMICONDUCI'OR
1.ypical DC and AC Characteristics
NO~ZEDACCESS
NORMALlZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORNUUJZEDSUPPLYCURRENT
VS. SUPPLY VOLTAGE
1.6
1.2
1.2
w
::;:
01.4
.E
cw
N
::J
./
1.2
..:
::;:
/"
a: 1.0
az
O.S
./
V
~
j
a
5.0
O.S.I::---~=-----:-!.
6.0
5.5
-55
leo
1.6
!zw
~
1.4
en
en
w
~
cw
N
::J
..:
::;:
1.2
1.0
a: O.S
v----
L-----
w
1£
25
125
AMBIENTTEMPERATURE ('G)
125
r--....
40
30
10
a
0
......
o
1.0
'"'"
2.0
3.0
4.0
175
....... !----
~ 125
a
100
z
75
!3
50
~~
a
'"
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
...,...V'
a:
25
J
1/
Vee = 5.0V
TA =25'C
/
0.0
-
I
17
o
1.0
2.0
3.0
OUTPUT VOLTAGE
3-65
.s
20.0
~
15.0
~
10.0
~
I'-.
.s 150
!z
1ii
I
4.5
5.0
5.5
6.0
~CALACCESST~ECHANGE
~
OUTPUT VOLTAGE M
~
0.4
4.0
25.0
"
AMBIENT TEMPERATURE ('C)
2001V static discbarge
• 5V ±10% Vee, commercial and
military
• Slim 2S-pin, 300-mil plastic or bermeticDIP
The CY7C265 is a 8192 x 8 registered
PROM. It is organized as 8,192 words by
8 bits wide, and has a pipeline output register. In addition, the device features a
programmable initialize byte that may be
loaded into the pipeline register with the
initialize signal. The programmable initialize byte is the 8,193rd byte in the
PROM and its value is programmed at
the time of use.
Packaged with 28 pins, the PROM has 13
address signals (Au through Al;V, 8 data
out signals (00 through 07), ElI (enable
or initialize), and CLOCK.
CWCK functions as a pipeline clock,
loading tbe contents of the addressed
memory location into the pipeline register
on each rising edge. The data will appear
on the outputs if they are enabled. One
pin on the CY7C265 is programmed to
perform either the enable or the initialize
function.
If the asynchronous enable (£) is being
used, the outputs may be disabled at any
time by switching the enable to a logic
HIGH, and may be returned to the active
state by switching the enable to a logic
Ww.
If the synchronous enable (Es) is being
used, the outputs will go to the OFF or
high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If
the synchronous enable pin is switched to
a logic Ww, the subsequent positive
clock edge will return the output to the
active state. Following a positive clock
edge, the address and synchronous enable
inputs are free to change since no change
in the output will occur until the next
WW-to-H1GH transition of the clock.
This unique feature allows the CY7C265
decoders and sense amplifiers to access
the next location while previously addressed data remains stable on the
outputs.
Logic Block Diagram
Pin Configurations
DIP/F1atpack
Top View
A,.
A,
Ao
Vee
A,.
A,.
A,.
As
As
A"
A,.
A,.
A,:,
A"
A,.
A,.
PROGRAMMABLE
ARRAY
A.
A,
ADDRESS
DECODER
A.
COLUMN
MULnPLEXER
8-BIT
EDGE-
T:':ir':'
A,:,
GND
FIE••I
CLK
GND
GND
A,
00
Ao
00
As
1---+-1>-0.
0,
A.
A,
I---1H:>- 0,
A,:,
Ao
L.._-'LJ',,"__
0.
0.
Os
Os
O.
GND
00
Ao
LCCIPLCC (Opaque Only)
Top View
mrr~.--------
CLK
__
Ao A,:,
~
---O............--\2001V
(per MIL-SlD-883, Method 3015)
Latch-Up Current ....••.••.••..•....•....... >200 rnA
Operating Range
Ambient
1emperature
O·Cto +70°C
Range
Vee
5V±10%
Commercial
Industria111]
- 40°C to +S5°C
5V±10%
Militart2]
- 55·Cto +125°C
5V±10%
Note:
1. Contact a Cypress representative for industrial temperature range
specifications.
2.
TA is the "instant on" case temperature.
Electrical Characteristics Over the Operating Range(3)
7Cl6S-15
Parameters
Description
= Min., IOH = - 2.0 rnA
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee =Min.,IOL =S.OrnA Com'l
VIH
Input mGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
Ioz
Output Leakage Current
7C26S-18
7C26S-25
Min. Max. Min. Max. Min. Max. Units
Test Conditions
2.4
2.4
I
Vee =Min.,IoL =6.0rnA I Mil
0.4
0.4
0.4
0.4
2.0
2.0
2.0
0.8
V
2.4
0.4
0.8
V
V
0.8
V
GND < VIN < Vee
-10
+10
-10
+10
-10
+10
GND~ Vour~ Veo
-40
+40
-40
+40
-40
+40
!lA
!lA
Output Disabled
= Max., Your .. GND
Vee =Max., lour =ornA I Com'l
IOS[4]
Output Short Circuit Current Vee
90
90
90
rnA
Icc
Vcc Operating Supply
Current
120
120
120
rnA
140
140
Vpp
Programming Supply Voltage
Ipp
ProgrammingSupplyCurrent
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
I Mil
12
13
12
50
3.0
12
13
V
50
rnA
3.0
3.0
0.4
3-69
13
50
0.4
V
0.4
V
o
a:
Q.
s:~
CY7C265
~;~croR
Electrical Characteristics Over the Operating Range[3] (continued)
7C265-40
Parameters
Description
7C26S-50
2.4
2.4
2.4
VOH
Output HIGH Voltage
Vcc = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vc:c = Min., IoL = 12.0rnA Com'l
Vm
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND.:5. VIN.s Vee
-10
+10
-10
+10
Ioz
Output LeakageCurrent
GND.:5. VOUT.:5. Vee,
Output Disabled
-40
+40
-40
+40
IOS[4]
Output Short Circuit Current
Vee = Max., VOUT = GND
lee
Vee Operating Supply
Current
Vee = Max., lOUT = 0 rnA Com'l
I
Vee = Min., IOL = S.OrnA I Mil
0.4
0.4
2.0
ProgrammingSupply Voltage
ProgrammingSupply Current
Vrnp
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
12
0.4
V
O.S
V
-10
+10
-40
+40
J.LA
J.LA
O.S
90
90
90
rnA
100
SO
SO
rnA
120
100
LMil
Ipp
V
2.0
O.S
I
V
0.4
0.4
2.0
Vpp
7C265-60
Min. Max. Min. Max. Min. Max. Units
'lest Conditions
13
12
13
50
3.0
3.0
12
50
13
V
50
rnA
3.0
0.4
0.4
V
0.4
V
Capacitance [5]
Parameters
CIN
CoUT
Description
'lest Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
10
pF
Vcc=5.0V
10
pF
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
5.
Units
Max.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
AC Test Loads and Wavefonns
'lest Load for -15 through -25 speeds
R1500
R15000
5v~(6580MiQ
OUTPUT
5v~(6580MiI)
'.ov~
OUTPUT
30 pF
I
INCLUDING _
JIG AND SCOPE
R23330
(4030 Mil)
_
-
5 pF
_
C265-4
(b) High Z Load
(a)
Equivalent to:
I
INCLUDING _
JIG AND SCOPE
R2 3330
(4030 Mil)
THEVENIN EQUIVALENT
RTH 2000 (2500 Mil)
OUTPUT ~ 2.0V
3-70
GND
5.5ns-
10~
I-
~
10%
-
5.5ns
C265-5
•- ,aPRESS
,
CY7C265
SEMICONDUCIDR
AC Test Loads and Waveforms (continued)
lest Load for -40 through -55 speeds
R1250Q
R1250Q
OUTP~~31
30
PFI
INCLUDING _
JIGAND SCOPE
OUTP~~31
R2167Q
_
-
5
R2167Q
_
-
U)
:E
oa::
C265-6
(d) High Z Load
(c)
Equivalent to:
pF I
INCLUDING _
JIG AND SCOPE
a..
THEVENIN EQUIVALENT
RTH1000
OUTPUT ()---'WI,---() 2.0V
Switching Characteristics Over the Operating Rangel3,5j
7C265-15
Parameters
Description
Min.
Max.
7C265-18
Min.
Max.
7C265-25
Min.
Max.
Units
tAS
Address Set-Up to Clock
15
18
25
ns
tHA
Address Hold from Clock
0
0
0
ns
teo
tpw
Clock Pulse Width
12
15
15
ns
tSES
Es Set-Up to Clock (Sync. Enable Only)
12
15
15
ns
tHES
Es Hold from Oock
5
5
5
tm
INIT to Output Valid
tRI
INIT Recovery to Clock
12
12
12
Clock to Output Valid
15
15
20
18
15
ns
25
ns
ns
20
15
ns
20
ns
tpWI
INIT Pulse Width
tcos
Output Valid from Clock (Sync. Mode)
12
15
20
ns
tHZC
Output Inactive from Clock (Sync. Mode)
12
15
20
ns
tnoE
Output Valid from E LOW (Async. Mode)
12
15
20
ns
tHZE
Output Inactive from E HIGH (Async. Mode)
12
15
20
ns
7C265-40
Parameters
Description
Min.
Max.
7C26S-50
Min.
Max.
7C265-60
Min.
Max.
Units
tAS
Address Set-Up to Clock
40
50
60
tHA
Address Hold from Oock
0
0
0
teo
Clock to Output Valid
tpw
Clock Pulse Width
15
20
20
ns
tSES
Es Set-Up to Clock (Sync. Enable Only)
15
15
15
ns
tHES
Es Hold from Clock
5
5
5
tm
INIT to Output Valid
tRI
INIT Recovery to Clock
20
25
25
tpWI
INlTPulse Width
25
35
35
tcos
Output Valid from Clock (Sync. Mode)
20
25
tHZC
Output Inactive from Clock (Sync. Mode)
20
tnoE
Output Valid from E LOW (Async. Mode)
tHZE
Output Inactive from E HIGH (Async. Mode)
25
20
25
3-71
ns
ns
25
35
ns
ns
35
ns
ns
ns
ns
25
25
25
20
25
25
ns
20
25
25
ns
ns
~
~~PRESS
~, SEMICONDucroR
CY7C265
Switching Waveform
ADDDRESS
SYNCHRONOUS
ENABLE
(PROGRAMMABLE) _ _ _"
CLOCK
OUTPUT
IDDE
ASYNCHRONOUS INIT
(PROGRAMMABLE)
ASYNCHRONOUS
ENABLE
C265-7
Erasure Characteristics
Bit Map Data
Wavelengths of lighl less than 4000 angstroms begin to erase the
7C265 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity. exposure time) or 25 Wsec/cmz. For an ultraviolet lamp with a 12
m w/cffi2 power rating the exposure time would be approximately
45 minutes. The 7C265 needs to be within one inch of the lamp
during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time.
7258 Wsec/cmz is the recommended maximum dosage.
Programmer Address (Hex.)
RAM Data
Decimal
Hex
Contents
0
0
Data
8191
8192
8193
IFFF
2000
2001
Data
INITByte
Control Byte
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronousinitialize
Programming Modes
The 7C265 offers a limited selection ofprogrammed architectures.
Programmingthese features should be done with a single 10-mswide pulse in place of the intelligent algorithm, mainly because
these features are verifiedoperationaJIy, not with the VFY pin.Architectureprogrammingisimplementedbyapplyingthesupervoltage to two additional pins during programming. In programming
the 7C265 architecture, Vpp is applied to pins 3, 9, and 22. The
choice of a particular mode depends on the states of the other pins
during programming, so it is important that the condition of the
otherpins be met as set forth in the mode table. The considerations
that applywithrespectto power-up and power-down duringintelligent programming also apply during architecture programming.
Once the supervoltages have been established and the correct logic states exist on the other device pins, programming may begin.
Programming is accomplished by pulling PGM from HIGH to
LOW and then back to HIGH with a pulse width equal to 10 ms.
1llble 1. Mode Selection
Pin Function
Read or Output Disable
A12
Au
AlO - A7
At;
A12
Au
AIO -A7
At;
As
As
A,j- A3
Other
A,j-A3
A2
Read
A12
An
AlO - A7
~
As
A2
Asynchronous Enable Read
A12
An
AlO- A7
~
As
Synchronous Enable Read
AIZ
Au
AlO- A7
~
As
A4- A3
A4- A3
A4- A3
Mode
3-72
A2
Az
Az
CY7C265
Table 1. Mode SelectioD (coDtinued)
PiD FunctioD
Bead or Output Disable
Au
Au
AI8 -A7
~
A5
Other
Au
Au
All -A7
~
A5
Asynchronous Initialization Read
Alz
An
AIO- A7
As
Program Memory
Au
An
AIO- A7
Program Verify
AIZ
An
AIO - A7
A6
A6
A6
A6
VllIP
Vpp
Mode
As
As
Program Inhibit
Alz
An
Alo- A7
Program Synchronous Enable
VllIP
VllIP
AIO - A7
Program Initialize
VU2
VllIP
AIO- A7
VllIP
Vpp
Program Initial Byte
AIZ
VII.P
AIO - A7
VllIP
Vpp
As
At- A3
At- A3
A4- A 3
A4- A 3
A4- A3
A4- A 3
A4- A 3
A4- A 3
A4- A 3
Az
Az
Az
Az
Az
Az
VllIP
VIl2
VIl2
PiD FunctioD
Program Verify
Al
Program Inhibit
Al
At
Au
Au
Au
Au
Au
Au
Au
Au
Program Synchronous Enable
Vpp
Mode
Read or Output Disable
Al
Other
Al
Read
Al
AsynchroDous Enable Read
Al
Synchronous Enable Read
Al
Asynchronous Initialization Read
Al
Program Memory
Al
GNU
CLK
GND
E,I
PGM
CLK
Vpp
D7- Do
VIL
VUJVllI
VIL
07- 0 0
VIL
07- 0 0
VIL
VIL
VIL
VUJVIH
VIL
VIL
WV
HighZ
HighZ
HighZ
HighZ
VIl2
VILP
07- 0 0
VIL
07-00
VIL
07- 0 0
VIHP
Vpp
07- 0 0
07- 0 0
VIHP
VILP
VIl2
Vpp
VIHP
VILP
VIHP
Vpp
HighZ
VILP
VIl2
VILP
VllIP
Vpp
07- 0 0
Program Initialize
Vpp
VILP
VIl2
VILP
VllIP
Vpp
07- 0 0
Program Initial Byte
Vpp
VllIP
VILP
VILP
VllIP
Vpp
07- 0 0
LCCIPLCC (Opaque Only)
D1P/Flatpaci<
,..,A7
,..,
Ao
Ao
Ao
PGII
CLK
Ao
~
...,
Do
0.,
0,
Do
0"
"-
9
22
21
A,.
A"
A,.
Vpp
NA
20 IIF'i'
Ao 10
Do 111213141516171lii< 0.,
NA
Ao
Do
0
CLK
v...
IIF'i'
4 32c\282726
25
24
23
Ao
A,.
A"
A12
...,
GND
U~J(~U .
,..,vee
3
o8'~.fd'.rcf
C265-9
Do
C265-8
Figure 1. Programming Pinout
Programming Information
ming information, including a listing of software packages, please
Programming support is available from Cypress as welI as from a
number of third-party software vendors. For detailed program-
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
3-73
II)
::IE
o
a:
Do
8 :;~PRFSS
~,
CY7C265
SEMICONDUCTOR
lYpical DC and AC Characteristics
NO~ZED SUPPLY CURRENT
NORMAUZED SUPPLY CURRENT
SUPPLY VOLTAGE
VS. AMBIENT TEMPERATURE
VS.
1.6
1.2
<"
1.1
a:
a:
I-
Z
Jl1.4
0
w 1.2
~
«
::;;
Icc
a: 1.0
0
z
0.8
V
0.6
4.0
V
V
./
0
~
w
:::)
0
0
w
N
~
W
1.0
0
a:
::;;
0
0
TA = 25°C
f=MAX.
4.5
5.0
5.5
SUPPLY VOLTAGE M
(I)
0.9
:::)
0.8
-55
NO~ZEDACCESS~
:::)
0
25
125
AMBIENT TEMPERATURE (0 C)
<"
~
125
::;;
~
o
..,-
1.0
~ ~
~
"" 0.8
a:
o
Z
0.6
-55
25
125
AMBIENT TEMPERATURE (0C)
a:
75
5
50
o
25
1i5
~
~
o
0.0
i'o...
""
1.0
2.0
3.0
OUTPUT VOLTAGE M
25.0
w
5 100
~
...........
10
4.0
30.0
175
Z
r-.....
TYPICAL ACCESS ~ CHANGE
.§. 150
1.2
"'
vs. OUTPUT LOADING
w
::;; 1.4
i=
fllw
,
20
VS.
r;; 1.6
!z
ll!
.......
30
OUTPUT SINK CURRENT
OUTPUT VOLTAGE
vs. AMBIENT TEMPERATURE
.s
~
40
I0..
I-
6.0
50
:::)
a:
Z
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
VS.
.§. 60
/'
i= 20.0
,.....
(I)
(I)
w 15.0
/
/
1/
o
0.0
1.0
~
~
:...J
w
Vcc=5.0V
TA = 25°C
2.0
3.0
OUTPUT VOLTAGE M
3-74
V
0
0
4.0
10.0
5.0
V
/
200
400
V
/
Vcc=4.5V TA = 25°C
j"
I
600 800 1000
CAPACITANCE (pF)
=-:-~
CY7C265
_ ' j ; CYPRESS
_
JF
SEMICONDUCTOR
Ordering Information
Speed Icc
(ns)
15
18
(rnA)
120
120
140
25
40
140
100
Ordering Code
CY7C265 -15DC
type
CY7C265-15JC
J64
CY7C265 -15PC
P21
CY7C265 -15WC
CY7C265 -18DC
W22
80
175
60
80
100
D22
CY7C265-18JC
D22
J64
CY7C265-18PC
P21
CY7C265 -18WC
W22
CY7C265-18DMB
CY7C265-18LMB
D22
CY7C265 -180MB
CY7C265-18WMB
064
W22
CY7C265-25DC
D22
CY7C265-25JC
CY7C265-25PC
CY7C265-25WC
J64
P21
W22
CY7C265-25DMB
D22
CY7C265-25LMB
L64
CY7C265-250MB
064
W22
CY7C265-25WMB
CY7C265-40DC
CY7C265-4OJC
50
Package
Operating
Range
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VIL
Commercial
IJX
Ioz
Icc
Military
ISB
L64
D22
Switching Characteristics
Parameters
Commercial
Military
CY7C265-40PC
P21
W22
CY7C265-50DC
CY7C265-5OJC
D22
J64
CY7C265-50PC
P21
CY7C265-50WC
W22
CY7C265-50DMB
CY7C265-50LMB
D22
L64
CY7C265-500MB
CY7C265-50WMB
064
W22
CY7C265-60DC
D22
CY7C265-6OJC
J64
P21
CY7C265-60PC
CY7C265-60WC
W22
CY7C265-60DMB
D22
CY7C265-60LMB
L64
CY7C265-600MB
CY7C265-60WMB
064
W22
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
teo
7, 8, 9, 10, 11
tpw
7,8,9, 10, 11
tSES
7, 8, 9, 10, 11
tHES
7,8,9, 10, 11
tcos
Document#: 38-0OO84-C
tAS
tHA
Commercial
J64
CY7C265-40WC
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Commercial
Military
Commercial
Military
3-75
•
II)
:E
o
a:::
a.
CY7C266
CYPRESS
SEMICONDUcrOR
Features
• CMOS for optimum speed/~r
• Windowed for reprogrammability
• Hlghspeed
-20 ns (commercial)
-25 ns (military)
• Lowpower
-660 mW (commercial)
-770 mW (military)
• Super low standby power
- Less than 85 mW when deseleeted
• EPROM technology 100%
programmable
• 5V :1:10% Vee, commercial and
military
8192 X 8 PROM Power
Switched and Reprogrammable
• TfL..c:ompatible I/O
• Direct replacement for 27C64
EPROMs
Functional Description
The CY7C266 is a high-performance
8192 word by 8 bit CMOS PROM. When
deselected, the CY7C266 automatically
powers down into a low-power standby
mode. It is packaged in a 600-mil-wide
package. The reprogrammable packages
are equipped with an erasure window;
when exposed to UV light, these PROMs
are erased and can then be reprogrammed The 'memory cells utilize proven EPROM f1oating-gate technology and
byte-wide intelligent programming algorithms.
The CY7C266 is a plug-in replacement for
EPROM devices. The EPROM cell requires only 12.5V for the super voltage
and low-current requirements allow for
gang programming. The EPROM cells
allow for each memory location to be
tested 100%, as each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each PROM is
also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading is acromplished byplac..!!!g an active WW signal on 1:m and CE. The
coritents of the memory location addressed by the address lines (Au through
Ala> will become available on the output
lines (00 through 0,).
Pin Configurations
Logic Block Diagram
CerDiP
0.
Top View
Vee
1
Vee
Vee
4
At
At
A,!
PR0GRAMMA8LE
ARRAY
Oe
lor
At
At
Ao
At
At
MULTIPLEXER
Oe
NC
A,
At
0.
00
0,
Oz
OND
0"
A,O
An
Oz
0,
00
:==~=r--------------------~
C2G6-1
C2G6-3
Selection Guide
Maximum Access Time (ns)
Maximum 3Serating
Current(mA:
Maximum Standby
Current (mA)
Commercial
Military
Commercial
Military
7CU6-20
7CU6-2S
7066-35
7C266-45
7C266-55
20
120
25
35
100
45
100
120
15
15
55
100
120
15
15
120
140
15
15
15
3-76
15
.:SP
~~PRF.SS
~_., SEMlCONDUClDR
CY7C266
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... -55°Cto+125°C
Supply Voltage to Ground Potential
(Pin28toPinI4) ....................... -0.5Vto+7.0V
DC Voltage Applied to Outputs
inHighZState ........................ -0.5Vto+7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
DC Program Voltage .............................. 14.0V
Static Discharge Voltage ........................ > 2001V
(per MIL-SID-883, Method 3015)
Latch-UpCurrent ............................ > 200 rnA
UVExposure ............................ 7258Wsec/cm2
Operating Range
Ambient
Thmperature
Range
Commercial
IndustriaIl.1]
O°Cto +70°C
Vee
5V± 10%
-4O°Cto +85°C
5V± 10%
Militaryf2]
- 55°C to +125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel3, 4]
7C266-20
Parameter
VOH
Description
Output HIGH Voltage
Min.
Thst Conditions
Vee = Min., IOH
=-
2.OrnA Com'l
7C266-25
Max.
Min.
2.4
2.4
Mil
VOL
Output LOW Voltage
Vee
= Min., IOL = 8.0 rnA
Vee = Min., IOL = 6.0 rnA
Vrn
Input HIGH Voltage
VlL
Input LOW Voltage
Max.
Units
V
2.4
Com'l
0.4
0.4
Mil
V
0.4
2.0
2.0
0.8
-10
V
+10
fAA
IIX
Input Current
Veo
Input Diode Clamp
Voltage
loz
Output LeakageCurrent
VOLS VOUT S VOH,
Output Disabled
-40
+40
- 40
+40
fAA
los
Output Short
CircuitCurrent[S]
Vee = Max., VOUT = GND
-20
- 90
-20
- 90
rnA
Icc
Power Supply Current
Vcc = Max., VIN
loUT = ornA
120
rnA
ISB
Standby Supply Current
-10
V
0.8
GNDSVINSVee
+10
Note 4
= 2.0V,
Com'l
120
140
Mil
Chip Enable Inactive,
lOUT = ornA
Com'l
CE~ Vrn,
Notes:
1. Contact a Cypress representative regarding industrial temperature
rangespecification.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Mil
4.
5.
3-77
15
15
rnA
15
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general infromation on testing.
For test purposes, not more than one output at a time sbould be
shorted. Short circuit test duration should not exceed 30 seconds.
•
I I)
:::E
o
a:
a..
CY7C266
Electrical Characteristics
Over the Operating Range[3, 4] (continued)
7C266-35
Description
Parameter
Thst Conditions
7C266-45
Min. Max. Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output WWVoltage
Vee = Min., IOL = 16.0 rnA
Vrn
Input HIGH Voltage
VIL
Input WW Voltage
2.4
2.4
2.0
0.8
GND~VIN~Vee
IJX
Input Current
Veo
Input Diode Clamp
Voltage
loz
Output LeakageCurrent
-10
+10
0.4
2.0
0.8
-10
V
2.4
0.4
0.4
2.0
7C266-55
Max. Min. Max. Units
+10
V
0.8
V
-10
+10
JlA
Note 4
VOL~ VOUT ~ VOH,
-10
+10
-10
+10
-10
+10
JlA
- 20
- 90
- 20
- 90
- 20
-90
rnA
100
100
rnA
120
120
Output Disabled
los
Output Short
Circuit Current[S]
Vee = Max., VOUT = GND
lee
Power Supply Current
Vee = Max., VIN = 2.0V,
lOUT = ornA
Com'l
Chip Enable Inactive,
CE? Vrn, lOUT = 0 rnA
Com'l
ISB
Standby Supply Current
100
Mil
Mil
15
15
15
15
15
Capacitance [4]
Parameters
V
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
3-78
Max.
Units
10
pF
10
pF
rnA
~~
J;;
•
F
CY7C266
CYPRESS
SEMICONDUCfOR
AC Test Loads and Waveforms
Thst Load for - 20 through -25 speeds
R1 500
R1 5000
OUTP~~~(65ag
MIL)
I
30 pF
INCLUDING _
JIG AND SCOPE
OUTP~~31(65agMIL)
R2 3330
(403Q MIL)
_
-
I
5 pF
INCLUDING _
JIGAND SCOPE
(a)
,OV~ 90%
GND
R23330
(4030 MIL)
~
10%
10%
.$.5ns--
I-
--
_
-
.$.5ns
C266-5
(b) High Z Load
THEVENIN EQUIVALENT
RTH 200 n
OUTPUT Q---'iM,---O 250n MIL
Thst Load for -35 through -55 speeds
R12500
R12500
OUTP~~~
30
PFI
INCLUDING _
JIG AND SCOPE
OUTP~~31
R21670
5
_
-
PF I
INCLUDING _
JIG AND SCOPE
R21670
_
-
C266-6
(d) High Z Load
(c)
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics OvertheOperatingRangel.1, 2, 4]
7C266-20
Parameters
Description
tAA
Address to Output Valid
tHZCE
Chip Enable Inactive to High Z
tHZOE
tAOE
7C266-25
7C266-35
7C266-45
Min. Max. Min. Max. Min. Max. Min.
20
25
35
7C266-55
Max. Min. Max. Units
45
55
ns
ns
25
30
40
45
55
Output Enable Inactive to High Z
12
15
20
25
25
ns
Output Enable Active
to Output Valid
12
15
20
25
25
ns
55
ns
tACE
Chip Enable Active to Output Valid
tOHA
Data Hold from Address Change
tpu
Chip Enable Active to Power-Up
25
30
40
45
55
ns
tpD
Olip Enable Inactive to Power-Down
25
30
40
45
55
ns
25
30
3
3
3-79
o
a::
a.
C266-4
I
Equivalent to:
(I)
:!:
45
40
3
3
ns
3
CY7C266
EPROM is exposed to high-intensity UV light for an extended
period of time.
7258 Wseclcm'}. is the recommended maximum dosage.
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
devices in the windowed package. For this reason, an opaque label should be placed over the window if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose ofultravioIet light for erasure is a wavelength of2537 angstroms for a minimum does (UV intensity multiplied by exposure time) or 2S Wsec/cm'}.. For an ultraviolet lamp
with a 12 mW/cm'}. power rating, the exposure time would be approximately 35 minutes. The CY7C266 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
Programming Modes
Programming support is available from Cypress as well as from a
number of third party software veDdors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
1Bble 1. Mode SelectloD
PiD FunclioDL6. 7J
Normal OperatioD
Read
As
At
PmI
At.!
Standby
X
X
Mode
Ai
'WY
Pnlllram
Output Disable
A18
Au
Au
~
"OE
LA.T
NA
NA
t:'!E
Vpp
0,-0.
AlO
An
All
VIL
VIL
0,
X
X
X
Vrn
X
'Ili-8tated
'Ili-8tated
00
As
At.!
AIO
Au
All
VIL
Program
VUiP
VII..P
VIl.P
VII..P
Vu'p
VII..P
Vrn
Vpp
Program Verify
VU.P
VUiP
VILP
VIl.P
VILP
VII..P
Vpp
0,-00
Program Inhibit
VUiP
VUiP
VII..P
VIl.P
VILP
VII..P
Vpp
'Ili-8tated
BIankCheck
VILP
VUiP
VILP
VII..P
VILP
VII..P
Vpp
07- 0 0
Notes:
6.
0,-0,
X = "dont't care" but must not e.xceed Vee + 5%.
7.
Address Aa - Al2 must be latched through linesAo mingmodes.
CerDlP
ThpView
NC
NA
A,
At
At
Ao/A,.
LCC/PLCC
ThpView
Vpp
NC
NC
Vf!V
5
i
NA
""Au
Iv,IA,.
Vpp
A,/At
llE
AdAt
Do
0,
!AT
0,
De
De
Da
"-
Vas
~dl~$$~
PmI
10
II
~ 3 2,\323130
~
07C266
i
24
VI'V
PGIiI
NA
NC
Vpp
!AT
23 llE
12
22
13
21
14151617181920
0,
De
tS'8'~~tS'cJr!r
Da
C266-8
C266-7
Figure 1. Pnll!rBmming Pinout
3-80
0,-00
Ai in Program-
---=--.
.
~
~.a CYPRESS
CY7C266
_ , SEMlCONDUCfOR
'lYPical DC and AC Characteristics
NORNUUUZEDACCESST~E
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORNUUUZEDSUPPLYCURRENT
vs. SUPPLYVOLTAGE
1.6
vs. SUPPLY VOLTAGE
1.2
1.2
w
:;
,,1.4
.!:?
aw
N
:::;
~
a:
0
./
1.2
/
1.0
z
0.8
/'
V
V
a
I:!j
5.0
~
oZ
0.8 '::------,1-::------..1
-55
25
125
AMBIENTTEMPERATURE (0C)
6.0
5.5
NORMALIZED ACCESS TIME
vs. TEMPERATURE
f=
w
()
1.6
1.4
«
1.2
~
1.0
()
a
w
~
a: 0.8
~
!
60
!zw
50
~
0
z
0.6
- 55
25
125
5
10
1=
o::J
0
-
o
1.0
2.0
3.0
OUTPUT VOLTAGE M
;;: 175
z
./
125
./
G 100
l<:
Z
75
5
50
5
25
en
1=
""
4.0
-
/
J
Vee = 5.0V
TA =25°C -
/
V
o
0.0
"..
I
1.0
2.0
3.0
OUTPUT VOLTAGE M
3-81
15.0
5.0
OUTPUTS~CURRENT
ll!
6.0
V
20.0
/
~ 10.0
vs OUTPUT VOLTAGE
.sr-- 150
~
~
""'" r-.... ......... r-....
AMBIENTTEMPERATURE (OC)
a:
5.5
SUPPLY VOLTAGE M
~
'i'...
::J
20
5.0
25.0
30
@
I
4.5
30.0
()
w
~
0.4
4.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
r-....
4.0
II)
:::E
o
IX
Q.
TA = 25°C
OUTPUT SOURCE CURRENT
vo.VOLTAGE
a:
~ 40
L..-----
--
"" 0.6
a:
SUPPLY VOLTAGE M
gj
-...-....;
~ 0.8
a
a:
·f
4.5
r-- r--
()
oz
TA = 25°C
f = fMAX
"..
0.6
4.0
w
:;
f=
~ 1.0
Jll.l 1---'~--t---------1
V
.....V
Vcc=4.5V _
TA= 25°C
·1
I
V
200
./
V
400
600
800 1000
CAPACITANCE (pF)
CY7C266
Ordering Information[8]
Speed
(ns)
20
25
35
45
55
CY7C266-20DC
Package
1YPe
D16
CY7C266-20PC
PIS
Ordering Code
CY7C266-20WC
W16
CY7C266- 25DC
D16
CY7C266-25PC
PIS
CY7C266-25WC
W16
CY7C266-25DMB
D16
CY7C266-25LMB
L55
CY7C266-25QMB
Q55
CY7C266-25WMB
W16
CY7C266-35DC
D16
CY7C266-35PC
PIS
CY7C266-35WC
W16
CY7C266-45DC
D16
CY7C266-45PC
PIS
CY7C266-45WC
W16
CY7C266-45DMB
D16
CY7C266-45LMB
L55
CY7C266-45QMB
Q55
CY7C266-45WMB
W16
CY7C266-55DC
D16
CY7C266-55PC
PIS
CY7C266-55WC
W16
CY7C266-55DMB
D16
CY7C266-55LMB
CY7C266-55QMB
L55
Q55
CY7C266-55WMB
W16
MIUTARY SPECIFICATIONS
Group A Subgroup Testing
Operating
Range
DC Characteristics
Commercial
Parameters
VOH
VOL
Vrn
VIL
Commercial
IJX
loz
Icc
ISB
Military
Commercial
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Commercial
Parameters
Subgroups
tAA
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
tAOE
tACE
Document #: 38-00086-C
Military
Commercial
Military
Notes:
8. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and prodnct availability.
3-82
CY7C268
CY7C269
CYPRESS
SEMICONDUCTOR
8192 x 8 Registered
Diagnostic PROM
Features
Functional Description
• CMOS for optimum speed/power
• Highspeed
-1S-ns max set-up
-12-ns clock to output
The CY7C268 and the CY7C269 are 8192
x 8 registered diagnostic PROMs. Th~y
are both organized as 8,192 words by 8 bIts
wide and they have both a pipeline output
register and an onboard diagnostic shift
register. Both devices feature a programmable initialize byte that may be loaded
into the pipeline register with the initialize
signal. The programmable initialize byte is
the 8,193rd byte in the PROM, and may be
programmedto any desired value.
The CY7C268 has 32 pins and features full
diagnostic capabilities while the CY7C269
provides limited diagnostics and is available in a space-efficient 28-pin package.
This allows the designers to optimize designs for either board-area efficiency with
the CY7C269, or combine the CY7C268
with other diagnostic products using the standard interface.
CY7C268
• Lowpower
- 660 mW (commercial)
-770mW (military)
• On-chip edge-triggered registers
- Ideal for pipelined microprogrammed systems
• On-chip diagnostic shift register
- For serial obsenability and controlability of the output register
• EPROM technology
-100% programmable
- Reprogrammable (7C269W)
• 5V :t10% Vee, commercial and
military
• Capable of withstanding >2001V static discharge
• Slim 300-mil, 28-pin plastic or hermetic DIP (7C269)
The full standard feature diagnostics of the
and SDO (shift in
CY7C268 utilize the
and shift out), MODE, and DCLK signals.
These signals allow serial data to be shifted
into and out of the diagnostic shift register at
the same time the pipeline register is used
for nonna! operation. The MODE signal is
used to control the transfer of the information in the diagnostic register to the pipeline
register, or the data on the output bus into
the diagnostic register. The data on the output bus may be provided from the pipeline
register or from an external source.
When the MODE signal is Ww. the
PROM operates in a normal pipeline
mode. The contents of the addressed
memory location are loaded into the pipeline register on the rising edge of PCLK.
the outputs are enabled with the ENA signal either synchronously or asynchronously, depending on how the device is configuredwhen programmed. If programmed
forasynchronous enable, ENA WW enables the outputs. If confignred for synchronous enable, ENA WW will enable
the outputs synchronouslywith PCLKduring the rising edge of PCLK. ENA
sm
The CY7C268 provides 13 address signals
(Ao through fuzb. 8 data out signals (00
through 07), ENA (enable), PCLK (pipeline clock) and INIT(initialize ) for control.
Pin Configurations
Logic Block Diagram
CerDIP/FIatpack
"lOp View
As
As
2
Pv,
4
As
Pv,
A,
A,
SOO
0,
As
0,
Ou
0.
0.
00
0,
0.
0.
02
GNO
O.
0.
O.
GNO
00
As
Ou
LCC/PLCC (Opaque OnIY)LCC/PLC~Opaque Only)
Top Vi~
"lOp I~
~ 'f~J<:?~ If
4 3 2L113231~
5
6
7
8
9
AlO
28
7C26B
27
0
26
25
3-/13
fuL
ENA
INIT
NC
A'2
SDI
SOO
24
10
23
11
12
22
~ 13
21 )0,
14151617181920
o d'~6' rJ (f(f
C268· 1
00
C26B-3
U:tJ<-9:t:t
NC
OCLK
PCLK
A,
SOl
0268-2
OCLK
(7C288)
SOO
MO~
A'2
EJEs. f
MODE
CLOCK
As
SOl
As
AlO
Al1
As
As
NC
0,
EA
As
As
A'2
SOl
SOO
PCLK
(7C269)
CLOCK
(7C269)
PCLK
(7C268)
ENA
(7C268)
INIT~L-_"""
(7C268)
vee
As
As
A7
A'D
A"
ENA
INIT
A2
MODE
NC
OCLK
MODE
CerDIP/Flatpack
"lOp View
Vee
As
As
A7
'"
As
5
A2
MODE
CLOCK
A,
6
C268-4
As
Ou
4 3 2 L11 282726
25
7C269
7
8
9
10
0
24
23
22
21
20
11121314151617113
AlO
Al1
A'2
EtEs.f
SOl
SOO
0,
o8'~6'8(!J(f
'"
C268-5
U)
~
oa:
a.
CY7C268
CY7C269
Functional Description (continued)
cru:1r:
mGH will synchronously disable the outputs
the rising
edge of PCLl{. The asynchronous initialize signal,
, transfers
the initialize byte into the pipeline register on a mGH to LOW
transition. rnlTLOW disables PCLK and must transition back to
a HIGH in order to enable PCLK. DCLK shifts data into SOl
and out of SDO on each rising edge.
When MODE is HIGH, the rising edge of the PCLK signal loads
the pipeline register with the contents of the diagnostic register.
Similarly, DCLK, in this mode, loads the diagnostic register with
the information on the data output pins. The information loaded
will be either the contents of the pipeline register if the outputs
are enabled, or data on the bus if the outputs are disabled (in a
high-impedance state).
CY7C269
The CY7C1fj9 is optimized for applications that require diagnostics in a minimum amount of board area. Packaged in 28 pins, it
has 13 address_siBnals (Au through AlU, 8 data out signals (00
through 07). FJI (Enable or Initialize). and CLOCK (pipeline
and diagnostic clock). Additional diagnostic signals consist of
MODE. SOl (shift in) and SDO (shift out). Normal pipelined operation and diagnostic operation are mutually exclusive.
When the MODE signal is LOW, the 7C269 operates in a normal
pipelined mode. CLOCK functions as a pipeline clock, loading
the contents of the addressed memory location into the pipeline
register on each rising edge. The data will appear on the outputs
if they are enabled. One pin on the 7C1fj9 is programmed to perform either the Enable or the Initialize function. If the M pin is
used for a 1NIT ( asynchronous initialize) function. the outputs
are permanently enabled and the initialize word is loaded into
the pipelinellQ~ter on a HIGH to LOW transition of the 1NIT
signal. The
LOW disables CLOCK and must return high to
re-enable CLOCK. If the M pin is used for an enable signal. it
may be programmed for either synchronous or asynchronous operation. This enable function then operates exactly the same as
the 7C268.
When the MODE si8!!al is HIGH, the 7C1fj9 operates in the
diagnostic mode. The M signal becomes a secondary mode signal designating whether to shift the diagnostic shift register or to
load either the diagnostic register or the pipeline register. IfPjl is
HIGH. CLOCK performs the function of DCLK, shifting SOl
into the least-significant location of the diagnostic register and all
bits one location toward the most-significant location on each rising edge. The contents of the most-significant location in the
diagnostic register are available on the SDO pin.
If the M signal is LOW, SOl becomes a direction signal, transferring the contents of the diagnostic register into the pipeline
register when SOl is LOW. When SOl is mGH, the contents of
the output pios are transferred into the diagnostic register. Both
transfers occur on a LOW to HIGH transition of the CLOCK. If
the outputs are enabled, the contents of the pipeline register are
transferred into the diagnostic register. If the outputs are disabled, an external source of data may be loaded into the diagnostic register. In this condition, the SDO signal is internally driven
to be the same as the SOl signal, thus propagating the "direction
of transfer information" to the next device in the string.
Selection Guide
7C269-15
7C269-18
Maximum Set-Up Time (ns)
15
18
25
Maximum Clock to Output (us)
12
15
20
Maximum Operating Current (mA)
I
7C269-25
120
120
140
140
7C268-40
7C269-40
7C268-SO
7C269-SO
7C268-60
7C269-60
Maximum Set-Up Time (ns)
40
50
60
Maximum Clock to Output (us)
20
25
25
100
80
80
120
100
I
Maximum Operating Current (mA)
I
I
Commercial
Military
120
Commercial
Military
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines. not tested.)
Storage 'Thmperature ................. - 65· C to + 150· C
Ambient 'Thmperature with
Power Applied ...................... - 55·Cto +125·C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
UV Exposure ........................... 7258 Wsec/cm2
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883. Method 3015)
Latch-Up Current ..•...••....•...••......... >200 mA
Operating Range
3-84
Range
Ambient
Temperature
Commercial
Industrial!l)
O·Cto +70·C
Vee
5V:!: 10%
- 4O·C to +85·C
5V:!: 10%
Militaryl2)
- 55·Cto +125·C
5V:!: 10%
CY7C268
CY7C269
-,~
~.cypRF.SS
~_.!II' SEMICONDUClDR
Electrical Characteristics
Over the Operating Rangd3, 4]
7C269-1S
Parameters
Description
Thst Conditions
7C269-18
7C269-2S
Min. Max. Min. Max. Min. Max. Units
2.4
2.4
2.4
V
VOH
Output HIGH Voltage
Vee = Min.,loH = - 2.0 mA
VOL
Output LOW Voltage
Vee = Min., 10L = 8.0mA Com'l
0.4
0.4
0.4
Vee=Min.,loL=6.0mA Mil
0.4
0.4
0.4
VIH
Input HIGH Voltage
VIL
Input WW Voltage
I
I
2.0
2.0
2.0
0.8
0.8
V
V
0.8
V
IJX
Input Load Current
GND.$. VIN.$. Vee
-10
+10
-10
+10
-10
+10
loz
Output LeakageCurrent
GND.$. VOUT .$. Vee.
Output Disabled
-40
+40
-40
+40
-40
+40
!LA
!LA
IOS[5]
Output Short Circuit Current
Icc
Vee Operating Supply
Current
VPP
Ipp
ProgrammingSupply Voltage
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
Parameters
Vee = Max.,loUT=OmA lCom'l
90
90
mA
120
120
mA
140
140
IMil
12
Programming Supply Current
Description
90
120
13
12
50
3.0
13
3.0
0.4
Thst Conditions
Output HIGH Voltage
Vee = Min.,loH = - 2.0mA
VOL
Output LOW Voltage
Vee = Min., 10L = 12.0mA Com'l
2.4
I
Vee = Min., 10L = 8.0mA I Mil
0.4
2.4
2.4
0.4
0.4
0.4
2.0
2.0
IJX
Input Load Current
GND.$. VIN.$. Vee
-10
+10
-10
+10
loz
Output LeakageCurrent
GND.$. VOUT.$. Vee,
Output Disabled
-40
+40
-40
+40
los
Output Short Circuit Current
Vee = Max., VOUT = GND
Vee Operating
Supply Current
Vee = Max., lOUT = 0 mA Com'I
Input LOW Programming
Voltage
2.0
0.8
I
I Mil
12
Programming Supply Current
VILP
0.8
3-85
V
-10
+10
"":'40
+40
!LA
!LA
90
90
mA
80
80
mA
120
100
13
12
13
12,
50
3.0
0.4
5.
V
0.8
90
3.0
4.
V
100
50
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
V
V
0.4
Input LOW Voltage
Input HIGH Programming
Voltage
0.4
0.4
Input HIGH Voltage
VIHP
V
0.4
VIL
Programming Supply Voltage
V
mA
3.0
VIH
VPP
Ipp
13
50
7C268-40
7C268-S0
7C268-60
7C269-S0
7C269-40
7C269-60
Min. Max. Min. Max. Min. Max. Units
VOH
lee
12
50
13
V
50.
mA
3.0
0.4
V
0.4
V
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
•
U)
:e
oa:
a.
CY7C268
CY7C269
L:::Z
~, ~~NDUCIDR
Capacitance[4,6]
Parameters
Description
InputCapacitance
OutputCapacltance
CIN
LoUT
'Thst Conditions
TA-25°C,f-1MHz,
Vee = 5.0V
Max.
10
10
Units
pF
pF
Note:
6. Thstedinitially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
'Thst Load for -15 through - 25 speeds
R1500
R15000
OUTP~~31(658Q
MIL)
I
OUTP~~31(658Q
MIL)
R2 333Q
(403Q MIL)
30 pF
INCWDING _
JIG AND SCOPE
_
-
(a)
Equivalent to:
I
R2333Q
5 pF
(403Q MIL)
INCWDING _
_
JIG AND SCOPE
C268-6
(b) HighZLoad
C266-7
I
THEVENIN EQUIVALENT
RrH200n
o-----wv---o
OUTPUT
250.0. MIL
'Thst Load for -40 through -60 speeds
R12500
R12500
OUTP~~31
OUTP:'31
30
PFI
INCWDING _
JIG AND SCOPE
R2167Q
5
_
-
PF I
INCLUDING _
JIG AND SCOPE
(c)
R2167Q
_
-
C266-8
(d) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics Over the Operating Rangel3,4]
7C269-15
Min.
Max.
15
7C269-18
Min.
Max.
18
7C269-25
Min.
Max.
25
Parameters
tAS
Description
Address Set-Up to Clock
tHA
Address Hold from Clock
tea
Clock to Output Valid
tpw
Clock Pulse Width
12
15
15
ns
tsES
Es Set-Up to Dock (Sync Enable Only)
12
15
15
ns
4rns
Es Hold from Clock
5
5
5
tm
INIT to Out Valid
tru
INIT Recovery to Dock
12
15
20
tpW!
INIT Pulse Width
12
18
25
teas
Output Valid from Clock (Sync. Mode)
12
15
20
ns
tHZS
Output Inactive from Dock (Sync. Mode)
12
15
20
ns
tDOE
Output Valid from ELOW (Asynch. Mode)
12
15
20
ns
tHZE
Output Inactive from E HIGH (Async. Mode)
12
15
20
ns
0
ns
20
15
18
15
3-86
0
0
12
Units
ns
ns
ns
25
ns
ns
ns
CY7C268
CY7C269
£..:~
==-:= CYPRESS
,
SEMICONDUClDR
Switching Characteristics Over the Operating Rangef3,4] (continued)
7C268-40
7C269-40
Parameters
Description
Min.
Max.
7C268-S0
7C269-S0
Min.
7C268-60
7C269-60
Max.
Min.
Max.
Units
tAS
Address Set-Up to Clock
40
50
60
tHA
Address Hold from Clock
0
0
0
teo
Clock to Output Valid
tpw
Clock Pulse Width
15
20
20
ns
tsES
Es Set-Up to Clock (Sync Enable Only)
15
15
15
ns
tHES
Es Hold from Clock
5
5
5
ns
tm
INIT to Output Valid
20
25
25
ns
ns
25
35
35
ns
ns
tRI
INIT Recovery to Clock
20
25
25
ns
tPWI
INITPuise Width
25
35
35
ns
tcos
Output Valid from Clock (Sync. Mode)
20
25
25
tHZS
Output Inactive from Clock (Sync. Mode)
20
25
25
ns
tOOE
Output Valid from E LOW (Asynch. Mode)
20
25
25
ns
tHZE
Output Inactive from E mGH (Async. Mode)
20
25
25
ns
ns
Diagnostic Mode Switching Characteristics Over the Operating Rangef3,4]
tssm
Description
Set-Up SDI to Clock
tHsm
SDI Hold from Clock
tosoo
SDO Delay from Clock
tOCL
Minimum Clock LOW
toCH
Minimum ClockmGH
tSM
Set-Up to Mode Change
tHM
Hold from Mode Change (7C269)
tMS
ModetoSDO
tss
SDIto SDO
tso
DataSet-Up to DCLK
tHO
Data Hold from DCLK
Parameters
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
7C269-1S
Min. Max.
20
0
7C268-40,SO,liO
7C269-2S 7C269-40,SO,liO
Min. Max. Min. Max. Min.
Max. Units
7C269-18
25
25
0
0
25
25
20
20
25
25
25
25
25
25
0
0
20
20
0
20
10
25
25
10
13
3-87
30
35
0
0
25
30
25
25
25
25
25
30
0
0
25
25
35
35
30
20
25
30
0
0
ns
30
40
25
25
25
25
25
30
0
0
25
30
10
15
ns
ns
ns
ns
ns
25
30
40
45
25
30
40
40
25
30
10
13
ns
ns
ns
ns
ns
I/)
~
oa:
a.
CY7C268
CY7C269
'Vt~NDucroR
Switching Waveforms!3,4]
Pipeline Operation (Mode
=0)
ADDDRESS ______________- J
SYNCHRONOUS
ENABLE
PROGRAMMABLE _ _...J
PCLK/CLOCK
(7C269)
---4-./
OUTPUT
IOOE
ASYNCHRONOUS
ENABLE _ _ _ _ _- '
C268-10
Diagnostic Waveform for the 7C268
DCLK
SDI
SDO
MODE
PCLK
OUTPUT
C268-9
3-88
CY7C268
CY7C269
~
.~
~=CYPRESS
_ .r
SEMICONDUCTOR
Switching Waveforms [3,41 (continued)
Diagnostic Application for the 7C269 (Shifting the Shadow Registerl81)
CLOCK
•
MOOE
In
::::!E
oa::
SOO
a.
SOl
Eli
C26B-12
Diagnostic Application for the 7C269 (Parallel Data lransfer)
CLOCK
MOOE
SOl
SOO
Eli
Noles:
7. Asynchronous enahle mode only.
8. Diagnostic register = shadow register = shift register.
9.
3-89
The mode transition to mGH latches the asynchronous enable state.
If the enable state is changed and held before leaving the diagnostic
mode (mode H • L) then the output impedance change delay is tMS.
CY7C268
CY7C269
Programming Modes
Bit Map Data
Procrammer Address (Hex.)
RAM Data
Dedmal
Hex
Cooteutll
0
0
Oata
8191
8192
8193
1FFF
Oata
Init Byte
Control Byte
2000
2001
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize (CY7C269 only)
Table 1. CY7C2t18 Mode Selection
Pin Function11UJ
As
As
A4 -A3
Al
A4-~
Al
Al
As
A,j -A3
Al
As
A,j-A3
As
A,j-A3
As
A,j-A3
Aa
Aa
Aa
Aa
AIO-A,
A6
A6
A6
A6
A6
As
A,j-A3
Az
Al
Au
AIO -A,
~
As
A,j-A3
Aa
Al
AIZ
Au
AIO - A,
A6
AS
A,j-A3
A2
Al
Program Memory
Al2
Au
AIO -A,
~
As
A,j-A3
Az
Al
Program Verify
Al2
Au
AIO -A,
As
A,j-A3
Az
Al
Program Inllibit
Al2
Vrnp
Au
AlO -A,
A6
A6
A,j-A3
Az
Al
VUIP
AlO -A,
VUIP
As
Vpp
A,j-A3
VIHP
Vpp
X
VILP
AIO-A,
VUIP
Vpp
A,j-A3
VILP
Vpp
Read or Output Disable
At
MODE
DCLK
PCLK
SOl
SOO
Other
At
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
PGM
DCLK
PCLK
NA
VFV
E, Es. I
Vpp
07- 00
07- 0 ,
Program Synchronous Enable
VILP
Program Initial Byte
Vrnp
Read or Output DiAbie
Au
Au
Ale - A7
~
Other
Au
Au
All -A,
~
Read
Ala
Au
AIO -A,
Load SR to PR
An.
Au
AIO -A,
Load Output to SR
AIZ
Au
AIO -A,
ShiftSR
AIZ
Au
AlO-A,
Asynchronous Enable Read
Ala
Au
Synchronous Enable Read
AIZ
Asynchronous Initialization Read
Mode
Program Synchronous Enable
Program Initial Byte
Al
Al
Al
Al
Pin Function11UJ
Mode
Read
Load SR to PR
Load Output to SR
ShiftSR
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
Program Verify
Program Inllibit
VIL
X
Vu./VIH
X
SOO
VIL
0,- 00
VIH
VIL
VIl}\'IH
X
SOl
X
0,-00
VIH
VlljVIH
VIL
VIL
SOl
VIH
07- 00
X
07- 0 0
VIH
VIlJVIH
VIL
OIN
SOO
VIL
VIL
X
VIL
SOO
VIL
07- 00
VIL
VIL
Vu./VIH
VIL
SOO
VIL
07- 0 0
VIL
X
VIL
SOO
VIL
07- 00
VIHP
Vpp
07- 0 0
VIL
VII.P
VILP
VILP
Vu
VIHP
VILP
VII.P
VILP
VILP
Vpp
VIHP
VILP
VILP
VILP
VIHP
Vpp
07-00
HighZ
VII.P
VILP
Vu
VII.P
VIHP
Vpp
07- 0 0
VIHP
Vpp
07- 0 0
VILP
3-90
VILP
VII.P
VII.P
i! ::::z
~=CYPRF.SS
~F
CY7C268
CY7C269
SEMICONDUCTOR
Thble 2. CY7C269 Mode Selection
Pin FunctionlLUJ
~-A3
Az
~
As
As
~-A3
Az
Al
AlO- A7
At;
A5
~-A3
A2
Al
Read or Output Disable
A12
Au
AIO - A7
~
Otber
A12
Au
AIO - A7
Read
A12
Au
Mode
Al
Load SRto PR
AI2
Au
AlO- A7
At;
A5
~-A3
A2
Al
Load Output to SR
A12
Au
AlO- A7
At;
A5
~-A3
A2
Al
ShiftSR
AI2
All
AlO- A7
At;
A5
~-A3
A2
Al
Asynchronous Enable Read
AI2
All
AlO- A7
At;
A5
~-A3
A2
Al
Synchronous Enable Read
A12
Au
AlO- A7
At;
A5
~-A3
A2
Al
AsynchronousInitializationRead
A12
Au
AlO- A7
At;
A5
~-A3
A2
Al
ProgramMemory
A12
Au
AlO- A7
At;
A5
~-A3
A2
Al
Program Verify
A12
Au
AlO- A7
At;
A5
~-A3
A2
Al
ProgramInhibit
Al2
Au
AlO- A7
At;
A5
~-A3
A2
Al
Program Synchronous Enable
Vrnp
Vrnp
AlO- A7
Vrnp
Vpp
~-A3
Vrnp
Vpp
ProgramInitialize
VILP
Vrnp
AlO-A7
Vrnp
Vpp
~-A3
VILP
Vpp
Program Initial Byte
AI2
VILP
AIO-A7
Vrnp
Vpp
~-A3
VILP
Vpp
Ao
Ao
MODE
Pin FunctionlLUJ
Read or Output Disable
Mode
Other
Read
LoadSRtoPR
VIL
sm
SDO
E,I
0,-00
NA
VFY
Vpp
n, -Do
VnJVrn
X
HighZ
VIL
07- 0 0
sm
sm
VIL
07- 0 0
VIL'
07- 0 0
SDO
VIH'
07- 0 0
HighZ
Va
0,-00
07- 0 0
VIH
VnJVrn
VIL
Vrn
VnJVrn
Vrn
Vrn
VnJVrn
VIL
VIL
DIN
X
VIL
VnJVrn
X
HighZ
VI!:-,
VIL
VIL
X
HighZ
VIL
07- 0 0
VILP
VILP
X
Vrnp
Vpp
D7- DO
VIHP
VILP
X
VILP
Vpp
07- 0 0
Vrnp
VILP
X
VIHP
Vpp
HighZ
VILP
VILP
VILP
X
VIHP
Vpp
D,-Do
ProgramInitialize
VILP
VILP
VILP
X
VIHP
Vpp
D, '- Do
Program Initial Byte
Vrnp
VILP
VILP
X
VIHP
Vpp
D,-Do
Load Output to SR
ShiftSR
Asynchronous EnabJe Read
Synchronous Enable Read
AsynchronousInitializationRead
ProgramMemory
Program Verify
ProgramInhibit
Program Synchronous Enable
Note:
10. X
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
PGM
CLK
CLK
~
"don't care" but not to exceed Vcc ±S%.
3-91
•
II)
::iE
o
a:
D.
CY7C268
CY7C269
CerDIP/FIatpack
A7
Po.,
CerDIP/Flatpack
vee
A7
Po.,
Po.,
Po.,
A10
A"
A,;/Vpp
Pv,
As
,.,.
PGM
NC
NA
NA
A,;/Vpp
Pv,
Ao
NA
Vpp
,.,.As
PGM
Vpp
NC
NA
NA
A'2
A,
VFY
Ao
D7
D.
D,
D,
D.
C268-13
Do
D,
D2
GND
D7
D,
D,
D,
D.
C268-15
Do
D,
vD2
__
LCC/PLCC (Opaque Ouly)
As 5
~6
NC
NA
NA
7
8
9
A,Npp
1~
Ao
12
Do
7C268
o
AoNpp
A,o
Al1
A'2
NA
VFY
A1Npp
Vee
Po.,
LCC/PLCC (Opaque Only)
A10
A"
NA
A,O
Al1
A'2
Vpp
NA
VFY
D7
Vpp
NC
A'2
~
D7
C268-16
C268-14
Figure 1. Programming Pinouts
3-92
CY7C268
CY7C269
~~
_'iECYPRESS
-=:F
SEMlCONDUCfOR
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBffiNT TEMPERATURE
NO~ZEDSUPPLYCURRENT
1,6
vs. SUPPLY VOLTAGE
1.2
01.4
.2
w 1,2
N
~
«
::;;
cr
az
Icc
1.0
V
0.8
/
Cl
W
N
~
V
0.6
4.0
4.5
5.0
W
1.0
U
cr
0.9
NO~ZEDACCESSTllWE
vs. AMBffiNTTEMPERATURE
« 175
1.6
::;;
i= 1.4
U
~
./
1.2
~
::;;
cr 0.8
0.6
/'
-55
150
z
w
~
125
~
/
Z
Cii
75
~
50
a
25
I!:
:::J
25
125
o
0.0
125
AMBIENT TEMPERATURE (0C)
o
1.0
" '"
2.0
3.0
""
4.0
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TllWE CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
30.0
25.0
u; 20.0
B100
/
Cl
w
N 1.0
az
S
I-
CIJ
CIJ
W
""'" ""'-
20
AMBIENT TEMPERATURE (OC)
SUPPLY VOLTAGE (V)
w
25
a
•
',,-
~ 10
D..
:::J
0.8
-55
6.0
30
:::J
aCIJ
I-
5.5
i'..
U
cr
TA = 25°C
f= MAX.
50
w
::;;
az
IZ
cr
cr
:::J 40
.2
/
Cl
60
S
0 1.1
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
«
/
0.0
/
V
./
V
.? 15.0
~w
V
10.0
/
Cl
5.0
Vcc=5.0V
TA = 25°C
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
3-93
4.0
./
V
.s
/
200
Vcc=4.5V
TA= 25°C
400
600
-
600 1000
CAPACITANCE (pF)
C266-17
CY7C268
CY7C269
~-:z
~=CYPRESS
~, SEMlCOlIDUCTOR
Ordering Information[ll]
Icc
Speed
(ns)
(mA)
40
100
50
80
120
60
80
100
Ordering Code
CY7C268-40DC
CY7C268-40WC
CY7C268-50DC
CY7C268-50WC
CY7C268-50DMB
CY7C268-50LMB
CY7C268-50QMB
CY7C268-50WMB
CY7C268-60DC
CY7C268-60WC
CY7C268-60DMB
CY7C268-60LMB
CY7C268-60QMB
CY7C268-60WMB
Package
'JYpe
D20
W20
D20
W20
D20
L55
Q55
W20
D20
W20
D20
L55
Q55
W20
Operating
Range
Commercial
Icc
Speed
(n.)
(mA)
15
120
18
120
Commercial
Military
140
Commercial
MilitaI)'
25
140
Notes:
11. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product avail-
ability.
40
100
50
80
120
60
80
100
3-94
Ordering Code
CY7C269-15DC
CY7C269-15PC
CY7C269-15WC
CY7C269-18DC
CY7C269-18PC
CY7C269-18WC
CY7C269-18DMB
CY7C269-18LMB
CY7C269-18QMB
CY7C269-18WMB
CY7C269-25DC
CY7C269-25LC
CY7C269-25PC
CY7C269-25QC
CY7C269-25WC
CY7C269-25DMB
CY7C269- 25LMB
CY7C269-25QMB
CY7C269-25WMB
CY7C269-40DC
CY7C269-40PC
CY7C269-40WC
CY7C269-50DC
CY7C269-50PC
CY7C269-50WC
CY7C269-50DMB
CY7C269-50LMB
CY7C269-50QMB
CY7C269-50WMB
CY7C269-60DC
CY7C269-60PC
CY7C269-60WC
CY7C269-60DMB
CY7C269-60LMB
CY7C269-6OQMB
C7C269Y -60WMB
Package Operating
'JYpe
Range
D22
Commercial
P21
W22
Commercial
D22
P21
W22
Military
D22
L64
Q64
W22
Commercial
D22
L64
P21
Q64
W22
D22
L64
Q64
W22
022
P21
W22
022
P21
W22
D22
L64
Q64
W22
D22
P21
W22
D22
L64
Q64
W22
MilitaI)'
Commercial
Commercial
Militaty
Commercial
Military
--
CY7C268
CY7C269
~~PRESS
~; SEMICONDUCIDR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vm
VIL
IJX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
Icc
IsB
•
II)
:E
o
a:
a.
Switching Characteristics
Parameters
Subgroups
tAS
tHA
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9,10,11
teo
tpw
tSES
tHES
teos
Diagnostic Mode Switching Characteristics
Parameters
Subgroups
tssm
tHSDI
tDSDO
tDCL
tDCH
tHM[12]
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tMS
tss
Notes:
12. 7C269 only.
Document#: 38-00069-C
3-95
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• O.8-micron CMOS for optimum speed!
power
• High speed
- 28 ns single access time
-14 ns burst access time
Reprogrammable 16K X 16
Processor-Specific PROM
• 100% reprogrammable in windowed
packages
• TTL-compatible I/O
• Capable ofwitbstanding greater than
2OO1V static dlsdlarge
FunctionalDe~ption
•
•
•
•
16-bit-wide words
Input Address Registered or Latched
On-cbip Programmable Burst Logic
Programmable compatiblIltywitb
many common microprocessors
• Three programmable c:bip selects
• Programmable output enable
• 44-pin PLCC and 44-pln LCC
packages
CY7C270
The CY7C270 is a 16K-word by 16-bit
PROM designed to support a number of
popular microprocessors witb little or no
"glueD logic. This PROM is packaged in a
44-pin PLCC package and a 44-pin LCC
package. The CY7C270 is available in
windowed packages for 100% reprogrammability. The memory celis utilize proven
EPROM floating-gate technology.
The CY7C270 offers a number of programmable features tbat allow the user to
configure the PROM for use with tbeir
chosen microprocessor. The programmable features include a choice between
registered and latched modes of operation. The CY7C270 also has an on-board
programmable counter for burst reads.
The user may select a 2-bit, 4-bit, or 8-bit
linear counter, or program tbe PROM to
use tbe Intel 80486 burst patte-
OE
0,
Do
C27Q.,
Selection Guide
3-96
PRELIMINARY
Pin Configuration
LCClPLCC (Opaque Only)
lbpVlew
J!J~d~ ~~I!l ~ri~
0,.
Ott
0,.
Do
Do
V..
Vee
Dr
Do
Do
D.
8
9
10
11
12
13
14
15
16
17
85432,1,4443424140
39
38
37
38
0
CY7C27O
35
34
33
32
31
Single Read Access in Latehed Mode
In latched mode, the CY7C270 can take advantage of situations
where the address is available well before the rising edge of eLK.
A read is initiated when the latch is opened (on the falling edge
ofm). The address is sent directly to the PROM core and to the
counter. The contents of the memory location addressed by the
original address are delivered to the outputs. The latch is closed
is deasserted.
when
Burst Sequence
During a burst, the first read is initiated as a single access read.
After the initial read, the
input is held inactive. The advance
enable input (AIW) controls the address sequencing starting
with the second read. AI5V is sampled on the rising edge of the
CLK input. HAI5V is sampled LOW, the address is incremented
to the next location. The number of address bits incremented by
the counter is programmed by the user. The counter wraps
around after reachiogthe maximum count without affecting other
bits in the address.
Special burst advancement logic is included in the CY7C270 to
support the Intel 80486 burst operation. The 80486 bursts in the
non-sequential pattern shown in 711b1e 2.
Some processors have the capability to suspend a burst. In order
to suspend a burst in the CY7C270 the processor must simply
deassert the ADV input. When the ADV input is reasserted the
burst will continue from where it left off. It is not necessary for
the processor to send a new address to the PROM.
rn
A,.
At.
At,
A,.
rn
Ae
V..
v..
Ae
A7
30 C Ae
29
18 19 20 21 22 23 24 25 26 27 29
CY7C270
Ae
Operating Modes
The CY7C270 can be configured for use with many popular microprocessors. The PROM configuration for some of these processors is detailed in 711b1e 1. Note that many of the processors
can use either registered or latched mode depending on their
speed.
Thble 2. Look.Up Dible for Use with Intel 486
Thble 1. Processor.Specific PROM Configuration
Processor
SPARC
Intel 486
Registered/Latched
-
Second
Address
Third
Address
Fourth
Address
A,.
A,.
Ax+
A,.
A,,+l
Thble Logid1J
A,. + 1
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
0
Registered
Latched
First
Address
Burst Counter
80386
Latched
-
Motorola 68040
Latched
2-Bit Counter
1
1
Motorola 68030
Latched
2-Bit Counter
Intel 80960KB
Registered
2-Bit Counter
Intel 80960CA
Latched
2-Bit Counter
8-Bit Counter
AMD29000
Latched
MIPSR3000
Registered
MIPSR2000
Registered
-
Motorola 88000
Registered
2-Bit Counter
Ax+
1
1
Application Example 1
ClK
ClK
Notes:
1. The Intel 486 uses a non-sequential burst The CY7C270 is equipped
with a look-up table (described in 7hble 2) for use with this processor.
Intel
49S
ms 1----.-1 0;:
DATA
ADR
DATA
ADR
cs"
cs,
Single Read Access In Registered Mode
A read access is initiated in registered mode on the rising edge of
CLK if all three chip selects are asserted and
is sampled
LOW. The address applied to the input is stored in a register and
is delivered to both the PROM core and the counter. The contents of the memory location accessed by the original address are
delivered to the outputs. When rn is asserted the system ignores
the advance enable (ADV) input.
rn
3-97
oSa
1lR
DE
80486 Instruction Memory Using 1Wo CY7C270s
A"
II)
~
o
a::
a.
'71~NDU~
PRELIMINARY
Application Example 2
CY7C270
Pin Definitions
Signal Name
A13
CLK
CLK
IE
IREQ
INST
ADDR
DATA
ADR
cs.
AM290110
CS,
CS.
IBREQ
CY7C270
ADV
OE
-=
-Ao
Description
I/O
I
AddressInputs
CLK
I
Clock
LE
I
Latch Enable
ADV
I
AdvanceEnable
CS2 - CSo
I
Programmable ChipSelects
OE
I
Programmable Output Enable
D1S - Do
0
Data Outputs
Vee
-
Power Supply
Vss
-
Ground
C270-4
AM29000 Instruction Memory Using 1\vo CY7C270s
Pin Descriptions
Input Signals
Au - Ao (Address lines). The address inputs are stored in a register at the rising edge of CLK if the device is programmed in registered mode. If the device is programmed in latched mode, the address inputs flow into the PROM while LE is active and are
captured at the rising edge of LE.
CLK (Clock line). The clock is used to sample the ADV input. In
registered mode, the clock is also used to sample LE, CS2 - CSo,
and the address.
LE (Latch Enable). In registered mode, this input is sampled on
the rising edge of CLK. If it is active, the address and chip selects
are stored in a register. In latched mode, the address and chip selects are latched on the rising edge of this signal.
ADV (Advance Enable). This signal is used for burst reads. IfLE is
inactive, ADV is sampled on the rising edge of CLK. If ADV is
Maximum Ratings
ww, the counter will be incremented and the next address will be
delivered to the PROM core.
C~ - CSo (Synchronous Chip Selects). The polarity of each chip
select is programmed by the user. The inputs from these pins are
storedin a register on the rising edge ofCLKinregistered mode. In
latched mode, the inputs are latched on the rising edge of LE. All
three chip selects must be active in order to select the device.
OE (Asynchronous Output Enable). The polarity of this pin is programmable. The outputs are active when OE is asserted and tristated when OE is deasserted.
Output Signals
D1S - Do (Data Outputs). Data from the array location addressed
on inputs A13 - Ao will appear on these pius. The output will be
tri-statedif the outputs are disabled or if the chip is not selected.
Operating Range
(Above which the useful life may be impaired. Foruser guidelines,
nottested.)
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to + 7 .OV
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B.OV
UVErasure ............................. 7258Wsec/cm2
Range
Commercial
Industriat2]
Militaryl3]
Ambient
Thmperature
Vee
O°Cto +70°C
5V±1O%
- 40°C to +85°C
5V±10%
- 55°Cto +125°C
5V±1O%
Notes:
2. Contact a Cypress representative for industtial temperature range
specifications.
3. TA is the "instant on" case temperature.
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . . . . .. . .. . . . . . .. . . . . . . . . . . . . >200mA
3-98
~
-.
:~
_
PRELIMINARY
. • CYPRESS
SEMlCONDUClDR
CY7C270
~F
Electrical Characteristics[4,51
CY7C270-20 CY7C270-30
CY7C270-2S CY7C270-40
Description
Parameters
lest Conditions
Min.
Max.
2.4
VOH
Output mGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output WW Voltage
Vee = Min., IOL = 8.0 rnA (6.0 rnA Mil)
VIR
Input mGH Level
Guaranteed Input Logical HIGH Voltage for All
Inputs
2.0
Vee
VIL
Input LOW Level
Guaranteed Input Logical WW Voltage for All
Inputs
-3.0
IIX
Input LeakageCurrent
GND.:'>. VIN.:'>. Vee
:....10
VeD
Input Clamp Diode
Voltage
loz
Output Leakage
Current
Vee = Max., VOL.:'>. VOUT .:'>. VOH, OutputDisabled
-.40
+40
los
Output Short Circuit
Current
Vee = Max., VOUT = O.OV[6]
~20
-90
Icc
Power Supply Current
Vee = Max., lOUT = 0.0 rnA
Min.
Max.
Units
2.4
0.4
V
0.4
V
2.0
Vee
V
0.8
-3.0
0.8
V
+10
-10
+10
JlA
-40
+40
JlA
-20
-90
rnA
(I)
Note 4
ICom'l
200
200
rnA
I Military
250
250
rnA
Shaded area contams advanced mformation.
Capacitance [41
Description
lest Conditions
Max.
Units
JnputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
10
Vec=5.0V
10
pF
pF
Parameters
CIN
CoUT
Notes:
4.
5.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
Seethe last page of this specification for Group A subgroup testing information.
6. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms
R15oo.[1
R1500.[1
OUTP~~ 3 9 ( 6 5 6 .mil)[ 1 R2 OUTP~~ 3 9 ( 6 5 6mil)
. [ 1 R2
3.0V
333.1"1
GND
3330
50 pFI
(403 mil)
5 pFI
(403.[1 mil)
5. 5 ns
ALL INPUT PULSES
90%
.D.
j~8~~~NG -=-
-=-
SCOPE
j~8~~~NG -=-
-=-
SCOPE
(b) High Z Load
(a)
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
200.[1 (250.0. mil)
2.0V
(1.9Vmil)
o-----wv---o
C27(J.7
3-99
C270·6
:E
o
a:
a.
&:~PRFSS
PRELIMINARY
~, SEMICQIDUCTOR
Switching Characteristics
Over the Operating RangelS]
CV7~-~
Parameters
CY7C270
CV7¢70"25
'Mm." Max. Mm..
Description
tcp
Clock Period
<2Il·· ..·.
25·
tCH
Clock HIGH Pulse Width
t(jP1
fer!
tCL
Clock LOW Pulse Width
. '" 2-:2.
tq;1
2"'-2.
icPf
~
.
."
.
.
CY7C270-30
CY7C270-40
Min.
Min.
Max.
"'4
Units
40
ns
tcpt
tcpt
ns
2-2
2-2
tcpt
2-2
2""2 . .
:.
4
'4'·> '.
2-:2 ..
Max.
30
tCPt
ns
2-2
5
ns
.. ;V
;I
4
4
ns
LE Set-Up to CLKRise
4'
,4
4
5
ns
tLEH
LE Hold from CLK Rise
3
4
4
ns
tLW
Latch Pulse Width
12
15
ns
tADVS
ADV Set-Up to CLK Rise
3
10
4
4
5
ns
tADVH
ADV Hold from CLK Rise
tASL
Address Set-Up to Latch Close
tAHL
Address Hold from Latch Close
3
tDH
Data Hold from CLK Rise
3.
tM
Address to Data for Single Read
tLEA
LE Low to Data Valid for Single Read
tCKA
Clock to Data for Single Read
.'
tCKB
CLK Rise to Data for Burst Read
I
tess
CS Set-Up to CLKRise
. If:
tcsH
CS Hold from CLK Rise
tcov
CLK Rise to Output Valid
tcoz
CLK Rise to High Z Output
tcsov
tcsoz
CS Asserted to Output Valid
tcsSL
CS Set-Up to Latch Close
4
tcsHL
CS Hold from Latch Close
3
twv
twz
Latch Open to Output Valid
toEV
OE Asserted to Output Valid
12
toEZ
OE Deasserted to High Z Output
12
tAS
Address Set-Up to CLKRise
tAH
Address Hold from CLKRise
tLES
ill
'
4 '.
..3
. '4
'
3
4
4
ns
4
4
5
ns
4
4
ns
3
3
3
.
3
,
28
ns
28'
35
40
ns
40
os
,
.28
28
35
'.
"':28'
28"
35
40
ns
1;1+'
19
24
30
ns
I:'
.'., .....
.4
......
4
5
.,.
.3
'.
4
4
ns
ns
12
15
18
ns
. ,112'
12
15
18
ns
115
15
18
21
ns
21
ns
'12
'.
...........•.
.....
."f."
.....
'3 .1:.
CS Deasserted to High Z Output
Latch Open to High Z Output
..
15
4
5
,3
4
4
.....
.'
15
.J5
Shaded area contams advanced information.
3-100
18
15
.4'
"
j
.....
ns
ns
15.
18
21
ns
15
18
21
ns
12
15
18
ns
12
15
18
ns
.
;~PRESS
_.F'
PRELIMINARY
CY7C270
SEMICONDUCTOR
Switching Waveforms
Single Reads - Registered Mode[7, S]
•
en
:E
oa:
a.
C270-8
Single Reads - Latched Mode[S]
VALID
0270-9
4-Word Burst Followed by Single Read - Registered Mode[S]
C270-10
Notes:
7. ADV is assumed HIGH.
8.
3-101
CSz - CSo, DE are assumed active.
~
PRELIMINARY
~-CYPRESS
~_., SEMICCtIDUCTOR
Switching Waveforms
CY7C270
(continued)
4-Word Burst Followed by Single Read - LatehedMode[8]
tcp
CLK
0270-11
Suspeuded Bursd 8, 9]
ClK
D15 - Do
_ _ _ _ _ _ _f'
0270-12
Output Controlled by CSand CLK - Registered Mode[lO]
ClK
tess --~~- tesH
INACTIVE
D15 - Do
AC IVE
______________________________t_eo_v_==:t
__~~--------------tco---z==:1
---I(
VALID
~
'------------~ HIGH Z
C27o-13
HIGH Z
Note:
9. Burst in progress.
10. OE assumed active_
3-102
PRELIMINARY
CY7C270
Switching Waveforms (continued)
Outputs Controlled by CS and LE - Latched Mode
[E----.. .
015 -
Do
INACTIVE
en
:::i
----------t:
HIGHZ
Outputs Controlled by OE[ll]
oa::
~
CS2 - CSo
£L
_ _ _ _ _ _ _ __
HIGHZ
1=
OE
ACTIVE - - - - - - - - - -....
LOW[12]
toEV=k
-----------------1(
HIGHZ
015 -
Do
-
VAlW
0270-14
t"'j.__
H_IG_H_Z
__
C270-15
Notes:
11. CS;z - CSo are assumed active.
12. OE active HIGH is a programmable option.
Erasure Characteristics
approximately 35 minutes. The 7C270 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
PROM is exposed to high intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dos-
Wavelengths of light less than 4000 Angstroms begin to erase the
CY7C270. For this reason, an opaque label should be placed over
the window if the PROM is exposed to sunlight or fluorescent
lighting for extended periods of time.
The recommended dose for erasure of ultraviolet light is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet
lamp with a 12 mW/cm2 power rating the exposure time would be
age.
Architecture Configuration Bits
The CY7C270 is configured by programming the Control Word
located at the end of the programmable arrily (4000H). 71lb1e 3
gives the specific information for configuring the architecture.
Table 3. Control Word for An:hitec:ture Configuration
Control Word
Programmed Level
Control Option
Bit
OE
Output Enable
Do
O=DEFAULT
1 = PROGRAMMED
C1 Co
(Counter Configuration)
~D1
R/L
Registered/Latched
D3
ChiP~ectO
D12
CSI
Chip Select 1
D13
00 = DEFAULT
01 = PROGRAMMED
10 = PROGRAMMED
11 = PROGRAMMED
O-DEFAULT
1 = PROGRAMMED
O=DEFAULT
1 = PROGRAMMED
0= DEFAULT
1 = PROGRAMMED
CS2
Chip Select 2
D14
O=DEFAULT
1 = PROGRAMMED
CSz Active WW
BE
(Burst Enable)
DIS
O-DEFAULT
1 = PROGRAMMED
No Borst
Burst (follow Cl Co)
3-103
Function
OEActiveWW
OE Active HIGa
486 2-Bit Counter
Linear 2-Bit Counter
Linear 4-Bit Counter
Linear 8-Bit Counter
Registered Mode
Latched Mode
<:So Active WW
<:So Active HIGH
CSI Active WW
CSI Active HIGH
CS2 Active HIGH
PRELIMINARY
BitMap
CY7C270
Table 4. Program Mode Table
Programmer Address (Hex)
0000
3FFF
4000
Vpp
PGM
VFY
Vpp
VIHP
VIHP
Do - D15
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VILP
Data
Mode
RAM Data
Data
Program Inhibit
Data
Control Word
Table 5. Configuration Mode Table
Vpp PGM VFY
Mode
Control Word (4000H - default state is OOH)
DIS
Do
BE CSz CSI CSoXXXXXXXXR/LCI CoOE
Program Inhibit
Program Control
Word
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages. please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
ver;t Control
A2
De - D15
Vpp VIlIP VIlIP Vpp
HighZ
Vpp VILP VIlIP Vpp Control Word
Vpp VIHP
Wo
Signature Mode
Device Code
J!JJ!~IJl~I~~I~ ~
85432.1.4443424140
Dlt
C'f7C%1O
9
Do 10
D.
Vss
Vee
0.
Do
Do
D.
11
12
13
14
15
18
17
0
38
38
87
88
85
34
33
32
31
30
29
18 1820 21 22 23 24 25 28 27 28
0"0040-0°
'I5>itt(°c-c""cf1)c"
Figure 1. Programming Pinout
3-104
Vpp Control Word
Table 6. Siguature Mode Table
Cypress Code
Ott
010
VILP
AtO
Att
A\1
,..
,..
""""
Ato
Vss
Vss
A7
C27Il-16
Ao
At
Do - D15
VILP
Vpp
0034H
VIlIP
Vpp
0013H
&~PRE&s
JF
PRELIMINARY
CY7C270
SEMICONDUCTOR
Ordering Information[13]
Speed
(ns)
CY7C270-20HC
Package
1YPe
H67
CY7C270-20JC
J67
CY7C270-25HC
H67
CY7C270-25JC
J67
CY7C270-25HMB
H67
CY7C270-25LMB
L67
CY7C270-25QMB
Q67
30
CY7C270-30HC
H67
CY7C270-3OJC
J67
40
CY7C270-40HC
H67
CY7C270-4OJC
J67
CY7C270-40HMB
H67
20
25
Ordering Code
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Operating
Range
Commercial
Commercial
Military
Commercial
Commercial
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
Vrn
1,2,3
VIL
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
Switching Characteristics
Military
Parameters
Subgroups
tAS
7,8,9,10,11
CY7C270-40LMB
L67
tAlI
7,8,9,10, 11
CY7C270-40QMB
Q67
tLES
7,8,9, 10, 11
tIER
7,8,9,10, 11
tADVS
7, 8, 9, 10, 11
tADVH
7, 8, 9, 10, 11
tDR
7, 8, 9, 10, 11
Shaded area contams advanced IOformation.
Note:
13. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
tCKA
7, 8, 9, 10, 11
tess
tCSR
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tCKB
7,8,9, 10, 11
tLEA
7, 8, 9, 10, 11
tOEV
7, 8, 9, 10, 11
tLW
7,8,9,10,11
tASL
7, 8, 9, 10, 11
tcssL
7,8,9, 10, 11
7, 8, 9, 10, 11
tAlIL
7, 8, 9, 10, 11
tesHL
7,8,9, 10, 11
tesov
7, 8, 9, 10, 11
twv
7,8,9,10,11
tcov
7, 8, 9, 10, 11
Document#: 38-00179-A
3-105
til
:::IE
oa:
a.
CY7C271
CY7C274
~~SS ~~~.~~~~~~~~~§§
SEMICONDUcrOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammablIity
• ffighspeed
-30 ns (commercial)
-35 ns (military)
• Lowpower
-660 mW (commercial)
-715 mW (military)
• Super low standby power
-Less tban 165 mWwben
deselected
• EPROM technology 100%
programmable
• Slim 300-mil package (7CZ71)
• Direct replacement for bipolar
PROMs
32,768 x 8 PROM Power
Switched and Reprogrammable
The CY7C271 and CY7C274 offer the advantage oflower power, superior performance, and programming yield. The
EPROM cell requires only 12.SV for the
super voltage, and low current requirements allow for gang programming. The
EPROMcellsalloweachmemorylocation
to be tested 100% because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading tbe 7C271 is accomplished by
I?!!cing active LOW signals on ~1 and
CEo and an active HIGH on CSz. Reading
the 7C274 is accom~ed by placing activeLOWsignalsonOEandm The contents of the memory location addressed by
the address lines (Ao - A14) will become
available on the au t lines (00 - 07).
• Capableofwltbstandlng >ZOOIVstatIc discbarp
Functional Description
The CY7C271 and CY7C274 are highperformance 32,768-wordEY.8-bit CMOS
PROMs. When disabled (CE IDGH), the
7C271flC274 automatically powers down
into a low-power stand-by mode. The
CY7C271 is packaged in the 300-mil slim
package. The CY7C274 is packaged in
the industry standard tiOO-mii package.
Both the 7C271 and 7C274 are available
in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When exposed to UV light, the
PROM is erased and can be reprogrammed. The memory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
Logic Block Diagram
A,.
A,.
A,.
0,
Vee
X
A"
A,.
0"
256.1024
PROORAMABLE
ARRAY
0"
""""
A7
Ae
As
OND
CE
07
A,
Ao
o.
o.
o.
0,
o.
o.
o.
o.
0"
A"
O"E
A,.
O.
0,
Ae
""
llE
07
Ao
o.
A,.
A13
1:7
26
25
CS,
CSt
A,
0-
Ae
Ae
Vee
A,.
A"
A,.
A,.
A,.
CIt
O.
o.
GND
C271-4
C271-2
As
LCC/PLCC (Opaque Only)
CIt
A,
LCCIPLCC (Opaque Only)
~;1~~11
:c::~~;;
Ao
.. 32,,323130
0,
5
Ao
At
8
26
9
26
10
24
11
23
22
12
21
13
14151817181920
Ae
00
(5
Ae
Ae
A,
Ae
NC
00
~
-
29
~
~ 3 2,,323130
A,.
A,.
A,.
Ae
Ae
CS",
Ao
AI
Ne
CSt
CE
0,
0"
0271-1
Ae
5
~
(5
-
2& Ae
~
8
26
9
25
A, 10
24
Ae 11
23
22
NC 12
21
o. 13
14151817181920
~NeO<'>"'''
At
A"
NC
O"E
A,.
llE
0,
De
00 aZ000C271_5
Selection Guide
Maximum Access Time (ns)
Maximum Operating Com'l
Current (mA)
Military
StandbyCurrent(mA) Com'l
Military
7071-30
7074-30
30
7071-35
7074-35
35
~
120
lW
130
30
13U
jlJ
40
3-106
7071-45
7074-45
45
3U
4U
7071-55
7074-55
55
lw
lJU
3u
4U
CY7C271
CY7C274
~
~~PRESS
~, SEMICONDUCTOR
Maximum Ratings
(Above which the usefullife may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65 ° C to + 150° C
Ambient Temperaturewith
Power Applied . . . . . . . .. . . . . . . . . . . . . .. - 5SoC to + 12SoC
Supply Voltage to Ground Potential. . . . . . .. - O.SV to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.SVto +7.0V
DC Input Voltage ...................... -3.0Vto +7.0V
DC Program Voltage .............................. 13.0V
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD·883, Method 301S)
Electrical Characteristics
Latch·UpCurrent ............................ >200rnA
UVExposure ............................ 7258Wsec/cm2
Operating Range
Ambient
Thmperature
Range
Commercial
O°Cto +70°C
Vee
SV±1O%
IndustriaJI]
-4O°Cto +8S0C
SV±10%
Militaryl2J
-55°Cto +12S0C
SV±10%
Over the Operating Rangel:3]
7C271-30, 35, 45, 55
7C274-30, 35, 45, 55
Parameters
Thst Conditions
Description
Min.
= - 2.0 rnA
Vee = Min., IOL = 8.0 rnA[4]
2.4
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
2.0
Input LOW Level
Guaranteedlnput Logical LOWVoltageforAll
Inputs
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
Vee = Min., IOH
Max.
Units
0.4
V
Vee
V
0.8
V
V
IJX
Input Current
GND~VIN~Vee
-10
+10
Ioz
Output LeakageCurrent
VOL ~ VOUT ~ VOH, Output Disabled
-40
+40
iJA
iJA
los
Output Short Circuit Current[5]
Vee = Max., VOUT
-20
Icc
Power Supply Current
Vee = Max., VIN
loUT = ornA
IsB
Standby Supply Current
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
= GND
= 2.0V,
Vee = Max., CS ~ VIH,
loUT = ornA
-90
rnA
Commercial
120
rnA
Military
130
Commercial
30
Military
rnA
40
12
13
V
SO
rnA
3.0
V
0.4
V
Capacitance [6]
Parameters
CIN
COUT
Description
InputCapacitance
Output CapacItance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV
Notes:
1. Contact a Cypress representative for information on industrial tern·
perature range specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group Asubgroup testing in·
formation.
4.
5.
6.
3-107
Max.
10
10
Units
pF
pF
6.0 rnA military
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Sec Introduction to CMOS PROMs in this Data Book for general in·
formation on testing.
CY7C271
CY7C274
=-r-
.~~
AC Test Loads and Waveformsl6]
R1 SOOQ
OUTP~~316SBQ
MIL
30
FI
OUTP~~316SBQ
MIL
R2333Q
(403Q MIL)
p
INCLUDING _
JIG AND SCOPE
R1 SOOQ
_
-
S
R2333Q
(403Q MIL)
P
INCLUDING _
JIGAND SCOPE
(a)
Equivalent to:
FI
ALL INPUT PULSES
~---
3.0V
GND
~90%
90%
10%
";S ns --
10%
\.-
";S ns
_
-
0271-7
0271-6
(c) Input Pulses
(b) IDgh Z Load
THEvENIN EQUIVALENT
200Q
OUTPUT 0-0---""'N","---oO 2.00V COMMERCIAL
2SOQ
OUTPUT 0-0---""'N","---oO 1.90V MILITARY
0271-8
Switching Characteristics Over the Operating Rangel3, 6]
7C271-30
7C274-30
Parameters
Description
7C271-35
7C274-35
7C271-45
7C274-45
7C271-55
7C274-55
Min. Max. Min. Max. Min. Max. Min. Max. Units
tAA
Address to Output Valid
30
35
45
55
ns
tHzCS
Chip Select Inactive to High Z (CSl and CS2, 7C271
Only)
20
25
30
30
ns
tACS
Chip Select Active to Output Valid (CSl and CS2,
7C271 Only)
20
25
30
30
ns
tHZOE
Output Enable Inactive to High Z (OE, 7C274 Only)
20
25
25
30
ns
toE
OutputEnable Active to Output Valid (OE, 7C274
Only)
20
25
25
30
ns
tHZCE
Chip Enable Inactive to High Z (CE Only)
35
40
50
60
ns
tACE
Chip Enable Active to Output Valid (CE Only)
35
40
50
60
ns
tpu
Chip Enable Active to Power Up
tpo
Chip Enable Inactive to Power Down
tOH
Output Hold from Address Change
0
0
0
40
35
0
0
tpu
~50%
Vee
SUPPLY
CURRENT
1.0 - A14
ADDRESS
50
0
Switching Waveform
0
ns
60
0
ns
ns
-
POWER DOWN CONTROLLED BY CE
C}SO%
)K:
"K:
~lAA-
~
PREVIOUS DATA VAUD
)KX K
I+-
.IK
(lHzoEl
IHzes(E) .....
DATAVAUD
I+-
...
(toEl
tAeS(E)
-1
HIGHZ / / / ' /
C271-9
Note:
7. CSzandCSl areusedonthc 7C271 only. OE is used on the 7C274only.
3-108
CY7C271
CY7C274
lamp during erasure. Permanent damage may result if the PROM
is exposed to high-intensity UV light for an extended period of
time_ 7258 Wsec/cm2 is the recommended maximum dosage.
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
7CJ..71 and 7CJ..74 in the windowed package. For this reason, an
opaque label should be placed aver the window if the PROM is
exposed to sunlight or fluorescent lighting for extended periods
of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity x exposure time) or 25 Wsec/cm'1.. For an ultraviolet lamp with a 12
mW/cm2 power rating, the exposure time would be approximately
45 minutes. The 7CJ..71 or 7CJ..74 needs to be within 1 inch ofthe
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Pin Function L8]
Read or Output Disable
At4 -
Other
At4 -
Ao
Ao
"CE
CS2
"CSt
07 -00
VFY
Pmi
Vpp
Dr -Do
Read
AI4 - Ao
VIL
VIH
VIL
D7- 0 0
Power Down
AI4 - Ao
VIH
X
X
HighZ
VIL
X
X
AI4-Ao
X
Output Disable
AI4 - Ao
X
Program
AI4-Ao
VUIP
Program Verify
AI4-Ao
VILP
Program Inhibit
AI4 - Ao
Blank Clleck
AI4 - Ao
Output Disable
'.
HighZ
HighZ
VILP
VIH
Vpp
o,-DO
VUIPIVILP
Vpp
D7- 0 0
VUIP
VIHP
Vpp
HighZ
VILP
VUIIt/VILP
Vpp
D7- 0 0
07-00
Table 2; CY7C274 Mode Selection
Pin Function[8]
-Ao
-Ao
t>E
~
Vpp
WY
~
Vpp
07- 0 0
AI4 - Ao
VIL
VIL
X
07- 0 0
Output Disable
AI4 - Ao
VIR
X
X
HighZ
Power Down
AI4-Ao
X
VIH
X
HighZ
D7 -Do
07 -00
Mode
Read or Output Disable
AI4
Other
AI4
Read
Program
AI4 - Ao
VIHP
VILP
Vpp
Program Verify
AI4-Ao
VILP
VIHPlVILP
Vpp
Program Inhibit
AI4 - Ao
VIHP
VIHP
Vpp
HighZ
Blank Clleck
AI4 - Ao
VILP
VIHPIVILP
Vpp
D7- 0 0
Note:
8. X = "doll't care" but not to exceed Vee ±S%.
3-109
II)
:::IE
o
a:
a.
Table 1_ CY7C271 Mode Selection
Mode
•
CY7C271
CY7C274
.~~~~R
DIP
ThpView
p..,
p..,
LCC
ThpView
~.f~~~~i
vee
A,.
Al1
A'2
A,.
A,.
Vpp
A7
p..,
As
A"
As
As
A,
As
D.
D,
D2
GND
p..,
As
A"
p..,
As
PGM
A,
VFY
D7
D.
D,
D.
D.
NC
As
Do
5
6
7
8
9
10
11
12
70271
0
A'2
A,.
A,.
NC
~
VFY
0.
D.
C 8'~ ~O'd' d'
C271-11
C271-10
LCC
ThpView
DIP
ThpView
Vpp
A,.
A7
As
As
A"
As
As
A,
As
Do
D,
D2
GND
vee
A,.
A,.
As
As
A"
As
As
p..,
As
Al1
VFY
AlO
PGM
D7
D.
D,
D.
D.
A,
As
NC
D.
As
p..,
5
6
7
8
9
10
11
12
7C274
0
Al1
NC
VFY
~
D7
D.
C 8'~ ~O'd' d'
0271-13
C271-12
Figure 1. Programming Pinouts
3-110
CY7C271
CY7C274
&1
•.~PRFSS
' SEMICONDUCIOR
'J-Ypical DC and AC Characteristics
/
«
:0
a: 1.0
0
z
O.B
/'"
0.6
4.0
V
4.5
~
~
a:
I
oz
O.B'=------:!=------:-:!
-55
25
125
AMBIENTTEMPERATURE rC)
6.0
5.5
1.6
§.
I-
Z
w
"
0
(J)
I-
a: O.B
::l
f!:
0
z
::l
0
25
125
~
~
-
""'" f'...
::l
~
:0
20
10
oo
1.0
2.0
'" '"
4.0
OUTPUT VOLTAGE (V)
AMBIENTTEMPERATURE (OC)
<"
~
~
3.0
5.0
5.5
6.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
25.0
w
30
a:
4.5
SUPPLY VOLTAGE (V)
50
()
0
0.6
-55
TA = ~5°C
30.0
()
1.2
1.0
Il.
0.4
4.0
60
w
a:
a: 40 "
::l
1.4
/
20.0
15.0
~ 10.0
5.0
V
1/
0.0 0
V
./
V
/
Vcc=4.5V _
TA=25°C
I
200
400
600
I
BOO 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
175
§. 150
!Zw
125
a
100
~
~
Z
75
5
50
en
5o
./
/
./
Vee = 5.0V
TA = 25°C
I
./
25
o/
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
3-111
o
:E
o
a::
OUTPUT SOURCE CURRENT
vs.VOLTAGE
<"
:0
~
«
O.B
a:
NO~DACCESS~E
w
- r--
I-
"" 0.6
oZ
I
vs. TEMPERATURE
~
r---
w
~
SUPPLY VOLTAGE (V)
()
[:l 1.0
o
TA = 25°C
f = fMAJ(
5.0
w
:0
;::
..? 1 . 1 1 - - - - + - - - - - - - - l
/
0
w
N 1.2
:::;
(J)
(J)
1.2
1.2
,-,1.4
2
w
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.6
;::
NO~ZEDACCESST~E
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
4.0
C271-14
CY7C271
CY7C274
~PRESS
_~CONDUcroR
Ordering Information[9]
Speed
(ns)
30
35
45
Ordering Code
Package
type
Operating
Range
Speed
(ns)
Commercial
30
Package
type
Operating
Range
CY7C274-30DC
D16
Commercial
CY7C274-3OJC
J65
CY7C271-30DC
016
CY7C271-30JC
J65
CY7C271-30WC
CY7C271-35DC
W22
D22
CY7C271-35JC
CY7C271-35PC
J65
P21
CY7C271- 35WC
W22
CY7C271-35DMB
CY7C271-35KMB
D22
K74
CY7C271-35LMB
CY7C271-35QMB
L55
Q55
CY7C274-35KMB
CY7C274-35LMB
CY7C271-35WMB
W22
CY7C274-35QMB
CY7C271-45DC
D22
CY7C271-45JC
J65
Commercial
35
Military
Commercial
CY7C274-30PC
P15
CY7C274-30WC
W16
CY7C274-35DC
CY7C274-35JC
CY7C274-35PC
016
J65
P15
CY7C274-35WC
W16
CY7C274-35DMB
016
K74
CY7C274-35TMB
T74
CY7C274-35WMB
W16
CY7C274-45DC
CY7C274-45JC
D22
J65
CY7C271-45PC
P21
CY7C271-45DMB
W22
D22
CY7C274-45PC
P15
CY7C271-45KMB
K74
CY7C274-45WC
W16
CY7C271-45LMB
L55
Q55
CY7C274-45DMB
CY7C274-45KMB
016
T74
CY7C274-45LMB
CY7C274-45QMB
CY7C271-45WMB
W22
CY7C271-55DC
CY7C271-55JC
D22
J65
CY7C271-55PC
CY7C271-55WC
W22
45
Military
Commercial
P21
55
CY7C274-45TMB
T74
CY7C274-45WMB
W16
CY7C274-55DC
CY7C274-55JC
CY7C271-55DMB
D22
CY7C274-55PC
CY7C271-55KMB
K74
CY7C274-55WC
W16
CY7C271-55LMB
L55
Q55
CY7C274-55DMB
D16
K74
CY7C271-55QMB
CY7C271-55TMB
CY7C271-55WMB
T74
CY7C274-55KMB
CY7C274-55LMB
W22
CY7C274-55QMB
Note:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-112
Military
Commercial
Military
K74
L55
Q55
016
J65
P15
Military
Commercial
L55
Q55
CY7C271-45WC
CY7C271-45QMB
CY7C271-45TMB
55
Ordering Code
L55
Q55
CY7C274-55TMB
T74
CY7C274-55WMB
W16
Commercial
Military
CY7C271
CY7C274
2 !~PR£§
. , SEMlcaIDUCfOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vm
VIL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IJX
Ioz
Icc
ISB
•
en
:iii
oa:
Ill.
Switching Characteristics
Parameters
Subgroups
tAA
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tACS1[1O]
toE[ll]
tACE
Notes:
10. 7C274 and 7C271 (CS2, CS3 and CS4 only).
11. 7C271 only.
SMD Cross Reference
SMD
Number
Suff'1X
Cypress
Number
5962-89817
01XX
CY7C271-55WMB
5962-89817
01YX
CY7C271-55TMB
5962-89817
01ZX
CY7C271-55QMB
5962-89817
02XX
CY7C271-45WMB
5962-89817
02YX
CY7C271-45TMB
02ZX
CY7C271-45QMB
5962-89817
Document#: 38-00068-F
3-113
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• O.8-micron CMOS for optimum speed!
power
• Higbspeed
- ZS ns max set-up
- ZS ns clock to output
• 16-bit-wide words
• Registered outputs
• Programmable synchronous or
asynchronous output enable
• Initialization capabUity
- Separate control pin (mrI')
- Programmable initialization word
• 40-pin, 600-mil-wide DIP packages
• 44-pin PLCC and 4.... pin LCC
packages
• 100% reprogrammable in windowed
packages
• 'fTL..compatible JlO
CY7C272
Reprogrammable 16Kx 16
Registered PROM
• Capable ofwltbstanding greater than
z00IV static discharge
Functional Description
The CY7Cl72 is a high-perfonnance
16K-word by 16-bit CMOS PROM with
output registers. It is available in 4O-pin,
6OO-mil-wide DIP packages and 44-pin
PLeC and LCC packages. The 7C272 is
100% reprogrammable in windowed
packages. The memory cells utilize proven
EPROM floating gate technology and
word-wide programming algorithms. The
CY7C272 is a plug-in replacement for
EPROM devices.
The CY7C272 features a programmable
synchronous or asynchronous output enable and a programmable initialization
word.
In order to read the CY7C272, an address
is placed on the address lines (A13 - Ao).
The data stored at tbe array location addressed by the address lines is placed in
the output registers at the rising edge of
eLK. The data will remain on the outputs
until the following rising edge of eLK.
If asynchronous output enable is being
used, the outputs will enter the active
state whenever a UJW i!..e!aced on rn:t
If a mGH is placed on OE, the outputs
will be tri-stated If the synchronous output enable is being used, the outputs will
enter the active state following the first
risil!Ledge of CLK after a UJW is placed
on 00. The outputs will be three-stated
following the first rising edge of CLK after a HIGH is placed on 00.
An initialization control input amn is
provided Applying a LOW to mIT
causes an immediate load of the programmable initialize word into the output registers and. onto the outputs. The output
enable must be active when reading the
initia1ization word. The DiTlT UJW disables CLK and must return HIGH to reenableCLK.
Logic Block Diagram
A13
A12
All
Al0
I.e
As
A7
As
As
~
Aa
~
Al
Ao
16K x 16
PROGRAMMABLE
ARRAY
"::u
8
~
31:
31:
>
aJ
015
16-BIT
EDGETRIGGERED
REGISTER
014
013
,....
m
012
Z
011
=I
5>
010
C
~
0
09
Z
08
~
::u
~
C
06
05
JJillT
04
03
elK
02
OE
01
Do
C272-1
3-114
~
.
;~PRF.SS
PRELIMINARY
CY7C272
.F SEMIC~DUCIDR
Pin Configurations
LCC/PLCC (Opaque Only)
~:!~:sl::o
Vee
INIT
ClK
80000
NC
NC
NC
NC
D,S
OClClO~Z>ZZZZ
0,.
0,3
012
CY7C272
0
38
37
36
35
0"
010
09
D.
34
Vss
33
32
07
D.
Os
D.
03
31
30
C272·2
•
A'3
A'2
A"
A,.
II)
Ae
:::liE
Vss
0
As
II:
A7
02
0,
As
As
As
As
As
Do
A,
DE
As
a.
C272-3
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
MaximumOperating
Current(mA)
I Commercial
I Military
Maximum Ratings
CY7C272-25
CY7C272-30
25
30
25
30
200
200
250
Operating Range
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to + 7.0V
DC Input Voltage ....................... - 3.0Vto +7.0V
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.0V
UVErasure .............................. 7258Wsec/cm2
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200mA
Ambient
Thmperature
Range
Commercial
O°Cto +70°C
Industrial!]
- 40°C to +85°C
5V±1O%
- 55°Cto +l25°C
5V±10%
Military!2]
Vee
5V±1O%
Note.:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature
3-115
.A~DU~
PRELIMINARY
CY7C272
Electrical Characteristics[3,4]
Description
Parameter
lest Conditions
CY7C272-2S
CY7C272-30
Min.
Min.
Vee = Min., IOH
= - 2.0 mA
Vee = Min., IOL = 8.0mA(6.0mAMil)
2.4
Max.
VOH
Output mGH Voltage
VOL
Output LOW Voltage
Vrn
Input HIGH Level
Guaranteed Input Logical HIGH Voltage
for All Inputs.
2.0
Vee
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs.
- 3.0
IIX
Input LeakageCXurent
GND 5 VlN 5 Vee
-10
VCD
Input Clamp Diode Voltage
loz
Output LeakageCXurent
Vee = Max., VOL 5 VOUT 5 VOH,
OutputDisabled
-40
+40
los
Output Short Circuit CXurent
Vee
-90
lee
= Max., VOUT = 0.OV[5]
= 0.0 mA
-20
Power Supply Current
Vee = Max., lOUT
Units
Max.
2.4
0.4
V
0.4
V
2.0
Vee
V
0.8
- 3.0
0.8
V
+10
-10
+10
iJA
-40
+40
iJA
- 20
-90
mA
200
mA
250
mA
Note 3
I Com'l
I Mil
200
Capacitance [3]
Parameters
Description
ClN
InputCapacitance
CoUT
OutputCapacitance
lest Conditions
= 25°C, f = 1 MHz,
Vee = S.OV
TA
Notes:
3. See Introduction to CMOS PROMs in this Data Book for general information on testing.
4. See the last page of this specification for Group A subgroup testing information.
Max.
10
Units
10
pF
pF
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms
R1500n
5V 3=t(65S!l
Mil)
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
J
(a)
R1500n
ALL INPUT PULSES
5V 5f}(65sn
3.0V----
Mil)
R2
OUTPUT
333.0.
(403.0. Mil)
5 pF
INCLUDING
JIG AND
SCOPE
_
J
_
90%
R2
GND
333.0.
(403.0. Mil)
-
C272-4
(b) ffigh Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
200£1 (250£1 Mil)
OUTPUT Q------'WIr--O 2.0V (1.9V Mil)
C272-6
3-116
0272--5
;:-
·~PRFSS
==.
=..,
PRELIMINARY
CY7C272
SEMICONDUCIOR
Switching Characteristics
Over the Operating Rangel3,4]
CY7C272-25
Parameters
Description
tcp
Clock Period
tCB
Min.
Max.
CY7C272-30
Min.
Max.
Units
25
30
ns
Clock HIGH Pulse Width
tcp/2 - 2
tep/2 - 2
ns
tCL
Clock LOW Pulse Width
tcp/2 - 2
tep/2 - 2
ns
tAS
Address Valid to CLK Rise
25
30
ns
tAB
Address Hold from CLKRise
0
0
ns
!eKO
Clock Rise to Output Data
toES
OE Set-Up to CLKRise
20
toEB
OE Hold from CLK Rise
10
tcov
Clock Rise to Output Valid
25
30
ns
tcoz
Clock Rise to High Z Output
25
30
ns
tOEv
OE LOW to Output Valid
25
30
ns
tOEZ
OE HIGH to High Z Output
25
30
ns
tIW
INITPulse Width
tIDY
INITLOW to Data Valid
35
ns
tICR
INIT Recovery to CLK
30
25
ns
15
15
ns
18
30
15
II)
ns
25
ns
18
ns
Switching Waveforms
Read Operation Timing Diagram[6]
I+----tcp
•
elK
DATAB
~
----~
C272-7
Asynchronous Output Enable
}s
~_EV__K V~f<)I.___~
a __
OE------Asynch.
015 - Do _ _ _ _ _ _ _
i~~)1----
to_EV-IC
HIG;:k
HIGHZ
VALID
~
HIGHZ
C272-8
Notes:
6. OE assumed active
3-117
•
:i
o
a::
a.
.il~NDUcroR
PRELIMINARY
CY7C272
Switching Waveforms (continued)
Synchronous Output Enable
ClK
--~.-- toEH
toES
---1.-
toEH
OE
Synch.
!cov
tcoz
!coz
D15-DO------------------~~--------------------_K
VAUD
VAUD
' -________________J
HIGH Z
HIGHZ
C272-9
Asynchronous Initialization Timing Diagram[6j
CLK
tA~
xxxxxxxxxX>d<
1
tlDV
XXXX ~. -I. . .__N--IT~~~~:......
DATAA
C272·10
Architecture Configuration Bits
The CY7C272 has two user-programmable options in addition to
the reprogrammable data array. For detailed programminginformation, contact your local Cypress representative.
The first programmable option determines the operation of the
output enable. When this control bit is programmed with a 0, the
output enable operates asyochronously. When this control bit is
programmed with a 1, the output enable operates syochronously.
The initialization word is also user-programmable.
Control Word
Control Option
Bit
Programmed Level
OS
Do
0
1
Function
OEAsynchronous
OESynchronous
BitMap
Programmer Address (Hex)
RAM Data
0000
Data
3FFF
Data
4000
Control Word
4001
InitializationWord
Control Word (4000H)
DIS
Do
XXXXXXXXXXXXXXXOS
3-118
PRELIMINARY
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
7072 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) or 25 Wsec/em2. For an ultraviolet
lamp with a 12 mW/em'}. power rating the exposure time would be
approximately 35 minutes. The 7Cl72 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm'}. is the recommended maximum dosage.
CY7C272
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Program Mode Table
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
Vpp
~
VFY
Do - 015
Program Inhibit
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VU.P
Data
Mode
Table 2. Signature Mode Table
Ae
At
Do - 015
Cypress Code
VII.P
Vpp
0034 (hex)
Device Code
VIIW
Vpp
0016 (hex)
Signature Mode
Table 3. Configuration Mode Table[7]
Vpp
PGM
WY
Az
A4
Program Inhibit
Vpp
VIHP
VIHP
X
X
HighZ
Program Control \\brd
Vpp
VILP
VIHP
Vpp
VII.P
Control Word
Mode
Notes:
7. X
Do - 015
Verify Control Word
Vpp
VIHP
VILP
Vpp
Vpp
VILP
VIHP
VILP
VILP
Vpp
Control Word
Program Init Word
Verify Init Word
Vpp
VIHP
VILP
VILP
Vpp
InitWord
InitWord
= "don't care" but not to exceed Vee ;1:5%.
DIP
LCC/PLCC
."r"'!St~ >81~~~
0000>
D..
D"
D,.
7
8
g
NC
0.,
Do
Do
0-
PGU
NC
NC
NC
0,.
D,.
D,.
0"
D,.
A,.
A,.
36
A,.
35
34
As
Vsa
33
NC
V..
32
31
30
As
0.,
A7
Do
Do
0
11
12
13
14
15
18
17
"
Vex:
eLK
8 5 4 3 2.1. 44 43 42 41 40
39
38
CNlC272
37
Do 10
Do
v..
Vpp
29
~~!2!l!425~!?28
"N"O~~
DODO
C . - N t ' ) ..
CCCCOC
0,.
A"
Do
Do
As
As
D.
Do
Da
D,
0272-11
Do
VFY
Figure 1. Programming Pinouts
3-119
A,.
A,.
A"
A,.
As
Vas
As
A7
As
As
Ao
As
As
A,
As
0212-12
•
.::~
PRELIMINARY
_'~~DUcroR
Ordering Information[8]
Speed (ns)
tAS
25
30
tcKO
25
30
Ordering
Code
CY7C272-25DC
Package
'JYpe
D18
CY7C272-25HC
H67
CY7C272-25JC
J67
CY7C272-25PC
P17
CY7C272-25WC
W18
CY7C272-30DC
D18
CY7C272-30HC
H67
CY7C272-30JC
J67
CY7C272-30PC
P17
CY7C272-30WC
W18
CY7C272-30DMB
D18
CY7C272-30HMB
H67
CY7C272-30LMB
L67
CY7C272-30QMB
Q67
CY7C272-30WMB
W18
Operating
Range
Commercial
Commercial
Military
Notes:
8.
Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIH
VIL
IIX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
Icc
Switching Characteristics
Parameters
Subgroups
tAS
tAH
tCKO
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
toES
toEH
tcov
toEv
tIW
tIDY
tICR
Document#: 38-00180-A
3-120
CY7C272
CY7C273
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• O.S·micron CMOS ror optimum speed!
power
• Highspeed
- 40 ns access time
• 16-bit-wide words
• 40-pin, 600-mil-wide DIP packages
• 44-pin PLCC and 44-pin LCC
packages
• Direct replacement ror EPROMs
• 100% reprogrammable in windowed
packages
16K X 16 Power Switched and
Reprogrammable PROM
• TfL-compatible I/O
• Capable orwitbstanding greater tban
2OO1V static disdlarge
Functional Description
The CY7C273 is a high-performance
16K-word by 16-bit CMOS PROM. It is
available in 4O-pin, 600-mil-wide DIP
packages and 44-pin PLCC and LCC
packages. The CY7C273 is 100% reprogrammable in windowed packages. The
memory cells utilize proven EPROM
floating-gate technology and word-wide
programming algorithms.
Logic Block Diagram
The CY7C273 is a plug-in replacement
for EPROM devices. When deselected,
the CY7C273 automatically powers down
into a low-power standby mode.
Reading is accomplished by~ing an active LOW signal on
and CE. The contents of the memory location addressed
by the address lines (A13 - AID) will become available on the output lines (DIS
- Do). The data will remain on the outputs until the address changes or the outputs are disabled.
on
Pin Configurations
0,6
16Kx 16
PROGRAMMABLE
ARRAY
DIP
NO
Vee
CE
NC
NC
NC
NC
0,.
0,.
0,.
0,.
0"
0,.
0,4
0 '3
0'2
A,.
A,.
A"
A,.
Dt
Dt
,.
0.
Vaa
At
Vaa
0
"
0,0
Dt
Dt
A7
At
At
A4
At
Ae
D.
De
Dt
Da
08
0,
A,
Do
tIE
Dr
Ao
C273-2
06
05
LCCIPLCC (Opaque Only)
04
.r.r.r~~ ~,.?~ ~ ~ ~
~
02
0,
Do
C273-1
854321114443424140
0,.
0"
0,.
ae
7
8
37
10
36
11
36
Vas 12
34
NO 13
33
0 7 14
32
CV7C273
Dt 15
31
Do 18
30
D. 17
29
\. 18~'!.2112122Z12425252728
Dt
Dt
,.
-'I.
0
oeowo~co~ ~c°c."'c.wcCl).."
3-121
A,.
A"
A"
:!II
e
Vaa
NC
At
A7
~
At
At
C273-3
•
I I)
:E
o
a:
D.
~~
~...
PRELIMINARY
CY7C273
SEMIcaIDUCTOR
Selection Guide
CY7C273-40
CY7C273-45
40
200
200
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Commercial
45
250
Military
Maximum Standby Current (rnA)
40
Commercial
40
Military
50
Maximum Ratings
(Above which the usefullife may be impaired. ForuserguideJines,
nottested. )
StorageThmperature .................. - 65°C to +150°C
Ambient Temperaturewith
PowerApplied ........................ - 55°Cto +l25°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ......................... - 0.5Vto +7.0V
DC Input Voltage ....................... - 3.0V to + 7.0V
DC Program Voltage. . . . . . . . . . .. . . .. .. . . . . . . . . . . . . 13.0V
UVErasure .............................. 7258Wsec/cm2
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
Thmperature
Range
Commercial
O°Cto +70°C
Vee
5V±1O%
Industrial1]
- 40°C to +85°C
5V±1O%
Militaryf2]
- 55°Cto +l25°C
5V±1O%
Electrical Characteristics[3,4]
CY7C273-40 CY7C273-45
Parameter
VOH
Description
Thst Conditions
Output HIGH Voltage
Vee - Min., IOH - - 2.0 rnA
Min.
Com'l
Max.
2.4
Output LOW Voltage
Vee - Min., IOL - 8.0 rnA
Com'l
Vee - Min., IOL - 6.0 rnA
Mil
V1H
Input mGH Voltage
Guaranteed Input Logical HIGH Voltage
for AIlInputs
VIL
Ioput LOW Voltage
Guaranteed Input Logical LOW Voltage
for All Ioputs
Max.
Units
2.4
Mil
VOL
Min.
V
2.4
0.4
0.4
V
0.4
2.0
2.0
0.8
V
0.8
V
IJX
Input Leakage Current
GND.5. VIN .5. V cc
-10
+10
-10
+10
loz
Output LeakageCurrent
Vee = Max., VOL.5. VOUT .5. VOH,
Output Disabled
-40
+40
- 40
+40
iJA
iJA
los
Output Short Circuit Currentl5 ]
Vcc = Max., VOUT
-20
-90
-20
- 90
rnA
Icc
Power Supply Current
Vee = Max., VIN
loUT = ornA
200
rnA
IsH
Standby Supply Current
= O.OV
= 2.0V
Com'l
200
Mil
Chip Enable Ioactive,
CE ~ V1H, lOUT = 0.0 rnA
Com'l
250
40
Mil
40
rnA
50
Capacitance [4]
Parameters
Description
CIN
IoputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
3-122
= 1 MHz,
Max.
Units
10
pF
10
pF
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds ..
~ , ;~PRESS
SEMICONDUCTOR
PRELIMINARY
CY7C273
AC Test Loads and Waveforms
R1500.o.
5V
R1500.o.
~(65B.o.
Mil)
OUTPUT
ALL INPUT PULSES
3.0V---
5V 5r}(65B.o.
Mil)
90%
R2
OUTPUT
R2
333.0.
333.0.
(403.0.
5 pF
(403.0.
Mil)
INCWDING
Mil)
JIG AND
SCOPE
C273-4
(b) High Z Load
50 pF
INCLUDING
JIG AND
SCOPE
(a)
J
_
J
GND
_
C273·5
en
::E
o
I
THEVENIN EQUIVALENT
200.0. (250.0. Mil)
OUTPUT 0--------'wIr-- 2.0V (1.9V Mil)
a::
a.
Equivalent to:
Switching Characteristics
C27:M
Over the Operating Rangd3.41
CY7C273-40
CY7C273-45
Max.
Units
tAA
Address to Output Data Valid
40
45
ns
tCEV
CE LOW to Output Valid
45
50
ns
tCEZ
CE mGH to High Z Output
45
50
ns
tOEV
OE LOW to Output Valid
25
30
ns
tOEZ
OE mGH to High Z Output
25
30
ns
Parameters
Description
Min.
Max.
Min.
Switching Waveforms
Read Operation Timing Diagram[61
XXXX
D'5 - Do
•
t
"=1-
t:~
A
X.....X,.....,.X
....>a<=_O-A_T-A=B====
X X X X X X X X 2 a ( - D - A T - A A - - - - -......
C273·7
Chip Enable and Output Enable Timing Diagrams
C273-B
Noles:
6. CE, OE assumed LOW.
3-123
PRELIMINARY
CY7C273
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin tq erase the
7073 in the windowed package. For this reason, an opaque label
should be placed over the window if the EPROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) or 25 Wsec/em'1.. For an ultraviolet
lamp with a 12 mW/em2 power rating the exposure time would be
approximately 35 minutes. The 7073 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
EPROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/em2 is the recommended maximum
dosage.
this section. Programming algorithms can be obtained from any
Cypress representative.
Thble 1. Program Mode Thble
Vpp
PGM
WY
D, - D15
Program Inhibit
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VIl.P
VIHP
Data
Program Verify
Vpp
VIHP
VIl.P
Data
Mode
Thble 2. Signature Mode Thble
Signature Mode
Programming Information
Programming support is available from Cypress as well as from a
number of third·party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
log
VIl.P
Vpp
0034H
Device Code
VIHP
Vpp
0017H
LCC,PLCC
DIP
£~J!~'!=~ ~~ ~~ ~
e
D,.
D"
D,.
Do
Do
Vas
9
10
11
12
13
NC
I>r
I.
Do
15
18
17
Do
D.
"
5 4 3 2.1. 44 43 42 41 40
38
38
CY7C273
~
38
35
0
34
33
32
31
30
29
1819202122232425282728
ofl)OWo-OO~ ~ CCc-CWcfl)c"
Vpp
Vee
t:E
POll
DII
D,.
D,a
D,.
D"
D,.
Do
Do
Vas
A,a
A,.
A"
A,.
At
Vas
NO
At
A7
At
At
I>r
Do
Do
D.
Do
Do
C273-9
D,
Do
Vf'V
Figure 1. Programming Pinouts
3-124
De -
At
Cypress Code
NC
NC
NC
A,a
A,.
-'I,
A,.
At
Vas
At
A7
At
At
Ao
At
At
A,
At
0273-10
D15
~
.~
.
,
PRELIMINARY
~§'NDUClOR
CY7C273
Ordering Information[7]
CY7C273-40DC
Package
lYPe
D18
CY7C273-40HC
H67
CY7C273-40JC
CY7C273-40PC
J67
P17
CY7C273-40WC
CY7C273-45DC
W18
D18
Speed (ns)
40
45
Ordering Code
CY7C273-45HC
H67
CY7C273-45JC
J67
CY7C273-45PC
P17
W18
CY7C273-45WC
CY7C273-45DMB
CY7C273-45HMB
D18
CY7C273-45LMB
CY7C273-45QMB
L67
Q67
CY7C273-45WMB
W18
Operating
Range
Commercia!
Military
H67
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IIX
Ioz
Icc
Switching Characteristics
Parameters
Subgroups
tM
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
IcEV
toEV
:::E
oa:
a.
Notes:
7. Most of the above products are available in industrial temperature
range. Contact a Cypressrepresentative for specifications and product
availability.
Parameters
•
en
Commercial
Document#: 38-00182-A
3-125
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• O.8-micron CMOS for optimum speed!
power
• Hlghspeed
- 20 ns max set-up
- 12 ns clock to output
• Hi-blt-wide words
• Registered outputs
• Three programmable input chip selects
• Synchronous or asynchronous chip
selects
• Programmable output enable
• Initialization capability
- Separate control pin (lNlT)
- Programmable initialization word
• Programmable synchronous or
asynchronous Ioit
• 44-pin PLCC and 44-pin LCC
packages
• 100% reprogrammable in windowed
packages
CY7C275
Reprogrammable 16Kx 16
Registered PROM
• TTI.-compatible I/O
• Capable ofwltbstanding greater than
2001V static discharge
Functional Description
The CY7Cl75 is a higb-perfonnance
16K-word by 16-bit CMOS PROM witb
output registers. It is available in a 44-pin
PLOC and a 44-pin LOC, and is 100% reprogrammable in windowed packages.
The memo!)' cells utilize proven EPROM
f1oating-gate technology and word-wide
programming algorithms.
The CY7Cl75 features three independently programmable syncbronous or
asynchronous chip selects (CS2 - CSO)
for on -chip address decoding of up to
eight banks of PROMs. The active polarity of the output enable (OE) is also programmable.
In order to read the CY7Cl75, all three
chip selects must be active and OE must
be enabled. The data stored at the array
location addressed by the address lines
(A13 - Ao) is placed in the output register at the rising edge of eLK. The data
will remain on the outputs until the following rising edge of CLK.
An initialization control input (INIT) is
provided The initialization mode can be
programmed to operate eitber synchronously or asyncbronously. If the stNWonous mode is being used, when
is
LOW during the rising edge of CLK, a
separate, programmable initialization
word appears on the output at the next
rising edge of CLIC. The chip selects and
output enable must be active when reading the initialization word.
If the asyncbronous initialize mode is being used, applying a LOW to mlT causes
an immediate load of the programmable
initialize word into the output registers
and onto the outputs. The chip selects and
output enable must be active when readmg the initialization word. The asynchronous mIT LOW disables CLK and must
return mGH to re-enable CLIC.
Logic Block Diagram
A13
A12
A"
A10
As
As
~
~
~
16-BIT
EDGETRIGGERED
REGISTER
As
As
Aa
012
011
~
0
09
~
08
010
Z
~
A1
:1J
0
Ao
013
Z
~c
~
014
III
fii
A7
m
015
""0
:1J
0
Gl
16Kx 16
PROGRAMMABLE
ARRAY
07
De
r;:=I:::N;IT:::IA=L;IZA~:r~I~O:::N::;-1 MUX
05
REGISTER
04
CLK
Da
CS
REGISTER
~
CS
DECODE
01
Do
OE
C27501
3-126
~~
_=CYPRESS
IF
~
PRELIMINARY
CY7C275
SEMlCONDUClDR
Pin Configurations
LCC, PLCC (Opaque Only)
ThpView
66~d~~~~~~~
D12
D"
D,.
D.
De
Vss
Vee
D7
D.
Ds
D.
7
8
g
10
11
12
13
"
15
16
17
6 5 4 3 2,1,4443424140
39
38
37
36
35
34
33
32
CY7C275
31
0
•
A'3
A12
A"
AIO
Po.,
Vss
vs.
II)
Po.,
:e
A7
30
Po.,
29
1819202122232425262728
As
a'"d'b. . .0° ~::sa..?<.('I..r 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200mA
Operating Range
Range
Commercial
Ambient
Thmperature
O°Cto +70°C
Vee
5V±10%
Industrial1J
MilitarylLJ
- 40°Cto +85°C
5V±10%
- 55°Cto +125°C
5V±1O%
Electrical Characteristics[3, 4]
CY7C27S-20
CY7C27S-2S
CY7C27S-30
Parameter
Deseription
Output HIGH Voltage
Thst Conditions
Input HIGH Level
V cc - Min., IOH - - 2.0 rnA
V cc - Min., IOL - 8.0 rnA (6.0 rnA Mil)
Guaranteed Input Logical HIGH Voltage for All Inputs
VIL
IJX
VCD
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
Input LeakageCurrent
Input Clamp Diode Voltage
GND~ VJN~ Vcc
loz
los
Output LeakageCurrent
Vee - Max., VOL ~ VOUT ~ VOH, Output Disabled
Output Short Circuit Current
Vee = Max., VOUT = O.OVl'J
Icc
Power Supply Current
Vee = Max., lOUT = 0.0 rnA
VOH
VOL
VIH
Output LOW Voltage
Min.
2.4
Max.
Units
0.4
V
V
V
2.0
Vee
- 3.0
0.8
-10
+10
Note 3
V
ItA
+40
ItA
- 90
rnA
I Com'l
200
rnA
1 Mil
250
- 40
-20
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TAis the "instant on" case temperature.
3. See Introduction to CMOS PROMs in this Data Book for general information on testing.
4.
See the last page ofthisspecification for Group Asubgroup testing information.
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3-127
PRELIMINARY
CY7C275
Capacitance[3J
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CaUT
'lest Conditions
Units
Max.
10
TA = 25°C, f = 1 MHz,
Vcc=5.0V
pF
pF
10
AC Test Loads and Waveforms
R1500n
5V
Rl500n
~(658n
Mil)
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
J
-
ALL INPUT PULSES
3.0V----
5V 5 f ] ( 6 5 8Mil)
n
OUTPUT
333rl
(403rl
_
Mil)
-
5 pF
INCWDING
JIG AND
SCOPE
J
_
-
90%
R2
333rl
(403rl
Mil)
-
GND
CV~
C2754
(b) High Z Load
(a)
I
Equivalent to:
THEVENIN EQUIVALENT
200n (250n Mil)
OUTPUT ~ 2.OV (1.9V Mil)
Switching Characteristics Over the Operating Rangel3, 4J
CY7C275-20
Parameters
Description
tcp
Clock Period
tCH
Min.
Max.
CY7C275-25
Min.
Max.
CY7C275-30
Min.
Max.
Units
20
25
30
ns
Clock HIGH Pulse Width
tepf2 - 2
tepf2 - 2
tcpf2 - 2
ns
tCL
Clock LOW Pulse Width
tcrf2- 2
tep/2 - 2
tepf2 - 2
ns
tAS
Address Valid to CLK Rise
20
25
30
ns
tAH
Address Hold from CLK Rise
0
teKO
Clock Rise to Output Data
tess
CS Set-Up to CLK Rise
4
4
5
ns
teSH
CS Hold from CLK Rise
3
4
4
ns
tcov
Clock Rise to Output Valid
12
15
18
ns
tcoz
Clock Rise to High Z Output
12
15
18
ns
toBV
OE Active to Output Valid
12
15
18
ns
toEZ
OE Inactive to High Z Output
12
15
18
ns
tIS
INIT Set-Up to CLK Rise
20
25
30
tIH
INITHold from CLK Rise
0
0
0
ns
tIW
Asynchronous InitPulse Width
12
15
18
ns
tIDY
Asynchronous Init to Data Valid
tICR
Asynchronous InitRecovery to CLK
tesov
cs Active to Output Valid
15
18
21
ns
tesoz
CS Inactive to High Z Output
15
18
21
ns
0
..
.. 12·
..
I
Shaded areas contain advanced information.
3-128
15
ns
18
20
15
12
0
15
ns
ns
25
18
ns
ns
-:~
PRELIMINARY
~_CYPRESS
~, SEMICONDUClDR
CY7C275
Switching Waveforms
Read Operation[6]
t-----tcP - - -......·1
•
ClK
II)
::E
o
a:
xxxxxxxxXXXXa"--DA-TAA~~
Q.
_
_ _ _'-/\J\T
A.L:::.C:::....
DATAB
C275-6
Synchronous Chip Select and Output Enable
ClK
CS2 - CSo
--"
OE---------+----~
Active HIGH
0 15 - Do
--------t(
C275-7
Asynchronous Chip Select and Output Enable
CS2 - CSo
-----INACTIVE
ACTIVE
INACTIVE
OE--------~---~
Active HIGH
tcsoz
tcsov
0 15 - Do _____________________1(
VALID
HIGHZ
HIGHZ
HIGHZ
C275-8
Notes:
6_ CS2 - CSo, OE assumed active
3-129
~
.AL~ONOOcroR
PRELIMINARY
CY7C275
Switching Waveforms (continued)
Synchronous Initialization Timing Diagram[6]
CLK
IcKO ::1 ,
D Do ~X~X=X"'7"l:X~X""'7'X~X~X~X~X~)Q(,-"""D_A-:r_A-A~~::;~
. . . . . . . _....J>
15 -
C275-10
Asynchronous Initialization Timing Diagram[6]
ClK
tA~
xxxxxxxxxX>ct
tlDV
DATAA
1
XXXx )k'-.. .I_N-IT~~~~;;
.....
C275-9
3-130
PRELIMINARY
CY7C275
Architecture Configuration Bits
Erasure Characteristics
The CY1C1.75 has seven user-programmable options in addition
to the reprogrammable data array. For detailed programming information, contact your local Cypress representative.
Wavelengths of light less than 4000 Angstroms begin to erase the
7C1.75 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The first four programmable options determine the active polarity for the three chip selects (CSz - CSo) and the active polarity
of OE. When these control bits are programmed with a 0, the inputs are active LOW. When these control bits are programmed
with a I, the inputs are active HIGH. The fifth option determines
the operation of the initialize function. When the control bit is
programmed with a 0, initialize is synchronous. When the control
bit is programmed with a I, initialize is asynchronous. The sixth
option determines the operation of the chip selects. When the
control bit is programmed with a 0, the chip selects are synchronous. When the control bit is programmed I, the chip selects are
asynchronous. The initialization word is also user-programmable.
Control
Option
Bit
Programmed
Level
OE
Do
0
1
OE Active LOW
OE Active HIGH
AE
D3
0
1
Synchronous CSo-z
Asynchronous CSo-z
CSo
DIZ
0
1
CSo Active LOW
CSo Active HIGH
D13
Function
0
1
CSI Active LOW
CSI Active HIGH
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Prograntming Information located at the end of
this section. Programming algorithms can be obtaiJied from any
Cypress representative.
Control Word
CSI
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) or 25 Wseclcmz. For an ultraviolet
lamp with a 12 m W/cm2 power rating the exposure time would be
approximately 35 minutes. The 7C1.75 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage.
CSz
D14
0
1
CSz Active LOW
CSz Active HIGH
IA
DIS
0
1
INIT Synchronous
INIT Asynchronous
'Thble 1. Program Mode 'Thble
0000
RAM Data
Data
3FFF
4000
4001
Data
Control Word
Initialization Word
Pmd
VFY
Do - D15
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VILP
Data
Mode
'Thble Z. Signature Mode 'Thble
Ao
At
Do - D15
Cypress Code
VU.P
Vpp
0034 (hex)
Device Code
VlliP
Vpp
0014 (hex)
Signature Mode
BitMap
Programmer Address (Hex)
Vpp
Program Inhibit
Control Word (4000H)
D15
Do
IA CSz CSI CSoXXXXXXXXAEXX OE
'Thble 3. Configuration Mode 'Thble[7)
Vpp
PGM
VFY
A2
A4
Program Inhibit
Vpp
VUIP
VlliP
X
X
HighZ
Program Control \\brd
Vpp
VIl.P
VlliP
Vpp
VU.P
Control Word
Mode
Do - D15
Verify Control Word
Vpp
VIHP
VIl.P
Vpp
Vu.P
Control Word
Program luit Word
Vpp
VILP
VIHP
VIl.P
Vpp
lnitWord
Verify Init Word
Vpp
VIHP
VIl.P
VIl.P
Vpp
lnitWord
Notes:
7. X = "don't care" but not to exceed Vee %5%.
3-131
•
(I)
:::IE
o
a:
a..
PRELIMINARY
Ordering Information[8]
~c
:!~~
goll~
cf
c
o o »~>
z >0
a:
0'2
011
0,.
D.
o.
Vss
Vee
0,
O.
O.
0,
6 5 4 3 2,1'4443424140
39
38
9
10
11
12
13
14
15
16
17
37
0
36
35
34
33
32
CY7=5
31
30
29
1819202122 23 24 25 26 27 28
a
(I)
C\I ....
0 0
a
ow CIl 0,.... (\I (I) ~
0 >Ul< < c( < <
CY7C275
Speed (ns)
A,s
A'2
A11
tAS
tcKO
20
12
A,.
Ag
25
Vss
Vss
15
Ag
A,
Ag
A.
18
30
C275-11
Figure 1. Programming Pinout
Ordering Code
Package
1YPe
Operating
Range
CY7C27S~20HC
H67
Co:nnnercial
CY7C275"'2OJC
J67
CY7C275 - 25HC
H67
CY7C275-25JC
J67
CY7C275-25HMB
H67
CY7C275-25LMB
L67
CY7C275-25QMB
Q67
CY7C275-30HC
H67
CY7C275-30JC
J67
CY7C275-30HMB
H67
CY7C275-30LMB
L67
CY7C275-30QMB
Q67
Commercial
Military
Commercial
Military
Shaded areas contam advanced mformation.
Note.:
8. Most of the above products are available in industrial temperature
range. Contact a Cypressrepresentative for specifications and product
availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tAS
7,8,9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
VOL
VIH
VIL
IIX
Ioz
Icc
tAH
tCKO
tess
tCSH
tCOY
toBY
tIS
tm
tIW
tIDY
tIeR
Document#: 38-00181-A
3-132
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• O.8-micron CMOS for optimum speed!
power
•
•
•
•
16Kx 16
Reprogrammable PROM
• TTL-c:ompatlble 110
• Capable of withstanding greater than
2001V static discharge
.
Functional Description
• Higb speed
- 2S ns access time
16-bit-wide words
Three programmable chip selects
Programmable output enable
44-pin PLCC and 44-pin LCC
packages
• 100% reprogrammable In windowed
packages
CY7C276
The CY7C276 is a high-performance
16K-word by 16-bit CMOS PROM. It is
available in a 44-pin PLCC and a 44-pin
LCC, and is 100% reprogrammable in
windowed packages. The memory cells
utilize proven EPROM floating-gate technology and word-wide programming algorithms.
The CY7C276 features tbree independently programmable chip selects (CSz CSo) for on-chip address decoding of up
to eight banks of PROMs. The polarity of
the output enable (OE) is also programmable.
In order to read the CY7C276, all three
cbip selects must be active and OE must
be enabled The contents of the memory
location addressed by the address lines
(A13 - Ao) will become available on the
output lines (DIS - DO)' The data will remain on the outputs until the address
cbanges or the outputs are disabled.
Pin Configurations
Logic Block Diagram
LCC/PLCC (Opaque ODly)
1bpVlew
16Kx 16
PROGRAMMABLE
ARRAY
'"--HI>-
013
.....-+-1>-
012
L...--+-D....
011
.....---t-tl>-
010
L----t-c>-
£J£~~~~~iBB
85432;104443424140
09
08
......- - - - ; - 0 - 0 7
L...----+i>
06
L------i~;>-
05
Dtl
Dtt
DtO
De
De
7
8
9
10
11
12
13
14
15
18
D.
17
De
De
V...
Voo
0.
0
c:r7Cml
38
38
At.
37
35
Att
AtO
35
34
33
32
31
AtAe
V...
Vas
Ae
A7
30
Ae
29
Ae
18 19 20 21 22 23 24 25 28 27 28
omaNa-0° ~ >1<11(0c'"eNernc"
04
03
CSo
CSI
CSz
CS
DECODE
02
.......------+0- 01
L...-------+f>
OE-----~__r--------~
Do
C276-1
Selection Guide
3-133
0276-2
•
I I)
:E
oa::
Il..
PRELIMINARY
CY7C276
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Static Discharge Voltage ........................ >2001V
(per MIlrSTD-883, Method 301S)
Latch-UpCurrent ............................ >200rnA
StorageThmperature ................. - 6S0Cto +lS0°C
Ambient Thmperaturewith
PowerApplied ....................... - SSOCto +l25°C
Supply Voltage to Ground Potential. . . . . . .. - O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.SV to + 7.0V
DClnputVoltage ...................... - 3.0Vto +7.0V
DC Program Voltage. . .. . .. .. . . . . . .. .. . . . . . . . . . . .. 13.0V
UVErasure ............................. 7258Wsec/cm2
Operating Range
Range
Commercial
Ambient
Thmperature
O°Cto +70°C
Vee
SV±lO%
IndustriaIl1]
- 40°C to +8SoC
SV±10%
Militaryl2]
- SSOCto +l25°C
SV±10%
Electrical Characteristics[3,4]
CY7C276-25[S]
CY7C276-30
CY7C276-35
Parameter
Thst Conditions
Description
Min.
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA (6.0 rnA Mil)
Vrn
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
Ilx
Input LeakageCurrent
Veo
Input Clamp 'Diode Voltage
loz
Output LeakageCurrent
Max.
Units
2.4
VOH
V
0.4
V
V
- 3.0
Vee
0.8
GND ~ VIN ~ Vee
-10
+10
tAA
Vee = Max., VOL~ VOUT ~ VOH,
Output Disabled
- 40
+40
tAA
- 20
V
Note 3
los
Output Short Circuit Current
Vee = Max., VOUT = O.OVLbJ
Icc
Power Supply Current
Vee = Max., lOUT = 0.0 rnA
- 90
rnA
I Com'l
200
rnA
I Military
250
rnA
Capacitance [3]
Description
InputCapacitance
Max.
Units
qN
Parameters
TA = 25°C, f = 1 MHz,
Thst Conditions
10
pF
CoUT
OutputCapacitance
Vcc= S.OV
10
pF
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature
3. See Introduction to CMOS PROMs in this Data Book for general information on testing.
4.
5.
6.
See the last page of this specification for Group A subgroup testing information.
Data for 25-ns is advanced information.
For test purposes, not more than one output at a time should be
shorted Short circuit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms
R1 SOOn
5V
R1500n
~(658n
Mil)
OUTPUT
50pF
INCWDING
JIG AND
SCOPE
(a)
J
ALL INPUT PULSES
3.0V---
5V 5 f 1 ( 6 5 8
Mil)
n
R2
OUTPUT
R2
3330,
333n
(403n
5pF
(4030,
Mil)
INCLUDING
Mil)
JIG AND
-0276-3
SCOPE
(b) High Z Load
_
J
90%
GND
_
C276-4
I
Equivalent to:
THEVENIN EQUIVALENT
200.0, (250.0, Mil)
OUTPUT 0--------'IMr-- 2.0V (1.9V Mil)
C27tHi
3-134
PRELIMINARY
CY7C276
Characteristics Over the
•
en
:E
o
a:
a.
Erasure Characteristics
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity
multiplied by exposure time) or 25 Wsec/cm2• For an ultraviolet
lamp with a 12 mW/cm2 power rating the exposure time would be
approximately 35 minutes. The 7Cl76 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
EPROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Wavelengths of light less than 4000 Angstroms begin to erase the
7Cl76 in the windowed package. For this reason, an opaque label
should be placed over the window if the EPROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
Switching Waveforms
Read Operation Timing Diagram[7]
XXX)(
t
ADDRA
t"-:_RB_:j_-.---
)C(X>CR~~~D-~-A-A----------~X~XX~X)K~D-~-A-B-Chip Select and Output Enable Timing Diagrams
cS:! - eSc
INACTIVE
ACTIVE HIGH
OE
C2,/'H
Notes:
7. CSz - CSo. OE assumed active.
3-135
PRELIMINARY
CY7C276
Architecture Configuration Bits
Programming Infonnation
The CY7C276 has four user-programmable options in addition
to the reprogrammable data array. For detailed programming information contact your local Cypress representative.
The programmable options detennine the active polarity for the
three chip selects (<:Sa - CSo) and OF. When these control bits are
programmed with a 0 the inputs are active LOW. When these control bils are programmed with a 1 the inputs are active mOlL
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information Ioc:ated at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Control Word
Control Option
Bit
Programmed Level
OE
Do
0
DIZ
0
1
CSo Active LOW
CSI
013
0
1
CSI Active LOW
CSI Active HIGH
CSz
014
0
1
CSz Active LOW
CSzActive mOH
CSo
FunctIon
OE Active LOW
OE Active mOH
1
CSo Active mOH
BitMap
1Bble 1. Program Mode 1Bble
Programmer Address (Hex)
0000
Vpp
PGM
VFY
Program Inhibit
Vpp
VIHP
VIHP
Do - D15
HighZ
Program Enable
Vpp
VII.P
VIHP
Data
Program Verify
Vpp
VIHP
VIl.P
Data
Mode
RAM Data
Data
Data
Control Word
3FFF
4000
1Bble 2. Signature Mode 1Bble
At
At
Cypress Code
VIl.P
Vpp
Do - D15
0034 (hex)
Device Code
VUIP
Vpp
0015 (hex)
Signature Mode
Control Word (4000H)
DIS
Do
X CSz CSI CSo XXXXXXXXXXX OE
1Bble 3. Configuration Mode 1Bble
Mode
Program Inhibit
Vpp
PC'M
WY
A2
Vpp
VIlIP
VIlIP
Vpp
D. - D15
HighZ
Program Control \\Urd
Vpp
VIl.P
VIlIP
Vpp
Control \\%)rd
Verify Control Word
Vpp
VllIP
VILP
Vpp
Control \\%)rd
3-136
~
PRELIMINARY
~-CYPRESS
~_. ,
CY7C276
SEMICONDUCTOR
", ... on
0. '" 0
ooo~::e-~~~
~I~ B
0
6 5 4 3 2 11144 43 42 41 40
D12
D"
DlO
D9
D8
VSS
Vee
D,
D8
D,
D,
39
9
10
11
12
13
38
!IT
CY7C276
36
0
35
34
33
32
31
15
16
30
17
29
1819202122 23 2. 25 26 27 28
,.
A'3
A'2
A"
AlO
A,
•
Vss
Vss
As
en
:!:
0
A,
As
A,
a::
Do
C'lN..-OWCI)O .... NCf)'IIt
C ceo
0 >CDct.
-< .:( < <
0278·8
Figure 1. Programming Pinout
Ordering Information[8]
Speed
(ns)
25
30
35
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Package
1YPe
Operating
Range
CY7C276-25HC
H67
Commercial
CY7C276-25JC
J67
Ordering Code
CY7C276-30HC
H67
CY7C276- 30JC
J67
CY7C276-30HMB
H67
CY7C276- 30LMB
L67
CY7C276-30QMB
Q67
CY7C276-35HC
H67
CY7C276-35JC
J67
CY7C276-35HMB
H67
CY7C276-35LMB
L67
CY7C276-35QMB
Q67
DC Characteristics
Parameters
Subgroups
Commercial
VOH
1,2,3
Military
VOL
Vrn
1,2,3
1,2,3
VIL
1,2,3
1,2,3
IJX
Ioz
Icc
Commercial
Military
1,2,3
1,2,3
Switching Characteristics
Shaded area contains advanced information.
Subgroups
tAA
7,8,9, 10, 11
7,8,9, 10, 11
tcsOY
tOEY
Notes:
8. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
Parameters
Document#: 38-00183
3-137
7, 8, 9, 10, 11
CY7C277
CY7C279
CYPRESS
SEMICONDUCTOR
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• Highspeed
- 30 ns (7C277) and 3 ns (7C279)
max. set-up
-15 ns (7C277) and 35 ns (7C279)
clock to output
• Lowpower
- 660 mW (commercial)
-715 mW (military)
Reprogrammable 32K X 8
Registered PROM
• Programmable address latch enable
input
• Programmable synchronous or
asynchronous output enable (7C277)
• On-chip edge-triggered output
registers (7C277)
• Optional registered/latched address
inputs (7C279)
• EPROM technology, 100%
programmable
• Slim 300-mil, 2S-pin plastic or
hermetic DIP
• 5V ±10% Vee, commercial and
military
• TIL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2000V static discharge
Logic Block Diagram
A,.
A,.
A'2
A"
A,o
A"
A"
Pin Configurations
07
ADDRESS
15-BIT
ADDRESS
TRANSPARENT
LATCH
ROW
DECODeR
256 x 1024
PROGRAMMABLE
1 OF 256
ARRAY
o.
6-Brr
1 OF 128
MUX
O.
(70277)
&-BIT
A7
A"
Ao
A.
A>
Aa
DIP/Flatpack
ThpView
15-BIT
03
(7C277
ONLy)
ADDRESS
REGISTER!
LATCH
(7C279)
A,
COLUMN
DECODER
10F32
As
As
A"
A'2
A'3
A,.
ALE
CP
A7
ElEs
A,
o.
07
As
00
O.
0,
02
GND
4
As
00
00
ep
Vee
A,o
A7
A,
02
0,
As
A"
A"
A"
Ao
A.
A>
Aa
O.
EDGE·
TRIGGERED
REGISTER
DIP
Top View
0,
o.
02
GND
0.
vee
A,o
A"
A'2
A,.
A,.
CPtALE
CS
4
5
A"
Ao
A.
A>
Aa
~
07
o.
o.
O.
0.
C277-2
LCC/PLCC (Opaque Only)
ThpView
CPt
ALE
~--!-~~~~~--------------------~~--~
A"
Ao
A.
A>
(7C279 ONLy)
CS-----L~-:/_-l==~::::~==~~;;~H;»-+---~
E/Es-
A2
A,
CP-I)()-...r-U-_-.J
As
NC
00
C277-1
C277-5
LCC/pLCC (Opaque Only)
ThpView
~.l.t~$.fi
u~\1$1.f
432!.,.1 j 323130
432,1,323130
29C
29
5
28
70277
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617181920
0
A'2
A'3
A,.
NC
ALE
CP
ElEs
Or
Os
A,
As
NC
00
om
5
6
7
8
25C
9
24
10
23
11
22\
12
21
13
14151617181920
A'2
A'3
A,.
NC
CP/ALE
CS
~
Or
Os
0- 8'~\1cS'0'd'
0- 8'~\1cS'0' d'
'"
A"
A"
A.
A>
Aa
'"
C277-3
C277-4
Selection Guides
7C277-30
Maximum oserating
Current(mA
Maximum Standby
Current(mA)
7C279-35
7C277-40
35
MaximumAcccss Time (ns)
Maximum Setup Time (ns)
Maximum Clock to Output (ns)
Com'!
Military
Com'!
Military
30
15
120
120
30
7C279-45
40
20
120
130
7C279-55
55
50
25
120
130
30
40
3-138
7C277-50
45
120
130
120
130
30
40
CY7C277
CY7C279
Functional Description
The CY7C277 and the CY7C279 offer the advantages of low
power, superior perfonnance, and high programming yield The
EPROM cell requires only 12SV for the supervoltage and low
current requirements allow for gang programming. The EPROM
cells allow for each memory location to be 100% tested, as each
location is written into, erased, and repeatedly exercised prior to
encapsulation. Each PROM is also tested for AC perfonnance to
guarantee that the product will meet DC and AC specification
limits after customer programming.
On the 7C277, the outputs are pipelined through a master-slave
register. On the rising edge of CPo data is loaded into the 8-bit
edge triggered output register. The Ms input provides a
programmable bit to select between asynchronous and synchro-
nous operation. The default condition i!..lI!)'Ilchronous. When the
asynchronous mode is selected, the EIEs pin operates as an
IISYI!chronous output enable. If the synchronous mode is selected,
the Ms pin is sampled on the rising edge of CP to enable and
disable the outputs. The 7C277 also provides a programmable bit
to enable the Address Latch input If this bit is not programmed,
the device will ignore the ALE pin and the address will enter the
device asynchronously. If tIie ALE function is selected, the
address enters the PROM while the ALE pin is active, and is
captured when ALE is deasserted. The user may define the
polarity of the ALE signal, with the default being active HIGH.
On the 7C279, address registers are provided to easily interface
with the Cypress 7C601 and other microprocessors that deliver
addresses around a rising clock edge. A programmable bit is
provided to select between latched and registered address inputs.
The default is registered inputs, which will sample the address on
the RISING EDGE of CP and load the address register. The
latched address option will recognize any address changes while
the ALE pin is active and load the address into the· address
latches on the deactivating edge of ALE. If the latched address
option is selected, another programmable bit is provided for the
user to select the polarity that will define ALE active, with the
default being active HIGH.
Maximum Ratings
Operating Range
The CY7C277 and the CY7C279 are high-perfonnance 32K
word by 8-bit CMOS PROMs. When deselected, the 7C279
automatically powers down into a low-power standby mode. The
7C277 and the 7C279 both are packaged in the slim 28-pin
3OO-mil package. The ceramic package may be equipped with an
erasure window; when exposed to UV light, the PROM is erased
and can then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technolo&y and byte-wide algorithms.
(Above which the useful life maybe impaired. Foruser guidelines,
not tested.)
Range
Storage Thmperature ................. - 6S·C to +1S0·C
Ambient Thmperature with
Power Applied ...................•.. - 5S·C to +125·C
Supply Voltage to Ground Potential. . . . . .. - O.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Ontputs
in High Z State ...•.....•.........•.... - O.5V to + 7.0V
DC Input Voltage ..............•..••... - 3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ...........•.... 13.0V
UV Erasure ..•...•.....•................ 7258 Wsec/cm2
Static Discharge Voltage ••.........•.......•.... >2oo1V
(per MIL-SID-883, Method 301S)
Latch-Up Current ....•.........••........... >200 rnA
AmbIent
Temperature
Commercial
Industrial!l)
O·Cto +70·C
Vee
SV::!:lO%
- 4O·C to +8S·C
SV::!:lO%
Militaryl2J
- SS·C to +l25·C
SV::!:10%
Notes:
1. Contact a Cypress representative for industrial temperature range
2.
3-139
specifICatiOns.
TA is the "instant onD case temperature.
(II
::::i
oa:
Il.
CY7C277
CY7C279
g~~PRESS
~
SEMICONDUCTOR
Electrical Characteristics
Over the Operating Rangef3, 4)
7C277-30 7C277-40,50
7C279-35 7C279-45,55
Min. Max. Min. Max. Units
'Thst Conditions
2.4
2.4
V
Vee - Min., IoH - - 2.0 rnA
0.4
0.4
V
Vee = Min., IOL = 8.0 rnA
Guaranteed Input Logical HIGH Voltage 2.0
2.0
V
Vee
Vee
for All Inputs
Description
Output HIGH Voltage
Parameters
VOH
VOL
VIH
.. ,.
Output LOW Voltage
Input HIGH Level
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
0.8
IIX
Input Leakage Current
loz
Input Clamp Diode Voltage
Output Leakage Current
-10
GND.:5. VIN.:5. Vee
Vee - Max., VIH - 2.0V lOUT - 0 rnA
VOL.:5. VOUT.:5. VOlI,OUtputDisabledPJ -40
+10
VCD
los
lee
Output Short Circuit Current
Power Supply Current
Vee = Max., VOUT
- 90
120
Issl7J
Vpp
Programming Supply Voltage
Ipp
ProgrammingSupplyCurrent
Input HIGH Programming Voltage
- 20
Vee-Max:,CS~VIH
Commercial
lOUT
Militaty
= ornA
Vee = Max., CS ~ VIH
lOUT = ornA
Standby Supply Current
VIHP
VILP
= 0.OV16J
-10
Note 6
+40 - 40
- 20
0.8
V
+10
t-tA
+40
t-tA
-90
rnA
rnA
120
130
Commercial
Militaty
12
30
30
rnA
13
40
13
50
V
rnA
12
50
3.0
3.0
Input LOW Programming Voltage
V
0.4
0.4
V
Capacitance [4)
'Thst Conditions
Description
InputCapacitance
Output Capacitance
Parameters
CIN
CoUT
Units
Max.
10
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
pF
pF
10
AC Test Loads and Waveforms [4)
R1500n
(658.0. MIL)
R1500n
(65Sn MIL)
5V
5V
OUTPUTo--~P---"
30PFI
INCLUDING
JIGAND _
5PFI
R2
333.0.
(403.(1 MIL)
INCLUDING
JIGAND _
SCOPE -
::=n0~
.s.5ns~ ~
R2
333.0.
(403.(1 MIL)
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo--~P---"
C277-6
(b) High Z Load
~
10%
....
5,.5n8
C277-S
C2n-7
THEVENIN EQUIVALENT
2()()!1
OUTPUT
O.O---"I""'~
250!1
OUTPUT 0.0---"1
.....----o01.9V
_ _--OO 2.OV
Military
Commercial
Notes:
3. See the last page of this specification for Group A subgroup testing in·
formation.
4. See "Introduction to CMOS PROMs" in this Book for general in·
formation on testing.
5. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
6.
7.
3-140
C277-9
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Only the CY7C279 has a standby mode.
CY7C277
CY7C279
&:~PRFSS
~,
SEMICONDUCTOR
CY7C277 Switching Characteristics Over the Operating Rangel3, 4]
7C277-30
Parameters
Description
tAL
Address Setup to ALE Inactive
tLA
Address Hold from ALE Inactive
tLL
ALE Pulse Width
tSA
Address Setup to Clock HIGH
tHA
Address Hold from Clock HIGH
tSES
Es Setup to Dock HIGH
tHES
Es Hold from Clock HIGH
teo
Dock HIGH to Output Valid
tpwe
Clock Pulse Width
tLZcL"J
Output Low Z from Clock HIGH
tHzcL~J
Output High Z from Clock HIGH
tLZE LlU]
Output Low Z from E LOW
tHZEliUJ
Output High Z from E HIGH
Min.
Max.
7C277-40
Min.
Max.
10
10
10
5
10
10
30
0
12
5
0
15
10
20
15
20
20
20
Units
ns
ns
ns
ns
ns
ns
ns
25
TIS
30
30
30
30
ns
ns
ns
20
20
20
15
15
15
15
Max.
10
15
15
50
0
15
10
40
15
7C277-S0
Min.
ns
ns
CY7C279 Switching Characteristics Over the Operating Rangel3, 4]
Parameters
7C279-3S
Min.
Max.
Description
tAA
Address to Data Valid (Latched Mode)
teo
Clock to Output Valid (RegisteredMode)
tHZCS
Chip Select Inactive to High Z
35
35
15-
tACS
tAR
Chip Select Active to Output Valid
15
Address Setup to Dock Rise (RegisteredMode)
tRA
Address Hold from Clock Rise (RegisteredMode)
tADH
Data Hold from Dock Rise (RegisteredMode)
tsu
Address Setup to ALE Inactive (Latched Mode)
tHD
tpu
Address Hold from ALE Inactive (LatchedMode)
tpD
Chip Enable Inactive to Power Down
toHLll ]
Output Hold from Address Change (Latched Mode)
tpWA
ALE Pulse Width
tcEse
Chip Enable Setup to Clock Rise
tcESL
tCEv
Chip Enable Setup to Latch Close
Chip Enable to ALE Active
40
Notes:
8. Applies only when the synchronous (lis) function is used.
9. These parameters apply to the 7079 only.
7C279 SS
Max.
Min.
55
55
20
20
20
20
10
10
5
10
10
0
0
20
10
10
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
30
10
10
60
10. Applies only when the asynchronous (Il) function is used.
11. tAA and tOR apply only when the latched mode is selected.
3-141
Units
ns
60
50
40
0
10
10
10
Max.
45
45
10
10
5
10
10
0
3
6
5
5
10
0
Chip Enable Active to Power Up
7C279 4S
Min.
ns
ns
ns
ns
ns
ns
o
::::!!:
o
a::
a.
•
CY7C277
CY7C279
::!p.::~
;'iii CYPRESS
,
SEMlCamUCTOR
Architecture Configuration Bits
Architecture
Bit
ALE
Device
7C277
Dl
ALE
7C279
Dl
ALEP
7C277
D2
ALEP
7C279
D2
E/Es
7C277
Do
Architecture Verify
D7- Do
O-DEFAULT
l=PGMED
O=DEFAULT
1-PGMED
O=DEFAULT
1-PGMED
O-DEFAULT
1 =PGMED
O-DEFAULT
1 =PGMED
Fuuction
Input 'fransparent
Input Latched
Input Registered
Input Latched
ALE = Active HIGH
ALE - Active LOW
ALE - Active mGH
ALE = Active LOW
Asynchronous Output Enable (E)
Synchronous Output Enable (Es)
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
7FFF
8000
Data
Control Byte
Architecture Byte (8000)
D7
C7 Q; Cs
Do
C! C3 C2 Cl Co
Timing Diagram CY7C277 (Input Latched)[12]
ALE
lOs
(SYNCH)
CP
00- 0 7 - - - - - - - ' ' - - - - - - '
tH~~~_t~__E_____
lOs ________________________________________________
(ASYNCH)
C277-10
Note.:
12. ALE is shown with positive polarity.
3-142
CY7C277
CY7C279
~
··~PRFSS
.
~_'I
SEMICalDUCfOR
Timing Diagram CY7C277 (Input Transparent)
Ao - A14
---
ES
(SYNCH)
CP
II)
:E
oa:
Il.
ES
(ASYNCH) - - - - - - - - - - - - - - - - - - - - - - - - '
C277-1'
Timing Diagram CY7C279 (Registered)[12]
Vcc
SUPPLY
CURRENT --:----:_
50%
CS _ _ _"
00
-
D7
Ao-A14
--.;...,;;..-<'--_+-J
_ _ _ _J
CP
Timing Diagram CY7C279 (ALE)
Vcc
SUPPLY
CURRENT --:---:-""'------tCEV
-------.1
CS _ _-J'\
HIGHZ
Ao- A14
---+----'
C277-13
ALE
3-143
CY7C277
CY7C279
Programming Information
Prograinming support is available from Cypress as Well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Functlon!13]
Mode
Read or Output Disable
A14 -
Otber
Al4 -
At
At
Read
A14 - Ao
0,-0,
E,Es,orCE
CPorCS
ALE or CPo ALE
nY
PGM
Vpp
07- 0 0
VIL
VIH
VlL
0,-00
Output Disable
A14 - Ao
VIH
X
X
HighZ
Program
A14 -Ao
VIlIP
VlLP
Vpp
0,-00
Program Verify
AI4-Ao
VlLP
VlllPlVu.p
Vpp
0,-00
VIlIP
Vpp
HighZ
VIlIPIVILP
Vpp
0,-00
Program Inhibit
A14 - Ao
B1ankOleck
A14 -Ao
VIlIP
VILP
Noles:
13. X = "don't care" but not to exceed Vee :1:5%.
At
At
A,
At
Ao
Ae
A"
At
At
Ao
Do
Dt
DIP
LCClPLCC (Opaque Only)
Top View
Top View
vee
At.
Au
At.
At.
Vpp
A" 5
A" 8
A< 7
A" 8
At 9
l'!lIIl
9F'i'
NC
At4
~
0.
Do
Do
Dt
D.
GIIID
Do
Do
7C277
7C279
10
11
12
0
o8'~~&:'r:rtr
C277-14
Figure 1. Programming Pinouts
3-144
At.
At.
At.
NC
~
9F'i'
D,
De
C277-15
CY7C277
CY7C279
-=--.
5
_
;'~PR£§
F SEMICONDUCI'OR
'iYpical DC and AC Characteristics
NO~DACCESSTIME
VS. SUPPLY VOLTAGE
NORNUUJZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED sUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
w
1.2
:;
/
0
w
N 1.2
:::;
<
:;
/
a: 1.0
0
z
0.8
1/
0.6
4.0
/
4.5
Jl1.11-----i-------j
~ 1.0
o
Ii;l
~
~
a:
oz
TA = 25°C
f = fMAJ(
5.5
1.6
w
~ 1.0
<
:;
a:
0 0.8
0.6
- 55
0.4
4.0
<60
OUTPUT SOURCE CURRENT
vO.VOLTAGE
4.5
30.0
50
25.0
'5
40
g 20.0
~
30
:::;
@ 20
~
o
1.0
~
r-....
~ 10
0
5.5
2.0
/
15.0
5.0
4.0
OUTPUT VOLTAGE (V)
V
/
/
~ 10.0
'" "
3.0
6.0
TYPICAL ACCESS TIME CHANGE
OUTPUT LOADING
~
~
o
5.0
VS.
~
-- '"""
25
125
AMBIENTTEMPERATURE (OC)
Q.
TA = ~5°C
SUPPLY VOLTAGE (V)
()
z
o
0.6
AMBIENT TEMPERATURE (OC)
.§.
-
a:
~
:;
0
~
0~5~5----2~5------1J25
6.0
NORMALIZED SET·UP TIME
vo. TEMPERATURE
i=
D. 1.4
:::;
.,!.
w
en 1.2
:E
-=
a:
I
5.0
II)
o 0.8
w
SUPPLY VOLTAGE (V)
w
-
i=
Jl1.4
/
/
200
TA=25°C
_
V~e=4i5V
400
600
800 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
< 175
.§. 150
I-
z
w 125
a:.::~
Z
./
100
75
/'
iii
~ 50
~
~
o
25
~
/
I
1/ 1.0
o
0.0
Vee = 5.0V
TA=25°C -
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
=7-16
3-145
CY7C277
CY7C279
,::;~~
_
. , SEMICONDUCIDR
Ordering Information!14]
Speed
(os)
30
40
50
CY7C277 - 30DC
Package
1YPe
D22
CY7C279- 35DC
D22
CY7C277-30JC
J65
CY7C279-35JC
J65
CY7C277 - 30PC
P21
CY7C279-35PC
P21
CY7C277-30WC
W22
CY7C279-35WC
W22
CY7C277-40DC
D22
CY7C279-45DC
D22
CY7C277-3OJC
J65
CY7C279-45JC
J65
CY7C277 - 30PC
P21
CY7C279-45PC
P21
CY7C277-40WC
W22
CY7C279-45WC
W22
CY7C277 -4ODMB
D22
CY7C279-45DMB
D22
CY7C277 -40KMB
K74
CY7C279-45KMB
K74
Ordering Code
Operating
Range
Speed
(ns)
Commercial
35
Commercial
45
Military
Package
Ordering Code
1YPe
Operating
Range
Commercial
CY7C277 -4OLMB
L55
CY7C279-45LMB
L55
CY7C277-4OQMB
CY7C279-450MB
055
CY7C277-40TMB
055
T74
CY7C279-45TMB
T74
CY7C277-40WMB
W22
CY7C279-45WMB
W22
CY7C277 - 50DC
D22
CY7C279-55DC
D22
CY7C277 - 50JC
J65
CY7C279-55JC
J65
Commercial
55
CY7C277 - 50PC
P21
CY7C279- 55PC
P21
CY7C277-50WC
W22
CY7C279-55WC
W22
CY7C277-50DMB
D22
CY7C279-55DMB
D22
CY7C277-50KMB
K74
CY7C279-55KMB
K74
CY7C277-50LMB
L55
CY7C279-55LMB
L55
CY7C277-500MB
055
CY7C279-550MB
055
CY7C277-50TMB
T74
CY7C279-55TMB
T74
CY7C277-50WMB
W22
CY7C279-55WMB
W22
Military
Notes:
Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
14.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
Device
Parameters
Subgroups
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
ISB!9]
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
7C277
tSA
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
tHA
7C279
teo
tAR
tRA
tDlIA
Document #:1 38-00085-D
3-146
Commercial
Military
Commercial
Military
CY7C281
CY7C282
CYPRESS
SEMICONDUCTOR
1024 X 8 PROM
• Capable ofwitbstanding > 1500V static discbarge
Features
• CMOS for optimum speed/power
• Highspeed
-30ns (commercial)
-45 ns (military)
Functional Description
The CY7C281 and CY7C282 are highperformance 1024-word by 8-bit CMOS
PROMs. They are functionally identical,
but are packaged in 300-mil and 600-miIwide packages respectively. The CY7C281
is also available in a 28-pin leadless chip
carrier. The memory cells utilize proven
EPROM floating-gate technology and
byte-wide intelligent programming algorithms.
The CY7C281 and CY7C282 are pJug-in replacemeots for bipolar devices and offer the
advantages of lower power, superior perfonnance, and programming yield The
EPROM cell requires only 13.5V for the supervoltage, and low current requirements
• Lowpower
-495 mW (commercial)
- 660 mW (military)
• EPROMtechnologyl00%
programmable
• Slim 300-mil or standard 600-mil DIP
or 28-pin LCC
• 5V:!: 10% Vee. commercial and
military
• TTL-compatibleI/O
• Direct replacement for bipolar
PROMs
Logic Block Diagram
allow for gang programming. The
EPROMcells allow each memory location
to be tested 100% because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming,
the product will meet DC and ACspecification limits.
Reading is accomplished by placing an active LOW signal on CSl and CS2, and active HIGH signals on CS3 and CS4. The
contents of the memory location addressedbythe address lines (Ao - A9)will
become available on the output lines (00
- 07).
Pin Configurations
DIP
ThpView
0,
0"
ROW
PROGRAMMABLE
DECODER
ARRAY
MULTIPLEXER
o.
A7
vee
""""
""""
A,
(;8,
(;8.
CS3
CS,
As
0,
Ao
As
As
o.
o.
00
0,
1----------'
DECODER 1-_________-'
COWMN
0,
o.
0,
03
GND
00
C281-2
LCC/PLCC
ThpView
o.
0,
UU
:;e~~z-9:eJf
A,
00
::~------'
Cs.
4 3 2 ~11 282726
25
24
23
7C261
22
8
7C262
21
9
20
10
19
11
12131415161718
Ao 5
As 6
As 7
As
NC
00
(;8,
i:S2
CS,
CS,
NC
0,
0"
o8'!i1~cS'd'"d'
CS3
'"
C281-1
C281-3
Selection Guide
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
I
I
7C281-30
7C282-30
30
100
Commercial
Military
3-147
7C281-45
7C282-45
45
90
120
•
CY7C281
CY7C282
.A~~R
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 6S0Cto +1S0°C
Ambient Thmperaturewith
PowerApplied ....................... -SSOCto +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . - O.SV to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ -O.5Vto +7.0V
DC Input Voltage ...................... -3.0Vto +7.0V
DC Program Voltage (Pins 18, 20) ................... 14.0V
Electrical Characteristics
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > lS00V
(per MIL-STD-883, Method 301S)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Commercial
Ambient
Thmperature
O°Cto +70°C
Vee
SV±10%
Industriat l ]
- 40°C to +8SoC
SV±lO%
Militaryl2]
-SSOCto +125°C
SV±10%
Overthe Operating Rangef3,4]
7C281-30
7C282-30
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0rnA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA
Vrn
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
VJL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
IJX
Input Current
GND~VIN~Vee
-10
+10
loz
Output LeakageCurrent
VOL ~ VOUT ~ VOH, Output Disabled
- 40
+40
los
Output Short Circuit Current[5]
Vcc = Max., VOUT = GND
- 20
- 90
lee
Power Supply Current!6]
Vee = Max.,
IoUT=OrnA
7C281-4S
7C282-4S
Min.
0.4
2.0
Units
0.4
V
V
2.0
0.8
ICommercial
IMilitary
Max.
2.4
V
0.8
V
-10
+10
-40
+40
JAA
JAA
-20
-90
rnA
90
rnA
100
120
Vpp
Program Voltage
13
Vrnp
Program HIGH Voltage
3.0
VILP
Program LOW Voltage
Ipp
Program Supply Current
14
14
V
0.4
0.4
V
SO
SO
rnA
13
3.0
V
Capacitance [4]
Parameters
CIN
CoUT
Description
Thst Conditions
InputCapacitance
UUtputcapacltance
TA - 25°C, f - 1 MHz,
10
Units
pF
Vcc=S.OV
10
pF
Max.
Notes:
1.
2.
3.
Contact a Cypress representative for industrial temperature range
specifications.
TA is the "instant on" case temperature.
See the last page of this specification for Group Asubgroup testing information.
4.
See "Introduction to CMOS PROMs" intbisDataBookforgeneralinformation on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
6. Due to the design of the differential cell in this device, Icc can ouly be
accurately measured on a programmed array.
S.
3-148
CY7C281
CY7C282
·;~PRESS
; ; ?EMICCWUcroR
AC Test Loads and Waveforms!4]
OUTP~~31R1250Q
5V31R1250Q
OUTPUT
30pF
R2
1670
I _
INCLUDING
JIGAND SCOPE
(a)
Equivalent to:
5 PF
I
R2
1670
INCLUDING _
_
JIG AND SCOPE
C281-4
(b) High Z Load
-
• •
ALL INPUT PULSES
'''31~=~ If:~5ns
GND
10%
10%
C281-5
o
THEvENIN EQUIVALENT
II:
Q.
1000
OUTPUT OO--~"'h"'---oO 2.0V
C281-6
Switching Waveforms
Ao-As
ADDRESS
)~
)(
I--
tAA
)(
-
tHZCS
~IACS
C281-7
Switching Characteristics
Over the Operating Rangel2,4]
7C281-30
7C282-30
Parameters
II)
::::!i:
Min.
Max.
Units
tAA
Address to Output Valid
30
45
ns
tHzCS
Chip Select Inactive to High Z
20
25
ns
tACS
Chip Select Active to Output Valid
20
25
ns
Description
3-149
Max.
7C28i-45
7C281-45
Min.
CY7C281
CY7C282
.7l~NDUCK)R
Programming Information
Programmingsupport is available from Cypress as well as from a
numberofthird partysofiwarevendors. Fordetailedprogramming
information, includingalistingofsofiwarepackages, please seethe
PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress
representative.
Thble 1. Mode Selection
Pin Function(7]
A,-J\o
A,-J\o
CS4
cs:!
C~
CSt
PGM
VFY
Vpp
CSt
n,-Oo
Read
A7-Ao
VIH
VIH
VIL
VIL
07- 0 0
Output Disable
Read or Ontput Disable
Mode
Other
07- 0 0
A7-Ao
X
X
VIH
X
HighZ
Output Disable
A7-Ao
X
VIL
X
X
HighZ
Output Disable
A7-Ao
VIL
X
X
X
HighZ
Output Disable
A7-Ao
X
X
X
VIH
HighZ
Program
A7-Ao
VILP
VIHP
Vpp
VILP
D7- D O
Program Verify
A7-Ao
VIHP
VILP
Vpp
VILP
07- 0 0
Program Inhibit
A7-Ao
VIHP
VIHP
Vpp
VII~
HighZ
VILP
D7- D O
A7-Ao
VILP
VIHP
Vpp
Blank Check Ones
A7-Ao
Vpp
VILP
VILP
VILP
Ones
Blank Check Zeros
A7-Ao
Vpp
VIHP
VILP
VILP
Zeros
Intelligent Program
Notes:
7. X = "don't care" but not to exceed Va; ±5%.
DIP
LCC/PLCC
Top View
Top View
~~<"~Jl~~
4 3 2!.,.11 282726
5
6
7
8
9
10
11
25
7C281
7C282
OS,
24
Vpp
23
22
21
VFY
PGM
20
19
12131415161718
NC
D7
D.
C281-9
C281-8
Figure 1. Programming Pinouts
3-150
CY7C281
CY7C282
.~
. ,
~~NDUCfOR
1Ypical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.2
Jl1.1
w
::i:
i=
~ 1.0
1.6
Jl1.4
/
Cl
~ 1.2
~
15
1.0
z
O.B
1/
0.6
4.0
V
4.5
/
~
U
1.2
u
«
z
TA = 25°C
f = fMAJ(
-f
5.0
W
~
a:
0
1.0
6.0
5.5
oZ
60
30.0
50
25.0
w
~
30
0
20
CJ)
....
:J
O.B
....a.
z
-
10
0
1.0
125
2.0
~
~
"""-"
:J
i:d
Cl
"""
"
3.0
4.0
15.0
~
10.0
5.0
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1/
0.0 0
'Z
."..
~ 125
a:
13
~
Z
Cii
75
5
50
o
25
5
/
100
o
f.--
V
1/
7
/
Vcc=5.0V
TA=25°C -
I
V
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
3-151
6.0
200
400
4.0
C281-1O
--
/
Vcc=4.5V _
TA = 25°C
I
I
600 BOO 1000
CAPACITANCE (pF)
<,175
.s150
V
V
OUTPUT VOLTAGE (V)
AMBIENTTEMPERATURE (OC)
5.5
/
g 20.0
'" t'-...
:J
I-""
5.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING'
....
z
U
I
4.5
SUPPLY VOLTAGE (V)
<'
w
"
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
a:
~
a:
:J 40
25
~
"" 0.6
O.B I::------:!-=------,-I
-55
25
125
AMBIENTTEMPERATURE (OC)
.s
0.6
- 55
O.B
'"'"
a:
Cl
N
~
a:
o
1.6
1.4
~
~
NORMALIZED ACCESS TIME
vs. TEMPERATURE
!Jl
w
1----+-------1
Cl
SUPPLY VOLTAGE (V)
w
::i:
i=
NO~DACCESSTDdE
vs. SUPPLY VOLTAGE
1.2
CY7C281
CY7C282
~CYPRESS
~~,
SEMICONDUCTOR
Ordering Information
Speed
(os)
30
Package
1Ype
D14
Ordering Code
CY7C281-30DC
CY7C281-30JC
CY7C281-30LC
CY7C281- 30PC
45
Speed
(os)
Commercial
30
P11
CY7C282-45DC
D12
P13
CY7C282-45PC
Pll
CY7C282-45DMB
D12
P13
D14
CY7C281-45KMB
CY7C281 -45LMB
K73
Commercial
Military
L64
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Subgroups
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
Switching Characteristics
Parameters
Subgroups
tM
tACS
7, 8, 9, 10, 11
7,8,9, 10, 11
SMD Cross Reference
SMD
Number
Suffix
Commercial
D12
CY7C281-45DMB
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Operating
Range
CY7C282-30PC
CY7C281-45PC
Parameters
Package
'JYpe
CY7C282-30DC
J64
L64
CY7C281-45LC
Orderiog Code
J64
L64
D14
CY7C281-45DC
CY7C281-45JC
Operating
Range
Cypress
Number
5962-87651
01JX
CY7C282-45DMB
5962-87651
01KX
CY7C281-45KMB
5962-87651
01LX
CY7C281-45DMB
5962-87651
013X
CY7C281-45LMB
Document#: 38-00056-D
3-152
Military
CY7C285
CY7C289
CYPRESS
SEMICONDUCTOR
65,536 X 8 Reprogrammable
Fast Column Access PROM
Features
Functional Description
• CMOS for optimum speed/power
• Windowed for reprogrammabUity
• Unique fast columD accesl
- tAA = 20 DS (commercial)
- tAA = 2S DS (military)
The CY7C285 and the CY7C289 are
high-perfonnance 65,536 by 8-bit CMOS
PROMs- The CY7C285 is available in a
28-pin 300-mi1 package. It features a
unique fast column access feature that allow access times as fast as 20 os for each
byte in a 64-byte page. There are 1024
pages in the device. The access time when
changing pages will be 65 os. In order to
easily facilitate the use of the fast column
access feature, a WAIT signal will be generated to advise the processor of a page
change. The CY7C289 also incorporates
the fast column access feature and
through the use of the ALE option adds
either synchronous address registers or
asynchronous address latches. The
CY7C289 is particularly well suited to
support applicatioos using the CY7C601
as well as other RISC or CISC microprocessors. It is available in a 32-pin 300-mil
• WAIT signal
• User con6gurable cbip select
decodiDg (7C289)
• EPROM technology. IIM1'1' programmable
• SV :tIll'll> Vee. commercial and military
• TTL-compatible I/O
• Slim 3OO-mil package
• Capable ofwitbstandlng >2001V statIc discharge
package.
The CY7C285 and CY7C289 offer the
adYantage of low power, superior performance, and programming yield The EPROM
cell requires only 12.5V for the super voltage and low current requirements. The
EPROM cells allow for each memory 10eation to be 100% tested, with each location being written into, erased, and repeatedly exercised prior to encapsulation.
Each PROM is also tested for AC perfonnance to guarantee that after customer programming the product will meet
DC and AC specification limits.
Reading the CY7C28S is accomplished by
placing an active LOW signal on the CS
pin. Reading the CY7C289 is accomplished by placing an active LOW signal
on the
pin and by placing active
mGH signals on the CSl or CSz pins as
appropriate. The contents of the memory
location addressed by the address lines
(Ao - AlS) will become available on the
output lines (00 - <>7).
rn
Logic Block Diagram
Pin Configurations
CerDIP
CerDIP
ThpVlew
1'9
Ae
0,
1
Vee
Ae
Ae
1.0
a.
o.
Ae
Ae
1.0
As
Ao.
Ao.
CI
CP/ALE
1'9
00
Or
A,
w.m
a.
0,
a.
CE
As
CS,
w.m
Ao
Do
0.
Da
Oa
GND
A,.
Au
A12
A,.
A,.
A,.
A,
Ae
As
Ao
Vee
1'9
Ae
A,.
Au
A,.
A,.
A,
a.
'lbpVlew
Or
GND
ONO
a.
00
0,
D.
Do
Da
C5a
C2II5-2
O.
Da
0,
C2S5-3
LCC
'lbpVlew
00
LeC
'lbpVlew
~!C~~$~i
Ao
~
: CS1
:cs.~L-
,
~
OND
__...J
00
I
C215-1
CY7C289
ONLY
5
8
7
8
7C2S5
0
28
v:1
28
25
9
24
10
23
11
22
12
21
13
14151617181920
A,.
A,.
A,.
A,.
NC
~
CP/ALE
CS
w.m
0,
GND
od'~c5'd' cfcf
(7C285on1y)
3-153
5
6
7
8
A,As ~o
Ao 11
GND
Do
0
7C28Q
'2
13
21
14151617181920
-'12
A,.
A'4
A,.
~,
.WlQT
Or
Do
58'~1fd'd'd'
C2II5-4
----------------------------.!
CI
----------------1
Ae
C2S5-5
(I)
==
o
a:
Q.
CY7C285
CY7C289
~
~~PRF.SS
~, ~camUCl'OR
Selection Guide
Description
Page Access Time
Maximum Access TIme (ns)
Column Access Time
Maximum Operating Current (mA)
7C285-65
7C289-65
65
20
7C285-75
7C289-75
75
25
180
180
200
I Commercial
I
Military
7C285-85
7C289-85
85
35
180
200
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(CY7C285: Pin 28 to Pin 14)
(CY7C289: Pin 32 to Pin 12, 21) .......... - O.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
DC Program Voltage
(CY7C285: Pin 22; CY7C289: Pin 26) ................ 13.0V
Electrical Characteristics
UVExposure ............................ 7258Wsec/cm2
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >2oomA
Operating Range
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
IndustriajI]
- 40°C to +85°C
5V± 10%
Militaryf2]
- 55°Cto +125°C
5V± 10%
Range
Commercial
Over the Operating Rangel3, 4]
7C285-65, 75, 85
7C289-65, 75, 85
Parameters
Description
Min.
Thst Conditions
Max.
Units
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 mA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 mA[S)
V
VIH
Input HIGH Level
Guaranteedlnput Logical HIGH Voltage
for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
VCD
Input Diode Clamp Voltage
IIX
Input Load Current
GND.s VIN 5. Vee
-10
+10
loz
Output LeakageCurrent
GND .s VOUT 5. Vec, Output Disabled
- 40
+40
IJA
IJA
los
Output Short Circuit Currentf6)
Vee = Max., VOUT = GND
-20
- 90
mA
Icc
Vee Operating Supply Current
Vee = Max., lOUT = 0 mA
180
mA
200
mA
2.0
0.4
V
Vee
V
0.8
V
Note 4
I Com'l
LMil
V
Capacitance(4)
Parameters
CIN
CoUT
Description
InputCapacitance
OutputCapacitance
Thst Conditions
TA=25°C,f=IMHz,
Vee=5.0V
Max.
10
10
Units
pF
pF
Notes:
1. Contact a Cypress representative for industrial temperature range
specification.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See Introduction to CMOS PROMs in this Data Book for general information on testing.
5. IOL=6.0rnAformilitary7C285,IoL=4.0rnAforcommercial7C289,
and IOL = 3.0 rnA for military 7C289.
6. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3-154
CY7C285
CY7C289
~
:~
iECYPRESS
F SEMICONDUCTOR
AF
_
AC Test Loads and Waveform[4, 7]
Rl5000
(R16580MiI)
Rl5000
(Rl6580 Mil)
5V
5V
OUTPUTG--.......,r--..
30 P
FI
INCLUDING
JIGAND _
o---~w..-,
5PFI
R2
3330
(4030 Mil)
INCLUDING
JIG AND _
SCOPE -
Equivalent to:
ALL INPUT PULSES
OUTPUTo---r--"
3.0V -----::I~9O%~----R2
GND
3330
(4030 Mil)
SCOPE -
(a)
THEVENIN EQUIVALENT
(b) High Z Load
C285-6
C285-7
2500
OUTPUT OO---"IY\I\I'_--QO 1.9V
2000
OUTPUT OO---"IY"",,,,_--QO 2.0V
Military
Commercial
Notes:
7.
NotethatRI andR2forthe7C7C289willbe96IQ and510Q for commercia! (Thevenin equivalent is 333Q to 1.73V) and 1250Q and
5880 for military (l1Ievenin equivalent is 400Q to 1.6V).
7C285 Switching Characteristics Over the Operating Rangel3, 4J
7C285-65
Parameters
Description
Min.
Max.
7C285-75
Min.
Max.
7C285-85
Min.
Max.
Units
tRAC
Slow Address Access Time (~ - AIS)
65
75
85
ns
tCAA
FastAddressAccessTime(Ao - As)
20
25
35
ns
tHZCS
Output High Z from CS
15
20
25
ns
tACS
Output Valid from CS
15
20
25
ns
tWD
Wait Delay from First Slow AddressChange
20
25
35
ns
tDW
Wait Hold from Data Valid
tww
Wait Recovery from Last AddressChange
tpWD
Wait Pulse Width
0
0
0
90
12
10
ns
120
110
15
ns
ns
7C289 Switching Characteristics Over the Operating Rangel3, 4J
7C289-65
Min.
7C289-75
Max.
Units
Slow AddressAccess Time (~ - AIS)
65
75
85
ns
tCAA!
FastAddressAccessTinle(Ao - As)
20
25
35
tARI
Register Address Set-Up Time
tRAI
tAR2[8J
Register Address Hold Tinle
Register Address Set-Up
tRA2[8J
Register Address Hold Tinle
2
Description
Max.
Min.
Max.
7C2119-85
tRACI
Parameters
Min.
ns
4
8
ns
6
6
10
ns
8
10
15
ns
4
8
ns
2
tHZCS
Output High Z from Clock mGH
20
20
25
ns
tACS
OutputVaiidfromClockmGH
20
20
25
ns
tpwc
Clock Pulse Width
11
13
15
ns
tADH
Data Hold Tinle
5
5
5
ns
tSCE
Chip Enable Set-Up
2
4
8
ns
tHCE
Chip Enable Hold
6
6
10
ns
Notes:
8. Parameters for the 7C289 with tAS option enabled.
3-155
CY7C285
CY7C289
5L~PRFSS
~I
SEMlCCtIDUClDR
Switching Characteristics for the 7C289 Over the Operating Rangel3, 4] (continued)
7C289-6S
7C289-75
7C289-85
Max.
Units
tWDl
tWD3[9]
Wait Delay from Clock LOW
0
19
0
25
0
30
ns
Wait Delay from Clock HIGH
0
16
0
20
0
25
ns
tRAd IO]
Slow AddressAccess Time (~ - AIS)
65
75
85
ns
tCAA2[10]
FastAddressAccessTime(Ao - As)
22
30
35
ns
tACE[lO]
Output Valid from CE
20
25
30
ns
30
ns
Parameters
Description
Min.
Max.
Min.
Max.
Min.
tHZCE[lO]
Output High Z from CE
tAL[IO]
Address Set-Up Time
5
8
12
ns
t!A[IO]
Address Hold Time
10
12
15
ns
tIL[IO]
ALE Pulse Width
10
12
15
ns
tpWD[lO]
Wait Pulse Width
10
12
15
tWD2[lO]
Wait Delay from First Slow AddressChange
tDwz[lO]
Wait Hold from Data Valid
twwZ[lO]
Wait Recovery from Last AddressChange
tCES[IO]
CE Set-Up Time for High Z Outputs
25
20
21
0
25
0
8
4
Architecture Configuration Bits (7C289 only)
Architecture
Bit
TAS
ALE
ALEP
WAITC
WAITP
Architecture Verify
00- 0 7
CS1E
O=Erased
Address Set-Up < AddressHold
1 =PGMED
Address Set-Up > Address Hold
Dz
O=Erased
Input Registered (ADDR, CE, CSt. CSz)
1 =PGMED
Input Latched (ADDR, CE, CSt. CSz)
D3
o= Erased
ALE = LOW, Addresses Latched
1 =PGMED
ALE = HIGH, Addresses Latched
D4
o = Erased
WAIT Follows the Falling Edge of CP
l=PGMED
WAIT Follows the Rising Edge of CP
0= Erased
WAIT Signal Active LOW
l=PGMED
WAIT Signal Active HIGH
D6
D?
CS2E
Function
DI
Ds
O=Erased
CSl (Pin 24) = LOW, Disables Outputs
l=PGMED
CSl (Pin 24) = HIGH, Disables Outputs
O=Erased
CSz (Pin 16) = LOW, Disables Outputs
1 =PGMED
CSz (Pin 16) = HIGH, Disables Outputs
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
FFFF
10000
Data
Control Byte
Architecture Byte (loo00H)
D7
Do
C7 ~ Cs ~ C3 C2 Cl
Notes:
9. Parameters for the 7C289 with WAITCoption enabled.
10. Parameters for the 7C289 with ALE option enabled.
3-156
120
110
Co
ns
ns
0
90
3
ns
30
ns
ns
CY7C285
CY7C289
~~PRESS
~,
SEMICONDUCTOR
Switching Waveform for the 7C285
en
tRAG
~
o
)V
a:
r-
D.
1cAA -
tww
I--
two
-tDW~
tPWD
WAIT
C285-9
Switching Waveforms for the 7C289
Fast Column Access
----------~)(~----~)(~-----VALID
VALID
HIGHZ
~-----1cAA1 ----~
CP
--_-/
WAIT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HIGH
C2B5-8
3-157
CY7C285
CY7C289
Switching Waveforms for the 7C289 (continued)
Using WAIT
CS1.CS2
={---IAR2
----------~)(~--~)(~-----
IARl
VALID
ALE Option
CE
00- 0 7
__
~
____________J
~-As
ALE
C285-11
3-158
CY7C285
CY7C289
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
7C285 and 7C289 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM is
exposed to sunlight or fluorescent lighting for extended periods
of time.
The recommended dose of ultraviolet light for erasure is a wavelength of2537 angstroms for a minimum dose (UV intensity multipled by exposure time) or 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The 7C285 or 7C289 needs to be within
1 inch of the lamp during erasure. Permanent damage may result
if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wseclcm2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
'Illble 1. CY7C285 Mode Selection
Pin Function
Read or Output Disable
07- 00
Au
Vpp
A14
LATCH
CS
WAlT
PmI
VFY
07-0.
AIS
AIS
AIS
A14
VIL
One
07-00
A14
VIL
Pulse LOW
A14
VIH
Output
07-00
HighZ
Program
Vpp
VILP
VILP
VIHP
Program Inhibit
Vpp
VILP
VIHP
VIHP
Program Verify
Vpp
VILP
VIHP
VJLP
Blank Check
Vpp
VJLP
VIIlP
VILP
Mode
Other
Read (within a page: A<; - AlS stable)
Read (page break: A<; - AlS transition)
Output Disable
D7- DO
HighZ
07- 0 0
Zeros
'Illble 2. CY7C289 Mode Selection
Pin Functionl l1J
Read or Output Disable
~
As
As
A4
A4
A3
A6
A<;
A<;
A<;
A<;
A<;
A<;
A<;
A<;
A<;
A<;
A<;
As
Au
Vpp
A14
LATCH
As
~
A3
AlS
A14
As
~
A3
AlS
A14
As
~
A3
Au
A14
As
~
A3
AlS
A14
As
As
As
As
As
As
As
~
A3
AlS
A14
~
A3
A14
~
A3
AIS
AIS
~
A3
Vpp
VILP
~
A3
Vpp
VILP
~
A3
Vpp
VIHP
~
As
As
As
As
As
As
As
As
As
As
As
As
As
~
A3
Vpp
VILP
Program Address Set-Up/Hold Option
VHH
VIHP
VJLP
X
X
VJLP
Vpp
VILP
Program Address/Latch Option
VHH
VIHP
VIHP
X
X
VJLP
Vpp
VILP
Program ALE Polarity Option
VHH
VIHP
VILP
X
X
VIHP
Vpp
VILP
Program Edge nigger for WAIT
VHH
VILP
VIHP
X
X
VILP
Vpp
VILP
Program WAIT Polarity
VHH
VJLP
X
X
VIHP
Vpp
VILP
Program CSlo CSz Polarity
VHH
VIHP
VIHP
VIHP
CS2
CSl
VIHP
Vpp
VIl.P
Mode
Other
At
At
Registered Input Read (FCA)
~
Registered Input Read (page break)
~
Latched Input Read (PCA)
~
Latched Input Read (page break)
Ag
Output Disable
~
Output Disable (default architecture)
~
Output Disable (default architecture)
~
Program
Program Inhibit
Ag
Ag
Program Verify
~
Blank Check
3-159
A14
•
U)
o
==
a:
D.
CY7C285
CY7C289
1llble 2. CY7C289 Mode Selection (continued)
Pin FunctionlllJ
CS1
PGM
C~
CE
CP/AL
WAIT
GND
NC
NC
VFY
n,-Do
Registered Input Read (FCA)
VIL
VIL
VIL
CLK
One
07- 0 0
Read or Output Disable
Mode
Other
0,-00
Registered Input Read (page break:)
VIL
VIL
VIL
CLK
Zero
07- 0 0
Latched Input Read (FCA)
VIL
VIL
VIL
LATCH
One
07- 0 0
Latched Input Read (page break)
VIL
VIL
VIL
LATCH
Pulse LOW
07- 0 0
Output Disable
X
X
Vrn
X
Output
HighZ
Output Disable (default architecture)
X
VIL
X
X
Output
HighZ
Output Disable (default architecture)
VIL
X
X
X
Output
HighZ
Program
VILP
VILP
X
X
Vrnp
D7 - Dl
ProgramInhibit
Vrnp
VILP
X
X
Vrnp
HighZ
Program Verify
Vrnp
VILP
X
X
VILP
07- 0 1
Blank Check
Vrnp
VILP
X
X
VILP
Zeros
ProgramAddress Set-Up/Hold Option
VILP
VILP
X
X
Vrnp
X
ProgramAddress/Latch Option
VILP
VILP
X
X
Vrnp
X
Program ALE Polarity Option
VILP
VILP
X
X
Vrnp
X
Program Edge ltiggerfor WAIT
VILP
VILP
X
X
Vrnp
X
Program WAIT Polarity
VILP
VILP
X
X
Vrnp
X
Program CSJ, CS2 Polarity
VILP
VILP
X
X
Vrnp
X
Note:
11. X = "don't care" but not to exceed V cc ±5%.
DIP
DIP
Vee
""""
""""
A10
An
A""A"
A7
At!
At!
4
At!
As
Ao
As
A,a/A,.
Ao
vee
A,.
A11
A7
4
A12/A14
A1a1A15
LATCH
Vpp
NC
NC
A,
LATCH
Vpp
PGM
VFY
As
PGM
".,
~
VFY
Do
0,
D.
D.
A,
".,
GND
0"
D.
Do
Do
GND
Ds
0,
02
D.
D.
0,
C285-14
As
As
C285-12
~
GND
GND
As
Ao
As
LCC
LCC
.f~::~.ii
~1<::f>~i
5 43 2
6
7
NC8
c1,3231~9~ A,VA,.
o
7C285
28
At!
AdA,.
Ao
27
LATCH
26Vpp
As9
25 NC
A,
10
24 PGM
"., 11
23 VFY
GND 12
22 ~
Do 13
21
GND
14151617181920
As
NC
As
A,
".,
GND
D.
432,1,323130
29
5
28
6
27
7
7C269
26
8
25
9
24
10
23
11
22
12
21
13
14151617181920
0
,....C\lCO (1')"1:1'11)
00 l;ZOCO
Figure 1. Programming Pinouts
3-160
~
AelA11
AoIA,.
LATCH
Vpp
NC
PGM
VFY
07
D.
C285-15
CY7C285
CY7C289
~
~~PRESS
~, SEMICONDUCTOR
Ordering Information[12]
Speed
(ns)
65
75
85
Package
1Ype
Operating
Range
Speed
(ns)
CY7C285-65PC
P21
Commercial
65
CY7C285-65WC
W22
75
CY7C285-75PC
P21
CY7C285-75WC
W22
CY7C285-75DMB
D22
CY7C285-75LMB
L55
CY7C285-75QMB
Q55
CY7C285-75WMB
W22
CY7C285-85PC
P21
CY7C285-85WC
W22
CY7C285-85DMB
D22
Ordering Code
CY7C285-85LMB
L55
CY7C285-85QMB
Q55
CY7C285-85WMB
W22
Commercial
Military
85
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
1,2,3
VIL
IJX
Ioz
Icc
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tAA
7,8,9, 10, 11
7,8,9, 10, 11
tCAA
tACS
tACE[13]
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Notes:
12. Most of these products are available iniodustrial temperature range.
Contact a Cypress representative for specifications and product availability.
13. CY7C289 only.
Document#: 38-00097-E
3-161
Package
'JYpe
Operating
Range
CY7C289-65WC
W32
Commercial
CY7C289-75WC
W32
Commercial
CY7C289-75DMB
032
Military
CY7C289-75LMB
L55
Ordering Code
CY7C289-75QMB
Q55
CY7C289-75WMB
W32
CY7C289-85WC
W32
Commercial
CY7C289-85DMB
032
Military
CY7C289-85LMB
L55
CY7C289-85QMB
Q55
CY7C289-85WMB
W32
•
U)
:E
o
a::
Il.
CY7C286
CY7C287
CYPRESS
65,536 x 8 Reprogrammable
SEMICONDUCTOR
Asynchronolls/Registered PROMs
Features
Functional Description
• CMOS for optimum speed/power
• Windowed for reprogrammabllity
• Hlgbspeed
- tSA = 45 ns (7C287)
- teo = 15 us (7C287)
-tACe = 50 ns (7C286)
The CY7C286 and the CY7C287 are
high-performance 65,536 ~ 8-bit CM~S
PROMs.. The CY7C286 IS configured. m
the JEDEC-standard. 512K E~ROM p~out and is available m a 28-pm, 600-mi1
package. Power consumption is 120 rnA in
the active mode and 40 rnA in the standby
mode. Access time is 50 ns. The CY7C287
has registered outputs and operates in the
synchronous mode. ~ can also be programmed into the synchronous mode, Es·
It is available in a 28-pin, 3OO-mi1 package. The address set-up time is 45 us a~d
• Lowpower
-120 mA active
-40 mA standby (7C286)
• On-diip, edge-triggered output
registers (7CZ87)
• Programmable synchronous (7C287
only) or asynebronous output enable
• EPROM teebnology, 100%
programmable
• 5V :t10% Vee, commerdaland
military
• 'fTL..compatible I/O
• Slim 300-mll package (7C287)
• Capable ofwithstaDding >ZOOIV static disebarge
~etimefromclockHIGHtooutputvahd
15 ns.
Both the CY7C286 and the CY7C21!7 are
available in a cerDIP package eqUIpped
with an erasure window to provide reprogrammability. When exposed to UV light,
the PROM is erased and can ~.e reprogrammed. The memory cells utilIZe proven EPROM floating-gate technology and
byte-wide intelligent programming algorithms.
IS
The CY7C286 and the CY7C287 01!er
the advantage of low power, supenor
performance, and programming yield
The EPROM cell requires only 12.5V.for
the supervoltage and low current .reqUIrements allow for gang programmmg. The
EPROM cells allow for each memory
location to be 100% tested with each
location being written into, erased, and
repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that t.h~ PI"?duct will meet DC and AC speCification
limits after customer programming.
Reading the CY7C286 is accomplished by
p1ac·
active LOW signals on the
and ~ pins. Reading the CY7C287 is accomplished by placing an active LOW signat on Ms. The contents of the memory
location addressed by the address lines
(Ao - AlS) will become available on the
output lines (00 - 0,) on the next rising
of CPO
un
Pin Configurations
Logic Block Diagram
CerDIP
Top View
A,._....---,
A14'"
A1.'"
A12....
Au ....
-'I.
A,.
A,
x
ROW
Ae
AIlDAEIl8
Ao
Ao
Ao
At
A,o-
Ae-
AeA,_
0.
AeAoy
AoCCll.- ~====~
Ao- AIlDAEIl8
t-
Ae-
A,_
,___________ _
.
,
Oz
00
0,
0.
0,
28
25
5
24
6 7C266 23
22
7
8 0 21
8
20
10
18
11
18
12
OND
Vee
"'A,..
1
2
3
4
Ao
Ao
A,
Ao
Ao
Ao
Ao
Ae
A"
tIE
A,o
Vee
A,.
A"
A,.
A,.
A,.
A,.
Ao
A,At
CE
CP
~
Ao
0Oe
Oe
0.
0.
0Oe
Oe
00
0,
Oz
o.
OND
0.
C286-5
C286-2
\CY>C21I1IONI:i)
CE~~J--_---"":=--";':-:1~-:-:1
-~
Ao
28
ro
O.
Ao-~~~---1
,
A,
1
2
3
4
CerDIP
ThpView
- ------------- -- -- --
LeC
Top View
LeC
Top VIew
.t~;~;$I~
~~~~$;~
Ao
Ao
C288-1
A"
NC
tIE
4"
Ao5
Ao 6
Ao 7
NC
a
Az8
A, 10
Ao 11
OND 12
00 >13
3 2,\323130
-
29 A,.
7C287
28' -'I.
27 A,.
0
29
A,.
I!5NC
24 CP
23
22
21
~
0,
OND
14151817181920
«5" d'~c5'd' &'d'
C288-4
3-162
CY7C286
CY7C287
~
~~PRF.SS
~# SEMICONDUCIOR
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (mA)
I
I
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
MaximumOperatingCurrent(mA)
Com'l
Mil
I Com'l
I
7C286-50
50
120
7C286-60
60
120
150
7C286-70
70
90
120
7C287-45
45
15
120
7C287-55
55
20
120
150
7C287-65
65
25
120
150
Mil
II)
:::.'E
o
a::
G..
Maximum Ratings
(Above which tbe useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperaturewitb
Power Applied. . . . . . . . . . . . . . . . . .. . ... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
(Pin 28 to Pin 14)
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
DC Program Voltage (Pin 22) . . . . . . . . . . . . . . . . . . . . . .. 13.0V
Electrical Characteristics
Parameters
Operating Range
Range
Commercial
IndustriaJ 1 I
Militaryt~1
Ambient
Thmperature
O°Cto +70°C
- 40°Cto +85°C
- 55°C to + 125°C
Vee
5V± 10%
5V± 10%
5V± 10%
Over the Operating Rangel3]
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
VeD
loz
Input Load Current
Input Diode Clamp Voltage
Output Leakage Current
los
Output Short Circuit
Current
Vee Operating
Supply Current
lee
(7C286)
UVExposure ............................ 7258Wsec/cm2
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Metbod 3015.2)
Latch-UpCurrent ............................ >200mA
(7C287)
Icc
Vee Operating
Supply Current
IsBLOI
Standby Supply Current
7C286-50
7C286-60
7C287-45
7C287-55
Thst Conditions
Min. Max. Min. Max.
2.4
2.4
Vee = Min., IOH = - 2.0 mA
0.4
0.4
Vee = Min.,loL = 8.0mA Com'l
0.4
Vee - Min., IOL - 6.0mA Mil
Guaranteed Input Logical HIGH 2.0 Vee 2.0 Vee
Voltage for Inputs
Guaranteed Input Logical LOW
0.8
0.8
Voltage for Inputs
-10 +10 -10 +10
GND ~ VIN ~ Vee
Note 4
-40 +40 -40 +40
GND ~ VOUT ~ Vee,
Output Disabled
-20 - 90 -20 -90
Vee = Max., VOUT = GNDPJ
Com'l
Mil
Com'l
Vee-Max.,
lOUT = OmA
Mil
Vee = Max.,CE = HIGH Com'l
lOUT = OmA
Mil
Vee = Max.,
lOUT = OmA
Notes:
1. TA is the "instant on" case temperature.
2. Contact a Cypress representative for industrial termperature range
specifications.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
3-163
120
120
40
120
150
120
150
40
50
7C286-70
7C287-65
Min. Max. Units
2.4
V
0.4
V
0.4
V
2.0
Vee
0.8
V
-10
+10
J.IA
-40
+40
J.IA
-20
- 90
mA
90
120
120
150
30
40
mA
mA
mA
See Introduction to CMOS PROMs for general information on
testing.
Short circuit test should not exceed 30 seconds.
Only the CY7C286 has a standby mode.
CY7C286
CY7C287
t&;~PRfSS
~,
SEMlCONDUCl'OR
Capacitance [4]
Parameters
Description
InputCapacitance
UutputCapacltance
CIN
COUT
Max.
Thst Conditions
TA - 2S°C,f -1 MHz,
Vcc=5.0V
Units
pF
pF
10
10
AC Test Loads and Waveform[4]
Al500.o.
(Al 658.0. MIL)
Al500.o.
(Al65Bn MI~
5V
5V
OUTPUTO----1r---+
30PFI
INCLUDING
JIGANO _
A2
333.0.
(4=
MI~
5PFI
INCWOING
JIGANO _
SCOPE -
3.OV
R2
333.0.
(403!l.
----.J.o. . 9O%=----..
GNO
MI~
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo---r---+
(b) High Z Load
C286-6
0286-7
THEvENIN EQUIVALENT
2=
OUTPUT OO--....·\I\N"'"---oO 1.9V
OUTPUT 00---"'·\I\o.,.":-,,,"---o02.OV
Military
Commercial
7C286 Switching Characteristics Over the Operating Range[3, 4]
7C286-50
Parameters
Description
tACC
AddressAccess Time
tCE
Output Valid from CE
Min.
LCommercial
7C286-60
7C286-70
Max.
Units
50
60
70
ns
50
60
70
ns
60
70
ns
Max.
Min.
I Military
Max.
Min.
tOE
Output Valid from OE
18
20
2S
ns
tDF
Output 'fri-State from CE/OE
18
20
2S
ns
tpu
Chip Enable to Power-Up
tpD
Chip Disable to Power-Down
0
0
40
ns
0
60
50
ns
7C287 Switching Characteristics Over the Operating Range[3, 4]
7C287-45
Parameters
Description
Min.
7C287-55
Min.
Max.
7C287-65
Min.
Max.
Units
tSA
Address Set-Up to Clock HIGH
45
55
65
tlIA
Address Hold from Cock HIGH
0
0
0
tco
Cock HIGH to Output Valid
15
20
2S
ns
tHZE
Output High Z from E
15
20
2S
ns
tDOE
Output Valid from E
15
20
2S
ns
tpwc
Cock Pulse Width
15
20
25
ns
tSEs[7]
Es Set-Up to Cock HIGH
12
15
18
ns
tHEs[7]
Es Hold from Clock HIGH
5
8
10
tHZC[7]
Output High Z from CLKlEs
tcoi7]
Output Valid from CLKIEs
Note:
7.
Max.
Parameters with synchronous Es option.
3-164
ns
ns
ns
20
2S
30
ns
2O!
2S
30
ns
CY7C286
CY7C287
ua.:~PRESS
~ifF
SEMlCONDUCTOR
Architecture Configuration Bits
Architecture
Bit
7C287
ElEs
Architecture Verify
Do
Device
Do
Function
I 0: Erased
Asynchronous Output Enable (Pin 20 : E)
I
Synchronous Output Enable (Pin 20 : Es)
1 :PGMED
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
FFFF
Data
Control Byte
10000
Architecture Byte (1 OOOOH)
nu
D7
C7 Q; Cs C4 C3 C2 Cl
til
:::E
o
a:
Q.
Co
Switching Waveform for the 7C286
IOF
IcE-
IOF
-toE-
~
Oo-~
~
./
VALID
HIGHZ
"
VALID
->k.....------IACC
C2B6-8
Switching Waveform for the 7C287
ES
CLOCK
VALID
Ico¥
IHZC~:1----------«:
_ _- - - - - ' r I H Z E
-
HIGHZ
VALID
t_lDOE_
C2B6-9
3-165
CY7C286
CY7C287
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
7C286 and 7C287 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM is
exposed to sunlight or fluorescent lighting for extended periods
of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) or 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The 7C286 or 7C287 needs to be within
1 inch of the lamp during erasure. Permanent damage may result
if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. CY7C286 Mode Selection
Pin Function[8]
Read or Output Disable
Mode
Other
Read
Al.
Au
CE
OE
Pmi
LATCH
V'FY
Vpp
07- 0 ,
AlO
Au
VIL
VIL
<>7 -
0, -00
00
Output Disable
AlO
Au
X
Output Disable & Power Down
AlO
Au
VIH
VIH
X
HighZ
HighZ
Program
VII~
VII~
VIHP
Vpp
07- 0 0
Program Verify
VIHP
VII~
VILP
Vpp
<>7 -
Program Inhibit
VIHP
VILP
VIHP
Vpp
HighZ
Blank Check
VIHP
VILP
VILP
Vpp
Zeros
0, -00
00
Table 2. CY7C287 Mode Selection
Pin Function[8]
CP
Al4
E.Es
Au
PGM
LATCH
VFY
Vpp
0, -Do
VnJVIH
A14
VIL
A15
<>7-00
Output Disable - Asychronous
X
A14
VIH
A15
HighZ
Output Disable - Synchronous
VnJVIH
A14
VIH
AlS
HighZ
07- 0 0
Read or Output Disable
Mode
Other
Synchronous Read
Program
VILP
VILP
VIHP
Vpp
Program Verify
VIHP
VILP
VILP
Vpp
<>7-00
Program Inhibit
VIHP
VILP
VIHP
Vpp
HighZ
Blank Check
VIHP
VILP
VILP
Vpp
Zeros
Note:
8. X = "don't care" but not to exceed Vee ±S%.
3-166
CY7C286
CY7C287
:i .~
~- CYPRESS
~, SEMICONDUCTOR
DIP
LCC
1"-(\1
Vee
A'3
Vpp
As
As
Ao
As
As
PGM
VFY
NC
Dr
Do
AsiA"
AelA,o
LATCH
A,
Ao
5
6
7
8
9
10
11
12
06
D.
D.
0,
LO O
O'O;f'r>")
««
A,.
7C286
0
AelA"
AelA,o
LATCH
NC
Vpp
PGM
VFY
07
06
C286-11
C286-10
DIP
LCC
~~::~~i
Vee
A,o
A"
A121A14
A13/A15
As
Ao
As
LATCH
NC
5
6
7
8
7C2B7
Vpp
As
9
PGM
VFY
Ao
10
11
12
A,
GND
Do
Dr
0
A,21A,.
A,slA15
LATCH
Vpp
NC
PGM
VFY
07
GND
De
D.
......ClJQ t"lOlltIt)CO
0 0 ~ococ
D.
0,
C2B6-12
Figure 1. Programming Pinouts
3-167
II)
:::!iE
o
IX
a.
..... 1;\100 C')'I3'1O
00 l5Z000
•
C2B6-13
CY7C286
CY7C287
ifl;-~~
~
SEMIcaIDUCTOR
Ordering Information[9]
Speed
(ns)
50
60
70
80
Ordering Code
Package
'JYpe
Operating
Range
Speed
(ns)
CY7C286-50PC
CY7C286-50WC
CY7C286-60PC
CY7C286-60WC
CY7C286-60DMB
CY7C286-60LMB
CY7C286-6OQMB
CY7C286-60WMB
CY7C286-70PC
CY7C286-70WC
CY7C286-70DMB
CY7C286-70LMB
CY7C286-7OQMB
CY7C286-70WMB
CY7C286-80WMB
CY7C286-80QMB
PIS
W16
PIS
W16
D16
L55
Q55
W16
PIS
W16
D16
L55
Q55
W16
W16
Q55
Commercial
45
Commercial
55
Military
65
Commercial
Military
Ordering Code
Package
'JYpe
Operating
Range
CY7C287-45PC
CY7C287-45WC
CY7C287-55PC
CY7C287-55WC
CY7C287-55DMB
CY7C287-55LMB
CY7C287-55QMB
CY7C287-55WMB
CY7C287 -65PC
CY7C287-65WC
CY7C287-65DMB
CY7C287-65LMB
CY7C287-65QMB
CY7C287-65WMB
P21
W22
P21
W22
D22
L55
Q55
W22
P21
W22
D22
L55
Q55
W22
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
Device
Parameters
VOH
VOL
Vrn
VIL
IIX
Ioz
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
7C286
tACC
Icc
IsB[lO]
teE
7C287
tOE
tSA
tHA
teo
tOOE
tpwc
Notes:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
10. CY7C286 only.
Document#: 38-00103-E
3-168
Subgroups
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
Commercial
Military
Commercial
Militaty
This is an abbreviated datasbeet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUcrOR
CY7C291
CY7C292
Reprogrammable 2048 X 8
PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• Highspeed
-35 ns (commercial)
- 35 ns (military)
• Lowpower
-330 mW (commercial)
-413 mW (military)
• EPROM technology 100%
programmable
• Slim 300-mil or standard 6OO-mU
packaging available
• SV ±10% Vee. commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding '> 2000v
static discharge
Functional Description
The CY7C291 and CY7C292 are highperfonnance 2048-word by 8-bit CMOS
PROMs. They are functionally identical,
but are packaged in JOO-miJ and 600-mil
wide plastic and hennetic DIP packages
respectively. The JOO-mil ceramic DIP
package is equipped with an erasure window; when exposed to UV light the
PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY7C291 and CY7C292 are plug-in
replacements for bipolar devices and offer
the advantages of 10wer power, superior
performance, and programming yield The
EPROM cell n:quires only 12.5V for the
super voltage, and low current requirements allow for gang programming. The
EPROM cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each
PROM is also tested for AC perfonnanee
to guarantee that after customer programming, the product will meet DC and
AC specification limits.
Reading is accomplished by placing an active LOW signal on "CSt. and active
HIGH signals on CSz and CSJ. The contents of the memory location addressed
by the address lines (Ao - AlO) will become available on the output lines (00 -
Ch).
Pin Configurations
Logic Block Diagram
DIP
ROW
128.128
DECODER
PRCXlRAMAIILE
1 OF 128
ARRAY
A7
Vex:
Os
At
At
At
At
Os
Ae
At
A,
cs.
cs"
0.
Ao
00
o.
A,.
Ao
ClI,
07
0,
Os
o.
O.
11
o.
OND
Os
COLUMN
DECODER
IOFIB
1----------'
1-_ _ _ _ _ _ _--'
:tn~~~~
Os
Ao 5
Ae B
At 7
0,
A,
Ao
NO
8
9
10
4 3 2,1,282726
25 ClI,
24
23 cs"
0
cs.
22
21
20
os.
NO
0.
Os 111213141516171~9 Os
Os
ClI, --'"'
0291-2
Lee
d-8'i !l~i!8
~
Os.
~--------------~
Os,,--,_.1
0291-3
W'mdow available OJ] 3O()..mU c:erDIP 0JI1y.
C291-1
Selection Guide
Maximum Access Time (ns)
Maximum ~rating
STD
Current(mA
L
Commercial
Military
Commercial
Note:
1. 7C291 only.
3-169
7C291-35
7C292-35
35
90
1201<1
7C291-50
7C292-50
50
90
120
60
60
II)
::::E
o
a:::
a..
CY7C291A
CY7C292A1CY7C293A
CYPRESS
SEMICONDUcrOR Reprogrammable 2Kx 8 PROM
• Direc:t replacement for bipolar
PROMs
• Capable of withstanding >2001V statIc dlscbarge
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• Highspeed
-20ns (commercial)
- 25 ns (military)
Functional Description
• Lowpower
- 660 mW (commercial and military)
• Low standby power
-220 mW (commercial and military)
• EPROM technology 100% programmable
• Slim 300-mil or standard tiOO-mlI
packaging available
• SV ±10% Vee. commercial and
military
• TTL-compatible I/O
The CY7C291A, CY7C292A, and
CY7C293A are high-performance 2Kword by S-bit CMOS PROMs. They are
functionally identical, but are packaged in
JOO-mil (7C291A, 7C293A) and 600-mil
wide plastic and hermetic DIP packages
(7C292A). The CY7C293A has an automatic power down feature which reduces
the power consumption by aver 70%
when deselected. The ceramic package
may be equipped with an erasure window;
when exposed to UV light the PROM is
erased and can then be reprogrammed.
The memol}' cells utilize proven EPROM
floating-gate technology and byte-wide inteigent programming algorithms.
Pin Configurations
Logic Block Diagram
""
DIP
'lbpVlew
0.
A,
Ao
PROGRAMMABLE
As
ARRAY
The CY7C291A, CY7C292A, and
CY7C293A are plug-in replacements for
bipolar devices and offer the advantages
of lower power, reprogrammability, superior performance, and programming
yield The EPROM cell requires only
125V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for
each memol}' location to be tested 100%,
as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after
customer programming the product will
meet DC and AC specification limits.
A read is accomplished by placing an active WW signal on 0:-10 and active
HIGH signals on C~ and CSJ. The contents of the memory location addressed by
the address line (Ao - AlO) will become
available on the output lines (00 - 07).
MUlll·
PLElCER
De
As
Ao
As
De
At
At
A4
At
o.
LCCIPLCC (Opaque Only)
'lbpView
Vee
At
At
A,.
,..
""
00
ClI,
AI
cs,.
cs.
A,
A7
Do
At
lie
o.
o.
o.
o.
0,
0.
A,.
07
Oa
GND
0,
~n'i.~~~
4 3 2, \ 282726
A4 5
~
AI
""
o.
NC
-
2S A,.
24
7C291A
6
23
7
22
8
21
8
7C283A
20
10
111213141516171818
0
ClI,
cs,.
cs.
NC
07
O.
o8'§ 'i.c5'd'c5'
C281A-3
C281A-2
WUldow available on
7C291A and 7C293A
only.
00
ClI,
cs.
cs.
C281A-l
Selection Guide
Maximum Access Time (os)
Maximum~erating Standard
Current (
)
L
Standbl Current (rnA
7C293 Only
Commercial
Military
Commercial
Commercial
Military
7C29lA-20
7C292A-20
7C293A-20
20
120
40
3-170
7C29lA-25
7C292A-25
7C293A-25
2S
7C29lA-30
7C292A-30
7C293A-30
30
90
120
120
30
40
40
7C291AL-35 7C291AL-50
7C292AL-35 7C292AL-50
7C293AL-35 7C293AL-50
7C29lA-50
7C29lA-35
7C292A-35
7C292A-50
7C293A-35
7C293A-50
50
35
90
90
90
90
60
60
30
30
40
40
CY7C291A
CY7C292A/CY7C293A
·-~PRFSS
-=-,
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13.0V
UVExposure ............................ 7258Wsec/cm2
Static Discharge Voltage. . . .. . . . .. .. . .. . . . . . . . . . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Industriam
Militaryf2]
O°Cto + 70°C
Vee
5V±1O%
- 40°C to + 85°C
5V±10%
- 55°C to + 125°C
5V±1O%
Electrical Characteristics Over the Operating Rangel3, 4]
7C291A-20
7C292A-20
7C293A-20
7C29IA-25
7C292A-25
7C293A-25
7C29IA-30
7C292A-30
7C293A-30
Min.
Min. Max.
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0rnA
2.4
VOL
Output LOW Voltage
Vee = Min.,
IOL = - 16.0 rnA
Vrn
Input HIGH Voltage
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Voltage
Guaranteed Input Logical
LOW Voltage for All Inputs
IIX
Input Load Current
GNDSVINSVee
Veo
Input Diode Clamp Voltage
Ioz
Output Leakage Current
los
Output Short Circuit Currend5] Vee = Max., VOUT = GND
lee
Vee Operating Supply Current Vee = Max.,
IoUT = ornA
ISB
Standby Supply Current
(7C293AOnly)
Parameters
Description
Vpp
Programming Supply Voltage
Ipp
ProgrammingSupplyCurrent
Vrnp
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
Max.
0.4
2.0
2.4
Vee
2.0
+10
Vee
+10
V
V
Vee
V
0.8
V
-10
+10
!lA
!lA
2.0
0.8
-10
Units
0.4
0.4
0.8
-10
Max.
2.4
Note 4
GNDs VOUTS Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
- 20
-90
-20
- 90
-20
-90
Com'l
120
120
Mil
Ycc = Max.,
120
Com'l
CSl~ Vrn
120
40
40
Mil
rnA
40
12
13
12
50
3.0
13
0.4
40
12
50
3.0
13
V
50
rnA
3.0
0.4
rnA
rnA
V
0.4
V
Noles:
1. Contact a Cypress representative for industrial temperature rauge
2.
3.
specifications.
TA is the "instaut on" case temperature.
See the last page of this specification for Group A subgroup testing information.
4.
5.
3-171
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general infromatiou on testing.
For test purposes, not more thau one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
•
tI)
:E
o
a:
a..
CY7C29lA
CY7C292A1CY7C293A
fC;~PRESS
~_.,
SEMIcamUCTOR
Electrical Characteristics
Over the Operating Rangel3, 4] (continued)
7C291AL-35,50
7C292AL-35,50
7C293AL-35,50
Description
Parameters
'lest Conditions
Min.
2.4
VOH
Output HIGH Voltage
Vex = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vex =Min., IOL = - 16.0rnA
Vrn
Input HIGH Voltage
Guaranteed Input Logical
HIGH Voltage for All Inputs
VJL
Input LOW Voltage
Guaranteed Input Logical
LOW Voltage for All Inputs
GND.s VIN.s Vex
7C291A-35,50
7C292A-35,50
7C293A-35,50
Min.
Max.
0.4
2.0
Units
0.4
V
V
2.0
0.8
-10
Max.
2.4
-10
V
0.8
V
+10
tJA
IIX
Input Load Current
Ven
Input Diode Qamp Voltage
Ioz
Output LeakageCurrent
GND.s VOUT.s Veo
Output Disabled
-10
+10
-10
+10
tJA
los
Output Short Circuit Current[5]
Vex = Max., VOUT = GND
-20
- 90
-20
-90
rnA
lex
Vee Operating Supply Current
Vee = Max.,
VIN= 2.0V
90
rnA
Standby Supply Current
(7C293AOnly)
ISB
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
Vrnp
Input HIGH Programming Voltage
VJLP
Input LOW Programming Voltage
+10
Note 4
Ycc= Max.,
CSl~ Vrn
Commercial
60
Military
90
Commercial
30
rnA
30
Military
40
12
13
12
50
3.0
13
V
50
rnA
3.0
0.4
V
0.4
V
Capacitance [4]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
TA
'lest Conditions
Max.
Units
= 25°C, f = 1 MHz,
10
pF
10
pF
Vex=5.0V
3-172
CY7C291A
CY7C292A/CY7C293A
~
·~PRESS
~F
SEMICONDUCTOR
AC Test Loads and Waveforms!4]
OUTP~~31R125og
5V31R125og
OUTPUT
30pF
R2
16m
I _
INCLUDING
JIG AND SCOPE
5 PF
I
-
_
-
~
10%
10%
C291A-5
C291A-4
In
::iE
oa:
(b) High Z Load
(a)
Equivalent to:
GND
R2
16m
INCLUDING _
JIG AND SCOPE
• ~5ns •
'0.31~=~
ALL INPUT PULSES
THEvENIN EQUIVALENT
D.
1000
OUTPUT 00-----'·"''''"''"---00 2.0V
C291A-6
Ao - A10
ADDRESS
~
i4" tpo ..
Vec
SUPPLY
CURRENT
~~ 50%
K50%
)~
)K
"'{
-IAA
I--
IHZCS
-I
XX
I-----
_I
lACS
--'I<:
///'/
'-.,,""
.::¥
C291A-7
Switching Characteristics Over the Operating Range!3, 4]
7C291AL-35 7C291AL-50
7C292AL-35 7C292AL-50
7C293AL-35 7C293AL-50
7C29IA-20 7C29IA-25 7C29IA-30 7C29IA-35 7C291A-50
7C292A-20 7C292A-25 7C292A-30 7C292A-35 7C292A-50
7C293A-20 7C293A-25 7C293A-30 7C293A-35 7C293A-50
Max.
Units
Address to Output Valid
20
25
30
35
50
ns
tHZCSl
Chip Select Inactive to High Z
15
20
25
25
ns
IACSI
Chip Select Active to Output Valid
15
20
20
20
25
25
ns
tHZCS2
Chip Select Inactive to High Z
(7C293A CSI Only)!6]
22
27
32
35
45
ns
tACS2
Chip Select Active to Output Valid
(7C293ACSIOnly)!6]
22
27
32
35
45
ns
tpu
Chip Select Active to Power-Up
(7C293ACSIOnly)
tpD
Chip Select Inactive to Power-Down
(7C293A CSl Only)
Description
Min. Max. Min. Max. Min. Max.
0
0
22
0
27
Notes:
6. tHZCS2 and IACS2 refer to 7C293A CSl only.
3-173
Min.
Max.
Min.
tAA
Parameters
0
32
0
35
ns
45
ns
CY7C291A
CY7C292A1CY7C293A
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
these PROMs. For this reason, an opaque label should be placed
over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose ofultrayiolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity x
exposure time) or 25 Wsec/cm2. For an ultraviolet lamp with a 12
mW/cm2 pawer rating. the exposure time would be approximately
30 to 35 minutes.
These PROMs need to be within 1 inch of the lamp during erasure. Pennanent damage may result if the PROM is exposed to
high-intensity UV light for an extended period of time. 7258
Wseqcm2 is the recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming infonnation, including a listing of software packages, please
see the PROM Programming Infonnation located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin FunctionF)
Mode
Read or Output Disable
AIO
Other
AIO
-At
-At
CS3
CSz
CSI
0,-0.
PmI
VFY
Vpp
)h-D.
Read
AlO -Au
VIH
VIH
VIL
07- 0 0
Output Disablel8)
AIO - Au
X
X
VlH
HighZ
Output Disable
AlO - Au
X
VIL
X
HighZ
VIL
X
X
HighZ
D7- DO
0,-00
Output Disable
AlO - Au
Program
AlO-Au
VILP
VIHP
Vpp
Program Verify
AlO-Au
VIHP
VILP
Vpp
Program Inhibit
AlO -Au
VIHP
VIHP
Vpp
HighZ
Intelligent Program
AlO-Au
VILP
VIHP
Vpp
D7- DO
Blank Check Zeros
AlO -Au
VIHP
VILP
Vpp
Zeros
Notes:
7. X = "don't care" but not to exceed Vee +5%.
8. The power-clown mode for the CY7C293A is activated by deselecting
~l'
LCClPLCC (Opaque Only)
Top View
DIP
Top V_
A7
~
~n~$u
Vc;c
~
4 3 2l1.282726
Ao
Ao 5
At
vpp
Ao
Ao
VFV
1Iim
""
Ao
....
Ao
Do
.....
Ao
Do
0.,
De
0,
o.
Do
O.
O.
GNO
""
A,
NO
6
7
8
9
10
7C291A
0
7C29IIA
25
24
23
22
21
20
11'2'3'4'5'8'7'8'9
cd"!i!~St!f,Jf
o
1:291A-8
Figure 1. Programming Pinouts
3-174
A,.
Vpp
VFV
1Iim
NC
0.,
De
1:291A-9
CY7C291A
CY7C292A/CY7C293A
~
~~PRESS
~, SEMlCONDUCTOR
1YPical DC and AC Characteristics
NO~ZEDACCESSTIME
NO~ZEDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
vs. SUPPLY VOLTAGE
1.2
1.2
1.6
w
:;
Jll.4
/
C
w
~
1.2
az
1.0
:li
IX:
O.B
1/
0.6
4.0
/
V
Jll.ll----+-------1
c
en
1.0
en
w
~C
w
~
a
5.0
a..
"" 0.6
IX:
z
0.8.'=------:!-::------.,.:!
-55
25
125
AMBIENTTEMPERATURE (OC)
6.0
SUPPLY VOLTAGE M
U)
:::E
o
a::
TA = 25°C
a
5.5
~
0.8
~
z
TA=25°C
f = fMAl(
,
r........ r--......
~
IX:
I
4.5
i=
I
0.4
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE M
C291A-10
w
:;
~ 1.41-----!-------I
[l
1
60
30.0
!zw
50
25.0
IX:
~ 40
o
o
!
IX:
~
c
z
~
~ 30
" I'...
~
gs
0.6'--_ _ _-'-_ _ _ _ _-1
- 55
25
125
5l
5
~
a
20
10
00
1.0
:::
"
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
.§. 150
!z
~ 125
a
IX:
~
100
z
75
5
50
5
25
iii
I!:
o
V
./
,/
J
V
0.0
I--
Vcc=5.0V
TA = 25°C
I
/
1.0
--
2.0
3.0
OUTPUT VOLTAGE M
.-
/
g 20.0
-
~
4.0
C291A-11
3-175
15.0
~ 10.0
"'" "'"
3.0
OUTPUT VOLTAGE M
AMBIENT TEMPERATURE (OC)
«'
TYPICAL ACCESS TIME CHANGE
vs.OUTPUTWADING
OUTPUT SOURCE CURRENT
vs.VOLTAGE
NO~EDACCESSTIME
vs. TEMPERATURE
1.6r----,-------,
4.0
5.0
V
1/
/
V
/
Vcc=4.5V _
TA = 25°C
I
200
400
600
I
BOO 1000
CAPACITANCE (pF)
CY7C291A
CY7C292A/CY7C293A
~
_'~~DUCTOR
Ordering Information[9]
Speed Icc
(ns)
(mA)
20
120
25
30
35
120
120
60
90
120
50
60
90
90
Ordering Code
CY7C291A-2OJC
CY7C291A-20PC
CY7C291A-20SC
CY7C291A-20WC
CY7C291A - 25JC
CY7C291A-25PC
CY7C291A-25SC
CY7C291A-25WC
CY7C291A-25DMB
CY7C291A-25LMB
CY7C291A-250MB
CY7C291A-25TMB
CY7C291A-25WMB
CY7C291A-30DMB
CY7C291A-30LMB
CY7C291A-300MB
CY7C291A-30TMB
CY7C291A-30WMB
CY7C291AL-35JC
CY7C291AL-35PC
CY7C291AL-35WC
CY7C291A - 35DC
CY7C291A - 35LC
CY7C291A-35SC
CY7C291A - 35PC
CY7C291A-35WC
CY7C291A-35DMB
CY7C291A-35LMB
CY7C291A -350MB
CY7C291A-35TMB
CY7C291A-35WMB
CY7C291AL-5OJC
CY7C291AL-50PC
CY7C291AL-50WC
CY7C291A-50DC
CY7C291A - 50LC
CY7C291A-50SC
CY7C291A-50PC
CY7C291A-50WC
CY7C291A-50DMB
CY7C291A-50LMB
CY7C291A-500MB
CY7C291A-50TMB
CY7C291A-50WMB
Package
'JYpe
J64
P13
S13
W14
J64
P13
S13
W14
D14
L64
064
T73
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
S13
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
S13
P13
W14
D14
L64
064
T73
W14
Operating
Range
Commercial
Speed Icc
(ns) (mA)
20
25
120
120
Commercial
Ordering Code
Package
'JYpe
Operating
Range
Commercial
CY7C292A-20DC
D12
CY7C292A -20PC
P11
CY7C292A-25DC
D12
CY7C292A-25PC
P11
Commercial
CY7C292A-25DMB
D12
Military
30
120
CY7C292A-30DMB
D12
Military
35
60
CY7C292AL-35PC
P11
Commercial
90
CY7C292A-35DC
D12
Commercial
CY7C292A-35PC
P11
120
CY7C292A-35DMB
D12
Military
60
CY7C292AL-50PC
P11
Commercial
90
CY7C292A-50DC
D12
Commercial
CY7C292A-50PC
P11
CY7C292A-50DMB
D12
Military
50
Military
120
Military
Notes:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
Commercial
Commercial
Military
Commercial
Commercial
Military
3-176
CY7C291A
CY7C292A/CY7C293A
·--~PRFSS
~.' SEMlCONDUCIDR
Ordering Information (continuedj9]
Operating
Range
CY7C293A-20JC
J64
Commercial
CY7C293A - 20PC
P13
Ordering Code
120
20
CY7C293A-20WC
25
30
35
120
120
60
90
90
50
60
90
90
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Package
'JYpe
Speed Icc
(ns) (rnA)
DC Characteristics
W14
CY7C293A-25JC
J64
CY7C293A - 25PC
P13
CY7C293A - 25WC
W14
CY7C293A-25DMB
D14
CY7C293A-25LMB
L64
CY7C293A -250MB
064
CY7C293A -25WMB
W14
CY7C293A-30DMB
D14
CY7C293A -30LMB
L64
CY7C293A-300MB
064
CY7C293A-30WMB
W14
CY7C293AL-35JC
J64
CY7C293AL-35PC
P13
CY7C293AL-35WC
W14
CY7C293A-35DC
D14
CY7C293A-35LC
L64
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
Commercial
Vrn
VIL
IJX
Military
Ioz
Icc
IsB[lO]
Military
•
Switching Characteristics
Commercial
Parameters
Subgroups
tAA
tACSl[ll]
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
tAcsz1 lO]
SMD Cross Reference
Commercial
SMD
Number
Suffix
Cypress
Number
CY7C293A-35PC
P13
5962-87650
OlKX
CY7C29l-50TMB
CY7C293A-35WC
W14
5962-87650
OlLX
CY7C29l-50WMB
CY7C293A-35DMB
D14
5962-87650
013X
CY7C291-500MB
CY7C293A-35LMB
L64
5962-87650
03KX
CY7C291- 35TMB
CY7C293A-350MB
5962-87650
03LX
CY7C29l-35WMB
CY7C293A-35WMB
064
W14
5962-87650
033X
CY7C291-350MB
CY7C293AL-5OJC
J64
5962-88734
02JX
CY7C292A-45DMB
CY7C293AL- 50PC
P13
5962-88734
02KX
CY7C29lA-45KMB
CY7C293AL-50WC
W14
5962-88734
02LX
CY7C29lA-45DMB
CY7C293A -50DC
D14
5962-88734
023X
CY7C29lA-45LMB
CY7C293A -50LC
L64
5962-88734
03JX
CY7C292A-35DMB
CY7C293A-50PC
P13
5962-88734
03KX
CY7C29IA-35KMB
CY7C293A-50WC
W14
5962-88734
03LX
CY7C29lA-35DMB
CY7C293A-50DMB
D14
5962-88734
033X
CY7C29lA-35LMB
CY7C293A-50LMB
L64
5962-88734
04JX
CY7C292A-25DMB
CY7C293A -500MB
064
5962-88734
04KX
CY7C291A-25KMB
CY7C293A -50WMB
W14
5962-88734
04LX
CY7C29lA-25DMB
5962-88734
043X
CY7C29lA-25LMB
Military
Commercial
Commercial
Military
Notes:
10. 7C293A only.
11. 7C291A and 7C292A only.
Document#: 38-00075-E
3-177
PROM Programming Information
CYPRESS
SEMICONDUCTOR
Introduction
PROMs or Programmable Read Only Memories have existed since
the early 1970's and continue to provide the highest speed non-volatile form of semiconductor memory available. Until the introduction of CMOS PROMs from Cypress, all PROMs were produced
in bipolar technology, because bipolar technology provided the
highest possible performance at an acceptable cost level. All bipolar PROMs use a fuse for the programming element. The fuses are
intact when the product is delivered to the user, and may be programmed or written once with a pattern and used or read infinitely.
The fuses are literally blown using a high current supplied by a Programming System. Since the fuses may only be blown or programmed once, they may not be programmed during test. In addition, since they may not be programmed until the user determines
the pattern, they may not be completely tested prior to shipment
form the supplier. This inability to completely test, results in less
than 100% yield during programming an use by the customer for
two reasons. First, some percentage of the product fails to program. These devices fallout during the programming operation,
and although a nuisance are easily identified. Additional yield is
lost because the device fails to perform even though it programs
correctly. This failure is normally due to the device being too slow.
This is a more subtle failure, and can only be found by 100% post
program AC testing, or even worst by trouble shooting an assembled board or system.
Cypress CMOS PROMs use an EPROM programming mechanism. This technology has been in use in MOS technologies since
the late 1970's. However, as with most MOS technologies the emphasis has been on density, not performance. CMOS at Cypress is
as fast as or faster than Bipolar and coupled with EPROM, becomes a viable alternative to bipolar PROMs form a performance
point of view. In the arena of programming, EPROM has some significant advantages over fuse technology. EPROM cells are programmed by injecting charge on an isolated gate which permanently turns off the transistor. This mechanism can be reversed by
irradiating the device with ultraviolet light. The fact that programming can be erased, totally changes the testing and programming
situation and philosophy. All cells can be programmed during the
manufacturing process and then erased prior to packaging and subsequent shipment. While these cells are programmed, the performance of each cell in the memory can be tested allowing the shipment of devices that program every time, and will perform as
specified when programmed. In addition when these devices are
supplied in a windowed package they can be programmed and
erased indefinitely providing the designer a RE-PROGRAMMABLE PROM for development.
Programmable Technology
EPROM Process Thchnology
EPROM technology employs a floating or isolated gate between
the normal control gate and the source/drain region of a transistor.
This gate may be charged with electrons during the programming
operation and when charged with electrons, the transistor is permanently turned off. When uncharged (the transistor is unprogrammed) the device may be turned on and off normally with the
control gate. The state of the floating gate, charged or uncharged,
is permanent because the gate is isolated in an extremely pure oxide. The charge may be removed if the device is irradiated with ultraviolet energy in the form of light. This ultraviolet light allows the
electrons on the gate to recombine and discharge the the gate. This
process is repeatable and therefore can be used during the process-
iug of the device repeatedly if necessary to assure programming
function and performance.
1\vo Transistor Cells
In order to provide an EPROM cell that is as fast as the fuse technology employed in bipolar processes, Cypress uses a two transistor EPROM cell. One transistor is optimized for reliable programming, and one transistor is optimized for high speed. The floating
gates are connected such that charge injected on the floatiug gate
of the programming transistor is conducted to read transistor, biasing it off.
Differential Memory Cells
In the 4K (CY7C225); 8K (CY7C235, CY7C281, CY7C282); and
16K (CY7C245, CY7C291, CY7C292) CMOS PROMs, Cypress
employs a differential memory cell and sense amplifier technique.
Higher density devices such as the 7C261, 7C263, 7C264, or 7C269
64K PROMs employ a single ended Cell and sense amplifier technique similar to the approach used in more conventional
EPROMs.
In a conventional high density EPROM a single EPROM transistor is used to switch the input to one side of a differential sense amplifier. The other side of the sense amplifieris biased at an intermediate level with a dummy cell. An unprogrammed EPROM
transistor will conduct and drive the sense amplifier to a logic "0."
A programmed EPROM transistor will not conduct, and consequently drives the sense amplifier to a logic "1." A conventional
EPROM cell therefore is delivered with a specific state "0" or "1"
in it depending on the number of inversions after the sense amplifier and can always be programmed to the opposite state. Access
time in this conventional approach is heavily dependent on the
time the selected EPROM transistor takes to move the input of the
sense amplifier from a quiescent condition to the threshold that the
dummy cell is biasing the second input to the sense amplifier. This
bias is several volts, and requires a significant delay before the
sense amplifier begins to react.
Cypress PROMs employ a true differential cell approach, with
EPROM cells attached to both inputs of the sense amplifier. As indicated above, the read transistor which is optimized for speed is
actually the transistor attached to the sense amplifier. In the erased
state, both EPROM transistors conduct when selected eccentrically biasing the input of the sense amplifier at the same level. If the
inputs were at identical levels, the output of the sense amplifier
would be in a mestastable condition or, neither a "I" nor "0." In
actual practice the natural bias and high gain of the sense amplifier
combine to cause the output to favor one or the other stable conditions. The difference between the two conditions is however only a
few millivolts and the memory cell should be considered to contain
neither a "1" nor a "0." As a result of this design approach, the
memory cell must be programmed to either a "I" or a "0" depending on the desired condition and the conventional BLANK
CHECK mechanism is invalid. The benefit of the approach however is that only a small differential signal from the cell begins the
sense amplifier switching and the access time of the memory is extremely fast.
Single Ended Memory Cells
Although a more conventional approach, single ended memory
cells and sensing techniques offer a superior trade-off between die
size and performance than the differential cell for devices of 64K
densities and above, the Single ended technique employed by Cy-
3-178
~~
_
~~PRESS
F
PROM Programming Information
SEMlCONDUCTOR
Programmable Technology (continued)
press uses a dummy cell for the reference voltage thus providing a
reference that tracks the programmed cell in process related parameters, power supply and temperature induced variations. The
memory cell used is a second generation two transistor cell derived
from earlier work at the 16K density level. It has an optimized
READ transistor that is matched to the sense amplifier, and a second transistor optimized for programming. The floating gates of
the two transistors that make up a memory cell are connected electrically so that the charge programmed onto one device controls
the threshold of the second transistor.
Unlike the differential memory approach, the erased single ended
device contains all "O"s and on the ones are programmed. Therefore a "I" on the data pins during programming causes a "I" to be
programmed into the addressed location.
Programming Algorithm
data on the output pins, and writing it into the addressed location
with the WRITE signal. Verification of data is accomplished by
reading the information on the output pins while the READ signal
is active.
The timing for actual programming is supplied in the unique programming specifications for each device.
Special Featnres
Depending on the specific CMOS PROM in question, additional
features that require programming may be available to the designer. Two of these features are a Programmable INITIAL BYTE and
Programmable SYNCHRONOUS/ASYNCHRONOUS ENABLE available in some of the registered devices. Like programming the array, these features make use of EPROM cells and are
programmed in a similar manner, using supervoltages. The specific
timing and programming requirements are specified in the data
sheet of the device employing the feature.
Programming Support
Byte Addressing and Programming
All Cypress CMOS PROMs are addressed and programmed on a
byte basis unlike the bipolar products that they replace. The address lines used to access the memory in a read mode are the same
for programming, and the address map is identical. The information to be programmed into each byte is presented on the data out
pins during the programming operation and the data is read from
these same pins for verification that the byte has been programmed.
Blank Check for DitTerential Cells
Since a differential cell contains neither a "I" not a "0" before it is
programmed, the conventional BlANK CHECK is not valid. For
this reason, all Cypress CMOS PROMs contain a special BlANK
CHECK mode of operation. Blank check is performed by separately examining the "0" and "1" sides of the differential memory
cell to determine whether either side has been independently programmed. this is accomplished in two passes one comparing the
"0" side of the differential cell against a reference voltage applied
to the opposite side of the sense amplifier and then repeating this
operation for the "1"s side of the cell. The modes are called
BlANK CHECK ONES and BlANK CHECK ZEROS. These
modes are entered by application of a supervoltage to the device.
Blank Check for Single Ended Cells
Single ended cells BlANK CHECK in a conventional manner. An
erased device contains all "O"s and a programmed cell will contain
a "1." Cypress PROMs that use the single ended approach provide
a specific mode to perform the BlANK CHECK which also provides the verify function. This makes the need to switch high voltages unnecessary during the program verify operation. See specific
data sheets for details.
Programming the Data Array
Programming support for Cypress CMOS PROMs is available
from a number of programmer manufacturers, some of which are
listed below.
Data I/O Corporation
10525 Willows Rd. N.B.
P.O. Box 97046
Redmond, WA 98073-9746
(206) 881-6444
Data I/O 29B Unipak II
Cypress
Part Nnmber
Generic Part
Number
Family Code
and Pinout
Revision
CY7C225
27S25
FO
B6
V12
CY7C235
27S35
FO
:85
V09
CY7C245
27S45A
PO
BO
V09
27S49
EF
31
Vll
CY7C281/2
27S281/282
EE
B4
V09
CY7C291/2
27S291/292
F2
AF
V09
CY7C261/3/4
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
(408) 988-1118
Programming is accomplished by applying a supervoltage to one
pin of the device causing it to enter the programming mode of operation. This also provides the programming voltage for the cells to
be programmed. In this mode of operation, the address lines of the
device are used to address each location to be programmed, and
the data is presented on the pins normally used for reading the contents of the device. Each device has a READ and WRITE pin in
the programming mode. These are active low signals and cause the
data on the output pins to be written into the addressed memory
location in the case of the WRITE signal or read out of the device
in the case of the READ signal. When both the READ and
WRITE signals are high, the outputs are disabled and in a high impedance state. Programming therefore is accomplished by placing
3-179
Data I/O 29B Unipak II
Cypress
Part Number
Generic Part
Number
Family Code
and Pinout
Revision
CY7C225
27S25
Rev 21
CY7C235
27S35
Rev 21
CY7C245
27S45A
Menu
Driven
Rev 24
CY7C281/2
27S281/282
Rev 21
CY7C291/2
27S291/292
Rev 21
•
I/)
:::E
oa:
a.
PROM Programming Information
Cypress Semiconductor, Inc.
3901 North First St.
San Jose, CA 95134
(408) 943-2600
Cypress CY3000 QuickPro Rev. PROM 2.10
Cypress
Generic
Part Number
Part Number
Family Code
and Pinout
CY7C225
CY7C235
CY7C245
CY7C261/3/4
Menu
Menu
CY7C268
Driven
Driven
CY7C269
CY7C281/2
CY7C291/2
3-180
INFO
SRAMs
PROMs
PlDs
FIFOs
lOGIC
COMM
RISC
MODULES
ECl
'''I
BUS
"I
MILITARY
TOOLS
QUALITY
PACKAGES
'I'
"~I
'~j
z
.~
Section Contents
~=CYPRF.SS
~_F
SEMICONDUCTOR
PLDs (Programmable Logic Devices)
Page Number
Introduction to Cypress PLDs ...............................................................................
Device Number
PLDC18G8
PALC20 Series
PAL20 Series
PALC20GlO
PALC20GlOB
PALC20GlOC
PLDC20RAlO
PALC22VlO
PALC22VlOB
PAL22V1OC
PAL22VPlOC
PAL22V10D
CY7C325
CY7C330
CY7C331
CY7C332
CY7B333
CY7B335
CY7B336
CY7B337
CY7B338
CY7B339
CY7C340 EPLD Family
CY7C341
CY7C342
CY7C345
CY7C343
CY7C344
CY7C361
PLD610
PLD Programming Information
4-1
Description
CMOS Generic 20-Pin Programmable Logic Device ................................. . 4-6
Reprogrammable CMOS PAL C 16L8, 16R8, 16R6, 16R4 ........................... . 4-13
5-ns, Industry-Standard, 20-Pin PLDs ............................................ . 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. . 4-29
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. . 4-29
4-37
Generic 24-Pin PAL Device .................................................... .
Reprogrammable Asynchronous CMOS Logic Device .............................. . 4-47
Reprogrammable CMOS PAL Device ........................................... . 4-57
Reprogrammable CMOS PAL Device ........................................... . 4-67
4-77
Universal PAL Device ........................................................ .
4-77
Universal PAL Device ........................................................ .
Flash Erasable, Reprogrammable CMOS PAL Device .............................. . 4-88
4-95
Timing Control Unit ......................................................... .
CMOS Programmable Synchronous State Machine ................................ . 4-102
Asynchronous Registered EPLD .............................................. . 4-113
Registered Combinatorial EPLD .............................................. . 4-126
General-Purpose Synchronous BiCMOS PLD .................................... . 4-136
Universal Synchronous EPLD ................................................. . 4-144
6-ns BiCMOS PAL with Input Registers ......................................... . 4-157
7-ns BiCMOS PAL with Input Registers ......................................... . 4-163
6-ns BiCMOS PAL with Output Latches ....................................... .. 4-169
7-ns BiCMOS PAL with Output Latches ........................................ . 4-175
Multiple Array Matrix High-Density EPLDs ..................................... . 4-181
192-Macrocell MAX EPLD .................................................. . 4-190
128-Macrocell MAX EPLD .................................................. . 4-201
128-Macrocell MAX EPLD .................................................. . 4-201
64-Macrocell MAX EPLD ................................................... . 4-214
32-Macrocell MAX EPLD ................................................... . 4-225
Ultra High Speed State Machine EPLD ......................................... . 4-235
Multipurpose BiCMOS PLD .................................................. . 4-249
4-257
........................................................................... .
PAL is a registered trademark of Advanced Micro Devices, Inc.
In
C
..J
a.
Introduction to Cypress PLDs
CYPRESS
SEMICONDUCTOR
Cypress PLD Family Features
Cypress Semiconductor's PLD family offers the user a wide range
of programmable logic solutions that incorporate leading-edge circuit design techniques as well as diverse process technology capabilities. This allows Cypress PLD users to select PLDs that best suit
the needs of their particular high-performance system, regardless
of whether speed, power consumption, density, or device flexibility
are the critical requirements imposed by the system.
Cypress offers enhanced-performance industry-standard 20- and
24-pin device architectures, proprietary 28-pin application-tailored architectures and highly flexible 28- to 84-pin universal device architectures. The range of technologies offered includes leading-edge 0.8-micron CMOS EPROM for high speed, low power,
and high density, 0.8-micron bipolar for the highest-speed ECL devices, 0.8-micron BiCMOS for high-speed, power-sensitive applications, and 0.65-micron FLASH technology for high speed, low
power and electrical alterability.
The reprogrammable memory cells used by Cypress serve the same
purpose as the fuse used in most bipolar PLD devices. Before programming, the AND gates or product terms are connected via the
reprogrammable memory cell to both the true and complement inputs. When the reprogrammable memory cell is programmed, the
inputs from a gate or product term are disconnected. Programming
alters the transistor threshold of each cell so that no conduction
can occur, which is equivalent to disconnecting the input from the
gate or product term. This is similar to "blowing" the fuses of BiCMOS or bipolar fusible devices, which disconnects the input gate
from the product term. Selective programming of each of these reprogrammable memory cells enables the specific logic function to
be implemented by the user.
The programmability of Cypress's PLDs allows the users to customize every device in a number of ways to implement their unique
logic requirements. Using PLDs in place of SSI or MSI components results in more effective utilization of board space, reduced
cost and increased reliability. The flexibility afforded by these
PLDs allows the designer to quickly and effectively implement a
number of logic functions ranging from random logic gate replacement to complex combinatorial logic functions.
The PLD family implements the familiar "sum of products" logic
by using a programmable AND array whose output terms feed a
fixed OR array. The sum of these can be expressed in a Boolean
transfer function and is limited only by the number of product
terms available in the AND-OR array. A variety of different sizes
and architectures are available. This allows for more efficient logic
optimization by matching input, output, and product terms to the
desired application.
PLD Notation
To reduce confusion and to have an orderly way of representing the
complex logic networks, logic diagrams are provided for the various part types. In order to be useful, Cypress logic diagrams
employ a common logic convention that is easy to use. Figure 1
shows the adopted convention. In part (a), an "x" represents an
unprogrammed EPROM cell or intact fuse link that is used to perform the logical AND operation upon the input terms. The convention adopted does not imply that the input terms are connected on
the common line that is indicated. A further extension of this convention is shown in part (b), which shows the implementation of a
simple transfer function. The normal logic representation of the
transfer function logic convention is shown in part (c).
PLD Circuit Configurations
Cypress PLDs have several different output configurations that
cover a wide spectrum of applications. The available output configurations offer the user the benefits of both lower package counts
and reduced costs when used. This approach allows designers to select PLDs that best fit their applications. An example of some of
the configurations that are available are listed below.
Programmable I/O
Figure 2 illustrates the programmable I/O offered in the Cypress
PLD family that allows product terms to directly control the outputs of the device. One product term is used to directly control the
three-state output buffer, which then gates the summation of the
remaining terms to the output pin. The output of this summation
can be fed back into the PLD as an input to the array. This programmable I/O feature allows the PLD to drive the output pin
when the three-state output is enabled or, when the three-state
output is disabled, the I/O pin can be used as an input to the array.
INTRO-l
(a)
INTRO-2
(h)
(c)
INTRO-3
Figure 1. Logic Diagram Conventions
4-1
II
II)
C
..J
a.
Introduction to Cypress PLDs (continued)
I~
]11111111Iii[1~1~lllllllll Boo
INTRO-4
Figure 2. Programmable I/O
-
-
INPUTS, FEEDBACK, AND I/O
CLOCK
>
;---
D
QI--
~
L1!~
--
....
INTRO-5
Figure 3, Registered Outputs witb Feedback
Registered Outputs with Feedback
Figure 3 illustrates tbe registered outputs offered on a number of
the Cypress PLDs which allow any of these circuits to function as a
state sequencer. The summation of the product terms is stored in
the D-type output flip-flop on tbe rising edge of the system clock.
The Q output oftbe flip-flop can then be gated to theoutpu~pin by
enabling the tbree-state output buffer. The output of the flip-flop
can also be fed back into the array as an input term. The output
feedback feature allows tbe PLD to remember and then alter its
function based upon tbat state. This circuit can be used to execute
such functions as counting, skip, shift, and branch.
Programmable Macrocell
The programmable macroceIl, illustrated inFigure 4, provides the
capability of defining the architecture of each output individually.
Each of the potential outputs may be specified to be "~egi~~red"
or "combinatorial." Polarity of each output may also be mdlvldualIy selected allowing complete flexibility of output configuration.
Further configurability is provided through "array" configurable
"output enable" for each potential output. This feature allows tbe
outputs to be reconfigured as inputs on an individual basis or a1ternatelyused as a bidirectional I/O controlled by tbe programmable
array (see Figure 5).
Buried Register Feedback
The CY7C330 and CY7C331 PLDs provide registers tbat may be
"buried" or "hidden" by electing feedback of the register outpUL
These buried registers, which are useful in state machines, may be
implemented witbout sacrificing tbe use of tbe associated devi~
pin as an input. In previousPLDs, when tbefeedbackpatb was activated, the input pin-path to the logic array was blocked. The p~o
prietary CY7C330 reprogrammable synchronous state machine
macrocell illustrates the shared input multiplexer, which provides
an alternative input patb for the I/O pin associated with a buri~d
macrocell register (Figure 6). Each pair of macrocells shares an 1U-
put multiplexer, and as long as alternate macrocells are buried, up
to six of the twelve output registers can be buried wi~hout tbe lo~
of any I/O pins as inputs. The CY7C330 also contams four dedicated hidden macrocells witb no external output that are used as
additional state registers for creating high-performance state machines (Figure 7).
Asynchronous Register Control
Cypress also offers PLDs tbat may be used in asynchronous systems in which register clock, set, and reset are controlled by tbe
outputs oftbe product term array. The clock signal is created bytb:e
processing of external inputs and/or internal feedback by tbe logiC
oftbe product term array, which is then routed to tbe register clock.
The register set and reset are similarly controlled by product te~m
outputs and can be triggered at any time indepen~ent of the reglsterclock in response to external and/or feedback inputs proce~d
bytbe logic array. TheproprietaryCY7C!~1 Asynchr~)Uo~ Re~
tered PLD, for which the I/O macrocellls illustrated In Ftgure 8, IS
an example of such a device. The register clock, set, and reset functions of tbe CY7C331 are all controlled by product terms and are
dependent ouly on input signal timing an~ comb~atorial ~elay
tbrough tbe device logic array to enable tberr respective functions.
Input Register Cell
Otber Cypress PLDs provide input register cells to capture short
duration inputs tbat would not otbetwise be present at the inputs
long enough to allow tbe device to respond. Botb tbe proprietary
CY7C330 Reprogrammable Synchronous State Machine and tbe
proprietary CY7C332 Combinatorial PLD provide these input
register cells (Figure 9). The c1ockfortbe input register may be provided from one of two external clock inputpins selectable by a configuration bit, C4, dedicated for tbis purpose for each input register. This choice of input register clock allows signals to be captured
and processed from two independent syst~m sourcc:s, each controlled by its own independent clock. These mpu~ regISt~r cells ~re
provided witbin I/O macrocells, aswell as for dedicated mput pms.
4-2
Introduction to Cypress PLDs
(continued)
CLOCK AR
OE
~
.....
0
...LJ)-
--Dll
~
v
MACRO-
CELL
>
~
SP
INTRO-6
Figure 4. Programmable Macroeell
PIN 14OUTPUT ENBLE (UE)
GLOBAL
SYNCHRONOUS SET
"'>c--.---+--I
I/O
~
PIN
MACROCELL
INPUT REGISTER
INPUT OR FEEDBACK TO LOGIC ARRAY
C1
FEEDBACK
MUX
Q
DI---....I
MACROCELL C2
INPUT CLOCK
MUX
TO SHARED
MACROCELL
INPUTMUX
GLOBAL STATE
REGISTER CLOCK
CLK(PIN1)
Figure 5. CY7C330 ItO Macrocell
4-3
INPUT
CLOCKS CK2 CK1
(PIN 3) (PIN 2)
110
INTRO-7
•
Introduction to Cypress PLDs
FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
INTRO-8
Figure 6. CY7C330 I/O Macrocell Pair Shared Input MUX
GLOBAL SYNCHRONOUS SET
D
HIDDEN
STATE
REGISTER
S
Q
RO
GLOBAL SYNCHRONOUS RESET
FEEDBACK TO LOGIC ARRAY
GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)
Figure 7. CY7C330 Hidden State Register Macrocell
4-4
INmO-9
(continued)
Introduction to Cypress PLDs
PIN 14
(continued)
-----I
OE
MUX
SET PRODUCT TERM
•
S
o
Q
1--4.-----1
OUTPUT
REGISTER
'"
C
..J
a.
CLOCK PRODUCT TERM
R
RESET PRODUCT TERM
t-_ _ _ _ _ _ _,FEEDBACK
--~"-.I
S
MUX
o
Q
INPUT
REGISTER
R
INTRO-IO
TO SHARED
INPUTMUX
Figure 8. CY7C331 Registered Asynchronous Macrocell
INPUT 1 - + - - - - - - - 1 0
PIN
o
INPUT
CLOCK
MUX
C4
Q
INPUT
REGISTER
INPUT TO
..c:~----+....
I
LOGIC
ARRAY
REGISTER INITIALIZED ON POWER·
UP TO Q EQUAL TO LOGIC LOW
INTAO-l1
CK1 CK2
(PIN 2) (PIN 3)
Figure 9. CY7C330 Dedicated Input Cell
Document #: 38-00165-A
4-5
PLDC18G8
CYPRESS
SEMICONDUcrOR
Features
Functional Description
• Generic architecture to replace standard logic functions Including: 10HB,
• Fast
-Commercial: tpu = 12 ns,
teo 10 ns, ts 10 ns
- Military/lDdustrial: tPD 15 us,
tco = 12 ns, ts = 12 hS
=
CMOS Generic 20-Pin
Programmable Logic Device
=
=
• Lowpower
- Icc max. of 110 mA
• Commercial, Industrial, and military
temperature range
• User-programmable output cells
- Selectable for registered or
combinatorial operation
- Output polarity control·
-Output enable source selectable
from pin 11 or product term
12H6, 14H4, 1682, lOU, 121.6, 14IA,
16L2, lOps, 12P6, 14P4, 16P2, 16H8,
161.8, 16P8, 16KB, 16K6, 16K4, 16RP8,
161UP6, 16RP4, 18P8, 16V8
• Eight product terms and one OE
product term per output
• CMOS EPROM technology for
reprogrammability
• Highly reliable
- Uses proven EPROM tecbnology
- Fully AC and DC tested
- Security feature prevents logic
pattern duplication
- >2000V Input protection for
electrostatic discharge
Cypress Pill devices are high-speed electrically programmable logic devices.
These devices utilize the sum-i)f-products
(AND-OR) structure, providing users
with the ability to program custom logic
functions for unique requirements.
In an unprogrammed state, the AND
gates are connected via EPROM cells to
both the true and complement of every
inpuL By selectively programming the
EPROM cells, AND gates may be connected to either the true or complement
or disconnected from both true and complement inputs.
Cypress Pill C18G8 uses an advanced
O.8-micron CMOS technology and a proven EPROM cell as the programmable
Logic Block Diagram, DIP and SOJ Pinout
110
110
VO
110
Vee
Pin Configurations
lBG8·1
PLCC
ThpView
__ fS~g
3 2!..11201~8
vo
17
16
15
14
B
910111213
VO
110
VO
4
5
6
7
3 2
110
110
110
110
vo
110
-,gllg g g
4-6
lBG8-2
PLDC18G8
Selection Guide
Generic
Part Number
ISGS-12
Icc (mA)
Ipo (DS)
Com'l
90
MII/IDd
90
70
110
ISGS-15
ISGS-15L
ISGS-2O
Com'l
12
15
15
teo
ts
MiI/lDd
Com'l
10
MiI/IDd
15
12
12
12
110
Functional Description (continued)
18G8 Functional Description
The PlDClSGS is a generic 2O-pin device that can be programmed to logic functions which include but are not limited to:
10HS, 12H6, 14H4, 16H2, 10LS, 12L6, 14L4, 16L2, lOPS, 12P6,
14P4, 16P2, 16HS, 16LS, 16P8, 16RS, 16R6, 16R4, 16RPS,
16RP6, 16RP4, lSPS, 16VS. Thus, the PlDC1SGS provides significant design, inventory, and programming flexibility over dedicated 20-pin devices. It is executed in a 2O-pin, 3OO-mil molded
DIP and a 300-mil windowed cerDIP. It provides up to IS inputs
and S outputs. When the windowed cerDIP is exposed to UV
light, the lSGS is erased and can then be reprogrammed.
The programmable output cell provides the capability of defining
the architecture of each output individually. Each of the 10 output cells may be configured with registered or combinatorial outputs, active mGH or active LOW outputs, and product term or
Pin 11 generated output enables. Four architecture bits determine the configurations as shown in the Configuration 'Thble. A
Mil/lDd
12
15
15
20
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability and
testability of the circuit, reducing the customer's need to test and
to handle rejects.
A preload function allows the registered outputs to be preset to
any pattern during testing. Preload is important for testing the
functionality of the Cypress PlD device.
Com'l
10
12
12
total of sixteen different configurations are possible. The default
or unprogrammed state is registered/active LOW/Pin 11 DE. The
entire programmable output cell is shown in Figure 1.
Architecture bit Cl rontrols the registered/combinatorial option.
In either combinatorial or registered configuration, the output
can serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register
may be fed back to the array. This allows the creation of state
machines by providing storage and feedback of the current system state. The register is clocked by the signal from Pin 1. The
register is initialized upon power-up to Q output LOW and Q
outputmGH
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit C2. The DE signal may be generated within the
array or from the external <:m (Pin 11). Pin 11 allows direct control of the outputs, hence having faster enable/disable times.
Each output cell can be configured for output polarity. The output can be either active mGH or active LOW. This option is controlled by architecture bit CO.
Along with this increase in functional density, the Cypress
PlDClSGS provides lower-power operation through the use of
CMOS technology and increased testability with a register preload feature.
-----------------------,I
OE PRODUCT TERM
OUTPUT
t---~ SEJ~f
I-t--+-+I
c:, Co
CP
INPUTI
FEEDBACK
MUX
Co
Ca
0,
Co
PIN 11
Figure 1. Programmable Output Cell
4-7
18G&-4
•
I I)
C
..J
D.
.J7~C1OR
PLDC18G8
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883 Method 3015)
Latch-UpCurrent ............................ >200rnA
StorageThmperature ................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . .. - 55 ° C to + 125 ° C
Supply Voltage to GroundPotentiai ........ - 0.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ -0.5Vto+7.0V
DCInputVoltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (WW) ............... 24 rnA
DC Programming Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. 13.0V
Electrical Characteristics
Parameters
Operating Range
Ambient
Thmperature
Range
Commercial
Industrial
Militaryll]
O°Cto +75°C
Vee
5V±5%
- 40°C to +85°C
5V±10%
- 55°C to +125°C
5V±1O%
Over the Operating Range (Unless Otherwise Noted)
Thst Conditions
Description
Min.
VOH
Output HIGH Voltage
Vex; = Min.,
VIN = VIH or VIL
IOH = - 3.2 rnA Commercial
IOH=-2rnA
Military/lndustrial
VOL
Output WW Voltage
Vex; = Min.,
VIN = VIH or VIL
IOL= 24 rnA
Commercial
IOL= 12 rnA
Military/lndustrial
Max.
Units
2.4
V
0.5
V
0.8
V
f.IA
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[2]
VIL
Input WW Level
Guaranteed Input Logical WW Voltage for All Inputs[2]
IIX
Input LeakageCurrent
Vss5 VIN 5 Vex;
-10
+10
Programming Voltage @ Ipp = 50 rnA Max.
12.0
13.0
V
-30
- 90
rnA
70
rnA
90
rnA
110
rnA
+40
f.IA
Vpp
Ise
Output Short Circuit Current Vee = Max., VOUT = 0.5V[3]
lee
Power Supply Current
VIN = 0, Vee = Max., lOUT = 0 rnA
2.0
Commercial-15L
Commercial
-15
-12,
Military/Industrial
Output Leakage Current
Ioz
- 40
Vex; = Max., Vss5 VOUT 5 Vex;
V
Capacitance [4]
Parameters
CIN
CoUT
Notes:
1.
2.
3.
Description
InputCapacitance
OutputCapacitance
TA is the "instant on" case temperature.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one ontput should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
Thst Conditions
Max.
Units
TA = 25°C,f= 1 MHz
10
pF
VIN = 2.0V, Vee = 5.0V
10
pF
4.
4-8
been chosen to avoid test problems caused by tester ground degradation.
Thsted initially and after any design or process changes that may affect
these parameters.
PLDC18G8
AC Test Loads and Waveforms
R1 160fl
R1 1600
"",:;~ ";;~"'
I
50pF
~~8~~~NG
-=
5 v ? ( 3 1MIL/INO)
9fl
OUTPUT
124fl
(236fl
-=
R2
~~8~~~NG
Mll./INO)
SCOPE
124fl
-= ( : 0 )
SCOPE
(a)
(b)
I
Equivalent to:
J
5pF
I
THEVENIN EQUIVALENT (Commercial)
Equivalent to:
70.0.
OUTPUT ~ 2.18V
1SGS-5
THEVENIN EQUIVALENT (Military/Industrial)
OUTPUT ~ 2.13V
18G8--7
Configuration Thble[5]
Configuration
C3
C2
C1
Co
0
0
0
0
Active LOW, Registered Mode, Registered Feedback, Pin 11 OE
Active HIGH, Registered Mode, Registered Feedback, Pin 11 OE
0
0
0
1
0
0
1
0
Active LOW, Combinalorial Mode, Registered Feedback, Pin 11 OE
0
0
1
1
Active HIGH, Combinatorial Mode, Registered Feedback, Pin 11 OE
0
1
0
0
Active LOW, Registered Mode, Registered Feedback, Product Tcrm OE
0
1
0
1
Active HIGH, Registered Mode, Registered Feedback, Product 'Ierm 01,
0
1
1
0
Active LOW, Combinatorial Mode, Registered Feedback, Product Term OE
0
1
1
1
Active HIGH, Combinatorial Mode, Registered Feedback, Product Thrm OE
1
0
0
0
Active LOW, Registered Mode, Pin Feedback, Pin 11 OE
1
0
0
1
Active HIGH, Registered Mode, Pin Feedback, Pin 11 OE
Active LOW, Combinatorial Mode, Pin Feedback, Pin 11 OE
1
0
1
0
1
0
1
1
Active HIGH, Combinalorial Mode, Pin Feedback, Pin 11 OE
1
1
0
0
Active LOW, Registered Mode, Pin Feedback, Product Thrm OE
1
1
0
1
Active HIGH, Registered Mode, Pin Feedback, Product Term OE
1
1
1
0
Active LOW, Combinatorial Mode, Pin Feedback, Product Term OE
1
1
1
1
Active HIGH, Combinatorial Mode, Pin Feedback, Product Thrm OE
Notes:
In the virgin or unprogrammed state, a configuration bit is in the "0"
5.
state.
4-9
en
a.....I
136.0.
18GS·6
II
Q.
.il~NDUQDR
Switching Characteristics
PLDC18G8
Over the Operating Range[l, 6, 7]
Commercial
Description
Parameters
Min.
Military/Industrial
-15,-15L
-12
Max. Min.
-15
Max. Min.
-20
Max. Min.
Max. Units
tpD
Input or Feedback to Non-RegisteredOutput
12
15
15
20
ns
tEA
Input to Output Enable
12
15
15
20
ns
tER
Input to Output Disable
12
15
15
20
ns
tpzx
Pin 11 to Output Enable
10
12
12
15
ns
tpxz
Pin 11 to Output Disable
10
10
10
15
ns
teo
Clock to Output
10
12
12
15
ns
ts
Input or Feedback Set-Up Time
10
12
12
15
ns
tH
tp[8]
Hold Time
0
0
0
0
ns
Clock Period
22
24
27
35
ns
tWH
Clock High Time
7
8
9
10
ns
tWL
Clock Low Time
8
9
10
11
ns
fMAX[9]
Maximum Frequency
50.0
41.6
41.6
33.3
MHz
Notes:
6. Part (a) of AC Thst Loads and Waveforms is used for all parameters
except tER, tpzx, and tpxz. Part (b) of AC Thst Loads and Waveforms
is used for tER, Ipzx, and Ipxz.
7. The parameters tER and Ipxz are measured as the delay from the input disahle logic threshold transition to VOH - O.5V for an enabled
mGH output or VOL + O.5V for an enabled WW input.
8. tB or minimum guaranteed clock period, is the clock period guaranteed for state machine operation and is calculated from tp = ts + teo.
9.
The minimum guaranteed period for registered data path operation
(no feedback) can be calculated as the greater of (twH + twL) or (Is
+ IH).
fMAX, or minimum guaranteed operating frequency, is the operating
frequency guaranteed for state machine operation and is calculated
fromfMAX = 1/(ts + teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower
of l/(tWH + twL) or 1/(ts + tH).
Switching Waveform
INPUTS I/O, ,......,.,...,...,.......
REGISTERED
FEEDBACK IU.~~~
CP
tpzx
REGISTERED
OUTPUTS _ _ _ _ _--I.~IL.V
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _...........................
18G8-8
4-10
PLDC18G8
Functional Logic Diagram
INPUT LINES
-ri)
0
OE
•
B
12
16
20
2.
·
-t;:;:7
0
I> CELL r-
·
OUTPUT
CELL
t;
4
··
~7
OUTPUT
CELL
d-
::J
o
OE
o
·
0
II:
c..
5
·
0
OUTPUT
CELL
>
7
-t;
OE
··
0
7
OUTPUT
CELL
>
7
-t;
OE
·
0
OUTPUT
CELL
>
7
8
-
9
~
if
15
14
13
12
11
18G8-9
4-11
16
~
OUTPUT
CELL
OE
6
~
~
7
-t;
17
~
0
I!!
18
r-
~
-t:;7
OE
II:
en
C
~ r-
0
en
II
OUTPUTf-<
OE
::;;
19
~ I-
OE
3
32
I> CELL r-
~
2
28
~ =~
~ ~
~ ~
D=
~
~ ~
==
~ === ~
~ === ~
~ ~
··
0
..J
a..
&;~PRFSS
PLDC18G8
~, SEMICONDUCTOR
Ordering Information
(rnA)
Icc
Speed
(ns)
90
12
70
15
90
15
110
15
110
15
110
20
110
20
Package
Ordering Code
PLDC18G8-12JC
PLDC18G8-12PC
PLDC18G8-12VC
PLDC18G8-12WC
PLDC18G8L-15JC
PLDC18G8L-15PC
PLDC18G8L-15VC
PLDC18G8L-15WC
PLDC18G8-15JC
PLDC18G8-15PC
PLDC18G8-15VC
PLDC18G8-15WC
PLDC18G8-15JI
PLDC18G8-15PI
PLDC18G8-15WI
PLDC18G8-15DMB
PLDC18G8-15KMB
PLDC18G8-15LMB
PLDC18G8-150MB
PLDC18G8-15WMB
PLDC18G8-20n
PLDC18G8-20PI
PLDC18G8- 20WI
PLDC18G8-20DMB
PLDC18G8-20KMB
PLDC18G8-2OLMB
PLDC18G8-2QOMB
PLDC18G8-20WMB
Operating
Range
1YPe
J61
P5
V5
W6
J61
P5
V5
W6
J61
P5
V5
W6
J61
P5
W6
D6
Commercial
Commercial
Commercial
Industrial
Military
K71
L61
061
W6
J61
P5
W6
D6
Industrial
Military
K71
L61
061
W6
Document #: 38-00080-C
4-12
PAL®C20 Series
CYPRESS
SEMICONDUCTOR
Reprogrammable CMOS
PALC 16L8, 16R8, 16R6, 16R4
• Higb reliability
- Proven EPROM technology
- > lSOOV Input protection from electrostatic discharge
-100% AC and DC tested
-10% power supply tolerances
- High noise immunity
- Security feature prevents pattern
duplication
-100% programming and functional
testing
Features
• CMOS EPROM technology for reprogrammability
• Higb performance at quarter power
-tpo=2Sns
-ts = lOns
-tco = ISns
-Icc = 4SmA
• Higb performance at military
temperature
-tpo = 20ns
-ts = lOns
-tco = 15 ns
-Icc 70mA
• Commercial and military temperature
range
PALs are offered in 20-pin plastic and ceramic DIP, plastic SO], and ceramic LCC
packages. The ceramic package can be
equipped with an erasure window; when
exposed to UV light, the PAL is erased
and can then be reprogrammed.
Before programming, AND gates or
product terms are connected via EPROM
cells to both true and complement inputs.
Programming an EPROM cell disconnects an input term from a product term.
Selective programming of these cells allows a specific logic function to be implemented in a PALC device. PALC devices are supplied in four functional configurations designated 16R8, 16R6, 16R4,
and 16L8. These eight devices have potentially 16 inputs and 8 outputs configurable by the user. Output configurations of
8 registers, 8 combinatorial, 6 registers
and 2 combinatorial as well as 4 registers
and 4 combinatorial are provided by the
Functional Description
Cypress PALC Series 20 devices are highspeed electrically programmable and UVerasable logic devices produced in a proprietary N-well CMOS EPROM process.
These devices utilize a sum-of-products
(AND-OR) structure providing users with
the ability to program custom logic functions serving unique requirements.
=
Logic Symbols and DIP and SOJ Pinouts
16R8
16R6
16R4
16L8
vee
0
0
0
1/0
0
1/0
110
0
0
0
0
K....,.-illjIlO
o
o
rw-n---";:::I
1/0
...._~--= 1/0
VO
LCC Pinouts
• 3 2~,201f8
5
6
7
8
17
16
15
I'
910111213
o
o
o
o
o
•
5
6
7
8
32 L1,201:8
17
16
15
I.
910111213
•
o
o
o
o
5
6
7
8
o
3 2 ~,201:8
17
16
15
I.
810111213
PAL is a registered trademark of Monolithic Memories Inc.
CYPRESS SEMICONDUcroR is a trademark of Cypress Semiconductor Corporation.
4-13
I/O
a
a
a
a
• 3 2 ~,201f817
5
8
7
8
16
15
I.
910111213
va
va
va
va
va
II
U)
C
...J
a.
PALC20 Series
EPROM technology is the basis for a superior product with inherent advantages in reliability, testability, programming, and
functional yield. EPROM technology has the inherent advantage
that all programmable elements maybe programmed, tested, and
erased during the manufacturing process. This also allows the device to be 100% functionally tested during manufacturing. An
ability to preload the registers of registered devices during the
testing operation makes the testing easier and more efficient.
Combining these inherent and designed-in features provides an
extremely high degree of functionality, programmability and assured AC performance, and testing becomes an easy task.
The register preload allows the user to initialize the registered
devices to a known state prior to testing the device, significantly
simplifying and shortening the testing procedure.
FUnctional Description (continued)
four functional variations of the product family. All combinatorial outputs on the 16R6 and 16R4 as well as 6 of the combinatorial outputs on the 161.8 may be used as optional inputs. All registered outputs have the U bar side of the register fed back into
the main array. The registers are automatically initialized upon
power-up to Q output LOW and U output IDOH. All unused inputs should be tied to ground.
All PALe devices feature a security function that provides the
user with protection for the implementation of proprietary logic.
When invoked, the contents of the normal array may no longer
be accessed in the verify mode. Because EPROM technology is
used as a storage mechanism, the content of the array is not visible under a microscope.
Cypress PALe products are produced in an advanced 1.2-micron
N-well CMOS EPROM technology. The use of this proven
Commercial and Industrial Selection Guide
Generic
Part
Number
161.8
16R8
16R6
16R4
Output
Enable
Logic
Icc (rnA)
-Outputs
L
Com'I/IDd
45
~ 6~ Bidirectional
D-OR-Invert
2 Dedicated
(8) 8-wide AND-OR Dedicated
Registered Inverting 45
(6) 8-wide AND-OR Dedicated
Registered Inverting 45
Programmable Bidirectional
~7-wide
D-OR-Invert
(4) 8-wide AND-OR Dedicated
Registered Inverting 45
Programmable Bidirectional
~7-wide
D-OR-Invert
~7-wide
tPD (ns)
Programmable
ts (ns)
teo (ns)
-25 -35 -25 -35 -25 -35
70
25
35
70
-
-
15
25
25
35
20
20
30
70
30
15
25
70
25
35
20
30
15
25
Military Selection Guide
Generic
Part
Number
Logic
Output
Enable
Icc
Outputs
(rnA)
tPD (ns)
teo (ns)
ts (ns)
-20 -30 -40 -20 -30 -40 -20 -30 -40
161..8
Programmable
~7-wide
D-OR-Invert
70
20
30
40
-
-
-
-
16R8
~8-wide
D-OR
70
-
-
-
20
25
35
15
20
25
16R6
-wide
<:k8D-OR
70
20
30
40
20
25
35
15
20
25
~7-wide
~6~ Bidirectional
2 Dedicated
Dedicated
Registered
Inverting
Dedicated
Registered
Inverting
Programmable Bidirectional
~8-wide
Dedicated
70
20
30
40
20
25
35
15
20
25
D-OR-Invert
16R4
D-OR
~7-wide
D-OR-Invert
Registered
Inverting
Programmable Bidirectional
4-14
~
Em
:-;:::;Z
PALC20 Series
-=CYPRESS
_, SEMICONDUCTOR
Maximum Ratings
(Abovewhich the useful life maybe impaired_ Foruserguidelines,
nottested_ )
Storage Temperature _________________ - 65°Cto +150°C
Ambient Thmperaturewith
Power Applied _______________________
- 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 20 to Pin 10) _______________________ - 05Vto +7_0V
DC Voltage Applied to Outputs
in High Z State ________________________ - 05V to
DC Input Voltage ______________________ - 3_0Vto
Output Current into Outputs (LOW) _______________
DCProgrammingVoltage __ .............. _....... _.
UVExposure ... _... _. _.................. 7258Wsec/cm2
Static Discharge Voltage .... _... _...... _. _...... >200lV
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .... _........... _.. _........ >200mA
Operating Range
Ambient
Thmperature
Range
+ 7_0V
+7_0V
24 rnA
14.0V
O°Cto +75°C
Vee
5V±IO%
Military(1]
- 55°Cto +125°C
5V±IO%
Industrial
- 40°C to +85°C
Commercial
•
U)
C
Electrical Characteristics
Parameters
VOH
VOL
...J
Over the Operating Range (Unless Otherwise Noted)[2]
Description
Output HIGH Voltage
Output LOW Voltage
D.
Thst Conditions
Vcc=Min.,
VIN = Vm or VIL
Vee = Min.,
VIN = Vm or VIL
Min.
IOH = - 3.2mA
Com'l/Ind
IOH=-2mA
Military
IOL=24mA
Com'l!Ind
IOL= 12mA
Military
Vm
Input HIGH Level
Guaranteed Input Logical HIGH[3] Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW[2] Voltage for All Inputs
IJX
Input Leakage Current
Vss:5. VIN:5. Vee
Vpp
Programming Voltage
Ipp = 50 mA Max.
Ise
Output Short Circuit Current
Vee = Max., Vour = 05V[4]
Icc
Power Supply Current
All Inputs = GND, Vee = Max.,
lOUT = 0 mA[S]
2.4
Ioz
Vee = Max., Vss:5. VOUT:5. Vee
Units
V
0.4
2.0
V
V
0.8
V
-10
10
fAA
13.0
14.0
V
- 300
mA
"1:'
45
mA
Com'l!Ind
70
mA
70
mA
100
fAA
Military
Output LeakageCurrent
Max.
-100
Notes:
1.
2.
3.
tA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
5.
4-15
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. Vour = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
ICC(AC) = (0.6 mA/MHz) X (Operating Frequency in MHz) +
ICC(DC)' ICC(DC) is measured with an unprogrammed device.
~
~~CYPRESS
~, SEMICONOOcroR
PALC20 Series
Electrical Characteristics
Parameter
Vx
tpxz(-)
1.5V
tpxz(+)
2.6V
tpzx(+)
Vthc
tpzx (-)
Vthc
tER (-)
1.5V
tER( +)
2.6V
Over the Operating Range (Unless Otherwise Noted)[2] (continued)
Output Wlveform-Measurement Level
VOH O.5V
VOL
~
Vx
0.5V
~
Vx
O.5V
VOH 0.5V
tEA (+)
Vthc
tEA (-)
Vthc
t
O.5V
:
:
VOL
0.5V
Vx
O.5V
Vx
0.5V
~
~
t
~
~
~
~
~
~
~
~
VX
C~
VX
C2().10
VOH
C20-11
VOL
C2()'12
VX
C20-13
Vx
C2Q.14
VOH
C20-15
VOL
C20-16
Capacitance [6]
lest Conditions
Max.
Units
CIN
InputCapacitance
Description
TA = 25"C,f= 1 MHz
10
pF
CoUT
Output Capacitance
VIN = 0, Vee = 5.0V
10
pF
Parameters
Switching Characteristics
Over Operating Range[2, 7, 8]
Commercial/lndustrial
-25
Parameter
Description
MilL
Military
-35
Max.
-20
-30
-40
Min. Max. Min. Max. Min. Max. Min. Max. Units
tpD
Input or Feedback to Non-Registered
Output 16L8, 16R6, 16R4
25
35
20
30
40
ns
tEA
Input to Output Enable 16L8, 16R6,
16R4
25
35
20
30
40
ns
tER
Input to Output Disable Delay 16L8,
16R6, 16R4
25
35
20
30
40
ns
tpzx
Pin 11 to Output Enable 16R8, 16R6,
16R4
20
25
20
25
25
ns
tpxz
Pin 11 to Output Disable 16R8, 16R6,
16R4
20
25
20
25
25
ns
teo
Clock to Output 16R8, 16R6, 16R4
ts
Input or Feedback Set-Up Time
16R8, 16R6, 16R4
tH
tp
Hold Time 16R8, 16R6, 16R4
0
0
0
Clock Period
35
55
35
tw
Clock Width
15
20
12
20
25
fMAX
Maximum Frequency
15
20
28.5
Notes:
6. Thsted initially and after any design or process changes that may affect
these parameters.
7. Part ( a) of AC Thst Loads and Waveforms is used for aU parameters
except tEA, tER. tpzx and tpxz. Part (b) of AC Thst Loads and Waveforms is used for tEAo tE&, tpzx and tpxz.
15
25
30
18
8.
4-16
20
25
20
28.5
25
ns
35
ns
0
0
ns
45
60
ns
22
ns
16.5
MHz
The parameters tER and tpxz are measured as the delay from the input disable logic thresbold transition to VOH - O.5V for an enabled
mOH output or VOL + O.SV for an enabled LOW output. Please see
Electrical Characteristics for waveforms and measurement reference
levels.
PALC20 Series
AC Test Loads and Waveforms
R1 175n.
OUTP:~R2
i
50pF
l133n.
5V~R1175n.
OUTPUT
-!-
Equivalent to:
R2
5 pF
THEvENIN EQUIVALENT COMMERCIAL
'::" 133.n.
OUTPUT
O__.,~5\1\•.f.---O
2.16V = Vtllt
C20-18
(a) Commercial
(b) Commercial
5V~R1337n.
OUTPUT
-!-
C20-17
5V~R1337n.
R2
OUTPUT
1
50 pF '::" 247n.
I
OUTPUT
":"
0_-1"~\I\A'---O 2.11V = Vthm
C20-19
(d) Military
.OV~ ...
10%
GND
.s.5ns
I-
(e)
Switching Waveforms
INPUTS 110,
REGISTERED
FEEDBACK
~t"'ft"l~
~UL.l~
CP
REGISTERED
OUTPUTS _ _ _ _ _.....'-¥......,
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _LK.lLJt.¥
C20-22
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
PALe device. In addition, high ambient light levels can create
hole-electron pairs that may cause "blank" check: failures or
"verify errors" when programming windowed parts. This phenomenon can be avoided by using an opaque label over the window during programming in high ambient light environments.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2• For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure would be
approximately 35 minutes. The PALC device needs to be placed
within 1 inch of the lamp during erasure. Permanent damage may
result if the device is exposed to high-intensity UV light for an
extended period of time. 7258 Wseclcm2 is the recommended
maximum dosage.
4-17
•
II)
THEVENIN EQUIVALENT MILITARY
247n.
5PF
-=
(c) Military
Equivalent to:
R2
C
..J
Ill.
~
=--;::;z
.'~~ucroR
PALC20 Series
Logic Diagram PALC16L8
INPUTS (0
- 31)
1
0
3
4
7
8
11
12
16
16
19
20
2S 24
Z728
31
0
r-d
··
·
....
0-ti::
··
·
~.I-',,"
8
~
~
~
~
15
3
19
L
18
~
16
··
·
23
4
17
'~
24
··
·
31
5
.;>
16
~
32
··
·
,,39
6
...t>
40
~
~
··
·
... 47
7
~
48
··
·
,,55
8
2
56
;=J
··
·
-
... 63
9
L
3 4
7
8
11 12
15 16
19 20
23 24
27 28
15
14
13
12
11
31
020-23
4-18
-=-
~--..~
PALC20 Series
_'Ji!
CYPRESS
- . ; SEMICONDUCTOR
Logic Diagram PALC16R4
INPUTS (0 - 31)
1
0
3
4
7
8
11
12
15
16
19
20
23 24
27 28
31
0
J
·
>--tl
··
CD---ci=
8
II
~J
···
",'5
3
19
L
16
··
·
23
A
4
I/)
18
a..
~M
24
··
·
m
I
=Dl
~
~
~
~
~
a
31
.....
5
32
··
·
",39
6
A
L
40
··
·
47
7
~
48
~J
···
",55
8
56
··
·
~
~-
.... 63
9
3
4
7
8
11
12
15 16
19
20
23
24
27 28
:r-6J
13
12
~
31
C20-24
4-19
C
...J
PALC20 Series
Logic Diagram PALC16R6
INPUTS (0
1
0
3
4
7
8
11
12
- 31)
15 16
19
20
23 24
27 28
31
0
rdJ
··
·
0---ci=
8
··
·
./
.... 15
3
-'"
S-
f
19
n~
16
··
·
........
.... 23
-'"
4
24
··
·
........
... 31
.....
5
32
···
6
... 39
f
<;
.....
40
··
·
47
7
-'"
L
S-
48
··
·
""
....
... 55
8
56
~
~
n
n
n
u
~
~J
··
·
... 63
9
3
4
7
8
11 12
15 16
19 20
23 24
27 28
Q
~
~
~
12
~
31
C20-25
4-20
=-.-:~
PALC20 Series
= - i i i l CYPRESS
~.iF' SEMlCONDUCTOR
Logic Diagram PALC16R8
INPUTS (0 - 31)
1
0
3
4
7
8
11
12
15
16
19
20
23
24
Z12B
31
0
0
0
0
....
0--ti=
8
0
o
./
0
n-~
nnM
nM
nnnn-M
Q
.....
..... 15
3
....
.i>
18
~
0
o
./
0
.....
..... 23
4
24
0
"'
o
./
0
.....
.. 31
5
32
0
o
0
6
..... 39
.i>
<:
....
40
0
o
0
Q
7
"
.....
47
....
48
~
~
0
o
0
8
M
...
.. 55
56
-....
.
0
0
....
.. 63
9
3
4
7
8
11 12
15 16
19 20
23 24
4-21
Z1 2B
31
~
C20-26
=*::il~NDUCTOR
PALC20 Series
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1,6r-----,------,
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4 . - - - - , . - - . . . , - - - , . . - - - "
J3
1.2~--+--~-~~-~
c
~
~
~
~
~
oz
1--"7i"---/- TA = 25°C
f=fMAX
4,5
5,0
SUPPLY VOLTAGE
5,5
c
~
::J
~
1.2
M
1,1
1.0
/-----+--7--_1
~----#-'------~
25
.,.s
"-
~
a:
o
z
15
/'"
/'
10
5
V
o
o
~----+---T---I
1,0 /-------::oIL------j
25
125
AMBIENT TEMPERATURE (OC)
0,9
0,8
4,0
""
4,5
I~
5,0
"'- .....
5,5
SUPPLY VOLTAGE
6,0
M
NORMAUZEDSET-UPTIME
vs. SUPPLY VOLTAGE
V
.....
/
200
~
1,1
cw
!:l
~
~
1,0
a:
0
z
400
600
0,9
0,8
4,0
600 1000
NORMALlZEDCWCK-TO-OUTPUT
TIME vs. SUPPLY VOLTAGE
8
'"
4,5
~
5,0
""-.....
5,5
SUPPLY VOLTAGE
6,0
M
NORMAUZEDCWCK-TO-OUTPUT
TIME vs. TEMPERATURE
1,4,-----..,--------.
1.1...----.---,---,.----,
0
1,3
cw
1,2
0
cw
1,1
Z
CAPACITANCE (pF)
NORMALIZED SET-UPTIME
vs. TEMPERATURE
1,3 . . . - - - - - . - - - - - - - - ,
c
~
1.0
a:
1,2
!3w
c
~
:;:
DELTA PROPAGATION TIME
vs.OUTPUTWADING
AMBIENT TEMPERATURE (0C)
::J
!:l
g
60
w
I
oIf
i\.
~ 100
:::>
/
~ 125
~ 100
V
200
w
:::>
-- "
"
OUTPUT SOURCE CURRENT
140 vs. VOLTAGE
~ 120
/"
~ 150
1
4.0
~
40
~
" ~ ..........
~
c.. 20
~
o
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Ordering Information
tPD (ns)
ts (ns)
tco (ns)
Icc(mA)
20
-
-
70
PALC16L8-20DMB
D6
K71
45
PALC16L8-20KMB
PALC16L8-20LMB
PALC16L8-20QMB
PALC16L8-20WMB
PALC16L8L-25LC
70
PALC16L8L-25PC
PALC16L8L-25VC
PALC16L8L-25WC
PALC16L8-25LC
70
PALC16L8-25PC/PI
PALC16L8-25VCNI
PALC16L8- 25WC/WI
PALC16L8-30DMB
45
PALC16L8-30KMB
PALC16L8-30LMB
PALC16L8-30QMB
PALC16L8-30WMB
PALC16L8L-35LC
L61
Q61
W6
L61
Commercial
PALC16L8L-35PC
PALC16L8L-35VC
PALC16L8L-35WC
PALC16L8-35LC
PALC16L8-35PC/PI
PALC16L8-35VCNI
PALC16L8-35WC/WI
PALC16L8-40DMB
P5
V5
W6
L61
P5
V5
W61
D6
Military
PALC16L8-40KMB
PALC16L8-40LMB
PALC16L8-40QMB
PALC16L8-40WMB
K71
25
30
35
-
-
-
-
-
-
70
40
-
-
70
Ordering Code
4-23
Package'JYpe
Operating Range
Military
L61
Q61
W6
L61
Commercial
P5
V5
W6
L61
P5
V5
W61
D6
Military
K71
L61
Q61
W6
•
In
o
..J
a.
PALC20 Series
Ordering Information (continued)
teo
Icc
tpD
(ns)
ts
(ns)
(ns)
(rnA)
20
20
15
70
Package
Ordering Code
PALCI6R4-20DMB
D6
PALCI6R4-20KMB
K71
PALCI6R4-20LMB
L61
Q61
PALCI6R4-20QMB
25
20
15
45
70
30
25
20
70
PALCI6R4-20WMB
PALCI6R4L-25LC
PALCI6R4L-25PC
25
45
V5
W6
PALCI6R4- 25LC
PALCI6R4-25PC/PI
L61
P5
PALCI6R4-25VCNI
V5
PALCI6R4-25WC/WI
W6
PALCI6R4-30DMB
D6
PALCI6R4-30KMB
PALC16R4-30LMB
K71
70
PALCI6R4L-35LC
40
35
25
70
W6
L61
V5
PALC16R4L-35WC
W6
PALC16R4-35LC
L61
P5
V5
W6
PALC16R4-40KMB
K71
PALC16R4-40LMB
L61
Q61
4-24
Commercial
Military
Commercial
P5
PALCI6R4-35VC/VI
PALC16R4-35WC/WI
PALC16R4-40DMB
PALC16R4-40QMB
PALC16R4-40WMB
Military
L61
Q61
PALC16R4L-35PC
PALC16R4L-35VC
PALC16R4-35PClPI
Operating
Range
P5
PALCI6R4L-25WC
PALCI6R4-30WMB
30
W6
L61
PALCI6R4L-25VC
PALC16R4-30QMB
35
'JYpe
D6
W6
Military
lb~~PRE&S
,.
PALC20 Series
SEMICONDUCIDR
Ordering Information (continued)
tpD
t8
teo
Icc
(ns)
(ns)
(ns)
(mA)
20
20
15
70
25
20
15
45
70
30
35
25
30
20
25
70
45
70
40
35
25
70
Ordering Code
PALCI6R6-20DMB
PALCI6R6-20KMB
PALCI6R6-20LMB
PALC16R6-200MB
PALC16R6-20WMB
PALCI6R6L-25LC
PALCI6R6L-25PC
PALC16R6L-25VC
PALCI6R6L-25WC
PALCI6R6-25LC
PALCI6R6-25PC/PI
PALCI6R6-25VCNI
PALCI6R6-25WCIWI
PALCI6R6-30DMB
PALC16R6-30KMB
PALC16R6-30LMB
PALC16R6-300MB
PALC16R6-30WMB
PALC16R6L-35LC
PALC16R6L-35PC
PALCI6R6L-35VC
PALC16R6L-35WC
PALCI6R6-35LC
PALC16R6-35PC/PI
PALCI6R6-35VCNI
PALCI6R6-35WC/WI
PALCI6R6-40DMB
PALCI6R6-40KMB
PALC16R6-40LMB
PALC16R6-400MB
PALC16R6-40WMB
4-25
Package
'JYpe
D6
Operating
Range
Military
K71
L61
061
W6
L61
P5
V5
W6
L61
P5
V5
W6
D6
Commercial
U)
C
..J
a.
Military
K71
L61
061
W6
L61
P5
V5
W6
L61
P5
V5
W6
D6
K71
L61
061
W6
Commercial
Military
1ir,~NDUC1OR
PALC20 Series
Ordering Information (continued)
Icc
tpD
(ns)
ts
(ns)
teo
(ns)
(rnA)
-
20
15
70
-
20
15
45
70
-
-
25
30
20
25
70
45
70
-
35
25
70
Package
Ordering Code
1Ype
PALCI6R8-20DMB
D6
PALCI6R8-20KMB
K71
PALCI6R8-2OLMB
L61
PALCI6R8-2OQMB
Q61
PALCI6R8-2OWMB
W6
PALCI6RBL-25LC
L61
PALC16RBL-25PC
P5
PALC16RBL-25VC
V5
PALCI6RBL-25WC
W6
PALC16RB-25LC
L61
PALC16RB-25PClPI
P5
PALC16RB-25VC/VI
V5
PALCI6RB-25WC/WI
W6
PALC16RB-30DMB
D6
PALC16RB-30KMB
K71
PALCI6RB-30LMB
L61
PALCI6RB-30QMB
Q61
PALC16RB-30WMB
W6
PALC16RBL-35LC
L61
PALC16RBL-35PC
P5
PALC16RBL- 35VC
V5
PALC16RBL-35WC
W6
PALC16RB-35LC
L61
PALC16RB-35PClPI
P5
PALC16RB- 35VCNC
V5
PALC16R8-35WC/WC
W6
PALC16R8-40DMB
D6
PALC16R8-40KMB
K71
PALC16RB-40LMB
L61
PALC16RB-40QMB
Q61
PALC16RB-40WMB
W6
4-26
Operating
Range
Military
Commercial
Military
Commercial
Military
PALC20 Series
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIR
VIL
IIX
Vpp
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Icc
Ioz
•
I I)
C
..J
Il.
Switching Characteristics
Parameters
Subgroups
tpD
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tpzx
teo
ts
tH
Document #: 38-00001-D
4-27
PAL®20 Series
16L8, 16R8, 16R6,
ADVANCED INFORMATION
16R4
CYPRESS
SEMICONDUCTOR
5-ns, Industry-Standard
20-PinPLDs
Features
Functional Description
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD = 5ns
-ts = 4ns
-rMAX = 117 MHz
Cypress PAL20 Series devices consist of
the PAL16L8, PALI6R8, PAL16R6, and
PAL16R4. Using BiCMOS process and
Ti-W fuses, these devices implement the
familiar sum-of-products (AND-OR) logic structure.
The PAL device is a programmable AND
array driving a fixed OR array. The AND
array is programmed to create custom
product terms while the OR array sums
selected terms at the outputs.
• Popular industry standard architectures
• Power-up RESET
• Highreliability
-Proven Ti-Wfuses
- AC and DC tested at the factory
- >2001V input protection
A security fuse is provided on all the devices to prevent copying of the device fuse
pattern.
Programming
The PAUO Series devices can be programmed using the QuickPro II programmer available from Cypress Semiconductor and also with Data I/O, Logical Devices, Stag, and other programmers.
Please contact your local Cypress representative for further information.
The product selector guide details all the
different options available. All the registered devices feature power-up RESET.
The register Q output is set to a logic
LDW when power is applied to the devices.
• Security ruse
Logic Symbols and DIP Pinouts
16R8
16L8
16R4
16R6
Vee
H!>+--ill! VO
o
o
u:r'Ul'>or....
lTP..-nL.,.."
0
0
o
.....--rr--...:.::I
VO
PLCC/LCC Pinouts
__ 2; ~o
•5 3 2~,201f817
6
7
8
16
15
1.
910111213
a
a
a
a
a
•
5
6
7
8
32!,.1. 201
fa
17
18
15
1.
910111213
•
a
a
o
3 2~1201~8
17
16
15
8
1.
910111213
5
6
7
o
o
PAL is a registered trademark of Monolithic Memories Inc.
4-28
I/O
a
o
a
o
•
5
3 2~,201~8
17
16
7
15
8
1.
910111213
8
vo
va
va
vo
va
PLDC20GIOB/PLDC20GIO
CYPRESS
SEMICONDUCTOR
Features
• Fast
-Commercial: tpD 15 ns, teo 10
ns, ts = 12ns
- Military: lpp 20 ns, teo 15 ns,
ts=lSns
=
=
=
=
• Lowpower
- ICC maL: 70 mA, commercial
- Icc max.: 100 mA, military
• Commercial and military temperature
range
• User-programmable output cells
- Selectable for registered or combinatorial operation
- Output polarity control
_ - Output enable source selectable
from in 13 or roduct term
CMOS Generic 24-Pin
Reprogrammable Logic Device
• Generic architecture to replace standard logic functions including: 2OLlO,
2OLS, 2ORB, 2ORli, 2OR4, 12LlO, 14L8,
16L6,18L4,20L2,and20VS
• Eight product terms and one OE
product term per output
• CMOS EPROM tecbnology for
reprogrammabillty
• Highly reliable
- Uses proven EPROM tecbDology
- Fully AC and DC tested
- Security feature prevents logic pattern duplication
- :1:10% power supply voltage and
bigber noise Immunity
Functional Description
Cypress PlD devices are bigb-speed electrically programmable logic devices.
These devices utilize the sum of products
(AND-OR) structure providiug users the
ability to program custom logic functions
for unique requirements.
In an unprogrammed state tbe AND
gates are connected via EPROM cells to
both the true and complement of every
input. By selectively programming the
EPROM cells, AND gates may be connected to either the true or complement
or disconnected from both true and
complement inputs.
Cypress PlD C20GlO uses an advanced
O.8-micron CMOS technology and a proven EPROM cell as tbe programmable element. This technology and the inherent
Logic Block Diagram
va"
IJOE
1107
va"
va"
va.
1/00
1103
1/00
110,
vee
IlOo
20010-1
Pin Configurations
LCC
STDPLCC
JEDEC PLCC[l)
Top View
ThpVIew
Thp'V"Jew
---~~g'g
!1 __ ~>8g'g
I
I
I
I
I
I
NO
4 3 2!1! 282726
5
25
6
24
7
23
PLDC2OG10
8
22
PLDC2OGIOB
9
21
10
20
11
19
12131415161718
--~~~g'g
4321282728
NC
1/00
IIOa
110.
1/00
va"
IIOr
--,;I~~~~
4321282728
uo.
NO
I
I
IIOa
I
I
I
IIOa
Vas
vo.
NO
1/00
IIOr
I
---,;I~~~
20010-2
Note:
1. The CG7C323 is the PLDC20GIO packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for
4-29
NC
110.
I
I
I
NC
NC
1102
110.
110.
2OO1G-4
IlOo
1107
- -,;I!i!~ §' §'
20010-3
both PLCC pinoU1s. The difference is in the location of the "no connect" or NC pins.
II)
C
..J
A.
PLDC2OGIOB/PLDC20GIO
Selection Guide
tpo (DB)
Icc(mA}
Generic
Part Number
L
Com/lnd
2OG10B-15
2OG10B-20
2OO1OB-25
2OG10-25
20010-30
20010-35
20010-40
Mil
Com/Ind
Com/IDd
15
70
70
100
100
55
12
12
20
25
20
30
40
20GIO Functi!)nal Description
The PlDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to:
20L10, 2OLS, 2OR8, 2OR6, 20R4, 12L10, 14LS, 161..6, 18LA,
20L2, and 2OV8. Thus, the PlDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin
devices. It is executed in a 24-pin 3OG-mil molded DIP and a
30G-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the
20GI0 is erased and then can be reprogrammed.
The Programmable Output Cell provides the capability of defining the architecture of each output individually. Each of the 10
output cells may be configured with registered or combinatorial
outputs, active HIGH or active LOW outputs, and product term
or Pin 13 generated output enables. Three architecture bits determine the configurations as shown in the Configuration Thble and
in Figures 1 through 8. A total of eight different configurations
10
12
Mil
15
15
15
30
80
advantage of being able to program and erase each ceD enhances
the reliability and testability of the circuit. This reduces the burden on the customer to test and to handle rejects.
A preload function allows the registered outputs to be preset to
any pattern during testing. Preload is important for testing the
functionality of the Cypress PlD device.
15
18
ComJInd
20
20
35
Functional Description (continued)
Mil
15
25
80
55
teo (DS)
ts (DS)
Mil
25
35
25
are possible, with the two most common shown in Figure 3 and
Figure 5. The default or unprogrammed state is registered/active!
LOW/Pin 11 OB. The entire Programmable Output Cell is shown
in the next section.
The architecture bit 'C!' controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an JlO pin, or if the output is disabled, as an
input only. Any unused inputs should be tied to ground. In either
registered or combinatorial configuration, the output of the register is fed back to the array. This allows the creation of controlstate machines by providing the next state. The register is clocked
by the signal from Pin 1. The register is initialized on power up to
Q output LOW and U output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit 'C2'. The OE signal may be generated within the
array, or from the extemaI t:m (Pin 13). The Pin 13 allows direct
control of the outputs, hence having faster enable!disable times.
Each output cell can be configured for output polarity. The output can be either active HIGH or active LOW. This option.is controlled by architecture bit 'CO'.
Along with this increase in functional density, the Cypress
PlDC2OGlO provides lower-power operation ~hrough the use of
CMOS technology and increased testability with a register preload feature.
Programmable Output Cell
r--------------------OE PRODUCT TERM
OUTPUT Ht--+-""'-1
t-_ _-Is~
~ -----r--~--------------_;_;--+_~
Of
~ --~-----------~
PIN 13
4-30
20010.5
s.;~
PLDC20GIOB/PLDC20GIO
~'~~UcroR
Configuration Thble
Figure
Cz
Cl
Co
1
0
0
0
Configuration
Product Thnn OE/Registered/Active LOW
2
0
0
1
Product Tenn OE/RegisteredlActive HIGH
5
0
1
0
Product TennOE/Combinatorial/Active LOW
6
0
1
1
Product ThrmOE/CombinatoriaVActive HIGH
3
1
0
0
Pin 13 OE/Registered/Active LOW
4
1
0
1
Pin 13 OE/Registered/Active HIGH
7
1
1
0
Pin 13 OE/Combinatorial/Active LOW
8
1
1
1
Pin 13 OE/CombinatoriaVActive HIGH
II
en
C
....
a.
Registered Output Configurations
Cz = 0
Cl =0
)----10
)----10
Q
Co= 1
Q
20010-6
2OG10--7
Figure 1. Product Thrm OE/Active WW
Figure 2. Product Thrm OE/Active mGH
C2= 1
C2= 1
o
Q
Cl =0
Cl =0
Co= 0
Co= 1
20010-8
20010-8
Figure 4. Pin 13 OE/Active mGH
Figure 3. Pin 13 OE/Active LOW
Combinatorial Output Configurations[2]
C2 = 0
C2= 0
=1
Cl = 1
Cl
Co=O
Co= 1
20010-10
20010-11
Figure 6. Product Thrm OE/Active mGH
Figure S. Product Thrm OE/Active WW
C2= 1
C2=
Cl = 1
Cl = 1
Co=O
Co= 1
2OG10-12
20010-13
PIN 13
PIN 13
Figure 8. Pin 13 OE/Active mGH
Figure 7. Pin 13 OE/Active WW
Notes:
2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected
4-31
1
dfii
~~CYPRFSS
~,
PLDC20GIOB/PLDC20GlO
SEMICOND\JCIOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 16 rnA
Electrical Characteristics
Parameters
DC Programming Voltage
PLDCZOGlOBandCG7C323B-A ................. 13.0V
PLDCZOGlOand CG7C323-A .................... 14.0V
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
'lemperature
O°Cto +75°C
Vee
5V±1O%
Military!j I
- SSOCto +125°C
SV±10%
Industrial
- 40°C to +S5°C
SV±1O%
Range
Commercial
Over the Operating Range (Unless Otherwise Noted)[4j
Deseription
'lest Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min.,
VIN = VIH or VIL
IOH= - 3.2 rnA Com'l!Ind
Military
IoH = - 2 rnA
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIH or VIL
IOL=24rnA
Com'VInd
VIH
Input mGH Level
Military
IOL= 12 rnA
Guaranteed Input Logical HIGH Voltage for All InputsPl
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All InputsPl
IJX
Input LeakageCurrent
Vss 5 VIN 5 Vee
Ise
lee
Output Short Circuit Current Vee = Max., VOUT = O.SVlb, II
Ioz
Power Supply Current
Output LeakageCurrent
Units
V
0.5
V
2.0
-10
05VIN5 Vee
Vee = Max.,
lOUT = ornA
UnprogrammedDevice
Max.
2.4
V
O.S
V
+10
fAA
-90
rnA
Com'l!Ind -15, - 20
70
rnA
Com'VInd-2S, -35
55
rnA
Military-20, -25
100
rnA
Military-30, -40
SO
rnA
100
fAA
-100
Vee - Max., Vss5 VOUT 5 Vee
Capacitance [7]
Parameters
CIN
Deseription
InputCapacitance
CoUT
OutputCapacitance
'lest Conditions
Notes:
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A suhgroup testing information.
5. These are absolute values with respect to device ground. AIl overshoots due to system or tester noise are included.
TA = 25°C,f= 1 MHz
Max.
10
Units
pF
VIN = 2.0V; Vee = S.OV
10
pF
6.
7.
4-32
Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
'Iested initially and after any design or process changes that may affect
these parameters.
¥-:~
PLDC20G10BIPLDC20G10
=-iilCYPRESS
F
SEMICONDUCTOR
AC Test Loads and Waveforms (Commercial)
R1 23&1
R1 23&1
5v~(319.o.
MIL)
OUTPUT
5V:=F1(319.o.
MIL)
OUTPUT
R2
INCLUDING
JIG AND
SCOPE
I-=
50pF
170.0.
236.0. MIL
-=
(
)
INCLUDING
JIG AND
SCOPE
(a)
I
5 pF
-=
-=
20G1().14
(b)
I
Equivalent to:
R2
170.0.
(236.0. MIL)
I
THEVENIN EQUIVALENT (Commercial)
Equivalent to:
99n
THEVENIN EQUIVALENT (Military/Industrial)
136n
OUTPUT ~ 2.13V = Vthm
OUTPUT ~ 2.08V = Vthc
20010-15
20010-16
•
en
C
...J
Switching Characteristics
a.
Over Operating Rangel3, 8,9]
Commercial
B-15
Parameters
Description
B-20
-25
-35
Min. Max. Min. Max. Min. Max. Min. Max. Units
tpD
Input or Feedback to Non-RegisteredOutput
15
20
25
35
ns
tEA
Input to Output Enable
15
20
25
35
ns
tER
Input to Output Disable
15
20
25
35
ns
tpzx
Pin 11 to Output Enable
12
15
20
25
ns
tpxz
Pin 11 to Output
Disable
12
15
20
25
ns
teo
Clock to Output
25
ns
ts
Input or Feedback Set-Up Time
tH
tp[lO]
Hold Time
0
0
Clock Period
22
24
tWH
Clock Higb Time
8
10
tWL
Clock Low Time
8
fMAX[ll]
Maximum Frequency
45.4
Notes:
8. Part (a) of AC Thst Loads and Waveforms used for all parameters except tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms
used for tER, tpzx, and tpxz.
9. The parameters!ER and tpxz are measured as the delay from the input
disable logic threshold transition to V OH - O.5V for an enabled HIGH
ontpnt or VOL + O.5V for an enabled WW input.
10. ts minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tp = ts + teo. The minimum
15
12
10
12
12
15
30
ns
0
0
ns
30
55
ns
12
17
ns
10
12
17
ns
41.6
33.3
18.1
MH2
guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (twH + twD or (Is + tH).
11. fMAX, minimum guaranteed operating frequency, is that guaranteed
for state machine operation and is calculated from fMAX = 1/(Is +
teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower 0 1/(twH + tWL) or
1/(ts + tH)·
4-33
~
~-CYPRESS
~,
PLDC20GIOBIPLDC20GIO
SEMlCONDUCTOR
Switching Characteristics
Over Operating Range ( continued)
Military/lndustrial
B-20
Parameters
Description
-40
-30
B-25
Min. Max. Min. Max. Min. Max. Min. Max. Units
tpD
Input or Feedback to Non-Registered Output
20
25
30
40
ns
tEA
Input to Output Enable
20
25
30
40
ns
tER
Input to Output Disable
20
25
30
40
ns
tpzx
Pin 11 to Output Enable
17
20
25
25
ns
tpxz
Pin 11 to Output
Disable
17
20
25
25
ns
teo
Clock to Output
15
15
20
25
ns
ts
Input or Feedback
Set-UpTime
tH
tpllO)
Hold Time
0
0
Clock Period
30
33
tWH
Clock High Time
12
14
tWL
Clock Low Time
12
fMAXIll)
Maximum Frequency
33.3
15
35
DS
0
0
ns
40
60
ns
16
22
ns
14
16
22
ns
30.3
25.0
16.6
MHz
18
20
Switching Waveform
INPUTS I/O, ~r-K"7C"l""
REGISTERED
FEEDBACK .............."""""
CP
tpzx
REGISTERED
OUTPUTS: _ _ _ _ _--'...........,
tEA
COMBINATORIAL
OUTPUTS: _ _ _ _ _ _ _ _ _
~~~~
20010-17
4-34
~.~
~ifCYPRESS
PLDC20GIOB/PLDC20GIO
~, SEMICONDUCTOR
Functional Logic Diagram
rt::
0
4
8
12
16
20
24
28
·
40
J:B../
programmeravailable from Cypress Semiconductor and also with
Data I/O, Logical Devices, STAG, and other programmers. Please
contact your local Cypress representative for further information.
Macrocell
r---------------------lI
OE PRODUCT TERM
0
OUTPUT
ENABLE
MUX
C2
10
00
01
CP
OUTPUT
SELECT
MUX
C,
Co
INPUT!
FEEDBACK
MUX
C,
~ ------;----+--________________
------+---~------------------~-+--~--~
I
C,
_ _ _ oJI
Co
~
------+---------------------------
OEPIN
QuickPro II is a trademark of Cypress Semiconductor Corporation.
4-38
G1OC-4
&~
PRELIMINARY
~=CYPRESS
~_'J SEMICONDUCTOR
PLD20GIOC
Configuration Table
Configuration
Figure
C2
Cl
Co
1
0
0
0
Product Term OE/Registered/Active LOW
Product Term OE/Registered/Active HIGH
2
0
0
1
5
0
1
0
Product TermOE/Combinatorial/Active LOW
6
0
1
1
Product TermOE/CombinatoriallActive HIGH
3
1
0
0
Pin OE/Registered/Active LOW
4
1
0
1
Pin OE/Registered/Active HIGH
7
1
1
0
Pin OE/CombinatoriaVActive LOW
8
1
1
1
Pin OE/CombinatoriaVActive HIGH
U)
C
..J
Registered Output Configurations
Q.
}-----\o
Q
G1OC-5
G10C-6
Figure 1. Product Term OE/Adive LOW
Figure 2. Product Term OE/Active HIGH
Cz= 1
Cl = 0
o
Co= 1
Q
Gl0C-B
Gl0C-7
Figure 3. Pin OE/Active LOW
Figure 4. Pin OE/Active IDGH
Combinatorial Output Configurations[l]
G1OC-9
G1OC-l0
Figure 6. Product Term ~E/Active IDGH
Figure 5. Product Term OE/Active LOW
$"~,,
PINOE
Figure 8. Pin OE/Active IDGH
Figure 7. Pin OE/Active WW
Notes:
1. Bidirectional I/O configurations are possible only when the combinatorial output option is selected.
4-39
,gf.:,~
•
-=
,
PRELIMINARY
CYPRESS
SEMICONDUCTOR
PLD20GIOC
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . .. - 55 ° C to + 125°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... - O.5V to Vee
DC Input Voltage ........................ - O.5V to Vee
DC Input Current .................... - 30 mA to +5mA
(except during programming)
DC Program Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Operating Range
Range
Commercial
Militaryf2]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±5%
- 55°Cto +125°C
4.75V to 5.5V
DC Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output WW Voltage
Min.
Thst Conditions
Vee = Min.,
VIN = VIH or VIL
IOH = - 3.2mA
Com'l
IOH = -2mA
Mil
Vee = Min.,
VIN = VIH or VIL
IOL= 16mA
Com'l
IOL= 12mA
Mil
VIH
Input HIGH Voltage
GuaranteedInput Logical HIGH Voltage for Allinputs[3]
VIL
Input WW Voltage
GuaranteedInput Logical LOW Voltage for All Inputs[3]
IJX
Input LeakageCurrent
VSSS VINS2.7V, Vee = Max.
II
MaximumInputCurrent
VIN = Vee, Vee = Max.
Max.
2.4
V
0.5
2.0
- 250
Units
V
V
0.8
V
50
!lA
!lA
Com'l
100
Mil
250
Ioz
Output LeakageCurrent
Vee = Max., VSSS VOUT S Vee
-100
100
!lA
Ise
Output Short Circuit Current
Vee = Max., VOUT = 0.5V[4]
- 30
-120
mA
Icc
Power Supply Current
Vee = Max., VIN = GND, Outputs Open
Com'l
190
mA
Mil
190
Notes:
2. TA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. V OUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
4-40
~~
PRELIMINARY
§5iiiIiII'.= CYPRESS
-:f!i!!!!!!!!!lF SEMICONDUcroR
PLD20GIOC
Switching Characteristics PLD20GIOC[5]
-7
Parameters
Description
Min.
-12
-10
Max. Min.
Max. Min.
-15
Max. Min.
Max.
Units
2
15
ns
2
15
ns
12
2
15
ns
2
12
2
15
ns
2
12
2
15
ns
1
9.5
1
10
ns
tPD
Input to Output PropagationDelay[6]
2
7.5
2
10
2
12
tEA
Input to Output Enable Delay
2
7.5
2
10
2
12
tER
Input to Output Disable Delay[7]
2
7.5
2
10
2
tpzx
OE Input to Output Enable Delay
2
7.5
2
10
tpxz
OE Input to Output Disable Delay
2
7.5
2
10
teo
Clock to Output Delay[6]
1
6.5
1
7.5
ts
Input or Feedback Set-Up Time
tH
Input Hold Time
tp
External Clock Period (teo
3
+ ts)
4.5
3.6
7.5
ns
0
0
0
0
ns
9
11.1
14
17.5
ns
ns
tWH
Clock Width HIGH[8]
3
3
3
6
tWL
Clock Width LOW[8]
3
3
3
6
ns
fMAXi
External Maximum Frequency (l/(tco
105
90
71
57
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL»[8, 10]
166
166
166
83
MHz
fMAX3
Internal Feedback Maximum Frequency
(1/(tcp + tS»[ll]
133
100
83
66
MHz
tcp
Register Clock to FeedbackInput[12]
tpR
Power-Up Reset Timd13]
+ tS»[9]
6.4
4.5
1
1
7.5
1
7.5
1
ns
!.IS
Capacitance [8]
CIN
Parameters
Description
InputCapacitance
CoUT
OutputCapacitance
Notes:
5. AC test load used for all parameters except where noted.
6. Thisspecificationis guaranteed for all device outputs changing state in
a given access cycle.
7. lbis parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. lbis delay
is measured to the point at which a previous mGH level has fallen to
0.5 volts below VOH min. or aprevious LOWlevel has risen toO.5volts
above VOL max.
8. 'Il:stedinitially and after any design or process changes that may affect
these parameters.
9. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
lO. lbis specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
Max.
8
10
Units
pF
pF
11. lbis specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
12. lbis parameter is calculated from the clock period at fMAX internal
(fMAJ{3) as measured (see Note 11) minns!s.
13. The registers in the PLD20G10Chave been designed with the capability to reset during system power-up. Following power-up, all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. lbisfeature is useful in establishing state
machine initialization. Th insure proper operation, the rise in V cc
must be monotonic and the timing constraints depicted in power-up
reset wavefonns must be satisfied.
4-41
•
U)
C
-I
a.
PRELIMINARY
PLD20GIOC
AC Test Loads and Waveforms
R1 238.0.
5V T.1(319.o.MIL)
OUTPUT
R2
170.0.
(236.0. MIL)
CL
I
INCWDING
JIG AND
':"
SCOPE
OUTPUT
Package
lSpF
PID
SOpF
JIK/lJY
':"
G1OC-13
I
Equivalent to:
CL[14]
THEVENIN EQUIVALENT
O-~Y~\I\'!)-~---
0
,
8
12
16
20
2'
28
32
~
~7
··
0
cell
(3)
DE
··
-f":::,
0
Macrocell
6--
7
(4)
DE
0
·
--f:::.
~
··
0
=--
g3"
-f'>7
(6)
DE
··
0
(7)
·
DE
0
·
-1".:,1
DE
0
·
21
(25)
20
(24)
19
(23)
18
(21)
17
(20)
cell
:::1--
16
(19)
Macrocell
DE
··
0
11
(13)
Q.
Macro-
§:jd----
-f':::7
(11)
10
(12)
~
~
D--'
(10)
9
Macrocell
~
..,.
~7
(9)
8
Macrocell
..-1.
~
=-
-f'::: 7
Macrocell
"1-----
~
~
DIKIP (JIUY) Pinouts
4-45
15
(18)
14
(17)
13
(16)
G10C21
In
C
.J
H==\
0
7
6-
~
DE
22
(26)
Macrocell
..,.
...... 7
6 -l
Macrocell
6-
7
DE
5
23
(27)
Macro-
--f') 7
2
4
cell
d----
:B=:I
DE
(5)
40
~
0
·
3
36
=~
~d-~
~
~
~
~
~
~
~
~
~
DE
1irA~DUcroR
PRELIMINARY
Ordering Information
Icc(mA)
190
tpD (ns)
7.5
fMAX(MHz)
10
90
105
12
71
15
57
Ordering Code
PLD20GlOC-7DC
PLD20G 10C-7JC
PLD20GlOC ?PC
PLD20G10C-7YC
PLD20GlOC-10DC
PLD20G lOC-1OJC
PLD20GlOC 10PC
PLD20G 10C-lOYC
PLD20GlOC-lODMB
PLD20GlOC-lOKMB
PLD20GlOC-lOLMB
PLD20GlOC lOYMB
PLD20G lOC-12DC
PLD20GlOC-12JC
PLD20GlOC 12PC
PLD20GlOC 12YC
PLD20GlOC-12DMB
PLD20GlOC-12KMB
PLD20GlOC-12LMB
PLD20GlOC 12YMB
PLD20G1OC-15DMB
PLD20GlOC-15KMB
PLD20GlOC-15LMB
PLD20GlOC 15YMB
Package lYPe
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameters
Subgroups
VOH
VOL
Vru
VIL
IIX
Ioz
Icc
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
7,8,9,10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
teo
ts
tH
Document#: 38-A-00027
4-46
Operating Range
Commercial
Commercial
Military
Commercial
Military
Military
PLD20GIOC
PLDC20RAIO
CYPRESS
SEMICONDUCTOR Reprogrammable Asynchronous
CMOS Logic Device
Features
• Advanced-user programmable macrocell
• CMOS EPROM technology ror reprogrammability
• Up to 20 input terms
• 10 programmable I/O macrocells
• Output macrocell programmable as
combinatorial or asynchronous Dtype registered output
• Product-term control or register
clock, reset and set and output enable
• Register preload and power-up reset
• Four data product terms per output
macroceU
- Military/lndustrial
tpo = 20ns
leo =20ns
tsu = 10ns
• Lowpower
- Icc max - 80 mA (Commercial)
- Icc max = as mA (Military)
• High reliability
-Proven EPROM technology
- >2001V input protection
-100% programming and Ibnctional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, PLCC available
Functional Description
The Cypress PLDC20RA10 is a high-perfonnance, second-generation program-
• Fast
- Commercial
tpo = 15ns
teo 15 ns
tsu 7ns
mabIe logic device employing a flexible
macrocell structure that allows any individual output to be configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation with superior speed
performance than functionally equivalent
bipolar devices through the use of highperformance 0.8-micron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24
pin 3OO-mil molded DIP, a 300-mil windowed cerDIp, and a 28-lead square leadless chip carrier, providing up to 20 inputs
and 10 outputs. When the windowed device is exposed to UV light, the 2ORA10
is erased and can then be reprogrammed.
=
=
Logic Block Diagram
Is
1107
IlOo RAlo-1
Vee
Selection Guide
Generic Part
Number
tpo ns
Com
20RA10-15
15
20RAlO-20
20
20RAIO-35
Com
tsu ns
Mil/lnd
7
20
10
25
20RA10-25
20RA10-30
Mil/lnd
30
10
20
15
leons
Mil/lnd
20
4-47
Com
Icens
Mil/lnd
80
20
80
85
85
25
30
15
35
Com
15
80
35
85
•
I I)
C
...J
a..
PLDC20RAIO
Pin Configurations
LCC
ThpView
8m PLCCIHLCC
ThpView
JEDEC PLCClHLCC [1)
ThpView
.!'.r~1~~!f2
.. 3 2_1 i 282726
125
••
!SHe
13
14
15
18
17
He
8
7
8
9
10
11
24
23
PLDC20RA10 22
21
20
19
12131415181718
1102
1103
1104
1105
1108
1107
RA1D-2
:~I~!il ~g>g
4321282728
NO
4321282728
15
18
1'02
1'03
1104
1'05
1'0&
1'07
NO
NO
13
14
He
-"'"_·.!"$Il!l~~
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well as
one term for control of the output enable function.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automatically chosen for all outputs since, for this case, the extemaI output
enable pin must be tied LOW. The active polarity of each output
may be programmed independently for each output cell and is
subsequently fixed. Figure 2 illustrates the output enable options
available.
When an IJO cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset product
term outputs to be mGH under all input conditions. This is
achieved by programming all input term programming cells for
these two product terms. Figwe 3 illustrates the available output
configuration options.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-dermed
logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input, the
device input configuration programmed by the user may val}'
from a total of nine programmable plus ten dedicated inputs (a
total of nineteen inputs) and one output down to a ten-input, tenoutput configuration with all ten programmable I/O cells configured as outputs. Each input pin available in a given configuration
RAl().3
PLDC20RA10
110 2
1103
1104
NO
1105
1108
1107
-·.!"$!illl!l~~
RA1D-4
is available as an input to the four control product terms and four
uncommitted product terms of each programmable IJO macrocell
that has been configured as an output.
An I/O cell is programmed as an input by tying the output enable
pin (pin 13) mGH or by programming the output enable product
term to provide a Ww. thereby disabling the output buffer, for
all possible input combinations.
When utili2ing the IJO macrocell as an output, the input path
functions as a feedback path allowing the output signal to be fed
back as an input to the product term array. When the output cell
is configured as a registered output, this feedback path may be
used to feed back the current output state to the device inputs to
provide current state control of the next output state as required
for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of
each register to be set by loading each register from an external
source prior to exercising the device. Thsting of complex state machine designs is simplified by the ability to load an arbitrary state
without cycling through long test vector sequences to reach the
desired state. Recovel}' from illegal states can be verified by loading illegal states and observing recovel}'. Preload of a particular
register is accomplished by impressing the desired state on the
register output pin and lowering the signal level on the preload
control pin (pinl) to a logic WW level. If the specified preload
set-up, hold and pulse width minimums have been observed, the
desired state is loaded into the register.1b insure predictable system initiali2ation, all registers are preset to a logic WW state
upon power-up, thereby setting the active WW outputs to a logicmGH.
Notes:
1. The CG7C324 is the PUlC20RAlOpackaged in theJEDEC-almpatible 28-pin PLCC pinout. Pin fuction and pin order is identical for
both PLCC pinouts. The principle differencd is in the location of the
"no connect" (NC) pins.
4-48
PLDC20RAIO
OUTPUT ENABUE
(FROM PIN 13)
PRELOAD
(FROM PIN 1)
•
TO 110 PIN
co
~
a.
...I
P~---+O<
R
RA1O-S
Figure I. PLDC20RAIO Macrocell
Output Always Enabled
Programmable
~.---
--[)o...-----
RA10-7
RA10-6
Combination of
Programmable and Hardwired
External Pin
-~r--RA10-8
RAlO-9
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RAIO
4-49
~-~
' . CYPRESS
?
PLDC20RAIO
SEMICONDUCTOR
Registered/Active LOW
Combinatorial/Active LOW
RA10-11
RA10-10
Combinatorial/Active HIGH
Registered/Active HIGH
RA10-12
Figure 3. Four Possible Macrocell Configurations for the PLDC20RAIO
4-50
RA10-13
=~
_'iECYPRESS
-==
IF
PLDC20RA10
SEMICONDUCfOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied . . . . . . . . . . . . .. .. . . . . . . .. - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - 0.5V to + 7.0V
DC Input Voltage ...................... -3.0 V to + 7.0 V
Output Current into Outputs (LOW) ................ 16 rnA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
DC Program Voltage ............................ , . 13.0V
Operating Range
Ambient
temperature
Vee
O°Cto +75°C
5V± 10%
Industrial
-40°C to +85°C
5V± 10%
Military!2]
- 55°Cto +125°C
5V ± 10%
Range
Commercial
•
I I)
C
..J
a.
Electrical Characteristics Over the Operating Range[3]
Parameters
VOH
Description
test Conditions
Output mGH Voltage
Vee = Min.,
VIN = VIH or VIL
Min.
IOH = -3.2rnA
Com'l
IOH = -2rnA
MilJInd
Max.
Units
V
2.4
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIH or VIL
VIH
Input mGH Level
Guaranteed Input Logical mGH Voltage for All Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[4]
IIX
Input LeakageCurrent
VssSVIN SVee, Vee = Max
-10
Ioz
Output LeakageCurrent
Vee = Max., Vss SVoUTSVee
-40
+40
Ise
Output Short Circuit Currend5]
Vee = Max., VOUT = 0.5y[6]
-30
-90
rnA
IcC!
Standby Power Supply Current
Vee= Max., VIN = GND Outputs Open
Com'l
75
rnA
MiVlnd
80
rnA
Iccz
Power
Frequen
Com'l
80
rnA
MiVInd
85
rnA
s#r Current at
0.5
IOL=8rnA
Vee = Max., Outputs Disabled (In High Z State)
Device Operating affMAX
2.0
V
0.8
V
+10
fAA
fAA
Capacitance [5]
Parameters
Description
test Conditions
Max.
Units
CIN
InputCapacitance
VIN = 2.0V@f= 1 MHz
10
pF
CoUT
Output Capacitance
VOUT = 2.0V@f= 1 MHz
10
pF
Notes:
2.
TA is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to devicee ground and all overshoots due to system or tester noise are included.
Thsted initially and after any design or process changes that may affect
these parameters.
Not more than one output should be tested at a time, Duration of the
short circuit should not be more than one second. VOUT = 0.5 V has
been chosen to avoid test problems caused by tester ground degradation.
4.
5.
6.
7.
8.
4-51
V
Part (a) of AC Test Loads was used for all parameters exceptlEA, tER,
tpzx and tpxz, which use part (b).
The parameters tER and tpxz are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled
mGR output or VOL +0.5V for an enabled LOW output. Please see
part (c) of AC Test Loads and Waveforms fotwaveforms and measurement reference levels.
~~
~=CYPRESS
~_F
PLDC20RA10
SEMICONDUClDR
Switching Characteristics Over the Operating Rangel3, 7, 8]
Commercial
-20
-15
Parameters
Description
Min.
Max. Min.
-30
Military/lndustrial
-25
-20
Max. Min. Max.
Min.
Max. Min. Max.
-35
Min.
Max. Units
tpD
Input or Feedback to
Non-RegisteredOutput
15
20
30
20
25
35
ns
tEA
Input to Output Enable
15
25
30
20
30
35
ns
tER
Input to Output
Disable
15
25
30
20
30
35
ns
tpzx
Pin 13 to Output
Enable
12
15
20
15
20
25
ns
tpxz
Pin 13 to Output
Disable
12
15
20
15
20
25
ns
tco
Clock to Output
35
ns
tsu
Input or Feedback
Set-UpTime
7
10
15
10
15
20
ns
tH
Hold Time
3
5
5
3
5
5
ns
tp
Clock Period
(tsu + teo)
22
30
45
30
40
55
ns
tWH
Clock Width HIGH
10
13
20
12
18
25
ns
tWL
Clock Width LOW
10
13
20
12
18
25
ns
fMAX
Maximum Frequency
45.5
33.3
22.2
33.3
25.0
18.1
MHz
15
30
20
20
25
(Vtp)
ts
Input to Asynchronous
Set of Registered
Output
15
20
35
20
25
40
ns
tR
Input to Asynchronous
Reset of Registered
Output
15
20
35
20
25
40
ns
tAR
AsynchronousSet/
Reset Recovery Time
twp
Preload Pulse Width
tsup
Preload Set-Up Time
tHP
Preload Hold Time
15
12
15
12
15
20
ns
15
15
15
15
15
15
ns
15
15
15
15
15
15
ns
15
15
15
15
15
ns
10
AC Test Loads and Waveforms (Commercial)
R1 4570
(4700 mil)
R1 4570
(4700 mil)
ALL INPUT PULSES
3.0V---90%
5V~ R2
OUTPUT
50 PF.l
INCLUDING JIG AND
SCOPE
5 V 3 = t R2
OUTPUT
GND
2700
2700
(319QMiI)
5PF.l
(319QMiI)
INCLUDING JIG AND
SCOPE
RAl0·l0
(a)
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT (Commercial)
~
RA1D-15
(b)
Equivalent 10:
1.86V=Vthc
RAID-IS
4-52
THEVENIN EQUIVALENT (Military/lnduslrial)
OUTPUT
~
2.02V=Vthc
RA1D-17
;~PRESS
.r
PLDC20RAIO
SEMICONDUCTOR
AC Test Loads and Waveforms (continued)
Parameter
Output Wtveform-Measurement Level
Vth
1.5V
tpxz( -)
VOH O.5V
2.6V
tpxz(+)
Vthc
Vx
tpzx(-)
Vthc
Vx
O.5V
1.5V
VOH O.5V
tER(+)
2.6V
VOL
tEA(-)
Vthc
Vx
Vthc
Vx
l I:
l I:
l I:
, I:
t:
I:
, I:
•
RA1Q-19
VOH
RA10·20
U)
VOL
RA1Q-21
C
..J
a..
Vx
RA10-22
Vx
O.5V:
RA1Q-23
VOH
O.5V:
O.5V
RA1Q-18
Vx
O.5V
tER(-)
tEA(+ )
VX
O.5V
VOL
tpzx(+)
~
l
RA10-24
VOL
RA1Q-25
(c)
Switching Waveforms
INPUTS, REGISTERED
FEEDBACK
I
-L
X I XI
X
~
tP,1
CP
tWH
ASYNCHRONOUS
RESET
ASYNCHRONOUS
SET
tWL
~
-tPD-
OUTPUTS
(HIGH ASSERTED)
j-tco-j,
X
I
I
OUTPUT ENABLE
INPUT PIN
cleR-/rtEA-I
I
\.
RA1Q-2
Preload Switching Waveforms
PIN 13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN 1
PRELOAD
CLOCK
RA10·27
4-53
-=~
"if CYPRESS
=='
SEMICONDUCIOR ================dP~L~D~C~2~OgRA~1~O~
Functional Logic Diagrani
1
.......
: .- - ·-O-~-~~:R[l~~::~"
3 ......
.
~
~~~[J~"
..~
•••
3 .....
~!D~r
,:---~'1~~A~[J~~::~r
.
4"
="1[l~r
~ ''10~r
7 ......
~~~r
55
..
.
~ ~tI~"
-
~~r
10 ..
"'''1[J~r
11 ...
o .s ..
1
•
11
12 1$
16 It
20 21 2427 28 31
32 l5 If 3t
4-54
. ::z
~i=
-
F
PLDC20RAIO
CYPRESS
SEMlCONDUCfOR
Ordering Information
Icc2
80
80
85
85
80
Package
tPJ) (os)
tsu (os)
tco (os)
15
7
15
20
20
25
30
10
10
15
15
20
20
25
30
Ordering Code
'JYpe
PLDC20RAlO-15HC
H64
PLDC20RAlO-15JC
J64
PLDCZORAlO-15PC
P13
PLDC20RAlO-15WC
W14
CG7C324-AI5HC
H64
CG7C324-AI5JC
J64
PLDC20RAlO-20HC
H64
PLDC20RAlO-20JC
J64
PLDC20RAlO-20PC
P13
PLDC20RAI0-20WC
W14
CG7C324-AZOHC
H64
CG7C324-AZOJC
J64
PLDC20RAlO-20DI
D14
PLDC20RAlO-20JI
J64
PLDC20RAlO-20PI
P13
PLDC20RA10-ZOWI
W14
PLDCZORAlO-20DMB
D14
PLDC20RAlO-20HMB
H64
PLDC20RA10-ZOLMB
PLDCZORA10-2QMB
L64
Q64
PLDC20RAlO-20WMB
W14
PLDC20RA10-25DI
D14
PLDCZORAlO-25JI
J64
PLDC20RAlO-25PI
P13
PLDCZORAI0-25WI
W14
PLDC20RA10-25DMB
D14
PLDCZORA10-25HMB
H64
PLDCZORA10-25LMB
PLDC20RAI0-25QMB
L64
Q64
PLDC20RAIO-25WMB
W14
PLDCZORA10-30HC
H64
PLDCZORA10-30JC
J64
PLDCZORA10-30PC
P13
PLDCZORA10-30WC
W14
CG7C324-A30HC
H64
CG7C324-A30JC
J64
4-55
Operatiog
Raoge
Commercial
Commercial
II)
C
...J
a.
Industrial
Military
Industrial
Military
Commercial
PLDC20RAIO
Ordering Information (continued)
IcC2
tpD
(ns)
tsu
(ns)
teo
Ordering Code
(ns)
PLDC20RA1O- 35DI
85
20
35
35
PLDCZORA10-3JI
J64
PLDC20RA10- 35PI
P13
PLDC20RA10-35WI
W14
PLDCZORA10-35DMB
D14
PLDC20RA10-35HMB
H64
PLDC20RA10-35LMB
L64
PLDC20RA1O-35QMB
Q64
PLDC20RA1O-35WMB
W14
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VIL
1,2,3
Ilx
1,2,3
Ioz
1,2,3
Icc
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
tpzx
teo
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
tsu
tH
Package
1YPe
D14
Document #: 38-00073-C
4-56
Operating Range
Industrial
Military
PALC22VIO
CYPRESS
SEMICONDUCTOR
Features
• Advanced second-generation PAL
architecture
• Lowpower
-55 mA max."Il'
- 90 mA max. standard
-120 mA max. military
Reprogrammable CMOS
PAL® Device
• Up to 22 input terms and 10 outputs
• High reliability
- Proven EPROM technology
-100% programming and functional
testing
• Windowed DIP, windowed LCe, DIP,
LCe, and PLCC available
• CMOS EPROM technology for
reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
-Individually selectable for registered or combinatorial operation
• 20, 25, 35 ns commercial and industrial
• 25, 30, 40 ns military
Functional Description
The Cypress PALC22VI0 is a CMOS second-generation programmable logic
array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new concept, the "programmable macrocell."
The PALC22VIO is available in24-pin
300-mil molded DIPs, 3OO-miJ windowed
cerDlPs, 28-lead square ceramic leadless
chip carriers, 28-lead square plastic
leaded chip carriers, and provides up to
Logic Block Diagram (PDIP/CDIP)
Vss
CP~
Pin Configuration
LCC/PLCC
Top View
__ K!!~gg
I
I
I
NC
5
6
7
8
9
4 3 2~1: 282728
25
24
ZI
\102
1103
1104
22
NC
21
1105
\106
\107
10
20
11
19
12131415161718
Vlo-2
PAL is a registered trademark of MonoJithic Memories lDc.
4-57
i)
22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the
22VIO is erased and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each output individually.
Each of the 10 potential outputs may be
specified as registered or combinatorial.
Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further
configurability is provided through arrayconfigurable output enable for each potential output This feature allows the 10
outputs to be reconfigured as inputs on
an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
II
U)
C
..J
a.
PALC22VIO
Functional Description (continued)
PALC22V10 features a variable product term architecture.
There are five pairs of product terms beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output. By providing this variable structure, the PALC22V10 is
optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance.
Additional features of the Cypress PALC22V10 include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the
need to dedicate standard product terms for initialization function. The device automatically resets on power-up.
For testing of programmed functions, a preload freature allows
any or all of the registers to be loaded with an initial value for
testing. This is accomplished by raising pin 8 to a supeIVoltage
Vpp, which puts the output drivers in a high-impedance state.
The data to be loaded is then placed on the I/O pins of the device
and is loaded into the registers on the positive edge of the clock:
on pin 1. A 0 on the I/O pin preloads the register with a 0, and a
1 preloads the register with a 1. The actual sigual on the output
pin will be the inversion of the input data. The data on the I/O
pins is then removed and pin 8 is returned to a normal TIL voltage. Again, care should be exercised to power sequence the device properly.
The PALC22V10 featuring programmable macrocells and variable product terms provides a device with the flexibility to implement logic functions in the 500 to 800 gate array complexity.
Since each of the 10 output pins may be individually configured
as inputs on a temporary or permanent basis, functions requiring
up to 21 inputs and only a single output and down to 12 inputs
and 10 outputs are possible. The 10 potential outputs are enabled
using product terms. Any output pin may be permanently se-
lected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved
through an individual programmable macrocell. These macrocells
are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is
available for establishing the next result in applications such as
control state machines. In a combinatorial configuration, the
combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility
provided by both programmable macrocell product term control
of the outputs and variable product terms allows a significant
gain in functional density through the use of a programmable
logic.
Along with this increase in functional density, the Cypress
PALC22VI0 provides lower-power operation through the use of
CMOS technology and increased testability with a register preload feature. Preload facilitates testing programmed devices by
loading initial values into the registers.
Configuration Table
Registered/Combinatorial
Configuration
Cl
Co
0
0
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
Macrocell
~----------------------,
AR
OUTPUT
>---+-----_-i D
01------1
SELECT
MUX
S1
CP
So
SP
INPUT/
FEEDBACK
MUX
S1
C1
Co
-----~----------~~~----~
~----------~~~~~-------~
4-58
V1~
-==-:
:~
PALC22VIO
_'ii!CYPRESS
_ , SEMICONDUCTOR
Selection Guide
Generic
Part Number
22VlO-20
22VI0-25
22VlO-30
22V10-35
22V10-40
55
Iccl (mA)
Com/lnd
90
90
55
90
"Il'
Mil
100
100
100
tpD (ns)
Mil
Com/lnd
20
25
25
30
35
40
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ..........•....•...... - 55° C to + 125° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (LOW) ...•••.•..•••• 16 rnA
Electrical Characteristics Over the Operating Rangel2]
Parameters
Description
Output HIGH Voltage
ts (ns)
Com/lnd
12
15
30
Operating Range
Ambient
Temperature
Range
Commercial
Industrial
Militaryll]
- 40°C to +85°C
5V±10%
- 55°C to +125°C
5V ±10%
Min.
Com'I!Ind
IOH=-2rnA
Mil
Vom
HIGH Level CMOS Output Vee-Min.,
Voltage[3]
VIN = VIH or VIL
IOH = - 100 J.IA
VOL
Output LOW Voltage
IOL-16rnA
VIH
Input HIGH Level
Input LOW Level
Vcc
5V ±1O%
O°Cto +75°C
Test Conditions
Vee = Min.,
VIN = VIH or VIL
25
UV Exposure ........................... 7258 Wsec/cm 2
DC Programming Voltage ......................... 14.0V
Latch-Up Current ........................... >200 mA
IoH= -3.2rnA
VIL
18
20
30
Vee = Min.,
VIN = VIH or VIL
VOHl
tco (ns)
Mil
Com/lnd
12
15
15
20
25
Mil
V
Veel.OV
V
Com'l/Ind
Mil
IOL-12rnA
Guaranteed Input Logical HIGH Voltage for All Inputsl4J
Guaranteed Input Logical LOW Voltage for All InputsL4J
Max. Units
2.4
0.5
V
0.8
V
2.0
V
IlX
Input Leakage Current
Vss.s. VIN.s. Vee. Vee = Max.
-10
+10
Ioz
Output Leakage Current
Vee - Max., Vss.s. VOUT.s. Vee
-40
+40
J.IA
J.IA
Ise
Output Short Circuit Current Vee - Max., VOUT = O.5Vl',']
-30
- 90
rnA
55
90
rnA
100
rnA
65
rnA
Ieel
Iccz
Standby Power Supply
Current
Vee = Max., VIN = GND Outputs Open
for Unprogrammed Device
"C'
Com'I!Ind
Mil
"£'
Operating Power Supply Cur- ftoggle = FMAXL3J
rent
rnA
Notes:
1.
2.
tA is
the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
3. Thsted initially and after any design or process changes that may affect
these parameters.
4.
5.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
Capacitance[3]
Parameters
CIN
COUT
Descriptiou
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V@f= 1 MHz
4-59
Min.
Max.
10
10
Units
pF
pF
en
C
..J
a.
=;;,~
_ . _ CYPRESS
~,
PALC22VIO
SEMIC~DUCTOR
Switching Characteristics PALC22VIO (Commercial and IndustriaI)[2. 6]
Commercial & Industrial
-20
Parameters
Description
Min.
-35
-25
Max.
Min.
Max.
Min.
Max.
Units
35
ns
25
35
ns
25
35
ns
15
25
ns
tpD
Input to Output Propagation Delay[7]
20
25
tEA
Input to Output Enable Delay
20
tER
Input to Output Disable Delay[8]
20
tco
Clock to Output Delay[9]
12
ts
Input or Feedback Set-Up Time
12
15
30
ns
tH
Input Hold Time
0
0
0
ns
tp
External Clock Period (tco
24
30
55
ns
tWH
Clock Width HIGH[3]
10
12
17
ns
tWL
Clock Width WW[3]
10
12
17
ns
+ ts)
+ tS»[10]
fMAXI
External Maximum Frequency (lI(tco
41.6
33.3
18.1
MHz
fMAX2
Data Path Maximum Frequency
(lI(twH + tWL»[3.11]
50.0
41.6
29.4
MHz
fMAX3
Internal Feedback Maximum Frequency
(lI(tcF + tS»[12]
45.4
35.7
20.8
MHz
tCF
Register Clock to Feedback Input[13]
tAW
Asynchronous Reset Width
20
25
35
ns
tAR
Asynchronous Reset Recovery Time
20
25
35
ns
10
13
25
18
25
35
ns
tAP
Asynchronous Reset to Registered Output Delay
tSPR
Synchronous Preset Recovery Time
20
25
35
ns
tpR
Power-Up Reset Timef l4 ]
1.0
1.0
1.0
flS
Notes:
6. Part (a) of AC Thst Loads and Waveforms used for all parameters except tEA. tER. tpzx, and tpxz. Part (b) of AC Thst Loads and Waveforms used for tEA, tER, tpzx, and tpxz.
7. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC Thst Loads and Waveforms for
the minimum guaranteed negative correction which may be subtracted
from tpD for cases in which fewer outputs are changing state per access
cycle.
8. This parameter is specified as the time after output disable input duringwhich the previous output data state remains stable on the output.
This delay is measured to the point at which a previous HIGH level has
fallen to O.5V below VOH min. or a previous LOW level has risen to
O.5V above VOL max. Please see part (e) of ACThst Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of ACThst Loads and Waveforms for
the minimum guaranteed negative correction that may be subtracted
from teo for cases in which fewer outputs are changing state per access
cycle.
ns
10. This specification indicates the guaranteed maximum frequency at
11.
12.
13.
14.
4-60
which a state machine configuration with external feedback can
operate.
This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
This parameter is calculated from the clock period at fMAl{ internal
(l/fMAX3) as measured (see Note 11 above) minus ts.
The registers in the PALC22VlO have been designed with the capability to reset during system power-up. Following power-up. all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. This feature is useful in establishing state
machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
=- ;~
CYPRESS
:z:
-=-.IF
PALC22VIO
SEMICONDUC'l'OR
Switching Characteristics PALC22VIO (Military)[2, 6)
Military
-30
-25
Parameters
Description
Min.
Max.
Min.
-40
Max.
Min.
Max.
Units
tpD
Input to Output Propagation Delay(6)
25
30
40
ns
tEA
Input to Output Enable Delay
25
25
40
ns
tER
Input to Output Disable Delayl7J
25
25
40
ns
tco
Clock to Output Delay(9)
15
20
25
ns
ts
Input or Feedback Set-Up TIme
18
20
30
ns
tH
Input Hold TIme
0
0
0
ns
II
II)
tp
External Clock Period (teo
tWH
Clock Width mOH(3)
+ ts)
tWL
Clock Width LOW(3)
fMAXl
External Maximum Frequency (1/(teo
fMAX2
33
40
55
ns
14
16
22
ns
14
16
22
ns
303
25.0
18.1
MHz
Data Path Maximum Frequency
(l/(tWH + tw0)[3.10)
35.7
31.2
227
MHz
fMAX3
Internal Feedback Maximum Frequency
(1/(tcF + ts))[11)
32.2
28.5
20.0
MHz
tCF
Register Clock to Feedback Input(12)
tAW
Asynchronous Reset Width
25
30
40
ns
tAR
Asynchronous Reset Recovery Time
25
30
40
ns
tAP
Asynchronous Reset to Registered Output Delay
tSPR
Synchronous Preset Recovery TIme
25
30
40
ns
tpR
Power-Up Reset TImel13)
1.0
1.0
1.0
JI.S
+ tS»19]
13
15
25
20
ns
40
30
ns
AC Test Loads and Waveforms
R1 238.0.
OUTP:~:Fi(319.o.
MIL)
OUTP:~
R2
R1 238.0.
:=F}(319.o.
MIL) R2
ALL INPUT PULSES
3.0V----
90%
j78~NG
50 pF
I-=
-=
170.0.
(236.0.
MIL)
SCOPE
j~8~~NG
I
50 pF
-=
-=
SCOPE
(a)
170.0.
(236.0.
MIL)
GND
VUH
(b)
(c)
I
Equivalent to:
OUTPUT
I
THEVENIN EQUIVALENT (Commercial)
~
V1()'5
Equivalent to:
THEVENIN EQUIVALENT (Military)
~~.n.
OUTPUT 0---'1'0'.>11.,----;0
2.08V = V1hc
V10-6
2.13V = V1hm
V1D-7
4-61
C
...J
Il.
PALC22VIO
AC Test Loads and Waveforms (continued)
Minimnm Negative Correetion to tpD and leo
vs. Nnmber or Outputs Switching
z
o
§
./
~:!! -0.2
~i1!:
o 0
~_o
~ a:
ClO
Vx
tER(-)
l.5V
/
Output Waveform-Measurement Level
VOH
O.SV
V
-0.4
y
2.6V
tER(+)
-0.6
~ ~ -0.8
::0-
~g -1.0
Z
~
Parameter
-1.
1/
1
V
/
2 3
4
5 6
7
8
Vlhc
lEAH
9 10
VOL
O.SV
Vx
O.5V
Vlhc
tEA(+)
~ ~~
Vx
NUMBER OF DEVICE. OUTPUTS
CHANGING STATE PER ACCESS CYCLE
O.SV
~
Vx
,~
V1lH1
Vx
V1Q.9
~
~
~ ~
VOH
V1D-l0
VOL
V1D-ll
Vl0·12
(e) Test Waveforms
(d)
Switching Waveform
INPUTSI/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
-.
XXX
..............
X
Is
r- ~
CP
IWL
~~
-,......-.,
- XX
- -
I--- ISPR
lAW
ASYNCHRONOUS
RESET
-
~-"
IWH.I
IH
Ip-
I - - I AR -
).
,
XX)
~
REGISTERED
OUTPUTS
lAP
I-
IpD
COMBINATORIAL
OUTPUTS
IER[7
I-
IER171 i-II
XX) ,
'"'"
//0
-
-
'/
......
'"
\;A[7]
\;A[7]
V1D-13
Power-Up Reset Waveforml13, 15]
POWER __________10%
SUPPLY VOLTAGE
~~~----------------------------------------------Voo
;.;,,;,;~
/4------- -------t
IPR
REGISTERED -------------++------------or__..,..~~~..,.or_mfor----------------ACTIVE LOW
OUTPUTS ----~N~O~T~E-15~~--t-r------------'~~~~~~~~
CLOCK
V10·14
Notes:
15. The clock signal input must be in a valid LOW state (YIN less than
O.8V) or a valid 1ll0H state (YIN greater than 2.4V) prior to occurrence of the 10% level on the monotonically rising power supply voltage as shown in Power-Up Reset Waveform. In addition, the clock in·
put signal must remain stable in that valid state as indicated until the
4-62
90% level on the power supply voltage has been reached. The clock
signal may transition LOW to 1ll0H to clock in new data or to execute
a synchronous preset after the indicated delay (tPR + Is) has been ob·
served.
PALC22VIO
Functional Logic Diagram for PALC22VIO
rC
~p~p.
0
4
8
12
16
20
24
28
AR
OE
Lr::7
!Pee- =tb
0
··
0
I--<
··
~
a-
~
~
11
OE
~
t::::
13
21
-
0
20
1T
=tb
:~ TT
=tb
IT
=tb
OE
:::'
··
::::~
15
OE
0
:::;
~
·
::::
eel
19
eel
18
cell
17
::::~
~
i:::
15
OE
0
;::
··
7
en
C
TT
eel
~
~ TT
13
OE
0
··
~tb
~
~
Macrocell
~
11
8
OE
0
TT
=b
15
00
gg
"'()()8~
-
V10B-2
PAL is a registered trademark of Monolithic Memories Inc.
4-67
-
00(.)-
:!!'z
OJ
co
gg
V10B-3
•
I II
C
..J
Q,
-
~~PRF$
-=-, SEMICCtIDI1CTOR
PALC22VIOB
Functional Description (continued)
individually selected, allowing complete flexibility of output configuration. Further configurability is provided through "array"
configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled
by the programmable array.
PALC22Vl0B features a ''variable product term" architecture.
There are 5 pairs of product terms beginning at 8 product terms
per output and incrementing by 2 to 16 product terms per output.
By providing this variable structure, the PALC22VlOB is optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22Vl0B include a synchronous preset and an asynchronous reset product term. These
product terms are common to all inacrocells, eliminating the
need to dedicate standard product terms for initialization function. The device automatically resets upon power-up.
For testing of programmed functions, a preload feature allows
any or all of the registers to be loaded with an initial value for
testing. This is accomplished by raising pin 8 to a supervoltage
Vpp , which puts the output drivers in a high-impedance state.
The data to be loaded is then placed on the I/O pins of the device
and is loaded into the registers on the positive edge of the clock
on pin 1. A 0 on the I/O pin preloads the register with a 0 and a 1
preloads the register with a 1. The actual signal on the output pin
will be the inversion of the input data. The data on the I/O pins is
then removed, and pin 8 returned to a normal TTL voltage. Care
should be exercised to power sequence the device properly.
The PALC22Vl0B featuring programmable macrocells and variable product terms provides a device with the flexibility to implement logic functions in the 500 to 800 gate array complexity.
Since each of the 10 output pins may be individually configured
as inputs on a temporary or permanent basis, functions requiring
up to 21 inputs and only a single output and down to 12 inputs
and 10 outputs are possible. The 10 potential outputs are enabled
using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an in-
put through the seiective use of individual product terms associated with each output. Each of these outputs is achieved
through an individual programmable macro cell. These macro
cells are programmable to provide a combinatorial or registered
inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is
available for establishing the next result in applications such as
control-state-machines. In a combinatorial configuration, the
combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility
provided by both programmable macrocell product term control
of the outputs and variable product terms allows a significant
gain in functional density through the use of a programmable logic.
Along with this increase in functional density, the Cypress
PALC22Vl0B provides lower-power operation through the use
of CMOS technology, increased testability with a register preload
feature, and guaranteed AC performance through the use of a
phantom array. This phantom array (Po - P3) and the "top test"
and "bottom test" features allow the 22VlOB to be programmed
with a test pattern and tested prior to shipment for full AC specifications without using any of the functionality of the device specified for the product application. In addition, this same phantom
array may be used to test the PALC22Vl0B at incoming inspection before committing the device to a specific function through
programming. Preload facilitates testing programmed devices by
loading initial values into the registers.
Configuration Table 1
Registered/Combinatorial
Configuration
Cl
Co
0
0
Registered/Active LOW
0
1
Registered/Active maR
1
0
CombinatoriaVActive LOW
1
1
CombinatoriaVActive maR
Macrocell
OE
r--------------------,
OUTPUT
r-+------4.....,D
a l - - - - t SELECT
MUX
°H--~St~S:J!.J
CP
'---,----'
SP
INPUT!
FEEDBAC
MUX
St
~ --------t-~~----------------------~
_________
______ J
~----+-------~~~~--~
~
~£~~~
4-68
V101H
~
g
:;~PRFSS
PALC22VIOB
~ F SEMICOID\.JCl'OR
Selection Guide
Generic
Part Number
22VlOB-15
22V10B-20
ICClmA
90
Mil
100
-
100
Com/lnd
tpo ns
Com/lnd
15
tsns
Com/lnd
10
Mil
15
-
-
20
Maximum Rating
(Above which the useful life may be impaired. Foruser guidelines,
not tested.)
Storage Thmperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pm 24 to Pin 12) ...................... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 16 rnA
leons
Com/lnd
10
Mil
10
-
17
Mil
10
15
UV Exposure ........................... 7258 Wsec/cm2
DC Programming Voltage ......................... 13.0V
Latch-Up Current ........................... >200 rnA
C
Ambient
Temperature
O°Cto +75°C
Vcc
5V±10%
-40°C to +85°C
5V±10%
- 55°C to +125°C
5V±1O%
Range
Commercial
Industrial
Militaryllj
Electrical Characteristics Over the Operating Rangel2]
Description
Parameters
Min.
Test Conditions
Vee = Min.,
VIN = VIH or VIL
IOH = -3.2 rnA
Com'l/Ind
IOH = -2 rnA
Mil
VOH2
HIGH Level CMOS Output Vee = Min.,
Voltagel3j
VIN = VIH or VIL
IOH = -100 IlA
VOL
Output LOW Voltage
VOHl
Output HIGH Voltage
Vee = Min.,
VIN = VIH or VIL
IOL= 16 rnA
Com'l/Ind
IOL = 12 rnA
Mil
Input HIGH Level
Guaranteed Input LogicalHIGHVoltage forAll Inputs[4]
Input WW Level
Guaranteed Input Logical WWVoltage for All Inputs[4]
IIX
Input Leakage Current
Vss~ VIN~
Vee, Vee = Max.
Vee = Max., Vss ~ VOUT ~ Vee
Ise
Output Short Circuit Current Vee = Max., VOUT = 0.5V[3,S]
Ieel
Standby Power Supply
Current
ICC2
Operating Power Supply
Current
Vee = Max., VIN = GND Outputs Com'l/Ind
Open for Unprogrammed Device
Mil
ftoggle = FMAX[3]
Com'l/Ind
Device Programmed with Worst Case Mil
Pattern, Outputs Three-Stated
NoteS!
1. tA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Thsted initially and after any design or process changes that may affect
these parameters.
4.
5.
V
Vee - 1.0V
VIL
Output Leakage Current
Max. Units
2.4
VIH
Ioz
0.5
V
0.8
V
-10
10
-40
40
!lA
!lA
-30
-90
rnA
90
rnA
2.0
V
100
rnA
90
rnA
100
rnA
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
Capacitance[3]
Parameters
CIN
CoUT
Description
Input Capacitance
Output Capacitance
1YPical
11
9
4-69
•
en
Operating Range
Max.
Units
pF
pF
...I
D..
PALC22VIOB
Switching Characteristics PALC22VIOl2.6)
Parameters
Commercial & Industrial
Military
B-15
B-15
Description
Min.
Max.
Min.
Military
B-20
Max.
Min.
Max.
Units
tpD
Input to Output Propagation Delay(7)
15
15
20
ns
tEA
Input to Output Enable Delay
15
15
20
ns
tER
Input to Output Disable Delayl8J
15
15
20
ns
t(X)
Clock to Output Delay(9)
10
10
15
ns
ts
Input or Feedback Set-Up Time
10
10
17
ns
tH
Input Hold Time
0
0
0
ns
tp
External Clock Period (tm
20
20
32
ns
tWH
Clock Width IDGH(3)
6
6
12
ns
tWL
Clock Width LOw(3)
6
6
12
ns
fMAXl
External Maximum Frequency
(l/(t(X) + ts»llO)
50.0
50
31.2
MHz
fMAX2
Data Path Maximum Frequency
(lI(tWH + twU)l3.11)
83.3
83.3
41.6
MHz
fMAX3
Internal Feedback Maximum Frequency
(l/(tCF + tS»l12)
80.0
80
33.3
MHz
+ ts)
tCF
Register Clock to Feedback Input(13)
tAW
Asynchronous Reset Width
15
15
20
tAR
Asynchronous Reset Recovery Time
10
12
20
tAP
Asynchronous Reset to Registered Output
Delay
tSPR
Synchronous Preset Recovery Time
10
20
20
ns
tpR
Power-Up ~eset Timel14]
1.0
1.0
1.0
J.IS
2.5
20
20
Notes:
6. Part (a) of AC 'lest Loads and Waveforms used for all parameters except tEA. tER. tPZl{, and tpxz. Part (b) of AC 'lest Loads and Waveforms used for tEA. tER. tpzx and tpxz.
7. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) ofAC'lest Loads and Waveforms for
the minimumguaranteednegat.ve correction which may be subtracted
from tpD for cases in which fewer outputs are changing state per access
cycle.
8. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This deJay
is measured to the point at whieh a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC '!bst Loads and Waveforms
forenable and disable test waveforms and measurement reference levels.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC 'lest Loads and Waveforms for
the minimum guaranteed negative correction which may be subtracted
from teo for cases inwhich fewer outputs are changing state per access
cycle.
13
2.5
ns
ns
ns
25
ns
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
13. This parameter is calculated from the clock period at fMAX internal
(l/fMAX3) as measured (see Note 11 above) minus ts.
14. The registers in the PALC22VIOB has been designed with the capabilityto reset during system power-up. Following power-up. all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. This feature is useful in establishingstate
machine initialization. 1b insure proper operation, the rise in V cc
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
4-70
.-:=...
~ j;CYPRFSS
_
PALC22VIOB
SEMIc:amucroR
AC Test Loads and Waveforms (Commercial)
Rl 238.0.
Rl 238.0.
OUTP:~(319.o.
MIL) R2
OUTP~~ : = F } ( 3 1 9MIL)
. o . R2
ALL INPUT PULSES
3.0V----
90%
50 pF
I
~78~~NG -=
-=
170.0.
(236.0.
~78~~NG
MIL)
SCOPE
I
50 pF
-=
-=
SCOPE
(a)
170.0.
(236.0.
GND
MIL)
V1OB-9
I
Equivalent to:
I
THEVENIN EQUIVALENT (Commercial)
!!.!!..o.
OUTPUT 0-----'1.1/\",..--0
V1OB-1D
(c)
(b)
Equivalent to:
l~E!..o.
OUTPUT O~-'V.Yh""--IO
2_08V = Vthc
C
2_13V = Vtlvn
V108-12
V10B-11
Minimum Negative Correction to tpD and teo
vs. Number of Outputs Switching
z
o
§
/
~ ~ -0_2
~~
U
-0.4
~.P
~ a:
-0_6
w 0
,/
V
C)O
::;;-
g
-1_0
/
~
Z
~
-1.2
Parameter
Vx
tER(-)
1.5V
tER(+)
2_6V
tEA(+)
Vthc
,/
~ ~ -0_8
~
/
tEA(-)
1
2 3
4
5 6
7
8
9 10
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
Vthc
Output Waveform-Measurement Level
VOH O.5V
l
VOL
O.5V
Vx
O.5V
Vx
O.5V
I:
l I:
l I:
:
I:
VX
V1DS-5
Vx
V1DS-6
VOH
Vl0S-7
VOL
Vl0B-8
(e) Test Waveforms
VI DS-13
(d)
Switching Waveform
------.no...
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS _ _ _...L.ltr , - - ,
PRESET
CP
ASYNCHRONOUS
RESET -------+-:-~---+_.IJ
REGISTERED
OUTPUTS _ _ _ _ _ _"""-'1LoV
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _-LlIUI'
V1OB-14
4-71
•
en
THEVENIN EQUIVALENT (Military)
...J
11.
PALC22VIOB
Power-Up Reset Waveform(13)
POWER
SUPPLY VOLTAGE
4V~------------------------Voo
-------=r-
-------1
.....- - - - - - tPR
REGISTERED ------++------~~:_7~~~~~ml7_-------
ACTIVE
LOW _ _ _ _ _ _-+-+-_____
OUTPUTS
"""'-~:......1I'_~~~'_;:v
CLOCK
V1OB-15
4-72
PALC22VIOB
Functional Logic Diagram for PALC22VIOB
1-rD
l~p·
4
8
12
16
20
24
28
32
36
40
AR
OE
··
0
~
...,...,,7
~
OE
0
··
~
9
2
OE
~
OE
0
4--1"
··
~
13
OE
0
··
~
5~15
OE
0
·
6----1'
Irf
15
OE
0
··
7
~
-t- 13
OE
0
··
[.-<1-
.... 11
~
8--1
OE
0
··
<1----
9
~
OE
0
··
7
~
22
U)
=tb
=tb
n
::tb
TT
=tb
TT
=tb
n
=tb
=tb
C
..J
21
1'1
cell
20
ceD
19
cell
18
cen
17
cell
16
IT
15
cell
9
1
~tb
cell
11
3
23
cell
cell
d--
0
··
=l1r
T-r
~~,
4
L.......,-
SP
.A
Vl0S-16
4-73
13
D.
PALC22V10B
1YPical DC and AC Chamcteristics
NORMAUZED STANDBY
SUPPLY CURRENT (Icc)
vs. SUPPLY VOLTAGE
1.4,----r---r--"""T--:a
Jl1.21--+---+---jlL----I
o
~
~
a:~
1.0
~
0.SI---¥O-4
1.21--'*-+-------1
1.01------3oII.,-----------l
5.0
5.5
O.S t--------if---'"""'....::---;
NORMALIZED PROPAGATION
DELAY VB. TEMPERATURE
1.3 r----,---------,
20.0
~ 1.21----1----~~1
15.0
w
':l
~
a:
o
1.1 r - - - - + - - - : r - - - I
Z 1.01----.,j
en
600
/"
/
0.0
/
a
40
Z
30
~_
20
10
en
Vee = 5.0V
TA = 25·C
I
1.0
2.0
3.0
o
4.0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
~ 50
a:
a:
~
-'-
70
g 60 ~
~
"-
a
0.0
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
PALC22VlOB. For this reason, an opaque label should be placed
over the window if the device is exposed to sunlight or fluorescent
lighting for extended periods of time. In addition, high ambient
light levels can create hole-electron pairs that may cause "blank"
check failures or ''verify errors" when programming windowed
parts. This phenomenon can be avoided by use of an opaque label
over the window during programming in high ambient light environments.
"- i'...
r--....
1.0
2.0
3.0
OUTPUT VOLTAGE M
OUTPUT VOLTAGE M
CAPACITANCE (pF)
~
"
ICC
tpD
ts
teo
(ns)
(os)
(os)
90
15
10
10
100
100
15
20
10
17
10
15
V10B-10
The recommended dose for erasure is ultraviolet light with a wavelength of 2537 Angstroms for a minimum dose (UV inte~ity
multiplied by exposure time) of 25 Wsec Icm2• For an ultraViolet
lamp with a 12 mW/cm2 power rating, the exposure would be
approximately 35 minutes. The PALC22VlOB needs to be placed
within 1 inch ofthe lamp during erasure. Permanent damage may
result if the device is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm2 is the recommended
maximum dosage.
Ordering Information
(rnA)
4.0
Ordering Code
Package
PALC22V10B-15PC,lPI
P13
PALC22V10B-15WC/WI
W14
PALC22V10B-15JC/JI
J64
PALC22V10B-15HC
H64
PALC22V10B 150MB
014
PALC22VlOB-15WMB
W14
PALC22VlOB-15HMB
H64
PALC22VlOB-15LMB
L64
PALC22V10B-15QMB
Q64
PALC22VlOB-15KMB
K73
PALC22V10B 200MB
014
PALC22VIOB-2OWMB
W14
PALC22VlOB 20HMB
H64
PALC22V10B-2OLMB
L64
PALC22VIOB-2OQMB
Q64
PALC22VIOB-2OKMB
K73
4-75
Operating Range
CommerciaIJIndustrial
Military
Military
•
:$=;1~
PALC22VIOB
~,~
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tPD
1,8,9,10,11
1,8,9,10,11
1,8,9, 10, 11
1,8,9, 10, 11
teo
ts
tH
Document #: 38-00195
4-16
PAL22VIOC
PAL22VPIOC
CYPRESS
SEMICONDUCTOR
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD
,,sns
-tsu = 3ns
=
-
(MAX
=111 MHz
• Reduced ground bounce and undershoot
• PLeC and LeC packages with additional Vcc and VSS pins for lowest
ground bounce
• Up to 22 inputs and 10 outputs Cor
more logic power
• Variable product terms
- 8 to 16 per output
Universal PAL@ Device
• 10 user-progrsmmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VP1OC)
• Synchronous PRF8E'I; asyndJronous
RESET, and PREWAD capabillty for
ftexlble design and testability
• High reliability
- Proven now fuse tecbnology
- AC and DC tested at the factory
• Security Fuse
Functional Description
The
CMn"ess
PAl22V1OC
and
PAL22VP1OC are second-generation programmable array logic devices. Using
BiCMOS process and Ti-W fuses, the
PAL22V1OC and PAL22VP10C use the
familiar sum-of-products (AND-OR) logic structure and a new concept, the programmable macrocell.
Both the PAL22V10C and PAL22VP10C
provide 12 dedicated input pins and
10 I/O pins (see Logic Block Diagram).
By selecting each I/O pin as eitherpermanent or temporary input, up to 22 inputs
can be achieved. Applications requiring
up to 21 inputs and a single output, down
to 12 inputs and 10 outputs can be realized. The output enable product term
available on each I/O allows this selection.
The PAU2V1OCand PAl22VPIOCfeature
variable product term architecture, where
8 to 16 product termsareaIlocated to each
output. This structure permits more
applications to be implemented with
Logic Block Diagram and PDIP (P)jCDIP (D) Pin Configuration
lIOs
U04
VOa
UOz
viDe-I
Pin Configurations
LCClL)
'lbpView
PLCC (1)ICLCC (y)
'lbpView
--~~~g'g
,....
I
I
I
"lis
I
I
I
5
4 3 2:1: 282728
25
8
7
8
9
10
11
24
Z!
4321"282728
1102
1103
1104
PAL22V10C 22 "lis
PAL22VP1OC 2t 1105
20
19
12131415161718
I
I
I
"lis
I
I
I
1106
1107
PAL22V10C
PA122VP10C
4-77
1$5
1105
1106
1107
- - ;;- gg
PAL iI a registered trademark of MODoIithic Memories IDe.
110 2
1103
1104
vlDc-3
II
11)
C
.....
a.
PAL22VIOC
PAL22VPIOC
~PRR§
_~ICONDUCJOR
Functional Description (continued)
Programmable Macrocell
these devices than with other PAL devices that have fIXed number
of product terms for each output.
Additional features include common synchronous preset and
asynchronous reset product terms. They eliminate the need to use
standard product termsforinitia1ization functions
Both the PAL22V1OC and PAL22VPI0C automatically reset on
power-up.In addition, the preload capability allows the output registers to be set to any desired state during testing.
A security fuse is provided on each of these two devices to prevent
copying ofthe device fuse pattern.
With the programmable macrocells and variable product term
architecture, the PAL22VIOC and PAL22VPI0C can implement
logic functions in the 700 to 800 gate array complexity, with the
inherent advantages of programmable logic.
The PAL22V1OC and PAL22VPIOC each has 10 programmable
outputmacrocells (see Macrocell figure). On the PAL22VIOCtwo
fuses(Cl and Co) canbe programmed to configure output in one of
four ways. Accordingly, each output can be registered orcombinatorial with an active HIGH or active LOW polarity. The feedback to the array is also from this output (see Figure 1). An additional fuse (C2) in the PAL22VP1OC provides for two feedback
paths (see Figure 2).
.
Programming
The PAL22V1OCand PAL22VPIOCcan beprograrnmed using the
QuickPro II programmer available from Cypress Semiconductor
and also with Data I/O, Logical Devices, STAG and other programmers. Please contact your local Cypress representative for
further information.
Macrocell
OE
r-----------------------II
I
I
I
I
I
I
AR
OUTPUT
SELECT
>--+------------~
QI------l
D
CP
MUX
Sl
So
Key:
AR
8P
OE
CP
SP
INPUT/
FEEDBACK
MUX
81
S:!
--------+I_--_--_-_--'_______M~~~~~ _ _ _ _ _ _ _ .J
v1!»4
Output Macrocell Configuration
C2 1l)
Cl
Co.
Output1YPe
0
0
0
Registered
Active LOW
0
0
1
Registered
Active HIGH
Registered
X
1
0
Combinatorial
Active LOW
lIO
Polarity
Feedback
Registered
X
1
1
Combinatorial
Active HIGH
1
0
0
Registered
Active LOW
lIO
lIO[l]
1
0
1
Registered
Active HIGH
lIO[l]
Notes: '
1. PAL2I!VPIOConly.
4-78
= Asynchronous RESET
= Synchronous PRESET
= Output Enable
= Clock Pulse
·
PAL22V10C
PAL22VP10C
~
~=
~,
CYPRESS
SEMICONDUCfOR
AR
AR
C2 [ll= 0
Cl =0
CO=O
C2[ll= 0
Cl =0
CO= 1
II
U)
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
C2 [ll=x
Cl = 1
C2[ll=x
Cl = 1
Co = 0
Co = 1
vlOcHl
v10o-7
110 FEEDBACK, COMBINATORIAL, ACTIVE-LOW OUTPUT
I{O FEEDBACK, COMBINATORIAL, ACTIVE-HIGH OUTPUT
Figure 1. PAL22VI0C and PAL22VPI0C Macrocell Configurations
AR
AR
v1 Oc-1 0
v10c-9
I{O FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
110 FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
Figure 2. Additional Macrocell Configurations for the PAL22VPIOC
4-79
C
-I
a.
PAL22VIOC
PAL22VPIOC
:::z
~=CYPRF.SS
~, SEMICONDUCTOR
Selection Guide
22VIOC-IO
22VPIOC-IO
190
190
22VIOC-12
22VPIOC-12
190
22VIOC-15
22VPIOC-15
190
190
12
12
15
IedrnA)
Commercial
22VIOC-7
22VPIOC-7
190
tPD(ns)
Military
Commercial
7.5
10
3.0
3.6
3.6
6.0
7.5
111
7.5
90
10
Military
to (ns)
tco(ns)
Commercial
Military
Commercial
fMAX(MHz)
Military
Commercial
4.5
4.5
9.5
7.5
9.5
10
71
71
57
90
Military
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65 ° C to + 150°C
Ambient Thmperaturewith
Power Applied ....................... - 55°Cto +l25°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... - O.5V to Vee
DC Input Voltage ........................ - O.5V to Vee
DC Input Current .................... - 30 rnA to + 5 rnA
(except during programming)
DC Program Voltage. . . .. . . . .. . . . . . . . . . .. . . . . . . . . .. lOV
Operating Range
Range
Commercial
Militaryl2]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±5%
- 55°Cto +125°C
5V±5%
DC Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output WW Voltage
Min.
Thst Conditions
Vee = Min.,
VIN = Vrn or VIL
lOR = - 3.2 rnA
Com'l
IOR=-2rnA
Mil
Vee = Min.,
VIN = Vrn or VIL
IOL= 16 rnA
Com'l
IOL= 12 rnA
Mil
Vrn
Input HIGH Voltage
GuaranteedInput Logical HIGH Voltage for All Inputs[3]
VIL
Input LOW Voltage
GuaranteedInput Logical LOW Voltage for All Inputs[3]
IIX
Input LeakageCurrent
Vss.:5. VIN.:5.2.7V, Vee = Max.
II
Maximum Input Current
VIN = Vee, Vee = Max.
Max.
V
2.4
0.5
2.0
- 250
Units
V
V
0.8
V
50
!JA
!JA
Com'l
100
Mil
250
Ioz
Output LeakageCurrent
Vee = Max., Vss.:5. VOUT.:5. Vee
-100
100
!JA
Ise
Output Short Circuit Current
Vee = Max., VOUT = 0.5V[4]
-30
-120
rnA
lee
Power Supply Current
Vee = Max., VIN = GND, Outputs Open
Com'l
190
rnA
Mil
190
Notes:
2. tA is the "instant on" case temperature.
3. These are absolute values witb respect to device ground. All over·
shoots due to system or tester noise are included.
4.
4-80
Not more tban one output should be tested at a time. Duration of tbe
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground
degradation.
-
PAL22VIOC
PAL22VPIOC
~~
=-iECYPRESS
,
SEMICONDUCTOR
Switching Characteristics[5]
Parameters
Description
22VIOC-7
22VPIOC-7
22VIOC-IO
22VPIOC-IO
22VIOC-12
22VPIOC-U
22VIOC-15
22VPIOC-15
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
tpD
Inputto Output Propagation Delay[6]
2
7.5
2
10
2
12
2
15
ns
tEA
Input to Output Enable Delay
2
7.5
2
10
2
12
2
15
ns
tER
Input to Output Disable Delay!7]
2
10
2
12
2
15
ns
tco
1
7.5
1
9.5
1
10
ts
2
7.5
Clock to Output Delayl6]
1
6.0
Input or Feedback Set-Up Time
3
tH
Input Hold Time
0
0
tp
ExternalOockPeriod(tco + ts)
9
11.1
tWH
Oock Width IDGH[8]
3
3
tWL
Oock Width LOW[S]
3
fMAXl
External Maximum Frequency
(lI(tco + tS»[9]
fMAX2
fMAX3
4.5
ns
7.5
ns
0
0
ns
14
17.5
ns
3
6
ns
3
3
6
ns
111
90
71
57
MHz
Data Path Maximum Frequency
(lI(tWH + tWL»[8, 10]
166
166
166
83
MHz
Internal Feedback Maximum Frequency
(1/(tcF + tS»[l1]
133
100
83
66
MHz
tCF
Register Clock to FeedbackInput[l2]
tAW
AsynchronousReset Width
tAR
tAP
3.6
4.5
6.4
7.5
7.5
ns
8.5
10
12
15
AsynchronousReset Recovery Time
5
6
7
10
AsynchronousReset to Registered
Output Delay
2
tSPR
SynchronousPreset Recovery Time
5
6
7
10
ns
tpR
Power-Up Reset Timel13]
1
1
1
1
!AS
12
2
12
2
14
2
ns
ns
20
ns
Capacitancel8]
Parameters
CIN
CoUT
Description
InputCapacitance
Output Capacitance
Max.
Units
8
pF
pF
10
Notes:
5. AC test load used for all parameters except where noted.
6. Thisspecificationis guaranteed for all device outputs changing state in
a given access cycle.
7. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
O.SvoltsbelowVOHmin. or apreviousLOW level has risen to O.5volts
above VOL max.
8. Thsted initially and after any desigu or process changes that may affect
these parameters.
9. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
10. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
12. This parameter is calculated from the clock period at !MAx internal
(fMAX3) as measured (see Note 11) minus ts.
13. The registers in the PA122VI0C/pA122VPI0C have been desigued
with the capability to reset during system power-up. Followingpowerup, all registers will be reset to alogic LOW state. The output state will
depend on the polarity of the output buffer. This feature is useful in
establishing state machine initialization. To insure proper operation,
the rise in V cc must be monotonic and the timingconstraintsdepicted
in power-up reset waveforms must be satisfied.
4-81
II)
o-I
a.
PAL22VIOC
PAL22VPIOC
J.::~
""'aiF"
- CYPRESS
SEMICONDUCTOR
AC Test Loads and Waveforms
R1 238.0,
ALL INPUT PULSES
3.0V - - - ~~-----\J
5V:FlC319.o,MILl
OUTPUT
INCLUDING
JIG AND
SCOPE
I
-=
GND
l~f.o, MIL
CL
-=
.s.3ns
l
OUTPUT
tER(-)
Vx
1.5V
tER(+)
2.6V
tEA(+)
1.5V
tEA(-)
1.5V
Parameter
THEVENIN EQUIVALENT
~
2.08V = Vthc
Commercial
THEVENIN EQUIVALENT
136.0,
OUTPUT
PID
50pF
J/K/UY
Output ~veform-Measurement Level
VOH O.5V
0-----'IIIIIr-- 2.13V = Vthm
MDitary
t ~
t I::
t ~
t ~
VOL
O.5V
Vx
O.5V
I
Equivalent to:
Package
15 pF[15]
v10c--16
v100-11
I
Equivalent to:
CL[14]
R2
Vx
O.5V
Vx
v1()c..12
Vx
v1()c.-13
VOH
v10c-14
VOL
v1Oc-15
Switching Waveform
----t"7\.
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS _ _ _-'-v
PRESET
1--1_-1
CP------.I1
ASYNCHRO~E~~
-+-:-____+-.11
______
REGISTERED
OUTPUTS _ _ _ _ _ _--'...K.-'.,.
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _....L:IL..Y
v10c-17
Power-Up Reset Waveform[13]
I~----------------------------V~
POWER __________________4_V,
~~-------------- tpR--------------~.~'
REGISTERED - - - - - - - - - - - - - - - - - - - - - - - -......... . . . , . - - - - - - - - ACTIVE LOW
OUTPUT - - - - - - - - - - - - - - - - - - - - - - - - - ' . ,
v1Oc-18
Notes:
14. CL = 5 pF for tER measurement for all packages.
15. For high-capacitive load applications (CL = 50 pF), use
PAl22V1OCF/PAl22VP10CR Call your Cypress representative for a
datasheet.
4-82
PAL22VIOC
PAL22VPIOC
~
-~PRESS
SEMICONDUCTOR
_,
Preload Waveform[16]
PIN 13 (16)
Vpp
-k
\
t OPRl
f--
\
PIN2 (3)
V1HP
VllP
V1HP
VllP
V1HP
PIN3 (4)
VllP
V1HP
PIN 6 (7)
i\
V1LP
V1HP
PINS (10)
~
V llP
Vpp
\
PIN9(11)
t OPR2
PRELOAD DATA
PINS 14-23
(17-21.23-27)
~
t OPR2
) -Vr"--
1/
"-
,/
t OPR2
~-
CLOCK PIN 1 (2)
tOPAl
t OPR2
t OPRl
.~
I
\
t OPR2
t OPRl
~-
-\"
tOPR2
t OPRl
tOPRl
t OPRl
.r--;.
7
I
OUTPUTS
DISABLED
IOPRl
PRELOAD
DATA
CLOCKED
IN
PRELOAD DATA
VILP Dr VIHP[17j
t OPRl
I\"
V1HP
V1LP
V1HP
V llP
V1HP
V1LP
REGISTE RS
PRELOAD ED.
OUTPUT
ENABLED
PRELOAD
DATA
REMOVED
v10c-19
Notes:
16. Pins 4 (5), 5 (6), 7 (9) atVu'p; Pins 10 (12) and 11 (13) at VIHP; Vee (Pin 24 (1 and 28» atVCCI>
17. Pins 2-8 (3-7, 9, 10). 10 (12), 11 (13) can be set at VIHP or VILP to insure asynchronous reset is not active.
D/K/P (J/UY> Pinouts
Forced Level on Register Pin
During Preload
Register Q Output State
After Preload
VIHP
HIGH
VII.P
LOW
Name
Description
Min.
Max.
Unit
Vpp
Programming Voltage
925
9.75
V
tDPR!
Delay for Preload
1
!-IS
tDPR2
Delay for Preload
05
Ils
VII.P
Input LOW Voltage
0
0.4
V
VIHP
Input HIGH Voltage
3
4.75
V
Vecp
V cc for Preload
4.75
5.25
V
4-83
•
11)
C
..J
Ill..
PAL22VIOC
PAL22VPIOC
£:~PRFSS
.~, SEMICONDUCTOR
Functional Logic Diagram for PAL22VIOC/PAL22VPIOC
1
(2)
-1)
0
4
B
12
16
20
24
2B
32
36
40
AR
DE
0
··
:a3:
--1'::;7
('\--
DE
0
a
·
~
··
··
t;:::
t;:::
cell
i:=l
15
I::::::l
··
'""'"
··
~
11
DE
0
9
(1.....-
DE
0
··
-
7
10
11
(13)
cell
16
(19)
IT
~:b
cell
'--J
9
(12)
17
(20)
~
··
(11)
cell
~
13
DE
0
'"
8 --I
18
(21)
0
(10)
19
(23)
~
DE
7
cell
~
··
(9)
20
(24)
=[b
~~
IT
=[b
:Jrr- 11
=[b
8fF'l" TT
=[b
t;r--,..
15
6
cell
21
(25)
~
DE
0
(7)
~±r
~ TT
13
··
(6)
'-r-r-
cell
~t---.
DE
0
5
22
(26)
~ IT
DE
0
4
~:b
~±r
~t---.
11
3
(4)
(5)
c::1--
DE
0
(3)
23
(27)
cell
cell
S
9
2
::-:b
-tr
~
'rr
=:b
cell
4-84
14
(17)
'--T-
....-1
D/KIP (JILfY) Pinouts
15
(18)
v1()c..20
13
(16)
PAL22V10C
PAL22VP10C
=7~~
=-iECYPRESS
~F SEMICONDUCTOR
'fYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
1.6
V
.."..-
~
~
Cl
UJ
N
~
1.2
1.4
0
0.8
NORMALIZED PROPAGATION
DELAYvs. SUPPLY VOLTAGE
NORMAUZED SUPPLY CURRENTvs.
AMBIENT TEMPERATURE
VS.
1.4
~
;:;
1.2
-
::;
«
::.
a: 1.0
0
z
~
1.1
1\
"'-I'-....
UJ
N
::; 1.0
«
::.
a:
0
z 0.9
0.8
TA = 25°C
0.6
4.0
I
0.6
-55
SUPPLY VOLTAGE M
25
125
AMBIENT TEMPERATURE (OC)
NORMALIZED PROPAGATION
DELAYvs. TEMPERATURE
TYPICAL CORRECTION TO tpD
AND teo vs. NUMBER OF
OUTPUTS SWITCHING
4.5
5.0
5.5
6.0
z
1.2 , - - - - - . . , - - - - - . , o
o
J/Kll.IY
i=
PACKAGES
l:d W-o.2
~ 1.1~---~-----~
Cl
~
1.0
f------:~==-----~
0.9
~---_t_-----~
~ 0 -0.6
~~
fL--I
OUTPUT SINK CURRENT
vo. OUTPUT VOLTAGE
«' 120
/
.s 105
~
fl"i
/
90
75
::J
4.01----+----i1:o/"---I---I
~ 60
z
CiS
I-
2.0 i---joo"'----if-:::;.,...9---j
25
50
75
CAPACITANCE (pF)
100
::J
~
o
45
/
I
15
/
0.0
~
70
-
60
~
50
!z
a:
"
l<:
Z
30
~
20
~
10
CiS
Vcc=5.0V
TA=25°C
_
I
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
~
o
"
"'"
G 40
/
30
o
OUTPUT SOURCE CURRENT
vo.VOLTAGE
~
\
o
0.0
1.0
2.0
3.0
\
4.0
OUTPUT VOLTAGE M
M
v10c-22
Ordering Information
tM
fMAX
Icc
(rnA)
190
(ns)
7.5
(MHz)
10
90
12
15
111
71
57
Ordering Code
PAL22VIOC-7DC
PAL22VlOC-7JC
PAL22VIOC-7PC
PAL22VIOC-7YC
PAL22V1OC-1ODC
PAL22VI0C-lOJC
PAL22VIOC 10PC
PAL22V1OC-1OYC
PAL22VIOCM -1ODMB
PAL22VIOCM-1OKMB
PAL22V1OCM 10LMB
PAL22V1OCM -1OYMB
PAL22VI0C-12DC
PAL22VI0C-12JC
PAL22VIOC 12PC
PAL22V1OC-12YC
PAL22VI0CM -12DMB
PAL22V1OCM -12KMB
PAL22V1OCM 12LMB
PAL22VIOCM 12YMB
PAL22VI0CM -15DMB
PAL22VIOCM -15KMB
PAL22VIOCM -15LMB
PAL22V1OCM 15YMB
4-86
Package
'JYpe
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
PAL22VIOC
PAL22VPIOC
£;~
~=CYPRESS
~, SEMICCtIDUCTOR
Ordering Information (continued)
ICC
(rnA)
190
tAA
(ns)
7.5
fMAX
(MHz)
Ordering Code
111
10
90
PAL22VPlOC-7DC
PAL22VPlOC-7JC
PAL22VPlOC-7PC
PAL22VPlOC 7YC
PAL22VPlOC-lODC
PAL22VPlOC-lOJC
PAL22VPIOC-lOPC
PAL22VPI0C lOYC
PAL22VPI0CM -lODMB
PAL22VPI0CM -lOKMB
PAL22VPI0CM-1OLMB
PAL22VPI0CM 10YMB
PAL22VP1OC-12DC
PAL22VP1OC-I2JC
PAL22VPI0C-12PC
PAL22VP1OC-12YC
PAL22VP1OCM 12DMB
PAL22VP1OCM -12KMB
PAL22VPI0CM -12LMB
PAL22VPI0CM -12YMB
PAL22VP1OCM 15DMB
PAL22VP1 OCM -15KMB
PAL22VP1OCM -15LMB
PAL22VP1OCM -15YMB
12
15
71
57
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameters
Subgroups
VOH
VOL
Vrn
VIL
IJX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
Icc
Switching Characteristics
Parameters
Subgroups
tpD
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
teo
ts
tH
Document#: 38-A-00020-C
4-87
Package
Type
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64
Operating
Range
Commercial
Commercial
Military
rn
C
..J
Q.
Commercial
Military
Military
PRELIMINARY
PALC22VIOD
CYPRESS
SEMICONDUCTOR
Flash Erasable,
Reprogrammable CMOS PAL® Device
-10 ns commercial
7nstco
5ns ts
10 nstpD
l00-MHz state machine
-12 ns military and industrial
10 ns tco
5ns ts
12 ns tpD
83-MHz state machine
- A 15-ns commercial and military
version is available, fully consistent
with Cypress PALC22VI0B-15
AD/DC specifications
- A 25-ns commercial and military
version is available, fully consistent
with Cypress PALC22VI0-25 AC
and DC specifications
Features
• Advanced second-generation PAL architecture
• Lowpower
- 90 rnA max_ standard
-120 rnA max. military
• CMOS Flash EPROM technology for
electrical erasability and reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
• High reliability
- Proven Flash EPROM technology
-100% programming and functional
testing
Functional Description
The Cypress PAL C 22VlOD is a CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and a
new concept, the "Programmable Macrocell."
The PAL C 22VlOD is executed in a24-pin
300-mil molded DIP, a 300-mil cerDIp, a
28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10
outputs. The 22VlOD can be electrically
Logic Block Diagram (PDIP/CDIP)
"ss
CPA
1/0 9
1/0 8
1/°7
1/°6
I/O:!
1/°0
1/°5
1/°2
1/°1
1/0 0
Vec
V10D-1
Pin Configuration
LCC
PLCC
Top View
Top View
- - ~~ ~gg
-_&~ygg
I
NC
I
4 3 2~1: 282726
25
20
7
23
8
22
9
21
10
20
11
19
12131415161718
"-
-
-
ClJO- Oleo
1f}z
1/°2
1/°3
I
NC
I
liDo
N/C
1/0 5
1/0 6
1/0 7
V100-2
gg
5
6
7
8
9
10
11
4 3 2~1: 282726
25
20
23
22
21
20
19
12131415161718
- - 000-
-!!'z
PAL is a registered trademark of Monolithic Memories Inc.
4-88
0)
co
gg
1/°2
1/°3
1100
N/C
1/05
1/0 6
1/°7
V10D-3
PRELIMINARY
Functional Description (continued)
erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as
"registered" or "combinatorial." Polarity of each output may also
be individually selected, allowing complete flexibility of output
configuration. Further configurability is provided through "array"
configurable "output enable" for each potential outpuL This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, oraltemately used as a combination I/O controlled
by the programmable array.
PAL C 22VI0D features a ''variable product term" architecture.
There are 5 pairs of product terms beginning at 8 product terms
per output and incrementing by2 to 16 product terms per OUtpuL
By providing this variable structure, the PAL C 22VI0D is optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PAL C 22VI0D include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the
need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up.
The PAL C 22VI0D featuring programmable macrocells and
variable product terms provides a device with the flexibility to implement logic functions in the 500- to 8OO-gate-array complexity.
Since each of the 10 output pins may be individually configured
as inputs on a temporal)' or permanent basis, functions requiring
up to 21 inputs and only a single output and down to 12 inputs
and 10 outputs are possible. The 10 potential outputs are enabled
PALC22V10D
using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each outpuL Each of these outputs is achieved
through an individual programmable macrocell. These macrocells
are programmable to provide a combinatorial or registered inverting or non-inverting outpuL In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is
available for establishing the next result in applications such as
control state machines. In a combinatorial configuration, the
combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility
provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic.
Along with this increase in functional density, the Cypress PAL C
22VI0D provides lower-power operation through the use of
CMOS technology, and increased testability with F1ash reprogrammability.
Configuration Table 1
Registered/Combinatorial
Cl
C.
Configuration
0
0
1
1
0
1
0
1
Registered/Active LOW
Registered/Active mOR
Combinatorial/Active LOW
Combinatorial/Active mOR
Macrocell
~----------------------~
AR
OUTPUT
>--+----....--10
01------1
I
I
I
I
SELECT
MUX
CP
SP
INPUTI
FEEDBACK
MUX
I
I
I
~---~------~~~~---~
MACROCELL
I
~----------------------~
C1
4-89
Y1OD-4
II)
C
....I
Q.
g;~PRE§
PRELIMINARY
~, SEMICONDUCTOR
PALC22VIOD
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
StorageThmperature ................. - 6S0Cto +1S0°C
Ambient Temperaturewith
PowerAppIied ....................... - SSOCto +125°C
Latch-UpCurrent ............................
>200rnA
Operating Range
SU'pply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . - O.SV to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.SVto +7.0V
DCInputVoltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (Low) ................ 16 rnA
DC Programming Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. 12.SV
Ambient
Thmperature
Range
Commercial
Militaryl!]
- SSoC to + 12SoC
SV±1O%
Industrial
- 40°C to +8SoC
SV±IO%
Vee
SV±S%
O°Cto +7SoC
Electrical Characteristics
Over the Operating Rangel2]
Description
Parameters
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Thst Conditions
Vee = Min.,
VIN = Vrn or VIL
Vcc = Min.,
VIN = Vrn or VIL
Min.
IOH = - 3.2 rnA
Com'VInd
IOH=-2mA
Mil
IOL= 16 rnA
Com'VInd
IOL= 12 rnA
Mil
Vrn
Input HIGH Level
GuaranteedInput Logical HIGH Voltage for All Inputs(3]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs(3]
IJX
Input LeakageCurrent
Vss.:5. VIN.:5. Vcc, Vee = Max.
Ioz
Output LeakageCurrent
Vcc = Max., Vss.:5. VOUT .:5. Vee
Ise
Output Short Circuit Current Vcc = Max., VOUT = 0.SV[4, 5]
Icc!
Standby Power Supply
Current
Max. Units
2.4
V
O.S
V
2.0
V
0.8
V
-10
10
-40
40
fAA
fAA
-30
- 90
rnA
90
rnA
120
rnA
Vcc = Max., VIN = GND Outputs Open Com'VInd
in Unprogrammed Device
Mil
Capacitance [5]
Parameters
CIN
CoUT
Notes:
Description
InputCapacitance
Output Capacitance
Thst Conditions
VIN = 2.0V@f= 1 MHz
VOUT= 2.0V@f= 1 MHz
1. TA is the "instant on" case temperature.
2.
3.
4.
See the last page of this specification for Group A subgroup testing in·
formation.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
5.
4-90
Min.
Max.
10
10
Units
pF
pF
Not more thao one output should be tested at a time. Duration of the short
circuit should not be more than one second VOUT = 05V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
·il~DUcroR
PRELIMINARY
PALC22VIOD
Switching Characteristics PALC22VIOD[2, 6]
Military & Industrial
Commercial
-10
Parameters
tpD
tEA
tER
teo
ts
tH
tp
tWH
tWL
fMAXl
fMAX2
fMAX3
tCF
tAW
tAR
tAP
tSPR
tpR
-15
Description
Input to Output
PropagationDelayl7J
Input to Output
Enable Delay
Input to Output
Disable Delay[8J
Min. Max. Min.
10
Clock to Output
Delay[7J
Input or Feedback
Set-UpTime
Input Hold Time
External Clock
Period (teo + ts)
CiockWidthHIGHL5J
Clock Width LOWL5J
External Maximum
Frequency
(1/(tco + tS»[9J
Data Path Maximum
Frequency
(1/(tWH + twd)[5, 10J
Internal Feedback
Maximum Fre!l.uency
(1/(tcF + tS»[5, 11J
Register Clock to
Feedback Inputl12J
Asynchronous
Reset Width
AsynchronousReset
Recovery Time
Asynchronous Reset
to Registered Output
Delay
Synchronous Preset
Recovery Time
Power-Up
Reset Timef5, 13J
-25
-12
Max. Min. Max. Min.
-15
-25
Max. Min. Max. Min. Max. Units
12
15
25
ns
15
25
10
15
25
12
15
25
ns
10
15
25
12
15
25
ns
7
10
15
10
10
15
ns
5
10
15
5
10
18
ns
0
11.1
0
20
0
30
0
15
0
20
0
33
ns
ns
3
3
90
6
6
50
12
12
33.3
4
4
66.6
6
6
50
14
14
30.3
ns
ns
MHz
142
83.3
41.6
125
83.3
35.7
MHz
100
80
35.7
83
80
32.2
MHz
5
13
2.5
7
13
2.5
ns
10
15
25
12
15
25
ns
6
10
25
8
12
25
ns
12
20
25
15
20
25
ns
6
10
25
8
20
25
ns
1.0
1.0
1.0
1.0
1.0
1.0
f.ls
Notes:
6. Part (a) ofACThst Loads and Waveforms is used for all parameters except tER, tpzx, and tpxz. Part (b) of AC Thst Loads and Waveforms is
used for tER, Ipzx and tpxz.
7. Thisspecification is guaranteed for all device outputs changing state in
a given access cycle.
8. This parameter is measured as the time after output disable input that
the previous output data state remaius stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOHmin. or a previous LOWlevel has risen to O.5volts
above VOL max. Please see part (d) of AC Thst Loads and Waveforms
for enable and disable test waveforms and measurement reference levels. The test load of part (b) of AC Thst Loads and w..veforms is used
for measuring tER only.
9. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
10. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
12. This parameter is calculated from the clock period at iMAx internal
(lIfMAX3) as measured (see Note 11 above) minus Is.
13. The registers in the PALC22V10D have been desigued with the capability to reset during system power-up. Followingpower-up, all registers will be reset to a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
statemachineinitialization.1b insure proper operation, the rise in V CC
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
4-91
•
~
• .I1L~D\JcroR
PRELIMINARY
PALC22VIOD
AC Test Loads and Waveforms
R1 238.fl
R1 238.fl
OUTP~~:F1(319.fl
MIL) R2
OUTP~~ : F 1 ( 3 1 9MIL). f l R2
~78~~~NG
I-=
CL
-=
1~gf.fl
~78~~~NG
MIL)
SCOPE
1
90%
5 pF
-=
-=
SCOPE
OUTPUT
1~gfn
GND
MIL)
Vl00-5
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.0V---
~
Equivalent to:
2.08V= V1hc
OUTPUT
THEVENIN EQUIVALENT (Military)
136a
o--------wv---o
2.13V = V1hm
VI 00·7
CL
Load Speed
lOns
SOpF
Package
PDIp, eDIp,
PLee,Lee
VI 00.,;
(e)
I
THEVENIN EQUIVALENt (Commercial)
VI 00-8
Parameter
Vx
tER( )
l.SV
tER(+)
2.6V
tEA(+)
Vthc
tEA(-)
Vthc
Output Wilveform-Measurement Level
VOH O.5V
VOL
Vx
Vx
:
O.5V:
O.SV:
O.5V
:
~
~
I::
~
Vx
VI 00-9
Vx
Vl0D-l0
VOH
V10D-11
VOL
Vl00-12
(d) lest Waveforms
Switching Waveform
R~~Mf~Fl'tPD
---""'t". .
FEEDBACK
SYNCHRONOUS ----'-~
PRESET
~~~~
CP
ASYNCHRONOUS
RESET _ _ _ _ _ _-4~----+_JI
REGISTERED
OUTPUTS _ _ _ _ _ _ _......~
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _....I..Jl.¥
Vl0D-13
Power-Up Reset Waveform[13]
~~~----------------------------Vcc
POWER
SUPPLY VOLTAGE
10%
-------...::tIr
90%
~------------- tpA------------~~
REGISTERED -------+-f-------~"'7'f::....,.~"'""'7'O:~~"'7'f::t_7--------
ACTIVE LOW
OUTPUTS -------+-f-------~~~~w-~~'-~
CLOCK
tPRMAX=1f.1S
4-92
Vl0D-14
~.
~~PRESS
=os"
PRELIMINARY
PALC22VIOD
SEMICONDUCTOR
Functional Logic Diagram for PALC22VIOD
1
ri'
P1 P3
P P
0
4
8
12
16
20
24
28
32
36
40
AR
OE
··
....f'::7
0
~
::~
<1---
~th
...........
~
~
OE
0
e-...
··
cell
9
2
OE
!=
0
··
~~
..... 11
OE
0
Macro-
cell
~
13
OE
0
··
15
OE
0
··
6----1"
E
15
OE
0
··
7
23
22
tn
C
21
20
TT
=tb
ff IT
=tb
~ IT
=tb
TT
=tb,
=th,
~
cell
19
cell
18
cell
17
cell
6
~
13
OE
0
··
8---1":::
==
;:;f-'"
~:.-<1,:::..,rO'I
11
OE
1=\
0
··
=
9
9
0
·
=8=1
SP
TT
cell
~
OE
7
~
.,..,...
~~
Macrc-
6--
cell
14
13
V10D 15
4-93
5
L..-..,-
.A
1
II
..J
TT
~tb
g
··
5----1'
=tb
cell
3--1
4
cell
a.
~~CYPRESS
~, SEMICONDUC!DR
Ordering Information
tpD
ts
Icc
PRELIMINARY
teo
(rnA)
(ns)
(ns)
(ns)
90
10
5
7
120
10
5
7
90
120
90
120
15
10
15
10
25
15
25
15
10
10
15
15
Ordering Code
PALC22VI0D-lOJC
Subgroups
VOH
VOL
V]H
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VIL
IIX
Ioz
Icc
P13
PALC22VI0D-12DMB
D14
PALC22VlOD-12JI
J64
PALC22VlOD-12KMB
K73
PALC22VI0D-12LMB
L64
PALC22VlOD-12PI
P13
PALC22VlOD-15JC
J64
PALC22VI0D-15PC
P13
PALC22VI0D-15DMB
D14
PALC22VlOD-15JI
164
PALC22VlOD-15KMB
K73
PALC22VI0D-15LMB
L64
PALC22VI0D-15PI
P13
PALC22VI0D-25JC
J64
PALC22VI0D-25PC
P13
PALC22VlOD-25DMB
D14
PALC22VlOD - 25JI
J64
PALC22VI0D-25KMB
K73
PALC22VIOD-25LMB
L64
PALC22VI0D-25PI
P13
Switching Characteristics
Parameters
Subgroups
tpD
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
teo
ts
tH
J64
PALC22VlOD -lOPC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Package
Document #: 38-00185-B
4-94
PALC22VIOD
Operating Range
Commercial
Military/lndustrial
Commercial
Military/lndustrial
Commercial
Military/lndustrial
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Timing Control Unit, Clock Generator for CY7C60lA and CY7C61lA
SPARC processors
• Supports 25-, 33-, 4O-MHz operation
• Simplifies interface to slow memory
and peripberals by eliminating the
need for wait-state logic
• Flexible clock extension arcbitecture
- O-cycle to 14-cycle extensions
- user controlled (continuous cycle)
extension
• 24-pin 300-mil DIP and 28-pin PLCC
packages
Overview
Like most RISC processors, a fast-running 7C601/611 SPARC Integer Unit (IU)
must spend time waiting for slower
memory or peripberal devices. Because
the 7C601/611 completes an instruction
and generates a new address every clock,
a complicated handshake protocol and a
correspondingly complicated state machine must be used to keep the ill from
getting abead of the slow devices.
HIWffi
relies primarily on thMWs
This
nals
(Memory ~6U1
(Memory Data Strobe).
is as-
CY7C325
Timing Control Unit
serted by the memory system,to freeze the
processor when data is unavailable. MI5S"
is used to strobe in the data when it becomes available. The timing relationships
between these signals and other processor-generated signals must be accounted
for by the state machine handling the
handshaking.
The purpose of the 7C325 Timing Control Unit (TCU) is to simplify the wait
state logic by controlling (stretching) the
clock sent to the IU. If the IU accesses a
device for which it must wait, the LOW
portion of the clock sent to the IU is extended-i.e., held low-until the device is
ready. Once the clock signal is subequentIy released, the IU can continue. Because
the IU effectively encounters only one
clock cycle per access, the need for the
complicated handshake state machine is
eliminated. The single chip TCU is especially useful in embedded control applications where low chip count is highly desirable.
Functional Description
The number of stretched cycles in the
7C325 TCU is controlled by a four-bit
binary count input: an input of 0001 will
stretch the clock for one cycle (keep it
LOW one extra cycle), an input of 0010
will stretch the clock for two cycles, and
so on up to an input of 1110 to stretch the
clock for fourteen cycles. A count input of
1111 will stretch the clock continuously
until an roJY (ready) signal is asserted.
An input of 0000 is the no stretch condition.
These counts are derived from the processor addresses. Because the input count is
four bits wide, the address space can be
divided into as many as sixteen subspaces,
and devices that require the same number
of wait cycles can be grouped into the
same subspace.
For example, if all devices that require
eight wait cycles are memory mapped to
hex address 3xxxxxxx, then whenever the
four most significant address bits are
equal to 0011, a code converter will generate a count of 1000 to the CY7C325.
This code converter can be easily implemented with a PAL or PLD. In addition, the
user does not need to create the full sixteen subspaces. If only 0, 2, 4, and continuous wait cycles are needed, the user may
create just four subspaces and, consequently, employ just two address bits to
generate the TeU input count. It should
also be noted that the subspaces can be of
different sizes.
Logic Block Diagram
XO
X1
X2
X3
RDL
WRTL
COUNT AND
CONTROL
INTERFACE
LOGIC
WAIT STATE
ENCODING
LOGIC
mN
INULL
FNULL
m:SET
DE-SKEW
CONTROL
OSC
SCLOCK1
SCLOCK2
OSC
CLOCK STRETCHING
LOGIC AND BUFFERS
FCLOCK
NOTFCLOCK
C325-1
4-95
•
I I)
C
....I
a..
~PRESS
~nEMICONDUcroR
Functional Description
PRELIMINARY
CY7C325
Power and Ground
(continued)
The code converter described above is preferred but not required.
Users who wish to reduce cost or board space can eliminate the
code converter by feeding the IU's address bits directly to the TCU
and memory mapping the devices by their counts (e.g., memory
map devices requiring eight wait cycles to hex address 8xxxxxxx).
The code converter can also be eliminated by programming the
number of wait cycles for each address into the IU's ASI bits.
The count inputs are sampled on the falling edge of the stretched
clock, SCLOCK, which is used as the system clock by the IU and
peripherals. It is one of the three clock signals provided by the
7C325. The other two are FCLOCK and NOTFCLOCK. If the
count input is notOOOO when it is sampled, the stretched clock output will stay LOW for the specified number of cycles.
ThetwoSCLOCKoutputscan be buffered to increase their driving
capability. However, the same buffer delay must be added to the
FCLOCK output path and the NOTFCLOCK output-skew control feedback path to eliminate skew. There are several other signals that affect the stretching operation as well. RD is an output
from the IU that indicates whether an access is a read (RD = 1) or
a write (RD = 0). WRT, anotherIU output, is asserted only on the
first cycle of a write. RD is needed because a read access (load) is
treated differently from a write access (store). A minimum write
accessconsists of two clock cycles. The first clock is used by the processorto reverse the data bus and by external logic to perform tasks
such as access protection checking, address translation, and cache
tag comparison. The second cycle is when the write is actuallyexecuted. Thus, the first cycle of a write is never stretched. Because
WRf is active only during the first cycle of a write, it is used by the
TCU to differentiate between the two cycles.
INULL and FNULL are signals asserted by the Integer Uuit and
FIoatingPoint Unit, respectively, to nullify the current access. Assertion of either signal during the first cycle of a load or store will
terminate an access. However, because INULLis always asserted
in the second cycle of a store (to prevent assertion ofMHOLD for
the remainder of the write), it is ignored by the 7C325 once a write
stretch has started.
VCC: power, connected to the +5V power supply.
GND: ground.
Inputs
CLK: clock input to TCU's internal logic.
OSC: input from the oscillator.
XO - X3: count inputs, derived from CPU address; equal to the
number of cycles the clock will be stretched. These inputs are
sampled by the falling edge of the SCLOCK.
X{3 •• 0}
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Number of Cycles SCWCK will be Stretched
zero - no stretch
one
two
three
four
five
six
seven
eight
nine
ten
eleven
twelve
thirteen
fourteen
countinuous until RDY
Pin Description
The following sections contain brief descriptions of the pin functions.
P~n
Configurations
DIP
Top View
PLCC
Top View
Vee
XO
Xl
X2
X3
RESET
RDL
INULL
GNO
NOTFClDCK
FClDCK
SClDCKl
SClDCK2
NC
NC
NC
NC
NC
NC
FNULL
C325·2
Xl
SClDCKl
X2
X3
GNO
RESET
ROY
SClDCK2
NC
GND
NC
NC
WRTL
NC
C325-3
4-96
.
:~
PRELIMINARY
==-==P iii CYPRESS
.F SEMICONDUCTOR
Pin Description (continued)
RESET. reset; restores the TCU to a known state; sampled by the
falling edge ofFCLOCK.
RDY: ready, from peripheral device; this input is sampled by the
fallingedgeofFCLOCK. Ifthis input is sampled WWthe TCUwill
terminatea continuous stretch. (a watchdog timer time - out signal
can be ORed into this input as well)
WRfL: earlywrite; this is the latched version of the processorsignal
WRf. It is sampled by the TCU at the falling edge of SCLOCK.
RDL: readlwrite; this is the latched version of the processor signal
RD. It is sampled by the TCU at the falling edge of SCWCK. (1 =
read, 0 = write)
CY7C325
FNULL: floating point nullify from the FPU. It is asserted by the
FPU to nUllify its current access. IfFNULL is HIGH the TCU will
end the current stretch.
Outputs
FCLOCK: non-stretched clock signal.
NOTFCLOCK:invertedFCWCK - fedbacktotheTCU CLKinput to eliminate skew.
SCLOCK1: system clock.
SCWCK2: system clock. (repeated to provide extra load driving
capability)
(I)
...J
a..
Selection Guide
7C325-40
7C325-33
Frequency (MHz)
40
33
25
Iec(rnA)
190
190
90
7C325-25
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ........................ - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ..................... - O.5V to + Vee Max.
DC Input Voltage ....................... - 0.5Vto +5.5V
DC Input Current ..................... - 30 rnA to +5 rnA
Static Discharge Voltage. . .. . . . . .. . . . .. . . . . . . . . . . >2001V
(per MII..-STD-883, Method 3015)
Operating Range
Range
Commercial
Ambient
Thmperature
Vee
5V±5%
O°Cto +70°C
Electrical Characteristics Over the Operating Range
7C325-40,33
Parameters
Description
VOH
Output mGH Voltage
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
V/L
Input LOW Voltage
IIX
Input LeakageCurrent
Ioz
Output Leakage Current
Ise
Icc
Power Supply Current
Output Short Circuit Current
Thst Conditions
Vee = Min., VIN = Vrn or VII.,
IOH = -3.2rnA
Vee = Min., VIN = Vrn or VJL,
IOL= 16 rnA
Guaranteed Input L0rtcal HIGH
Voltage for Aliinputs 1]
Min.
Max.
2.4
7C325-25
Min.
Max.
2.4
2.0
2.0
V
V
0.8
V
Vss.$. VIN.$. Vee, Vee = Max.
-250
+50
-10
+10
Vss.$. VOUT.$. Vee, Vee = Max.
Vee = Max., VOUT = 0.5V[2]
-100
+100
-40
+40
!lA
!lA
-30
-90
-30
-90
Vee = Max., VIN = GND,
Outputs Open
2.
4-97
0.8
Units
V
0.5
0.5
Guaranteed Input L0rtcal WW
Voltage for Aliinputs 1]
Notes
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
•
C
INULL: integernullify from the processor. It is asserted by the IU
to nullify its current access. If INULL is HIGH the TCU will end
the current stretch.
190
90
rnA
rnA
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
~~PRFSS
~
PRELIMINARY
CY7C325
SEMICONDUCTOR
Capacitance
Max.
Units
CIN
Parameters
InputCapacitance
Description
10
pF
CoUT
Output Capacitance
10
pF
AC Test Loads and Waveforms
2380
ALL INPUT PULSES
2380
OUTP~~ ~ OUTP~~ ~
'n~~,:F1
'n,.~,:F1
J 1
_ 1700
J 1
_1700
INCLUDING
JIG AND
SCOPE
-
INCWDING
JIG AND
SCOPE
-
(b)
(a)
Speed
40 MHz
33 MHz
25 MHz
-
3.0V---90%
GND
-
figlab-4
figlab-S
Package
CL
15pF
DC,PC
50pF
JC
15pF
DC,PC
50pF
JC
50pF
DC,PC,JC
THEVENIN EQUIVALENT
Equivalent to:
~
OUTPUT
2.0BV = VTHC
Switching Characteristics Over the Operating Range
7C325-40
Parameters
toc
tss
tSF
tH
tSKW
tCYC
tascH
tascL
Description
Min.
OSC to FCWCK, NOTFCWCK, and
SCWCKs delay[3]
Max.
7C325-33
Min.
7C325-25
Min.
12
8
Set-Up TlDle to SCWCK Falling Edge
Max.
Max.
Units
15
ns
ns
10
10
2
Set-Up TlDle to FCLOCK Falling Edge
Hold Time
Skew Between Any Two Clock Outputs[4]
4
4
5.5
5.5
2
2
Cyc1eTime
25
30
40
ns
ns
.45 tCYC
.45 !eYc
.45tCYC
.45tCYC
.45tCYC
.45tCYC
ns
ns
OscillatorillGHTime
OscillatorWWTime
1
1
ns
ns
1
Notes
3. This specification is guaranteed for all device outputs changing state in
a given cycle.
4. The capacitive loading at each clock output is with 10% of the other
clock outputs.
4-98
4:~
•
,
~
PRELIMINARY
CYPRESS
SEMICONDUCTOR
CY7C325
Switching Waveforms
OSC
FCLOCK
SCLOCK
NOTFCLOCK
XO-X3
WRTL, RDL
RESET, ROY,
INULL, FNULL
1ooI1.f---- CLOCK STRETCHED FOR 6 CYCLES
Read
.-.jl
_ _ _ _ _..
FCLOCK
SCLOCK
X3 - XO
ROL
______
X&7 '87 'XXXXXXXXXXXXXXXXXXXXXXXXX/ 'XXXXXXXXX
~XXXXXXXXXXXXXXXXXXXXXXXxX..:::OOOO:::::..
INULL
(not shown - RESET, ROY, WRTL, OSC, NOTFCLOCK, FNULL)
Read - Continuous Stretch
""1_-----FCLOCK
SCLOCK
~-~
ROL
ROY
INULL
~~
1
CLOCK STRETCHED CONTINUOUSLY UNTIL ROY - - - - - - - . ....
__________________________________________
~~
~XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXxec:
X&7
,~~
'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX/
,
'-../
______________________________________________________
(not shown - RESET, WRTL, OSC, NOTFCLOCK, FNULL)
4-99
PRELIMINARY
CY7C325
Switching Waveforms (continued)
I-- NO STRETCH ..I
Write[5j
FCLOCK
SCLOCK
X3-XO
.....,:OOOO='_ _ _J
_-JXXXXXXXXXXXXXXXXXXXXXX'-_oooo=___
"....;:.:OI:.:OI.......
/XXXXXXXXXXXXXXXXXXXX,
ROL
WRTL
INULL
------~~~------~/
Read Thrminated by INULL
FCLOCK
SCLOCK
X3-XO
0011
0011
0011
ROL
INULL
INUIL on first cycle
ends stretch after frrst
stretched cycle
(not shown - RESET, WRTL, ROY, OSC, NOTFCLOCK, FNULL)
Write Thrminated by INULL
FCLOCK
SCLOCK
X3 -XO
ROL
WRTL
INULL
' _---....
(not shown - RESET, OSC, ROY, NOTFCLOCK, FNULL)
- - - - + - I N U L L on second cycle of a store is ignored
by TCU and does not end a stretch
[NULL on first cycle of a store
ends stretch immediately
(not shown - RESET, OSC, ROY, NOTFCLOCK, FNULL)
Note:
5. The first cycle of a write is not stretched.
4-100
/
PRELIMINARY
CY7C325
'IYPical Application Configuration
OSC
(SKEW CONTROL FEEDBACK)
CV7B336
CY7C611A
IU
A20
AO
xo
A2l
Al
Xl
A22
A2
A23
A3
X2
X3
L
X3
FCLOCK
RD
r
RDL
WRT
WRTL
'"
INULL
II)
...I
a.
ROY
Package
(MHz)
(mA)
Ordering Code
1YPe
40
190
P13
Dl4
33
190
CY7C325-40PC
CY7C325-40DC
CY7C325-40JC
CY7C325-33PC
CY7C325 - 33DC
CY7C325 - 33JC
CY7C325-25PC
CY7C325-25DC
CY7C325-25JC
J64
P13
D14
J64
P13
Dl4
J64
Operating
Range
Commercial
Commercial
Commercial
Document #: 38-00184
4-101
RDL
WRTL
SCLOCKl
SCLOCK2
SCLOCKl
SCLOCK2
FNULL ~
INULL
From FPU
RESEr
Ordering Information
fMAX
Icc
RDY
•
Q
TCU
RESEr
RD
90
NOTFCLOCK
FCLOCK
xo
~CY7C325
r--WRT
25
CLK_DSKW'N
N01FCLOCK
' - - - - - OSC
CY7C330
CYPRESS
SEMICONDUCTOR
Features
• lWelve I/O macrocells each having:
- registered, three-state I/O pins
- input register clock select multiplexer
- feed back multiplexer
-output enable (OE) multiplexer
• All twelve macrocell state registers
can be hidden
• User-configurable state registersJK, KS, T, or D
• One input multiplexer per pair 011/0
macrocells allows I/O pin associated
with a hidden macrocell state register
to be saved for use as an input
• Four dedicated hidden registers
• Eleven dedicated, registered inputs
CMOS Programmable
Synchronous State Machine
• Three separate clocks-two inputs,
one output
• Common (pin 14-controlled) or
product term -controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
• 66-MHzoperation
- 3-ns input set-up and 12-ns clock to
output
-15-ns input register clock to state
register clock
• Lowpower
- 130mA1cc
• 28-pin, 300-mil DIP, LCC
• Erasable and reprogrammable
Functional Description
TheCY7C330is ahigh-performance,erasable,programmable, logic device (EPW)
whose architecture has been optimized to
enable the user to easily and efficiently
construct very high performance synchronous state machines.
The unique architecture of the CY7C330,
consisting of the user-configurable output
macroceII, bidirectional I/O capability, input registers, and threeseparateclocks,enabIes the user to design high-performance
state machines that can communicate either with each other or with microprocessors over bidirectional parallel buses of
user-definablewidths.
Logic Block Diagram
VO'D
VOa
va,
VOa
Vss
vo.
Vee
vOa
vo,
va.,
0330-1
Selection Guide
Maximum Operating Frequency,
fMAX(MHZ)
Commercial
Power Supply Current Icc! (rnA)
Commercial
7C330-66
66.6
Military
140
Military
7C330-50
50.0
7C330-40
50.0
40.0
4-102
7C330-28
28.5
130
130
160
7C330-33
33.3
150
150
".-=: ::;z
CY7C330
~=CYPRESS
==::::::;,
SEMICONDUcroR
Input Clock Multiplexer, and architecture configuration bit C4
which determines the input clock selected.
Pin Configuration
LCC/PLCC
ThpView
a. . ~
0
I/O Macrocell
.,....
Thelogic diagram ofCY7C330 I/O macrocell is shown inFigure 5
There are a total of twelve identical macrocells.
Each macrocell consists of:
C\I
__o~Gggg
432~282726
23
1/0 3
1/0 4
1/0 5
22
Vee
25
24
7C330
21
Vss
20
II0a
11 12 13 14 15 16 17 16 19
1/0 7
0330·2
0.,.... 0
-co -0) ....
.,. . .... a 0CD
Q Q
'" '"
011ii
0)
Functional Description (continued)
Three separate clocks permit independent, synchronous state
machinesto be synchronized to each other. The two input clocks,
C1, C2, enable the state machine to sample input signals that may
be generated by another system and that may be available on its
bus for a short period oftime.
Theuser-configurablestateregisterflip-flopsenablethedesigner
to designateJK-, RS-, T-, or D-type devices, so that the number of
productterms required to implement the logic is minimized.
The major functional blocks of the CY7C330 are (1) the input
registersand (input) clock multiplexers, (2) the EPROM (AND)
cell array, (3) the twelve I/O macrocells and (4) the four hidden
registers.
Input Registers and Clock Multiplexers
- An Output State register that is clocked by the global state
counter clock, CLK (Pin 1). The state register can be configured
as a D, JK, RS, or T flip-flop (default is aD-type flip-flop). Polarity can be controlled in the D flip-flop implementation by use of
the exclusive or function. Data is sampled on the LOW to HIGH
clock transition. All of the state registers have a common reset
and set which are controlled synchronously by Product Thrms
which are generated in the EPROM cell array.
- A Macrocell Input register that may be clocked by either the
CK1 or CK2 input clock as programmed by the user with architectureconfiguration bit C2, which controls the I/O Macrocell Input OockMultiplexer. The Macrocell Input registers are initialized upon power-up""such that all of the Q outputs are at logic
LOW level and the Q outputs are at a logic HIGH level.
- An Output Enable Multiplexer (OE), which is user programmable using architecture configuration bit CO, can select either
the common OE signal from pin 14 or, for each cell individually,
the signal from the output enable product term associated with
each macrocell. The output enable input signal to the array product term is clocked through the input register by the selected input register clock, CK1 or CK2.
- An Input Feedback Multiplexer, which is userprogrammable,
can select either the output of the state register or the output of
the Macrocell Input register to be fed back into the array. This
option is programmed by architecture configuration bit Cl. If the
output of the Macrocell Inputregisteris selected by the Feedback
Multiplexer, the I/O pin becomes bidirectional.
There are a total of eleven dedicated input registers. Each input
register consists of a D flip-flop and a clock multiplexer. The
clock multiplexer is user-programmable to select either CK1 or
CK2 as the clock for the flip-flop. CK2 and OE can alternatively
be used as inputs to th~array. The twenty-two outputs ofthe registers (Le., the Q and Q outputs of the input registers) drive the
array of EPROM cells.
co
An architecture confignration bit (C4) is reserved for each dedicated input register cell to allow selection of either input clock
CK1 or CK2 as the input register clock for each dedicated input
cell. If the CK2 clock is not needed, that input may also be used as
a general-purpose array input. In this case the input registerfor
this input can only be clocked by input clock CKl. Figure 4 illustrates the dedicated input cell composed of an input register, an
TO ARRAY
INPUT REGISTER
H----------l
D
Q
TO ARRAY
0330-4
FROM ADJACENT MACROCELL
C4
C3
c33Q.3
Figure 2. Macrocell and Shared Input Multiplexer
Figure 1. Dedicated Input Cell
4-103
o
C
..J
a.
-~PRESS
IF
CY7C330
SEMICONDUCTOR
Functional Description
(continued)
Macrocell Input Multiplexer
Each pair of I/O macrocells share a Macrocell Input Multiplexer
that selects the output of one or the other of thepair'sinputregisters to be fed to the input array. This multiplexer is shown in Figure 2. The Macrocell Input Multiplexer allows the input pin of a
macrocell,forwhich the state register has been hidden by feeding
back its input to the input array to be preserved for use as an input
pin. This is possible as long as the other macrocell of the pair is
not needed as an input or does not require state register feedback. The input pin input register output that would normally be
blocked by the hidden state register feedback can be routed to the
array input path of the companion macrocell for use as array input.
State Registers
By use of the exclusive OR gate, the state register may be configured as a JK-, RS-, or T-type register. The default is aD-type
register. For the D-type register, the exclusive OR function can
be used to select the polarity or the register output.
a common, synchronous set, S, as well as a common, synchronous
reset, R, which override the data at the D input. The Sand R signals are product terms that are generated in the array and are the
same signals used to preset and reset the state register flip-flops.
Macrocell Product Thrm Distribution
Each pair of macrocells has a total of thirty-two product terms.
Two product terms of each macrocell pair are used for the output
enables (OEs) for the two output pins. Two product terms are
also used as one input to each of the two exclusive OR gates in the
macrocellpair. The number of product terms available to the designeris then 32 - 4 = 28 for each macrocell pair. These product
terms are divided between the macrocell state register flip-flops
as show in Table 1.
Thble 1. Product Thrm Distribution for Macrocell
State Register Flip-Flops
Macrocell
Pin Number
Product Terms
0
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
20
19
18
17
16
15
9
19
The set and reset of the state register are global synchronous signals. They are controlled by the logic of two global product terms,
for which input signals are clocked through the input registers by
either of the input clocks, CKI or CK2.
Hidden Registers
In addition to the twelve macrocells, which contain a total of
twenty-fourregisters, there are four hidden registers whose outputs are not brought out to the device output pins. The Hidden
State Register Macrocell is shown in Figure 6.
The four hidden registers are clocked by the same clock as the
macrocellstate registers. All of the hidden register flip-flops have
GLOBAL SET PRODUCT TERM
:
"-
1-
J)
D
PIN 1, elK
GLOBAL RESET PRODUCT TERM
-p.
S
11
11
17
13
15
15
13
17
11
19
9
Hidden State Register Product Thrm Distribution
Each pair of hidden registers also has a total of32 product terms.
Two product terms are used as one input to each of the exclusive
OR gates. However, because the register outputs do not go to any
output pins, output enable product terms are not required.
Therefore,30 product terms are available to the designer for each
pair of hidden registers. The product term distribution for the
four hidden registers is shown in Table 2.
Thble 2. Product Term Distribution for Hidden Registers
Q
Hidden Register Cell
Q
'---T--
0
1
2
3
f--
TO ARRAY
Product Terms
19
11
17
13
Architecture Configuration Bits
s::
The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in
Table 3.
c330-5
Figure 3. Hidden State Register Macrocell
4-104
CY7C330
Thble 3. Architecture Configuration Bits
Architecture
Configuration Bit
CO
Output Enable
SelectMUX
Cl
C2
C3
C4
Number of Bits
12 Bits, 1 per I/O Macrocell
Value
0--Virgin State
I-Programmed
Output Enable Controlled by Pin 14
State Register
FeedbackMUX
12 Bits, 1 per I/O Macrocell
0--Virgin State
State Register Output is Fed Back to Input Array
I-Programmed
I/O Macrocell is Configured as an Input and Output of Input Register is Fed to Array
I/O Macrocell
Input Register
Clock Select MUX
12 Bits, 1 per I/O Macrocell
0--Virgin State
CKI Input Register Clock (Pin 2) is Connected to
I/O Macrocell Input Register Clock Input
I-Programmed
CK2lnput Register Clock (Pin 3) is Connected to
I/O Macrocell Input Register Clock Input
I/O Macrocell Pair
Input Select MUX
Dedicated Input
Register Clock
SelectMUX
6 Bits, 1 per I/O Macrocell
Pair
11 Bits, 1 per Dedicated
Input CeIl
Function
Output Enable Controlled by Product Term
0--Virgin State
Selects Data from I/O Macrocell Input Register
of Macrocell A of Macrocell Pair
I-Programmed
Selects Data from I/O Macrocell Input Register
of Macrocell B of MacroceIl Pair
0--Virgin State
CKI Input Register Clock (Pin 2) is Connected to
Dedicated Input Register Clock Input
I-Programmed
CK2 Input Register Clock (Pin 3) is Connected to
Dedicated Input Register Clock Input
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
StorageThmperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 22 to Pins 8 and 21) ................. -0.5Vto+7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DCInputVoltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 12 rnA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
4-105
Latch-UpCurrent ............................ >200rnA
DC ProgrammingVoltage ......................... l3.0V
Operating Range
Range
Commercial
MilitaryllJ
Ambient
Thmperature
O°Cto +75°C
Vee
5V ± 10%
- 55°Cto +125°C
5V± 10%
Note:
1 TA is the "instant on" case temperature.
II
I/)
C
..J
Il.
~
~=CYPRESS
CY7C330
~, SEMIcalDUCTOR
Electrical Characteristics
Overthe Operating Rangel2]
Description
Parameters
Thst Conditions
Min.
Output HIGH Voltage
Vee = Min., VIN = VIH or VIL
IoH = -3.2 rnA (Com'l), IOH = -2 rnA (Mil)
VOL
Output LOW Voltage
Vee = Min., VIN = VIH or VIL,
IOL = 12 rnA (Com'l), IOH = 8 rnA (Mil)
Vrn
Input HIGH Voltage
Guaranteed Logical HIGH Voltage for all Inputs[3]
VIL
Input LOW Voltage
Guaranteed Logical LOW Voltage for all Inputs[3]
IIX
Input LeakageCurrent
Vss < VIN < Vee, Vee = Max.
Ioz
Output LeakageCurrent
Vee = Max., Vss < VOUT < Vee,
Isd4]
Output Short Circuit Current
Vee = Max., VOUT = 0.5V[5]
IcC!
Standby Power Supply
Current
Vee = Max., VIN = GND
Outputs Open
Power S~1y Current at
Frequen ~, 6]
Iccz
Vee = Max.
Outputs Disabled
(in High Z State),
Device o&erating at fMAX
External fMAXI)
Max. Units
2.4
VOH
V
0.5
V
2.2
V
0.8
V
-10
+10
-40
+40
!AA
!AA
-30
-90
rnA
Commercial-66
140
rnA
Commercial-33, -50
130
Military-50
160
Military -28,-40
150
Commercial-66
180
Commercial- 33, - 50
160
Military-50
200
Military -28, -40
180
rnA
Capacitance[4]
Max.
Units
CIN
Parameters
InputCapacitance
Description
VIN = 2.0V at f = 1 MHz,
Thst Conditions
10
pF
CoUT
Output Capacitance
VOUT = 2.0Vatf= 1 MHz,
10
pF
Notes:
2. See the last page of this specification for Group A subgroup testing
infonnation.
3. These are absolute values with respect to device ground and allover·
shoots due to system or tester noise are included.
4. Thsted initially and after any design or process changes that may af·
fect these parameters.
5.
6.
Min.
Not more than one output should be tested at a time. Duration of the
short circnit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degrada.
tion.
Tested by periodic sampling of production product.
AC Test Loads and Waveforms
R1 3130
R1 3130
OUTP~~ ~(4700
Mil)
I
50 pF
INCLUDING _
JIG AND
SCOPE
OUTP~~ 5 f ] ( 4 7 0
Mil)0
R22080
(3100 Mil)
_
-
Equivalent to:
90%
R2 2080
(3100 Mil) GND
1
5 PF
INCLUDING _
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0V
~ 5 ns
_
-
(b)
0330-7
THEVENIN EQUIVALENT (Commercial)
Equivalenllo:
1250
OUTPUT 0---'wIr--<) 2.00V = Vthc
THEVENIN EQUIVALENT (MiIHary)
OUTPUT
c~
4-106
~
2.02V =Vthm
c33O-9
~
·~PRfSS
~F
CY7C330
SEMICONDUCTOR
AC Test Loads and Waveforms
Parameter
tpXZ(-)
tPXZ(+)
(continued)
Vx
Output \'\\lveform-Measurement Level
1.5V
0_5V~
2.6V
VOL
tpzX(+)
tcER(-)
tCER(+)
Vthc
1.5V
VOH
O.5V~
2.6V
VOL
tCEA(+)
Vx
tCEA(-)
Vthc
VOH
c330-12
U)
C
~~
VOL
c33O-13
~~
Vx
c330-14
...I
a..
Vx
0330-15
~~
O.5V~
Vx
•
c330-11
?~
O.5V~
Vthc
0330-10
Vx
7~
O.5V~
O.5V~
Vx
Vx
~~
0.5V~
Vthc
Vx
tpZX(-)
~~
O.5V~
VOH
VOH
0330-16
~~
VOL
c330-17
(c) Thst Waveforms and Measurement Levels
Switching Characteristics
Parameters
tIS
los
tco
tIH
tCEA
tCER
tpzx
tpxz
Over the Operating Rangel2, 7]
Description
Input or Feedback
Set-Up Time to Input
RegisterClock
Input Register Oock to
Output RegisterClock
Output Register Clock to
Output Delay
Input Register Hold Time
Input Register Clock to
Output Enable Delay
Input Register Clock to
Output Disable Delay[8]
Commercial
Commercial
-66
-SO
-33
-SO
-28
-40
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3
5
10
ns
5
5
10
15
20
12
20
30
15
20
25
15
ns
35
20
25
ns
.
5
Pin 14 Enable to Output
Enable Delay
Pin 14 Disable to
Output Disable Delay[8]
20
5
20
5
30
5
20
5
25
5
35
ns
ns
20
20
30
20
25
35
ns
20
20
30
20
25
35
ns
20
20
30
20
25
35
ns
tWH
Input or Outp.ut Clock
Width HlGH[4, 6]
6
8
12
8
10
15
ns
tWL
Input or Oumut Clock
Width LOW 4, 6]
6
8
12
8
10
15
ns
4-107
CY7C330
Switching Characteristics Over the Operating Rangef7,2J (continued)
Commercial
Commercial
-50
-50
-28
-33
-40
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3
3
3
3
3
3
ns
-66
Parameters
toR
Description
Output Data Stable Time
fromS~chronousOock
tIOR-tIH
Input!
Output Data Stable Time
This Device Minus IIP
Reg Hold Time Same
DeviceClOJ
0
0
0
0
0
0
ns
tOR - tIH
33x
Output Data Stable TIme
Minus IIP Reg Hold Time
7C330 and 7C332
Devices!l1]
0
0
0
0
0
0
ns
tp
External Clock Period
~O + tIS), Input and
tputOockCommon
Maximum External
15
20
30
20
25
35
ns
66.6
50.0
33.3
50.0
40.0
28.5
MHz
fMAXI
OperatingFre~wency
fMAX2
(1/(tco + tIS» 2]
Maximum Re&,sterToggle
Frequencyl6, ]
83.3
62.5
41.6
62.5
50.0
33.3
MHz
fMAX3
Maximum Internal
OperatingFrequencyll4]
74.0
57.0
37.0
57.0
45.0
30.0
MHz
Notes:
7. Part (a) of AC Thst Loads is used for all parameters except 1:cEA,
tCER, tpzx, and tpxz, which use part (b).
8. This parameter is measured as the time after output register disable
input that the previous output data state remains stable on the output. This delay is measure to the point atwhich a previous ffiGHlevel has fallen to O.5V below VOH Min. or a previous WW level has
risen to 0.5V above VOL Max. Please see part (c) of AC 'lest Loads
and Wavefonns for enable and disable test waveforms and measurement reference levels.
9. This parameter is measured as the time after output register clock input
that the previous output data state remains stable on the output.
10. This difference parameter is designed to guarantee that any 7C330
output fed back to its own inputs esternally or internally will satisfy
the input register minimum input hold time. This parameter is guaranteed for a given individual device and is tested by a periodic sampling of production product.
11. This specification is intended to guarantee feeding of this sigual to
another 33X family input register cycled by the same clock with sufficient output data stable time to insure that the input hold time minimum
of the following input register is satisfied. This parameter difference
specification is guaranteed by periodic sampling of production product
of 7C330 and 7C332 It is guaranteed to be met only for devices at the
same ambient temperature and V cc supply voltage.
12. This specification indicates the guaranteedmaximum frequency at which
a state machine configuration with estemal feedback can operate.
13. This specification indicates the guaranteed maximum frequency at
which an individual input or output register can be cycled.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with only internal feedback can
operate. This parameter is tested periodically on a sample basis.
Switching Waveform
I/O INPUTS,
REGISTERED _ _ __
FEEDBACK
INPUTS
INPUT CLOCK
OUTPUT CLOCK
OUTPUTS _ _"""-='1-
PIN14
OE
c330-18
4--108
--::~
_ F SEMICONDUCTOR
CY7C330
~=CYPRESS
CY7C330 Logic Diagram (Upper Halt)
[I}s
ID-
11~
LO
L66
.
"
.!
....
L2178
....
~
~~
~8
":j~
~.
om
(CO•. 2)
III
C
..J
C.
~ f{IDS
~l-"
:+~
L3036
(CO•• 3)
nod. =40
_L,J
L792
LIIb
.":'. RESET nodo = 2.
(co.. 3)
(CO •. 2)
.,gO
11~
LiIH
~Il
....
fiill2
nod. = 38
,,~
l5.80
HillS
L6oI02
LiIH
.J
If
t;;•
) "..0=3
~1rnt·,
T(V
L . . - - - - - - - - - T O LOWER S E C T l O N - - - - - - - - - - - . . . . J
4-109
(CO .. J)
(CO•• 2)
~~
~1ECYPRESS
"
JF
CY7C330
SEMICONDUCTOR
CY7C330 Logic Diagram (Lower Half)
. . . . - - - - - - - - - 1 0 UPPER S E C T I O N - - - - - - - - - - ,
~f€l"
11111111
I!H
~
...
LH34I
-11111111
Il!h
mH
~.u
II
'07".(co.. 3l
noch=l1
~
~
..._,
ftm
J-=32
~
.,
.~
nod.=l1
~~
mH ., ...
Hm
_=36
~
U3992
~ r..
..
~
~(co..•)
...
ftOde;=35
L,.J
f€i(
~
L16962
:iEf
.
ill ...
4-110
n0d4=JO
,,"'"(co.. 2)
F@
~..
, ....
(CO•. 2)
or
co.. 2)
~
~-;:.z
CY7C330
~~CYPRESS
~, SEMICOIDUCTOR
Ordering Information
Iccl (max)
fMAX(MHz)
140
66.6
160
130
150
130
150
50
50
40
33.3
28.5
CY7C330-66HC
Package
lYpe
H64
CY7C330-66JC
J64
Ordering Code
CY7C330-66PC
P21
CY7C330-66WC
W22
CY7C330-50DMB
D22
CY7C330-50HMB
H64
CY7C330-50LMB
L64
CY7C330-50QMB
CY7C330-50TMB
064
T74
CY7C330-50WMB
W22
CY7C330-50HC
H64
CY7C330-5OJC
J64
CY7C330-50PC
P21
CY7C330-50WC
W22
CY7C330-40DMB
D22
CY7C330-40HMB
H64
CY7C330-40LMB
L64
CY7C330-40QMB
Q64
CY7C330-40TMB
T74
CY7C330-40WMB
W22
CY7C330-33HC
H64
CY7C330-33JC
J64
CY7C330-33PC
P21
CY7C330-33WC
W22
CY7C330-28DMB
D22
CY7C330-28HMB
H64
CY7C330- 28LMB
L64
CY7C330-280MB
064
CY7C330-28TMB
T74
CY7C330-28WMB
W22
4-111
Operating
Range
Commercial
Military
til
C
..J
a...
Commercial
Military
Commercial
Military
&;~PRFSS
CY7C330
~, SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VIL
1,2,3
IJX
Ioz
Icc
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tISU
tosu
teo
tH
tCEA
tpzx
7,8,9,10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
Document #: 38-00064-C
4-112
CY7C331
CYPRESS
SEMICONDUCTOR Asynchronous Registered EPLD
Features
• 1\velve I/O macroce\ls each having:
- One state Dip-flop with an XOR
sum-of-products input
- One feedback Dip-flop with input
coming from the I/O pin
- Independent (product term) set,
reset, and clock inputs on all
registers
- Asynchronous bypass capability on
all registers under product term
control (r s 1)
- Global or local output enable on
three-state I/O
- Feedback from either register to
the array
• 192 product terms with variable distribution to macrocells
= =
• 13 inputs, 12 feedback I/O pins, plus 6
shared I/O macrocell feedbacks for a
total of 31 true and complementary
inputs
• High speed: 20 ns maximum tpD
• Security bit
• Space-saving 28-pin slim-line DIP
package; also available in 28-pin
PLCC
• Lowpower
-90 mA typical Icc quiescent
-IBO mA Icc maximum
- UV-erasable and reprogrammable
- Programming and operation 100%
testable
Functional~~ption
The CY7C331 is the most versatile PLD
available for asynchronous designs. Central resources include twelve full Ootype
Dip-flops with separate set, reset, and
clock capability. For increased utility,
XOR gates are provided at the O-inputs
and the product term allocation per flipflop is variably distributed.
I/O Resources
Pins 1 through 7 and 9 through 14 serve
as array inputs; pin 14 may also be used as
a global output enable for the I/O macrocell three-state outputs. Pins 15 through
20 and 23 through 28 are connected to
I/O macrocells and may be managed as
inputs or outputs depending on the configuration and the macrocell OE terms.
Logic Block Diagram
I.
m'I1'2
110"
110,.
110.
va.
lIOo
Vee
GND
C331-1
Selection Guide
Generic Part
Number
CY7C331-20
CY7C331-25
CY7C331-30
CY7C331-35
CY7C331 40
Iccl (mA)
Com'I
130
120
tPD (ns)
Mil
160
150
120
Com'l
20
25
ts (ns)
Mil
25
30
Mil
15
40
4-113
teo (ns)
Mil
Com'l
20
25
25
30
15
15
35
150
Com'l
12
12
35
20
40
•
en
o
...J
a.
:i.Yn
~
CY7C331
PRffiS
SEMIC<:l'IDUCTOR
Pin Configuration
'Q' (sets it false). Ifboth RandS are asserted (true) at once, then
the output will follow the input ('Q' = 'D') (see Table 1) .
PLCC
Top View
.»~.r..9~gg
Thble 1. RS Truth Thble
va.
vo.
va.
"
I.
I.
GND
GND
I.
I.
VD7
Q
o
o
1
1
D
1
Va.
::~55QQ
fj :;.::;. - -
S
1
o
Vee
17
R
Shared Input Multiplexer
C331·2
I/O Resources (continued)
It should be noted that there are two ground connections (pins 8
and 21) which, together with Vcc (pin 22) are located centrally
on the package. The reason for this placement and dual-ground
structure is to minimize the ground-loop noise when the outputs
are driving simultaneously into a heavy capacitive load.
The CY7C331 has twelve I/O macrocells (seeFigwr! 1). Each macrocell has two D-type flip-flops. One is fed from the array, and one from
the I/O pin. For each flip-flop there are three dedicated product
terms driving the R, S, and clock inputs, respectively. Each macrocell
has one input to the array and for each pair of macrocells there is one
shared input to the array. The macrocell input to the array may be
configured to come from the 'Q' output of either flip-flop.
The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the 'Q' output of the flip-flop coming from the I/O pin is
used as the input signal source (see Figure 2).
Product Term Distribution
The product terms are distributed to the macrocells such that 32
product terms are distributed between two adjacent macrocells.
The pairing of macrocells is the same as it is for the shared inputs. Eight of the product terms are used in each macrocell for
set, reset, clock, output enable, and the upper part of the XOR
gate. This leaves 16 product terms per pair of macrocells to be
divided between the sum-of-products inputs to the two state registers. The following table shows the I/O pin pairing for shared
inputs, and the product term (PT) allocation to macrocells
associated with the I/O pins (see Thble 2).
The D-type flip-flop that is fed from the array (i.e., the state flipflop) has a logical XOR function on its input that combines a
single product term with a sum(OR) of a number of product
terms. The single product term is used to set the polarity of the
output or to implement toggling (by including the current output
in the product term).
The Rand S inputs to the flip-flops override the current setting
of the 'Q' output. The S input sets 'Q' true and the R input resets
Table 2. Product Term Distribution
Macrocell
Pin Number
Product Terms
0
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
20
19
18
17
16
15
4
12
6
10
8
8
8
8
10
6
12
4
11
MACROCELLA
FEEDBACK TO
LOGIC ARRAY
TO ARRAY
----::>"1
---<:)00..1
Q-OUTPUT FROM
INPUT REGISTER OF
I/O MACROCELL A
INPUT TO - - - . , . . - ,
LOGIC ARRAY ---0-..1
INPUT REGISTER CLOCK PRODUCT TERM
Q-OUTPUT FROM
INPUT REGISTER OF
I/O MACROCELL B
INPUT REGISTER RESET PRODUCT TERM
r--~-..L.---,
OUTPUT FROM
LOGIC ARRAY
C331·3
TO ARRAY
MACROCELLB
FEEDBACK TO - - - 7 ' 1
LOGIC ARRAY ---0-..1
FROM ADJACENT MACROCELL
C2
Figure 2. Shared Input Multiplexer
Figure 1. I/O Macrocell
4-114
C331-4
CY7C331
Maximum Ratings
I/O Resources (continued)
The CY7C331 is configured by three arrays of configuration bits
(CO, C1, C2). For each macrocell, there is one (l) bit and one C1
bit. For each pair of macrocells there is one C2 bit.
There are twelve CO bits, one for each macrocell. If (l) is programmed for a macrocell, then the three-state enable (OE) will
be controlled by pin 14 (the global OE). If CO is not programmed, then the OE product term for that macrocell will be
used.
There are twelve C1 bits, one for each macrocell. The C1 bit selects inputs for the product term (PT) array from either the state
register (if the bit is unprogrammed) or the input register (if the
bit is programmed).
There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the
C2 bit is not programmed, then the input to the product term
array comes from the upper macrocell (A). If the C2 bit is programmed, then the input comes from the lower macrocell (B).
The timing diagrams for the CY7C331 cover state register, input
register, and various combinational delays. Since internal clocks
are the outputs of product terms, all timing is from the transition
of the inputs causing the clock transition.
~Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Thmperature .......•.•••.•.... - 65· C to + 150·C
Ambient Thmperature with
Power Applied ............•••.•••.... - 55·C to + 125·C
SU.Pl'ly Vol~e to Ground Potential
(Pm 28 to Pm 8 or 21) •.....•.•..••...... - 0.5V to +7.0V
DC Input Voltage ..............•..•.•... - 3.0V to +7.0V
Output Current into Outputs (LOW) ..••........... 12 rnA
~~~~t~J~~I~ili~d' jOiS) . . . . . . . . . . . . . . .. >2001 V
Latch-Up Current ....•..••................•.• >200 rnA
DC Programming Voltage •••......•.............. , 13.0 V
Operating Range
Ambient
Temperature
Range
Commercial
Militaryll]
O·Cto +70·C
Vee
5V:!: 10%
- 55·Cto +125·C
5V:!: 10%
Electrical Characteristics Over the Operating Range[2]
Description
Parameters
MiD. Max. UDits
Test ConditioDs
VOH
Output mGR Voltage
Vcc = Min., VIN = VlHorVIL
IOH = - 3.2 rnA (Com'I), IoH = - 2 rnA (Mil)
VOL
Output LOW Voltage
VIH
Input mGR Voltage
VCC = Min., VIN = VIH or VIL
IOL = - 12 mA (Com'I), IOL = - 8 rnA (Mil)
Guaranteed mGR Input, all Inputsl3]
VIL
Input LOW Voltage
Guaranteed LOW Input, all Inputsl3)
IIX
Input Leakage Current
Vss < VIN < Vcc, Vcc = Max.
Ioz
Output Leakage Current
Vss < VOUT < Veo Vcc = Max.
Isc
Output Short Circuit
Currentl4)
Vee = Max., VOUT = O.5y[S]
-30
ICCI
Standby Power Supply
Current
Vee = Max., VIN = GND,
Outputs Open
Power Su~1y Current at
Frequen 4,6]
Iccz
Vee = Max., Outputs Disabled
gn
High Z State)
evice Operating at fMAX External (fMAXI)
V
24
0.5
V
0.8
V
-10
+10
-40
+40
i.tA
i.tA
-90
rnA
Com'1-20
130
rnA
Com'! -25, -35
120
Mil-25
160
Mil-30, -40
150
Com'l
180
Mil
200
22
V
rnA
rnA
Capacitance(4)
Parameters
Max.
UDitS
CIN
Input Capacitance
VIN = 2.0V at f = 1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0Vat f = 1 MHz
10
pF
Notes:
NO TAG.
Description
Test CoDditiODs
TA is the "instant on" case tempera-
S.
lUre.
3.
3.
4.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Thsted initially and after any deaign or proceas changea that may affect
these parameters.
6.
4-115
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second Vour = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
Because these input signals are controlled by product terms, active input polarity may be of either polarity. Internal active input polarity has
been shown for clarity.
II
en
o
a.
...J
CY7C331
AC Test Loads and Waveforms
R13130
R1 3130
OUTP~~ § = i ( 4 7 Mil)
00
50 pF . r
INCLUDING _
JIG AND
SCOPE
R2 2080
(3100 Mil)
_
-
(b)
~
90%
O33Hl
0331-5
THEVENIN EQUIVALENT (Commercial)
OUTPUT
3.0V
R22080
(3190 Mil) GND
_
5. 5 ns
-
5 PF.r
INCLUDING _
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
OUTP~~ 5 f l ( 4 7 0
Mil)0
Equivalent to:
2.00V = Vthc
THEVENIN EQUIVALENT (Military)
OUTPUT
~
2.02V = Vthm
O33HI
0331·7
Parameter
tpXZ(-)
tpxz(+)
Vx
1.5V
Output \'\aveform-Measurement Level
VOH
O.5V~
0.5V~
2.6V
VOL
tpZX(+)
0.5V~
Vthc
Vx
tpZX(-)
tER(-)
tER(+)
Vthc
1.5V
Vx
VOH
0.5V~
0.5V~
O.5V~
2.6V
VOL
tEA(+)
0.5V~
Vthc
Vx
tEA(-)
Vthc
Vx
O.5V~
~~
Vx
~~
0331-9
Vx
C331-10
7~
VOH
0331-11
~~
VOL
0331-12
~~
Vx
0331-13
7~
Vx
0331-14
~~
VOH
0331-15
~~
VOL
0331-16
(e) Test Waveforms and Measurement Levels
Switching Characteristics Over the Operating Rangel3]
Commercial
-20
Parameters
Description
Min.
-25
Min.
-35
Max.
Min.
Max.
Units
tpD
Input to Output PropagationDelay(7]
20
25
35
tlCO
tIOH
Input Register Clock to Output Delay[8]
35
40
55
ns
ns
tIS
tIH
Max.
Output Data Stable Time from Input Clock[8]
Input or Feedback Set-Up Time to Input RegisterClock[8]
5
2
5
2
5
ns
2
ns
Input Register Hold Time from Input Clock[8]
11
13
15
ns
4-116
I
rr ·-~
i IE CYPRESS
CY7C331
~.' SEMlCONDUCIOR
Switching Characteristics
Over the Operating Range[3] (continued)
Commerdal
-20
Description
Parameters
Min.
tIAR
Input to Input Register Asynchronous Reset Delayl8]
trRw
Input Register Reset Width[4, 8J
35
trRR
tIAS
Input Register Reset Recovery Timel4, 8]
35
trsw
trsR
tWH
tWL
Input to Input Register Asynchronous Set Delay[8]
Input Register Set Width[4, 8]
Input Register Set Recovery Timel4, 8]
-25
Max.
Min.
35
Min.
40
40
Max.
55
55
40
35
Input and Output Clock Width HIGH[8, 9, 10J
Input and Output Clock Width LOwt:8, 9, 10J
-35
Max.
ns
ns
55
40
Units
ns
55
ns
35
40
55
ns
35
40
55
ns
12
15
20
ns
12
27.0
15
20
ns
23.8
17.5
MHz
fMAXI
Maximum Frequency with Feedback in Input Registered
Mode (l/(trco + trs»[llJ
fMAX2
Maximum Frequency Data Path in Input RegisteredMode
(Lowestofl/trco, l/(tWH + tWL), or l/(tIS + tIH)[8]
28.5
25.0
18.1
MHz
tIOHtIH33X
Output Data Stable from Input Clock Minus Input Register
Input Hold Time for 7C330 and 7C332[12, 13]
0
0
0
ns
teo
tOH
Output Register Clock to Output Delayl9]
Output Data Stable Time from Output Clock[9]
3
3
3
ns
ts
Output Register Input Set-Up Time to Output Clock[9]
12
12
15
ns
tH
Output Register Input Hold Time from Output Clock[9]
8
8
10
tOAR
Input to Output Register Asynchronous Reset Delay[9]
tORW
Output Register Reset Width[9]
20
tORR
Output Register Reset Recovery Timel9]
20
tOAS
Input to Output Register Asynchronous Set Delay[9]
tosw
Output Register Set Widthl9]
20
25
35
tOSR
20
25
35
tEA
Output Register Set Recovery Timel9]
Input to Output Enable Delay[I4, 15]
tER
tpzx
Input to Output Disable Delayl14, 15]
Pin 14 to Output Enable Delay[14, 15]
tpxz
Pin 14 to Output Disable Delay[14, 15]
fMAX3
MaximumFrequen~with Feedback in Output Registered
Mode (l/(tco
+ ts»
20
35
25
20
25
20
ns
35
35
25
25
ns
ns
35
25
ns
ns
35
ns
ns
ns
25
25
35
ns
25
25
35
ns
20
20
30
ns
20
20
30
ns
31.2
27.0
20.0
MHz
41.6
33.3
25.0
MHz
0
0
0
ns
35.0
30.0
22.0
MHz
16, 17]
fMAX4
Maximum Frequency Data Path in Output RegisteredMode
(Lowest of l/teo, 1/(tWH + twL), or l/(ts + tH»[9]
tOHtIH33X
Output Data Stable from Output Clock Minus In8ut
Register Input Hold Time for 7C330 and 7C332[ ,18]
fMAX5
Maximum Frequency PipelinedModel1O, 17]
Notes:
7. Refer to Figure 3, configuration 1.
8. Refer to Figure 3, configuration 2.
9. Refer to Figure 3, configuration 3.
10. Refer to Figure 3, configuration 6.
11. Refer to Figure 4, configuration 7.
12. Refer to Figure 5, configuration 9.
13. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C331. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product.
14. Part (a) of AC Thst Loads and Waveforms used for all parameters except tpZXI, tpXZI, tpzx, and tfXZ, which use part (b). Part (c) shows
the test waveforms and measurement levels.
15. Refer to Figure 3, configuration 4.
16. Refer to Figure 4, configuration 8.
17. Thisspecification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated
with output register and input register clocks controlled by the same
source. These parameters are tested by periodic sampling of produc·
tion product.
18. Refer to Figure 5, configuration 10.
4-117
•
U)
C
..J
Q.
~
.~~
Switching Characteristics
CY7C331
Over the Operating Range!3] (continued)
Military
-25
Parameters
Max.
Units
25
30
40
ns
tlCO
Input Register Oock to Output Delayl4, 8]
45
50
65
ns
tlOH
Output Data Stable Time from Input Clock[4, 8]
5
5
5
ns
tiS
tm
Input or Feedback Set-Up Time to Input RegisterClock[8]
5
13
5
15
5
ns
tIAR
Input to Input Register Asynchronous Reset Delay[4, 8]
tlRW
Input Register Reset Width[8]
45
50
65
tlRR
tIAS
Input Register Reset Recovery Timel"8]
45
50
65
tWH
tWL
Input Register Hold Time from Input Oock[4, 8]
Input to Input Register Asynchronous Set Delay[8]
Input Register Set Width[8]
Input Register Set Recovery Timel"8]
Input and Output Clock Width High[8, 9, 10]
Input and Output Clock Width Lowl8, 9, 10]
Max.
Min.
-40
Input to Output PropagationDelayl7]
tlSR
Min.
-30
tpo
tlSW
Description
45
Max.
Min.
20
50
50
45
ns
65
ns
ns
ns
65
ns
45
50
65
ns
45
50
65
ns
15
20
25
ns
15
20
25
ns
fMAXI
Maximum frequency with Feedback in Input Registered
Mode (1/(tlCO + tIS»[11]
20.0
18.1
14.2
MHz
fMAX2
Maximum frequency Data Path in Input RegisteredMode
(Lowestof1/tlco, l/(tWH + tWL), or 1/(tIS + tm)[8]
22.2
20.0
15.3
MHz
tlOHtm 33X
Output Data Stable from Input Clock Minus Input Register
Input Hold Time for 7C330 and 7C332[12, 13] .
0
0
0
ns
teo
Output Register Clock to Output Delay[9]
tOH
ts
Output Data Stable Time from Output Clock[9]
3
3
3
ns
Output Register Input Set-Up Time to Output Clock[9]
15
15
20
ns
tH
Output Register Input Hold Time from Output Clock[9]
10
10
12
tOAR
Input to Output Register Asynchronous Reset Delay[9]
25
30
40
30
25
tORW
Output Register Reset Width[9]
25
30
40
Output Register Reset Recovery Timel"9]
25
30
40
toAS
tosw
Input to Output Register Asynchronous Set Delay[9]
Output Register Set Width[9]
25
30
40
tOSR
tEA
Output Register Set Recovery Timel"9]
Input to Output Enable Delay[14, 15]
25
30
40
tER
tpzx
tpxz
fMAX3
MaximumFrequen~with Feedback in Output Registered
25.0
22.2
fMAX4
Maximum Frequency Data Path in Output RegisteredMode
(Lowest of 1/tco, 1/(tWH + twd, or 1/(ts + tH)[9]
33.3
toHtm33X
Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C330 and 7C332[13, 18]
fMAXS
Maximum Frequency PipelinedMode[lO, 17]
30
25
25
30
Input to Output Disable Delay[14, 15]
25
30
Pin 14 to Output Enable Delay[14, 15]
20
Pin 14 to Output Disable Delay[14, 15]
20
Mode )1/(tco + ts)[ 6, 17]
4-118
ns
40
tORR
ns
ns
ns
ns
40
ns
ns
ns
ns
40
40
ns
25
35
ns
25
35
16.6
ns
MHz
25.0
20.0
MHz
0
0
0
ns
28.0
23.5
18.5
MHz
.
~
~=CYPRESS
"'=9!!!!!F F SEMICONDUCTOR
CY7C331
Switching Waveforms
INPUT OR
1/0 PIN
I/O INPUT
REGISTER
CLOCK[6I
•
OUTPUT
REGISTER
CLOCK[6I
I/)
OUTPUT
C
..J
a..
SET AND
RESET
INPUTS[6I
0331-17
OEPRODUCT
TERM INPUT[6, 15]
PIN 14 AS OE[24]
--4--"1
OUTPUT
--4----""'J'I
OUTPUT
REGISTER
RESET INPUT[6,91 _ _ _ _ _ _ _ _ _ _ _ _",
OUTPUT
REGISTER
-------------------t~;;l::===t:j:=~
CLOCK[6,9I
OUTPUT
REGISTER
SET INPUT[6,91 _ _ _ _ _ _ _ _ _ _ _ _ _ _.,-_ _ _1-_-'
~AR
I/O INPUT
REGISTER RESET
INPUT[6,BI _ _ _ _ _ _ _ _ _ _ _ _ _--'
IOSR
tosw
I/O INPUT
REGISTER
CLOCK[6,BI _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~---+-
lIAS
I/O INPUT
REGISTER
SET INPUT[6, B
IISR
~sw
C331-18
Notes:
19. Output register is set in 1tansparent mode. Output register set and reset inputs are in a HIGH state.
20. Dedicatedinput or input register set in 1tansparentmode. Inputregister set and reset inputs are in a HIGH state.
21. CombinatorialMode. Reset andsetinputs of the input and output registers should remain in aHlGH state at least nntil the output responds
at tpD. When returning set and reset inputs to a WW state, one of
these signals should go LOW a minimum of tOSR (set input) or toRR
(reset input) prior to the other. This guarantees predictable register
states upon exit from Combinatorial mode.
22. When entering the Combinatorial mode, input and output register set
and reset inputs must be stable in a HIGH state a minimum of tlSR or
tJRR and toSR or tORR respectively prior to application oflogic input
signals.
23. When returning to the input andlor output Registeredmode, register
set and reset inputs must be stable in a WW state a minimum of tISR
or tmR and toSR or tORR respectively prior to the application of the
register clock input.
24. RefertoFigure3,coufiguration5.
4-119
~
•
~PRF.SS
CY7C331
.
,
SEMlCONDUcroR
CONFIGURATION 1
~ ~------------q;---§PIN
~
El
ARRAY
DE
INPUT OR 110 PIN
PIN l
_____~C~LO;,C;K/S~/R~--D~=:j
r
CONFIGURATION 2
I/O PIN
UNREGISTERED
INPUT OR liD PIN
INPUT
PRODUCT
lERM
ARRAY
INPUT REGISTER
OUTPUT REGISTER
PIN
CONFIGURATION 3
D
UNREGISTERED
INPUT OR I/O PIN
PIN
Q
PRODUCT
TERM
ARRAY
RESET
CLOCK/SIR
INPUT
UNREGISTERED
INPUT OR 110 PIN
PIN
CONFIGURATION 4
PRODUCT
TERM
ARRAY
INPUT OR I/O PIN
PIN
INPUT OR 110 PIN
I/O PIN
PIN
14
CONFIGURATION 5
INPUT OR 110 PIN
PIN
INPUT OR liD PIN
INPUT REGISTER
CONFIGURATION 6
UNREGISTERED
INPUT OR I 0 PIN
OUTPUT REGISTER
PRODUCT
lERM
ARRAY
CLOCK
CLOCK
PIN
C331-19
CLOCK INPUT
Figure 3. Timing Configurations
4-120
d1
•,'=~CYPRESS
SEMlCONDUClDR
CY7C331
DATA INPUT
INPUT REGISTER
CONFIGURATION 7
-t____
•
/I)
OUTPUT REGISTER
L-~D~A~JA~I~NP~U~T~-1~~:::j~____
PIN J
OUTPUT REGISTER
CONFIGURATION 8
PIN
C
~
...I
a..
PRODUCT
TERM
ARRAY
}-...E::22~!!:!!!:....--t:~::::j
C331-20
Figure 4
CONFIGURATION 9
CONFIGURATION 10
C331-21
CLOCK
FigureS
4-121
ii!iPRESS
_
.
CY7C331
SEMICONDUCTOR
CY7C331 Logic Diagram (Upper Half)
-
-
~
IS
24
...
U
.
,-I-
LO
l!J.
L806
~
rrL-J
34
.OO(02)
~
(co•.• )
~
(CO•• ,)
E
u .....
1":"1
-Li_
l!.r.S
-
ID
L2852
1.0
I:J.
E
-
,..".,
-
33
9" (02)
~
(co••• )
~
(CO•• ,)
J
U ...
-
'-!..r-.
In
g
noct. 32
L".'S(02)
L41M111
,-
r;"1
I
TO LOWER SECTION
4-122
'I
~
(co•.• )
~-
~~PRESS
~, SEMIC~DUClOR
CY7C331
CY7C331 Logic Diagram (Lower Half)
TO UPPER SEtnON
I
....L
....5.
~
l~srr
"'"
....
~
"- ~ 1
6130
j.D
..,..,.
.....
node 31
L.It•• ( C2)
~
LI....
(co..• )
~
rJr
(00..')
.... :so
L•• '" ( C2)
0
._.
I.
~
rr~I
~
(co..• )
~
(co•.• )
........20
' ... r i=
.....,.,.,
~~
L1.
1-....
-
.-..
4-123
node 21
LI113. ( C2)
.
::r ~
J
II
CY7C331
Ordering Information
Iccl (mA)
tpn (ns)
ts (ns)
teo (ns)
130
20
12
20
160
25
15
25
Package
'JYpe
Operating
Range
CY7C331-20HC
H64
Commercial
CY7C331-20JC
J64
Ordering Code
CY7C331-20PC
P21
CY7C331-20WC
W22
CY7C331-25DMB
CY7C331-25HMB
D22
H64
CY7C331-25LMB
L64
Q64
CY7C331-25QMB
120
150
25
30
12
15
25
30
CY7C331-25TMB
174
CY7C331-25WMB
CY7C331-25HC
W22
H64
CY7C331-25JC
J64
CY7C331-.25PC
P21
CY7C331-25WC
W22
CY7C331-30DMB
D22
H64
CY7C331-30HMB
CY7C331-30LMB
CY7C331-30QMB
120
150
35
40
15
20
35
40
174
CY7C331-30WMB
CY7C331-35HC
W22
H64
CY7C331-35JC
J64
CY7C331-35PC
P21
CY7C331-35WC
CY7C331-40DMB
W22
D22
CY7C331-40HMB
H64
CY7C331-40LMB
L64
Q64
CY7C331-40TMB
CY7C331-40WMB
4-124
Commercial
Military
L64
Q64
CY7C331-30TMB
CY7C331-40QMB
Military
174
W22
Commercial
Military
· -;::z
CY7C331
_·~CYPRESS
-=::.F
SEMICONDUcroR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VIL
1,2,3
IJX
1,2,3
Ioz
1,2,3
IcC!
•
II)
C
..J
1,2,3
a.
Switching Characteristics
Parameters
Subgroups
tIS
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tIH
tWH
tWL
teo
tpD
tIAR
tIAS
tpxz
tpzx
tER
tEA
ts
tH
Document #: 38-00066-C
4-125
CY7C332
CYPRESS
SEMICONDUCTOR
Features
• 121/0 macroceUs each having:
- Registered, latched, or transparent
array input
- A choice of two clock sources
- Global or local output enable (OE)
- Up to 19 product terms (PTs) per
output
- Product term (Pf) output polarity
control
• 192 product terms with variable
distribution to macrocells
- An average of 14 PTs per macrocell
sum node
• 1\vo clock inputs with configurable
polarity control
Registered Combinatorial
EPLD
Functional Description
• 13 input macrocells, each having:
- Complementary input
- Register, latch, or transparent
access
-1\vo clock sources
The CY7C332 is a versatile combinatorial
PLD with I/O registers on-board. There
are 25 array inputs; each has a macrocell
that may be configured as a register, latch,
or simple buffer. Outputs have polarity and
three-state control product terms. The allocation ofproductterms to I/O macrocells
is varied so that functions of up to 19 product terms can be accommodated.
• 15 ns tpD max.
• Lowpower
-120 mA typical Icc quiescent
-180 mA max.
- Power-saving "Miser Bit" feature
I/O Resources
• Security fuse
• 28-pin slim-line package; also available in 28-pin PLCC
• UV-erasable and reprogrammable
• Programming and operation 100%
testable
Pins 1 through 7 and 9 through 14 function
as dedicated array inputs. Pins 1 and 2
function as input clocks as well as normal
inputs. Pin 14 functions as a global output
enable as well as a normal input.
Logic Block Diagram
I/O"
vo,o
VOo
19
I.
vo.
I/O,
VOo
Vss
I.
Vss
Vee
1,/CK2
I/O,
VO.
1/00
VOo
loICK1
1/00
C332-1
Selection Guide
Iccl (mA)
Generic Part Number
Commercial
tIS (ns)
tICO/tpD (ns)
Military
Commercial
Military
Commercial
Military
7C332-15
130
7C332-20
120
160
20
23/20
3
4
7C332-25
120
150
25
25
3
4
7C332-30
3
18/15
150
30
4-126
4
~
~~PRESS
~_, ~CONDUCfOR
CY7C332
Pin Configuration
There are 13 input macrocells, corresponding to pins 1 through 7
and 9 through 14. Each macrocell has a clock that is selected to
come from either pin 1 or pin 2 by configuration bit C2. Pins 1 and
2 are clocks as well as normal inputs. There is no C2 configuration
bit for either of these two input macrocells. Macrocells connected
to pins 1 and 2 do not have a clock choice, but each has a clock coming from the other pin.
LCC/PLCC
Top View
g~
~~~~~gg
~
I,
16
Each input macrocell can beeonfigured as a register, latch, orsimpie buffer (transparent path) to the product term array. For a register the configuration bit, CO, is 1 (programmed) and Cl is 1. For a
latch, CO is 0 and Cl is 1. Ifboth CO and C1 are 0 (unprogrammed),
then the macroceJl is completely transparent.
1/0"
va.
1/0,
Vss
Vee
Vss
~
Va.
Va.,
~
19
Configurationbit C3 determines the clock edge on which the register is triggered or the polarity for which the latch is asserted. This
clock polarity can be programmed independently for each input
register. These confirmation options are available on all inputs, includingthose in the I/O macroceJl.
If C3 is 0 (unprogrammed), the clock will be rising-edge triggered
(register mode) or HIGH asserted (latch mode). If C3 is 1 (programmed), the clock will be falling-edge triggered (register mode)
or LOW asserted (latch mode).
0332-2
I/O Resources
(continued)
PIN 1
D----:J---'lD-I"
CKl
I/O Macrocell
PIN1.SO
PIN 2
D----:J--'lD-I"
There are 12 I/O macroceJls corresponding to pins 15 through 20
and23 through 28. Each macroceJlhas a three-state output control
and XOR product term to dynamicaIlycontrol polarity, and a eonfigurablefeedbackpath.
CK2
0332-3
PIN2.S0
Figure 1. CK1 and CK2
Pins 15 through 20 and 23 through 28 are connected to I/O macrocells and may be combinatorial outputs as well as registered or direct inputs.
Input Macrocell
For each I/O macroceJl, the three-state control for the output may
be configured two ways. If the configuration bit, C4, is a 1 (programmed), then the global OE signal is selected. Otherwise, the
OE product term is used.
For each I/O macrocell, the input/feedback path may be configured as a register, latch, or shunt. There are two configuration bits
per I/O macroceJl that configure the feedback path. These are programmedin the same way as for the input macrocells.
For each I/O macroceJl, the input register clock (or Latch Enable)
that is used for the input/feedback path may be selected as pin 1
(select bit, C2, not programmed) or pin 2 (select bit, C2, programmed).
Array Allocation to Output Macrocell
The number of product terms in each output macrocell sumis position dependent. Table 1 summarizes the allocation.
'DIble 1. Product Thrm Allocation in Output Macrocell
C2
co
Cl
0332-4
C3
C2
Cl
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
CO
0
1
1
1
1
1
0
0
0
0
Input Register Option
Combinatorial
Illegal
Registered, CLKl, Rising Edge
Registered, CLK2, Rising Edge
Registered, CLKl, Falling Edge
Registered, CLK2, Falling Edge
Latched, CLKl, LOW 1l:ansparent
Latched, CLK2, LOW 1l:ansparent
Latched, CLK1, HIGH 1l:ansparent
Latched, CLK2, HIGH Transparent
Macrocell
Pin Number
Product Thrms
0
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
20
19
18
17
16
15
9
19
11
Figure 2. Input Macrocell
4-127
11
17
13
15
15
13
17
11
19
9
•
I I)
C
..J
a.
CY7C332
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature .................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied. . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 125 ° C
Supply Vol~ge to Ground Potential
(Pin 22 to Pins 8 and 21) .................. -0.5Vto+7.0V
DCInputVoltage ....................... - 3.0Vto +7.0V
Output Current into Outputs (WW) ................ 12 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
DC ProgrammingVoltage .......................... 13.0V
C4
MACROCELL
INPUT REGISTER
Operating Range
C2
co
C1
Range
Commercial
C332-5
Figure 3. Input MacroceD
Militaryll)
Ambient
Thmperature
O°Cto +75°C
Vee
5V± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameters
Description
Thst Conditions
VOH
Output mGH Voltage
Vcc=Min.,
VIN = Vrn or VIL
VOL
Output WW Voltage
Vcc = Min.,
VIN = Vrn or VIL
Min. Max. Units
IoH = - 3.2 rnA
Commercial
IOH=-2rnA
Military
IoL=12rnA
Commercial
IOL=8rnA
Military
V
2.4
0.5
V
0.8
V
!lA
!lA
Vrn
Input HIGH Voltage
Guaranteed mGH Input, all Inputs(2)
VIL
Input WWVoltage
Guaranteed LOW Input, all Inputs(3)
IIX
Input LeakageCurrent
Vss < VIN < Vee, Vcc = Max.
-10
+10
Ioz
Output LeakageCurrent
Vee = Max., Vss < VOUT < Vcc,
-40
+40
Ise
Output Short Circuit Current
Vee = Max., VOUT = 0.5V(3)
-30
ICCl
Standby Power Supply
Current
Vcc = Max., VIN = GND
Outputs Open
ICC2
Power S~ly. Current at
Frequen 4, 5)
Vcc = Max.
Ou~uts Disabled (In High Z State)
DeVIce O&erating at fMAX
External fMAXl)
Notes:
1. TA is the "instant on" case temperature.
2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. V OUT = O.SV has
been chosen to avoid test problems caused by tester ground degrada.
tion.
4.
5.
4-128
2.2
V
-90
rnA
Commercial
120
rnA
Commercial -15
130
Military
150
Military-20
160
Commercial
180
Military
200
Thsted by periodic sampling of production product.
Refer to Figure 4 configuration 2.
rnA
~
-. -::z
~=CYPRF.SS
CY7C332
~, SEMICONDUCI'OR
Capacitance [6)
Description
Parameters
'lest Conditions
= 2.0Vatf = 1 MHz
= 2.0V at f = 1 MHz
eIN
InputCapacitance
VIN
CoUT
Output Capacitance
VOUT
Max.
Units
10
pF
10
pF
Note:
6. 'Iested initially and after any design or process changes that may affect
these parameters.
•
AC Test Loads and Waveforms
R1 313Q
R1 313Q
OUTP:~ 3=t(4701J
MIL)
I
50 pF
INCWDING _
JIG AND
SCOPE
R2208Q
(3100 MIL)
5 PF
_
INCWDING _
JIG AND
SCOPE
I
(a)
Equivalent to:
ALL INPUT PULSES
OUTP:~ 5 f 1 ( 4 7 0MIL)Q
(b)
3.0V
~
C
..J
R2 208Q
(319Q MIL) GND
_
-
a.
.$. 5
ns
C332-6
THEVENIN EQUIVALENT (Commercial)
OUTPUT
U)
90%
C332-7
Equivalent to:
2.00V = Vthc
THfNENIN EQUIVALENT (Military)
OUTPUT
~
2.02V = Vthm
C332-9
C332-8
Parameter
tpXZ(-)
tpXZ(+)
Vx
1.5V
Output Wtveform-Measurement Level
VOH
2.6V
VOL
tpZX(+)
Vthc
Vx
tpZX(-)
tER(-)
tER(+)
Vthc
1.5V
Vx
VOH
2.6V
VOL
tEA(+)
Vthc
Vx
tEA(-)
Vthc
Vx
0.5V~
0.5V~
0.5V~
O.SV~
O.5V~
0.5V~
O.5V~
O.5V~
~~
7~
Vx
7~
VOH
C332-10
=-11
=-12
~t::
VOL
C332-13
~t::
Vx
C332-14
7~
Vx
7t=
VOH
~t::
(c) 'lest Waveforms and Measurement Levels
4-129
Vx
C332-15
C332-16
VOL
=-17
.r,~DocmR
Switching Characteristics
CY7C332
Over the Operating Range!3]
Commercial
Commercial
-15[7]
Parameters
Description
-20[7]
-25
-20
-25
-30
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tpD
Input to Output
PropagationDelay[8]
15
20
25
20
25
30
ns
tiCO
Input Register Clock to
Output Delay[6]
18
20
25
23
25
30
ns
tIS
Input or Feedback
Set-Up Time to Input
RegisterClock[6]
3
3
3
4
4
4
ns
tm
Input Register Hold
Timel6]
3
3
3
4
4
4
ns
tEA
Input to Output Enable
Delayf9, 10]
20
20
25
25
25
30
ns
tER
Input to Output Disable
Delayf9, 10]
20
20
25
25
25
30
ns
tpzx
Pin 14 Enable to Output
Enable Delayl9, 11]
15
15
20
20
20
25
ns
tpxz
Pin 14 Disable to Output Disable Delay[9, 11]
15
15
20
20
20
25
ns
tWH
Input Clock Width
High[4,6]
9
10
10
10
10
12
ns
Input Clock Width
9
10
10
10
10
12
ns
tlOH
Output Data Stable
Time from Input RegisterClockInput[6,7]
3
3
3
3
4
4
ns
tlOH-tm
Output Data Stable
Tune This Device Minus
IJP Reg Hold Time
Same Device[7, 12, 13]
0
0
0
0
0
0
ns
tlOH tm 33x
Output Data Stable
Tune Minus IJP Reg
Hold Time 7C330 and
7C332Device[7,14]
0
0
0
0
0
0
ns
tpE
External Clock Period
(tIeD + t18)[6]
21
23
28
27
29
34
ns
fMAXI
Maximum External
47.6
43.4
35.7
37
34.4
29.4
MHz
55.5
50.0
40.0
50.0
40.0
33.3
MHz
twL
Lowl4,6]
OperatingFre~uency
(1!(tiCO
fMAX
+ tIS» 6]
Maximum Frequency
Data Path[6]
Notes:
7. Preliminaryspecifications.
8. Refer to Figure 3 configuration 1.
9. Part (a) ofAClest Loads and Waveforms is used for all parameters
except tEA. tER, tpzx, and t!'XL which use part (b). Part (c) shows test
waveform and measurement reference levels.
10. Refer to Figure 4 configuration 3.
11. Refer to Figure 4 configuration 4.
12. Refer to Figure 4 configuration 5.
13. This specification is intended to guarantee that configuration 5 ofFigUTe 4 with input registered feedback can be operated with all inputregister clocks controlled by the same source. These parameters are
tested by periodic sampling of production product.
14. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C332. This
specificationis met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product.
4-130
CY7C332
CONFIGURATION 1
PIN
~-------t~==~
INPUT OR I/O PIN
INPUT REGISTER
CONFIGURATION 2
CLOCK 1 OR2
II)
I---------t~==~ PRODUCT
TERM
CONFIGURATION 3
9a.
ARRAY
INPUT OR VO PIN
VOPIN
CONAGURATION 4
INPUT OR VO PIN
INPUT REGISTER
DATA
INPUT
CONFIGURATION 5
PRODUCT
TERM
NmAY
CLDCK10R2
DATA
OUTPUT
CLOCK 1 OR2
C332-18
Figure 4. Timing Configurations
Switching Waveforms
INPUT OR
I/OPINI15]
INPUT
CLOCKI16]
PIN 14
AS~
OUTPUT
Notes:
15. Because OE can be controlled by the DE product term, input signal
polarity for control of DE can be of either polarity. Internally the
product term DE signal is active IDGH.
16. Sincetheinputregisterclockpolarityisprogrammable, the input clock
may be rising- or falling-edge triggered.
4-131
2~
•
~- CYPRESS
S~OONOOC~ ~====================================~CY~7~C3~3~2~
CY7C332 Logic Diagram (Upper HalO
m1 ~1--I;'~~1
8
3: II
l!:=t ~
IL9:600~IIIIIIIIIIIIIIIILE97110~)(~WBOJ'0)
L9650
t
(CO,1.3)
9
m-4
L9603 ~.-
~
L972H~'1
L9655
_3
(CO.I.3)
(CO.. 4)
}-rm
Ft'---l";;;;;j.......
119
III--Il1-b. . -~_~
~
16 ~
L9606 L1600~II~IIIIIIIIIIIIIIILL9t742!t(~WB3~2'44)
L9660
IItJ 'l--t-so=mtttt!::itt!1
;r
L9755 CMB45
.
(CO •• 3)
.11
63)
L9665
(CO.. ")
(CO •• 3)
117
~~J-ml
~'~·~~~lW
L961" .J'1:;200JlllliIIIIIIIIIIILt977:4~~~~~"78)
~\.~
~L
3) ~L39"'50 IIIIIIEL97893ICWB79
. 95) L9675
(co.. 3)
11
113
L.:.11L9618
(CO..
1
~
L9670
...(co.. ")
(CO.. ,,)
115
r~):-€l
...;,r'
I......- - - - - - - - - - TO
LOWER SEenON _ _ _ _ _ _ _ _ .
4-132
II
~
~-CYPRESS
~_.'I
CY7C332
SEMICONDUCTOR
CY7C332 Logic Diagram (Lower Half)
r - - - - - - - - - - - - T O UPPER SECnOH - - - - - - - - - - - ,
~
L9622 ..
(CO •• l)
~
L9806(WB96 .• 112)
l====I
115
~
1-1
..
l-m1
10-
~650
C
L9685
(CO•••)
~ }--mJ
III
,
~
't2j ~400
L98lB (WBI28.. 1.6)
L
(CO•• l)
17
~~
L9857(~a:.7.
L7l50
(CO•• l)
,
159)
6
11 '
L9690
(CO •••)
}--{ill
L9695
(co•••)
}--1m
~
IL9870(WBI60 •.. 180)
t;ooo
(CO •• l)
L9700
(co•.•)
1====1
19
~
}-lEI
,
~ ~50
LI891 (WBt81 , .191)
9
L9646
(CO•• l)
~Y
."..
4-133
---
lkI
(CO•• l)
•
I I)
'L982l (WB11 l. 127)
(co•• l)
mH
L9618 ..
L9680
(CO•••)
L9705
(CO•••)
TT}--{ill
....I
a..
CY7C332
Ordering Information
Iccl (max)
tIcoItpo (ns)
tIS (ns)
tili (ns)
120
18/15
3
3
120
160
120
150
150
20
23/20
25
25
30
3
4
3
4
4
3
4
3
4
4
CY7C332-15HC
Package
1YPe
H64
CY7C332-15JC
J64
Ordering Code
CY7C332-15PC
P21
CY7C332-15WC
W22
CY7C332-20HC
H64
CY7C332-2OJC
J64
CY7C332-20PC
P21
CY7C332-20WC
W22
CY7C332-20DMB
D22
CY7C332-20HMB
H64
CY7C332-20LMB
L64
CY7C332-200MB
064
CY7C332- 20TMB
T74
CY7C332-20WMB
W22
CY7C332-25HC
H64
CY7C332-25JC
J64
CY7C332-25PC
P21
CY7C332-25WC
W22
CY7C332-25DMB
D22
CY7C332-25HMB
H64
CY7C332- 25LMB
L64
CY7C332- 250MB
CY7C332-25TMB
064
T74
CY7C332-25WMB
W22
CY7C332-30DMB
D22
CY7C332-30HMB
H64
CY7C332-30LMB
L64
CY7C332-300MB
064
CY7C332- 30TMB
T74
CY7C332-30WMB
W22
4-134
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
·-4CYPRESS
=
='=
-
F
CY7C332
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VIL
1,2,3
IIX
1,2,3
Ioz
1,2,3
ICCI
1,2,3
•
1/1
C
..J
a..
Switching Characteristics
Parameters
Subgroups
tIS
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tIH
tWH
tWL
tICO
tpD
tpxz
tpzx
tER
tEA
Document #: 38-00067-C
4-135
CY7B333
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 161/0 macrocells, eacb baving:
-Cboice oCcombinatorial or
registered output
- Registers programmable to T.type
or Ootype
- Emulation oC RS and JK flip-flop
- Independent (product term) output
enable
- Syncbronous clock input and product term controlled asynchronous
reset product term Cor each bank oC
8 macrocells
- Programmable output polarity control
- Up to 8 macrocell registers may be
buried wbile preserving the use oC
tbe associated pins as inputs and
witbout using additional product
terms
- 8 product terms per output
• 146 product terms total
• 2 clock inputs that can also be logic
inputs
• Higb performance
-10 ns maximum propagation delay
General-Purpose
Synchronous BiCMOS PLD
• Higb noise immunity
• Advanced BieMOS tecbnology
• Availahle in 28·pin, JOO-mil POIP,
cerOIP, PLCC, and LCC packages
• Programmable security bit
Functional Description
The CY7B333 is a 28-pin, general-purpose, high-performance PLD with seven
dedicated inputs, two clock inputs, and
sixteen I/O macrocells (two banks of eight
I/O macrocells). These are connected to a
logic array of 146 product terms and 50
input terms. The CY7C333 has one Vcc
and two Vss pins located at pins 22, 21,
and 8, respectively for improved noise immunity.
The CY7B333 uses an 8-wide sum of
product terms distribution scheme. Each
one of the 16 I/O macrocells has as its input an 8-wide sum of product terms.
There are two asychronous reset product
terms (one product term per bank of eight
I/O macrocells).
CLKl provides the synchronous clock input for one bank of macrocells, and CLK2
provides the synchronous clock input for
the other bank of macrocells. If no synchronous clock inputs are needed, the
CLKl and CLK2 inputs can function as
standard logic inputs. Output enable is
controlled with one dedicated product
term per macrocell. An asynchronous reset product term is provided for each
bank of macrocells.
Each macrocell has a register that can be
programmed to be a T-type or D-type.
RS-type and JK-type registers can be
emulated. The macrocell architecture also
allows up to one half of the macrocell registers to be buried without sacrificing any
I/O pins and without using additional
product terms.
The CY7B333 is available in a wide variety of packages including 28-pin, JOO-mil
plastic DIP and windowed ceramic DIP,
28-pin square plastic leaded chip carrier
(PLCC), 28-pin windowed square Jleaded hermetic ceramic chip opaque carrier (HLCC) and, for military only, standard windowed and opaque ceramic leadless chip carrier (LCC).
Logic Block Diagram
I/O
VCLK2
I/O
I/O
I/O
I/O
Vss
vo
vo
I/O
va
vo
vo
I/O
I/O
I/O
I/CLK1
vo
I
8333-1
4-136
=:;~~
PRELIMINARY
CY7B333
'SEMICOIDUCTOR
Selection Guide
ICC! (rnA)
Commercial
Militaty
Commercial
Militaty
Commercial
Militaty
Commercial
Militaty
tpD (ns)
t" (ns)
teOl (ns)
7B333-10
7B333-12
150
150
170
12
12
10
Macrocell Description
The control bits in each macroceU allow independant selection of
combinatorial or registered output and polarity. There are five
configuration bits (Co-~) in each 1/0 macrocell. Each I/O
macrocell has one register that may be configured by the de·dicated configuration bit, Co, as T-type or D-type register. The Ttype register may also be used to implement an RS or JK register.
Cl controls whether the output is registered or combinatorial. C2
controls output polarity. The clock sources for the two groups of
eight registers on the left and right side of the package are CLKI
and CLK2, respectively.
The one-of-three feedback multiplexer in the macrocell allows a
choice of three feedback sources: (1) register output, (2) macrocell I/O pin, and (3) adjacent macrocell I/O pin. This is done by
programming the C3 and C! configuratiojn bits. The cIloice of
either of two 1/0 pins as input source allows registers to be buried while preserving the use of the associated I/O pin as an input by routing of the pin to the array through adjacent unused
macrocell-feedback multiplexer.
8
10
8
10
10
10
C3
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
C2
0
0
0
1
1
1
Cl
Co
0
1
1
0
1
1
X
X
0
0
0
1
1
1
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
X
0
1
X
0
1
X
X
0
1
1
1
X
0
1
X
0
1
X
0
1
170
15
12
12
This approach allows up to one half of the registers to be buried
without sacrifice of any I/O pins and is accomplished with no increase in array size or the accompanying degradation of die cost
or speed performance.
The three-state output buffer of each macrocell is controlled by
an individual product term.
The CY7B333 has a single asynchronous reset product term for
each group of eight macrocells.
Control Bit Description
Control bit Co in the I/O macrocell selects the type of the output
register. If Co = 0 (default) then the output register will be D
type. On the other hand, setting Co = 1 will configure aT-type
register. Cl controls whether the input is registered or combinatorial. C2 controls output polarity. C3 and C! select feedback
from register output, macrocell I/O pin, or adjacent macrocell
I/O pin. The default comfiguration (~, C3, C2, Ch Co = 0) is an
inverted combinational output with I/O pin feedback. Table 1 describes the various macrocell configurations and the corresponding values of ~ -Co.
Table 1. Macrocell Configuration Bits
C4
7B333-1S
Configuration
Combinatorial, Inverted, I/O Feedback
D Register, Inverted, I/O Feedback
T Register, Inverted, I/O Feedback
Combinatorial, Noninverted, 1/0 Feedback
D Register, Noninverted, I/O Feedback
T Register, Noninverted, 1/0 Feedback
Illegal
Combinatorial, Inverted, Registered Feedback
D Register, Inverted, Registered Feedback
T Register, Inverted, Registered Feedback
Combinatorial, Noninverted, Registered Feedback
D Register, Noninverted, Registered Feedback
T Register, Noninverted, Registered Feedback
Combinatorial, Inverted, Adjacent I/O Feedback
D Register, Inverted, Adjacent I/O Feedback
T Register, Inverted, Adjacent 1/0 Feedback
Combinatorial, Noninverted, Adjacent I/O Feedback
D Register, Noninverted, Adjacent I/O Feedback
T Register, Noninverted, Adjacent I/O Feedback
4-137
•
PRELIMINARY
CY7B333
Maximum Ratings
(Above which the useful life maybe impaired. Foruser guidelines,
not tested.)
Storage Thmperature ......••....•.... - 6S·C to +lS0·C
Ambient Thmperature with
Power Applied ......•....•....•..... - SS·Cto +l25·C
Supply Voltage to Ground Potential ••.• '" - O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State ..••...••••..••••.••• - O.5V to Vcc Max.
DC Input Voltage ................ - O.5V to (Vee + O.SV)
DC Input Current. . . . . . . . . . . . . . . . . .. - 30 rnA to + S rnA
(except during programming)
DC Program Voltage ....................•......•.. 9.5V
Static Discharge Voltage .....•.....•............ >2001 V
(per MIL-STD-883, Method 301S)
Operating Range
Ambient
Temperature
Range
Commercial
Military!l)
Yee
O·Cto +70·C
- SS·Cto +l25·C
SV±S%
SV± 10%
Electrical Characteristics Over the Operating Range
Parameter
Min.
Test Conditions
Description
= Min.,
= VIHor VIL
Vee = Min.,
VIN = VIHor VIL
IOH
= -4rnA
IOL
= 4mA
VOH
Output mGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for All Inputs
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs(2)
IJX
Input Leakage Current
Ioz
Output Leakage Current
Isc
Output Short Circuit
Currentl4)
= Max.
= Max., Vss~ VOUT~ Vee
Vee = Max., VOUT = 0.5V(3)
ICCl
Standby Power Supply
Current
Vee
Power Sue/l~ Current at
Frequency 4 )
Vee Max., Outputs Disabled (in High Z
State), Device Operating at fMAJo
ICC2
Vee
VIN
Max.
Units
2.4
V
0.5
V
2.2
V
0.8
V
Vss ~ YIN ~ Vcc, Vee
-250
50
Vee
-100
100
JIA
JIA
-30
-130
rnA
rnA
= Max., YIH = GND, Outputs Open
=
Com'l
150
Mil
170
Com'l
170
Mil
190
rnA
Capacitance(4)
Parameters
Description
CiN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
= 2.0V at f = 1 MHz
VOUT = 20Vatf = 1 MHz
YIN
Notes:
1. tA is the "instant on" case temperature.
2. Minimum DC input voltage is -0.3 volts. During transitions, the inputs may undershoot to -2.0 volts for periods less than 20 ns.
3. Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second yOlTl' = O.SV has
been chosen to avoid test problems caused by ground degradation.
4.
Max.
Units
10
pF
10
pF
Thsted initially and after any design or process changes that may affect
these parameters.
S. Measured with the device configured as a 16-bit counter.
4-138
PRELIMINARY
CY7B333
AC Test Loads and Waveforms
+5V
O~:"pFf
OV
I:::
I
OUTPUTO
C= 35PF
R=237Q
y"
1
I
T
OUTPUTO
VTH
= 1.45V
C
I
= 5PFT
ov
OV
(b) Th~venin Eqoivalent (Load 1)
(a) Nonnal Load (Load 1)
6333-8
8333-7
R=237Q
OV
(c) Three-state Delay Load (Load 2)
8333-9
II
",
C
..J
All INPUT PULSES
3.0V ~lOs.:'"
Jt::90%
10%
GND
S3M
a.
~
S3M
(d)
Parameter
Vx
tER( )
1.5V
tER(+)
2.6V
tEA(+)
VTH
tEA(-)
VTH
8333-2
Output WaveCorm-Measurement Level
VOH O.5V
:
VOL
O.5V:
Vx
O.5V:
Vx
O.5V
:
j:-
Vx
~
Vx
I:
VOH
j:-
6333 3
8333-4
8333-5
VOL
6333-6
Switching Waveform
----rJ'\..
INPUTS I/O.
REGISTERED
FEEDBACK
SYNCHRONOUS - - -......,
PRESET
14--1---1
CP - - - - - - . 1 1
ASYNCHRONOUS _ _ _ _ _ _ _ _~~---~-"I
RESET
REGISTERED ------""""\:"K""l"'- ~--_+-~1M\o,.
OUTPUTS _ _ _ _ _ _-'-l1Ul'
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _L.K.V
8333-10
4-139
PRELIMINARY
CY78333
Power- up Reset Waveform
POWER SUPPLY
VOLTAGE
Vee
90%
10%
tpR
REGISTERED
ACTIVE LOW
OUTPUTS
xxx XXXXX'
~
_\\
CLOCK
twL
SWI'tCh'IDa Charact'
erls f ICS [6]
78333-10
Parameters
tpD
Description
Input to Output Propagation DelayFJ
tEA
Input to Output Enable Delay
Com'l
78333-12
Min. Max. Min.
10
Mil
tER
Com'l
Mil
Com'l
Input to Output Disable DelayLHJ
12
12
Mil
tem
Clock to Output DelayllJ
Com'l
8
Mil
te02
toH
ts
tH
Qock to Registered Feedback to Combinatorial
Output Delay[4,9]
Output Data Stable Time from Input Clock
Input or Feedback Set-Up Time
Input Hold Time
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
17
tWH
tWL
fMAXI
fMAX2
fMAlO
tCF
tAW
External Clock Period (tem
+ tS)LIUJ
Clock Width HIGHI4J
CLock Width LOWL"!
External Maximum Frequency (1/(tem
+ tS»LlU,llJ
Data Path Maximum Frequency (1/(tWH + twL»14,lUJ
Internal Feedback Maximum Frequency
(1/(teF + tS»[4,12]
Register Clock to Feedback Inputll~J
Asynchronous Reset Widthl4 J
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
1
8
0
16
tAP
Asynchronous Reset Recovery Timd4]
Asynchronous Reset to Registered Output Delay
Com'l
Mil
Com'l
6
625
Power-Up Reset TimeL4,14J
Com'l
Mil
4-140
ns
16
ns
12
25
ns
1
ns
12
ns
0
ns
24
ns
10
ns
10
MHz
50
50
55.5
55.5
58
58
83.3
80
5
8
41.6
MHz
50
MHz
48
10
12
1.0
ns
7
7
9
ns
10
10
12
12
Mil
tpR
ns
16
ns
9
9
9
9
6
Units
ns
15
20
1
1
10
10
0
0
20
20
Mil
tAR
78333-15
Max.
Min.
20
Mil
tp
Max.
12
12
14
14
14
14
10
10
12
ns
15
ns
14
14
1.0
17
loU
loU
J.LS
PRELIMINARY
CY7B333
Programming
The 7B333 canbeprogrammedusing the QuickPro II programmer
available from Cypress Semiconductor and also with Data I/O,
Logical Devices, STAG, and other programmers. Please contact
your local Cypress representative for further information.
Synchronous I/O Macrocell
GLOBAL SYNCHRONOUS
CLOCK (ONE PIN PER
EIGHT MACROCELLS
FROM 1/0 PIN
OF ADJACENT MACROCELL
OUTPUT ENABLE PRODUCT TERM
(I)
C1
~
"
./
L
f
0
QI-
D
D(O) OR
T(1) TYPE
CLK
1
'---
C
C2
...I
a.
rf?~~
110
PIN
0
R
I
10
* tL
FEEDBACK
MUX
)
00
11
110 MACROCELL ON DIP PINS 3 THROUGH 7, 9 THROUGH 11,
18 THROUGH 20, AND 23 THROUGH 27
8333-11
GLOBALASYNCHRONOUS
RESET (ONE PIN PER
EIGHT MACROCELLS
TO FEEDBACK MUX
OF ADJACENT MACROCELL
Notes:
6. AC test load (Load 1) used for all parameters except where noted.
7.
specification is guaranteed for all devices outputs changing state
1U a gtven access cycle.
8. This parameter is measured as the time after the output disable input
that the previous output data state remains stable on the output. This
delay is measured to the point at which aprevious HIGH level has fallen 100.5 volts belowVoHmin. ora previous WWlevel has risen to 0.5
volts above VOL max. (See Load 2.)
9. Delay measured from clock of registered macrocell to feedback
throujlh logic array to second macrocell output configured as a combinatorial path.
:nus
10. This is a calculated parameter and is not directly tested.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.
13. This parameter is calculated from the clock period at fMAX internal
(fMAlO) as measured (see Note 7) minus ts and is not directly tested.
14. This spec indicates the guaranteed maximum frequency at which a
state machine configuration with internal-only feedback can operate.
4-141
~:~PR5S
PRELIMINARY
CY7B333
~F SEMICONDUCTOR
Block Diagram
I/O
I/O
1/0
I/O
I/O
I/O
1/0
I/O
8333-12
4-142
g
:;>CYPRFSS
--==-F
PRELIMINARY
CY7B333
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VJH
VIL
Ilx
IOZ
ICCl
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
II
(II
C
..J
a.
Switching Characteristics
Parameters
Subgroups
tpo
tCOl
tEA
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
tER
tOH
ts
tH
tCF
Ordering Information
ICC
tPD
CMAX
(mA)
(ns)
(MHz)
150
10
83.3
12
170
12
15
55.5
55.5
50
Ordering Code
PAL7B333-10DC
PAL7B333-1OJC
PAL7B333-10PC
PAL7B333-12DC
PAL7B333-12JC
PAL7B333-12PC
PAL7B333-12DMB
Psekage
lYPe
D22
Operating
Range
Commercial
J64
P21
D22
Commercial
J64
P21
D22
PAL7B333-12~
L64
PAL7B333-15DMB
D22
PAL7B333-15~
L64
Document #: 38-00099-B
4-143
Military
Military
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 83-MHz registered pipelined
operation
• 1Welve I/O macrocells, each having:
- Registered, three-state I/O pins
- Input and output register clock select multiplexer
- Feed back multiplexer
- Output enable (OE) multiplexer
• Bypass on input and output registers
• All twelve macroccll state registers
can be hidden
• User contigurable I/O macroeells to
implement JK or RS nip-nops and T
or D registers
• Input multiplexer per pair of I/O rnacrocells allows I/O pin associated with
a hidden macrocell state register to be
saved for use as an input
• Four dedicated hidden registers
• 1Welve dedicated registered inputs
with individually programmable bypass option
CY7C335
Universal Synchronous EPLD
• Four separate clocks-two input
clocks, two output clocks
• Common (pin 14-controlled) or
product term -controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macroeells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
- 2-ns input set-up and 10-ns output
register clock to output
-12-ns input register clock to state
register clock
• 28-pin, 300-mil DIP, LCC, PLCC
• Erasable and reprogrammable
• Programmable security bit
Functional Description
TheCY7C335 is ahigh-performance, erasable, programmable logic device (EPLD)
whose architecture has been optimized to
enable the user to easily and efficiently
construct very high performance state machines.
The architecture of the CY7C335, consisting of the user-configurable output
macrocell, bidireetionall/O capability, input registers, and three separate clocks,
enables the user to design highperformance state machines that can
communicate either with each other or
with microprocessors over bidirectional
parallel buses of user-definable widths.
The four clocks permit independent, synchronous state machines to be synchronized to each other.
The user-configurable macrocells enable
the designer to designate JK-, RS-, T-, or
D-typedevices so that the number of produet terms required to implement the logic
isminimized.
TheCY7C335 is available in a wide variety
ofpackages including 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and LeCs.
Logic Block Diagram
vo"
vo,o
vo"
1/0"
I.
VS.
va.
VS.
1,/ClK3
Vee
4-144
vo.
IIOs
fo/CLK2
vo,
CLK'
1100
C335-1
PRELIMINARY
CY7C335
Pin Configurations
PLCC
Top View
LCC
Top View
5
6
7
4 3 2:1; 282728
25
23
22
a
9
10
11
va.
va.
va.
24
Vee
21
20
Vss
19
12131415161718
I/o,
va,
(I)
C33&-2
Q
C335-3
...I
a.
Selection Guide
Maximum Operating Frequency (MHz)
Commercial
Military
ICCI (rnA)
Commercial
Militaty
CY7C33S-83
83.3
140
CY7C33S-66
66.6
66.6
140
160
CY7C33S-S0
50
CY7C33S-40
50
140
160
40.0
160
Architecture Configuration Bits
The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in 1bb1e 1.
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit
Number of Bits
Value
Function
CO
Output Enable
SelectMUX
12 Bits, 1 Per
I/O Macrocell
O-Virgin State
1-Programmed
Output Enable Controlled by Pin 14
C1
State Register
Feed Back MUX
12 Bits, 1 Per
I/O Macrocell
O-Vrrgin State
State Register Output is Fed Back to Input Array
1-Programmed
I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array
I/O Macrocell
Input Register
Clock Select
MUX
12 Bits, 1 Per
I/O Macrocell
O-Vrrgin State
ICLK1 Controls the Input Register I/O Macrocell
Input Register Clock Input
1-Programmed
ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input
C3
Input Register
BypassMUXI/O Macrocell
12 Bits, 1 Per
I/O Macrocell
O-Vrrgin State
Selects Input to Feedback MUX from Input
Register
1-Programmed
Selects Input to Feedback MUX from I/O pin
C4
Output Register
Bypass MUX
12 Bits, 1 Per
I/O Macrocell
0-Virgin State
Selects Output from the State Register
1-Programmed
Selects Output from the Array, Bypassing the State
Register
State Clock MUX
16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell
O-Vrrgin State
State Clock 1 Controls the State Register
1-Programmed
State Clock 2 Controls the State Register
12 Bits, 1 Per
Dedicated Input
Cell
O-Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
1-Programmed
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
C2
C5
C6
Dedicated Input
Register Clock
SelectMUX
4-145
Output Enable Controlled by Product 'Thrm
PRELIMINARY
CY7C335
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit
Number of Bits
InputR~r
Function
Value
12 Bits, 1 Per
Dedicated Input
Cell
O-Vrrgin State
Selects Input to Array from Input Register
1-Programmed
Selects Input to Array from Input Pin
ICLK2 Select
MUX
1 Bit
O-Virgin State
Input Oock 2 Controlled by Pin 2
1-Programmed
Input Oock 2 Controlled by Pin 3
ICLKl Select
MUX
1 Bit
O-Vrrgin State
Input Oock 1 Controlled by Pin 2
C10
SCLK2 Select
MUX
ex
I/O Macrocell
PairInM&c
Select
C7
Bypass
-
Input Cell
C8
C9
(11-16)
1-Programmed
Input Oock 1 Controlled by Pin 1
1 Bit
0-Virgin State
State Oock 2 Grounded
1-Programmed
State Oock 2 Controlled by Pin 3
6 Bits,1 Per
I/O Macrocell
Pair
0-Vrrgin State
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
1-Programmed
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
1
-
INPUT REGISTER
INPUT
PIN
IClK1
IClK2
0
Or-INPUT
CLOCK r1 MUX
0
Q
INPUT
REG
BYPASS
MUX
....
T
>
C6
C335-4
Figure 1. CY7C335 Input Macrocell
4-146
TOARRAY
... :t>
PRELIMINARY
CX (11 - 16)
FROM ADJACENT MACROCELL
Figure 2. CY7C335 Input/Output Macrocell
4-147
CY7C335
PRELIMINARY
SET PRODUCT TERM
S
)---1 D
Q
I
C5
RESET PRODUCT TERM
C335-6
Figure 3. CY7C335 Hidden Macrocell
SCLK2 TO OUTPllf MACROCELLS AND HIDDEN MACROCELLS
PIN 1
ICLKI 1CLK2
SCLKI TO OUTPllf MACROCELLS AND HIDDEN
MACROCELLS
PIN 2
co
PIN 3
C335-7
Figure 4. CY7C335 Input Clocking Scheme
4-148
CY7C335
PRELIMINARY
CY7C33S
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Thmperature .•............... - 65·C to +150·C
Ambient Thmperature with
Power Applied ...................... - 55·C to +125·C
Supply Voltage to Ground Potential
(Pm 22 to Pins S and 21) ..............•. - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (Low) ............... 12 mA
Static Discharge Voltage ......•..........•..... > 2001 V
(per MIL-STD·S83, Method 3015)
Latch·Up Current ........................... > 200 rnA
DC Programming Voltage ...........••........•... 13.0V
Operating Range
Ambient
Temperature
Range
O·Cto +75·C
Vee
5V± 10%
- 40·C to +S5·C
5V± 10%
- 55·Cto +l25°C
5V± 10%
Commercial
Industrial
MilitaryllJ
Electrical Characteristics Over the Operating Range(2)
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
'lest Conditions
Vee - Min.,
VIN = VlH or VIL
Vee = Min.,
VIN = VIH or VIL
Min.
IOH - -3.2mA
Com'l
IOH- -2mA
Mil/Ind
IOL= 12mA
Com'l
VlH
Input HIGH Level
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputsl']
IJX
Input Leakage Current
VSSSYINS Vee, Vee = Max.
Ioz
Output Leakage Current
Isc
Output Short Circuit Current
ICCl
Standby Power
Supply Current
Vee - Max., VIN = GND
Outputs Open
Power Suppl~ Current
at Frequency S, 6)
Vee- Max.,
Ouil>uts Disabled (in High Z State
DevIce Operating at !MAx Externa (fMAXS)
ICCl
I'
Units
V
V
0.5
Mil/Ind
IOL - SmA
Guaranteed Input Logical mGH Voltage for All Inputsl"]
Vee = Max., VssS VOUTS Vee
Vee = Max., VOUT = 0.5VL4,4]
Max.
2.4
2.2
V
O.S
V
-10
10
-40
40
fAA
fAA
-30
-90
mA
Com'l
140
mA
MilJlnd
160
mA
Com'l
1S0
mA
MilJlnd
200
rnA
Capacitance(4)
Max.
Units
CIN
Parameters
Input Capacitance
Description
VIN = 2.0V@f= 1 MHz
'lest Conditions
10
CoUT
Output Capacitance
VOlJT = 2.0V@ f = 1 MHz
10
pF
pF
Notes:
1. tA is the "instant on" case temperature.
2. See the Last page of this specification for Group Asubgroup testing in·
formation.
3. These are absolute values with respect to device ground and all over·
shoots due to system or tester noise are ineLuded.
4.
5.
6.
4-149
Min.
Not more than one output shoWd be tested at a time. Duration of the
short circuit should not be more th~n one second. VOUT O.5V has
been chosen to avoid test problems caused by ground degradation.
Thsted initially and after any design or process changes that may affect
these parameters.
This parameter is sample tested periodically
=
•
=iil~
PRELIMINARY
CY7C335
AC Test Loads and Waveforms (Commercial)
R13130
OUTP~~~700Mimnd)
I
R22080
(3190 MiVlnd)
50 pF
INCLUDING
JIG AND
':"
SCOPE
ALL INPUT PULSES
3.0V ---1"9--0%~----~
.s3 ns
C335-8
(a)
=
I·...
1
R
OUTPUTO
C = 50 pF
GND
':"
r
OUTPUTO
VTH =2.00v
(2.02V Mil)
C= 5PF
ov
C335-9
Vx
tpxz(-)
1.5V
tPXZ(+)
2.6V
tpzx (+)
Vth
tpzx (-)
Vth
tcERH
l.5V
tcER(+)
2.6V
tcEA (+)
Vth
tcEA(-)
Vth
Vx
OV
C335-10
(d) Three-state Delay Load (Load 2)
(e) Thevenln Equivalent (Load 1)
Parameter
I ... 1
T T
R = 1250 (1900 Mil)
1250 (1900 MiQ
T
C335-11
(b)
Output Waveform-Measurement Level
VOH
O.5V
VOL
O.5V
Vx
Vx
VOH
t
t
0.5V
O.5V
0.5V
~
t
~t=
j
O.5V
Vx
t=
t:=
t:=
t=
t
O.5V
VOL
Vx
t
O.5V
j
Figure S. Test Waveforms
4-150
t=
t=
t=
Vx
0335-12
Vx
0335-13
VOH
C335-14
VOL
0335 15
Vx
0335-16
Vx
0335-17
VOH
0335-18
VOL
0335-19
CY7C335
PRELIMINARY
AC Characteristics (Commercial)
7C335-50
7C335-83 I 7C335-66
Parameter
Description
Min.
Max.
Max.I Min.
Min.
Max.
Units
25
ns
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Combinatorial Mode Parameters
tpD
Input to Output Propagation Delay
Input Registered Mode Parameters
15
tiCO
Input Register Clock to Output Delay
tIOH
tIS
Output Data Stable Thne from Input Oock
Input or Feedback Set-Up Tune from Input Clock
teEA
teER
tpzx
Input Clock to Output Enabled
Input Clock to Output Disabled
Pin 14 Enable to Output Enabled
Pin 14 Disable to Output Enabled
Input to Output Enable
Input to Output Disable
tpxz
tEA
tER
t/H
20
I
20
18
3
2
3
2
3
3
17
15
12
12
15
15
tWH
tWL
Input Register Hold Tune from Input Oock
Input and Output Oock Width HIGH[4]
Input and Output Oock Width LOW[4]
fMAXI
MaximumFrequen~withExternalFeedbackinIn~utRegistered
Mode (Lower of 11 tlCO + tiS) & lI(twL + !wID)~]
20
20
15
15
20
20
25
25
20
20
25
25
2
2
3
5
6
8
5
50
6
45.4
8
35.7
MHz
fMAX2
Maximum Frequency DatapathinInput~teredMode (Lowest of (1/(tlco). 1/(tWH + twLJ. l/(tls + tl [4]
55.5
50
40
MHz
tIOH - t/H
33x
Output Data Stable from Input Clock Minus Input Register Hold
Timefor7C330.7C332.and7C335
0
0
0
ns
Output Registered Mode Parameters
Output Register Clock to Output Delay
Output Data Stable Time from Output Clock
toH
0
Maximum Frequency with External Feedback in Oumut Registered Mode (Lower of 1/(tco + ts) & lI(!wL + tWID [4]
50
0
41.6
ns
ns
ns
ns
33.3
MHz
Maximum Frequency Data Path in Output Re~tered Mode
(Lowest of lI(teo). 1/(tWL + twID. 1/(ts + tH»
toH - t/H Output Data Stable from Output Clock Minus Input Register
33x
Hold Time for 7C330. 7C332. and 7C335[7]
Pipelined Mode Parameters
100
83.3
62.5
MHz
0
0
0
ns
12
83.3
15
66.6
20
50
MHz
ts
tH
fMAlO
Output Register Input Set-Up Time to Output Clock
Output Register Input Hold Time to Output Clock
fMAX4
tcos
fMAXS
12
10
teo
Input Clock to Output Clock
Maximum Frequency Pipelined Mode (Lowest of lI(teos).
1/(tco). 1/(tco + tiS). lI(twL + tWH»[4]
Power-Up Reset Parameters
Power-Up Reset Timel4•8]
tpOR
Notes:
7. This specification is intended 10 guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C33S. This
specification is met for the devices operating at the same ambienttemperature and at the same power supply voltage.
8. This part has been desigued with the capability to reset during system
power-up. Following power-up. the input and output registers will be
reset to a logic LOW state. The output state will depend on how the
4-151
I
15
2
10
2
12
2
15
0
I
1
I
I
1
I
ns
I 1 If.IS
array is programmed. Th insure proper operation, the rise in Vcc must
be monotonic and the timing constraints depicted in Power-Up Reset
Waveforms must be satisfied The clock signalinput must be in a valid
LOW state (VIN less than O.8V) or a valid mGR state (VIN greater
than 2.2V) prior to occurrence. After the delay (tPR) has been observed. normal operation can begin.
II
fI)
C
..J
Q.
PRELIMINARY
CY7C335
AC Characteristics (Military/lndustrial)
I
Parameter
Description
7C335-66
Min.
7C335-50 I 7C335-40 I
Max.
Min. I Max. I Min.
Max.I Units
Combinatorial Mode Parameters
I
Input to Output Propagation Delay
tpD
Input Registered Mode Parameters
tl(;o
Input Register Clock to Output Delay
tlOH
tiS
Output Data Stable T1I1le from Input Clock
Input or Feedback Set-Up Thne from Input Clock
20
I 25
23
I
25
3
3
3
3
30
I ns
30
ns
ns
3
4
ns
teEA
Input Clock to Output Enabled
20
teER
tpzx
Input Clock to Output Disabled
20
25
25
30
30
ns
Pin 14 Enable to Output Enabled
15
20
30
ns
tpxz
Pin 14 Disable to Output Enabled
15
20
30
ns
tEA
Input to Ouiput Enable
20
25
30
ns
tER
Input to Output Disable
20
25
30
ns
tIH
Input Register Hold T1I1le from Input Clock
Input and Output Clock Width HIGH(4]
tWH
ns
3
3
4
us
6
8
10
ns
6
38.4
8
35.7
10
29.4
ns
MHz
tWL
Input and Output Clock Width LOw!4]
fMAXI
Maximum FrequencY with External Feedback in Input
Registered Mode (LOwer of 1/(tloo + tiS) & 1/(tWL + twW)[4]
fMAX2
Maximum FrJ(\uencY Data Path in Input Registered Mode
(Lowest of (11 tloo), 1/(tWH +tWL), 1/(tls +tIW)[4]
43.4
40
33.3
MHz
tlOH - tIH
33x
Output Data Stable from Input Clock Minus Input Register
Hold Tune for 7C330, 7C332, and 7C335[7]
0
0
0
ns
Output Registered Mode Parameters
teo
Output Register Clock to Output Delay
toH
ts
tH
Output Data Stable Time from Output Clock
2
12
2
2
ns
Output Register Input Set-Up Time to Output Clock
12
15
0
20
us
us
Output Register Input Hold Tune to Output Clock
fMAJO
Maximum FrequencY with External Feedback in Output
Registered Mode (Lower of 1/(tco + ts) & 1/(tWL + tWH»[4]
fMAX4
Maximum FrequencY Data Path in Output Re~tered Mode
(Lowest of 1/(tco), 1/(tWL + twm, 1/(ts + tH»
Output Data Stable from Output Clock Minus Input Register
Hold Time for 7C330, 7C332, and 7C335[7]
toH - tIH
33x
0
41.6
15
20
ns
33.3
0
25
MHz
83.3
62.5
50
MHz
0
0
0
ns
15
20
25
ns
66.6
50
40
MHz
Pipelined Mode Parameters
teas
Input Clock to Output Clock
fMAXS
Maximum FrequencY Pipelined Mode
(Lowest of 1/(teos), 1/(tIS), 1/(tco»[4]
Power-Up Reset Parameters
Power-Up Reset Time(4,8j
tpOR
1
4-152
I
1
1
!IS
C:i~
= ., ~caIDUCl'OR
PRELIMINARY
CY7C335
Switching Waveform
INPUT OR
110 PIN
INPUT REG.
CLOCK
•
- - " ' - - - tWL
~------------~s----~~--~~
OUTPUT
REG. CLOCK
U)
C
...J
a..
OUTPUT
~--- (Po ------<~
I.
leER
-----I
14----------- teR ----------..1
PIN 14
ASUE
C335-20
Power-Up Reset Waveform[8)
Vee
OUTPUT
CLOCK
C335-21
4-153
PRELIMINARY
CY7C335
Block Diagram (Page 1 of 2)
TO LOWER SECTION
0335-22
4-154
CY7C335
PRELIMINARY
Block Diagram (Page 2 of 2)
TO UPPER SECTION
L
115
', ~ r-t:t~
~~-n
~
~
,
...J
Q.
~
lnode= 32
~ ~
] node= 31
'''-D
,
I/)
C
node= 37
',,~ f i
J -
II
~
J -
117.rJb
"j
~'
~
node= 36
. . r -q HEl
~
19~
,~ ~
~~ ~
(C
'SET
rn:
~
node= 35
~
rM
,,<=
node=30
0335-23
4-155
·
,~PRFSS
~F
PRELIMINARY
SEMlcaIDUCTOR
Ordering Information
fMAX
Iccl
(MHz)
(rnA)
83.3
140
66.6
66.6
50
160
140
140
Package
Ordering Code
40
160
160
Operating
Range
Commercial
CY7C335-83HC
H64
CY7C335-83JC
CY7C335-83PC
J64
P21
CY7C335-83WC
W22
CY7C335-66DI
CY7C335-66HI
CY7C335 -66PI
D22
H64
P21
CY7C335 -66WI
W22
CY7C335-66DMB
CY7C335-66HMB
CY7C335 -66LMB
CY7C335 -66QMB
D22
H64
L64
Q64
CY7C335-66WMB
W22
CY7C335-66HC
H64
CY7C335-66JC
CY7C335-66PC
CY7C335-66WC
J64
P21
Industrial
Military
Commercial
W22
H64
Commercial
CY7C335-50PC
CY7C335-50WC
CY7C335-50DI
J64
P21
W22
D22
Industrial
CY7C335-50HI
H64
CY7C335-50HC
CY7C335-50JC
50
1YPe
CY7C335-50PI
P21
CY7C335 - 50WI
CY7C335-50DMB
CY7C335 -50HMB
W22
D22
H64
CY7C335-50LMB
CY7C335-50QMB
L64
Q64
CY7C335-50WMB
W22
CY7C335-40DI
CY7C335-40HI
D22
Industrial
H64
CY7C335-40PI
P21
CY7C335-40WI
W22
CY7C335-40DMB
CY7C335-40HMB
H64
CY7C335 -40LMB
Military
D22
CY7C335-40QMB
L64
Q64
CY7C335-40WMB
W22
Military
Document #: 38-00186-A
4-156
CY7C335
CY7B336
PRELIMINARY
CYPRESS
SEMICONDUCTOR
6-ns BiCMOS PAL®
with Input Registers
• Available in 28-pin 300-mil PDIP and
CerDIp, and in SOJ, PLeC, and LeC
packages
Features
• Very high performance decoder
-tICO 6ns
- fMAXD 156 MHz
=
=
Functional Description
The CY7B336 is a 6-ns, 2S-pin programmable logic device specially designed for
decoding applications with high-performance RISC processors and fast state machines.
There are twelve input registers that capture data at the rising edge of the clock signal and forward the information to the 24
by 16 programmable array. Processeddata
from the programmable array is available
to extemallogic via the eight output pins.
Each outp~t provides two product terms.
However; only one product term is used to
•
•
•
•
•
•
•
12 input registers
8 outputs
2 product terms per output
Asynchronous output enable
Power-on reset
ffigh noise immunity
>2001V input protection from electrostatic discharge
• Advanced BiCMOS technology
sum products from the array; the other
productterm is used to control thetri-state
output buffers. This output enable product
term is ANDed with the complement of
the output enable input pin to generate the
output enable signal for each output buffer.
Additional features of the CY7B336 include a power-on reset circuit that initializesall input registers to a "0" upon powerup, and six centrally located power pins
(two Vee pins and four ground pins),
which improve noise margins.
TheCY7B336 is available in a wide variety
of package types including 2S-pin, 300-mil
plasticandceramicDlPs, SOJs, LeCs, and
PLCes.
Pin Configuration
Logic Block Diagram and DIP/SOJ Pinout
LCCand PLCC
Top View
:.:
~~..=~dc:f6
8336-2
8336-1
Selection Guide
Generic
Part Number
7B336-6
tlCO (ns)
Com'l
6
7B336-7
7B336-S
Com'l
Mil
156
7
S
tiS (ns)
Icc(mA)
fMAXD(MHz)
Mil
Com'l
Mil
ISO
131
Mil
2
2.5
ISO
ISO
113
Com'l
3
7B336-1O
10
96
ISO
3
7B336-12
12
80
ISO
3.5
PAL is a registered trademark of Monolithic Memories Inc.
4-157
•
z:~
PRELIMINARY
~=CYPRESS
~_'J SEMlCONDUCTOR
CY7B336
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. - 65°C to +150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pins 7 and 22 to Pins 8, 20, 21, and 23) ..... - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState .................... - O.5Vto +VeeMax.
DC Input Voltage ................ - 0.5V to + Vee +0.5V
Output Current into Outputs (LOW) ............... 12 rnA
DC Input Current .................... - 30 rnA to +5 rnA
(Except during programming)
DC ProgrammingVoltage ........................... 9.5V
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. > 2001 V
(per MIL-STD-883 Method 3015)
Latch-UpCurrent .. . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Operating Range
Range
Commercial
Militaryll]
Ambient
Thmperature
O°Cto + 70°C
Vee
5V± 10%
- 55°Cto + 125°C
5V± 10%
Electrical Characteristics Over the Operating Range
7B336
Parameters
VOH
Description
Output HIGH Voltage
Thst Conditions
VOL
Output LOW Voltage
VIH
VIL
IJX
Input HIGH Level
Input LOW Level
Input LeakageCurrent
Ioz
Output LeakageCurrent
Ise
lee
Output Short Circuit Current
Power Supply Current
IOH = -4rnA Com'l
IoH=-3mA Mil
Com'l
Vee = Min., VIN = VIHorVIL IOL= 12rnA
Mil
IoL=8rnA
Guaranteed Input Logical HIGH Voltage for All Inputs
Guaranteed Input Logical LOW Voltage for All Inputs
Vee = Max.,O.4V S VINS2.7V
Vee = Min., VIN = VIH or VIL
Vee = Max.,O.4V S VOUT s2.7V
Vee = Max., VOUT = 0.5V[2]
Vee = Max., Outputs Disabled (in High Z State), Com'l
Device Operating at fMAX
Mil
Min.
2.4
2.4
Max.
Units
V
0.4
0.4
V
2.2
V
V
-250
0.8
25
-100
100
-30
-130
180
180
IlA
IlA
rnA
rnA
Capacitance [3]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
COUT
'!Yp.
11
9
Notes:
1. TA is the "instant on" case temperature.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOlIT = O.SV has
been chosen to avoid test problems caused by tester groond degradation.
3.
4.
Units
pF
pF
Max.
10
10
Tested initially and after any design or process changes that may affect
these parameters.
The normal test load is used for all parameters except for tCER, 1cEA,
tpxz, and tpzx, which are tested using the three-state load.
AC Test Loads and Waveforms[4]
R = 125Q
R1329Q
OllTl':;;: "",
Iil~
(181~
OUTPU~~-------.-~~
1
(288Q MIL)
INCWDING _
_
JIG AND SCOPE
(a) Normal Load
~
10%
5 PF
....
.s3ns
B336-4
(b) Three-State Load
8336-3
Equivalent to:
ALL INPUT PULSES
V:
THEvENIN EQUIVALENTS
125Q
OUTPUT_
8336-5
1810
OUTPUT C).o------"J
..."'~__---oo
1.90 = Vthc
Commercial
Military
4-158
1.85 = Vthm
4£
•
:;::z
PRELIMINARY
. - CYPRESS
_" SEMI~DUCTOR
CY7B336
AC Test Loads and Waveforms (continued)
Pammeter
Output Waveform-Measurement Level
Vx
tCER(-)
tpxz(-)
1.5V
tCER(+)
tpxz(+)
2.6V
tCEA(+)
tpzx(+)
Vthc
tCEA(-)
tpzx(-)
Vthc
:
VOH O.5V
t:I:
O.5V:
VOL
Vx
O.5V
Vx
~
~
0.5V:
Vx
Vx
:
•
VOH
VOL
II)
C
..J
a.
Switching Characteristics Over the Operating RangeISJ
Military
Commercial
6
Parameters
tlCO
Description
Min.
Input Register Clock to
Output Delay
7
8
Max.
Min.
Max.
Min.
8
6
10
Max.
Min.
12
Max.
Min.
10
7
Max.
Units
12
ns
tp
Clock Period (tWH+tWL)[3J
fMAXD
Maximum Frequency Data
Path (l/tp)[3J
tWH
Clock Width HIGH[3J
3_2
4.4
3.8
5.2
6.2
ns
tWL
Clock Width LOW[3J
3.2
4.4
3.8
5.2
6.2
ns
tOH
Output Hold Mter
OockHigh
0
0
0
0
0
ns
6.4
113
156
10.4
7.6
8.8
131
12.4
96
ns
80
MHz
tIS
Input Set-Up Time
2
3
2.5
3
3.5
ns
tlH
Input Hold Time
2
3
2.5
3
3.5
ns
tCER
Input Register Clock to
Output Disable Delay[6J
9
13
11
14
17
ns
tCEA
Input Register Clock to
Output Enable Delay
9
13
11
14
17
ns
tpxz
Pin 15 to OutP.ut
Disable Dela:YI6J
7
10
8.5
11.5
14_5
ns
tpzx
Pin 15 to Output
Enable Delay
7
10
8.5
11.5
14.5
ns
tpR
Power-Up Reset Time17J
1
1
1
1
1
J.ls
Notes:
5. AC test load is used for all parameters except where noted.
6. This parameter is measured as the time that the previous output data
state remains stable after the output disable signal is received. This
delay is measured to the point at which a previous mGH level has fallen to 0.5 volts below VOH Min. or a previous WW level has risen to
0.5 volts above VOL Max.
7. This part has been designed with the capability to reset during system
power-up. FOllowing power-up, the input registers will be reset to a
logic LOW state. The output state will depend on how the array is
programmed. Th insure proper operation, the rise in Vcc must be
4-159
monotonic and the timing constraints depicted in power-up reset
waveforms must be satisfied. The clock signal input must be in a valid
WW state (YIN less than O.SV) or a valid HIGH state (VIN greater
than 2.2V) prior to occurrence of the 10% level on the monotonically
rising power supply voltage. In addition, the clock input signal must remain stable in that valid state as indicated until the 90% level on the
power supply voltage has been reached. The clock signal may transition WW to HIGH to clock in new data or to execute a synchronous
preset after the indicated delay (tpR + tIS) has been observed.
&;i:~
~~
PRELIMINARY
CY7B336
SEMICONDUC"1DR
Switching Waveform
~---------tp----------~
ClK _ _ _ _ _ _J
0
~ER5
~~~
C"'3
L~=1
0
OE
0
8336-6
Power-Up Reset Waveform[7]
POWER
~~~-------------------------------------------------v~
OUTPUT
ClK
INPUT
8336-7
4-160
~
~~PRESS
~, SEMICONDUcroR
CY7B336
PRELIMINARY
CY7B336 Logic Diagram
elK
~
10
REG
R
~
REG
1
R
~
REG
M
R
~
REG
~
IJ
R
~
~
~
J
~
REG
~
-0
0
01
J
02
J
03
R
1
~
~
I'
H!r
1_J
""\
~
1
R
IS
~
REG
R
19
REG
R
~
~
~
J
J
..,
J
""\
J
J
-
REG
R
vccd
R
vss~
8-8336-8
4-161
II>
C
Q.
J
REG
R
•
....I
"'\
f
R
15
'\
J
PRELIMINARY
Ordering Information
tICO
iMAxn
(ns)
(MHz)
6
156
Ordering Code
CY7B336-6PC
CY7B336-6DC
7
8
131
113
12
96
80
Operating
Range
P21
D22
Commercial
CY7B336-6JC
J64
CY7B336-6VC
V21
CY7B336-7DMB
CY7B336-7LMB
D22
CY7B336-8PC
P21
D22
CY7B336-8DC
10
Package
'JYpe
CY7B336-8JC
J64
CY7B336-8VC
V21
022
CY7B336-lODMB
CY7B336-lOLMB
Military
L64
Commercial
Military
L64
CY7B336-12DMB
D22
CY7B336-12LMB
L64
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vm
VIL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IIX
Ioz
Switching Characteristics
Parameters
Subgroups
tICO
tIS
tm
tcxz
tczx
tpxz
tpzx
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10,11
Document #: 38-00134-B
4-162
CY7B336
CY7B337
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• Very blgb performance decoder
-tIco = 7ns
-fMAXl) = 141 MHz
• 12 input registers
• 8 outputs
• 4 product terms per output
•
•
•
•
Asynchronous output enable
Power.on reset
High noise immunity
>lOO1V Input protection from elec·
trostatic discbarge
• Advanced BiCMOS technology
7-ns BiCMOS PAL®
with Input Registers
• Available In 18-pin 300-mil PDIP and
CerDIP, and In SOJ, PLCC, and LCe
packages
Functional Description
The CY7B337 is a 7-ns, 28-pin programmable logic device specially designed for decoding applications with high-performance
RISC processors and fast state machines.
There are twelve input registers that capture
data at the rising edge of the clock signal and
forward the information to the 24 by 32 programmable array. Processed data from the
programmable array is available to ezternal
logic via the eight output pins.
Each output provides four product terms.
All outputs can be three-stated using the
output enable signal.
Additional features of the CY7B337 include a power-on reset circuit that initializes all input registers to a "0" upon power-up, and six centrally located power pins
(two Vcc pins and four ground pins),
which improve noise margins.
The CY7B337 is available in a wide variety of package types including 28-pin,
3OO-mil plastic and ceramic DIPs, SOJs,
LCCs, and PLCCs.
Pin Configuration
Logic Block Diagram and DIP/SOJ Pinout
LCC and PLCC
Top View
:.:
~..J:'..::.s>dd'o
8337-2
8337-1
Selection Guide
7B337-7
Com'l
Mil
7
7B337-8
7B337-9
fMAXl) (MHz)
tlCO (ns)
Generic
Part Number
Com'!
Mil
142
8
9
Icc(mA)
Com'l
tIS (ns)
Mil
125
111
Com'l
Mil
2
180
2.5
180
180
3
7B337-10
10
96
180
3
7B337-12
12
80
180
3.5
PAL is a registered trademark of Monolithic Memories Inc.
4-163
II
en
C
...I
a.
&:~crPRFSS
~_"
PRELIMINARY
CY7B337
SEMICONDUCIDR
Maximum Ratings
(Abovewhich the useful life may be impaired. Foruserguidelines,
nottested.)
StorageThmperature ................. - 65°C to +150°C
Ambient Thmperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pins 7 and 22 to Pins 8, 20, 21, and 23) ..... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .................... - 0.5V to + Vee Max.
DC Input Voltage ................ - 0.5V to + Vee +O.5V
Output Current into Outputs (WW) ............... 12 rnA
DC Input Current .................... - 30 rnA to +5 rnA
(Except during programming)
DC ProgrammingVoltage ........................... 9.5V
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-SID-883 Method 3015)
Latch-UpCurrent ............................ > 200 rnA
Operating Range
Range
Commercial
Militaryll)
Ambient
Thmperature
O°Cto + 70°C
Vee
5V± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Range
7B337
Parameters
Description
lest Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., VIN = Vrn or VIL
IoH = -4rnA Com'l
IoH= -3rnA Mil
Com'l
IOL= 12 rnA
Mil
IoL=8rnA
VOL
Output WW Voltage
Vee = Min., VIN = VrnorVIL
Vrn
Input mGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
VIL
IJX
Input WW Level
Input LeakageCurrent
Guaranteed Input Logical WW Voltage for All Inputs
Vee = Max.,0.4V 5 VIN 52.7V
Ioz
Output LeakageCurrent
Vee = Max., O.4V 5 VOUT 5 2.7V
Isc
Output Short Circuit Current
Icc
Power Supply Current
Vee = Max., VOUT = 0.5V!2]
Vee = Max., Outputs Disabled (in High Z State),
Device Operating at fMAX
Max.
2.4
2.4
Units
V
0.4
0.4
2.2
V
V
0.8
V
-250
25
-100
100
!-tA
!-tA
-30
-130
rnA
180
rnA
Com'l
Mil
180
Capacitance(3)
CIN
Parameters
Description
InputCapacitance
CoUT
Output Capacitance
Notes:
1. TA is the "instant on" case temperature.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
lYP.
Max.
11
9
10
10
Units
pF
pF
3. Thsted initially and after any design or process changes that may affect
these parameters.
4. The normal test load is used for all parameters except for tpxz and
tpzx, which are tested using the three-state load.
AC Test Loads and Waveforms(4)
R1329Q
V:
OUTP~~31(490Q
MIL)
35PFI
R = 12SQ
(181~
OUTPUT~-------·-lL~
I
R2
202Q
(288Q MIL)
INCLUDING _
_
JIG AND SCOPE
(8) Normal Load
~ns
SpF
8337-4
(h) Three·State Load
8337-3
Equivalent to:
ALL INPUT PULSES
8337-5
THEvENIN EQUIVALENTS
12SQ
OUTPUT 000--__
",\1\.'_ _-00 1.90 =
181Q
OUTPUT 000--__
"'\1\1'_--00 1.85 =
Vthc
Military
Commercial
4-164
Vthm
1!:W~PRffiS
~
PRELIMINARY
CY7B337
SEMICCNDUCTOR
AC Test Loads and Waveforms (continued)
Parameter
Output Waveform-Measurement Level
Vx
tpxz(-)
l
1.5V
VOH O.5V
2.6V
tpxz(+)
tpzx(+)
VOL
0.5V:
Vx
O.5V:
Vthc
tpzx(-)
Vthc
Vx
l
O.5V
~
Vx
~
Vx
~
~
VOH
II
II)
VOL
C
...I
D.
Switching Characteristics Over the Operating Range/5]
Military
Commercial
7
Parameters
Description
Min.
8
I}
Max.
Min.
Max.
Min.
12
10
Max.
Min.
Max.
Min.
Max. Units
tICO
Input Register Clock to
Output Delay
tp
Clock Period (twH+twd3]
fMAXD
Maximum Frequency Data Path
(Lower of l/tICO and l/tp)[3,6]
tWH
Clock Width IDGH(3]
3.2
4.4
3.8
5.2
6.2
ns
tWL
Clock Width LOW[3]
3.2
4.4
3.8
5.2
6.2
ns
tOH
Output Hold After
Clock High
0
0
0
0
0
ns
tIS
Input Set-Up Time
2
3
2.5
3
3.5
ns
tm
Input Hold Time
2
3
2.5
3
3.5
ns
tpxz
Pin 15 to OutP,ut
Disable Delay(7]
7
10
8.5
11.5
14.5
ns
tpzx
Pin 15 to Output
Enable Delay
7
10
8.5
11.5
14.5
ns
tpR
Power-Up Reset Time[8]
1
1
1
1
1
!-IS
7
8
9
6.4
7.6
8.8
111
142
Notes:
S. AC test load is used for all parameters except where noted.
6. Maximum frequency data path (fMAXD) is limited by l/tICO for the 7and 9-ns commercial and the 8-ns military versions. Maximum frequency data path (fMAxD) is limited by 1/tp for the 10- and 12-ns mill·
Ial)' versions.
7. This parameter is measured as the time that the previous output data
state remains stable after the output disable signal is received. This
delay is measured to the point at which a previous HIGH level has fall·
en to 0.5 volts below V OH Min. or a previous WW level has risen to
0.5 volts above VOL Max.
8. This part has been design~d with the capability to reset during system
power-up. Following power-up, the input registers will be reset'to a
4-165
12
10
10.4
125
12.4
ns
80
96
ns
MHz
10gicWW state. The output state will depend on how the array is programmed. Th insure proper operation, the rise in V cc must be monotonic and the timing constraints depicted in power-upresetwaveforms
must be satisfied. The clock signal input must be in a valid WW state
CV:IN less than 0.8V) or a valid HIGH state (YIN greater than 2.2V)
pnor to occurrence of the 10% level on the monotonically rising power supply voltage. In addition, the clock input signal must remain
stable in thatvaJid state, as indicated, until the 90% level on the power
supply voltage has been reached. The clock signal may transition
WW to HIGH to clock in new data or to execute a synchronous preset after the indicated delay (tPR + tIS) has been observed.
PRELIMINARY
CY7B337
Switching Waveform
~--------tp--------
ClK
__
------""
tl~~1
o _ _ _ _ _.JX~"'----OE
o
-----
....
t~3__
8337-6
Power-Up Reset Waveform[8]
Vee
POWER
OUTPUT
ClK
INPUT
4-166
~
.
;~PRESS
~,
PRELIMINARY
CY7B337
SEMICONDUCTOR
CY7B337 Logic Diagram
c
~
~
10
REG
R
REG
R
--;:t
00
•
I I)
C
:-4f
REG
R
~
-
~
REG
..J
a..
t=t:L
01
~
R
02
~
REG
R
15
~
~
~
~
03
~
REG
R
16
REG
IN.
R
~
REG
17
R
~
~
~
18
~
REG
R
19
-
~
REG
R
~
~
~
~
IN.
17
REG
R
Vee
d
REG
R
Vss
B-
9
8337-8
4-167
~PRR§
~J
PRELIMINARY
SEMlCONDUCl'OR
Ordering Information
(MHz)
7
142
8
9
10
12
Package
type
Operating
Range
CY7B337 -7PC
P21
Commercial
CY7B337-7DC
D22
fMAX»
tIeo
(ns)
125
111
96
80
Ordering Code
CY7B337-7JC
J64
CY7B337-7VC
V21
CY7B337-8DMB
D22
CY7B337-8LMB
L64
CY7B337-9PC
P21
CY7B337-9DC
022
CY7B337-9JC
J64
CY7B337-9VC
V21
CY7B337 -10DMB
D22
CY7B337-lOLMB
L64
CY7B337-12DMB
D22
CY7B337 -12LMB
L64
Military
Commercial
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vm
VIL
IJX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
Switching Characteristics
Parameters
Subgroups
tlCO
tIS
tm
tpxz
tpzx
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, lO, 11
Document #: 38-00139-B
4-168
CY7B337
CY7B338
PRELIMINARY
CYPRESS
SEMICONDUCTOR
6-ns BiCMOS PAL®
with Output Latches
• Available In 28-pin 3OG-mi. PDIP and
CerDIp, and in SOJ, PLCC, and LCC
packages
Features
• Very high performance decoder with
latched outputs
-tpD = 6ns
- tLEO = 5.5 ns
-tIS =3ns
Functional Description
The CY7B338 is a 6-ns, 28-pin programmable logic device specially designed for
decoding applications with high-performance general-purpose processors and
fast state machines.
There are twelve inputs that feed into the
24 by 16 programmable array. Processed
data from the programmable array is delivered to the eight output latches. When
the latch enable input is IDGH, the output latches are transparent and data from
the array is available to the output buffers. When the latch enable input goes
from HIGH to LOW, the latch contents
are froz£n.
•
•
•
•
•
•
•
12 inputs
8 latched outputs
2 product terms per output
Asynchronous output enable
Power-on reset
High noise immunity
>2001V input protection from electrostatic discharge
• Advanced BiCMOS technology
There are two product terms per output.
However, only one product term is used
to sum products from the array; the other
product term is used to control the threestate output buffers. This output enable
product term is ANDed with the complement of the output enable input pin to
generate the output enable signal for each
output buffer.
Additional features of the CY7B338 include a power-on reset circuit that initializes all output latches to a "0" upon power-up, and six centrally located power pins
(two Vee pios and four ground pios),
which improve noise margins.
The CY7B338 is available in a wide variety of package types including 28-pin,
300-riill plastic and ceramic DIPs, SOJs,
LCCs, and PLCCs.
Pin Configuration
Logic Block Diagram and DIP/SOJ Pinout
LCCandPLCC
Top View
PROGRAMMABLE AND ARRAY
(24 x 16)
OUTPUT LATCHES
8338-2
OUTPUT BUFFERS
LE
8338-1
Selection Guide
Generic
Part Number
7B338-6
tpD (ns)
Com"
6
7B338-7
7B338-8
Mil
Com"
Mil
8
Com"
Mil
180
5.5
7
tiS (ns)
Icc(mA)
tLEO (ns)
6.5
Mil
3
4
180
180
7.5
Com'l
5
7B338-10
10
8
180
5
7B338-12
12
9.5
180
6
PAL is a registered trademark of Monolithic Memories Inc.
4-169
en
C
....I
Q.
~
.iL~ucroR
PRELIMINARY
CY7B338
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerAppJied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pins 7 and 22 to Pins 8, 20, 21, and 23) ..... - O.sV to + 7.OV
DC Voltage Applied to Outputs
in High Z State .................... - O.5V to + Vee Max.
DC Input Voltage ................ - O.5V to + Vee +0.5V
Output Current into Outputs (LOW) ............... 12 mA
DC Input Current .................... - 30 mA to +5 mA
(Exceptduringprogramming)
Electrical Characteristics
DC ProgrammingVoltage ........................... 9.sV
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. > 2001 V
(per MIL-STD-883 Method 3015)
Latch-UpCurrent ............................ > 200mA
Operating Range
Range
Commercial
Militaryll]
Ambient
Thmperature
Vee
O°Cto + 70°C
5V:!: 10%
- 55°C to + 125°C
5V:!: 10%
Over the Operating Range
7B338
Description
Parameters
Output HIGH Voltage
VOH
Min.
Thst Conditions
Vee = Min., VIN = VIHorVIL
IoH= -4mA Com'l
IOH= -3mA Mil
Max.
Units
2.4
V
2.4
VOL
Output LOW Voltage
VIH
VIL
Input HIGH Level
Input LOW Level
Com'l
IoL= 12mA
Mil
IOL= SmA
Guaranteed Input Logical HIGH Voltage for All Inputs
Guaranteed Input Logical LOW Voltage for Ail Inputs
IIX
Input LeakageCurrent
Vee = Max.,O.4V 5 VIN 52.7V
-250
Ioz
Output LeakageCurrent
Vee = Max.,O.4V 5 VOUT 52.7V
-100
100
fAA
fAA
Isc
Output Short Circuit Current
Vee = Max., VOUT = 0.sy[2]
-30
-130
mA
Icc
Power Supply Current
Vee = Max., Outputs Disabled (in High Z State), Com'l
Device Operating atfMAX
Mil
180
mA
0.4
0.4
Vee = Min., VIN = VIHorVIL
V
2.2
V
0.8
25
V
180
Capacitance [3]
Parameters
Description
InputCapacitance
CIN
Output Capacitance
CoUT
Notes:
1. TA is the "instant on" case temperature.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradatiolL
1YP.
Max.
Units
11
10
10
pF
9
pF
3. Tested initially and after any design or process changes that may affect
these parameters.
4. The normal test load is used for all parameters except for tER, tEA.
tpxz, and tpzx, which are tested using the three-state load.
AC Test Loads and Waveforms[4]
R1329Q
R = 125Q
OUTP~~31(490QMIL)
V
0
(181~
R2
202Q
(288Q MIL)
35PFI
INCWDING _
JIG AND -
I
_
-
5pF
aov~1~0%
~3ns
I-
~
10%
GND
_
~3ns
B338-4
SCOPE
Normal Load
(b) Three-State Load
(a)
8338-3
Equivalent to:
ALL INPUT PULSES
oUTPu~",o-----'l"
8338-5
THEvENIN EQUIVALENTS
125Q
1810
OUTPUT 00---'11.\1\._---DO 1.90 = Vthc
Commercial
OUTPUT oo---~~",,----oo 1.85 = Vthm
Military
4-170
.
~
_'iECYPRESS
-=-.'
PRELIMINARY
CY7B338
SEMlCONDoc:TOR
AC Test Loads and Waveforms (continued)
Parameter
Output Waveform-Measurement Level
Vx
tER (-)
tpxz(-)
1.5V
tER (+)
tpxz(+)
2.6V
tEA(+)
tpzx(+)
Vthc
tEA (-)
tpzx(-)
Vthc
:
VOH O.5V
O.5V:
VOL
0.5V
Vx
Vx
F
0.5V
Vx
Vx
t="
~
t
:
VOH
~
II
(I)
VOL
C
...J
a..
Switching Characteristics Over the Operating RangelS]
Military
Commercial
8
6
Parameters
Description
Miu.
Max.
Miu.
10
7
Max.
Min.
Max.
Min.
12
Max.
Min.
Max.
Units
12
ns
tpD
Input to Output
Propagation Delay
tp
Clock Period (tWH+ tWLP]
fMAXD
Maximum Frequency Data
Path (l/tp)[3]
tWH
Latch Enable HIGH[3]
3.2
4.4
3.8
5.2
6.2
ns
tWL
Latch Enable LOW[3]
3.2
4.4
3.8
5.2
6.2
ns
tLEO
Latch Enable to
Output Delay
tWH
Output Hold After
Latch Enable
0
0
0
0
0
ns
tIS
Input Set-Up Time
3
5
4
5
6
ns
tlH
Input Hold Time
0.5
0.5
0.5
0.5
0.5
ns
tER
Input to Output
Disable Delay[6]
9
13
11
14
17
ns
tEA
Input to Output
Enable Delay
9
13
11
14
17
ns
tpxz
Pin 15 to OulP.ut
Disable Delay[S]
7
10
8.5
11.5
14.5
ns
tpzx
Pin 15 to Output
Enable Delay
7
10
8.5
11.5
14.5
ns
tpR
Power-Up Reset Time[7]
1
1
1
1
1
f.IS
8
6
6.4
8.8
7
113
5.5
131
7.5
Notes:
5. AC test load is used for all parameters except where noted.
6. This parameter is measured as the time that the previous output data
state remains stable after the output disable signal is received. This
delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH Min. or a previous LOW level has risen to
0.5 volts above VOL Max.
10.4
7.6
156
7.
4-171
10
12.4
96
6.5
ns
80
9.5
8
MHz
ns
This part has been designed with the capability to reset during system
power·up. Following power·up, the output latches will be reset to a
logic WW state. To insure proper operation, the rise in V cc must be
monotonic and the timing constraints depicted in power-up reset
waveforms must be satisfied. The latch enable inpnt must be in a valid
LOW state (VIN less than O.SY) prior to occurrence of the 10% level
on the monotonically rising power supply voltage. In addition, the
latch enable signal must remain stable in that valid WW state, as indicated, nntil the 90% level on the power supply voltage has been
reached. The latch enable is allowed to change from its WW state
only after the indicated delay (tpR) has been observed.
PRELIMINARY
CY7B338
Switching Waveform
~-------------tp----------
LE
----
14----- tWH
-----.l~---
__
tWL - - - - - . I
o
rn:
.'G.:b.~ ={-----------
-----
o
8338-6
Power-Up Reset Waveform[7]
POWER
..Jc-:::::::--------------------
Vee
......- - - - tpR - - - - - - - - - I
LE
OUTPUT
INPUT
.... ....
1:=
tOH
~X""'X..,...X~X..,...X~X..,...X~X..,...X~X"'7':X--,.....X X~X X-~------8338-7
4-172
tn~
PRELIMINARY
CY7B338
CY7B338 Logic Diagram
LE
....
10
..
11
...
12
Ii"'
-
~
, "' ~
~
-~
....
.
00
-
01
1 ...
....
3
-,.,
..
~
....
4
...
1 """\
......
...
,
....
..
...
19
1
....
...
-
-I"'
-
,
.
.
.
03
.r1
-
~ ~
-
~
~_:;I
~
-v 06
......
....
..
-
......
....
18
-...
[3-
~
Vee
-..,
d
~
6338-8
4-173
II
~
.~
~=CYPRESS
PRELIMINARY
~; SEMICONDUCTOR
Ordering Information
tpD
(ns)
tLEO
(ns)
6
5.5
7
8
6.5
7.5
8
10
12
9.5
CY7B338-6PC
Package
1Ype
P21
CY7B338-6DC
D22
Ordering Code
CY7B338-6JC
J64
CY7B338-6VC
V21
CY7B338-7DMB
D22
CY7B338-7LMB
L64
CY7B338-8PC
P21
CY7B338-8DC
D22
CY7B338-8JC
J64
CY7B338-8VC
V21
CY7B338-IODMB
D22
CY7B338-10LMB
L64
CY7B338-12DMB
D22
CY7B338-12LMB
L64
Operating
Range
Commercial
Military
Commercial
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VJH
VIL
IJX
Ioz
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tIS
tJH
tLEO
tER
tEA
tpxz
tpzx
Document #: 38-00133-B
4-174
CY7B338
CY7B339
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Very bigb performaDce decoder witb
latcbed outputs
-tpD=7DS
- tLEO = 5.5 ns
-t[s=4ns
7-ns BiCMOS PAL®
with Output Latches
• Available in 28-pin 300-m11 PDlP aDd
CerDIP, and iD SOJ, PLCC, and LCC
packages
There are four product terms per output
and all outputs can be three-stated using
the output enable signal.
Functional Description
Additional features of the CY78339 include a power-on reset circuit that initializes all output latches to a "0" upon power-up, and sixcentraIly located power pins
(two Vee pins and four ground pins),
which improve noise margins.
The CY7B339 is available in a wide variety of package types including 28-pin,
3OO-m11 plastic and ceramic DIPs, SOls,
LCCs, and PLCCs.
The CY7B339 is a 7-ns, 28-pin programmable logic device specially designed for
decoding applications with high-performance general-purpose processors and
fast state machines.
There are twelve inputs that feed into the
24 by 32 programmable array. Processed
data from the programmable array is delivered to the eight output latcl1es. When
the latch enable input is mGH, the output latcl1es are transparent and data from
the array is available to the output buffers. When the latch enable input goes
from HIGH to LOW, the latch contents
are frozen.
• 12 inputs
• 8 Iatcbed outputs
• 4 product terms per output
• Asyncbronous output enable
• Power-on reset
• High noise immunity
• >2001V input protectiOD from electrostatic discbarge
• Advanced BiCMOS technology
Pin Configuration
Logic Block Diagram and DIP/SOJ Pinout
LCCandPLCC
Top View
~~.:~~d'o
PROGRAMMABLE AND ARRAY
(24 x 32)
OUTPUT LATCHES
8339-2
OUTPUT BUFFERS
8339-1
Selection Guide
tPD (DS)
GeDeric
Part Number
78339-7
Com'!
78339-9
Com'!
Mil
5.5
7
78339-8
IccCmA)
tLEO (DS)
Mil
tIS (ns)
Mil
7.5
Com'l
Mil
4
180
6.5
8
9
Com'l
5
180
6
180
78339-10
10
8
180
6
78339-12
12
9.5
180
7
PAL is a registered trademark of Monolithic Memories Inc.
4-175
•
tI)
9D.
~PRFSS
_~camUClDR
PRELIMINARY
CY7B339
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied .. ..... .. .. .... .. .. .... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pins 7 and 22 to Pins 8, 20, 21, and 23) ..... - 0.5Vto +7.0V
DC Voltage Applied to Outputs
in High Z State .................... - O.5V to + Vee Max.
DC Input Voltage ................ - O.5V to + Vee +O.5V
Output Current into Outputs (LOW) ............... 12 mA
DC Input Current .................... - 30 mA to +5 mA
(Exceptduringprogramming)
DC ProgrammingVoJtage ........................... 9.5V
StaticDischargeVoltage ........................ > 2001V
(per MIL-STD-883 Method 3015)
Latch-Up Current ............................ > 200 mA
Operating Range
Range
Commercial
Militaryfl)
Ambient
Thmperature
O°Cto + 70°C
Vee
SV± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Overthe Operating Range
78339
Description
Parameters
Output HIGH Voltage
VOH
Output LOW Voltage
VOL
Min.
Thst Conditions
Vee = Min., VIN = VIHorVIL
IoH = -4mA Com'l
2.4
2.4
Vee = Min., VIN = VIHorVIL
IoH= -3mA Mil
Com'l
IOL=12mA
Mil
IoL=8mA
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
Max.
Units
V
0.4
V
0.4
2.2
V
0.8
V
Irx
Input LeakageCurrent
Vee = Max.,O.4V ~ VIN~2.7V
-250
25
Ioz
Output LeakageCurrent
Vee = Max., 0.4V ~ VOUT ~2.7V
-100
100
!JA
!JA
Ise
lee
Output Short Circuit Current
Vee = Max., VOUT = 0.SV(2)
-30
-130
mA
Power Supply Current
Vee = Max., Outputs Disabled (in High Z State), Com'l
Device Operating at fMAX
I Mil
180
180
mA
Capacitance(3)
CIN
Parameters
Description
InputCapacitance
CoUT
OutputCapacitance
11
Max.
10
Units
pF
9
10
pF
'JYp.
Note.:
1. TAis the "instant on" case temperature.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
3.
4.
Tested initially and after any design or process changes that may affect
these parameters.
The normal test load is used for all parameters except for tpxz and
tpzx, which are tested using the three-state load.
AC Test Loads and Waveforms(4)
Rl329Q
R= 125Q
a:t)
OUTP~31(490Q
MIL)
v:
(181
oUTPu~Oo-----'l"
I
R2
202Q
(288Q MIL)
35PFI
INCLUDING _
_
JIGAND SCOPE
(a> Normal Load
~~ns
5pF
8339-4
(b> Three-State Load
8339-5
8339-3
Equivalent 10:
ALL INPUT PULSES
THEvENIN EQUIVALENTS
125Q
OUTPUT 000-_...·"'''''..._ _-00 1.90 = V1hc
OUTPUT 000_ _...·"'''''..._ _-00 1.85 = V1hm
Commercial
Military
4-176
-~
. .j; CYPRESS
-=-_:
PRELIMINARY
CY7B339
SEMICONDUCTOR
AC Test Loads and Waveforms (continued)
Output Waveform-Measurement Level
Vx
Parameter
1.5V
tpxz(-)
tpxz (+)
2_6V
tpzx (+)
Vthc
tpzx (-)
:
~
VOL
05V:
~
Vx
Vx
05V
~
~
VOH
VOH 05V
Vthc
Vx
~
:
05V
Vx
II
VOL
I/)
C
...J
a..
Switching Characteristics Over the Operating Range[S]
Military
Commercial
9
7
Parameters
Description
tpD
Input to Output
Propagation Delay
tp
Clock Period (tWH+tWL)[3]
fMAXD
Maximum Frequency Data Path
(Lower of l/tp and l/tpD)[3.6]
Min.
Max.
Min.
7
Min.
604
7_6
8.8
142
Max.
Min.
111
Max.
Min.
10
8
9
12
10
8
Max.
96
tWH
Latch Enable HIGH[3]
3.2
4.4
3_8
5.2
6.2
tWL
Latch Enable LOW[3]
3.2
4.4
3_8
5.2
6.2
tLEO
Latch Enable to
Output Delay
tLOH
Output Hold After
Latch Enable
7.5
5.5
0
65
0
0
Units
12
ns
80
MHz
1204
lOA
125
Max.
ns
ns
95
8
0
ns
ns
0
ns
ns
tIS
Input Set-Up Time
tm
Input Hold Time
tpxz
Pin 15 to Outllut
Disable Delay[7]
7
10
85
11.5
145
ns
tpzx
Pin 15 to Output
Enable Delay
7
10
8.5
115
145
ns
tpR
Power-Up Reset Time[8]
1
1
1
1
1
!-Is
4
6
5
6
7
05
05
05
05
05
Notes:
5. AC test load is used for all parameters except where noted.
6. Maximum frequency data path (fMAXD) is limited by 1/tpD for the 7and 9-ns commercial and the 8-ns military versions. Maximum frequency data path (fMAXD) is limited by 1/tp for the 10- and 12-ns military versions.
7. This parameter is measured as the time that the previous output data
state remains stable after the output disable signal is received_ This
delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH Min. or a previous LOW level has risen to
0.5 volts above VOL Max.
8.
4-177
ns
This part has been designed with the capability to reset during system
power-up. Following power-up, the output latches will be reset to a
logic LOW state_ To insure proper operation, the rise in Vee must be
monotonic and the timing constraints depicted in power-up reset
waveforms must be satisfied. The latch enable input must be in a valid
LOW state (VIN less than 0.8V) prior to occurrence of the 10% level
on the monotonically rising power supply voltage. In addition, the
latch enable signal must remain stable in that valid LOW state, as indicated, until the 90% level on the power supply voltage has been
reached. The latch enable is allowed to change from its LOW state
only after the indicated delay (tPR) has been observed.
~~
PRELIMINARY
.;~
CY7B339
Switching Waveform
~-------------tp----------~
14-----
tWH
------1----
tWL
------.I
LE _ __
......----~-~~xx*---
o
OE
-------
HIGHb~ ={------
-------
o
8339-7
Power-Up Reset Waveform!?]
! , - - - - - - - - - - - - - - - - - - - - - - vee
POWER
1 4 - - - - - - - - tpR
-----~
LE
OUTPUT
1::=
tOH
INPUTX~X-X~X-X~X-X~X-X~X..,..X~X..,..x~x..,..x-K------8339-6
4-178
CY7B339
PRELIMINARY
CY7B339 Logic Diagram
LE
0
1
2
-...
...
...
~
....
...
~
...
3
...
-;::t
~
-;:t
.--.
~
:TCH
...
...
...
OUT
~
....
16
...
...
...
----;:L
OUT
-
~
-
~
--
....
19
~
-~
....
....
18
~
~
-
~
:=tP
...
OUT
~
....
....
B-
...
...
~
.
~
....
~
~
----;:L
vccd
VSS
9
8339-8
4-179
1/1
c..
----;:L
..
4
•
C
..J
OUT
=-
00
06
PRELIMINARY
Ordering Information
tLEO
tm
(os)
(ns)
7
5.5
8
9
6.5
7.5
10
12
8
9.5
Package
'JYpe
Operating
Range
cY1B339-7PC
P21
Commercial
CY7B339-7DC
D22
Ordering Code
CY1B339-7JC
J64
CY7B339-7VC
V21
CY7B339-8DMB
D22
CY7B339-8LMB
L64
CY1B339-9PC
P21
CY7B339-9DC
D22
CY7B339-9JC
J64
CY7B339-9VC
V21
CY7B339-10DMB
D22
CY7B339-10LMB
L64
CY7B339-12DMB
D22
CY7B339-12LMB
L64
Military
Commercial
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
YOH
VOL
Vrn
1,2,3
1,2,3
VIL
IIX
Ioz
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tPD
7, 8, 9, 10, 11
tIS
trn
7,8,9,10, 11
7, 8, 9, 10, 11
tLEO
tpxz
7,8,9,10, 11
7,8,9, 10, 11
tpzx
7, 8, 9, 10, 11
Document #: 38-00138-B
4-180
CY7B339
CY7C340 EPLD Family
CYPRESS
SEMICONDUCTOR
Multiple Array MatriX
High-Density EPLDs
Features
General Description
• Erasable, user-conflgurable CMOS
EPLDs capable of implementing bigbdensity custom logic functions
• Advanced 0.8-mlcron double-metal
CMOS EPROM technology
• Multiple Array MatriX architecture
optimized for speed, density, and
straigbtforward design Implementation
-1YPical clock frequency = SO MHz
- Programmable Interconnect Array
(PIA) simplifies routing
- Flexible macroceUs increase utilization
- Programmable clock control
- Expander product terms implement complex logic functions
• MAX+PLUS® development system
eases design
- Runs on IBM PClAT® and compatible machines
- Hierarcbical schematic capture
witb 7400 series TTL and custom
macrofunctions
- State machine and Boolean entry
- Graphical delay path calculator
- Automatic error location
- Timing simulation
- Grapblcallnteractive entry of
waveforms
The Cypress Multiple Array MatriX
(MAX®) family of EPlDs provides a
user-configurable, high-density solution
to general-purpose logic integration requirements. With the combination of innovative architecture and state-of-the-art
process, the MAX EPLDs offer J..')I density without sacrificing speed.
The MAX architecture makes it ideal for
replacing large amounts of 1TL S8I and
MSI logic. For example, a 74161 counter
utilizes only 3% of the 128 macrocells
available in the CY7C342. Simllarly, a
74151 8-to-l multiplexer consumes less
than 1% of the over 1,000 product terms
in the CY7C342 This allows the designer
to replace 50 or more 1TL packages with
just one MAX EPLD. The family comes
in a range of densities, shown below. By
standardizing on a few MAX building
blocks, the designer can replace hundreds
of different 7400 series part numbers currently used in most digital Systems.
The family is based
8.rchitecture of
flexible macrocells grouped together into
Logic Array Blocks (LABs). Within the
LAB is a group of additional product
terms called expander product terms.
These expanders are used and shared by
the macrocells, allowing complex functions of up to 35 product terms to be easiy implemented in a singie macrocell. A
Programmable Interconnect Array (PIA)
giobally routes all signals within devices
containing more than one LAB. This architecture is fabricated on the Cypress advanced 0.8-micron, double-layer-metal
CMOS EPROM process, yielding devices
with significantly higher integration density and system clock speed than the largest
of previous generation EPLDs.
The density and flexibility of the
CY7C340 family is accessed using the
MAX + PLUS development system. A PCbased design system, MAX + PLUS is optimized specifically for the CY7C340 family architecture, providing efficient design
processing. A hierarchical schematic entry
mechanism is used to capture the design.
State machine, truth table, and Boolean
equation entry mechanisms are also supported, and may be mixed with schematic
capture. The powerful design processor
performs minimization and logic synthesis, then automatically fits the design into
the desired EPLD. Design verification is
done using a timing simulator, which provides full AC simulation, along with an interactive graphic waveform editor package to speed waveform creation and debugging. During design processing a sophisticated automatic error locator shows
exactly where the error occurred by popping the designer back into the schematic
at the exact error location.
on an
Max Family Members
Feature
CY7C344
CY7C343
CY7C342
CY7C341
Macrocells
32
64
128
192
MAX Flip-Flops
32
64
128
192
MAX Latches!l)
64
128
256
384
MAX Inputs l2J
23
35
59
71
MAX Outputs
16
28
52
64
28H,J,W,D
44H,J
68H,J,R,G
84H,J,R,G
Packages
Key: D-DIP; G-Pin Grid Array; H-Wmdowed Ceramic Leaded Qlip Carrier; J-J-Lead Chip Carrier; R-Wmdowed Pin Grid Array;
W-Wmdowed Ceramic DIP
Notes:
1. When all expander product terms are used to implement latches.
2 With one output.
PAL is a registered trademark of Monolithic Memories Inc.
MAX and MAX +PWS are registered trademarks of A1tera Corporation.
IBM and IBM PC!AT are registered trademarks of International Business Machines Corporation.
4-181
•
tI)
C
...I
D.
~PR£SS
.,rs'1wCONDUCIDR
CY7C340 EPLD Family
DEDICATED INPUTS
1\
0
~
I
~~~~
~
tr>-D
-
ff-
'~
MULTIPLE
> ARRAYS
(LABS)
LOGIC
BLOCK .....
ARRAY
(LAB)
~
r-.
-
~
~
f-
(]- -{>-- DUAL
I/O
FEEDBACK
V
EXPANDER ,,/"
V
PRODUCT
TERMS
-
f-
I
-1
-
~
~
MACROCELLS
~
PROGRAMMABLE
INTERCONNECT
ARRAY (PIA)
Figure 1. Key MAX Features
4-182
0340-1
CY7C340 EPLD Family
Functional Description
The Logic Array Block
The logic array block, shown in Figure 2, is the heart of the MAX
architecture. It consists of a macrocell array, expander product
term array, and an I/O block. The number of macrocells, expanders, and I/O vary, depending upon the device used. Global feedback of all signals is provided within a LAB, giving each functional block complete access to the LAB resources. The LAB itself is
fed by the programmable interconnect array and dedicated input
bus. The feedbacks of the macrocells and 1/0 pins feed the PIA,
providing access to them through other LABs in the device. The
members of the CY7C340 family of EPLDs that have a single
LAB use a global bus, so a PIA is not needed (see Figure 3).
The MAX Macrocell
1i"aditionally, PLDs have been divided into either PLA (programmable AND, programmable OR), or PAL® (programmable
AND, fIXed OR) architectures. PLDs of the latter type provide
faster input-to-output delays, but can be inefficient due to fIXed
allocation of product tenns. Statistical analysis of PLD logic designs has shown that 70% of all logic functions (per macrocell)
require three product terms or less.
The macrocell structure of MAX has been optimized to handle
variable product term requirements. As shown in Figure 4, each
macrocell consists of a product term array and a configurable register. In the macrocell, combinatorial logic is implemented with
three product terms ORed together, which then feeds an XOR
gate. The second input to the XOR gate is also controlled by a
product term, providing the ability to control active HIGH or active LOW logic and to implement T- and lK-type flip-flops. The
MAX +PLUS software will also use this gate to implement complex mutually exclusive-OR arithmetic logic functions, or to do
n
1"'1
r---
I
1
1
1
1
1
1
1
P
I
A
The expander product terms, as shown in Figure 5, are fed by the
dedicated input bus, the programmable interconnect array, the
macrocell feedback, the expanders themselves, and the I/O pin
feedbacks. The outputs of the expanders then go to each and every product term in the macrocell array. This allows expanders to
be "shared" by the product terms in the logic array block. One
expander may feed all macrocells in the LAB, or even multiple
product terms in the same macrocell. Since these expanders feed
the secondary product terms (preset, clear, clock, and output enable) of each macrocell, complex logic functions may be implemented without utilizing another macrocell. Likewise, expanders
may feed and be shared by other expanders, to implement complex multilevel logic and input latches.
r----------------,1
MACROCELL
I
N
P
U
T
S
DeMorgan's Inversion, reducing the number of product terms required to implement a function.
If more product terms are required to implement a given function, they may be added to the macrocell from the expander
product term array. These additional product terms may be added to any macrocell, allowing the designer to build gate-intensive
logic, such as address decoders, adders, comparators, and complex state machines, without using extra macrocells.
The register within the macrocell may be programmed for either
D, 1; JK, or RS operation. It may alternately be configured as a
flow-through latch for minimum input-to-output delays, or bypassed entirely for purely combinatorial logic. In addition, e~h
register supports both asynchronous ~t ~d clear, a1lo~g
asynchronous loading of counters of shift regISters, as found m
many standard TTL functions. These registers may be clocked
with a synchronous system clock, or clocked independently from
the logic array.
ExpanderProductTenns
~
APIIAY
I- ~ B~~
lL
-
110
PINS
r----------------,1
1
110
PINS
rI
N
P
U
T
S
~
I
~
EXPANDER
[
PRODUCT
TERM
ARRAY
1
1
1
1
reLft
..r
V
1
1
~---------------C340-3
..... ,
PROGRAMMABLE
INTERCONNECT
C340-2
ARRAY
Flgure 2_ 'JYpicallAB Block Diagram
Figure 3. 7C344lAB Block Diagram
4-183
1
•
-=~PRFSS
CY7C340 EPLD Family
- , SEMICONDUCTOR
PROGRAMMABLE
INTERCONNECT
SIGNALS
16
MACROCELL
FEEDBACKS
(32 FOR 7C344)
•
•
•
•
0
0
0
I/O OUTPUT
ENABLE
0
0
0
0
"/
PRESET
0
PROGRAMMABLE FLIP-FLOP
(D, TJK
,
SR)
REGISTERED OR FLOWTHROUGH-LATCH OPERATION
PROGRAMMABLE CLOCK
ASYNC CLEAR AND PRESET
0
0
0
0
0
0
0
p
0
-
0
0
TO
I/OCONTR OL
0
0
Q
0
0
0
00
r-
0
00
0
00
r-
0
00
0
00
0
00
0
00
0
00
0
0
ARRAY
CLOCK
I
r--
>
C
--4
I
I
0
0
CLEAR
0
0
0
0
r.
0
~
0
0
MACROCELL
FEEBACK
0
0
0
NOTE: ONE SYSTEM CLOCK PER LAB
0
TO
PIA
0
8
DEDICATED
INPUTS
32
EXPANDER
PRODUCT
TERMS
(64 FOR 7C344)
C340-4
Figure 4_ Macrocell Block Diagram
Functional Description (continued)
I/O Block
MACROCELL
P-TERMS
Separate from the macrocell array is the I/O control block of the
LAB. Figure 6 shows the I/O block diagram. The three-state buffer
is controlled by a macrocell product term and the drives the I/O
pad. The input of this buffer comes from a macrocell within the associated LAB. The feedback path from the I/O pin may feed other
blocks within the LAB, as well as the PIA.
By decoupling the I/O pins from the flip-flops, all the registers in
the LAB are "buried," allowing the I/O pins to be used as dedicated
outputs, bidirectional outputs, or as additional dedicated inputs.
Therefore, applications requiring many buried flip-flops, such as
counters, shift registers, and state machines, no longer consume
both the macrocell register and the associated I/O pin, as in earlier
devices.
The Programmable Interconnect Array
•
•
EXPANDER
P-TERMS
C340-5
Figure 5. Expander Product Terms
PLD density and speed has traditionally been limited by signal
routing; Le., getting signals from one macrocell to another. For
smaller devices, a single array is used and all signals are available to
all macrocells. But as the devices increase in density, the number of
signals being routed becomes very large, increasing the amount of
silicon used for interconnections. Also, because the signal must be
global, the added loading on the internal connection path reduces
4-184
CY7C340 EPLD Family
Functional Description (continued)
the overall speed performance of the device. The MAX architecture solves these problems. It is based on the concept of small,
flexible logic array blocks that, in the later devices, are interconnected by a PIA.
The PIA solves interconnect limitations by routing only the signals needed by each lAB. The architecture is designed so that
every signal on the chip is within the PIA. The PIA is then programmed to give each lAB access to the signals that it requires.
Consequently, each lAB receives only the signals needed This
effectively solves any routing problems that may arise in a design
without degrading the performance of the device. Unlike masked
or programmable gate arrays, which induce variable delays dependent on routing, the PIA has a fixed delay from point to point.
This eliminates undesired skews among logic signals, which may
cause glitches in internal or external logic.
MAX+PLUS Development System Description
The PLDS-MAX+PLUS (Programmable Logic Design System)
is a unified CAE system for designing logic with Cypress's
CY7C340 family of EPLDs (Figure 7). PLDS-MAX+PLUS includes design entry, design processing, timing simulation, and device programming support. PLDS-MAX+PLUS runs on IBM
PS/2, PC-AT, or compatible machines, and provides tools to
quickly and efficiently create and verify complex logic designs.
The MAX + PLUS software compiles designs for MAX EPLDs
in minutes. Designs may be entered with a variety of design entry
mechanisms. MAX + PLUS supports hierarchical entry of both
Graphic Design Files (GDFs) with the MAX+PLUS Graphic
Editor, and 'Thxt Design Files (TOFs) with the Advanced Hardware Description Langnage (AHDL). The Graphic Editor offers
advanced features such as multiple hierarchy levels, symbol editing, and a library of 7400 series devices as well as basic SSI gates.
AHDL designs may be mixed into any level of the hierarchy or
used on a standalone basis. AHD L is tailored especially for
EPLD designs and includes support for complex Boolean and
arithmetic functions, relational comparisons, multiple hierarchy
levels, state machines with automatic state variable assignment,
truth tables, and function calls.
FROM
MACROCELL
IN lAB
THREE-8TATE
BUFFER
TO PIA (lAB FOR 7C344)
Figure 6.1/0 Block Diagram
0341).6
In addition to multiple design entry mechanisms, MAX + PLUS
includes a sophisticated compiler that uses advanced logic synthesis and minimization techniques in conjunction with heuristic fitting rules to efficiently place designs within MAX EPLDs. A programming file created by the compiler is then used by
MAX+PLUS to program MAX devices with the QP2-MAX
programming hardware.
Simulations may be performed with a powerful, event-driven timing simulator. The MAX + PLUS Simulator interactively displays
timing results in the MAX + PLUS Waveform Editor. Hardcopy
table and waveform output is also available. With the Waveform
Editor, input vector waveforms may be entered, modified,
grouped, and ungrouped. In addition, the Waveform Editor compares simulation runs and highlights the differences.
The integrated structure of MAX + PLUS provides features such
as automatic error location and delay prediction. If a design contains an error in either a schematic or a text file, MAX + PLUS
flags the error and takes the user to the actual location of the error in the original schematic or text file. In addition, propagation
delays of critical paths may be determined in both the Graphic
and 'Thxt Editors with the delay predictor. After the source and
destination nodes are tagged, the shortest and longest timing delays are calculated.
MAX + PLUS provides a seamless design framework using a consistent graphical user interface throughout. This framework simplifies all stages ofthe design cycle: design entry, processing, verification, and programming. In addition, MAX + PLUS offers
online help to aid the user.
Design Entry
MAX + PLUS offers both graphic and text design entry methods.
ODFs are entered with the MAX+PLUS Graphic Editor; Boolean equations, state machines, and truth tables may be entered
with the MAX+PLUS 'Thst Editor using AHDL. The ability to
freely mix graphics and text files at all levels of the design hierarchy and to use either a top-down or bottom-up design method
makes design entry simple and versatile.
Graphic Editor
The Graphic Editorprovides amouse-driven, multi-windowed environment in which commands are entered with pop-up menus or
simple keystrokes. The Hierarchy Display window, shown at the
top, lists all schematics used in a design. The designer navigates
the hierarchy by placing the cursor on the name of the design to be
edited and clicking the left mouse button. The 'Ibtal View window
(next to the Hierarchy window) shows the entire design. By c1ickingon an area in this window, the user is moved to that area of the
schematic. The Error Report window lists all warnings and errors
in the compiled design; selecting an error with the cursor highlights the problem node and symbol. A design is edited in the main
area, which may be enlarged by closing the auxiliary windows.
When entering a design, the user may choose from a library of
over two hundred 7400 series and special-purpose macrofunctions that are all optimized for MAX architecture. In addition,
the designer may create custom functions that can be used in any
MAX +PLUS design.
1b take advantage of the hierarchy features, the user first saves
the entered design so the Graphic Editor can automatically
create a symbol representing the design. This symbol may be
used in a higher-level schematic or in another design. It may also
be modified with the Symbol Editor.
4-185
"
~~
e
~
....I
~
a
=
".
~
b
Figure 7. MAX+PWS Block Diagram
e....~
~
CY7C340 EPLD Family
Graphic Editor (continued)
Thg-and-drag editing is used to move individual symbols or entire
areas. lines stay connected with orthogonal rubberbanding. A
design may be printed on an Epson FX-compatible printer, or
plotted on an HP- or Houston Instruments-compatible plotter.
Symbol Editor
The MAX +PLUS Symbol Editor enables the designer to create
or modify a custom symbol representing a GDF or IDF. It is also
possible to modify input and output pin placement of an automatically generated symbol.
The created symbol represents a lower-level design, described by
a GDF or IDF. The lower-level design represented by the symbol may be displayed with a single command that invokes either
the Graphic Editor for schematics or the 'lext Editor for AHDL
designs.
AHDL
The Advanced Hardware Description Language (AHDL) is a
high-level, modular language used to create logic designs for
MAX EPLDs. It is completely integrated into MAX +PLUS, so
AHDL files may be created, edited, compiled, simulated, and
programmed from within MAX +PLUS.
AHDL provides support for state machine, truth tables, and
Boolean equations, as well as aritbmetic and relational operations. AHDL is hierarchical, which allows frequently used functions such as TTL and bus macrofunctions to be incorporated in a
design. AHDLsupports complex aritbmetic and relational operations, such as addition, subtraction, equality, and magnitude comparisons, with the logic functions automatically generated. Standard Boolean functions, including AND, OR, NAND, NOR,
XOR, and SNOR are also included. Groups are fully supported
so operations may be performed on groups as well as on single
variables. AHDL also allows the designer to specify the location
of nodes within MAX EPLDs. 1bgether, these features enable
complex designs tobe implemented in a concise, high-level description.
Text Editor
The MAX +PLUS 'lext Editor enables the user to view and edit
text files within the MAX + PLUS environment. Any ASCII text
file, including Vector Files, Thble Files, Report Files, and AHDL
'lext Design Files (IDFs), may be viewed and edited without having to exit to DOS.
The 'lext Editor parallels the Graphic Editor's menu structure. It
has a Hierarchy Display and a 1btal View window for moving
through the hierarchy levels and around the design. It includes
automatic error location and hierarchy traversal. If an error is
found in a IDF during compilation, the 'lext Editor is automatically invoked and the line of AHDL code where the error occurred is highlighted In addition, a design may use both text and
graphic files. As the designer traverses the hierarchy, the Thxt
Editor is invoked for text files, and the Graphic Editor is invoked
for schematics.
Symbol Libraries
The library provided with MAX +PLUS contains the most commonly used 7400 series devices such as counters, decoders, encoders, shift registers, flip-flops, latches, and multipliers, as well
as special bus macrofunctions, all of which increase design productivity. Because of the flexible architecture of MAX EPLDs
(that includes asynchronous preset and clear), true TTL device
emulation is achieved. Cypress also provides special-purpose bus
macrofunctions for designs that use buses. All macrofunctions
have been optimized to maximize speed and utiIization. Refer to
the MAX +PLUS TTL MacroFunctions manual for more information on TTL macrofunctions.
Design Processing
The MAX +PLUS Compiler processes MAX designs. The Compiler offers options that speed the processing and analysis of a design. The user can set the degree of detail of the Report File and
the maximum number of errors generated. In addition, the user
may select whether or not to extract a netlist file for simulation.
The Compiler compiles a design in increments. If a design has
been previously processed, only the portion of the design that has
been changed is re-extracted, which decreases the compilation
time. This "Make" facility is an automatic feature of the Compile
'
command.
The first module of the Compiler, the Compiler Netlist Extractor,
extracts the netlist that is used to define the design from each file.
At this time, design rules are checked for any errors. If errors are
found, the Graphic Editor is invoked when the error appears in a
GDF, and the 'lext Editor is invoked when the error appears in a
IDF. The Error Report window in both editors highlights the location of the error. A successfully extracted design is built into a
database to be used by the Logic Synthesizer.
The Logic Synthesizer module translates and optimizes the userdefined logic for the MAX architecture. Any unused logic within
the design is automatically removed. The Logic Synthesizer uses
expert system synthesis rules to factor and map logic within the
multilevel MAX architecture. It then chooses the approach that
insures the most efficient use of silicon resources.
The next module, the Fitter, uses heuristic rules to optimally
place the synthesized design into the chosen MAX EPLD. For
MAX devices that have a Programmable Interconnect Array
(pIA), the Fitter also routes the signals across this interconnect
structure, so the designer doesn't have to worry about placement
and routing issues. A Report File (.RPI') is issued by the Fitter,
which shows design implementation as well as any unused resources in the EPLD. The designer can then determine how
much additional logic may be placed in the EPLD.
A Simulator Netlist File (.SNF) may be extracted from the compiled design by the Simulator Netlist Extractor if simulation is desired. Finally, the Assembler creates a Programmer Object File
(.POF) from the compiled design. This file is used with the
QP2-MAXprogramming hardware to program the desired part.
Delay Prediction and Probes
MAX +PLUS includes powerful analysis tools to verify and analyze the completed design. Delay analysis with the delay predictor
may be performed interactively in the Graphic Editor, or in the
Simulator. The Simulator is interactive and event-driven, yielding
true timing and functional characteristics of the compiled design.
The delay predictor provides instant feedback about the timing of
the processed design. After selecting the start point and end point
of a path, the designer may determine the shortest and longest
propagation delays of speed-critica1 paths.
Also, a designer may use probes to mark internal nodes in a design. The designer may enter a probe by placing the cursor on any
node in a graphic design, selecting the SPE (Symbol:Probe:Enter) command, and then entering a unique name to define the
probe. This name may then be used in the Graphic Editor, Simulator, and Waveform Editor to reference that node, so that
lengthy hierarchical path names are avoided.
4-187
•
CY7C340 EPLD Family
Simulator
Input stimuli can be defined with a straightforward vector input
language, or waveforms can be directly drawn using the Waveform Editor. Outputs may also be viewed in the Waveform Editor, or hardcopy table and waveform files may be printed.
The Simulator used the Simulator Nedist File (SNP) extracted
from the compiled design to perform timing simulation with
1/10-nanosecond resolution. A Command File may be used for
batch operation, or commands may be entered interactively. Simulator commands allow the user to halt the simulation dependent
on user-defined conditions,to force and group nodes, and perform AC detection.
If flip-flop set-up or hold times have been violated, the Simulator
warns the user. In addition, the minimum pulse width and period
of oscillation may be defined. If a pulse is shorter than the minimum pulse width specified, or if a node oscillates for longer than
the specified time, the Simulator issues a warning.
Waveform Editor
The MAX +PLUS Waveform Editor provides a mouse-driven environment in which timing waveforms may be viewed and edited.
It functions as a logic analyzer, enabling the user to observe simulation results. Simulated waveforms may be viewed and manipulated at multiple zoom levels. Nodes may be added, deleted, and
combined into buses, which may contain up to 32 signals represented in binary, octal, decimal, or hexadecimal formaL Logical
operators may also be performed on pairs of waveforms, so that
waveforms may be inverted, ORed, ANDed, or XORed together.
The Waveform Editor includes sophisticated editing features to
define and modify input vectors. Input waveforms are created
with the mouse and familiar text editing commands. Waveforms
may be copied, patterns may be repeated, and blocks may be
moved and copied. For example, all or part of a waveform may be
contracted to simulate the increase in clock frequency.
The Waveform Editor also compares and highlights the difference between two different simulations. A user may simulate a
design, observe and edit the results, and then resimulate the design, and the Waveform Editor will show the results superimposed upon each other to highlight the differences.
All MTA options may be listed in an MTA command file. With
this file, the user may specify all information needed to configure
the output.
SNF2GDF Converter
SNF2GDF converts the SNP into logic schematics represented
with basic gates and flip-flop elements. It uses ,the SNPs delay
and connection information lind creates a series of schematics
fully annotated with propagation delay and set-up and hold information at each logic ga,te. Certain speed paths of a design may be
specified for conversioli, so the user may graphically analyze only
the paths considered critical.
If State Machine or Boolean Equation design entry is used,
SNF2GDF shows how the high-level description has been synthesized and placed into the MAX architecture.
Device Programming
PLDS-MAX contains the basic hardware and software for programming the MAX EPLD family. Adapters are included for
programming the CY7C344 (DIP and PLCC) and CY7C342
(PLCC) devices. Additional adapters supporting other MAX devices may be purchased separately. MAX +PLUS programming
software drives the QP2-MAX programming hardware. The designer can use MAX+PLUS to program and verify MAX
EPLDs. If the security bit of the device is not set to ON, the designer may also read the contents of a MAX device and use this
information to program additional devices.
System Requirements
Minimum System Configuration
mM PS/2 model 50 or higher, PClAT or compatible
computer.
PC-DOS version 3.1 or higher.
640 Kbytes RAM.
EGA, VGA or Hercules monochrome display.
2O-MB hard disk drive.
1.2-MB 5W' or 1.44-MB 3'h" floppy disk drive.
MAX + PLUS Timing Analyzer (MTA)
The MAX +PLUS Timing Analyzer (MTA) provides user-configurable reports that assist the designer in analyzing critical delay
paths, set-up and hold timing, and overall system performance of
any MAX EPLD design. Critical paths identified by these reports
may be displayed and highlighted.
Timing delays between multiple source and destination nodes
may be calculated,thus creating a connection matrix giving the
shortest and longest delay paths between all source and destination nodes specified. Or, the designer may specify that the detailed paths and delays between specific sources and destinations
be shown.
The set-up/hold option provides set-up and hold requirements at
the device pins for all pins that feed the D, CLK, or ENABLE
inputs of flip-flops and latches. Critical source nodes may be specified individually, or set-up and hold at all pins may be calculated. This information is then displayed in a table, one set of setup and hold times per f1ip-flop/latch.
The MTA also allows the user to print a complete list of all accessible nodes in a design; i.e., all nodes that may be displayed during simulation or delay prediction.
Three-button serial port mouse.
Recommended System Configuration
IBM PS/2 model 70 or higher, or Compaq 386 20-MHz
computer.
4-188
PC-DOS version 3.3.
640 Kbytes of RAM plus 1 MB of expanded memory with LIM
3.2-compatible EMS driver.
VGA graphics display.
2O-MB hard disk drive.
1.2-MB 5~I or 1.440MB 3~ floppy disk drive.
Three-button serial port mouse.
~
--=-_'
-
CY7C340 EPLD Family
~~CYPRESS
SEMlCONDUClDR
Device Adapters
Ordering Information
CY3200 MAX +PillS System including:
CY3201
MAX + PLUS software, manuals,
and key.
CY3202
QP2-MAX Pill programmer with
CY3342 and CY3344 adapters.
CY3220 MAX + PLUS II System including:
CY3340
Adapterfor CY7C341 in PLCCpackages.
CY3340F
Adapter for CY7C341 in PGApackages.
CY3342
Adapterfor CY7C342 in PLCCpackages.
CY3342F
Adapter for CY7C342 in Fiatpack
packages.
CY3342R
Adapter for CY7C342 in PGApackages.
CY3221
MAX + PLUS II software for Windows 386, manuals, and key.
CY3344
Adapter for CY7C344 in DIP and PLCC
packages.
CY3202
QP2- MAX PLD programmer with
CY3342 and CY3344 adapters.
CY33435
Adapterfor CY7C343 in PLCCpackages.
II
In
C
..J
a..
Document#: 38-00087-8
4-189
CY7C341
PRELIMINARY
CYPRESS
SEMICONDUCTOR
192-Macrocell MAX® EPLD
software or by the model shown in
Features
Logic Array Blocks
• 192 macroceUs iD 12 LABs
• 8 dedicated Inputs, 64 bidirectional
I/O pins
• Programmable iDterconnect array
• 384 expander product terms
• Available In 84.pin HLCe, PLCC. and
PGA packages
There are 12 logic array blocks in the
CY7C341. Each lAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32
expanders, and an I/O block. The lAB is
fed by the programmable interconnect
array and the dedicated input bus. All
macrocell feedbacks go to the macrocell
array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell
array. All I/O feedbacks go to the programmable interconnect array so that
they may be accessed by macrocells in
other LABs as well as the macrocells in
the LAB in which they are situated.
Externally, the CY7C341 provides 8 dedicated inputs, one of which may be used as
a system clock. There are 641/0 pins that
may be individually configured for input,
output, or bidirectional data flow.
Functional Description
The CY7C341 is an Erasable Programmable Logic Device (EPW) in which
CMOSEPROMceilsareusedtoconfigure
logic functions within the device. The
MAX architecture is 100% user configurable allowing the devices to accommodate
a variety of independent logic functions.
The 192macrocells in the CY7C341 aredivided into 12 Logic Array Blocks (LABs).
16perLAB. There are 384 expander product terms. 32 per LAB. to be used and
shared by the macrocells within each LAB.
Each LAB is interconnected with a programmable interconnect array. allowing all
signals to be routed throughout the chip.
The speed and density of the CY7C341 allows it to be used in a wide range of applications, from replacement of large
amounts of 7400 series TIL logic, to complex controllers and multifunction chips.
Withgreater than37 times the functionality
of20-pin PWs. the CY7C341 allows the
replacement of over 75 TIL devices. By
replacing large amounts of logic. the
CY7C341 reduces board space. part count,
and increases system reliability.
Each LAB contains 16 macrocells. In
LABs A. F, G, and L. 8 macrocells are
connected to I/O pins and 8 are buried,
while for LABs B, C, D, E, H, I, 1, and K,
4 macrocells are connected to I/O pins
and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there
are 32 single product term logic expanders
in each lAB. Their use greatly enhances
the capability of the macrocells without
increasing the number of product terms in
each macrocell.
Selection Guide
Programmable Interconnect Array
The Programmable Interconnect Array
(PIA) solves interconnect limitations by
routing only the signals needed by each
logic array block. The inputs to the PIA
are the outputs of every macrocell within
the device and the I/O pin feedback of every pin on the device.
Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fIXed delay.
This eliminates undesired skews among
logic signals, which may cause glitches in
internal or external logic. The fixed delay,
regardless of programmable interconnect
array configuration, simplifies design by
assuring that internal signal skews or races
are avoided. The result is ease of design
implementation, often in a single pass,
without the multiple internal logic placement and routing iterations required for a
programmable gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C341 may be
easily determined using MAX+PLUS@
Maximum Access Time (ns)
Maximum 3.)erating
Current (rnA
Commercial
IndustrIal
Military
Maximum Standby
Commercial
Current (rnA)
Industrial
MilitalY
MAX and MAX + PLUS are regIStered trademarks of A1tera Corporation.
4-190
7C341-30
30
380
480
360
435
Figure 1. The CY7C341 has fixed internal
delays, allowing the user to determine the
worst case timing delays for any design.
For complete timing information, the
MAX + PLUS software provides a timing
simulator.
Design Recommendations
For proper operation, input and output
pins must be constrained to the range
GND.s.(VINorVOUT).s. Vee. Unused
inputs must always be tied to an appropriate logic level (either Vee or GND).
Each set of Vee and GND pins must be
connected together directly at the device.
Power supply decoupling capacitors of at
least 0.2 !IF must be connected between
Vee and GND. For the most effective decoupling, each Vee pin should be separately decoupled to GND, directly at the
device. Decoupling capacitors should
have good frequency response, such as
monolithic ceramic types.
Design Security
The CY7C341 contains a programmable
design security feature that controls the
access to the data programmed into the
device. If this programmable feature is
used, a proprietary desigu implemented
in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data,
may be reset simply by erasing the device.
The CY7C341 is fully functionally tested
and guaranteed through complete testing
of each programmable EPROM bit and
all internal logic elements thus ensuring
100% programming yield.
The erasable nature of these devices allows test programs to be used and erased
during early stages of the production
flow. The devices also contain on-board
logic test circuitry to allow verification of
function and AC specification once encapsulated in non-windowed packages.
7C341-35
35
380
480
480
360
435
435
7C341-40
40
480
435
~
--~PRESS
PRELIMINARY
~, SEMlCONDUCIOR
CY7C341
Logic Block Diagram
.....
.....
r1 (A6)
INPUT/ClK '"""-
2 (AS)
INPUT
41 (1<6)
INPUT
INPUT _
42 (J6)
LAB A
4
(C5)
5
(AO)
6
7
8
9
(84)
(A3)
(A2)
(83)
10
11
(82)
(A1)
-
g:-
~
a--
MACROCEL.4
. MACIIOCEL. 5
MACROCEL.8
LABB
(C2)
(81)
(C1)
(D2)
!::::
~
Il'--
rv-
'----,I
Vt--
(F2)
Vt-
rv-
(F3)
..!.~
Fe
DMACROCELL 37 - 48
A
P
I
1""'-
A
~
LAB 0
(00)
(G1)
(F1)
(H1)
~
a--
..!.~
MACRI :EL.50
MACROCEL . 52
MACROCELL 53 - 64
~
lit-IV--f----.J\
'"
Vt-
rv---
:---,;
27
28
29
30
(H2)
(J1)
(1<1)
(J2)
~
• "'-J.
LABE
MACRI 'CEL.85
MACRI CEL.67
Vt--
f..--J\
~
Vt-
IV--MACROCELL 89 - 80
rv---
_LABF
38
(L1)
(K2)
(1<3)
(L2)
(La)
(1<4)
~2.
8=
~
(L4)
(J5)
A
...I\.
.....-
'"
rv---
:---,;
3, 24, 45, 66 (85, G2, K7, E10)
18,19,39,40,80,61,81,82 (E1, E2, KS, L5, G10, G11, A7, 87)
C>C>-
Vee
GNO
4-191
II)
Q
...J
11.
FlS
54
55
56
57
(J10)
(K11)
(J11)
(H10)
58
59
62
83
(H11)
(F10)
(00)
MACROCELL 117 - 128
..!.J.
LAB I
MACRC :EL 130
MACROCEL .132
~
(F9)
MACROCELL 133 - 144
..!.
7
LABJ
M, GRC ;EL 148
MACROCEL 148
~
~
64 (F11)
65 (E11)
67 (E9)
68 (011)
MACROCELL 149 - 160
~J.
MACRC
LABK
181
MACRC
183
~
69 (010)
~
73
74
75
78
70 (C11)
71 (B11)
72 (C10)
MACROCELL 185 - 176
~
7 ,\
LABL
n
(A11)
(B10)
(89)
(A10)
(A9)
78 (88)
79(A6)
.A
MACROCELL 89 . 96
~
48(L6)
47 (L8)
48 (1<6)
49 (L9)
50 (L10)
51 (K9)
52 (L11)
53 (K10)
LABH
'"
:---,;
31
32
33
34
35
38
37
'"
Vt-
~
MACROCEL 115
MACROCEI .its
f..--J\
rv-
:---,;
22
23
25
26
..!.J.
-y
f----.J\
LABC
LABG
MACROCELL 105 ·112
f..---.J\
:---,;
(E3)
(J7)43
MACROCE .102
'r-
(01)
(L7) 44
INPUT
.A
MACROCELL 21 - 32
16
17
20
21
(C7)83
INPUT
MACROCEL .100
-y
'If
(C6)84
INPUT
-5
--"
..!.~
MACEl 'eEL .19
~
~
;----f'
MACROCELL 9 . 16
12
13
14
15
SYSTEM CLOCK
~.7
INPUT
80 (88)
MACROCELL 185 . 192
() • PERTAIN TO SHIN PGA PACKAGE
C341-1
.
.~
PRELIMINARY
_'~CfOR
CY7C341
Pin Configurations
PGA
Bottom View
1110 9 8 7 6 5 4 3 2 U 84 83 B2 81 8079 78
n
7.
13
I/O
GND
I/O
~
36
~
~
110
29
110
32
I/O
I/O
GND
~
36
39
INPUT
41
110
110
110
110
I/O
I/O
110
I/O
I/O
28
110
30
110
38
INPUT INPUT
42
~
H
110
2B
110
21
G
I/O
23
Vee
I/O
I/O
I/O
25
20
110
21
GND
18
GND
19
110
11
110
16
110
15
C
110
l'
110
12
•
B
I/O
13
110
11
110
9
I/O
8
110
10
I/O
8
I/O
7
I/O
5
F
I/O
1C341
I/O
I/O
GND
GND
110
110
I/O
110
110
110
I/O
110
I/O
~~~~~u~~~~~~~~~u~~oo~~~
M
110
110
110
D
A
INPUT
44
I/O
41
110
Vee
I/O
~
~
I/O
51
110
22
24
Vee
Vee
~
110
16 15
GND
~
I/O
34
K
110
110
I/O
I/O
I/O
I/O
GND
110
I/O
110
110
110
31
1C341
~
110
50
110
110
I/O
55
53
I/O
M
I/O
I/O
51
110
58
I/O
62
GND
60
GND
61
I/O
63
I/O
59
110
84
110
Vee
61
66
110
65
INPUT INPUT
84
83
110
GND
80
B2
INPUTI
IN~ln CLK GND
1
81
Vee
3
56
69
110
68
I/O
12
110
10
I/O
110
4
~
I/O
78
I/O
15
I/O
7.
110
11
I/O
79
110
I/O
76
110
73
C341-2
n
10
11
C341-3
"''''"'''''~
DELAY
~
~
IN
tEXP
REGISTER
-tI CONTROL
LOGIC ARRAY~vIt;
DEI.J\
tClR
INPUT
DELAY
tiN
-~
M
-~
tLAC
LOGIC ARRAY
DELAY
lLAD
I
tpRE
I
tRSU
J
OUTPUT
DELAY
--t
tRD
teoMB
lLATCH
tRH
too
txz
tzx
INPUTI
OUTPUT
--c
SYSTEM CLOCK DELAY IICS
~
PIA
DELAY
IplA
'---!I
~
I
CLOCK
DELAY
I
IIC
I
I
I
I
1/0 DELAY
110
LOGIC ARRAY
DELAY
IFD
L
I
l
I
Figure 1. CY7C341 Internal Timing Model
4-192
C341-.
~
..
~PRE§
~iF
PRELIMINARY
CY7C341
SEMICCt-lDUCIDR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. -6S0Cto +lS0°C
Ambient Temperaturewith
PowerApplied ........................... O°Cto +70°C
Maximum Junction Temperature
(Under Bias) ................................... lS0°C
Supply Voltage to Ground Potential. . . . . . .. - 2.0V to + 7.0V
MaximumPowerDissipation .................... 2SoomW
DC Vee or GND Current. . . . . . . . . . . . . . . . . . . . . . .. SOO rnA
DC Output Current, per Pin ........... -25 rnA to +25 rnA
DC Input Voltagel l ] .................... -2.0Vto +7.0V
DC Program Voltage .................... -2.0Vto +13.5V
Operating Range
Ambient
Thmperature
Range
Commercial
O°Cto +70°C
Vee
SV±S%
-40°Cto +8SoC
SV± 10%
-55°C to +125°C(Case)
5V± 10%
Industrial
Military
Parameters
I I)
Vee = Min., IOH = - 4.0 rnA
VOH
VOL
Vm
Output LOW Voltage
Input HIGH Level
VlL
IIX
Input LOW Level
Input Current
Ioz
Output Leakage Current
los
Output Short
Circuit Current
Iccl
Power Supply
Current (Standby)
VI = VeeorGND
(No Load)
PowerS~p!y
VI = Vcc or GND (No Load)
f = 1.0 MHz[3, 5]
Iecz
GND:::::; VIN:::; Vee
Vo = VccorGND
Vee = Max., VOUT = GND[3,4]
tR (Recommended)
Input Rise Time
tF (Recommended)
Input Fall Time
D.
Units
V
O.4S
V
2.2
-0.3
Vcc+O.3
0.8
V
V
-10
+10
-40
-30
+40
-90
!lA
!lA
Vcc = Min., IOL = 8 rnA
Current!:
...J
CY7C341
Min.
Max.
2.4
Thst Conditions
Description
Output HIGH Voltage
Com'!
rnA
360
435
Mil/Ind
Com'l
rnA
rnA
rnA
380
480
Mil/Ind
rnA
ns
100
100
ns
Capacitance[6]
Parameters
CIN
COUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
Notes:
1. MinimumDCinputis -O.3Y. Duriogtransitious, the inputs may undershoot to - 2.0V for periods less than 20 ns.
2. 'JYpicalvalues are forTA = 25°C and Vee = 5V.
3. Guaranteed but not 100% tested.
4. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. Vour = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
5.
6.
Max.
Units
10
20
pF
pF
Thisparameterismeasuredwithdeviceprogrammedasa 16-bitcounter in each LAB and is tested periodically by sampling production
material.
Part (a) in AC Test Load and Waveforms is used for all parameters except tER and txz, which is usedforpart (b)inACThstLoad andWaveforms. All external timing parameters are measured referenced to external pins of the device.
AC Test Loads and Waveforms
R1464n
5V<>-----....,
5V~R1464.o.
--+
OUTPUT<>---.....
50PFI
ALL INPUT PULSES
OUTPUT
R2
250.0.
5pF
3.OV ----...I.~9O%~-----
I
R2
250.0.
00
~~
GND
INCLUDING
JIGAND _
SCOPE -
00
Equivalent to:
•
o
Electrical Characteristics Over the Operating Rangel2]
THEvENIN EQUIVALENT (cDmmercial/military)
1aan
OUTPUT 00----"'.""
..•...- - - 0 0 1.75V
4-193
C341-6
~
;~PRF.SS
-.
,
PRELIMINARY
CY7C341
SEMICONDUCTOR
External Synchronous Switching Characteristics OvertheOperatingRangel4]
7C341-30
Parameters
tpOl
tPD2
tPD3
Description
Min.
Dedicated Inp.ut to Combinatorial
Output Delay[7]
Com'l
I/O Input to Combinatorial
Output Delay[8]
Com'l
Dedicated Input to Combinatorial
Output Delaywith Expander Delayf9]
Max.
7C341-35
Min.
30
45
55
Com'l
tEA
Input to Output Enable Delayl:J, .'J
Com'l
Input to Output Disable DelaylbJ
59
75
30
35
Synchronous Clock Input to
Output Delay
tco2
Synchronous Clock to Local Feedback
to Combinatorial Output[3, 11]
tS1
30
tS2
tH
tWH
Com'l
Synchronous Clock Input Low Time
20
Asynchronous Clear Width!:J, bJ
Asynchronous Clear Recoveryl:J, .'J
Com'l
tpw
Asynchronous Clear to Registered
Output Delay[5]
AsynchronousPreset Width[:J, bJ
AsynchronousPreset Recovery Timel:J, bJ
Com'l
4'-194
ns
12.5
10
15
12.5
ns
12.5
15
35
30
ns
35
30
40
35
ns
35
30
Com'l
Mil
0
12.5
10
40
35
ns
35
30
30
40
35
35
Mil
tpR
ns
0
Mil
Com'l
52
0
0
Mil
tRO
ns
45
Mil
tRR
28
45
39
Mil
Com'l
ns
25
Mil
tRW
ns
48
25
Mil
Com'l
23
42
42
Mil
tWL
ns
20
35
Mil
Com'l
ns
40
20
Mil
Input Hold Time from Synchronous
Clocklnputf6]
Synchronous Clock Input High Time
16
Com'l
Com'l
ns
40
35
Mil
I/O Input Set-up Time to
Synchronous Clock Inputf8]
90
35
Com'l
Com'l
ns
35
Com'l
Dedicated Inp!!t or FeedbackSet-uf,
Time to Synchronous Clock Output 6,12]
65
75
Mil
Mil
tC01
ns
55
Mil
tER
ns
65
55
44
Mil
ns
40
35
35
Units
40
55
Com'l
Max.
ns
35
Mil
I/O Input to Combinatorial
Output Delaywith Expander Delayf3, 10]
7C341-40
Min.
35
Mil
tpD4
Max.
ns
40
PRELIMINARY
CY7C341
External Synchronous Switching Characteristics Over the Operating Range[4J(continued)
7C341-30
Parameter
tpo
tCF
tp
fMAXI
fMAX2
Description
Asynchronous Preset to Registered
Output Delayl6J
Synchronous Clock to Local
Feedback Input!3. 13J
External S~chronous Clock Period
(1/tMAX3) J
External Feedback Maximum Frequency
(l/(tc01 + tSl»[3, 14J
Internal Local Feedback Maximum Fre~uen-
cy, lesser of (1/(tsl
fMAX3
fMAX4
tOH
+ tcF» or (1/lc01)13. 5J
Data Path Maximum Frequency, least of
1/(twr.. + tWH), 1/(tSI +
or (1/tC01)13. 16J
tw,
Maximum Register 'RIggle Frequency
(l/(tWL + tWH»[3.17]
Output Data Stable Time from Synchronous
Clock Input!3. 18J
Min.
Com'l
Max.
7C341-35
Min.
30
7C341-4O
Min.
3
40
us
5
Mil
5
Com'l
20
Com'l
27.7
Mil
43
33
50
40.0
Mil
33
Com'l
Mil
40.0
Com'l
50.0
Mil
Com'l
3
MHz
3
28.5
MHz
33.3
MHz
33.3
us
3
12. Ifdata is applied to an I/O input for capture by a macrocell register, the
I/O pin set-up time minimums should be observed. These parameters
are tS2 for synchronous operation and tAS2 for asynchronous opera-
tion.
13. This specification is a measure of the delay associatedwith the internal
register feedback path. This is the delay from synchronous clock to
lAB logic array input. This delay plus the register set-up time, tSl, is
the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same lAB.
This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed
to be local originating within the same lAB.
15. This specification indicates the guaranteed maximum frequency at
which a state machine, withinternal-onlyfeedback, can operate. If register output states must also control external points, this frequency can
still be observed as long as this frequency is less than 1lteOl.
16. This frequency indicates the maximum frequency at which the device
may operate in data path mode (dedicated input pin to output pin).
This assumesdatainputsignalsare applied to dedicated input pins and
no expander logic is used. If any of the data inputs are I/O pins, tS2 is
the appropriate ts for calculation.
17. This specification indicates the guaranteed maximum frequency, in
synchronousmode,atwhichanindividualoutputorburiedregistercan
be cycle by a clock signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after asynchronous register clock input that the previous register output data is maintained on
the output pilL
4-195
I I)
C
a.
MHz
3
•
...I
19.6
40.0
40.0
Mil
us
30
22.2
22.2
Com'l
7
25
25
Mil
Units
us
35
Com'l
Max.
35
Mil
Notes:
7. This specification is a measure of the delay from input signal applied
to a dedicated input to combinatorial output on any output pin. This
delay assumes no expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, andlor
asynchronous preset) is ap'plied to a dedicated input only and no signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to
tPIA should be added to the comparable delay for a dedicated input.
If expanders are used, add the maximum expander delay tEXP to the
overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied
to an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
9. Thisspecificationisameasureofthedelayfromaninputsignalapplied
to a dedicated input to combinatorial output on any output pin. This
delay assumes expander terms are used to form the logic functions and
includes the worst-<:ase expander logic delay for one pass through the
expander logic.
10. Thisspecification isa measure of the delay from an input signal applied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the lAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register issynchronously clocked and all
feedback is within the same lAB. This parameter is tested periodically
by sampling production material.
Max.
.:~
_ CYPRESS
-==,
PRELIMINARY
External Asynchronous Switching Characteristics
Over the Operating Rangel4) (continued)
7C341-30
Parameters
tACOI
tAC02
tASI
tAS2
tAB
tAWH
tAWL
tACF
tAP
fMAXAI
fMAXA2
fMAXA3
fMAXA4
tAOH
CY7C341
SEMlCOIDUC'l'a<
Min.
Description
Dedicated Asynchronous Clock Input
to Output De!ay(6)
Com'!
DedicatedInputor FeedbackSet-upTinIeto
AsynchronousDock Inputl6)
Com'!
I/O Input Set-Up TinIe to
Asynchronous DockInputl6)
Com'!
Input Ho!d TinIe from Asynchronous
C!ockInputl6)
Com'!
Asynchronous Dock Input
HIGH TinIel6)
Com'!
Output Data Stable TinIefrom
Asynchronous C!ockInput(26)
ns
ns
10
30
ns
30
33
ns
10
8
10
14
12
16
Mi!
ns
20
16
Com'!
11
ns
14
Mil
20
14
Com'!
64
8
27
18
ns
22
Mil
26
22
Com'!
25
Com'!
27
Com'!
40
Com'!
33.3
Com'!
40
Com'!
15
MHz
22.2
33.3
33.3
Mil
MHz
25
28.5
28.5
Mil
MHz
18
33.3
33.3
Mil
40
23
23
Mil
ns
30
30
MHz
25
ns
15
15
Units
ns
55
8
Mil
Mil
MasinIumAsynchronousRegister
Toggle Frequency l/(tAWH + tAWL)[25)
6
Max.
45
55
Mil
Externa! Feedback MasinIum Frequeng in
AsynchronousMode 1/(tACOI + tASl)[ )
Data Path MasinIum Frequency in
AsynchronousModel24)
46
Mil
Mil
7C341-40
Min.
35
Mil
Externa! Asynchronous C!ockPeriod
(1/tMAX4)
MasinIum InternalAsynchronous
Frequencyl23)
30
Max.
35
Com'!
Asynchronous Dock to Local
Feedback Input(21)
7C341-35
Min.
Mil
Asynchronous Dock Input to Local
Feedback to Combinatoria! Output (19)
Asynchronous Dock Input
LOW Timel6,20)
Max.
15
Notes:
19. This specification is ameasure ofthe delay from an asynchronous registerclockinput to internal feedback of the register output signal to the
input of the lAB logic array and then to a combinatorial output. This
delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the
dedicated clock input pin and allfeedback is within a single lAB. This
parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggeredclockatthe
register. Fornegative-edge triggering. the tAWH and tAWLparameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL21. Thisspecificationis a measure of the delay associated with the internal
registerfeedbackpathforanasynchronousclocktolABlogicarrayinput. This delay plus the asynchronous register set-up time, tASl, is the
minimum internal period for aninternal asynchronously clocked state
machine configuration. This delay is for feedback within the same
lAB, and assumes there is no expander logic in the clock path and the
clock input signal is applied to a dedicated input pin. This parameter
is tested periodically by sampling production material.
22. This specification indicates the guaranteed maximum frequency at
whichan asynchronously clocked state machine configuration with ex-
23.
24.
25.
26.
4-196
ternal feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no
expander logic is employed in the clock signal path or data path.
This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine with internal-ouly
feedback can op-erate. This parameter is determined by the lesser of
(l/tACF + tASl) or (l/(tAWH +tAwr). If register output states must
also control external points, thisfrequencycanstill beobserved aslong
as this frequency is less than l/tACOl.
Thisfrequency is the maximum frequency at which the device may operatein the asynchronously clocked data path mode. This specification
is determined by the least of l/(tAWH + tAW!), l/(tASl + tAR) or
l/tACOl. It assumes data and clock input signalS are applied to dedicated input pins and no expander logic is used.
This specification indicates the guaranteed maximum frequency at
whichanindividual output or buried register canbe cycledinasynchronously clocked mode by a clock signal applied to an external dedicated
input pin.
This parameter indicates the minimum time that the previous register
outputdataismaintained on the output after anasynchronousregister
clock input applied to an external dedicated input pin.
::,rilPRESS
~
PRELIMINARY
CY7C341
SEMICCtIDUCIDR
Switching Waveforms
External Combinatorial
~
DEDICATED
I/OINPUT!
INPUT _ _ _ _ __
"",~"",,,
COMBINATORIAL
OUTPUT
I6
)
......._------
=1----------=4
_
HIGH-IMPEDANCE
I--3-STATE
I-- tEAI3.7]
_ _OUTPUT
_ _ _ _ ___
HIGH IMPEDANCE - - - - - - - - - - - - _ _ _VALID
COMBINATORIAL - - - - - - - - - - - tER ]
REGISTERED OUTPUT _ _ _ _ _ _-:-_ _~~
~STATE
C341-7
External Synchronous
DEDICATED INPUT!
I/O INPUTI7]
~._ _..,-__
tS1
SYNCHRONOUS _ _ _ _ __
CLOCK
of-+-_+--'
ASYNCHRONOUS _ _ _ _t_OH_ _
CLEAR/PRESET(7]
REGISTERED
OUTPUTS _ _ _ _ _--:--1""""'''
1---=----:...---
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACKl10]
!c02
-----*~
- - - - - - -
---C341-8
External Asynchronous
DEDICATED INPUT!
I/O INPUTI7]
~
.----""T"'"-....
tAS1
ASYNCHRONOUS
CLOCK INPUT _ _ _ _ _J
ASYNCHRONOUS
CLEAR/PRESETI7]
------+-+--1--'1
ASYNCHRONOUS REGISTERED
OUTPUTS _ _ _ _ _--:--1""""'''
------*~_
1---=----:...-- tAC02
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ __
C341-9
4-197
•
--
.~PRFSS
,
PRELIMINARY
Internal Switching Characteristics
Parameters
Over the Operating Rangel 1]
tIN
Description
Dedicated Input Pad and
Buffer Delay
tlO
I/O Input Pad and
Buffer Delay
tEXP
tLAD
tlAC
tOD
tzx
txz
tRSU
tRH
tLATCH
tRD
tCOMB
1m
teL
tiC
tICS
tFD
tpRE
tCLR
tpcw
tpCR
tPIA
CY7C341
SEMICOND\.JCIQ(
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable DelayLZ/j
Output Buffer Disable Delay
Register Set-Up Time Relative to
Clock Signal at Register
Register Hold Time Relative to
Clock Signal at Register
Flow-TbrougbLatch Delay
Register Delay
'fransparent Mode DelayL~Kj
Clock High Time
Clock Low Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
AsynchronousRegister Preset Time
AsynchronousRegister Clear Time
AsynchronousPresetand
Clear Pulse Width
AsynchronousPresetand
Clear Recovery Time
ProgrammableInterconnect
Array Delay Time
Noles:
27. Sample tested only for an outpnt change of 500 m V.
7C341-30
Min.
Max.
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'!
Mil
Com'l
Mil
7C341-35
Max.
Min.
7
7C341-40
Max.
Min.
9
9
9
9
20
6
14
11
ns
12
ns
25
20
14
16
16
13
13
6
6
13
13
13
13
12
5
11
11
8
8
ns
15
ns
15
ns
12
ns
4
4
2
2
4
4
12.5
12.5
12.5
12.5
16
ns
4
ns
2
ns
4
ns
15
ns
15
18
18
3
3
2
2
7
7
7
7
2
1
6
6
6
ns
7
10
4
10
ns
14
12
2
10
ns
18
10
10
10
4
ns
20
ns
4
ns
3
ns
8
ns
8
7
6
16
Units
ns
ns
7
8
7
7
8
ns
20
20
ns
24
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-198
-==--.
.~
PRELIMINARY
~=CYPRESS
CY7C341
- . F SEMICONDUCIDR
Switching Waveforms (continued)
Internal Combinatorial
)/(
tlN--
INPUT PIN
F
tlO
tplA
----00
•
I
1/0 PIN
I--EXPANDER
ARRAY DELAY
IEXP---
K
en
C
j4-- lLAC. lLAD ---LOGIC ARRAY
INPUT
...I
a.
~K
LOGIC ARRAY
OUTPUT
~
C341-10
Internal Asynchronous
IR
r
~I:= IAWH ' .
CLOCK PIN
liN
CLOCK INTO
-J. ~
IAWL },....----;.....IF
1V '4--- ,'-___
..J/
~
LOGIC ARRAY
tiC
CLOCK FROM
;t
*%
_
~
LOGIC ARRAY
IRSU
,'-_____
, " -_ _ _ _.../
IRH
DATAARRAY
FROM
LOGIC
"1--,..------------
"'__ _ _ __
-+-
~
--+-
X=
tRD.4..ATCH
IFD
telR.ipRE
IFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY - - - - - - - - - - - - - __________________
IP_IA=*~-----------
REGISTER OUTPUT
TO ANOTHER LAB
C341-11
External Asynchronous
SYSTEM CLOCK PIN
SYSTEM
CLOC~
AT REGISTER
DATAARRAY
FROM
LOGIC
)= ~ ----r-
=£
IcH
tel
tlH - : E I I C S
tRSU
=*
,
...._ _ _ _/
IRH _ _
,"-----,"----
~------------------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
C341-12
4-199
1i17~~R
PRELIMINARY
CY7C341
Switching Wavefonns (continued)
Internal Synchronous
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C341-13
Ordering Infonnation
Speed
(ns)
30
35
40
Package
'JYpe
Operating
Range
CY7C341- 30GC
G84
Commercial
CY7C341-30HC
H84
Ordering Code
CY7C341-3OJC
J83
CY7C341-30RC
R84
CY7C341-35GC
G84
CY7C341-35HC
H84
CY7C341-35JC
J83
CY7C341-35RC
R84
CY7C341-35HMB
H84
CY7C341-35RMB
R84
CY7C341-40HMB
H84
CY7C341-40RMB
R84
Commercial
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
IIX
1,2,3
Ioz
1,2,3
ICCl
1,2,3
Parameters
Subgroups
tpDl
tPD2
tPD3
tPD4
tCOl
ts
tH
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
tACOl
tAC02
tAS
tAR
Document #: 38-00137-C
4-200
CY7C342
CYPRESS
SEMICONDUCTOR
128-Macrocell MAX® EPLDs
MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions.
The 128 macrocells in the CY7C342 are
divided into 8 Logic Array Blocks
(LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be
used and shared by the macrocells within
each LAB.
Each LAB is interconnected with a programmable interconnect array, allowing
all signals to be routed throughout the
chip.
Features
• 128 macrocells in 8 LABs
• 8 dedicated inputs, 52 bidirectional
I/O pins
• Programmable interconnect array
• Available in 68-pin HLeC, PLCC,
PGA, and Flatpack
Functional Description
The CY7C342 is an Erasable Programmable Logic Device (EPLD) in which
CMOS EPROM cells are used to configure logic functions within the device. The
The speed and density of the CY7C342
allows it to be used in a wide range of
applications, from replacement of large
amounts of 74oo-series TIL logic, to
complex controllers and multifunction
chips. With greater than 25 times the
functionality of 20-pin PLDs, the
CY7C342 allows the replacement of over
50 TIL devices. By replacing large
amounts of logic, the CY7C342 reduces
board space, part count, and increases
system reliability.
a.
1 (B6)
INPUT/ClK
INPUT
(A7)
2 (AS)
INPUT
INPUT
(AS)
68
32 (l4)
INPUT
INPUT
(l.6)
36
34(l5)
INPUT
INPUT
(KIl)
35
.......,
4 (AS)
5 (B4)
6 (A4)
7(83)
8(Aa)
9(A2)
10(B2)
11 (Bl)
-
..:
I
~
SYSTEM ClOCK
..
-
MACRO
MACRO
MACRO
MACRO
:ElI.18
:ElI.19
:ElI.2O
:ElI
MACROCEll 22·32
18 (F2)
19 (Fl)
21 (Gl)
22 (H2)
23 (HI)
-
!
---v
~
.U~
tL-
.........-
P
I
A
LABO
29(K3)
30 (l3)
31 (K4)
~
--
MAGH'-"'''LL 04
-
A
M"""""~LL""
<7.
'ELI. 99
.97
I---
-
~
. LABF
.CAO ::ELI. as
-
I"
lA--
~
~
i~~
1..1.
1"'--
r---v~
.
..
IV
C>16,33, 50, 67 (E2, KS, Gl0, B7) C>3.20.37. 54 (BS, G2, K7, El0)
Vee
GNO
MAX and MAX +PLUS are registered trademarks of Altera Corporation.
4-201
(011) 57
(010) 56
(Ell) 55
(Fll) 53
(FlO) 52
(GIl) 51
(Hll) 49
(HID) 48
(J11) 47
(Jl0) 46
MACROCEll86·00
"f-..JI.
."""".,,,
(88) 66
(A9)64
(B9) 63
(AID) 62
' LABG
aTol
.64
..!J..
MAGHUG"LL 50
I---
~
Y
-
I---
MACROCElll02·112
~
---,I
24 (J2)
25 (Jl)
26 (Kl)
27(K2)
28 (l2)
18
(BID) 61
(611160
(Cl1) 59
(C10) 58
~E1i
IA
LABC
MACROCEl. 33
MAGR()(;E .34
MACROCEll 38-48
MAC :ROC
MACROCEll 12"'28
IV--
r---v'
_"H'-"'''LL ..
,j LABH
:110 CEl.12O
v- I
·U~
LABB
--
68
---.
."
."
MACROCEll9·16
12(C2)
13 (Cl)
14(02)
15(01)
17 (El)
.
MAGHUG"LL3
MAGH()(;E .6
..:
IIJ
C
...J
Logic Block Diagram
LAB A
MACRe :ELI
II
(Kll) 45
(KID) 44
{lID)43
(l9) 42
{K9)41
(LS) 40
{K8)39
(l7) 36
I MACROCEll73-80
( ) • PERTAIN TO 68-PIN PM PACKAGE
0342-1
ir7,~NDUCfOR
CY7C342
Selection Guide
7C342-25
7C342-30
7C342-35
7C342-40
25
250
30
250
320
320
225
275
275
35
250
320
320
225
275
275
40
Maximum Access Time (ns)
Commercial
Military
Industrial
Commercial
Military
Industrial
Maximum 3.)erating
Current (rnA
Maximum Standby
Current (rnA)
320
225
275
320
275
Pin Configurations
PLCC!FIatpack
1bpView
PGA
Bottom View
110
110
I/O
110
I/O
110
H
G
VO
110
110
VO
Vee
110
110
110
110
110
110
110
110
110
110
110
110
Vee
GND
I/O
110
I/O
110
I/O
E
110
GND
Vee
110
D
I/O
I/O
110
110
C
I/O
I/O
I/O
110
110
110
110
110
I/O
K
7
6
5
60J
110
110
GND
I/O
110
110
Vee
110
GND
INPUT
4 3 2 86667666564636261
VO
VO
VO
VO
INPUT INPUT INPUT
o
VO
56J VO
56J VO
57J VO
56J VO
VO
Vee
110
110
110
GND
110
110
I/O
110
110
110
7C342
110
110
110
110
110
110
C342-2
7C342
B
110
I/O
110
110
Vee
INPUTI
GND
CLK
A
•
I/O
110
110
I/O
INPUT INPUT INPUT
110
10
11
C342-3
4-202
~~
CYPRESS
~.~I
CY7C342
SEMICONDUClDR
Maximum Ratings
DC Input Voltagel l ] .................... - 2.0V to + 7.0V
DC Program Voltage. . . . . . . . . . . . . . . . . .. - 2.0V to + 13.5V
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ........................... O°Cto +70°C
Maximum Junction Temperature
(under bias) .................................... 150 ° C
Supply Voltage to Ground Potential. . . . . . .. - 2.0V to + 7.0V
MaximumPowerDissipation .................... 2500mW
DC Vee or GND Current. . . . . . . . . . . . . . . . . . . . . . .. 500 rnA
DC Output Current per Pin ........... - 25 rnA to +25 rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Vee
5V±5%
O°Cto +70°C
Industrial
Military
- 40°C to +85°C
5V± 10%
- 55°Cto +12S0C(Case)
SV± 10%
VOH
VOL
VIH
VII.
IIX
Ioz
los
Icc!
Overthe Operating Rangel2]
Description
Thst Conditions
Output HIGH Voltage
V cc = Min., IOH = -4.0 rnA
Output LOW Voltage
V cc - Min., IOL - 8.0 rnA
Input HIGH Voltage
Input LOW Voltage
Input Current
GND ~ VIN ~ Vee
Output LeakageCurrent
Va = Vccor GND
Vcc - Max., VOVT - O.5Vl', qj
Output Short Circuit Current
PowerSupp!yCurrent (Standby) VI = GND (No Load)
ICC2
Power Supply Currentl~ j
tR
tF
Recommended Input Rise Time
Recommended Input Fall Time
Parameter
C
Min.
2.4
2.2
- 0.3
-10
- 40
- 30
Com'!
MillInd
Com'!
Mil!Ind
VI = Vee or GND (No Load)
f = 1.0 MHz[4]
Max.
Units
V
V
V
V
0.45
Vee +0.3
0.8
+10
+40
-90
225
275
250
320
100
100
!LA
!LA
rnA
rnA
rnA
ns
ns
Capacitance [6]
Parameters
Thst Conditions
CIN
Description
InputCapacitance
VIN
CoUT
Output Capacitance
VOUT - 2Y, f - 1.0 MHz
= 2Y, f = 1.0 MHz
Notes:
1. Minimum DC iuput is - O.3V. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.
2.. "JYpicalvalues are forTA = 25°C and Vee = 5V.
3. Not more than one output should be tested at a time. Duration of the
short circnit should not be more than one second. V OUT = O.5V has
been chosen to avoid test problems caused by tester ground
degradation.
4.
5.
6.
Units
Max.
10
pF
pF
10
Guaranteed but not 100% tested.
This parameter is measured with device programmed as a 16-bit
counter iu each lAB.
Part (a) iu AC Test Load and Waveforms is used for all parameters
except tER and txz, which is used for part (b) iu AC Thst Load and
Waveforms. All external timing parameters are measured referenced
to external pins of the device.
AC Test Loads and Waveforms[4]
R1464Q
R1464Q
OUTP~~31
OUTPUT
5V31
50pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
R2
I _
2500
-
-
5pF
I
10%
90%
'.ov~
R2
INCLUDING _
JIGAND SCOPE
(a)
ALL INPUT PULSES
2500
_
C342-4
(b)
THEVENIN EQUIVALENT (commercial/military)
163Q
OUTPUT 0.0_ _--"1.\1\._ _--00 1.75V
4-203
•
U)
Electrical Characteristics
GND
.s6ns ....
l'e.:
10%
....
.s6ns
C342-5
...J
Il.
.7,~~~R
CY7C342
Logic Array Blocks
required for a programmable gate array to achieve design timing
objectives.
There are Slogic array blocks in the CY7C342. Each LAB consists
ofamacrocell array containing 16macrocells, anexpanderproduct
tennarray containing 32 expanders, and an I/O block. The LAB is
fed by the programmable interconnect array and the dedicated
input bus. All macrocell feedbacks go to the macrocell array, the
expander array, and the programmableinterconnectarray.Expandersfeed themselves and the mal;focell array. All I/O feedbacks go
to the programmable interconnect array so that they may be accessedbymacrocells in other LABs aswell as the macrocells in the
LAB in which they are situated.
Externally, the CY7C342 provides eight dedicated inputs, one of
which may be used as a system clock. There are 52 I/O pins that
may be individually configured for input, output, or bidirectional
dataflow.
Timing Delays
Tuningdelayswithin the CY7C342maybeeasilydetenninedusing
MAX +PWS® software or by the model shown in Figure 1. The
CY7C342has fixed internal delays, allowing the user to detennine
theworst case timing delays for any design. Forcomplete timing infonnation the MAX +PLUS software provides a timing simulator.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under "Maximum Ratings" may cause pennanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings
conditions for extended periods of time may affect device reliability. The CY7C342 contains circuitry to protect device pins
from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher
than the maximum rated voltages.
Programmable Interconnect Array
The ProgrammablelnterconnectArray (PIA) solves interconnect
limitations by routing only the signals needed by each logic array
block. The inputs to the PIA are the outputs of every macrocell
within the device and the I/O pin feedback of every pin on the device.
Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This
eliminates undesired skews among logic signals that may cause
glitches in internal or external logic. The fixed delay, regardless of
programmable interconnect arrayconfjguration, simplifies design
by assuring that internal signal skews or races are avoided. The
result is ease of design implementation, often in a signal pass, without the multiple internal logic placement and routing iterations
Forproperoperation,inputandoutputpinsmustbeconstrainedto
the range GND 5 (YIN or VOUT) 5 V ce. Unused inputs must always be tied to an appropriate logic level (either Vce or GND).
Each set of V ce and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2
"F must be connected between V ce and GND. Forthe most effective decoupling, each Vce pin should be separately decoupled to
GND directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types have.
~DER~
DELAY
~
--!I
IN
~
tEXP
LOGIC ARRAY ,~
CONTROL DELAY teLA
f-~
INPUT
DELAY
tiN
--!I
1
REGISTER
I
tLAC
~H
tpRE
I
LOGIC ARRAY
DELAY
I
ItAo
OUTPUT
DELAY
OUTPUT
tRSU
tRO
tCOMB
tRH
ItATCH
1-i1
too
txz
tzx
-~
SYSTEM CLOCK DELAY Itcs
r
PIA
DELAY
tPiA
'---!I
I
CLOCK
DELAY
~
I
tiC
I
I
I
I
I/O DELAY
FEEDBACK
DELAY
tFo
L
r
L
tlO
0342-6
Figure 2. CY7C342 Internal Timing Model
4-204
CY7C342
Design Security
TIming Considerations
The CY7C342 contains a programmable design security feature
that controls the access to the data programmed into the device.
If this programmable feature is used, a proprietaty design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that
controls this function, along with all other program data, may be
reset simply by erasing the entire device.
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander
delay too to the overall delay. Similarly, there is an additional
tpIA delay for an input from an I/O pin when compared to a signal from straight input pin.
The CY7C342 is fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internallogic elements thus ensuring 100% programming yield
The erasable nature of these devices allows test programs to be
used and erased during early stages of the production flow. The
devices also contain on-board logic test circuit!}' to allow verification of function and AC specification once encapsulated in nonwindowed packages.
'JYpical Icc vs. fMAX
~~------------------------~
Ii
~
300 -
Vcc=S.OV
Room Temp.
<"
S
~
~
200 -
The parameter toR indicates the system compatibility of this device when driving other synchronous logic with positive input
hold times, which is controlled by the same synchronous clock. If
toR is greater than the minimum required input hold time of the
subsequent synchronous logic, then the devices are guaranteed to
function properly with a common synchronous clock under worstcase environmental and supply voltage conditions.
100 -
o~~~--L---~--~--~--~
100Hz 1 kHz
10kHz
100kHz 1 MHz 10MHz SDMHz
MAXIMUM FREQUENCY
!zw
a:
a:
::l
o
I
The parameter tAOR indicates the system compatibility of this
device when driving subsequent registered logic with a positive
hold time and using the same asynchronous clock as the
CY7C342.
Output Drive Current
~
l
When calculating synchronous frequencies, use tSI if all inputs
are on dedicated input pins. The parameter tS2 should be used if
data is applied at an I/O pin. If tS2 is greater than teol, 1/tS2 becomes the limiting frequency in the data path mode unless
lI(twH + twL) is less than l/tsz.
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tsi' Determine which of
l/(twH + twu, l/teoh or lI(tEXP + tsl) is the lowest frequency.
The lowest of these frequencies is the maximum data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use tASl if
all inputs are on the dedicated input pins. If any data is applied to
an I/O pin, tAS2 must be used as the required set-up time. If (tAS2
+ tAU) is greater than tACOh l/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless l/(tAWH + tAWU is
less than 1I(tAs2 + tAH).
When expander logic is used in the data path, add the appropriate maximum expander delay, lEXP to tASl' Determine which of
l/(tAWH + tAWL), l/tACOh or l/(tEXP + tASI) is the lowest frequency. The lowest of these frequencies is the maximum data
path frequency for the asynchronous configuration.
In general, if tAOR is greater than the minimum required input
hold time of the subsequent logic (synchronous or asynchronous)
then the devices are guaranteed to function properly under
worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device,
but not for the driven device. This is due to the expander logic in
the second device's clock signal path adding an additional delay
(tEXP) causing the output data from the preceding device to
change prior to the arrival of the clock signal at the following device's register.
100
IOL
80
60
40
20
.s;
0
0 .46
1
2
3
Vo OUTPUT VOLTAGE
4
5
M
4-205
•
I I)
C
..J
a.
£:,~
CY7C342
~=CYPRESS
~F SEMICONDUCTOR
External Synchronous Switching Characteristics[4] Over Operating Range
Parameters
Description
tpDl
Dedicated Inp.ut to Combinatorial
Output Delay(7]
tPD2
I/O Input to Combinatorial
Output Delay[8]
tpD3
Dedicated Input to Combinatorial
Output Delay with
Expander Delay[9]
tPD4
tEA
tER
tcO!
7C342-40
7C342-30
7C342-25
7C342-35
Min. Max. Min. Max. Min. Max. Min. Max. Units
30
35
ns
Com'l/lnd
25
Mil
30
35
40
Com'l!Ind
40
45
ns
55
Mil
45
55
65
ns
37
44
55
Com'VInd
Mil
I/O Input to Combinatorial
Output Delay with
Expander Delay[4, 10]
Com'l!Ind
Input to Output Enable
Delayl4,7]
Com'l!Ind
Input to Output Disable
Delayl4,7]
Com'l!Ind
Synchronous Clock Input to
Output Delay
Com'VInd
tS2
I/O Input Set-Up Time to
Synchronous Clock Input[7]
Com'l!Ind
tH
Input Hold Tinle from
Synchronous Clocklnput[7]
Com'VInd
Synchronous Clock Input
HIGH Time
Com'l!Ind
Synchronous Clock Input
LOWTinle
Com'VInd
AsynchronousClearWidth[4,7]
Com'l!Ind
tWL
tRW
14
Com'VInd
Mil
Dedicated Input or Feedback
Set-UpTime to
SynchronousClocklnput[7,12]
tWH
25
Mil
Com'VInd
tS1
25
Mil
Synchronous Clock to Local
Feedback to Combinatorial
OutputI4,11]
tc02
52
Mil
30
Mil
15
Mil
30
Mil
0
Mil
8
tRO
tpw
Com'l!Ind
Asynchronous Clear to Registered
Output Delayl7]
Com'VInd
AsynchronousPreset Width[4, 7]
Com'l!Ind
8
tpo
AsynchronousPreset Recovery
Timel4,7]
25
25
Mil
75
30
30
30
30
16
16
35
35
35
35
35
20
35
42
25
25
39
39
0
0
45
45
0
0
12.5
12.5
12.5
12.5
35
35
35
35
25
Mil
AsynchronousPreset to Registered Com'VInd
Output Delayl7]
25
Mil
4-206
ns
40
ns
23
ns
48
ns
28
ns
52
ns
0
ns
15
ns
15
ns
40
ns
40
35
35
35
35
30
30
ns
40
35
35
30
30
30
30
30
30
25
ns
90
42
20
25
65
20
20
Mil
Com'VInd
75
59
10
10
30
30
30
30
Mil
tpR
59
10
Mil
Asynchronous Clear Recovery
Timel4,7]
55
10
Mil
Mil
tRR
44
ns
40
ns
40
ns
40
35
35
ns
40
--=--.
.:~
CY7C342
Ellii'1= CYPRESS
~F
SEMlCONDUCfOR
External Synchronous Switching Characteristics[4] Over Operating Range
7C342-25
Parameters
Description
Min.
Synchronous Clock to Local
FeedbackInput[4,13]
Com'VInd
External Synchronous Clock
Period (1!(fMAX3))[4]
Com'VInd
fMAXI
External Feedback Maximum
Frequency(l/(tcOl + t81))[4,14]
Com'VInd
fMAX2
Internal LocaI Feedback
Maximum Frequency, lesser of
(1/(t81 + tcF» or (1!tCOl)[4,15]
Com'VInd
Data Path Maximum Frequency,
lesserof(l/(tWL + tWH))
(l/(tsl + tH» or (1/tCOl)f4, 16]
Com'VInd
Maximum Register Toggle
Frequency(l/(tWL + tWH»[4, 17]
Com'VInd
Output Data Stable Time from
Synchronous Clock Input[4, 18]
Com'l/lnd
tcF
tp
fMAX3
fMAX4
tOR
Max.
7C342-30
Min.
3
Mil
16
Mil
34.5
Mil
55.5
Mil
62.5
Mil
62.5
Mil
3
Mil
Max.
7C342-35
Min.
Max.
3
6
3
6
20
25
20
25
27.7
22.2
27.7
22.2
43.4
32.2
43.4
32.2
50
40
50
40
50
40
50
40
3
3
3
3
7C342-40
Min.
Max.
Units
ns
9
ns
30
MHz
19.6
MHz
This specification is a measure of the delay from input signal applied
to a dedicated input (68·pin PLCC input pin I, 2, 32, 34, 35, 66, or 68)
to combinatorial output on any output pin. This delay assumes no ex·
pander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, and/or
asynchronous preset) is applied to a dedicated input only andno signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to
tPIA should be added to the comparable delay for a dedicated input. If
expanders are used, add the maximum expander delay tEXP to the
overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied
to an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
9. This specification is ameasure of the delay from aninputsignalapplied
to a dedicated input (68·pin PLCC input pin I, 2, 32, 34, 35, 36, 66, or
68) to combinatorial output on any output pin. This delay assumes ex·
pander terms are used to form the logic function and includes the
worst·caseexpander logic delay for one pass through the expander log·
ic.
10. Thisspecificationisameasureofthedelayfromaninputsignalapplied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst·case
expander logic delay for one pass through the expander logic. This pa·
rameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the LAB logic array and then to a combinatorial output. This delay as·
sumes no expanders are used, register is synchronously clocked andall
feedback is within the same LAB. This parameteris tested periodically
by sampling production material.
a..
27
MHz
33.3
MHz
33.3
ns
3
12. If data is applied to an I/O input for capture by a macrocell register, the
I/Opin input set·up time minimums should be observed. Theseparam·
eters are 182 for synchronous operation and tAS2 for asynchronous op·
eration.
13. This specification is a measure ofthe delay associated with tbe internal
register feedback path. This is the delay from synchronous clock to
LAB logic array input. This delay plus the register set·up time, tst. is
the minimum internal period for an internal synchronous state rna·
chine configuration. This delay is for feedback within the same LAB.
This parameter is tested periodicallybysamplingproductionmaterial.
14. This specification indicates the gnaranteed maximum frequency, in
synchronous mode, at which a state machine configuration with exter·
nal feedback can operate. It is assumed that all data inputs and feed·
back signals are applied to dedicated inputs. All feedback is assumed
to he local originatmg within the same LAB.
15. This specification indicates the gnaranteed maximum frequency at
whichastate machine with internal·onlyfeedbackcan operate. Ifregis.
ter output states must also control external points, this frequency can
still be ohserved as long as this frequency is less than l/tem.
16. This frequency indicates the maximum frequency at which the device
may operate in data path mode (dedicated input pin to output pin).
This assumes data input signalsare applied to dedicated input pins and
no expander logic is used. If any of the data inputs are I/O pins, 182 is
the appropriate ts for calculation.
17. This specification indicates the gnaranteed maximum frequency, in
synchronous mode, atwhichanindividualoutput orburiedregistercan
be cycled by a clock signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after a synchronous regis.
ter clock input that the previous register output data is maintained on
the output pin.
4-207
II)
C
...J
Notes:
7.
•
.s;:
~~PRFS'3
~F SEMICONDUCTOR
CY7C342
External Asynchronous Switching Characteristics[4] Over Operating Range
7C342-2S
Parameters
tACOl
tAC02
tASI
tAS2
tAH
tAWH
tAWL
tACF
tAP
fMAXAI
fMAXAZ
fMAXA3
Description
Asynchronous Clock Input to
Output Delayl7]
Min.
Com'l/lnd
Mil
Com'VJnd
Com'VJnd
I/O Input Set-Up Time to
Asynchronous Clock Input[7]
Com'VJnd
Mil
Com'l/Ind
Mil
Com'l/Ind
Mil
Com'VJnd
Mil
Com'VJnd
Mil
Com'VJnd
Mil
Com'VJnd
Input Hold Time from
Asynchronous ClockInput[7J
Asynchronous Clock Input
High Timef7J
Asynchronous Clock Input
Low Timef7, 20]
Asynchronous Clock to Local
FeedbackInput[4,21]
ExternalAsynchronousClock
Period (l!(fMAXA4»[4]
External FeedbackMaximum
Fre~uenz in Asynchronous
Mo e(l! tACOI + tAS1»[4, 22]
MaximumIntemalAsynchronous
Frequencyl4, 23]
Data Path MaximumFre~ency
in Asynchronous Model4, J
fMAXA4
Maximum Asynchronous
Register Thggle Fr~ency
l!(tAWH + tAWL)[4, ]
tAOH
Output Data Stable Time from
AsynchronousClockInpud4,26J
7C342-30
Min.
40
Asynchronous Clock Input to
Local Feedback to Combinatorial
Mil
Outputl:19]
Dedicated Input or Feedback
Set-Up Time to Asynchronous
Clock Inpud7J
Max.
25
Max.
30
30
46
7C342-3S
Min.
46
5
Mil
20
6
11
33.3
Mil
50
Com'l/Ind
Mil
Com'VJnd
Mil
Com'l/Ind
40
50
Mil
15
Com'l/Ind
Mil
Notes:
19. This specification is a measure ofthe delay from an asynchronous register clock input to internal feedback of the register output signal to the
input of the LAB logic array and then to a combinatorial output. This
delayassumesnoexpandersareusedinthelogicofcombinatorialoutput or the asynchronous clock input. The clock signal is applied to the
dedicated clock input pin and all feedbacki. within a single LAB. This
parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge triggered clock at the
register. For negative edge triggering, the tAWH and tAWLparameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL
21. This specification is ameasure of the delay associated with the internal
registerfeedbackpathforan asynchronous clock to LAB logic arrayinput. This delay plus the asynchronous register set-up time, tASh is the
minimum internal period for an internal asynchronously clocked state
machine coufiguration. This delay is for feedback within the same
LAB,assumesnoexpanderlogicintheclockpath,andassumesthatthe
clock input signal is applied to a dedicated input pin. This parameter
is tested periodically by sampling production material.
22. This specification indicates the gnaranteed maximum frequency at
which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clockin-
Units
ns
ns
64
55
8
8
10
21
21
8
8
14
14
28
28
10
35
10
10
ns
ns
ns
ns
16
16
14
14
18
18
Max.
45
6
15
20
7C342 40
Min.
6
11
11
9
Max.
35
35
55
18
ns
16
22
22
ns
26
25
25
27.7
30
30
23.2
34
27.7
23.2
18.1
40
40
33.3
33.3
40
33.3
33.3
28.5
28.5
33.3
40
33.3
29.4
15
15
15
15
15
ns
MHz
MHz
27.7
MHz
22.2
MHz
ns
puts, and feedback signals are applied to dedicated inputs and that no
expander logic is employed in the clock signal path or data path.
23. This specification indicates the gnaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. This parameter is determined by the lesser of
(l/(tACF + tAS» or (l/(tAWH + tAWL». If register output states must
also control external pomts, this frequency can still be observed as long
as this frequency is less than l/tACOI.
This specification assumes no expander logicis utilized, all data inputs
and clock inputs are applied to dedicated inputs, and all state feedback
is within a single LAB. This parameter is tested periodically by sampIing production material.
24. This frequency is the maximum frequency at which the device mayoperate in the asynchronously clocked data path mode. This specification
is determined by the lease of l/(tAWH + tAWL), l/(tASI + tAH) or
l/tACOl. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
25. This specification indicates the gnaranteed maximum frequency at
whichan individual output or buried register can be cycledinasynchronously clocked mode by a clock signal applied to an external dedicated
input pin.
26. This parameter indicates the minimum time that the previous register
output data is maintained on the output after an asynchronous register
clock input applied to an external dedicated input pin.
4-208
·~
~JiiCYPRESS
CY7C342
~F SEMlCaIDUCTOR
'J.Ypical Internal Switching Characteristics Over Operating Range
7C342-2S
Parameters
Description
Dedicated Input Pad and
tIN
Buffer Delay
tIO
I/O Input Pad and
Buffer Delay
tEXP
Expander Array Delay
tLAD
Logic Array Data Delay
tlAC
Logic Array Control Delay
taD
Output Buffer and Pad Delay
tzx
Output Buffer Enable Delayl"' I]
txz
Output Buffer Disable Delay
tRSU
Register Set-Up Time Relative
to Clock Signal at Register
tRH
Register Hold Time Relative
to Oock Signal at Register
tlATCH
Flow Through Latch Delay
tRO
Register Delay
tCOMB
'fransparentMode Delayl",']
tCH
Clock HIGH Time
tCL
Clock LOW TIme
tIC
Asynchronous Clock Logic Delay
tICS
Synchronous OockDelay
tFD
Feedback Delay
tpRE
AsynchronousRegister
Preset Time
tCLR
AsynchronousRegister
Clear Time
tpcw
AsynchronousPreset and
Clear Pulse Width
tpCR
AsynchronousPresetand
Clear Recovery Time
tPIA
Programmablelnterconnect
Array Delay Time
Notes:
27. Sample tested only for an output change of 500 m V.
Min.
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'VInd
Mil
Com'l/lnd
Mil
Com'VInd
Mil
Com'VInd
Mil
Max.
5
7C342-30
Min.
6
12
12
10
5
Max.
7
7
6
6
14
14
14
14
12
12
5
5
10
11
10
11
11
11
6
3
3
14
16
16
2
2
2
1
1
5
6
6
6
6
5
14
18
18
3
3
2
2
7
7
7
7
1
6
6
6
6
5
5
4
4
2
2
4
4
12.5
12.5
12.5
12.5
10
10
10
10
8
16
16
13
13
6
6
13
13
13
13
4
4
2
2
4
4
1
8
20
10
10
10
10
8
8
8
8
6
7C342-3S
Min. Max.
9
9
9
9
20
7
7
7
7
16
16
20
20
7C342-40
Min. Max. Units
ns
11
ns
12
ns
25
ns
18
ns
14
ns
7
ns
15
ns
15
ns
12
ns
12
ns
4
ns
2
ns
4
ns
15
ns
15
ns
20
ns
4
ns
3
ns
8
ns
8
ns
8
ns
8
ns
24
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-209
•
II)
C
..J
Q.
fL:?~
CY7C342
~_~ ~NDUCfOR
Switching Waveforms
External Combinatorial
DEDICATED
I/OINPUT/
INPUT _ _ _ _ __
~
""m"",~
COMBINATORIAL
OUTPUT
)..--_ _ _ _ __
=1-----------
I---
COMBINATORIAL OR - - - - - - - - - - - tER!7I
REGISTERED OUTPUT _ _ _ _ _ _-:-_ _ _
~
HIG~~~~~~~~
E~rnalSynchronous
DEDICATED INPUTS OR
REGISTEREDFEEDBACK!7I
_
1---. tEA[7]~
_____________
=i
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
--------
0342-7
_ _.....__
lsI
SYNCHRONOUS
CLOCK - - - - - - '
ASYNCHRONOUS
~H
CLEAR/PRESEl'17] _ _ _ _ _.....;-1_-+__'
REGISTERED
OUTPUTS ------"!""""-f-~
~~~----~02----------~~
COMBINATORIAL OUTPUT FROM
REGISTEREDFEEDBACK[II]
- - - - - - -
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
-----0342-8
=i
___..,....__
tASl
ASYNCHRONOUS
CLOCK INPUT _ _ _ _ __
ASYNCHRONOUS
CLEAR/PRESET
tAOH
-----.....;-If--+--'
ASYNCHRONOUS REGISTERED
OUTPUTS _ _ _ _ _---:~~v
~~---'--- tAC02 -----~~~
COMBINATORIAL OUTPUT FROM
ASYNCHRONOUS REGISTERED
FEEDBACK--------------------
--------0342--9
4-210
~
.s::-
.~
CY7C342
~i=cyPRESS
~,
SEMICaIDUCTOR
*
Switching Waveforms (continued)
Internal Combinatorial
INPUT PIN
IIN-
F
110
tplA-----
I--
IEXP--
~
EXPANDER
ARRAY DELAY
II)
I----
a.
LOGIC ARRAY
OUTPUT
~
i!1:= It
IAWH
liN
CLOCK INTO
LOGIC ARRAY
11/
14--
CLOCK FROM
LOGIC ARRAY
DATAARRAY
FROM _ _ _ _ __
LOGIC
tlC;t
\..
}~IF
/-
*% t
~-----------------
,,'--_ _ _-J.
\..
/
' ...._ _ _ _.J.
~ tRSU
IRH
tRD.tLATCH
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
IAWL
C342-10
-Jt
Internal Asynchronous
IR
C
.....
lLAc. lLAD - -
}K
LOGIC ARRAY
INPUT
CLOCK PIN
•
I
I/O PIN
-+-
tFD
-
,,-----
IClR.lpRE
-+-
IFD
k=
- - - - - - - - - - - - - - - - - - I P - I A J <_ _ _ _ _ _ _ _ _ _ _ __
REGISTER OUTPUT
TO ANOTHER LAB
C342-11
Internal Synchronous
1:=
-.Jr
~
IcH
SYSTEM CLOCK PIN _ _
SYSTEM CLOCK
AT REGISTER _ _
tCl
4N:tIICS
~
____
tRSU
DATA FROM
LOGIC ARRAY
:::::1
r- -1
/
~~
~
~
tRH
=*
~
~
_ _ _ _- J/
,,'------
,,'----
----------------------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~=
C342-12
4-211
&;~PRFSS
~.i.
CY7C342
SEMICONDucroR
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM
LOGIC ARRAY _ _ _ _ _")
DATA FROM
LOGIC ARRAY
OUTPUT PIN
0342-13
Ordering Information
Speed
(ns)
25
30
35
40
Ordering Code
Package
'JYpe
CY7C342-25GC1GI
G68
CY7C342-25RCIHI
R81
CY7C342-25JC/ll
J81
CY7C342-25RC/RI
R68
CY7C342-30GCIGI
G68
CY7C342-30RClHI
R81
CY7C342-30JC/JI
J81
CY7C342-30RC/RI
CY7C342-30HMB
R68
R8I
CY7C342-30RMB
R68
CY7C342-3OTMB
T68
CY7C342-35GC/GI
G68
CY7C342-35RClHI
R81
CY7C342-35JC/JI
J81
CY7C342-35RC!RI
R68
CY7C342-35RMB
R81
CY7C342-35RMB
R68
CY7C342-35TMB
T68
CY7C342-40HMB
R81
CY7C342-40RMB
R68
CY7C342-40TMB
T68
Operating
Range
CommerciaVlndustrial
CommerciaVIndustrial
Military
Commercialllndustrial
Military
Military
4-212
=;~~
CY7C342
~=CYPRESS
~p SEMlCONDUCIDR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VIL
IIX
Ioz
ICCI
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
•
Switching Characteristics
Parameters
Subgroups
tPDl
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9, 10,11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
tpD2
tPD3
tcO!
tSI
tS2
tH
tWH
tWL
tRO
tpo
tACO!
tAC02
tASI
tAH
tAWH
tAWL
Document #: 38-00119-B
4-213
CY7C343
CYPRESS
SEMICONDUCTOR
64-Macrocell MAX®
EPLD
Features
Functional Description
• 64 MAX macrocells in 4 LABs
• 8 dedicated inpnts, 24 bidirectional
I/O pins
• Programmable interconnect array
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343 is a high-performance,
high-density erasable programmable logic
device, available in 44-pin PLCC and
HLCCpackages.
The CY7C343 contains 64 highly flexible
macrocells and 128 expander product
terms. These resources are divided into
four Logic Array Blocks (LABs) connected through the Programmable Inter-
connect Array (PIA). There are 8 input
pins, one of which doubles as a clock pin if
needed. The CY7C343 also has 28 I/O
pins, each connected to a macrocell (6 for
LABs A and C, and 8 for LABs B and D).
The remaining 36 macrocells are used for
embedded logic.
The CY7C343 is excellent for a wide range
of both synchronous and asynchronous
applications.
Logic Block Diagram
INPlJT35
91NPlJT
11 INPlJT
INPlJTlCLK 34
121NPlJT
INPlJT33
131NPlJT
INPlJT31
44
42
VOPINS
41
40
39
38
37
16
110 PINS
me
15
17
18
20
19 _ _r---,
110 PINS
30
29
28
27
_,,,._-1
.....
1/0 PINS
28
24
22 ,,-..----,
23
(3, 14,25, 36)
(10, 21. 32, 43)
C>C>-
Vee
GND
C343-1
Selection Guide
7C343-2S
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
Maximum Standby
Current(mA)
Commercial
25
135
Military
Industrial
225
Commercial
125
Military
Industrial
200
MAX and MAX +PLUS are registered trademarks ofAltera Corporation.
4-214
7C343-30
30
135
7C343-3S
35
135
7C343-40
40
225
225
225
225
225
125
125
200
200
200
200
200
CY7C343
HLCC
'lbp View
Pin Configuration
ggg>gggg~ggg
VO
I/O
I/O
VO
VO
Vee
INPUT
GND
0
INPUT
INPUT
INPUT
Vee
VO
VO
VO
INPUT
INPUT/CLK
INPUT
GND
7C343
INPUT
I/O
I/O
ggg~ggg>gggg
0343-2
Maximnm Ratings
DC Output Current, per Pin . . . . . . . . . . .. -25 rnA to + 25 rnA
DC Input Voltagel1l .•...........•....... -2.0Vto +7.0V
DC Program Voltage .................... -2.0Vto +13.5V
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
StorageThmperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ........................... O°Cto +70°C
Maximum Junction Thmperature
(Under Bias) ................................... 150°C
Supply Voltage to Ground Potential ...... " - 2.0V to + 7.0V
MaximumPowerDissipation .................... 2500mW
DC Vee or GND Current. . . . . . . . . . . . . . . . . . . . . . .. 500 rnA
Electrical Characteristics
Parameters
VOH
VOL
Operating Range
Commercial
Industrial
Military
Description
Output HIGH Voltage
- 40°C to +85°C
5V±1O%
- 55°C to + 125°C(Case)
5V±1O%
Output LDW Voltage
Thst Conditions
Input HIGH Level
Input LDW Level
Ioz
Output LeakageCurrent
Output Short Circuit Current
GND is the lowest fre-
4-216
~CYPRESS
~-~
~"
CY7C343
SEMICONDUCTOR
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or asynchronous),
then the devices are guaranteed to function properly under worstcase environmental and supply voltage conditions, provided the
~lock signal source is the same. This also applies if expander logic
IS used in the clock signal path of the driving device, but not for the
driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing
the output data from the preceding device to change prior to the
arrival of the clock signal at the following device's register.
quency. The lowest of these frequencies is the maximum data path
frequency for the asynchronousconfiguration.
'J!le parame!e~ toH indicates the system compatibility ofthis deV.lce when. dn~mg other synchronous logic with positive input hold
times, WhICh IS controlled by the same synchronous clock. If tOH is
greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case
environmental and supply voltage conditions.
'J!le parame~e: tAOH indicates the system compatibility of this deVIce when dnvmg subsequent registered logic with a positive hold
time and using the same clock as the CY7C343.
E"P,"D,"~
DELAY
~
REGISTER
LOGIC ARRAY ,~
CONTROL DELAY IelR
H
-H
~
'EXP
INPUT
DELAY
H
liN
...... L-..W
ItAc
LOGIC ARRAY
DELAY
I
IpRE
I
IRSU
I
tLAD
I
RH
OUTPUT
DELAY
IRO
tCOMB
ItATCH
I-r-'
too
INPUTI
OUTPUT
,...~
txz
tzx
SYSTEM CLOCK DELAY tiCS
~
PIA
DELAY
tplA
~
~
I
CLOCK
DELAY
I
tiC
I
I
I
I
1/0 DELAY
110
FEEDBACK
DELAY
tFO
IL
I
r
Figure 1. CY7C343 Internal Timing Model
4-217
C3 43-5
•
~PRFSS
~.I1b.nCOIDUCl'OR
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range
CY7C343-2S CY7C343-30 CY7C343-35 CY7C343-40
Parameters
tpDl
tPD2
tPD3
tPD4
tEA
tER
Description
Min.
Dedicated Input to
CombinatorialOutputDelay[7]
Com'l & Ind
IJO Input to Combinatorial
Com'l & Ind
Output Delay£8]
Com'l & Ind
IJO Input to Combinatorial
Com'I&Ind
Output Delaywitb Expander
Delay£4, 10]
Mil
Input to Output Enable
Delay£4,7]
Com'l & Ind
25
25
Com'l & Ind
Mil
Com'l& Ind
Dedicated Input or Feedback
Set-Up Time to Synchronous
Clock Inputl7]
Com'I&Ind
tS2
IJO Input Set-Up Time to
Synchronous Oock Input[7,12]
Com'l & Ind
tH
Input Hold Time from
SynchronousClocklnput[7]
Com'l & Ind
Synchronous Clock Input
HIGH Time
Com'l & Ind
tWL
Synchronous Clock Input LOW
Time
Com'l & Ind
tRW
AsynchronousClearWidtbl4,1J
Com'l& Ind
tWH
51
Mil
Synchronous Clock to Local
Feedback to Combinatorial
Outputf4,11]
tSI
37
Mil
Com'l& Ind
tC02
39
Mil
Synchronous Clock Input to
Output Delay
teOl
14
Mil
30
Mil
15
Mil
30
Mil
0
Mil
Com'l&Ind
tRO
Asynchronous Oearto
Registered Output Delay[7]
Com'l & Ind
tpw
AsynchronousPreset Widtbl4, '/J
Com'l& Ind
AsynchronousPreset Recovery
Timel4,7]
35
44
53
44
53
44
55
44
55
58
73
58
73
30
35
30
35
30
35
30
35
16
20
16
20
35
42
35
42
20
25
20
25
35
42
35
42
0
0
0
0
8
10
12.5
10
12.5
25
30
35
30
35
30
35
30
35
25
30
25
25
Mil
4-218
Min.
Max.
ns
os
62
ns
65
os
87
ns
40
os
40
ns
23
ns
48
ns
28
ns
45
ns
0
ns
15
ns
15
ns
40
ns
40
os
35
30
35
30
35
30
35
30
35
Units
40
35
30
25
Mil
Com'I&Ind
30
12.5
Mil
Max.
35
12.5
Mil
tpR
Min.
30
10
Mil
Asynchronous Clear Recovery
Timel4,7]
Max.
10
8
Mil
Mil
tRR
Min.
25
Mil
Dedicated Input to
Combinatorial Output Delay
with Expander Delay[9]
Input to Output Disable
Delay£4,7]
Max.
40
ns
40
ns
40
~
E ....
:~
.F SEMICONDucrOR
CY7C343
-=CYPRESS
External Synchronous Switching Characteristics[6] Over Operating Range(continued)
CY7C343-25 CY7C343-30 CY7C343-35 CY7C343-40
Parameters
tpo
tCF
tp
fMAXI
fMAX2
fMAX3
fMAX4
tOH
Description
Min.
Asynchronous Preset to
Registered Output Delay[7]
Com'l& Ind
Synchronous Clock to Local
FeedbackInput[4, 13]
Com'l& Ind
External Synchronous Clock
Period (1/fMAX3)[4]
Com'I&Ind
External Maximum Frequency
(1/(tcOl + tS1»[4, 14]
Com'I&Ind
Internal Local Feedback
Maximum Frequency, lesserof
(1/(tSI + tCF» or (1/tCOl)[4, 15]
Com'l& Ind
Data Path Maximum Frequency,
least of 1/(tWL + tWH),
1/(tSI + tH), or (lItcOl)[4, 16]
Com'l& Ind
Min_
25
Mil
3
Mil
16
Mil
34
Mil
55
Mil
625
Mil
Maximum RegisterThggle
Com'l& Ind
Frequency (1/(tWL + tWH»[4, 17]
Mil
Output Data Stable Time from
Synchronous Clock Input[4, 18]
Max_
625
Com'l& Ind
3
Mil
Max_
Min.
Max.
30
35
30
35
3
5
3
5
20
25
20
25
27
22.2
27
22.2
43
33
43
33
50
40
50
40
50
40
50
40
3
3
3
3
Min_
Max. Units
ns
40
ns
7
ns
30
MHz
19.6
MHz
285
MHz
33
MHz
33
ns
3
Notes:
7.
This specification is a measure of the delay from input signal applied
to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or
35) to combinatorial output on any output pin. This delay assumes no
expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, and/or
asynchronous preset) is applied to a dedicated input only and no signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin, an additional delay equal to
tPIA shonld be added to the comparable delay for a dedicated input.
If expanders are used, add the maximum expander delay tEXP to the
overall delay for the comparable delay without expanders.
8. This specification is a measnre of the delay from input signal applied
to an I/O macrocell pin to any ontpnt. This delay assumes no expander
terms are used to form the logic function.
9. Thisspecification is a measure of the delay from aninputsignalapplied
to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13,31,33, 34, or
35) to combinatorial output on any output pin. This delay assumes expauder terms are used to form the logic function and includes the
worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
10. Thisspecificationisameasureofthedelayfromaninputsignalapplied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all
12.
13.
14.
15.
16.
17.
18.
4-219
feedbackiswithin the same LAB. This parameteristested periodically
by sampling production material.
Ifdata is applied to an I/O inputfor capture by a macrocell register, the
I/O pin set-up time minimums shonld be observed. These parameters
are tS2 for synchronous operation and tAS2 for asynchronous operation.
Thisspecification is a measure of the delay associatedwith the internal
register feedback path. This is the delay from synchronous clock to
LAB logic array input. This delay plus the register set-up time, tSh is
the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB.
This parameter is tested periodically bysamplingproduction material.
This specification indicates the gnaranteed maximum frequency, in
synchronous mode, at which a state machine confignration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs.
This specification indicates the guaranteed maximum frequency at
whichastatemachine,withinternal-onlyfeedback, can operate. Ifregister output states must also control esternal points, this frequency can
still be observed as long as this frequency is less than l/tcot. All feedback is assumed to be local, originating within the same LAB.
This frequency indicates the maximum frequency at which the device
may operate in data path mode. This delay assumes data input signals
are applied to dedicated inputs and no expander logic is used.
This specification indicates the guaranteed maximum freqnency, in
synchronousmode, atwhichanindividual outputorburiedregistercan
be cycled.
This parameter indicates the minimum time after a synchronous register clock inpnt that the previous register output data is maintained on
the output pin.
•
L~
CY7C343
~'~UCI'OR
External Asynchronous Switching Characteristics Over Operating Rangel6]
CY7C343-2S CY7C343-30 CY7C343-35 CY7C343-40
Parameters
tACOI
Description
Asynchronous Clock Input to
Output Delay[7]
Min.
Com'l&Ind
Mil
Com'l&Ind
tAC02
Asynchronous Clock Input to
Local Feedbackto
CombinatorialOutput[19]
tASI
Dedicated Input or Feedback
Set-Up Time to Asynchronous
Clock Inputl7J
Com'l&Ind
I/O Input Set-Up TlUle to
Asynchronous Clock Inputl7J
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'I&Ind
Mil
Com'l & Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l&Ind
tAS2
tAH
tAWH
tAWL
tACF
tAP
fMAXAI
fMAXA2
fMAxA.3
fMAxA4
tAoH
Input Hold Time from
Asynchronous Clock Input[7J
Asynchronous Clock Input
HIGH Timel7J
Asynchronous Clock Input
LOW Time[7, 20]
Asynchronous Clock to Local
FeedbackInput[4,21]
ExternalAsynchronous Clock
Period (1!fMAXA4)[4]
External Maximum Frequency
in Asynchronous Mode
lI(tACOI + tAS!)[4, 22]
Maximumlnternal
AsynchronousFrequencyl4,23]
Data Path Maximum Fre~ency
inAsynchronousMode[4, ]
Maximum Asynchronous
RegisterThggle Fre~ency
l/(tAWH + tAWr)[4, ]
Output Data Stable Timefrom
AsynchronousClocklnputl4,26]
Max.
25
Min.
Max.
30
Min.
30
40
46
Mil
46
5
Mil
20
6
11
9
33
Mil
Com'l & Ind
Mil
Com'I&Ind
Mil
Com'l & Ind
50
40
50
Mil
Com'l&Ind
Mil
15
Notes:
19. This specification is ameasure of the delay from an asynchronous registerclockinput to internal feedback of the register output signal to the
input of the lAB logic array and then to a combinatorial output. This
delay assumes no expanders are used in the logic ofcombinatorial output or the asynchronous clock input. The clock signal is applied to a
dedicated input pin and all feedback is within a single lAB. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge triggered clock at the
register. Fornegativeed~e triggering, the tAWH and tAwLparameters
must be swapped. If a gwen input is used to clock multiple registers
with both positive and negativepolarity,tAwHshouldbeusedforboth
tAWH and tAWL21. Thisspecification is ameasure of the delay associated with the internal
register feedback path for anasynchronousclockto lAB logic array input. This delay plus the asynchronous register set-up time, tAS!, is the
minimum internal period for an internal asynchronously clocked state
machine configuration. This delay is for feedback within the same
lAB,assumesno expanderlogicintheclockpath,and assumes that the
clock input signal is applied In a dedicated input pin. This parameter
is tested periodically by sampling production material.
22. This specification indicates the gnaranteed maximum frequency at
whichan asynchronously clocked state machine configuration with ex-
23.
24.
25.
26.
4-220
Min.
Max.
ns
55
64
8
6
8
10
25
25
8
8
14
14
11
11
30
30
34
ns
ns
ns
10
15
10
16
16
14
14
18
18
ns
17.5
ns
17.5
22
22
ns
26
25
25
27
30
30
23
35
27
23
18
40
40
33
33
27
33
33
28
28
Units
ns
45
6
15
20
Max.
35
35
55
ns
MHz
MHz
MHz
22
40
33
40
33
28.5
MHz
15
15
15
15
15
ns
ternal feedback can operate.ltis assumed that all data inputs, clock inputs, andfeedbacksignals are applied to dedicated inputs, and that no
expander logic is employed in the clock signal path or data path.
This specification indicates the gnaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. This parameter is determined by the lesser of
(l/tACF + tASt» or (l/(tAWH +tAWt.}). If register output states must
also control external points, this frequency can still be observed as long
as this frequency is less than l/tACOt.
This frequency is the maximum frequency at which the device may operatein the asynchronously clocked data path mode. Thisspecification
is determined by the least of l/(tAWH + tAWL), l/(tASl + tAH) or
l/tACOt. It assumes data and clock input signals are applied In dedicated input pins and no expander logic is used.
This specification indicates the gnaranteed maximum frequency at
whichanindividualoutputorburiedregistercanbecycledinasynchronouslyclocked mode by a clock signal applied to an external dedicated
input pin.
This parameter indicates the minimum tinle that the previous register
output data is maintained on the output after an asynchronous register
clock input.
;_
·rCYPRES'
3
F
CY7C343
SEMICONDUCIDR
Internal Switching Characteristics
Over Operating Rangel1]
Parameters
Description
Dedicated Input Pad and
tIN
Buffer Delay
tIO
I/O Input Pad and Buffer Delay
tEXP
Expander Array Delay
tlAD
Logic Array Data Delay
tlAC
Logic Array Control Delay
taD
Output Buffer and Pad Delay
tzx
Output Buffer Enable Delayl£/]
txz
Output Buffer Disable Delay
tRSU
Register Set-Up Time Relative
to Clock Signal at Register
tRH
Register Hold Time Relative to
Clock Signal at Register
tLATCH
Flow-Through Latch DeJay
tRD
Register Delay
tCOMB
'fransparent Mode Delayl£O]
tCH
Clock HIGH Time
tcr..
Clock LOW Time
tIC
Asynchronous Clock Logic
Delay
tICS
Synchronous Clock Delay
tFD
Feedback Delay
tpRE
Asynchronous Register Preset
Time
tcr..R
Asynchronous RegisterClear
Time
tpcw
Asynchronous Preset and Clear
Pulse Width
tpCR
Asynchronous Preset and Clear
Recovery Time
tPIA
ProgrammableInterconnect
Array Delay Time
Com'l&lnd
Mil
Com'l& Ind
Mil
Com'l&lnd
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l&lnd
Mil
Com'I&Ind
Mil
Com'I & Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'I&Ind
Mil
Com'l& Ind
Mil
Com'J& Ind
Mil
Com'l&lnd
Mil
Com'l&lnd
Mil
Com'I & Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'J&lnd
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l&lnd
Mil
Notes:
27. Sample tested only for an output change of 500 mY.
CY7C343 2S CY7C343 30 CY7C343 3S CY7C343 40
Min. Max. Min. Max. Min. Max. Min. Max. Units
ns
5
7
9
7
9
11
5
5
7
ns
5
7
9
12
14
20
ns
14
20
25
12
14
16
ns
14
16
18
12
13
ns
10
14
12
13
ns
5
5
6
7
5
6
10
11
13
ns
11
13
15
10
11
13
ns
11
13
15
10
ns
6
8
8
10
12
12
ns
6
8
12
14
8
ns
4
4
3
4
4
4
ns
2
1
2
2
2
2
4
ns
3
4
4
4
4
12.5
ns
10
8
10
12.5
15
12.5
8
10
ns
10
12.5
15
14
16
18
us
20
16
18
us
2
2
3
2
4
3
1
2
ns
1
1
2
3
ns
5
7
6
6
7
8
ns
5
6
7
8
6
7
ns
5
6
7
6
7
8
5
6
7
ns
6
7
8
ns
14
16
20
20
24
16
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-221
•
g
...I
0.
...J5
~~PRF.SS
~'~NDUCfOR
CY7C343
Switching Waveforms
External Combinatorial
~
DEDICATED
INPUTI _ _ _ _ __
I/OINPUT
,""",,,,,,'0 )
COMBINATORIAL
OUTPUT
=1--------4
COMBINATORIAL OR ------~----I------ tER!71
REGISTERED OUTPUT _ _ _ _ _ _--:-_____
HIGH-IMP~~~~~
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK[71
_ _ _ _ _ __
_
I------tEA[7!
_____________
4
HIGH-IMPEDANCE
3-STATE
VALID OUTPUT
-----------------
C343-6
~_.,....~
t51
SYNCHRONOUS
CLOCK _ _ _ _ __
ASYNCHRONOUS
~
CLEAR/PRESET!7] _ _ _ _H
__
+-+-_+--'
REGISTERED
OUTPUTS _ _ _ _ _-.,..-I'~
~
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK!11]
- - - - - - -
External Asynchronous
r
------C343-7
DEDICATED INPUTS OR ~
REGISTERED FEEDBACK[7] -
tAS1 .. I- tAH
I-
~
ASYNCHRONOUS
CLOCK INPUT
~
.. tRW/tpw- I--- tRR/tPR - - ~
I-
tAOH -
~"
""l~
tAC01
ASYNCHRONOUS
CLEARIPRESET!7]
tAWH- I- tAWl --
i'\.
... tRoItpo ....
~) K
ASYNCHRONOUS REGISTERED
OUTPUTS
I.
-:l
tAC02
j,
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-------C343-8
4-222
~
~~PRF.SS
~, ~bvncamuCl'OR
CY7C343
*
Switching Waveforms (continued)
Internal Combinatorial
INPUT PIN
1,0
liN
F_
-----00
lp'A - -
•
I
I/O PIN
I«-EXPANDER
ARRAY DELAY
IEXP--'
K
I I)
Q
- - lLAC,ILAO - - .
LOGIC ARRAY
INPUT
...I
a.
(
LOGIC ARRAY
OUTPUT
~
C343-9
j(1:= It
-J{
Internal Asynchronous
IR
CLOCK PIN
IAWH
liN
CLOCK INTO
LOGIC ARRAY
1V
14--
CLOCK FROM
LOGIC ARRAY
DATAARRAY
FROM _ _ _ _ __
LOGIC
}~IF
dI. '''--__
'- - .
*
-+- %
~-----------------
-.J/
I,C
1
,
'\........_ _ _
~ IRSU
Ifo
-
/
,'---------
~-------
...J
IRH
IRO,it.ATCH
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
IAWl
~
teLR,lpRE
-
-+ Ifo
k=
------------------------------Ip-~-J<-------------------C343-10
Internal Synchronous
}=
teH
SYSTEM CLOCK PIN __---:......;
SYSTEM CLOCK
AT REGISTER
DATAARRAY
FROM
LOGIC
=£
=~LI-~~
liN : t I I C S
__+-__
IRSU
~
IRH
=*
tel
--j
~
~
'\..
/
"--__- - J
,,'------
,,"-------
~------------------'__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
C343-11
4-223
-
~~PRF.SS
~_, SEMICONDUCTOR
CY7C343
Switching Waveforms (continued)
Output Mode
CLOCK FROM
LOGIC ARRAY _ _ _ _ _Jj
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C343-12
Ordering Information
Speed
(ns)
Ordering Code
Package
lYpe
Operating
Range
25
CY7C343-25HCIHI
H67
CommerciallIndustrial
CY7C343-25JC/n
J67
CY7C343-30HC/HI
CY7C343-30JCm
CY7C343-30HMB
H67
H67
Military
CY7C343-35HC/HI
H67
CommerciallIndustrial
30
35
40
CommerciallIndustrial
J67
CY7C343-35JC/n
J67
CY7C343-35HMB
H67
Military
CY7C343-40HMB
H67
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vrn
VIL
IIX
Ioz
ICC!
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
tpDl
7,8,9, 10, 11
7,8,9,10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tPD2
tPD3
tcO!
ts
tH
tACO!
tAC02
tAS
tAH
Document#: 38-00128-D
4-224
CY7C344
CYPRESS
SEMICONDUCTOR
32-Macrocell MAX® EPLD
Features
Functional Description
• High-performance,high-density replacement for TTL, 74HC, and custom
logic
• 32 macrocells, 64 expander product
terms in one LAB
• 8 dedicated inputs, 161/0 pins
• 28-pin 300-mil DIP, cerDIP or 28-pin
HLCC, PLCC package
Available in a 28-pin 300-mil DIP or windowed J -leaded ceramic chip carrier
(HLCC), the CY7C344 represents the
densest EPLD of this size. 8 dedicated inputs and 16 bidirectionalI/O pins communicate to one logic array block. In the
CY7C344 lAB there are 32 macrocells
and 64 expander product terms. When an
I/O macrocell is used as an input, two expanders are used to create an input path.
Even if all of the I/O pins are driven by rnacrocellregisters, there are still 16 "buried"
Logic Block Diagram[l]
registers available. All inputs, macrocelIs,
and I/O pins are interconnected within the
lAB.
The speed and density of the CY7C344
makes it a natural for all types of applications. With just this one device, the designercan implement complex state machines,
registeredlogic, and combinatorial "glue"
logic, without using multiple chips. This architecturalflexibility allows the CY7C344
to replace multichip TTL solutions, whether they are synchronous, asynchronous,
combinatoria1,or all three.
INPUT
INPUT
HLCC
1bpView
1(8)
15(23)
INPUT
INPUT/CLK
27(6)
INPUT
INPUT
13(20)
28(7)
INPUT
INPUT
14(21)
ggg~~gg
2(9)
1/0
1/0
1/0
MACROCElJ.2
VO
3(10)
MACROCElJ.4
1/0
4(11)
MACROCElJ.6
1/0
5(12)
6(13)
INPUT
INPUT
INPUT
INPUT/ClK
0
INPUT
INPUT
INPUT
INPUT
MACROCEll8
1/0
MACROCElJ. 10
1/0
9(16)
MACROCElJ. 12
1/0
10(17)
MACROCElJ. 14
1/0
11(18)
MACROCELL 16
VO 12(19)
MACROCElJ. 18
1/0
MACROCElJ. 20
MACROCEll22
VO 18(25)
VO 19(28)
MACROCEll 24
1/0
20(21)
MACROCElL 26
VO
23(2)
va
MACROCELl28
vo
24(3)
1/0
1/0
1/0
MACROCELL 30
1/0
25(4)
110
26(5)
VO
1/0
MACROCElJ. 32
Vee
Vee
GND
GNO
1/0
1/0
1/0
gg~~ggg
C344-2
CerDIP
1bpView
17(24)
INPUT
INPUT/ClK
vo
110
110
1/0
VO
INPUT
INPUT
1
2
3
INPUT
INPUT
VO
VO
VO
va
1/0
INPUT
INPUT
C344-3
Selection Guide
Maximum Access Time (ns)
MaximumOperating
Current(mA)
Maximum Standby
Current(mA)
7C344-20
7C344-25
7C344-35
20
200
25
200
220
220
150
170
170
35
200
Commercial
Military
Industrial
220
Commercial
Military
Industrial
150
170
Note:
1. Figures in 0 are for J-Ieaded packages.
MAX and MAX +PillS are registered trademarks of Altera Corporation.
4-225
II)
C
...J
D.
Pin Configurations
15(22)
II
220
150
170
~
·
~=CYPRESS
CY7C344
~, SEMICONDUClDR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Thmperature .................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied ........................... O°Cto +70°C
Maximum Junction Thmperature
(Under Bias) ................................... 150°C
Supply Voltage to Ground Potential. . . . . . .. - 2.0V to + 7.0V
MaximumPowerDissipation .................... 1500mW
DC Vee or GND Current. . . . . . . . . . . . . . . . . . . . . . .. 500 rnA
DC Output Current, per Pin . . . . . . . . . .. - 25 rnA to + 25 rnA
DC Input Voltage£2] .................... - 2.0Vto +7.0V
DC Program Voltage. . . . . . . . . . . . . . . . . .. - 2.0V to + l3.5V
Operating Range
Ambient
Thmperature
Range
Commercial
O°Cto +70°C
Vcc
5V±5%
- 40°C to +85°C
5V±1O%
- 55°C to +125°C(Case)
5V±1O%
Industrial
Military
Electrical Characteristics Over the Operating Range[3]
Parameters
VOR
VOL
VIR
VIL
IJX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Thst Conditions
Output LeakageCurrent
Output Short
Circuit Current
Power Supply
Current (Standby)
loz
los
IcC!
Min.
2.4
Max.
GND~VIN~VcC
2.2
- 0.3
-10
Vee + 0.3
0.8
+10
Vo = VccorGND
Vee = Max., VOUT
- 40
-30
+40
- 90
Vee = Min., lOR = - 4.0 rnA
Vee = Min., IOL = 8 rnA
VI = VeeorGND(NoLoad)
f = 1.0 MHz[4, 6]
Iccz
Power Supply Current
tR
tF
Recommended Input Rise Time
Recommended Input Fall Time
0.45
= 0.5V[4,5]
VI = VeeorGND(NoLoad)
f = 1.0 MHz[4, 6]
Units
V
V
V
V
Commercial
Military/lndustrial
Commercial
Military/lndustrial
IlA
IlA
rnA
rnA
150
170
200
220
100
100
rnA
rnA
rnA
ns
ns
Capacitance
Parameters
Description
InputCapacitance
OutputCapacitance
CIN
CoUT
Thst Conditions
VIN = 2Y, f = 1.0 MHz
VOUT = 2.0Y,f= 1.0MHz
Max.
10
10
Units
pF
pF
AC Test Loads and Wavefonns[7)
"""':;;: "pF
INCLUDING _
JIGAND SCOPE
Equivalent to:
1~
Ii'
5V~R1464n.
ALL INPUT PULSES
OUTPUT
5pF
I
. _ 25On.
-
(a)
'W;:=j1""
GND
R2
250n.
<6ns ....
10%
I.-
tR
(b)
C344-4
~
10%
If ....
--
~
< 6ns
C344-5
THEvENIN EQUIVALENT (commercial/military)
163n.
OUTPUT OO---"'ylllJ'_----OO 1.75V
C344-6
Notes:
2. Minimum DC input is -0.3Y. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.
3. Typical values are forTA = 25°C and Vee = sv.
4. Guaranteed but not 100% tested.
5. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems caused by tester ground degradation.
6.
7.
4-226
Measured with device programmed as a 16-bit counter.
Part (a) in AC Test Load and Waveforms is used for all parameters except tER and txz, which is used for part (b) inACThstLoadand Waveforms. All external timing parameters are measured referenced to external pins of the device.
CY7C344
Timing Delays
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to tst. Determine which of l/(twH
+ twd,1Itcot. or l/(tEXP + tSt) is the lowest frequency. The lowest of thjlSe frequencies is the maximum data path frequency for
the synchronous configuration.
Timing delays within the CY7C344maybeeasilydeterminedusing
MAX + PLUS® software or by the model shown in Figure 1. The
CY7C344 has fixed internal delays, allowing the user to determine
theworstcase timing delays for any design. Forcomplete timing in·
formation, the MAX +PLUS software provides atimingsimulator.
When calculating external asynchronous frequencies, use tASt if
all inputs are on dedicated input pins. If any data is applied to an
I/O pin, tAS2 must be used as the required set-up time. If (tAS2 +
tAW is greater than tACOt. 1/(tAS2 + tAlI) becomes the limiting
frequency in the data path mode unless l/(tAWH + tAwd is less
than 1/(tAS2 + tAlI),
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tASt. Determine which of
1I(tAWH + tAWL), 1ItACOt. or l/(tEXP + tASt> is the lowest frequency. The lowest of these frequencies is the maximum data
path frequency for the asynchronous configuration.
Design Recommendations
Operation of the devices described herein with conditions above
thoselistedunder'~soluteMaximumRatings"maycauseperma
nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this data sheet is not
implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344
contains circuitry to protect device pins from high staticvoltages or
electric fields; however, normal precautions should be taken to
avoid applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be constrained
to the range GND!i. (VINor VOUT) !i. Vex. Unused inputs must
always be tied to an appropriate logic level (either Vcc or GND).
Each set of Vex and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at
least 0.2 "F must be connected between Vex and GND. For the
most effective decoupJing, each Vex pin should be separately decoupled.
The parameter toH indicates the system compatibility of this device when driving other synchronous logic with positive input
hold times, which is controlled by the same synchronous clock. If
IoH is greater than the minimum required input hold time of the
subsequent synchronous logic, then the devices are guaranteed to
function properly with a common synchronous clock underworstcase environmental and supply voltage conditions.
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a positive
hold time and using the same clock as the CY7C344.
Timing Considerations
In general, iftAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or asynchronous),
then the devices are guaranteed to function properly under worstcase environmental and supply voltage conditions, provided the
clock signal source is the same. This also applies if expander logic
is used in the c10cksignal path ofthe driving device, but not for the
driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing
the output data from the preceding device to change prior to the
arrival of the clock signal at the following device's register.
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay
tEXP to the overall delay.
When calculating synchronous frequencies, use tSt if all inputs
are on the input pins. tS2 should be used if data is applied at an
I/O pin. If tS2 is greater than tcOl, 1Its2 becomes the limiting frequency in the data path mode unless 1I(twH + twd is less than
1ItS2·
I----M.
t:"tI
~
t-1--iI
INPUT
DELAY
~N
t:!I
-->;
t-1--iI
~_DCR~
DELAY
texp
REGISTER
,h
LOGIC ARRAY
CONTROL DELAY
'LAC
LOGIC ARRAY
DELAY
lLAD
OUTPUT
DELAY
leLA
I lfRe
OUTPUT
JI fRsu
'A
'AD
1-1'
too
txz
tzx
teOMB
!LATCH
H
SYSTEM CLOCK DELAY ~
VO
VO
'::!I
110
--iI
I/O DELAY
::
CLOCK
DELAY
IIC
I
I
I
FEEDBACK
I
D~Y
rL
Fignre 1. CY7C344 TIming Model
4-227
0344-7
""'"""
---...
•
I I)
C
..J
D.
CY7C344
External Synchronous Switching Characteristics[?] Over Operating Range
Parameters
tpDl
tpD2
tPD3
Description
Dedicated Inp'utto Combinatorial
Output Delay(8)
Com'l & Ind
I/O I~ut to Combinatorial Output
Dela )
Com'l&Ind
Dedicated Input to Combinatorial
Output Delaywith Expander Delay(10)
Com'l& Ind
CY7C344-20
CY7C344-2S
Min.
Min.
Max.
20
20
20
tER
Input to Output Disable Delay(4)
Com'l&Ind
20
Com'l&Ind
Com'l& Ind
12
Input Hold Time from Synchronous
ClockInput[?]
Com'l & Ind
Synchronous Oock Input HIGH Timel4)
Com'l&Ind
22
29
Mil
0
8
7
ns
8
10
ns
8
7
8
20
10
ns
25
35
25
Com'l & Ind
20
ns
25
Mil
35
25
Asynchronous Clear to Registered
Output Delay(4)
Com'l&Ind
AsynchronousPreset Width[4)
Com'I&Ind
20
ns
25
Mil
35
25
20
ns
25
Mil
AsynchronousPreset Recovery Timel4)
ns
0
0
Mil
tpR
ns
0
Mil
Com'l & Ind
37
21
15
Com'l&Ind
ns
15
Mil
tpw
20
29
12
Mil
tRO
ns
15
Mil
AsynchronousOear Recovery Timel4)
ns
35
15
Dedicated Input or Feedback Set-Up
Time to Synchronous Oock Input
tRR
35
25
Mil
ts
Asynchronous Clear Width(4)
ns
25
25
Synchronous Clock to Local Feedbackto Com'I&Ind
CombinatorialOutput[4, 12)
tRW
55
25
tC02
Synchronous Clock Input LOW Timel4)
ns
40
Mil
tWL
ns
55
40
Mil
tWH
us
35
40
Com'I&Ind
tH
us
40
30
Mil
35
25
Com'l&Ind
Mil
20
us
25
25
4-228
Units
35
25
Input to Output Enable Delay(4)
Max.
25
Mil
tEA
Synchronous OockInput to Output
Delay
Min.
25
30
tcOl
CY7C344-35
25
Mil
I/O Input to Combinatorial OutputDelay Com'I&Ind
with Expander Delay[4, 11)
Mil
tpD4
Max.
35
~
~~
--_.
=CYPRESS
,
SEMICONDUCTOR
CY7C344
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
Description
Parameters
tpo
tCF
AsynchronousPreset to Registered
Output Delay[4)
Com'l& Ind
Synchronous Oock to Local Feedback
Input!4,13)
Com'I&Ind
CY7C343-20
CY7C343-2S
CY7C343-3S
Min.
Min.
Min.
Max.
20
Mil
4
ns
7
ns
7
Com'l & Ind
External Maximum Frequency
(1/(tcOl + tS1»[4, 14)
Com'l & Ind
14
Mil
13
16
16
Units
35
25
External Smchronous Clock Period
(1/fMAX3) 4)
Max.
25
Mil
tp
Max.
ns
20
II
II)
fMAXl
62.5
45.4
Data Path Maximum Frequency, least of Com'l & Ind
1/(tWL + tWJI),1/(ts + tH),or(l/tcOl)[4, 16)
Mil
71.4
62.5
Maximum Regil!terToggie Frequency
1/(tWL + tWH)[4, 17]
Com'l & Ind
71.4
Output Data Stable TinIe from
SynchronousClockInputf4,18)
Com'l & Ind
Maximum Frequency with Internal Only Com'l & Ind
fMAX3
tOH
33.3
33.3
Mil
fMAX2
fMAX4
41.6
Feedback (1/(tep
+ ts»[4, 15)
45.4
Mil
62.5
3
MHz
29.4
MHz
47.6
MHz
50.0
3
3
Mil
24.3
62.5
62.5
Mil
MHz
ns
3
Notes:
8.
This parameter is the delay from an input signal applied to adedicated
input pin to a combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to
an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
10. This parameter is the delay associated with an input signal applied to
a dedicated input pin to combinatorial output on any output pin. This
delay assumes expander terms are used to form the logicfuoction and
includes the worst-case expander logic delay for one pass through the
expander logic. This parameter is tested periodically by sampling production material.
10. This parameter is the delay associated with an input signal applied to
an I/O macroceU pin to any output pin. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clockinputtointernalfeedbackoftheregisteroutputsignaltoacombinatoria! output for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the
combinatorial output and the re~ter is synchronously clocked. This
parameter is tested periodically by sampling production material.
13. Thisspecificationis ameasureofthedelay associated with the internal
registerfeedbackpath. This delayplus the register set-uptime, ts, is the
minimum internal period for an internal state machine coofiguration.
This parameter is tested periodicallybysamplingproductionmaterial.
14. This specification indicates the gnaranteed maximum frequency at
which a state machine configuration with external oniy feedback can
operate.
15. This specification indicates the gnaranteed maximum frequency at
whichastatemachinewithinternal-oniyfeedbackcanoperate. Ifregister output states must also control external points, this frequency can
still be observed as long as it is less than 1/tCOI. This specification assumes no expander logic is used. This parameter is tested periodically
by sampling production materia!.
16. This frequency indicates the maximum frequency at which the device
may operate in data path mode (dedicated input pin to output pin).
This assumes that no expander logic is used.
17. Thisspecificationindicates thegnaranteedmasimumfrequencyinsynchronousmode,atwhich an individnal output or buried register can be
cycled by aclocksignal applied to either a dedicated input pin or an I/O
pin.
18. This parameter indicates theminimum time after a synchronous register clock input that the previous register output data is maintained on
the output pin.
4-229
C
...I
0..
&;~CYPRFSS
~#
CY7C344
SEMlCONDUCfOR
External Asynchronous Switching Characteristics Over Operating Range[7]
Parameters
tACOI
tAC02
tAS
tAH
tAWH
tAWL
Description
Asynchronous Oock Input to Output
Delay
Min.
20
Com'l& Ind
Input Hold Time from Asynchronous
OockInput
Com'l&Ind
30
tAP
9
fMAXAI
fMAXAZ
fMAXA3
fMAXA4
tAOH
ns
15
ns
12
7
17.5
9
Mil
ns
9
15
11
9
ns
11
Asynchronous Clock to Local Feedback Com'l& Ind
Input[4,21]
Mil
Com'l & Ind
18
21
16
Com'l & Ind
Data Path Maximum Freffuency in
AsynchronousModd4, 24
Com'l & Ind
34.4
37
50
Com'l & Ind
50
15
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to
a combinatorial output for which the registered output signal is used
as an input. Assumes no expanders are used in logic of combinatorial
output or the asynchronous clock input. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggeredclockatthe
register. For negative edge triggering, the tAWH and tAwLparameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL.
21. Thisspecificationis ameasure of the delay associated with the internal
register feedback path for an asynchronously clocked register. This
delay plus the asynchronous register set-up time, tAs, is the minimum
internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in the asynchronous clock
path. This parameter is tested periodically by sampling production material.
22. Thisparameterindicates the guaranteed maximum frequency at which
an asynchronously clocked state machine configuration with external
feedbackcan operate. It is assumed thatno expander logic is employed
in the clock signal path or data path.
MHz
28.5
50
MHz
33.3
15
15
Mil
MHz
23.8
40
40
62.5
MHz
20
30.3
30.3
Mil
ns
30
27
27
Mil
MaximumAsynchronousRef,isterToggle Com'l & Ind
Frequency1J(tAWH + tAwL> 4, 25]
Mil
ns
27
20
20
Maximum InternalAsynchronous
Frequency1J(tACE +zW» or
1/(tAWH + tAWL)[4,
15
21
Mil
External Maximum Frequency in
Com'l & Ind
Asynchronous Mode 1J(tACOI + tAS)[4,22]
Mil
Output Data Stable Time from
AsynchronousClockInput[4,26]
ns
49
12
Mil
AsynchronousOock Input LOW Timel4J Com'I&Ind
(lIfMAX4)[4
37
12
HIGH Com'I&Ind
External~chronous Clock Period
ns
12
Mil
Units
35
37
9
Max.
25
Mil
Mil
tACF
Max.
25
Dedicated Input or Feedback Set-Up
Time to Asynchronous Clock Input
Input
CY7C344-35
Min.
Max.
Mil
Com'l & Ind
Oock
CY7C344-25
Min.
Com'I&Ind
Asynchronous Clock Input to Local
Feedback to Combinatorial Outputl l9]
Asynchronous
Tund4,20]
CY7C344-20
ns
15
23. This specification indicates the guaranteed masimum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency
is less than 1/tACOl. Thisspecificationassumesnoexpander logicisutilized. Thisparameteristestedperiodicallybysamplingproductionmaterial.
24. This specification indicates the guaranteed maximum frequency at
whichanindividual output or buried register can be cycledinasynchronously clocked mode. This frequency is least of l/(tAWH + tAwL),
1/(tAS + tAR), or 1/tACOl. It also indicates the maximum frequency at
which the device may operate in the asyochronously clocked data path
mode. Assumes no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at
whichan individual output or buried register can be cycled inasynchronously clocked mode by a clock signal applied to an external dedicated
input or an I/O pin.
26. This parameter indicates the minimum time that the previous register
output data ismaintained on the output pin after an asynchronous register clock input to an external dedicated input or I/O pin.
4-230
~
=.
,::.z
--=-,=
==-=oi
CY7C344
CYPRESS
SEMICONDUCTOR
lYPical Internal Switching Characteristics OverOperatingRangel2]
Parameters
Description
Dedicated Input Pad and Buffer Delay
tIN
tIO
tEXP
tLAD
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
tLAC
Logic Array Control Delay
tOD
Output Buffer and Pad Delay
tzx
txz
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
tCL
tIC
tICS
tpD
tpRE
tCLR
tpcw
tpCR
Output Buffer Enable DelayLUJ
Output Buffer Disable Delay
Register Set-UpTime Relative to
Clock Signal at Register
Register Hold Time Relative to
Clock Signal at Register
Flow-Through Latch Delay
Register Delay
Transparent Mode Delay!:a>J
Clock HIGH TIme
Clock LOW Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and Clear
Pulse Width
Asynchronous Preset and Clear
Recovery Time
Notes:
27. Sample tested only for an output change of 500 mY.
CY7C344-20
Min.
Max.
Com'l& Ind
Mil
Com'I&Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'I&Ind
Mil
Com'1 & Ind
Mil
Com'1 & Ind
Mil
Com'I&Ind
Mil
Com'l& Ind
Mil
Com'1 & Ind
Mil
Com'1 & Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'1& Ind
Mil
Com'1&Ind
Mil
Com'1 & Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'I&Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
5
5
CY7C344-25
Min.
Max.
7
7
7
7
9
7
8
ns
12
ns
12
ns
ns
2
1
ns
3
3
5
1
1
1
3
3
5
ns
ns
ns
8
8
8
8
8
9
ns
9
10
10
12
3
3
5
1
1
1
ns
ns
ns
ns
9
9
9
9
6
6
5
ns
8
15
7
7
7
7
12
ns
12
ns
9
ns
9
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-231
II
tn
C
...I
D.
7
12
12
1
5
ns
11
1
7
ns
11
8
8
1
7
ns
20
5
5
11
11
11
11
8
9
ns
11
7
7
5
Units
ns
11
15
15
10
10
10
5
CY7C344-35
Min.
Max.
CY7C344
Switching Waveforms
External Combinatorial
~
DEDICATED INPUT!
I/O INPUT - - - - - - -
~ tpD1/tpD2 ~_ _ _ _ _ _ __
COMBINATORIAL
OUTPUT
=3------
_
I---- tER
_ _OUTPUT
_ _ _ _ __
HIGH-IMPEDANCE - - - - - - - I----tEA=4
- _ _ _ _ _ _VALID
COMBINATORIAL OR - - - - - - - - - - REGISTERED OUTPUT _ _ _ _ _ _'"'""':'____
HIGH-IMPEDANCE
3-STATE
~STATE
C344-8
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
=f
_ _ _.,.-_
Is
SYNCHRONOUS
CLOCK _ _ _ _ _-'
ASYNCHRONOUS
~H
CLEAR/PRESET _ _ _ _ _~~--+--'I
REGISTERED
OUTPUTS _ _ _ _ _--,~I'-:v
~~~---- ~2 --------~~
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK!11!
- - - - - - -
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
------C344-9
=i
....._-.-_ _
tAS1
ASYNCHRONOUS
CLOCK INPUT _ _ _ _ _..J
ASYNCHRONOUS
tAOH
CLEAR/PRESET - - - - - - I - I - - - - l l - ' I
ASYNCHRONOUS REGISTERED
OUTPUTS -------,:---1l'-v
------*~~_ _ _ _ _ __
1+-'----'----COMBINATORIAL OUTPUT FROM _ _ _ _ _ _ _
_ _ _ _ _tAC02
_______
ASYNCH. REGISTERED
FEEDBACKl19]
C344-10
4-232
~
.
:~
-----.;
-= CYPRESS
.# SEMlCONDUCfOR
CY7C344
Switching Waveforms (continued)
Internal Combinatorial
tlN_
*
INPUT PIN
j:::=-
110
tplA -
I
I/O PIN
-
EXPANDER
ARRAY DELAY
tEXP----
(
!-- 1t.Ac, It.Ao ----
LOGIC ARRAY
INPUT
'(
LOGIC ARRAY
OUTPUT
-c.'(
C344-11
Internal Asyncbronous
tR
~I:= tAWH
CLOCK PIN
tiN
CLOCK
INTO
LOGIC
ARRAY
It
1llC
\.
;1(. ,,'--_--J/...---t
-+- 1
-+- *=
IRSU
DATAARRAY
FROM _ _ _ _ _ _
LOGIC
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
~-----------------
/-
,'"
_ _ _ _ _-J.
t
~
--l{
}~tF
\.
_.
CLOCK FROM
LOGIC ARRAY
tAwl
' ' "_ _ _ _ _ _ __
~
tRH
_ _ _ _ _ __
tRD,tLATCH
tFa
teLR,tpRE
IFD
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _t_
PI__
A ] (_ _ _ _ _ _ _ _ _ _ ___
REGISTER OUTPUT
TO ANOTHER LAB
C344-12
Internal Syncbronous (Input Path)
I::::
Jr
=f
teH
SYSTEM CLOCK PIN _ _ _
SYSTEM CLOCK
AT REGISTER
r-
t'NltICS
----+----~
DATAARRAY
FROM
LOGIC
tRSU
"
=;L
--j /
~~
~
tRH
=*
tel
'\..
......_ - - - -
/
~---~
" _-......
~---------------------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
C344-13
4-233
CY7C344
Switching Waveforms (continued)
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C344-14
Ordering Information
Speed
(ns)
20
25
35
CY7C344-200CIDI
Package
lYPe
022
CY7C344-2OHC/HI
H64
Ordering Code
CY7C344-2OJClJI
J64
CY7C344-2OPC/PI
P21
CY7C344-2OWC/WI
W22
CY7C344-250CIDI
022
CY7C344-25HC/HI
H64
CY7C344-25JClJI
J64
CY7C344-25PC/PI
P21
CY7C344- 25WC/WI
W22
CY7C344-250MB
022
CY7C344-25HMB
H64
CY7C344-25WMB
W22
CY7C344-350MB
022
CY7C344-35HMB
H64
CY7C344-35WMB
W22
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Operating
Range
Commercial/lndustrial
Commercia1!Industrial
Military
Military
Switching Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
VOL
VIR
VIL
IJX
Ioz
ICCl
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tpDl
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tPD2
tPD3
taH
ts
tH
tACOl
tACOl
tAS
tAH
Oocument#: 38-00127-B
4-234
CY7C361
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• High speed: 125-MHz state machine
output generation
-Thken passing
- Multiple, concurrent processes
- Multiway branch or join
• One clock with programmable clock
doubler
• Programmable miser bits for power
savings
• 8 to 12 inputs with input macrocells
- Metastability hardened: 10-year
MBTF
- 0, 1, or 2 input registers
- 3 programmable clock enables
• 32 synchronous state macrocells
• 10 to 14 outputs
- Skew-controlled OR output array
- Outputs are sum of states like PLA
Ultra High Speed
State Machine EPLD
• Security fuse
• Available in 28-pin slimline DIP and
28-pinPLCC
• Low-power "C' versions
-150 rnA max. at 125 MHz
• IN-erasable and reprogrammable
• Programming and operation 100%
testable
Product Characteristics
The CY7C361 is a CMOS erasable, programmablelogic device (EPLD) with very
high speed sequencing capabilities.
Applicationsincludehigh-speed cache and
I/O subsystems control, control of highspeed numeric processors, and high-speed
arbitration between synchronous or
asynchronoussystems.
A programmable on-board clock doubler
allows the device to operate at 125 MHz internally based on a 62.5-MHz input clock
reference. The clock doubler is not a
phase-lockedloop. It produces an internal
pulse on each edge of the external clock.
The length of each internal pulse is determined by the intrinsic delays within the
CY7C361. When the doubler is enabled,
all macrocells in the CY7C361 are referenced to the doubled clock. If the clock
doubleris disabled, a 125-MHz input clock
can be connected to pin 4, and it will be
used as a clock to all macrocells.
The CY7C361 has two arrays, similar to
those in a PLA except that the registers are
placed between the two arrays so that the
long feedback path of the PLA is eliminated.
Logic Block Diagram
B2
Pin Configurations
17
Is
15
14
13
GND Vee
12
11
LCC, PLCCJ.and HLCC
Thp view
114I113I[i2J1i1l1iOlf91f91I7lf9115l
4 3 2 1 282726
U
25
I,
M3
M.
I.
GND
7C361
Vee
Vee
GND
GND
1:3
M,
Mo
'"
I,
CI)~C\I(')o
.....
C\I
0361-2
--mmD..n.D..
STATE REGISTERS
OUTPUT ARRAY
0361-1
Selection Guide
Generic Part Number
CY7C361-125
Com
200
CY7C361-1OO
200
CY7C361-83
CY7C361-66
Icc rnA at fMAX
Com"C'
Mil
Mil"C'
150
150
150
150
fMAXMHz
Com
Mil
125.0
200
tIsns
Com
Mil
150
100.0
100.0
2
3
150
150
83.3
66.6
83.3
66.6
5
5
4-235
3
5
5
tco ns
Com
Mil
15
19
23
23
19
23
25
•
II)
C
...J
a..
PRELIMINARY
Product Characteristics (continued)
In the CY7C361, the state information is contained in 32 state
macrocells sandwiched between the input and output arrays. The
current state information is fed back fast enough to achieve the
125-MHz operating frequency. These state macrocells also have
serial connections that allow state machines to be built using a taken-passing methodology similar to one hot encoding, but with
the ability to support multiple active states at any given time.
The output array performs an OR function over the state macrocell outputs, allowing thll control signals of the state machine to
be produced directly_ The signals from the output array are connected to the 14 device outputs (4 of which are bidirectional). In
addition there are 3 sum terms that act as clock enables to the 3
groups of input macrocells. There are also 4 sum term output enables for the 4 bidirectional pins.
Input MacroceUs
The CY7C361 has 12 input macrocells, shown in Figure 1. Each
macrocell can be configured to have 0, 1, or 2 registers in the
path of the input data. In the configuration where there is no input register, the set-up time required is the longest, because it includes the propagation delay through the input array plus the
state register set-up time. In the single-registered configuration
the set-up time is less than half of the unregistered case_ The
double-registered configuration is used to synchronize asynchronous inputs without causing metastable events.
TO
INPUT
ARRAY
DATA
CLOCK
C1 CO
ENABLE _ _~~_ _---J
Figure 1. Input Macrocell
Input Register Enables
The input macrocells are divided into 3 groups of 4 macrocells
each. Each of these groups has a register clock enable coming
from the output array. The assignment of enable signal node
numbers to input macrocells is as follows:
Input Nodes
EnabJeNode
3,5,6,9
29
10, 11, 12, 13
30
1,2,14,15
31
When the enable node is true, data is clocked into the registers of
the input macrocells on the rising edge of the internal global clock.
Metastability Immunity
A high level of metastable. immunity is afforded in the doubleregistered configuration. The CY7C361 registers are done in fast
CMOS and they resolve inputs in a minimal amount of time.
With all inputs switching at maximum frequency, one metastable
event capable of violating the set-up time ofa subsequent register
occurs every 10 years. The probability of failure in a configured
state machine is much lower than this calculation suggests, because there are more registers in the device and thus more decision time is allowed. No state machine failures due to metastable
phenomena will be observed if the maximum frequency and
double-registered operation frequency are used. This makes the
CY7C361 ideally suited for constructing state machines requiring
CY7C361
arbitration. For more information on metastability, refer to the
"Are Your PLDs Metastable?" application note in the Cypress
Applications Handbook.
Input Array
The inputarrayis based on the condition decoder, shown inFigure
2. In aconventional PLA or PlD device, only PRODUCT1 would
be present in the fITSt array and the output and the feedbackwould
be encoded by a second programmable or fixed or array. The
speed of state machines is limited mainly by the feedback path.
PRODUCT 1
PRODUCT 2
MISER
Figure 2. Condition Decoder
The condition decoder of the CY7C361 forms a productofa product and a sum over the input field. (The sum term is obtained by
inverting the inputs to PRODUCI'2.) Since there is immediate
feedback information in the input field, multiwayfork and join operations can be performed using this type of condition decoder. In
other words, the condition decoder is used to control or gate the
token being passed from macrocell to macrocell. In contrast, a
traditional PlD or PLA requires more logic because the array is
used to encode the states. In the CY7C361, state transitions can be
made in half the time because there is no "state encoding" delay.
Each condition decoder has a miser bit in its sum term path. If
the term is not used, the miser bit is automatically programmed.
The miser bit completely disconnects the product term and replaces it with a logic HIGH. This results in a power savings.
The input array has 41 condition decoders: one global reset decoder, 8 local reset decoders, and 32 macrocell decoders. The
array has 44 true/complement input pairs, 88 inputs total.
For speed reasons, the feedback signals are segmented. This
means that for each group of 8 macrocells, 2 have global feedback,
2 have intermediate feedback to 16 of the 32 macrocells, and 4
have local feedback within their group of 8 macrocells only. Segmenting the feedback reduces the number of inputs per decoder
to 56. Because the CY7C361 utilizes token passing, a large state
machine will be effectively broken down into several smaller machines using 4 or less macrocells. The global and intermediate
feedbackisused to communicate between these smaller machines,
and the local feedback is used within the smaller machines. For
more information on the hot state encoding or token-passing design methodology, refer to the application notes titled "State Machine Design Considerations and Methodologies" and "Understanding the CY7C361" in the Cypress Applications Handbook.
State Machine Macrocells
The CY7C361 has 32 state macrocells. The state macrocells each
have a single condition decode and share a common clock and
global reset condition. The global reset is synchronous, and it
lasts for two internal clock cycles. For each group of four state
macrocells, there is a synchronous local reset condition.
AIl 32 of the macrocells are "daisy-chained." Each has a C_IN input that is connected to the C_OUT output of the previous macrocell, as shown in Figure 3. Configuration bit C2 is used in all state
macrocells to select C_IN to be active (C2=0) or inactive (C2=1).
4-236
-=-. :,~PRFSS
:J
iF
PRELIMINARY
CY7C361
SEMICONDUCTOR
the condition decoder fires, which causes the token to be terminated. Another way of saying this is that the TERMINATE macrocelJ is like a synchronous SR flip-flop. It is set by C_IN and
reset by the condition decoder. Local resets have no effect on this
configuration.
CONDo
DECODE
STATE
INPUT
lOCAL
RESET
GLOBAL
RESET
CLOCK
0361·5
•
Figure 3. CY7C361 Macrocell
For the topmost macrocell (node 32), the C2 bit is used to specify
a reset option. If the bit is 0, then the C_IN for this macrocell will
be true (1). If the C2 bit is 1, then the C_IN for the macrocell will
be false (0).
There are three state macrocell configurations: START,
TOGGLE, and TERMINATE. The purpose of the START configuration is to create a "token" based on the condition decode.
The TOGGLE configuration is used for building counters. The
TERMINATE configuration is used to insert wait states in a process. It captures a token and holds it until a condition tells it to
terminate the token.
Figure 4 shows a state macrocell in the START configuration. This
configuration synchronously creates a token if C_IN or the condition decode is a logic HIGH. The token is represented by a true
output on the macrocell register going to the output array and back
as feedback to the input array. A machine implemented in the
CY7C361 will consist of multiple machines or processes running
concurrently, each with zero, one or more tokens active at any given time. Put anotherway, each state macrocelJ in the CY7C361 can
be thought of as a line of microcode that can execute concurrently.
I I)
C
..J
Q.
Cl,CO = 0,1: TERMINATE
Figure 5. Terminate Configuration
The TOGGLE macrocell (see Figure 6) operates like aT-type
f1ip- flop. If C_IN or the condition decode is asserted, the state
register will toggle on every rising edge of the internal clock. If
neither the C IN nor the condition decoder are asserted, the
state register will retain its current state. The TOGGLE configuration is used to build counters. A local reset condition will synchronously reset the state register in this configuration.
c IN
ARRAY
STATE
INPUT
ARRAY
0361·8
C1,CO = 1,0: TOGGLE
Figure 6. Toggle Configuration
0361-6
The Output Array
Cl,CO = 0,0: START
Figure 4. Start Configuration
In addition to the main register going to the array, there is an R-S
latch in the feedback path that is used to convert the input condition to a pulse.
In operation, the START macrocell starts from a reset condition
(output array input = FALSE). When a condition decode "fires"
or a token is carried in (C_IN), the register output (Q going to
the array) goes true for exactly one cycle. The OR of the condition decode and the C_IN must go FALSE before the START
configuration can fire again. Local resets have no effect on this
configuration.
The TERMINATE macrocell (see Figure 5) captures a token via
thc C_IN path. The token is then held in the state register until
The output array is an OR-based array. The array inputs are the
LOW-asserted outputs of the 32 state macrocells. There are five
types of array outputs. The first type is the three clock enables for
the input macrocells. Each enable is a programmable OR of asserted state macrocelJs; when one of the connected macrocells is
asserted, the clock is enabled. Next are the four output enables of
the bidirectional I/O pins. Again, the output enables are a programmable OR of the connected asserted state macrocells; when
onc ofthc connected macrocells is asserted, the output is enabled.
The third type of array outpnt is the "pure" device output. These
six outputs are a functional OR of the low asserted outputs of the
state registers. Next is the output path of the four bidirectional I/O
pins, which is identical to that of the "pure" outputs. The last type
of array output is the Mealy output macrocell. The CY7C361 has
four of these outpu ts; they can be nsed as a fast combinatorial ontput. The three device outputs are pictured in Figure 7. Note that
the Mealy output is the only one that is configurable.
4-237
PRELIMINARY
~NORMAl
~OllTPUT
OR TERM
~
_O:.,;R,;,.TE..:.;,:;RM;.:...___
BIDIRECTIONAL
OllTPUT
INPUT _ - - - - '
C1 CO
C2
MEALY
OllTPlIT
L-----Ill
c361-9
FUNCTION
Figure 7. Start Configuration
In order to reduce output skew, the CY7C361 output array contains a set of self-timed latches in the output array path. These
latches are controlled by an internal cIock that has a delay equal
to the worst-case path through the output array. While this
delayed internal clock is LOW, the output array data is latched.
When the delayed internal clock is mOH, the latches become
transparent, and the outputs change. These latches are the reason
why the teo max is 15 ns with respect to the state registers, but
the part can change its outputs every 7.5 ns. Since these latches
cannot be accessed by the user, they have been left off of the
block diagram.
The normal output signal from the device is a boolean sum of a
subset of the state macrocell outputs. The subset selection is programmed into the output array. The number of state machines in
the device, and the output mappings of each are determined by
the user. The architecture is thus "horizontally divisible" and of-
CY7C361
fers advantages in coding efficiency and event response time over
the non-divisible architectures found in most PLA and sequencer
implementations.
An output pin is normally LOW-asserted. The output gate performs an OR function over the flip-flop outputs of the state macrocells. The OR function includes only the outputs that are programmed to be connected to the OR line in the output array.
When none of the connected state macrocell flip-flops are in the
true or set condition, the output is mOH, or deasserted. If any
connected macrocell flip-flop is asserted (true) then the OR gate
function is true and the output pin is LOW.
Forcing a false condition is easily accomplished by disconnecting
all of the state macrocells from the OR line. 1b force a true
condition, the OR line is connected only to node 73, which is labeled as Vee in the block diagram. Any OR line connected to
this node will be forced permanently true, which will cause any
normal output to always be LOW.
The bidirectional outputs are I/O pins that may be used as either
inputs or outputs. Under state machine control, these pins may
be three-stated and used as inputs or outputs depending on how
the DE term is programmed. If the DE is connected to node 73,
the pin will always function as an output.
The Mealy outputs are designed to implement the fastest possible
path between a device input and an output. Functions are available that combine the OR term and a specific input signal. These
functions, XOR, AND, and OR, coupled with output polarity
control are useful for data strobes and semaphore operations
where signaling occurs based on the current state, but independent of a signal transition.
The AND and OR functions can be used to gate data strobe signals by the state. The XOR function can be used to implement
two-cycle signaling, which is used in self-timed systems to minimize signaling delays. If these functions are not needed, then the
Mealy outputs can be configured as normal outputs.
Maximum Ratings
(Above which the useful life may be impaired. For user gnidehnes, not tested.)
Storage'Thmperature .................. - 65°C to + 150°C
Ambient 'Thmperature with
Power Applied ....................... - 55°C to +l25°C
Supply Voltage to Ground Potential
(DIP Pins 7 or 22 to Pins 8, 21, or 23) ...... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to +7.0V
DC Voltage Applied to Outputs
During Programming ...................... O.OV to +7.0V
DC InputVoItage ....................... - 3.0Vto +7.0V
DC Programming Voltage .......................... 13.0V
Output Current into Outputs (LOW) ................ 8 rnA
UV Exposure ............................ 7258 Wsec/cm2
Static Discharge Voltage ........................ >2OO1V
(per MIL-STD-883, rvfethod 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
4-238
Range
Commercial
Military
Ambient
Temperature
O°C to +70°C
Vee
5V± 10%
- 55°C to +l25°C
5V± 10%
·~PRESS
PRELIMINARY
CY7C361
- , SEMICONDUCTOR
Electrical Characteristics Over the Operating Range
Parameters
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
VOL
Output WW Voltage
= Min., V IN = VIH or V IL
Vee = Min., VIN = VIH or VIL
= -4.0mA
IOL = 8.0 rnA
VIH
Input HIGH Level
Guaranteed HIGH Input, All Inputs[l]
VIL
Input WW Level
Guaranteed LOW Input, All Inputs[3]
IIX
Input Leakage Current
Ioz
Output Leakage Current
= Max.
= Max., Vss < VOUT< Vee
Vee = Max., VOUT = O.5V[3]
Vee = Max., VIN = GND,
Outputs Open,
Operating at f = fMAX
Vee
Isd2 ]
Output Short Circuit Current
IecL2J
Power Supply Current
IOH
Max.
Units
2.4
V
0.4
V
0.8
V
J.IA.
J.IA.
2.2
V
Vss < VIN < Vee, Vee
-to
+10
Vee
-40
+40
-30
-110
mA
150
rnA
Commercial "~J
200
rnA
Military
3.
shoots due to system or tester noise are included.
2.
Tested initially and after any design or process changes that may affect
this parameter.
AC Test Loads and Waveforms
R14810
OUTP~~ ~
I
30 PF
INCLUDING _
JIG AND
SCOPE
Equivalent to:
Not more than one outpnf should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
TI
R14810
R2
OUTP~~
2550
I
5 pF
_
-
ALL INPUT PULSES
3.0V--90%
R2
2550
GND
__
-<361-10
(a)
<361-11
(b)
THEvENIN EQUIVALENT
1670
OUTPUT
o-------wv-----
1.73V
<361·12
Test Waveforms
Parameter
teER(-)
Vx
O.OV
Output Waveform-Measurement Level
O.5V
tcER(+)
2.6V
tcEA(+)
O.OV
1.5V
Vx
tcEA(-)
2.6V
~
~
O.5V
VOL
Vx
1.5V
~~
~
VOH
~
4-239
7~
7~
~~
I II
C
a..
Commercial
Notes:
1. These are absolute values with respect to device ground and all over-
•
....I
Military"~'
Vx
<361-13
Vx
C361·14
VOH
<361-15
VOL
<361-16
PRELIMINARY
CY7C361
Switching Characteristics Over the Operating Range[4,51
Commercial
-100
-125
Parameters
Description
-66
-83
Min,
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
2
9
2
11
2
12
2
15
os
tpD
Input to Mealy Output Delay
tcol bJ
Clock to Output Delay
15
19
23
25
os
tCMlbJ
Clock to Mealy Output Delay
17
20
25
28
os
tOH
Output Stable Time
tiS
Input Register Input Set-Up Time
5
os
5
5
os
5
5
os
12
14
os
0
0
9
0
11
os
7
6
7
9
11
os
Input Clock Period (Doubler Enabled)
15
20
24
30
os
Input Clock Pulse Width HIGH
2
4
5
ns
Input ClOck Pulse Width LOW
2
3
3
10
4
5
os
State Register Input Set-Up Time
t';7J
State Register Input Hold Time
tDWHlz,H,~J
Input Clock Pulse Width HIGH
(Doubler Enabled)
tDWLI~,H,>J
Input Clock Pulse Width LOW
(Doubler Enabled)
tDp14>J
tWLl.t.,~,lUJ
5
4
Input Register Input Hold Time
tslIJ
H,lUJ
5
3
9
tm
tWHl~,
5
2
3
7
0
6
os
tplZ, lUJ
Input Clock Period
tsolH]
Output Skew
2
2
2
2
os
tSMI1ZJ
Mealy Output Skew
3
3
3
3
os
fMAXII~,
lUI
7.5
12
72.9
os
Input Maximum Frequency
(Doubler Enabled)
62.5
fMAX lZJ
tCERl44J
Output Maximum Frequency
125.0
Clock to Output Disable Delay
16
20
22
25
os
!eEAl.t., U, 14J
Clock to Output Enable Delay
16
20
22
25
os
Notes:
4. Output reference point on AC measurements is l.Sy, except as noted
in Thst Waveforms:
1eER(-) negative going is measured at VOH - O.Sv.
1eER(+) positive going is measured at VOL + O.SV
S. Part (a) of ACThst Loads and Waveforms is used for all parameters
except tCEA and leER. Part (b) of AC Thst Loads and Waveforms is
used for ICEA and teER.
6. This specification is Il"aranteed for the worst-case programmed pattern for which all deYlceoutputs are changing state on a given access or
clock cycle.
7. Input register bypassed.
8. The clock input is tested to accommodate a 60140 duty cycle waveform
at the maximum frequency.
9. This applies to the input clock when the doubler is enabled.
50.0
15
100.0
MHz
33.3
MHz
66.6
83.3
10. This applies to the input clock when the doubler is disabled.
11. This parameter specifies the maximum allowable teo clock to output
delay difference, or skew, between any two outputs on the same device
triggered by the same clock edge with all other device outputs changing state Within the same clock cycle.
12. This parameter specifies the maximum allowable tpD difference between any two Mealy outputs on the same device triggered by the same
or simultaneous input signals with all other device outputs changing
state within the same access or clock cycle.
13. Rl is disconnected for ~ +) positive going (open circuited). See
part (b) of AC Thst Loads and Waveforms.
14. R2 is disconnected for ~ _) negative going (open circuited). See
part (b) of AC Thst Loads and Waveforms.
4-240
~7l~
PRELIMINARY
CY7C361
Switching Characteristics Over the Operating Rangel4,5]
Military
Parameters
Description
tpo
Input to Mealy Output Delay
tcol6J
Clock to Output Delay
tCMl6J
Clock to Mealy Output Delay
tOH
Output Stable Time
tIS
Input Register Input Set-Up Time
tm
tspj
State Register Input Set-Up Time
tHl/j
State Register Input Hold Time
tOWHI4~, ~J
Input Clock Pulse Width mGH
(Doubler Enabled)
tOWLL"~"J
Input Clock Pulse Width LOW
(Doubler Enabled)
topL2,9J
tWHL2,~,1OJ
tWLlz,~,lUJ
-66
-83
-100
Min.
Max.
Min.
Max.
Min.
Max.
Units
1.5
11
1.5
13
1.5
15
os
23
25
os
25
28
os
19
21
5
3
4
9
0
7
9
5
5
5
14
0
11
7
9
11
os
Input Clock Period (Doubler Enabled)
20
Input Clock Pulse Width LOW
3
3
tplZ, 10J
Input Clock Period
10
24
4
4
12
30
5
5
15
os
Input Clock Pulse Width HIGH
tsolllJ
Output Skew
tSM1l"J
Mealy Output Skew
fMAXIL4 lUJ
Input Maximum Frequency
(Doubler Enabled)
fMAXL2J
Output Maximum Frequency
tCERL4J
tCEALZ, 13, 14J
Clock to Output Disable Delay
20
22
Clock to Output Enable Delay
20
22
Input Register Input Hold Time
5
5
5
12
0
3
4
50
os
os
os
os
os
os
os
3
4
33.3
72.9
os
os
MHz
66.6
83.3
100.0
4-241
3
4
os
os
MHz
25
25
os
os
•
11)
C
..J
a..
PRELIMINARY
CY7C361
Switching Waveforms
Clock Doubler Inactive (Virgin State).
Nonregistered Input (VIrgin State - Cl,CO
EXTERNAL (INPU1) CLOCK
NONREGISTERED INPUT
,
= 0,0).
~
'\.
1--1$
twL
tp-
I"""twH
-
'\.
"
]I:
MEALY INPUT
]I:
leo
-II
leo
-I
11'
AN'{Po - P5
i--IoHAN'{
l.-
tSO.,
OTHER Po - P5
I---
tcM
tpO (MAX) -
MEALY OUTPUT A
tpO
1-+
(MIN)
i--IoH -
MEALY OUTPUT B
tSM
-I
-
tsM
I--
i
f-tcEA
OUTPUT So -
1
•
leeR
B:J
0361-17
Clock Doubler Enabled (CO = 1)
Nonregistered Input (V'1l'gin State - Cl,CO = 0,0)
tOWL
EXTERNAL (INPU1) CLOCK
NONREGISTERED INPUT
"
/
.,--Is -
-r-: toWH _~
'L.
r
r
top
-,,
'L.
/
I
MEALY INPUT
~Ieo~tc°l
x:
ANYPo- P5
I---
IoH
f-...
ANY OTHER Po - P5
XXX
"IX ~tsoXX
I---- t c M - t p o - I - - tcM---...
MEALY OUTPUT A
XXX
-I
MEALY OUTPUT B
IoH I-I-tSM
XXX
I-OUTPUT So
- B:J
xx
xx
:x:
'XX
I---
tcER ---I
-tcEA
I
~
.. ~
0361-18
4-242
PRELIMINARY
CY7C361
Switching Waveforms (continued)
Clock Doubler Inactive (Virgin State).
Single-Registered Input (Cl,CO 0,1).
=
1p~
,.
lIo.
EXTERNAL (INPUT) CLOCK
tlH _I
L tiS
REGISTERED INPUT
~tWL" I--
~
tWH
I
•
MEALY INPUT
leo
teo
AN'(
I /)
C
Po - P5
I+--
toH-
Iso
11-
isM
--I
...J
Q.
Iso., -
ANY OTHER Po - P5
leM
tpo(MAX)-
MEALY OUTPUT A
!Po
(MIN) ~
isM
...
..j
MEALY OUTPUT B
OUTPUT Bo -
.-
Ba
leM
~
-I
leEA
leER
-I
-'
i+- tSM
(
c361-19
=
Clock Doubler Enabled (CO 1)
Single-Registered Input (Cl,CO = 0,1)
EXTERNAL (INPUT) CLOCK
REGISTERED INPUT
"
"I
/
tiS
X
I+--
tco
ANY Po - P5
f4-
toH -
ANY OTHER Po - P5
r---
-tpo-
XXX
r.
/
-1 -
t co - - - ,
.X
XXI
.I
XX
r-- H"'tso
I--leMleM-J
.XX
~ toH- I-
MEALY OUTPUT B
"
X
MEALY INPUT
MEALY OUTPUT A
tOWH ~
-lop
tlH
I
-t.
,
tOWL
....1
tSM
XXX
XX
X
~ tSM
XX
~leER
_ _ _ _ _ _ _§ t c E A = k
OUTPUT Bo -
Ba
c361-20
4-243
PRELIMINARY
CY7C361
Switching Waveforms (continued)
Clock Doubler Inactive (Virgin State)
Double-Registered Input (ClI C. = 1,x)
EXTERNAL (INPUT) CLOCK
2-REGISTERED INPUT ==~~=k:===~::)c:==±====::l==========:
MEALYINPUT:::::~::::::::::1r::::::::::~::::::::t;::::::~~:::::::;r=
Ico
ANYPo- Ps ::::::j::::::::::~::::::=::~.:::::::tco~~~~~;aC!XXXXggggk:
-toH
ANYOTHERPO-PS===~=====~=========~ca~xxxt=xxggcccdc::
1 - - - - IcM ---.-1.1
MEALY OUTPUT A:::~=t=:pCCl~DJff=========:::::l~~~~~
(M!PoIN)
tsM ....
MEALY OUTPUT B:====:D~XXDltt====~;:===::J~~~~~~~Ugga:=
OUTPUT So - Sa :============~I=.======~Ic~':=R=-=-::=-=-=-=tcj5Lj
-.
______·Jlt====:::
0361>21
4-244
PRELIMINARY
CY7C361
CY7C361 Block Diagram (Upper Half)
I
•
§
tn
C
~
!
..J
a..
=
~~
~ n I;
.r;:-;
nnn
~; ~i I; ~a ~1 §t ~~
g~ ~i ~i §i
liE 11:; !E 2E II:; it:; II::!E: It:; iJ:; iJ:; iE 11:; It:; II:; ~
Ii
il
~~~
,'0. 11..
l~
~
1
[-J
,
-
~
~
=
K
~
~
!
~
~
~
~~i
I:-~
C!1~
..!..~~
.~N
4-245
PRELIMINARY
CY7C361
CY7C361 Block Diagram (Lower Half)
lit
..
.
iii
;;
RZ
~ ~
~ ~
~
L
~
2
;
~
:
=
-G.
-II
w
5'
~~
="
;t
~~
:~
. ;.
;i!!.
,~
:6
!l§.
l~
·
·
·
N
4-246
-§~
=~
=G
&2
=&..-
:~
PRELIMINARY
-=-,
_'=CYPRESS
SEMlCOND\JC1DR
CY7C361
Ordering Information
ICCmA
fMAXMHz
200
125.0
150
200
150
200
150
125.0
100.0
100.0
100.0
100.0
Ordering Code
CY7C361-125HC
83.3
J64
CY7C361-125PC
P21
CY7C361-125WC
CY7C361L-125HC
W22
H64
CY7C361L-125JC
J64
CY7C361L-125PC
P21
CY7C361L-125WC
W22
CY7C361-100HC
H64
CY7C361-100JC
J64
CY7C361-100PC
P21
CY7C361-100WC
W22
CY7C361L-100HC
H64
CY7C361L-100JC
J64
CY7C361L-100PC
P21
CY7C361L-100WC
CY7C361-100DMB
W22
D22
CY7C361-100HMB
H64
CY7C361-100LMB
CY7C361-100QMB
L64
Q64
CY7C361-100WMB
W22
CY7C361L-100DMB
D22
CY7C361L-100HMB
H64
CY7C361L-100LMB
L64
Q64
CY7C361L-100WMB
CY7C361L-83HC
CY7C361L-83JC
150
66.6
H64
CY7C361-125JC
CY7C361L-100QMB
150
Package 1Ype
Commercial
II
Commercial
H64
Q.
Commercial
Military
Military
Commercial
J64
P21
CY7C361L- 83WC
W22
CY7C361L- 83DMB
CY7C361L- 83HMB
D22
CY7C361L-83LMB
CY7C361L-83QMB
L64
Q64
CY7C361L-83WMB
W22
CY7C361L-66HC
H64
J64
Military
H64
CY7C361L-66PC
P21
CY7C361L-66WC
W22
CY7C361L-66DMB
D22
CY7C361L-66HMB
H64
CY7C361L-66LMB
CY7C361L-66QMB
L64
Q64
CY7C361L-66WMB
W22
4-247
II)
C
..J
W22
CY7C361L-83PC
CY7C361L-66JC
Operating Range
Commercial
Commercial
Military
PRELIMINARY
MILITARY SPECIFICATIONS
, Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VJH
1,2,3
VIL
1,2,3
IIX
1,2,3
IOZ
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
teo
tCM
toH
tIs
tJH
ts
tH
tso
tSM
Document #: 38-00106-B
4-248
CY7C361
PLD610
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Multipurpose BiCMOS PLD
- Array feedback from I/O pin or
Features
register
- Product term controlled asynchronous reset
- Programmable output polarity
control
• Function, pin, and JEDEC compatible
with EP600, EP610, EP630, 8SC060,
and PALCE610 PIDs
• Very high performance
-tPD = IOns
• 161/0 macrocells, each having:
- Choice of combinatorial or registered output
- Registers programmable to T-type
andD-type
- Emulation ofRS and JK Dip-flops
- Array feedback from I/O pin or
register
• 160 product terms
• Available in 24-pin, 300-mil PDIP and
cerDIP, and 28-pin, J-leaded chip carriers, PLCCs, and LCCs
• Advanced BiCMOS technology
• Programmable security bit
Functional Description
The PID610 is a 24-pio, multipurpose,
high-performancePLD with 16 I/O macrocells, 4 dedicated ioputs, and 2 global
clockioputs.
CLKI provides the synchronous clock ioput for one bank of eight macrocells, and
CLK2 provides the synchronous clock ioput for the other bank of eightmacrocells.
Output enable and selection of asynchronous or synchronous clock source are controlled with one dedicated product term
per macrocell. An asynchronous reset
product term is provided for each rnacrocell.
Logic Block Diagram
Vss
vo
1/0
vo
1/0
vo
vo
1/0
vo
coo
110
110
110
vo
vo
1/0
110
VO
CLK1
Vee
0610-1
Selection Guide
ICC1(mA)
tpD(ns)
ts (ns)
teo (ns)
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
PLD610-10
130
10
7
7
4-249
PID610-12
130
170
12
12
8
8
9
9
PLD610-1S
130
170
15
15
9
10
10
10
PID610-2S
130
170
25
25
20
20
15
15
II
en
C
..J
11.
PRELIMINARY
Functional Description (continued)
Each macrocell also has a register that can be programmed to be a
D-type or T-type register. Other programmable options include
output polarity, registered or combinatorial output, feedback to
the array from the I/O pin or from the register output, and whether
the dedicated product term controls the output enable or the register clock.
Maximum Ratings
(Above which the useful life maybe impaired. Foruser guidelines,
not tested.)
Storage Thmperature .........•....•.. - 65° C to + 150° C
Ambient Thmperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ..... . . . . . . . . . . . . . . .. - 0.5V to Vee Max.
DC Input Voltage ................ - O.5V to (Vee + 0.5V)
DC Input Current. . . . . . . . . . . . . . . . . .. - 30 rnA to + 5 rnA
(except during programming)
PLD610
The PID610 is available in a wide variety of packages including
24-pin, 300-mil plastic and ceramic DIPs, 2S-pin, square J-Ieaded,
ceramic chip carriers, 2S-pin PLCCs, and 2S-pin ceramic LCCs.
DC Program Voltage .............................. 9.5V
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-S83, Method 3015)
Operating Range
Range
Commercial
Military[!]
Electrical Characteristics Over the Operating Range
Parameter
Description
Ambient
Temperature
O°Cto + 70°C
Vcc
5V±5%
- 55°C to + 125°C
5V ± 10%
Min.
Test Condi tions
VOH
Output mGH Voltage
Vee = Min.,
VIN = VIH or VIL
IOH = -4mA
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIH or VIL
IOL= SmA
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for All Inputs[2]
VIL
Input WW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs[2]
Max.
Units
2.4
V
0.5
2.0
V
V
O.S
V
/lA
Ilx
Input Leakage Current
VSSS VINS Vee, Vee = Max.
-250
50
Ioz
Output Leakage Current
Vee = Max., VssS VOUTS Vee
-100
100
/lA
Ise
Output Short Circuit Current
Vee = Max., VOUT = 0.5V[3,6]
-30
-130
rnA
Ieci
Power Supply
Current Standbyl4]
Vee = Max., VIH = GND, Outputs Open
130
rnA
150
rnA
Iecz
Power Suppl;{ Current
at Frequency 5,6]
Com'II-1O
1Vee = Max., Outputs Disabled (in High Z
State), Device Operating at fMNa
12
Mil
170
Com'II-10
130
rnA
170
rnA
1- 12
Mil
190
Capacitance[6]
Parameters
CIN
CoUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0V at f = 1 MHz
VOUT = 2.0Vatf = 1 MHz
Notes:
1. TA is the "instant on" case temperature.
2. Minimum DC input voltage is -O.3Y. During transitions, the inputs
may undershoot to - 2.0V for periods less than 20 ns.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by ground degradation.
4. Some of the devices compatible with Cypress's PLD610 have both a
slow power-down mode and a faster turbo mode. Cypress's PAL6lO,
however, only operates in a vel}' fast turbo mode. In order to maintain
full JEDEC compalibility,the Cypress PLD6lO has two fuses that correspond to the turbo bits in other devices. Please note that the opera-
5.
6.
4-250
Max.
10
10
Units
pF
pF
tion of the device is entirely independent of these "dummy" fuses. The
PLD610 operates at very high speed regardless of whether the turbo
bits are programmed (TURBO = ON) or unprogrammed (TURBO
= OFF).
Thsted with device programmed as a 16-hit counter.
Thsted initially and after any design or process changes that may affect
these parameters.
*!jil~
PRELIMINARY
PLD610
AC Test Loads and Waveforms
+5V
~R14480
~-"pFt t"'ov
I
OUTPUTD
C
R = 1580
1r
=35PFT
VTH
OV
0""""
= 1.77V
C
= 5 pF
f
R = 1580
OV
(a) Nonnal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
0610-7
OV
(c) Three-State Delay Load (Load 2)
0610-8
0610-9
ALL INPUT PULSES
.OV~1::'
_~s
GND
I-
.s.3 ns
0610-2
(d)
Parameter
Vx
tER(-)
1.5V
tER(+)
2.6V
tEA(+)
VTH
tEA(-)
VTH
Output Waveform-Measurement Level
VOH O.5V
: r
VOL
O.5V:
Vx
O.5V:
Vx
O.5V
:
Vx
~
~
0610 3
Vx
0610-'
VOH
D610-5
I:
VOL
0610-6
Switching Waveform
R~~Mig~~'6 ---"T'7'\
FEEDBACK
SYNCHRONOUS ---~
PRESET
.....~I4--eoI
SYNCHRONOUS
OR
ASYNCHRONOUS
CLOCK INPUT
------"1
ASYNCHRONOUS -------~~------_r-ll
RESET
tEA
REGISTERED
OUTPUTS ______________
-+>I..¥
COMBINATORIAL
OUTPUTS
-------------nf'7\..
~---------......;;;.;....~>'\~--+E2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .......... '" . . . . . .. . . . . . . . . >200rnA
Storage Thmperature ................. - 65° C to + 150° C
Ambient Temperaturewith
PowerApplied....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 16 to Pin 8) ........................ - 0.5Vto+7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current, into Outputs (Low) ..... . . . . . . . . . .. 20 rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Militaryl2]
Electrical Characteristics Over the Operating Rangel3]
Parameters
Description
O°Cto +70°C
- 55°C to
+125°C
Thst Conditions
Vss
VDD VGG[l]
NC
5V±1O% GND
5V±10% GND
Min.
= Min., IOH = - 0.3 rnA
Vss = Min., IOL = 1.6 rnA
Max.
NC
Units
VOH
Output HIGH Voltage
2.4
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
2.0
Vss
V
- 3.0
0.8
V
Vss
VlL
Input LOW Voltage
IIX
Input LeakageCurrent
VOO~VI~VSS
los
Output Short Circuit Current[4]
Vss = Max., VOUT
100
Power Supply Current
-10
= Voo
Vss = Max., lOUT = 0 rnA
I Commercial
I Military
V
+10
!1A
- 90
rnA
45
rnA
60
rnA
0
VooCurrent
100
V
0.4
Capacitance [5]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CoUT
Thst Conditions
TA = 25°C, f
Vss = 5.0V
Notes:
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
Units
Max.
7
= 1 MHz,
pF
pF
10
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
Rl 2.42 1m
OUTP~~3=t
30 PF.l
INCLUDING
JIG AND
SCOPE
-
ALL INPUT PULSES
3.0V---90%
R2
3.28 kn
GND
3341-5
334HI
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
105 kn
o-----vw---o
2.08V
3341-4
5-2
-====-:~
.
CY3341
IE CYPRESS
SEMlCONDUCTOR
~_,
Switching Characteristics
Parameters
Over the Operating Rangel3, 6]
Description
Thst
Conditions
3341-2
3341
Min.
Note 7
Max.
Min.
1.2
Max.
Units
2
MHz
fMAX
Operating Frequency
tpHSI
SI HIGH Time
80
80
ns
tpLSI
SILOWTime
80
80
ns
ns
too
Data Set-Up to SI
0
0
tHSI
Data Hold from SI
200
100
tIR+
Delay, SI HIGH to IR LOW
20
350
20
160
ns
tIR-
Delay, SI LOW to IR HIGH
20
450
20
200
ns
tpHSO
SO HIGH Time
80
80
tpLSO
SO LOW Time
80
80
tOR+
Delay, SO HIGH to OR LOW
20
370
20
160
ns
tOR-
Delay, SO LOW to OR HIGH
20
450
20
200
ns
tOA
Data Set-Up to OR HIGH
0
0
ns
tOH
Data Hold from OR LOW
75
20
ns
tBT
Bubble Througb Time
tMRW
MRPulse Width
tOSI
MRHIGH to SI HIGH
tOOR
MRLOWtoORLOW
400
200
ns
tDiR
MRLOWtoIRHIGH
400
200
ns
1000
Notes:
6. Thst conditioos assume signal transition time of 10 ns or less, timing
reference levels of l.5V and output loading of the specified IOI)IOH
and 30-pF load capacitance.
7.
Switching Waveforms
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA INPUT
5-3
ns
ns
ns
500
ns
400
200
ns
30
30
ns
l/fMAX > tPHS! + tIR-, l/fMAX > lNIso
+ tOR-.
•
~
~~CYPRESS
~I
CY3341
SEMICONDUC'TOR
Switching Waveforms (Continued)
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUTPUT
3341-8
Master Reset Timing Diagram
-IMAW--
MASTER RESET
~
"'I
lOlA
INPUT READY
/1(
IOOA
~~
OUTPUT READY
""1..1 - - - - - IOSI
------""'1~
SHIFT IN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.
~/-----------
DATAOUTPUT _ _ _ _ _ _ _ _ _"'_~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
3341-7
Ordering Information
CY334IPC
Package
1YPe
PI
CY334IDC
D2
CY334IDMB
D2
Ordering Code
(1.2 MHz)
Operating
Range
CY334I-2PC
Package
1Ype
PI
CY334I-2DC
D2
CY334I-2DMB
D2
Ordering Code
(2 MHz)
Commercial
Military
5-4
Operating
Range
Commercial
Military
L~PRFSS
""SJ!!!!II!"
CY3341
SEMlCONDUClDR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIR
VILMax.
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IJX
100
•
Switching Characteristics
Parameters
Subgroups
fMAX
7,8,9, 10, 11
tpHSI
7, 8, 9, 10, 11
tpLSI
7,8,9, 10, 11
too
tIR+
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tIR-
7,8,9, 10, 11
tPHSO
tpLSO
7, 8, 9, 10, 11
7, 8, 9, 10, 11
toR+
7, 8, 9, 10, 11
tOR-
7,8,9, 10, 11
tOA
7, 8, 9, 10, 11
tOH
7,8,9, 10, 11
tHSI
tBT
7,8,9, 10, 11
tMRW
7, 8, 9, 10, 11
tOS1
7, 8, 9, 10, 11
tOOR
7, 8, 9, 10, 11
tOIR
7,8,9, 10, 11
Document#:
38-00011-B
5-5
CY7C401/CY7C403
CY7C402/CY7C404
CYPRESS
SEMICONDUCTOR
Cascadeable 64 X 4 FIFO and
64x5 FIFO
Features
Functional Description
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High-speed lirst-in first-out memory
The CY7C401 and CY7C403 are asynchronousfirst-in first -out memories (FlFOs)
organized as 64 four-bit words. The
CY7C402 and CY7C404 are similar FIFOs organized as 64 five-bit words. Both
the CY7C403 and CY7C404 have an output enable (OE) function.
The devices accept 4- or 5-bit words at the
data input (Dlo - DIn) under the control
of the shift in (SI) input. The stored words
stackup at the output (DOo - DOn) in the
order they were entered. A read command
on the shift out (SO) input causes the next
to last word to move to the output and all
data shifts down once in the stack. The input ready (IR) signal acts as a flag to indicate when the input is ready to accept new
data (HIGH), to indicate when the FIFO is
full (LOW), and to provide a signal for cascading. The output ready (OR) signal is a
flag to indicate the output contains valid
data (HIGH), to indicate the FIFO is
(FIFO)
• Processed with high-speed CMOS for
optimum speed/power
• 25-MHz data rates
• 50-ns bubble-through time-25 MHz
• Expandable in word width and/or
length
• 5-volt power supply ±10% tolerance,
both commercial and military
• Independent asynchronous inputs
and outputs
• TTL-compatible interface
• Output enable function available on
CY7C403 and CY7C404
• Capable of withstanding greater than
2001V electrostatic discharge
• Pin compatible with MMI
67401A/67402A
Logic Block Diagram
empty (LOW), and to provide a signal for
cascading.
Parallel expansion for wider words is accomplished by logically ANDing the IR
and OR signals to form composite signals.
Serial expansion is accomplished by tying
the data inputs of one device to the data
outputs of the previous device. The IR pin
ofthe receiving device is connected to the
SO pin of the sending device, and the OR
pin of the sending device is connected to
the SI pin of the receiving device.
Reading and writing operations are completelyasynchronous, allowing the FIFO
to be used as a buffer between two digital
machinesofwidelydifferingoperatingfrequencies. The 25-MHz operation makes
these FIFOs ideal for high-speed communicationand controller applications.
Pin Configurations
DIP
DIP
(CYlC401) NC
(CYlC403) OE
IR
SI
IR
WRITE POINTER
WRITE MULTIPLEXER
(CY7C402) NC
vee (CY7C404) OE
so
IR
OR
1
010
01,
OE
012
010
01,
DO,
DO.
Dis
003
MR
GND
MEMORY
ARRAY
013
C401-2
00,
DO.
(01 4)
7
GND "1.::_ _ _..r
000
01.
2
010
011
012
013
014
000
6
(004)
LCC
~g;~~~
81
SO
010
01,
01.
OR
NC
C401-1
MR
IQ 0
READ MULTIPLEXER
MR
000
001
002
003
004
C401-4
LCC
DO,
READ POINTER
Vee
SO
OR
1
4
5
6
7
8
3 2 111 2019
18
CYlC401 17
NC
OR
CY7C403
00,
1~
000
14
910111213
DO.
81
0 10
01,
01.
013
•
5
6
7
8
3 2 111 2019
18
17
CYlC402 16
CYlC404 15
1.
910111213
OR
000
00,
DO.
003
a~l~g~
B~ 1~g'\1
C401-3
C401-5
Selection Guide
7C401/2-5
7C40X-10
7C40X-15
5
75
10
15
25
75
90
75
90
75
90
MaximumAccess Time (ns)
MaximumOperating
Current(mA)
I Commercial
I
Military
5-6
7C40X-25
CY7C401/CY7C403
CY7C402/CY7C404
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Vol~e .••.................... > 2001V
(per MIL-STD-883, ethod 3015)
Latch-UpCurrent ..........•..•..•.....•.... > 200 rnA
Storage Thmperature ................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ...................... -55°Cto+125°C
Supply Voltage to Ground Potential. . . . . .. - O.SV to + 7.0V
DC Voltage Applied to Outputs
in HighZState ........................ -O.SVto +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . • . . • . . • • . • . . . . . .. 1.0W
Output Current, into Outputs (LOW) ....•......... 20 rnA
Operating Range
Ambient
Temperature
Range
Commercial
Military!l]
O°Cto +70°C
Vee
5V:l:1O%
- 55°C to +125°C
5V:l:1O%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)!2]
7C40X-I0, 15, 25
Parameters
Description
VOH
Output HIGH Voltage
Test Conditions
Min.
= Min., IOH = - 4.0 mA
Vee = Min., IOL = 8.0 rnA
Units
Max.
24
Vee
V
VOL
Output LOW Voltage
0.4
V
VIH
Input HIGH Voltage
20
6.0
V
VIL
Input LOW Voltage
- 3.0
0.8
V
IIX
Input Leakage Current
GNDS VI$.. Vee
-10
+10
f1A
VCD!3]
Input Diode Clamp Voltage£3]
Ioz
Output Leakage Current
GNDS VOUT$.. Vee, Vee = 5.5V
Output Disabled (CY7C403 and CY7C404)
- 50
+50
f1A
los
Output Short Circuit Currentl4]
- 90
rnA
lee
Power Supply Current
= Max., VOUT = GND
Vee = Max., lOUT = 0 rnA I Commercial
75
mA
90
mA
Vee
I Military
Capacitance!S]
Parameters
Description
Input capacitance
Output Capacitance
CIN
CoUT
Test Conditions
TA = 25°C, f
Vee = 4.5V
Notes:
1. TA is the (~instant on" case temperature.
2. See the last page ofthis specification for Group Asubgroup testing information.
3. The CMOS process does not provide a clamp diode. However, the
FIFO is insensitive to - 3V de input levels and - SV undershoot pulses
ofless than 10 OS (measured at 50% output).
AC Test Loads and Waveforms
Rl 437.0.
OUTP~~ ~
30PFI
INCLUDING
JIG AND
SCOPE
-
272.0.
_
-
5f1
5PFI
INCLUDING
JIG AND
SCOPE
(a)
.Y.
167.0.
pF
pF
7
ALL INPUT PULSES
90%
R2
272.0.
_
-
-
(b)
C40HI
THEVENIN EQUIVALENT
OUTPUT 0
Units
5
3.0V ---I.,...-----~
I
Equivalent to:
Max.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
Rl 437.0.
OUTP~~
R2
4.
5.
= 1 MHz,
01.73V
C401·B
5-7
GND
.s.5ns
C40H
•
CY7C401/CY7C403
CY7C402/CY7C404
=;: !~PRES'3
-=-
F SEMICONDUCTOR
Switching Characteristics Over the Operating Range[3.6]
Parameters
Description
7C401-5
7C402-5
Thst
Conditions
7C40X-IO
Min. Max. Min.
Note 8
7C40X-15
Max. Min.
7C40X-25[7]
Min.
15
10
5
Max.
Max.
Units
25
MHz
fO
Operating Frequency
tpHSI
SI lllGH Time
20
20
20
11
us
tpLSI
SOWWTime
45
30
25
20
us
tSSI
Data Set-Up to SI
Note 9
0
0
0
0
us
tHSI
Data Hold from SI
Note 9
60
40
30
20
ns
tOUR
Delay, SI lllGH to IR WW
tOHIR
Delay, SI WW to IR lllGH
tpHSO
SO lllGH Time
20
20
20
11
tpLSO
SOWWTime
45
25
25
20
tOLOR
Delay, SO lllGH to OR WW
75
40
35
19/21
ns
tOHOR
Delay, SO WW to OR lllGH
80
55
40
34/37
ns
tSOR
Data Set-Up to OR lllGH
0
0
0
0
tHSO
Data Hold from SO WW
5
5
5
5
tBT
Bubble-Through Time
75
40
35
21/22
ns
75
45
40
28/30
ns
200
10
95
10
65
10
ns
ns
ns
ns
50/60
ns
tSIR
Data Set-Up to IR
Note 10
5
5
5
5
tHlR
Data Hold from IR
Note 10
30
30
30
20
ns
tplR
Input Ready Pulse HIGH
20
20
20
15
ns
tpOR
Output Ready Pulse lllGH
20
20
20
15
ns
tpMR
MR Pulse Width
40
30
25
25
ns
toS!
MR lllGH to SI lllGH
40
35
25
10
tOOR
MR WW to OR WW
tDlR
MR WW to IR lllGH
tLZMR
MR WW to Output WW
tOOE
Output Valid from OE WW
tHZOE
Output High Z from OE lllGH
ns
ns
85
40
35
35
us
us
85
40
35
35
Note 11
50
40
35
25
us
35
30
20
ns
Note 12
-
30
25
15
us
Notes:
6. Thst conditions assume signal transition time of 5 nsor less. timing reference levels of l.SV and output loading of the specified 10lJIoH and
30-pF load capacitance, as in part (a) of AC Thst Loads and Waveforms.
7. Commercial/Military
8. lifo> tpHSI + tOHlRo lifo> tpHSO + tOHOR
9. tSSI and tHSI apply when memory is not full.
10. tSIR and tHlR apply when memory is full. S1 is high and minimum
bubble-through (tBT) conditions exist.
11. AIldataoutputswillbeatLOWlevelafterresetgoesHIGHuntildata
is entered into the FIFO.
12. HIGH-Z transitions are referenced to the steady-state VOH -500 m V
andVoL +SOOmVlevelson the output. tHzoEistestedwithS-pFload
capacitance as in part (b) of AC Thst Loads and Waveforms.
5-8
CY7C401/CY7C403
CY7C402/CY7C404
-=: :;~PRF.SS
~,
SEMICONDUCTOR
Operational Description
Concept
Unlike traditional FIFOs, these devices are designed using a dualport memoI)', read and write pointer, and control logic. The read
and write pointers are incremented by the SO and SI respectively.
The availabilityof an empty space to shift in data is indicated by the
IR signal, while the presence of data at the output is indicated by
the OR signa\. The conventional concept of bubble-through is absent. Instead, the delay for input data to appear at the output is the
time required to move a pointer and propagate an OR signal. The
output enable ~ signal provides the capability to OR tie multiple FIFOs together on a common bus.
There are several implementation techniques for managing the
window so that all SO signals are recognized:
1. The first involves delaying SO operation such that it does not
occur in the critical window. This can be accomplished by causingafixeddelayof40ns"initiatedbytheSIsignalonlywhenthe
FIFO is empty" to inhibit or gate the SO activity. However, this
requires that the SO operation be at least temporarily synchronized with the input SI operation. In synchronous applications
this may well be possible and a valid solution.
2. Anothersolutionnotuncommoninsynchronousapplicationsis
to only begin shifting data out of the FIFO when it is more than
halfful\. ThisisacommonmethodofFIFO application, asearJier FIFOs could not be operated at maximum frequency when
near full or empty. Although Cypress FIFOs do not have this
limitation, any system designed in this mannerwill not encounter the window condition described above.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (MR)
signal. This causes the FIFO to enter an empty condition signified
by the OR signal being WW at the same time the IR signal is
HIGH. In this condition, the data outputs (DOo - DOn) will be in
aWWstate.
Shifting Data In
Data is shifted in on the rising edge of the SI signal. This loads input data into the first word location of the FIFO. On the falling
edge of the SI signal, the write pointer is moved to the next word
position and the IR signal goes HIGH, indicating the readiness to
accept new data. If the FIFO is full, the IR will remain WW until
a word of data is shifted out.
Shifting Data Out
Data is shifted out of the FIFO on the falling edge ofthe SO signal.
This causes the internal read pointer to be advanced to the next
word location. If data is present, valid data will appear on the outputs and the OR signal will go HIGH. Ifdata is not present, the OR
signal will stay WW indicating the FIFO is empty. Upon the rising
edge of SO, the OR signal goes Ww. The data outputs of the
FIFO should be sampled with edge-sensitive type D flip-flops (or
equivalent), using the SO signal as the clock input to the flip-flop.
Bubble-Through
Tho bubble-through conditions exist. The frrst is when the device is
empty. After a word is shifted into an empty device, the data propagates to the output. After a delay, the OR flag goes IDGH, indicating valid data at the output.
3. The window may also be managed by not allowing the first SO
signal to occur until the windowinquestion haspassed. This can
be accomplished by delaying the SO 40 ns from the rising edge
of the initial ORsigna\. This however involves the requirement
that this only occurs on the first occurrence ofdata being loaded
into the FIFO from an empty condition and therefore requires
the knowledge of IR and SI conditions as well as SO.
4. Handshaking with the OR signal is a third method of avoiding
the window in question. With this technique the rising edge of
SO,orthefactthatSO signal is IDGH,will cause the OR signal
to go Ww. The SO signal is not taken LOW again, advancing
the internal pointer to the next data, until the OR signal goes
Ww. This ensures that the SO pulse that is initiated in the window will be automatically extended long enough to be recognized.
5. There remains thedecision as towhatsignal will be used to latch
the data from the output of the FIFO into the receiving source.
The leading edge of the SO signal is most appropriate because
datais guaranteed to be stable prior to and after the SO leading
edge for each FIFO. This is asolutionfor any numberofFIFOs
in parallel.
Any of the above solutions will ensure the correct operation of a
Cypress FIFO at 25 MHz. The specific implementation is left to
the designer and is dependent on the specific application needs.
The second bubble-through condition occurs when the device is
full. Shifting data out creates an empty location that propagates to
the input. After a delay, the IR flag goes IDGH. If the SI signal is
HIGH at this time, data on the input will be shifted in.
Application of the 7C403 -25I7C404-25 at 25 MHz
Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs
requires knowledge of characteristics that are not easily specified
in a datasheet, but which are necessaI)'for reliable operation under
all conditions, so we will specify them here.
When an empty FIFO is filled with initial information at maximum
"shift in" SI frequency, followed by immediate shifting out of the
data also at maximum "shift out" SO frequency, the designer must
be aware of a window of time which follows the initial rising edge of
the OR signal, during which time the SO signal is not recognized.
This condition exists onlyat high -speed operation where more than
one SO may be generated inside the prohibited window. This condition does not inhibit the operation of the FIFO at full-frequency
operation, but rather delays the full 25-MHz operation until after
the window has passed.
5-9
•
CY7C401/CY7C403
CY7C402/CY7C404
Switching Waveforms
Data In TIming Diagram
SHIFT IN
INPUT READY
DATA IN
C401-9
Data Out TIming Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
0401-10
1
Bubble Througb, Data Out To Data In Diagram
SHIFTOUT~
SHIFT IN
~-------1r-------------------------~
..
BT
~~
INPUT READY
i---
DATA IN
J
tplR
~(
~(
-
\.
!sIR
tHIR
C4D1-11
5-10
CY7C401/CY7C403
CY7C402/CY7C404
~:~~
""'E!!!fiii' SEMICONDUCTOR
Switching Waveforms (continued)
Bubble Through, Data In 10 Data Out Diagram
SHIFT IN
/
_--J
....- - - tBT - - - - " - -
OUTPUT READY
~------
_ _ _ _ _ _ _ _ _ _ _ ~ tsOR
DATA OUT
------------------
•
en
C401-12
oLL
~
Master Reset Timing Diagram
MASTER RESET
I----~k..
tpMR - -
1£
tolR
INPUT READY
;;
toOR
~
OUTPUT READY
toSI
SHIFT IN
"",1
..- - IuMR
DATA OUT
}
---~-I
------------------~----------------------0401-13
Output Enable Timing Diagram
~
OUTpUt ENABLE
~
~~E ~-----------_
_________
tH_zOE
DATA OUT _ _ _ _ _ _ _ _ _
NOTE 10
0401-14
5-11
CY7C401/CY7C403
CY7C402/CY7C404
g ;riPRFSS
_ , SEMICONDIJC1OR
1Ypical DC and AC Characteristics
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
NORMAUZED SUPPLY CURRENT
rn~.~sUP~Pr~=Y~V~O=~T~A=G~E~~__~
vs. AMBIENT TEMPERATURE
1
60
ffi
50
o
a
40
~
w
~
1.2
1.4
jll.0 1---+----1---jo~~
w
~
o
0.81----+--'7"-'1----+-----1
"-
30
:::l
tr
Z
Vee = 5.5V
VIN = 5.0V
0.0 L -_ _ _....L._ _ _ _--'
125
-55
25
0.4 L-_-":-_---''-_-L-_--'
4.0
4.5
6.0
SUPPLY VOLTAGE
M
1.2
5w
1.1
If
@ 1.0
N
0.9
-
~
ffi
5w
If
f.--
5.5
SUPPLY VOLTAGE
~
~
0.6
-55
6.0
M
o
::<:
~
1.6
/
!ill.4
If
/
01.3
;;! 1.2
::;:
tr
01.1
z
1.0
/
o
5
40
0
,;'
w
N
:::J
J
20
o/
/
1.0
OUTPUT VOLTAGE
M
..IV
0.9
tr
/
0.8
0
z
./
0.7
0.0
600
Vee = 5.0V
TA = 25·C
I
2.0
3.0
4.0
/
c(
::;:
400
~
"".
17
0.0
j l 1.0
/
200
4.0
NORMALIZED Icc
vs. FREQUENCY
-
V
'"
M
1.1
/
w
60
§
./
80
~
125
25
~CALFREQUENCYCHANGE
:::l
3.0
~
AMBIENT TEMPERATURE (0C)
~
ffi 1.5
2.0
100
:::l
vs. OUTPUT LOADING
~
1.0
z
Z
5.0
'"
Vee = 5.0V
TA = 25·C
0
0.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
tr
1.2
~
:;( 140
E
;:- 120
~
15 0.8
~ 0.8
4.5
10
"
OUTPUT VOLTAGE
1.4
o
~ 1.0
tr
0.7
4.0
~
o
1.6
..-./"'"
20
NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE
1.3
°ffi>-
g
AMBIENT TEMPERATURE (0C)
NORMALIZED FREQUENCY
n. SUPPLY VOLTAGE
~
i\..
tr
tr
800 1000
CAPACITANCE (pF)
o
5
V
10
15
20
25
30
5-12
35
C401-15
FREQUENCY (MHz)
CY7C401/CY7C403
CY7C402/CY7C404
g;i~
~,~
FIFO Expansion[13,14,IS, 16, 17]
128 x 4 Application[18]
SHIFT IN
INPUT READY
OR
SO
000
001
002
003
MTAW{
51
IR
010
011
012
013
lm
lmo--------4~------------~
OR
SO
000
001
00 2
003
OUTPUT READY
SHIFT OUT
} MTA~
C401-16
192 x 12 Application[19]
-COMPOSITE
INPUT READY
rr-"--J--
---
IR
SO
SI
OR
000
01 0
011
001
002
01 2
013 1.im 003
IR
SO
SI
OR
000
010
011
001
002
01 2
013 lm 003
T
r
IR
SO
SI
OR
000
010
011
001
002
012
013 lm003
IR
SO
SI
OR
000
01 0
011
001
002
01 2
013 lm 003
SHIFT IN
-
--
IR
SI
01 0
011
01 2
013 lm
so
OR
000
001
002
003
IR
SI
01 0
Dll
012
013
IR
SI
01 0
011
01 2
013 lm
SO I---<
OR
000
001
002
003
rrrr-
COMPOSITE
OUTPUT READY
L.....r-\
r-L-'
I
so
OR
000
001
00 2
lm003
r
T
SHIFT OUT
rrr-
r
r
T
IR
SO
SI
OR
000
01 0
011
001
002
01 2
013 MFf 003 I--
IR
SI
01 0
011
01 2
013 lm
so I - -
OR
000 I 001 I-002 I-003 I--
r
lm
C401-17
Notes:
13_ When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles
through to the output_ However, OR will remain LOW; indicating data
at the output is not valid_
14_ WhentheoutputdatachangesasaresuitofapulseonSO,theORsignal always goes LOW before there is any change in output data, and
stays LOW until the new data has appeared on the outputs_ Anytime
OR is HIGH, there is valid, stable data on the outputs_
15_ If SO is held HIGH while the memory is empty and a word is written
into the input, thatwordwill ripple through the memory to the output_
OR will go HIGH for one internal cycle (at least toRI.) and then go
back LOW again_ The stored word will remain on the outputs_ If more
words are written into the FIFO, they will line up behind the firstword
and will not appear on the outputs until SO has been brought LOW.
16_ When the master reset is brought LOW; the outputs are cleared to
LOW; m goes HIGH and OR goes LOW. If SI is HIGH when the
master reset goes HIGH, then the data on the inputs will be written
into the memory and m will return to the LOW state until SI is
brought LOW. If SI is LOW when the master reset is ended, then IR
will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
17_ All Cypress FlFOs will cascade with other Cypress FIFOs_ However,
hey may not cascade with pin-compallble FIFOs from other manufac-
turers_
18_ FIFOs can be easily cascaded to any desired depth_ The handshaking
and associated timing between the FIFOs are handled by the inherent
timing of the devices.
19_ FlFOs are expandable in depth and width. However, in forming wider
words two external gates are required to generate composite input and
output ready flags_ This need is due to the variation of delays ofthe FIF08-
5-13
•
CY7C401/CY7C403
CY7C402/CY7C404
Ordering Information
Speed
(ns)
Ordering Code
Package
'JYpe
Operating
Range
Speed
(ns)
10
Package
'JYpe
Operating
Range
CY7C403-100C
D2
Commercial
CY7C403 -iOLC
L61
Ordering Code
5
CY7C401-5PC
P1
Commercial
10
CY7C401-100C
02
Commercial
CY7C401-10LC
L61
CY7C403-10PC
P1
CY7C401-iOPC
P1
CY7C403-100MB
02
CY7C401-100MB
02
CY7C403-10LMB
L61
CY7C401-10LMB
L61
CY7C401-150C
02
CY7C401-15LC
L61
CY7C403-15PC
PI
CY7C401-15PC
P1
CY7C403-150MB
02
Military
CY7C401-150MB
Military
CY7C401-15LMB
02
L61
CY7C403 -15LMB
CY7C403-250C
L61
02
Commercial
CY7C401-250C
D2
Commercial
CY7C403-25LC
L61
CY7C401-25LC
L61
CY7C403 - 25PC
PI
CY7C401-25PC
P1
CY7C403-250MB
02
CY7C401-250MB
02
CY7C403-25LMB
L61
CY7C401-25iMB
L61
15
25
Speed
(ns)
Ordering Code
Military
15
Commercial
25
Military
Package
'JYpe
Operating
Range
Speed
(ns)
CY7C403-150C
02
CY7C403-15LC
L61
Ordering Code
Commercial
CY7C404-iOOC
04
P3
Commercial
CY7C404-iOLC
L61
10
CY7C402-100C
04
L61
Commercial
CY7C402-10LC
CY7C404-10PC
CY7C404-100MB
P3
04
CY7C402-10PC
P3
CY7C404-10LMB
L61
15
25
04
CY7C402-iOLMB
L61
Military
15
CY7C404-150C
04
CY7C404-15LC
L61
CY7C402-150C
04
CY7C404-15PC
P3
CY7C402-15LC
L61
CY7C404-150MB
04
CY7C402-15PC
P3
CY7C404-15LMB
L61
CY7C402-150MB
04
CY7C402-15LMB
L61
Commercial
Military
25
CY7C404-250C
04
CY7C404-25LC
L61
CY7C402-250C
04
CY7C404-25PC
P3
CY7C402-25LC
L61
CY7C404-250MB
04
CY7C402-25PC
P3
CY7C404-25LMB
L61
CY7C402-250MB
04
CY7C402-25LMB
L61
Commercial
Military
5-14
Military
Operating
Range
CY7C402-5PC
CY7C402-iOOMB
Commercial
Package
'tYpe
5
10
Military
Military
Commercial
Military
Commercial
Military
CY7C401/CY7C403
CY7C402/CY7C404
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIH
VILMax.
IIX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
los
ICC
II)
Switching Characteristics
Parameters
Subgroups
fo
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7,8, 9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7,8,9,10,11
7,8, 9, 10, 11
tpHSI
tpLSI
tSSI
tHSI
tOUR
tOHIR
tpHSO
tpLSo
tOWR
tOHOR
tSOR
tHSO
tBT
tSIR
tHiR
tpIR
tPOR
tpMR
tOSI
tOOR
tDlR
tLZMR
tOOE
tHZOE
oII.
u:::
Document #: 38-00040-D
5-'15
CY7C408A
CY7C409A
CYPRESS
SEMICONDUCTOR
Features
• 64 x 8 and 64 x I) fIrSt-in first-out
(FIFO) buffer memory
• 35-MBz shift in and shift out rates
• Almost Full/Almost Empty and Half
Full flags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs
and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO
depth
• SV :1:10% supply
• TIL compatible
• Capable of withstanding greater than
2001V electrostatic discharge voltage
• 300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are
64-word deep by 8- or 9-bit wide first-in
first -out (FIFO) buffer memories. In addition to the industry-standard handshaking
signals, almost full/almost empty (APE)
and half full (HF) flags are provided.
Cascadeable 64 X 8 FIFO
Cascade able 64 X 9 FIFO
AFEisHIGHwhentheFlFOisalmostfulI
or almost empty, otherwise APE is LOW.
HF is HIGH when the FIFO is half full,
otherwiseHF is LOW.
The CY7C408A has an output enable
(OE) function.
The memory accepts 8- or 9-bit parallel
words at its inputs (DIo - DIs) under the
control of the shift in (SI) input when the
input ready (IR) control signal is HIGH.
The data is output, in the same order as it
was stored, on the DOo - DOs output pins
under the control of the shift out (SO) input when the output ready (OR) control
signal is HIGH. If the FIFO is full (IR
LOW), pulses at the Slinput are ignored; if
the FIFO is empty (OR LOW), pulses at
the SO input are ignored.
The IR and OR signals are also used to
connect the FIFOs in parallel to make a
wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implementedby logically ANDing the IR and
OR outputs (respectively) ofthe individual
FlFOs together (Figure 5). The AND operation insures that all of the FIFOs are eitherready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and
thus compensate forvariations in propagation delay times between devices.
Serial expansion (cascading) for deeper
buffer memories is accomplished by connecting the data outputs of the FIFO closest to the data source (upstream device) to
the data inputs of the following (downstream) FIFO (Figure 4). In addition, to insure proper operation, the SO signal ofthe
upstream FIFO must be connected to the
IR output of the downstream FIFO and
the SI signal of the downstream FIFO
must be connected to the OR output of the
upstream FIFO. In this serial expansion
configuration, the IR and OR signals are
used to pass data through the FIFOs.
Reading and writing operations are completelyasynchronous, allowing the FIFO
to be used as a buffer between two digital
machinesofwidelydifferingoperatingfrequencies. The high shift in and shift out
rates of these FlFOs, and their high
throughput rate due to the fast bubblethrough time, which is due to their dualport RAM architecture, make them ideal
for high-speed communications and controllers.
Logic Block Diagram
Pin Configurations
HF
Vee
MR
IR
60
61
OR
AFE
61
WRITE POINTER
AFE
IR
WRITE MULTIPLEXER
HF
DID
DOD
01,
GNO
DO,
GNO
00,
01.
01,
DO,
DO. (7C409A)
01.
01.
01.
DOo
DID
MEMORY
ARRAY
Ol-r
(7C409A) 01.
OE (7C408A)
READ MULTIPLEXER
DO.
DO.
DOo
007
Ol-r
OR
MR
00.
READ POINTER
60
(7C409A) NC
(7C409A) Dis
OE (7C409A)
DO. (7C409A)
C408A-3
C409A-1
(ijg;~~>g~~
43 2
DID
Flag Definitions
01,
GNO
OF
L
L
H
H
AFE
H
L
L
H
01.
01,
0/0
01.
Words Stored
0-8
9 - 31
32-55
56- 64
~11282726
5
6
7
8
9
7C40BA
7C409A
25
24
23
22
21
20
10
19
11
12131415181718
c"'cffi"'gg"'g"'
5-16
OR
DOD
DO,
GNO
DO.
DO.
DO.
C409A-2
CY7C408A
CY7C409A
~
~~PRESS
~, SEMJCONDUCrOR
Selection Guide
7C408A-lS
7C409A-lS
Maximum Shift Rate (MHz)
I Commercial
MaximumOperating
Current (mA)[l]
I Military
7C408A-2S
7C409A-2S
7C40SA-3S
7C409A-3S
15
25
35
115
125
135
140
150
N/A
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Output Current, into Outputs (Low) ... . . . . . . . . . . . .. 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
StorageThmperature ................. -65°Cto+150°C
Ambient Thmperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . .. - 55° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State (7C408A) ................ - O.5Vto +7.0V
DCInputVoltage ...................... - 3.0Vto +7.0V
PowerDissipation ................................ 1.0W
Electrical Characteristics
Parameters
Operating Range
Range
Commercial
Military[2]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±1O%
- 55°C to +l25°C
5V±1O%
Over the Operating Range (Unless Otherwise Noted)[3]
Description
Min.
Thst Conditions
V cc = Min., IOH
= - 4.0 rnA
VCC = Min., IOL = 8.0 rnA
VOH
Output HIGH Voltage
VOL
Output WW Voltage
VIH
Input HIGH Voltage
2.2
VIL
Input WW Voltage
Irx
Input LeakageCurrent
GND.5. VI.5. Vee
los
Output Short Circuit CUrrentL4J
Vee = Max., VOUT = GND
ICCQ
Quiescent Power Supply Current
Vee = Max., lOUT = 0 rnA
VIN.5. VIL VIN ~ VIH
I Commercial
I Military
V
0.4
V
Vcc
0.8
V
- 3.0
-10
+10
!LA
- 90
rnA
V
100
rnA
125
rnA
ICC = ICCQ + 1 mA/MHz X (:CsI + fso)/2
Power Supply Current
Icc
Max. Units
2.4
Capacitance [5]
Parameters
Description
InputCapacitance
Output Capacitance
qN
CoUT
Thst Conditions
= 25°C, f = 1 MHz,
Vee = 4.5V
TA
Notes:
1. Icc = ICCQ + 1 mA/MHz X (fs! + fso)/2
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing in·
formation.
AC Test Loads and Waveforms
R14B2n.
5V5fl
5V~ OUTPUT
CL I 30 pF
256.0.
R2
-
-
5pF
INCLUDING
JIG AND
SCOPE
(a)
J
-
(b)
R2
256.0.
_
GND
10%
5.5n5
-
C408A-4
Equivalent to:
o------wv-----o
pF
pF
ALL INPUT PULSES
3.0V - - - _ - - - - - - , 1
90%
I
THEVENIN EQUIVALENT
167.0.
OUTPUT
1.73V
7
Units
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Testedinitially and after any design or process changes that may affect
these parameters.
R14B2n
OUTPUT
INCLUDING
JIG AND
SCOPE
4.
5.
Max.
5
C408A-6
5-17
C408A-5
•
en
ou..
u::
CY7C408A
CY7C409A
~
.r.~C1OR
Switching Characteristics
Parameters
Over the Operating Rangel3, 6]
Description
7C408A-15
7C409A-15
Thst
Conditions
Min.
Max.
7C408A-25
7C409A-25
Min.
Max.
7C40SA-35
7C409A-35
Min.
Max.
Units
35
MHz
to
OperatingFrequency
Note 7
tpHS!
SIHIGHTime
Note 7
23
11
9
ns
tpLS!
SO LOW Time
Note 7
25
24
17
ns
tSS!
Data Set-Up to SI
NoteS
0
0
0
ns
tHS!
Data Hold from SI
Note 9
30
20
12
tOUR
Delay, SI IDGH to IR LOW
35
21
15
ns
tOHIR
Delay, SI LOW to IR IDGH
40
23
16
ns
tpHSO
SO HIGH Time
Note 7
23
11
9
tpLSO
SOWWTime
Note 7
25
24
17
tOWR
Delay, SO HIGH to OR WW
25
15
21
35
40
ns
ns
15
ns
16
ns
tOHOR
Delay, SO LOW to OR IDGH
tSOR
Data Set-Up to OR HIGH
0
0
0
tHSO
Data Hold from SO LOW
0
0
0
taT
Fall-through, Bubble-backTime
10
tS!R
DataSet-UptolR
Note 9
5
5
5
ns
tHiR
Data Hold from IR
Note 10
30
20
20
ns
tPIR
Input Ready Pulse IDGH
Note 10
6
6
6
ns
tpOR
Output Ready Pulse HIGH
Note 11
6
6
6
tmzoE
OE LOW to LOW Z (7C40BA)
Note 12
35
30
25
ns
tOHZOE
OE IDGH to IDGH Z (7C40SA)
Note 12
35
30
25
ns
tOHHF
SI LOW to HF HIGH
65
55
45
ns
tOLHF
SO LOW to HFLOW
65
55
45
ns
tOIAFE
SO or SI LOW to AFE LOW
65
55
45
ns
tOHAFE
SO or SI LOW to AFE HIGH
45
ns
tpMR
MR Pulse Width
55
45
35
toS!
MRHIGHtoSIIDGH
25
10
10
tOOR
MRLOWto OR LOW
55
45
35
ns
tDiR
MRLOWtolRIDGH
55
45
35
ns
tLZMR
MRLOW to Output LOW
55
45
35
ns
tAFE
MRLOWto AFE HIGH
55
45
35
ns
tHF
MR LOW to HF LOW
55
45
35
ns
too
SO LOW to Next Data Out Valid
28
20
16
ns
65
23
ns
10
Noles:
6. Test conditions assume signal transition time of 5 ns or less, timingreference levels of 1.5V and output loading of the specified 10rJIOH and
30-pF load capacitance, as in parts (a) and (b) of AC Thst Loads and
Waveforms.
7. lifo ~ (tPHS! + tPLSV, lifo ~ (tPHSO + tPLSO).
8. tSS! and tHS! apply when memory is not full.
9. tSIR and tHIR apply when memory is full, SI is high and minimum
bubble-through (lIlT) conditions exist.
10. At any given operating condition tPIR ~ (tpHSO required).
11. At any given operating condition tpOR ~ (tPHS! required).
10
55
65
Note 13
60
ns
ns
50
ns
ns
ns
ns
12. tDHWE and tDlzOE are specified with CL = 5 pF as in part (b) of AC
Test Loads and Waveforms. IoHWE transition is measured ±500mV
from steady-state voltage. tDLWE transition is measured ±loo mV
from steady-state voltage. These parameters are guaranteed and not
100% tested.
13. All data outputs will be at WWlevel afterreset goes IDGH until data
is entered into the FIFO.
5-1S
.
CY7C408A
CY7C409A
·~PRFSS
~F
SEMICONDUCTOR
Switching Waveforms
Data In Timing Diagram
SHIFT IN
INPUT READY
•
DATA IN
AFE
HF
(LOW)
----~~-----------------------------------------C408A·7
Data Out Timing Diagram
------rI4-----
lifo
----..r
SHIFT OUT
,-----,
OUTPUT READY
DATA OUT
HF
(LOW)
-t-~--
AFE
C408A-8
Notes:
14. FIFO contains 8 words.
15. FIFO contains 9 words.
5-19
CY7C408A
CY7C409A
~
~~
~.CYPRESS
~F
SEMICONDUCTOR
Switching Waveforms (continued)
Data In Timing Diagram
1 - - - - - I/fo
SHIFT IN
-------i~-----
I/fo - - - - - - \
~--"
NOTE 16
---i~-- tp~1 --~
INPUT READY
DATA IN
(lO~
AFE
HF
tDHHFf_ _ _ _ _ _ _ _ _ __
C40BA-9
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
HF
(lO~
AFE
C408A-10
Output Enable (CY7C408A only)
~
OUTPUT ENABLE
~
~ tDLZOE : (_ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _tD_H_ZOE
DATA OUT _ _ _ _ _ _ _ _ _ _
NOTE 12
-
C4Q8A..11
Notes:
16. BFO contains 31 words.
17. FIFO contains 32 words.
5-20
CY7C408A
CY7C409A
~
.,CYPRF5S
_
SEMICONDUCIDR
Switching Waveforms (continued)
Data In Timing Diagram
SHIFT IN
INPUT READY
•
DATA IN
HF
(II
0
AFE
U.
u::
C408A-12
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
AFE
HF
(HIGH)
Bubble-Back, Data Out Th Data In Diagram
SHIFT OUT : ; 0 1 " ' ' '
SHIFT IN
t
C40BA-13
r---------+---------------------------~,~
1 4 - - - - IBT -----I.~I
____________
"-
INPUTREADY ____________________________________- '
DATA IN
'sIR
Notes:
18_ FIFO contains 55 words_
-01+----
20_ FIFO contains 64 words_
19_ FIFO contains 56 words_
5-21
C408A-14
CY7C408A
CY7C409A
Switching Waveforms (continued)
Fan·Through, Data In to Data Out Diagram
SHIFT IN
SHIFT OUT
OUTPUT READY
DATA OUT
NOTE 21
/
J
k----
IBT
----+10_-
_____>k
lSOR
------------------------C408A-15
Master Reset Timing Diagram
-lpMR-
MASTER RESET
~
/
IOIR
}I{
INPUT READY
ioCR
~
OUTPUT READY
IOSI
SHIFT IN
}
tl2MR
"' '\.
DATA OUT
HF
AFE
_IHF
-
IAFE
"'
/
C408A-16
Note:
21. FIFO is empty.
5-22
CY7C408A
CY7C409A
Architecture of the CY7C408A and CY7C409A
The CY7C40BA and CY7C409A FIFOs consist of an array of 64
wordsof8 or9 bits each (which are implemented using a dual-port
RAM cell), a write pointer, a read pointer, and the control logic
necessary to generate the handshaking (SI/lR, SO/OR) signals as
well as the almostfulllalmost empty (APE) andhalffull (HF) flags.
The handshaking signals operate in a manner identical to those of
the industry standard CY7C40l/402/403/404 FIFOs.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent ofeach other, which isnecessaryto achieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
to propagate through the memory, which it would have to do if the
memory were implemented using the conventional register array
architecture.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the output of an initially empty FIFO is defined as the fall-through time.
The time required for anemptylocation to propagate from the output to the input of an initially full FIFO is defined as the bubbleback time.
The maximum rate at which data can be passed through the FIFO
(called the throughput) is limited by the fall-through time when it
is empty (or near empty) and by the bubble-back time when it is full
(or near fuJI).
The conventional definitions of fall-through and bubble-back do
not apply to the CY7C40BA and CY7C409A FIFOs because the
data is not physically propagated through the memory. The read
and write pointers are incremented instead of moving the data.
However, the parameter is specified because it does represent the
worst-case propagation delay for the control signals. That is, the
time required to increment the write pointer and propagate a signal from the SI input to the OR output of an empty FIFO or the
time required to increment the read pointer and propagate a signal
from the SO input to the IR output of a fuJI FIFO.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (QR)
signal. This causes the device to enter the empty condition, which
is signified by the OR signal being LOW at the same time that the
IR signal is HIGH. In this condition, the data outputs (DOo -
DOs) will be LOW. The APE flag will be HIGH and the HF flag
will be LOW.
Shifting Data Into the FIFO
The availability of an empty location is indicated by the HIGH
state of the input ready (IR) signal. When IR is mGH a LOW to
mGH transition on the shift in (SI) pin will clock the data on the
DID - DIs inputs into the FIFO. Data propagates through the device at the falling edge of S1
The IR output will then go LOW, indicating that the data has been
sampled. The mGH-to-LOW transition of the SI signal initiates
the LOW-to-ffiGH transition of the IR signal if the FIFO is not
full. If the FIFO is full, IR will remain LOW.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated by
the mGH state of the output ready (OR) signal After the FIFO
is reset all data outputs (000 - DOs) will be in the LOW state.
As long as the FIFO remains empty, the OR signal will be LOW
and all SO pulses applied to it will be ignored After data is
shifted into the FIFO, the OR signal will go mGH. The external
control logic (designed by the user) shoUld use the HIGH state of
the OR signal to generate a SO pUlse. The data outputs of the
FIFO shoUld be sampled with edge-sensitive type 0 flip-flops (or
equivalent), using the SO signal as the clock input to the flip-flop.
AFE and HF Flags
1\vo flags, almost full/almost empty (APE) and half fuJI (HF), desenne how many words are stored in the FIFO. APE is HIGH
when there are 8 or fewer or 56 or more words stored in the FIFO.
Otherwise the APE flag is LOW. HF is HIGH when there are 32 or
more words stored in the FIFO, otherwise the HF flag is LOW.
Flag transitions occur relative to the falling edges of SI and SO
(Figures 1 and 2).
Due to the asynchronous nature of the SI and SO signals, it is
possible to encounter specific timing relationships which may
cause short pUlses on the APE and HF flags. These pUlses are entirely due to the dynamic relationship of the SI and SO signals.
The flags, however, will always settle to their correct state after
the appropriate delay (tOHAFE, tOLAFE, tomm or tOLHF).
Therefore, use of level-sensitive rather than edge-sensitive flag
detection devices is recommended to avoid false flag encoding.
Cascading the 7C408/9A -35 Above 2S MHz
If cascaded FIFOs are to be operated with an external clock rate
greater than 25 MHz, the interface IR signal must be inverted before being fed back to the interface SO pin (Figure 3). 1\vo things
should be noted when this configuration is implemented.
FULL
EMPTY
2
SHIFT IN
...Jr'1LJr'1L •••
8
9
10
31
32
33
55
56
57
64
....I1..
•••
HF
AFE
C4D8A·17
Figure 1. Shifting Words In
5-23
•
(I)
o
LL.
u:::
CY7C408A
CY7C409A
~
~~PRFSS
~, SEMICONDUClDR
FULL
64
SHIFT OUT
EMPTY
63
56
55
31
32
54
9
30
7
8
...IL
JUL...
HF
AFE
C408A-1B
Figure 2. Shifting Words Out
A
IR
IRx
SI
Six
DINX
c
B
IR
SO
SI
OR
~
IR
SO
SI
OR
~
IR
SO
SOx
SI
OR
ORX
~N
: DoUlX
I
• • •
2
..
N
UPSTREAM
DOWNSTREAM-----_
..
C408A-19
Figure 3. Cascaded Configuration Above 25 MHz
128 x 9 Configuration
HF/AFE
HF/AFE
SHIFTIN_ SI
INPUT READY
DATA IN
---
OR
SO
SI
IR
OR
OUTPUT READY
IR
SO
SHIFT OUT
Dio
Dll
DOo
DOl
Dio
Dll
DOo
DOl
DI2
D02
DI2
D02
D03
D04
DI3
DI,j
D03
D04
DOs
Dis
D06
D07
D08
DI6
DI7
DI8
DOs
D06
DATA OUT
D~
MR
D08
C408A-20
MR
Figure 4. Cascaded Configuration at or below 25 MHz[22, 23, 24, 25, 261
First, the capacity ofN cascaded FIFOs is decreased from N X 64
to(N X 63) + 1.
Noles:
22. FlFOs can be easily cascaded to any desired depth. The handshaking
and associated timiog between the FlFOs are handled by the inherent
timing of the devices.
23. When the memory is empty the last word read will remaio on the outputs until the master reset is strobed or a new data word falls through
to the output.
24. WhentheoutputdatachangesasaresultofapulseonSO,theORsignal always goes LOW before there is any change io output data and
stays LOW until the new data has appeared on the outputs. Anytime
OR is mOH, there is valid stable data on the outputs.
25. If SO is held mOH while the memory is empty and a word is written
into the input, that word will fall through the memory to the output.
OR will go mOH for one internal cycle (at least lpoR) and then go
back LOW agaio. The stored word will remaio on the outputs. If more
words are written into the FIFO, theywilliioe up behiod the first word
and will not appear on the outputs until SO has been brought LOW.
5-24
CY7C408A
CY7C409A
~
~~
. • CYPRFSS
_
F
SEMICONDUCfOR
192 x 27 Configuration
HF/AFE
HF/AFE
-
IR
SI
010
011
012
013
014
015
Dis
017
Ole
--
SHIFT IN
-
-
IR
SI
010
011
012
013
SO
OR
000
001
002
003
004
005
006
007
MR OOe
IR
SI
010
011
012
013
014
015
016
017
Ole
SO
OR
000
001
002
003
004
005
006
007
MR OOe
IR
SI
010
011
012
013
014
015
016
017
Ole
O~
015
016
017
Ole
r
COMPOSITE
INPUT READY
-- -0=
SO
OR
000
001
002
003
004
005
006
007
MR OOe
IR
SI
010
011
012
013
O~
015
Dis
017
Ole
O~
015
016
017
Ole
IR
SI
010
011
012
013
SO
OR
000
001
002
003
004
005
006
007
MR OOe
IR
SI
010
011
012
013
SO
OR
000
001
002
003
004
DOs
DOs
OCr
MR OOe
IR
SI
010
011
012
Ola
O~
015
016
017
Ole
r
r
IR
SI
010
011
012
013
SO
OR
000
001
002
003
004
005
006
007
MR OOe
I
SHIFT OUT
r
O~
015
016
017
Ole
r
r
SO
OR
000 I-001 I-002 I-003 I-004 I-005 I-006 I-007 I-MR DOe I--
r---
SO
OR
000 I-001
002 r003 r 004
005
006
007
MR DOe
O~
~
---l.-./
r-
r
015
016
017
Dis
COMPOSITE
OUTPUT READY
SO
OR
000
001
002
003
004
005
006
007
MR DOe
-
---MFi
I
C40BA-21
Figure S. Depth and Width Expansion[23, 24, 25, 26, 27]
Notes:
26. When the master reset is brought LOW, the outputs are cleared to
LOW, IR goes mOH, and OR goes LOW.
27. FIFOs are expandable in depth and width. However, io formiogwider
words, two external gates are required to generate composite ioput
5-25
ready and output ready flags. This needis due to the variation of delays
of the FIFOs.
CY7C408A
CY7C409A
If data is to be shifted out simultaneously with the data being
Secondly, the frequency at the cascade interface is less than the
35 MHz rate at which .the external clocks may operate. Therefore, the first device has its data shifted in faster than it is shifted
out, and eventually this device becomes momentarily full. When
this occurs, the maximum sustainable external clock fre'l!l.!lncy
changes from 35 MHz to the cascade interface frequency.l2ll]
shifted in, the concept of "virtual capacity" is introduced VIrtual
capacity is simply how large a packet of data can be shifted in at a
fixed frequency, e.g., 35 MHz, simultaneously with data being
shifted out at any given frequency. Figure 6 is a graph of packet
size(30) vs. shift out frequency (fsOX> for two different values of
shift in frequency (fsW when two FIFOs are cascaded.
The exact complement of this occurs if the FIFOs initially contain
data and a high shift out frequency is to be maintained, i.e., a 35
MHz fsOx can be sustained when reading data packets from devices cascaded two or three deep.!31) If data is shifted in simultaneously, Figure 6 applies with fSIx and fsOx interchanged.
When data packets129] are transmitted, this phenomenon does
not occur unless more than three FlFOs are depth cascaded. For
example, if two FIFOs are cascaded, a packet of 127 (=2 X 63 +
1) words may be shifted in at up to 35 MHz and then the entire
packet may be shifted out at up to 35 MHz.
400
350
~300
'SIx=30MHz
",
1250
~200
(/)
Iii
150
~
~ 100
-
If
...!!!~
'slx=35 MHz
50
o
o
4
8 12 16 20 24 28 32 36
OUTPUT RATE
(lsaxl OF BOTTOM FIFO (MHz)
Figure 6. Virtual Capacity vs. Output Rate for 1\\'0 FIFOs Cascaded Using an Inverter
Notes:
28. Because the data throughput io the cascade ioterface is dependent on
the ioverter delay, it is recommended that the fastest available ioverter
be used.
29. 'fransmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs isshifted io without simultaneous shift out
clock occurring. The complementofthis holdswhen data is shifted out
as a paclcet.
30. These are typical packet sizes using an ioverter whose delay is 4 ns.
31. Only devices with the same speed grade are specified to cascade together.
5-26
dt:':z
~.CYPRESS
~_,
CY7C408A
CY7C409A
SEMlCONDUClDR
1YPicaJ DC and AC Characteristics
NORMUUAZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMUUAZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.2 ,:.:-::....:....,---'-'-::........:r=--..,---,
31.0 1----+--+---2o'~_l
1.4
3
Q
Q
~ 0.81---+-~+----+---j
::J
a:
o
Z
1.21------+------1
1.01------=""'io"""""-----l
~
a:
0.4 L-_--'--_----'L-_--'--_--'
4.0
4.5
6.0
0.0 L-_ _ _--'--_ _ _ _--'
-55
25
125
~
w
N
::J
«
::;;
0.9
-
0
0.8
a:
Z
0.7
4.0
~
1.2
~
Q
r'
w
5.5
SUPPLY VOLTAGE
o
O
0.6
-55
6.0
!l:!
a:
100
u
80
~
25
/
~ 60
~
40
""
4.0
5
20
oI
125
L
~
/
1.0
0.0
Vcc=5.0V
TA = 25°C
I
2.0
3.0
4.0
OUTPUT VOLTAGE M
NORMUUAZED Icc
vs. FREQUENCY
1.6
1.1
r5 1.5
V
./
::l
@1.4
u
y
Q
~
/
/
w 0.9
~a:
/
~
~ 1.2
1.0
.2
/V
fE
Q 1.3
1.0
o
3.0
/
~
Z
"'"
./~
AMBIENT TEMPERATURE (OC)
M
2.0
OUTPUT VOLTAGE M
:><:
TYPICAL FREQUENCY CHANGE
vs.OUTPUTWADING
01.1
1.0
0.0
::l
Z
5.0
Vcc= 5.0V
TA= 25°C
10
Z
l5 0.8
4.5
§
f-
@
fE
"-
20
<" 140
::l
I----
~
fil
5
~
.s 120
r51.4
1.0
"
30
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
~
Z
w
~
VS. AMBIENT TEMPERATURE
1.6
a:
"-
50
a:
~ 40
NORMUUAZEDFREQUENCY
NORMUUAZEDFREQUENCY
vs. SUPPLY VOLTAGE
1.3
u..
!zw
AMBIENT TEMPERATURE (0 C)
SUPPLY VOLTAGE M
Q
60
::l
Vcc= 5.5V
V'N=5.0V
w 1.2
::l
C 1.1
.s<"
U
~
~ 0.81------+------1
0.6 f-7"--+---
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
oZ
J
0.8
/
0.7
/'
/
V
0.0
200
400
600
800 1000
o
5
10 15 20
25
30
35
C408A-23
FREQUENCY (MHz)
CAPACITANCE (pF)
5-27
•
I I)
o
LL
ii:
CY7C408A
CY7C409A
&.nPRKSS
~__
SEMICONDUClDR
Ordering Information
Frequency
(MHz)
15
25
35
Package
1YPe
Operating
Range
Frequency
(MHz)
CY7C408A -15DC
D22
Commercial
15
CY7C409A -15DC
Package
1Ype
D22
CY7C408A -15LC
L64
CY7C409A -15LC
L64
CY7C408A -15PC
P21
CY7C409A -15PC
P21
CY7C408A-15VC
V21
CY7C409A -15VC
V21
CY7C408A-15DMB
D22
CY7C409A-15DMB
D22
CY7C408A-15KMB
K74
CY7C409A-15KMB
K74
Ordering Code
CY7C408A-15LMB
L64
CY7C408A-25DC
D22
CY7C408A-25LC
Military
Ordering Code
CY7C409A-15LMB
L64
CY7C409A-25DC
D22
L64
CY7C409A-25LC
L64
CY7C408A-25PC
P21
CY7C409A-25PC
P21
CY7C408A-25VC
V21
CY7C409A-25VC
V21
CY7C408A-25DMB
022
CY7C409A-25DMB
D22
CY7C408A-25KMB
K74
CY7C409A-25KMB
K74
Commercial
25
Military
CY7C409A-25LMB
L64
CY7C409A-35DC
D22
L64
CY7C409A - 35LC
L64
CY7C408A-35PC
P21
CY7C409A-35PC
P21
CY7C408A-35VC
V21
CY7C409A - 35VC
V21
CY7C408A-25LMB
L64
CY7C408A-35DC
022
CY7C408A-35LC
Commercial
·5-28
35
Operating
Range
Commercial
Military
Commercial
Military
Commercial
CY7C408A
CY7C409A
=::~
~-CYPRESS
~, SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VILMax.
Ilx
loz
los
leCQ
Parameters
Subgroups
fo
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
tpHSI
tpLSI
tSSl
tHSI
tOLm
tOHIR
tpHSO
tpLSO
tOWR
tOHOR
tSOR
tHSO
tBT
tsm
tHm
tpm
tpOR
tSlm
tSOOR
tOLZOE
tOHZOE
tOHHF
tOLHF
tOJAFE
tOHAFE
tB
too
tpMR
tOSI
tOOR
tOIR
tLZMR
tAFE
tHF
Document #: 38-00059-E
5-29
II)
o
u.
u::
CY7C420, CY7C421
CY7C424, CY7C425
CY7C428, CY7C429
CYPRESS
SEMICONDUCTOR
Features
Cascade able 512 X 9 FIFO
Cascadeable 1Kx 9 FIFO
Cascadeable 2Kx 9 FIFO
• TTL compatible
• Three-state outputs
• Pin compatible and functional
equivalent to ID17201, IDT7202, and
ID17203
33.3 MHz. The write operation occurs
when the write ("1 signal is LOW. Read
occurswhen read (R)goesWW. The nine
data outputs go to the high-impedance
state when R is HIGH.
• Asynchronous read/write
Functional Description
• High-speed 33.3-MUz read/write
The CY7C420/CY7C421, CY7C424/
CY7C425, and CY7C428/CY7C429 are
first-in first-out (FIFO) memories offered
in 600-mil wide and 300-mil wide packages. They are, respectively, 512, 1,024,
and 2,048 words by9-bitswide. Each FIFO
memory is organized such that the data is
read in the same sequential order that it
was written. Full and Empty flags are provided to prevent overrun and underrun.
Three additional pins are also provided to
facilitate unlimited 'expansion in width,
depth, or both. The depth expansion technique steers the control signals from one
device to another in parallel, thuseliminating the serial addition of propagation delays, so that throughput is not reduced.
Data is steered in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
A Half Full (HF) output flag is provided
that is valid in the standalone and width
expansion configurations. In the depth expansion configuration, this pin provides
the expansion out (XO) information that is
used to tell the next FIFO that it will be activated.
• 512 x 9, 1,024 x 9, 2,048 x 9 FIFO buffermemory
• DuaI-portRAMcell
independentordep~dth
• Low operating power
- Icc (max.) 142 mA
=
(commercial)
- Icc (max.) = 147 mA (mllitary)
• Half Full nag in standalone
• Empty and Full nags
• Retransmit in standalone
• Expandable in width and depth
• Parallel cascade minimizes
bubble-through
• SV::!: 10% supply
• 300-milDIPpackaging
• 300-mil SOJ packaging
Logic Block Diagram
In the standalone and width expansion
configurations,a WW on the retransmit
(lIT) input causes the F.!!Os to retransmit
the data. Read enable (R)andwrite enable
(W) must bot!!.. be HIGH during retransmit, and then R is used to access the data.
The CY7C420, CY7C421, CY7C424,
CY7C425, CY7C428, and CY7C429 are
fabricated using an advanced 0.8-micron
N-weUCMOS technology. Input ESD protection is greater than 2000V and latch-up
is prevented by careful layout, guard rings,
and a substrate bias generator.
Pin Configurations
DATA INPUTS
(Oo-D8)
DIP
Top View
PLCC/LCC
Top View
D2
4
D,
S
6
Do
7
Xl
FF
8
9
3
2 111 32 31 30
29
28
ZT
26
7C42X
25
00
10
2'
0,
11
23
NC
22
12
13
21
1. 1S 16 17 181920
00
DATA OUTPUTS
(Oo-Oal
C42Q.2
W
DB
D8
D3
D7
D2
NC
D,
FLJRT
DO
MIl
Xi
EF
FF
XOIHl'
00
Or
0,
Os
02
03
08
GND
Vee
D,
DS
D6
D7
mRT
MR
EF
XO/HF
07
06
05
0,
R
C42Q.{1
C420-1
5-30
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~4
~=CYPRF.SS
. ' SEMICalDUCfOR
Selection Guide
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
Frequency (MHz)
333
28.5
12.5
20
142
25
132
25
30
20
MaximumAccessTime(ns)
125
40
115
65
100
147
140
130
115
MaximumOperating
Current (rnA)
I
I
Commercial
Military/lndustrial
Maximum Rating
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to +150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Power Dissipation ................................ LOW
Output Current, into Outputs (LOW) ............... 20 rnA
Electrical Characteristics
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Ambient
Thmperature!l]
Range
O°Cto + 70°C
Vee
5V± 10%
Industrial
- 40°C to +85°C
5V± 10%
Military
- 55°C to +125°C
5V± 10%
Commercial
Over the Operating Rangel2]
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
Parameter
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min.,IoL = 8.0 rnA
VIH
Input HIGH Voltage
Com'l
2.. 4
0.4
Vee
MilJInd
VIL
Input LOW Voltage
IIX
Input LeakageCurrent
Ioz
Output LeakageCurrent
R~ VIH,GND.s Vo.s Vee
lee
Operating Current
Vee = Max.,
lOUT = ornA
MilJIndl4]
All Inputs = VIH Min.
Com'l
ISBI
Standby Current
GND.sVI.sVee
Com'I!3]
Power-Down Current
AlIInputs~ Vee-
0.2V Com'l
Output Short
Circuit Currentl5]
Vee = Max., VOUT = GND
Notes:
1. TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing infonnation.
3. Icc (commercial) = 100_rnA + [(l' -12.5)· 2mNMHz]
for f ~ 12.5 MHz
where l' = the larger of the write or read operating frequency.
2.
2.4
0.4
V
0.4
V
V
2.0
Vee
2.0
Vee
2.2
2.2
Vee
-3.0
0.8
-3.0
-3.0
0.8
V
-10
+10
-10
+10
-10
+10
-10
+10
-10
+10
-10
142
30
25
MilJInd
los
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
Vee
0.8
Mil/lnd
IsB2
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
Max. Min. Max. Min. Max. Units
2.4
2.0
- 90
+10
flA
flA
132
125
rnA
147
140
25
25
30
30
20
20
25
25
-90
-90
rnA
rnA
rnA
Icc (military) =
115_rnA + [(l'-12.5)· 2mNMHz]
_
for f ~ 12.5 MHz
where f = the larger of the write or read operating frequency.
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4.
5-31
•
( I)
Operating Range
o
u.
u:::
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
Electrical Characteristics
Over the Operating Rangel2] (continued)
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
Description
Parameter
Thst Conditions
Min.
VOR
Output HIGH Voltage
Vee = Min., lOR = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
7C420-6S
7C421-6S
7C424-6S
7C425-6S
7C428-65
7C429-6S
Max.
2 ..4
Min.
Max.
Units
0.4
V
V
2.4
0.4
V
Com'l
2.0
Vee
2.0
Vee
MilJlnd
2.2
Vee
2.2
Vee
VIL
Input LOW Voltage
- 3.0
0.8
- 3.0
0.8
V
IJX
Input Leakage Current
GND,==;,VI,==;,Vee
-10
+10
-10
+10
loz
Output LeakageCurrent
R~ VIH,GND.==;. Vo'==;'
-10
+10
-10
+10
J.tA.
J.tA.
Icc
OperatingCurrent
Vee = Max.,
lOUT = ornA
Com'I[3]
115
100
rnA
MilJInd4]
130
115
Alllnputs = VIH Min.
Com'l
25
25
Mil
30
30
20
20
Standby Current
ISBl
Vee
ISB2
Power-DownCurrent
AllInputs~ Vee-
los
Output Short
CircuitCurrend5]
Vee = Max., VOUT = GND
0.2V Com'l
Mil
25
25
-90
- 90
rnA
rnA
rnA
Capacitance [6]
Parameters
CIN
CoUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C,f= 1 MHz,
Max.
8
Vee = 4.5V
10
Units
pF
pF
Notes:
6. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1500r.!
R1500r.!
5V 0-----'11Il10--,
OUTPUTo--_ _- ..
OUTPUT 0 - -_ _- "
30PFI
INCWDING
JIGAND _
R2
333C
-=-
SCOPE -
5V o - - - - - ' w . . . ,
C420-4
GND
R2
333C
INCLUDING
JIGAND _
(a)
Equivalent to:
5PFI
ALL INPUT PULSES
3.OV~
SCOPE -
C420-5
(b)
THEvENIN EaUIVALENT
2000
OUTPUT 0 0 0 - -....·""....
· · - - - 0 0 2V
5-32
90%
10%
.s.5ns-..
~
C420-6
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
s;;=~
------. CYPRESS
~.,
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[7.8]
7C420-20
7C421-20
7C424-20
7C42S-20
7C428-20
7C429-20
Parameters
25
25
30
35
40
50
80
ns
tRHF
Read HIGH to HF HIGH
30
35
40
50
80
ns
tRAE
Effective Read from
Write HIGH
20
25
30
35
60
ns
tRPE
Effective Read Pulse Width
After EF HIGH
tWAF
Effective Write from
Read HIGH
tWPF
Effective Write Pulse Width
After FF HIGH
tXOL
Expansion Out LOW
Delay from Clock
20
25
30
40
65
ns
tXOH
Expansion Out HIGH
Delay from Clock
20
25
30
40
65
ns
20
20
3
3
30
3
3
35
25
10
10
10
10
12
0
30
20
10
20
20
30
20
10
25
10
25
25
35
25
10
30
30
30
25
25
25
20
20
10
10
10
30
5-33
65
40
35
30
30
25
80
80
80
60
60
60
60
10
80
65
15
65
65
80
65
15
10
25
25
25
25
50
50
50
35
35
35
35
30
80
65
10
15
30
20
0
50
40
10
40
40
50
40
40
40
40
25
20
50
40
35
35
35
65
15
65
3
3
25
40
30
10
18
0
40
30
10
30
30
40
30
10
15
0
35
40
20
18
15
30
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
80
10
40
3
3
10
3
3
Max.
50
30
25
10
25
10
Max.
Min.
Write LOW to HF' LOW
tHWzL9j
tWR
tSD
tHO
tMRSC
tpMR
tRMR
tRPW
twpw
tRI'C
tpRI'
tRr'R
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
35
Min.
40
Min.
tWHF
twc
tpw
Max.
7C420-6S
7C421-6S
7C424-6S
7C42S-6S
7C428-6S
7C429-6S
tWFF
tDVRL•• 1Uj
tHZRL9 .lUj
30
Min.
7C420-40
7C421-40
7C424-40
7C42S-40
7C428-40
7C429-40
30
30
30
30
tLZRL~j
Max.
7C420-30
7C421-30
7C424-30
7C42S-30
7C428-30
7C429-30
Description
Read Cycle TIme
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Read HIGH to Data Valid
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EFLOW
MRto HF'HIGH
MRtoFFHIGH
Read LOW to EF LOW
Read HIGH to J:'F HIGH
Write HIGH to EF HIGH
Write LOW to 'FF LOW
tRC
tA
tRR
tpR
Min.
7C420-2S
7C421-2S
7C424-2S
7C42S-2S
7C428-2S
7C429-2S
40
ns
60
65
ns
ns
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
Switching Waveforms
Asyn~nous~dandVVrire
R---.,
-e
w
0 0 -08
I ~ 4--------.J/""'---
Ow
I:: Iso
--------K~
tHO
DATA VALlD_
~
JI»-------C(
DATA VALID
)>----
0120-7
Master Reset
1 4 - - - - - - tMRScf 12l - - - - - - - - - - - . . . .
_________~~----tpMR -------~~Jr----_+-----------------R,W[ll]
HF
FF
711111Z/7fl/;;mm}
C420-8
Half-Full Flag
HALF FULL
HALF FULL +1
W
HALF FULL
- -
/
iRHF
~ tWHF·
r-
Notes:
7. Thst conditions assume signal transition time of S ns or less, timing
reference levels of 1.5V and output loading of the specified IOrlIOH
and 30 pF load capacitance, as in part (a) of AC Thst Load and
Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing
information.
9.
tHZR transition is measured at +SOo mV from VOL and -SOO mV
from VOH. toVR transition is measured at the 1.SV level. tHWZ and
tLZR transition is measured at ± 100 mV from the steady state.
10. tHZR and tDVR use capacitance loading as in part (b) of AC Thst Load
and Waveforms.
11. Wand R ~ VIH around the rising edge of MR.
12. tMRSC = tpMR + tRMR.
5-34
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
·
~
_·iECYPRESS
~.F SEMICONDUCTOR
Switching Waveforms (continued)
Last Write to First Read Foil Flag
LAST WRITE
R --~------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
W
FF
--~--...... I
C420-10
•
U)
o
u..
Last Read to First Write Empty Flag
LAST READ
ADDITIONAL
WRITES
FIRST WRITE
u::
FIRST READ
W --~------------~
EF
DATA OUT
-+-+-.1
--I--lY.Y\iAi:i~
C420-11
Retransmitl13]
tRTC[ 14l
I---
tpRT
FlIRT
R,W
I+---
tRTA - -
Note.:
13. EF, HF and FF may change state during retransmit as a result of the
offset of the read and write pointers, but flags will be valid at tRTC.
14. tRTC = tpRT + tRTR.
5-35
C420-12
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
Switching Waveforms (continued)
Empty Flag and Empty Boundary Timing Diagram
DATA IN
w--+----.
EF
----jl-------:----j.----'
DATA OUT ----i!--------....I-k'
0420-13
Full Flag and Full Boundary Timing Diagram
w
~--i-------~---J
tHD
DMAIN--~--------------------~~-~~~~~~~~7r~-~~A_----------------t~,------.
DATA OUT
----<2$.M
DATA VALID
)@-----------------C420-14
5-36
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~
~=CYPRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Expansion Timing Diagrams
w ___......
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
DATA VALID
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
00- 0 8
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
---+-----(
Notes:
15. ExpansjQ.n Out of device 1 (XOI) is connected to Expansion In of device 2 (XI2).
5-37
•
en
0120·15
o
u..
u:::
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
Architecture
The CY7C420/421/424/425/428/429 FIFOs consist of an army of
512/1024/2048 words of 9 bits each (implemented by an array of
dual-E2rt RAM celis), a read..l!!!..inter, a write pointer, control signals (W, It, XI, XO, J:I:, RT, MR), and Full,Ha,lf Full, and Empty
flags.
Dual-Port RAM
The dual-port RAM architecrure refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of eaCh other, which is necessary to
achieve truly asynchronous operation of the inputs and outputs.
A second benefit is that the time required to increment the read
and write pointers is much less than the time that would be required for data propagation through the memory, which would be
the case if the memory were implemented using the conventional
register array architecture.
Resetting the FIFO
~ power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the. Empty flag (J!P) being LOW, and both the Half
Full (HF') and Full flags (F'F) being mGH. Read (R:) and write
(JIl) must be HIGH tRPw/twpw before and tRMR after the rising
edge of MR for a valid reset cycle. If reading from the FIFO after
a reset cycle is attempted, the outputs will all be in the high-impedance state.
Writing Data to the FlFO
The availability of at least one empty location is indicated by a
mGH FE The falling edgeofW initiates a write cycle. Data appearing at the inputs (Do - D8) tSD before and tHD after the rising
edge of W will be stored sequentially in the FIFO.
The EF LOW-to-mGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. RF goes
LOW twHP after the falling edge of W following the FIFO actually being Half Full. Therefore, the RF is active once the FIFO
is filled to half its capacity plus one word. RF will remain LOW
while less than one half of total memory is available for writing.
The LOW-to-mGH transition ofm occurs tRHF after the risl!!g
edge of It when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF goes
LOW tWFP after the falling edge of W, during the cycle in which
the last available location is filled. Intemallogic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the
write pointer is not incremented. FF goes mGH tREP after a
read from a full FIFO.
Reading Data from the FIFO
The falling edge of It initiates a read cycle if the m:' is not LOW.
Data outputs (QO - Qs) are in a high-impedance condition between read operations (R mGH) when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of 1m When the FIFO is empty, the
outputs I!fIl in a high-impedance state. Reads to an empty FIFO
are ignored and do not increment the read pointer. From the
empty condition, the FIFO can be read twEF after a valid write.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last :Q'II cycle. A LOW pulse on
ItT resets the internal read pointer to the first physical location of
the FIFO. R and Wmust both be mGH while and tRrR after retransmit is LOW. With every read cycle after retransmit, previously accessed data is read and the read pointer is incremented
until it is equal to the write pointer. Full, Half Full, and Empty
flags are governed by the relative locations of the read and write
pointers and are updated durin~ retransmit cycle. Data written
to the FIFO after activation of RI' are transmitted also.
The full depth of the FIFO can be repeatedly transmitted.
Standalooe/Wldth Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to V ce. FIFOs can be
expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any device can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a x:m: cycle, expansion Out (XO) of one device is connected to Expansion In
('XI) of the next device, with XO of the last device connected to
XI of the first device. In the depth expansion mode the First
Load (TI[) input, when grounded, indicates that this part is the
first to be loaded. All other devices must have this pin mGH. 'Th
enable the correct FIFO, XC> is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW
again when the last physical location is read. Only one FIFO is
enabled for read and one for write at any given time. All other
devices are in standby.
FlFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When e!l!..anding in depth, a composite
FF must be created by ORing the FFs~ether. Likewise, a co.!!!::
posite m:' is created by ORing the BPs together. HF and RT
functions are not available in depth expansion mode.
5-38
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
"rCYPRKSS
~_,
SEMlCONDUCTOR
xc
Vii
FF
9
D
9, "-
/
L "
,v'
r---
Ii"
EF
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
I
I
9
/
IT
"a
v
Vee
Xl
XC
.....
FULL
FF
9, "-
I v'"
EMPlY
EF
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
tI)
o
L&.
IT
u::
f-
XI
XC
-
-
*
FF
9~
IV
MR
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
Xl
EF
r---
~
* FIRST DEVICE
C420-17
Figure 1. Depth Expansion
5-39
•
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
'JYpical DC and AC Characteristics
NORMAI.JZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2 r---r--,......-~-----.
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
VS.AMBffiNTTEMPERATURE
VB.
«60
1.4
.§.
f-
Jl1.0 1---t---t---2o'c---I
a
z
w
N
:J 1.0
«
::;:
""-
a:
0
z
0.61-7~+--
0.4'----'-_ _-'--_-'-_--'
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
Vee = 5.5V
VIN= 5.0V
f=20MHz
0.8
0.0
-55
M
1"'-
-
w
~ 30
:::>
20
g
~
25
125
AMBIENT TEMPERATURE (OC)
~
Vee = 5.0V
TA = 25°C
10
o~
0
0.0
1.0
2.0
'" "'3.0
4.0
OUTPUT VOLTAGE M
« 140
1.6
1.3
"
()
NORMALIZED tA
vs. AMBffiNT TEMPERATURE
NORMALIZED tA
vs. SUPPLY VOLTAGE
50
Z
w
a
I/:l
:J 0.8 f---\--7fl'C-+---+---I
io
3
a:
~ 40
1.2
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
.§.
1.2
:1-
e 1.1
w
~
~
f-
,:11.4
,..............
1.0
r--
r--
a:
0 0.9
z
0.8
0.7
4.0
4.5
--
TA = 25°C
I
5.0
5.5
aw
N
:J
Z
1.2
a: 1.0
z
0.8
~
Vee = 5.0V
25
NORMAI.JZED~CHANGE
1.5
1.4
Z
a
w 0.9
:J
V
1.0 /"
o 200
./
./
N
~ 0.7
a:
/
1.2
1.1
"
/
1.1
.!?
/
1.3
a:
0
1.3
/
Z
0.5
Vee=5.0V
TA = 25°C
'"
0.0
400
600
800 1000
CAPACITANCE (pF)
/
/
./
0
10
V
Vee = 5.0V
TA = 25°C
20
30
CYCLE FREQUENCY (MHz)
5-40
Vee = 5.0V
TA = 25°C
I
4.0
2.0
3.0
OUTPUT VOLTAGE M
NORMAI.JZED Icc VS. CYCLE
FREQUENCY
/
:1-
::;:
1.0
0.0
17"
/
/
§ !//
o
125
VS. OUTPUT LOADING
1.6
~
~ 60
~ 40
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE M
a
/
20
0.6
-55
6.0
a
80
:.::
.,/
«
::;:
0
120
~ 100
a:
40
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
....:=...
~~
_'=
-.F
CYPRESS
SEMICONDUCTOR
Ordering Infonnation
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C420-20DC
CY7C420-20PC
CY7C420-25DC
CY7C420-25PC
CY7C420-25DI
CY7C420-25PI
CY7C420-25DMB
CY7C420-30DC
CY7C420-30PC
CY7C420-30DI
CY7C420-30PI
CY7C420-30DMB
CY7C420-40DC
CY7C420-40PC
CY7C420-40DI
CY7C420-40PI
CY7C420-40DMB
CY7C420-65DC
CY7C420-65PC
CY7C420-65DI
CY7C420-65PI
CY7C420-65DMB
Package
1Ype
D16
PI5
D16
PI5
DI6
PI5
D16
D16
P15
D16
P15
D16
Operating
Range
Speed
Commercial
20
(ns)
Commercial
Industrial
25
Military
Commercial
Industrial
Military
D16
P15
Commercial
D16
P15
Industrial
DI6
DI6
PI5
DI6
PI5
DI6
Military
Commercial
30
Industrial
Military
40
65
5-41
Ordering Code
CY7C421-20DC
CY7C42I-2OJC
CY7C42I 20LC
CY7C42I- 20PC
CY7C42I-20VC
CY7C42I- 25DC
CY7C42I-25JC
CY7C42I-25LC
CY7C42I- 25PC
CY7C42I-25VC
CY7C42I 25DI
CY7C42I-25JI
CY7C42I- 25PI
CY7C42I-25DMB
CY7C42I-25KMB
CY7C42I-25LMB
CY7C42I-30DC
CY7C42I-3OJC
CY7C42I-30LC
CY7C42I 30PC
CY7C421-30VC
CY7C421-30DI
CY7C421-30JI
CY7C421-30PI
CY7C42I-30DMB
CY7C421 30KMB
CY7C421-30LMB
CY7C421-40DC
CY7C42I-40JC
CY7C42I-40LC
CY7C421-40PC
CY7C421-40VC
CY7C42I-40DI
CY7C42I-40JI
CY7C42I-40PI
CY7C421-40DMB
CY7C42I-40KMB
CY7C42I-40LMB
CY7C42I-65DC
CY7C42I-65JC
CY7C421-65LC
CY7C421-65PC
CY7C42I 65VC
CY7C42I-65DI
CY7C42I-65JI
CY7C421-65PI
CY7C421- 65DMB
CY7C42I-65KMB
CY7C42I 65LMB
Package
1YPe
D22
J65
155
P2I
V2I
D22
J65
155
P2I
V2I
022
J65
P2I
022
K74
155
022
J65
155
P21
V21
D22
J65
P2I
D22
K74
155
D22
J65
155
P21
V21
D22
J65
P21
D22
K74
155
D22
J65
155
P21
V21
D22
J65
P21
D22
K74
155
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
•
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
.il~CR)R
Ordering Information (continued)
Speed
(os)
20
25
30
40
65
Package
1)pe
Operatiog
Range
Speed
(os)
CY7C424-20DC
D16
Commercial
20
CY7C424-2OPC
PIS
CY7C424-25DC
D16
CY7C424-25PC
PIS
CY7C424-25DI
DI6
CY7C424-25PI
PIS
CY7C424-25DMB
D16
Military
CY7C424-30DC
D16
Commercial
Ordering Code
CY7C424-30PC
PIS
CY7C424-30DI
D16
Commercial
Industrial
Industrial
CY7C424-30PI
PIS
CY7C424-30DMB
D16
Military
CY7C424-40DC
DI6
Commercial
CY7C424-40PC
PIS
CY7C424-40DI
D16
CY7C424-40PI
PIS
CY7C424-40DMB
DI6
Military
CY7C424-65DC
D16
Commercial
CY7C424-65PC
PIS
CY7C424-65DI
DI6
CY7C424-65PI
PIS
CY7C424-65DMB
D16
25
30
Industrial
Industrial
Military
40
65
5-42
Ordering Code
CY7C425-20DC
CY7C425-2OJC
CY7C425-20LC
CY7C425-20PC
CY7C425-2OVC
C77C425-25DC
CY7C425-25JC
CY7C425-25LC
CY7C425 25PC
CY7C425-25VC
CY7C425-25DI
CY7C425-25JI
CY7C425 - 25PI
CY7C425-25DMB
CY7C425 25KMB
CY7C425-25LMB
C77C425-30DC
CY7C425-3OJC
CY7C425-30LC
CY7C425 - 30PC
CY7C425-30VC
CY7C425 - 30DI
CY7C425 30JI
CY7C425 - 30PI
CY7C425-30DMB
CY7C425-30KMB
CY7C425-30LMB
C77C425-40DC
CY7C425-4OJC
CY7C425-40LC
CY7C425-40PC
CY7C425-40VC
CY7C425-40DI
CY7C425-4OJI
CY7C425-40PI
CY7C425-40DMB
CY7C425-40KMB
CY7C425-40LMB
C77C425-65DC
CY7C425-65JC
CY7C425-65LC
CY7C425-65PC
CY7C425-65VC
CY7C425-65DI
CY7C425 65JI
CY7C425-65PI
CY7C425-65DMB
CY7C425-65KMB
CY7C425-65LMB
Package
1)pe
Operating
Raoge
D22
J65
L55
P2I
V2I
D22
J65
L55
P2I
V2I
D22
J65
P2I
D22
K74
L55
D22
J65
L55
P2I
V2I
022
J65
P2I
D22
K74
L55
022
J65
L55
P2I
V2I
022
J65
P2I
D22
K74
L55
022
J65
L55
P2I
V2I
022
J65
P2I
D22
K74
L55
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
·
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
.~
~~CYPRESS
0'
SEMlCONDUCTOR
Ordering Information (continued)
Speed
(ns)
20
25
Ordering Code
CY7C428-20DC
Package
'lYpe
D16
CY7C428-20PC
PIS
CY7C428-25DC
CY7C428-25PC
D16
CY7C428-25DI
D16
CY7C428-25PI
PIS
D16
CY7C428-25DMB
30
CY7C428-30DC
65
Speed
(ns)
Commercial
20
Commercial
PIS
Industrial
25
Military
DI6
PIS
Commercial
CY7C428-30DI
CY7C428-30PI
D16
Industrial
CY7C428-30DMB
DI6
Military
CY7C428-40DC
DI6
Commercial
CY7C428-40PC
CY7C428-40DI
PIS
DI6
Industrial
CY7C428-30PC
40
Operating
Range
PIS
CY7C428-40PI
PIS
CY7C428-40DMB
D16
Military
CY7C428-65DC
DI6
Commercial
CY7C428-65PC
CY7C428-65DI
PIS
DI6
Industrial
CY7C428-65PI
PIS
CY7C428-65DMB
DI6
30
Military
40
65
5-43
Package
Ordering Code
1YPe
CY7C429-20DC
CY7C429-20JC
CY7C429-20LC
CY7C429-20PC
CY7C429-20VC
CY7C429-25DC
CY7C429-25JC
CY7C429-25LC
CY7C429-25PC
CY7C429-25VC
CY7C429-25DI
CY7C429 25JI
CY7C429-25PI
CY7C429-25DMB
CY7C429-25KMB
CY7C429-25LMB
CY7C429-30DC
CY7C429-30JC
CY7C429-30LC
CY7C429-30PC
CY7C429-30VC
CY7C429-30DI
CY7C429-30JI
CY7C429-30PI
CY7C429-30DMB
CY7C429-30KMB
CY7C429- 30LMB
CY7C429-40DC
CY7C429-4OJC
CY7C429-40LC
CY7C429-40PC
CY7C429-40VC
CY7C429-40DI
CY7C429-40JI
CY7C429 40PI
CY7C429-40DMB
CY7C429-40KMB
CY7C429-40LMB
CY7C429-65DC
CY7C429-65JC
CY7C429-65LC
CY7C429-65PC
CY7C429-65VC
CY7C429 65DI
CY7C429-65JI
CY7C429-65PI
CY7C429-65DMB
CY7C429-65KMB
CY7C429-65LMB
D22
J65
155
P2I
V2I
D22
J65
L55
P2I
V2I
D22
J65
P2I
D22
K74
L55
D22
J65
L55
P2I
V2I
D22
J65
P2I
D22
K74
L55
D22
J65
155
P2I
V2I
D22
J65
P21
D22
K74
155
D22
J65
155
P2I
V2I
D22
J65
P2I
D22
K74
155
Operating
Range
Commercial
Commercial
Industrial
ID
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
oIL
ii:
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
Vrn
VILMax.
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IJX
Icc
ISBI
ISB2
los
Switching Characteristics
Parameters
Subgroups
9,10,11
9,10,11
tA
9,10,11
tRR
9,10,11
tpR
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
twc
tpw
9,10,11
9,10,11
tHwz
9,10,11
tWR
9,10,11
tSD
9,10,11
tHD
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRI'C
9,10,11
tpRT
9,10,11
tRI'R
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document #: 38-00079-G
tRC
5-44
CY7C432
CY7C433
CYPRESS
SEMICONDUCTOR
Cascadeable 4Kx 9 FIFO
Features
Functional Description-
•
•
•
•
The CY7C432 and CY7C433 are first-in
first-out (FIFO) memories offered in
6OO-mil-wide and 300-mil-wide packages,
respectively. They are 4096 words by 9
bits wide. Each FIFO memory is organized so that the data is read in the same
sequential order that it was written. Full
and Empty flags are provided to prevent
overrun and underrun. Three additional
pins are also provided to facilitate unlimited expansion in width, depth, or both.
The depth expansion technique steers the
control signals from one device to another
in parallel, thus eliminating the serial addition of propagation delays so that
throughput is not reduced. Data is steered
in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
28.5 MHz. The write operation occurs
when the write (W) signal is LOW. Read
occurs when read (R) goes Ww. The 9
data outputs go to the high-impedance
state when 'R: is mOHo
•
•
4096 x 9 FIFO buffer memory
Dual.port RAM cell
Asynchronous read/write
Higb.speed 2S.5·MHz read/write
independent of deptb/width
25.ns access time
Low operating power
- Icc (max.) = 142 mA commercial
- Icc (max.) 155 mA military
Half Full nag in standalone
Empty and Full nags
Expandable in width and depth
Retransmit in standalone
Parallel cascade minimizes
bubble.througb
5V ± 10% supply
300·mil DIP poc:kaging
300.mil SOJ packaging
TTL compatible
Three·state outputs
Pin compatible and functionally
equivalent to IDT7204
=
•
•
•
•
•
•
•
•
•
•
•
Logic Block Diagram
A Half Pull (nr:') output flag is provided
that is valid in the standalone and width
expansion configurations. In the depth expansion confJg1lration, this pin provides
the expansion out (XO) information that
is used to tell the next FIFO that it will be
activated.
In the standalone and width expansion
configurations, a WW on the retransmit
(In') input causes the FIFOs to retransmit the data. Read enable (R) and write
enable (W) must both be mOH during a
retransmit cycle, and then 'R: is used to
access the data.
The CY7C432 and CY7C433 are fabricated using advanced O.8-micron N-well
CMOS technology. Input ESD protection
is greater than 2000V and latch-up is prevented by careful layout, guard rings, and
a substrate bias generator.
Pin Configurations
DATA INPUTS
PLCCILCC
ThpVIew
(Do-Del
d"' d"8
Do
4
Do
5
6
7
XI
8
0,
J!F
00
a,
NC
Do
9
10
11
DIP
ThpVlIlW
~ >8 0" t!'
3 2 ", 323130
21
21
27
Do
0.
NC
1'IJRT
25 1111
III
7C432
7C433
24
m
22
12
13
21
14 15 1617 181920
EF
XO/FIF
Cb
Do
W
Vee
Do
Do
O.
O.
O.
Do
0,
07
Do
FrJRT
!1FI
EF
XO/RF
XI
FF
ao
Q,
a.
00
at
DATA OUTPUTS
(ao-Ool
GNO
a7
a.
a.
a.
II
0432-3
C432-1
5-45
II)
oIL
u::
CY7C432
CY7C433
f ;r,~NDUcr)R
Selection Guide
Frequency (MHz)
Access Time (ns)
MaximumOperating
Current (rnA)
7C432-25
7C433-25
28.5
25
142
I Commercial
I
Military/Industrial
7C432-30
7C433-30
25
30
135
155
7C432-40
7C433-40
20
40
125
145
7C432-65
7C433-65
12.5
65
110
130
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.) .
Storage Temperature .................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ........................ - 55°Cto +l25°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ......................... - 0.5Vto +7.0V
DC Input Voltage ....................... - 3.0Vto +7.0V
Power Dissipation ................................ 0.88W
Output Current, into Outputs (LOW) ..... . . . . . . . . . .. 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Industrial
Militaryl!]
O°Cto +70°C
Vee
5V± 10%
- 40°C to +85°C
5V± 10%
- 55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
7C432-25
7C433-25
Parameter
Thst Conditions
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
Min.
Vee = Min., IOH
= - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Com'l
Max.
2.4
7C432-30
7C433-30
Min.
0.4
2.0
Max.
2..4
Vee
Mil/lnd
Units
V
0.4
V
2.0
Vee
V
2.2
Vee
VIL
Input LOW Voltage
-3.0
0.8
-3.0
0.8
V
IJX
Input LeakageCurrent
GND~VI~Vee
-10
+10
-10
+10
loz
Output LeakageCurrent
R~ Vrn,
-10
+10
-10
+10
f.lA.
f.lA.
lee
OperatiogCurrent
135
rnA
ISB!
Standby Current
GND ~ Vo~ Vee
Com'I[3]
Vee = Max.,
lOUT = ornA
Mil/lnd[4]
All Inputs
= VIR Min.
Com'l
140
155
25
Mil/lnd
IsB2
Power-Down Current
AllInputs~ Vee
los
Output Short
CircuitCurrend5]
Vee = Max., VOUT = GND
- 0.2V Com'l
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing ioformation.
3. Icc (commercial) = 110 rnA + [(1 - 12.5).2 mAIMHz] for
1.
rnA
30
20
20
-90
-90
rnA
25
Mil/lnd
Notes:
25
rnA
4.
Icc (military) = 130 rnA + [(f -
5.
where f = the larger of the write or read operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
12.5)·2 mA/MHz] for
f~12.5MHz
2.
f~12.5MHz
where f = the larger of the write or read OPerating frequency.
5-46
CY7C432
CY7C433
~ .~
~=CYPRESS
~.iF' SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangel2] (continued)
77C432·40
77C433·40
Parameter
Description
Thst Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Min.
Vee = Min., IOH
= - 2rnA
Vee = Min., IOL = 8.0 rnA
2.0
Vee
V
MiVInd
2.2
Vee
2.2
Vee
V
-3.0
0.8
-3.0
0.8
V
-10
+10
-10
+10
-10
+10
-10
loz
Output LeakageCurrent
R~ VIH,GND~ Vo~ Vee
Icc
Operating Current
+10
!1A
!1A
Com'I[3]
125
110
rnA
MiVIm14]
145
130
Com'l
25
25
MiVInd
30
30
20
20
25
25
-90
-90
All Inputs ~ Vee - 0.2V Com'l
Power-Down Current
IsB2
MiVlnd
Vee = Max., VOUT = GND
Output Short Circuit
CurrentlS]
los
V
Vee
GND~VI~Vee
= VIH Min.
V
0.4
2.0
Input Leakage Current
All Inputs
Units
Com'l
Input LOW Voltage
Standby Current
Max.
2..4
0.4
VIL
IsB!
Min.
Max.
2.4
Irx
Vee = Max.,
lOUT = ornA
77C432·6S
77C433·6S
rnA
rnA
rnA
Capacitance [6]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
= 25°C, f
Vee = 4.5V
TA
Max.
Units
8
pF
10
pF
= 1 MHz,
Notes:
6. Tested initially aod after aoy design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
OUTP~~~R1S00&1
30pF
I
SpF
R2
INCLUDING _
JIG AND SCOPE
_
- 0432-4
R2
I _
INCLUDING
JIG AND SCOPE
(a)
Equivalent to:
3.0V
GND
333Q
333Q
-
C432-5
(b)
THEVENIN EQUIVALENT
200&1
OUTPUToo--~·",
...",·- - - 0 0
=n
fe::
ALL INPUT PULSES
R1S0
SV31
O&1
OUTPUT
2V
5-47
SSns ....
90%
10%
\.-
90%
10%
....
SSns
C432-6
CY7C432
CY7C433
~~
~= CYPRF.SS
""'!!tf!!!iiTr
SEMICONDUCTOR
Switching Characteristics
Parameters
Over the Operating Rangel7,8]
Description
7C432-25
7C433-25
7C432-30
7C433-30
Min.
Min.
Max.
35
Read Cycle Time
tA
Access Time
tRR
Read Recovery Tune
10
tpR
tLZRL9j
Read Pulse Width
25
Read LOW to Low Z
tDVRL9,lUj
Read HIGH to Data Valid
3
3
tHZRL9,lUj
Read HIGH to High Z
twc
Write Cycle Time
35
tpw
tHwzL9j
Write Pulse Width
25
Write HIGH to Low Z
10
40
30
10
tWR
Write Recovery Time
10
10
tSD
Data Set-Up Time
tHD
Data Hold Time
tMRSC
MR Cycle Time
15
0
35
tpMR
MR Pulse Width
25
tRMR
MR Recovery Time
10
tRPW
Read HIGH to MR HIGH
25
twpw
Write HIGH to MR HIGH
25
tRTC
Retransmit Cycle Time
35
tpRT
Retransmit Pulse Width
25
18
0
40
30
10
30
30
40
30
tRTR
RetransmitRecoveryTime
10
10
tEFL
MRtoEFLOW
tHFH
MRtoHFHIGH
tFFH
MRtoFFHIGH
35
35
35
tREF
Read LOW to EF LOW
25
tRFF
Read HIGH to FF HIGH
25
tWEF
Write HIGH to EF HIGH
25
tWFF
Write LOW to FF LOW
25
tWHF
Write LOW to HF LOW
tRHF
Read HIGH to HF HIGH
35
35
tRAE
Effective Read from Write HIGH
25
tRPE
Effective Read Pulse Width after EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width after FF HIGH
tXOL
Expansion Out LOW Delay from Clock
25
txOH
Expansion Out HIGH Delay from Clock
25
18
30
9.
30
30
ns
ns
ns
ns
10
ns
15
30
10
80
65
15
65
65
80
65
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
80
80
60
60
60
60
80
80
60
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
65
40
40
ns
80
65
65
40
ns
ns
30
50
50
50
35
35
35
35
50
50
35
40
Units
os
65
25
40
40
40
30
30
30
30
40
40
30
Max.
15
65
3
3
50
40
10
10
20
0
50
40
10
40
40
50
40
10
30
Min.
40
20
25
7C432-65
7C433-65
80
10
40
3
3
30
25
Max.
50
10
30
3
3
25
Min.
30
25
Noles:
7. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOu'lOH and
30-pF load capacitance, as in part (a) of AC Thst Loads, unless otherwise specified
8. See the last page of this specification for Group A subgroup testing information.
Max.
40
tRe
7C432-40
7C433-40
ns
ns
65
65
ns
ns
tHZR transition is measured at +500 mV from VOL and -500 mV
from VOH. tDVR transition is measured at the 1.5V level. 4Iwz and
tLZR transition is measured at ±100 mV from the steady state.
10. tHZR and tDvRuse capacitance loadingasinpart (a) ofACThstLoads.
5-48
CY7C432
CY7C433
Switching Waveforms
Asynchronous Read and Write
R - -...... I
~~~---t~------~~-
W~_
---------'/
)1-----«
Master Reset
1-----
)>---
tpMR - - - - - -.....
v----+--------------
C432-8
Half·FuII Flag
HALF·FULL
HALF·FULL
HALF·FULL +1
/
"f.-
-
tRHF
~
tWHF ..
I,r--
C432-9
Notes:
11. tMRSC = tpMR + tRMR·
12. W and R ~ Vrn for at least twpw or tRPR before the rising edge of
MR
5-49
o
u.
iL
R,Wl 121
W
•
II)
C432-7
----------t
~---- tMRSC[111
--------~
DATA VALID
CY7C432
CY7C433
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
R --~------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
W ---.-u
Fl' --+---""",,1
0432-10
Last Read to First Write Empty Flag
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
W--~------------~
EF
--+-+-,1
DATA OUT --I-~~~'J
C432-11
Retransmid13]
tRTC[14]
r----
tpRT
R,W
/
I---
tRTR--
C432-12
Notes:
13. BE HF and FF may change state during retransmit as a result of the
offset of the read and write pointers, but flags will be valid at tRTCo
14. tRTe = tpRT + tRTR.
5-50
CY7C432
CY7C433
Switching Waveforms (continued)
Empty Flag and Empty Boundary
DATA IN
W
•
R
U)
0
LL
u:::
EF
DATA OUT
C432-13
Full Flag and Full Boundary
w
DATA IN
tA
-:::I.
DATA OUT --------~~~D-A-JA--VA-L-ID--~------------------------------------
0432-14
5-51
«
,
CY7C432
CY7C433
·~PRFSS
SEMlCONDUClDR
Switching Waveforms
(continued)
Expansion
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
C432-15
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
C432-16
Notes:
15. ExpansiQ.n Out of device 1 (XO!) is connected to Expansion In of device 2 (XI2).
5-52
CY7C432
CY7C433
Architecture
The CY77C432133 FIFOs consist of an array of 4096 words of 9
bits each (implemented by an array of dual-JlQrt RAM cells), a
read2nter, a write pointer, control signals ~ It, xr, m, Fr,
RT. MR), and Full, Half Full, and Empty flags_
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM The cell itself enables the read and write operations to be independent of each other, which is necessary to
achieve truly asynchronous operations of the inputs and outputs.
A second benefit is that the time required to increment the read
and write pointers is much less than the time that would be required for data to propagate through the memory, which would
be the case if the memory were implemented using the conventional register array architecture.
Resetting tbe FIFO
~ power-up, the FIFO must be reset with a master reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the empty flag ~ being LOW; and both the Half
Full (HF) and Full flag (FF) resetting to IDGH. Read ~ and
write (!W) must be HIGH tRPw/twPw nanoseconds before and
tRMR nanoseconds after the rising edge of MR for a valid reset
cycle.
Writing Data to tbe FIFO
The availability of an empty location is indicated ~ the HIGH
state of the Full flag (FF). A falling edge of write (W) initiates a
write cycle. Data appearing at the inputs (Do-D8) tSD before
and tHD after the rising edge of W will be stored sequentially in
the FIFO.
The Empty flag ~ LOW-to-IDGH transition occurs tWEF
nanoseconds after the first LOW-to-HIGH transition on the
write clock of an empty FIFO. The Half Full flag (HF) will go
LOW on the fall~edge of the write clock following the occurrence of half full. HFwill remain LOW while less than one half of
the total memory of this device is available for writing. The
LOW-to-IDGH transition of the IIF flag occurs on the rising
edge of read (R). FiF is available in single device mode only. The
Full flag (FF) goes LOW on the falling edge of W during the
cycle in which the last available location in the FIFO is written,
prohibiting overflow. FF goes HIGH tRFF after the completion
of a valid read of a full FIFO.
Reading Data from tbe FIFO
The falling edge of read (R) initiates a read cycle if the Empty
flag ~ is not LOW. Data outputs (Qo-Qi!Lare in a high-impedance condition between read operations (R HIGH), when the
FIFO is empty, or when the FIFO is in the depth expansion mode
but is not the active device.
The falling edge of It during the last read cycle before the empty
condition triggers a IDGH-to-LOW transition ofm:: prohibiting
any further read operations until lWEF after a \lIlIid write.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be interrogated by the receiver and retransmitted if necessary.
The retransmit (M') input is active in the single device mode
only. The retransmit feature is intended for use when 4096 or less
writes have occurred since the previous W cycle. A LOW pulse
on :RT resets the internal read pointer to the first~hysicalloca
tion of the FIFO. The write pointer is unaffected. It and W must
both be IDGH during a retransmit cycle. Full, Half Full, and
Empty flags are governed by the relative locations of the read
and write pointers and will be updated by a retransmit operation.
After a retransmit cycle, previously read data may be reaccessed
using It to initiate standard read cycles beginning with the first
physical location.
Single Device/Widtb Expansion Modes
Sin~ device and width expansion modes are entered by connect-
!!!&.XI to-.8!.ound prior la an MR cycle. During these modes the
HF and Rf features are available. FIFOs can be expanded in
width to provide word widths greater than 9 in increments of 9.
During width expansion mode all control line inputs are common
to all devices and flag outputs from any device can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR: cycle, exIlansion Out (XO) of one device is connected to expansion in
(0) of the next device, with
of the last device connected to
XI of the first device. In the depth expansion mode the first load
(F[) input, when grounded, indicates that this part is the first
part to be loaded. All other devices must have this pin IDGH. 'Ib
enable the correct FIFO,
is pulsed LOW when the last physical location of the previous FIFO is written to and is pulsed LOW
again when the last physical location is read. Only one FIFO is
enabled for read and one is enabled for write at any given time.
All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When e~anding in depth, a composite
FF must be created by ORing the FFs~ther. Likewise, a composite ~ is created by ORing the EFs together. RF and Rf
functions are not available in depth expansion mode.
5-53
m
m
•
. r\rlPRF$
CY7C432
CY7C433
~JF SEMICONDUCTOR
Ixc
Vii
Ii
FF
9~
9
D
/
/ v/
EF
I
CY77C432
CY77C433
i'[
9,
/
9v
Vee
~
Xi
XC
I-
~
FULL
9,,,-
/ "-
-,/
EMPTY
EF
FF
CY77C432
CY77C433
i'[
1-1-
XI
XC
*
'---
FF
9,1\.
Mli
/
,v'"
EF
CY77C432
CY77C433
XI
n
• FIRST DEVICE
Figure 1. Depth Expansion
5-54
t---
C432-17
CY7C432
CY7C433
-=-~
~~NDUClDR
"
lYPical DC and AC Characteristics
NO~DSUPPLYCURRENT
NO~DSUPPLYCURRENT
1.2
./
1.0
Icc
u
2
0
0.8
::J 0.6
«
::;
a:
0
0.4
./
V
VIN= 5.0V
TA = 25°C
0.2
I
I
5,0
5.5
0.0
4,5
0.6
gj
0.4
z
-
NO~DACCESS
0.2
0.0
-55
6.0
1,2
«
0
1.1
z
1.0
............
1=
125
4,5
5.0
-----5,5
SUPPLY VOLTAGE
5
"'"
20
0
0.0
1,0
« 120
.s.
100
fi:l
a:
a:
80
o
1.2
1.0
z
w
1------ --V cc = 5,OV
0,8
0.6
6,0
-55
M
125
25
"
2.0
~
3.0
OUTPUT VOLTAGE
!z
a:~
TA = 25°C
~
0.9
0.8
4.0
-
Vcc = 5.0V
TA = 25°C
...................
40
$1.4
N
N
a:
25
~
1.6
1,3
::;
60
@
vs. AMBffiNTTEMPERATURE
$
w
80
NO~DACCESSTIME
TIME
1.4
::J
~
w
~
AMBIENTTEMPERATURE (OC)
vs. SUPPLY VOLTAGE
0
100
a:
::l
Vcc = 5.5V
VIN= 5.0V
P=20MHz
M
SUPPLY VOLTAGE
ifi
U
~
120
I-
fi:l
z
4.0
g
i;---
13 0.8
/
w
N
r---
1.0
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
~
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.2
::l
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
z
60
/
en
~
40
1=
::l
20
o
o
-
/'
U
:.:
4.0
M
II
0.0
I
Vcc = 5.0V
TA = 25°C
I
1,0
2,0
3.0
OUTPUT VOLTAGE
AMBIENTTEMPERATURE (OC)
4.0
M
~CALACCESSTIMECHANGE
NORMALIZED Icc YO. CYCLE TIME
vs. OUTPUT LOADING
1.6
1.5
/
s-
;
o 1.4
oz
Vcc=5,OV
TA = 25°C
/
1.2
1.0
o
V
./
200
13
o
/
~
gj
V
z
Vcc= 5.0V
TA = 25°C
400
1.0 ~--+--:I"'~------l
600
0.0 L-_ _.....L_ _-L_ _---I
800 1000
CAPACITANCE (pF)
10
20
30
40
CYCLE FREQUENCY (MHz)
C432-1B
5-55
•
CY7C432
CY7C433
.-~
..ifCYPRESS
- _ F SEMlCONDUClDR
Ordering Information
Speed
(ns)
25
30
40
65
Package
'JYpe
Operating
Range
Speed
(ns)
CY7C432-25DC
DI6
Commercial
25
CY7C432-25PC
PI5
CY7C432-30DC
DI6
CY7C432-30PC
PI5
CY7C432-30DI
D16
Ordering Code
Commercial
Industrial
30
CY7C432-30PI
PI5
CY7C432-30DMB
DI6
Military
CY7C432-40DC
DI6
Commercial
CY7C432-40PC
PI5
CY7C432-40DI
DI6
Industrial
CY7C432-40PI
PI5
CY7C432-40DMB
D16
Military
CY7C432-65DC
DI6
Commercial
CY7C432-65PC
PI5
CY7C432-65DI
D16
CY7C432-65PI
PI5
CY7C432-65DMB
DI6
Industrial
40
Military
65
5-56
Package
lYpe
Operating
Range
CY7C433 - 25DC
D22
Commercial
CY7C433-25JC
J65
CY7C433 - 25LC
L55
Ordering Code
CY7C433-25PC
P2I
CY7C433-25VC
V2I
CY7C433 - 30DC
D22
CY7C433-3OJC
J65
CY7C433 - 30LC
L55
CY7C433-30PC
P2I
CY7C433-30VC
V2I
CY7C433-30DI
D22
CY7C433 - 30JI
J65
CY7C433 - 30PI
P2I
CY7C433-30DMB
D22
CY7C433 - 30KMB
K74
CY7C433- 30LMB
L55
CY7C433-40DC
D22
CY7C433-40JC
J65
CY7C433-40LC
L55
CY7C433-40PC
P2I
CY7C433-40VC
V2I
CY7C433-40DI
D22
CY7C433-40JI
J65
CY7C433-40PI
P2I
CY7C433-40DMB
D22
CY7C433-40KMB
K74
CY7C433-40LMB
L55
CY7C433-65DC
D22
CY7C433-65JC
J65
CY7C433-65LC
L55
CY7C433-65PC
P2I
CY7C433-65VC
V2I
CY7C433-65DI
D22
CY7C433-65JI
J65
CY7C433-65PI
P2I
CY7C433-65DMB
D22
CY7C433 - 65KMB
K74
CY7C433 - 65LMB
L55
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C432
CY7C433
z
~~PR£SS
~, SEMICONDUcroR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VJH
VILMax.
IJX
Icc
IsBl
IsB2
los
Switching Characteristics
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Parameters
Subgroups
9,10,11
9,10,11
9,10,11
tRR
9,10,11
tpR
9,10,11
tlZR
9,10,11
tOVR
9,10,11
tHZR
9,10,11
twc
9,10,11
tpw
9,10,11
tHWZ
9,10,11
tWR
9,10,11
tso
9,10,11
tHO
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRrC
9,10,11
tPRI"
9,10,11
tRI"R
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document#: 38-00109-A
tRC
tA
5-57
•
CY7C439
CYPRESS
SEMICONDUCTOR
Bidirectional 2K x 9 FIFO
Features
Functional Description
• 2048 x 9 FIFO buffer memory
The CY7C439 is a 2048 x 9 FIFO memory
capable of bidirectional operation. As the
term first-in first-out (FIFO) implies, data
becomes available to the output port in
the same order that it was presented to the
input port. There are two pins that indicate the amount of data contained within
the FIFO block-M (Empty/FlllI) and
lIP (Half Full). These pins can be decoded to determine one of four states. 1Wo
9-bit data ports are provided. The direction selected for the FIFO determines the
input and output ports. The FIFO direction can be programmed by the us;~
time through the use of the reset pin
and the bypass/direction pin
~ .
There are no control or status registers on
the CY7C439. making the part simple to
• Bidirectional operation
• High-speed 285·MBz asyncbronous
reads and writes
• Simple control interrace
• Registered and tranaparent bypass
modes
• Flags indicate Empty, FuJI, and Half
Full conditions
• SV:t 10% supply
• Available In 3OG-mil DIP, PLCe. LCe.
and SOJ packages
• TfL compatible
use while meeting the needs of the majority of bidirectional FIFO applications.
FIFO read and write operations may occur simultaneously. and each can occur at
up to 28.5 MHz. The port designated as
the write port drives its strobe pin (S'fBX.
X = A or B) LOW to initiate the write
operation. The port designated as the
read port drives its strobe pin LOW to
initiate the read operation. Output port
pins go to a high-impedance state when
the associated strobe pin is IDOH. All
normal FIFO operations require the bypass control pin (BYPX. X = A or B) to
remain HIGH.
In addtion to the FIFO. two other data
paths are provided; registered bypass and
transparent bypass. Registered bypass can
be considered as a single-word FiFO in the
reverse direction to the main FIFO. The
Pin Configurations
Logic Block Diagram
PLCCILCC
TopV\ew
STBB
III'PII
At At AoNCAt At A7
A,
Ao
!'i'P1\
GND
BI'PB
~
PORTA .._
Ao-At
So
NC
.......
B,
TRANSPARENT
43 2.1.323130
29'
5
6
1
8
7C439
9
10
23
11
22
12
21
13
14151611181920
u
:.
v..
~.
BYPASS
At
~:
NC
~
QR
STBB
RF
Be
Ba BaS. NC Ba Ba IIr
C439-2
DIP
ThpV\ew
FLAG
l-_-+-+-.lC.ONTROL
Ao
At
At
A7
At
ElF
Ao
At
A,
Ao
!'i'P1\
~
GND
III'PII
Voo
QR
~
204809
FIFO
STBB
So
RF
B,
Ba
B7
Ba
Ba
Be
S.
C43II-l
Ba
C439-3
Selection Guide
7009-25
7009·30
28.5
2S
7009-40
20
2S
30
140
170
40
130
160
Frequency (MHz)
Maximum Access Time (ns)
Maximum 3Serating
Current(mA
I Commercial
I
147
Military
5-58
7009·65
12.5
65
115
145
·
------
~rlPRESS
-?
CY7C439
SEMICONDUCTOR
Functional Description (continued)
bypass register provides a means of sending a 9-bit status or control
word to the FIFO-write port. The bypass data available pin (BDA)
indicates whether the bypass register is full or empty. Thedirection
of the bypass register is always opposite to that of the main FIFO.
The port designated to write to the bypass register drives its bypass
control pin (BYPX) LOW. The other port detects the presence of
data by monitoring BDA and reads the data by driving its bypass
control pin (BYPX) LOW. Register~ass operations require
that the associated FIFO strobe pin (STBX) remains HIGH. Registered bypass operations do not affect data residing in the FIFO,
or FIFO operations at the other port.
Transparent bypass provides a means of transferring a single word
(9 bits) of data immediately in either direction. This feature allows
the device to act as a simple 9-bit bidirectional buffer. This is useful
for allowing the controlling circuitry to access a dumb peripheral
forcontrol/programminginformation.
For transparent bypass, the port wishing to send immediate data to
the other side drives both its bypass and its strobe pins LOW simultaneously. This causes the buffered data to be driven out of the otherport. On-chip circuitry detects conflicting use of the control pins
and causes both data ports to enter a high-impedance state until
the conflict is resolved.
Additionally, a Test mode is offered on the CY7C439. This mode
allows the user to load data into the FIFO and then read it back out
of the same port. Built-In Self Test (BIST) and diagnostic functions
can take advantage of these features.
The CY7C439 is fabricated using an advanced 0.81-1 N-well CMOS
technology. Input ESD protection is greater than 2000V and latchup is prevented by reliable layout techniques, guard rings, and a
substrate bias generator.
•
In
Maximum Ratings
(Above which the useful life maybe impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . . . - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Power Dissipation ................................ l.OW
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ > 200 rnA
Operating Range
Range
Commercial
Military!1]
Signal
Name
I/O
Description
A(s-O)
I/O
Data Port Associated with BYPA and STBA
B(S-O)
I/O
Data Port Associated with BYPB and STBB
BYPA
I
Registered Bypass Mode Select for A Side
BYPB
I
Registered Bypass Mode Selectr for B Side
BDA
0
Bypass Data Available Flag
STBA
I
Data Strobe for A Side
STBB
I
Data Strobe for B Side
0
Encoded EmptyIFull Flag
HF
0
Half Full Flag
MR
I
Master Reset
O°Cto +70°C
Vee
5V ± 10%
- 55°C to + 125°C
5V+ 10%
Notes:
1. TA is the "instant on" case temperatnre.
Pin Definitions
ElF
Ambient
Temperature
5-59
ou..
u::
~PRFSS
~rs~CONDUCI'OR
Electrical Characteristics
CY7C439
Over the Operating Rangef2)
7C439-25
Description
Parameters
lest Conditions
Min.
VOH
Output HIGH
Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW
Voltage
Vee = Min., IOL = 8.0 rnA
Vru
Input HIGH
Voltage
IJX
Input Leakage
Current
loz
Output Leakage
Current
Operating
Current
Standby Current
ISBl
Power-Down
Current
ISB2
0.4
2.2
2.4
0.4
7C439-65
Min. Max. Units
2.4
V
0.4
0.4
V
Vee
2.2
Vee
2.2
Vee
V
- 3.0
0.8
Vee
0.8
2.2
-3.0
Vee
0.8
2.2
2.2
-3.0
Vee
2.2
- 3.0
Vee
0.8
V
V
GND~VI5..Vee
-10
+10
-10
+10
-10
+10
-10
+10
JlA
STBX2. Vru, GND ~ Vo
-10
+10
-10
+10
-10
+10
-10
+10
JlA
115
145
rnA
~Vee
Com'I(3)
Mil(4)
Vee = Max.,
lOUT = ornA
147
140
170
130
160
Aliinputs = VruMin. Com'l
Mil
40
40
45
40
45
Aliinputs Vee - 0.2V Com'l
Mil
20
20
25
20
25
-90
- 90
-90
Output Short
Vee = Max., VOUT = GND
CircuitCurrentl5)
los
2.4
Mil
Input LOW
Voltage
7C439-30
7C439-40
Max. Min. Max.
Min.
2.4
Com'l
VIL
lee
Max.
40
rnA
45
20
rnA
25
- 90
rnA
Capacitance (6)
Parameters
qN
CoUT
Description
lest Conditions
Max.
Units
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
8
pF
Vee = 4.5V
10
pF
Notes:
2. See the last page of this specification for Group Asubgroup testing information.
3. Icc (commercial] = 115 rnA + [(f - 12.5)' 2 mNMHz] for
where f
4.
f~12.5MHz
= the larger of the write or read
5.
operating frequency.
6.
Icc (military) = .145 rnA + [(f - 12.5)' 2 mNMHz] for
_ f~12.5MHz
where f = the larger of the write or read
operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thstedinitially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveform
Rl5000
R1Sooo
OUTPUT
SV31
OUTP~~31
30pF
SPFI
R2
333&1
I _
INCLUDING
JIG AND SCOPE
INCLUDING _
JIG AND SCOPE
-
(a)
Equivalent to:
ALL INPUT PULSES
R2
333&1
_
0439-4
(b)
THEvENIN EQUIVALENT
2000
OUTPUT~O-----N.~.
____-402V
5-60
~ns
C439-5
~
,~PRE&S
.
~
F
CY7C439
SEMlCONDUcroR
Switching Characteristics Over the Operating Rangd7,8]
7C439-25
Description
Parameters
Min.
Max.
7C439-30
Min.
Max.
40
35
7C439-40
Min.
Max.
50
7C439-65
Min.
Max.
Units
tRC
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
10
10
10
15
ns
tpR
tLZR[9,lO]
Read Pulse Width
25
30
40
65
ns
Read LOW to Low Z
3
3
3
3
ns
tDVR[9,1O]
Read HIGH to Data Valid
3
3
3
3
tHZR[9,1O]
Read HIGH to High Z
25
30
18
40
20
ns
80
65
ns
30
25
ns
ns
twc
Write Cycle Time
35
40
tpw
Write Pulse Width
25
30
40
65
ns
tHWZ[9,1O]
Write HIGH to Low Z
10
10
10
10
ns
tWR
Write Recovery Time
10
10
10
15
ns
tSD
Data Set-Up Time
15
18
20
30
ns
tHD
Data Hold Time
0
0
0
10
ns
tMRSC
MR Cycle Time
35
40
50
80
ns
tpMR
MR Pulse Width
25
30
40
65
ns
tRMR
MR Recovery Time
10
10
10
15
ns
tRPS
STBXHIGH to MR HIGH
25
30
40
65
ns
tRPBS
BYPA to MR HIGH
10
10
15
20
ns
tRPBH
BYPAHold after MR HIGH
0
0
0
0
tBDH
MR LOW to BDAHIGH
35
10
50
80
ns
40
10
50
ns
80
15
10
ns
ns
tBSR
STBXHIGH to BYPALOW
tEFL
MRtoEIFLOW
35
40
50
80
ns
tHFH
MRtoHFHIGH
35
40
50
80
ns
tBRS
BYPXHIGH to STBX LOW
tREF
STBXLOW to ElF LOW (Read)
25
30
35
60
ns
tRFF
STBX HIGH to ElF HIGH (Read)
25
30
60
ns
tWEF
STBX HIGH to ElF HIGH (Write)
25
30
35
35
60
ns
tWFF
STBX LOW to ElF LOW (Write)
25
30
35
60
ns
tBDA
BYPXHIGH to BDALOW (Write)
25
30
35
60
ns
tBDB
BYPX HIGH to BDA HIGH (Read)
25
30
35
60
ns
tBA
BYPX LOW to Data Valid (Read)
30
40
60
ns
tBHZ[9,1O]
BYPX HIGH to High Z (Read)
18
30
20
25
30
ns
tTSB
STBXHIGH to BYPXLOW Set-Up
10
tTBS
STBXLOW after BYPXLOW
0
tTSN
tTSO[9,1O]
STBXHIGH Recovery Time
10
tTBN
BYPXHIGH Recovery Time
tTBD
BYPXHIGH to Data High Z
10
10
10
10
0
18
0
10
10
15
25
ns
ns
30
25
10
20
0
ns
15
10
20
10
10
5-61
10
ns
15
10
10
18
STBXHIGH to Data High Z
15
10
ns
ns
30
ns
•
--
.~
JF SEMICONDUCTOR
CY7C439
='iiiCYPRESS
-
Switching Characteristics
Over the Operating Rangd7,8] (continued)
7C439-25
Parameters
tTPD[9,1O]
Description
Min.
Max.
STBXWW to Data Valid
20
7C439-30
Min.
7C439-40
Max.
Min.
20
Max.
7C439-65
Min.
Max.
Units
30
55
ns
tDL
TransparentPropagationDelay
20
20
25
30
ns
tESD[9,1O]
STBXLOW to High Z
18
20
25
30
ns
tEBD[9,1O]
BYPX LOW to High Z
18
20
25
30
ns
tEDS
STBXHIGHtoLowZ
18
20
25
30
ns
tEDB
BYPX HIGH to Low Z
18
20
25
30
ns
tBPW
BYPXPulse Width (Trans.)
25
30
40
65
ns
tTSP
tBLZ[9,lO]
STBXPulse Width (Trans.)
20
20
30
55
ns
BYPX LOW to Low Z (Read)
10
10
10
10
ns
tBDV
BYPXHIGH to Data Invalid (Read)
3
3
3
3
tWHF
STBXLOW to HF LOW (Write)
35
40
50
80
ns
tRHF
STBXHIGH to HF HIGH (Read)
35
40
50
80
ns
tRAE
Effective Read from Write HIGH
60
ns
tRPE
Effective Read Pulse Width after ElF
HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width after ElF
HIGH
25
30
40
65
ns
lBSU
Bypass Data Set-Up Time
15
18
20
30
ns
tBHL
Bypass Data Hold Time
0
0
0
10
ns
25
25
30
35
30
25
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, and output loading ofthe specified IOrJIOH and
30-pF load capacitance as in part (a) of AC Test Loads, nnless otherwise specified.
8. See the last page ofthis specification for Group A subgroup testing information.
40
30
ns
65
35
ns
60
ns
9.
tDVR, tBDV, tHZR, tTBD, tBHz, tEBD, tESD, tTSD, tLzR, tHwz, and tBLZ
use capacitance loading as in part (b) of AC Test Loads.
10. tHZR, tTBD, tBHZ, tEBD, tESD, and tTSD transition is measured at
+500 m V from VOL and - 500 m V from VOH. tDVR and tBDV transition is measured at the 1.5V level. tLZR, tHwz, and tBLZ transition is
measured at ± 100 m V from the steady state.
Switching Waveforms
Asynchronous Read and Write Timing Diagram
STBBI11]
READ
PORT B
-------l(
2 '" ~tWR
~---------------twc --------------~~
STBB[11]
i
PORT A
--------1(
WRITE
K"" '"
DATA VALID
---------/
:t--------« . . .___DA_I_A_V_A_L1_D_....;)--
5-62
C439-6
~
~~
-=-,
CY7C439
='=CYPRESS
SEMICONDUCTOR
Switching Waveforms
(continued)
Master Reset Timing Diagram
•
0439-7
Half-Foil Flag Timing Diagram[12]
HALF FUll + 1
HALF FULL
~,
HALF FULL
Ir-
tRHF ....
;V
.. tWHF ....
i'\.
./
rC439-8
Last Write to First Read Empty/Fnll Flag Timing Diagram[12]
lAST WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
0439-9
Notes:
11. Direction selected Port A to Port B.
12. Direction selected as A to B.
5-63
;~
CY7C439
" ; . CYPRESS
_ , SEMICaIDUCTOR
Switching Waveforms (continued)
LastRead to First Write Empty/FuU Flag Timing Diagram[12j
LAST READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
E
-
~
....
....
tREF{
tWEF
....
/E
-tA ....
DATA OUT
C439-10
Empty/Full FIagand Read Bubble-Tbrough Mode Timing Diagram[12j
DATA IN
(PORTA)
ElF
EMPTY
DATA OUT
(PORTS)
DATA VALID
C439-11
Empty/FullFIagand Write Bubble-Througb Mode TimingDiagram[12j
,,~--FULL
DATA IN
(PORTA)
DATA OUT
(PORTS)
DATA VALID
DATA VALID
0439-12
5-64
·--S--
CY7C439
·JreYPRESS
_ , SEMICONDUCIDR
Switching Waveforms (continued)
Registered Bypass Read Timing Diagram[13]
tBSR
-----1,...--
C439-13
Registered Bypass Write Timing Diagram[14]
tBSU
I..
·+1·...
tBPW - - - - -....
~
t,------C439-14
lransparent Bypass Read Timing Diagram[15]
'7~~~--------~ ~~---------~sP -------r::::::::~~~::::~-~~
------~.~--~----------tBPW------+---~~/--------~
rPORTA
tTPD
VALID INPUT 1
VALID INPUT 2
PORTB
VALID OUTPUT 2
C439-15
Notes:
13. Port B selected to read bypass register (FIFO direction Port B to
PortA).
14. Port A selected to write bypass register (FIFO direction Port B to
PortA.
15. Diagramsbows traosparent bypass initiated by Port A. Times are identical if initiated by Port B.
5-65
•
~
5
.~PRF.§
""=!!!!!lilT'
CY7C439
SEMICONDUClDR
Switching Waveforms (continued)
lest Mode Timing Diagram
C439-16
Exception Condition Timing Diagram[15j
~~
__________________________________
~;I
--------------------------;1
,!of
~,
I--
.. IESD ..
~
I- IEDB
'I'\..
IDATAB
VALID OUTPUT
IEBD ...
....
IEDS •
HIGHZ
..
V
I"
VALID OUTPUT
C439-17
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM array,
a read pointer, a write pointer, data switching circuitry, buffers, a
bypassregister, control signals (STBA, STBB, BYPA, BYPB, MR),
and flags (ElF, HF, BDA).
Operation at Power-On
~n power-up, the FIFO must be reset ~t~ ~ ~aster Re.set
(MR) cycle. During an MR cycle, the user can InItialIZe the deV1c~
by choosing the direction of FIFO operation (see Table 1). There IS
a minimum LOW period for MR, but no maximum time. The state
of BYPA is latched internally by the rising edge ofMR and used to
determine the direction of subsequent data operations.
Resetting the FIFO
Duringthe reset conditlon~e Table l1.the FIFO three-states the
data ports, sets BDA and HF HIGH, ElF LOW, and ignores the
state of BYPA/B and STBA/B. The bypass registers are initialized
to zero. During this time the user is expected to set the direction of
the FIFO by driving BYPAHIGH or LOW, andBYPB, STBA, and
STBB HIGH. If BYPA is LOW (selecting direction B>A), the
FlFOwili then remain in aresetcondition until the user terminates
theresetoperstion by driving BYPAHIGH. If BYPA is HIGH (selectingdirectionA> B), thereset condition terminatesafterthe ris-
ing edgeofMR. The entire reset phase can be accomplished in one
cycle time of tRe.
FIFO Operation
The operation of the FIFO requires only one control pin per port
(STBX). The user determines the directio~ of the FIFO data flow
by initiating an MR cycle (see Table 1), WhICh cleru;; the FlFC? and
bypass register and sets the data path and control SIgnal multIplexers. The bypass register is configured in the opposite direction to
the FIFO data flow. The FIFO direction can be reversed at any
time by initiating another MR cycle. Data is written into the FIFO
on the rising edge of the input, STBX, and read from the FIFO by
a low level at the output, STBX. The two ports are asynchronous
and independent. If the user attempts to read the FIFO when it is
empty, no action takes place (the read pointer is not incremented)
until the other port writes to the FIFO. Then a bubble-through
read takes place, in which the read strobe is generated internally
and the data becomes available at the read port shortly thereafter
if the read strobe (STBX) is still LOW. Similarly, for an attempted
write operation when the FIFO is full, no internal operation takes
place until the other port performs a read operation, at which time
the bubble-through write is performed if the write strobe (STBX)
is still LOW.
5-66
CY7C439
Registered Bypass Operation
Theregistered bypass feature provides a means of transferring one
9-bit word of data in the opposite direction to normal data flow
without affecting either the FIFO contents orthe FIFO write operations at the other port. The bypass register is configured during
resetto provide a data path in the opposite direction to that of the
FIFO (see Table 1). For example, if port A is writing data to the
FIFO (hence port B is reading data from the FIFO) then BYPB is
used to write to the bypass register at port B, and BYPA is used to
read a single word from the bypass register at port A. The bypass
data available flag (BDA) is generated to notify port A that bypass
data is available. BDA goes true on the trailing edge of the BYPX
write operation and false upon the trailing edge of the BYPXread
operation.
Data is written on the rising edge of BYPX into the bypass register
for later retrieval by the other port, regardless of the state ofBDA.
The bypass register is read by a low level at BYPx, regardless of the
state of BDA.
1hmsparent Bypass Operation
The transparent bypass feature provides a means of sending immediate data "around" the FIFO in either direction. The FIFO contents are not affected by the use of transparent bypass, but the control signals for transparent bypass are shared with those of the
normal FIFO operation. Hence there are limitations on the use of
transparent bypass to ensure that data integrity and ease of use are
preserved. The port wishing to send immediate data must ensure
that the other port will not attempt a FIFO read orwrite during the
transparent bypass cycle. If this isnotpossible, registered bypass or
external circuitry should be used.
Thansparent bypass mode is initiated by bringing both BYPA and
STBALOW together. Care should be taken to observe the following constraints on the timing relationships. Since STBA is used for
normal FIFO operations, it must follow BYPAfaIling edge b.Y.!ms
to prevent erroneous FIFO read orwrite operations. Since BYPA
is used alone to initiate registered bypass read and write, it is internally delayed before initiating registered bypass. IfSTBA falls during this time, delay registered bypass is averted, and transparent
bypass is initiated. Identical arguments apply to BYPB and STBB.
Ifa transparent bypass sequence is successfully accomplished, data
presented to the initiating port (portAin the above discussion) will
be buffered to the other (port B) after tDL. Either port can initiate
a transparen.!b~ojJeration at any time, but if the control signals (STBNE, BYPA/B) are in conflict (exception condition), internal circuitry will switch both ports to high-impedance until the
conflict is resolved.
'lest Mode Operation
The Thst mode feature provides a means of reading the FIFO contents from the same port that the data was written to the FIFO.
This feature is useful for Built-In Self Thst (BIST) and diagnostic
functions. Th utilize this capability, initialize FIFO direction A to B
and load data into the FIFO using normal write timing. In order to
read data back out of the same port (port A), initiate a MR cycle
with both BYPA and BYPB LOW (see Thst Mode Timing diagram).After completing the cycle, the data can be read out of port
Ain FIFO order. Data will be inverted when read out of the device.
Also, flags are not valid when reading data.
Flag Operation
There are two flags, Empty/Full (ElF) and Half Full (HF), which
are used to decode four FIFO states (see Table 4). The states are
empty, 1-1024 locations full, 1025-2047 locations full, and full.
Note that two conditions cause the EtFpin to go LOW, Empty and
Full, hence both flag pins must be used to resolve the two conditions.
Thble 1. FIFO Direction Select 'fruth Thble
MR
BYPA
BYPB
STBA
STBB
1
X
X
X
X
NormalOperation
FIFO Direction A to B, Registered Bypass Direction B to A
..s..s0
Action
1
1
1
1
O
1
1
1
FIFO Direction B to A, Registered Bypass Direction A to B
X
X
X
X
Reset Condition
Thble 2. Bypass Operation 'fruth Thble
Action
Direction
STBA
BYPA
STBB
BYPB
~B
1..[
1
1
Normal FIFO Operations, Write at A, Read at B
~B
1
1..[
1..[
1..[
1
Normal FIFO Read at B, Bypass Register Read at A
~B
1..[
1..[
1
1
1..[
Normal FIFO Write at A, Bypass Register Write at B
BtA
1
1
Normal FIFO Operations, Write at B, Read at A
BtA
1
1..[
1..[
1..[
1
Normal FIFO Write at B, Bypass Register Write at A
BtA
1..[
1
1
1..[
Normal FIFO Read at A, Bypass Register Read at B
X
0
0
1
1
No FIFO Operations, Thansparent Data A to B
X
1
1
0
0
No FIFO Operations, Thansparent Data B to A
5-67
•
I I)
o
u..
ii:
CY7C439
Thble 3. Exception Conditions: Operation Not Defined
Direction
STBA
BYPA
STBB
BYBP
X
0
1
0
0
Data Buses High Impedance
X
1
0
0
0
Data Buses High Impedance
X
0
0
0
0
Data Buses High Impedance
X
0
0
1
0
Data Buses High Impedance
X
0
0
0
1
Data Buses High Impedance
Action
Thble 4. Flag ll-uth Thble
ElF
HF
0
1
Empty
1
1
1-1024 Locations Full
1
0
1025 - 2047 Locations Full
0
0
Full
State
'IYpical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.2 ....--.....- - , . . . - - - , - - - - ,
1.4
8
a
1 .2
~ 1.0
~
::;;
cc
cc
oz
~
0.4 L-_.....l..._ _L - _ - L _ - - - l
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
0.0
-55
M
«
::;;
z
125
~ ......
1.0
0.9
0
N
::J
1.2
«
::;;
cc 1.0
z
0.8
0.8
TA = 25°C
0.7
4.5
5.0
40
~
30
5.5
SUPPLY VOLTAGE M
k.
" "'- "'-
:J
5l
t:;
t:;
o
20
Vee= 5.0V
TA = 25°C
10
0
0.0
1.0
6.0
2.0
""
3.0
'"
4.0
OUTPUT VOLTAGE M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
<"
140
E
;::- 120
.:f- 1.4
ill
4.0
25
z
~ 100
a
1.1
cc
0
gj
o
a.
1.6
.:f-
::J
50
NORMALIZEDtA
vs. AMBIENT TEMPERATURE
1.2
N
60
!zill
AMBIENT TEMPERATURE (0C)
1.3
ill
Vee = 5.5V
VIN =5.0V
f=20MHz
0.8
NORMALIZED tA
vs. SUPPLY VOLTAGE
a
-
ill
N
N
l
cc
a
ill
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
----
0.6
-55
25
cc
~
Vee = 5.0V
/
80
~
60
t:;
a.
40
5
20
/
f-
o
125
AMBIENT TEMPERATURE (0C)
5-68
5:.::
"
/
i/
0.0
/
Vee = 5.0V
TA=25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE M
4.0
--:- ~
~=CYPRESS
CY7C439
~F SEMICONDUCTOR
lYPical DC and AC Characteristics (continued)
NORMALIZED tA CHANGE
vs.OUTPUTLOADING
NORMAUZED Icc vs. CYCLE
FREQUENCY
1.3
1.6
1.5
o 1.1
~
0 1.4
L
w
::;
1.3
«
:;
N
I
II:
0
z
_
1.2
1.1
1.0
o
Vee = 5.0V
TA = 25°C
I
I
400
/
w 0.9
N
::;
25
30
40
65
Package
1YPe
P21
J65
V21
D22
L55
P21
J65
V21
D22
L55
D22
L55
K74
P21
J65
V21
D22
L55
D22
L55
K74
P21
J65
V21
D22
L55
D22
L55
K74
0.7
/
z
0.5
Vee = 5.0V
TA = 25°C
0.0
600
800 1000
10
20
30
CYCLE FREQUENCY (MHz)
Ordering Information
Ordering Code
CY7C439-25PC
CY7C439-25JC
CY7C439-25VC
CY7C439-25DC
CY7C439-25LC
CY7C439-30PC
CY7C439-3OJC
CY7C439-30VC
CY7C439-30DC
CY7C439-30LC
CY7C439-30DMB
CY7C439- 30LMB
CY7C439-30KMB
CY7C439-40PC
CY7C439-4OJC
CY7C439-40VC
CY7C439-40DC
CY7C439-40LC
CY7C439-40DMB
CY7C439-40LMB
CY7C439-40KMB
CY7C439-65PC
CY7C439-65JC
CY7C439-65VC
CY7C439-65DC
CY7C439-65LC
CY7C439-65DMB
CY7C439-65LMB
CY7C439-65KMB
/1'
0
CAPACITANCE (pF)
Speed
(ns)
I.....
V
V
«
:;
II:
--1/
200
0
0
v
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
5-69
40
•
I I)
o
LL.
u:::
k .~
-= CYPRESS
_ , SEMICONDUCTOR
CY7C439
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIR
VILMax.
IJX
Icc
ISBl
IsB2
los
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
tRC
tA
tRR
tpR
tLZR
toVR
tHZR
twc
tpw
tHWz
tWR
tso
tHO
tMRSC
tpMR
tRMR
tRPS
tRPBS
tRPBH
tBOH
tBSR
tEFL
tHFH
tBRS
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
Subgroups
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, 1Q, 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
1),10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10; 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9; 10, 11
9,10,11
tWPF
tBSU
tBHL
tBOA
taOB
tBA
tBHZ
tTSB
tTBS
tTSN
tTSO
tTBN
tTBO
ttpo
tOL
tESO
tEBO
tEOS
tEOB
tBPw
tTSP
tBLZ
tBOY
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, 1Q, 11
9,10,11
9,10,11
9,10,11
9, Hl, 11
9,10,11
9,10,11
9,10,11
Document #: 38-00126-C
5-70
CY7C441
CY7C443
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Clocked 512 x 9, 2K x 9 FIFOs
Features
Functional Description
• 512 x 9 (CY7C441) and 2,048 x 9
(CY7C443) FIFO buffer memory
• IDgh-speed 70-MHz operation
• Supports free-running 50% duty cycle
clock inputs
• Empty, Almost Empty, and Almost
Full status Oags
• Fully asynchronous and simultaneous
read and write operation
• Width expandable
• Independent read and write enable
pins
• Center power and ground pins for
reduced noise
• Available in 300-mil28-pin DIP,
PLCC, LCe, and SOJ packages
• Proprietary 0.8" CMOS tl!chnology
• TTL compatible
The CY7C441 and CY7C443 are highspeed, low-power, first-in first-out (FIFO)
memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The
CY7C441 has a 512 word by 9 bit
memory array, while the CY7C443 has a
2048 word by 9 bit memory array. These
devices provide solutions for a wide varieo/ of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and communications buffering.
Both FIFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running 50% duty cycle
clock (CKW) and a write enable pin
(ENW). When nNW is asserted, data is
written into the FIFO on the rising edge
of the CKW signal. While nNW is held
active, data is continually written into the
FIFO on each CKW cycle. The output
port is controlled in a similar manner by a
free-runninMNa:)CIOCk (Cm) and a read
enable pin
. The read (CKR) and
write (CKW) clocks may be tied together
Logic Block Diagram
CKW
for single·c1ock operation or the two doclcs
may be run independently for asynchronous read/wrlte applications. Qock frequencies up to 71.4 MHz are acceptable.
The CY7C441 and CY7C443 docked
FIFOs pr!Mde two status flag pins (Fl
and F2). These flags are decoded to determine one of four states: Empty, Almost
Empty, Intermediate, and Almost Full
(Table 1). The flags are synchronous i.e.,
change state relative to either the read
clock (Cm) or the write clock (CKW).
The Empty and Almost Empty states are
updated exclusively by the
while Almost Full is updated exclusively by CKw.
The synchronousflagarchi~ture guarantees that the flags maintain their status for
some minimum time. This time is equal to
approximately one cycle time.
The CY7C441 and the CY7C443 use
center power and ground for reduced
noise. Both configurations are fabricated
using an advanced 0.8" N-well CMOS
technology. InputESD protection is greater than 2001 V. and latch-up is prevented
by reliable layout techniques, guard rings,
and a substrate bias generator.
em
Pin Conngurations
PLCCILCC
Top View
00-.
0,
5
CKW
6
7
EIiIW
vee
Vss
Fl
F2
He
2001V
(per MIL-STD-883, Method 3015)
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
Industrial
- 40°C to +85°C
SV± 10%
Militaryll]
- 55°Cto +l25°C
5V± 10%
Range
Commercial
Pin Definitions
Signal Name
> 200 rnA
I/O
Description
Do-s
I
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge)
writes data (Do - Ds) into the FIFO's memory
00-8
0
DataOutputs: whentheFIFOisnotemptyandENRisactive,CKR(risingedge)
reads data (00 - Os) out of the FIFO's memory
ENW
I
Enable Write: enables the CKW input
ENR
I
Enable Read: enables the CKR input
CKW
"}
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and
updates the Almost Full flag state
CKR
I
ReadClock: the rising edge clocks data out of the FIFO when El:'lR is LOW and
updates the Almost Empty and Empty flag states
Fl
0
Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in
(see Table 1)
F2
0
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in
(see Table 1)
MR
I
Master Reset: resets the device to an empty condition
Note:
1. TA is the "instant on" case temperature.
5-72
--==--.
~~
'iii CYPRESS
~F
CY7C441
CY7C443
PRELIMINARY
SEMlCONDUCfOR
Electrical Characteristics Over the Operating Rangel2]
Parameters
Description
7C441-14
7C443-14
Min. Max.
Thst Conditions
7C441-20
7C443-20
Min. Max.
7C441-30
7C443-30
Min. Max. Units
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
VIR
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
2.2
Input LOW Voltage
Input Leakage
Current
-3.0
Vee
0.8
-3.0
Vee
0.8
-3.0
Vee
0.8
V
VIL
IJX
-10
+10
-10
+10
-10
+10
fAA
los[3]
Output Short
Circuit Current
OperatingCurrent
leel4]
2.4
2.4
0.4
Vee = Max.,
2.4
0.4
0.4
2.2
2.2
GND~VI~Vee
-90
Vee = Max., VOUT = GND
Vee-Max.,
lOUT = ornA
ICom'l
I Mil/lnd
-90
-90
140
160
V
V
V
rnA
120
140
100
130
rnA
rnA
Capacitance IS]
Parameters
CIN
Description
InputCapacitance
Thst Conditions
TA = 25°C,f= 1 MHz,
Max.
10
Units
pF
Vee = 5.0V
Note.:
2. See the last page ofthis specification for Group A subgroup testing information.
3. Thst no more than one output at a time and do not test any output for
more than one second.
4.
Input signals switch from OV to 3V with a rise/fall time of less tban 3
os, clocks and clock enables switch at maximum frequency (±MAx),
while data inputs switch at fMAxJ2. Outputs are unloaded.
5. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and WaveformI6,7]
R15000
OUTP~~31
CLI
INCLUDING _
JIG AND SCOPE
Equivalent to:
ALL INPUT PULSES
~
10%
R2
.s.3ns
_ 333Q
C441-4
C441-5
THEVENIN EQUIVALENT
2000
OUTPUT~O-----N.~.____-402V
5-73
•
#';~PRFSS
~, SEMICONDUCTOR
Switching Characteristics
CY7C441
CY7C443
PRELIMINARY
Over the Operating Rangel2,8]
7C441-14
7C443-14
Parameters
Min.
Description
Max.
7C441-20
7C443-20
Min.
Max.
7C441-30
7C443-30
Min.
Max.
Units
tCKW
Write Clock Cycle
14
20
30
ns
tcKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
Clock LOW
6.5
9
12
tA
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After Read,Mtite mGH
0
0
0
ns
tSD
DataSet-Up
7
9
12
ns
tHD
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
tFD
Flag DeIay
tSKEWl[9]
Opposite Clock After Clock
14
20
30
ns
tSKEW2[lO]
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
toHMR
Data Hold FromMR LOW
0
0
0
ns
tMRR
Master Reset Recovery (MR HIGH Set-Up to First
Enabled Write/Read)
14
20
30
ns
tMRF
MR mGH to Flags Valid
14
20
30
ns
tAMR
MRmGH to Data Outputs LOW
14
20
30
ns
10
10
Note.:
6. CL = 30 pF for all AC parameters.
7. All AC measurements are referenced to 1.5V.
8. "Iest conditions assume signal transition time 00 ns or less, timing reference levels of 1.5Y, and output loading as shown in the AC "Iest
Loads and Waveforms and capacitance as in note 6, unless otherwise
specified.
9. tSKEW! is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to beincluded in the current clock cycle (for
purposes offlag update). If the opposite clock occurs less than tSKEW!
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock
ns
20
15
ns
20
15
ns
ns
is the sigual to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the the opposite
clock for the Almost Full flag. The clock is the signal to which a flag is
synchronized; i.e., CKW is the clock for the Almost Full flag, CKR is
the clock for Empty and Almost Empty flags.
10. tSKEW2 is the minimum time an opposite clock can occur before a
clock and still be guaranteed to be included in the current clock cycle
(for purposes of flag update). If the opposite clock occurs less than
tSKEW2 before the clock, the decision of whether or not to include the
opposite clock in the current clock cycle is abritrary. See Note 9 for
definition of clock and opposite clock.
5-74
J~~DucroR
PRELIMINARY
CY7C441
CY7C443
Switching Waveforms
Write Clock Timing Diagram
CKW
00-8
•
F1
(I)
oLL.
u::
Read Clock Timing Diagram
CKR
°0-8
C441-7
Master Reset Timing Diagram[11,12,13,14j
------------,
....- - - - - tpMR
-----.-j
/------------------
CKW
CKR
°0-8
ALL DATA
OUTPUTSI.I)W
VAUDDATA
tMRFZl
'C
5-75
C441-B
::JfV;~NDU~R
PRELIMINARY
CY7C441
CY7C443
Switching Waveforms (continued)
Read to Empty Timing Diagram[15,17,18]
1 (no change)
COUNT
LATENT CYCLE
CKR
CKW
C441-10
Read to Empty Timing Diagram with Free-Running C1ocks[15,16,17]
COUNT
LATENT CYCLE
CKR
CKW
C441-9
Notes:
11. ENW or CKW must be inactive while MR is LOW.
12. ENRor CKR must be inactive while MR is LOW.
13. All data outputs (00 _ 8) go LOW as aresult of the rising edge ofMR.
14. In this example, 00 _ 8 will remain valid until tOHMR if the first read
shown did not occur or if the read occurred soon enough such that the
valid data was caused by it.
15. "Count" is the number of words in the FIFO.
16. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than IsKEW2 before R3. Therefore, the FIFO
still appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
17. CKR is clock and CKW is opposite clock.
18. R3 updates the flags to the Empty state by bringing F1 LOW. Because
WI occurs greater than tSKEWl after R3, R3 does not recognize WI
when updating flag status. But because WI occurs tSKEW2 before R4,
R4 includes WI in the flag update and therefore updates the FIFO to
the Almost Empty state. Itis important tonote lhat R4 is alate!!!.£Y!:le;
i.e., it only updates the flag status, regardless of the state of ENR. It
does not change the count or the FIFO's data outputs.
5-76
·il~DUCTOR
CY7C441
CY7C443
PRELIMINARY
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[15,17]
COUNT
17
16
17
18
17
16
15
CKR
ENR
•
CKW
~
ENW
___-J/
II>
oLI.
u::
HIGH
F1
F2
C441-11
Read to Almost Empty Timing Diagram with Read FIag Update Cycle with Free-RunningClocks[15 ,17,19,20]
18 (no change)
COUNT
17
16
17
FLAG UPDATE CYCLE
18
17
16
15
~____________t_FD_~______
C441-12
Noles:
19. R4 only updates the flag status. It does not affect the couot because
ENRis IDGH.
20. When making the transition from Almost Empty to Intermediate, the
couot must increase by two (16 • 18; two enabled writes: W2, W3)
before a read (R4) can update flags to the Intermediate state.
5-77
-
~~PRFSS
~, SEMJCOIDUClDR
Switching Waveforms
CY7C441
CY7C443
PRELIMINARY
(continued)
Write to Almost Full Timing Diagram[15,21,22,23,24]
COUNT
2030
[494]
2031
[495]
21X3.2
[496J
2030
2031
[495J
[494J
21X3.2
[496]
2031
[497]
2030- .
:J~;
i
i
203t'
: J~7! ~
2033
[497]
i
'2002- :
:J~!!
CKW
CKR
C441-14
Write to Almost Full Timing Diagramwith Free_RunningClocks[15,21,22]
COUNT
2031
[495J
2IX3.2
[496J
2031
[495J
2031
[495J
2030
[494J
21X3.2
[496]
2033
[497]
CKW
CKR
C441-13
Note.:
21. CKW is clock and CKR is opposite clock.
22. Count 2032 iodicates Almost Full for CY7C443 and count 496 iodicates Almost Full for CY7C441. Values for the CY7C441 count are
shown io brackets.
23. The dashed lines show W3 as flag update write rather than an enabled
.
write because ENW is dellS/l~rted.
=
=
24. W2 updates the flags to the Almost Full state by bringiog Fl LOW.
Because Rl occurs greater than tSKEW! after W2, W2 does not recognize Rl when updating the flag status. W3 includes R2 io the flag update because R2 occurs greater than IsKEW2 before W3. Note that W3
does not have to be enabled to update flags.
25. When making the transition from Almost Full to Intermediate, the
count must decrease by two (2032.2030; two enabled reads: R2, R3)
before a write (W4) can update flags to Intermediate state.
5-78
~
~~PRFSS
~, ~ICONDUcroR
Switching Waveforms
PRELIMINARY
CY7C441
CY7C443
(continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clock[15,21,22,25]
2030 (no change)
[494]
FLAG UPDATE CYCLE
CKW
CKR
~________~__t_FD_~_______
C441-15
Architecture
The CY7C441/443 consist of an array of 512/2048 words of 9 bits
each (implemented by an array of dual-port RAM cells), a read
I!2!!tter, a write pointer, control signals (CKR, CKw, ENR, ENW,
MR), and flags (F1, F2).
Resetting the FIFO
~n
power-up, tbe FIFO must be reset witb a Master Reset
(MR) cycle. This causes tbe FIFO to enter the Empty condition
signified by both flags F1 and F2 b~ LOW. All data outputs
(00-8) go LOW at tbe rising edge ofMR. In order fortbe FIFO to
read to its default state, a falling ~e must occur on MR and tbe
user must not read or write while MR is LOW (unless ENR and/or
ENW are HIGH). Upon completion oftbe Master Reset cycle, all
data outputs will go LOW tAMR after MR is deasserted. FlandF2
are guaranteed to be valid tMRF after MR is taken HIGH.
ically equal to approximately one cycle time. The Empty and Almost Empty flag states are exclusively updated by each rising edge
oftbe read clock (CKR). For example, when tbe FIFO contains 1
word, the next read (rising edge of CKR while ENR=LOW)
causes the F1 and F2 pins to output a state signifying tbe Empty
condition. The Almost Full flag is updated exclusively bytbe write
clock (CKW). For example, if the CY7C443 FIFO contains 2031
words (2032 words or greater indicates Almost Full in tbe
CY7C443), tbe next write (rising edge of CKW while
ENW= LOW) causes the F1 and F2 pins to output tbeAlmost Full
state.
Thble 1. Flag 'Ihlth Thble
FIFO Operation
When tbe ENW signal is active (LOW), data on tbe DO-8 pins is
written into tbe FIFO on each rising edge oftbe CKW signal. Similarly, when the ENR signal is active, data in tbe FIFO memorywill
be presented on the 00-8 outputs. New data will be presented on
each rising edge of CKR while ENR is active. ENR must set up
tSEN before CKR for it to be a valid read duration. ENW must occur tSEN before CKW for it to be a valid write function.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO maintains tbe data of tbe last valid read on its 00-8 outputs even after
additional reads occur.
Flag Operation
The CY7C441/3 provide two flags, F1 and F2, which are used to
decode four FIFO states (see Table 1). All flags are synchronous,
meaning that tbe change of states is relative to one of tbe clocks
(CKR or CKw, as appropriate). The synchronous architecture
guaranteessome minimum valid time for the flags. This time is typ-
5-79
CY7C441
Fl
F2
State
0
0
Empty
1
0
1
1
0
1
Almost
Empty
Intermediate
Range
Almost Full
or Full
Number of
WInIs in FIFO
CY7C443
Number of
Words in FIFO
0
0
1-16
1-16
17 - 495
17 - 2031
496 - 512
2032 - 2048
PRELIMINARY
CY7C441
CY7C443
Flag Operation (continued)
Non-Boundary Flags (Almost Emp~ Almost Full)
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the Almost Full flag is only updated by
the CKW, careful attention must be given to the flag operation.
The user must be aWllle that.if a flag boundary (Empty, Almost
Empty, and Almost Full) is crossed due to an operation from a
clock that the flag is not synchronized to (ie.,CKR does not .effect Almost FnlI), a flag update is necessary to represent the
FIFO's new state. This signal to which a flag is not synchronized
will be referred to as the opposite clock (CKW is opposite clock
for Empty and Almost Empty flags; CKR is the opposite clock
for the Almost Full flag). Until the flag update cycle is executed,
the synchronous flags do not show the true state of the FIFO.
For example, if 2,040 writes are performed to an empty
CY7C443 without a single read, F1 and F2 will still exhibit an
Empty flag. This is because F2 is exclusively updated by the
CKR, therefore, a single read (flag update cycle) is necessary to
update flags to Almost Full state. It should be noted that this flag
update read does not require :mom: = LOW, so a free-running
read clock will initiate the flag update cycle.
When updating the flags, the CY7C441/443 decide whether or
not the opposite clock was recognized when a clock updates the
flag. For example, if a write occurs at least tSKEWl after a !'\lad
when updating the Empty flag, the write is guaranteed not to be
included when CKR updates the flag. If a write occurs at least
tsKEW2 before a read, the write is guaranteed to be included
when CKR updates the flag. If a write occurs within
tSICEWl/tSKEW2 after or before CKR, then the decision ofwhether ~r not to include the write when the flag is updated by CKR is
arbitrary.
The update cycle for non-boundary flags (Almost Empty, Almost
Full) is different from that used to update the boundary flag
(Empty). Both operations are described below.
The flag status pins, Fl and Flo exhibit the Almost Empty status
when bottJ. the CY7C441 and the CY7C443 contain 16 words or
less. The Almost Full Flag becomes active when the FIFO contains 16 or less empty locations. The CY7C441 becomes Almost
Full when it contains 496 words. The CY7C443 becomes Almost
Full when it contains 2032 words. The Almost Empty flag (like
the Empty flag) is synchronous to the CKR signal, whereas the
Almost Full flag is synchronous to the CKW signal. Non·boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO state. For example, if the
FIFO just reaches the Almost Empty state (16 words) and then
two words are written, a read clock (CKR) will be required to update the flags to the Intermediate state. However, unlike the
boundary (Empty) flag's update cycle, the state of the enable pin
~ in this case) affects the operation. Therefore, ENR set·up
&ENl and hold (tHEN) times must be met IfENR is asserted
(ENR-LOW) during the latent cycle, the count and data update
in addition to F1 and F2 If:mom: is not active (ENR = 1) during
the flag update cycle, only the flag is updated.
The same principles apply for updating the flags when a transition from the Almost Full to the Intermediate state occurs. If the
CY7C443 just reaches the Almost Full state (2032 words)'and
then two words are read, a write clock (CKW) will be required to
update the flag to the Intermediate state. Ifll.NW is LOW during the f1ag~ cycle, the count and data update in addition to
the flags. If
is lllGH, only the flag is updated, Therefore,
'£NW set-up (isBN) and hold (tHEN) times must be met. Thbles 3
and 4 show examples for a sequence of operations that affect the
Almost Empty and Almost Full flags, respectively,
Boundary Flag (Empty)
The Empty flag is synchronized to the CKR signal. The Empty
flag can only be updated by a clock pulse on the CKR pin. An
empty FIFO that is written to will be described with an Empty
flag state until a clock pnIse is presented on the CKR pin. When
making the transition from Empty to Almost Empty (or Empty to
~ntermediate or Empty to Almost Full), a clock cycle on the CKR
IS necessary to update the flags to the current state. Such a state
(flags displaying empty even though data has been written to the
FIFO) would require two read cycles to read data out of FIFO.
The first read serves only to update the flags to the Almost
Empty, Intermediate, or Almost Full state, and the second read
outputs the data. This first read cycle is known as the latent or
flag update cycle because it does not affect the data in the FIFO
or the count (number of words in FIFO). It simply deasserts the
Empty flag. The flags are updated regardless of the :mom: state.
Therefore the update occurs even when mR: is deaSserted
(HIGH) so that a valid read is not necessary to update the flags
to correctly describe the FIFO.. With a free-running clock connected to CKR, the flag updates with each cycle. Thble 2 shows
sample operations that update the Empty flag.
Although a Full flag is not supplied externally on the
CY7C441/CY7C443, a Full flag exists internally. The operation
of the FIFO at the Full boundary is analogous to its operation at
the Empty boundary. See the text section "Boundary Flags
(Full)" in the CY7C451/CY7C453 datasheet.
Width Expansion
The CY7C441/3 can be expanded in width to provide word width
greater than 9 in increments of 9. During width expansion mode,
all control inputs are common. When the FIFO is being read
near the Empty boundary, it is important to note that both sets of
flags shonld be checked to see if they have been updated to the
Not Empty condition on all devices.
Cllecking all sets of flags is critical so that data is not read from
the FIFOs "staggered" by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than tSKEWl after the first
write to two width expanded devices (A and B), device A may go
Almost Empty (read recognized as flag update) while device B
stays Empty (read iguored).The first write occurs because a read
within 1sKEW2 of the first write is only guaranteed to be either
recognized or ignored, but which of the two is not guaranteed.
The next read cycle outputs the frrst half of the frrst word on device A while device B updates its flags to Almost Empty, Subsequent reads will continue to output ~'staggered" data assuming
more data has been written to the FIFOs.
In the width expansion configuration, any of the devices' flags
may be monitored for the composite Almost Full status.
5-80
d;~
-= CYPRESS
,
SEMlCONDUCIDR
CY7C441
CY7C443
PRELIMINARY
Thble 2. Empty Flag Operation Example [26]
Status Before Operation
I NumDeror
Current State
Words
of FIFO
Fl
F2
in FIFO
0
0
0
Empty
Empty
0
0
1
Empty
0
0
2
AE
1
0
2
AE
1
0
1
Empty
0
0
0
Empty
0
0
1
AE
1
0
1
Operation
Write
(ENW=LOW)
Write
(ENW=LOW)
Read
(ENR= HIGH)
Read
(ENR=LOW)
Read
(ENR=LOW)
Write
(ENW=LOW)
Read
(ENR=X)
Read
(ENR=LOW)
Status After Operation
Number of
Words in
FIFO
Comments
1
Write
Next State
of FIFO
Empty
Fl
0
F2
0
Empty
0
0
2
Write
AE
1
0
2
Flag Update
AE
1
0
1
Read
Empty
0
0
0
Empty
0
0
1
Read ('fransition for
Almost Empty to Empty)
Write
AE
1
0
1
Flag Update
Empty
0
0
0
Read ('fransitionfromAlmost Empty to Empty)
Thble 3. Almost Empty Flag Operation Example[26]
Status Before Operation
Status After Operation
Nnmberof
Number of
Current State
Words
Next State
Words in
of FIFO
Fl
F2
in FIFO
Operation
Fl
Comments
of FIFO
F2
FIFO
AE
1
0
16
Write
AE
1
0
17
Write
(ENW=LOW)
AE
1
0
17
Write
AE
1
0
18
Write
(ENW=LOW)
1
AE
1
18
Flag Update
0
Read
Intennediate
1
17
(ENR=LOW)
and Read
Intermediate
1
1
17
Read
AE
1
16
Read ('fransition
0
fromIntennediate
(ENR=LOW)
to Almost Empty)
AE
1
0
16
Read
AE
1
0
16
Ignored Read
(ENR=HIGH)
Thble 4. Almost Full Flag Operation Example[27,28]
Status Before Operation
Status After Operation
I Number of Number of
Number of Number of
Current
Words in
Words in
Words in
Words in
State of
FIFO
FIFO
Next State
FIFO
FIFO
Fl F2 CY7C441
CY7C443
FIFO
Operation
of FIFO
Fl F2 CY7C441
CY7C443
AF
0
1
496
2032
Read
1
495
2031
AF
0
(ENR=LOW)
AF
0
1
495
2031
Read
AF
0
1
494
2030
(ENR=LOW)
AF
0
1
494
2030
494
2030
Write
Intennediate 1
1
(ENW=HIGH)
Intennediate 1
1
494
2030
Write
1
495
2031
Intennediate 1
(ENW=LOW)
Intennediate 1
495
1
2031
Write
AF
0
1
496
2032
(ENW=LOW)
Comments
Read
Read
Flag
Update
Write
Write
Vransition
rom Intermediate
to Almost
Full)
Note:
26. Applies to both the CY7C441 and CY7C443 operations.
27. The CY7C441 Almost Full state is represented by 496 or more words.
28. The CY7C443 Almost Full state is represented by 2032 or more
words.
5-81
•
rC~PRE§
~,
CY7C441
CY7C443
PRELIMINARY
SEMICONDUCTOR
Ordering Information
Speed
(ns)
14
Package
1YPe
Operating
Range
Speed
(ns)
CY7C441-14PC
P21
Commercial
14
CY7C441-14JC
CY7C441-14VC
CY7C441-14DC
J65
V21
D22
CY7C441-14LC
CY7C441-14PI
L55
P21
CY7C441-14JI
J65
022
Ordering Code
CY7C441-14DI
CY7C441...,14DMB
20
Military
Operating
Range
CY7C443-14PC
P21
Commercial
CY7C443-14JC
CY7C443-14VC
J65
V21
CY7C443-14DC
D22
CY7C443-14LC
CY7C443-14PI
L55
P21
CY7C443-14JI
CY7C443-14DI
J65
D22
CY7C443-14DMB
D22
CY7C443 -14LMB
CY7C443 -14KMB
L55
K74
CY7C441-14LMB
CY7C441-14KMB
L55
K74
CY7C441-20PC
P21
CY7C443-20PC
P21
CY7C441-20JC
J65
V21
CY7C443-20JC
J65
CY7C443-20VC
V21
022
L55
CY7C443-20DC
022
CY7C443-20LC
L55
P21
CY7C441-20VC
CY7C441-20DC
CY7C441-20LC
CY7C441- 20PI
30
D22
Industrial
Package
type
Ordering Code
P21
CY7C441-20JI
J65
CY7C441-20DI
D22
CY7C441-20DMB
CY7C441-20LMB
D22
CY7C441-20KMB
L55
K74
CY7C441-30PC
P21
CY7C441-30JC
Commercial
20
Industrial
CY7C443-20PI
CY7C443-20JI
CY7C443-20DI
Military
CY7C443-20DMB
CY7C443-20LMB
D22
CY7C443-20KMB
CY7C443-30PC
P21
J65
CY7C443-30JC
J65
CY7C441-30VC
CY7C441- 30DC
V21
D22
CY7C443-30VC
CY7C443-30DC
V21
D22
CY7C441-30LC
L55
CY7C441-30PI
P21
CY7C441-30JI
J65
CY7C441-30DI
D22
D22
CY7C441-30DMB
CY7C441-30LMB
CY7C441-30KMB
30
Industrial
Military
CY7C443 - 30LC
L55
CY7C443-30PI
P21
CY7C443-30JI
J65
CY7C443-30DI
CY7C443-30DMB
022
CY7C443-30LMB
L55
K74
CY7C443-30KMB
5-82
Military
Commercial
Industrial
J65
022
L55
K74
Commercial
Industrial
Military
Commercial
Industrial
D22
L55
K74
Military
=.
~
~- cYPRF.SS
~.,
PRELIMINARY
CY7C441
CY7C443
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VILMax.
IJX
ICC
lOS
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
Subgroups
teKR
teKW
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tCIrn
teKL
tA
toH
tFH
tso
tHo
tSEN
tHEN
tHENR
tFo
tSKEWl
tSKEW2
tpMR
tsCMR
. tOHMR
tMRR
tMRF
tAMR
Document #:
su..
u::
38-00124-C
5-83
CY7C451
CY7C453
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Cascadeable Clocked 512 x 9
and Cascadeable Clocked 2K x 9
FIFOs with Programmable Flags
Features
FuncUonalDe~ption
• 512 x 9 (CY7C451) and 2,048 x 9
(CY7C453) FIFO buffer memory
• Expandable in widtb and depth
• High-speed 70-MHz standalone;
50-MHz cascaded
• Supports free-running 5K duty cycle
clock inputs
The CY7C451 and CY7C453 are highspeed, low-power, first-in first-out (FIFO)
memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit
memory array, white the CY7C453 has a
2048-word by 9-bit memory array. Devices can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Empty" flags and generation!
checking of parity. These FlFOs provide
solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
Both FlFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running 50% duty cycle
clock (CKW) and a write enable pin
(t!NW). When ENW is asserted, data is
written into the FIFO on the rising edge of
theCKW signal. WhileENWisheldactive,
data is continually written into the FIFO
on each CKW cycle. The output port is
• Empty, Almost Empty, Half Full,
Almost Full, and Full status Dags
• Programmable Almost Full/Empty
nags
• Pari ty generation/cbeckIng
• Fully asynchronous and simultaneous
read and write operation
• Output Enable (00)
• Independent read and write enable
pins
• Center power and ground pins for reducednoise
• Available in 301).mll 32-pln DIP,
PLCC, and LCC packages
• Proprietary O.S" CMOS technology
• TTL compatible
Logic Block Diagram
controlled in a similar manner by a freerunning read clock (CKR) and a read enable pin (mM). The read (CKR) and
write (CKW) clocks may be tied together
for singIe-clock operation or the two docks
may be run independently for asynchronous readlwrite applications. Oock frequencies up to 71.4 MHz are acceptable
in the standalone configuration, and up to
50 MHz is acceptable when FIFOs are
cascaded for depth expansion.
Depth expansion is possIble using the cascade~t (XI) and cascade output /XO).
The XO signal is connected to the ~ of
the next device, and the XU of the last device should be connected to the XI of the
first device. In standalone mode, the input (XI) pin is simply tied to Vss.
The CY7C451 and CY7C453 provide three
status pins to the user. These pins are decoded to detennine one of six states: Empty,
Almost Empty, Les!; than or EquaI to Half
FuR, Greater than Half Full, Almost FuR,
and FuR (see Thbk 1). The Almost Empty/
Full flag (PAPB) and XC> functions share
the same pin. The Almost EmptylFuD flag
Pin Configurations
Do-I
PLCClLCC
TopYlew
DoD, liz DaD. Dolle
XI
5
6
7
EIQW
CKW
CKW
EIQW
Vee
Vaa
Da
Do
XI
5-84
tlE"
00/f'G/PE
0451-2
Ile
F[
CKW
UI!
vee
Vss
Vss
RI'
M'
EIQFI
Co
a,
a.
0451-1
CKR
EIQFI
D.
D.
D.
D7
EIQW
~
EIQFI
UI!
DIP
'IbpYlew
D.
D,
CKR
DI
:: Vas
a, a.a.a. Co Co 0,
RI'
M'
lW'E"JXO
a. -7. QWPGII'E
F[
70451
9
7C453
24
10
23
11
22
12
21
13
14151617181920
a.
xr-l ~C:CKlN
0.
~:
-
8
RI'
M'
lW'E"JXO
~ =:/L_~_ES_ij_.J
432,\323130
291
a.
CKR
tlE"
aalPGII'E
0,
al
a.
a.
0451-3
.......-...-=.
.
·~PRFSS
CY7C451
CY7C453
PRELIMINARY
_ . F SEMICONDUCTOR
Functional Description (continued)
is valid in the standalone and width expansion configurations. In
the depth expansion, this pin provides the expansion out (XO) infonnation that is used to signal the next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to either
the read clock (CKR) or the write clock (CKW). When entering or
exiting the Empty and Almost Empty states, the flags are updated
exclusivelyby the CKR. The flags denoting Half Full, Almost Full,
and Full states are updated exclusively by CKW The synchronous
flag architecture guarantees that the flags maintain their status for
some minimum time. This time is typically equal to approximately
one cycle time.
The CY7C451 and the CY7C453 use center power and ground for
reduced noise. Both configurations are fabricated using an advanced 0.81-1 N-well CMOS technology. Input ESD protection is
greater than 2001 V, and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Selection Guide
7C451-14
7C4S3-14
7C451-20
7C453-20
7C451-30
7C453-30
Maximum Frequency (MHz)
71.4[1]
50
33.3
Maximum Cascadeable Frequency
N/A[2]
50
33.3
Maximum Access Time (ns)
10
15
20
Minimum Cycle Time (ns)
14
20
30
Minimum Clock HIGH Time (ns)
6.5
9
12
Minimum Clock LOW Time (ns)
6.5
9
12
7
9
12
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
0
0
0
Maximum Flag Delay (ns)
10
15
20
I Commercial
140
120
100
I Military!Industriai
160
140
130
Maximum Current (rnA)
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
Power Applied . . . . . . . . . . . . . . . . . . . . . .. - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Notes:
1. 71.4-MHzoperation is available only in the standalone configuration.
2. The - 14 device cannot be cascaded.
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 200 rnA
Operating Range
Range
Commercial
O°Cto +70°C
Vee
5V± 10%
Industrial
- 40°C to +85°C
5V± 10%
Military[3]
- 55°C to +l25°C
5V± 10%
3.
5-85
Ambient
Thmperature
TA is the "instant on" case temperature.
•
~.
PRELIMINARY
.'~NDUCrOR
CY7C451
CY7C453
Pin Definitions
I/O
Description
Do-s
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ s) into the
FIFO'smemory. IfMR is asserted at the rising edge of CKW then data iswritten into the FIFO's programming
register. Ds is ignored if the device is configured for parity generation.
00-7
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (00 _ 7) out of the
FIFO'smemory. IfMR is active at the rising edge of CKR then data is read from the programming register.
Og/PG/PE
0
Function varies accordingto mode:
Parity disabled - same function as 00 - 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
ENW
I
Enable Write: enables the CKW input (for both non-program and program modes)
ENR
I
Enable Read: enables the CKRinput (for both non-program and program modes)
CKW
I
Write Oock: the risin~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: the rising ed~locks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Flag - synchronized to CKW:
ElF
0
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
PAFE/XO
0
Dual-Mode Pin:
Not Cascaded - ProgrammableAlmostFuil is synchronized to CKW; Programmable AlmostEmptyissynchronizedtoCKR
Cascaded - Expansion Out signal, connected to XI of next device
XI
I
Not Cascaded - XI is tied to Vss
Cascaded - Expansion Input, connected to XO of previous device
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to Vss; all other devices will have FL tied to Vcc
Signal Name
(Figurel)
Not Cascaded - tied to Vcc
MR
I
Master Reset: resets device to empty condition.
__
Non-Programming Mode: program register is reset to default condition of no parity and PAFE active at 16 or
less locations from Full/Empty.
ProgrammingMode: Data present on Do _ 8 is written into the programmable register on the rising edge of
CKw. Program register contents appear on 00 _ S after the rising edge ofCKR.
OE
I
Output Enable for 00 _ 7 and Og/PG/PE pins
5-86
-.-.
;~PRESS
CY7C45 1
CY7C453
PRELIMINARY
~.F SEMICONDUCTOR
Electrical Characteristics Over the Operating Range!4]
Parameters
7C451-14
7C453-14
Min. Max.
Thst Conditions
Description
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Vrn[5]
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
2.2
VIL[5]
Input LOW Voltage
IIX
Input Leakage
Current
IOS[6]
10ZL
10ZH
lee[7]
2.4
7C451-20
7C453-20
Min. Max.
2.4
-3.0
Vee = Max.
-10
+10
Output Short
Circuit Current
Vee = Max., VOUT = GND
-90
Output OFF, High Z
Current
OE~
Operating Current
Vee = Max., lOUT = 0 rnA Com'l
Vrn, Vss < Vo < Vee
-10
2.4
2.2
2.2
0.4
V
V
flA
-3.0
Vee
0.8
-3.0
Vee
0.8
-10
+10
-10
+10
-90
+10
V
0.4
0.4
Vee
0.8
7C4S1-30
7C4S3-30
Min. Max. Units
-10
rnA
-90
+10
V
-10
+ 10
flA
I
140
120
100
rnA
I Mil/Ind
160
140
130
rnA
Capacitance [8]
Parameters
CIN
CoUT
Description
InputCapacitance
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Max.
Units
pF
pF
10
12
AC Test Loads and Waveforms[9, 10, 11, 12, 13]
R1500Q
ALL INPUT PULSES
OUTP~~31
ClI
INCLUDING _
JIG AND SCOPE
Equivalent to:
~
10%
R2
3330
..
_
C451-4
53n5
C451-5
THEvENIN EQUIVALENT
2()()Q
OUTPUTGo-----Ny~~
____~o2V
Notes:
4. See the last page of this specification for Group Asubgroup testing information.
5. The YllI and VIL specifications apply for all inputs exce.E!..XI and FL.
The XI pin is not a TIL input. It is connected to either XO ofthe previous device or Vss. FL must be connected to either Vss or Vce.
6. Test no more than" one output at a time for not more than one second.
7. Input signals switch from OV to 3V with a rise/fall time of less than 3
us, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAxI2. Outputs are unloaded.
8. Thsted initially and after any design or process changes that may affect
these parameters.
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for toHZ.
11. All AC measurements are referenced to 1.5V except toE, tOLZ, and
tOHZ.
12. tOE and toLZ are measured at ± 100 mV from the steady state.
13. tOHZis measured at +500 mV from VOLand - 500 mV from VOH.
5-87
II)
o
u..
u::
CY7C451
CY7C453
PRELIMINARY
Switching Characteristics
Over the Operating Rangel2, 14]
7C451-14
7C453-14
Parameters
Description
Min.
Max.
7C451-20
7C453-20
Min.
Max.
7C451-30
7C453-30
Min.
Max. Units
tCKW
Write Qock Cycle
14
20
30
ns
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
Clock LOW
6.5
9
12
tA
Data Access Time
tOH
Previous Output Data Hold Mter Read HIGH
0
0
0
ns
tPH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
tso
DataSet-Up
7
9
12
ns
tHo
Data Hold
0
0
0
ns
tSEN
EoableSet-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
tOE
toLZ[6]
OE LOW to Output Data Valid
toHZ[6]
OE HIGH to Output Data io High Z
10
15
20
os
tpG
Read HIGH to ParityGeoeratioo
10
15
20
ns
tpE
Read HIGH to Parity Error Flag
10
15
20
ns
tFO
Flag Delay
10
15
20
tSKEW1[15]
Opposite Clock After Clock
14
20
30
os
ns
15
10
15
10
OE LOW to Output Data io Low Z
0
0
ns
20
ns
os
20
os
os
0
ns
tSKEW2[16]
Opposite Clock Before Clock
14
20
30
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
os
tSCMR
LastVaiidClockLOWSet-UptoMRLOW
0
0
0
ns
tOHMR
Data Hold FromMR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MRHIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MRHIGH to Data Outputs LOW
14
20
30
ns
tSMRP
ProgramMode-MR LOW Set-Up
14
20
30
ns
tHMRP
ProgramMode-MR LOW Hold
10
15
25
ns
tFfp
ProgramMode-Write HIGH to Read HIGH
14
20
30
tAP
Program Mode-DataAccess Time
tOHP
Program Mode-Data Hold Time from MR HIGH
14
Notes:
14. Thst conditions assume signal transition time of3 ns or less, timing reference levels of 1.5Y, and output loading as shown in AC Thst Loads
and Waveforms and capacitance as in notes 6 and 10, unless otherwise
specified.
15. tSKEW! is the minintum time an opposite clock can occur afier a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW!
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the sigualtowhich aflag is not synchronized; i.e., CKW is the opposite
clock for Empty and Almost Empty flags, CKR is the the opposite
0
20
0
ns
30
0
ns
ns
clock for the Almost Full, HaIfFuII, and Full flags. The clock is the signal to whiclt a flag is synchronized; i.e., CKW is the clock for the Half
Fnll, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
16. tSKEW2 is the minimum time an opposite clock can occur before a
clock and still be guaranteed to be included in the current clock cycle
(for purposes of flag update). If the opposite clock occurs less than
tSKEW2 before the clock, the decision of whether or not to include the
opposite clock in the current clock cycle is arbitrary. See Note 15 for
definition of clock and opposite clock.
5-88
-==--.
·~PRESS
=-F
PRELIMINARY
CY7C451
CY7C453
SEMICONDUCTOR
Switching Wavefonns
Write Clock Timing Diagram
CKW
°0-8
•
( II
o
u:
u.
Read Clock Timing Diagram
CKR
QO-8
C451-7
Master Reset (Default with Free-Running Clocks) Timing Diagram!l?, 18, 19,20]
_________.1-----
tpMR
-----I
~------------
CKW
CKR
QO-8
ALL DATA
OUTPUTS Lcr.N
VAUDDATA
C451-8
5-89
C~PRE§
~_,
PRELIMINARY
SEMICONDUCl'OR
CY7C451
CY7C453
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram[19,20 1
CKW
DO- 8
CKR
ENR
00-8
~w~w
________
~~
__________________+-____
~
______ ___________________________
~
ALL DATA
VALID DATA
OUTPUTSWW
C451-9
Master Reset (programming Mode with Free-Running Clocks) Timing Diagram[19,20 1
tHMRP
MR
CKW
ENW
Do-8
CKR
ENR
All DATA
°O-B
OUTPUTS lOW
0451-10
Notes:
17. 1b only perform reset (no programming), the following criteria must
be met: ENW or CKW must be inactive while MR is LOW
18. 1b only ~rm reset (no programming), the following criteria must
be met: ENR or CKR must be inactive while MR is LOW
19. All data outputs (00 - 8) go LOW as a result ofthe rising edge ofMR
aftertAMR·
20. In this example, Qo _ 8 will remain valid until tOHMR if either the fIrst
read shown didnotoccur or if the read occurred soon enough such that
the valid data was caused by it.
5-90
PRELIMINARY
Switching Waveforms
CY7C451
CY7C453
(continued)
Read to Empty Timing Diagram[21, 24, 25]
1 (NO CHANGE)
COUNT
LATENT CYCLE
CKR
CKW
II
C451-12
Read to Empty Timing Diagram with Free-Rnnning Clocks[21, 22, 23, 24]
LATENT CYCLE
COUNT
CKR
CKW
ENW
HF
HIGH
ElF
PAFE
tFD=)
IDW
C451-11
Notes:
21. "Count" is the number of words in the FIFO.
22. The FIFO is assumed to be programmed with P>O (i.e., PAFE does
not transition at Empty or Full).
23. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tSKEW2 before R3. Therefore, the FIFO
still appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
24. CKR is clock; CKW is opposite clock.
25. R3 updates the flag to the Empty state by asserting EJF. Because W1
occurs greater than tSKEW! after R3, R3 does not recognize W1 when
updating flag status. But because WI occurs tsKEW2 before R4, R4 includes WI in the flag update and, therefore, updates FIFO to Almost
Empty state. It is important to note that R4 is alaten~e; i.e., it only
updates the flag status regardless of the state of ENR. It does not
change the count or the FIFO's data outputs.
5-91
CY7C451
&:;~
PRELIMINARY
~'~NDUCIDR
CY7C453
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[21, 24, 26]
COUNT
17
16
17
18
17
15
16
CKR
ENR
CKW
ENW
HF
HIGH
Ell'
HIGH
tFD~
tFDl
PAFE
tFD~
C451-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks[21, 24, 26, 27, 28]
18 (no change)
COUNT
17
HF
HIGH
Ell'
HIGH
16
17
FLAG UPDATE CYCLE
18
17
16
15
C451-13
Notes:
26. The BFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
27. R4 ouly updates the flag status. It does not affect the count because
ENRisffiGH.
28. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 • 18; two enabled writes: W2, W3)
before a read (R4) can update flags to the Less Than Half Full state.
5-92
PRELIMINARY
CY7C451
CY7C453
Switching Waveforms (continued)
Write to Half Full TIming Diagram with Free-Running Clocks[21, 29, 30, 31]
COUNT
102'
[256]
1025
[257]
102.
[256[
1023
1024
[2551
[256[
1025
[2571
1026
[2581
CKW
am
•
CKR
J:NR
-------'/
RF
ElF
HIGH
PAFE
HIGH
C451-15
Write to Half Full TIming Diagram with Write Flag Update Cycle with Free-Running Clocks[21, 29, 30, 31, 32, 33]
\~ino change)
FLAG UPDATE CYClE
COUNT
CKW
em
CKR
ENR
HF
ElF
HIGH
J5AFE
HIGH
C451-16
Notes:
29. CKW is clock and CKR is opposite clock.
30. Count 1,025 indicates Half Full for the CY7C453 and count 257
indicates Half FuJI for the CY7C451. Values for CY7C451 count are
shown in brackets.
31. When the FIFO contains W4 [256J words, the rising edge of the next
enabled write causes the ttl' to be true (LOW).
=
=
32. The 'HFwrite flag update cyc:Ie does not affect the count because ENW
is HIGH. It only updates HF to HIGH.
33. When making the transition from Half Full to Less Than Half FUll, the
count must decrease by two (1,025. 1023; two enabled reads: R2 and
R3) before a write (W4) can update flags to less than Half Full.
5-93
CY7C45 1
PRELIMINARY
CY7C453
Switching Waveforms (continued)
Write to Almost Full Timing Diagram[21, 26, 29, 34, 35]
COUNT
2030
[494]
2031
[495]
2031
[495]
2032
[496]
2030
[494]
2031
[4S5]
i
2030- :
:1~!!
2032
[496]
i
203r:
:1~!!
2033
[497]
i
2002- :
:J~!J
CKW
CKR
ENR
PAFE
HF
LOW
~
HIGH
C451-18
Write to Almost Full Timing Diagram with Free-Running Clocks[21, 26, 29]
COUNT
2031
[4S5]
2032
[~
2031
[4S5]
2030
[494]
2031
[4S5]
2032
[498]
2033
[497]
CKW
ENW
CKR
ENR
HF
LOW
~
HIGH
PAFE
tFD1
C451-17
Notes:
34. W2 updates the flag to the Almost Full state by asserting PAFE. Because Rl occurs greater than IsKEw! after W2, W2 does not recognize
Rl when updating flag status. W3 includes R2 in the flag update because R2 occurs greater than IsKEW2 before W3. Note that W3 does
not have to be enabled to update flags.
35. The dashed lines show W3 as a flag update write rather than an enab]ed write because ENW is deasserted.
.
5-94
CY7C451
CY7C453
PRELIMINARY
Switching Waveforms (continued)
=
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[21, 26, 29]
(no chango)
FLAG UPDATE CYCLE
COUNT
CKW
ENW
•
CKR
ENR
HF
u:m
ElF
HIGH
tFD~_
tFD~_
_
tFD)_ _
PAFE
C451-19
Write to Full Flag Timing Diagram with Free-Running ClockS[21, 29, 36]
COUNT
CKW
CKR
HF
LOW
C451-20
Notes:
36. W2 is ignored because the FIFO is full (count = 2,048 (512)). It is important to note that W3 is also ignored because R3, the first eoabled
read after full, occurs less than tSKEW2 before W3. Therefore, the
5-95
FIFO still appears full when W3 occurs. Because R3 occurs greater
than tSKEW2 before W4, W4 iocludes R3 io the flag update.
~~
PRELIMINARY
~=CYPRESS
~, SEMICONDUCTOR
Switching Wavefonns
CY7C451
CY7C453
(continued)
Even Parity Generation Timing Dlagram[37, 38]
CKR
OalPG/PE
00-7
-}
ENABLED READ
tPG
, . . . _______J/
DISABLED READ ,
......_ _ _ _ __
---~
PREVIOUS WORD:
EVEN NUMBER OF 10
NEW WORD
ODD NUMBER OF 1s
t
CKR
II)
o
u..
u:::
ff.--------+------+-J
O~PGf--------------------------------~;;f~------------------
PE
B LSBsOF
WORDM+2
C451-23
Output Enable Timing[41, 42]
CKR
______----J/
READM+1
,'---------
LOW
Oo-a
VAUDDATA
VALID DATA
WORDM
WORDM+1
C451-24
Notes:
40. In this example, the FIFO is assumed to be programmed to check for
even parity.
41. This example assumes that the time from the CKR rising edge to valid
42. IfENRwasillGHaronndtherisingedgeofCKR(Le.,readdisabled),
the valid data at the far right wonld once again be word M instead of
wordM+1.
wordM+l~tA·
5-97
CY7C451
CY7C453
PRELIMINARY
Architecture
The CY7C451 and CY7C453 consist of an array of 512J21)48
words of9 bits each (implemented by an array of dual-port RAM
cells), a read~ter, a write--I!Ointer, control signals---,--CKR,
CKW, mR. ENw, MR,
FL, XI, XO), and flags (HF, BJF,
on.
PAm).
Resetting the FIFO
~
power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty condition
signified by PJF and PAm being LOW and HFbeillLIDGH. All
data outputs (00 _ 8) go low at the rising edge of MR. In order
for the FIFO to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is
LOW (unless ~ and/or nNW are IDGH or unless the device
is being programmed). Upon completion of the Master Reset
cycle, all data outputs will go LOW tAMR after MR is deasserted
All flags are guaranteed to be valid tMRF after JdR: is taken
IDGH.
FIFO OPERATION
When the nNW signal is active (LOW), data present on the
Do _ 8 pins is written into the FIFO on each rising edge of the
CKW signal. Similarly, when the I!NR signal is active, data in the
FIFO memol}' will be presented on the 00 _ 8 outputs. New data
will bENRnted on each rising edge of CKR while mR is active.
must set up tsEN before CKR for it to be a valid read
must occur tsEN before CKW for it to be a valid
function.
write function.
An output enable (On) pin is provided to three-litate the 00 - 8
outputs when 00 is not asserted. When OJ! is enabled, data in
the output register will be available to 00 _ 8 outputs after toE. If
devices are cascaded, the OS ·function will only output data on
the FIFO that is read enabled.
The FIFO contains overflow circuit!}' to disallow additional
writes when the FIFO is full, and underflow circuit!}' to disallow
additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its 00 _ 8 outputs even after additional reads occur.
mw
tions for the CY7C451 and CY7C453 are listed in 7hble 5. Programming resolution is 16 words for either device.
The. programmable JIAi!I! function is only valid when the
CY7C45l/453 are not cascaded. If the user elects not to program
the FIFO's flags, the default (P=1) is as follows: Almost Empty
condition (Almost Full condition) is activated when the
CY7C45l/453 contain 16 or less words (empty locations).
Parity is programmed with the D6 _ 8 bits. See 7hble 7 for a sumM8I}' of the various parity programming options. Data present on
D6 _ 8 during a program write will determine whether the FIFO
will generate or check even/odd parity for the data present on
Do-8 thereafter. If the user elects not to program the FIFO, the
parity function is disabled. Flag operation and parity are described in greater detail in subsequent sections.
Flag Operation
The CY7C451/413"provide three status pins when not cascaded.
The three pins, FJF, JI.i\F£, and HF. allow decoding of six FIFO
states (7hble 1). JIAi!I! is not available when FIFOs are cascaded
for depth expansion. All flags are synchronous, meaning that the
change of states is relative to one of the clocks (CKR or CKW, as
appropriate). The synchronous architecture guarantees some
minimum valid time for the flags. This time is typically equal to
approximately one cycle time. The Empty and Almost Empty flag
states are exclusively updated by each rising edge of the read
clock ~. For example, when the FIFO contains 1 word, the
next read (risingedgeofCKR while ENR:=LOW) causes the flag
pins to output a state that represents Empty. The Half Full, Almost Full, and Full flag states are updated exclusively by the write
clock (CKW). For example, if the CY7C453 FIFO contains 2047
words (2048 words indicate Full for the CY7C453), the next write
(rising edge of CKW while m'W=LOW) causes the flag pins to
output a state that is decoded as Full.
Table 1. Flag 1hJtb Table[43]
ElF
PAFE HF
Programming
0
0
1
The CY7C451 and CY7C453 are programmed during a master
reset cycle. IfMR and nNW are LOW, a rising edge on CKW will
write Do _ 8 inputs into the programming register. MR must be
set up a minimum of tsMRP before the program write rising edge
and held tHMRP after the program write falling edge. The user
has the ability to also perform a program read during the master
rese~e. This will occur at the rising edge of CKR when MR
and ENR: are asserted. The program read must be performed a
minimum of tFJ"P after a program write, and the program word
will be available tAP after the read occurs. If a program write
does not occur, a program read may occur a minimum of tSMRP
after Mir is asserted. This will read the default program value.
When free-running clocks are tied to CKW and CKR, programming can still occur during a master reset cycle with the adherence to a few additional timing parameters. The enable pins must
be set-up tSEN before the rising e~Wf CKW or CKR. Hold
and mR.
times of tHEN must also be met for
Data present on Do _ 5 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full)
flags will become active. See 7hble 1 for a description of the six
possible FIFO states. P in 7hble 1 refers to the decimal equivalent
of the bin8l}' number represented by Do _ 5. Programming op-
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
State
Empty
Almost
Empty
Less than
CY7C451
S12x9
Number of
Words In
FIFO
0
0
H(16·P)
1 H16·P)
or~ualto ~~.P)+H
Hal Full
Greater
than Half
Full
Almost
Full
Full
CY7C453
2Kx9
Number of
Words in
FIFO
(16· P)+lt
1024
257 t 511 (16· P)
1025 t
2047 -16·P
512 - (16 •
P)t511
512
2048 - (16 •
P) t 2047
2048
Note:
43. P is the decimal value of the binary number represented by DO _ 5 .
When programming the CY7C451/S3, P can have values from 0 to 15
for the CY7C451 and values from 0 to 63 for the CY7C453. See 1/W/e
5 for Do _ 5 representation. P = 0 signifies Almost Empty state =
Empty state.
5-98
~~PRESS
-=-IF
CY7C451
CY7C453
PRELIMINARY
SEMICONDUCIOR
Flag Operation (continued)
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half Full,
Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware
that if a boundary (Empty, Almost Empty, Half Full, Almost Full,
or Full) is crossed due to an operation from a clock that the flag is
not synchronized to (Le., CKW does not affect Empty or Almost
Empty), a flag update cycle is necessary to represent the FIFO's
new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty
and Almost Empty flags; CKR is the opposite clock for Half Full,
Almost Full, and Full flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the
FIFO.
When updating flags, the CY7C451/453 must make a decision as to
whether or not the opposite clock was recognized when a clock updates the flag. For example (when updating the Empty flag), if a
write occurs at least tSKEWl after a read, the write is guaranteed
not to be included when CKR updates the flag. If a write occurs at
least tSKEW2 before a read, the write is guaranteed to be included
when CKR updates flag. If awrite occurs within tSKEWl/tSKEW2 after or before CKR, then the decision of whether or not to include
the write when the flag is updated by CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the boundaryflags (Empty, Full). Both operations are described below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
The Empty flag is synchronized to the CKR signal (Le., the Empty
flag can only be updated by a clock pulse on the CKR pin). An
empty FIFO that is written to will be described with an Empty flag
state until a rising edge is presented to the CKR pin. When making
the transition from Empty to Almost Empty (or Empty to Less
than or Equal to Half Full), a clock cycle on the CKR is necessary
to update the flags to the current state. In such a state (flags show-
ing Empty even though data has been written to the FIFO), two
read cycles are required to read data out of FIFO. The first read
serves only to update the flags to the Almost Empty or Less than or
Equal to Half Full state, while the second read outputs the data.
This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number
of words in FIFO). It sinl~-asserts the Empty flag. The flag is
updated regardless of the ENR state. Therefore, the update occurs
even when ENR is unasserted (HIGH), so that a valid read is not
necessaryto update the flags to correctly describe the FIFO. In this
example, the write must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the write will be
included in the count when CKR updates the flags. When a freerunning clock is connected to CKR, the flag is updated each cycle.
Table 2 shows an example of a sequence of operations that update
the Empty flag.
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (Le., the Full flag
can only be updated by a clock pulse on theCKW pin). A full FIFO
that is read will be described with a Full flag until a rising edge is
presented to the CKW pin. When making the transition from Full
to Almost Full (or Full to Greater Than Half Full), a clock cycle on
the CKW is necessary to update the flags to the current state. In
such a state (flags showing Full even through data has been read
from the FIFO), two write cycles are required to write data into the
FIFO. The first write serves only to update the flags to tlte Almost
Full or Greater Than Half Full state, while the second write inputs
the data. This flTst write cycle is known as the latent or flag update
cycle because it does not affect the data in the FIFO or the count
(number of words in the FIFO). It sinl~-asserts tlte Full flag.
The flag is updated regardless of the ENW state. Therefore, the
update occurs even when ENW is deasserted (HIGH), so thll:t a
valid write is not necessary to update the flags to correctly descnbe
the FIFO. In this example, the read must occur at leasttSKEw2 before tlte flag update cycle in order for the FIFO to guarantee that
the read will be included in the count when CKW updates the flags.
When a free-running clock is connected to CKW, the flag updates
each cycle. Full flag operation is sinlilar to the Empty flag operation described in Table 2.
Thble 2. Empty Flag (Boundary Flag) Operation Example
Status Before Operation
Current
Number
of Words
State of
FIFO
ElF AFE HF in FIFO Operation
0
0
1
0
Write
Empty
(ENW= 0)
Empty
0
0
1
1
Write
(ENW=O)
Empty
0
0
1
2
Read
(ENR=X)
AE
1
0
1
2
Read
(ENR= 0)
1
AE
0
1
1
Read
(ENR= 0)
0
Write
Empty
0
1
0
(ENR= 0)
Empty
1
1
0
Read
1
(ENR=X)
AE
1
0
1
1
Read
(ENR= 0)
Status After Operation
0
AFE
0
HF
1
Number
of words
in FIFO
1
Empty
0
0
1
2
Write
AE
1
0
1
2
Flag Update
AE
1
0
1
1
Read
Empty
0
0
1
0
Empty
0
0
1
1
Read(transitionfromAlmost Empty to Empty)
Write
AE
1
0
1
1
Flag Update
Empty
0
0
1
0
Read(transitionfromAlmost Empty to Empty)
Next State
of FIFO
Empty
5-99
ElF
Comments
Write
•
CY7C451
CY7C453
PRELIMINARY
Non-Boundary FIags (Almost Emp~ HalfFull,Almost Full)
The CY7C451/453 feature programmable Almost Empty and A1most Full flags. Each flag can be programmed a specific distance
from the corresponding boundaty flags (Empty or Full). The
flags can be programmed to be activated at the Empty or Full
boundary, or at a distance of up to 1008 wordsllocations for the
CY7C453 (240wordsllocations for the CY7C451) from the Em,.
ty/Full boundary. The programming resolution is 16 wordsllocations. When the FIFO contains the number of words or fewer for
which the flags have been programmed, the PAm flag will be asserted signifying that the FIFO is Almost Empty. When the FIFO
is within that same number of empty locations from being Full,
the PAm will also be asserted signifying that the FIFO is Almost
Full. The 'RF flag is decoded to distinguish the states.
The default distance (CY7C451/453 not programmed) from
where ~ becomes active to the boundary (Empty, Full) is 16
wordsllocations. The Almost Full and Almost Empty flags can be
programmed so that they are 0~1y a~e at. Full fi!1d Em~ty
boundaries. However, the operation wIll remam consIStent With
the non-boundary flag operation that is discussed below.
Almost Empty is only updated by CKR while Half Full and Almost Full are updated by CKw. Non-boundary flags employ flag
update cycles similar to the boundary flag latent cycles in order to
update the FIFO status. For example, if the FIFO just reaches
the Greater than Half Full state, and then two words are read
from the FIFO, a write clock (CKW) will be required to update
the flags to the Less than Half Full state. However, unlike the
boundary flag latent cycle, the state of the enable pin (l!NW in
this case) affects the operation. Therefore, set-up and hold times
for the enable pins must be met (tsEN and tHEN). If the enable
pin is active during the~da~cle, the count and data are
updated in addition to PAFE and HF. If the enable pin is not asserted during the flag update cycle, only the flags are updated
Thbles 3 and 4 show an example of a sequence of operations that
update the Almost Empty and Almost Full flags.
Programmable Parity
The CY7C451/453 also features even or odd parity checking and
generation. D6 _ 8 are used during a program write to describe
the parity option desired. Thble 6 gives a summary of programmable parity options. If user elects not to program the device,
then parity is disabled. Parity information is provided on one
multi-mode output pin (08/PG7PE). The three possible modes
are described in the following paragraphs. Regardless of the
mode selected, the OE pin retains three-state control of all 9
00 - 8 bits.
Parity Disabled (Q8 mode)
When parity is disabled (or user does not program parity option)
the CY7C451/453 stores all 9 bits present on Do _ 8 inputs internally and will output all 9 bits on 00 - 8.
Parity Generate (pG mode)
This mode is used to generate either even or odd parity (as programmed) from Do _ 7. D8 input is ignored. The parity bit is
stored internally as D8 and during a subsequent read will be
available on the PG pin along with the data word from which the
parity was generated (00 _ 7). For example, if parity generate is
set to ODD and the DO _ 7 inputs have an EVEN number of Is,
PG will be HIGH.
If the expected parity is present, D8 will be set HIGH in~ernally.
When this word is later read, PP; will be HIGH. If a panty error
occul!L!>8 will be set WW internally. When this word is later
read. PH will be Ww, For example, if parity check is set to odd
and Do _ 8 have an even number of ls, a parity error occurs.
When that word is later read, Pn will be asserted (WW).
Width Expansion Modes
During width expansion all flags (programmable and nonprogrammable) are available. The CY7C451/453 can be expanded in
width to provide word width greater than 9 in increments of 9.
Duringwidth expansion mode all control line inputs arecommo~.
When the FIFO is being read near the Empty (Full) boundary, It
is important to note that both sets of flags should be checked to
see if they have been updated to the Not Empty (Not Full) condition to insure that the next read (write) will perfOrtD the same operation on all devices.
Checking all sets of flags is critical so that data is not read from
the FlFOs "staggered" by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than tSKEW2 after the first
write to two width-expanded devices, A and B, device A may go
Almost Empty (read recognized as flag update) while device B
stays Empty (read ignored). This occurs because a read can be
either recognized or ignored if it occurs within tSKEW2 of a write.
The next read cycle outputs the first half of the frrst word on device A while device B updates its flags to Almost Empty. Subsequent reads will continue to output "staggered" data assuming
more data has been written to FlFOs.
Depth Expansion Mode
The CY7C451/453 can operate up to 50 MHz when cascaded.
expansion is accomplished by connecting expansion out
of the first device to expansion in
of the next device,
with
of the last device connected to Xl ofthe first device. The
first device has its first load pin (F[) tied to VSS while all other
devices must have this pin tied to Vce. The first device will be the
first to be write and read enabled after a master reset
Proper operation also~res that all cascaded devices have
common CKw, CKR, ENW, rn;m, Do - 8, 00 - 8, and QR: pins.
When cascaded, one device at a time will be read enabled so as to
avoid bus contention. By assertingXOwhen appropriate, the currently enabled FIFO alerts the next FIFO that it should be enabled The next rising edge on eKR puts 00 _ 8 outputs of the
first device into a high-impedance state. This occurs regardless of
the state ofBNl{ or the next FIFO's Empty flag. Therefore, if the
next FIFO is empty or undergoing a latent cycle, the 00 _ 8 bus
will be in a high-impedance state until the next device receives its
first read, which brings its data to the 00 _ 8 bus.
§j
am
Program Write/Read of Cascaded Devices
Programming of cascaded FlFOs is the same as for a single device. Because the controls of the FlFOs are in parallel when cascaded, they all get programmed the same. During program mode,
only parity is programmed since Almost Full and Almost Empty
flags are not available when CY7C451/453 are cascaded. Only
the "first device" (FIFO with }:'[=LOW) will output its program
register contents on 00 _ 8 during a program read. 00 _ 8 of all
other devices will remain in a high-impedance state to avoid bus
contention.
Parity Check (liE mode)
If the CY7C451/453 is programmed for parity checking, the
FIFO will compare the parity of Do _ 8 with the program register.
5-100
~
=.
~
CY7C451
CY7C453
PRELIMINARY
'= CYPRESS
SEMlCONDUcrOR
~F
CKW
ENR
rW
i
J\...
-V
CKR
XI
00-8
0 0 -8
CKW
CKR
CY7C451/3
OATAIN
00-8
MR
--
ENW
MR
BiiR
~
HF
Ell"
OE
OATAO UT
00- 8
PAFE/XO f [ l
VSS
""a/
00-8
CKW
ENW
-
IL
00-8
CKR
ENR
CY7C451/3
--
-=
XI
MR
I
IX
~
HF
~/F
OE
I
PAFE!XO f[
FULL
EMP
Vee
W
Figure 1. Depth Expansion with CY7C4S1I3
lhble 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[44]
Status Before Operation
Status After Operation
NumDer
Number
Current State
of Words
Next State
ofwords
of FIFO
AFE
OF
in
FIFO
ElF
of FIFO
Operation
ElF PAFE OF in FIFO
AE
1
0
1
32
Write
AE
1
0
1
33
(ENW= 0)
AE
34
1
0
1
33
Write
AE
1
0
1
(ENW= 0)
AE
1
0
1
34
Read
HF
(ENW= 1)
1
0
494
2030
Write
>HF
(ENW=O)
1
0
495
2031
Write
AF
(ENW=O)
ElF
1
AF
1
AF
1
>HF
1
>HF
1
1
0
0
494
2030
Read
1
1
0
494
2030
FiagUpdate
1
1
0
495
2031
Write
1
0
0
496
2032
Write~sition
>HFtoAF)
1ltble S. Programmable Almost Full/Almost Empty Options - CY7C4S11CY7C4S3[46]
DS
0
0
0
0
D4
0
0
0
0
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
DO
0
1
0
1
PAFE Active when CY7C4S1/4S3 is:
Completely Full and Empty.
16 or less locations from Empty/FuII (default)
32 or less locations from Empty/FuII
48 or less locations from Empty/FuII
224 or less locations from Empty/FuII
240 or less locations from Empty/FuII
992 or less locations from Empty/FuII
1008 ot less locations from Empty/Full
1ltble 6. Programmable Parity Options
D8
0
1
1
1
D7
X
0
0
1
1
1
D6
X
0
1
0
1
Condition
Parity disabled.
Generate even parity on PG output pin.
Geherate odd parity on PG output pin.
Check for even parity. Indicate error on PE output pin.
Check for odd parity. Indicate error on PE output pin.
Notes:
44. Applies to both CY7C451 and CY7C453 operations when devices are
programmed so that Almost Empty hecomes active when the FIFO
contains 32 or fewer words.
45. Programmedso that Almost Full becomes active when the FIFO con·
tains 16 or less empty locations.
46. D4 and D5 are don't care for CY7C451.
47. Referenced in Table 1.
5-102
PLq'j
0
1
2
3
CY7C451
CY7C453
PRELIMINARY
Ordering Information
Package
'JYpe
Operating
Range
Speed
CY7C451-14DC
D32
Commercial
14
CY7C451-14JC
J65
Speed
(ns)
14
20
30
Ordering Code
CY7C451-14LC
L55
CY7C4S1-14DI
CY7C451-14JI
032
J65
Industrial
CY7C451-14DMB
032
CY7C451-14LMB
L55
(ns)
Package
1YPe
Operating
Range
CY7C453-14DC
D32
Commercial
CY7C453-14JC
J65
Ordering Code
CY7C453-14LC
L55
CY7C453-14DI
CY7C453-14JI
D32
J65
Industrial
Military
CY7C453-14DMB
D32
Military
L55
Commercial
CY7C453-14LMB
CY7C453-2ODC
D32
CY7C453-2OJC
CY7C453-20LC
J65
L55
Industrial
CY7C453-20DI
D32
CY7C453-20JI
CY7C453-20DMB
J65
D32
Military
CY7C453-20LMB
CY7C453-30DC
L55
D32
Commercial
CY7C453-3OJC
J65
CY7C451-20DC
D32
CY7C451-2OJC
CY7C451-20LC
J65
L55
CY7C451- 20DI
032
CY7C451-20JI
J65
CY7C451-2ODMB
032
Military
CY7C451-20LMB
CY7C451-30DC
L55
D32
Commercial
CY7C451-3OJC
J65
CY7C451-30LC
L55
CY7C451-30DI
J65
CY7C451-30JI
CY7C451-30DMB
D32
032
CY7C451-30LMB
L55
20
30
Commercial
(I)
Industrial
CY7C453-30LC
L55
Industrial
CY7C453-30DI
D32
Industrial
Military
CY7C453-30JI
CY7C453-30DMB
J65
D32
Military
CY7C453-30LMB
L55
5-103
•
o
u.
u::
PRELIMINARY
N.UIJTARYSPECnnCATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IJX
Icc
los
Switching Characteristics
Parameters
Subgroups
tCKW
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tCKR
tCKH
tCKL
tA
tOH
tFH
tSD
tHO
tSEN
tHEN
tOE
tpG
tPE
tFD
tSKEWl
tSKEW2
tpMR
tscMR
toHMR
tMRR
tMRF
tAMR
tSMRP
tHMRP
tFfP
tAP
tOHP
Document#: 38-00125-C
5-104
CY7C451
CY7C453
CY7C460
CY7C462
CY7C464
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Cascade able 8K X 9 FIFO
Cascade able 16K X 9 FIFO
Cascadeable 32K X 9 FIFO
Features
Functional Description
• 8Kx 9,16Kx 9, 32Kx 9 FIFO buffer
memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent oC depth/width
• Low operating power
- Icc (max.) = 160 mA
(commercial)
- Icc (max.) = 165 mA (military)
The CY7C460, CY7C462, and CY7C464
are respectively, 8K, 16K, and 32K words
by 9-bit wide flrst-in-flrst-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same
sequential order that it was written. Full
and Empty flags are provided to prevent
overrun and underrun. Three additional
pins are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered
in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
33.3 MHz. The write operation occurs
when the write (Jr). signal is LOW. Read
occurs when read (R) goes LOW. The nine
•
•
•
•
•
•
HalC Full Dag in standalone
Empty and Full Dags
Retransmit in standalone
Expandable in width and depth
SV ± 10% supply
PLCC, LCe, and 600-mil DIP
packaging
• Tn. compatible
• Three-state outputs
• Pin compatible to IDT7205 and
IDT7206
Logic Block Diagram
data outputs go to the high-impedance
state when R" is mOHo
A Half Full (IIP) output flag is provided
that is valid in the standalone (single device) and width expansion configurations.
In the depth expansion configuration, this
pin provides the expansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFOs to retransmit
the data. Read enable (It) andwrite enable
(Jr) must both be mGH during a retransmit cycle, and then R is used to access the
data.
The CY7C460, CY7C462, and CY7C464
are fabricated using an advanced O.8-micronN-well CMOS technology. InputESD
protection is greaterthan2000V and latchup is prevented by careful layout, guard
rings, and a substrate bias generator.
Pin Configurations
DATA INPUTS
PLCCJLCC
Top View
(Do-Dal
0(1) 0«013:
D.
0,
~ >8 0 "" 01/)
4
D.
07
5
6
NO
Do
XI
FF
a,
9
10
11
NO
12
00
7C46D
7C462
1'rAIT
J;lI!
7C464
EI'
XO!HF'
Or
00
Do
d" d"::1 ~ Ia: c'" d"
DATA OUTPUTS
(ao-aal
0
11m
DIP
TopY"lI!W
0461).2
W
v..
D.
D.
D.
0,
D.
D.
D.
D.
07
FrIRT
XI
FF
EF
a.
a,
a.
a.
a.
OND
J;lI!
XOIRF
a7
a.
a.
a.
II
FrJm"
C46Il-3
0460·1
5-105
•
(I)
o
u.
u::
CY7C460
CY7C462
CY7C464
~
~~PRF$
SEMlCCtIDUCl'OR
PRELIMINARY
~,
Selection Guide
7C460-20
7C462-20
7C464-20
28.5
20
7C460-15
7C462-15
7C464-15
33.3
15
160
Frequency (MHz)
MaximumAccess Time (ns)
Maximum Operating
I Commercial
Current (rnA)
I Military
7C460-25
7C462-25
7C464-25
28.5
25
145
165
165
7C460-40
7C462-40
7C464-40
20
40
125
145
Maximum Ratings
(Above which the useful life maybe impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°C to +150°C
Ambient Temperaturewith
PowerApplied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DClnputVoltage ...................... - 3.0Vto +7.0V
PowerDissipation ................................ 1.0W
Output Current, into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Commercial
Industrial
Military!l]
Ambient
Thmperature
Vee
O°Cto + 70°C
5V± 10%
- 40°C to +85°C
5V± 10%
- 55°Cto +125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel2]
7C460·15
7C462·15
7C464-15
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
Thst Conditions
Vee = Min.,loH = - 2.0rnA
2.4
Vee = Min., IOL = 8.0 rnA
Com'l
Mi1Jlnd
2.0
ISB!
Standby Current
IsB2
Power·DownCurrent
los
Output Short
CircuitCurrent[5]
2.4
0.4
GND~VI~VCC
-10
R2VIH,GND~VO~Vcc
-10
+10
Com'113j
Mil/Indl4 j
0.4
2.0
2.2
0.4
2.0
2.2
V
V
0.8
+10
-10
0.8
+10
-10
0.8
+10
IJA
-10
+10
-10
+10
-10
+10
IJA
145
165
25
125
145
25
rnA
30
20
25
30
20
25
-90
25
30
20
-90
4.
V
-10
165
Icc (military) =
25
-90
-90
V
rnA
rnA
rnA
145_mA + [(f - 20)' 2.5 mA/MHz]
forf~20MHz
5.
forf~20MHz
where f = the larger of the write or read operating frequency.
7C460·40
7C462·40
7C464·40
2..4
0.4
160
Aliinputs - VIH Com'l
Min.
Mil/Ind
All Inputs VCC
Com'l
-0.2V
Mil/Ind
Vee - Max., VOUT - GND
Notes:
1. . TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing in·
formation.
3. Icc (commercial) = 125_mA + [(f - 20)' 2.5mNMHz]
2..4
2.2
0.8
+10
Vee = Max.,
lOUT = ornA
7C460·25
7C462·25
7C464·25
Min. Max. Min. Max. Min. Max. Min. Max. Units
Description
Output HIGH
Voltage
Output LOW Voltage
Input IDGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
Operating Current
7C460·20
7C462·20
7C464·20
6.
5-106
where f = the larger of the write or read operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should uot exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
·~
~.CYPRESS
CY7C460
CY7C462
CY7C464
PRELIMINARY
~_, SEMlCONDUcroR
Capacitance [6]
Description
InputCapacitance
Output Capacitance
Parameters
qN
CoUT
Thst Conditions
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
Max.
5
Units
7
pF
pF
AC Test Loads and Waveforms
R1500.(1
R1500.(1
---J-.,
5V C>-_ _
5V C>----"""'-,
OUTPUTC>------1P---...
FI
INCLUDING
JIGAND _
333.(1
-=-
SCOPE -
5PFI
R2
30 P
3'OV~
C460-4
GND
R2
333.(1
SCOPE -
10%900/0
..s.5ns.....
INCLUDING
JIGAND _
k-
•
C460-5
(b)
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTC>---------
C460-7
IMRSC [11]
IpMR
~
A,W[lD]
.~
~IEFl~
Iwpw
\:
I---
IHFH
I--
IFFH
I-
IRMR ...
-r-
------------~}------------------Notes:
7. Thst conditions assume signal transmission time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IOrJIOH
and 30 pF load capacitance, as in part (a) of AC Thst Load, unless
otherwise specified.
8. tHZR and tOVR use capacitance loading as in part (b) ofAC Thst Load.
C46(H!
A IDOH-to-LOW transition of either the write or read strobe causes
a HIOH-to-LOW transition of the responding flag. Correspondingly,
a low-to-high strobe transition causes aLOW-to-IDOH flag transition.
10. Wand R = VIH around the rising edge ofMR.
11. tMRSC = tpMR + tRMR'
9.
5-108
CY7C460
CY7C462
CY7C464
~
~~PRESS
"'¥!!.!ifi'.' SEMICONDUCTOR
PRELIMINARY
Switching Waveforms
Half FoIl Flag
w
HALF FUll
HALF FUll +1
/
i--
tWHF
"
-1
~
HALF FUll
-
tRHF
l-
rC460-9
Last Write to First Read FoIl Flag
LAST WRITE
R
--+-------+..,.
ADDITIONAL
READS
FIRST READ
FIRST WRITE
(I)
o
u..
~
w
~-_f_-....... I
C460-1 0
Last READ to First WRITE Empty Flag
LAST READ
W - - t - - - - - - - - t -....
ADDITIONAL
WRITES
FIRST WRITE
FIRST READ
EF-+-t---.I
DATA OUT
--+--(
C460-11
Retransmid 12,13]
tRTC
-tPRT
R,w
I+Notes:
12, tRTC = tpRT
+ tRTR,
•
t RTR
----10
C460-12
13. EF, HF and FF may change state during retransmit as a result of the
offset of the read and write pointers, but flags will be valid at tRTG
5-109
&;~PRFSS
~., SEMICONDUClDR
PRELIMINARY
CY7C460
CY7C462
CY7C464
Switching Waveforms (continued) .
Empty Flag and Read Bubble-Through Mode
DATA IN
W --1-----.
EF----+-----------------~----J
DATA OUT
C460-13
Full Flag and Write Bubble-Througb Mode
W
~---+-------~----JI
DATAIN
---+---------------------------l
t~,
DATA OUT
-------QS.M...-D-A-JA-VA-U-D-)@~---------------------------------C460-14
5-110
·~PRfSS
CY7C460
CY7C462
CY7C464
PRELIMINARY
- . F SEMlCONDUClDR
Switching Waveforms
(continued)
Expansion Timing Diagrams
w---""""
X01(X12l1141
---------------I===j-
DATA VALID
C480·15
Notes:
14. Expansion out of device 1 (XO!) is connected to expansion in of device 2 (XI2).
5-111
-===-=$iiiE~PRFSS
~; SEMICOIDUCTOR
PRELIMINARY
CY7C460
CY7C462
CY7C464
Architecture
Retransmit
Resetting the FIFO
The retransmit featlire is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiverand retransmitted if necessary. The retransmit (RT) input is
active in the standalone and width expansion modes. The retransmit featlire is intended for use when a number of writes
equal-to-or-less-thanthe depth of the FIFO have occurred since
the last MR cycle. A LOW pulse on RT resets th~internJ!.l read
pointer to the first physical location of the F.I~O. R and.W must
both be HIGH while and tRJ"R afterretransIDItJsLOW. Wlthevery
read cycle afterretransmit, previously accessed d~tais r~ad and the
read pointer incremented until equal to the wnte pomter. Full,
Half Full, and Empty flags are governed by the rel~tivelocations~f
the read and write pointers and are updated durm~etransIDIt
cycle. Data written to the FIFO after activation of RT are transmittedalso.
The full depth of the FIFO can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Upon power up, the FIFO must be reset with a mast~~ rese.t (~.R)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty ~ (EF) being LOW, andJJOth the Half_Full (HF),
and Full flags (FF) being HIGH. Read (R) and write (W) must be
HIGH tRPw/twpw before and tRMR after the rising edge of MR
for a valid reset cycle. If reading from the FIFO after a reset cycle
is attempted, the outputs will all be in the high-impedance state.
Writing Data to the FIFO
The availability of at least one~mpty location is indicated by a
HIGH FE The falling edge ofW initiates a write cycle. Dat~ ~p
pearingat the inputs (Do - Ds) tSD before and tHO after the nsmg
edge ofW will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGHtransition ofW for an empty FIFO. HF goes
LOW tWHF after the faIling ed~fW following the FIFO actJIally
being half full. Therefore, the HF is active once.the FIFO ~ filled
to half its capacity plus one word. HFwill remam LOW while less
than one half of total mem..2!Y is available for writ~~. The
LOW-to-HIGHtransition ofHF occurs tRHFafterthe nsmgedge
ofR when the FIFO goes from half full + 1 to half full. HF is available in standalone and width expansion modes. FF goes LOW
tWFF after the faIling edge of W, during the cycle in which the. last
available location is filled. Internal logic prevents overnmnmg a
full FIFO. Writes to a full FIFO are ignored and the write pointer
is not incremented. FF goes HIGH tRFF after a read from a full
FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Qo - Qsl.are in a high-impedance condition between read operations (R HIGH), when the FIFO is empty,. or
when the FIFO is not the active device in the depth expansIOn
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition ofEE When the FIFO is empty, the
outputs are in a high-impedance state. Reads t~ an empty FIFO
are ignored and do not increment the read pomter..Fro!:? the
empty condition, the FIFO can be read tWEF after a valid wnte.
Standalone and width expansion modes are set by groundin~
pansion in (XI) and tying first load (FE) to Vee prior to a MR
cycle. FlFOs can be expanded in width to provide word widths
greater than nine in increments of nine. During width expansion
mode, all control line inputs are common to all devices, and flag
outputs from any device can be monitored.
Depth Expansion Mode (see Figure 1)
DeptheX(lansionmode is~nte.redwhen, during a MR:cyc~e, ~an
sion out (XO) of one deVice IS connect~d to expansIOn 1!UXI) of
the next device, with XO of the last deVice connected to XI of the
first device. In the depth expansion mode, the firstload (FL) input,
when grounded, indicates that this is the first part to be loaded. All
other devices must have this pin HIGH. To enable the correct
FIFO, XO is pulsed LOW when the last physical .location of the
previousFIFO is written to and is pulsed L~W agam when the last
physical location is read. Only one F~FO IS enabled fo~ read ~d
one is enabled for write at any given time. All other deVices are m
standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO c~ be. created with word
widths in increments of nine. When expandmg m depth, a composite FF is created byORi!!Jl!he FFs together. Likewise, ~compostie
EFiscreatedbyORingEFstogether.HFandRTfunctJonsarenot
available in depth expansion mode.
5-112
=. ~
-...-J= CYPRESS
PRELIMINARY
~.iF' SEMlCONDUcrOR
xo
IN
R
EF
FF
D
CY7C460
CY7C462
CY7C464
9
/
I
I
9,""
/-,,/
9
CY7C460
CY7C462
CY7C464
/
i'[
~
Vee
~
Xl
-
FULL
tn
LL.
EF
FF
9,"",/ /
EMPlY
CY7C460
CY7C462
CY7C464
V
i'[
1-----0
l-
X!
XO
L....
L-..-
•
o
XO
*
FF
i~
EF
CY7C460
CY7C462
CY7C464
AS
X!
~
~
• FIRST DEVICE
C460-17
Figure 1. Depth Expansion
5-113
Ii:
&:~mss
CY7C460
CY7C462
CY7C464
PRELIMINARY
~_., SEMICCtIDUCTOR
Ordering Information
Speed
(ns)
15
20
25
40
CY7C460-15DC
Package
1YPe
D16
CY7C460-15JC
J65
CY7C462-15JC
J65
CY7C460-15LC
L55
CY7C462-15LC
L55
CY7C460-15PC
PIS
CY7C462-15PC
PIS
CY7C460-15JI
J65
CY7C460-15PI
PIS
CY7C460-2ODMB
CY7C460-20LMB
016
L55
Military
CY7C460-25DC
CY7C460-25JC
016
J65
Commercial
CY7C460-25LC
CY7C460-25PC
CY7C460-25JI
J65
CY7C460-25PI
PIS
CY7C460-25DMB
016
CY7C460-25LMB
L55
CY7C460-40DC
016
CY7C460-4OJC
J65
CY7C460-4OLC
CY7C460-4OPC
CY7C460-4OJI
J65
CY7C460-4OPI
PIS
CY7C460-4ODMB
D16
CY7C460-4OLMB
L55
Ordering Code
Operating
Range
Speed
(ns)
Commercial
15
Industrial
Package
Ordering Code
CY7C462-15DC
1YPe
016
CY7C462-15JI
J65
CY7C462-15PI
PIS
CY7C462-2ODMB
016
CY7C462-20LMB
L55
CY7C462-25DC
D16
CY7C462-25JC
J65
L55
CY7C462-25LC
L55
PIS
CY7C462-25PC
PIS
20
25
Industrial
CY7C462-25JI
J65
CY7C462-25PI
PIS
CY7C462-25DMB
016
CY7C462-25LMB
L55
CY7C462-40DC
016
CY7C462-40JC
J65
L55
CY7C462-40LC
L55
PIS
CY7C462-40PC
PIS
Military
Commercial
Industrial
Military
5-114
40
CY7C462-40JI
J65
CY7C462-40PI
PIS
CY7C462-40DMB
016
CY7C462-40LMB
L55
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
4.:.~
• -=
PRELIMINARY
CYPRESS
. , SEMICONDUCTOR
CY7C460
CY7C462
CY7C464
Ordering Information (continued)
Speed
(ns)
15
20
25
40
Package
'JYpe
Operating
Range
CY7C464·15DC
D16
Commercial
CY7C464-I5JC
J65
CY7C464-I5LC
L55
CY7C464· I5PC
P15
Ordering Code
CY7C464-15JI
J65
CY7C464-15PI
P15
CY7C464-20DMB
D16
CY7C464-20LMB
L55
CY7C464-25DC
D16
CY7C464-25JC
J65
CY7C464-25LC
L55
CY7C464-25PC
PIS
CY7C464-25JI
J65
CY7C464-25PI
PIS
CY7C464-25DMB
D16
CY7C464-25LMB
L55
CY7C464-40DC
D16
CY7C464-4OJC
J65
CY7C464-40LC
L55
CY7C464-40PC
PIS
CY7C464-40JI
J65
CY7C464-40PI
PIS
CY7C464-40DMB
D16
CY7C464-40LMB
L55
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
5-115
•
CY7C460
CY7C462
CY7C464
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIH
VILMax.
IJX
Icc
ISBl
ISB2
los
Switching Characteristics
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Parameters
Subgroups
9,10,11
9,10,11
tA
9,10,11
tRR
9,10,11
tpR
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
twc
9,10,11
tpw
9,10,11
tHWZ
9,10,11
tWR
9,10,11
tSD
9,10,11
tHD
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRTC
9,10,11
tpRT
9,10,11
tRTR
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document#: 38-00141-B
tRC
5-116
CY7C470
CY7C472
CY7C474
PRELIMINARY
CYPRESS
SEMICONDUCTOR
8Kx 9 FIFO, 16Kx 9 FIFO,
32K x 9 FIFO with Programmable Flags
Features
Functional Description
• 8Kx9, 16K x 9, and 32Kx 9 FIFO
buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write
independent of depth/width
• Low operating power
- Icc (max.) = 160 mA
(commercial)
- Icc (max.) 165 mA (military)
• Programmable Almost FuWEmpty
nag
• Empty, Almost Empty, Half Full,
Almost Full, and Full status nags
• Programmable retransmit
• Expandable in width
• 5V ± 10% supply
• TTL compatible
• Three-state outputs
• Proprietary 0.8-micron CMOS
technology
TheCYC47XFIFOseriesconsistsofhigbspeed, low-power, first-in first-out (FIFO)
memories with programmable flags and
The
CY7C47D,
retransmit mark.
CY7C472,and CY7C474 are 8K, 16K, and
32K words by 9 bits wide, respectively.
They are offered in 600-mil DIP, PLCC,
and LCC packages. Each FIFO memory is
organized such that the data is read in the
same sequential order that it was written.
Threestatus pins-Empty/Full (ElF), Programmable Almost Full/Empty (PAFE),
and Half Full (HF)-are provided to the
user. These pins are decoded to determine
one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half
Full, Almost Full, and Full.
The read and write operations may be
asynchronous; each can occur at a rate of
33.3 MHz. The write operation occurs
=
Logic Block Diagram
whenthewrite(W)signalgoesLOW.Read
occurs when read (R) goes LOW. The nine
data outpu~ go into a higb-impedance
state when R is HIGH.
The user can store the value of the read
pointerfor retransmit by using the MARK
pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer to the value stored in
themarkpointer.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFO to resend the
data. With the mark feature, retransmit
can start from any word in the FIFO.
The CYC47X series is fabricated using a
proprietary D.8-micron N-well CMOS
technology.InputESD protection is greaterthan 2001Vand latch-up is prevented by
the use of reliable layouttechniques, guard
rings, and a substrate bias generator.
Pin Configurations
DATA INPUTS
(Do-D.)
DIP
Top View
PLCC/LCC
Top View
oCt) cCDI;:
~ >8 c..... cln
0,
0,
Do
MARK
8
00
a,
NC
a.
w
7C470·2
W
Ds
D.
D3
07
D2
NC
D1
AT
Do
Mil MARK
ElF PAFE
RF
00
Or
01
a.
02
03
Os
GND
7C47Q.3
DATA OUTPUTS
(Oo-a.)
70470-1
5-117
•
U)
o
u.
ii:
CY7C470
CY7C472
CY7C474
~
=- .. ~
-=-_''.is
=::
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Cutrent (rnA)
7C470-15
7C472-15
7C474-15
7C470-20
7C472-20
7C474-20
7C470-25
7C472-25
7C474-25
33.3
15
160
28.5
20
28.5
25
145
165
I Commercial
I
Military/Industrial
165
Maximum Ratings
Storage Temperature _................ - 65°C to + 150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Power Dissipation ................................ l.OW
Output Current, into Outputs (LOW) ..... . . . . . . . . .. 20 rnA
7C470-40
7C472-40
7C474-40
20
40
125
145
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Temperature
Range
Commercial
Vee
5V ± 10%
O°Cto +70°C
Industrial
Military(J]
- 40°C to +85°C
5V ± 10%
- 55°Cto +125°C
5V± 10%
Electrical Characteristics Over the Operating Range[2]
7C470-15
7C472-15
7C474-15
Parameter
Description
Thst Conditions
Output HIGH
Voltage
VOL
VIH
Output LOW Voltage Vee - Min., IOL - 8.0 mA
Input HIGH Voltage Vee = Max.,
Com'!
lOUT = ornA
Mil/Ind
VIL
IIX
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
Operating Current
Icc
2..4
2.4
Vee = Min.,
IOH = - 2.0 rnA
0.4
ISBZ
lospJ
Standby Current
0.4
7C470-40
7C472-40
7C474-40
GND~VI~Vee
-10
R.? VIH,
-10
+10
2.4
0.4
2.0
2.2
2.2
0.8
+10
V
0.4
2.0
2.2
Com'II~J
Al! InputsVIHMin.
0.8
+10
0.8
+10
0.8
V
-10
-10
+10
IlA
-10
+10
-10
+10
-10
+10
IlA
125
145
25
30
20
25
-90
rnA
160
165
Com'!
Mil/Ind
Com'!
MiVInd
25
30
20
-90
Vee = Max.,
VouT=GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. !ce (commercial) = 125 rnA + (£ - 20) • 2.5 mNMHz for
f.?, 20 MHz
where f = the larger of the write or read operating frequency.
V
V
-10
GND~Vo~Vec
Power-DownCurrent All Inputs '=
Vee- 0.2V
Output Short Circuit
Current
2..4
2.0
Miil4J/lnd
ISBl
7C470-25
7C472-25
7C474-25
Min. Max. Min. Max. Min. Max. Min. Max. Units
VOH
loz
7C470-20
7C472-20
7C474-20
25
-90
145
165
25
30
20
25
-90
rnA
rnA
rnA
!ce (military) = 145 rnA + (f - 20)·2.5 mNMHz for
f.?,20MHz
where f = the larger of the write or read operating frequency.
5. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
4.
5-118
-~
.
;~ CYPRESS
CY7C470
CY7C472
CY7C474
PRELIMINARY
~.' SEMICONDUCTOR
Capacitance [6]
Parameters
CIN
COUT
Description
Thst Conditions
InputCapacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
Vcc= 4.5V
Max.
Units
5
pF
7
pF
AC Test Loads and Waveforms
R1500.o.
R15oo.o.
5VO----_....,
5V
OUTPUTO---+--~
FI
5PFI
333.0.
INCLUDING
JIGAND _
SCOPE -
-=
7C4704
GND
R2
333.0.
INCLUDING
JIGAND _
SCOPE -
7C47()-6
7C4J'O.5
(b)
(a)
Equivalent to:
3.0V ---~Jr=----~
OUTPUTo---~--i
R2
30 P
ALL INPUT PULSES
<>---------.:,
OUTPUT
o
u.
u::
....----oo 2V
oo--~."'
Switching Characteristics
Over tbe Operating Rangd7,8]
7C470-15
7C472-15
7C474-15
Parameters
Description
•
en
THEvENIN EQUIVALENT
Min.
Max.
30
7C470-20
7C472-20
7C474-20
Min.
Max.
7C470-25
7C472-25
7C474-25
Min.
Max.
7C470-40
7C472-40
7C474-40
Min.
Max.
Units
ns
IcY
Cycle Time
tA
Access Time
tRY
Recovery Time
15
15
10
10
ns
ns
35
15
35
20
50
25
40
ns
tpw
PulseWidtb
15
20
25
40
tLZR
Read LOW to Low Z
3
3
3
3
ns
tDVR[9]
Read HIGH to Data Valid
3
3
3
3
ns
tHZR[9]
Read HIGH to High Z
tHWZ
Write HIGH to Low Z
5
5
5
5
ns
tSD
DataSet-UpTime
11
12
15
20
ns
tHD
Data Hold Time
0
tEFD
E/FDelay
15
20
25
40
tEFL
MRtoE/FLOW
30
35
35
50
ns
tHFD
HFDeiay
30
35
35
50
ns
tAFED
PAFEDelay
50
ns
tRAE
Effectlve Read from Write HIGH
15
20
25
40
ns
tWAF
Effective Write from Read HIGH
15
20
25
40
ns
15
15
0
0
30
18
35
25
0
35
ns
ns
ns
Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7. Test conditions assume signal transmission time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IOrJIOH
and 30 pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
9. tHZR and tDVR use capacitance loading as in part (b) of AC Thst
Loads. tHZR transition is measured at +500 mV from VOL and - 500
mV from VOH. tnVR transition is measured at the 1.5V level. tHWZ
and tlZR transition is measured at ± 100 mV from the steady state.
5-119
.-=-?~PRESS
PRELIMINARY
CY7C470
CY7C472
CY7C474
SEMlCONDUClDR
Switching Waveforms
Asynchronous Read and Write
QO-Qs--------------~SA'___~~~~__~~~,'~___________ J
w
-E'~
r:= =1tSD
Do-Os
--------------I(!<.-
~
T
tHD
:::1
4,-----J
1, - - - - -
)1)1--------------«
DATA VALID
DATA VALID
)>--------
7C470-7
Master Reset (No Write to Programmable Flag Register)
tCY
tpw
I
R,W
tRV"
l'
tRY
~
I--
tHFD
-I-
HF
I
Ell'
I---tEFL~
I
'k'
I--
tAFED
7C47CHl
Master Reset (Write to Programmable Flag Register)[JO]
tRV-
~
W(R)
I--
tpw -
I+-
tSD
tCY
tRV-
IHD
VALID
7C470-9
Note:
10. Waveform labels in parentheses pertain to writing the programmahle
flag register from the output port (Qo - Q8).
5-120
~
_=CYPRESS
_ F
.
CY7C470
CY7C472
CY7C474
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
ElF Flag (Last Write to First Read Full Flag)
W
FULL-1
R
I:/F
HF
t~1
FULL
FULL-1
/
\
~~j-
LDW
7C470-1 0
•
II)
ElF Flag (Last Read to First Write Empty Flag)
0
IL
iL
R
EMPTY +1
w
I:/F
HF
t~1
EMPTY
EMPTY +1
/
\
~~j-
HIGH
7C470·11
Half Full Flag
W
R
HF
HALF-FULL
HALF-FULL + 1
HALF-FULL
/
-'ffi
1
\
Hffij7C47()'12
5-121
-~
.
:~PRESS
--=--_F
PRELIMINARY
CY7C470
CY7C472
CY7C474
SEMICONDUCTOR
Switching Waveforms (continued)
PAFE Flag (Almost Full)
W
/
t-1--_\'---~-~-"~i-
R
PAFE
HF
LOW
7C470-13
PAFE Flag (Almost Empty)
R
/
W
L"1
PAFE
HF
HIGH
7C470-14
Retransmit
ICY
ICY
I
~IA-I
~ IRV'" - - I p w - 4- IRV'"
I
I~R
ICY
00- 0 8
-----------------------(z:z><
DATA VALID
)
7C470-15
5-122
#~
PRELIMINARY
§i!II!Iii= CYPRESS
~_'J SEMICONDUClDR
CY7C470
CY7C472
CY7C474
Switching Wavefonns (continued)
Mark
lev
tev
\
.. tRV" I-- tpw--- ~ tRV'"
•
rn
7C470-16
o
u..
u::::
Empty Flag and Empty Boundary
DATA IN
W
---+----.
ElF ----1---------'---11
DMAOUT
----~------------L_~~~Nr~~~o_\_-------------
7C470-17
5-123
PRELIMINARY
CY7C470
CY7C472
CY7C474
Switching Waveforms (continued)
Full Flag and Full Boundary
- ....- - - - t P W -
DATAIN------~------------------------~------------~~-----------------DATA OUT - - - - [
70470-18
Architecture
Retransmit
TheCY7C470,CY7C472,andCY7C474FIFOsconsistofanarray
of8,192, 16,384, and 32,768 words of9 bits each, respectively. The
control consists of a read pointer, a write pointer, a retransmit
pointer, control signals (i.e., write, read, mark, retransmit, and
masterreset), and flags (i.e., Empty/Full, Half Full, and Programmable Almost FullJEmpty).
Resetting the FIFO
Upon power up, the FIFO must be reset with a master reset (MR)
cycle. This causes the !:,IFO to enter the empty condition signified
by the Empty flag (ElF) being LOW, and both the Pro~mable
Almost Ful1JEmpty flag (PAFE) and Half Full flag (HF) being
HIGH. The read pointer, write pointer~d retransmi!Eointer are
reset to zero. For a valid reset, read (R) and write (W) must be
HIGH tRl'Wf!wpw before the falling edge and tRMR after the rising edge of MR.
Writing Data to the FIFO
Data canJ!.e written to the FIFO when it is not FUu1111. A falling
edge of W initiates a write cycle. Data appearing at ~ inputs
(00- Ds) tSD before and tHD after the rising edge of W will be
stored sequentially in the FIFO.
Reading Data from the FIFO
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and resent if necessary. Retransmission can start from anywherein the FIFO and be repeated without limitation.
The retransmit methodology is as follows: mark the current value
of the read pointer, after an error in subsequent read operations return to that location and resume reading. This effectively resends
all of the data from the mark point. When MARK is WW, the current value of the read pointer is stored. This..2.I?eration marks the
beginning ofthe packet to be resent. When RT is Ww, the read
pointeris updated with the mark location. During each subsequent
read cycle, data is read and the read pointer incremented.
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the mark
pointer, because further write operations will overwrite data.
Programmable Almost FullJEmpty Flag
Data c8l!.!>e read from the FIFO when it is not empty[121. A falling
edge of R initiates a read cycle. Data outputs (Qo-Qs) are in a
high-impedance ~ndition when the FIFO is em£ty and between
read operations (R HIGH). The falling edge of R during the last
readcy~~efore the empty condition triggers a high-to-Iowtransition of ElF, prohibiting any further read operations until tRFF after
a valid write.
Notes:
11. When the FIFO is less thanha1Lfull, the flags make a LOW-to-JilGH
traosition on the rising edge Qj'W aod make the JilGH-to-LOW traosition 00 the falling edge of R. If the FIFO is more than half full, the
flags make the LOW-to-HIGH traosition on the ~ing edge ofR aod
IDGH-to-LOW transition on the falling edge ofW.
The CY7C470/2/4 offer a variable offsetfor the Almost Empty and
the Almost Full condition. The offset is loaded into the pro~
mabIe flag register (PFR) during a master reset cycle. While MR is
Ww, the PFR can be lo~ed from Qs-Qo by pulsing RWW or
from Ds-Do by pulsing W Ww. The offset options are listed in
Table 2. See Table 1 for a description of the six FIFO states. If the
PFR is not loaded during master reset ('R: and W HIGH) the default offset will be 256 words from Full and Empty.
12. Full and emQ!y--.!'tates cao he decoded from the Half-Full (HF) aod
Empty/Full (ElF) flags.
5-124
PRELIMINARY
CY7C470
CY7C472
CY7C474
Table 1. Flag Truth Table[13]
CY77C470
HF
ElF
PAFE
1
0
0
State
CY77C472
CY77C474
(8Kx9)
(16Kx9)
(32Kx9)
Number of Words in
FIFO
Number of Words in
FIFO
Number of Words in
FIFO
0
0
0
Empty
1
~p
I~P
l~P
P + 1 ~8192
P + 1 ~ 16384
1
1
0
Almost Empty
1
1
1
Less than Half Full
0
1
1
Greater than Half Full
4097 ~ 8190 - P
8193 ~ 16382 - P
16385 ~ 32766 - P
0
1
0
Almost Full
8191 - P ~ 8191
16383 - P ~ 16383
32767 - P ~ 32767
0
0
0
Full
8192
16384
32768
P+l~4096
en
D3
D2
Dl
DO
0
0
0
0
0
0
0
1
16 or less locations from Empty/Full
16
0
0
1
0
32 or less locations from Empty/Full
32
0
0
1
1
64 or less locations from Empty/Full
64
0
1
0
0
128 or less locations from Empty/Full
128
0
1
0
1
256 or less locations from Empty/Full (default)
256
0
1
1
0
512 or less locations from Empty/Full
512
P
PAFE Active when:
256 or less locations from Empty/Full (default)
256
0
1
1
1
1024 or less locations from Empty/Full
1024
1
0
0
0
2048 or less locations from Empty/Full
2048
1
0
0
1
4098 or less locations from Empty/Fu11[15]
4098
1
0
1
0
8192 or less locations from Empty/Full[16]
8192
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
5-125
•
oLL
Table 2. Programmable Almost Full/Empty Empty Options[14]
u::
~~CONDUClDR
CY7C470
CY7C472
CY7C474
PRELIMINARY
. ,
Ordering Information
Speed
(ns)
15
20
25
40
Package
'JYpe
Operating
Range
CY77C472-15DC
D16
Commercial
CY77C472-15JC
J65
L55
CY77C472-15LC
L55
P15
CY77C472-15PC
PIS
CY77C472-15DI
D16
CY77C472-15JI
J65
Package
'JYpe
Operating
Range
Speed
(ns)
CY77C470-15DC
D16
Commercial
15
CY77C470-15JC
J65
CY77C470-15LC
CY77C470-~5PC
CY77C470-l5PI
D16
CY77C4?0-15JI
J65
Ordering Oode
CY77C470-15PI
P15
CY77C470-20DMB
D16
CY77C470-20LMB
L55
Industrial
Military
20
Ordering Code
CY77C472-15PI
PIS
CY77e472-20DMB
D16
CY77C472-20LMB
L55
CY77C470-25DC
D16
CY77C472-25DC
D16
CYnC470-25JC
J65
CY77C472-25JC
J65
CY77C470-25LC
L55
CY77C472-25LC
L55
CY77C470-25PC
PIS
CY77C472-25PC
PIS
CY77C470-25PI
D16
CY77C472-25DI
D16
CY77C470-25JI
J65
CY77C472-25JI
J65
Commercial
25
Industrial
CY77C472-25PI
PIS
CY77C472-25DMB
D16
CY77C472-25LMB
1.55
CY77C472-40DC
D16
CY77C472-4OJC
J65
L55
CY77C472-40LC
L55
PIS
CY77C472-40PC
P15
CY77C472-40DI
D16
CY77C472-40JI
J65
CY77C470-25PI
PIS
CY77C470-25DMB
D16
~Y77C470-25LMB
L55
GY77C470-40DC
D16
CY77C470-40JC
J65
CY77C470-40LC
CY77C470-40PC
CY77C470-40DI
D16
CY77C470-40JI
J65
CY77C470-40PI
PIS
CY77C470-40DMB
D16
CY77C470-40LMB
L55
Military
Commercial
Industrial
Military
5-126
40
CY77C472-40PI
P1S
CY77C472-40DMB
D16
CY77C472-40LMB
L5S
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
•
~~
;6i CYPRESS
PRELIMINARY
CY7C470
CY7C472
CY7C474
JI? SEMlCONDUcroR
Ordering Infonnation (continued)
Speed
(ns)
15
20
25
40
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Code
1YPe
Operating
Range
CY77C474-15DC
D16
Commercial
CY77C474-15JC
J65
Package
DC Characteristics
Parameters
Subgroups
1,2,3
CY77C474-15LC
155
VOH
CY77C474-15PC
P15
VOL
1,2,3
CY77C474-15D1
D16
Vrn
1,2,3
CY77C474-15JI
J65
VILMax.
1,2,3
CY77C474-15PI
P15
IIX
1,2,3
CY77C474-20DMB
D16
los
1,2,3
CY77C474-20LMB
155
ICC
1,2,3
CY77C474-25DC
D16
CY77C474-25JC
J65
CY77C474-25LC
155
CY77C474-25PC
P15
CY77C474-25D1
D16
CY77C474-25JI
J65
CY77C474-25PI
P15
CY77C474-25DMB
D16
CY77C474-25LMB
155
CY77C474-40DC
D16
Industrial
Military
Commercial
Switching Characteristics
Industrial
Military
Commercial
Parameters
Subgroups
IcY
9,10,11
tA
9,10,11
tRY
9,10,11
tpw
9,10,11
tUR
9,10,11
toVR
9,10,11
tHzR
9,10,11
tHWZ
9, 1Q, 11
CY77C474-40JC
J65
CY77C474-40LC
155
CY77C474-40PC
P15
CY77C474-40DI
D16
tso
9,1(},11
CY77C474-40JI
J65
tHO
9,10,11
CY77C474-40PI
P15
tEFD
9,10,11
CY77C474-40DMB
D16
tHFD
9,10,11
CY77C474-40LMB
155
tAFED
9,10,11
tRAE
9,10,11
tWAF
9,10,11
Industrial
Military
Document#: 38-00142-B
5-127
•
INFO
SRAMs
PROMs
PlDs
FIFOs
lOGIC
RISC
MODULES
"
"
,I
':1
ECl
I ..,
BUS
I"
MiliTARY
ItA
TOOLS
1M
QUALITY
I"
PACKAGES
I~i
=~PRfSS
Section Contents
~, ~CONDUClDR
LOGIC
Page Number
Device Number
Description
CY2901C
CY2909A
CY2911A
CY2910A
CY7C510
CY7C516
CY7C517
CY7C901
CY7C909
CY7C911
CY7C910
CY7C9101
CY7C9115
CY7C9116
CY7C9117
CMOS 4-Bit Slice ............................................................. .
CMOS Microprogram Sequencers ............................................... .
CMOS Microprogram Sequencers ............................................... .
CMOS Microprogram Controller ............................................... .
16 x 16 Multiplier Accumulator ................................................. .
16 x 16 Multipliers ........................................................... .
16 x 16 Multipliers ........................................................... .
CMOS 4-Bit Slice ............................................................ .
CMOS Microprogram Sequencers .............................................. .
CMOS Microprogram Sequencers .............................................. .
CMOS Microprogram Controller ............................................... .
CMOS 16-Bit Slice ........................................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
CMOS 16-Bit Microprogrammed ALU .......................................... .
6-1
6-8
6-8
6-12
6-17
6-27
6-27
6-38
6-52
6-52
6-62
6-73
6-90
6-90
6-90
•
0
a0
...J
CY2901C
CYPRESS
SEMICONDUCTOR
Features
CMOS Four-Bit Slice
• Capable of withstanding greater than
2001V static discharge voltage
• Pin compatible and functional equivalent to Am2901C
Functional Description
• Lowpower
• Vee margin
-5V:!:lO%
- All parameters guaranteed over
commercial and military operating
temperature range
• Performs eigbt operations on two
4-bit operands
• Infinitely expandable in 4-bit increments
• Four status flags: carry, overflow, negative, zero
The CY2901 is a high-speed, expandable,
4-bit wide ALU that can be used to implement the arithmetic section of a CPU, peripheral controller, orprograrnmable controller. The instruction set of the CY2901
is basic but yet so versatile that it can emulate the ALU of almost any digitalcomputer.
The CY2901, as illustrated in the block
diagram, consists of a 16-word by 4-bit duai-port RAM register file, a 4-bitALU and
the required data manipulation and controllogic.
Theoperation performed is determined by
nine input control lines (10 to Is) that are
usually inputs from an instruction register.
The CY2901 is expandable in 4-bit increments, has three-state data outputs as well
as flag outputs, and can use either a full
carry look-ahead or a ripple carry.
TbeCY2901 is a pin-compatible, functionallyequivalent,improved-performancereplacement for the AM2901.
The CY2901 is fabricated using an advanced 1.2-micron CMOS process that
eliminateslatch-up, provides ESD protection over 2001V; and achieves superior
performanceat low power dissipation.
- Pin Configuration
Logic Block Diagram
•
u
(3
o
...J
'ThpView
As
OE
A,
A,
Y.
Y,
Y,
Yo
A"
16
16
17
'B'
(READ/WRITE)
ADDRESS
RAM.
RAMo
Vee
F~O
10
I,
I.
CP
l'
OVR
Cn +4
G
F.
GND
Co
1.0
Is
I.
ao
Do
Bo
B,
D,
S.
S.
D2
Do
00
2901C·2
DATA OUT
2901C·1
Selection Guide See last page for ordering information
Read Modify-Write Cycle (Min.) in ns
Operating Icc (Max.) in mA
Operating Range
Part Number
31
140
Commercial
CY2901C
32
180
Military
CY2901C
6-1
~~
.;~CWUCTOR
CY2901C
Maximum Ratings
(Abowwhich the useful life may be impaired.)
Static Discharge Voltage ........................
(Per MIL-STD-883 Method 3015)
Storage Temperature .................
- 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied .......................
- 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 10 to Pin 30) .•.....................
- O.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................
- O.5Vto +7.0V
DC Input Voltage ......................
- O.5V to +7 .OV
Output Current into Outputs (LOW) ............... 30 rnA
Latch-Up Current (Outputs) ...................
>2001V
>200rnA
Operating Range
Range
Ambient
Thmperature
Vee
Commercial
O°Cto +70°C
5V±1O%
- 55°Cto +l25°C
5V±10%
Militaryll]
Notes:
1. TA is the "instant on" case temperature.
Pin Definitions
Signal
Name
I/O
Signal
Name
Description
These four address lines select one of the registers in the stack and output its contents on the
(internal) A port.
Q3
RAM3
(cont.)
I/O
Description
1/0
Outputs: When the destination code on lines 16,
7, 8 indicates a shift left (UP) operation the
three-state ontputs are enabled and the MSB of
the Q register is output on the Q3 pin and the
MSB of the ALU output (F3) is output on the
RAM3pin.
These four address lines select one of the registers in the sack and output its contents on the
(internal) B port. This can also be the destination address when data is written back into the
register file.
Inputs: When the destination code indicates a
shift right (DOWN) the pins are the data inputs
to the MSB of the Q register and the MSB of
the RAM.
These nine instruction lines select the ALU data
sources (lo, 1, 2), the operation to be performed
(13,4,5), and what data is to be written into either the Q register or the register file (16, 7, 8)'
10 - 18
Qo
These are four data input lines that may be selected by the 10, 1, zlines as inputs to the ALU.
o
These are three-state data output lines that,
when enabled, output either the ontput of the
AI1J or the data in the A latches, as determined
by the code on the 16, 7, 8lines.
Outpnt Enable. This is an active LOW input
that controls the Yo - y 3 outpnts. When this
signal is WW the Y outputs are enabled and
when it is HIGH they are in the high-impedance
state.
CP
I/O
RAMo
Oock Input. The WW level of the clock writes
data to the 16 x 4 RAM. The HIGH level of the
Clock writes data from the RAM to the A-purt
and B-port latches. The operation of the Q register is similar. Data is entered into the master
latch on the WW level of the clock and transferred from master to slave when the clock is
Cn
Cn+4
0
The carry-out from the internal ALU.
G,P
0
The carry generate and the carry propagate outputs of the ALU, which may be used to perform
a carry look-ahead operation over the 4 bits of
theALU.
OVR
0
Overflow. This signal is logically the exclusiveOR of the carry-in and the carry-out ofthe MSB
of the ALU. This pin indicates that the result of
the ALU operation has exceeded the capacity of
the machine. It is valid only for the sign bit and
assumes two's complement coding for negative
numbers.
F=O
0
Open collector output that goes HIGH if the
data on the ALU outputs (Fo, 1, 2, 3) are all
WW. It indicates that the result of an ALU operation is zero (positive logic).
F3
0
The most significant bit of the ALU output.
The carry-in to the internal ALU.
HIGH.
I/O
These two lines are bidirectional and are controlled by the 16, 7, 8 inputs. Electrically they are
three-state output drivers connected to the
'JTL.compatible CMOS inputs.
6-2
These two lines are bidirectional and function in
a manner similar to the Q3 and RAM3lines,
except that they are the LSB of the Q register
and RAM.
:~
CY2901C
~=CYPRESS
,
SEMICONDUCTOR
Electrical Characteristics
Parameters
VOH
VOL
Vm
VIL
Over the Operating Range (VeeMin. = 4.5V, VeeMax. = 5.5V)[2]
Description
Output HIGH Voltage
Output LOW Voltage
IlL
IOH
Max.
Units
0.4
V
V
Vee
0.8
V
V
Vee = Max., VIN = Vee
10
Vee = Max., VIN = GND
Vee = Min., VOH = 2.4V
-10
JlA.
JlA.
V ce
= Min., IOH =
2.4
-3.4 rnA
Vee = Min.,
IOL = 20 rnA Commercial, 16 rnA Military
~.O
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
1m
Min.
Thst Conditions
-3.0
IOL
Output HIGH Current
Output LOW Current
loz
Output Leakage Current
Vee = Max., VOUT = GND or Vee
Ise
Icc
Output Short Circuit Currentl3]
Supply Current
Vee = Max., VOUT = OV
Vec=Max.
I Commercial
1 Military
Vee = Min., VOL = O.4V
-3.4
rnA
20
rnA
rnA
16
-40
JlA.
rnA
LCommercial
+40
- 85
140
I
180
rnA
-30
Military
rnA
Capacitance[4]
Parameters
Thst Conditions
Max.
CIN
Description
InputCapacitance
TA = 25°C, f = 1 MHz,
5
Units
pF
COUT
Output Capacitance
Vee=5.0V
7'
pF
Notes:
2. See the last page of this specification for Group A subgroup testing infonnation.
3. Not more than one output should be shorted at a time. Duration ofthe
short circuit should not be more than one second.
4.
Thsted initially and after any design or process changes that may affect
these parameters.
Output Loads used for AC Performance Characteristics
2901C-3
2901C-4
Open drain (F = 0)
All outputs except open drain
Notes:
1. CL = 50 pF includes scope probe, wiring and stray capacitance.
2. CL = 5 pF for output disable tests.
3. Loads shown above are for commercial (20 rnA) IOL specifications
only.
Commercial
Military
RJ
2030
2520
R2
1480
1740
6-3
•
-:rr1l~NDUCfOR
CY2901C
CY2901C Guaranteed Commercial Range AC
Performance Characteristics
Cycle Time and Clock Characteristics
CY2901-
The tables below specifytbe guaranteed ACperformance oftbese
devices over tbe Commercial (0° C to 70° C) operating temperature range with Vee varying from 4.5V to 5.5V. All times are in
.)1anosecondsand are measured betweentbe 1.5V signal levels. The
'inputs switch between OV and 3V with signal transition rates of IV
per nanosecond. All outputs have maximum DC current loads. See
previous page for loading circuit information.
This data applies to parts witb the following numbers:
CY2901CPC, CY2901CDC, CY2901CLC
C
Read-Modify-Wite Cycle (from selection
of A, B registers to end of cycle)
31ns
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
32 MHz
Minimum Clock LOW Time
15ns
Minimum Clock HIGH Time
Minimum Clock Period
15ns
31 ns
For faster performance see CY7C901-23 speCification.
Combinatorial PropagatilJn Delays. CL = 50 pF[5]
y
ThOutput
F3
y
From Input
F3
Cn + 4
G,P
G,P
Cn +4
F-O
F-O
OVR
Qo
Q3
-
RAMo
RAM3
OVR
A,BAddress
40
40
40
37
40
40
40
D
30
30
30
30
38
30
30
Co
22
22
20
-
25
22
25
1012
35
35
35
37
37
35
35
1345
35
35
35
35
38
35
35
-
1678
25
-
-
-
26
26
35
-
-
-
-
ABypassALU (I = 2XX)
-
-
-
-
Clock (LOW to illOH)
35
35
35
35
35
35
35
28
Set-Up and Hold Times Relative to Clock (CP) Input[5,6]
CP:
Input
~
-,- Set-UpTime
~
Set-UpTime
BeforeH. L
Hold Time
AfterH.L
BeforeL.H
15
1
(Note 7)
30,15 +tPWL
(Note 8)
A, B Source Address
B Destination Address
15
D
1012
-
1345
-
~78
10
RAMo, 3, Qo, 3
-
Co
•-
•
Do Not Change
25
-
1
1
0
20
0
30
0
30
Do Not Change
-
•
Hold Time
AfterL.H
12
•
0
0
0
Output EnablelDisable Times
Notes:
5. A dash indicates a propagation delay path or set-up time constraint
does not exist.
6. Certain signals must be stable during the entire clock: LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change."
7. Source addresses must be stable prior to the clock
L transition to
allow time to access the source data before the latches close. TheAaddress may then be changed. The B address could be changed if it is not
H.
a destination; i.e. if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time.
8. The set-up time prior to the clock
H transition is to allow time for
data to be accessed, passed through the ALU, and retnrned to the
RAM. It includes aU the time form stable A and B addresses to the
clock L • H transition, regardless of when the clock H • L transition
occurs.
6-4
L.
~
--:~PRESS
CY2901C
. ' SEMICONDUCfOR
Cycle Time and Clock Characteristicsl2]
CY2901C Guaranteed Military Range AC
Performance Characteristics
CY2901-
The tables below specify the guaranteed ACperformance of these
devicesover the Military ( - 55°Cto + 125°C)operatingtemperature range with V cc varying from 4.5V to 5.5V. All times are in
nanosecondsand are measured between the 1.5V signal levels. The
inputs switch between OV and 3V with signal transition rates of 1V
per nanosecond. All outputs have maximum DC current loads. See
"Electrical Characteristics" of this data sheet for loading circuit information.
This data applies to parts with the following numbers:
CY2901 CDMB
48
48
32ns
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
31 MHz
Minimum Oock LOW Time
Minimum Clock HIGH Time
Minimum OockPeriod
For faster performance see CY7C901 - 27 specIfication.
Combinatorial Propagation Delays. CL = 50 pFI2, 5]
1bOutput
Y
F3
Cn +4
From Input
Y
F3
Cn +4
A,BAddress
C
Read-Modify-Wite Cycle (from selection
of A, B registers to end of cycle)
F=O
F=O
OVR
RAM3
G,P
OVR
RAMo
44
48
48
48
37
G,P
48
15ns
15ns
32ns
Q3
Qo
-
D
37
37
37
34
40
37
en
25
25
21
-
28
25
28
-
1012
40
40
40
44
44
40
35
-
1345
40
40
40
40
40
40
40
-
-
29
29
-
-
40
33
1678
29
-
-
A BypassALU (I = 2XX)
40
-
-
-
-
-
Clock (WW to HIGH)
40
40
40
40
40
40
Set-Up and Hold Times Relative to Clock (CP) InputI5,6]
CP:
~
Set-UpTime
BeforeHt L
Hold Time
At'terHtL
A, B Source Address
15
2
(Note 7)
B Destination Address
15
D
en
-
1012
Input
•-
.- -
~
Set-UpTime
BeforeLtH
Hold Time
At'terLtH
30,15 + tPWL
(Note 8)
2
Do Not Change
t
25
2
0
-
20
0
-
-
30
0
1345
-
-
30
0
1678
10
RAMo, 3, Qo, 3
-
•
Output EnablelDisable Times
6-5
Do Not Change
-
t
12
0
0
•
o
c:;
g
CY2901C
Ordering Information
Read
ModifyWrite Cycle
(ns)
31
Package
Ordering Code
CY2901CDC
CY2901CPC
CY2901CDMB
32
Operating
Range
1Ype
D18
P17
D18
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Combinational Propagation Delays (Contioued)
Parameters
Subgroups
VOH
VOL
Vm
VILMax.
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1m
IlL
IoH
IoL
Ioz
Isc
Icc
Parameters
Fromc.,toY
FromCntoF3
From Cn to Cn + 4
FromCntoF=O
From c., to OVR
From c., to RAMo, 3
From 1012 to Y
From 1012 to F3
From 1012 to c., + 4
From 1012 to G, P
From 1012 to F = 0
From 1012 to OVR
From 1012 to RAMo, 3
From 1345 to Y
From 1345 to F3
From 1345 to Cn + 4
From 1345 to G, P
From 1345 to F = 0
FromI345toOVR
From 1345 to RAMo, 3
From 1678 to Y
Cycle Time and Clock Characteristics
Parameters
MinimumOock LOW Time
Mioimum Oock HIGH Time
Subgroups
7,8,9, 10, 11
7,8,9, 10, 11
Combinational Propagation Delays
Parameters
FromA, B Address to Y
From A, B Address to F3
From A, B Address to c., + 4
From A, B Address to G, P
From A, B Address to F = 0
From A, B Address to OVR
From A, B Address to RAMo, 3
FromDtoY
FromDtoF3
FromDtoc., + 4
FromDtoG,P
FromDtoF-O
FromDtoOVR
From D to RAMo 3
Subgroups
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
From 1678 to RAMo, 3
From 1678 to Qo, 3
From A Bypass ALU to Y (I = 2XX)
From Oock LOW to HIGH to Y
From OockLOW to HIGH to F3
From Oock LOW to HIGH to c., + 4
From Clock LOW to HIGH to G, P
From Clock LOW to HIGH to F = 0
From Clock LOW to HIGH to OVR
From Oock LOW to HIGH to RAMo, 3
From Clock LOW to HIGH to Qo 3
6-6
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8,9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
·)L~~
CY2901C
Set-Up and Hold Times Relative to Clock (CP) Input
Parameters
Subgroups
A, B Source Address
Set-UpTime BeforeH. L
A, B Source Address
Hold Time After H • L
A, B Source Address
Set-UpTime Before L. H
A, B Source Address
Hold Time After L. H
B Destination Address
Set-UpTime Before H. L
B Destination Address
Hold Time After H. L
B Destination Address
Set-UpTimeBeforeL.H
B Destination Address
Hold Time After L. H
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
D Set-Up Time BeforeL. H
7,8,9,10, 11
D Hold Time After L. H
7,8,9,10,11
c.. Set-Up Time Before L. H
c.. Hold Time After L. H
7,8,9,10,11
7,8,9,10,11
1345 Set-Up Time Before L. H
(3
o
..J
7,8,9,10,11
7, 8, 9, 10, 11
1345 Hold Time After L. H
7, 8, 9, 10, 11
1678 Set-Up Time Before H. L
7,8,9,10, 11
L.
o
7, 8, 9, 10, 11
1012 Set-Up Time Before L. H
1012 Hold Time After L. H
7, 8, 9, 10, 11
1678 Hold Time After H. L
1678 Set-Up Time Before
•
7,8,9, 10, 11
H
7,8,9,10, 11
1678 Hold Time After L. H
7,8,9,10,11
RAMo, RAM3, Qo, Q3
7,8,9, 10, 11
Set-Up Time Before L. H
RAMo, RAM3, Qo, Q3
7, 8, 9, 10, 11
Hold Time After L. H
Document#: 38-00008-B
6-7
CY2909A
CY291lA
CYPRESS
SEMICONDUCTOR
Features
• Fast
-CY2909A11IAhas a 40-ns (min.)
clock-to-output cycle time (commercial)
- CY2909!11 has a 40-n8 (min.)
clock-to-output cycle time (military)
• Lowpower
- Icc (max.) = 70 mA (commercial)
- Icc (max.) 90 mA (military)
=
• Vccmargin
-sv :1:10%
- AIl parameters guaranteed over
commercial and military operating
temperature range
CMOS Micro Program
Sequencers
• Infinitely expandable in 4-bit increments
• Capable of withstanding >2001V static discharge voltage
• Pin compatible and functional equivalent to AMD AM2909A1AM2911A
Functional Description
The CY2909A and CY2911A are highspeed, four-bit-wide address sequencers
intended to control the sequence of executionofmicro-instructionscontained in microprogram memory. They may be connected in parallel to expand the address
width in 4-bit increments. Both devices are
implemented in high-performance CMOS
for optimum speed and power.
The CY2909A can select an address from
any of four sources. They are: (1) a set of
Logic Block Diagram
Pin Configurations
R (2909A ONLy)
PUSH/POP
FILE
ENABLE
FE
lIE
Vee
CP
110
CP
PUP
Vee
R_
R,
REGISlER
ENABLE
lIE
DANDR
CONNECTED
ON 2911A
ONLV
four external direct inputs (Di); (2) external data stored in an internal register (R;);
(3) a four-word-deep push/pop stack; or
(4) a program counter register (which usually contains the last address plus one).
The push/pop stack includes control lines
so that it can efficiently execute nested
subroutine linkages. Each of the four outputs (Yi) can be ORed with an external input for conditional skip or branch instructions. A ZERO input line forces the outputs to all zeros. The outputs are tri-state,
controlled by the output enable (OE) input.
The CY2911A is an identical circuit to the
CY2909A, except the four OR inputs are
removed and the D and R inputs are tied
together. The CY2911A is available in a
20-pin, 300-mil package. The CY2909A is
available in a 28-pin, 600-mil package.
FE
On
On
OE
Ro
OR3
03
DR_
.(4
DIRECT
INPl/TS
0 > - _ - , *...
+,
PUP
FE
lIE
Cn + 4
03
Co
D.
OE
0,
V3
0.
v_
Do
v.
OR,
0,
ORo
V,
Vo
GND
V,
ZERO
Vo
Do
So
So
8,
CLOCK
V.
8,
ZERO
GND
2909A-3
2909A-2
8,
~ -I ~~ ->---..,'r---+--h
-+...
:
,
:
OR1 ) -_ _ _
ORo > - - ' " - - ,
_~_A~~L~ ~
o Q.
c£&'£I!!?&~
...-, ......, ......,
4
ZERO
flo
0110
03
OR_
0_
OR
0,
4 3 2!J 282726
25
24
23
2909A
22
a
21
9
20
10
5
6
7
11'2'3'415'6'71'3
FE
On+.
Co
OE
V3
v.
V,
CO +4
2909A-1
6-8
0,
Do
GND
4
32 111 2019
1a
17
16
15
14
910111213
2911A
~~Ui.p>
2909A-4
Co
03
0.
2909A-5
CY2909A
CY2911A
~
. -;:::z
_'iECYPRESS
F SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ....................... -55°Cto+I25°C
Supply Voltage to GroundPotentiai ........ - O.sVto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Static Discharge Voltage ............ , . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Militaryll]
O°Cto
+ 70°C
- 55°Cto +125°C
Vee
5V±10%
5V±10%
Output Current, into Outputs (LOW) .......... . . . .. 30 rnA
Electrical Characteristics
Parameters
Over the Operating Range£2]
Description
Thst Conditions
Output HIGH Voltage
VOR
V cc = Min., lOR = - 2.0 rnA
V cc = Min., lOR = - 1.0 rnA
Min.
ICommercial
IMilitary
Max.
Units
V
2.4
2.4
V
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
2.0
VjL
Input LOW Voltage
- 2.0
Vee
0.8
IIX
Input Load Current
GNDSVjsVee
-10
+10
loz
Output LeakageCurrent
GND s Va s Vee, Output Disabled
-20
+20
tAA
tAA
los
Output Short Circuit Current[3]
Vee = Max., VOUT = GND
-30
- 85
rnA
lee
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA
ICommercial
70
rnA
I Military
90
Vee = Min., IOL = 16.0 rnA
0.4
V
V
V
Capacitance [4]
Parameters
Description
Input Capacitance
Output Capacitance
qN
CoUT
Thst Conditions
TA = 25°C,f= 1 MHz,
Vee = S.OV
Notes:
1. TA is the "iostant on" case temperature.
2. See the last page of this specification for Group A subgroup testing ioformation.
AC Test Loads and Waveforms
OUTP~~31
50pF
4.
Units
pF
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
5V31
I _
R1
R1
I
INCLUDING _
JIG AND -
3.
Max.
S
7
OUTPUT
5pF
R2
_
-
R2
INCLUDING
JIG AND -
SCOPE
-
SCOPE
(a)
(b)
Commercial
2909A-6
Military
Rl
254Q
258Q
R2
187Q
216Q
6-9
2909A-7
o
(3
9
CY2909A
CY2911A
4.;?~PRE§
~, SEMlCCtIDUCTOR
Switching Characteristics Over the Operating Rangel2]
Commercial
Military
Units
Minimum Clock LOW Time
20
20
ns
Minimum Clock HIGH Time
20
20
ns
MAXIMUMCOMBINATORIALPROPAGATIONDELAYS
From Input To:
Y
Cn+ 4
Y
Cn + 4
Dj
17
22
20
25
ns
SO,S1
29
34
29
34
ns
ORi(CY2909A)
17
22
20
25
ns
Cn
-
14
-
16
ns
ZERO
29
34
30
35
ns
OE LOW to Output
25
-
25
-
ns
OE HIGH to High Z[S]
25
-
25
-
ns
=LH
Clock HIGH, So, S1 = LL
Clock HIGH, So, S1 = HL
39
44
45
50
ns
39
44
45
50
ns
44
49
53
58
ns
Clock HIGH, SO, S1
ns
MINIMuM SET-UP AND HOLD TIMES (All Times Relative to ClockLOW-to-HIGH ltansition)
Hold
Inplit
Set-Up
Hold
Set-Up
From
RE
19
4
19
5
ns
R[6]
I·
10
4
12
5
ns
Push/Pop
25
4
27
5
ns
FE
25
4
27
5
ns
Cn
18
4
18
5
ns
Dj
25
0
25
0
ns
ORj(CY2909A)
25
0
25
0
ns
SO,S1
25
0
29
0
ns
ZERO
25
0
29
0
ns
Note.:
5. Output Loading as in part (b) of AC Thst Loads and Waveforms.
6.
RjandDjareintemaIlyconnectedontbeCY2911A. Use Rj set-up and
hold times for Dj inputs.
Switching Waveforms
MIN CLOCK LOW
CLOCK
HOLD
TIMES
---+,
INPUT
(EXCEPT OE) - - - t - '
I
OUTPUT~
~~:P+UJ ===:XXXXXXXXXXX_ ,-,-_-_-_-_-_-_-_-_-_-_-_-_
.-
INPUT TO
CLOCK TO OUTPUT
2909A-8
6-10
CY2909A
CY2911A
=n"
:~
_"iECYPRESS
~F
SEMICONDUCIOR
Ordering Information
Package
1Ype
D16
Ordering Code
CY2909ADC
CY2909ALC
CY2909APC
CY2909ADMB
L64
P15
D16
CY2909ALMB
L64
Operating
Range
Ordering Code
Commercial
CY291lADC
CY2911ALC
CY291lAPC
Military
CY2911ADMB
CY2911ALMB
Package
'JYpe
D6
L61
P5
D6
Operating
Range
Commercial
Military
L61
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIH
1,2,3
1,2,3
•
1,2,3
1,2,3
VILMax"
Ioz
1,2,3
1,2,3
loS
1,2,3
Icc
1,2,3
Irx
o
C3
o
...I
Switching Characteristics
Parameters
Subgroups
Parameters
Minimum Clock LOW Time
7,8,9, 10, 11
7,8,9,10, 11
Minimum Clock HIGH Time
MAXIMUM COMBINATORIAL PROPAGATION DELAYS
Di toY
7,8,9,10, 11
Di toCn+4
So, S1 to Y
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
So, S1 to Cn + 4
ORi (2909A) to Y
ORi (2909A) to Cn + 4
4 t0 4+4
ZEROtoCn +4
Clock HIGH, So, Sl = LH to Y
Clock HIGH, So, Sl = LH to Cn+4
Clock HIGH, So, Sl = LL to Y
MINIMUM SET-UP AND HOLD TIMES
RESet-UpTime
REHoidTime
Push/Pop Set-Up Time
Subgroups
7,8,9,10, 11
7,8, 9, 10, 11
7, 8, 9, 10, 11
FE Hold Time
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10,11
4 Set~Up Time
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
cnHoldTime
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Push/Pop Hold Time
FE Set-Up Time
Di Set-Up Time
DiHoldTime
OR< (2909A) Set-Up Time
7,8,9, 10, 11
7, 8, 9, 10, 11
ORi (2909A) Hold Time
Clo~kHIGH,So,Sl = LLtoCn +4
Clock HIGH, So, Sl = HL to Y
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
So, S1 Set-Up Time
So, Sl Hold Time
ZERO Set-Up Time
ClockHIGH,So,Sl = HLt04+4
7, 8, 9, 10, 11
ZERO Hold Time
Document#: 38-00009-B
6-11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10, 11
7,8,9,10, 11
CY2910A
CYPRESS
SEMICONDUCTOR
Features
• Fast
- CY2910AC has a 50-ns (min.) clock
cycle; commercial
-CY2910AMhasa51-ns (min.)
clock cycle; military
• Lowpower
-IcC (max.) 170 mA
• Vee margin of 5V ±10% commercial
and military
• Sixteen powerfnl micro-instructions
• Three output enable controls for
three-way branch
• 1\velve-bit address word
• Four sources for addresses: microprogram counter (MPC), branch address
bus,9-word stack internal holding
register
=
CMOS Microprogram
Controller
• Internal 9-word by 12-bit stack can be
used for subroutine return address or
data storage
• 12-bit internal loop counter
• Capable of withstanding greater than
2001V static discharge voltage
• Pin compatible and functional equivalent to the Am2910A and Am29C10A
Functional Description
The CY2910A is a standalone microprogram controller that selects, stores, retrieves, manipulates, and tests addresses
that control the sequence of execution of
instructions stored in an external memory.
All addresses are 12-bit binary values that
designate an absolute memory location.
The CY291OA, as illustrated in the block
diagram, consists of a 9-word by 12-bit
LIFO (Last-ln-First-Out) stack and SP
(Stack Pointer), a 12-bit RC (Register/
Counter), a 12-bit MPC (MicroProgram
CP
Logic Block Diagram
Counter) and incrementer, a 12-bit-wide
by 4-input multiplexer, and the required
data manipulation and control logic.
Theoperation performed is determined ~Y
four input instruction lines (10 to 13) that 10
turn select the (internal) source of the next
micro-instruction to be fetched. This address is output on the Yo =..2J.lpins. Tho
additionalinputs (CC and CCEN) are provided that are examined during certain instructions and enable the user to make the
execution of the instruction either unconditional or dependent upon an external
test.
The CY2910A is a pin-compatible, functional-equivalent,improved-performance
replacementfor the Am2910A.
The CY2910A is fabricated using an advanced 1.2-micron CMOS process that
eliminateslatch-up, results in ESDprotection over 2001 V; and achieves superior
performanceand low-power dissipation.
Pin Configuration
DIP
ThpView
03
Y3
02
Y2
0,
Y,
Do
Yo
CI
CP
GND
DE
Yl1
011
Y,o
010
Y.
D.
CLEAR/COUNT
YB
DB
2901A-2
DATA PATH
CONTROL LINES
Y,
2901A-l
SeIecf IOn Gw'de
Minimum Clock Cycle (ns)
50
51
Stack Depth (words)
9
9
6-12
Operating Range
Commercial
Military
Part Number
CY2910AC
CY2910AM
~~
.iii CYPRESS
F
CY2910A
SEMlCONDUCfOR
Maximum Ratings
(Above which the useful life maybe impaired. Foruserguidelines,
nottested.)
Storage Temperature ................. Ambient Temperaturewith
PowerApplied ....................... Supply Voltage to Ground Potential
(Pin 10 to Pin 30) . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Outputs
inHighZState ........................
DC Input Voltage ......................
65°Cto +150°C
55°Cto +125°C
Output Current into Outputs (WW) ............... 30 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . >2001 V
(Per MIL-SID-883 Method 3015)
Latch-UpCurrent(Outputs) ................... >200rnA
Operating Range
- 0.5V to + 7.0V
Range
Commercial
Militaryll]
- 0.5Vto +7.0V
- 3.0Vto +7.0V
Ambient
lemperature
O°Cto +70°C
Vee
5V±1O%
- 55°C to +125°C
5V±1O%
Electrical Characteristics Over Commercial and Military Operating Rangel2, 3]
Parameters
Description
VOH
VOL
Vrn
Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
VlL
Irn
Input LOW Voltage
IlL
IOH
IOL
loz
Ise
Icc
lest Conditions
Vee = Min.,loH = - 1.6rnA
Vee = Min., IOL = 8 rnA
Min.
Max.
Units
0.5
V
V
2.4
2.0
- 3.0
Input HIGH Current
Input LOW Current
Output HIGH Current
Vee = Max., VIN = Vee
Vee = Max., VIN = GND
Vee = Min., VOH = 2.4V
-1.6
Output WW Current
Output LeakageCurrent
Vee = Min., VOL = O.5V
8
Vee = Max., VOUT = GNDorVee
Output Short Circuit Current[4]
SupplyCurrent
Vee
0.8
V
10
-10
!1A
!1A
V
rnA
rnA
-40
+40
!AA
Vee = Max., VOUT = OV
- 85
Vee = Max.
170
rnA
rnA
Capacitance [5]
CIN
Parameters
Description
InputCapacitance
CoUT
Output Capacitance
lest Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Output Load for AC Performance Characteristics[6. 7]
3.0V---------"
INPUTS
1:
+5V
°
fQ
8
Units
pF
10
pF
Switching Waveforms
All Outputs
v..
Max.
1.,------"",-
~---------'I'--------'
3.0V
CLOCK
~
OUTPUTS
290lA-3
2901A-4
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. V cc Min. = 4.5V, V cc Max. = 5.5V
4. Notmore than one output should be shorted at a time. Duration ofthe
short circuit should not be more than one second.
5.
6.
7.
6-13
'Illsted initially and after any desigo or process changes that may affect
these parameters.
CL = 50 pF includes scope probe, wiring, and stray capacitance.
CL = 5 pF for output disable tests.
•
o
a
g
~
~PRESS
~J,. SEMICONDUClDR
CY2910A
Clock Requirements [2, 8]
Guaranteed AC Performance Characteristics
The tables below specify the guaranteed AC performance of the
CY2910Aover the commercial (O°C to +70°C) and the military
(- 55° C to + 125° C) temperature ranges with Vcc varying from
4.5V to 5.5Y. All times are in nanoseconds and are measured between the I.5V signal levels.
Theinputsswitch betweenOV and3Vwithsignai transition rates of
IV pernanosecond. All outputs have maximum DC current loads.
Commercial
Military
Minimum ClockLOW
20
25
Minimum ClockHIGH
20
25
Minimum Clock Period 1 = 14
50
51
MinimumClockPeriod 1 = 8,9,15[9]
50
50
Combinatorial Propagation Delays (CL = 50 pF)[2, 8]
'ThOutput
Commercial
Military
From Input
Y
P4VECT,MAP
FULL
y
Do -Du
10 - 13
CC
CCEN
20
35
30
30
-
-
-
25
40
36
36
CPI= 8,9,15
(Note 9)
40
-
31
-
CP All Other 1
40
31
46
OE
(Note 10)
25
27
-
-
25
30
30
FULL
P4VECT,MAP
-
-
35
-
-
-
-
35
35
-
Minimum Set-Up and Hold Times Relative to clock LOW-to-HIGH transition (CL = 50 pF)[2]
Military
Commercial
Set-Up
Hold
Set-Up
Hold
DI.RC
16
0
16
0
DI.MPC
30
0
30
0
10 - 13
35
0
38
0
CC
24
0
35
0
CCEN·
24
0
35
0
CI
18
0
18
0
RLD
19
0
20
0
Notes:
8. A dash indicates that a propagation delay path or set-up time does not
exist.
9. These instructions are dependent upon the register/counter. Use the
shorter delay times if the previous instruction either does not change
the register/counter or could only decrement it. Use the longer delay
if the instruction prior to the clock was 4 or 12 or if RLD was Ww.
10. The enable/disable times are measured to a O.5V change on the ontput
voltage level with CL = 5 pH
6-14
_
k:~
CY2910A
- CYPRESS
. , SEMlCC'IIIDIJClDR
_
Table of Instructions
Result
REGI
13 - 10 Mnemonic
CNTR
Contents
Name
Fail
CCEN = LandCC = H
Pass
CCEN = HorCC =L
REGI
Y
STACK
Y
STACK
CNTR
Enable
0
JZ
Jump Zero
X
0
Clear
0
Clear
Hold
PL
1
CJS
CondJSBPL
X
PC
Hold
D
Push
Hold
PL
Jump Map
X
D
Hold
D
Hold
Hold
Map
CondJumpPL
X
PC
Hold
D
Hold
Hold
PL
PL
2
JMAP
3
CJP
4
PUSH
Push/Cond LD CNTR
X
PC
Push
PC
Push
(Note 11)
5
JSPR
Cond JSB R/PL
X
R
Push
D
Push
Hold
PL
6
CJV
Cond Jump Vector
X
PC
Hold
D
Hold
Hold
Vect
7
JRP
Cond Jump R/PL
X
R
Hold
D
Hold
Hold
PL
8
RFCT
~O
F
Hold
F
Hold
Dec
PL
Repeat Loop,
CNTR~O
RPCT
9
RepeatPL,
CNTR~O
10
=0
PC
Pop
PC
Pop
Hold
PL
~O
D
Hold
D
Hold
Dec
PL
=0
PC
Hold
PC
Hold
Hold
PL
F
Pop
Hold
PL
CRIN
CondRTN
X
PC
Hold
11
CJPP
Cond Jump PL & Pop
X
PC
Hold
D
Pop
Hold
PL
12
LDCT
LD Cntr & Continue
X
PC
Hold
PC
Hold
Load
PL
13
LOOP
Thst End Loop
X
F
Hold
PC
Pop
Hold
PL
14
CONT
Continue
X
PC
Hold
PC
Hold
Hold
PL
15
TWB
~O
F
Hold
PC
Pop
Dec
PL
=0
D
Pop
PC
Pop
Hold
PL
Three-\\ay Branch
H=IDGH
L=LOW
X = Don't Care
Note:
11. If CCEN = Land CC = H, then hold; else load.
Ordering Information
Clock Cycle
(ns)
50
51
Ordering Code
CY29IOA-DC
CY29IOA-JC
CY29IOA-LC
CY29IOA-PC
CY2910A-DMB
CY2910A-LMB
Package
1YJle
Dl8
J67
L67
P17
D18
L67
Operating
Range
Commercial
Military
6-15
•
o
C;
9
@:~
.
CYPRESS
~ SEMlCONDUClDR
•
CY2910A
MIUTARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Minimum Set-Up and Hold Times
Parameters
Subgroups
VOH
VOL
Vm
VILMax.
1m
IlL
IOH
IOL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
loz
Isc
Icc
Parameters
DI.RCSet-UpTime
DI. RC Hold Time
DI.MPCSet-UpTime
DI. MPC Hold Time
10 - 13 Set-Up Time
10 - 13 Hold Time
CCSet-UpTime
CCHoldTime
CCENSet-UpTime
CCENHold Time
CI Set-Up Time
CIHoldTime
RID Set-Up Time
RID Hold Time
Clock Requirements
Parameters
Minimum Clock LOW
Subgroups
7,8,9, 10, 11
Combinational Propagation Delays
Parameters
From Do - Dll to Y
From 10 - 13 to Y
From 10 - 13 to PL, VECf, MAP
FromCCtoY
From CCEN to Y
From CP (I = 8, 9, 15) to FULL
From CP (All Other I) to Y
From CP (All Other I) to FULL
Subgroups
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
Document #: 38-00010-B
6-16
Subgroups
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10, 11
CY7C510
CYPRESS
SEMICONDUCTOR
Features
• Fast
- CY7C510-45 has a 45-ns (max.)
clock cycle (commercial)
- CY7C510-55 has a 55-ns (max.)
clock cycle (military)
• Lowpower
- Icc (max. at 10 MHz) = 100 mA
(commercial)
- Icc (max. at 10 MHz) = 110 mA
(military)
• Vee margin 5V ±10%
• All parameters guaranteed over commercial and military operating temperature range
16 X 16 Multiplier
Accumulator
• 16 x 16 bit parallel multiplication with
accumulation to 35-bit result
• 1Wo's complement or unsigued maguitude operation
• Capable ofwitbstanding greater tban
1001V static discharge voltage
• Pin compatible and functional equivalent to Am29510 and TMC2110
Functional Description
The CY7C51O is a high-speed 16 x 16 parallel multiplier accumulator that operates
with a 45-ns clocked multiply accumulate
(MAC) time (22-MHz mUltiply accumulate rate). The operands may be specified
as either two's complement or unsigned
magnitude 16-bit numbers. The accumulator functions include loading the accumu-
lator with the current product, adding or
subtracting the accumulator contents and
the current product, or preloading the accumulatorfrom the external world.
All inputs (data and instruction) and outputs are registered. These independently
clocked registers are positive edge-triggered D-type flip-flops. The 35-bit accumulator/output register is divided into a
3-bit extended product (XTP), a 16-bit
most significant product (MSP), and a
16-bit least significant product (LSP). The
XTP and the MSPhavededicated ports for
three-state output; the LSP is multiplexer
with the Y-input. The 35-bit accumulator/
output register may be preloaded through
the bidirectional output ports.
a
Logic Block Diagram
9
16
16
CLKX
>----,....-----1:> x-
REGISTER
CLKY
16
16
16 x 16 ASYNCHRONOUS MULTPUER ARRAY
TC
RND
ACC
35
SUB
7C510·1
Selection Guide
MaximumMultiplyAccumulate Time (ns)
II
o
Commercial
Military
CY7C510-45
45
6-17
CY7C510-55
55
55
CY7C510-65
65
65
CY7CSI0-75
75
75
d:_~
CY7C510
~=CYPRESS
~, SEMICONDUCTOR
Functional Description (continued)
DIP
1bpView
The CY7C51O incorporates a 16-bitparaIlel multiplier followed by
a35-bit accumulator. All inputs (data and instruction) and outputs
are registered. The 7C51O is divided into four sections: the input
section, the 16 x 16 aSynchronous multiplier array, the accumulator, and the output/preload section.
The input section has two 16-bit operand input registers for the S
and Y operands, clocked by the rising edge of CLKX and CLK Y,
respectively. The four-bit instruction register (TC, RND, ACC,
SUB) is clocked by the rising edge of the logical OR of CLKX and
CLKY.
The 16 x 16 asynchronous multiplier array produces the 32-bit
product of the input operands. Either two's complement or unsigned magnitude operation is selected, based on instruction bit
TC. If rounding is selected, (RND = 1), a "1" is added to the MSB
oftheLSP (position PIS). The 32-bit product is zero-filled or signextendedas appropriate and passed as a 35-bit number to the accumulatorsection.
The accumulator function is controlled by ACC, SUB, and PREL.
Four functions may be selected: the accumulator may be loaded
with the current product; the product may be added to the accumulator contents; the accumulator contents may be subtracted from
the current product; or the accumulator may be preloaded from
the bidirectional ports.
Theoutput/preloadsectioncontainstheaccumulator/outputregister and the bidirectional ports. This section is controlled by the signals PREL, OEX, OEM, and OEL. When PREL is HIGH, the
output buffers are in high-impedance state. When the controls
OEX, OEM, and OEL are also HIGH, data present at the output
pinswill be preloaded into the appropriate accumulatorregisterat
the rising edge of CLK P. When PREL is WW, the OEX, OEM,
and OEL signals are enable controls for their respective threestate output ports.
x.
X.
SUB
PREL
23
OEM
CLKP
po.
2'
x,.
Xo
Yo. Po
X,.
X,.
OEL
RND
V1,P1
Y2. P2
Va. Pa
Y4. P4
SUB
Ys. Ps
ACC
CLKX
CLKY
Vee
TC
OEX
PREL
OEM
CLKP
p..
p..
P02
p.,
po.
P2.
P2.
P27
P2.
P2'
P2.
Va. Pa
Y7. P7
GND
Va, Pa
Vg, Pg
V1Q, P10
Y11,P11
Y12. P12
Y13. P13
Y14. P14
V15. P 15
p,.
P'7
p,.
p,.
P20
P2'
P22
P23
7C51 0-3
PGA
ThpView
9 8 7 6 5 4 3 2 1 68 6766 65 64 63 62 61
ACC
CLKX
CLKY
Vee
Vee
Vee
Vee
TC
OEX
X11
X,.
X,
LCc/pLCC
ThpView
10
11
12
13
14
15
16
17
18
19
20
21
22
X.
X.
x,.
X.
Pin Configurations
X,.
OEL
RND
X7
X.
X.
60
59
58
57
56
P2. Y2
P3. Va
P7. Y7
54
53
GND
GND
ps. Va
52
51
50
49
48
47
46
P12, Y12
P13, Y13
45
P15. Y15
44
p,.
55
X11
X'2
47
SUB
45
CLKX
~
Vee
TC
40
38
PREL CLKP
p..
41
OEX
39
OEM
P'2
34
NC
32
p••
p.,
30
P28
31
P29
~
37
p••
56
x,.
59
X7
X.
~
35
~
58
P26
60
26
X.
P2'
24
62
~
29
P27
27
Po.
25
X.
X.
P22
P20
65
X,
64
X2
22
p ••
23
p.,
66
20
p,.
21
p,.
18
p,.
P'7
68
7C511}·2
49
48
46
44
RND ACC CLKY
54
X.
67
Yo, Po
&~~OO~~~~55~~~M~~~~
~~~~~~~~~~~~~~~~~
QE[
63
P10. Y10
26
52
X,.
61
P11,Y11
25
53
X,.
X.
Pg, Yg
P14. Y14
50
X,.
57
P4. Y4
ps. Ys
ps. VB
55
51
NC
Xo
1
3
5
7
9
NC
Y1,P1 Va,P3 Ys. Ps Y7,~ Ya, Pa
•
8
10
Y2, P2 Y4. P4 Ye. Pa GND
Ya, Pa
2
4
6
11
Y1Q,
13
15
p,.
Y12,
P'2
Y14,
P14
Y111,2
Y1J,4
Y1~,6
P11
P,o
p,.
19
17
NC
7C51Q.4
6-18
-~
. '1= CYPRESS
F
CY7C510
SEMICCtIDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Range
Commercial
Milita.ylj
Ambient
Thmperature
O°Cto +70°C
5V±10%
- 55°Cto +l25°C
5V±10%
AmbientTemperatureUnderBias ........ - 55°Cto +l25°C
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ....................... - O.5V to + 7.0V
DC Voltage Applied to Outputs .......... - O.5V to Vee Max.
Output Current into Outputs (WW) ................ 10 rnA
Static Discharge Voltage .. . . . . . . . . . . . . . . . . . . . . . . . > 1001V
(Per MIL-STD-883 Metbod 3015)
Notes:
1. TA is the "instant on" case temperature.
Preload Function Table
Accumulator Function Table
Output Register
PREL
SUB
L
L
X
Q
Load
L
H
L
Q
Add
H
Q
Subtract
X
PL
Preload
PREL
OEM
OEL
XTP
MSP
LSP
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
Q
Q
Q
Q
Q
Q
Q
L
H
H
X
1
1
Z=
Q=
PL =
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
z
Z
Z
Z
Z
Z
Z
Z
PL
PL
PL
PL
z
z
z
Q
Q
Q
Q
z
Z
Z
Z
PL
PL
Z
Z
PL
PL
z
Operation
ACC
OEX
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
P
Vee
•
o
a
z
9
Q
Z
Z
PL
Z
PL
Z
PL
Z
PL
Output buffers at high impedance (disabled).
Output buffers at low impedance. Contents of output register
available through output ports.
Output disabled. Preload data supplied to the output pins will be
loaded into the output register at the rising edge of eLK P.
6-19
CY7CSIO
Pin Definitions
Signal
Name
XIS
-Xo
YIS - Yo
(PIS -Po)
X-Input Data. This 16-bit number may be
interpreted as two's complement or unsigned
magnitude.
I/O
Y -Input Data/LSP Output Data. When this
port is used to input a Y value, the 16-bit
number may be interpreted as two's complement or unsigned magnitude. This bidirectional port is multiplexed with the LSP output (PIS - Po), and can also be used to preload the LSP register.
P34 - P32
I/O Extended Product (XTP) Output Data. This
port is bidirectional. The extended product
emerges through this port. The XTP register
may also be preloaded through this port.
P31 - P16
I/O
PIS - Po
I/O LSP Output Data. This port is bidirectional.
The least significant product emerges
through this port. The LSP register may also
be preloaded through this port.
CLK X
Signal
Name
Description
I/O
I/O
Description
OEL
Output Enable Least. When LOW, the LSP
bidirectional port is enabled for output.
When HIGH, the output drivers are disabled
(high impedance) and the MSP port may be
used for preloading. See Preload Function
Thble.
PREL
Preload. When HIGH, the three bidirectional ports may be used to preload data into the
accumulator register at the rising edge of
CLK P. The three-state controls (OEX,
OEM, OEL) must be HIGH to preload data.
When LOW, the accumulated product is
loaded into the accumulator/output register
at the rising edge of CLK P. The ou~driv
ers must be enabled (OEX, OEM, OEL
must be LOW) for the accumulated product
to be output. Ordinarily, PREL, OEX,
OEM, and OELare tied together. SeeAccumulator Function Table.
MSP Output Data. This port is bidirectional.
The most significant product emerges
through this port. The MSP register may also
be preloaded through this port.
TC
'lWo's Complement Control. When HIGH,
the 7C51O is in two's complement mode,
where the input and output data are interpreted as two's complement numbers. The
device is in unsigned magnitude mode when
TC is LOW. This control is loaded into the
instruction register at the rising edge of CLK
X+CLKY.
X-Register Qock. X-Input data are latched
into the X-register at the rising edge of CLK
X.
CLKY
Y -Register Clock. Y -Input data are latched
into the Y -register at the rising edge of CLK
Y.
RND
CLKP
Product Register Clock. XTp, MSp, and LSP
are latched into their respective registers at
the rising edge of CLK P. If preload is selected, these registers are loaded with the
preload data at the output pins via the bidirectional ports. If preload is not selected,
these registers are loaded with the current
accumulatedproduct.
Round Control. When HIGH, rounding is
enabled and a "1" is added to the MSB of the
LSP (PIS). When LOW, the product is unchanged. This control is loaded into the instruction register at the rising edge of CLK X
+CLKY.
ACC
AccumulateControi. When HIGH, the accumulator/output register contents are added
to or subtracted from the current product
(XY) and this result is stored back into the
accumulator/output register. When LOW,
the product is loaded into the accumulator
register, overwriting the current contents.
This control is loaded into the instruction
register at the rising edge of CLK X +
CLKY.
SUB
Subtract Control. When both ACC and SUB
are HIGH, the accumulator register contents
are subtracted from the current product XY
and this result is written back into the accumulator register. WhenACC is HIGH and
SUB is LOW, the accumulator register contents and current product are sununed, then
written back to the accumulator register.
This control is loaded into the instruction
register at the rising edge of CLK X + CLK
Y. See Accumulator Function Thble.
Output Enable Extended. When Ww, the
extended product bidirectional port is enabled for output. When HIGH, the output
drivers are disabled (high impedance) and
the XTP port may be used for preloading.
See Preload Function Thble.
Output Enable Most. When WW, the MSP
bidirectional port is enabled for output.
When HIGH, the output drivers are disabled
(high impedance) and the MSP port may be
used for preloading. See Preload Function
Thble.
6-20
~~PRFSS
~-',
CY7C510
SEMICONDUClDR
CY7C510 Input Formats
Fractional 'I\vo's Complement Input
XIN
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
°
YIN
1115 14 13 12 11 10
~~~~~~~~~~~~~~~~
(Sign)
9
8
7
6
5
4
3
2
°
1
~~~~~~~~~~~~~~~~
(Sign)
Integer'I\vo's Complement Input
XIN
YIN
,--15_1_4_13_1_2_1_1_10_ _
9_8_7_ _
6_5_4_ _3_2_ _
1_0---,1115 14 13 12 11 10
_215 214 213 212 2" 210 29 28 27 26 25 24 23 22 21 20
(Sign)
9
8
7
6
4
5
3
2
°I
1
_215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
Unsigned Fractional Input
XIN
15 14 13 12 11 10
9
8
7
6
2-1 2-2 2-3 24 2-5 2-6 2-7 2-8 2-9 2-10
YIN
° II
2-11 2-12 2-13 2-14 2-15 2-16
5
4
3
2
15 14 13 12 11 10
1
9
8
7
6
4
5
2
3
1
°
2-1 2-2 2;3 ~ 2-5 2-6 2-7 2-8 2-9 2;10 2-11 2-12 2-13 2;14 2-15 2-16
YIN
,--1_5_1_4_13_1_2_11_1_0_9_8_7_ _6_5_ _
4_3_2_ _1_0--11115 14 13 12 11 10
9
8
7
6
5
4
3
2
°
1
~~~~~~~~~~~~~~~~
CY7C510 Output Formats
'I\vo's Complement Fractional Output
XTP
MSP
LSP
134 33 321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9
8
7
6
5
4
3
2
1
°
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(Sign)
'I\vo's Complement Integer Output
I~
XTP
TI
nl§
~
m28
~
MSP
26 25 24 23 22
n 20
~
U "
MI~
LSP
M 13 U 11 10 9
8
7
6
5
4
3
2
1
01
~~~~~~~~~~~~~~~~~~~~~~~~~~~p~~~~~~~
(Sign)
Unsigned Fractional Output
XTP
MSP
LSP
134 33 321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9
22 21 20
2-1 2-2 2-3
~
2-5 2-6 '];7 2-8 2-9 2-10 2-112-122-132-1242-15 2-16
2-172;182-192-20 '];21
'];22
8
7
6
5
4
3
2
1
0
'];23 2-24 2-25 '];26 '];27 '];28 '];29 2-30 ,];31 2-32
Unsigned Integer Output
I~
XTP
MSP
LSP
33 nll31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10
9
8
7
6
5
4
3
2
1
01
~~~~~~~~~~~~~~~~~~~~~~~~~~~p~~~~~~~
6-21
o
§
Unsigned Integer Input
X IN
~~~~~~~~~~~~~~~~
•
---
=;~
~i;;
CY7CSIO
CYPRESS
SEMICONDUCfOR
~,
Electrical Characteristics the Over Operating Rangel2]
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
VOL
Vrn
Output LOW Voltage
Input HIGH Voltage
VIL
Input LOW Voltage
IOH
IOL
IJX
Output HIGH Current
Output WW Current
Input Leakage Current
II
los(3]
Input Current; Max. Input Voltage
Output Short Circuit Current
IOZL
IOZH
lec(Ql)[4]
Output OFF (High Z) Current
Output OFF (High Z) Current
Supply Current (Quiescent)
ICC(Q2)[4]
Supply Current (Quiescent)
lec(Max.)l4]
Supply Current
Vee = Max., fCLK = 10 MHz
Min.
Max.
Units
0.4
V
V
0.8
V
V
2.4
Vee = Min., IOH = - 0.4 rnA
Vcc = Min., IOL = 4.0 rnA
2.0
- 004
4.0
-10
Vcc = Min., VOH = 2AV
Vee = Min., VOL = OAV
GND< VISVCC
Vee = Max., VIN = 7.0V
Vee = Max., VOUT = O.5V
Vee = Max., OE = 2.0V
-3
Vee = Max., OE = 2.0V
25
rnA
rnA
+10
10
- 30
JLA
rnA
rnA
- 25
JLA
JLA
Vee = Max., VIN = [GND to VIL] or [Vrn to Vcc]
Commercial
Vee = Max., Vcc~ VIN ~3.85V,
O.4V ~ VIN ~ GND
Military
30
rnA
20
25
rnA
Commercial
Military
100
110
rnA
Capacitance [5]
Description
InputCapacitance
Max.
Units
CIN
Parameters
TA = 25°C, f = 1 MHz,
Thst Conditions
8
CoUT
Output Capacitance
Vee = 5.0V
10
pF
pF
Output Loads used for AC Perfonnance Characteristics
R1
10250
OUTP~~n
J
40 PF
-=
R3
5000
TO
OUTPUT ~
PIN ~ _~.l
..l...
5PFL--I. Vx
R2
8170
-=
7C51Q.5
Normal Load (Load 1)
Equivalent to:
7C51()'6
Three-State Delay Load (Load 2)
THEvENIN EQUIVALENT
4550
OUTPUT 0>---....,..\1\.- - - 0 2.22V
7C51().7
Notes:
2.
3.
4.
See the last page of this specification for Group Asubgroup testing infonnation.
Not more than one outpnt shonld be shorted at a time. Duration of the
short circuit should not be more than one second.
For Icc measnrements, the outputs are three-stated. Tho quiescent
fignres are given for different input voltage ranges. Th calculate Icc at
5.
6-22
any given frequency, nse 30 rnA + Icc(AC) where Icc(AC) = (7 mN
MHz) X Oeck Freqnency for the commercial temperature range.
Icc(AC) = (8mA/MHz) X OockFreqnencyformilitarytemperature
range.
Thstedinitially and after any design or process changes that may affect
these parameters.
~
~-CYPRESS
-==-,
CY7C510
SEMlCalDUClDR
Switching Characteristics Over Operating Rangel2]
7C510-45
Parameters
Description
tMA
Multiply Accumulate Time
ts
Set-UpTime
Min.
Max.
7C510-55
Min.
45
Max.
Max.
25
20
Min.
65
55
20
7C510-75
7C510-65
Min.
Max.
75
Units
ns
25
ns
ns
tH
Hold Time
3
3
3
3
tpw
Clock Pulse Width
25
25
30
30 ,"".
tpDP
Output Clock to P
30
30
35
35
ns
tpDY
Output Clock to Y
30
30
35
35
ns
tpHZ
OEX, OEM to P;
DEL to Y (Disable Time)
HIGHtoZ
25
25
30
30
ns
LOWtoZ
25
25
30
30
ns
OE2(, OEM to P;
DEL to Y (Enable Time)
ZtoHIGH
30
30
35
35
ns
ZtoWW
30
30
35
35
tpLZ
tpZH
tpzL
tHCL
Relative Hold Time
0
0
ns
ns
ns
0
Parameter
Vx
All tpD'S
Vee
O.OV
tpHZ
VOH
*1.5V
VOH
O.5V
2.6V
tpLZ
0.5V
VOL
~~
t
~
O.OV
7~
2.6V
O.OV
tPZH
2.6V
tpZL
O.OV
{-"1.5V
2.6V
~1.5V
VOH
VOL
7C51C>-B
Pulse Width[7]
Set-Up and Hold Time[6]
DATA
INPUT
TIMING
INPUT
~
JIDffi :,,.
• 7=_t_H____ ::
-F-
LOW-HIGH~
~1.5V
PULSE -
tpw
---+-
7C510-10
1.5V
OV
7C51Q-9
Notes:
6. Cross hatched area is don't care condition.
7.
6-23
o
9
Ontput \\aveform-Measurement Level
VOL
•
a
Test Waveforms
Diagram shown for HIGH data only. Output transition may be opposite sense.
.J7~~croR
CY7C510
CY7C510 Timing Diagram
Ipw-
CLKX
CLKY
X.N, YIN
RND, TC
ACC, SUB
CLKP
::~~
OUTPUT
,..;.;;.;....------
p,Y
10...._ _ _ _ __
7C51D-11
Preload Timing Diagram
CLKP
PREL
OEX
OEM
QE[
OUTPUT
PINS
7C510-12
Three-State Timing Diagram
1/
THREE-STATE
CONTROL
(HIGH LEVEL)
THREE-STATE
OUTPUT
IPHZ ..
(DISABLE)
"""'
VOH
1.5V
VOL
~
I-
IpZH ..
(ENABLE)
VOH
1.5V
VOH - O.5V
(HIGH IMPEDANCE)
VO H +O.5V
(LOW LEVEL)
I--
IpZL ..
(ENABLE)
... IpLZ ....
(DISABLE)
1\
1.5V
VOL
7C510-13
6-24
.£S~
CY7CS10
~=CYPRESS
~F SEMICONDUClDR
'JYpical DC and AC Characteristics
NO~EDSUPPLYCURRENT
NO~ZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.2,----r--,----,---,
1.4
I
30
....
J3
o
~
~
1.0r----+-----r--~~--_1
J3
Vee=5.5V
VIN= 5.0V
o
w
O.B~---+--~~----+_--~
~
o
N
~
~
~
z
0.4 L-_-'-_ _.1-_---'-_----'
4.0
4.5
5.0
5.5
6.0
1.0
O.B
~
25
I
gj
20
Vcc= 5.0V
TA= 25°C
w
~
15
a:
1.2
o
~ .........
:J
~
SUPPLY VOLTAGE (V)
g
10
~
5
f=
:J
0.0
-55
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
25
125
o
o
"" ""
0.0
I""
~
1.6
2.4
OUTPUT VOLTAGE (V)
O.B
AMBIENTTEMPERATURE (0C)
3.2
•
o
NO~EDFREQUENCY
NO~ZEDFREQUENCY
()
zw
1.2
~1.4
w 1.1
fiI
IE
0
0
1.0
~
0.9
w
«
::;:
a:
0
z
.s....
()
:J
a:
u..
<'
1.6
:J
~
V
o
r·
w
TA = 25°C
o
...........
:J
5.0
5.5
6.0
~
15
Vee = 5.0V
~
10
SUPPLY VOLTAGE (V)
./
20
1/
~
f=
i5
0.6
-55
..,.,. f,..--
30
r----
o
z
4.5
35
zw
a: 25
a:
~ O.B
O.B
0.7
4.0
~
1.2
25
9
vs.OUTPUTVOLTAGE
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.3
a
OUTPUT SINK CURRENT
125
5
/
'"
/
Vcc= 5.0V
TA= 25°C
oV
I
0.0
1.0
AMBIENTTEMPERATURE (OC)
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NO~ZEDOUTPUTDELAY
NO~ED Icc vs. FREQUENCY
vs. OUTPUT LOADING
4.0
1.6
3.5
~
....
:J
....0..
:J
w
./
3.0
0
/
0
0
"
2.5
w
N
V
1.5
1.0
1/
o
«
::;:
a:
0
z
Vcc=5.0V _
TA = 25°C
I
..V
1.2
,/
~
/V
2.0
l/
1.4
.2
1.0
/
0.8
I
0.6
200 400
600 BOO 1000
CAPACITANCE (pF)
o
/
Vee=5.5V
TAMB = 25°C
VIN = 0,3V
I I I
5
10
FREQUENCY (MHz)
6-25
20
7C51().14
-
-"
,::Z
_".CYPRESS
CY7C510
~F SEMICONDUCTOR
Ordering Information
Speed
(ns)
45
55
65
75
Ordering Code
CY7C510-45DC
CY7C510-45GC
CY7C510-45JC
CY7C51O-45LC
CY7C51O-45PC
CY7C51O-55DC
CY7C510-55GC
CY7C510-55JC
CY7C51O-55LC
CY7C510-55PC
CY7C51O-55DMB
CY7C51O-55GMB
CY7C51O-55LMB
CY7C510-65DC
CY7C510-65GC
CY7C51O-65JC
CY7C51O-65LC
CY7C510-65PC
CY7C51O-65DMB
CY7C51O-65GMB
CY7C510-65LMB
CY7C51O-75DC
CY7C510-75GC
CY7C510-75JC
CY7C51O-75LC
CY7C51O-75PC
CY7C510-75DMB
CY7C51O-75GMB
CY7C510-75LMB
Package
1Ype
030
G68
J81
L81
P29
D30
G68
J81
L81
P29
D30
G68
L81
D30
G68
J81
L81
P29
030
G68
L81
D30
G68
J81
L81
P29
030
G68
L81
Operating
Range
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Commercial
Subgroups
VOH
VOL
VIH
VIL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IOH
IOL
Ilx
II
los
IOZL
IOZH
ICc(Ql)
Icc(Qz)
Icc(Max.)
Military
Commercial
Military
Parameters
Switching Characteristics
Parameters
Subgroups
Commercial
tMA
ts
tH
tpw
Military
tpDP
tpDY
tpHZ
tpLZ
tpZH
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
tpzL
tHCL
Document#: 38-00014-C
6-26
CY7C516
CY7C517
CYPRESS
SEMICONDUCTOR
Features
• Fast
- 38-ns clock cycle (commercial)
- 42-ns clock cycle (military)
• Lowpower
- Icc (max. at 10 MHz) 100 mA
(commercial)
- Icc (max. at 10 MHz) 110 mA
(military)
• Vcc marginof5V±10%
- All parameters guaranteed over
commercial and military operating
temperature range
=
=
16 x 16 Multipliers
• 16 x 16 bit parallel multiplication with
full precision 32-bit product
output
• 'l\vo's complement, unsigned magnitude, or mixed-mode multiplication
• CY7C516 is pin compatible and functionally equivalent to Am29516,
MPYOI6K, MPY016H
• CY7C517 is pin compatible and functionally equivalent to Am29517
Functional Description
The CY7C516/517 are high-speed 16 x 16
parallel multipliers that operate at 38-ns
clocked multiply times (26-MHz multiplication rate). The two input operands may
be independently specified as either two's
complement or unsigned magnitude numbers. Controls are provided for rounding
and format adjustment of the full-precision 32-bit product.
On the 7C516, individually clocked input
and output registers are provided to maximize throughput and to simplify bus interfacing. On the 7C517, a single clock (CLK)
is provided, along with three register enables. This facilitates the use of the 7C517
in microprogrammed systems. The input
and output registers arepositive-edge-triggered D-type flip-flops. The output registermay be made transparent for asynchronous output.
Logic Block Diagram
YIN/
TCX
XIN
CLKX
RND CLKY
XIN
LSPOUT
ENX
YIN/
LSPOUT
CLKY
32
FA
FT
CLKM
16
16
MSP OUT/LSP OUT
MSP OUT/LSP OUT
7C516-1
70516·2
Selection Guide
MaxintumMultiply Time
Clocked/Unc1ocked(ns)
Commercial
Military
7C516-38[1]
7C517-38
38/58
7C516-42
7C517-42
42/65
Notes:
1. 38-08 version available in cerDIP, LCC, PLCC, and PGA packages
only.
6-27
7C516-45
7C517-45
45/65
•
o
CY7C517
CY7C516
7C516-55
7CS17-55
ssm
ssm
7C516-75
7C517-75
75/100
75/100
ao
....I
CY7CS16
CY7CS17
4::::z
= - ' - CYPRESS
,
SEMlCONDUCTOR
Functional Description (continued)
1Wo output modes may be selected by using the output multiplexer
control,MSPSEL. Holding MSPSELLOW causes the most significant product (MSP) to be available at the dedicated output port.
The LSP is simultaneously available at the bidirectional port
shared with the Y inputs.
The other mode of output involves toggling the MSPSELcontrol,
to allow both the MSP and LSP to be available for output through
the dedicated 16-bit output port.
Pin Configurations
DIP{CerDIP
ThpView
9 8 7 6
P3. P19
21
22
5 4 3 2'1'68 676665 64 63 62 61 "
L.
60
59
58
57
56
55
54
7C516
53
(7C517)
52
51
50
49
48
P2. P1B
23
47
Xo
Y5. Ps
P1. P17
4B
OEL
po. P1B
24
25
Ya. Pa
45
~
U
CLK L (CLK)
CLKY (ENY)
PiS. P3i
P14. P3Q
P13. P29
P12. P28
P11. P27
Pl0. P26
Pg. P25
Pe. P24
P7. Pm
Pa. P22
PSI P21
P4. P20
10
11
12
13
14
15
16
17
18
19
20
NC
X'2
Xll
x,.
Xs
X.
X,
X.
X.
Xo
X.
OEL
(CLK) CLK L
X,.
X.
Xs
(ENY) CLKY
Yo. Po
X'2
X,.
X.
V1. P1
Y2. P2
Va. P3
X,.
X,.
CLKX (ENX)
Y4. P4
AND
TCX
TCY
X.
X.
x,
Y7. Pr
Ya. Pa
NC
53
Xll
55
X.
57
X7
59
Xs
61
X.
63
X,
65
52
X'2
50
X,.
49
X,.
48
X,.
47
CLKX
(ENX)
4B
AND
Y12. P12
FT
V13. P13
FA
Y14, P14
OEP
CLKM (ENP)
45
TCX
V1S. P1S
"
TCY
~
Vee
~
Vee
41
GND
40
GND
~
MSi'Si
38
FT
36
OEP
M
37
FA
CLKM
(ENP)
~
64
p,.
P30.
X,.
M
56
P28.
X.
P'2
28
P26.
58
p,.
X.
U
60
P24. P
X.
24
62
~
NC
~
22
64
p,.
29
P27.
Pll
V
P25. Pg
25
23
P.o. P
P21. Ps
67
CLKY
(ENY)
68
CLKL
(CLK)
20
P1B. P
21
P19. P3
17
19
21
23
25
Yo, Po Y2, P2 Y4, P4 Ve. Pa Ya. PB
•
18
20
22
24
26
V1,P1
Va,Pa
Ys. Ps
Y7. P7
Vg, Pg
27
p,.
V10.
~
V11,
Pll
29
Y12.
P'2
M
31
p,.
V14.
V1S.
19
P1B. P P17, P1
32
p,. p,.
V13 •
18
17
NC
6-28
P2, P1B
P29. Pi3
P3. Pi9
P28. P12
P4. P20
P27. P11
P5. P21
PS, P22
P26. P10
P25. Pg
Pr. P23
P24. Pa
70516-5
31
P,..
Xo
68
Pal. P15
P3Q. P14
p,.
OEL
NC
po. P1B
Pl. P17
P3l.
P22, Pa P23.Pr
X.
Vee
Vee
GND
GND
MSPSEL
Yg, Pg
PGA
ThpView
Xll
Y11,P11
V10, Pl0
70516-3
51
X7
Xg
X7
"
V~~M~~~~M~g~~.~~~
X.
X.
X.
7C516-4
·
CY7C516
CY7C517
.~
~=
~.F
CYPRFSS
SEMICONDUcroR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
AmbientTemperatureUnderBias ....... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - O.5Vto +7.0V
DC Voltage Applied to Outputs ......... - O.5V to Vee Max.
Output Current into Outputs (LOW) ............... 10 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 1000V
(Per MIL-SID-883 Method 3015)
Range
Commercial
MilitarylzJ
Ambient
Thmperature
O°Cto +70°C
Vee
5V±1O%
- 55°C to +125°C
5V±1O%
Note:
2.
TA is the "instant on" case temperature.
Pin Definitions
Signal
Name
XIS -
Xo
YIS -Yo
(PIS - Po)
I
0
P31 - PI6
(PIS - Po)
0
FT
FA
RND
TCX
TCY
Signal
Name
Description
I/O
X-Input Data. This 16-bit number maybe
interpreted as two's complement or unsignedmagnitude.
Y-lnput/LSP Output Data This 16-bit number
may be interpreted as two's complement or
unsigned magnitude.
MSP-Out/LSP-Out. This 16-bit port may cany
either the MSP (P31 - P16) or the LSP
(P15 - Po).
The MSP and LSP registers are made transparent (asynchronous operation) if FT is
HIGH.
Format Adjust Control. If FA is HIGH, a
full 32-bit product is output. If FA is LOW, a
left-shifted product is output, with the sign
bit replicated in the LSP. FA must be HIGH
for two's complement integer, unsigned
magnitude,andmixed-modemultiplication.
Output Multiplexer Control. When MSPSEL
is LOW, the MSP is available for output at the
MSP output port, and the LSP is available at
the Y input/LSP output port. When MSPSEL
is HIGH, the LSP is available at both ports
(above) and the MSP is not available.
I/O
OEP
OEL
CY7CS16 Only
CLKX
I
CLKY
CLKM
CLKL
CY7CS17 Only
CLK
I
Round Control. When RND is HIGH, a one
is added to the MSB of the LSP. This position
is dependent on the FA contro~ FA = HIGH
means RND adds to the 2- 15 bit ~~S)' FA =
LOW means RND adds to the 2- bit (P14).
Two's Complement Control X. X-input data
are interpreted as two's complement when
TCX is HIGH. TCX LOW means the data
are interpreted as unsigned magnitude.
'lWo's Complement Control Y. Y -input data
are interpreted as two's complement when
TCY is HIGH. TCY LOW means the data
are interpreted as unsigned magnitude.
Description
MSP-Out/LSP-Out Three-State Control.
When OEP is LOW, the output port is enabled; when OEP is HIGH, drivers are in a
high-impedancestate.
Y -1n!LSP Out Three-State Control. When
OEL is LOW, the tinIeshared port is enabled
for LSP output. When OEL is HIGH, the
output drivers are in a high-inIpedance state.
This is required for Y input.
X-Register Clock. X-input data and TCX
are latched in at the rising edge of CLK X.
V-Register Clock. V-input data and TCY
are latched in at the rising edge of CLK Y.
MSP Register Clock. The most significant
product (MSP) is latched in at the MSP Register at the rising edge of CLKM.
LSP Register Clock. The least significant
product (LSP) is latched in at the LSP Register at the rising edge of CLK L.
Clock. All enabled registers latch in their
data at the rising edge of CLK
X-Register Enable. When ENX is LOW, the
X register is enabled. X-input data and TCX
will be latched in at the rising edge of CLK
when the register is enabled. When ENX is
HIGH, the X register is in hold mode.
Y -Register Enable. ENY enables the Y register (see ENX).
Product Register Enable. ENP enables the
product register. Both the MSP and LSP sections are enabled by ENP (see ENX).
Input Formats (All Devices)
Fractional 'l\vo's Complement Input Fonnat
TCX,TCY= 1
I
15 14 13 12 11 10
XIN
7
Ym
0
11 15 14 13 12 11 10 9 8 7 6 5 4 3 2
_20 2-1 2-2 2"3 24 2.5 2-6 2.7 2-ll 2-9 2"10 2-11 2"12 2-13 2-14 2-15 _20 2-1 2-2 2"3 24 2-5 2-6 2-7 2-ll 2-9 2.10 2.11 2.122-13 2-14 2.15
(Sign)
(Sign)
9
8
6
5
4
3
2
0
6-29
II
o
C;
9
CY7C516
CY7C517
Input Formats (All Devices) (continued)
Integer 1Wo's Complement Input Format
TCX,TCY= 1
Xl!:!
115 14 13 12 11 109 8 7 6 5 4 3 2 1 0
_215 214 213 212 211 210 29 28 21 26 25 24 23 22 21 2°
II
(Sign)
Yl!:!
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
_215 214 213 212 211 210 29 28 21 26 25 24 23 22 21 2°
(Sign)
Unsigned Fractional Input Format
TCX,TCY=O
Xl!:!
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
II
0
~~~~~~~~~~~~~~~~
Ym
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
~~~~~~~~~~~~~~~~
Unsigned Integer Input Format
TCX,TCY=O
I
Xm
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
II
0
~~~~~~~~~~~~~~~~
Ym
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
I
~~~~~~~~~~~~~~~~
Output Formats (All Devices)
Fractional1Wo's Complement (Shifted) Outputl3]
FA =0
I
MSP
LSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1115 14 13 12 11 10
_20 2-1 2-2 2-3
(Sign)
~
2-5 2-6 2-1 2-ll Z-9 2-10 2-11 2-12 Z-13 2-14 2-15
9
8
7
6
5
4
3
2
1
0
_20 Z-16 2-11 2-18 2-19 2-20 2-21 Z-22 2-23 2-24 2-25 2-26 2-21 2-28 2-29 2-30
(Sign)
Fractional1Wo's Complement Output
FA =1
I
MSP
LSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1115 14 13 12 11 10
~~~~~~~~~~~~~~~~
9
8
7
6
5
4
3
2
1
0
~~~~~~~~~~~~~~~~
(Sign)
FA
I
Integer 1\vo's Complement Output
=1
MSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
II
~~~~~~~~~~~~~~~~
LSP
15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
I
~~~~~~~~~~~~~~~~
(Sign)
FA
Unsigned Fractional Output
=1
MSP
n ~ m
28
~
26 25 24 23 22
n
20 6
U
n
M
II ~
~~~~~~~~~~~~~~~~
LSP
M 13 U 11 10
9
8
7
6
5
4
3
2
1
0
~~~~~~~~~~~~~~~~
Unsigned Integer Output
FA =1
I
MSP
LSP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 "
15 14 13 12 11 10
~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~
Note:
3_ In this format an overflow occurs in the attempted multiplication ofthe
two'scomplementnumber 1.000 ... (-1 )withitself, yielding a product
of1.000 ... or-I.
6-30
9
8
7
6
5
4
3
2
1
0
I
CY7C516
CY7C517
.~PR£§
~, SEMICONDUCIDR
Electrical Characteristics
Parameters
Over Operating Rangel4]
Description
Thst Conditions
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
IOH
Output HIGH Current
IoL
IIX
Ios[5]
Output LOW Current
Input Leakage Current
Max.
204
Vee = Min., IOL = 4.0 rnA
Output OFF (Hi-Z) Current
Supply Current (Quiescent)
Vee = Min., VOH == 2.4V
Vee = Min., VOL = OAV
- 0.4
VSS < VIN.s Vee, Vee = Max.
Vee = Max., VOUT = OV
Vee = Max., OE = 2.0V
-10
-3
V
V
V
0.8
V
rnA
4.0
rnA
+10
- 30
!IA
rnA
-25
!IA
!IA
Commercial (-38)
Military ( -42)
40
rnA
All Others
30
Vee = Max., OE = 2.0V
25
GND.s VIN .s VILQ!...
VIH.s VIN .s Vee; OE = HIGH
Units
004
2.0
Output Short Circuit Current
Output OFF (Hi-Z) Current
IOZL
IOZH
Iee(Ql)[6]
Min.
Vee = Min., IOH = - 004 rnA
45
Icc(Q2)[6]
Supply Current (Quiescent)
Commercial
GND.s VIN .s OAV ~
3.85V.s VIN.s Vee; OE = HIGH Military
20
25
rnA
Iee(Max. )[6]
Supply Current
Ycc = Max., fcLK = 10 MHz;
Commercial
100
rnA
OE=HIGH
Military
110
Capacitance [7]
CIN
Parameters
Description
InputCapacitance
TA = 25°C,f= 1 MHz,
Thst Conditions
CoUT
Output Capacitance
Vee = 5.0V
Max.
Units
8
10
pF
pF
Output Loads Used for AC Performance Characteristics
R1
1025Q
OUTP~~n
40PFJ
PIN ~ _~l.
R2
--L
5PF~
-::- 8170
7C516-6
":"
Normal Load (Load 1)
Equivalent to:
5000
TO
OUTPUT~
Vx
70516-7
Three-State Delay Load (Load 2)
THEvENIN EQUIVALENT
4S5Q
OUTPUT
0>---_''."'.---<0
2.22V
7C516-8
Note.:
4. Seethe last page of this specification for Group Asubgroup testing information.
5. Not more than one output should be shorted at a time. Duration of the
short circuit should not be more than one second.
6. 1\\10 quiescent fJgUIes are given for different input voltage ranges. Th
calculate Icc at any given clock frequency, use 30 rnA + Icc(AC)
7.
6-31
where Icc(AC) = (7 mA/MHz) X Clock Frequencyfor the commercial temperature range. Icc(AC) = (8 mA/MHz) X Clock Frequency
for military temperature range.
Thsted initially and after any design or process changes that may affect
these parameters.
II
CY7C516
CY7C517
.J1L~cmR
Switching Characteristics Over Operating Rangel2]
Parameters
Description
tMUC
tMC
ts
tH
tSE
tHE
tpWH, tpWL
tpoSEL
tpop
tpOY
tpHZ
tpLZ
tpZH
tpZL
Unclocked Multiply Time
Clocked Multiply Time
Xi, Yi,RND, Tcx, TCYSet-UpTime
Xi, Yj, RND, TCX, TCY Hold Time
ENX, ENY, ENP Set-Up Time (7CS17 Only)
ENX, ENY, ENP Hold Time (7CS17 Only)
Clock Pulse Width (HIGH and LOW)
MSPSEL to Product Out
Output Clock to P
Output Clock to Y
OEP Disable Time
HIGHtoZ
LOWtoZ
OEP Enable Time
ZtoHIGH
ZtoLOW
OEL Disable Time
HIGHtoZ
LOWtoZ
OEL Enable Time
ZtoHiGH
ZtoLOW
Clock LOW Hold Time CLK XY Relative to
tLHZ
tLLZ
tLZH
tLZL
tHCL
Thst
Conditions
Description
tMUC
tMC
ts
tH
tSE
tHE
tpWH, tpWL
tpOSEL
tpop
tpOY
tpHZ
tpLZ
tpZH
tpZL
tLHZ
tLLZ
tLZH
tLZL
tHCL
Unclocked Multiply Time
Clocked Multiply Time
Xj, Y i, RND, TCX, TCY Set-Up Time
Xi, Y i, RND, TCX, TCY Hold Time
ENX, ENY, ENP Set-Up Tune (7CS17 Only)
ENX, ENY, ENP Hold Time (7CS17 Only)
Clock Pulse Width (HIGH and LOW)
MSPSEL to Product Out
Output Clock to P
Output Clock to Y
OEP Disable Time
HIGHtoZ
LOWtoZ
OEP Enable Time
ZtoHIGH
ZtoLOW
OEL Disable Time
HIGHtoZ
LOWtoZ
OELEnabie Time
ZtoHiGH
ZtoLOW
Clock LOW Hold Time CLK XY Relative to
CLKMrJ8]
Min.
Load 1
Max.
7CS16-42
7CS17-42
Min. Max.
Load 1
Thst
Conditions
0
7CS16-SS
7CS17-S5
Max.
Min.
Note:
8. Th ensure that the correct product is entered in the output registers,
new data may not be entered into the input registers before the output
registers have been clocked.
6-32
7CS16-7S
7CS17-7S
Min.
Max.
100
75
2S
3
2S
3
30
20
3
20
3
25
Load 1
0
75
55
25
30
30
2S
2S
30
30
2S
2S
30
30
Load 2
0
2S
30
30
2S
2S
30
30
2S
2S
30
30
21
30
30
17
17
2S
2S
17
17
2S
2S
0
Load 1
65
45
20
3
20
3
20
8
3
15
3
10
18
2S
2S
15
15
23
23
15
15
23
23
Load 2
7C516-4S
7CS17-4S
Min. Max.
65
42
58
38
7
3
10
3
10
CLKML[8]
Parameters
7CS16-38LIJ
7CS17-38
30
35
35
30
30
35
35
30
30
35
35
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.
CY7C516
CY7C517
'~PRESS
-?
SEMICONDUCTOR
Test Waveforms
Parameter
All tpDs
Vx
Vee
Output waveform-Measurement Level
VOH
*1.5V
VOL
lpHZ,ILHZ
O.OV
VOH
O.5V
lpLZ,ILLZ
2.6V
O.5V
VOL
lpZH,ILZH
lpZL,ILZL
:~
: 7~
O.OV
~5V
2.6V
~.5V
O.OV
2.6V
O.OV
-2.6V
-VOH
•
_VOL
o
7C516-9
a
o
Pulse Width[lOj
Set-Up and Hold Time[9j
..J
DATA
INPUT
TIMING
INPUT
~'r'"JlOOf;:
LOW-HIGH9=LOW
PULSE -
_
~
---
1.5V
Tpw
7C516-11
ov
7C516-10
Three-State Timing Diagram
THREE-STATE
CONTROL
tLZH, tPZrL
VOH
1.5V
VOL
(ENABLE) ~
VOH
1.5V
lLHZ. tpH
(DISABLE)
HIGH LEVEL
VOH - O.5V
THREE-STATE
OUTPUT
HIGH IMPEDANCE
1.5V
VOL
VOH +O.5V
LOW LEVEL
tLLZ, tpLZ
tLZL, tPZL
(DISABLE)
(ENABLE)
Notes:
9. Cross-hatched area is don't care condition.
7C51&12
10. Diagram shown for HIGH data only. Output transition may be opposite sense.
6-33
CY7C516
CY7C517
.A~NDucroR
Timing Diagram 7CSt6
tpw
CLKX
CLKY
l-"'>-C'lJ-;;>-o
6 5 4 3 2 ,1,44434241 40
18
17
RAM3
RAMo
F
NC
9
10
Vee
11
0
12
=:
10
13
12
CP
NC
14
15
16
17
38
37
P
35
G
34
33
F3
GND
OVR
en + 4
32
31
30
29
18192021 22232425262728
MO..-C\JC";)OC')(\J..-0Q
en
14
15
13
(Above which the useful life maybe impaired. Foruserguidelines,
nottested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential
(Pin 11 to Pin 33) .. . .. .. .. .. .. .. .. . .. ... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) ............... 30 rnA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(Per MIL-STD-883 Method 3015)
>200 rnA
Latch-Up Current (Outputs)
7C901-3
Oa:l(DCOIDOOOOOZ
Operating Range
Range
Ambient
Thmperature
Vee
Commercial
O°Cto +70°C
5V ±1O%
- 55°Cto +125°C
5V ±1O%
Militaryll]
Notes:
l. TA is the "instant on" case temperature.
Pin Definitions
Signal
Name
Ao-
Signal
Name
Description
I/O
These four address lines select one of the registers in the stack and output its contents on
the (internal) A port.
A3
Bo - B3
These four address lines select one of the registers in the stack and output its contents on
the (internal) B port. This can also be the destination address when data is written back into
the register file.
10 - 18
These nine instruction lines select the ALU
data sources (10, 1, 2), the operation to be performed (13,4,5), and what data is to be written
into either the Q register or the register file
YO-Y3
I/O These two lines are bidirectional and are controlled by the 16, 7, 8 inputs. Electrically they
are three-state output drivers connected to the
TTL-compatible CMOS inputs.
Outputs: When the destination code on lines
16, 7, 8 indicates a shift left (UP) operation the
three-state outputs are enabled and the MSB
of the Q register is output on the Q3 pin and
the MSB of the ALU output (F3) is output on
the RAM3 pin.
Inputs: When the destination code indicates a
shift right (DOWN) the pins are the data inputs to the MSB of the Q register and the
MSB of the RAM.
Qo
RAMo
I/O These two lines are bidirectional and function
in a manner similar to the Q3 and RAM3lines,
except that they are the LSB of the Q register
and RAM.
These are four data input lines that may be selected by the 10, 1, 2 lines as inputs to the ALU.
OE
0
These are three-state data output lines that,
when enabled, output either the output of the
ALU or the data in the A latches, as determined by the code on the 16, 7, 8 lines.
Output Enable. This is an active LOW input
that controls the Yo - Y 3 outputs. When this
signal is LOW the Y outputs are enabled and
when it is HIGH they are in the high-impedance state.
6-39
Description
Clock Input. The LOW level of the clock
writes data to the 16 x 4 RAM. The HIGH level of the clock writes data from the RAM to
the A-port and B-portlatches. The operation
of the Q register is similar. Data is entered
into the master latch on the LOW level of the
clock and transferred from master to slave
when the clock is HIGH.
Q3
RAM3
(16,7,8),
Do-D3
I/O
CP
Cn
I
The carry-in to the internal ALU.
Cn+4
0
The carry-out from the internal ALU.
II
o
a
o
..J
CY7C901
Pin Definitions (continued)
Signal
Name
I/O
Description
The carry generate and the carty propagate
outputs of the ALU, which may be used to perform a carry look-ahead operation over the 4
bits of the ALU.
G,P
o
OVR
0
Overflow. This signal is logically the exc1usiveOR of the carry-in and the carty-out of the
MSB of the ALU. This pin indicates that the
result of the ALU operation has exceeded the
capacity of the machine. It is valid only when
the sign bits of the operands are identical (add)
or opposite (substract).
=0
0
Open collector output that goes HIGH if the
data on the ALU outputs (Fo, I, 2, 3) are all
LOW. It indicates that the result of an ALU
operation is zero.
0
The most significant bit of the ALU output.
F
F3
Description of Architecture
General Description
A block diagram of the CY7C901 is shown inFigure 1. The circuit
is a 4-bit slice consisting of a register file (16 x 4 dual-port RAM),
the ALU, the Q register, and the necessary control logic. It is expandable in 4-bit increments.
RAM
The RAM is addressed by two 4-bit address fields (Ao - A3, Bo B3) that cause the data to appear at the A or B (internal) ports. If
the A and B addresses are the same, the data at the A and B ports
will be identical.
New data.is written into the RAM location specified by the B address when the RAM write enable (RAM EN) is active and clock
input is LOW. Each of the four RAM inputs is driven by a 3-input
multiplexer that allows the outputs of the ALU (Fo, 10 :z, 3) to be
shifted one bit position to the left, the right, or not to be sllifted.
The other inputs to the multiplexer are from the RAM3 and RAMo
I/O pins.
For a shift left (up) operation, the RAM3 output buffer is enabled
and the RAMo multiplexer input is enabled. For a shift right
(down) operation the RAMo output buffer is enabled and the
RAM3 multiplexer input is enabled.
The data to be written into the RAM is applied to the D inputs of
the CY7C901 and is passed (unchanged) through the ALU to the
RAM location addressed by the B word address.
The outputs of the RAM A and B ports drive separate 4-bitlatches
that are enabled (follow the RAM data) when the clock is HIGH.
The outputs of the A latches go to three multiplexers whose outputs drive the two inputs to theALU (Ro, 10 2, 3) and (So, 1o:z, 3) and
the (Yo, 1, 2, 3) chip outputs.
ALU (Arithmetic Logic Unit)
The ALU can perform three arithmetic and five logical operations on two 4-bit input words, Rand S. The R inputs are driven
from four 2-input multiplexers whose inputs are from either the
(RAM) A-port or the external data (0) inputs. The S inputs are
driven from four 3-input multiplexers whose inputs are from the
A-port, the B-port, or the Q register. Both multiplexers are controlled by the 10, 10 2 inputs as shown in 'lIlble 1. This confignration of multiplexers on the ALU Rand S inputs enables the user
to select eight pairs of combinations of A, B, D,Q, and "0" (unseleeted) inputs as 4-bit operands to the ALU. The logical and
arithmetic operations performed by the ALU upon the data present at its Rand S inputs are tabulated in Table 2. The ALU has a
carry-in (Co) input, carty-propagate (P) output, carty-generate
(G) output, carry-out (Cn + 4) and overflow (OVR) pins to enable the user to (1) speed up arithmetic operations by implementing carry look-ahead logic and (2) determine if an arithmetic
overflow has occurred.
As shown in Table 3, th~ AI:U data outputs (FO, 1, 2, 3) are routed
to the RAM, the Q regISter mputs, and the Y outputs under control of the 16, 7, 8 control signal inputs. In addition, the MSB of
the ALU is output as F3 so that the user can examine the sign bit
without enabling the three-state outputs. The F = 0 output, used
for zero detection is HIGH when all bits of the F output are
LOW. It is an open-drain output which may be wire ORed across
multiple 7C901 processor slices.
Q Register
The Q register functions as an accumulator or temporary storage
register. Physically it is a 4-bit register implemented with masterslave latches. The inputs to the Q register are driven by the outputs
from four 3-input multiplexers under control of the ~, 7, 8 inputs.
The Qo and Q31/0 pins function in a manner similar to the RAMo
and RAM3 pins. The other inputs to the multiplexer enable the
contents of the Q register to be shifted up or down, or the outputs
of the ALU to be entered into the master latches. Data is entered
into the master latches when the clock is LOW and transferred
from master to slave (output) when the clock changes from LOW
to HIGH.
ALU Source Operand and ALU Functions
The ALU source operands and ALU function matrix is summarized in Table 4 and separated by logic operation or arithmetic operation in Tables 5 and 6, respectively. The 10,1, 2 lines select eight
pairs of source operands and the 13, 4, 5 lines selectthe operation to
be performed. The carry-in (CJ signal affects the arithmetic result
and the internal flags; not the logical operations.
Conventional Addition and Pass·Increment/Decrement
When the carty-in is HIGH and either a conventional addition or
a pass operation is performed, one (1) is added to the result. If the
decrement operation is performed when the carry-in is LOW, the
value of the operand is reduced by one. However, when the same
operation is performed when the carry-in is HIGH, it nullifies the
decrement operation so that the result is equivalent to the pass operation.
Subtraction
Recall that in two's complement integer coding - 1 is equal to all
ones, and that in one's complement integer coding zero is equal to
all ones. 'Ib convert a positive integer to its two's complement (negative) equivalent, invert (complement) the number and add 1 to it;
i.e., TWC = ONC + 1. In Table 6 the symbol - Q represents the
two's complement of Q so that the one's complement of Q is then
-Q-1.
6-40
-_.C<:
RAMO~
I
T
)(
!!!II~III
RAMS
Ili~ ~
rn~N
r:=;c~~*lTf11fJ~OS
1
ADRIr
AS
DATA OUT
L~====o:o======~.::=~
RAM
Ao A1 A2 AS
WE
EN
,1
CLOCK~
A LATCH
Cpr--v-r E
1 1 1
B LATCH
I'
IE
., j j
0\
..,.
,....
I
DATAi -2
INPUTS
g1
o
f,;l
DO
II ~
°
OEN
REGISTER
00
01
°3
02
ALU
DESTINATION
DECODE
~16
17
IS
I
I I I I
ALU
~~~!~~
DECODE
ISS
ALU
14
FUNCTION
15
DECODE
D:J
D2
D1
1------------+-111CP
Ao A1 A2 AS
I I I I
S~
2
8
I'
10
11
12
,'\)
ARITHMETIC LOGIC UNIT (ALU)
1>C
n
'=::::::L
t---C + 4
n
F 1
FO
1 I
1
F2
FS
I-- OVR
~F~O(O/c) LFS
--_._---_._-
NOTE: LSB IS NUMBERED ·0·; MSB IS NUMBERED "S".
X BIDIRECTIONAL
_ . . . UNIDIAECllONAL
OE
~
!
Yo
Y1
Y2
a
n
t
YS
Figure 1. CY7C901 Block Diagram
LOGIC
•
~
=>
~
:.il~NDUcroR
CY7C901
Functional Tables
Thble 1. ALU Source Operand Control
AWSource
Operands
MicroCode
Mnemonic
AQ
AB
ZQ
ZB
ZA
DA
DQ
DZ
12
L
L
L
L
H
H
H
H
11
L
L
H
H
L
L
H
H
Octal
Code
10
Thble 2. ALU Function Control
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
R
MicroCode
S
Q
B
Q
B
A
A
Q
A
A
°0
0
D
D
D
Mnemonic
Is 11
ADD
SUBR
SUBS
OR
AND
NOTRS
XOR
XNOR
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
13
L
H
L
H
L
H
L
H
Octal
Code
0
1
2
3
4
5
6
7
AW
Function
RPlusS
SMinusR
RMinusS
RORS
RANDS
RANDS
RXORS
RXNORS
Symbol
R+S
S-R
R-S
RVS
Ri\S
Ri\S
R¥S
R¥S
0
Thble 3. ALU Destination Control
RAM Function
MicroCode
Mnemonic
Is
QREG
L
NOP
RAMA
Octal
Code
0
Q-Reg. Function
Shift
Load
Shift
Load
X
None
None
X
HQ
None
X
None
17
L
I(;
L
L
H
1
X
None
L
H
L
2
None
HB
RAMF
L
H
H
3
None
HB
X
None
RAMQD
H
L
L
4
DOWN
F/2.B
DOWN
Q/2.Q
RAMD
RAMQU
H
L
H
5
DOWN
F/2.B
X
H
H
L
6
UP
2F.B
UP
None
2Q.Q
RAMU
H
H
H
7
UP
2F.B
X
None
L
RAM Shifter
Y
Output
F
F
A
F
F
F
F
F
RAMo
X
RAM3
X
Q Shifter
Qo
X
Q3
X
X
X
X
X
X
X
X
X
X
X
X
X
Fo
1N3
Qo
Fo
1No
1N3
Qo
1N3
X
F3
1No
F3
1No
X
Q3
Q3
. IS. a TIL mput mtemally connected to a three-state output that ..
x = Don't care. Electrically, the mput shift pm
IS m the high-Impedance state.
A = Register addressed by A inputs.
B = Register addressed by B inputs.
UP is toward MSB, DOWN is toward LSB.
Thble 4. Source Operand and ALU Function Matrix
1210 Octal
AWSource
Octal
1543 AWFunction
0
Cn=L
RplusS
Cn ="
1
Cn=L
SminusR
Cn ="
2
Cn=L
RminusS
Co="
3
RORS
0
1
2
3
4
5
6
7
D,O
A,Q
A,B
O,Q
O,B
o,A
D,A
D,Q
A+Q
A+B
Q
B
A
D+A
D+Q
D
A+Q+l
A+B+l
Q+l
B+l
A+l
D+A+l
D+Q+l
D+l
Q-A-l
B-A-l
Q-l
B-1
A-I
A-D-l
Q-D-l
-D-l
Q-A
B-A
Q
B
A
A-D
Q-D
-D
A-Q-l
A-B-l
-Q-l
-B-1
-A-l
D-A-l
D-Q-l
D-l
A-Q
A-B
-Q
-B
-A
D-A
D-Q
D
AVQ
AVB
Q
B
A
DVA
DVQ
D
0
0
Di\A
Di\Q
0
B
A
Di\A
Di\Q
0
4
RANDS
Ai\Q
Ai\B
5
RANDS
Ai\Q
Ai\B
0
Q
6
RXORS
A¥Q
A¥B
Q
B
A
D¥A
D¥Q
D
7
RXNORS
A¥Q
A¥B
Q
B
A
D¥A
D¥Q
D
+ = Plus; -
= Minus; V = OR; /I = AND; ¥ = XOR
6-42
':~PRESS
=--'J'
CY7C901
SEMICONDUCTOR
Thble 5. ALU Logic Mode Functions
Octal
1543. 1210
40
41
45
46
30
31
35
36
60
61
65
66
70
71
75
76
72
73
74
77
62
63
64
67
32
33
34
37
42
43
44
47
50
51
55
56
Group
AND
OR
XOR
XNOR
INVERT
PASS
PASS
"ZERO"
MASK
Thble 6. ALU Arithmetic Mode Functions
Octal
Function
AflQ
AflB
DflA
DflQ
AVQ
AVB
DVA
DVQ
A¥Q
A¥B
D¥A
D¥Q
A¥Q
A¥B
D¥A
D¥Q
Q
B
A
0
Q
B
A
D
Q
B
A
D
0
0
0
0
AflQ
AflB
O/IA
O/lQ
1543.
1210
00
01
05
06
02
03
04
07
12
13
14
27
22
23
24
17
10
11
15
16
20
21
25
26
6-43
Cn = o(LOW)
Group
ADD
Function
A+Q
A+B
D+A
D+Q
Q
PASS
B
A
D
Decrement
Q-l
B-1
A-I
D-l
l'sComp.
-Q-l
-B-1
-A-l
-D-l
Subtract
Q-A-l
(l'sComp.) B-A-l
A-D-l
Q-D-l
A-Q-l
A-B-l
D-A-l
D-Q-l
Cn = 1 (HIGH)
Group
Function
ADD plus A+Q+l
one
A+B+l
D+A+ 1
D+Q+l
Increment·
Q+l
B+l
A+l
D+l
PASS
Q
B
A
D
2's Comp.
-Q
(Negate)
-B
-A
-D
Subtract
Q-A
(2'sComp.)
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
o
C;
9
lIAL~C1DR
CY7C901
Logic Functions for G, P, Cn + 4, and OVR
Definitions (+ = OR)
The four signals G, P, Cn + 4, and OVR are designed to indicate
cany and overflow conditions when the CY7C901 is in the add or
subtract mode. Table 7 indicates the logic equations for these four
signalsfor each of the eightALU functions. The R and S inputs are
the two inputs selected according to Table 1.
Po
PI
Pz
= Ro + So
= Rl + Sl
= Rz + Sz
Go
Gl
Gz
~=~+~
= RoSo
= RISI
= RzSz
~=~~
C4 = G3 + P3GZ + P3PZGl + P3PZGO + P3PzPlPOCn
C3 = Gz + PZGI + PZPIGO + PZPIPOCn
llIble 7. G, Po CD + " and OVR Logic Functions
1543
Function
P
G
0
R+S
P3P2PlPO
G3 +P3Gz+P~ZGI-l:.P~ZPIGO
1
S-R
2
R-S
••
I
I
CD +4
C4
OVR
C3¥C4
Same as R + S equations, but substitute Ri for Ri in definitions
Same as R + S equations, but substitute Si for Si in definitions
3
RVS
LOW
P3PZPlPO
4
RI\S
LOW
G3+ GZ+ G I+ GO
5
RI\ S
LOW
6
R¥S
7
R¥S
~+GZ+GI+GO
•
•
I
I
P3PZPlPO + Cn
G3+ GZ+ GI +Go+Cn
I
I
P3PZPlPO+ Cn
~+GZ+GI +Go+Cn
Same as R 1\ S equations, but substitute Ri for Ri in definitions
Same as R ¥ S, but substitute Ri for Ri in definitions
~ + P3GZ+ P3PZG l + P3PZP l G O
I
G, + P,GZ + P,PZGl
+ P~ZPIPO(GO + Co)
Notes:
2.
I
I
[Pz + GzPI + (hGIPO + G2GIGOc.J ¥ [1'3 + G3P2 + G3G2PI + ~G2GIPO + G3GzGIGoCnl
+=OR
6-44
I
Note 2
••
••
. ::z
CY7C901
~=CYPRESS
~_.J, SEMICONDUCTOR
Electrical Characteristics Over Commercial and Military Operating Rangel.3, 4]
Description
Parameters
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
VIH
VIL
IIX
IOH
IoL
Input HIGH Voltage
Input LOW Voltage
Input LeakageCurrent
Output HIGH Current
Output LOW Current
Ioz
Ise
lee
Output LeakageCurrent
Output Short Circuit Currend5]
Supply Current
lee!
Supply Current
Thst Conditions
Min.
Vee = Min., IOH = - 3.4 IDA
Vee = Min.,
IOL = 20 IDA Commercial, 16 IDA Military
Vss~ VIN ~ Vee, Vee = Max.
Vee = Min., VOH = 2.4V
Commercial
Vee = Min., VOL = O.4V
Military
Vee = Max., VOUT = Vss to Vee
Vee = Max., VOUT = OV
Commercial-31
Vee = Max.
Commercial- 23
Military-27, -32
Commercial
VIH~ Vee -1.2Y, 10 MHz,
VIL~O.4V
Military
Max.
Units
0.4
V
V
2.0
- 3.0
Vee
0.8
V
V
-10
10
2.4
- 3.4
20
16
-40
IJA
IDA
IDA
+40
IJA
-85
70
80
90
26.5
31
IDA
IDA
IDA
Parameters
Description
InputCapacitance
Output Capacitance
CoUT
Thst Conditions
TA= 25°C,f= 1 MHz,
Vee=5.0V
Max.
5
7
Units
pF
pF
Output Loads used for AC Performance Characteristics[7, 8, 9]
+5V
VOUT~
-i 1
CL
2000
1500
7C901·5
7C90Hl
Open drain (F = 0)
All outputs except open drain
Notes:
3. See the last page ofthis specification for Group A subgroup testing information.
4. VccMin. = 4.5V, VccMax. = 5.5V
5. Not more tban one output should be shorted at a time. Durationoftbe
short circuit should not be more tban one second.
6. Thsted initially and after any design or process changes tbat may affect
these parameters.
7.
8.
CL = 50 pF includes scope probe, wiring and stray capacitance.
CL = 5 pF for output disable tests.
9. Loads shown above are for commercial (20 rnA) IOL specifications
6-45
only.
o
C;
9
Capacitance [6]
CIN
•
CY7C901
Cycle Time and Clock Characteristics[2)
CY7C901-23 Commercial and CY7C901-27
Military AC Perfonnance Characteristics
The tables below specify the guaranteed AC performance of
these devices over the commercial (O°C to 70 0 C) and militaIy
(- 55°C to + 125°C) operating temperature range with Vcc vaI)'ing from 4.5V to 5.5Y. All times are in nanoseconds and are
measured between the 1.SV signal levels. The inputs switch between OV and 3V with signa\ transition rates of IV per nanosecond. All outputs have maximum DC current loads. See "Electrical Characteristics" for loading circuit information.
This data applies to parts with the following numbers:
CY7C901-23PC CY7C901-23DC
CY7C901-23LCCY7C901-27JC
CY7C901-27DMB CY7C901-27LMB
CY7C901
-23
-27
Read-Modify-Write Cycle (from selection
of A, B registers to end of cycle)
23ns
27ns
Minimum Cock LOW Time
Y
F3
23
27
23
27
D
30
21
Cn
17
33
24
18
10,1,2
26
28
33
23
17
27
13,4,5
27
18
26
-
-
A Bypass ALU (I = 2XX)
26
16
24
30
20
16
25
24
-
Clock (LOW to lllOH)
24
27
23
A,BAddress
16,7,8
27
13ns
IOns
23ns
Minimum Oock lllOH TlDIe
Minimum Oock Period
Combinatorial Propagation Delays (CL = 50 pF)[3,10)
y
Th Output
F3
C.+4
From Input
Speed (ns)
43 MHz 37 MHz
Maximum Cock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
Ca +4
23
27
30
33
20
23
14
14
24
26
24
26
G,P
G,P
23
28
20
24
24
27
33
21
F=O
OVR
RAMo
F=O
23
27
33
30
OVR
RAM3
27
23
23
27
33
30
21
16
24
17
15 ns
12ns
27ns
Qo
QJ
23
27
30
22
33
25
-
18
25
19
27
-
26
-
-
-
25
19
29
26
24
18
25
26
27
24
24
27
26
-
-
-
-
21
27
21
21
21
-
-
-
-
24
27
24
26
24
27
19
20
28
-
-
- -
-
-
26
23
26
23
25
-
Set-Up and Hold Times Relative to Clock (CP) Input[3,10,l1)
CP:
~
Set-UpTime
BeforeH. L
Speed (ns)
A, B Source Address
23
10
B Destination Address
10
Data
-
-
7
9
-
-
1012
134S
1678
RAMo
3,QO 3
I
27
12
12
Co
Hold Time
AfterHtL
23
27
•
Hold Time
AfterL.H
23
I 27
0
Set-UpTime
BeforeLtH
27
23
J
o(Note 12)
21, 10 + tPWL (Note 13)
Do Not Change
t
-
0
16
0
13
19
-
•
'7
'-1--
0
0
0
0
19
Do Not Olange
-
I
t
0
9
Output Enable/Disable Times[2)
Output disable tests performed with CL = 5 pF and measured to
O.5V change of output voltage level.
Notes:
10. A dash indicates a propagation delay path or set-up time constraint
does not exist.
11. Certain signals must be stable during the entire clock LOW time to
ayOid erroneous operation. This is indicated by the phrase "do not
change."
12. Source addresses must be stable prior to the clock
L transition to
allow time to access the source data before the latches close. The A address may then be changed. The B address can be changed if it is not
H.
Device
Input
Output
Enable
Disable
CY7C901-23
DE
14
16
CY7C901-27
OE
y
y
16
18
a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time.
13. The set-up time prior to the clock
H transition is to allow time for
data to be accessed, passed through the ALU. and returned to the
RAM It includes all the time from stable A and B addresses to the
clock L. H transition, regardless of when the clock H • L transition
6-46
L.
occurs.
1P~~
CY7C901
CY7C901-31 Commercial and CY7C901-32
Military AC Performance Characteristics
Cycle Time and Clock Characteristics[2]
-32
-31
CY7C901
The tables below specify the guaranteed AC performance of
these devices over the commercial (O°C to 70 0 q and militlll}'
(- 55°C to +125°q operating temperature range with Vcc varying from 4.5V to 5.5Y. All times are in nanoseconds and are
measured between the 1.5V signal levels. The inputs switch between OV and 3V with signal transition rates of IV per nanosecond. All outputs have maximum DC current loads. See "Electrical Characteristics" for loading circuit information.
This data applies to parts with the following numbers:
CY7C901-31PC CY7C901-31DC
CY7C901-31LC
CY7C901-31JC
CY7C901-32DMB CY7C901-32LMB
32ns
Read-Modify-Write Cycle (from selection 31 ns
of A, B registers to end of cycle)
Maximum Oock Frequency to shift Q
32 MHz 31 MHz
(50% duty cycle, I 432 or 632)
17ns
16ns
Minimum Oock LOW Time
15ns
Minimum aock mOH Tune
15ns
32ns
Minimum Oock Period
31 ns
For fasterperfonnance see CY7C901-23 specificaoon on page 9.
=
Combinatorial Propagation Delays (CL = 50 pF)[3,10]
To Output
From Input
Speed (ns)
A, BAddress
D
Cn
1012
1345
1678
A Bypass ALU (I - 2XX)
Clock (LOW to mOll)
Y
F3
c,,+4
Y
F3
c,,+4
31
32
40
48
30 37
20
21
40
35
35
40
30
32
44
34
-
-
37
35
44
31
40
30
22
35
35
25
35
35
32
48
37
25
40
40
29
40
40
31
40
30
22
35
35
32
48
37
25
40
40
G,P
G,P
31
37
32
48
40
40
31
40
38
25
37
38
40
OVR
OVR
31
32
40
48
30 37
22
25
40
35
35
40
-
-
40
35
F=O
F=O
-
-
-
-
-
-
-
-
35
40
35
40
35
40
35
28
44
RAMo
Qo
RAM3
Q]
31
40
31
32
-
-
-
-
-
25
35
35
26
32
48
37
28
40
40
29
26
29
-
-
-
-
40
35
40
28
33
30
-
-
-
-
Set-Up and Hold Times Relative to Clock (CP) Input[3,10,l1]
CP:
Set-UpTime
BeforeH. L
Hold Time
AfterH.L
15
0
(Note 12)
A, B Source Address
B Destination Address
15
D
-
Cn
1012
1345
1678
10
RAMo, 3, QO,3
-
•
•
Output Enable/Disable Times[2]
Output disable tests performed with CL = 5 pF and measured to
0.5V change of output voltage level.
Device
CY7C901-31
CY7C901-32
Input
em
em
-,-
~
Output
Enable
Disable
Y
23
23
Y
25
25
6-47
~-
Set-UpTime
BeforeL.H
30,15 + t5f'
(Note 13
Do Not Change
-
25
Hold Time
AfterL. H
0
0
0
0
20
30
0
30
0
Do Not Change
-
•
"f-
12
•
0
0
-
•
~
fil~~
CY7C901
Minimum Cycle Time Calculations for 16-Bit Systems
Speed used in calculations for parts other than CY7C901 are representative for MSI parts.
.--------1 CN
13, l'
A,B,I,C n
CY7C901
(1)
Cn + x
Cn +y
Cn + z
WIRED "OR" F~O FROM
OTHER CY7C901s
FROM
CY7C901 (2, 3)
•••
•••
Pipelined System, Add without Simultaneous Shift
CY7C245
CY7C901
Carry Logic
CY7C901
Register
Data Loop
Clock to Output
A,BtoG,P
Go, Po to + z
to Worst Case
Set-Up
en
en
CY7C245
12
MUX
28
9
CY7C901
18
CY7C245
4
7I ns
Minimum Clock Period = 71 ns
Control Loop
Clock to Output
Select to Output
CCtoOutput
Access Time
7C901-7
12
12
22
20
66 ns
FROM
7C901 (2,3)
•••
•• •
•• •
Pipelined System, Simultaneous Add and Shift Down (RIGHT)
CY7C245
CY7C901
Carry Logic
CY7C901
XORand MUX
CY7C901
Data Loop
Clock to Output
A, B to G, I'
Go, Po to Cn + Z
to Worst Case
Prop. Delay, Select to
Output
RAM3Setup
en
12
28
9
18
20
CY7C245
MUX
CY7C901
CY7C245
Control Loop
Clock to Output
Select to Output
CC to Output
Access Time
7C901-8
12
12
22
20
66 ns
9
%ns
Minimum Clock Period
6-48
=% ns
~
:~
_'=
-=-_' CYPRESS
ar
CY7C901
SEMlcalDucroR
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs_ SUPPLY VOLTAGE
1.2 r - - - , - - - - , - - . - - - - - - ,
1.4
Jl1.0
Jl1.2
o
ow
W
N
~
a:
~
O.6 1---+--7'9---+----1
1.0
~
z
0.4 '----'-----'----'------'
4.0
4.5
5.0
5.5
6.0
0.6
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
.s
60
!zw
50
~
40
I
'"""
a:
U
a:
o
~
~ 30
~ ........
Vee=~
VIN =5.0V
0.0
-55
25
a:
:::l
125
5l
20
':i
1=
10
5
~
0
0.0
1.0
AMBIENTTEMPERATURE (OC)
SUPPLY VOLTAGE (V)
Vcc=5.0V TA = 25°C
2.0
""
3.0
4.0
OUTPUT VOLTAGE (V)
•
o
NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE
NO~ZEDFREQUENCY
vs. SUPPLY VOLTAGE
(;
Z
w 1.2
:::l
CJ 1.1
w
a:
u.
0
w
1.0
N
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.6
1.3
V
::J 0.9
4:
:2
a:
0 0.6
(;
--
aJ
fE
1.2
o
...............
w
o
TA = 25°C
5.0
5.5
[50.6
6.0
1.6
w 1.5
I-
:::l
0
./
1.4
/
1.3
w
::J 1.2
4:
:2
a: 1.1
0
z
1.0
o
/
60
1/
::.:
~ 60
':i
1=
5
125
40
20
oI
V
200
---
/
/
Vee = 5.0V
TA = 25°C
I
1.0
0.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
-
"
1.0
V
.2
0
w 0.9
N
::J
4:
:::;:
a: 0.6
0
z
400
........
NO~ZEDIcc vs. FREQUENCY
V
I
'"
/
1.1
1/
0
N
100
AMBIENTTEMPERATURE (OC)
0
:::l
U
25
NORMALIZED OUTPUT DELAY
vs. OUTPUT LOADING
D..
I-
a:
:::l
Vcc=5.0V
0.6
-55
SUPPLY VOLTAGE (V)
~
z
~
--
z
4.5
140
I-
1.4
r· '"
~
z
0.7
4.0
~
.s 120
:::l
(3
Vee = 5.0V
TA=25°C
I
I
600 600 1000
0.7
1/
0.0
o
5
V
10
/
V
Vee=5.0V
VIN = OVOR3V
TA = 25°C
1
15
20
25
30
35
7C901-9
CAPACITANCE (pF)
FREQUENCY (MHz)
6-49
9
CY7C901
.ordering Information
Read·
Modify·
Write Cycle
(ns)
23
27
31
32
Package
Ordering Code
'J.Ype
CY7C901-23DC
CY7C901-23JC
CY7C901-23LC
CY7C901-23PC
CY7C901-27DMB
CY7C901- 27LMB
CY7C901-31DC
CY7C901-31JC
CY7C901-31LC
CY7C901-31PC
CY7C901-32DMB
CY7C901-32LMB
018
J67
J..1j7
Operating
Range
Commercial
P17
D18
J..1j7
Military
D18
J67
J..1j7
P17
D18
J..1j7
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Combinational Propagation Delays
Parameters
Subgroups
VOH
VOL
Vrn
Vn.,Max.
1,2,3
1,2,3
IJX
Ioz
Isc
Icc
Icc1
Parameters
FromA, B Address to Y
From A, B Address to F3
From A, B Address to Cn + 4
From A, B Address to G, P
From A, B Address to F = 0
From A, B Address to OVR
From A, B Address to RAMo, 3
FroinDtoY
FromDto F3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
FromDtoCn + 4
FromDtoG,P
FromDtoF=O
FromDto OVR
Cycle Time and Clock Characteristics
Parameters
MinimumOock LOW Time
Minimum Clock HIGH Time
Subgroups
7,8,9, 10, 11
7,8,9, 10, 11
From D to RAMo, 3
FromCntoY
FromCn toF3
FromCn toCn + 4
FromCntoF = 0
From Cn to OVR
From Cn to RAMo, 3
From 1012 to Y
From 1012 to F3
From 1012 to Cn + 4
From 1012 to 0, P
From 1012 to F = 0
From 1012 to OVR
From 1012 to RAMo 3
6-50
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10,11
-=r
.
~~NDUcroR
CY7C901
Combinational Propagation Delays (continued)
Pammeters
Set-Up and Hold Times Relative to 'Clock (Cl») Input
Subgroups
From 1345 to Y
Pammeters
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
From 1345 to F3
en
From 1345 to
+4
From 1345 to G, P
7,8,9,10,11
°
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10, 11
From 1345 to F =
From 1345 to OVR
From 1345 to RAMo, 3
From 1678 to Y
7, 8, 9, 10, 11
7,8,9,10, 11
From 1678 to RAMo, 3
Subgroups
A, B Source Address
Set-UpTime Before H. L
7,8,9,10,11
A, B Source Address
Hold Time After H. L
7,8,9,10,11
A, B Source Address
Set-UpTimeBeforeL.H
A, B Source Address
Hold Time After L. H
7, 8, 9, 10, 11
B Destination Address
Set-Up Time Before H. L
7, 8, 9; 10, 11
7,8,9,10,11
From 1678 to 00, 3
From A Bypass ALU to Y (I = 2XX)
From Clock LOW to HIGH to Y
7,8,9, 10, 11
B Destination Address
Hold Time After H. L
7, 8, 9, 10, 11
7,8,9, 10, 1.1
7, 8, 9, 10, 11
B Destination Address
Set-UpTimeBeforeL. H
7, 8, 9, 10, 11
From ClockWW to HIGH to F3
7,8,9,10, 11
7,8,9,10, 11
7,8,9,10,11
B Destination Address
Hold Time After L. H
7,8,9,10, il
From Clock WW to HIGH to Cn + 4
FromClockWWtoHIGHtoG,P
D Set-Up Time BeforeL. H
7, 8, 9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
°
From Clock LOW to HIGH to F =
From ClockWW to HIGH to OVR
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From Clock WW to HIGH to RAMo, 3
From Clock LOW to HIGH to 00 3
7,8,9, 10, 11
D Hold Time After L. H
Set-Up Time Before L. H
Hold Time After L. H
en
en
7, 8, 9, 10, 11
1012 Set-Up Time Before L. H
1012 Hold Time After L. H
1345 Set-Up Time Before L. H
1345 Hold Time After L. H
1678 Set-Up Time Before H. L
1678 Hold Time After H. L
1678 Set-Up Time Before L. H
1678 Hold Time After L. H
RAMo, RAM3, 00, 03
Set-Up Time Before L. H
RAMo, RAM3, 00, 03
Hold Time After L. H
Document #: 38-00021-B
6-51
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
•
o
ao
....I
CY7C909
CY7C911
CYPRESS
SEMICONDUCTOR
Features
• Fast
- CY7C909/11 has a 30-ns (min.)
c1ock-to-ontpnt cycle time (commercial and military)
• Lowpower
-Icc (max.) = 55 rnA (commercial
and military)
• Vee margin
-sv ±10%
- All parameters gnaranteed over
commercial and military operating
temperature range
• Infinitely expandable in 4-bit increments
CMOS Micro Program
Sequencers
• Capable of withstanding >2001V static discharge voltage
• Pin compatible and fnnctionally
equivalent to Am2909A/Am2911A
Functional Description
The CY7C909 and CY7C911 are highspeed, four-bit-wide address sequencers
intended to control the sequence of execution of micro-instructions contained in microprogram memory. They may be connected in parallel to expand the address
width in 4-bit increments. Both devices are
implementedin high-performance CMOS
for optimum speed and power.
The CY7C909 can select an address from
any of four sources. They are: (1) a set of
four external direct inputs (Dj); (2) exter-
Logic Block Diagram
R (7C909 ONLy)
nal data stored in an internal register (Ri);
(3) a four-word-deep push/pop stack; or
(4) a program counter register (which usually contains the last address plus one). The
push/pop stack includes control lines so
that it can efficiently execute nested subroutine linkages. In the CY7C909, each of
the four outputs (Yi) can be ORed with an
external input for conditional skip or
branch instructions. A ZERO input line
forces the outputs to all zeros. The outputs
are three-state, controlled by the output
enable (OE) input.
The CY7C911 is an identical circuit to the
CY7C909, except the four OR inputs are
removed and the D and R inputs are tied
together. The CY7C911 is available in a
20-pin, 300-mil package.
Pin Configurations
PUSH/POP
DIP
ThpView
DIP
ThpView
liE
vee
CP
R3
R,
R,
CP
PUP
vee
liE
FE
Ro
OR3
OANOR
CONNECTED
ON7C911
ONLY
.(4
o
03
Co
0,
DE
Y,
Y,
Yo
OR,
CLOCK
en +4
0,
Y3
Do
Y,
GNO
Y,
Y3
0,
ORo
DIRECT
INPUTS
FE
en +4
Co
DE
03
OR,
0,
PUP
5,
Do
GNO
So
ZERO
ZERO
Yo
So
5,
C909-3
C909~2
PLCC/LCC
ThpView
PLCCILCC
Top View
4 3 2,-1, 28272~5
Ro
OR3
03
OR,
0,
OR
0,
OE
FE
24
Cn +4
21
20
Y3
Y2
11121314151617113
Y1
7C909
10
~~ ~
C909-4
Cn + 4
C909~1
6-52
03
4
0,
0,
5
8
7
8
Do
GNO
3 2,1,2019
18
17
7eg11
18
15
14
910111213
CY7C909
CY7C911
~
~=CYPRESS
~, SEMICONDUCIDR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Thmperaturewith
Power Applied . . . . . . . . . .. . . . . . . . . . . .. - 55°C to + 125°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Output Current, into Outputs (LOW) ............... 30 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
Operating Range
Range
Commercial
Militaryll]
Ambient
Thmperature
O°Cto + 70°C
Vee
5V±1O%
- 55°C to +125°C
5V±1O%
Electrical Characteristics Over the Operating Rangel2]
VOH
Parameters
Description
Output HIGH Voltage
Vex; = Min., IOH = - 2.6 rnA
Commercial
Vex; = Min., IOH = - 1.0 rnA
Military
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA
Vrn
Input HIGH Voltage
2.0
VlL
Input LOW Voltage
IJX
Input Load Current
Ioz
los
Output LeakageCurrent
Output Short Circuit Current[3]
lee
Vex; Operating Supply Current
leCl
Thst Conditions
Vex; Operating Supply Current
Min.
2.4
Max.
Units
V
204
V
0.4
V
V
-2.0
Vee
0.8
GND.5. VI.5. Vee
GND .5. Vo.5. Vee, Output Disabled
-10
+10
-20
Vee = Max., VOUT = GNDorVee
Commercial
Vee = Max., lOUT = 0 rnA
-30
+20
-85
!lA
!lA
rnA
55
rnA
Vee = Max.
Vrn? 3.0V; VlL.5. OAV
Military
55
Commercial
35
Military
35
V
rnA
Capacitance[4]
Description
InputCapacitance
uutputcapacltance
Parameters
CIN
LoUT
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testiug information.
AC Test Loads and Waveforms
OUTP~~31
I
INCLUDING _
JIGAND SCOPE
(a)
4.
5V31
I _
Units
pF
pF
Not more thao 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
'Jested initially and after any design or process changes that may affect
these parameters.
R1
R1
50pF
3.
Max.
5
7
OUTPUT
5pF
R2
_
-
R2
INCLUDING
JIG AND SCOPE
(b)
Commercial
-
C909-6
Military
R1
2540
2580
R2
1870
2160
6-53
ALL INPUT PULSES
t
10%
--I
$5n5
C909-7
•
o
c;
9
CY7C909
CY7C911
~
~~PRfSS
~, SEMlCamuCfOR
Switching Characteristics Over the Operating Range!2, 51
CY7C909-30, CY7C911-30
CY7C909-40, CY7C911-40
Commercial
Military
Commercial
Military
Units
Minimum Clock LOW Time!61
15
15
20
20
ns
Minimum ClockIDGHTime[61
15
15
20
20
ns
MAXIMUM COMBINATORIALPROPAGATION DElAYS
Y
Co +4
Y
Co+4
Y
Co+4
Y
Cu+4
ns
Dj
17
18
18
19
17
22
20
25
ns
SO,S1
18
18
20
20
29
34
29
34
ns
ORj (CY7C909)
16
16
17
17
17
22
20
25
ns
Co
-
13
-
15
-
14
-
16
ns
ZERO
18
18
20
20
29
34
30
35
ns
DE LOW to Output
16
18
-
25
25
16
18
-
25
-
25
-
ns
DE HIGH to High Z[51
-
-
= l1f
Clock HIGH, S1> So = LL
ClockIDGH,Sl So, = HL
20
20
22
22
39
44
45
50
ns
20
20
22
22
39
44
45
50
ns
20
20
22
22
44
49
53
58
ns
From Input To:
Clock HIGH, S1> So
ns
MINlMUM SET·UPAND HOLD TIMES (All Times Relative to ClockLOW-to-IDGHTransition)
Set.Up
Hold
Set-Up
Hold
Set.Up
Hold
Set-Up
Hold
RE
11
0
12
0
19
0
19
0
ns
RP1
10
0
11
0
10
0
12
0
ns
Push/Pop
12
0
13
0
25
0
27
0
ns
FE
12
0
13
0
25
0
27
0
ns
Co
10
0
11
0
18
0
18
0
ns
Dj
14
0
16
0
25
0
25
0
ns
ORj (CY7C909)
12
0
14
0
25
0
25
0
ns
SO,S1
14
0
16
0
25
0
29
0
ns
ZERO
12
0
13
0
25
0
29
0
ns
From Input
Notes:
5. Output loading as in part (b) of AC Thst Loads and Waveforms.
6. System clock cycle time (Clock WW Time and Clock HIGH TIme)
cannot be less thanmaximum propagation delay.
7.
Rj and Dj are internally connected on the CY7C911. Use Rj set-up and
hold times for Dj inputs.
Switching Waveforms
MIN CLOCK LOW
MIN CLOCK HIGH
CLOCK
INPUT
(EXCEPTOE)
I
OUTPUT
(Y, Cn +4)
INPUT TO
OUTPUT~
CLOCK TO OUTPUT
===XXXXXXXXXXX_~.-_-_-_-_-_-_-_-_-_-_C909-8
6-54
CY7C909
CY7C911
<:.~
•
- CYPRESS
. , SEMICONDU(''TOR
Functional Description (continued)
The tables below define tbe controllogic oftbe 7C909/911. Table 1
contains the multiplexer control logic, which selects tbe address
source to appear on the outputs.
Table 3 illustrates the output control logic oftbe 7C909/911. The
ZERO control forces the outputs to zero. The OR inputs are
ORed with the output of tbe multiplexer.
Thble 1. Address Source Selection
Thble 3. Output Control
Octal
SI
So
Source for Y Outputs
0
L
L
1
2
L
H
H
H
L
H
Microprogram Counter (IAPC)
Address/HoldingRegister(AR)
Push-Pop Stack (STK)
Direct inputs (Di)
[I;J
Control of tbe Push/Pop Stack is contained in Table 2. File enable
(FE) enables stack operations, while Push/Pop (PUP) controls the
stack.
Thble 2. Synchronous Stack Control
FE
PUP
Push-Pop Stack Change
H
L
X
H
L
L
No change
Push current PC into stack, increment stack
pointer
Pop stack, decrement stack pointer
O~
ZERO
OE
Yi
X
X
H
HighZ
X
L
L
L
H
H
L
H
L
H
L
Source selected by So Sl
Table 4 defines the effect of So, S10 FE, and PUP controlsignals on
the 7C909. It illustrates the address source on the outputs and the
contents of tbe internal registers for every combination of tbese
signals. The internal register contents are illustrated before and afterthe c10ck LOW-to-HIGH edge.
o
c:;
9
Thble 4. Output Control
Cycle
SI, So, FE, PUP
N
N+1
0000
N
0001
N+1
-
N
N+1
001X
N
N+ 1
0100
N
N+1
0101
N
N+1
011X
N
N+ 1
1000
N
N+1
1001
N
N+ 1
10 IX
N
N+ 1
1100
N
N+1
1101
N
N+1
ll1X
-
-
-
"PC
J
J+1
REG
STKO STKl
K
K
Ra
Rb
Rb
Rc
•
STK2
STKJ YOUT
Rc
Rd
Rd
Ra
J
Comment
Principle
Use
Pop Stack
End Loop
PushlAPC
Set-Up
-
J
K
Ra
Rb
Rc
Rd
J
J+1
K
J
Ra
Rb
Rc
-
J
J+1
K
K
Ra
Ra
Rb
Rb
Rc
Rc
Rd
Rd
J
-
J
K+1
K
K
Ra
Rb
Rb
Rc
Rc
Rd
Rd
Ra
J
K+1
K
K
Ra
J
Rb
Ra
Rc
Rb
Rd
Rc
J
K+1
K
K
Ra
Ra
Rb
Rb
Rc
Rc
Rd
Rd
K
Jump to Address inAR
JMPAR
-
J
Ra+ 1
K
K
Ra
Rb
Rb
Rc
Rc
Rd
Rd
Ra
Ra
Jump to Address in STKO;
Pop Stack
RTS
-
J
Ra+ 1
K
K
Ra
J
Rb
Ra
Rc
Rb
Rd
Rc
Ra
Jump to Address in STKO;
-
J
Ra+ 1
K
K
Ra
Ra
Rb
Rb
Rc
Rc
Rd
Rd
Ra
Push "PC
Jump to Address in STKO
J
D+1
K
K
Ra
Rb
Rb
Rc
Rc
Rd
Rd
Ra
Jump to Address on D;
Pop Stack
End Loop
-
J
D+1
K
K
Ra
J
Rb
Ra
Rc
Rb
Rd
Rc
D
Jump to Address on D;
JSRD
-
Push "PC
J
D+1
K
K
Ra
Ra
Rb
Rb
Rc
Rc
Rd
Rd
D
Jump to Address on D
-
Loop
Continue
Continue
Use AR for Address;
Pop Stack
End Loop
K
Jump to Address in AR;
JSRAR
-
Push "PC
K
D
J = Contents of microprogram counter; K = Contents of address register; Ra, Rb, Re, Rd = Contents in stack
6-55
Stack Ref
(Loop)
JMPD
CY7C909
CY7C911
Functional Description (continued)
Two examples of subroutine execution appear below. Thb1e 5 illustrates a single subroutine while Thbles 6 illustrates two nested subroutines. The starting address of the subroutine is applied to the D
inputs of the 7C909 at the appropriate time, and the instruction to
be performed is applied to the 80.10 m, and PUP inputs. 1Jpically,
these signals are derived from a micro-instruction, register, and the
output of the seqw:ncer. (Y;) ~t is the address in the control
ROM of the next Jnlcro-IDstruction to be executed.
Thbles 5 shows the sequence of micro-instructions to be executed.
At address J + 2, the sequence control portion of the microinstruction contains the command "Jump to subroutine at A" At
the time T:z, the 7C909 inputs are set up to execute the jump and
save the return address. The subroutine address A is applied to the
D inputs and appears on the Y outputs. On the next clock transition, the return address J + 3 is pushed onto the stack. The return
instruction is executed at Ts. Thbles 6 has a similar timing chart
showing one subroutine linking to a second, with the latter consisting of only one micro-instruction.
Table S. Subroutine Execution!8]
Execute Cycle
To
Tl
T2
T3
T4
Ts
T,
T7
Clock
L
L
L
L
L
L
L
L
S~So
0
H
X
X
0
H
X
X
3
L
H
A
0
H
X
X
0
H
X
X
2
L
L
X
0
H
X
X
0
H
X
X
J+1
J+2
J+3
--
-
-
A+3
J+3
-
--
A+2
J+3
J+5
--
A+1
J+3
J+4
-J+1
J+2
A
A+1
A+2
J+3
J+4
J+5
Continue
Continue
JSRA
Continue
Continue
RTS
Continue
Continue
-
Signals
Inputs
PUP
D
tfio
STKl
Internal
Registers
-
STK2
STK3
Output
Y
Instruction being
executed
-
-
--
-
-
--
Table 6. Two Nested Subroutines, Routine B is Only One Instruction!8]
Execute Cycle
To
Tl
Tl
T3
T4
Ts
T,
T7
Ts
T,
Clock
L
L
L
L
L
L
L
L
L
L
Si!J!So
0
H
X
X
3
L
H
A
0
H
X
X
0
H
X
X
3
L
H
B
0
H
X
X
2
L
L
X
0
H
X
X
2
L
L
X
0
H
X
X
J+2
J+2
A+1
J+2
A+2
J+2
A+3
J+2
B+1
A+3
J+2
A+4
J+2
J+3
-
-
--
A+5
J+2
-
B +1
A+3
J+2
STK2
STK3
---
Y
J+1
A
B
B+1
A+3
A+4
J+3
J+4
Continue
JSRA
JSRB
Continue
RTS
Continue
RTS
Continue
-
Signals
Inputs
(from
f.lWR)
Internal
Registers
Output
Instruction
being
executed
PUP
D
tfio
STKl
-
---
--
A+1
--
A+2
Continue Continue
Note:
8. Cn=ffiGH
6-56
--
-
--
!J
.
Jl~
"'8."
.9
!
L ~ pop
0-
~
~
§
Ro
0-
o
Jl
.go
R,
fY
R2
fY
I
FE
R3l(
S~
:>0--......- - - - - - - - ,
I
ENA:~:::P:~~:)
v
lWO-SIT
B
\;l
UP/DOWN COUNTER
~D
~
iI
"
fY
H~PUSH
puP >---~H
-bD
0
D
-bD
0
D
~D
0
'b
0
CP
,
Oo~OO
cr
,
O
~
(0
RE
t"'
s:::
~"
rl
a
~
rl
:
Q
~
I
<.A
-..J
0
CLOCK
n
:1
S,
n_
'"
~
So
~
l
~
f
~
t"
ZERO
--{>o-j)
~
--v
D
1_
CP[~
~
[~[2:......
[2:......
~~
~
'
~
So
~ .1·
~
Do
OR;~ 11
U
OR~1 U
U
Y\Y~r yY.Y~r
l~
~
~~l
-v--v
D.lf--I/~,w,,'N.!,WJ
f-- I/; -:- -:- -
~
D:3
0,
D,
OR2~il OR3~li
::::
r- Y3 ~
+--------+-1 y 2 ~
F3
13
-
[
OJ
-
~-
4X4MATRIXOF
1--1/0 MEMORY CELLS
:I ~ -~~~
f--I/;
_ce~;~~~"II~
- : -
D.lo,OJ'b
r---
F2
+--------+-------~--1Y1 ~ F1r---------~
OE
~
~
Yo
~
Y,
~
Y2
~ YO~nFO
Y3
Cn
II
Q~
",::$
II~~
~
I
'"
LOGIC.
CY7C909
CY7C911
Functional Description (continued)
Archilecttlre
The CY7C909 and CY7C911 are CMOS microprogtam sequencers for use in high-speed processor applications. They are cascad~ble. in 4-bit 4terjllllCnts. 'l\vo devices can address 2S6 words of
microprogram. three can address up to 4K words. and so on. The
architecture of the CY7C9091!l1l is illustrated in the logic diagram inF1gUI'I11. The various blocks are descn"bed below.
Multiplexer
The multiplexer is controlled by the So and S1 inputs to select the
address source; It selects either the direct inputs (D;). the address
register (AR). the microprogram counter (!'PC). or the stack
(SP) as the source of the next micro-instroction address.
Direct Inputs
The direct inpUtS (D;) allow addresses from an I".xtemal Source to
be output on the Y outputs. On the CY7C911. the direct inputs
are also inputs to the address register.
Address Register
The address register (AR) consists of four D~type. edge:!!!&.gered, flip-flops that are controlled by the register enable (RE)
input. When register enable is LOW, new data is entered into the
register on the LOW-to-IllGH clock transition.
Microprogram Counter
The mierop1"l;lgram counter (!'PC) is composed of a 4-bit inerementer fotrowed by a 4-bit register. The incrementer has a carry
in (Cn)input and a carry out (c" + 4) output to facilitate cascading. The carry in input controls the microprogram counter. When
canyin is HIGH the inerementercounts sequentially. The counter register is loaded with the current Y output plus one (Y + 1 •
!'PC) on the next clock cycle. When cany in is LOW the inerementer does not count. The mieroprogram counter register is
loaded with the same Y output (Y • !,PC) on the next clock cycle.
Stack
The Stack consists of a 4 x 4 memory array and a built-in stack
pointer (SP). which always points to the last word written. The
stack is used to store return addresses when executing mierosubroutines..
The stack pointer is an up/down counter controlled by file enable
(FE) and 1'1!sh/Pop (PUP) inputs. The fde enable input allows
stack.9PCf8lions only when it is LOW. The Push/Pop input controls the stack pointer position.
.
The: PUSH operation is initiated at the beginning of a mierosubroutine. Push/Pilp is setlllGH while file. enable is kept LOW.
The stack pointer is incremented and the memory array is written
with the miero-instruction address following t1ie subroutine jump
that initiated the push.
The POP operation is initiated at the end of a microsubroutine to
obtain the return addreSs. Both Push/Pop and file enable are set
LOW. The return address is already available to the multiplexer.
The stack pointer is deeremented on the next LOW-to-IllGH
clock transition, effectively removing old information from the
top ofthe stack. The stack is configured so that data will roll-over
ifmore than four POPS are performed, thus preventing data from
being lost.
The contents of the memory position pointed to by the stack
pointer is always available to the multiplexer. Stack reference operations can thus be performed without a push or a pop. Since
the stack is four words deep. up to four microsubroutines can be
nested.
The Z'BRU input resets the four Y outputs to a binary zero state.
The OR inputs (7C909 only) are connected to the Y outputs such
that any output can be set to a logical one.
The output enable (Un) input controls the Y outputs. A HIGH
on output enable sets the outputs into a high -impedance state.
Definition of Terms
Name
Description
INPUTS
S1,So
Multiplexer Control Unes for Access Source Selection
FE
File Enable, Bnables Stack Operation, Active LOW.
PUP
Push/PoP. Selects Stack Operation
RB
Register Enable, Enables Address Register Active LOW
ZERO
Forces Output to Logical Zero. Active LOW
OB
Output Bnable. Controls Three-State Outputs Active LOW
ORi
Logic Or Iilput to each Address Output Line (7C909 only)
Cn
Carry In. Controls Microprogram Counter
Ri
Iilputs to the Iiltemal Address Register (7C909 only)
Di
CP
Oocklilput
Direct Inputs to the Multiplexer
OUTPUTS
Yi
I
Address Outputs
Cn+4
I
Cany Out from Incrementer
6-58
CY7C909
CY7C911
~
~~PRF.SS
~_? SEMICONDUCTOR
Definition of Terms (continued)
Description
Name
INTERNALSIGNALS
!!PC
Contents of the Microprogram Counter
AR
Contents of the Address Register
STKO-STK3
Contents of the Push/Pop Stack
SP
Contents of the Stack Pointer
EXTERNAL SIGNAL
A
Address to the Counter Memory
1YPical DC and AC Characteristics
NO~EDSUPPLYCURRENT
NORMUUAZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.2 F::"::"::"::'="'-''''::':::r-:'':':'''-,--,
1.4
Jl 1.0 t---+--r--~«---l
Jll.2
1 60
•
OUTPUf SOURCE CURRENT
vs.OUTPUfVOLTAGE
I-
c
I:!l
:::;
~
C
O.SI---+-~+---+--';
a:
~
1.0
a:
~
~
0.4 L-_...L_---J'--_....l...._---I
4.0
4.5
5.5
6.0
O.S
N
125
cw
~ 1.0
0.9
TA = 25°G
!§
z
0.7
4.0
5.0
SUPPLY VOLTAGE (V)
6
0
0.0
1.0
O.S
6.0
-55
~
2.0
o
-I
.~
4.0
3.0
OUTPUT VOLTAGE (V)
. /~
z
----
ll!a:
100
o
SO
:::l
:..:
~ 60
5
Vcc= 5.0V
40
/"
1/
I
/
o5 20
Vcc= 5.0V
TA = 25°C
oV
0.6
5.5
10
I-
z
4.5
5~
~
.s 120
1.4
fiI
IE 1.2 ~ ............
.---
::!:
a:
0 O.S
~
2001 V
(Per MIL-STD-883 Method 3015)
Range
Commercial
Militaryll]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±1O%
- 55°C to + 125°C
5V±1O%
Note:
1. TA is the "instant on" case temperature.
6-63
9
-===-.
$i~PR£SS
-= iF
CY7C910
SEMICONDUCTOR
Pin Definitions
Signal
Name
DO - D11
Signal
Name
Description
I/O
I/O
CI
Carry input to the LSB of the incrementer
fortheMPC.
Register load. Control input to RC that,
when LOW, loads data on the Do - D11 pins
into RC on the LOW-to-HIGH clock (CP)
transition.
OE
Control for Yo - Y 11 outputs. LOW to enable; HIGH to disable.
Yo - Y11
a
Address output to microprogram memory.
Yo is LSB and Yu isMSB.
FULL
a
When LOW indicates the stack is full.
PL
a
When LOW, this indicates the pipeline register has been selected as the direct input (Do
- D11) source.
Enable for CC input. When HIGH CC is ignored and a pass is forced. When LOW the
state of CC is examined.
MAP
a
When Law, this indicates the mapping
PROM (or PLA) has been selected as the
direct input (Do- D11) source.
Clock input. All internal states are changed
on the LOW-to-HIGH clock transitions.
VECf
a
When Law, this indicates the Interrupt Vector has been selected as the direct input (Do
- D11) source.
Instruction inputs that select one of sixteen
instructions to be performed by the
CY7C91O.
Control input that, when Law, signifies that
a test has passed.
CP
Description
Direct inputs to the RC (Register/Counter)
and multiplexer. Do is LSB and D11 is MSB
Architecture of the CY7C910
Introduction
The CY7C91O is a high-performance CMOS microprogram controller that produces a sequence of 12-bit addresses that control
the execution of a microprogram. The addresses are selected from
one of four sources, depending upon the (internal) instruction being executed (To - 13), and other external inputs. The sources are
(1) the external (Do - D11) inputs, (2) the RC, (3) the stack, and
(4) the MPC. Twelve bit lines from each of these four sources are
the inputs to a multiplexer as shown in the Logic Block Diagram.
The outputs of the multiplexer are applied to the inputs of the
three-stateoutput drivers (Yo - Y 11)'
External Inputs: Do - Dll
Theexternal inputs are used as the source fordestination addresses
for the jump or branch type of instructions. These are shown as Ds
in the two columns in the Thble of Instructions. A second use of
these inputs is to load the RC.
Register Counter: RC
The RC is implemented as twelve D-type, edge-triggered flip-flops
that are synchronously clocked on the LOW-to-HIGH transition
of the clock, CP. The data on the D inputs is synchronously loaded
into the RCwhen the load control input, RLD, is Law. The output of the RC is available to the multiplexer as its R input and is
output on the Y outputs during certain instructions, indicated with
an R in the Table ofInstructions.
The RC is operated as a 12-bit down counter. Its contents are decremented and tested to see if they are zero during instructions 8,
9, and 15. This enables micro-instructions to be repeated up to
4096 times. The RC is arranged such that if it is loaded with a number, n, the sequence will be executed exactly n + 1 times.
The Stack and Stack Pointer: SP
The 17-word by 12-bit stack is used to provide return addresses
from micro-subroutines or from loops. The Sp, which points to the
last word written, is integral to the operation ofthe stack. This per-
mits reference to the data on the top ofthe stack without having to
perform a Pop operation.
The SP operates as an up/down counter that is incremented when
a Push operation (instructions 1, 4, or 5) is performed or decrementedwhen a Pop operation (instructions 8,10,11,13, or 15) is performed. The Push operation writes the return address on the stack
and the Pop operation effectively removes it. The actual operation
occurs on the LOW-to-HIGH clock transition following the instruction.
The stack is initialized by executing instruction zero (JUMP TO
LOCATION 0 or RESET). Every time a "jump to subroutine" instruction (1, 5) or a loop instruction (4) is executed, the return address is Pushed onto the stack; and every time a "return from subroutine (or loop)" instruction is executed, the return address is
Popped off the stack.
When one subroutine calls another or a loop occurs within a loop
(or a combination), which is called nesting, the logical depth of the
stack increases. T~sical stack depth is 17 words. When this
depth occurs, the FULL signal goes LOW on the next LOW-toHIGH clock transition. Any further Push operations on a full stack
will cause the data at that location to be overwritten, but will not
increment the SP. Similarly, performing a Pop operation on a
empty stack will not decrement the SP and may result in non-meaningfuldata being available at the Y outputs.
The Microprocessor Counter: MPC
The MPC consists of a 12-bit incrementer followed by a 12-bit register. The register usually holds the address ofthe instruction being
fetched. When sequential instructions are fetched, the carry input
(CI)to the incrementeris HIGH and one is added to the Youtputs
of the multiplexer, which is loaded into the MPC on the next LOWto-HIGH clock transition. When the CI input is Law, the Y outputs of the multiplexer are loaded directly into the MPC so that the
same instruction is fetched and executed.
6-64
~~"'---CYPRESS
~.
~
CY7C910
SEMlCONDUCTOR
Electrical Characteristics Over Commercial and Military Operating Range, Vee Min. = 4.5V, Vee Max. = 5.5V[2]
Parameters
Description
Thst Conditions
VOH
VOL
VIH
Output HIGH Voltage
VIL
IIH
IlL
Input LOW Voltage
Input HIGH Current
Input LOW Current
IOH
Output HIGH Current
IOL
Output LOW Current
Output Leakage Current
Output Short Circuit Current[3]
Output LOW Voltage
Input HIGH Voltage
loz
Min.
Max.
Units
0.4
V
V
Vcc
0.8
V
V
10
-10
fAA
fAA
2.4
Vee = Min., IOH = - 1.6 rnA
Vee = Min., IOL = 12 rnA
2.0
- 3.0
Vee = Max., VIN = Vee
Vee = Max., VIN = Vss
Vee = Min., VIH = 2.4V
-1.6
12
-40
Vcc = Min., VOL = O.4V
Ise
Icc
Supply Current
Vee = Max., VOUT = VssJVee
Vcc = Max., VOUT = OV
Vee = Max.
Icc!
Supply Current
VIH ~ 3.85Y, VIL5 O.4V
Commercial
Military
rnA
rnA
fAA
+40
- 85
rnA
rnA
70
90
35
Commercial
Military
rnA
50
o
a
Capacitance [4]
Parameters
qN
Description
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
r--1
CL
8
10
Switching Wavefonns
+5V
J
Units
pF
_pF
Max.
TA = 25°C, f = 1 MHz,
Vee=5.0V
Output Loads for AC Perfonnance Characteristics[5,6]
VOUT
•
INPt~~
----------.J. .
...
-~----
J'~1.5~V:-
w---------'I'--------J"I'-HOLD
TIME
3.0V
CLOCK
34OQ
255Q
1.5V
OV
1------<+ 1~~Jil
DELAY
7C9l0-4
OUTPUTS
All Outputs
1.5V
7C91D-5
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Notmore than one ontpnt should be shorted at a time. Duration of the
short circuit should not be more than one second.
4.
5.
6.
6-65
Thsted initially and after any design or process changes that may affect
these parameters.
CL = 50 pF includes scope probe, wiring, and stray capacitance.
CL = 5 pF for output disable tests.
9
CY7C910
Guaranteed AC Performance Characteristics
Th!l tables below specify the guaranteed AC performance of the
CY7C910 over the commercial (0° C to +70°C) and the military
( - 55°C to + 125 ° C) temperature ranges with V cc varying from
4.5V to 5.5Y. All times are in nanoseconds and are measured between the 1.5V siguallevels.
Theinputs switch between OV and 3V with signal transition rates of
1 volt per nanosecond. All outputs have maximum DC current
loads.
Clock Requirements [2]
Commercial
Military
Speed (ns)
40
50
93
46
51
99
Minimum Clock LOW
20
20
50
23
25
58
Minimum Clock HIGH
20
20
35
23
25
42
Minimum Clock Period 1 = 14
40
50
93
46
51
100
Minimum Clock Period 1 = 8,9, 15
40
50
113
46
51
114
Combinatorial Propagation Delays
(CL = 50 pF)[2, 7]
Commercial
Military
Y
Speed (ns)
40 50 93
40
50
93
40
Do -: Du
!u..:- 13
CC
CCEN
17
25
22
22
20
35
30
30
20
50
30
30
-
30
-
-
-
CP 1 = 8, 9, 15[8]
30 40
75
-
CP All Other 1
QE!8]
30
40 55
-
21
21
25
27
-
PI, VECT, MAP
20
-
35
30
Minimum Set-Up and Hold Times
y
FULL
From Input
50
93
46 51
99
46
51
99
46
51
99
21 25
30 40
27 36
27 36
25
54
35
37
-
-
-
-
-
-
-
77
-
-
-
30
35
-
30
35
67
-
-
-
-
-
- - - - - - -
-
25
31
60
35
46
-
-
25
31
60
35
46
61
-
- - -
22 25
22 30
40
30
-
51
-
25
50
58
-
-
-
67
Military
Commercial
40
35
Relative to c10ck LOW-to-HIGH 'Itansition(CL = 50pF)[2]
Set-Up
Speed (ns)
FULL
PI, Vf.:CT, MAP
Bold
Set-Up
93
40
50
93
46
51
Bold
99
46
51
99
0
DItRC
13
16
24
0
0
0
13
16
28
0
0
DItMPC
20
30
58
0
0
0
20
30
62
0
0
0
10 - 13
25
35
75
0
0
0
27
38
81
0
0
0
CC
20
24
63
0
0
0
25
35
65
0
0
0
CCEN
20
24
63
0
0
0
25
35
63
0
0
0
CI
15
18
46
0
0
0
15
18
58
0
0
0
RLD
15
19
36
0
0
0
15
20
42
0
0
0
Notes:
7. Adash indicates that a propagation delay path or set-up time does not
exist.
8. The enable/disable times are measured toaO.5 Volt change on the output voltage level with CL = 5 pF.
6-66
~;~PRFSS
CY7C910
~, SEMICONDUC'TOR
Thble of Instructions
Result
Io
Reg/Cntr
Contents
Fail
CCEN = L and CC = H
Pass
CCEN = HorCC =L
Y
Stack
Y
Stack
0
JZ
Jump Zero
X
0
Clear
0
Clear
Hold
PL
1
CJS
CondJSBPL
X
PC
Hold
D
Push
Hold
PL
13 -
Mnemonic
Name
Reg!Cntr Enable
2
JMAP
Jump Map
X
D
Hold
D
Hold
Hold
Map
3
CJP
CondJumpPL
X
PC
Hold
D
Hold
lIold
PL
4
Push
PushiCond LD CNTR
X
PC
Push
PC
Push
(Note 9)
PL
5
JSPR
Cond JSB R/PL
X
R
Push
D
Push
Hold
PL
6
CJV
Cond Jump Vector
X
PC
Hold
D
Hold
Hold
Vect
7
JRP
8
RFCT
X
R
Hold
D
Hold
Hold
PL
Repeat Loop,
CNTR#O
Cond Jump R/PL
#0
F
Hold
F
Hold
Dec
PL
=0
PC
Pop
PC
Pop
Hold
PL
Dec
PL
9
RPCT
RepeatPL,
CNTR#O
#0
D
Hold
D
Hold
=0
PC
Hold
PC
Hold
Hold
PL
10
CRfN
CondRTN
X
PC
Hold
F
Pop
Hold
PL
11
CJPP
Cond Jump PL & Pop
X
PC
Hold
D
Pop
Hold
PL
1·";
12
LDCT
LD Cntr & Continue
X
PC
Hold
PC
Hold
Load
i>L
13
LOOP
Thst End Loop
X
F
Hold
PC
Pop
Hold
PL
14
CaNT
Continue
X
PC
Hold
PC
Hold
Hold
PL
15
TWB
#0
F
Hold
PC
Pop
Dec
FL
=0
D
Pop
PC
Pop
Hold
PL
Three-Wiy Branch
H=IDGH
L=LOW
X = Don't Care
Notes:
9. If CCEN = Land CC = H, then hold; else load.
6-67
•
o
§
CY7C910
:t4
CY7C910 Flow Diagrams
o Jump Zero (JZ)
1 Cond JSB PL (CJS)
8
69
70
66
67
58
69
67
58
®
20
66
67
58
36
f
21
30
31
9 Repeat PL, CNTR -=I 0 (RPCl)
~(PUSH)
®
RESISTER!
COUNTER
10 Cond Return (CRTN)
:~®COUNTER
65 .
J6a)
STACK
66~~
67
58
30
~~~'~~
~33
35
69
70
11 Cond Jump PL & POP (CJPP)
34
12 LD CNTR & Continue (LOCl)
36
...--® ~:j~~
37
66~
:r®COUNTER
67
f
40
:(f~r+~--20--l-" ~~ t :~
70
71
~
40
41
42
43
44
Q., STACK
69
70
65
~
~
~~®STACK
30~0
31
71
32
72
33
34
5
8 Repeat Loop, CNTR oF 0 (RFCl)
. '-,
65
RESISTER{
COUNTER
7 Cond Jump R!PL (JRP)
~h35
'.'
65
66
25
26
:
5 Cond JSB R!PL (JSRP)
65k@)STACK
6 Cond Jump Vector (CJV)
69
66
67
58
4 Push{Cond LD CNTR (PUSH)
65h
65~
STACK
40
41
42
43
67
68
3 Cond Jump PL (CJP)
2 Jump Map (JMAP)
21
22
14 Continue (CONl)
32
T
13 Test End Loop (LOOP)
67
58
15 Three-Way Branch (TWB)
:
®
~\ 67
STACK
(PUSH)
67~
65
66
65!
67
58
66
67
68
69
~
STACK
67
(PUSH)
N
REGISTER!
COUNTER
72
73
68
69
70
71~
72
7C91 0-6
6-68
~
~-CYPRESS
~_,
CY7C910
SEMICONDUCTOR
One-Level Pipeline-Based Architecture (recommended)
MAP
rl3
~
CC
r---
CLOCK
CY7C91 0
I
Y
A+1
MICROPROGRAM
MEMORY
CY7C245
REGISTERED PROM
I(A+1)
PIPELINE
REGISTER
I
•
----I
o
I(A)
f--
c:;
CY7C901
ALU
o
~
!
~
SeA)
PIPELINE
REGISTER
I
S(A-1)
7C91G-7
•
72-ns CYCLE TIME
CLOCK
(CLOCK TO REGISTER OUTPUT)
.-+--------------------+-
PIPELINE
CY7C910 ------.-..,....,.....,......
REGISTER. INSTRUCTION
OUTPUT
INPUT
-----~~~~~--------------------+I-----<_+_ 18 ns (MUX SELECT TO OUTPUT)
MUX
CY7C91 0
OUTPUT· CC INPUT _ _ _ _ _..J..Ox_K..l~~...K....K..+_-----------------+(CCTOy)
CY7C91 0
OUTPUT _ _ _ _ _'_Jj;~~"_J/~..liL...~'_Jj;~~"_J/~~~'_+-------_+(PROM ADDRESS SET-UP TIME)
1----
20ns
MICROPROGRAM ------------~~~~~~~~~~~~~~~~~~~~~~~--
MEMORY
OUTPUT _ _ _ _ _ _ _..J..~~~~...K.~~~~~...K.~~~~...K....K..Ox_K..l~~...K.~~_
7C91D-8
6-69
'.;:rlPRESS
CY7C910
~; SEMlCONDUCfOR
lYpicai DC and AC Characteristics
NO~EDSUPPLYCURRENT
NO~EDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.2 r------,----.---r-----,
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
1.4
60
I
I-
J:l
J:l
1.0
c
~
:::i
~
o
II:
Z
0
Z
0.4'--_--1._ _...J...._ _.l-_--'
4.0
4.5
5.0
5.5
6.0
0.8
NO~ZEDFREQUENCY
vs. AMBIENT TEMPERATURE
1.3
15
15::>
fE
~,...
1.2
C
TA=25°C
0.9
II:
~ 0.8
0
0.0
1.0
~
1.0
g5
0.8
5.5
'"
3.0
Z
""
~ 100
II:
~
r--
B
80
tj
60
/
I-
40
::>
[3o
25
20
"...
--
Vcc =5.0V
TA = 25°C
oV
125
I
1.0
0.0
2.0
3.0
OUTPUT VOLTAGE (V)
NO~EDOUTPUTDELAY
NO~ZED
vs. OUTPUT WADING
~
1.6
~ 1.5
~ 1.4
a.
~
/'
/
01.3
~:::i
~
g5
I"
Z
1.0
1
o
200
1.0
cw
0.9
II:
0.8
/'
~
..:
:;
. . .V
0
Z
/
1.1
0
.2
/
1.2
400
Vee=5.0V
TA = 25°C
0.7
I
0.0
600
Icc vs. FREQUENCY
1.1
-
/'
I
800 1000
/
o
5
:/
10
V
15
Vee =5.5V
V1N = OV OR 3V
TA = 25°C
20
25
30
35
7C910-9
CAPACITANCE (pF)
FREQUENCY (MHz)
6-70
4.0
/
/
AMBIENTTEMPERATURE (0G)
SUPPLY VOLTAGE (V)
V'
/
~
Vee = 5.0V
0.6
-55
6.0
2.0
~ 140
Z
5.0
10
;:- 120
1.4
@
4.5
~
"'-
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
1.2
::>
Ow 1.1
0.7
4.0
20
OUTPUT VOLTAGE (V)
1.6
~
~
...... ~
AMBIENTTEMPERATURE (0G)
NO~ZEDFREQUENCY
C 1.0
,/'
w
6en
6
0.0 ' - - - - - - - ' ' - ' ' ' ' - - - - - - - '
-55
125
vs. SUPPLY VOLTAGE
N
~
I-
SUPPLY VOLTAGE (V)
fE
40
w
~ 30
1.0
II:
0.6h"c:....-t---
gj
Vee=5.0V TA = 25°C
()
w
~
..:
:;
50
II:
1.2
C
0.81----+--7'<+---+-----1
15
4.0
e?7,~~NDUcroR
CY7C910
Ordering Information
Clock Cycle
(ns)
40
46
50
51
93
99
Ordering Code
CY7C910-40DC
CY7C91O-40JC
CY7C91O-40LC
CY7C91O-40PC
CY7C91O-46DMB
CY7C910-46LMB
CY7C91O-50DC
CY7C91O-50JC
CY7C910-50LC
CY7C91O-50PC
CY7C91O-51DMB
CY7C91O-51LMB
CY7C91O-93DC
CY7C91O-93JC
CY7C91O-93LC
CY7C910-93PC
CY7C91O-99DMB
CY7C910-99LMB
Package
'Jype
Operating
Range
D18
J67
L67
P17
D18
L67
D18
Commercial
J67
L67
P17
D18
L67
D18
J67
L67
P17
D18
L67
Military
Commercial
Military
Commercial
Military
6-71
•
~
~-CYPRESS
~_"
CY7C9l0
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Minimum Set-Up and Hold Times
Parameters
Subgroups
VOH
VOL
VIH
VILMax.
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IIH
IlL
IOH
IOL
Ioz
Isc
Icc
IcCl
Parameters
DI.RCSet-UpTime
DI. RC Hold Time
DI. MPC Set-Up Time
DI. MPC Hold Time
10 - 13 Set-Up Time
10 - 13 Hold Time
CC Set-Up Time
CCHoidTime
CCEN Set-Up Time
CCENHold Time
CI Set-Up Time
CIHoldTime
RLD Set-Up Tune
RLO Hold Time
Clock Requirements
Parameters
MinimumClock LOW
Subgroups
7,8,9,10,11
Combinational Propagation Delays
Parameters
From 00 - 011 to Y
From 10 - 13 to Y
From 10 - 13 to PL, VECf, MAP
FromCCtoY
FromCCEN to Y
From CP (I = 8, 9, 15) to FULL
From CP (All Other I) to Y
From CP (All Other I) to FULL
Subgroups
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
Oocument#: 38-00016-B
6-72
Subgroups
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
CY7C9101
CYPRESS
SEMICONDUCTOR
Features
• Fast
- CY7C9l0l-30 bas a 30·ns (maL)
dockcyde (commercial)
- CY7C9l0l-35 bas a 35·ns (max.)
dock cycle (military)
• Lowpower
- Icc (max. at 10 MHz) 60 mA
(commercial)
- Icc (max. at 10 MHz) 85 mA
(military)
• Vee margin oC 5V :tlO%
• All parameters guaranteed over
commercial and military operating
temperature range
• Replaces Cour 200ts witb carry look·
abeadlogic
• Eight·Conction ALU performs tbree
aritbmetic and five logical operations
on two l6.bit operands
=
=
CMOS 16-Bit Slice
• lnfinitely ekpanclable In lel·bit incre·
ments
• Four status Clags: carry, overflow, neg·
ative, zero
• Capable ohrltbstaDding greater tban
200lV static discharge voltage
• Pin compatible aDd Cunctional equiva.
lent to AM29ClOl
Functional Description
The CY7C9101 is a high-speed, expandable, 16-bit-wide ALU slice that can be
used to implement the arithmetic section
of a CPU, peripheral controller, or programmable controller. The instruction set
of the CY7C9101 is basic, yet so versatile
that it can emulate the ALU of almost any
digital computer.
The CY7C9101, as shown in the logic
block diagram, consists of a 16-word by
16-bit dual-port RAM register file, a 16-bit
Logic Block Diagram
ALU, and the necessary data manipulation and control logic.
The Cunction performed is determined by
9-bit instruction word (Is to 10), which is
usually input via a micro-instruction register.
The CY7C9101 is expandable in 16-bit
increments, has three-state data ontputs
as well as flag outputs, and can implement
either a full look-ahead carry or a ripple
carry.
The CY7C9101 is a pin-compatible, functional equivalent for the Am29CIOl with
improved performance. The 7C9101 replaces four 29018 and includes on-chip
carry look-ahead logic.
Fabricated in an advanced 1.2-micron
CMOS process, the CY7C9101 eliminates latch-up, has ESD protection greater than 2000Y, and achieves superior performance with low power dissipation.
Pin Configuration
lbpView
Ia
a,.
RAM,.
As
~
RAM,.
Co
A (READ)
ADDRESS
B (REAllJWAlTE)
ADDRESS
°15_0
(DIRIiCT
DATA-IN)
F,.
v,.
v,.
v,.
V'2
v l1
v,o
V.
v.
GND
tlE
v,
V.
v.
V.
V.
v.
v,
Vo
'"
"0
D,.
D,.
D,.
D'2
D"
D,o
D.
De
Vee
Dr
D.
D.
D.
Os
D.
0,
D.
So
F=D
c..
I.
I,
10
Ie
I,
7C8101-1
7C81D1-2
V15-0
DATA OUT
6-73
•
o
s
9
~PR£SS
~~CONDUCfOR
CY7C9101
Pin Configuration (continued)
PGA
Top View
51
50
V.
V,
53
F=O
52
49
v.
55
V.
48
V.
47
V5
48
45
NC
43
vs.
V7
42
44
DE
v.
41
vss
40
v.
38
V,.
36
V,.
37
35
V,.
34
V,.
32
F,.
33
V,.
39
Vo
V"
54
cn
"
56
57
30
10
59
'7
61
O.
Co+1
"
28
58
'.
'.
60
65
67
So
68
D.
•
29
P
G
27
26
"
83
62
CP
RAM.
e,.
31
oV~
"
25
24
0,.
'3
23
22
64
B3
1.0
66
B,
A,
RAM15
21
20
33
0,
03
D.
34
D.
36
D.
38
D.
35
37
39
Dr
40
Vee
41
NC
43
D.
44
42
Vee
Do
45
47
1.0
19
18
0,. 0,. 0,.
48
48
0" 0,. 0,.
Ae
17
7 C9101-3
LCC/PLCC
Top View
9 8 7 6
NC
0,.
0,.
0,.
0"
0,.
Os
D.
13
14
15
16
17
Vee
18
Dr
19
20
21
D.
D.
D.
5 4 3 2 1 68 6766 65 64 83 62 61
10
11
12
60
59
58
57
56
Y14
Y13
V12
Y11
Y10
55
Vo
54
53
52
51
Va
GND
GND
V7
V.
V5
DE
22
50
49
48
03
23
47
Y4
D.
24
0,
25
48
45
V3
Y2
D.
26
44
V,
2726~30~3233343536~38394O~.43
7C9101-4
Selection Guide
Minimum Clock Cycle (ns)
Commercial
Military
CY7C9101-30
CY7C9101-35
30
35
Maximum Operating Current
at 10 MHz (mA)
Commercial
Military
60
85
6-74
CY7C9101-40
CY7C9101-45
40
45
60
85
=--~
=-===liE CYPRESS
CY7C9101
_ , SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
Storage Temperature .................. -65°Cto+150°C
Ambient Thmperaturewith
PowerApplied ........................ -55°Cto+125°C
Supply Voltage to Ground Potential. . . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to + 7.0V
DCInputVoltage ....................... - 3.0Vto +7.0V
Output Current into Outputs (LOW) ................ 30 rnA
Static Discharge Voltage. . . .. . . . .. . . . . . .. . .. .. . . . >2001V
(Per MIL-STD-883 Method 3015)
Latch-UpCurrent(Outputs) .................... >200rnA
Operating Range
Range
Commercial
Militaryll]
Ambient
Thmperature
O°Cto +70°C
Vee
5V±10%
- 55°C to +l25°C
5V±10%
Notes:
TA is the "instant on" case temperature.
1.
Pin Definitions
Signal
Name
I/O
A3-Ao
Ig - 10
Instruction Word. This 9-bit word is decoded to
determine the ALU data sources (10, 1, 2), the
ALU operation (13, 4, 5), and the data to be written to the Q register or register file (I6, 7, g).
CP
Q15
RAM15
Qo
RAMo
Direct Data Input. This 16-bit data word may
be selected by the 10, 1, 2lines as an input to
theALU.
D15-00
OE
Q15
RAM15
(cont.)
RAM Address B. This 4-bit address word selects one of the 16 registers in the register file
for output on the (internal) B port. When data
is written back to the register file, this is the
destinationaddress.
B3 - Bo
Y15- YO
Signal
Name
Description
RAM Address A. This 4-bit address word selects one of the 16 registers in the register file
for output on the (internal) A port.
0
Data Output. These are three-state data output lines that, when enabled, output either the
output of the ALU or the data in the A latch,
as determined by the code on the 16, 7, glines.
Output Enable. This is an active LOW input
that controls the Y 15 - Yo outputs. A HIGH
level on this signal places the output drivers at
thehigh-impedancestate.
Clock. The LOW level of CP is used to write
data to the RAM register file. A HIGH level
of CPwrites data from the dual-port RAM to
the A and B latches. The operation ofthe Q
register is similar; data is entered into the master latch on the LOW level of CP and transferred from master to slave during CP =
HIGH.
I/O These two lines are bidirectional and are controlled by 16, 7, g. They are three-state output
drivers connected to the TTL-compatible
CMOS inputs.
6-75
Description
I/O
I/O Output Mode: When the destination code on
lines 16,7, g indicates a left shift (UP) operation, the three-state outputs are enabled and
the MSB of the Q register is output on the Q15
pin and likewise, the MSB of the ALU output
(F15) is output on the RAM15 pin.
Input Mode: When the destination code indicates a right shift (DOWN), the pins are the
data inputs to the MSB of the Q register and
the MSB of the RAM,respectively.
I/O These two lines are bidirectional and function
similarly to the Q15 and RAMl5lines. The Qo
and RAMo lines are the LSB of the Q register
and the RAM.
en
I
Carry In. The carry in to the internal ALU.
en + 16
0
Carry Out. The carry out from the internal
ALU.
G,P
0
Carry Generate, Carry Propagate. Outputs
from the ALU that may be used to perforin a
carry look-allead operation over the 16 bits of
theALU.
OVR
0
Overflow. This signal is the logical exclusiveOR of the carry in and the carry out of the
MSB of the ALU. This indicates when the result of the ALU operation has exceeded the
capacity of the ALU's two's complementnumberrange.
F=O
0
Zero Detect. Open drain output that goes
HIGH when the data on outputs (FIS - Fo) are
all LOW. It indicates that the result of an ALU
operation is zero (positive logic assumed).
F15
0
Sign. The MSB of theALU output.
•
~
0
0
..J
~
.
_
·~PRESS
F
CY7C9101
SEMICONDUCTOR
Description of Architecture
General Description
TheCY7C9101 general block diagram is shown on the first page of
this datasheet, in the Logic Block Diagram section. Detailed block
diagrams (Figures 1 through 3) show the operation of specific sections as described below. The device is a 16-bit slice consisting of a
register file (16-word by 16-bit dual-port RAM), the AID, the Q
register, and the necessary control logic. It is expandable in 16-bit
increments.
Register File
The dual-port RAM is addressed by two 4-bit address fields (A3 Bo) that cause the data to simultaneously appear at the A
or B (internal) ports. If the A and B addresses are the same, the
data at the A and B ports will be identical.
Data to be written to RAM is applied totheD inputs of the 7C9101
andis passed (unchanged) through the ALU to the RAM location
Ao, B3 -
specifiedbythe B-addressword. New data iswritten into the RAM
by specifying a B address while RAM write enable (RAM EN) is
active and the clock input is LOW. RAM EN is an internal signal
decoded from the signals 16, 7, 8. As shown in Figure 1, each of the
16 RAM inputs is driven by a three-input multiplexer that allows
theALU output (F15 - Fo) to be shifted one bit position to the left
or right, or not shifted at all. The RAM15 and RAMo I/O pins are
also inputs to the 16-bit, 3-input multiplexer.
Duringthe left-shift (upshift) operation, the RAM15 output buffer
and RAMo input multiplexer are enabled. For the right-shift
(downshift)operation, the RAMo output buffer and the RAM15
input multiplexer are enabled.
TheA and B outputs of the RAM drive separate 16-bitlatches that
are enabled when the clock is HIGH. The outputs ofthe A latch go
to the three multiplexers that feed the two ALU inputs (R 15 - Ro
and S15 - So) and the chip output (Y 15 - YO). The B latch outputs
are directed to the multiplexer that feeds the S input to the ALU.
RAMo
Ie
17
0
: RAM SHIFTER
o (16 x 3-IN MUX)
•••
16
•••
02
01
DO
Sa
B:!
B1
WE
Bo
}
BAOORESS
7C9101-5
Figure 1. Register File
6-76
CY7C9101
Description of Architecture (continued)
QRegister
The a register is, mainly intended for use as a separate working
register for multiplication and division routines. It may also function as an accumulator or temporary storage register. Sixteen
master-slave latches are used to implement the a register. As
shown in Figure 2, the a-register inputs are driven by the outputs
of the a shifter (sixteen 3-input multiplexers, under the control
of 4 1 8). The function of the a register input multiplexers is to
allow the a register to be shifted either left or right, or loaded
with the ALU output (PIS - Fo). The alS and 00 pins (110)
function similarly to the RAMIS and RAMo pins described earlier. Data is entered into the master latches when the clock is
LOW and is transferred to the slave (output) at the clock LOWto-HIGH transition.
ALU (Arithmetic Logic Unit)
The ALU can perform three arithmetic and five logical operations on the two 16-bit input operands, R and S. The R input
multiplexer selects between data from the RAM A port and data
at the external data input, DIS - Do- The S input multiplexer selects between data from the RAM A port, the RAM B port, and
the a register. The R and S multiplexers are controlled by the 10,
1 2 inputs as shown in Thble 1. The Rand S input multiplexers
e'ach have an "inhibit capability," offering a state where no data is
passed This is equivalent to a source operand consisting of all
zeros. The R and S ALU source multiplexers are configured to
allow eight pairs of combinations of A, B, D, a, and "0" to be
selected as ALU input operands.
The AW input functions, which are controlled by 13, 4, S, are
shown in Thbk 2. Carry look-mead logic is resident on the
7C9101, us~ the ALU carry in (c,,) input and the ALU carry
propagate (P), carry generate (0), carry out (c" + 16), and overflow outputs to implementcarrylook-ahead arithmetic and dete.rmine if arithmetic overflow has occurred Note that the carry In
(c,,) signal affects the arithmetic result and internal flags only; it
has no effect on the logical operations.
Control signals 4 1 8 route the ALU data output (PIS - Fo) to
the RAM, the a reSister inputs, and the Y outputs as shown in
Thbk 3. The ALU result MSB (PIS) is output so the user may examine the sign bit without needing to enable the three-state outputs. The F = 0 output, used for zero detection, is mOH when
all bits of the F output are LOW. It is an open drain output that
may be wire ORed across multiple 7C9101 processor s1ices. Figure 3 shows a block diagram of the ALU.
The ALU source operands and ALU function matrix are summarized in Thbk 4 and separated by logic operation or arithmetic
operation in Thbles 5 and 6, respectively. The Io. 1. 2 lines select
eight pairs of source operands and the 13. 4, S lines select the operation to be performed.
•••
Figure 2. Q Register
6-77
7C8101-6
•
o
a
o
....I
1ir,:~NDU~R
CY7C9101
Description of Architecture (continued)
Conventional Addition and Pass-IncrementlDecrement
Subtraction
When the carry in is HIGH and either a conventional addition or a
PASS operation is performed, one (1) is added to the result. If the
DECREMENT operation is performed when the carry in is LOW,
the value of the operand is reduced by one. However, when the
same operation is performed when the carry in is HIGH, itnullifies
the DECREMENT operation so that the result is equivalent to the
PASS operation. In logical operations, the carry in (Cn) will not affect the ALU output.
Recall that in two's complement integer coding - 1 is equal to all
ones, and that in one's complement integer coding zero is equal to
all ones. To convert a positive integer to itstwo'scomplement(negative) equivalent, invert ( complement) the number and add 1 to it;
i.e., TWC = ONC + 1. In Table 6 the symbol - 0 represents the
two's complement of 0, so the one's complement of 0 is then - 0
Thble 1. ALU Source Operand Control
Thble 2. ALU Function Control
12
11
Io
AO
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
AB
ZO
ZB
ZA
DA
DO
DZ
MicroCode
AWSource
Operands
MicroCode
Mnemonic
-1.
Octal
Code
0
1
2
3
4
5
6
7
R
S
A
A
a
a
a
D
D
D
0
B
0
B
A
A
0
a
Mnemonic
Is
4
13
ADD
SUBR
SUBS
OR
AND
NOTRS
XOR
XNOR
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Octal
Code
0
1
2
3
4
5
6
7
ALU
Function
Symbol
RPlusS
SMinusR
RMinusS
RORS
RANDS
RANDS
RXORS
RXNORS
R+S
S-R
R-S
RVS
R 1\ S
R 1\ S
R¥S
R¥S
Thble 3. ALU Destination Control
RAM Function
MicroCode
RAM Shifter
Q-Reg. Function
QShifter
y
Mnemonic
Is
16
Shift
Load
Shift
Load
Output
RAMo
RAMIS
Qo
Q15
OREG
L
17
L
Octal
Code
L
0
X
None
None
F
X
X
X
X
Nap
L
L
H
1
X
None
X
HO
None
F
X
X
X
X
RAMA
L
H
L
2
None
F.B
X
None
A
X
X
X
X
RAMF
L
H
H
3
None
F.B
X
None
F
X
X
X
X
RAMOD
H
L
L
4
DOWN
F/2.B
DOWN
Q/2.0
F
Fo
IN15
00
IN15
RAMD
H
L
H
5
DOWN
F/2.B
X
None
F
Fo
IN15
00
X
RAMOU
H
H
L
6
UP
2F.B
UP
20.0
F
INo
F15
INo
015
RAMU
H
H
H
7
UP
2F.B
X
None
F
INo
F15
X
015
..IS a TIL mput mtemally connected to a three-state output that IS m the high-unpedance state.
x = Don't care. Electrically, the mput shift pm
A = Register addressed by A inputs.
B = Register addressed by B inputs.
UP is toward MSB, DOWN is toward LSB.
6-78
~~
~ii!lCYPRESS
CY7C9101
~, SEMJCONDUC'TOR
Description of Architecture (continued)
•••
• ••
Do
, . . - - + _ - - - - + - - + _ - - - - - - 015
, . . - - - - _ f _ - - + - - - - - - 014
AI5-1~~--+_----_f_--~~~--~+_-~r_---_+-_,
•
•
•
AI4-.~-+_-_1-----+__.-+_+---~-_1+---~
Al
•
•
•
-f-rt-_;---+~~---r_;__;-+_--_f_;__,
Ao~+-+-t-_+~t--t_+_--_+_+____t-t_-~
Rl
Ro
SIS
S14
16-BIT ARITHMETIC LOGIC UNIT (ALU)
...
• • •
SI
FO
o
g
..J
14----1
ALU
DESTINATION
DECODE
7C9101-7
•••
Yo
Figure 3. ALU
Thble 4. Source Operand and ALU Function Matrix
1210 Octal
ALUSource
Octal
1543 ALU Function
0
Cn=L
RplusS
Cn=H
1
Cn=L
SminusR
Cn=H
2
3
Cn=L
RminusS
Cn=H
RORS
4
RANDS
5
RANDS
6
REX·ORS
7
REX-NORS
+ = Plus; -
0
1
A
2
3
4
0
0
6
7
D
Q
B
Q
0
B
A
5
D
A
A+Q
A+B
Q
B
A
D+A
A+Q+l
Q-A-l
A+B+l
B-A-l
Q+ 1
Q-l
B+l
B-1
A+l
A-I
Q-A
A-Q-l
B-A
A-B-l
Q
- Q-l
B
-B-1
A
-A-l
A-D
D-A-l
Q-D
D-Q-l
-D
D-l
A-Q
AVQ
AAQ
AAQ
A¥Q
A¥Q
A-B
AVB
AAB
AAB
A¥B
A¥B
-Q
Q
-B
B
-A
A
D-A
DVA
DAA
DAA
D¥A
D¥A
D-Q
DVQ
DIIQ
DIIQ
D¥Q
D¥Q
D
D
A
0
0
0
Q
Q
Q
B
B
B
A
A
A
= Minus; V = OR; 1\ = AND; ¥ = EX-OR
6-79
D
Q
0
D+Q
D
D+A+ 1 D+Q+ 1
A-D-l Q-D-l
D+l
-D-l
0
0
D
D
CY7C9101
Description of Architecture (continued)
Thble 5. ALU Logic Mode Functions
Thble 6. ALU Arithmetic Mode Functions
Octal
1543,1210
Group
40
41
45
46
30
31
35
36
AND
AIIQ
AIIB
DIIA
DIIQ
OR
AVQ
AVB
DVA
DVQ
60
61
65
66
XOR
A¥Q
A¥B
D¥A
D¥Q
70
71
75
76
XNOR
A¥Q
A¥B
D¥A
D¥Q
72
INVERf
Q
73
74
77
62
63
64
67
Octal
Function
Is43,I210
B
PASS
A
D
Q
B
A
D
32
3.3
34
37
PASS
Q
B
A
D
42
43
44
47
"ZERO"
0
0
0
0
50
51
55
56
MASK
AIIQ
AIIB
DIIA
DIIQ
6-80
c,,=O(WW)
Group
Group
Function
A+Q
A+B
D+A
D+Q
Q
B
A
D
ADDpJus
one
A+Q+ 1
A+B+l
D+A+ 1
D+Q+ 1
Increment
Q+ 1
B+l
A+l
D+ 1
PASS
00
01
05
06
02
03
04
07
ADD
12
13
14
27
Decrement
Q-l
B-1
A-I
D-l
22
23
24
17
l'sComp.
- Q-l
-B-1
-A-1
- D-1
10
11
15
16
20
21
25
26
Subtract
PASS
Cn =l(mGH)
Function
2'sComp.
(Negate)
Q-A-l Subtract
(1'sComp.) B-A-l (2'sComp.)
A-D-l
Q-D-l
A-Q-1
A-B-1
D-A-1
D-Q-1
Q
B
A
D
-Q
-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
~
;~PRESS
.
CY7C9101
.F SEMlCONDUcroR
Electrical Characteristics
Over Commercial and Military Operating Rangd Z]
Vee Min. = 4.5V; Vee Max. = 5.5V
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 304 rnA
All Outputs Except F = 0
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
Vee = Min., IOL = 16 rnA
VIL
IJX
Input LOW Voltage
IOH
Input LeakageCurrent
Output HIGH Current
Vss ~ VIN ~ Vee, Vee = Max.
Vee = Min., VOH = 2AV
All Outputs Except F = 0
IOL
Ioz
Output LOW Current
Output LeakageCurrent
Vee = Min., VOL = OAV
Output Short Circuit Current[3]
Iec(Ql)[4]
Supply Current (Quiescent)
V
V
V
10
VSS~VIN~VILO~
VSS~VIN~0.4Vor_
OE=HIGH
iJA
rnA
rnA
+40
iJA
iJA
-85
rnA
Commercial
30
rnA
Military
35
rnA
Commercial
Military
Commercial
25
30
60
rnA
rnA
rnA
Military
85
rnA
-40
Ycc = Max., feLK = 10 MHz;
Supply Current
004
Vee
0.8
-304
VOUT = Vss to Vee
Vee = Max., VOUT = OV
All Outputs Except F = 0
3.85V ~ VIN ~ Vee; OE = HIGH
Iec(Max·14]
2.0
-3.0
-10
Units
V
16
VIH ~ VIN ~ Vee; OE = HIGH
Supply Current (Quiescent)
Max.
2.4
Vee = Max.
Ise
lee(Qz)[4]
Min.
Capacitance [5]
Parameters
Description
CIN
InputCapacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Units
8
pF
10
pF
Output Loads Used for AC Performance Characteristics[6,7]
1:
+5V
V=O
1~
7C9101·8
7C91 01-9
All Outputs Except Open Drain
Open Drain (F = 0)
Notes:
2. See the last page of this specification for Group A subgroup testing iuformation.
3. Not more than one output should be shorted at a time. Duration of the
short circuit should not be more than one second.
4. Two quiescent figures are given for different input voltage ranges. To
calculate Icc at any given frequency, use Iec(01) + Icc(AC) where
Icc(01) is shown above and Iec(AC) = (3 mA/MHz) X Clock Fre-
5.
6.
7.
6-81
quencyforthe commercial temperature. Icc(AC) = (SmNMHz) X
Clock Frequency for military temperature range.
Tested iuitially and after any design or process changes that may affect
these parameters.
CL = 50 pF iucludes scope probe, wiriug, and stray capacitance.
CL = 5 pF for output disable tests.
•
o
a
9
.
~
.
_
CY7C9101
CYPRESS
SEMICONDUCTOR
Thble 7. Logic Functions for CARRY and OVERFLOW Conditions
1543
Function
0
R+S
1
S-R
2
R-S
3
RVS
4
Ri\S
5
Ri\S
6
R¥S
7
R¥S
P
••
Po
G
GIS + PlSG14 + PlSP14G13 + ... + PI
PIS
Cn + 16
OVR
C16
C16 ¥ CIS
PISGO
Same as R + S equations, but substitute Ri for Ri in definitions
Same as R + S equations, but substitute Si for Si in definitions
HIGH
HIGH
Definitions (+ = OR)
Po - PIS = PlSPVJ)13P12PllPlOP9P8P7P6PSP~3P2PlPO
Po=Ro+So
PI = Rl + Sl
P2 = R2 + Sz
P3 = R3 + S3, etc.
WW
Go - GIS = GlSG14G13G12GllGlOG9G8G7G6GSG4G3G2GlGO
Go= RoSa
Gl = RlSl
G2= R2S2
G3 = R3S3, etc.
C16 = GIS + PlSG14 + PlSP14G13 + ... + Po - PlSCn
CIS = G14 + P14G13 + Pl~13G12 + ... + Po - P14Cn
CY7C9101-30 and CY7C9101-40 Guaranteed
Commercial Range AC Performance Characteristics
Cycle Time and Clock Characteristics
-30
CY7C9101
The tables below specifytbe guaranteed ACperformance of these
devicesoverthe commercial (0° C to 70° C)operatingtemperature
range with Vcc varying from 4.5V to 5.5V. All times are in nanoseconds and are measured between tbe 1.5V sigual levels. The inputs switch between OV and 3V with sigual transition rates of IV
pernanosecond.A1l outputs have maximum DC current loads. See
the Electrical Characteristics section for loading circuit information.
-40
Read-Modify-Wite Cycle (from selection
3008
40ns
of A, B registers to end of cycle)
Maximum Clock Frequency to shift Q
33 MHz 25 MHz
(50% duty cycle, 1 = 432 or 632)
This data applies to parts with the following numbers:
CY7C9101-30PC
CY7C9101-30DC
CY7C9101-30LC
CY7C9101-40PC
CY7C9101-40DC
CY7C9101-40LC
Combinatorial Propagation Delays (CL =
WW
••
Minimum Clock WWTime
Minimum Clock HIGH Time
20ns
IOns
25ns
15ns
Minimum Clock Period
30ns
40ns
CY7C9101-3OJC
CY7C9101-4OJC
CY7C9101-30GC
CY7C9101-40GC
50 pF)[8]
ThOutput
Y
F15
Cn + 16
G,P
F=O
OVR
RAMo
Qo
From Input
Y
F15
G,P
F=O
OVR
Q15
30
40
Speed (ns)
30
40
30
40
Cn + 16
30
40
30
40
30
40
30
40
RAM15
30
40
A,BAddress
37
47
36
47
35
44
32
41
35
46
32
42
32
40
-
D
29
34
28
34
25
32
25
30
29
36
21
26
27
33
-
-
-
Cn
22
27
22
27
20
25
-
-
22
26
22
26
24
30
1012
32
40
32
40
30
38
28
36
34
42
26
32
27
35
I34S
34
43
33
42
33
42
27
35
34
40
32
42
29
38
1678
A Bypass ALU (I - 2XX)
19
22
-
-
-
-
22
26
-
-
26
-
-
22
-
-
-
30
-
-
25
-
-
-
-
-
-
Clock (LOW to HIGH)
31
40
30
39
30
38
27
34
28
37
34
34
27
35
20
23
Note.
8. A dash indicates a propagation delay path or set-up time constraint
does not exist.
6-82
,
-
·-~PRESS
CY7C9101
.F SEMICONDUCTOR
Set-Up and Hold Times Relative to Clock (CP) Input[8]
~
CP:
Set-Up Time
BeforeH. L
Speed (ns)
30
40
A, B Source Address
10
15
B Destination Address
10
15
Data
-
13,4,5
-
-
16,7,8
10
12
RAMo, RAM15, Qo, Q15
-
-
en
10, h2
7'r
_.- 1 - Hold Time
AfterH. L
30
3lYj
•
40
3lYj
Set-Up Time
BeforeL.H
30
30lIUj
40
4()IlUj
Do Not Change lllj
•
Hold Time
Afted.H
30
40
0
0
0
0
0
0
-
-
22
28
16
22
0
0
-
26
35
0
0
-
-
37
0
0
0
0
0
0
29
Do Not Changelllj
•
-
-
11
•
14
Output EnableIDisable Times
Output disable tests performed with CL = 5 pF and measured to O.5V change of output voltage level.
Device
Input
Output
Enable
Disable
CY7C9101- 30
OE
Y
18
16
CY7C9101-40
OE
Y
22
19
Notes:
9. Source addresses must be stable prior to the clock HIGH-to-LOW
transition to allow time to access the source data before the latches
close. The A address may then be chaoged. The B address could be
chaoged if it is not a destination; i.e., if data is not being written back
into the RAM. Normally A aod B are not changed during the clock
LOW time.
10. Theset-uptimepriortotheclockLOW-to-HIGHtransitionistoallow
time for data to be accessed, passed through the ALU, aod returned to
•
o
a
9
the RAM. Itincludes all the time from stable Aaod B addresses to the
clock LOW-to-HIGH traosition, regardless ofwhen the clockIDGHto-LOW transition occurs.
11. Certain signals must be stable during the entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change."
6-83
CY7C9101
Cycle Time and Clock Characteristics(2)
CY7C9101-35 and CY7C9101-45 Guaranteed
Military Range AC Performance Characteristics
-45
-35
CY7C9101
The tables below specify the guaranteed AC performance of
these devices over the military (- 55°C to +125°C) operating
temperature range with Vccvarying from 4.5V to 5.5Y. All times
are in nanoseconds and are measured between the 1.5V signal
levels. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond All outputs have maximum DC
current loads. See the Electrical Characteristics section for loading circuit information.
This data applies to parts with the following numbers:
CY7C9101-35DMB CY7C9101-35LMB CY7C9101-35GMB
CY7C9101-45DMB CY7C9101-45LMB CY7C9101-45GMB
4508
Read-Modify-Write Cycle (from selection 35ns
of A, B registers to end of cycle)
28 MHz 22 MHz
Maximum Oock Frequency to shift Q
(50% duty cycle, 1 = 432 or 632)
23ns
28ns
Minimum Oock LOW Time
1208
Minimum Oock mGH Time
1708
35ns
4508
Minimum Oock Period
Combinatorial Propagation Delays (CL = 50 pF)[2, 8)
10 Output
y
From Input
Y
Speed (os)
A,BAddress
D
Cn
1012
1345
1678
A Bypass ALU (1 = 2XX)
Clock (LOW to mGH)
35
41
31
25
36
38
21
28
35
F1S
FIS
45
52
37
30
44
48
24
33
44
G,P
G,P
C.+16
C.+ 16
35
40
31
24
35
37
45
51
36
29
43
47
-
-
45
35
38
29
23
33
37
36
27
41
46
-
-
48
35
40
33
24
38
38
40
29
46
45
OVR
OVR
45
35
36
46
23
32
23
27
29
38
36
45
F=O
F=O
35
37
28
45
45
32
-
-
31
31
38
38
-
-
45
48
-
-
- - - -
-
-
-
34
43
34
34
40
28
.-
~-
42
30
37
35
36
30
26
30
33
24
45
43
35
31
38
41
28
24
28
-
-
-
-
-
38
30
37
21
25
-
-
Qo
Qu
RAMo
RAMlS
35
45
-
-
-
-
Set-Up and Hold Times Relative to Clock (CP) Input!2,8)
CP:
.3.,
Set.UpTIme
DeforeH. L
Speed (os)
35
45
A, B Source Address
12
17
B Destination Address
12
17
D
-
-
Cn
1012
-
-
1345
-
-
1678
12
16
RAMo, RAM15, Qo, Q15
-
-
Hold TIme
AfterH.L
35
3(9)
•-
•-
45
3(9)
7
Set.UpTIme
BeforeL. H
35
35(10)
Input
Output
Enable
0I3
Y
20
17
CY7C9101-45
em
Y
23
20
Disable
6-84
45
0
0
1
1
0
0
-
-
19
24
0
0
30
37
0
0
-
33
40
0
0
0
0
1
1
30
Do Not Changel ll )
-
13
Output disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.
Device
•
35
25
Output EnablelDisable Times(2)
CY7C9101-35
Hold TIme
AfterL. H
45
45(10)
Do Not Change[ll)
r
15
•
~
aP
_
4
CY7C9101
. . CYPRESS
....",..,.., SEMICONDUClDR
Applications
Minimum Cycle TIme Calculations for 16-Bit Systems
Speed used in calculations for parts other than CY7C9101 and CY7C91O are representative for available MSI parts.
A,B,t,Cn
F=O
C n +16
CY7C9l0l
OVR 1-":;'<-_--1
F'5
7C9l0l-l0
Pipelined System, Add Without Simultaneous Shift
CY7C245
CY7C901
Register
Data Loop
Clock to Output
A,BtoY,Cn + 16,OVR
Set-Up
12
37
4
53 ns
Control Loop
Clock to Output
Select to Output
CCtoOutput
Access Time
CY7C245
MUX
CY7C910
CY7C245
12
12
22
20
66 ns
Minimum Clock Period = 66ns
CV7C9101 F~O
F16
r-:RE:G:IS;:;TE:R:;-"i------.1 A, B, I, en
"'::==;:t====:.J
I-
OVA
7C9l0l-ll
Pipelined System, Simultaneous Add and Shift Down (Right)
CY7C245
CY7C9101
XORandMUX
CY7C9101
Data Loop
Clock to Output
A, B to Y, Cn + 16, OVR
Prop. Delay, Select to
Output
RAM15 Set-Up
12
37
20
CY7C245
MUX
CY7C91O
CY7C245
11
Control Loop
Clock to Output
Select to Output
CCtoOutput
Access Time
12
12
22
20
66 ns
80 ns
Minimum Clock Period = 80 ns
6-85
•
o
a
9
~
~-CYPRESS
~, SEMICONDUCIOR
CY7C9101
'IYPicaJ DC and AC Characteristics
NORMAUZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
1.4
.E
0
UJ
N
1.2
a:
0
0.8
V
0.6
4.0
:/
5.0
SUPPLY VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
::>
125
o
100
i}i
75
:.:
I-
::>
~
o
50
25
V'
/
100
o
80
i}i
60
1.2
~
O
---
::>
r--.
~
-55
25
1.6
1.5
/
::> 1.4
0-
I-
::>
0 1.3
/
«
::E
a:
0
z
1.1
1.0
o
[
200
is
20
125
-
V
0
0
UJ
!:l«
/
/
Vee=5.0V
TA = 25°C
oV
I
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
/
1.0
/
0.9
::E 0.8
a:
z
Vee=5.0V
TA = 25°C
0.7
I
0.0
600
./'" ~
/
0.0
.E
0
400
M
NORMAUZED Icc vs. FREQUENCY
V
/
4.0
1.1
/
0
UJ
1.2
40
",
/
AMBIENT TEMPERATURE (0C)
I-
~
::>
I!:
Vcc= 5.0V
TYPICAL OUTPUT DELAY
CHANGEvs. OUTPUT WADING
0
:.:
I-
z
M
3.0
z
~ 0.8
4.0
~
2.0
I-
0.6
3.0
OUTPUT VOLTAGE
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
a:
I
UJ
0
0.0
::>
r'
Vcc= 5.0V
TA = 25°C
2.0
is
.s 120
IE
.~
10
~
@
J
1.0
" ""-
C(' 140
~1.4
~
/
/
::>
01-
NORMAUZEDFREQUENCY
vs. AMBIENT TEMPERATURE
ow
oV
0.0
/'
20
OUTPUT VOLTAGE
1.6
Z
30
Vee=5.0V TA = 25°C
AMBIENT TEMPERATURE (0C)
C(' 175
I-
~
"-
I-
M
.s 150
40
g
Vee = 5.5V
VIN= 5.0V
0.8 '----_---''--_ _ _ _--'
-55
25
125
6.0
5.5
~
I
::>
z
I
4.5
50
o
i
f=10MHz
TA = 25°C
60
!z
UJ
a:
1.1 I - - - - . . . . . . , f - - - - - - - i
o
/
~
::E 1.0
z
15
/
0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
.s
C('
I
800 1000
CAPACITANCE (pF)
/
o
5
V
10
V
Vcc= 5.0V
TA= 25°C
VIN = OV or 3V
II
15 20 25 30
FREQUENCY (MHz)
6-86
35
7C9101-12
$nrlPRESS
~_"
CY7C9101
SEMICOlDUC"lDR
Ordering Information
Speed (ns)
Ordering Code
Package
'JYpe
Operating
Range
30
CY7C9101-30DC
CY7C9101-30GC
CY7C9101-30JC
CY7C9101- 30LC
CY7C9101-30PC
CY7C9101-35DMB
CY7C9101-35GMB
CY7C9101- 35LMB
CY7C9101-40DC
CY7C9101-40GC
CY7C9101-401C
CY7C9101-40LC
CY7C9101-40PC
CY7C9101-45DMB
CY7C9101-45GMB
CY7C9101-45LMB
D30
G68
181
LS1
P29
D30
G68
L81
D30
G68
J81
LS1
P29
030
G68
LS1
Commercial
35
40
45
Military
Commercial
II
o
Military
8....
6-87
CY7C9101
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Combinational Propagation Delays (continued)
Parameters
Subgroups
VOH
VOL
VIR
VILMax.
IJX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
loz
Isc
ICc(Ql)
Icc(Q2)
IcdMax.)
Parameters
From c" to F = 0
From c" to OVR
From c" to RAMo,15
From 10,1,2 to Y
From 10,1,2 to F15
From 10,1,2 to c" + 16
From 10,1,2 to G, P
From 10,1,2 to F = 0
From 10,1,2 to OVR
From 10,1,2 to RAMo,15
From 13,4,5 to Y
From 13,4,5 to F 15
From 13,4,5 to c" + 16
From 13,4,5 to G, P
From 13,4,5 to F - 0
From 13,4,5 to OVR
From 13,4,5 to RAMo,IS
From 16,7,8 to Y
From 16,7,8 to RAMo,IS
From 16,7,8 to QO,IS
From A Bypass ALU to Y (I = 2XX)
From Clock LOW to HIGH to Y
From Clock LOW to HIGH to F15
From Clock LOW to HIGH to c" + 16
From Clock LOW to HIGH to G, P
From Clock LOW to HIGH to F - 0
From Clock LOW to HIGH to OVR
From Clock LOW to HIGH to RAMo,IS
From Clock LOW to HIGH to Qo 15
Combinational Propagation Delays
Parameters
FromA, B Address to Y
From A, B Address to F15
From A, B Address to c" + 16
From A, BAddress to G, P
From A, B Address to F = 0
From A, B Address to OVR
From A, B Address to RAMo,15
FromDtoY
FromDtoF15
From D to Cn + 16
FromDtoG,P
FromDtoF=O
FromDtoOVR
From D to RAMo,15
Fromc"toY
From c" to F 15
From c" to c" + 16
Subgroups
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10,11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
6-88
Subgroups
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9,10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10, 11
7,8,9,10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
~~
~.CYPRESS
_
IF
CY7C9101
SEMICONDUC'TOR
Set-Up and Hold Times Relative to Clock (CP) Input
Parameters
Subgroups
A, B Source Address
Set-Up Time Before H. L
7,8,9, 10, 11
A, B Source Address
Hold Time After H • L
7,8,9,10,11
A, B Source Address
Set-UpTime Before
L.
7,8,9, 10, 11
H
A, B Source Address
Hold Time After L. H
7,8,9, 10, 11
B Destination Address
Set-Up Time Before H. L
7, 8, 9, 10, 11
B Destination Address
Hold Time After H. L
B Destination Address
Set-UpTime Before
H
7, 8, 9, 10, 11
B Destination Address
Hold Time After L. H
7,8,9,10,11
D Set-Up Time Before L. H
D Hold Time After L. H
CnSet-UpTimeBeforeL. H
7,8,9, 10, 11
Cn Hold Time After L. H
7,8,9, 10, 11
1012 Set-Up Time Before L. H
7,8,9, 10, 11
7,8,9, 10, 11
L.
1012 Hold Time After L. H
1345 Set-Up Time Before L. H
1345 Hold Time After L. H
~78 Set-Up Time Before L.
7,8,9,10,11
RAMo, RAM15, Qo, Q15
Set-Up Time Before L. H
RAMo, RAM15, Qo, Q15
Hold Time After L. H
9
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
H
o
c;
7,8,9,10,11
7,8,9,10,11
1678 Set-Up Time Before H. L
1678 Hold Time After H. L
1678 Hold Time After L. H
•
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
Document#: 38-00017-C
6-89
CY7C9115
CY7C9116/CY7C9117
CYPRESS
SEMICONDUCTOR
Features
• Fast
- 35-ns worst-case propagation delay,
ItoY
• LowpowerCMOS
- Icc (max. at 10 MHz) = 145 mA
(commercial)
- Icc (max. static) 68 mA
(commercial)
=
• Vcc marginSV:!:IO%
-.!JI parameters guaranteed over
commercial and military operating
temperature range
• Instruction set and architecture optimized for high-speed controller applications
CMOS 16-Bit
Microprogrammed ALU
• Pin compatible and functionally
equivalent to 29116, 29116A, 29C116,
29117,29117A, 29C117
• CY7C9117 separate I/O
- One and two operand arithmetic
and logical operations
- Bit manipulation, field insertion!
extraction instructions
- Eleven types of instructions
• Immediate instruction capability
• 16-bit barrel shifter capability
• 32-word x 16-bit register file
• 8-bit status register
- Four ALU status bits
- Unk bit and three user-definable
status bits
• Capable of withstanding greater than
2001V static discharge voltage
Logic Block Diagram CY7C9115, CY7C9116
Functional Description
The CY7C9115, CY7C9116, and
CY7C9117 are high-speed 16-bit microprogrammed Arithmetic and Logic Units
(ALUs).
The architecture and instruction set of the
devices are optimized for peripheral controller applications such as disk controllers,graphics controllers, communications
controllers, and modems. When used with
the CY7C517 multiplier, the CY7C9115,
CY7C9116, and CY7C9117 also support
microprogrammed processor applications.
..--------<:::::J OEv
OLE
16
10 -1'5
c-,.'¢>crJ>N»O,!l
Y.
Y.
GND
0Ev
Y7
Vee
Vee
Y.
Y.
Y1Q
OLE
GND
Y"
8
9
10
11
12
13
14
15
16
17
18
19
20
y..:.:
~O
7 6 5 4 3 2 1115251 504948 47
46
45
44
43
42
7C9115 PLCC
41
7C9116 LCC
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
17
10
114
113
112
115
Y.
v,
I"
I,.
v.
va
I.
I.
I.
GND
Vee
I.
la
17
I.
Is
GND
Vee
I.
I,
I.
CP
lEN
SRE
I.
la
I.
I,
';';';';~~~~N~~C9~V~ t;
7C9115-3
I.
CP
lEN
SRE
er
DEr
T.
Ta
GND
T.
v.
v.
v.
GND
CEy
V7
Vee
Vee
v,
v.
v,.
OLE
GND
V"
V'2
V,a
v,.
v's
NC} RESERVED
NC
T,
7C9115-5
PLCC
Top View
Ya
NC
Y.
Y.
Y.
GND
0Ev
Y7
Vee
Vee
Y.
Y.
Y,.
OLE
GND
I.
I.
17
I.
Is
GND
Vee
I.
la
'I,2
I.
CP
Y"
lEN
SRE
CT
Y'2
OEr
7C9115-4
6-92
CY7C9115
CY7C9116/CY7C9117
J~
.'~~DUCIDR
Pin Configurations (continued)
LCC/PLCC
Top View
,
9 B 7 6
Y3
10
0-,
11
Y4
Ys
Va
GNO
12
13
14
OEy
15
16
V7
17
Vee
18
Vee
Va
19
20
V.
21
Y10
22
OLE
23
GNO
24
V11
25
Y12
26
543 2:11686766 6564636261
• •
60
59
5&
57
56
55
54
53
52
51
50
49
46
CY7C9117
I.
I.
17
I.
10
GNO
Vee
I.
I_
I,
I,
I.
CP
II
o
lEN
47
46
45
SRE
CT
44
OET
.~~~~~~~~~D~~~~~~
a
7C9115·7
68PGA
Top View
51
D.
53
V"
55
OLE
57
V.
59
Vee
60
NC
62
0Ev
64
V.
66
V.
68
V3
•
52
V,,
49
V,.
50
V,.
47
GND
48
V15
45
44
0,.
0"
46
43
D.
D'2
~
T,
40
GND
41
T,
~
0,.
~
38
014
T_
37
015
35
T,
33
54
CT
GNO
31
56
v,o
lEN
28
58
I.
v.
61
~
I_
CY7C9117
V7
25
63
GNO
65
22
I.
67
20
07
17
49
V,
Vo
51
50
V,
GNO
52
53
D.
54
Do
D.
55
57
0,
115
12
56
0,
5&
0,
Do
59
14
I,.
13
114
16
I"
15
112
32
SRE
30
CP
28
I,
27
I,
24
Vee
I.
Vo
34
OET
18
I.
23
GNO
21
I.
19
I.
17
I,.
7C9115-B
6-93
9
CY7C9115
CY7C9116/CY7C9117
Maximum Ratings
(Above which the useful life maybe impaired. Foruser guidelines,
not tested.)
StorageThmperature .....•.......•..•. -65'Cto+lSO'C
Ambient Thmperature with
Power Applied ......•••.........••••• - SS·C to + 12S'C
Supply Voltage to Ground Potential. • . • • • •. - O.sV to + 7.0V
~'iri';i!~:~~~~ ~~ ~~~............
Static Discharge Voltage •........•.•........••.• >2001V
(Per MJL-STD-883 Method 301S)
Latch-Up Current (Outputs} •••.•......•..•..... >200 mA
Operating Range
Range
Commercial
- O.SV to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (LOW) ...•....•...... 30 mA
MilitatyllJ
Ambient
Temperature
O'Cto +70'C
Vee
SV±10%
- 55'Cto +12S'C
SV±lO%
Notes:
1.
TA is the "instant on" case temperature.
Description of Architecture
The CY7C9115, CY7C9116, and CY7C9117 are 16-bit micro-
programmed arithmetic and logic units comprised of the following sections (see block diagram):
• 32-Word x 16-Bit Register File
• DataLatch
• Instruction Latch and Decoder
• Accumulator
• Logic Unit with a 16-Bit Barrel Shift Capability
captures the instruction at the instruction inputs. For Immediate
Instructions, the data at the instruction inputs during the second
clock cycle is used as one of the operands for the Immediate Instruction specified during the first clock cycle. Upon completion
of the Immediate Instruction (the end of the second clock cycle),
the Instruction Latch again becomes transparent.
Accumulator
The accumulator is a 16-bit edge-triggered register. If the lEN is
LOW and the current instruction specifies the accumulator as its
destination, the accumulator accepts Y -input data at the clock
LOW-to-HIGH transition. Word instructions write into all 16 bits
of the accumulator, byte instructions write into the lower eight
bits.
16-Bit Barrel Shifter
• Arithmetic Unit
• Priority Encoder
• Condition Code Generator and Multiplexer
• Status Register
• Output Buffers
32·Word x 16·Blt Register File
The 32-word x 16-bit register file is a single-port RAM with a
16-bit latch at the output. The latch is transparent while CP is
HIGH and latched when CP is LOW. IfmN is LOW and the current instruction specifies the RAM at its destination, data is written into the RAM while CP is LOW. Word instructions write into
all 16 bits of the RAM word addressed; byte instructions write
into only the lower eight bits.
Use of an external multiplexer on five of the instruction inputs
makes it possible to select separate read and write addresses for
the same Non-immediate Instruction. Immediate Instructions do
not allow this two-address operation for the 7C911S and 7C9116.
The 7C9117 does support two-address Immediate Instructions.
Data Latch
The data latch holds the 16-bit input to the CY7C911S,
CY7C9116, and CY7C9117 from the Y (bidirectional) bus for
the 7C911S and 7C9116 and the data bus for the 7C9117. When
DLE is HIGH, the latch is transparent, and it is latched when
DLEisLOW.
Instruction Latch and Decoder
The 16-bit instruction latch is always transparent, except when
Immediate Instructions are executed The Instruction Decoder
decodes the instruction inputs into the internal signals which control the CY7C9115, CY7C9116, and CY7C9117. All instructions
other than Immediate Instructions execute in a single clock cycle.
Execution ofImmediate Instructions takes two clock cycles. During the first clock cycle, the Instruction Decoder identifies the instruction as an Immediate Instruction and the Instruction Latch
The barrel shifter can rotate data input to it from either the register file, the accumulator, or the data latch from 0 to 15 bit positions. In word mode, the barrel shifter rotates a 16-bit word; in
byte mode, it only affects the lower eight bits. The barrel shifter is
used as one of the ALU inputs.
Arithmetic and Logic Unit
The CY7C911S, CY7C9116, and the CY7C9117 have an arithmetic unit and a logic unit. The arithmetic unit is capable of operating on one or two operands while the logic unit is capable of
operating on one, two, or three operands. The two units in parallel are able to execute the one and two operand instructions such
as pass, complement, two's complement, add, subtract, AND,
OR, EXOR, NAND, NOR, and EXNOR. Three operand instructions include rotate/merge and rotate/masked compare.
There are three data types supported by the CY7C911S,
CY7C9116, and CY7C9117; bit, byte, and 16-bit word.
All arithmetic and logic unit operations can be performed in eitherword or byte mode, with byte instructions performed only on
the lower eight bits.
Three status outputs are generated by the arithmetic unit: carry
(C), negative (N), and overflow (OVR). A zero flag (Z) detects a
zero condition, though this flag is not generated by the arithmetic
unit or the logic unit. These flags are generated in either word or
byte mode, as appropriate.
The arithmetic unit uses full carry look-ahead across all 16 bits
during arithmetic operations. The carry input to the arithmetic
unit comes from the carry multiplexer, which can select either
zero, one, or a stored carry bit (QC) from the status register.
Multiprecision arithmetic uses QC as the carry input.
6-94
=--
CY7C9115
CY7C9116/CY7C9117
---·~PRESS
IF
SEMICONDUCTOR
Description of Architecture (continued)
Priority Encoder
The priority encoder generates a binary-weighted code based on
the location of the highest order ONE in its input word or byte. The
operand to be prioritized may be ANDed with a mask to eliminate
certain bits from the priority encoding. This masking is performed
by the logic unit.
In word mode, the output is a binary one if bit 15 is the first (unmasked) HIGH encountered, a binary two if bit 14 is the first
HIGH and so on. IfbitO is the only HIGH, the output of the priority encoder is binary 16. If no bits are HIGH, a binary zero is output.
In byte mode, only bits 7 through 0 are examined. Bit 7 HIGH produces a binary one, bit 6 a binary two, and so on. Ifbit 0 is the only
HIGH, a binary eight is output; if no bits are HIGH, a binary zero
is output.
Condition Code Generator and Multiplexer
The twelve condition code test signals are generated in this section.
The multiplexer selects one of these twelve and places it at the CT
output. The multiplexer is addressed by either using the Test Instruction or by using the bidirectional T bus as an input. The test
instruction specifies the test condition to be placed at the CT output, but it does not allow an ALU operation at the same time. Usingthe Tbus as input, the CY7C9115, CY7C9116, and CY7C9117
may simultaneously test and execute an instruction. The test instructionlines (14 - 10) take precedence overT4 - Tl for testing
status.
Status Register
The 8-bit status word is held by the status register. The status registeris updated at the end of all instructions except NO-Op' Save Status, and lest Status,~vided the status register enable (SRE) and
instruction enable (lEN) are both LOW. The status register is inhibitedfrom changing if either SRE or lEN are HIGH.
The lower four status bits are the ALU status: OVR (overflow), N
(negative),C (carry), and Z (zero). The upper four bits are a link
bit and three user-defined status bits (Flagl, Flag2, Flag3).
As stated above, when lEN and SRE are LOW, the status register
is updated at the end of all instructions other than NO-Op, Save
Status, and Test Status. The lower four status bits are updated under the above conditions, with the additional exception of when
lEN and SRE are LOW and the Status Set/Resetinstructionisperformed on the upper four bits. When lEN and SRE are LOW, the
upperfour status bits are only changed during their corresponding
Status Set/Reset instructions and during Status Loadinstructions
in word mode. The Link-Status bit is also updated after every shift
instruction.
The status register can be loaded via the internal Y bus; it can also
be selected as a source for the internal Y bus. Loading the status
registerin word mode updates all eight bits ofthe status register. In
byte mode, only the lower four bits are updated.
Using the status register as a source in the word mode loads all
eight bits into the lower byte of the destination; the upper byte is
zero-filled.ln byte mode, the status register loads the lower byte of
the destination; however the upper byte is unchanged. Interrupt
and subroutine processing is facilitated by this store/load combination, which allows saving and restoring the status register. The lowerfour bits of the status register can be read directly by outputting
them to the T4 - T 1 outputs. These outputs are enabled when OET
is HIGH.
Output Buffers
1Wo sets of bidirectional buses exist on the CY7C9115 and
CY7C9116.ThebidirectionaIYbus(16bg&iscontrolledbyOEy.
The three state outputs are enabled when OEy is LOW, they are at
high impedance when OEy is HIGH. This will allow data to be input to the data latch from the external world. The second bidirectional bus is the four-bit T bus. These three-state buffers are enabled by a HIGH on OET, which will output the internal ALU
status bits (OVR, N, C, Z). If OET is LOW, the T outputs are at
high impedance, and a test condition can be input on the T bus to
determine the CT output.
The 7C9117 has separate Y bus output and Data Input buses. All
other pins are functionally equivalent to the 7C9115 and 7C9116.
6-95
•
o
C;
o
...I
CY7C9115
CY7C9116/CY7C9117
Pin Definitions
Signal
Name
Y15 - Yo
I/O Data Input/Output. These bidirectional lines
are used to directly load the 16-bit data latch
when OEy is HIGH. When OEy is LOW, the
arithmetic unit or the logic unit output data is
output on Y 15 - yo.
CT
OEy
Y Output Enable. This controls the 16-bit
Y15 - Yo I/O port. When OEy is LOW, the
Y outputs are enabled, when OEy is HIGH,
the Y outputs are disabled (high impedance).
ORr
T Output Enable. The four-bit T outputs are
enabled when OET is HIGH; they are disabled (high impedance) when ORr is LOW.
CP
Qock Pulse. The RAM output latch is transparent when CP is HIGH; the RAM output is
latched when CP goes LOW. If lEN is LOW
and the current instruction specifies the
RAM as the destination, then data is written
into the RAM while CP is LOW. If lEN is
LOW, the Accumulator and Status Register
will accept data at the clock LOW to HIGH
transition. The instruction latch becomes
transparent upon exiting an Immediate Instruction during a LOW to HIGH clock transition.
DIS - Do
These input lines are used to directly load the
data latch.
Y15 - Yo
I/O These output lines are used to present the
arithmetic unit or the logic unit output when
OEyisLOW. (CY7C9117Y15 - Yo and output only.)
Conditional Test. One of twelve condition
code signals is selected by the condition code
multiplexer to be placed on the CT output.
CT = HIGH for a pass condition; CT =
LOW for a fail condition.
DLE
Data Latch Enable. The 16-bit data latch is
transparent when DLE is HIGH and latched
when DLE is LOW.
lEN
Instruction Enable. The following occurs with
lEN LOW: Data may be written into the
RAM when the clock is LOW, the accumulator can accept data during the clock LOW to
HIGH transition, and the Status R~tercan
be updated when SRE is LOW. If lEN is
HIGH, CT is disabled as a function of the
instruction inputs. lEN should be LOW during the first half of the first cycle of Immediate Instructions.
Description
Status Register Enable. The Status Register
is updated at the end of all instructions except NO-Op, Save Status, and Thst Status
when SRE and lEN are both LOW. The Status Re~r is inhibited from changing when
either SRE or lEN are HIGH.
I/O Status Input/Output. These bidirectional pins
are used to output the lower four status bits
(OVR, N, C, and Z) when ORr is HIGH.
When OET is LOW, these lines are used as
inputs to generate the conditional test (CT)
output.
0
I/O
SRE
Instruction Word. This 16-bit word selects
the function performed by the 7C911X.
These lines are also used to input data when
executing Immediate Instructions.
115 - 10
T4- T l
Signal
Name
Description
I/O
Instruction Set
The instruction set of the CY7C9115, CY7C9116, and CY7C9117
is optimized for peripheral controller applications. It features: Bit
Set, Bit Reset, Bit Test, Rotate and Merge, Rotate and Compare,
and Cyclic-Redundancy-Check (CRC) generation, in addition to
standard Single- or 1\vo-Operand logical and arithmetic instructions. A single clock cycle will execute all but the Immediate Instructionswhich take 2 clock cycles.
The CY7C9115, CY7C9116, and CY7C9117 can operate in three
different data modes: bit, byte, and word (16 bits). The LSB of the
word is used for Byte Mode. Also in Byte Mode when the status
registeris specified as the destination, only the LSH (OVR, N, C,
Z) of the register is updated. Save Status and Thst Status instructions do not change the status register. During Test Status instructions the Y bus (or D bus for the CY7C9117) is undefined; the result is in the CT output.
The eleven instruction types outlined below are described in detail
on the following pages.
Single-Operand
Rotate and Compare
Prioritize
1\vo-Operand
CRC
Single Bit Shift
Bit-Oriented
Status
Rotate by n Bits
No-Op
Rotate and Merge
OEy is assumed LOW for all cases, allowing ALU outputs on the
YorDbus.
Instructions are individually distinguished by using OP-CODES
and two assigned quadrant bits. Four quadrants, 0 to 3, have been
assigned to each instruction type in order to ease groupings of instructions and addressing modes.
6-96
·
CY7C9115
CY7C9116/CY7C9117
~
~iE CYPRF.SS
---:=-.F
SEMlCGlDUcroR
Thble 1. Operand Source-Destination Combinations
Operand Combinations[2]
Instruction 'JYpe
Source (R/S)
Destination
RAMl"3]
RAM
ACC
YBus
Status
ACCand
Status
SingJeOperand
SOR
SONR
ACC
D
D~OE)
SSE)
I
0
Two Operand
TOR!
TOR2
TONR
Source (R)
Source(S)
Destination
RAM
RAM
D
D
ACC
D
ACC
RAM
ACC
YBus
Status
ACCand
Status
I
RAM
ACC
I
I
Source(U)
Destination
RAM
ACC
ACC
D
D
D
RAM
ACC
YBus
RAM
ACC
YBus
Source (RlS)
Destination
RAM
ACC
D
RAM
ACC
YBus
Source(U)
Destination
RAM
ACC
D
RAM
ACC
YBus
Single Bit Shift
SHFTR
SHFfNR
Bit Oriented
BOR!
BOR2
BONR
Rotate n Bits
ROTRl
ROTRZ
ROTNR
Rotated
Source(U)
Rotate and
Merge
ROTM
ROTC
D
D
D
D
ACC
RAM
Mask(S)
I
RAM
I
ACC
I
I
Operand Combinations[2]
Instruction 'lYpe
Rotated
Source(U)
Rotate and
Compare
CDAI
CDR!
CDRA
CRA!
Prioritizel:4]
PRTl
PRT2
PRTNR
Cyclic RedundancyCheck
CRCF
CRCR
Mask(S)
Non-Rotated
Source/
Destination (R)
I
ACC
RAM
RAM
ACC
Sonrce (R)
Mask(S)
Destination
RAM
ACC
D
RAM
ACC
I
RAM
ACC
YBus
Data In
Destination
Polynomial
QLINK
RAM
ACC
D
D
D
RAM
I
I
ACC
0
o
a
9
Bits Affected
OVR,N,C,Z
Set Reset Status
SETST
RSTST
SVSTR
SVSTNR
TEST
LINK
Flagl
FJagZ
FJag3
Store Status
Status Load
Non-Rotated
Source/
Destination (R)
Source
Destination
Status
RAM
ACC
YBus
Source (R)
Source(S)
Destination
D
ACC
ACC
Status
Status and
ACC
I
D
ACC
ACC
RAM
RAM
RAM
ACC
I
Thst Condition (CT)
Test Status
(N ¥OVR) +Z
N¥OVR
Z
OVR
Low
C
No Operation
NOOP
Notes:
2. Ifthere is no division between the R/S operand or SOURCE and DESTINATION, the two are a given pair. If a division exists, anycombination is possible.
3.
4.
6-97
•
Z+C
N
LINK
Flagl
FlagZ
Flag3
-
RAMcannot be used as source when both ACC and STATUS are designated as a DESTINATION.
OPERAND and MASK must be different sources.
CY7C9115
CY7C9116/CY7C9117
@.;;rl
~'~UCTOR
Instruction Set(continued}
Single-Operand Instructions
Each Single-Operand instruction contains four designators:
4. Mode (Byte or Word)
5. Opcode
6. Source
7. AddressorDestination
These designators are divided into two basic categories, those that
use RAM addresses and those that do not.
SOR
Quadrant
B/W
13
14
15
SONR
13
14
15
Quadrant
B/W
The instruction formats shown below are unique for each category.
In both cases the desired operation, controlled by the instruction
inputs, is performed on the source with the result either placed on
the Y bus or stored in the destination or both. The functions of Extending Sign Bit (D(SE}) and Binary Zero (D(OE» over 16 bits in
Word mode are available for cases where 8-bit to 16-bit conversion
is necessary. The functions performed using Single-Operand instructionsupdate the LSB of the status register (OVR, N, C, Z) but
do not effect the MSB (FlAG1, FlAG2, FLAG3, LINK). Singleoperand instructions are limited such that when both the ACC and
the status register are the destination, the source cannot be RAM.
9
12
Opcode
Opcode
o
4
SRC-Dest
9
12
5
8
RAM Address
5
8
o
4
SRC
I
Destination
Fignre 1. Single-Operand Field Definitions
Thble 2. Single-Operand Instruction Set
15 14 13 12
Instruction!5] BJWl6] Quad!?]
SOR
O=B
l=W
10
Instruction
BIW
Quad
SONR
O=B
l=W
11
8 5
9
4
RlS!8]
Opcode
1100
1101
1110
1111
MOVE
COMP
INC
NEG
1100
1101
1110
1111
MOVE
COMP
INC
NEG
SRC.Dest
SRC.Dest
SRC+1.Dest
SRC+UDest
0000
0010
0011
0100
0110
0111
1000
1001
1010
1011
SORA
SORY
SORS
SOAR
SODR
SOIR
SOZR
SOZER
SOSER
SORR
0100
0110
0111
1000
1001
1010
SOA
SOD
SOl
SOZ
SOZE
SOSE
Dest!8]
RAM
RAM
RAM
ACC
YBus
Status
ACC
RAM
D
RAM
I
RAM
RAM
0
D~OE} RAM
DSE) RAM
RAM RAM
0
RAM Address/Destination
00000 ROO
RAM Reg 00
11111 R31
RAM Reg 31
RlS!8]
Opcode
SRC. Dest
SRC.Dest
SRC+UDest
SRC+1.Dest
....
Destination
ACC
D
I
0
D~OE}
00000
00001
00100
00101
NRY
NRA
NRS
NRAS
YBus
ACC
Statusl9]
Acc,Statusl9]
D SE)
Thble 3. Y Bns and Status!lO]
Instruction
Opcode
SOR
SONR
COMP
SRC.Dest
Description
INC
SRC+1. Dest
MOVE
SRC.Dest
NEG
SRC+1.Dest
Notes:
5. Instructionmnemonic.
6. B = Byte Mode, W = Word Mode.
7. Quadrant subdivides instructions into categories.
8. R =Source; S = Source; Dest =Destination.
B/W
l=W
O=B
FlagJ
FIag2
Flagl
LINK
OVR
N
C
Z
Y.SRC
NC
NC
NC
NC
0
U
0
U
Y.SRC+1
NC
NC
NC
NC
U
U
U
U
Y.SRC
NC
NC
NC
NC
0
U
0
U
Y.SRC+ 1
NC
NC
NC
NC
U
U
U
U
YBns
9.
Status is destination,
Status i. Yi
i = 0 to 3 (byte mode)
i = Ot07 (word mode)
10 SRC = Source' NC = No Change' 1 = Set· U
. i = 0 to 15 wh~n not specified"
6-98
= Update' 0 = Reset·
,
,
-
CY7C9115
CY7C9116/CY7C9117
-~
. .1= CYPRESS
JF
SEMICONDUCTOR
Instruction Set (continued)
1Wo-Operand Instructions
These instructions are further divided into those using RAM addresses and those that do not. The first type uses two formatswhich
differ only by quadrant designator.
Each Two-Operand instruction is constructed of 5 fields:
1. Mode (Byte or Word)
Functions are performed on the specified Rand S sources and results are stored in the specified destination and/or placed on the Y
bus. Arithmetic functions update the least significant nibble of the
status register (OVR, N, C, Z), while logical functions affect only
theN andZbits. Executions ofiogical functions ciear the OVR and
C bits of the status register.
2. Opcode
3. RSource
4. SSource
5. Address or Destination
15
14
13
TORI
9
12
8
5
SRC-SRC, Dest
15
14
13
TOR2
8
5
SRC-SRC, Dest
15
13
14
TONR
4
0
•
RAM Address
9
12
0
RAM Address
9
12
4
8
5
SRC-SRC, Dest
4
0
Destination
o
C;
o....I
Figure 2. 1Wo-Operand Field Definitions
Thble 4. 1Wo-Operand Instruction Set
Instruction
B/W
Quad
TORI
O=B
I=W
00
0000
0010
0011
1000
1010
1011
1100
1110
1111
TORAA
TORIA
TODRA
TORAY
TORIY
TODRY
TORAR
TORIR
TODRR
R[8]
S[8]
Dest[8]
RAM
RAM
D
RAM
RAM
D
RAM
RAM
D
ACC
I
RAM
ACC
I
RAM
ACC
I
RAM
ACC
ACC
ACC
YBus
YBus
YBus
RAM
RAM
RAM
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Instruction
B/W
Quad
TOR2
O=B
I=W
10
R[B]
S[8]
Dest[8]
0001 TODAR D
0010 TOAIR ACC
0101 TODIR D
ACC
I
I
RAM
RAM
RAM
SminusR 00000
SminusR
with carry 11111
SUBS
RminusS
SUBsd ll ] RminusS
with carry
ADD
RpiusS
ADDC
R plus S
with carry
AND
Ri\S
NAND
Ri\S
EXOR
R¥S
NOR
RVS
OR
RVS
EXNOR
R¥S
0100 ADD
0101 ADDC
0110
0111
1000
1001
1010
1011
11. For subtraction the carry is interpreted as borrow.
6-99
AND
NAND
EXOR
NOR
OR
EXNOR
ROO RAM RegOO
....
RAM Reg31
R31
RAM Address
Opcode
0000 SUBR
0001 SUBRCLllJ
0010 SUBS
0011 SUBsd ll ]
Notes:
RAM Address
Opcode
0000 SUBR
0001 SUBRC[Il]
SminusR 00000
SminusR
with carry 11111
RminusS
RminusS
with carry
RpiusS
R plus S
with carry
Ri\S
Ri\S
R¥S
RVS
RVS
R¥S
ROO RAM Reg 00
.. . ...
R31 RAM Reg31
CY7C9115
CY7C9116/CY7C9117
-'~PRESS
- , F SEMICONDUCTOR
Instruction Set (continued)
Thble 4. Tho-Operand Instruction Set (continued)
Instruction
B/W
Quad
TONR
O=B
l=W
11
0001 TODA
0010 TOAI
0101 TOD!
R[8]
S[8]
D
ACC
D
ACC
I
I
Opcode
Destination
0000 SUBR
SminusR 00000
0001 SUBRC[ll] SminusR 00001
with cany 00100
0010 SUBS
RminusS 00101
0011 SUBsd ll ] RminusS
withcany
0100 ADD
RpIusS
R plus S
0101 ADDC
withcany
0110 AND
Ri\S
0111 NAND
Ri\S
1000 EXOR
R¥S
1001 NOR
RVS
1010 OR
R VS
1011 EXNOR
R¥S
NRY
NRA
NRS
NRAS
YBus
ACC
Status[9]
ACC,Status[9]
Thble S. Y Bus and Status[12]
Instruction
TORI
TOR2
TONR
Opcode
ADD
Description
RplusS
Flag3
Flag2
Flagl
Y+R+S
NC
NC
NC
YBus
B/W
O=B
l=W
LINK OVR
NC
U
N
C
Z
U
U
U
ADDC
R plus S with carry
Y+R+S+QC
NC
NC
NC
NC
U
U
U
U
AND
Ri\S
Y+RiANDSi
NC
NC
NC
NC
a
U
0
U
EXOR
R¥S
Yi + Ri EXOR Si
NC
NC
NC
NC
0
U
0
U
EXNOR
R¥S
Yi + Ri EXNOR Si
NC
NC
NC
NC
0
0
U
NAND
Ri\S
Yi + Ri NAND Si
NC
NC
NC
NC
a
U
NOR
RVS
Yi+RiNORSi
NC
NC
NC
NC
0
U
OR
RVS
Yi+RiORSi
NC
NC
NC
NC
a
U
a
a
a
a
SUBR
SminusR
Y+S+R+1
NC
NC
NC
NC
U
U
U
U
SUBRC
S minus R with carry
Y+S+R+QC
NC
NC
NC
NC
U
U
U
U
SUBS
RminusS
Y+R+S+l
NC
NC
NC
NC
U
U
U
U
SUBSC
R minus S with carry
Y+R+S+QC
NC
NC
NC
NC
U
U
U
U
U
U
U
Note:
12. U = Update; NC = No Change; 0 = Reset; 1 = Set; i = 0 to 15 when
not specified
During a shift up the LSB may be loaded with a zero, one, or with
the link status bit (QLINK), while the MSB is shifted into the
QLINK bit. During a shift down, the MSB is loaded with a zero,
one, the status carry bit (QC), the exclusive-or ofthe negative-status bit and the overflow-status bit (QN ¥ QOVR), or thelink-status bit. The status register's Nand Z bits are updated, while the
OVR and C bits are reset. Shift down with QN ¥ QOVR can be
used in two's complement multiplication.
Single-Bit Shift Instructions
Single-Bit Shift instructions are constructed of four fields:
1. Mode (Byte or Word)
2. Direction (up or down) and shift linkage
3. Source
4. Destination
These instructions are further divided into those using RAM addresses and those that do not. The shift linkage indicator indicates
what is to be loaded into the vacant bit.
6-100
·
CY7C9115
CY7C9116/CY7C9117
=
~
===='
=:,
CYPRESS
SEMICONDUCTOR
Instruction Set (continued)
15
14
I B/W I
SHFTNR I B/W I
SHFTR
13
9
12
5
8
o
4
Quadrant
SRC-Dest
Opcode
RAM Address
Quadrant
Source
Opcode
Destination
Figure 3. Single Bit Shift Field Definitions
SOURCE
SOURCE
o
01_
MUX
QCQN¥QOVR _
QLlNK
MUX
QUNK - L - _ - - '
DESTINATION
DESTINATION
7C9115-B
7C911S-9
Figure 4. Shift Up Function
Figure 5. Shift Down Function
1llble 6. Single Bit Shift Instruction Set
Instruction
B/W
Quad
SHFTR
O=B
l=W
10
Instruction
B/W
Quad
SHFTNR
O=B
l=W
11
U[13]
Desd13]
0110 SHRR RAM RAM
0111 SHDR D
RAM
0000
0001
0010
0100
0101
0110
0111
1000
SHUPZ
SHUPI
SHUPL
SHDNZ
SHDNI
SHDNL
SHDNC
SHDNOV
0000
0001
0010
0100
0101
0110
0111
1000
SHUPZ
SHUPI
SHUPL
SHDNZ
SHDNI
SHDNL
SHDNC
SHDNOV
U[13]
0110 SHA
0111 SHD
ACC
D
Up
Up
Up
Down
Down
Down
Down
Down
0
00000 ROO RAM Reg 00
1
....
QLINK
11111 R31 RAM Reg 31
0
1
QLINK
QC
QN¥QOVR
Opcode
Up
Up
Up
Down
Down
Down
Down
Down
Destination
0
00000 NRY YBus
1
00001 NRA ACC
QLINK
0
1
QLINK
QC
QN¥QOVR
1llble 7. Y Bus and Status[lO]
Instruction
SHR
SHNR
Opcode
Description
SHUPZ
SHUPI
SHUPL
UpO
Upl
UpQLINK
SHDNZ
SHDNI
SHDNL
SHDNC
SHCNOV
B/W
FlagJ Flag2 Flagl LINKl14] OVR
YBus
N
CZ
l=W Yi.SRq-1.i= ltol5;
Yo. Shift Input
NC
NC
NC
SRC15
0
SRC14 OU
Yi. SRq _ 1. i = 1 to 7;
Yo. Shift Input;
YS.SRC7, Yi. SRq-9
fori = 9 to 15
NC
NC
NC
SRC7
0
SRQ; OU
Down 0
1-W Yi.SRq+ 1.i- Oto 14;
Down 1
Y 15 • Shift Input
DownQLINK
O=B Yi.SRq + 1.i = Ot06;
DownQC
Yi. SRq_7,i=8t014;
DownQN¥
Y7, 15 • Shift Input
QOVR
NC
NC
NC
SRCo
0
Shift OU
Input
NC
NC
NC
SRCo
0
Shift OU
Input
O=B
Notes:
13. U = Source; Dest = Destination
14. Shifted output is loaded into the QUNK.
6-101
•
o
RAM AddressIDestination
Opcode
C3
9
CY7C9115
CY7C9116/CY7C9117
fiil~NlYJC1OR
Instruction Set(continued)
Reset Bit n: Forces the nth bit to ZERO without affecting other bit
positions.
Thst Bit n: Sets the Z status bit to the state of bit n.
Load 2°: Loads ZERO in bit positionn and sets all other bits.
Load 2°: Loads ONE in bit position n and clears all other bits.
Bit-Oriented Instructions
Bit-Oriented instructions are constructed from four fields:
1. Mode (Byte or Word)
2. Operation
3. Source or Destination
4. Bit position operated on (0 = LSB)
These instructions are further divided into those using RAM addresses and those that do not. The specified function operates on
the given source and the result is stored in the specified destination
and/or on the Y bus.
Increment 2°: Adds 2° to the operand.
Decrement 2°: Subtracts 2° from the operand.
Load, Set, Reset, and Test instructions update N and Z status bits
while forcing OVR and Cbits to ZERO. Arithmetic operations affect the entire lower nibble of the status register (OVR, C, N, and
Z).
Set Bit n: Forces the nth bit to ONE without affecting other bit positions.
15
BOR1
15
15
14
13
8
N
5
8
N
o
4
RAM Address
Opcode
9
12
Quadrant
B/W
Opcode
9
12
5
8
N
Quadrant
B/W
BONR
13
14
9
12
Quadrant
B/W
BOR2
13
14
4
0
RAM Address
5
4
1100
0
Opcode
Figure 6. Bit-Oriented Field Dermitions
lhble 8. Bit-Oriented Instruction Set
Instruction
B/W
Quadrant
BOR1
O=B
l=W
11
Instruction
B/W
Quadrant
BOR2
O=B
l=W
10
Instruction
B/W
Quadrant
BONR
O=B
l=W
11
Opcode
n
Oto15 1101 SETNR
1110 RSTNR
1111 TSTNR
n
Ot015 1100
1101
1110
1111
n
Set RAM, bit n
Reset RAM, bit n
Thst RAM, bit n
RAM Address
00000 ROO
RAM Reg 00
11111 R31
RAM Reg 31
Opcode
LD2NR
LDC2NR
A2NR
S2NR
~.RAM
....
RAM Address
00000 ROO
RAM Reg 00
2°. RAM
RAM plus 2°. RAM
11111 R31
RAM minus 2°. RAM
RAM Reg 31
Opcode
Ot015 1100
Opcode
00000
00001
00010
00100
00101
00110
00111
10000
10001
10010
10100
10101
10110
10111
6-102
....
TSTNA
RSTNA
SETNA
A2NA
S2NA
LD2NA
LDC2NA
TSTND
RSTND
SETND
A2NDY
S2NDY
LS2NY
LDC2NY
Thst ACC, bit n
Reset ACC, bit n
Set ACC, bit n
ACC plus 2° • ACC
ACC minus 2° • ACC
~.ACC
2°.ACC
ThstD, bitn
Reset D, bit n
SetD, bitn
D plus 2° • Y Bus
D minus 2° • Y Bus
~.YBus
2°.YBus
-
CY7C9115
CY7C9116/CY7C9117
~
.J'
~=CYPRESS
~_
SEMICONDUCTOR
Instruction Set (continued)
Rotate by n Bits Instructions
the number of bit positions the source is to be rotated up (0 to 15),
and the result is either stored in the specified destination or placed
on the Y bus or both. An example of this instruction is given inFig.
ure 8. In the Word mode, a1116 bits are rotated up; while in the Byte
mode, only the lower 8 bits (0 - 7) are rotated up. In the Word
mo~e, a ~ot.ate up.by n bits is equivalent to a rotate down by (16 n) bits. Similarly, ill the Byte mode a rotate up by n bits is equivalentto a rotate down by (8 - n) bits. TheN andZbits of the status
register are affected and OVR and C bits are forced to zero.
The Rotate by n Bits instructions contain four indicators: byte or
word mode, source, destination, and the number of places the
source is to be rotated. They are further subdivided into two types.
The first type uses RAM as a source and/or a destination and the
second type does not use RAM as a source or destination. The first
type has two different formats and the only difference is in the
quadrant. The second type has only one format as shown in Table 9.
Under the control of instruction inputs, the n indicator specifies
15
ROTRI
ROTR2
ROTNR
B/W
14
13
12
9
Quadrant
5
8
n
o
4
SRC-Dest
RAM Address
~~==~==~==~==~
B/W
Quadrant
n
SRC-Dest
RAM Address
~~==~==~==~====~
B/W
Quadrant
n
1100
SRC-Dest
•
~~______~______- L__~~-L~~~~
Figure 7. Rotate by n Bits Shift Field Definitions
o
EXAMPLE: n = 4, Word Mode
Source
0001
0011
Destination
0011
0111
0111
1111
1111
0001
EXAMPLE: n = 4, Byte Mode
Source
0001
Destination
0001
0111
1111
1111
0111
0011
0011
(3
o
...J
Figure 8. Rotate by n Example
Thble 9. Rotate by n Bits Instruction Set
Instruction
ROTRI
Instruction
ROTR2
Instruction
ROTNR
B/W
Quadrant
n
00
Oto 15
0 B
I=W
B/W
Quadrant
n
01
Oto 15
0 B
I=W
B/W
Quadrant
n
11
Oto 15
0 B
I=W
U[13]
Destl13]
1100
1110
1111
RTRA
RTRY
RTRR
RAM
RAM
RAM
U[13]
ACC
YBus
RAM
Destl13]
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
0000
0001
RTAR
RTDR
ACC
D
RAM
RAM
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
U[13]
Destl l3]
11000
11001
11100
11101
RTDY
RTDA
RTAY
RTAA
D
D
ACC
ACC
1100
RAM Address
..
..
. ...
RAM Address
..
. ...
YBus
ACC
YBus
ACC
Thble 10. Y Bus and Status[IO]
Instruction
ROTRI
ROTR2
ROTNR
Opcode
YBus
B/W
1
W
Yi. SRC(i -
0
B
Yi. SRq + 8
fori=Ot07
n)mod 16
-
SRC(i -
n)mod 8
6-103
FJag3
FIag2
Flagl
LINK
OVR
C
Z
NC
NC
NC
NC
0
SRCI5-n 0
U
NC
NC
NC
NC
0
SR4-n
0
U
N
CY7C9115
CY7C9116/CY7C9117
~
.'~DUCIDR
Instruction Set (continued)
Rotate and Merge Instructions
Each Rotate and Merge instruction consists of five fields:
1. Mode (Byte or Word)
2. Rotated Source (U}
n
3. Non-Rotated Source (R)
4. Mask Location(S)
5. NumberofbitsRotated(n)
This shift register rotates source U up n places. ANDing with the
mask causes any bit i to be passed from the rotated source that corresponds to a set bit in mask position i. The R input is not shifted,
but is masked by the compliment of mask S, so that a ZERO in
mask bit i will pass bit i of R The ORed result is stored in register
R Rotate and Merge operations update the Nand Z status bits,
while clearing the OVR and C bits.
7C9115-10
Figure 9. Rotate and Merge Function
ROTM
I
15
B/W
I
14
12
13
9
Quadrant
EXAMPLE: n = 4, Word Mode
U
0011
RotatedU
0001
R
1010
Mask(S)
0000
Destination
1010
U,R,S
0001
0101
1010
1111
0101
4
5
8
n
0101
0110
1010
0000
1010
I
0
RAM Address
0110
0011
1010
1111
0011
Figure 10. Rotate and Merge Field Definitions
1ltble 11. Rotate and Merge Instruction Set
Instruction
ROTM
B/W
O=B
l=W
Quadrant
n
01
Oto 15
V115]
0111
1000
1001
1010
1100
1110
MDAl
MDAR
MDRI
MDRA
MARl
MRAI
D
D
D
D
ACC
RAM
R/Destl15]
ACC
ACC
RAM
RAM
RAM
ACC
sI15]
I
RAM
I
ACC
I
I
RAM Address
00000
11111
ROO
..
R31
RAM Reg 00
....
RAM Reg 31
Notes:
15. U = Rotated Source; RlDest = Non-Rotated SourcelDestination;
S=Mask
1ltble 12. Y Bus and Statusl12]
Instruction
ROTM
Opcode
B/W
YBus
FlagJ
Flag2
Flagl
LINK
OVR
N
C
Z
l=W
Yi. (Non Rot 0p)i • (mask)i +
(Rot Op)(i - n)mod 16 • (mask)i
NC
NC
NC
NC
0
U
0
U
O=B
Yi. (Non Rot 0p)i • (mask)i +
(Rot Op )(i - n)mod 8 • (mask)i
NC
NC
NC
NC
0
U
0
U
6-104
CY7C9115
CY7C9116/CY7C9117
·-·~PRfSS
-::;;;;;F
SEMICONDUCIOR
Instruction Set (continued)
u
Rotate and Compare Instructions
The five fields of the Rotate and Compare instructions are:
1. Mode (Byte or Word)
2. Rotated Source (V)
3. Non-Rotated Source (R)
4. Mask(S)
5. NumberofbitsRotated(n)
Input U is rotated n bits, ANDed with the inversion of Sand compared with the input R ANDed with the inversion ofS. Thus, a zero
in the mask Swill allow that bit of both inputs to be compared. The
Z bit of the status register is set ifthe comparison passes, and reset
if it does not. OVR and C bits are reset in the status register.
S(MASK)
R
n
COMPARATOR
(XOR)
7C9115-11
Figure 11. Rotate and Compare Function
15
ROTC
B/W
14
13
Quadrant
12
8
9
0001
0101
0101
0101
o
...I
RAM Address
0101
0110
1111
1111
0110
0011
0000
1111
Figure 12. Rotate and Compare Field Definitions
Thble 13. Rotate and Compare Instruction Set
Instruction
ROTC
B/W
O=B
I=W
Quadrant
n
01
Oto 15
0010
0011
0100
0101
CDAl
CDRI
CDRA
CRA!
U[16]
R[16]
S[16]
D
D
D
RAM
ACC
RAM
RAM
ACC
I
I
ACC
I
RAM Address
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
..
..
....
Notes:
16. U = Rotated Source; R = Non-Rotated Source; S = Mask
Thble 14. YBus and Status[12]
Instruction
ROTC
Opcode
B/W
YBus
Flag3
Flag2
Flag!
LINK
OVR
N
C
Z
l=W
Yi. (Non Rot 0p)i • (mask)i "l(Rot Op )(i - n)mod 16· (mask)i
NC
NC
NC
NC
0
V
0
V
O=B
Yi. (Non Rot 0p)i • (mask)i "l(Rot Op)(i - n)mod 8 • (mask)i
NC
NC
NC
NC
0
V
0
V
6-105
•
ao
o
4
V,R,S
n
EXAMPLE: n = 4, Word Mode
0011
V
Rotated V
0001
R
0001
Mask(S)
0001
Z (Status) = 1
5
CY7C9115
CY7C9116/CY7C9117
.A~C1DR
R S(MASK)
Instruction Set (continued)
Prioritize Instructions
The four fields of the Prioritize instructions are:
1. Mode (Byte or Word)
2. MaskSource(S)
3. OperandSource(R)
4. Destination
The inverter mask, S is ANDed with R. A "one" in S prohibits that
bit from participating in the priority encoding. From the 16-bit input, the priority encoder outputs as-bit binaryweighted code indicating the bit-position of the highest priority active bit. IT there are
no active bits, the output is zero. See Figure 14 for operation in both
word and byte mode. Using Prioritize updates the N and Z bits of
the status register, and forces C and OVR to zero. This instruction
is limited in that the operand and the mask must be different
sources.
15
13
14
12
7C9115-12
Figure 13. Prioritize Function
5
8
9
o
4
BfW
Quad
Destination
Source(R)
RAM Address/
Mask(S)
BfW
Quad
Mask(S)
Destination
RAM Address/
Source(R)
BfW
Quad
Mask(S)
Source(R)
RAM Address!
Destination
BfW
Quad
Mask(S)
Source(R)
Destination
Byte Mode[l7]
Word Mode
Highest Priority
Bit Active
Encoder
Output
Highest Priority
Bit Active
Encoder
Output
None
15
14
0
1
2
None
7
6
0
1
2
1
0
15
16
1
0
8
:
Figure 14. Prioritize Instruction Field Dermitions
Note:
17. Bits 8 through 15 not available.
6-106
7
CY7C9115
CY7C9116/CY7C9117
~
==er.
.~PRESS
~ iF SEMICONDUCTOR
Instruction Set (continued)
Thble 15. Prioritize Instruction Set
Instruction
PRTl
B/W
O=B
l=W
Instruction
PRTI
B/W
B/W
B/W
Destination
1000
1010
1011
PRIA
PR1Y
PR1R
1000
1010
1011
PRA
PRZ
PRI
1000
1010
1011
PRA
PRZ
PRI
1000
1010
1011
PRA
PRZ
PRI
Quad
10
10
11
0111
1001
ACC
0000
0010
RPT1A
PRlD
ACC
D
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
..
Destination
0
PRZA
PR2Y
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
....
Source(R)
ACC
0
I
0011
0100
0110
PR3R
PR3A
PR3D
0100
0110
PRTA
PRID
Mask(S)
....
RAMAddress/Source (R)
ACC
YBus
I
Mask(S)
Quad
O=B
l=W
RAM Address/Mask (S)
Source(R)
ACC
YBus
RAM
Mask(S)
Quad
O=B
l=W
Instruction
PR1NR
10
O=B
l=W
Instruction
PRT3
Quad
RAM AddressIDestination
RAM
ACC
D
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
ACC
D
00000
00001
NRY
NRA
....
Source(R)
ACC
0
•
Destination
YBus
ACC
I
Thble 16. Y Bus and Status-Prioritize Instruction[lO]
Opcode
B/W
YBus
F1ag3
F1ag2
F1agl
LINK
OVR
N
C
Z
PRT1
PRTI
l=W
Yi. CODE (SCRn • mask.,);
Ym.O; i = Ot04andn = Oto 15
m=5to15
NC
NC
NC
NC
0
U
0
U
PRT3
PR1NR
O=B
Yi. CODE (SCRn • mask.,);
Y m .O;i = Ot03 andn = Ot07
m =4to15
NC
NC
NC
NC
0
U
0
U
Instruction
CRC Instructions
The single designator for this instruction is the address of the RAM
location that is used as the checksum register. 1Wo CRC instructions, CRC Forward and CRC Reverse, are available. These instructions give the procedure for determining the check bits in a
CRC calculation. Since the CRC standards do not specify which
data bit is transmitted first, the MSB or the LSB, both Forwardand
15
CRCF
CRCR
1
14
13
Reverseoptions are available to the user. The process for generatingthe check bits for the CRC ForwardandReverseoperationsare
illustrated in Figures 16 and 17. The ACC is used as a polynomial
mask while the RAM contains the partial sum and eventually the
final check sum. The serial input comes from the QLINK bit of the
status register. Status register bits OVR and C are forced to zero
while LINK, N, and Z bits are updated.
9
12
8
5
4
o
Quadrant
0110
0011
RAM Address
Quadrant
0110
1001
RAM Address
Figure 15. Cyclic-Redundancy-CheckDefinitions
6-107
CY7C9115
CY7C9116/CY7C9117
f~PR£SS
~
SEMICCtIDUcroR
Instruction Set(continued)
POLYNOMIAL MASK
(ACC)
7C9115-13
Figure 16. eRe Forward Function
POLYNOMIAL MASK
(ACC)
SHIFTER N = 15
7C9115-14
Figure 17. eRe Reverse Function
Note:
18. 1hls bit must be transmitted first.
6-108
..
.
CY7C9115
CY7C9116/CY7C9117
'~PRESS
_ , SEMICONDUCTOR
Instruction Set (continued)
Thble 17. Cyclic Redundancy Check Instruction Set
Instruction
B/W
Quad
CRCF
1
10
Instruction
B/W
Quad
CRCR
1
10
RAM Address
0110
0011
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
..
..
. ...
RAM Address
0110
1001
..
....
Thble 18. Y Bus and Status[12]
B/W
YBus
F1agJ
Flag2
F1ag1
LINK
CRCF
l=W
Vi. [(QLINK¥RAM1S) o ACq]
¥RAMi _lfori = 15 to 1
Yo. [(QLINK¥RAM1S) o ACCo] ¥O
NC
NC
NC
RAM1S[19]
0
u
0 U
CRCR
l=W
Vi. [(QLINK¥RAMo) o ACq)
¥RAMi + 1 for i = 14toO
Y1S. [(QLINK¥RAMo) oACC1S]¥0
NC
NC
NC
RAMo[19]
0
u
0 U
Instruction
Opcode
~
19. QUNK is loaded with the shifted out bit from the checksum register.
Status Instructions
765
I F1ag3 I F1ag2 I F1ag1
20. lEN' test status instruction has priority over T 1 - T4 instruction.
Thble 19. Condition Code Output Selection
4
3
2
1
0
Link
OVR
N
C
Z
15
0
14
RSTST
0
Quad
SVSTR
B/W
Quad
SVSTNR
B/W
Quad
T2
12
0
0
0
0
1
N¥OVR
0
0
1
0
Z
0
0
1
1
OVR
0
1
0
0
LOW
0
1
0
1
C
0
1
1
0
Z+C
0
1
1
1
N
1
0
0
0
LINK
1
0
0
1
F1ag1
1
0
1
0
Flag2
1
0
1
1
Flag3
4
12
13
Quad
0
T3
13
0
T4
Set Status: Specifies which bits in the status register are to be set.
Reset Status: Specifies which bits in the status register are to be
cleared.
Store Status: Indicates byte or word and the destination into which
the processor status is saved. The register is always stored in the
low byte of the destination. The high byte is unchanged for RAM
storage and is loaded with zeroes for ACCstorage.
Load Status: Imbedded in the Single- and Two-Operandinstructions.
Thst Status: Instructions specify which of the twelve possible test
conditions are to be placed on the conditional test output. In addition to the eight status bits, four logical may be selected: N ¥ OVR,
(N ¥ OVR) + Z, Z + C, and LOW. These functions are useful in
testing two's complement and unsigned number arithmetic operations.
The status register may also be tested via the T bus as shown in
Table 19. The instruction lines 11 through 14 have bus priority for
testing the status register on the CT outputl. 20l,
SETST
OVR N C Z
9
8
5
Tl
11
0
CT
(N¥OVR)+Z
0
4
I
1011
1010
I
1010
1010
°Ecode
I
0111
1010
RAM Address/
Dest
0111
1010
Destination
Figure 18. Status
6-109
Opcode
•
~
"9
CY7C9115
CY7C9116/CY7C9117
e;;il~~R
Instruction Set(continued)
Thble 20. Status Instruction Set
Instruction
B/W
Quad
SETST
0
11
Instruction
B/W
Quad
RSTST
0
11
Instruction
B/W
Quad
SVSTR
O=B
l=W
10
Instruction
B/W
Quad
SVSTNR
O=B
l=W
11
Instruction
B/W
Quad
Test
0
11
Opcode
Set OVR, N, C, Z
Set LINK
Set Flag1
SetFlag2
SetFlag3
1011
1010
00011
00101
00110
01001
01010
SONCZ
SL
SF1
SF2
SF3
1010
1010
00011
00101
00110
01001
01010
RONCZ
RL
RF1
RF2
RF3
0111
1010
00000
ROO
RAM Reg 00
11111
R31
RAM Reg 31
Opcode
Reset OVR, N, C, Z
Reset LINK
Reset Flag1
Reset Flag2
ResetFlag3
RAM AddressIDestination
....
Destination
0111
1010
00000
00001
NRY
NRA
1001
1010
00000
00010
00100
00110
01000
01010
01100
01110
10000
10010
10100
10110
TNOZ
TNO
TZ
TOVR
TLOW
TC
TZC
TN
TL
TF1
TF2
TF3
YBus
ACC
Opcode(CT)
6-110
Test (N ¥ OVR)
ThstN¥OVR
TestZ
ThstOVR
ThstLOW
TestC
TestZ + C
TestN
ThstLINK
ThstFlagl
TestFlag2
ThstFlag3
+Z
CY7C9115
CY7C9116/CY7C9117
Instruction Set (continued)
Thble 21. Y Bus and Statusl lZ]
C
Z
0
0
0
RONCZ ResetOVR,N,C,Z O=B Yi. Ofori = Oto 15
NC
NC
NC
NC
0
RL
Reset LINK
NC
NC
NC
0
NC
NC NC NC
RF1
Reset Flagl
NC
NC
0
NC
NC
NC NC NC
RF2
Reset Flag2
NC
0
NC
NC
NC
NC NC NC
RF3
Reset Flag3
0
NC
NC
NC
NC
NC NC NC
SONCZ
SetOVR,N,C,Z
NC
NC
NC
NC
1
SL
Set LINK
NC
NC
NC
1
NC
NC NC NC
SF1
Set Flag1
NC
NC
1
NC
NC
NC NC NC
SF2
SetFlag2
NC
1
NC
NC
NC
NC NC NC
SF3
Set Flag3
1
NC
NC
NC
NC
NC NC NC
NC
NC
NC
NC
NC
NC NC NC
Test
B/W
O=B Yi.1fori = Oto IS
SaveStatusLL1J
SVSTR
SVSTNR
YBus
N
Opcode
RSTST
SETST
Description
F1ag3 F1ag2 F1agl LINK OVR
Instruction
O=B Yi. Status fori.O to 7;
l=W Yi .Ofori = 8to 15
Note 22
1
1
1
TNOZ
Thst(N ¥OVR)+Z O-B
NC
NC
NC
NC
NC
NC NC NC
TNO
Thst (N ¥ OVR)
NC
NC
NC
NC
NC
NC NC NC
TZ
TestZ
NC
NC
NC
NC
NC
NC NC NC
TOVR
ThstOVR
NC
NC
NC
NC
NC
NC NC NC
TLOW
Test LOW
NC
NC
NC
NC
NC
NC NC NC
TC
TestC
NC
NC
NC
NC
NC
NC NC NC
TZC
TestZ + C
NC
NC
NC
NC
NC
NC NC NC
TN
ThstN
NC
NC
NC
NC
NC
NC NC NC
TL
Test LINK
NC
NC
NC
NC
NC
NC NC NC
TFI
ThstFlagl
NC
NC
NC
NC
NC
NC NC NC
TF2
Thst Flag2
NC
NC
NC
NC
NC
NC NC NC
TF3
TestFlag3
NC
NC
NC
NC
NC
NC NC NC
Notes:
21. In byte mode only the lower byte from the Y bus is loaded into the
RAM or ACC and in word mode all 16 bits from the Y bus are loaded
into the RAM or ACe.
22. Y Bus is Undefined.
No-Op Instruction
The No-Op Instruction does not affect any internal registers; the
Status Register, RAM register and AC register are left unchanged.
The 16-bit opcode is fixed.
15
NO-OP
o
M
D
11
I
U
985
1000
1010
4
0
00000
I
Figure 19. No-Op Field Definition
Thble 22. Status Instruction Set
Instruction
B/W
Quad
No-Op
o
11
1000
Thble 23. Y Bus and Status llO]
6-111
1010
0000
•
~
CJ
o
...I
CY7C9115
CY7C9116/CY7C9117
.7.~~ucroR
Electrical Characteristics Over Commercial and Military Operating Rangel23J
Description
Parameters
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 1.6 rnA
VOL
VIH
Output WW Voltage
Vee = Min., IOL = 16 rnA
Min.
Input HIGH Voltage
Input WW Voltage
VIL
Max.
Units
0.4
V
V
Vee
0.8
V
2.4
2.0
V
IJX
Input Leakage Current
Vss5. VIN 5. Vee, Vee = Max.
-10
+10
loz
Ise
lee(Ql)[25]
Output LeakageCurrent
Output Short Circuit Current[24]
Vee = Max., VOUT = Vss to Vee
Vee = Max., VOUT = OV
-10
+10
- 85
Supply Current (Quiescent)
Vss5. VIN 5. VIL0LVIH 5. VIN 5. Vee; OEy = HIGH
Commercial
Military
126
145
rnA
lee(Q2)
Supply Current (Static)
VIN = Vee or GND, Vee = Max.,
IOPER = o!!A
68
rnA
Ycc = Max., fCLK = 10 MHz;
Commercial
Military
Commercial
78
145
rnA
OEy=HIGH
Military
166
lecCMax.)[25]
Supply Current
!!A
!!A
rnA
Capacitance [26]
Description
Parameters
CIN
Input Capacitance
CoUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Units
5
pF
7
pF
Output Loads Used for AC Performance Characteristics[27,28]
VO~O !~
1:
ALL INPUT PULSES
ALL OUTPUTS
+5V
R1 =114Q
Vour 0
0
'#
2.22V
7C9115·15
,OV~10~%
GND
5.5ns-
I-
t
10%
-I
5.5ns
7C9115·17
7C9115·16
Noles:
23. Vcc Min. = 4.5V, Vcc Max. = S.SY.
24. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
25. Th calculate Icc at any given frequency, use Icc(Ql) + Icc(AC)
where Icc(Ql) is shown above and Icc(AC) = (1.9 roNMHz) X
Oock Frequency for the Commercial temperature range. Icc(AC) =
(2.1 mNMHz) X Clock Frequency for Military temperarure range.
26. Tested on a sample basis.
27. CL = SO pF includes scope probe, wiring and stray capacitance.
28. CL = S pF for output disable tests.
6-112
CY7C9115
CY7C9116/CY7C9117
~
~~PRESS
~_.r SEMICCNDUCfOR
Commercial Switching Characteristics[29]
Combinatorial Propagation Delays (ns)
lbOutput
From Input
Yo -YIS
TI-T4
Yo -YIS
TI-T4
CT
CT
Speed (ns)
35
45
65
35
45
65
10 - 14 (ADDR)
35
45
65
35
52
73
10 - lIS (DATA)
35
45
65
35
52
73
10 - 115 (INST)
DLE[30]
35
45
65
35
52
73
20
32
55
30
32
55
CP
30
32
60
30
32
66
Yo- YI5
20
32
53
30
32
53
TI- T4
lEN
35
45
65
20
29
30
15
25
27
25
25
37
15
25
25
EnablelDisable Times[31] (ns)
From Input
Speed (ns)
DEy
DET
Enable
I
35
45
65
35
45
65
35
45
65
35
45
65
I
Yo - YI5
18
20
22
18
20
22
18
20
22
18
20
22
TI- T4
15
20
22
15
20
22
15
20
22
15
20
22
I
Clock and Pulse Requirements (ns)
Input
TpZH
TpZL
Minimum LOW Time
Minimum mGHTime
Speed (ns)
35
45
65
35
45
65
CP
15
15
20
15
15
15
15
15
15
15
15
20
DLE
lEN
Notes:
29. TA = O'Cto +70'C, Vee = 4.5Vto5.5V,CL = 50pF.
31. Q = 5 pF, Disable Only.
30. DLE is guaranteed by other tests.
6-113
a
TpLZ
TpHZ
•
o
Disable
lbOutput
9
CY7C9115
CY7C9116/CY7C9117
$r~PRFSS
~
SEMICONDUCTOR
Set-Up and Hold Times (ns)
Input
Note 32
With
Respect
1b
Speed (os)
IDGH-to-WW'Ihlnsition
Set-Up
WW-to-IDGH'Iransition
Set-Up
Hold
35
45
65
35
45
65
0
0
0
1
10 - 14
(RAM Addr)
CP
12
13
13
2
10 - 14
(RAM Addr)
CP&
5
5
5
•
lEN
35
10 - 115
(Data)
CP
4
10- 4
(RAM Addr)!33)
lEN
15[34) 18(34) 24(34)
4[34)
5[34)
10[34)
5
CP
CP
15[34) 18[34) 24[34J
4[34)
5[34)
10[34) 40
6
10 - 115(lostr)[35)
IEN[33)
7
lEN HIGH
IENWW
CP
CP
5
8
9
IENWW
5
10
11
SRE
y[36)
CP
CP
12
y[36)
DLE
13
DLE
CP
40
6
60
43
60
5
1
5
1
5
6
5
45
Comments
65
Single Addr
(Source)
0
0
0
0
0
0
1WoAddr
(Destination)
10
10
0
0
0
8
8
8
1WoAddr
(Immediate)
0
1
2
Disable
0
1
1
Enable
Note 34
0
CP
6
43
35
TwoAddr
(Immediate)
10
5
Hold
65
•
Do Not Change
3
5
45
12
12
12
0
0
0
32
32
42
0
0
0
20
25
43
0
0
0
5
Military Switching Characteristics[37]
Combinatorial Propagation Delays (os)
1bOutput
From Input
Speed(ns)
10-
4 (ADDR)
Yo- YIS
TI- T4
Yo- YIS
Tl- T4
CT
CT
40
65
79
40
45
79
40
65
79
40
65
79
10 - 115 (DATA)
40
65
79
40
65
79
10 - 115 (INST)
DLE[30)
40
65
79
40
65
79
20
52
62
30
52
62
CP
30
57
67
35
65
75
Yo - Y15
20
52
60
30
52
60
TI- T4
lEN
Notes:
32. tsx and tIIX referenced on the waveforms are looked up on this table
by x = line number on the left. Ex: lsI = 13 ns for -53 ns devices.
33. CY7C91170nly.
34. Timing for immediate instruction for first cycle.
40
65
79
22
26
29
15
26
29
33
33
39
20
26
29
35. CY7C9115 and CY7C9116 only.
36. Y = D for CY7C9117.
37. TA = - 55°C to + 125°C, Vee = 4.5Vt05.5V,CL= 50pR
6-114
CY7C9115
CY7C9116/CY7C9117
'~~PRESS
-.F
SEMICONDUClDR
Enable/Disable Times[31] (ns)
Enable
From Input
Speed (ns)
I
ThOutput
I
OEy
I
OET
Disable
TpZL
TPZH
TpLZ
TpHZ
40
65
79
40
65
79
40
65
79
40
65
Yo - Y15
18
22
25
18
22
25
18
18
25
18
18
25
TI- T4
18
18
20
18
18
20
15
15
20
15
15
20
Clock and Pulse Requirements (ns)
Input
Minimum Low Time
Speed (ns)
40
65
CP
15
20
Minimum High Time
79
40
65
79
25
15
15
15
15
15
15
DLE
lEN
15
79
15
15
Set-Up and Hold Times (ns)
Input
Note 38
With
Respect
Th
Speed (ns)
IDGH-to-LOW'Ihmsition
Set-Up
LOW-to-IDGHlhmsition
Hold
Set-Up
40
65
79
40
65
79
1
10- 4
(RAM Addr)
CP
12
12
12
0
1
1
2
10 - 14
(RAM Addr)
CPIli
lEN
5
7
7
3
•
40
65
10 - 115 (Data)
CP
10 - 14
(RAM Addr)[33]
lEN
15[34]
25
27[34]
5[34]
12
12[34]
5
10 - 115 (Instr)[35]
CP
15[34]
25
27[34]
5[34]
12
12[34] 45
6
IEN[33]
CP
43
79
•
Do Not Change
4
Hold
56
65
40
65
Comments
79
SingleAddr
(Source)
0
0
0
0
0
0
1WoAddr
(Immediate)
56
65
0
2
2
8
8
8
1WoAddr
(Immediate)
Disable
7
lEN HIGH
CP
8
lEN LOW
CP
9
IENLOW
CP
10
SRE
y[36]
CP
10
10
12
0
1
1
11
CP
39
45
53
0
0
0
12
y[36]
DLE
13
DLE
CP
20
46
54
0
0
0
5
5
5
10
7
7
7
7
0
7
3
7
Notes:
38. tsx and tHX referenced on the waveforms are looked up on this table
by x = line nnmber on the left. Ex: tSI = 24 ns for - 79 ns devices.
6-115
3
3
1WoAddr
(Destination)
10
12
0
2
2
0
3
3
Enable
Note 34
3
3
•
CY7C9115
CY7C9116/CY7C9117
£~PR£$S
~,
SEMlCOIDUCfOR
Switching Waveforms
Single Address Access Timing[39j
ONE CYCLE - - - - + I
CP
lEN
DISABLE
WRITE
lEN
ENABLE
WRITE
DLE
D
(INPUl)
' - - - - - - Isl0 ----_14--..1
709115-18
Double Address Access Timing
1----
ONE CYCLE
CP
709115-19
Note:
39_ If thll is satisfied, thlO need not be satisfied.
6-116
CY7C9115
CY7C9116/CY7C9117
~
~~PRESS
~_'J SEMICONDUcrOR
Switching Waveforms (continued)
One-Address Immediate Instruction Cycle Timing
1st CYCLE
CP
EXECUTES
INSTRUCTION
10-15 =
DATA
7C9115-20
'l\vo-Address Immediate Instruction Timing (7C9117 Only)
•
o
a
9
7C9115-21
6-117
-PRESS
~
CY7C9115
CY7C9116/CY7C9117
~j,. SEMICONDUCTOR
1YPical DC and AC Characteristics
NO~ZEDSUPPLYCURRENT
NO~EDSUPPLYCURRENT
vs.AMBIENT TEMPERATURE
vs SUPPLYVOLTAGE
1.4
1.2
01.0
.E
V
0
w
~
«
0.8
V
./
:::;:
a:
0
z
0.6
/
0.4
4.0
/
13
1.2
~
1.0
a:
~
0.8
VIN= 5.0V
TA = 25°C
I
6.0
5.0
5.5
4.5
SUPPLY VOLTAGE
0 1.1
w
a:
u.
0
w
1.0
::J 0.9
«
:::;:
a:
0
z
iTI
25
125
20
~
TA = 25°C
o
0.0
1.4
iTI
~
1.2
r-----
140
120
~ 80
5
60
o
40
20
~
-55
6.0
M
25
NO~ZEDOUTPUTDELAY
5
is
I!:
fil
~
1.6
1.5
1.4
13
1.4
./
1.2
0
w
~
N
:::;:
I
V
o
a:
0
z
Vcc=5.0V _
TA = 25°C
I
200
1.0
0.0
400
600
2.0
3.0
OUTPUT VOLTAGE M
FREQUENCY
/
/
~
1.2
~
V-
~ 1.1
a:
oz
1.0
Vcc= 5.0V
TA = 25°C
/
NO~DIcC
VS.
1.6
1.3
/
AMBIENTTEMPERATURE (OC)
vs.OUTPUTWADING
~
w
o
/
o
125
./"'"
./
() 100
Vcc=5.0V
/
1.0
/
I
0.6
CAPACITANCE (pF)
o
1/
5
10
V
Vcc=5.5V
TAMB = 25°C
VIN=0.3V
0.8
800 1000
15
I
I
I
20
25
25
FREQUENCY (MHz)
6-118
4.0
M
L
:.:
1.0
......
3.0
2.0
./
:::l
IS 0.8
5.5
SUPPLY VOLTAGE
1.0
""'-
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
« 180
0.6
5.0
""'-
10
I-
z
4.5
......
.§. 160
o
/
'"
OUTPUT VOLTAGE
:::l
0.8
0.7
4.0
@
I
Vcc= 5.0V
TA = 25°C
~ o
@
If
V
30
5
iJ
V
N
~
NO~ZEDFREQUENCY
,.--
:::l
""'-
50
:::l
1.6
w 1.2
~
w 40
vs. AMBIENT TEMPERATURE
SUPPLY VOLTAGE
1.3
iJz
60
AMBIENTTEMPERATURE (0G)
NORMAL~EDFREQUENCY
VS.
~
()
~
M
70
:::l
~ r--...
0.0
-55
I
~
Vcc= 5.5V
VIN=5.0V
o
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
VB.
35
7C9115-22
4.0
CY7C9115
CY7C9116/CY7C9117
~
=-~
~'-CYPRESS
~,
SEMICONDUCTOR
Cross References for Set-Up and Hold Times
IDGH-to-LOW
'ftansition
Note 40
Set-Up
Hold
1
tS1
th1
2
tS2
LOW-to-HIGH
'fransition
Set-Up
Hold
th2
3
4
tS5
thS
5
tS4
th4
tS3
th3
tS13
th13
6
7
th6
tS7
th7
8
9
th8
tS8
tS14
th14
10
tS9
th9
11
ts10
th10
tS12
th12
12
tS11
II
o
C;
th11
13
9
Notes:
40. Refer to Set-Up and Hold times shown on pages 25 and 26.
Ordering Information
Speed
(ns)
35
45
65
Speed
(ns)
35
40
45
65
79
Ordering Code
CY7C9115 - 35JC
CY7C9115 -45JC
CY7C9115-65JC
Ordering Code
CY7C9116-35DC
CY7C9116- 35JC
CY7C9116-35LC
CY7C9116-40DMB
CY7C9116-40LMB
CY7C9116-45DC
CY7C9116-45JC
CY7C9116-45LC
CY7C9116-65DC
CY7C9116-65JC
CY7C9116-65LC
CY7C9116-65DMB
CY7C9116-65LMB
CY7C9116-79DMB
CY7C9116-79LMB
Package
'iYpe
J69
J69
J69
Package
lYPe
D28
J81
L69
D28
L69
D28
J81
L69
D28
J81
L69
D28
L69
D28
L69
Operating
Range
Speed
(ns)
Commercial
35
40
Operating
Range
45
Commercial
65
Military
Commercial
79
Military
6-119
Ordering Code
CY7C9117-35GC
CY7C9117-35JC
CY7C9117-35LC
CY7C9117 -40GMB
CY7C9117 -40LMB
CY7C9117-45GC
CY7C9117 -45JC
CY7C9117-45LC
CY7C9117-65GC
CY7C9117-65JC
CY7C9117-65LC
CY7C9117-65GMB
CY7C9117 -65LMB
CY7C9117-79GMB
CY7C9117-79LMB
Package
lYPe
G68
J81
Operating
Range
Commercial
LSI
G68
Military
LSI
G68
J81
Commercial
LSI
G68
J81
Commercial
LSI
G68
LSI
G68
LSI
Military
·1
CY7C9115
CY7C9116/CY7C9117
~r,~NDtaoR
MrnUTARYSPECllITCATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIH
VILMax.
IIX
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
loz
Isc
ICC(Ql)
Icc(Max.)
Switching Characteristics
Parameters
Subgroups
10 - 14 (Addr)
10 - 115 (Data)
10 - 115 (Instr)
DIE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
Tl- T4
CP
Yo - Y25
lEN
DEy
DET
CP
Document#: 38-000S7-C
6-120
"INFO
SRAMs
I'
".
PROMs
&J1
,
;~
PlDs
II
FIFOs
II
lOGIC
II
COMM
RISC
MODULES
,.
ECl
BUS
MILITARY
TOOLS
QUALITY
PACKAGES
In
-'"---
z·
-=-._~PRFSS
Section Contents
SEMICONDUCTOR
Communication Products
Device Number
CY7B921
CY7B922
CY7B923
CY7B931
CY7B932
CY7B933
CY7B991
CY7B992
Page Number
Description
7-1
H01Link 'ftansmitter/Receiver
7-1
HOTLink 'ftansmitter/Receiver
7-1
HOTLink 'ftansmitter/Receiver
7-1
H01Link Transmitter/Receiver
HOTLink Transmitter/Receiver ................................................. . 7-1
HOTLink Transmitter/Receiver ................................................. . 7-1
Programmable Skew Clock Buffer (PSCB) ........................................ . 7-26
Programmable Skew Clock Buffer (PSCB) ....................................... .. 7-26
•
:E
:E
o
o
PRELIMINARY
CYPRESS
SEMICONDUCTOR
HOTLink@)
Transmitter/Receiver
Features
Functional Description
•
•
•
•
•
•
•
•
•
The CY7B92X HOTLink Transmitterand
CY7B93X HOTLink Receiver are pointto-point communications building blocks
that transfer data over high-speed serial
links (fiber, coax, and twisted pair) at 130
to 310 Mbits/second. Figure 1 illustrates
typical connections to host systems or controllers.
Eight bits of user dataorprotocolinformation are loaded into the HOTLink transmitter and are encoded. Serial data is
shifted out of the thrcc differential Pseudo
ECL (PECL) serial ports at the bit rate
(which is 10 times the byte rate).
The HOTLink receiver accepts the serial
bit stream at its differential line receiver inputs, and using a completely integrated
PLL clock synchronizer recovers the timing information necessary for data reconstruction. The bit stream is deserialized,
•
•
•
•
•
Fibre Channel compliant
IBMESCON@Jcompliant
SB/IOB-coded or to-bit unencoded
130- to 310-Mbps data rate
TTL synchronous I/O
No external PLL components
'friple ECL lOOK serial outputs
Dual ECL lOOK serial inputs
Low power: 350 mW max (Tx),
500mWmax (Rx)
Compatible with fiber optic modules,
coaxial cable, and twisted pair media
Built-In Self-Test
Single +5V supply
2S-pinDIP/PLCC/LCC
O.S" BiCMOS
CY7B92X Transmitter Logic Block Diagram
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
decoded, and checked for transmission errors. The recovered byte is presented in
parallel to the receiving host along with a
byte rate clock.
The 8B/lOB encoder/decoder can be
disabled in systems that already encode or
scramble the transmitted data. I/Os are
available to create a seamless interface
with both asynchronous FIFOs (i.e.,
CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern
generatorand checker allows testing of the
transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
H OTLink devices are ideal for a variety of
applications where a parallel interface can
be replaced with a high-speed point-topoint serial link. Applications include interconnecting workstations, servers, mass
storage, and video transmission equipment.
CY7B93X Receiver Logic Block Diagram
RF
RP ENN
ENA
NB
FOTO
INA
INB
CLOCK
GENERATOR
REFCLK _ _ _ _-oj
MODE
MODE . .
BISTEN . .
BISTEN
B921~1
se/D (08) 8921-2
go
a::
XW
20915
a::
a.
"'~
mw
lIlo
.... w
a::
SERIAL LINK
HOST
HOST
Figure 1. HOTLink System Connections
HOTLinkis a registered trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
7-1
8921-3
•
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
CY7B93X Receiver Pin Configurations
CY7B92X Transmitter Pin Confagurations
DIP
·ThpView
DIP
ThpView
OutBOutCOulC+
VCCN
BISTEN
GND
MODE
RP
VcCQ
SVS(Dg)
D7
D6
Ds
D4
InAInA+
OutB+
OutA+
OutAFOTO
ENN
ENA
Vcca
CKW
GND
SC/D (Da)
Do
D1
D2
D3
8921-1
InB+
InBMODE
SI
Vcca
SO
CKR
VCCN
GND
AlB
BISTEN
RF
GND
RDY
GND
VCCN
RVS (Og)
07
06
Os
04
4
6
9
SC/D(Oa)
00
01
02
03
8921-3
PLCC
PLCC
ThpView
ThpView
+ I I ++ I
ti~~!!l!!l~~
>°000000
BISTEN
GND
MODE
RP
VCCQ
SVS (Dg)
D7
6
7
8
9
"""nrmm'i+'nn--.r
COIO"="C")N...-O
CCCCCCC
FOTO
ENN
ENA
Vcca
CKW
GND
SC/D (Da)
RF
GND 6
7B931
RDY
7B932
GND
7B933
VCCN 9
21
RVS(09)
07 "1..:.:..r4T~-i2rT,.,.,.rr:r
co Il)v
8921-2
C")
(\I
....
SI
VCCQ
SO
CKR
VGCCN
;ND
SC/D (Oa)
0
0000000
8921-4
Selection Guide
7B921
7B931
130-170
13-17
'Ihmsmitter
Receiver
'ItansmissionRate (Mbits/sec)
'ItansmissionRate (Mbytes/sec)
Maximum Ratings
7B922
7B932
170-240
17-24
7B923
7B933
240-310
24-31
Operating Range
(Above which the useful life may be impaired. Foruserguidelines,
nottested.)
Storage Temperature ..................... - 65 C to + 150 C
Ambient Temperature with
Power Applied. . . . . .. . . . . . . . . . . .. .. . . . .. - 55 C to + 125 C
Supply Voltage to Ground Potential. . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage ....................... -O.5Vto +7.0V
Output Current into TLL Outputs (LOW) ............ 30 rnA
Output Current into ECL outputs (HIGH) . . . . . . . . .. -50 rnA
Static Discharge Voltage ......................... >2001V
(per MIL-SID-883, Method 3015)
Latch-UpCurrent ............................. >200rnA
7-2
Range
Commercial
Industrial
Military
Ambient
Temperature
O°Cto +70°C
Vee
5V± 10%
-40°Cto +85°C
5V ± 10%
- 55°C to +125°C
Case Temperature
5V ± 10%
~
~~
~=CYPRESS
~.iF' SEMlCONDUCfOR
PRELIMINARY
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
Pin Descriptions
CY7B92XHOTLink 'fioansmitter
Name
Description
I/O
00-7
TIL In
Parallel Data Input. Data is clocked into the 1tansmitter on the rising edge of CKW if ENA is LOW (or
on the next rising CKW with ENN LOW).IfENA and ENN are HIGH, a Null character (K28.5) is sent.
SC/O
(08)
TIL In
SVS
(09)
TIL In
Special CharacterIDataSelect.A HIGH on SCID when CKW rises causes the transmitter to encode the
pattern on 00-7 as a control code (Special Characte.!1, while a LOW causes the data to be coded using the
8B/10B data alphabet. When MODE is HIGH, SCID (08) acts as 08 input.
Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is e!!..coded and sent while
the data on the parallel inputs is ignored. IfSVS is LOW, the state of 00-7 and SC/O determines the code
sent. In BIST mode, SVS ov~rides the BlST generator and forces the transmission of a Violation code.
When MODE is HIGH, SC/O (09) acts as 09 input.
ENA
TTL In
ENN
TIL In
CKW
TIL In
Enable Parallel Data. IfENA is LOW on the rising edge of CKw; the data is loaded, encoded, and sent.
IfENA is HIGH, the data inputs are ignored and the Transmitterwill insert a Null character (K28.5) to fill
the sbace between user data. ENA may be held HIGH/LOW continuously or it may be pulsed with each
data yte to be sent.IfENA is being used for data control, ENN will normally be strapped HIGH, but can
be used for BIST function control.
Enable Next Parallel Data. IfENN is LOW, the data appearing on 00-7 at the next rising edge of CKW
is loaded, encoded, and sent. IfENN is HIGH, the data appearing on 00-7 at the next rising edge ofCKW
will be ignored and the 1tansmitterwill insert a Null character to fill the space between user data. ENN
may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. IfENN is being used
for data control, ENA will normally be strapped HIGH, but can be used for BlST function control.
Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the highspeed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW must
be connected to a crystal controlled time base that runs within the specified frequency range of the 1tansmitter and Receiver.
FOTO
TTL In
Fiber Optic Transmitter Off. FOTO determines the function of two of the three ECL transmitter output
pairs. If FOTO is LOW, the data encoded by the 1tansmitter will appear at the outputs continuously. If
FOTO is HIGH, OUTA± and OUTB± are forced to their "logic zero" state (OUT+ = LOW and
OUT- = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is unaf~ected by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testmg.
OUTA±
OUTB±
OUTC±
ECLOut
DifferentialSerial Data Outputs. These ECL lOOK outputs ( +5V referenced) are capable of driving terminatedtransmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs can be
wired to Vce to reduce Gower if the output is not required. OUTA± and OUTB± are controlled by the
level on FOTO, and wil remain at their "logical zero" states when FOTO is asserted. OUTC± is unaffected by the level on FOTO. (OUTA + and OUTB+ are used as a differential test clock input while in
Test mode.)
MODE
3-Level
In
BlSTEN
TTL In
RP
TIL Out
Encoder Mode Select. The level on MODE determines the encoding method to be used. When wired
LOW, MODE selects 8B/1OB encoding. When wired HIGH, data inputs bypass the encoder and the bit
pattern on 00-7, 08, and 09 goes directly to the shifter. When left floating (internal resistors hold the
input at Vcd2) the internal bit-clock generator is disabled and OUTA + /OUTB+ become the differential bit clock to be used for factory test. In typical applications MODE is tied HIGH or LOW.
Built-In Self-Test Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends
an alternating 1-0 pattern (010.2 or 021.5). When either ENA or ENN is set LOW the transmitter begins a repeating test sequence that allows the 1tansmitter and Receiver to work together to test the function ofthe entire link. In normal use this input is held HIGH or wired to V ce. The BlST generator is a
free-runningpattern generator that need not be initialized, but if required, the BISTsequence can be initialized by momentarily asserting SVS while BISTEN is LOW.
Read Pulse. RP is a 70% LOWduty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is inde~dent
of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will
remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BlST loop.
VCCN
Power for output drivers.
VCCQ
GND
Ground.
Power for internal circuitry.
7-3
II
::E
::E
o
o
.-~
~.CYPRF.SS
~_, SEMICONDUcroR
PRELIMINARY
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
CY7B93X HOTLinkReceiver
Name
Description
I/O
00-7
TfLOut
00-7 Parallel Data Output. 00-7 contain the most recently received data. These outputs change synchronouslywith CKR.
SCID(08)
TfLOut
RVS(09)
TfLOut
Special CharacterlData Select. SCID indicates the context of received data. HIGH indica~s- a Control
(Special Character) code, LOW indicates a Data character. When MODE is HIGH, SCID acts as 08
output.
Received Violation Symbol. A HIGH on RVS indicates that acode rule violation has been detected in the
received data stream. A WW shows that no error has been detected. In BIST mode, a WW on RVS
indicatescorrect operation of the nansmitter,Receiver, and link on a byte-by-byte basis. When MODE
is HIGH, RVS acts as 09 output.
RDY
TIL Out
Data Output Ready. AWW pulse on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted
by the transmitter as a pad between data inputs). In BISTmode RDY will remain LOW for all but the last
byte of a test loop and will pulse HIGH one byte time per BlST loop.
CKR
TfLOut
Clock Read. This~ rate clock output is phase and frequency aligned to the incoming serial datastream.
RDY, 00-7, SCID (08), and RVS (09) all switch synchronously with the rising edge ofthis output.
INA±
INB±
DiffIn
Differential Serial Data Inputs. The differential signal at the receiver end of the communication link is
connectedto the differential pairs INA± or INB±. Either the INA pair or the INB pair can be used as the
main data inpi!! and the other can serve as a loop-back channel or as an alternative data input selected by
the state of AlB. INB ± is used as the test clock while in Test mode.
AlB
ECLin
SI
ECLin
Serial Datajnput Select. This ECL lOOK (+5V referenced) input selects INA or INB as the active data
inIDlt. If AlB is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If
AlB is LOW INB is selected.
Status In. The ECL lOOK ( + 5V referenced) signal appearing on SI is translated to a TTL signal at SO. SI
is typically used to translate the Carrier Detect output from a fiber optic receiver.
SO
TTL Out
Status Out. SO is the TfL translated output of S1 It is typically used to translate the Carrier Detect output from a fiber optic receiver.
RF
TIL In
REFCLK
TfLIn
Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. When RFis held Ww, thereframingloglc is disabled. The incoming data stream is then continuously de-serialized and decoded using byte
boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to reframe the data erroneously.
Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLKmust be connected to a crystal-controlled time base that runs within the frequency limits ofthe
TxiRxpair, and the frequency must be the same as the transmitter CKW frequency (within CKW ±O.l %).
MODE
TfLIn
BISTEN
TfLIn
VCCN
VCCQ
GND
Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When
tied LOW, MODE selects 8B/l@decoding. When tied HIGH, registered shifter contents bypass the decoder and are sent to 00-7, SCID and RVS directly. When leftfloating(internalresistorshold the MODE
pin at Vcd2) the internal bit clock generator is disabled and INB± becomes the bit rate test clock to be
used for factory test. In typical applications, MODE is tied HIGH or LOW.
Built-InSelf-Thst Enable. When BISTEN is LOW the Receiver awaits a DO.O (sent once per BlSTIoop)
character and begins a continuous test sequence that tests the functionality of the nansmitter, the Receiver, and the link connecting them. In BIST mode the status of the test can be monitored with RDY and
RVS outputs. In normal use BISTEN is held HIGH or wired to Vce.
Power for output drivers.
Power for internal circuitry.
Ground
7-4
.....::=-....
.
,~PRFSS
PRELIMINARY
- . F SEMICONDUCTOR
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
cludedin the Clock Generator and is not affected by signal levels or
timing at the input pins.
OutA, OutB, OutC
CY7B92X HOTLink Transmitter Block Diagram
Description
Input Register
The Input register holds the data to be processed by the HOTLink
transmitter and allows the input timing to be made consistent with
a standard FIFOs. The Input register is clocked by CKW and
loaded with information on the 00-7, SCID (Os), and SVS (09)
pins. Two enable inputs (ENA and ENN) allow the user to choose
when data is to be sent. Asserting ENA (Enable, LO~uses the
inputs to be loaded on the rising edge of CKW. If ENN (Enable
Next, LOW) is asserted when CKW rises, the data present on the
inputs will be loaded into the input register on the next rising edge
of CKw. These two inputs allow proper timing and function for
compatibility with either asynchronous FIFOs or clocked FIFOs
without external logic, as shown in Figure 2.
In BIST mode, the Input register becomes the signature pattern
generatorby logically converting the parallel input register into a
Linear FeedbackShift Register(LFSR). When enabled, thisLFSR
will generate all possible input patterns in a predictable but pseudo-random sequence that can be matched to an identical LFSR in
the Receiver.
Encoder
The Encoder transforms the input data held by the Input register
into a form more suitable fortransmission on aserial interface link.
The code used is specified by ANSI X3T9.3 (Fibre Channel) and
the IBM ESCON channel (code tables are at the end of this datasheet). The eight 00-7 data inputs are converted to either a DATA
symbol or a Special Character, depending upon the state of the
SCID input. If SCID is HIGH, the data inputs represent a control
code and is encoded using the Special Character code tables. If
SeID is LOW, the data inputs are converted using the DATA code
table. If a byte time passes with the inputs disabled, the Encoder
will output a Special Character Comma K28.5 (or SYNC) that will
maintain link synchronization. Strings of SYNC will be decoded in
the Receiver as Null characters, thus simplifying the system control
logic for FIFO interfaces. SVS input forces the transmission of a
specified Violation symbol to allow the user to check error handling system logic in the controller.
The 8B/lOB coding function of the Encoder can be bypassed for
systems that include an external coder or scrambler function as
part of the controller. This bypass is controlled by the MODE select pin. When in bypass mode, 00-7, scio (Os), and SVS (09)
become the ten inputs to the Shifter.
Shifter
The Shifter accepts paraIlel data from the Encoder once each byte
time and shifts it to the serial interface output buffers using a PLL
multiplied bit clock that runs at ten (10) times the byte clock rate.
Timing for the parallel transfer is controlled by the counter in-
The serial interface ECL output buffers (lOOK referenced to +5v)
are the drivers for the serial media. They are all connected to the
Shifter and contain the same serial data. Two of the output pairs
(OUTA± and OUTB±) are controllable by the FOTO input and
can be disabled by the system controller to force a logical zero (i.e.,
"light off") at the outputs. The third output pair (OUTC±) is not
affected by FOTO and will supply a continuous data stream suitable for loop-back testing of the subsystem.
OUTA± and OUTB± will respond to FOTO input changes within
a few bit times. However, since FOTO is not synchronized with the
transmitter data stream, the outputs will be forced off or turned on
at arbitrary points in a transmitted byte. This function is intended
to augment an external laser safety controller and as an aid for Receiver PLL testing, and thus need not be synchronized.
In wire-based systems, control of the outputs may not be required,
and FOTO can be strapped LOW. The three outputs are intended
to add system and architectural flexibility by offering identical serial bit streams with separate interfaces for redundant connections
or for multiple destinations. Unneeded outputs can be wired to
Vee to disable and power down the unused output circuitry.
Clock Generator
Theclockgenerator is an embedded phase-locked loop (PLL) that
takes a byte-rate reference clock (CKW) and multiplies by ten (10)
to create a bit rate clock for driving the serial shifter. The byte rate
reference comes from CKW, the rising edge of which clocks data
into the Input register. This clock must be a crystal referenced
pulse stream that has a frequency between the minimum and maximum specified for the HOTLink 'Il'ansmitter/Receiverpair. (Each
'Il'ansmit/Receive pair; 7B9211931, 7B922/932, 7B923/933 have a
specified range of operating frequencies.) Signals controlled by
this block form the bit clock and the timing signals that control internal data transfers between the Input register and the Shifter.
The read pulse (RP) is derived from the feedback counter used in
the PLL multiplier. It is a byte-rate pulse stream with the proper
phase and pulse widths to allow transfer of data from an asynchronous FIFO. Pulse width is independent of CKW duty cycle, since
proper phase and duty cycle is maintained by the PLL. The RP
pulse stream will insure correct data transfers between asynchronous FIFOs and the transmitter input latch with no external logic.
ThstLogic
Thst logic includes the initialization and control for the Built-In
Self-lest (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic to properly select the data encoding.
Thst logic is discussed in more detail in the CY7B92X HOTLink
'Il'ansmitterOperating Mode Description.
7-5
:E
:E
o
o
-
. ·rCYPRESS
PRELIMINARY
_ , SEMICOIDUCTOR
CY7B93X HOTLink Receiver Block Diagram
Description
Differential Inputs
This pair of differential line receivers are the inputs for t~ serial
data stream. INA± or INB± can be selected with the NB inpu!:,
INA± is selected with AlB HIGH and INB± is selected with NB
LOW. The threshold of AlB is compatible with the ECL l00Ksignals from ECL fiber optic interface modules. The differential
threshold of INA± and INB± will accommodate wire interconnect with filtering losses or transmission line attenuation greater
than 20 db (VDIP ~ SOmv) or can be directly connected to fiber optic interface modules (any ECL logic family, not limited to ECL
lOOK) with up to 1.2 volts of differ~ntial signal. ~ecommo~m~de
tolerance will accommodate a WIde range of sIgnal termmation
voltages. The highest mGH input that can be tolerated is VIN =
Vee, and the lowest LOW input that can be interpreted correctly
is VIN = GND+2.5Y.
ECL-TI'L 1hmslator
This positive-referenced ECL-to-TTL translator is I?r~vided to
eliminate external logic between an ECL fiber-optIc Interface
module "carrier detect" output and the TTL input in the control
logic. The input threshold is compatible with ECL lOOK levels
(+SVreferenced). It can also be used as part ofthe link status indication logic for wire connect~d systems.
Clock Sync
The Clock Synchronizer function is performed by an embedded
phase-Iockedloop (PLL) that tracks the frequency of the incoming
bit stream and aligns the phase of its internal bit rate clock to the
serial data transitions. This block contains the logic to transfer the
data from the Shifter to the Decode register once every byte. The
counterthat controls this transfer is initialized by the Frameriogic.
CKR isa buffered output derived from the bit counter used to control Decode register and Output register transfers.
Clock output logic is designed so that when reframing causes the
counter sequence to be interrupted, the period and pulse width of
CKR will never be less than expected. Reframingmay stretch the
period of CKR by up to 90%, and either CKR Pulse Width HIGH
or Pulse Width LOW may be stretched, depending on when reframe occurs.
The REFCLK input provides a byte-rate reference frequency to
improve PLLacquisition time andlimitunlockedfrequencyexcursions of the CKR when no data is present at the serial inputs. The
frequency of REFCLK is required to be within ±0.1 % of the frequencyofthe clock that drives the transmitter CKW pin.
Framer
Framer logic checks the incoming bit stream for the pattern that
defines the byte boundaries. This combinatorial logic filter looks
for the X3T9.3 symbol defined as a Special Character Comma
(K28.5). When it is found, the free-running bitcounterin the Clock
Sync block is synchronously reset to its initial state, thus framing
the data correctly on the correct byte boundaries. The Fibre Channel specification optionally allows this lO-bitpattern (0011111000
or 11 00000111) to be detected using only a 7-bit detector (but restricts usage of other Data and Special Character codes). Framer
logic in the Receiver will completely decode all ten (10) bits of
K28.5 to reframe, and thus remove the limitations on code sequences.
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
The Framer can be inhibited by holding the RF input LOW. When
RF rises, RDY will be inhibited until a K28.S has been detected,
after which RDY will resume its normal function.
Shifter
The Shifter accepts serial inputs from the Differential inputs one
bit at a time, as clocked by the Clock Sync logic. Data. is transferred
to the Framer on each bit, and to the Decode regISter once per
byte.
Decode Register
The Decode register accepts data from the Shifter once per byte as
determinedby the logic in the Clock Sync block It is presented to
the Decoder and held until it is transferred to the output latch.
Decoder
Parallel data is transformed fromANSI X3T9.3 8B/lOBcodes back
to "raw data" in the Decoder. This block uses the standard decoder
patterns shown in the Valid Data Characters and Valid Special
Character Codes and Sequences sections of this datasheet. Data
patterns are signaled by a LOW on the SC/D output anJ! Special
Character patterns are signaled by a HIGH on the SC/D output.
Unused patterns or disparity errors are signaled as errors by a
mGH on the RVS output and by specific Special Character codes.
Output Register
The Output register holds the recovered data (QO-7, SCIf?, and
RVS) and aligns it with the recovered byte clock (CKR). ThIs synchronizationinsures proper timing to match a FIFO interfaa: or
other logic that requires glitch free and specified output behavIOr.
Outputs are changed synchronously with the rising edge of CKR.
In BISTmode, this register becomes the signature pattern ge~era
tor and checker by logically converting the parallel output regIster
into a Linear Feedback Shift Register (LFSR) pattern generator.
When enabled, this LFSR will generate all possible code patterns
ina predictable but pseudo-random s~quence that can be m~tche?
to an identical LFSR in the 'Il'ansmltter. When synchromzed, It
checks each byte in the Decoder with each byte generated by the
LFSR and shows errors at RVS. Patterns generated by the LFSR
are compared after being buffered to the output J(ins and .then fed
back to the comparators, allowing test of the entIre receIve function.
In BIST mode the LFSR is initialized by the first occurrence of the
transmitter BIiiT loop start code DO.O (DO.O is sent only once per
BIST loop). Once the BIST loop has been started, RVS will be
HIGH for pattern mismatches between the re~ive? sequence ~d
the internally generated sequence. Code rule VIolatIOns or runnmg
disparityerrors that occur as part of the BIST loop will not cause an
error indication. RDY will pulse HIGH once per BIST loop and
can be used to check test pattern progress. If it is suspected thatthe
receiver pattern generator has lost sync with t~~ ~~smitter BI~T
pattern, the receiver BIST generator can be remltiallZed by leaVIng
andre-entering BISTmode.
ThstLogic
'lest logic includes the initialization and control for the Built-In
Self-'lest (BIST) generator, the multiplexer for Test mo?e. clo~k
distribution and control logic for the decoder. Test logIC IS dlscussedinm~re detail in the CY7B93X HOTLink ReceiverOperatingMode Description.
7-6
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
~
-~PRESS
--
~.!!'"
PRELIMINARY
SEMlCONDUCTOR
CY7B92X/CY7B93X Electrical Characteristics Over the Operating Rangel!]
Parameter
Description
Min.
Thst Conditions
Max.
Units
0.45
V
-15
-90
rnA
2.0
Vee
V
'fransmitter TIL·Compatible Pins: DO-7' S~/D, SV~NA, ENN, CKW; FOTO, BISTEN, RP
Receiver TTL- Compatible Pins: QO-7' SC/D, RVS, RDl; CKR, REFCLK, RF, BISTEN, SO
VOlIT
Output HIGH Voltage
IOH=-2rnA
VOLT
Output LOW Voltage
IOL=4rnA
lOST
Output Short Circuit Current
VOUT=OV[2]
VIlIT
Input HIGH Voltage
VILT
Input LOW Voltage
IIHT
Input HIGH Current
VIN= Vee
lILT
Input LOW Current
VIN = O.OV
2.4
V
- 0.5
0.8
V
-10
+10
-500
tAA
tAA
'fransmitter ECL-Compatible Output Pins: OUTA+, OUTA-, OUTB+, OUTB-, OUTC+, OUTCVOHE
Output HIGH Voltage (Vee referenced)
Load = 50 ohms to Vee - 2V
Vee-1.03
Vee-0.88
V
VOLE
Output LOW Voltage (Vee referenced)
Load = 50 ohms to Vee - 2V
Vee-1.81
Vee-1.63
V
V
Receiver ECL·Compatible Input Pins: AlB, SI
VIHE
Input HIGH Voltage
Vee-1.17
Vee- 0.88
VILE
Input LOW Voltage
Vee-1.8I
Vee-1.48
V
IIHE
Input HIGH Current
VIN = VIHE Max.
+500
lILE
Input LOW Current
VIN = VJLLMin.
tAA
tAA
Differential Line Receiver Input Pins: INA +, INA -, INB+, INBInput Differential Voltage
VDIFF
I(IN+) - (IN-) I
VIHH
Highest Input HIGH Voltage
VILL
Lowest Input LOW Voltage
+0.5
50
1200
mV
Vee
V
2.5
V
Miscellaneous
leCT
Transmitter Power Supply Current
Vee = Max., TA = Max.,
Freq. = Max. (One ECLoutput pair
loaded with 50 ohms to
Vee - 2.0V, others tied to Ved
TBD
rnA
leeR
Receiver Power Supply Current
Vee = Max., TA = Max.,
Freq. = Max.
TBD
rnA
Capacitance [3]
Parameters
Thst Conditions
Description
InputCapacitance
TA = 25°C,fo = 1 MHz, Vee = 5.0V
Notes:
1. See the last page of this specification for Gronp A subgroup testing
information.
2. Thsted on one output at a time, output shorted for less than one se·
cond, less than 10% duty cycle.
3.
7-7
Thsted initially and after any design or process changes that may affect
these parameters.
•
:::E
:::E
oo
# ==:~PRffiS
~,
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
SEMICONDUCTOR
AC Test Loads and Waveforms
R1 = 9620
R2 = 5100
Rl= 500
Cl<30pF
(Includes fixture and
probe capacitance)
Cl < 5pF
(Includes fixture and
probe capacitance)
(a) TTL AC Thst Load[4]
(b) ECL AC Thst Load[4]
3.0V
VIHE
V IHE
3.0V
2.0V
80%
1.0V
GND
VILE
VILE
.5.2 ns
B921-7
6921·6
(c) TIL Input Test Waveform
7B921/2/3 Transmitter Switching Characteristics
(d) ECL Input Thst Waveform
OvertheOperatingRangeC1]
7B921
Parameters
Description
8921-5
7B922
7B923
Min.
Max.
Min.
Max.
Min.
Max.
Units
tcKW
Write Oock Cycle
56
76
42
57
32
43
ns
tB
Bit Timel5]
5.6
7.6
4.2
5.7
3.2
4.3
ns
tcPWH
CKW Pulse Width HIGH
9
9
9
ns
tcPWL
CKW Pulse Width LOW
9
9
9
ns
tso
Data Set-Up Timel6]
5
5
5
ns
tHO
Data Hold Timel6]
0
0
0
ns
tSEND
Enable Set-U~ Time (to
capture data)[
5
5
5
ns
tSENP
Enable SeHJQ....Time (to
assure correct RP)[8]
71!.tB+4
71!.tB+4
71f.tB+4
ns
tHEN
Enable Hold Time
tPOR
Read Pulse Aiignmentl9]
tpPWH
Read Pulse HIGH[9]
3tB-3
3tB-3
3tB-3
ns
tpPWL
Read Pulse LOW[9]
7tB-3
7tB-3
7tB-3
ns
0
(-\4tB -3)
0
(+\4tB +3)
Notes:
4. Cypress uses constant current (ATE) load configurations and forcing
functions. This figure is for reference only.
5. Transmitter tB is calculated as tCKw/lO. The byte rate is one tenth of
the bit rate.
6. Data includes DO-7, SC!D (DB), and SVS (D9).
7.
8.
9.
7-8
(-\4tB -3)
0
(+\4tB +3)
(-\4tB -3)
ns
(+\4tB +3)
ns
tSEND minimum tim~assures correct Data load on rising edge of
CKW, but not proper RP functiou or timi!!g.
tSENP minimum timing insures correct RP pulse widtb and correct
Data load on risiug edge of CKW.
Loading on RP pin is.5.2 rnA and .5.15 pF.
.::4
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
~=CYPRESS
. ' SEMlCamucroR
7B931/2/3 Receiver Switching Characteristics Over the Operating Range[l]
7B931
Parameters
7B932
7B933
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tCKR
Read Clock Period (No Serial Data Input), REFCLK as Referencel lO)
-1
+1
-1
+1
-1
+1
%
tB[l1]
Bit Time
5.6
7.6
4.2
5.7
3.2
4.3
tCPRH
Read Clock Pulse HIGH
5tB-3
5tB-3
5tB-3
ns
tCPRL
Read Clock Pulse LOW
5tB-3
5tB-3
5tB-3
ns
tRH
RDY Hold Time
tB-3
tB-3
tB-3
ns
tpRL
RDY Pulse Width LOW
6tB-3
6tB-3
6tB-3
ns
tpRH
RDY Pulse Width HIGH
Data Access Timel l2, 13]
Data Hold Timel l 2, 13]
4tB-3
4tB-3
4tB-3
tA
tROH
2tB-3
2tB+3
tB-3
2tB-3
2tB-3
2tB+3
+0.1
tB-3
-0.1
+0.1
tB-3
-0.1
REFCLK Clock Period Referenced to
CKW of 1tansmittetll4]
tCPXH
REFCLK Clock Pulse HIGH
9
9
9
tCPXL
REFCLK Clock Pulse LOW
9
9
9
tDS
Propagation Delay SI to SO (note ECL
and TTL thresholds)[15]
+0.1
15
Notes:
10. The period of tCKR will match the period of the traosmitter CKW
when the receiver is receiving serial data. When data is interrupted,
CKR may drift to one of the raoge limits above.
11. Receiver tn is calculated as tCKwlO if no data is being received, or
tCKW/lO if data is being received. See note 5.
12. Data includes QO-7, SC!D (Qs), and RVS (Q9).
13. tA aod tRQlI specifications are only valid if all outputs (CKR, ROY,
QO-7, SC/D, aod RVS) are loaded with the same DC aod AC load.
-0.1
ns
2tB+3
tcKx
15
ns
ns
ns
%
ns
ns
15
ns
14. REFCLK has no phase or frequency relationship with CKR aod only
acts as a centering reference to reduce clock synchronization time.
REFCLKmust be within 0.1 % of the transmitter CKW frequency, necessitating a ±500-PPM crystal.
15. The ECL switching threshold is the midpoint between the ECLVOH, aod VOL specification (approximately V cc - 1.35V). The TIL
switching threshold is 1.5Y.
7-9
•
:::i
:::i
o
o
1ij:~okUCTOR
PRELIMINARY
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
Switching Waveforms for the CY7B92X HOTIink Transmitter
1 - - - - - - tcKW - - - - - + 1
tcPWH CKW
1----
tSENP
----+I
Do - 0 7•
SC/D (Os).
SVS(Og)
B921-l!
tpPWL ----1~-- tpPWH -
_1-------
1..
tcKW
-----~
CKW
'sEND
0IL- 07.
SC/O (Os).
SVS (Og)
B921-9
7-10
-='-~~
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
~=CYPRESS
-_SF SEMICONDUC'TOR
Switching Waveforms for the CY7B93X HOTlink Receiver
tCKR
-tCPRH, - tCPRL - ,
I
CKR
-..I
I
\
-tPRH -
tRH
'{
tpRL
1\
RDY
RVS (0 9 )
~
-...
.. tA ..
00 - 07.
sC/O (08),
\
~ tROH
W
'V
Ir\
/r\
8921-10
•
:::!!:
:::!!:
o
o
REFCLK[141
S[
-tDS
so
NOTE 15
1.5V
8921-12
7-11
e:~
=--r;.
CYPRF.SS
~, SEMICONDUCTOR
PRELIMINARY
CY7B92X HOTlink Transmitter Operating Mode
Description
The CY7B92X Thansmitteroperatingwith the CY7B93XReceiver
forms a general-purpose data communication subsystem capable
of transporting user data at up to 30 Mbytesper second over several types of serial interface media. In normal operation, the Thansmittercan operate in either of two modes. The Encoded mode allows a user to send and receive eight (8) bit data and control
informationwithout first converting it to transmission characters.
The Bypass mode is used for systems in which the encoding and decodingis performed on an external protocol controller.
In either mode, data is loaded into the input register of the Transmitteron the rising edge of CKw. The input timing and functional
response of the Thansmitter input can be made to match timing and
function of either an asynchronous FIFO or a clocked FIFO by an
appropriate connection of input signals (See Figure 2).
Encoded Mode Operation
In Encoded mode the input data is int~reted as eight bits of data
(Do - D7), a context control bit (SCID), and a system diagnostic
input bit (SVS). If the context of the data is to be normal message
data, the sc/D input will be LOW, and the data will be encoded using the valid data character set described in the Valid Data Characters section of this datasheet. If the context ofthe data is to be control or protocol information, the Sc;D input will be HIGH, and the
data will be encoded using the valid special character set described
in the Valid Special Character Codes and Sequences section. Special characters include all protocol characters necessary to encode
packets for Fibre Channel, ESCON, proprietary systems, and for
diagnosticpurposes.
Thediagnosticcharacters and sequences available as Special Characters include those for Fibre Channel link testing, as well as codes
to be used for testing system response to link errors and timing.
The Violation symbol can be explicitly sent as PaI!2f a user data
packet (i.e., send CEO; D7-0 = 11100000 andSC/D = 1),orcan
be sent in response to an external system using the SVS input. This
will allow system diagnostic logic to evaluate the errors in an unambiguous manner, and will not require any modification to the transmissioninterface to force transmission errors for testing purposes.
Bypass Mode Operation
In BlPass mode the input data is interpreted as ten (10) bits (DO-7,
SC/D (Ds), and SVS (D9» of pre-encoded transmission data to be
ASYNCHRONOUS FIFO
CLOCKED FIFO
7C42X/3X/6X/7X
7C44X/5X
R
00- B
I
/ ~
ENR
i 1
CKW
Rp
CKW
I
I
ENA
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
OO-B
I
/
• •
ENA
Do -7. SCID
CKW
V9
Do -7. SCID
7B92X
7B92X
HOTLINK TRANSMITTER
HOTLINK TRANSMITTER
HOTLINK
CKR
HOTLINK RECEIVER
HOTLINK RECEIVER
7B93X
7B93X
RDY
CKR
00-7. SCID
I
RDY
00-7. SCID
V-
./ 9
W
./
CKW
Do -B
ENW
7C42X/3X/6X/7X
7C44X/5X
ASYNCHRONOUS FIFO
CLOCKED FIFO
Filmre 2. Seamless FIFO Interface
7-12
V9
DO-B
8921-13
PRELIMINARY
serialized and sent over the link. This data can use any encoding
method suitable to the designer. The only restrictions upon the
data encoding method is that it contain suitable transition density
for the Receiver PLL data synchronizer, and that it be compatible
with the transmission media.
Data loaded into the Input register on the rising edge of CKW will
be loaded into the Shifter on the following rising edge of CKW. It
will then be shifted to the outputs one bit at a time using the internal clock generated by the clock generator. The first bit of the
transmission character will appear at the output (OUTA±,
OUTB±, and OUTC±) immediately upon loading the Shifter.
While in either the Encoded mode or Bypass mode, if a CKW edge
arrives when the inputs are not enabled (ENA and ENN both
HIGH), the Encoder will insert a pad character K28.5 (e.g., COS)
to maintain proper link synchronization (in Bypass mode the proper sense of running disparity cannot be guaranteed for the first pad
character, but is correct for all pad characters that follow). This automatic insertion of pad characters can be inhibited by insuring
that the Transmitter is always enabled (i.e., ENA is hard-wired
LOW).
ECL Output Functional and Connection Options
The three pairs of ECL outputs all contain the same information
and are intended for use in systems with multiple connections.
Each output pair may be connected to a different serial media and
may be a different length, link type, or interface technology. For
systems that do not require all three output pairs, the unused pairs
should be wired to V cc to minimize the power dissipated by the
output circuit, and to minimize unwanted noise generation.
In systems that require the outputs to be shut off during some periods when link transmission is prohibited (e.g., for laser safetyfunctions), the FOTO input can be asserted. While it is possible to insure that the output state of the ECL drivers is LOW (i.e., light is
off) by sending all O's in Bypass mode, it is often inconvenient to
insert this level of control into the data transmission channel, and
it is impossible in Encoded mode. FOTO is provided to simplify
and augment this control function (typically found in laser-based
transmissionsystems). FOTOwill force OUTA± and OVTB± to
go LOW, while allowing OUTC± to continue to function normally
(OUTC is typically used as a diagnostic feedback and cannot be
disabled). This separation offunction allows various system configurationswithout undue load on the control function or data channellogic.
Transmitter Test Mode Description
The CY7B92X TI-ansmitter offers two types of test mode operation, BIST mode and Test mode. In a normal system application,
the Built-In Self-Thst (BIST) mode can be used to check the functionality ofthe Transmitter, the Receiver, and the link connecting
them. This mode is available with minimal impact on user system
logic, and can be used as part of the normal system diagnostics.
JYpicalconnections and timing are shown in Figure 3.
BISTMode
BISTmode functions as follows:
1. SetBISTEN LOW to be~n test pattern generation. Transmitter
begins sending bit rate ... 10lD...
2. Set either ENA or ENN LOW to begin pattern sequence generation (use of Enable pin not being used for normal FIFO interface can minimize logic delays between the FIFO and transmitter).
3. Allow the TI-ansmitterto run thro.!!ll!t several BIST loops or until the Receiver test is complete. RP will pulse HIGH once per
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
BISTloop, and can be used to count the number oftest pattern
loops.
4. When testing is completed, set BlSTEN HIGH and ENA and
ENNHIGH and resume normal function.
Note: It may be advisable to send violation characters to test the
RVS output in the Receiver. This can be done by explicitly sending
a violation with the SVS input, or allowing the transmitter BIST
loop to run while the Receiver runs in normal mode. The BlST
loop includes deliberate violation symbols and will test the RVS
function adequately.
BlST mode is intended to check the entire function of the TI-ansmitter( except the TI-ansmitterinputpins and the bypass function in
the Encoder), the serial link, and the Receiver. It augmentsnormal
factory ATE testing and provides the designer with a rigorous test
mechanismtocheckthelinktransmissionsystemwithoutrequiring
any significant system overhead.
When in Bypass mode, the BIST logic will function in the same way
as in the Encoded mode. MODE = HIGH and BISTEN = LOW
causes the Transmitter to switch to Encoded mode and begin sending the BISTpattern, as if MODE = LOW. When BlSTEN returns
to HIGH, the TI-ansmitterresumesnormal BYPASS operation. In
Thst mode the BIST function works as in the Normal mode.
ThstMode
The MODE input pin selects between three transmitte.!..functional
modes. When wired to HIGH, the DO-7, SVS, and SCID inputs bypass the Encoder and load directly from the Input register into the
Shifter. When wired to LOW, the inputs are encoded using the
8B/l0B codes and sequences shown at the end of this datasheet.
Since the TI-ansmitter is usually hard wired to Encoded or Bypass
mode, a third function is provided for the MODE pin. Thstmode is
used for factory or incoming device test. Thst mode is selected by
floating the MODE pin (internal resistors hold the MODE pin at
Vcd2.)
Thstmode causes the TI-ansmitterto function in its Encoded mode,
but with OutA +IOutB+ (used as a differential test clock input) as
the bit rate clock input instead of the internal PLL-generated bit
clock. In this mode, inputs are clocked by CKW and transfers between the Input register and Shifter are timed by the internal
couoters. The phase and pulse width of RP are controlled by
phases of the bit couoter (PLL feedback counter) as in Normal
mode. Input and output patterns can be synchronized with internal
logic by observing the state ofRP or the device can be initialized to
match an ATE test pattern using the following technique:
1. AssertThst mode for several test clock cycles to establish normal
countersequence.
2. AssertBlSTEN for one or more test clock cycles.
3. Deassert BISTEN and the next test clock cycle will reset the
counter.
4. Proceedwith pattern, voltage, and timing tests.
Test mode is intended to allow logical, DC, and AC testing of the
TI-ansmitter without requiring that the tester check output data
patterns at the 300-MHz bit rate, or accommodate the PLL lock,
tracking, and frequency range characteristics that are required
when the HOTLink part operates in its normal mode. To use
OutA+IOutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This forces the two outputs to go to an
"ECL LOW," which can be ignored while the test system creates a
differential input signal at some higher voltage.
7-13
•
:E
:E
oo
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
CY7B92X
FOTO
,,
---,,
,,
,,
,,
-1
Tx
START
...,
MODE
,,
Ss
LO°
un
n
CKW
,,r
,,
Rp
,,
'"
'8
,
r-
((
'f> »
OUTA
00-7
OUTB
SVS
OUTC
ENA
ENN
Tx
STOP
SS SS
SCID
r
BISTEN
CY7B93X
REFCLK
MODE
51
RF
SO
CKR
SCID
'"
8
ERROR
0))
))
INA
Qo -7
INB
RVS
AlB
ROY
BISTEN
, Rx~'----~~----~~
,BEGIN
SIGNALS NOT SHOWN ARE NOT REQUIRED FOR BIST.
Figure 3. Built-In Self-Thst D1ustration
7-14
8921-14
PRELIMINARY
CY7B93X HOTlink Receiver Operating Mode
Description
The CY7B93X Receiveroperatingwith the CY7B92X'Itansmitter
forms a general-purpose data communication subsystem capable
of transporting user data at up to 30 Mbytes per second over several types of serial interface media. In normal user operation, the Receivercan operate in either of two modes. The Encoded mode allows a user system to send and receive 8-bit data and control
informationwithout first converting it to transmission characters.
The Bypass mode is used for systems in which the encoding and decoding is performed by an external protocol controller.
In either mode, serial data is received at one ofthe differential line
receiver inputs and routed to the Shifter and the ClockSynchronizer. The PLL in the Clock Sync aligns the internally generated bit
rate clock with the incoming data stream and clocks the data into
the shifter. At theendofa byte time (ten bit times), the data accumulated in the shifter is transferred to the Decode register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in Clock Sync must be initialized.
Framer logic block checks the incoming bit stream for the unique
pattern that defines the byte boundaries. This combinatorial logic
filter looks for the X3T9.3 symbol defined as "Special Character
Comma"(K28.5). Once K28.5 is found, the free running bit counter in the Clock Sync block is synchronously reset to its initial state,
thus "framing" the data to the correct byte boundaries.
Since noise-induced errors can cause the incoming data to be corrupted, and since many combinations of error and legal data can
create an alias K28.5, an option is included to disable resynchronization of the bit counter. The Framer will be inhibited when the
RF input is held LOW. When RFrises, RDY will be inhibited until
a K28.5 has been detected, and RDY will resume its normal function. Data will continue to flow through the ReceiverwhileRDY is
inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight bits of
data (00 - 07), a context control bit (SCID), and a system diagnostic output bit (RVS). If the pattern in the Decode register is
found in the Valid Data Characters table, the context ofthe data is
decoded as normal message data and the SCID output will be
LOW. If the incoming bit pattern is found in the Valid Special
CharacterCodes and Sequences table, it is interpreted as "control"
or "protocol information," and the SCID output will be HIGH.
Special characters include all protocol characters defined for use in
packets for Fibre Channel, ESCON, and other proprietary and
diagnosticpurposes.
The Violation symbol that can be explicitly sent as part of a user
dat~acket (i.e., Transmitter sending CEO; D7-0 = 1110 0000 and
SC/D = 1; or SVS = 1) will be decoded and indicated in exactly the
same way as a noise-induced error in the transmission link. This
function will allow system diagnostics to evaluate the error in an
unambiguousmanner, and will not require any modification to the
receiver data interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is transferreddirectly to the Output register's 10 bits (00-7, 08, and 09).
It is assumed that the data has been pre-encoded prior to transmission,andwill be decodedinsubsequentlogicexternal to HOTLink.
This data can use any encoding method suitable to the designer.
The only restrictions upon the data encoding method is that it contain suitable transition density for the Receiver PLL data synchronizer, and that it be compatible with the transmission media.
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
Theframerfunction in Bypass mode is identical to Encoded mode,
so a K28.5 pattern can still be used to re-frame the serial bit stream.
Parallel Output Function
The 10 outputs (00-7, Sc;D, and RVS) all transition simultaneously, and are aligned with RDY and CKR with timing allowances to interface directly with either an asynchronous FIFO or a
clocked FIFO. Typical FIFO connections are shown inFigure 2.
Data outputs can be clocked into the system using either the rising
or falling edge of CKR, or the rising or falling edge of RDY. If
CKRis used, RDY can be used as an enable for the receiving logic.
A LOW pulse on RDY shows that new data has been received and
is ready to be delivered. The signal on RDY is a 60% - LOW duty
cycle byte-rate pulse train suitable for the write pulse in asynchronous FIFOs such as the CY7C42X, or the enable write input on
ClockedFIFOs such as the CY7C44X. HIGH on RDY shows that
the received data is the null character (normally inserted by the
transmitter as a pad between data inputs) and should be ignored.
When the 'Itansmitter is disabled it will continuously send pad
characters (K28.5). To assure that the~ive FIFO will not be
overfilled with these dummy bytes, the RDY pulse output is inhibited during fill strings. Data at the 00_70utputswill reflect the correct received data, but will not appear to change, sinE' a string of
K28.5s all are decoded as 07-0 =0000 0101 and SC/D = 1 (C05).
When new data appears (not K28.5), the RDY output will resume
normalfunction.
Fillcharacters are defined as any K28.5 followed by another K28.5.
All fi1lcharacterswillnot cause RDY to pulse. Any K28.5 followed
by any other character (including violation or illegal characters)
will be interpreted as usable data and will cause RDY to pulse.
As noted above, RDY can also be used as an indication of correct
framingof received data. While the Receiver is awaiting receipt of
a K28.5 with RF HIGH, the RDY outputs will be inhibited. When
RDY resumes, the received data will be properly framed and will
be decoded correctly.
Code rule violations and reception errors will be indicated as follows:
RVS sCLD Oouts
1. Good Data code received with
0
0 OO-FF
goodRD
2. Good Special Character code
OO-DB
0
received with good RD
EO
3. Unassigned code received
1
El
4. - K28.5 + received when RD was +
E2
1
5. + K28.5 - received when RD was E4
6. Good code received with wrong RD
Receiver Test Mode Description
The CY7B93x Receiver offers two types of test mode operation,
BIST mode and Thst mode. In a normal system application, the
Built-In Self-Thst (BIST) mode can be used to check the functionality of the 'Itansmitter, the Receiver and the link connecting them.
This mode is available with minimal impact on user system logic,
and can be used as part of the normal system diagnostics. Typical
connections and timing are shown in Figure 3.
BISTMode
BIST Mode function is as follows:
1. Set BISTEN LOW to enable self-test generation and await
RDY LOW indicating that the initialization code has been received.
7-15
::IE
::IE
oo
PRELIMINARY
2. Monitor RVS and check for any byte time with the pin mGH
to detect pattern mismatches. ROY will pulse mGH once per
BIST loop, and can be used to check test pattern progress.
QO-7 and SC/Ii will show the expected pattern and may be
useful for debug purposes.
3. When testing is completed, set BIS'i'EN mGH and resume
normal function.
Note: A specific test of the RVS output may be required to assure
an adequate test. 1b perform this test, it is only necessaIY to have
the 1tansmitter send violation (SVS = mGH) for a few bytes before beginning the BIST test sequence. Alternatively, the Receiver could enter BIST mode after the 1tansmitter has begun sending BIST loop data, or be removed before the Transmitter
finishes sending BIST loops, each of which contain several deliberate violations and should cause RVS to pulse HIGH.
BIST mode is intended to check the entire function of the 1tansmitter, serial link, and Receiver. It augments normal factoIY ATE
testing and provides the user system with a rigorous test mechanism to check the link transmission system, without requiring any
significant system overhead.
When in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = mGH and BISTEN =
WW causes the Receiver to switch to Encoded mode and begin
checking the decoded received data of the BIST pattern, as if
MODE = Ww. When lnS'I'mil' returns to HIGH, the Receiver
resumes normal Bypass operation. In 'lest mode the BIST function works as in the normal mode.
Test Mode
The MODE input pin selects between three receiver functional
modes. When wired HIGH, the Shifter contents bypass the Decoder and go directly from the Decoder latch to the QO-7, RVS,
and SOO inputs of the Output latch. When wired WW, the outputs are decoded using the 8B1lOB codes shown at the end of this
datasheet. The third function is lest mode, used for factoIY or incoming device test. This mode can be selected by leaving the
MODE pin open (internal circuitI)' forces an open pin to Vcc/2).
Test mode causes the Receiver to function in its Encoded mode,
but with INB± as the bit rate 'lest clock instead of the PLL VCO.
In this mode, transfers between the Shifter, Decoder register and
Output register are controlled by their normal logic, but with an
external bit rate clock instead of the PLL (the recovered bit
clock). Internal logic and test pattern inputs can be synchronized
by sending a SYNC pattern and allowing the Framer to align the
logic to the bit stream. The flow is as follows:
1. Assert 'lest mode for several test clock cycles to establish normal counter sequence.
2. Assert RF to enable reframing.
3. Input a repeating sequence of bits representing K28.5 (Sync).
4. RDY falling shows the byte boundaI)' established by the K28.5
input pattern.
5. Proceed with pattern, voltage and timing tests as is convenient
for the test program and tester to be used.
Internal PLL dividers can be checked in 'lest mode by asserting
RF = mGH. In this mode, the outputs on Qo, Qh and J:Nor QOUT
Byte Name
765
43210
Hex Value
DO.O
000
00000
00
D1.0
000
00001
01
D2.0
000
00010
02
D5.2
010
000101
45
D30.7
111
11110
FE
D31. 7
111
11111
FF
7-18
0101010101
0101010101
D10.2
111010 1010
111010 1010
Code Violation
::;--~
CYPRESS
SEMICONDUCl'OR
PRELIMINARY
'=
.
-
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
F
Valid Data Characters (SC(D
= LOW)
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
00.0
000
00000
100111
0100
011000
Bits
CurrentRD-
fghi
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
fghj
1011
00.1
001
00000
100111
1001
011000
1001
CurrentRD+
Bits
CurrentRD-
CurrentRD+
01. 0
000
OOOOJ
011101
0100
JOOOI0
1011
01.1
001
00001
011101
1001
100010
1001
02.0
000
00010
10J 101
0100
010010
1011
02.1
001
00010
101101
1001
010010
1001
03.0
ODD
00011
110001
1011
110001
0100
D3 .1
DOl
00011
110001
1001
110001
1001
04.0
000
00100
110101
0100
001010
1011
D4.1
001
00100
110101
1001
001010
1001
05.0
000
00101
101001
1011
101001
0100
05.1
001
00101
101001
1001
101001
1001
06.0
000
00110
011001
1011
011001
0100
06.1
001
00110
011001
1001
011001
1001
D7.0
000
0011J
111000
1011
000111
0100
07.1
001
00111
111000
1001
000111
1001
08.0
000
01000
111001
0100
000110
1011
08.1
001
01000
111001
1001
000110
1001
09.0
000
01001
100101
10}]
100101
0100
09.1
001
01001
100101
1001
100101
1001
010. a
000
01010
010101
1011
010101
0100
010.1
001
01010
010101
1001
010101
1001
011.0
000
OJ 011
1J0100
1011
110100
0100
011.1
001
01011
110100
1001
110100
1001
1001
012.0
000
01100
001101
1011
001101
0100
012.1
001
01100
0011 01
1001
001101
013.0
000
01101
101100
1011
101100
0100
013 .1
001
011 01
101100
1001
101100
1001
014.0
000
01110
0111 00
1011
011100
0100
014.1
001
01110
011100
1001
011100
1001
a
000
01111
010111
OJOO
101000
1011
015.1
001
01111
010111
1001
101000
1001
016. a
000
10000
011011
0100
100100
1011
D16.1
001
10000
011011
1001
100100
1001
017.0
000
10001
100011
1011
100011
0100
D17.1
OOJ
10001
100011
1001
100011
1001
018.0
000
10010
010011
1011
010011
0100
018.1
001
10010
010011
1001
010011
1001
019.0
000
10011
110010
1011
llOO10
0100
019.1
001
10011
110010
1001
110010
1001
020.0
000
10100
001011
1011
001011
0100
020.1
001
10100
001011
1001
001011
1001
021.0
000
10101
101010
1011
101010
0100
021. 1
001
10101
101010
1001
101010
1001
022.0
000
10110
011010
1011
011010
0100
022.1
001
10110
011010
1001
OllO10
1001
023.0
000
10111
111010
0100
000101
1011
023.1
001
10111
111010
1001
000101
1001
024.0
000
11000
1100J 1
(nOO
001100
1011
024.1
001
11000
110011
1001
001100
1001
025.0
000
11001
100110
1011
100110
0100
025.1
001
11001
100110
1001
100110
1001
026.0
000
11010
010110
1011
010110
0100
026.1
001
11010
010110
1001
010110
1001
027.0
000
11011
110110
0100
001001
1011
027 .1
001
llOll
110110
1001
001001
1001
028.0
000
11100
001110
1011
001110
0100
028.1
001
11100
001110
1001
001110
1001
000
11J 01
101110
0100
010001
1011
029.1
001
11101
101110
1001
010001
1001
001
11110
011110
1001
100001
1001
001
11111
101011
1001
010100
1001
015.
D29.0
030.0
000
11110
011110
0100
100001
1011
D30.1
031.0
000
11111
101011
0100
010100
1011
031.1
7-19
•
::E
::E
o
o
.r.~~R
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
Valid Data Characters (SCJD = LOW) (continued)
Data
Byte
Name
fgbi
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
DO.2
010
00000
100111
0101
011000
HGF EDCBA
0101
DO.3
011
00000
D1.2
010
00001
011101
0101
D2.2
010
00010
101101
0101
100010
0101
D1. 3
011
010010
0101
D2.3
011
D3.2
010
00011
110001
0101
110001
0101
D3.3
D4.2
010
00100
110101
0101
001010
0101
DS.2
010
D6.2
010
00101
101001
0101
101001
00110
011001
0101
011001
D7.2
010
00111
111000
0101
DS.2
010
01000
111001
0101
Bits
CurrentRD-
CurrentRD+
Bits
CurrentRD-
CurrentRD+
abcdei
fgbj
abcdei
fghj
100111
0011
011000
1100
00001
011101
0011
100010
1100
00010
101101
0011
010010
1100
011
00011
110001
1100
110001
0011
D4.3
011
00100
110101
0011
001010
1100
0101
DS.3
011
00101
101001
1100
101001
0011
0101
D6.3
011
00110
011001
1100
011001
0011
000111
0101
D7.3
011
00111
111000
1100
000111
0011
000110
0101
DS.3
011
01000
111001
0011
000110
1100
D9.2
010
01001
100101
0101
100101
0101
D9.3
011
01001
100101
1100
100101
0011
D10.2
010
01010
010101
0101
010101
0101
D10.3
011
01010
010101
1100
010101
0011
D11.2
010
01011
110100
0101
110100
0101
Dll.3
011
01011
110100
1100
110100
0011
D12.2
010
01100
001101
0101
001101
0101
D12.3
011
01100
001101
1100
001101
0011
D13 .2
010
01101
101100
0101
101100
0101
D13 .3
011
01101
101100
1100
101100
0011
D14.2
010
01110
011100
011
01110
011100
1100
011100
0011
0101
011100
0101
D14.3
D1S.2
010
01111
010111
0101
101000
0101
D1S.3
011
01111
010111
0011
101000
1100
D16.2
010
10000
011011
0101
100100
0101
D16.3
011
10000
011011
0011
100100
1100
D17.2
010
10001
100011
0101
100011
0101
D17.3
011
10001
100011
1100
100011
0011
D1S.2
010
10010
010011
0101
010011
0101
D1S.3
011
10010
010011
1100
010011
0011
D19.2
010
10011
110010
0101
110010
0101
D19.3
011
10011
110010
1100
110010
0011
D20.2
010
10100
001011
0101
001011
0101
D20.3
011
10100
001011
1100
001011
0011
D21.2
010
10101
101010
0101
101010
0101
D21.3
011
10101
101010
1100
101010
0011
D22.2
010
10110
011010
0101
011010
0101
D22.3
011
10110
011010
1100
011010
0011
D23.2
010
10111
111010
0101
000101
0101
D23.3
011
10111
111010
0011
000101
1100
D24.2
010
11000
110011
0101
001100
0101
D24.3
011
11000
110011
0011
001100
1100
D2S.2
010
11001
100110
0101
100110
0101
D2S.3
011
11001
100110
1100
100110
0011
D26.2
010
11010
010110
0101
010110
0101
D26.3
011
11010
010110
1100
010110
0011
D27.2
010
11011
110110
0101
001001
0101
D27.3
011
11011
110110
0011
001001
1100
D2S.2
010
11100
001110
0101
001110
0101
D2S.3
011
11100
001110
1100
001110
0011
D29.2
010
11101
101110
0101
010001
0101
D29.3
011
11101
101110
0011
010001
1100
D30.2
010
11110
011110
0101
100001
0101
D30.3
011
11110
011110
0011
100001
1100
D31.2
010
11111
101011
0101
010100
0101
D31.3
Oll
11111
101011
DOll
010100
1100
7-20
~PRESS
~,L
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
SEMICONDUCTOR
Valid Data Characters (SCID = LOW)(continued)
Data
Byte
Name
HGF
Bits
EDCBA
abcdei
CurrentRDfghj
CurrentRD-
CurrentRD+
HGF
EDCBA
abcdei
fgbj
abedei
DO.4
100
00000
100111
D1.4
100
00001
011101
DO.S
101
00000
100111
1010
011000
1010
D1. S
101
00001
011101
1010
100010
1010
D2.4
100
00010
101101
D3.4
100
00011
110001
1101
D2.S
101
00010
101101
1010
010010
1010
0010
D3.S
101
00011
110001
1010
110001
D4.4
100
00100
110101
1010
001010
1101
D4.S
101
00100
110101
1010
001010
DS.4
100
00101
1010
1101
101001
0010
DS.S
101
00101
101001
1010
101001
D6.4
100
1010
011001
1101
011001
0010
D6.S
101
00110
011001
1010
011001
D7.4
1010
00111
111000
1101
000111
0010
D7.S
101
00111
111000
1010
000111
1010
100
01000
111001
0010
000110
1101
DB.S
101
01000
111001
1010
000110
1010
100
01001
100101
1101
100101
0010
D9.S
101
01001
100101
1010
100101
1010
D10.4
100
01010
010101
1101
010101
0010
DI0.S
101
01010
010101
1010
010101
1010
D11.4
100
01011
110100
1101
110100
0010
D11. S
101
01011
110100
1010
110100
1010
D12.4
100
01100
001101
1101
001101
0010
D12.S
101
01100
001101
1010
001101
1010
D13 .4
100
01101
101100
1101
101100
0010
D13.S
101
01101
101100
1010
101100
1010
D14.4
100
01110
011100
1101
011100
0010
D14.S
101
01110
011100
1010
011100
1010
D1S.4
100
01111
010111
0010
101000
1101
D1S.S
101
01111
010111
1010
101000
1010
D16.4
100
10000
011011
0010
100100
1101
D16.S
101
10000
011011
1010
100100
1010
D17.4
100
10001
100011
1101
100011
0010
D17.S
101
10001
100011
1010
100011
1010
D1B.4
100
10010
010011
1101
010011
0010
D1B.S
101
10010
010011
1010
010011
1010
D19.4
100
10011
110010
1101
110010
0010
D19.S
101
10011
110010
1010
110010
1010
D20.4
100
10100
001011
1101
001011
0010
D20.S
101
10100
001011
1010
001011
1010
D21.4
100
10101
101010
1101
101010
0010
D21. S
101
10101
101010
1010
101010
1010
D22.4
100
10110
011010
1101
011010
0010
D22.S
101
10110
011010
1010
011010
1010
D23.4
100
10111
111010
0010
000101
1101
D23.S
101
10111
111010
1010
000101
1010
D24.4
100
11000
110011
0010
001100
1101
D24.S
101
11000
110011
1010
001100
1010
D2S.4
100
11001
100110
1101
100110
0010
D2S.S
101
11001
100110
1010
100110
1010
D26.4
100
11010
010110
1101
010110
0010
D26.S
101
11010
010110
1010
010110
1010
D27.4
100
11011
110110
0010
001001
1101
D27.S
101
11011
110110
1010
001001
1010
D2B.4
100
11100
001110
1101
001110
0010
D28.S
101
11100
001110
1010
001110
1010
D29.4
100
11101
101110
0010
010001
1101
D29.S
101
11101
101110
1010
010001
1010
D30.4
100
11110
011110
0010
100001
1101
D30.S
101
11110
011110
1010
100001
1010
D31.4
100
11111
101011
0010
010100
1101
D31.5
101
11111
101011
1010
010100
1010
abcdei
CurrentRD+
fgbi
Data
Byte
Name
0010
011000
1101
0010
100010
1101
0010
010010
1101
110001
0010
101001
00110
100
DS.4
D9.4
7-21
Bits
fgbj
•
=:,~
CYPRFSS
~.a
_ F
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
SEMICONDUCTOR
Valid Data Characters (SCm = LOW)(continued)
Data
Byte
Name
HGF EDCBA
CurrentRD-
CurrentRD+
CurrentRD+
fgbj
abcdei
fgbi
Data
Byte
Name
CurrentRD-
abcdei
HGF
EDCBA
abcdei
fgbj
abcdei
DO,6
fgbj
110
Dl, 6
110
00000
100111
0110
011000
0110
DO.7
111
00000
100111
0001
011000
1110
00001
011101
0110
100010
0110
D1.7
111
00001
011101
0001
100010
D2,6
1110
110
00010
101101
0110
010010
0110
D2.7
111
00010
101101
0001
010010
1110
D3.6
110
00011
110001
0110
110001
0110
D3.7
111
00011
110001
1110
110001
0001
D4,6
110
00100
110101
0110
001010
0110
D4.7
111
00100
110101
0001
001010
1110
DS.6
110
00101
101001
0110
101001
0110
DS.7
111
00101
101001
1110
101001
0001
D6.6
110
00110
011001
0110
011001
0110
D6.7
111
00110
011001
1110
011001
0001
D7.6
110
00111
111000
0110
000111
0110
D7.7
111
00111
111000
1110
000111
0001
DB.6
110
01000
111001
0110
000110
0110
DB.7
111
01000
111001
0001
000110
1110
0001
Bits
Bits
D9.6
110
01001
100101
0110
100101
0110
D9.7
111
01001
100101
1110
100101
D10.6
110
01010
010101
0110
010101
0110
D10.7
111
01010
010101
1110
010101
0001
D11,6
110
01011
110100
0110
110100
0110
D11.7
111
01011
110100
1110
110100
1000
D12.6
110
01100
001101
0110
001101
0110
D12.7
111
01100
001101
1110
001101
0001
D13.6
110
01101
101100
0110
101100
0110
D13.7
111
01101
101100
1110
101100
1000
D14.6
110
01110
011100
0110
011100
0110
D14.7
111
01110
011100
1110
011100
1000
D1S.6
110
01111
010111
0110
101000
0110
D1S.7
111
01111
010111
0001
101000
1110
D16.6
110
10000
011011
0110
100100
0110
D16.7
111
10000
011011
0001
100100
1110
D17.6
110
10001
100011
0110
100011
0110
D17.7
111
10001
100011
0111
100011
0001
D1B.6
110
10010
010011
0110
010011
0110
D1B.7
111
10010
010011
0111
010011
0001
D19.6
110
10011
110010
0110
110010
0110
D19.7
111
10011
110010
1110
110010
0001
D20.6
110
10100
001011
0110
001011
0110
D20.7
111
10100
001011
0111
001011
0001
D21,6
110
10101
101010
0110
101010
0110
D21, 7
111
10101
101010
1110
101010
0001
D22.6
110
10110
011010
0110
011010
0110
D22.7
111
10110
011010
1110
011010
0001
D23.6
110
10111
111010
0110
000101
0110
D23.7
111
10111
111010
0001
000101
1110
D24.6
110
11000
110011
0110
001100
0110
D24.7
111
11000
110011
0001
001100
1110
D2S.6
110
11001
100110
0110
100110
0110
D2S.7
111
11001
100110
1110
100110
0001
D26.6
110
11010
010110
0110
010110
0110
D26.7
111
11010
010110
1110
010110
0001
D27.6
110
11011
110110
0110
001001
0110
D27.7
111
11011
110110
0001
001001
1110
D2B.6
110
11100
001110
0110
001110
0110
D28.7
111
11100
001110
1110
001110
0001
D29.6
110
11101
101110
0110
010001
0110
D29.7
111
11101
101110
0001
010001
1110
D30.6
110
11110
011110
0110
100001
0110
D30.7
111
11110
011110
0001
100001
1110
010100
0110
D31.7
111
11111
101011
0001
010100
1110
D31.6
110
11111
101011
0110
7-22
t>~
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
PRELIMINARY
~=CYPRESS
_ifF SEMICONDUCTOR
Valid Special Character Codes and Sequences (SCtD = IDGH)[16J
Bits
S.C. Byte Name
K28.0
S.C. Code Name
CO.O
(COO)
CurrentRD-
CurrentRD+
HGF
EDCBA
abcdei
fghj
abcdei
fgbi
000
00000
001111
0100
110000
1011
K28.1
CL a
(Cal)
000
00001
001111
1001
110000
0110
K28.2
C2.0
(CO2)
000
00010
001111
0101
110000
1010
K28.3
C3.0
(C03 )
000
00011
001111
0011
110000
1100
K28.4
C4.0
(C04)
000
00100
001111
0010
110000
1101
K28.S
CS.O
(COS)
000
00101
001111
1010
110000
0101
K28.6
C6.0
(C06)
000
00110
001111
0110
110000
1001
K28.7
C7.0
(C07)
000
00111
001111
1000
110000
0111
K23.7
C8.0
(C08)
000
01000
111010
1000
000101
0111
K27.7
C9.0
(C09)
000
01001
110110
1000
001001
0111
K29.7
C10.0
(COA)
000
01010
101110
1000
010001
0111
K30.7
C11. a
(COB)
000
01011
011110
1000
100001
0111
Reserved
C12.0
(COC)
000
01100
Reserved
C31.0
(C1F)
000
11111
Idle
CO.1
(C20)
001
00000
-K28.S+,D21.4,D21.5,D21.S,repeaP~
R_RDY
CL1
(C21)
001
00001
- K2 8 . S + , D21 . 4 , D1 a . 2 , D1 a . 2 , repea p8J
EOFxx
C2.1
(C22)
001
00010
-K28. S, Dn.xxxd19J
Reserved
C3.1
(C23)
001
00011
Reserved
C3L 6
(CDF)
110
11111
+K28. 5, Dn.xxx1[19J
< Code Rule Violation>[20J
Exception
CO.7
(CEO)
111
00000
-K28.S
CL7
(CE1)
111
00001
001111
1010[21J
001111
1010[21J
+K28. S
C2.7
(CE2 )
111
00010
110000
0101[22J
110000
0101[22]
Reserved
C3.7
(CE3 )
111
00011
Exception
C4.7
(CE4)
111
00100
Reserved
CS.7
(CES)
111
00101
Reserved
C3L 7
(CFF)
111
11111
Notes:
16. Notation for Special Character Byte Name is consistent with Fibre
Channel and ESCON naming conventions. Special Character Code
Name is intended to describe bioary information present on I/O pios.
Common usage for the name can either be in the form used for describiog Oata patterns (I.e., CO.O through C31.7), or in hex notation
(I.e., Cun where nn=the specified value between 00 and FF).
17. C20 = 'fransmitNegative K28.5 ( - K28.5 + ) disregardiog Current RD
when ioput is held for only one byte time. If held longer, transmitter
begios sendiog the repeating transmit sequence -K28.5+, 021.4,
021.S, 021.S, (repeat all four bytes) ... defined in X3T9.3 as the primitive signal "Idle word." This Special Character input must be held for
four (4) byte times or multiples of four bytes or it will be truncated by
the new data.
[23]
Receiver will never output this Special Character, since K28.S is decoded as COS, and the subsequent bytes are decoded as data.
18. C21 = 'fransmitNegativeK28.5 (-K28.5+) disregarding Cnrrent RD
when ioput is held for only one byte time. If held longer, transmitter
begios sending the repeating transmit sequence - K28.5 +, 021.4,
010.2, OlO.2,(repeat all four bytes) ... dermed io X31'9.3 as the primitive signal "Receiver_Ready (R_ROY). "This Special Character ioput
must be held for four (4) byte times or multiples of four bytes or it will
be truncated by the new data.
Receiver will never output this Special Character, sioce K28.5 is decoded as COS, and the subsequent bytes are decoded as data.
7-23
•
:E
:E
0
0
.:riPRffiS
~_"
PRELIMINARY
SEMICONDUCTOR
Notes (continued):
19. C22 = 'fransmiteither -K28.S+ or +K28.5- as deterroined by Current RO and modify the 'fransmission Character that follows, by setting its least significant bit to 1 or O. If Current RD at the start of the
following character is plus ( + ) the LSB is set to 0, and if Current RD
is minus ( - ) the LSB becomes 1. This modification allows construction of X3T9.3 "EOF" frame delimiters wherein the second data byte
is determined by the Current RO.
For example, to send "EOFdt" the controller could issue the sequence C22-021.4- 021.4-021.4, and the HOTUnk 'fransmitter
will send either K28.5-021.4-021.4-021.4 or K28.5-021.S021.4-021.4 based on Current RD. Likewise to send "EOFdti" the
controller could issue the sequence C22- 010.4-021.4-021.4, and
the HOTUnk 'fransmitter will send either K28.S-010.4-021.4021.4 or K28.5- 010.5-021.4- 021.4 based on Current RD.
Receiver will never output this Special Character, since K28.5 is decoded as COS, and the subsequent bytes are decoded as data.
20. CEO = 'fransmit a deliberate code rule violation. The code chosen for
this function follows the normal Running ~isparity rules. 'fransmis-
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
sion of this Special Character has the same effect as asserting SVS =
HIGH.
Receiver will ouly output this Special Character if the 'fransmission
Character being decoded is not found in the tables.
21. CE1 = 'fransmit Negative K28.5 (-K28.5+) disregarding Current
RD.
Receiver will only output this Special Character if K28.5 is received
with the wrong running disparity. Receiverwill output CE1 if - K28.S
is received with RO+, otherwise K28.5 is decoded as COS.
22. CE2 = 'fransmit Positive K28.S ( + K28.S - ) disregarding Current RO.
Receiver will only output tbis Special Character if K28.5 is received
with the wrong running disparity. Receiverwill output CE2 if + K28.5
is received with RO-, otherwise K28.5 is decoded as COS.
23. CE4 = 'fransmit the same deliberate code rule violation as is sent by
asserting CEO.
Receiver will only output this Special Character if the 'fransmission
Character being decoded is found in the tables, but RunningDisparity
does not match.
Ordering Information
Package
'tYPe
Operating
Range
CY7B921-DC
022
Commercial
CY7B921-JC
CY7B921-LC
J64
L64
CY7B921-PC
P21
CY7B921-JI
J64
CY7B921-PI
P21
D22
Ordering Code
CY7B921-DMB
CY7B921- LMB
Package
Ordering Code
Industrial
Military
D22
J64
L64
CY7B931-PC
P21
CY7B931-JI
J64
P21
Industrial
D22
Military
CY7B931-DMB
CY7B931- LMB
CY7B922-JC
CY7B922-LC
L64
CY7B932-LC
CY7B922-PC
P21
CY7B932-PC
CY7B922-DC
CY7B922-JI
J64
CY7B922-PI
CY7B922-DMB
P21
D22
CY7B922-LMB
L64
Ordering Code
CY7B923-DC
CY7B923-JC
Package
1YPe
D22
CY7B923-LC
J64
L64
CY7B923-PC
P21
CY7B923-JI
J64
CY7B923-PI
CY7B923-DMB
P21
D22
CY7B923-LMB
L64
Operating
Range
Ordering Code
Commercial
CY7B932-DC
CY7B932-JC
Industrial
CY7B932-JI
Military
CY7B932-PI
CY7B932-DMB
CY7B932-LMB
Operating
Range
L64
Package
1YPe
D22
Commercial
J64
L64
P21
J64
P21
D22
L64
Industrial
Military
Operating
Range
CY7B933-DC
CY7B933-JC
D22
J64
Commercial
CY7B933-LC
L64
CY7B933-PC
P21
Industrial
CY7B933-JI
J64
P21
Military
CY7B933-PI
CY7B933-DMB
CY7B933-LMB
7-24
Operating
Range
Package
'Jype
Ordering Code
Commercial
Commercial
CY7B931-DC
Package
1YPe
D22
J64
Ordering Code
Operating
Range
CY7B931-JC
CY7B931-LC
CY7B931-PI
L64
'tYPe
D22
L64
Industrial
Military
=-.
-
:::;b
PRELIMINARY
-~CYPRESS
,
SEMICONDUCTOR
CY7B921/CY7B931,
CY7B922/CY7B932,
CY7B923/CY7B933
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOHT
1,2,3
tom
VOLT
1,2,3
tCKW
VOHE
1,2,3
tCKX
VOLE
1,2,3
lOST
1,2,3
VIHT
1,2,3
tCPRH
VILT
1,2,3
tCPRL
9, to, 11
9, to, 11
9, to, 11
9, to, 11
9, to, 11
9,10,11
9, to, 11
9, to, 11
9, to, 11
9, to, 11
9,10,11
9, to, 11
9, to, 11
9,10,11
9, to, 11
9, to, 11
9,10,11
9, to, 11
9,10,11
9,10,11
9, to, 11
9,10,11
9,10,11
9, to, 11
tB
tcpWH
tcPWL
VIHE
1,2,3
tcPXH
VILE
1,2,3
tCPXL
IIHT
1,2,3
tRH
lILT
1,2,3
IIHE
1,2,3
IILE
1,2,3
tA
Icc
1,2,3
tSD
VDIFF
1,2,3
tHD
VIHH
1,2,3
tROH
VILL
1,2,3
tDS
tpRH
tpRL
tSEND
tSENP
tHEN
tpDR
tpPWH
tPPWL
Document #: 38-00189
7-25
::::E
::::E
oo
PRELIMINARY
CYPRESS
SEMICONDUCTOR
CY7B991
CY7B992
Programmable Skew
Clock Buffer (PSCB)
Features
Functional Description
• Output pair skew <100 ps typical
(250 max.)
• All outputs skew <300 ps typical
(750 max.)
• 15- to SO-MHz operation
• User-selectable output functions
- Selectable output skew to 18 ns
- Inverted and non-inverted outputs
- Outputs at 'h and Y. input freq.
- Outputs at 2x and 4x input freq.
• Zero input to output delay
• 50% duty-cycle outputs
• Symmetrical output drivers
- ±24 rnA TTL levels (CY7B991)
- ±50 rnA CMOS levels (CY7B992)
- Drive terminated lines 50Q lines
• Low operating current: <65 rnA
• 32-pin PLCC/LCC package
The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer
user-selectable control over system clock
functions. These multiple-output clock
drivers provide the system integrator with
functions necessary to optimize the timing
of high-performance computer systems.
Eight individual drivers, arranged as four
pairsofuser-controllable outputs, can each
drive terminated transmission lines with
impedances as low as 50Qwhile delivering
minimal and specified output skews and
full-swing logic levels (CY7B991 TIL or
CY7B992 CMOS).
Each output can be hardwired to one of
nine delay or function configurations.
Delay increments of 0.7 to 1.5 ns are determined by the operating frequencywith out-
7-26
puts able to skew up to ±6 time units from
their nominal "zero" skew position. The
completely integrated PLL allows external
load and transmission line delay effects to
be canceled. When this "zero delay" capability of the PSCB is combined with the selectable output skew functions, the user
can create Output-to-Output delays of up
to ± 12 time units.
Divide-by-twoand Divide-by-four output
functions are provided for additional flexibility in designing complex clock systems.
When combined with the internal PLL,
these divide functions allow distribution of
a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clockdistributiondifficultywhileallowingmaximumsystem clock speed and flexibility.
-=..
•
- r..
~
CY7B991
CY7B992
PRELIMINARY
; __
==CYPRESS
- , SEMICONDUC'TOR
Pin Definitions
Signal Name
I/O
Description
REF
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured,
FB
PLL feedback input (typically connected to one of the eight outputs),
FS
Three-state frequency range select. See Table 1,
IFO,IFI
Three-state function select inputs for output pair 1 (I QO, I Ql), See Table 2.
2FO,2FI
Three-state function select inputs for output pair 2 (2QO, 2QI). See Table 2.
3FO,3Fl
Three-state function seiect inputs for output pair 3 (3QO, 3Ql). See Table 2.
4FO,4Fl
Three-state function select inputs for output pair 4 (4QO, 4Ql). See Table 2.
TEST
Test mode select. In normal operation, this input will be wired to GND.
o
o
o
o
lQO,IQI
2QO,2Ql
3QO,3Ql
4QO,4Ql
Output pair 1. See Table 2.
Output pair 2. See Table 2.
Output pair 3. See Table 2.
Output pair 4. See Table 2.
VCCN
PWR
VCCQ
PWR
Power supply for output drivers.
Power supply for internal circuitry.
GND
PWR
Ground.
Block Diagram Description
Skew Select Matrix
Phase Frequency Detector and Filter
The skew select matrix is comprised offour independent sections.
Each section has two low-skew, high-fanout drivers (xQO, xQl),
and two corresponding three-state function select (xFO, xFl) inputs. Table 2 below shows the nine possible output functions for
each section as determined by the function select inputs. All times
are measured with respect to the REF input assuming that the output connected to the FB input has Otu selected.
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator(VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator to
create discrete time units that are selected in the skew select matrix.
The operational range ofthe VCO is determined by the FS control
pin. The time unit (tv) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table I.
Thble 1. Frequency Range Select and tu Calculation!!]
f1QO(MHz)
FS!2]
Min. Max.
1
tu = f
lQO X N
where N =
Approximate
Frequency At
Which tu = 1.0 ns
LOW
15
30
44ns
22.7 MHz
MID
25
50
26ns
37.5 MHz
HIGH
40
80
16ns
62.5 MHz
Note:
1. For all three·state inputs, HIGH indicates a connection to Vee, LOW
indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to
Vcd2.
2. FS level is determined by output frequency on 1QO.
7-27
Thble 2. Programmable Skew Configurations!l]
Function Selects
IFl,2Fl,
3Fl,4Fl
lFO,2FO,
3FO,4FO
LOW
LOW
Output Functions
lQO,lQl,
2QO,2Ql
- 4tU
3QO,3Ql
4QO,4Ql
Divideby2 Divideby2
LOW
MID
- 3tu
- 6tU
LOW
HIGH
- 2tU
- 4tU
- 4tU
MID
LOW
-ltu
- 2tu
- 2tv
MID
MID
Otu
Otu
Otv
MID
HIGH
+ltu
+ 2tu
HIGH
LOW
+ 2tu
+ 4tU
+ 2tv
+4tV
HIGH
MID
+ 3tu
+ 6tu
+ 6tu
HIGH
HIGH
+ 4tu
Divideby4
Inverted
- 6tU
•
·-~PRESS
~
-
CY7B991
CY7B992
PRELIMINARY
SEMJCONDUCTOR
Ii'
0
on
~
:i'
cf
I
I
I
_0
0
~
(\J
=>
::?
I
0
0
0
0
=>
N
+
+
_0
0
=>
;:;)
+
_0
=>
::0:
+0
=>
;n
+
0
=>
10
+
_0
FB Input
REF Input
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
- Btu
LL
LH
- 4tu
LM
(N/A)
- 3tu
LH
ML
- 2tu
ML
(N/A)
- 1tu
MM
MM
MH
(N/A)
+ 1tu
HL
MH
+ 2tu
HM
(N/A)
+ 3tu
HH
HL
+ 4tu
(N/A)
HM
+Btu
(N/A)
LL/HH
DIVIDED
(N/A)
HH
INVERT
----'
Otu
V-
7B99x-3
Figure 1. 'JYpical Outputs with FB Connected to a Zero-Skew Output[3]
Maximum Ratings
Operating Range
(Above which the usefullife may be impaired. Foruserguidelines,
nottested. )
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 64 rnA
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent .. . . . . . . . . . . . . . . . . . . . . . . . . . . >200 rnA
Range
Commercial
O°Cto +70°C
Vee
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Militaryl4]
- 55°Cto +125°C
5V± 10%
Notes:
3 FB connected to an output selected for "zero" skew (Le.,xFl = xFO = MID)
4. Indicates case temperature.
7-28
Ambient
Temperature
CY7B991
CY7B992
~
.
··~PRESS
PRELIMINARY
,F SEMlCONDUcroR
Electrical Characteristics Over the Operating Rangel5]
CY7B991
Parameter
Description
Output HIGH Voltage
VOH
Thst Conditions
Min.
Vee = Min., lOR = - 24 rnA
2.4
Max.
Output LOW Voltage
Max.
Units
V
Vee = Min., lOR =- 50 rnA
VOL
CY7B992
Min.
VCC - 0.75
VCC = Min., IOL = 24 rnA
0.45
V
0.45
Vcc = Min., IOL =50 rnA
Vrn
Input HIGH Voltage
(REF and FB inputs only)
2.0
Vcc
Vcc -1.35
Vee
V
VIL
Input LOW Voltage
(REF and FB inputs only)
- 0.5
0.8
- 0.5
1.35
V
Irn
Input HIGH Leakage Current
(REF and FB inputs only)
Vee = Max., VIN ~3.0V
10
!lA
IlL
Input LOW Leakage Current
(REF and FB inputs only)
Vee = Max., VIN.5. O.4V
los
Output Short Circuit Current[6]
Vcc = Max., VOUT = GND
(25°C only)
IcCQ
Operating Current Used by
Internal Circuitry
V CCN = VeeQ = Max.,
Input Selects Open, fMAX
ICCN
Output Buffer Current
10
-500
-500
!lA
-250
-250
rnA
65
65
rnA
TBD
TBD
InN
MHz/pF
o
Capacitance [7]
Parameters
o
Description
InputCapacitance
TA
Thst Conditions
Max.
Units
= 25°C,f= 1 MHz, Vee = 5.0V
10
pF
Notes:
5. Seethe last page of this specification for Group A subgroup testing information.
6. Thsted one output at a time, output shorted for less than one second,
less than 10% duty cycle. Room temperature only.
7. AppliestoREFandFBinputsonly.Testedinitiallyandafteranydesign
or process changes that may affect these parameters.
AC Test Loads and Waveforms
SV
~
I
CL
R1
R2
3.0V
R1 = 180
R2 =68
CL=SOpF
(Includes fixture and probe capacitance)
2.0V
Vth = 1.SV
1.0V
~ns
-:-
-:-
7899><-4
7B99x-5
TTL AC Thst Load (CY7B991)
TTL Input Thst Waveform (CY7B991)
5V
n
:!!
:!!
tR1
R2
R1 = 100
R2 = 100
CL=50pF
(Includes fixture and probe capacitance)
80%
Vth =Vcd2
20%
~2ns
7899><-5
7B99x-7
CMOS AC Thst Load (CY7B992)
CMOS Input Thst Waveform (CY7B992)
7-29
;'~~NOOcr)R
CY7B991
CY7B992
PRELIMINARY
Switching Characteristics Over the Operating RangelS, 8]
CY7B991-7
Parameters
fREF
Description
Operating Clock Frequency in MHz
Min.
'Jyp.
CY7B992-7
Max.
Min.
'Jyp.
Max. Units
FS=LOw!1]
15
30
15
30
FS=MID[1]
25
50
25
FS=HIGH[1]
40
80
40
50
80[9]
MHz
tRPWH
REF Pulse Width HIGH
5.0
5.0
tRPWL
REF Pulse Width LOW
5.0
5.0
tRRISE
REF Rise Time (1.0V - 2.0V)
3.0
5.0
ns
3.0
5.0
ns
ns
ns
tRFALL
REF FaIl Time (2.0V - 1.0V)
tu
Programmable Skew Unit
tUE
Programmable Skew Unit Error[10]
0.0
±0.7
0.0
±0.7
ns
tSKEWPR
Zero Output Matched-Pair Skew (XQO, XQ1 )[11, 12]
0.1
0.25
0.1
0.25
ns
tSKEWO
Zero Output Skew (All Outputs)[11, 13]
0.3
0.75
0.3
0.75
ns
tSKEWl
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[11, 14]
0.6
1.0
0.6
1.0
ns
tSKEW2
Output Skew 1Rise-Fall, Nominal-Inverted, DividedDividedj11, 1 ]
1.0
1.5
1.0
1.5
ns
tSKEW3
OutputSkew(Rise-Rise,FaIl-FaIl,DifferentClassOutputs)[11,14]
0.7
1.2
0.7
1.2
ns
tSKEW4
Output Skew ~Rise-FaII, Nominal-Divided, DividedInvertedj11,1 ]
1.2
1.7
1.2
1.7
ns
tSKEWS
Device-to-DeviceSkew
tpD
-0.7
0.0
+0.7
- 0.7
0.0
+0.7
ns
10DCV
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variatiod16]
-1.0
0.0
+1.0
-1.0
0.0
+1.0
ns
tORISE
Output Rise Timel l 7]
1.0
2.0
3.0
1.0
3.0
5.0
ns
10FALL
Output FaIl Timel 17]
1.0
2.0
3.0
1.0
3.0
5.0
ns
tLOCK
PLL Lock Timel18]
0.5
ms
See Table 2.
See Note 15.
0.5
Notes:
8. Testing levels for the CY7B991 are TTL levels (1.5V to 1.5V). '!bsting
levels for the CY7B992 are CMOS levels (Vcd2 to V 002).
9. Not specified nuder full load.
10. tUE is a measure of the timing error from tu as calculated in Table 1.
The major contributors to this error inclnde ontput edge variations,
cross talk, and load-induced variations between package pins and between sigoallines external to the chip. tUE is not cumulative across
mnltiple tu delays.
11. SKEW is defined as the time between the earliest and the latest output
transition among all outputs for which the same tu delay has been se·
lectedwhen all are loadedwith50pF and terminatedwith500 to 1.37V
(CY7B991) or Vcd2 (CY7B992).
12. tSKEWPR is defined as the skew between a pair of outputs (XOO and
X01) when all eight outpnts are selected for Otu.
13. tSKEWO is defined as the skew between all eight outputs when all are
selected for Olu.
14. There are three classes of outputs: Nominal (mnltiple of Iu delay), Inverted (400 and 401 only with 4FO = 4Fl = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by4 mode).
15. tSKEWS is the ontput-to-output skew between two or more devices op·
erating nuder the same conditions (Vce, ambient temperature, air
flow, etc.). The maximum variation between two parts is 0.2 +
tSKEWn#1 + tSKEWn#2 where tSKEWn is one of the applicable skew
specifications in this table.
16. tODev is the deviation of the output from a 50% duty cycle. Output
pnlse width variations are included in tSKEW2 and tSKEW4 specifications.
17. Output rise and fall times are as specified with outputs loaded with 50
pF and terminated through 500 to l.37V (CY7B991) or Vcd2
(CY7B992). The measurement is taken between 1.0V and 2.0V for the
CY7B991 and between O.2Vee and 0.8Vce for the CY7B992.
18. tWCK is the time that is required before synchronization is achieved.
Thisspecificationisvalid only after V ceis stable and within normal operating limits. This parameter is measured from the application of a
new sigoal or frequency at REF or FB until tpD is within specified
limits.
7-30
~~PRESS
~I SEMlCONDUClDR
PRELIMINARY
CY7B991
CY7B992
AC Timing Diagrams
REF
FB
Q
OTHERQ
:E
:E
oo
INVERTEDQ
REF DIVIDED BY 2
REF DIVIDED BY 4
N*IU
N*lu
Q (OIu)
..J
-
tUE
.-
-
OTHER Q (N1u)
IUE
.....
7-31
!-I-
_8
:iI.~PRLSS
~J
CY7B991
CY7B992
PRELIMINARY
SEMlCONDUCfOR
Operational Mode Descriptions
REF~~
· ..
ZO
·· ..
..
:
FB
SYSTEM
CLOCK
REF
FS
:
:
LOAD
L1
LOAD
': ": : ~,-----,
~
L2
~ ' - -_ _- J
4FO
4F1
3FO
3F1
300
301
2FO
2F1
200
201
:::
~...l!l
..., .,~
~
LOAD
'------'
1FO
1F1
LOAD
TEST
7B99x·9
Figure 2. Zero·Skew and/or Zero·Delay Clock Driver
Figure 2 shows thePSCB configured as a zero-skew clock buffer. In
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission
Jines (with impedances as low as 50 ohms), allows efficient printed
circuit board design.
this mode the 7B991/992 can be used as the basis for a low-skew
clock distribution tree. When all of the function select inputs (xFO,
xFl) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input
REF
FB
SYSTEM
CLOCK
_ _- - - - - 1
.Jt.Jt.JL
·
.
...
REF
FS
•
•
•
~
~
4FO
4F1
L2
1------,
3FO
3F1
300
301
:.h.h..h.;
• • •
'--_----1 2FO
200
201
· ..
·· ..
:f.lf.tf.l:~4
..
2F1
, - - -_ _--1 1FO
1F1
LOAD
Zo ' - - - - - - - - '
LOAD
~ #~L-----'
100
101-
TEST
LOAD
'------'
LENGTH L1=L2
L3 < L2 by 18 inches
L4 > L2 by 18 inches
Zo
7899x·10
Figure 3. Programmable-Skew Clock Driver
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between outputs, the PSCB can be programmed to stagger the timing ofitsoutputs. The four groups of output pairs can each be programmed to
different output timing. Skew timing can be adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4QO output is fed
back to FB and configured for zero skew. The other three pairs of
outputs are programmed to yield different skews relative to the
feedback. By retarding the clock signal on the longer traces or advancing the clock signal on shorter traces, all loads can receive the
clock pulse at the same time.
In this illustration the FB input is connected to an output with O-ns
skew (xFl, xFO = MID) selected. The internal PLLsynchronizes
the FB and REF inputs and aligns their rising edges to insure that
all outputs have precise phase and frequency alignment.
Clock skews can be advanced by ±6 time units (tu) when using an
output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also adjusted. Since
the definition of "Zero Skew", +tu, and - tu are defined relative
to output groups, and since the PLL aligns the rising edges of REF
and FB, it is possible to create wider output skews by proper selection of xFn inputs. For example a + 10 tu between REF and 3Qx
can be achieved by connecting lQO to FB and setting IFO = IFI =
GND, 3FO = MID, and3Fl = High. (Since FB aligns at - 4tuand
3Qxskewsto +6tu, a total of + 10 tu skew is realized.) Manyother
configurationscan be realized by skewing both the output used as
the FB input and skewing the other outputs.
7-32
-.
~I'CYPRESS
~
~_F.i SEMICONDUCTOR
REF~
, ,
REF~
,
20 MHz
FB
REF
FS
4FO
4F1
400
401
3FO
3F1
300
301
1.f1str
,
2FO
2F1
200
201
lJl.nI""
, , ,
1FO
1F1
100
101
t.ri..r1.r
, , ,
,
TEST
CY7B991
CY7B992
PRELIMINARY
, , ,
FB
REF
FS
4FO
4F1
3FO
3F1
2FO
2F1
1FO
1F1
TEST
'40 MHz
400
401
300
301
200
201
100
101
-u-u--tJ'20 MHz
~
'80 MHz
.t.uuuu:uL
nn.n..rtn..rL
7B99x_12
1
Figure 5. Frequency MultipJierwith Skew Connections
7B99x~11
Figure 5 illustrates the PSCB configured as a clock multiplier. The
Figure 4. Inverted Output Connections
Figure 4 shows an example of the invert function of the PSCB. In
this example the 4QO output used as the FB input is programmed
for invert (4FO = 4F1 = HIGH) while the other three pairs of out·
puts are programmed for zero skew. When 4FO and 4F1 are tied
high 4QO and 4Q1 become inverted, zero phase outputs. The PLL
aligns the rising edge of the FB input with the rising edge of the
REF. This causes the 1Q, 2Q, and 3Q outputs to become the "in·
verted" outputs with respect to the REF input. By selecting which
output is connect to FB, it is possible to have 2 inverted and 6 non·
inverted outputs or 6 inverted and 2 non·inverted outputs. The cor·
rect configuration wonld be determined by the need for more (or
fewer) inverted outputs. Although not shown, outputs can also be
skewed to compensate for metal traces of varying length in addi·
tion to inversion.
3QO output is programmed to divide by four and is fed back to FB
This causes the PLL to increase its frequency until the 3QO and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qxoutputs
run at 80 MHz. The 4QO and 4Q1 outputs are programmed to di·
vide by two, which results in a 40·MHzwaveform at these outputs.
Note that the 20· and 40·MHz clocks fall simultaneously and are
out of phase on their rising edge. This will allow the designer to use
the rising edges of the Y2 frequency and y., frequency outputs with·
out concern for rising·edge skew. The 2QO, 2Q1, 1QO, and 1Q1
outputs run at 80 MHz and are skewed by programming their se·
lect inputs accordingly. Note that the FS pin is wired for 80·MHz
operation because that is the frequency of the fastest output.
REF
...IL..h....lt.
,
"
FB
REF
FS
,
~OMHz
"
'
4FO
4F1
400
401
1-f"""l.....rl-
3FO
3F1
2FO
2F1
300
301
~
1FO
1F1
TEST
100
101
200
201
I
I
I
I
, , , ,
'SHllHz
~OtYIHz
-f1..f1..rLf1..
, , , ,
,
.fU1.f1..ftJ""U
7B99x·13
Figure 6. Frequency Divider Connections
Figure 6 demonstrates the PSCB in a clock divider application. 2QO
is fed back to the FB input and programmed to zero skew. 3Qx is
programmed to divide by four. 4Qx is programmed to divide by
two. Note that the falling edges of the 4Qx and 3Qx outputs are
aligned. This allows use of the rising edges of the Y2 frequency and
y., frequencywithout concern for skew mismatch. The 1Qx outputs
are programmed to zero skew and are aligned with the 2Qx out·
puts. In this example, the FS input is grounded to configure the de·
vice in the 15· to 30· MHz range since the highest frequency output
is running at 20 MHz.
7-33
•
CY7B991
CY7B992
PRELIMINARY
_ _- - - - - - _ _ _
20-MHz
DISTRIBUTION
CLOCK
REF~
I
SO-MHz
FB
~----'REF
FS
I
I
I
I
I
I
I
I
I
:
I
:
I
:
~INVERTED
LOAD
400
4FO
4F1
3FO
3F1
2FO
2F1
401
300
301
200
201
100
101
...-''-----1 1FO
1F1
TEST
20-MHz
~
---
..n.rt.nJ"1,..- I
I
I
I
I
I
I
SO-MHz
ZERO SKEW
I
I
~----: : : : ::
80-M~
•
SKEWED 4 ns
Zo ____--,
f-ILI ___
LOAD
--l
Zo
I
:fIZo
"'I
LOAD
L._ _ _----l
7B99x-14
Figure 7. Multi-Function Clock Driver
The other functions that are selectable on the 3Qxand 4Qx outputs
include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to
clock different subsystems on opposite edges, without suffering
from the pulse asymmetry typical of non-uniform loading. This
function allows the two subsystems to each be clocked 180 degrees
out of phase, but still to be aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the "IX" clock. Without this
feature,an extemaldividerwouldneed to be added, and thepropa-
REF
gation delay of the divider would add to the skew between the different clock signals.
Thesedivided outputs, coupled with the Phase Locked Loop,allow
the PSCB to multiply the clock rate at the REF input by either two
orfour. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still
maintaining the low-skew characteristics of the clock driver. The
PSCBcan perform all of the functions described above at the same
time. It can multiply by two or four while it is dividing by two (or
four) at the same time that it is shifting its outputs over a wide
range or maintaining zero skew between all outputs.
.JLlLJL
I
I
FB
SYSTEM
CLOCK
LOAD
REF
FS
4FO
4F1
3FO
3F1
2FO
2F1
300
301
1FO
1F1
100
101
LOAD
200
201
TEST
-
Figure 8. Board-to-Board Clock Distribution
The CY7B991/992 can be connected in series to construct a zeroskew clock distribution tree between boards. Delays of the downstream clock buffers can be programmed to compensate for the
wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating
7B99x-15
a zero-delay clock tree. Cascaded clock buffers will accumulate
low-frequencyjitter because of the non-ideal filtering characteristics of the PLL filter. It is not recommended that more than two
clock buffers be connected in series.
7-34
CY7B991
CY7B992
~
=-:- .~
CYPRESS
PRELIMINARY
~c~
""'!iii!!!!ii-" SEMlCONDUCTOR
Ordering Information
CY7B991-7JC
Package
'lYpe
J65
CY7B991-7LC
155
Accuracy
(ps)
750
Ordering Code
CY7B991-7JI
J65
CY7B991-7LI
155
CY7B991-7LMB
155
Operating
Range
Accuracy
(ps)
Commercial
750
Industrial
Military
CY7B992-7JC
Package
'lYpe
J65
CY7B992-7LC
155
Ordering Code
CY7B992-7JI
J65
CY7B992-7LI
155
CY7B992-7LMB
L55
Operating
Range
Commercial
Industrial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIH
VIL
IlL
rIH
los
Icc
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1
1,2,3
•
Switching Characteristics
Parameters
tRPWH
tRPWL
tRRISE
tRFALL
tu
tUE
tSKEWPR
tSKEWO
tSKEWl
tSKEW2
tSKEW3
tSKEW4
tpD
tODCV
tORISE
tOFALL
tWCK
Subgroups
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
Document #: 38-00188
7-35
INFO
I'
SRAMs
PROMs
II
PlDs
FIFOs
II
lOGIC
COMM
RISC
.:1
MODULES
iIi
ECl
lili
BUS
I"
ItI
In
I"
MILITARY
TOOLS
QUALITY
PACKAGES
1~1
Section Contents
RIse
Page Number
8-1
Introduction to RISC
Device Number
CY7C601A
CY7C602A
CY7C604A
CY7C605A
CY7C611A
CY7C613
CY7C614
CY7C615
CY7C616
CY7C617
CY7C618
CYM6001K
CYM6002K
CYM6003K
Description
32-Bit RISC Processor ......................................................... .
Floating-Point Unit .......................................................... .
Cache Controller and Memory Management Unit ................................. .
Cache Controller and Memory Management Unit ................................. .
32-Bit RISe Controller ....................................................... .
MBus Memory Controller ..................................................... .
MBus Peripheral I/O Controller ................................................ .
Interrupt Controller .......................................................... .
MBus-to-SBus Interface Controller ............................................. .
MBus-to-Video Graphics Controller ............................................ .
SBus Controller ............................................................. .
SPARCore CPU Module ...................................................... .
SPARCore Dual-CPU Module ................................................. .
SPARCore CPU Module for Multiprocessing ..................................... .
8-6
8-14
8-20
8-29
8-39
8-46
8-47
8-48
8-49
8-50
8-51
8-52
8-58
8-65
CYPRESS
SEMICONDUCTOR
Introduction to RISe
Introduction
This section provides an overview of the basic concepts and advantages of RISC computer architectures in general and a brief summary of the specific features of Cypress's CY7C6OO family of
SPARC@ RISC microprocessors.
Scalable Processor Architecture
The Cypress CY7C600 family is an implementation of the SPARC
architecture. SPARC, an acronym for Scalable Processor ARChitecture, is the only open, multi-vendor RISC architecture, and it
has quickly become an industry standard. The term "scalable" refers to the the fact that SPARC's inherent simplicity allows it to be
manufactured in a variety of semiconductor technologies. This
characteristic not only enables the CY7C600 SPARC family to
scale down in size as process technologies mature, but lends itself
to a wide range of system designs. Already, applications for the
CY7C6OO range from massively parallel multiprocessing supercomputers to desktop and laptop workstations and personal computers, as well as embedded control.
What is RISC?
RISC, an acronym for Reduced Instruction Set Computer, is a
computer architecture emphasizing simplicity and efficiency. RISC
designs begin with a necessary and sufficient instruction set. Typically, a few simple operations account for ahnost all computations.
RISC machines are about two to five times faster than machines
with traditional complex instruction set architectures. Also, RISC's
simpler designs are easier to implement, resulting in shorter design
cycles.
RISC architectures are a response to the evolution from assembly
language to high-level languages. Assembly language programs occasionally employ elaborate machine instructions, whereas highlevel language compilers rarely do. For example, most C compilers
use only about 30% of the available instructions on CISC machines. Studies show that approximately 80% of a typical program's computations require only about 20% of a processor's instruction set.
RISC is to hardware what the UNIX@ operating system is to software. The UNIX system proves that operating systems can be both
simple and useful. Hardware studies lead to the same conclusion.
As advances in semiconductor technology reduce the cost of processing and memory, complex instruction sets become a performance liability. The designers of RISC machines strive for hardware
simplicity, with close cooperation between machine architecture
and compiler design. At each step, computer architects must ask: to
what extent does a feature improve or degrade performance and is
it worth the cost of implementation? Each additional feature, no
matter how useful it is in an isolated instance, makes all others perform more slowly by its mere presence.
The goal of RISC architecture is to maximize the effective speed of
a design by performing infrequent functions in software, including
hardware-only features that yield a net performance gain. Performance gains are measured by conducting detailed studies of
large high-level language programs. RISC improves performance
by providing the building blocks from which high-level functions
can be synthesized without the overhead of general but complex instructions.
RISCArchitecture
The following characteristics are typical of RISC architectures, including the CY7C600 design:
• Single-cycle execution. Most instructions are executed in a
single machine cycle.
• Non-destructive three-address architecture. Holding source
and destination operands in registers after an operation is completed allows compilers to better utilize the processor's pipeline
by more efficiently scheduling instructions to reuse operands.
• Hardwired coutrol with no microcode. Microcode adds a level
of complexity and raises the number of cycles per instruction.
• Load/store, register-to-register design. All computational instructions involve registers. Memory accesses are made with only
load and store instructions.
• Simple fixed-format instructions with few addressing modes.
All instructions are one word long (typically 32 bits) and have
few addressing modes.
• Pipelining. The instruction set desi(\D allows for the processing
of several instructions at the same tIme.
• High-performance memory. RISC machines have a large number of general-purpose registers (the 7C601Ahas 136) and large
cache memories.
• Migration of functions to software. Only those features that
measurably improve performance are implemented in hardware. Programs contain sequences of simple instructions for executing complex functions rather than the complex instructions
themselves.
• Simple, efficient instruction pipeline visible to compilers. For
examI?le, branches take effect after execution of the following instructIOn, permitting a fetch of the next instruction during execution of the current instruction.
SPARC is a registered trademark of SPARC International, Inc.
Sun-4'" , and NFS'" are trademarks of Sun Microsystems, Inc.
UNIX is a registered trademark of AT&T Bell Laboratories.
VAX is a registered trademark of Digital Equipment Corporation.
8-1
~PRffiS
~Ts~calDUCTOR
The real keys to enhanced performance are single-cycle execution
and keeping the cycle time as short as possible. Many characteristics of RISC architectures, such as load/store and register-to-register design, facilitate single-cycle execution. Simple fixed-format instructions, on the other hand, permit shorter cycles by reducing
decoding time.
number of instructions actually executed may not be as great as the
increased program size would indicate. A windowed register file,
for example, simplifies call1return sequences so that context
switches become less expensive.
Note that some of these features, particularly pipelining and highperformance memories, have been used in super-computer designs
for many years. The difference is that in RISC architectures these
ideas are integrated into a processor with a simple instruction set
and no microcode.
The CY7C600 family of 32-bit SPARC microprocessors has been
partitioned to offer a complete solution for high-performance
computer and embedded applications.
Moving functionality from run time to compile time also enhances
performance. Functions calculated at compile time do not require
further calculating each time the program runs. Furthermore, optimizing compilers can rearrange pipelined instruction sequences
and arrange register-to-register operations to reuse computational
results.
A new set of simplified design criteria has emerged:
• Instructions should be simple uuless there is a good reason for
complexity. Th be worthwhile, a new instruction that increases
cycle time by 10% must reduce the total number of cycles executed by at least .10%.
• Microcode isn't any faster than sequences of hardwired instructions. Movin!! software into microcode does not make it better,
it just makes It more difficult.
• Fixed-format instructions and pipelined execution are more important than program size. As memory gets cheaper and faster,
the space/time tradeoff resolves in favor of time. Reducing space
no longer decreases time.
• Compiler technology should use simple instructions to generate
more complex instructions. Instead of substituting a complicated
microcoded instruction for several simple instructions, which
compilers did in the 1970s, optimizing compilers can form sequences of simple, fast instructions out of complex high-level
code. Operands can be kept in registers to increase speed even
further.
RISC's Speed Advantage
Using any given benchmark, the performance (P) of a particular
computer is inversely proportional to the product of the benchmark's instruction count (I), the average number of clock cycles per
instruction (C), and the inverse of the clock speed (S). Assuming
that a RISC machine runs at the same clock speed as a corresponding traditional machine, S is identical. The number of clock cycles
perinstruction (C), is around 1.3 to 1.7 for RISC machines, and between 4 and 10 for traditional machines. This makes the instruction
execution rate of RISC machines about 3 to 6 times faster than traditional machines. But because traditional machines have more
powerful instructions, RISC machines must execute more instructions for the same program, typically about 10% to 30% more.
Since RISC machines execute 10% to 30% more instructions 3 to
6 times faster, they are about 2 to 5 times faster than traditional
machines for executing typical large programs.
P=
IxCx
~
Compiled programs on RISC machines are somewhat larger than
compiled programs on traditional machines because several simple
instructions replace one complex instruction resulting in decreased
code density. All SPARC instructions are 32 bits wide, whereas
some instructions on traditional machines are narrower. But the
CY7C600 Architecture
The SPARC CPU is comprised of the CY7C601A integer unit
(IV), the CY7C602A floating-point unit (FPU), the CY7C604A/
CY7C605A cache controller and memory management units
(CMU and CMU-MP), and the CY7C157A cache storage unit
(CSU). The CY7C601A communicates with the CY7C602A and
the CY7C604A via a 32-bit address bus and a 32-bit instruction/data bus. The CY7C604A also interfaces to Mbus, the SPARC-standard 64-bit multiplexed address/data bus that provides a high
bandwidth path to main memory.
The CY7C604A/CY7C605A provide uni- and multiprocessing
memory management and cache control functions that, when combined with the CY7C157A SRAMs, provide up to 256K of zerowait-state cache memory.
The CY7C611A is a derivative of the CY7C601A, but has been optimized for embedded control applications.
The CY7C601A and CY7C60ZA operate concurrently. The FPU
performs all floating-point calculations with its own set of registers
and ALU logic.
Instruction Categories
The CY7C600 architecture has 62 basic integer instructions.
CY7C600 instructions fall into seven basic categories:
• Load and store instmctions (the only way to access memory).
These instructions use two registers or a register and a constant
to calculate the memory address involved. Half-word accesses
must be aligned on 2-byte boundaries, word accesses on 4-byte
boundaries, and double-word accesses on 8-byte boundanes.
These alignment restrictions greatly speed up memory access.
• Arithmetic/logicaI/shift instmctions. These instructions compute a result that is a function of two source operands and then
place the result in a register. They perform arithmetic, logical, or
shift operations.
• Floating-point and coprocessor instmctions. These include
floating-point calculations, operations on floating-point registers, ana instructions involving the optional coprocessor. Floating-point operations execute concurrently with IU instructions
and with other floating-point operations when necessary. This
concurrency is transparent to the progranuner.
• Control transfer instructions. These include jumps, calls, traps,
and branches. Control transfers are usually delayed until after
execution ofthe next instruction so that the pipeline is not emptied every time a control transfer occurs. Thus compilers can be
optimized for delayed branching.
• Read/write control register instmctions. These include instructions to read and write the contents of various control registers.
Generally the source or destination is implied by the instructions.
• Artificial intelligence instmctions. These include the tagged
arithmetic instructions Thgged Add and Thgged Subtract. Thgged
instructions are useful for implementing artificial intelligence
languages such as LISp, because tags can automatically indicate
to software interpreters the data type of arithmetic operands.
8-2
==--~
_'=CYPRESS
- o F SEMICONDUcrOR
• Multiprocessing instructions. These include two instructions
for implementing semaphores in memory: Atomic Load/Store
Vnsigned Byte, which loads a byte from memory and then sets
the location to allIs, and SWAP, which exchanges the contents
of a re~ister and memory location. Both of these instructions are
"atomIc" or ininterruptible.
Register Windows
A unique feature contributing to the high performance of the
CY7C600 design is its register windows. Because of overlapping
registers between adjoining windows, results left in registers by a
calling routine automatically become available operands for the
called routine, reducing the need for load and store instructions to
memory.
According to the architectural specification, there may be anywhere between 2 and 32 register windows, each window having 24
working registers, plus 8 global registers. The CY7C601A has 8
register windows with 24 registers each plus 8 global registers, for
a total of 136 registers. This windowed register model simplifies
compiler design, speeds procedure calls, and efficiently supports
A1 programming languages such as Prolog, LISp, and Smalltalk. In
addition, they can be alternately configured for fast context switching.
'Ihlps and Interrupts
The CY7C600 design supports a full set of traps and interrupts.
They are handled by a table that supports 128 hardware and 128
software traps. Even though floating-point instructions can execute concurrently with integer instructions, floating-point traps
are precise because the FPV supplies (from the table) the address
of the instructions that failed.
Protection
Some CY7C600 instructions are privileged and can only be executed while the processor is in supervisor mode. This instruction
execution protection ensures that user programs cannot accidentally alter the state of the machine with respect to its peripherals.
The CY7C600 design also provides memory protection, which is
essential for smooth multitasking operation. Memory protection
makes it impossible for user programs to corrupt the system, other
user programs, or themselves.
Open Architecture
Advantages of Open Architecture
The CY7C600 design is the first open RISC architecture, and one
of the few open CPV architectures. Standard products are more
beneficial than proprietary ones because standards allow users to
acquire that most cost-effective hardware and software in a competitive multivendor marketplace. Integrated circuits come from
several competing semiconductor vendors, while software is
supplied by systems vendors. This advantage is lost when users are
limited by a processor with proprietary hardware and software.
RISC architectures, and the CY7C600 design in particular, are
easy to implement because they are relatively simple. Since they
have short design cycles, RISC machines can absorb new technologies almost immediately, unlike more complicated computer architectures.
CY7C600 Machines and Other RISC Machines
The CY7C600 design has more similarities to Berkeley's RISC-II
architecture than to any other RISC architecture. Like the RISC-II
architecture, it uses register windows in order to reduce the number ofload/store instructions. The CY7C600 architecture allows 32
register windows, but the initial implementation has 8 windows.
The tagged instructions are derived from SOAR, the "Smalltalk
On A RISC" processor developed at Berkeley after implementing
RISC-II.
CY7C600 systems are designed for optimal floating-point performance and support single-, double-, and extended-precision operands and operations, as specified by the ANIS/lEEE 754 floating-point standard. High floating-point performance results from
concurrency of the IV and FPV. The integer unit loads and stores
floating-point operands, while the floating-point unit performs calculations. If an error (such as a floating-point exception) occurs,
the floating-point unit specifies precisely where the trap took
place; execution is expediently resumed at the discretion of the integer unit. Furthermore, the floating-point unit has an internal instruction queue; it can operate while the integer unit is processing
unrelated functions.
CY7C600 systems deliver very high levels of performance. The
flexibility of the architecture makes future systems capable of delivering performance many times greater than the performance of
the initial implementation. Moreover, the openness of the architecture makes it possible to absorb technological advances almost
as soon as they occur.
CY7C600 Product Family
CY7C60lA Integer Unit
The IV is the basic processing engine that executes all of the instruction set except for floating-point operations. The CY7C601A
IV contains a large 136 x 32 triple-port register file, which is divided into 8 windows. Each window contains 24 working registers
and has access to the same 8 global registers. A current window
pointer (CWP) fIled in the processor state register keeps track of
which window is currently active. The CWP is decremented when
the processor calls a subroutine and is incremented when the processor returns.
The registers in each window are divided into ins, outs, and locals.
Each window shares its ins and outs with adjacent windows. The
outs of the previous window are the ins of the current window, and
the outs of the current window are the ins of the next window. The
globals are equally available to all windows and the locals are
unique to each window. The windows are joined together in a circular stack where the outs of the last window are the ins of the first
window.
The IV supports a multitasking operating system by providing user
and supervisor modes. Some instructions are privileged and can
only be executed while the processor is in supervisor mode. Changing from user to supervisor mode requires taking a hardware interrupt or executing a trap instruction.
The IV supports both asynchronous traps (interrupts) and synchronous traps (error conditions and trap instructions). naps
transfer control to an offset within a table. The base address of the
table is specified by a trap base register and the offset is a function
8-3
=~PR£SS
. . . .,
~&!CONDUCTOR
of the trap type. naps are taken before the current instruction
causes any changes visible to the programmer and can therefore be
considered to occur between instructions.
CY7C602AFloating-Point Unit
The CY7C602A FPU provides high-performance, IEEE
STD-7S4-198S-compatible single- and double-precision floatingpoint calculations for 7C600 systems and is designed to operate
concurrently with the CY7C601A All address and control signals
for memory accesses by the CY7C602A are supplied by the
CY7C601A Floating-point instructions are addressed by the
CY7C601A, and are simultaneously latched from the data bus by
both the CY7C601A and CY7C602A. Floating-point instructions
are concurrently decoded by the CY7C601A and the CY7C602A,
but do not begin execution in the CY7C602A until after the instruction is enabled by a signal from the CY7C601A Pending and
currently executing FP instructions are placed in an on-chip queue
while the IU continues to execute non-floating-point instructions.
The CY7C602A has a 32 x 32-bit data register file for floatingpoint operations. The contents of these registers are transferred to
and from external memory under control of the CY7C601A using
floating-point load/store instructions. Addresses and control signals for data accesses during a floating-point load or store are
supplied by the CY7C601A, while the CY7C602A supplies or receives data. Although the CY7C602A operates concurrently with
the CY7C601A, a program containing floating-point computations
generates results as if the instructions were being executed sequentially.
CY7C604A Cache Controller and Memory Management Unit
The CY7C604A Cache Controller and Memory Management
Unit (CMU) provides hardware support for a demand-paged virtual memory enviromnent for the CY7C601A processor. The
CY7C604A conforms to the standard SPARC architecture definition for memory management. Page size is fixed at 4 kilobytes. The
CMU translates 32-bit virtual addresses from the processor into
36-bit physical addresses and provides both write-through and
buffered copy-back cache policies. The on-chip context register allows support of up to 4096 contexts.
High-speed address look-up is provided by an on-chip translation
lookaside buffer (TLB). Each entry contains the virtual to physical
mapping of a 4-kbyte page. If a virtual address match is detected in
one of the TLB entries, the physical address translation contained
in that entry will be delivered to the outputs of the CMU.If the virtual address from the processor has no corresponding entry in the
CMU, the CMU will automatically perform address translation for
the virtual address using on-chip hardware to access a main
memory resident three-level page table. Each "matched" TLB
entry is checked for protection violation automatically and violations are reported to the Integer Unit as memory exceptions.
The CMU also provides storage for 2048 cache address tags for a
64-kbyte cache with a 32-byte line size. The tag entries can be directlywritten or read by the processor. In normal operation, eleven
low-order bits (15 - 5) of the virtual address from the processor are
used to select one of the tag entries in the CY7C604A and its 16-bit
contents are compared on chip with the 16 high-order processor
address bits to determine ifthe cache contains the required data or
instruction. This cache hit/miss comparison is then qualified by various bnilt-in protection checks. Pipelined accesses are supported
via on-chip registers that capture both address and data from the
processor.
The CY7C604A also contains the logic required in a system to implement the byte and half-word write capabilities provided in the
SPARC instruction set. Cache tag update is also simplified by an
automatic page update on miss feature, which eliminates the need
for processor accesses during tag update.
CY7C60SA Cache Controller and Memory Management Unit for
Mnltiprocessor Systems
The CY7C60SA Cache Controller and Memory Management
Unit is an extension of the CY7C604A for use in multiprocessor
systems. The CY7C605A provides the same SPARC reference
MMU as the CY7C604A, but adds an enhanced cache controller
that incorporates bus snooping and cache coherency protocol required to maintain a multiprocessor cache. The CY7C605A provides a dual-cache tag memory, which allows the CY7C605A to
perform bus snooping while it simultaneously supports cache accesses by the CY7C601A The CY7C60SA cache coherency protocol is based on the IEEE Futurebus, which has been recognized as
a superior protocol for maintaining cache consistency without degrading processor performance.
The CY7C605A supports direct data intervention, which is the capability of a CY7C60SA-based cache to directly supply modified
data to another requesting cache without requiring main memory
intervention. In addition to direct data intervention, the
CY7C605A also supports memory reflection. Memory reflection
allows a memory system to automatically update itself during a direct data intervention operation. This feature allows a multiprocessing system to update both a requesting cache and main memory in
a single bus operation. The CY7C605A is pin-compatible with the
CY7C604A This feature allows a system to be upgraded from uniprocessor to multiprocessor by modifying the operating system and
replacing the CY7C604A with the CY7C60SA
CY7ClS7A Cache Storage Unit
The CY7C157A 16K x 16 CSU is designed to interface easily to
and provide maximum performance for the CY7C600 processor.
The RAM has registered address inputs and latched data inputs
and outputs as well as a self-timed write pulse that greatly simplifies the design of cache memories for the CY7C601A Integer Unit.
The device has a single clock that controls loading of the address
register, data input latches, data output latches, pipeline control
latch, and chip enable register. The chip enable is clocked into a
register and pipelined through a control register to condition the
output enable. This pipelined design allows a cache that works as
an extension of the internal instruction pipeline of the CY7C601A
integer unit, thereby maximizing performance. The write enable is
edge-activated and self-timed, thereby eliminating the need for the
user to generate accurate write pulses in external logic. A separate
asynchronous output enable is provided to disable outputs during
a write or to allow other devices access to the bus.
8-4
·
~
~PRF.SS
SEMICONDUCTOR
F
CY7C602A
FLOATINGPOINT
UNIT (FPU)
CY7C601A
INTEGER UNIT (IU)
r----- -------------t------I
I
MKI
CY7C604A (or 60SA)
CY7C1S7A
I
I
rCACHE STORAGE
I
I CACHE CONTROLLER
&MMU(CMU)
UNIT (2)
I
I
I
I
I
I
I1_ _ - _ ~------------------J
"MBUS
v
Figure 1. Full System Block Diagram
Copyright 1989 by Cypress Semiconductor Corporation and Sun Microsystems, Inc.
8-5
•
CY7C601A
CYPRESS
SEMICONDUCTOR
32-Bit RIse Processor
- Registers can be used as eight windows of 24 registers each for low
procedure overhead
- Registers can also be used as register banks for fast context switching
Features
• Reduced Instruction Set Computer
(RISe) Architecture
- Simple format instructions
- Most instructions execute in a
single cycle
• Multiprocessing support
• Large virtual address space
- 32-bit virtuaI address bus
- 8-bit address space identifier bus
• Very high performance
- 25-,33-, and 4O-MHz clock speeds
yield 18, 24, and 29 MIPS sustained
throughput respectively
- Very fast interrupt response
- Four-stage pipeline
• Hardware pipeline interlocks
• Multitasking support
- User/supervisor modes
- Privileged instructions
• Large windowed register file
-136 general-purpose 32-bit registers
• Artificial intelligence support
• High-performance coprocessor interface for user-defined coprocessor
Logic Block Diagram
• FPU interface allows concurrent execution of floating-point instructions
• O.8-micron CMOS technology
• 207-pin grid array package
Overview
The CY7C601A integer unit is a highspeed CMOS implementation of the
SPARC@ 32-bit RISC processor. The
RISCarchitecture makes possible the creation of a processor that can execute instructions at a rate of one instruction per
processorclock. The CY7C601Asupports
a tightly coupled floating-point interface
and coprocessor interface that allows concurrent execution offloating-point, coprocessor, and integer instructions.
Pin Configuration
A(31:0)
PHOLD
ASI(7:0)
FEXC
SIZE(1:0)
DEsnN~ION
FXACK
MAO
FCC(1:0)
REGISTER FILE
136x 32
D(31:0)
-+_--"
SOUR\-C_E_1_ _ _
~
AD~ER
I
r
AND lOGIC
ARITHMETIC
UNIT
L-_~
I
PROGRAM
COUNTERS
II
r
FINS2
MOLDA
FPSYN
MOLDB
BHOLD
I I
_ _~
!
TOE
7C601 A
COE
CLK
SHIFT UNIT
SPARC
IRL 3:0
L _ _ _ _~
INTACK
~
PROCESSOR
INST
FLUSH
MEXC
RESET
ERROR
ALIGN
1 1 ~:~~Tr~D'II
-1..--.--'"-
CE
SOUI 2
FCCV
FINS1
MOll
INSTRUCTION
DECODE
TIW' BASE
1
ADDRESS
RD
WE
ALIGN
T
INSTRUCTION/D~A
B01M
WRT
DXFER
CHOLO
LOSTO
CEXC
INULL
CXACK
LOCK
DOE
CCC(1:0)
AOE
CCCV
CINS1
1FT
CINS2
601A-2
Selection Guide
7C60lA-40
650
MaximumOperating Current (rnA)
SPARe is a registered trademark of SPARClnternational, Inc.
8-6
7C60lA-33
600
7C601A-25
600
--: :l?:
CYPRFSS
_
F
CY7C601A
SEMICONDUCTOR
Overview (continued)
The CY7C601A SPARC processor provides the following features:
Simple instruction format. All instructions are 32-bits wide
and aligned on 32-bit boundaries in memory. The three basic instruction formats feature uniform placement of opcode and address fields.
Register intensive architecture. Most instructions operate on
either two registers or one register and a constant, and place the
result in a third register. Only load and store instructions access
off-chip memory.
Large windowed register tile. The processor has 136 on-chip
32-bit registers configured as eight overlapping sets of 24 registers each and eight global registers. This scheme allows compilers to cache local values across subroutine calIs and provides a
register-based parameter passing mechanism.
Delayed control transfer. The processor always fetches the next
instruction after a control transfer, and either executes it or annus it depending on the state of a bit in the control transfer instruction. This feature allows compilers to rearrange code to
place a useful instruction after a delayed control transfer and
thereby take better advantage of the processor pipeline.
Concurrent floating-point Floating-point instructions can execute concurrently with each other and with non-floating-point instructions.
Fast interrupt response. Interrupt inputs are sampled on every
clock cycle and can be acknowledged in one to three cycles. The
first instruction of an interrupt service routine can be executed
within 6 to 8 cycles of receiving the interrupt request.
The 7C600 Family
The SPARC processor family consists of a CY7C601A integer
unit to perform all non-floating-point operations and a
CY7C602A floating-point unit (FPU) to perform floating-point
arithmetic concurrent with the CY7C601A. Support is also provided for a second generic coprocessor interface. The
CY7C601A communicates with external memory via a 32-bit address bus and a 32-bit data/instruction bus. In typical data processing applications, the CY7C601A and CY7C602A are combined with a high-performance CY7C604A memory
management unit and cache controller and a cache memory implemented with CY7C157A 16-Kbyte x 16 cache RAMS. In
many dedicated controller applications the CY7C601A can function by itself with only high-speed local memory.
Coprocessor InterCace
The CY7C601A is the basic processing engine that executes all
of the instruction set except for floating-point operations. The
CY7C601A and CY7C602A operate concurrently. The
CY7C602A recognizes floating-point instructions and places
them in a queue while the CY7C601A continues to execute
non-floating-point instructions. If the CY7C602A encounters an
instruction that will not fit in its queue, the CY7C602A holds the
CY7C601A until the instruction can be stored. The CY7C602A
contains its own set of registers on which it operates. The contents of these registers are transferred to and from external
memory under control of the CY7C601A via floating-point
load/store instructions. Processor interlock hardware hides
floating-point concurrency from the compiler or assembly language programmer. A program containing floating-point computations generates the same results as if instructions were executed sequentially.
8-7
Registers
The CY7C601A contains a large 136 x 32 triple-port register file
which is divided into 8 windows, each with 24 working registers
and each having access to the same 8 global registers. A current
window pointer (CWP) field in the processor state register keeps
track of which window is currently active. The CWP is decremented when the processor calls a subroutine and is incremented when the processor returns. The registers in each
window are divided into ins, outs, and locals. The eight global
registers are shared by all windows and appear as registers 0- 7
in each window. Registers 8-15 serve as outs, registers 16-23
as locals, and 24-31 serve as ins. Each window shares its ins and
outs with adjacent windows. The outs of the previous window are
the ins of the current window, and the outs of the current window are the ins of the next window. The globals are equally
available to all windows and the locals are unique to each window. The windows are joined together in a circular stack where
the outs of window 7 are the ins of window o.
Multitasking Support
The CY7C601A supports a multitasking operating system by
providing user and supervisor modes. Some instructions are
privileged and can only be executed while the processor is in supervisor mode. Changing from user to supervisor mode requires
taking a hardware interrupt or executing a trap instruction.
Interrupts and Traps
The CY7C601A supports both asynchronous traps (interrupts)
and synchronous traps (error conditions and trap instructions).
Traps transfer control to an offset within a table. The base address of the table is specified by a trap base register and the offset is a function of the trap type. Traps are taken before the current instruction causes any changes visible to the programmer
and can therefore be considered to occur between instructions.
Instruction Set Summary
Instructions fall into five basic categories as follows:
1. Load and store Instructions. Load and store are the only instructions which access external memory. They use two
CY7C601A registers or one CY7C601A register and a signed immediate value to generate the memory address. The instruction
destination field specifies either an CY7C601A register, a
CY7C602A register, or a coprocessor register as the destination
for a load or source for a store. Integer load and store instructions support 8-, 16-, 32-, and 64-bit transfers while floating-point
and coprocessor instructions support 32- and 64-bit accesses.
2. Arithmetic/logicaVshift. These instructions compute a result
that is a function of two source operands and write the result
into a destination register or discard it. They perCorm arithmetic,
tagged arithmetic, logical, and shift operations. An instruction
SETHI, useful in creating 32-bit constants in two instructions,
writes a 22-bit constant into the high order bits of a register and
zeroes the remaining bits. The contents of any register can be
shifted left or right any number of bits in one clock cycle as
specified by a register or the instruction itself. The tagged instructions are useful in artificial intelligence applications.
3. Control transfer. Control transfer instructions include jumps,
calls, traps and branches. Control transfer is usually delayed so
that the instruction immediately following the control transfer
(called the delay instruction) is executed before control is transferred to the target location. The delay instruction is always
•
oU)
a:
~~
~ ~NDUcroR
CY7C601A
Instruction Set Summary (continued)
fetched,however, a bit in the control transfer instruction can cause
the delay instruction to be nullified if the branch is not taken. This
flexibility increases the likelihood that a useful instruction can be
placed after the control transfer thereby fIlling an otherwise unused hole in the processors pipeline. Branch and call instructions
use program counter relative displacements. Ajump and link instructionusesaregisterindirectdisplacementcomputingitstarget
address as either the sum of two registers or the sum of a register
and a 13-bit signed immediate value. The branch instruction provides a displacement plus or minus 8 megabytes, and the call instructions 30-bit displacement allows transfer to almost any address.
4. Read/write control registers. The processor provides special
instructions to read and write the contents of the various control
registerswithin the machine. These registers include the multiply
step register, processor state register, window invalid mask register, and trap base register.
S. Floating-point/coprocessor instructions. These instructions
include all floating-point conversion and arithmetic operations as
well as future coprocessor instructions. These instructions involve
operations only on the contents of the register fIle internal to the
CY7C602Aorcoprocessor.
The instruction set of the processor is summarized in Table 1.
Registers
ThefollowingsectionsprovideanoverviewoftheCY7C601Aregisters. The CY7C601A has two types of registers; working registers (r registers), and control registers. The r registers provide
storage for processes, and the control registers keep track of and
control the state of the CY7C601A
r Registers. The r registers (Figure 1) consist of eight 32-bit
global registers, and 8 windows, each having twenty-four 32-bit
registers. Each two adjacent windows are overlapped in eight
registers. This results in a total of 136 32-bit general purpose registers on the chip.
CY7C60lA Control Registers. The CY7C601A control registers
contain various addresses and pointers used by the system to control its internal state. They include the program counters (PC and
nPC), the processor state register (PSR), the window invalid mask
register (WIM), the trap base register (TBR), and the Y register.
The following paragraphs briefly describe each:
Processor Status Register (PSR). The processor status register
contains fields that describe and control the state of the
CY7C601A (see Figure 2).
IU Implementation and IU Version Numbers (IMPL field,
PSR<31:28>; VER field, PSR<27:24». These are read-only
fields in the PSR. The version number and the implementation
number are each set to "0001".
Integer Condition Codes (PSR <23:20». The integer condition
codes consist of four flags: negative, zero, overflow, and carry.
Theseflags are set by the conditions occurring during integer logic
and arithmetic operations.
Enable Coprocessor (EC bi~ PSR<13». This bit is used to enable the coprocessor. If a coprocessor operation (CPop) is encountered and the EC bit is cleared (i.e., coprocessor disabled), a
coprocessor disabled trap is generated.
Enable Floating Point Unit (EF bit, PSR<12». This bit is used to
enable the floating point unit. If a floating point operation (FPop)
is encountered and the EF bit is cleared (i.e., FPU disabled), a
floating point disabled trap is generated.
Processor Interrupt Level (PIL field, PSR<11:8». This four bit
field sets the CY7C601A interrupt level. The CY7C601A will
only acknowledge interrupts greater than the level indicated by
the PIL field. Bit 11 is the MSB; bit 8 is the LSB.
Supervisor Mode (S bit, PSR<7». S = 1 indicates that the
CY7C601Ais in supervisor mode. Supervisor mode can only be
entered by a software or hardware trap.
Previous Window
r31
r24
r~3
de
r1,5
r8
Jl
INS
Trap Enable (El]
LOCALS
'r.$1
OUTS
INS
r24
r~
-1"16'
LOCALS
r1;6"
,OUTS
iii
Next Window
r31
da
r 1,5
I
r7
IU
r8
.
INS
Number
LOCALS
~
1
(impl.)
I
31
4
l
l
Processor
Interrupt
(ver,)
I
26
4
(ICC)
I
24
OUTS
4
6
'., '..
11H
141312
22
1111111
8 78 5
Current
Window
Pointer
(CWP)
5
cany
(z)
23
~~
Reserved
I
zero
,
~:
r 0 GLO,!3AI.S
_ . ,
Number
Implementation
r24
r~3
l
Previous Supervisor Mode (PS) ~
Supervisor Mode (5)
Enable Floating P oint Unit (EF)
Enable Coprocessor (Ee)
Integer Condition Codes
IUVersion
Current Window
(0)
21
20
601A-4
601A-3
Figure 2. Processor State Register
Fignre 1. Register Windows
8-8
I
-~
CY7C601A
_'ii!CYPRESS
- . F SEMICONDUCTOR
Thble 1. Instruction Set Summary
Inputs
jg
e>
;:
"
~
.s
~
.s
"-'
.
"8
..
~
~
~
...
"-'
;;;,
.!l
~
;:
~
ofi
~
.
oSl
jg
~
]
e
e>
U
LDSB(LDSBA *)
LDSH(LDSHA *)
LDUB(LDUBA *)
LDUH(LDUHA*)
LD(LDA*)
LDD(LDDA*)
LDF
LDDF
LDFSR
LDC
LDDC
LDCSR
STB(STBA*)
STH(STHA*)
ST(STA*)
STD(STDA*)
STF
STDF
STFSR
STDFQ*
STC
STDC
STCSR
STDCO*
LDSTUB(LDSTUBA *)
SWAP(SWAPA*)
ADD(ADDcc)
ADDX(ADDXcc)
TADDcc(TADDccTV)
SUB(SUBcc)
SUBX(SUBXcc)
TSUBcc(TSUBccTV)
MULScc
AND(ANDcc)
ANDN(ANDNcc)
OR(ORcc)
ORN(ORNcc)
XOR(XORcc)
XNOR(XNORcc)
SLL
SRL
SRA
SETHI
SAVE
RESTORE
Bicc
FBicc
CBccc
CALL
JMPL
RETT
Ticc
Operation
t=
Cycles
Load Signed Byte
(from Alternate Space)
Load Signed Halfword
AlW=W Space
Load Unsigned Byte
from Alternate
Load Unsigned Halfword
from Alternate Space
from Alternate Space
Load Word
Load Doubleword
Load Floating Point
Load Double Floating Point
Load Floating Point State Register
LoadCoprocessor
Load Double Coprocessor
Load Coprocessor State Register
Store Byte
(into Alternate Space)
Store Halfword
~into Alternate Space~
Store Word
into Alternate Space
Store Doubleword
into Alternate Space
Store Floating Point
Store Double Floating Point
Store Floating Point State Register
Store Double Floating Point Queue
Store Coprocessor
Store Double Coprocessor
Store Coprocessor State Register
Store Double Coprocessor Queue
Atomic Load/Store Unsigned Byte
~inAlternate Space~
Swap r Register with Memory
in Alternate Space
Add
~mOdifyiCC)
Add with Carry
modify icc)
Tagged Add and modify icc
(and nap on overflow)
Subtract
(modify icc)
Subtract with Carry
(modify icc)
Thgged Subtract and modify icc
(and nap on overflow)
Multiply Step and modify icc
(and modify icc
And
And Not
~ and modify icc
and modify icc
Inclusive Or
Inclusive Or Not
and modify icc
Exclusive Or
~ and modify icc
and modify icc
Exclusive Nor
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic
Set High 22 Bits of r Register
Save Caller'swindow
Restore Caller'swindow
Branch on Integer Condition Codes
Branch on Floating Point Condition Codes
Branch on Coprocessor Condition Codes
Call
Jump and Link
Return from nap
nap on Integer Condition Codes
Sp=j
~fromAlternatespace
8-9
2
2
2
2
2
3
2
3
2
2
3
2
3
3
3
4
3
4
3
4
3
4
3
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1*'
1-'
1**
1*'
2**
2'1 (4 if Thken)
CY7C601A
'Thble 1. Instruction Set Summary (continued)
Inputs
5
i~
~~
u=
!i:~1S.
~O
Operation
RDY
RDPSR
RDWIM
RDTBR
WRY
WRPSR*
WRWIM*
WRTBR*
UNIMP
IFLUSH
FPop
CPop
Cycles
Read Y Register
Read Processor State Register
Read Window Invalid Mask
Read nap Base Register
Write Y Register
Write Processor State Register
Write Window Invalid Mask
Write nap Base Register
UnimplementedInstruction
Instruction Cache Flush
Floating Point Unit Operations
CoprocessorOperations
• Privileged instruction.
1
1
1
1
1
1
1
1
1
1
1 to Launch
1 to Launch
•• Assuming delay slot is filled with useful instruction.
Processor Statos Register(continued)
WindowO
Window 1
Previous Supervisor Mode (PS bit, PSR<6». This bit indicates
Bo~=:-lll
the state of the supervisor bit before the most recent trap.
Trap Enable (ET bit, PSR<5». This bit enables or disables the
CY7C601A traps. This bit is automatically set to 0 (traps disabled) upon entering a trap. WhenET = 0, all asynchronous traps
are ignored. If a synchronous trap occurs when ET = 0, the
CY7C601Aenters error mode.
Reserved
'ftap Base Register (TBR). The trap base register contains the
base address of the trap table and a field that provides a pointer
into the trap table.
Trap Base Address
Trap Type (tt)
20
31
Reserved
B
12 11
4 3
0
Figure 3. 'frap Base Register
Wmdow Invalid Mask Register (WIM). The window invalid
maskregister determines which windows are valid and which window accesses cause window_overflow and window_underflow
traps.
o
31
Current Window Pointer (CM field, PSR<4:0». The r registers
are addressed by the current window pointer (CWP), a field of the
processor status register (PSR), which points to the 24 active local
registers. It is incremented by a RESTORE instruction and decremented by a SAVE instruction. Note that the globals are always
accessible regardless of the CWP. In the overlapping configuration each window shares its ins and outs with adjacent windows.
The outs from a previous window (CWP + 1) are the ins of the currentwindow, and the outs from the current window are the ins for
the next window (CWP -1). In both the windowed and register
bank configurations globals are equally available and the locals
are unique to each window.
Program Counters (PC and nPC). The program counter (PC)
holds the address of the instruction being executed, and the next
program counter (nPC) holds the address of the next instruction
to be executed.
l
Figure 4. Window Invalid Mask
Y register. The Y register is used to hold the partial product during execution of the multiply-step instruction (MULSCC).
Pin Description
The integer unit's external signals fall into three categories:
(1) memory subsystem interface signals, (2) floating-point unit!
coprocessorinterface signals, and (3) miscellaneous I/O signals.
Theseare described in the following sections. Paragraphs after the
tables describe each signal. Signals that are active LOW are
markedwith an overcomer; all others are active HIGH. Forexampie, WE is active LOW, while RD is active HIGH.
Memory Subsystem Interface Signals
A[31:0j. These 32 bits are the addresses ofinstructions or data
and they are sent out "unlatched" by the integer unit. Assertion of
the MAO signal during a cache miss will force the integer unit to
put the previous (missed) address on the address bus. A[31 :0] pins
are three-stated if the AOE or TOE signal is deasserted.
ASI[7:0j. These 8 bits are the address space identifier for an
instruction or data access to the memory. ASI[7:0] are sent out
"unlatched" by the integer unit. The value on these pins during
any given cycle is the address space identifier corresponding to the
memory address on the A[31 :0] pins at that cycle. Assertion of the
MAO signal during a cache miss will force the integer unit to put
the previous address space identifier on the ASI[7:0] pins.
ASI[7:0] pins are three-stated if the AOE or TOE signal is deas-
8-10
.
~
~=CYPRESS
CY7C601A
~.iF' SEMICONDUCIOR
serted. Normally, the encoding of the ASI bits is as shown in
Table 2. The remaining codes are software generated.
llIble 2. ASI Bit Assignment
Address Space Identifier (ASI)
00001000
00001010
00001001
00001011
Address Space
User Instruction
User Data
Supervisor Instruction
Supervisor Data
D[31:0j. D[3l:0) is the bidirectional data bus to and from the integer unit. The data bus is driven by the integer unit during the
execution of integer store instructions and the store cycle of
atomicloadlstore instructions. Similarly, the data bus is driven by
the floating-point unit only during the execution offloating-point
store instructions. The store data is sent out unlatched and must
be latched externally before it is used. Once latched, store data is
valid during the second data cycle of a store single access, the second and third data cycle of a store double access, and the third
data cycle of an atomic load store access. The alignment for load
and store instructions is done inside the processor. A double word
is aligned on an 8-byte boundary, a word is aligned on a 4-byte
boundary, and a half word is aligned on a 2-byte boundary. D(31)
corresponds to the most significant bit of the least significant byte
ofthe 32-bit word. If a double word, word, or half word load or
store instruction generates an improperly aligned address, a memory address not aligned trap will occur. Instructions and operands
are always expected to be fetched from a 32-bit wide memory.
SIZE[1:0j. These two bits specify the data size associated with a
data or instruction fetch. Size bits are sent out "unlatched" by the
integer unit. The value on these pins at any given cycle is the data
size corresponding to the memory address on the A[3l:0) pins at
that cycle. SIZE[l:O) remains valid on the bus during all data cyclesofloads, stores, load doubles, store doubles and atomicload
stores. Since all instructions are 32-bitslong, SIZE[l:O) is set to
"10" during all instruction fetch cycles. Encoding of the SIZE[l :0)
bits is shown in Table 3.
llIble 3. Size Bit Assignment
Size 1
0
0
1
1
Size 0
0
1
0
1
Data lhmsfer lYPe
Byte
Halfword
Word
Word (Load/Store Double)
MHOLDA and MHOLDR The processor pipeline will be frozen
while MHOLDA or MHOLDB is asserted and the CY7C60lA
outputs will revert to and maintain the value they had at the rising
edge of the clock in the cycle before MHOLDAor MHOLDBwas
asserted. MHOLDA/B is used to freeze the clock to both the integer and floating point units during a cache miss (for systems with
cache) or when a slow memory is accessed. This signal must be
presentedto the processor chip at the beginning of each processor
clock cycle and be stable during the high time of the processor
clock:. Either MHOLDA or MHOLDB can be used for stopping
the processor during a cache miss or memory exception.
MHOLDB has the same defmition as MHOLDA The processor
hardware uses the logical "OR" of all hold signals (i.e., MHOLDA, MHOLDB and BHOLD) to generate a final hold signal for
freezing the processor pipeline. All HOLD signals are latched
(transparentlatch) in the CY7C60lA before they are used.
BHOLD. BHOLD is asserted by the I/O controller when an external bus master requests the data bus. Assertion of this signal
will freeze the processor pipeline. Extemallogicshouldguarantee
thatafterdeassertion ofBHOLD, the data at all inputs to the chip
is the same as what itwasbeforeBHOLDwasasserted.Thissignal
must be presented to the processor chip at the beginning of each
processor clock cycle and be stable during the high time of the
processorciocksincetheCY7C60lAprocessestheBHOLDinput
through a transparent latch before it is used. BHOLD should be
used only for bus access requests by an external device since the
MDS and MEXC signals are not recognized while this input is active. BHOLD should not be deasserted while LOCK is asserted.
MDS. Assertion of this signal will enable the clock input to the
on-chip instruction register (during an instruction fetch) or to the
load result register (during a data fetch). In a system with cache,
MDS is used to signal the processor when the missed data (cache
miss) is ready on the bus. In a system with slowmemories,MDS is
used to signal the processor when the read data is available on the
bus. MDS must be asserted only while the processor is frozen by
either the MHOLDA or MHOLDB input signals. The
CY7C60lA samples the MDS signal via an on-chip transparent
latch before it is used. The MDS signal is also used for strobing
memory exceptions. In other words, MDS should be asserted
whenever MEXC is asserted (see MEXCdefinition).
MEXC. This signal is asserted by the memory (or cache) controller to initiate an instruction (or data) exception trap. MEXC is
latched in the processor at the rising edge of CLK and is used in
the following cycle. If MEXC is asserted during an instruction
fetch cycle an instruction access exception is generated, and if
MEXC is asserted during a data fetch cycle, a data access exception trap is generated. The MEXC signal is used during
(MHOLD) in conjunction with the MDS signal to indicate to the
CY7C60lAthat the memory system was unable to supp!y~id instruction or data. If MDS is applied without MEXC, the
CY7C60lAaccepts the contents ofthe data bus as valid information but when MDS is applied with MEXC an exception trap is
generated and the contents of the data bus is ignore~e
CY7C60lA(i.e., MHOLD and MDS must be low when MEXC is
asserted). MEXC must be deasserted in the same clock cycle in
which MHOLD is released.
AOE. Deassertion of this signal will three-state all output drivers
associatedwithA[3l:0) andASI[7:0) outputs. AOE is connected
directly to the output drivers of the address and ASI signals and
must be asserted during normal operations. This signal should be
deasserted only when the bus is granted to another bus master
(i.e., when either BHOLD, MHOLDAor MHOLDBisasserted).
DOE. Deassertion of this signal will three-state all output drivers
of the data D[3l :0) bus. DOE is connected directly to the data bus
output drivers and must be asserted during normal operations.
This signal should be deasserted only when the bus is granted to
another bus master (i.e., when either BHOLD, MHOLDA or
MHOLDBis asserted).
COE. Deassertion of this signal will three-state all output drivers
associated with SIZE[l:O), RD, WE, WRT, LOCK, LDSTO and
DXFER outputs. COE is connected directly to the output drivers
and must be asserted during normal operations. This signal
should be deasserted only when the bus is granted to another bus
master (i.e., when either BHOLD, MHOLDA, or MHOLDB is
asserted).
8-11
.'
0
U)
a:
CY7C601A
RD. This signal specifies whether the current memo!), access is
a read or write operation. It is sent out "unlatc~e~" by the intc:ger unit and must be latched externally before It IS used. RD IS
set to "0" only during address cycles of store instructions including the store cycles of atomic load store instructions. This signal
when used in conjunction with SIZE[1:0], ASI[7:0], and LDSTO,
can be used to check access rights of bus transactions. In addition, the RD signal may be used to tum off the output drivers of
data RAMs during a store operation. For atomic load store instructions the RD signal is "1" during the first address cycle
(read cycle) and "0" during the second and third address cycles
(write cycle).
WE. This signal is asserted by the integer unit during the second address cycle of store single instructions, the second and
third address cycles of store double instructions, and the third
address cycle of atomic load/store instructions. The WE signal is
sent out "unlatched" and must be latched externally before it is
used. The WE s~ may be externally qualified by HOLD sigand MHOWB) to avoid writing into the
nals (i.e., MHO
memo!), during memo!), exceptions.
WRT. This signal is asserted (set to "1") by the processor during
the first address cycle of single or double integer store instructions, the first address cycle of single or double f1oatinll-point
store instructions, and the second address cycle of atomic load/
store instructions. WRr is sent out ''unlatched'' and must be
latched externally before it is used.
LDSTO. This signal is asserted by the integer unit during the
data cycles of atomic load store operations. LDSTO is sent out
"unlatched" by the integer unit and must be latched externally
before it is used.
LOCK. This signal is set to "1" when the processor needs the
bus for multiple cycle transactions such as atomic load/store,
double loads and double stores. WCK signal is sent "unlatched" and should be latched externally before it is used. The
bus may not be granted to another bus master as long ~ WCK
signal is asserted (i.e.,llllOID should not be asserted In the following processor clock cycle when LOCK=1).
DXFER. This signal is asserted by the processor at the beginning of all bus data transfer cycles. DXFER is "unlatched" and
DXFER = 1 indicates a data cycle.
INULL. Assertion ofINULL indicates that the current memo!),
access (whose address is held in an external latch) is to be nullified by the processor. INULL is intended to be used to disable
cache misses (in systems with cache) and to disabl~ memo~ exception generation for the current memo!), access (I.e., MD and
MEXC should not be asserted for a memo!), access when INULL=1). INULL is a latched output and is active during the
same cycle as the address, which it nullifies (the address is not on
the bus, but is latched externally). INULL is asserted u";der the
following conditions: During the second cycle of a store inStruction, or whenever the CY7C601A address is invalid due to an external or internal exception. If a floating-point unit or coproceSsor unit is present in the system, INULL should be ORed with the
FNULL and CNULL signals from these units.
1Ft The state of this~ determines the behavior of the
IFLUSH instruction. If IFI'= 1, then IFLUSH executes like a
NOP with no side effects. If lFI'=O, then IFLUSH causes an
unimplemented instruction trap.
Floating-Point/Coprocessor Interface Signals
FP. This signal indicates whether or not a floating-point unit exists in the system. The FP signal is normally pulled up to VDD
by a resistor. It is grounded when the FPU chip is present. The
integer unit generates a floating-point disable trap ifFP = 1 during the execution of a floating-point instruction, FBfcc instruction or floating-point load, and store instructions.
CPO This signal indicates whether or not a coprocessor exists in
the system. The CP signal is normally pulled up !O YOD by a
resistor. It is grounded when the coproc~sor chip ~ ~ent.
The integer unit generates a coproce~r dis~le trap if ~p = 1
during the execution of a coprocesS?r Ins~tion, CBccc !nstruction or coprocessor load and store !nstructions.
FCC[1:0j. These bits are taken as the current condition code
bits of the FPU. They are considered valid if FCCV = 1. During
the execution of the FBfcc instruction, the processor uses these
bits to determine whether the branch should be taken or not.
FCQ1:0] are latched by the processor before they are used.
CCC[1:0j. These bits are taken as the current condition code
bits of the coprocessor. They are considered valid if CCCV=l.
During the execution of the CBccc instruction, the processor uses
these bits to determine whether the branch should be taken or
not. CCC[1:0] are latched by the processor before they are used.
FCcv. This signal should be asserted only when the FCC[1:0]
bits are valid. The floating-point unit deasserts FCCV if pending
floating-point compare instructions exist in the ~oating:poi~t
queue. FCCV is reasserted when the compare Instruction IS
completed and the floating-point condition codes FCQ1:0] are
valid. The integer unit will enter a wait state if FCCV is deasserted (i.e., FCCV = "0"). The FCCV signal is latched (transparent latch) in the CY7C601A before it is used.
CCCv. This signal should be asserted only when th~ CCC[~:O]
bits are valid. The coprocessor deasserts CCCV If pending
coprocessor compare instructions exist i'.' the col?roc:essor queue.
CCCV is reasserted when the compare !nstruction IS completed
and the coprocessor condition codes CCQ1:0] are valid. Th~ integer unit will enter a wait state if CCCV is deasserted (I.e.,
CCCV = "0"). The CCCV signal is latched (transparent latch)
in the CY7C601A before it is used.
mm:J'j. This signal is asserted by the floating-point unit if a
situation arises in which the FPU cannot continue execution.
The floating-point unit checks all dePOndencies in the d~ode
stage of the instruction and asserts FH LD (if necessa!)') In the
next cycle. This signal is used by the integer unit to freeze the
instruction p~eline in the same cycle. The FPU must eventually
deassert FH LD in order to unfreeze the integer unit's pipeline.
The FHOLD signal is latched (transparent latch) in the
CY7C601A before it is used.
CHOLD. This signal is asserted by the copr~cessor if a ~ituation
arises in which the coprocessor cannot continue execution. The
coprocessor checks all deWnden~ies in the dec:ode stage of the
instruction and asserts CH LD (if necessa!)') In the next cycle.
This signal is used by the integer unit to freeze the instruction
pipeline in the same cycle. The coprocess?r must e~~nln:a1ly
deassert CHOLD in order to unfreeze the Integer urnt s pipeline. The mom signal is latched (transparent latch) in the
CY7C601A before it is used.
FEXC. Assertion of t~a1 indicate~ that a f1oatin~-poi";t exception has occurred.
must remain asserted un~i1 the integer unit takes the trap and acknowledges the FPU Via FXACK
signal. Floating-point exceptions are taken only during the execution of floating-point instructions, FBfcc instruction and floating-point load, and store instructions. pnxc is latched in the i";teger unit before it is used. The FPU should deassert FHOLD If
it detects an exception while FHOLD is asserted. In this case
FEXC should be asserted a cycle before FHOLD is deasserted.
8-12
CY7C60lA
CEXC. Assertion of this signal indicates that a coprocessor exception has occurred. This signal must remain asserted until the integer unit takes the trap and acknowledges the coprocessor via
CXACKsignal. Coprocessor exceptions are taken only during the
execution of coprocessor instructions, CBccc instruction and
coprocessor load and store instructions. CEXC is latched in the
integer unit before it is used. The coprocessor should deassert
CHOLD if it detects an exception while CHOLD is asserted. In
this case CEXCshouid be asserted a cycle before CHOLD is deasserted.
INST This signal is asserted by the integer unit whenever a new
instruction is being fetched. It is used by the FPU or coprocessor
to latch the instruction on the D[31:0] bus into the FPU or coprocessor instruction buffer. The FPU (or coprocessor) needs two instruction buffers (Dl and D2) to save the last two fetched instructions. When INST is asserted a new instruction enters into the Dl
buffer and the old instruction in Dl enters into the D2 buffer.
FLUSH. This signal is asserted by the integer unit and is used by
the FPU or coprocessor to flush the instructions in its instruction
registers. This may happen when a trap is taken by the integer
unit. Instructions that have entered into the floating-point (or
coprocessor) queue may continue their execution if FLUSH is
raised as a result of a trap or exception other than floating-point
(or coprocessor) exceptions.
FINSL This signal is asserted by the integer unit during the decode stage of an FPU instruction if the instruction is in the Dl
buffer of the FPU chip. The FPU uses this signal to latch the instruction in D 1 buffer into its execute stage instruction register.
FINS2. This signal is asserted by the integer unit during the decode stage of an FPU instruction if the instruction is in the D2
buffer of the FPU chip. The FPU uses this signal to latch the instruction in D2 buffer into its execute stage instruction register.
CINS!. This signal is asserted by the integer unit during the decode stage of a coprocessor instruction if the instruction is in the
Dl buffer of the coprocessor chip. The coprocessor uses this signal to latch the instruction in D 1 buffer into its execute stage instructionregister.
CINS2. This signal is asserted by the integer unit during the decode stage of a coprocessor instruction if the instruction is in the
D2 buffer of the coprocessor chip. The coprocessor uses this signal to latch the instruction in D2 buffer into its execute stage instructionregister.
FXACK. This signal is asserted by the integer unit in order to acknowledge to the FPU that the current FEXC trap is taken. The
FPU must deassert FEXC after it receives an asserted level of
FXACKsignal so that the next floating-point instruction does not
cause a "repeated" floating-point exception trap.
CXACK. This signal is asserted by the integer unit in order to acknowledge to the coprocessor that the current CEXC trap is
taken. The coprocessor must deassert CEXC after it receives an
asserted level of CXACK signal so that the next coprocessor instructiondoes not cause a "repeated" coprocessor exception trap.
Miscellaneous I/O Signals
IRL[3:0]. The data on these pins defines the external interrupt
level. IRL[3:0] =0000 indicates that no external interrupts are
pending. The integer unit uses two on-chip synchronizing latches
to sample these signals on the rising edge of CLK. A given interrupt level must remain valid for at least two consecutive cycles to
be recognized by the integer unit. IRL[3:0]=1111 signifies an
non-maskable interrupt. All other interrupt levels are maskable
by the PIL field of the processor state register (PSR). External interrupts should be latched and prioritized by the external logic before they are passed to the integer unit. The external interrupt
latches should keep the interrupts pending until they are taken
(and acknowledged) by the integer unit. External interrupts can
be acknowledged by software or by the Interrupt Acknowledge
(INTACK) output.
INTACK. This signal is asserted by the integer unit when an external interrupt is taken.
RESET Assertion of this pin will reset the integer unit. The RESET signal must be asserted for a minimum of eight processor
clock cycles. After a reset, the integer unit will start fetching from
address O. The RESET signal is latched by the integer unit before
it is used.
ERROR This signal is asserted by the integer unit when a trap is
encountered while traps are disabled via the ET bit in the PSR. In
this situation the integer unit saves the PC and nPC registers, sets
the tt value in the TBR, enters into an error state, asserts the ERROR signal and then halts. The only way to restart the processor
~ed in the error state, is to trigger a reset by asserting the RESET signal.
TOE. This signal is used to force all output drivers of the processor chip into a high-impedance state. It is used to isolate the chip
from the rest of the system for debugging purposes.
FPSYN. This pin is a mode pin which is used to allow execution of
additional instructions in future designs. It should be normally
kept deasserted (FPSYN =0) to disable the execution of these instructions.
CLK. CLK is a 50% duty-cycle clock used for clocking the
CY7C601A:s pipeline registers. It is HIGH during the first half of
the processor cycle, and LOW during the second half. The rising
edge of CLK defines the beginning of each pipeline stage in the
CY7C601Achip.
Document#: 38-R-lOoo1-A
8-13
•
CY7C602A
CYPRESS
SEMICONDUCTOR
Features
• Direct interface to CY7C601 integer
unit
• Direct interface to CY7C157 Cache
Storage Unit (CSU)
• FulIcompliancewitbANSI/IEEE-754
standard for binary floating-point
arithmetic
• Supports single and double precision
floating~point operations
• 6.15 MFLOPs peak doubleprecision performance at 40 MHz
• SPARC-compatible interface allows
concurrent execution of integer and
Boating-point instructions
Floating-Point Unit
• Hardware interlocks synchronize integer unit and floating-point unit operations
• 64-bit multiplier and divide/square
root unit
• 64-bitALU
• 16 64-bit registers or 32 32-bit
registers in a three-port floating-point
register tile with an independent load!
store port.
• 144-pinPGApackage
• Available in speeds of 25, 33, and 40
Description
TheCY7C602Ais a high-speed SPARC®compatible floating-point unit for use with
the CY7C601A integer unit.
The
CY7C602Af1oating-point unit allows floating-point instructions to execute concurrently with CY7C601A integer unit
instructions. The CY7C602A interfaces
directly to the CY7C601A integer unit
without glue logic. The CY7C602A provides a peak 6.15 MFLOPS of doubleprecisionperformance at 40 MHz.
MHz
Logic Block Diagram
Pin Configuration
A
32
64
ADORESS
PIPE
INSTRUCTION
PIPE
0(31:0)
A(31:0)
Ff>
RESET
FHOlO
FEXC
MHOlOA
FCCV
MHOlOB
MOS
64
BHOLD
FNUll
7C602A
FLOATING-POINT
UNIT
FCC(1:0L
INST
FINS1
FINS2
DOE
CCCV
FLUSH
CHOLD
FXACK
ClK
?
C602-2
64
o (SAME AS INPUT D)
C602-1
Selection Guide
MaximumSupply Current (rnA)
Commercial
SPARC is a registered trademark of SPARCIntemational, Inc.
8-14
7C602A-40
7C602A-33
7C602A-25
450
400
350
CY7C602A
7C601A
INTEGER
UNIT
INST
FINS1
FINS2
FWSH
FleA K
7C602A
FLOATING-POINT
UNIT
1'1'
FCC(1:0)
FCCV
1'Rlmf
1'EXC
9-
...
~
9-
§'
e.
Ii=!
~ ~
0
I'" ~ I~ I~ 18
:> U)
:j
z w
LL
0:
Ii
ADDRESS BUS
.A
....
-
--""
DATA BUS
.A
....
--"
CONTROL SIGNALS
...
--""
...
C602-3
Figure 1. CY7C60lA - CY7C602A Hardware Interface
Functional Description
The CY7C602A floating-point unit is a high-performance,
single-chip implementation of the SPARC reference floatingpoint unit The CY7C602A FPU directly interfaces with the
CY7C601A integer unit, providing concurrent floating-point and
integer instruction execution. The Cypress 7C600 chipset, comprised of the CY7C601A integer unit, CY7C602A floating-point
unit, CY7C604A cache controller and memory management
unit, and two CY7C157A CSUs, constitutes a high-performance
CPU requiring no interface logic. The Cypress 7C600 chip-set is
available in speeds up to 40 MHz, providing a sustained 29
MIPS of integer unit performance and over 6 MFLOPS of double-precision floating-point performance.
The CY7C602A supports single and double precision floatingpoint operation. Double precision floating-point is efficiently
executed in the CY7C602A using a 64-bit internal datapath.
The floating-point datapath circuitry contains a 64-bit multiplier,
a 64-bit ALU, and a 64-bit divide/square-root unit. The
CY7C602A provides thirty-two 32-bit floating-point registers,
which can be concatenated for use as 64-bit registers. The
CY7C602A complies with the ANSI/IEEE-754 floating-point
standard.
The CY7C602A supports the execution of SPARC floating-point
instructions. These instructions are separated into two groups:
floating-point load/store and floating-point operate instructions
(FPops). Floating-point load/store instructions are used to transfer data to and from the data registers (f registers). FP load/store
instructions also allow the CY7C601A integer unit to read and
write the floating-point status register (FSR) and to read the
front entry of the floating-point queue. Floating-point operate
instructions (FPops) include basic numeric operations (add, subtract, multiply, and divide), conversions between data types, register to register moves, and floating-point number comparison.
FPops operate only on data in the floating-point registers. floating-point branch instructions are executed by the IU on the basis of FP condition codes, and are not executed by the FPU.
The SPARC floating-point/integer unit interface provides concurrent execution of integer and floating-point instructions. The
CY7C601A integer unit fetches all instructions for both itself
and the CY7C602A FPU, providing all addressing and control
signals. The CY7C602A floating-point unit latches all integer
and floating-point instructions in parallel with the CY7C601A.
When the CY7C601A decodes a floating-point instruction, itsignals the CY7C602A with the flNS1 or flNS2 signal. This starts
the execution of the floating-point instruction by the
CY7C602A.
CY7C602A Registers
The CY7C602A has three types of user-accessible registers: the f
registers, the FP ~ueue, and the floating-point sta~ register
(FSR). The f registers are the CY7C602A data registers. The
FSR is the CY7C602A status and operating mode register. The
FP queue contains the CY7C602A instructions that h~ve sta~ed
execution and are awaiting completion. The followmg section
describes these registers in detail.
fRegisters
The CY7C602A provides 32 registers for floating-point operations, referred to as f registers. These registers are ~2 bits in
length, which can be concatenated to support 64-blt double
words.
Integer and single precision data reqnires a single 32-bit f register. Double precision data reqnires 64 bits of storage and occupies an even-odd pair of adjacent fregisters. Extended precision
data requires 128 bits of storage and occupies a group of four
consecutive f registers, always starting with register f4, fS, f12,
f20, f24, or f28.
The CY7C602A forces register addressing to match the data
type specified by the floating-point instruction. This ensures
data alignment in the f register file for double and extended precision data. FIgUre 2 illustrates how the CY7C602A uses the five
8-15
ro,
•
.
~
CY7C602A
~=CYPRESS
- , SEMICONDUCTOR
register address bits in a floating-point instruction for the different types of data. Single data word transfers (integer, single-precision floating-point) can be stored in any register. Consequently, all five bits of the register address specified in the
floating-point instruction are valid. Double-precision data must
reside in an even-odd pair of adjacent registers. By ignoring the
LSB of the register address for a FPop requiring a register pair,
the CY7C602A ensures data alignment. In a similar manner, the
two LSBs of the register address are ignored in a SPARC FPU
that supports extended precision data.
r-:
:I
rd,rSl,
or rs2 field
of FP instruction
.---.---.--,---.---.
I
single precision
and integer data .
I
.
all five bits of
register address
are used
I_"'---I_-'-__• ·."'·.·.· " l
double precision data ...
extended
precision data
LSB is ignored
2 LSB's are
ignored
Figure 2. f Register Addressing
FPQueue
The CY7C602A maintains a floating-point queue of instructions
that have started execution, but have yet to complete execution.
The FP queue is used to accommodate the multiple clock nature
of floating-point instructions. It also allows the CY7C602A to
optimize execution through the use of data forwarding. Data
forwarding allows FPop results to be used by a subsequent FPop
before the results have been stored in its destination register.
This saves one clock of execution time for each instruction that
uses this feature.
The other purpose of the FP queue is to support the handling of
FP exceptions. When the CY7C602A encounters an exception
case, it enters pending exception mode and waits for the next FP
instruction to be executed. When the CY7C60lA decodes a FP
instruction following the exception, it asserts the FINSl or
FINS2 ~ The CY7C602A then enters exception mode and
asserts FEXC to signal a floating-point exception. When the
CY7C602A enters the exception mode, floating-point execution
halts until the FP queue is emptied. This allows the CY7C60lA
to store the floating-point instructions under execution when the
exception case occurred. Emptying the FP queue frees the
CY7C602A for use by the trap handler without losing the preexception state of the CY7C602A. After the trap handler finishes execution, the CY7C60lA again fetches the FPop instructions previously stored in the FP queue, thus bringing the
CY7C602A back to its previous state.
The FP queue contains the 32-bit address and 32-bit FPop instruction of up to three instructions under execution. Only FPop
instructions are queued. The top entry of the FP queue is accessible by executing the store double floating-point queue
(STDFQ) instruction. A load FP queue instruction does not exist, as the FP queue must be re-initialized by launching the
queued instructions.
Floating.Point Status Register (FSR)
The following paragraphs describe the bit fields of the Floatingpoint status register (FSR). Figure 3 illustrates the bit assignments for the FSR. Refer to Table 1 (following page) for bit assignments for the FSR fields.
RDFSR(31:30). Rounding Direction: These two bits define the
rounding direction used by the CY7C602A during an FP arithmetic operation.
RP FSR(29:28). Rounding Precision: These two bits define the
rounding precision to which extended results are rounded. This
is in accordance with the ANSIJIEEE STD-745-1985.
TEM FSR(27:23). Trap Enable Mask: These five bits enable
traps caused by FPops. These bits are ANDed (1 = enable, 0=
disable) with the bits of the CEXC (current exception field) to
determine which traps will force a floating-point exception to the
CY7C60lA. All trap enable fields correspond to the similarly
named bit in the CEXC field (see below). The TEM field only
affects which bits in the CEXC field will cause the FEXC signal
to be asserted. ALL trap types, regardless of the state of the
TEM field, are reported in the AEXC and CEXC fields.
NS FSR(22). Non-Standard Floating Point: This bit enables
non-standard floating-point operations in the CY7C602A.
version FSR(19:17). The version number is used to identify the
SPARC floating-point processor type. This field is set to 011
(3H) for the CY7C602A, and is read-only.
FTT FSR(16:14). Floating-point Trap lYPe: This field identifies
the floating-point trap type of the current FP exception. This
field can be read only.
QNEFSR(13). Queue Not Empty: This bit signals whether the
FP queue is empty. (0= empty, 1 = not empty)
FCC FSR(11:10). Floating-point Condition Codes: These two
bits report the FP condition codes (see Table 1 below).
AEXCFSR(9:5). Accumulated EXCeptions: This field reports
the accumulated FP exceptions. All exception cases, masked or
unmasked, are ORed with the contents of the AEXC and accumulated as status. All accumulated fields have the same definition as the corresponding field for CEXC (see below). This field
can be read and written, and must be cleared by software (see
Table 1).
CEXC FSR(4:0). Current EXCeptions: This field reports the
current FP exceptions. This field is automatically cleared upon
the execution of the next floating-point instruction. CEXC status is not lost upon assertion of a floating-point exception, since
instructions following a valid exception are not executed by the
CY7C602A. The following defines the five CEXC bits:
nYc = 1 indicates invalid operation exception. This is defined
as an operation using an improper operand value. An example
of this is 0/0, 00, or -00.
olc = 1 indicates overflow exception. The rounded result would
be larger in magnitUde than the largest normalized number in
the specified format.
ule = 1 indicates underflow exception. The rounded result is inexact, and would be smaller in magnitude than the smallest normalized number in the indicated format.
dze = lindicates division-by-zero, XlO, where X is subnormal or
normalized. Note that % does not set the dzc bit.
nxe = 1indicates inexact exception. The rounded result differs
from the infinitely precise correct result.
R FSR21, 20, and 12. Reserved - always set to O.
8-16
CY7C602A
RD
RP
TEM
3130 2928 27
I I I
I IONEI I
NS
R
version
FIT
23,22 2120 19
1716 14
13
R
12
I
FCC
11 109
I
AEXC
I
CEXC
5'.4
0
TEM
nvml
ofm
I ufin I dzm I nxm I
Figure 3. Floating-Point Status Register
18ble 1. Floating-Point Status Register Summary
Field
RD
RP
TEM
NS
Values
o- Round to nearest (tie-even)
Description
FSRbits
Loadableby
LDFSR
31:30
RoundingDirection
yes
1- Round to 0
2 - Round to +00
3 - Round to - 00
o-Extended precision
1 - Single precision
2 - Double precision
3 - Reserved
29:28
Extended Rounding Precision
yes
o-Disable trap
27:23
nap Enable Mask
yes
1 - Enable trap
NVM
OFM
UFM
DZM
NXM
O-Disable
I-Enable
27
26
25
24
23
22
invalid operation trap mask
overflow trap mask
underflow trap mask
divide by zero trap mask
inexact trap mask
oen
a:
Non-standardFloating-point
yes
0-7
19:17
FPU version number
no
FIT
O-None
1 - IEEE Exception
2 - Unfinished FPop
3 - Unimplemented FPop
4 - Sequence Error
5 - 7 Reserved
16:14
Floating-point trap type
no
QNE
o-queue empty
FCC
0-=
1- <
2->
3 - Unordered
version
AEXC
NVA
OFA
UFA
DXA
NXA
CEXC
NVC
OFC
UFC
DZC
NXC
r
Always set to 0
13
11:10
9:5
9
8
7
6
5
4:0
4
3
2
1
0
21,20,12
8-17
•
Queue Not Empty
no
F1oating-pointCondition Codes
yes
Accrued Exception Bits
accrued invalid exception
accrued overflow exception
accrued underflow exception
accrued divide by zero exception
accrued inexact exception
yes
Current Exception Bits
current invalid exception
current overflow exception
current underflow exception
current divide by zero exception
current inexact exception
yes
reserved bits
no
CY7C602A
CY7C602A Pin Definitions
Integer Unit Interface Signals:
FP active-low output Floating-point Present: This signal indicates to the CY7C601A that a FPU is present in the system. In the
absence of a FPU, this signal is pulled up to VCC by a resistor.
This is a static signal; it always asserts a low o~ut. The
CY7C601Agenerates a floating-point disable trap ifFP is ,not asserted during the execution of a floating-point instruction.
FCC(l:O) output.
Floating-point Condition Codes: The
FCC(1:O)bits indicate the current condition code of the FPU, and
are valid only if FCCV is asserted. FBfcc instructions use the value of these bits during the execute cycle if they are valid. If the
FCC bits are not valid, then FCCV is released, which halts the
CY7C601A until the FCC bits become valid.
FCC1
FCCD
Condition
0
0
equal
0
1
Op1 < Op2
1
0
Op1 > Op2
1
1
Unordered
1llble 2. FCC(1:0) Condition Codes
FCCV output. Floating-point Condition Codes Valid: The
CY7C602A asserts the FCCV signal when the FCC represent a
valid condition. The FCCV signal is deasserted when a pending
floating-point compare instruction exists in the floating-point
queue. FCCV is reasserted when the compare instruction is completed and FCC bits are valid.
FHOLD output. Floating-point HOW: The FHOLD signal is
asserted by the CY7C602A if it cannot continue execution due to
aresource or operand dependency. The CY7C602Achecksfor all
dependencies in the decode stage, and if necessary, asserts
PHOW in the next cycle. The PHOLD signal is used by the
CY7C601A to freeze its pipeline in the same cycle. The
CY7C602A must eventually deassert FHOW to release the
CY7C601Apipeline.
FEXC output. Floating-point EXCeption: The FEXCis asserted
if a floating-point exception has occurred. It remains asserted until the CY7C601A acknowledges that it has taken a trap by asserting FXACK. Floating-point exceptions are taken only during the
executionofafloating-pointinstruction. TheCY7C602Areleases
FEXCwhen it receives FXACK.
FXACK input. Floating-point eXception ACKnowledge: The
FXACK signal is asserted by the CY7C601A to acknowledge to
the CY7C602A that the current FP trap is taken.
INST input. INS'Ihlction fetch: The INST signal is asserted by
the CY7C601A whenever a new instruction is being fetched. It is
usedby the CY7C602Ato latch the instruction ontheD(31:0) bus
into the FPU instruction buffer. The CY7C602A has two instruction buffers (D1 and D2) to save the last two fetched instructions.
When INST is asserted, the new instruction enters the D1 buffer
and the old instruction in Dl enters the D2 buffer.
FINSl input. Floating-pointINStruction in buffer 1: The FINS1
signal is asserted by the CY7C601A during the decode stage of a
FPU instruction if the instruction is stored in the D1 buffer of the
CY7C602A. The CY7C602A uses this signal to launch the instruction in the D1 buffer into its execute stage instruction register.
FINS2input. Floating-point INStruction in buffer 2: The FINS2
signal is asserted by the CY7C601A during the decode stage of a
FPU instruction if the instruction is stored in the D2 buffer of the
CY7C602A. The CY7C602A uses this signal to launch the instruction in the D2 buffer into its execute stage instruction register.
FUJSH input. Floating-point instruction flUSH: The FLUSH
signalis asserted by the CY7C601A to signal to the CY7C602A to
flush the instructions in its instruction registers. This may happen
when a trap is taken by the CY7C601A. The CY7C601A will restart the flushed instructions after returning from the trap.
FLUSH has no effect on instructions in the floating-point queue.
In addition to freezing the FPU pipeline, the CY7C602A uses
FLUSH to shut off D bus drivers during store. Th ensure correct
operation of the CY7C602A, FLUSH must not change state more
than once during a clock cycle.
Coprocessor Interface Signals:
CHOLD input. Coprocessor HOLD: The CHOLD signal is asserted by the coprocessor if it cannot continue execution. The coprocessor must check all dependencies in the decode stage ofthe
instruction and assert the CHOLD signal, if necessary, in the next
cycle. The coprocessor must eventually deassert this signal to unfreeze the CY7C601A and CY7C602A pipelines. The CHOLD
signal is latched with a transparent latch in the CY7C602A before
it is used.
CCCV input. Coprocessor Condition Codes Valid: The coprocessor asserts the CCCV signal when the CCC(1:0) represent a
valid condition. The CCCV signal is deasserted when a pending
floating-point compare instruction exists in the coprocessor
queue. CCCV is reasserted when the compare instruction is completed and CCC bits are valid. The CY7C602A will enter a wait
state if CCCV is deasserted. The CCCV signal is latched with a
transparentiatch in the CY7C602A before it is used.
System/Memory Interface Signals:
A(31:0) input. Address bus (31:0): The address bus for the
CY7C602Ais an input-only bus. The CY7C601A supplies all addresses for instruction and data fetches for the CY7C602A. The
CY7C602Acapturesaddressesoffioating-pointinstructionsfrom
theA(31:0) bus into the DDAregister. When INST is asserted by
the CY7C601A, the contents of the DDA is transferred to the
DA1 register.
D(31:0) input/output. Data bus (31:0): The D(31:0) bus is driven
by the FPU only during the execution of floating-point store instructions. The store data is sent out unlatched and must be
latched externally before it is used. Once latched, store data is valid during the second data cycle of a store single access and on the
second and third data cycle of a store double access. The data
alignmentfor load and store instructions is done inside the FPU.
A double word is aligned on an eight-byte boundary. A single
word is aligned on a four-byte boundary.
DOE input Data Output Enable: The DOE signal is connected
directly to the data output drivers and must be asserted during
normal operation. deassertion of this signal tri-states all output
drivers on the data bus. This signal should be deasserted only
when the bus is granted to another bus master, i.e, when either
BHOLD, MHOLDA, or MHOWB is asserted.
MHOLDA, MHOLDB input.
Memory HOLD: Asserting
MHOLDA or MHOLDB freezes the CY7C602A pipeline. Either MHOLDA or MHOWB is used to freeze the FPU (and the
8-18
=a:----...
~ ' ' CYPRESS
~,
CY7C602A
SEMICONDUCTOR
IU)pipelines during a cache miss (for systems with cache) orwhen
slow memory is accessed.
BHOLDinput. BusHOLD: This signal is asserted by the system's
I/O controller when an external bus master requests the data bus.
Assertionof this signal will freeze the FPU pipeline. Externallogic should guarantee that after deassertion ofBHOLD, the state of
all inputs to the chip is the same as before BHOLDwas asserted.
MDS input. Memory Data Strobe: The MDS signal is used to
load data into the FPU when the internal FPU pipeline is frozen
by assertion ofMHOLDA, MHOLDB, or BHOLD.
FNULLoulput. Fpu NULlify cycle: This signal signals to the
memory system when the CY7C602A is holding the instruction
pipelineofthe system. This hold would occur when FHOLD or
FCCV is asserted. This signal is used by the memory system in the
same fashion as the integer unit's INULL signal. The system
needs this signal because the IU's INULL does not take into account holds requested by the FPU.
RESET input. RESET: Asserting the RESET signal resets the
pipeline and sets the writable fields of the floating-point status
register (FSR) to zero. The RESET signal must remain asserted
for a minimum of eight cycles. After a reset, the IU will start fetching from address O.
eLK input. CLOCK: The CLK signal is used for clocking the
FPU's pipeline registers. It is high during the first half of the processor cycle and low during the second half. The rising edge of
CLK defines the beginning of each pipeline stage in the FPU.
Document#: 38-R-10004-A
•
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CY7C604A
CYPRESS
SEMICONDUCTOR
Features
Cache Controller and
Memory Management Unit
Description
• Fully conforms to the SPARC@ Reference Memory Management Unit
(MMU) Architecture
• Hardware table walk
• Large address space support
- 32-bit virtual address
- 36-bit pbysical address
• Support for virtual memory
• Supports context switching
- 4096 contexts for TLB entries
- 4096 contexts for cache tag
• 2048 cache tag entries
• 32-byte cache line size
• Address and data latches for virtual
bus
• On-chip Translation Lookaside Buffer
• Lockable cache
• Write-through and copy-back cache
polices
• 32-byte read line buffer
• 32-byte copy-back write line buffer
• 32-byte write-through buffer
• Conforms to SPARC Reference Mbus
Level 1 speci6cation
• Aliasing detection
• Byte write generation
• 0.8-micron CMOS technology
• 2.2 watts typical power dissipation at
33 MHz
(TLB)
- 64 fully associative entries
-
Multi-level TLB flush
TLB probe support
Lockable entries
Random TLB replacement
Supports multi-level address mapping (4-Kbyte, 2S6-Kbyte,
16-Mbyte, and 4-Gbyte).
• Page-level memory access protection
- Read/Write/Execute
- User/supervisor modes
Logic Block Diagram
I
VIRTLI'\l BUS
CONTROL
TLBARRAY
EJE]
I
I
ARRAY
ARRAY
TLB CONTROL
TABLE
WALK
CONTROL
I
Mbus CONTROL
The CY7C604A consists of a cache controller with on-chip cache tag and a
memory management unit. It is a highspeed CMOS implementation of the
SPARC reference memory management
architecture, combined with a cache tag
and cache memory controller. The
CY7C604A directly connects to the
CY7C601A integer unit microprocessor
and CY7C157A cache storage unit without any external circuitry.
When combined with two CY7C157A
16-Kbyte by 16 cache storage units, the
CY7C604A forms a complete, no waitstate, 64-Kbyte, direct-mapped virtual
cache. The cache size can be scaled up to
256-Kbyte and the number ofTLB entries
increased to 256 with the use of additional
CY7C604Asand CY7C157As.
Pin Configuration
CONTROL
REGISTER!
MAO(63:0)
A(1:0)
MAS
A(15:2)
~
[]!]
ICTPR I
I CXR I
I TRCRI
CACHE
TAG
ARRAY
CACHE
I DPTPI
=
MERR
0(31:0)
MRTY
ASI(5:0)
MROY
SIZE(1:0)
MRST
RO
CY7C604A
WE
CACHE CONTROLLER
AND
MEMORYMANAGEMENT
UNIT
LDSTO
---p:n;-
~
~
~
A(31:16)
SNULL
CACHE CONTROL
INULL
AND
AUASDETECTION
FNULL
(CMU)
ERROR
FAULT REGISTERS
MBR
MBG
MBB
CSTA
CROE
CBWE(3:0)
I SFSR II AFSR I
IRST
CLK
I SFAR II AFAR I
MHOLO
POR
I WRITEBUFFER(S) I
II READ BUFFER I
MOS
cw:
MEXC
CMER
'i'OE
10E
C602-1
C602 2
Selection Guide
Commercial
SPARC is a registered trademark of SPARCInternational, Inc.
8-20
7C604A-40
7C604A-33
650
600
7C604A-2S
600
~
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~:"'CYPRESS
_
CY7C604A
. , SEMICONDUCTOR
I
Functional Description
The CY7C604A(CMU) is a combined memory management unit
(MMU)andcachecontrollerwith on-chip cache tag memory. The
CY7C604Ais designed as part of a system solution for high-performancecomputing using the Cypress SPARC chip set. This chip
set consists of the CY7C601A integer unit, the CY7C602A floating-point unit, the CY7C604A CMU, ~nd two CY?C157~ cac?e
storage units. The Cypress SPARC chip set compnses a fIVe ChiP,
high-performanceCPU requiring no additionalgIuelogic. Aspart
of this chip set, the CY7C604A provides support for large adru;e.ssingspaces with virtual to physical address translation. In addition
to an MMU, the CY7C604A provides 2048 cache tag entries ~nd
logic to control a 64-Kbyte virtual cache. The CY7C604A IS a
high-performance, high-ingetration solution to virtual memory
and cache support for the CY7C600 family.
CY7C60tAJ
1
The MMU performs its address translation task by comparing a
virtual address supplied by the CY7C601A (integer unit) to the
address tags in the TLB entries. If the virtual address and the value of the context register match a TLB entry, a TLB "hit" occurs.
When this occurs, the physical address stored in the TLB is used
to translate the virtual address to a physical address. The access
type (read/write of data or instruction) and privilege level (user/
supervisor)are checked during translation. If a TLB hit occurs ~ut
access level protection is violated, the MMU signals an exceptIOn
and the operation ends.
If the virtual address or context does not match any valid TLB
entry, a TLB "miss" occurs. This causes a table walk to be performed by the MMU. The table walk is a search performed by the
MMU through the address translation tables stored in main
memory. The MMU searches through several levels of tables for
the PTE corresponding to the virtual address. Upon finding the
PTE, the MMU translates the address and selects a TLB entry for
replacement, where it then stores the PTE.
The 64-Kbyte virtual cache is organized into 2048 lines of32 bytes
each. The term ''virtual cache" refers to the direct addressing of
the cache by the integer unit (CY7C601A) with the virtual address
bus. Virtual address bits (VA(15 :5» selectthe cache line, and vir-
VA<4:2>
CACHEWORDAD!,,:!E~fj _
:
t
.t ____________ ,
32 BYTES (8 X 32-BIT WORDS) :
CAC::~~~~DDR"~, r J I\ "
2048 LINES
CBWE<3:0>
CROE
CY7C604A
...
'-
The CY7C604A is designed to be used in conjunction with the
CY7C157Acache storage unit. Two 16-Kbytex 16-bit CY7C157s
and one CY7C604A constitute a 64-Kbyte cache. The combination of a CY7C604A and two CY7C157As may be cascaded to
provide up to 256 Kbytes of cache.
The MMU portion of the CY7C604A provides translation from a
32-bit virtual address range (4 gigabytes) to a 36-bit physical address (64 gigabytes), as provided in the SPARC reference MMU
specification. Virtual address translation is further extended with
the use of a context register, which is used to identify up to 4096
contexts or tasks. The cache tag entries and TLB entries contain
contextnumbers to identify tasks or processes. Thisminimizesunnecessary cache tag and TLB entry replacement during task
switching.
TheMMU features a64-entrytranslationlookaside buffer (TLB).
The TLB acts as a cache for address mapping entries used by the
MMU to map a virtual address to a physical address. These mappingentries, referred to as page table entries or PTEs, allow one of
four levels of address mapping. A PTE can be defined as the address mapping for a single 4-Kbyte page, a 256-Kbyte region, a
16-Mbyte region, or a 4-Gbyte region. The TLB entries are lockable, allowing important TLB entries to be excludedfromreplacement. The use of multiple CY7C604As in a system allows the
number of TLB entries to increase from 64 up to a maximum of
256.
DATA BUS
VA<31:0>
----'
,
/
,
,
,
Mbus (pHYSICAL BUS)
Figure 1. Virtual 64-Kbyte Cache
tual address bits (VA(4:2» select the 32-bitword of the cache line,
as illustrated inFigure 1. The CY7C604A provides access control
for the cache by checking the context and virtual address against
the cache tags. If the virtual address, access level, and context
match the cache tag for the cache line addressed, a cache hit occurs and the access is enabled. If the virtual address or context do
not match the cache tag for the cache line, a cache miss occurs and
the cache controller accesses main memory for the required data.
•
o
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The CY7C604A provides cache locking, which prevents the data
stored in the cache from being replaced. The entire cache is
locked by setting the cache lock bit (CL) in the System Control
Register(SCR).
The cache controller supports two modes of caching:
write-throughwithnowrite allocate and copy-back with write allocate. Write-through mode is a simpler style of cache management
that causes write accesses to the cache to be written through to
main memory upon each write access. The advantage of this
method is that the cache always remains coherent with main
memory. Its disadvantage is that each write to the cache is echoed
to main memory, which increases traffic on the system bu~.
Another disadvantage to write-through is that the processor IS
delayed by the time required to arbitrate the system bus and write
the data to main memory. However, in the case of the
CY7C604A, this disadvantage is largely offset by the inclusion of
write buffers. The write buffers can store up to four double-word
accesses, allowing the CY7C601A to continue execution while
data is written to main memory.
Copy-back cache mode causes write accesses to be written to the
cache only. This causes the cache line to become modified. Modified cache lines are automatically written back to main memory
only when the cache line is no longer needed. Copy-back mode
provides substantial system performance improvements over
write-throughdue to decreased traffic on the system bus.
A 32-byte write buffer and a 32-byte read buffer are provided in
the CY7C604A to fully buffer the transfer of a cache line. This
feature allows the CY7C604A to simultaneously read a cache line
from main memory as it is flushing a modified cache line from the
cache. This feature is also used in write-through cache mode for
write accesses to main memory. The write buffer avoids stalling
8-21
a:
&:'~PRFSS
CY7C604A
~, SEMICONDUCTOR
the CY7C601A on writes to main memory by storing the write
data until the physical bus becomes available. The write buffer
writes the data to memory as a background task.
The CY7C604A supports the SPARC Mbus standard bus lnterface. The Mbus is a peer level, high-speed, 64-bit, multiplexed address and data bus which supports a full peer level protocol (i.e.,
multiple bus masters). The Mbus transfers data in either burst or
non-burst mode, depending upon size. Data transactions larger
than eight bytes (one doubleword) are transferred in burst mode,
which consists of an address phase followed by four data phases
(32 bytes total). Non-burst transactions consist of an address
phase followed by one data phase, and are used for data transactions less than eight bytes. Bus mastership is granted and controlled by an external bus arbiter. The bus arbiter sets bus priorities, and grants access to a bus master.
Memory Management Unit
The MMU provides virtual to physical address translation with
the use of an on-chip translation lookaside buffer (TLB). The
translationlookaside buffer is in reality a full Address ltanslation
Cache (ATe) for address translation entries stored from tables in
main memory. These entries, referred to as page table entries or
PTEs, contain the mapping information used by the MMU to
translate the virtual addresses. Addresses presented to the MMU
for translation are compared against the set ofPTEs stored in the
TLB. All entries in the TLB are simultaneously accessed through
the use of advanced content addressable memory (CAM) technology. If a match for the virtual address and context is found in a valid TLB entry and the access protection is not violated, a TLB hit
occursand the address is translated. A virtual address and context
that matches a valid TLB entry but violates the memory access
protections will cause theCY7C604A to generate a memory exception to the CY7C601A. If the TLB entries do not match the
address and context, or the TLB entry is invalid, then a TLB miss
occurs. The MMU responds to the TLB miss by initiating a table
walkto find the correct PTE stored in main memory for thevirtual
address.
The MMU Uses a tree-structured table walk algorithm to fmd
page table entriesnotfound in the TLB. The table walk is a search
through a series of tables in main memory for the PTE correspondingto a virtual address. The table walk uses a series of four
tables. These tables are: the context table, the level 1 table, the
level 2 table, and the level 3 table. The table walk uses the context
pointer register as a base register and the context number as an
offset to point to an entry in the context table. At any address, the
MMU finds either a PTE, which terminates its search, or a page
table pointer (PTP). A PTP is a pointer used in conjunction with
a field in the virtual address to select an entry in the next level of
tables. The table walk continues searching through levels oftables
as long as PTPs are found pointing to the next table. The table
walk terminates when a PTE is found, or anexceptionisgenerated
if a PTE is not found after accessing the level 3 table. An exception is also generated if the table walk finds an invalid or reserved
entry in the page tables.
Upon finding the PTE, the CY7C604A stores it in an available
TLB entry and translates the corresponding virtual address. The
table walk processing is implemented in the CY7C604A hardware. It is self-initiated, and is transparent to the user.
Cache Controller
The cache controller provides cache memory access control for a
64-Kbyte direct mapped virtual cache. The cache controller is designed to use two CY7C157A cache storage units for the cache
memory. These cache RAMs are 16-Kbyte x 16 SRAMs with
on-chip IIddress and data latches and tinting control. The
CY7C601Acache can be expanded to a maximum of 256 Kbytes
by adding additional groups of one CY7C604A and two
CY7C157As. Using multiple CY7C604As to expand the cache is
referredto as a multichip configuration for the CY7C604A, and is
described. in the CY7C604A Multichip Configuration section in
the SPARC RISC User's Manual.
The cache is organized as 2048 cache lines of 32 bytes each. The
CY7C604Ahas 2048 cache tag entries on-chip, one tag entry for
each cache line. Addressing for the virtual cache is provided directly from the virtual address bus. The virtual address field
(VA(15:5»selects one of the 2048 lines of the cache. Thisaddress
field also selects one of the corresponding cache tag entries in the
CY7C604A. A cache hit occurs when the upper sixteen bits of the
virtual address and the context register match with the virtual address and context stored in the selected cache tag entry. The lowest five bits of the virtual address bus (VA(4:0» select one of the
32 bytes in the cache line. Cache data replacement is always performed by replacing cache lines.
The cache is designed to provide data with every read access asserted on the virtual bus, regardless of the cache controller. The
CY7C604Acontrols cache read access by holding the CY7C601A
if a cache hit is not detected by the cache controller. The cache
controller then reads the new cache line from main memory, and
suppliesthe correct data to the CY7C601A. After the correct data
is latched into the CY7C601A by strobing the MDS signal, the
CY7C601Ais released and execution proceeds normally.
Writes to the cache are controlled by the CY7C604A, which decodes the lowest two bits of the virtual address, the SIZE(1 :0) signal, and checks for a cache hit to enable the correct cache byte
write enable signals. If a cache write hit occurs, the CY7C604A
decodes the correct CBWE signals for the write access, and outputs these to theCY7C157 cache RAM write enables. Ifthe cache
mode is set to write-through (see Cache Modes), the write data is
also written to main memory. If a write cache miss occurs for
write-through cache mode, the data is written to main memory
and the cache is not updated. Ifthe write cache miss occurs during
copy-back cache mode (see Cache Modes), the cache line is
fetched from main memory. If the cache line stored in the cache
when the write cache miss occurred has been modified, the old
cache line is written to main memory before the cache line is replacedbythenewdata. After the cache line has been replaced, the
write access is enabled by the CY7C604A.
Cache Tag
The CY7C604A features 2048 direct-mapped cache tag entries.
The on-chip cache tag and the TLB are accessed simultaneously.
Each entry in the cache consists of 16 bits of virtual address
(VA(31:16»,a 12-bit context number (CXN(11:0», one valid bit
(V) and one modified bit (M). The valid bit (V) is set or cleared to
indicate the validity of the cache tag entry. The modified bit (M)
of a cache tag entry is set during copy-back mode after a write access to the cache line. This indicates that the cache line has been
modified. The modified bit has no meaning for write-through
cache mode. The cache line select field (VA(15:5» is used to select a cache line entry and its corresponding cache tag entry. The
address field (VA(31:16» and context register are compared
against the virtual address and the context fields of the selected
cache tag entry. If a match occurs, then a cache hit is generated.
If a !!latch is not found, then a cache miss is generated. Th complete an access successfully, both the cache tag and the TLB must
be hit with appropriate access level permission. Upon power-on
reset (POR), all cache tag entries are invalidated (all V bits are
cleared).
8-22
« :;~PRFS')
CY7C604A
~, SEMICOIDUCTOR
A supervisor bit (S) is included in the cache tag entry. For cache
tag entries which are accessible by the supervisor only (access
level field 6 or 7), the S bit is set. During a cache tag look up, if
the access is supervisor mode and the the S bit is set, the context
number comparison is ignored and the context match is forced.
This operation is similar to a TLB look up with access level field
set to either 6 or 7.
Cache Modes
The virtual cache can be programmed for either write-through
with no write allocate or copy-back with write allocate. The two
cache modes differ in how they treat cache write accesses.
Write-through cache mode causes write hits to the cache to be
written to both cache and main memory. Write-through write
cache misses will only update main memory and invalidate the
cache tag, but will not modify the cache.
A write access in copy-back mode will modify the cache only.
The writing of the modified cache line to main memory is deferred until the cache line is no longer required. Copy-back
cache mode has the advantage of reducing traffic on the system
bus. Bus traffic is reduced since all updates to memory are deferred and are performed subsequently only as absolutely required. In addition, all such data transfers are made utilizing the
more efficient burst mode.
CY7C604A Registers
All values in all control registers are read/write (with the exception of the implementation and version fields of the SCR). Control registers are accessible by use of the alternate space load or
store instructions with ASI = 4.
Programmer's Note: 1b ensure software compatibility with future versions of the CY7C604A, reserved fields in a register
should be written as zeros and masked out when read.
System Control Register (SCR)
The system control register, as shown in Figure 2, defines the operation modes for the cache controller and MMU. The following describes the functions of the bit fields in the SCR.
CEo Cache-enable bit (SCR(8» indicates whether the virtual
cache is enabled or not. This bit is set to 1 to enable the cache
controller.
CL. Cache~lock bit (SCR(9» indicates whether the entire cache
is locked or not. This bit is set to 1 to lock the cache.
CM. Cache-mode bit (SCR(10» indicates whether the cache is
operating under write-through no write allocate policy or
copy-back write allocate policy. This bit is set to 1 to enable
copy-back cache mode. Setting this bit to 0 will enable
write-through cache mode.
C. Cacheable bit (SCR(13» indicates whether the access is
cacheable or not when the MMU is disabled. This bit is set to 1
if accesses on the physical bus (with the MMU disabled) are to
be considered cacheable.
BM. Boot-mode bit (SCR(14» indicates the system is in boot
mode. This bit is set to 1 to indicate boot mode and is automatically set upon power-on reset.
MCA(1:0). Multichip address.field (SCR(23:22» provides the
address field in multichip configuration. For more information,
refer to the CY7C604A Multichip Configuration section in the
SPARC RISC User's Manual.
MCM(1:0).
Multichip mask.field (SCR(21:20» provides a
masking facility to mask certain multichip address (MCA) bits in
order to provide a facility to build systems with a differentnumber of CY7C604As (from 1 to 4).
MY. Multichip configuration valid bit (SCR(19» indicates that
the MCA and MCM fields are valid.
NF. No-fault bit (SCR(1» prevents supervisor data accesses
from signaling data faults to the CY7C601A. When the NF bit is
set, exception-generating logic (in both the TLB and the table
doeC)ot indicate supervisor data faults to the CY7C601A
(via EX ,but status and address information is recorded in
the SFSR and SFAR registers as in normal data access operations. When the NF bit is not set, the CY7C604A reports the
supervisor data exceptions.
.
walkh
ME. MMU-enable bit (SCR(O» indicates whether the MMU is
enabled or not. This bit is set to 1 to enable the MMU.
The implementation number (SCR(31:28» and the version
number (SCR(27:24» fields are hardwired; they are read only
fields and writes to those fields are ignored.
Implementation number field: 0001
Version number field: 0001
On power-on reset, all writeable control bits except the BM bit
are cleared. This sets the CY7C604A into the following state:
cache disabled (CE
0), cache unlocked (CL
0),
write-through mode (CM = 0), non-cacheable (C = 0),
boot-mode enabled (BM = 1), multichip disabled (MV = 0), no
fault disabled (NF = 0), and MMU disabled (ME = 0).
=
=
RSV
7
IMPL = Specific Implementation of the MMU
VER = Version of Specific Implementation (typically mask revision)
MCA (0:1) = Multichip Address
MCM (0:1) = Multichip Mask
MV = Mullichip Valid
BM = Boot Mode
CM = Cache Mode
CL = Cache Lock
CE = Cache Enable
NF= No Fault
ME = MMU Enable
RSV = Reserved
C = Cacheable (when MMU disabled)
Figure 2. System Control Register (SCR)
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CY7C604A
Context Thble Pointer Register (CTPR)
RP
The context table ppinter points to the context table in physical
memory. The table is indexed by the contents of the context register. The context table pointer appears on bits 35 through 14 of the
Mbus (MAD(3S:14» during the fIrst fetch ofTLB miss processing. Once the root pointer is cached in the PTPC (page table
pointer cache), no fetching of the root pointeris required until the
context is changed (see Figure 3).
CTP
31
0
CTP = Context Table Pointer
RSV = Reserved
RSV = Reserved
V=Valid
Figure 6. Root Pointer Register
Instruction access PTP (IPTP)
The IPTP is the instruction access level 2 table page table pointer
(PTP) and is part ofthe page table pointer cache. Upon power-on
reset, the V bit is cleared.
Figure 3. Context Thble Pointer Register
Context Register (CXR)
The context register defInes a virtual address space associated
with the current process. The CXR is a twelve bit register that supports 4096 contexts. This register is used to defIne the current
context for the CY7C604A. Nearly all CY7C604Aoperations are
dependent upon matching the value of this register to a cache tag
entry or 1LB entry.
RSV
31
IPTP
RSV
IPTP = Instruction Access PTP
RSV = Reserved
V= Valid
Figure 7. Instruction Access PTP Register
o
Data access PTP (DPTP)
The DPTP is the data access level 2 table page table pointer (PTP)
and is a register in the page table pointer cache. Upon power-on reset, the V bit is cleared.
CXN = Context Number
RSV = Reserved
Figure 4. Context Register
DPTP
Reset Register (RR)
RSV
The RR register contains information regarding whether watch
dogreset (WDR), software internal reset (SIR), or software externalreset (SER) occurred. This is a read/write register, and setting
the software internal reset bit (SIR) or the software external reset
(SER) causes the corresponding reset. Upon power-on reset, the
WDR, SIR, and SER bits in the RR will be cleared. Readingthe
RR will also clear these bits.
2
DPTP = Data Access PTP
RSV = Reserved
V=Valid
Figure 8. Data Access PTP Register
IndexThg Register (lTR)
The ITR contains the tag (index1 and index2) fIelds of the IPTP
and DPTP entries.
RSV
3
o
4 3
31
RSV = Reserved
WDR = Watchdog Reset
SIR = Software Internal Reset
SER = Software External Reset
o
4 3
31
CXN
12 11
31
o
RP = Root Pointer
On power-on reset, the V bit is cleared. When the current context
is changed bywriting to the context pointer register (CXR), the V
bit of the RPR is cleared. The Vbit is also cleared when the CTPR
register is written.
RSV
109
RSV
6 5
31
o
I
ITAG
31
18
DTAG
RSV
17
16
15
RSV = Reserved
ITAG = Instruction Access PTP Tag
DTAG = Data Access PTP Tag
Figure 5. Reset Register
Root Pointer Register (RPR)
The RPR is the context-level table page table pointer (PTP) and is
cached in the page table pointer cache.
8-24
Figure 9. Index Thg Register
I
RSV
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o
~
a;___ , ;~PRFSS
SEMICONDUCTOR
CY7C604A
(SFAR) is a valid fault address. The over-write bit (OW) is set in
the case of a double fault where the fault status stored in the SFSR
does not correspond with the fault first trapped on by the
CY7C601A.
TLB Replacement Control Register (TRCR)
The TRCR contains the replacement counter (RC) and initial replacement counter (IRC) fields as shown in Figure 10_ These
fields are used in order to support random replacement and to
support locking capabilities of the TLB- On power-on reset, both
the RC and IRC fields are initialized to zero.
RSV
RC
31
Synchronoos Fault Address Register (SFAR)
The synchronous fault address register contains the faulted virtuaJ
address.
IRC
14 13
8
7
6 5
o
SFA
SFA = Synchronous Fault Address
Figure 12. Synchronous Fault Address Registers
Figure 10. TLB Replacement Control Register
Asynchrouous Fault Status Register (AFSR)
Synchronous Fault Status Register (SFSR)
The synchronous fault status register, iIIustratedinFigure ll,contains fault-associated information for synchronous faults. Synchronous faults are faults that occur during an integer unit access
of memory. Synchronous faults include almost all possible faults
for the CY7C604A. This type oHault is synchronous to the operations of the CY7C601A. For the CY7C604A, this fault type covers all cases except those caused by delayed writes of data stored in
the write buffers. These faults are asynchronous to the operation
of the CY7C601A, and are named asynchronous faults.
An example of a synchronous fault is a privilege violation fault
caused by attempting an unauthorized memory access. Upon encountering a synchronous fault, the CY7C604A asserts the
!VlEXCsignal, alongwithl\ITIDrn andMJ:)SMiWchronOUSfaults
are the only exception type that assert the
signal.
The CBT bit indicates that a translation error occurred during a
table walk for the flush of a modified cache line of a copy-back
mode cache miss. The SFAR will contain the address of the
missed cache access, not the modified cache line address causing
the translation error. When this type of error occurs, the cache tag
remains valid, and the cache line remains modified.
The uncorrectable error (UE), timeout error (TO), Rd bus error
bits (BE) report error status as encoded in the ME R, MRTY,
and MRDY signals. (Refer to the section on Mbus for further information.) The level bits (L) describe the level in a table walk
process at which the fault occurred (if applicable).
31
14 13
12
11
109
RSV = Reserved
UC = Uncorrectable Error
TO = Time Out Error
BE = Bus Error
CBT = Copy-back Translation Error
o
31
RSV = Reserved
RC = Replacement Counter
IRC = Initial Replacement Counter
Asynchronous faults are those faults caused bya delayed memory
access initiated by the CY7C604A. This type of error can only be
caused by a delayed write to main memory initiated by the write
buffer. Asynchronous faults cause the CMER signal to be asserted, which can be used as an interrupt to the CY7C601A.
The Uc. TO, and BE bits are identicalto those in the SFSR. They
are set by the information encoded into the MERR, MRTY, and
FJRIiY signals of the Mbus. The asynchronous fault address bits
provide the upper four bits of the physical address not captured in
the asynchronous fault address register (AFAR), which is a
thirty-two bit register.
RSV
31
I I I I I
RSV
UC TO BE
13 12
11
109
RSV = Reserved
UC = Uncorrectable Error
TO = Time Out Error
AFA(35:32)
87
I
FF~
RSV
4 3
1
0
BE = Bus Error
AFA = Asynchronous Fault Address
AFO = Asynchronous Fault
Occurred
Figure 13. Asynchronous Fault Status Register
The asynchronous fault occurred bit (AFO) issetwhen an asynchronous fault is encountered. Once the asynchronous fault occurred (AFO) bit is set, no further asynchronous faults are recorded until the AFO bit is cleared, which is accomplished by
reading the asynchronous fault address register (see Figure 13).
On power-on reset, the UC, TO, BE, and AFO bits in the AFSR
will be cleared. Reading the AFSR will also clear these bits.
Asynchronous Fault Address Register (AFAR)
The AFAR contains bits 31- Oof the physical address for a asynchronous faults (bus errors). Asynchronous faults can occur during
delayed write accesses or during background cache line flush operations in copy-back mode (see Figure 14). The address in the
AFAR is concatenated with the four AFA bits in the AFSR to define the entire 36-bit physical address.
L = Level
AT = Access Type
FT = Fault Type
FV = Fault Address Valid
OW = Over Write
AFA
Figure 11. Synchronous Fault Status Register
The access type bits (AT(2:0» describes the access type that
caused the fault. This field specifies user/supervisor access and
whether the access is load or store of data or instruction. The fault
type bits (FT) describe the fault type. The fault address valid bit is
set when the address in the synchronous fault address register
8-25
o
31
AFA = Asynchronous Fault Address
Figure 14. Asynchronous Fault Address Register
•
CY7C604A
~~']
VirtualBusSignals
A(1:0)
A(1S:2)
Virtual Bus Signals (continued)
CSEL
Sigual
CSTA
Name
I/O
D(31:0)
I/O
TOE
A(31:16)
ASIO:51
0(31:0)
SIZE 1:0
MbusSlg!!!!!!l
CY7C604A
POA
RO
MAD(63:O)
WE
MAS
MERR
LDSTO
SNULL
MRlY
INULL
MROV
FNULL
MBR
ERROA
Error (active LOW) signal from the
CY7C601A. When this signal is asserted, it
indicates the CY7C601A has halted due to
entering the error state. The CY7C604A
reads this signal and initiates a watchdog reset.
MBG
MHOLO
MBB
MilS
MRS'f
MEXC
CMER
10E
lAST
CachB
--
J
RAM Sign als
CBwE(3:01.
CROE
FNUlL
Floating point unit NUlLification cycle (ac.
tive ffiGH). When FNULL is active, the current access will be ignored.
INULL
Integer unit NULLification cycle (active
ffiGH). When INUlL is active, the current
access will be ignored.
Figure 15. CY7C604A Pin Configuration
o
Pin Definitions
The functional pinout is shown in Figure 15. Note that all
three-state output signals are driven to their inactive state before
they are released to three-state.
Virtual Bus Signals
o
Signal
Name
I/O
A(31:16)
A(lS:2)
Description
LDSTO
Virtual Address bus. Three-state input/output signals. A(lS:2) are input signals during
normal readlwrite accesses and are latched
into the CY7C604A on the rising edge of the
clock. They are output signals during cache
line loads into the cache RAM and modified
cache-line reads from the cache RAM.
A(l:O)
Virtual Address bus. A(l:O) are input signals
during normal readlwrite accesses and are
latched on the rising edge of clock.
ASI(S:O)
Address Space Identifiers. The ASI bits are
used to:
1. Identify various types of accesses (user/
supervisor, instruction/data)
2. Access CY7C604A registers
3. Initiate MMU flush/probe operation
4. Identify cache flush operations
5. Recognize diagnostic operations
6. Recognize pass physical address space
Integer unit Output Enable (active LOW).
This signal is continually drive~ or low.
This signal is connected to the AOE and
DOE inputs of the CY7C601A. When asserted, the IOE will place the address
(A(31:0», address space identifiers
(ASI(7:0», and data (D(31:0» drivers of the
CY7C601A in a three-state condition.
Integer unit Reset (active LOW) is asserted
to reset integer unit. This signa1 is contioual-
ly driven high or low.
Virtual Address bus. A(31:16) are input sig·
nals during normal readlwrite accesses and
are latched into the CY7C604A on the rising
edge of clock.
I/O
Description
Virtual Data bus. Three·state input/output
signals. D(31:0) are input signals during
CY7C601A normal write accesses, modified
cache-line reads from the cache RAM,
CY7C604A register writes or CY7C604A
diagnostic accesses. They are output signals
during cache line loads into cache RAM,
CY7C604A register reads or CY7C604A
diagnostic accesses.
8-26
Load Store Atomic operation indicator (active ffiGH). Asserted by the CY7C601A
during atomic load store cycles and is
sampled by the CY7C604A on the rising edge
of the clock.
o
Memory Data Strobe (active LOW) is asserted for one clock to strobe data into the
CY7C601A during a cache miss. MHOLD
must be low when MDS is asserted. It is driven off of the falling edge of the clock. This is
a three-state output.
o
Memory Esception (active LOW) is asserted
for one clock whenever a privi1ege or protection violation is detected. MHOLD and
MDS must be low when MEXC is asserted.
This is a three-state output.
o
Memory Hold (active LOW) is asserted by
the CY7C604A whenever it reqnires additional time to complete the current access
such as during cache miss etc. It is driven off
of the falling edge of the clock.
~
7:.
:;:::z
~~NDUcroR
CY7C604A
. ;
Virtual Bus Signals
Signal
Name
I/O
Mbus Signals
(continued)
Signal
Name
Description
RD
Read cycle indicator (active HIGH). Asserted
by the CY7C601A during read cycles. Is
sampled by the CY7C604A on the rising edge
of the clock. This signal is also used to generate
cache output enable (CROE).
SIZE(I:0)
SIZE of access indicator. Specifies the data
width of the CY7C601A access and is
sampled by the CY7C604A at the rising edge
ofthe clock.
SNULL
System NUllification cycle (active LOW).
When SNULL is active, the current access
will be ignored.
WE
Write Enable to indicate write cycle (active
WW). Asserted by the CY7C601A during
write cycles and is sampled by the CY7C604A
on the rising edge of the clock. This signal is
also used to generate cache byte write enables
(CBWE(3:0)).
I/O
Description
CMER
0
CMUError (active LOW). This signal is asserted if any bus error has occurred during
writes to main memory. A system can use
this signal to cause an interrupt. This signal
has the same timing specifications as the
Mhus control signals and remains asserted
until the AFAR is read. This signal is a threestate signal.
MAD
(63:0)
I/O
MAD(63:46) Reserved during address phase
(Driven high).
During the data phase of the transaction the
MAD(63:0) lines contain the 64 bits of data
being transferred.
OH
IH
2-FH
MAS
0
MhusAddressStrobe (activeWW). Asserted by the bus master during the first cycle
of every bus transaction to indicate the address phase of that transaction. This is a
three-state output.
MBB
I/O
Mhus Bus Busy (active LOW). Asserted by
the current Mhus master during an entire
transaction and, if required, during both the
read and write transactions of indivisible accesses. The potential bus master devices sampIe MBB in order to obtain bus mastership as
soon as the current master releases the bus.
This is a tbree-state output.
Mhus Bus Grant (active WW). Asserted by
external arbiter when the Mhus is granted to
a master. This signal is continually driven.
MBG
Mhus Address and Data (three-stated bus).
During the address phase of a transaction
MAD(35:0) contains the physical address
PA(35:0). The remaining signals
MAD(63:36) during the address phase of the
transaction contains the transaction associated information as shown below:
MADQ9:J§)
Description
MAD(45) (MBL) Mhus Boot Mode/LocaJ
indicator. MBL is high during the address
phase of boot mode transactions. The instruction fetch and data accesses to the Mhus
while the MMU is disabled in boot mode are
considered BOOT MODE transactions. The
data trausactions on the Mhus required for
Load/Store Alternate instructions with ASI =
1 are considered WCAL transactions.
Mbus Signals
Signal
Name
I/O
(continued)
MBR
1i:ansacti!l!lll'lle
Mhuswrite
Mhusread
Reserved
0
MERR
Mhus Error (active LOW). Asserted or deasserted by an Mhus slave during every data
phase of a transaction. This signal is to be
three-stated when released.
MRDY
Mhus Ready (active LOW). Asserted or deasserted by an Mhus slave during every data
phase of a transaction. This signal is to he
three-stated when released.
MAD(
VA<4:2>
u
:
CAc::~~5~5:Doo.,:,: l
CY7C605A
:<3:0>
' -......_ _ _...J
t
j_l ____________ -.
cAcHEWDADAD!?'!E2 s
I
32 BYTES (8 X 32-BIT WORDS)
I
\"
2048 LINES
/
~:
~ _6_4:K_b~~ :~c~~ ~~~~~
Mbus (PHYSICAL BUS)
__ _
Figure 1. Virtual 64.Kbyte Cache
The cache controller supports two modes of caching:
write-through withnowrite allocate and copy-backwith write allocate. The difference between the two caching modes is in how
they handle write accesses to the cache. Write-through mode
causes write accesses to the cache to be written through to both
cache and main memory upon each write access. Copy-backcache
mode causes write accesses to be written to the cache only, which
causes the caches lines to become modified with respect to main
memory. Modified cache lines are automatically written back to
main memory only when the cache line is no longer needed.
Write-through has the disadvantage that each write to the cache
increases traffic on the system bus. This disadvantage becomes
of increasing importance as multiple processors contend for
memDry bus bandwidth. Write-through also has the disadvantage that the processor is delayed by the time required to arbitrate the system bus and write the data to main memory. However, in the case of the CY7C60SA, this disadvantage is largely
offset by the inclusion of write buffers. The write buffers can
store up to four double-word accesses, allowing the CY7C601A
to continue execution while data is written to main memory.
Copy-back caching has long been recognized as providing higher
system performance than write-through. Blocks of write accesses
(typically occurring in context switching or data intensive opera-
8-30
CY7C60SA
tions) cause a write-through cache system to stall the processor
even with the inclusion ofwrite buffers. This is a problem inherent
with write-through that is avoided by copy-back caching mode.
However, copy-back caching in multiprocessing systems introduces the issue of data consistency. Since copy-back holds modified data until the processor no longer requires the data, main
memory becomes inconsistent with the contents of the cache.
Cache coherency protocols have been established to deal with
the data consistency problem, but many cache designs have
avoided copy-back caching due to the complexity of implementing the protocol. The CY7C605A solves the problems of supporting cache consistency protocols and provides the multiprocessor designer with the performance of a true copy-back cache
system The CY7C605A supports a cache coherency protocol
modeled after the IEEE Futurebus, which has been acclaimed in
the industry as a superior cache protocol. 1b support this protocol, the CY7C605A utilizes a dual cache tag memory to allow
concurrent bus snooping. This enables the CY7C605A to monitor all bus activity without stalling the processor. The
CY7C605A uses the bus activity information to maintain cache
coherency, which it does automatically as a concurrent task without interfering with the cache operations for the processor.
Therefore, the CY7C605A provides a multiprocessing system
that allows a maximum performance copy-back cache without
the problems of supporting a cache coherency protocol.
A 32-byte write buffer and a 32-byte read buffer are provided in
the CY7C605A to fully buffer the transfer of a cache line. This
feature is used in copy-back cache mode to allow the CY7C605A
to simultaneously read a cache line from main memory as it is
flushing a modified cache line from the cache. This feature is
also used in write-through cache mode for write accesses to main
memory. The write buffer avoids stalling the CY7C601A on
writes to main memory by storing the write data until the physical bus becomes available. The write buffer then writes the data
to memory as a background task.
The CY7C605A supports the SPARC Mbus standard bus interface. The Mbus is a peer level, high-speed, 64-bit, multiplexed
address and data bus that supports a full peer level protocol (i.e.,
multiple bus masters). The Mbus transfers data in transaction
sizes from 1 to 128 bytes. These data transfers are performed in
either burst or non-burst mode, depending upon size. Data
transactions larger than eight bytes (one doubleword) are transferred in burst mode, which consists of an address phase followed by multiple data phases. Non-burst transactions consist of
an address phase followed by one data phase, and are used for
data transactions less than eight bytes. Bus mastership is
granted and controlled by an external bus arbiter. The bus arbiter sets bus priorities, and grants access to a bus master.
Mbus is divided into two levels of implementation: levelland
level 2. Levell, implemented on the CY7C604A, is the uniprocessor version of Mbus. Levell is a subset of level 2, which is
the multiprocessor version of Mbus. The CY7C605A supports
level 2 Mbus. Level 2 Mbus includes the IEEE Futurebus cache
coherency protocol, which has been recognized in the industry as
a superior method of supporting multiproCessing systems.
The level 2 Mbus supports direct data intervention, which allows
a cache system with the up-to-date version of a cache line to directly supply the data to another cache system without having to
first update main memory. Direct data intervention provides a
significant performance improvement over systems which do not
support this feature. In addition, the CY7C605A provides support for memory systems with reflective memory controllers. A
memory system with reflective memory control can recognize a
cache to cache data transaction and automatically update itself
without delaying the system. Secondary cache controllers are
also supported by the CY7C605A, which provide a performance
advantage over systems directly using main memory.
Memory Management Unit
The MMU provides virtual to physical address translation with
the use of an on-chip translation lookaside buffer (TLB). The
translation lookaside buffer is in reality a full address translation
cache (ATC) for address translation entries stored from tables in
main memory. These entries, referred to as page table entries or
PTEs, contain the mapping information used by the MMU to
translate the virtual addresses. Addresses presented to the
MMU for translation are compared against the set of PTEs
stored in the TLB. All entries in the TLB are simultaneously accessed through the use of advanced content addressable memory
(CAM) technology. If a match for the virtual address and context is found in a valid TLB entry and the access protection is not
violated, a TLB hit occurs and the address is translated A virtua address and context that matches a valid TLB entry but violatesthe memory access protections will cause the CY7C605A to
generate a memory exception to the CY7C601A. If the TLB entries do not match the address and context, or the TLB entry is
invalid, then a TLB miss occurs. The MMU responds to the
TLB miss by initiating a table walk to find the correct PTE
stored in main memory for the virtual address.
The MMU uses a tree-structured table walk algorithm to find
page table entries not found in the TLB. The table walk is a
search through a series of tables in main memory for the PTE
corresponding to a virtual address. The table walk uses a series
of four tables. These tables are: the context table, the level 1
table, the level 2 table, and the level 3 table. The table walk uses
the context pointer register as a base register and the context
number as a offset to point to an entry in the context table. At
any address, the MMU finds either a PTE, which terminates its
search, or a page table pointer (pTP). A PTP is a pointer used in
conjunction with a field in the virtual address to select an entry
in the next level of tables. The table walk continues searching
through levels of tables as long as PTPs are found pointing to the
next table. The table walk terminates when a PTE is found, or
an exception is generated if a PTE is not found after accessing
the level 3 table. An exception is also generated if the table walk
finds an invalid or reserved entry in the page tables.
Upon rmding the PTE, the CY7C605A stores it in an available
TLB entry and'translates the corresponding virtual address. The
table-walk processing is implemented in the CY7C605A hardware. It is self-initiated, and is transparent to the user.
Cache Controller
The cache controller provides cache memory access control for a
64-Kbyte direct-mapped virtual cache. The cache controller performs this task by comparing memory accesses against the address
and status entries in a cache tag memory. The CY7C605A provides two separate cache tag memories for access comparison.
cache memory accesses from the processor are compared against
the processor virtual cache tag (PVTAG) memory. Bus snooping
operations are compared against the Mbus physical cache tag
(MPTAG) memory. The use of two cache tag memories allows the
8-31
•
:: ::z
~-CYPRESS
CY7C605A
"if!!f!!!!!!!!; SEMICONDUCIDR
cache controller to service processor cache accesses concurrently
with bus snooping cache tag accesses. This feature of the
CY7C605Aprovidessignificantperformanceimprovements over
cache systems sharing a single cache tag memory between the processorcache access and the bus snooping operations. Single cache
tag systems typically must stall the processor when a bus snooping
operationis required, causing serious performance degradation.
The cache controller is designed to use two CY7C157A cache
storage units for the cache memory. These cache RAMs are
16-Kbyte x 16 SRAMswith on-chip address and data latches and
timing control. 'RvoCY7C157As andoneCY7C605A comprise
an entire 64-Kbyte cache system with physical bus interface and
read and write buffers.
The cache is organized as 2048 cache lines of 32 bytes each. The
CY7C605A has 2048 cache tag entries in both the PVTAG and
MPTAG, one entry in each cache tag memory per cache line. Addressing for the virtual cache is provided directly from the virtual
address bus. The virtual address field (VA(15:5)) selects one of
the 2048 lines of the cache. This address field also selects the
cache tag entry in the PVTAG dedicated to the selected cache line.
A cache hit occurs when the upper sixteen bits of the virtual address and the context register match with the virtual address and
contextstored in the selected cache tag entry in PVTAG. The lowest five bits ofthe virtual address bus (VA(4:0)) select one of the
32 bytes in the cache line. Cache data replacement is always performed by replacing cache lines.
The cache is designed to provide data with every read access asserted on the virtual bus, regardless of the cache controller. The
CY7C605Acontrols cache read access by halting the CY7C601 if
a cache hit is not detected by the cache controller. The cache controller then reads the new cache line from main memory, and supplies the correct data to the CY7C601A. After the correct data is
latched into the CY7C601A by strobing the MDS signal, the
CY7C601Ais released and execution proceeds normally.
Writes to the cache are controlled by the CY7C605A, which decodes the lowest two bits of the virtual address, the SIZE(1:0) signal, and checks for a cache hit to enable the correct cache byte
write enable signals. If a cache write hit occurs, the CY7C605A
decodes the correct CBWE signals for the write access, and outputs these to the CY7C157 cache RAM write enables. Ifthe cache
mode is setto write-through (see Cache Modes), the write data is
also written to main memory. If a write cache miss occurs for
write-through cache mode, the data is written to main memory
and the cache is not updated. If the write cache miss occurs during
copy-back cache mode (see Cache Modes), the cache line is
fetched from main memory. If the cache line stored in the cache
when the write cache miss occurred has been modified, the old
cache line is written to main memory before the cache line is replacedbythe new data. After the cache line has been replaced, the
write access is enabled by the CY7C605A.
CacheThg
The CY7C605A features two separate cache tag arrays: the processorvirtual cache tag memory (PVTAG) and the Mbus physical
cache tag memory (MPTAG). Cache controllers using only one
cache tag array must delay the processor when bus snooping reqnires access to the cache tags. The inclusion of two independent
cache tag memories allows the CY7C605A to support processor
accesses to cache while simultaneously performing bus snooping
ontheMbus.
Cache Modes
The cache can be programmed for either write-through with no
write allocate or copy-back with write allocate. The two cache
modes differ in how they treat cache write accesses.
Write-through cache mode causes write hits to the cache to be
written to both cache and main memory. Write-through write
cache misses will only update main memory and will not modify
the cache.
A write access in copy-back mode will modify the cache only. The
writing of the modified cache line to main memory is deferred until the cache line is no longer required. Copy-backcachemodehas
the advantage of reducing traffic on the system bus. Bus traffic is
reduced since all updates to memory are deferred and are subsequently performed only as absolutely required. In addition, all
such data transfers are made utilizing the more efficient burst
mode. The following describes the two cache modes in detail.
Write-through mode with no Write Allocate
For write-through cache mode, write access cache hits cause both
the cache and main memory to be updated simultaneously. A
write access cache miss causes only main memory to be updated
(no write allocate). Write-through caching mode normally requires a processor to delay during a write miss while the data is
written to main memory. The CY7C605A provides write buffers
to prevent this delay in most cases. The write buffers store the
write access and write the data to main memory as a background
task.
During read access cache hits, the cached data is read out and
supplied to the CY7C601A. In the case of a read access cache
miss, a cache line is fetched from main memory to load into the
cache and the required data is supplied to the CY7C601A.
Copy-back mode with Write Allocate
When the cache is configured for copy-back mode, only the cache
is updated on write access cache hits (i.e., main memory is not updated). The modified bit of the cache tag for the cache line is set
on a copy-back write access (write hit or after a write miss is corrected). During write access cache misses, if the selected cache
line is clean (not modified), a cache line is fetched from main
memory to load into the cache and only the cache is updated. If
the selected cache line is modified, the selected cache line is
flushed out to update main memory. The CY7C605A
simultaneouslyfetches the new cache line from main memory and
stores it into the read buffer as it flushes the modified cache line
from the cache and stores it into its write buffer. After the modified cache line has been flushed, the CY7C605A writes the modified cache line out of its write huffer into main memory while the
new cache line is stored into the cache memory from the read
buffer.
During read access cache hits, the cached data is read out and
supplied to the CY7C601A. During read access cache misses, if
the selected cache line is clean (not modified), a cache line is
fetched from main memory to load into the cache. If the selected
8-32
g :[riPRFSS
......... '
CY7C605A
SEMlCCM:lUCTOR
Shared Modified (SM): The same cache line may exist in more
than one cache module, but this cache module is the OWNER of
the cache line. The next level of memory does not have a valid
copy of this cache line, and this cache module has the responsibility to update the next level of memory and to supply any other
cache that may reference this same memory location.
These five states are described by three state bits (valid (V),
shared (SH), and modified(M» in each MPTAG cache tag entry.
The PVTAG cache tag entries corresponding to the same cache
lines have two state bits, valid (V) and shared (SH).
Under write-through cache mode, only the valid and invalid
states apply to either the MPTAG or PVTAG cache tag entries.
The shared and modified bits in the MPTAG are ignored by the
CY7C605A when in write-through mode.
cache line is modified, the selected cache line is flushed out to the
CY7C605A write buffer, and a new cache line is fetched from
main memory and stored into the read buffer. The new cache line
is then stored in the cache from the read buffer, while the modified
cache line stored in the write buffer is written out to main memory.
Multiprocessing Support
The CY7C605A is specifically designed to support multiprocessing systems. The CY7C605A accomplishes this by providing
features necessary to maintain cache coherency with a second-level memory system (typically main memory or a secondary
cache) and other caching systems on the shared bus.
The CY7C605A supports two modes of caching: write-through
and copy-back. Write-through caching mode modifies main
memory with each write access to the cache. This avoids the issue of lack of coherency between the individual cache systems
and main memory, but greatly increases memory bus traffic.
The effect of this increased bus traffic is a degrading of the performance of a multiprocessor system as the processing nodes
compete for memory bus bandwidth. This problem is greatly reduced when copy-back caching mode is used.
Copy-back mode holds all changes to a cache line until the line is
flushed from the cache. This minimizes bus traffic to only those
transactions necessary to maintain the cache. However, by allowing the cache line to be modified without updating main
memory, a problem arises when other processing nodes require
an up-to-date copy of that memory location. The problem of
modified cache lines is solved by the enforcement of a cache coherency protoco\'
CY7C60SA Registers
All values in all control registers are read/write (with the exception ofthe implementation and version fields of the SCR). Control registers are accessible by use of the alternate space load or
store instructions with ASI = 4.
System Control Register (SCR)
The system control register, as shown inFigure 2, defines the operation modes for the cache controller and MMU. The following
describes the functions of the bit fields in the SCR.
The CY7C605A implements a cache coherency protocol specified by the SPARe reference standard Mbus level-2 interface.
This protocol is modeled after that used by the IEEE Futurebus.
In this protocol, each cache line is described by one of five
states: Invalid (I), Exclusive Clean (EC), Exclusive Modified
(EM), Shared Clean (SC), and Shared Modified (SM). The following describes these five cache states:
Invalid (I): Cache line is not valid.
Exclusive Clean (EC): Only this cache module has a valid copy
of this cache line, other than the next level of memory (main
memory or secondary cache). No other cache module on the
same level of memory has a valid copy of this cache line.
Exclusive Modified (EM): Only this cache module has a valid
copy of this cache line. This cache modnle is the OWNER of the
cache line, and has the responsibility to update the next level of
memory (main memory or secondary cache) and also to supply
data if any other cache references this memory location.
Shared Clean (SC): The same cache line may exist in more than
one cache module. The next level of memory mayor may not
contain a valid copy of this cache line, depending upon whether
this cache line has been modified in any other cache.
IMPL, VER-The implementation number (SCR(31:28» and
the version number (SCR(27:24)} fields are hardwired; they are
read only fields and writes to those fields are ignored.
•
Implementation number field: 0001
Version number field: 1111
MID(3:0)-Module Identification number (SCR(18:15» identifies the processor module during transactions on the Mbus. This
four- bit module identification number is embedded in the Mbus
address phase of all Mbus transactions initiated by the
CY7C605A.
BM-Boot-mode bit (SCR(14» indicates the system is in boot
mode. This bit is set to 1 to indicate boot mode. This bit is automatically set upon power-on reset
0
C-Cacheable bit (SCR(13» indicates whether the access is
cacheable or not when the MMU is disabled. This bit is set to 1
if accesses on the physical bus (with the MMU disabled) are to
be considered cacheable.
MR-Memory Reflection (SCR(ll» indicates whether the main
memory system on the Mbus supports memory reflection. MR
affects the status of the MTAG cache tag bits.
CM-Cache-mode bit (SCR(lO» indicates whether the cache is
operating under write-through no write allocate policy or
copy-back write allocate policy. This bit is set to 1 to enable
copy-back cache mode. Setting this bit to 0 will enable
write-through cache mode.
RSV
RSV
19
IMPL = Specific Implementation of the MMU
VER = Version of SpecHic Implementation (typically mask revision)
MID(3:0) = Module Identifier (3:0)
BM = Boot Mode
C = Cacheable (when MMU disabled)
7
MR = Memory Reflection
CM = Cache Mode
CE = Cache Enable
NF= No Faull
ME = MMU Enable
RSV = Reserved
Figure 2. System Control Register (SCR)
8-33
:
~
a::
.r.~tK;TOR
CY7C60SA
CE-Cache-enable bit (SCR(S» indicates whether the virtual
cache is enabled or not. This bit is set to 1 to enable the cache controller.
NF-No-fault bit (SCR(1» prevents supervisor data accesses
from signaling data faults to the CY7C601A When the NF bit is
set, exception-generating logic (in both the 1LB and the table
walk) does )ot indicate supervisor data faults to the CY7C601A
(viaMEXC ,butstatusandaddressinformationisrecordedinthe
SFSR and SFAR registers as in normal data access operations.
When the NF bit is not set, the CY7C605Areports the supervisor
data exceptions.
ME-MMU-enable bit (SCR(O» indicates whether the MMU is
enabled or not. This bit is set to 1 to enable the MMU.
On power-on reset, allwriteablecontrol bits except the BM bit are
cleared. This sets the CY7C605A into the following state: cache
disabled(CE = 0), write-through mode (CM = 0), non-cacheable
(C = 0), boot-mode enabled (BM = 1), no fault disabled (NF =
0), and MMU disabled (ME = 0).
RSV
31
Root Pointer Register (RPR)
The RPR is the context level table page table pointer (PTP) and is
cached in the page table pointer cache.
RP
RSV
6 5
31
1
0
RP = Root Pointer
RSV = ReseNed
V=Valid
Figure 6. Root Pointer Register
The context table pointer points to the context table in physical
memory. The table is indexed by the contents of the context register. The context table pointer appears on bits 35 through 14 of the
Mbus (MAD(35:14» during the first fetch of1LB miss processing. Once the root pointer is cached in the PTPC (page table
pointer cache), no fetching of the root pointer is required until the
context is changed (see Figure 3).
CTP
RSV
On power-on reset, the V bit is cleared. When the current context
is changed bywriting to the context pointer register (CXR), the V
bit of the RPR is cleared. The Vbitis also cleared when the CTPR
registeris written.
Instruction access PTP (IPTP)
The IPTP is the instruction access level 2 table page table pointer
(PTP) and is part ofthe page table pointer cache. Upon power-on
reset, the V bit is cleared.
o
10 9
IPTP
CTP = Context Table Pointer
RSV = RessNed
The context register defines a virtual address space associated
with the current process. The CXR is a twelve-bit register that
supports4096 contexts. This register is used to define the current
contextforthe CY7C605A Nearly all CY7C605Aoperations are
dependent upon matching the value of this register to a cache tag
entry or TLB entry.
0
Figure 7. Instruction Access PTP Register
Data access PTP (DPTP)
TheDPTP is the data access level 2 table page table pointer(PTP)
and is a register in the page table pointer cache. Upon power-on
reset, the V bit is cleared.
CXN
12 11
1
IPTP = Instruction Access PTP
RSV = ReseNed
V = Valid
Context Register (CXR)
RSV
RSV
4 3
31
Figure 3_ Context Table Pointer Register
31
o
2
Figure S. Reset Register
Context Table Pointer Register (CTPR)
31
3
RSV = ReseNed
WDR = Watchdog Reset
SIR = Software Internal Reset
RSV
DPTP
o
4 3
31
1
0
DPTP = Data Access PTP
CXN = Context Number
RSV = ReseNed
RSV = ReseNed
V = Valid
Figure 4_ Context Register
Figure 8. Data Access PTP Register
Reset Register (RR)
The RR register contains information regarding whether watch
dogreset (WDR) or Software Internal Reset (SIR) occurred. This
is a read/write register, and setting the software internal reset bit
(SIR)orthe software external reset (SER) causes the corresponding reset. Upon power-on reset, the WDR, SIR, and SER bits in
the RR will be cleared. Reading the RR will also clear these bits.
Index Tag Register (ITR)
The ITR contains the tag (index1 and index2) fields of the IPTP
and DPTP entries.
ITAG
31
DTAG
18 17 16 15
RSV = ReseNed
ITAG = Instruction Access PTP Tag
DTAG = Data Access PTP Tag
Figure 9. Index Tag Register
8-34
I
RSV
2
o
CY7C605A
TLB Replacement Control Register (TRCR)
SFA
The TRCRcontains the replacement counter (RC) and Initial Replacement Counter (IRC) fields as shown in Figure 10. These
fields are used in order to support random replacement and to
support locking capabilities of the TLB. On power-on reset, both
the RC and IRC fields are initialized to zero.
RSV
I I
RC
31
RSV
14 13
8
7
0
IRC = In~ial Replacement Counter
Figure 10. TLB Replacement Control Register
Synchronous Fault Status Register (SFSR)
Thesynchronousfault status register, illustrated inFigure 11, contains fault-associated information for synchronous faults. Synchronous faults are faults that occur during an integer unit access
of memory. Synchronous faults include almost all possible faults
for the CY7C605A. This type offault is synchronous to the operations of the CY7C601A. For the CY7C605A, this fault type covers all cases except those caused by delayed writes of data stored in
the write buffers. These faults are asynchronous to the operation
of the CY7C601A, and are named asynchronous faults.
An example of a synchronous fault is a privilege violation fault
caused by attempting an unauthorized memory access. Upon encountering a synchronous fault, the CY7C605A asserts the
MEXCsignal, alongwithMHOLD andMDS. Synchronous faults
are the only exception type that assert the MEXC signal.
The uncorrectable error (UE), timeout error (TO), and bus error
bits ~port error status as encoded in the MERR, MRTY,
and MRDY signals. (Refer to the section on Mbus for further information.) The level bits (L) describe the level in a table walk
process at which the fault occurred (if applicable).
31
luclrolBEI
13
12
11
109
RSV = Reserved
UC = Uncorrectable Error
TO = Time Out Error
BE = Bus Error
I
AT
L
87
54
FT
Figure 12. Synchronous Fault Address Register
Asynchronousfaults are those faults caused by a delayed memory
access initiated by the CY7C605A. This type of error can only be
caused by a delayed write to main memory initiated by the write
buffer. Asynchronous faults cause the CMER signal to be asserted, which can be used as an interrupt to the CY7C601A.
The UC, TO, and BE bits are identical to those in the SFSR. They
are set by the information encoded into the MERR, MRTY, and
MRDY signals of the Mbus. The asynchronous fault address bits
provide the upper four bits of the physical address not captured in
the asynchronous fault address register (AFAR), which is a
thirty-two bit register.
RSV
Iuc I I I I
TO BE
RSV
AFA(35:32)
I
RSV
FH~
87
4 3
0
31
13 12 11 109
BE = Bus Error
RSV = Reserved
UC = Un correctable Error
AFA = Asynchronous Fault Address
TO = Time Out Error
AFO = Asynchronous Fault Occurred
Fignre 13. Asynchronous Fault Status Register
The Asynchronous Fault Occurred bit (AFO) is set when an
asynchronousfault is encountered. Once the Asynchronous Fault
Occurred (AFO) bit is set, no further asynchronous faults are recorded until the AFO bit is cleared, which is accomplished by
reading the asynchronous fault address register (see Figure 13).
On power-on reset, the UC, TO, BE, and AFO bits in the AFSR
will be cleared. Reading the AFSR will also clear these bits.
Asynchronous Fault Address Register (AFAR)
The AFAR contains bits 31- 0 of the physical address for asynchronous faults (bus errors). Asynchronous faults can occur during
delayedwriteaccessesorduringbackgroundcacheJineflushoperations in copy-back mode (see Figure 14). The address in the
AFAR is concatenated with the four AFA bits in the AFSR to define the entire 36-bit physical address.
IFAV lowi
2
SFA = Synchronous FauHAddress
Asynchronous Fault Status Register (AFSR)
IRC
6 5
RSV = Reserved
RC = Replacement Counter
RSV
o
31
0
L = Level
AT = Access Type
FT = FauH Type
FV = Fault Address Valid
OW Over Write
AFA
=
o
31
Figure 11. Synchronous Fault Status Register
The access type bits (AT(2:0» describes the access type that
caused the fault. This field specifies user/supervisor access and
whetherthe access is load or store of data or instruction. The fault
address valid hit is set when the address in the synchronous fault
addressregister (SFAR) is a valid fault address. The over-write bit
(OW) is set in the case of a double fault where the fault status
stored in the SFSR does not correspond with the fault first trapped
on by the CY7C601A.
Synchronous Fault Address Register (SFAR)
Thesynchronous fault address register contains the faulted virtual
address.
8-35
AFA = Asynchronous Fault Address
Fignre 14. Asynchronous Fault Address Register
•
o
~
a::
CY7C605A
Virtu al Bus Signals
Cache
RAM Signals
Virtual Bus Signals
CBWE~Q).
CSEL
A(1:0)
Signal
Name
CROE
A(1S:2)
MiS~~gnaISJ
A(31:16)
ASIO:S
I/O
POR
SIZE(0:1)
Mbus Signals
RD
MAD(63:0) -
WE
CY7C605A
LDSTO
MAS
SN\JiI
MRTY
INULL
D(31:0)
FNULL
I/O
ERROR
MHOLD
MBG
MDS
MEXC
IDE
IRST
MIH
MSH
VINT
--
Error (active WW) signal from the
CY7C6010 When this signal is asserted, it
indicates the CY7C601A has halted due to
entering the error state. The CY7C605A
reads this signal and initiates a watch dog reset.
FNULL
Floating point unit NULLification cycle (active HIGH). When FNULL is active, the current access will be ignored.
INULL
Integer unit NULLification cycle (active
IDGH). When INULL is active, the current
access will be ignored.
Pin Definitions
The functional pinout is shown in Figure 15. Note that all
three-state output signals are driven to their inactive state before
they are released to three-state.
Vu1:ual Bus Signals
I/O
A(31:16)
A(lS:2)
A(1:0)
Description
IOE
I/O
Integer unit Output Enable (active WW).
Three-state in~utput. This signal is connected to the AOE and DOE inputs of the
CY7C601A. When asserted, the IOE will
place the address (A(31:0», address space
identifiers (ASI(7:0», and data (D(31:0»
drivers of the CY7C601 in a three-state condition.
IRST
0
Integer unit Reset (active WW) is asserted
to reset integer unit. This signal is continually driven IDGH or LOW.
Virtual Address bus. A(31:16) are input signals during normal read/write accesses and
are latched into the CY7C605A on the rising
edge of clock.
I/O
Virtual Address bus. Three-state input/output signals. A(lS:2) are input signals during
normal readlwrite accesses and are latched
into the CY7C60SA on the rising edge of the
clock. They are output signals during cache
line loads into the cache RAM and modified
cache-line reads from the cache RAM.
LDSTO
VIrtual Address bus. A(l:O) are input signals
during normal readlwrite accesses and are
latched on the rising edge of clock.
8-36
Virtual Data bus. Three-state input/output
signals. D(31:0) are input signals during
CY7C601A normal write accesses, modified
cache-line reads from the cache RAM,
CY7C60SA register writes, or CY7C60SA
diagnostic accesses. They are output signals
during cache line loads into cache RAM,
CY7C60SA register reads, or CY7C60SA
diagnostic accesses.
ERROR
Figure 15. CY7C60SA Pin Configuration
Signal
Name
Description
Address Space Identifiers. The ASI bits are
used to:
1. Identify various types of accesses (user/
supervisor, iustructionldata)
2. Access CY7C60SA registers
3. Initiate MMU flusblprobe operation
4. Identify cache flush operations
S. Recognize diagnostic operations
6. Recognize pass physical address space
ASI(S:O)
TOE
0(31:0)
(continued)
Load Store Atomic operation indicator (active IDGH). Asserted by the CY7C601 during atomic load store cycles and is sampled by
the CY7C60SA on the rising edge of the
clock.
~
~~
'iiI CYPRESS
-:::::::!!!!!!!F SEMICONDUCTOR
CY7C605A
Virtual Bus Signals
Signal
Name
MDS
MEXC
MHOLD
I/O
0
0
0
RD
Description
SH
6-FH
Write Enable to indicate write cycle (active
WW). Asserted by the CY7C601A during
write cycles and is sampled by the CY7C60SA
on the rising edge of the clock. This signal is
also used to generate cache byte write enables
(CBWE(3:0».
I/O
TraDsamoD SiR
Byte (8 bits)
Halfword (16 bits)
Word (32 bits)
Doubleword (64bits)
4
16 Bytes'
S
32 Bytes
6
64 Bytes'
7
128 Bytes'
• Not supported by the CY7C60SA.
MAD(43) (MC) Mhus Cacheable (active
HIGH). Indicates the current Mhus transaction is cacheable.
MAD(4S) (MBL) Mhus Boot ModelLocal
indicator. MBL is HIGH during the address
phase of boot mode transactions. The instruction fetch and data accesses to the Mhus
while the MMU is disabled in boot mode are
considered BOOT MODE transactions. The
data transactions on the Mhus required for
loadlstore alternate instructions with ASI = 1
are considered WCAL transactions.
MAD(63:46) Reserved during address phase
(driven HIGH).
During the data phase of the transaction the
MAD(63:0) lines contain the 64 bits of data
being transferred.
Virtual INThrvention. Three-state input/output (active LOW). Used by the CY7C605A
when in multichip mode to interrupt activity
on the virtual bus for snooping.
MAS
I/O
Mhus Address Strobe (active WW). Asserted by the bus master during the first cycle
of every bus transaction to indicate the address phase of that transaction. This signal is
bidirectional on the CY7C60SA.
MBB
I/O
Mhus Bus Busy (active LOW) asserted by the
current Mhus master during an entire transaction and, if required, during both the read
and write transactions of indivisible accesses.
~otential bus master devices sample
MBB in order to obtain bus mastership as
soon as the current master releases the bus.
This is a three-state output.
Mbus Signals
Signal
Name
I/O
Description
CMER
0
CMUError (active LOW). This open-drain
signal is asserted if any bus error has occurred during writes to main memory. A system can use this signal to cause an interrupt.
This signal has the same timing specifications
as the Mbus control signals.
I/O
Mbus Address and Data (three-stated bus).
During the address phase of a transaction
MAD(3S:0) contains the physical address
PA(3S:0). The remaining signals
MAD(63:36) during the address phase of the
transaction contains the transaction associated information as shown below:
MAD
(63:0)
Mhuswrite
Mhusread
Coherent invalidate
Coherent read
Coherent write and
invalidate
Coherent read and
invalidate
Reserved
0
1
2
3
SIZE of access indicator. Specifies the data
width of the CY7C601A access and is
sampled by the CY7C60SA at the rising edge
of the clock.
WE
1hmliactiOD ])PI:
MAD(
F
CRT
TIMING
I--
=
~
PIXE'"
C817-1
8-50
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUCTOR
Features
• Supports two independent peripheral
channels
• Supports packing and unpacking from
32-bit SBus to 16- or 8-bit data paths
• Byte, hallword, and word transfers
on the SBus are supported as both
master and slave
• Rerun acknowledgments are supported as both master and slave
• Support for access of SBus Fcode
PROM is included
Introduction
The SBus DMA controller provides an
SBusinterface for peripheral controllers of
subsystems such as the Ethernet and disk
I/O. It provides two independentchanneIs,
one with a 16-bit data path and one with an
SBus DMA Controller
8-bit data path. (Refer to the Logic Block
Diagram. The blocks contained within the
dotted lines correspond to the logic described here.) Each channel can operate as
either an SBus master or a slave.
I
1
I
I
I
I
I
I
L
In contrast, the 8-bit channel, called the D
channel, supports the sort of peripheral
controller that has no DMA circuitry itself
but participates in the DMA transfer by
means of a DMA request/DMA acknowledge signal handshake. Hence the D channel has full DMA master functionality, including address and byte counters. Eightto 32-bit packing/unpacking is supported.
The two channels differ in their operation
asSBus masters. The 16-bitchannel, called
theE channel, supports peripheral controllers that generate their own memory addressesfor DMA, keep track of the state of
the transfer in terms of bytes transferred,
and so on. In other words, the Ethernet
---,
I
I
I
I
I
I
32
channel supports peripheral controllers
that have their own memory bus master
functionality. The E channel essentially
acts as a sort of "lever arm" into the SBus
by which the peripheral controllers'
memory access cycles are converted into
the protocol of the SBus. Addresses are extendedfrom 24 to 32 bits and data is packed/unpacked from 16 to 32 bits.
The status of the DMA transfers in progress can be monitored and the progress of
the transfer can be controlled by means of
accessing status and control information
on the DMA controller and the peripheral
controllers, which is available at any time
for SBus access by the CPU.
Logic Block Diagram
SBusD
CY7C618
ECHANNEL
I
DATA
E-AD
I
ADDRESS!
r-
I
I
lsi
I
I
I
!
ETHERNET
CONTROLLER
ETHERN ET
E-A"
81
I
I
I
I
I
INTERNALD
SBus INTERFACE
l-
II
32
DCHANNEL
I
ADDRESS!
COUNT
STATUS/
CONTROL
DATA
c::::::J
c:::::J
I I I I I
D-D"
"8
SCSI
CONTROLLER
I
I
I
I
I•
------- -----
1. SCSI
8
ID/FCODE
PROM
C618-1
8-51
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Complete SPARC@) CPU solution, including cache
- CY7C601 Integer Unit (IV)
- CY7C602 Floating-Point Unit
(FPU)
- CY7C604 Cache Controller and
Memory Management Unit (CMU)
-1\'1'0 CY7C157 Cache Storage Units
(CSU)
• SPARC compliant
- SPARC Instruction Set Architecture (ISA) compliant
- Conforms to SPARC Reference
MMU Architecture
- Conforms to SPARC Levell MBus
Module Specification (Revision
1.2)
• High performance
- 32 MIPS (sustained)
-7MFLOPS [SP],5MFWPS [DP]
(sustained)
- 28 SPECmarks
Logic Block Diagram
CYM6001K
SPARCore@ CPU Module
• Available at 25, 33, and 40 MHz
• Each SPARCore module features:
- SPARC integer and fioating-point
processing
- Zero-wait-state, 64-Kbyte cache
- Demand-paged virtual memory
management
- Surface-mount packaging for more
compact design
- Provides CPU upgrade path at
module level
• Module design
-1\vo power and two ground planes
- Minimum-skew clock distribution
- MBus-standard form factor: 3.30"
(8.34 em) x 5.78" (14.67 em)
• SPARCore MBus connector
- SPARC-standard
- Separate power and ground blades
(100 active pins)
- Designed for high frequency (low
capacitance, low inductance)
Functional Description
The CYM6001K SPARCore Module is a
complete SPARe CPU board. It is packaged as a compact PCB and interfaces to
the remainder of the system via a SPARCstandard MBus connector. The CPU on
the CYM6001K consists of a high-speed
integer unit (CY7C601), floating-point
unit (CY7C602), cache controller and
memory management unit (CY7C604),
and two 16Kx 16 CY7C157 cache storage
units (providing a 64-Kbyte cache for the
CPU). The CYM600lKdelivers sustained
performance of 32 MIPS and 7/5 (single
precision/double precision) MFLOPS at
an operating frequency of 40 MHz. The
CYM6001K achieves an overall SPECmark rating of 28. IC components are surface mounted for a compact footprint. The
CYM6001Kfitswithin thec1earance envelope for MBus modules per the SPARC
MBusSpecification.
r------------------,
CY7C601
IU
CY7C602
FPU
TT
VA<31:0>
I~
CY7C604
CMU
L
___ ~
r
I
I
l
VD<31:0>
CY7C157
csu
II
l
CY7C157
csu
t
I
t
-------------MBus (Level 1)
6001K-1
Selection Guide
6001K-40
6001K-33
40
33
25
Commercial
1720
1555
1390
Commercial
2600
2350
2100
250
250
250
OperatingFrequency(MHz)
'!ypical Supply Current (rnA)
Maximum Supply Current (rnA)
I
I
ReqniredAmbient Airflow - Module Top Side (LFM)
SPARCore is a trademark of ROSS Thchnology, Inc.
SPARC is a trademark of SPARCInternational.
8-52
6001K-25
-~
PRELIMINARY
. 'J:: CYPRESS
CY6001K
,F SEMlCONDUc..'TOR
Thble 1. MBus Connector Pinout[1 J
Functional Description (continued)
Pin #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
The CYM6001K interfaces to the rest of the system via the SPARC
MBus and conforms to the SPARC Reference MMU. This
standardizationallows the CYM600lK to be replaced by other CypressSPARCMBus-based CPU modules without having to modify
any portion of the memory system or I/O. This CPU "building
block" strategy not only decreases the user's time to market, but
also provides a mechanism for upgrading in the field. For a more
complete description of the individual SPARCcomponents used in
the CYM600lK (i.e., the CY7C601 IV, the CY7C602 FPU, the
CY7C604 CMU, and the CY7C157 CSUs), please refer to the
Cypress SPARC RISC User's Guide.
Module Design
Clock Distribution
The CYM6001K uses two module clock signals (MCLKO and
MCLK1) as defined in the MBus Specification. In order to minimize clock skew, traces have been carefully routed. All clock lines
are routed on inner layers of the module PCB, and their impedanceshave been matched. All clock lines have diode termination to
reduce signal undershoot and overshoot.
MBus Connector (Module)
The CYM6001K interface is via the 100-pin SPARC MBus
connector, which is a two-row male connector with 0.050" spacing
(AMP "microstrip" part number 121354-4). The connector is a
controlled impedance-type (55Q + 10%) based on a microstrip
configuration which provides a controlled characteristic
impedance plus very low inductance and capacitance. Separate
power and ground blades are provided for isolation to prevent
noise. Table 1 details the CYM6001K standard connector pinout.
Mating MBus Connector (System Interface Board)
The module connects to the system interface by means of a
standard MBus female connector (AMP vertical receptacle
assembly, part number 121340-4).
Reset and Interrupt Signals
A power-on reset signal is generated to the module from the MBus
via the RSTIN signal. Level-sensitive interrupts (15 max) are
generated to the CY7C601 via the IRLO[3:0] and lines from the
MBus. A value of OOOOb means that there is no interrupt whil.~ a
value of ll11b means an NMI (Non-Maskable Interrupt) is being
asserted.IRL values between 0 and 15 represent interrupt requests
that can be masked by the processor.
Signal Name
RES1
RES3
RES5
IRLO[O)
IRLO[2)
MAD[O)
MAD[2)
MAD[4]
MAD[6)
MAD[8)
MAD[IO)
MAD[12)
MAD[14)
MAD[16)
MAD[18)
MAD[20)
MAD[22]
MAD[24)
MAD[26)
MAD[28]
MAD[30]
MBR[O)
MBG[O]
MCLKO
MCLK1
RES9
RESIO
RES11
RES12
MAD[32]
MAD[34]
MAD[36]
MAD[38)
MAD[40]
MAD[42]
MAD [44]
MAD [46]
MAD[48]
MAD[50]
MAD [52]
MAD [54]
MAD [56]
MAD [58]
MAD [00]
MAD[62]
SPARE2
RES14
RES16
RSTIN
RES18
Blade
Blade #1
Ground
Ground
Ground
Ground
Blade #2
+5V
+5V
+5V
+5V
Blade #3
Ground
Ground
Ground
Ground
Blade #4
+5V
+5V
+5V
+5V
Blade #5
Ground
Ground
Ground
Ground
Pin1f
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Signal Name
RES2
RES4
IRLO(1)
IRLO[3)
RES6
MAD[l)
MAD[3)
MAD[5)
MAD[7)
MAD[9)
MAD[ll)
MAD[13)
MAD[15)
MAD[17)
MAD[19)
MAD[21)
MAD[23)
MAD[25)
MAD[27)
MAD[29]
MAD[31)
RES7
RES8
MRfY
MRDY
MERR
MAS
MBB
SPARE1
MAD[33)
MAD[35)
MAD[37]
MAD[39)
MAD[41]
MAD[43]
MAD[45]
MAD[47]
MAD[49]
MAD[51]
MAD[53]
MAD[55)
MAD[57]
MAD[59]
MAD[61]
MAD [63]
RES13
RES15
AERR
RES17
RES19
Note:
1. RES pins are not used in the CYM600lK but are reserved for other
MBus module upgrades (e.g., multiprocessing, dual CPUs, JTAG capabilities). See the System Design Considerations section for the assigmnents of these reserved pins per the SPARC MBus Specification.
8-53
•
PRELIMINARY
Maximum Ratings[2]
CY6001K
Operating Range
(Provided as guidelines; not tested.)
StorageThmperature .................. - 20°C to +75°C
Ambient Thmperaturewith
PowerAppJied . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +50°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
InputVoltage.......................... - 0.3Vto +7.0V
Range
Ambient
Thmperature[3]
Vee
Commercial
O°Cto +50°C
5V±5%
DC Electrical Characteristics Over the Operating Rangel4]
Description
Parameters
Min.
Thst Conditions
Max.
Units
VOH
Output HIGH Voltage
Vee = Min.,IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Vrn
Input HIGH Voltage
2.1
VIL
lnput LOW Voltage
- 0.5
0.8
V
lIZ
Input Leakage Current (non-clockpins)
Vee = Max., Vss.:5. VOUT.:5. Vee
-10
+10
rnA
2.4
V
0.5
V
Vee
V
Icu
I~
VD<:31:0>
CY7C605
CMU-MP
I
U
csu
ff
VA<31:0>
I
II
U
, ,
CY7C157
CY7C602
FPU
CY7C601
IU
CY7C157
csu
H
I
CY7C605
CMU-MP
--- ------------- --
I
I
~
VD<31:0>
CY7C157
csu
II
U
CY7C157
csu
t
I
t
------------MBus (Level 2)
6002K-1
Selection Guide
6002K-40
6002K-33
40
33
25
Commercial
3700
3380
3040
Commercial
5600
5100
4600
Required Ambient Airflow - Module Top Side (LFM)
300
200
300
200
300
Required Ambient Airflow - Module Bottom Side (LFM)
OperatingFrequency(MHz)
'JYpical Supply Current (rnA)
Maximum Supply Current (rnA)
I
I
SPARCore is a trademark of ROSS Technology,Inc.
SPARC is a trademark of SPARCIntemational
8-58
6002K-25
200
·:,~
'~~DucrOR
PRELIMINARY
Functional Description
The CYM6002K SPARCore Module is a complete dual-SPARC
CPU board. It is packaged as a compact PCB and interfaces to the
remainder of the system via a SPARC-standard MBus connector.
Each of the two CPUs on the CYM6oo2Kconsists of a high-speed
integer unit (CY7C601), floating-point unit (CY7C602), cache
controller and memory management unit for multiprocessing
systems (CY7C605), and two 16K x 16 CY7C157 cache storage
units (providing a 64-Kbyte cache for the CPU). The CYM6oo2K
deliverssustained performance of 59 MIPS and 13/9 (single precision/doubleprecision) MFLOPS at an operating frequency of 40
MHz. The CYM6002K also achieves a SPECthruput rating of 51.
IC components are surface mounted for a compact footprint and
high frequency of operation. The CYM6002Kfits within the clearance envelope for MBus modules per the SPARC MBusSpecification.
The CYM6002K interfaces to the rest of the system via the SPARC
MBus and conforms to the SPARC Reference MMU. This
standardization allows the CYM6002K to be replaced by other
Cypress SPARC MBus-based CPU modules without having to
modify any portion of the memory system or I/O. This CPU
"building block" strategy not only decreases the user's time to
market,but provides a mechanism for upgrading in the field. For a
more complete description of the individual SPARC components
used in the CYM6002K (i.e., the CY7C601 IV, the CY7C602
FPU, the CY7C605 CMU-MP, and the CY7C157 CSUs), please
refer to the Cypress SPARC RISC User's Guide.
Module Design
Clock Distribution
The CYM6002K uses four module clock signals (MCLKO,
MCLK1,MCLK2,andMCLK3) as defined in the MBus Specification. MCLKO and MCLK2 are used for CPUO, and MCLK1 and
MCLIGforCPU1. In order to minimize clock skew, all traces have
CYM6002K
been carefully routed. All clock lines are routed on inner layers of
the module PCB, and their impedances have been matched. All
clocklines have diode termination to reduce signal undershootand
overshoot.
MBus Connector (Module)
The CYM6002K interface is via the 1OO-pin SPARe MBus
connector, which is a two-row male connector with 0.0501 spacing
(AMP "microstrip" part number 121354-4). The connector is a
controlled impedance-type (50g ±1O%) based on a microstrip
configurationthat provides a controlled characteristic impedance
plus very low inductance and capacitance. Separate power and
ground blades are provided for isolation to prevent noise transference. Table 1 details the CYM6002K standard connector pinout.
ThisMBus connector supports Level 2 MBus.
Mating MBns Connector (System Interface Board)
The module connects to the system interface by means of a
standard MBus female connector (AMP vertical receptacle
assembly, part number 121340-4).
Reset and Interrupt Signals
Apower-on reset signal is generated to the module from the MBus
via the RSTIN signal. Each CPU has its own direct set of interrupt
lines. Level sensitive interrupts (15 max) are generated to each
CY7C601 via the IRLO[3:01 and IRLl[3:01lines from the MBus. A
value of OOOOb means that there is no interrupt, while a value of
Illlb means an NMI is being asserted. IRL values between 0 and
14 represent interrupt requests that can be masked by the
processor.
MBns Request and Grant Signals
Two separate sets of request and grant signals (MBR[Ol, MBG[Ol,
MBR[11, and MBG[l]), one for each CPU, are generated to/from
the CYM6oo2Kmodules to arbitration logic on the motherboard.
8-59
•
~
=.
.;Z
PRELIMINARY
CYPRESS
. , SEMICONDUCTOR
CYM6002K
Thble 1. MBus Connector pinoud l ]
Pin #
Signal Name
1
RESl
3
RES3
5
RES5
7
IRl1l[O]
9
IRl1l[2]
11
MAD[O]
13
MAD[2]
15
MAD[4]
17
Blade
Blade #1
Ground
Ground
Pin #
Signal Name
Pin #
Signal Name
Blade
Pin #
Signal Name
2
RES2
51
MCLK2
Ground
52
MERR
4
RES4
53
MCLK3
6
IRl1l[l]
55
MBR[l]
8
IRl1l[3]
57
MBG[l]
58
SPAREl
10
RES6
59
MAD[32]
60
MAD[33]
Ground
54
MAS
56
MBB
12
MAD[l]
61
MAD[34]
Blade #4
62
MAD[35]
14
MAD[3]
63
MAD[36]
+5V
64
MAD[37]
16
MAD[5]
65
MAD[38]
66
MAD[39]
MAD[6]
18
MAD[7]
67
MAD[40]
19
MAD[8]
20
MAD[9]
69
MAD[42]
21
MAD[10]
Blade #2
22
MAD[l1]
71
MAD[44]
23
MAD[12]
+5V
24
MAD[13]
73
MAD[46]
25
MAD[14]
26
MAD[15]
75
MAD[48]
27
MAD[16]
28
MAD[17]
77
MAD[50]
78
MAD[51]
29
MAD[18]
30
MAD[19]
79
MAD[52]
80
MAD [53]
31
MAD[20]
32
MAD[21]
81
MAD [54]
82
MAD [55]
33
MAD[22]
34
MAD[23]
83
MAD[56]
84
MAD [57]
35
MAD[24]
36
MAD[25]
85
MAD[58]
86
MAD [59]
37
MAD[26]
38
MAD[27]
87
MAD[60]
88
MAD[61]
39
MAD[28]
40
MAD[29]
MAD[62]
90
MAD[63]
41
MAD[30]
42
MAD[31]
89
91
92
IRL1[0]
43
MBR[O]
44
MSH
93
IRL1[1]
94
IRL1[2]
45
MBG[O]
46
MIH
95
IRL1[3]
96
AERR
47
MCLKO
48
MRTY
97
RSTIN
98
RES7
49
MCLKl
50
MRDY
99
RES8
100
RES9
Ground
Ground
+5V
+5V
+5V
Blade #3
Ground
Ground
Note:
1. RES pins are not used in the CYM6002K but are reserved for other
MBus module upgrades. See the System Design Considerations section for the assignments of these reserved pins per the SPARC MBus
Specification.
8-60
SPARE2
+5V
+5V
+5V
Blade #5
Ground
Ground
Ground
Ground
68
MAD[41]
70
MAD[43]
72
MAD[45]
74
MAD[47]
76
MAD[49]
;~
.
_=
-.r
PRELIMINARY
C'YPRESS
SEMICONDUCTOR
Maximum Ratings[2]
CYM6002K
Operating Range
(Provided as guidelines; not tested.)
Storage Temperature ................... Ambient Temperaturewith
Power Applied ............................
Supply Voltage to Ground Potential. . . . . . .. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . -
20°C to + 75 aC
Range
Ambient
Thmperaturel3]
Vee
Commercial
oaCto +50°C
5V±5%
OaCto +50°C
0.5V to + 7.0V
O.3V to + 7.0V
DC Electrical Characteristics Over the Operating Range[4]
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
Min.
Max.
Units
2.4
2.1
V
0.5
V
Vee
V
- 0.5
0.8
V
-10
+10
rnA
Vee = Max., Vss.:'S. VOUT.:'S. Vee
- 40
+40
rnA
Vee = Max., Vss.:'S. VOUT.:'S. Vee
- 15
+15
rnA
Vee = Max., VOUT = OV
- 30
- 350
rnA
VIL
Input LOW Voltage
lIZ
Input Leakage Current (non-clock pins)
Vee = Max., Vss.:'S. VOUT.:'S. Vee
leLIa
Input Leakage Current (clock pins)
Ioz
Output Leakage Current
Ise
Output Short Circuit Currentl4]
Capacitance [5]
Parameters
Description
Test Conditions
Max.
Units
20
pF
24
pF
30
pF
CIN
InputCapacitance
COUT
Output Capacitance
CIQ
Input/OutputCapacitance
ClNeLK
Clock Input Capacitance
70
pF
Vee = 5.0V
TA = 2soC,f= 1 MHz
Notes:
2. All power and ground pins must be connected to other pins of the
same type before any power is applied to the module. At least one
clock cycle must be applied to the module to set up the internal chip
drivers properly.
3. Ambienttemperature is the temperature ofthe air in immediate proximity of the module.
4.
5.
8-61
Not more than one output should be tested at one time. Duration of
the short circuit should not be morc than one second.
Tested initially and after any design or process changes that may affect
these parameters.
•
o
C/)
~
~
.
=--,·iI
PRELIMINARY
CYPRF.SS
SEMlCONDUClDR
CYM6002K
AC Electrical Characteristics Over the Operating Rangel6, 7]
Synchronous signals[S]
Description
Parameter
CYM60OZK-40 CYM6002K -33 CYM6002K-2S
Signal
Edge
Max.
Min.
tcy
ClockCyc1e
tCHL
Clock High and Low
11.5
tR,tF
ClockRise and Fall (between 0.8V and 2.0V)
0.8
25
Min.
Max.
30
13.5
Max.
Min.
13.5
16.5
0.8
Units
ns
40
18.5
21.5
0.8
ns
Vlns
tSKU
CiockSkew[9]
tMOD
MAD(63:0) Output Delay
CLK+
tMOH
MAD(63:0) Output Valid
CLK+
4
4
4
ns
tMIS
MAD( 63:0) Input Set-Up
CLK+
3.5
5.5
7.5
ns
tMill
MAD( 63:0) Input Hold
CLK+
4.5
4.5
4.5
troD
MBus Bused Control Output Delay
CLK+
tCOH
MBus Bused Control Output Valid
CLK+
4
4
4
ns
tCIS
MBus Bused Control Input Set-Up
CLK+
5.5
8
10
ns
tCill
MBus Bused Control Input Hold
CLK+
4.5
tpOD
MBus Point-to-Ibint Control Output Delay
CLK+
tpOH
MBus Point-to-Ibint Control Output Valid
CLK+
3.5
3.5
3.5
ns
tpIS
MBusPoint-to-lbintControIInputSet-Up
CLK+
7.5
9
11
ns
tpill
MBus Point-to-Ibint Control Input Hold
CLK+
4
4
4
ns
tRIS
PORInput Setup
CLK+
5
5
5
ns
tRill
PORInputHold
CLK+
6
6
6
ns
tus
IRL Input Setup
CLK+
5
5
5
ns
tUH
IRL Input Hold
CLK+
7
7
7
ns
1.0
2.0
2.0
us
20
22
30
ns
19
ns
21
4.5
29
4.5
17
ns
ns
19
27
ns
Asynchronous signals [10, 11]
Parameter
RSTINt:12]
Description
MBusReset
Input
Notes:
6. Thst conditions assume signal transition times of 3 ns or less, a timing
7.
8.
CYM6002K-40 CYM6002K-33 CYM6002K - 2S
Signal
type
reference level of 1.Sv, input levels of 0 to 3.0V, and output loading of
80~pacitance, not including the module itself (with the exception
of MBR, tested with an output loading of 40 pF).
All measurements made at MBus connector.
All timing parameters are relative to one of the two processors (e.g.,
tMOD is guaranteed relative to MCLKO for Processor 0 and relative to
MCLKI for Processor 1.)
9.
Min. IMax.
Min. I Max.
Min. IMax.
500
500
500
I
I
I
Units
ms
Measured between any two CLK signals. The relaxed skew requirements for 25 and 33 MHz should be considered carefully since upgrading to 40 MHz requires a 1.0-ns or shorter clock skew.
10. The module requires that the interrupt lines (IRLO[O:3]) remain valid
until the interrupt is cleared by software with a miuimum of two clock
cycles.
11. The asynchronous error signal, AERR, wiD remain asserted until the
AFAR register in the CY7C60S is read by software.
12. Measured at room temperature.
8-62
~
~~PRF.SS
~_~ ~EMICONDUCfOR
PRELIMINARY
CYM6002K
Mechanical Dimensions[13, 14, 15]
MBus connector (AMP PIN 121354-4, 100-pin male, .0647" height)
Top View
Heat Sink
Pin 1
+
CYM6002K
B
I' I
I I
I I
: I'
iI
I
I' I
1\
I, I
2.75"
1
(69.8
i
I
I
I
I
EJ
II'
I I
I, I
.100" (2.54 mm)
(3.17mm)
.200' (5.08 mm)
2.100" (53.34
mm)
~--- - - -
-
-
-
- - - 5.40" (137.16 mm)- -
-
-
-
-
-
- --
1 4 - - - - - - - - - - - - - - 5.78'(146.70mm)----------
Side View
TI
CY7C157
t-
.20" (5.1 mm)
i
J
L.807" (20.3 mm) Stack height includes mated connector
(male and female)
+ .067' thickness of module PCB
6002K-2
Notes:
13. Drawing is not to scale.
14. All tolerances are per ANSI/IPC-D-300G Specification (Class B).
15. Thesedimensions are CYM6002K-specific but are also within tbe mechanical limits specified for MBus modules. Th ensure compliance
witballfuture MBusmodules, systems developersshouJd design to tbe
MBus module envelope per the SPARCMBus Specification.
8-63
•
==-
~
~
- -i1
~,
PRELIMINARY
CYPRESS
SEMlCONDUCTOR
CYM6002K
MBus Timing Diagram
Single Read Transaction
elK
DATA
MAD(63:0)
M"
~~__~~'~1+-__
t_po_H__
~,-Jlr____--------__------__----
"'"-----,--t 11tplS
tplH
~ tCOD .~
~
tcoHll;--
tCOD
-
~I tCIS
r-I
tCIH
r-
~
System Design Considerations
The CYM6002Kimplements a subset of all possible MBus signals;
signals that are optional and/or specifically for JTAG test capabilities may not be supported. However, the MBus connector, per the
SPARCMBusSpecification, defines the assignments listed in Table
2 for pins reserved on the CYM6002K. Systems designers should
be aware of these assignments in order to more easily upgrade to
other and future MBus modules.
Thble 2. Pins Reserved on CYM6002K
Pin #
Signal Name
Pin #
Signal Name
1
SCANDI
2
SCANTMS1
3
SCANDO
4
SCANTMS2
5
SCANCLK
10
INTOUT
98
m[l]
99
m[2]
100
m[3]
6002K-3
All MAD, bused control, and point-to-point control signals use
8-mA drivers (with the exception of MAS, which uses a 16-mA
driver). The MSH and AERR signals use an open drain driver.
The following pull-up resistors are recommended for the MBus
signals: MSH is pulled up to 5V with a 620Q resistor; AERR is
pulled up to 5V with a 1.5 KQ resistor; all other MBus signals are
pulled up to 5V with 10 KQ resistors.
As the frequency of operation increases, transmission line effects
playa bigger role. Care must be taken to keep skew between any
two clock signals at the MBus connector within the specifications
given in the Synchronous Signals table in the ACCharacteristics
section. MBus signal lines must be routed carefully to minimize
crosstalk and interference. A thorough SPICE analysis of the motherboard design is recommended. For a discussion of the intricacies of high-frequency design, see the application note titled
"High-SpeedSPARC CMOS System Design" in the Cypress Applications Handbook.
Use of HH Smith #4387 (3/4" length by 1/4" OD) stand-offs on
the motherboard or equivalent is recommended to support the
module and prevent damage to the connector.
Document #: 38-R -00008
8-64
CYM6003K
PRELIMINARY
SPARCore@) CPU Module
for Multiprocessing
Features
• SPARC compliant
- SPARC Instruction Set Architecture (ISA) compliant
- Conforms to SPARC Reference
MMU Architecture
- Conforms to SPARC Level 2 MBus
Module Specification (Revision 1.2)
• Complete SPARC@ CPU solution
including cache
- CY7C601 Integer Unit (IU)
- CY7C602 Floating-Point Unit
(FPU)
- CY7C605 Cache Controller and
Memory Management Unit for
Multiprocessing (CMU - MP)
-Tho CY7C157 Cache Storage Units
(CSU)
• Available at 25, 33, and 40 MHz
• Each SPARCore module features:
- SPARC integer and floating-point
processing
- Zero-wait-state, 64-Kbyte cache
- Demand-paged virtual memory
management
- Surface-mount packaging for more
compact design
- Provides CPU upgrade path at
module level
• Full multiprocessing capability
- Hardware support for symmetric,
shared-memory multiprocessing
- Level 2 MBus support for cache
consistency
- Direct data intervention
- Reflective memory support
• Module design
-Tho power and two ground planes
- Minimum-skew clock distribution
- MBus-standard form factor: 3.30"
(8.34 cm) x 5.78" (14.67 cm)
• SPARCore MBus connector
- SPARC standard
- Separate power and ground blades
(100 active pins)
- Designed for high frequency (low
capacitance, low inductance)
• High performance
- 32 MIPS (sustained)
-7MFLOPS [SP],5 MFLOPS [DP]
(sustained)
- 28 SPECmarks
•
Logic Block Diagram
r------------------,
CY7C602
FPU
CY7C601
IU
ff
VA<31:0>
I~
VD<31:0>
CY7C605
CMU-MP
L- _ _ _
~
If
o
~
a::
I
!
I CY7C15711
csu
:!
CY7C157!
csu
f
f
-------------MBus (Level 2)
6003K-1
Selection Guide
6003K-40
6003K-33
40
33
25
Commercial
1850
1690
1520
Commercial
2800
2550
2300
250
250
250
Operating Frequency (MHz)
Typical Supply Current (mA)
Maximum Supply Current (mA)
I
I
Required Ambient Airflow - Module Top Side (LFM)
SPARCore is a trademark of ROSS Technology, Inc.
SPARC is a trademark of SPARCInternational
8-65
6003K-25
fUl~
PRELIMINARY
Functional Description
The CYM6oo3K SPARCore Module is a complete SPARC CPU
board. It is packaged as a compact PCB and interfaces to the remainder of the system via a SPARC-standard MBus connector.
The CPU on the CYM6oo3K consists of a high-speed integer
unit (CY7C601), floating-point unit (CY7C602), cache controller
and memory management unit for multiprocessing systems
(CY7C60S), and two 16K x 16 CY7C1S7 cache storage units
(providing a 64-Kbyte cache for the CPU). The CYM6003K
delivers sustained performance of32 MIPS and 7/5 (double precision/single precision) MFLOPS at an operating frequency of 40
MHz, and an overall SPECmark rating of 28. IC components are
surface mounted for a compact footprint. The CYM6003K fits
within the clearance envelope for MBus modules per the SPARC
MBus Specification.
The CYM6oo3K interfaces to the rest of the system via the
SPARC MBus and conforms to the SPARC Reference MMU.
This standardization allows the CYM6oo3K to be replaced by
other Cypress SPARC MBus-based CPU modules without having
to modify any portion of the memory system or I/O. This CPU
"building block" strategy not only decreases the user's time to
market, but also provides a mechanism for upgrading in the field.
For a more complete description of the individual SPARC
components used in the CYM6003K (i.e., the CY7C601 IU, the
CY7C602 FPU, the CY7C60S CMU-Mp, and the CY7C1S7
CSUs), please refer to the Cypress SPARC RISC User's Guide.
CYM6003K
are routed on inner layers of the module PCB, and their impedances have been matched. All clock lines have diode termination
to reduce signal undershoot and overshoot.
MBus Connector (Module)
The CYM6003K interface is via the loo-pin SPARC MBus
connector, which is a two-row male connector with 0.050"
spacing (AMP "microstrip" part number 121354-4). The connector is a controlled impedance-type (SSg ±10%) based on a
microstrip configuration that provides a controlled characteristic
impedance plus very low inductance and capacitance. Separate
power and ground blades are provided for isolation to prevent
noise. 1/zb/e 1 details the CYM6003K standard connector pinout.
Mating MBus Connector (System Interface Board)
The module connects to the system interface by means of a
standard MBus female connector (AMP vertical receptacle
assembly, part number 121340-4).
Reset and Interrupt Signals
Module Design
A power-on rR'sitgnal is generated to the module from the
MBus via the
N signal. Level-sensitive interrupts (15 max)
are generated to the CY7C601 via the IRLO[3:0] and lines from
the MBus. A value of OOOOb means that there is no interrupt,
while a value of lll1b means an NMI (Non-Maskable Interrupt)
is being asserted. IRL values between 0 and 15 represent
interrupt requests that can be masked by the processor.
Clock Distribution
MUus Request and Grant Signals
The CYM6003K uses two module clock signals (MCLKO and
MCLK1) as defined in the MBus Specification. In order to minimize clock skew, traces have been carefully routed. All clock lines
One set of request and grant signals (MBR[O] and MBG[O]) is
generated to/from the CYM6oo3Kmodule to arbitration logic on
the motherboard.
8-66
--.-=-
,~
PRELIMINARY
=''::;CYPRESS
F
CYM6003K
SEMICONDucrOR
Table 1. MBus Connector Pinout[l]
Pin #
Signal Name
1
RES1
3
RES3
5
RES5
7
IRLO[O]
9
IRLO[2]
11
MAD[O]
13
MAD[2]
15
MAD [4]
Blade
Blade #1
Ground
Ground
Ground
Ground
Pin #
Signal Name
Pin #
Signal Name
Blade
Pin #
Signal Name
2
RES2
51
RES7
Ground
52
MERR
4
RES4
53
RES8
6
IRLO[1]
55
RES9
8
IRLO[3]
57
RES10
58
SPARE1
10
RES6
59
MAD(32)
60
MAD[33]
MAD(35)
Ground
54
MAS
56
MBB
12
MAD[1]
61
MAD[34]
Blade #4
62
14
MAD[3]
63
MAD[36]
+5V
64
MAD[37)
16
MAD[5]
65
MAD[38]
66
MAD[39)
17
MAD[6)
18
MAD[7]
67
MAD[40)
19
MAD[8]
20
MAD[9]
69
MAD(42)
21
MAD[10)
Blade #2
22
MAD[ll]
71
MAD(44)
23
MAD[12)
+5V
24
MAD(13)
73
MAD(46)
26
MAD[15]
75
MAD[48)
28
MAD[17]
77
MAD[50]
30
MAD[19]
79
MAD[52]
32
MAD(21)
81
MAD [54]
34
MAD(23)
83
MAD [56]
36
MAD(25)
85
MAD[58]
+5V
+5V
MAD(41)
70
MAD(43)
72
MAD(45)
74
MAD[47)
76
MAD[49)
78
MAD(51)
80
MAD[53]
82
MAD [55]
84
MAD [57]
25
MAD(14)
27
MAD[16)
29
MAD[18]
31
MAD[20)
33
MAD(22)
35
MAD(24)
37
MAD(26)
38
MAD(27)
87
MAD[60]
39
MAD(28)
40
MAD(29)
89
MAD[62]
41
MAD(30)
42
MAD[31)
91
SPARE2
43
MBR[O)
44
MSH
93
RES 12
45
MBG[O]
46
MIH
95
RES 14
47
MCLKO
48
MRTY
97
RSTIN
98
RES15
49
MCLK1
50
MRDY
99
RES16
100
RES17
+5V
+5V
+5V
Blade #3
Ground
Ground
Note:
I. RES pins are not used in the CYM6003Kbut reserved for other MBllS
module upgrades (e.g., dual CPUs, JTAG test capabilities). See the
8-67
+5V
68
Blade #5
Ground
86
MAD [59]
88
MAD[61]
90
MAD[63]
Ground
92
RESll
94
RES13
Ground
96
AERR
Ground
System Design Considerations section for the assignments of these reserved pins per the SPARC MBllS Specification.
•
o
~
a:
zii91PRFSS
~
PRELIMINARY
CYM6003K
SEMlCCtIDUCTOR
Maximum Ratings[2)
Operating Range
(Provided as guidelines; not tested.)
Storage Thmperature ................... - WOC to +75°C
Ambient Thmperature with
Power Applied ........................... O°C to +50°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
Input Voltage .•....................... - 0.3V to + 7.0V
Range
Ambient
Temperature[31
Vee
Commercial
O°Cto +50oC
5V±5%
DC Electrical Characteristics Over the Operating Ranget41
Parameters
Description
Test Conditions
VOH
Output IflGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input IflGH Voltage
VIL
Input WW Voltage
lIZ
Input Leakage Current (non -clock pins)
leLia
loz
Ise
Output Short Circuit Currend4)
Min.
Max.
Units
2.4
V
0.5
V
2.1
Vee
V
- 0.5
0.8
V
Vee = Max., Vsss VOUTS Vee
-10
+10
rnA
Input Leakage Current (clock pins)
Vee = Max., Vsss VOUTsVee
-40
+40
rnA
Output Leakage Current
Vee = Max., Vss S VOUT s Vee
-15
+15
rnA
Vee = Max., VOUT = OV
-30
- 350
rnA
Capacitance[5)
Parameters
Description
Test Conditions
Max.
Units
10
pF
12
pF
CIN
Input Capacitance
COUT
Output Capacitance
CIO
Input/Output Capacitance
15
pF
CINCLK
Clock Input Capacitance
60
pF
Vee =5.0V
TA = 25°C, f = 1 MHz
Notes:
2. All power and ground pins must be connected to other pins of the
same type before any power is applied to the module. At least one
clock cycle must be applied to the module to set up the internal chip
drivers properly.
3. Ambient temperature is the temperature of the air in immediate proximity of the module.
4.
5.
8-68
Not more than one output should be tested at one time. Duration of
the short circuit should not be more than one second.
Thsted initially and after any design or process changes that may affect
these parameters.
PRELIMINARY
CYM6003K
AC Electrical Characteristics Over the Operating Rangel6, 7]
Synchronous Signals[8)
Parameter
Description
CYM6003K-40
Signal
Edge
Min.
Max.
25
CYM6003K-33
Min.
ley
Dock Cycle
IcHL
Dock High and Low
11.5
tR,tF
Clock Rise and Fall (betweenO.8Vand2.0V)
0.8
tSKU
Dock Skewl9]
tMOD
MAD(63:0) Output Delay
CLK+
tMoH
MAD(63:0) Output Valid
CLK+
4
4
Max.
13.5
Min.
Max.
16.5
0.8
18.5
21.5
2.0
2.0
20
22
30
ns
ns
4
ns
ns
tMIS
MAD(63:0) Input Set-Up
CLK+
3.5
5.5
7.5
tMIH
MAD(63:0) Input Hold
CLK+
4.5
4.5
4.5
leOD
MBus Bused Control Output Delay
CLK+
teoH
MBus Bused Control Output Valid
CLK+
4
ns
21
4
ns
VI""
0.8
1.0
19
Units
ns
40
30
13.5
CYM6003K-2S
29
ns
4
ns
ns
tas
MBus Bused Control Input Set-Up
CLK+
5.5
8
10
taR
MBus Bused Control Input Hold
CLK+
4.5
4.5
4.5
tpOD
MBus Point-to-Point Control Output Delay CLK+
tpOR
MBus Point-to-Point Control Output Valid CLK+
3.5
3.5
3.5
ns
tpIS
MBus Point-to-PointControl Input Set-Up CLK+
7.5
9
11
ns
tpIH
MBus Point-to-Point Control Input Hold
CLK+
4
4
4
ns
tRIS
PmI Input Setup
CLK+
5
5
5
ns
tRIH
POR Input Hold
CLK+
6
6
6
ns
tus
IRL Input Setup
CLK+
5
5
5
ns
tUH
IRL Input Hold
CLK+
7
7
7
ns
17
ns
19
27
ns
Asynchronous Signals [10, 11]
Parameter
RSTIN[12]
Description
MBusReset
CYM6003K-40
Signal
1Ype
Min.
Input
Notes:
6. Thst conditiol1l' assume signal transition times of3 ns or less, a timing
reference level of l.SY, input levels of 0 to 3.0Y, and output loading of
lOO-pF M'pacitance, not including the module itself (with the exception of BR, tested with an output loading of 4{) pF).
7. All measurements made at MBus connector.
8. All timing parameters are guaranteed relative to MCLKO.
9. Measured between any two CLK siguals. The relaxed skew requirements for 25 and33 MHz should be considered carefully since upgrading to 4{) MHz requires a l.O-ns or shorter clock skew.
500
I
I
Max.
CYM6003K-33 CYM6003K-2S
Min.
500
I Max.
I
Min.
500
I
I
Max.
Units
ms
10. The module requires that the interrupt lines (IRLO[0:3]) remain valid
until the interrupt is cleared by software with a mimmum of two clock
cycles.
11. The asynchronous error sigual,~, will remain asserted until the
AFAR register in the CY7C60S is read by software.
12. At room temperature.
8-69
o
(f)
i:t
PRELIMINARY
CYM6003K
Mechanical Dimensions[13, 14, 1S]
+
3.050"
(77.47mm)
I
I
I
I
I
I
I
I
I
I
I
I
3.300'
(83.82mm)
(3.17mm)
1-------------
1. . .
\4--.-----------
5.40" (137.16mm)---------5.78" (146.70 mm)--- -
- --- - -
---~
Side View
TI
-t-L
.802" (20.3 mm) Stack height includes mated connector
(male and female) + .062" thickness of module PCB
6OOOK·2
Notes:
13. Drawing is not to scale.
14. All tolerances are per ANSI/IPC-D-300G Specification (Oass B).
15. These dimensions are CYM6003K-specific but within the mechanical
limits specified for MBus modules. 1b ensure compliance with all future MBus modules, systems developers should design to the MBus
module envelope per the SPARC MBus Specification.
8-70
=z ;;~PRFSS
as'
CYM6003K
PRELIMINARY
SEMJCX::M)I)CTOR
MBus Timing Diagram
Single Read Transaction
elK
IMls
MAD(63:0)
1,_....i.-':"
DATA
- W1i""
oU)
~
System Design Considerations
The CYM6003K implements a subset of all possible MBus signals; signals that are optional andlorspecifically for multiprocessing may not be supported. However, the MBus connector, per
the SPARC MBus Specification, defines the assignments listed in
Thb1e 2 for pins reseIVed on the CYM6003K. Systems designers
should be aware of these assignments in order to more easily upgrade to other and future MBus modules.
Table 2. Pins Reserved on CYM6003K
Pin #
Signal Name
Pin #
Signal Name
1
SCANDI
2
SCANTMS1
3
SCANDO
4
SCANTMS2
5
SCANCLK
10
INTOUT
51
MCLK2
53
MCLKJ
55
MBR1
57
MBG1
92
IRL1[0]
93
IRL1[1]
94
IRL[2]
95
IRL[3]
98
!D[1]
99
!D[2]
100
!D[3]
All MAD, bused control, and point-tMXSint control signals use
8-mA drivers ically, any digital component
that is available in surface-mount packaging can be used, but the
module is not limited to this. Standard and custom modules include
SRAM, FIFOs,dualports,EPROM,Flash,andE2PROM devices,
combined or mixed. Logic may also be employed to provide decoding, pipelinedstorage, or extra drive capability. The CYM1461 and
the CYM1540 are examples of such devices. In the CYMl461, sixteen 32K x 8 RAMs are arranged to form a 512Kx 8 module and
the individual SRAMs are selected by an on board decode. The
CYM1540 provides address and control buffering for a 256K x 9
static RAM module so that only a single device load and capacitance is presented to the system. Other custom modules provide
for unusual memory word widths. The CYMl720 is a memory
module specifically designed for 24-bit-wide DSP processors.
ECLis also a logic family suitable for collecting into a module. Unless the system is largely EeL, it makes sense to place the ECL
components onto a module that is optimized for performance. Delivered as a tested component, the ECL module can be assembled
into the system with high confidence of proper functionality.1YJ>ical examples of custom ECL modules include wide ECL-to-TIL
translators and deep and/or wide ECL PROM or RAM memory
arrays.
More complex functions may also be integrated onto a custom
module; e.g., processor subsystems, embedded within asystem that
are dedicated to specific functions. These functions may include
several forms of memory, a microprocessor or DSp, communication ports, and bus interface circuitry with possibly shared memory
control. A custom module may also include an ASIC designed especially to implement the desired function. One example of such a
device is the CYM4241 deep FIFO. This device includes three
high-speed SRAMs, a surface-mount 50-MHz crystal oscillator,
and a wire-bonded ASIC die on substrate that integrates the RAM
interface control and port access arbitration. This combination of
components yields a 64K by 9 FIFO in a single 28-pin DIP. Bysimply changing the memory content, the device can be extended to
256Kby9.
Modules undergo complete characterization and qualification before being released to production. Characterization includes the
following: AC and DC characterization over voltage and temperature,andcompletecustomspecificationreview.Releasetoproduction requires a verified test program with test hardware and correlation samples, complete assembly drawings and approved parts
list, production and test travelers, a formal design review, and customerapproval. In production,custom (andstandard)modulesare
built using fully tested components, and are rigorously tested before they are shipped. As an example of the rigorous production
testing, memory modules are tested for all DCparametrics, allAC
parametrics, and functionality. FUnctional testing includes a select
set ofmemorypattem sensitivity tests. Thiscomplete testing allows
the module to be treated by the user as a true component with a set
of specifications that are guaranteed by the manufacturer. This
saves time and effort during system manufacture and provides a
degree of reliability not obtainable from operations focused on
only assembly.
Future Technologies
The ultimate in multichip technology is multiple die on a substrate
that offers highly efficient interconnect and the densest multichip
assembly technology. The technology is available now for multi-
chip configurations with silicon chips on ceramic, epoxy laminate,
and silicon substrates.
Introduction to Modules for the New User
The use of modules is growing rapidly since it is a vehicle for obtaining high integration and high performance with minimal impact on cost. Almost every personal computer now has main
memory as plug in SIMM packages constructed from surfacemount DRAM components. High-performance RISC and CISC
CPU subsystems are available as modules where the supplier has
optimized the component I/O design and the substrate layout for
maximum performance amongst the tightly coupled components.
Size is one obvious advantage of modules; their small size allows a
function fit into a very small space. Consider the economics ofhaving a large memory array together with the system CPU on a single
card in contrast to the cost of mUltiple memory cards connected via
a backplane bus and the resulting performance loss. In many cases,
the module approach is a considerable savings in materials and
manufacturing cost by reducing the total number of system cards.
Applying the tight design rules of modules has its limitations. A
module has line widths and spacings that support close packing of
VSOP and die components, and these spacing/width design rules
are at the limit of what can be handled by capable volume production substrate producers. The use of fully tested modules gives the
density gain of tight design rules at economically attractive system
manufacturing yields. Therefore in the manufacturing process, the
module exhibits the characteristics of a monolithic device: high integration, ease of application, and high system manufacturing
yield. The module brings high-density surface-mount technology
to the through-hole manufacturing environment.
Performance is another significant gain obtainable from module
application. Unfortunately this is the most difficult gain to quantify. Consider a memory subsystem collected tightly around a CPU
versus the same memory capacity spread over one or more boards.
It seems intuitively plausible that the larger subsystem will be slower: the distance to travel is longer, and the memory address and
data bus lines have larger capacitance due to their longer length
and the larger number of stubs on the lines. This is indeed the case.
Many of the custom modules include buffers for reduced loading,
registers for data pipelining, and simple or specialized decoders to
ease system bus interfacing. Thken as a component, these modules
typically exhibit higher capacitance than a monolithic component
and incur about 5 ns additional delay for on board decoders or
buffers. However, the module is from four to sixteen times as dense
as through-hole monolithic devices and consequently achieve a net
performance advantage.
Custom Module Development Flow
Multichip's focus is on providing turnkey memory modules. Figure
1 illustrates the tasks performed during the development of the
module.
Module development commences with thegenerationofadetailed
Objective Specification. The module is designed to this specification' and once in production itwill be guaranteed to perform as indicated in the Objective Specification.
Components are selected while the specification is being generated. In many cases, the spec is designed such that multiplesources
of components can be utilized. Once the spec is complete and the
components are selected, a schematic for the module is generated.
The netlist from the schematic is used to drive the circuitsimulator.
9-3
II
U)
LLI
....I
;:)
C
o
::::E
2 ;APRFSS
~
Custom Module Capabilities
SEMICCMJUCTOR
Custom Module Development Flow (continued)
During simulation, several types of analyses are performed. A
function simulation is used to ensure that the module's logic is designed properly. Timing simulation is run to verify that the module
will function when subjected to the worst-case timing delays of the
components. Finally, thermal analysis may be performed to determine the thermal characteristics of the module.
The layout of the module is also netlist driven. An autorouter may
be used, depending on the complexity and density of the module.
Design rule checks are run to ensure that the layout does not violate any electrical or mechanical design rules. Fmally, the layout
output is used to generate the module substrate.
The layout output is also used to drive the pick and place equipment. Thisensuresconsistencybetweendesignandmanufacturing.
While the module prototypes are being assembled, the test program is generated and the test fIXture is constructed. Thst program
generation is largely automated, using as inputs the simulation outputs andpre-definedtestprogramsubroutines forcommonconfigurations.
Once prototypes have been generated, the standard releaseprocedure is initiated. This procedure includes steps such as bench testing' module characterization and qualifICation, and fine tuning of
the test program. Following customer approval of the module, it is
released to production.
Quoting Information
In order to prepare a quotation or proposal, we need as much as
possible of the following information:
• Circuit schematic
• Functional description
• Mechanical dimensions required
• Speed and power requirements
• Prototype and production deadlines
• Production quantity estimates
• An engineering contact to answer questions
Once the above information is received, a budgetary quotation will
typically be provided within one to two weeks.
Figure 1. Custom Module Flow
9-4
This is an abbreviated data sheet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUCTOR
256K X 4 Static RAM Module
Features
Functional Description
• High.density l.megabit SRAM
module
• High.speed CMOS SRAMs
-Access time oUS ns
The CYMl240 is a very high perfonnance
I-megabit static RAM module organized
as 256K words by 4 bits. The module is
constructed using four 256K x 1 static
RAMs in leadless chip carriers mounted
onto a ceramic substrate with pins. It is
socket-compatible with monolithic 256Kx
4SRAMs.
Writing to the memory module is accomplished when the chip select (CS) and
write enable (WE) inputs are both LOW.
Data on the four input/OUlput pins (IlOo
• Low active power
-2.6W (max.)
• SMD technology
• T'fL.compatible inputs and outputs
• Low profile
- Max. height of 0.3 in.
CYM1240
J/03) of the device is written into the
memory location specified on the address
pins (Ao through Au).
Reading the device is accomplishecU!r
taking chip select (CS) LOW while WE
remains inactive or HIGH. Under these
conditions, the contents of the memory
location specified on the address pins will
appear on the appropriate data input/output pins.
The data input/output pins remain in a
high-impedance state when CS is HIGH
or WI! is LOW.
through
• Small PCB footprint
- 0.62 sq. in.
Pin Configuration
Logic Block Diagram
DIP
Top View
I-
f- -
256Kx 1
SRAM
I- -
-
SRAM
I
'-L---
vee
As
Pte
As
Al0
All
A12
A13
A14
A15
AIS
A17
SRAM
T
I
L..-- 256Kx 1
256Kx 1
A7
256Kx 1
SRAM
I
1240-1
Selection Guide
Maximum Standby Orrrent (rnA)
Shaded area contains preliminary information.
9-5
As
~
A3
A2
Al
Ao
NC
'CE
NC
1/°3
1/02
1/°1
1/°0
Vss
WE'
1240-2
II
en
LLI
..J
::::»
C
0
:E
CYM1420
CYPRESS
SEMICONDUCTOR
128K X 8 Static RAM Module
Features
Functional Description
• High-density 1-megabit SRAM
module
The CYM1420 is a very high performance
I-megabit static RAM module organized
as 128Kwordsby8bits. The module is constructed using four 32K x 8 static RAMs
mounted onto a substrate. A decoder is
used to interpret the higher-order addressesA15 andA16 and to select one of the four
RAMs.
• High-speed CMOS SRAMs
- Access time of 20 ns
• 32-pin, 0.6-inch-wide DIP package
• Low active power
-l.2W (max.)
•
•
•
•
Hermetic or plastic SMD technology
1TL-compatible inputs and outputs
JEDEC-compatible pinout
Commercial and military
temperature ranges
Writing to the memory module is accomplishedwhen the chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the eight input/output pins (1/00 - 1/07)
is written into the memorylocationspecifiedontheaddresspins(Ao - A1S).
Readingthe device is accomplished by taki!YLchip select (~and output enable
(OE) LOW while WE remains inactive or
HIGH. Under these conditions, the contents of the memory location specified on
the address pins will appear on the eight input/output pins.
The input/output pins remain in a highimpedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Pin Configuration
Logic Block Diagram
DIP
1bpView
AO-~4--~~15------------~~--------~
~------------~~------~
w£--------------~~------~
1014
Decoder
L..-________-L..__.J..-,~ 1/00 - 110,
1420-1
1420-2
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (mA)
Commercial
1420-20
1420-25
1420-30
1420-35
1420-45
20
30
35
45
55
210
25
210
210
210
210
210
140
140
··',210
Military
Maximum Standby Current (mA)
Commercial
Military
Shaded area contains preliminary information.
9-6
1420-55
210
210
210
140
140
140
140
,",14Q:. ' .
140
140
140
-~
;
CYM1420
Maximum Ratings
(Above which the useful life may be impaired.)
DC Input Voltage ...................... - O.5V to + 7.0V
Output Current into Outputs (LOW) ••....•...•..• 20 rnA
Storage'Thmperature ................. - 6SoC to +1S0°C
Ambient 'Thmperature with
Power Applied ........... -10°C to +8S0C(Commercial)
-55°C to +125°C (Military)
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
Operating Range
Ambient
Temperature
Range
Commercial
Military
Vee
SV± 10%
SV± 10%
O°Cto + 70°C
-SsoC to +125°C
Electrical Characteristics Over the Operating Range
1420
Parameters
Min.
VOH
Description
Output HIGH Voltage
'lest Conditions
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
Ilx
Input Load Current
loz
Output Leakage Current
los
Output Short Circuit
Current!l]
Vee
lee
Vee Operating Supply
Current
ISSl
ISS2
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
2.4
Vee
Units
V
0.4
V
V
-0.5
Vee
0.8
-10
+10
V
+10
!lA
!lA
-300
rnA
~
210
rnA
Automatic ~ Power-Down
Current!2]
Max. Vee; "CS ~ VIH
Min. Duty Cycle = 100%
140
rnA
Automatic ~ Power-Down
Currentl2]
Max. Vee;"CS~ Vee - 0.3V,
VIN ~ Vee - 0.3Vor VIN!'i. 0.3V
80
rnA
GND !'i. VI !'i. Vee
GND !'i. VO!'i. Vee, Output Disabled
-10
= Max., VOUT = GND
= Max., lOUT = 0 mA,
!'i.VIL
II
U)
UJ
..J
::)
Capacitance!3]
Q
Parameters
CIN
Description
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV
Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2.
Max.
3S
40
Units
pF
pF
A pull-up resistor to V cc on the "CS" input is required to keep the device deselected during Vee power-up, otherwise ISBwillexceedvalues
given.
3. Thsted on a sample basis.
AC Test Loads and Waveforms
Rl 481n
Rl 481n
OUTP~~ ~
,~~:FI
J 1
_
R2
OUTP:
-
INCWDING
JIG AND
SCOPE
-
(a)
-
-
(b)
142\h1
I
Equivalent to:
THEVENIN EaUIVALENT
OUTPUT
0
'!JJ..n
0
90%
R2
GND
255n
255n
INCLUDING
JIG AND
SCOPE
~
,~,.~:FI
J 1
_
ALL INPUT PULSES
3.0V - - - !r~-----r
1.73V
9-7
1420-4
o
:E
CYM1420
Switching Characteristics Over the Operating Range[4]
1420-25
1420-20
Parameters
Description
Min.
Max.
Min.
Max.
1420-30
Min.
Max.
Units
READ CYCLE
tRC
tAA
tOHA
tACS
tooE
tLZOE
tHroE
tLZCS
tHZCs
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Zl~J
_CSHIGH to High Zl~. OJ
20
Write Cycle Time
20
CS LOW to Write End
15
15
2
5
15
10
2
0
0
25
20
3
30
25
3
3
25
20
10
0
30
15
10
0
0
20
10
10
3
30
3
5
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLEL1
twc
tscs
tAW
tHA
tSA
tPWE
tso
tHD
tLZWE
tHZWE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Zl>J
WE LOW to High ZL~. 6J
8
25
20
20
2
5
20
12
2
0
0
Max.
Min.
1420-35
Parameters
Description
Min.
I
ns
ns
ns
ns
ns
ns
ns
ns
30
25
25
10
5
5
25
18
3
5
0
1420-45
Max.
ns
15
ns
1420-55
Min.
Max.
Units
READ CYCLE
tRC
tAA
tOHA
tACS
tOOE
tLZOE
tHZOE
tLZCS
tHZCs
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
LOW to Low Z
OE HIGH to High Z
CS LOW to Low Zl>J
CS HIGH to High ZL~. 6J
35
Write Cycle Time
35
30
30
5
5
45
25
25
20
on
45
3
55
45
35
5
35
18
0
5
45
55
30
25
0
20
3
55
0
25
20
5
5
20
20
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
25
ns
os
os
ns
ns
os
ns
ns
ns
ns
WRITE CYCLEt?
twc
tscs
tAW
tHA
tSA
tpWE
tso
tHO
tLZWE
tHZWE
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Zl5J
WE LOW to High Zl~. OJ
18
3
5
0
9-8
55
45
45
40
40
5
5
15
5
5
0
5
5
30
25
15
5
5
0
CYM1420
Switching Waveforms[lOJ
Read Cycle No. 1[8. 9J
~~= ~§"""'-~= EV=lo=u=~=:=~=2=V=1o.=UD=t=Q= = = = :_tRC- .-I-~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ -~-~-,-v- , "-~-IO~ ~ ~ ~ ~ ~ ~ ~ ~ ~1420-5
Read Cycle No. 2[8.10 J
~
tRe
r
~~
tACS
.......
~~
I---
tDOE
tHZOE-
tLZOE
HIGH IMPEDIINCE
D1o.TAVAUD
~~
-
tLZCS-
_j-5O%- - - - = i = : :
-
Vee
SUPPLY
CURRENT
tHZCS
HIGH IMPEDIINCE
DATA OUT
-
tpu
tpo
1420-6
Write Cycle No.1 (WE Controlled)[7. 11J
tscs
tSA
t HA tPWE
1
~'\.~ ItI
r
..,
tSD
]
tHO
D1o.TA-INVALID
"*
I-t--*"
----------------------------------------1~
__~H~IG~H~ ~PE~D1o.~N~ _::~~------:::)---k
'I
-I
j.-
DATA 1/0
::l
- ~//LL 'LLLLLLLLL
tAw
DATA IN
LLI
...I
"if-
'\.'\. \ I'\.'\.'\.T
tHZWE
tLZWE
__
DATA UNDEFINED
1420-7
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of
the specified IOlJIoH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCS is less than
tucs for any given device. These parameters are guaranteed and not
100% tested.
6. tHzcsand tHZWEarespecifiedwithCL = 5 pFasinpart (b) ofACThst
Loads. ltansition is measured ±500 mV from steady state voltage.
7. The internal write time of the memory is defined by the overlap ofi::S
WW and WE Ww. Both signals must be WW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
•
tn
twe
ADDRESS ~~
set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
8.
9.
10.
11.
12.
9-9
WE: is HIGH for read cycle.
=
=
Device is continuously selected, 'CS VIL and 'OJ! VIL'
Address valid prior to or coincident with "CS transition Ww.
Data LO will be higb impedance if'OJ! = VIH.
If CS goes HIGH siumultaneously with WE HIGH, the output remains in a high-impedance state.
C
o
:E
.Tn
CYM1420
~~
Switching Wavefonns (continued)
Write Cyde No. 2 (~Controlled) (7,11,12)
twc
ADDRESS
-
~~
~
tSA
fo
tscs
.1
~
-:f"
tHA
I
tAW
\.\.\.\.'\.'\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.'\:
DATA IN
*"
I
DATAI/O
DATA UNDEFINED
tPWE
"
-: fLLLLLLLLLLLLLL
tSD
DATA-IN VALID
...... tHZWE
tHO
*"
I
1::!!!i!::!!flrU:Ii~"i
142Gl1
'fruth Thble
~
OE
WE
Inputs/Outputs
Mode
DeselectlPowerDown
X
X
HighZ
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
H
Ordering Information
Speed
(ns)
20
CYM1420PD-20C
Package
'lYPe
PD05
25
CYM1420PD-25C
PD05
CYM1420HD-25C
HD04
30
35
45
55
Ordering Code
CYM1420PD-30C
PD05
CYM1420HD-3OC
HD04
Operating
Range
Commercial
Commercial
Commercial
CYM1420PD-35C
PD05
CYM1420HD-35C
HD04
CYM1420HD 35MB
HD04
Military
CYM1420PD 45C
PD05
Commercial
CYM1420HD-45C
HD04
CYM1420HD-45MB
HD04
Military
CYM1420PD-55C
PD05
Commercial
CYM1420HD-55C
HD04
CYM1420HD-55MB
HD04
Commercial
Military
Document #: 38-M-OOOOl-C
9-10
CYM1422
CYPRESS
SEMICONDUCTOR
128K x 8 Static RAM Module
1/07) is written into the memory location
specified on the address pins (Ao through
A1S).
Features
Functional Description
• High-density I-megabit SHAM
module
• High-speed CMOS SHAMs
- Access time of 35 ns
The CYM1422 is a high-performaoce
1-megabit static RAM module orgaoized
as 128Kwords by 8 bits. The module is constructed using four 32K x 8 static RAMs in
SOICs mounted onto a single-sided multilayer epoxy laminate board with pins.Adecoderis used to interpret the higher-order
addresses(A 15 and A16) aod to select one
of the four RAMs.
Readingthe device is accomplished bytaki!!.8....chip select (~and output enable
(DE) LOW while WE remains inactive or
HIGH. Under these conditions, the contents of the memory location specified on
the address pins will appear on the eight
data input/output pins.
Writing to the memory module is accomplishedwhen the chip select (CS) aodwrite
enable (WE) inputs are both LOW. Data
on the eight input/output pins (1/00 through
The input/output pins remain in a highimpedaoce state unless the module is selected, outputs are enabled, aod write enable (WE) is HIGH.
• Low active power
-1.IW (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.65 in.
• Small PCB footprint
-0.8 sq. in.
Logic Block Diagram
Pin Configuration
SIP
Component Side
~ - A,. -......,~15:-------r-------,
~--------------~------~
~----------~~~----~
II
1of4
Decoder
1/00 -I/o,
1'22·1
1422·2
Selection Guide
1422-35
1422-45
45
55
Maximum Operating Current (rnA)
35
200
200
200
Maximum Standby Current (rnA)
140
140
140
MaximumAccess Time (ns)
9-11
1422-55
CYM1422
DC Input Voltage ..........•........... - O.5V to + 7.0V
Output Current into Outputs (LOW) .•......••.... 20 rnA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage'Thmperature ................. Ambient 'Thmperature with
Power Applied .•.............•........
Supply Voltage to Ground Potential. . . . . ••
DC Voltage Applied to Outputs
in High Z State ..... . . . . . . . . . . . . . . . . . ..
Operating Range
6S·C to +lS0·C
-10·Cto +90·C
- O.5V to + 7.0V
Ambient
Temperature
O·Cto + 70·C
Range
Commercial
Vee
SV± 10%
- O.SV to + 7.0V
Electrical Characteristics Over the Operating Range
Parameters
'lest Conditions
Description
Output HIGH Voltage
Output LOW Voltage
Input mGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Vee Operating Supply
Current
Automatic CS Power-Down
Current(1)
VOH
VOL
VIR
VIL
IJX
loz
lee
ISBl
2.2
-0.5
Vee
0.8
-15
-15
+15
+15
J.LA
J.LA
200
rnA
Max. Vee;rn~ VIR
Min. Duty Cycle = 100%
140
rnA
Max. Vee; rn ~ Vee - 0.3Y,
VIN> Vee - 0.3V or VIN < 0.3V
80
rnA
= Min., IoH = -4.0 rnA
= Min., IOL = 8.0 mA
0.4
GND~VI~Vee
GND < Vo < Vee, Output Disabled
~
= Max., lOUT = 0 rnA,
~VIL
Automatic CS Power-Down
Currentl1)
ISB2
1422
Max.
Units
V
V
V
V
Vee
Vee
Min.
2.4
Capacitance(2)
Parameters
CIN
Description
Input Capacitance
COUT
Output Capacitance
'lest Conditions
TA = 25·C, f
Vee = S.OV
= 1 MHz,
Max.
40
Units
pF
35
pF
Notes:
1.
A pull-up resistor to Vcc on the CS input is required to keep the device deselected during V ccpower-up, othelWise Isu will exceed values
2.
Thsted on a sample basis.
given.
AC Test Loads and Waveforms
R1 481.n.
OUTP:
R1 481.n.
ALL INPUT PULSES
~ OUTP~~ ~
'n~:FI
'n,.~:FI
J 1
_
J 1
_
R2
255
INCLUDING
JIG AND
SCOPE
-
-
90%
R2
.n.
25S
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
3.0V---
-
-
(b)
1422-3
I
THEVENIN EQUIVALENT
167.n.
OUTPUT ~ 1.73V
9-12
GND
.n.
1422-4
g-jt~
""5!!!!1'
CYM1422
SEMJCa.IDUCTOR
Switching Characteristics Over the Operating Rangel3]
1422-35
Min.
Description
Parameters
Max.
1422-45
Min.
Max.
1422-55
Min.
Max.
Units
55
ns
55
30
ns
READ CYCLE
tRC
Read Cycle Time
tM
Address to Data Valid
tORA
Data Hold from Address Change
tACS
~ WW
tDOE
<:m WW to Data Valid
trzoE
(YE WW to Low Z
tHroE
(YE HIGH to High Z
trzes
CS WW to Low Zl4J
tHZCs
tpu
CSHIGH to High ZL4.>J
20
0
Write Cycle Time
CS LOW to Write End
tAW
Address Set-Up to Write End
tRA
Address Hold from Write End
tSA
Address Set-Up to Write Start
35
30
30
5
5
tpWE
WE Pulse Width
25
20
3
3
0
tLZWE
WE HIGH to Low ZL4J
WI! LOW to High ZL4. >J
tHZWE
Notes:
3. Thst conditions assume signal transition times of S ns or less. timing
reference levels of loS¥, input levels of 0 to 3.0¥, and output loading of
the specified IOlJIoH and 30·pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tucs for any given device. These parameters are guaranteed and not
100% tested.
S. tHzcs and tHZWE are specified with CL = S pF as in part (b) ofACThst
Loads. nansition is measured ±SOO mV from steady state voltage.
6. The internal write time of the memory is defined by the overlap ofCS
LOW and WE Ww. Both signals must be WW to initiate a write,
40
40
5
5
35
20
5
3
0
25
ns
55
55
45
45
5
5
35
20
5
3
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
II
ns
25
ns
and either signal can terminate a write by going IDOH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
7. WI! is IDOH for read cycle.
8. Device is continuously selected, CS = VIL and UR = VIL.
9. Data I/O will be high impedance iflJE = V!H.
10. Address valid prior to or coincident with CS transition Ww.
11. If CS goes IDOH siumultaneously with WI! IDOH, the output remains in a high-impedance state.
fJ)
LLI
..J
::::>
C
::E
*__
=*§t---,~
Read Cycle No. 1[7·8]
",TAO"T
45
20
20
0
45
ns
ns
o
Switching WaveCormsl9]
"ORES'
20
ns
ns
20
3
0
35
twc
Data Hold from Write End
3
3
ns
3
20
20
tscs
Data Set·Up to Write End
25
3
3
ns
3
45
35
20
tpD
CS HIGH to Power·Down
WRITE CYCLEl6J
tSD
3
3
CS WW to Power·Up
55
45
35
to Data Valid
tHO
45
35
"~::~------------------------DA-~-A-V~--ID-------------------1422·5
9-13
CYM1422
Switching Waveforms (continued)
Read Cycle No. 2[7. 10)
tAC
----:! r
~~
tACS
.,IL
..:l~
~
tOOE
t HZOE -
tlZOE
tHzcs
HIGH IMPEDANCE
DATA OUT
-
HIGH IMPEDANCE
DATA VALID
tlZCS-
--------~-~-------------------------------------~::
I---tpo
-
Vee
SUPPLY
CURRENT
tpu
1422-6
Write Cycle No.1 (WE Controlled)[6)
twc;
~~
..U·
ADDRESS
tscs
.... .,.//// ' / / / / / / / / /
'\.'\.\ '\.'\.'\.'T
tHA-
tAW
-I
tSA
tPWE
~'\. '\..::1 ~
"::l ~
1
tHO
tSD
DATA IN
~~
----------------------------------;!~
__~HIG~H=IM~~DAN~~~_-:t~-_:::::::
:::)----k
I--
DATA OUT
-l~
DATA-IN VALID
f---
t HZWE
tLZWE
DATA UNDEFINED
1422-1
Write Cycle No.2
(CS Controlled) [6.11)
ADDRESS
'"l~
twc
-
~~
tSA
tscs
'T
..., ~
tHA
tAW
tPWE
'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.~r-
"".l
' // / / 7777// / / / /
tHO
tSD
-t-
DATA IN
'I
DATA OUT
DATA-IN VALID
ioI-
tHZWE
-t'I
~lSitllr.1I:1i~"i
DATA UNDEFINED
1422-6
9-14
=:,r.~
CYM1422
Ordering Information
'fruth Table
~
m:
WE
H
X
X
HighZ
DeselectIPower-Down
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
Speed
(ns)
Mode
Ordering Code
Package
lYPe
Operating
Range
35
CYM1422PS-35C
PS03
Commercial
45
CYM1422PS-45C
PS03
Commercial
55
CYM1422PS-55C
PS03
Commercial
Document #: 38-M-00003-B
II
en
UJ
....I
~
C
o
:E
9-15
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications.
CYM1423
CYPRESS
SEMICONDUCTOR
128K X 8 Static RAM
Module
Features
Functional Description
• High-density I-megabit SRAM module
TheCYMI423isahigh-performance
I-megabitstaticRAMmoduleorganizedas
128Kwordsby8bits. This module is constructedusingfour 64Kx4static RAMsin
SOJpackagesmoUDtedontoanepoxylaminateboardwithpins.Adecoderisusedto
interpretthehigher-orderaddressandselecttwo of the four RAMs.
• High-speed CMOS SRAMs
- Access time of 45 ns
• 32-pin, 0.6-inch-wide DIP package
• JEDEC-compatiblepinout
• Low active power
-1.2W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Commercial temperature range
\\Titing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
eight input/output pins (liDo through 1107)
of the device is written into the memory
location specified on the address pins (Ao
throughA16). Reading the device isaccompJished by taking chip select (CS) and output enable (DE) LOW, while write enable
(WE) remains inactive or HIGH. Under
these conditions, the contents of the memory location specified on the address pins
(Ao through A 16) will appear on the eight
input/output pins (liDo through 1107).
Theinput/outputpinsremaininahigh-inlpedance state uuless the module is
selected, outputs are enabled, and write enable (WE) is HIGH.
• Small PCB footprint
-1.1 sq. in.
Logic Block Diagram
Pin Configuration
DIP
Thp View
Ao - A 15 -----------,r-------,
~------------_,rr--------,
NC
A 1a
~-------------.+;--------,
A14
A12
A7
Aa
A5
A4
As
A2
A1
Ao
1/0 0
1/0 1
1/0 2
10f2
Decoder
GND
L.._ _ _ _ _.L...--L_
1/00 - I/o,
1423-1
1423-2
Selection Guide
1423-45
1423-55
MaxinlumAccess Tinle (ns)
45
55
70
MaxinlumOperatingCurrent(mA)
210
210
210
Maxinlum Standby Current (mA)
80
80
80
9-16
1423-70
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUCTOR
256K X 8 Static RAM Module
Features
Functional Description
• High-density 2-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 25 ns
The CYM1441 is a very high performance
2-megabit static RAM module organized
as 256K words by8 bits. The module is constructed using eight 256K x 1 static RAMs
in SOJ packages mounted onto an epoxy
laminate substrate with pins. Tho chip selects (CSL and CSu) are used to independentlyenable the upper and lower 4 bits of
the data word.
• Low active power
- 5.3W (max.)
•
•
•
•
SMD technology
Separate Data I/O
6O-pin ZIP package
TIL-compatible inputs and outputs
Writing to the memory module is accomplishedwhen the chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the eight input pins (DIo through Dh) is
written into the memory location specified on the address pins (Ao through A 17).
• LowprofIle
- Max. height of 0.5 in.
• Small PCB footprint
-1.14 sq. in.
CYM1441
Readingthe device is accomplished bytaking ci!!E.select (CS) LOW while write enable WE remains inactive or HIGH. Under these conditions, the contents of the
memory location specified on the address
pins will appear on the appropriate data
output pins (DOo through DOl).
The data output pins remain in a highimpedance state unless the module is selected and write enable (WE) is HIGH.
Tho pins (PDo and PDl) are used to identify module memory density in applications wehre alternate versions of the JEDEC-standard modules can be interchanged.
Logic Block Diagram
Pin Configuration
ZIP
lbpView
(OPEN) POo
NC
Vc;c
010
000
Ao
A2
256Kx 1
256Kx 1
SRAM
I
J
I
256Kx 1
SRAM
I
I
I
256Kxl
SRAM
I
I
I
A4
SRAM
I
I
I
As
0
GNO
011
001
WE
Ag
0 4 - 007
CSL
010 - 013
-
I
-
256Kx 1
SRAM
256Kx 1
SRAM
'--
I
I
I
I
II
I...-
-
256Kx 1
~
SRAM
NC
NC
Vee
01 2
002
Ala
A12
A14
Ala
NC
013
003
NC
NC
GNO
256Kx 1
SRAM
'--
I
I
I
I
I
0
00 - 003
1441-1
GNO
POl (GNO)
NC
014
004
NC
Al
As
As
A7
015
005
Vee
As
NC
CSU
NC
NC
Ola
DOa
GNO
All
A13
A15
A17
017
007
Vc;c
NC
NC
1441·2
Selection Guide
1441-45
1441-25
1441-35
MaximumAccess Time (ns)
25
35
45
Maximum Operating Current (rnA)
960
960
960
Maximum Standby Current (rnA)
320
320
320
9-17
II
U)
LLl
...I
::::)
C
0
==
CYM1460
CYPRESS
SEMICONDUCTOR
512K X 8 Static RAM
Module
Features
Functional Description
• High-density 4-megabit SRAM module
The CYM1460 is a high-performance
4-megabit static RAM module organized as
512K words by 8 bits. This module is constructed from sixteen 32Kx 8 SRAMs in
plastic surface mount packages on an epoxy
laminate board with pins. 1\vo choices of
pins are available forverticaI (PS) or horizontal (PF) through-hole mounting. Onboard decoding selects
one of the sixteen SRAMs from the highorder address lines, keeping the remaining
fifteen devices in standby mode for minimum power consumption.
An active LOW write enable signal (WE)
controls the writing/reading operation of
• Higb-speed CMOS SRAMs
- Access time of35 ns
• Low active power
-3.4W(max.)
• Double-sided SMD technology
• TTL-compatible inputs and outputs
• Low profile version (PF)
- Max. height of .345 in.
• Small footprint SIP version (PS)
- PCB layout area of 1.2 sq. in.
the memory.When MS and WE inputs are
both LOW, data on the eight data
input/output pins is written into the
memory location specified on the address
pins. Reading the device is accomplished
by select~the device and enabling the
.2!!!Puts, MS and OE , active Law, while
WE remains inactive or IDGH. Under
these conditions, the content of the location addressed by the information on the
address pins is present on the eight data
input/outputpins.
The input/output pins remain in a high- impedance state unless the module is
selected, outputs are enabled, and write
enable (WE) is HIGH.
Pin Configuration
Logic Block Diagram
SIP
Ao -A14----~----~;::::==:;-T;::::==::;_T_;::==::;_l
,.__--,
15
33
34
35
36
1460-1
14110·2
SeIecf Ion G UI°de
1460-35
1460 45
1460-55
Maximum Access Time (ns)
35
45
55
70
Maximum Operating Current (rnA)
625
625
625
625
Maximum Standby Current (rnA)
560
560
560
560
9-18
1460-70
~
·~PRESS
.
F
CYM1460
SEMICONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Range
Ambient
Thmperature
Vee
Commercial
O°C to +70°C
5V± 10%
Storage Thmperature . . . . . . . . . . . . . . . . . . .. -65°C to + 150°C
Ambient Temperature with
Power Applied. . . .. . . . . . .. . . . . . . . . . . . . . . ..
O°C to +70°C
Supply Voltage to Ground Potential. . . . . . . .. -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .........................
-0.5V to + 7.0V
DC Input Voltage .......................
-O.5V to +7.0V
Electrical Characteristics Over the Operating Range
CYMl460
Parameters
Description
Thst Conditions
Units
Min.
VoH
Output HIGH Voltage
Vee = Min., I OfF -4.0 rnA
2.4
VoL
Output LOW Voltage
Vee = Min., I OL= 8.0 rnA
0.4
Max.
V
V
\hi
Input HIGH Voltage
2.2
Vi:L
Input LOW Voltage
-0.5
0.8
V
IIX
Input Load Current
GND Vee - 0.2VorVIN < 0.2V
10
10
mA
Capacitance [2]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CoUT
Thst Conditions
TA
Max.
40
30
= 25°C, f = 1 MHz,
= 5.0V
Vee
Notes:
1. VIL(Min.) = -3.0Vfor pulse widths less than 20 ns.
2.
Units
pF
pF
Tested on a sample basis.
AC Test Loads and Waveforms
R1481Q
Rl481Q
5V
5V
OUTPUT
OUTPUT
30
PFI
INCLUDING
JIGAND _
SCOPE (a)
PF I
R2
255Q
5
INCLUDING
JIG AND _
SCOPE (b)
':'
R2
255Q
':'
1464-3
Equivalent to:
THEVENIN EQUIVALENT
167.0.
OUTPUT oo----'·"',v""---oo 1.73V
9-30
aov~10~
GND
.s.5ns--
I-
Jt:::
10%
.s.5 ns
1464-4
~
7 ~~ONDUCTOR
CYM1464
Switching Characteristics Over the Operating Rangef3]
1464-20
Parameters
Description
Min.
Max.
1464-25
Min.
Max.
1464-30
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
20
tDOE
OE LOW to Data Valid
13
tLZOE
OE LOW to Low Z
0
tHzOE
OE HIGH to High Z
0
tLZCS
CS LOW to Low Z
5
tHzCS
CS HIGH to High Z[4]
0
Mite Cycle Time
20
25
tscs
CS LOW to Write End
15
tAW
Address Set-Up to Write End
15
tHA
Address Hold from Write End
tSA
20
5
ns
ns
0
0
ns
0
10
5
15
ns
ns
30
25
0
10
30
25
5
5
ns
30
25
20
0
10
15
0
ns
ns
10
20
ns
WRITE CYCLE
30
ns
20
25
ns
20
25
ns
3
3
3
ns
Address Set-Up from Write Start
5
5
5
ns
tpWE
WE Pulse Width
15
15
20
ns
tSD
Data Set-Up to Mite End
12
15
15
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
ns
tHZWE
WE LOW to High Z[4]
twc
15
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V; input levels of 0 to 3.0V; and output loading of
the specified IOrflOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) ofACTest
Loads. 'fransition is measured ±500 m V from steady state voltage.
5. WE is IDGH for read cycle.
6. Device is continuously selected, CS = VJL.
7. Address valid prior to or coincident with CS transition Ww.
8.
15
15
ns
The internal write time of the memory is defined by the overlap of CS
WW and WE WW. Both signals must beWWto initiateawrite and
9.
9-31
either signal can terminate awrite bygoingHIGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
IfCS goes HIGH simultaneously with WEIDGH, the output remains
in a high-impedance state.
•
&:?~PRFSS
~_
"
CYM1464
SEMICONDUCJ'OR
Switching Characteristics
Over the Operating Rangel3) (continued)
1464-35
Parameters
Description
Min.
Max.
1464-45
Min.
Max.
1464-55
Min.
Max.
1464-70
Min.
Max.
Units
READ CYCLE
35
45
70
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACS
CS LOW to Data Valid
35
45
55
70
ns
tDOE
OE LOW to Data Valid
20
25
30
35
ns
tlZOE
OE WW to LowZ
0
tHZOE
OE HIGH to High Z
0
tucs
CS LOW to Low Z
10
tHZCS
CS IDGH to HighZ[4)
0
35
55
55
45
5
5
5
0
15
0
10
0
20
5
0
15
0
ns
15
10
10
20
0
20
0
ns
ns
0
0
15
ns
70
ns
ns
20
ns
WRITE CYCLE
twc
Write Cycle Time
35
45
55
70
ns
tscs
CS WW to Write End
30
40
50
60
ns
tAW
Address Set-Up to Write End
30
40
50
60
ns
tHA
Address Hold from Write End
3
3
3
3
ns
tSA
Address Set-Up from Write Start
6
5
5
5
ns
tpWE
WE Pulse Width
25
35
40
50
ns
tSD
Data Set-Up to Write End
20
25
35
45
ns
tHD
Data Hold from Write End
2
3
3
3
ns
tLZWE
WE HIGH to Low Z
0
0
0
0
tHZWE
WE WW to High Z[4)
15
15
20
ns
25
ns
Switching Waveforms
Read Cycle No. tl5, 6)
IRC
ADDRESS
)(
~E
1M
---IoHA~
DATA OUT
PREVIOUS DATA VALID
*XX
{
DATA VALID
1464-5
9-32
~
~~PRF.SS
~_.~ SEMICONDUCTOR
CYM1464
Switching Waveforms
Read Cycle No. 2[5,7]
CS
IRe
~"
lACS
/1{
"
IOOE
- - ILZOE-HIGH IMPEDANCE
DATA OUT
Vee
SUPPLY
CURRENT
I--
?
Ipu
S'
I-///
IHZOE IHZCS -
,
DATA VALID
I,""
HIGH
IMPEDANCE
/
-
Ipo----.t
50%
ICC
50%C
IS8
1464-6
Write Cycle No.1 (WE Controlled)[8]
Iwe
ADDRESS
~(
~~ ~
)K
Ises
"
/
•
IHA-
lSA
IPWE
~~~
i~
IHO ...
Iso
)(
DATA IN
~
DATA VALID
I-DATA OUT
W'~ ~
lAW
DATA UNDEFINED
~
IHZWE
ILZWE;t
HIGH IMPEDANCE
V
~
/I
1464-7
Write Cycle No.2 (CS Controlled) [8,9]
ADDRESS
------<....---
14-+---
Iscs
Iso --~~...
DATA IN
I HZWE
=-!
DATA OUT _ _ _ _ _ _ _
D_AT_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _--'~ HIGH IMPEDANCE
1464-8
9-33
~
.'~UCIDR
CYM1464
Truth Table
CS
WE
OE
Inputs/Outputs
H
X
X
HighZ
L
H
L
Data Out
Read Word
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
Mode
Deselect/fuwer-Down
Ordering Information
Speed
(ns)
20
25
30
35
45
55
70
Package
1YPe
Operating
Range
CYMl464PD-20C
PD02
Commercial
CYMl464PD-25C
PD02
Commercial
CYMl464PD-30C
PD02
Commercial
CYMl464PD-35C
PD02
Commercial
CYMl464PD-45C
PD02
Commercial
CYM1464PD-55C
PD02
Commercial
CYMl464PD-70C
PD02
Commercial
Ordering Code
Document#: 38-M-00030-B
9-34
CYM1465
CYPRESS
SEMICONDUCTOR
512K X 8 SRAM Module
Features
Functional Description
• High-density4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 70 ns
The CYM1465 is a high-performance
4-megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 128K x 8 RAMs
mounted on asubstratewith pins.Adecoder is used to interpret the higher-order addresses(A17 and AIS) and to select one of
the four RAMs. Twopackagingoptionsare
offered: VSOP packages on FR4 substrate
(PD), and SOIC packages on ceramic substrate (SD).
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both WW Data on the
• Low active power
- 605 mW (DlIlX-)
•
•
•
•
JEDEC-compatiblepinout
32-pin, 0_6-inch-wide DIP package
TTL-compatible inputs and outputs
Low profile
- Max. height of .27 inches
• Small PCB footprint
- 0.98 sq. in.
eight input/output pins (1/00 through
110;) of the device is written into the
memory location specified on the address
pins (Ao through AIS). Reading the device
is accomplishe~ taking chip select and
output enable(OE) WW while write enable remains inactive or HIGH. Under
these conditions, the contents of the
memory location specified on the address
pins (Ao through AlB) will appear on ~e
eight appropriate data input/output pms
(1100 through 1/07).
Theinput/outputpinsremaininahigh-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Pin Configuration
Logic Block Diagram
DIP
Top View
Ao - A 1 6 - - - - - - - - - r - - - - - - - - ,
Vee
A18
A16
A14
A12
A7
WE--------------.t---------,
OE------------,rrt--------,
A15
A17
WE
A13
As
As
AI;)
A11
As
~
m:
Aa
A10
A2
A1
A17
A18
Ao
CS
V07
V01
V02
1/°6
1/05
1/04
GND
V03
VOo
10f4
Decoder
1465-2
VO o - Va,
1465-1
Sit·
e ec Ion GUl·de
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
1465-70
70
110
1465-85
85
110
1465-100
100
110
1465-120
120
1465-150
150
110
110
12
12
12
12
12
9-35
II
en
LLI
...I
:::)
Q
0
::E
CYM1465
Operating Range
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Thmperature ..•.... _....... _. - SSoC to +l2S°C
Ambient Thmperature with
Power Applied ........................ -10°C to +8S°C
Supply Voltage to Ground Potential ........ -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State ...••.............•...... -O.sV to + 7.0V
DC Input Voltage .•.....•.......•....••. -O.sV to +7.0V
Range
Commercial
Industrial
Ambient
Temperature
O°Cto + 70°C
Vee
SV:!: 10%
- 40°C to + SSoC
SV:!: 10%
Electrical Characteristics Over the Operating Range
1465
Parameters
Description
Output mGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Vee
Vee
Ioz
lee
Output Leakage Current
Vee Operating Supply
Current
ISBI
Automatic
Current
ISB2
Automatic CS Power-Down
Current
VOR
VOL
VIR
VIL
IIX
Min.
Test Conditions
CS Power-Down
= Min., lOR = - 1.0 mA
= Min., IOL = 2.1 mA
Max.
Units
0.4
V
V
2.4
GND~VI~VCC
2.2
-0.3
-10
Vee +0.3
O.S
+10
GND S Vo S Vee, Output Disabled
-20
+20
110
mA
12
mA
S
420
mA
= Max., lour = 0 mA,
S VIL
Vee = Max., CS2 VIR
Min. Duty Cycle = 100%
~
Vee = Max., CS 2 Vee - 0.2V,\ Standard Version
VIN2 Vee-0.2VorVlNSO.2VI L Version
V
V
J.IA
J.IA
J.IA
Capacitance!l]
Parameters
Description
Input Capacitance
Output Capacitance
CIN
Cour
Test Conditions
TA = 2S°C, f
Vee = S.OV
= 1 MHz,
Max.
4S
4S
Units
pF
pF
AC Test Loads and Waveforms
1.847kC
1.847kC
OUTP:~
,~,.,~
INCLUDING
JIG AND
SCOPE
Equivalent to:
1
J
OUTP:~
_
CL[21 11k C
-
-
(a)
1
,,~, ~ J
_
5PF 1
..
INCLUDING
JIG AND
SCOPE
(b)
3.0V----
1kC
1466-3
I
ALL INPUT PULSES
90%
GND---'1
oS. 10 ns
1466-4
THEVENIN EQUIVALENT
OUTPUT 0
~.o.
01.76V
Notes:
1. Thsted on a sample basis.
2. Thst conditions assume signal transition times of 10 ns or less, timing
reference levels of loS¥, input levels of 0 to 3.0¥, and output loading of
9-36
the specified IOrJIOH and l00-pF load capacitance for 85, 100, 120,
and 150 ns speeds. CL = 30 pF for 70 ns speed.
-==-r...
liJjl~
CYM1465
Switching Characteristics Over the Operating Range[2]
1465-70
Parameters
Description
1465-85
1465-100
1465-120
1465-150
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
taHA
Data Hold from Address Change
tACS
'CS'LOW to Data Valid
70
85
100
120
150
ns
tOOE
DE LOW to Data Valid
DE LOW to Low Z
DE HIGH to High Z[3]
35
45
50
60
75
ns
tLZOE
tHZOE
trzes
tHZCS
CS LOW to Low Z
CS HIGH to High Z[3]
70
85
10
10
5
2S
30
30
10
35
10
30
45
ns
55
10
45
ns
ns
5
10
35
ns
150
10
5
5
10
150
120
100
10
5
10
120
100
8S
70
ns
ns
60
ns
WRITE CYCLE
twc
Write Cycle Time
70
85
100
120
150
ns
tscs
CS LOW to Write End
65
75
90
100
115
ns
tAW
Address Set-Up to Write End
65
75
90
100
110
ns
tHA
Address Hold from Write End
0
5
5
5
5
ns
tSA
Address Set-Up from Write Start
0
5
5
5
5
ns
tpWE
WE Pulse Width
55
65
75
85
95
ns
tSD
Data Set-Up to Write End
30
35
40
45
50
ns
tHO
Data Hold from Write End
0
0
0
0
0
ns
II
trzWE
WI! HIGH to Low Z
WI! LOW to High Z[3]
5
5
5
5
5
ns
UJ
tHZWE
U)
25
30
40
35
45
ns
..J
::::)
C
o
:iE
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial
Parameters
Description
'lest Conditions
VDR
Vee for Retention Data
CS~ Vee - 0.2V
ICCDR3
Data Retention Current
tCDR[4]
Chip Deselect to Data Retention Time
Vee = Max., 'CS'~ Vcc - 0.2V,
VIN~ Vee-0.2VorVIN,S,O.2V
tR[4]
Operation Recovety Time
Industrial
Min.
Max. Min. Max.
Units
2.0
20
V
50
150
flA
0
0
ns
5
5
IDS
Notes:
3.
4.
S.
6.
7.
CL = 5 pF as in part (b) of AC Thst Loads. 11-ansition is measured
±SOO mV from steady state voltage.
Guaranteed, not tested.
WE is HIGH for the read cycle.
Device is continuously selected, "CS" = VIL.
Address valid prior to or coincident with"CS" transition LOW.
8.
9.
9-37
The internal write time of the memory is defined by the overlap ofCS"
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate a write by going mOH. The data input setup and hold timing should be referenced to the risingedge ofthe signal
that terminates the write.
If"CS" goes mOHsimultaneouslywith WEmOH, the outputremians
in a high-impedance state.
~
~Ts~CCWUCIOR
CYM1465
Data Retention Waveform
DATA RETENTION MODE
Vee
4.
VOR
1466-5
Switching Waveforms
Read Cycle No 1 [5,6]
lOR
~r
ADDRESS
)
I - - toHA
DATA OUT
~
1M
--=-!
PREVIOUS DATA VALID
*XX~ (
DATA VALID
1455-6
Read Cycle No. 2 15,7]
1Re
-.....'\..
~~
lACS
~
~
-~
tooE
~tuOE-
HIGH IMPEDANCE
DATA OUT
tues
'///
tHZes
DATA VALID
.'- '-'-
HIGH
IMPEDANC E
/
1465-7
Write Cycle No.1 (WE Controlled) [8]
!we
ADDRESS
=:) r
~(
tscs
~~ ~,
/W////~ ~
lSA
lAw
~~
~I"
Iso
DATA IN
)
IHA-
tPWE
(
DATA-IN VALID
I--ItiZWE
j
tHO ..
j
r- tuwE-I
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _D_A_:rA_U_N_D_E_FI_NE_D_ _ _ _ _ _-J»-------~(""_
____
1455-8
9-38
CYM1465
Switching Waveforms (continued)[8.9j
Write Cycle No.2 (CS Controlled)
__~========~~======~r----t~
~+--- tSD - -....1--<101
,-----------
----------------------~
tHZWE~
_____________
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _ _
DATA UNDEFINED
_ 1465-9
Truth Table
Inputs
CS
WE
OE
H
L
X
X
H
L
H
L
L
Outputs
Mode
X
HigbZ
Data Out
Data In
DeselectlPower-Down
Read Word
Write Word
H
HigbZ
Deselect
L
U)
Ordering Information
Speed
(ns)
70
Ordering Code
CYMl465PD-70C
CYMl465LPO-7OC
CYMl465SD-70C
Package
1)pe
POO3
Operating
Range
Speed
(ns)
Commercial
100
Sool
120
CYMl465LSD-70C
85
CYMl465PD-85C
PD03
CYMl465LPD-85C
CYM1465SD-85C
CYM1465LSD-85C
S001
CYM1465PD-85I
PD03
Commercial
100
CYM1465LPD-1ooC
CYM1465SD-1ooC
CYM1465LSD-100C
CYM1465PD-10OI
Operating
Range
CYM1465SD-1ooI
CYM1465LSO-1ooI
CYM1465PD-120C
SD01
Industrial
PD03
Commercial
CYM1465LPD-12OC
CYM1465SD-12OC
SD01
CYM1465LSD-120C
CYM1465PD-12OI
P003
Industrial
CYM1465SD-12OI
Iudustrial
SD01
CYM1465LSD-120I
SD01
PD03
150
Commercial
SD01
PD03
CYM1465PD-150C
CYM1465LPD-150C
CYM1465SD-l50C
SD01
CYM1465LSD-150C
CYM1465PD-150I
PD03
CYMl465LPD-l5OI
CYMl465SD-l5OI
CYM1465LSO-15OI
Industrial
CYM1465LPD-1ooI
Document #: 38-M-00036-B
9-39
LLI
...J
:;)
C
o
:::E
CYM1465LPD-12OI
CYM1465LPD-85I
CYM1465SD-85I
CYM1465LSD-85I
CYM1465PD-looC
Ordering Code
Package
1)pe
Poo3
SD01
Commercial
Industrial
CYM1466
PRELIMINARY
CYPRESS
SEMICONDUCTOR
512K X 8 SRAM Module
Features
Functional Description
• High-density4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 30 ns
The CYM1466 is a high-performance
4-megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 128K x 8 RAMs in
ceramic leadless chip carrier packages
mounted on a ceramic substrate. A decoder is used to interpret the higher-order addresses (A17 and A18) and to select one of
the four RAMs.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
eight input/output pins (1/00 through 1/0?)
of the device is written into the memory
• Low active power
-1.9W (max.)
• JEDEC-compatiblepinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
location specified on the address pins (Ao
through A 18). Reading the device is accomplished.EY.taking chip select and output enable(OE) LOW while write enable
remains inactive or HIGH. Under these
conditions, the contents of the memory location specified on the address pins (Ao
through A18) will appear on the eight appropriate data input/output pins (1/0)0
through 1/07)'
Theinput/output pins remain in ahigh-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Pin Configuration
Logic Block Diagram
1.0 -
DIP
Top View
A16----------r-------.
WE---------------~~--------..,
OE--------------T4-r------~
10f4
Decoder
~====--t====~~LJ-,/OO -1i0r
1466-2
1466-1
Selection Guide
Maximum Access Time (ns)
1466-30
1466-35
1466-45
1466-55
1466-70
1466-85
30
35
45
55
70
85
1466-100 1466-120
100
120
MaximumOperatingCurrent(mA)
I Mil
250
250
250
250
250
110
110
110
MaximumStandbyCurrent(mA)
I
120
120
120
120
120
15
15
15
Mil
9-40
~
~~
~~CYPRESS
""'Sf!!!!!IIf'
CYM1466
PRELIMINARY
SEMlCONDUClDR
Maximum Ratings
(Above which the useful life may be impaired.)
Operating Range
Ambient
'lemperature
- 55°C to + 125°C
Range
Military
Storage Thmperature ................. - 65 ° C to + 125 ° C
Supply Voltage to Ground Potential ......... -O.3V to +7.0V
DC Voltage Applied to Outputs
in High Z State .............................. OV to Vee
DC Input Voltage ................... -O.3V to Vee +O.3V
Vee
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameters
VOH
Description
Output HIGH Voltage
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
VIL
IJX
Input LOW Voltage
Input Load Current
loz
Output Leakage
Current
Vee Operating
Supply Current
AutomaticCS
Power-Down Current
AutomaticCS
Power-Down Current
lee
ISBl
ISB2
'lest Conditions
10H = - 4.0 rnA
10H = -1.0rnA
Vee = Min.
10L= 8.0 rnA
IOL=2.0rnA
Vee = Min.
1466-30
1466-35
1466-45
1466-55
1466-70
Min.
Max.
2.4
Units
V
2.4
0.4
2.2
Vee = Max., 0:::;; VI:::;; Vee
CS = Vrn, Vee = Max.,
O.$. Vo.$. Vee
Ycc - Max., 10 - 0 rnA,
CS < VIL
Vee = Max., CS ~ Vrn,
10 = ornA
Vee = Max., CS ~ Vee - 0.2Y,
Vee - 0.2V < VI < 0.2Y, 10 = 0 rnA
1466-85
1466-100
1466-120
Max.
Min.
-0.5
-10
-20
V
0.4
Vee
+0.3
0.8
+10
+20
f.tA
f.tA
250
110
rnA
120
15
rnA
40
10
rnA
Vee
+0.3
0.8
+10
+20
2.2
-0.5
-10
-20
V
V
•
( /)
UJ
...I
::::)
Q
o
::&
Capacitance[l]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CoUT
'lest Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
45
45
Units
pF
pF
Note.:
1.
Thsted on a sample basis.
AC Test Loads and Waveforms
5V
OUTPUT
TI
R1
C1
INCLUDING
JIG AND
SCOPE
J
-
(a)
R1
5pF
INCWDING
JIG AND
SCOPE
J
-
(b)
_
ALL INPUT PULSES
90%
OUTPUT
R2
_
-
5V3=t
3.0V---R2
GND---Ji
.5. 10 ns
-
1466-3
9-41
1466-4
-=--.
~::z
~=CYPRESS
. . . . . .,
CYM1466
PRELIMINARY
SEMICONDUCI'OR
Load Capacitor and Resistor Values
1466-30
1466·35
14(i(i..45
14(i(i..55
Cl
Rl
1466·70
30
0.481
R2
0.255
Switching Characteristics
1466.85
1466·100
1466·120
Units
100
1.84
pF
1.00
ill
kQ
Over the Operating Range[2]
1466·30
Parameters
Description
Min.
Max.
1466·35
Min.
Max.
1466·45
Min.
Max.
1466·55
Min.
Max.
1466·70
Min.
Max. Units
READ CYCLE
35
45
55
70
tRC
Read Cycle Time
tAA
Address to Data Valid
taHA
Data Hold from AddressChange
tACS
CS WW to Data Valid
30
35
45
55
70
ns
tDOE
OE WW to Data Valid
10
15
20
30
35
ns
tLZOE
OEWWtoLowZ
tHZOE
OE HlGH to High Z[3]
tLZCS
CS LOW to Low Z
30
30
5
35
5
0
5
CS HlGH to High zI3]
tHZCS
WRITE CYCLE
5
0
10
45
5
10
5
0
15
55
5
5
ns
30
ns
ns
5
25
ns
ns
0
25
20
15
5
0
20
ns
70
30
ns
twc
Write Cycle Time
30
35
45
55
70
ns
tscs
CS WW to Write End
26
26
30
45
50
ns
tAW
Address Set·Up to Write End
26
26
30
45
50
ns
tRA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up from Write Start
5
5
5
5
5
ns
tpWE
WE Pulse Width
18
20
25
35
45
ns
tSD
Data Set-Up to Write End
12
16
20
25
30
ns
tHO
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HlGH to Low Z
0
0
0
5
5
tHZWE
WE WW to High zI3]
0
10
0
9-42
15
0
15
0
15
0
ns
15
ns
·~PRFSS
Switching Characteristics
Over the Operating Rangel.4] (continued)
1466-85
Parameters
CYM1466
PRELIMINARY
·- , SEMICONDUCTOR
Description
Min.
1466-100
Max.
Min.
1466-120
Max.
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
85
100
120
taHA
tACS
Data Hold from AddressChange
c:s LOW to Data Valid
85
100
120
ns
tOOE
OE LOW to Data Valid
40
50
60
ns
tLZOE
0
tHZOE
OE LOW to Low Z
OE HIGH to High z[5]
45
ns
tLZCS
CS LOW to Low Z
5
tHZCS
CS HIGH to High Z[3]
45
ns
85
5
ns
100
5
120
5
5
5
35
ns
35
5
5
35
ns
ns
ns
35
WRITE CYCLE
twc
Write Cycle Time
85
100
120
ns
tscs
c:s LOW to Write End
55
90
100
ns
tAW
Address Set-Up to Write End
55
90
100
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up from Write Start
5
5
5
ns
tpWE
WE Pulse Width
55
75
85
ns
tso
Data Set-Up to Write End
35
40
45
ns
tHO
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z
WE LOW to High z[3]
5
5
5
tHZWE
Data Retention Characteristics
0
15
0
35
40
ns
(L Version Only)
Description
3.
4.
5.
6.
en
::)
Thst Conditions
VOR
V cc for Retention Data
CS~ Vcc
ICCOR
tcoR[4]
Data RetentionCurrent
VOR= 3.0V
tR[4]
Operation Recovery Time
Chip Deselect to Data Retention Time
- 0.2V
Min.
Max.
2.0
Q
o
:::&
1466-85
1466-100
1466-120
Min.
Max.
Units
1000
!JA
2.0
6000
V
0
0
ns
tRC
tRC
ns
Notes:
2.
•
LLI
...I
1466-30
1466-35
1466-45
1466-55
1466-70
Parameters
ns
0
Thst conditions assume signal transition times of 10 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V, and outputloading of
the specified IOr/IOH and load capacitance.
CL = 5 pF as in part (b) ofACThstLoads. 1tansitionismeasured ±500
m V from steady state voltage.
Guaranteed, not tested.
WE is HIGH for the read cycle.
Device is continuously selected, cs = VILo
7.
8.
9.
9-43
Address valid prior to or coincident with CS transition LOW.
The internal write time of the memoty is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate awriteand
either signal can terminate a write by going HIGH. The data input setup and hold timingshouIdbe referenced to tbe rising edge ofthe signal
that terminates the write.
IfCSgoesHIGHsimultaneouslywith WEIDGH, theoutputremians
in a high-impedance state.
'&:~PRFSS
CYM1466
PRELIMINARY
~_., SEMICONDUCTOR
:J:
:i:-:v:, ~V," ~f"-----V..;O..;:o-:-2-V------"~:.~
Data Retention Waveform
DATA RETENTION MODE
1466-5
Switching Waveforms
Read Cycle No. 1[5,6]
IRC
~(
~~
ADDRESS
1M
-
DATA OUT
!aHA
--=-..j
PREVIOUS DATA VALID
*XX~ ~
DATA VALID
1466-6
Read Cycle No. 2[5,7]
es
IRC
~~
~~
lACS
~~
/
I+DATA OUT
1o0E
ILZOE-
I--
HIGH IMPEDANCE
1/////
ILZCS
"""""
DATA VALID
-~
IHZCS
HIGH
IMPEDANCE
/
1466-7
Write Cycle No.1 (WE Controlled)[8]
lwe
ADDRESS
=:)(
IscS
~~ ~,
/
W/////h W///m
lAW
IHA-
!sA
IPWE
~
/
Iso
DATA IN
~~
IHO --
)(
DATA-IN VALID
~ IHZWE
j
-
IlZWE
---j
HIGH IMPEDANCE
DATAOUT _ _ _ _ _ _ _D_AT_A_U_N_D_EF_IN_E_D_ _ _ _ _ _--J)~-------~<~
____
1466-8
9-44
~~PRESS
~, SEMICONDUCTOR
PRELIMINARY
CYM1466
Switching Waveforms (continuedj8,9]
Write Cycle No.2 (CS Controlled)
ADDRESS
- - - - -.....- - - Iscs
~-+---- tso - - -.....-.1
DATA IN
I HZWE
:1
..)I HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _D_A_I_A_U_N_D_E_FI_N_E_D_ _ _ _ _ _ _ _ _
1466-9
Truth Table
Inputs
CS
WE
OE
H
X
X
HighZ
DeselectlIbwer-Down
L
H
L
Data Out
Read Word
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
Outputs
Mode
•
U)
LLI
..J
~
C
o
::::IE
9-45
UT,~u~
PRELIMINARY
Ordering Information
Speed
(ns)
30
35
45
55
70
85
100
120
Ordering Code
Package
'JYpe
CYMl466HD-30M
HD12
CYM1466UID-30M
HD12
CYMl466HD-30MB
HD12
CYM1466LHD-30MB
HD12
CYMI466HD-35M
HD12
CYM1466LHD-35M
HD12
CYM1466HD-35MB
HD12
CYM1466LHD-35MB
HD12
CYM1466HD-45M
HD12
CYM1466LHD-45M
HD12
CYM1466HD-45MB
HD12
CYM1466LHD-45MB
HD12
CYMI466HD-55M
HD12
CYM1466LHD-55M
HD12
CYMl466HD-55MB
HD12
CYMI466LHD-55MB
HD12
CYM1466HD-70M
HD12
CYMI466LHD-70M
HD12
CYM1466HD-70MB
HD12
CYMl466LHD-70MB
HD12
CYM1466HD-85M
HD12
CYMl466UID-85M
HD12
CYMI466HD-85MB
HD12
CYM1466UID-85MB
HD12
CYM1466HD-I00M
HD12
CYM1466LHD-100M
HD12
CYM1466HD-lOOMB
HD12
CYM1466UID-lOOMB
HD12
CYM1466HD-120M
HD12
CYM1466UID-120M
HD12
CYM1466HD-I20MB
HD12
CYM1466LHD-120MB
HD12
Operating
Range
Military
Military
Military
Military
Military
Military
Military
Military
Document#: 38-M-00044-A
9-46
CYM1466
CYM1471
CYM1481
CYPRESS
SEMICONDUCTOR
l024Kx 8 SRAM Module
2048K x 8 SRAM Module
Features
Functional Description
• High-density 8-/16-megabit SRAM
modules
• High-speed CMOS SRAMs
- Access time of 85 ns
The CYMI471 and CYM1481 are highperformance 8-megabit and 16-megabit
static RAM modules organized as 1024K
words (1471) or 2048K words (1481) by 8
bits. These modules are constructed from
eight (1471) or sixteen (1481) 128K x 8
SRAMsin plastic surface-mount packages
on an epoxy laminate board with pins. Two
choices of pins are available for vertical
(PS) or horizontal (PF) through-hole
mounting. On-board decoding selects one
of the SRAMsfrom the high-order address
lines, keeping the remaining devices in
standby mode for minimum power consumption.
• Low active power
- 605 mW (max.), 2M x 8
• Double-sided SMD technology
• TIL-compatible inputs and outputs
• Very low profile version (PF)
- Max. height of 0.205 in.
• Small footprint SIP version (PS)
- PCB layout area of 0.72 sq. in.
• 2V data retention (L version)
• Compatible with CYM1460/CYMl461
the memory. When MS and WE inputs are
botb LOW, data on tbe eight data input/
output pins is written into the memory location specified on the address pins. Reading tbe device is accomplished by select.!!!&
the device and enabling the outputs, MS
and OE active LOW, while WE remains inactive or HIGH. Under these conditions,
tbe content of the location addressed by
the information on tbe address pins is present on the eight data input/output pins.
Tbe input/output pins remain in ahigh-impedance state unless tbe module is selected, outputs are enabled, and write enable (WE) is HIGH.
An active LOW write enable signal (WE)
controls tbe writing/reading operation of
Logic Block Diagram
Pin Configuration
SIP
~--------------------------------,
I Ao-~6
I
I
I
OE
I
I WE
11A.,7-~
I
I
I
I
MS
I
I
I
I
I
I
I
17
A19
ro;
Vee
~!
I-CYM1471
I
I
I
I
I
A3
A4
GND
1/0 5
A10
A11
A5
A13
~A20(1481)~
1...___
NC(1471)
~
A15
A 16
A12
A18
A6
1/01
i~~~~~~~~~~~~l;~~~!::r::::~Jl~.<
8
•
1/03
1/00
1/00- 1/07
GND
28
Ao
27
A7
A8
28
29
1/0 7
1/0 4
1/0 6
30
31
32
33
34
35
A9
A17
Vee
OE
1471-1
( J)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LLl
...J
::l
C
0
::::i
36
Selection Guide
CYM1471
CYMl481
Maximum Access Time (ns)
85
100
120
85
100
120
Maximum Operating Current (rnA)
95
95
95
110
110
110
Maximum Standby Current (rnA)
16
16
16
32
32
32
9-47
CYM1471
CYM1481
V!cmFSS
d£
--::::iii'"
SE:MICCWUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Storage 'Thmperature ................. - 55· C to +125· C
Ambient 'Thmperature with
Power Applied •...•....•................ O·C to +70·C
Supply Voltage to Ground Potential. . . . . .. - 0.3V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.3V to + 7.0V
DC Input Voltage • . . • . . . . . . . . . . . . . . . . .. - 0.3V to + 7.0V
Output Current into Outputs (LOW) ••.••••.....•. 20 rnA
Ambient
Temperature
Range
Commercial
Vee
5V± 10%
O·Cto + 70·C
Electrical Characteristics Over the Operating Range
1471
Parameter
Description
Test Conditions
Min.
VOH
Output mGH Voltage
Vee = Min., IOH = -1.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 20 mA
VIH
Input mGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
1481
Max.
Min.
2.4
Max.
0.4
2.0
Vee + 0.3
2.2
Units
V
2.4
0.4
V
Vee +0.3
V
- 0.3
0.8
- 0.3
0.8
V
GND.s. VI.s. Vee
-20
+20
-20
+20
-20
+20
-20
+20
!JA
!JA
95
110
rnA
16
32
rnA
-I Standard
16
32
rnA
I L Version
250
500
!JA
Units
75
CYM1481
Max.
125
25
25
95
165
pF
pF
loz
Output Leakage Current
GND .s. VI.s. Vee, Output Disabled
lee
Vee Operating
Supply Current
Vee = Max., m.s. VIL
lOUT = ornA
ISBI
Automatic lVIS
Power-Down Current
Min. Duty Cycle = 100%
ISB2
Automatic lVIS
Power-Down Current
Max. Vee. m
~ VIH,
Max. Vee, m ~ Vee
0.2Y, VIN ~ Vee - 0.2Y,
or VIN.s. 0.2V
Capacitance[l]
Parameter
Description
Test Conditions
CINA
qNB
Input Capacitance (Ao-16, OE, WE)
Input Capacitance (AI7-20, M-s)
COUT
Output Capacitance
CYM1471
Max.
TA = 25·C, f = 1 MHz,
Vee =5.0V
pF
Notes:
1. Thsted on a sample basis.
AC Test Loads and Waveforms
sv_--....._.,
RI2530,n
RI253D,n
5V_----'_~
OUTPUT--_P_-,.
1DDPFI
R2
R2
28300.
5pF
2830n
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
ALL INPUT PULSES
OUTPUT-----;p---t
INCLUDING
JlGAND _
SCOPE -
(a)
THEvENIN EQUIVALENT
(b)
1471-3
134o.Cl.
OUTPUT 0_ _--"\I\o.'\''''"---o02.84V
9-48
:~~cOO%
~M
1471-4
CYM1471
CYM1481
=:r.~~
Switching Characteristics Over the Operating Range[2]
1471-85
1481-85
Parameter
Description
Min.
1471-120
1481-120
1471-100
1481-100
Max.
Max.
Min.
Min.
Max.
Units
120
ns
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
85
100
toliA
Data Hold from Address Change
tAMS
MS LOW to Data Valid
85
100
120
tOOE
45
50
60
5
tHZOE
DE LOW to Data Valid
DE LOW to Low Z
DE mGH to High Z[3]
tLZMS
MS LOW to Low Z[4]
10
tHZMS
MSmGH to High z[3,4]
tLZOE
10
ns
120
100
85
10
10
ns
ns
ns
5
5
35
30
45
ns
45
ns
ns
10
10
30
35
WRITE CYCLE[S]
twe
Write Cycle Time
85
100
120
ns
tsMS
MS LOW to Write End
75
90
100
ns
tAW
Address Set-Up to Write End
75
90
100
ns
tliA
Address Hold from Write End
7
7
7
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
tpWE
WE Pulse Width
65
75
85
ns
tso
Data Set-Up to Write End
35
40
45
ns
tHO
Data Hold from Write End
5
5
5
ns
tHZWE
WE LOW to High Z[3]
tLZWE
WE mGH to Low Z
30
5
40
35
5
ns
ns
5
II
(f)
UJ
..J
::l
C
o
:::E
Data Characteristics (L Version only)
1471-85
Parameter
Description
VOR
V cc for Retention Data
ICCDR
Data Retention Current
tcoR[6]
Chip DeSelect to Data
Retention Time
tR[7]
Operation Recovery Time
Test Conditions
Min.
~=3.0Y,
Max.
2.0
~ Vee -0.2Y,
VIN~ Vcc-0.2Y,
1471-100
1471-120
Min. Max. Min.
2.0
400
orVIN.:;;.0.2V
Notes:
2. '!Cst conditions assume signal transition times of 10 "" or less, timing
reference levels of 1.sv, input levels of 0 to 3.0V, output loading of 1
TTI..load, and 100-pF load capacitance.
3. tHZOEo tHZMs. and tHZWE are specified with Q = S pF as in part 9b)
of AC '!Cst Loads. 'fransition is measured ±500 mV from steady state
voltage.
4. At any given temperature and voltage condition, tHZMS is less than
tLZMs for any given device. These parameters are guaranteed and not
100% tested.
1481-85
Max. Min. Max. Units
2.0
125
1481-100
1481-120
2.0
V
250
800
I£A
0
0
0
0
ns
5
5
5
5
ns
5.
6.
7.
9-49
The internal write time ofthe memory is deImed by the overlap ofMS
LOW andWE LOW, Both signals must be LOW to initiate awriteand
either signal can terminate a write by going IDOH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
Guaranteed. not tested.
tRe = Read Cycle TIme.
CYM1471
CYM1481
Data Retention Waveform
DATA RETENTION MODE
4.
1471-5
Switching Waveforms
*_
Read Cycle No. 1[8,9]
ADDRESS~§_==_tRC
4 - t~M.1
_ _
tOHA---.,
DATA OUT
======================011=:1:=111l=0\u==0===============
PREVIOUS OATAVALID
1471-6
Read Cycle No. 2[9, 10]
~
tRc
-:'
It'
tAMS
...,~
...l~
I---
tDOE
tLZOE
DATA OUT
tHZOEtHZMS
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
I---
t lZMS -
Notes:
8. Device is continuously selected. OE, MS = VIL.
9. Address valid prior to or coincident with MS transition LOW.
1471-7
10. Wi! is mOR for read cycle.
9-50
=<#"
CYM1471
CYM1481
~~PRF$
_ , SEMICOIDUCTOR
Switching Waveforms (continued)
Write Cycle No. tis, 11]
ADDRESS
-
IWC
-H-
-H'
Isus
\.\.\ .\.\.\.'T
~
~////,
lAW
-I
tSA
tPWE
~\. \...::! ir-
1
DATA IN
"":l
F-
I
.1
tSD
'*
DATA-IN VAUD
tHO
-l If
'I
DATA 1/0
'/////////
t HA -
-------------------------------------------;!I-__
~H~IG~H~IM~P=EDA~N~~ --:t__«~-------::)I---k
I--
~ t HZWE
tLZWE
__
DATA UNDEFINED
1471-8
Write Cycle No. 2[5, 11, 12]
ADDRESS
-
IWC
-'!f-
-'!ftSA
ISMS
~
..., ~
tHA
tPWE
'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.\.\.'\.'\.'\.'\.'\.\.~.
DATA IN
'*
/ / / / / / / / / / / /
~
:E
'*
HIGH IMPEDANCE
DATA UNDEFINED
1471-9
Truth Table
WE
OE
H
X
X
HighZ
DeselectlPower-Down
L
H
L
Data Out
Read
MS
Input/Outputs
Mode
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Notes:
11. Data I/O is high impedance ifOE
= VIH.
12.
If:fJS goes HIGHsimultaneouslywith WJ!HIGH, the output remains
in a high-impedance state.
9-51
~
o
'I
tHZWE
.....I
Q
tHO
DATA-IN VAUD
1
DATA 1/0
U.I
-: ~/ /
tSD
.1
•
C/)
lAW
CYM1471
CYM1481
CYM1471 Ordering Infonnation
Speed
(ns)
85
Ordering Code
CYM1471PF-85C
CYM1481 Ordering Infonnation
Package
1)'pe
Operating
Range
Speed
(ns)
PF05
Commercial
85
CYM1471LPF-85C
CYM1471PS-85C
CYM1471PF-100C
CYM1481PS-85C
PSOS
PF05
Commercial
100
CYM1471PF-120C
CYM1481PF-100C
CYM1481PS-lOOC
PSOS
Commercial
PS06
PF04
Commercial
PS06
CYM1481LPS-100C
PF05
Commercial
120
CYMl481PF-120C
PF04
CYM1481LPF-12OC
CYM1471LPF-120C
CYM1471PS-120C
PF04
CYMl481LPF-100c
CYM1471LPS-100C
120
Operating
Range
CYM1481LPS-85C
CYM1471LPF-100C
CYM1471PS-100C
CYMl481PF-85C
Package
1)'pe
CYM1481LPF-85C
CYM1471LPS-85C
100
Ordering Code
CYM1481PS-120C
PS08
CYM1481LPS-120C
CYM1471LPS-120C
Document #: 38-M-00041
9-52
PS06
Commercial
CYM1540
CYPRESS
SEMICONDUCTOR
Features
• High-density 2-megabit SRAM module
with parity
• High-speed CMOS SRAMs
- Access time of 30 ns
• Buffered address and control inputs
• Low active power
-6.2W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .52 in.
256K X 9 Buffered SRAM
Module with Separate I/O
• Small PCB footprint
-1.6 sq. in.
Functional Description
The CYM1540 is a vel)' high performance
2-megabit static RAM module organized as
256K words by 9 bits. This module is constructed using nine 256Kx 1 static RAMs in
SO] packages mounted on an epoxy laminate board with pins. Input buffers are provided on the address and control lines to
reduce input capacitance and loading.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
data input pins (DIo through Dig) of the
device is written into the memol)' location
specified on the address pins (Ao through
Al7). Reading the device is accomplished
by taking chip select (CS) LOW, while
write enable (WE) remains inactive or
maH. Under these conditions, the contents of the memol)' location specified on
the address pins (Ao through Al7) will appear on the appropriate data output pins
(000 through DOS).
The data output pins remain in a highimpedance state when chip select (CS) is
maH or when write enable (WE) is LOW.
Logic Block Diagram
Pin Configuration
SIP
Ao - AI7
-'-D----.-------..-------,
WE
cs---D-.H--------n~------,
•
en
LLI
...I
:»
o
o
==
01 0 - Ole
-~----IL.---.L...--t=~====:t=~==~~.L_L 00 0 -
O~
1540-1
1540-2
Selection Guide
1540-30
1540-35
30
35
45
Maximum Operating Current (rnA)
1125
1125
1125
Maximum Standby Current (rnA)
350
350
350
Maximum Access Time (ns)
9-53
1540-45
CYM1540
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Range
Ambient
'Thmperature
Vee
Commercial
0·Cto+70·C
5V± 10%
Storage'Thmperature ................... -45·C to + 125·C
Ambient 'Thmperature with
Power Applied ••••••••..•...•••....•.• -lO·C to +85·C
Supply Voltage to Ground Potential... .•. .. -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State .••. . • . . . . . . . . . . . . . . • • . .. -O.SV to + 7.0V
DC Input Voltage. . . . . . . . . . . . . . • . . . . • . .. -O.5V to +7.0V
Electrical Characteristics Over the Operating Range
Parameters
Description
CYM1540
Test Conditions
Min.
VOH
Output mGH Voltage
\tc = Min., IOH= -4.0 mA
\bL
Output LOW Voltage
Vee = Min., IOL = 8.0 mA
\tHA
Input HIGH Volt!!ge
AO - At7,C;S, WE
Input mGH Voltage
DIO - DIs
\tHD
\tID
Input LO'Y.Y2!!!!.ge
AO - Al7, CS, WE
Input LOW Voltage
DIO - DIS
\tK
Input Clal!m..~l
Ao - Al7, CS, WE
Vee = Min., lIN = -18 mA
\tLA
Max.
2.4
Units
V
0.4
V
2.0
6.0
V
2.2
6.0
V
0.8
V
0.8
V
-1.2
V
-0.5
IlL
Input Load Current
GND vee - 0.2V or '\iN < 0.2V
230
mA
= Max., I our= 0 mA,
CS --rr---------O+---------,
cs--~:~~--------~~------~
' - -_ _ _ _ _..J...._ _ _ _ _--'-_..L....
DO o - DOs
1560-1
1560-2
Selection Guide
CYM1560-30
30
CYM1560-35
35
CYM1560-45
45
Maximum Operating Current (rnA)
1125
1125
1125
Maximum Standby Current (rnA)
350
350
350
MaximumAccess Time (ns)
9-58
~F~PRFSS
--=-
F
PRELIMINARY
CYM1560
SEMICONDUCIOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Storage Temperature ................. - 45°Cto +125°C
Ambient Temperaturewith
PowerApplied ......................... -lOOCto +85°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.3Vto +7.0V
DC Input Voltage ...................... - 0.5V to + 7.0V
Ambient
Thmperature
O°Cto + 70°C
Range
Commercial
Vee
5V± 10%
Electrical Characteristics Over the Operating Range
1560
Parameter
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input ClamlLevel
Ao - A17, CS, WE
Vee = Min., lIN = -18 rnA
IIL
Input Load Current
GND.$. VI.$. Vee
loz
Output LeakageCurrent
GND .$. Va.$. Vee, Output Disabled
Icc
Vee Operating
Supply Current
ISB!
ISB2
Units
Max.
2.4
V
0.4
V
2.2
6.0
V
- 0.3
0.8
V
-1.2
V
-10
+10
-10
+10
!JA
!JA
Vee = Max., CS.$. VIL,
IoUT= ornA
1125
rnA
Automatic CS
Power-DownCurrent[l]
Max. Vee, CS ~ Vrn,
Min. Duty Cycle = 100%
350
rnA
AutomaticCS
Power-DownCurrentl1]
Max. Vee, MS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Y, or VIN.$. 0.2V
230
rnA
•
( f)
LLI
....I
~
C
o
Capacitance [2]
Parameter
CIN
Description
InputCapacitance
COUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee=5.0V
Notes:
1. A pull-up resistor to V cc on the CS input is required to keep the device deselected during power-up, otherwise ISB will exceed values
given.
2.
Max.
15
20
Units
pF
pF
Thsted on a sample basis.
AC Test Loads and Waveforms
OUTP~~314B1Q
30 pF
I
OUTP~~314B1Q
255Q
5 pF
I
INCLUDING _
_
INCLUDING _
JIGAND JIG AND SCOPE (a)
SCOPE (b)
Equivalent to:
THEvENIN EQUIVALENT
167Q
OUTPUT 0.0---'\I\o~...---oo 1.73V
ALL INPUT PULSES
255Q
'W~10~%
GND
55 ns
_
1560-3
9-59
I+-
~
10%
55 ns
1560-4
:E
:&;~PRFSS
~_
PRELIMINARY
CYM1560
. , SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangel3]
1560-30
Parameter
Description
Min.
Max.
1560-35
Min.
Max.
1560-45
Min.
Max.
Units
READ CYCLE
30
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACS
CS LOW to Data Valid
tIZCS
CS LOW to Low Z
5
tHZCS
CS mGH to High Z(4)
2
tpu
CSLOWtoPower-Up
3
tpD
cs mGH to Power-Down
35
30
5
45
35
5
30
5
35
5
20
2
2
ns
ns
20
3
35
ns
ns
45
5
20
3
30
ns
45
ns
ns
45
ns
WRITE CYCLE[S]
twc
Write Cycle Time
30
tscs
CS LOW to Write End
35
45
ns
20
tAW
Address Set-Up to Write End
20
2S
35
ns
2S
35
tHA
Address Hold from Write End
5
5
ns
5
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
tpWE
WE Pulse Width
20
2S
35
ns
tSD
Data Set-Up to Write End
15
20
2S
ns
tHD
Data Hold from Write End
5
5
5
ns
tLZWE
WE mGH to Low Z
2
2
2
tHZWE
WE LOW to High Z[4]
2
20
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V, output loading of the
specified IOI)IOH, and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of ACThst
Loads. Transition is measured ±500 mV from steady state voltage.
5. The internal write time of tbe memory is defined by the over/a)? of CS
WW and WE Ww. Both signals must be LOW to initiate awnteand
2
20
2
ns
20
ns
either signal can terminate awritebygoingHIGH.Thedatainput setupandbold timingsbouId be referenced to the rising edge of the signal
that terminates the write.
6. WE is HIGH for read cycle.
7. Device is continuously selected, CS = VJL.
Switching Waveforms
f......--__--*-
Read CycIeNo. 1[6,7)
Rc
ADDRESS
t
~tOHA~
DATA OUT
1
PREVIOUS DATA VALID mXX><*=================O=Al=A=VA=L=IO===============
1560-5
9-60
·&;~PRFSS
~,
PRELIMINARY
CYM1560
SEMIcet.lDUCIOR
Switching Waveforms
(continued)
Read Cycle No. 2[6,8]
CS
I RC
~~
..,--
lACS
HIGH IMPEDANCE
DATA OUT
_
VCC
SUPPLY
CURRENT
I HZCS
I
HIGH IMPEDANCE
DATAVAlJD
I LZCS
Ipu
____j-50-%------------------=1=: :~~
- l pD
1560-6
Write Cycle No.1 (WE ControlIed)[5]
ADDRESS
--
lwe
-:E-
-lEIscs
'\.'\.'\ '\.'\.'\.+
..., ~//// / / / / / / / /
lAW
l HA -
lSA
IPWE
Ir
-T'\.V ~
I
t
DATA IN
*"
IHD
*"
DATAVAlJD
')
DATA OUT
II
-1
.1
ISD
.1
I
--------------------------------------------~~--~HI~GH~I~MP~E=DAN~CE~---:t---«--------::)---k
I--
I---
IHZWE
tlZWE
DATA UNDEFINED
1560-7
Write Cycle No.2 (CS Controlled) [5,9]
IwC
ADDRESS
-
~~
-IflSA
Iscs
-I'-
~
IHA
lAW
IPWE
\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.~t""
DATA IN
DATA OUT
~_~_U_N_DE_R_N_ED
_____________
-:f// / / // / / / / / / /,
IHD
ISD
.)
'*
DATAVAlJD
'*
'I
')
-
IHZWE
~~.---------------------------
_________________________
HIGH IMPEDANCE
1560-8
Note.:
8.
Address Valid prior to or coincident with CS transition LOW.
9.
9-61
If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
~
2r.~ucroR
PRELIMINARY
Truth Table
CS WE
Data In
Data Out
Mode
H
X
X
HighZ
Deselect/lbwer-Down
L
H
X
Data
Outo-8
Read
L
L
Data
lno-8
HighZ
Write
Ordering Infonnation
Speed
(ns)
30
35
45
CYM1560PF - 30C
Package
lYPe
PF06
CYM1560PS-30C
PS07
CYM1560PF - 35C
PF06
CYM1560PS-35C
PS07
CYM1560PF -45C
PF06
CYM1560PS-45C
PS07
Ordering Code
Operating
Range
Commercial
Commercial
Commercial
Document#:38-M-00043-A
9-62
CYM1560
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUCTOR
16K X 16 Static RAM
Module
• 2V data retention (L version)
Features
• High-density 256K-bit SRAM module
Functional Description
• High-speed CMOS SRAMs
- Access time of12 ns
TheCYMl610isahigh-performance
256-kbitstaticRAMmoduleorganized
as 16Kwords by 16 bits. This module is constructed from four 16Kx4 SRAMs
in leadless chip carriers mounted on a
ceramicsubstratewithpins.
Selecting the device is achieved byachip selectin~tpinaswell as two byte select pins
(VB, LB)forindependentlyselectingupper
or lower byte for read orwrite
operations.
Writingtothememorymoduleisaccomplished when the chip select (CSh!Pe select(UB, LB) and write enable (WE) inputs
• Low active power
-3W(max.)
• Hermetic SMD technology
• TIL-compatible inputs and outputs
• Low profile
- Max. height of .215 in.
• Small PCB footprint
-1.2 sq. in.
• JEDEC-def"medpinout
• Independent byte select
CYM1610
Logic Block Diagram
are Law. Data on the input/output pins of
the selected byte (1108 - 1/015,
1/00 - 1/07) is written into the memorylocation specified on the address pins (Ao
throughA13)·
Readingthe device is accomplishedbnakingchipselect (CS):!!x!e select (UB, ~
and output enable (OE) LOW, while WE
remains inactive or HIGH. Underthese
conditions, thecontentsofthememorylocation specified on the address pins will appear
on the appropriatedatainput/outputpins.
The input/output pins remain in a high- impedan~a~whenchipselect (CS1.£.yte
select (UB, LB) or output enable (OE) is
HIGH, orwrite enable (WE) is Law.
Pin Configuration
DIP
•
ThpView
~-~3~1~4---------r---------------'
cs -----,.-+-------,
Vee
Vce
~------~;-~---------,
OE - - r - I - - H f - - - - - - - ,
cs
WE
1/°15
1/0 14
1/°13
1/0 12
1/0 11
1/°10
I/Og
I/O a
m
US
L---t----if-i-+-----....L..---r'-- I/O a - I/q5
0
0
::E
Aa
A7
As
As
A4
A3
A2
A1
Ao
1/0 7
I/Os
1/0 5
1/0 4
1/°3
1/°2
1/01
I~
IB--------------~+_----------~
LLl
..J
:::l
GND
GND
UB----~-r_+_+---L_+--~~-r_+--~
en
NC
A13
A12
A11
A10
Ag
'------------------J'-----:;-r- 1/00 - I/D,
1610-2
1S10-1
Selection Guide
1610HD-12 1610HD-15 1610HD-20 1610HD-25 1610HD-35 1610HD-45 1610HD-50
Maximum Access Time (ns)
Maximum OperatiugCurrent
(rnA)
Maximum Standby Current
(rnA)
Com'l
12
15
20
25
35
45
50
550
550
330
330
330
330
330
550
550
360
330
330
330
250
60
60
60
60
60
250
250
60
60
60
60
Mil
Com'l
Mil
250
9-63
CYM1611
CYPRESS
SEMICONDUCTOR
16K X 16 Static RAM Module
Features
Functional Description
• High-density 256-kilobit SRAM
module
The CYMI611 is a very high performance
256-kilobit static RAM module organized
as 16Kwordsbyl6bits. The module is constructed using four 16K x 4 static RAMs
mounted on a vertical substrate with pins.
The vertical DIP format minimizes board
spacewhile still keeping a maximum height
of 0.5 in.
• High-speed
- Access time of 12 ns
• 16-bit-wide organization
• Low active power
-1.8W (max.) at 25 ns
• TIL-compatible inputs and outputs
• Low profile
- Max. beight of 0.5 in.
• Small PCB footprint
- 0.4 sq. in. (ceramic version)
- 0.6 sq. in. (plastic version)
location specified on the address pins (Ao
through A 13).
Readingthe device is accomplishedbytaking chip select CS and outE!!!.enable (OE)
LOWwhilewriteenable(WE)remainsinactive or IDGH. Under these conditions,
the contents of the memory location specified on the address pins will appear on the
sixteen data input/output pins.
The input/output pins remain in a highimpedance state unless the module is selected, outputs are enabled, and write enable (WE) is IDGH.
Writing to the memory module is accomplishedwhen the chip select (CS) and write
enable (WE) inputs are both LOW, Data
on the sixteen input/output pins (Do
through 015) is written into the memory
• 2V data retention (L version)
Logic Block Diagram
Pin Configuration
VDIP
ThpView
AO-~3~~14~------~--------------~
~------~-4----------~
WE
-----.--I--I------~
~
----r-If-I-4--------.
1611-1
1611-2
Selection Guide
1611-12
1611-15
1611-20
1611-25
1611-30
1611-35
Maximum Access Time (ns)
12
15
20
25
30
35
45
MaximumOperating Current (mA)
550
550
330
330
330
330
330
Maximum Standby Current (mA)
250
250
80
80
80
80
80
9-64
1611-45
~
.:~
~,~
CYM1611
Maximum Ratings
(Above which the useful life may be impaired.)
Operating Range
Range
Commercial
Storage Temperature .•............... - 6SoC to +l25°C
Ambient 'Thmperature with
Power Applied .•...................... -10°C to +B5°C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . • . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Ambient
Temperature
O°C to + 70°C
Vee
5V± 10%
Electrical Characteristics Over the Operating Range
Parameters
Description
Output mGH Voltage
VOH
VOL
VIH
lest Conditions
= Min., IOH = -4.0 rnA
Vee = Min., IOL = -B.O rnA
Vee
Output LOW Voltage
Input mGH Voltage
Input LOW Voltage
Input Load Current
VIL
Ilx
1611-12
1611-15
Min.
Max.
GND Vce - 0.3v, or VIN < O.3V
"CS" Power-Down
Units
C
o
:::E
Capacitance[2j
CIN
Parameters
Description
Input Capacitance
COUT
Output Capacitance
lest Conditions
TA = 25°C, f
Vce = 5.0V
Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
AC Test Loads and Waveforms
Rl 481.n
5V~
J _
R2
30 pF
OUTPUT
2SS.n
-
5V5f1
5 pF
INCLUDING
JIG AND
SCOPE
-
(a)
Equivalent to:
2.
,
J
-
(b)
3.0V---
167.n
Max.
Units
40
pF
15
pF
ALL INPUT PULSES
90%
R2
255.n
_
GND
.s.5ns
-
1611·3
THEVENIN EaUIVALENT
OUTPUT~
= 1 MHz,
Thsted on a sample basis.
Rl 481.n
OUTPUT
INCLUDING
JIG AND
SCOPE
LLI
...J
1.73V
9-65
1611-4
CYM1611
Switching Characteristics Over the Operating Range(3)
1611-12
Parameters
Description
Min.
Max.
1611-15
Min.
Max.
1611-20
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle TIme
tAA
Address to Data Valid
toHA
tACS
~ WW to
Data \-hlid
12
15
tOOE
'OE LOW to Data Valid
10
10
tLZOE
2
tHZOE
<:m WW to Low Z
<:m HIGH to High z[4]
tLZCS
<::S WW to Low ZlSj
3
tHZCS
tpu
CSHIGH to High z[4.S]
12
Data Hold from Address Change
2
2
20
10
3
8
3
8
5
8
8
CS HIGH to Power-Down
tpD
WRITE CYCLEL6j
2
2
0
0
20
15
8
CS WW to Power-Up
20
15
12
12
8
0
20
15
twc
Write Cycle Time
12
15
20
tscs
CS WW to Write End
10
12
15
tAW
Address Set-Up to Write End
10
12
15
tHA
Address Hold from Write End
2
2
tSA
tpWE
Address Set-Up to Write Start
0
0
WI! Pulse Width
10
12
tSD
Data Set-Up to Write End
10
10
2
0
15
10
2
3
tHD
Data Hold from Write End
2
2
tLZWE
WI! HIGH to Low ZL4j
WI! LOW to High Z
3
3
tHZWE
0
7
0
7
0
os
os
os
os
os
os
os
os
os
os
os
os
os
os
os
os
ns
7
os
os
os
os
Notes:
3. 11:st conditions assume signaL transition times of 5 ns or less, timing
reference levels of 1.5Y, input levels of 0 to 3.0Y, and output loading of
the specified IorftoH and 30-pF load capacitance.
4. tHZOEo tHZCSo and tHZWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. Transition is measured ::1:500 mV from steady state
voltage.
5. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
6. The internal write time of the memory is defmed by the overlap ofCS
LOW and WE LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hoLd timing should be referenced to the rising edge of the
signal that terminates the write.
9-66
CYM1611
Switching Characteristics Over the Operating Range(3) (continued)
1611-25
Parameters
Descriptioo
Min.
READ CYCLE
Read Cycle TIme
tRC
Min.
Address to Data Valid
tOHA
Data Hold from Address Change
Max.
30
25
tM
1611-35
1611-30
Max.
Min.
3
Min.
Max.
45
35
30
25
1611-45
Max.
ns
45
35
3
3
Units
ns
ns
5
~ WW to Data Valid
25
30
35
45
ns
15
20
25
30
ns
0
tHZOE
<:m WW to Data Valid
<:m WW to Low Z
<:m mGH to High zl4J
tLZCS
~ WW to Low zlSJ
5
tACS
tDOE
tLZOE
tHZCS
~ HIGH
tpli
~ WW to Power-Up
tpD
~ HIGH to Power-Down
0
to High zl4, 5)
10
20
15
20
10
20
ns
ns
0
35
30
ns
ns
15
0
0
0
20
10
10
ns
0
0
15
10
45
ns
WRITE CYCLEl6)
twe
Write Cycle TIme
20
25
25
35
ns
tscs
C'S WW to Write End
20
25
30
40
ns
tAW
Address Set-Up to Write End
20
25
30
40
ns
tHA
Address Hold from Write End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
2
ns
tPWE
WP: Pulse Width
20
25
25
30
ns
tSD
Data Set-Up to Write End
13
20
20
25
ns
tHD
Data Hold from Write End
2
2
2
2
ns
tLZWE
WP: mGH to Low Z
WP: WW to High Z
0
tHZWE
1
0
3
12
5
0
12
0
5
15
ns
ns
5
Data Retention Characteristics (L Version Only)
1611
Parameters
VDR
ICCDR
tCDR
tR
Iu
Description
Vee for Retention of Data
Data Retention Current
Chip Deselect to Data Retention TIme
Test Conditions
Vee
=2.0V,
CS' ~ Vee -
0.2V,
VIN ~ Vee - 0.2V,
orVINsO.2V
Operation Recovery Time
Min.
4
mA
ns
ns
5
Notes:
=
=
Units
V
0
tRC(7)
Input Leakage Current
7. tRe = read cycle time.
8. WE is HIGH for read cycle.
Max.
2.0
=
9. Device is continuously selected, ~ VIL and OE VII..
10. Address valid prior to or coincident with ~ transition LOW.
!lA
11. Data I/O will be high impedance if OE VIH.
12. Ift::St:ocsHIGHsimultaneouslywithWEHIGH,theoutputremains
in a high-impedance state.
9-61
II
U)
UJ
...J
:::)
C
o
::E
CYM1611
Data Retention Waveform
:f____
DATA RETENllON MOOE
f.~:
"cc
VD_R_"'2_V_ _ _
~ ll/ZZT.'
"oR
~~
?sS\\S
"1"
I
IH
V
1611-5
Switching Waveforms
tl8• 9)
Read Cycle No.
:~ ~§" " -PREVl: -o-u-I-SO-DA:-HA-:J:-2:Il-jUJD- - I-A -~- -: : : _I_RC_.I-~ ~ ~ ~ ~ ~ ~ ~ ~ ~ _:rA_'-~_-_IO~ ~ ~ ~ ~ ~ ~ ~1611-1i
Read Cycle No. 2[8. 10)
IRC
---:J~
'"l
I'
lACS
..l
r-
~I'-
I---
lOOE
tlZOE
IHZCS
HIGH IMPEDANCE
DATA OUT
I HZOE -
.'\c
HIGH IMPEDANCE
DATA VAlID
'\c
tLZCS_ t pu
Vee
SUPPLY
CURRENT
-------~-~----------------------------------------~:
ioe--IPD
1611-7
Write Cycle No.1 (WE Controlled)[6. 11)
ADDRESS
-
twc
-:f-
~
'\. '\."\ I'\.'\.'\.""k-
~
fo/ / / /, / / / / / / / / /
tAW
lSA
l HA -
-,
IPWE
,
T~'\..:I It"
. "1 ~
IHD
tSD
DATA IN
..,~
DATA-IN VAlID
-l ~
------------------------------------;!I-__
: : :~H~~H~IM~~~~_-:t~------)I-k
..... IHZWE
DATAI/O
E-
tscs
I--
tLZWE
DATA UNDEANED
161 HI
9-68
CYM1611
Switching Waveforms (continued)
Write Cycle No. 2 (~ Controlled) [6,11,12]
twc
ADDRESS ~ ~
-
~t"-
..,.
tSA
tscs
..., ~
tHA
tAW
'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.~
...
tPWE
...,f// / / / / / / / / / / / /
tHO
tso
DATA IN
'*
I
DATAI/O
'*
DATA VALID
-
tHZWE
DATA UNQEFINEC
I
~!iH IYe5~"i
1611-9
'fruth Table
"CS OE WE
H
X
X
Ordering Information
Inputs!
Outputs
HighZ
Speed
(ns)
Ordering Code
Package
lYPe
Operating
Range
Deselect!
Power-Down
12
CYM1611HV -12C
HV01
Commercial
CYM1611PV -12C
PV03
15
Mode
L
L
H
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
20
25
30
35
45
Document #: 38-M-00015-B
9-69
CYM1611HV -15C
HV01
CYM1611PV -15C
PV03
CYM1611HV-2OC
HVOl
CYM1611LHV -2OC
HVOl
CYM1611PV -2OC
PV03
CYM1611LPV -2OC
PV03
CYM1611HV-25C
HV01
CYM1611LHV 25C
HVOl
CYM1611PV-25C
PV03
CYM1611LPV-25C
PV03
CYM1611HV -3OC
HV01
CYM1611LHV -30C
HVOl
CYM1611PV-3OC
PV03
CYM1611LPV - 30C
PV03
CYM1611HV -35C
HVOl
CYM1611LHV -35C
HVOl
CYM1611PV - 35C
PV03
CYM1611LPV - 35C
PV03
CYM1611HV -45C
HVOl
CYM1611LHV -45C
HVOl
CYM1611PV -45C
PV03
CYM1611LPV -45C
PV03
Commercial
Commercial
II
en
LLI
...I
::l
Q
Commercial
Commercial
Commercial
Commercial
o
:E
CYM1620
CYPRESS
SEMICONDUCTOR
64K X 16 Static RAM Module
Features
Functional Description
• High-de~sity 1-megabit SRAM
module
The CYM1620 is a very high performance
I-megabit static RAM module organized
as 64Kwords by 16 bits. The module is constructed using four 32K x 8 static RAMs
mounted onto a substrate. A decoder is
used to interpret the higher-order address
A 15 and select one of the two pairs of
RAMs.
Writing to the memory module is accomplished when the chip select (CS),~e select (UB, LB) and write enable (WE) inputs are both LOW. Data on the input/output pins of the selected byte (1/08 through
1/015,1/00 through I/07) is written into
• High-speed CMOS SRAMs
- Access time or20 ns
• 4O-pin, 0.6-inch-wide DIP package
• Low active power
-1.9W (max.)
•
•
•
•
Hermetic SMD technology
TIL-compatible inputs and outputs
JEDEC-compatiblepinout
Commercial and military
temperature ranges
the memory location specified on the address pins (AothroughA15).
Readingthe device is accomplish~tak
ing chip select (CS)~e select (UB, !m
and output enable (WE) LOW, while WE
remains inactive or IDGH. Under these
conditions, the contents of the memory 10cation specified on the address pinswill appear on the appropriate data input/output
pins.
The input/output pins remain in a hjg!limpedance state when chip select (CS),
b~ select (UB, LB) or output enable
(OE) is HIGH, or write enable (WE) is
LOW.
Logic Block Diagram
Pin Configuration
DIP
lbpView
AO-~4----71~5-------------'----------~
~--------------~------~
~------------~+4------~
A15 ----r--l
~--T""""if--l
'---.----1
UB--++-----J
1l! ________....I
L-+H__......L_---,"-
110 8
- 1I~5
'--_ _ _ _-1-_~_
1100
-
1/0,
1620-1
162().2
Selection Guide
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
Commercial
1620-20
1620·25
1620-30
1620-35
1620·45
20
340
25
30
35
45
55
340
340
340
340
340
140
140
Military
Maximum Standby Current (rnA)
Commercial
340
340
340
140
140
140
140
"H4{)',:
140
140
140
,<,'
Military
Shaded area contains preliminary information.
9-70
340'
1620·55
','"
:~
·
CYM1620
~-CYPRESS
~_"J
SEMICONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Commercial
StorageThmperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied ............ (Commercial)-lO°Cto +55°C
(Military) -55°Cto +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Military
Ambient
lemperature
O°Cto + 70°C
Vee
5V± 10%
-55°Cto +l25°C
5V± 10%
Electrical Characteristics Over the Operating Range
1620
Parameters
Min.
2.4
Max.
2.2
-0.5
-10
Vee
0.8
-10
+10
!JA
!JA
VOH
VOL
Vrn
VIL
IIX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
loz
Output Leakage Current
GND5VI5 Vee
GND 5 Vo 5 Vee, Output Disabled
los
Output Short Circuit
Vee = Max., VOUT = GND
-300
rnA
ICCx16
Vee Operating Supply
Current
Ycc..=..Max·,loOT = 0 rnA,
CS, VB, and LB = VIL
340
rnA
leCx8
Yce = Ma&!oUL::' 0 rnA,
CS 5 VIL, VB or LB = VIL
200
rnA
ISB!
Vee Operating Supply
Current
AutornaticCS Power-Down
Max. Vee; CS ~ Vrn
Min. Duty Cycle = 100%
140
rnA
ISB2
AutomaticCS Power-Down
Max. Vee; CS ~ Vee - 0.3Y,
VIN > Vee - O.3V or VIN < O.3V
80
rnA
lest Conditions
Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Curren~l]
Curren~2]
Curren~2]
0.4
+10
Units
V
V
V
V
II
en
LLI
...I
=»
C
o
:::E
Capacitance [3]
qN
Parameters
Description
InputCapacitance
CoOT
Output Capacitance
lest Conditions
TA= 2S o C,f= 1 MHz,
Vee = S.OV
Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vex:; on the CS input is required to keep the device deselected during Vex:;power-up, otherwise ISBWili exceed values
3.
Max.
35
40
Units
pF
pF
Thsted on a sample basis.
given.
AC Test Loads and Waveforms
R1481.(1
ALL INPUT PULSES
R1481.(1
OUTP:~ ~ OUTP:~ ~
'n,~~:FI
'n,.~,:FI
J 1
J 1
_
R2
255
INCWDING
JIG AND
SCOPE
-
-
3.0V---90%
R2
.(1
255
INCWDING
JIG AND
SCOPE
(a)
-
(b)
GND
.(1
-
1620-3
I
Equivalent to:
THEVENIN EQUIVALENT
167.(1
OUTPUT o-----wv----o 1.73V
9-71
1620-4
CYM1620
Switching Characteristics Over the Operating Rangef4J
Parameters
READ CYCLE
tRC
tM
toHA
tACS
tOOE
tLZOE
tHZOE
tLZCS
tHzcs
WRITECYCLEll
twc
tscs
tAW
tHA
tSA
tpWE
tso
tHO
tLZWE
tHZWE
Parameters
READ CYCLE
tRe
tM
tOHA
tACS
tOOE
tLZOE
tHZOE
tLZCS
tHZCS
WRITECYCLEl'
twc
tscs
tAW
tHA
tSA
tpWE
tSD
tHO
tLZWE
tHZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from AddressChange
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CSLOWtoLowZl~J
1620-20
Min.
Max.
20
3
Description
Read Cycle Time
Address to Data Valid
Data Hold from AddressChange
CS LOW to Data Valid
OE LOW to Data Valid
OELOWtoLowZ
OE HIGH to High Z
CSLOWtoLowZl~J
0
3
20
15
15
2
5
15
10
2
0
0
8
1620-35
Min.
Max.
20
45
40
40
15
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
20
5
5
25
20
5
5
0
25
0
5
15
55
45
45
5
5
30
25
5
5
0
ns
ns
ns
ns
ns
ns
ns
ns
55
30
20
20
9-72
5
0
Units
ns
55
45
25
20
3
1620-55
Min.
Max.
55
5
0
30
25
25
5
5
25
18
3
5
0
45
35
18
35
30
30
5
5
25
18
3
5
0
10
1620-45
Min.
Max.
35
3
20
5
45
35
15
0
3
25
20
20
2
5
20
12
2
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
15
10
20
20
3
25
10
10
CS HIGH to High Zl', bJ
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low ZPJ
WELOWtoHighZLO,OJ
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
25
20
10
0
1620-30
Min.
Max.
30
25
20
CS HIGH to High Zl', bJ
Write Cycle Time
CSLOWto Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to LowZPJ
WE LOW to High ZLo, OJ
1620-25
Min.
Max.
.
-
'~PRESS
F
CYM1620
SEMICONDUCTOR
Switching Waveforms[lOJ
--*--
Read Cycle No. 1[8, 9J
'"O~ ~§I4-----tO-HA-~==-I-'~"
PREVIOUS DATA VAUD "*XX><*========================D=Al=A=VA=U=D=============
=======
162Q.5
DATA OUT
Read Cycle No. 2[8,lOJ
tRC
~r
-:If-
tACS
.........
tLZOE
HIGH IMPEDANCE
DATA OUT
....,1'-
IDOE
~
tHZOE-
DATAVAUD
/ L / /
~ILZCS14-- tpu
VCC
SUPPLY
CURRENT
IHZCS
HIGH IMPEDANCE
~tpD
_j-50%- - - - : 1 : : : : : :
1620-6
Write Cycle No.1 (WE Controlled) [7, 11 J
ADDRESS
--
-l ~
/ /. ' / / / / / / / / /
tHA-
tPWE
I
T'\V .....
.....~
I
tSD
.1
DATA IN
C
....., ~//
lAW
I
::)
-
Iscs
tSA
~
DATA-IN VALID
DATAI/O
W
..J
-jt-
\. \. \ l\.\.\'-T
DATA UNDEFINED
.=!
tHZWE
.1
.1 tHD
"*
I
- ILZWE HIGH IMPEDANCE
162Q.7
Notes:
4. Test conditions assume signal transition times of S ns or less, timing
reference levels of 1.Sv, input levels of 0 to 3.0V, and output loading of
the specified IOl)lOH and 30-pF load capacitance.
S. At any given temperature and voltage condition, 1Hzcs is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
6. tHZcsandtHZwEarespecifiedwithCL = SpFasinpart (b) ofACThst
Loads. 1tansition is measured ±SOO mV from steady state voltage"-7. The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
•
U)
IWC
set-up and hold timing should be reference to the rising edge of the signal that tenninates the write.
8. WE is IDGH for read cycle.
9. Device is continuously selected, CS = V~d OE = VII"
10. Address valid prior to or coincident with CS transition LOW.
11. Data I/O will be high impedance ifOE = V!H.
12. IfCS goesIDGH simultaneously with WEIDGH, the output remains
in a high-impedance state.
9-73
o
::E
fYnPRFSS
~_•
CYM1620
SEMICONDUCIDR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled) [7, 8,
ADDRESS
--
12)
Iwe
.l~
"'~
lSA
Iscs
~
..., ~
lHA
lAW
IPWE
:s\.\.\.\.\.\.\.\.\.\.~\.\.\.\.\.\.~ r-
...., fo/ /
/ / / / / / / / / / //
ISD
DATA IN
DATAI/O
_____
. . .;D; .;A~; .;A.; ;UN.; ;D.; ;EF.; ;IN; ; ED; . .
*"
IHD
*"
DATA INVAUD
'I
I--
I HZWE
9-
___________
'I
HIGH IMPEDANCE
1620-8
Truth Table
Ordering Information
CS UB LB OE WE
H
X
X
X
L
H
H
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
L
L
L
H
L
L
H
L
L
H
Inputs!
Outputs
X
HighZ
X
X
HighZ
L
L
L
X
X
X
H
H
H
H
H
H
L
L
L
H
H
H
Data auto 15
DataIno 7
Data Outs-iS
DataIno 15
DataIno 7
Data Ins 15
HighZ
HighZ
HighZ
Mode
Speed
(ns)
Deselect!
Power-Down
Deselect!
Power-Down
Read
Read Lower Byte
Read Upper Byte
Write
Write Lower Byte
Write Upper Byte
Deselect
Deselect
Deselect
20
25
Document#: 38-M-OOOO8-C
9-74
30
35
45
55
Ordering Code
Package
'JYpe
Operating
Range
CYM1620PD-20C
CYM1620PD-25C
CYM1620HD-25C
CYM1620PD 30C
CYM1620HD-30C
CYM1620PD-35C
CYM1620HD-35C
CYM1620HD 35MB
CYM1620PD-45C
CYM1620HD-45C
CYM1620HD-45MB
CYM1620PD 55C
CYM1620HD-55C
CYM1620HD-55MB
PD04
PD04
HD03
PD04
HD03
PD04
HD03
HD03
PD04
HD03
HD03
PD04
HD03
HD03
Commercial
Commercial
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications.
CYPRESS
SEMICONDUCTOR
64Kx 16 Static RAM
Module
Features
Functional Description
• High-density I-megabit SRAM module
• High-speed CMOS SRAMs
- Access time of20 ns
• Customer configurable
-x4,x8,xI6
TheCYM1621 isahigh-performance
I-megabitstaticRAMmoduleorganizedas
64Kwordsbyl6bits. This module is constructedfrom sixteen 64Kx 1 SRAMsin
leadlesschipcarriersmountedonaceramic
substrate with pins. Four separate CS pins
are used to control each4-bit
nibbleofthe 16-bitword. This feature permits the user to configure this module as
either 256Kx 4, 128Kx80r 64Kx 160rganization through externaJdecodingand appropriatepairingoftheoutputs.
Writingtothedeviceisaccomplishedwhen
the chip select (CSxx) and write
enable (WE) inputs are both LOW. Data on
the data lines (Dx) is written into the memory location specified on the address pins
(AothroughA 15).
• lAIw active power
- 6.8W (max.)
• Hermetic SMD technology
• TTL-compatible inputs and outputs
• lAIw profile
- Max. height of .270 in.
• Small PCB footprint
-2 sq. in.
• 2V data retention (L version)
CYM1621
Readingthedeviceisaccomplishedbytakingthe c.!!!E..select(CSxx) LOW, while write
enable(WE)remainsHIGH. Under these
conditions thecontentsofthememorylocation specified on the address pinswill appear
on the data lines (Dx).
The data output is in theE.!Bh-impedance
statewhench~able (CSxx) is HIGH or
write enable (WE) is LOW.
Power is consumed in each 4-bit nibble only
when the appropriate CS is enabled, thus
reducingpowerinthex40rx8mode.
Pin Configuration
Logic Block Diagram
~_~5~16~-,----------.----------.---------,
DIP
"lbpView
WE----rt--------rt--------~--------,
II
C~-3--,-rt------,-rt-------rt;------,
tJ)
W
....I
;:)
C~-7--~~------~~-------.~------~
C
o
:::e
C~-11
---.t;-------.-rt-------rt-r------,
C~2-15 ---r+-~------~~------~~+_------,
1621-2
1621·1
Selection Guide
1621-20
MaximumAccess Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
Commercial
1621-30
1621-35
1621-45
20
25
30
35
45
1250
1250
1250
1250
1250
1250
1250
1250
1250
320
320
320
320
320
320
320
320
Military
Commercial
1621-25
320
Military
9-75
CYM1622
CYPRESS
SEMICONDUCTOR
64Kx 16 Static RAM Module
Features
Functional Description
• High-density1-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of25 ns
The CYM1622 is a very high perfonnance
I-megabit static RAM module organized
as64Kwordsbyl6bits. The module is constructed using four 64K x 4 static RAMs
mounted onto a vertical substrate with
pins. The pinout of this module is compatible with two other Cypress modules
(CYMI611 and CYM1624) to maximize
systemfiexibility.
• Low active power
-2.2W(max.)
• SMD technology
• TTL-compatible inputs and outputs
• Pinout compatible with CYM1611 and
CYM1624
• Low profile
- Max. height of .50 in
Writing to the memory module is accomplishedwhen the chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the sixteen input/output pins (JlOo
through JlO,S) of the device is written into
the memory location specified on the address pins (Ao through A,S).
Readingthe device is accomplished bytak~chip select (CS) and output enable
(OJ?) ~~ while write enable (WE) remamsmaCtiveor HIGH. Under these conditions, the contents of the memory location specified on the address pins will app~ar on the appropriate data input/output
pms.
The input/output pins remain in a highimpedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
• Small PCB footprint
-0.5 sq. in. (cemmic)
- 0.68 sq. in. (FR4)
Logic Block Diagram
Pin Configuration
Ao - ~5----r------~
VDIP
lbpView
~-----r+--------~
~----~~------~
Vee
110,5
110 '4
110 '3
110 '2
GND
A '3
A'2
A"
A ,o
Ag
Aa
1/0 11
110 '0
cs--~----~~--------~
' -_ _ _ _ _---L_--L_
1/00 -
II0 g
1I0 a
WE
1I~5
"ITE
A'5
NC
1622-1
1622-2
Selection Guide
1622-25
1622-30
1622-35
MasimumAccess Time (ns)
25
30
35
45
Masimum Operating Current (rnA)
Masimum Standby Current (rnA)
400
140
400
140
400
140
400
9-76
1622-45
140
~
~-CYPRESS
~,
CYM1622
SEMICONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Storage Temperature ................. - 65°Cto +l25°C
Ambient Temperaturewith
PowerApplied ......................... -10°C to +SO°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto +7.0V
DC Input Voltage ...................... - 0.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Ambient
lemperature
Vee
5V± 10%
Electrical Characteristics Over the Operating Range
CYM1622
Parameters
VOH
VOL
VIH
VIL
IJX
Min.
2.4
Max.
Vee
O.S
+20
+10
!JA
!JA
Max., lOUT = 0 rnA,
CS5VIL
Vee = Max.; CS ~ VIH
Min. Duty Cycle = 100%
400
rnA
140
rnA
Vee = Max.; CS ~ Vee - 0.2Y,
VIN> Vee - 0.2VorVIN < 0.2V
SO
rnA
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
lest Conditions
Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = S.O rnA
0.4
Input Load Current
GND5 VI5 Vee
2.2
-0.5
-20
loz
Output LeakageCurrent
GND 5 Vo 5 Vee, Output Disabled
-10
Icc
Vee Operating Supply
Current
AutomaticCS Power-Down
Current
AutomaticCS Power-Down
Current
Ycc =
ISB!
ISBZ
Units
V
V
V
V
Capacitance[Z]
CIN
Parameters
Description
InputCapacitance
CoUT
Output Capacitance
lest Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
1. VIL(MIN) = -3.0V for pulse widths less than 20 ns.
2.
Max.
35
15
Units
pF
pF
Tested on a sample basis.
AC Test Loads and Waveforms
~ln
OUTP~~~
'n,~~:Fl
J
INCWDING
JIG AND
SCOPE
-
ALL INPUT PULSES
~ln
1_
OUTP:~
255n
-
3.0V---
'n,.~:Fl
J
INCWDING
JIG AND
SCOPE
(a)
-
(b)
90%
1_
GND
255n
-
1622·3
I
Equivalent to:
THEVENIN EQUIVALENT
167n
OUTPUT o--------vw---o 1.73V
9-77
1622·4
•
£.APRE5S
~__
CYM1622
SEMlCOlDUCTOR
Switching Characteristics Over the Operating Range[3]
1622-25
Parameters
Description
READ CYCLE
Read Cycle Time
tRC
Min.
Max.
1622-30
Min.
Max.
1622-35
Min.
Max.
1622-45
Min.
Max.
Units
25
30
35
45
ns
tM
Address to Data Valid
25
30
35
45
ns
tOHA
Data Hold from Address Change
CS LOW to Data Valid
3
30
3
35
3
45
ns
tACS
3
25
tOOE
OE LOW to Data Valid
tlZOE
OE LOW to Low Z
tHZOE
OE mGH to High Z
trzcs
CS LOW to Low Z
CS mGH to High ZlqJ
3
CS LOW to Power-Up
0
tHZCS
tpu
tpo
15
0
20
0
15
3
25
0
25
CS HIGH to Power-Down
3
3
30
20
0
30
35
0
35
ns
ns
20
20
20
15
0
0
20
ns
30
25
ns
ns
20
ns
45
ns
45
ns
WRITECYCLEl~J
twc
Write Cycle Time
25
30
CS LOW to Write End
20
25
35
30
45
40
ns
tscs
tAW
Address Set-Up to Write End
20
25
30
40
ns
tHA
Address Hold from Write End
3
3
Address Set-Up to Write Start
2
3
2
ns
tSA
tpWE
3
2
WE Pulse Width
25
25
Data Set-Up to Write End
20
20
30
25
ns
tso
20
15
tHO
Data Hold from Write End
2
2
2
2
ns
trzWE
WE HIGH to Low Z
WE LOW to High Zl4J
0
0
0
0
tHZWE
0
15
Noles:
3. Thst conditions assnme signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of
the specified IOrJIOH and 3Q.pF load capacitance.
4. tHZCS andlHzwEarespecifiedwithCL = 5 pF as in part (b) ofACThst
Loads. "Itansition is measured ±500 mV from steady-state voltage.
5. The internal wtite time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a wtite,
and either signal can terminate a wtite by going HIGH. The data input
6.
7.
8.
9.
0
2
15
0
15
0
ns
ns
ns
ns
20
ns
set-np and hold timing should be reference to the rising edge ofthe signal that terminates the write.
WE is IDGH for read cycle.
Device is continuouslyselected,CS = VIL.
Address valid prior to or coincident with Cs transition LOW.
IfCS goesIDGH simnltaneouslywith WE HIGH, the output remains
in a high-impedance state.
Switching Waveforms
Read Cycle No. d 6, 7]
~:,: ~"'·"~-P~R~EV~IO~U~:0~ ~A-'-2~V~ALI~D~t-A -~ ~ ~ ~ ~ _t_RC_.-I-~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~_~_A'_'_'- ALl- -D~ ~ ~ ~ ~ ~ ~ ~ ~ ~
1622-5
9-78
CYM1622
Switching Waveforms (continued)
Read Cycle No. 2[6, 8]
tRC
~r
-:ftACS
"" ....
-:~
I---
tDOE
tHZOE-
t LZOE
t HZCS
HIGH IMPEDANCE
DATA OUT
1L
HIGH IMPEDANCE
DATA VALID
_ t LZCS _
tpu
Vee
SUPPLY
CURRENT
----1-50%-------------------:1== ::~
I---
t pD
1622-6
Write Cycle No.1 (WE Controlled)[5]
twe
ADDRESS
-
-3 ~
~f-tscs
\.\.\ '\.'\. '\.-T
-, 'f-////
tSA
'/////////
tHA-
tAW
tPWE
I
~\. "\..J It"
-::;
II
f-
I
DATA IN
J tHO
tso
J
"* I--"*
------------------------------------------~I---~H~IG~H~IM~P~ED~AN~C~E-----:t~=:::::::::
::)/--k.DATA-IN VALID
I
I
t HZWE
DATA OUT
- - tlZWE
DATA UNDEFINED
1622-7
Write Cycle No.2 (CS Controlled)[5, 9]
ADDRESS
--
twe
--'
F-
~f--
tSA
tscs
...,~
t
tHA
tAW
tPWE
\.\.\.\.\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.~ !.-
-,f-/ / / / / / / / / / / / / /
tSD
DATA IN
*
I
DATA If0
DATA-IN VALID
I--
t HZWE
tHO
*
I
HIGH IMPEDANCE
DATA UNDEANED
1622-8
9-79
~CYPRF.SS
~~_,
CYM1622
SEMICONDUCIDR
Truth Table
CS
OE
Orderi~g
WE
Mode
Inputs/Outputs
H
X
X
HighZ
Deselect/lbwerDown
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Information
CYM1622HV -25C
Package
'tYPe
HV03
CYM1622PV-25C
PV04
CYM1622HV -30C
HV03
CYM1622PV - 30C
PV04
CYM1622HV-35C
HV03
CYM1622PV-35C
PV04
CYM1622HV -45C
HV03
CYM1622PV -45C
PV04
Speed
(os)
25
30
Deselect
35
45
Document#: 38-M-OOOOI-B
9-80
Ordering Code
Operatiog
Range
Commercial
Commercial
Commercial
Commercial
CYM1624
CYPRESS
SEMICONDUcrOR
64Kx 16 SRAM Module
Features
Functional Description
• High-density 1.megabit SHAM module
The CYM1624 is a very high perfonnance
I-megabit static RAM module organized
as 64K words by 16 bits. This module is
constructed using four 64K x 4 static
RAMs in SO] packages mounted on an epoxy laminate board with pins. The pinout
of this module is compatible with two other
Cypress modules (CYMI611 and
CYM1622) to maximize system flexibility.
Writing to the module is accomplished
when the chip select (rn) and write enable
(WI!) inputs are both LOW, Data on the
sixteen input/output pins (1100 through
I101S) of the device is written into the
• High.speed CMOS SHAMs
-Access time 0(25 ns
• Low active power
-2.7SW (maL)
• SMD technology
• TTL-compatible inputs and outputs
• Pin layout compatible with CYM1611
andCYM1622
• Low profile
- Max. height of .54 in.
• Small PCB footprint
-0.7 sq. in.
Logic Block Diagram
memory location specified on the address
pins (Au through A1S)·
Reading the device is accomplished by taking chip select (r:S) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the
memory location specified on the address
pins (Au through AlS) will appear on the
appropriate data input/output pins
(liDo through 1/015).
The data input/output pins remain in a
high-impedance state when chip select
(CS) is HIGH or when write enable (WI!)
is LOW,
Pin Configuration
Plastic VDIP
Ao -
~5i-----r----~
~----~~------~
(/)
U..I
..J
::::)
C
o
:t
1/0 0 -1/0 15
1624-1
1624-2
Selection Guide
162445
1624·25
1624·35
Maximum Access Time (ns)
25
35
45
Maximum Operating Current (mA)
500
500
500
Maximum Standby Current (mA)
160
160
160
9-81
CYM1624
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Range
Ambient
Thmperature
Vee
Commercial
O·Cto +70·C
SV:!: 10%
Storage 'Thmperature .••.•.•....•....... -45°C to + 125°C
Ambient 'Thmperature with
Power Applied ..••...••.•.•...•.•.•..• -10·C to +SS·C
Supply Voltage to Ground Potential. . • . . • .• -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State .....•..•....•..•...••... -O.SV to + 7.0V
DC Input Voltage .•...•.....•.••....•... -O.SVto +7.0V
Electrical Characteristics Over the Operating Range
Description
Parameters
CYMl624
'lest Conditions
Min.
\bH
Output mGH Voltage
Vee = Min., IOH = -4.0 rnA
\bL
Output LOW Voltage
Vee = Min., IOL = S.O rnA
'hi
Input mGH Voltage
\fL
Input LOW VoitageJ1J
IIX
Input Load Current
Ioz
Units
Max.
2.4
V
0.4
V
2.2
Vee
V
-0.5
O.S
V
GNDsVlsVee
-20
+20
Output Leakage Current
GND s Vo s Vee, Output Disabled
-20
+10
!LA
!LA
Icc
Vee Operating
Supply Current
Vee = Max., lour = 0 IDA,
"CS < VIL
500
rnA
IsB!
Automatic "CS
Power-Down Current
Vee = Max.,"CS ~ VIH,
Min. Duty cYcle = 100%
160
rnA
SO
rnA
rn
IsB2
rn
Vee = Max.,
~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN s 0.2V
Automatic
Power-Down Current
Capacitance [2J
Parameters
Description
Input Capacitance
CIN
CoUT
Output Capacitance
Notes:
1. VIL(MIN) = - 3.OV for pulse widths less than ZOos.
'lest Conditions
Max.
Units
TA=25·C,f= 1 MHz,
Vee= S.OV
35
pF
15
pF
2. 'Jested on a sample basis.
AC Test Loads and Waveforms
5V:FJ 5V:=F}
4810
OUTPUT
INCLUDING
JIG AND
SCOPE
All Input Pulses
4810
3 . 0 V - - - - , _ - - - - -......1
90%
OUTPUT
~
(a)
30 pF
2550
-=
5 pF
INCLUDING
JIG AND
SCOPE
r -
(b)
2550
GND---'i
s5ns
S5ns
-
1624-3
9-S2
1624-4
---.,..
~ICYPRESS
~,iF'
CYM1624
SEMlCONDUCfOR
SWItc
. h·m~ CharactenstIcs Over the Operating Range []3
1624-25
Parameters
1624-35
1624-45
Units
Description
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACS
CS LOW to Data Valid
35
25
3
3
25
5
tLZCS
CS LOW to Low Z
lHzcs
CS HIGH to High Z
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
5
0
ns
45
ns
30
ns
ns
5
25
0
25
ns
45
3
35
15
[4]
45
35
ns
0
35
ns
45
ns
WRITE CYCLE
twc
Write Cycle Time
25
35
45
ns
tscs
CS LOW to Write End
20
30
35
ns
tAW
Address Set-Up to Write End
20
30
35
ns
tHA
Address Hold from Write End
3
5
5
ns
tSA
Address Set-UI' from Write Start
2
3
5
ns
tpWE
WE Pulse Width
25
35
ns
tSD
Data Set-Up to Write End
20
15
20
20
ns
tHD
Data Hold from Write End
3
5
5
ns
tLZWE
WE HIGH to Low Z
WE LOW to High Z
3
3
2
tHZWE
[4]
0
15
0
15
0
ns
15
ns
eithersignalcan terminate awritebygoingIDGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
6. WE is HIGH for read cycle.
7. Device is continuously selected, CS = VIL8. Address valid prior to or coincident with CS transition low.
9. IfCSgoesHIGHsimuitaneouslywithWEIDGH,theoutputremains
in a high-impedance state.
Switching Wavefonns
Read Cycle No.1 [6,7J
~s 4=
_____ ==-=-=--=--=--=--=---1*____
~ 'M
---j
t_RC
DATA OUT
•
r J)
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of
the specified IOrJIOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) ofAC
Thst Loads. "fransition is measured +500 mV from steady state voltage.
5. TheintemalwritetimeofthememoryisdefmedbytheoveriapofCS
WW and WE LOW. Both signals must be WWto initiate awrite and
PREVIOU~O:TA:ixXXX~========================D=AT=A=V=AU=D====================
1624-5
9-83
U.I
...J
::)
C
o
::i
~~~
CYM1624
~, SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No.2
CS
[6, 8]
IRC
----:!I ~
-"'lr'""
lACS
IHZCS
DATA OUT
-
SUPPLY
CURRENT
HIGH IMPEDANCE
DATAVAUD
t L2cs
----------~-~-%---------------------------------------------~::
-
VCC
1
HIGH IMPEDANCE
I---
t pu
tpD
1624-6
Write Cycle No.1 (WE Controlled)
ADDRESS
--
[5]
IwC
-'l f
..:JEtscs
'\.'\.\ I'\. '\. '\.T
-: ~////
lAW
ISA
IPWE
~'\. V
1 I
Ir
...
DATA IN
"1f-
...
.J
.1
ISD
.1
DATA-IN VAUD
'I
I--DATA OUT
/////////
t HA -
.=!
I HZWE
IHD
I--- 'ItLZWE
--1
HIGH IMPEDANCE
DATA UNDEFINED
1624-7
Write Cycle No.2 (CS Controlled)
ADDRESS
--
[5,9]
twc
-'~
~rISA
Iscs
~
-~
IHA
lAW
IPWE
'\.'\.'\.'\.'\.'\.'\.'\.'\.\."'--\.\.\.\.\.\.\.\.\.\.~Ir
...
.1
DATA IN
'I
DATA OUT
tSD
DATA-IN VALID
14-
tHZWE
-.r-LLLLLLLLLL/ / / /
...
IHD
'I
HIGH IMPEDANCE
DATA UNDEFINED
1624-8
9-84
L~
CYM1624
~_, ~~NDucroR
1hIth Table
CS
WE
H
X
HighZ
Deselect Power-Down
L
H
Data Out
Read
L
L
Data In
Write
Input/Outputs
Mode
Ordering Information
Speed
Ordering Code
Package
1Ype
Operating
Range
Commercial
25
CYM1624PV-25C
PVOl
35
CYM1624PV-35C
PVOl
Commercial
45
CYM1624PV-45C
PVOl
Commercial
Document #: 38-M -00028
II
en
U.l
...J
:::l
C
o
::::E
9-85
CYM1641
CYPRESS
SEMICONDUCTOR
256Kx 16 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of25 ns
The CYMI641 is a high-performance
4-megabit static RAM module organized
as 256K words by 16 bits. This module is
constructed from sixteen 256Kx 1 SRAMs
in leadless chip carriers mounted on a ceramic substrate with pins. Four separate
CS pins are used to control each 4-bit nibbleofthe 16-bitword. This feature permits
the user to configure this module as either
1M x 4, 512Kx 8 or 256Kx 16 organization
through external decoding and appropriate
pairing of the outputs.
Writingto the device is accomplishedwhen
the chip select (CSxx) and write enable
(WEu,L) inputs are both LOW. Data on
• Customer configurable
-x4,xS,x16
• Low active power
-lOW (max.)
• Hermetic SMD tecbnology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .300 in.
• Small PCB footprint
-2.2 sq. in.
the data lines (Ox) is written into the
memory location specified on the address
pins (Ao through A17).
Readingthe device is accomplished by taking the chip select (CSxx) LOW, while
write enable (WEu,L)remainsHIGH.Under these conditions the contents of the
memory location specified on the address
pins will appear on the data lines (Ox).
The data output is in the high-impedance
state when chi~able (CSxx) is HIGH or
write enable (WEu,L) is LOW.
Power is consumed in each 4-bit nibble
only when the appropriate CS is enabled,
thus reducing power in the x4 or x8 mode.
Logic Block Diagram
~-~7
~18~~
Pin Configuration
DIP
__________r -________~ ________- '
Top View
WEL----~r-------~~--------~+--------,
C~-3--~r+------r+~----~~+-----~
C~_7 --~rt------~rt------~rt------~
W~--~--~~4=====~~==~~~-j
C~-11 --,-ri-------r~r-----_,r+1-------,
C~2-15 --~-H~------,._++-------r++--------.
1641-1
1641-2
Selection Guide
1641-25
MaximumAccess Time (ns)
Maximum Operating
Current(mA)
Commercial
MaximumStandby
Current(mA)
Commercial
Military
25
1800
1641-30
30
1641-35
1641-45
1641-55
35
45
1800
1800
1800
560
1800
1800
560
55
1800
560
560
Military
560
560
9-86
1800
560
560
CYMl641
Maximum Ratings
(Above which the useful life may be impaired For user guidelines, not tested.)
Storage Thmperature .•..•...•••••..•• - 65· C to + ISO· C
Output Current into Outputs (LOW) .............. 20 rnA
Ambient Thmperature with
Power Applied .........••.•••....... Supply Voltage to Ground Potential .......
DC Voltage Applied to Outputs
in High Z State ...•......•.....•..•....
DC Input Voltage ......................
Operating Range
55·C to +l25·C
- 0.5V to +7.0V
Range
Commercial
Militaryll]
- O.5V to + 7.0V
- O.5V to + 7.0V
Ambient
Temperature
O·Cto + 70·C
Vee
5V± 10%
- 55·C to + 125·C
5V± 10%
Electrical Characteristics Over the Operating Range
CYMl641
Parameter
Description
Test Conditions
VOH
Output mGH Voltage
Vee = Min., IoH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min.
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
IJX
Input Load Current
Units
0.4
V
V
0.4
2.0
Vee
V
- 0.5
0.8
V
- 80
+80
-10
+10
IlA
IlA
= 0 rnA
1800
rnA
~
= Max., lour = 0 rnA
XX!>. VIL
950
mA
Vee Operating Supply
Current by 4 Mode
~
720
rnA
Automatic~
Max. Vee. ~xx~ Vrn,
Min. Duty Cycle = 100%
560
rnA
GND!>. VI S Vee
Output Leakage Current
GND !>. Vo!>. Vee, Output Disabled
1cc.16
Vee Opera~udc;ly
Current by 16 0 e
~c = Max., lour
lcexs
Vee Operating Supply
Current by 8 Mode
1cc.4
ISB2
Max.
2.4
I IoL = 12.0 rnA I Com'!
I IoL= 8.0 rnA I Mil
loZ
ISBl
Min.
Power·Down Current[2)
c:s-
Automatic
Power-Down Current!2)
XX < VIL
= Max., lour = 0 rnA
XX!>. VIL
C/)
I&J
320
rnA
Capacitance[3)
Parameters
Description
Input Capacitance (Ao - Al7, C:S-, WE)
Input Capacitance (DO - DIS)
Cour
Output Capacitance
Test Conditions
TA = 25·C, f = 1 MHz,
Vee = 5.0V
Max.
150
Units
30
pF
30
pF
pF
Notes,
1. TA is the "instant on· case temperature.
2. A pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vcc power-up, otherwise IsB will exceed val-
3. Thsted initially and after any design or process changes that may affect
these parameters.
uesgiven.
9-87
~
Q
Mas. Vee. C:S-xx ~ Vee - 0.2V
VIN~ Vee - 0.2VorVINsO.2V
CINA
CINB
...J
o
:t
CYM1641
AC Test Loads and Waveforms
RI329Q
(481QMIJ
RI481Q
(48IQMH)
5V31 5V:.TI
I =
0U11'UT
0UlPUT
30pF
AI
~OWD~
JIGAND _
_
SCOPE -
-
~Mm
5pF
_
SCOPE -
-
MIQ
(b)
tHZCS, and tLZCEare specified with CL S pF as in part (b) of
AC Thst Loads. 1tansition is measured ±SOO mV from steady state
voltage.
6.
=
9-93
The internal write time of the memory is dermed by the overlap of CS
LOW andWE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CYM1720
*___
Switching Waveforms
Read Cycle No. 1[7.8]
ADDRESS
~§_-=--=--=--===_tRC_ _ _ _
--f- --1t~AA"1
t OHA
DATA OUT
PREVIOUS DATA VAUO
===================D=AT.=A=V.=AU==D===========
1720-7
Read Cycle No. 2[7,9]
~---------------------tRC ----------------------1.--------------
Vee _ ......___-'1
SUPPLY
CURRENT
ISB
1720-5
Write Cycle No.1 (WE Controlled)[6,10]
!we
ADDRESS
=:){
j~
tscs
~~~
/
tSA
WE
ItIA -
IpwE
".'l~r...
~I{:
IsD
DATA IN
Wffff.10 W/////#
lAw
~(
DATA VALID
-lHzwEj
IHD·
31('
~tuwe-1
HIGH IMPEDANCE
DATAOUT _______D_A_T._A_U_N_D_EF_IN_E_D_______~»-----------< and !t.zcEare specified with CL = 5 pF as in part (b) of
AC'Thst Loads. 1ransition is measured :!:SOO mV from steady state
voltage.
10
0
10
0
15
ns
6. The internal write time of the memo!), is dermed by the overlap of~
LOW andWB LOW. Both signaIs must be LOW to initiate awriteand
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
9-98
1i!il~~
*_
Switching Waveforms
Read Cycle No. 117, 8]
ADDRESS
~§~....---=====_tAC
--1-
CYM173 0
PRELIMINARY
tAAQ'"
__
tOHA----J
DATA OUT
PREVIOUS DATA
====================D=AT=A=V=A=L=ID=============
VAUD
1730-8
Read Cycle No. 2[7,9]
~----------------------
tAC
----------------------~Ir--------------
ICC
Vce
SUPPLY _ ......_____-'\
CURRENT
ISB
1730-6
U>
Write Cycle No.1 (WE Controlled)[6, 10]
LLI
...J
::»
twc
ADDRESS
=:)~
C
""~
o
:t
tses
/W#///h all///&
~~ ~ ~
lAw
tSA
iHA-
tpWE
~'£
~~
!ti~
tso
DATA IN
""(
...
r
DATA VALID
-!tiZWEj
-ItzwE
HIGH IMPEDANCE
-!
DATAOUT __________D_A_TA
__
U_N_D_EF_IN_E_D_ _ _ _ _ _ _-J»----------~(,
_______
1730-7
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL and OE = VIL.
9. Address valid prior to or coincident with CS transition Ww.
10. Data I/O will be high impedance if OE = VIR.
11. IfCS (loes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
9-99
CYM1730
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (~ Controlled)[6, 10, 11]
~-----------------------twc----------------------~
1-+--DATA IN
tso - - -....I--.-f
---------------------JI~r_~--~~----~~-----------
DATA OUT
tHZWEJ
lhIthTable
CS WE OE
HIGH IMPEDANCE
~-------------------1730-9
DATA UNDEFINED
Ordering Information
Input/outputs
Mode
H
X
X
HighZ
DeseJect/Power-Down
L
H
L
Data Out
Read Word
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
Package
Speed
(ns)
Document #: 38-M-00049
9-100
Ordering Code
1YJIe
Operating
Range
25
CYM1730PZ-25C
P'Z1J7
Commercial
30
CYM1730PZ-30C
P'Z1J7
Commercial
35
CYM1730PZ-35C
P'Z1J7
Commercial
CYM1821
CYPRESS
SEMICONDUCTOR
16K X 32 Static RAM Module
Features
Functional Description
• High-density 512-kbit SRAM module
• High-speed CMOS SRAMs
- Access time of 12 ns
The CYM1821 is a high-perfonnance
512-Kbit static RAM module organized as
16K words by 32 bits. This module is constructed from eight 16K x 4 SRAM SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CS],
CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
• Low active power - 4W (max.)
• SMD technology
• TIL-compatible inputs and outputs
• LowprorIIe
- Max. height of .50 in.
• Small PCB footprint
-1.0 sq. in.
• JEDEC-compatiblepinout
• 2V data retention (L version)
• SIMM version socket-compatible with
CYM1831 and CYM1841
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WE) inputs are both LOW.
Data on the input/output pins (I/Ox) is
written into the memory location specified
on the address pins (Ao throughA13).
Logic Block Diagram
Readingthe device is accomplished by taking the chip selects (CSN) LOW, while
write enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(I/Ox).
Thedatainput/outputpinsstayinthe~
impedance state when write enable (WE)
is LOW, or the appropriate chip selects are
HIGH.
lWo pins (PDO and PD1) are used
to identify module memory density in
applications where alternate versions of
the JEDEC standard modules can be interchanged.
Pin Configuration
ZIP
Top View
Ao
-~s
~
~
PDO-GND
PD1-0pen
14
1/0 4 -1/0 7
1/00 -I/Os
GND
PDo
1/0 0
1/°1
1/°2
I/O s
Vee
A7
A8
A9
FtBl
i~g4
CS1
1/0 5
1/0 6
1/08 -1/0 11
1/012 -1/015
CS2
1/016 -1/0 19
1/020 -1/0 23
1/024 -1/0 27
1/028 -I/OSl
CSs
~
( J)
U.I
...J
::l
C
~2
NC
CSl
0
::E
CS4
CSs
NC
GND
1/°16
1/°17
1/°18
1/0 19
A10
All
A12
~
1/°24
1/°25
1/°26
1/°27
As
A4
A5
Vee
A6
l/~lS
110 20
1/0 21
I/O:
GND
CS4
•
i}g:
I/O 10
A 11
AO
Al
2
1/°12
1/0 1S
i}g14
GNCf
i~828
1/0 29
I/O~~
1821-1
1821·2
Selection Guide
1821-45
1821-12
1821-15
1821-20
1821-25
1821-35
MaximumAccess Time (ns)
12
15
20
25
35
45
Maximum Operating Current (rnA)
960
960
720
720
720
720
Maximum Standby Current (rnA)
450
450
160
160
160
160
9-101
g ;r.~NOOcroR
CYM1821
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Commercial
StorageThmperature ................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied.......................... lOOCto +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 0.5V to + 7.0V
Output Current into Outputs (WW) ............... 20 rnA
Electrical Characteristics
Ambient
temperature
Over the Operating Range
VOH
VOL
Vrn
VIL
IIX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND 5. VI 5. Vee
1821-12
1821-15
Min. Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-20
+20
Ioz
Output Leakage Current
GND 5. Va 5. Ven Output Disabled
-20
los
Output Short Circuit
Currentf l ]
Vee = Max., VOUT = GND
lee
Vee Operating Supply
Current
Parameters
Vee
5V± 10%
O°Cto + 70°C
test Conditions
Vee = Min., IOH = -4.0 rnA
Vee = Min.,loL = 8.0 rnA
1821-20
1821-25
1821-35
1821-45
Min. Max.
2.4
0.4
Units
V
V
V
V
2.2
-0.5
-20
Vee
0.8
+20
-20
+20
!JA
!JA
-350
-350
rnA
Ycc = Max., lOUT = 0 rnA,
960
720
rnA
450
160
rnA
160
160
rnA
IISBl
Automatic CS Power-Down
Currentf2]
CSN5. VIL
Max. Vee; CSN ~ Vrn
Min. Duty Cycle = 100%
IISB2
Automatic CS Power-Down
Currentf2]
Max. Vee; CSN ~ Vee - 0.3Y,
VIN > Vee - O.3Vor VIN < O.3V
+20
Capacitance [3]
Parameters
qNB
Description
Input Capacitance (ADDR, OE, WE)
Input Capacitance (CSN)
CoUT
OutputCapacitance
CINA
Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vcc on the CS input is required to keep the
device deselected during Vcc power-up, otherwise ISB will exceed
values given.
test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
3.
9-102
Thsted on a sample basis.
Max.
70
35
20
Units
pF
pF
pF
~
CYM1821
~=CYPRESS
-===S_'
SEMlCONDUcroR
AC Test Loads and Waveforms
~1n
OUTP~~ ~
.~.~:Fl
J 1
_
2ssn
INCLUDING
JIG AND
SCOPE
-
All. INPUT PULSES
~1n
-
3.0V----
OUTP~~ ~
.~ ~:Fl
J 1
_
..
INCLUDING
JIG AND
SCOPE
(a)
90%
GND
255
-
-
(b)
1821-3
!l
1821-4
I
Equivalent to:
THEVENIN EQUIVALENT
167!l
OUTPUT 0---'wIr---0 1.73V
Switching Characteristics Over the Operating Rangel4]
1821-12
Parameters
Description
Max.
Min.
1821-15
Min.
Max.
1821-20
Min.
Max.
Units
20
ns
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
12
20
15
12
15
ns
toHA
Data Hold from AddressChange
tACS
CS WW to Data Valid
12
15
20
ns
tOOE
OE LOW to Data Valid
10
10
10
os
tLZOE
OEWWtoLowZ
tHzOE
OE HIGH to High Z
tLZes
CS LOW to Low Z[5]
tHzes
CS HIGH to High Z[5, 6]
tpu
CS LOW to Power-Up
tpo
CS HIGH to Power-Down
2
3
2
2
2
8
3
8
8
0
8
8
15
ns
os
8
0
0
12
ns
5
3
3
ns
20
ns
en
ns
...J
:)
ns
WRITE cycLEl7J
C
o
:E
20
Write Cycle Time
12
15
tscs
CS WW to Write End
10
12
15
ns
tAW
Address Set-Up to Write End
10
12
15
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
2
ns
tpWE
WE Pulse Width
10
12
15
ns
tso
Data Set-Up to Write End
10
10
10
ns
tHO
Data Hold from Write End
2
2
2
os
tLZWE
WE HIGH to Low Z[S]
3
3
3
tHZWE
WEWWtoHighZ[5,6]
0
twe
w
Notes:
4. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of l.5V, input levels of 0 to 3_0V, and output loading of
the specified IOrJIOH and 30-pF load capacitance.
5_ At any given temperature and voltage condition, IHzcs is less than
tLZCS for any given device. These parameters are gnaranteed and not
100% tested.
6. tHzcsandtHZWEarespecifiedwithCL = SpFasinpart(b)ofACThst
Loads. Transition is measured ±SOO mV from steady state voltage_
7
7.
9-103
0
7
0
ns
n.
7
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going IDGH. The data input
set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
.7l~~croR
CYM1821
Switching Characteristics
Over the Operating Rangef4] (continued)
1821-25
Parameters
Description
Min.
1821-35
Max.
Min.
Max.
1821-45
Min.
Max.
Units
READ CYCLE
2S
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from AddressChange
tACS
CS LOW to Data Valid
tDOE
OE LOW to Data Valid
trzOE
OE LOW to Low Z
tHWE
OE HIGH to High Z
trzcs
CS LOW to Low Z[5]
tHZCS
CS HIGH to High Z[5]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
35
25
3
45
35
3
25
0
30
ns
20
ns
10
15
0
25
ns
ns
20
10
45
3
10
5
ns
25
3
15
ns
3
35
15
3
ns
45
ns
ns
20
ns
0
45
35
ns
WRITECYCLFJ7J
twc
Write Cycle Time
25
35
45
ns
tscs
CS LOW to Write End
20
25
35
ns
tAW
Address Set-Up to Write End
20
25
35
ns
tHA
Address Hold from Write End
2
2
2
ns
2
ns
tSA
Address Set-Up to Write Start
2
2
tPWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
13
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
trzWE
WE HIGH to Low Z15]
3
5
5
tHZWE
WE LOW to High Z15, 6]
0
Data Retention Characteristics
Parameters
7
0
10
15
ns
(L Version Only)
Description
VDR
Vee for Retention Data
ICCDR
tCORIS]
Data Retention Current
tRIS]
luIS]
Operation Recovery Time
Chip Deselect to Data Retention Time
'lest Conditions
fu=2.0Y,
CS~ Vcc - 0.2Y,
VIN ~ Vee - 0.2Y,
or VIN.5. 0.2V
Min.
Max.
Units
8
rnA
2
V
ns
0
tRcl9]
Input LeakageCurrent
ns
10
Notes:
8. Guaranteed, not tested.
ns
0
9.
9-104
tRC = Read Cycle Time.
!JA
=;;
:~
CYM1821
. • CYPRF.SS
_ _F
SEMICONDUCTOR
Data Retention Waveform
DATA RETENTION MODE
Vee
4.5V
"' -______________
\loR ~ 2V
-J
7~ 4.5V
:
-tRl
;;"j\\ \ \ \ \
I
1821-5
*_ _ _ _ _ _
Switching Waveforms [13]
Read Cycle No. d 10, 11]
ADDRESS
DATA OUT
~F,.~~~~~~~~~~~~~~~_t_RC________________
--t=.~~ I
PREVIOUS DATAVAUDEXXmk:========================D=Al:=A=Il=AU=D================
1821-6
Read Cycle No.2 (WE Controlled) [10, 12]
'"'l ....
.
DATA OUT
II
tRC
~ I[-
L&J
...J
~
tLZOE
HIGH IMPEDANCE
_
_ tt LZCS -
SUPPLY
CURRENT
~
'"'l ....
tOOE
C
o
- tHZOE -
tHZCS
HIGH IMPEDANCE
DATAVAUD
----------~-~----------------------------------------------~~~
pu
Vee
(f)
tACS
-t
po
1821-7
Notes:
10_ WE is HIGH for read cycle.
11. Device is continuously selected, CS = VIL and OE = VIL.
12. Address valid prior to or concident with CS transition Ww.
13. est. CS2, CS3, and CS4 are represented by CS in the Switching Characterisics and Switching Waveforms sections.
9-105
==
CYM1821
Switching Waveforms
Write Cycle No.1 (WE Controlled)(7]
ADDRESS
--
lwe
-'f-
~~
L
Iscs
...., ~//// / / / / / / / / /
\.. \.. \ I\..\..\..T
tAW
t HA -
tSA
WE
IPWE
I
DATA IN
...
..
..
-------------------------------------------;!~ ~H~IG~H~IM~PE_DAN~CE~_--=t~---------T\.. \...Jr-
~
L
JJ
tSD
I
I
I
-
DATA OUT
tHD
DATA-IN VALID
-
tHZWE
tLZWE
__
::::)'--k
__
DATA UNDEANED
1821-8
Write Cycle No.2 (CS Controlled)!7, 14]
ADDRESS
--
twe
4~
-'l ~
tSA
tscs
~
-: tL
tHA
tAW
WE
tPWE
\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\..\.."'~
""'l
,./ / / / / / / / / / / / / /
tSD
DATA IN
~
I
DATA OUT
DATA-IN VALID
tHD
~
I
~ tHZWE
HIGH IMPEDANCE
DATA UNDEANED
1821-9
Notes:
14. If CS goesIDGHsimultaneouslywithWEIDGH,the output remains
in a high-impedance state.
9-106
,~PRFS'3
-
~F
CYM1821
SEMICONDUCI'OR
Truth Table
CSN
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Inputs/outputs
Mode
Deselect/Power- Down
Ordering Information
Speed
(os)
12
15
20
25
35
45
Package
1Ype
Operating
Range
CYM1821PM -12C
PM01
Commercial
CYM1821PZ-12C
PZ01
CYM1821PM -15C
PM01
CYM1821PC-15C
PZ01
CYM1821PM -20C
PM01
CYM1821LPM -20C
PM01
CYM1821PZ- 20C
PZ01
Ordering Code
CYM1821LPZ- 20C
PZ01
CYM1821PM -25C
PM01
CYM1821LPM -25C
PM01
CYM1821PZ- 25C
PZ01
CYM1821LPZ-25C
PZ01
CYM1821PM -35C
PM01
CYM1821LPM - 35C
PM01
CYM1821PZ-35C
PZ01
CYM1821LPZ-35C
PZ01
CYM1821PM -45C
PM01
CYM1821LPM -45C
PM01
CYM1821PZ-45C
PZ01
CYM1821LPZ-45C
PZ01
Commercial
Commercial
Commercial
Commercial
•
( /)
U.I
...J
:::)
Commercial
C
o
::E
Document #: 38-M -00015 - D
9-107
CYM1822
CYPRESS
SEMICONDUcrOR
16K x 32 Static RAM Module
with Separate I/O
Features
Functional Description
• High-density 512K-bit SRAM module
• High-speed CMOS SRAMs
- Access time of 12 ns
• Low active power
-5.3W (max.)
• Hermetic SMD technology
• T'fL..compa tible inputs and outputs
The CYM1822 is a high-performance
S12-kbitstatic RAM module organized
as 16Kwords by 32 bits. This module is constructed from eight 16Kx 4 separate I/O
SRAMs in leadless chip carriers mounted on
a ceramic substrate with pins. 1\vo chip selects (CSuand~.J are used to independentlyenable the upper and lower 16-bitdata
words.
Writing to the device is accol.!!£1ished when
the chip selects (Bu and/or CSIJ and write
enable (WE) inputs are both LOW. Data on
the input pins (DIx) is written into the memory location specified on the address pins
(Ao through A 13).
• Low profile
- Max. height of .5Z in.
• Smail PCB footprint
-1.0 sq. in.
• ZV data retention (L version)
Reading the device is accomplished by taking the chip selects (Buand/or Ql) and
output enable (00) LOW, while write enable (WE) remains HIGH. Under these
conditions the contents ofthe memorylocationspecified on the address pinswill appear
on the data output pins (DOx).
The output pins stay in the high-impedance
state when write enable (WE) is LOW, the
appropriate chip selects are HIGH. or OE is
HIGH
Pin Configuration
Logic Block Diagram
VDIP
Ao -
At3'"""71~4--r-----"'----,-----,
~~~4-------T+-------r+------,
DI6
017
80
010
011
DI2
~--~+-----r++-----~;-----.
01 16- Ohl
88
87
86
85
84
83
82
81
GNO
013
DI4
015
~+H--r-++I---'r--;'-t+-r-H-t-'
AD
/12
A4
DI8
DI8
0110
0111
0112
0113
0114
0115
~
~
0116
0117
0118
0119
75
74
73
72
71
70
69
88
67
86
85
64
63
62
0123
All
57
0122
M
AID
A12
0124
0125
1822·1
n
76
61
60
59
59
0120
0121
~L------~4-----~~------~t-----~
L-_ _ _ _.L..-_ _ _ _1 -_ _ _.....L*_" 000 - 00.5
79
78
0126
0127
0126
0129
0130
0131
GNO
5&
55
54
53
52
51
50
49
48
47
48
46
vee
DOD
001
002
000
D04
DD5
D06
007
AI
A3
A5
DD9
D09
0010
0011
0012
0013
0014
0015
tl§l
~
0016
0017
0018
0019
D020
0021
DD22
DD23
A7
A9
All
A13
0024
0025
0028
D027
D028
DD29
DOOO
0001
vee
1822·2
Maximum
Shaded area contains preliminary information.
9-108
~
~~PRESS
~_, SEMICONDUCIOR
CYM1822
Maximum Ratings
Operating Range
(Above which the useful life may be impaired)
Ambient
Thmperature
Range
Storage Temperature. . . . . . . . . . . . . . . . . . .. -65°C to + 150°C
Commercial
Ambient Thmperature with
Power Applied. . . . . . . . . . . . . . . . . . . . . . . .
-55 ° C to + 125 ° C
Military
Vee
0°Cto+70°C
5V± 10%
-55°C to + 125°C
5V± 10%
Supply Voltage to Ground Potential. . . . . . . .. -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .........................
-O.5V to +7.0V
DC Input Voltage.......................
-O.5V to +7.0V
Output Current into Outputs (Low) ................. 20 rnA
Electrical Characteristics Over the Operating Range
Parameters
Description
Thst Conditions
Min.
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Vee
Vee
1822HV·20
1822HV·25
1822HV·35
1822HV-45
1822HV·50
1822HV·12
1822HV·15
= Min., IOH = -4.0 rnA
= Min., IOL = 8.0 rnA
Max.
Min.
2.4
Units
Max.
2.4
0.4
0.4
2.2
-0.5
Vee
0.8
2.2
-0.5
Vee
0.8
V
V
V
V
IIX
Input Load Current
GND 5VI 5 Vee
-20
+20
-20
+20
Ioz
Output Leakage Current
Output Short Circuit
Current [1]
GND 5 Vo 5 Vee, Output Disabled
-20
+20
-20
+20
fAA
fAA
-350
-350
rnA
960
720
rnA
II
450
160
rnA
...J
:::)
-
160
rnA
los
ISBl
Vee Operating
Supplv Current
AutomaticCS
Power.Down Current [2]
ISB2
Automatic CS
Power.Down Current [2]
Icc
..
= Max., VOUT = GND
Vee = Max., lOUT = 0 rnA
Vee
CSL CSu ---------------.~~~________
I--
tLZWE
HIGH IMPEDANCE
1822·11
Write Cycle No.2 (CS Controlled)
[7.14]
twc
ADDRESS ~f-
-
~~
tSA
tscs
-: f-
""'1t"'
tHA
tAW
tPWE
,\,\'\.'\.,\",\,\,\,\,\,\,\,\,\,\,\,\:'\.,\"~ I<-
.1.
,
DATA IN
DATA OUT
tSD
~
DATA INVALID
14--
-: f"/ LLLL/ /
.1
/ / / / / / /
tHO
~
"
t HZWE
HIGH IMPEDANCE
DATA UNDERNED
1822-10
9-113
•
.il~~
CYM1822
Truth Thble
CSu CS{,
H
H
OE
Ordering Information
WE Input/outputs
X
X
HighZ
Mode
Speed
Ordering Code
Deselect/Power-Down
Package
'JYpe
Operating
Range
L
L
L
H DataOuto 31 Read
12
CYM1822HV-12C
HV02
Commercial
H
L
L
H
Data Out 0-15 Read Lower Word
15
CYM1822HV-15C
HV02
L
H
L
H DataOut16 3 Read Upper Word
20
CYM1822HV-20C
HV02
Commercial
Commercial
L
L
X
L
CYMI822LHV-20C
HV02
CYMI822HV-25C
HV02
CYMI822LHV-25C
HV02
H
L
X
L
Data In 0-31
Data In 0-15
L
H
X
L
L
L
H
HighZ
H HighZ
H HighZ
H
L
H
L
H
H
H
Write
25
Write Lower Word
Data In 16 31 Write Upper Word
Deselect
30
Deselect
Deselect
CYMI822HV-30C
HV02
CYM1822LHV-30C
HV02
35
CYMI822HV-35C
HV02
CYM1822LHV-35C
HV02
45
CYM1822HV-45C
HV02
CYM1822LHV-45C
HV02
Document #: 38-M-00016-B
9-114
Commercial
Commercial
Commercial
Commercial
CYM1828
PRELIMINARY
CYPRESS
SEMICONDUCTOR
32K X 32 Static RAM Module
Features
Functional Description
• High-density I-megabit SRAM
module
• ffigb-speed CMOS SRAMs
- Access time of 25 ns
The CYMI828 is a very high performance
I-megabit static RAM module organized
as32K words by32 bits. The module is constructed using four 32K x 8 static RAMs
mounted onto a multilayer ceramic substrate. Four chip selects (CSt, CS2, CS3,
CS4) are used to indepeudentlyenable the
four bytes. Reading or writing can be executedon individual bytes or any combination of multiple bytes through proper use
of selects.
Writing to each byte is accomplished when
the appropriate chip selects (c..'IN) and
write enable (WEN) inputs are both Law.
• "-pin, 1.1-inch-square PGA package
• Low active power
-3.3W (max.)
• Hermetic SMD technology
• TTL-compatible inputs and outputs
• Commercial and military
temperature ranges
Logic Block Diagram
Data on the input/output pins (I/Ox) is
written into the memory location specified
on the address pins (Ao throughA14).
Readingthe device is accomplished bytaking chip selects LOW while write enable
remains HIGH. Under these conditions,
the contents of the memory location specified on the address pins will appear on the
data input/output pins.
The data input/output pins remain in a
high-impedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
Pin Configuration
Top View
12
Ao -
A14 --?''"S---'
OE----,
1/°0- 7
1/°8-15
34
23
45
56
a
vo",O
o vo" 0 WE2 avo,.
a vo" a cs,. avo,.
o vo,. a GNO avo,.
a A,. a vo" a VO'2
a A,. a A,. aCE
A, OAsO
o NC
NC 0
OA"
vo..O
Vee
110..0 cs.O 110.00
110..0 WE:. a 110a00
As
o NC
a WE,
avo,
a vo"
a
Ao
As
a
1/°16-23
1/°24-31
OVO,ONC aVo.
110170 GNOO vo.,O
a
vo,.O 1/0190 vo.oO
1828-1
NC
VOo
a Vee
a cs,
22
As
OAoO
As
a
As
...J
::l
c
a
0
:::E
WEaO Vo..O
vo,.O cs.O V0 220
vo. 0110" 0110.
11
en
LLI
0 A, 0
a
a
a
NC OA'2
•
V02'O vo..O
33
44
55
66
1828-2
Selection Guide
1828-25
1828-30
1828-35
1828-45
1828-55
30
600
35
600
45
55
70
600
600
200
600
200
200
600
200
200
600
200
200
600
600
MaximumOperatingCurrent (rnA)
Commercial
25
600
MaximumStandby Current (rnA)
Military
Commercial
200
MaximumAccess Time (ns)
Military
9-115
1828-70
200
200
PRELIMINARY
Maximum Ratings
CYM1828
Operating Range
(Above which the useful life may be impaired.)
StorageThmperature ................. Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
inHighZState ........................
DCInputVoltage ......................
Range
Commercial
65°Cto +150°C
- O.SV to + 7.0V
Military
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
- 55°Cto +125°C
5V ± 10%
- O.5Vto +7.0V
- O.5Vto +7.0V
Electrical Characteristics Over the Operating Range
1828
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Parameters
VOH
VOL
Vrn
Thst Conditions
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Input LOW Voltage
Input Load Current
Output LeakageCurrent
VIL
IIX
Ioz
Vee = Max., lOUT = 0 rnA,
Vee Operating Supply
Current by 16 Mode
Vee = Max., lOUT = 0 rnA,
Vee Operating Supply
Current by 8 Mode
Vee = Max., lOUT = 0 rnA,
IsB!
Automatic CS Power-Down
Currentl l ]
Max. Vee; CS 2. Vrn,
Min. Duty Cycle = 100%
ISB2
Automatic CS Power-Down
Currentl!]
Max. Vee;CS2. Vee - 0.2Y,
VIN > Vee - 0.2Vor VIN < 0.2V
ICCx!6
IeCx:8
CSN~VIL
Vee
+ 0.3
0.8
+20
+20
600
400
360
230
240
145
200
-20
LVersion
CSN~VIL
2.2
-0.3
-20
LVersion
CSN~VIL
Max.
0.4
GND ~ VI < Vee, Vee = Max.
GND ~ Va ~ Vee, Output Disabled
Vee Operating Supply
Current by 32 Mode
ICCt32
Min.
2.4
LVersion
100
Units
V
V
V
V
JAA
JAA
rnA
rnA
rnA
rnA
rnA
Capacitance [2]
CIN
Description
InputCapacitance
CoUT
Output Capacitance
Parameters
Thst Conditions
TA= 25°C,f= 1 MHz,
Vee=5.0V
Notes:
1. A pull-up resistor to Vcc on the CSN input is required to keep the device deselected during Vcc power-up, otherwise ISB will exceedvalues
2.
Max.
50
20
Units
pF
pF
Thsted on a sample basis.
given.
AC Test Loads and Waveforms
TIR2
4R1 481n
OUTP~~
30 pF
255n
~~g~~NG
OUTP~~
SCOPE
(a)
3.0V---
5nR2
5 pF
255.0.
~~g~~NG
-=-
SCOPE
Equivalent to:
ALL INPUT PULSES
R1481.o.
4(b)
167n
o-----wv----o
GND
-=182~
THEvENIN EQUIVALENT
OUTPUT
90%
1.73V
9-116
1828-4
g;~
PRELIMINARY
~=CYPRESS
~_, SEMICONDUCTOR
CYM1828
Switching Characteristics Over the Operating Range[3]
Parameters
READ CYCLE
tRC
tAA
tOHA
tACS
tDOE
tUOE
tHZOE
tues
tHZCS
WRITECYCLE ;J
twc
tses
tAW
tHA
tSA
tPWE
tSD
tHD
tUWE
tHZWE
Parameters
Description
1828-25
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from AddressChange
CS LOW to Data Valid
OE LOW to Data Valid
OELOWtoLowZ
OE HIGH to High Z
CS LOW to Low ZL4J
CS HIGH to High ZL4, ~J
25
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to LowZL4J
25
20
20
0
0
20
15
0
0
0
WELOWtoHighZl4,~J
Description
1828-30
Min.
Max.
30
25
3
3
15
1828-45
Min.
Max.
30
0
3
25
3
15
30
25
25
0
0
25
20
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
20
15
15
25
3
0
15
3
35
30
17
20
1828 55
Min.
Max.
35
30
30
0
0
25
17
0
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
30
25
15
0
1828-35
Min.
Max.
1828 70
Min.
Max.
Units
READ CYCLE
tRC
tAA
tOHA
tAes
tDOE
tUOE
tHZOE
tues
tHZes
WRITECYCLE 'J
twc
tscs
tAW
tHA
tSA
tpWE
tSD
tHD
tUWE
tHZWE
Read Cycle Time
Address to Data Valid
Data Hold from AddressChange
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to HighZ
CS LOW to LowZl4j
CS HIGH to High zl4, 5 J
45
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Zl4j
WE LOW to High Zl4, 5J
45
40
40
0
0
30
25
0
0
0
3
55
3
45
25
0
3
0
3
25
0
30
55
45
45
0
0
35
30
0
0
0
30
30
70
55
55
0
0
45
40
0
0
0
ns
ns
ns
ns
ns·
3
30
ns
ns
ns
70
35
30
3
30
70
55
30
25
9-117
70
55
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
ns
II
~
.~~~
PRELIMINARY
CYM1828
Data Retention Characteristics (L Version Only)
Parameters
VOR
ICCOR3
tcDR[7]
tR!7]
Description
Vee for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
1828
Min. Max.
2.0
320
0
lest Conditions
CS2 Vee - 0.2V
CS2 Vee - 0.2Y,
VIN 2 Vee - 0.2Y,
or VIN 5 0.2Y, VOR = 3.0V
tRe
Units
V
tJA
ns
ns
Data Retention Wavefonn
DATA RETENTION MODE
' - __________________J
4.5V- '\.
~R ~ 2V
7 I'- 4.5V
_ IR
~R
I
--1
"'H1'\\\\\
1828-5
Switching Wavefonns
Read Cycle No. tl8, 9]
== =i'"'§'"
-~-AU==:=AA-~- = = = =_IRC_.-I-~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ *_DA_I_'_~-A~L1-0- - - - - - - - - - - - - - - - - - -
- P=R-EVl--0=U=SO-DA-=!-2'
HA
1828-5
Read Cycle No. 2[8, 10]
I RC
CSN
---:!r-
....,
...
lACS
-'r
-: ...
- I HZOE -
100E
I 120E
HIGH IMPEDANCE
DATA OUT
IHZCS
L
L
HIGH IMPEDANCE
DATA VALID
cs-
_ 1 12
____j-50%---------------------------------------:1== :~~
_
VCC
SUPPLY
CURRENT
Ipu
-Ipo
1821H
Notes:
3. Thstconditionsassume signal transition timesof5 us or less, timing referencelevelsofl.5V,inputleveIsofOt03.0V,andoutputloadiogofthe
specified IorJIoH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
trzcs for any given device. These parameters are gnaranteed and not
100% tested.
5. tHZCS and tmWEare specified with CL = 5 pF as in part (b) of AC'Thst
Loads. 'Itansition is measured ±5oo mV from steady state voltage.
6. Theintemal write time of the memory is defined by the overlap of CSN
LOW and WEN LOW. Both signals must be LOW to initiate a write,
7.
8.
9.
10.
9-118
and either signal can terminate awrite bygoingIDGH. The data input
set-up and hold timing should be referenced to the risiog edge of the
signal that terminates the write.
Guaranteed, not tested.
WEN is IDGHfor read cycle.
Deviceiscontinuouslyselected,CS = VILand OE = VILAddress valid prior to or coincident with CS transition LOW.
-=-=-.
-. ~
~=CYPRESS
PRELIMINARY
CYM1828
~, SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled) [6, 11]
twe
-
ADDRESS ~ fCSN
-Iftscs
- 'f////
'\'\\ 1,\,\'\T
lAW
ISA
..., F-
T"\. "\...:l~
,
'-
J
,I
tSD
,I
*",
DATA IN
DATAI/O
IPWE
1
WE
'/////////
I HA -
tHD
~
DATA VALID
-------------------------------------------;!~
__~H~IG~H~IM~P=E~=N~C~E ~__«~-------::j----k
-
I---
tHZWE
tLZWE
___
DATA UNDEFINED
1828·8
Write Cycle No.2 (CS Controlled) [6, 11, 12]
IWC
-
ADDRESS ~ f-
~l'tSA
Iscs
-'Ii;"
..,
~
tHA
lAW
tPWE
~. . . . '\"\~'\'\~'\'\"\~'\'\""_\.'\'\"\. . . . ~r
ISD
,I
DATA IN
*'"
DATA VALID
I
DATAI/O
I--
DATA UNDEFINED
Notes:
11. Data I/O will be high impedance ifOE = VIH.
tHZWE
9
, ~/ /
/ / // / / / / / / / /
.1 IHD
*'"
tn
W
...I
;:)
C
o
"
:::liE
HIGH IMPEDANCE
1828-9
12. If CSN goes mOH simultaneously with WEN mOH, the output remains in a high-impedance state.
9-119
•
~ ;V;~DUcroR
PRELIMINARY
Truth Table
c~
OE
WEN
HighZ
H
Mode
Inputs/Outputs
X
X
Deselect/fbwer-Down
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information
Speed
(ns)
Ordering Code
Package
type
Operating
Range
HGOI
HGOI
Commercial
Commercial
25
CYMI828HG-25C
30
CYMI828HG-30C
35
CYMI828HG-35C
CYMI828LHG-35C
HGOI
CYMI828HG-35MB
HGOI
CYMI828LHG-35MB
HGOI
CYMI828HG-45C
HGOI
Commercial
CYMI828LHG-45C
CYMI828HG-45MB
HGOI
HGOI
Military
CYMI828LHG-45MB
HGOI
CYMI828HG-55C
HGOI
CYMI828LHG-55C
HGOI
CYM1828HG-55MB
CYMI828LHG-55MB
HGOI
HGOI
Military
CYMI828HG-70C
CYM1828LHG-70C
HGOI
Commercial
CYMI828HG-70MB
HGOI
CYMI828LHG-70MB
HGOI
45
55
70
Commercial
HGOI
Military
Commercial
HGOI
Military
Document #: 38-M -00042
9-120
CYM1828
CYM1830
CYPRESS
SEMICONDUCTOR
64K X 32 Static RAM
Module
Features
Functional Description
• High-density 2-megabit SRAM module
TheCYM1830isahigh-performance
2-megabitstaticRAMmoduleorganizedas
64Kwordsby32bits. This module is constructed from eight 64Kx4 SRAMs in LCC
packagesmountedonaceramicsubstrate
with pins. Fourchip selects (CSo
CSt ,CS2 and CS3)areusedtoindependentlyenable the four bytes. Two write enables(WEo and WE1)areusedtoindependentIywritetoeitherupperorlower
16-bitwordofRAM.Reading orwriting
can be executed on individual bytes or any
combinationofmultiplebytesthrough
properuseofselectsandwriteenables.
Writing to each byte is accom...£!ishedwhen
the appropriate chipselect (CSx) and write
• High-speed CMOS SRAMs
- Access time of 25 ns
• Independent byte and word controls
• Low active power
-4_8W(max.)
• Hermetic SMD technology
• 1TL-compatible inputs and outputs
• Lowpror.:Je
- Max. height 0(.270 in.
• SmaIl PCB footprint
-1.Ssq.in.
Logic Block Diagram
enable (WEx) inputs are both LOW. Data
on the input/output pins (IIOx) is written
intothememorylocation specified on the
addresspins(AothroughA1S).
Readingthe device isaccomplishedbytakingthechip selects(CSx) LOW,whilewrite
enables(WEx)remainsHIGH. Under these
conditions the contents ofthe memory locationspecifiedontheaddresspinswiIIappear
on the data input/output pins (OOx).
The Data input/output pins stayin the highinlpedancestatewhenwriteenables(WEx)
areWw,ortheappropriatechipselectsare
HIGH.
Pin Configuration
DIP
AO-~5~~1~6-''-----------------------'
WEo--'-~-------------------'
c~--+-~--~------------+-~~
U)
1&1
..I
:»
c~
WE 1
C
---+--L..----------lf__....J
o
--~~~------------------~
:::IE
c~--+-+--L..-------+---lf--....J
c~----~----------~
1830-1
Selection Guide
MaxinlumAccess Tinle (ns)
MaxinlumOperating Current (rnA)
Maxinlum Standby Current (rnA)
Commercial
1830-30
1830-35
1830-45
25
30
35
45
55
880
880
880
880
880
880
880
880
320
320
320
320
320
320
320
320
Military
Commercial
1830-55
1830-25
Military
9-121
.s:~PRFSS
CYMl830
~, SEMlCOlDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines not tested.)
Operating
Storage Thmperature.................... -6SoC to +1S0°C
Ambient Thmperature with
Power Applied........................
Ambient
Thmperature
Vee
O°Cto +70°C
SV± 10%
-SsoC to + 12SoC
SV± 10%
Range
-SsoC to +12SoC
Supply Voltage to Ground Potential. . . . . . . .. -O.5V to + 7.0V
Commercial
DC Voltage Applied to Outputs
inHighZState .........................
Military
-O.5Vto +7.0V
DC Input Voltage.......................
-O.5V to +7.0V
Output Current into Outputs (LOW) ...............
Range
[4]
20 rnA
Electrical Characteristics Over the Operating Range
Parameters
Descripti"n
CYMl830
Thst Conditi"ns
MaX.
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
2.4
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
IJX
Input Load Current
loz
Output Leakage Current
los
Output Short Circuit
Current [1]
Icc
Units
V
0.4
V
Vee
0.8
V
-O.S
GND~VI~VCC
-20
+20
GND ~ Va ~ Vee, Output Disabled
-10
+10
tAA
tAA
Vee = Max., VOUT = GND
-3S0
rnA
Vee Operating Supply
Current by 16 Mode
Vee = Max., lOUT = 0 rnA
880
rnA
ISB1
Automatic CS
Power-Down Current [2]
Max. Vee, CSx ~ VIR
Min. Duty Cycle = 100%
320
rnA
IsB2
Automatic CS
Power-Down Current [2]
Max. Vcc , CSx ~ Vee - 0.3V,
VIN> Vee - O.3Vor VIN < O.3V
160
rnA
CSX~V1L
V
Capacitance [3]
Parameters
Descripti"n
Input Capacitance, Address Pins
CINA
CINB
Input Capacitance, I/O Pins
CoUT
Output Capacitance
Thst Conditions
Max.
TA = 25°C, f = 1 MHz,
Vee =S.OV
90
Units
pF
30
pF
30
pF
Note.:
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed val·
ues given.
3. Thsted initially and after any design or process changes that may af-
1.
fect these parameters.
4. TA is the "instant on" case temperature.
AC Thst Loads and Waveforms
R1 329.0.
OUTP:
R1 329.0.
~(4B1
.o.MIL)
R2
I
INCLUDING
JIG AND
SCOPE
OUTP~~ ~(4B1
.o.MIL)
-=
30pF
-=
I
f~:5.o..o.MIL)
INCLUDING
JIG AND
SCOPE
(a)
-=
3.0V
90%
R2
5pF
-=
f~l5.o..aMIL)
~5ns
1830-8
1830-5
THEVENIN EQUIVALENT
125.0.
167.0.
OUTPUT ~ 1.9OV
OUTPUT ~ 1.73V
Military
GND
(b)
I
Equivalent to:
ALL INPUT PULSES
_ _ _ _-.I
---I~~
9-122
Commercial
4:~PRFSS
~I
CYMl830
SEMICOIDUcrOR
Switching Characteristics Over the Operating Range [5J
1830-25
Parameters
1830-30
Description
Min.
Max.
Min.
Max.
1830-35
Min.
Max.
1830-45
Min.
Max.
1830-55
Min.
Unit
Max.
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid
tOIIA
Output Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z
tHzcs
CS HIGH to High Z
tpU
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
WRITECYCLE
30
25
3
3
25
3
3
15
[6,7]
25
45
20
30
20
0
us
ns
20
ns
55
ns
us
0
45
35
ns
ns
55
3
3
0
ns
55
3
3
3
0
55
45
35
15
0
45
35
30
3
[7]
35
30
[8J
twc
Write Cycle Time
25
30
35
45
55
ns
tscs
CS LOW to Write End
20
25
30
40
40
ns
tAW
Address Set-Up to Write End
20
25
30
40
40
ns
tIIA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
2
2
ns
tpWE
WE Pulse Width
20
25
25
30
40
ns
tSD
Data Set-Up to Write End
15
20
20
25
25
ns
tHD
Data Hold from Write End
2
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
WE LOW to High Z
1
3
3
3
3
[7]
[6,7]
tHZWE
0
15
Note.:
5. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of
the specified IorJIOH and 3O-pF load capacitance.
6. tHZCS and IHZWE are specified with CL = 5 pF as in part (b) of
AC'Iest Loads. Thansition is measured ±500 mV from steady state
voltage.
7. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
8. The internal write time of the memory is defined by the overlap of CS
LOW and WEWW. Both signals must be LOW to initiate awrite and
0
9.
10.
11.
12.
20
0
20
0
20
0
ns
20
ns
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = Vn,
Address valid prior to or coincident with CS transition Ww.
If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Switching Waveforms [10J
Read Cycle No.1
ADDRESS
DATA OUT
[9,10J
=12,-
'M
~
*-==
__
PR~OUSDAT::lxXXX><*~___________D_Al_A_VAU_D_________
1830-7
9-123
•
¥~
.'~CfOR
Switching Waveforms
Read Cycle No.2
CYMl830
(continued)
[9,10J
lAC
~~
....,ItlACS
DATA OUT
~
I--
I
I.
HIGH IMPEDANCE
IHzcs
:1
DATAVAUD
HIGH IMPEDANCE
IlZCS
~lpD
t pu
---
=:j-ICC
~ISB
VCC
SUPPLY
CURRENT
Write Cycle No.1 (WE Controlled)
[8]
lwe
ADDRESS
-If.
-lEtscs
-: ~////
\..\..\ \.. \.. \..T
-I
tSA
IPWe
T\"V ~
1
...
.,
l
..l
:1
tSD
J
DATA IN
DATA-IN VAUD
tHO
'*
·1
1
-------------------------------------------;!~
~H~IG~-H~IM~PE~DAN~CE ~
: :__)
k~---------~ tHZWE
DATA OUT
j////////
tHA-
tAW
-
tLZWE
_____
DATA UNDEFINED
1830-9
Write Cycle No.2 (CS Controlled)
ADDRESS
--
[8, 12J
twe
~f-
-'JftSA
tscs
.....,~
T
tHA
tAW
tPWe
\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"Vr-
...
DATA IN
1
DATA OUT
DATA UNDEFINED
-;
Iso
DATA-IN VAUD
-
tHZWE
f/ / / / / / / / / / / / / /
...
tHO
1
HIGH IMPEDANCE
1830-10
9-124
~
71 ;~PRESS
,
CYMl830
SEMlCONDUCTOR
Truth Table
CSx
WEx
H
X
L
L
Input/outputs
Mode
HighZ
DeselectIPower-Down
H
Data Out
Read
L
Data In
Write
Ordering Information
Speed
Ordering Code
Package
1YPe
Operating
Range
Commercial
25
CYM1830HD-25C
HD06
30
CYM1830HD-30C
HD06
Commercial
35
CYM1830HD-35C
HD06
Commercial
CYM1830HD-35MB
HD06
Mililary
CYM1830HD-45C
HD06
Commercial
CYM1830HD-45MB
HD06
Military
CYM1830HD-55C
HD06
Commercial
CYM1830HD-55MB
HD06
Military
45
55
Document #: 38-M-00017-A
•
9-125
CYM1831
CYPRESS
SEMICONDUcrOR
Features
64Kx 32 Static RAM Module
Readingthe device is accomplished bytaking the chip selects (CSN) LOW and outIlut enable (OE) LOW while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear
on the data input/output pins (I/Ox).
Thedatainput/outputpinsstayin the~
impedance state when write enable (WE)
is LOW or the appropriate chip
selects are HIGH.
1Wo pins (PDO and PD1) are used to
identify module memory density in
applications where alternate versions
of the JEDEC-standard modules can be
interchanged.
Functional Description
• High-density2-Mbit SRAM module
• High-speed CMOS SRAMs
- A£cess time of 20 ns
• Low active power
- 5.3W (max.)
• SMD technology
• TIL-compatible inputs and outputs
• Low profile
- Max. height of .50 in.
• Small PCB footprint
-1.2 sq. in.
• JEDEC-compatiblepinout
The CYM1831 is a high-performance
2-Mbit static RAM module organized as
64K words by 32 bits. This module is constructedfrom eight 64Kx 4 SRAMs in SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CSh
CSz, CS3 and CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WE) inputs are both LOW.
Data on the input/output pins (I/Ox) is
written into the memory locationspecified
on the address pins (Ao throughA1S).
Logic Block Diagram
Pin Configuration
ZIP/SIMM
Top View
PDo-o~en
Ao- A15
OE
PD1-G 0
16
PD~
GND
PD1
Vee
I/Oa
1/0 9
1/0 10
1/0 11
Ao
A1
A2
1/0 12
1/0 0
1/0 1
1/0 2
I/Os
A7
1/0 4 -1/0 7
1/0 0 -I/Os
~a
110 9
1/0 4
1l0 S
CS1
1~§1S
II ~:
I/O~
1/0 8 -1/0 11
1/0 12 -1/0 1S
GS2
1/0 16 -1/0 19
1/0 20 -1/0 23
GND
~
~2
~4
~s
NC
GND
~
1/024
1/0 25
1/0 26
1/0 27
As
A4
As
1/0 16
1~817
GSs
1/0 26 -1/0 31
1/0 24 -1/0 27
GS4
1/0 18
A19
10
A
A11
A12
1S
1/0 20
110
IZ021
Vee
A6
1~8:
IIO~
1831-1
1I0 so
I/OS1
1831-2
GND
Selection Guide
1831-20
1831-25
1831-30
1831-35
25
30
35
45
Maximum Operating Current (rnA)
20
960
720
160
160
720
160
720
Maximum Standby CurrentirnA)_
720
160
Maximum Access Time (ns)
9-126
1831-45
160
CYMl831
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Thmperature ..••••...•....••• - 65· C to +150· C
Output Current into Outpus (LOW) ..•.••.....•••• 20 mA
Ambient Thmperature with
Power Applied .•...•................ Supply Voltage to Ground Potential. . • • • ..
DC Voltage Applied to Outputs
in High Z State ...•...........•.••..•••
DC Input Voltage ........•. , . . . . . . . . ••.
Operating Range
55· C to + 125· C
Ambient
Temperature
- O.SV to + 7.0V
Range
Commercial
- O.SV to + 7.0V
- O.SV to +7.0V
O·Cto + 70·C
Vee
SV:!: 10%
Electrical Characteristics Over the Operating Range
1831-25, 30, 35, 45
1831-20
Parameter
Description
Thst Conditions
VOH
Output mGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
I/X
Input Load Current
Min.
= Min., IOH = - 4.0 mA
Vee = Min., IOL = 8.0 mA
2.4
Vee
Ioz
Output Leakage Current
Vee Operating
Supply Current
Min.
Max.
Units
2.4
0.4
2.2
lee
Max.
Vee
2.2
V
0.4
V
Vee
V
-0.5
0.8
-0.5
0.8
V
GND.s. VI.s. Vee
-20
+20
-20
+20
GND.s. Vo.s. V cc. Output Disabled
-20
+20
-20
tg; = Max., lour = 0 mA
+20
!lA
!lA
960
720
mA
N.s. VIL
=
ISBl
Automatic "CS
Power-Down Current!l)
Vee Max.,"CSN ~ VIH
Min. Duty Cycle 100%
320
320
mA
ISB2
Automatic "CS
Power-Down Current!l)
Vee = Max., "CSN ~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor VIN .s. 0.2V
160
160
mA
=
Capacitancel2)
(/)
Parameters
Description
qNA
CINB
Input Capacitance (Ao - AlS, 'CS,
Input Capacitance (1/00 - I/O:I1)
Cour
Output Capacitance
Thst Conditions
wn. tm)
=
=
TA 25·C, f
Vee S.OV
Notes:
1. A pull-up resistor to Vcc on the ~ input is required to keep the device deselected during V ccpower-up; otherwise Iso will exceed values
2.
= 1 MHz,
Max.
Units
80
pF
15
pF
15
pF
'Thsted on a sample basis.
given.
AC Test Loads and Waveforms
R1481Q
OUTP~j1
30pF
5V31R1481Q
OUTPUT
R2
255Q
INCWDING _
JIG AND -
5pF
_
-
R2
255Q
INCWDING _
JIGAND -
SCOPE
_
-
ALL INPUT PULSES
~ns
SCOPE
(a)
Equivalent to:
II
(b)
1831-3
THEvENIN EaUIVALENT
167Q
OUTPUT o-a--~,.\I\o"---oa 1.73V
9-127
1831-4
IoU
...J
:::»
C
o
:IE
CYM1831
witching Characteristics Over the Operating Rangel31
1831-20
Parameters
Description
READ CYCLE
Read Cycle Time
tRe
Address to Data Valid
tM
Output Hold fromAddress Cltange
1831-15
1831-30
1831-35
1831-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2S
20
3
30
3
3
os
45
35
30
2S
20
35
3
45
os
3
loHA
tACS
~ LOW to Data Valid
20
2S
30
35
45
toos
~ LOW to Data ¥.Ilid
10
15
20
20
30
tLZOS
.~.;;:\.:;:
·4811 ....
. >100':.
9-136
1836-45
- -·_.,~
• CYPRESS
CYMl836
,F SEMICONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 55°Cto +125°C
Ambient Temperaturewith
Power Applied ........................ -lO°Cto +85°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - 0.5Vto +7.0V
DC Input Voltage ...................... - 0.5Vto + 7.0V
Electrical Characteristics
Ambient
lemperature
Range
Commercial
Vee
5V ± 10%
O°Cto + 70°C
Over the Operating Range
CYMI836
Parameter
Description
lest Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min.,IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min.,IoL = 8.0 rnA
Vrn
Input HIGH Voltage
Max.
Units
0.4
V
Vee
V
2.4
2.2
V
VIL
Input LOW Voltage
- 0.5
0.8
V
IJX
Input Load Current
GND.$. VI.$. Vee
- 20
+20
Ioz
Icc
Output LeakageCurrent
GND .$. Vo.$. Vee, Output Disabled
-20
+20
!AA
!AA
Vee Operating Supply Current
Vee = Max., lOUT = rnA, CSN.$. VIL
480
rnA
IsBl
AutomaticCS
Power-DownCurrent[l]
Max. Vee, CSN ~ Vrn,
Min. Duty Cycle = 100%
100
rnA
IsB2
AutomaticCS
Power-DownCurrent[l]
Max. Vee, CSN:2. Vee - 0.2Y,
VIN ~ Vee - 0.2Y, orVIN .$.0.2V
28
rnA
LLI
..J
Capacitance [2]
Parameters
CIN
Description
InputCapacitance
CoUT
Output Capacitance
lest Conditions
'JYp.
33
12
TA = 25°C, f = 1 MHz,
Vec=5.0V
Notes:
1. A pull-up resistor to VC£ on the CS input is required to keep the device deselected during Vc£ power-up, otherwise ISB will exceed valuesgiven.
2.
Max.
40
15
Units
pF
pF
Thsted on a sample basis.
AC Test Loads and Waveforms
5V31·
R1481
Rl481
OUTP~~31
FI
30 P
-=
OUTPUT
5pF
R2
2550
INCLUDING
JIG AND
SCOPE (a)
I-=
INCLUDING
JIG AND
SCOPE (b)
-=
R2
2550
-=
1836-4
Equivalent to:
II
en
THEVENIN EQUIVALENT
16m
OUTPUT 0.0--_""""·---00 1.73V
9-137
,OV~.,.
GND
.,;.5ns'-
10%
I--
re:
10%
.,;.5ns
1836-5
::)
C
o
:IE
1i;:~CfOR
CYMl836
Switching Characteristics OvertheOperatingRangef3)
~:'1~.2'
1836-25
1836-30
1836-35
1836-45
~.;,.
Parameters
Description
READ CYCLE
Read CycleTime
tRC
tM
Address to Data Valid
~~~~: Min. Max. Min. Max. Min. Max. Min. Max. Units
~'~~f
,'<
Yc,
Output Hold from Address Change
tACS
CS LOW to Data Valid
tOOE
OE LOW to Data Valid
••• ?:': 'r~'>
tUOE
OE LOW to Low Z
~';O?
tHZOE
OEHIGHtoHighZ
>.i;:i~. :>.'~.:.:::
tues
CS LOW to Low z(4)
\~~
tHZCS
WRITE CYCLEl6)
5
"20'
'15:
Write Cycle Time
CS LOW to Write End
tAW
Address Set-Up to Write End
tRA
Address Hold from Write End
"':'~b,
tSA
Address Set-Up to Write Start
45
35
5
8
35
10
0
12
0
3
10
ns
45
ns
ns
15
0
11
10
ns
45
5
30
0
r'10
tscs
5
25
'.? "',~
35
30
3
,
twc
30
25
;R~E,. ii{
. •. :)y•. C·2(i;;
taRA
CS HIGH to High Z[4, 5]
25
~'ZCf
12
3
15
ns
18
ns
3
13
15
ns
25
30
35
45
ns
15
18
20
25
ns
15
18
20
25
ns
0
0
0
0
ns
0
0
0
0
ns
18
20
25
ns
10
13
15
20
ns
ns
"
. 15:' I" ....
,. . :'.:.".<"
tpWE
WE Pulse Width
.. ll:~>: .'.iJi,,:;,'·
15
.. il$.'; .;>
tso
DataSet-Up to Write End
',W"
tHO
Data Hold from Write End
() ~
tLZwE
WE HIGH to LowZ[4)
g.
tHZWE
WELOWtoHighZ[4,5)
".
I:;'"
:':0
,8'
ns
ns
"
0
0
0
0
0
0
0
0
0
10
0
15
15
0
0
ns
18
ns
Shaded areas contaIn preliminary mformation.
Data Retention Characteristics Over the Operating Range (L Version Only)
1836
Parameters
VOR
ICCDR
tCDR[7]
tR[7]
DeScription
Vee for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
lest Conditions
Ys:,c= 2.0V,
CE~ Vee - 0.2V,
VIN ~ Vee - 0.2V,
orVIN~0.2V
Min.
2.0
2
0
tRC
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V; input levels of 0 to 3.0V; and output loading of
the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tucs for any given device. These parameters are guaranteed and not
100% tested.
5. tHZcsandtHZWEarespecifiedwithCL=5pFasinpart{b)ofACThst
Loads. 1l:ansition is measured ±500 m V from steady state voltage.
6.
Max.
Units
V
rnA
ns
ns
The internal write time of the memory is defined by the overlap of CS
WW and WE Ww. Both sigualsmust be WW to initiate awrite and
7.
9-138
eithersignalcanterminateawritebygoingIDGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
Guaranteed, not tested.
=-~PRESS
==-
iF
CYM1836
SEMICONDUcrOR
Data Retention Waveform
cs
DATA RETENTION MODE
~...__
Vcc
J::::k
i~-----VO_~_:___2_V____~I'~':"=L
4_.5_V
~""""~"""""~~"""""'~h""""'~""""j/;j,...,...~,....,.f,'--VIH-'"
I
~~~\\
1836-0
Switching Waveforms [8)
Read Cycle No. 1[9, 10)
~--------------------- t RC -----------------------~
ADDRESS
14-------
tAA------------"'~
tOHA ----1-1
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1836-9
Read Cycle No. 2[9, 11)
t RC -----------------------~,,......-------
t Hzes
III
HIGH IMPEDANCE
DATAVAUD
DATA OUT
en
Vee
SUPPLY
CURRENT
lee
_....1._ _ _-'1
ISB
1836-7
Write Cycle No.1 (WE Controlled) [6)
twe
ADDRESS
~K
)K
tscs
CS
~ ~t\
.IW##ffi~
tAW
tHA - - -
tSA
tPWE
~~
)ftso
DATA IN
) I(
DATA VALID
tHO ....
~I(
~ tlZWE-1
HIGH IMPEDANCE
DATAOUT _ _ _ _ _ _ _ _ _D_A_T_A_U_N_D_E_FI_N_ED
_ _ _ _ _ _ _--J)~--------~<~
-tHZWEj
_____
1836-8
Notes:
8. CS1, CSz. CS3. and CS4 are represented by CS in the Switching Characteristics and Switching Waveforms sections.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS = VILand OE = VIL.
11. Address valid prior to or coincident with CS transition LOW.
9-139
LIJ
....I
:::>
C
o
:E
:~
mS.
CYMl836
'5!I!I!Ii!I!iiI= CYPRESS
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 12]
~----------------------- twc----------------------~
ADDRESS
~==~~~~t~~~==
~+---
tso
--~--t
DATA IN
tHZWE])___
DATA UNDEFINED
DATA OUT
~H~IG~H~I~M~P~ED~A~N~C~E~__________
----------------------------------~
1836-10
Notes:
12. IfCS goes IDGH simultaneousiywith WE HIGH, the output remains
in a high-impedance state.
Truth Table
CSN WE
H
X
OE Input/outputs
X
HighZ
Mode
Deselectllbwer-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information
Speed
(ns)
Package
1YPe
Ordering Code
Operating
Range
H2O..
.
CYMl1136PZ~20C
. PZ08 ...
25
CYM183~PJ.~25C
CYM1836PM -25C
PM03
30
CYM1836PZ-25C
eyM1836PJ,...3QC· .
PZ08
pJ02
CYMl836L1'J-+3OC .
P:TQ2
CYM1836PM -30C
•
.PJQ2
CYM1836LPM -30C
PM03
PM03
CYM1836PZ-30C
PZ08
CYM1836LPZ-30C
PZ08
Speed
(ns)
Ordering Code
Package
'JYpe
Operating
Range
35
CYM1836PM-35C
PM03
Commercial
CYM1836LPM -35C
PM03
CYM1836PZ-35C
CYM1836LPZ-35C
PZ08
PZ08
CYM1836PM -45C
CYM1836LPM -45C
PM03
PM03
CYM1836PZ-45C
PZ08
CYM1836LPZ-45C
PZ08
..
Commercial
45
Commercial
Shaded areas contain preliminary information
Document #: 38-M -00050
9-140
Commercial
CYM1838
PRELIMINARY
CYPRESS
SEMICONDUCTOR
128K X 32 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of25 ns
The CYM1838 is a very high performance
4-megabit static RAM module organized
as 128K words by 32 bits. The module is
constructed using four 128x 8 static RAMs
mounted onto a multilayer ceramic substrate. Four chip selects (CSlo CSz, CS3,
CS4) are used to independently enable the
four bytes. Reading or writing can be executed ou individual bytes or anycombination of multiple bytes through proper use
of selects.
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WEN) inputs are both Law.
• 66-pin, 1.I-inch-square PGA package
• Low active power
-4.0W(max.)
• Hermetic SMD technology
• 'ITlrcompatible inputs and outputs
• Commercial and military
temperature ranges
Logic Block Diagram
Data on the input/output pins (IIOx') is
written into the memory location specified
on the address pins (An throughA14).
Readingthe device is accomplished bytaking chip selects LOW while write enable
remains HIGH. Under these conditions,
the contents ofthe memory location specified on the address pins will appear on the
data input/output pins.
The data input/output pins remain in a
high-impedancestate when write enable is
LOW or the appropriate chip selects are
HIGH.
Pin Configuration
PGA
1bpView
12
Ao -
A16 """"7'1~7--'
OE----,
WE1:::::::ti=L~::~
CS1
1/°0-7
34
23
o vo. 0 WE, 0 vo,.
o vo. 0 cs, 0 vo,.
o V010 0 GND 0 1/0'3
o A'3 01/011 0
o A,. o A10 ODE
o A,. OA11 o GND
o A,. o A12 OWE,
o GND 0 Vee OliO?
o vOo 0 cs, 01/0.
o VO, 0 GND 0 VO.
o VO, 0 01/0.
I/O"
1/°8-15
1/°16-23
1/°24 - 31
1838-1
I/o.
11
22
vo,.O
45
Vee
0 vo.,O
vo,.O cs.O vo.oO
•
1/0,.0 WE. 0 vo"O
~
Ovo,.,O vo,.O
A7 0
As
GNDO
~
0 Ao 0
U)
LLl
...I
0 A, 0
0 A, 0
~
0
As
~
o
WEaO 1/0230
~
C
0
:::e
vo,.O cs.0 V0220
V0170 GNDO 1/02,0
vo,.O vo,.O vO,oO
44
33
56
55
1838-2
66
Selection Guide
MaximumAccess Time (ns)
1838-35
1838-25
1838-30
25
30
35
Maximum Operating Current (rnA)
Commercial
720
720
720
Military
Commercial
Military
720
240
240
720
240
240
720
Maximum Standby Current (rnA)
9-141
240
240
CYMl838
PRELIMINARY
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
StorageThmperature ................. Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
inHighZState ........................
DClnputVoltage ......................
Range
Commercial
65°C to +150°C
- 0.5V to + 7.0V
Military
Ambient
'lemperature
O°Cto +70°C
Vee
5V± 10%
- 55°C to +125°C
5V ± 10%
- 0.5Vto +7.0V
- 0.5Vto +7.0V
Electrical Characteristics Over the Operating Range
Parameters
VOH
VOL
Vrn
VIL
IIX
loz
leru2
lec..16
leCx8
IsB!
ISB2
Description
Output HIGH Voltage
Output WWVoltage
Input HIGH Voltage
Input WW Voltage
Input Load Current
Output Leakage Current
'lest Conditions
Vee = Min., IOH = -4.0rnA
Vee = Min., IOL = 8.0 rnA
Vee Operating Supply
Current by 32 Mode
Vee = Max., lOUT = 0 rnA,
CSN Vrn,
Min. Duty Cycle = 100%
LVersion
AutomaticCS Power-Down
Currend1]
Max. Vee; CS > Vee - 0.2Y,
VIN> Vee- (l2VorVIN < 0.2V
LVersion
Min.
2.4
2.2
- 0.3
-10
-10
GND < VI < Vee, Vee = Max.
GND < Va < Vee, Output Disabled
Max.
0.4
6.0
0.8
+10
+10
720
720
480
480
360
360
240
200
40
20
Units
V
V
V
V
!'A
!'A
rnA
rnA
rnA
rnA
rnA
Capacitance [2]
CIN
Description
InputCapacitance
CoUT
Output Capacitance
Parameters
'lest Conditions
TA=25°C,f=IMHz,
Vee = 5.0V
Notes:
1. A pull-up resistor to V cc on the CSN input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
2.
Max.
50
50
Units
pF
pF
Thsted on a sample basis.
AC Test Loads and Waveforms
R1 481n.
R1 481n.
OUTP~~ ~R2 OUTP~~ ~R2
30 pF
j~8~~~NG ~
SCOPE
255 n.
-=
5 pF
j~8~~NG ~
255 n.
ALL INPUT PULSES
3.0V - - - r-9O%--------1
GND
-=
SCOPE
(a)
(b)
1838-3
I
Equivalent to:
THEVENIN EQUIVALENT
167n.
OUTPUT cr--wv--o 1.73V
9-142
1838"
CYM1838
PRELIMINARY
Switching Characteristics
Over the Operating Range!3]
1838-25
Parameters
Description
Min.
Max.
1838-30
Min.
Max.
1838-35
I
Max.
Min.
I
Units
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
tACS
Data Hold from AddressChange
OE LOW to Data Valid
tUOE
OEWWtoLowZ
tHZOE
OE HIGH to High Z
CS WW to Low Zl4j
35
25
3
13
0
35
ns
15
ns
0
10
ns
15
0
CS HIGH to High Zl4, J j
tHZCS
WRITECYCLE 'j
ns
ns
30
12
0
35
3
25
0
ns
30
3
CS WW to Data Valid
tDOE
trzes
30
25
20
ns
20
ns
ns
0
15
18
twe
Write Cycle Time
25
30
35
tscs
CS LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
tSA
tpWE
Address Hold from Write End
0
0
0
ns
Address Set-Up to Write Start
0
0
0
ns
WE Pulse Width
17
21
25
ns
tso
Data Set-Up to Write End
12
13
15
ns
tHO
Data Hold from Write End
WE HIGH to LowZl4j
WE LOW to High Zl4, OJ
2
2
2
ns
0
0
0
tuWE
tHZWE
10
0
0
12
ns
ns
0
15
ns
-
Data Retention Characteristics
UJ
...J
1838
Description
Parameters
Thst Conditions
VOR
Vee for Retention Data
CS > Vcc - 0.2V
ICCOR3
Data RetentionCurrent
tCDR[7]
Chip Deselect to Data Retention Time
CS > Vee - 0.2V,
VIN-> Vee - 0.2V,
or
0.2V, VOR = 3.0V
tR[7]
Operation Recovery Time
\liN.:=:
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
referencelevels of l.SV; input levels of 0 to 3.0V; and output loading of
the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tucs for any given device. These parameters are gnaranteed and not
100% tested.
5. tHZCS and tHZWEare specified with CL = 5 pF as in part (b) of ACThst
Loads. "fransition is measured ±500 m V from steady state voltage.
6.
7.
::)
Min.
Max.
Units
2.0
5.5
V
3000
J.tA
0
ns
tRe
ns
The intemalwrite time of the memory is defmed by the overiap OfCSN
LOW and WEN Ww. Both signals must be WW to initiate a write,
and either signal can terminate a write by going IDGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
Guaranteed, not tested.
Data Retention Waveform
DATA RETENTION MODE
4.SV
'bR ~ 2V
4.SV
1838-5
9-143
•
t/)
Overthe Operating Range (L Version Only)
C
o
:E
fa: >crPRFSS
CYMl838
PRELIMINARY
~, SEMICONDUCI'OR
Switching Waveforms
-*-
Read Cycle No. tl8, 9]
-~<~§I4-----===-tM
'-j_'OC.'
PREVIOU:O:T~======================DA=TA=V=1\LI=D=============
DATA OUT
1838-6
Read Cycle No. 2[8, 10]
CSN
~
tRC
~
..,1'-
.......
SUPPLY
CURRENT
-:1'-
tLZOE
HIGH IMPEDANCE
I--- tLZCS~ tpu
DATA OUT
VCC
tACS
tDOE
1
f--/1
tHZOE -
tHzcs
HIGH IMPEDANCE
DATA VALID
I---
tpD
____j-50%-------------------:t=:~~
1838-7
Write Cycle No.1 (WE Controlled)[6, 11]
ADDRESS
CSN
---
twc
-l ~
-H-
tscs
\.'\.\ l'\.'\.'\.~
~
tSA
DATA IN
tAW
I
~'\.V ~
1
tSD
DATAVAUD
I-- tHZWE
.1
'///////
tHA-
..,
.1 tHO
"*
--"*
tlZWE
-----------------------------------------~~--~H~IG~H~IM~PE=DAN~CE~--=:t--~=::::::
DATA UNDEFINED
::)-----l<...
'I
DATAI/O
tPWE
~////
'I
1838-8
Notes:
8. WEN is mGH for read cycle.
9.
Device is continuously selected, CS
=VILand OE =VII..
10. Address valid prior to or coincident with CS transition LOW.
11. Data I/Owi1l be high impedance ifOE = Vrn.
9-144
·~PRFSS
,
CYMl838
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CS ControUed)[6, 11, 12]
ADDRESS
twc
-
~
..J~
'ftSA
tscs
~
-:1"tHA
tAW
,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\~
...
tPWE
..., 'f// / / / / / / / / / //
tSD
DATA IN
*
DATAVAUD
I
DATAI/O
DATA UNDEFINED
-
t HZWE
tHD
*
I
HI!aH IMPEDANCE
Note:
12. IfCSN goes HIGH simultaneously with WEN IDGH, the output remains in a high-impedance state.
Truth Table
CSN
OE
WEN
H
X
X
HighZ
Deselect/lbwer-Down
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
Mode
Ordering Information
Speed
(ns)
25
30
35
Ordering Code
Package
'JYpe
Operating
Range
Commercial
CYMl838HG-25C
Hool
CYMl838LHG-25C
HOOt
CYM1838HG-25MB
Hoo1
CYM1838LHG-25MB
Hoo1
CYM1838HG-30C
HG01
CYMl838LHG-3OC
HGOt
CYMt838HG-30MB
HOOt
CYMl838LHG-30MB
HOOt
CYMl838HG-35C
HOOt
CYM1838LHG-35C
Hoo1
CYM1838HG-35MB
Hoo1
CYM1838LHG-35MB
Hoo1
Military
Commercial
Military
Commercial
Military
Document#: 38-M-00046-A
9-145
•
CYM1840
PRELIMINARY
CYPRESS
SEMICONDUCTOR
256K X 32 Static RAM
Module
Features
Functional Description
• High-density 8-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
The CYM1840 is a high-performance
8-megabit static RAM module organized
as 256K words by 32 bits. This module is
constructed from eight 256Kx 4 SRAMsin
LCCpackages mounted on a ceramic substrate with pin!:..!'our chip selects (CSo,
CS}, CS2, and CS3) are used to independentlyenable the four bytes. Two write enables (WEo and WEI) are used to independently write to eiilier the upper or
lower 16-bit word of RAM. Reading or
writing can be executed on individual bytes
or on any combination of multiple bytes
through the proper use of selects and write
enables.
Writing to each byte is accol!!Elished when
the appropriate chip select (CSx) and write
• Independent byte and word controls
• Low active power
-6.2W(max.)
• Hermetic SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .290 in. (HD)
• Small PCB footprint
-1.8 sq. in.
Logic Block Diagram
Ao-A7
enable (WEx) inputs are both Law. Data
on the input/output pins (I/Ox) is written
into the memory location specified on the
address pins (Ao through A 17).
Reading the device is accomplished by
taking the chip selects (CSx) Law, while
write enables (WEx) remain HIGH. Under these conditions the contents of the
memory location specified on the address
pins will appear on the data input/output
pins (I/Ox).
The Data input/output pins stay in the
h1g!J:impedancestate when write enables
(WEx) are LOW or the appropriate chip
selects are HIGH.
Pin Configuration
DIP
--~'~6~r---------------------~
WEo ---r~~-------------------'
110,-110 7
c~--+-~--L------------+~~~
CS,----~--~------------------~--~
WE, ---r~~-------------------,
c~--+--r--~-------------+--r-~
CSa ________"'----'--______________---1
1840-1
1840-2
Selection Guide
Maximum Access Time (ns)
Commercial
MaximumOperating
Current(mA)
Military
Commercial
Maximum Standby
Current(mA)
Military
1840-20
20
1120
1840-25
25
1120
1840-30
30
1120
320
320
320
9-146
1840-35
35
1120
1120
320
320
1840-45
45
1120
1120
320
320
1840-55
55
1120
1120
320
320
~
~~PRF.SS
~, fiEMICONDUCTOR
PRELIMINARY
CYM1840
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
not tested.)
StorageThmperature ................. - 65°Cto +150°C
Ambient Temperaturewith
PowerApplied(HD) .................. - 55°Cto +125°C
Ambient Thmperaturewith
Power Applied (PO) ................... - lOoC to +85°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... - O.5Vto +7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
DC ProgramVoitage .............................. 14.0V
Static Discharge Voltage. . . . . . . . .. .. . .. .. . . . .. . . >2001V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................ >200rnA
UVExposure . . . . . ... . . . . . . . .. .. . . . .. . . .. 7258Wsec/cm2
Operating Range
Range
Commercial
Military!l]
Ambient
Thmperature
O°Cto +70°C
Vee
5V± 10%
- 55°C to +125°C
5V± 10%
Electrical Characteristics
Parameter
Over the Operating Range
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Min.
Max.
Units
0.4
V
V
2.4
V
Vrn
Input HIGH Voltage
2.2
Vee
VIL
Input WW Voltage
- 0.5
0.8
V
IIX
Input Load Current
GNDS VI SVee
- 20
+20
flA
Ioz
Output LeakageCurrent
GNDS VoS Vee,
Output Disabled
-50
+50
flA
lee
Vee Operating Supply
Current by 16 Mode
Vee = Max., lOUT = 0 rnA,
CSxS VIL
1120
rnA
ISB1
AutomaticCS
Power-DownCurrend2]
Max. Vee, CSx~ Vrn,
Min. Duty Cycle = 100%
320
rnA
ISBl
Automatic CS
Power-DownCurrent!2]
Max. Vee, CSx ~ Vee - 0.3v,
VIN ~ Vee - O.3VorVIN SO.3V
160
rnA
en
LLI
...I
::»
C
o
Capacitance (3]
Parameters
II
CINA
CINB
Description
Input Capacitance, Address Pins
Input Capacitance, I/O Pins
CoUT
Output Capacitance
'lest Conditions
TA=25°C,f=lMHz,
Vee=5.0V
Max.
100
30
Units
pF
30
pF
pF
Notes:
1. TA is the c'instant on" case temperature.
2.. A pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vccpower-up, otherwise ISBwiII exceed values
3.
given.
9-147
'Thsted initially and after any design or process changes that may affect
these parameters.
::E
.7,~~R
PRELIMINARY
CYM1840
AC Test Loads and Waveforms
Rl329.o.
(4BQl1 MI~
Rl329.o.
5V
5V
OUTPUT 0----.,....--+
30PFI
ALL INPUT PULSES
o--_ _-.,;..(480.0._....,MI~
OUTPUTO----"",,--+
5PFI
R2
202.0.
INCLUDING
JIGAND _
SCOPE -
R2
202.0.
INCLUDING
JIGAND _
SCOPE -
1840-4
(b)
(a)
1840-3
Equivalent to:
THEvENIN EQUIVALENT
167.0.
OUTPUT 00---".""...- - - 0 0 1.73V
125.0.
OUTPUT 00---".",,"'---00 1.9OV
Military
Switching Characteristics
Commercial
Over the Operating Rangel4]
1840-20
Parameters
Description
Min.
Max.
1840-25
Min.
Max.
1840-30
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
taHA
Output Hold from AddressChange
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z[5]
tHZCS
CS HIGH to High Z[5,6]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
20
30
25
20
5
5
20
5
5
5
0
5
20
0
20
ns
ns
20
0
ns
ns
30
25
ns
ns
30
25
20
ns
30
25
ns
WRITE cycLEl7J
twc
Write Cycle Time
20
25
30
ns
tscs
CS LOW to Write End
18
20
25
ns
tAW
Address Set-Up to Write End
18
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tPWE
WE Pulse Width
15
20
25
ns
tSD
DataSet-Up to Write End
13
15
15
ns
tHO
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z[5]
0
0
0
tHZWE
WE LOW to High Z[5,5]
0
Note.:
4. Thst conditions assume signal transition time of S DS or less, timing refereDce levels of l.Sv, input levels of 0 to 3.0V, and output loading of
the specified IOrJIOH and 30-pF load capacitance.
S. At any given temperature and voltage condition, lHzcs is less than
tLZCS for any given device.
6. tHZCS and lHzWE are specified with CL = S pF as in part (b) ofACThst
Loads. 1l:ansition is measured ± SOO mV from steady state voltage.
15
0
15
0
ns
15
ns
7. The internal write time of the memory is defmed by the overlap of CS
LOWandWELOW. Both signals must be WW to initiate awrite and
eithersignalcanterrninateawritebygningIDGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
9-148
-~PR£SS
~,
PRELIMINARY
CYM1840
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel4] (continued)
1840-35
Parameters
Min.
Description
Max.
1840-45
Min.
1840-55
Max.
Min.
Max.
Units
READ CYCLE
35
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from AddressChange
tACS
CS WW to Data Valid
tLZCS
CS LOW to Low Z[5]
tHZCS
CS HIGH to High Z[5,6]
tpu
CS WW to Power-Up
tpo
CS HIGH to Power-Down
45
5
55
5
5
5
25
0
55
55
5
35
ns
ns
25
25
0
ns
ns
45
35
5
ns
45
35
ns
ns
0
45
55
ns
WRITECYCLEl7J
twc
Write Cycle Time
35
45
55
ns
tscs
CS LOW to Write End
30
40
50
ns
tAW
Address Set-Up to Write End
30
40
50
ns
tRA
Address Hold from Write End
6
6
6
ns
tSA
Address Set-Up to Write Start
6
6
6
ns
tpWE
WE Pulse Width
25
30
40
ns
tso
Data Set-Up to Write End
25
30
35
ns
tHO
Data Hold from Write End
6
6
6
ns
tLZWE
WE HIGH to Low Z[5]
0
0
0
tHZWE
WE WW to High Z[5,6]
0
25
0
25
ns
25
0
ns
Switching Waveforms [8]
Read Cycle No. 1[8,9]
IRC
)
ADDRESS
*
(
lAA
I---IoHA~
PREVIOUS DATA VALID
)l(XX~ {
DATA OUT
DATA VALID
1840-5
Read Cycle No. 2[8,9]
ITS
tRC
~"
tACS
DATA OUT
HIGH IMPEDANCE
////
ILZCS
'-""
DATA VALID
~~=d
/
-lpD
_tpu
HIGH
IMPEDANCE
~ICC
I
50%~SB
1840-6
Notes:
8.
Device is continuously selected, CS = VIL.
9.
9-149
WE is HIGH for read cycle.
.r.~~cr)R
CYMl840
PRELIMINARY
Switching Waveforms [8] (continued)
Write Cycle No.1 (WE ControUed)[7]
twc
ADDRESS
~t'
~
Iscs
/~ ~
~ ~ t\..
tAW
tHA-
tSA
tPWE
~~
/'{:
Iso
~t'
DATA IN
tHO .....
----------------~)
I-- tLZWE
-tHZWE
DATA OUT
)K
DATA-IN VALID
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
DATA UNDEFINED
-
HIGH IMPEDANCE1,......---1840-7
Write Cycle No.2 (CS Controlled)l1,lO]
~.~----------------------twc-------------------------.·
ADDRESS ~___________________________________________________ ~________
----------~-----t~s----~
~·~-------------------~W----------------~~--
14--+------ tso ------.....1DATA VALID
DATA OUT
r
~ZWE -1"-----_
_ _ __
HIGH IMPEDANCE
DATA UNDEFINED
1840-8
Note:
10. HCSgoesHIGHsimultaneousIywithWEHIGH,theoutputremains
in a high-impedance state.
Truth Table
CSx
WEx
H
X
Inputs/Outputs
HighZ
L
H
Data Out
Read
L
L
Data In
Write
Mode
Deselect!R>wer-Down
9-150
.
:~
PRELIMINARY
i;" CYPRESS
"'=!!!!!!!!:,
SEMlCONDUClDR
CYM1840
Ordering Information
Speed
(ns)
20
25
30
35
45
55
Ordering Code
CYM1840PD-2OC
CYM1840PD-25C
CYM1840HD-25C
CYM1840PD-30C
CYM1840HD-30C
CYM1840PD-35C
CYM1840HD-35C
CYM1840HD-35MB
CYM1840PD-45C
CYM1840HD-45C
CYM1840HD-45MB
CYM1840PD-55C
CYM1840HD-55C
CYM1840HD-55MB
Package
'JYpe
Operating
Range
PD06
PD06
HDll
PD06
Commercial
Commercial
HD11
PD06
HDll
HD11
PD06
HDll
HDll
PD06
HDll
HDll
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Document#: 38-M-00040-A
•
(f)
ILl
...I
~
Q
o
::iE
9-151
CYM1841
CYPRESS
SEMICONDUcrOR
256K X 32 Static RAM Module
Features
FUncUonalDe~ption
• Hlgh-denslty 8-megablt SHAM
module
• High-speed CMOS SHAMs
-Access time of20 ns
The CYM1841 is a high-performance
8-megabit static RAM module organized
as 2S6K words by 32 bits. This module is
constructed from eight 2S6Kx4SRAMs in
SO] packages mounted on an epoxy laminate board witJu?ins. Four chip selects
(eSt. ~ 'CS3• ~) are used to independently enable the four bytes. Reading or
writingcanbeexecutedonindividuaIbytes
or any combination of multiple bytes
through proper use of selects.
• Low active power
-5.3W (max.) at 25 DS
• SMD technology
• T1'L-compatlble Inputs and outputs
• Low profile
- Max. height of
.ssln.
• Small PCB rootprint
-1.3 sq. In.
• JEDEC-compatlble pinout
• Available in SIMM or ZIP rormat
Writing to each byte is accoS!lished when
the apprE.e!!ate chipselect (CSN) and write
enable (WE) inputs are both Ww. Data
ontheinput/outputpins(IIOx)iswritten
into the memory location specified on the
address ins
throu A 17 •
Readingthedevice is accomplishedbytakingthe~select~N) WWwhilewrite
enable (WE) remainsHIOH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (IIOx).
The data input/output pins stay at the highimpedance state when write enable is
WW or the appropriate chip selects are
mOHo
1\vo pins (pDoandPDr) are used to identify module memory density in applications
where alternate versions of the mDECstandard modules can be interchanged.
Pin Configuration
Logic Block Diagram
ZIP
~-~7~I~e----'---------------------'
Top View
PDo-GND
PDI-GND
42
Ft8°
6
110 0
~-----r+----------------'
~----r++--------------,
110 21
110
V, 3
____
~~
__-L____________
AI
A2
110 12
~§:6
B
1~§la
1/ ::
~
~2----~~---L-------------+~~~
GND
~2
X!4
~:
110 20 -110 23
~
~ND
10
16
110 24
110 25
110 26
1~817
~3----~rT--~-------------+~r-~
110 Ie
1S
A
AID
110 28 -110 31
110 24 -110 27
110 27
~
~
Vee
A"
A12
1I0~
~4----------~----------------~
1~8g
110 10
Ae
Ag
-+~~~
II0 e
~11
~
110 0 -IIO a
~I
GND
PDI
As
1~§21
1I§26
I~
1/ :
:
110 31
GND
1841-1
1841-2
Selection Guide
1841-20
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
20
1120
480
1841-25
2S
960
480
9-152
1841-30
1841-35
35
1841-45
45
1841-55
30
960
480
960
480
960
480
960
480
5S
':r.~
CYM1841
Maximum Ratings
(Above which the usefullife maybe impaired. For user guidelines,
not tested.)
Operating Range
II
Storage'Thmperature ................. - 55°C to +l25°C
Ambient 'Thmperature with
Power Applied ........•.............. - 10°C to +85°C
Supply Voltage to Ground Potential. . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DC Input Voltage .......•.............. - O.5V to + 7.0V
AmbieDt
Temperature
RaDge
Commercial
Vee
5V± 10%
O°Cto + 70°C
Electrical Characteristics Over the Operating Range
CYMl841
Parameter
DescriptioD
VOH
Output mGH Voltage
VOL
Output WW Voltage
VIH
Input mGH Voltage
MiD.
Thst CoDditioDS
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
UDits
2.4
Vee
2.2
VIL
Input WW Voltage
IIX
Input Load Current
GND.s. VI.s. Vce
Ioz
Output Leakage Current
GND .s. Vo.s. Vce, Output Disabled
V
0.4
V
Vee
V
- 0.5
0.8
V
-16
+16
-10
+10
JAA
JAA
I 25, 30, 35 ns
960
rnA
J 20ns
1120
rnA
Vee Operating Supply
Current
tg;N.s.=Max.,
lOUT =ornA,
VIL
ISBI
Automatic CS
Power-Down Currentl l ]
Max. Vee. CSN ~ VIH,
Min. Duty Cycle 100%
480
rnA
ISB2
Automatic CS
Power-Down Current[2]
Max. Vee, CSN ~ Vce - 0.2Y,
16
rnA
Ice
=
VIN ~ Vce - 0.2Y, or VIN .s. 0.2V
::)
Parameters
CIN
Description
Input Capacitance
CoUT
Output Capacitance
Thst CoDditioDs
TA = 25°C, f
Vee = 5.0V
Notes:
1 A pull-up resistor to V cc on the CS input is required to keep the device deselected during V cc power-up, otherwise IsB will exceed valuesgiven.
2.
= 1 MHz,
Max.
Units
70
pF
pF
20
R1481
Thsted on a sample basis.
R1481
OUTP~~~
I
INCLUDING _
JIG AND -
SCOPE (a)
R2
255C
_
-
5V~
OUTPUT
5pF
R2
255Q
INCLUDING
JIG AND ":"
"':::11'"
GND
,$5n6
10%
I-
":"
SCOPE (b)
1841-3
THE:VENIN EQUIVALENT
167C
OUTPUT 0.0--.....-111"'110----o01.73V
9-153
C
o
:iE
AC Test Loads and Waveforms
Equivalent to:
en
LI.I
..oJ
Capacitance[2]
30pF
•
1841-4
CYM1841
Switching Characteristics Over the Operating Range(3)
1841-20
Parameters
Description
Min.
READ CYCLE
Read Cycle TIme
tRC
Max.
1841-25
Min.
Max.
25
20
1841-30
Min.
Max.
30
Units
os
tAA
Address to Data Valid
tOIIA
Output Hold from Address Change
tACS
rn WW to Data Valid
20
25
30
os
tOOE
'OE WW to Data Valid
13
15
20
lIS
tLZOE
tHZOE
tm ww to Low Z
tm mGH to High Z
15
os
tLZCS
rn WW to Low z[41
tHZCS
~ HIGH
tpD
~ mGH to Power Down
25
20
5
5
15
10
10
to High Zl4.51
0
15
os
os
5
0
0
30
lIS
10
os
20
20
20
os
20
25
30
ns
WRITE CYCLE 6)
twc
Write Cycle Time
20
25
30
tscs
~ WW to Write End
18
20
25
lIS
tAW
Address Set-Up to Write End
18
20
25
os
tIIA
Address Hold from Write End
0
0
0
os
tSA
Address Set-Up to Write Start
2
2
2
lIS
tpWE
\VB Pulse Width
15
20
25
os
os
tSD
Data Set-Up to Write End
13
15
15
ns
tHO
Data Hold from Write End
2
2
2
os
tLZWE
\VB mGH to Low ZL4)
\VB WW to High Zl4. 51
0
tHZWE
0
0
15
1841-35
Parameters
Description
Min.
READCY<:;LE
Read Cycle TIme
tRC
tAA
Address to Data Valid
tOIIA
Output Hold from Address Change
tACS
rn LOW to Data Valid
Max.
0
1841-45
Min.
5
tm LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tm HIGH to High Z
tLZCS
~ LOW to
tHzcs
rn HIGH to High z[4. 5)
20
tpD
<::S mGH to Power Down
35
25
9-154
os
os
55
35
lIS
lIS
os
0
15
Units
os
55
30
15
10
Max.
5
0
0
os
1841-55
Min.
45
35
15
55
5
tOOE
0
45
35
Low Z(4)
Max.
45
35
os
0
15
15
os
20
20
os
45
55
os
10
10
lIS
~~
~nEMl~
CYM1841
Switching Characteristics Over the Operating Range[3] (continued)
1841-35
Parameters
Description
Min.
Max.
1841-55
1841-45
Min.
Min.
Max.
Max.
Units
WRITE CYCLE[6]
twc
Write Cycle Time
35
45
55
ns
tscs
CS" LOW to Write End
30
40
50
ns
tAW
Address Set-Up to Write End
30
40
50
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpwE
WE Pulse Width
30
35
45
ns
tso
Data Set-Up to Write End
20
25
35
ns
tHO
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z[4]
0
0
0
tHZWE
WE LOW to High z[4, 5]
0
0
0
15
15
ns
15
ns
Data Retention Characteristics Over the Operating Range (L Version Only)
1841
Parameters
VOR
ICCOR
tCOR[7]
tR[7]
Description
Test Conditions
Vcc = 2.0V,
CE~ Vee - 0.2V,
VIN ~ Vee - 0.2V,
or VIN .5. 0.2V
Vee for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes:
3. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of
the specified IOI.}IoH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
5.
Max.
2.0
V
800
0
5
Units
f1A
ns
ns
(f)
U.I
6.
tues for any given device. These parameters are guaranteed and not
100% tested.
tHZCS and tHZWE are speeifiedwith CL = 5pFasinpart(b) ofACThst
Loads. nansilion is measured ±500 mV from steady state voltage.
Min.
The internal write time of the memory is defmed by the overlap of"CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going mOH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
7.
Guaranteed, not tested.
Data Retention Waveform
DATA RETENTION MOOE
4.5V
9-155
-I
::::I
C
o
:::!E
CYM1841
Switching Waveformsl8)
Read Cycle No.; 119. 10)
~--------------------t~ ----------------------~
ADDRESS
DATA OUT
DATAVAUD
1841-8
Read Cycle No.; 2[9. 11)
~-------------------- t~ --------------------~I,_------------
DATA OUT
tHzcs
HIGH IMPEDANCE
DATAYAUD
Vee __
SUPPLY
CURRENT
~
______
~
1841-6
Write Cycle No.1 (WE CoDtrolled)[6)
twe
ADDRESS :=)~
j~
tscs
~ ~ l\.
.IWffff~ V//////#
tSA
IHA-
lAw
tr>wE
~~
DATA IN
-"ftso
DATAVAUD
~I(
::i
ltio ...
~r
--j
I- tuwE
HIGH IMPEDANCE
DATAOUT _______________
DA_~_A_U_N_D_E_R_N_ED_______________J»--------------~(,
I--ltiZWE
_________
1841-7
Notes:
8. t:!S1. CS"20 CSl. and CS"4 are represented by CS" in the Switching Characteristics and Switching Wavefonns sectiOns.
9. WE is HIGH for read cycle.
10. Device is continuously selected. CS" = VIL and OE =VIl..
11. Address valid prior to or coincident with t:!S transition LOW.
9-156
CYM1841
Switching Waveforms (continued)
Write Cycle No. 2 (~ Controlled)[6. 12)
~----------------------- Iwc----------------------~
ADDRESS
____________________
DATA IN
DATA OUT
-J~~----~~----~,-----------
tHZWEJ•___
____________
H~I~G~H_IM_P_E_DAN~C_E
DATA UNDEFINED
-------------------------------
1841-9
Noles:
12. If~ goes IDOHsimuitaneouslywilh WEIDOH.lhe output remains
in a high-impedance state.
'ftuth Table
~N WE em Input/Outputs
H
X
L
L
L
Mode
X
HighZ
Deselect/Power-Down
H
L
Data Out
Read
L
X
Data In
WrIte
H
H
HighZ
Deselect
II
U)
UJ
...J
;:)
Ordering Information
Speed
(ns)
Ordering Code
20
CYM1841PM -WC
25
30
35
Q
Package
1Ype
Operating
Range
Speed
(ns)
PM02
Commercial
35
Ordering Code
Package
'JYpe
Operating
Range
CYMl841LPN-35C
PN02
Commercial
PZ03
CYM1841PN -20C
PN02
CYM1841PZ-35C
CYM1841PZ-20C
PZOJ
CYM1841LPZ-35C
PZ03
CYM1841PM -25C
PM02
CYM1841PM -45C
PM02
CYM1841PN - 25C
PN02
CYM1841LPM 45C
PM02
CYM1841PN -45C
PN02
CYM1841LPN-45C
PN02
PZ03
Commercial
45
CYM1841PZ-25C
PZ03
CYM1841PM-3OC
PM02
CYM1841LPM -30C
PM02
CYMl841PZ-45C
CYM1841PN-30C
PN02
CYM1841LPZ-45C
PZ03
CYM1841LPN - 30C
PN02
CYM1841PM -55C
PM02
CYM1841PZ-30C
PZOJ
CYM1841LPM-55C
PM02
CYM1841PN -55C
PN02
CYM1841LPN-55C
PN02
Commercial
55
CYM1841LPZ-3OC
PZOJ
CYM1841PM -35C
PM02
CYM1841LPM -35C
PM02
CYM1841PZ-55C
PZ03
CYM1841PN-35C
PN02
CYM1841LPZ-55C
PZ03
Commercial
Document#: 38-M-00031-B
9-157
Commercial
Commercial
o
:E
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications. PRELIMINARY
CYPRESS
SEMICONDUCTOR
16K X 68 SRAM Module
Features
Functional Description
• Hlgb-denslty I.megablt SHAM module
• Hlgb.speed CMOS SHAMs
-Access time of2! os
The CYM1910 is a very high performance
1-megabit static RAM module organized
as 16K words by 68 bits. This module is
constmcted using seventeen 16Kx 4 static
RAMs in SOJ packages mounted onto an
epoxy laminate board with pins. The
memory is organized as three banks of
16K x 16 and one of 16K x 20, each of
which has its own chip select, write enable,
and output enable signals.
Writing to the module is accomplished
when the appropriate chip select (CS.)
and write enable (WI!,.) inputs are both
LOW. Data on the appropriate input/output pins (I10nn> of the device is written
• Low active power
- lO.4W (max.)
• SMD technology
• Registered address inputs
• Four completely Independent memory
banks
• Small PCB footprint
-1.9 sq. In.
CYM1910
into the memory location specified by the
content of the address register. The address register is loaded on the rising edge
of the clock signal (eLK).
Reading the device is accomplished by taking chip select ~ and output enable
(OE,.) low while WE" remains inactive or
mOHo Under these conditions, the contents of the memory location specified by
the contents ofthe address register will appear on the appropriate data input/output
pins (I10n o).
The data input/output pins remain in a
high-impedance state when chip select
(CS,.) or output enable (tm,.) is mOH, or
when write enable (WE,.) is LOW.
Logic Block Diagram
Pin Configuration
Plastic VDIP
Top View
OND
lIDo
lID,
!!
~
~
Register
eLK
~--------~---------.
~'--------~----------,
i5E:
CSA----r~1
GND
CIa
110,.
110"
110,.
110,.
01:8.-_ _ _ _ _+-1
WEB------+-I
CS -----------t-L_-1'"
iIO,.
110,.
110"
B
110,.
OND
~
Ao
At
Ao
~c------------~------------,
A"
A,.
~'--------~--------,
CSc-----------+----------,
Vee
110..
IiD:M
110..
vo..
11011
110..
110..
110..
110.,
~
GND
~
~
110",
1101/2
va.,
I/Oa
I/O,.
110,.
Ao
Ao
A.
Ao
Ao
A,.
A,.
elK
IiD:M
!lOa.
11017
11088
110..
UEo,-----------t
WEo
_______
110..
CSo------------l-....--.t'
I/O.q
110..
110..
110.,
~
1104,
~
I/04J
VO~
~
~
GND
~
~
110..
11<4.
110"
110..
uo..
110..
~
110..
OND
I/O.q
I/O.q
1910-1
lID84
110..
l1Ooo
IIOao
110..
110..
OND
1910-2
9-158
This is an abbreviated datasheet.
Contact a Cypress representative
for complete specifications. PRELIMINARY
CYPRESS
SEMICONDUCTOR
16K X 68 SRAM Module
Features
Functional Description
• High-density I.megabit SRAM module
The CYM1911 is a very high-performance
1-megabit static RAMmoduleorganized as
16K words by 68 bits. This module is constructed using seventeen 16K x 4 static
RAMs in SOJ packages mounted onto an
epoxy laminate board with pins. The
memory is organized as three banks of 16K
x 16 and one of16Kx20, each of which has
its own chip select, write enable, and output
enable signals.
Writing to the module is accomplished
when the appropriate chip select (CS'x) and
write enable (WBx) inputs are both LOW.
If Latch Enable (ALE) is HIGH, data on
the appropriate input/output pins (1/00 0>
of the device is written into the memory location specified on the address pins (Au
through Ai3). If ALE is LOW; data is writ-
• High.speed CMOS SRAMs
-Access time of25 ns
• Low active power
- lO.4W (max.)
• SMD technology
• Latched address inputs
• Four completely Independent memory
hanks
• Small PCB footprint
-1.9 sq. In.
CYM1911
ten into the address specified by the contents of the address latch. The value in this
latch is updated on the falling edge of ALE.
Reading the device is accomplished by tak~chip select (CS'x) and output. ena~le
(OEx) LOW while
rematns mactlve
or HIGH. If Latch Enable (ALE) is HIGH,
the contents of the memory location
specified on the address pins (~ throu~h
A13)willappearontheappropnatedatamput/outputpins(IJOnn). IfALE is LOW; the
contents of the memory location specified
by the value in the address latchwill appear
on 1/000,
The data input/output pins remain in a
high~impedance state when chip select
(CS'x) or output enable (UI!x) is HIGH, or
when write enable (WBx) is LOW.
mx
Pin Configuration
Logic Block Diagram
Plastic VOIP
~~ 1...2
1. 104..... Vee
.... ~
103
110..
I::
~~: :~I::~:
~::: I~E~:
vo.
vo. I...
ALE
7
8
88 1000 110..
97 ~ 110..
~§ ~o :§~:
utA-----------t-------------,
WEA-----------t----------~
"CSA-----------t---===--,
!!Qo ~ 11
MA I:
I... 1123
tlE..
OND~ 14
C'!Ia,.:= ::
94
F~
1=
:1::
w""
92..... OND
~
110
E 110
....
1=
87 1= 110..
~::2 ~ :I;~:
110,. ~ 21
94 E 110..
110
110',87 ~ 2223
831= 110,.
::
82 E 110,.
IIO
110" :: 17
110,. i= 18
====+1
WEB
utB
"CSB-----------1rL-,~
OND:: 24
89
88
:1::
~
~2: ~ E ::
"0
27
~~::
~--------~---------.
A,,~
.t;:::
~
~--------+---------,
"CSc-----------r--=====_~
30
1iOa7
33
34
35
IIOaa
uo.,.
~~
~
~
L..:...=::::....________--IL--____. . I - _
I/O~
110..
110..
110..
67
::
~
::
38
39
OND
42:
~
~64
::
61
45
60
110..
48
59
00.7
47
58
110...... 48
57
~ 49
58
l1Ooo I... so 55
1190,
51
54
Vee
~
va..
uo..
9-159
E
~:E ~ll
IiOa7
73
72
71
70
110..
~
1911·1
77100."0
76
A,.
!=
~
110.,
OND
~
110..
!IOta
110.7
110..
110..
110..
110,.
110..
OND 1911.2
II
U)
LLI
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:»
C
o
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CYM4210
CYM4220
CYPRESS
SEMICONDUCTOR
Cascadeable 8K X 9 FIFO
Cascade able 16K X 9 FIFO
Features
Functional Description
• 8Kx9FIFObutTermemory(4210)
or 16K x 9 FIFO buffer memory
(4220)
The CYM4210 is afirst-in frrst-out (FIFO)
memory module that is 8,192 words by 9
bits wide. The CYM4220 is 16,384 words
by 9 bits wide. Each is offered in a600-milwide DIP package. Each FIFO memory is
organized such that the data is read in the
same sequential order that it was written.
Full and empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate
unlimited expansion in width, depth, or
both. The depth expansion technique
steers the control signals from one deviceto
another in parallel, thus eliminating the
• Asynchronous read/write
• High-speed 2S-MHz read/wrlte
• Pin-compatible with 7C42X series of
monolithicFIFOs
• Low operating power
- Icc (max.) =S40 mA (commercial)
• 600-mil DIP package
• Emp~ full nags
• Small PCB footprint
- 0.88 sq. in.
serial addition of propagation delays so
that throughput is not reduced. Data is
steered in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
25 MHz. ~writeoperationoccurswhen
the write ("{l signal is LOW. Read occurs
when read (R) goes LOW. The 9 data outp"uts go to the high-impedance state when
RisHIGH.
In the depth expansion configuration the
(XO) pin provides the expansion outinformation that is used to tell the next FIFO
that it will be activated.
• Expandable in depth and width
Logic Block Diagram
Vi
DO-8
=======c:::;j
Pin Configuration
~-------------------m
Vi
RI-,.-----------___ R
7'6'W9
r------------V 00-8
7C433
FF EF
AS IT
I-+--
Vee
DIP
ThpView
W
Ds
D3
D2
D1
Do
Xl
FF
00
01
02
03
Os
GND
4210-2
Mll---===±:::l
I====---IT
~ ------------------~
4210-1
9-160
CYM421 0
CYM4220
Selection Guide
Frequency (MHz)
Access Time (ns)
I Commercial
Maximum ~erating
Current (rnA
I
4210·65
4220·65
12.5
4210·50
4220.50
15.4
30
421040
422040
20
40
50
65
540
540
540
540
640
640
640
4210·30
4220·30
25
Military
Maximum Ratings
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pm28toPin14) ...................... -0.5Vto+7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - O.5V to + 7.0V
Operating Range
Ambient
Temperature
Range
Commercial
Vee
10%
5V~
O°Cto + 70°C
Industrial
- 40°C to + 85°C
Military[l]
- 55°C to + 125°C
~
10%
5V~
10%
5V
Electrical Characteristics Over the Operating Range
Parameters
VOH
Description
Output HIGH Voltage
VOL
V IH [2]
Output LOW Voltage
Input HIGH Voltage
VrL
Input LOW Level
Irx
Input Current
loz
lee
4210
4220
Min. Max.
Test Conditions
Vee
Vee
= Min., IOH = - 20 mA
= Min., IOL = 8.0 rnA
Units
2.4
Com'l
V
0.4
V
Vee
2.0
2.2
- 0.5
Vee
0.8
V
V
V
GND VIH, GND < Vo < Vee
-10
+10
Operating Current
Vee = Max., lOUT = 0 rnA,
fMAX, Outputs Open
MiI/1nd
ISBl
Standby Current
All Inputs = VIH Min., Vee =Max.
fMAX, lOUT = 0 rnA
ISB2
Power-Down Current
AllInputs, Vee - 0.2.s. VrN.s.O.2,
Vee = Max., lOUT = 0, f = 0
Com'l
540
J.tA
rnA
MiIIInd
Com'l
640
rnA
100
rnA
MiI/1nd
120
rnA
Com'l
80
100
rnA
MiI/1nd
rnA
Capacitance
Parameters
Description
Input Capacitance
Output Capacitance
ClN
COUT
Test Conditions
TA = 25°C, f = 1 MHz
Vee = 4.5V
Notes:
1. TA is the "instant on" case temperature.
2.
Max.
Units
30
30
pF
pF
XI must use CMOS levels with VIH'<:' 3.5V (CYM4220 only).
AC Test Loads and Waveforms
0-----_.,
Rl500!l.
5V
OUTPUTo---1"'---+
30pF
INCLUDING
JIG AND
SCOPE
I-=
0-----_.,
R1 SOO!l.
5V
R2
333!l.
5PFI
3.0V~
R2
GND
10%00%
333!l.
INCLUDING
JIGAND _
.sSM
~
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo---1"'---+
THEVENIN EQUIVALENT
(b)
4210-3
2OO!l.
OUTPUT 00--_*",
• ...--_02V
9-161
4210-4
II
en
w
..J
~
C
o
:E
CYM4210
CYM4220
Switching Characteristics Over the Operating Range[3,4, 5)
8pee.-3O
Parameters
Description
tRC
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
tPR
Read Pulse Width
tLZR
Read LOW to Low Z
toVR
Read mGH to Data Valid
tHZR
Read HIGH to High Z
Min. Max.
8pee.-40
Min.
Max.
10
30
3
3
15
50
3
3
10
40
3
3
20
twc
Write Cycle Time
40
tpw
Write Pulse Width
tHWZ
Write HIGH to Low Z
SO
40
10
10
20
0
50
tHO
Data Hold Time
tMRSC
MR Cycle Time
30
10
10
18
0
40
tpMR
MR Pulse Width
30
40
tRMR
K:m: Recovery Time
10
10
tRPW
twpw
Read HIGH to MR mGH
30
40
Write HIGH to K:m: HIGH
30
40
tEFL
MR to EF LOW
40
tFFH
K:m: to PF mGH
tREF
Read LOW to:sF LOW
40
30
tRFF
Read mGH to PF HIGH
30
40
tWEF
Write HIGH to :sF mGH
30
40
tWFF
Write LOW to PF LOW
40
tRAE
Effective Read from Write mGH
30
30
tRPE
Effective Read Pulse Width After
EFHIGH
tWAF
Effective Write from Read mGH
tWPF
Effective Write Pulse Width After
PFmGH
tXOL
Expansion Out LOW Delay from Clock
tXOH
Expansion Out HIGH Delay from aock
twa
Write Recovery Time
tSD
Data Set-Up Time
30
5
65
50
15
50
50
50
40
40
lIS
lIS
lIS
lIS
lIS
lIS
65
15
65
65
lIS
lIS
lIS
80
80
lIS
60
60
lIS
60
lIS
60
lIS
lIS
lIS
60
65
50
50
lIS
lIS
60
65
50
lIS
lIS
50
40
lIS
lIS
lIS
65
50
50
50
50
50
40
lIS
80
65
40
40
30
30
Notes:
3. 'Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOlJIoH and
30-pF load capacitance, as in part ofAC Thst Load and Waveform,
unless otherwise specified.
30
40
30
80
65
15
15
30
10
lIS
lIS
30
65
50
50
30
15
65
3
3
50
15
15
Units
lIS
65
30
25
Max.
80
50
40
30
8pee.-65
Max. Min.
65
SO
40
8pee.-5O
Min.
lIS
lIS
60
60
lIS
lIS
4. tHZR transition is measured at +500 mV from VOL and -500 mV
from VOH. tovR transition is measured at the 1.5V level.1HWZ and
tLZR transition is measured at :1:100 mV from the steady state.
5. tHZR and tDVR use capacitance loading as in part (b> of ACThst Load
and Waveform.
9-162
CYM4210
CYM4220
Switching Waveforms
Aynchronous Read and Write Timing Diagram
i4---ltiZR----.
DATA VALID
DATA VALID
>Wr;=~I~~-i-~/
Do- D8
-------1<1'-
DATA VALID
J»---
~lI--------C<,-___DP;_:T:_A_V_AL_ID_ _
4210-6
Last Write to First Read Full Flag Timing Diagram
FIRST WRITE
LAST WRITE
w
•
tn
4210-5
UJ
...J
::l
C
o
:E
Last Read to First Write Empty Flag Timing Diagram
LAST READ
FIRST READ
w
DATA OLIT
4210-7
9-163
CYM4210
CYM4220
Switching Waveforms (continued)
Master Reset TimiDg Diagram
....- - - - fMRSC[6]
-------~
R. W(1)
4210-8
Empty Flag and Read Bubble-Through Mode Timing Diagram
DATA IN
W
DATA OUT
--;-------;-1(
4210-9
Full Flag and Write Bubble-Through Mode Timing Diagram
ItiD
DATA IN
--+-------------IC
DATA OUT
4210-10
9-164
CYM4210
CYM4220
Switching Waveforms (continued)
Expansion Timing Diagram
w
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
Iso - •
Do - Os
ltio
..:.:.:~
DATA VALID
,-----
READ FROM LAST PHYSICAL
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 1
_ - - _ LOCATION OF DEVICE 2
_--------
4210-11
Noles:
6. tMRSC = tpMR + tRMR.
7. Wand R: ~ VIH for at least twPw or IRPR before the rising edge of
8.
MR
Expansion Out of Device 1 (XlJl) is connected to Expansion In of Device 2 (Xi":z).
tn
U.I
...I
~
C
o
::::s
9-165
CYM4210
CYM4220
Architecture
The CYM4210 FIFO module is an array of 8,192 words of 9 bits
each and is implemented using four2Kx9 monolithic FIFOs. The
CYM4220is an array of16,384 words of9 bits each and is implemented using four 4K x 9 monolithic FIFOs. Each version has full
and empty flags, but since the FIFOs are internally cascaded using
the depth mode, the half full and retransmit features are not available.
w
o
Pinout of the CYM4210 and CYM4220 are compatible with industry standard 28-pin DIP. The functionality is compatible with
monolithic FIFO devices and with other FIFO modules.
Q
CYM4210
CYM4220
]:F4----J
1--+--i~EF
'R'S" - - - - . . J
Resetting the FIFO
Upon power-up, the FIFO must be resetwith a master reset (RR)
cycle. This causes the FIFO to enter the empty condition signified
by the empty flag (m!) beinL.LOW and full flag (PF) resetting to
HIGH. Read (R)andwrite (W) mustbe HIGH tRPW/twpw before
and tRMR after the rising edge ofJ.lR: for a valid reset cycle.
4210-12
Figure 1. Single Device Mode
Writing Data to the FIFO
w
The availability of an empty location is indicated ~ the HIGH
state of the full flag (FF). A falling edge of write (W) initiates a
write cycle. Data appearing at the inputs (Do-Ds) tso before and
tHO after the rising edge of W will be stored sequentially in the
FIFO.
W
o
Q
CYM4210
CYM4220
EF
"4--t--t
The empty flag (m!) LOW to HIGH transition occurs twEF after
the first LOW to HIGH transition on the write clock of an empty
FIFO. The full flag (PF) goes LOW on the falling edge ofW during
the cycle in which the last available location in the FIFO is written,
prohibiting overflow. PF goes HIGH tRFFafter the completion of
a valid read of a full FIFO.
'R'S"
"FE
-T'"""-+---I~
":'
UPPER WORD
Reading Data from the FIFO
XCi
The falling edge of read (it) initiates a read cycle if the empty flag
(ill") is not LOW. Data outputs (OO-OS) are in a high-impedance
condition between read operations (R HIGH), wben the FIFO is
empty, or when the FIFO is in the depth expansion mode but is not
the active device.
o
Q
The falling edge of~ during the last read cycle before the empty
condition triggers a HIGH to LOW transition ofm:', prohibiting
any further read operations until tWEF after a valid write.
Single Device Mocle
4210-13
Single device modeisenteredbyconnectingato ground and connectingXO to XI (see Figure 1).
Figure 2. Width Expansion Mode
Width Expansion Mode
FIFOs can be expanded in width to provide word widths greater
than 9 bits in increments of9 bits. Devices are connected similar to
the single device mode but with control line inputs in common to
all devices. Flag outputs from any device can be monitored (see
Figure 2).
Depth Expansion Mode
~th expansion mode ~ Figure 3) is entered when, during a
lIJR: cycle,expansion out (XO) of one device isconnected to expan-
sionin(Xl) of the next device,withXOofthe last device connected
to XI of the fIrst device. In the depth expansion mode the fIrst load
(F[) input, when grounded, indicates that this part is the fIrst to be
loaded. All other devices must have this pin HIGH. 'lb enable the
correct FIFO,mis pulsed LOWwhen the last physical location of
the previous FIFO is written to and is pulsed LOW again when the
last physical location is read. Only one FIFO is enabled for read
and one is enabled forwrite at any given time. All other devices are
in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths inincrementsof9bits. Whenexpandin~ depth, acomposite PI! and P;P must be created by ORing the FFs together and the
'EFs together.
9-166
CYM4210
CYM4220
.
FF--
w
1
9/
I I
9/
,/
/
D
...
./"
-
XO
CYM4210
CYM4220
.
--
'R
T
I
r----
-
_f[
j~}«
FO[[
....
~
~
~
D
FF'"
...
y
"'
I+w!----=CYM4210
CYM4220
Q
--y
Vc c
..
I-
f[
'::\
~-I
'-------J
--~
...
~
r----
~
r
...
9/
,/
XO
.-
1
I--
j}«
L-L...--
'1m
.
FF r
SA
7')
......
.
II
XO
CYM4210
CYM4220
.~
I-f[
}«
I-
• = FIRST DEVICE
':'
4210-14
Figure 3. Depth Expansion Mode
9-167
CYM4210
CYM4220
Ordering Information
Speed
(ns)
Ordering Code
30
40
50
65
Package
'JYpe
Operating
Range
Speed
(ns)
CYM42l0HD-3OC
HDlO
Commercial
30
CYM42l0HD-4OC
HDlO
Commercial
40
CYM42l0HD-4OMB
HOlO
Militaly
CYM4210HD-5OC
HOlO
Commercial
CYM4210HD-50MB
HOlO
Militmy
CYM4210HD-65C
HDlO
Commercial
CYM4210HD-65MB
HDlO
Militmy
Document #: 38-M -OOO33A
9-168
50
65
CYM4220HD-30C
Package
'lYPe
HD10
Commercial
CYM4220HD-4OC
HDlO
Commercial
CYM4220HD-40MB
HDlO
Militaly
CYM4220HD-50C
HOlO
Commercial
CYM4220HD-50MB
HDlO
Militmy
CYM4220HD-65C
HDlO
Commercial
CYM4220HD-65MB
HOlO
Militaly
Ordering Code
Operating
Range
CYM4241
PRELIMINARY
CYPRESS
SEMICONDUCTOR
64Kx 9 FIFO
Features
Functional Description
• 65,536 x 9 FIFO buffer memory
• Advanced SRAM-based FIFO architecture
• Asynchronous read/write
• High-speed 7.5-MHz read/write independent of width
• Low operating power
- IcC<&>~------------------4241-10
9-173
:IE
PRELIMINARY
CYM4241
Architecture
The CYM4241 RAMFIFO 0)
N+k+l
Early BACK
Real-Tune DS,
No BACK
EarlyDS,
Real-Tune BACK
MBus,
DSGnded
Cntrlr FIFO goes empty
Cntrlr asserts BACK
Cntrlr accepts DATA
Read Action
System asserts DS &
closes SNW by cycle N
Cntrlr asserts BACK,
Error status ignored
Cntrlr asserts DATA,
Error status ignored
See Table 2
See Table 2
N
See Table 2
N
N+k(k> 0)
N+k+l
9-181
II
U>
W
...I
::::»
o
o
==
Read Cycle
N
N+k
N+k+l
CYM7232
CYM7264
ADVANCED INFORMATION
Read transactions with the Real-TIme Data Strobe mode invoked
operate as described in the Real-TIme Bus Acknowledge Read
modes.
Early Data Strobe/Real-Time Bus Acknowledge Mode
Data is accepted one clock cycle after Data Strobe is asserted in
this mode. Bus Acknowledge is asserted in the same cycle in which
the data is accepted (real-time Bus Acknowledge). Referring to
Table 1, the system asserts Data Strobe in cycle N. The FIFO goes
emptyincycleN + k.lftheFIFOisalreadyempty,kisO. The controller asserts Bus Acknowledge and accepts the data in the neXt
cycle (N + k + 1).
Readtransactions with the Early Data Strobe mode invoked operate as descnbed in the Real-TIme Bus Acknowledge Read modes.
MbusMode
DataStrobe is permanently asserted in Mbusmode. The controller
operates as if it were in Early Data Strobe Mode. The system asserts Address Strobe in cycle O. The FIFO goes empty in cycle k. If
the FIFO is already empty, k is O. The controller asserts Bus Acknowledge and accepts the data in the next cycle (k + 1).
Read transactions with the MBus mode invoked operate as described in the Real-TIme Bus AcknowledgeReadmodes.
Real-Time Bus Acknowledge Read Modes
Mode 1 always passes the data through the error correctioncircuitryand includes the error status ofthe data in the Bus Acknowledge
(BACK [2] asserted if the data contains an uncorrectable error).
Referring to Thble 2, the system asserts Data Strobe and the snoop
window closes ~ N. The controller then supplies data to the
bus and asserts BACK in cycle N + k, where k is two or greater. If
the transaction is a burst, subsequent data may be available in the
next cycle or wait states may be inserted depending upon the details of the programmed DRAM timing. Note that since the data
passes through the error correction circuitry, the data and the Bus
Acknowledge may not meet required set-up times to the clock in
highest-speedbus clock systems.
Mode2 always passes the data through the error correction circuitry and includes the error status of the data in the Bus Acknowledge
(BACK [2] asserted if the data contains an uncorrectable error).
Referringto Thble 2, the system asserts Data Strobe and the snoop
window closes b~ N. The controller then supplies data to the
bus and asserts BACK in cycle N + k, where k is three or greater.
Ifthe transaction is aburst, subsequent data maybe available inthe
next cycle or wait states may be inserted depending upon the detailsofthe programmed DRAM timing. Note that since await state
is inserted (k is 3 or greater), the data and the BusAcknowledgeare
asserted early in the cycle and afford maximum set up time to the
clock.
For the Real-TIDle Data Strobe, Early Data Strobe, and Mbus
Modes,read operations are the same. During reads for these three
modes, thecontrollerrespondswith abus acknowledge in the same
cycle in which the data is transferred. There are three Real-TIDle
Read Bus Acknowledge modes: Mode 0, Mode 1, and Mode 2.
Table 2 summarizes the modes. These modes are invoked by programmingthe Command register. Refer to the register descriptionsfor details. The timing for the read modes is illustrated inFigures 1 and2.
CLOCK
BA~KMODEO ~
DATA
Mode 0 is intended to beahigh-performancemodefor high-speed
bus clocks. In this mode, the data bypasses the error correction circuitry and the Bus Acknowledge is asserted as soon as the data becomes available without regard to the error status of the data. Errors are still logged in the status bits. This affords maximum set-up
time for the data and the acknowledge. Referring to Table 2, the
system asserts Data Strobe and the snoop window closes b~
N. The controller then supplies data to the bus and asserts BACK
in cycle N + k, where k is two or greater. If the transaction is a
burst, subsequent data may be available in the next cycle or wait
states may be inserted depending upon the details of the progranunedDRAM timing.
BACKMODE1
DATA
BACKMODE2
~'--~_
~
I
_'__ _'--_ _ __
I
I
DATA
~L_ _ _ _ _ _ __ _
M7232·3
DS ..
I
\~....L-""~""~""""r-""~""-r""~~---
~. . . . . . . .~. . . . . . . .~\
................
I
~
L.!..-1
I
I
~R~ ~I--~--~--~--~'\ I I
BACK
'----1
DATA
I
~
Figure 2. Timing of the Three Real-Time Bus Acknowledge Read
Modes
CLOCK
NORMAL
BACK
r=:::x'--.L-______'--____
I
~~---~~~:~
M7232- 2
Figure 1. Early and Normal Bus Acknowledge Modes for Reads
9-182
·
~
ADVANCED INFORMATION
~ircyPRESS
CYM7232
CYM7264
~.' SEMICONDUCTOR
Thble 2. Real·Time Bus Acknowledge Modes for Reads
Mode
Read Action
Read Cycle
Mode 0, Max BACK setup to clock,
Error status ignored
System asserts DS &
Ooses SNW by cycle N
N
Cntrlr asserts DATA & BACK
DATA not corrected for errors
N+k(k~2)
System asserts DS &
Closes SNW by cycle N
N
Cntrlr asserts DATA & BACK
DATA corrected for errors
N+k(k~2)
System asserts DS &
Closes SNW by cycle N
N
Cntrlr asserts DATA & BACK
DATA corrected for errors
N+k(k~3)
Mode 1, Min BACK setup to clock
Mode 2, Max BACK setup to clock,
Wait states inserted as required
Bus Acknowledges in transformed transactions
DRAM Interface
When a read is transformed, the operation internal to the controller becomes a write. Bus Acknowledge becomes an input and is
used as a data strobe to clock the data into the reflective FIFO on
each data transfer. The controller will treat the data strobe derived
from the incoming bus acknowledge as an early data strobe when
programmed in the early bus acknowledge mode. Otherwise the
controller assumes that the data is aligned with the corresponding
data strobe derived from the incoming bus acknowledge.
When a write is transformed, the operation converts to a read. In
this case, the controller behaves according to the invoked read
mode.
Bus Acknowledge Timing Characteristics
The DRAM array is 128 data bits wide. This dataissubdividedinto
banks: 4 banks of 32 bits each for the 32-bit EDC version and two
banks of 64 bits each for the 64-bit EDC version. Each bank includes the associated error check bits: 7 bits for the 32-bit EDC
version and 8 bits for the 64-bit EDC version. The DRAM array is
dividedin depth into blocks. Each blockmaybe populatedwithdifferent DRAM chip sizes, however, all DRAM chips in a given
block must have the same depth. From one to four blocks may be
populated with DRAM, however there are certain restrictions as
given in other sections.
The DRAM interface consists of a bidirectional data bus for each
DRAM bank, plus a bidirectional bus for the associated error detection and correction check bits. There is also a set of bankassociatedwrite/read control o~ts. The DRAM blocks are controlled by separate RAS and CAS control outputs. There is one
RAS and one CAS for each block. The entire DRAM array is addressed through one set of 12 row/column multiplexed address
lines. The row/column partition is dictated by the DRAM thatpopulates a particular block.
DRAM Interface for the 32-Bit EDC
The Bus Acknowledge control signals are bidirectional and maybe
driven by the controller or another device on the system bus.
Thereforethere are times when no device will be driving this signal
line. At high bus speeds, pull-ups may not be sufficient to guarantee that the Bus Acknowledge line will revert in a sufficiently sbort
time to the deasserted state after the controller has ceased driving
the line. Th guarantee the state of the BACK signal lines at the end
ofa transaction, the controller first drives the outputs HI GH (deasserted) in the first half of the clock cycle in which Bus Acknowledge
is to be deasserted and then three-states these outputs in the secondhalf of this clock cycle. To insure that the BusAcknowledgesignal lines remain in the deasserted state when no device is driving
them for long periods, pull-ups sbould be employed. At the beginning of a transaction cycle, Bus Acknowledgeremains three-stated
until it is to be asserted. Thus in the first acknowledge cycle of a
transaction, BACK becomes driven and asserted at the same time.
BACK continues to be driven until the end of the transaction cycle
and terminates as described above.
Burst Last
Any read or write burst transaction may be terminated prematurely with the assertion of BLST. BLST must be asserted during the
clockcycle in which the last piece of data is transferred. BLST is not
intemaIlypipelined into the DRAM controller's input control register. As a result the set-up time for BLST to the clockwill be greater than the other control signals and it will prove more useful in
slower bus systems (25 MHz and 33 MHz). Systems that require
the data bus t~o three-state in the next cycle must also deassert
Data Strobe (DS) when asserting BLST.
The controller supports an organization of DRAM that is 156 bits
wide (four banks each consisting of 32 bits of data plus 7 error
check bit~d up to four blocks deep. Each block is controlled by
separateRASandCASsignals(RAS[3:0],C~3:0J).EachBankis
controlledby separate read/write signals (R/W[3:0J). The DRAM
address outputs from the controller module consists of a 12-bit
row/column multiplexed bus. This bus is intended to drive a symmetrical set of address driver devices, which in tum drive the
DRAM array address lines. Timing for the RAS and CAS outputs
as well as other DRAM related timing is programmable. Arepresentation of the DRAM organization is shown inFigure 3.
Each square inFigure 3 represents a bankofmemorythatis32data
bits wide plus 7 check bits. A block is a column offour banks totalling 128 data bits wide plus 28 check bits. Each block is controlled
by dedicated RAS and CAS signals. With 12 multiplexed row/column address lines, each bank can be up to 16 megabits deep. The
row/columnaddressmuitiplexingisprogrammable. The controller
supports256K-, IM-, 4M-, and 16M-deep DRAMs.
DRAM Interface for the 64-Bit EDC
Thiscontrollersupports an organization of DRAM that is 144 bits
wide (two banks each consisting of 64 bits of data plus 8 error check
bits) and up to four blocks ~. Each block is controlled by separateRAS and CASsignals(RAS[3:0], CAS[3:0J). Eachbank is con-
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ADVANCED INFORMATION
CYM7232
CYM7264
RAS3 _ _ _ _--,
CAS3
RASf
CAS1 - - - - - - ,
RASO _ _ _ _ _-,
RASO _ _ _ _ _-,
CASO
CASO
DDA[31 :0]
-....::=,'--~
64
EOA[6:0] ----"-j'---I
R/W[O]---~
DDB[31 :0] -~'---I
64
EDB[6:0] ----"-j'---I
R/W[1]
----.J
DDC[31 :0]
--=,'---+1
M7232·5
EOC[6:0] ----"-j'---I
Figure 4. DRAM Configuration for the CYM7264
R/W[2] - - - - I
result. If any of the four compare results, one from each block, are
true, then the controller responds to the memory transaction request by generating DRAM timing signals to the appropriate
block. If there is no valid comparison, the controller remains inactive. This programming therefore positions the main memory in
the system address space. Note that there is no check to assure that
the Block Placement and Block Maskva1ues are consistent.
32
DOO[31 :0] ....._ =t-_-+I
EOD[6:0] .....--..:.~---I~
R/W[3] - - - - I
M7232·4
Figure 3. DRAM Configuration for the CYM7232
DRAM Interface Signals
trolledby~ateread/write signals (RJW[1:0)). Addressoutputs,
CYM7232 - 32-bit EDC
RAS and CAS outputs and DRAM timing is identical to that in the
32-bit EDCversion. A representation of the DRAM organization
is shown in Figure 4.
EachsquareinFigure4representsabankofmemorythatis64data
bits wide plus 8 check bits. A block is a column of two banks totaling 128 data bits wide plus 16 check bits. Each block is controlled
by dedicated RAS and CAS signals. With 12 multiplexed row/columnaddresslines, each bank can be up to 16 megabits deep. As in
the 32-bit EDC version, the row/column address multiplexing is
programmable. The controller supports 256K-, 1M-, 4M-, and
16M-deep DRAMs.
DRAM Block Programming and Address Recognition
The module interface to the DRAM array is made through the signals described below.
DDA[31:0) - Data Bus (Bank 0) DDA[31:0] forms a 32-bit data
bus that is connected to bank 0 in every populated block.
DDB[31:0) - Data Bus (Bank 1) DDB[31:0] forms a 32-bit data
bus that is connected to bank 1 in every populated block.
DDC[31:0) - Data Bus (Bank 2) DDC[31:0] forms a 32-bit data
bus that is connected to bank 2 in every populated block.
DDD[31:0) - Data Bus (Bank 3) DDD[31:0] forms a 32-bit data
bus that is connected to bank 3 in every populated block.
EDA[6:0) - Check Bus (Bank 0) EDA[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDA[31:0].
EDB[6:0) - Check Bus (Bank 1) EDB[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDB[31:0].
EDC[6:0) - Check Bus (Bank 2) EDC[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDC[31:0].
EDD[6:0) - Check Bus (Bank 3) EDD[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDD[31:0].
ADRS[11:0) - Address Bus. ADRS is a 12-bit row/column multiplexed address bus that supplies the address to the DRAM to access the proper 128-bit data word. The multiplexing is programmable for different depths of DRAM.
The DRAM block population is specified through a set of fields in
the Command register. The block population field specifies which
Blocksare populated. For each block there are two fields that specify the address range of the block: the address location of the block
(Block Placement), and the address comparison mask (Block
Mask). The type of DRAM with which the block is populated is
specified by the Population Code. Refer to the registerdescription
for programming details.
The Block Placement fields and the Block Mask fields are used to
generate address compare signals which determine if the main
memory is being addressed from the system bus. Each block comparisonis accomplished by doing a bit by bit exclusive OR of the
contents of the Block Placement register with system bus address.
The bit by bit comparisons are then masked as specified in the
Block Mask register aild fmally combined to produce a compare
RJW[3:0) - Read/write control. RJW[3:0] are ~ read/write controls for the four banks of the DRAM array. R/WO controls read!
write for all blocks of DDA[31:0], RJW1 controls read/write for all
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CYM7264
ADVANCED INFORMATION
SEMlCONDUCIDR
blocks of DDB[31:0hJ~JW2 controls read/write for all blocks of
DDC[31:0j, and RJW3 controls read/write for all blocks of
DDD[31:0j.
RAS[3:0] - These signals are the four RASoutputs to control each
block of the DRAM.
CAS[3:0] - These signals are the four CAS outputs to control each
block of the DRAM.
The address bus, ADRS[1l:0j, RAS[3:0j, CAS[3:0j, and RJW[3:0j
should be connected through a set of drivers to the appropriate
DRAM inputs. The driver configuration is dependent upon the capacitance that must be driven.
The data bus, check bus, and read/write control signals are connected across the DRAM array. DDA[31:0j and EDA[6:0j are
connected to the data I/O of all the Bank 0 DRAMs. The Bank 0
DRAMs are the top row of DRAMs inFigure 3.R/WOisconnected
to the Write Control input of all the Bank 0 DRAMs. DDB[31:0j
and EDB[6:0j are connected to the data I/O of all the Bank 1
DRAMs. The bank 1 DRAMs are the second row of DRAMs.
R/Wl is connected to the Write Control input of all the Bank 1
DRAMs. This connection pattern continues with Banks 2 and 3.
RASO and CASO are connected to the RAS and CASinputsrespectively of all of the DRAMs of Block O. Block 0 is the left column of
DRAMs in the array in Figure 3. Note that each block consists of
BanksO~h 3. Similarly, RASI and CASI are connected to the
RAS and CAS inputs respectively of all of the DRAMs of Block 1.
This connection pattern continues through Block3.
CYM7264 - 64-bit EDC
The module interface to the DRAM array is made through the signalsdescribed below.
DDA[63:0] - Data Bus (Bank 0) DDA[63:0j forms a 64-bit data
bus that is connected to bank 0 in every populated block.
DDB[63:0] - Data Bus (Bank 1) DDB[63:0] forms a 64-bit data
bus that is connected to bank 1 in every populated block.
EDA[7:0] - Check Bus (Bank 0) EDA[7:0] forms an 8-bit error
check bit bus that is associated with the data on DDA[63:0j.
EDB[7:0] - Check Bus (Bank 1) EDB[7:0] forms an 8-bit error
check bit bus that is associated with the data on DDB[ 63:0j.
ADRS[1l:0] - Address Bus. ADRS is a 12-bit row/column multiplexed address bus that supplies the address to the DRAM to access the proper 128-bit data word. The multiplexing is programmabie for different depths of DRAM.
R/W[1:0] - Read/write control. R/W[1:0] are the read/write controls for the two banks of the DRAM..array. R/Wo controls read!
write for all blocks ofDDA[63:0], RJWl controls read/write for all
blocks ofDDB[63:0],
RAS[3:0] -ThesesignalsarethefourRASoutputstocontroleach
block ofthe DRAM.
CAS[3:0] - These signals are the four CAS outputs to control each
block of the DRAM.
The address bus, ADRS[11:0], RAS[3:0j, CAS[3:0], and RJW[I:0]
should be connected through a set of drivers to the appropriate
DRAM inputs. The driver configuration is dependent upon thecapacitancethat must be driven.
The data bus, check bus and read/write control signals are connected across the DRAM array. DDA[64:0] and EDA[7:0] are
connected to the data I/O of all the Bank 0 DRAMs. The Bank 0
DRAMs are the top row of DRAMs inFigure 4. R/Wo is connected
to the Write Control input of all the Bank 0 DRAMs. DDB[63:0]
and EDB[7:Ql are connected to the data I/O of all the Bank 1
DRAMs. RJW[I] is connected to the read /write control inputs of
all of the DRAMs of Bank 1.
RASO and CASO are connected to the RAS and CASinputsrespectively of all of the DRAMs of Block O. Block 0 is the left column of
DRAMs in the array in Figure 4. Note that each block consists of
Bank 0 and Bank 1. Similarly, RASI and CASI are connected to
the RAS and CAS inputs respectively of all of the DRAMs of Block
1.
DRAM Timing
The system bus clock rate determines the DRAM timing through
an internal phase lock loop. The clock mUltipliers can be programmedby the user to select an internal clock of 1, 2, 3, or 4 times
the input system bus clock. Alongwith the multiplier selection, the
appropriate phase lock loop is selected to generate either an
80-MHzor lOO-MHz (or 99-MHz) internal clock. This selection is
shown in Table 3. There are two versions, -Hand -So The - H
version permits the use of the higher clock frequency multiples for
maximumperformance.
'Thble 3. Clock Multiplier Selection and
Required PLL Frequency
Bus
Clock
(MHz)
40
Clock Multiplier
Coding
01 (2x)
50
33
25
00 (2xllx)
10 (3x/2x)
11 (4x/3x)
Phase Lock
Loop
Frequency
(MHz)-H
80
100
99
100
Phase Lock
Loop
Frequency
(MHz)-S
80
50
66
75
The phase lock loops should be operated close to their center frequency to guarantee operation. Therefore, only the bus frequencies listed should be used. Refer to the PLL[I:0] field in the Commandregisterforprogrammingdetails.
DRAM timing is fully programmable through internal registers.
The resolution of the timing is equal to the period of the internal
clock. (This is normally twice the bus clock frequency for 40- and
50-MHz bus speeds.) The parameters listed in Table 4 are programmable.
'Thble 4. DRAM Programmable Timing Parameters
Parameter
tAR
tRAM
tMAC
tRAS
tRPR
tcp
tDC
tRIN
Description
Address to RAS assertion
RAS to multiplexed address
Multiplexed address to CAS
RAS pulse width
RAS pre-charge width
CAS pre-charge width
FIFO data delay to CAS
tENR
RAS completion during non-reflective inhibit
Enable delay on read
tENW
Enable delay on write
Refer to the timing diagrams at the end of this data sheet for the
timing definitions. Refer to the Register Descriptions for details.
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ADVANCED INFORMATION
Refresh and Scrubbing
Refreshrequirements vary depending on the density and organization of the DRAM chips in the system. However, rows must be refreshedat the same interval (approximately every 15 microseconds
the next row is refreshed). The refresh requests are generated by
two cascaded counters. A programmable 7-bit counter divides
CLK down to create a 1-MHz clock signal. This clock is further divided by a 4-bit, modulo 15 counter, to generate a refresh request
every 15 iJ.Sec. These refresh requests are synchronously arbitrated
with memory requests.
The RefreshAddress counter is advanced by one row every refresh
request. The column address forms the next most significant portion of the refresh address. After all rows are refreshed and
scrubbed at the same column address, the column count advances
andallrowsare then refreshed atthenextcolumnaddress. The row
and column address counters are each 12 bits long spanning 16
Mbits.
All four banks of a given block are scrubbed simultaneously at a
particular address. All error correction channels in the controller
are used in parallel (4 channels in CYM7232, 2 channels in
CYM7264). While one of the four DRAM blocks is scrubbed, the
other three blocks undergo normal refresh. The 2-bit Scrub Block
counter advances after all rows and columns in a particular block
are refreshed so that the next block can be scrubbed. A fully populatedmemoryusing 16-Mbitdevices to achieve 1-gigabytecapacity
is scrubbed in little more than 15 minutes. When an error is detected during scrubbing operations, the correction address will be
copied from the Refresh Address counter to the Error Location
register. (Note that when an error occurs in a normal read operation, the corrected data is not written back into the memory array.
Data is corrected inside the DRAMs during scrubbing cycles only.)
When an error occurs during refresh/scrubbing operations the refresh cycle (i.e., a read to check for errors) is turned into a scrub
cycle (i.e., read-modify-write to correct the errors).
Each block of memory may be populated with different sized
DRAM components however, all banks within a given block must
be populated with the same depth memory chip. For simplicity, the
RefreshAddress counter treats every block as if it were populated
with DRAMs of maximum (16-Mbit) capacity. When refreshing
smallermemories, the same address location will be scrubbedmultiple times before the counter advances to the next location.
Each block pair would share a common CAS. The controller may
be configured to internally OR the appropriate CAS pairs to produce a single CAS output for each pair of blocks. Refresh in the
non-overlapping RAS mode is longer than that of the staggered
RAS refresh mode. Refer to the Register Descriptions for details.
Initialization
The DRAM is initialized when the INIT command is given. The
DRAMs are energized with 16 RAS only cycles. All of DRAM are
then fIlled with zeros and the associated error check bits.
Diagnostic Features
For diagnostic purposes, the DRAM error check bits may be read
or written by the system. The error check bits may be accessed by
reading the EDC registers at any time. The error check bit fields
will contain the error check bits from the previous DRAM read
cycle. Error check bits may be directly written to DRAM by first
writing the desired check bits to the Write Check Bit register and
then setting the appropriate control bit in the Command register.
All subsequent DRAM writes will write the check bits from this
register. Clearing the control bit will return the check bit source to
the data path's write error check bit generation circuitry.
Bus Interface Signal Description
0[63:0] - Data. During the data phase, D[63:0] contains the
transactionsdata.
DP [7:0] - Data Parity. Duringthe data phase, DP[7 :0] reflects the
parityofthe transaction's data. During the address phase, DP[7:0]
is ignored and the outputs are three-stated. Data parity is checked
only over those bytes that are enabled. During a data phase write,
DP[7:0] are inputs, receiving the parity as transferred across the
bus. During a data phase read, DP[7:0] are outputs, indicating the
parity of the data that has been applied to the bus. The parity output is enabled onlywhen the relevant data byte is enabled. Theparity outputs remain three-stated when the parity is disabled. The
parity's sense (i.e., odd/even and enable/disable) is specified by the
Parity Mode bits, PM[2:0]. DP[7:0] are assigned as given in Table 5.
'Thble 5. Data Parity Assignments
Data Parity
Refresh Modes
There are two modes of refresh/scrubbing. The four RAS signals
are staggered differently in each mode. Staggering prevents noise
problems when switching· current simultaneously to multiple
blocks of DRAM.
Staggered RAS
The onset of each RAS signal is staggered by one bus clock (four
bus clocks overa.ill..!!I the first mode. Once all RAS lines are asserted a single CAS signal is selected for presentation to the
scrubbed block of memory. The strobe signal used to enable clocking of the scrubbed data into the controller is also delayed by an
amount equal to the staggered RAS delay.
Mutually Ex£lusive RAS
Some SIMMs are constructed with multiple sections of RAS enabled DRAM (i.e., common CAS lines across sections) The controller offers a second non-overlapping RAS refresh mode that
supports these SIMMs. This is essential so that the CAS that is asserted for the scrub operation will enable only the required SIMM
section. Should this type of DRAM SIMM be used, pairs of blocks
would be RAS enabled during refresh or normal DRAM accesses.
CYM7232
CYM7264
Data Byte
DPO
D[7:0]
DP1
D[15:8]
DP2
D[23:16]
DP3
D[31:24]
DP4
D[39:32]
DP5
D[47:40]
DP6
D[55:48]
DP7
D[63:56]
PMD [2:0] - Parity Mode. The Parity Mode bits specify the parity
computation algorithm and identify those signals that participate
in the parity computation. They must be asserted during the address phase and held valid during the entire transaction. The parity
modeselectionisappliedto both the address and data buses. These
bits are defined below.
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o
1
Odd ParityComputed
Even Parity Computed
PM1
o
1
Data Parity Disabled
Data Parity Computed
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SEMICONDUCIDR
PMO
o
Address Parity Disabled
1
Address Parity Computed
A[35:0] - Address. During the address phase, the ~em will supply the transaction's address on A[35:0] and assert AS.
AP[3:0] - AddressParity. During the address phase, the lowest 32
bits of the transaction's address can be checked for parity. The system can generate a set of parity inputs AP[3:0] that correspond to
A[31:0]. Parity is not supported for A[35:32]. The parity's sense
(i.e., odd/even and enable/disable) is specified by the Parity Mode
bits, PM[2:0]. Note that the parity mode bits also define the parity
mode for the data bus. AP[3:0] are assigned as given in Table 6.
wraparound at the cache line end and complete the burst access for
the remainder of the cache line.
1lIble 8. Burst Counter Length
Burst Length
(bytes)
1lIble 6. Address Parity Assignments
Address Parity
Address Byte
APO
A[7:0]
API
A[15:8]
AP2
A[23:16]
AP3
A[31:24]
TYPE [5:0] - TI-ansaction 'JYpe. During the address phase,
TYPE[5:0] specify the TI-ansaction 'JYpe (see Table 7). These are
synchronousinputs. Note that the TYPE input may be changed on
a transaction by transaction basis, consequently, different processors may be mixed within the system.
1lIble 7. 1Ype Interpretation
'JYpe Bits
Data Size
0 0 X XX 0 Any
Write
0 X X XX 1 Any
Read
o
X XX 0 Default Burst Write
1 XX XX 1 Default Burst Read
XX X X 0 X
XX X X 1 X
XX X
oX
~BusWidth
Sequential Burst Order
~BusWidth
Intel Burst Order
X Any
oX
X 1 X X .:5, Bus Width
XX
oX
XX Any
XX 1 X XX Any
0 1 X XX 0 Any
Size [3:0] are Size Bits
Size [7:0] are Byte Enables
Little-EndianBus
Big-EndianBus
Burst Counter Length
for 32-Bit Bus (bits)
Burst Counter
Length for M-Bit
Bus (bits)
Not Burst
8
1
16
2
1
32
3
2
64
4
3
128
5
4
Anew address, in which the burst counter serves as the lowest portion, is formed. The counter extends the length of address bits as
shown in Table 8 and starts at AD2 for a 32-bit system bus and at
AD3 for a 64-bit system bus. All higher address bits (above the
counter)remain fixed throughout the burst transaction and are not
affected by rollover of the burst counter. As an example, for a
64-bit system bus and a SIZE of 64 bytes, the system ignores
AD[2:0], fixing these bits at O. AD[5:3] form the internal burst
counter starting from the address as transferred over the system
bus, and AD[35:6] remain fixed as originally input. This address
generation is shown for this example in Table 9.
1lIble 9. Burst Address Example
[
TI-ansaction 'JYpe
5 4 3 2 1 0
1
CYM7232
CYM7264
ADVANCED INFORMATION
AD[35:6]
Fixed
I AD[5:3] IAD[2:0]
Counter
000
I
When TYPE1 = 0 the burst order is sequential. Subsequent addresses are generated by sequentially incrementing the bits of the
addresswithin the range of the burst counter as determined above.
After reaching the address in which all burst counter bits are ones,
the counter wraps around to zero. Higher-order addresses remain
fixed.
When TYPE 1 = 1 the burst counter increments in the non-sequential fashion characteristic of Intel processors. In all other respects,
the address for the burst is the same as that in the sequential case.
The non-sequential burst counter algorithm extends the Intel
scheme to any length burst. The nonsequential counting starts at
the address specified by the address bus input. The counter bits are
then incremented in the following fashion:
1. the lowest-order bit always toggles,
Posted Write
2. a bit toggles only if the next lowest order bit in the counter
is toggling for the second time (independent of its value).
1 1 X X X 0 Default Burst Posted Write
TYPEO - Read/Write. When 0, this bit indicates the transaction is
a write. When 1, this bit indicates the transaction is a read.
TYPE1- Burst Order. Given a system bus of width N bytes (N =
4 or 8), any transaction as specified by the SIZE input which is
greater than N constitutes a burst. Thus transactions of double
words (8 bytes) and larger are bursts for a 32-bit bus and transactions of 16 bytes and larger are bursts for a 64-bit bus. The maximum burst length is 128 bytes. During bursts the lowest order bits
ofthe address input are ignored. AD[1:0] are ignored for a 32 bit
bus system and AD[2:0] are ignored for a 64 bit bus system. This is
the alignment constraint.
The next higher set of address inputs are loaded into a counter,
which generates the proper address as the burst proceeds. The
counter length is given in Table 8. The generated burst address will
For example, if the burst counter is 3 bits in length (AD[5:3] as
above) and begins at address 101, then the counting sequence is
101,100,111,110,001,000,011,010
Notice that in this counting sequence, higher-order bits change the
least often and therefore result in a minimum number of DRAM
page mode accesses.
TYPE2 - SIZE Interpretation. The SIZE bits have twoalternative
interpretations.When TYPE2 = 0, the transaction length in bytes
is given by the value ofSIZE[3:0]. When TYPE2 = 1, the byte(s)
that are enabled in the transaction are specified when theirrespective size bits are asserted low (e.g., SIZE[N] means BYTE[N] participatesin the transaction). Forelaborationsee the SIZE[7:0] definition.
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ADVANCED INFORMATION
TYPE3 - little Endian/Big Endian. Processorsmaydefmethe position of BYTE 0 on the bus in either of two ways. Either BYTE 0
appears as the lowest byte on the bus (D[7:0] - little endian,
TYPE3 = 0) or BYTE 0 appears as the highest byte on the bus (big
endian - D[M:M -7], where M = Bw - 1. Bw is the bus width in
bits, TYPE3 = 1). For elaboration see the definition of the
SIZE[7:0] bits.
.
TYPE4 - Write Posting. When TYPE4 = 1, the write data is
posted into the Write FIFO, where it remains until the next read is
completed. This can be used to postpone the actual DRAM write
until after the DRAM read is completed, thereby speeding cache
line fills.
TYPES - Default Burst Mode. When TYPES = 0, the transaction'ssize is specified by SIZE[7:0] (which are interpreted according to TYPE2). When TYPES = 1, the transaction's size is specified by the default burst size programmed into the Command
register. The burst size defaults to this value regardless of TYPES
during reflective reads transformed into writes and writes transformedto reads for ownership.
SIZE [7:0] - nansaction Size. During the address phase,
SIZE[3:0] specify the number of bytes to be transferred during a
bus transaction. These are synchronous inputs. SIZE[7:4] are an
extended size control used to support byte enabled transfers. The
expanded definition is compatible with i486, i860, SPARe, MIPS,
88K and 68040 processors. The interpretation of SIZE is determinedbyTYPE2 as in Table 10 through Table 16. Note that for size
specificationsthat are larger than the system bus size, the nansaction Size specifies the internal burst address generation wraparound.
1lIble 11.64 Bit Bus Address Interpretation Size
A2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SIZE 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SIZE 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SIZE 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AO
0
1
0
1
0
1
0
1
Byte #
0
1
2
3
4
5
6
7
BigEndian
D[63:56]
D[55:48]
D[47:40]
D[39:32]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
=1 Byte
Little Endian
D[7:0]
D[15:8]
D[23:16]
D[31:24]
D[39:32]
D[47:40]
D[55:48]
D[63:56]
1lIble 12.64 Bit Bus Address Interpretation Size = 2 Bytes
A2
At
0
1
0
1
0
0
1
1
AO
X
X
X
X
Halfword#
0
1
2
3
Big Endian
D[63:48]
D[47:32]
D[31:16]
D[15:0]
Little Endian
D[15:0]
D[31:16]
D[47:32]
D[63:48]
1lIble 13. 64 Bit Bus Address Interpretation Size = 4 Bytes
A2
A1
X
X
0
1
1lIble 10. Size Interpretation with TYPE2 = 0,
SIZE[7:4] = XXXX
SIZE 3
At
0
0
1
1
0
0
1
1
AO
X
X
Big Endian
D[63:32]
D[31:0]
Word #
0
1
Little Endian
D[31:0]
D[63:32]
1lIble 14.32 Bit Bus Address Interpretation Size = 1 Byte
nansaction Size
Byte
HaIfword (2 Bytes)
Word (4 Bytes)
Doubleword (8 Bytes)
16-Byte Burst
32-Byte Burst
64-Byte Burst
128-Byte Burst
32-Byte Burst
32-Byte Burst
64-Byte Burst
64-Byte Burst
Doubleword (8 Bytes)
Word (4 Bytes)
HaIfword (2 Bytes)
Byte
A2
A1
0
0
1
1
X
X
X
X
Byte #
AO
0
1
0
1
Big Endian
D[31:24]
D[23:16]
D[15:8]
D[7:0]
0
1
2
3
Little Endian
D[7:0]
D[15:8]
D[23:16]
D[31:24]
1lIble 15. 32 Bit Bus Address Interpretation Size = 2 Bytes
A2
A1
X
X
0
1
AO
HaIf-
X
X
Word #
0
1
Big Endian
D[31:16]
D[15:0]
little Endian
D[15:0]
D[31:16]
1lIble 16. Size Interpretation with TYPE2 = 1
nansaction
Big Endian
SIze[x]
Two interpretations are offered in the above table to support
SPARe MBus and Motorola 88K processors.
7
X
X
X
X
X
X
X
0
9-188
6
X
X
X
X
X
X
0
X
5
X
X
X
X
X
0
X
X
4 3
X X
X X
X X
X 0
0 X
X X
X X
X X
2
X
X
0
X
X
X
X
X
1
X
0
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
D[63:56]
D[55:48]
D[47:40]
D[39:32]
D[31:24]
D[23:16]
D[15:8]
D[7:01
nansaction
Little Endian
D[7:0]
D[15:8]
D[23:16]
D[31:24]
D[39:32]
D[47:40]
D[55:48]
D[63:56]
=t: ;:~
~=CYPRESS
~I SEMICONDUCTOR
CYM7232
CYM7264
ADVANCED INFORMATION
Processorsgenerally require their byte enable signals to be contiguous. No checking is performed to distinguish invalid combinationsfrom valid combinations.
Thble 17. BACK[2:0]
BACKl
ERR
BACK1
ACK
BACKO
RTY
1
0
1
Valid Data 1Iansfer
0
0
1
Uncorrectable
Read Error
1
1
1
Wait States
AS - Address Strobe. This signal is asserted by the bus master during the address phase of the transaction. The address and transaction attributes are strobed into the Controller Module during the
addressphase. The address phase is one clock cycle long and is normallyfollowed by one or more data phases.
OS - Data Strobe. This signal is asserted by the bus master to begin the data phase of the transaction. Data strobe is recognized in
certain modes and can be used by the system to delay the onset of
the transaction. If the transaction is a burst, data strobe can not be
used to interrupt or delay individual data phases of the burst. Data
Strobe may be permanently asserted in those applications that do
not need this function. Refer to the section on Bus Acknowledge
and Data Strobe Modes for details.
BLST - Burst Last. The burst length is specified by SIZE[3:0] or
the programmed default burst length by way of the TYPE input
during the address phase of every transaction. BLST may be used
by the bus master to override the default or SIZE specified burst
lengthbyprematurelyterrninating the bus transaction. BLSTmust
be asserted in the same cycle as the last data transfer. Note that
BLST is not a pipeJined signal and therefore has an earlier set-up
time than the other control signals.
INH - Inhibit. This signal may be asserted by a cache controller in
multiprocessing environments to abort a bus transaction already in
progress.When INHisreceivedbeforethesnoopwindowends, the
operation is terminated. If the transaction is a memory read, no
data is transferred over the system bus while the snoop window is
open. If the transaction is a memory write and data has already
been transferred, the internal FIFOs are cleared. Inhibit may be
used to ~aturelyterminate I/O operations before data is transferred. INH should not be asserted after the snoop window closes.
Three-state Three-state Three-state Idle Cycles
Thble 18. BACK[1:0] Inputs When RSTIN is Asserted
BACKI
BACKO
0
0
MBus (DS Gnd)
With Data
0
1
Early DS (10k)
With Data
1
0
Real-Time DS
None (Uses BR/FE)
1
1
EarlyDS (2Clks)
Early BACK (1 Clk)
RSTIN - Reset In. This signal is used to reset the controller. The
signal must last for at least four clocks. This signal is internally synchronized to the bus clock.
BACK[2:0] - Bus Acknowledge. These signals supply the transaction acknowledge to the bus master. They are defined in Table 17.
Thesesignals also receive acknowledgesfromthesystemduringreflective reads thereby acting as data strobes. During system reset
BACK[2:0] act as inputs to program bus acknowledge modes and
select the source of the snoop window signal.
BACK[2:0] are used as inputs during Reset to select the Bus Acknowledge and Data Strobe modes as well as the source of the
snoop window determination (internal counter/SNW external input). BACK[2:0] must be driven according to Table 18 and
Table 19 when Reset is asserted to invoke the desired mode.
OS Mode
BACK Mode
Thble 19. BACKl Inputs When RSTIN is Asserted
BACKl(SNW)
Snoop Window Source
0
External
1
Internal
When a read is inhibited and transformed into a write, the
BACK[2:0] signals become inputs and are used to strobe the bus
data into the Reflective FIFO. Table 20 gives the interpretation of
the BACK[2:0] inputs when the reflective writes are in progress.
Thble 20. BACK[2:0] Inputs as Reflective Reads are 1hmsfonned Into Writes
TRC - 1Iansform Cycle. This signal, when asserted along with
INH, transforms an inhibited read cycle into a write cycle (reflective) or an inhibited write cycle into a read cycle (read-for-ownership). 1Iansformed transactions use the programmed default burst
length and ignore the SIZE specified in the original transaction.
The burst begins at the address specified at the transaction start.
SNW - Snoop Window. This input may be used to define the duration of the snoop window. Operations may be inhibited and transformed in any cycles in which this signal is asserted. As an alternative, the duration of the snoop window may be defined by an
internal counter.
Definition
BACKl
ERR
BACKI
ACK
BACKO
RTY
1
0
1
1
1
1
All
Other
Modes
Definition
Valid Data 1Iansfer
Idle Cycle
Invalid
BERR - Bus Error. This signal indicates that a parity error conditionhas occurred during the address or data phase of atransaction.
This signal is asynchronous (i.e., it will occur one cycle after the
corresponding address parity error or two cycles after the correspondingdata parity error). BERR may be programmed to last for
one clock cycle or until cleared.
BR/FE - Bus Request/FIFO Empty. This signal will be issued by
the controller during reflective read transactions. BR from the
main memory system should be interpreted as the highest pri~
~uestfor bus mastership to the system's arbiter. In this case BRI
FE works in conjunction with BG and BB to effect this mastership.
Additionalsystem bus transactions will be prevented until the ongoing write (resulting from the reflective read) to main memory
has completed. Systems having more elaborate protocols for acknowledging data transfers between a requesting cache and a
cache data owner can use this signal to prevent the next transaction
from overwriting the reflective data path inside the controller.
This output m~so be programmed to include the empty status
of the FIFOs. BR/FE will then be asserted if either the reflective
FIFO or the normal write FIFO are not empty. When this option is
selectedBG and BB are not used. This output may be used by systems that assess the availability of the controller before the data
phase is initiated and pause until the controller becomes available.
9-189
II
ADVANCED INFORMATION
BG - Bus Grant. This signal is asserted by the external arbiter in
response to a BR, to indicate that the controller has been granted
ownership of the bus.
BB - Bus Busy. lbis signal is asserted by the controller for the durationofits bus ownership. The controller will acquire the bus asit
completes the main memory write transaction during reflective
readoperations.
'IlIble 21. ID[3:0] in Generic Mode
ID3
0
0
0
0
0
1
ID2
0
1
1
1
1
X
ID1
X
0
0
1
1
X
IDO
X
0
1
0
1
X
DRAM Mode Selection
Not Selected
Not Selected
JlO Registers
Indirect Address Register
Not Selected
Memory
CYM7232
CYM7264
ID [3:0] - Identification. The Identification bits are synchronous
inputs recognized during the address phase. The ID bits are used in
conjunction with address signals to define the nature of the bus
transaction and select I/O registers or DRAM memory. For Mbus
operation refer to Table 39. For the generic mode a match is requiredbetween ID[3:0] and the fixed values shown in Table 21.
eLK - Clock. CLK synchronizes all bus transactions. All transactions are strobed in at the rising edge of clock.
INT - Interrupt. This signal indicates that the module has a pending interrupt that requires service. lbis output remains asserted
until the interrupting condition is cleared.
IMD - Interface Mode. When tied LOW, the controller operates
in the MBus mode. When tied HIGH, the controller operates in
the generic mode.
Pin Description
Table 22 through Table 25 summarize the functional pin connectionsof the controller module. Power and ground connections are
not listed.
'IlIble 22. Pin Descriptions
Signal Name
D[63:0]
DP[7:0]
PMD[2:0]
A[35:0]
AP[3:0]
AS
DS
BLST
BACK[2:0]
RSTIN
Description
I/O
I/O System Data Bus: These lines are used to
transfer data to and from the DRAM
Module. These lines are normally threestated except when a valid read cycle is in
progress.
I/O Data Bus Parity: These signals follow the
direction of the data bus. When the device
is driving the data bli!dread), data parity is
generated and supp . to these pins. When
data is entering the device, data parity is
checked.
Parity Mode: These inputs specify the
I
parity mode for data and address.
I
System Address Bus: These lines are used
to transfer the address to the DRAM
module.
I
Address Bus Parity: These inputs are examined for address integrity during accesses to the device.
I
Address Strobe: lbis input is used to indicate that the bus address and control signals are valid. It is used to enable clocking
of the address and control information
into the controller.
I
Data Strobe: This input is used to indicate
that the data transaction is to take place.
I
Burst Last: This input can be used to terminate a transaction.
I/O Bus Acknowledge:Theseacknowledge
signals output the transactionresponse
back to the bus master. During reflective
reads, these signals are inputs. During Reset, act as inputs and are used to invoke
certainmodes.
I
Master Reset: Activating this inaut causes
the module to set all control an status
bits to their reset state.
Signal Name
CLK
I/O
I
BERR
0
INH
I
SNW
I
TRC
I
TYPE[5:0]
I
SIZE[7:0]
I
INT
0
ID[3:0]
I
BR/FE
0
BG
BB
ADRS[11:0]
R!W[3:0]
I
0
0
0
R!W[1:0]
0
RAS[3:0]
0
CAS[3:0]
0
9-190
Description
System Bus Clock: This clock is used to
synchronize the controller's operation to
the system bus clock.
Bus Error (Open Drain): Indicates that a
parity error has occurred on the bus.
BERRis asynchronous.
Inhibit is used to abort read and write operations.
Snoop Window: Dermes the time in which
Inhibit can be asserted.
ltansform Cycle: This input reverses the
sense of inhibited operations.
ltansaction 1Ype: These inputs determine
the transaction type.
ltansaction Size: These inputs indicate
the size of the transaction.
Interrupt (Open Drain): This output indicates that an interrupt request is pending.
Identification: Selects memory or internal
registers; positions the module in the address space.
Bus Request/FIFO Einpty. Reflects the
status of the reflective orwrite FlFOs .
Bus Grant.
Bus Busy.
DRAM row/colunmmultiplexed address.
DRAM read/writecontrol.; one output
per bank. (CYM7232 only)
DRAM read/write control.; one output
per bank. (CYM7264 only)
DRAM row address strobe; one per
block.
DRAM colunm address strobe; one per
block.
~
.il~UCIDR
ADVANCED INFORMATION
Thble 23. Special Function Signals
Signal
Name
TSTE
JlO
I
Description
Test Enable; this input must be grounded for
properoperation.
TSTM
I
ThstMode.
TST[2:0]
0
MCLK
I
Test Outputs.
Multiple Frequency Clock. Optional input if
internal PLLs are not used.
IMD
I
MBus/genericinterface mode select
tembus. The controller maybe further connected fora multiplexed
address/data bus by tying A[31:0j to D32[31:0j.
If the system bus employs bus parity, then DPO should be tied to
DP4,DP1 tied toDP5 and so forth forming a four-bit parity nibble
for the 32-bit system bus.
64·Bit System Bus Connection
The 64-bit EDCversion of the controller may only be connected to
64 bit bus systems. Address and data may be multiplexed, as in the
32 bit case, by connecting the module's address bus to a portion of
its data bus. Address parity and data parity may also be shared, by
connecting the module's address parity bus bits to a portion ofits
data parity bus.
Internal Registers
Thble 24. DRAM Data Signals (CYM7232)
Signal
Name
DDA[31:0]
EDA[6:0]
DDB[31:0]
JlO
Several internal registers are available to set-up the controller and
report status to the host. Each register is spaced 16 bytes apart in
the address space so that its contents will be accessible on D[7:0] of
the data bus regardless of system bus width or orientation (littlelbig
endian). The EDC registers are accessed as 32-bit registers. An internal8-bit indirect address register is provided topointto the individual I/O locations inside the controller. A register map is provided in Table 26.
Description
I/O DRAM data bus interface, Bank 0
I/O DRAM error check bit bus interface, Bank 0
EDB[6:0]
I/O DRAM data bus interface, Bank 1
I/O DRAM error check bit bus interface, Bank 1
DDC[31:0]
EDC[6:0]
I/O DRAM data bus interface, Bank 2
I/O DRAM error check bit bus interface, Bank 2
DDD[31:0] I/O DRAM data bus interface, Bank 3
I/O DRAM error check bit bus interface, Bank 3
EDD[6:0]
•
Thble 25. DRAM Data Signals (CYM7264)
Signal
Description
JlO
Name
DDA[63:0] I/O DRAM data bus interface, Bank 0
DDB[63:0]
I/O DRAM error check bit bus interface, Bank 0
I/O DRAM data bus interface, Bank 1
EDB[7:0]
I/O DRAM error check bit bus interface, Bank 1
EDA[7:0]
CYM7232
CYM7264
tn
U.I
..J
::;)
C
o
:IE
Power and Ground Connections
There are two sets of power and ground connections. One set is for
the logic and I/O circuitry and is indicated by V ss and VDD in the
pin diagram. All Vss pins should be connected to ground and all
VDD pins should be connected to the +5 volt supply. There are
separate supply connections for the internal phase lock loops.
VDDLis the +5 volt supply connection and VsSLis the ground connection for the phase lock loops. For superior noise immunity,
VSSL and VDDL should be connected with independent pcb routing. These connections should run to the power supply where it
connects to the circuit board on which the controller module resides.
The pinout lists several no connect (NC) pins. These connections
should be left open. Theymay be usedinfutureversionsofthecontroller. IMD should be tied high to invoke the generic bus interface
mode. TSTE must be grounded.
32·Bit System Bus Connection
The 32-bit EDCversion of the controller (CYM7232) may be connected to a 32-bit system data bus. This is accomplished by tying
DO to D32, Dl to D33 and so forth. The SBS[1:0] field in the Command register must also be programmed with 00 to invoke the
32-bit system bus mode forcing the controller to multiplex read
data onto the system bus and demultiplex write data from the sys-
9-191
.~
"SEMICONDUCTOR
;: CYPRESS
CYM7232
CYM7264
ADVANCED INFORMATION
Thble 26. Register Map
Index
Name
OOH
Command Register 0
01H
02H
CommandRegister 1
Command Register 2
03H
CommandRegister 3
04H
OSH
06H
07H
CommandRegister4
CommandRegister S
Reserved
Reserved
08H
DRAM Timing 0
09H
OAH
OBH
DRAM Timing 1
DRAM Timing 2
DRAM Timing 3
OCH
ODH
OEH
OFH
DRAM Timing 4
Reserved
Reserved
Reserved
lOH
llH
Block 0 Placement [7:0]
Block 0 Placement [1S:8]
12H
13H
Block 1 Placement [7:0]
14H
ISH
Block 1 Placement [1S:8]
Block 2 Placement [7:0]
Block 2 Placement [1S:8]
16H
17H
Block 3 Placement [7:0]
Block 3 Placement [IS:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
CIE
I
INIT
I WC I
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9-192
4
3
2
1
o
RFD
SBS
ES
BLP
I
I
PLL
lIE
I DFB
SEN. I CAM J RSM tBRM
BLK
RTA
PLM
SWC
I EDC I EDP J EAP
EME I EVE
I EDE I ESE
RAS
AR
MAC
CP
RIN
RPR
DC
ENW
ENR
RAM
BAO[27:20]
BAO[3S:28]
BA1[27:20]
BA1[3S:28]
BA2[27:20]
BA2[3S:28]
BA3[27:20]
BA3[3S:28]
·4
_ ' j e CYPRESS
~_~
CYM7232
CYM7264
ADVANCED INFORMATION
SEMUCONDUCTOR
Thble 26. Register Map (continued)
Index
18H
Name
Block 0 Mask [7:0]
19H
Block 0 Mask [15:8]
lAH
lBH
Block 1 Mask [7:0]
Block 1 Mask [15:8]
lCH
lOH
lEH
Block 2 Mask [7:0]
Block 2 Mask [15:8]
Block 3 Mask [7:0]
IFH
Block 3 Mask [15:8]
Error Location Address [7:0]
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
R/W
R!W
R!W
R!W
R!W
R!W
R!W
R!W
R!W
7
4
5
6
BM2[27:20)
BM2[35:28]
BM3[27:20)
BM3[35:28)
ELA[7:0]
Error Location Address [15:8]
Error Location Address [23:16]
Error Location Address [31:24]
R
R
R
ELA[15:8)
ELA[23:16]
EDC Register 0
EDC Register 1
R
R
Reserved
Reserved
Syndrome FIFO Flags 0
R
Syndrome FIFO Flags 1
R
Reserved
Reserved
2CH
2DH
Diagnostic Check Bit 0
Diagnostic Check Bit 1
2EH
Reserved
2FH
Reserved
30H
Population Code
31H
32H
Bus Error
Interrupt Status Register
o
1
BMl[27:20)
BMl[35:28]
R
2AH
2BH
2
3
BMO[27:20]
BMO[35:28]
ELA[31:24)
See Section on Error Status Registers
W
W
•
(/)
LIJ
....I
R!W
I
PN3
W
PN2
I
PNI
I
PNO
BERR Control
R!W
9-193
I
IC
I DBE I ABE I MEW I UEW I DEW I SBW
~
C
o
:::i
CYM7232
CYM7264
~
-
;~PRESS
~F
ADVANCED INFORMATION
SEMICONDUCTOR
Index Register
IA[7:0] - Index Address. This register's contents points to all otherregisters inside the controller. During access to the controller's
internal byte wide I/O path, little endian processors should apply
an address with A[3:0] = 0 to enable data onto D[7:0] on their system bus. Big-endian processors should apply an address with their
A[3:0] = F to enable data onto D[7:0] on their system bus. Access
to the internal registers is controlled through the ID bits. For ID3
equal to 1, all accesses occur to memory. For ID3 equal to 0, access
is to the internal registers: with ID[2:0] equal to 110, transactions
are directed to the Index register, with ID[2:0] equal to 101, transactions are directed to the register pointed to by the Index register.
For all other combinations of the ID input, the controller is not selected. ID3 functions as the Memory/IO select and the remaining
ID inputs function as selects or chip enables.
This register is not nsed in MBns mode. See MBns section for details on writing and reading I/O registers.
ES - EDC Size. Specifies the number of data bits in each EDC
packet.
o 32 Bits
1 64 Bits
PLL - Phase Locked Loop Multiplier. These bits program the
multiplicationfactor from the incoming bus clock (CLK) to the internal DRAM timing clock. They are defined as follows:
PLL[I:0] Clock Multiplier
00
X 2/X 1 - 50 MHz bus
01
X2-40MHzbus
10
X 3/X 2 - 33 MHz bus
11
X 4/X 3 - 25 MHz bus
RFf - RefreshTestMode. This bit must be clear for proper operation.
Command Register 2
Index
7
6
Command Registers - Write / Read
7
6
5
4
3
2
RFD
CIE - Coherent Invalidate Acknowledge Enable. When this bit is
set HIGH it enables acknowledges to MBus Coherent Invalidate
cycles. BACK[2:0] are generated two clocks after the address
phase in which the TYPE bits specify this cycle. Systems requiring
different acknowledge delays should set CIE = 0 and use an external PLD to generate the acknowledge. This bit should be set to 0
when in the Generic Mode.
RFD - Refresh Counter Divisor. These bits divide CLKdown to 1
MHz. The output ofthis counter is further divided by a fixed divide
"by 15" counter, which produces the 15 microsecond refresh requests. The division factor is the load value plus 1. Forexample, the
divisorload values in decimal for the various bus clock frequencies
are:
24
25MHz
32
33MHz
39
40MHz
49
50MHz
7
6
5
4
3
2
BLK
DFB
o
o
BLP - Block Population. These bits define which blocks are populated. BLP[N] = lindicates that Block N is populated. Blockpopulationmust be contiguous with one exception. BLPO and BLP2 can
be assertedsimultaneouslywith BLP1 andBLP3 deasserted simultaneouslywhen supporting 36- and 40-bit SIMMS populated with
two sections of DRAM memory.
BLK - Number of Blocks. These bits specify the total number of
populated blocks. 0 (H) = 1 block ... 3 (H) = 4 blocks.
DFB - Default Burst Length. This field defines the default burst
length for cache line read/writes. The bus will execute burst transactions with this default length when the appropriate TYPE bit is
asserted during the address phase of a transaction orwhen an operation is transformed. These bits are interpreted as follows:
DFB [1:0] Default Burst Length
00
01
10
11
16 Bytes
32 Bytes
64 Bytes
128 Bytes
Command Register 3
Index
Command Register 1
o
2
3
o
o
7FH
Index
4
BLP[3:0]
Command Register 0
Index
5
7
6
5
4
3
2
o
o
INIT - Initialization. This bit, when set, triggers an initialization of
the DRAM memory and its check bits. The contents of the memory
are set to zero and the corresponding check bits are set.
WC - Write Check Bits. Enables writing of the EDC check bits
from the registers inside the data path.
o Write EDC check word computed from incoming data.
1 Write EDC check word from check bit register.
SBS [1:0] - System Bus Size. Specifies the number of data bits in
the system bus.
00 32Bits
01 64 Bits
RCM - Refresh Control Modes. These bits control refresh and the
DRAM INIT process for test purposes. RCM must be set to 11 for
proper operation. When asserted, RCM[O] enables refresh and
RCM[l] enables the INIT process. (The INIT process occurs after
DRAM energizing and fills all DRAM with 0.)
RTA - Real-TIme Bus Acknowledge Mode (Reads). The RealTime Bus Acknowledge modes (RTA[1:0]) described below only
take effect when read bus acknowledges are programmed to occur
in real-time (not early).
RTA[1:0]
Real-time Read Bus AcknowledgeMode
00 ModeO. EDC status ignored for BACK[2:0] assertion. Maximum set-up time from BACK[2:0] to rising edge of system
9-194
CYM7232
CYM7264
~
~~~NDtaOR
ADVANCED INFORMATION
clock. System bus data not corrected on reads. This mode always used during early bus acknowledge cycles.
m- Interrupt Enable. This bit must be set to enable interrupts to
01
Mode 1. EDC status incorporated into BACK[2:0] assertion.
Errors corrected in real-time to bus. Minimal set-up time
from BACK[2:0] to rising edge of system clock.
EDC - Enable Error Detection and Correction. Enables the correction of single bit errors in the data path.
10
Mode2. EDC status incorporated into BACK[2:0] assertion.
Errorscorrectedinreal-timetobus.Additionaiwaitstatesinserted at selected points. Maximum set-up time from
BACK[2:0] to rising edge of system clock.
SEN - Scrub Enable. This bit enables scrubbing when asserted
HIGH.
CAM - CAS Assertion Mode
o CAS[3:0] independently asserted.
1 CAS[3:2LQ.Red" to produce CAS2, CAS[1:0] "ORed to
produce CASO. This mode is provided to support some 36or 4O-bit-wide DRAM SIMMs that contain two rows of
memorywith independent RAS and common CAS.
RSM - RAS Stagger Mode (during RefreshiScruboperations).
o RAS[3:0] staggered by one bus clock.
1 RAS[3:0]staggeredtobenon-overiapping(mutuallyexclusive in time). This mode is provided to support some 36- or
40-bit-wide DRAM SIMMs that contain two rows of
memory with independent RAS and common CAS. The
RAS signals must be mutually exclusive when scrubbing
these SIMMs.
BRM - Bus RequestMode
o
1
Bus arbiter ON. BR/FEassertionindicatesrefiectiveFIFO
status only. With bus arbiterO~R/FEisdeasserted with
the recognition ofBus Grant (BG) and Bus Busy (BB) is assertedafter the B~~es HIGH.
Bus arbiter OFF. BR/FE assertion combines write FIFO
status and reflective FIFO status (iogicalOR). BothFIFOs
must be empty for the BR/FE 0.!I!Put tobedeasserted. With
the bus arbiter OFF, BG and BB are ignored and BR/FE
output simply reflects the combined FIFO status.
Command Register 4
Index
7
6
5
4
3
1
2
PLM
SWC
FH
FH
the system bus.
EDP - Enable Data Bus Parity Interrupt. Enables the interrupt indicating that one of the data bytes has a parity error.
EAP - Enable Address Bus Parity Interrupt. Enables the interrupt
indicating that one of the address bytes has a parity error.
EME - Enable Read-Modify-Wite Multiple Error Interrupt. Enables the interrupt indicating that a multiple error has occurred on
aread-modify-writecycle.
EUE - Enable Uncorrectable Error in Word Interrupt. Enables
the interrupt indicating that an uncorrectable error has occurred in
a word.
EDE - Enable Double Bit Error in Word Interrupt. Enables the
interrupt indicating that a double bit error has occurred in a 32(64-) bit word.
ESE - Enable Single Bit Error Interrupt. Enables the interrupt indicating that a single bit correctable error has occurred in a 32(64-) bit word.
DRAM Timing Program Registers - Write I Read
DRAM Timing Register 0
Index
6
5
4
3
o
2
RAM
AR
FH
FH
DRAM Timing Register 1
Index
7
6
5
4
3
o
2
RAS
MAC
FH
FH
DRAM Timing Register 2
Index
o
7
7
6
5
4
3
o
2
CP
RPR
FH
FH
DRAM Timing Register 3
PLM - Phase Locked Loop Mode. These bits specify which of the
internal VCOs in the phase locked loop are enabled for test or operation. When the PLL is bypassed the DRAM timing is derived
from the external signal MCLK.
SWC - Snoop Window Count. This value programs the duration
of the snoop window in bus clock cycles. The snoop window counter is enabled one clock after an address phase on the bus in which
thecontrollerisselected. WhenaOis programmed into the counter
the snoop window closes immediately (i.e., the cycle after the address phase). The window can be extended up to 16 clocks after the
address phase appears on the bus. Mter power-up the counter defaults to the maximum value.
CommandRegister 5
Index
7
6
5
4
3
2
o
Index
7
6
5
4
3
2
1
o
DC
FH
DRAM Timing Register 4
Index
7
6
5
4
3
o
2
ENW
ENR
FH
FH
All timing values are set with 4-bit values. The time intervals are
specified to to-ns accuracy when the internal clock is running at
100 MHz, 12.5-ns accuracy when the internal clock is running at 80
MHz, 13.3-ns accuracy when the internal clock is running at 75
MHz, or 15.2-ns accuracy when the internal clock is running at 66
MHz. Refer to the timing diagrams for elaboration.
9-195
II
CYM7232
CYM7264
ADVANCED INFORMATION
llIble 27. DRAM Timing Values
Delay/Width (ns)
66 MHz
15.2
30.3
45.5
60.7
80
91
106
121
136
152
167
182
197
212
227
242
Hex Value
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
llIble 28. DRAM Timing Program[l]
Parameter
tRAM
tAR
tRAS
tMAC
tcP
tRPR
truN
tDC
tENR
tENW
tACe
tcu
leY
Field
Name
RAM
AR
RAS
MAC
CP
RPR
RIN
DC
ENR
ENW
-
-
80 MHz
12.5
25
37.5
50
62.5
75
87.5
100
112.5
125
137.5
150
162.5
175
187.5
200
7SMHz
13.3
26.6
40
53.3
66.6
80
93.3
106.6
120
133.3
146.6
160
173.3
186.6
200
213.3
lOOMHz
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Block 0 Placement Register
Description
15
RAS to multiplexed address
Address to RAS assertion
RAS pulse width
Multiplexed address to CAS
CAS pre-charge width
RAS pre-charge width
RAS completion during non-reflective Inhibit
FIFO data delay to CAS
Enable delay on read
Enable delay on write
DRAM access time (determine by
DRAM chips)
DRAM CAS to Output Low Z (determinedby DRAM chips)
Bus CLK period
Note:
1. All timings may be resolved to l/n of leY, wbere n is the phase locked
loop multiplier (e.g. 50-MHz systems having aPLLmultiplierof2with
tcy = 20 ns can have DRAM timing resolutions defined to 10 ns).
Therefore, unless the timing values are constrained, the DRAM read
data could arrive at the data path input pipeline on a lO-ns boundary
rather than a bus clock boundary. The controller will automatically extend certain values that are programmed to providedataon a bus clock
boundary, whenever necessary.
Block Placement Registers - Write/Read
The Block Placement registers are 16-bit registers. Each register is
byte addressable only. Access of the upper and lower byte of the
register is through D[7:0].
Address 10H, BAO{27:20] (Bits 7:0)
Address llH, BAO{35:28] (Bits 15:8)
8 7
BAO[35:28]
BAO[27:20]
OOH
OOH
o
Block 1 Placement Register
15
!Default
Address 12H, BAl{27:201 (Bits 7:0)
Address 13H, BAl{35:2~ (Bits 15:8)
8 7
BA1[35:28]
BA1[27:20]
ooH
ooH
0
Block 2 Placement Register
15
!DefaUlt
Address 14H, BA2{27:201 (Bits 7:0)
Address 15H, BA2{35:2lf] (Bits 15:8)
8 7
BA2[35:28]
BA2[27:20]
ooH
ooH
0
Block 3 Placement Register
Address 16H, BA3{27:20] (Bits 7:0)
Address 17H, BA3{35:28] (Bits 15:8)
15
!Default
8 7
0
BA3[35:28]
BA3[27:20]
OOH
OOH
BAO, BAl, BA2, BAJ - Block Placement register. Specifies the location of each of the four blocks of memory in the overall memory
map. Block N is selected when the incoming address bits A[35:20]
match BA(N)[35:20]. Any bits in the BA(N) field can be masked
9-196
.i~PRESS
"
CYM7232
CYM7264
ADVANCED INFORMATION
SEMICONDUCTOR
and therefore not considered in the comparison. Comparisons do
not begin until the lnit bit is set in the Command register.
Block Mask Registers - Write/Read
The Block Mask registers are 16-bit registers. Each register is byte
addressable only . Accessof the upper and lower byte of the register
is through D[7:0].
Block 0 Mask Register
Address 18H, BMO[27:20J (Bits 7:0)
Address 19H, BMO[35:28J (Bits 15:8)
~
870
BMO[35:28]
BMO[27:20]
OOH
OOH
Block 1 Mask Register
Address 1AR, BM1[27:20J (Bits 7:0)
Address lBH, BM1[35:28J (Bits 15:8)
~
870
__--+___B_M_1-,[~35_:2_8-,-]_-+_ _B_M_1,,-[2_7_:20~]'--_-I1
~~efault
OOH
OOH.
Block 2 Mask Register
Address 1CH, BM2[27:20J (Bits 7:0)
Address lDH, BM2[35:28J (Bits 15:8)
15
8 7
BM2[35:28]
BM2[27:20]
OOH
OOH
Block 3 Mask Register
Address 1EH, BM3[27:20J (Bits 7:0)
Address 1FH, BM3[35:28J (Bits 15:8)
15
8 7
IDefaUIt
BM3[35:28]
BM3[27:20]
OOH
OOH
BMO, BM1, BM2, BM3 - Block Mask register. Indicates whether
a particular bit in the Block Placement registeris considered in the
memory map address comparison. Summarizing the mask definition:
BM(N)[X] = 0: Ignore Bit X when comparing AD[35:20] against
BA(N)[35:20]. N is the memory block number.
BM(N)[X] = 1: Include Bit X when comparingAD[35:20] against
BA(N)[35:20]. N is the memory block number.
Error Location Register - Read Only
The Error Location register is a 32 bit register that contains the address of the most recent error. This register is read only and is byte
addressable only. All bytes appear on D[7:0]. Byte addresses are as
follows:
20H ELA[7:0]
21H ELA[l5:8]
22H ELA[23:l6]
23H ELA[31:24]
Error Locat~~nAddress [31:0J
ELA[3l:0]
OOH
IDefaulJ
o
o
Error Status Registers - CYM7232
The Error Status registers provide information on errors that have
occurred during any read operation (including scrubbing and read
modify write). The location of these registers on the data bus will
depend on the system bus configuration (32 or 64 bits). Table 29
shows the location of data path registers for the 64-bit system
bus.Table 30 shows the location of the same registers in the 32-bit
system bus application.
o
Name
24H
EDC Register 0
25H
26H
27H
EDC Register 1
Reserved
Reserved
28H
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
29H
2AH
2BH
2CH
Reserved
Reserved
Diagnostic Check Bit 0
2DH
Diagnostic Check Bit 1
2EH
Reserved
Reserved
2FH
(J)
UJ
..J
:::)
o
o
:::E
Thble 29. Error Status Register Map for CYM7232 with 64-Bit System Bus
Index
II
RJW
63:56
R
R
CB3
55:48
CB2
47:40
SYN3
39-.32
31:24
23:16
15:8
7:0
CBl
CBO
SYNl
SYNO
SYN2
R
FLO
R
FLl
W
W
DCBl
DCBO
9-197
CYM7232
CYM7264
ADVANCED INFORMATION
'Thble 30. Error Status Register Map for CYM7232 with 32·Bit System Bus
Index
Name
R/W
31:24
23:16
15:8
7:0
24H
EDC Register 0
R
CBl
CBO
SYNO
25H
EDC Register 1
R
CB3
CB2
SYNI
SYN3
26H
27H
Reserved
Reserved
28H
29H
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
2AH
Reserved
2BH
Reserved
2CH
2DH
2EH
2FH
Reserved
Reserved
SYN2
R
FLO
R
FLl
Diagnostic Check Bit 0
W
DCBO
Diagnostic Check Bit 1
W
DCBl
EDC Registers
The EDC Registers contain the Read Error Log FIFO and Check
Bits fields. The registers are Read Only. The register at address 24
appears on D[31:0] and the register at address 25 appears on
D[63:32]when the module is connected a 64 bit system bus. For 32
bit systems, both registers appear on D[31:0].
EDC Register 0
Index
31 30
24 23 22
o
8 7 6
16 15 14
CBl
CBO
SYNI
SYNO
OOH
OOH
Undefined
Undefined
EDC Register 1
Index
31 30
16 15 14
24 23 22
8 7
o
6
CB3
CB2
SYN3
SYN2
OOH
OOH
Undefined
Undefined
This register will appear on D[63:32] of the 64-bit system bus.
When used in a 32-bit system bus application, this register will appearonD[31:0].
SYNO, SYNl, SYN2, SYN3 - Syndrome Bits. These bits originate
fromthe outputs of the syndrome FIFO. Theyreflect the EDCsyndrome bits on any memory read error condition (including reads,
readbursts, scrubs, andread modifywrites). The syndrome outputs
containvaiidinformationwhenevertheFIFOFlagregister'scorrespondingstatus bits indicate that the FIFOs are not empty. SYNO
contains the syndrome values for errors in DRAM Bank O. SYNI
contains the syndrome values for errors in DRAM Bank 1, and so
forth.
CBO, CDl, CB2, CB3 - Check Bits. These bits reflect the EDC
check bits that were present during the previous read operation.
CBO contains the check bits from DRAM Bank 0 for the most recentread. CBl contains the check bits from DRAM Bankl for the
most recent read and so forth.
Syndrome FIFO Flag Registers
The Syndrome FIFO Flag registers contain the full!emptystatus of
the syndrome FIFOs. The registers are read only (byte addressable
only). When the modnle is used in a 64-bit bus system the register
at address 28 appears on D[7:0] and the register at address 29 appears on D[39:32]. In 32-bit system bus operation the register at
address29 will appear on D[7:0].
Syndrome FlFO flag register 0 (32- & 64-bit system bus)
Index
7
6
54321
o
Reserved
OOH
Syndrome FIFO flag register 1 (64-bit system bus)
Index
39
38
37
36
35
34
33
32
1
o
Reserved
OOH
Syndrome FlFO flag register 1 (32-bit system bus)
Index
7
65432
Reserved
OOH
ESFO, ESFl, ESF2, ESF3 - Syndrome FIFO Empty Flags. These
bits reflect the EDC syndrome FIFO empty status. When set to 1,
these bits indicate that the associated FIFO is empty. ESFO reflects
the status of FIFO 0 which stores the syndrome values from
DRAMBankO.ESFI reflects the status of FIFO 1 which stores the
syndromevalues form DRAM Bank 1 and so forth.
9-198
~
.it~NDOC1OR
FSFO,FSFl, FSF2, FSF3 - Syndrome FIFO Full Flags. These bits
reflect the EDC syndrome FIFO full status. When set to 1, these
bits indicate that the associated FIFO is full. FSFO reflects the statusofFIFO Owhich stores the syndrome values form DRAM Bank
O. FSF1 reflects the status of FIFO 1, which stores the syndrome
values from DRAM Bank 1 and so forth.
Diagnostic Check Bit Registers
Diagnostic Check Bit Register 0 (32 & 64 bit system bus)
Index
7
6
o
54321
DCBO
OOH
Diagnostic Check Bit Register 1 (64 bit system bus)
Index
39
38
37
CYM7232
CYM7264
ADVANCED INFORMATION
36
35
34
33
32
DCB1
Diagnostic Check Bit Register 1 (32 bit system bus)
Index
7
6
5432
1
o
DCB1
OOH
DCBO, DCBl: Check Bit Register - Write only. These bits can be
written to override the check bits generated by the write polynomialgenerator. In a 64-bit system bus configuration, the register at
address 2C appears on D[7:0] and the register at address 2D appearsonD[39:32]. When used in a 32-bit system bus, the register at
address 2D will appear on D[7:0]. Data written into Diagnostic
Check Bit register owill write into the check bits for DRAM Banks
oand 2. Data written into Diagnostic Check Bit register 1 will write
into the check bits for DRAM Banks 1 and 3. The selection to use
EDCcomputedfrom the write data or use the EDC as contained in
this register is determined by bit WC in the Command register 1.
OOH
Error Status Registers - CYM7264
Table 31. Data Path Register Map for CYM7264
Index
Name
24H
EDC Register 0
25H
EDC Register 1
Reserved
26H
27H
R!W
Reserved
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
28H
29H
2AH
2BH
31:24
R
R
23:16
15:8
CBO
CBI
7:0
SYNO
SYN1
R
R
FUl
FL1
W
DCBO
W
DCB1
Reserved
2CH
Reserved
Diagnostic Check Bit 0
2DH
2EH
2FH
Diagnostic Check Bit 1
Reserved
Reserved
EDC Registers
The EDC Registers contain the Read Error Log FIFO and Check
Bitsfields. The registers are Read Only. These registers will appear
in D[31:0] of the system data bus as shown in Table 31.
EDC Register 0
Index
31
24 23
SYNO
CBO
Undefined
o
8 7
16 15
OOH
Undefined
Undefined
EDC Register 1
Index
31
SYN1
CB1
Undefined
o
8 7
16 15
2423
DOH
Undefined
SYNO, SYNI - Syndrome Bits. These bits reflect the EDC syndromebits on an error condition. SYNOcontains the syndrome valuesfor errors in DRAM Bank O. SYN1 contains the syndrome values for errors in DRAM Bank 1.
Undefined
CBO, CBl - Check Bits. These bits reflect the EDC check bits that
were present during the previous read operation. CBO contains the
check bits read from DRAM Bank O. CB1 contains the check bits
read from DRAM Bank 1.
9-199
CYM7232
CYM7264
ADVANCED INFORMATION
BERR Control Register - Write Only
Syndrome FIFO Flag Registers
Syndrome FIFO Flag Register 0
Index
7654
Index
3
2
0
131H
IF:FO! ES;oI
7
6
54
3
2
Reserved
0
IFS;1! ES;11
OOH
ESFO,ESFI- Syndrome FIFO Empty Flags. These bits reflect the
EDCsyndrome FIFO Empty status. When set to 1, these bits indicate that the associated FIFO is empty. ESFO is the flag for Syndrome FIFO 0 and ESF1 is the flag for Syndrome FIFO 1.
FSFO, FSFI - Syndrome FIFO Full Flags. These bits reflect the
EDCsyndrome FIFO full status. When set to 1, these bits indicate
that the associated FIFO is full. FSFO is the flag for Syndrome
FIFO 0 and FSF1 is the flag for Syndrome FIFO 1.
Diagnostic Check Bit Registers
7
6
4
5
L:~a:tl
2
3
1
0
OOH
7
6
~~:tl
5
4
2
3
0
Population Code Register
54
3
o
2
PNl
PNO
o
o
PNO, PNI, PN2, PN3 - Population Code. Specifies the DRAM
chip depth installed in all banks ofBlockN. The population code is
defined as follows:
00
I
Thisregister controls operation of the BERR output.
CBE - Clear Bus Error. This bit, when asserted, clears BERR
when MBE (above) is set.
Interrupt Status Register
Index
7
6
543210
IC - Initialization Complete. This bit indicates initialization of the
DRAM is complete.
DBE - Data Parity Error. This bit indicates that a data bus parity
error has occurred over the system bus.
SBW - Single Correctable Error. This bit indicates that a single
correctable error has occurred in a 32- (64-) bit word.
OOH
6
210
DEW - Double Error in a Word. This bit indicates that a double
bit error has occurred in a 32- (64-)bit word.
DCB1
7
3
UEW - Uncorrectable Error in a Word. This bit indicates that an
uncorrectable error has occurred in a 32- (64-) bit word.
DCBO, DCBI - Check Bit Register. These bits can be written to
override the check bits generated by the write polynomial register.
Data in DCBO is written to DRAM Bank 0 and data in DCBl is
written to DRAM Bank 1. The selection to use EDC computed
from the write data or use the EDC as contained in this register is
determined by bit WC in the Command register Byte 1.
Index
4
MEW - Multiple Errors in a Read-Modify-Wite. This bit indicates that multiple errors have occurred during a
read-modify-writeoperation.
DCBO
Diagnostic Check Bit Register 1
Index
5
ABE - Address Parity Error. This bit indicates that an address bus
parity error has occurred over the system bus.
Diagnostic Check Bit Register 0
Index
6
MBE - Mode Bus Error. When MBE is set, BERR remains asserted till explicitly cleared when reporting data parity errors.
OtherwiseBERR is asserted for one clock only.
Syndrome FIFO Flag Register 1
Index
7
256K depth (Le. 256Kx 1 or 256Kx 4)
01
1M depth (Le.1Mx 1 or 1Mx4)
10
4M depth (i.e. 4M x 1 or 4M x 4)
11
16M depth (Le. 16M x 1)
InterruptStatus register bits ISR[6:0] are latched. Theseinterrupts
can be cleared individually by writing the register with the desired
bit high. Otherwise those status bits remain indefinitely, or until
RSTIN is asserted LOW.
Special Characteristics of I/O Registers
The two EDC registers can be accessed with 32-bit reads over the
system bus. All other I/O registers must be accessed by reading or
writing a single byte at the address location shown. That byte will
always be located at the lowest 8 bits of the system's data bus
(D[7:0]). Programmingregisters are readlwrite for diagnostic purposes. These register's address locations are separated by 16 bytes
to support wide system data paths.
Syndrome Decoding
Thefollowing tables give the decoding for the syndrome values for
the 32 and 64 bit error detection and correction algorithms.
Table 32 gives the syndrome decoding for the 32-bit error-detectionand correction algorithm. Table 33 gives the syndrome decodingfor the 64 bit error detection and correction algorithm. In these
two tables, U indicates a multiple (greater than 2) bit uncorrectable error, D indicates a double bit error, nm indicates an error in
data bit nm, and Cn indicates an error in check bit n.
9-200
~
~~PRESS
~_., SEMlCONDUCfOR
CYM7232
CYM7264
ADVANCED INFORMATION
llIble 32. Syndrome Decoding, 32-bit EDC
S6
SS
S4
S[3:0]
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
0000
0001
U
D
D
0
D
U
U
D
D
U
U
D
U
D
D
16
0010
0011
0100
0101
D
29
7
D
U
D
D
U
U
D
D
U
D
13
23
D
D
28
6
D
U
D
D
17
U
D
D
1
D
U
D
D
U
D
22
21
D
0110
0111
1000
1001
12
11
D
5
D
U
D
D
C3
D
27
26
4
D
U
D
D
U
U
D
D
U
D
31
D
D
U
D
10
9
20
19
D
1010
1011
1100
1101
1110
1111
D
25
3
D
15
D
D
C2
U
D
D
U
D
8
18
D
D
D
D
24
2
D
U
D
D
D
U
U
D
14
D
D
C1
CO
30
D
D
C6
D
C5
C4
N
II
llIble 33. Syndrome Decoding, 64-bit EDC
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
0
0
C4
C5
D
C6
D
D
62
C7
D
D
D
D
14
D
U
U
D
D
U
U
D
U
D
34
56
D
D
50
40
S7
S6
SS
S4
S[3:0]
0
0
0
0
0000
0001
N
CO
Cl
D
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
46
D
U
U
D
D
U
D
D
30
D
U
D
D
U
D
18
8
D
U
D
D
U
U
D
D
U
D
2
24
D
C2
D
D
15
D
35
57
D
D
51
41
D
U
D
D
31
D
19
9
D
U
D
D
63
U
D
D
47
D
D
20
10
D
U
D
D
U
U
D
D
U
D
3
4
25
D
26
D
U
D
D
U
D
D
D
D
U
U
D
D
D
42
43
U
D
52
53
D
D
58
59
D
C3
36
37
D
U
D
D
U
D
11
D
U
D
D
U
U
D
D
U
D
5
12
D
33
D
D
U
49
D
D
U
D
6
27
28
D
D
21
22
17
D
D
U
D
38
60
D
D
54
44
D
1
D
D
U
D
23
13
D
U
D
D
U
U
D
D
U
D
7
29
D
U
D
D
U
D
39
61
D
D
55
45
D
U
D
D
U
16
D
D
U
D
U
U
D
D
U
U
D
0
D
D
U
D
U
U
D
32
D
D
U
48
D
D
U
D
U
U
D
9-201
D
tJ)
UJ
...I
:::»
C
o
:e
ADVANCED INFORMATION
MBos Operation
Bus Transactions General Description
System transactions follow the MBus specification January 31st,
1991, Revision 1.2 (Review draft) including Level 2. Only those
functions required of a main memory system are implemented
The implementation of the generic interface is an extension of the
MBus specification adopted to an adaptable interface useable bya
variety of processors. The descriptions of the generic interface are
therefore applicable to MBus applications. The intent of this sec·
tion is not to repeat the MBus specification but to identify those
operating characteristics and functions which are invoked with the
MBus mode selection.
Module Connections
During reset, ~2:01 must be driven to invoke the proper
Mbusmodes. The snoop window source must originate internally.
1b make theseseIections, ~2:0] mustbe driven to binary 100
during~L Refer to 1IJb1e 18 and 1IJb1e 19.
Bus Interrace Signal Description
The bus interface signal descriptions are identical to that given in
the generic descriptionil except for some minor variations and nomenclature. This section will present only those differences and
highlight the nomenclature equivalences.
Transaction Specific Control
Thmsactionspecificcontrol informationiscontained in fields within the address as specified by MBus. These fields are given in
1IJb1e36.
The SPARC MBus is an address/data multiplexed bus therefore,
the address and data pins of the module must be wired together.
The controller accommodates the multiplexed bus by storing the
address and control information that is presented during the address phase allowing the data on the address pins to change after
the deassertion of the address strobe. The module connections to
MBus are given in the following tables. Note that some module
pins are tied together to the MBus connection. Other connections
must be permanently tied to a HIGH or LOW level.
Thble 34. MBus Signal 'Iranslation
Controller
CLK
D[63:0]
A[3S:0]
TYPE[3:0]
SIZE[2:0]
AS
HACtq2:0]
INH
BR
BG
13B_
ID[3:0]
BERR
RSTIN
INT
MBus
CLK
MAD[63:0]
MAD[3S:0]
MAD[39:36]
MAD[42:40]
MAS
MERR, MRDY, MRTY
MIH
MBR
MBG
MOO
ID[3:0] (fixed value)
AERR
Thble 36. Multiplexed Bus Address Subfields
Signal Name
A[3S:0]
TYPE[3:0]
SIZE[2:0]
BLST
TSTE
PMD[2:0]
TRC
Description
Physical Address
'nansaction 1Ype
'nansaction Data Size
Reserved
Parity is not defined for MBus, however, the controller retains the
capability to generate and check parity when configured for MBus.
TYPE[2:0): 'Iransaction 'JYpe
During the address phase, TYPE[2:0] specify the transaction type.
TYPE[2:0] are multiplexed bus signals and are directly MBuscompatible. The module fully responds to Write. Read, Coherent Read.
Coherent Write and Invalidate, and CoherentRead andInvalidate.
The response to Coherent Invalidate cycles is programmable. If
the Coherent Invalidate Acknowledge Enable in the Command
register is 0, the module makes no response to these cycles. This is
the default condition after reset. If the Coherent Invalidate Acknow~
Enable in the Command register is 1, the module asserts
for Coherent Invalidate cycles but, otherwise, plays
no role in the transaction.
Thble 37. 'Iransaction 'JYpes
RSTIN
INTOUT
0
0
0
0
1
'JYpe
1
0
0
1
1
0
1
0
2
MBus
o(MBus mode)
o(Ignored)
0
0
1
0
0
tied high for non-reflective
memory
tied to INH for reflective
memory
Physical
Signal
MAD[3S:0]
MAD[39:36]
MAD[42:40]
MAD[63:43]
Parity
Thble 35. Extra Signals in MBus
Controller
IMD
TYPE[S:4]
SIZE3
DS
CYM7232
CYM7264
Data Size
Transaction Site
0
1
0
1
0
Any
Any
32 Bytes
32 Bytes
Any
Write
Read
Coherent Invalidate
Coherent Read
Coherent Write & Invalidate
1
32 Bytes
Coherent Read & Invalidate
Reserved
0
All Other Combinations
TYPE[2:O): Transaction Size
During the address phase, SIZE[2:0] specify the number of bytes
to be transferred during the data phase of the bus transaction.
SIZE[2:0] are multiplexed bus signals and are directly MBus compabole.
9-202
CYM7232
CYM7264
~
#t:~
511ii1iii;; CYPRESS
~,
ADVANCED INFORMATION
SEMICONDUCTOR
Thble 38. Size 'Iransaction
Size2
0
0
Sizel
0
0
1
1
0
0
1
1
0
0
1
1
1
1
SizeO
0
1
0
1
0
1
0
1
MERR, MRDY, MRTY - Bus Acknowledges
'Iransaction Size
Byte
HaJfword (2 Bytes)
Word (4 Bytes)
Doubleword (8 Bytes)
16-Byte Burst
32-Byte Burst
64-Byte Burst
128-Byte Burst
Thble 39. Address Interpretation in Byte Mode (Size [2:0] =0)
A2
Al
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
AO
0
1
0
1
0
1
0
1
Byte#
0
1
2
3
4
5
6
7
Bits
D[63:56]
D[55:48]
D[47:40]
D[39:32]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Thble 40. Address Interpretation in Halfword mode
(Size [2:0] =1)
A2
Al
AO
Byte#
Bits
0
0
1
X
0
D[63:48]
0
1
1
0
X
X
1
2
D[47:32]
D[31:16]
1
X
3
D[15:0]
These signals supply the transaction acknowledge to the bus master. They are defined in the Bus Acknowledge Tables and follow
the MBus encoding. MERR corresponds to BACK2, MRDY corresponds to BACK1, and MRTY corresponds to BACKO.
BR/FE - Bus Request. This signal will be issued by the controller
duringreflective read transactions. BR from the main memory system should be interpreted as the highest priority request for bus
mastership to the system's arbiter. Additional system bus transactions will be prevented until the ongoing write (resulting from the
reflective read) to main memory has completed. (The original
MBusspecification has no explicit mechanism for reflective main
memories to postpone the next bus transaction while the data being transferred between two caches is simultaneously written to
DRAM.)
In the MBus mode, The BRM bit in Command register 3 should be
programmedOtoenable the bus request handshaking. When thisis
done,BRisdeasserted uE2!l the recognition ofBG and is followed
by the assertion of BB. BB remains asserted until the Reflective
FIFO is empty.
BG - Bus Grant. This signal is asserted by the external arbiter in
response to a BR, to indicate that the controller has been granted
ownership of the bus.
BB - Bus Busy. This signal is asserted by the controller for the duration of its bus ownership. The controller will require the bus as it
completes the main memory write transaction during reflective
read operations.
ID[3:0] - Identification. The ID field selects various configuration spaces within the MBus address space for access to the Port
register and other I/O registers.
Thble 43. ID[3:0] Mapping
F/Fl00/0000 H to F/FIFF/FFFF H
ID[3:0]
oH reserved for boot
PROM
IH
F/FnOO/OOOO H to F/FnOO/OOOO H
nH
F/FEOO/OOOO H to F/FEFF/FFFF H
EH
F/FFOO/OOOO H to F/FFFF/FFFF H
FH
MBusCONFIGURATION SPACE
F/FOOO/OOO H to F/FOFF/FFFF H
Thble 41. Address Interpretation in Word Mode (Size [2:0] =2)
A2
0
Al
X
1
X
AO
Byte#
Bits
X
X
0
D[63:32]
D[31:0]
1
Thble 42. BACK 'Iranslation
0
0
0
0
0
1
0
1
0
Controller
Definition
Reserved
Uncorrectable
Error
Reserved
0
1
1
Reserved
1
1
0
0
0
1
1
1
0
Reserved
Valid Data
Transfer
Not Used
1
1
1
Idle Cycle
MERR
MRDY MRTY
Internal Registers
MBus
Definition
Retry
Error3 Uncorrectable
Error2 Timeout
Errorl- Bus
Error
Reserved
Valid Data
Ransfer
Relinquish and
Retry
Idle Cycle
Several internal registers are available to set up the DRAM controller and report status to the host. The register's individual bits
are defined in the sections describing the generic mode of operation. The registers appear on the MBus exactly as they would in the
64-bit bus generic mode, big-endian operation.
When the MBus mode is invoked, the MBus Portregisterbecomes
accessible. Its form, content, and address are defined below. In addition, the Command register 0 contains a control bit specific to
MBus operation. This control bit affects the controllers response
to MBus coherent invalidate cycles. Addressing of the internal registers is direct in the MBus mode and therefore the index register is
not used. The address of each register has the form (in hexadecimal)
FFnxxOmpx
9-203
•
en
LLl
..J
;:)
Q
o
:::i
CYM7232
CYM7264
ADVANCED INFORMATION
MR[3:0] - Revision Number. This specifies the revision level for
MBus compatible devices - 0 H.
MD[7:0] - Device Number. This specifies a unique number that
indicatesthe vendor specific MBus device present at this port.
MP[31:16]- Reservedforlateruse.
Specific Programming
where n is a nibble that is compared to the input on the ID pins, x
is a don't care condition, and mp are the two nibbles of the indexed
address as given in the register descriptions. For example, if
ID[3:0] is A H, then the MBus address for the BERR Register is
FFAxx031xH.
MBus Port Register - 2 Bytes - Read Only
Address 7
6
I:::tl
Address 15
5
4
3
o
2
MR
MY
OH
IH
14
13
12
11
10
9
For MBus, there will be specificregisterprogranuning to configure
the controller for MBus operation. Forconvenience, specificfields
are listed below along with the load value appropriate to MBus.
There are other programming selections that must be made which
are dependent upon the specific application.
PLL[I:0]
01
4O-MHzBus
SBS[I:0]
01
64-BitSystemBus
PLLMODE TBD 80-MHzPLLEnabled
8
MD
tbdH
I=:tl
Timing
MY[3:0] - Vendor Code. This specifies the vendor code for MBus
compatible devices - 1 H for Cypress Semiconductor.
Bus timing diagrams reflect generic applications, however they are
applicable to MBus. All of the diagrams must be interpreted for
data strobe, DS, permanently asserted.
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
Operating Range
StorageThmperature ................. - 4O°Cto +125°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . - O.3V to + 7.0V
Input Voltage. . . . . . . . . . . . . . . . . . . . .. - 3.0V to Vee + O.3V
Output Voltage ........................... 0 to Vee Volts
Range
Commercial
Ambient
Thmperature
Vee
0°Cto+70°C
5V±5%
Electrical Characteristics Over the Operating Range
CYM7232
CYM7264
Description
Parameter
Thst Conditions
Min.
Max.
Units
4.75
5.25
V
0
70
°C
Vee
Supply Voltage
TAMB
Ambient Thmperature
Commercial
VOHl
Output HIGH Voltage 'JYpe 1
Vee = Min., IOHl = - 8.0 rnA
2.4
VOH2
Output HIGH Voltage 'JYpe 2
IOH2= -12 rnA
2.4
VOLl
Output LOW Voltage 'JYpe 1
Vee = Min., lOlL = 8.0 rnA
VOH2
Output LOW Voltage 'JYpe 2
IoH2= 12 rnA
VlH
Input HIGH Voltage
VIL
Input LOW Voltage
lIN
Input LeakageCurrent
Vee = Max., 0 5. VIN 5. Vss
lOUT
Output Leakage Current
Vee = Max., Vss5. VOUT 5. Vee
lee
Operating Current
Outputs Open, f = fMAX
2.4
-0.3
V
V
0.4
V
0.4
V
Vee+O.3
V
0.8
V
+10
+10
!lA
!lA
TBD
rnA
Capacitance
Parameters
CIN
CoUT
CIQ
Description
InputCapacitance
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
I/O Capacitance
Max.
TBD
Units
TBD
pF
pF
TBD
9-204
pF
I
I
CYM7232
CYM7264
ADVANCED INFORMATION
Output Signals by 1Ype
Output
Description
BACK[2:0]
Type 1
BERR
Type 1 (Open Drain)
BR/FE
Type 1
BB
Type 1
INT
Type 1 (Open Drain)
RAS[3:0]
Type 2
CAS[3:0]
Type 2
ADRS[11:0]
Type 2
DDA, DDB, DDC, DDD
Type 1
EDA, EDB, EDC, EDD
Type 1
R!W[3:0]
Type 1
DP[7:0]
Type 1
D[63:0]
Type 1
1Jpe 1 outputs are designed to drive50-pF loads with a DC drive of
8 rnA. Type 2 outputs are designed to drive 50-pF loads with a DC
drive of 12 rnA. The open drain outputs have identical pull down
characteristics to the two-state output of the same type. MBus
modules are tested with 100-pF loads to guarantee compatibility
with the MBus specification.
II
AC Test Loads and Waveforms
ALL INPUT PULSES
Output JYpe 1
446n
OUTP~~ ~
,~,~~:Fl
J 1
_
174n
INCLUDING
JIG AND
SCOPE
-
3.0V----
446n
-
90%
OUTP~~ ~
,~,.~:Fl
J 1
_
GND
174n
INCLUDING
JIG AND
SCOPE
(a)
-
-
M7232-7
(b)
,
Output 1Ype 2
Equivalent to:
402n
402n
5V~
I 30 pF 116rr
OUTPUT
-(c)
THEVENIN EQUIVALENT
125n
Type 1
OUTPUT~ 1.40V
5V~
OUTPUT
5pF
I--
-(d)
116rr
90n
-M7232- 6
9-205
OUTPUT~
1.12V
Type 2
CYM7232
CYM7264
ADVANCED INFORMATION
Switching Diagrams
Read
REAL-TIME BACK CYCLE
CLK
~~~~~~Q~~~~~~~~~~~~~Vu1
r-
~J
\
:1
Note 4
~
it
x
BUS DATA
~
Note 4
THREE-STATE
~It~>--
~ci;
~r,
BLSf(5]
Do D1
1\ -'
\. 1-1
rm
~n ~nill
-".
-to 2 ~
ADRS[11:01
~\n ~\n tm~
n~ \ ~I ~
I~ tr4
!-- r--
.!RAM
X
-
ROW
X
COy,
~
tAR
+2
Min
ROW
COL1
.nU\n ~ IU
nrut
tRPC
I
\
tAR
1
\
RAM
"';mw X
tENR
\
tcp
I
tMAC IENR
tENR
NOles~ ~
I
NotelS
1
Icz .. ~
~ READ DATAr- ~READDATA
~
I\.Note
1-1 2
X
COL1
'--
tMAC
DRAM
DATA
I
\
t\
THREE-STATE
MCLK
~ ~~~Q "'l.
\~
I
r-
EARLY BACK CYCLE
~J
~
II
~READDATA
\.
V
Nole3
,
Notes:
2.
3.
FESTRBis asserted here following the closure of the snoopwindowin
the previous clock cycle.
FESTRBwouJd normally occur after t~ delay if necessary to
a1ignFESTRB to a bus clock boundary. FESTRB is asserted here following the assertion of OS (data strobe) in the previous clock cycle.
4.
5.
9-206
BACK remains three-stated until it is first asserted. At the end of the
transaction, BACK is deasserted in the first half of the clock cycle and
then three-stated.
FESTRB would normally occur here after tENR, however, it is automatically delayed by the controller to align to a bus clock boundary.
·
~PRESS
~F
CYM7232
CYM7264
ADVANCED INFORMATION
SEMICctIDUCTOR
Switching Waveforms (continued)
Write - Real-Time Bus Acknowledge/Early Data Strobe
WRITE
ClK
rLrt. L rL.rL.rL rLlL L rLh- ~ ~rt. L L h- rL rL 1L1Lrt. L~ ~h--~ ~
-
~J
\. J
I
I
\.
I
\.
I
I I
\.
THREE-STATE
THREE-STATE
'tl
"Bo B1 Bl Bf"1
~
BUS
DATA
Do
r-"
r
I\... ~
MClK
nn
~~~~
If
\
ADRS
[11:0]
X
':JW X
y
11 ~
-
~~ VI
,
C I.n
I
R/W
\
II
o~
D
'- \
J
~
\ J
t1E
NOTE 11
NOTE 8
Noles:
6. FESTRBis an ioternal signal that unclocks the FIFO. FESTRB is one
bus clock cycle long.
7. BLST may be ioternal or external
8. The assertion of CAS (and all subsequent CAS cycles of the burst) requires
tDC to have expired
tcp to have expired (t2A > tc.P)
After CAS asserted, FES1'RBunclocks the write FIFO presenting
the next data page to the DRAM.
9. DS may be deasserted in any of the cycles shown.
~ tRM.
I~ ~~
~~ ~
t1A
I--
IX
I
X
II
X
-
UJ
U.I
..J
:::)
C
II
DOl
~
\ J
NOTE 12 NOTE 7
10. tR ~ tRPC + 2 MCLK
tR ~ tAR + 2 MCLK
11. The assertion of CAS requires
tcp to have expired (from previous transaction)
tMAC have expired (ttA;;'" tMAe)
!Dc..!.o have expired (tIB ~ tDe)
SNW to have closed 2 bus clocks previous.
12. ttA is measured from the rising edge of the bus clock after !RAM has
expired.
9-207
II
I I o::e
\
-
~M
tENW --
COL
\ \
-
D..,
X
FESTRB[61
tR
ROW
\
DRAM
~
~o
/
\WRo\ WAo
DATA
_
x
L;l l
X
~1-'
\. f../
~
.. teNW - - t2A ...
NOTE 9
THREE-STATE
= .. ~
~~,
CYM7232
CYM7264
ADVANCED INFORMATION
CYPRF.SS
SEMICCtIDUCIDR
Switching Waveforms (continued)
Write - Real-Time Data Strobe
WRITE
CLK
rt-rt- L rt-rt-n.rLrt-rt-n.
f--
riM
~J
~rt-n.n. roo ~ n. n. rt-f1-IV1-n.h-
'- ~
I
\
I
\. f-- ~
I
\
THREE-STATE
,.,,.,
BLST[7]
ADRS
[11:01
R/W
DRAM
DATA
FESTRB[6]
I
I\.1-1
nn
R W IX
Pt~ Yt ~ n
teNW
-r.- t2A ..
X
COL"
COL
I
I\WRcX. WR.
!ENlI
i¥
t"\
tR~~~~ tL~V1 ~, I-~ ~~
t:l
tENW ..... 1 ,
X
R W
Dn.
~ 1--11
II
X
IX
\WR.\ WR.,
II
"
~.x
I--
I\.1-1
~~t!~ ru- Ir I---n~ f..
1\
IX
D
'"
\
BRIFE
MCLK
roo
D.x~D:XD
BUS
DATA
D
~\ J
J\...
\ ~
NOTE 11
NOTE 8
9-208
IX-
I
,
\
t-"
x
Dn.
X
\ II
NOTE 12 NOTE 7
-
COL
--
CYM7232
CYM7264
ADVANCED INFORMATION
Switching Waveforms (continued)
Write - Early Bus Acknowledge
WRITE
ClK
rLrq-q"q-q-q-LILrt- rt- rt- ~
- ~~
~h..rLh-ILrt- rt-1L1Lrt- rt- ~
I\. ~
I
I
\
Note 9
I
\
I
'\
I I
!I'
THREE-~
THREE-STATE
"Bo B1 B2 B3
~A ~
Do
IXD
I\. V
RAS
ADRS
[11:0]
R/W
nIl
~~trt rtf
\
IX
nw X
\. 'J
Jn~ ~ ~
n~
r-
I--
CO~
X
t1A
tENW ---- - - t2A .-
FESTRB[61
nl
\WR~ WAD
_tR+
~~
v----
t1A.
r-X
~\
D••
\. .I
J
NOTE 11
NOTES
9-209
\
l
,
U)
Ir\
o
X
X
...J
:;)
C
1/
X
•
U.I
X
ROW
/
D
t1B
~M lit ~v
~Id ...
Ir-
X'
I
...E,X
~
NOTE 10
\
DRAM
DATA
THREE-STATE
r "\
\
MClK
I
'f,11'
W
BUSDAI'A
I
.r")....-
D
\. .I
NOTE 12 NOTE 7
o
:::liE
~PRESS
CYM7232
CYM7264
ADVANCED INFORMATION
.---:
- , SEMICONDUCTOR
Switching Waveforms (continued)
I/O Cycles - Read[13]
ClK
AS
rL rLrLrL rL rLrL rLrL rL rL rL
~~
"- ~
BUS
DATA
/"DATA
"--f-.-/
THREE-STATE
BACK
J
(Norma I)
L
BACK
THREJ-STATE
THREE-STATE
IJ'
T1REE-sT1TE
'- J'
(Early)
WRITE
~U
BUS
DATA
\.. ~
«< ««< ~««
~««
K«« [«« [««
DATA
THREE-STATE
BACK
"-
(Normal )
BACK
TJREE-STJE
L
(Early)
Note:
13. Data transfer occurs 5 clock cycles after SNW or DS whichever occurs
last.
9-210
L!'
:>
Lf
THREE-STATE
THREE-lTATE
I--
~
~=CYPRESS
~,
ADVANCED INFORMATION
CYM7232
CYM7264
SEMICONDUCTOR
Switching Waveforms (continued)
Arbitration for Bus Mastership During Reflective Read
elK
It-IL K)L rL IL IL rL ~ )LIt-rL ~ >-- rLrL
f-
~~
\.. ~
I
J
\
\
BB(OUTPUTj
rr ~~
MASTERBB
9-211
£:i~PRFS5
~,
CYM7232
CYM7264
ADVANCED INFORMATION
SEMICONDUCTOR
Switching Waveforms (continued)
Pre·initialization
•
SET INIT BIT
RSTIN
I
I
PRE·INIT PHASE _ _ _ _ _ _~
16 RAS CYCLES
Initialization
RSTIN
~
"FiAS
lRf
CAS
IIIII
ADRS[11:0]
~
~
:III
:III
NORMAL OPERATION
REFRESH COMMENCES
RESET
PRE·INIT
INIT
M/RITE ALL LOCATIONS IN
ROW REFRESH ORDER)
15jJS
+ICBITSET
9-212
==-.
~
~=CYPRESS
~_,
ADVANCED INFORMATION
CYM7232
CYM7264
SEMICONDUCTOR
Switching Waveforms (continued)
Reset Cycle
CLOCK
1--------
4 CLK CYCLES/MIN
+-----++1
BACK[14]
tiS
II
en
Note:
14. BACK used as input to select bus acknowledge modes and snoop window source during reset.
II.!
...I
::;)
C
o
:E
9-213
£:.~
•
- CYPRESS
CYM7232
CYM7264
ADVANCED INFORMATION
. , SEMICCtIDUCTOR
Switching Waveforms (continued)
Mbus Coherent Invalidate Cycle (Cm set)
ClK
0
1
2
3
4
I
I
I
I
I
BACK[l]
MRDY
THREE-STATE
BACK[O]
THREE-STATE
MRTY
BACK[2]
MERR
THREE-STATE
9-214
2 :::z
~-CYPRESS
~,
ADVANCED INFORMATION
SEMICONDUCTOR
Ordering Information
Ordering Code
Package
'JYpe
Operating
Range
CYM7232PG-HC
PG01
Commercial
CYM7232PG-SC
PG01
Commercial
CYM7264PG-HC
PG02
Commercial
CYM7264PG-SC
PG02
Commercial
Document #: 38-M -00051
9-215
CYM7232
CYM7264
INFO
SRAMs
I'
Ii
PROMs
PlDs
FIFOs
lOGIC
I'
"
"
COMM
RISC
MODULES
ECl
I...
BUS
MILITARY
TOOLS
QUALITY
PACKAGES
Ii'
I"
'~j
#;~PRFSS
Section Contents
~, SEMICONDUCTOR
EeL
Page Number
Device Number
Description
CY10E301
CY100E301
CY10E302
CY100E302
CYlOE383
CYlO1E383
CY10E422
CY100E422
CY10E470
CY100E470
CY10E474
CY100E474
CYlOE484
CY100E484
CY101E484
CY10E494
CY100E494
CY101E494
Combinatorial ECL 16P8 Programmable Logic Device .............................
Combinatorial ECL 16P8 Programmable Logic Device .............................
Combinatorial ECL 16P4 Programmable Logic Device .............................
Combinatorial ECL 16P4 Programmable Logic Device .............................
EClJITL Translator and High-Speed Bus Driver ................................. .
EClJITL Translator and High-Speed Bus Driver ................................. .
256 x 4 ECL Static RAM ..................................................... .
256 x 4 ECL Static RAM ..................................................... .
4096 x 1 ECL Static RAM .................................................... .
4096 x 1 ECL Static RAM .................................................... .
1024 x 4 ECL Static RAM .................................................... .
1024 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
4096 x 4 ECL Static RAM .................................................... .
16,384 x 4 ECL Static RAM
16,384 x 4 ECL Static RAM
16,384 x 4 ECL Static RAM
.
.
.
.
10-1
10-1
10-6
10-6
10-11
10-11
10-17
10-17
10-24
10-24
10-29
10-29
10-36
10-36
10-36
10-43
10-43
10-43
II
...I
o
UJ
CYIOE301
CYIOOE301
CYPRESS
SEMICONDUcrOR
Combinatorial ECL 16P8
Programmable Logic Device
Features
Functional Description
• Standard l6P8 pinout and
architecture
-16 inputs, 8 outputs
- User-programmable output
polarity
• Ultra high speed/standard power
- tpD
4 ns (max.)
- lEE = 240 mA (max.)
• Low-powerversion
- tpD = 6 ns (max.)
-lEE = 170 mA (max.)
• Both 10KH- and lOOK-compatible
I/O versions available
• Enhanced test features
- Additional test input terms
- Additional test product terms
Cypress Semiconductor's Pill family offers the user the highest level of performance in ECL programmable logic devices.
These PLDs are developed using an advanced STAR@> bipolar process incorporating proven Ti-W fuses.
The CYlOE301 is lOKH-compatible and
the CYlOOE301 is lOOK-compatible.
These Pills implement the familiar sumof-products logic functions by selectively
programming cell elements to configure
the AND gates by disconnecting either the
true or the complement input term. If all
inputs are disconnected from an AND
gate, then a logical true will exist at the output of this AND gate. An output polarity
fuse is also provided to allow an active WW
=
to occur if this fuse is blown. Asecurityfeature provides the user protection for the
implementation of proprietary logic.
When invoked by blowing the security
fuse, the contents of the array cannot be
accessed in the verify mode.
The CYlOE301 and CYl00E301 can be
programmed using Cypress's QuickPro II
or other industry-standard programming
equipment. Programming support information can be obtained from local
CypressSemiconductor sales offices.
• Security fuse
Logic Block Diagram
Pin Configuration
PDlP/CerDIP
Top View
I/O
o
VCC2
PLCClCLCC
Top View
o tl
I/O
0
II
z>-I/O
I/O
o
o
VCC1
VCC2
NC
NC
o
o
I/O
I/O
I
I
--wu--~z
E3Q1·2
Selection Guide
Maximum Input to Output Propagation Delay Time (ns)
IEE(mA)
l
I
Commercial
Military
STAR is a trademark of Aspen Semiconductor.
10-1
10E301-4
100E30l-4
4
-240
10E30l-5
5
240
10E301L-6
10OE301L-6
6
170
...I
o&'-'
CYIOE301
CYI00E301
Maximum Ratings
Operating Range Referenced to Vcc at Ground
(Above which the useful life may be impaired. Exposure to absolute maximum-rated conditions for extended penods may affect
device reliability. For user guidelines, not tested.)
StorageThmperature •................ - 65°C to +150°C
Ambient Thmperaturewith
PowerApplied .........•............. - 55°Cto +l25°C
Supply Voltage VEE to Vcc ............... -7.0V to +O.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. VEE to +O.5V
OutputCurrent ............................... -SOmA
Electrical Characteristics
Parameters
VOH
Range
Commercial
(Standard,L)
Commercial
(Standard,L)
Military
Version
lOE
O°Cto +85°C
Ambient
-4.5V ±O.3V
lOE
-55°Cto +l25°C
Case
-5.2V±5%
Over the Operating Rangel 1]
Thmperature[2]
Description
Thst Conditions
Output HIGH Voltage 10KH, RL = 500 to -2V,
Tc= -55°C
VIN = VIHMin. orVILMax.
TA=O°C
TA= +25°C
Output WW Voltage
lOOK, RL - 500 to -2V,
VIN = VIH Min. or VILMax.
lOKH, RL = 500 to - 2V,
Tc = -55°C
VIN = VIH Min. orVILMax.
TA=O°C
TA= +25°C
TA= +75°C
Tc= +l25°C
TA = O°Cto 85°C
VIH
Input HIGH Voltage
lOOK, RL = 500 to -2V,
VIN = VIH Min. or VILMax.
10KH
Tc= -55°C
Input WW Voltage
Supply Current (All
inputs and outputs
open)
lOE301
Min.
Max.
-1140 -920
-1020 -840
-980
-920
-810
-735
-900
-700
-1025
10KH
lEE
Input HIGH Current
Input LOW Current
-920
-840
TA= +25°C
TA= +75°C
-1130
-1070
-810
-735
-700
mV
mV
mV
mV
-880
mV
mV
220
0.5
-170
-240
mV
mV
mV
mV
-1810 -1475
-240
-240
mV
mV
mV
220
0.5
-170
mV
mV
mV
mV
mV
mV
-1810 -1620
-1270
-1170
Units
mV
mV
mV
mV
-1950 -1600
-1950 -1590
TA=O°C
TA=0°Ct085°C
VIN = VIHMax.
VIN - VIL Min. (Except I/O Pins)
Commercial L (Low Power)
Commercial (Standard Power)
Military
-880
-1950 -1650
-1950 -1630
-1950 -1630
lOOK
IIH
IlL
lOOE301
Min.
Max.
-1050
Tc = +l25°C
-1165
TA = 0°Ct085°C
-1950 -1520
Tc= -55°C
-1950 -1480
TA=O°C
-1950 -1480
TA= +25°C
-1950 -1450
TA= +75°C
-1950 -1440
Tc= +125°C
lOOK
VIL
Vee
-5.2V±5%
100E
TA= +75°C
Tc = +125°C
TA = O°C to 85°C
VOL
Thmperature
O°Cto +75°C
Ambient
mV
!IA
!IA
mA
mA
mA
Notes:
1. See AC 'Illst Loads and Waveforms for test conditions.
2.
10-2
Commercialgrade is specified as ambient temperature with transverse
airflow greatertban 500 Iinearfeetperminute. Military grade is.pecified as case temperature.
-=,
CYIOE301
CYIOOE301
It;~
~~ONDUcroR
Capacitance [3]
Parameters
Description
InputCapacitance
Output Capacitance
CIN
CoUT
Min.
tYP.
Max.
4
8
10
6
Units
pF
pF
AC Test Load and Waveform[4, 5, 6, 7, 8, 9]
GND
ALL INPUT PULSES
Dour
INPUT
::: _--";;;2..;.;0%..;.;rf-
'--_~
VeE
RLI
C
t,
0.01 j.lFI
-2.0V
':'
E301-3
E301-4
Noles:
3. Thsted initially and after any design or process changes that may affect
these parameters.
4. VIL = VIL Min., VIH = VIH Max. on lOE version.
5. VIL = -l.N, VIH = -0.9Von lOOE version
6. RL = 5()Q, C < 5 pF (includes fIXture and stray capacitance).
7. All coaxial cables should be 50g with equal lengths. The delay of the
8.
9.
coaxial cables should be "nulled" out of the measurement.
t, = tf = 0.7 ns
All timing measurements are made from the 50% point of all wave-
forms.
Switching Characteristics Over the Operating Rangell ]
lOE301·4
lOOE301·4
Parameters
Description
Min.
Max.
lOE301·5
Min.
Max.
tpD
Input to Output PropagationDelay
tr
Output Rise Time
0.35
1.5
0.35
1.5
tf
Output Fall Time
0.35
1.5
0.35
1.5
4.0
lOE301L-6
lOOE301L-6
Max.
Units
6.0
ns
0.35
1.5
ns
0.35
1.5
ns
Min.
5.0
Switching Waveforms
INPUT
OUTPUT
~'~--=>k~----------------------------E301-5
10-3
..J
o
UJ
CYIOE301
CYI00E301
'riPRFSS
~ . SEMICONDUCTOR
Functional Logic Diagram (DIP Pinout)
INCREMENT-
0
1
2
4
3
5
6
7
8
9
10
11
12
14
13
16
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
r@ Vee
31
ITJ---{?
:>
2
FIRST-o
FUS E
64
NUMBERS
128
23
<
22
~
l:ET>-p,- --@]
96
1
192 224
~
<:
"2
3
<
2048
~ ---EI
256
320288
384 ~
448480
<:
2049
I/O
T
I/O
I
....,.....
512
576 544
~ --€I o
640 608
704672
736
2050
~
768
832
896 864
~ -0 o
960 992
~
1024
1068 1056
1152 1120
1216 1184
1248
2051
~>;D- -E!J o
...,.
2052
1280
13441312
1408 1376
1472 1440
1504
~ -EI
~::1568
~ --EI
16841632
1728 1696
1760
~
2054
<
o
1/0
I
~
1792
1856192
19201888
1984 1952
2016
a=r>-p,--0
~
<
2055
I/O
T
<
16
9
"2
<:
15
10
:>
<
14
11
.:>
<
13
E301-6
JEDECfuse number = first fuse number + increment
10-4
CYIOE301
CYIOOE301
~
~~PRFSS
~_.J, SEMICONDUCTOR
Ordering Information
tpD
I/O
(ns)
lEE
(rnA)
10KH
4
240
5
6
lOOK
4
6
240
170
240
170
Package
'JYpe
Operating
Range
CY10E301-4DC
D14
Commercial
CY10E301-4YC
Y64
CY10E301-5DMB
D14
CY10E301-5YMB
Y64
Ordering Code
CY1OE301L-6JC
J64
CY1OE301L-6PC
P13A
CY100E301-4DC
D14
CY100E301-4YC
Y64
CY100E301L-6JC
J64
CY100E301L-6PC
P13A
Military
Commercial
Commercial
Commercial
Document #: 3Kl-A-ooOll-B
II
...J
o
ill
10-5
CYIOE302
CYIOOE302
CYPRESS
SEMICONDUCTOR
Combinatorial ECL 16P4
Programmable Logic Device
Features
Functional Desoription
• Standard 16P4 pinout and
architecture
-16 inputs, 4 outputs
- User-programmable output
polarity
• Ultra high speed/standard power
- tPD 3 ns (max.)
- lEE 220 mA (max.)
• Low-powerversion
-tpD
4 ns (max.)
-lEE
170mA(max.)
• Both 10KH- and lOOK-compatible
110 versions available
• Enhanced test features
- Additional test input terms
-Additional test product terms
Cypress Semiconductor's Pill family offers the user the highest level of performance in ECL programmable logic devices.
These Pills are developed using an advancedprocess incorporating proven 'n-W
fuses.
The CYI0E302 is lOKH compatible and
the CYlOOE302 is lOOK compatible.
These PLDs implement the familiar sumof-products logic functions by selectively
programming cell elements to configure
the AND gates by disconnecting either the
true or complement input term. If all inputs are disconnected from an AND gate,
then a logical true will exist at the output of
this AND gate. An output polarity fuse is
also provided to allow an active WW to
=
=
=
=
occur if this fuse is blown. A security feature provides the user protection for the
implementation of proprietary logic.
When invoked by blowing the security
fuse, the contents of the array cannot be
accessed in the verify mode.
The CYlOE302 and CY1OOE302 can be
programmed using Cypress's QuickPro II
or other industry-standard programming
equipment. Programming support information can be obtained from local
CypressSemiconductor sales offices.
• Security fuse
Pin Configuration
Logic Block Diagram
PDIP/CerDIP
o
PLCC/CLCC
Top View
VCC2
0
Top View
___ o
z>8 __
I
I
o
o
VCC1
VCC2
NC
NC
o
o
I
I
I
--UJO--;!1!z
E302-1
E302-2
Selection Guide
10E302 3
l00E302-3
Maximum Input to Output Propagation Delay TIme (ns)
IEE(mA)
I
I
Commercial
Military
10-6
10E302-4
3
4
-220
220
-220
l00E302-4
10E302L 4
100E302L-4
4
4
220
170
CYIOE302
CYIOOE302
~
==--~
. ,
~NDUcroR
Maximum Ratings
Operating Range Referenced to Vee at Ground
(Above which the useful life may be impaired. BJqlosure to absolute maximum-rated conditions for extended penods may affect
device reliability. For user guidelines, not tested.)
Range
Commercial
(Standard,L)
Storage Temperature ................. - 65°Cto +150°C
Ambient Temperaturewith
Power Applied ....................... - 55°Cto +l25°C
Supply Voltage VEE to Vee ............... -7.0Vto +O.5V
InputVoJtage ............................. VEE to +O.5V
Output Current ............................... - 50 rnA
Electrical Characteristics
Parameters
VOH
VOL
Vrn
VIL
Temperature
O°Cto +75°C
Ambient
lOOK
O°Cto +85°C
Ambient
Commercial
(Standard, L)
Military
Vee
-5.2V+5%
-42V to -O.3V
100KH -55°Cto +l25°C
Case
-5.2V + 5%
Over the Operating Rangel 1]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Supply Current
(All inputs and
outputs open)
TA= O°C
TA= +25°C
-980
-810
mV
TA= +75°C
-920
-735
mV
Te= +125°C
-900
-700
Te= 55°C
lOOK, RL - 50g to -2Y,
VIN = Vrn Min. or VILMax.
lOKH, RL = 50g to -2Y,
VIN = Vrn Min. or VILMax.
Min.
Min.
Max.
Units
mV
mV
mV
-1025
TA = O°C to 85°C
lOOK, RL = 50g to -2Y,
VIN = Vrn Min. or VILMax.
10KH
lOOE302
lOE302
Max.
-1140 -920
-1020 -840
Temperature[2]
Test Conditions
lOKH, RL = 500 to - 2Y,
VIN = VrnMin.orVILMax.
-880
mV
Te = -55°C
-1950
-1650
mV
TA= O°C
-1950
-1630
mV
TA= +25°C
-1950
-1630
mV
TA = +75°C
-1950
-1600
mV
Te = +125°C
-1930
-1590
-1810
TA = O°C to 85°C
-1620
mV
mV
Te= -55°C
-1270
-920
mV
TA=O°C
-1170
-840
mV
TA= +25°C
TA= +75°C
-1130
mV
-1070
-810
-735
Te= +l25°C
TA=0°Ct085°C
-1050
-700
lOOK
10KH
Te= 55°C
-1950
-1520
mV
TA=O°C
-1950
-1480
mV
TA = +25°C
-1950
-1480
mV
TA = +75°C
-1950
-1450
mV
Te= +l25°C
-1950
-1440
lOOK
Irn
IlL
lEE
I/O
lOKH
Notes:
1. See AC Thst Loads and Waveforms for test conditions.
2.
10-7
mV
-1165
-880
220
-1475
mV
220
JlA
JlA
-170
-220
rnA
rnA
rnA
0.5
0.5
-170
-220
-220
mV
mV
-1810
TA = 0°Ct085°C
VIN = VrnMax.
VIN - VILMin.
Commercial L (Low Power)
Commercial (Standard Power)
Military
mV
Commercialgrade is specified as ambient temperature with transverse
airflowgreaterthan500Iinearfeetperminute.Militarygradeisspecifled as case temperature.
•
~
0
W
CYI0E302
CYI00E302
Capacitance[3]
Parameters
Description
eIN
Min.
InputCapacitance
Output Capacitance
CoUT
'JYp.
4
Max.
Units
8
6
10
pF
pF
AC Test Load and Wavefonn[4, 5, 6, 7, 8, 9]
GND
::~ ~~~~~2-0;.;.%-;.;.-fT-~
DoUTI'-_~
INPUT
ALL INPUT PULSES
1f~20%
80%
VeE
t,
-2.0V
O.01I'FI.
,.. VeE
If
E302-4
Notes:
3.
'Thsted initially and after any design or process changes that may affect
these parameters.
VJL = VJL Min., VIH = VIH Max. on 10KH version.
VJL= -1.7Y,VIH= -O.9Von100Kversion
RL = SO~ C < S pF (inclndes fixture and stray capacitance).
4.
S.
6.
7.
8.
9.
All coaxial cables should be SOIJ with eqnallengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
t f = tf = 0.7ns
All timing measurements are made from the SO% point of all wavefonns.
Switching Characteristics Over the Operating Rangel!]
lOE302-3
lOOE302-3
Description
Parameters
Min.
Max.
lOE302-4
lOOE302-4
Min.
Max.
lOE302L-4
lOOE302L-4
Min.
4.0
Max.
Units
4.0
ns
tpD
Input to Output Propagation Delay
tr
Output Rise Time
0.35
1.5
0.35
1.5
0.35
1.5
ns
tf
Output Fall Time
0.35
1.5
0.35
1.5
0.35
1.5
ns
3.0
Switching Wavefonns
INPUT
OUTPUT
~,~~------------------------------10-8
CY10E302
CY100E302
"-~
_"=
CYPRESS
- . F SEMICONDUCTOR
Functional Logic Diagram (DIP Pinout)
INCREMENT - 0
2
1
4
3
6
5
7
8
10
9
12
11
13
14
15
16
18
17
19
GJ--U
20
21
22
24
23
25
26
27
28
29
30
--8 Vee
31
<
23
2
:;:-
<
22
3
>
<
21
4
:;:-
FIRST-+-512
576
FUS E
640
NUMBERS
704
~
s::r
544
60B
~~~
---§] o
2050
76B
832 800
WP- ---0 o
896 864
960
~!~
2051
~ -@] o
1024
1088 1056
1152 1120
1216 1184
124B
2052
II
..J
o
~-{2]
1280
1344 1312
1408 1376
1472 1440
1504
<-
17
>
>
<
16
<
15
10
:;:-
<
14
11
'2
<
13
8
9
w
o
E302-6
JEDECfuse number = first fuse number + increment
10-9
CYIOE302
CYI00E302
Ordering Information
tPD
lEE
I/O
(os)
(mA)
lOKH
3
220
4
4
4
lOOK
3
4
4
220
220
170
220
220
170
CYlOE302-3DC
Package
1YJle
014
CY10E302-3YC
Y64
CYlOE302-4DC
014
CY10E302-4YC
Y64
CY10E302-4DMB
014
CY10E302-4YMB
Y64
CY10E302L-4PC
P13A
CY10E302L-4JC
J64
CY100E302-3DC
014
CY100E302-3YC
Y64
CY100E302-4DC
014
CY100E302-4YC
Y64
CY100E302L-4PC
P13A
CY100E302L-4JC
J64
Ordering Code
Document#: 38-A-00023-B
10-10
Operating
Range
Commercial
Commercial
Military
Commercial
Commercial
Commercial
Commercial
CYIOE383
CYIOIE383
CYPRESS
SEMICONDUcrOR
ECLrrTL Translator and
High-Speed Bus Driver
Features
Functional Description
• BiCMOS for optimum speed/power
• High speed (max.)
- 2.S ns tPD TTL-to-ECL
-3 ns tPDECL-to-TTL
• Low skew < ± Ins
• Can operate on single +SV supply
• Full-duplex ECUfTL data transmission
• Intemal2 kQ ECL pull-down
resistors on each ECL output
• Surface-mount PLCC/CLCC package
• VBB ECL reference voltage output
• Single- or dual-supply operation
• Capable of greater than 200IV ESD
• ECL cable/twisted pair driver
The CYI0/l01E383 is a new-generation
TTL-to-ECL and ECL-to-TTL logic level
translator designed for high-performance
systems. The device contains ten independent TTL-to-ECL and ten independent
ECL-to-TTL translators for high-speed
full-duplex data transmission, mixed logic,
and bus applications. The CYlO/lOIE383
is especially suited to drive ECL backplanes between TTL boards. The
CYlO/101E383 is implemented with differentialECL I/O to provide balanced low
noise operation over controlledimpedance
buses between TTL andlor ECL subsystems. In addition, the device has internal
output 2 kg pull-down resistors tied to
VEE to decrease the number of external
components. For system testing purposes
Logic Block Diagram
Pin Configuration
PLCClCLCC
Top View
vee
DO
DO
DIFFERENTIAL D1
ECl INPllTS D1
ECl SUPPLY D2
D2
co
~gBa~~6c~8g~~~~B~8g8~
~@@@@@@@@@~~~~~~~~~~~
01
Q2
os
os
or for driving light loads, the 2 kg is used
as the only termination thereby eliminating up to 20 external resistors. The part
meets standard 1OK/I0KHand 100Klogic
levels with the internal pull-down while
driving 50g to - 2Y.
The device is designed with ample ground
pins to reduce bounce, and has separate
ECL and TTL power/ground pins to reduce noise coupling between logic families. The parts can operate in single- or dual-supplyconfigurationswhilemaintaining
absolute lOK/lOKH and lOOK level
swings. The translators are offered in standard 10K/I0KH (10E) and lOOK (101E)
ECL-compatible versions with -5.2V or
- 4.5V power supply. The TTL I/O is fully
TTL compatible. The CYI0/lOIE383 is
packaged in 84-pin surface-mountable
PLCCs and CLCCs.
Q3
D4
D4
D5
D5
D6
as
D7
D7
DB
07
04
TIL OUTPUTS
TIL SUPPLY
06
os
Q8
DB
DB
Q8
09
010
010
011
011
D10
011
013
013
QlA
D14
014
015 DIFFERENTIAL
015
016 EClOUTPUTS
016 EClSUPPlY
a17
a17
a1B
01B
019
a19
TILiNPUTS D1S
TIL SUPPLY D16
D17
D1B
D19
~1 ~lMl ~1-1
10E383
101E383
ECLVBB
~
D12
D13
EClD5
EClll5
EClD6
ECl liS
ECLD7
ECl 117
EClOS
EClll9
EClD9
EClll9
EClVCC
ECla10
ECla10
EClVCCO
ECla11
EClO11
EClVCCO
ECl012
ECl012
EClVCCO
TIlGND
TIlQ4
TIlVCC
TIlQ3
TTLGND
TTL 02
TIlVCC
TIla1
TIlGND
TTL 00
TTLGND
TTLD19
TIlD1B
TIlD17
TTLD16
TIlD1S
TTLD14
TTLD13
TTLD12
TIlD11
TTL D10
E3B3-2
E3B3-1
10-11
•
...I
0
W
CYI0E383
CYIOIE383
Selection Guide
w\;_, .• ' ,
liP.$1I3 ~1
;"·UllEc3~"'a
..
::,
IOE383-3
IOIE383-3
3
4
270
"'::'.". ,
!:.'.: •. '. . :.:~'.<:'
Maximum Propagation Delay Time (ns) (TIL to ECL)
Maximum Propagation Delay Time (ns) (ECL to TTL)
Maximum Operating Current (rnA) Sum OfIEE and Icc
",',.":';:,·.:,,3;':::"
, '
·····:.·:Z7Q,:
Shaded area contains prelimmary mformation.
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature ................. - 65°C to +lS0°C
Ambient Thmperaturewith
Power Applied ....................... -SSOCto +l25°C
TTLSupplyVoltagetoGroundPotentiai ... - O.sVto +7.0V
TTLDCInputVoltage .................. - 3.0Vto +7.0V
ECLSupplyVoitageVEEtoECLVcc ..... -7.0Vto +O.sV
ECL Input Voltage ........................ VEE to +O.sV
ECL Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . - SO rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. > 2001 V
(per MIL-STD-883, Method 3015)
Latch-UpCurrent ............................
> 200 rnA
Operating Range
Range
Commercial
Ambient
Version Thmperature
10E
10K
O°Cto
lOKH
+7SoC
Commercial lOOK
101E
.~\ll~
10E
',:.' .....
. 10K
lOKH
I:
TTL
Vee
SV±
5%
EeL
VEE
-S.2V
±S%
I/O
-4.2Vto SV±
-S.46V 5%
O°Cto
+8S oC
--S.2V
±S%
-SS·C
to +125°c
'.'
case
SV±
5%
.
Shaded area contams prelimmary mformation.
".
ECL Electrical Characteristics Over the Operating Rangel1]
Parameters
VOH
Description
Output HIGH Voltage
Thmperature[2]
Thst Conditions
10E, RL = SOQ to - 2V
Tc= -~5~C
VIN = VrnMin.orVlLMax.
TA=O°C
TA= +2SoC
TA= +7S oC
Tc= +12:S"C. '.'
TA = O°C to 8S°C
VOL
Vrn
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
10lE RL = SOQ to - 2V,
VIN = Vrn Min. or VlLMax.
1OE, RL - 50Q to - 2V
Tc'" "';SS:c:
VIN = VrnMin. orVlLMax.
TA=O°C
TA= +25°C
TA = +7SoC
IOE383
Min.
Max.
IOIE383
Min.
Max.
-1140 :"900
....
.'
-1000
-960
-840
-810
mV
mV
-900
-735
mV
mV
mV
-880 "~700
-1025
-1920 -1670, ,
-1870 -1665
-880
..
.
-1850 -1650
-1830 -1625
lOlE
TA = O°C to 85°C
TC"'~5$°d'· ... :
TA=O°C
TA= +25°C
TA= +7SoC
-1165
7"1950 .-1540
-1950 -1480
-1950 -1475
-1950 -1450
mV
mV
mV
mV
,-1~.30 -1610.
Tc='+l25°C
-1810 -1620
10lE RL - SOQ to - 2V,
TA = O°C to 85°C
VIN=VrnMin.orVlLMax.
10E
:"1260 -900·
'Fe"; ::-SS",C
-1170 -840
TA=O°C
-1130 -810
TA = +25°C
-1070 -720
TA = +7S oC
.'
7"1030 :"700,
TC::;+l25°C'
'.,:
10E
Units
mV
"'.:'
-880
"
.': ......
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
, .....
TC"!'iel2:S°C> 1:':""'19~ -'l4SP .... , :>,.' mV
-1810 -1475 mV
TA = O°C to 85°C
101E
10-12
CYI0E383
CYIOIE383
~
.::::r:-: ~
~ircyPRESS
==,
SEMlCONDUCfOR
ECL Electrical Characteristics
Parameters
VBB
Over the Operating Rangel l ] (continued)
lemperature[2]
lest Conditions
lOEl:iJ
Description
Output Reference
Voltage
TA = 0°Ct075°C
Min.
-1.37
Max.
-1.18
TC= -55°C
-1.46
-1.32
-1.29
-1.14
Tc
101E[3]
= +l25°C
TA = 0°Ct085°C
Vcm [4]
Common Mode Voltage ± Vem with respect to VBB
Vdiff
In.eut Voltage
Differential
Required for Fun Output
Swing
1m
Input HIGH Current
VIN = Vm Max.
IlL
Input LOW Current
VIN = VILMin.
RpD
Pull-Down Resistor
Connected from All ECL TA =O°C to 75°C
Max.
-1.40
-1.23
1.0
mV
1.6
2.4
2.4
J.IA
J.IA
220
-0.5
170
1.6
170
kg
1.6
TA=0°Cto85°C
Supply Current (All inputs and outputs open)
V
150
220
Tc" -55°Cto
+l25°C
Units
V
1.0
150
-0.5
Outputs to VEE
lEE
Min.
2.4
-180
-180
rnA
..
Shaded area contams prelmunary information.
TTL Electrical Characteristics
Over the Operating Rangel l ]
lOE383
lOlE383
Description
Parameters
lest Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH
VOL
Output LOW Voltage
Vee
Vm
Input HIGH VoltagelS]
VIL
Input LOW VoltagelS]
Veo
Input Clamp Diode Voltage
los
Output Short-Circuit Current
Min.
= -3.2 rnA
Max.
Units
0.5
V
2.4
= Max., IOL = 16.0 rnA
V
2.0
V
0.8
= -lOrnA
Vee = Max., VOUT = 0.5V[6]
IJX
Input Load Current[7]
GND.:: VI':: Vee
Icc
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA, f
V
-1.5
lIN
V
-180
-40
-250
+20
J.IA
90
rnA
= f max.
rnA
Capacitance
Parameters
CIN
CoUT
Description
lest Conditions
InputCapacitance
Output Capacitance
Max.
Units
4
pF
5
pF
Notes:
1.
2.
3.
4.
See AC Thst Load aod Waveform for test conditions.
Commercialgrade is specified asambient temperature with traosverse
airflow greater thao 500 linear feet per minute. Military grade is specified as case temperature.
5.
6.
7.
Max. IBB = -1 mAo
The internal gain of the CY101/10E383 guaraotees that the output
voltage will not chaoge for common mode signals to ± 1V. Therefore,
input CMRR is infmitewithin the common mode raoge.
10-13
These are absolute values with respect to device ground.
Not more than one output should be tested at a time. Duration of the
short should not be more thao one second.
I/O pin leakage is the worst case ofIIX (where X = H or L).
•
...I
o
u.I
CYI0E383
CYIOIE383
TTL AC Test Load and Waveforml8]
Rl 2381l (319C MIL)
5V
Je.
OUTPUTo-----jp---i
10%
R2
CLPFI
1701l
(2361l MIL)
~3ns
INCWDlNG
JIGAND _
SCOPE -
Equivalenl to:
ES83-{1
THEVENIN EQUIVALENT (Commercial)
THEvENIN EQUIVALENT (Military)
991l
13BC
OUTPUT 0.0- - - ¥ h t l . - - - G O
OUTPUT 0.0--....,'1'\/\
.. _ _-00
2.1l8V
2.13Vthm
ECL AC Test Load and Waveforml9, 10, 11, 12, 13, 14]
GND
INPUT
ALL INPUT PULSES
VIH
Vee, Vcco
DoUT
VEE
RL
I
1f=
-tT-
VIL
CL
I,
0.01 ~Fl
If
-2.0V
VeE
E383-5
Notes:
8. TTL test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5 V; inpnt pulse levels of 0 to 3.0V; and output
loading of the specified IOrJIOH, and CL = 10 pR
9. VIL = VIL Min., Vrn = Vrn Max. on 10KH version.
10. VIL = -1.7Y, Vrn = -0.9Von 10lE version
11. ECL RL = 5()Q, CL < 5 pF (includes fIXture and stray capacitance).
ECL-to-TTL Switching Characteristics
12. All coaxial cables should he 500 with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
13. t, = tf= 0.7ns
14. All timing measurements are made from the 50% point of all waveforms.
Over the Operating Range
l0E383-3
lOlE383-3
Parameters
tpHL
Description
. '~li/ 'i'~':
Max.
Units
Propagation DelayTime
4
ns
Propagation DelayTIme
4
ns
Thst Conditions
Min.
Shaded area contains preliminary information.
TTL-to-ECL Switching Characteristics
Over the Operating Range
l0E383-3
lOlE383-3
Parameters
Description
Thst Conditions
tpLH
Propagation DelayTime
DntoQ",Qn
tpHL
Propagation Delay Time
DntoQn,Qn
tr
Output Rise TIme
20% to 80%
Output Fall Time
tf
Shaded area contains preliminary information.
Skew Time Switching Characteristics
Symbol
20% to 80%
,;~
"
"'~"
Min.
"·2S·
["':',
..... : . (:2:5
.i.
:0$$
.: 1.-7"
·,'0;35 ~;:····l'-i·
.:
. 1'.'1·
.;~
'
Max.
Units
3
ns
3
ns
0.35
1.7
ns
0.35
1.7
ns
(Sametest conditions as 1TL-to-ECL and ECL-to-TTL Electrical Characteristics)
Max.
Units
tSIcr
Data Skew Time ECL-Io-TTL
Characteristic
TTLQn to TTLQn+ 1
Thst Conditions
±l
ns
tSKE
Data Skew Time1TL-to-ECL
ECLQn, Q n to ECLQn+t. Q n+l
±1
ns
10-14
Min.
:
CYI0E383
CYIOIE383
.:;z
~=CYPRF.SS
~; SEMIcrnDUCTOR
Switching Waveforms
ECL-to·1TL Timing
f- ~ -I~j_~_iOi(
________________¥
""':-1
~
1.5V
E383·7
TTL-to·ECL Timing
4=~i""'---50%-"vl=_-""'l<--50%
--Skew Test (tSKT)
'ITiQn·to·'ITlQn+1
t'0~ -----j ..---_~_~V-tsKT::1Qn+1(TTL)
~
_ _ _ _ _ _ _ _ _ _ _ _J 1 . 5 V
II
...J
E383-9
.)
(50%
.J( 50%
I--- tSKE)
Qn+1(ECL)
Qn+1(ECL)
)(50%
50%
-tSKE-
I--- tSKE-
ECL·to·TIL Truth Table
-tsKE-
E383·10
TTL·to-ECL Truth Table
Inputs
Outputs
Inputs
Outputs
ECLDn
ECLDn
'ITLQn
'ITLDn
ECLQn
ECLQn
Open
Open
L
L
L
H
L
H
L
H
H
L
H
L
H
10-15
(.)
UJ
CYI0E383
CYIOIE383
Nominal Voltages
Ordering Information
TheCY1Ol/10E383 can be used in dual ±SV or single +SV supply
systems. The supply pins should be connected as shown in Tables 1
and2. This connection technique involves shifting up allECLsupply pins by SY. When operating in single-supply systems, the ECL
terminationvoltage level must also be shifted up by adding SY. For
example, if the termination is SO ohms to - 2V in a dual-supplysystem,thesingle+SVsystemshouldhaveSOohmsto+3Y.Iftheterminationis a thevenin type, then the resistor tied to ground is now
at + SV and the resistor tied to - SV is now at ground potential.
Consideration should be given to the power supply so that adequate bypassing is made to isolate the ECL output switching noise
from the supply. Having separate TIL and ECL +SV supply lines
will help to reduce the noise. Table 3 shows the CY1OE383 nominal
voltagesappJied in a 10K system.
Speed
(ns)
Single-Supply
System
Dual-Supply
System
TILVcc
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECL Vcc!Vceo
+S.OV
O.OV
ECLVEE
O.OV
-4.SV
Document#: 38-A-00023-C
'Thble 2. CY101E383 Nominal Voltages Applied in 101K System
Supply Pin
Single-Supply
System
Dual-Supply
System
TILVcc
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECL Vcc!Vceo
+S.OV
O.OV
O.OV
-S.2V
ECLVEE
'Thble 3. CY10E383 Nominal Voltages Applied in 10K System
Supply Pin
Single-Supply
System
Dual-Supply
System
TILVcc
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECL VccfVceo
+S.OV
O.OV
ECLVEE
O.OV
-S.2V
Operating
lYPe
Range
Shaded area contains preliminary infonnation.
'Thble 1. CY101E383 Nominal Voltages Applied in lOOK System
Supply Pin
Package
10-16
CYIOE422
CYIOOE422
CYPRESS
SEMICONDUCTOR
Features
• 256 x 4-bit organization
• Ultra high speed/standard power
-tAA = 3.5ns
-lEE = 220mA
• Low-powerversion
-tAA=5ns
-lEE = 150mA
• Both IOKH/IOK- and lOOK-compatible
I/O versions
• IOK/IOKII military version
• Capable of withstanding >200IVESD
256 X 4 EeL Static RAM
• On-chip voltage compensation for
improved noise margin
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CYI0E422 and CYI00E422
are 256 x 4 ECL RAMs designed for
scratch pad, control, and buffer storage
applications. Both parts are fully decoded
random access memories organized as
1024 words by 4 bits. The CYlOE422 is
1OKH/I0Kcompatible and is available in a
militaryversion .. The CYl00E422 is lOOK
compatible.
Logic Block Diagram
As
The four independent active LOW block
select (8) inputs control memory selection
and allow for memory expansion and ~
configuration. Each block select (Bl
through 84), when active, turns off the corresponding oUlput and memory block. The
read and write operations are controlled
by the state of the active LOW write enable (W) input. With W and 8x LOW, the
corresponding data at Dx is written into
the addressed location. To read, Wis held
HIGH, while 8 is held Law. Open emitter
oulputs allow for wired-OR connection to
expand or reconfigure the memory.
Pin Configurations (continuedon next page)
CerDIP
CerDIP
Top View
Top View
veCA
0_
Ba
Ql
Bl
An
a:
Al
0
w
~
a:
W
A2
An
A.,
0
0
()
w
I
I
I
I
3:
0
a:
I
I
I
i
I
I
Q2
B_
B2
Q-
O2
Vec
VeGA
W
Ql
01
I
Bl
As
MEMORY CELL ARRAY
0
Q3
9J!
As
i
62
01
A7
I
I
VEE
...I
E422-2
E422-3
w
E422-1
Selection Guide
IOE422-4
l00E422-3.5
3.5/4
220
Maximum Access Time (ns)
lEE Max. (rnA)
Commercial
IOE422-5
IOOE422-5
5
220
IOE422-7
lOOE422-7
7
L (Low Power)
150
150
Military (10K/lOKH only)
150
150
10-17
o
U.I
CY10E422
CY100E422
Pin ConrlgUrations (continued)
Quad Cerpaek
Top View
LCC
Top View
Imol~allll"
N
....
0
PLCClCLCC
Top View
Itt . . .
--§o8..s ..
(0
«<>«
11110> Z >UIIII
32i!j242322
02
4
B:!
01
02
4
21
20
10E422
100E422
7
19
18
W
As
17
16
03
83
04
03
A.t
Aa
As
W
10E422
l00E422
02
5
82
6
3
..
2 11128 27 26
25
03
24
83
02
01
01
23
04
22
NC
8
02
9
21
03
W
10
20
As
11
A.t
Aa
82
1011 12 13 1415
10E422
l00E422
NC
02
Q) .... w
0
N
«~«<
or"
19
12 13 14 15 16 17 18
E422-4
E422-5
Maximum Ratings
E422-6
Operating Range Referenced to Vee
(Above which the useful life may be impaired. Exposure to absolute maximum-rated conditions for extended penods may affect
device reliability. For user guidelines, not tested.)
StorageThmperature ................. - 65°C to +lS0°C
Ambient Thmperaturewith
PowerApplied....................... - 5S 0 Cto +l25°C
SupplyVoltageVEEtoVcc .............. -7.0Vto+0.SV
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. VEE to +O.SV
Output Current ............................... - SOmA
Ambient
'Thmperature
Range
I/O
Commercial 10KH/
(Standard, L) 10K
O°Cto 75°C
VEE
-S.2V±5%
QOCto +8SoC
-4.SV±0.3V
-55°Cto+125°C
Case
-S.2V±S%
Commercial lOOK
(Standard, L)
Military (L)
1OKH/
10K
Electrical Characteristics
Parameters
VOH
VOL
Over the Operating Range
Description
'Thst Conditions
Output HIGH Voltage
Output LOW Voltage
10EL2j RL = SOg to - 2V
VEE = - S.2Y,
Vee = VCCA = GND
VIN = V1H Max. or VJLMin.
lOOK RL = SOg to - 2Y,
VEE = - 4SY,Vee=VCCA=GND
VIN = V1H Max. or VILMin.
lOE RL = SOg to - 2V
VEE = - S.2Y,
Vee = VCCA= GND
VIN = V1H Max. orVJLMin.
lOOK RL = SOg to - 2Y,
VEE = - 4SY,Vee=VCCA=GND
VIN = V1H Max. or VILMin.
10-18
'Thmperature[l]
Min.
-1140
Max.
Units
Tc = - 55°C
- 900
mV
TA= O°C
-1000
- 840
mV
TA= +25°C
- 960
- 810
mV
TA= +7SoC
- 900
-73S
mV
Tc = +l25°C
- 880
-700
mV
TA = O°C to 85°C
-1025
-880
mV
Tc= - 5SoC
-1920 -1670
mV
TA= +O°C
-1870 -166S
mV
TA= +25°C
-1850 -1650
mV
TA= +7SoC
-1830 -1625
mV
Tc = +125°C
-1830 -1610
mV
TA=0°Ct085°C
-1810 -1620
mV
.
CYIOE422
CYIOOE422
~
_li!
~.F
CYPRESS
SEMlCONDUcrOR
Electrical Characteristics
Parameters
VIH
VIL
Over the Operating Range(continued)
'Thmperature[1 J
'Thst Conditions
- 1260
Max.
- 900
Units
Te= - 55°C
TA =O°C
- 1170
- 840
mV
TA = +25°C
- 1130
-810
mV
TA = +75°C
-1070
- 720
mV
lOOK VEE = - 4.5V
Vee = VeeA = GND
Te = +125°C
- 1030
-700
mV
TA = DoC to 85°C
- 1165
- 880
mV
lOE
VEE = - 5.2V
Vee = VeeA = GND
Te = - 55°C
-1950 - 1540
mV
TA = DoC
-1950
-1480
mV
TA = +25°C
- 1950 - 1475
mV
TA = +75°C
- 1950 - 1450
mV
Te = +125°C
- 1950 - 1450
mV
TA = DoC to 85°C
- 1810 - 1475
mV
Description
Input HIGH Voltage
lOE
VEE = - 5.2V
Vee = VeeA = GND
Input LOW Voltage
lOOK VEE = - 4.5V
Vee = VeeA = GND
Min.
IIH
Input HIGH Current
VIN = VIH Max.
IlL
Input LOW Current
VIN = VILMin.
lEE
Supply Current (All inputs
and outputs open)
Commercial/Military L(Low Power)
- 150
Commercia/Standard
- 220
mV
fAA
fAA
220
Binputs[3J
0.5
- 50
All other inputs
170
rnA
rnA
Capacitance [4J
Parameters
Description
CIN
Input Pin Capacitance
CoUT
Output Pin Capacitance
'JYp.
4
Max.[5J
Units
5
pF
5
6
pF
AC Test Loads and Waveforms [6, 7, 8, 9, 10, 11J
III
....I
o
GND
UJ
VIH
Vee
INPUT
DOUT
VEE
O.Q1IlF~
ALL INPUT PULSES
RL
r
V1L
c
20%
11I,
-2.0V
1f
20%
If
VEE
E422-7
E422-8
Notes:
1. Commercialgrade is specified as ambient temperature with transverse
air flow greater than 500 linear feet per minute. Military grade is specified as case temperature.
2. 10E specifications support both 10K and 10KH compatibility.
3. B inputs have pull-down resistors, all other inputs do nol have pulldowns. The value of the resistors is nominally 50 kQ, so the B inputs are
active when left floating.
4. Tested initially and after any design or process changes that may affect
these parameters.
5. For all packages except cerDIP (D40), which has maximums of
CIN = 8 pF, COUT = 9 pF.
VIL = VILMin., VIH = VIHMax. on 10Eversion.
VIL = -1.7V, VIH = -0.9V on lOOK version.
RL = 500, C < 5 pF (3-ns grade) or < 30pF(5-, 7-nsgrade). Includes
fixture and stray capacitance.
9. All coaxial cables should be 50n with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
10. tr = tf = 0.7 ns.
11. All timing measurements are made from the 50% point of all waveforms.
6.
7.
8.
10-19
CYI0E422
CYIOOE422
iI7~UCTOR
i
Switching Characteristics Over the Commercial Operating Range
lOOE422-3.5
lOE422-4
lOE422-5
lOOE422-5
lOE422-7
lOOE422-7
Max.
Min.
Max.
Min.
Max.
Units
tABS
Block Select to Output Delay
2.5
2.5
0.5
3.0
0.5
4.0
ns
tRBS
Block Select Recovery
2.5
2.5
0.5
3.0
0.5
4.0
ns
tAA
AddressAccess Time
3.5
4.0
1.2
5.0
1.2
7.0
tw
Write Pulse Width
3.5
tWSD
Data Set-Up to Write
tWHD
Data Hold to Write
tWSA
Parameters
Description
Min.
Max.
Min.
ns
3.5
5.0
ns
0.5
3.5
0.5
0.5
1.0
ns
1.0
1.0
1.0
1.0
ns
AddressSet-Up/Write
0.5
0.5
0.5
1.0
ns
tWHA
AddressHold/Write
1.0
1.0
1.0
1.0
ns
tWSBS
Block Select Set-Up/Write
0.5
0.5
0.5
1.0
ns
tWHBS
Block Select Hold/Write
1.0
1.0
1.0
1.0
tws
Write Disable
0.3
2.5
0.3
2.5
0.3
3.5
0.3
4.0
ns
tWR
Write Recovery
0.5
3.5
0.5
3.5
0.5
3.5
0.5
8.0
ns
tr
Output Rise Time
0.35
1.5
0.35
1.5
0.35
2.5
1.0
2.5
ns
tf
Output Fall Time
0.35
1.5
0.35
1.5
0.35
2.5
1.0
2.5
ns
ns
Switching Characteristics Over the Military Operating Range
lOE422-5
Parameters
Description
lOE422-7
Min.
Max.
Min.
Max.
Units
tABS
Block Select to Output Delay
0.5
4.0
0.5
4.0
ns
tRBS
Block Select Recovery
0.5
4.0
0.5
4.0
ns
tAA
Address Access Time
1.2
5.0
1.2
7.0
ns
tw
Write Pulse Width
5.0
5.0
tWSD
Data Set-Up to Write
0
0
ns
1.0
1.0
ns
ns
tWHD
Data Hold to Write
tWSA
AddressSet-Up/Write
1.0
1.0
ns
tWHA
AddressHold/Write
1.0
1.0
ns
twsBS
Block Select Set-Up/Write
0
0
ns
tWHBS
Block Select Hold/Write
1.0
1.0
tws
Write Disable
0.3
4.0
0.3
4.0
ns
tWR
Write Recovery
0.5
5.0
0.5
8.0
ns
tr
Output Rise Time
1.0
2.5
1.0
2.5
ns
tf
Output Fall Time
1.0
2.5
1.0
2.5
ns
10-20
ns
CY10E422
CY100E422
# ::~PRFSS
. ' SEMICONDUCTOR
Switching Waveforms
Read Mode
~%
'I---- '- =:a_ _
Q
~~tr
========~_"================t=AA=:'--=:'--==--=:-
ADDRESS
-=:-_=:-_==-_==--*--.I
.. '-====-=--=--=
Q
E422-9
Write Mode
~
ADDRESS
D
}t'5O%
50%~(
50%""
50%~ (
K
50%*
II
tWHD
w
tWSD
"-
-tWSA
Q
50%~
50%
tww
if:
~tWHA-
..J
o
tWHBS
UJ
if:
tWSBS
. . tws
tWA
E422-10
10-21
CY10E422
CY100E422
&:;~CYPRFSS
~_.,
SEMICONDUCTOR
'JYpical DC and AC Characteristics (l0E422/10E422UlOOE422/100E422L)
NO~ZEDSUPPLYCURRENT
NO~DSUPPLYCURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.2
w
1.1
1.1
.!!J
cw 1.0
N
::J
«
::;;
0.9
a:
0
z 0.8
-
-
....-- ---
~
w 1.0
w
i
l:::==-+--....,======!
0.9
a:
0.81----+------1
~
0.71----+------1
0.7
4.0
5.0
4.5
-55
6.0
5.5
1.2 r - -....- - - , , - - - , - - - - - ,
1.3
1.2
c 1.1
w
N
::J
«
::;;
1.0
L
a:
0
z
125
NO~ZEDACCESS TIME
VS. SUPPLY VOLTAGE
NO~DACCESS TIME
vs. AMBIENT TEMPERATURE
$
25
AMBIENTTEMPERATURE (OC)
SUPPLY VOLTAGE (V)
0.9
0.8 to--"
w
1.0
N
::J
«
::;;
a: 0.9
0
z
0.8
25
4.0
125
AMBIENT TEMPERATURE rC)
'fruth Table
Inputs
1.1
c
/
---
-55
$
Output
Bx
W
Dx
Qx
H
X
X
L
Disabled
Mode
L
L
H
L
WriteH
L
L
L
L
WriteL
L
H
X
Out
Read
10-22
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
6.0
CYIOE422
CYIOOE422
. .::;b
~iE CYPRESS
-:=:JF
SEMlCONDUCI'OR
Ordering Information
I/O
(mA)
tAA
(ns)
lOEllLJ
220
4
lEE
S
1S0
S
7
CYlOE422-4KC
Package
1YPe
K63
CYlOE422-4LC
L63
Ordering Code
CYlOE422-4YC
Y64
CYlOE422-SDC
D40
CYlOE422-SKC
K63
CYlOE422-SLC
L63
CYlOE422-SYC
Y64
CYlOE422L-SDC
D40
CYlOE422L-SJC
J64
CYlOE422L-SKC
K63
CYlOE422L-SLC
L63
CYlOE422L-SDMB
D40
CY10E422L-SKMB
K63
CYlOE422L-SYMB
Y64
CYlOE422L-7DC
D40
CYlOE422L-7JC
J64
CYlOE422L-7KC
K63
Operating
Range
Commercial
Commercial
Military
Commercial
CYlOE422L-7LC
lOOK
220
3.5
S
1S0
S
7
CYlOE422L-7DMB
D40
CYlOE422L-7KMB
K63
CYlOE422L-7YMB
Y64
CYlOOE422-3.SKC
K63
CYlOOE422-3.5LC
L63
CYlOOE422-3.5YC
Y64
CYlOOE422-SDC
D40
CYlOOE422-SKC
K63
CYlOOE422-SLC
L63
CYlOOE422-SYC
Y64
CYlO0E422L-SDC
D40
CYlOOE422L-SJC
J64
CYlOOE422L-SKC
K63
CYlOOE422L-SLC
L63
CY100E422L-7DC
D40
CY100E422L-7JC
J64
CY100E422L-7KC
K63
CYlOOE422L-7LC
L63
Military
Commercial
•
..J
ow
Commercial
Notes:
12. 10E specifications support both 10K and 10KH compatibility.
Document#: 38-A-00002-B
10-23
CYIOE470
CYIOOE470
CYPRESS
SEMICONDUCTOR
4096 x 1 EeL Static RAM
Features
Functional Description
• 4096 x 1-bit organization
• High speedllow power
-tAA = 5ns
-lEE = 200mA
• Both 10K· and 100K·compatible ver·
sions
• On.chip voltage compensation for im·
proved noise margin
• Open emitter output for ease of
memory expansion
• Industry·standard pinout
The Cypress CYlOE470 and CYlOOE470
are ECL RAMs designed for scratch pad,
control, and buffer storage applications.
Both parts are fully decoded random ac·
cess memories organized as 4096 words by
1 bit. The CYI0E470 is 10K-compatible.
The CYlOOE470 is lOOK-compatible.
Logic Block Diagram
The active LOW chip select (S) input controis memory selection and allows for
memory expansion. The read and write operations are controlled by the state of the
active LOW write enable (W) input. With
Wand S LOW, the data at D is written into
the addressed location. To read, W is held
HIGH, while Sis held LOW. Open emitter
outputs allow for wired-OR connection in
order to expand the memory.
Pin Configuration
CERDIP
Top View
Ao
A1
a:
~
0
A2
a:w
0
0
A3
@
~
'"
A5
0
C470-2
0
a:
Q
S
W
D
C470-1
Se Iecf Ion GUI'de
10E470·5
100E470·5
5
MaximumAccess Time (ns)
200
lEE Max. (rnA)
10-24
10E470·7
100E470·7
7
200
CYIOE470
CYIOOE470
·~PRESS
-iF
SEMICONDUCTOR
Maximum Ratings
Operating Range referenced to Vee
(Above which the useful life may be impaired. Exposure to absolutemaximumratedconditionsforextendedperiodsmayaffectdevice reliability. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperaturewith
Power Applied ........................ -55°Cto +125°C
Supply Voltage VEE to Vee ............... -7.0V to +O.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. VEE to +O.5V
Output Current ............................... -50mA
Range
Commercial
Version
lOE
Ambient
Temperature
O°Cto + 75°C
VEE
-5.2V:!:5%
Commercial
100E
O°Cto + 85°C
-4.5V:!: O.3V
Electrical Characteristics Over the Operating Range
Parameters
VOH
Description
Output HIGH Voltage
Output LOW Voltage
VOL
Input HIGH Voltage
VIH
Test Conditions
lOE RL = 50g to -2V
VEE = -5.2V
VIN = VIHMax. orVILMin.
lOOK RL = 50g to - 2V
VEE = -4.5V
VIN = VIH Max. or VIL Min.
10E RL = 50Q to -2V
VEE = -5.2V
VIN = VIH Max. or VIL Min.
lOOK RL = SOO to - 2V
VEE -4.5V
VIN = VIH Max. or VIL Min.
lOE
VEE = -S.2V
lOOK VEE
Input LOW Voltage
VIL
lOE
VEE
= -4.5V
= -S.2V
= -4.5V
= VIH Max.
= VILMin.
lOOK VEE
IIH
IlL
Input HIGH Current
Input LOW Current
VIN
VIN
lEE
Supply Current
(Allinputs and outputs open )
Commercial
Temperature[l]
Min.
-1000
Max.
-840
Units
mV
-960
-810
mV
-900
-720
mV
-1025
-880
mV
TA = O°C
-1870
-1665
mV
TA = +2S o C
-1850
-16S0
mV
TA = +75°C
-1830
-1625
mV
= O°C to 85°C
-1810
-1620
mV
TA
= O°C
= +25°C
TA = +7S o C
TA = O°C to 85°C
TA = O°C
TA = +25°C
TA = +75°C
TA = O°C to 85°C
-1145
-840
mV
TA
-110S
-810
mV
-1045
-720
mV
-1165
-880
mV
-1870
-1490
mV
-1850
-1475
mV
-1830
-14S0
mV
-1810
-1475
mV
220
170
!JA
!JA
!JA
= O°C
TA = +25°C
TA = +75°C
TA = O°C to 85°C
TA
TA
Sinputs
All other inputs
O.S
-50
-200
rnA
Capacitance [2]
Parameters
CIN
COUT
Description
Input Pin Capacitance
Output Pin Capacitance
Min.
Notes:
1. Commercialgrade is specified as ambient temperature with transverse
air flow greater than 500 lioear feet per minute.
2.
1O-2S
'lYp.
4
6
Max.
Units
pF
pF
Tested initially and after any design or process changes that may affect
these parameters.
III
..J
ow
CY10E470
CY100E470
&:~PRF$
~, SEMlCONDlJC'l'OR
AC Test Loads and Waveforms[3, 4, 5, 6, 7, 8]
GND
INPUT
-tl
V1H
Vcc
DouT
VeE
RL
Ie
V1L
~
o.01j.LFI
~
1f---20%
If
r
-2.0V
VEE
ALL INPUT PULSES
C470-4
C470-3
Switching Characteristics Over the Operating Range
lOE470-S
lOOE470-S
Parameters
Description
Min.
Max.
lOE470-7
lOOE470-7
Max.
Units
tAC
Input to Output Delay
3.0
Min.
3.5
ns
tRC
Chip Select Recovery
3.0
3.5
ns
tAA
AddressAccess Time
5.0
7.0
ns
tww
Write Pulse Width
tSD
5.0
7.0
ns
Data Set-Up to Write
0
0
ns
tHD
Data Hold to Write
0
0
ns
tSA
AddressSet-Up/Write
0
1.0
ns
tHA
AddressHold/Write
0
1.0
ns
tsc
Chip Select Set-Up/Write
0
0
ns
tHC
Chip Select Hold/Write
0
0
tws
Write Disable
3.0
3.5
ns
tWR
Write Recovery
5.0
8.0
ns
tr
Output Rise Time
1.0
2.5
1.0
2.5
ns
tf
Output Fall Time
1.0
2.5
1.0
2.5
ns
ns
Notes:
3.
4.
5.
6.
VIL = VILMin., Vrn = VrnMax.on lOEversion.
VIL= -1.7Y,Vrn= -0.9VonlOOKversion.
RL = 500, C < 30 pF (includes fixture and stray capacitance).
All coaxial cables should be 50g with equallengtbs. The delay of the
coaxial cables should be "nulled" out of the measurement.
7.
8.
10-26
t, = tf = 0.7ns.
All timing measurements are made from the 50% point of all waveforms.
CYI0E470
CYIOOE470
~
.
:~PRESS
~.iF' SEMICONDUCTOR
Switching Waveforms
Read Mode
't-
IAC;t
________________~2~0~
Q
80%
I,
ADDRESS
Q
C470-5
Write Mode
~
;i"50%
50%~ I(
ADDRESS
5~
50%j /{
D
K
50%
II
IHD
Vii
50%
ISD
I---tSA
Q
tww
50%; ~
I--tHA t HC
...J
oU.I
;10"
Isc
I-- Iws
IWR
C470-6
Truth Table
Inputs
Output
S
W
D
Q
Mode
H
X
X
L
Disabled
L
L
H
L
Write"H"
L
L
L
L
Write "13'
L
H
X
DOUT
Read
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
10-27
CYIOE470
CYI00E470
Ordering Information
lEE
Package
1.Ype
Operating
Range
CY10E470-5DC
D4
Commercial
CYIOE470-7DC
D4
5.0
CYlOOE470-5DC
D4
7.0
CY1OOE470-7DC
D4
tAA
I/O
(mA)
(ns)
Ordering Code
10K
200
5.0
7.0
lOOK
200
Document#: 38-A-OOOO3-B
10-28
Commercial
CYIOE474
CYIOOE474
CYPRESS
SEMICONDUCTOR
Features
• 1024 x 4-bit organization
• Ultra high speed/standard power
-tAA =3.5ns
-lEE
275mA
• Low-powerversion
-tAA=5ns
-lEE
190mA
• Both 10KH/10K- and lOOK-compatible
I/O versions
• 10K/10KH military version
• Capable ofwitbstanding >2001V ESD
=
=
l024x4 EeL
Static RAM
• On-chip voltage compensation for improved noise margin
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CYlOE474 and CY100E474
are lkx 4 ECL RAMs designed for scratch
pad, control, and buffer storage applications. These RAMs are developed by AspenSemiconductorCorporation, a subsidiaryofCypressSemiconductor. Both parts
are fully decoded random access memories organized as 1024 words by 4 bits. The
As
03
04
Ao
A1
A2
A3
A4
A5
NC
As
VEE
A5
a:
A3
A2
~
a:
~
w
0
a0
w
A1
Ao
0
~
a:
into the addressed location. To read, W is
held HIGH while S is held LOW. Open
emitter outputs allow for wired-OR connection to expand the memory.
I
I
I
I
I
MEMORY CELL ARRAY
I
I
I
(continued next page)
CerDIP
Top View
VeGA
A4
WandSLOW,thedataatD(1_4)iswr~n
Pin Configurations
Logic Block Diagram
Ag
CYI0E474is 1OKH/10Kcompatibleandis
available in a military version. The
CY100E474is 100Kcomptaible.
The active LOW chip select (S) input controls memory selection and allows for
memory expansion. The read and writeoperations are controlled by the state of the
active LOW write enable (W) input. With
I
I
I
I
I
I
CerDIP
Top View
Vee
O2
~
O2
01
04
03
O2
01
03
04
01
S
W
Ag
As
A7
O:!
Vee
VeGA
S
~E
Oa
W
~
Ag
As
A7
Ao
A1
A2
A6
NC
A5
A4
A3
E474-2
E474-3
0(1-4)
S
W
0(1-4)
E474-1
Selection Guide
Maximum Access Time (ns)
lEE Max. (rnA)
Commercial
10E474-4
100E474-3.5
3.5/4
10E474-5
100E474-5
5
275
275
10E474-7
100E474-7
7
L
190
190
Military (lOK/lOKH only)
190
190
10-29
II
-I
o
UJ
CYIOE474
CYIOOE474
2.~
~=CYPRESS
~F SEMlCamUCfOR
Pin Configurations (continued)
Quad Cerpack
Top View
PLCC/CLCC
TopVlew
LCC
Top View
oa$~»ar5
... '" is
Ao
04
As
Ao
4
A1
Oa
A4
A1
S
A3
A2
Aa
A4
10E474
100E474
A2
NC
NC
01
12 1a 14 1S 16 17 18
A2
A1
S
A4
As
10E474
100E474
02
21
Aa
0
oo~~rSc
As
Ao
04
20
Oa
02
01
19
18
17
10E474
100E474
9
S
W
16
10 11 12 1314 1S
W
U
COw
,...
CD CD
Zc(~c(c(c(
(,)cowo"com
zc(;!t'zc(c(c(
E474-4
E474-S
Maximum Ratings
E474-6
Operating Range Referenced to Vcc
(Abovewhich theusefullifemaybeimpaired. Exposure to absolute
maximumrated conditions for extended periods may affect device
reliability. For user guidelines, not tested.)
StorageThmperature ................. - 6S0Cto +lS0°C
Ambient Temperaturewith
PowerApplied ....................... - SSOCto +12SoC
Supply Voltage VEE to Vcc .............. - 7.0V to +O.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . .. VEE to + O.SV
Output Current ............................... -SOmA
Range
Commercial
(Standard,L)
Commercial
(Standard,L)
Military(L)
I/O
10KH/I0K
lOOK
10KH/lOK
Ambient
Thmperature
0°Ct07S0C
-S.2V±S%
QOCto + 8SoC
-4.5V±0.3V
-SSOCto
+l25°CCase
-S.2V±S%
VEE
Electrical Characteristics Over the Operating Range
Parameters
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Thst Conditions
lOE[2] RL = SOg to -2V
VEE = -S.2V,VCC=VCCA=GND
VIN = Vrn Max. or VlLMin.
100KRL = SOg to - 2V,
VEE = -4.5V,Vcc = VCCA = GND
VIN = VrnMax.orVlLMin.
lOE RL = SOg to -2V
VEE = -S.2V,VCC=VCCA=GND
VIN = VrnMax.orVILMin.
l00KRL = SOg to -2V,
VEE = -4.SV,Vcc= VCCA = GND
VIN = VrnMax.orVlLMin.
10-30
Thmperature[l]
Tc = -SsoC
Min.
-1140
-900
Units
mV
TA= O°C
-1000
-840
mV
TA= +25°C
-960
-810
mV
TA= +7SoC
-900
mV
Tc = +l25°C
-880
-73S
-700
TA = O°C to 8SoC
-1025
-880
mV
Tc= -SsoC
-1920 -1670
mV
TA= +O°C
-1870 -166S
mV
TA= +25°C
-18S0 -16S0
mV
TA= +7SoC
-1830 -1625
mV
Tc= +l25°C
-1830 -1610
mV
TA=0°Ct08SoC
-1810 -1620
mV
Max.
mV
CY10E474
CY100E474
::: : :.;z
~=
,
CYPRF.SS
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range(continued)
Description
Input HIGH Voltage
Parameters
VIH
Input LOW Voltage
VIL
IIH
IlL
Input HIGH Current
Input LOW Current
lEE
Supply Current (AIl
inputs and outputs open)
Thmperature[l]
Thst Conditions
lOE
VEE = -5.2V
Vee = VCCA = GND
Te = -55°C
Min.
-1260
Max.
-900
Units
mV
TA=O°C
-1170
-840
mV
TA= +25°C
-1130
-810
mV
TA= +75°C
-1070
-720
mV
Te= +125°C
-1030
-700
mV
lOOK VEE = -4.5V
TA = 0°Cto85°C
-1165
-880
mV
10E
VEE = -5.2V
Vee = VeCA = GND
Te= -55°C
-1950 -1540
mV
TA = O°C
-1950 -1480
mV
TA = +25°C
-1950 -1475
mV
TA = +75°C
-1950 -1450
mV
Te= +125°C
-1950 -1450
mV
Te = 0°Cto85°C
-1810 -1475
mV
lOOK VEE = -4.5V
Vee = VCCA = GND
VIN = VIH Max.
VIN = VJLMin.
Sinputs
All other inputs
Commercial/Military Standard L (Low Power)
CommercialStandard
0.5
-50
-190
-275
220
170
!AA
!AA
rnA
rnA
Capacitance [3]
CIN
Parameters
Description
Input PinCapacitance
COUT
Output Pin Capacitance
lYP.
MaxJ4]
Units
4
5
5
6
pF
pF
II
...J
o
AC Test Loads and Waveforms [5, 6, 7, 8, 9, 10]
U.I
GND
ALL INPUT PULSES
V1H
Vee
DoUT
INPUT
VEE
RL
Ie
V1L
20%
~Ir
O.D1 IlFJ
-2.0V
1f
20%
If
VEE
E474-8
E474-7
Notes:
1. Commercialgrade is specified as ambient temperature with traosverse
air flow greaterthao 500 linear feet per minute. Military grade is specified as case temperature.
2. lOE specifications support both 10K aod 10KH compatibility.
3. Thsted initially aod after aoy design or process chaoges that may affect
these parameters.
4. For all packages except cerDIP (D40), which has maximums of
CIN = 8 pF, Com = 9 pF.
5. VIL = VILMin., Vru = Vru Max. on 10E version.
6.
7.
VIL = -1.7V, Vru = -0.9V on lOOK version.
RL = 50Q C < 5 pF (3.5/4-ns grade) or < 30pF (5-, 7-ns grade). Includes fixture aod stray capacitaoce.
8. All coaxial cables should be 50Q with equallengtbs. The delay of the
coaxial cables should be "nulled" out of the measurement.
9. t, = tf= 0.7 os.
10. All timing measurements are made from the 50% point of all waveforms.
lO-31
CY10E474
CY100E474
· ir&PRESS
_ , SEMICONDUCTOR
Switching Characteristics
Overthe Commercial Operating Range
lOOE474-3.5
lOE474-7
lOOE474-7
Max.
Min.
Max.
Min.
Max.
Units
tAc
2.5
2.5
0.5
3.0
0.5
5.0
ns
tRc
Chip Select Recovery
2.5
2.5
0.5
3.0
0.5
5.0
ns
1.2
5.0
1.2
7.0
ns
tAA
Address Access Time
tww
Write Pulse Width
tSD
Min.
Min.
lOE474-5
lOOE474-5
Input to Output Delay
Parameters
Description
lOE474-4
Max.
4.0
3.5
5.0
5.0
5.0
5.0
ns
Data Set-Up to Write
0
0
0
0
ns
tHO
Data Hold to Write
0
0
0
1.0
ns
tSA
AddressSet-Up/Write
0
0
0
1.0
ns
tHA
AddressHoldlWrite
0
0
0
1.0
ns
tsc
Chip Select Set-Up/Write
0
0
0
0
ns
tHC
Chip Select HoldlWrite
0
0
0
1.0
tws
Write Disable
0.3
2.5
0.3
2.5
0.3
3.0
0.3
6.5
ns
tWR
Write Recovery
0.5
3.5
0.5
3.5
0.5
5.0
0.5
7.0
ns
tf
Output Rise Time
0.35
1.5
0.35
1.5
0.35
2.5
1.0
2.5
ns
tf
Output Fall Time
0.35
1.5
0.35
1.5
0.35
2.5
1.0
2.5
ns
Switching Characteristics
Over the Military Operating Range
lOE474-5
Parameters
tAC
ns
Description
Input to Output Delay
tRC
Chip Select Recovery
lOE474-7
Min.
MaL
Min.
Max.
Units
0.5
4.0
0.5
5.0
ns
0.5
4.0
0.5
5.0
ns
5.0
1.2
7.0
ns
tAA
Address Access Time
1.2
tww
Write Pulse Width
5.0
5.0
ns
tSD
Data Set-Up to Write
0
0
ns
tHD
Data Hold to Write
1.0
1.0
ns
tSA
AddressSet-Up/Write
1.0
1.0
ns
tHA
AddressHoldlWrite
1.0
1.0
ns
tsc
Chip Select Set-Up/Write
0
0
ns
tHC
Chip Select HoldlWrite
1.0
1.0
tws
Write Disable
0.3
4.0
0.3
6.5
ns
tWR
Write Recovery
0.5
5.0
0.5
7.0
ns
tf
Output Rise Time
1.0
2.5
1.0
2.5
ns
tf
Output Fall Time
1.0
2.5
1.0
2.5
ns
10-32
ns
CYIOE474
CYI00E474
-~
.'~DUCrOR
Switching Waveforms
Read Mode
Q
-*,--,.==--==--==-==--:
--~--~~~~i~
ADDRESS
..
Q
~
~' ~
tM - - - - - - - - - -....
E474 9
Write Mode
~~
ADDRESS
D
) Ii'50%
50~ (
50%j
50%~ (
K.
50%
., tHO
w
tso
") r
I---tSA
Q
tsc
50%
50%
It'
I - - - tHA -
tww
...J
ow
tHC
..Iijt"
I-- tws
tWR
E474-10
10-33
CY10E474
CY100E474
'JYpical DC and AC Characteristics (lOE474/10E474IJIOOE474/100E474L)
NO~DSUPPLYCURRENT
NORNUUJZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.2
w
1.1
1.1
~
c
w
1.0
N
~
«
:::;:
~
0.9
~
~
w 1.0~:;;;;;;__-1--""~=;
~
w
c
~ o.g~----+-----I
II:~
II:
oz
0
z 0.8
0.71------+--------1
0.7
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
-55
6.0
NORNUUJZEDACCESST~
NORNUUJZEDACCESST~
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.0
0
o.g
II:
z
0.8
-
-55
----
1.1
w
1.0
N
~
«
:::;:
.../'
II:
0.9
0
z
0.8
4.0
25
125
AMBIENT TEMPERATURE (OC)
Truth Table
Inputs
$
c
/
N
125
1.2.----r--,----,--.,
~ 1.2
cw 1.1
~
25
AMBIENT TEMPERATURE (OC)
M
1.3
«
:::;:
0.8 ~----+-----I
Output
S
W
D
Q
Mode
H
X
X
L
Disabled
L
L
H
L
WriteH
L
L
L
L
WriteL
L
H
X
DOUT
Read
10-34
4.5
5.0
5.5
SUPPLY VOLTAGE M
6.0
CYIOE474
CYI00E474
L~PRFSS
~,
SEMlCONDUCfOR
Ordering Information
tAA
lEE
I/O
lOOK
Operating
Range
CY100E474-3.5LC
L63
Commercial
CYlO0E474- 3.5YC
Y64
CY100E474-3.5KC
K63
(ns)
Ordering Code
275
3.5
5
190
5
7
lOElUJ
Package
'JYpe
(mA)
275
4
5
190
5
7
CYlOOE474-5LC
L63
CY100E474-5DC
D40
CY100E474-5YC
Y64
CY100E474-5KC
K63
CYlOOE474L-5LC
L63
CY100E474L-5DC
D40
CYlOOE474L-5JC
J64
CYlOOE474L-5KC
K63
CYlOOE474L-7LC
L63
CYlOOE474L-7DC
D40
CYlOOE474L-7JC
J64
CYlOOE474L-7KC
K63
CY10E474-4LC
L63
CY10E474-4YC
Y64
CY10E474-4KC
K63
CYlOE474-5LC
L63
CYlOE474-5DC
D40
CYlOE474-5YC
Y64
CYlOE474-5KC
K63
CYlOE474L-5LC
L63
CYlOE474L-5DC
D40
CYlOE474L-5JC
J64
CY10E474L-5KC
K63
CY10E474L-5DMB
D40
CYlOE474L-5KMB
K63
CYlOE474L-5YMB
Y64
CYlOE474L-7LC
L63
CYlOE474L-7DC
D40
CYlOE474L-7JC
J64
CYlOE474L-7KC
K63
CYlOE474L-7DMB
D40
CYlOE474L-7KMB
K63
CYlOE474L-7YMB
Y64
Commercial
Commercial
Commercial
II
...I
o
w
Military
Commercial
Military
Notes:
11. lOE specifications support both 10K and lOKH compatibility.
Document#: 38-A-00OO4-C
10-35
CYIOIE484
CYIOE484
CYIOOE484
CYPRESS
SEMICONDUCTOR
Features
• 4096 x 4·blt organization
• Ultra high speed/standard power
-tAA=4,Sns
=
-lEE 320mA
• Low·power version
-tAA = 7, 10 ns
-lEE
=200mA
• Both 10KII/10K· and lOOK·compat·
ible I/O versions
• On.chip voltage compensation for im·
proved noise margin
• Capable of withstanding >2001V ESD
4096 x 4 EeL Static RAM
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CY101E484, CY10E484, and
CY1OOE484 are 4K x 4 EeL RAMs designed for scratch pad, control, and buffer
storage applications. These parts are fully
decoded random access memoriesorganized as 4096 words by 4 bits. The
CYI0E484 is 10KH-/l0K.-compatible. The
CY1OOE484 is lOOK2001VESD
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CYl0E494, CY100E494, and
CYlO1E494 are 16K x 4 ECL RAMs designed for scratch pad, control, and buffer
storage applications. Both parts are fully
decoded random access memories organized as 16,384 words by 4 bits. The
CYlOE494 is lOKH/lOK compatible, the
CY100E494 is lOOK compatible, and the
CY101E494 has lOOK-compatible levels
with a - 5.2V supply voltage.
The active LOW chip select (S) input controls memory selection and allows for
memory expansion. The read and write operations are controlled by the state of the
active LOW write enable (W) input. With
Wand SLOW, the data atD(1-4) iswri!!5ln
into the addressed location. Th read, W is
held HIGH while S is held LOW. Open
emitter outputs allow for wired-OR connection to expand the memory.
Logic Block Diagram
A7 As
Pin Configurations
As
Al0 All A12 A13
01
02
03
04
01
~
Ao
Al
A2
A3
A4
A5
A6
Vec
VCGA
a:
w
~
a:
0
I
if
W
I
I
I
I
S
w
I
I
I
0
~
I
I
I
NC
A13
A12
All
Ao
Al
A2
A3
A4
Oa
I
I
I
iii
Al0
VEE
As
As
A7
A6
A5
a.
MEMORY CELL ARRAY
0
~
E494-2
a:
0(1-4)
5
iii
0(1-4)
Selection Guide
MaximumAccess Time (ns)
Commercial
Maximum,IEE(mA)
..
lOE494-7
lOlE494-7
7
180
L
Military (lOKllOKH only)
lOE494-8
lOOE494-8
lOlE494-8
lOE494-l0
lOOE494-10
lOlE494-10
lOE494-l2
lOOE494-12
lOlE494-12
8
180
10
180
12
190
Shaded area contams prehmmary mformatlOn.
10-43
135
190
II
..J
0
W
CYIOE494
CYI00E494
CYIOIE494
Pin Conragurations (continued)
SOJ
ThpView
Rectangular Cerpak
ThpView
~
01
02
Os
04
01
O2
Vee
VCCA
03
04
Ao
Al
A2
As
E4B4-3
W
NC
A 13
A12
All
Al0
VEE
As
As
A7
A6
As
A4
E4B4-4
Maximum Ratings
Operating Range Referenced to Vcc
(Abovewhich theusefullifemaybeimpaired. Exposuretoabsolute
maximum rated conditions for extended periods may affect device
reliability. Foruser guidelines, not tested.)
StorageThmperature .................. - 65°Cto +150°C
Ambient Thmperaturewith
PowerApplied ........................ - 55°Cto +l25°C
Supply Voltage VEE to Vee............... -7.0Vto +O.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. VEE to + 0.5V
Output Current ................................ - 50 rnA
Static Discharge Voltage
(perMIL-STD-883C,Method3015) ............. > 2001V
Ambient
Thmperature
Range
Version
Commercial lOE
O°Cto + 75°C
Commercial
100E
O°Cto + 85°C
Commercial
lOlE
10E ,"
'Military"
",,'
Vee
-5.ZV::!:5%
-4.5V::!:
0.3V
-5.ZV::!:5%
O°Cto + 75°C
.. 55"Cto, +12s°C I,..S.ZV:t'5% :
I
Cas",
"
Shaded area contains preliminary information.
Electrical Characteristics Over the Operating Range
Parameters
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Thst Conditions
lOEI·] RL - 500 to - ZV
VEE = -5.ZV,
VIN = Vrn Max. orVJLMin.
l00E RL - 500 to - Zv,
VEE = - 4.5Y, 101El3) VEE = - 5.ZV
VIN = VrnMax. orVJLMin.
10ERL - 500 to - ZV
VEE = -5.ZV
VIN = VrnMax.orVJLMin.
100ERL - 500 to - Zv,
VEE = -4.5V,
101E(3) VEE = - S.Zv,
VIN = VrnMax. orVJLMin.
Notes:
1. Commercialgradeisspecified asambient temperaturewitb traosverse
air flow greater tbaoSoo linear feet per minute. Militarygrade is specifled as case temperature.
ThmperatnreL"]
Te= -55°C
TA =O°C
TA= +25°C
TA= +75°C
Te = +l25°C
TA = O°Cto85°C
Min.
-1140
-1000
-960
-900
-880
1025
Te= -55°C
TA=O°C
TA= +25°C
TA= +75°C
Te= +l25°C
TA = O°C to 85°C
-1920
-1870
-1850
-1830
-1830
-1810
Max.
-840
-810
-735
-700
880
Units
mV
mV
mV
mV
mV
mV
-1670
-1665
-1650
-1625
-1610
-1620
mV
mV
mV
mV
mV
mV
-900
2. lOE specifications support botb 10K and lOKH compatibility.
3. 10lE specifications support lOOK compatibility witb VEE = -S.2V,
TA = O°C to 75°C.
10-44
·
CYIOE494
CYIOOE494
CYIOIE494
·~PRFSS
~,
SEMICONDUClDR
Electrical Characteristics Over the Operating Range (continued)
Parameters
VIH
Description
Input HIGH Voltage
Input LOW Voltage
VIL
IIH
IlL
Input HIGH Current
Input LOW Current
lEE
Supply Current (All inputs
and outputs open)
Thst Conditions
10E
VEE = -5.2V
100E VEE - -4.5V
IOlE[3] VEE = -5.2V
10E
VEE = -5.2V
100E VEE - -4.5V
10lE[3] VEE = -5.2V
VIN - VIHMax.
VIN - VILMin.
I
Thmperature!1J
Tc= -55°C
TA = O°C
TA= +25°C
TA= +75°C
Tc= +l25°C
TA = O°C to 85°C
Min.
-1260
-1170
-1130
-1070
-1030
-1165
Max.
-900
-840
-810
-720
-700
-880
Units
mV
mV
mV
mV
mV
mV
Tc = - 55°C
TA=O°C
TA = +25°C
TA = +75°C
Tc = +l25°C
TA = 0°Ct085°C
-1950
-1950
-1950
-1950
-1950
-1810
-1540
-1480
-1475
-1450
-1450
-1475
mV
mV
mV
mV
mV
mV
S
Allothers
0.5
50
-135
180
-190
220
170
t-tA
t-tA
Commercial L (Low Power)
CommercialStandard
Military Standard
rnA
rnA
rnA
Capacitance [4]
Parameters
Description
Input Pin Capacitance
Output Pin Capacitance
CIN
CoUT
lYP.
MaxJ5]
3
6
7
5
Units
pF
pF
AC Test Loads and Waveforms [6, 7, 8, 9, 10, 11]
...I
GND
o
V1H
INPUT
---:If---=-
V1L _ _.;;2..;.0%;";'°1
1
t,
ALL INPUT PULSES
80%
k%
II
~.;;2..;.0%;....-_ _
If
-2.0V
E494-5
E494-6
Note.:
4. Thsted initially and after any design or process changes that may affect
these parameters.
5. For all packages except CerDIP (D42), which has maximums of CIN =
S pF, CoUT = 9 pF.
6. VIL= VILMin., Vrn = VrnMax. on lOEversion.
7. VIL = -1.7Y, Vrn = -0.9Von lOOK version.
RL = 50g, C < 5pF (7-, S·nsgrade) or < 30pF(1O·, 12-nsgrade).Ineludes fixture and stray capacitance.
9. All coaxial cables should be 500 with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
10. tr = tf = 0.7 us.
11. All timing measurements are made from the 50% point of all waveforms.
S.
10-45
UJ
CY10E494
CY100E494
CY101E494
&:~PRFSS
~,
SEMICONDUCTOR
Switching Characteristics
Over the Operating Range
lOE494-7
lOlE494-7
Parameters
lOE494-8
lOOE494-8
lOlE494-8
Min.
lOE494-10
lOOE494-10
lO1E494-10
lOE494-12
lOOE494-12
lOlE494-12
Min.
Min.
Max.
Units
tAC
Input to Output Delay
5.0
5.0
5.0
5.0
ns
tRC
Chip Select RecoveIY
5.0
5.0
5.0
5.0
ns
tAA
Address Access Time
7.0
8.0
10.0
12.0
tww
Write Pulse Width
5.0
6.0
tSD
Data Set-Up to Write
1.0
1.0
tHD
Data Hold to Write
1.0
1.0
tSA
AddressSet-Up/Write
1.0
tHA
AddressHold/Write
tsc
Chip SelectSet-Up/Write
tHC
Chip Select Hold/Write
tws
Write Disable
5.0
5.0
5.0
5.0
tWR
Write RecoveIY
8.0
8.0
12.0
14.0
ns
tr
Output Rise Time
0.35
1.5
0.35
1.5
0.35
1.5
0.75
2.5
ns
tf
Output FaIl Time
0.35
1.5
0.35
1.5
0.35
1.5
0.75
2.5
ns
Description
Min.
Max.
Max.
Max.
ns
6.0
8.0
ns
2.0
2.0
ns
2.0
2.0
ns
1.0
2.0
2.0
ns
1.0
1.0
2.0
2.0
ns
1.0
1.0
2.0
2.0
ns
1.0
2.0
2.0
ns
1.0
10-46
ns
CY10E494
CY100E494
CY101E494
~
~~
CYPRESS
- ? SEMICONDUCTOR
_=
Switching Waveforms
Read Mode
Q
=~~~_-_-_~....;I_"-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_tA ~=_-==_-:=_-:~_-=~_-=~_-:::~~-I*-"'-====--=--=
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Truth Table
Inputs
Output
S
W
D
Q
Mode
H
X
X
L
Disabled
L
L
H
L
WriteH
L
L
L
L
WriteL
L
H
X
DOUT
Read
10-47
CYIOE494
CYI00E494
CYIOIE494
.;:~
~-CYPRESS
~.,
SEMlCCt-IDUCIOR
Ordering Information
Package
tAA
lEE
Version
(rnA)
(ns)
Ordering Code
'JYpe
10E
180
7
CYlOE494-7DC
CYlOE494-7KC
CYlOE494-7VC
CYlOE494-8DC
CYlOE494-8KC
CYI0E494-8VC
CYI0E494-10DC
CYI0E494-10KC
CYI0E494-10VC
CYI0E494L-12DC
CYlOE494L-12KC
D42
KSO
V21
D42
CYlOE494L-12VC
V21
8
10
12
135
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8
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CYI00E494-8DC
CYl00E494-8KC
CY100E494-8VC
CYI00E494-lODC
CYl00E494-lOKC
CY100E494-10VC
CY100E494L-12DC
10
135
10lE
180
12
7
8
10
135
12
Commercial
KSO
V21
D42
KSO
V21
D42
KSO
' 'CYlUE4~4"'71-o:OMB: "'"Dil2;",
,'C¥lUE494';;'1(jIW'B" ,,::gsO>,
12
CY100E494L-12VC
CY100E494L-12KC
CY101E494-7DC
CYI01E494-7KC
CYI01E494-7VC
CYI01E494-8DC
CY101E494-8KC
CY101E494-8VC
CYI0lE494-10DC
CYI0lE494-10KC
CYI01E494-lOVC
CY101E494L-12DC
CY101E494L-12KC
CY101E494L-12VC
Operating
Range
'}J42
.'~<:.
D42
K80
V21
D42
f~~~;:""
1\,
.•',
I:· :,;:,:"
Commercial
KSO
V21
D42
V21
KSO
D42
Commercial
KSO
V21
D42
K80
V21
D42
KSO
V21
D42
KSO
V21
Shaded area contains preliminary information.
Docwnent#: 38-A-00009-C
10-48
INFO
SRAMs
PROMs
PlDs
I'
FIFOs
lOGIC
COMM
"
RISC
MODULES
ECl
MiliTARY ~~~~~~~~~~~~
TOOlS~~~~~~~~~~~~
QUALITY ~~~~~~~~~~~~
PACKAGES
~~~~~~~~~~~
Section Contents
Bus Interface Products
Page Number
Device Number
Description
VIC068
VAC068
VIC64
CY7C964
VMEbus Interface Controller .................................................. .
VMEbus Address Controller .................................................. .
VMEbus Interface Controller witb D64 Functionality ..............................
Bus Interface Logic Circuit ....................................................
11-1
11-16
11-27
11-39
•
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Complete VMEbus interface controller and arbiter
- 58 internal registers provide configuration control and status of
~Ebusandlocaloperations
- Drives arbitration, interrupt, address modifier utility, strobe, address lines A07through AOI and
data lines D07 through DOO directly, and provides signals for control
logic to drive remaining address
and data lines
- Direct connection to 68xxx family
and mappable to non-68xxx processors
• Complete master/slave capability
- Supports read, write, write posting,
and block transfers
- Accommodates ~Ebus timing requirements with internal digital
delay line ('I.-clock granularity)
- Programmable metastability delay
- Programmable data acquisition delays
- Provides timeout timers for local
bus and ~Ebus transactions_
• Interleaved block transfers over
VMEbus
- Acts as DMA master on local bus
VlC068A
VMEbus Interface Controller
- Programmable burst count, transfer length, and interleaved period
inte"al
- Supports local module-based
DMA.
• Arbitration support
- Supports single-level, priority and
round robin arbitration
- Supports fair request option as requester_
• Interrupt support
- Complete support for the VMEbus
interrupts: interrupter and interrupt handler
- Seven local interrupt lines
- 8-level interrupt priority encode
-Thtal 0129 interrupts mapped
tbrough the VIC068A.
• Miscellaneous features
- Refresh option for local DRAM
- Four broadcast location monitors
- Four module-specific location monitors
- Eight interprocessor communications registers
- PGA or QFP packages
- Compatible with IEEE Specification 1014, Rev. C
- Supports RMC operations
Functional Description
The VMEbus ioterface controller
(VIC068A) is a siogle chip designed to
minimize the cost and board area requirementsand to maximize performance of the
VMEbus interface of a VMEbus master/
slave module. This can be implemented on
either a 8-bit, 16-bit, or 32-bit VMEbus
system. The VIC068A was designed usiog
high-performancestandard cells on an advanced 1 micron CMOS process. The
VIC068A performs all VMEbus system
controller functions plus many others,
which simplify the development of a VMEbus interface. The VIC068A utilizes patented on-chip output buffers. These
CMOS high-drive buffers provide direct
connection to the address and data lioes. In
addition to these signals, the VI C068A
connects directly to the arbitration, interrupt, address modifier, utility and strobe
lioes. Signals are provided which control
data direction and latch functions needed
fora 32-bit implementation.
The VIC068A was developed through the
efforts of a consortium of board vendors,
under the auspices of the VMEbus International Trade Association (VITA). The
VIC068A thus iosures compatibility between boards designed by different manufacturers.
•
11-1
--!;~
~0NDUCf0R
-- "
VIC068A
PRELIMINARY
Pin Configurations
A
B
c
D
E
F
Pin Grid Array (PGA)
Bottom View
H
G
J
K
L
M
N
p
R
VSS
IPl2
UACKO
LlRQ2
LlRQ5
ASIZl
ASIZO
SLSELl
WORD
FlACK
NJ2
A04
VOO
VSS
IRQ4
L06
BLT
Jli[1
VDO
iJRQl
LlRQ4
LlRQ5
ICFSEL
MWB
NJl
A03
AOS
NJ7
IROO
iR07
2
LD2
L05
OEOLK
IPLO
LAEN
LlROO
LlRQ7
VSS
SLSELO
VSS
NJ6
IRQl
IRQ2
IRae
ACFAlL
3
LOl
lD3
LD7
LOCATOR
PIN
IROO
VDO
IACKOUT
LA7
LDO
lD4
SYSFAIL
S'i'SRESE'
OTACK
LA3
lAS
LAS
IACKIN
lACK
AMO
LA2
LM
VSS
vss
AS
AMl
LAl
LNJ
VCC7
VSS
AM2
AM3
8
es
OSACKl
os
VDO
LWORO
AM4
9
PAS
LBERR
RESET
BEAR
WRITE
AM5
10
OSACKO
R/W
FCl
BA2
OSl
OSO
11
HALT
RMC
LBR
BBSY
BAl
BAO
12
FC2
SIZO
SCQN
SIZl
IRESET
LAOO
LBG
ABEN
VOO
7
BGOIN
BA3
VSS
13
DOl
VSS7
BGOOUT
BG31N
BGllN
BCiJ'[
14
004
002
BG30UT
BG20UT
SYSCLK
vss
15
VDO
vssa
VCC5
000
LEDI
OOIR
LWDENIN
OENO
D06
Dos
LEOO
UWDENIN
SWDEN
ISOBE
007
11-2
6
BG2IN
VSS
DOS
5
BG10UT
LADI
CLK64M
4
-----.
.
;~PRESS
--=-"
VIC068A
PRELIMINARY
SEMICONDU(''TOR
Pin Configurations (continued)
Quad Flat P.tck (QFP)
ThpView
vss
VSS
119
VSS
VSS
LBG
IRESET
iPLO
IPLJ
11B
117
iPl2
116
SCON
VDD
115
114
AaEN
LAEN
LlAKO
u"Rch
LlRQ2
LlRQ3
LlRQ4
LlRQ5
"'Ci'RQ6
DRll7
=,
ASIZQ
ICFSEL
§'L§ET..1
VSS
SLSELO
WORD
FCiACK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
113
LADO
112
111
LADI
LEDI
110
VDD
LEDO
109
108
107
106
105
104
103
DDIR
UWDENIN
VSS
LWDENIN
i5ENo
SWDEN
102
ISOBE
101
100
VDD
VSS
D07
99
MWB
98
97
A1
96
vss
CLK64M
D06
D05
D04
A2
95
94
A3
93
VDD
D03
D02
A4
92
D01
VDD
91
AS
90
89
DOD
BGOUT3
A6
A7
88
87
VSS
lRtI1
86
85
iRa2
iRa3
84
IRQ4
83
VSS
82
VSS
81
VSS
BGOUT2
BGOUT1
BGOUTO
SYSCLK
BGIN3
BGIN2
VSS
VSS
VIC068A-1
11-3
III
en
m
;:)
41;~
. . . . . .,
PRELIMINARY
~CONDUCIDR
VIC068A
VIC068A on 68030 Board
512/256K X 36 ORAM
512/256KX 36 ORAM
68030
4 JEOEC EPROMs
DRAM I/O
~------------------r-------------~Fm
024- 031
Fm
543
016-023
Fm
543
Fm
245
I~0
Fm
245
543
I
008-016
Al-A7
SYSCLK
DOO - D07
LOO - LD7
AMO-AM5
WriI~~L~~~T:~~R
BGiiN. BGiOUT, BRi, aBSY
LAO -LA7
lACK. IACKIN. IACKOUT
scaN
IRQ1.IRQ7. ACFAIL.
SYSFAIL
STSRESET
SLSELO
SLSEL1
ICFSEL
A31-A24
A23-16
Al5-A08
11-4
LlACKO
LlRQ1-LlRQ7
VIC068A-2
~
~~PRESS
~, SEMlCONDUClDR
PRELIMINARY
Signal Descriptions
BG3IN - BGOIN
VMEbus Signals
Input:
Output:
Drive:
Thefollowingsignals are VMEbus specified signals that are driven
and received directly by the VlC068A For complete definitions
and description of these signals refer to the VMEbus specification
(IEEE 1014).
Yes
No
None
The VMEbus daisy-chained Bus-Grant-In signals.
BG30UT - BGOOUT
SYSRESET
Input:
Output:
Drive:
VIC068A
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
The VMEbus system reset signal. A LOWlevel on this signal resets
the internal logic of the VlC068A and asserts the signals HALT
and RESET. These signals remain asserted for a minimum of 200
ms. If the VlC068A is configured as VMEbus system controller, a
LOW level on IRESET asserts SYSRESET for a minimum of 200
ms.
No
Yes
8mA
The VMEbusdaisy-chainedBus-Grant-Outsignais.
BBSY
Input:
Output:
Drive:
Yes
Yes,rescinding
64mA
The VMEbus Bus-Busy signal.
Input:
Output:
Drive:
BCLR
Yes
No
None
The VMEbus AC fail signal. This signal should be driven by the
VMEbus power monitor (if installed). The VIC068A can be enabled to provide a local interrupt on the assertion of this signal.
Yes
Yes,3-state
64mA
The VMEbus Bus-Clear signal.
D7-DO
SYSFAIL
Input:
Output:
Drive:
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
As an output the SYSFAILsignai is asserted when HALT has been
detected asserted for more than 4,ms (by a source other then the
VIC068A).
Yes
Yes,3-state
64mA
The VMEbus low-order data lines.
A7-Al
Input:
Output:
Drive
Yes
Yes,3-state
64mA
This signal is asserted by the VlC068A after a global reset. It may
be masked by clearing ICR6[6j or by setting ICR7[7j. The
VIC068A can also be enabled to provide a local interrupt on the
assertion of this signal.
The VMEbuslow-order address lines.
SYSCLK
AS
Input:
Output:
Drive:
Input:
Output
Drive:
No
Yes,3-state
64mA
Yes
Yes,rescinding
64mA
The VMEbus system clock signal. This signal is driven by the
VlC068Awhen configured as system controller (SCONasserted).
The frequency driven is 1/4th the frequency delivered to the
VlC068A CLK64M signal. Th deliver the required 16 MHz on this
signal, the VlC068A must run at 64 MHz. The VlC068A does not
use this signal internally for any purpose.
The VMEbus Address Strobe signal.
BRJ-BRO
The VMEbus Data Strobe signals.
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
The VMEbus Bus Requestsignals.
DSl- DSO
Input:
Output:
Drive:
Yes
Yes, rescinding
64mA
DTACK
Input:
Output:
Drive:
Yes
Yes,rescinding
64mA
The VMEbus Data-1tansfer-Acknowledgesignal.
11-5
II
PRELIMINARY
BERR
Input:
Output:
Drive:
LD7 -LDO
Yes
Yes, rescinding
64mA
Input:
Output:
Drive:
The VMEbus Bus-Error signal.
Yes
Yes, 3-state
SmA
The Local Data 7-0 signals. These signals are typically connected to the local processor data lines D(7:0) through an isolation buffer. VIC06SA register accesses are also made through
these data signals.
WRITE
Input:
Output:
Drive:
VIC068A
Yes
Yes, 3-state
64mA
LA7-LAO
Input:
Output:
Drive:
The VMEbus Data-Direction signal.
LWORD
Yes
Yes, 3-state
SmA
The VMEbus Long-word signal.
The Local Address 7-0 signals. These signals are typically connected to the local processor address lines. VIC06SA registers
are also addressed through these signals. When actinSe local
bus master, the VIC06SA drives these lines with the
signal
to supply the local address.
AMS-AMO
"CS
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
Yes, 3-state
64mA
Yes
Yes,3-state
64mA
Input:
Output:
Drive:
The VMEbus Address-Modifier signals.
The VIC068A chip select signal. This signal should be asserted
whenever access to the VI0l68A interual registers is required.
lACK
Input:
Output:
Drive:
Yes
No
None
m
Yes
Yes, 3-state
64mA
Input:
Output:
Drive:
The VMEbus Interrupt Acknowledge signal.
Yes
Yes, rescinding
SmA
The VMEbus daisy-chained Interrupt-Acknowledge-In signal.
The physica1lprocessoraddressstrube. This signal isused toqualify
an incoming address when performing VMEbusmasteroperations
or register operations. This signal is driven when becoming the local bus master and performing slave transfers, DRAM refresh,
slave block transfers and block transfers with local DMA. When
acting as an output, the minimum assertion and negation timing for
this signal is configured by the Local Bus Timing Register.
iACKOut
DS"
iACKiN
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
No
None
Input:
Output:
Drive:
No
Yes
SmA
The VMEbus daisy-chained Interrupt-Acknowledge-Out signal.
IRQ7 - IRijO
Input:
Output:
Drive:
Yes
Yes, open conector
64mA
The VMEbus Interrupt request signals.
Yes
Yes, rescinding
SmA
The local data strobe. This signal is used to qualify incoming data
when performing VMEbus master operations or register operations. This signal is driven when becoming the local bus master and
performing slave transfers, DRAM refresh, slave block transfers,
and block transferswithlocalDMA. When acting as an output, the
minimum assertion and negation timing for this signal is directed
by the Local Bus Timing Register.
DmKI, DSACKO
Local Signals
These signals define the local bus structure of the VIOl68A
They are modeled after Motorola 6SK signals.
Input:
Output:
Drive:
Yes
Yes, rescinding
SmA
The local data-size-acknowledge signals. One or both of these signals should be asserted to the VIC068A whenever the VIC06SA is
local bus master to acknowledge the successful completion ofeach
cycle ofa slave transfer, slave block transfer, or block transfers with
local DMA. The VIC068A asserts one or both of these signals to
11-6
~CYPRFSS
~~,
PRELIMINARY
VIC068A
SEMICONDUCIDR
acknowledgethe successful completion of a VMEbusmaster operation (after receiving the VMEbus DTACKsignal). The following
should be noted about the DSACKl/Osignals:
RiW indicates data direction for VMEbus master cycles. In this
case, WRITE reflects the value of R/WAnassertedconditionindicates a write operation.
• The VIC068A only asserts a 16 bit DSACKi code when the
WORD signal is asserted indicating access to a D16 VMEbus
resource is complete.
• The VIC068A treats the assertion of any DSACKl/O signal as
a 32-bit acknowledge for slave accesses.
• The VIC068A does not directly support 16 or 8-bit local port
sizes.
• The VIC068A always asserts both DSACKs for register accesses. as well as for interrupt acknowledge cycles.
FC2,FCl
Input:
Output:
Drive:
The local function code signals. These signals identify the type of
local cycle in progress. As inputs, they should reflect the type of operations in terms of User/Supervisory Code/Data. They may be
connected directly to the Motorola FCZ/l outputs for 68000-30
processors. For the 68040, the FC2/1 inputs may be connected to
the TM2/1 outputs respectively. Additional qualification may be
requiredfor 68040 applications since the 68040 uses previouslyreservedlunusedfunction codes.
LBERR
Input Yes
Output: Yes,rescinding
Drive:8mA
The local bus-error signal. This signal should be asserted to the
VIC068A whenever the VIC068A is local bus master to acknowledge the unsuccessful completion of a cycle of a slave transfer,
slave block transfer, and block transfers with local DMA in which
case the VIC068A asserts the VMEbus BERR signal. The
VIC068Aasserts this signal to acknowledge the unsuccessful completion of a VMEbus master operation (after receiving the VMEbus BERRsignal).
RESET
FCI
Description
0
0
1
1
0
1
0
1
User Data
User Program
Supervisory Data
Supervisory Program
Asoutputs, the VIC068A drives these signals whenever local bus
master to indicate the type oflocal cycle the VIC068A is performing.
FCI
Description
FC2
1
1
The local reset indication signal. This signal is asserted whenever
the VIC068A is in a reset condition. an internal, global, or system
reset causes the VIC068A to assert RESET for a minimum of ZOO
ms.Iftheresetcondition continues for longer then 200 ms, RESET
begins additional 200 ms timeouts until all reset conditions are
cleared.
HALT
Yes
Yes, Open collector
8mA
The "halted" condition indication signal. This signal, along with
RESET, is asserted during reset conditions. An internal, global,
and system reset causes the VIC068A to assert HALT for a minimumof200ms. Ifthe reset condition continues for longer then ZOO
ms,HALTbeginsan additional ZOO ms timeouts until all reset conditions are cleared. Assertion of HALT for greater than 4 ms by
anything other then the VIC068A causes the VIC068A to assert
SYSFAIL
HALT may be configured to assert during dead-lock conditions
along with LBERR to initiate a retry sequence for Motorola 68K
processors.
RJW
Input:
Output:
Drive:
B::2
o
o
Input No
Output: Yes, Open-collector
Drive:8mA
Input:
Output:
Drive:
Yes
Yes, rescinding
8mA
Yes
Yes,rescinding
8mA
Thelocaldata direction signal. Thissignalisdrivenwhile VIC068A
is a local bus master to indicate local data direction. As an input,
o
1
o
Slave Block 1ransfer
LocalDMA
Slave Access
DRAM Refresh
1
SIZ1,SIZO
Input:
Output:
Drive:
Yes
Yes,rescinding
8mA
The local data size signals. As inputs, these signals should identify
the width of the VMEbus data to be transferred. The SIZi signals
should not be used to indicate the physical port size of the slave device (DI6, or D32). This is done with the WORD signal. As outputs, they are driven by the VI C068A as local bus master to identify the width of the incoming data.
SIZI
SIZO
Data Width
o
o
0
1
1
0
1
Long Word
Byte
Word
3-Byte
1
LBR
Input:
Output:
Drive:
No
Yes
8mA
The local bus request signal. This signal is asserted whenever the
VIC068A desires mastership of the local bus. This signal remains
asserted for the entire bus tenure.
Localbusmastership is requested when each of the followingoperations is desired:
• Standard slave accesses
11-7
III
PRELIMINARY
BiZI,DiZO
• Slave block transactions
• Block transfers with local DMA
• DRAM refresh
Yes
No
None
The local bus grant signaI. The signal should be asserted in response the assertion of the ~ signal. The VIC068A does not
incOIporate a local bus grant acknowledge protocol so, the I:BU
signal should remain asserted for the duration of~.
MWB
Input:
Output:
Drive:
1
FcrAN
Yes
No
None
SLSELl, SLSELO
Yes
No
None
The slave select signals. These signals indicate the VIC068A has
been selected to perform a VMEbus slave operation. When qualified by AS' and valid AM codes, the VIC068A requests the local
bus to perform the slave cycle. These signals are usually asserted
by VMEbus-to-local address decoders.
The SLSELl/O signals may be used independently of each other
to provide unique slave characteristics as defined by the Slave Select Control registers.
ICFSEL
Input:
Output:
Drive:
1
ASIm
Address Size
o
1
o
User defined
A32
A16
A24
1
The AS'IZI7IJ signals are also used for cycle acknowledge signals
for module-based DMA transfers. During a module-based DMA
transfer, the AS'IZli si al is used as a data-transfer-acknowledge
signaI (analogous to
. The ASIZr signal is used as a buserror signal (analogous to
wmm
The local interrupt acknowledge signal. This signal should be asserted (qualified by PAS) to acknowledge all VIC068A-generated
local interrupts.
Input:
Output:
Drive:
The VMEbus address size signals. These signals should be driven
to indicate the VMEbus address size of master VMEbus transfers. The address size information is issued on the VMEbus AM
codes. The assertion ofAS'IZli indicates an A16 transaction. The
assertion of ASIZr indicates an A32 transaction. Asserting neither indicates an A24 transaction. User-defmed address spaces
may be accessed by asserting both AS'IZI7IJ signals. In this case,
the AM codes are issued according to the programming of the
Address Modifier Source Register.
ASIZI
o
o
Yes
No
None
The "Module-Wants-Bus" signal. This signal should be asserted by
local resources to begin a VMEbus transaction. Whenqualifiedby
the PAS signal, the VIC06SA asserts the VMEbus lmIsignal. This
signal is usually asserted by local-to-VMEbus address decoders.
Input:
Output:
Drive:
Yes
No
None
Input:
Output:
Drive:
Lii(j
Input:
Output:
Drive:
VIC068A
Yes
No
None
Input:
Output:
Drive:
Yes
No
None
The VMEbus data-width control signal. This signal, when asserted, indicates the requested VMEbus transaction should be
treated as a D16 data path. When negated, the VMEbus data
path is assumed to be D32. This signal should be used to configure VMEbus data-width for master cycles only. Data-width for
slave cycles is configured in the Slave Select Control Registers.
This signal is also used to configure the data-width for block
transfers with local DMA. When this signal is asserted during the
block transfer initiation cycle, the block transfer is assumed to be
a D16 block transfer.
This signal may be changed dynamically for individual transfers,
or strapped WW at power-up for permanent D16 operation. If
womJ is strapped WW at power-up, the VIC06SA is configured as a D16 slave independent of the slave configuration in
the Slave Select Control Registers.
WOID'5 should not be used to indicate data size (i.e., byte, word,
or long-word) only local data port size (i.e., D16 or D32).
BLT
The Interprocessor Communication Facility (ICF) Select signal.
This signal is used to indicate that the ICF functions of the
VIC06SA have been selected. These include the ICF r~ters
and the ICF switch interrupts. This signal is qualified with AS and
A16 AM codes (A16/Supervisory for global switches).
Input:
Output:
Drive:
Yes
Yes, open-collector
SmA
The Block transfer with local DMA indication signal. This signal
is used to indicate that a block transfer with local DMA is in
progress. This signal remains asserted for the entire block transfer including interle~eriods with the exception of local page
boundary crossings. BLT toggles during local boundary crossings
to increment the extemallA( +:S) counters.
If the m:!f signal is asserted simultaneously with the ~ signal
and BTCR[7) is set, a module-based DMA transfer is performed.
l1-S
~
'rCYPRESS
~F
PRELIMINARY
DEDLK
Input:
Output:
Drive:
IRESET
No
Yes
SmA
Input:
Output:
Drive:
The dead-lock indication signaL This signal is used to indicate a
dead-lockcondition has occurred. This signal should be used by 10cal logic to remove its request for the VMEbus. DEDLKremains
asserted until the slave transaction is complete.
DEDLK is also asserted to indicate that a VMEbus master cycle is
being attempted during the interleave period of a block transfer
with local DMA, without the dual path feature enabled. In this
case, DEDLK is asserted while MWB is asserted. If, during the interleave period, the MWB signal is asserted after the VMEbus has
been re-obtained, the VIC06SA will assert DEDLK for the duration of the burst.
IPL2, IPL!, IPLO
Inputs:
Output:
Drive:
IPLOonly
Yes, open-collector
SmA
During the assertion of IRESET, IPLO becomes an input. If IPLO
is asserted at this time, a global reset is performed.
LIRQ7 - LIRQl
IRESET contains internal hysteresis to allow the connection ofthis
signal to an external RC network for power-up resets.
SCON
Yes
No
None
The system controller enabling signal. This signal is used to configure the VIC068A as VMEbus system controller. This signal must
be strapped LOW at power-up and remain LOW for VIC068A to
reliably assume the role ofVMEbus system controller.
CLK64M
Input:
Output:
Drive:
Input
No
None
The VIC068Amasterclock input. This 64-MHzclock input is used
to clock internal arbitration, timing, and delay functions within the
VIC068A
Buffer Control Signals
Yes
LIRQ20nly
SmA (LIRQ2 only)
The local interrupt request signals. These signals serve as local interrupt request signals for the VIC06SA If enabled to handle the
particular local interrupt, the VIC06SA in turn issues a processor
interrupt with the IPLi signals at the assertion of a LIRQL Extensive configuration oflocal interrupts is allowed through the Local
Interrupt Configuration Registers.
LIRQ2may also be configured to issue periodic "heartbeat" interrupts at user defined intervals.
LIACKO
Input:
Output:
Drive:
Yes
No
None
The internal reset signaL This signal is used to issue both internal
and global resets to the VIC068A If asserted with IPLO, a global
reset is performed. If asserted without IPLO, an internal reset is
performed. All internal state machines and selected register bits
are reset during the assertion of IRESET. HALT and RESET are
both asserted during the assertion ofIRESET. If configured as system controller, SYSRESET is also asserted during the assertion of
IRESET.
Input:
Output:
Drive:
The local priority encoded interrupt request signals. These signals
are asserted to interrupt the local processor. All local VIC06SAinterrupts are issued with these signals. These signals are meant to
emulate the Motorola 6SK interrupt algorithms. The assertion of
one or more of these signals indicate a single interrupt with a priority given by the negative-logic value of the IPLi signals. Level 7 is
the highest priority. These signals are open-collector to allow the
wire-ORingofmuitiple interrupt sources.
Input:
Output:
Drive:
VIC068A
SEMICONDUCTOR
No
Yes
SmA
These signals control the latching and enabling of the external address and data latches and buffers. For block transfers with local
DMA, some of these signals are used to control the counting and
enablingof external counters required for page boundarycrossing.
ABEN
Input:
Output:
Drive:
No
Yes
8mA
The VMEbus Address Bus ENable signal. This signal is used to enable the external VMEbus address drivers for VMEbusmaster operations. It is typically connected to the OEAB input of a '543 addresstransceivers.
LAEN
The "autovectoring" indication signal. This signal is asserted when
the VIC06SA is configured to allow the interrupting device to
place its status/lD vector on the local data bus in response to a
VIC06SA-handledlocal interrupt acknowledge. This signal maybe
used to signal a autovectored interrupt acknowledge cycle for
6S020/30/4O processors. This signal may be connected directly to
the AVEC signal for these processors.
Input:
Output:
Drive:
No
Yes
8mA
The Local Address ENable signaL This signal is used to enable the
externallocal address drivers for slave accesses. It is typically connected to the OEBA input of a '543 address transceivers through
an inverter.
Note that this signal is an active-HIGH signal.
11-9
II
PRELIMINARY
read and slave write cycles. This signal is typically connected to the
OEBA input of the upper '543 data latches.
LADO
Input:
Output:
Drive:
VIC068A
No
Yes
8mA
LEDO
The Latch ADdress Out signal. This signal is used to latch the outgoing VMEbus address for VMEbus master operations. When this
signal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in a fall-through
state. This allows direct connection to the '543 address driver
LEAB input. LADO is very important for proper operation of
master write posting and block transfers with interleave periods.
For these operations, VIC068A may use LADO in combination
with LADI and ABEN to temporarily store the contents of a
VMEbus address during intervening slave accesses.
Input:
Output:
Drive:
The LatchEnableDataOutsignal. Thissignallatchestheoutgoing
VMEbus dataformasterwrite and slave read cycles. When thissignal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in a fall-through
state. This allows direct connection to the '543 address driver
LEAB input.This signal is used in conjunction with LEDI to temporarilystore outgoing master write post data (data switch-back).
LADI
LEDI
Input:
Output:
Drive:
Input:
Output:
Drive:
No
Yes
8mA
No
Yes
8mA
No
Yes
8mA
The LatchADdress In signal. This signal is used to latch the incoming VMEbus address for slave accesses. When this signal is asserted (HIGH), it is assumed that the latches are in a latched state.
When negated, the latches should be in a fall-through state. This
allows direct connection to the '543 address driver LEBA input.
LADI is used in conjunction with LADO to temporarily store outgoing VMEbus master transaction addresses during intervening
slave accesses.
The Latch Enable Data In signal. This signal latches the incoming
VMEbusdata formasterread and slave write cycles. When thissignal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in afall-through
state. This allows direct connection to the '543 address driver
LEBAinput.This signal is used in conjunction with LEDO to temporarily store outgoing master write post data.
DENO
Input:
Output:
Drive:
Input:
Output:
Drive:
No
Yes
8mA
The Data ENable Out signal. This signal enables data onto the
VMEbus data bus for master write and slave read cycles. This signal is typically connected to the OEAB input of the '543 data
latches.
No
Yes
8mA
The Lower Word Data ENable IN signal. This signal enables data
onto the lower word of the local data bus LD(15:8) for master read
and slave write cycles. This signal is typically connected to the
OEBAinput of the '543 lower data latch.
Input:
Output:
Drive:
SWDEN
No
Yes
8mA
The Upper Word Data ENable IN signal. This signal enables data
onto the upper word of the local data bus LD(31:16) for master
No
Yes
8mA
The SWap Data ENable signal. This signal, along with the ISOBE
signal, provides byte lane switching. It provides for swapping
LD(31:16) to LD(15:0). This signal is typically connected to the
EN input of the '245 swap buffer.
DDIR
Input:
Output:
Drive:
UWDENIN
No
Yes
8mA
The ISOlation Buffer Enable signal. This signal, along with the
SWDEN signal, provides byte lane switching. This signal is typically connected to the EN input of the '245 isolation buffer.
Input:
Output:
Drive:
LWDENIN
Input:
Output:
Drive:
ISOBE
No
Yes
8mA
The Data DIRection signal. This signal provides the data direction
(i.e., read/write) information to the isolation and swap buffers.
When asserted, buffers should be configured in thelocal-to-VMEbus (A-to-B) direction. This signal is typically connected to the
DIR input of the '245. isolation/swap buffers.
11-10
~
~~
PRELIMINARY
=-=
CYPRESS
,
SEMlCONDUClDR
VIC068A
VIC068A Register Values After Reset Operations
Address
(bex)
03
VIICR
VMEbus Interrupter Interrupt Control Register
11111000
Internal
Reset
11111 •••
07-lF
CICRl-7
VMEbus Interrupt Control Registers 1-7
11111**'
11111 •••
11111*'*
23
DMASR
DMA Status Register
11111000
11111 .**
11111'"
37-3F
LlCRl-7
Local Interrupt Control Registers 1-7
loooXOOO
1"'**X***
1 ***X***
43
ICGSICR
ICGS Interrupt Control Register
11111000
11111 ._.
11111*"
47
ICMSICR
ICMS Interrupt Control Register
11111000
11111**'
11111*'*
4B
EGlCR
Error Group Interrupt Control Register
11111000
11111'"
11111'"
4F
ICGSVBR
ECGS Vector Base Register
00001111
00001111
00001111
00001111
Name
Global
Reset
Description
System
Reset
11111'"
53
ICMSVBR
ICGS Vector Base Register
00001111
00001111
57
LlVBR
Local Interrupt VEctor Base Register
00001111
00001111
00001111
5B
EGlVBR
Error Group Interrupt Vector Base Register
00001111
00001111
00001111
SF
ICSR
Interprocessor Communications Switch Register
00000000
""0000
00000000
63-73
ICRO-4
InterprocessorCommunicationsRegisters 0-4
00000000
00000000
00000000
77
ICRS
InterprocessorCommunicationsRegister 5
Version
Version
Version
7B
ICR6
InterprocessorCommunicationsRegister 6
Xll111XX
X1111111
X1111110
7F
ICR7
InterprocessorCommunicationsRegister7
OOXOOOOO
XOXXXXXX
OOXOOOOO
83
VIRSR
VMEbus Interrupt Request Status Register
00000000
VIVBRl-7
VMEbus Interrupt Vector Base Regtisters 1-7
00001111
*******0
********
00000000
87-9F
A3
TIR
'fransfer Timeout Register
01101000
01101000
01101000
A7
LBTR
Local Bus Timing Register
00000000
********
********
AB
BTDR
Block 'fransfer Definition Register
00000000
00000000
00000000
00001111
AF
ICR
Interface Configuration Register
00000000
00000000
00000000
B3
ARCR
Arbiter/Requester Configuration Register
01100000
011'0000
011'0000
B7
AMSR
Address Modifier Source Register
00000000
00000000
00000000
BB
BESR
Bus Error Status Register
XOooooOO
XOooOooo
XOoooOOO
BF
DMASR
DMA Status Register
00000000
00000000
00000000
C3
SSOCRO
Slave Select 0 Control Register 0
00000000
00******
00******
C7
SSOCR1
Slave Select 0 Control Register 1
00000000
********
********
CB
SSlCRO
Slave Select 1 Control Register 0
00000000
00******
00******
CF
SSlCR1
Slave Select 1 Control Register 1
00000000
********
***"'****
D3
RCR
Release Control Register
00000000
00000000
00000000
D7
BTCR
Block 'fransfer Control Register
00000000
00000000
00000000
D8
CTLRO
Block 'fransfer Length Register 0
00000000
00000000
00000000
DF
BTLR1
Block 'fransfer Length Register 1
00000000
00000000
00000000
E3
SRR
Ssytem Reset Register
11111111
11111111
11111111
Reserved Locations
11111111
11111111
11111111
EB-FF
11-11
II
PRELIMINARY
VIC068A
Theory of Operation
Indivisible Cycles
The VIC068A is an interface between a local CPU bus and the
VMEbus. The local bus interface of the VIC068Aemuiates Motorola's family of32-bit CISC processor interfaces. Other processors
can easily be adapted to interface to the VIC068A using the appropriate logic.
Resetting the VIC068A
Read-modify-write cycles and indivisible multiple-address cycles
(IMACs) are easily performed using the VIC068A. Significant
controlis allowed to:
The VIC068Acan be reset by any of three distinct reset conditions:
Internal Reset. This reset is the most common means of reseting
the V1C068A.ltresets select register values and a11logicwithin the
device.
System Reset. This reset provides a means of resetting the
VIC068A through the VMEbus backplane. The V1C068A may
also signal a SYSRESET by writing a configuration register.
Global Reset. This provides a complete reset ofthe VIC068A. This
reset resets all of the V1C068Xs configuration registers. This reset
should be used with caution since SYSCLK is not driven while a
global reset is in progress.
All three reset options are implemented in a different manner and
have different effects on the VIC068A configuration registers.
VIC068A VMEbus System Controller
The VIC068A is capable of operating as the VMEbus system controller.1t provides VMEbus arbitration functions, including:
• Priority,round-robin,andsingle-Ievelarbitrationschemes
• DrivingIACKDaisy-Chain
• Driving BGiOUT Daisy-Chain (All fourJevels)
• DrivingSYSCLKoutput
• VMEbus arbitration timeout timer
The System controller functions are enabled by the SCON pin of
the VIC068A. When strapped LOW, the VIC068Afunctions as the
VMEbussystem controller.
VIC068A VMEbns Master Cycles
The VIC068A is capable of becoming the VMEbus master in response to a request from local resources. In this situation, the local
resource requests that a VMEbus transfer is desired. The
V1C068Amakes a request for the VMEbus. When the VMEbus is
granted to the VIC068A, it then performs the transfer and acknowledges the local resource and the cycle is complete. The
VIC068Aiscapableofallfour VMEbusrequestlevels. The followingrelease modes are supported:
• Release on request (ROR)
• Release when done (RWD)
• Release on clear (ROC)
• Release under RMC control
• Bus capture and hold (BCAP)
The VIC068A supports A32,A24, and A16, aswellasuser-defined
address spaces.
Master Write-Posting
The VIC068Ais capable of performing master write-posting (bus
decoupling).1n this situation, the VIC068A acknowledges the local resource immediately after the request to the VIC068A is
made, thus freeing the local bus. The VIC068A latches the local
data to be written and performs the VMEbus transfer without the
local resource having to wait for VMEbus arbitration.
• Requestin~e VMEbus on the assertion ofRMC independent of M
(this prevents any slave access from interrupting
local indivisable cyc1es)
• Stretching the VMEbusAS
• Making the above behaviors dependent on the local SIZi signals
Deadlock Condition
If a master operation is attempted when a slave operation to the
same module is in progress, a deadlock condition has occurred.
The VIC068A will signal a deadlock condition by asserting the
DEDLKsignal. This should be used by the local resource requesting the VMEbus to try the transfer after the slave access has completed.
Self-Access Condition
If the VIC068A, while it is VMEbus master, has a slave select signaled,a self access is said to have occurred. The VIC068A will issue
a BERR, which in tum will cause a LBERR to be asserted.
VIC068A VMEbus Slave Cycles
The VIC068A is capable of operating as a VMEbus slave controller. The VIC068Acontainsahighlyprogrammableenvironmentto
allow for a wide variety of slave configurations. The VIC068A aIlows for:
• D32 or D16 configuration
• A32, A24, A16, or user-defined address spaces
• Programmable block transfer support including:
- DMA-type block transfer (PAS and DSACKi held asserted)
- non - DMA-type block transfer (toggle PAS and DSACKi)
- No support for block transfer
• Programmable data acquisition delays
• Programmable PAS and DS timing
• Restricted slave accesses (supervisory accesses only)
When a slave access is required, the V1C068AwiIlrequest the local
bus. Whenlocalbusmastershipisobtained, the V1C068AwiIlread
or write the data to/from the local resource and assert the DTACK
signal to complete the transfer.
Slave Write-Posting
The VIC068A is capable of performing a slave write-post operation (bus decoupling). When enabled, the VIC068A latches the
datato bewritten and acknowledge the VMEbus (assertsDTACK)
immediatelythereafter. This prevents the VMEbus from having to
wait for local bus access.
Address Modifier (AM) Codes
The V1C068Aencodesanddecodesthe VMEbusaddressmodifier
codes. For VMEbus master accesses, the V1C068A encodes the
appropriateAM codes through the VIC068A FCi and ASIZi signals, as well as the block transfer status. For slave accesses, the
VIC068A decodes the AM codes and checks the slave select control registers to see if the slave request is to be supported with regard to address spaces, supervisory accesses, and block transfers.
The VIC068A also supports user-defined AM codes; that is, the
11-12
~
;~PRESS
PRELIMINARY
.
_ , SEMICONDUCTOR
VIC068A can be made to assert and respond to user-defined AM
codes.
VIC068A VMEbus Block Transfers
The VIC068A is capable ofbotb master and slave blocktransfers.
The master VIC068A performs a block transfer in one of two
modes:
• MOVEM-type Block 'Itansfer
• Master Block Transferwitb Local DMA
In addition to these VMEbus block transfers, tbe VIC068A is also
capable of performing block transfers from one local resource to
another in a DMA-like fashion. This is referred to as a ModulebasedDMA transfer.
The VMEbus specification restricts block transfers from crossing
256-byte boundaries witbout toggling tbe address strobe, in addition to restricting tbe maximum length of the transfer to 256 bytes.
The VIC068A allows for easy implementation of block transfers
tbat exceed the 256-byte restriction by releasing tbe VMEbus at
tbe appropriate time andrearbitratingforthe bus at a programmed
time later (tbis in-between time is referred to as tbe interleave period), while at tbe same time holding botb the local and VMEbus addresseswitb internal latches. All of this is performed without processor/software intervention until the transfer is complete.
The VIC068A contains two seperate address counters for the
VMEbus and tbe local address buses. In addition, a seperate address is counter-provided for slave block transfers. The VIC068A
addresscounters are 8-bit up-counters tbat provide for transfers up
to 256 bytes. For transfers tbat exceed the 256-byte limit, tbe Cypress VAC068A or external counters and latches are required.
The VlC068A allows slave accesses to occur during tbe interleave
period. Master accesses are also allowed during interleave with
programming and external logic. This is referred to as the "dual
patb" option.
The VAC068A may be used in conjunction witb tbe VIC068A to
provide much of tbe external logic required for extended block
transfer modes, such as tbe 256-byte boundary crossing and dual
patb. tbe VAC068A extends the 8-bit counters in tbe VIC068A to
support full 32-bit incrementing addresses on botb tbe local bus
and VMEbus. The VAC068Aaisocontainstbeiatchesrequiredfor
extended address block transfers as well as tbose required for supporting tbe dual patb feature. The VAC068A is not required to
support block transfers, it simply enhances tbem.
VIC068A
In tbis mode, the VIC068A captures the VMEbus address, and
latches them into internal counters. For subsequent cycles, the
VIC068Asimply increments this counter for each transfer. The local protocol for slave block transfe~n be configured in a full
handshake mode by toggling both PAS and DS and expect!!!g
DSACKi to ~Ie, or in an accelerated mode in which only DS
toggles and PAS is asserted tbroughout tbe cycle.
Module-based DMA Transfers
The VIC068A is capable of acting as a DMA controller between
two local resources. This mode is similar to that of master block
transfers with local DMA, witb the exception tbat tbe VMEbus is
not tbe second source or destination.
VIC068A Interrupt Generation and Handling Facilities
The VIC068A is capable of generating and handling a seven-level
prioritized interrupt scheme similar to tbat used by the Motorola
CISC processors. These interrupts include the seven VMEbus interrupts, seven local interrupts, five VIC068A error/status interrupts, and eight interprocessor communication interrupts.
The VIC068A can be configured to act as handler for any of the
seven VMEbus interrupts. The VIC068A can generate the seven
VMEbus interrupts as well as supplying a user-defined status/ID
vector. The local priority level (IPL) for VMEbus interrupts is programmable.Whenconfigured as tbe system controller, theVIC068
will drive tbe IACKdaisy-chain.
The local interrupts can be configured witb the following:
• User-defined local interrupt priority level (IPL)
• Option for VlC068A to provide the status/ID vector
• Edge or level sensitivity
• Polarity (rising/falling edge, active HIGH/LOW)
The VI C068A is also capable of generating local interrupts on certain error or status conditions. These include:
• ACFAILasserted
• SYSFAILasserted
• Failed master write-post (BERR asserted)
• Local DMAcompletion for block transfers
• Arbitrationtimeout
• VMEbus interrupter interrupt
The VIC068Acan also interrupt on the setting ofa module orglobal switch in the interprocessor communication facilities.
MOVEM Master Block Transfer
Interprocessor Communication Facilities
This mode ofblocktransferprovidestbe simplest implementation
ofVMEbus block transfers. For this mode, the local resource simply configures the VIC068Afora MOVEM block transfer and proceeds with the consecutive-address cycles (such as a 680XO
MOVEM instruction). The local resource continues as tbe local
bus master in this mode.
Master Block Transfers with Local DMA
The VIC068A includes interprocessor registers and switches that
can be written and read through VMEbus accesses. These are the
only such registers tbat are directly accessible from tbe VMEbus.
Includedin the interprocessor communication facilities are:
Intbismode, tbe VIC068Abecomes thelocalbusmasterandreads
or writes tbe local data in a DMA-like fashion. This provides a
much faster interface tban the MOVEM block transfer, but witb
less control and fault tolerence.
VIC068A Slave Block 1ransfer
The process of receiving a block transfer is referred to as a slave
block transfer. The VIC068A is capable of decoding the address
modifier codes to determine tbat a slave block transfer is desired.
• Four general purpose 8-bit registers
• Fourmoduleswitches
• Four global switches
• VIC068Aversion/revisionregister(read-only)
• VIC068A Reset/Haltcondition (read-only)
• VIC068Ainterprocessorcommunicationregistersemaphores
When set through a VMEbus access, these switches can interrupt a
local resource. The VI C068Aincludes module switches that are intended for a single module, and global switches which are intended
to be used as a broadcast.
11-13
III
='~~UcroR
~
PRELIMINARY
VIC068A
BulTer Control Signal for Shared Memory Implementation!l]
..:.
LAB -l.A31
ABEN
L...--""""~f-- LADO
=
D16
D32CPU
SHARED
MEMORY
D32SHARED
MEMORY
LEDI
LOO
~
LD15
VMEbus
08- 015
LDO - L07
VMEbus 000 - D07
VIC
LAO- LA7
S1Z1
S1ZD
WORD
Note:
t. This configuration can suppor! Slave Block 'fransfers and Master and
Slave Write-Post Operation_ This buffer configuration cannotsuppor!
block transfers with DMA_
11-14
VMEbus A01 A07
M
080081-
.-~
_
·a CYPRESS
PRELIMINARY
VIC068A
.F SEMICONDUClDR
Operating Range
Ambient
Thmperature
Range
O°Cto +70°C
Vee
5V±5%
Industrial
-40°C to +85°C
5V± 10%
Military
-55°Cto +125°C
5V± 10%
Commercial
Electrical Characteristics (For guideline, not tested)
Parameters
lee
Thst Conditions
Description
Vcc Operating
Supply Current
CLK64M = 64 MHz
Commercial
TA = -O°C, Vee = 5.25V
Industrial
TA = -40°C, Vee = 5.5V
Military
TA = -55°C, Vee = 5.5V
Min.
Max.
Units
150
rnA
150
150
For More Information
See the following documents:
VIC64 Datasheet
VAC068ADatasheet
CY7C964 Datasheet
VIC068A User's Guide
J04C068A User's Guide
Ordering Information
Ordering Code
VIC068A-BC
VIC068A-GC
VIC068A-NC
VIC068A-UC
VIC068A-GI
VIC068A-UI
VIC068A-GM
VIC068A-UM
Package
1Ype
B144
G145
N160
Ul62
G145
Ul62
G145
Ul62
Operating
Range
Commercial
Industrial
Military
U)
:::>
ID
Document #: 38-00167-A
11-15
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Features
• Optional companion part to VIC068A
• Implements master/slave VMEbus interface in coJQunc:tion witb tbe
VIC068A
• Complete VMEbus and I/O DMA capability for a 3Uit CPU
• Complete loc:aI and VMEbus memory
map decoding
- Separate seaments on local side
available for DRAM, VME subsystem bus (VSB), shared resources,
VMEbus, local JlO, and EPROM
-Separate segments for tbe VMEbus
address decode for slave select 0,
slave select 1, and Interproc:essor
communication facilities
- 64-Kbyte resolution for both local
and VMEbus memory maps
• Supports block transfers over 256
byte boundaries
- Address counters for botb VMEbus
A(31-8) and local IA(31-8)
- Supports dual-path mode
-Supports Implementation ofVSB
Interface with DMA capability
VAC068A
VMEbus Address Controller
• Dual UART channels on board
- Double-buffered on transmit,
quint-bull'ered on receive
- Baud rate programmable
• Miscellaneous features
- Pin grid array or quad Datpack
package
- Supports unaligned transfers
- Programmable DSACKI for local
I/O
- Programmable timer and Interrupt
controller
- Programmable I/O (PIO)
Functional Description
The VMEbus address controlJer
(VAC068A) is a programmable memory
map address controlJer. In conjunction
with the VIC068A (VMEbus intermce
conttoRer), the VAC068A maximizes the
VMEbus interface perfurmaru:e of a master/sIave module.
The VAC068A contains programmable
registers to aIJow the user to easily define
memory maps for both the local and
VMEbus address regions. The VAC068A
also contains the address counters and
handshaking signals to allow easy implementation of block-level transfers over
256-byte boundaries. Additional features
include dual internal UART channels, redirection control on the local bus to VSB
(VME subsystem bus) or shared resource
area, data swapping for unaligned transfers, programmable DSACKi, programmable timer and interrupt controlJer.
The VAC068A connects directly to the local bus and the VIC068A. VMEbus address lines A8 through A31 are driven directly, and VMEbus data lines 08
through DlS are driven by an external
buffer. The VAC068A output drivers feature patented high-drive outputs and
TTL-compatible inputs. The VAC068A
was designed using high-performance
standard celJs on an advanced CMOS
process.
The VAOJ68A is available in pin grid
array (with 122 active signals, 22 power
and ground pins, and 1 locator pin) and
quad fJatpack.
Sample Board Design
VACtJ68.1
11-16
PRELIMINARY VAC068A
Block Diagram
~EZJZII!ZIIZir:zEZZ:ZZll!Zl~;;;q;;;;~~~:c>
Local Address (31 :6)
VMEbus ADDRESS
Local Data (31 :6)
~
J;1WlJ
~
vm
EPROMCS
~
~
VSB"SE[
m:sE[lj
'SI:S'EIT
am
"RESET
"PAS
R/W
FC2
WORD
"FCIACR
mJCS
"R"EFGT
ASIZ170
DSACK1/0
IDt1ACK
lOSEI17O
VAC066A
REGISTER
MAP
GENERAL
PURPOSEI/O
OR
1O"RDIVm
~
7
~
SIO
1XDA
RXDA
1XDB
RXDB
2
INTERRUPT
OUT
3
LOCAL 1/0
MAP DECODE
•
CI)
:::t
lObus (15:6)
VAC068-2
11-17
m
PRELIMINARY VAC068A
Pin Configurations
Pin Grid Array (PGA)
Bottom
v_
A
B
c
o
E
F
Am
IllSElI
PI013/
ODlll
PlOll
LAD!
m:r
REFGT"
1CFSE[
I>2fJ
A22
lIWDER
m
mR
PI04I
1011'!1
VSI!SE(
SlSElD
A17
A19
A21
!ADO
rDIil\"CK
vss
Il!R
wo
A16
A18
we
lOCATOR
PIN
Al.
A15
vss
VDD
A12
A13
vss
A1D
All
G
H
M
N
p
101.
lISIZG
K
L
m:srn
108
1011
1013
1010
108
1012
WORD
1'llIlICK
FCO
vss
1015
M1Zf
CPUClK
LAEN
J
R
Fel
PAS
2
~
3
L019
4
USlICI«I
L021
5
VSS
lO16
L017
6
WO
lO23
lO18
WOO
vss
FC2
TflW
7
AOB
A09
vss
LD2'
L022
LD25
8
A25
A24
WO
VSS
L027
LD26
9
A27
A26
vss
WO
lD29
LD2B
10
A2B
A2B
DIW.lllS"
LOO1
LOOD
11
ASl
PIOll
PKl6I
RXDA
RlWR
VSS
1"EI'It!lQC'l
"!.lWIJ
12
A30
PI03/
RXDB
PID7
TOSm
PI08I
VSS
LA2B
vss
WO
WO
vss
LA13
lAB
LAll
I~
FI"IlmI
13
PlO6I
PI01D
"IlS
LASl
lA26
LA24
lA22
1lllIm
LA17
LA15
LAl'
LA12
lAB
~
14
lA30
SRIICS
lA26
lA27
lA25
lA23
LA21
LA19
lA20
LA18
LA16
LA1D
1!lSErn
15
P1D2/
TXOB
VDD
1CSEt'3
Pl09/
1OSE13
PIOOI
TXDA
PlOl21
VAC068-3
11-18
L~PRFSS
~...
PRELIMINARY VAC068A
SEMlCCNDUCTOR
Pin Configurations (continued)
VSS
VSS
vss
vss
i:Ai5O
Sii'iiiEN
VOO
PI06-iOSEl3
voo
PIO 13-IOSEL2
AS
PIOII-iiiSEL4
PIOII-IOSEL5
ODIR
f'Kll0
vss
.QIEIiI
PlOll
Cl!
VSS
Plo..iOiiii
LA(3O)
LAD!
LA(31)
VSBSEL
LA(2&)
LA(29)
PI01~S
IBR
LA(26)
REFUlT
LA(24)
LA(27)
LA(25)
SLSEW
iCffil
vss
VOD
vss
VOD
SlSELl
10(8)
LA(23)
LA(22)
10(10)
10(9)
LA(21)
LA(l9)
VSS
10(11)
VOO
IOSELl
10(12)
10(13)
LA(l7)
10(14)
vss
LA(2O)
WORD
1A(18)
10(15)
LA(15)
1'CIACT<
LA(l8)
~
J\!lIZl
LA(13)
LA(14)
CPUCLK
LA(lO)
FCO
LA(l2)
FCl
LA(9)
vss
vss
vss
vss
VAC068-4
11-19
•
PRELIMINARY VAC068A
VIC068AlVAC068A on 68030 Board
5121256K X 36 DRAM
512/256K X 36 DRAM
4 JEOEC EPROMS
~--------------------------~Rrr
024-031
~--------------------------_4Rrr
016- D23
r---------------------------~~
...-------------------,l~
DOO·D07
AMD·AM5
lIS, DSo, ml1, tII'l\llK,
WRIT!O, IW!lIIR,lIERR
Bl1IIIiI, 1mIOlJT. BRI, BIISV
ll\CK, 1lIl:lR1IiI, 1lICR01JT
VAC068
08-015
DRAM
IJO
VACD6B-5
VMEbus EPROM
A(8-31)
11-20
PRELIMINARY VAC068A
Pin Descriptions
This signal is the VMEbus address strobe and is an input. It responds to both VIC068A- and VMEbus-generated address
strobes.
The address size signals are three-state outputs. They are used to
profile the address size of an access. They are active under programmable control from the appropriate region attribute register. These signals are typically driven to VIC068A along with
to determine address and data path size.
Addressing Mode
ASIZII
ASIZI
16-bit Addressing
1
32-bit Addressing
1
o
24-bit Addressing
o
o
VMEbus Signals
All -AS
The VMEbus address signals A(31:08) are both inputs and threestate outputs.
wom
o
ID15 - ID8
DSEI«, mERli
The isolated data bus signals 10[15:08) are both inputs and
three-state outputs. They are used to interface local data [15:8) to
VMEbus D[15:8) in conjunction with transparent latching bidirectional I/O buffers. They also are used to interface with local
8-bit I/O peripherals via the Device Location and 15SACKI Control registers.
CPU/Local Interface Signals
The data sizing acknowledge signals are three-state outputs. They
are eeratedV§BsEYof the VAC068A device select outputs except CS and
L accesses. ~ or ~ can be selectively disabled or enabled in the Decode Control register. It is
assumed that EPROM 15SACKI is set up on power-up via the
FORCE EPROM mode.
LD31-LD16
The function code signals are inputs. They are used by VAC068A
to determining the local access type and are typically driven by
the local processor and VIC068A as shown in the following table:
Processor:
The local data bus signals LD[31:16) are both inputs and threestate outputs. They are used to write or read the local data bus
and for writing and reading the on-chip control registers.
Note: The IDbus connects to LD[15:8) and VIC068A connects to
LD[7:0).
Fe, Fe!, FCO
EC2
Kl
EQ!
0
1
LA31- LAS
0
0
1
0
The local address bus signals LA[31:8) are both inputs and threestate outputs. They are used as inputs during a VMEbus master
cycle and to access on-chip control registers. As outputs, they are
used during local or slave accesses.
1
1
1
0
1
~
User Data Space
User Program Space
Supervisor Data Space
1
0
1
Supervisor Program Space
CPU Space
PAS
VIC068A:
This signal serves as the local-processor address strobe and is an
input. It indicates to VAC068A that a valid address is present on
the address bus. This signal is typically driven by either VIC068A
or the local processor.
EC2
Kl
0
0
0
~
Slave Block'll"ansfer
0
1
LocalDMA
Slave Access
DRAM Refresh
This input is the local read/write signal. When cleared, this signal
indicates that the current cycle is a read. If it is asserted, the current cycle is a write. This signal is typically driven by either
VIC068A or the local processor.
RESET
This wet is used to reset the VAC068A It is used alone or along
with
RD to reset VAC068A internal registers. There are two
reset types that may be implemented. They are discussed in the
reset section.
This signal is an input and three-state output. It is active under
programmable control from the appropriate region attribute register and controls the length of the data field. When asserted, the
data path is 16 bits. If cleared, a 32-bitJE~Gth is set. It is also
used as an input in conjunction with
to set VAC068A
registers. It is typically driven to VI C068A as an output.
1
MWB
The module-wants-bus signal is an output. It is active under programmable control of the appropriate region attribute register
and is used as an indication that a VMEbus access is occurring.
This signal is typically driven to VIC068A.
FCiACK
The local interrupt acknowledge signal is an output. It indicates
that the current cycle is an interrupt acknowledge cycle. This signal is typically driven to VIC068A It is active under local
VAC068A interrupt cycles, or when HIACKEN is enabled in the
PIO Direction register or IDSEI3 address space is accessed
when programmed in the PIO Function register.
DRAMCS
The DRAM chip select signal is an output and is active when the
local address maps into region 0 as defined by the DRAM Upper
11-21
•
en
:l
CD
&;~PRFSS
'"'=!l5i!F ,
PRELIMINARY VAC068A
SEMICOND1.JCTOR
Limit Address register. It is also active when redirection is programmed in the VAC068A Decode Control register.
EPROMCS
The EPROM chip select signal is an output. It is active under a
global reset, local access, and under redirection on the local bus
via the VAC068A Decode Control register. An access to the
EPROM address space is indicative of EPROMCS being asserted.
FPUCS
The floating-point-unit chip select signal is an output and is active
when a floating-point coprocessor access is occurring. This activity is decoded via the processor function codes or under programmable control in the PIO Function register to be asserted in the
IOSEIA address range.
VSBSEL
The VSB (YME Subsystem Bus) select signal is an output and is
used to identify accesses to a daughter board or VSB. It is active
under programmable control from the appropriate region attribute register.
REFGT
The refresh grant signal is an output and is active on a refresh
cycle. This activity is typically decoded via the VIC068A function
codes.
LBR
The VIC068A local bus request signal is an input and is used to
signal the VAC068A when the VIC068A is ~iring the local
bus. It is typically connected to the VIC068A I:BR: signal.
CS
The slave select 0 signal is an output. It is active under programmable control by a comparison of its base address register and
the address on the VMEbus. It indicates to the VIC068A that a
slave operation is pending.
SLSELl
The slave select 1 signal is an output. It is active under programmable control by a comparison of its base address register and
the address on the YMEbus. It indicates to VIC068A that a slave
operation is pending.
ICFSEL
The interprocessor communications signal is an output and is active under programmable control of a comparison of its base address register and the address on the VMEbus. It is indicative of
a VIC068A interprocessor communication access.
IOSELl, IOSELO
The I/O select signals are outputs only. They are active when the
local bus address matches their fixed memory location. They are
also used in conjunction with the IDBus when so programmed in
the PIO Function register.
Parallel I/O-Shared Function Signals
The function of these signals are programmed in the PIO function register. When the corresponding bit is set in this register,
the signal is the shared function. When the corresponding bit is
cleared, the signals are in the general-purpose I/O mode.
PlOO-TXDA
The PlOO-TXDA signal is an input or three-state output. This
signal can be programmed to serve either as General-Purpose I/
pin, bit 0 or as an output for the UART Channel-A 'fransmit
signal.
o
The VIC068A select signal is an output and is active when the
fixed address of the VIC068A ($FFFC 0000 to $FFFC FFFF) is
presented on the local address bus. This ~a1 is typically connected to the VIC068A chip select signal (CS).
BLT
P101-RXDA
The PI01- RXDA signal is an input or a three-state output. This
signal can be programmed to serve as either General-Purpose I/
pin, bit 1 or as an input for the UART Channel-A Receiver signal.
o
The block transfer signal is an input and is used to determine
when a block transfer is in progress. It is also used to increment
local address counters internal to VAC068A. This signal is typically driven by VIC068A.
CACHINH
PI02-TXDB
The PI02-TXDB signal is an input or three-state output. This
signal can be programmed to serve as either General-Purpose I/
pin, bit 2 or as an output for the UART Channel-B 'fransmit
signal.
o
The cache inhibit signal is an open collector output. It is active
under programmable control of the appropriate region attribute
register. It is also asserted when an access is made to the mailbox
])ll~e VMEbus address bus. It is
typically connected to the
signal of a 74x543 when
VAC068A is not used.
PI012-8HRCS
The PI012-S1IRC5 signal is an input or a three-state output.
This signal can be programmed to serve as either General-Pur-
11-23
III
PRELIMINARY VAC068A
VAC068 Address Map
Address 0000 (lIl/lQ"-~
Region 0
_-LocalDRAM_----
------
------
--------
Programmable Boundary 1
Region 1
Ma~us
VSBbus
_---Shared Reso~-
In any 1 of the 3
programmable regions
---------
I-" ::~------------------------~~
------
Note: A24 Overlay must not cross
programmable boundaries
Programmable Boundary 2
Region 2
Map to:
VMEbus
VSBbus
Shared Resource
Programmable Boundary 3
Region 3
Map to:
VMEbus
VSBbus
Shared Resource
Address FFOO 0000
Region 4
EPROM
Address FFFO 0000
RegionS
Local I/O:
A 24 Address Overlay
[32 Mb VMEbus A24]
FFFO XXXX msErn
FFF2 XXXX IDSEIT
FFFI XXXX msm::!
FFF6 XXXX IOSEL3
FFFS XXXX IDSEIA
FFFA XXXX IDSEi3
FFFC XXXX <::g
FFFDXXXX~
Address FFFE 0000
Region 6
VMEbusA16
Address FFFF FFFF
11-24
PRELIMINARY VAC068A
VAC068 Register Map
FFFDOOXX
FFFDOIXX
FFFD02XX
FFFD03XX
'SI:SEIJ" Address Mask Register
'SI:SEIJ" Base Address Register
sr:sm::n Address Mask Register
sr:sm::n Base Address Register
FFFD04XX
rmm:: Address Register
FFFD05XX
DRAM Upper limit Register
FFFD06XX
Boundary 2 Address Register
FFFD07XX
Boundary 3 Address Register
FFFD08XX
0008XX
A24ADDSpaceBaseAddressRegister
FFFD09XX
Region 1 Attribute Register
FFFDOAXX
Region 2 Attribute Register
FFFDOBXX
Region 3 Attribute Register
FFFDOCXX
IOSElA DSACK Control Register
FFFDODXX
IOSElS DSACK Control Register
FFFDOEXX
SHRCS DSACK Control Register
FFFDOFXX
EPROM DSACK Control Register
FFFD 10XX
IOSELO DSACK Control Register
FFFD llXX
IOSELl DSACK Control Register
FFFD 12XX
IOSEL2 DSACK Control Register
FFFD 13XX
FFFD 14XX
IOSEL3 DSACK Control Register
Decode Control Register
FFFD 15XX
Interrupt Status Register
FFFD 16XX
Interrupt Control Register
FFFD 17XX
Device Location Register
FFFD 18XX
PIO Data Out Register
FFFD 19XX
PIO Pin Register
FFFDIAXX
PIO Direction Register
FFFDIBXX
PIO Function Register
FFFDICXX
Baud Rate Divisor Register
FFFDlDXX
Channel A Mode Register
FFFDIEXX
Channel A 1tansmit Data Register
FFFDIFXX
Channel B Mode Register
FFFD20XX
Channel A Receiver FIFO
FFFD21XX
Channel B Receiver FIFO
FFFD22XX
Channel B nansmit Data Register
FFFD23XX
Channel A Interrupt Mask Register
FFFD24XX
Channel B Interrupt Mask Register
FFFD25XX
Channel A Interrupt Status Register
FFFD26XX
Channel B Interrupt Status Register
FFFD27XX
Timer Data Register
FFFD28XX
Timer Control Register
FFFD29XX
VAC068A ID Register
•
11-25
PRELIMINARY VAC068A
Power Supply Current
Parameters
Icc
Description
Voo Operating
Supply Current
Test Conditions
CPUCLK-50 MHz
Operating Range
Ambient
Temperature
Range
Commercial
O°Cto +70°C
VDD
5V±5%
Industrial
-40°C to +85°C
5V ± 10%
Military
-55°C to +125°C
5V± 10%
For More Information
See the following documents:
VIC068A Datasheet
VIC64 Datasheet
CY7C964 Datasheet
VIC068A User's Guide
VAC068A User's Guide
Ordering Information
Package
1Ype
Operating
Range
VAC068A-BC
B144
Commercial
VAC068A-OC
VAC068A-NC
0145
VAC068A-UC
U162
0145
Ordering Code
VAC068A-OI
VAC068A-UI
N160
Industrial
U162
VAC068A-OM
G145
VAC068A-UM
U162
Military
Document #: 38-00169-A
11-26
Commercial
TA = O°C, Voo = 5.2SV
Industrial
TA = -40°C, VOO = 5.sV
Military
TA = -55°C, Voo = 5.sV
Min.
Max.
Units
150
mA
150
150
PRELIMINARY
CYPRESS
SEMICONDUCTOR
VMEbus Interface Controller
with D64 Functionality
Features
• An enhanced VIC068A
•
•
•
•
•
•
VIC64
- 64-bit MBLT operation
- Higher transfer rate
Complete VMEbus interface controller and arbiter
- 58 internal registers for configuration control and VMEbus and local operations status
- Drives arbitration, interrupt, address modifier, utility,
strobe, address line A[7:1], and data line D[7:0] directly.
and provides control signals to drive remaining address
and data lines
- Direct connection to 68K family and mappable to non-68K
processors
Complete master/slave capability
- Supports read, write, write posting, and block transfers
- Accommodates VMEbus timing requirements with internal digital delay line with half-clock granularity
- Programmable metastability delay
- Programmable data acquisition delays
- Provides programmable timeout timers for local bus and
VMEbus transactions
Interleaved block transfers
- D64 block transfer capability in conformance with IEEE
1014,Rev.D
- Can act as DMA master on local bus
- Programmable burst counter, transfer length, and interleave period
- Allows master and slave transfer to occur during interleave period
- Also supports local module-based DMA
Arbitration support
- Supports single-level, priority, and round-robin arbitration
- Support fair request option as requester
Interrupt support
- Complete support for the VMEbus interrupts; interrupters and interrupt handler
- Seven local interrupt lines
- 8-level interrupt priority encoded
-1btal of 29 interrupts mapped through the VIC64
Miscellaneous features
- Refresh option for local DRAM
- Four broadcast location monitors
- Four module-specific location monitors
- Eight interprocessor communication registers
Functional Description
Cypress'sVIC64 VMEbusInterfaceControllerwithD64 functionality is a single chip desigued to minimize the cost and board area
requirementsand to maximize theperformanceofa VMEbusmaster/slave module. Data transfers of 70 Mbyte/sec are possible between boards using VIC64.
In addition to D16 and D32 operations, the VIC64 performs D64
data transfer. The VIC64 is designed with an advanced CMOS processusinghigh-performancestandardcells.On-chipoutputbuffers
are used to provide direct connection to address and data lines.
The VIC64 is based on the industry-standard VIC068A. For most
applications, the VIC64 is fully software and plug compatible with
the VIC068A. (As VIC64 uses register bits that are unassigned in
VIC068A,usercodemayrequiresimplereworkto insurecompatibility.)
The local bus interface ofthe VIC64emulatesMotorola'sfamilyof
32-bit 68K processor interfaces. Other processors can easily be
adapted to interface to the VIC64 using appropriate logic.
Resetting the VIC64
The VIC64 can be reset by any of three distinct reset conditions:
• Internal Reset. This reset is the most common means of resetting the VIC64. It resets selected register values and logic
within the device.
• System Reset. This reset provides a means of resetting the
VIC64 through the VMEbus backplane. The VIC64 may also
initiate a system reset by writing a configuration register.
• Global Reset. This provides the most complete reset of the
VIC64. It resets all of the VIC64's configuration registers.
All three reset options are implemented in a different manner and
have different effect on the VIC64 configuration registers.
VIC64 VMEbus System Controller
The VIC64 is capable of operating as the VMEbus system controller. It provides VMEbus arbitration functions, including:
• Priority, round-robin, and single-level arbitration schemes
• DrivingIACKdaisy-chain
• Driving BGiOUT daisy-chain (all four levels)
• DrivingSYSCLKoutput
• VMEbusarbitration timeout timer
The system controller functions are enabled by the SCaN pin of
the VIC64. This pin is sampled during Reset and if LOW, VIC64
performsas system controller. After Reset the pin becomes an output signifying a D64 transfer.
VIC64 VMEbus Master Cycles
The VIC64 is capable of becoming the VMEbus master in response to a request from local resources. In this situation, the local
resource requests a VMEbus transfer. The VIC64 makes a request
for the VMEbus. When the VMEbus is granted to the VIC64, it
then performs the transfer and acknowledges the local resource
and the cycle is complete. The VIC64 is capable of all four VMEbus request levels. In addition, the following release modes are
supported:
•
•
•
•
•
11-27
Release On Request(ROR)
Release When Done (RWD)
Release On Clear (ROC)
Release Under RMC Control
Bus Capture And Hold (BCAP)
•
VIC64
PRELIMINARY
Pin Configurations
PIn Grid Array (pGA)
Bottom View
A
B
c
o
E
F
YSS
m
Illl:iRO
[1R02
lJRll5
MIZ1
;QIIZIJ
SIlIE[l
wmm
LIl6
m
11'[1
VDD
DR01
tJIll4
lJRll5
1CFSE[
IIViIIJ
A01
N1IJ
LD2
LIl6
DEDIR
1P!ll
lAEN
tJIll3
DRll'7
VSS
mE[o
YSS
AII6
LDl
LOG
LD1
LOCATOR
PIN
LA1
LDO
LA3
L
M
N
p
R
AD2
A04
YOO
VSS
1Rll4
NJ7
IRll3
Rl7
2
1RtT2
lR06
l\CFlQ[
3
1Rll5
YOO
110CRDUT
4
LD4
SVSFJOr:
~
DTAllK
5
LA6
LAS
w:m
liICR
AMO
LA2
LA4
VSS
YSS
lIS
AMl
LAl
LAO
YarT
VSS
AM2
AM3
8
llS
J:lSj\CKl
DB
YDD
lWOIID
AM4
9
PAS
rBERR
RESET
!!ERR
I'IRITE
AM5
10
lI!IXCRD
R!R
FCl
BIll!
DBl
m:o
11
Hm
'AIm
[BI!
1IBSV
!!Ill
1!IID
12
FC2
SlZIl
~
CI.KS4M
LAD!
VSS8
VDD
VSS8
VCC5
DDO
mmror
l!lmIiI
1RlIiIR
I!R3
YSS
13
Sill
1RESET
LADO
LEDI
lXIIR
IWDmIl
1mIIIJ
D06
DOO
DOl
YSS1
IIQliOIJT
lIll3lIiI
1!lRW
Bct:FI
14
nm
~
VDD
LEDO
ISOBE
D01
D06
D04
D02
YSS
15
IllWllEI'lIfl lIWDEII
G
H
J
11-28
K
Rm:R
lRl:Il
D!lUT Bm!OUI' SYSCLK
6
7
2
~
VIC64
PRELIMINARY
~=CYPRF.SS
~F SEMICONDUCIOR
Pin Configurations (continued)
Quad Flat &ck (QFP)
lbpView
~m~~~~~~~~~~~~~~~~~;~~~~~~~~~ro~~~~~~~~~~
ws
VSS
1
---------------------------------------~~
119
116
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
IPLO
iPLl
IPl2
VDD
LAEN
1iAi«i
L1RQl
CJRb7
iISI21
9
10
11
12
13
14
15
16
ASIZO
17
ICFSEL
FCiAcR
MWii
18
19
20
21
22
23
24
Al
25
WS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
iJRQ2
iJRcia
LIRa.
LIRQ5
L1RQ6
SL5El.l
vss
SLSELO
WORD
i>2.
A3
A4
VDD
A!;
AS
A7
VSS
lR!l1
iRa2
iRa3
iRa.
ws
vss
93
92
91
90
B9
88
B7
86
85
B4
83
B2
81
WS
WS
LBG
iFiESEi"
SCON/D64
Cl.K64M
AeEN
LADO
LADI
LEDI
VDD
LEDO
00iR
lii'iDENiiii
vss
LWDENiN
DENa
SWDEN
iSOBE
VDD
WS
007
006
DOS
D04
VDD
D03
D02
001
DOO
BGOuT3
WS
BGOUT2
BCiOliTl
BGOUTO
SYSCLK
BGiN3
BGiN2
vss
WS
V1C64-1
11-29
III
U)
:::»
In
PRELIMINARY
fiilPRffiSNOOC1OR
Functional Description
(continued)
The VIC64 supports A32, A24, and A16, as well as user-defined
addressspaces.
Master Write-Posting
The VIC64 is capable of performing master write-posting (bus decoupling). In this situation, the VIC64 acknowledges the local resource immediately after the request to the VIC64 is made, thus
freeingthe local bus. The VIC64latches the local data to be written
and performs the VMEbus transferwithoutthelocalresource having to wait for VMEbus arbitration.
Indivisible Cycles
Read-modify-writecycles and indivisible multiple-address cycles
(IMACs)are easilyperformed using the VIC64. Significant control
is allowed for:
• Requesting the VMEbus on the assertion ofRMC independent of MWB (this prevents any slave access from interrupting
local indivisible cycles)
• Stretching the VMEbus AS
• Making the above behaviors dependent on the local SIZi signals
Deadlock
If a master operation is attempted when a slave operation to the
same module is in progress, a deadlock condition occurs. The
VIC64 signals a deadlock condition by asserting the DEDLOCK
signaL This should be used by the local resource requesting the
VMEbus to try the transfer after the slave access has completed.
Self-Access
If the VIC64, while it is VMEbus master, has a slave select signaled, a self-access has occurred. The VIC64 asserts BERR and
LBERR
VIC64 VMEbus Slave Cycles
The VIC64 is capable of operating as a VMEbus slave controller.
The VIC64 contains a highly programmable environment to allow
for a wide variety of slave configurations. The VIC64 allows for:
• D64,D32,orDI6configuration
• A32, A24, A16, or user-defined address spaces
• Programmable block transfer support including:
- DMA-type block transfer (PAS and DSACKiheld asserted)
- Non DMA-type block transfer (toggle PAS& and DSACKi)
- No support for block transfer
• Programmable data acquisition delays
• ProgrammablePAS and DS timing
• Restricted slave accesses (supervisory accesses only)
When a slave access is required, the VIC64 requests the local bus.
When local bus mastership is obtained, the VIC64 reads or writes
the data to/from the local resource and asserts the DTACKsignal
to complete the transfer.
VIC64
propriateAM codes through the VIC64 FCi and ASIZisignals, as
well as the block transfer status. For slave accesses, the VIC64 decodes the AM codes and checks the slave select control registers to
see if the slave request is to be supported with regard to address
spaces, supervisory accesses, and block transfers. The VIC64 also
supportsuser-definedAMcodes; thatis, the VIC64can be made to
assert and respond to user-defined AM codes.
VIC64 VMEbus Block Transfers
The VIC64 is capable of both master and slave block transfers. The
master VIC64 performs a block transfer in one of two modes:
• The Master Block llansferwith Local DMA (DI6, D32, and
D64)
• The MOVEM-type Block llansfer (016 and D32)
In addition to these VMEbus block transfers, the VIC64 is also capable of performing block transfers from one local resource to
another in a DMA-like fashion. This is referred to as a module-basedDMA transfer.
For D32 block transfers, the VMEbus specification restricts block
transfers from crossing 256-byte boundaries without toggling the
addressstrobe, in addition to restricting the maximum length ofthe
transfer to 256 bytes. The VIC64 allows for easy implementation of
block transfers that exceed the 256-byte restriction byreleasingthe
VMEbus at the appropriate time and re-arbitrating for the bus at
a programmed time later (this in-between time is referred to as the
interleave period), while at the same time holding both the local
and VMEbus addresses with internal latches. All of this is performed without processor/software intervention until the transfer
is complete. For D64block transfers, the VMEbus specification allows for bursts of up to 2048 bytes.
The VIC64 contains two separate address counters for the VMEbus and local address buses. In addition, aseparate address counter
is provided for slave block transfers. The VIC64 address counters
are 8-bit up-counters that provide for transfers up to 256 bytes. For
transfers that exceed the 256 byte limit, the external counters and
latches are required.
The VIC64 is capable ofperformingA32/D64 or A24/D64 master
blocktransfers. For D64 transfers, external logic is required for the
multiplexing of the data and address signals for the upper 24 address/datalines. Multiplexing for the lower 8 bits is done within the
VIC64.
The VIC64 allows slave accesses to occur during the interleave period. Master accesses are also allowed during interleave with programmingand external logic. This is referred to as the dual-path
option.
MOVEM Master Block 'Ihlnsfer
This mode of block transfer provides the simplest implementation
ofVMEbus block transfers. For this mode, the local resource simply configures the VIC64 for a MOVEM block transfer and proceedswith the consecutive-address cycles (such as a 68KMOVEM
instruction). Thelocalresource continues as the local bus master in
this mode.
Slave Write-Posting
Master Block 'Ihlnsfers with Local DMA
The VIC64 is capable of performing a slave write-post operation
(bus decoupling). When enabled, the VIC64 latches the data to be
written, and acknowledges the VMEbus (asserts DTACK) immediatelythereafter. This prevents the VMEbus from having to wait
for local bus access.
Address Modifier (AM) Codes
In this mode, the VIC64 becomes the local bus master and reads or
writes the local data in a DMA-like fashion. This provides a much
fasterinterface than the MOVEMblocktransfer, butwith less control and fault tolerance.
D64 block transfers are not supported by MOVEM protocol.
The VIC64 encodes and decodes the VMEbus address modifier
codes. For VMEbus master accesses, the VIC64 encodes the ap-
11-30
~
~=CYPRESS
PRELIMINARY
~_iF SEMICONDUcrOR
VIC64 Slave Block 1i'ansfer
The process of receiving a block transfer is referred to as a
A241D640r A321D64 slave block transfer. The VIC64 is capable of
decoding the address modifier codes to determine that a slave
block transfer is desired. In this mode, the VIC64 captures the
VMEbus address, and latches it into internal counters. For subsequent cycles, the VIC64 simply increments this counter for each
transfer. The local protocol for slave block transfers can be configured in a full handshake mode by toggling both PAS and DS and
expecting DSACKi t~gle, or in an accelerated mode in which
only DS toggles and PAS is asserted throughout the cycle.
For D64 slave block transfers, the SCON/D64 signal is asserted to
indicate a D64 transfer is in progress. External logic is required to
de-multiplex the data from the VMEbus address bus for the upper
24 address/data lines. The lower 8 bits are done within the VIC64.
Module-Based OMA 1i'ansfers
The VIC64 can act as a DMA controller between two local resources. This mode is similar to that of master block transfers with
local DMA, with the exception that the VMEbus is not the source
ordestination.
VIC64 Interrupt Generation and Handling Facilities
The VI C64 can generate and handle aseven-levelprioritizedinterrupt scheme similar to that used by the Motorola 68K processors.
These interrupts include:
• 7 VMEbus interrupts
• 7 local interrupts
• 5 VIC64 error/status interrupts
• 8interprocessorcommunicationinterrupts.
The VIC64 can be configured to act as handler for any of the seven
VMEbus interrupts. The VIC64 can generate the seven VMEbus
interrupts as well as supplying a user-defined status/ID vector. The
local priority level (IPL) for VMEbus interrupts isprogrammable.
When configured as the system controller, the VIC64 drives the
lACK daisy chain.
The local interrupts can be configured with the following:
• User-defined local interrupt priority level (IPL)
• Option for VIC64 to provide the status/lD vector
• Edge or level sensitivity
• Polarity (rising/falling edge, active HI GH/LOW)
The VIC64 is also capable of generating local interrupts on certain
error or status conditions. These include:
• ACFAILasserted
• SYSFAILasserted
• Failedmasterwrite-post (BERRasserted)
• Local DMAcompletion for block transfers
• Arbitrationtimeout
• VMEbusinterrupterinterrupt
The VIC64 can also interrupt on the setting of a module or global
switch in the interprocessor communication facilities.
Interprocessor Communication Facilities
The VIC64 includes interprocessor registers and switches that can
be written and read through VMEbus accesses. These are the only
such registers that are directly accessible from the VMEbus. Includedin the interprocessor communication facilities are:
• Fourgeneral-purpose8-bitregisters
VIC64
• Four module switches
• Four global switches
• VIC64 version/revisionregister (read-only)
• VIC64reset/haitcondition(read-only)
• VIC64interprocessorcommunicationregistersemaphores
Whenset through a VMEbus access, these switches can interrupt a
local resource. The VIC64 includes module switches that are intendedfor a single module, and global switches which are intended
to be used as a broadcast.
Signal Descriptions
VMEbus Signals
The following signals are VMEbus specified signals that are driven
and received directly by the VIC64. For complete definitions and
description of these signals refer to the VMEbus specification
(IEEE 1014).
SYSRESET
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
TheVMEbussystemresetsignal.ALOWlevelonthissignalresets
the internal logic of the VIC64 and asserts the signals HALT and
RESEr These signals remain asserted for a minimum of200ms. If
the VIC64 is configured as VMEbussystemcontroller, aLOWlevel on IRESET asserts SYSRESET for a minimum of 200 ms.
ACFAIL
Input:
Output:
Drive:
Yes
No
None
The VMEbus AC fail signal. This signal should be driven by the
VMEbus power monitor (if installed). The VIC64 can be enabled
to provide a local interrupt on the assertion of this signal.
SYSFAIL
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
As an output the SYSFAILsignai is asserted when HALT has been
detected asserted for more than 4,ms (by a source other then the
VIC64).
This signal is asserted by the VIC64 after a global reset. It may be
maskedbyciearingICR6[6] or by setting ICR7[7]. The VIC64can
also be enabled to provide a localinterrupt on the assertion of this
signal.
SYSCLK
Input:
Output:
Drive:
No
Yes,3-state
64mA
The VMEbus system clock signal. This signal is driven by the
VIC64 when configured as system controller (SCON asserted).
Thefrequencydrivenis l/4th thefrequencydelivered to the VIC64
CLK64Msignai. Todelivertherequired 16 MHz on this signal, the
VIC64 must run at 64 MHz. The VIC64doesnotuse this signal internallyfor any purpose.
11-31
·
:;
~
CYJ>RES<)
PRELIMINARY
VIC64
. , SEMlCONDUcroR
BRJ-BRO
Input:
OUtput:
Drive:
DTACK
Yes
Yes, open collector
64mA
Input:
OUtput:
Drive:
Yes
Yes,rescinding
64mA
The VMEbus Bus Requestsignals.
The VMEbus Data-lIansfer-Acknowledgesignal.
BG3IN - BGOIN
BERR
Input:
Output:
Drive:
Yes
No
None
Input:
Output:
Drive:
Yes
Yes, rescinding
64mA
The VMEbus daisy-chained Bus-Grant-In signals.
The VMEbus Bus-Error signal.
BG30UT - BGOOUT
WRITE
Input:
Output:
Drive:
Input:
Output:
Drive:
No
Yes
SmA
Yes
Yes,3-state
64mA
The VMEbus daisy-chained Bus-Grant-Outsignals.
The VMEbusData-Direction signal.
BBSY
LWORD
Input:
Output:
Drive:
Yes
Yes, rescinding
64mA
Input:
Output:
Drive:
Yes
Yes,3-state
64mA
The VMEbus Bus-Busy signal.
This VMEbus Long-v.brd signal.
BCLR
AMS-AMO
Input:
Output:
Drive:
Yes
Yes,3-state
64mA
Input:
Output:
Drive:
Yes
Yes,3-state
64mA
The VMEbus Bus-Clear signal.
These VMEbus Address-ModifielSignals.
D7-DO
lACK
Input:
Output:
Drive:
Yes
Yes,3-state
64mA
Input:
Output:
Drive:
Yes
Yes, 3-state
64mA
The VMEbus low-order data lines.
The VMEbus Interrupt-Acknowledgesignal.
A7-A1
IACKIN
Input:
Output:
Drive
Yes
Yes, 3-state
64mA
Input:
Output:
Drive:
Yes
No
None
The VMEbus low-order address lines.
The VMEbus daisy-chained Interrupt-Acknowledge-Insignal.
AS
IACKOUT
Input:
OUtput
Drive:
Yes
Yes, rescinding
64mA
Input:
OUtput:
Drive:
No
Yes
SmA
The VMEbus Address Strobe signal.
The VMEbus daisy-chained Interrupt-Acknowledge-Outsignal.
DS1- DSO
IRQ7-IRQO
Input:
Output:
Drive:
Yes
Yes, rescinding
64mA
The VMEbus Data Strobe signals.
Input:
Output:
Drive:
Yes
Yes, open collector
64mA
The VMEbus Interrupt Requestsignals.
11-32
PRELIMINARY
Local Signals
Thesesignals defme the local bus structure of the VIC64. They are
modeled after Motorola 68K signals.
LD7-LDO
Input:
Output:
Drive:
Yes
Yes,3-state
8mA
The Local Data 7 - 0 signals. These signals are typicaIly connected
to the local processor data lines D(7:0) through an isolation buffer.
VIC64 register accesses are also made through these data signals.
LA7-LAO
Input:
Output:
Drive:
Yes
Yes,3-state
8mA
CS
Yes
No
None
The VIC64 chip select signal. This signal should be asserted whenever access to the VIC64 internal registers is required.
PAS
Input:
Output:
Drive:
Yes
Yes, rescinding
8mA
ThephysicaIJprocessor address strobe. This signal is used to qualify
anincomingaddresswhenperforming VMEbusmasteroperations
or register operations. This signal is driven when becoming the local bus master and performing slave transfers, DRAM refresh,
slave block transfers and block transfers with local DMA. When
acting as an output, the minimum assertion and negation timingfor
this signal is configured by the Local Bus Timing Register.
DS
Input:
Output:
Drive:
bus master to acknowledge the successful completion of each cycle
of a slave transfer, slave block transfer, or block transferswithlocal
DMA. The VIC64 asserts one or both of these signals to acknowledge the successful completion ofa VMEbus master operation (after receiving the VMEbus DTACK signal). The following should
be noted about the DSACKl/Osignals:
• The VIC64 only asserts a 16 bit DSACKi code when the
WORD signal is asserted indicating access to a D16 VMEbus
resource is complete.
• The VIC64 treats the assertion of any DSACKl/O signal as a
32-bit acknowledge for slave accesses.
• The VIC64 does not directly support 16 or 8-bit local port
sizes.
• The VIC64 always asserts both DSACKs for register accesses.
as well as for interrupt acknowledge cycles.
LBERR
The Local Address 7-0 signals. These signals are typically connectedto the local processor address lines. VIC64 registers are also
addressedthrough these signals. When acting as the local bus master, the VIC64 drives these lines with the LAEN signal to supply
the local address.
Input:
Output:
Drive:
VIC64
Yes
Yes, rescinding
8mA
The local data strobe. This signal is used to qualify incoming data
when performing VMEbus master operations or register operations. This signal is driven when becoming the local bus master and
performing slave transfers, DRAM refresh, slave block transfers,
andblocktransfers with local DMA. When acting as an output, the
minimum assertion and negation timing for this signal is directed
by the Local Bus Timing Register.
Input: Yes
Output: Yes,rescinding
Drive:8mA
The local bus-error signal. This signal should be asserted to the
VIC64wheneverthe VIC64 is local bus master to acknowledge the
unsuccessful completion of a cycle of a slave transfer, slave block
transfer, and block transfers with local DMA in which case the
VIC64 asserts the VMEbus BERR signal. The VIC64 asserts this
signal to acknowledge the unsuccessful completion of a VMEbus
master operation (after receiving the VMEbus BERRsignal).
RESET
Input: No
Output: Yes,Open-collector
Drive:8mA
The local reset indication signal. This signal is asserted whenever
the VIC64 is in a reset condition. an internal, global, or system reset causes the VIC64 to assert RESET for a minimum of200 ms. If
the reset condition continues for longer then 200 ms, RESET begins additional 200 IDS timeouts until all reset conditions are
cleared.
HALT
Input:
Output:
Drive:
The "halted" condition indication signal. This signal, along with
RESE1; is asserted during reset conditions. An internal, global,
and system reset causes the VIC64 to assert HALTfor a minimum
of 200 ms. If the reset condition continues for longer then 200 IDS,
HALT begins an additional 200 ms timeouts until all reset conditionsare cleared. Assertion of HALT for greater than 4 ms by anything other then the VIC64 causes the VIC64 to assert SYSFAIL
HALT may be configured to assert during dead-lock conditions
along with LBERR to initiate a retry sequence for Motorola 68K
processors.
DSACKl, DSACKO
RiW
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
Yes, rescinding
8mA
The local data-size-acknowledge signals. One or both of these signals should be asserted to the VIC64 whenever the VIC64 is local
Yes
Yes, Open collector
8mA
Yes
Yes, rescinding
8mA
Thelocal data direction signal. This signal is driven while VIC64 is
alocalbusmastertoindicatelocaldatadirection.Asaninput,RIW
11-33
•
PRELIMINARY
indicates data direction for VMEbus master cycles. In this case,
WRITE reflects the value of R/W. An asserted condition indicates
a write operation.
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
Yes, rescinding
8mA
The local function code signals. These signals identify the type of
local cycle in progress. As inputs, they should reflect the type of operations in terms of User/Supervisory Code/Data. They may be
connected directly to the Motorola FCZ/l outputs for 68000-30
processors. For the 68040, the FC2/l inputs may be connected to
the TM2/l outputs respectively. Additional qualification may be
requiredfor 68040 applications since the 68040 uses previously reservedlunusedfunction codes.
FC2
FCl
Description
1
1
0
1
0
User Data
User Program
Supervisory Data
Supervisory Program
1
As outputs, the VIC64 drives these signals whenever local bus master to indicate the type of local cycle the VIC64 is performing.
FCZ
FCl
Description
o
o
1
1
• BlocktransferswithlocalDMA
• DRAM refresh
LBG
FC2,FCl
o
o
VIC64
0
1
0
Slave Block 1tansfer
LocalDMA
Slave Access
DRAM Refresh
1
Yes
No
None
The local bus grant signal. The signal should be asserted in response the assertion of the LBR signal. The VIC64 does not incorporate a local bus grant acknowledge protocol so, the LBG signal
should remain asserted for the duration of LBR.
MWB
Input:
Output:
Drive:
Yes
No
None
The "Module-Wants-Bus" signal. This signal should be asserted by
local resources to begin a VMEbus transaction. When qualified by
the PAS signal, the VIC64 asserts the VMEbusBRisignal. Thissignal is usually asserted by local-to-VMEbus address decoders.
FCIACK
Input:
Output:
Drive:
Yes
No
None
The local interrupt acknowledge signal. This signal should be asserted (qualified by PAS) to acknowledge all VIC64-generated 10cal interrupts.
SLSELJ,SLSELO
SIZ1,SIZO
Input:
Output:
Drive:
Input:
Output:
Drive:
Yes
Yes, rescinding
8mA
Yes
No
None
The local data size signals. As inputs, these signals should identify
the width of the VMEbus data to be transferred. The SIZi signals
should not be used to indicate the physical port size of the slave device (Dl6, or D3Z). This is done with the WORD signal. As outputs, they are driven by the VIC64 as local bus master to identify
the width of the incoming data.
SIZl
S!Z!!
Data Width
The slave select signals. These signals indicate the VIC64 has been
selected to perform a VMEbusslave operation. When qualified by
AS and valid AM codes, the VIC64 requests the local bus to perform the slave cycle. These signals are usually asserted by VMEbus-to-Iocaladdress decoders.
The SLSELl/O signals may be used independently of each other to
provide unique slave characteristics as defined by the Slave Select
Controlregisters.
o
o
ICFSEL
1
1
0
1
0
Long Word
1
3-B~e
B~e
Input:
Output:
Drive:
Word
LBR
Input:
Output:
Drive:
No
Yes
8mA
The local bus request signal. This signal is asserted whenever the
VIC64 desires mastership of the local bus. This signal remains asserted for the entire bus tenure.
Localbus mastership isrequestedwheneachofthefollowingoperations is desired:
• Standard slave accesses
• Slave block transactions
Yes
No
None
The Interprocessor Communication Facility (ICF) Select signal.
This signal is used to indicate that the ICF functions of the VIC64
have been selected. These include the ICF registers and the ICF
switch interrupts. This signal is qualified with AS and Al6 AM
codes (Al6/Supervisory for global switches).
ASIZl, ASIZO
Input:
Output:
Drive:
Yes
No
None
The VMEbus address size signals. These signals should be driven
to indicate the VMEbus address size of master VMEbus transfers.
The address size information is issued on the VMEbusAM codes.
11-34
·~PRESS
-=:F
PRELIMINARY
The assertion of ASIZO indicates an A16 transaction. The assertion of ASIZI indicates anA32 transaction. Asserting neither indicates an A24 transaction. User-defined address spaces may be accessed by asserting both ASIZl/O signals. In this case, the AM
codes are issued according to the programming of the Address
Modifier Source Register.
ASIZI
ASIZO
Address Size
o
o
1
o
1
o
1
1
Userdefined
A32
A16
A24
WORD
Yes
No
None
The VMEbus data-width control signal. This signal, when asserted,
indicates the requested VMEbus transaction should be treated as
aD16 data path. When negated, the VMEbusdata path is assumed
to be D32. This signal should be used to configure VMEbus
data-width for master cycles only. Data-width for slave cycles is
configured in the Slave Select Control Registers.
This signal is also used to configure the data-width for block transfers with local DMA. When this signal is asserted during the block
transfer initiation cycle, the block transfer is assumed to be a D16
block transfer.
Thissignal may be changed dynamically for individual transfers, or
strapped LOW at power-up for permanent D16 operation. If
WORD is strapped LOW at power-up, the VIC64 is configured as
a D16 slave independent of the slave configuration in the Slave Select Control Registers.
WORD should not be used to indicate data size (i.e., byte, word, or
long-word) only local data port size (i.e., D16 or D32).
Yes
Yes, open-collector
SmA
The Block transfer with local DMA indication signal. This signal is
used to indicate that a blocktransferwith local DMAis in progress.
This signal remains asserted for the entire block transfer including
interleaveperiods with the exception oflocal page boundary crossings. BLT toggles during local boundary crossings to increment the
externalLA( +:S) counters.
If the BLT signal is asserted simultaneously with the MWB signal
and BTCR[7] is set, a module-based DMA transfer is performed.
DEDLK
Input:
Output:
Drive:
Inputs:
Output:
Drive:
No
Yes
SmA
The dead-lock indication signal. This signal is used to indicate a
dead-Iockcondition has occurred. This signal should be used by 10-
IPLOonly
Yes,open-coJlector
SmA
The local priority encoded interrupt request signals. These signals
are asserted to interrupt the local processor. All local VIC64 interrupts are issued with these signals. These signals are meant to emulate the Motorola 6SK interrupt algorithms. The assertion of one
or more of these signals indicate a single interrupt with a priority
given by the negative-logic value of the IPLi signals. Level 7 is the
highest priority. These signals are open-collector to allow the
wire-ORingof multiple interrupt sources.
During the assertion of IRESET, IPLO becomes an input. IfIPLO
is asserted at this time, a global reset is performed.
LIRQ7 - LIRQl
Input:
Output:
Drive:
Yes
LIRQ20nly
SmA (LIRQ2 only)
The local interrupt request signals. These signals serve as local interruptrequest signals for the VIC64. If enabled to handle the particular local interrupt, the VIC64 in turn issues a processor interrupt with the IPLi signals at the assertion of a LIRQi. Extensive
configuration of local interrupts is allowed through the Local InterruptConfiguration Registers.
LIRQ2may also be configured to issue periodic "heartbeat" interrupts at user defined intervals.
LIACKO
Input:
Output:
Drive:
BLT
Input:
Output:
Drive:
cal logic to remove its request for the VMEbus. DEDLKremains
asserted until the slave transaction is complete.
DEDLKis also asserted to indicate that a VMEbus master cycle is
being attempted during the interleave period of a block transfer
with local DMA, without the dual path feature enabled. In this
case, DEDLK is asserted while MWB is asserted. If, during the interleave period, the MWB signal is asserted after the VMEbus has
beenre-obtained, the VIC64 will assert DEDLKfor the duration
of the burst.
IPL2, IPLl, IPLO
TheASIZl/0signals are also used for cycle acknowledge signals for
module-based DMA transfers. During a module-based DMA
transfer, the ASIZO signal is used as a data-transfer-acknowledge
signal (analogous to DTACK). The ASIZI signal is used as a buserror signal (analogous to BERR).
Input:
Output:
Drive:
VIC64
SEMICONDUCTOR
No
Yes
SmA
The "autovectoring" indication signal. This signal is asserted when
the VIC64 is configured to allow the interrupting device to place its
status/IDvector on the local data bus in response to a VIC64-handied local interrupt acknowledge. This signal may be used to signal
a autovectored interrupt acknowledge cycle for 6S020/30/40 processors. This signal may be connected directly to the AVEC signal
for these processors.
IRESET
Input:
Output:
Drive:
Yes
No
None
The internal reset signal. This signal is used to issue both internal
and global resets to the VI C64. If asserted with IPLO, a global reset
is performed. If asserted without IPLO, an internal reset is performed. All internal state machines and selected register bits are
reset during the assertion ofIRESET. HALT and RESET are both
asserted during the assertion of IRESET. If configured as system
11-35
III
PRELIMINARY
controller, SYSRESET is also asserted during the assertion of
IRESE'I
IRESETcontainsinternalhysteresis to allow the connection ofthis
signal to an external RC network for power-up resets.
SCONJD(i4
Input:
Output:
Drive:
Yes
Yes
16mA
CLK64M
Input
No
None
These signals control the latching and enabling of the external address and data latches and buffers. For block transfers with local
DMA, some of these signals are used to control the counting and
enablingof external counters required for page boundarycrossing.
No
Yes
SmA
The VMEbus Address Bus ENable signal. This signal is used to enable the external VMEbus address drivers for VMEbus master operations. It is typically connected to the OEAB input of a '543 addresstransceivers.
Input:
Output:
Drive:
No
Yes
SmA
The Local Address ENable signal. This signal is used to enable the
external local address drivers for slave accesses. It is typically connected to the OEBA input of a '543 address transceivers through
an inverter.
Note that this signal is an active-HIGH signal.
LADO
No
Yes
SmA
The Latch ADdress Out signal. This signal is used to latch the outgoing VMEbusaddressfor VMEbusmasteroperations. When this
signal is asserted (HIGH), it is assumed that the latches are in a
No
Yes
SmA
The Data ENable Out signal. This signal enables data onto the
VMEbus data bus for master write and slave read cycles. This signal is typically connected to the OEAB input of the '543 data
latches.
LWDENIN
No
Yes
SmA
The Lower Word Data ENable IN signal. This signal enables data
onto the lowerword ofthe local data bus LD(15:S) for master read
and slave write cycles. This signal is typically connected to the
OEBA input of the '543 lower data latch.
UWDENlN
Input:
Output:
Drive:
LAEN
Input:
Output:
Drive:
No
Yes
SmA
The LatchADdress In signal. This signal is used to latch theincoming VMEbus address for slave accesses. When this signal is asserted(HIGH), it is assumed that the latches are in a latched state.
When negated, the latches should be in a fall-through state. This
allows direct connection to the '543 address driver LEBA input.
LADIis used in conjunction with LADO to temporarily store outgoing VMEbus master transaction addresses during intervening
slave accesses.
Input:
Output:
Drive:
ADEN
Input:
Output:
Drive:
Input:
Output:
Drive:
DENO
The VIC64 master clock input. This 64-MHz clock input is used to
clock internal arbitration, timing, and delay functions within the
VIC64.
Butrer Control Signals
Input:
Output:
Drive:
latched state. Whennegated, the latches should be in afall-through
state. This allows direct connection to the '543 address driver
LEAB input. LADO is very important for proper operation of
master write posting and block transfers with interleave periods.
For these operations, VIC64 may use LADO in combination with
LADI and ABEN to temporarily store the contents of a VMEbus
address during intervening slave accesses.
LADI
Thispinis sampled by theVIC64'sinternallogicduring a Resetperiodto deterrnine whether the VIC64 is to become the system controller. If the pin is driven LOW during Reset, system controller
functions are performed; if the pin is driven HIGH the VIC64 is
not the system controller. After the Reset period ends the pin becomes an output that is driven LOW by VIC64 except during the
data phase of the 64-bit MBLToperations. (Use a resistive pull-up
or pull-down to select the SCON state.)
Input:
Output:
Drive:
VIC64
No
Yes
SmA
The Upper Word Data ENable IN signal. This signal enables data
onto the upper word of the local data bus LD(31:16) for master
read and slave write cycles. This signal is typically connected to the
OEBAinput ofthe upper '543 data latches.
LEDO
Input:
Output:
Drive:
No
Yes
SmA
The LatchEnableDataOutsignal. This signal latches the outgoing
VMEbusdataformasterwrite and slave read cycles. When thissignal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in afall-through
state. This allows direct connection to the '543 address driver
11-36
=.-~
PRELIMINARY
'il; CYPRESS
~.r
LEAB input.This signal is used in conjunction with LEDI to temporarily store outgoing master write post data (data switch-back).
LEDI
Input:
Output:
Drive:
No
Yes
8mA
The Latch Enable Data In signal. This signal latches the incoming
VMEbus data formasterreadand slavewritecycIes. When thissignal is asserted (HIGH), it is assumed that the latches are in a
latched state. When negated, the latches should be in a fall-through
state. This allows direct connection to the '543 address driver
LEBAinput.This signal is used in conjunction with LEDO to temporarily store outgoing master write post data.
SWDEN
Input:
Output:
Drive:
No
Yes
8mA
The SWap Data ENable signal. This signal, along with the ISOBE
signal, provides byte lane switching. It provides for swapping
LD(31:16) to LD(15:0). This signal is typically connected to the
EN input of the '245 swap buffer.
DDIR
Input:
Output:
Drive:
No
Yes
8mA
The Data D IRectionsignal. This signal provides the data direction
(i.e., read/write) information to the isolation and swap buffers.
Whenasserted, buffers should be configured in the local-to-VMEbus (A-to-B) direction. This signal is typically connected to the
DIRinputofthe '245. isolation/swap buffers.
ISOBE
Input:
Output:
Drive:
VIC64
SEMICONDUCTOR
No
Yes
8mA
The ISOlation Buffer Enable signal. This signal, along with the
SWDEN signal, provides byte lane switching. This signal is typically connected to the EN input of the '245 isolation buffer.
11-37
VIC64
PRELIMINARY
Operating Range
Ambient
temperature
Range
Commercial
Vee
OCCto +70 c C
5V±5%
Industrial
-40°C to +85°C
5V± 10%
Military
-55°Cto +125°C
5V± 10%
Power Supply Current
Parameters
Icc
Description
Vee Operating
Supply Current
test Conditions
CLK 64M - 64 MHz
For More Information
Seetbe following documents:
VIC068ADatasbeet
VAC068ADatasheet
CY7C964 Datasheet
VIC068A User's Guide
VAC068A User's Guide
Ordering Information
Package
Ordering Code
VIC64-BC
VIC64-GC
VIC64-NC
VIC64-UC
VIC64-GI
VIC64-UI
VIC64-GM
VIC64-UM
'J.Ype
BI44
G145
N160
U162
G145
U162
G145
U162
Operating
Range
Commercial
Industrial
Military
Document #: 38-00196
11-38
Commercial
TA = O°C, Vee = 5.25V
Industrial
TA = -40°C, Vee = 5.5V
Military
TA = -55°C, Vee = 5.5V
Min.
Max.
Units
150
rnA
150
150
ADVANCED INFORMATION
CYPRESS
SEMICONDUCTOR
Features
• Comparators, counters, latches, and
drivers minimize logic requirements
for a variety of multiplexed and nonmnltiplexed buses
• Directly drives VMEbus address and
data signals
• 8-/16-bit comparator for slave address
decoding
• Flexible interface optimized for VMEbus applications
• Companion device to Cypress VMEbus family of components
• Replaces multiple SSI/MSIcomponents
• Cascadeable
• 64-pin QFP package
CY7C964
Bus Interface Logic Circuit
CY7C964 is ideal in applications where
high-performance and real estate are primary concerns.
Although having many applications, the
Bus Interface Logic Circuit is an ideal companion part to Cypress's VMEbus family
of components, the VIC068A and the
VIC64. It is intended to drive the address
and data buses (only the three upper bytes,
as the VIC068A/VIC64 drives the lower
byte of data and address buses), so three of
these small devices are needed per controller. The VIC068A/VIC64 provides the
control and timing signals to control the
Bus Interface Logic Circuit as it acts as a
bridge between the VMEbus and the Local
bus.
Functional Description
Application with VMEbus
Architecture
The CY7C964 integrates several spaceconsuming functions into one small package, freeing board space for the implementation of added-value board features.
It contains counters, comparators, latches,
and drivers configured to be of value to implementorsof any backplane interface with
address and data buses, particularly VMEbus interfaces. The on-chip drivers are suitable for driving the VMEbus directly. The
The CY7C964 Bus Interface LogicCircuit
is a seamless interface between the
VIC068A/VIC64and the VMEbussignals.
The device functions equally well in the established 32-bit VMEbus arena and the
emerging64-bit VMEbus standard (IEEE
1014, Rev. D). The device contains three
8-bit counters to fulfill the functions of
Blockcounters, and DMA counters as im-
Use with Cypress VMEbus Controllers
plied by the D64 portion of the VMEbus
specification.lt also contains the necessary
multiplexing logic to allow the 64-bit-wide
VMEbus path to be funnelled to and from
the 32-bit local bus. Control circuitry is included to manage the switching of the
32-bit address bus during normal (32-bit)
operations, and during MBLT (64-bit) operations. All the controls for these operations are directly provided from the
VIC068A/VIC64. The on-chip drivers are
capable of driving the VMEbus directly
(48mA).
Use in Other VMEbns Controller
Implementations
The CY7C964 circuitry is designed to be of
use to designers of VMEbus circuitry, including VSB (VME subsystem bus) and
designs not requiring the features of the
Cypress VIC068A and VIC64. The logic
diagram includes general-purpose blocks
of comparators, counters, and latches that
can be controlled using the flexible control
interface to allow many different options
to be implemented. Although the device is
packaged in a small 64-pin package, the
use of multiplexed input and output pins
provides access to the many internal functions, thus saving external circuitry.
Pin Configuration
PQFP/CQFP
Top View
~ggS95g5~§g9~§5~
III
GNO
GNO
L07
LOO
LOS
LAO
FC1
OENIN
DENIN1
LAEN
STROBE
MWB
LCOUT
GNO
VCOMP
VCOUT
LAOO
LAOI
LEOI
LEOO
LCIN
VCIN
VCC
064
DENO
ABEN
DO
AD
GNO
A7
VSS
C964-1
11-39
a:;~PRFSS
~, ~b.ncaIDUCTOR
ADVANCED·INFORMATION
Application with Other Bus Architectures
The CY7C964 is optimized for applications requiring wide buffers
and high-performance multiplexing operations. The architecture
can be configured to provide functions such as 16-bit bidirectional
three-state latch and 16-bit comparator with mask register, or
CY7C964
more complex functions such as 16-to-8 pipelined bidirectional
multiplexerwith address counter/comparator circuitry. The device
can be cascaded to generate counters and comparators suitable for
multiple byte address/data buses. The on-chip 48 rnA drivers can
be directly connected to many standard backplane buses.
Maximum Ratings
(Above which the useful life may be impaired. Foruserguidelines,
nottested. )
StorageThmperature .................. - 65°C to +150°C
Ambient Thmperaturewith
PowerApplied ........................ - 55°Cto +125°C
Electrical Characteristics
Parameters
Supply Voltage to Ground Potential. . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ......................... - O.5Vto +7.0V
OutputPinSinkCurrent .......................... 120rnA
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 m W
Over the Operating Range
Description
VOH
Output mGH Voltage (YME)
VOL
Output WW Voltage (YME)
VOH
Output mGH Voltage
VOL
Output WW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Min.
Max.
2.6
V
0.6
2.4
2.0
11-40
V
V
0.8
See the Ji7C068A/VAC068A User's Guide for more information on
this part and on related products.
Document #: 38-00197
V
V
0.5
For More Information
Units
V
INFO
'I
SRAMs
PROMs
PlDs
FIFOs
lOGIC
COMM
RISC
MODULES
•
ECl
BUS
MILITARY
TOOLS
QUALITY
PACKAGES
'"
dl-~
~,'iJICYPRESS
. , SEMlCONDUCTOR
Military Information
Section Contents
Page Number
Military Overview ........................................................................................
Military Product Selector Guide.............................................................................
Military Ordering Information .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-2
12-7
•
CYPRESS
SEMICONDUCTOR
Military Overview
Features
Success in any endeavor requires a high level of dedication to the
task. Cypress Semiconductor has demonstrated its dedication
through its corporate commitment to support the military marketplace. This commitment starts with product design. All products
are designed using our state-of-the-art CMOS, BiCMOS, and bipolar processes, and they must meet the full - 55 to + 125 degrees
Celsius operational criteria for military use. The commitment continues with the 1986 DESCcertification of our automated U.S. facility in San Jose, California. The commitment shows in our dedication to meet and exceed the stringent quality and reliability
requirements of MIL-STD-883D and MIL-M-3851OJ. It shows in
Cypress's participation in each of the military processing programs: MIL-STD-883D compliant, SMD (Standardized Military
Drawing), and JAN. Finally, our commitment shows in our leadership position in special packages for military use.
Product Design
Every Cypress product is designed to meet or exceed the full temperature and functional requirements of military product. This
means that Cypress builds military product as a matter of course,
rather than as an accidental benefit of favorable test yield. Designs
are being carried out in our industry-leading 0.65-micron CMOS,
BiCMOS, and Bipolar processes. Cypress is able to offer a family
of products that are industry leaders in density, low operating and
standby current, and high speed. In addition, our technology results in products with very small manufacturable die sizes that will
fit into the LCCs and flatpacks so often used in military programs.
DESC-Certitied Facility
On May 8, 1986, the Cypress facility at 3901 North First Street in
San Jose, California was certified by DESC for the production of
JAN Class B CMOS Microcircuits. This certification not only allows Cypress to qualify product for JAN use, but also assures our
customers that our San Jose Facility has the necessary documentation and procedures to manufacture product to the most stringent
of quality and reliability requirements. Our wafer fabrication facilities are Class 10 (San Jose) and Class 1 (Round Rock, TX and
Bloomington, MN) manufacturing enviromnents and our assembly facility is also a clean room. In addition, our highly automated
assembly facility is located entirely in the U .SA and is capable of
handling virtually any hermetic package configuration.
Data Sheet Documentation
Every Cypress final data sheet is a corporate document with a revision history. The document number and revision appears on each
final data sheet. Cypress maintains a listing of all data sheet documentation and a copy is available to customers upon request. This
gives a customer the ability to verify the current status of any data
sheet and it also gives that customer the ability to obtain updated
specifications as required.
Every final data sheet also contains detailed Group A subgroup
testing information. All of the specified parameters that are tested
at Group A are listed in a table at the end of each final data sheet,
with a notation as to which specific Group A test subgroups apply.
Assembly Traceability CodeGM>
Cypress Semiconductor places an assembly traceability code on
every military package that is large enough to contain the code.
The ATC automatically provides traceability for that product to
the individual wafer lot. This unique code provides Cypress with
the ability to determine which operators and equipment were used
in the manufacture of that product from start to finish.
Quality and Reliability
MIL-STD-883D and MIL-M-3851OJ spell out the toughest of
quality and reliability standards for military products. Cypress
products meet all of these requirements and more. Our in-house
quality and reliability programs are being updated regularly with
tighter and tighter objectives. Please refer to the chapter on Quality, Reliability, and Process Flows for further details.
Military Product Offerings
Cypress offers three levels of processing for military product.
First, all Cypress products are available with processing in full
compliance with MIL-STD-883, Revision D.
Second, selected products are available to the SMD (Standardized
Military Drawing) program administered by DESC. These products are not only fully MIL-STD-883D compliant, but are also
screened to the electrical requirements of the applicable military
drawing.
Third, selected products are available as JAN devices. These products are processed in full accordance with MIL-M-3851OJ and
they are screened to the electrical requirements of the applicable
JAN slash sheet.
Product Packaging
All packages for military product are hermetic. A look at the package appendix in the back of this data book will give the reader an
appreciation of the variety of packages offered. Included are cerDIPs, windowed CerDIPs, leadless chip carriers (LCCs), windowed leadless chip carriers, cerpaks, windowed cerpaks, quad
cerpaks, windowed quad cerpaks, bottom-brazed flatpacks, and
pin grid arrays. As indicated above, all of these packages are assembled in the U.S. in our highly automated San Jose plant.
Summary
Cypress Semiconductor is committed to the support of the military marketplace. Our commitment is demonstrated by our product designs, our DESC-certified facility, our documentation and
traceability, our quality and reliability programs, our support of all
levels of military processing, and by our leadership in special packaging.
Assembly 1taceability Code is a trademark of Cypress Semiconductor Corporation.
12-1
•
_
4:::~
Military Product Selector Guide
- CYPRESS
_ . , SEMlCOIDUCfOR
Static RAMs
Size
64
64
64
64
64
1K
1K
1K
1K
1K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
32K
32K
32K
32K
32K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
Organization
16 x 4-Inverting
16x4-Non-Inverting
16x4-lnverting
16 x 4-Non-Inverting
16x 4-InvertingILow Power
256x4-10K/10KHECL
256x4
256x4
256x4
256x4
4Kx 1-CS Power-Down
4Kx 1-CS Power-Down
4Kx 1-CSPower-Down
4Kx 1-CS Power-Down
1Kx4-1OK/lOKHECL
1Kx4-CSPower-Down
1Kx4-CSPower-Down
1Kx4
1Kx4
1Kx 4-Separate I/O
1Kx8-DualPort
1Kx8-Dual-Port Slave
4Kx4-CSECL
2KxB-CS Power-Down
2KxB-CSPower-Down
2KxB-CSPower-Down
16Kx 1-CSPower-Dowo
4Kx4-CSPower-Down
4Kx4
4Kx4-OutputEnabie
4Kx 4-Separate I/O
4Kx4-Separate I/O, PowerDown
2Kx8-Dual-Port
2Kx8-Dual-Port Slave
4Kx8-Dual-Port
4Kx 8-Dual-Port
4Kx8-Dual-Port Semaphores
4Kx8-Dual-Port Semaphores
Int,Busy
4Kx9-Dual-Port Semaphores
Int,Busy
8KxB-CS Power-Down
8KxB-CSPower-Down
8KxB-CS Power-Down
8KxB-CS Power-Down
8KxB-CS Power-Down
8KxB-CS Power-Down
8KxB-CSPower-Down
8Kx8-CSPower-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
16Kx4-OutputEoabie
16Kx4-0utputEnable
16Kx4-SeparateI/O, T-write
16Kx 4-Separate I/O
16Kx 4-Separate I/O
64Kx 1-CS Power-Down
8Kx8-Dual-Port Semaphores
lot, Busy
8Kx9-Dual-Port Semaphores
lot, Busy
milprodsel - 1/92
Pins
(DIP)
JAN/SMD
Number
PartNumber
20
20
20
22S
24S
24S
CY7C189
CY7Cl90
CY27S03/A
CY27S07/A
CY27LS03
CY10E422L
CY7C122
CY7Cl23
CY9122/91L22
CY93422A/93L422A
CY7C147
CY2147
CY7C147
CY2147
CY10E474L
CY7Cl48
CY2148
CY7C149
CY2149
CY7C150
CY7C130/31
CY7Cl40/41
CYIOE484L
CY7Cl28A
CY6116AnA
CY7C128A
CY7C167A
CY7Cl68A
CY7C169A
CY7C170A
CY7Cl71A
CY7C172A
48
48
48
52
52
68
CY7C132/36
CY7C142/46
CY7B134
CY7B135
CY7B1342
CY7B138
68
CY7B139
28S
28S
28S
28S
28
28
28
28
22S
22S
22S
24S
28S
28S
28S
22S
68
CY7C185A
CY7C185A
CY7Cl85A
CY7B185
CY7C186A
CY7C186A
CY7C186A
CY7B186
CY7C164A
CY7Cl64A
CY7Bl64
CY7C166A
CY7C166A
CY7B166
CY7C161A
CY7C162A
CY7B16112
CY7C187A
CY7Bl44
68
CY7B145
16
16
16
16
16
24
22
24S
22
22
18
18
18
18
24
18
18
18
18
24S
48
48
28
24S
24
24S
24S
24S
5962-8%94
5962-88594
5962-906%
5962-88594
5962-88594
M38510/289
M38510/289
5962-88587
5962-88587
5962-91518
M38510/289
M38510/289
5962-88588
5962-86875
5962-86875
5962-89690
5962-89690
84036
84132
5962-86705
5962-89790
5962-90620
5962-90620
5962-38294
5%2-8%91
5962-85525
5962-91594
5962-38294
5962-8%91
5962-85525
5962-91594
5962-8%92
5962-86859
5962-91593
5962-89892
5962-86859
5962-91593
5962-90594
5962-89712
5962-86015
12-2
IccflSBfIcCDR
883
AvailabUity
tAA-25
tAA=25
tAA=25,35
tAA =25,35
tAA=65
tAA=5,7
tAA=25,35
tAA = 10, 12, 15
tAA=35,45
tAA=45,55,60,75
tAA=35,45
tAA =45,55
tAA=35,45
tAA = 45,55
tAA=5,7
tAA=35,45
tAA = 45,55
tAA=35,45
tAA = 45,55
tAA = 12, 15,25,35
tAA = 35,45,55
tAA = 35,45,55
tAA=7,10
tAA=2O,25
tAA=2O,25
tAA = 35,45,55
tAA = 20,25,35
tAA = 20,25,35
tAA = 20,25,35
tAA = 20,25,35
tAA = 20,25,35
tAA=2O
70@25
70@25
100@35
100@25
38@65
150@5n
90@25
150@15
90@45
90@55
1l0/10@35
140/25@45
1l0/10@35
140/25@45
190@5n
1l0/1O@35
140/25@45
1l0@35
140@45
100@15
12O/40@45
120/40@45
2OO@10
125@2O
125@2O
125/40@25
70/20@25
100/20@25
100/20@35
120@25
100/20@25
9O@2O
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
2Q92
Now
Now
Now
Now
Now
Now
Now
Now
Now
tAA = 35,45,55
tAA =35,45,55
tAA=25,35
tAA=25,35
tAA=25,35
tAA=25,35
170/65@35
12O/40@45
280@25
280@25
280@25
280@25
Now
Now
2Q92
2Q92
2Q92
2Q92
tAA = 25,35
280@25
2Q92
tAA = 20,25,35,45,55
tAA = 20,25
tAA = 35,45,55
tAA = 10,12,15
tAA = 20,25,35,45,55
tAA = 20,25
tAA = 35,45,55
tAA = 10, 12, 15
tAA=20,25
tAA=35,45
tAA = 10, 12, 15
tAA = 20,25
tAA = 35,45
tAA = 10,12, 15
tAA = 20,25,35,45
tAA=2O,25,35,45
tAA= 12,15
tAA = 20,25,35,45
tAA = 25,35
125@2O
125@20
100/20/1 @45
145/50@15
125@2O
125@20
100/20/1@45
145/50@15
9O@2O
70/20/1@35
135/50@15
90@20
70/20/1@35
135/50@15
70/20/l@35
70/20/1@35
135/50@15
70/20/1@35
280@25
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
2Q92
tAA = 25,35
280@25
2Q92
Speed(ns)
(mA@ns)
:2:~
•
,
Military Product Selector Guide
;; CYPRFSS
SEMICONDUCTOR
Static RAMs (continued)
Size
Organization
64K
64K
64K
128K
128K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
16Kx4-ECL
4Kxl8-CacheThg
4Kx 18-Cache Thg
8Kx 16--Cache
8Kx 16-Cache
64Kx4-JEDEC
32KxS-JEDEC
16Kx16-CacheRAM
32Kx8-CS Power-Down
32KxS-CSPower-Down
64Kx4-CSPower-Down
64Kx4-CSPD+OElCEl
64Kx4-CSPD +OElCE2
64Kx4-SeparateI/O, T-write
64Kx 4-Separate I/O
256Kx 1-CSPower-Down
32KxS-CSPower-Down
32KxS-CSPower-Down
64Kx4-SeparateI/O, T-write
64Kx 4-Separate I/O
64Kx4-CSPower-Down
64Kx4-CSPD,OE
64Kx4-CSPD,OE,2CE
256Kx l-CommonI/O, OE
256Kx l-CSPower-Down
64Kx 4-SeIfDecoded
64Kx4-SeIfDecoded
256Kx l-SeIfDecoded,
Separate I/O
32Kx9-Synchronous Cache
128Kx8-CSPower-Down
128KxS-CSPower-Down
256Kx4-CSPower-Down/OE
256Kx 4-Separate I/O,
T-Write
256Kx 4-Separate I/O
1Mx1-CSPower-Down
256K
1M
1M
1M
1M
1M
1M
Pins
(DIP)
JAN/SMD
Number
Part Number
28
68
68
48
48
24
28
44
28
28S
24S
28S
28S
28S
28S
24S
28
28S
28S
28S
24S
28S
28S
24S
24S
28S
28S
28S
CYlOE494
CY7B181
CY7C180
CY7C183
CY7C184
CY7M194
CY7M199
CY7C157A
CY7C198
CY7C199
CY7C194
CY7C195
CY7C196
CY7C191
CY7C192
CY7CI97
CY7B198
CY7B199
CY7B191
CY7B192
CY7B194
CY7B195
CY7B196
CY7B193
CY7B197
CY7B153
CY7B154
CY7B163
44
32
32
28
32
CY7B174
CY7C108
CY7CI09
CY7CI06
CY7C101
32
28
CY7C102
CY7C107
5962-88662
5962-88662
5962-88681
5962-90664
5962-89935
5962-88725
5962-89598
5962-89598
ICcJISu/IcCDR
(mA@ns)
883
Availability
tAA=1O,12
tAA = 15.20
tAA = 15,20
tAA=35,45
tAA =35,45
tAA = 15,20
tAA = 15,20
tAA=24,
tAA = 20,25,35,45,55
tAA =20,25,35,45,55
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA =20,25,35,45
tAA = 20,25,35,45
tAA =20,25,35,45
tAA=15,20
tAA = 12, 15,20
tAA = 12, 15,20
tAA = 12, 15,20
tAA = 12, 15,20
tAA = 12,15,20
tAA = 12, 15,20
tAA = 12, 15,20
tAA =12,15,20
tAA=15,20
tAA =15,20
tAA=15,20
190@10
250@15
250@15
200@35
200@35
375@15
425@15
300@24
180/40@15
180/40@15
160/40@15
160/40@15
160/40@15
160/40@15
160/40@15
160/40@15
170/60@15
170/40@12
170/40@12
170/40@12
170/40@12
170/40@12
170/40@12
130/40@12
130/40@12
145/60@15
145/60@15
120/60@15
2Q92
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
tAA= 18,21
tAA = 25,35,45
tAA =25,35,45
tAA = 25,35,45
tAA =25,35,45
250@18
140/35@25
140/35@25
130/25@25
130/25@25
Now
Now
Now
Now
Now
tAA = 25,35,45
tAA =25,35,45
130/25@25
130/25@25
Now
Now
Speed (ns)
PROMs
Size
4K
8K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
64K
64K
64K
64K
Organization
512x S-Registered
1KxS-Registered
1Kx8
1Kx8
2KxS-ReprogrammabJe State
Machine
2KxS-ReprogrammabJe State
Machine
2Kx S-Registcred
2KxS-Registered
2Kx S-Registered
2Kx8
2Kx8
2KxS-CSPower-Down
2Kx8
2Kx8
8KxS-CSPower-Down
8KxS-CSPower-Down
8Kx8
8Kx8
milprodsel - 1/92
Pins
PartNumber
24S
24S
24S
24
28
CY7C225
CY7C235
CY7C281
CY7C282
CY7C258
28
CY7C259
24S
24S
24S
24S
24S
24S
24
24
24S
24S
24S
24
CY7C245
CY7C245A
CY7C245A
CY7C291
CY7C291A
CY7C293A
CY7C292
CY7C292A
CY7C261
CY7C261
CY7C263
CY7C264
JAN/SMD
Number[1]O
5962-88518(0)
5962-88636(0)
5962-87651(0)
5962-87651(0)
5962-87529(W)
5962-89815(W)
5962-88735(0)
5962-87650(W)
5962-88734(0)
5962-88680(W)
5962-88734(0)
5962-87515(W)
5962-90803(0)
5962-87515(W)
5962-87515(W)
12-3
Speed (ns)
IccJISB
(mA@ns)
883
Availability
tSNco = 30/15, 35/20, 40/25
tSNco = 30/15,40/20
tAA=45
tAA=45
tAA = 15,18,25
120@30/15
120@30/15
120@45
120@45
2OO@15
Now
Now
Now
Now
3Q92
tAA = 15,18,25
2OO@15
3Q92
lSNco = 35/15,45/25
tSNco = 18/12,25/12,35/15
lSNco = 25/12,35/15
tAA=35,50
tAA = 25,30,35,50
tAA =25,30,35,50
tAA=50
tAA =25,30,35,45,50
tAA =25,35,45,55
tAA = 25,35,45,55
tAA =25,35,45,55
tAA = 25,35,45,55
120@35/15
120@25/15
120@25/15
120@35
120@30
120/30@35
120@50
120@30
120/40@35
175@25
120@35
120@35
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
.r.~NDUcroR
Military Product Selector Guide
PROMs (continued)
Organization
Size
Pins
PartNumber
JAN/SMD
Number[ljO
64K
8Kx8-Registered
28S
CY7C265
5962-89967(0)
64K
64K
8Kx8-EPROM Pinout
8Kx 8-Registered/Diagnostic
28
28S
CY7C266
CY7C269
5962-91624(W)
5962-90831(0)
64K
128K
128K
256K
256K
256K
256K
256K
256K
256K
256K
256K
512K
512K
512K
512K
1M
1M
1M
8Kx 8-Registered/Diagnostic
16Kx8-CSPower-Down
16Kx8
Processor Specific
16Kx 16-Registered
16Kx 16-Registered
16Kx 16-Power-Down
16Kx16
32Kx8-CS Power-Down
32Kx 8-EPROMPinout
32Kx 8-Registered
32Kx8-Latched
64Kx8-Fast ColumnAccess
64Kx 8-EPROM Pinout
64Kx 8-Registered
64Kx 8-FCA/Regor Latched
128Kx8
64Kx 16-Power-Down
64Kx 16-Registered
32
28S
28
44
44
44
44
44
28S
28
28S
28S
28S
28
28S
32S
32
40
40
CY7C268
CY7C251
CY7C254
CY7C270
CY7C275
CY7C272
CY7C273
CY7C276
CY7C271
CY7C274
CY7C277
CY7C279
CY7C285
CY7C286
CY7C287
CY7C289
CY7B201
CY7B21O
CY7B211
5962-89537(W)
5962-89538(W)
5962-89817(W)
5967-91744(W)
5962-91637(0)
5962-90913(W)
Icc/IsB
(mA@ns)
Speed (ns)
t~ = 18/15,25/20,40/20,
50 ,60/25
tAA=55
~O = 18/15,25/20,40/20,
50 ,60/25
tSA/CO = 50/25,60/25
tAA = 45, 55, 65
tAA = 45, 55, 65
tcp=25,4O
tAS/CKO = 25/15
tcp=30
tAA=45
tAA=35
tAA= 45, 55
tAA = 45,55
tSNco = 40/20,50/25
tAA = 45,55
tAAiFCA = 75/25, 85/35
tAA =60, 70
tSA/CO = 55/20,65/25
tAAfFCA = 75/25,85/35
tAA =30
tAA=30
tSA/co = 25/15
883
Availability
120@50/25
Now
90
l00@6O/25
Now
Now
100@60/25
120/35@55
120@55
250@25
250@25
250@30
50@45
250@35
130/40@55
130/40@55
130/40@55
130/40@55
200@75
150@70
150@65
200@75
220@30
240@30
22O@25
Now
Now
Now
4092
4092
4092
4092
4092
Now
Now
Now
Now
Now
Now
Now
Now
3092
4092
4092
PLDs
Organization
PALC20
PALC20
PLD20
PLD24
PLD24
PLDC24
PLD24
PLDC24
PLD24
PLDC24
PLDC24
PLDC24
ECL
ECL
PLD24
PLDC28
PLDC28
PLDC28
PLDC28
PLD28
PLD28
PLD28
PLD28
PLD28
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
18GS-Generic
22VlOC-Macrocell
22VI0C-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
20GI0-Generic
20RAIO-Asynchronous
16P8-10KHECL
16P4-10KHECL
PLD610-Multi-Purpose
7C330-State Machine
7C331-Asynchronous
7C331-Asynchronous
7C332-Combinatorial
7B333-Synchronous
7B335-Universal State
Machine
7B336-Input Reg!2PTs
7B337-Input Reg/4PTs
MAX28
MAX40
MAX68
MAX84
PLDC28
PartNumber
JAN/SMD
Number[ljO
Availability
tpo = 20,30,40
tpo = 20,30,40
tpo/s/co = 15/15/20
tPOIS/CO = 1O/3.6n.5
tpo/s/CO = 1O/3.6n.5
tPOIS/cO = 25/18/15
tpo/s/co = 20/17/15
tPOIS/CO = 25/18/15
tpo/s/co = 15/12/10
tPOIS/CO = 20/17/15
tpo/s/co = 20/17/15
tpolSU/CO = 20/10/20
tpo=5
tpo=4
tpo= 15,17
50, 40, 28MHz
tpo = 25/30/40
tpo = 25/30/40
tpo = 20/25/30
tpo= 12,15
fMAXS = 66.6,50
70@2O
70@2O
110
190@10
19O@10
100@25
l00@20
100@25
120@15
120@25
80@30
l00@25
-240@5
-22O@4
170@15
180@40MHz
2OO@20MHz
2OO@20MHz
2OO@24MHz
170@12
16O@66.6MHz
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
2092
Now
Now
Now
Now
2092
3092
PALC16XX
PALC16XX
PLDC18G8
PAL22VI0CM
PAL22VP1OCM
PALC22VlO
PALC22VlOB
PALC22VI0
PALC22VI0B
PALC22VI0B
PLDC2OGI0
PLD20RAI0
CYIOE301
CYI0E302
PLD610
CY7C330
CY7C331
CY7C331
CY7C332
CY7B333
CY7C335
7B338-0~ut
28S
28S
28S
CY7B336
CY7B337
CY7B338
fMAXO = 131 MHz
fMAXD = 125 MHz
tpo=8
180
180
180
Now
Now
Now
7B339-O~ut
28S
CY7B339
tpo=7
180
Now
Latched/4 s
7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C361-State Machine
28S
40/44
68
84
28S
CY7C344
CY7C343
CY7C342
CY7C341
CY7C361
tPOIS/CO = 25/15/15
tpo/S/CO = 35/25/20
tpOIS/CO = 35/25/20
tpo=35
100, 83, 50 MHz
220/170
1601120
320/240
320/240
150@I00MHz
Now
Now
Now
2092
Now
milprodsel - 1/92
5962-88678(W)
5962-88713(0)
5962-91568(0)
883
Icc
(mA@ns/MHz)
Speed(ns/MHz)
20
20
20
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
28S
28S
28S
28S
28S
28
Latched12
PLD28
Pins
5962-87539(W)
5962-87539(W)
5962-88670(0)
5962-88670(0)
M38510/507(W)
5962-88637(0)
5962-90555(0)
5962-90573(0)
5962-90573(0)
5962-89546(W)
5962-90754(W)
5962-89855(0)
5962-91584(W)
s
5962-90611(W)
5962-89468(W)
12-4
Military Product Selector Guide
FIFOs
Orgaoizatioo
64 x 4-Cascadeable
64 x 4-Cascadeable
64x 4-Cascadeable/OE
64 x 5--Cascadeable
64 x 5--Cascadeable/OE
64 x 8--Cascadeable/OE
64 x 9--Cascadeable
512 x 9-Cascadeable
512 x 9--Cascadeable
lKx9-Cascadeable
lKx9--Cascadeabie
2Kx 9--Cascadeable
2Kx 9-Cascadeable
2K x 9-Bidirectional
4Kx9--Cascadeable
4Kx9-Cascadeable
512x 9--Clocked
2Kx 9--CJocked
512 x 9--CJockediCascadeable
2Kx 9--Clocked/Cascadeable
8Kx 9-HaifFull Flag
8Kx9-Prog. Flags
16Kx9-HalfFuJlFlag
16Kx9-Prog. Flags
32Kx 9-HaifFull Flag
32Kx 9-Prog. Flags
Pios
PartNumber
16
16
16
18
18
28S
28S
28
28S
28
28S
28
28S
28S
28
28S
28S
28S
32
32
28
28
28
28
28
28
CY3341
CY7C401
CY7C403
CY7C402
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C439
CY7C432
CY7C433
CY7C441
CY7C443
CY7C451
CY7C453
CY7C460
CY7C470
CY7C462
CY7C472
CY7C464
CY7C474
JAN/SM»
Number
5962·89523
5%2-86846
5962-89664
5%2·89661
5%2·89863
5962-89863
5962-91585
5%2-91585
5%2-88669
5%2-88669
5962-90715
5962-90715
ICc/ISB
(mA@ns/MHz)
Speed
1.2, 2 MHz
10, 15, 25 MHz
10, 15, 25 MHz
10, 15,25 MHz
10, 15, 25 MHz
15, 25 MHz
15, 25 MHz
tA = 25, 30,40, 65 os
tA = 25, 30, 40, 65 08
tA = 25, 30,40, 65 ns
tA = 25, 30,40, 65ns
tA = 25, 30,40, 65ns
tA = 25, 30,40, 65 os
tA = 40, 65ns
tA = 30,40,6508
tA =30,40,6508
tc =14, 20,3008
tc=14,2O,3008
tc=14,20,300s
tc=14,20,300s
tA = 15, 25, 40 os
tA = 15,25,4008
tA = 15,25,4008
tA = 15, 25,40ns
tA = 15,25,4Ons
tA = 15, 25, 40ns
60@2.0MHz
90@15MHz
90@25MHz
90@15MHz
90@25MHz
120@25MHz
12O@25MHz
14O/30@30
14O/30@30
14O/30@30
14O/30@30
14O/30@30
14O/30@30
165/45@40
160/30@30
160/30@30
200@14
2OO@14
200@14
200@14
180@25
180@25
lSO@25
lSO@25
180@25
lSO@25
883
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Logic
Organization
Programmable Skew Clock Buffer
(TIL Outputs)
~ammable Skew Clock Buffer
OS Outputs)
(
2901-4-Bit Slice
2901-4-Bit Slice
4x2901-16-BitSlice
2909-Sequencer
2911-Sequencer
2909-Sequencer
2911--Sequencer
2910--C0ntroller (17-Word Stack)
2910--C0ntroller (9-Word Stack)
16-Bit Microprogrammed ALV
16-Bit Microprogrammed ALV
16x16Muitiplier
16x 16 Multiplier
16x 16 Multiplier/Accumulator
Pins
PartNumber
32
CY7B991
32
CY7B992
40
40
64
28
20
28
20
40
40
52
68
64
64
64
CY7C901
CY2901C
CY7C9101
CY7C909
CY7C911
CY2909A
CY2911A
CY7C910
CY2910A
CY7C9116
CY7C9117
CY7C516
CY7C517
CY7C510
JAN/SMD
Number
5962-88535
5962-88535
5962-89517
5962-90609
5962-90609
5962-87708
5962-87708
5962-88612
5962-86873
5962-87686
5962-88733
Icc
(mA@ns)
Speed (ns)
883
Availability
fREF = 15 - 80MHz
65
3Q92
fREF= 15 -80MHz
65
3Q92
tCLK = 27,32
C
tCLK=35,45
tCLK=30,4O
tCLK=30,4O
A
A
tCLK = 46,51,99
A
40,65,79
40,65,79
tMC = 42, 55, 75
tMC = 42, 55, 75
tMC = 55,65, 75
90@27
180@32
85@35
55@30
55@30
90@4O
90@4O
90@46
170@51
166@lOMHz
166@10MHz
1l0@10MHz
1l0@10MHz
1l0@10MHz
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
VMEbus Interface Products
Organization
Pins
VME Interface Controller
VMEAddress Controller
64-BitVIC
144/160
144/160
144/160
milprodsel - 1/92
Speed (MHz)
Part Number
VIC068A
VAC068A
VIC64
64
50
64
12-5
ICC
(mA)
250
150
300
Packages
B,G,N,V
B,G,N,V
B,G,N,V
883
Avallability
Now
Now
Now
~
~~
5&11'..
Military Product Selector Guide
CYPRESS
'SEMICONDUCTOR
Communication Products
Organization
HotLink 'fransmitter
HotLink 'ftansmitter
HotLink 'ftansmitter
HotLink Receiver
HotLink Receiver
HotLink Receiver
Pins
Speed (MHz)
PartNumber
28
28
28
28
28
28
130-170
170-240
240-310
130-170
170-240
240-310
CY7B921
CY7B922
CY7B923
CY7B931
CY7B932
CY7B933
Icc
(mA)
TBA
TBA
TBA
TBA
TBA
TBA
Packages
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
883
Availability
4092
4Q92
4Q92
4092
4092
4Q92
Modules
Size
Organization
Pins
Part Number
Packages
Speed (ns)
Icc
(mA@ns)
883
Availability
,
SRAMs
375@12
425@12
550@15;330
@25
480@25
21O@35
340@45
1250@25
400@35
880@35
720@25
350@35
Now
Now
Now
Now
Now
Now
1Q92
Now
HD05
HDll
tAA = 15,20
tAA=15,2O
tAA = 15,20,25,35,
45,50
tAA = 25,35,45
tAA =35,45,55
tAA = 35,45,55
tAA = 25,30,35,45
tAA = 35, 45, 55, 70
tAA =35,45,55
tAA = 25,30,35
tAA = 35,45,55,70
85,100,120
tAA =35,45,55
tAA =35,45,55
1800@35
1120@35
Now
Now
HD10
HD10
tA = 40,50,65
tA = 40, 50, 65
640@40
640@40
Now
Now
256K
256K
256K
64Kx4 SRAM(JEDEC)
32Kx8 SRAM(JEDEC)
16Kx16 SRAM(JEDEC)
24
28
40
CYM1220
CYM1400
CYM1610
HD08
HD09
HD01
1M
1M
1M
1M
1M
2M
4M
4M
256Kx4 SRAM (JEDEC)
128Kx8 SRAM(JEDEC)
64Kx16 SRAM(JEDEC)
64Kx16SRAM
32Kx32SRAM
64Kx32SRAM
128Kx32SRAM
512Kx8SRAM
28
32
40
40
66
60
66
32
CYM1240
CYM1420
CYM1620
CYM1621
CYM1828
CYM1830
CYM1838
CYM1466
HD07
HD04
HD03
HD02
HG01
HD06
4M
8M
FIFO.
256Kx16 SRAM
256Kx32 SRAM
48
60
CYMl641
CYMI840
8Kx 9 Cascadeable FIFO
16Kx 9 Cascadeable FIFO
28
28
CYM4210
CYM4220
HD12
Now
Now
Now
Notes:
The Cypress facility at 3901 North First Street in San Jose, CA is DESC-certified for JAN class B production.
All of the above products are available with processing to MIlrSTD-883D at a minimum. Many of these products are also available either to SMDs
(Standardized Military Drawings) or to JAN slash sheets.
The speed and power specifications listed above cover the full military temperature range.
Modules are available with MIlrSTD-883D components. These modules are assembled and screened to the proposed JEDEC military processing
standard for modules.
W = Windowed Package
o = Opaque Package
HD = Hermetic DIP Module
HV = Hermetic Vertical DIP
lOOK ECL devices are available ouly to extended temperature range.
22S stands for 22-pin 300-mil DIP.
24S stands for 24-pin 300-mil DIP.
28S stands for 28-pin 300-mil DIP.
milprodsel - 1/92
12-6
~
2 ;~PRFSS
,
Military Ordering Information
SEMICONDUCTOR
Cypress Semiconductor fully supports the DESC standardized
Military Drawing Program for devices that are compliant to the
Class B requirements of MIL-STD-883D.
Listed below are the SMDs for which Cypress is an approved
source of supply. Please contact your local Cypress representative for the latest SMD update.
DESC SMD (Standardized Military Drawing) Approvals!!]
Package[3]
SMDNumber
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84036
84132
84132
84132
84132
84132
84132
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-38294
5962-85525
5962-85525
5962-85525
5962-85525
5962-85525
5962-85525
mildesc - 1/92
09JX
09KX
09LX
09XX
09YX
093X
IlJX
llKX
llLX
llXX
llYX
113X
14JX
14KX
14LX
14XX
14YX
143X
02RX
02SX
02YX
05RX
05SX
05YX
09MTX
23MUX
09MXX
09MYX
09MZX
llMTX
25MUX
llMXX
llMYX
llMZX
13MTX
27MUX
13MXX
13MYX
13MZX
15MTX
29MUX
15MXX
15MYX
15MZX
17MTX
30MUX
17MXX
17MYX
17MZX
05TX
05UX
05XX
05ZX
06TX
06UX
Cypress!2]
Part Number
CY6116A -45DMB
CY7CI28A-45KMB
CY7CI28A -45DMB
CY6117A-45LMB
CY7CI28A-45LMB
CY6116A-45LMB
CY6116A-55DMB
CY7CI28A-55KMB
CY7CI28A-55DMB
CY6117A-55LMB
CY7C128A -55LMB
CY6116A - 55LMB
CY6116A-35DMB
CY7C128A-35KMB
CY7CI28A-35DMB
CY6117A-35LMB
CY7CI28A-35LMB
CY6116A - 35LMB
CY7CI67A-45DMB
CY7C167A-45KMB
CY7CI67A-45LMB
CY7C167A-35DMB
CY7CI67A-35KMB
CY7CI67A-35LMB
CY7C185A-55KMB
CY7CI85A-55LMB
CY7C186A-55DMB
CY7CI86A-55LMB
CY7CI85A-55DMB
CY7C185A -45KMB
CY7C185A -45LMB
CY7C186A -45DMB
CY7C186A -45LMB
CY7C185A -45DMB
CY7C185A-35KMB
CY7CI85A-35LMB
CY7CI86A-35DMB
CY7C186A -35LMB
CY7CI85A-35DMB
CY7CI85A-25KMB
CY7C185A -25LMB
CY7C186A - 25DMB
CY7CI86A-25LMB
CY7CI85A-25DMB
CY7C185A - 20KMB
CY7C185A-20LMB
CY7CI86A-20DMB
CY7C186A -20LMB
CY7CI85A-20DMB
CY7C185A-55KMB
CY7C185A -55LMB
CY7CI86A-55DMB
CY7CI85A-55DMB
CY7C185A -45KMB
CY7CI85A-45LMB
Description
'iYpe
24.6 DIP
24CP
24.3 DIP
32RLCC
24RLCC
28SLCC
24.6 DIP
24CP
24.3 DIP
32RLCC
24RLCC
28SLCC
24.6 DIP
24CP
24.3 DIP
32RLCC
24RLCC
28SLCC
20.3 DIP
20CP
20RLCC
20.3 DIP
20CP
20RLCC
28CP
28R TLCC
28.6 DIP
32RLCC
28.3 DIP
28CP
28RTLCC
28.6 DIP
32RLCC
28.3 DIP
28CP
28RTLCC
28.6 DIP
32RLCC
28.3 DIP
28CP
28RTLCC
28.6 DIP
32RLCC
28.3 DIP
28CP
28R TLCC
28.6 DIP
32RLCC
28.3 DIP
28CP
28RTLCC
28.6 DIP
28.3 DIP
28CP
28RTLCC
D12
K73
014
LS5
LS3
12-7
L64
D12
K73
014
LS5
014
L64
012
K73
D14
LS5
LS3
L64
D6
K71
LSI
D6
K71
LSI
K74
LS4
D16
LS5
D22
K74
LS4
016
LS5
D22
K74
LS4
016
LS5
D22
K74
LS4
016
LS5
D22
K74
LS4
016
LS5
D22
K74
LS4
016
D22
K74
LS4
Product
Description
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8SRAM
2Kx8 SRAM
2Kx8SRAM
2Kx8 SRAM
2Kx8 SRAM
2Kx8SRAM
16K x 1 SRAM
16KxlSRAM
16K x 1 SRAM
16Kxl SRAM
16Kxl SRAM
16Kxl SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8 SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8 SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8 SRAM
8Kx8 SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8 SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8 SRAM
8Kx8SRAM
8Kx8SRAM
II
·&;~PRFSS
~_.,
Military Ordering Information
SEMICCtIDUCl'OR
DESC SMD (Standardized Military Drawing) Approvals[l]
(continued)
Package[3]
SMDNumber
5962-85525
5962-85525
5962-85525
5962-85525
5962-85525
5962-85525
5962-86015
5962-86015
5962-86015
5962-86015
5962-86015
5962-86015
5962-86015
5962-86015
5962-86705
5962-86705
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86859
5962-86873
5962-86873
5962-86873
5962-86873
5962-86873
mildesc - 1/92
06XX
06ZX
07TX
07UX
07XX
07ZX
01YX
01ZX
02YX
02ZX
03YX
03ZX
04YX
04ZX
12RX
12XX
01VX
012X
01XX
02VX
022X
02XX
03VX
032X
03XX
15KX
15LX
15UX
15XX
16KX
16LX
16UX
16XX
17KX
17LX
17UX
17XX
18KX
18LX
18UX
18XX
21KX
21YX
21ZX
22KX
22YX
22ZX
23KX
23YX
23ZX
24KX
24YX
24ZX
O1XX
O1YX
O1ZX
01UX
02XX
Cypres.[2]
Part Number
CY7CI86A-45DMB
CY7C185A-45DMB
CY7C185A - 35KMB
CY7C185A-35LMB
CY7C186A-35DMB
CY7C185A-35DMB
CY7C187A-35DMB
CY7C187A-35LMB
CY7C187AL-35DMB
CY7C187AL-35LMB
CY7CI87A-45DMB
CY7CI87A-45LMB
CY7CI87AL-45DMB
CY7C187AL-45LMB
CY7C168A - 35DMB
CY7C168A-35LMB
CY7C404-10DMB
CY7C404-10LMB
CY7C404-lOKMB
CY7C404-15DMB
CY7C404-15LMB
CY7C404-15KMB
CY7C404-25DMB
CY7C404-25LMB
CY7C404-25KMB
CY7C166AL-45KMB
CY7C166AL-45DMB
CY7CI66AL-45LMB
CY7C166AL-45LMB
CY7CI66A-45KMB
CY7Cl66A -45DMB
CY7Cl66A-45LMB
CY7C166A -45LMB
CY7C166AL-35KMB
CY7C166AL-35DMB
CY7C166AL-35LMB
CY7CI66AL-35LMB
CY7C166A-35KMB
CY7C166A-35DMB
CY7C166A-35LMB
CY7CI66A-35LMB
CY7C164AL-45KMB
CY7CI64AL-45DMB
CY7CI64AL-45LMB
CY7C164A-45KMB
CY7CI64A-45DMB
CY7C164A -45LMB
CY7CI64AL-35KMB
CY7CI64AL-35DMB
CY7CI64AL-35LMB
CY7C164A-35KMB
CY7CI64A-35DMB
CY7C164A-35LMB
CY7C516-42DMB
CY7C516-42LMB
CY7C516-42GMB
CY7C516-42FMB
CY7C516-55DMB
Description
1YPe
28.6 DIP
28.3 DIP
28CP
28RTLCC
28.6DlP
28.3 DIP
22.3 DIP
22RLCC
22.3 DIP
22RLCC
22.3 DIP
22RLCC
22.3 DIP
22RLCC
20.3 DlP
20RLCC
18.3 DlP
20SLCC
18CP
18.3 DIP
20SLCC
18CP
18.3 DlP
20SLCC
18CP
24CP
24.3 DIP
28RLCC
28R ncc
24CP
24.3 DlP
28RLCC
28R TLCC
24CP
24.3 DlP
28RLCC
28R TLCC
24CP
24.3 DIP
28RLCC
28RTLCC
24CP
22.3 DIP
22RLCC
24CP
22.3 DlP
22RLCC
24CP
22.3 DlP
22RLCC
24CP
22.3 DIP
22RLCC
64DlP
68SLCC
68PGA
64QFP
64 DIP
Dl6
D22
K74
1.54
Dl6
D22
DlO
1.52
DlO
1.52
D10
1.52
D10
1.52
D6
1.51
D4
L61
K70
D4
L61
K70
D4
L61
K70
K73
Dl4
1.54
1.54
K73
Dl4
1.54
1.54
K73
D14
1.54
1.54
K73
Dl4
1.54
1.54
K73
DlO
1.52
K73
DlO
1.52
K73
DlO
1.52
K73
DlO
1.52
D30
LSI
G68
12-8
F90
D30
Product
Description
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
8Kx8SRAM
64Kx 1 SRAM
64Kxl SRAM
64Kxl SRAM
64Kx1SRAM
64Kxl SRAM
64Kxl SRAM
64Kx1 SRAM
64Kx 1 SRAM
4Kx4SRAM
4Kx4SRAM
64x5 FIFO
64x5 FIFO
64x5 FIFO
64x5 FIFO
64x5 FlFO
64x5 FIFO
64x5 FlFO
64x5 FlFO
64x5 FIFO
16Kx4SRAMW/OE
16Kx4SRAMW/OE
16Kx4SRAMW/OE
16Kx4 SRAM W/OE
16K x 4 SRAM W/OE
16Kx4SRAMW/OE
16Kx4SRAMW/OE
16K x 4 SRAM W/OE
16Kx4SRAMW/OE
16K x 4 SRAM W/OE
16K x 4 SRAM W/OE
16Kx4SRAMW/OE
16Kx4 SRAM W/OE
16K x 4 SRAM W/OE
16K x 4 SRAM W/OE
16Kx4SRAMW/OE
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
-==-.~
• CYPRESS
•i
Military Ordering Information
SEMICONDUClOR
DESC SMD (Standardized Military Drawing) Approvais[l]
(continued)
Packagel3]
SMDNumber
5962-86873
5962-86873
5962-86873
5962-86873
5962-86873
5962-86873
5962-86873
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87529
5962-87529
5962-87529
5962-87529
5962-87529
5962-87529
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-87651
5962-87651
mildesc - 1/92
02YX
02ZX
02UX
03XX
03YX
03ZX
03UX
03XX
03YX
03ZX
03UX
04XX
04YX
04ZX
04UX
llXX
llYX
llZX
llUX
12XX
12YX
12ZX
12UX
17XX
17YX
17ZX
18XX
18YX
18ZX
05KX
05LX
053X
06KX
06LX
063X
01KX
01LX
013X
02KX
02LX
023X
01KX
OlLX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
01KX
01LX
0l3X
03KX
03LX
033X
OUX
OlKX
Cypressl2]
Part Number
CY7C516-55LMB
CY7C516-55GMB
CY7C516-55FMB
CY7C516-75DMB
CY7C516-75LMB
CY7C516-75GMB
CY7C516-75FMB
CY7C130-55DMB
CY7C130-55LMB
CY7C131-55LMB
CY7C131-55FMB
CY7C130-45DMB
CY7C130-45LMB
CY7C131-45LMB
CY7C131-45FMB
CY7C140-55DMB
CY7CI40-55LMB
CY7CI41-55LMB
CY7CI41-55FMB
CY7CI40-45DMB
CY7CI40-45LMB
CY7C141-45LMB
CY7C141-45FMB
CY7C130- 35DMB
CY7C130-35LMB
CY7C131-35LMB
CY7C140-35DMB
CY7CI40-35LMB
CY7C141-35LMB
CY7C261-451MB
CY7C261-45WMB
CY7C261-45QMB
CY7C261-55TMB
CY7C261-55WMB
CY7C261-55QMB
CY7C245-451MB
CY7C245 -45WMB
CY7C245 -45QMB
CY7C245 - 351MB
CY7C245-35WMB
CY7C245-35QMB
PALC22VI0-25TMB
PALC22VI0-25WMB
PALC22VI0-25QMB
PALC22V10-30TMB
PALC22VlO-30WMB
PALC22VlO-30QMB
PALC22VI0-401MB
PALC22VI0-40WMB
PALC22VI0-40QMB
PALC22VI0B-201MB
PALC22VI0B-20WMB
PALC22V10B-ZOQMB
CY7C291-5OTMB
CY7C291-50WMB
CY7C291-50QMB
CY7C291-351MB
CY7C291-35WMB
CY7C291-35QMB
CY7C282-45DMB
CY7C281-45KMB
Description
1YJle
68SLCC
68PGA
64QFP
64 DIP
68SLCC
68PGA
64QFP
48.6 DIP
48LCC
52LCC
64QFP
48.6 DIP
48LCC
52LCC
64QFP
48.6 DIP
48LCC
52LCC
64QFP
48.6 DIP
48LCC
52LCC
64QFP
48.6 DIP
48LCC
52LCC
48.6 DIP
48LCC
52LCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24.6 DIP
24CP
LSI
G68
F90
D30
LSI
G68
F90
D26
L68
L69
F90
D26
L68
L69
F90
D26
L68
L69
F90
D26
L68
L69
F90
D26
L68
L69
D26
L68
L69
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
173
W14
Q64
D12
K73
12-9
Product
Description
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
lK x 8 Dual·Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
1K x 8 Dual-Port SRAM
lKx 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8Kx8UVEPROM
8K x 8 UV EPROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
2K x 8 UV EPROM
2K x 8 UV EPROM
2K x 8 UV EPROM
2Kx 8 UV EPROM
2Kx8UVEPROM
2Kx8UVEPROM
lKx8 PROM
1Kx8PROM
Military Ordering Information
DESC SMD (Standardized Military Drawing) ApprovaJS!11 (continued)
Package[3]
SMDNumber
5962-87651
5962-87651
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87686
5962-87708
5962-87708
5962-87708
5962-87708
5962-87708
5962-87708
5962-88518
5962-88518
5962-88518
5962-88518
5962-88518
5962-88518
5962-88535
5962-88535
5962-88535
5962-88535
5962-88535
5962-88535
5962-88587
5962-88587
5962-88587
5962-88587
5962-88587
5962-88587
5962-88588
5962-88588
5962-88588
5962-88588
5962-88588
5962-88588
5962-88588
5962-88588
5962-88588
5962-88594
5962-88594
5962-88594
5962-88594
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
5962-88612
mildesc - 1/92
OlLX
0l3X
01XX
01YX
01ZX
01UX
02XX
02YX
02ZX
02UX
03XX
03YX
03ZX
03UX
01QX
01UX
04QX
04UX
05QX
05UX
01LX
0l3X
02LX
023X
03LX
033X
01QX
01XX
01YX
02QX
02XX
02YX
01VX
01XX
01YX
02VX
02XX
02YX
01KX
01LX
01XX
02KX
02LX
02XX
03KX
03LX
03XX
02WX
02KX
03WX
03KX
OlXX
01YX
01UX
02XX
02YX
02UX
03XX
03YX
03UX
04XX
Cypress[21
Part Number
Description
'JYpe
CY7C281-45DMB
CY7C281-45LMB
CY7C517-42OMB
CY7C517-42LMB
CY7C517-42GMB
CY7C517-42FMB
CY7C517-55DMB
CY7C517-55LMB
CY7C517-55GMB
CY7C517-55FMB
CY7C517-75DMB
CY7C517-75LMB
CY7C517-75GMB
CY7C517-75FMB
CY2910ADMB
CY2910ALMB
CY7C910-51DMB
CY7C91O-51LMB
CY7C910-46DMB
CY7C910-46LMB
CY7C225-30DMB
CY7C225-30LMB
CY7C225-35DMB
CY7C225-35LMB
CY7C225-4ODMB
CY7C225-4OLMB
CY7C901-320MB
CY7C901-32LMB
CY7C901-32FMB
CY7C901-27DMB
CY7C901-27LMB
CY7C901-27FMB
CY7C147-45DMB
CY7C147-45KMB
CY7C147-45LMB
CY7C147-35DMB
CY7C147-35KMB
CY7C147-35LMB
CY7C150-35KMB
CY7C150-35DMB
CY7C150-35LMB
CY7C150-25KMB
CY7C150-25DMB
CY7C150-25LMB
CY7C150-15KMB
CY7C150-15DMB
CY7C150-15LMB
CY7C122-35DMB
CY7C122-35KMB
CY7C122-25DMB
CY7C122-25KMB
CY7C9116-99DMB
CY7C9116-99FMB
CY7C9116-99LMB
CY7C9116-75DMB
CY7C9116-75FMB
CY7C9116-75LMB
CY7C9116-65DMB
CY7C9116-65FMB
CY7C9116-65LMB
CY7C9116-4ODMB
24.3 DIP
28SLCC
64 DIP
68SLCC
68PGA
64QFP
64 DIP
68SLCC
68PGA
64QFP
64 DIP
68SLCC
68PGA
64QFP
40.6 DIP
44LCC
40.6 DIP
44LCC
40.6 DIP
44LCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
40.6 DIP
44LCC
42FP
40.6 DIP
44LCC
42FP
18.3 DIP
18CP
18RLCC
18.3 DIP
18 CP
18RLCC
24CP
24.3 DIP
28RLCC
24CP
24.3 DIP
28RLCC
24CP
24.3 DIP
28RLCC
22.4 DIP
24CP
22.4 DIP
24CP
52.8 DIP
64FP
52SLCC
52.8 DIP
64FP
52SLCC
52.8 DIP
64FP
52SLCC
52.8 DIP
014
L64
030
LS1
G68
F90
030
LS1
G68
F90
030
LS1
G68
F90
018
L67
D18
L67
018
L67
014
12-10
L64
014
L64
D14
L64
018
L67
F76
018
L67
F76
D4
K70
LSO
D4
K70
LSO
K73
014
LS4
K73
014
LS4
K73
D14
LS4
D8
K73
D8
K73
D28
F90
L69
D28
F90
L69
D28
F90
L69
D28
Product
Description
1Kx8PROM
1Kx8PROM
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
Microprogram Controller
Microprogram Controller
Microprogram Controller
Microprogram Controller
Microprogram Controller
Microprogram Controller
512 x 8 Registered PROM
512 x 8 Registered PROM
512 x 8 Registered PROM
512 x 8 Registered PROM
512 x 8 Registered PROM
512 x 8 Registered PROM
4-Bit Slice
4-Bit Slice
4-Bit Slice
4-Bit Slice
4-Bit Slice
4-Bit Slice
4Kx1SRAM
4Kx1SRAM
4Kx1SRAM
4Kx1SRAM
4Kx1SRAM
4Kx1SRAM
1K x 4 SRAM with Reset
1K x 4 SRAM with Reset
1Kx 4 SRAM with Reset
1Kx 4 SRAM with Reset
1K x 4 SRAM with Reset
1K x 4 SRAM with Reset
1Kx 4 SRAM with Reset
1K x 4 SRAM with Reset
1K x 4 SRAM with Reset
256x4SRAM
256x4SRAM
256x4SRAM
256x4SRAM
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microprogrammed ALU
16-Bit Microorol!11llllllled ALU
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals!!]
(continued)
Package!3]
SMDNumber
5962-88612
5962-88612
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88637
5962-88637
5962-88637
5962-88637
5962-88637
5962-88637
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
5962-88678
mildesc - 1/92
04YX
04UX
OlKX
OlLX
013X
02KX
02LX
023X
OlKX
OlLX
0l3X
02KX
02LX
023X
03UX
03XX
03YX
03NX
04UX
04XX
04YX
04NX
05NX
06NX
02UX
02XX
02YX
02ZX
03UX
03XX
03YX
03ZX
04UX
04XX
04YX
04ZX
05UX
05XX
05YX
05ZX
OlKX
OlLX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
05KX
05LX
053X
OlRX
OlSX
OlXX
02RX
02SX
02XX
Cypress[2]
Part Number
CY7C9116-40FMB
CY7C9116-40lMB
CY7C235-40KMB
CY7C235-40DMB
CY7C235-40lMB
CY7C235-30KMB
CY7C235-30DMB
CY7C235-30lMB
PLDC20GlO-40KMB
PLDC20GlO-40DMB
PLDC20GlO-40lMB
PLDC20GlO-30KMB
PLDC20GlO-30DMB
PLDC20GlO-30LMB
CY7C199-55LMB
CY7C198-55DMB
CY7C198-55LMB
CY7C199-55DMB
CY7C199-45LMB
CY7C198-45DMB
CY7C198-45LMB
CY7C199-45DMB
CY7C199-35DMB
CY7C199-25DMB
CY7C429-65KMB
CY7C428-65DMB
CY7C429-65DMB
CY7C429-65LMB
CY7C429- 50KMB
CY7C428-50DMB
CY7C429-50DMB
CY7C429-50LMB
CY7C429-40KMB
CY7C428-40DMB
CY7C429-40DMB
CY7C429-40LMB
CY7C429-30KMB
CY7C428-30DMB
CY7C429-30DMB
CY7C429-30LMB
PALC22VlO-25KMB
PALC22VlO-25DMB
PALC22VlO-25LMB
PALC22VlO-30KMB
PALC22VlO-30DMB
PALC22VlO-30lMB
PALC22VlO-40KMB
PALC22VlO-40DMB
PALC22VlO-40lMB
PALC22VlOB-20KMB
PALC22VlOB-20DMB
PALC22VlOB-20LMB
PALC22VlOB-15KMB
PALC22VlOB-15DMB
PALC22VlOB-15LMB
PALC16L8-40WMB
PALC16L8-40TMB
PALC16L8-40QMB
PALC16R8-40WMB
PALC16R8-4OTMB
PALC16R8-40QMB
Description
lYPe
64FP
52SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
28RLCC
28.6 DIP
32RLCC
28.3 DIP
28RLCC
28.6 DIP
32RLCC
28.3 DIP
28.3 DIP
28.3 DIP
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
20.3 DIP
20CP
20SLCC
20.3 DIP
20CP
20SLCC
F90
L69
K73
014
L64
K73
014
L64
K73
014
L64
K73
014
L64
L54
016
L55
D22
L54
016
L55
022
022
D22
K74
016
D22
L55
K74
016
D22
L55
K74
016
D22
L55
K74
DI6
D22
L55
K73
014
L64
K73
014
L64
K73
014
L64
K73
014
L64
K73
014
L64
W6
T1l
Q6l
W6
T1l
Q6l
12-11
Product
Description
l6-Bit Microprogrammed ALU
l6-Bit Microprogrammed ALU
lKx 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
Generic CMOS PLD
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
2Kx9 FIFO
2Kx9 FIFO
2Kx9 FIFO
2Kx9 FIFO
2Kx9 FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx 9 FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
24-Pin CMOS PLD
2O-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
20-Pin CMOS UV EPLD
II
>
a::
e
CY7C186A-200MB
CY7CI85A-ZOOMB
CY7C164A - 25KMB
CY7CI64A-250MB
CY7CI64A-25LMB
CY7C164A - 20KMB
CY7CI64A-200MB
CY7C164A - 20LMB
CY7C190-250MB
CY7CI90-25KMB
CY7CI90-25LMB
CY7CI62A-45LMB
CY7CI62A-450MB
CY7CI62A -45KMB
CY7CI62A -45LMB
CY7CI62A-35LMB
CY7CI62A-350MB
CY7CI62A-35KMB
CY7C162A-35LMB
CY7CI62A-25LMB
CY7CI62A-250MB
CY7CI62A-25KMB
CY7CI62A-25LMB
CY7CI62A-20LMB
CY7CI62A-200MB
CY7CI62A-ZOKMB
CY7CI62A-20LMB
CY7C245A-35WMB
CY7C245A -35TMB
CY7C245A-35QMB
CY7C245A - 25WMB
CY7C245A - 25TMB
CY7C245A - 25QMB
CY7C245A -18WMB
CY7C245A -18TMB
CY7C245A -18QMB
CY7C271-55WMB
CY7C271-55TMB
CY7C271-55QMB
CY7C271-45WMB
CY7C271-45TMB
CY7C271-45QMB
CY7C331-400MB
CY7C331-40KMB
CY7C331-40YMB
CY7C331-40LMB
CY7C331- 300MB
CY7C331-30KMB
CY7C331- 30YMB
CY7C331- 30LMB
CY7C331-250MB
CY7C331-25KMB
CY7C331-25YMB
CY7C331-25LMB
CY7C421-65KMB
CY7C420-650MB
CY7C421-650MB
CY7C421-65LMB
CY7C421-50KMB
CY7C420-500MB
CY7C421-500MB
28.6 DIP
28.3 DIP
24CP
22.3 DIP
22RLCC
24CP
22.3 DIP
22RLCC
16.3 DIP
16CP
ZOSLCC
28RLCC
28.3 DIP
28CP
28R 1LCC
28RLCC
28.3 DIP
28CP
28R 1LCC
28RLCC
28.3 DIP
28CP
28R 1LCC
28RLCC
28.3 DIP
28CP
28R 1LCC
24.3 DIP
24CP
28SLCC
24.3 DIP
24CP
28SLCC
24.3 DIP
24CP
28SLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
28SJCQ
28SLCC
28.3 DIP
28CP
28SJCQ
28SLCC
28.3 DIP
28CP
28SJCQ
28SLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
016
022
K73
010
L52
K73
010
L52
02
K69
L61
L54
022
K74
L54
L54
022
K74
L54
L54
022
K74
L54
L54
022
K74
L54
W14
T73
Q64
W14
T73
Q64
W14
T73
Q64
W16
T74
Q55
W16
T74
Q55
022
K74
Y64
L64
022
K74
Y64
L64
022
K74
Y64
L64
K74
016
022
L55
K74
016
022
12-15
Product
Description
8Kx8 SRAM
8Kx8SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16Kx4SRAM
16x4SRAM
16x4SRAM
16x4SRAM
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
16K x 4 SRAM with Separate I/O
2K x 8 Registered UV EPROM
2K x 8 Registered UV EPROM
2K x 8 Registered UV EPROM
2K x 8 Registered UV EPROM
2K x 8 Registered UV EPROM
2Kx8 Registered UV EPROM
2K x 8 Registered UV EPROM
2Kx 8 Registered UV EPROM
2K x 8 Registered UV EPROM
32Kx 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
Asynchronous Pill
Asynchronous PLO
Asynchronous Pill
Asynchronous PLO
Asynchronous PLO
Asynchronous Pill
Asynchronous PLO
Asynchronous PLO
Asynchronous PLO
Asynchronous PLO
Asynchronous Pill
Asynchronous PLO
512x9 FIFO
512x9 FIFO
512x9 FIFO
512x 9 FIFO
512x 9 FIFO
512x9F1FO
512x 9 FIFO
&:~
Military Ordering Information
~I ~CONDUCTOR
DESC SMD (Standardized Military Drawing) Approvals!1l
(continued)
Package[3]
SMDNumber
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89892
5962-89892
5962-89892
5962-89892
5962-89892
5962-89892
5962-89892
5962-89892
5962-90573
5962-90573
5962-90573
5962-90573
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
03ZX
04UX
04XX
04YX
04ZX
05UX
05XX
05YX
05ZX
06UX
06XX
06YX
06ZX
02KX
02LX
02XX
02YX
04KX
04LX
04XX
04YX
OlLX
OlXX
02LX
02XX
OlMXX
OlMYX
OlMZX
OlM3X
02MXX
02MYX
02MZX
02M3X
03MXX
03MYX
03MZX
03M3X
Cypress[l]
Part Number
Description
1YPe
CY7C421-50lMB
CY7C421-40KMB
CY7C420-40DMB
CY7C421-40DMB
CY7C421-40LMB
CY7C421-30KMB
CY7C420-30DMB
CY7C421- 30DMB
CY7C421-30lMB
CY7C421-25KMB
CY7C420-25DMB
CY7C421-25DMB
CY7C421-25lMB
CY7CI66A-25KMB
CY7CI66A-25DMB
CY7CI66A-25LMB
CY7CI66A-25LMB
CY7CI66A-20KMB
CY7CI66A-20DMB
CY7CI66A-20LMB
CY7C166A-20LMB
CYI0E301-5DMB
CYI0E30l-5YMB
CYI0E302-4DMB
CYI0E302-4YMB
CY7C331-40WMB
CY7C331-4OTMB
CY7C331-40HMB
CY7C331-400MB
CY7C331- 30WMB
CY7C331-3OTMB
CY7C331-30HMB
CY7C331-300MB
CY7C331-25WMB
CY7C331-25TMB
CY7C331-25HMB
CY7C331-250MB
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
28CP
28.6 DIP
28.3 DIP
32RLCC
24CP
24.3 DIP
28RLCC
28R TLCC
24CP
24.3 DIP
28RLCC
28RTLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
28.3 DIP
28CP
28SJCO
28SLCC
28.3 DIP
28CP
28SJCO
28SLCC
28.3 DIP
28CP
28SJCQ
28SLCC
155
K74
016
D22
155
K74
016
D22
155
K74
016
D22
155
K73
014
154
154
K73
014
154
154
014
Y64
014
Y64
W22
174
H64
064
W22
174
H64
064
W22
174
H64
064
Product
Description
512x 9 FIFO
512x9BFO
512x9FIFO
512x9 BFO
512x9F1FO
512x9 BFO
512x 9 F1FO
512x9 F1FO
512x 9 F1FO
512x9F1FO
512x 9 F1FO
512x9 FIFO
512x 9 FIFO
16K x 4 SRAM w/OE
16Kx4SRAMw/OE
16K x 4 SRAM w/OE
16Kx4SRAMw/OE
16K x 4 SRAM w/OE
16Kx4SRAMw/OE
16Kx4SRAMw/OE
16Kx4SRAMw/OE
16P4ECLPLD
16P4ECLPLD
16P4ECLPLD
16P4ECLPLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
AsVnchronous UV PLD
Not..:
1. Devices listed have been approved by DESC for the SMD
indicated as of the date of publication. Contact your local Cypress
representative, or the Cypress SMD Hotline at 408/943-2716, for
the latest update.
2. Use the SMD part number as the ordering code.
3. Package:
SMD Hotline: 408/943-2716
mildesc - 1/92
12-16
24.3 DIP = 24-pin 0.300" DIP;
24.6 DIP = 24-pin 0.600" DIP;
28 R LCC = 28 terminal rectangular LCC,
S = Square LCe, TLCC =Thin LCC
24 CP = 24-pin ceramic flatpack (Configuration 1);
FP = brazed flatpack;
PGA = Pin Grid Array.
~
~~PRF.SS
~_, SEMlCONDU(''TOR
Military Ordering Information
JAN M38510 Qualifications
Package!31
Cypress[2l
Part Number
Description
1Ype
Product
Description
Qualilication
Status
CY7CI47-35DMB
CY7C147-35KMB
CY2147-55DMB
CY2147-55KMB
CY7C148-35DMB
CY7C148-35KMB
CY2148-55DMB
CY2148-55KMB
18.3 DIP
18CP
18.3 DIP
J8CP
18.3 DIP
18CP
18.3 DIP
18CP
D4
K70
D4
K70
D4
K70
D4
K70
4Kxl SRAM
4Kx 1 SRAM
4KxlSRAM
4Kxl SRAM
IKx4SRAM
lKx4SRAM
IKx4SRAM
IKx4SRAM
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
Qualified
JAN Number
JM
JM
JM
JM
JM
JM
1M
JM
3851O/28901BVA
38510/28901BYA
38510/28903BVA
3851O/28903BYA
38510/28902BVA
38510/28902BYA
3851O/28904BVA
3851O/28904BYA
SMD Ordering Information
5962-XXXXX 01
-
-
LX
-
[
~LEADFINrSH
A = Solder Dip
B = Tin Plate
C = Gold
X = Don't Care (The letter "X" will not be marked on tbe device, but will be
replaced witb the actual lead finish designation.)
PACKAGE TYPE (Not a complete list)
V = 18-pin 0.300 DIP
J
R = 20-pin 0.300 DIP
Q
S = 20-pin Cerpack
K
W = 22-pin 0.400 DIP
2
L = 24-pin 0.300 DIP
3
24-pin 0.600 DIP
4O-pin 0.600 DIP
24-pin Cerpack
W-pin SQ LCC
28-pin SQ LCC
X, Y, Z, U, T, N = Non-dedicated package designations and will vary per drawing.
' - - - - - - DEVICE CLASS DESIGNATOR
No character = Old (Pre March 1990) SMD
M
= New "One Part-One Part Number" System SMO, Class B
' - - - - - - - DEVICE TYPE
' - - - - - - - - - - DRAWING NUMBER
' - - - - - - - - - - - - - DRAWING PREFIX
5962 = Federal Stock Class (FSC) for microcircuits. Pre- J985 drawings do
not have this prefix.
Cypress Military Marking Information
Manufacturer's identification:
Cypress Logo, CYPRESS, CYP, and CY are trademarks of Cypress Semiconductor Corporation.
Manufacturer's designating symbol or CAGE CODE:
Designating symbol = CETK or ETK
CAGE CODE/FSCM Number = 65786
mildesc - 1/92
12-17
•
Military Ordering Information
In general, the codes for all products (except modules) follow the format below.
PAL&PLO
PREFIX DEVICE
'PALC'
PALC
PLOC
CY
CY
SUFFIX
I 16R8 I '-20 DMB '
22V10
-15 WMB
20010
-20 WMB
7C330
-50 DMB
-4 DMB
1OE302
RAM, PROM, FIFO,
PREFIX
PALlO
PAL 24 VARIABLEPRODUcr1ERMS
GENERIC PLO 24
PLO SYNCHRONOUS STATE MACHINE
10KECLPLO
liP. EeL
DEVICE
rg'r~
CY
CY
CY
CY
FAMILY
C245A
7C404
7C901
10E422L
B = BiCMOS
C = CMOS
SUFFIX
-35DMB '
-10DMB
-18WMB
-10DMB
-27DMB
-5 DMB
FAMILY
CMOSSRAM
BiCMOSSRAM
PROM
FIFO
!'l'
10KECLSRAM
PROCESSING
B = ill REL MIL SID 883D FOR MILITARY PRODUcr
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUcr
T = SURFACE·MOUN'IED DEVICES (V & S PACKAGE) TO
BE TAPE AND REELED
R = LEVEL 2 PROCESSING ON 'D\PE AND REEL DEVICES
1EMPERATURE RANGE
M = MILITARY (-55°C TO
+125°C)
PACKAGE
D = CERDIP
F = FLATPAK
G = PIN GRID ARRAY (PGA)
H = WINDOWED LEADED CHIP CARRIER
K = CERPAK (GLASS·SEALED F'LXf PACKAGE)
L = LEADLESS CHIP CARRIER
Q = WINDOWED LEADLESS CHIP CARRIER
R = WINDOWED PGA
T = WINDOWED CERPAK
U = WINDOWED CERAMIC QUAD FLATPACK
W= WINDOWED CERDIP
X = DICE (WAFFLE PACK)
Y = CERAMIC LEADED CHIP CARRIER
SPEED (ns or MHz)
L = LOW-POWER OPTION
A, B, C = REVISION LEVEL
e.g., CY7C128A-35DMB, PALC16R8-20DMB
Cypress FSCM #65786
mildesc - 1/92
12-18
Military Ordering Information
The codes for module products follow the the format below.
PREFIX
DEVICE
SUFFIX
, CYM'
rJ:4201
'HD -25 MB'
PROCESSING
B = MILITARY STANDARD 883
= STANDARD
TEMPERATURE RANGE
M = -SSOC TO 12S0C
SPEED
CONFIGURATION
D = DUAL-IN-LINE
G = PIN GRID ARRAY
TYPE
H= HERMETIC
Cypress FSCM #65786
•
>
a:
~
::i
i
mildesc - 1/92
12-19
INFO
SRAMs
PROMs
PlDs
FIFOs
lOGIC
COMM
RISC
MODULES
ECl
BUS
I'"
III
MILITARY
QUALITY ~~~~~~~~~~~~~§§IIII'II
PACKAGES ~~~~~~~~~~~~I
Section Contents
Design and Programming Tools
Device Number
CY3101
CY3102
CY3200
CY3210
CY3220
CY3300
Page Number
Description
PLDTholKit ......... ... .......... .................. ........... ..... .........
13-1
Wap1 PLD Compiler .........................................................
13-3
PLDS·MAX + PLUS Design System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 5
PLS- EDIF Bidirectional Netlist Interface ....................................... 13-10
MAX + PLUS II Design System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
QuickPro II.................................................................
13-22
II
CY3101
CYPRESS
SEMICONDUCTOR
PLD ToolKit
Features
Description
•
•
•
•
•
•
The Cypress PLD ToolKit is a sophisticated programmable logic design tool that
supports the Cypress family of programmable logic products. The ToolKit includes
the ability to assemble a logic source file,
interactively perform logic simulation on
the result, and write a standard JED EC
output file for programming the PLD. In
addition, JEDEC files may be read, simulated, and reverse assembled, creating
source files that may be modified and reassembled.
The PLD TholKit runs on any standard
IBM PC®, AT®, 386 or compatible personal computer with a CGA, EGA, VGA, or
Hercules display. The ToolKit features
mouse, keyboard, or command line interface, and supports Logitech@j) and Micro-
Logic assembler, Reverse assembler
Concise easy-to-use syntax
JEOEC read/write capability
Integrated waveform logic simulator
Mouse-driven simulation editor
Mouse, keyboard, command line interface
• CGA, EGA, VGA, Hercules support
• Supports all Cypress PLOs
soft® mouse compatibility. Command line
control is provided for assembly from a
source file to JEDEC file or disassembly of
a JEDEC file to a source file.
The language contains syntax that allows
the management of programmable logic
device macrocells in all possible configurations, as well as default conditions that
provide concise source files. In addition,
there are language constructs called connectives that provide expressions for connecting any product term to a macrocell.
The TholKit simulator features waveform
entry, multiple views and mUlti-segment
simulation. The simulator provides the capability to specify initial design conditions,
and "view nodes" may be created and used
to probe internal nodes in the device.
II
IBM and IBM PC, AT are registered trademarks of International Business Machines Corporation.
Logitech is a trademark of Logitech, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
13-1
CY3101
PLD ToolKit Command Menus
Simulation Colors
Command Menu
Assemble
Invokes Assembler
Background
InputThace
Disassemble
Invokes Disassembler
WriteJEDEC
Writes JEDEC Output File
OutputThace
ReadJEDEC
Reads JEDEC File into PLD
TholKit
Name of Pin or Node
Simulate
Invokes Simulator
Allows the selection of colors
for the Simulator Display
Pio or Node Background
Thace Selected
Options
Selects Option Menu
Information
Selects System Information
Menu
Memory
Clear
Resets TholKit
512 kbytes of total memory is required to operate the PLD ToolKit.
Selected Thace Background
Devices Supported
Information
Release Number
Release Date
PALC16R8, PALC16R6, PALC16R4, PALC16L8, PALC22VI0,
PLDC20GlO, PLDC18G8, CY7C330, CY7C331, CY7C332,
CY7C361, CYlOE301, CYl00E301, CYlOE302, CY100E302
Information about the PLD
ToolKit for registration purposes
Free Memory
Ordering Information
Screen Size
CY3101 Cypress PLD ToolKit Levell contains:
lWo 5 14" Floppy Disks
One 3 'hI! Floppy Disk
One Manual
One Registration Card
Number of Colors
Options
Simulation Colors
Selects Simulation Colors Menu
Menu Colors
Selects Menu Color Menu
JEDEC Brief/Annotate
Thggles JEDEC Annotated
or Brief listing
G Fuse (JEDEC Security):
ON/OFF
Toggles Security Fuse
Working Directory Path ( )
Sets Path to Working Directory
Document #: 38-00145
13-2
CY3102
CYPRESS
SEMICONDUCTOR
Features
• supports CY7C36112S-MHz state
machinePLD
• supports creation of sequential, concurrent, and parallel hot-coded state
machines
• Performs state and logic minimization
• Uses industry-standard high-level language
- VHDL (VHSIC Hardware Description Language
• Produces Cypress PLD Tholkit Assemblyoutput
- allows low-level manual optimization
• Includes PLD Tholkit
- AssemblerlDis-assembler
- JEDEC read/write
Warp1@) PLD Compiler
- Integrated Waveform Oriented
simulator
- Mouse-driven simulation editor
• Runs on mM PC-XT®, -AT®,386,
or 486 compatible machines
Description
The Cypress WapI PLD compiler provides high-level language desigu synthesis
support for the Cypress CY7C361
125-MHz state machine PLD. Cypress believes that our software effort is best directed at producing tools that maximize the
value of our innovative PLDs in design environments based on open standards.
WapI is the first phase of a product family
that will support our line of CY7C33x and
CY7C36x devices.
WapI uses a subset of the industry-standard VHDL hardware behavioral description language to describe your PLD design.
The CY7C361 is capable of supporting sequential, concurrent, and parallel hotcoded state machines. Sequential state machines have only one active state at a time .
Concurrent state machines have multiple
independent state machines operating simultaneously on a single device. A parallel
hot-coded state machine can have multiple
states active simultaneously and can be
used in both concurrent and non-concurrent designs. VHDL is an emerging standard language that has the ability to describe sequential as well as concurrent
state machines with or without parallel
hot-coding. Having designs described using VHD L syntax also increases portability
of the circuit to other design environments
that support VHDL. The nature of the
CY7C361 also encouraged the development of algorithms that are targeted to
state minimization. The CY7C361 uses a
state macrocell to uniquely identi1y
II
ruM and ruM PC, AT are registered trademarks of International Business Machines Corporation.
WapI is a trademark of Cypress Semiconductor Corporation.
13-3
.7L~NDUcr)R
Description
CY3102
(continued)
each possible state in the design (hot-coding). The Wa1p1 compiler
reduces the number of states required to synthesize the design,
then performs conventional logic reduction. Wa1p1 is the only software of its kind to provide optimization for both state and logic reduction.
been previously programmed can be facilitated through this JEDEC read and dis-assembly option. More information on PLD
Toolkit's capabilities is available in the CY3101 data sheet.
Wa1p1 is the first element in a chain of tools that results in fully
functional programmed devices (see Figure 1). The Wa1p1 Pill
512 Kbytes of free memory and 1 Mbyte of hard disk space is required for operation at Wa1p1.
Compiler accepts a user-written VHDL description of the design.
When the design is performing as desired, the Toolkit can produce
an industry-standard JEDEC file that is used to program parts with
Cypress's QuickProII@ programmer or third-party programmers
that support the CY7C361.
The Wap1 PLD Compiler includes the Cypress PLD Tholkit. In
addition to providing simulation and assembly of designs for the
CY7C361, the Pill Tholkit can also assemble and simulate other
Cypress PLDs. PLD Tholkit also provides the ability to read JEDEC files created by other software tools for simulation or reverse
assembly to a .CYP file. This allows you to use Tholkit's on-screen
simulator to verify designs that were compiled using third-party
tools. Also, the documentation or alteration of PLDs that have
Memory Requirements
Ordering Information
CY3102 Wa1p1 PLD Compiler includes:
CY3101 PLD Tholkit package
One 5 \4" 1.2M Floppy Disk
One 3 \fz" 1.44M Floppy Disk
One Manual
One Registration Card
Document #: 38-00170
On-Screen
Waveform
Interactive Simulator
VHDL
ASCII Text
Warp1
PLD
Compiler
D
.CYPFile
ASCII Text
PLD
Toolkit
JEDEC
File
ASCII Text
W
D
Third-Party
Device
Programmers
Figure 1_ Chain of1OO18 to a Fully Functional Programmed Device
13-4
QuickProll
Device
Programme
CY3200
CYPRESS
SEMICONDUCTOR
Features
• Unified development system for Multiple Array MatriX (MAX®) EPLDs
• Hierarchical design entry methods for
both graphical and textual designs
- Multiple-level schematics and
bardware language descriptions
- Library of 7400 Series TTL and bus
macrofunctions optimized for MAX
architecture
- Advanced Hardware Description
Language (AHDL) supporting state
machines, Boolean equations, truth
tables, arithmetic, and relational
operations
- Delay prediction for graphic and
text designs
• Logic synthesis and minimization for
quick and efficient processing
• Compiler that compiles a 100% utilized CY7C342 in only 10 minutes
• Automatic error location for AHDL
text files and schematics
• Interactive Simulator with probe assignments for internal nodes
PLDS-MAX + PLUS®
Design System
• Runs on IBM PC/AT®, PS/2® or compatible machines
• Waveform Editor for entering and
editing waveforms and viewing simulation results
Description
The PLDS-MAX+PLUS (Programmahle
Logic Development System) is a unified
CAE system for designing logic with Cypress's CY7C340 family of EPLDs (Figure
1). PLDS-MAX+PLUS includes design
entry, design processing, timing simulation, and device programming support.
PLDS-MAX+PLUS runs on IBM PS/2,
PC-AT, or compatible machines, and provides tools to quickly and efficiently create
and verify complex logic designs.
The MAX + PLUS software compiles designs for MAX EPLDs in minutes. Designs may be entered with a variety of design entry mechanisms. MAX + PLUS supports hierarchical entry of both Graphic
Design Files
(GDFs) with the
MAX+PLUS Graphic Editor, and Text
Design Files (TDFs) with the Advanced
Hardware
Description
Language
(AHDL). The Graphic Editor offers advanced features such as multiple hierarchy
levels, symbol editing, and a library of7400
series devices as well as basic SSI gates.
AHDLdesigns may be mixed into any level of the hierarchy or used on a standalone
basis. AHDL is tailored especially for
EPLD designs and includes support for
complex Boolean and arithmetic functions, relational comparisons, multiple
hierarchy levels, state machines with automatic state variable assignment, truth
tables, and function calls.
In addition to multiple design entrymechanisms, MAX + PLUS includes a sophisticated compiler that uses advanced logic
synthesis and minimization techniques in
conjunction with heuristic fitting rules to
efficiently place designs within MAX
EPLDs. A programming file created by
the compiler is then used by MAX + PLUS
to program MAX devices with the QP2MAX programming hardware.
Simulationsmay be performed with a powerful, event -driven timing simulator. The
MAX + PLUS Simulator interactively displays timing results in the MAX + PLUS
Waveform Editor. Hardcopy table and
waveform output is also available. With
tbe Waveform Editor, input vector waveforms may be entered, modified, grouped,
~
o
o
I-
MAX and MAX +PLUS are registered trademarks of Altera Corporation.
IBM PCIAT and PS/2 are registered trademarks of International Business Machines Corporation.
QP2-MAX and QuickPro II are trademarks of Cypress Semiconductor Corporation.
13-5
fj'l~
i{lQ~
A~
o~
a
Q
f,;l
I-'
W
I
a,
n
Figure 1. MAX +PillS Block Diagram
~
N
=
=
CY3200
and ungrouped. In addition, the Wavefonn Editor compares simulation runs and highlights the differences.
TheintegratedstructureofMAX+PLUSprovidesfeaturessuchas
automatic error location and delay prediction. Ifa design contains
an error in either a schematic or a text file, MAX + PLUS flags the
error and takes the user to the actual location of the error in the
original schematic or text file. In addition, propagation delays of
critical paths maybe determined in both the Graphic and ThxtEditors with the delay predictor. After the source and destination
nodes are tagged, the shortest and longest timing delays are calculated.
MAX + PLUS provides a seamless design framework using a consistentgraphicaluserinterfacethroughout. Thisframeworksimplilies all stages of the design cycle: design enhy, processing, verification, and programming. In addition, MAX + PLUS offers online
help to aid the user.
Design Entry
MAX + PLUS offers both graphic and text design enhy methods.
GDFsare entered with the MAX + PLUS GraphicEditor; Boolean
equations, state machines, and truth tables maybe entered with the
MAX + PLUS Thst Editor using AHDL. The ability to freely mix
graphics and textflles at all levels of the design hierarchy and touse
either a top-down or bottom-up design method makesdesignentl}'
simple and versatile.
Graphic Editor
The Graphic Editorprovides amouse-driven, multi-windowed environment in which commands are entered with pop-up menus or
simple keystrokes. The Hierarchy Display window, shown at the
top, lists all schematics used in a design. The designernavigates the
hierarchy by placing the cursor on the name of the design to be
edited and clicking the left mouse button. The Thtal View window
(next to the Hierarchy window) shows the entire design. Byclicking
on an area in this window, the user is moved to that area of the
schematic. The Error Report window lists all warnings and errors
inthe compiled design; selecting an errorwith the cursor highlights
the problem node and symbol. A design is edited in the main area,
which may be enlarged by closing the auxilia!}' windows.
When entering a design, theusermaychoose from a librBl}' of over
200 7400 series and special-purpose macrofunctions that are all
optimized for MAX architecture. In addition, the designer my
create custom functions that can be used in any MAX + PLUS design.
Th take advantage of the hierarchy features, the user first saves the
entered design so the Graphic Editor can automatically create a
symbol representing the design. This symbol maybe used ina higher-level schematic or in another design. It may also be modified
with the Symbol Editor.
Thg-and-drag editing is used to move individual symbols or entire
areas. Lines stay connected with orthogonal rubberbanding. A design maybeprintedonanEpsonFX-compatibleprinter, orplotted
on an HP- or Houston Instruments-compatible plotter.
Symbol Editor
The MAX + PLUS Symbol Editorenables the designertocreate or
modify a custom symbol representing a GDForTDR Itis aIso possible to modify input and output pin placementofan automatically
generated symbol.
The created symbol represents a lower-level design, described bya
GDF or TDR The lower-level design represented by the symbol
may be displayed with a single command that invokes either the
Graphic Editor for schematics or the Thxt Editor for AHDL designs.
ABDL
The Advanced Hardware Description Language (AHDL) is a
high-level, modular language used to create logic designs for MAX
EPLDs. It is completely integrated into MAX + PLUS, so AHDL
files may be created, edited, compiled, simulated, and programmed from within MAX + PLUS.
AHDLprovides support for state machine, truth tables, and Boolean equations, as well as srithmetic and relational operations.
AHDLishierarchical, which allows frequently used functions such
as TTL and bus macrofunctions to be incorporated in a design.
AHDL supports complex arithmetic and relational opeartions,
such as addition, subtraction, equality, and magnitude comparisons, with the logic functions automatically generated. Standard
Boolean functions, including AND, OR, NAND, NOR, XOR, and
SNOR are also included. Groups are fully supported so operations
may be perfonned on groups as well as on single variables. AHDL
also allows the designer to specify the location of nodes within
MAX EPLDs. Thgether, these features enable complex designs to
be implemented in a concise. high-level description.
Text Editor
The MAX + PLUS Thxt Editor enables the user to view and edit
text files within the MAX + PLUS environment. Any ASCII text
file, including Vector Files, Thble Files, Report Files, and AHDL
Thxt Design Files (TDFs) maybeviewedandeditedwihtouthaving
to exit to DOS.
The Thxt Editor parallels the Graphic Editor's menu structure. It
has a Hierarchy Display and a Thtal View window for moving
through the hierarchy levels and around the design. It includes automatic error location and hierarchy traversal. If an error is found
in a TDF during compilation, the Thxt Editor is automatically invoked andthelineofAHDLcodewherethe error occurred is high·
lighted. In addition, a design may use both text and graphic files. As
the designer traverses the hierarchy, the Thxt Editor is invoked for
text files, and the Graphic Editor is invoked for schematics.
Symbol Libraries
The libra!}' provided with MAX + PLUS contains the most commonly used 7400 series devices such as counters, decoders, encoders, shift registers, flip-flops, latches, and multipliers, aswe\l as special bus macrofunctions, all ofwhich increase design productivity.
Because of the flexible architecture of MAX EPLDs (thatinc\udes
asynchronous preset and clear), true TIL device emulation is
achieved. Cypress also provides special·purpose bus macrofunctions for designs that use buses. All macrofunctions have been optimized to maximize speed and utilization. Refer to the
MAX+PLUS TTL MacroFunctions manual for more information
on TTL macrofunctions.
Design Processing
The MAX + PLUS CompilerprocessesMAXdesigns.The Compiler offers options that speed the processing and analysis of a design.
The user can set the degree of detail of the Report File and the
maximum number of errors generated. In addition, the user may
select whether or not to extract a netlist file for simulation.
The Compilercompiles adesign in increments. If a design has been
previously processed, only the portion of the design that has been
changed is re-extracted, which decreases the compilation time.
This "Make" facility is an automatic feature of the Compile command.
13-7
CY3200
The first module of the Compiler, the Compiler NetJist Extractor,
extracts the netIist that is used to define the design from each file.
At this time, design rules are checked for any errors. If errors. are
found, the Graphic Editor is invoked when the error appears in a
GDF, and the Text Editor is invoked when the error appears in a
TDETheErrorReportwindowinbotheditorshighlightsthelocationofthe error. Asuccessfullyextracted design is built into a database to be used by the LogicSynthesizer.
The Logic Synthesizer module translates and optimizes the userdefined logic for the MAX architecture. Any unused logic within
the design is automatically removed. The Logic Synthesizer uses
expert system synthesis rules to factor and map logic within the
multilevel MAX architecture. It then chooses the approach that
ensures the most efficient use of silicon resources.
The next module, the Fitter, uses heuristic rules to optimally place
the synthesized design into the chosen MAX EPlD. For MAX devices that have a ProgramntableInterconnectArray(PIA), the Fitter also routes the signals across this interconnect structure, so the
designerdoesn't have to worry about placement and routingissues.
A Report File (.RPT) is issued by the Fitter, which shows design
implementationas well as any unused resources in the EPLD. The
designer can then determine how much additional logic may be
placed in the EPlD.
A Simulator Netlist File (.SNP) may be extracted from the compiled design by the Simulator Nellist Extractor if simulation is desired. Finally, the Assembler creates a Programmer Object File
(.POF) from the compiled design. This file is used with the
QP2- MAX programming hardware to program the desired part.
Delay Prediction and Probes
MAX + PLUS includes powerful analysis tools to verify and analyze the completed design. Delay analysis with the delay predictor
may be performed interactively in the Graphic Editor, or in the
Simulator. The Simulator is interactive and event-driven, yielding
true timing and functional charactersitics of the compiled design.
The delay predictor provides instant feedback about the timing of
the processed design. After selecting the start point and end point
of a path, the designer may determine the shortest and longest
propagationdelays of speed-critical paths.
Also, a designer may use probes to mark internal nodes in a design.
The designer may enter a probe by placing the cursor on any node
in a graphic design, selecting the SPE (Symbol:Probe:Enter)command, and then entering a unique name to define the probe. This
name may then be used in the Graphic Editor, Simulator, and
WaveformEditor to reference that node, so thatJengthy hierarchical path names are avoided.
Simulator
Input stimuli can be defined with a straightforward vector input
language, or waveforms can be directly drawn using the Waveform
Editor. Outputs may also be viewed in the Waveform Editor, or
hardcopy table and waveform files may be printed.
The Simulator used the Simulator Netlist File (SNP) extracted
from the compiled design to perform timing simulation with
lI10-nanosecond resolution. A Command File may be used for
batch operation, or commands maybe entered interactively. Simulatorcommands allow the user to halt the simulation dependent on
user-defined conditions, to force and group nodes, and perform
ACdetection.
If flip-flop set-up or hold times have been violated, the Simulator
warns the user. In addition, the minimum pulse width and period
of oscillation may be defined. If a pulse is shorter than the mini-
mum pulse width specified, or if a node oscillates for longer than
the specified time, the Simulator issues a warning.
Waveform Editor
The MAX + PWS Waveform Editor provides a mouse-driven environmentin which timing waveforms may be viewed and edited. It
functions as a logic analyzer, enabling the user to observe simulationresults. Simulated waveforms maybe viewed and manipulated
at multiple zoom levels. Nodes may be added, deleted, and combinedinto buses, which may contain up to 32 signals represented in
binary, octal, decimal, or hexadecimal format. Logical opeartors
may also be performed on pairs of waveforms, so that waveforms
may be inverted, ORed, ANDed, or XORed together.
The Waveform Editor includes sophisticated editing features to
define and modify input vectors. Inputwaveforms are created with
the mouse and familiar text editing commands. Waveforms may be
copied, patterns may be repeated, and blocks may be moved and
copied. For example, all or part of a waveform may be contracted
to simulate the increase in clock frequency.
The WaveformEditor also compares and highlights the difference
between two different simulations. A user may simulate a design,
observe and edit the results, and then resimulate the design, and
the Waveform Editor will show the results superimposed upon
each other to highlight the differences.
MAX + PLUS Timing Analyzer (MTA)
The MAX + PLUS Timing Analyzer (MTA) provides user-configurable reports that assist the designer in analyzing critical delay
paths, set-up and hold timing, and overall system performance of
any MAX EPLD design. Critical paths identified by these reports
may be desplayed and highlighted.
Tuningdelays between multiple source and destination nodes may
be calculated, thus creating a connection matrix giving the shortest
and longest delay paths between all source and destination nodes
specified. Or, the designer may specify that the detailed paths and
delays between specific sources and destinations be shown.
The set-up!hold option provides set-up and hold requirements at
the device pins for all pins that feed the D, CLK, or ENABLE inputs of flip-flops and latches. Critical source nodes may be specified individually, or set-up and hold at all pins may be calculated.
This information is then displayed in a table, one set of set-up and
hold times per flip-flop/latch.
The MTA also allows the user to print a complete list of all accessible nodes in a design,; i.e., all nodes that may be displayed during
simulation or delay prediction.
All MTAoptions may be listed in an MTA command file. With this
file, the user may specify all information needed to configure the
output.
SNF2GDF Converter
SNF2GDF converts the SNP into logic schematics represented
with basic gates and flip-flop elements. It uses the SNF's delay and
connection information and creates a series of schematics fully annotated with propagation delay and set-up and hold information at
each logic gate. certain speed paths of a design may be specified
for conversion, so the user may graphically analyze only the paths
consideredcritical.
If State Machine or Boolean Equation design entry is used,
SNF2GDFshows how the high-level description has been synthesized and placed into the MAXarchitecture.
13-8
4~
CY3200
~=CYPRESS
~, SEMlCONDUClOR
Device Programming
Recommended System Configuration
IBM PS/2 model 70 or higher, or Compaq 386 20-Mhz
computer.
PLDS-MAX contains the basic hardware and software for programmingthe MAX EPLD family. Adpaters are included for programming the CY7C344 (DIP and PLCe) and CY7C342 (PLCe)
devices. Additional adapters supporting other MAX devices may
be purchased separately. MAX + PLUS programming software
drives the QP2- MAX programming hardware. The designer can
use MAX +PLUS to program and verify MAX EPLDs. If the security bit of the device is not set to ON, the designer may also read the
contents of a MAX device and use this information to program additionaldevices.
PC-DOS version 3.3.
640 kbytes of RAM plus 1 MB of expanded memory with LIM
3.2-compatibleEMSdriver.
VGAgraphics display.
20-MB hard disk drive.
System Requirements
1.2-MBSV.· or 1.44-MB 3Yz' floppy disk drive.
Minimum System Configuration
IBM PS/2 model SO or higher, PC/AT or compatible
computer.
3-button serial port mouse.
Ordering Information
CY3200
PC-DOS version3.l or higher.
640 kbytes RAM.
EGA, VGA or Hercules monochrome display.
PLDS-MAX + PLUS System including:
CY320l
MAX +PLUS software, manuals
and key.
CY3202
QP2- MAXPLD programmer with
CY3342 & CY3344 adapters.
20-MB hard disk drive.
1.2-MB sv." or 1.44-MB 3Y2' floppy disk drive.
Device Adapters
3-button serial port mouse.
Document #: 38-00132-A
CY3342
Adapter for CY7C342 in PLCC packages.
CY3344
Adapter for CY7C344 in DIP and PLCC
packages.
CY3342R
Adapter for CY7C342 in PGApackages.
CY33435
Adapter for CY7C343 in DIP
and PLCC packages.
•
13-9
CY3210
PRELIMINARY
CYPRESS
PLS-EDIF
Bidirectional N etlist Interface
SEMICONDUCTOR
Features
Description
• Bidirectional netlist interface between
MAX + PWS® and other lIllIjor
CAE software packages
• Supports the industry-standard Electronic Design Interchange Format
(EDIF) version 200.
• MAX EPID designs entered on workstation CAE tools can be downloaded to
MAX+PWS for compilation; compile
designs can then be returned to the
workstation for device- or system-level
simulation.
• EDIF netlist reader imports EDIF netlists into MAX + PWS. Library Mapping Files (LMFs) convert CAE library functions to MAX+ PWS library functions.
• LMFs allow conversion of common
Dazix, Mentor Graphics, Valid Logic,
and Viewlogic functions to
MAX+ PWS functions.
• EDIF netlist writer produces post-synthesis logic and delay information
used during device- or board-level
simulation with popular CAE tools.
• RunsonffiMPS/2®,PC-AT®,or
compatible machines.
The PLS-EDIF tool kit is a bidirectional
EDIF netlist interface between workstation-basedCAEsoftware packages and the
PLDS-MAX+PillS Design System (Figure 1).
PLS-EDIFallowsthedesignertoenterand
verify logic designs for MAX EPLDs using
third-party CAE tools. The EDIF 200 netlist exchange format is the two-way bridge
between MAX + PillS and third-party
schematic capture and simulation tools.
PLS-EDIFruns on an IBM PSI2, PC-AT,
or compatible machines.
Any CAE software package that produces
EDIF 200 netlists can interface to
MAX + PLUS with PLS-EDIE EDIF netlists are imported into MAX + PLUS using
the EDIF Design File-to-Compiler Netlist
File(EDF2CNF) Converter. Library Mapping Files (LMFs) are used with
EDF2CNFto map third-party CAE library
functions to the MAX + PLUSlibraryfunctions. LMFs are provided for Dazix, Mentor Graphics, Valid Logic, and Viewlogic
software, but designers may create LMFs
to map any CAE software library.
After a design is imported into
MAX+ PLUS, it is compiled with the sophisticated MAX + PLUS Compiler, which
CAE Workstation!
PC Platform
uses advanced logic synthesis and minimization techniques together with heuristic
fitting rules to optimize the design for
MAX BPLD architecture. A Programmer
Object File created by the MAX + PillS
Compiler is then used together with standard Cypress or third-party programming
hardware to program MAX devices.
EDIF netlists can be exported from
MAX + PillS using the Simulator Netlist
File-to-EDIF Design File (SNF2EDF)
Converter. This converter generates an
EDIF output file from a compiled
MAX + PillS design. The EDIF file contains the post-synthesis information used
by CAE simulators to perform device- or
board-Ievelsimulation.
PLS-EDIFprovides an open environment
that allows popular CAE tools to be used
to create and simulate MAX EPLD designs. The designer may use a preferred
workstation schematic capture package to
enter logic designs, and then quickly convert and compile them with EDF2CNF
and MAX + PLUS. Likewise, designs compiled in MAX + PLUS and converted with
SNF2EDF may be transferred to a workstationforsimulation. ThePLS-EDIFnetlist reader and writer together allow MAX
EPLD designs to be entered and simulated
on any workstation platform.
•
•
•
•
Logic Entry
Device Simulation
PC Platform
•
Board Simulation
,------------------------------,
i - - - .... -- .......................... - ..
•
•
Logic Entry .
Logic SynthesIs
Device Simulation
Programming
EDIF200
Exchange Format
~
~
Gl
,
,
.... ________ .. ____ ... _______ l
1_
..
__
..
__
...........................
Shaded items are provided with PLS-EDIR
Figure 1. PLS-EDIFWorkstation Interface
MAX+PWS is a registered trademark of A1tera Corporation.
IBM PS/2 and PC-AT are registered trademarks ofIntemational Business Machines Corporation.
13-10
____
..
__
....
1
CY3210
EDFlCNF Converter
The EDF2CNF Converter generates one or more MAX +PLUS
Compiler Netlist Files (CNFs) from an EDIF file. For each CNF,
a Hierarchy Interconnect File (IDF) and a Graphic Design File
(GDF) are also generated (see Figure 2). The CNF contains the
connectivity data for a design file, while the IDF defines the hierarchical connections between design files. The GDF is a symbol
that represents the actual design data in the CNR This symbol
may be entered in the MAX+PLUS Graphic Editor and integrated into a logic schematic.
EDF2CNFcanconvertanyEDIF200netiistwiththefollowingparameters:
EDIFlevelO
keyword level 0
view type NETLIST
cell type GENERIC
Library Mapping Files (LMFs) are used with EDF2CNF to convert workstation CAE functions into equivalent MAX + PLUS
functions. This direct substitution is beneficial because
MAX + PLUS functions are optimized for both logic utilization
and performance in MAX EPLD designs.
Workstation
EDIFWriter
One or more sets
of CNF, HIF, and GDF
are generated.
One or more
Ubrary Mapping Filas
may be used as inputs.
Figure 2. EDF2CNF Block Diagram
!)
o
o
I-
13-11
.il~u~
CY3210
Workstation Information
EDF2CNF has been specifically tested for use with the Dazix,
MentorGraphics, Valid Logic, and Viewlogic CAE software packages. In addition, LMFs for these products are provided with the
PLS-EDIFtoolkit.
Dam
Th design logic and create an EDIF file with Dazix software, the
followingapplications are required:
ACE (Dazixgraphicseditor)
DANCE and DRINK (Dazixcompiler)
ENW verison 1.0 (Dazix EDIF netlistwriter)
Table 1 lists the Dazix basic functions that are mapped to
MAX + PLUS functions.
Mentor Graphics
Th design 10gic and create an EDIF file using Mentor Graphics
software, the following applications are required:
NETED (Mentor Graphics graphics editor)
EXPAND (Mentor Graphics compiler)
EDIFNETversion 7.0 (Mentor Graphics EDIFnetIistwriter)
Table 2 lists the Mentor Graphics basic functions that are mapped
to MAX + PWSfunctions.
Thble 1. Dazix Library Mapping File
MAX+PWS Function
Dazix Function
Thble 2. Mentor Graphics Libary Mapping File
Mentor graphics
Function
MAX + PLUS Function
AND#
AND#
BUF
SCLK
DELAY
MCELL
DFF
DFF2
R#AND
AND#
(# = 2,3,4,5,6,7,8,9)
R#ANDD
BNOR#
(# = 2,3,4,5,6,7,8,9)
INY
NOT
JKFF2
(# = 2,3,4,5,6)
R#NAND
NAND#
(# = 2,3,4,6,7,8,9,13)
JKFF
R#NANDD
BOR#
(# = 2,3,4,5,7,8,9,13)
LATCH
MLATCH
R#NOR
NOR#
(#=2,3,4,5)
NAND#
NAND#
(# = 2,3,4,5,6,9)
R#NORD
BAND#
(#=2,3)
NOR#
NOR#
(# = 2,3, 4, 6, 8,16)
(# = 2,3,4,5)
OR#
OR2#
(# = 2,3,4,6,8)
(# = 2,3,4,5)
XNOR2
XNOR
XOR2
XOR
R#OR
OR#
R#ORD
BNAND#
RlBUF
MCELL
RIINV
NOT
RIINVD
EXP
RIOCBUF
SCLK
RIOTBUF
TRIBUF
RlTINY
TRINOT
R2XNOR
XNOR
R2XOR
XOR
R3UAOI
1A2NOR2
R4AOI
2A2NOR2
R40AI
20R2NA2
RSAOI
4A2NOR4
R13TNAND
TNAND13
R13TNANDD
TBOR13
RDFLOP
DFF2
RDLATCH
RDLATCH
RJKFWP
JKFF2
13-12
&-----,..
ilCYPRFSS
F SEMlCONDUcroR
2
CY3210
VaJidLogic
Viewlogic
To design logic and create an EDIF file using Valid Logicsoftware,
the following applications are required:
ValidGED (Valid Logic graphics editor)
VaIidCompiler
GEDIFNET (Valid Logic EDIF netlistwriter)
Table 3 lists the Valid Logic basic functions that are mapped to
MAX + PLUS functions.
To design logic and create an EDIF file using Viewlogicsoftware,
the following applications are required:
Workview (Viewlogicgraphicseditor)
EDIFNETZ version 3.02 (Viewlogic EDIF netlistwriter)
Table 4 lists the Viewlogic basic functions that are mapped to
MAX + PLUS functions.
Thble 3. Mentor Grapbics libary Mapping File
Valid Logic Function
MAX+PWS Function
INV
EXP
LSOO
NAND2
LS02
NOR2
LS04
NOT
LS08
ANDZ
LSlO
NAND3
LSll
AND3
LS20
NAND4
LS21
AND4
LS27
NOR3
LS28
NOR2
LS30
NAND8
LS32
OR2
LS37
NAND2
LS40
NAND4
LS74
DFF2
LS86
XOR
LS126
TRI
LS280
DFF2
LS386
XOR
Thble 4. Viewlogic libary Mapping File
Dazix Function
13-13
MAX+PWS Function
AND#
AND#
ANDNOR22
2A2NOR2
(# = 2, 3, 4, 8)
BUF
SOFT
DAND#
DAND#
DELAY
MCELL
DOR#
DOR#
(# = 2, 3, 4, 8)
DXOR#
DXOR#
(#=2,3,4,8)
JKFFRE
JKFFRE
(#=2,3,4,8)
MUX41
MUX41
NAND#
NAND#
(#=2,3,4,8)
NOR#
NOR#
(# = 2,3,4,8)
NOT
NOT
OR#
OR#
(# = 2,3,4,8)
TRIAND#
TAND#
(# = 2, 3, 4, 8)
TRIBUF
TRIBUF
TRINAND#
TNAND#
(#=2,3,4,8)
TRINOR#
TNOR#
(#=2,3,4,8)
TRINOT
TRINOT
TRIOR#
TOR#
UBDEC38
DEC38
UDFDL
UDFDL
UJKFF
UJKFF
XNOR2
XNOR
XNOR#
XNOR#
XOR2
XOR
XOR#
XOR#
(# = 2, 3, 4, 8)
(#=3,4,8)
II
(#=3,4,8)
o
!J
o
t-
CY3210
LMF Support for TTL Macrofunctions
In addition to the basic gates, LMFs map various Dazix, Mentor
Graphics, Valid Logic, and ViewlogicTILmacrofunctionstotbeir
MAX +PLUS equivalents, as shown in Table 5.
'Thble 5. TIL Function Mappings in LMFs
Dazix
MAX+PWS
7442
LS42
Mentor Graphics
Viewlogic
Valid Logic
74LS42
LS42
74LS42
DFF2
LS74
74LS74A
LS74
74LS74A
7483
LS83
74LS83A
LS83
74LS83A
7485
LS85
74LS85
LS85
74LS85
7491
LS91
74LS91
LS91
74LS91
7493
LS93
74LS93
LS93
74LS93
74138
LS138
74LS138
LS138
74LS138
74139
LS139
74LS139A
LS139
74LS139
74LS151
LS151
74139M
74151
LS151
74153
74LS151
74LS153
74LS153
74153M
LS153
74157
LS157
74LS157
LS153
74160
LS160
74LS160A
LS160
74LS160A
74161
LS161
74LS161A
LS161
74LS161A
74162
LS162
74LS162A
LS162
74LS162A
74163
LS163
74LS163A
LS163
74LS163A
74164
LS164
74LS164
LS164
74LS164
74165
LS165
74LS165
LS165
74LS165
74174
LS174
74LS174
74LS157
74157M
LS157
74174M
74LS174
LS174
74181
LS181
74LS181
LS181
74LS181
74190
LS190
74LS190
LS190
74LS190
74191
LS191
74LS191
LS191
74LS191
74194
LS194
74LS194A
LS194A
74LS194A
74273
LS273
74LS273
74174M
74279MD
74LS273
LS273
LS279
74LS279
LS279
74LS279
74280
LS280
74LS280
LS280
74LS280
74373
LS373
74LS373
74279M
74373M
74374
LS374
74LS374
74374M
74393M
74LS373
LS373
74LS374
LS374
LS393
74LS393
13-14
LS393
74LS393
~
-=---------
·rlPRFSS
-=J!!f!!!!!!!l!F
CY3210
SEMlCONDUC'TQR
Custom Library Mapping Files
Designers can map their commonly used workstation functions to
MAX +PLUS equivalents by modifying an LMF or creating a new
one. If no equivalent function currently exists in MAX + PLUS, the
user can create the function with the MAX + PLUS Graphic Editor
or Thxt Editor before mapping the function in an LMF. Figure 3
shows an example of this process.
SNF2EDF Converter
The SNF2EDF Converter creates an industry-standard level 0
EDIF file from a MAX + PLUS Simulator Netlist File (SNF). The
SNF, which is optionally generated during compilation of a MAX
EPLD design, contains all post-synthesis functional and delay in-
formationfor the completed design. This design-specific information is also contained in the EDIF output file after conversion so
that it may be integrated into a workstation environment for simulation. An optional command file enables the user to customize the
output EDIF file for various workstation environments byrenaming certain constructs or by changing the EDIF level or keyword
level (see Figure 4).
The EDIF output file may have one of two formats. The first format expresses all delays with special EDIF property constructs.
The second expresses combinatorial delays with portdelay constructs and registered delays as pathdelay constructs-a format
that is especially useful for behavioral simulators. Both formats are
shown in Figure 5.
Step 1: Select a workstation function for mapping
A05
A
B
z
C
Step 2: Design an equivalent circuit with the MAX +PillS GraphicEditor
CYPRESS_A05
,
, A_IN
INPUT
•_____________ ~~ __
'
r--------·
, AND2
.r~_+--L_~r-T--,
,
I ...
,
, BJN
1-
INPUT
'
Vee
.................................
.
~
_
..
_____
'
J
AND2- ......... :
: NOFt2 ........ :~ ................................... .. _.
r-.--..__)---;--~==~,=~
I _______
INPUT
,
..
J
• ________
'
Vee
......................................
Step 2: Map the workstation function to the MAX + PLUS function in an LMF
LIBRARY new_lib
%User Library Mapping File%
BEGIN
FUNCTION MAX_ADS (A_IN, B_IN, C_IN)
RETURNS (Z_OUT)
FUNCTION "ADS" ("A", "B", "C")
RETURNS ("Z")
END
Figure 3. Creating a Library Mapping File
13-15
,_~~T~~~
1
Z~~~T___ ;
_____
CY3210
Workstation
EDIFReader
Figure 4. SNFlEDF Block Diagram
Format 1: Delays expressed with property constructs
FOI1llllt 2: Delays expressed with portdelay and pathdelay constructs
(instance xor2_5
(viewRef view1
(cellRef XOR2
(property TPD(integer 20) (unit TIME)))
(instance xor2_5
(viewRef view1
(cellRef XOR2
(port Instance &1
(portDelay
(derivation CALCULATED
(de1ay(e 20 - 10)))))
Figure S. EDIF File Formats
System Requirements
Package Contents
• IBM PC-AT or compatible computers; IBM PS/2 modesl50,
60, 70, or 80
• MS- DOS version 3.1 or later version
• 640 Kbytes of RAM
• 1 Mbyte of expanded memory compatible with version 3.2 or a
later version of the Lotus/lnteVMicrosoftExpandedMemory
Specification
• EGA, VGA, or Hercules Monochrome display
• 20-Mbyte hard disk drive
• 1.2-Mbyte 5W' or 1.44-Mbyte 3W' floppy disk drive
• MAX +PLUS version 2.01 or a later version
• Workstation-PC network hardware and software with the ability to transfer ASCII files
• Fioppydiskettes containing aU PLS-EDIFprograms and files
for both PC-AT and PS/2 platforms
- EDF2CNFConverter
- SNF2EDFConverter
- Library Mapping Files for Dazix, Mentor Graphics, Valid
Logic, and Viewlogic
- MAX + PLUS macrofunctions for Dazix, Mentor Graphics,
Valid Logic, and Viewlogiclibraries
- Examplefiles
• Documentation
Document #: 38-00144
13-16
CY3220
CYPRESS
SEMICONDUCTOR
Features
• Unified development system for Multiple Array MatriX (MAX®) CY7C340
EPLDs plus compiler support for all
Altera Classic, Max 5000, Max 7000,
and STG EPLDs
• Microsoft Windows version 3.0 to provide graphical user interface,
multi-tasking abilities, efficient
memory management, and extensive
printer and plotter support
• Hierarchical design entry methods for
graphical, textual, and waveform designs
- Graphic Editor for schematic
designs
- Thxt Editor for Thxt Design Files
(TDFs) in the Advanced Hardware
Description Langnage (AHDL) will
support state machines, Boolean
equations, truth tables, arithmetic,
and relational operations
- Waveform Editor for waveform
entry to define logic and view
simulation results
• Logic synthesis and minimization for
quick and efficient processing
• Automatic error location for AHDL
text files and schematics
• Interactive Simulator with probe assignments for internal nodes
MAX+PLUS® II
Design System
• Multichip partitioning to divide large
designs into multiple EPLDs
• Library of 7400 series TTL and bus
macrofunctions optimized for MAX
architecture
• Bidirectional EDIF 2 0 0 netlist interface compatible with a variety of CAE
schematic capture and simulation
tools
• RunsonIBMPC/AT®,PS/2®orcompatible machines
Description
The MAX + PLUS II programmable logic
development system is a unified CAE system for designing logic with Cypress's
CY7C340 family of EPLDs (Figure 1).
MAX + PLUS I I includes design entry, design processing, timing simulation, and device programming support. MAX + PLUS
II ronson IBM PS/2, PC-AT, or compatible
machines, and provides tools to quickly
and efficiently create and verify complex
logicdesigns.
The MAX + PWS II software compiles designs for MAX EPLDs in minutes. Designs may be entered with a variety of design entry mechanisms. MAX + PLUS II
supports hierarchical entry of Graphic Design Files (GDFs) with the MAX+PLUS
II Graphic Editor, Text Design Files
(TDFs) with the Advanced Hardware
Description Language (AHDL), and waveforms with the Waveform Editor. The
Graphic Editor offers advanced features
such as multiple hierarchy levels, symbol
editing, and a library of7400 series devices
as well as basic SSI gates. AHDL designs
may he mixed into any level of the hierarchy or used on a standalone basis. AHDL
is tailored especially for EPLD designs and
includes support for complex Boolean and
arithmetic functions, relational comparisons, multiple hierarchy levels, state machines with automatic state variable assignment, truth tables, and function calls.
MAX + PLUS II includes a sophisticated
compiler that uses advanced logic synthesis and minimization techniques in conjunction with heuristic fitting rules to efficientlyplace designs within MAX EPLDs.
A programming file created by the compiler is then used by MAX + PLUS II to program MAX devices.
MAX + PLUS II features multichip partitioning that automatically splits large designs into multiple EPLDs, allowing the
user to create large system-level designs.
The partitioner lets the user specify speedcritical path for optimum EPLD selection
and design placement.
Simulationsmay be performed with a powerful, event-driven timing simulator. The
MAX + PLUS II Simulator interactively
II
rn
...J
o
o
I-
MAX and MAX +PLUS II are registered trademarks of Altera Corporation.
IBM PC/AT and PS/2 are registered trademarks of International Bnsiness Machines Corporation.
QP2-MAX and QuickPro II are trademarks of Cypress Semiconductor Corporation.
13-17
~
~~
~12
2
@
:-'
W
I
>-'
00
n
Figure 1. MAX +PillS II Block Diagram
~
N
N
=
.~~
~.
CY3220
SEMlCOIDUCTOR
displays timing results in the MAX+PLUS II Waveform Editor.
Hardcopy table and waveform output is also available. With the
WaveformEditor, input vector waveforms may be entered, modified, grouped, and ungrouped, and simulation errors may be
viewed. In addition, the Waveform Editor compares simulation
runs and highlights the differences.
The integrated structure of MAX + PillS II provides features such
as automatic error location and delay prediction. If a design contains an error in either a schematic or a text file, MAX + PillS II
flags the error and takes the user to the actual location of the error
in the original schematic or text file. The designer uses the Clipboard to quickly copy design information from one editor to another. In addition, propagation delays of critical paths may be determined in both the Graphic and Text Editors with the delay
predictor. After the source and destination nodes are tagged, the
shortest and longest timing delays are calculated.
MAX + PLUS II provides a seamless design framework using a
consistent graphical user interface throughout. This framework
simplifies all stages of the design cycle: design entry, processing,
verification,and programming. In addition, MAX + PillS II offers
extensive, context-sensitive online help to aid the user.
Design Entry
MAX + PillS II supports three hierarchical design entry mechanisms: (1) the Graphic Editor is used to enter schematic designs;
(2) the Text Editor is used to enter Thxt Design Files (TDFs) in the
AdvancedHardware Description Language (AHDL); and (3) the
WaveformEditoris used to enter waveforms to define logic. These
design entry methods can be freely mixed within a single project,
allowingthe designer to specify each logic block in the most appropriate format. In addition, EDIF 2 0 0 netlists with popular CAE
schematic tools such as ORCAD, Viewlogic, FutureNet, Mentor
Graphics or Valid Logic are easily imported into MAX + PLUS II.
Graphic Editor
The Graphic Editor provides a mouse-driven, multi-windowed environmentin which commands are entered with pop-up menus or
simplekeystrokes. The Hierarchy Displaywindow listsallschematics used in a design. The designer navigates the hierarchy by placing the cursor on the name of the design to be edited and clicking
the left mouse button. The Thtal Viewwindowshows the entire design. The Error Report window lists all warnings and errors in the
compiled design; selecting an error with the cursor highlights the
problem node and symbol. A design is edited in the main area,
which may be enlarged by closing the auxiliary windows.
Whenentering a design, the user may choose from a library of over
300 7400 series and special-purpose macrofunctions that are all
optimized for MAX architecture. In addition, the designer may
create custom functions that can be used in any MAX + PLUS II
design.
Th take advantage of the hierarchy features, the user first saves the
entered design so the Graphic Editor can automatically create a
symbol representing the design. This symbol may be used in a higher-Ievel schematic or in another design. It may also be modified
with the Symbol Editor.
The Graphics Editor offers many advanced schematic entry and
debugging features. For example, probes can be entered into the
schematic so a specific net (e.g., flip-flops, logic outputs) can be
easily viewed during simulation; critical paths can be specified in
the schematic; and objects can be quickly moved with tag-and-drag
editing. Lines stay connected with orthogonal rubberbanding. Designers can also group nodes into buses, quickly locate source and
destination of nets, and use the search-and-replace to make
changes to the net name.Adesignmay be printed on an Epson FXcompatible printer, or plotted on an HP- or Houston Instruments-compatibleplotter.
Symbol Editor
The MAX + PLUS II Symbol Editor enables the designer to create
or modify a custom symbol representing a GDF or IDE It is also
possible to modify input and output pin placement of an automatically generated symbol.
The created symbol represents a lower-level design, described by a
GDF or TDE The lower-level design represented by the symbol
may be displayed with a single command that invokes either the
Graphic Editor for schematics or the Text Editor for AHDL designs.
AHDL
The Advanced Hardware Description Langnage (AHDL) is a
high-Ievel,modular language used to create logic designs for MAX
EPLDs. It is completely integrated into MAX + PillS II, so
AHDLfIles may be created, edited, compiled, simulated, and programmed from within MAX + PLUS II.
AHDL provides support for state machine, truth tables, and Boolean equations, as well as arithmetic and relational operations.
AHDLishierarchical, which allows frequently used functions such
as TTL and bus macrofunctions to be incorporated in a design.
AHDL supports complex arithmetic and relational operations,
such as addition, subtraction, equality, and magnitude comparisons, with the logic functions automatically generated. Standard
Booleanfunctions, including AND, OR, NAND, NOR, XOR, and
XNOR are also included. Groupsarefullysupportedsooperations
maybe performed on groups as well as on single variables. AHDL
also allows the designer to specify the location of nodes within
MAX EPLDs. Thgether, these features enable complex designs to
be implemented in a concise, high-level description.
Text Editor
The MAX + PLUS II Thxt Editor enables the user to view and edit
text files within the MAX + PLUS II environment. Any ASCII text
file, including Vector Files, Thble Files, Report Files, and AHDL
ThxtDesignFiles(TDFs)maybeviewedandeditedwithouthaving
to exit to DOS.
The Text Editor parallels the Graphic Editor's menu structure. It
has a Hierarchy Display and a Thtal View window for moving
through the hierarchy levels and around the design. It includes automatic error location, hierarchy traversal, global search-and-replace, and multiple fonts. If an error is found in a TDF durin~ compilation, the Text Editor is automatically invoked and the Ime of
AHDLcodewhere the error occurred is highlighted. In addition, a
design may use both text and graphic files. As the designer traverses the hierarchy, the Thxt Editor is invoked for text files, and
the Graphic Editor is invoked for schematics.
Waveform Editor
The MAX + PLUS II Waveform Editor provides a mouse-driven
environment in which waveform algorithms automatically generate logic from user-defined input and output waveforms. It also
functions as a logic analyzer, enabling the user to observe simulation results.
Simulated waveforms may be viewed and manipulated at multiple
zoom levels. Nodes may be added, deleted, and combined into
13-19
CY3220
buses,whichmaycontain upt032signalsrepresentedin binary,octal, decirna1, or hexadecin\a1 format. Logical operators may also be
performed on pairs of waveforms, so that waveforms may be inverted, ORed, ANDed, or XORed together.
The Waveform Editor includes sophisticated editing features to
define and modify input vectors. Input waveforms are created with
the mouse andfamiliartexteditingcommands. Waveforms maybe
copied, patterns may be repeated, and blocks may be moved and
copied. For example, all or part of a waveform may be contracted
to simulate the increase in clock frequency.
The WaveformEditor also compares and highlights the difference
between two different simulations. A user may simulate a design,
observe and edit the results, and then resimulate the design, and
the Waveform Editor will show the results superimposed upon
each other to highlight the differences.
Symbol Libraries
The library provided with MAX + PLUS II contains the most commonly used 7400 series devices such as counters, decoders, encoders,shift registers, flip-flops, latches, and multipliers, as well as special bus macrofunctions, all of which increase design productivity.
Because of the flexible architecture of MAX EPLDs (that includes
asynchronous preset and clear), true TTL device emulation is
achieved. Cypress also provides special-purpose bus macrofunctionsfordesignsthatusebuses.Allmacrofunctionshavebeenoptimized to maximize speed and utilization.
EDIF Support
MAX +PillS II software supports bidirectional EDIF 2 0 0 netlists, providing a convenient way to import popular CAEschematic
capture and simulation tools. The Ubrary Mapping Files (LMFs)
of MAX +PLUS II converts EDIF 2 0 0 netlists into equivalent
primativesand macrofunctions. Users can create their own LMFs
to map any CAE software library. MAX +PLUS II then automatically generates a symbol from a translated EDIF file, so that the
file can be directly incorporated into a MAX + PillS II schematic
or AHDL design. EDIF netlists can also be exported to the popularsimulation tool ofthe user'schoice. The netlistcontains all postsynthesis function and delay information forthe completed design.
Design Processing
The MAX +PLUS II CompilerprocessesMAXdesigns. The Compileroffers options that speed the processing and analysis of a design. The user can set the degree of detail of the Report File and
the maximum number of errors generated. In addition, the user
may specify for which MAX EPLD the compiler should target the
design and select whether or not to extract a netlist file for simulation.
The Compiler compiles a design in increments. If a design has been
previouslyprocessed, only the portion of the design that has been
changed is re-extracted, which decreases the compilation time.
This "Make" facility is an automatic feature of the Compile command.
The first module of the Compiler, the Compiler Netlist Extractor,
extracts the netlist that is used to derme the design from each file.
At this time, design rules are checked for any errors. If errors are
found, the Graphic Editor is invoked when the error appears in a
GDF, and the lext Editor is invoked when the error appears in a
TDE The Error Reportwindowinboth editors highlights the location ofthe error. Asuccessfully extracted design is built into a database to be used by the LogicSynthesizer.
The Logic Synthesizer module translates and optimizes the userdefined logic for the MAX architecture. Any unused logic within
the design is automatically removed. The Logic Synthesizer uses
expert system synthesis rules to factor and map logic within the
multilevel MAX architecture. It then chooses the approach that
ensures the most efficient use of silicon resources.
The next module, the Fitter, uses heuristic rules to optimally place
the synthesized design into the chosen MAX EPLD. For MAX devices that have a Programmable InterconnectArray(PIA), the Fitter also routes the signals across this interconnect structure, so the
designerdoesn't have to worry about placement and routing issues.
A Report File (.RPT) is issued by the Fitter, which shows design
implementationas well as any unused resources in the EPLD. The
designer can then determine how much additional logic may be
placed in the EPLD.
For large system-level designs, the logic design is broken up into
multipleEPLDs of the same family. The designer does not have to
manually split a large design into many smaller designs. The user
can control the design's partitioning at the source level by specifying chip assignments to flip-flops and pins.
A Simulator Netlist File (.SNF) may be extracted from the compiled design by the Simulator Netlist Extractor if simulation is desired. Finally, the Assembler creates a Programmer Object File
(.POF) from the compiled design. This file is used with the
QP2-MAX programming hardware to program the desired
CY7C340family member.
Delay Prediction and Probes
MAX +PillS II includes powerful analysis tools to verify and analyze the completed design. Delay analysis with the delay predictor
may be performed interactively in the Graphic Editor, or in the
Simulator. The Simulator is interactive and event-driven, yielding
true timing and functional characteristics of the compiled design.
The delay predictor provides instant feedback about the timing of
the processed design. After selecting the start point and end point
of a path, the designer may determine the shortest and longest
propagation delays of speed-critical paths.
Also, a designer may use probes to mark internal nodes in a design.
The designer may enter a probe by placing the cursor on any node
in a graphic design, selecting the SPE (Symbol:Probe:Enter)command, and then entering a unique name to define the probe. This
name may then be used in the Graphic Editor, Simulator, and
Waveform Editor to reference that node, so that lengthy hierarchical path names are avoided.
Simulator
The MAX +PLUS II Simulator uses the virtual memory of Windows 3.0 to run simulations of large, multichip EPLDs.
Input stimuli can be defined with a straightforward vector input
language, or waveforms can be directly drawn using the Waveform
Editor. Outputs may also be viewed in the Waveform Editor, or
hardcopy table and waveform files may be printed.
The Simulator uses the Simulator Netlist File (SNF) extracted
from the compiled design to perform timing simulation with
lI10-nanosecond resolution. A Command File may be used for
batch operation, or commands maybe entered interactively. Simulatorcommands allow the user to halt the simulation dependent on
user-defined conditions, to force and group nodes, and perform
ACdetection.
If flip-flop set-up or hold times have been violated, the Simulator
warns the user. In addition, the minimum pulse width and period
of oscillation may be defined. If a pulse is shorter than the minimum pulse width specified, or if a node oscillates for longer than
the specified time, the Simulator issues a warning.
13-20
CY3220
MAX +PLUS II Timing Analyzer (MTA)
System Requirements
The MAX +PLUS II TimingAnalyzer(MTA)providesuser-configurable reports that assist the designer in analyzing critical delay
paths, set-up and hold timing, and overall system performance of
any MAX EPLD design. Critical paths identified by these reports
may be displayed and highlighted.
Minimum System ConrJgUration
IBM PS/2 model 70 or higher, PC/AT or compatible
80386-basedcomputer.
PC-DOS version 3.1 or higher.
Timingdelays between multiple source and destination nodes may
be calculated, thus creating a connection matrix giving the shortest
and longest delay paths between all source and destination nodes
specified. Or, the designer may specify that the detailed paths and
delays between specific sources and destinations be shown.
4 Mbytes RAM.
Microsoft Windows version 3.0.
Microsoft Windows-compatible graphics card and monitor.
EGA, VGAor Hercules monochrome display.
The set-uplhold option provides set-up and hold requirements at
the device pins for all pins that feed the D, CLK, or ENABLE inputs of flip-flops and latches. Critical source nodes may be specified individually, or set-up and hold at all pins may be calculated.
This information is then displayed in a table, one set of set-up and
hold times per flip-flop/latch.
The MTA also allows the user to print a complete list of all accessible nodes in a design; i.e., all nodes that may be displayed during
simulation or delay prediction.
20-MB hard disk drive.
1.2-MB SV4" or 1.44-MB 3Y2" floppy disk drive.
3-buttonserialportmousecompatiblewithMicrosoftWindows
3.0.
Parallel port.
Recommended System Configuration
All MTAoptions may be listed in an MTAcommand file. With this
file, the user may specify all information needed to configure the
output.
IBM PS/2 model 70 or higher, or compatible 386-based computer.
SNF2GDF Converter
4 Mbvtes of RAM plus 10 Mbytes of expanded memory with
LIM ~.2-compatible EMS driver.
PC-DOS version 3.3 or higher.
SNF2GDF converts the SNF into logic schematics represented
with basic gates and flip-flop elements. It uses the SNF's delay and
connection information and creates a series of schematics fully annotated with propagation delay and set-up and hold information at
each logic gate. Certain speed paths of a design may be specified
for conversion, so the user may graphically analyze only the paths
consideredcritical.
Microsoft Windows version 3.0.
VGAgraphics display.
2O-MB hard disk drive.
1.2-MB Sv." or 1.44-MB 3'h" floppy disk drive.
3-buttonserialportmousecompatiblewithMicrosoftWindows
3.0.
If State Machine or Boolean Equation design entry is used,
SNF2GDFshows how the high-level description has been synthesized and placed into the MAXarchitecture.
Device Programming
PLDS-MAX contains the basic hardware and software for programming the CY7C340 MAX EPLD family. Adapters are included for programming the CY7C344 (DIP and PLeC) and
CY7C342 (PLeC) devices. Additional adapters supporting other
MAX devices may be purchased separately. MAX +PLUS II programming software drives the QP2- MAX programming hardware. The designer can use MAX + PLUS II to program and verify
CY7C340 MAX EPLDs. If the security bit of the device is not set
to ON, the designer may also read the contents of a MAX device
and use this information to program additional devices.
Parallel port.
Ordering Information
CY3220 MAX +PLUS II System including:
MAX +PLUS II software,
CY3221
manuals
and key.
CY3202
QP2- MAX PLD programmer with
CY3342 & CY3344 adapters.
Device Adapters
CY3340
Adapter for CY7C341 in PLeC packages.
CY3340R Adapter for CY7C341 in PGApackages.
CY3342
Adapter for CY7C342 in PLeC packages.
CY3342R Adapter for CY7C342 in PGA packages.
CY3342F Adapter for CY7C342 in FIatpack (TMB) packages.
CY3344
Adapterfor CY7C344 in DIP and PLCCpackages.
CY3343S Adapter for CY7C343 in DIP and PLeC packages.
Document#: 38-00187
13-21
II
CY3300
CYPRESS
SEMICONDUCTOR
QuickPro II@)
Features
•
•
•
•
•
•
•
•
•
•
Combined PROM, PLD, and EPROM Programmer
Programs all Cypress CMOS & ECL PLDs and PROMs
Easy-to-use, menu-driven software
New device and feature updates via floppy disk and adapters
Plugs into standard IBM PC@ parallel port-no need to use
up a bus slot
Compatible with IBM PC/AT@,PS/2@, and compatible computers
Programs 20-, 24-, 28-, 32-, 40-, 44-, and 68-pin Cypress
PLDs and PROMs via device adapters
Modular design with adapter bus for future device support
and future feature enhancements
Comprehensive self-test and automatic calibration software
Supports Vmargin verification for a higher degree of device
reliability
6". The parallel port cable and AC power adapter cable are both
approximately 6' in length.
Power
AC Power Adapter:
Device Adapters
17 VAC@500mA
Device adapters are external modules with various pin and socket
configurations. Each adapter plugs into the QuickPro II bus connector and maps the pins of particular devices and packages to the
pin electronics resources available at the connector. Each adapter
has at least one LED that indicates when power is being applied to
the socket. In addition to these device adapters, package adapters
are also used to accommodate the various package options available for PLDs and PROMs.
Memory
640K of total memory is necessary to operate the QuickPro II software.
Devices Supported
Description
QuickPro II is Cypress's second-generation QuickPro PLD and
PROM device programmer. It incorporates new architectural features that enable it to handle all current and future devices through
a 96-pin universal bus connector. The QuickPro II hardware can be
installed on any IBM PC/AT- or PS/2-compatible computer by simply plugging into a standard parallel port. The software communicates with the QuickPro II electronics via this parallel port and utilizes intelligent programming algorithms to minimize device
programming time.
The QuickPro II architecture and feature set were dictated by the
needs of Cypress's new-generation PLDs and PROMs. Many of
these devices offer very high performance and complexity with
large numbers of pins. To meet these needs, the QuickPro II utilizes flexible pin electronics, a universal adapter bus and a carefully
engineered system design that minimizes electrical noise. Pin electronics are located as close as possible to the device being programmed. In addition to the Vpp and Vee voltage sources needed
to program parts, the QuickPro II incorporates a Vmargin voltage
source for measuring the relative programming margins to which a
device has been programmed and a Vref voltage source for doing
self-testing and calibration.
For PLDs, QuickPro II uses the JEDEC standard data format, so
present and future design tools such as PLD ToolKit@, ABEL@,
CUPL@, and PALASM@ can be used. QuickPro II reads Intellec
86@, Motorola S, TEK and space format files. It also reads and
writes PROM PC DOS binary files for use with assemblers and
compilers. QuickPro II is a low-cost, full-feature programming/verification system with a flexible and extendible architecture. The
user interface software is menu-driven with complete on-screen explanations.
QuickPro II hardware and software supports the programming and
verification of all Cypress and Aspen PLDs and PROMs.
Ordering Information
CY3300
QuickPro II system including:
CY3301
QuickPro II base unit
CY3302
QuickPro II parallel port cable
CY3303
QuickPro II AC power adapter
CY3304
QuickPro II software (disk & manual)
CY3202
QP2-MAX version of QuickPro II for
PLDS-MAX + PLUS design tool that consists of
the CY3300 system and the CY3342 and CY3344
adapters.
International versions (220V) of the CY3300 and the CY3202 are
also available.
Device Adapters
Technical Information
Size
The QuickPro II base unit is approximately 10 1/2" x 81/2" xl".
Individual device family adapters vary in size from 5" x 3" to 6" x
13-22
CY3320
Adapter for all Cypress 20-,24-,28-, and 32-pin
devices excluding the MAX parts. Contains
20-, 24, and 28- pin DIP sockets (package
adapters required for 32-pin devices).
CY3342
Adapter for the CY7C342-PLCC
CY3342R
Adapter for the CY7C342-PGA
CY3342F
Adapter for the CY7C342-Flatpack
CY3340
Adapter for the CY7C341-PLCC
CY3340R
Adapter for the CY7C341-PGA
CY3344
Adapter for the CY7C344-PLCC & DIP
CY33435
Adapter for the CY7C343-PLCC & DIP
;.~
1= CYPRESS
ry ·
,
CY33 00
SEMICONDUCIDR
Package Adapters
Package adapters are used with the CY3320 generic device programming adapter on the QuickPro II in order to accommodate
Cypress's wide variety of device packaging options. The package
adapters used with devices having 28 native pins on the QuickPro
II are the same as those used on the original QuickPro@. The number of native pins that a device has refers to the number of actual
signal, power and ground pins used-exduding any N/C (No Connects) in a particular package. All devices are programmed in the
CY3320 adapter's DIP socket having the same number of pins as
the native pins on the device. Therefore, a 22VlO is programmed in
the 24-pin DIP socket, regardless of whether it is in a DIP package
or a PLCC package, even though the PLCC package has 28 pins (4
are N/Cs). A package adapter between the 28-pin PLCC and the
24-pin DIP sockets is used to accomplish this. The following list
summarizes the package adapters used with the CY3320 adapter
on the QuickPro II.
Devices with 20 native pins
CY3OO5
20-pin LCC - Package codes L61 and 061 - All devices
CY3OO7
2O-pin PLCC - Package code J61 - All devices
CY3031
20-pin SOJ - Package code V5 - All devices
CY3021
20-pin Cerpack - Package code K71
Devices with 24 native pins
CY3OO4A
28-pin LCC (22VlO, CG7C323, CG7C324)
CY3OO4B
28-pin LCC (7C225, 7C235, 7C245, 7C261/3/4, 7C281/2, 7C291/2, 7C245, 7C291N2N3A)
CY3010
28-pin LCC (20GlO, 20RAI0)
CY3006A
28-pin PLCC and HLCC (22VI0, CG7C323, CG7C324)
CY3006B
28-pin PLCC and HLCC (7C225, 7C235, 7C245, 7C261/3/4, 7C281/2, 7C291/2, 7C245, 7C291N2N3A)
CY3011
28-pin PLCC and HLCC (20GIO, 20RAlO)
CY3019
24-pin Cerpack - Package codes K73, T73 - All devices
CY3030
24-pin SOIC - Package code S13 - All devices
Devices with 28 native pins
CY3OO8
28-pin LCC - Package codes L64 and Q64 - All devices
CY3009
28-pin PLCC and HLCC - Package codes J64 and H64 - All devices
CY3014
28-pin SOIC - Package code S21 - All devices
CY3022
28-pin SOJ - Package code V21 - All devices
CY3020
28-pin Cerpack - Package codes K74, T74 - All devices
CY3017
32-pin rectangular LCC (7C251/4)
CY3024
32-pin rectangular LCC (7C266, 7C271/4, 7C277, 7C279, 7C286)
CY3026
32-pin DIP (7C289)
CY3027
32-pin rectangular LCC (7C285, 7C287)
CY3029
32-pin rectangular LCC (7C289)
II
!J
o
o
....
Document #: 38-00129-B
QuickPro, QuickPro II, and Pill ToolKit are trademarks of Cypress Semiconductor Corporation.
IBM PC, PC/AT, and PS/2 are registered trademarks of International Business Machines Corporation.
ABEL is a registered trademark of Data I/O Corporation.
CUPL is a registered trademark of Assisted Thchnology.
PALASM is a registered trademark of Monolithic Memories Inc.
Intellec 86 is a trademark of Intel Corporation.
13-23
iL:riPRF-SS
~.!
SEMlCONDUClDR
Quality and Reliability
Section Contents
Page Number
Quality, Reliability, and Process Flows .......................................................................
Tape and Reel Specifications ..............................................................................
14-1
14-16
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CYPRESS
SEMICONDUCTOR
Quality, Reliability, and Process Flows
Corporate Views on Quality and Reliability
Cypress believes in product excellence. Excellence can only be defined by how the users perceive both our product quality and reliability. If you, the user, are not satisfied with every device that is
shipped, then product excellence has not been achieved.
Product excellence does not occur by following the industry
norms. It begins by being better than one's competitors, with better designs, processes, controls and materials. Therefore, product
quality and reliability are built into every Cypress product from
the start.
Some of the techniques used to insure product excellence are the
following:
• Product Reliability is built into every product design, starting
from the initial design conception.
• Product Quality is built into every step of the manufacturing
process through stringent inspections of incoming materials
and conformance checks after critical process steps.
• Stringent inspections and reliability conformance checks are
done on fmished product to insure the fmished product quality requirements are met.
• Field data test results are encouraged and tracked so that
accelerated testing can be correlated to actual use experiences.
Product Assurance Documents
Cypress Semiconductor uses MIL-SID-883D and MIL-M38510J as baseline documents to determine our Test Methods,
Procedures and General Specifications for semiconductors.
Customers using our commercial and industrial grade product receive the benefit of a military patterned process flow at no additional charge.
Product testing Categories
Five different testing categories are offered by Cypress:
1. Commercial operating range product: 0 ° C to + 70 ° C.
2. Industrial operating range product: - 40°C to +85°C.
3. Military Grade product processed to MIL-SID-883D; Military
operating range: - 55 ° C to + 125 ° C.
4. SMD (Standardized Military Drawing) approved product: Military operating range: - 55 ° C to + 125 ° C, electrically tested per
the applicable Military Drawing.
5. JAN qualified product; Military operating range: - 55°C to
+ 125°C, electrically tested per MIL-M-38510J slash sheet requirements.
Categories 1, 2, and 3 are available on all products offered by Cypress Semiconductor. Categories 4 and 5 are offered on a more
limited basis, dependent upon the specific part type in question.
Commercial Product Assurance Categories
Commercial grade devices are offered with two different classes of
product assurance. Every device shipped, as a minimum, meets
the processing and screening requirements of level 1.
Levell:
For commercial or industrial systems where the demand for quality and reliability is high, but where field
service and device replacement can be reasonably accomplished.
Level 2:
For enhanced reliability applications and commercial
or industrial systems where maintenance is difficult
and/or expensive and reliability is paramount.
Devices are upgraded from Levell to Level 2 by additional testing and a burn-in to MIL-SID-883D, Method 1015.
Tables 1 and 2 list the 100% screening and quality conformance
testing performed by Cypress Semiconductor in order to meet requirements of these programs.
Military Product Assurance Categories
Cypress's Military Grade components and SMD products are processed per MIL-SID-883D using methods 5004 and 5005 to define our screening and quality conformance procedures. The processing performed by Cypress results in a product that meets the
class B screening requirements as called out by these methods. Every device shipped, as a minimum, meets these requirements.
JAN, SMD, and Military Grade devices supplied by Cypress are
processed for applications where maintenance is difficult or expensive and reliability is paramount. Tables 3 through 7 list the
screening and quality conformance testing that is performed in order to meet the processing requirements required by MILSID-883D and MIL-M-3851OJ.
14-1
III
Quality, Reliability, and Process Flows
Thble 1. Cypress Commercial and Industrial Product Screening Flows-Components
Product Thmpemture Ranges
Commercial O°C to +70°C; Industrial-40°C to +8S o C
Levell
Screen
MIL-STD-883D Method
Level 2
Plastic
Hermetic
Plastic
Hermetic
O.4%AQL
100%
O.4%AQL
100%
LTPD =5
100%
Does Not Apply
Does Not Apply
LTPD =5
100%
100%
100%[1]
100%
100%[1]
100%
5% (max)[2]
100%
5% (max)[2]
~sua~echanical
• Internal Visual
2010
• Hermeticity
- Fine Leak
- Gross Leak
1014, CondAorB (sample) Does Not Apply
Does Not Apply
1014,CondC
Burn-in
• Pre-Bum-in Electrical
• Bum-in
Per Device Specification
Does Not Apply Does Not Apply
Per Cypress Specification
Does Not Apply Does Not Apply
• Post-Bum-in Electrical
Per Device Specification
Does Not Apply Does Not Apply
Does Not Apply Does Not Apply
• Percent Defective
Allowable (PDA)
Final Electrical
Per Device Specification
• Static (DC), Functional,
and Switchmg (AC) Tests
1. At 25°C and Power
Not Performed
Not Performed
100%[1J
100%[1]
100%
100%
100%
100%
Supplies Extremes
2. At Hot Thmperature and
Power Supply Extremes
Cypress Quality
Lot Acceptance
• External Visual
2009
Note 3
Note 3
Note 3
Note 3
• Final Electrical
Conformance
Cypress Method 17-00064
Note 3
Note 3
Note 3
Note 3
Thble 2. Cypress Commercial and Industrial Product Screening Flows-Modules
Product Thmpemture Ranges
Commercial O°C to +70°C; Industrial-40°C to +8S o C
Screen
MIL-STD-883DMethod
Levell
Level 2
Burn-in
• Pre-Burn-in Electrical
• Bum-in
Per Device Specification
Does Not Apply
100%
1015
Does Not Apply
100%
• Post-Burn-in Electrical
Per Device Specification
• Percent Defective
Allowable (PDA)
Final Electrical
• Static (DC), Functional,
and SWltchmg (AC) Thsts
Does Not Apply
100%
Does Not Apply
15%
Not Performed
100%
100%
100%
Per Cypress Module Specification
Per Cypress Module Specification
Note 3
Note 3
Per Device Specification
1. At 25 ° C and Power
Supply Extremes
2. At Hot Temperature and
Power Supply Extremes
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical
Conformance
2009
Cypress Method 17-00064
Notes:
1. Burn-in is performed as a standard for 12 hours at lSO°C.
2. Electrical "Iest is performed after burn-in. Results of this are used
to determine PDA percentage.
3.
14-2
Lot acceptance testing is performed on every lot to gnarantee
ZOO PPM average outgoing qualily.
-=--,;~PRF.SS
Quality, Reliability, and Process Flows
.
SEMICONDUCTOR
1llble 3. Cypress JAN/SMD/Military Grade Product Screening Flows for Class B
Screen
Product Temperature Ranges -55°C to
Screening Per
Method 5004 of
MIL-STD·883D
JAN
SMD/Military
Grade Product
+125°C
Military Grade
Module
VisuaVMechanical
• Internal Visual
Method 2010, Cond B
100%
100%
N/A
• Thmperature Cycling
Method 1010, CondC, (10 cycles)
100%
100%
Optional
• Constant Acceleration
Method 2001, Cond E (Min.),
Yl Orientation Only
100%
100%
N/A
• Hermeticity:
-Fine Leak
-GrossLcak
Method 1014, Cond A or B
Method 1014, Cond C
100%
100%
100%
100%
N/A
N/A
• Pre-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
100%
• Bum-in Test
Method 1015, Cond D,
160 Hrs at 125°C Min. or
80 Hrs at 150°C
100%
100%
100%
(48 Hours at 125°C)
• Post-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
100%
• Percent Defective
Allowable (PDA)
Maximum PDA, for All Lots
5%
5%
10%
Burn·in
Final Electrical Tests
• Static Thsts
Method 5005
Subgroups 1, 2, and 3
100% Test to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Functional Thsts
Method 5005
Subgroups 7, 8A, and 8B
100% Test to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Switching
Method 5005
Subgroups 9, 10, and 11
100% Thst to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
100%
100%
100%
Quality Conformance Tests
• GroupA[4]
Method 5005, see
• GroupB
• GroupC[5]
Tables 4 - 7 for details
• GroupD[5]
External Visual
Method 2009
Notes:
4. Group A subgroups tested for SMD/Military Grade products are 1,2,
3, 7, 8A, 8B, 9, 10, 11, or per JAN Slasb Sheet.
5.
14-3
Group C and D end-point electrical tests for SMD/Military Grade
products are performed to Group A subgroups 1, 2, 3, 7, 8A, 8B, 9, 10,
11, or per JAN Slasb Sheet.
III
•
=:'~~cra<
Quality, Reliability, and Process Flows
llIble 4. Group A lest Descriptions
Sub·
group
1
package type and lead finish built within a six week seal period and
submitted to Group B testing at the same time.
Sample Size/Accept No.
Description
Static Thsts at 25°C
116/0
77/1
Static Thsts at
Maximum Rated
Operating Thmperature
116/0
3
Static Thsts at
Minimum Rated
Operating Temperature
116/0
55/1
4
Dynamic Thsts at 25°C
116/0
77/1
5
Dynamic Thsts at
Maximum Rated
Operating Thmperature
116/0
55/1
6
Dynamic Thsts at
Minimum Rated
Operating Thmperature
116/0
55/1
2
llIble 6. Group C Quality Thsts
Components Modules[6)
Sub·
group
55/1
1
Steady State Ufe Thst,
End·Point Electricals,
Method 1005, Cond D
Components Modules[6)
5
15/2
Group C tests for JAN product are performed on one device type
from one inspection for lot representing each technology. Sample
tests are performed per MIL-M·3851OJ from each three month
production of devices, which is based upon the die fabrication date
code.
Group C tests for SMD and Military Grade products are performed on one device type from one inspection lot representing
each technology. Sample tests are performed per MIL-STD·883D
from each four calendar quarters production of devices, which is
based upon the die fabrication date code.
7
Functional Thsts at 25 ° C
116/0
77/1
8A
Functional Thsts at
Maximum Thmperature
116/0
55/1
End-point electrical tests and parameters are performed per the
applicable device specification.
8B
Functional Thsts at
Minimum Temperature
116/0
55/1
llIble 7. Group D Quality lests (Package Related)
9
Switching Thsts at 25 ° C
116/0
77/1
10
Switching Thsts at
Maximum Thmperature
116/0
55/1
Switching Thsts at
Minimum Thmperature
116/0
11
Sub·
group
Quantity/Accept #
orLTPD
Components Modules[6)
Description
2
Resistance to Solvents,
Method 2015
4/0
4/0
3
Solderability,
Method 2003
10
10/0
5
Bond Strength,
Method 2011
15
NA
Group B testing is performed for each inspection lot. An inspection lot is defined as a group of material of the same device type,
Notes:
Military Grade Modules are processed to proposed JEDEC standard
flows for MIL-SID·883D compliant modules.
14-4
Description
Components Modules!6]
Physical Dimensions,
Method 2016
15
15/2
2
Lead Integrity, Seal:
Fine and Gross Leak,
Method 2004 and 1014
15
15/2
3
Thermal Shock, Temp
Cycling, Moisture
Resistance, Seal: Fine
and Gross Leak, Visual
Examination, EndPoint, Electricals,
Methods 1011, 1010,
1004 and 1014
15
15/2
4
Mechanical Shock,
Vibration· Variable
Frequency, Constant
Acceleration, Seal:
Fine and Gross Leak,
Visual Examination,
End·Point Electricals,
Methods 2002, 2007,
2001 and 1014
15
15/2
llIble S. Group B Quality lests
Sub·
group
Quantity/Accept #
orLTPD
1
55/1
Cypress uses an LTPD sampling plan that was developed by the
Military to assure product quality. Testing is performed to the sub·
groups found to be appropriate for the particular device type. All
Military Grade component products have a Group A sample test
performed on each inspection lot per MIL-STD-883D and the
applicable device specification.
6.
LTPD
Description
--~
.
Quality, Reliability, and Process Flows
·..tC¥PRESS
SEMlCONDUCTOR
-.r
Military Grade Product
1llble 7. Group D Quality 'lests (Package Related)
(continued)
Subgroup
5
6
7
8
Description
Salt Atmosphere,
Seal: Fine & Gross Leak,
Visual Examination,
Methods 1009 & 1014
Internal Water-Vapor
Content; 5000 ppm
maximum@ 100°C,
Method 1018
Adhesion of Lead
Finish,[8]
Method 2025
• SMD and Military Grade components are manufactured in
compliance with paragrap'h 1.2.1 of MIL-STD-883D. Compliant products are identified by an 'MB' suffIX on the part
number (CY7CI22-25DMB) and the letter "C"
• JAN devices are manufactured in accordance with
MIL-M-3851OJ
• Military grade devices electrically tested to:
- Cypress data sheet specifications
OR
- SMD devices electrically tested to military drawing specifications
Quantity/Accept #
orLTPD
Components Modules(7)
15 (0)
15/2
3(0) or 5(1)
N/A
15(0)
15/2
5(0)
N/A
Lid Torque,
Method 2024[9]
OR
- JAN devices electrically tested to slash sheet specifications
• All devices supplied in hermetic packages
• Quality conformance inspection: Method 5005, Groups A, B,
C, and D performed as part of the standard process flow
• Burn-in performed on all devices
- Cypress detailed circuit specification for non-Jan devices
Notes:
7.
8.
9.
Does not apply to leadless chip carriers.
Based on the number of leads.
Applies only to packages with glass seals.
OR
- Slash sheet requirements for JAN products
Group D tests for JAN product are performed per MIL-M-3851OJ
on each package type from each six months of production, based
on the lot inspection identification (or date) codes.
Group D tests for SMD and Military Grade products are performed per MIL-STD-883D on each package type from each 52
weeks of production, based on the lot inspection identification (or
date) codes.
End-point electrical tests and parameters are performed per the
applicable device specification.
Product Screening Summary
• Static functional and switching tests performed at 25 ° C as
well as temperature and power supply extremes on 100% of
the product in every lot
• JAN product manufactured in a DESC certified facility
Ordering Information
JAN Product:
• Order per military document
• Marked per military document
Ex: JM3851O/28901BVA
Commercial and Industrial Product
SMD Product:
• Screened to either Level 1 or Level 2 product assurance flows
• Hermetic and molded packages available
• Incoming mechanical and electrical performance guaranteed:
- 0.02% AQL Electrical Sample test performed on every lot
prior to shipment
- 0.65% AQL Esternal Visual Sample inspection
• Order per military document
• Marked per military document
Ex: 5962-8867001LA
Military Grade Product:
- Order per Cypress standard military part number
- Marked the same as ordered part number
Ex: CY7CI22-25DMB
• Electrically tested to Cypress data sheet
Ordering Information
Military Modules
Product Assurance Grade: Levell
• Military Temperature Grade Modules are designated with an
'M' suffix onfy. These modules are screened to standard combined flows and tested at both military temperature extremes.
• MIL-STD-883D Equivalent Modules are processed to proposed JEDEC standard flows for MIL-STD-883D compliant
modules. All MIL-STD-883D equivalent modules are assembled with fully compliant MIL-STD-883D components.
• Order Standard Cypress part number
• Parts marked the same as ordered part number
Ex: CY7CI22-15PC, PALC22VlO-25PI
Product Assurance Grade: Level 2
• Burn-in performed on all devices to Cypress detailed circuit
specification
• Add 'B' Suffix to Cypress standard part number when ordering to designate burn-in option
• Parts marked the same as ordered part number
Ex: CY7CI22-15PCB, PALC22VI0-25PIB
14-5
•
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components
Area
PROCESS
QC
INCOMING MATERIALS
INSPECTION
All incoming materials are inspected to documented procedures covering the
handling, inspection, storage, and release of raw materials used in the
manufacture of Cypress products. Materials inspected are: wafers, masks,
leadframes, ceramic packages and/or piece parts, molding compounds, gases,
chemicals, etc.
FAB
DIFFUSION/ION
IMPLANTATION
Sheet resistance, implant dose, species and CV characteristics are measured
for all critical implants on every product run. Test wafers may be used to collect
this data instead of actual production wafers. If this is done, they are processed
with the standard product prior to collecting specific data. This insures accurate
correlation between the actual product and the wafers used to monitor
implantation.
FAB
OXIDATION
Sample wafers and sample sites are inspected on each run from various
positions of the furnace load to inspect for oxide thickness. Automated
equipment is used to monitor pinhole counts for various oxidations in the
process. In addition, an appearance inspection is performed by the opeartor to
further monitor the oxidation process.
FAB
PHOTOLITHOGRAPHY
/ETCHING
Appearance of resist is checked by the operator after the spin operation. Also,
after the film is developed, both dimensions and appearance are checked by
the operator on a sample of wafers and locations upon each wafer. Final CDs
and alignment are also sample inspected on several wafers and sites on each
wafer on every product run.
FAB
METALIZATION
Film thickness is monitored on every run. Step coverage cross-sections are
performed on a periodic basis to insure coverage.
FAB
PASSIVATION
An outgoing visual inspection is performed on 100% ofthe wafers in a lot to
inspect for scratches, particles, bubbles, etc. Film thickness is verified on a
sample of wafers and locations within each given wafer on each run. Pinholes
are monitored on a sample basis weekly.
FAB
QC VISUAL OF
WAFERS
FAB
E-TEST
Electrical test is performed for final process electrical characteristics on every
wafer.
FAB
QC MONITOR OF
E-TESTDATA
Weekly review of all data trends; running averages, minimums, maximums,
etc. are reviewed with the process control manager.
TEST
WAFER PROBE/SORT
Verify functionality, electrical characteristics, stress test devices.
TEST
QC CHECK PROBING
AND ELECTRICAL
TEST RESULTS
Pass/faillot based on yield and correct probe placement.
•
Process Details
TO ASSEMBLY
AND TEST
(continued)
14-6
.
_
,~PRFSS
Quality, Reliability, and Process Flows
. ' SEMICONDUCTOR
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
COMMERCIAL AND INDUSTRIAL PRODUCT
PLASTIC
ASSEMBLY
FLOW
HERMETIC
ASSEMBLY
FLOW
Wafer Prep/MounVSaw
Inspect for accurate sawing of
scribeline and 100% saw-through
Die Visual Inspection
Inspect die per Cypress equivalent to
MIL-STD-883D, Method 2010, condition B
OC Visual Lot Acceptance
Sample inspect die; 1.0% AOL
Die Attach
Attach per Cypress detailed specification
OC Process Monitor
Inspect for die position, quality and uniformity of
die attach and attachment strength,
MIL-STD-883D, Method 2010, criteria
Wire Bond
Bond per Cypress detailed speCification
OC Process Monitor - Wire Bonding
Monitor bond strength and failure mode
Internal Visual Inspection
Low-power (3OX) inspection of workmanship
MIL-STD-883D, Method 2010, condition B
OC Visual Lot Acceptance
Sample inspect lot to verify workmanship,
MIL-STD-883D, Method 2010, condition B,
criteria; 0.4% AOL
Die Coat
Coating applied to selected products
(continued)
14-7
•
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components (continued)
Commercial and Industrial Product
PLASTIC
HERMETIC
QC Visual Lot Acceptance for Die Coated Products
Mold/Encapsulate: Plastic Devices
Seal Hermetic Devices
Periodic QC Monitor, Lid-Torque
Shear strength of glass-frit seal tested
to MIL-STD-883D, Method 2024
Post Mold Cure
Per Cypress method for molding compound
Lead Trim/Form
Lead trim and form for plastiC devices, lead
trim for hermetic devices (where applicable)
LotlD
Mark assembly lot on devices
Lead Prep/Finish (Solder Dip)
Prepare leads for solder dip, solder dip devices
and inspect for uniform solder coverage
QC Process Monitor
Verify workmanship and solder coverage
Fine and Gross Leak Test
Method 1014, Cond A or B; fine leak (sample)
Method 1014, Cond C; gross leak (100%)
External Visual Inspection
Inspect for workmanship, construction, cracked or
broken devices, bent leads, crazing, castellation
alignment, and solder coverage.
MIL-STD-883D, Method 2009
(continued)
14-8
Qualit~ Reliabili~
and Process Flows
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
PLASTIC
HERMETIC
OPTIONAL BURN-IN PROCESSING FOR LEVEL 2
Pre-Bum-In Electrical Test
o·
o·•
o·
o•
Burn-In
o
OC Monitor - Burn-In Documents/Results
o
•
Post-Bum-In Electricals
Per applicable device specification
~-<>
•
OC Inspection
PDA verified within limits
••
<>-l
Final Electrical Test
100% test lot; static (DC), functional and switching (AC)
tests perfomed per applicable device specification
Final Device Marking
Final Visual Inspection
Inspect for bent leads, marking, solder coverage, etc.
OC LOT ACCEPTANCE
External Visual Sample
Method 2009; 0.4% AOL
Electrical Sample Test
0.02% AOL to guarantee 200 PPM
Inspection - Pre-Shipment
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
Pack/Ship Order
Key
o
Production Process
D
TesVlnspection
IQ]
Production Process and Test Inspection
<>
OC Sample Gate and Inspection
14-9
•
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components
Militury Components
MILITARY ASSEMBLY FLOW
Wafer Prep/MounVSaw
Inspect for accurate sawing of scribeline and 100% saw-through
Die Visual Inspection
Inspect die per MIL-STD-883D, Method 2010, condition B
OC Visual Lot Acceptance
Sample inspect die; 1.0% AOL
Die Attach
Attach per Cypress detailed specification
Die Adherence Monitor
MIL-STD-883D, Method 2019 or Method
2027
Wire Bond
Bond per Cypress detailed specification
Bond Pull Monitor
MIL-STD-883D, Method 2011
Internal Visual Inspection
Low-power and high-power inspection per
MIL-STD-883D, Method 2010, condition B
OC Visual Lot Acceptance
Sample inspect lot per MIL-STD-883D,
Method 2010, condition B, 0.4% AOL
Die Coat
Coating applied to selected products
OC Visual Lot Acceptance for Die Coated Products
Seal
Periodic OC Monitor, Lid-Torque
Shear strength of glass
(continued)
14-10
;~PRFSS
Quality,
.
_ , SEMICONDUcroR
Reliabilit~
and Process Flows
Product Quality Assurance Flow-Components (continued)
Military Components
Temperature Cycle
Method 1010, Cond C, 10 cycles
Constant Acceleration
Method 2001, Cond E, Y1 Orientation
Lead Trim
Lead trim when applicable
LotlD
Mark assembly lot on devices
Lead Finish
Solder dip or matte tin plate applicable devices and inspect
QC Process Monitor
Verify workmanship and lead finish coverage
External Visual Inspection
Method 2009
Pre-Bum-In Electrical Test
Method 5004, per applicable device specification
Burn-In
Method 1015, condition D
Post-Bum-In Electricals
Method 5004, per applicable device specification
PDA Calculation
Method 5004, 5%
Final Electrical Test
Method 5004; Static, functional and switching
tests per applicable device specification
(continued)
14-11
•
~~PRFSS
Quality, Reliability, and Process Flows
~, SEMlCONDUCJ'OR
Product Quality Assurance F1ow-Components (continued)
Military Components
Lead Finish - Solder Dip
Solder dip applicable devices
Fine and Gross Leak Test
Method 1014, condition A or B, fine leak; condition C, gross leak
Final Device Marking
MIL-STD-883D or applicable device specification
GroupB
Method 5005
Group A
Method 5005, per applicable device specification
Group C and D
Method 5005, in accordance with
1.2.1 of MIL-STD-883D; JAN devices
in accordance with MIL-M-3851OJ
External Visual
Method 2009,100% inspection
External Visual Sample
Method 2009, 0.4% AQL
Plant Clearance
Pack/Ship Order
Key
o
o
Test/Inspection
IQ]
Production Process and Test Inspection
<>
Production Process
QC Sample Gate and Inspection
14-12
&.~PRESS
~,
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Product Quality Assurance Flow-Modules
•
All incoming materials are inspected to documented
procedures covering the handling, inspection, storage,
Incoming materials
and release of raw materials used in the manufacture of
inspection
Cypress products. Materials inspected are: substrates,
active device packages, chip capacitors, lead frames,
solder paste, inks, chemicals, etc.
Kit Picked
Compliance verified, documented,
and traceability established
Clean
Pre-assembly cleaning of components
Solder Paste Depostion
Screen printed and/or dispensed per detailed specifiction
Component Placement
Robotic and/or manual per detailed specification
Solder Reflow
Microprocessor controlled infrared reflow oven
Data logging
(optional)
<>-__
Clean
Flux removal by vapor phase
per detailed specification
AQLvisual
2-sided
1-sided
0,
100% visual
Double-Sided Assembly
Repeat process for side 2
Solder paste deposition
IQI,
Component placement
0,
0
Solder reflow
--_J_--O
AQLvisual
100% visual
Electrical Test
(Pre-bum-in test)
14-13
~
,
<)
Lead Trim
(continued)
0,
0
Clean
Inspect
2-sided
<> -- ---~
1-sided
•
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Modules (continued)
---.
0
OPTIONAL BURN-IN PROCESSING FOR LEVEL 2
(STANDARD FOR MIL DEVICES)
,- --
.
0
o
l-<>
Burn-In
Method 1015
0
QC Monitor - Burn-In Documents!
Results
0
Post-Bum-In Electricals
Per applicable device specification
o
QC Inspection
PDA verified within limits
I
I
I
<>-l
I . __
Final Electrical Test
100% test lot; DC, AC, functional, and dynamic
tests performed per applicable device specification
Final Device Marking
Final Visual Inspection
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
QA electrical test
(room temperature)
Inspection - Pre-Shipment
Pack/Ship Order
o
Key
Production Process
o
TesVlnspection
IQI
Production Process and Test Inspection
<>
QC Sample gate and inspection
14-14
~
_'11; CYPRESS
-?
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Reliability Monitor Program
The Reliability Monitor Program is a documented Cypress procedure that is described in Cypress specification #25-00008, which is
available to Cypress customers upon request This specification
describes a procedure that provides for periodic reliability monitors to insure that all Cypress products comply with established
goals for reliability improvement and to minimize reliability risks
for Cypress customers. The Reliability Monitor Program monitors
our most advanced technologies and packages. Every technology
produced at a given fabrication site (Tech. - Fab.) and all assembly houses are monitored at least quarterly. If failures occur, detailed failure analyses are performed and corrective actions are
implemented. A summary of the Reliability Monitor Program test
and sampling plan is shown below.
Quarterly Reliability Monitor Test Matrix
Devices Tested
#per
Quarter
Stress
HTOL
HAST
Tech. - Fab.
6
All High Volume
3
Tech. - Fab.
6
All High Volume
3
PCT
Plastic Packages
3
TC
Tech. - Fab.
6
Plastic Packages
3
Ceramic Packages
6
All High Volume
3
DRET
FAMOS - San Jose and Texas
2
HTSSL
All Technologies
5
Total
46
Reliability Monitor Test Conditions
Abbrev.
Thmp.(°C)
R.H.(%)
Bias
Sample
Size
LTPD
Read Points
(hrs.)
High-Temperature
Operating Life
HTOL
150
N/A
5.75V Dynamic
116
2
48, 168, 500,
1000
High-Temperature SteadyState Life
HTSSL
150
N/A
5.75V Static
116
2
48, 168, 500,
1000
Data Retention for
Plastic Packages
DRET
185
N/A
N/A
76
3
168,1000
Data Retention for
Ceramic Packages
DRET2
250
N/A
N/A
76
3
168,1000
Thst
PCT
121
100
N/A
76
3
96, 168
Highly Accelerated Stress
Test
HAST
130
85
5.5V Static
76
3
100
Temperature Cycling for
Plastic Packages
TC
-40 to
125°C
N/A
N/A
76
3
500, 1000 Cycles
Temperature Cycling for
Ceramic Packages
TC2
-65 to
150°C
N/A
N/A
45
5
500, 1000 Cycles
Pressure Cooker
14-15
III
CYPRESS
SEMICONDUCTOR
Tape and Reel Specifications
Description
Surface-mounted devices are packaged in embossed tape and
wound onto reels for shipment in compliance with Electronics Industries Association Standard EIA -481 Rev. A
Specifications
Cover Tape
• The cover tape may not extend past the edge of the carrier tapes
• The cover tape shall not cover any part of any sprocket hole.
• The seal of the cover tape to the carrier tape is uniform, with the
~al extending over 100% of the length of each pocket, on each
SIde.
SOICDevices
• The force to peel back the cover tape from the carrier tape shall
be: 20 gms mmimal, 70 gms nominal, 100 gms maximal, at a pullback speed of 300 ± 10 mm/min.
Loading the Reel
Empty pockets between the first and last filled pockets on the tape
are permitted within the following requirements:
• No two consecutive pockets may be left empty
• No more than a total of ten (10) empty pockets may be on a reel
The surface-mount devices are placed in the carrier tape with the
leads down, as shown in Figure 1.
lYPlCAL
PLCC and LCC Devices
TYPICAL
...
SOJDevices
DIRECTION OF FEED
lYPlCAL
DIRECTION OF FEED
[[][[][[]
...
DIRECTION OF FEED
Figure 1. Part Orientation in Carrier Tape
14-16
PIN #1 TO BE ON CIRCUlAR
SPROCKET-HOLE SIDE OF TAPE
~
~~PRESS
~#' SEMICONDUCTOR
Tape and Reel
Leaders and Thailers
The carrier tape and the cover tape may not be spliced. Both tapes
must be one single uninterrupted piece from end to end.
Both ends of the tape must have empty pockets meeting the following minimum requirements:
• Trailer end (inside hub of reel) is 300 mm minimum
• Leader end (outside of reel) is 500 mm min., 560 mm max.
• Unfilled leader and trailer pockets are sealed
• Leaders and trailers are taped to tape and hub respectively using masking tape
Packaging
• Full reels contain a standard number of units (refer to Table 1)
• Reels may contain up to 3 inspection lots.
• Each reel is packed in an anti-static bag and then in its own individual box.
• Labels are placed on each reel as shown in Figure 2. The information on the label consists of a minimum of the following information, which complies with EIA556, "Shipping and Receiving Transaction Bar Code Label Standard":
- Barcoded Information:
Customer PO number
Quantity
Date code
- Human Readable Only:
Package count (number of reels per order)
Description
"Cypress-San Jose"
Cypress pin
Cypress CS number (if applicable)
Customer pin
• Each box will contain an identical label plus an ESD warning label.
Ordering Information
CY7Cxxx-yY'ZXL
xxx = part type
yy = speed
=
= package, temperature, and options
SCT = soic, commercial temperature range
SIT = soic, inductrial temperature range
SCR = soic, commercial temperature plus bum-in
SIR = soic, industrial temperature plus bum-in
VCT = soj, commercial temperature range
VIT = soj, industrial temperature range
VCR = soj, commercial temperature plus burn-in
VIR = soj, industrial temperature plus bum-in
JCT = pIce, commercial temperature range
JIT = pIce, industrial temperature range
JCR = pIce, commercial temperature range plus bum-in
JIR = pIce, industrial temperature range plus bum-in
Notes:
1. The Tor R suffix will not be marked on the device. Units will be
marked the same as parts in a tube.
2. Order releases must be in full-reel multiples as listed in Table 1.
Thble 1. Parts Per Reel and Thpe Specifications
Package 1YPe
Thrminals
Carrier Width (mm)
Pocket Pitch
Parts Per Meter
Parts Per Full Reel
PLCC
18
20
28(S)
44
52
68
84
20
24
28
20
24
28
84
100
132
164
196
24
16
24
32
32
44
44
24
24
24
24
24
24
32
44
44
56
56
3
3
4
6
6
8
8
3
3
3
3
3
3
8
9
9
83.3
83.3
62.5
41.6
41.6
31.2
31.2
83.3
83.3
83.3
83.3
83.3
83.3
31.2
27.7
27.7
22.7
22.7
750
750
500
400
400
350
350
1,000
1,000
1,000
1,000
1,000
1,000
500
400
350
200
SOIC
SOJ
PQFP
11
11
14-17
ZOO
III
Tape and Reel
'Thpe and Reel Shipping Medium
ESDSTICKER
TAPE SLOT IN CORE
13"
REGULAR, SPECIAL, OR
BAR CODE LABEL
Label Placement
Figure 2. Shipping Medium and Label Placement
14-18
INFO
'I
SRAMs
PROMs
PlDs
FIFOs
lOGIC
COMM
RISC
MODULES
ECl
BUS
"I
MiliTARY
',1
TOOLS
'i
QUALITY
"~I
PACKAGES
'~i
.4§i2
:,?:
~,
CYPRFSS
SEMICONDUcroR
Packages
Section Contents
Page Number
Thermal Management and Component Reliability ............................................................. .
Package Diagrams ....................................................................................... .
Module Package Diagrams ............................................................................... .
15-1
15-8
15-61
Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
III
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CYPRESS
SEMICONDUCTOR
Thermal Management and
Component Reliability
One of the key variables determining the long-term reliability of an
integrated circuit is the junction temperature of the device during
operation. Long-term reliability of the semiconductor chip degrades proportionally with increasing temperatures following an
exponential function described by the Arrhenius equation of the
kinetics of chemical reactions. The slope of the logarithmic plots is
given by the activation energy of the failure mechanisms causing
thermally activated wear out of the device (see Figure 1.).
Typical activation energies for commonly observed failure mechanisms in CMOS devices are shown in Table 1.
L
1
,
1.4 eV
I
105
~
1.0eV
/
1Q4
...J
iIi
,
:§
w
a:
w
~
I
1(J3
/
If
~
/
0.5eV""""
C\I
C\I
w
a:
U
/ /
102
C\I
C\I
~O.4ev./
S./
/1
~ =0;
I
/,
,
(i!j
(l)
/
0.3eV=
./
./
./ " /
/
a:
IV'
250
:5- rn r-rn
2 -~r-~
iIi Z ,--0
200 175 150 125 100
75
50
25
TEMPERATURE (OC)
Figure 1. Arrhenius plot, which assumes a failure rate proportional to EXP ( - EAlkT)
where EA is the activation energy for the particular failure mechanism
15-1
d~it~~
Thermal Management
1llble 1. Failure Mechanisms and
Activation Energies in CMOS Devices
Failure Mode
Thermal Performance Data of Cypress Component
Packages
The thermal performance of a semiconductor device in its package
is determined by many factors, including package design and construction, packaging materials, chip size, chip thickness, chip attachment process and materials, package size, etc.
Approximate
Activation Energy (Eq)
Oxide Defects
Silicon Defects
Electromigration
Contact Metallurgy
Surface Charge
Slow napping
Plastic ChemistIy
Polarization
Microcracks
Contamination
O.3eV
O.3eV
0.6eV
0.geV
0.5-1.0eV
1.0eV
1.0eV
1.0eV
1.3eV
1.4eV
Thermal Resistance (aJA, aJc)
Thermal resistance is a measure of the ability of a package to transfer the heat generated by the device inside it to the ambient.
For a packaged semiconductor device, heat generated near the
junction of the powered chip causes the junction temperature to
rise above the ambient temperature. The total thermal resistance is
defined as
a JA = TJ - TA
P
and eJA physically represents the temperature differential between
the die junction and the surrounding ambient at a power dissipation of 1 watt.
Th reduce thermally activated reliability failures, Cypress Semiconductor has optimized both their low-power generating CMOS device fabrication process and their high heat dissipation packaging
capabilities. Table 2 demonstrates this optimized thermal performance by comparing bipolar, NMOS, and Cypress high-speed 1K
SRAM CMOS devices in their respective plastic packaging environments under standard operating conditions
1llble 2. Thermal Performance of Fast lK SRAMs
in Plastic Packages
technology
Device Number
Speed (ns)
Icc(mA)
Vcc(V)
l\w{(mW)
Package RTH (JA) (oC/W)
Junction Temperature (0C)
at Data Sheet PMAX[l]
Bipolar
NMOS
Cypress
CMOS
93422
30
150
5.0
750
120
9122
25
110
5.0
550
120
7C122
25
60
5.0
300
70
160
136
91
The junction temperature is given by the equation
where
and
aeA= Tc-TA
P
TA = Ambient temperature at which the device is operated; Most
common standard temperature of operation equals 70°C
TI = Junction temperature of the IC chip
Tc = Thmperature of the case (package)
P = Power at which the device operates
alC = Junction-to-case thermal resistance. This is mainly a function of the thermal properties of the materials constituting
the package.
alA = Junction-to-ambient thermal resistance
eeA = Case-to-ambient thermal resistance. This is mainly dependent on the surface area available for convection and radiation and the ambient conditions among other factors. This
can be controlled at the user end by using heat sinks providing greater surface area and better conduction path or by air
or liquid cooling.
Notes:
1. Tambient = 70·C
During its normal operation, the Cypress 7C122 device experiences a 91 ° C junction temperature, whereas competitive devices in
their respective packaging environments see a 45°C and 69°C
higher junction temperature. In terms of relative reliability life expectancy, assunting a 1.0 eV activation energy failure mechanism,
this translates into an improvement in excess of two orders of magnitude (lOOx) over the bipolar 93422 device and more than one order of magnitude (3Ox) over the NMOS 9122 device.
The junction-to-ambient environment is a still-air environment
where the device is inserted into a low-cost standard device socket
and mounted on a standard .062· G 10 PC board. For junction-tocase measurements, the same assembly is immersed into a constant
temperature liquid reservoir approaching infinite heat sinking for
the heat dissipated from the package surface.
The thermal resistance values of Cypress standard packages are
graphically illustrated in Figures 2 through 5. Each envelope represents a spread of typical Cypress integrated circuit chip sizes (upper
boundary = 5000 Mils2, lower boundary = 30,000 Mils2) in their
thermally optimized packaging environment.
These thermal characteristics were measured using the TSP (Thmperature Sensitive Parameter) test method described in MIL SID
883C, Method 1012.1. A thermal silicon test chip, containing a
25Q diffused resistor to heat the chip and a calibrated TSP diode to
measure the junction temperature, is used for all characterizations.
15-2
~
=--~
Thermal Management
=;;;CYPRESS
.F SEMICONDUCTOR
Thermal Resistance of Packages with Forced
Convection Air Flow
Thble 3. 24-Lead Cermaic and Plastic DIPs
Package
Cavity/PAD
Size (mils)
8 Je (OC/W}[2,3]
8 JA (OC/W)
24LCDIP[4]
170 x 270
14
64
24LPDUl[5]
160x21O
22
72
One of the methods adopted to cool the packages on PC boards at
the system level is to used forced air (fans) specified in linear feet
per minute or LFM. This helps reduce the device operating temperature by lowering the case to ambient thermal resistance. Available surface area of the package and the orientation of the package
with respect to the air flow affect the reduction of thermal resistance that can be achieved. A general rule of thumb is:
Notes:
2. 8Je measurements were taken in a fluid bath.
3. 8Je evaluation by simulation used a Heat·sink configuration.
4. 24LCDIP = 24 lead CerDIP
5. 24LPDIP = 24 lead Plastic DIP
• For plastic packages:
- 200 LFM air flow can reduce 8JA by 20 to 25%
6. ANSYS Finite Element Software User Guides
SDRC·IDEAS Pre and Post Processor User Guide
SEMI International Standards, Vol. 4, Packaging Handbook, 1989.
7. "Thermal resistance measurements and finite calculations for
ceramic hermetic packages." James N. Sweet et.al., SEMI·
Therm, 1990.
Thermal Resistance:
Finite Element Model
8 Je and 8 JA values given in the following tables have been obtained by simulation using the Finite element software ANSYS[61.
SDRC-IDEAS Pre and Post processor software was used to create
the finite element model of the packages and the ANSYS input
data required for analysis.
- 500 LFM air flow can reduce 8 JA by 30 to 40%
• For ceramic packages:
- 200 LFM air flow can reduce 8JA by 25 to 30%
- 500 LFM air flow can reduce 8 JA by 35 to 45%
If 8JA for a package in still air (no air flow) is known, approximate
values of thermal resistance at 200 LFM and 500 LFM can be estimated. For estimation, the factors given in Table 4 can be used as a
guideline.
Thble 4. Factors for Estimating Thermal Resistance
SEMI Standard (Semiconductor Equipment and Materials International) method SEMI G30-88 states "heat sink" mounting techuique to be the "reference" method for 8 JC estimation of ceramic
packages. Accordingly, 8 J e of packages has been obtained by applying the boundary conditions that correspond to the heat sink
mounted on the packages in the simulation.
Air Flow Rate
(LFM)
Multiplication
Factor
Plastic
200
0.77
Plastic
500
0.66
Ceramic
200
0.72
Ceramic
500
0.60
Package 'IYPe
For 8 JA evaluation, SEMI standard specification SEMI G38-87
suggests using a package-mounting arrangement that approximates the application environment. So, in evaluating the 8JA, package on-board configuration is assumed.
Example:
Model Description
8JA for
a plastic package in still air is given to be 80° C/W. Using
the multiplication factor from Table 4;
• One quarter of the package mounted on a FR-4 PC board.
• Leads have been modeled as a continuous metallic plane, and
equivalent thermal properties have been used to account for
the plastic (or the glass in the case of ceramic packages) that
fills the space between the leads.
• 1W power dissipation over the entire chip is assumed.
• 70°C ambient condition is considered.
• 8 JA at 200 LFM is (80 x 0.77) = 61.6° C/W
• 8 JA at 500 LFM is (80 x 0.66) = 52.8° C/W
8 JA for a ceramic package in still air is given to be 70 ° C/W. Using
Table 4;
Comparison of Simulation Data with Measured
Data
In the case of ceramic packages, it is not unusual to see significant
differences in 8Je values when a heat sink is used in the place of
fluid bathJ7] However, SEMI G30-88 test method recommends
the heat sink configuration for 8 JC evaluation.
8 JA values from simulation compare within 12 percent of the measured values. 8JA values obtained from simulation seem to be conservative with an accuracy of about + 12 percent.
• 8JA at 200 LFM is (70 x 0.72) = 50.4° C/W
• 8JA at 500 LFM is (70x0.60) = 42.0° C/W
Presentation of Data
The following tables present the data taken using the aforementioned procedures.
The letter in the header (D,P,I, etc.) refer to the package designators as detailed in the Package Diagrams section of this catalog.
The numeric values given in the table (e.g., 20.3) refer to the lead
count (20) and package width in inches (.3). If no decimal appears,
then the reader must refer to the package diagrams.
15-3
III
Thermal Management
Thble 5. Plastic DIP Packages
Package'JYpe
Paddle Size
"P"
(mil)
LFMaterial
Die Size
(mil)
Die Area
(sq. mil)
(OC/W)
(0 C/W still air)
6JC
6JA
16.3
110 x 140
Copper
59x70
4,130
56
130
20.3
150 x 190
Copper
145 x 120
17,400
36
97
20.3
150x 190
Copper
109 x 113
12,317
36
99
22.3
160x210
Copper
54x 113
6,102
41
92
22.4
140 x 170
Copper
54x 113
6,102
42
90
24.3
160 x 210
Copper
145 x 120
17,400
28
82
24.3
160 x 500
Copper
145 x213
30,885
26
78
24.3
160 x 580
Copper
129x346
44,634
23
67
24.6
180 x 210
Copper
145 x 120
17,400
24
60
24.6
220 x 240
Copper
145 x 213
30,885
23
58
28.3
120 x 170
Copper
83x98
8,134
30
89
28.3
160x286
Copper
145 x 213
30,885
26
74
28.3
160 x 500
Copper
145 x 213
30,885
24
70
40.6
180 x 180
Copper
100 x 118
11,800
31
57
48.6
250 x 250
Copper
172 x 213
36,636
20
42
64.9
230 x 230
Copper
148 x 196
29,008
22
39
Thble 6. Plastic Surface Mount SOIC, SOJ[8,9]
6 JC
6 JA
Package 'JYpe
"S"and"V"
Paddle Size
(mil)
LFMaterial
Die Size
(mil)
Die Area
(sq. mil)
(OC/W)
(OC/W still air)
16
140 x 170
Copper
98x84
8,232
19.0
120
18
140 x 170
Copper
98x84
8,232
18.0
116
20
180 x 250
Copper
145 x213
30,885
17.0
105
24
180 x 250
Copper
145 x 213
30,885
15.4
88
24
170 x 500
Copper
141 x 459
64,719
14.9
85
28
170 x 500
Copper
145 x213
30,885
16.7
84
28
170 x 500
Copper
141x459
64,719
14.4
80
Notes:
8. The data in Table 6 was simulated for sOle packaging.
9. SOICs and SOJs have very similar thermal resistance characteristics.
The thermal resistance values given above apply to SO] packages also.
15-4
Thermal Management
Thble 7. Plastic Leaded Chip Carrier
Package type
Paddle Size
(mil)
LFMaterial
Die Size
(mil)
20
180x 180
Copper
l09x 113
28
170x280
Copper
118 x 125
28
200 x 256
Copper
145 x 213
32
200 x 356
Copper
44
360x430
Copper
52
270 x 270
52
31Ox31O
52
8Je
Die Area
(sq. mil)
8JA
(OC/W)
(0 CIW still air)
12,317
28
102
14,750
28
82
30,885
28
80
145x 213
30,885
26
76
292 x 350
102,200
16
60
Copper
172 x 213
36,636
21
54
Copper
269 x 244
65,636
20
52
370 x 370
Copper
305 x 305
93,025
17
47
68
360 x 360
Copper
324x318
103,032
15
40
84
250 x 250
Copper
163 x 165
26,895
17
45
84
425 x 425
Copper
335 x 384
128,640
14
35
"J"
Thble 8. Plastic Quad Flatpacks
Package 1YPe
8Je
8JA
Paddle Size
(mil)
Die Size
(mil)
(0C/W)
Alloy 42
310x310
235 x 235
20
78
Alloy 42
310x31O
235 x 235
22
69
160
Alloy 42
31Ox31O
230 x 230
22
68
208
Alloy 42
400 x 400
290 x 320
20
60
"N"
LFMaterial
100
144
(OCIW still air)
Thble 9. Ceramic DIP Packages
Package 1YPe
"D"and"W"
Cavity Size
(mil)
LFMaterial
Die Size
(mil)
Die Area
(sq. mil)
8Je
8JA
(OC/W)
(OCIW still air)
16.3
160x 120
Alloy 42
6Ox70
4200
12
96
18.3
260 x 140
Alloy 42
162x 123
19,926
10
86
20.3
170 x 290
Alloy 42
l09x 113
12,317
10
85
20.3
170x290
Alloy 42
145 x 213
30,885
7
83
22.4
180x210
Alloy 42
145 x 120
17,400
6
63
24.3
180x210
Alloy 42
145 x 120
17,400
8
69
24.3
270 x 170
Alloy 42
145 x 213
30,885
7
67
28.3
175x335
Alloy 42
147 x 176
25,872
5.5
46
28.3
190 x 580
Alloy 42
145 x 270
68,150
5
44
28.3
175 x530
Alloy 42
145 x 470
68,150
5
45
28.6
260 x 260
Alloy 42
118 x 125
14,750
6
40
28.6
260 x 260
Alloy 42
150x 180
27,000
6
43
28.6
260 x 260
Alloy 42
145 x 213
30,885
5
39
28.6
290 x 560
Alloy 42
145 x 213
30,885
4
39
40
32.3
175x530
Alloy 42
198 x 240
47,520
5.5
40.6
260 x 270
Alloy 42
145 x 213
30,885
5
35
48.6
260 x 340
Alloy 42
145 x 213
30,885
5
30
•
(/)
UJ
CJ
1!l!
I
I
---*L
L'360~
.015
~~
~ .050 BSC
.590
,045 MAX,
I
.050 BSC
I
~
.005 MIN
L
.400
l
,340---J
,005 MIN,
.380
BASE AND
BASE AND
SEATING
PLANE
SEATING
.003
:o69L
PLANE
r
L,26D
I
L250
,370
L,250
--l
.370
.325
32·Lead Rectangular Cerpack K75
28·Lead Rectangular Cerpack KSO
DIMENSIONS IN INCHES
DiMENSIONS IN INCHES
MIN.
MIN.
MAX,
PIN 1 I.D.
r
MAX,
.045 MAX.
I
,840 MAX,
~.05DBSC
I
~
L .005 MIN.
L340~
L'375~
.3811
,390
BASE AND
SEATING
PLANE
EASE AND
SEATING
PLANE
.003
.Q06L
r
L~
.370
I
L350-l
,390
15-28
L
,350
,390
~
==-=~
'.:11 CYPRESS
-=-.,
Package Diagrams
SEMICONDUCTOR
Ceramic Leadless Chip Carriers
32·Lead Leadless Chip Carrier lAS
1S·Pin Rectangular Leadless Chip Carrier LSO
MIL-STD-1835 C-IOA
PIN 1
U---t-T
.075
DIMENSIONS IN INCHES
MIN.
095
MAX .
DIMENSIONS IN INCHES
MIN .
MAX.
.045
.055
.045
.055
.075
.085
A§Q1
,090
.050
.070
[ 1J7
.742
.758
.433
[2Bod-l
C,44~_
,458
.300
20·Pin Rectangular Leadless Chip Carrier LS1
22·Pin Rectangular Leadless Chip Carrier LS2
MIL-STD-1835 C-13
DIMENSIONS IN INCHES
MIN.
MAX.
DIMENSIONS IN INCHES
MIN,
MAX,
,045
,055
.008 R,
20 PLACES
n
,045
,050
,008 R.
22 PLACES
1
,062
,078
,050
,066
~
n
.484
.496
c~jJ
.296
15-29
1
,075
,060
,050
,063
~
•
Package Diagrams
Ceramic Leadless Chip Carriers (continued)
24-Pin Rectangular Leadless Chip Carrier LS3
28·Pin Rectangular Leadless Chip Carrier L54
MIL-SID-1835 C-llA
DIMENSIONS IN INCHES
MIN.
INCHES
MAX,
,045
Jj55
,045
Jj55
ir
,062
,078
,008 R.
24 PLACES
'065~
~
,055
,075
.050
.066
n
.065
,542
,558
c=",JjJ
,358
32·Pin Rectangular Leadless Chip Carrier LSS
20·Pin Square Leadless Chip Carrier 1.61
MJL-SID-1835 C-12
MIL-SID-1835 C-ZA
DIMENSIONS IN INCHES
MIN,
MAX,
#1
,045.31,055
,008 R,
0-1
32 PLACES
.Q£i
090
~
,045
,055
C
050
000
DIMENSIONS IN INCHES
MIN,
MAX,
BOTTOM
~
TOP
,d-i
c ..
,458
O
t==~yl
fI
,358
15-30
i
~
S!DE~
~
'060
,075
,054
,066
42.::~
.
CYPRESS
•
,
Package Diagrams
SEMICONDUCTOR
Ceramic Leadless Chip Carriers (continued)
24-Square Leadless Chip Carrier 1.63
28-Square Leadless Chip Carrier Ui4
MIL-SID-1835 C-4
DIMENSIONS IN INCHES
MIN
BOTTOM
DIMENSIONS IN INCHES
MIN.
8OTTOM
MAX.
MAX .
.045
.055
1
~
008 PLACES
R
24
TOP
OJ
.045
.055
060
100
050
088
.008 R.
28 PLACES
"~~
TOP
~
1
'064
.078
.045
.066
SIDE
L.395 --J
.410
44-Square Leadless Chip Carrier 1.67
48-Square Leadless Chip Carrier L68
MIL-SID-1835 C-5
PIN 1
PIN 1
DIMENSIONS IN lNCHES
MIN.
MAX.
DIMENSIONS IN INCHES
MlN.
MAX.
.037
043
&1:i:
.055
.008 R.
44 PLACES
[~~_~~J r1
~'''=W
100
064
1
.066
.07B
~
48 PLACES
1r
.054
,066
054
088
II
.660
15-31
Package Diagrams
Ceramic Leadless Chip Carriers (continued)
52-Square Leadless Chip Carrier L69
32-Pin Leadless Chip Carrier L75
DIMENSIONS IN INCHES
MIN,
MAX,
DIMENSIONS IN INCHES
MIN,
MAX.
.740
.760
,045
,055
1
,086
~ ,072
~
,100
,088
~
J
7[
1---- ,740_ _
,761
I------I
,392
.408
--------1
j
915
.835
~LJ
68-Square Leadless Chip Carrier LS1
MIL-STD-1835 C-7
DIMENSIONS IN INCHES
MIN,
MAX,
.045
,055
,008 R,
68 PLACES
n
~
,93
_,93~_
1
,962
15-32
==--~
=.
- - i -=
,
Package Diagrams
CYPRESS
SEMIC~DUCTOR
Plastic Quad Flatpacks
64-Lead Plastic Quad F1atpack N64
TYP.
DIMENSIONS IN MILLIMETERS
LEAD CDPLANARITY 0.102 MAX.
0.80 TYP.
R 0.30 TYP.
0.25 MAX.
R 0.20 TYP.
STANDOFF
0.80±0.!5
III
15-33
~PRF£S
W.l1inCONDUCTOR
Package Diagrams
Plastic Quad Flatpacks (continued)
160-Lead Plastic Quad FIatpack Nl60
PIN #1
.650 (,0256)
TYP,
DIMENSION IN
MI"l
[
INCHES o.s reference only ]
LEAD CDPLANARITY .100 [.004]
,
Mill.
,127±,Q2
~
MAX. 3,':39
~LOOT±'OO1l
. -
....~ ....c.~
••••
~
•••
~
••.•
~ ~ ~.~ ~.~.~---1...
••
•.•
•.
L.!.ill.
Ll57J
I
Mlli.lu
MAX. .500
lQQ21
[,020]
-Il
r
.BOO±.15
L031±.006J
15-34
[
SEAT]NG PLANE
Package Diagrams
Plastic Quad Flatpacks (continued)
160-Lead Plastic Quad Flatpack
with Molded Carrier Ring N161
Q.35±Q.15
TEST PAD
1.50±O,13
#192
TEST
"
0.000
.50 DIA. TYP
L5D DIA. TYP
2.50±O.SO RAD.
TOP 8. BOTTOM
0.25 TYP
TEST PAD
1t129
4.QQ±Q.50 RAD.
TOP 8. BOTTOM
SECTION B-B
0.45±O.05
t
-=E~~~~~~~~~~~~~~~~~(T~E~S~T~P~AD~'~56~X):3=~
r
Q,65±O.20
4.80±O.lOJ
~
~----------------------~
l1.80±0.10
1.50±O.13
II
15-35
Package Diagrams
Plastic Quad Flatpacks (continued)
2OS-Lead Plastic Quad Flatpack N208
PIN #1
o
DIMENSION IN
MM
[
INCHES o.s reference only ]
LEAD CDPLANARITY ,100 [.004]
.500 [,0197]
TYP,
~ 28'OO±'10SQ~
n.l02±.004J
31.20±,25 SQ
[l,228±.010]
.127±,02
LOOS±.OOI]
M.l.ti .3..4.3.
MAX, 3.94
~JSEATINGPLANE
[~
[,155J
t
~ ,oJo
MAX,
.500
[J!.Q.2l
~l-
,aOO±O.1S
L031±,Q06J
[,020]
15-36
.-~
-=;;F SEMICONDUcroR
Package Diagrams
_'~CYPRESS
Plastic Quad Flatpacks (continued)
20S·Lead Plastic Quad F1atpack
with Molded Carrier Ring N209
II
15-37
Package Diagrams
Plastic Dual-In-Line Packages
16-Lead (300-Mll) Molded DIP PI
PIN 1
DIMENSIONS IN INCHES ~
MAX,
l1.21.!l
0.260
1=
I- 0.035
Q.HQ
0.770
IS-Lead (300-MiI) Molded DIP P3
PIN 1
DIMENSIONS IN INCHES .M.Iti.
MAX,
r-1,--
0,280-1
O.325
9
l1
~~ 3'
I-~-l
0,009
0,012+
MIN
2O-Lead (300-MiI) Molded DIP PS
PIN 1
DIMENSIONS IN INCHES MI!:l.
MAX.
~
----""""
~:;::::;::;::::;::=:::::;:::::;:;:::::;~ ~
r
=
SEATING PLANE
:
0,060
15-38
.
£)
~~PRESS
~, SEMICCtlDUCTOR
Package Diagrams
Plastic Dual-In-Line Packages (continued)
22-Lead (400-MiI) Molded DIP P7
PIN 1
DIMENSIONS IN INCHES MIN.
I
MAX.
~
0,360
~:n::;rt"""'~""""""""~~
IllMI!
f- 0.060
r-
0.380--1
11°.425,1
0,0121-q
~r
0.009
3· MIN
I- 0.410-----1
0.485
22-Lead (300-MiI) Molded DIP P9
DIMENSIONS IN INCHES
lilll
MAX.
0280 -j
1- 0325
Ir
,I
0009 BU+
0012+
3. MIN
0.090
0,015
0,110
0.020
I- 0.3IO~
0.385
24-Lead (600-MiI) Molded DIP PH
P1N 1
DIMENSIONS IN INCHES
lilll
MAX.
~
230
r-- a
1260
I~
570
0625
-----I
~I
0009W
0012
QMl!.~
0.685
15-39
3 • MIN
'
Package Diagrams
Plastic Dual-In-Line Packages (continued)
24-Lead (300-MiI) Molded DIP PI3/P13A
OQ;5:
DIMENSIONS IN INCHES
MAX,
--.l
P 13A
1Jl..Q.
]2;lQ
1.200
1.26.0
I
0.030
0.050
l!Jlfill
~
NOTE B
fo~EA~
01,60
P 13
!
NOTE A
0.270
NOTE B
M.\lh
O,OBO
Ir~~
~--A-3.MIN
~JIVV J
~=-I
0.385
0.110
28-Lead (600-Mil) Molded DIP PIS
PIN 1
DIMENSIONS IN INCHES MIN,
MAX.
r--------
1..------
r--- 0570 ----I
Ir-- 0625~1
1 450
1480
~:FW?~~m
J
0T-Q,Q2Q
0009.~3.
0012
I--
0,110
0610
0.685
4O-Lead (600-Mil) Molded DIP P17
PIN 1
=
0.550
~""FlIF!J
~~
15-40
DIMENSIONS IN INCHES MIN,
MAX,
MIN
Package Diagrams
Plastic Dual-In-Line Packages (continued)
32-Lead (600-MiI) Molded DIP P19
PIN 1
DIMENSIONS IN INCHES
28-Lead (300-MiI) Molded DIP P21
DIMENSIONS IN INCHES
r-- 0280-l
Ir 0 325 II
QJlJl2
!8!~~
3. MIN
0012+
I-
~
48-Lead (600-MiI) Molded DIP P25
PIN 1
DIMENSIONS IN INCHES MIN.
MAX.
•
U)
UJ
C!'
c:(
~
o
c:(
a..
15-41
.
.
;~PRESS
Package Diagrams
. , SEMICONDUCTOR
Plastic Dual-In-Line Packages (continued)
64-Lead (900-MiI) Molded DIP P29
PIN 1
DIMENSIONS IN INCHES MIN.
MAX,
Ceramic Windowed Leadless Chip Carriers
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
20-Pin Windowed Square Leadless Chip Carrier Q61
MIL-STD-1835 C-2A
DIMENSIONS IN INCHES
MIN
DIMENSJDNS IN INCHES
MIN.
MAX.
MAX.
.045
.055
.045
,055
.084
.110
1
~~~s
~
,050
DlA
-;oso
~
TOP
[Q]n
.342
-:358
CdR:tJ
.358
15-42
1
084
~~1~4
SIDE~
.066
·~PRFSS
.
~,
Package Diagrams
SEMICONDUCTOR
Ceramic Windowed Leadless Chip Carriers (continued)
44·Pin Windowed Leadless Chip Carrier Q67
MIL-SID-1835 C-5
28·Pin Windowed Leadless Chip Carrier Q64
MIL-SID-1835 C-4
DIMENSIONS IN INCHES
MIN.
MAX
.045
,055
~
.045
.055
008 R
29 PLACES
.290 DIA.
LENS
fl
TOP
t=~gJ
458
1
~
087
n...
114
045
066
SIDE~
66ij
~
:1 ~
~
458
Ceramic Windowed Pin Grid Arrays
68·Pin Windowed PGA Cemmic R68
DIMENSIONS IN INCHES
MIN
MAX.
J75
.185
DIA.
Jir
ffi
350 DIA.
LENS
[ij]
L
68 X
:~k~
l
S
.100
TYP.
~
4X
100
ill
SEATING
PLANE
J
........-
.050 DIA. ---1.
!==
L·040
.060
•
en
w
~
oc(
a..
15-43
iT~~croR
Package Diagrams
Ceramic Windowed Pin Grid Arrays (continued)
84-Lead Wmdowed Pin Grid Array R84
r
,390 DIA,
LENS
(
SEATING PLANE
INDEX MARl<
(NO PIN)
,100
.-----~;~=-~~~~~~~
X
~DIA '
,020
BOTTOM VIE\,!
Plastic Small Outline ICs
16-LeadMolded sOle Sl
PIN 1 ID
DIMENSIONS IN INCHES
MIN,
MAX,
LEAD CDPLANARITY 0,004 MAX,
r---
0,050
TYP,
0,397
----j
0,413
__
W
I~
II
-II- 0,013
0,019
+__,
SEA T1NG PLANE
0,092
~ iJTo5
QJlQ.3.
0,012
15-44
~
=.CYPRF.SS
.
Package Diagrams
- . F SEMICONDUCTOR
Plastic Small Outline ICs (continued)
18-LeadMolded sOle S3
PIN 1 ID
0.291
0.300 0.393
J
DIMENSIONS IN INCHES MIN.
MAX.
LEAD COPLANARITY 0~04 MAX.
0.420
~~
0.032
t=
.!lMZ
------j
SEATING PLANE
OA63~~
~'-.l """'
0.105
0.050
TYP.
II
0.013
--1 f--- 0.019
0.003
o:Di2
20-Lead Molded sOle S5
PIN 1 ID
0.291
0.300 0.393
J
DIMENSIONS IN INCHES
MIN.
MAX.
LEAD COPLANARITY 0.004 MAX.
0.420
~~
0.032
t=
0.497
---------j
SEATING PLANE
+__~
0.513 _ _ _
Jjl,----h~~
'-.l0I65
~m'
0.050
TYP.
II
--1 f---
0.013
0.019
.!l.lI.l.O.
0.003
0.050
o:Di2
15-45
I l-------r M!lZ
--1 f---
0.013
.il~NDU~R
Package Diagrams
Plastic Small Outline ICs (continued)
24-Lead Molded sOle S13
PIN 1 lD
DIMENSIONS IN INCHES
MIN,
MAX,
LEAD CDPLANARITY 0,004 MAX,
r--I~
SEATING PLANE
0,597 ~
0.615 ~l.---1
~
0,050
TYP,
~===:r----°'rlO_5----,-~
II
--11-
0,013
0,019
0.003
0.012
28-Lead Molded sOle S21
PIN 1 ID
DIMENSIONS IN INCHES
MIN,
MAX,
LEAD CDPLANARITY 0,004 MAX,
SEATING PLANE
~0T05
~
II
---.-~'0,092
0.050
TYP.
0,013
-II-
0.019
r-o
=lLl!Q.3.=;,
0.012
15-46
J~I===k}\~
0,015 J [ l 0,007
0.050
0,013
-~~PRESS
----=-F
Package Diagrams
SEMICONDUCTOR
Plastic Small Outline ICs (continued)
28-Lead (400-MiJ) Molded SOIC S28
DIMENSIONS IN INCHES
MIN.
MAX.
LEAD CDPLANARITY 0.004 MAX.
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
qp
--I I--
~:,~j
.013
.019
.020
OPTION 1
.
050
TYP
~:W.ll.'2ll.
~
A
OPTION 2
SEATING PLANE
Jrri=IL.~~~~~~ll~
109
.015
,050
~
~ f----rL
.007
,013
32-Lead (400-MiJ) Molded SOIC S33
DIMENSIONS IN INCHES MIN.
MAX.
LEAD COPLANARITY 0.004 MAX,
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
f J1~ .
~032
,026
.m.:;:
,020
SEA TING PLANE
,050
TYP,
15-47
~~.
" CYPRESS
_
Package Diagrams
SE;MICONDUCIDR
Windowed Cerpacks
24-Lead Windowed Cerpack T73
DIMENSIONS IN INCHES
MIN,
MAX.
.170 DlA, LENS
/
lN11.D'\
1,005
:1ll5
~
-
=
--,
c5
f
,5 90
045 MAX.
[
j
,015
~,019
!
-.I'
050 ESC
--,
~
L ,005
L~~
M1N,
.400
004
,009
BASE AND
SEATING
PLANE
L
r
I
L260~
L
.325
.260
.325
28-Lead Windowed Cerpack T74
DlMENSlDNS lN INCHES
fr
I~
II
MIN.
MAX,
PI N 11.0,
t-- i~~,
-
,;...
-
['
045 MAX,
--,
,015
~,022
r~
TYP,
=
~D
!
-.I
050 BSC
--,
~
L'340~
L ,005
MIN,
,380
BASE AND
SEATING
PLANE
15-48
.
~
Package Diagrams
~=CYPRESS
....... F
SEMlCONDUCTOR
Windowed Cerpacks (continued)
68-Lead Windowed Cerquad Flatpack T91
ELECTRICAL
,045
,055
PIN 1
,380 DIA, LENS TYP,
MECHANICAL
PIN 1
II
15-49
Package Diagrams
Ceramic Quad Flatpacks
160-Lead Ceramic Quad FIatpack Ul60
DIMENSION IN MM (INCH)
MIN,
MAX,
PIN 1
0,650 (,0256)
TYP,
0,300 (,012)
TYP,
f=-----
(f,~~~ ~OO~~)
------1
SQ,
- SEATING PLANE
3.43 <.135)
(,155)
~4
'ilmilmlmilllmimll!lF' I.r
1.'
0.15 ±0,02
(,006
±,OOJ)
~L.I (,020
051 ±0,20
±,OOS)
0,050 (,002)
0,500 (,020)
15-50
~~
Package Diagrams
~icYPRESS
~,
SEMICONDUCTOR
Ceramic Quad Flatpacks (continued)
2OS-Lead Ceramic Quad Flatpack U20S
DIMENSION IN MM (INCH)
MIN
MAX,
PIN 1
0,50 (,0197)
TYP.
0,20 (,008)
TYP,
E
2S,00 ±0,1O
(1.102 ±,OOS)
~
•
SQ,
31.22 ±0,25
(1.229 ±,01O)
SQ,
SEA TING PLANE
1~lIlUumIllIllIllIllIlIlIlW~ I
T
0,050 (,002)
0,500 (,020)
r
J~
0.15 ±0,02
(,006
±,00l)
0,51 ±0,20
(,020 ±OOS)
-(/)
U.I
~
~.~
MIN.
---II--
1.430 _ _ _ _ _---1
~
I----~=-,-:=_-~=,-_,I:.4=8~5~h:+~~~:=~~·::;;I:i,
_
BASE
PLANE
13"1~
.150
MIN.
290
L
.009
~1.2~
IS"
.330
.390
SEA TING PLANE
32-Lead (300-Mil) Windowed CerDIPW32
.140 X .300 DR
.140 X 0400
GLASS LENS
O
t
PIN 1
..
DIMENSIONS IN INCHES
MIN
MAX
245
-,-,-n".-nrTT,,-rrT'-'~~
065
---III-~
850
I
I
.COO
·
_
_
~~
_
_
_
_.
~~~ lr=320II
TI
005 MIN
; - 0§5
155
r r h B A S E PLANE
1.650
290--1
"~~,'rIIS~
tjc:! ~ ~ L~~ ~ ~ L ~
065
.~k~
:rro
SEA TING PLANE
15-57
3'
T5'
.~~~
II
Package Diagrams
Ceramic J-Leaded Chip Carriers
52-Pin Ceramic Leaded Chip Carrier Y59
DIMENSIONS IN INCHES
MIN.
MAX.
PIN 1
SEE
VIEV A
_+ nl
I
.738.785
.756 .795
~~
.756
,z.l&
.795
SEATING PLANE
.006
:oro
-I ~.050
.040 X 45'
BSC
VIEV A
15-58
Package Diagrams
Ceramic J-Leaded Chip Carriers (continued)
28·Pin Ceramic Leaded Chip Carrier Y64
PIN 1
I
---+---
n
f
I
SEATING
PLANE
~
.02"-
m2
l--.050
BSC
.040 X 45°
•
15-59
Package Diagrams
CeramicJ-Leaded Chip Carriers (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
PIN 1
I
I
m
---+----
1.142
1.158
DIMENSIONS IN INCHES
MIN.
MAX.
1.185
1.195
I
.155
.200
SEA TING PLANE
I
---+---
I
--II-- .050
.040 X 45'
BSC
'JYpicaJ Marking for DIP Packages (P and D 'JYpe)
PLACE OF MFG.
"USA:'
DATE CODE:
XXYY
xx
= YEAR
YY = WORKWEEK
WEEK PARTS WERE MARKED (FOR PLASTIC)
WEEK PARTS WERE SEALED (FOR HERMETIC)
MARK LOT CODE:
IDENTIFIES SPECIFIC MARK LOT
THE PRODUCE CAME FROM.
15-60
DEVICE WITH
SPEED, PACKAGE, AND TEMP RANGE
ASSEMBLY CODE:
IDENTIFIES THE SPECIFIC ASSEMBLY
LOT THE PRODUCT CAME FROM.
Module Package Diagrams
CYPRESS
SEMICONDUCTOR
40·Pin DIP Module HDOI
~
I-
IDDD
"I
DDDI~a...&.....+-j• T
0.009
0.013
DIMENSIONS IN INCHES
MIN.
MAX.
~
0.065
0.100
TYP
.!!.Ql§.
0.021
0.050
TYP
40·Pin Ceramic DIP Module HD02
2.220
~
I"
"I
T
rDDDD
0.890
0.910
10000
0.210
0.270
a.. &. . .+-l
l~~~~~~~~ ~~~~~U~~~U~ ~.m
T.lW§
+
~.175
Q:ll!!§.
' ' ~ h~h
0.100
TYP
0.015
0.021
-1
0.050
TYP
15-61
~
0.013
II
Module Package Diagrams
4O·Pin DIP Module HD03
I"
-I
.1.lIZ5
2.025
T
0.590
0.610
~.1
,
O.220G
0.27~ ill~ ~~ ~~ ill ~ ~~ ~~ ~~ ~~ ~~
1-11-1
r
0.010
0.050
~
.QJlllll
~
0.320
0.013
DIMENSIONS IN INCHES
~
MIN.
MAX.
0.175
~ ~ ~~~N
0.100
TV?
0.015
0.021
0.050
TYP
32-Pin DIP Module H004
I"
-I
.u!lIl
1.620
11~~II:Jlf
T
0.590
0.610
~.1
t
.QJlllll
0.013
DIMENSIONS IN INCHES
MIN.
MAX.
0.100
TYP
0.015
0.021
0.050
TV?
15-62
-=--
::;z
~=
CYPRESS
""='? SEMlCONDUCIOR
Module Package Diagrams
===============;;;;;;;;;;;=;;;;;;;;;;;==
48·Pin Ceramic DIP Module HDOS
I-
~
TDDDD
lDDDD
.QJ!!!Q
[] []
~I Llij!~ ~
0.24
0.300
+
0.010
0.050
[] []
[] []
-I
T
0.890
0.920
[] []
~1
.l!.QQZ
~~
0.013
~~~~~~~~~~~~~~~~~~~.250
T.QJg§
I.~.175
~ h~h
0.100
TYP
-1
0.015
0.025
DIMENSIONS IN INCHES
MIN.
0.035
0.060
MAX.
6O·Pin Ceramic DIP Module HD06
~
I-
[I [I~D~"IJ~D~
~I
1
[ T
=4-
1
.l!.QQZ
0.013
DIMENSIONS IN INCHES
0.035
0.060
0.015
0.021
0.100
TYP
15-63
MIN.
MAX.
•
G~PRESS
Module Package Diagrams
SEMICONDUCTOR
============~~==
28·Pin DIP Module HD07
I..
1.386
1.414
..
I
1c=J[dDI}~ [[~
0.230
0.285
II
Q.QW.
-II-- 0.021
I I
DIMENSIONS IN INCHES
MIN.
"MAx.
0.100
-I I-- TYP
28·PIn DIP Module HD09
I'"
1.386
1.414
"I
[:: ::r8Ol----L.:~~
+
f
_~~
.110
_--<..+
~~=~
.108
.132
t
~
J
.330
DIMENSIONS IN INCHES
MIN.
MAX.
15-64
'1L: ~PRESS
SOOOO~UcmR
Module Package Diagrams
~~~~~~~~~~~~~~~~~~~
24-Pin DIP Module HDOS
I~
1.212
~
~I
t
.316
*
f
.290 MAX.
~
.330
DIMENSIONS IN INCHES
MIN.
MAX.
•
15-65
Module Package Diagrams
28-Pin Ceramic DIP Module HDIO
141----o
1.415/1.445
----.I-I
o
I
o
.585/.595
~~~~~
PIN 1
INDICATOR
""'NJ=~
L:
l00TYP.~ ~ I
1.300~
.590/.610
60-Pin Ceramic DIP Module HDll
-L
-L
0.30
MIN.,
-II-
.100TYP.
15-66
'
~F
ll.192
0.208
~
.590/.610
~
Module Package Diagrams
32-Pin DIP Module HD12
I-
1.600
"I
CDC}
~~EMAA
~
0.175
JL
DIMENSIONS IN INCHES
MIN.
MAX.
III UII UR III Ii I
1111111111111111
- - 0.600---1
0.100
•
15-67
--
~~PRE'.SS
~_, SEMICONDUCTOR
Module Package Diagrams
66-Pin PGA Module HGOl
PIN 1
0
/
0
1~
OJ
J
r- .-1
1.09OMAX
t
112233
445566
@) @ 0
@@@
@@@
@@@
@@@
@@@
@@@
o @ @
@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@
.
O.100TYP.
-
.
1 1223
344556
15-68
1.0
TYp.
Module Package Diagrams
36-Pin Vertical DIP Module HVOI
Q..U!Q
1 i
-.-
0 225
.
1------- ~ ------+1
~
0.358
~
0.009
0.013
ill!.!!Q
~~~~
0.100
TYP
0.110
0.015
0.021
0.050
TYP
DIMENSIONS IN INCHES
MIN.
MAX.
SS·Pin Vertical DIP Module HV02
0.200
0.225
1 I
~ ----------+l~1
1-1----------
1
DO DO DO DO
JI
~
1111
~
11
fo1
0.009
0.013
~~
~~
0.090
0.110
ITT
J1J1~
1~
~~
_
_
5
0.12
0.175
...
~~
0.100
TYP
f
0.52o
0.005 MAX
0.015
D.ii2i"
~
0.050
TYP
DIMENSIONS IN INCHES
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MAX.
40·Pin VDIP Module HV03
L~J
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0.125
0.175
0.100
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0.D15
0.025
0~~5
15-69
DIMENSIONS IN INCHES
0.009
0.013
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32-Pin DIP Module PDOI
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0.370
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DIMENSIONS IN INCHES
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15-71
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6O-Pin DIP Module PD06
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15-73
Module Package Diagrams
44-Pin FIat SIP Module PF02
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0.040
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15-80
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15-82
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40-Pin VDIP Module PV01
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15-83
Module Package Diagrams
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0.090
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1.700 REF.
DIMENSIONS IN INCHES
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15-84
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15-86
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Module Package Diagrams
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32-Pin DIP Module SDOl
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0.650
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1.500
15-88
Sales Representatives and Distributors
Domestic Direct Sales Offices
California
Cypress Semiconductor
Corporate Headquarters
3901 N. First Street
San Jose, CA 95134
(408) 943-2600
1l:1ex: 821032 CYPRESS SNJ UD
TWX: 910 997 0753
FAX: (408) 943-6860
Cypress Semiconductor
23586 Calabasas Rd., Ste. 201
Calabasas, CA 91302
(818) 222-3800
FAX: (818) 222-3810
Cypress Semiconductor
2 Venture Plaza, Suite 460
Irvine, CA 92718
(714) 753-5800
FAX: (714) 753-5808
Cypress Semiconductor
12526 High Bluff Dr., Ste. 300
San Diego, CA 92130
(619) 755-1976
FAX: (619) 755-1969
Alabama
Cypress Semiconductor
303 Williams Ave., Ste. 125
HuntsviJle, AL 35801
(205) 533-2794
FAX: (205) 533-2796
Colorado
Cypress Semiconductor
4851 Independence SL, Ste. 189
Wheat Ridge, CO 80033
(303) 424-9000
FAX: (303) 424-0627
Florida
Cypress Semiconductor
10014 N. Dale Mabry Hwy. 101
Thmpa, FL 33618
(813) 968-1504
FAX: (813) 968-8474
Cypress Semiconductor
2SS South Oranae A _
Suite 1255
Orlando, FL 32801
(407) 422-0734
FAX: (407) 422-1976
Illinois
Cypress Semiconductor
1530 E. Dundee Rd., Ste. 190
Palatine, u.. 60067
(708) 934-3144
FAX: (708) 934-7364
Maryland
Cypress Semiconductor
54571Win Knolls Rd, Ste. 103
Columbia, MD 21045
(410) 740-2087
FAX: (410) 997-2571
Minnesota
Cypress Semiconductor
14525 Hwy. 7, Ste. 360
Minnetonka, MN 55345
(612) 935-7747
FAX: (612) 935-6982
New Hampshire
Cypress Semiconductor
61 Spit Brook Road, Ste. 110
Nasbua, NH 03060
(603) 891-2655
FAX: (603) 891-2676
New York
Cypress Semiconductor
244 Hooker Ave., Ste. B
PoulJhkeepsie, NY 12603
(914) 485-6375
FAX: (914) 485-7103
Cypress Semiconductor
Hauppauge Exec. Center
300 \olInderbilt Motor Pkwy., #2100
Hauppauge, NY 11788
(516) 231-0238
FAX: (516) 544-4359
North Carolina
Cypress Semiconductor
7500 Six Forks Rd., Suite G
Raleigh, NC 27615
(919) 870-0880
FAX: (919) 870-0881
Oregon
Cypress Semiconductor
12225 SW 2nd Street, Ste. 200
Beaverton, OR 97005
(503) 626-6622
FAX: (503) 626-6688
Pennsylvania
Cypress Semiconductor
1\\'0 Neshaminy Interplex, Ste. 206
Th:vose, PA 19053
(215) 639-6663
FAX: (215) 639-9024
'Thns
Cypress Semiconductor
3jj West Campbell Rd., Ste. 240
Richardson, TX 75080
(214) 437-0496
FAX: (214) 644-4839
Cypress Semiconductor
Great Hills Plaza
9600 Great Hills 'frail, Ste. 150W
Austin, TX 78759
(512) 338-0204
FAX: (512) 338-0865
Cypress Semiconductor
20405 SH 249, Ste. 216
Houston, TX 77070
(713) 370-0221
FAX: (713) 370-0222
Vu-ginia
Cypress Semiconductor
3151 C Anchorway Court
Falls Church, VA 22042
(703) 849-1733
FAX: (703) 849-1734
Domestic Sales Representatives
Alabama
Group 2000 Sales Inc.
l09C Jefferson St.
Huntsville, AL 35801
(205) 536-2000
FAX: (205) 533-5525
Arizona
Thom Luke Sales, Inc.
2940 North 67th PI., Ste. H
Scottsdale, AZ 85251
(602) 941-1901
FAX: (602) 941-4127
California
TAARCOM
451 N. Shoreline Blvd.
Mountain View, CA 94043
(415) 960-1550
FAX: (415) 960-1999
Canada
bbd Electronics, Inc.
6685 -1 Millcreek Dr.
Mississauga, Ontario LSN 5M5
(416) 821-7800
FAX: (416) 821-4541
bbd Electronics, Inc.
298 Lakeshore Rd., Ste. 203
Pointe Claire, Quebec H9S 4L3
(514) 697-0801
FAX: (514) 697-0277
bbd Electronics, Inc. - Onawa
(613) 564-0014
FAX: (416) 821-4092
bbd Electronics, Inc. - WInnipeg
(204) 942-2977
FAX: (416) 821-4092
Mirika
84 Woodland Dr.
Delta, British Columbia V4C 3Cl
(604) 943-5020
FAX: (604) 943-8184
Connecticut
HLM
3 Pembroke Rd
Danbury, cr 06810
(203) 791-1878
FAX: (203) 791-1876
Florida
CM Marketing
445 Douglas Ave., #1455-E
Altamonte Springs, FL 32714
(407) 682 -7709
FAX: (407) 682-7995
Sales Representatives and Distributors
Domestic Sales Representatives (continued)
CM Marketing
1435 - D Gulf to Bay Blvd.
Clearwater, FL 34615
(813) 443-6390
FAX: (813) 443-6312
CM Marketing
3108 NE 26th St.
Ft. Lauderdale, FL 33305
(3OS) 566-6386
FAX: (30S) 537-4725
Georgia
Group 2000 Sales Inc.
5390 Peachtree Industrial Blvd
Suite 210B
Norcross, GA 30071
(404) 729-1889
FAX: (404) 729-1896
Illinois
Micro Sales Inc.
901 W. Hawthorn Drive
Itasca, IL 60143
(708) 285 -1000
FAX: (708) 285-1008
Indiana
Thchnology Mktg. Corp.
599 Industrial Dr.
Carmel, IN 46032
(317) 844-8462
FAX: (317) 573-5472
Thchnology Mktg. Corp.
4630-10 W. Jefferson Blvd.
Ft. Wayne, IN 46804
(219) 432-5553
FAX: (219) 432-5555
Thchnology Marketing Corp.
1214 Appletree Lane
Kokomo, IN 46902
(317) 459-5152
FAX: (317) 457-3822
Iowa
Midwest Thchnical Sales
463 Northland Ave., N.B.
Suite 101
Cedar Rapids, IA 52402
(319) 377-1688
FAX: (319) 377-2029
Kansas
Midwest Thchnical Sales
21901 La Vista
Goddard, KS 67052
(316) 794-8565
Midwest Thchnical Sales
15301 W. 87 Parkway, Ste. 200
Lenexa, KS 66219
(913) 888-5100
FAX: (913) 888-1103
Kentucky
Thchnology Marketing Corp.
4012 DuPont Circle, Ste. 414
Louisville, KY 40207
(502) 893-1377
FAX: (502) 896-6679
Michigan
Thchrep
2200 North Canton Center Rd.
Suite 110
Canton, MI 48187
(313) 981-1950
FAX: (313) 981-2006
Missouri
Midwest Thchnical Sales
514 Earth CIty Expwy., #239
Earth CIty, MO 63045
(314) 298-8787
FAX: (314) 298-9843
New Jersey
HLM
333 littleton Rd.
Parsippany, NJ 07054
(201) 263 -1535
FAX: (201) 263-0914
New Mexico
Thchni-Source, Inc.
1101 Cardenas NE #103
Albuquerque, NM 87110
(505) 268-4232
FAX: (50S) 268-0451
New York
HLM
P.OBox328
Northport, NY 11768
(516) 757-1606
FAX: (516) 757-1636
Reagan/Compar
37A Brook Hill Lane
Rochester, NY 14625
(716) 271-2230
FAX: (716) 381-2840
Reagan/Compar
214 Dorchester Ave., #3C
Syracuse, NY 13203
(315) 432-8232
FAX: (31S) 432-8238
Reagan/Compar
3301 Country Cluh Road
Ste.2211
P.O. Box 135
Endwell, NY 13760
(607) 754-2171
FAX: (607) 754-4270
Ohio
KW Electronic Sales, Inc.
8514 North Main Street
Dayton, OH 45415
(513) 890-2150
TWX: 510 601 2994
FAX: (513) 890-5408
KW Electronic Sales, Inc.
3645 Warrensville Center Rd. #244
Shaker Heights, OH 44122
(216) 491-9177
TWX: 62926868
FAX: (216) 491-9102
Pennsylvania
L. D. Lowery
2801 West Chester Pike
Broomall, PA 19008
(21S) 356-5300
FAX: (215) 356-8710
KW Electronic Sales, Inc.
4068 Mt. Royal Blvd., Ste. 110
Allison Park, PA 15101
(412) 492-0777
FAX: (412) 492-0780
Puerto Rico
Electronic Thchnical Sales
P.O. Box 10758
Caparra Heights Station
San Juan, P.R. 00922
(809) 798-1300
FAX: (809) 798-3661
Utah
Sierra Thchnical Sales
4700 South 900 East, 30-150
Salt Lake CIty, UT 84117
(801) 566-9719
FAX: (801) 565 -1150
Washington
Electronic Sources
1603 116th Ave. NE, Ste. 115
Bellevue, WA 98004
(206) 451-3500
FAX: (206) 451-1038
Wisconsin
Micro Sales Inc.
210 Regency Court
Suite LlOI
Waukesha, WI 53186
(414) 786-1403
FAX: (414) 786-1813
Sales Representatives and Distributors
Internationa1 Direct Sa1es Offices
Cypress ~emiconductor
International-Europe
Avenue Ernest Solvay, 7
B-1310 La HuJpe, Belgium
Thl: (32) 2-652-0270
Thlex: 64677 CYPINT B
FAJe(32)2-652-1504
France
Cypress Semiconductor France
Miniparc Bit. no 8
Avenue des Andes, 6
ZA de Courtaboeuf
91952 Les Ulis Cedes, France
Thl: (33) 1-69-07-55-46
FAJe (33) 1-69-07-55-71
Germany
Cypress Semiconductor GmbH
Munchner Str. 15A
W-8011, Zorneding, Germany
Thl: (49) 081-06-2855
FAX: (49) 081-06-20087
Cypress Semiconductor GmbH
BiiroNord
Matthias-Claudius-Str. 17
W-2359 Henstedt-Ulzburg, Germany
1l:I: (49) 4193-77217
FAX: (49) 4193-78259
Italy
SfPress Semiconductor
Via del Poggio Laurentino 118
00144 Rome, Italy
1l:I: (38) 65-920-723
FAX: (39) 65-920-924
Cypress Semiconductor
VI.. Quintino 28
10121 Thrino, Italy
Thl: (39) 11-515-421 or 11-517-421
FAJe (39) 11-518-612
Japan
Sweden
Cypress Semiconductor Scandinavia AB
Marknadsvagen 15
S-183111l1by, Sweden
1lIby Centrum, Ingang S
Thl: (46) 8 638 0100
FAX: (46) 8 792 1560
United Kingdom
Cypress Semiconductor U.K., Ltd.
3;illackhorse Lane, Hitchin,
Hertfordshire, U.K., SG4 9EE
Thl: (44) 462-42-05-66
FAX: (44) 462-42-19-69
Cypress Semiconductor Manchester
27 Saville Rd. Cheadle
Gatley, Cheshire, U.K.
Thl: (44) 614-28-22-08
FAJe (44) 614-28-0746
Cypress Semiconductor Japan K.K.
FUchu-Minami Bldg., 2F
1()'3, 1-Chome, FUchu-machi,
FUchu-shi, Thkyo, Japan 183
Thl: (81) 423-69-82-11
FAJe (81) 423-69-82-10
Internationa1 Sa1es Representatives
Australia
Braemac Ply. Ltd.
Unit 6,111 Moore St
Leichhardt, N.S.W 2040, Australia
Thl: (61) 2-564-1211
FAX: (61) 2-564-2789
Braemac Ply. Ltd.
10-12 Prospect Street, Box Hill
Melbourne, Victoria, 3128, Australia
Thl: (61) 3-899-1272
FAX: (61) 3-899-1276
Austria
Hitronik Vertriebsge GmbH
St. Veitgasse 51
A-I130 Wien, Austria
Thl: (43) 222-824-199
Thlex: 133404 IDT A
FAX: (43) 222-828-55-72
Belgium
Sonetech
limburg Stirum 243
1780 Wemmel, Belgium
Thl: (32) 2-460-0707
FAX: (32) 2 -460-1200
Denmark
Nordisk Elektronik NS
1ransformervej 17
DK-2730 Herlev, Denmark
Thl: (45) 42-84-20-00
Thlex: 35200 NORDEL DK
FAX: (45) 44-92-15-52
Finland
Oy Ferrado AB
p.o. Box 67
02631 Espoo, Finland
Thl: (358) 0 5281
FAX: (358) 0 528 4333
France
ArrCIW Electronics
73n9, Rue des Sole.,.
Silic585
94653 Rungis Cedex
1l:I: (33) 1 4978 49 00
FAJe (33) 1 49 78 05 99
ArrCIW Electronics
Les Jardins d'Entreprises
BetimentB3
213, Rue Gerland
690074'on
Thl: (33) 78 72 79 42
FAX: (33) 78 72 80 24
ArrCIW Electronics
Centreda
Avenue Didier Daurat
31700 Blagnac
1l:I: (33) 6115 75 18
FAJe (33) 61 3001 93
ArrCIW Electronics
Immeuble St. Christophe
Rue de la Frebardiere
Zi Sud Est
35135 Chantepie
1l:I: (33) 99 41 7044
FAX: (33) 99 50 11 28
Newtek
Rue de I.!Esterel, 8, Silic 583
F -94663 Rungis Cedes, France
Thl: (33) 1-46-87-22-00
Thlex: 263046 F
FAX: (33) 1-46-87-80-49
Newtek
Rue de l'Europe, 4
ZacFont-Ratel
38640 Claix, France
Thl: (33) 16-76-98-56-01
FAJe (33) 16-76-98-16-04
Scaib, SA
80 Rue d' Arcueil Silic 137
9 4523 Rungis, Cedes, France
Thl: (33) 1-46-87-23-13
FAJe (33) 1-45-60-55-49
Germany
API Electronik GmbH
Lorenz-Brarenstr 32
W -8062 Markt, Indersdorf
Germany
Thl: (49) 8136 7092
1l:Iex: 527 0505
FAX: (49) 8136 7398
AstekGmbH
Gottlieb - Daimler Str. 7
W - 2358 Kaltenkirchen
Germany
Thl: (49) 41 91-80 07-0
Thlex: 2180120 ASK D
FAX: (49) 41 91-80 07-33
Metronik GmbH
Leonhardsweg 2, Postfach 1328
W -8025 Unterhaching,
Germany
Thl: (49) 89 611080
Thlex: 17897434 METRO D
FAX: (49) 89 6116468
Sales Representatives and Distributors
International Sales Representatives (continued)
Metronik GmbH
Laufamholzstrasse 118
W-SSOO N'Ilmberg.
Germany
Thl: (49) 911 544966
Thlex: 6 26 205
FAX: (49) 911542936
Metronik GbmH
Uiewenstrasse 37
W -7000 Stuttgart 70
Germany
Thl: (49) 711 764033
Thlex: 7 - 255 - 228
FAX: (49) 711 7655181
Metronik GmbH
Siemensstrasse 4-6
W-6805 Heddesheim, Germany
Thl: (49) 6203 4701
Thlex: 465 035
FAX: (49) 6203 45543
Metronik GmbH
Zum Lonnenbohl38
W -4600 Dorbnund 13, Germany
Thl: (49) 231217041
FAX: (49) 231 210799
Metronik GmbH
Buckhomer Moor 81
W -2000 Norderstedt, Germany
Thl: (49) 40 5228091
Thlex: 2162488
FAX: (49) 40-5228093
Metronik Halle
Thalmannplatz 16/0904
0-4020 Halle, Germany
Spoerle Electonic
Kackertstrasse 10
W -5100 Aachen 1, Germany
Thl: (49) 2 41/81162
FAX: (49) 241/81162
Spoerle Electronic
Rudower Strasse 27-29
W-1000 Berlin 47, Germany
Thl: (49) 30/6 014057
Thlex: 186029
FAX: (49) 30 /60 60 11
Spoerle Electronic
Hildebrandstrasse 11
W -4600 Dorbnund 13, Germany
Thl: (49) 231/21801-0
Thlex: 822 555
FAX: (49) 61 03/30 42 01
Spoerle Electronic
Hans-Bunte-Strasse 2
W-7800 Freiburg i.Br., Germany
Thl: (49) 7 61/51045-0
Thlex: 7 721 994
FAX: (49) 761/502233
Spoerle Electronic
Rodeweg 18
W - 3400 Gattingen, Germany
Thl: (49) 5 51/9 04-0
Thlex: 96 733
FAX: (49) 5 51/9 04 46/48
Spoerle Electronic
Wmsbergring 42
W -2000 Hamburg 54, Germany
Thl: (49) 40 /85 3134-0
Thlex: 2164536
FAX: (49) 40 ISS 3134 91
Spoerle Electronic
Thomaskirchhof 22
0-7010 Leipzig, Germany
ThI: (37) 41/28 1838
or (37) 41/2818 49
FAX: (37) 41/281772
Spoerle Electronic
Fohringer Allee 17
W -8043 Unterfohring. Germany
Thl: (49) 89/9 50 99-0
Thlex: 5 216 379
FAX: (49) 89/9 50 99 99
Spoerle Electronic
Rabtsbergstrasse 17
W-SSOO Numberg 10, Germany
Thl: (49) 9 11/5 21 56-0
Thlex: 622 996
FAX: (49) 911/5215635
Spoerle Electronic
Hopftgheimer Slrasse 5
W -7120 Bietigbeim - Bissingen, Germany
Thl: (49) 7142/70 03-0
Thlex: 724 287
FAX: (49) 7142/7003 60
Hong Kong
Thkcomp Electronics, Ltd.
514 Bank Centre
636, Nathan Road
Kowloon, Hong Kong
Thl: (SS2) 3-880-629
Thlex: 385131EKHL
FAX: (852) 7-805-871
India
Spectra Innovations Inc.
Manil'ai Centre, Unit No. S-822
47, Dickenson Rd
Bangaiore-560,042
Thl: 812-566 630 x3808
Thlex: 845 2696 or 8055
(Attn: ICfP-705)
FAX:812-261468 (ICFAX217)
Israel
Thlviton Electronics
P.O. Box 21104, 9 Bilbnore Street
Thl Aviv 61 210, Israel
Thl: (972) 3-544-2430
Thlex: 33400 VITKO
FAX: (972) 3-544-2085
Italy
Cramer ltalia s.p.a.
Via C. Colombo, 134
1-00147 Roma, Italy
Thl: (39) 65-17-981
Thlex: 611517 Cramer I
FAX: (39) 65-14-07-22
Dolt. Ing. Guiseppe De Mica s.p.a.
V. Le Vittorio Veneto, 8
1-20060 Caasina d'Pechi
Milano, Italy
Thl: (39) 29-53- -43-600
Thlex: 330869 DEMICO I
FAX: (39) 29-52-22-27
Silverstar Ltd SPA
V..le fUlvio Thsti, 280
20126 Milano, Italy
Thl: (39) 2 661251
ThIes: 33 2189 SIL 71
FAX: (39) 2 66101359
Japan
1bmen Electronics Corp.
2-1-1 Uchisaiwai-Cho, Chiyoda-Ku
1bkyo, 100 Japan
Thl: (81) 3-3506-3673
Thlex: 23548 TMELCA
FAX: (81) 3-3506-3497
ere Components Systems Co. Ltd
4-8-1, Thuchihashi,
Miyamae-Ku, Kawasaki-Shi,
Kanagawa, 213 Japan
Thl: (81) 44-SS2-5121
Thlex: 3842272 CI'CEC J
FAX: (81) 44-877-4268
Fuji Electronics Co., Ltd.
Ochanomizu Center Bldg.
3-2-12 HOng<), Bunkyo-Ku
1bkyo, 113 Japan
Thl: (81) 3-3814-1411
Thlex: J28603 FUJITRON
FAX: (81) 3-3814-1414
N.D.A. Co. Ltd
Cuctus lidabashi Bldll'
4-8-3 lidabashi Chiyoda-Ku
'lbkyo, 102 Japan
Thl: (81) 3-3264-1321
Thlex: J29503 lSI JAPAN
FAX: (81) 3-3264-3419
Fujitsu Devices, Inc.
Osaki West Bldg.
8-8, Osaki 2-Chome, Shinagawa-ku
1bkyo 141, Japan
Thl: (81) 3-3490-3321
FAX: (81) 3-3490-7274
Korea
Hanaro Corporation
HanaBldg.
122-30 Chung Dam Dong
Kangnam-ku
Seoul, Korea
Thl: (82) 2-516-1144
FAX: (82) 2-516-1151
Sales Representatives and Distributors
International Sales Representatives (continued)
Netherlands
Semicon B.V.
Gulberg 33, NL-5674
11: Nuenen
The Netherlands
11:1: (31) 40-83-70-75
11:1= 59418 INfRA NL
FAX: (31) 40-83-86-35
Norway
Nortec Electronics NS
Smedsvingen 4, P.O. Box 123
N -1364 Hvalstad, Norway
11:1: (47) 2-84-62-10
11:lex: 77546 NENAS N
FAX: (47) 2-84-65-45
Singapore
Serial Systems Marketing
21 Moonstone Lane
Pohleng Building #0201
Singapore 1232
11:1: (65) 29-38-830
FAX: (65) 29-12-673
Spain
Comella s.a.
Emilio Munoz, 41 Nave 1-1-2
28037 Madrid, Spain
11:1: (34) 1-327-0614
11:lex: 42007 CETA-E
FAX: (34) 1-327-0540
Comelta s.a.
Pedro Iv, 8-4-5 Planta
08005 Barcelona, Spain
11:1: (34) 3-007-7712
Sweden
1H:s Elektronik AB
P.O. Box 3027
Arrendevigen 36
Sl63 03 SPANGA, Sweden
11:1: (46) 8 362 970
1l:lex: 111 45 tenik s
FAX: (46) 8 761 3065
Switzerland
Basix fUr Elektronik A G.
Hardturmstrasse 181
CH-8010 Zurich, Switzerland
11:1: (41) 1-276-11-11
11:1= 822762 BAEZ CH
FAX: (41) 1-276-12-34
Thiwan R.O.C.
Prospect 1l:chnology Corp.
5, Lane 55, Long-Chiang Road
Thipei, Thiwan
11:1: (886) 2-721-95-33
1l:l= 14391 PROS'IECH
FAX: (886) 2-773-37-56
Sales Representatives and Distributors
Distributors
Arrow Electronics:
Alabama
Huntsville, AL 35816
(205) 837-6955
Arizona
'Thmpe, AZ 85282
(602) 431-0300
California
Calabasas, CA 91302
(818) 880- 9686
San Diego, CA 92123
(619) 565-4800
San Jose, CA 95131
(408) 452-3550
San Jose, CA 95134
(408) 432-7171
Thstin, CA 92680
(714) 838-5422
Canada
Mississauga, Ontario L5T lMA
(416) 670-7769
Dorval, Quebec H9P 2T5
(514) 421-7411
Neapean, Ontario K2E 7W5
(613) 226-6903
Quebec City, Quebec G2E 5RN
(418) 871-7500
Burnaby, British Columbia V5A 4T8
(604) 421-2333
Colorado
En2lewood, CO 80112
(303) 799-0258
Connecticut
Wallingford, CT 06492
(203) 265-7741
Florida
Deerfield Beach, FL 33441
(305) 429-8200
Lake Mary, FL 32746
(407) 333-9300
Georgia
Deluth, GA 30071
(404) 497-1300
Illinois
Itasca, IL 60143
(108) 250-0500
Indiana
Indian~lis,
(317) 2
IN 46268
-2071
Iowa
Cedar Rapids, IA 52402
(319) 395-7230
Kansas
Lenexa, KS 66214
(913) 541-9542
Maryland
Columbia, MD 21046
(301) 596-7800
Gathersbu1; MD
(301) 670- 600
Massachusetts
Wllminfa0n, MA 01887
(617) 6 8-0900
Michigan
Livonia, MI 48152
(313) 462-2290
Minnesota
Eden Prairie, MS 55344
(612) 941-5280
Ha6)l2auge, NY 11788
,(51 231-1000
New Jersey
Marlton, NJ 08053
(609) 596-8000
North Carolina
Raleigh, NC 27604
(919) 876-3132
Ohio
Centerville, OH 45458
(513) 435-5563
Solon, OH 44139
(216) 248-3990
Oklahoma
Thlsa, OK 74146
(918) 252-7537
Oregon
Beaverton, OR 97006-7312
(503) 629-8090
Pennsylvania
Pittsbut.' PA 15238
(412) 9 3-6807
Texas
Austin, TX 78758
(512) 835-4180
Carrollton, TX 75006
(214) 380-6464
Houston, TX 77099
(713) 530-4700
Missouri
St. Louis, MO 63146
(314) 567-6888
Washington
Bellewe, WA 98007
(206) 643-9992
New Jersey
Pinebrook, NJ 07058
(201) 227-7880
Wisconsin
Brookfield, WI 53045
(414) 792-0150
New York
Rochester, NY 14623
(716) 427-0300
Sroikane, WA 99206-6606
( 09) 924-9500
Sales Representatives and Distributors
Distributors (continued)
Marshall Industries:
Alabama
Huntsville, AL 35801
(205) 881-9235
Arizona
Phoenix, AZ 85044
(602) 496-0290
California
Marshall Industries,
Headquarters
EI Monte, CA 91731-3 4
(818) 307-6000
Co20
Irvine, CA 92718
(714) 458-5301
Chatsworth, CA 91311
(818) 878-7000
Rancho Cordova, CA 95670
(916) 635-9700
San Diego, CA 92131
(619) 578-9600
Milfitas, CA 95035
(40 ) 942-4600
Canada
Brampton, Ontario
(416) 458-8046
Ottawa, Ontario
(613) 564-0166
Pointe aaire, Quebec
(514) 694-8142
Colorado
Thornton, CO 80241
(303) 451-8383
Connecticut
Wallin~ord,
CT 06492-0200
(203) 65-3822
Florida
Ft. Lauderdale, FL 33309
(305) 977-4880
Florida (continued)
Altamonte ~rings, FL 32701
(305) 767- 85
SL PetersbulJ5 FL 33716
(813) 573-1 99
New York
Johnson Ci¥3 NY 13790
(607) 785- 45
Rochester, NY 14624
(716) 235-7620
Georgia
Norcross, GA 30093
(404) 923-5750
North Carolina
Raleigh, NC 27604
(919) 878-9882
illinois
Schaumbrut, IL 60173
(708) 490- 155
Ohio
Solon, OH 44139
(216) 248-1788
Indiana
Indian~olis,
IN 46278
(317) 2 7-0483
Kansas
Lenexa, KS 66214
(913) 492-3121
Maryland
Silver S:ff.,s, MD 20910
(301) 6 - 118
Massachusetts
Wllminrs0n, MA 01887
(617) 6 8-0810
Michigan
Livonia, MI 48150
(313) 525-5850
Minnesota
P~outh,
MN 55441
( 12) 559 - 2211
Missouri
Bridfeton, MO 63044
(314 291-4650
New Jersey
Fairfield, NJ 07006
(201) 882-0320
Mt Laurel, NJ 08054
(609) 234-9100
Dayton, OH 45414
(513) 898-4480
Oregon
Beaverton, OR 97005
(503) 644-5050
Pennsylvania
ML Laurel, NJ 08054
(609) 234-9100
Pittsburgh, PA 15238
(412) 788-0441
Texas
Austin, TX 78754
(512) 837-1991
Carrollton, TX 75006
(214) 233-5200
Houston, 'IX 77040
(713) 467-1666
Utah
Salt Lake C~, UT 84115
(801) 973- 88
Washington
Bothell, WA 98011
(206) 486-5747
Wisconsin
Waukesha, WI 53186
(414) 797-8400
Sales Representatives and Distributors
Distributors (continued)
Semad:
Toronto
Markham, Ontario LJR 4Z4
(416) 475-3922
FAX: (416) 475-4158
Montreal
Pointe Claire, Quebec H9R 427
(514) 694-0860
1-800-363-6610
FAX: (514) 694-0965
Ottawa
Ottawa, Ontario K2C ORJ
(613) 727-8325
FAX: (613) 727-9489
Vancouver
Burnaby, British Columbia V3N 4S9
(604) 420-9889
i-81J0-663-8956
FAX: (604) 420-0124
Calgary
Calgary, Alberta 'I2H 288
(403) 252-5664
FAX: (604) 420-0124
Falcon Electronics:
Ha'!Ppauge, U, NY 11788
(SIb) 724-0980
Franklin, MA 01701
(508) 520-0323
Milford, cr 06460
(203) 878-5272
Baltimore, MD 21233
(301) 247-5800
Wmter Park, FL 32792
(407) 671-3739
Anthem Electronics, Inc.:
1bm~,
AZ 85281
(602) 966-6600
Zeus Components,lDc.:
Agoura Hills, CA 91301
(818) 889-3838
Chatsworth, CA 91311
(818) 775-1333
Yorba Linda, CA 92686
(714) 921-9000
East Irvine, CA 92718
(714) 768-4444
San Jose, CA 95131
(408) 629-4789
Rocklin, CA 95677
(916) 624-9744
Oviedo, FL 32765
(305) 365-3000
San Jose, CA 95131
(408) 453-1200
Lexington, MA 02173
(617) 246-8200
San Diego, CA 92121
(619) 453-9005
Columbia, MD 21045
(301) 997-1118
Englewood, CO 80112
(303) 790-4500
Port Chester, NY 10573
(914) 937-7400
Waterbury, cr 06705
(203) 575-1575
Ronkonkoma, NY 11779
(516) 737-4500
Clearwater, FL 34623
(813) 797-2900
Dayton, OH 45439
(513) 293-6162
Schaumburg,_ IL 60173
(708) 884-0200
Richardson, TX 75081
(214) 783-7010
WIlmington, MA 01887
(508) 657-5170
Columbia, MD 21046
(301) 995-6640
Eden Prairie, MN 55344
(612) 944-5454
Pine Brook, NJ 07058
(201) 227-7960
Commack, NY 11725
(516) 864-6600
Beaverton, OR 97005
(503) 643-1114
Horsham, PA 19044
(215) 443-5150
Richardson, TX 75081
(214) 238-7100
Salt Lake City, UT 84119
(SOl) 973-8555
Bothel, WA 98011
(206) 483-1700
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