1992_Hitachi_Application_Handbook 1992 Hitachi Application Handbook

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APPLICATION
HANDBOOK
• Application Notes
• Technical Notes
• Technical Briefs

HITACHI~

MOOT021

(

When using this document, keep the following in mind:

J. This document may, wholly or partially, be subject to change without
notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
5. No license is granted by implication or otherwise under any patents or
other"rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not" limited to, use in life support systems. Buyers of Hitachi' s products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.

August 1992

©Copyright 1992. Hitachi America. Ltd.

Printed in U.S.A.

Application Handbook Index

SECTIONS:

z
o

~

HITACHI~

HITACHI APPLICATION HANDBOOK
Table of Contents
SECTION 1
Page
Introduction ............................................................................................................................................. 3

APPLICATION NOTES AND TECHNICAL NOTES & BRIEFS
SECTION 2
HD64180 Family
HD641180X, 3180X, 7180X Technical Q & A Application Note ...........................................................3
HD64180S NPU Technical Q & A Application Note .........................................................................101
HD64180 Technical Q & A Application Note ....................................................................................193
Working with Interrupts-HD64180RlZ, 7180X Application Note ...................................................237
Demo Board to PC Bus Shared Memory Interface Application Note ..............................................241
180 Applications Board-Hardware Notes-HD64180R, Z Application Notes ............................... 245
Using the NPU in Appletalk Applications .........................................................................................249
. Chained Block Transfer DMA Application Note ...............................................................................289
Memory Read and Write Timing Application Note ...........................................................................307
Task Switching Using the 64180 MMU Application Note ................................................................311
Reading of a Short Data Byte from the 64180 CSIO Technical Brief ..............................................333
Start Bit Detection in the 64180's ASCI Technical Brief ..................................................................334
Differences in Mask Sand S2 of NPU Technical Note ....................................................................336
Start Bit Detection in MSCI Technical Note .....................................................................................337
DCDO Line Operation-HD64180R, Z, 7180X Technical Note........................................................339
HD64180 DMAC: Memory-mapped 1/0 Transfers Technical Note ..................................................340
Notes on HD64180S (NPU) Bit Sync Loop Mode Technical Note ...................................................341
HD647180X Port A Programming Technical Brief ...........................................................................342
SECTION 3
4-Bit Family
TMA3 bit on Timer A Operation-Compact 400 Technical Note .........................................................3
4-bit ZTAT Microcomputer PROM Programming Tip HMCS400 Technical Note ............................... 5
HD404272 User Cable Conversion Board ...........................................................................................7
SECTION 4
Display Devices
Graphics
QA Test/Reliability Data-HD63484/487 Technical Note ....................................................................5
ACRTC-Mask History Technical Note ...............................................................................................7
EV63487 MIVAC Evaluation Board Technical Brief .................................... :........................................8

HITACHI APPLICATION HANDBOOK
Table of Contents (cont'd)
Page
SECTION 4
LCD
HD447S0 and LCD Panel Design Tutorial Application Note .............................................................. 21
HD61830B/LM200 Split Panel Scanning Application Note .............................................................. .47
Pixie Switch Auto Dash Board Indicator Application Note ................................................................63
HD61830/LM200 Custom Char. Gen. Tutorial Part II Application Note ............................................. 75
HD61830B/LM200 Panel Design !utorial Application Note ............................................................ 107
LCD Controller ROM Mask Change Char Generator Technical Note .............................................. 143
LVIC II ROM Programming Mode-Palette Registers Access-HD66841 Technical Note ............. 149
HS/325 Evaluation Board & LCD Panel Technical Brief ............................•......................................151
LVIC Proto-Type Board-VGA BIW Panel Technical Brief .............................................................. 157
EV66841 LVIC Evaluation Board Technical Brief .............................................................................172
HD66108T-lnternal Oscillator Usage Technical Note ....................................................................192
HD667SO-MPU Read Operation Timing Technical Note ...............................................................194
SECTION 5
H8 Family
H8I3XX Series
HS/31 0 Article on Smart Card Applications .........................................................................................5
H8/300 CPU Technical Q & A Application Note ................................................................................11
H8/300 16 x 16 Multiply Application Note .........................................................................................45
H8/330 Print Buffer Application Note.................................................................................................51
H8/330 Power-down Operation Application Note .............................................................................77
HS/3XX Instruction Execution Time Calculations Technical Note .....................................................85
HS/320 Family EPROM Security Technical Note ...............................................................................8S
HS/350 EPROM Security Technical Note ..........................................................................................90
HS/330 EPROM Security Technical Note ..........................................................................................92
H8/300 CPU Divide Instruction Technical Note .................................................................................94
HS/300 CPU SUBX Instruction Technical Note .................................................................................95
H8I5XX Series
HS/500 CPU Technical Q & A Application Note ..............................................................................101
H8/500 Series Technical Q & A Application Note ............................................................................135
HS/520.EPROM Security Technical Note ........................................................................................185
HS/534 EPROM Security Technical Note ........................................................................................187
H8/536 EPROM Security Technical Note .............................. ;..........................................·............... 189
H8/51 0 Instruction Execution Time Calculations Technical Note .................................................... 191
H8/500 Instruction Execution Time Calculations Technical Note .................................................... 193
H8/532 EPROM Security Technical Note ........................................................................................195

HITACHI APPLICATION HANDBOOK
Table of Contents (cont'd)
SECTION 6
Page
Memory
Word-wide DRAM Applications Technical Note ..................................................................................3
Mask History of HN58C256 Technical Note ........................................................................................5
FLASH Modifications to Intel Code Technical Note ............................................................................7
1M to 4M Flash Upgrade and Features Technical Note ......................................................................9
Low Voltage Memory Offerings T~chnical Note ................................................................................11
Extended Refresh DRAM Technical Note ..........................................................................................12
SECTION 7
Support Tools
H8/300 XRAY Tutorial Application Note ..............................................................................;...............3
H8/300 Software Development from C Source to S Record Application Note ................................. 13
H8/325 Standard I/O Application Note ..............................................................................................25
H8 Fourth Display Routine with HD61830B Application Note ........................................: ..................29
Emulator to PC Interface Guide Application Note .............................................................................45
Symbolic Debugging with the H Series ASE Application Note ..........................................................55
Interfacing to the ASE Emulator Application Note .............................................................................59
Disassemble Code Printout Technical Note ..........................................................'............................61
Starting up Emulator Version XRAY Technical Note ..........................................................................64
Hitachi's ASMH83 H8/300 Assembler/Linker-ASMH83 Assembler Technical Note .......................65
Direct Memory Addressing with C Pointers-Microtec Toolkit Technical Note ................................67
HITACHI SALES OFFICES .....................................................................................................................70

Application Handbook
Application Notes,
Technical Notes and Briefs

HITACHI@

Section

1
Introduction

HITACHI®

z
o

~
LU

(/)

2

Section

HITACHI

1

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

FOREWORD
In this manual you will find a collection of Application Notes, Technical Briefs, TechNotes, and
Question & Answers written by Hitachi, Ltd. and Hitachi America, Ltd. This collection was
compiled through the efforts of the Technical Marketing Group for Hitachi, Ltd., and the
Application Engineering Group and the Field Applications Engineers for Hitachi America, Ltd.
The documents in this handbook included design ideas and examples, application tips and ~
hints, and also product tutorials. They are designed to assist the user in further understanding §
the technical information already available on each of the products. At this time we would like ~
to extend thanks to the individual contributors of Hitachi America, Ltd. for making this handbook possible.
Stan Ayers, Field Application Engineer
Tom Hampton, Manager, Application Engineering
Carol Jacobson, Senior Application Engineer
Amelia Lam, Application Engineer
Marnie Mar, Senior Field Application Engineer
Oomer Serang, Senior Field Application Engineer
Kash Yajnik, Senior Application Engineer
Paul Yiu, Associate Application Engineer
This title is not all inclusive, so please check with your nearest Hitachi representative for
additional information.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300

Section

1

3

4

Section

HITACHI

1

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2
HD64180
Family

HITACHI®

2

Section

HITACHI

2

Hitachi America. Ltd.' San Francisco Center. 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300

HD641180X, HD643180X, HD647180X
Technical Q and A

Application Note
Preface
The HD643180X, a member of the HD64180 family, is a single-chip microcontroller incorporating
16 kbytes of mask ROM. The HD647180X is a ZTA'fI"M (zero turnaround time) microcontroller that
incorporates 16 kbytes of programmable ROM instead of mask ROM. The HD641180X has no
internal ROM. The HD641180X, HD643180X and HD647180X incorporate the following on a
single chip:
•
•
•
•
•

512 bytes of RAM
Memory management unit (MMU)
DMA controller
Timer
Asynchronous serial communication interface (ASCI)
Clock synchronous serial I/O port (CSI/O)
• Analog comparator
• Parallel I/O pins

z
o

@
C/)

Note: ZTA'fI"M is a tradcmark of Hitachi

How to Use This Technical Q&A Manual
This technical manual contHins answers to questions I hal many users have asked regarding Hitachi
microcontrollers. It is intended to supplement the explanations in the current -1

>-

Low Power Mode
Refresh
Clock Generator
ASE

Common
base reg
(OFH)

~~

1EFFFH

Vr"''''',;X

1CFFFH

~

1BOOOH

Bank base -<
reg (11H)

k?~~~~

Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

15000H
Reference Q&A

Figure 1 Overlapping Common Areas
Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

9

Type HD641180X, HD643180X,HD647180xl Q&A
Item

No.1 QA641-003A!E

DEl Bit in the DMA Status Register (DSTAT)

Classification

Q

MMU

1. How long is DMA transfer disabled when the DEl bit is
set to O?

"

2. How does DMA restart?

DMAC
ASCI

CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait

A

Reset

1. DMA transfer is disabled until DEl is reset to 1. Write 0
to bit DWET before performing any software write to
DEl.
2. If memory H memory DMA transfer is executed in burst
mode, DMA transfer cannot be interrupted. It can only be
interrupted in memory H memory cycle steal mode.
memory H 1/0, or memory H memory-mapped 1/0
transfer mode.
To restart DMA transfer, set DEl to 1.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

commentj

10

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 OA641-004EJ/E
Item

DME (DMA Master Enable) Bit in DMA Status Register

Classification

Q
When NMT occurs, DME is reset to 0 and DMA operation is
disabled, passing control to the CPU.

MMU

,j

DMAC
ASCI

1. How is DMA operation timing halted?

CSI/O

2. How does DMA operation restart?

Timer
Bus Interface
Interrupt
1/0 Port

Memory

z

o

~

IJ)

Wait
A

Reset

1. When NMT occurs, the CPU takes control after the
current DMA cycle is completed (figure 1)
T1

T3

T2

T1

T2

T3

T1

6

Low Power Mode
Refresh
Clock Generator
ASE

~

NMI

Software

DME bit reset to 0.' then
DMA operation stops

:4

~:4

DMA read cycle

~:

..........

: DMA write cycle

Figure 1 f\JMl Timing

2. To restart DMA operation, set DE bit (DEO or DE 1) to 1.

Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

(This operation sets DME to 1.) The following program
restarts DMAC:
LD A,

aUTO
Comment

Reference Q&A

SOH
(30H) , A

OA641-054A

I

HITACHI
Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

11

Type HD641180X, HD643180X, HD647180xI a&A No., QA641-005A1E
Item

OWE Bit in DMA Status Register
Classification

a
What is the function of the OWE bit in the DMA status
register?

MMU

-J

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
A

Reset

The DE bit enables DMA operation for the internal DMAC,
while the DWE bit enables a software write to the
corresponding DE bit, for a specific channel operation.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

commentl

12

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type

HD641180X, HD643180X, HD647180xI Q&A No.

Item

Memory H 1/0 Transfer (channel 0)

I QA641-006B/E

Q

Classification

To enable DliEOo input, both A17 and A16 of the 1/0
address must be set to O.
Is the DMA requested by'Dl1EOo accepted if either A17 or
A16 is set to 1?

MMU

..J DMAC
ASCI
CSIIO

Timer
Bus Interface
Interrupt
I/O Port
A

Memory

No. If either A17 or A16 is set to 1, lJREOo is disabled and
the DMA request is not accepted.

Wait

To use rmEOo input as DMA request, set the bank bit (A16,
A17) according to tables 1 and 2.

Low Power Mode

Table 1 Source Address Register

Clock Generator

SAR18
Don't care
Don't care
Don't care
Don't care

SAR17
0
0
1
1

SAR16
0
1
0
1

DMA Reguest
DR EO 0
RDRF (ASCI chO)
RDRF (ASCI ch1)
Reserved

Table 2 Destination Address Register

z
o

§
w

.CIl

Reset

Refresh

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

DAR18
Don't care
Don't care
Don't care
Don't care
Comment

DAR17
0
0
1
1

DAR16
0
1
0

1

DMA Reguest
DREa o
TDRE (ASCI chO)
TDRE (ASCI ch1)
Reserved

Reference Q&A

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point PkWy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

13

Type HD641180X, HD643180X, HD647180xI Q&A
Item

Memory

H

NO., QA641-007B/E

ASCI DMA Transfer

Classification

Q

To execute memory H ASCI DMA transfer, program DMA
source/destination address register as follows:
1. Set bits Ao-A7 to the address of the ASCI transmit or
receive data register

MMU

"

DMAC
ASCI
CSIIO
Timer

2. Set bits As-AI5 to DOH

Bus Interface

3. Set bits A16, A17 to 0,1 or 1,0

Interrupt
Can the memory H ASCI DMA transfer be executed
correctly if bits As-A15 in the DMA source/destination
address register are not set to OOH?

I/O Port
Memory
Wait

A

Reset

No, if bits As-A15 in the DMA source/destination address
register are not set to DOH, memory H ASCI DMA transfer
cannot be executed correctly.
For example, to execute ASCI (channel 0) RDR -? memory
DMA transfer, set bits Ao-A7to OSH, bits As-AI5 to DOH,
andbitA16,A17toO,I.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD6411S0X, HD6431S0X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment' Setting bits As-AI5 to anything other than OOH causes the internal DMAC
to access another 110 address, not RDR. (DMA request from ASCI
channel 0 is not reset).

Section

14 2

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra PoinIPkwy.· Brisbane, CA 94005-1619 • (415) 569-6300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-00SAlE
Item

Memory (specified in application program)

H

I/O DMA Transfer

Q

Classification

Is it possible to execute memory (specified in application
program) H 1/0 DMA transfer indepenently of the MMU
base register?

MMU

.,J DMAC
ASCI

CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait
A

Reset

No, to execute memory (specified in application program)
1/0 DMA transfer correctly, the physical source address
must be defined as follows:

Low Power Mode

H

Refresh

1. Software calculates the physical source address of the
data area using the logical address and the base register

ASE

2. The calculated physical source address is loaded into the
DMA source address register

Others

If the physical address is known, it can be loaded into the
DMA address register directly, but if the DMA transfer is
executed within the logical memory area, block transfer
instructions can be used.

Clock Generator

Software

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

15

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO., QA641-009B/E

Memory H I/O (Z80SI0) OMA Transfer

Q

Classification

When memory H 110 (Z80SI0) OMA transfer is executed
while
is programmed for leliel sense, OMA transfer
does not complete correctly.

nm:a

Are there any restrictions on OMA operation? (ROY signal
from Z80SI0 is input to 0l1E0 of H064180.)

MMU

"

OMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt
I/O Port
Memory
Wait

'A ,

Reset

The Z80SI0 ROY signal is negated during OMA write cycle
to the peripheral LSI. Therefore, if the UREO is
programmed for level sensing, an additional OMA cycle
starts since ROY is negated after UREO signal sampling
(figure 1)
, OMA read cycle ,

:...

: Tl
Ii>

Address

=p<

ACK

'

:

OREO
(Z80SIu- ,,
ROY output)

T2

....: ....

T3

:

Tl

OMA write cycle
T2

: Tw

...:
T3 :

:'"
,
:

,

Refresh
Clock Generator
ASE
Software

Tl

:£

,
:X
,

Low Power Mode

~

/'

Others

Application Manual
H0641180X, H0643180X,
HD647180X Hardware Manual

Other Data

,

Additional
!
OREOsampled OMA cycle
(If ORE"O'"is not negated here,
an additional OMA cycle starts)
Figure 1 DMATiming

Reference Q&A

I

Comment Take one of three measures: 1} Program ITRE::i for edge sensitivity,
2} Insert a wait state during OMA write cycle to modify 'R1JY response
timing 3) Mask ITRE::i(ROY} signal by the ACK Signal.

16

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy_· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI a&A No.1 QA641-040AlE
Item DMAC Priority

a

Classification

Which has higher priority, ch 0 memory H memory DMA
transfer or ch 1 memory H I/O DMA transfer?
Is it possible to execute ch 1 memory H 1/0 DMA transfer
before ch 0 memory H memory DMA transfer?

MMU

..j

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory

z

o

§
(J)

Wait
A

Reset

DMA ch 0 has priority. However, when ch 1 DMA request is
generated when ch 1 is enabled and ch 0 is disabled, and
the ch 1 DMA is generated continuously, the ch 1 DMA
transfer can be performed.

Low Power Mode
Refresh
Clock Generator
ASE

During ch 0 memory H 1/0 DMA transfer, a ch 1 DMA
request can be accepted if no more ch 0 DMA requests are
generated.
During ch 0 memory H memory DMA transfer, ch 1 DMA
requests are ignored until ch 0 DMA transfer ends.

Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference a&A

Comment

I

HITACHI
Hitachi America, Ltd.· San FranCisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300

SectIOn

2

17

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-042NE
Item

DACK Signal Generation
Classification

Q

How can theDA"CR signal, which indicates DMA transfer
completion, be generated during ch 0 memory H external
1/0 DMA transfer?

MMU

-J

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

110 Port
Memory
Wait

A

Reset

When external 110 is accessed during a DMA cycle, the
external 1/0 address is output through the address bus. At
this time, the TOE signal and address output are decoded to
generate al:JACK.l' signal (figure 1, (1)).

Low Power Mode
Refresh
Clock Generator
ASE

When external 110 is accessed to initialize registers during a
CPU cycle, l:JACK.l' and ST signals are 10gical-ORed to
generate DAC'K-2 to distinguish a DMA from a CPU cycle
(figure 1, ®).
Figures 1 and 2 (next page) show the lJ'ACKgeneration
circuit and signal timing, respectively.

Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data
HD64180 App. Note

Reference Q&A

Comment

18

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180X
Item

UACK Signal Generation

A

roe
Add_

---i
=1

Decoder

:I

[:::(2)-~._<

ST
Figure 1 Circuit Example
,
,

:-

DMA read cycle

:

~:.

DMA wr~e cycle

,,,

z
o

...:,

~

: T1

. . : ;...t1OO1

IOE ---------------~

OACJ<-f--+--------.
/ ASCI
CSI/O
Timer
Bus Intertace
Interrupt

1/0 Port
Memory

z
o
~
UJ

(/)

Wait

A

Reset

No, the OCD flag is not reset unless the ASCI status
register is read. This allows the OCO interrupt to be
serviced correctly.

Low Power Mode

If the ITC1J pin and the DCD flag were reset simultaneously,
the ITC1J interrupt request would always be cleared and
could not be serviced when a higher priority interrupt
occurred simultaneously with the OCO interrupt (figure 1).
Figure 2 shows the actual function used by the
H0647180X.

ASE

Refresh
Clock Generator

Software
Others

Application Manual

Other Data

Reference a&A

Commentl

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300

Section

2

25

r

Type

HD641180X, HD643180X, HD647180xI Q&A No.

Item

ocn Pin and OeD Flag

I QA641-044A-2/E

A

I

OCUpin

I

DCDflag
(Interrupt source)

:

,
,.

,,
,

,,

I

"»)

")j

/"

OCUpin

DCDflag

Interrupt source

oeo

2

,

4

DCD interrupt is
negated, so its interrupt
routine never executes

Flag Synchronized with

I
I

I

,,

I

,,

I

OC'I:J Pin

t(

s)

t(

Sj

,

:
:

1%

Ii

Figure 2 H0647180X

Section

:,

~

Interrupt routine with
priority higher than
OeD will execute

26

/:

)

Interrupt routine with
priority higher than
oeD will execute

Figure 1

:/

,;!

I

Ii

Higher priority
interrupt

,,
,

I
4

oeD interrupt routine
can be executed

OeD Function

HITACHI
Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point P~wy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180X
Item

Q&A

NO.1 QA641-04SAlE

External Clock Divide Ratio

Q

Classification
MMU

Can the internal baud rate generator divider circuit be used
when the ASCI uses an external clock?

DMAC

.J

ASCI
CSI/O
Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
Reset

A
No, the divider cannot be used when the ASCI uses an
external clock. Therefore, the external clock must be ell + 40.
However, sampling rate can be controlled by the DR bit of
the ASCI control register (table 1).

Low Power Mode
Refresh
Clock Generator
ASE

Table 1 Sampling Rate
ORBit
0
1

Software

Samellns Rate
+16
+64

Internal
clock. -

Baud rate
selector (+1-+64)

Others
Application Manual

Prescaler
(+ 10, +30)

T . .,

Sampling

(+ 16,+64)

External
clock
fcs.+
40

Comment

HD641180X, HD643180X,
HD647180X Hardware Manual

~

Other Data

Reference Q&A

I

HITACHI

Section

Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

2

27

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-066A1E
Item

ASCI Data Sampling

Classification

Q

Where on the baud rate clock does the CPU sample data?

MMU
DMAC

..j ASCI
CSI/O

Timer
Bus Interface
Interrupt

110 Port
Memory
Wait
Reset

A
The CPU samples ASCI data at the falling edge of the baud
rate clock.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

Section

28

2

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· 8risbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-067NE
Hem

Restarting ASCI from 1/0 Stop Mode

Classification

Q

MMU

How does ASCI restart from 10STOP mode?

DMAC

..J

ASCI
CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory

z

o

§
CIl

Wait
Reset

A
First, resetting the 10STP bit in the 1/0 control register (ICR)
causes 1/0 stop mode recovery.

Low Power Mode

Then setting the receive enable (RE) bit or transmitter
enable (TE) bit of the ASCI control register restarts ASCI
transmission.

Clock Generator

Refresh

ASE
Software
Others

Application Manual
HD641180X. HD643180X.
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America. Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

29

Type HD641180X, HD643180X, HD647180xI Q&A
Item

No.1 QA641-068A!E

TSR Status

Classification

Q
When transmit enable (TE) is reset to 0, the transmitter is
disabled.

MMU

Does this operation initialize the transmit shift register
(TSR)? .

ASCI

DMAC

-.J

CSIJO
Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait
A

Reset

No, resetting TE to 0 does not initialize the transmit shift
register (TSR) (figure 1).

out~§]~~l§iI§~I~T-

Figure 1 Transmit Shift Register

Refresh
Clock Generator

1

ASE

1

Others

• TE reset to 0

~~ELiI~J2I2I~J-

Low Power Mode

Software

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

comment!

30

Section

HITACHI

2

Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-069A1E
Item

Transmit Interrupt Timing

Classification

Q

When does the CPU acknowledge the transmit interrupt in
the ASCI transmit sequence?

MMU
DMAC

'>/ ASCI
CSIIO
Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
A

Reset

The CPU acknowledges the transmit interrupt when the
start bit goes out to the TXA pin.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

31

Type HD641180X, HD643180X, HD647180xI a8cA No.1 QA641-070AlE
Item

RE and External Serial Clock for the CSIIO
Classification

a

MMU

What is the relation between receive enable (RE) and the
external serial clock (t x in figure 1)?
CKS

'~

:, I x

L

I

:
RXS

RE

DMAC
ASCI

.J

CSI/O
Timer

=IX
:

Bus Interface
Interrupt

~

110 Port

Figure 1 Receive Timing

Memory
Wait

A

Reset

Time tx must be more than 5 system clocks (51jl). If it is less
than 51jl, CSI/O receive operation cannot start correctly.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference a8cA

CommentJ

Section
32

2

HITACHI
Hitachi America, Ltd.' San Francisco Cenler • 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-012B/E
Item

Timer Output

Classification

Q

Does the timer (PRT) channel 0 provide a timer output
function?

MMU
DMAC
ASCI
CSI/O

;j Timer
Bus Interface
Interrupt

1/0 Port

z
o

Memory

@
(/J

Wait

A

Reset

No, PRT channell should be used for timer output.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD6471 BOX Hardware Manual

Other Data

Reference Q&A
\

Comment

I

HITACHI
Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

33

Type HD641180X, HD643180X, HD647180xI a&A NO.' QA641-013A/E
Item

Timer (PRT) Count Down Using External Clock

a

Classification
MMU

Can the PRT count down using the external clock?

DMAC
ASCI
CSIIO

"

Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait

A

Reset

No. The PRT can count down lIIsing only the tP clock
(divided by 20).

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X. HD643180X,
HD647180X Hardware Manual

Other Data

Reference a&A

Commentl

Section

34

2

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xl Q&A
Item

NO.' QA641-071A1E

Reload Timing

Classification

Q

When the timer data register (TMDR) counts down to 0, it is
automatically reloaded with the contents of the timer reload
register (RLDR).
How long does reloading take?

MMU
DMAC
ASCI
CSIIO

<.j Timer
Bus Interface
Interrupt
I/O Port
Memory

z
o

~
w

en

Wait
A

Reset

TMDR is reloaded with the contents 01 RLDR alter 20
cycles.



Low Power Mode
Refresh
Clock Generator
ASE

-

Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

I

HITACHI

Section

Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

2

35

Type HD641180X, HD643180X, HD647180xI Q&A NO., QA641-072NE
Item

TMDR Count Down

Classification

Q

MMU

While the timer data register (TMDR) counts down, when
timer count down enable (TOE) is reset to 0, what is the
status of TMDR and the reload register (RLDR)?

DMAC
ASCI
CSIIO

-J

Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
Reset

A
The TMDR and RLDR remain the same when the counter
stops.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

comment[

36

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-014B/E
Item

Bus State during Internal 1/0 Access

Q

Classification

1. What is the bus status during internal 1/0 access?

MMU

2. What happens if external 1/0 is assigned to the same
address as internal I/O?

ASCI

DMAC

CSIIO

Timer

,.j. Bus Interface
Interrupt
1/0 Port

Memory
Wait
A

Reset

1. Bus status during internal 110 access is as follows:

·
·

Data bus
-Read:
High impedance state
-Write:
Outputs data
Address bus
- Readlwrite: Outputs address

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

2. When an internal 1/0 address and an external 1/0
address overlap, bus status is as follows:
bus
· -DataRead:
-Write:

·

Reads internal 1/0; does not read
external 1/0
Outputs data to both internal and
external I/O

Address bus
- Readlwrite: Outputs address

Comment

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

I

HITACHI

Section

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· 8risbane, CA 94005-1819 • (415) 589-8300

2

37

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO., QA641-037NE

E Clock during Sleep Mode or Bus Release Mode

Q

Classification
MMU

Is it possible to extend E clock pulse width by inserting wait
states (Tw) during sleep mode or bus release mode?

DMAC
ASCI
CSI/O
Timer

-J

Bus Interface
Interrupt
I/O Port
Memory
Wan

A

Reset

No. Because WAiT input is ignored during sleep mode or
bus release mode, the E clock cycle cannot be extended.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

38

I

Section

HITACHI

2

Hitachi America, ltd.' San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO.' QA641-038A1E

E Clock Timing during DMA Cycles or Refresh Cycles

Q

Classification
MMU

What is the E clock output timing during the DMA or refresh
cycle?

DMAC
ASCI
CSIIO
Timer

...;

Bus Interface
Interrupt
1/0 Port
Memory
Wait

A

z
o

~

Reset
Low Power Mode

DMA access memory or 1/0 duration of E clock output high
is identical to the CPU. Table 1 shows output timing.

Refresh

Table 1 Output Timing

Clock Generator

C~cle

MemoryRfIN
110 read
1/0 write

Timing
T2 rising ( i) to T3 falling ( ,1)
First Tw rising (i) to T3 falling (,1)
First Tw rising ( i) to T3 rising ( i)

,

During refresh cycles, E clock output is held low.,

ASE
Software
Others
Application Manual
HD641180X. HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300

Sectkln

2

39

.ft

Type HD641180X, HD643180X, HD647180X
Item

I

Q&A

NO., QA641-046A1E

Data Sampling Timing during Memory Read

Q

Classification

Does the CPU sample data at the rising edge of T3 during
opcode fetch cycles and at the falling edge of T3 during
operand and data read cycles?

MMU
DMAC
ASCI

CSIIO
Timer

...j Bus Interface
Interrupt

1/0 Port
Memory
Wait
A

Reset

Yes, the CPU samples the opcode on the data bus at the
rising edge of T3 while it samples operands and data at the
falling edge of T3 (table 1).

Low Power Mode

Table 1 Sampling Timing

ASE

CPU C~cle
Opcode fetch cycle

T3 rising edge (i)

Data and operand fetch cycle

T3 falling edge (J,)

Sam~linlI

TiminII

Refresh
Clock Generator

Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

40

I

Section

HITACHI

2

Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

- ---------------

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-015B1E
Hem

Interrupt during MMU Operation

Q

Classification
MMU

How will the MMU be affected if an interrupt occurs during
its operation?

DMAC
ASCI
CSIIO
Timer
Bus Interface

"

Interrupt
1/0 Port

Memory
Wait

A

~

Ul

Reset

If an interrupt occurs during MMU operation, the interrupt
vector is relocated according to the MMU base register
programming. Therefore, the interrupt vector should be
defined with reference to MMU base register programming
(figure 1).
However, the interrupt vector can be located in common
area 0, which is always located in the same logical address
space.
FFFFFH

FFFFH

~~

..-- X: Interrupt vector

'x
4

Base
'x
Fxi~ase
regi~er (2)
I--

,X register (1)
OOOOOH
Physical address space
Logical address space
Figure 1 Interrupt Vector Generation during MMU
Operation

Comment

z

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

41

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO.' QA641-016A1E

Interrupt during DMA Operation
ClassHlcatlon

Q

MMU

How will the DMAC be affected if an interrupt occurs during
its operation?

DMAC
.ASCI
CSI/O
Timer
Bus Interface

...;

Interrupt
I/O Port
Memory
Wait

A

Reset

1. If an NfiifT occurs, DMAC operation Is disabled.
2. If an ffiIT or an internal interrupt occurs during burst
mode memory H memory DMA operation. the interrupt
is ignored.

3. If an ffiIT or an internal interrupt occurs during cycle steal
mode memory H memory DMA operation, the interrupt
is acknowledged and the interrupt sequence (CPU cycle)
and DMAC read/write (DMACcycle) are executed as in
figure 1.
DMA

CPU

DMA

~

Interrupt read
wr~e
acknowledge
Figure 1 Interrupt during Cycle Steal Mode DMA
read

Comment

Section

42

2

write

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X. HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

I

HITACHI
Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94Q05-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A NO-l QA641-017A1E

Item

000 Mode 2
Classification

Q

MMU

In Z80 000 mode 2, the LSB of the lower vector in the 16bit vector address (Ao) is always O.

DMAC

In the HD647180X, is the LSB of the lower vector (Do)
automatically set to 0 in 000 mode 2?

CSI/O

ASCI
Timer
Bus Interface

.J

Interrupt
1/0 Port

Memory
Wait
Reset

A
No, in Z80 000 mode 2, the LSB of the lower vector is not
automatically set to O. The Z80 data book explains that the
LSB (Ao) must be set to O.
In HD647180X 000 mode 2, the LSB of the lower vector
(Do) must be set to 0 since 000 mode 2 requires a 2-byte
vector.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

However, even if the LSB of the lower vector (Do) is set to
1, the interrupt sequence is executed correctly.

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

43

Type HD64118PX, HD643180X, HD647180xI Q&A
Item

NO., QA641-018A1E

NMI during Interrupt Acknowledge Cycle

Q

Classification

Is NMI acknowledged during the interrupt acknowledge
cycle, such as for TNT?

MMU
OMAC
ASCI
CSIIO
Timer
Bus Interface

..J Interrupt
1/0 Port

Memory
Wait
A

Reset

Yes, one instruction (excluding EI and 01 instructions) is
executed after the TNT acknowledge cycle, then the NMI
, acknowledge cycle starts.
The NMI response sequence during the NMT acknowledge
cycle is the same.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

Section

44

2

I

HITACHI

Hitachi Ameiica, Ltd.' San Francisco Center· 2000 Sierra Point PkWy~' Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-019NE
Item

Interrupt after Reset
Classification

Q
Is NMT or

m

MMU

acknowledged immediately after reset?

DMAC
ASCI
CSI/O
Timer
Bus Interface

'>l

Interrupt
I/O Port
Memory

z

o

tw

CIl

Wait
A

Reset

No, for three cycles immediatley after reset (power-on reset
cycle), NMT and lJ'iJT are disabled.
After these three cycles, the first instruction is executed and
interrupts are enabled. Figure 1 shows the timing.

Low Power Mode
Refresh
Clock Generator
ASE
Software

¢

Others

,

RESET~~

Power-on reset

..

:

Application Manual
Opcode fetch
(restart from
OOOOH), interrupts
enabled

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Figure 1 Power-On Reset Timing
Note: NMT is latched immediately after the power-on reset
cycle.
Comment

Reference Q&A

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

45

Type HD641180X. HD643180X. HD647180xI Q&A No.1 QA641-020B/E
Item

Interrupt during Refresh Cycle
Classification

Q
Is an interrupt (/IJMl or TliIT) acknowledged during refresh
cycles?

MMU
DMAC
ASCI
CSIIO

Timer
Bus Interface

,j Interrupt
1/0 Port

Memory
Wait
A

Reset

No. interrupts are ignored during refresh.cycles. However.

Low Power Mode

/IJMl is acknowledged immediately after refresh cycles
during instruction execution because /IJMl is edge sensitive.
Figure 1 shows /IJMl acknowledge timing after refresh cycle.

Refresh
Clock Generator
ASE

¢

....: :.-

=x.
Machine
cycle
NfVf[

~:

:~

X:
Refresh
cycle

~:

....:

:~

Software
:~

X Last machine xt=

NfVf[

cycle

I

acknowledge
cycle

Others
Application Manual
HD641180X. HD643180X.
HD647180X.Hardware Manual
Other Data

Figure 1 Refresh Timing
TNT (TNTO.TliITl • and TNT2) is ignored during refresh cycles.
If TfJT remains active after the refresh cycle. it is
acknowledged during the instruction just after refresh.

Reference Q&A

Commentj

46

Section

HITACHI

2

Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-021B/E
Item

ffiiAT Acknowledge

Q

Classification

Is ffiiifT acknowledged if it occurs during the timing
sequence in figure 1?
:~

Last machine cycle
T3
: T,
T2

.:

MMU
DMAC
ASCI
CSI/O
Timer

0

Bus Interface
Nt.JIl

:

,

l'JM1 sample
timing

;j Interrupt
I/O Port

tNMIW
(more than 120 ns)

Memory

Figure 1 NMTTiming

Wait

A

Reset

Yes, if tNMIW (ffiiifT pulse width) is 120 ns or more, NMT is
sampled and NMT acknowledge cycle begins after the last
MC (machine cycle)
If the ffiiifT is asserted low for tNMIW or longer between 1
and 2 in figure 2, it will be sampled at the falling edge of the
clock marked 2.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Current
instruction~

:..

Next instruction

Application Manual

.:

0

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

1

2

Figure 2 NMTTiming
Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

47

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-047A1E
Item

Interrupt Acknowledge Timing after EI Instruction Execution

Classification

Q

MMU

When is an interrupt acknowledged after an EI instruction?

,

DMAC
ASCI
CSIIO'
Timer
Bus Interface

..;

Interrupt
1/0 Port

Memory
Wait
Reset

A
Maskable interrupts (lNT0, etc.) are acknowledged in the
last machine cycle .of any instruction cycle other than EI.

Low Power Mode

Note that no interrupts can be acknowledged during EI
instruction execution. Therefore, if an interrupt occurs
immediately before or during an EI instruction cycle, it is
acknowledged after the end of ihe RETI instruction cycle
following the EI instructio(1.

Clock Generator

Refresh
ASE
Software
Others

Application Manual

For example:

HD641180X, HD643180X,
HD647180X Hardware Manual
~

Other Data

Interrupt request

EI
RETI ...., Interrupt request acknowledged during this
instruction
(Interrupt acknowledge cycle)

Reference Q&A

Comment \

Section
48

2

HITACHI
Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra PoinIPkwy.· Brisbane, CA 94005~1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A No·l QA641-048A1E
Item

Interrupt Sampling during Block Transfer Instruction Execution
Classification

Q

MMU

Normally, the CPU samples interrupts at the falling edge of
the 41 clock pulse prior to state T3 or Ti in the last machine
cycle.

DMAC
ASCI

When does the CPU sample interrupts during a block
transfer instruction which may require a hundred or more
machine cycles?

CSI/O
Timer
Bus Interface

--J

Interrupt
I/O Port
Memory

z

o

~

(J)

Wait
A

Reset

The CPU samples interrupts at the falling edge of the 41
clock pulse prior to state T 3 or Ti in the last machine cycle
of each one byte transfer (figure 1).
Interrupt acknowledge cycle

-

(n -1 )th byte
transfer cycle

o JlIl
Interrupt

n-th byte transfer cycle

MC5

\

~C6l

~
T1 T2 T3 T1 T2 T3 T1 T2 T T1 T2 T Ti Ti lJl

Interrupt
sampling

Low Power Mode
Refresh
Clock Generator
ASE
$oftware
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Figure 1 Interrupt during Block Transfer
Reference Q&A

Commentl

HITACHI
Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

49

Type HD641180X. HD643180X. HD647180xl Q&A No.1 QA641-049A1E
Item

Interrupt during SLP Instruction Cycle

Q

Classification

What is the CPU status when an interrupt occurs during
SLP instruction execution?

MMU
DMAC
ASCI
CSI/O
'Timer
Bus Interface

.J

Interrupt
1/0 Port

Memory
Wait
A

Reset

How the CPU operates when an interrupt occurs during
SLP instruction execution depends on whether it is the
HD647180X. The different responses are shown on the
next page.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

Comment

50

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type
Item

QA641-049A-2/E
Interrupt during SLP Instruction Cycle

A

SLP fetch cycle

T1

Interrupt

T2

Ta

: Sleep mode; Interrupt acknowledge cycle

.i~

: T1

.:~

T2

: T1

T2

U
z
o

Address

2nd SLP opcode address

Next address

t3w

CIl

7FFFFH
Figure 1 HD647180X SLP Timing
When an interrupt is sampled during an SLP instruction cycle, RACT is asserted low
for 1 clock state, and the address bus outputs FFFFFH.

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Section

2

51

Type HD641180X, HD643180X, HD647180xl Q&A
Item

NO., QA641-050A/E

TNTo Mode 0
Classification

Q
If the CALL instruction (three-byte instruction) is executed
during TNT0 mode 0 acknowledge cycle, the CPU cannot
return from the interrupt service correctly. Why is this?

MMU
DMAC
ASCI
CSIIO
Timer
Bus Interface

..J Interrupt
110 Port
Memory
Wait

A

Reset
Low Power Mode

TNT0 mode 0 operates as follows:
1. Stacks PC contents by an instruction, usually (one-byte)
RST, fetched during lNT0 mode 0 acknowledge cycle
2. Stops incrementing the PC during TNT0 mode 0
acknowledge cyote
3. Executes instruction fetched from data bus during
interrupt acknowledge cycle
However, if the (three-byte) CALL instruction, which
requires three machine cycles to fetch including the
operand, is executed during TNT 0 mode 0 acknowledge
cycle, PC increment stops only during interrupt
acknowledge cycle (one machine cycle) and is incremented
by 2 during the rest of the CALL instruction (operand fetch).
As a reSUlt, PC + 2 is stacked as the return address.
Therefore, decrement the stacked PC value by 2 in
software to return from the interrupt correctly.
Comment

52

Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

I

Section

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Type HD641180X. HD643180X. HD647180xI Q&A No.1 QA641-0S1A1E
Item

miff Interrupt Sampling Timing

Q

Classification

miff is sampled at the falling edge of a cp clock state prior to

MMU

T3 or Tj in the last machine cycle of each instruction.

DMAC

1. When is miff sampled if the last machine cycle is an
internal Ti cycle?

ASCI

2. How about llilT?

Timer

CSIIO
Bus Interface

..J Interrupt

z

1/0 Port

Q

Memory

~I/J

Wa~

Reset

A
Both miff and 1fJT are always sampled at the falling edge of
a cp clock pulse prior to state T3 or Ti of the last machine
cycle. The NfVlT sampling is not affected by the number of
internal Ti cycles (figure 1).

Instruction cycle

,~

T3

Tl

T2

T3

Ti

.,.

Interrupt
acknowledge
cycle

: Tj

: Tj

Tl

~~
: Sampling

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X. HD643180X.
HD647180X Hardware Manual
Other Data

'...........--J
Ti prior to Ti of last machine cycle

Figure 1 Interrupt Sample Timing during TI

Comment

Reference Q&A

I

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Section

2

53

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-052A1E
Item

Status Bit during TRAP

Q

Classification

1. What happens if an additional TRAP occurs before the
INT/TRAP control register TRAP bit is cleared?

MMU

2. What is the status of the TRAP and UFO bits in this
case?

ASCI

DMAC

CSI/O
Timer
Bus Interface

..,j

Interrupt
I/O Port
Memory
Wait

A

Reset

1. An additional TRAP interrupt occurs.

Low Power Mode

2. The TRAP bit remains 1 since it can be cleared only by
software.

Clock Generator

The UFO bit remains unchanged since it cannot be
modified while the TRAP bit = 1.

Refresh

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

I

Comment UFO bit: Indicates if TRAP occured in 2nd or 3rd opcode fetch cycle:
UFO = 0: TRAP occurred in 2nd opcode fetch cycle
UFO = 1: TRAP occurred in 3rd opcode fetch cycle

54

Section

HITACHI

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Type HD641180X, HD643180X, HD647180xI Q&A No.
Item

I QA641-053A1E

PC Stacking during TRAP

Q

Classification
MMU

Why is the stacked PC value different for TRAP occurrence
during second opcode fetch and during third opcode fetch?

DMAC
ASCI
CSIIO
Timer
Bus Interface

"

A
Table 1 summarizes CPU operations when TRAP occurs
during the second and third opcode fetches.

Interrupt
1/0 Port

Memory

z

o

@
en

Wait
.Reset
Low Power Mode

Table 1 CPU Operations during TRAP

Refresh

3

TRAP during Second
0E!code Fetch
Status
PC
TRAP
PCoccurrence
Internal
PC
operation
PCStack

4

-

Machine
C~cle

1
2

-

TRAP during Third
0E!code Fetch
Status
PC
TRAP
PC
occurrence
Memory
read
pc=
Internal
oQeration
PC+ 1
Stack
PC-1

il

Clock Generator
ASE
Software
Others
Application Manual

Other Data

When the TRAP occurs in the second opcode, the CPU
stacks the PC for the undefined opcode's location.
When it occurs in the third opcode, the CPU stacks PC - 1
for the undefined opcode's location.
Comment

Reference Q&A

I

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Section

2

55

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-054A1E

Nfii1T during DMA Transfer

Item
Q

Classification
MMU

What happens to DMAC after Nfii1T assertion?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt

'"

I/O Port
Memory
Wan

A

I

Reset

When N1iifT is asserted low during DMA transfer, the DMA
transfer ends at the end of the current DMA cycle.

Low Power Mode

However, note that the fiJfiill acknowledge cycle begins at
different times, depending on the CPU status before DMA
transfer (figures 1, 2, and 3). In addition, Nfii1T is sampled
twice to stop the DMA cycle and start the Nfii1T acknowledge
cycle.

Clock Generator

DMAC operations can be restarted by writing to the
corresponding channel's DE bit.

N1iifT acknowledge cycle timings are shown on the next

Refresh

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

pages.

Reference Q&A

Comment

56

I

Section

HITACHI

2

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Type HD641180X, HD643180X, HD647180X
Item

NMT during DMA Transfer

A
1. When DMA transfer starts during instruction execution cycle
a. When the DMA cycle starts during the instruction execution cycle, before the last
machine cycle (T1, T2, and T3) of instruction A, NMT is sampled at the falling
edge of T2 in the last machine cycle of A (figure 1).
Reset of
NMI acknowledge
cycle

DMAcycie

z
o
OREO

NMI sampling to
stop DMA cycle

sampling

NUl sampling to start NMI
acknowledge cycle

~

Figure 1 DMA Cycle Starting Before Last Machine Cycle
b. When the DMA cycle starts during the instruction execution cycle, before the last
internal cycle (Ti) of instruction A, NfiilT is sampled during the DMAcycle
(figure 2).

DMAcycle

sampling

NUl acknowledge cycle

NMI sampling to start NMI
acknowledge cycle
NUl sampling to
stop DMA cycle

Figure 2. DMA Cycle Starting Before Last Imernal Cycle

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Section

2

57

T}'pe HD641180X, HD643180X, HD647180X
f\1K,U during DMA Transfer

Item

A
2. When DMA transfer starts at the end of the instruction execution cycle, fJfVff is
sam!)led at the next falling edge of T2 or Ti of the last machine cycle of the next
instruction, B (figure 3).

DRE0r-

DMAcycie

ell

NMT sampling to
stop DMA cycle

NMT sampling to start m;u
acknowledge cycle

OREO
sampling

Figure 3· DMA Cycle Starting at End of Instruction Cycle

58

Section

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Type H0641180X. H0643180X. H0647180xl Q&A No.1 QA641-055A1E
Item

ORE'Oi and fiJMT

Q

Classification
MMU

What happens to DMAC operation if fiJMT is asserted low
while the DMAC operates under the control of the ORE'Oi
pin?

DMAC
ASCI
CSI/O
Timer
Bus Interface

,J

Interrupt

z

1/0 Port

o

Memory

en

i=

frl

Wait
A

Reset

DMAC operation is suspended and fiJMT is sampled with the
timing shown in figure 1.

m.u acknowledge
"I~PU cyc~ I~MA cYCI:'I~PU cyc~I"

t

DREOi

cycle

"1"-

~ Not accepted

Sampling

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

m.u

'-1
Figure 1 DMA Cycle Stopped by JiDJT

HD641180X. HD643180X.
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

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Section

2

59

Type HD641180X, HD643180X, HD647180X Q&A No.
Item

I QA641-055A-2/E

lJR"EO"i and N"fi,f[

A
Note that if lJR"EO"i and N"fi,f[ are asserted simultaneously, N"fi,f[ sampling has priority
(figure 2).
Instruction cycle
(last machine cycle)

NIiil1 acknowledge
cycle

~~J\hn
NIiil1
Figure 2

60

\J.--.l
'OREOi and m.u Conflict

Section

HITACHI

2

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Type HD641180X, HD643180X, HD647180xI Q&A NO.' QA641-056A1E
Item

Internal Interrupt Sampling liming
Classification

Q

MMU

External interrupts are sampled at the falling edge of state
T2 or Ti in the last machine cycle.

DMAC

When are internal interrupts sampled?

ASCI
CSIIO
Timer
Bus Interface

;j Interrupt
1/0 Port

Memory

z
o
~
w

Cf)

Wait
Reset

A
During a DMA cycle, internal interrupts from sources like
DMAC, ASCI, timer, and CSIO are not sampled.
They are sampled at the falling edge of state T2 or Ti in the
last machine cycle of the instruction cycle following the
DMA cycle (figure 1).

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300

Section

2

61

Type
Item

QA641-056A-2/E

Intemallnterrupt Sampling TIming

A

I

I

I

•

st=t~~ .~ DMA read ~ DM~ wrfte ~r--'lT--I. '-_"--_

:...

..

DMA transfer

(last 1-byte transfer~
DMAC
interrupt
request
(active low)

~'...

~'

CPU operation.
(only one instruction:

...

Interrupt
acknowledge

L.~·'i-___is_ex_e_cu_t_ed_)_-r:_---'~Ie
!
•
,.

•
,.

Figure 1 Internal Interrupt Sampling

Section

622

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Type HD641180X, HD643180X, HD647180xI a&A No.1 QA641·057 AlE
Item

TfJTA Signal Generation

a

Classification

The HD64180 can be interfaced to the 8259 to control 110
interrupts.

MMU

1. How can we generate an TI'JTA signal to be input to the
8259 from the HD64180?

ASCI

2. Are there any precautions?

Timer

DMAC

CSIIO

Bus Interface

.J

Interrupt

z

110 Port

o

Memory

@
(/)

Wait

A

Reset

1. Three TNTA signal pulses must be input when the 8259 is
used to control interrupts:
a. One TNTA pulse for opcode fetch
b. Two TNTA pulses for operand fetch

Low Power Mode
Refresh
Clock Generator
ASE
Software

The INTA pulse for opcode fetch can be produced by DR
and TOE. The TfJTA pulse for operand fetch can be
produced by 11U.
This interface is the same as for Z80 and 8259.
Figure 1 shows an example of an TNTA signal generation
circuit.

Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference a&A
QA641-050A
Comment

I

This circuit is for reference only. Check logic and timing carefully for your application.

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Section

2

63

\

Type HD641180X, HD643180X, HD647180X
Item TfiITA Signal Generation

A
LS06

11'iITA
LS32

(8259)

DR
QEWR

HD643180

1C

2G
TIl

ME

TOE
RO

B
A

WR

2'71

MEAD

lY

170WR

lY1

170lm

Figure 1 TfiITA Signal Generation Circuit Example
2. Precautions
• This circuit cannot be used when the DMAC is used in the system.
• When signal"Rn is used to generate the TfiITA signal for operand read (1b above)
TOE must be used to avoid data conflict between VO and memOry (note 1 in
figure 2).
• In lNTo mode 0, if the RST instruction is executed during its acknowledge cycle,
the PC is put on the stack. If a CALL instruction is executed, PC + 2 is put on the
-stack.

64

Section

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Type HD641180X. HD643180X. HD647180X
Item

Tf\JTA Signal Generation

A

1

TlilTo mode 0
Internal cycle
Stack
acknowledge cycle CALL instruction
(CALL instruction fetch)
operand read
(high)

~,--_PC_ _'CJ§J PC+1

Stack
(low)

~

INTOLJ

Start address

z
o

hlen

LlR - - - ,

ME ----------------,
IOE ------,
Note 1

...

ro------~C~~~---~·-~~)-------,LJ

WR ----------------------------~

.....JIL.JLJ

~

INTA - - - : '_ _

Note 2

CCJ)

Notes: 1.RD input to memory pulled high to
prevent bus conflict.
2.RD input to INTA pulled high to prevent
8259 malfunction.

Figure 2 Tf\JTATlmlng

HITACHI

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2

65

Type HD641180X, HD643180X, HD647180xT Q&A No.1 QA641-073A1E
Item

Interrupt Request during HALT Opcode Fetch

Classification

Q

Can the CPU acknowledge the interrupt request during
HALT opcode fetch?

MMU
DMAC
ASCI
CSI/O
Timer
Bus Interface

~ Interrupt
I/O Port
Memory
Wait

A

Reset

Yes. When interrupt enable flag 1 is set to 1, the CPU will
acknowledge the interrupt request.

Low Power Mode
Refresh
. Clock Generator
ASE
Software
Others

Application Manual

Other Data

Reference Q&A

Comment

Section

66

2

I

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO.' QA641-074A1E

Sample Mode Programming Pins' Levels

Q

Classification
MMU

1. When does the CPU sample the level on the mode
programming (MP) pins?

DMAC

2. Is it possible to change the CPU mode during operation?

ASCI
CSIIO
Timer
Bus Interface
Interrupt

-.J 1/0 Port
Memory

z
a

hlen

Wait
A

Reset

1. The CPU samples the MP pins' levels at the. rising edge
of RESET.

Low Power Mode

2. No. It is impossible to change the CPU mode during CPU
operation. (CPU does not check mode pins' levels.)

Clock Generator

Refresh
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

Comment

I

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Section

2

67

Type HD641t80X, HD643180X, HD647180xl Q&A No.1 QA641-075A1E
Item

Change from Input to Output

Q

Classification
MMU

What does the I/O port output just after it changes from
input to output?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt

.J

I/O Port
Memory
Wait

A

Reset

The I/O ports output depends on the contents of the output
data register (OOR). If the data direction register (ODR) is
set to 1 and the OOR is not set to output level data, the 1/0
port outputs undefined data. Therefore, put valid data in the
ODR before setting the 'DOR to 1.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

68

I

Section

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Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-076NE
Item

I/O Port Status in Sleep Mode

Q

Classification

What is the status of the I/O port during sleep mode?

MMU
DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

..J I/O Port
Memory

z
o

hlen

Watt
A

Reset

The I/O port holds its output levels when the CPU enters
sleep mode.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

CommentJ

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Section

2

69

Type HD641180X, HD643180X, HD647180xI Q&A NO.1 QA641-077A!E
Item

Port G

Q

Classification
MMU

Can port G be left open?

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

..J 1/0 Port
Memory
Wait
A

Reset

No. Connect port G to Vee or GND through a resistance.

Low Power Mode
Refresh
Clock Generator
. ASE
Software
Others
Application Manual

Other Data

Reference a&A

Comment

Section

70

2

I

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Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-120AlE
Item

Notice at alternating Port A's function
Classification

Q
How can we alternate Port A's function?

MMU
DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

~ 1/0 Port
Memory

z

o

~
w

(/)

Wait
Reset

A
Port A pins can also be used as ASCI channel 1 pins or
DMA channel 1 pins. If you want to use Port A as ASCI ch 1
pins or DMA ch 1 pins, please program DDRA after DERA.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

Comment

I

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Section

2

71

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-078A1E
Item

RAM Relocate Area

Q

Classification
MMU

Is it possible to locate the external memory to the RAM
relocate area?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
I/O Port

.J

Memory
Wait

A

Reset

Yes, it is possible to locate the external memory in any
physical address except for the internal RAM (or ROM)
areas.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

commentT

72

Section

HITACHI

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Type HD643180X, HD647180X
Hem

I

Q&A

NO., QA641-121A1E

Inserting Wait State to Internal ROM

Q

Classification
MMU

When internal ROM is accesed, are wait states inserted
according to the programmed value in operating mode 2?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
I/O Port

.J

Memory
Wait

z
o

~

Reset

A
Yes, wait states are inserted for internal ROM.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

Other Data

Reference Q&A

Comment

I

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Section

2

73

Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO., QA641-022B/E

WAIT Insertion during Refresh Cycle

Q

Classification
MMU

Can WAIT cycles be inserted during refresh cycle by
activating the WATT input (figure 1)?
TR
cjl

DMAC

TR

TIW

ASCI
CSI/O

,

Mach~

Refresh cycle

--

I

I

WAIT

~ineCycle

Timer
Bus Interface
Interrupt

Figure 1 Walt dzurlng Refresh

1/0 Port

Memory
A

..J Wait

,

Reset

No, WAIT input is disabled during the refresh cycle.
However, the refresh cycle can be programmed to two or
three cycles by setting the REFW bit in the refresh control
register accordingly (figure 2).
7

6

IREFE

IREFW I

5

4

3

2

1

0

§VC1 §VCO I
I
I
I
o = Refresh disabled, 1 = refresh enabled
o = No wait during refresh,
1 = 1 wait inserted during refresh
CVC1,CVCO: Refresh cycle interval

REFE:
REFW:

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD6471 BOX Hardware Manual

Other Data
Figure 2 Refresh Control Register
Refresh cycles occur every 10 clock cycles and last for 3
clock cycles after RESET.

Comment

74

Reference Q&A

I

Section

HITACHI

2

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Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-023B/E
Item

WAIT Function at 110 Access

Q

Classification
MMU

Is the WAIT state (Tw) always inserted during 110 access?

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

110 Port
Memory

..j
A

z
o

~

(f)

Wait
Reset

Yes, at least one wait state is inserted during external 110
access.
During on-chip 110 access, zero to four wait states are
automatically generated, depending on the status of CPU
and on-chip 110 (ASCI, CSIIO, PRT DATA register access).
For internal 110 access, the value of the DMAIWAIT control
register is ignored.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others
Application Manual

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

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Section

2

75

Type HD641180X, HD643180X, HD647180X
Item

I

Q&A No.1 QA641-122A1E

Inserted Wait States

Classification

Q

How many wait states are inserted after the reset start in
the single-chip mode?

MMU
DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

110 Port
Memory

..j Wan
A

Reset

After reset, three wait states are inserted, depending on the
initial value.

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual

Other Data

Reference Q&A

Comment

Section

76

2

I

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Type HD641180X, HD643180X, HD647180xI d&A
Item

NO.1 QA641-024A1E

Power-On Reset Sequence

Q

Classification
MMU

How is the power-on reset sequence performed?

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt
1/0 Port

Memory

z
o

~

Wait
A

I

.J

Low Power Mode

Figure 1 shows the power-on reset sequence.

I

Reset

I Restart
Reset !ltate: Opcode fetch

Refresh
Clock Generator
ASE

III

Software

! More that 6 clock~cycles

Hi~h imDedance (

RESET
Ao-A19

Others
OOOOOH)

Restart address
Figure 1 Power-On Reset Sequence

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment
)

I

RESET pin should be low for more than 6 clock cycles.

HITACHI
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Section

2

77

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-058A1E
Item

Control Signal Status after Reset
Classification

Q

MMU

What is the status of the control signals after each reset?

DMAC
ASCI

CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait
A

-J

Reset

The RESET signal must be asserted for at least 6 states.
Table 1 shows the status of each control signal.

Low Power Mode

Table 1 Control Signal Status

Clock Generator

Control Slanal
Address bus
Data bus
Control signals (00, WR ME, TOE,
ST, DR, HALT, BUSACR, TEfID,l
E

!2

Status
High im~edance
High im~edance
High (1)
Low (0)
Clock out~ut

However, if "RESET is not held low for at least 6 clock states
at power-on reset, the state of these signals is undefined.
For external reset, each signal remains unchanged until it is
reset.

Refresh

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A
QA641-024A

comment/

78

Section

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Type HD641180X, HD643180X, HD647180XI Q&A No.1 QA641-025A1E
Item

Bus Status during Sleep Mode
Classification

Q
What is the bus status when the SLP instruction is
executed?

MMU
DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt
1/0 Port

z
o

Memory

@

Wait

Cf)

Reset

A

..J Low Power Mode

Table 1 shows the bus status.

Refresh

Table 1 Bus Status

Clock Generator
Sianals
Address bus
Data bus
Control signals

Status
High (Ao-A'g = FFFFFH)
High impedance
Inactive

ASE
Software
Others
Application Manual
HD641180X HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
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Section

2

79

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-026AJE
Item

Sleep Mode and System Stop Mode

Q

Classification
MMU

What is the difference between sleep mode and system
stop mode?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
I/O Port
Memory
Wait

A

Reset

-J

Table 1 shows the major differences.
Table 1 Sleep Mode and System Stop Mode

Low Power Mode
Refresh
Clock Generator

Mode
Sleep

Function
CPU stop

System
stop

CPU and internal
1/0 stop

Exit

•
•
•
•

Interrupt (internal/external)
Reset
Interrupt (external)
Reset

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

80

I

Section

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Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-027B/E
Item

Recovery from System Stop

Classification

Q

MMU

What is the system status after recovery from system stop
mode?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt

110 Port
Memory

z

o

§
C/)

Wait

A

Reset

System stop mode is a combination of sleep and 1/0 stop
modes.
The HD64180 exits system stop mode on detection of ffiVlT
or TNT extemal interrupts only, except for RESET.
If interrupts are globally disabled (IEF1 = 0), instruction
execution begins with the instruction following the SLP
instruction.
If interrupts are globally enabled (IEF1 = 1), the appropriate
normal interrupt response sequence executes.
However, 110 stop mode continues until the 110 stop bit is
set to 0 after recovery from system stop mode.

"

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
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Section

2

81

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641 -028B/E
Item

System Standby Function
Classification

Q
Does the HD64180 have a system standby function (stop
clock) to reduce power consumption?

MMU
DMAC
ASCI
CSI/O

Timer
Bus Interface
Interrupt

110 Port
Memory
Wait
A

Reset

No, clock stop function is not provided. Minimize the clock
frequency to reduce power consumption. However, if you
stop the clock completely, MPU operation and data in the
registers are not guaranteed.

..j Low Power Mode
Refresh
Clock Generator
ASE

To minimize power consumption, we recommend:
1. Store all register information into battery backed-up RAM

Software
Others
Application Manual

2. Stop power supply to HD64180

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

. Section

82

2

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180XI Q&A No.1 QA641-059AfE
Item

Interrupt Sampling in Sleep Mode

Classification

Q

MMU

1. Can an interrupt be accepted in sleep mode?

DMAC

2. If so, when is sleep mode cancelled?

ASCI
CSIIO
Timer
Bus Interface
Interrupt

110 Port
Memory
Wait
A

Reset

1. The CPU accepts interrupts at the falling edge of the $
clock pulse one pulse after it enters sleep mode
(figure 1).
2. Sleep mode is cancelled one and a half $ clock pulses
after an interrupt is accepted. The CPU status is
recovered according to the IEF flag status:

"

Low Power Mode
Refresh
Clock Generator
ASE
Software
Others

• IEF flag

= 1:

CPU begins an interrupt acknowledge
cycle

• IEF flag

=0:

CPU begins an NfiilT acknowledge cycle or
executes the instruction following the SLP
instruction for maskable interrupts

Application Manual

, H0641180X, HD&43180X,

HD647180X Hardware Manual

Qt.her,Oata
,

i

Reference Q&A

,
,

, 'commentl

HITACHI
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Section

2

83

Type
Item

Interrupt

Sampling in Sleep Mode

A

SLP instruction
cycle

Interrupts can
be sampled

Interrupt
acknowledge cycle

Sleep
mode

Interrupt

1.56

1¢

Figure 1 Timing of Interrupt during Sleep Mode

84

Section

HITACHI

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Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-029NE
Item

Dynamic RAM Refresh during DMA

Q

Classification
MMU

Is DRAM refreshed during internal DMA operation?

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt
I/O Port
Memory
Wait

A

Reset
Low Power Mode

Yes, refresh cycles are inserted during internal DMA cycles.
The refresh controller does not distinguish DMA cycles from
CPU cycles.
Dynamic RAM refresh is performed at the end of the
machine cycle during both CPU and DMA cycles. The
interval and duration of the refresh cycle are programmable.

-J

Refresh
Clock Generator
ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

I

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Section

2

85

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-030B/E
Item

Dynamic RAM Refresh

Q

Classification
MMU

1. Is the HD647180X refresh controller different from the
Z80 refresh controller?

DMAC
ASCI

2. What is the function of the R counter?

CSI/O

Timer
Bus Interface
Interrupt

110 Port
Memory
Wait
A

Reset

1. Yes, the refresh controller is different from the zao
refresh controller. Refresh cycles are inserted or
supressedby software. Also, the interval (10+-S0cp) and
length (2<1>-3cp) of the refresh cycle are programmable.
The refresh address (8-bit address) is output at AcrA7
(figure 1).
Me

... .....
I

Ret'tesh cycle

~

..

I

MC+1

Low Power Mode
...J

Refresh
Clock Generator
ASE
Software
Others
Application Manual

Address

X

REF

\

Ao-A7

X
I

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Figure 1 Refresh Example (refresh programmed to 3
cycles)
2. The R counter counts the number of CPU opcode
fetches. It has no relation to dynamic RAM refresh.
Comment

86

Reference Q&A
QA641-022B

I

Section

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Type HD641180X, HD643180X, HD647180xI Q&A
Item

NO.' QA641-060NE

Refresh Cycle Insertion
Classification

Q
Normally, a refresh cycle is inserted at the breakpoint of an
instruction cycle (machine cycle).

MMU

Is it possible to insert a refresh cycle between consecutive
internal machine cycles (Ti)?

ASCI

DMAC

CSI/O
Timer
Bus Interface
Interrupt

z

1/0 Port

o

Memory

C/)

t3w

Watt
Reset

A
Yes, a refresh cycle can be inserted between internal
cycles, and between internal and machine cycles (figure 1).
Internal Refresh Internal
MC'
cycle
cycle
cycle
MC'
~I"~I"
... 1.... ~I>4
T3

Ti

TR1

TR2

Ti

T1

Low Power Mode

~ Refresh
Clock Generator
ASE
Software



MC' . , ..
T3

Ti

Internal
cycle
Ti

Others

I

\

REF

.,

Application Manual

Refresh
cycle
....

TR

MC'

"'/4TR

T1

¢

REF

\

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

I

MC': Normal machine cycle ( h 12, (Tw)' and T3)

Reference Q&A

Figure 1 Refresh CyCle Insertion Point

commen~

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Section

2

87

Type HD641180X, HD643180X, HD647180XI Q&A

Item

NO.1 QA641-061A1E

EXTAL and cI>

Q

Classification

What is the relationship between EXTAL input and cI> clock
output when an external clock is input through EXTAL?

MMU
DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
A

Reset

clock changes synchronously with the falling edge of
EXTAL (figure 1).

cI>

~
-..:
-..:
Delay

EXTAl

Delay
¢

:~

iI

:~

!L

,
Delay: 40 ns typ (reference only)
Figure 1 External Clock

Low Power Mode
Refresh
...J Clock Generator

ASE
Software
Others
Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

88

I

SeJ:tion

HITACHI

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Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-062A1E
Item

cj) Clock Output Frequency Error

Q

Classification

Normally, cj) clock output frequency is one half of the crystal
oscillator frequency.

MMU

Why does cj) clock output frequency equal the crystal
frequency in our system?

ASCI

DMAC
CSI/O
Timer
Bus Interface
Interrupt
1/0 Port

z
o

Memory

~

§

Wait
A

Reset
Low Power Mode

How RESET and Tout 1 terminals are handled may effect cj)
clock output frequency. Therefore, take the following two
types of measures:
1. Check that the reset circuit design asserts the RESET
signal for at least six clock states.
2. Do not pull down Tout 1 (it is an output signal).

Refresh
Clock Generator

'"

ASE
Software
Others

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I
...

HITACHI
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Section

2

89

Type HD641180X, HD643180X, HD647180xl Q&A No.' QA641-123A1E
Item

cjl Pin Handling

Classification

Q

MMU

If cjl pin is not used, can it be connect capacitively to GND
(figure 1)?

DMAC

~
:J;

ASCI
CSI/O
Timer
Bus Interface

Figure 1 Unused cjl Pin

Interrupt
I/O Port
Memory
Wait

A

Reset
Low Power Mode

Yes. The cjl pin can be connected to GND through a
maximum capacitance of 90 pF.

Refresh

..j

Clock Generator
ASE
Software
Others
Application Manual

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

90

I

Section

HITACHI

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point PkWy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD641180X, HD643180X, HD647180XI aiA
Item

NO.1 QA641-031 AlE

ASE Trace Function

a

Classification
MMU

How is ASE trace information displayed on the CRT?

DMAC
ASCI
CSIIO
Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait
Reset

A
After go or step command execution, the trace buffer
pointer indicates the last trace data location. Specify display
numbers with negative values until the pointer corresponds
to the trace pointer. After moving the trace buffer pointer
with the trace pointer command, you can specify the display
number with a positive value (figure 1).
Trace

lJ
buff"

Trace
bUffer;
Increment
pointer
by negative
value

i
Wf"ij
Trace

T~

pointer

'"",,

- -

isplay number
can be specified
by either positive
or negative
number

Figure 1 Displaying Trace Information

Comment

Low Power Mode
Refresh
Clock Generator

.J

ASE
Software
Others
Application Manual

H180AS01 User's
Manual
Other Data

Reference a&A

I

HITACHI
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Section

2

91

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-032A!E
Item

Dynamic RAM Refresh of ASE

Classification

Q
Dynamic RAM refresh depends on the refresh control
register programming.

MMU

If the dynamic RAM refreshed during the wait state for
command input when using ASE?

ASCI

DMAC

CSI/O

Timer
Bus Interface
Interrupt

1/0 Port
Memory
Wait
A

Reset

When ASE is used, dynamic RAM refresh is executed as
follows, depending on refresh control register programming:

Refresh
Clock Generator

1. Refresh enable: REFE = 1
If REFE bit is set to 1, dynamic RAM is refreshed while
ASE is waiting for command input.
2. Refresh disable REFE =

Low Power Mode

°

;j ASE
Software
Others

Application Manual

If REFE bit is set to 0, dynamic RAM is not refreshed
while ASE is waiting for command input. (But refresh
cycles are inserted during trace.)

H180ASOI User's
Manual

Other Data

Reference Q&A

Comment

92

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Section

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Type HD641180X, HD643180X, HD647180xI a&A No.1 QA641-033A1E
Item

Difference between RET and RETI Instructions
Classification

a

MMU

What is the difference between the RET and the RETI
instructions?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt

z

I/O Port

o

Memory

(J)

~

Wait
A

Reset

Both RET and RETI instructions return from a subroutine to
the main program. Both instructions have identical
functions.

Low Power Mode

However, RETI is normally used to return from an external
interrupt (000,001, or TNT2) service routine.

ASE

Since RETI is a two-byte instruction, peripheral devices
know the completion o.f the current interrupt service routine
during RETI execution, especially when using daisychain
(Z80 peripheral).
However, for external interrupts, especially daisychained
interrupts, the RET instruction is useful for identifying an
internal interrupt service routine.

Refresh
Clock Generator

"

Software
Others

Application Manual

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference a&A

Comment

I

HITACHI
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Section

2

93

Type HD641180X, HD643180X, HD647180XI Q&A
Item

NO.' QA641-034A1E

LD A, Rand LD R, A Instructions

Q

Classification
MMU

Can the refresh address be read by executing an LD A, R
orLD R, A instruction?

DMAC
ASCI
CSIIO
Timer
Bus Interlace
Interrupt

1/0 Port
Memory
Wait
A

Reset
Low Power Mode

No, the refresh address cannot be read by executing the LD
A, R or LD R, A instruction.
The HD64180 incorporates a dynamic RAM refresh
controller. But the R counter indicates the number of CPU
opcode fetch cycles and has no relation to dynamic RAM
refresh.

Refresh
Clock Generator
ASE

..J

Software
Others
Application Manual

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

94

I

Section

HITACHI

2

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Type HD641180X, HD643180X,HD647180xl Q&A No.1 QA641-035NE
Item

Processing Speed of S0200 Cross Assembler
Classification

Q

MMU

What is the processing speed of the cross assembler for the
S0200?

OMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
I/O Port
Memory
WaR

A

Reset

z

o

§

*

Low Power Mode

It is about 2.5 minutes per 1,000 steps (2.5 min/kstep)
(floppy disk based) on the S0200 for S180XAS6F (version
1.0).

Refresh
Clock Generator
ASE

-J

Software
Others
Application Manual

HD641180X, HD643180X,
HD647180X Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

95

Type HD641180X, HD643180X, HD647180xI Q&A No.1 QA641-036A!E
Item

LOIR Instruction

Classification

Q

What is the bus cycle status during LOIR instruction
execution?

MMU
OMAC
ASCI
CSI/O

Timer
Bus Interface
Interrupt
1/0 Port

Memory
Wait
A

Reset

Fourteen instruction cycles are repeated. The last execution
cycle (BC =0) is twelve cycles. That is:

.

BC ~ 0: fourteen instruction execution cycles are
repeated

. BC =0:

twelve instruction execution cycles are repeated

Low Power Mode
Refresh
Clock Generator
ASE

~ Software
Others

See figure 1.

Application Manual
HD641180X, HD643180X,
HD647180X Hardware Manual

Other Data

Reference Q&A

Comment

96

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Section

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2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

QA641-036A-2/E

Type HD641180X, HD643180X, HD647180X
Item

LDIR Instruction

A
LDIR (EDB ¢)
Operation

(HL)m ... (DE)m

BC r -l ... Be r
DEr+ 1 ... DEr
HL r+l ... HL r
Repeat until BC r = 0

Bus cycle

1st
opcode
fetch

DE

Ti

opcode
fetch

..

1st
opcode
fetch

Ti

/

'\

z
o

~
w

en

Execution cycle

,

opcode
fetch

opcode
fetch
/

Last execution cycle (BC = 0)
•.

1 machine cycle
Internal operation machine cycle

Figure 1

LOIR Instruction Timing

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Section

2

97

Type HD641180X, HD643180X, HD647180xl Q&A No.1 QA641-063A1E
Item

Extension Instructions (INO, OUTO)

Classification

Q

MMU

Are there any limitations when the INO or OUTO instructions
access external I/O?

DMAC
ASCI
CSI/O
Timer
Bus Interface
Interrupt
I/O Port
Memory
Wa~

Reset

A

Yes, the INO and OUTO instructions can only access the
lower 256 bytes of I/O space.

Low Power Mode

IN g, (c) and OUT (c), g instructions can access more than
256 bytes of I/O space (figure 1).

Clock Generator

Refresh

ASE

-J
FFFfH

~--------- --} Ao~",d bj

OOFFH

--- -- ----- -

-I

""'",d

Others

Application Manual

lNg, 10'"

:_I~~e:~~~ I~~___ ~~~~!?~ _
_OUT (c), 9

OOOOH

Software

110 space

Other Data

Figure 1 I/O Space Access
Reference Q&A

Comment

98

I

Section

HITACHI

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Type HD641180X, HD643180X, HD647180xl Q&A
Item

No.1 QA641-064NE

DEC (INC) and DAA Instructions

Q

Classification

Normally, the DAA instruction is executed to obtain BCD
data after ADD or SUB instruction execution.

MMU

Does the DAA instruction adjust the result after DEC (INC)
instructions?

ASCI

DMAC

CSI/O
Timer
Bus Interface
Interrupt
I/O Port
Memory

z
o

~

C/)

Wait
A

Reset

No, the DAA instruction does not support BCD adjustment
after DEC (INC) instructions.
DAA execution results depend on flag conditions. See table
1 for an example.

Low Power Mode
Refresh
Clock Generator
ASE

;j Software

Table 1 DAAExample

Others
Flag

Instruction
(Initial valuel
DECA
DAA

Acc
00
FF
F9 (FF+FA)

N

C

H

a

a
a

a

1
1

1

1
1

Application Manual
HD64180 Data Sheet
Other Data

Refer to the HD64180 user's manual for details.
Reference Q&A

Comment!

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589-8300

Section

2

99

Section
100 2

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415)589-8300

HD64180S NPU Network Processing Unit
Technical Q and A

Application Note
Preface
The HD64180S NPU (network processing unit) is a single-chip microcontroller that facilitates highspeed, low-cost processing of a variety of communication functions such as communication protocol
and other user-specified functions.
The HD64180S mainly incorporates the following on a single chip:
•
•
•
•

8-bitCPU
Multiprotocol serial communication interface (MSCI)
Asynchronous serial communication interface/clock-synchronous serial I/O port (ASCI/CSIO)
DMA controller

The HD64180S enables high-speed data transfer by taking over communication program processing
from the host CPU.
This LSI, for example, can be used in an auxiliary communication system for computer-to-computer
communication, or in the distributed control unit installed in an industrial robot
In addition, the HD64180S can be easily applied to any type of existing communication system
because it can interface with LSIs having conventional communication functions and can be
controlled by conventional communication programs.

How to Use This Technical Q&A Manual
This technical manual contains answers to questions that many users have asked regarding Hitachi
microcontrollers. It is intended to supplement the explanations in the current data books and user's
manuals. Thus, please use tbis manual together with the data books and user's manuals.
If any further questions arise as you use this manual and the products described, please do not

hesitate to get in touch with your nearest Hitachi semiconductor sales office.

HITACHI

Section

H~chi America, Ltd.' San Francisco Center· 2000 Sierra Paint Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

_

...... _ .. ........

2101

_._---------_._---------

Section

HITACHI

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102

Contents
MMU
Logical to Physical Address Translation ...........................QA64I-002B/E ..... 107

DMAC
DE (DMA Enable) Bit in DMA Status Register ...............QA641-004C/E .....
DWE Bit in DMA Status Register .....................................QA641-005A1E .....
Memory (specified in application program)-to-I/O
DMA Transfer ...................................................................QA641-00SAIE .....
Memory H 110 (ZSO Peripheral) DMA Transfer..............QA641-009B/E .....
DACK Signal Generation ..................................................QA641-042B/E .....
Ring Configuration during a Chained-Block Transfer ......QA64 1-097AlE .....
CRC Code Transmission during a Memory-to-MSCI
DMA Transfer ...................................................................QA641-09SA/E .....
DMAC Error Handling ......................................................QA641-099A1E .....

108
109
110
III
112
114
liS
116

z

o

~

lrl

MSCI, ASCIICSIO

(/)

DCD Pin and CDCD Flag .................................................QA641-044B/E ..... 117
Signal Direction ofTXCM Pin (l) ....................................QA641-100AlE ..... 119
Signal Direction ofTXCM Pin (2) ....................................QA641-101A1E ..... 120
AC Characteristics of Manchester Codes ..........................QA641-1 02A/E ..... 121
AC Characteristics of Receive FM Data ...........................QA641-103A1E ..... 122
RXRDYFlag .....................................................................QA641-104A1E ..... 123
CRC Error Handling ..........................................................QA641-105A/E ..... 124
Transmit Data Fixing .........................................................QA641- Hl6A1E ..... 125
Mark Output Modulation ...................................................QA641-107 AlE ..... 126
Idle Pattern Transmission ..................................................QA641-lOSAIE ..... 127
I/O Direction Setting of SYNC Line .................................QA641-109A1E ..... 128
Synchronization Using SYNC Line ..................................QA641-110AlE ..... 129
Phase Relationship between SYNC Line and Data ...........QA641-1 11AlE ..... 130
SYNC Codes for Byte Synchronous Mode .......................QA641-112AIE ..... \31
Data Insertion between Flags in Bit Synchronous Mode
...........................................................................................QA641-113 AlE ..... 132
Character Insertion in Bit Synchronous Loop Mode .........QA641-114AIE ..... 133
Address Field Check Usage ...............................................QA641-115AIE ..... 134
ADPLL Synchronization Pattem .......................................QA64I-116A1E ..... \35
Duty Cycle for ADPLL Operation ....................................QA641-117 AlE ..... 136
ADPLL Operation in Local Loop-Back Mode ..................QA641-11SA/E ..... \37

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

103

Timer
Timer Counting Operation Using Input Clock ..................QA641-013C/E ..... 138
Compare-Match Flag .........................................................QA641-119A/E ..... 139

Bus Interface
Bus State during Internal I/O Access ................................QA641-014B/E .....
Data Sampling Timing during Memory Read ...................QA641-046A/E .....
Address Bus Status during INTO Acknowledge Cycle
...........................................................................................QA641-079A/E .....
ST Output Timing in INTo Mode O...................................QA641-0SOA/E .....

140
141
142
143

Interrupt
Interrupt during MMU Operation ......................................QA641-015B/E .....
INTO Mode 2 .....................................................................QA641-017A/E .....
NMI during Interrupt Acknowledge Cycle .......................QA641-0 18A/E.....
Interrupt after Reset.. .........................................................QA641-019A/E .....
Interrupt during Refresh Cycle ..........................................QA641-020B/E .....
NMI Acknowledge ............................................................QA641-021B/E .....
Interrupt Acknowledge Timing after EI Instruction
Execution ...........................................................................QA641-047A/E .....
Interrupt Sampling during Block Transfer Instruction
Execution ...........................................................................QA641-048A/E .....
Interrupt during SLP Instruction Cycle .............................QA641-049B/E .....
INTo ModeO .....................................................................QA641-0SOA/E .....
NMI Interrupt Sampling Timing .......................................QA641-051A/E .....
Status Bit during TRAP .....................................................QA641-052A/E.....
PC Stacking during TRAP.................................................QA641-0S3B/E .....
NMI during DMA Transfer ...............................................QA641-0S4B/E .....
DREQi and NMI ................................................................QA641-0S5A/E .....
Internal Interrupt Sampling Timing ...................................QA641-056B/E .....
INTA Signal Generation ....................................................QA641-057B/E .....
Interrupt Priority ................................................................QA641-081A/E .....
Interrupt Request during HALT Opcode Fetch .................QA641-082A/E .....
ST Output Timing during Interrupt Acknowledge Cycle
...........................................................................................QA641-083A/E .....

144
145
146
147
148
149
150
151
152
153
154
155
156
158
161
163
164
167
168
169

Wait
Wait Function at I/O Access ..............................................QA641-023C/E ..... 170

Section

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104

Reset
Power-On Reset Sequence.................................................QA641-024B/E ..... 171
Control Signal Status after Reset .......................................QA641-058B/E ..... 172

Low Power Mode
Sleep Mode and System Stop Mode ..................................QA641-026B/E ..... 173
System Standby Function ..................................................QA641-028C/E ..... 174
Interrupt Sampling in Sleep Mode ....................................QA641-059B/E ..... 175

Refresh
Dynamic RAM Refresh during DMA ...............................QA641-029A/E ..... I77
Dynamic RAM Refresh (R Counter Function) .................QA64I-030B/E ..... 178
Refresh Cycle Insertion .....................................................QA641-060A/E ..... 179
Bus Release Mode and Refresh ..........:..............................QA641-095B/E ..... 180

z
o

Clock Generator

§

EXTAL Input and $ Clock Output ...................................QA641-061B/E ..... 181
$ Clock Output Frequency Error .......................................QA641-062A/E ..... 182
$ Pin Handling ...................................................................QA641-096A/E ..... 183

w

C/)

ASE
ASE Trace Function ......................... ,................................QA641-031A/E ..... 184
Dynamic RAM Refresh of ASE ........................................QA641-032A/E ..... 185

Software
Difference between RET and RETI Instructions ...............QA641-033A/E .....
LD A, Rand LD R, A Instructions ....................................QA641-034B/E .....
Processing Speed of SD200 Cross Assembler ..................QA641-035A/E .....
LDIR Instruction ...............................................................QA641-036A/E .....
Extension Instructions (INO, OUTO) .................................QA641-063B/E .....
DEC (INC) and DAA Instructions ....................................QA641-064B/E .....

186
187
188
189
191
192

HITACHI
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Section

2105

Section
1062

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

I Q&A

Type HD64180S
Item

NO~ 0A641-o02B1E

Logical to Physical Address Translation
Classification

Q
Can the MMU base register (MMU common base register
and MMU bank base register) be programmed so that
common area 1 overlaps with the bank area?

V

MMU
MSCI
ASCVCSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

Yes, depending on the MMU base register programming,
common area 1 and the bank area may overlap (figure 1).

FFFFH

r-~"m~~"
area 1

COOOH

4000H

~""~
~"(%

~j >CommOl
II18II 0

OOOOH

Software

Physical
address space

}- Common basE ~
rag (OFH) ,

Bank base
reg (11H)

(

-<

~~"
>~!'~~<

%"(~
~area ~

"

Others
1EFFFH

area 1

---,,-,,,"'

CommOl
II18II0

Clock Generator
ASE

Figure 1 Overlapping Common Areas
Logical
address space

Bus Interface

1CFFFH

Application Manual
HD64180S
Hardware Manual
Other Data

lBOOOH
15000H
04000H

Reference Q&A

Commentl

HITACHI
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Section
2107

'""-"---~---.----,----------,--~~

I

Type HD64180S
QlcA No.1 QA641-o04C/E
DE
COMA
Enable)
Bit
in
DMA
Status
Register
Hem

Classification

Q

MMU

When Nm' occurs, DE is reset to 0 and DMA operation is
disabled, passing control to the CPU.

MSCI
ASCVCSIO

1. How is DMA operation timing halted?

.J

2. How does DMA operation restart?

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

1. When Nm' occurs, the CPU takes control after the
current DMA cycle is completed (figure 1).

ASE

DE bit is reset to 0, !hen
DMA operation stops

Tl

III
RMI

T2

T3

··
··
i

Tl

··
·
·
... ·
:...
i

·...
~

: DMA read cycle

+

T2

Bus Interface
Clock Generator
Software
Others

T3

Tl

Application Manual

LJ
Ito

: DMA write cycle

...

HD64180S
HardWare Manual
Other Data
CPUcycte

(DMAstops)

Figure 1

m.;u Timing
Reference QlcA

2. To restart DMA operation, set DE bit to 1.
Comment

Section

108

2

I

HITACHI
Hitachi America, ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 '(415) 589-8300

I

Type HD64180S

Item

Q&A No·loA641-005A1E

OWE Bit in DMA Status Register
Classification

Q

MMU

What is the function of the OWE bit in the DMA status
register?

MSCI
ASCI/CS10

..J

DMAC
Timer
Wait
Refresh
Chip Select

z
o

Low Power Mode

hlen

Reset
A

Interrupt

The OWE bit, which enables write operation to the DE bit, is
necessary to prevent the DE bit from being affected by the
write operation to the other bits of the DMA status register.
The following gives a more specific description.

Bus Interface
Clock Generator
ASE
Software

Before writing to the EOT, EOM, BOF, or COF bit during
Others
DMA transfer, 1 must be written to the DE bit. However, if
the DMA transfer ends immediately before writing to the DE
Application Manual
bit, DMA transfer will undesirably resume when 1 is written
to the DE bit. The OWE bit prevents this, disabling any
HD64180S
unnecessary write operation to the DE bit.
Hardware Manual
Other Data

Reference Q&A

Comment!

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2109

I

Type HD64180$

Q&A No.1 QA641-008A/E

Item Memory (specified in application program)-to-1I0 DMA Transfer
Classification
Q
MMU

Is it possible to execute memory (specified in application
program)-to-I/O DMA transfer independently of the MMU
base register?

MSCI
ASCI/CSIO

...j

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt
Bus Interface

No, to execute memory (specified in application program)to-I/O DMA transfer correctly, one of the following two
conditions must be met:

Clock Generator

1..The physical source address is defined beforehand.

Software

.

ASE
Others

2. A common area contains the value of the base register
that corresponds to the physical source address.
Application Manual
If the DMA transfer is executed using only the logical
address, block transfer instructions can be used.

HD64180S
Hardware Manual
Other Data

Reference Q&A
/

Comment

I

,/
\

Section
110 2

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point PkWy.· Brisbane, CA 94005-1819 • (415) 589-8300

I

NO.'

Type

H064180S

Item

Memory H 1/0 (Z80 Peripheral) OMA Transfer

Q&A

QA641-009B/E
Classification

Q

MMU

When memory H 1/0 (Z80 peripheral) OMA transfer is
executed while UREa is programmed for level sensitivity.
OMA transfer does not complete correctly.
Are there any restrictions on OMA operation? (ROY signal
from Z80 peripheral is input to UREa of H064180S. with
one inverter inserted to invert the active-high ROY signal.)

MSCI
ASCI/CSIO

.,j

OMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

t

UJ

en

Reset
A

Interrupt

The zao peripheral ROY signal is negated during OMA write
cycle to the peripheral LSI. Therefore. if UREa is
programmed for level sensitivity. an additional OMA cycle
starts since ROY is negated after UREa sampling (figure 1).

·...T1

· T1
T3
·
·
;~
··

DMA read cycle

:
:
C\l

Address ~

ACK
l5REQ

(zao
peripheral

ROY
output)

.X

···
·

T2

...: ..

· T1
T3
·

DMA write cycle

T2

...:

·· Tw

·:

.XI

.X

Z

·

,

~

'-

~REO sampled

,/ .

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
H064180S
Hardware Manual
Other Data

Additional
DMAcycle

(If DREO is not negated here.

an additional DMA cycle starts)

Reference Q&A

Figure 1 DMA Timing
Comment

I Take one of three measures: 1) Program lJRE'Ci for edge sensitivity.
2) Insert a wait state during OMA write cycle to modify ROY response
timing. 3) Mask the UREa (ROY) Signal by the ACK signal.

HITACHI
Hitachi America. Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300

Section

2

111

Type HD64180S

I Q&A

NO~ QA641-042B/E

Item OACK Signal Generation
Classification

Q

MMU

How can the OACK signal be generated during channel 0
memory H external 1/0 DMA transfer?

MSCI
ASCI/CSIO
DMAC
I "

Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset
A

Interrupt

When extemalllO is accessed during a DMA cycle, the
external 1/0 address is output through the address bus. At
this time, the JOE signal and address output are decoded to
generate a 0ACI<-1 signal (figure 1, I

_

~--~

MC~2

~

~

(Only DMAC
accesses the I/O)
(DMAC and CPU
access the 1/0)

Figure 1 Circuit Example

··

.

DMA read cycle

I..

Ii>
Address

T1

DMA write cycle

~I"

T2

T3

z
o

...

~

C/l

·

:D<________-J:x~i.__________~:x===
..

IoE ----------------~~.. ,~----------~:./~~-----

..

~----------~:./~~-----

DACK-l
(j)

ST

----t\

i5ACK-2
~

Figure 2 Timing Chart

HITACHI
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Section

2

113

Type HD64180S

I Q&A

NO~QA641-097NE

Item Ring Configuration during a Chained-Block Transfer
Classification

Q

MMU

Is it possible to configure a ring, by using the function that
allows a descriptor to specify n number of buffers during a
DMAC chained-block transfer?

MSCI

..

"

ASCIICSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A

Yes. Load the starting address of the descriptor
corresponding to the first buffer into the chain pointer
corresponding to the n-th buffer. In this case, operations are
the same as for the case without a ring.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

commentl

Section
114 2

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type HD64180S
Item

I

Q&A

NO.' QA641-098A1E

CRC Code Transmission during a Memory-to-MSCI DMA Transfer
Classification

Q
How is the CRC code sent during a memory-to-MSCI DMA
transfer?

MMU

...j

MSCI
ASCI/CSIO

..J

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

@
C/)

Reset
A

Interrupt

During a chained-block transfer, the CRC is automatically
sent when status bit 7 of the descriptor corresponding to
the buffer containing the last data value is set to 1.
During a single-block transfer, set the CRCCC bit t01, and
the CRC code will be automatically sent if an underrun error
occurs at DMA transfer completion, setting the UDRN flag
to 1.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2 115

Type HD64180S
Item

J Q&A NO.' QA641-099A1E

DMAC Error Handling
Classification

Q
What will happen when an error occurs during a DMA
transfer between memory and the MSCI?

MMU

"
"

MSCI
ASCI/CS10
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

A

Reset
Interrupt

When an error such as counter overflow occurs in the
DMAC, the DMAC stops transfer.
When an error occurs in the MSCI, the DMAC does not stop
the transfer, but indicates the error status in the descriptor.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

Section
116 2

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Type

H064180S

Item

OCU Pin and COCO Flag

I

Q&A NO.' QA641-044B/E
Classification

Q
Is the COCO flag (MST1, ST1) reset when the OClJis
asserted low?

MMU

.,j
.,j

MSCI
ASCI/CSIO
OMAC
Timer
Wait
Refresh
z

Chip Select

o

Low Power Mode

en

B
w

Reset
A

Interrupt

No, the COCO flag is not reset unless 1 is written to the bit
position. This allows the OCU interrupt to be serviced
correctly.
If the 0ClJpin and the COCO flag were reset
simultaneously, the OCU interrupt request would always be
cleared and could not be serviced when a higher priority
interrupt occurred simultaneously with the OCU interrupt
(figure 1). Figure 2 shows the actual function used by the
H064180S.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
H064180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
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Section

2

117

I

Type

H064180S

Item

UCD" Pin and COCO Flag

Q&A No

I QA641-044B-21E

A

1iCDpin
CDCDftag

____~I

Higher priority
interrupt

~I--~i--~---­

Interrupt routine with
priority higher than
DCD will execute

OCD interrupt is
negated, so its
interrupt routine never
executes

Figure 1 COCO Flag Synchronized with

'i5CDpin

I

CDCDftag

I

Interrupt
source

I

,

i

I:I

I
I

Interrupt routine with
priority higher than
DCD will execute

J:Rm" Pin

i
i

I'

,

I

DCD interrupt routine
can be executed

Figure 2 H064180S COCO Function

Section

HITACHI

2

Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

118

I Q&A

Type

HD64180S

Item

Signal Direction of TXCM Pin (1)

No·1 QA641-100AlE

Classification

Q
Does the TXCM pin input or output the receive clock signal
specified as the transmit clock signal by the MSCI MTXS
register?

MMU

..J

MSCI

..

ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

The TXCM pin outputs the clock Signal supplied from the
RXCM pin.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl
MTXS register: MSCI TX clock source register

HITACHI
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Section

2

119

I Q&A

T,ype HD64180S

No·IOA641-101A1E

Item Signal Direction of TXCM Pin (2)
Classification

Q

Does the TXCM pin function as an input or output when the
TXCM line input is specified as the transmit clock by the
MSCI MTXS register, and the auto-echo function (where the
TXCM pin functions as an output) is selected by MMD2?

MMU

...j
...j

MSCI
ASCI/CSIO
DMAC
Timer
Waij
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

The TXCM pin functions as an output, with the MMD2
register setting (auto-echo or local loop-back) given higher
priority. Similarly, MMD2 and MD2 register settings are
given higher priority for pins TXCA and RXCA of
ASCI/CSIO, and pin RXCM.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

commen~
MMD2: MSCI mode register 2

Section

HITACHI

2

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120

Type HD64180S
Item

I

Q&A No.1 QA641-1 02A1E

AC Characteristics of Manchester Codes
Classification

Q
How are the AC characteristics of the Manchester codes
defined? The bit boundaries are unclear.

MMU

-.J

MSCI
ASCVCSIO
DMAC
Timer

\

Wait
Refresh
Chip Select
Low Power Mode
Reset
A

I

Interrupt

When TXCM functions as an input pin, the time between
the rising edge of the TXCM input and the intermediate
transition point of the Manchester code is defined as
tTDD1M' The same time period is also defined as tTDD2M
when TXCM functions as an output.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

COmmentJ

HITACHI
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Section

2121

I

Type HD64180S
Item

Q&A No.1 QA641-103A1E

AC Characteristics of Receive FM Data
Classification

Q
What is the timing relationship between the external clock
signal and FM-coded data received?

MMU

"

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt
Bus Interface

The timing is shown in figure 1.

Clock Generator
tRCRM____

r--

RXCM
(input)

----

ASE

~~

Software

tRCLWM

,.--

Others

tRCHWM
tRCYCM
tRDS1M

----

~IM

i+-

RXOMJ
(input)
""-

(

.

K

I-bit data
Figure 1 Receive Timing (RXCM = Input)

Comment

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

I

Section

HITACHI

2

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122

I

Type

HD64180S

Item

RXRDYFlag

aiA No·1 QA641-1 04A1E
Classification

a
Is it possible to clear the RXRDY flag (MSTO) by any
method other than the three given in the manual: hardware ..J
reset, channel reset command, and system stop mode?

MMU
MSCI
ASCIICSIO
DMAC
Timer·
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

The RXRDY flag is automatically cleared when the receive
buffer is empty.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

.

HD64180S
Hardware Manual
Other Data

Reference aiA

Comment I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2123

Type HD64180S
Item

I

Q&A No.1 QA641-105A1E

CRC Error Handling
Classification

Q
What must be done to prevent an interrupt if the CRC error
interrupt bit is enabled, when the CRCE flag of MSCI status
register 2 (MST2) is set to 0 or 1 according to the contents
of the status FIFO during data reception?

MMU

"

MSCI
ASCIICSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

The CRC interrupt (bit) usually must be masked. To
determine when a CRC error has occurred, generate an
interrupt at the end of the receive frame, and check bit 2
(CRCEF flag) of the MFST (MSCI frame status register)
within the corresponding interrupt routine.

Bus Interface
Clock Generator
ASE
Software
Others
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Reference Q&A

Comment

I

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Type

HD64180S

Item

Transmit Data Fixing

I

Q&A No.1 QA641-106A1E
Classification

Q
Is it possible to hold MSCI transmit data to either 0 or 1 for
consecutive cycles, by software?

MMU

Iv

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

It is possible in the idle state, where 8-bit values in the idle
pattern register (MIDL) are sent. The MIDL value should be
set to OOH or FFH.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
OthetOata

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2125

Type HD64180S
Item

I

Q&A

No.1

QA641-107A1E

Mark Output Modulation

Classification

Q

MMU

Is mark output subject to modulation when FM codes are
selected?

MSCI

""

ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A
Yes. The 1 level is modulated for the corresponding code
type before being output.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual

Other Data

Reference Q&A

Comment I

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126

Type

H064180S

Item

Idle Pattern Transmission

J Q&A NO.1 QA641-108A/E
Classification

Q

In HOLC mode, does the idle pattern transmission state
enter the flag transmission state after all eight bits of the
idle pattern have been transmitted?

MMU

Iv

MSCI
ASCI/CSIO
OMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A

Bus Interface

Yes.

Clock Generator
ASE
Software
Others

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Hardware Manual
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Reference Q&A

Comment

I

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Section

2127

I

Type

HD64180S

Item

1/0 Direction Selling of SYI\JC Line

Q&A No.1 QA641-109A1E

Classification

Q

-How is the 1/0 direction of the SYNC line specified?

MMU

...;

MSCI
ASCI/CSIO
DMAC
Timer
Wail
Refresh
Chip Select
Low Power Mode
Reset

I

A

Interrupt

It is specified by the MMDO register (002BH) as shown in
table 1.
Table 1

Bus Interface
Clock Generator
ASE

SYNC" Line Direction

Software
MMDO Bits

SYI\JC

7

6

5

Protocol Mode

0

0

0

Asynchronous

Input

0

0

1

Byte synchronous mono-sync

Output

0

1

0

Byte synchronous bi-sync

Output

0

1

1

Byte synchronous external

Input

1

0

0

Bit synchronous HDLC

Output

1

0

1

Bit synchronous· loop

Output

1

1

0

Reserved

Output

1

1

1

Reserved

Output

Comment

Others

Direction
Application Manual
HD64180~

Hardware Manual
Other Data

Reference Q&A

I

MMDO: MSCI mode register 0

Section
128

2

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I

Type

HD64180S

Item

Synchronization Using SYf\IC Line

Q&A No.1 QA641-110AlE
Classification

Q

Is it possible to establish synchronization at the end of data
similar to that at the beginning of data. by using the SYf\IC
line in MSCI byte synchronous and external synchronous
modes?

MMU

Iv

MSCI
ASCI/CS10
DMAC
Timer
Watt
Refresh
Chip Select
Low Power Mode

z

o

~

w

C/)

Reset
Interrupt

A

No. The HD64180S can establish synchronization only at
the beginning of data.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual

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Reference Q&A

Comment I

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Section

2129

I

Type

HD64180S

Item

Phase Relationship between SYf'lC" Line and Data

Q&A No.1 QA641-111A1E

ClassIfIcation

Q
What is the phase relationship between the SYf'lC" line and
data?

MMU

.J

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A
The relationship is shown in figure 1. Note that sufficient
setup time and hold time are necessary for SYf'lC" and data
in relation to the rising edge of the input clock pulse.

Clock Generator
ASE
Software

RXCM
(input)

.....

SYNC
(input)

\
tRD 1M.

=>

RXDM
(input)

~

Others

tsysu

1""1-

~
tRDHlI1

(

Figure 1 Phase Relationship between SYRC' Line and
Data
Comment

Bus Interface

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

I

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I

Type

HD64180S

Item

SYNC Codes for Byte Synchronous Mode

Q&A No.1 QA641-112A1E
Classification

Q
Mus! SYNC code's match during reception in MSCI byte
synchronous and extemal synchronous modes?

MMU

'"

MSCI
ASCVCSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

Q

§
en

Reset
A

I

Interrupt

No, it is not necessary, because synchronization is
established using the SYNC line in byte synchronous and
extemal synchronous modes. Any SYNC code can be
transmitted.

Bus Interface
Clock Generator
ASE
Software
Others
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Hardware Manual
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Reference Q&A

Comment

I

HITACHI
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Section
2131

Type HD64180S
Item

I

Q&A

NO.'

OA641-113A1E

Data Insertion between Flags in Bit Synchronous Mode
Classification

Q
Is it possible to insert data between a closing flag and an
opening flag, in bit synchronous mode?

MMU

..j

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

Yes. Delaying the data write operation to the transmit buffer
allows the idle pattern register value to be inserted between
a closing flag and an opening flag.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

Section
132 2

I

HITACHI
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Type HD64180S
Item

I

Q&A

NO.' QA641-114A1E

Character Insertion in Bit Synchronous Loop Mode

Classification

Q

Is it possible to insert a desired character during the idle
state in Bit Synchronous loop mode?

MMU

IV

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select

z
o

Low Power Mode

@
en

Reset
Interrupt

A

Yes. The primary station transmits a character written to
the idle pattern register. The secondary station transmits a
character written to the idle pattern register when the GOP
bit is set to 1. When the GOP bit is cleared to 0, the
secondary station enters the retransmission idle state and
retransmits the data, which was transmitted from the
primary station, after a 1-bit delay time.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual

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Reference Q&A

Comment

I

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Section

2133

I

Type HD64180S
Item

Q&A No·1 QA641-115A1E

Address Field Check Usage
Classification

Q

In what kind of applications is single address 2 mode
useful?

MMU

-.J

MSCI
ASCI/CSIO
DMAC
TImer
Wait
Refresh
Chip Select
Low Power Mode

"';

Reset
A

Interrupt

Single address 2 mode is very useful in the application
shown in figure 1, where data is transmitted to a specific
group of stations. This is achieved by specifying the group
address as the high-order address, and each terminal
address as the low-order address.
Receive
stations
( Transmit "\
station
Group A

J

(ER.

l cg)

Group B

l~Groupc
Terminal
Figure 1 Data Transmission to Specific Stations
Comment

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Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
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Reference Q&A

I

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134

I

Type

HD64180S

Item

ADPLL Synchronization Pattern

Q&A No.1 QA641-116NE
Classification

Q
Is it possible to establish synchronization using the
Manchester-coded ADPLL synchronization pattern in which
Os and 1s are reversed?

MMU

"

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z
o

~

UJ
CIl

Reset
A

Interrupt

Yes. Synchronization patterns AAH and 55H can both be
used.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

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Section

2135

I

Type HD64180S

Hem

Q&A

NO.' QA641-117A1E

Duty Cycle for ADPLL Operation
Classification

Q
Does the ADPLL operate correctly using an operating clock
whose duty cycle is smaller than 50%?

MMU

..j

MSCI
ASCI/CSIO
DMAC
Timer

Wait
Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A
Yes. It operates correctly as long as tpLHWM and tpLLWM
characteristics are satisfied, where tpLHWM is the high-level
pulse width of the ADPLL operating clock, and tpLLWM is
the low-level pulse width.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
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Reference Q&A

Comment

I

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136

I

Type

HD64180S

Item

ADPLL Operation in Local Loop-Back Mode

Q&A No.1 QA641-118A1E
Classification

Q
Is it possible to extract the clock element from the data in
the receive shift register, in MSCllocal loop-back mode?

MMU

Iv

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z
o

fj

w

(Jl

Reset
A

Interrupt

No. Refer to figure 4-2, Block Diagram of the MSCI
Receiver, on page 111 in the hardware manual.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
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Section

2

137

Type HD64180S

I

Q&A No.1 QA641-013C/E

Item Timer Counting Operation Using Input Clock
Classification

Q

MMU

Can the timer count events by using the external clock?

MSCI
ASCVCSIO
DMAC

..J

Timer
WaR
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

Yes. The internal timer can count the inputs on the TINo and
TIN1 pins by using the event-counting function with the
external clock set to a frequency of 1jt14 or smaller.

Bus Interface
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ASE
Software
Others
Application Manual
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Reference Q&A

Comment

I

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Type

HD64180S

Item

Compare-Match Flag

I

Q&A No·loA641-119A1E
Classification

Q

MMU

What happens if the CMF flag is not cleared after the
interrupt is issued (if enabled) when the contents of the timer
up-counter (TCNT) and timer constant register (TCONR)
match, setting the CMF flag?

MSCI
ASCI/CSIO
DMAC

Iv'

Timer
Wait
Refresh
Chip Select
Low Power Mode

z
o

fj
w

(J)

Reset
A

Interrupt

If the CMF flag is not cleared, the operation enters the same
interrupt routine immediately after the preceding interrupt
routine. Consequently, the CMF flag must be cleared within
the (first) interrupt routine.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
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Hardware Manual
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Reference Q&A

Comment

I

HITACHI
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Section

2139

I

Type

HD64180S

Item

Bus State during Internal 1/0 Access

Q&ANo.!OA641-014B/E
Classification

Q
1. What is the bus status during internal 1/0 access?

MMU

2. What happens when external I/O is assigned to the same
address as internal I/O?

ASCI/CSIO

MSCI
DM!,C
TImer
Wait
Refresh
Chip Select
Low Power Mode
Reset
A

Interrupt

1. Bus status during internal 1/0 access is as follows:

V

Bus Interface
Clock Generator

• Databus
-Read:
High impedance state
-Write:
Outputs data
• Address bus
- Readlwrite: Outputs address
2. When an internal I/O address and an external 1/0
address overlap, bus status is as follows:

·

Data bus
-Read:
-Write:

Reads internal 1/0; does not read
external 1/0
Outputs data to both internal and
external 110

ASE
Software
Others
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HD64180S
Hardware Manual
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Reference Q&A

• Address bus
- Readlwrite: Outputs address
Comment

Section

140

2

I

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I

Type

HD64180S

Item

Data Sampling Timing during Memory Read

Q&A No.1 QA641-046A1E
Classification

Q

MMU

Does the CPU sample data at the rising edge of T3 during
opcode fetch cycles and at the falling edge of T3 during
operand and data read cycles?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z
o

~
w

en

Reset
A

Interrupt

Yes, the CPU samples the operation code on the data bus at
the rising edge of T3 while it samples operands and data at
the falling edge of T3 (table 1).

Iv

Bus Interface
Clock Generator
ASE
Software

Table 1 Sampling Timing

Others
CPU Cycle

Sampling Timing

Operation code fetch cycle

T3 rising edge (i)

Data and operand fetch cycle

T3 falling edge (J. )

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

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Section

2

141

Type
Item

HD64180S

I

Q&A No.1 QA641-079A1E

Address Bus Status during 000 Acknowledge Cycle
Classification

Q

MMU

What is on the address bus generated by the CPU during
the INTo acknowledge cycle when 10E is asserted low?

MSCI
ASCI/CSIO
DMAC
Timer
Wail
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

The CPU puts the PC value following the address of the last ..J
machine cycle on the address bus during the INTo
acknowledge cycle. Although 10E is asserted low in this
case, it has no affect since 'RUIWR is negated.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

Reference Q&A

commentJ

Section

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142

Type

HD64180S

Item

ST Output Timing in

I

Q&A No. QA641-080AlE

1Jirr0 Mode 0
Classification

Q

MMU

How is ST output during the INTo mode 0 interrupt
acknowledge cycle?

MSCI
ASCVCSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

Q

§
en

Reset
A

Interrupt
...J

The timing is shown in figure 1.

Bus Interface
Clock Generator

J
·sr

...

tSTDl

~

,

r--

4-

Figure 1

J
t;:

INTo (Mode 0) Operation Timing

~

ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
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Sectio~

2143

I

Type HD64180S
Item

Q&A

NO.' QA641-015B1E

Interrupt during MMU Operation
Classification

Q

MMU

How will the MMU be affected if an interrupt occurs during
its operation?

MSCI
ASCI/CSIO
DMAC
Timer
Waft
Refresh
Chip Select
Low Power Mode
Reset

A

...j

If an interrupt occurs during MMU operation, the interrupt
vector is relocated according to the MMU base register
programming. Therefore, the interrupt vector should be
defined with reference to the MMU base register
programming (figure 1).
However, the interrupt vector can be located in common
area 0 or in an area where banks are not switched. These
areas are always located in the same logical address space.
Interrupt r-vector 2 r-• X

,-b1
vector

, X

Logical address space

Interrupt
vector 1

r--

Interrupt
vector

1=

i

,X

r--:

X

Bas!
Base
register (2)
register (1) •

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

~

Physical address space

Reference Q&A

Figure 1 Interrupt Vector Generation during MMU
Operation
Comment

Section
144 2

I

HITACHI
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Type

HD64180S

Item

000 Mode 2

I Q&A

No~ QA641-017A1E
Classification

Q

MMU
In Z80 INTo mode 2, the LSB of the lower vector in the 16bit vector address (Ao) is always O.

MSCI
ASCI/CSIO

In the HD64180S, is the LSB of the lower vector (Do)
automatically set to 0 in INTo mode 2?

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

i=

frl

C/)

Reset
A

I'"

No, in Z80 INTo mode 2, the LSB of the lower vector is not
automatically set to O. The Z80 data book explains that the
LSB (Ao) must be set to O.
In HD64180S INTo mode 2, the LSB of the lower vector
(Do) must be set to 0 since INTo mode 2 requires a 2-byte
vector.
However, even if the LSB of the lower vector (Do) is set to
1, the interrupt sequence is executed correctly.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2145

Technical Questions & Answers
Type H064l80S

I

Q&A No.1 QA641-0 l8A1E

Item JiJtVlT during Interrupt Acknowledge Cycle
Classification

Q

MMU

Is JiJfiifI acknowledged during the interrupt acknowledge
cycle, such as for TNT?

MSCI
ASCI/CSIO
OMAC
Timer
WaR
Refresh
Chip Select
Low Power Mode
Reset

..j

A
Yes, one instruction (excluding EI and 01 instructions) is
executed after the TNT acknowledge cycle, then the JiJfiifI
acknowledge cycle.
The JiJfiifI response sequence during the JiJfiifI acknowledge
cycle is the same.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

H064l80S
Hardware Manual
Other Data

Reference Q&A

Comment

I

Section

HITACHI

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146

Technical Questions & Answers

I

Type HD64180S
Item

Q&A No.1 QA641-019A1E

Interrupt after Reset
Classification

Q

MMU

Is JiJMfor 1NT acknowledged immediately after reset?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

~

Reset

Iv'

A
No, for three cycles immediately after reset (power-on reset
CyCle), m.lf and 1NT are disabled.
After these three cycles, the first instruction is executed and
are enabled. Figure 1 shows the timing.

interrupt~

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

•
RESET

.
~4.

.I
.

Power-on reset

fetch
...: opcode
(restart from
OOOOH). intarrupts
enabled

Application Manual
HD64180S
Hardware Manual
Other Data

Figure 1 Power-On Reset Timing
Note: m.lf is latched immediately after the power-on reset
cycle.
Comment

Reference Q&A

I

HITACHI
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Section
2147

I

Type HD64180S
Item

Q&A

NO.' QA641-020B/E

Interrupt during Refresh Cycle
Classification

Q

Is an interrupt (Jiltiifl or m) acknowledged during refresh
cycles?

MMU
MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

..j

A

Interrupt

No. interrupts are ignored during refresh cycles. However.

Bus Interface

Jiltiiff is acknowledged immideately after refresh cycles
during instruction execution because Jiltiiff is edge sensitive.
Figure 1 shows Jiltiiff acknowledge timing after refresh cycle.

Clock Generator

,

...X::..-

,

,

Machine
cycle

'::..Last
machine
cycle

I

NMI

Software
Others

::..-

j~

Refresh
cycle

...>t=

ASE

NMI
acknowledge

cycle

Application Manual
HD64180S
Hardware Manual
Other Data

Figure 1 Refresh Timing

m (INTo. INT1• and INT2) is ignored during refresh cycles.
If m remains active after the refresh cycle. it is

Reference Q&A

acknowledged during the instruction just after refresh.
Comment

I

Section

HITACHI

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148

I

Type

HD64180S

Item

JiJMT Acknowledge

Q&A

NO.' QA641·021B/E
Classification

Q

MMU

Is JiJMT acknowledged if it occurs during the timing sequence
in figure 1?

·'1

~

fiIMT

Last machine cycle

MSCI

:

ASCI/CSIO

~.

sJ1I~.
,
,,,
,,

·

Mr sample

timing

DMAC
Timer
Wait

,
,,,
,

Refresh
Chip Select

NMIW

(more than 120 ns)

Figure 1

Low Power Mode

NMT Timing

z

o
~
w

(/)

Reset
A

..J

Yes, if tNMIW (I'JMI pulse width) is 120 ns or more, NMT is
sampled and JiJMT acknowledge cycle begins after the last
MC (machine cycle).
If the I'JMI is asserted low for tNMIW or longer between 1
and 2 in figure 2, it will be sampled at the falling edge of the
clock marked 2.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
Current
Next instruction
instructio,. i 111

,

....:

Other Data

«I>

2

1

Figure 2

Comment

HD64180S
Hardware Manual

NMT Timing

Reference Q&A

I

HITACHI
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Section

2149

Type HD64180S
Item

I

Q&A No.1 QA641-047A1E

Interrupt Acknowledge Timing after EI Instruction Execution
Classification

Q

MMU

When is an interrpt acknowledged after an EI instruction?

MSCI
ASCIICSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

..j

A
Maskable interrupts (llilm, etc.) are acknowledged in the
last machine cycle of any instruction cycle other than EI.
Note that no interrupts can be acknowledged during EI
instruction execution. Therefore, if an interrupt occurs
immediately before or during an EI instruction cycle, it Is
acknowledged after the end of the RETI instruction cycle
following the EI instruction.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual

For example:

Other Data
~

EI
RETI

Interrupt request

Interrupt request acknowledged during this'
instruction
(interrupt acknowledge cycle)
Comment

~

Reference Q&A

I

Section

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150

I

Type

HD64180S

Item

Interrupt Sampling during Block Transfer Instruction Execution

Q&A No.1 QA641-048A1E

Classification

Q

MMU

Normally. the CPU samples interrupts at the falling edge of
the $ clock pulse prior to state T3 or Ti in the last machine
cycle.

MSCI
ASCIICSIO
DMAC

When does the CPU sample interrupts during a block
transfer instruction which may require over hundreds of
machine cycles?

Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

i=

~

C/)

Reset
A
The CPU samples interrupts at the falling edge of the $
clock pulse prior to state T3 or Ti in the last machine cycle
of each one byte transfer (14$ or 12$) (figure 1).

"

Interrupt
Bus Interface
Clock Generator
ASE
Software

Interrupt acknowledge cycle

-

(n -l)th byte
transfer cycle

n·th byte transfer cycle

Interrupt

\

J

~

.J1Il.. Tl T

Others

MC5 Mesl

T3 Tl T2 T3 T T2 T Tl T T3 1 Tih.J1

Interrupt
sampling

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A
Figure 1 Interrupt during Block Transfer

Comment

I

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Section

2151

I

Type HD64180S
Item

Q&A

No.1 QA641-049B/E

Interrupt during SLP Instruction Cycle
Classification

Q

MMU

What is the CPU status when an interrupt occurs during
SLP instruction execution?

MSCI
ASCIICSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

...j

A
The CPU operates as shown in figure 1.
Interrupt
SLP fetch cycle

•

Tl

T2

U

Interrupt

RALT

T3

... ....

• Sleep mode •

·

:TS1 TS2

···
··
·
I

Address

acknowledge

..;...

2nd SLP opcode address

Interrupt
Bus Interface

·

cycle

ASE
Software

: T1

T2

·····

···
'LJ.·

Others
Application Manual
HD64180S
Hardware Manual

· .

~

Clock Generator

Next address

. Other Data

FFFFFH

Figure 1 CPU Timing
When an interrupt is sampled during an SLP instruction
cycle, RA[T is asserted low for 1 clock state, and the
address bus outputs FFFFFH.
Comment

Reference Q&A

I

Section

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. 152

Type

HD64180S

I

Q&A No.J QA641-050AlE

Item rnTo Mode 0
Classification

Q

MMU

If the CALL instruction (three-byte instruction) is executed
during INTo mode 0 acknowledge cycle, the CPU cannot
return from the interrupt service correctly. Why is this?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

hlen

Reset

..,j

A

Bus Interface

INTo mode 0 operates as follows:
1. Stacks PC contents by an instruction, usually (one-byte)
RST, fetched during INTo mode 0 acknowledge cycle
2. Stops incrementing the PC during INTo mode 0
acknowledge cycle
3. Executes instruction fetched from data bus during
interrupt acknowledge cycle.
However, if the (three-byte) CALL instruction, which
requires three machine cycles to fetch including the
, operand, is executed during INTo mode 0 acknowledge
cycle, PC increment stops only during interrupt
acknowledge cycle (one machine cycle) and is incremented
by 2 during the rest of the CALL instruction (operand fetCh).
As a result, PC + 2 is stacked as the return address.
Therefore. decrement the stacked PC value by 2 in
software to return from the interrupt correctly.
Comment

Interrupt
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

Reference Q&A

I

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Section

2153

I

Type

HD64180S

Item

NMT Interrupt Sampling Timing

Q&A No.' QA641-0S1 AlE

Classification

Q

MMU

JIIliAT is sampled at the falling edge of a cj) clock pulse prior to

MSCI

state T3 or Tj in the last machine cycle of each instruction.

ASCI/CS10
1. When is NMT sampled if the last machine cycle is an
internal Tj cycle?

DMAC
Timer

2. How about lliIT?

Wait
Refresh
Chip Select
Low Power Mode
Reset

A
Both NMT and lliIT are always sampled at the falling edge of
the second last cj) clock pulse of the last machine cycle. The
NMT sampling is not affected by the number of internal Tj
cycles (figure 1).

"

Interrupt
Bus Interface
Clock Generator
ASE
Software

T3

....

Interrupt
acknowledge
cycle

Instruction cycle
T1

T2

T3

Ti

· ···
··:
:

Ti

~

...

Ti

T1

·.-........-;

tn1ing

Others

Application Manual
HD64180S
Hardware Manual
Other Data

TiPriorto Ti of last machine cycle

Reference Q&A
Figure 1 Interrupt Sample TIming during TI

Comment

I

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154

I Q&A

Type HD64180S
Item

NO~ QA641-0S2A1E

Status Bit during TRAP

Classification

Q

MMU

1. What happens if an aditional TRAP occurs before the
INTITRAP control register TRAP bit is cleared?

MSCI
ASCI/CSIO

2. What is the status of the TRAP and UFO bits in this
case?

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

§
CIJ

Reset
A

i"

1. An additional TRAP interrupt occurs.

Interrupt
Bus Interface
Clock Generator

2. The TRAP bit remains 1 since it can be cleared only by
software.

ASE
Software

The UFO bit remains unchanged since it cannot be
modified while the TRAP bit = 1.

Others

Application Manual
HD64180S
Hardware Manual

Other Data

Reference Q&A

commentl UFO bit: Indicates if TRAP occurred in 2nd or 3rd opcode fetch cycle:
UFO bit = 0: TRAP occurred in 2nd opcode fetch cycle
UFO bit = 1: TRAP occurred in 3rd opcode fetch cycle

HITACHI
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Section
2155

I

Type HD64180S
Item

Q&A No. QA641-053B/E

PC Stacking during TRAP
Classification

Q

MMU

1. Why is the stacked PC value different for TRAP
occurrence during second opcode fetch and during third
opcode fetch?

MSCI
ASCI/CSIO
DMAC

2. How can the first opcode address be calculated?

Timer
Wan
Refresh
Chip Select
Low Power Mode
Reset
A
1. Table 1 summarizes CPU operations when TRAP occurs
during the second and third opcode fetches.
Table 1 CPU Operations during TRAP

"

Interrupt
Bus Interface
Clock Generator
ASE
Software

TRAP during 2nd
TRAP during 3rd
O~code Fetch
Oecode Fetch
Bus Cycle
Bus Cycle
PC
PC
lstopcode
PC -1 .... 1st opcode
PC-3 . .
fetch
fetch
2ndopcode
PC
2nd opcode
PC-2
fetch
felch
Stack
PC Operand
PC-l
read
3rd opcode
PC
fetch
Memory read
PC
Stack
PC-l -

Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

-

Comment

I

Section

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156

Type HD64180S
Item

I

I

Q&A No QA641-053B-21E

PC Stacking during TRAP

A

Therefore, the first opcode address can be calculated from one of the following
equations to execute the instruction disturbed by TRAP occurrence .
• TRAP during 2nd opcode fetch
1st opcode address = stacked PC value - 1
• TRAP during 3rd opcode fetch
1st opcode address = stacked PC value - 2

z
o

@
(/)

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

157

Type HD64180S

I Q&A

NO~aA641-054B1E

Item Nfiiffduring DMA Transfer
Classification

Q

MMU

What happens to DMAC after Nf,ifJ assertion?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

..j

A

-

When NMI is asserted low during DMA transfer, the DMA
transfer ends at the end of the current DMA cycle.
However, note that the NMI acknowledge cycle begins at
different times, depending on the CPU status before DMA
transfer (figures 1, 2, and 3).
DMAC operations can be restarted by writing 1 to the
corresponding channel's DE bit.
NMI acknowledge cycle timings are shown in the following
pages.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

commentl

Section

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158

Type HD64180S
Item JiJtilT during DMA Transfer
A

1. When DMA transfer starts during instruction execution cycle
a. When the DMA cycle starts during the instruction execution cycle, before the last
machine cycle (T1, T2, and T3) of instruction A, JiJtilT is sampled at the falling
edge of T2 in the last machine cycle of A (figure 1).
Rest of
Instruction
A cycle

Wi acknowledge

DMAcycle

cycle

z
o

~
w

iiiMi sampling to

NMi sampling to start NMi

stop DMA cycle

acknowledge cycle

!/)

samplin

g

Figure 1 DMA Cycle Starting before Last Machine Cycle

b. When the DMA cycle starts during the instruction execution cycle, before the last
internal cycle (Ti) of instruction A, NMf is sampled during the DMA cycle (figure 2).

Instruction
A cycle

DMAcycle

Ti of
instruction A

NMi acknowledge

q,

DRE~
BREci
sampling

NMi sampling to start
aCknowledge cycle

NMi

NMi sampling to
stop DMA cycle

Figure 2 DMA Cycle Starting before Last Internal Cycle

HITACHI
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Section

2

159

Type HD64180S

Item Jiiffiifl during DMA Transfer

A
2. When DMA transfer starts at the end of the instruction execution cycle, NfJT is'
sampled at the next falling edge of T2 or Ti of the last machine cycle of the next
instruction, B (figure 3).

Instruction A cycle
(last machine cycle)

•~
t

DREQ
sampling

DMAcycle

t············i
NMi sampling to
stop DMA cycle

NMI sampling to start NMI
acknowledge cycle

Figure 3 DMA Cycle Starting at the End of Instruction Cycle

As shown in figure 1 to figure 3, NfJT has the following two functions:
1. To stop the DMA.
2. To execute the NfJT routine.

Section

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160

I Q&A

Type

HD64180S

Item

0l1E0i and WI

NO~ QA641-055A/E
Classification

Q

MMU

What happens to DMAC operation if WI asserted low while
the DMAC operates under the control of the O'REOT pin?

MSCI
ASCI/CSIO
DMAC
Timer
Watt
Refresh
Chip Select
Low Power Mode
Reset

A

...J

DMAC operation is suspended and WI is sampled with the
timing shown in figure 1.

Interrupt
Bus Interface
Clock Generator
ASE
Software

NMI acknowledge

.14

.,_

cpu cycle

--

DMA cycle

t'""·..

DREQI~

Lt

_'4

.'4

CPU cycle

cycle

_,_

N. _ " ,

\!.J

NMI

Others

Application Manual
HD64180S
Hardware Manual
Other Data

Figure 1 DMA Cycle Stopped by IiIMT

Reference Q&A

commentl

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Paint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2161

I

Type HD64180S
Item

1

Q&A No QA641-055A-2/E

tmEOi and mT

A
Note that if 0J1E0Iand mT are asserted low simultaneously, mT sampling has
priority (figure 2).
NMI acknowledge
Instruction cycle
cycle (OMA
(last machine cycle) .• ... disabled)

~
'_~r+-:---

15Rmi

-----.\0

Figure 2

Section
162 2

rmm and m.M Conflict

HITACHI
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I Q&A

Type

HD64180S

Item

Internal Interrupt Sampling Timing

No·1 QA641-056B/E
Classification

Q

MMU

Extemal interrupts are sampled at the falling edge of state
T2 or TI in the last machine cycle.

MSCI
ASCI/CSIO

When are internal interrupts sampled?

DMAC
Timer
Waft
Refresh
Chip Select
Low Power Mode
Reset

V

A
They are sampled at the falling edge of state T2 or Ti in the
last machine cycle of the instruction cycle.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl

HITACHI
HltachiAmerica, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2163

I

Type HD64180S

Q&A No.1 QA641-057B/E

Item lfITA Signal Generation
Classification

Q

MMU

The HD64180S can be interfaced to the 8259 to control 110
interrupts.

MSCI
ASCIICSIO

1. How can we generate an lfITA signal to be input to the
8259 from the HD64180S?

DMAC
Timer

2. Are there any precautions?

Wait
Refresh
Chip Select
Low Power Mode
Reset

...j

A
1. Three lfITA signal pulses must be input from the
HD64180S to the 8259 to control interrupts:
a. One lfITA pulse for opcode fetch
b. Two lfITA pulses for operand read
The lfITA pulse for opcode fetch can be produced by OR
and TOE. The lfITA pulse for operand read can be
produced by "AU.
This interface is the same as for Z80 and 8259.
Figure 1 shows an example of an lfITA signal generation
circuit.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

This circuit is for reference only. Check logic and timing carefully for your application.

Section

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164

Type

HD64180S

Item

1JiITA Signal Generation

A
LSCS
INTA
(8259)

LS32
LIR

MEWR
HD64180S
10

~

2G
lG
B
A

ICE
RD
W'l

2Yl

MERD

1Y2

VOWR

z

W1

IIORD

i=
(.)
w
(/)

0

Figure 1 1JiITA Signal Generation Circuit Example
2. Precautions
• This circuit cannot be used when the internal or external DMAC is used in the
system.
• When'RU signal is used to generate the 1JiITA signal for operand read (1 b
above) TOE must be used to avoid dataconflict between I/O and memory (note 1
in figure 2).
• In lJiJTO mode 0, if the RST instruction (3-byte) is executed during its
acknowledge cycle, the PC is put on the stack. If a CALL instruction is executed,
PC + 2 is put on the stack.

HITACHI
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Section

2165

Type HD64180S
Item

TI\ITA Signal Generation

A

INTO mode 0
acknowledge cycle
(CALL instruction felch)

1

Inlernal cycle
CALL instruction
operand read

Stack
(high)

Stack
(low)

~

PC
~PC+2~
......- - - - - '
Start address

IOE
Nole 1

CLTLJ)

Lf
LJL..J

Note 2

Ct. ... D
Noles: 1.

AD inpullo memory pulled high 10

l!!!vent bus..£2!!!!iCl.
2. RD input to INTA pulled high to prevent
8259 malfunction.

Figure 2 lfiIT}; Timing

Section

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166

l:ype
Item

HD64180S

I Q&A

No~ QA641-081 AlE

Interrupt Priority
Classification

Q
1. How does the MPU accept interrupts that occurred
simultaneously from many internal 1/0 operations?

MMU

2. What about internal interrupts that occurred
simultaneously with f\JfiilT or OO?

ASCI/CS10

MSCI

DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z

o

~

UJ

(/)

Reset
A

...J

Internal interrupts are maintained, and interrupts are
accepted in order of highest priority.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2167

Type HD64180S
Item

I

Q&A No·1 QA641-082A1E

Interrupt Request during HALT Opcode Fetch
Classification

Q

MMU

Can the CPU acknowledge an interrupt request during
HALT opcode fetch?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode
Reset

.J

A
Yes. When interrupt enable flag 1 (IEF1) is set to 1, the
CPU will acknowledge the interrupt request.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

Section

H ITACH I

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168

I

HD64180S

Type

Q&A No.1 QA641-083A1E

Item ST Output Timing during Interrupt Acknowledge Cycle
Classification

Q

MMU

--

What is the ST status during the INTo acknowledge cycle
in mode O?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

z
o

@
rn

Reset
A

.J

I

ST status is the same as in modes 1 and 2.

Interrupt
Bus Interface
Clock Generator
ASE
Software
Others
Application Manual

HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2169

Type HD64180S

Item

I

a&A

NO.1 QA641-023C/E

Wait Function at 1/0 Access
Classification

a

MMU

Is a wait state (Tw) always inserted during 1/0 access?

MSCI
ASCIICSIO
DMAC
Timer

V

Wait
Refresh
Chip Select
Low Power Mode
Reset

A

Interrupt

Yes, the number of wait states specified by the software
are inserted during extemal 110 access.
During on-chip I/O access, no wait state is inserted.

Bus Interface
Clock Generator
ASE
Software
Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference a&A

Comment

I

Section

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170

I

Type

HD64180S

Item

Power-On Reset Sequence

Q&A No.1 QA641-024B/E

Classification

Q

MMU

How is the power-on reset sequence performed?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

.J
A

z
o

~

(/)

Reset
Interrupt

Figure 1 shows the power-on reset sequence.

I

~

•

~

Reset state

$

T1

Clock Generator
Restart
Opcode fetch
T2 T3

JlJ"1J"1J1.IliU1.J1Jl..
More than 6 clock cycles

RESEi'" ~

...

•

11/

High
impedance

>-s---<

OOOOOH
Restart address

Address

Bus Interface

ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
Other Data

Figure 1 Power-On Reset Sequence
Reference Q&A

COmment

I

RESET pin must be low for more than 6 clock cycles.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2171

I

Q&A NO~ QA641-058B1E
Type HD64180S
Control
Signal
Slatus
after
Reset
Item·
Classification

Q

MMU

What is the status of the co~rol signals after each reset?

MSCI
ASCVCSIO
DMAC
Timer
Wait
Refresh
Chip Select
Low Power Mode

V
A

Reset
Interrupt
Bus Interface

The 'RESET signal must be asserted for at least 6 states.
Table 1 shows the status of each control signal.

Clock Generator

Table 1 COntrol Signal Status

ASE
Software

Control Signal
Address bus
Data bus
Control signals (RD, WR, JlE, lOE,
ST, m, WJ:T, ~, TENl'J)

Status
High impedance
High impedance
High (1)

ell

Clock output

However, if 'RESET is not held low for at least 6 clock states
at power-on reset, the state of these signals is undefined.
For external reset, each signal remains unchanged until it is
reset.

Others
Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl

Section

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172

I

Type

HD64180S

Item

Sleep Mode and System Stop Mode

Q&A No.1 QA641-026B/E
Classification

Q

MMU

What is the difference between sleep mode and system
stop mode?

MSCI
ASCI/CSIO
DMAC
Timer
Wait
Refresh

'"
A

Chip Select

z
o

Low Power Mode

@
en

Reset
Interrupt

System stop mode is entered when the 10STP bit is set to 1
and the sleep instruction is executed. Other major
differences are as follows:

Bus Interface
Clock Generator
ASE
Software

• Sleep mode
CPU stopped; I/O not stopped

Others

• System stop mode
CPU and 1/0 stopped; clock generator and oscillator
not stopped

Application Manual
HD64180S
Hardware Manual
OtherOata

Reference Q&A

Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2173

Type HD64180S
Item

I

Q&A No·1 QA641-028C/E

System Standby Function
Classification

Q

MMU

Does the HD64180S have a system standby function (stop
clock) to reduce power consumption?

MSCI
ASCI/CSIO
DMAC
Timer
Watt
Refresh
Chip Select

.,j

Low Power Mode
Reset

A

Interrupt
Bus Interface

Yes. However, if the clock is completely stopped, MPU
operation and data retention in the registers are not
guaranteed.

Clock Generator

To avoid these problems, we recommend that all register
information be stored in a battery-powered RAM and then
power supply to HD64180S be stopped.

Others

ASE
Software

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Comment

Section
174/2

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

I

Type

HD64180S

Item

Interrupt Sampling in Sleep Mode

Q&A

NO.1 QA641-059B/E
Classification

Q

MMU

1. Can an interrupt be accepted in sleep mode?

MSCI
2. If so, when is sleep mode canceled?

ASCIICSIO
DMAC
Timer
Wait
Refresh

z

Chip Select

o

...J

Low Power Mode

(Jl

...J

Interrupt

fj
w

Reset
A
1. The CPU accepts interrupts at the falling edge of the,
clock pulse one pulse after it enters sleep mode (figure
1).
2. Sleep mode is cancelled two and a half, clock pulses
after an interrupt is accepted. The CPU status is
recovered according to the IEF1 flag status:
• IEF flag

• IEF flag

= 1:
=0:

CPU begins an interrupt acknowledge
cycle
CPU begins an JiIfi.lT acknowledge cycle
or executes the instruction following the
SLP instruction for maskable interrupts

In this case, input the external interrupt signal so that a
low level is sampled two or more consecutive times.
Comment

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180S
Hardware Manual
OtherOata

Reference Q&A

I

HITACHI
Hitachi America, Ltd.· San.francisco Center· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2175

Type HD64180S
Item Interrupt Sampling in Sleep Mode
A
Interrupts can
be sampled
SLP instruction
cycle

Sleep

mode

Interrupt
acknowledge or
instruction
execution cycle

Interrupt

Figure 1 nmlng of Interrupt during Sleep Mode

Section
176 2

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

I Q&A

Type

HD64180S

Item

Dynamic RAM Refresh during DMA

NO~ QA641-029A1E
Classification

Q

MMU

Is DRAM refreshed during internal DMA operation?

MSCI
ASCIICSIO
DMAC
Timer
Wait

..j

Refresh
Chip Select
Low Power Mode

z

o

t5w

(J)

Reset
A

Interrupt

Yes, refresh cycles are inserted during internal DMA cycles.

Bus Interface
Clock Generator

The refresh controller does not distinguish DMA cycles from
CPU cycles.

ASE

Dynamic RAM refresh is performed at the end of the
machine cycle during both CPU and DMA cycles. The
interval and duration of the refresh cycles are
programmable.

Others

Software

Application Manual
HD64180S
Hardware Manual
Other Data

Reference Q&A

Commentl

HITACHI
Hitachi America, Ltd.· San Francisco Cent~r • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2177

I

Type

HD64180S

Item

Dynamic AAM Aefresh (A Counter Function)

Q&A No.1 QA641-030B/E
Classification

Q
1. Is the HD64180S refresh controller different from the Z80
refresh controller?

MMU

2. What is the function of the A counter?

ASCI/CS10

MSCI
DMAC
Timer
Wait

-,J

Aefresh
Chip Select
Low Power Mode
Aeset

A

Interrupt

1. Yes, the refresh controller is different from the Z80
refresh controller. Aefresh cycles are inserted or
supressed by software. Also, the. interval and length (2CP9CP) of the refresh cycle are programmable. The refresh
address (12-bit address) is output at Ao-All (figure 1).

-

M::

.. I....

Refresh cycle

Bus Interface
Clock Generator
ASE
Software
Others

MC+1

...1 ....

cjl

Application Manual

Address

X

REF

\

1J:a:1J: ll

X
I

HD64180S
Hardware Manual
Other Data

Figure 1 Refresh Example (refresh programmed to 3
cycles)
2. The A counter counts the number of CPU opcode
fetches. It has no relation to dynamic RAM refresh.
Comment

Section
178 2

Reference Q&A

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

I

Type

HD64180S

Item

Refresh Cycle Insertion

Q&A No·1 QA641-060AlE
Classification

Q

MMU

Normally, a refresh cycle is inserted at the breakpoint of an
instruction cycle (machine cycle).

MSCI
ASCI/CSIO

Is it possible to insert a refresh cycle between consecutive
internal machine cycles (Ti)?

DMAC
Timer
Wait .

"

Refresh
Chip Select
Low Power Mode

z
o

§
UJ

CIJ

Reset
A

Interrupt

Yes, a refresh cycle can be inserted between internal cycles,
and between internal and machine cycles since an internal
cycle is also considered as a machine cycle (figure 1).
MC·

.. ,....,.
Internal
cycle

T3

Refresh
cycle

Tj

TRl

...,....,.
Internal
cycle
Tj

TR2

MC·

Bus Interlace
Clock Generator
ASE
Software
Others

Tl



ReF

\
MC·

.. ,.

T3

Internal
cycle

Tj

Application Manual

I

Tj

Refresh
cycle

"I·

MC·

...~

TRl

TR2

HD64180S
Hardware Manual
Other Data

Tl



~

\

r-

MC·; Normal machjne cycle ( T l' T 2 ' (TW), and T3 )

Reference Q&A

Figure 1 Refresh Cycle Insertion Point
Comment

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2

179

I Q&A

Type HD64180S
Item

NO~ QA641-09SB/E

Bus Release Mode and Refresh
Classification

Q

How is DRAM refreshed after eOSREQ occurs at Q) in
figure 1?

.

Bus release mode

i CPU cycle

i

Refresh
cycle

MMU
MSCI

i

~HHt:nH:~~m:n

ASCI/CSIO
DMAC
Timer

REF~~

Wait

!(j)!~

:::~
In ~ins
r+est
---------tli
i
!
'BOSACK
;,;;.;.,,;.--------'H
:

Figure 1 Bus Release Mode and. Refresh

..j

Refresh
Chip Select
Low Power Mode
Reset
Interrupt

A
Only one refresh request is retained, and it is performed
after the bus cycle following the CPU operation (one
machine cycle) in the figure.

Bus Interface
Clock Generator
ASE
Software
Others

Application Manual
HD64180:s
Hardware Manual
Other Data

Reference Q&A

Commentl

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

180

I

Type

HD64180S

Item

EXTAL Input and ';>~.':Y{§;

Title

I

(\:;';K·'!'{;R5bK"L,);'· } Overlapped
Area

Reference Q
No.
I

&

A

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

198

No

QA641-003A/E

04S 08S .8M Ol6M 0 Software
Type

HD64180

Item

Div

o Evaluation

kit '

Emulator

OSD OSBC

DEl bit in the DMA Status Register (DSTAT)

Q

Classifica tion
MMU

(1)

How long is DMA transfer disabled when DEl bit
is set to O?

(2)

How does DMA restart?

0 DMAC

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET

z
o

~

LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
A

Applicable Manual
Title
(1)

(2)

DMA transfer is disabled until DEl bit is reset
to 1. DWEl bit must be written with 0 when
performing any software write to DEL
If memory ~ memory DMA transfer is executed in
burst mode, DMA transfer cannot be interrupted.
It can only be interrupted in memory ++ memory
(cycle steal mode), memory ++ I/O, or memory ++ memory
mapped I/O transfer mode.
To restart DMA transfer, DEl must be set to 1.

I

HD64180
Data Sheet
Other Data
Title

I

Reference Q
No.
I

COMMENT

&

A

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra POint Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2199

No

-

QA641 004A/E

_

o4S o8S .8M 016M 0 Software
Type

HD64180

Div
o Evaluation kit '
Emulator

oSD oSBC

DME bit (DMA MASTER ENABLE bit) in DMA Status Register

Item

Classificstion

Q

MMU

When NMI occurs, DME bit is reset to 0 and DMA
operation is disabled passing control to the CPU.
(1)

How is DMA operation timing halted?

(2)

How does DMA operation restart?

0 DMAC

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SO
SOFTWARE
OTHERS
Applicable Menual

A
(1)

When NMI occurs, the CPU is given control after
the current DMA cycle is completed.
The following shows the timing
Tl

"

T2

T3

TI

T2

T3

LJcycle
,,+ DMA write

(2)

To restart DMA operation, DE (DEO or

~

I

HD64180
Data Sheet
Other Data

TI

.....Jr-u-L..JlJLJL..JLIL
.
.

NMI

Title

Title

I

CPU cycle

DEI~

Reference Q&A
No.
I

bit

must be set to 1.

COMMENT

I
,

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

200

No

QA64l-00SA/E

D4S D8S .8M D16M 0 Software
Type

HD64180

Div

o Evaluation

kit '
Emulator

DSD DSBC

DWE bit in DMA Status Register

Item

Classification

Q

HMO

What is the function of OWE bit in DMA status
register?

0 DMAC

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT

z

o

§
C/)

RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
A
DE bit enables DMA operation of internal DMAC, while
bit enables a software write to its corresponding
DE bit, for a specific channel operation.

~

Applicable Manual
Title I
HD64180
Data Sheet
Other Data
Title

I

Reference
No.

COMMENT

Q

&

A

I

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2,000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2201

No

QA641-006A/E

04S 08S .8M 016M 0 Software
Type

HD64180

Item

Memory

Div

++

o Evaluation

kit '

Emulator

OSD OSBC

I/O DMA Transfer
Classification

Q

MMU

To enable external DREQO input, both All and A16 of
I/O address must be set to O.
Is DMA requested by DREQO acknowledged if either All
or A16 is set to l?

o

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE

SD
SOFTWARE
OTHERS
Applicable Manual

A

Title
No, if either Allor A16 is set to I, DREQO is
disabled and the DMA request is not accepted.

I

HD64180
Data Sheet
Other Data
Title

J

Reference

No.

COMMENT

Q &A

I

I

Section

HITACHI

2

Hitachi America,Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

202

No. QA641-007A/E
o4S o SS .SM 016M 0 Software
Type

HD641S0

Div
DEvaluation kit'

Emulator

Item

,

oSD oSBC

Memory ++ ASCI DMA Transfer
Classification

Q

MMU

To execute memory++ ASCI DMA transfer, DMA source/
destination address register should be programmed as
follows.
(1)

Bits AO-A7 must contain the address of the ASCI
transmit or receive data register.

(2)

Bits AS-A15 must be set to OOH.

(3)

Bits A16-A17 must be set to "01" or "10".

Can the memory ++ ASCI DMA transfer be executed
correctly if bits AS-A15 in DMA source/destination
address register are not set to OOH?

o

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE

SD
SOFTWARE
OTHERS
Applicable Manual
'Title

A
No, if bits AS-A1S in DMA source/destination address
register are not set to OOH, Memory ++ ASCI DMA
transfer cannot be executed correctly.
For example, to execute ASCI (channel 0) RDR'"
memory DMA transfer, Bits Ao-A7 must be set to OSH,
bits AS-Al?, must be set to OOH and bits A16-A17 must
be set to '01" for correct ASCI (channell) RDR ...
memory DMA transfer.

J

HD641S0
Data Sheet
Other Data

J

Title

Reference
No.

Q& A

J

COMMENT

I

Bits AS-A15 set to other than OOH will cause internal DMAC to access
other I/O address and not RDR.
(DMA request from ASCI channel 0 is not reset)

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005·1819 • (415) 589-8300

Section

2203

No
D4S DSs .SM Dl6M
Type

HD64lS0

QA64l-00SA/E

0 Software

Div
"

DEvaluation kit'

Emulator

DSD DSBC

Memory (specified in application program) ++ I/O DMA Transfer

Item

Classification

Q
Is it possible to execute memory (specified in
spplication program) + I/O DMA transfer independently
of the MHO Base Register?

o

MHO
DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS

A

Applicable Manual
No, to execute memory (specified in application program)
I/O DMA transfer correctly, physical source address
must be defined as follows.

Title

I

++

(1)

(2)

COMMENT

Software calculates physical source address of
data area using the logical source address and
the Base Register.
The calculated physical source address is loaded
into the DMA source address Register.
When the physical address is known, it can be
loaded into the DMA address register directly,. but
if DMA transfer is executed within the logical
memory area, Block transfer instructions can be
used.

Other Data
Title

I

Reference Q&A
No.
I

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

204

No

QA641-009A/E

04S OSS • SM Ol6M 0 Software
Type

HD641S0

Memory

Item

++

Div

o Evaluation kitEmulator
'

OSD OSBC

I/O (ZSOSIO) DMA Transfer
Classification

Q

MMU

When memory ++ I/O (Z80SI0) DMA transfer 1s executed
while DREQO is programmed for level sense, DMA transfer
does not complete correctly.
Are there any restrictions in DMA operation?
(ROY signal of ZSOSIO is input to DREQO of HD641S0)

0 DMAC

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR

z
o

~

ASE
SD
SOFTWARE
OTHERS
Applicable Manual

A

Title
When DREQO is programmed for level sense additional
DMA cycle is executed since RDY signal (which is
input to DREQO> is set high after additional sampling
of DMA request signal (DREQO).
The timing chart follows.
DMA write cycle
I DMA read cycle I
1:1
T2
T3 ' Il
TW T3
T2

Next DMA
cycle
_If ead

J

HD641S0
Data Sheet
Other Data
Title

I

f,

AO"'A1S

=><

ACK
DREQ

7~I

>c=
NMI

aCknowledge
cycle
Reference
No.

I

NMli

I

HD64180
Data Sheet

INT (INTO' INTI and INT2) is ignored during refresh cycles.
If !NT remains active after refresh cycle it can be
acknowledged during instruction executed just after

Q

&

A

I

reset.

COMMENT

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

216

No

QA64l-021A/E

04S 08S .8M 016M 0 Software
Type

HD64180

Div
O'Evaluation kit '
Emulator

OSD OSBC

NMI Acknowledge

Item

Classification

Q

HMU

Is lIRr acknowledged if occuring during the following
timing sequence?

I'
: Tl

;,

I

iI"t

NMI

Last MC
T2
T3
I

I
I
I
I
I

I
NMIW ' (
(more than l20ns)
NMI Sample timing

t

I!
I

I

;
I
I

,
i

t
I

Me: Machine Cycle

A
Yes, if tNMIW (NMI pulse Width) is 120ns or more,
NRI is sampled and NMI acknowledge cycle begins
after last MC.

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
0 INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
Applicable Manual
Title I
HD64180
Data Sheet
Other Data
Titie

J

Reference
No.

Q&A

J

COMMENT

I

HITACHI
Hitachi America, ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2217

No. QA64l-022A/E
04S
Type

HD64l80

Item

Div

o 8S

.8M Ol6M 0 Software

o Evaluation

kit ,
Emulator

OSD OSBC

WAIT Insertion during Refresh Cycle
Classification

Q

MMU

Can WAIT cycle be inserted during refresh cycle by
activating WAIT input?
TR

TR

TRW

DMAC
ASCI
CSI/O
TIMER

f,

Machine cycleX

I

WAIT

Refresh Cycle

XMachine Cycle

I

BUS INTERFACE
INTERRUPT
0 WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS

A
No, WAIT input is disabled during refresh cycle.
However, the refresh cycle can be programmed to two
or three cycles setting the REFW bit in the refresh
control register accordingly.

Applicable Manual
Title I
HD64l80
Data Sheet
Other Data
Title

I

Reference
No.

COMMENT

Section
218

2

Q &A

J

I

HITACHI
Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819 • (415) 589-8300

No. QA641-023A/E
Type

HD64180

Item

WAIT Function at I/O Access

Div

o 4S 08S .8M 016M 0 Software
o Evaluation kitEmulator
'
OSD OSBC

Q

Classification
MMU

Is wait state (TW) always inserted when accessing I/O?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
0 WAIT

z
o

§
(/)

RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
Applicable Manual

A

Title
When accessing external I/O, a minimum of one wait
state is inserted.
When accessing on-chip I/O, zero to four wait states
are automatically generated depending on the status
of CPU and on-chip I/O.
(ASCI, CSI/O, PRT DATA register access)

I

HD64180
Data Sheet
Other Data
Title

J

Reference
No.

COMMENT

Q &A

I

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2219

No

QA641-0Z4A/E

04S 08S .8M 016M 0 Sof tware
Type

HD64180

Item

Div

o Evaluation

kit •
Emulator

OSD OSBC

Power-on Reset Sequence

Q

Classif ica don
MMU

How is the power-on reset sequence performed?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
0

RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS

I

A

Applicable Manual

The Power-on reset sequence is as follows.

I¢

Reset state

~
more than 6 clock

RESET
Address

COMMENT

"

~
Restart
•
Op-code Fe tch
TI
TZ
T3

;J

J

Title

J

HD64180
Data Sheet
Other Data
Title

J

cycles
High Impedance

~~

OOOOOH
Restart Address

Reference

No.

Q &A

I

J

RESET pin should be held low for more than 6 clock cycles.

Section
220 2

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589·8300

No. QA64l-025A/E
04S 08S .8M Ol6M 0 Software
Type

HD64l80

Div

o Evaluation

kit •
Emulator

OSD OSBC

Bus Status during Sleep Mode

Item
Q

Classification
MMll

What is the Bus status when the sleep instruction is
excuted?

DMAC
ASCI
CSI/O
TIMER

BUS INTERFACE
INTERRUPT
WAIT

z
o

@
C/)

RESET
0 LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
Applicable Manual

A

Title

I

The Bus status is as follows.
HD64l80
Data Sheet
Status

Address Bus

---------

High

Data Bus

3-state

Control signal

Inactive

(Ao - Al8 • 7FFFF)

Other Data
Title

J

Reference
No.

COMMENT

Q

&

A

J

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2221

No

-

QA641 026A/E

04S 08S .8M Ol6M 0 Software
Type

HD64180

Div

o Evaluation

kit

.

Emulator

OSD OSBC

Sleep Mode and System Stop Mode

Item

Classification

Q

MMU

What is the difference between sleep mode and system stop

DMAC

mode?

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
0

LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE

SD
SOFTWARE
OTHERS
Applicable Manual

A

Title
The major differences are as follows.
Mode

Sleep

System stop

function

CPU stop

CPU and internal I/O
stop

exit

Interrupt
(Internal/
External)
Reset

Other Data
Title

I

Interrupt
(External)
Reset

Reference
No.

COMMENT

I

HD64180
Data Sheet

Q

&

A

I

I

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

222

No QA64l-027A/E
04S
Type

HD64lS0

Div

oss

.SM Ol6M 0 Software

o Evalua tion ki Emulator
t •

OSD OSBC

Recovery from System Stop Mode

Item

Classification

Q

MMU

What is the system status after recovery from SYSTEM
STOP mode?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
0 LOW POWER MODE
REFRESH
CLOCK GENERATOR

ASE
SD
SOFTWARE
OTHERS
Applicable Manual

A
SYSTEM STOP mode is the combination of SLEEP and
10 STOP modes.
The SYSTEM STOP mode is exited by detection of
RMI or INf external interrupts only.
If interrupts are globally disabled (IEFl~O).
instruction execution begins with the instruction
following the SLEEP instruction.
If interrupts are globally enabled (IEFl-l). the
appropriate normal interrupt response sequence is
executed.

However. I/O STOP mode is maintained until the I/O
STOP bit is set to 0 after recovery from SYSTEM STOP

Title

I

HD64lS0
Data Sheet
Other Data
Title

I

Reference
No.

Q &A

I

mode.

COMMENT

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2223

No

QA641-028A/E

048 088 .8M DI6M. 0 Software
Type

HD64180

Div
DEvaluation kit'
Emulator

D8D D8BC

System Standby Function

Item

Classification

Q

MMU

Does the HD64180 have a system standby function
(stop clock) to reduce power consumption?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
0 LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
Applicable Manual
Title

A
No, clock stop function is not provided. Minimize
the clock frequency to reduce power consumption.
i

However, if clock is stopped completely, MPU
operation and data in the registers are not guaranteed.

J

HD64180
Data Sheet
Other Data
Title

I

Reference Q & A
No.
I

COMMENT

Section
224 2

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

No QA64l-029A/E
o4S OSS .SM ol6M 0 Software
Type

HD64lS0

Div
o Evaluation kit '
Emulator

oSD oSBC

Dynamic RAM Refresh during DMA.

Item

Classification

Q

MMU

Is DRAM refreshed during internal DMA operation?

DMAC
ASCI
CSI/O
TIMER

BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
0 REFRESH
CLOCK GENERATOR

,
A
Yes, refresh cycle is inserted during internal DMA
cycle.
Refresh controller does not distinguish DMA cycle
from CPU cycle.
Dynamic RAM refresh is performed at the end of
machine cycle during both CPU cycle and DMA cycle,
and the internal and duration of the refresh cycle
are programmable.

z
o

~

ASE
SD
SOFTWARE
OTHERS
Applicable Manual
Title I

Other Data
Title

I

Reference
No.

Q & A

I

COMMENT

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2225

o Software

No
04S 08S .8M016M
Type

HD64180

Div

o Evaluation

.

kit
Emulator

QA641 030A/E

OSD OSBC

Dynamic RAM Refresh

Item

Classification

Q

MMU

Is the refresh controller of the HD64180 different
from that of the Z80?

DMAC

What is the function of the R counter?

ASCI
CSI/O
TIMER
BUS INTERFACE
. INTERRUPT
WAIT
RESET
0

LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS

A
Yes, the refresh controller of the HD64180 differs from

that of the Z80. Refresh cycle is inserted or
suppressed by software. Also the internal and
length of refresh cycles are programmable.
The refresh address (8-bit address) is output at AO-A7'
MC
MC+l
Refresh cycle

.I.

.I.

Applicable Manual
Title I
HD64180
Data Sheet
Other Data
Title

,p

X

Address
REF

\
* Refresh

AO- A7

X
I

should be 3 cycles.

I

Reference

No.

Q & A

I

The R Counter counts the number of CPU op-code fetch
cycles and has no relation to dynamic RAM refresh.
COMMENT

Section
226 2

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

No
04S OSS .SM 016M
Type

HD64lS0

Div

o Evaluation

QA64l-03lA/E

o Software

kit '

Emulator

OSD OSBC

Trace Function of ASE

Item
Q

Classification
MMU

How is the trace information of ASE displayed on the
CRT?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
0 ASE

SD
SOFTWARE
OTHERS
Applicable Manual
Title

A
After excution of the Go or Step command, the trace
buffer pointer indicates the last trace data.
Specify display number with negative value until the
pointer corresponds with Trace Pointer.
After moving the Trace Buffer pointer with the Trace
Pointer Command, it is possible to specify the display
number with a positive value.
Trace Buffer
Trace Buffer

1] fi'~M'81
pointer

Trace Buffer
Pointer

COMMENT

tIncrement
with
negative value

I

HlSOASOl
User's Manua

Other Data
Title

I

Reference
- -The display
number can be
No.
specified
with either
a positive or
negative value.

Q Ii. A

J

I

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2227

No
D4s
Type

HD64l80

o 8S

.8M Dl6M

Div

0 Software

,

DEvaluation kit
Emulator
Item

-

OA64l 032A/E

DSD DSBC

Dynamic RAM Refresh of ASE
Classification

Q

MMU

Dynamic RAM is refreshed depending on the Refresh Control
Register programming.
Is the dynamic RAM refreshed during the wait state for
command input when using ASE?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
0 ASE

SD
SOFTWARE
OTHERS
Applicable Manual

A

Title
When using ASE, dynamic RAM refresh is executed as
follows by programming the Refresh Control Register.

I

Hl80ASOl
User's Manual

(1)

Refresh enable: REFE=l
If REFE bit is set to 1, dynamic RAM is refreshed

during waiting state for command input.
(2) Refresh disable: REFE-O
If REFE bit is set to 0, dynamic RAM is not
refreshed during wait state command input.
(But refresh cycle is inserted during trace.)

Other Data
Title I

Reference
No.

Q & A

J

COMMENT

I

Section

HITACHI

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228

No QA641-033A/E
04S 08S .8M 016M 0 Software
Type

HD64180

Div
DEvaluation kit '
OSD OSBC
Emulator

Difference between RET and RETI Instructions

Item

Classification

Q

HMU

What is the difference between the RET and RETI
instruction?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR

A
Both the RET and RETI instructions are used to return
to the main-program from a subroutine, and both
instructions have identical functions.
However, RETI instruction is normally used to return
from an external interrupt (IATQ, INTi or 1NT2)
service routine.
Since RETI is a two-byte instruction, peripheral devices
know the completion of the current interrupt service
routine during RETI execution especially when using the
daisy chain (Z80 Peripheral).
Also, when using an external interrupt, especially the
daisy chain, RET instruction is useful in identifying an
internal interrupt service routine.

COMMENT

ASE
SD
0 SOFTWARE
OTHERS
Applicable Manual
Title I
HD64180
Data Sheet
Other Data
Title I

Reference Q & A
No.
I

J

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300

Section

2229

J

No. QA64l-034A/E
04S
Type

HD64l80

Item

Div

o 8S

.8M Ol6M 0 Software

o Evaluation

kit '

Emulator

OSD OSBC

LD A, R/LD R, A Instructions
Classification

Q

MMU

Can the refresh address be read by executing a LD A, R

DMAC

or LD R, A instruction?

ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
OTHERS
Applicable Manual

0

A

Title
No, refresh address cannot be read by the LD A, R or

LD R, A instruction.

I

llD64l80
Data Sheet

The HD64180 incorporates a dynamic RAM refresh controller.
But the R counter indicates the number of CPU op-code
fetch cycles and has no relation to dynamic RAM refresh.

Other Data

Title

I

Reference Q
No.
I

COMMENT

&

A

I

Section'

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

230

No

QA64l - 036A/E

04S 08S .8M 016M 0 Software
Type

H064180

Item

Oiv

o Evaluation

kit '

Emulator

OSD OSBC

LDIR Instruction
C1assif ica tion

Q

MMU

What is the status of the bus cycle during LDIR

OMAC

instruction execution?

ASCI
CSI/O
TIMER
BUS INTERFACE'
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
0

SD
SOFTWARE
OTHERS

Applicable Manual

A

Title

I

14 instruction execution cycles are repeated.
The last execution cycle (BC-O) is 12 cycles.
If BC ~ 0, 14 instruction execution cycles are repeated.
If BC

= 0, 12 instruction execution cycles are repeated.

HD64180
Data Sheet
Other Data
Title

I

(refer to the following page)

Reference Q & A
No.
I

COMMENT

I

HITACHI
Hitachi America, Ltd,. San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2231

No

QA641-036A-2/E

045 085 .8M 016M 0 Software
Type

HD64180

Div

o Evaluation

.

kit
Emulator

OSD OSBC

LDIR Instruction

Item
Q

LDIR (ED Btl)
Operation

Bus cycle

~
\

(HL)m -> (DE)m
BCR-l ->BCR
DER+1 ->DER
HLR+l ->HLR
Repeat until BCR=O

X

IMC *
1st
Op code
fetch

2nd
Op code
fetch

X

HL

'IL~
Ti

DE

Ti

**
I

1st
Op code
fetch

c:

execution cycle

::1
\

1st
Op code
fetch

X

2nd
Op code
fetch

X

HL

X

DE

X
I

Last execution cycle (BC=O)

*
**

Section
232

2

1 machine cycle
machine cycle for internal operation

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

No. QA641-037A/E
Type

HD64180

Item

Div

o 4S D8S .8M D16M 0
o Evaluation kitEmulator
'

Software
DSD DSBC

E Clock during Sleep Mode or Bus Release Mode

Q

Classification
MMU

Is it possible to extend E clock pulse width by
inserting wait status (TW) during Sleep Mode or
Bus Release Mode?

A

I
No, since WAIT input is ignored during Sleep Mode or
Bus Release Mode, E clock cycle cannot be extended.

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CWCK GENERATOR
ASE
SD
SOFTWARE
0 OTHERS
Applicable Manual
Title I
HD64180
Data Sheet
Other Data
Title

I

Reference Q & A
No. I

COMMENT

I

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2233

No
D4S DSS .SM D16M
Type

HD641S0

Div
DEvaluation kit'
Emulator

Item

QA641-03SA/E

0 Software
DSD DSBe

E Clock Timing during DMA Cycles or Refresh Cycles
Classification

Q

MMU

What is .the E clock output timing during the DMA or
refresh cycle?

I

A
DMA access memory or I/O duration of E clock output
'High' is identical to the CPU.
Thus, the output timing is as follows.

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE
SD
SOFTWARE
0 OTHERS
Applicable Manual
Title I
HD641S0
Data Sheet
Other Data

M R/W cycle

T2t '" Ts'"

I/O read

1st TW t '" Ts'"

I/O write

1st TW t '" Tst

During refresh cycle clock output is held low.

COMMENT

Section

234

2

Title

J

Reference
No.' J

Q & A

I

HITACHI
Hitachi America, Ltd.· San Francisco Center- • 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

No

-

QA64l 039A/E .

D4S D 8S .8M Dl6M D Software
Type

HD64l80

Div
DEvaluation kit·
Emulator

Item

DSD DSBC

Internal I/O and External I/O Access
Classification

Q

MMU

How is internal I/O accessed if an external I/O address
conflicta with an internal I/O address?

DMAC
ASCI
CSI/O
TIMER
BUS INTERFACE
INTERRUPT
WAIT
RESET
LOW POWER MODE
REFRESH
CLOCK GENERATOR
ASE

A

SD
SOFTWARE
0 OTHERS
Applicable Manual
Title

(1)
(2)

Read case
Internal I/O is read.
Write case
Both internal and external I/O are written with
the same value.

T

HD64180
Data Sheet
Other Data
Title

I

Reference
No.

r

COMMENT

Q &A

I

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2235

Section
236 2

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

May, 1991

HD64180R/Z, HD647180X
Application Note

Working with Interrupts

Marnie Mar

Introduction
Hitachi's HD64180RlZ and HD647180X devices suit many
controller applications that take advantage of the services of
these devices' on-chip features. Such applications also
require interrupt handling to respond to events occurring in
the system.
This Application Note discusses details of the 64180 device's
interrupt prioritization and handling capabilities. Included
are examples of the use of the on-chip Asynchronous Serial
Communications Interface transmit and receive interrupts.

(EI) command. This sets the IEFI and IEF2 flags to 1. As
described in the hardware manuals, lEFi controls general
enabling and disabling of maskable interrupts (enabled when
IEFI = I). IEF2 manages the occurrence of NMI.
The 64180 maskable interrupts are enabled at two levels, a
general enable using the IEFI bits (controlled using the EI and
DI instructions), and an interrupt specific enable in either the
ITC or a on-chip control register. This combination of
enabling allows the user to control when each interrupt can be
accepted.

Interrupt Service Routines
This Application Note supplements information that is available in the 64180 family Hardware Manuals. For more
information on interrupts and details on the registers mentioned,pIeasereferto the Hardware Manual for the HD64180R/
Z or the HD647180X.

All vectored interrupts require a user-written interrupt service
routine (ISR) to execute the system response to the interrupt.
This routine should perform the following steps:

Enabling Interrupts

I. Save all registers used by the ISR, or swap to the alternate
register set using the EXX and EX AF,AF' instructions.

A hardware reset disables all interrupts except NMI and
TRAP, which arenon-maskable. The following steps must be
taken in order for the interrupt controller to accept and handle
maskable interrupts:
1. When using INTO Mode 2 or internal interrupts, load the
Interrupt Vector Register (I) with the most significant eight
bits of the 16-bit vector table address.

2. When using internal interrupts, load the Interrupt Vector
Low Register (IT..) to access to vector table.
3. For external interrupts, set the lTE2, !TEl and lTEO bits
of the INT/I'rap Control Register (ITC) to 1 to enable INTZ,
INTI and INTO respectively.
4. For internal interrupts, set the control register bits for the
function to enable the required in t~ rrupt. For instance, enable
the Transmit Interrupt for the Asynchronous Serial Communication Interface (ASCI) by setting bit 0 of the ASCI Status
Register (STAT) to 1. Bit 0 is the Transmit Interrupt Enable
(TIE) bit.
5. Finally, when the required vectors are initialized and
interrupts enabled, the CPU must execute the Enable Interrupt

2. Perform interrupt handling tasks, polling status bits as
necessary to determine the exact cause of the interrupt.
3. Restore registers saved or swapped.
4. Reenable interrupts using the EI command. When the CPU
accepts an interrupt, the IEFI flag is set to 0 preventing all
other interrupts from occurring. The EI command sets this
flag back to 1 to allow other interrupts to be accepted.
5. Return to the interrupted program using either RET or
RET!. Both perform the same function, butRETI is a two byte
instruction. Use RETI when interfacing to an external 1/0
device that decodes RETI to determine the end of an interrupt
service.

Interrupt Prioritization
The 64180 interrupts are prioritized in order from highest to
lowest as shown in the hardware manual for the particular
64180 device in use. When more than one interrupt occurs at
a time, this prioritization determines which interrupt is accepted and serviced.
Once the CPU accepts an interrupt and interrupt service

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2237

~

t3

lJl

E
..l1li

HD64180R/Z, HD647180X

Application Note

Main

1
INTO-+
request

INT1 -+
request

ASCI~

request

~

m

/wro .......

/

~

EI
-----RETI

~

~

INT1 service
INO A,(STATO) ; disable RX interrupt
ORF7
OUTO (STATO),A

EI

II

0(

INTO can be
accepted after here

(re-enable ASCIO receiver interrupt)
RETI

.
~ ASCIO service
_____
EI
<0(0('---- INTO and INTtcan b
accepted after here

·~~RETI
Figure 1 • Interrupt Prioritization

begins, no other interrupt can be accepted until theEI instruction is encountered in the executing interrupt service routine.
WhenEI executes, theIEFI Oag isset, and any new orpending
interrupt can be accepted.
Keep this in mind when setting up systems requiring nested
interrupts, or higher priority interrupts that should preempt
. lower priority interrupt service. The EI command can be
placedanywhereinaninterruptserviceroutine, with the result
of any enabled interruptbeing acceptable following EI execution.
The 6418O's interrupt prioritization allows the highest pending interrupt request to be serviced. but does not prevent a

lower priority enabled interrupt from being accepted during
ahigher priority interrupt service routine once EI is executed.
To prevent a lower priority interrupt from occuring in such a
case, disable this interrupt at the control register level during
the higher priority interrupt service routine.
Figure 1 shows an example of allowing higher priority
requests to interrupt a lower priority interrupt service routine.
In this example, INTO is generated by an external source to
signal an alarm condition that should trigger a response in
most cases, but sometimes is masked. INT2 should be
serviced without interruption, except when external circuitry
.triggers INTO. In addition, the system receives data through
the ASCI under interrupt control.

Section

HITACHI

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589·8300

238

Application Note

HD64180R/Z, HD647180X

Once the system has been initialized, only these three interrupts are enabled (INTO, INTI, and ASCIO). Since the INTI
service should not be interrupted by an ASCIO interrupt, this
routine should start by masking the ASCIO receive interrupt
by setting theRIE bit of STATO to 0 (this interrupt should be
reenabledpriortoretuming). The next step of this routine, and
the frrststep of the ASCIO service routine would be to execute
the EI command. This allows all other enabled interrupts to
be executed.

Asynchronous Serial Communication Interface
(ASCI) Interrupts
The 64180 ASCI channels can each generate an interrupt to
a separate vector location. The ASCI channels can be
programmed to generate an interrupt on either the receiver
condition, the transmitter condition, or both.
An interrupt can be generated by the receiver condition when
the receive data register is full (RDRF), or an overrun, parity

or framing error occurs. An interrupt can be generated by the
transmitter when the transmit data register is empty.
If both the receiver and transmitter interrupts are enabled for
an ASCI channel, this channel's interrupt service routine must
check to see which source caused the· interrupt. Do this by
polling the ASCI status register.

Interrupt driven serial data transfers can minimize CPU time
while maximizing data transfer rates. When using interrupt
driven data reception, data can be received into a buffer in
memory via an interrupt service routine. This memory buffer
can be accessed by the CPU when it is ready to read the data.

This frees the CPU from polling the ASCI receiver, and allows
the CPU to work on other tasks.
In terrupt driven data transmission can also minimize CPU
involvement. Place data to be transmitted in a buffer in
memory, and enable the transmit interrupt. Each time the
transmit data register is empty, an interrupt service routine is
executed. This routine takes a byte of data from the memory
buffer and places it in the transmit data register. The service
routine should disable the transmit interrupt when all the
memory buffer data has transferred.
Whether to use interrupt driven serial I/O depends on the
amount of data being transferred, and the relationship between the data transfer speed and the system operating speed. ~
For slower system speeds and faster data transfer rates. the i=
amount of time required to enter and process an interrupt ~
service routine may offer little benefit over a polling scheme.
Consider these parameters when choosing between interrupt
driven or polled schemes.

Summary
The HD64180R/Z and HD647180X devices provide users
with an interrupt controller with two levels of interrupt
enabling, fixed prioritization, and flexibility that allows nested
interrupts and preemption of lower priority interrupts by
higher priority requests.
Both off-chip interrupts and interrupts generated by the onchip peripheral functions can be handled. The ASCI interrupts. described in detail here, can be used to maximize data
transfer rates, while minimizing CPU time for controlling
these transfers.

HITACHI
Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2239

E
 came from and make it
the primary interface. All future
output is only sent through this
interface (before this point all output is sent to both interfaces).
To use the other interface the user
may perform a RESET and press
return on the terminal connected
to the other interface.

PC Memory Space

'180 I/O Space

OF

C481F

C4807
C4806

AOR

C4801
C4800

CMD

ADR
REL

Dr

1\

CMD

C7
C6

C1

CO

2. Selecting the PC Memory
Diagram 3 • SDPRAM register space mapping for regis.
Segment
ters used by this application
Sinee there are several segments
that the PC can use 10 map shared
memory we have to find out which is being used. This is done
a command line parameter when starting the NPU Client
at the hardware level and at the software level.
software on the PC.
At the hardware level the DIP Switch SW3 must have
positions 3 and 4 set to indicate the memory segment being

All four possible mapping schemes are supported as long as
both the hardware and software settings are correcL

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

Section

2243

Section
244

2

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

October, 1990

HD64180R,Z
Hardware Notes

180 Applications Board

Mamie Mar

The 64180 Applications Board (Aps Board) is a general
purpose CPU board that can be used as the basis for systems
designs using Hitachi or other manufacturer's peripheral
devices. This document discusses the hardware features of
this board, which are summarized below:
- HD64180R or Z operating at 9.216MHz
- SRAM (64K or 128Kword byte-wide device)
- EPROM (16Kbyte or larger device)

The board's memory decode logic supports chip selects for five
other blocks of memory. These select lines can be tied directly
to user add-on hardware.
The SRAM and User Memory spaces are accessed through the
MMU bank area. Portions of each section are accessed by
programming the MMU's Bank Base Register (BBR) with the
information that causes the desired area of memory to be
addressed.
z
The areas indicated by cross-hatching should not be used for
User memory space, since the decode logic allows these
spaces to be overlayed by Aps Board memory spaces. For
instance, if a 27256-type EPROM is used (8000h bytes), the

- HD63310 Smart Dual Port RAM
- PC bus interface with selectable address space
- RS-232 level interface from 64180 ASCI port to DB-9
- Memory decode logic for 5 additional memory spaces

FFFFh
Common Area 1
f-----------j

- I/O decode logic for 6 additionalI/O spaces
Logical Memory Map
The 64180's Memory Management Unit (MMU) is used to
access a larger than 64Kbyte memory space. The memory
space has been defined assuming that the MMU's logical
space is assigned at reset, and not changed during the course
of program operation. This logical space assignment is shown
in Figure 1. Although some of the information to follow
assumes that this logical space setup will be used, keep in
mind that this setup is defined by software, and can be
modified.

EOOOh

Bank Area

f-----------j

3000h

Common Area 0
'--_ _ _ _ _ _---' 0000h

Physical Memory Map
The board's physical memory map is shown in Figure 2. The
EPROM space is assigned to low memory, which allows it to
be accessible as Common Area 0 at all times. The SDPRAM
space is assigned to high memory, and is accessible through
Common Area 1.
The SRAM, although it consists of a contiguous block of
memory, is accessed in two separate areas of the physical
memory. See the section on RAM Memory Map for more
information.

Figure 1 • Logical Memory Space

device will be activated for addresses OOOOh-7FFFh, SOOOhFFFFh, lOOOOh-17FFFh, etc., since the EPROM is chip selected for all physical addresses in the range OOOOOh-2FFFFh,
and the device responds address lines AO-AI4.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2245

E

§ .
(f)

HD64180R,Z

Application Note

Physical I/O Space
The Aps Board I/O space is shown in Figure 3. The SDPRAM
control registers have been mapped into locations CO-FFh.
HD64180RlZ on-chip I/O registers are mapped into locations
00-3Fh.

FFFFh

Pdditionall/O Space

The locations identified as 100,101, etc. are those that can be
accessed using chip-select signals generated by I/O decode

0200h

IOJ
101
102
103
SDPRAM Registers
105
105
107 -on-chip I/O

r~
FFOOOh

FE800h
FEOOOh

01COh
018a"t
014al
01001
00C0h
0000h

004al
0000h

Figure 3 - System I/O llllap

EOOOOh
MCS4

MCS3
MCS2
MCS1

MCSO

COOOOh

logic. The remaining I/O space is available for other system
use.

AOOOOh

RAM Space
The RAM space is divided into two areas, one accessible
through the bank area, and one accessible through Common
Area 1. The bank area RAM would most likely be used for
download of user code. The area accessed through Common
1 serves two purposes -one area (FEBOOh-FEFFFh) is used by
the monitor forscratchpad RAM, the remaining area (FEOOOhFEAFFh) can be allocated by the user.

80000h

60000h

~

If 64Kbytes of RAM are used, physical locations 2EOOOh2EFFFh are accessed through Common 1 for scratchpad and
high user RAM.

User RAM

1--_ _ _ _ _ _- - I

2OOOOh

Monitor EPROM

00000h

_

OterIay area - do not use

Figure 2 - System Memory Map

Using the MMU set-up described earlier, physical RAM
locations 3FOOOh-3FFFFh cannot be accessed by the processor, since this area overlays the logical memory space allocated to the SDPRAM. All other RAM areas can be accessed
by loading the MMU Bank Base Register (BBR) with the
appropriate address. For instance, to access physicallocalions 20000h-2AFFFh through the logical Bank Area located
from 3000H-DFFFh, program the BBR with lDh.

SDPRAM Use
TheHD6331OisaIKbyteSmartDuaiPortRAM(SDPRAM)
device which is used by the Aps Board for communication

Section

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246

HD64180R,Z

Application Note

LOOICAL
EtOOl- ; ;

PHYSICAL

~-I!I!~~1MJrj"1Il TO BE WRITTEN BY DMA

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2265

HD64180S

Application Note

Appendix C . NPU Initialization Routine (continued)
;

DEFB
RX BUFFER 2
ORG
DEFW
DEFW
DEFB
DEFB
DEFW
DEFB
DEFB
RX BUFFER 3
ORG
DEFW
DEFW
DUB
DEFB
DEFW
DEFB
DEFB
RX BUFFER 4
ORG
DEFW
DEFW
DEFB
DEFB
DEFW

; RESERVED
1l0H
120H
320H
00

; STARTING ADDRRESS OF NEXT DESCRIPTOR' 120H
; LOWER 16 BIT OF RX BUFFER POINTER - 320H

120H
130H
340H
00

; STARTING ADDRRESS OF NEXT DESCRIPTOR - 130H
; LOWER 16 BIT OF RX BUFFER POINTER - 340H

HIGHER 4- BIT OF 20 BIT RX BUFFER POINTER - 00
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS ==-> TO BE WRITTEN BY DMA
RESERVED

HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER - 00
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS ===> TO BE WRITTEN BY DMA
RESERVED

130H
140H
360H
00

STARTING ADDRESS OF NEXT DESCRIPTOR· 140H
LOWER 16 BIT OF RX BUFFER POINTER = 360H
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER = 00
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS """"=> TO BE WRITTEN BY DMA
RESERVED

DEFB
DEFB
RX BUFFER 5
ORG
DEFW
DEFW
DEFB
DEFB
DEFW

140H
150H
380H
00
0

; STARTING ADDRRESS OF NEXT DESCRIPTOR = 150H
; LOWER 16 BIT OF RX BUFFER POINTER = 380H
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER
RESERVED

DEFB
DEFB
RX BUFFER 6
ORG
DEFW

DEFW
DEFS
DEFB
DEFW
DEFB
DEFB
RX BUFFER 7
ORG
DEFW
DEFW
DEFB

00

STATUS

===> TO BE WRITTEN BY DM

RESERVED
150H
160H
3AOH
00
0

160H
170H
3COH
00

DEFB
DEFW
DEFB
DEFB
RX BUFFER 8
ORG
DEFW
DEFW
DEFB
DEFB
DEFW
DEFB
DEFB

=

DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA

; STARTING ADDRRESS OF NEXT DESCRIPTOR = 160H
; LOWER 16 BIT OF RX BUFFER POINTER = 3AOH
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER = 00
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DM
STATUS ===> TO BE WRITTEN BY DMA
RESERVED

;
;

STARTING ADDRRESS OF NEXT DESCRIPTOR = 170H
LOWER 16 BIT OF RX BUFFER POINTER = 3COH
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER = 00
RESERVED

DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS ===> TO BE WRITTEN BY DMA
RESERVED

170H
100H
3EOH
00
0

; STARTING AODRRESS OF NEXT' DESCRIPTOR =' 1 DOH
; LOWER 16 BIT OF RX BUFFER POINTER = 3EOH
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER = 00
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS ===> TO 8E WRITTEN BY DMA
RESERVED

; ** ** ,,********* ******** ** ** ** ** ** ** ** 1r * ** ** "'* "'''' '" '" * *" *'" **
CTSframe initializ~tion
; **** ****** ************ ** ** ** ** "'* ** **" ****-* *"'" * *" ** ** ** **
CTSframe:
DEFB
; reserved for dest addr
DEFB
STAADDR ;source addr is self

Section

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266

HD64180S

Application Note
Appendix C - NPU Initialization Routine (continued)
;CTSframe type

8Sh

DEFB

; ***. ** **** ** ** ** .:It"' •• "''''. ** '" '" ** .. '" ** ** "' .. '" '" * * .. '" * '" ** '" '" "' .. '" *
TRANSMIT DESCRIPTOR SET UP

; ***'" ** ****** ** ********** ** ** ** ..... * ** ** ** ** ..... * **** ** '" *
;

TX BUFFER
ORG

TXOESCR: :
OEFW
TXOESCBUF: :
DEFW
DEFB
DEFB
TXDESCT: :
DEFW
DEFB
DEFB

4000H

4000H

STARTING ADDRRESS OF NEXT

OOOOH
00
0

LOWER 16 BIT OF TX BUFFER POINTER = TBD
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER
RESERVED

00

DATA LENGTH OF BLOCK 1 TO BE WRITTEN TX Prog
81H
0

STATUS EOM, EaT INCLUDED
RESERVED

; ** *** *** ** **** .. '" ****** *** .. ** .... * "' .. "' .. '" * '" "' .. '" '" '" '" ** .. ** ** ** "' ..
It

MSCI initialization

cseg
_NPUINIT: :
DISABLE WAIT STATE/REFRESH
LO

OUTO
aUTO
aUTO
OUTO

aUTO
aUTO
aUTO
aUTO

A,OOh
(WCRL) ,A
(WCRM) ,A
(WeRH) ,A
(lOWeR) ,A
(INTWR) ,A
(RWCR) ,A
(RCR) ,A
(OF4h) ,A

;disable transmit driver

TRANSMITTER AND RECEIEVER SET UP
LD
A,21H
OUTO (MCMD), A
LD
A,87H
OUTO (MMDO) , A

LD

CHANNEL RESET
BIT-SYNC HOLC,AUTO ENABLE=O,
; CRC-CCITT=l INITIALLY

A,40H

OUTO (MMDl) , A
LD
A,OCOH
OUTa (MMD2), A

Single ADDRESS CHECKED
FULL DUPLEX,

A,91H
LD
aUTO (MCTL), A

TxRDY ON NOT FULL, -RTSM=HIGH
ABORT ON IDLE & UNDERRUN

LD
A,70H
aUTO (MRXS) ,A

LD

FMO CODE,
; xB ADPLL CLK

RXCM FROM BRG

(AOPLL ap. CLK)

A, DOH

aUTO (MTXS), A
LD
A, 05H
aUTO (MTMC) ,A

TXCM FRaM
;

SET TMC=5

~>

BAUD RATE

; for appletalk test ing
LD

A, OOOH

aUTO (MIEO) ,A
LD
A,83H
aUTO (MIEl),A
aUTO (MFIE), A
LD
A, STAADDR
aUTO (MSAO) , A

TXINT AND RXINT DISABLED
UNDERRUN,ABORT, IDLE DETECTION
; INTERRUPT disABLED

SET SECONDARY STATION ADDRE.SS

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2267

HD64180S

Application Note

Appendix C - NPU Initialization Routine (continued)
LD
A/7EH
OUTO (MIOL) ,A

;

SET FLAG PATTERN "" 01111110 AS

; IDLE PATTERN

; "''''''''''''''''''''''*''''''''''''''' *'" ********** ** ********** ** *'" "'''''''''' "'II' "'* "''''It''''''
OMA CHANNEL 0 SET UP
; ""II'

(RECEIVER)

"'''''''''''''."'''''''*.* **.*"''''_._. "' __ "'*"''''''' "'* * "''''''' . . * "'II' **** "'*
LD
OUTO

A,96H
(DMRAO) ,A

LD
OUTO

A/O

LO
OUTO
LO

A,70H
(EOAOL) ,A
A,OlH

(CPBO) ,A

OUTO

(EOAOH) ,A

LD
OUTO
LD

A,OOH
(CDAOL) ,A
A,OlH

OUTO

(CDAOH) ,A

LO
OUTO

A,Sdh
(BUFLOL) ,A

LD

A,02h

OUTO

10
OUTO

OUTO

"''''''''II '"

4 HIGHER BIT OF THE
20-BIT DESCRIPTOR ADDR

l70H
STARTING ADDR (LOW-ORDER
16 BITS) OF THE
RX DESCRIPTOR 8

lOOH
STARTING AOOR (LOW-ORDER
16 BITS) OF THE
FIRST RX DESCRIPTOR

(BUFLOH) ,A

ALLOWING 600 BYTES IN
EACH RX BUFFER

A,40H
(DIRO),A

DMA CHANNEL 1 SET UP

LD

"'II'

OMA MODE REGI STER A
MSCI, CBSA,
Mscr ->MEMORY, MULTI FRAME

EOM INTERRUPT ENABLED

(TRANSMITTER)

A,098H
(DMRAl) ,A

DMA MODE REG I STER A
MSCI, CHAINED,

MEMORY->MSCI, SINGLE FRAME

10
OUTO

A,O
(CPBl) ,A

LD
OUTO
LD

(EDAlL) ,A
A,40H

OUTO

(EDA1H) ,A

LO
OUTO
LD
OUTO

LD
OUTO

4 HIGHER BIT OF THE
20-BIT DESCRIPTOR ADDR

A / 20H

A, DOH
(COArL) ,A
A / 40H

(CDAlH) ,A

4020H
STARTING ADDR (LOW-ORDER
16 BITS) OF THE
DESCRIPTOR NEXT TO THE
LAST TX BUFFER

4000H
STARTING ADDR (LOW-ORDER
16 BITS) OF THE
FIRST DESCRIPTOR OF THE
FIRST TX BUFFER

A,OOH
(OIRl) ,A

EOT INTERRUPT DisABLED

Enable DMIBO interrupts
LD
OUTO

A,OSh
(IERl) ,A

;enable flags

EI

JP

,DMIBO

receive

; receive frames

Section

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268

HD64180S

Application Note
Appendix C - receive routine
/**********************************************************/
/* This file processes the packet data received using
*/
1* ReceivePacket
*/
1* Calls:outportO - compiler routine to output to an I/O port
*/
/* Enables DMA controller for receiving frames
*/
/* Manages circular receive descriptors
*/
/**********************************************************/

#include "Itdefs.h"
char octet, anAddress, aLAPtype;
char aDataField[maxFrameSize];
char MyAddress, fCTSexpected, fAdrValid, fAdrlnUse;
charmemory[605];
int rcvStatus, i;
int outgoingLength, incomingLength;
char dstParam,srcParam,typeParam,dataParam;
int dataLength;
struct structFrame ACKframe, *incomingPacket;
struct Descriptor *rxDescrPtr; /* global storage address of current descriptor */
receive()
char dstParam,srcParam,typeParam,dataParam;
int dataLength,descrNumber;
char *dataFrame;
charEDAvalLo,EDAvaIHi;
unsigned int EDAaddr;
/* simulate that address has been checked out on network */
fAdrValid=TRUE;

/* receiver does not expect CTS until RTS is received */
fCTSexpected = FALSE;
/* for this example, a node address is selected
in actual cases, network inquiries would be used
to select an check for an unused node number

*/

My Address = Ox44;
/* enable DMA ch 0 operation for receiving frames */
outport(DSRO,Enable);
/* enable MSCI receiver */
outport(MCMD,RXenable);
/* place receiver in Search Mode */
outport(MCMD,EnterSearch);
descrNumber= 0;
/* zero out rcvStatus counter */
rcvStatus = 0;

HITACHI
Hitachi America, Ltd,· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2269

HD64180S

Application Note

Appendix C - receive routine (continued)
do
{

rxDescrPtr = &rxDescript[descrNumberJ;
while (rcvStatus == 0);
dataFrame = (*rxDescrPtr).BufferPtr;
dataFrame = dataFrame+5; /* skip address info */
incomingLength = «*rxDescrPtr).DataLength - 5);
/* move frame data to memory location accessed by
application */
if(incomingLength > 3)
(
for(i=O;i= Ox80)
(
switch{templ)
{
case JapRTS :
CTSframe.destAddr={*structPacket).srcAddr;
/**********************************************************/

/*
/*
/*
/*
/*
/*

*/
*/

TFCODE.asm

*/

Code segment to transfer a frame
(for CTS response to RTS)
In-line assembly code

*/
*/

/**********************************************************/

!lasm
mstatO:
mcomd:

equ
EQU

02lH
02AH

Dstatl:

EQU

OSOH

DMA STATUS REG CH

txdrv:
TXDen:
TXDdis:
TXen:
DMACen:

EQU
EQU
EQU
EQU
EQU

OF4H
OlSH
OOSH
002H
002H

NPU board control register
enables tx drivers on npu bd
disables tx drivers on npu bd
enables tx of MSCI
enables DMAC channel

extern

;
;

;

;
;

MSCI Status Reg
MSCI COMMAND REG
1

TXDESCBUF,TXDESCT

assembly entry code
push
af
push
bc
push
hl
ld
outO
ld
ld
ld
ld

a,l2h
(2Ah), a
hl,CTSframe
(TXDESCBUF),hl
a,03h
(TXDESCT),a

;disable receiver
;load address of structure (ptr)
;place this in tx descriptor
;load count of bytes to transfer
;place this in tx descriptor

enable transmit drivers for 1.5 bit times
tftime:
LD
LD
aUTO

A,5
B,TXDen
(txdrv) , B

;prepare to count 1.5 bit times
;enable transmit drivers

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

Section

2277

HD64180S

Application Note

Appendix C - ReceiveFrame Routine (continued)
TLOOP1:

SUB
JR

;decrement A for timing
;loop until timeout

1

NZ,TLOOP1

disable transmit drivers for 1.5 bit times
LD
A,5
LD
B,TXDdis
;disable transmit drive
OUTO (txdrv) ,B
TLOOP2:
;decrement A for timing
SUB
1
JR
NZ,TLOOP2
;loop until timeout
enable transmit for 1 byte time (flag)

TLOOP3:

LD
LD
OUTO
LD
OUTO
SUB
JR

A,28
B,TXDen
(txdrv) ,B
B,TXen
(mcomd),B

;enable transmit drive
;,enable transmit

1

NZ,TLOOP3

;loop until timeout

enable DMAC to load TX buffer

ENDLP:

LD
OUTO

B,DMACen
(Dstatl) ,B

;enable DMAC channel 1

INO
AND
JR

A, (mstatO)
02h
Z,ENDLP

;wait for end of frame

wait for all chars and CRC to transmit

TLOOP4:

LD
SUB
JR

A,OAOh
1

NZ,TLOOP4

;prepare for abort string
; 12 bit times
;loop until timeout

disable transmitter
LD
B,03h
OUTO (mcomd) ,B
wait for NULLs to transmit as Abort sequence

TLOOP5:

LD
SUB
JR

A,43h
1

NZ,TLOOP5

;12 bit times
;loop until timeout

disable transmit drivers
LD'
OUTO

Section
278 2

B, TXDdis
(txdrv) ,B

;disable transmit drive

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD64180S

Application Note
Appendix C - ReceiveFrame Routine (continued)
; re enable receiver, and enter search mode
LD
outO
LD
outO

B,12h
(2ah) , b
B,3lh
(2ah) , b

pop
pop
pop

hl
bc
af

#endasm
RcvFrame = lapRTSframe;
break;
case lapENQ : RcvFrame = lapENQframe;
break;
case lapACK : /* Note ACK portion should be handled as RTS is to meet IFG requirements */
RcvFrame = lapACKframe;
fAdrlnUse = TRUE;
break;
case lapCTS :
if(fCTSexpected)
RcvFrame=lapCTSframe;
else
{
fAdrlnUse = TRUE;
RcvFrame = badframeType;
break;
default: RcvFrame = badframeType;
}
else
RcvFrame = lapDATAframe;
}

else if «"'structPacket).srcAddr != OxFF)
(
fAdrlnUse = TRUE;
RcvFrame = noFrame;
else RcvFrame = noFrame;
retum(RcvFrame);
}

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

Section

2279

HD64180S

Application Note

Appendix C - TransmitFrame Routine (continued)
/**********************************************************/

r

~

/* transmitFrame - transmits a single LLAP frame

*/

/* Based on procedural model in Inside AppleTalk

*/
*/

r

~

/* Calls; tftimeO, disableRxO,ResetMissingClockO

r

~

/**********************************************************/

#include "Itdefs.h"
extern unsigned int TXDESCR;
/* address of tx descriptors*/
extern tftimeO,disableRxO,ResetMissingClockO;
transmitFrame(strucptr,framesize)
struct structFrame *strucptr;
int framesize;
struct Descriptor txDescript,*txDescrPtr;
int mode;
/* Disable Receiving, since link is shared */
disableRxO;
/* Initialize TX Descriptor */
txDescrPtr = &TXDESCR;
(*txDescrPtr).BufferPtr strucptr;
(*txDescrPtr).DataLength = framesize;

=

tftimeO;
/* generate synchronizing pulse */
/* S tart frame transmission */
/* allow one flag byte to transmit */
/* enable DMAC to start transfer of data */
ResetMissingClockO;
enableRxO;

Section

HITACHI

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280

HD64180S

Application Note
Appendix C . Timing related routines for transmitting frames
*********************************************************

tftime - transmit frame timing related routines
called by TransmitFrame
generates missing clock signal by enable and disable
of transmit driver
enables transmitter for one byte time to allow two
flags to transmit
enables DMAC channel 1 to load MSCI with transmit data
reprograms MSCI to output MARK in idle state
waits for end of transmission
at end of frame, allows approx. 12 bit times of mark
for LLAP Abort sequence requirement
npu io address assignments 10-11-88 06:23:00
MCMD:
MCTL:
MIDL:
MST2:

EQU
EQU
EQU
EQU

02AH
02EH
031H
023H

DSR1:
DMRA1:
DMRB1:
DIR1:
DCR1:

EQU
EQU
EQU
EQU
EQU

080H
081H
082H
084H
08SH

NPUreg:
TXDen:
TXDdis:
TXen:
DMACen:

EQU
EQU
EQU
EQU
EQU

OF4H
018H
008H
002H
002H

MSCI COMMAND REG
MSCI CONTROL REG
MSCI IDLE PATTERN REG
MSCI Status Register 2

;

DMA
DMA
DMA
DMA
DMA
;
;
;
;
;

STATUS REG CH 1
MODE REG A CH 1
MODE REG B CH 1
INTERRUPT ENABLE REG CH 1
COMMAND REG CH 1

NPU board control register
enables tx drivers on npu bd
disables tx drivers on npu bd
enables tx of MSCI
enables DMAC channel

;******************************************************

public tftime
cseg
enable transmit drivers for 1.5 bit times
tftime:

TLOOP1:

LD
LD
OUTO
SUB
JR

A,S
B,TXDen
(NPUreg),B
1
NZ,TLOOP1

;prepare to count 1.5 bit times
;enable transmit drivers
;decrement A for timing
; loop until timeout

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

Section

2281

HD64180S

Application Note

Appendix C - Timing related routines for transmitting frames (continued)
disable transmit drivers for 1.5 bit times
LD
A,5
LD
B,TXDdis
OUTO (NPUreg),B
;disable transmit drive
TLOOP2:
SUB
1
;decrement A for timing
JR
NZ,TLOOP2
; loop until timeout
enable transmit for 1 byte time (flag)

TLOOP3:

LD
LD
OUTO
LD
OUTO
SUB
JR

A,28
B,TXDen
(NPUreg), B
B,TXen
(MCMD) ,B
1
NZ,TLOOP3

; enable transmit drive
;enable transmit
;loop until timeout

enable DMAC to load TX buffer

ENDLP:

LD
OUTO

B,DMACen
(DSR1) ,B

;enable DMAC channel 1

INO
AND
JR

A, (MST2)
02h
Z,ENDLP

;wait for end of frame

wait for all chars and CRC to transmit

TLOOP4 :

LD
SUB
JR

A,OAOh
1
NZ,TLOOP4

;prepare for abort string
;12 bit times
;loop until timeout

disable transmitter
LD
B,03h
OUTO (MCMD),B
wait for NULLs to transmit as Abort sequence

TLOOP5:

LD
SUB
JR

A,43h
1

NZ,TLOOP5

;12 bit times
;loop until timeout

disable transmit drivers
LD
OUTO

B,TXDdis
(NPUreg),B

;disable transmit drive

return to transmitFrame routine
RET

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

282

HD64180S

Application Note
Appendix C • NPU Hardware Interface Routines
/**********************************************************/
~

~

/* This file contains global variable declarations
/* and NPU hardware interface routines
/* Filename: NPUhwrt.c

*/
*/
*/

~

~

/**********************************************************/

#include "Itdefs.h"
int CarrierSenseO

/* Reads MSTl and returns FLGD bit: (p. 145)
I: Flag detected
0: No flag detected

*/

int MSCIStatRegl, status;
MSCIStatRegl = inport(MSTl);
status = (MSCIStatRegl & SYNCDmask);
retum(status);

iot RcvDataAvailO
/* Also referred to as RxCharAvail */
/* Reads MSTO and returns RxRDY bit: (p. 141)
I: data in rx buffer
0: no data in rx buffer

*/

int MSCIStatRegO, status;
MSCIStatRegO == inpon(MSTO);
status = (MSCIStatRegO & RXRDYmask);
return(status);

iot OverRunO

/* Reads MST2 register and returns OVRN bit:
I: Overrun error detected
0: No overrun error detected

(p. 150)

*/

int MSCIStatReg2, status;
MSCIStatReg2 = inport(MST2);
status = (MSCIStatReg2 & OVRNmask);
retum(status);

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2283

HD64180S

Application Note

Appendix c· NPU Hardware Interface Routines (continued)
int EndOtFrameO

/* Reads MSTZ register and returns EOM bit:
1: End ofreceive frame detected
0: Receive frame end not detected

(p. 150)

*/

int MSCIStatReg2, status;
MSCIStatReg2 = inport(MSTZ);
status = (MSCIStatReg2 & EOMmask);
retum(status);

intCRCokO

/* Reads MSTZ register and checks CRC bit:
1: CRC error detected, return 0
0: no CRC error detected, return 1

(p. 150)

*/

int MSCIStatReg2, status;
MSCIStatReg2 = inport(MSTZ);
status (MSCIStatReg2 & CRCmask);
if (status)
return(FALSE);
else return(TRUE);

=

void resetRxO

/* Resets and reenables receive by issuing commands
to the MCMD register (p. 137)

*/

outport(MCMD ,RXreset);
outport(MCMD,RXenable);
}
void enableRxO
/* reenables receive by issuing commands
to the MCMD register (p. 137)

*/

outport(MCMD,RXenable);

void disableRxO

/* Disables receive by issuing commands to the MCMD reg. */
(

outport(MCMD ,RXdisable);

Seclion
284 2

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HD64180S

Application Note
Appendix C - NPU Hardware Interface Routines (continued)
void EnterSearchModeO
/* Issues Enter Search Mode command to the MCMD register */
outport(MCMD,EnterSearcp);

char rxDATAO
/*retums a character of data from the MSCI receive buffer*/
char data;
data = inport(MTRB);
retum(data);

void enableTxO
/* enables transmit by issuing commands to the MCMD register

(p. 137)

*/

outport(MCMD,TXenable);

void enableTxDriversO
/* enables Tx drivers by writing to hardware register on NPU
board (p. 18 of Dev Board UM) */
char data;
data = inport(NPUreg);
data = data I Oxl0;
outport(NPUreg,data);
void disableTxDriversO
/* disables Tx drivers by writing to hardware register on
NPU board (p. 18 of Dev Board UM) */
char data;
data = inport(NPUreg);
data = data & OxOEF;
outport(NPUreg,data);

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Section

2285

HD64180S

Application Note

Appendix C - NPU Hardware Interface Routines (continued)
char endoITXO
/* polls DMA ch 1 status register 1 (DSRI) to check for End
of Frame condition (p.576) */
char data;
data = inport(DSRI);
data data & Ox40;
retum(data);

=

void enableDMACIO
/* enables DMAC to MSCI ttansfer for ttansmit data */
outport(DSRl,DMACenable);

Section

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286

HD64180S

Application Note
Appendix C - Miscellaneous Routines
/**********************************************************/

/* Miscellaneous Functions */
#define
#define
#define
#define
#define
#define
#define
#define
#define

FALSE
CMF
TCSRO
TCONRO
TCNTO
TMRenable
IDGslottime
MST3
MCn

OxOO
7
Ox52
Ox5l
Ox50
Ox12
100.0
Ox24
Ox2e

intrval;
int bitCount(bitVector)
int bitVector;
int

sum;

sum = BIT(&bitVector.O);
sum = sum + BIT(&bitVector.l);
sum = sum + BIT(&bitVector,2);
sum = sum + BIT(&bitVector.3);
sum = sum + BIT(&bitVector,4);
sum = sum + BIT(&bitVector.5);
sum = sum + BIT(&bitVector.6);
sum = sum + BIT(&bitVector.7);
return(sum);

int min(vall. val2)
intvall.val2;

/* BIT is a function which returns a bit value(specified by 2nd parameter) */
/*
from a bit vector (address specified as 1st parameter */

/* returns the minimum of two values */

if (vall < val2)

return(vall);
else return(vaI2);

int max(vall.vaI2)
nt vall.val2;

/* returns the maximum of two values */

if (vall> val2)
return(vall);
else return(vaI2);

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Section
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HD64180S

Application Note

Appendix C . Miscellaneous Routines (continued)
float random (maxval)
intmaxval;

/* returns a simulated random value based on the value in the NPU R register */

extern int rval;
float randval,floatslot;
#asm
ld
a,r
ld
(rval),a
#endasm
randval=maxval*«float)rval/(float)127);
randval=(randval*IDGslottime )n76;
return (randval);
)
void timerInit(seed,enable)
char seed,enable;

1* initializes the NPU timer channel 0 */

outport(TCONRO,seed);
outport(TCSRO,enable);

/* polls the NPU timer channel 0 for timeout condition */

char timeoutO
( int status;

/* disables timer when timeout detected */

=
=

status inport(TCSRO);
status BIT(&status,CMF);
if(status)
(
inport(TCNTO); /* clear CMF */
outport(TCSRO,OxOO);
} /* disable counter */
return(status);

void ResetMissingClockO

/* generate negative pulse on /RTSM output line */
/* causes reset of external missing clock circuitry */

outport(MCTL,Ox80);
outport(MCTL,Ox81 );

char MissingClockO

/* reads state of output of missing clock circuitry */

/* if /CTSM high, then detected */
(

return(IBIT(MST3,Ox03»;

Section
288 2

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January, 1990

HD64180S (NPU)
Application Note

Chained Block Transfer DMA
Introduction
Hitachi's HD64180S Network Processing Unit (NPU) combines the 64180 8-bit CPU core with a set of on-chip peripherals which provide the user with high-integration communications control capability. The on-chip peripherals include a
Multi-protocol Serial Communications Interface (MSCI)
which can support Asynchronous, Byte Synchronous and Bit
Synchronous communications protocols. To assist in han-

Mamie Mar, Jun Tsong, Tom Yu
dling data transmitted and received by the MSCI, the NPU
also includes a two-channel Direct Memory Access Controller(DMAC}.
The DMA capability provided on-chip includes standard
DMA functions such as single and dual address transfers of
data using external or auto (program generated) requests. In
addition, when using Bit Synchronous protocols such as
SDLC with the MSCI, the DMAC is capable of transmitting

~

r-------------------------------------------------------------------------------, 5
UJ

C/)

NPU DMAC

SYSTEM MEMORY

DMA
Control
Registers

SAB
BAB
BCB

Descriptor

Buffer

G#1J~~iiil.iiiim~iiiiiiiil ] ~BFL

EPA

l

1stframe
received

#5

BEL

SAR: Source Address Register
DAR: Destination Address Register
BAR: Butler Address RegislBr
BCR: Byte Count Register

DESCRIPTOR CONTENTS:
• Address pointer to next desaiptor
• Number of data bytes transferred (loaded following end of frame or end of buffer)
• Beginning address of current buffer (placed in BAR)
• Status byte (loaded from MSCI status following transfer)

EDA: Error Descriptor Address Register
CDA: Current Descriptor Register
BFL: Buffer Length

Figure 1 - Receive Data storage using MSCI and DMAC

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Section

2289

E
~

HD64180S

Application Note

NPU DMAC

SYSTEM MEMORY

DMA
Control
Registers

Buffer

ISAR (BAR) I

I
I

DAB
BCR

I
I

G:=l~~:~·:··,!j!i·~@;:.!·i'l
",

lstframe
transmitted

H::::::::~::m:H

J

Descriptor
Control
Registers

I

]

2ndframe
transmitted

CDA

I~~~~~-t....r-l1C;~=~~~~l>.·'
EDA
.....

vl

BEL.

SAR: Souroe Address Regisler
DAR: Destination Address Regisler
BAR: Buffer Address Regisler
BCR: 8yIe Count Regisler

Nolready
forDMA

I

DESCRIPTOR CONTENTS:
• Address poinler to next descriptor
• Number of data bytes transferred (loaded to BCR prior to start of buffer transmission)
• Beginning address of current buffer (placed in BAR)
• Slatus byte (read by DMAC 10 determine if buffer contains end of frame and/or transmission»

EDA: Error Desaiptor Address Regisler
COA: Current Descriptor Regisler
BFL: Buffer Length

Figure 2 • Accessing transmit data usind MSCI and DMAC
data from and receiving data into a series of blocks, or buffers,
in memory. This capability is provided by an internal
connection between the DMAC channel 0 and the MSCI
receiver, and channell and the MSCI transmitter.
These memory buffers can be located anywhere in the 1
MByte memory space accessible by the NPU. Once initializationoftheDMACandatableinRAMdefiningthememory
buffers occurs, data transfer and buffer management proceeds
without further CPU intervention.
This Application Note discusses the details of this DMAC
capability, refered to as the Chained-block Transfer Mode. A
simple example program using the MSCI to transfer data
using this mode is also discussed, and the program code is
included as an example.

Section
290 2

NPU's Buff~r Management Scheme
The NPU can dynamically allocate individual buffers in
various locations in system memory as the source or destination for DMA transfers. These buffers are identified when the
user initializes a table of information in memory which
contains an entry for each buffer. Each entry, called a
descriptor, contains attributes such as starlofbuffer location,
link pointer to the address of the next buffer's descriptor,
buffer size, and buffer status. Using this descriptor table, the
DMA channel can autonomously handle Bit Synchronous
protocol data transfers between the MSCI and the memory
buffers.
The size of buffers used depends on the application. Bit-

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HD64180S

Application Note
oriented protocols generally operate by transferring groups of
data framed by control infonnation, which are referred to as
framesorpacketsofdata. Thesizeofbufferscanbeseparately
specified for transmit and receive data.
For transmissions, data to be sent in a frame may be located
in one or more locations in memory, and therefore the transmit
buffer(s) would be shorter than or equal in length to the data
frame/packet. Data in several buffers can be contiguously
sent to make up a frame. The status infonnation held in each
transmit buffer
descriptordescriptor indicates
System'
Memory
to the DMAC if
Address Bit 7
the buffer conChain POinter (L)
n
tains the end of a
Chain Pointer(H)
frame.

Advantages of the Linked-Chaining Mode
The NPU's linked chaining capabilities provide advantages
over conventional DMA handling of serial data. Some of the
advantages of this scheme are listed below:

- High performance in both serial data transmission rates
and system throughput - the Chained-block Transfer Mode

allows the DMAC to continuously load data received by t/le
MSCI into memory without incurring CPU overhead to switch
buffers. Coupled
with the MSCI's
multi-block transfer
capability,
the
Bit 0
DMAC operating in z
this mode can move
]
Link to next descriptor
back-to-back frames &l
of data located in dif_ C/)
Buffer Pointer (L)
ferent parts of
Starting address of
The DMAC can
Buffer Pointer (H)
corresponding buffer
memory to the
be programmed
IBuffer'" . .'L
MSCl's transmitter,
to transmit one
Reserved
also without CPU asframe of data at a
Data Length (L)
]
Bytes of data in
sistance. System
time, or to transData Lenath (H)
corresponding buffer
processing time for
mit multiple
Status Byte
n+8
received data is enframes to assist in
Reserved
hanced by the
high speed data
MSCI's three-byte
transfer.
FIFO for both re~
If the DMAC
ceiver and transmitchannel is initialFigure 3 -BulTer Descriptor for Chained Block Transfer DMA
ter.
ized for multiple
frame transmissions, the status infonnation in the transmit
- Efficient utilization of system memory - In a system
buffer descriptor includes a bit to indicate if the buffer
without smart buffer management, consecutive memory blocks
identified by the descriptor contains the end of data to be
need to be reserved for each of the frames or packets of data
transmitted.
to be received. The size of each memory block would need
to be a long as the maximum frame/packet size (e.g. 264 bytes
For reception, frames are received and stored in one or more
in an ISDN LSPD frame, 603 bytes in a LLAP packet for
buffers. A pre-determined maximum buffer size is used to
AppleTaIk).
allocate memory for these buffers. If the incoming data frame
is longer than this maximum size specified, the frame will be
With the capabilities of the NPU, multiple buffers can be
brokenupintoseparatebuffers. TheMSCIsignalstheDMAC
chained together to hold the data contained in one received
when the last byte of a frame has been transferred using an
frame. Although receive data buffer sizes must be fixed (for
internal signal line. By specifying a maximum buffer size
memory allocation), the size selected can be optimized by
equal to the size of the average frame, less memory space will
specifying the average frame size.
be wasted by smaller frames or portions of frames which do
not fill the buffer size allocated.

g

]

...

-Efficient transmission ofdata stored in multiple locations
If multi-frame mode of ooeration has been specified, the
DMAC will perfonn buffet switching following the receipt of
the End of Frame signal. Data for the next frame will be
received into a new buffer.

- In the case of data transmission, frame data may be
scattered in system memory space in blocks of differing size.
Provided with link infonnation in the descriptors, the NPU's
DMA can autonomously transfer such a frame of data to the
MSCI's transmitter. Without this linking capability, the data

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Section

2291

E
:..

HD64180S

Application Note

Receive Buffer Descriptor

Transmit Buffer Descriptor

Buffer's size is pre-programmed in BFL
register

Buffer size is variable

Data length field is written with the BCR
contents by the DMAC during buffer switching.
If switching occurs in the middle of a frame,
length field will equal BFL register value.

Data length field is programmed by the user
During buffer switching, data length information
lis written to the DMAC's BCA.

Status field is written by theDMAC during
each buffer switch

CPU programs the Status field value

Status field is read by the user program prior
to processing the receive buffer data

During buffer switching, OMAC reads the status
field to determine if actions should be taken upon
completion of transmission. If EOM bit is set,
OMA notifies MSCI of end of frame.
In multi-frame mode, if the EOT bit is set,
the OMAC stops following data transfer.
Otherwise, if data is available (COA not equal to
EOA), transmission continues.
'

Table 1 • Differences between transmit and receive buffer descriptors

blocks would have to be combined in memory prior to
transmission. With the DMAC's multiple frame transmission
capability, multiple frames of this type can be transferred to
the MSCI's transmitter continuously by DMA without CPU
intervention.
- Low bus bandwidth overhead - Without buffer managerment capability, the DMAC would have to poll to determine if data was available for transmission, or an interrupt
would have to be generated and serviced in order to signal the
DMAC that data was ready to be transferred.
The NPU's buffer management capability allows the CPU to
dynamically update the Error Descriptor Address (BDA)
register which indicates to the DMAC the address of the last
descriptor in the linked list. The buffer referenced by this last
descriptor is not available to the DMAC. Each time the
DMAC finishes with a buffer and proceeds to the attributes of
the next buffer in the linked descriptor list, the EDA is
automatically comp!ll'ed with the address of the new descriptor. If the addresses match, then DMA transfer ends. If the
addresses do not match, the DMAC begins transfer to or from
this buffer. No bus activity is required to make this determi-

Section
292 2

nation.
- Low overhead in buffer switching - the DMAC automatically performs housekeeping tasks during buffer switching. No programmed intervention is required.
DMAC Control Registers
The following registers are used by the DMAC to implement
the Chained Block Transfer Mode.
CPR: Chain Pointer Base specifies the four highest order bits
of the descriptor's address. Written only by the CPU.
CDA: Current Descriptor Address specifies the lower 16 bits
of the current descriptor's 20 bit address. CPB provides the
four highest bits. The CDA is initially programmed by the
user, and is updated by the DMAC during buffer switching.
EDA: Error Descriptor Address indicates the lower 16 bits
of a descriptor's starting address. The descriptor identified in
this register is the entry in the linked list following the last
descriptor which is valid for DMAC use. The user can
dynamically reprogram the EDA during MSCI - DMAC

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HD64180S

Application Note

Bh7

Transmit

BhO

Bh 7

Receive

Bit a

Figure 4 - DMA descriptor Status Bytes
operation which allows reuse of transmit or receive buffers.
BCR: Byte Count Register is a 16-bit down counter. For
transmitting, the BCRindicates the number of remaining data
bytes to be transferred in the transmit buffer current being
accessed. For receiving, the BCR represents the number of
unused bytes remaining in the receive buffer. The initial value
of BCR is obtained from the current descriptor. The BCR is
updated by the DMAC and cannot be written by the user.
BAR: Buffer Address Register specifies the address of data
being transferred from or to the buffer. The initial value of
BAR is obtained from the current descriptor. This register is
updated by the DMAC, and cannot be written by the user.
BFL: Receive Buffer Length specifies the fixed size of
receive buffers. All receive buffers have the same size
determined by the value programmed in the BFL. During
buffer switching, the BFL is copied to the BCR BFL is
programmed by the user.
DMA Buffer Descriptor Format
Each buffer to be used by the DMAC for data transfer must be
identified using a descriptor, which has a format as shown in
Figure 3. Each descriptor contains 10 bytes of data. All
descriptor information must be contained in the 64Kbyte
space defined by theCPB (ChainPointerBase),so up to 6,553
descriptors may be defined. The components of a descriptor
are described below:

receives, this information is written by the DMAC when the
buffer is filled, and is determined by the BFL (Receive Buffer
Length) and the BCR (Byte Count Register) value when
reception into the buffer has completed.
Status Byte: Status information on the buffer. The status byte
differs for transmit and receive descriptors, as shown in Figure
4.
For transmit buffer descriptors, the status byte's BOM and
BOT bits are read by the DMAC during buffer switching.
BOM = I notifies the DMAC that the corresponding buffer
contains the end of a frame. The BOT bit is used only when
the MSCI is in multi-frame transmit mode. BOT = 1 indicates z
that the corresponding buffer contains the end of data to be
transferred, and DMAC operation ends when this buffer has ~
been transmitted.

E

g

For receive buffer descriptors, the status byte is directly
copied from the MSCI's Frame Status register (MFST) upon
the DMAC's receipt of an EOM condition. When the DMAC
receives the end offrame signal internally from the MSCI, the
DMAC will request the MSCI to dump the contents of its
status register during buffer switching. If the buffer switching
occurs in the middle of receiving a frame, the DMAC writes
OOh to the descriptor's status byte.
Constructing a ring of descriptors for re-using buffers
Since buffer descriptors are organized in a linked list, it is
possible to form a ring by programming the address of the first
entry into the link field of the last entry. This would allow the
DMAC to automatically access the list of descriptors and their
associated buffers in a ring configuration. This would allow
re-use of buffers in memory.
Because the DMAC compares the CDA and BDA in order to
determine when all buffers available to the DMAC have been
accessed, there will always be at least one descriptor that
references a buffer that is unavailable to the DMAC. There
are two ways of dealing with this descriptor and buffer:

Chain Pointer: Two bytes providing linkinformation. The 20bit address of the next descriptor in the linked list is formed
by combining these bits with the information in the CPB
(Chain Pointer Base) as the four most significant bits.
Buffer Pointer: Twenty bits which point to the start address
of the buffer corresponding to this descriptor

1. This descriptor can be set up as a dummy. The last real
descriptor in the link would point to this dummy descriptor,
and the BDA would be programmed with the address of this
descriptor. When the DMAC reaches this dummy entry in the
linked list, the CDA would equal the BDA, and the DMA
channel would stop.

Data Length: The amount of data stored in the buffer. For
transmits, this information is initialized by the user. For

2. The BDA can be programmed to the address of this last
descriptor at the start, then when the buffer associated with the

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Section
2293

.01

HD64180S

Application Note

fIrSt descriptor has been accessed the EDA can be reprogrammed to the address of the first descriptor. The link pointer of
the last descriptor should point to the address of the fIrSt
descriptor. The CPU could poll the DMAC's CDA register to
determine when buffer 1 transfer has completed (CDA will
contain the address of buffer 2's descriptor). Using this
method of reprogramming theEDA allows buffers to be used
in a ring configuration.

- MSCI initialized for bit oriented protocol, single frame
transfer,localloopback mode
- DMAC channel 0 initialized for receiving data into the
receive buffers in chained block mode
- DMAC channel I initialized for transmitting data from
the transmit buffers using chained block transfer mode
- DMAC channels, MSCI receiver and MSCI transmitter
are enabled in that order

An example using this ring configuration of receive buffers is
shown in Figure 5. In this example, eight memory buffers are
allocated for receiving data from the MSCI under DMA
control.

Preparation/or transmitting data

A program using this ring configuration ofreceive buffers was
written to demonstrate the initialization of the NPU required
to handle this type of receive operation. The code for this
program is included in Appendix A.
To simplify the hardware required to execute this program,
the NPU MSCI's localloopback mode was selected to cause
data placed in the MSCI's transmit buffer to be looped back
into the receive buffer. The data to be transmitted was
initialized as a single frame contained in two separate buffers
in memory. The transmit descriptor table was configured as
a linked list containing the two entries for the buffers plus a
dummy descriptor.
The program initializes the MSCI for bit oriented communications, then uses chained block transfer mode of the DMAC
to transmit a frame of data. This transmitted data is looped
back into the MSCI receiver, where it is received using
chained block transfer mode DMA. As each of the receive
buffers are filled, the contents of the buffer is moved under
program control to a new location in memory.
This program was tested using the Hitachi 64180S ASE
(Adaptive System Evaluator) Emulator. Correct operation of
the program was determined by examining memory upon
completion of the program to show that the transmitted data
had been received and stored into memory. Examination of
the DMAC registers also showed that DMA transfers had
completed sucessfully.
The sequence of events that occur in this program is described
. below:

Initialization by user program:
- Transmit data buffers initialized
- Transmit descriptor table for DMA initialized
- Receive descriptor table for DMA initialized

Both DMAC channels prepare to transfer data between the
MSCI and memory. For DMAC channell, the following
occurs:
- DMAC compares CDAI and EDAI, and continues ifnot
equal
- DMAC reads information from the transmit descriptor
pointed to by CDAL The starting address information is
stored in the DMAC's Source Address Register (SAR). The
link address and status information are transferred to DMAC
internal registers for future reference.
- The DMAC loads the data length value from the descriptor into the BCR
- DMAC responds to the MSCI internal request to accept
transmit data

Transmitting data
- DMAC transfers one byte of data from buffer to the MSCI
transmitter
- DMAC decrements the BCRI and increments the DAR 1
- Transfers continue until BCRI = 0
- When BCRI = 0, buffer switching is initiated

Buffer switching during transmission
- The link field information of the descriptor for the buffer
just transferred (descriptor #1, buffer #1) is read from the
internal working register and written to the CDAI register.
- The status field information of descriptor #1, which was
placed in an internal working register prior to transmitting
buffer # I' s data, is checked to determine if the EOM bit is set.
If so, transfer ends. If this bit is not set, tasks continue. (If
Multi-frame mode was selected, the status field would be
checked for EOT bit set, and transmission would complete
only if this bit was set) .
- This new CDAI value is compared with the value in
EDAI. If they are not equal, the buffer referenced by the
descriptor addressed by the CD AI contains data that should
be transmitted. (If CDA = EDA, DMA transfer stops)
- The new descriptor's link field is stored in the internal
working register. The buffer pointer stored in the descriptor

Section

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294

HD64180S

Application Note

System Memory
Adctess
4100h

4110h

4120h

--->~ I""""'i""'"' '::::i' "i'",,,,'i' "i'l

--~'I"'''''''''''"''''''

=:""""

Initialization:
CPB-O
CDA.4000h
EDA.8000h

'"' "' ' "' 1

--->-~ I""i"""'i' ' ' ''':::':'''''' ' ' ' """'1

4130h

--->~["'m''''''''''i'i' .':=':i""'" ,""" """'i'l

4140h

---')~I""'i"'i""'i""'i'=':'"'' i"""""""""1

4150h

---:)~r"i"'i"""'"'''' ~=:""""" ' ' i' ' ' ' '1

!Y1HHUY1HHH!

Link Field: pointer to starting eddress 01 next descriptor

Figure 5 - Buffer Descriptors set up for continuous receipt of MSCI data

HITACHI
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Section

2295

HD64180S

Application Note

is loaded into the DMAC's BAR
- Data length field of the descriptor pointed to by the link
field of descriptor #1 is loaded into the BCR.
- Status field of this next descriptor is loaded into an
internal working register.
- Data transmission from buffer #2 begins.
33 bus states are required to complete the buffer switching
tasks when the switch occurs during the middle of a frame. 37
states are required when the buffer switch occurs at the end of
a frame.

Preparation/or receiving data
For DMAC Channel 0 (DMA receive data), the following
actions occur:
- DMAC compares CDAO and EDAO, and continues if not
equal
- DMAC reads information from the receive descriptor
pointed to by CDAO. The starting address information is
stored in the DMAC's Destination Address Register (DARO).
The link address is transferred to a DMAC internal register for
future reference.
- The DMAC loads the data length value from BFLO into
BCRO.
- DMAC responds to the MSCI internal request to receive
data.

Receiving data
-DMAC transfers one byte of data from the MSClreceiver
to the receive buffer
- DMAC decrements BCRO and increments DARO
-Transfers continue until end of frame is detected or BCRI
= 0, when buffer switching is initiated

Receive Buffer Switching
- The number of bytes received into the buffer is written to
the descriptor's data length field.
- If the end of the frame/packet was not received into this
buffer, the DMAC writes OOh to the status field of the
descriptor. If the end of the frame was received, the DMAC
requests the MSCI toputits MFST value onto the internal data
bus. This information is transferred by the DMAC to the
descriptor's status field.
- The descriptor's link field information, which was placed
into an internal working register when the descriptor was
examined prior to receiving the data, is transferred to theCDA
register.
- This new CDA value is compared with the value in the
EDA. If they are not equal, the buffer referenced by the

descriptor addressed by the CDA is available to store receive
data. (If CDA = EDA, DMA transfer stops)
- The new descriptor's link field is stored in the internal
working register. The buffer pointer stored in the descriptor
is loaded into the DMAC's BAR.
- The DMAC's BFL value is copied to the BCR
- Data reception into the new buffer begins
34 states are required to perform these buffer switching tasks.
Closing the loop
After one or more receive buffers have been filled by DMA
transfers, the user program can begin processing the buffer
data. When processing of first buffer's data is complete, the
user program can update the EDAO to point to the address of
the next buffer's descriptor. The receive buffers will be filled
sequentially, and when the eighth buffer is filled, its link
address, which will be placed in CDAO, will point to the
descriptor of the first buffer. SinceEDAOdoes not point to this
first buffer's descriptor, upon comparison CDAO will not
equal EDAO so reception from the MSCI will continue and
receive data will be transferred to this first buffer again,
closing the loop.
In this example program, the processing performed on the
received data is to move it from the receive buffer to another
location in memory, where the entire frame will be assembled
in contiguous bytes. Following enabling of the DMAC and the
. MSCI, the user program polls the CDAO register to determine
when the first buffer has been filled and the DMAC has
switched to filling the second buffer. The user program
detects that this has occurred when the CDAO register points
to the second descriptor. The program continues this polling
then moving for each receive buffer in the descriptor table.
Although eight receive buffers are available to the DMAC, a
total of ten b~ffers worth of data will be received to process
the transmitted frame. To accomplish this, the first two
receive buffers must be reused. Upon initialization, EDAO
points to the descriptor forthe eighth buffer. The DMAC will
therefore stop receiving data when the eighth descriptor is
reached, unless EDAO is reprogrammed.
Once the first buffer has been filled and the data transferred,
this buffer is available for reuse. At this point in the program,
EDAO can be reprogrammed to point to the address of the
descriptor of the second buffer. When the second buffer has
been filled and transferred, EDAO can safely be reprogrammed to point to the address of the descriptor of the third buffer.
When this second buffer has been filled the second time and
buffer switching is initiated, the DMAC will detect that the

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Genter· 2000 Sierra Point Pkwy.· Brisbane, GA 94005-1819 • (415) 589-8300

296

HD64180S

Application Note
CDA = EDA, and transfer will stop.

How can the DMAC reclaim buffers written with data received in a badframe?

Questions and Answers
The following paragraphs contain questions and answers
pertaining to the use of the Chained Block Transfer Mode of
DMA operation.
How does the DMAC know that the next descriptor references
a bl4fer that is available for transfer?
During buffer switching, the current buffer's chain pointer
becomes the new CDA. The DMAC compares this new CDA
with the current EDA value. If they are equal, the end of the
chain has been reached. If they are not equal, the new buffer
is available for use by the DMAC.
How does the user program know that a particular buffer has
been used by the DMAC?
The program can read the DMAC channel's CDA. If, for
instance, the CDA contains the starting address of the third
descriptor in the linked list, the user can determine from this
that:

The MSCI can be programmed to cause an interrupt upon
receipt of a bad frame, for instance by signalling a CRC error.
In the service routine for this interrupt, the user program can
determine which buffer contains the start of the bad frame
detected. The program can then disable the DMA channel
handling the receive, and reprogram the CDA with the start
address of the descriptor referencing this buffer. Upon
reenabling the DMA channel, new data will be written over
the data of the bad frame.

z
o

How can aframe be retransmitted?

i=

The user program can determine the start address of frames ~
being transmitted from the transmit buffer descriptor table. If en
the need to retransmit a frame occurs, the DMAC can be
disabled and the CDA register can be reprogrammed with the
address of the descriptor corresponding to the buffer containing the start of the frame to be retransmitted. When DMA is
reenabled, transmission will start with the beginning of the
frame.

l. The DMAC is ready to access buffer #3 OR
2. The DMAC is in the process of accessing buffer #3.
In either case, the user can be certain that the DMAC is
finished with buffers corresponding to the first and second
descriptors in the list, and these buffers can be processed by
the user program and then reused as DMAC data buffers.

HITACHI
Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2297

E

HD64180S
CPU
HOF

0000
0000

Application Note

·64180.TBL
·INT8 N

N

;******************** •• *******************************.**_.* ••

TITLE:

NPU DMA BUFFER MANAGEMENT DEMOSTRATION PROGRAM

;***************************************************** •••• _ •••

DEFSEG ROM, ABSOLUTE
SEG
ROM
DATA TO BE TRANSMITTED
3000
3000 030B465241
3100
3100 2046524140

ORG
DFB
ORG
DFB

3000H
03,OBH,-FRAME1 B1-BUFFER MANAGEMENT DEMOSTRATION PROGRAM ;50 BYTES
3100H
• FRAMEl B2-ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmN
;50 BYTES
R

;*--*._-_ .. __ . __ ... _. __ ... __ .... -.. -.. __ ... _*._ .. _._-**

;-_._-_....•-.•. _.. _-•• -••. _.--_ •. _._ •. _-_._--.-.•••. -*
TRANSMIT DESCRIPTOR SET UP

4000
4000
4002
4004
/4005
4006
4008
4009

4010
4010
4012
4014
4015
4016.
4018
4019

4020
4020
4022
4024
4025
4026
4028
4029

1040
0030
00
00
3200
00
00

TX· BUFFER 1
ORG
OWL
OWL
DFB
OFB
DWL
OFB
DFB

2040
0031
00
00
3200
81
00

TX BUFFER 2
ORG
OWL
OWL
.DFB
OFB
OWL
OFB
DFB

3040
0032
00
00
3200
80
00

TX BUFFER 3
ORG
OWL
OWL
DFB
OFB
OWL
DFB
OFB

4000H
4010H
3000H
00

o
50

o
o
4010H
4020H
3100H
00

o
50
81H
0\

4020H
4030H
3200H
00

o
50
80H

o

STARTING ADDRRESS OF NEXT DESCRIPTOR = 4010H
LOWER 16 BIT OF TX BUFFER POINTER = 3000H
HIGHER 4 BIT OF 20 BIT TX BUFFER POINTER - 00
RESERVED
DATA LENGTH OF BLOCK 1 = 50
STATUS ===> NO EOM , NO EOT
RESERVED

STARTING ADDRRESS OF NEXT DESCRIPTOR = 4020H
LOWER 16 BIT OF TX BUFFER POINTER = 3100H
HIGHER 4 BIT OF 20 BIT TX BUFFER POINTER = 00
RESERVED
DATA LENGTH OF BLOCK 2 = 50
STATUS ===> EOM, EOT
RESERVED

STARTING ADDRRESS OF NEXT DESCRIPTOR = 4030H
LOWER 16 BIT OF TX BUFFER POINTER = 3200H
HIGHER 4 BIT OF 20 BIT TX BUFFER POINTER = 00
RESERVED
DATA LENGTH OF BLOCK 3 = 50
STATUS ===> EOM , NO EOT (END OF FRAME 1)
RESERVED

;.wxx •• xx •• _ •• _ •••••••• _. ______ ._ •• __ • __ ._ •••• *_ ••••• _**

RECEIEVE DESCRIPTOR SET UP

:••• _•••-.--.--•• -•• -._-•••• _.-•• -••••••••••• -••• _--*.*
4100

Section
298 2

RX BUFFER 1
ORG

4100H

HITACHI
Hitachi America, Ltd.· San francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD64180S

Application Note
4100
4102
4104
4105
4106
4108
4109

1041
0030
03
00
0000
00
00

4110
4110
4112
4114
4115
4116
4118
4119

2041
2030
03
00
0000
00
00

4120
4120
4122
'4124
4125
4126
4128
4129

3041
4030
03
00
0000
00
00

4130
4130
4132
4134
4135
4136
4138
4139

4041
6030
03
00
0000
00
00

4140
4140
4142
4144
4145
4146
4148
4149

5041
8030
03
00
0000
00
00

4150
4150
4152
4154
4155
4156
4158

6041
A030
03
00
0000
00

OWL
OWL
DFB
DFB
OWL
DFB
DFB
RX BUFFER 2
ORG
OWL
OWL
DFB
DFB
OWL
DFB
DFB
RX BUFFER
ORG
OWL
--"L
,-,'B

DFB
OWL
DFB
DFB
RX BUFFER
ORG
OWL
OWL
DFB
DFB
OWL

DFB
DFB
RX BUFFER 5
ORG
OWL
OWL
DFB
DFB
OWL
DFB
DFB
RX BUFFER 6
ORG
OWL
OWL
DFB
UP'B
OWL
DFB

4110H
3000H
03

o
o
o
o
4110H
4120H
3020H
03

o

o
o
o
4120H
4130H
3040H
03

o

4130H
4140H
3060H
03
0
0
0
0
4140H
4150H
30BOH
03
0
0

4150H
4160H
30ACH
0_

o
o
o

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
DATA LENGTH OF BLOCK 1 TO
STATUS ===> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4110H
POINTER = 3000H
BUFFER POINTER = 03

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
DATA LENGTH OF BLOCK 1 TO
STATUS ===> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4120H
POINTER = 3020H
BUFFER POINTER = 03

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF n'IT RX
RESERVED
DATA LENGTH OF BL~~K 1 TO
STATUS ===> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4130H
POINTER = 3040H
BUFFER POINTER = 03

BE WRITTEN BY DMA
BY DMA

BE WRITTEN BY DMA
_, Y DMA

BE WRITTEN BY DMA
BY DMA

STARTING ADDRESS OF NEXT DESCRIPTOR = 4140H
LOWER 16 BIT OF RX BUFFER POINTER = 3060H
HIGHER 4 BIT OF 20 BIT RX BUFFER POINTER = 03
RESERVED
DATA LENGTH OF BLOCK 1 TO BE WRITTEN BY DMA
STATUS ===> TO BE WRITTEN BY DMA
RESERVED

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
DATA LENGTH OF BLOCK 1 TO
STATUS ===> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4150H
POINTER = 30BOH
BUFFER POINTER = 03

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
;.DATA LENGTH OF BLOCK 1 TO
; STATUS ===> TO BE WRITTEN

DESCRIPTOR = 4160H
POINTER = 30AOH
BUFFER POINTER - 03

BE WRITTEN BY DMA
BY DMA

BE WRITTEN BY DMA
BY DMA

HITACHI
Hitachi America, Ltd,' San Francisco Center' 2000 Sierra Point Pkwy,' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2299

HD64180S
4159 00
'4160
4160
4162
4164
4165
4166
4168
4169

7041
C030
03
00
0000
00
00

4170
4170
4172
4174
4175
4176
4178
4179

0041
E030
03
00
0000
00
00

Application Note

DFB
RX BUFFER 7
ORG
OWL
OWL
DFB·
DFB
OWL
DFB
DFB
RX BUFFER 8
ORG
OWL
OWL
DFB
DFB
OWL
DFB
DFB

0

RESERVED

4160H
4170H
30COH
03
0
0
0
0

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
DATA LENGTH OF BLOCK 1 TO
STATUS ---> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4170H
POINTER = 30COH
BUFFER POINTER = 03

4170H
4100H
30EOH
03
0
0
0
0

STARTING ADDRRESS OF NEXT
LOWER 16 BIT OF RX BUFFER
HIGHER 4 BIT OF 20 BIT RX
RESERVED
DATA LENGTH OF BLOCK 1 TO
STATUS ===> TO BE WRITTEN
RESERVED

DESCRIPTOR = 4100H
POINTER = 30EOH
BUFFER POINTER = 03

BE WRITTEN BY DMA
BY DMA

BE WRITTEN BY DMA
BY DMA

;************ •• ****************************************

CPU ROUTINE
;******************************************************

ORG

FOOO
FOOO

OFOOOH

RESET:

: ***** *** **** ***** ***** ** ****** ** **'k *** * * * * * * * * * .'* * * * * * * *
MSCI TRANSMIT IN DMA SET UP
;********************************************************

TRANSMITTER AND RECEIEVER SET UP
FOOO
F002
F005
F007
FOOA
FOOC
FOOF
FOll
F014
F016

3E21
ED392A
3E87
ED392B
3EOO
ED392C
3E03
ED392D
3EBl
ED392E

LD
OUTO
LD
OUTO
. LD

F019
FOIB
FOIE
F020
F023
F025

3E43
ED3933
3E43
ED3934
3E80
ED3932

LD
OUTO
LD
OUTO
LD
OUTO

A,43H
(MRXS) ,A
A,43H
(MTXS) ,A
A,BOH
(MTMC) ,A

LD

A,OOOH

F028 3EOO

A,21H
(MCMD) ,A
A,87H
(MMDO),A
A,OOH
OUTO (MMel) ,A
A,03H
LD
OUTO (MMD2) ,A
LD
A,OBIH
OUTO (MCTL) ,A

CHANNEL RESET
BIT-SYNC HDLC,AUTO ENABLE=0,CRC-CCITT=1 INITIALLY
ADDRESS NOT CHECKED
FULL DUPLEX, NRZ CODE, LOCAL LPBK
DMA,FLAG AND IDLE, -RTSM=HIGH
SPECIFIES FCS NO-LOAD
RXCM FROM BRG
TXCM FROM BRG
SET TMC-12B -> BAUD RATE SELECTED=9.6K

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

300

HD64180S

Application Note
F02A
F02D
F02F
F032
F034
F037
F039

ED3926
3E83
ED3927
3E32
ED392F
3E7E
ED3931

OUTO
LD
OUTO
LD
OUTO
LD
OUTO

(MIEO) ,A
A,83H
(MIE1) ,A
A,32H
(MSAO),A
A,7EH
(MIDL) ,A

TXINT AND RXINT DISABLED
UNDERRUN,ABORT,IDLE DETECTION INTERRUPT ENABLED
SECONDARY STATION ADDRESS

= 02H

SET FLAG PATTERN = 01111110 AS IDLE PATTERN

;*******************************************************

DMA CHANNEL 0 SET UP

(RECEIEVER)

:*******************************************************

F03C
F03E
F041
F043

3E94
ED3969
3EOO
ED395D

LD
OUTO
LD
OUTO

A,94H
(DMRAO) ,A
A,O
(CPBO) ,A

F046
F048
F04B
F04D

3E70
ED3960
3E41
ED3961

LD
OUTO
LD
OUTO

A,10H
(EDACL) ,A
A,41H
(EDAOH) ,A

4110H
STARTING ADDR (LOW-ORDER 16 BITS) OF THE
RX DESCRIPTOR 8

FOSO
F052
F055
F057

3EOO
ED395E
3E41
ED395F

LD
OUTO
LD
OUTO

A,OOH
(CDAOL) ,A
A,41H
(CDACH) ,A

4100H
STARTING AD DR (LOW-ORDER 16 BITS) OF THE
FIRST RX DESCRIPTOR

FOSA
F05C
F05F
F061

3EOA
ED3962
3EOO
ED3963

LD
OUTO
LD
OUTO

A,lO

F064 3E80
F066 ED396C

LD
OUTO

A,80H
(DIRO) ,A

(BUFLOL) ,A
A,O
(BUFLOH) ,A

DMA MODE REGISTER A
MSCI,CBSA,MSCI->MEMORY,MULTI FRAME
4 HIGHER BIT OF THE 20-BIT DESCRIPTOR ADDR

ALLOWING ONLY 10 BYTES IN EACH RX BUFFER

; EOT INTERRUPT ENABLED

;*******************************************************

DMA CHANNEL 1 SET UP

(TRANSMITTER)

:*******************************************************

F069
F06B
F06E
F070

3E9C
ED3981
3EOO
ED3975

LD
OUTO
LD
OUTO

A,09CH
(DMRA1) ,A
A, a
(CPB1) ,A

DMA MODE REGISTER A
MSCI,CHAINED,MEMORY->MSCI,MULTI FRAME

F073
F075
F078
F07A

3E20
ED3978
3E40
ED3979

LD
OUTO
LD
OUTO

A,20H
(EDAlL) ,A
A,40H
(EDA1H) ,A

4020H
STARTING ADDR (LOW-ORDER 16 BITS) OF THE
DESCRIPTOR NEXT TO THE LAST TX BUFFER

F07D
F01F
F082
F084

3EOO
ED3976
3E40
ED3971

LD
DUTO
LD
OUTO

A,OOH
(CDAlL) ,A
A,40H
(CDA1H) ,A

4000H
STARTING ADDR (LOW-ORDER 16 BITS) OF THE
FIRST DESCRIPTOR DF THE FIRST TX BUFFER

4 HIGHER BIT OF THE 20-BIT DESCRIPTOR ADDR

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2301

HD64180S
FOS? 3ESO
FOS9 ED39S4

Application Note
LD
OUTO

A,SOH
(DIR1) ,A

: EOT INTERRUPT ENABLED

TO ENABLE DMA CHANNEL 0, 1 AND MSCI TX,RX
FOSC
FOSE
F091
F093
F096
F09S
F09B
F09D

3E02
ED396S
3E02
ED39S0
3E12
E0392A
3E02
E0392A

LD
OUTO
LO
OUTO
LO
OUTO
LD
OUTO

A,02H
(OSRO)
A,02H
(DSR1)
A,12H
(MCMO)
A,02H
(MCMO)

,A

DMA CHANNEL

ENABLE

,A

OMA CHANNEL 1 ENABLE

,A

RX ENABLE

,A

TX ENABLE

TEST CDA OF RECEIEVER
CHANGE EDA AFTER EACH BLOCK IS DONE
RECONSTRRUCT DATA INTO ONE PIECE
FOAO
FOA2
FOAS
FOAS
FOA8
FOM
FOAC
FOAF
FOB2
FOBS

3E30
ED3902

A,30H
(BBR) ,A

INO
CP

A, (CDAOL)
0
Z,BLKI

: BBR OF MMU SET AT 30

BLK1:
ED3SSE
FEOO
28F9
210030
1l003A
OlOAOO
EDBO

FOB?
FOB? ED385E
FOBA FE10
FOBC 2SF9
FOBE 212030
FOC1 OlOAOO
FOC4 EDBO

FOC6
FOC8
FOCB
FOCD
FODO
FODO
FOD3
FODS

LD
OUTO

3E10
ED3960
3E41
ED3961
ED38SE
FE20
2SF9

Section
302 2

JR

MOVE BLOCK 1
LD
LD
LD
LDIR

: CHECK LOWER BYTE OF CDAO

HL,3000H
DE,3AOOH
BC,lO

BLK2:
INO
CP
JR
MOVE BLOCK2
LD
LD
LDIR
CALL
DFB
SET. NEW EDA
LD
OUTO
LD
OUTO
BLK3:
INO
CP
JR
MOVE BLOCK3

A, (CDAOL)
10H
Z,BLK2

CHECK LOWER BYTE OF CDAO

HL,3020H
BC,10
PUTSCR
'BLOCK2 MOVED' ,0

A,lOH
(EDAOL) ,A
A,4lH
(EDAOH) ,A
A, (CDAOL)
20H
Z,BLK3

NEW EDAO=41l0H
buffer of descr at 4l00h
ready for reuse
CHECK LOWER BYTE OF CDAO

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD64180S

Application Note
FOD? 214030
FODA 010ACO
FODD EDBO
FODF

FODF
FOE1
FOE4
FOE6

HL,3040H
BC,10

BLK4:

3E20
ED3960
3E41
ED3961

FOE9 ED385E
FOEC FE30
FOEE 28EF
FOFO 216030
FOF3 010ACO
FOF6 EDBO
FOF8
FOF8
FOFA
FOFD
FOFF

LD
LD
LDIR

3E30
ED3960
3E41
ED3961

F102 ED385E
FlOS FE40
FlO? 28EF
F109 218030
flOC 010AOO
FlOF EDBO
Flll
Flll ED385E
F114 FESO
F1l6 28F9
F118 21A030
FllB 010AOO
FllE EDBO
F120
F120 ED385E
F123 FE60
F12S 28F9
F12? 21C030
F12A OlOAOO

; SET NEW EDA
LD
OUTO
LD
OUTO
INO
CP
JR
MOVE BLOCK4
LD
LD
LDIR

A,20H
(EDAOL) ,A
A,41H
(EDAOH) ,A
A, (CDACL)
30H
Z,BLK4

can be reused

CHECK LOWER BYTE OF CDAO

~I

HL,3060H
BC,10

BLKS:
; SET NEW EDA
A,30H
LD
OUTO (EDAOL) ,A
A,41H
LD
OUTO (EDAOH) ,A
INO
CP
JR
MOVE BLOCKS
LD
LD
LDIR

NEW EDAO=4120H
buffer of descr 4110h

A, (CDAOL)
40H
Z,BLK5

NEW EDAO=4130H
buffer of descr 4120h

can now be reused

CHECK LOWER BYTE OF CDAO

HL,3080H
BC,lO

BLK6:
INO
CP
JR
MOVE BLOCK6
LD
LD
LDIR

A, (CDAOL)
SOH
Z,BLK6

CHECK LOWER BYTE OF CDAO

HL,30AOH
BC,10

BLK?:
INO
CP
JR
MOVE BLOCK?
LD
LD

A, (CDAOL)

CHECK LOWER BYTE OF CDAO

60H
Z,BLK?
HL,30COH
BC,10

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section
2303

HD64180S
F12D EDBO
F12F
F12F ED385E
F132 FE70
F134 28F9

Application Note
LDIR

BLK8:
INO
CP
JR

CHECK LOWER BYTE OF CDAO

A, (CDAOL)
70H
Z,BLK8

;. MOVE BLOCK8

F136 2lE030
F139 OlOAOO
F13C EDBO
F13E
F13E ED385E
Fl41 FEOO
FH3 28F9
F145 210030
F148 OlOAOO
FHB EDBO
F14D
F14D ED385E
F150 FEIO
Fl52 28F9

"LD
LD
LOIR

HL,30ECH
BC,lO

INO
CP

A, (CDAOL)
OOH
Z,BLK9

BLK9:

JR

MOVE BLOCK9
LD
LD
LDIR

CHECK LOWER BYTE OF CDAO

HL,3COOH
BC,lO

BLKlO:
INO
CP
JR

CHECK LOWER BYTE OF CDAC

A, (CDAOL)
10H
Z,BLKIO

MOVE BLOCKIO
Fl54 212030
Fl57 OlOAOO
Fl5A EOBC

LD

LO
LDIR

Fl5C
Fl5C 3EOO
F15E ED3902

BLKll:

Fl61
Fl61 C361Fl

DONE:

LD
OUTO

HL,3020H
BC,IO

A,CH
(BBR) ,A

BBR OF MMU SET AT .0

loop here when done

JP

NPU EV BOARD 10 ASSIGNMENT
npu 10 address assignments 10-11-88 06:23:00

=

0.002 =
00.03 =
0004
0005 =

ICR:
CBR:
BBR:
CBAR:
OMCR:
IOCR:

EOU
EOU
EOU
EOU
EOU
EOU

OOOH
OOlH
002H
003H
004H
005H

INTERRUPT CONTROL REG
MHU COMMON BASE REG
MHU BANK BASE REG
MHU COMMON/BANK AREA REG
OPERATION MODE CTRL REG
I/O CTRL REG

0.020
0021
0022 =

MTRB:
MSTO:
MSTl:

EOU
EOU
EOU

020H
02lH
C22H

MSCI TX!RX BUFFER REG
MSCI STATUS REG
MSCI STATUS REG 1

0000

0001 -

Section

HITACHI

2

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304

HD64180S

Application Note
0023 =
0024 =
0025 =
0026 0027

MST2:
MST3:
MFST:
MIEO:
MIE1:

EQU
EQU
EQU
EQU
EQU

023H
024H
025H
026H
027H

MSCI
MSCI
MSCI
MSCI
MSCI

STATUS REG 2
STATUS REG 3
FRAME STATUS REG
INTERRUPT ENABLE REG
INTERRUPT ENABLE REG

=

=

MIE2:
MFEI:
MCMD:
MHDO:
MHD1:
MMD2:
MCTL:
MSAO:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

028H
029H
02AH
02BH
02CH
02DH
02EH
02FH

MSCI
MSCI
MSCI
MSCI
MSCI
MSCI
MSCI
MSCI

INTERRUPT ENABLE REG 2
FRAME INTERRUPT ENABLE REG
COMMAND REG
MODE REG
MODE REG 1
MODE REG 2
CONTROL REG
SYNCHRONOUS ADDRESS REG

0030
0031
0032
0033
0034 =

MSA1:
MIDL:
MTMC:
MRXS:
MTXS:

EQU
EQU
EQU
EQU
EQU

030H
031H
032H
033H
034H

MSCI
MSCI
MSCI
MSCI
MSCI

SYNCHRONOUS ADDRESS REG
IDLE PATTERN REG
TIME CONSTANT REG
RX CLOCK SOURCE REG
TX CLOCK SOURCE REG

0058
0058
0059
0059
005A
005A
005B
005B
005C
005C
005D
005D
005E
005F

DAROL:
BAROL:
DAROH:
BAROH:
DAROB:
BAROB:
SAROL:
DRWROL:
SAROH:
DRWROH:
SAROB:
CPBO:
CDAOL:
CDAOH:

EQU
EQU
EQU
EQU
EQU
EQU
EOU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

058H
058H
059H
059H
05AH
05AH
05BH
05BH
05CH
05CH
05DH
05DH
05EH
05FH

DESTINATION ADDRESS REG CH 0 LOW
BUFFER ADDRESS REG CH 0 LOW
DESTINATION ADDRESS REG CH 0 HI
BUFFER ADDRESS REG CH 0 HI
DESTINATION ADDRESS REG CH
BANK
BANK
BUFFER ADDRESS REG CH
LOW
SOURCE ADDRESS REG CH
DESCRIPTOR READ/WRITE REG CH
LOW
SOURCE ADDRESS REG CH 0 HI
DESCRIPTOR READ/WRITE REG CH 0 HI
SOURCE ADDRESS REG CH 0 BANK
CHAIN POINTER BASE CH 0
ACCESS DESCRIPTOR ADDRESS REG CH
LOW
ACCESS DESCRIPTOR ADDRESS REG CH
HI

0060 =
0061
0062 0063
0064
0065

EDAOL:
EDAOH:
BUFLOL:
BUFLOH:
BCROL:
BCROH:

EQU
EQU
EQU
EQU
EQU
EOU

060H
061H
062H
063H
064H
065H

ERROR DESCRIPTOR ADDRESS REG CH
ERROR DESCRIPTOR ADDRESS REG CH
RX BUFFER LENGTH CH 0 LOW
RX BUFFER LENGTH CH 0 HI
BYTE COUNT REG CH 0 LOW
BYTE COUNT REG CH
HI

0068 •

DSRO:

0069 =
006A =
006B
006C =
006D

DMRAO:
DMRBO:
leNTO:
DIRO:
DCRO:

EQU
EQU
EQU
EQU
EQU
EQU

068H
069H
06AH
06BH
06CH
06DH

DMA STATUS REG CH 0
DMA MODE REG A CH
DMA MODE REG B CH 0
FRAME END INTERRUPT COUNTER CH
DMA INTERRUPT ENABLE REG CH
DMA COMMAND REG CH 0

0070

DAR1L:

EQU

070H

DESTINATION ADDRESS REG CH 1 LOW

0028
0029
002A
002B
002C
002D
002E
002F

=

=

=

=

=
=
=

=
=
=

=

LOW
HI

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2305

HD64180S
0070
0071
0071
0072
0072
0073
0073
0074
0074
0075
0075
0076
0077
0078
0079
007A
007B
007C
007D
0080
0081
0082
0083
0084
0085

=
=

•
=

-

=
=

=
=

-

=
=

-

Application Note

BARIL:
DARIH:
BARIH:
DARIB:
BARIB:
SARIL:
DRiiRIL:
SARIH:
DRiiRIH:
SARIB:
CPB1:
CDAlL:
CDAIH:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

070H
071H
071H
072H
072H
073H
073H
074H
074H
075H
075H
076H
077H

BUFFER ADDRESS REG CH 1 LOW
DESTINATION ADDRESS REG CH 1 HI
BUFFER ADDRESS REG CH 1 HI
DESTINATION ADDRESS REG CH
BANK
BUFFER ADDRESS REG CH
BANK
SOURCE ADDRESS REG CH
LOW
DESCRIPTOR READ/WRITE REG CH 1 LOW
SOURCE ADDRESS REG CH 1 HI
DESCRIPTOR READ/WRITE REG CH
HI
SOURCE ADDRESS REG CH 1 BANK
CHAIN POINTER BASE CH 1
ACCESS DESCRIPTOR ADDRESS REG CH
LOW
ACCESS DESCRIPTOR ADDRESS REG CH
HI

EDAIL:
EDAIH:
BUFLIL:
BUFLlH:
BCRlL:
BCRlH:

EQU
EQU
EQU
EQU
EQU
EQU

078H
079H
07AH
07BH
07CH
07DH

ERROR DESCRIPTOR ADDRESS REG CH
ERROR DESCRIPTOR ADDRESS REG CH
RX BUFFER LENGTH CH 1,LOW
RX BUFFER LENGTH CH 1 HI
BYTE COUNT REG CH 1 LOW
BYTE COUNT REG CH 1 HI

DSR1:
DMRA1:
DKRB1:
ICNT1:
DIR1:,
DCR1:

EQU
EQU
EQU
EQU
EQU
EQU

080H
081H
082H
083H
084H
085H

DMA STATUS REG CH
DMA MODE REG A CH
DMA MODE REG B CH 1
FRAME END INTERRUPT COUNTER CH
DMA INTERRUPT ENABLE REG CH 1
DMA COMMAND REG CH 1

LOW
HI

DEFINITIONS
FFFF
0005
OOFE
OOOD
OOOA
0011
0013
0003
0017
0000

-

=

=

USRSP:
PUTSCR:
INTV:
CR:
LF:

=
=

=
-

Section
306 2

XON:
XOFF:
EOT:
EOB:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
END

OFFFFH
5
OFEH
ODH
OAH
llH
13H
03H
17H

HITACHI

Hitachi America. Ltd.· San Francisco Center' [2000 Sierra Point Pkwy.· Brisb~ne. CA 94005-1819 • (415) 589-8300

November, 1989

HD64180 Family
Application Note
Mamie Mar

Memory Read and Write Timing

Revision B

'l'hisnoteprovidesdesigner:sofHD64180-family device based
systemswithCPUtiminginformationforMemoryRead/Write
cycles.

Although the timing parameters shownQll the following pages
arecontainedinthedatabooks,atimingcUagramsbowingtheir
relation to the system clock is not included.

This timing differs from Opcode Petch cycle in that for
Memory Read cycles, read data is latched on the falling edge
of1'3. Por Opcode Petch, data is latched on the rising edge of
1'3. Opcode Petch and I/O cycle timing diagrams are shown
in the 64180 family data books.

Please referto the following data books for more information
on these timing parameters.
* HD641S0 S-Bk Microprocessor Hardware Manual (#U77)
(HD6418ORO, HD64180Rl, and HD64180Z)
*HD64718OX 8-Bit MiaoconImller Hardware Manual (#U94)

t; ~
i=

@
en

12

11

13

Clock

ME

E

RD

OO.D7~

____

~

+-__________

____

~

(rud)

WR

,4
DO· D7,_______o(J
(wrllII)

CPU Memory ReadIWrite Timing
HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2307

HD64180 Family

Applicadon Note

HD64180RO AC Characteristics
Vee.5V -t1-10%.

v... 0 V. Ta. -20 to +7SOC
l::tD64A liUlBII

(4MHz)

!
1

2
3
4

-

~

JlI.m

tAO

Add,... Delay Time"
ME Delay TIme 1
\AddI88& Set-up Time"
ME Delay Time 2
Addraaa Hold Time
Enable Delay Time 1
Enable Delay Time 2
RD Delay Time 1
RD Delay Time 2
Data Read Set-up Time
Data Read Hold Time
WR Delay Time 1
WR Delay TIme 2
Write Data Delay Time
Write Data Set-up Time
WR Pulse WIdth
Write Data Hold Time
Write Data Floating
Delay TIme

tM

.t....

5

tNt

6
7
8
9
10
11
12
13
14
15
16
17
18

!m,

',-"

tllDDa

toRS

tDAH

fw..o,
lw'woo
fwoa

''waH
"-

Yin

MIl

l::tD84B lBIIBQ

(6MHz)

Yin

110
85
10

45

85
80

35
100
100
85
85

50
0

45

0
90
90
110

60
220

40
135
40

60

100

MIl
105nS
75 nS
- nS
75 nS
nS
95 nS
95 nS
75 nS
75 nS
nS
nS
80 nS
80 nS
90 nS
nS
nS
nS
95 nS

-

-

-

" See data book for additional Infonnatlon on these Items

HD 64180R1 AC Characteristics

vee. 5V +1-10%. V... 0 V. Ta. -20 to +7SOC
I::tC§jlAQBl~

&mim1.1l1m

!
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

tAl)

"tM
'tNt

1m,

leu.

'ta.''''two.
'~
twoz

Addl88& Delay Time
ME Delay Time 1
AddI1l88 Set-up Time
ME Delay TIme 2
Addrass Hold TIme
Enable Delay Time 1
Enable Delay Time 2
AD Delay Time 1
AD Delay Time 2
Data Read Set-up Time
Data Read Hold TIme
WR Delay TIme 1
WR Delay Time 2
Write Data Delay TIme
Write Data Set-up TIme
WR Pulse WIdth
Write Data Hold TIme
Write Data floating
Delay Time

Yin

t:tC§jl BgBl :fi
MIl

Yin

MIl
110
85

90
60

50

60

80

95
95
60
60

60 a
280

100

25
0
60
60
80

65
60
90
20
130
15

40
170
40

60

10
70
70
50
50

30
0

·40
• O·
90
90
110

10

50
20

35
100
100
85
85

95

I::tCII~lBl:lBi-lg·

Yin

80
50
20

30
85

50
0

l::tC§jlBIIBl-B
MIl

Yin

15
110
10
70

Mil
70 nS
50 nS
nS
50 nS
nS
60 nS
60 nS
50 nS
50 nS
nS
nS
50 nS
50 nS·
60 nS
nS
nS
nS
60 nS

-

-

-

• - Prellminaly Specilk:ation

Section

HITACHI

2

Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

308

HD64180 Family

Application Note

HD64180Z AC Characteristics
Vee. 5V +/- 10%, Vas" 0 V, Ta. -20 to +75"C

!

UbgI

1
2
3
4
5
6
7
8

tAl)
tllEl)1
tM
tloEllll
tAH
tED,
t_

'-I
'10M

9
10
11
12
13
14
15
16
17
18

leAH
lw-

t..wo

t..-

~
~

t..-

t:lCli!llllgZ-g
MIn
Mil

t:lCli!llllgZ~

.Ilim

MIn

Address Delay Time
ME Delay TIme 1
Address Set-up Time
ME Delay Time 2
Address Hold Time
Enable Delay Time 1
Enable Delay Time 2
RD Delay Time 1 IOC.1
10C.O
RD Delay Time 2
Data Read Set-up Time
Data Read Hold Time
WR Delay Time 1
WR Delay Time 2
Write Data Delay Time
Write Data Set-up Time
WR Pulse Width
Write Data Hold Time
Write Data Floatlng
Delay Time

Mil

Mil
80
50

90
60

110
85
30

50

10

60

50

35

10

20

100
100
85
85

95
95
60
65
60

85
50

40

0

0

70
70
50

60
50
25
0

30
0

90
90
110

60
60
80

65
80
90

60
280

15
110
10

20
130
15

40

170
40

60

70 nS

20

85
80

t:lCli!llllgZ-l g*
MIn
Mil

t:lC~lIlQZ-1I

MIn

100

70

95

50 nS
nS
50 nS
nS
60 nS
60 nS
50 nS
55 nS
50 nS
nS
nS
50 nS
50 nS
60 nS
nS
nS
nS
60 nS.

• PreUmlnary SpecllIc:aIlon

HD647180X AC Characteristics
Vee.5V +/-10%, Vas" 0 V, Ta. -20 to +75"C
11.

1
2
3
4
5
8

7
8
9
10
11
12
13
14
15
16
17
18

-

UbgI

tAl)
tAl

'tAH
1m,
tma

"'to..
loAtt

~,

t..wo
t..-

~
~

t..-

.Ilim
Address Delay Time
ME Delay Time 1
Address Set-up Time
ME Delay TIme 2
Addraa Hold Time
Enable Delay Time 1
Enable Delay Time 2
RD Delay Time 1 IOC.1

I:IC~lllg~~

t:lCIi!lZlllg~-g

I::IC~ZlllgH

MIn

MIn

MIn

110
85

MIl
60

20
60

85
80

35

50

40

0

0

30
0

65
80
90

90
90

110
60
280
60

20
95
95
60
65
60

100
100
85
85
85

20
130
15

40

170
40

100

95

Mil
80 nS

90
30

50

lOC-O

RD Delay Time 2
Data Read Set-up Time
Data Read Hold TIme
WR Delay TIme 1
WR Delay Time 2
Write Data Delay Time •
Write Data Set-up Time
WR Pulse Width
Write Data Hold Time
Write Data FIoatlng
Delay Time

MIl

50
50
-

nS
nS
nS
nS
70 nS
70 nS
50 nS
80 nS
50 nS
- nS
- nS
60 nS
60 nS
80 nS
- nS
- nS
- nS
70 nS

HITACHI
Hitachi America, Ltd. * San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section
2309

;1

Section

HITACHI

2

Hitachi America, Ltd,· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819 • (415) 589-8300

310

September, 1989

HD64180 Family
Application Note

Task Switching Using the 64180 MMU
Introduction

Hitachi'sHD64180 family ofdevices combine a wealth ofonchip 1/0 features with a Memory Management Unit (MMU)
which allows access to512Kor IMbyteofmemory 64Kbytes
at a time. The MMU features can be used to demonstrate a
.method of switching between multiple tasks residing in
different areas of physical memory.
This tasJt switching method is exammed here in a program
which bases the requests for task switches 011 events caused by
on-chip peripherals. The HD64180 family features used by
this program are also described, and flow charts for each task
and the imal coded program are also presented.
Some familiarity with the HD64180 devices is assumed. For
further information, please refer the HD64180 Microprocessor Hardware Manual, the HD647180X Microcontroller
Hardware Manual, and the HD64180 Software Manual.
H064180 Family Devices

The HD64180 features highlighted in this note are available
·ontheHD64180Rl,HD6418OZandHD647180Xmembersof
the family, and the code example shown will run on any of
these devices. References to the HD64180 throughout this
article refer to any of these three devices.
Thanks to the high integration of these devices, execution of
the code written for this note depends mainly on on-chip
features. Because of this, the code presented here will run on

many systems based on these devices. A HD64180Rl-based
single board computer was used to test this example code.
This boardcomputerconsistsoftheHD641SORI interfaced to
64K of EPROM in physical locations Oh - FFFFh, 64K of
SRAM in locations l0000h - IFFFFh, and RS232 drivers and
receivers connected for ASCI port 1 communications. A
switch was connected to the HD641SO's/lRQl input to allow
simulation of external events.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Mamie Mar

HD64180 Family

Application Note

Data: Task C and

1F800h

"

Too.

1FAOOh

Data: Task B only

1FOOOh

Data: Tasks A,B,C

OCOOOh

Task C code

OAOOOh

Task B code

08000h

Task A code

CBAR: F4h,
1111101001

-,--r-

v!OOOh

Common Area 1

V
Bank Area
(Task Code)
L-?'"4000h

03FFFh
OOOOh

pommon Area 0

Main Program and
Interrupt Vectors

OOOOOh

Logical Memory Space

Physical Memory Space

MMU Memory Mapping
Application: Time Control Using the HD64180
The features of the HD64180 are used in this application to
perform the following tasks:
- control an elapsed time clock in memory
- display the elapsed time on a display device (terminal)
connected to ASCI port 1, using the DMAC to transfer the
time information to the ASCI
- acknowledge the occurrence of an external event by
incrementing a count of the number of external events and
recording the time of the last occurrence
- display external event occurrence information to the
display device
- accept and service interrupts based on these events
These tasks are performed in response to requests made to the
HD64I80CPUbyextemai and internal events. Three of these
events (Programmable Reload Timer (PRT) channel 0 and
PRT channell count match, and external interrupt level I)
cause interrupts to occur, which are handled by theon-Chip
interrupt controller. The HD64180 polls for the fourth event,
which is the receipt ofa character by the SCI (RXRDY flag
. set).

In order to demonstrate the HD64ISO's ability to handle task
switching using the MMU, each of the interrupt driven tasks
is assigned to a different area of physical memory. Task
switching is handled by reprogramming the MMU to access
the area of memory where the task handler exists.
Memory Management
The HD64180 Memory Management Unit (MMU) allows
access to IMbyte of address space or 512Kbyte of address
space (for HD64180Rl DIP package, due to pin limitation).
To maintain compatibility withZSO-type devices, at any point
in time the device has access to 64Kbytes of memory. These
64Kbytes are addressed directly as a contiguous block of
logical memory,
This logical memory actually maps into up to three different
portions of physical memory. This mapping of logical
addresses to physical addresses is accomplished using the
three registers related to the MMU: the Common/Bank Area
Register (CB AR) , the Common Base Register (CBR), and the
Bank Base Register (BBR),

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

312

HD64180 Family

Application Note

Task A Code Execution Start Address: .

o0

BBR: 04h

Logical Addresses: +
Physical Addresses:

000 1 0 0

o1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

(4000h,logical base of code)

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 8000h

Task A Data Storage Start Address:
CBR: 10h

000 1 0 0 0 0

Logical Addresses:
Physical Addresses:

+

1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

(FOOOh, logical base of data)
= 1FOOOh

64180 family MMU logical to Physical Address Calculation

These registers divide the logical address space into up to
three areas, referred to as Common Area 0, Common Area ·1,
and Bank Area. The starting logical and physical address of
Common Area 0 is always location OOOOh. The starting
logical addresses of Bank Area and Common Area 1 are
specified by the CBAR. The physical starting address of
Common Area 1 and the Bank Area are specified using the
CBR and BBR, respectively.
Keep in mind that the actual physical starting address of the
Bank Area and Common Area 1 is not determined solely from
the CBR and BBR. These registers specify an eight-bit value
that is added to most significant four bits of the logical address
to provide the most significant 8 bits of the physical address.
See the MMU Memory Mapping figure shown above.
180's features can be used to trigger task servicing
The HD64180's on-chip peripheral features provide the capabilities required to carry out this application. The two
channels of programmable reload timer are each capable of
counting down from a programmed value, and generating an
interrupt when a count of zero is reached.
PRTO is programmed to count down every .01 second. The
interrupt service routine requested when PRTO's countdown
interrupt occurs increments the elapsed time clock stored in
memory.

elapsed time stored in memory. PRTl is programmed to cause
an interrupt every tenth of a second. Service of this interrupt
involves initializing and initiating DMAC channell, which is
used to display the elapsed time.
The full duplex ASCI channel serves two purposes for this
application. The transmitter portion is used to transfer elapsed
time (using the DMAC, as mentioned above) and external
event information to the terminal screen. The RDRF bitofthe
receiver, set when data is received, can be used to initiate a
task (display of event data) whenever a key press occurs on a
terminal connecter to the ASCI port.
Interrupt Handling
The HD64180's interrupt controller handles interrupts from
four external sources and eight internal souces. These interrupts are maskable (except for the Non Maskable Interrupt,
NMI, and the Undefined Op-code Trap, TRAP), and are
prioritized with fixed priority. Upon receiving and accepting
an interrupt, the controller in most cases determines the
location of an interrupt service routine using a vector table that
is programmably located in memory.
Two other modes of vector generation are available with
external interrupt 0 (INTO), one fetches vector information
from the bus, the other vectors directly to a fixed location.

PRTl is used by this application to trigger the display of the

The HD64180 prioritizes interrupts using fixed priority levels. The priorities of the interrupts used for this program are

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2313

HD64180 Family

Application Note
(from highest to lowest): \IRQ I, PRTO countdown, followed
by PRTl countdown. Note that for correct operation, PRTO
interrupt must always be accepted in order to maintain the
elapsed time.
Program Design Notes

CPU Activity During Program Operation

Begin Execution of
Main Task

Once the CPU and on-chip peripherals are initialized for this
application, no further activity need be undertaken until an
event (PRT time-out, external interrupt, receiver data ready)
occurs. Since all these events can generate an interrupt to the
CPU, the HD64180 could be placed in a sleep mode, to be
awakened when an interrupt occurs.
Another option is to have the CPU poll for one of the events
following initialization. This method was selected, and the
least important task, in this case, reporting external event
information, was chosen to be the task request polled. The
remainder of the tasks interrupt this task whenever the event
triggering them occurs.

Memory Configuration Considerations
The physical hardware to be used must be considered in
designing the program. Since the program is to be placed in
EPROM, data areas that are modified by the program must be
singled out and placed in RAM. These data areas must also
be initialized by the program to bring them to a known state.
Additionally, the program's use of logical and physical
memory must be determined. Program initialization and the
polling loop were selected for execution out of common area
1. Note that although this area starts at logical and physical
address OOOOh, the starting address of program code in this
area must be selected carefully. The HD64180 expects a reset
vector to be located at physical address OOOOh, and the
interrupt vector table may also be located starting in this area,
depending on the programmed values for the IL (Interrupt
vector Low) register.
The bank area was selected for execution of the tasks.
Logically, this was setto 4000h. The MMU is reprogrammed
by the task switcher to access each of the different tasks at this
location, so the physical address of each task differs.

Main Task Flow Diagram

Finally, Common Area I was selected for use as the data areas
accessed by the different tasks. Since only a small amount of
data area is required, this logical area is programmed to start
at FOOOh. This logical address space maps to physical
addresses in RAM for this program.

Section

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314

HD64180 Family

Application Note
The program to carry out the tasks outlined above was written
in sections. The main program, to execute out of Common
Area 0, consists of initialization of the HD64180 core and the
on-chip peripherals functions to be used, and initialization of
the RAM areas to be usedfor display data and the elapsed time
clock. Following initialization, this main program enters a
routine that continually checks for a keystroke on the terminal
keyboard, which is signalled by the RXD bit of the serial
channel 1 being set to 1.
The second section of code performs task switching, and is
entered each time one of the enabled interrupts occurred. This
section reprograms the MMU and preserves register contents
prior to initiating the execution of interrupt service routines.
This section also handles return from exception, by restoring
register contents.
The other code sections perform the different tasks signalled
for by interrupts. Task A increments the clock every .Q1
second. Task B counts the PRTI interrupts requested and
initializes theDMAC and enables the DMAC on theappropriate counts.

of the assembler.

Execution of Task C results from an external event indicated
by interrupt\IRQ1 going active. Task C increments a count
of external events, and record the current value of the elapsed
time clock.

For this program, the default reset value for the I/O Registers
base address was taken. Similarly, the Operation Mode
Control Register (OMCR) available in the HD64180Z and
HD647180X was not reprogrammed from its' default value.

The resulting program is shown in the Appendix.

On-chip Peripheral Initialization

Initialization

ASCI channel I and the PRT channels are initialized by
writing the appropriate values into the associated control
registers. PRTO is programmed for a count based on the CPU
clock and a start count and a reload count ofh'1200, which
results in an interrupt once every .01 seconds with a CPU clock
of 9.216 MHz. During service of this interrupt, the elapsed
time clock is updated.

At power-on, the HD64180 control registers take on default
values that allow the device to operate according to default
conditions. If deviation from these defaults is desired, the
individual registers must be programmed with new initialization values. The stack pointer must be programmed to a valid
address for stack operations to be performed correctly.
For this program, the MMU control registers were programmed to divide the logical space into three areas, accessing three different sections of physical memory. Since
SRAMs were used, the refresh capability of HD64180 was
turned off by writing to the Refresh Control Register (RCR).
The Interrupt Vector Table and I/O Registers are relocatable
by programming their associated control registers. The
Interrupt Vector Table was located al20H by programming
the II. register, so that the reset vector located at OOH would
not overlay the vector entry for /INTI. Note that the interrupt
vector table was initialized in EPROM using the capabilities

Note that DMAC channel 0 must be used in order to cause
DMA transfer to or from the on-chip serial channel. This
channel is connected to the serial channels internally, allowing these transfers to occur. For this transfer to operate
correctly, DMA channel 0 must be used, bits 0-2 of the DMA .
Destination Address Register DAROB must be programmed
for the. correct destination, and the channel must be programmed to respond to edge-sense requests using the DMS
(DMA request Sense) bits of the DMA/WAIT Control Register(DCNTL).
Values for ASCI baud rate (in CNTRLB 1) and PRT data and
reload registers were determined based on the CPU clock

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2315

HD64180 Family

Application Note
controller must be set. This is accomplished by executing the
EI instruction.
Task switching using the MMU

As mentioned previously, the HD64180's logical address
space is divided into the three areas allowed by the MMU.
Common Area 0 is used for RAM initialization data, interrupt
vectors, initialization code, and the main task execution.
Common Area I is used for shared RAM space, which stores
the elapsed time clock data and other data that is manipulated
by the tasks. The Bank area is used for executing the subtask
code segments.
.
Since the subtask execution code is always mapped to the
logical addresses of the Bank area, task switching can be
accomplished by storing the existing values of the MMU
registers to the stack, reprogramming them to access the
physical locations of the new task and its' associated data
RAM area, and jumping to the first location of the bank area.
With this scheme, each task can be located in a different area
no

Move to next more
significant position
of clock value

>-''''''-_ _~ Initialize DMAC
for clock output
to ASCI

Task B Flow Diagram
input crystal frequency of 9.216MHz.
Interrupt Enable

Once the HD64180 has been initialized for operation, interrupts can be enabled, and the main task can be initiated.
Enabling interrupts is a two level process.
First, individual bits in control registers must be set to enable
interrupts. For the PRT channels, the Timer Interrupt Enable
(TIE) bits of the Timer Con,. l Register (TCR) must be set.
At the same time, the Timer countdown can be started by
setting the Timer Down Count Enable (TOE) bits. To enable
INTI and disable INTO, which is enabled at reset, the appropriate bits of the ITC must be programmed.
Second, the Interrupt Enable Flags (IEF) of the interrupt

Task C Flow Diagram

Section

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Hitachi America, Ltd.' San FranciSCO Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

316

HD64180 Family

Application Note
of physical memory, yet still be accessed using the same
addresses in logical memory.
In more complex applications, this method of switching tasks
all.ows easy handling of the non-contiguous memory space.
Although the entire code for this application could have fit in
the directly addressable 64Kbyte memory space, more complex code would have to be broken into sections that would fit
within the logical address space.
In this example, all tasks accessed the same data area, and the
CBR was not reprogrammed during task switching. Note that
by reprogramming the CBR register, physical data area
locations can be switched at the same time as physical code
areas.
Coding the Tasks
The main task operates continuously, and is interrupted by the
other tasks based on events. This tasks consists simply of
polling the RDRF bit of the ASCIl status register to detect
when a key has been pressed on the terminal. When a key
input is detected (RDRF set), a routine is entered which
. displays the current external event information stored in RAM
by transferring the data character by character through ASCI
channell.
Task A is executed in respo~se to the PRTO countdown
. interrupt. This task increments the elapsed time clock that is
stored in RAM. Note that Task B interrupt requests are
disabled during the main task execution, to prevent time data
from being updated to the screen during the event display.
However, note also that the elapsed time and external events
can be accepted.
Task B is executed in response to the PRTl countdown
interrupt. The DMA controller is initiated as part of this task
for data transfer to the ASCIl transmit data register . When the
Task B interrupt count reaches 10, the elapsed time clock
value is copied to the memory location indicated as the DMA
source address, and DMA transfer for channel 0 is enabled.
This causes the current elapsed time to be display to the
terminal through ASCIl. Copying the elapsed time clock
value during Task B execution eliminates the possibility of a
PRTO interrupt changing the time during output to the terminal. Since DMA transfer continues beyond the time that Task
B ends and interrupts are reinabled, it is possible that Task A
could increment the elapsed time clock in memory before the
entire DMA transfer completed.

Task C interrupts are serviced in response to an INTI interrupt, which signals an external event. This routine simply
copies the current elapsed time toa buffer in memory to record
the time of the most recent event, and increments the event
counter. To simplify programming, the event counter can
increment to a maximum of nine. This event information is
displayed by the main task in response to a key entry. If more
than nine external events have occurred, an "*" is displayed
in place of the number of external events.
Assembling Code for MMU Task Switching
Since the logical and physical addresses differ for the sections
of code and data that are located outside of Common Area 0,
care must be taken when specifying code addresses during ~
assembly. Since the processor uses the logical addresses for t>
execution, code should be located at the logical address space ~
during assembly. For this example, all task code should be
ORGed or located at h'4000, the logical address for task
execution.
When downloading code to a development system or
EPROMs, an offset should be specified so that the code is
physically loaded to the correct address. For instance, Task
C would be ORGed to location 4oo0h. When downloading to
development system memory, an offset of 6000h should be
specified so that the code would be loaded to the correct
physical address of AOOOh, where the MMU will expect it to
be.
Summary
This application identifies how the HD64180R, HD64180Z
and HD647180X devices' on-chip features can be used in a
multi-tasking operation. Reprogramming the MMU to initiate task switching allows for a simple method of allocating
physical address space to executable code. The on-Chip
Programmable Reload Timers can generate interrupts which,
during interrupt service accumulate elapsed time. The onchip Serial Communications Interface controls transfer of
data to a terminal, either using DMA or program transfer of
data to the SCI transfer registers.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2317

B

HD64180 Family

Application Note

APPENDIX: Main Task Code Listing
;**********************************************************

64180 Application Program
Elapsed time clock and external event logger
Main Program:

(1n common area 0)

Initializes the 64180 as follows:
Interrupt vectors are loaded to

h~20

HMU is set up so that:
Common Area 0 is fixed at h'OOOO
Bank Area is at logical 4000h
Common Area I is at logical FOOOh
PRTO - generates an interrupt every .01 sec
PRTl - generates an interrupt every .1 ·sec

ASCIO - displays elapsed time clock
DMACO - handles transfer of data to terminal
- Enters a loop ,polling for RxD condition
RxD Handler: (follows main program)
- Initializes pointers for display of event data

- Polls for TDRE, displays event data
- Returns to loop polling for RxD condition
- PRT1 interrupt disabled during this routine
Task Switcher:

(in common area 0)

- stores current HMU context

- loads HMU values for next task
- executes task code

- executes return from interrupt

Task A: (in bank area, physical 8000h)
- Results from PRTO timer interrupt (every .01s)
- Increments elapsed time clock in common area 1
- Returns to Task Swit~her
Task B: (in bank area, physical AOOOh)
- Results from PRT1 timer interrupt (every .1s)
- Increments count of task B inte,rrupts
- If count - 5, then
initialize DMACO for displaying clock
- If count = 10, then
reads and stores elapsed time clock
starts DMACO to display time
resets count
- Returns to Task Switcher
Task C: (in b'ank area, physical COOOh)
'- Results from external event (INTI)
- Records Elapsed Time Clock value (time of event)
- Increments event count
- Returns to Taak,,$witcher

"

Section

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

318

HD64180 Family

Application Note
APPENDIX: Main Task Code Ulting (continued)
00'0000
000000
000000

PAGE
CPU -64180. TBLINCL -INTIO. LIB64180 Internal I/O register equates
Copyright 1988, SOFTAID, INC., Columbia, MD.
Note: BASE must be defined as the internal I/O
relocation offset of OOh, 40h, 80h or OCOh
and register ICR must be set appropriately.

00000000

BASE:

EOU

OOh

00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000001
00000008
00000009
OOOOOOOA
OOOOOOOB
OOOOOOOC
00000000
OOOOOOOE
OOOOOOOF
00000010
00000014
00000015
00000016
00000011
00000020
00000021
00000022
00000023
00000024
00000025'
00000026
00000021
00000028
00000029
0000002A
0000002B
0000002C
0000002E

CNTLAO:
CNTLA1:
CNTLBO:
CNTLB1:
STATO:
STAT1:
TDRO:
TDR1:
RDRO:
RDR1:
CNTR:
TRDR:
TMDROL:
TMDROH:
RLDROL:
RLDROH:
TCR:
TMDR1L:
TMDR1H:
RLDR1L:
RLDR1H:
SAROL:
SAROH:
SAROB:
DAROL:
DAROH:
DAROB:
BCROL:
BCROH:
HARlL:
MAR1H:

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

OOH
OlH
02H
03H
04H
05H
06H
01H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH
10H
14H
15H
16H
18H
20H
21H
22H
23H
24H
25H
26H
21H
28H
29H
2AH
2BH
2CH
2EH

MlIP'Il:

IAR1L:
IAR1H:
BCR1L:

BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
+ BASE'
+ BASE
+ BASE
+ BASE
+ BASE
+ BASE
+ BASE,
+ BASE

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

ASCI CONTROL REGISTER A CH 0
ASCI CONTROL REGISTER A CH 1
ASCI CONTROL REGISTER B CH 0
ASCI CONTROL REGISTER B CH 1
ASCI STATUS REGISTER CH 0
ASCI STATUS REGISTER CH 1
ASCI TRANSMIT DATA'REGISTER CH 0
ASCI TRANSMIT DATA REGISTER CH 1
ASCI RECEIVE DATA REGISTER CH 0
ASCI RECEIVE DATA REGISTER CH 1
CSI/O CONTROL REGISTER
CSI/O TRANSMIT/RECEIVE DATA REGISTER
TIMER DATA REGISTER CH OL
TIMER DATA REGISTER CH OH
RELOAD REGISTER CH OL
RELOAD REGISTER CH OH
TIMER CONTROL REGISTER
TIMER DATA REGISTER CH lL
TIMER DATA REGISTER CH 1H
RELOAD REGISTER CH lL
FREE RUNNING COUNTER
DHA SOURCE ADDRESS REGISTER CH OL
DHA SOURCE ADDRESS REGISTER CH OH
DHA SOURCE ADDRESS REGISTER CH OB
DHA DESTINATION ADDRESS REGISTER CH OL
DHA DESTINATION ADDRESS REGISTER CH OH
DHA DESTINATION ADDRESS REGISTER 'CH OB
DHA BYTE COUNT REGISTER CH OL
DHA BYTE COUNT REGISTER CH OH
DHA MEMORY ADDRESS REGISTER CH lL
DHA MEMORY ADDRESS REGISTER CH lH
DHA MEMORY ADDRESS REGISTER CH lB
DHA I/O ADDRESS REGISTER CH lL
OHA I/O ADDRESS REGISTER CH 1H
DHA BYTE COUNT REGISTER CH lL

"''HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300

Section

2319

HD64180 Family

Application Note

APPENDIX: Main Task Code Listing (continued)
0000002F
00000030
00000031
00000032
00000033
00000034
00000036
00000038
00000039
0000003A
0000003F

BCR1H:
DSTAT:
DMODE:
DCNTL:
IL:
ITC:
RCR:
CBR:
BBR:
CBAR:
ICR:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

2FH
30H
31H
32H
33H
34H
36H
38H
39H
3AH
3FH

+
+
+
+
+
+
+
+
+
+
+

BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE
BASE

DMA BYTE COUNT REGISTER CH 1H
DMA STATUS REGISTER
DMA MODE REGISTER
DMA/WAIT CONTROL REGISTER
IL REGISTER(INTERRUPT VECTOR'LOW REG)
INT/TRAP CONTROL REGISTER
,REFRESH CONTROL REGISTER
MMU COMMON BASE REGISTER
MMU BANK BASE REGISTER
MMU COMMON/BANK AREA REGISTER
I/O CONTROL REGISTER

Programmable reload timer enable equates
00000001
00000010

PRT":'COUNT:
PRT_INT:

EQII
EQU

TIMER COUNT ENABLE
TIMER INTERRUPT ENABLE

01H
10H

ASCI initialization and status equates
00000000
00000001
00000002
00000003
00000004
00000005
00000006

ASCI_38400:
ASCI_19200:
ASCI_9600:
ASCI_4800:
ASCI_2400:
ASCI_1200:
ASCI_600:

EQU
EQU
EQU
EQU
EQU
EQU
EQU

OOH
01H
02H
03H
04H
05H
06H

BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD

00000004
00000002
00000001

EQU
ASCI~8BITS:
ASCI_PARITY: EQU
ASCI_2STOP:
EQU

04H
02H
01H

DATA BITS
PARITY ENABLE
2 STOP BITS

00000002
00000080
000000

ASCI_TDRE:
ASCI _ RDRF: '

EQU
EQU
HOF

02H
80H
"INT16 N

TDRE BIT MASK
RDRF BIT MASK

00000000
00000000
OOOOOOOA
00000000
000000B4
00000000
00000012
00004000

NULL:
CR:
LF:
TILOW:
TIHI:
TOLOW:
TOHI:
BANK:

EQU
OOh
EQU
ODh
EQII
OAh
EQU
OOOh
EQU
OB4h
EQU
OOh
EQU
012h
EQU
04000h ; bank logical location for task
; handling routines

RATE
RATE
RATE
RATE
RATE
RATE
RATE

Section

HITACHI

2

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320

HD64180 Family

Application Note
APPENDIX: Main Taskeode Listing (continued)

;**********************************************************
Data Storage

- System Data
ORG

000000
000000 C30001
000020
000020
000022
000024
000026
000028
00002A
00002C
00002E
000030

B901
DE01
AB01
B201
DE01
DE01
DE01
DE01
DE01

JP

ORG
INT1: OWL
INT2: OWL
PRTO: OWL
PRT1: DWL
DMAO: OWL
DMA1: OWL
CSIO: OWL
ASCIO:
ASCI1:

OOh
CLSTART

020h
TASKC
INTEND
TASKA
TASKB
INTEND
INTEND
INTEND
OWL
OWL

;initialize reset information

; interrupt vector table
;external event interrupt

II

:timer 0 countdown interrupt
:timer

countdown interrupt

INTEND
INTEND

Preliminary Storage area for task data - data in this
area (ROM) is moved to RAM during initialization
ORG

000040

040h

; storage area (Common 1)

;used by all tasks
000040 30303A30303A30ELCLK:
00004A 3000

00004C
00004F
000050
000062
00007A
000088

EVDATA:
ODOAOA
30
206576656E1473
204C6173742065
30303A30303A30
00

DFB
DFB

~OO:OO:OO.OH

"D",eR

;storage area X (Common 1)
;used by Task Conly
DFB CR,LF,LF
DFB
30h
;storage for count of events
DFB
" events occurred",CR,LF
DFB

" Last event occurred at "

DFB
DFB

~OO:OO:OO.OON,CR,LF,LF

OOh

«=

9)

lend of data
; storage area Y (Common 1)

; used by Task B
000090
000090 00
CTRDATA:
000091 30303A30303A30

ORG
DFB
DFB

090h
Oh
·OO:OO:OON,CR

HITACHI
HitachiAmerica, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Section

2321

HD64180 Family

Application Note

APPENDIX: Main Task Code Listing (continued)
RAM DATA TABLE:

the following sets up logical

addresses to correspond with those used in

tasks. These addresses map to physical RAM,
which must be intialized by the main program
OOFOOO

ORG

OFOOOh

OOFOOO 30303A30303A30ET_CLK: ,
OOFOOA 3000
ET_CLKend:

OFB
OFB

·OO:OO:OO.OH
·OR,eR

00F800

ORG
OF800h
;storage area X (Common 1)
;used by Task Conly
OF~
CR,LF,LF
OFB
30h
;storage for count of events
DFB
.. events occurred",CR,LF
.. Last event occurred at ..
OFB
·OO:OO:OO.OOH,CR,LF,LF
OFB
OOh
; end of data

;storaqe area (Common 1)

;used by all tasks

OOFSOO
00FB03
00F804
00FB16
00F82!
00FB3C

OOOAOA
30
EVNT_CT:
206576656E7473
204C6173742065
30303A30303A30LAST_EV:
00

OOFAOO

ORG

«=

9)

OFAOOh
istoraqe area Y

(Commo~

1)

;usedby Task B
OOFAOO 00
CTR:
00FA01 30303A30303A300_TIME:
OOFAOA

OFB
OFB

Oh
·OO:OO:OOH,CR

PAGE
;******************************************************** ••

Initialization routines for 64180
000100

ORG

100h

Initialize MHU: common 0 at location OOOOh (logical)
common 1 at location FOOOh (logical)
bank at location 4000h (logical)
000100
000102
000105
000107
OOOlOA
OOOlOE
000110
000112

3EF4
E0393A
3EIO
E03938
0021FFFF
00F9
3EOO
E03936

a

LO
OUTO
LO
CUTO
LO
LO
LO
CUTO

A,OF4h ;Common 1 at FOOOh, Bank at 4000h
(CBAR),A
A,lOh ;Commonl physical at IFOOOh
(CBR),A
;stack at high memory
IX,OFFFFh
SI?,I'X
A,OOh ;turn off refresh insertion
(RCR),A

.

HITACHI

SectIon
322

CLS'!',~RT:

H~chi

America, Ltd. 0 San Francisco Center 0 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005·1819 0(415) 589·8300

HD64180 Family

Application Note
APPENDIX: Main Task Code Listing (continued)
000115

PAGE
i·**************************************************** *****
Initialize interrupt vector registers,

000115 3E20
000117 ED3933

LD
A,20h
aUTO (IL) ,A

table

;use low memory page

:1 initialized to DOh on reset

i**************·*********************************·**** *****

Initialize common RAM areas

00011A
00011D
000120
000123

214000
1100FO
010COO
EDBO

LD
LD
LD
LDIR

HL,ELCLK
OE,ET_CLK
BC,12

000125
000128
00012B
00012E

214COO
1100F8
013DOO
EDBO

LD
LD
LD
LDIR

HL,EVDATA
DE,EV_START
BC,61

000130
000133
000136
000139

219000
1100FA
010AOO
EDBO

LD
LD
LD
LDIR

HL,CTRDATA
DE,CTR
BC,IO

00013B

idata to be moved to RAM
:data area to be loaded

; count of characters

;data to be moved to RAM

;data area to be loaded

; count of characters

:data to be moved to RAM
;data area to be loaded

; count of characters

PAGE
i**·************************************************** *****

Initialize ASCI1 for serial communications
9600 baud, 7 data bits, 1 stop bits, no parity

0001 .

10
0001
3901
21
0001
00014" .003903
000145 3EOO
000147 ED3905

SCINIT:

LD
OUTO
LD
OUTO
LD
aUTO

A,70h
(CNTLA1) ,A
A,21h
(CNTLB1) ,A
A,OOh
(STATl) ,A

;RE,TE,7,N,1

;9600 at 9.216MHz

;disable receiver interrupts

;**********************************************************

Initialize PRTO for interrupt every .01 second
Interrupts not yet enabled
00014A
00014D
00014F
000152
000155

011000
3EOO
ED390C
ED390E
3EI2

"OINIT:

LD
LD
aUTO
aUTO
LD

BC,TCR
A,TOLaw
(TMDROL) ,A
(RLDROL) ,A
A, TOHI

jload address of register
jtimer data register OL
;reload data register OL

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2323

HD64180Family

Application Note

APPENDIX: Main Task Code listing (continued)
000157 ED390D
,00015A ED390F
00015D

OUTO
OUTO

(TMDROH) ,A
(RLDROH) ,A

;timer data register OH
;reload data reqister OH

PAGE
:***************************************** ••• *.***********.

Initialize PRTl for interrupt every .1 second
Interrupts not yet enabled

00015D
00015F
000162
000165
000167
00016A
000160

3EOO
ED3914
ED3916
3EB4
ED3915
ED3917

LD
OUTO
OUTO
LD
OUTO
OU:rO

A,T1LOW
(TMDR1L)-,A
(RLDRIL) ,A
A,T1HI
(TMDR1H) ,A
(RLDRIH) ,A

;timer data register lL

;reload data register lL
;timer data register lH
;reload data register lH

PAGE
;****************************************************.*****

Enable all Interrupts, start clock, and wait for RxRDY
00016D
00016E
000170
000173
000175

FB
3E02
ED3934
3E33
ED3910

EI
LD
LD

A,02h
OUTO
A,33h
OUTO

(ITC) ,A

;enable INT1 interrupts

(TCR),A

;start PRT timers

;**********************************************.***********

MAIN TASK:
Loop here until RxRDY received from ASCIO

000178 010500
00017B ED7480
00017E 28F8

KEYLOOP:

LD
TSTIO
JR

BC,STAT1
80h
Z,KEYLOOP

;ASCI status register
;tests i f RDRF

Reach here when RxRDY received'
000180
000183
000185
000188
00018A

ED3809
3E13
ED3910
3E20
ED3930

00018D
000191
000194
000196

DD2100F8
ED7402
28FB
D07EOO

Section
324 2

KEYIN:
OUTLP:

INO
LD
OUTO
LD
OUTO

A, (RDR1)
A,13h
(TCR),A
A,20h
(DSTAT) ,A

LD
TSTIO

IX,OF800h
02h
Z,OUTLP
A, (IX+O)

JR

LO

;read RDR to clear RDRF
;disable Task B irq
;disable DMA in progr,ess

;tests i f TDRE
;get memory to output

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300

HD64180 Family

Application Note
APPENDIX: Main Task Code Listing (continued)
000199
00019B
000190
0001AO
0001A2

FEOO
2807
E03907
0023
18EO

00.01A4 3E33
0001A6 E03910
0001A9 18CO

CP
JR

OUTO
INC
JR

KEYENO:

LO
OUTO
JR

;test if end of string

NULL
Z,KEYENO
(TOR1),A
IX
OUTLP

;output to asci port 1
:increment memory pointer

A,33h
(TCR),A
KEYLOOP

;enable timer irqs

:*************************************************************
Task Switcher - interrupt service

entry point to this section depends on IRQ recv'd

.0001AB
0001AC
OOOlAE
OOOlBO

C5
OE04
0610
180C

TASKA:

0001B2
0001B3
0001B5
0001B7

C5
OE06
0610
1805

TASKB:

0001B9 C5
000lBA OE08
OOOlBC 0610

TASKC:

OOOlBE E01838
OOOlCl E01039
0001C4 05

enter here for PRTO irq
PUSH BC
C,04h
:task A at physical 8000h
LD
B,10h
: common 1 at physical 10000h
LO
SWITCH
JR
enter here for PRTl irq
PUSH BC
C,06h
:task B at physical AOOOh
LD
B,10h
: common 1 at physical 10000h
LO
SWITCH
JR

enter here for IRQl request
PUSH BC
;task C at physical COOOh
C,08h
LO
;common 1 at physical 10000h
B,10h
LO

Task switches handled here
SWITCH: INO E, (CBR) ; read commonl base address
INO
0, (BBR)
; read bank base address
PUSH
DE
; save to stack

0001C5 E00939
0001C8 E00138

OUTO
OUTO

(BBR),C
(CBR),B

OOOlCB E5
OOOlCC F5
OOOlCD 00E5

PUSH
PUSH
PUSH

AF

; initialize BBR
; initialize CBR

HL
;save context prior to lnt sve

IX

Memory switched, call task handler routine
000lCF C00040

CALL

BANK

;switch to task in bank area

HITACHI
Hitachi America. Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 5B9-8300

Section

2325

HD64180 Family

Application Note

APPENDIX: Task Switcher Code Listing
Task complete, perform clean-up for return from task

000102
000104
000105
000106
000107
00010A
000100

00E1
F1
E1
01
E01139
E01938
Cl

00010E FB
00010F E040
000000

Section
326 2

RETURN:
POP
POP
POP
OUTO
OUTO
POP

POP
AF

IX

HL
DE
(BBR) ,0
(CBR) ,E
BC

; restore MMU

;restore MMU

INTEND: EI
RETI
END

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

HD64180 Family

Application Note
APPENDIX: Task A Code listing

;*-* •••••• __ ••• __ .* •• _-_ •• _**_ •• __ ._ •• *_ •• * •••

TASK A ROUTINES:

-.***.-... **.

Interrupt service for timer 0

- Causes elapsed time clock to increment by
one hundredth of a second

;.* ••••••

_._._---*-_._-*._- .. -._-_. __ .. _._ ... _--* •• _••.••• -

Task A Code: executed upon receipt of PRTO interrupt
CPU
INCL

000000
000000

·64l80.TBL"INTIO.LIBR

;.. _._ .. _... *._ ...... ** •• _. ____ ._ •••• _•• ___ ** __ ._*_ .. _*xxx.
Use same table of equates as for Main Task

RAM area loaded with data by main program
ORG

OOFOOO

OFOOOh

;storaqe area (Common 1)

OOFOOO 30303A30303A30ET_CLK:
DFB
"00:00:00.0OOFOOA 300D
ET_CLKend:DFB 'OR,CR
OOFOOC

PAGE

;** ____ •• __ • ___ ._ ••• _ •• __

._* .• __ ._ .. _____ .____ ._._** •.. ww*_

Task A: increment elapsed time clock

ORG

004000
004000
004004
004006
004009
00400B
00400D
00400F
004012
004014
004016
004019
00401B
00401D
00401F
004022
004024
004026

DD210AFO
3EOl
DD8600
FE39
2018
3E30
DD1100
DD2B
3EOl
DD8600
FE39
2068
3E30
DD1100
DD2B
DD2B
3EOl

CLK_CHG:
LD
ADD
CP
JR

LD
LD
DEC
LD
ADD
CP
JR
LD
LD
DEC
DEC
LD

;org at logical address

4000h

;IX contains address of clock
IX,ET_CLKend
LD
A,Olh
;1ncrement
A, (ix+o).
;if 3A, then update
39h
NZ,UPDATE
;reset to 0
A,30h
;prepare to incr preceeding
(IX+O) ,A
IX
A,Olh
; increment
A, (IX+O)
;it 3A, then update
39h
NZ,UPDATE
A,30h
" ; reset to 0
:prepare to incr preceeding
(IX+O) ,A
IX
; skip period
IX
A,Olh

HITACHI
Hitachi America, Ltd.' San Francisco Center • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

Sectlon
2327

·HD64180 Family

Application Note

APPENDIX: TakA Code Listing (continued)
update seconds
004028
00402B
004020
00402F
004031
004034
004036
004038
00403B
004030
00403F
004041
004044
004046
004048

008600
FE39
2056
3E30
001700
002B
3E01
008600
FE36
2046
3E30
007700
002B
002B
3E01

AOO
CP

JR
LO
LO
OEC
LO
ADO
CP

JR
LO
LO
OEC
DEC
LO

A, (IX+O)
39h
NZ, UPOATE
A,30h
(IX+O) ,A
IX
A,Olh
A, (IX+O)
36h
NZ,UPOATE
A,30h
(IX+O) ,A
IX.
IX
A,Olh

iincrement
;if 3A, then update
;reset to 0

;prepare to incr preceeding

; increment
;if 37 (>60), then update
;reset to 0
;prepare to incr preceeding

; skip period

update minutes
00404A
004040
00404F
004051
004053
004056
004058
00405A
004050
00405F
004061
004063
004066
004068
00406A

008600
FE39
2034
3E30
001700
002B
3E01
008600
FE36
2024
3E30
001700
002B
002B
3E01

AOO
CP
JR

LO
LO
OEC
LO
ADD
CP
JR

LO
LO
OEC
OEC
LO

A, (IX+O)
39h
NZ,UPOATE
A,30h
(IX+O) ,A
IX
A,Olh
A, (IX+O)
36h
NZ,UPOATE
A,30h
(IX+O) ,A
IX
IX
A,Olh

; increment
;if 3A, then update
:reset to 0
;prepare to incr preceeding

; increment
; H 37 (>60), then update
:reset to 0

;prepare to incr preceeding
; skip period

update hours
00406C
00406F
004071
004073

008600
FE39
2012
3E30

AOO
CP

004075
004078
00407A
00407C
00407F
004081
004083

007700
002B
3E01
008600
FE39
2002'
3E30

to

Sec1lon
328 2

JR

LO
DEC

to
ADO
CP

JR

to

A, (IX+O)
39h
NZ,UPOATE
A,30h
(IX+O) ,A
IX
A,Olh
A, (IX+O)
39h
NZ,UPOATE
A,30h

; increment
;if 3A, then update
;reset to 0
;prepare to incr preceeding

; increment
;if >100, then reset to 0
;reset to

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD64180 Family

Application Note
APPENDIX: TaskA Code Listing (continued)
004085 001700

UPOATE:

(IX+O) ,A

LO

INO

A, (TCR)

00408B E0380C

INO

A, (THOROL)

00408E C9

000000

;prepare to incr preceeding

iread timer registers to reset

004088 E03810

timer interrupt

;return from task routine
; to task switcher
;*.***********.******* •• **** •••• ********************** ••• **
RET

ENO

HITACHI
Hitachi America, Ltd.• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2329

HD64180 Family

Application Note

APPENDIX: Task B Code Listing
:*********************************************************-

Task B - Executed upon receipt of PRTl interrupt

000000
000000

CPU
INCL

~64180.TBLN
~INTIO.LIBN

Include same table of equates used for Main Task
i***************************************************** *****

Data Storage
- System Data
OOE'OOO

OFOOOb ; storage area (Common 1)
by all tasks

ORG
;u~ed

OOFOOO 30303A30303A30ET_CLK:
ET_CLKend:
OOFOOA 300D

DFB
DFB

OOFACO
CTR:
OOFAOO 00
00FAC1 30303A30303A30D TIME:

ORG
DFB
DFB

~OO:OO:OO.O"
~O",CR

; storage area Y (Common 1)
;used by Task 8

OFAOOb
Ob

~OO:OO:OOH,CR

i*******-**·**··***_··*************·*****-*-_·_******* *****

Task 8 - Prepare for and perform DMA to ASCIl
ORG

004000
004000
004004
004006
004009
00400B

DD2100FA
3EOl
DD8600
FEOS
2005

CLK._DSP:
LD
ADD
CP
JR

4000b

iorg at logical address

IX,CTR
LD
A,Olb
A, (IX+O)
OSb
NZ,SEC_CHK

;IX contains address of count

; increment
;cornpare to 5

reach bere if count equals S

00400D
004010
004012
004014

CD3140
181B
FEOA
2017

CALL
JR
SEC_CHK:
JR

:if

DMINIT
DSP_END
CP
OAb
NZ,DSP_END

=c

5, initialize DMAC

icompare to 10

reach bere if count equals 10

004016 3EOO
004018
004018
00401E
004021

Section
330 2

2100FO
1l01FA
010800
EDBO

LD

A,OOh

LD
LD
LD
LDIR

HL,ET_CLK
DE,D_TIME
BC,8

:reset count value in A

;Copy current clock

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD64180 Family

Application Note
APPENDIX: Task B Code Usting (continued)
004023 0620
004025 EDOI07

LD

B,20h

;output a space

OUTO

(TDR1),B

;prior to starting ASCI ch O.

004028 0640

LD

B,40h

00402A ED0130

OUTO

(DSTAT), B

; start DMAC ch 0

exit interrupt service here
00402D DD7700

DSP_END:
INO

004030 ED38I0
004033 ED3814

INO

004036 C9

RET

(IX+O),A
;restore counter to memory
LD
:read registers to clear
A, (TCR)
interrupt request
A, (TMDRlL)

:return from task B

i*****************************

DMAC Channel 0 Initialization
for displaying elapsed time to terminal
004037 OIOIFA

DMINIT:

LD

BC,D_TIME

OUTO
OUTO

(SlIROL),C
(SAROH),B

004040 1601

LD

D,Olh

004042 ED1l22

OUTO

(SAROB),D

004045 010700

LD

BC,TDRI

004048 ED0923

OUTO

(DAROL),C

00403A ED0920
00403D ED012I

;prepare to load source addr
; source address at ET_CLK

:prepare to load dest addr

00404B ED0124

OUTO

(DAROH),B

00404E 1602

LD

D,02h

004050 ED1l25

OUTO

(DAROB),D

004053 0600

LD

B,Oh

004055 ED0127

OUTO

(BCROH),B

004058 0609
00405A ED0126

LD

B,9

OUTO

(BCROL),B

00405D 0630

LD

B,30h

00405F ED0131

OUTO

(DMODE) ,B

004062 06F4

LD

B,OF4h

004064 ED0132

OUTO

(DCNTL) ,B

004067 C9

RET

:TDREl generates request

;byte count high = 0
:byte count low
;source (mem)

= 9 chars

ines,

i/o stays

ledge sense on channel 0

;*******~********************************************. *****

000000

END

HITACHI
Hi.tachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2331

HD64180 Family

Application Note

APPENDIX: Task C Code Listing
;**********************************************************

Task C - executed upon receiving IRQ1 (external event)
Cause~

count of external events to be incremented

;**********************************************************

000000
000000

~64180. TBLN
"INTIO.LIBR

CPU
INCL

Include equates file used for Main Task
;**********************************~****************** *****

Data Storage
- System Data loaded from EPROM at initialization
OOFOOO

OR~

OFOOOh ;storage area (Common 1)

OOFOOO 30303A30303A30ET_CLK:
OOFOOA 300D

DFB
DFB

"OO:OO:OO.ON
"'ON,eR

00F800

ORG

fused by all tasks

00F800
00F803
00F804
00F816
00F82E

ODOAOA
EV_START:
30
EVNT CT:
206576656E7473
204C6173742065
30303A30303A30LAST_EV:

OF800h

;storage area X (Common 1)

;used by Task Conly
DFB CR,LF,LF
;storage for count of events
DFB
30h
DFB
\\ events occurred",CR,LF
\\ Last event occurred at ~
DFB
"OO:OO:OO.OO",CR,LF,LF
DFB

«=

9)

;**********************************************************

Task C
copy current value of real time clock to memory
increment event counter

ORG

004000
004000
004003
004006
004009
00400B
00400E
00400F
004011
004012
004014
004016
004017
004017

210BFO
1139F8
C10COO
EDB8
2103F8
34
3E39
BE
3003
3E30
77
C9

04000h

iorg at logical address

LD HL,ET_CLK+11
;end of ET_CLK string
DE,LAST_EV+11 ;end of LAST_EV string
BC,12
inumber of chars to move
LDDR
LD
INC
LD
CP
JR
LD
LD
SAV_END:
RET

;move information

HL,EVNT_CT
(HL)
A,39h
(HL)
NC,SAV_END
A,HO"
(HL),A

iincrement event count
;load '9' + 1
icompare to value in Ace
;if not equal, then return
iif equal, then reset

i***************************************************** *****

000000

Section

332

2

END

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

April,1992

Reading of a Short Data Byte from the 64180 CSIO
Tech Notes

Application Engineering

Amelia Lam

In 64180, the clock synchronous serial I/O (CSIO) port is used for fixed 8-bit data transfer in half
duplex mode. Both transmit and receive use the same Data Register (TRDR) and the same Control!
Status Register (CNTR). In the CNTR, an End flag (EF) is provided to indicate the status of an
8-bit data transfer; it is set to one if the transfer is completed, or reset to zero when data is read from
or written to the TRDR.

In some cases, the user might have a link established with data less than 8-bit. When that happens,
the data will still be available in the Data Register, and the user can read the shorter byte, e.g. 6bit, as soon as it is done. Question may arise as to what will happen to the EF bit, since this bit get
set at the end of8-bit data transfer.

In 64180, whenever a read occurs, it causes an CSIO intemal3-bit counter to be reset. This 3-bit
counter will set the EF flag after it has counted to zero and reset the flag after data is read. And
it will perform the down-counting at the next available clock. But if the read occurs right after the
6-bit transfer, the counter does not have a chance to reach zero. Because of this, the EF flag will
never get set. Hence, the user cannot rely on the CNTR for status information and has to ensure
the correct data is read with external circuitry.
EF=O
3-bit counter

> 1 11 11 11

Read

~ JLclock

~

1 11 11

TRDR

•
•
•
•

1E8

t

01

t

1 1 1

CNTR
EF=

1 01 01 01

1

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2333

June, 1992

Start Bit Detection in the 64180's ASCI
Tech Notes

Application Engineering

Amelia Lam

(Note: This technote is to replace #TN-0041, March 1992)
The ASCI detects a start bit by monitoring the low level of the receive data after the following
sequences have taken place to prevent the wrong interpretation of the noise signal as the start bit:

1. The receiver is enabled
2. On the falling edge of the serial clock (CKA)
3. a delay of 10 system clocks (q»
If a low level is detected, the ASCI will sample the RXD again at 1/2 of a bit time later; that is 8 CKA
in + 1(? mode or 32 CKA in +64 mode. The start bit will become valid if the sampling level is still
low. From this point on, the ASCI then samples the data bit at one-bit time interval, which happens
to take place in the middle of each bit. If a valid start bit is not detected, the ASCI will repeat the
search at each falling edge of the clock.

~ ~*q>

CKA
clock

~

Start bit

RXAl

)1<

bit 1

I

~rr--8-C-KA--~~r<-----16~CKA

~

)1<

16CKA

• n Is determined from 8$0.1.2 bits & PS bit of ASCI Control Register B

pata sampling in + 16 mode

The delay of 10 q> clock is determined so that the next sampling point will be aligned at the center
of the bit even in the worst case scenario with small prescale factor:
divide ratio is + 1 (SSO, SSI, SS2 = (00); prescale by 10 (PS=O); samplingcJock isCKA + 16 (DR=O)

RXA

,:
.

tt

10q>=lCKA
()(

7CKA

~.-+1--r-+-~-+~r-+-~1r-+-~--------------

~~(----~>t
8CKA

Section

HITACHI

2

Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300

334

Start Bit Detection in the 64180's ASCI

Tech Notes

Here, 10 cI> equals 1 CKA, and the 64180 actually waits after 7 CKA elapsed then perfonns the second
sampling of the start bit. With this, the total durations still equal 8 CKA. This is not so critical if
the prescale factor is higher, since 10 cI> takes a less significant weight in the entire sampling cycle.

The following flow chart highlights the detection of a start bit in an Asynchronous data transfer.

Search Start bit on falling
edge of CKA

Monitor the RXA level afte
10 system clocks

No

Sample the RXA level at
1/2 bit time later

No

Start data sampling

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

2335

March,1992

Differences Between HD64180S and HD64180S2
Tech Notes

Application Engineering

Amelia Lam

The new product marking for the NPU is HD64180S2. It is the same as HD64180S except with the
following differences :

HJl!!~UUlS
1. Condition - Bit synchronous
Loop Mode

HD!'i~UU1Sl

Cannot be used

Can be used

The user is required to
generate an "enter search
mode" command

An "enter search mode"
command is automatically
issued by the MSCI. No
software intervention

The closing flag sent by
the transmitter becomes
seven l's. The receiver
thus interprets this as an
Abort sequence and
results in the wrong
frame.

The MSCI will correctly
transmit the closing flag
even if the last data byte is
between FO - F7H.

2. Condition - Bit or Byte
synchronous FM encoding
(FMO, FMl, Manchester)

-

When the continous frames
received by the MSCI are out
of phase, the synchronization
can be done by the ADPLL if
an "enter search mode"
command is generated in
between the idle state of each
frame

3. Condition - Bit synchronous
HDLC or Loop mode

-

If an FCS is not included in the

transmit frame, and the last data
immediately before the closing
flag is in the range of FO - F7H
(i.e. the bit sequence right
before the flag is seen as
xxxOllll)

iT
IT

........

in 64180S

FF ............
FF

I

last byte
xxx0111

~

Flag
011 1 111

~

JJ.
I

last byte
. xxx01 1 1

~ Flag
~
11111 11 ,
=::;:;=

Abort sequenc

Section

HITACHI

2

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

336

March,1992

Start Bit Detection in the 64180's ASCI
Tech Notes

Application Engineering

Amelia Lam

The ASCI detects a start bit by monitoring the
low level of the receive data after the following
sequences have taken place:

noise signal as the start bit.
If a low level is detected, the ASCI will sample
the RXD again at 112 of a bit time later; that is 8
CKA in +16 mode or32CKAin +64 mode. The
1. The receiver is enabled
start bit will become valid if the sampling level is
2. On the falling edge of the serial clock still low. From this point on, the ASCI then
(CKA)
samples the data bit at one-bit time interval,
3. a delay of 10 system clocks (1<

bit 2 :

16CKA

Data sampling in + 16 mode

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Section

2

337

Tech Notes

Start Bit Detection in the 64180's ASCI

The following flow chart highlights the detection of a start bit in an Asynchronous data transfer.

Search Start bit on falling
edge of CKA

Monitor the RXe level after
10 system clocks

No

Sample the RXe level at
1/2 bit time later

No

Start data sampling

Section
338 2

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November, 1990

HD64180 Family-DCDO Line Operation
Tech Notes

Application Engineering

Mamie Mar

Hardware Manual Supplement
When 64180 designs using ASCI channel 0 require DCDO to be active, users should be aware of the
following if receive interrupts are enabled.
A receive interrupt will be generated whenever receive interrupts are enabled and the ASCI detects
a low to high transrnition of the DCDO bit of Status Register 0 (STATO). This bit transition will occur
if either the external DCDO input line transitions from low to high, or if the DCDO bit of STATO is
cleared by reading STATO, but the external DCDO line remains high. The DCDO bit will be cleared
by the STATO read, but the bit will be reset as soon as the external DCDO line is detected high.
If the external DCDO line is to be held high in an application, recieve interrupts should be disabled
by clearing the RIB bit of STATO. Otherwise, receive interrupts will be requested continuously until

the external DCDO line is set low.

ASCI Status Register 0 (STATO : 1/0 Addres
bit

7

R

6

R

5

R

4

= 04H

320

IDCDfTDR~

FE

RIE

R

RIW

R

R

TIE

I

RIW

R: read only
RIW: read and write

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Section
2339

August, 1990

64180 DMAC: Memory-Mapped 1/0 Transfers
Tech Notes

Application Engineering
A fixed memory location can be specified as the source or destination for a DMAC channel 0 transfer
on the HD64180R, Z and HD647180X. When this occurs, the DMAC assumes that the fixed address
is a register in an external memory-mapped I/O device which is capable of generating an external
hardware request signal to be input on the DREOo pin. Once the channel has been initialized and
enabled, transfers will occur as requested by the DREOo input which can be programmed to be edge
or level sensitive.
If the user's system does not have the capability of providing a DREOo input to trigger transfers to
or from this location, transfers can be triggered by program control. In order for this to happen,
program DREOo to be level sensitive (set the DMSO bit of the DCNTL register to 0) and tie the
DREOo pin low. This will cause DMA transfers to occur in burst mode whenever channel 0 is
enabled (by writing 1 and 0 to the DSTAT register's DMEO and DWEO bits, respectively).

Note on tying the DREQopin low: Since the DREOoline is multiplexed with the CKAo input/output
line, the user must not enable the ASCIO baud rate generator prior to initializing DMAC channel 0
for memory-mapped I/O transfers. Initializing the system in this order would cause the CKAo line
to output the baud clock, and this pin in the output state should not be tied low.

Section

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340

June, 1990

Notes on HD64180S (NPU) Bit-Sync Loop Mode
Tech Notes

Application Engineering

Mamie Mar

Abnormal transmission of data in seeondary stations
ThefollowiDgpobJem may befouad whea usiDg die HD64180S NetworkPlOc:essiDg UDit(NPU). The MuJ.Iiprotac:ol
Serial Commonic:a&ions In1e:rfaco (MSCl) of tbis deYico may on& operae CGmICtly when it is used in die Bit
SynduoDous Loop Modo in IUppCIrl of IICICOOday sI8tiona for bit syacIaoaoaa loap II'IDsmi'lim of daIa. Por deIIIils
011 die conect opcadoD of die Bit-Syachronous Loop Modo, please Iefer 10 the HD64180S NPU Hanlware ~
#KJ16.
The MSCI operaIiDg in tbis modo may traDsmit eta abIIormaIly wIleD die Go acdve On Poll (ooP) bitoftbo MSCI
ConuolRegisrer (MCIL) is cbaapclfrom 0 10 1. If ~ couecdy, eta """""iajon woaklDOl beBiD UDIil boIh
tboGOP bit is c:haapcl1O 1 _ a Go Ahead (GA) paaem bas been detecIec1. Pigam 1 sbows Ibis iDconectopcnlion.

'TXDM
GOP.1 ....0
I1pre L FaUun III data tnnsm.... 1Il allClllldlr)' Radon

Warning on mjnr tho GOP bit

The GOP bit IbauId bo chaagecl from 0 10 1 only during die TXdisabIe . . . illJmediatfty after bardWIR nut. AffIJt
dial, wridDglO tbo GOP bit sboulcl be avoided in die application software.

Pigme 2 sbows a ponionofdle Stale TraDsitioo DiagIam forTnnsmission iii Bit SyucbloDous Loop Mode. Toawicl
abnormal tmnsmiaion of daIa. die GOP bit sbouId DOVel' be wriaaa by appJicaIion soflwaJe after it bu been
jnjriaHzarion 10 ·~I". Tbaefore. GOP remaias in tbo "I" Stale daring apntion. To cause tmnsition from 1bo Idle
state 10 die Retransmit Idle Stale without wridngWO· 10 the GOP bit zequiIes die followiDg steps:

1) Issuing die "TX Reset" COIDIII8IId in die Idle . . . causes tnmsition to the TX Disable state
2) Issuing the "TX Enable" command in die TX disable Stale causes 1I8DSition 10 die R.elraDsmit Idle stale

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Section
2 341

Tech Notes

Notes on HD64180S (NPU) Bit-Sync Loop Mode

"TX ..... -lIaatd and
"Channel ....... 1Autd
front all It....
"TX tnIbIe-lllUed

~ dIsabIe-lsIuad
Initial ..."
after .....

eep·'•

..-J Transitions not

Data In ttanamlt buff.r,
CiA patt.rn rtOtptlon
and GOP • .,-

.

used due

to GOP

operation problem
Idle stat.

Data In transmit buffer

and GOP.·'-

Figure 2. State tnnsitlon
Countermeasure by software
Figure 3 shows the results of the countenneasure for the loop mode operation problem in software:

I

Idle state

TX dllable atate

"'-111

TXOMJ'..:.'7.:;:;EH".;...;;.;trana;;.;;.;.m;.;;;It~I-·.;.F;..;.FH".;...;;.;trIn;;.;;.;..mIt;.;.;,;.....,
#
MIOL • "7EH"
MIDL - -FFH"
Data tranarrit end In

Retransmllch state

TX.nabI.
command lllUed

a eecondary atatlon
Change to
MIDL.·FFH"

I

"'-111

Ch.ngeto
MIDL."7EH·

TXrtHt
command Ia1ued

Flaure 3. Example
Notes:
1) The MSCI Idle pattern register (MIDL) is programmed to FFh from 7Eh during the Idle state to cause the change
from flag ttansmit to mark transmiL
2) The TXDMoutput pin is in mark state during theTXDisable state,which is the same as it would be if direct transition
to Retransmit Idle state occurred.
3) When the GA pattern is detected, a secondary station transitions to the Idle state even though it does not have
transmit data (refer to Figure 2). When this occurs, the above operation needs to be repeated to return to the retransmit
idle state, since writing "0" to the GOP bit could cause problems.
Section
342 2

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Notes on HD64180S (NPU) Bit-Sync Loop Mode

Tech Notes

• Seco"!fltv station Inlllllzallon
• GOP ......,.
• MIDL +- "7EH-

TX dlllbit Itlt.

Retranlmlt
IdIo ItItt

Secondary
I1IIlon
data transmit

Idlaltltt

Idle stalt

lXdl8abl.
It&t.

FJpre 4. State transition control Dow at bit iynchronousloop mod.
HITACHI
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Section
2 343

Notes on HD64180S (NPU) Bit-Sync Loop Mode

Tech Notes

FlowChart
Figure 4 shows the flow chart of the transmit operation in Bit Synchronous Loop Mode using the recommended
software countermeasure.
Notes:
1) Condition branches in the flow chart occur as a result of interrupts, or by CPU polling.
2) Operation shown in the box marked A replaces writing "0" to the GOP bit
3) The GOP bit is always"1 " , so a secondary station transitions to an Idle State when the GA pattern is detected in
the Retransmit Idle State whether or not transmit data is available. When this occurs, operation should return to the
Retransmit Idle State by clearing the Go Ahead Pattern Detect (GAPD) bit of MSCI Status Register I (MSTl).

Section

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344

December, 1989

Port A Register Programming
Tech Notes

Application Engineering

Mamie Mar

Writing to the DERA (port A Disable Register) can affect the values programmed into the DDRA
(Data Direction Register A). For instance, if the DDRA is programmed to set up directions for the
I/O port pins, and the DERA register is later programmed with a value, it is possible for the DDRA
value to change causing the data directions for the I/O pins to change.
To ensure that the directions of I/O pins are preserved, the following steps should be taken:

1. DERA should be programmed prior to programming the DDRA.
2. If the DERA is reprogrammed, the DDRA should also be reprogrammed.

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Section

2345

Section
346 2

HITACHI
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Section

3
4-Bit
Family

HITACHI®

2

Section

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February, 1992

Effect ofTMA2 on Timer A Operation
Tech Notes

Application Engineering

Amelia Lam

In the Compact 400 series, Timer A can be configured by mask option in two operation modes, namely
Free-running timer or Watchdog timer. According to the databook, bit 3 of the Timer Mode Register
A (TMA) is used for "TCA initialization for watchdog timer". This technote is to explain the usage
of this bit 3 in watchdog mode, and the additional feature it provides in free-running mode.

Timer Mode Register (fMA)
This is a 4-bit write-only register. The prescaled input clock to Timer A is determined from bitO
to bit2, and bit 3 is for resetting the counter TCA.

Input clock selection for free-running timer
(1/2,1/4,1/8,1/32,1/123,1/512,1/1024,1/2048)
TCA initialization for watchdog timer

Watchdog Timer
In the watchdog timer mode, Timer A counts up on every 1/2048 of the system clock signal and.
generates an overflow when the counter reaches FF, causing the MCU to reset at the same time.
Therefore, TMA3 is used to reset the counter before the overflow situation occurs .
. .TCA=FF

TMA3 is set to 1- -~

.

.

- - . TCA=OO

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Section

3

3

Effect of TMA2 on Timer A Operation

Tech Notes

Free-running Timer
In the free-running timer mode, Timer A counts up on the clock signal selected by the TMA register.
As soon as the counter reaches FF, it generates an overflow and sets the interrupt request flag. Timer
A is then reloaded with 00 and starts counting again. But if TMA3 is set, the counter will get reset
before it has the chance to reach FF, thus defeats the purpose of Timer A serving as a free-running
timer. The databook refers this phenomenon as "the MCU malfunction". In fact, it is the timer,
not the MCU, that is being referred.. The real issue is the counter does not function as expected in
the free-running timer mode. On the contrary, setting this bit 3 provides an additional feature, an
event counter for Timer A in the free-running mode.
__TCA-FF

TCA-OO

4

Section

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January, 1992

4-Bit ZTAT Microcomputer PROM Programming
Tech Notes

Application Engineering

Amelia Lam

The on-chip PROM of the HMCS400 ZTAT microcontrollers is programmed in the same way as a
standard 27256 EPROM does. Since each instruction of the HMCS400 is 10 bits wide, a special
programming sequence is employed in order to properly convert a 10-bit program code onto 'an 8bit memory locations.
However, there may be times when the PROM programmer reports a device or programming error
even there isn't one. This may be caused by some of the records in the object file not having the entire
memory space occupied with data. After the object file is downloaded into the PROM programmer,
those unoccupied areas are then filled with data of '00' byte. This violates the HMCS400
programming specification which requires the upper three bits of each byte be '111 '.
The following text illustrates a method to circumvent this problem.

ZTAT Vs 27256 EPROM Code Assemblying
By using the Cross-Assembler, the lO-bitinstruction source code will be transformed into an 8-bit
object file ready for downloading. This is done by splitting lO-bit word into two halves and each
half is padded with' 111' in the most significant three bits to form a byte.

If an 8-bit EPROM is used for programming, the command is:
"ASSEMBLE filename "
this will create two 8-bit wide files to be burned into two EPROMs; one contains all the even address
code, and the other one contains all the odd address code.

nK

EPROM

EPROM

nKx 8

nKx 8

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Section

3

5

Tech Notes.

4-Bit ZTAT Microcomputer PROM Programming

If the ZTAT is used for programming, the command is:
"ASSEMBLE filename /P"
this will generate an object file 'xxx.P' which contains both odd and even addresses interleaving with
each other.
3 bits

5 bits

2nK <
111
111
111
111

XXXPfile

Downloading
Wh~n

using a menu-driven software such as "PROMLINK" for downloading, fIrst fill the
programmer RAM space with FF prior to loading with the object code. This ensures all ones in
the most significant three bits on each byte even after 00 is loaded to the RAM.

PROM Programming
Adjust the operation boundaries by setting the device block size to the code size. Instead of
programming the entire ROM which the ZTAT part comprises, it only program the selected ROM
space. By doing this, it adds efficiency in the burning process.

Alternative
Besides filling the programmer RAM withFF, an alternative to eliminate the gap between each record
is to pad the source code with FF so that the starting address to the ending address of a whole record
will have data in it.

6

Section

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May, 1990

HD404272 User Cable Conversion Board SWI Pin Layout
Tech Notes

Application Engineering

Amelia Lam

HS4274ECS28H is a User System Interface Cable connecting to a general-purpose target probe
(HS400ETAOIH). Itis used specifically forthe high-voltage I/O Compact device HD404272 family.
The unit includes a conversion board with header plugged into the target probe, one set of flexible
ribbon cables with 28-pin shrink DIP connector plus protection socket, a power supply cable and a
spare protection socket (No.3).
Rather than software programmable, the high-voltage pins on this user cable must be fixed to either
input or output. The way to do this is by means of the on-board switches (SWI, SW3 & SW4).
However, there is a mismatch in the SWI switch layouts between the schematic and the board itself.
On the schematic of the HS4274ECS28H user's manual, the SWI pinouts are connected to the
databus as follows:

DO~

D1~
D2~
D3~
D4~

D1~
D1~
SW1

The correct settings should be the one showing on the board:

D1~

'D12~

D4~
D3~
D2~
D1~
DO~
SWt

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Section

3

7

HITACHI
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,

Section

4
Display Devices
• Graphics
• LCD

HITACHIQl)

2

Section

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Section

4
Display Devices
Graphics

HITACHI@

/

/

Section

4

4

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March,1992

HD63484 ACRTC AND HD63487 MIVAC Data
Tech Notes

Application Engineering

Kash Yajnik

Q / A, Test, and Reliability Information
The most frequently requested Q/ A, test, and reliability data by the Hitachi customers using the parts
listed above, is summarized below;
1.0

ACRTC (HD63484) - Transistor Count = 117,000

2.0

MTBF
o

HD63484 (ALL Packages) = 3.8 xlO 6 Hours at T A = 55 oc, and
Confidence Level = 60%

o

HD63487 (ALL Packages) = 3.4 xlO 6 Hours at T A = 55 oc, and

II

Confidence Level = 60%
3.0

ACRTC (HD63484) - Junction to Case Thermal Resistance
PRODUCT

PACKAGE

COMMENT

e J.e

HD63484P8

DP-64

Plastic DIP

75 ocl W

HD63484-8

DC-64

Ceramic DIP

35 ocl W

HD63484CP8

CP-68

PLCC

45 OCt W

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Section

4

5

HD63484 and HD63487 MIVAC Data

Tech Notes
4.0

ACRTC (HD63484)- Power Consumption Vs Speed
SPEED

6

fcc (Max)

@

Vee = +5V ± 5 %

9.8MHz

120mA

8 MHz

100mA

6 MHz

80mA

4 MHz

60mA

Section

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November, 1991

HD63484 ACRTC
Tech Notes

Application Engineering
PRODUcr :

Kash Yajnik

ACRTC

HD63484

Mask History

The details of limitations on the usage of the "R", "S", and "un mask are shown below
along with the product mask diagram for identifying different masks.

•

HD83484 ACRTC UmlatloM an U.....

The status of lhe item numben described in lhis par&8J'8ph is summarized in the followinl
table.

LimiIldiOD on &he ACRTC function.
No.
1

2
3
4

II

e
7
8

•

LImIIaIion far 1M Ac::RTC funcIIan

L/gIIt .... ....,..
AS 8IgnoI UIng DMA T_ _

/lIMA MoIM far AFRCT. RFRCT .a PAINT CornrnMda
DAD ConvIwId
DMCIO Camrn.nd
PAUSE iii

'""*"

AS Output
UIng ZomnkIg
8LNC "-lIn
CUI. WT _ fNIT Command

R MIIIk

SMMk

u.-..

u....
u....
u.-.

UIIuNb1e
UIIuNb1e
UnuIIbIe
UnuIIbIe
UnuIIbIe
UnuIIbIe
UnuMbIe

Un_

UnuubIe
Un_

UIIIbIIt
UMble

UubIe

u....
UubIe
UubIe
UnuIIbIe

u.-.
u.-.
UubIe
UubIe
UubIe
UubIe

u.-.
UubIe
UubIe

10

WriItna '" ReQiIt8n during DAD c-end ExecUlion

11
12

TIne UIing 1M PAINT Comm_

Un_bIe

u....

13

DIIIpIeying WWDOW

Unu.eble

UnuIIbIe

u.-.
u.-.

14
111

PARAMETERs for aLPSE c:omm.nd
PARAMETEIIIlor ELLPSE ARC Camrn.nd

UnuaebIe

UnuubIe

Un.....

Un.....

UnuIIbIe

UnuIIbIII

Ie

UghI .... SlnIbe DMect

UnuHIIIe

lJnuNtIIe

UubIe

~DMAT""'..

MoIM

IU'DI . . . BI1

R: IndIcetII R mule ".,.,.

LatNllmber

~

\ .•

C~84

UnuubIe

;E

UMMk
U....
U....

R

r-

s: IncIicatII S INIIk ".,.,.
U: indica. . U meek ".,.,.

R IndlCltll R mo'" "",ion

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Section

4

7

July. 1991

EV63487
Thchnical Brief

MIVAC Evaluation Board

Kash Yajnik

The EV63487 MIVAC Evaluation Board was designed by
Hitachi Europe Ltd.. Munich, Gennany, and can be ordered
through Hitachi America Ltd. in U.S.A. The board is shipped
in a foil cover with a User Manual,and the associated software
diskette capable of demonstrating graphics patterns on a 6.3"
or 10.4" TFT color Liquid Crystal Module from Hitachi.
Up to eight colors may be displayed depending upon the
selected LCD panel from Hitachi's ELT Division. The
EV63487 MIVAC Evaluation Board can reside inside IBM
PC-AT or a compatible system running later than DOS
version 2.0. It is also possible to run the EV63487 Board with
an external power supply. This board takes one slot in the
chasis and its size is half that of the standard card. The back
light power is also supplied by this card. Identical color
. images can be displayed on the CRT monitor as well as the
color LCD panels.
The EV66387 Evaluation board uses Hitachi's Advanced
CRT Controller (ACRTC) HD63484, andMemory Interface
Video Attribute Controller (MIVAC) HD63487. This board
has no LCD controller part as the CRT data is serially sent to
the color panel for display.

This technical brief is written to complement the EV63487
User's Guide for one specific application using the 6.3" color
TFT module (TM16DOIHC) from Hitachi's Electron Tube
Division (ELT). A coPy of the schematic is also included to
provide the design implementation detail. A system diagram
is also included to high light the laboratory environmenL
Similarly, each user may tailor display subsystem requirements for the desired application.
The scope of this document is to help make the design task
easier and quicker. The circuit minimization tasks are left to
each user and are not attempted. This is intended as an
iIIustriltive example for the Hitachi field and technical staff.
and their customers.
The following pages cover system configuration and componenents, EV63487 Board set up, System debug, and Demonstration software. The Appendix "A" covers LCD cable and
the Appendix "B" shows the Back light power connections.
The Appendix "c" lists the· schematic.
Refer to the subsequent pages for more detail.
I

Section

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8 .

EV63487

Technical Brief

SYSTEM CONFIGURATION

The development system was configured with IBM PC-AT or compatible machine, Paradise Autoswitch EGA
480 card, EV63487 MIVACEvaluation Board, Smartscan Amdek735 digital color monitors, and Hitachi 1Ff
active matrix, 8 color, 6.3" LCD display (TMl6DOIHC) from the ELT division. The 9 pin TTL video cables
required to provide CRT video signals from the EV63487 Evaluation board or the Paradise video board are
not provided. The MIVAC Evaluation board output connector cable to the 6.3" 1Ff display is shielded to
increase noise immunity and to make the LCD display connection task easier. A separate +12V DC c~ble is
also required for the back light option (#BLS-006M). The back light is easily mounted with the four corner
screws of the 6.3" 1Ff display.
The system diagram is shown below:
EV63487
MIVAC
EVALUATION

PARADISE
CRT

AMOEK

CONTROLLER

SMARlSCAN

BOARD

TTL

AMDEK

SMARlSCAN

736
"C2"

TTL

• C1•

6.3· T FT

BACK UGHT

DISPlAY

OPTION

"C4"
"C3"

NOTE;

1.0 "Cl " =" C2 " = "C3" = "C4" cables are not provided.

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Section

4

9

EV63487

Technical Brief

SYSTEM COMPONENTS
The hardware components are described in this section while the " C3 "," C4", cable wiring diagrams and
schematic are shown in the Appendices.
PC.AT: AST Premium 286 model 70 was operating at 10 MHZ, with 512KB memory, 20MB hard disk drive,
and 1.2 MB, 5.25 " floppy drive. It was also running DOS version 3.2.
VIDEO CONTROLLER: It provides the video signals to the Amdek monitor # lover the cable" CI".
Paradise Autoswitch EGA is card used in the CGA mode at (640H x 200V) resolution to generate the TTL
level signals to the monitor. The switch settings for 80 column, RGB monitorin CGA mode are shown below
in its diagram:

POS.

- -- - -6

5

4

3

2

1

OFF

ON

NOTE: 1.0 For more details refer to the Paradise CRT controller manual.
2.0 Make sure this switch is. correctly set.

EV63487 MIVAC EVALUATION BOARD
This board has no switches and its settings are built in. So, please referto the EV66841 User's Guide for details.
Only the 6.3" TFT LCD display was used, eventhough the manual describes the 10.3" display.
The EV63487 board provides TfL level output signals1carried by the 9 pin cable" C2 " to the the video monitor
Amdek # 2. The R,G,B, HSYN:C, and VSYNC signals are included in that cable. The output signals are also
sent over the 34 pin cable" C3" to the 6.3" TFT, 8 colors, Hitachi display. This board also supplies +12 Volts
required by the back light through the·cable " C4 ".

10

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EV63487

Technical Brief

HITACHI COLOR LCD TIT MODULE (TM16DOIHC) :
Refer to the display data sheet for detail. The page 14 of it shows how the sub-pixels are designated for LVIC
HD66841 interface with 160 dots (H) and 200 dots (V) resolution. The cable" C3 " provides the signals to
the display while cable" C4 " provides the back light power. The display tilt and swivel angles provide different
contrast ratios in the ambient light, so it should be adjusted for the most desirable viewing angle.
AMDEK MONITORS
The two CRT color monitors #1 and #2 are used in the CGA mode. They show the DOS commands dialogue
on monitor #1 while the monitor #2 displays the demonstration program output. Observe that the monitor #2
and the 6.3" 1Ff display show identical color images in the 640H x 200V mode.
SYSTEM DEBUG
First power up the system in CGA mode using the AMDEK color monitor #1 and the EGA board. Only the
cable "Cl" is plugged while the cables "C2", "C3", and "C4" are not connected effectively disconnecting the
6.3" TFT LCD display. After the system is up in the CGA mode, with a DOS prompt, verify that it works
correctly. Then reconnect the EV63487 board cables "C2", "C3", and "C4". Also, verify that the cable "C2"
is properly connected to the display, since there is no key in the connector. If the cable "C4" is properly
connected, back florescent light should come on and it is clearly visible.
If every thing is working correctly, one can execute all the DOS commands when appropriate prompts are
displayed on the CRT monitor #1 screen.
DEMONSTRATION SOFTWARE
After DOS 3.2 or later is installed, load the programs from the software diskette after creaqng MIV AC and
SOURCE directories. Modify the AUTOEXEC.BAT file to run file INI20-32.EXE to initialize the ACRTC
(HD63484) and the MIVAC (HD63487) from Hitachi. After the initialization program is run, execute the
DEM0200.EXE program to show identical graphic images on the color 6.3" LCD panel as well as the video
monitor #2.
The AUTOEKaC.BAT file sample is shown below:
PATII = C:\;C:\DOS;
SET PROMPT = $P$G

CLS
C:\MIV Ao.EV63487\lNI-32.EXE
ECHO HIT RElURN FOR TFT DEMO
ECHO OTHERWISE TYPE "C

HITACHI
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Section

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11

EV63487

Technical Brief

DEMONSTRATION SOFfWARE (eNTD.)
PAUSE
C:\MIVAC\EV63487\DEM0200.EXE
The DEM0200.EXE program screen output on the DOS monitor #1 is described below:
1.0 1000 Random filled circles
2.0 1000 Random filled rectangles
3.0 1000 Random rectangles
4.0 Lines
5.0 Color bars
6.0 16 filled ellipses
7.0 Logo
The corresponding images should be displayed on the 6.3" TFf color LCD display as the demonstration
program is executed in the ffiM PC-AT or compatible machine.

Section

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EV63487

Technical Brief

APPENDIX " A "
The 34 pin LCD shielded cable" C3 " is shown below:

II'-JE~V~63487~~B~D~_ _ _ _ _--"'----------1(_

TMl6DOlHC
TIT DISPLAY

)
_

"C3"

VEE (-20V)

Pin 1

VOOA (+SV)

Pin 3
PinS
Pin 7
Pin 9
Pin 11
Pin 13

NC
IMO(+SV)
IMl(G)
DOTE
VSYNC
HSYNC
DTMG

PinlS
Pin 17
Pin 19

G
G
G
G
G

Pin 22
Pin 13
Pin2S
Pin 27

G

Pin 29

G

Pin 31

G

Pin 33

•• ••
•• ••
• •.•• •
••
•• ••
•• •
•
•• •
•
••
• •
••

Pin 2
Pin 4
Pin 6
Pin 8
Pin 10
Pin 12
Pin 14
Pin 16
Pin 18
Pin 20
Pin 22
Pin 24
Pin 26

VEE (-lOV)
VDOA (+SV)
Voo (+SV)
VDD (+SV)
VDO (+SV)
G
G

il]

G
G
G
GRN

Pin 28
Pin 30

G
RED
G
BLU

Pin 32

DCLK

Pin 34

LCLK

HITACHI
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EV63487

Technical Brief
APPENDIX " B "

Back light power cable C4
II

II ,

II

Cl ", and C2 are shown in this Appendix :
II

II

EV63487 MIVAC EVAL BOARD
6.3" TFT COLOR DISPLAY

DC-DC CIRCUIT

,

Ii:iJ
GND

BLJ(

RED
" C4"

NOTE: Back light power is to be externally supplied through the II C4 II cable.

" Cl " AND " C2 " CABLES:

They are atached to the two monitors and are provided by Amdek, the manufacturer.

14

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I

EV63487

Technical Brief

APPENDIX

It

C

It

This section shows a copy of the schematic supplied by Hitachi Europe Ltd .• Munich. Gennany. It is inluded
for reference and completeness.

DC.pC conycrter;
+ 12 V ar-IBM PC ilia)

ii

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MAX63o&

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l

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I

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L8R

ex

• 7PF

i~ CJO

V
IV

,.v.
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:-07S~
I~ O.I~F

~

VLCD

20 V

~
INI1I7

~~

$

100CIIlF/ISV

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I

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CJO

..

HITACHI
Hitachi America,.Ltd. 0 San Francisco Center 0 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0(415) 589-8300

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EV63487

Technical Brief

APPENDIX "C"
This section shows a copy of the schematic supplied by Hitachi Europe Ltd., Munich, Germany. It is merely
included for reference and completeness.

!!f=!l

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EV63487

MIV AC Evaluation Board
This document presents infonnation for a 6.3" or 10.4" color active matrix LCD subsystem implementation using Hie" :hi semi
conductor products ACRTC ,HD63484 and MIVAC HD63487. Its major components include IBM PC-AT. EV63487 MIVAC
Evaluation Board. Paradise Video Concroller Board. and the color LCD display ( TMI6DOIHC) from Hitachi's ELT Division. It
can be further enhanced by adding demonsaation software that runs on the IBM PC-AT or a compatible machine.

•

FEATURES

--Hardware-(1) IBM PC-AT or compatible machine

(2) EV63487 MlVAC Evaluation Board from Hitachi Europe in Germany.
(3) Color LCD 6.3" Active Matrix display from Hitachi with Back Light option
(4) Paradise Video Concroller Board
·-Software-(1) OOS 3.2 Version or later

(2) ACRTC and MlVAC Inilialization programs
(3) Source code for the programs in " C " or BASIC
(4) Demonsaation programs for 6.3" or 10.4" 'IFI' active maaix color LCD display

•
~fIIIIAD' • •
CORT
CO.. ,.."'OL. .... ..-

TTL.

.. c::

.. 0 2 "
1

..

• . . . . T,.T

o . . ~v
.. c s ..

•

OBJECTIVES

(1) To display EV63487 MlVAC Evaluation Board
. (2) To demonsaate 6.3" color active malrix display
(3) To show demoastration software running on the EV63487 MlVAC Evaluation Board
(4) To high light PC-AT bus interface

•

ADDmONAL INFORMATION

The details oflhe SYSlem configuration and its deaign along with the associated software.are available intheHitachl
America Lid. Technical Brief #TBOI01.

HITACHI
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18

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Section

4
Display Devices
LCD

HITACHI@
-

~-------------

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March, 1992

8D44780 / LCD PANEL
Design Thtorial

HS/325 Application Note

Kash Yajnik

OVERVIEW

This tutorial is written to complement the H8/325 micro
processor literature and also iUustrate the HD44 780 development for one specific application i.e. interfacing to a
selected number of LCD panels from Hitachi's ELT Division.
A copy of the schematic and software listing is included to
provide the design implementation detail. A system diagram
is also included to high light the laboratory environment.
Similarly, each user may tailor requirements for the desired
application.
The scope of this document is to help make the customizing
task easier and quicker. The circuit minimization tasks areleft
to each user and are not attempted. This is intended as an
illustrative example for the Hitachi field and technical staff,
and theircustomers.The H8/325 Series Model-I ASE (Adaptive System Evaluator) was designed by Hitachi Ltd., Tokyo,
Japan, and can be ordered through Hitachi America Ltd., in
U.S.A. The associated Emulator Box (HS328ABXOIH) for
H8/325 microprocessor based product development was used
to send digital information. A HD44780 LCD Controller
Driver located on the Hitachi panel from Electorn Tube (ELT)
Division, Chicago, lllinois, processed the displayed message.
Black and white character information can be shown on
selected LCD panels from Hitachi's ELT Division. Among
the many products offered by the Hitachi's ELT Division, for
this application, LCD panels LMOI6XML, LMOI6L,

LM04IL, LM044L, and LM054 were selected and tested.
An Emulator Inter connect Board is required to enable the H81
325 ASE to talk to the LCD display panels. The character data
is sent to the LCD panel for processing as well as display. The
HD44780 LCD Controller Driver from Hitachi, SICD, located on the panel, processes the data sent by the H8/325
development system for display.
The H8/325 Emulator Interconnect Board resides on a bench
connected to a LCD panel. The other end of the board is
connected to the H8/325 Emulator User probe. Italsorequires
external power supply. After power on, a demonstration
program is loaded in the ASE system. It is then run to display
a character message.
The following pages cover system configuration and compo- z
nents, H8/325 ASE Development System, Hardware Design, ~wt=CIJ
Software, and Demonstration Program. The Appendix" A "
covers H8/325 ASE system details, and the Appendix" B "
shows the Emulator Interconnect Board schematic. Also,
Appendix" C " lists the LCD Panel data sheets, and Appendix
" D " shows the H8/325 Initialization software listing. The
appendices" E ",and" F" show HD44780 code listing and the
reference literature respectively.
Refer to the subsequent pages for more detail.

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HD44780 / LCD PANEL

Application Note

TABLE OF CONTENTS

TOPICS

PAGE

1.0

INlRODUCTION .....................................................................................................................................

23

2.0

SYSTEM COMPONENTS ........................................................................................................................

24

3.0

HARDWARE DESIGN .............................................................................................................................

25

4.0

HD447S0 INITIALIZATION FLOW CHART ...........................................................................................

27

5.0

HD447S0 DATA TRANSFER FLOW CHART .........................................................................................

29

6.0

APPENDICES ...........................................................................................................................................

31

22

APPENDIX

"A"

HS/325 ASE SYSTEM .....................................................................................

32

APPENDIX

"D"

EMULATOR INTERCONNECT BOARD .......................................................

34

APPENDIX

"CO

LCD PANELS FEATURE LIST .......................................................................

35

APPENDIX

"0"

HS/325 INITIALIZATION CODE LISTING ....................................................

40

APPENDIX

"E"

"INTIT7S0B.ABS" PROGRAM LISTING ........................................................

41

APPENDIX

"F"

REFERENCE LITERATURE ..........................................................................

45

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HD44780 / LCD PANEL

Application Note

INTRODUCTION:
This section describes the design goals and provides a
general overview of this presentation, along with a software
development listing.

To use Hitachi H8/325 Emulator and User probe.
To use readily available software at Hitachi Field
Offices for development.
To generate HD44780 / LCD Panel Tutorial.

o
o
o

The design goals established for this project are briefly
listed below:
o
o
o
o
o

To use H8/325 ASE system with software.
To display with LM016XML, LM016L, LM041L,
LM044L, and LM054 panels from Hitachi.
To display four data bytes in the character mode
using HD44780.
To design Emulator Interconnect Board.
To write programs for debug and test.

A brief description of the LCD display system components
listed above is provided in the next section as an overview.
To complete the overview, a system block diagram is also
presented. The rest of the sections described in the Table
Of Contents are expanded in greater details along with their
programming data. The Appendices give additional
information, the program listing, and also list the referenced
literature. A copy of the Emulator Interconnect Board
schematic is also provided to illustrate the implementation
details of this application.

-SYSTEM CONFIGURATION
The display system was configured with H8/325 ASE Unit,
Emulator Box, User cable, and a variety of LCD panels from
theELT Division, along with an Emulator Interconnect Board.
The required cable lengths are shown in the schematic for
CMOS signallevels. The LCD power pins are apart of the 14
HS/S25

pin panel cable, so a separate power cable is not required.
The system block diagram for the Emulator Interconnect
Board is shown in the Appendix" B ". The system block
diagram is shown below in Figure 1:

ASE SYSTEM

HITACHI
HBj326

ASE
COMPUTER

EMULATOR
INTERCONNECT

BOARD

64

DIP

HITACHI

LCD

H8~26

NOTE:

PANEL

FIGURE 1

1.0 The required ASE and Emulator cables are provided by
Hitachi Ltd.

2.0 The Emulator IntercconnectBoard power and panel cables
are built from the available documentation.

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t5
~f=UJ
w

E
•'

HD44780 / LCD PANEL
SYSTEM COMPONENTS

Application Note
Emulator Interconnect Board: A wire wrap board

was built to send parallel data, control signals, and power to the
LCD panel over the "LI" cable. The 64 pin male DIP User
Cable was connected to the DIP socket on the Emulator
Interconnect Board. The LCD panel contrast adjust potentiometer was also put on this board. The data bus and gating
logiC were also located. Thepoweronresetpu!sewasprovided
88/325 ASE Unit: ThisproductwasdesignedbyHitachi by the H8/325 Emulator unit. Refer to the Appendix" B " for
Ltd.,Tokyo,lapan. It is used as a demonstration and develop- its schematic.
menttool. Refer to the Appendix " A" for its features and other
details including a picture. The system software allows line Power Supply: Open frame switcher power supply from
assembly, disassembly, editing, trace, break setting, and other K'tPCo, Model # ECM-02IK-CB was used to power up the
debug facility.
Emulator Interconnect Board as well as the display panel. Its
It is used in transparent mode and the host port is connected to rating was +5V@ 2A. +12V @0.3A,and-12V @ 0.2A. Note
a VAX computer. The CRT port is connected to DEC VT320 that the Emulatoralso sources poweras shown in the schematic
terminal. The Motorola S record compatible programs are in Appendix" B
loaded by 1.2 MB, 5 1/4" diskette. They are run to develop the
code and associated demonstration software. The ASE is run Software: The H8/325 ASE system and PC resident
at the emulation clock speed of 7.3 MHz and H8/325 mode 2 software development tools, packages, and utilities are deoperation. The development system comes with ASE system scribed very briefly:
program, control program, configuration file, edit command
program, and diagnostic program. Formore details,refer to the H8/325 Cross Assembler: It is designed for DOS environASE manual ( HS328ASEOlHE).
ment inside the IBM PC-AT compatible Personal Computer.
When the user program is submitted as the source file, it
LCD Display Panels : These character display panels assembles the code. Consequendy,itproducesObjectandList
are provided by the Hitachi's ELT Division. Although, files of the source program.
LMOI6XML, LMOI6L, LM04IL,LM044L,andLM054 panels were used and tested in the laboratory, most of the code H8/ 325 Linker: To link various object code segments (••
development was done using LMOI6XML. The appendix" C tit .OBI " extention) developed in parallel for a larger program.
" lists the panels and their features. Their cable pin outs are The linked file has" tit .ABS "extention. Motorola" S " record
identical and so, switching between them is easier. Note that conversion utility is also included with the linker, and is used
the display orientation for panels LM04IL and LM044L is as output file with" S " record format.
upside down from the other panels. The same demonstration
program was run on all the LCD panels to show "S ", " I ", " Load: To Load "s "Record file "INIT780B.ABS ", afterthe
C",and"D".
ASE system is powered up, the floppy load command shown
All the panels mentioned above are capable of displaying 1 or below is issued:
2 or 4 lines of eight or sixteen or twenty 5x7 alpha numeric :FL INIT780B.ABS;sICR I
characters. Their resolution varies from 40 dots to 100 dots
in width and 8 dots to 32 dotS in height The duty cycle may NOTE: H8/325 ASE COMMANDS ARE NOT OOS
EQUIVALENT.
be 1/8 or 1/16.
The parallel data may be clocked in at a maximum" E " clock
rate of 1 MHz. They run from +5V power supply. The . Demonstration File: After the program file " INIT780B.ABS
customer has to solder 14 pins on each of the panels for the " is loaded from the floppy diskette, the following commands
appropriate connector used on the Emulator Interconnect are given to run the program:
BOard. The LCD panel mounting and the proper viewing :.pc300gu
angles are critical to a strain free LCD display. Please, handle :goQ!!
the panels according to the care recommended by the LCD
display manufacturer. The logic signals sent to the LCD panel Screen Editor: Any word processing package is acceptable.
In this application, Microsoft "WORD" package was used.
are at CMOS levels;
The source programs are created and edited with this package.
The source program files have" tit .SRC " extention.
The LCD display system components such as HS/325 ASE
Unit, Emulator, User cable, Emulator Interconnect Board, a
variety of display panels, External Power Supply and the
related software are described in this section.

It.

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HD44780 / LCD PANEL

Application Note

HARDWARE DESIGN
This section covers H8/325 microprocessor design high lights,
H8/325 initialization, operation mode selection, I/O port
assignments, and HD44 780 design guide lines.

H8/325 MPU Design: This HD6473258 product was
,designed by SICD, Hitachi Ltd., Tokyo, Japan. Refer to the
.Appendix· F' for all the required product design manlials for
the associated circuit design. Only high lights are addressed
iii this illustrative application, since LCD controller peripheral
design is the mam goal.
H8/325 Initialization: Refer to the Appendix· D • for code
sample. This program was developed to scope the H8/325
waveforms iii operating mode 2. The" E" and .. f6. clocks were
measured. RESET Emulation command can be issued used
durilig the debug process as required when ASE is used.
" E " Clock Determination: The maximum' E .. clock rate
of 1 MHz is specified iii the panel specs. as well as the
HD44780 data sheet. Based upon it, the maximum" f6. rate
of8 MHz is established. Therefore, the H8/325 crystal should
be set at 16 MHz. Then ASE system is used, the " f6 .. clock is
set at 7.37MHz usilig the CLOCK Emulation command.

0
0

Port 5 ; Serial Communication
Port 6; Interrupt Request and Free Running Timer

All the ports were listed to make sure that they were initialized
correctly ( specially port 7 ) to match the input output
requirements of the HD44 780 on the LCD panel.

HD44780 LCD Controller Driver : The reset conditions and busy flag check areas are discussed for more clarity:
Reset: The intemal reset conditions or the hardware chip reset
signal, timing sequence is specified in its data sheet. They are
based upon the VCC on or offpower sequence. If these can be
assured at all times, no other reset e.g. software reset, is
necessary for the panel. However, in case of doubt or for
reliability purposes, a software power up sequence specified in
the HD44 780 data sheet may be executed. When contrast pot
is correctly set, the panel will power up with visible character
grid but no character display. Note that the software reset
sequence depends upon 8 or4 bitMPU interface. However, for
this application 8 bit software reset flow chart was used.

Busy Flag Check: The HD44780 instruction execution times
are shown in a table in the data sheet. When the software is
Operating Mode Selection: Operating Mode 2 i.e. Expanded designed to ensure that these execution times are guaranteed
mode with on chip ROM ( 32 K Bytes) address space was , to meet or exceed the specifications, no busy flag check is
chosen. The associated external address space and address required. This will reduce the software code size but will not
map is dermed iii the H8/320 Series Hardware Manual. The optimize the panel data transfer rate. Since, minimizing the
peripheral addressilig is memory mapped, so please refer to it LCD data transfer delay was DIll one of the objectives of this
for details.
application, busy flag was not checked. The associated
The H8!325 • E " clock timilig generation was done by this software had the built in delay to ~ the table of required
MPU and so extemaJlogic was not required. This is one of the instruction execution times.
strengths of the Hitachi H8!320 Series micro processors. It
was decided to exploit this feature.
LCD Display Panels : Although,LMOl6XML,LMOI6L,
VO Port Assignments: The operating mode 2 selection also LM041L, LM044L, and LM054 panels tested in the Applicapre determ.ined the I/O port selection. They are briefly tions Engilieerilig Laboratory, refer to the LMOI6XML specs
for the remainder of this tutorial. The software cridilig was
summarized below:
developed with it in milid. Minor panel dependent code
o Ports 1 and 2; Address Bus
changes are not shown and are left to each user for customizing
o Port 3; Data Bus
the desired panel.
o Port 7 (Partly); Bus Control signals
o Port 4 (Bits 6 and 7 ); .. f6 .. and • E .. Clocks

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HD44780/ LCD PANEL

Application Note

SOFTWARE
This section covers HD44780 software initialization code as
well as the command sequence flow chart. For more coding
details refer to the associated listing for the demonstration
program " INIT780B.ABS .. in the Appendix" E ".

HD44780 Initialization: The data sheet defines the
desirable flow chart for 8 bit initialization sequence. However
the actual implementation code is shown below:

INIT780

FUNCTION
SET COMMAND
30H

FUNCTION
SET COMMAND
30H

FIRST INSTRUCTION - 8 BIT
MPU INTERFACE

SECOND INSTRUCTION - 8
BIT MPU INERfACE

FIGURE 2

26

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HD44780 / LCD PANEL

Application Note
HD44780 Initialization :
This is continued in Figure 3 from the previous page:

FUNCTION
SET COMMAND
30H

FUNCTION
SET COMMAND
3F

DISPLAY AND
CURSOR ON
COMMAND OEH

THIRD INSTRUCTION - 8 BIT
MPU INTERFACE

FOURTH INSTRUCTION - 1/16
DUTY CYCLE

FIFTH INSTRUCTION DISPLAY & CURSOR TURNED
ON

FIGURE 3

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HD44780 / LCD PANEL

Application Note

8D44780 Initialization:
This is continued in Figure 4 from the previous page :

ENTRY MODE
SET COMMAND
06H

SIXTH INSTRUCTION - ENTRY
MODE SET

RETURN HOKE
COMMAND 02H

SEVENTH INSTRUCTION RETURN HOME

SET DDRAM
ADDRESS
COMMAND 80H

EIGHTH INSTRUCTION - SET
DDRAM ADDRESS

INITIALIZATION OVER

FIGURE 4
Section

28

4

HITACHI
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HD44780 / LCD PANEL

Application Note

HD44780 Data Transfer:
This is continued in Figure 5 from the previous page:

WRITE

CHARACTER
CODE FOR

"S"

DATA INSTRUCTION

".

~

CHARACTER CODE 53H FOR

"

WRITE
CHARACTER
CODE FOR

"r"

DATA INSTRUCTION CHARACTER CODE 4!JH FOR
"1 "

WRITE
CHARerER

CODE FOR

"c"

OA''1'A INSTRUCTION -

CHARCTER CODE 438 FOR

"e"

WRITE
CHARACTER
CODE FOR

"0"

SLEEP
COMMAND

DATA INSTROCTION CHARACTER CODE HI!. FOR
"0"

88/325 SLEep COMMAND

ISSUED

FIGURES

HITACHI
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Section

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane,CA 94005-1819 • (415) 589-8300

HD44780/ LCD PANEL

Application Note

AppENDICES

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

31

HD44780 / LCD PANEL

Application Note

APPENDIX " A "

'.

----.~. ..

-.--- --

Features

-

-

-Jt..c-

'\W.-:

• Reallime emulation

• A wide selecIion of emuWion camJII8IIIIs. promoting efficient development for many fllllCliaaa
• Ope:rabUity a a stand.alone system. connected ro an RS·232C inrerf'ace console

• A S.2S·inch floppy disk drive. which faci1itateS:
- Loading. saving. and verifying user system memory contents
-Savingem~n~wlS

-Input. edit. and eMCUIion of commlnds using a floppy disk for external Storage
• An RS·232C inrerf'ace ro a host system whic:h enables:
- Using a host sysa:m console a an ASE console
- Loading. saving. anc! vcnfying the user program using hOSI system facilities
• A Cenlnlnics printer inrerf'acc fill' printoutS of emWation ~ullS.
• Usability of the ASE station compatibility with all H·Serics mic:roprDCCssors

• HELl' functions ro asisl command usage without a manual
• Commanc! execution ciuring emulation (called parallel mode). for example:
- Trace ciats display
- User memory ciisplay and modification
.' MemClI'Y and clock options

- EmWation memory (substitua: user system memory) : 64 kbytes
_ Clock (emulation cloc:lt): 3.6864 MHz. 4.9152 MHz. 7.3728 MHz. anc! 9.8304 MHz

Section

32

4

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589.8300

HD44780 / LCD PANEL

Application Note

APPENDIX " A "
Transparent mode

CRT

HOST
PRINTER
ASE

ASE Components

ASEstation

CRT interface cable (RS-232C)

S.2S-inch flOPPY disk drive

ElTlJlator box -----~

External probes (8)
User system------------~\.
interlace cable
MPU connector --~~-_I'::=~
User system

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Paint Pkwy .• Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

33

Application Note

HD44780 / LCD PANEL
APPENDIX

II

B II

...

o:w

r-+------------f-,

:!
~o

>COl

W,
~----------------' ~~

Section

34

4

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

HD44780 / LCD PANEL

Application Note

APPENDIX " C "

LM016XML
•
•
•
•

18chlrcterx211nes
INTERNAL PIN CONNECTION
Controllor LSI HD44780 il built~n (Soe page 97).
! Pin No. I Symbot I LIWt
+5V single po_ supplV
11VSS
OV
Color tone . . . . . . • . . • • . . . . . . . . . . . . . . . Now gray
+5V

MECHANICAL DATA (Nomineldlm_1
Modu~ iiZll ••••••••.•• 84W x 44H x 12T (max.) 111m
Effwcti.. dlllliav ar.. • •••.•...••• 81W x 15.8H mm
Cha_liza (5 x 7 datil ••••.••• 2.98W x 4BSH mm
Charletor P11l:h. . • • • • • • . . • . . . • . . • • • • • • 3.55 mm
Dot size .•..••.••••..•.•.••• O.58W x 0.8SH mm
Weight ..•..•....••..•.....•...... about 35 ,

E

010

m.x.

6.5 V
VooV
5O·C
70·C

ELECTRICAL CHARACTERISTICS
Ta - 2S·C. V"O • 5.0 V:I: 0.25 V
InpUt "high" voltage (Vi .. 1 •••..••.••.••• 2.2 V min.
InpUt '10w" voltage (Vi L I .............. 0.8 Vma •.
OutpUt"high"vOltage (VoHI (-10... 0.2 mAl .. 2.4 V min.
Output"low"voltage (Vod (IoL' 1.2 mAl .... 0.4 Vmax.
Power supply current (100 I (V"o • 5.0 V) .. 1.0 mA typ.
3.D mA max.
Power supply for LCD drive (Recommendedl (V"o-Vol
Duty -1/18
Range of Voo - Va . . . . . . . . . . . . . . 1.5 - 5.25 V
Ta - O·C . . . . . . . . . . . . . . 4.S V typ.
T. - 25" C ............. 4.4 V typ.
T•• 5O·C ........•.... 4.2 V typ.
OPTICAL DATA . . . . . . . . . . . . . . . . . . . . .

DB1

DB2

6.5V

UII

H: Dote_CLCD"-"~1 I
L: Dote ••• CLCD _ _

AIW

I

ABSOLUTE MAXIMUM RATINGS
min.
Pow.r suaply for logIc (V,," - Vso ) . • . . • • • 0
Power IUPply for LCD drive
(Voo-Vo ) . • . . . . . . . . . . . . . . . . 0
InpUt volt"e (Vi) ...•..•...•.....• Vso
Operating temepratufl (Tal .•.••••••••• 0
Storage temperature (Tltgl •••...••• " -20

L.: IftItNCIlOft codiIlnput
H: DMaII'lDUI

H/L

n

I 083
I 084

12

i D.

10

-

!H,H"L 1

I >IlL
>IlL
>IlL
I >IlL
I >IlL
I >IlL

13

I OBI I

1.

017

I

i
I
I

I
I

CeClaulliM

N_I1I,121

;

>IlL
>IlL

In ,-. Ha..18O. ,1M . . Aft be ...... in lith. 4Git 2. . . .tlOft or

8-tHc , . . . . . . . . 1Mt it CIIn im.fece to tIOtft 4 ..... bit MPU·I.
11) WNft i . . . . . . . . . . . . . bits toni. __ .. tnnIf.,.. uli", onlY 4
bu_ of 01. - Os., and Os. -08, are not VM. ON era. . .
. . . . . . 'M H00M18O and .... MPU ~W. . . . . . . . . . . .I
trMIf.".. twIOI. 0 . . of 1M t'ligMr ordW .. bits Icon.,... of
01. -DB., w-.. .nttrt. . .tI il • biU 10"" it trlMfWNd fira.
Iftd . . . . . . . . Older. bftt tCOM.,. of 08, -oa, ..... '"""HI
_
• • bits ....... .
t2) WMn ............1 8 bits 10"1• •e. II t,.,....,.. UII'" 8 dlta

_oIDI,-DB,.
Ullit:lD.

See_7

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005"1819. (415) 589"8300

Section

4

35

HD44780 / LCD PANEL

Application Note

APPENDIX " C "

LM016L
• 16 charocter x 2 lin..
• Controller LSI HD44780 i. built-in (See page 97).
• +5V lingle _
supply

INTERNAL PIN CONNECTION

IPlft No.

I

Sy_

FunctiOft

H.H ....L I

8
010

I

DBl
DB2
10

6.SV

11

Voo V

12

SO·C
70'C
ELECTRICAL CHARACTERISTICS
Ta • 2S·C. Vao • 5.0 V ± 0.25 V
InpUt "high" voltage (Vi,,1 .............. 2.2 V min.
InpUt "low" volt. (Vi L ) .........•.... 0.8 Vma •.
OutpUt"high"volt1Q8 (VO") (-10" • 0.2 mAl .• 2.4 V min.
OutpUtlow"VOlt. (VOL) (IoL • 1.2 mAl .... 0.4 VmlX.
_ r supply current Uoo ) (Veo • 5.0 V) .. 1.0 mA typo
3.0 mAma •.
Power supply for LCD drive (Recommended) (Voo -V e)

Duty· 1/18
Range of Vee - Ve. . . . . . . . . . . • . . .• 1.5-5.25 V
T.·O°C ...........•.. 4.6 V typo
T•• 25°C ............. 4.4 V typo
T•• SO'C ............. 4.2 V typo
OPTICAL DATA. . . . . . . . . . • . . . . . . • . .•

Section

36

4

-,
13
14

DB3
,

HIL
HIL

I
,

HIL
HIL

,

OM

HIL

DBS

HIL

DBS
DB?

HIL

I

O... bulhne

N_I1I.121

>ilL

In the H044780. 1he dig CIIn be 11m: in either 4.oit 2-ooera.ton or
8-bit ' . . . .tlOn 10 tnet it Cln Interface 10 bOttt 4 lnet 8 bit MPU',.
11) When ifttttrflC8 CSIta i, ,. bit. lone, oau i, trantflfftld Uling onty ..
bu. of 08. - 08" and DB. -08, .... nen: u.... Olq tr.Nt.
betWNn 1M HO. .'80 Ind the MPU comotn.. ¥If'*' 4-blt 4MI ..

trlftlflfNd twa. Data of the higNr order .. bit. 'con..ntl of
oa, -DB, WMn in'''''" dig .. a bitl tong) il ttln".rlG 'ir•

.... ttlen IOwW ora.... tm. h:ontiMlof 08, -D., when Int'"__

a

dI. it bitt to",).
(2) When Interface diu II 8 bit, 10,.. dl" i. 'rlnlf.,," "II", 8 dMa
bu. . ofOa.-OI.,.

Uait:m..

See page 7

HITACHI
. Hitachi America, Ltd.· San Francisco Genter· 2000 Sierra Point Pkwy.• Brisbane, GA 94005-1819 • (415) 589-8300

HD44780 / LCD PANEL

Application Note

APPENDIX " C "

LM041L
I

I
I

16 ChirEttr x 4 Ii ....
ContrOller LSI H044780 is built·in ISeI page 97).
+5V singlt _
supply

MECHANICAL DATA INomonal di .......ioml
Moduli." •....•.... , 87W x 60H x 12T Imax.1 mm I
Effective'display,,"a . . . . . . . . . . .
OIaractlrsi.. 15 x 7 dots I ........
Character potch. . . . . . . . . . . . . . . .
Dot ".. . . . . . . . . . . . . . . . . . . . .
Wligh, .... . . . . . . . . . . . . . . . . .

61.BW x 2S.2H mm
2.95W x 4.1SH mm
. . . . . .. 3.55 mm
O.SSW x O.SSH mm
. . . . .. abou, 60g

i

5

so'e
70'e

i

12

I.
13

ELECTRICAL CHARACTRISTICS

,
i
I

I
I

-

I
OV

I

~V

I

MIL

I

MIL
MIL
>IlL
>IlL
I >IlL
! MIL
I >IlL
I >IlL

081
082
083

,

,
,

OM
0115

i 088
I 087

,

!

I

L.: InRNC1lon coOl inout
H: o.Uinout

M: 00...... ILCO .-1o_PUI
L: 0 ... Wflt. tL.CD "...,.. ..-wul

e_ ......

H,H"L I

I

-

I

MIL

OBO

p--

Function

i

RS

E

7
8
9
10
11

i

i

RIW

6

,

I

Vo

i •
,

6.SV
6.SV
Voo V

I

3

ABSOLUTE MAXIMUM RATINGS
Power SUDOIV fa. logoc IVoo -Vss) . . . . . . 0
PowersuDOIV fa. LCDd""IV oo -Vo) .... 0
Inou,valtoge IV,) . . . . . . . . . . . . . . . . . Vs •
Opera,ong tlmpora,ure ITa) . . . . . . . . . . . . 0
S,orlge tlmporaturo ITstg) . . . . . . . . . .. -20

....-

IN'DRNAL PIN CONNECTION

I Pin No. I Sv_
I 1 I V.
, 2
Veo

I
I
I

Oatil bUlh,.

,i

",_111.121

II
I

_._il ___

TI-2S'C. Voo ·5.0VtO.2SV
N. . .:
Inout "high" voltage IV, .. ) . . . . . . . . . . . . .. 2.2V min. In tM H00M18D. the . , . CIIn btl sent in either 4S
96

."

,.
100

101
102
10J

'H'FF, R1L

SASE '1' ICK£R PRESET COUNT- FrH

OECR BASE TICKER

R1L

.'E

RlL COUNT DOWN CONTIlfUZS
BASE TICKER. COUNT OVER.

fIFTH INST1\UCTION -

0358 FeOE
ol5A fiACS 9000

HOV.S

035& 0000

NO'

DISPLAY ~D CURSOR ON -

'H'Oe. RlL
HOYTP! RlL.IH'9000:16

OEH

INSTRUCTION CODE - OEH
PERIPHERAL WRITE MITH E CLOCK

START DELAY 6 - EDEDS .. 0 uS

laC
105

0360 F9FF

106
107

0362 lA09

DEC

108

:J3, ..

urc

••E

HOV.a

,H'FF, R1L

BASE TICKER. PRESET COUNT- P'FH

R1L

DEeR. BASE tICXZIt
R1L COUNT DOWN CONTINUU
SASI TICKER COUNT OVER

10'

lla
III

0366 0000

112

ll3
llC
llS

Section
42

4

NO'
SIXTH INSTRUCTION - ENTRY MODE SET

- 06R

')368 FB06

MOV.a

'H ' 06. R3L

:J36A 6ACS 9000

MOVTPIT

RlL.'H'gOOOn6 ; PERIPHERAL WRITE WITH E cLOCtt

INSTRUCTION CODe -

06M

HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

HD44780 / LCD PANEL

Application Note

APPENDIX" E "

_r

!-!.lcroc.ec R•••• rcb ASMH83

Line

116
11'
:18
119
120
121
122
123

"enlon 1.0A

tie". 3

Cct. 09 10;25136 1911

036! 0000
0370 F9rr
0312 lAc9

NOP

0374 UFe

8NE

MaV.S

tH'IT,R1L

DEC

PRESET BASE TICKER COUNT

:l.lL

DECR R1L

; COUNT DOWN CQNTIIiUBI

DELAY EXEEDS 40uS

124
125

126
:21
:28
129
130
131
132
III

S£VENTH INSTRUCTICN -

0376 FB02
J318 GAce 9000
'J37C

ooco

CURSOR HOME ,

MaV.S

~H·02.

MOVTP!

RlL.@H'9000:16

alL

OORAM ADR SET '1'0 0 .. 02H

!NSTRUCTION CODE. 02H
?ERIPHERAL WRITE WITH E CLOCK

NOP

sTARr OELAY 1 - EDEDS 1.64
OJ7£ F9FF

HOY.S

0380 lA09
0382 Hrc

DEC

'H'FF,

!lIS

R1L

BASE TICKER PRESET COUNT- FP'H

134
135
ll1
137
138

130

R1L

OEeR BASE Tlcx&Jt

8Ha

0384 lAOA
0386 'l6re

o,c

0388 0000

NOP

alL COUN'l' DOWN COM'l'tNUU

BASK '1' ICKER COUNT efta
OEeR SIGNIFICANT 'l'IMIIl
R2L COUNt DONN CON'l'I1IU&a

R2L

8Na

140

141
142
143

1. 64rftS DELAX OVER

144
145
146

HOH78a INITtAL;ZATION COMPLETE
fIRST COMMAND -

SET DDRAM ADDRESS -

80H

1-41

:48

:49

03SA

oeoc

~38C

FaBO

~50

')]8£ 6ACB 900e

:51
152
153
154
155
156
15'

0)92

oooc

NOP
~V.B

tH'80, RlL

HRITZ OORAM ADR CODE -

MOVTPE

RlL. @H'9000:16

?ERIPHERAL WRItE. WITH E CLOCK

NOP
DELAY E](EZDS 40\1$

0394 F9FF
0396 lA09
0398 UFC

lsa
159

HOY.S
DEC

'H'FF.R1L
RlL

BNa
SECOND COMMAIID NO.

OJ9C F!35J

HOY.S
tH'53. R3L
MOVT,Z R3L. fR'9001:16

168

,.9

DEeR R1L
: COUNT DOWN CON'nNUU

WRI'l'E CHMAC'rER CODE 538 TO DORAM

OlgA 0000

161
162
163

OJ9E 6ACS 9001
'J3A2 cooo

PRESET BASE rIet(ER COUN'!'

K

"'0

:.64
165
160
:67

80H

CHARACTER CODE FOR "S· - 53H

PERIPHERAL. WRITE WITH E. CLOCK

NO.

DELAY EXEEDS 40u5
NOP

OJA4 F9FF

HOV.9

03A6 a09

DEC

OlA8 16FC

8H'

IH IFF. RlL

PRES!.T BASE TICKER CCUB!

R1L

; DECR lUL
; COUNT DOWN CONTINUES

:10
:.71

112
113

THIRD COMMAND - WRITE CHARACTER CODE - o19K
OlAA 0000

NO.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra POint Pkwy .• Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

43

HD44780 / LCD PANEL

Application Note

APPENDIX " E "

Oct

101n.

17'
175

176
177

HOV.S

tR'49. R3L

MOV1'PE

RJL. @H'9001:lG

0382 0000

NO.

:'85

CHARACTER CODE FOR I - <498
?ERUHERAL WRITE WITH E cLOCJC

DELAY EXEEDS 40uS

0384 F9rr
03B6

LA~g

0388 46FC

1B4

186
187
188

10:25:36 1991

A5OMO (OC2OOV)
Withstanding \tlIIage: AC25rN (1 minute)
SwieCh Bounce:
< 5mIc
SwIICn rrav.l:
0.118 in.
Ac:tuI*In Fcn:e:
130 g :I: 20 g
Life ~
> 1,000,000 acIUIIiOnI

Nominal Raling:
Contact Reastance:

884 (24x36) LCD ~ WIlt! super·twiII
18 Max. (USIng 5 x 7 malrix. 3 lines by II diQiIs>
.014 in. IQ.

.490x.590 in.

CONNECTOR PIN ASSIGNMENTS

....

"-lIon

2

PIn
SW1
SW2

3

Voa

IUCIIlIY \IOUgI for lOgIc + 5V

~IUCIPIY

~

DIN

DauT CI careaIIr

5
II
7
8

LP

dIIa Inoue
IIIICI\' puIIe

1

SWIICI'I
SWIICI'I

COnIIIetI-.
u.- CMllned
u.- CMIIned

FI.M

ftlll line IMIII8r

conInIIIIr
conInIIIIr

V\.C

SICIGIV IdICII for LCD

~SICIGIV

GND

ground (tOY)

~.,.

9

0CuT

dIIa~

10

SCP

"12

RST
I.£DA

..... Clack III*,..1iQnII

OIl
conInIIIIr
conInIIIIr

13

LEOK

LID ....
LID . . . .

DIMENSIONAL DRAWINGS

DOWIr
DOWIr

~

IU·

IUDIII¥
IUDIII¥

74

it

ffiJ
......
......

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • 1415) 589-8300
/

September, 1990

HD61830B / LM200
Custom Character Generation

TUTORIAL PART II

Kash Yajnik

TheflfSttutorial described in the Hitachi document #AE 150
presents in depth design process for a LCD subsystem. this
document is part II of that tutorial and describes custom
character generation. Its major components include H8/532
Evaluation board as the local processor, LCD Controller
HD61830B,andthedisplaypaneILM200fromHitachiELT
Division, and EPROM resident custom character set.
The HD61830B controller is designed to run in the character
mode. TheHS/532 Evaluation Board is designed by Hitachi
Microsystems. The LM200 LCD panel can display 240
Dots(W) by 64 Dots(H) character or graphics data. Hitachi
Monitor firmware resident on the H8/532 Evaluation Board
provides the program debugging andhostcomputercommunication facilities.
By adding a laptop computer to download the programs to the
Evaluation Board, a program development station can be
readilybuilt. 1beH8/S32CrossAssembler,Linker,anyword
processor package e.g. "WORD" as screen editor, and
Motorola "S" record conversion utility inside the Hitachi
laptop PC complete the software development environment.
The "PROCOMM" communication package is used to facilitate down load or up load of programs to the H8/532 Evaluation board.

The custom character generation program is listed in the
Appendix "A". No effort is spent in either code or logic
minimization.
This tutorial is intended for the technical staff at customer
sites and other Hitachi emplOyees who are fairly familiar with
LCD design guide lines. Therefore, basic LCD design
principles are not covered.
The HD61830B LCD Controller design tutorial includes
Introduction, Design Overview, Custom Character definition
and display, LCD Interface Board Schematic, along with the
associated Software.
While a lotof programs were developed, only one is listed as
an example in the Appendix "A". The Appendix "B" covers
EPROM font data while the Appendix "C"lists the reference
literature.
Only the details not available in the reference section are z
explained at greater length in this article. The page f shows ~
the Table Of Contents.
~
Refer to the subsequent pages for more informationonthepart
II of this design.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819 • (415) 589-8300

Section

4

75

I

~

76

Section

HITACHI

4

Hitachi America, Ltd .. • San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

TABLE OF CONTENTS

TOPICS

PAGE

1.0

IN1RODUCTION ........................................................................................................... .

78

2.0

DESIGN OVERVIEW .................................................................................................... .

79

3.0

CUSTOM rnARAC1ER DEFINITION ........................................................................ ..

82

4.0

CUSTOM C'HARACfER DISPLAY ............................................................................... .

87

5.0

LCD INTERFACE
BOARD SClIEMATIC .................................................................... ..
,

89

6.0

SOFIWARE .................................................... ;.............................................................. . 94

7.0

APPENDICES ................................................................................................................ ..

95

APPENDIX "A"

XCG.LIS ....................................................................................... .
(CUSTOM rnARAC1ER GENERATION - FOUR BY1ES)

95

APPENDIX "B"

EPROM CHARACTER FONT DATA ...................................... 100

APPENDIX "C"

REFERENCE LI1ERATURE .......................................................

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300

II

105

Section

4

77

1.0 INTRODUCTION:
This section describes the design goals and provides a general overview of this presentation, along with a
software development listing.
The design goals established for this project are briefly listed below:

1.1 To use H8/532 Evaluation Board with Monitor Software.
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9

To provide custom character LCD display with LM200 panel from Hitachi.
To display largest characters in the character mode of the HD61830B.
To design Interface Board for the LM200 LCD panel.
To write programs for debug and test.
To use Hitachi Laptop Personal Computer "HL320".
To use readily available software at Hitachi Field Offices for development.
To build a stand alone display unit.
To generate HD61830B / LM200 panel design tutorial part n.

A brief description of the LCD display subsystem components listed above is provided in the next section
as an overview. To complete the overview, a subsystem block diagram is also presented. The rest of the
sections described in the Table Of Contents are e~panded in greater details along with their programming
data. The Appendices give the program listing, EPROM font data, and also list the referenced literature.
A copy of the LCD Interface Board schematic is also provided to illustrate the implementation details of
this tutorial.

78

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

2.0 DESIGN OVERVIEW:
The LCD display subsystem components such as H8 / 532 Evaluation Board, LM200 display, LCD
Interface Board, Hitachi Laptop Computer, and the related software are described in this section. At the
end, a subsystem block diagram is also presented. For the HD61830B LCD Controller, and the LM200
LCD panel data sheets, as well as other related documentation refer, to the Appendix "C". This description from the HD61830B / LM200 Design Tutorial Part I is included only for completeness of this document, and can therefore be skipped by those familiar with the Part I.
2.1 H8I532 Evaluation Board: This board was designed by Hitachi Micro Systems. It is provided as a
training and development tool. On-board EPROM contains the Hitachi Monitor finnware used for single
line assembly, disassembly, line editing, and debug purposes. Of the two serial ports, only the Terminal
port is used to down load, up load, and run the programs. The I/O extention connectors "11" and "J2" are
used to connect to the LCD Interface Board. The partially decoded extented I/O space is further decoded
on the LCD Interface Board. This board is designed to run at lOMHz and uses a 20 MHz crystal for that
purpose. However, in this application a 16 MHz crystal is used to provide IMHz "E" clock to the
LCD Controller HD61830B. All the jumpers on this board are set at the factory according to their
default states.
2.2 LM200 LCD Panel display: This display is provided by the Hitachi ELT Division. It is capable
of displaying alpha-numeric characters as well as the graphics data. However, only character mode is
used in this application. It is 240 dots wide and 64 dots high. It has 1 /32 duty cycle. The s.erial data is
clocked in at 500KHz. It runs from: +5V, and -12V power supply. The customer has to solder the pins
on LM200 for the appropriate connector used on the LCD Interface Board. The LM200 LCD panel
mounting and the proper viewing angles are critical to a strain free LCD display. Please, handle the
panels according to the care recommended by the LCD display manufacturer. The logic signals sent to
the LCD panel are at CMOS levels.

~

:::
F-~

2.3 LCD Interface Board : A wire wrap board was built to control the LCD panel LM200. It also
exchanged data with the H8/532 Evaluation Board over the I/O extention cables "11" and "J2". The
Hitachi LCD controller HD61830B was used on the LCD Interface Board. A 4,096 byte display buffer
memory was also designed to store the character data. The 500KHz dot clock required by the display
was also provided on this board. The LM200 LCD panel contrast adjust potentiometer was also put on
this board. Set the jumper "110" on this board to the "C-2" position. Test connectors were also provided
to help debug this board.
2.4 Hitachi Laptop Personal Computer "HL320" : It is connected to the serial terminal port of the
H8/532 Evaluation Board. The connector RJ-12 is attached to the Terminal port while a male to female
25 pin adapter cable is required at the Laptop PC end. The Hitachi "HL320" PC provides the software
development tools for the user programs. The program up load and down load capability is also provided
by the laptop PC. The communication link is full duplex, 9600 baud, 8 bits, 1 stop bit, and no parity
check.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

79

I
••

2.0 DESIGN OVERVIEW: (CNTD.)
2.S Software Tools : The laptop PC resident software development tools, packages, and utilities are
described very breifly.
H8 /532 Cross Assembler: It is designed for DOS environment inside the laptop Personal Computer.
When the user program is submitted as the source file, it assembles the code. Consequently, it produces
Object and List files of the source program. The list files with" * .LIS " extentions are reproduced in the
appendices for the programs developed on the software work station.
H8/ 532 Linker: To link various object code segments (" *.OBJ " extention) developed in parallel for a
larger program. The linked file has " *.ABS " extention.
Motorola S record Conversion Utility: It is used to convert the machine code into Motorola" S "
record format for uploading it to the H8 / 532 Evaluation Board. The converted file has" *.MOT "
extention.
It

It

Up Loading Of Laptop PC "S" Record file: Push" EDIT SHIFT" Key down. Depress the" PO UP "
key when using PROCOMM " package for communications. Also, select ASCn format.
It

Screen Editor: Any word processing package is acceptable. In this application, Microsoft "WORD"
package is used. The source programs are created and edited with this package. The source program
files have " *.SRC " extentions.
File Management Utilities: To help aid the program development, packages such as " XTREE ",
or " TREE86 " may also be used.
Back -Up Utility: It is a good practice to back up program files. Such packages as "FASTBACK ", OR
" FASTBACK PLUS" can also be used.
EPROM Programming: Data I/O Model 212 Multi-programmer was used to program the 32KByte or
16KByte UV erasable EPROMS.
The stand alone display unit block diagram is shown on the next page.

80

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

HD61830B I LM200 STAND ALONE UNIT

HITACHI
l.APTOP
COMPUTER

L

LCD INTERFACE BOARD (*)

,.........,

;,--..

HD
H8!532

J1

,.........,

,.........,

.12

BOARD

.........

J1
'--"

'--"

EVAL.

IpOWER

4"
~

4"

I--'--

J2'
'--"

---I

H

61830B

4KB
BUFFER

l

CO
EPROM

§f

r-

-'

J3
(

)

J4

,

12"

LCD PANEL
LM200

'--'

I
* NOTE

1.0 8 MHZ OSC. DIVIDED DOWN.
2.0 SET "J1" JUMPER TO "C-2· POSITION.

BLOCK DIAGRAM

HITACHI
Hitachi AmeriCa, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

81

CUSTOM CHARACTER DEFINITION:
In character mode, for visual comparison, the maximum programmable font size of 8 (Columns) x 16
(Rows) using the Hitachi LCO controller HD61830B was chosen for display. Also, note that in the
graphics mode of the HD61830B, larger font sizes beyond the character mode limits are possible.
However, for this tutorial, only the character mode is considered to illustrate custom character generation
using an EPROM.
.
The custom characters were displayed on the LCO panel LM200 from Hitachi America Ltd.
Arbitrarily, four custom characters "K", "A", "S", and "H" were chosen for font generation using a 32K
bytes EPROM. The Figures 1,2,3, and 4 show each character, its character code, line position, and the
EPROM data output. The character shapes were purposely chosen to be slightly different from the
standard character shapes defined in the HD61830B data sheet. This makes character verification easier
and distinguishes custom characters from the standard character set.
The custom character font line position address bits (A3-AO) were connected to the (MA1S-MA12)
signals from the HD61830B. These four bits form the lowest address nibble of the 32KB character
generator EPROM. The character code address bits (A11-A4) are also provided by the (MD7-MOO)
signals from the HD61830B. These character code bits determine the square in the character map where
the custom character is located. For more information on the character map refer to the H061830B data
sheet. The standard character in the character map is replaced by the custom character at the location
addressed by the character code bits (A11-A4) of the EPROM.
Note that only one 4,096 bytes long page can be addressed by the HD61830B from the available 8 pages
in the 32K Bytes EPROM space in the character mode. Therefore, the upper address bits (A12-A14) of
the EPROM are grounded to select page O. The character font EPROM output data bits (07'-00') are
sent to the HD61830B ROM data input bus (RD7-RDO).
IUs left up to the reader to come up with a scheme to locate 8 different character sets on a 4KB page
boundary e.g. Eight different languages for eight countries in Europe within the 32KB EPROM character
space. The appropriate font page for a country should be activated when a LCD display panel is used for
a product in the specified country. Such a font design would make the product saleable in the international markets.
For the implementation details on the four custom character EPROM refer to the schematic in the
sectionS.

HITACHI

Section

82

4

.Hitachi America, Ltd.'

San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

F.PHOM

C
H
I~

"""r"

ADIHU1SS

EPROM OUTPU'l'

LINE

CODJlJS

CHARACTIo:R

POSITION

IAll AlO AS A6 IA7 A6 A5 A4 AS A2
0
1
1
1
0
1
0
0
0
0
0

0

0
0
-

0

0

0
0

Al
0

0
.1.
1,

i

.1.
1

0

0

AO
0
1

0

1
0
1

07 06

•
0

0

0
0

0

0

05 04 03

0

0

02

0

0

0

E

0

0

111

0

0

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0

0

00
0

r·········,

IE
0

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0

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0

0

i··········,
0

0

I··········,

"K"

0

1

1

0

0

0

0

0

0

0

I···········
0

1

1

1

0

0

0

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1
l.
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18

0

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0

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FIGURE 1

HITACHI
Hitachi America, Ltd. ~ San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

83

E!PHOM

C

ADDHF.:SS

~-------------------------r----------~
LINE
H
CI:IAHAC'I'EH CODES

Ii!PROM

()U'l'PU'l'

POSITION

RAllA10~A~~~A5A4~~AlM~~050403020100
..... ,

0

1

0

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0

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0

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II

0

0

0

0

. ..... ,................................. ···········1··········1·········1···········

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OOOlOOmO.OOO

. ·1······· ·1······· t····· ··1·······

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FIGURE 2

84

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I······....

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589'8300

()

0

0

c
H

/'-

CHAHAC'I'EH

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..... ,............ + ......... +...... ;................... ..

o

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LINE

CODES

POSITION

1

o

1

. ....... · ........ 1·; .. ·.... ·

0

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·

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,

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.... ·1 ....

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,

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.

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()
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1

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a

0

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0

FIGURE 3

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

85

ADDfmSS

H!PROM

C
H

CHARAC'I'ER

. . . r--

1

0

0

1

0

()U'fPU'f

POSI'I'lON

R IAll A10 A9 AS A7 AS A5 A4
0

Jl::PROM

LINE

CODES

0

0

~3 ..JJ.2 ~ ~ ~~~~~~ ~
0
0
0
0
0
0
0
0
0
0
.. . ........... I············

0

0

0

...........

0

.1.

0

0

0

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0

0

t···········
0

0

1

0

0

0

0

0

0

0

t·...•···•..
()

0
I···· ..

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0

1

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11
....... I···········

0

0

()

()

0

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0

0

0

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0

()

..

t········ .. ·

0

0
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1

0

0

1

0

0

0

0

0

0
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0

1

1

0

0

1

1

1

0

0

0

()

0

0
t···········

0

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0

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l.

0

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0

1

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I'V

V I'V- I'V- 1'1..;

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1

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0

0

FIGURE 4

86

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

()

0

0

CUSTOM CHARACTER DISPLAY :

The horizontal character pitch (HP) is. 8. Also, the inter character space is 1 row horizontally and 1
column vertically. Programming a logic 1 inside the EPROM corresponds to a lighted dot on the LCD
panel LM200. It appears as a dark dot on the plain background. A variable resistor is also provided to
adjust the contrast ratio. The character display for each of the four characters "K", "A", "S", and "H" is
shown in the Figures 5,6,7, and 8 respectively. Observe the display pattern inversion from the corresponding programmed patterns of the EPROM illustrated in the Figures 1,2,3, and 4 of the section 3.
The Appendix "B" shows the EPROM font data and its addresses along with a check sum. The Data I/O
model 212 Multi Programq:ler was used for programming the 32K Bytes Hitachi EPROM HNC256AG15 or 16K Bytes HitachiEPROMHN27128AG-17. Both the EPROMS were used for generating the
same four custom characters defined in the section 3 and displayed in the Figures of the section 4.

DISPLAY

CHARACTER
\10XOI
COLUMNS

FIGURE-S

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

87

DISPLAY
CHARACTER
(Olexa)
COLUMNS

0

II

3
4

1\
6

i

'7

8
9

10

11
.\2

13
14

111

FIGURE 6
DISPLAY
CHAFIACTER
( 16XS)

COLUMNS

0

II

3

4

1\

(I

'7

()

:I

3
4
5
6

i

'7
8
9
10
.t1

11l
13
14
15

FIGURE 7

88

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

DISPLAY
CHARACTER

FIGURE 8

s.o LCD

INTERFACE BOARD SCHEMATIC:

The next two pages show the schematic of the LCD interface board used in custom character generation.
The Hitachi UV EPROM HN27C256AG -15 (32KBx8) resident in a ZIP sOcket was used as a character
generator. As an alternate part, EPROM HN27128AG-17 (16KBx8) was also tested for the same application. Also, note that the LCD PANELLM200 DC power supply (+5V,G, -12V) can also be tied to the
H8/532 Evaluation Board power source atone point In such a case, the display contrast resistor may
have to be re-adjusted.

HITACHI
Hitachi America. Ltd,· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane. CA 94005-1819 ", (415) 589-8300

Section

4

89

TUTORIAL PART II
io

HD6183QB I LMlOO DESIGN.· CUSTOM CHARACTER GENERAIION
LCD INTERFACE BOARD . SCHEMATIC

,

...)

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n

i

NI

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&4\.10

X

~

'j
:r..

Section

90

4

HITACHI
Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

TUTORIAL· PART II
H061mB I LM200 DESIGN. CUSTOM CHARACTER GENERATION
LCD INTERFACE BOARD • SCHEMATIC

Vcc;

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2,1;.

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.,

NOTE:
1.0 Test Connectors Tl,l2, and 1'3 are for test and debug.
2.0 After power on reset, Display is "OFF", Slave Mode "ON", and Hp = 6.

HITACHI
Hitachi America, Ltd.· San Francisco Genter· 2000 Sierra Point Pkwy.· Brisbane, GA 94005-1819 • (415) 589-8300

Section

4

91

TUTORIAL-PART II
Custom Character Generation-Schematic
~ FROM PAGE 2

RD0 - RD7 BUS'

MA12 -MA1S BUS"

TO PAGE 2

~ ..

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i

VCC'1

u;

r;:1=l?~~!lY ~ ~_illll f=
r==
!! ~
~
I~
'-S

11

T3

o

P

G'

-:1

HITACHI
D PAN EL
LCLM200

.

;0

L....--

LCD POWER SHOWN ON PA GE 1

PR GEl OF 2

92

Section

HITACHI

4

Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

Custom Cbanu:ier Geperation

PAGE
FROM
1 [

>-~

__~~__,

......111101111~.....-~

••
r.

114"~T5
=

TO PAGE 1

04
o.
06
0'

32K X 8
UV EPROM
HN27C256AG-17

ZIF SOCKET

LCD POWER
+5V

0.1 tI

T3

IK. 0.1"

*0

GND

1.1 ,.,
.HV
0.1 uT

+5V
GND
.,.5V
Vo.

140, O.IN

PINS 7,8,9 AND 10 OF
J3 PROVIDE POWER FOR

l_C_D_e~~1

PANEL SHOWN__l_M_2_0_0
ON PAGE
__ 1.
_ _________________________________________________T_H_E_H_I_T_A_C_H_I

NOTES:
1.0

Test connectors Tl, T2, T3, T4, ond T5 ore for test ond debug.

2.0

On H8/325 EVAl. BOARD chonge "YI" crystol from

3.0

Power on reset: Dlsploy off, Slove Mode On, ond Hp

4.0

Instol I 28 pin ZIF wlre-wrop socket . .

5.0

Color code wires.

6.0

Decouple VCC pin 2B.

7.0

Keep wire lengths os short os possible.

8.0

For HN27128AG-17 EPROM, A14 (pin 27l

9.0
10.0
11.0

20 MHz to 16 MHz.

= 6.

Is tied to VCC.

* Jl ond J2 ore from H8/S32 Evoluotlon boord.
* * U1 - U8 eoch hove 0.01 uF copocitor between
* * * U7 hos ground ot pin 7 ond Vcc ot pin 14.
0

Vcc ond ground.

PAGE 2 OF 2
HITACHI
Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

SectIon

4

93

~

•

7.0 SOFfWARE :
The software section covering the H.D61830B /LM200 panel design tutorial part I shows I/O address,
Busy Flag Varification, Initialization Flow Chart, Code Assembly Procedure while its Appendices show
the program listings.

In the tutorial part II, the custom character generation program" XCG.MOT " is listed in the Appendix
"A". The Appendix "B" shows the character font patterns loaded in a 32KB EPROM. The
" XCG.MOT " program is located at the address 8000H in the H8/532 processor Evaluation
Boanl memory space. After initailizing the LCD controller HD61830B, it enables the external character
generator. Then clears the screen by writing character code 20H Le. code for a blank: in the LCD display
memory. Following a screen clear routine, the character for the four custom character "K","A","S", and
"H" are written in the LCD display frame memory. Since the display is memory mapped, the four
custom characters get displayed. For more information on the " XCG.MOT " program refer to the Appendix "A". The number of custom characters can be expanded from 4 to 256 with a maximum font size
of 16 (Rows) x 8 (columns) only in the character mode. However, for demonstartion purposes only four
custom characters were chosen for this tutorial.
For register programming details, refer to the H.D61830B data sheet.
The code developed in the Appendix "A" for external character generator program can also be transported
to the H8/532 Evaluation Boanl. It can reside within a HN27512AG -25 EPROM which replaces the
HMS V1.2 debugger EPROM located at "U6" onthe H8/532 Evaluation Board. In this manner, a stand
alone custom character display unit can also be built.

94

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point PkwY.· Brisbane, CA 94005-1819 • (415) 589-8300

H8/330

Application Note

Listing 2; START LIS 'continued)
: enable input delay timer

3"

399 proCJr.. C aDAE Fl08
400 program. C 0080 3190
401
....... H8/300 ASSEMBLER
PROGRAM NAME 402
403 program C 0082
404 proqnm C 0082 OUO
40S
406 program C 0084 40re
407
408
U***TOTAL ERRORS
**·**TOTAL WARNINGS

66

lIov.b
mov.b
VER 1.1

***

t8~rOl

rOl.@frt_tier

;enable delay timer interrupts
PAGE

03/20/91 08:11:20

Butfer Initialization Routine
:uin loop
main:
sleep
bra

Ivait for interrupts

main

• end

Section

HITACHI

5

Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

H8/330

Application Note
Listing 2; START LIS (gQntinued)
319
320 proqr&/ll C 0048 ODS6
HI/300 ASSBHBLBR

.... II

PROGRAM NAMS -

321
322
323
32.
325 pro;ram.
32.
327
328 prognna
32.
330
331 proqnm

C 004E 19000000

proqum

C 0052 68801'1'92

332

333
334 prognm

335 proqrlll
33.
33"1 proqram
338 proqtaftl.
33.
340 proqnm
341 program
342
343
344 proqram.
345 program
346
341 proqram
348 program
3 ••
350 program
351 proqu.
3.2
353 proqrm
354 proqum
355 program

3$6 proqrlll
3.7
3.'
359 proqr&m.
360 proqram
361

VER

:re-initialize buffer pointers
IIlOV.W
rS,r6
;clear lOP and ODP
03/20/91 08:11:20
Buffer Initialization Routine

1.1

;initialize proqram constants and flags
C COCA
C

ooce

ruo

:initialize mar9in area
I\\Ov.b
th'10,r4h

FClS

: initialize flags
mov.b
,h'lS,r41

:mar91n .. 16 bytes

; initialize free-running timer tor input watchdog timing
mov.IiI'
to,rO
rO,@frt_frc
;reset counter

e

0056 1'801
C 0058 3891

IIlOv.b
mov.b

fl, rOl

rOl,@frt_tcsr

;clear counter on match a

C DOSA 1'800
C
3896

IIlOv.b
mov.b

to. rOl
rOl,@frt_tcr

luse phi/2

C 005& 79000IN
C 0062 6a80FF94

mov.IiI'

tSOO, rO
rO,@frt_ocra

I set count for 100 usee

oose

C 0066 F801

C 0068 llcl
C 006A F800

C 006C lact
C 006B 1'100

e

0010

lIce

C 0012 re02

e

007.(

3aca

C 00'16 Fl05
C 0078 31CA

C 001A ,801
C 007C lIDO

: initialize multi-function timer a for output strobe generation
mov.b
fl,rOl
mov.b
rOl,@tmrO_tcr
IU8e phi/8, no interrupts
mov.b
mav.b

tO,rOl
r01,@trnrO_tcsr

;ne9ative strobe

mav.})
moY.b

tO,rOl
r01,@tmrO_tent

Ic1ear counter

mov.b
mov. b
mov.b
IIlOv.b

#2,r01
1'01, @tmrO teorb
fS,r01
r01,@tmrO_tcora 1generate strobe 2.4 usee wide

: initialize mUlti-function timer 1 for initialization timing
mov.b
fl,r01
mov.b
r01,@tmr1_tcr
IUle phi/8, no interrupt

proqram

C 007& ra06

363 proqrUll

C 0010 38D1

mov.b
IIlOY.b

f6,r01
rOl,Itmrl_tesr

;negat1ve strobe

C 0012 raoo
C 0084 3804

mav.b
mov.b

fO, rOl
rOl,@tmrl_tent

;.et counter to a

367
368 program
369 proqram

e

310 pr09um
371 program

e OOIA F834
coole 38D2

mov.b
mov.b
mov.b
mov.b

t2,r01
rOl,@tmrl tcorb
fh'34,rOlrOl,@tmrl_tcora 1generate strobe 11.0 usee wide

362

364
365 proqram

366 proqrd

0086 1'802

C 0088 3803

372
373

374
375
376
377

proCJum
proqrlm
proqrUl
proqum

e
C
C
c

008!
0090
0092
0094

F807
38c6
38e7
0700

37'

37.

380 proqram
3'81 pro9um

PAGE

COO" F800
C 0098 38D4

: initialize interrupt structure
mov.b
t7,r01
mov.b
rOl,@iscr
mov.b
rOl, Uer
Ide
fh' 00, ccr

; Bet maskable interrupts
: for falling edge
; enable maskable interrupts
; 910bal interrupt enable

: enable inU pulse timer
mov.b
fO,rOl
tlOY.b
rOl,Itmrl_tcnt

;reset init pulse count

3'2

383 proqram
384 pr09ram

e 009A F8U
cOOte 31DO

mov.})
mov.b

'b'4.l,rOl
rOl,@tmrl_tcr

IUle phi/a, interrupt- on match

,&

30S

3.'

38'1 proqtatl
388 proqralll
3,89 proQra

e OOAO UFe

: teat for initialization complete
init loop;
btlt.b 'buf in1t flag,r41
bne
init:looP-

dnit done '1
;no

e 00.\2 1F821240

; enable input handshaking
bc:lr.h t1buay_bit, Un_hs

: release input busy si9nal

C aOA6 1F827200
c OOM 7F827210

;set atatu. indicators
bc1r.b fready_bit,htatyort
bclr.b 'online_bit,8.stat_port

:Light Ready LED
:Light On Line LED

C 009E
C 009! 132e

390

391
392 proqram
393
394

395 program
396 pro9uIIl
3'7

HITACH.I
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589-8300

Section

5

65

HS/330

Application Note

M.st:ing 2' START US
... H8'300 ASSBHBLER
PROGRAM NAMB -

.3/2./U .,,11,2 •
Buffer Initialization Routine

VBR 1.1

PAGE

"Buffer Initialiu.tion Routine-

.hudin9

;HI/330 Print Buff.r Routine
;r.vision 2.0
Iwritten bYI
1'0111. Hampton
Hitachi AlMlrica, Ltd •
Application £nvinaaring

7

.

••

• output
.priDt

241
249
2'.
2'1
2.2

·CJ1oba1

253 pr09rAm

2"
2 ••
256 proqr.tm
\251

J2SJ
259 program
26.
261
262
263
2 ••
265
266
267
261
269
27.
271
212

dbCJ,obj
Docraf,no.ct

c

program, code

•• ection

0000

C 0000

: initbUu.tion routin••
.tartl

C 0000 'lt01Fr80

:initialize .tack pointer
IIlOV.W' •• top_ram,r7

; aet sp to top of ram

program

C 0006 38a2

program

C 0008 3880

: initialize input hand.hake and status indicators
mov.b
.h'ff,rOl
;set IBUSY active to keep
mov.b
r01 .. @p1_dr
: istb interrupts inactive
:clear LEOs
mov.b
rOl,@p1_ddr
:set port as outputs

program.
program

C DOGA 31DA
C DO DC 38B'

: initiali~8 Meaory Control Port
mov.b
rOl,lpS dr
;set WE\, CSl\, , CSO\ inactive
mov.b
r01,@pS:ddr
;set pins as outputs

proqram
273 proCJram
214 program

C ODOE 31B6

275 proqram
276
277
218 proCJram.

program

C 0004 FlFF

C 0014 3880

: initialize MeJIory Addr... Bus
mov.b
r01,1p3 dr
moy. b
1'01, epl- dr
mov. b
1'01, ep3- ddr
IllOv.b
rOl,ePI:ddr

;set ports as outputs

COOl' 3889

: init.iUlze OUtput Data Port
"
mov.b
rOl,lp'_ddr

;set port as output

C 0018 31el

: initialize Input Port Controls and Pause
IllOv.b
r01,lp'_dr
:turn-on NOS pull-Up'

C 0010 31ar
c 0012 38a4

J19
2 ••
281 program
282
283
284 program

C aOlA F8U

285 prograll C OOIC 38a1
286 program c 001& "812
proC)ram C 0020 38a5

2.,

288
2.0
20.
291
292 proljlram
293 proqram

294 pro9nm.
295 progralll
296 proqram.
297
298 program

209
300
301
302
303
304
305

0022
0024
0026
002'

FlIT
3881
1'800
79050000

c

OOZC 3883

C OOZE

program

C 002E 3086

program

C 0030 35ar

program C 0032 4B04
proqraa C 0034
program. C 0034 FlO2
pro.gram C 0036 4002

306 program
30'1 proqraJll

308
309
310
311

C
C
C
C

prograll
program
pro9ram
proCJram

C 0038
e 0031
e 003A
C 003A
C 003e
e 0031

: initiaUze JlUIJIOry buffer
mov.b
fwrite,r01
lIlov.b
r01,e_ dir
mov.b
.0,r01mov.W'
'O,rS
m.oy.b
rOl.IJl.ell_data
clear buffer;
;clear buffer location
moy.b
r51.lad.dr 10
m.ov. b
rSh, hddr-hi
bm.i
vr_csl-

WI'

312
313
31' program

e

315 proCJram
316 program
317 proCJraJD

C DOU 1501
C 004& 4416

0040 IDOl
C 0042 U&A

set buffer address a. "FFF

: initialize output Port Control.
IIlOv.b
.h'13,r01
IftOv.b
rOl,Ip4_dr
; set OlNIT\ active and OSTS\ inactive
: set port as follow.;
mov.b
.b'12,rOl
JIlOv.b
rOl,@p4_ddr
Sit 4 &8 output (OIRlT)
ait 1 &8 output COSTa\)
; Bit 0 &8 input coausy), MOB pull-Up active

11'101
31BA
'107
31BA

I

-

: set melllory data port as output
:clearing value
:buffer pointer
: set data

: .et address

lIlov.b
bra

.wrcsO,rOl
vr_cont

;write to chip 0

mov.b

fwrcsl,r'Ol

:write to chip 1

IIlOv.b
IIlOv.b
mov.b

rOl,IJIleJll etrl
''',rOlrOl,lmam_ctrl

:aetivate write pulse

cont:

; increment buffer pointer
add.b
fl. rSl
bec
clear buffer
add.b
fl,rSh
bee
clear_buffer

ode-activate write pulse

: loop until buffer cleared
: loop until buffer cleared

318

64

Section

HITACHI

5

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

H8/330

Application Note
Lilting 1· IQITIB L;[S
... H8/300 ASSEMBLBR
PROGRAM HAMS -

VER 1.1

03/20/91 08: 11: 13

PAGE

Vector Table Definition.
"Vector Table Definitions"

.hea.dinq

:88/330 Print Buffer Routine
Ir.vidan 2.0

3

•
•7
•
,.•
5

;written

bYI
TOIIl Hampton

Hitachi Amedca. Ltd.
Application Engineering

248
249
25.
251
252
253
25.
255 vector
256
257

D 0000

• output

db9.obj

• print

nocref, naset

.qlobal
.qlobal
.qlobal

start
online int,pause int,input lnt,Hnit tnt
output:int,ostb_Int,oinit_Int
-

· section

vector, data, locate-O

;vector table initialization

258
259 vector
260 vector

D 0000
D 0000 0000

.org
.data.w start

I

D 0006
D 0006 0000

.org
runi vee
.data.w Hnlt_int

;input init strobe detect

D 0008
D 0008 0000

• or;
irqO _vee
.data.w online_int

;online pushbutton detect

D OOCA

.or9
irql_vee
.d.ata.w pause_int

;paus. pushbutton detect

.org
irq2 vee
.d.ata.w input_lnt

; input strobe detect

D 0020 0000

.orq
ocia vee
.data.w output_int

: output service request

D OOU
D 0026 0000

.org
amiOa vee
· data. w ostb_Int

1 out put

D OOZC
D ooze 0000

.org
cmlla vee
· data. W oin1 t )nt

10utPUt init strobe generator

reset vector

261
262 vector
263 vector

264
265 vector
266 vector

267
26. vector
269 vector

D CODA 0000

27.
271 vector
2'12 vector

D COOC
D CODe 0000

273
274 vector

275 vector

D 0020

276
277 vector

278 vector

data strobe generator

27.
280 vector
281 vector

282
283

.end

***flflTOTAL &RROI.S
flflfluT01'AL WARNINGS

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, cA 94005-1819 • (415) 589-8300

Section

5

63

H8/330

Application Note

o ....

f--1~

dTl I,
~~; i; I
...

IRG~~'

-i-~~!

i--tt--'

.-

~
.-

K...

\

.~~

II

0 ... 0

~~\

••

__ Ii
II

"~~,

~~II

;: ;:~~ II

~~~I

::&
~-o--j".

I

I

;:n;:.: ;:::::.: 1:;:=sl~III~:::S!t
:~~::~:~ :;;ii~~;: ~~=~~",5i ~~~~~~!
u u ...... sb:!isi I~:~~:;;;~ e=::::~

I

!m!~! i !""; jj~..::..

I

H!~!~!!

~

rl~

I .~

hI. ,.'_
! .,.~

L/

~~~~~~~~~~~~I:

Ii "-1
.2

I u.
\~f---"-Io'

I

I'

Figure A-l: Schematic Diagram

62

Section

HITACHI

5

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane,.CA 9400~-1819 • (415) 589-8300

H8/330

Application Note

APPENDIX A
TABLE OF CONTENTS

Figure A-I:
Listing 1:
Listing 2:
Listing 3:
Listing 4:
Listing 5:
Listing 6:
Listing 7:
Listing 8:
Listing 9:
Listing 10:
Listing 11:

Print Buffer Schematic Diagram

Vector initialization .................................................................................................... BUFFER.LIS
Buffer initialization ........................................................................................................ START.LIS
Input strobe service routine ............................................................................................. INPUT.LIS
Output service routine ................................................................................................. OU'IPUT.US
Output data strobe service routine .............................................................................. OUT-STB.LIS
Input initialization pulse service routine ........................................................................ IN-INIT.LIS
Output initialization puise service routine ................................................................. OUT-INIT.US
"Online" pushbutton service routine ............................................................................. ONLINE.LIS
''Pause''pushbuuonserviceroutine ................................................................................ PAUSE.LIS
Print buffer design equates .......................................................................................... BUFFER.INC
H8/330equates ............................................................................................................... H8330.INC

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

5

61

HS/330

Application Note

Set IBUSY
active

This routine executes whenever the "Pause" pushbutton is
pressed. Whenever this button is pressed. an interrupt
request is generated that allows the software to control the
ability of the print buffer to output any input data to the
printer. This would be very similar to having pressed the
"Online" pushbutton at the printer itself.

PAUSE PuSHBUTION SERVICE ROUTINE

If the print buffer output is currently active when this
pushbutton is pressed. then this routine will make it
inactive. This is done by setting the "output hold" status
flag and disabling input watchdog interrupts.
Yea

If the print buffer output is currently inactive when this
pushbutton is pressed. then this routine will make itacti ve.
This is done by resetting the "output hold" status flag and
enabling input watchdog interrupts. Foraflow chartofthis
service routine. refer to Figure 9.
Yea

CONCLUSION
While this example does not use all of the peripheral
features of the H8/330. it does provide examples of
progranuning for both timers and I/O pons. as well as
features of the individual I/O ports. Also included are
methods for initializing the interrupts structure of the H8/
330. Enhancements can most cenainly be made to this
example by doing some rearranging of the I/O ponchoices.
A serial input or output option canbe made by using the onchip SCI and moving the memory buffer control functions
to another I/O port. Morememorycould be added by using
more I/O bits from another pan to expand the address field.
This would also required a little extra address manipulation in determining buffer conditions. but it is achievable.

No

Set Hold
LED

Clea, Hold
LED

Set Hold
Status

Clea, Hold
Itatus

DI8abie

Delay T I"",
Interrupts

Enable

Delay T I"",
Interrupts

Clea' IBUSY

.1\7101

Figure 9: Pause Pushbutton Service Routine

60

Section

HITACHI

5

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

H8/330

Application Note

ONLINE PuSHBUTfON SERVICE ROUTINE

This routine executes whenever the "Online" pushbutton is
pressed. Whenever this button is pressed. an interruptrequest
is generated that allows the software to control the ability of
the print buffer to accept any input data. To inhibit input
interrupts from being requested. the IB USY signal is set active
during the processing of this routine.

Set Input
POI t Busy

If the print buffer is currently online when this pushbutton is
pressed. then this routine will take it off-line. This is done by
resetting the "online" status flag and disabling input strobe
interrupts. The ISTB interrupt itself is disabled as well as the
IBUSY signal left active so that the sending device has an
indication that the buffer is now "off-line."
If the print buffer is currentl y off-line when this pushbutton is
pressed. then this routine will take it online. This is done by
setting the "online" status flag and enabling input strobe
interrupts. The ISTB interrupt itself is enabled as
well as the IBUSY signal made inactive so that the
sending device has an indication that the buffer is
now "online." For a flow chart of ibis service
routine. refer to Figure 8.

Clear
O1llne LED

Set O1llne

LeO

Set Oliine
StOtUi

Clear Input
Por t Busy

Clear
O1llne
status

Return

Figure 8: Online Pushbutton Service Routine

HITACHI
Hitachi America, Ltd .." San Francisco Center" 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 " (415) 589-8300

Section

5

59

HS/330

Application Note

accept such data. If no data is in the buffer or the printer is not
ready to accept the buffered data, this routine merely resets the
input watchdog timer and checks to determine if the IBUSY.
signal should be activated before returning to the main program.

(thus generating no more strobes). Execution then returns to
the data output service routine. For a flow chart of this service
routine, refer to Figure 5.

lNPur INIT PULSE
SERVICE ROUTINE

If there is data in the buffer and the printer is ready to accept
the data, then this routine goes through the process of getting
the data from the buffer and sending it to the output parallel
port. In getting the data from the memory buffer, this routine
must change the direction of the memory buffer's data bus to
be input as well as set the address bus with the output data
pointer. The proper CS signal is then generated in order to
"read" the data to be output. That data is moved to the output
parallel port and the multi-function timer that generates the
output strobe (O'STII) is enabled. The H8/330 then goes to
"sleep" until the output strobe interrupt occurs:
After returning from the output strobe interrupt routine, the
data output service routine has to determine whether or not the
memory buffer is in a either the "empty" or "full" condition.
If the bufferis in the empty condition, then this routine sets the
"buffer empty" flag, deactivates the IBUSY signal, and resets
the input watchdog timer in completing its operations. If the
buffer is not "empty," then this routine must determine
whether.or not the bufferis in the "full" condition. If the buffer
is in a "full" condition, then this routine just resets the input
watchdog timer and completes
its service with the IBUSY signal
still being set. If the buffer is not
in the "full" condition, then the
routine clears the "buffer full"
flag, deactivates the IBUSY signal, and resets the input watchDisable
dog timer in completing its opCSTB\
Inter rupls
erations.

OUTPur STROBE SERVICE
ROUTINE

Clear Flags

During the execution of the data
output service routine, one of the,
8-bit multi-function tirners is programmed to generate the
signal, and also an interrupt on
the trailing edge of that strobe.
During this service routine, this
timer is programmed not to generate any more interrupts and also
to keep its output at a high level

asm

Disable

CUtpul
ChTa\la

Disable
further
T Irrer
Inter rupts

JlIlP to
very

~~Om~

Figure 6: IImT Pul~e
Service Routine

OUTPur INIT Puu>E
SERVICE ROUTINE

During the execution of the main
routine, one of the 8-bit multifunction timers is programmed
to generate the OINIT signal, and
also an interrupt on the trailing
edge of that strobe. During this
service routine, this timer is programmednotto generate anymore
interrupts and also to keep its
output at a high level (thus generatingno more strobes). Theroutine also clears the "oinit" status
bit so that the main routine can
complete it operation. For a flow
chart of this service routine, refer
to Figure 7.

FigureS: Output Strobe
Service Routine

58

The input mIT pulse (IINIT)
signal is connected directly to
the m;rr input of the H8/330.
Wheneverthe sending device sets
this signal active, the print buffer
will disable all timers from generating any of their interrupts. It
then restarts the software just as
if the reset pushbutton had been
pressed. This allows the sending
device to control the reset of the
buffer and printer through its
hardware signal. It does not interfere with any software reset
commands sent directly to the
printer. For a flow chart of this
service routine, refer to Figure 6.

Disable
further

OINIT\
pulse

Interrupts

CI ear t I rrer
flags

Clear OINIT
control
flag

Figure 7: OINIT Pulse
Service Routine

Section

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H8/330

Application Note

Set Irwt
Bus y SIIJlOI

Ves

Ves

9!t ClJtput
Data

Ves

ClJtput Data

Gl!ner ate
ClJtputData
Strobe

Oeor IBUSV

Slg10l

Ves

~~---I

Oeor

Buffer Full
FLCQ

Reset Input
Del CII Tiner

Set Buffer
Enpty FICQ

RETl.IlN

Figure 4: Data Output Service Routine

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Section

5

57

H8/330

Application Note
Now we can enable the second 8-bit multi-function timer to
generate the OINIT signal and also the interrupts. Here we
wait in a loop until the "oinit" status bit has been cleared to
indicate that the pulse has occurred. Now we clear out the
IB USY signal so that input data strobes can occur,and set the
status indicators to show that the print buffer is "online" and
"ready."

Set I nPJt
B16Y S IIJlOI

The last thing we do in the main routine is to enable the input
watchdog timer so that its interrupts can be generated.
DATA INPUf SERVICE ROUTINE

Racxl D::Ita

The input data strobe (lSTB) is input to the H8/330 as the
lowest level maskable interrupt. Whenever the falling edge of
the ISTB signal is detected, the H8/330 goes through the
process of inputting data from the parallel pon and placing
into the print buffer. For a flow chan of this service routine,
refer to Figure 3. In order to keep further ISTB interrupts from
occurring.before the print buffer is ready to accept them, this
routine first sets the IB USY signal active before it can do
anything else. It then goes through the process of getting the
data and writing it to the memory buffer.

Place D::Ita
Into Mnory
Butler

Yeti

Clear
Buffin
Enpty Flag

Set Buffer
Full Flag

Clear InPJt
Bus y S IIJlOI

Turn 01
Buffer Full
Status

A separate pointer is maintained for the input position of the
buffer. This position is checked against the output data pointer
to determine when the b¢'feris to full to accept any more data.
As long as the buffer is not full, the "buffer empty" flag is
cleared, the input watchdog timer is reset, and the IBUSY
signal is deactivated. This would complete this service routine. If the memory buffer is determined to be full, then the
"buffer full" flag is set, the "Buffer Full" status indicator is
"turned on," and the service routine completes with the
IBUSY signal remaining active after resetting the input
watchdog timer. This inhibits further input strobe interrupts
from occurring until the buffer has been emptied of some of
its data.
DATA OUTPUf SERVICE ROUTINE

Retlet DeIC7f
T IlT8r

Figure 3: Data Input Service Routine

56

One of the timers is initialized such that it will generate an
interrupt to the H8/330 if no input or output activity takes
place within 100 Jlsec. Both the data input and data output
service routines reset this counter in order to keep both
activities going. For a flow chart of this service routine, refer
to Figure 4. To ensure thatno input data requests are generated
while the output service is taking place, this routine also sets
the IBUSY signal active immediately.
Since a timer generated this request rather the printer itself,
this routine must determine whetherornot there is data in the
buffer to be output and whether or not the printer is ready to

Section

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88/330

Application Note
could possi~be ~sted before the H8/330 is initialized
[except for NMI (UNIT), which performs the same function
as a reset] , wecannow go about the business ofinitializing the
H8/330 without worrying about missing a request for buffering.

certain that theprinteritself gets reset) and to enable theMOS

pull-up on the OBUSY signal. To do this we programthe data
,egisteroftheport with the value H'13 before programming .
the direction of the port. For setting up bits 4 and 1 as outputs
while bit 0 is an input, we must program the direction register
with the value H'12.

At this point, we go through the process of initializing all of
the I/O ports for proper usage. Since all of the I/O ports of the
H8/330 are initialized as input ports at reset, we must go
through each port and setup both direction and functions.

At this point in the main routine we finally come to where we
get to use the I/O ports for controlling the memory buffer. We
use this opportunity to clear the memory buffer contents. In
performing this operation, we must rust set the I/O port used
for the data bus to the output direction. We can then setup the
ports used for the memory address witha valid address as well
as the data port with the clearing value to be written. Next we
write to the I/Oportused forthe control signals to activate the
WE and correct CS signal. Since were are using different
instructions to set and clear these bits, we can immediately
deactivate the signals after baving activated them. This
sequence provides plenty of time forproperSRAM operation.
This function is positioned inside a loop that executes until the
entire buffer has been cleared.

I/OPort 1is used for two functions; status indication and input
busy(IBUSy) signalconttol. All of these signals are outputs.
The initial status for outputs on this port should be all high.
This "turns" the LEOs off and sets the IBUSY signal active.
Toensurethstthisbappensassoonastheportisprogrammed
foroutputfunctioD. we write to the dataregisterpriorto setting
the direction.
The secondsetofports we initialize are for thememorybuffer.

In order to make sure that the memory is inactive when we

programtheports,wewritetothel/O~rt(portS)usedforthe

conttol signals to make the WE and CS signals inactive when
the direction is changed to outputs. We are then able to
program the I/O ports to be used as the address bus. Both of
these ports (port 3 and Port 8) are to be used as outputs. The
only other port used in connection with the memory buffer is
for data ilccess. Since this port will be used bidirectionally, the
direction will be programmed as we need to use iL
We can now program the ports that we intend to use for the
parallel input and output ports. Since we have chosen Port 7
for the input port, no direction programming is necessary
because Port 7 is input only anyway. Port 6 is used for the
output parallel portso its direction must be changed. Port 9 is
used for control over both the input and output parallel ports.
The signals involved here are the input strobe (lSTB) and the
two control panel switches for online and output hold. Since
all three of these signals are inputs, no direction change is
required. We can, however, use the internal MOS pull~up
featureoftheportsothatextemalresistorsarenotneeded. To
control this feature, we can write to the port data register with
".1s"to enable the pull-ups (this feature is available only with
port bits that are inputs).
Port4 is used for conttol signals directly affecting the output
parallelporL These signals include the output strobe (OSTB),
output busy (OBUSy), and output initialization (OINIT).
Since the OBUSYsignal is an input while the other two signals
are outputs, we must program this port for a mixture of input
and output lines. Initially, we would like to ensure that the
OSTB signal is inactive while the OINIT is active (to make

.
We are now at a position where we can set the program
constants and operation flags, as well as initializing the timers
for their uses. The 16-bit free-running timer is used for
watching input activity. This timer is programmed to generate
aninterruptevery IOOpsec,butthisoccursonlyifitisnotreset
in a service routine. One of the 8-bit multi-function timers is
used to generate the output data strobe. This timer is programmed to generate a negative-going strobe that is 2.4)lSec
in width, and an interrupt on the trailing edge of that pulse.
Since we don't want to generate the strobe at this time, the
timer output is programmed to remain at a high level with no ~
interrupts generated. We control the output level during the i=
output service routine. The second 8-bit multi-function timer @
is used to generate the output initialization (OINIT) pulse. en
This timeris programmed to generateanegative-goingstrobe
that is 40 )lSec in width, and an interrupt on the trailing edge
of that pulse. Again, wedonotwish to generate the strobe right
now so the timer output is programmed to remain at a high
level withno interrupts generated. We will generate the strobe
right after we initialize the interrupt structure.

1:1

The interrupt structure must be setup to handle three (3)
external interrupts and also for those extema1 interrupts
generated by the falling edge of a signal. For the external
interrupts, this is accomplished byprogrammingthe Interrupt
Sense Control Register (ISCR) for edge selection prior to
programming the InterruptEnable Register (IER). The interrupt mask is then released in the Condition Codes Register
(CCR) of the H8/330 in order to enable all interrupts.

HITACHI
Hitachi America, Ltd.' San.Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Section

5

55

HS/330

Application Note

STPm

1
Set Top of
Stack

1
Set Input
Busy

1
Clear
Status
I ndlootors

1
Inl t lallze
Mrrory
Address and
Olntrol
Ports

1
Initialize

1"1
Inl tlollze
OJtput Port
Olntrols

1
Inl tallze
Mrrory
Buffer

1
Inl tlollze
Buffer
Pointers

1
Inl tlallze

~ov:r.ar.

and Flags

1

!

!

Initialize
INIT Pulse
Galerator

Ermle
Del Of T I mlr

Encble INIT
Pulse
Gherator

L

INIT
Pulse Olne
?

N:>

Yes

~

~

~

Inl tlallze
Input Port
Olntrols

Inl tlallze
OJtput
strebe
Gherator

L

SLEEP

J

Encble
I-Ia1c1!haklng

I

!-

Initialize
Interrupt
Structure

Inl tlallze
Input De.IOf
T Imlr

OJt~~tDJta

L

1

Set Status
I ndl ootors

L

Figure 2: Main Routine

54

Section

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HS/330

Application Note
Three of the on-chip timers are used for strobe generation and
event monitoring. One of the 8-bit multi-function timers is
used to generate an output data strobe whilethesecondmultifunction timer is used to generate an output printer initialization strobe. Since the multi-function timers can control both
of these oUlputs directly, Port4 was used forthis function. The
16-bit free-running timer is used for event monitoring; its
function is basically that of a watchdog timer. This timer is
started and allowed toruncontinuousiyuntil aninput service
is requested. During the service of the inputinterruptrequest,
this1imer is reseL If the timer is allowed to overflow, then the
software assumes that there was no input activity and will
check to determine if any output service can be performed.
This timer is also reset during the output service routine. The
interruptgeneratedbythis timerisusedintemallyonlyandnot
brought out to the rest of the system.
MEMORY

all the external interrupt routines, but does take precedence over all internal interrupts.
3. The output service routine is responsible for placing
data from themetnory buffer out to the output port. This
routine is allowed to occur only when no other higher
priority activity (IINIT, ISTB, or control panel switch
press) has requested service within 100 psec. This
routine is also responsible for generating the output data
strobe (OSTB).
4. Theoutputstrobeserviceroutinetakescareofdisabling
the multi-function timer from generating further output
strobes (mB) as requested by the output service
routine.
5. Theinputinitialization(IINIT)serviceroutineprovides
a means by which the sending device can reset the print
buffer as well as the printer connected to iL This
includes generation of an output initialization strobe
(OIm't) as well as initializing the print buffer

8\J1i11ER

The interface to the memory buffer requires fifteen (15) lines
for address (32K.),eight(8) lines for data access, two (2) lines
for chip selectiOll,andone (1) line for write control. Since the
metDOry devices draw the tDOst power when they are chip
selected, it was unnecessary to use an I/O line to control the
output enables. 1beselines wereleft tied to ground so that they
. would always be active.ln this manner, the chip select (CS,.)
signal activate the appropriate memory device and keep
power consumption to a minimum. IjOPort 5 happens to be
a 3-bit port and is ideal for use for the three control signals. .

6. The initialization strobe routine takes care of disabling
the multi-function timer from generating further output
initialization strobes (OlNIT) as requested by the input
initialization service routine.
7. The online pushbutton service routine monitors an
external switch which allows the user control over
whether or not to allow data to be input to the Print
buffer. This performs a function similar to a printer's
"online" switch.

Since Port 8 is already a 7-bit port, it was convenient to use it
for the most significant portion (MA I4 -MAl) of the address
bus. Two more 8-bitpOrts arerequired to complete the address
bus as well as the data access bus. Since only two full 8-bit
ports remained, we used Port 2 for the data bus (MD,-MDJ
and Port 3 for the least significant byte (MA,-MAJ of the
address bus.

SOFfWARE
The print buffer software basically consists of eight separate
routines.
1. The main routine performs initialization of the I/O

ports, timers, and the metDOry buffer as well as the
generation of an initialization pulse for the printer
.
attached to the buffer.
2. The input strobe (ISTB) service routine is responsible
for placing data from the input data port into the
memory buffer. This routine has the lowest priority of

~

8. The pause pus
.. hbutton service routine als.o tDOnitor an
external switch. This routine allows the user control &:l
over allowing the data in the memory buffer to beoulput CI)
to the printer. This would be useful in instances where
the printer's "online" switch might not be readily'
accessible.
Complete source listings for each routine, as well as supporting files, can be foundin Appendix A.

MAIN RoUTINE
This routine performs the function of initializing the print
buffer for operation. For a flow chart of its sequence, please
refer to Figure 2. Inorder to prevent any interrupts frombeing
requested by the input port, the main routine sets the !BUSY
signal active. By setting this signal active, the sending device
is inhibited from generating any strobe ~) signals to the
print buffer. Since the ISTB interruptis the only interrupt that

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Section

5

53

m

H8/330

Application Note

DESIGN CONSIDERATIONS
One ofthe main considerations in the demo design was to keep

the parts count to a minimum. This meant that we wouldhave
to use the features of the H8/330 whereverpossibleratherthan
an external device. A simple block diagram of the print buffer
is shown in Figure 1.
The required parts had to consist of the H8/330 and some
memory chips. We chose to use two (2) HM62256 SRAMs
(32Kx8) to provide us witha 64Kbyte buffer. In order to clean
up the power-on reset circuitry, we chose to add a 74HC14
although it probably wasn't necessary. This kept our parts
count to only four ICs.

We also wanted to have some control over the operationofthis
print buffer. For this reason, three (3) switches were added to
provideforanexternalreset,ameansoftakingthebuffer"offline" Gust as if it were a printer), and a means of halting the
buffer's output. We also wanted to have an indication of this
control, so four(4) LEDs were added to indicate the status of
the buffer.
You will fmd acomplete schematic of the H8/330PrintBuffer
in Appendix A (Figure A-I). You may want to refer to this
1/
schematic as we discuss our decisions for devices and
o port usage.

I/O PORT USAGE
In the expanded modes of operation, the H8/330 has the
capabilityofdirectlyaddressingextemalmemorythroughthe
use of twenty-seven (27) of its I/O lines. We could have used
one of these modes of operation, but that would limit the size
of our storage buffer to considerably less than 64K bytes.
Also, in these modes of operation, the only two ports on the
H8/330 that have the capability to drive LEOs directly also
serveas theexternaladdress bus. Inordernot torequire theuse
of an external device to drive LEOs, and also to allow a large
storage buffer (we chose 64K bytes for simplicity), the singlechip mode of operation was used. This forces us to use
individual I/O ports to control buffers addressing, memory
control, and data access. We are, however, not losing the use
of any I/O lines because of this.
STAres DISPLAY

In this design, we have four (4) LEOs that are used to display
the status of the print buffer. These status indicators include
Ready,On1ine,BufferFull,andOulputHold.Sinceonlyports
1 and 2 have the capability of driving LEOs directly, neither
could be used to address the extepJal memory buffer. Port 1

52

was chosen to indicate the status.
CONTROL PANEL

Also in this design, we have two (2) switches which are used
to provide user control over the actions of the print buffer.
These two switches allow the user to halt (or restart) the
buffer's output, and take the print buffer on-line or off-line.
Since continual polling of these switches would take too much
time out of the spooling action, it was decided to use external
interrupts as the switch inputs. This meant that Port 9 would
be used for this function. I was also convenient since Port 9has
internal MOS pull-up resistors, thus keeping with our constraint of minimizing the parts counts.
The third switch ofthe control panel controls a hardware reset
to the print buffer in the event that the user wishes to reset the
buffer during its normal operation.
PARALLEL

lNPur AND OUTPUr

Since this print buffer is parallel-in and parallel-out, three (3)
8-bit ports are required to allow for this interface (data plus
handshake). The AID converter of the H8/330 is not being
utilized for this application so I/O Port 7 is ideal for the parallel
input port (since it happens to be an input only port anyway).
Also, since no other external interrupts are required and the
free-running timer interrupt is internal only, I/O Port 6 is an
ideal selection for the parallel output port.
Additionally, three control signals (mIT, STB. and BUSy)
from both the input and output ports are necessary for proper
operation.
The INIT strobe (IINIT) from the input port is fed directly to
the NMI input of the H8/330. When the personal computer
generates this strobe, it is an indication that the system
hardware wishes to reset theprinter. Forthisreason, this event
takes precedence over all others. When this occurs, the print
buffer will generate anlNITpulse (OINIT) forthe output port
to reset the printer. This pulse is also generated during the
initialization sequence of the print buffer.
The input STB signal (ISTB) is accepted as a maskable
interrupt to Port 9. This strobe has the lowest priority of all
maskable external interrupts 'in order to ensure that the
initialization pulse and the switch press interrupts take precedence. This event causes the generation of the input BUSY
signal (IBUSY) sothatno other input STBs canoccuruntil the
data is properly buffered.

Section

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March, 1991

H8/330
Application Note

Parallel-to-Parallel Print Butter Controller

Tom Hampton

INTRODUCTION
TheHD6473308 (H8/330) is a highly integrated 8-bitmicrocomputinguniLAlongwithacentralprocessingunitutilizing
a reduced instruction set designed for speed, the H8/330
incorporates several system peripheral devices and memory
onto a singlechip. Theseon-chip functions include 16K bytes
of ROM or EPROM,S 12 bytesofRAM,ls bytes of dual-port
RAM,stimers,aUARTchannel,8channelsofA/Dconversion, and 91/0 Ports.
These features allow the H8/330 to be used inmany applications; a print buffer is merely one of the vast possibilities. In
this application. we are able to examine the usage of several
of the on-chip peripherals as well as I/O ports and interrupt
control. While this application does notuse all of the peripheral features of the H8/330, it does provide programming
examples formanyoftheperipherals as well as the CPU itself.
Three of the on-chip timers are used to control sucbevents as

tion, and also for event monitoring. This is accomplished
through the exceptionprocessingfeaturCs of the H8/330. Four
external interrupts are utilized to monitor input data strobes,
input initialization strobes, and pushbutton (control panel)
events.
In order to maximize the external memory addressing capabilities for this application. the H8/330 device is used in the
single-chip mode of operation. In this mode,many of the I/O
ports are used to control the memory bufferitselfas well as for
status displays. One of the I/O ports is even used for a
bidirectional data bus even though the H8/330 does not have
that feature directly.

Even though this application uses very littleon-chipmemory
(less than 512 bytes of ROM and less than 20 bytes ofRAM),
the on-<:hipmemory capabilities of the HS/330provide enough
room for code anddata storage required by most applications.

strobe generation for both output data and printer initializa-

--

• @• @• •
@

Ready

:::J

a.
:::J

0

Pause

Online

Buffer
Full

Reset

H8/330

BB

:::J

a.
c:

Figure 1: Buffer Block Diagram

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Hitachi America, Ltd.· San Francisco Genter· 2000 Sierra Point Pkwy.· Brisbane, GA 94005-1819 • (415) 589-8300
/

Section

5

51

50

Section

HITACHI

5

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

H8/300 Family

Application Note
Lilting 1· Ux1fi Mpl.Upl.y RQUti,M
... HI/300 ASSBMBLBR
PROGRAM NAIll •

VEa 1.1"·

.ACE

05/01/91 12: 20: 11

:81/300 CPU 16x16 Multiply Routine

1
2
3
4
5

;Thb routine u ••• strictly r&q:hten to maintain all

,stora,e facUitie. and for

,
•,

c.lculat~on.

,R8ghter V1oI.9_

7

:lntrYI

Rl - Multiplier
HZ • Nult1pUcand

10

11

,

12

,&xitl

13
14
15
16
17

a3,.4 - T_porary a ..ult
as - Temporary ston;.
al - . . .ult. LSW
R2 -

auuu,

MS"

;Pictorial D••cdption:
R2R
RIR

,18

R2L
RIL

10
20
21
22
23
24
25
26
27 •

28.
20.
30
31 •
32 •
33

...

R2L"RlR
R2R"RIR
"'-RBSULT--

C 0000
C 0000 19040000

e

lftult16:

stepl;

C 0006 5092

atep2:

lBulxQ

JIOv.v

CODal aDZ3

r2,1'5

1 clear

1'8sult reqister
: .. ve Alultiplicand

r11,1'2
r2.r3

,1.

10,1'4

0004 OD2S

Jlftultiplier(L) X mUltiplicand(L)
R3 <- R2L*RIL

C DaDA OCSA

step31

JIOv.b

rSh,r21

: retrieve multiplicand (H)

e oooe 5092
e OOOB 01Al
C 0010 012e

step':

IllUlxu
add.b
addx

1'11.1'2
r2l, r3h
1'2h,r41

:m.ultipl1arCL) x JIIultiplicancl(H)
R3H <- R3H + (R2H*RlL)L
R4L <- (R2H*RIL}H + CY

35

36.
37 •
31 •

,2.

30
e 0012 OD52

stepS;

mov.v

1'5,1'2

: retrieve multiplicand

42.
43.

C 0014 5012
C 0016 003

stepll

IllUlxu
add.b

U.

e 0011 012e
e 001A '400

aclclx
aclclx

1'1h,r2
r2l,1'3h
1'2h,r41
to,r4h

:Ja.ultiplier(H)
R3H <:3.
R4L 
0
0

o

-~

..

'-

r----;

LCW INTERFACE

00

,~.,~

---I~·-·-----:-

1989

EV668-

~

I~Y

~
:r

=
[
t:I:I
.,.

.~

~g

~

SECTION

I!I

EV66841

Technical Brief

Q

.

U

.

.
r--

i

~

."

.

.,

~,;i

!

u - ..

"'!~

~-:.,

:c

1:::
!i

::!l

--

;

.,
......

.. i~
. .,,-...-- . r· .
~ ..
'"'"
IL

:::

.

:a
u
...J
0

~.

,

III

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819 • (415) 589-8300

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Hitachi America, Ltd,' San Francisco Center' 2000 Sierra Point Pkwy,' Brisbane, CA 94005-1819 • (415) 589-8300

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Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy. ~ Brisbane, CA 94005-1819 • (415) 589-8300

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Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589.8300

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Hitachi America, Ltd.' San Francisco Center. 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819 • (415) 589-8300

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EV66841

Technical Brief
APPENDIX " B "
Back light power cable" C3 " is shown in this Appendix :

EV66841 LVIC EVAL BOARD

1

2

14, •

6.3" TFT COLOR DISPLAY

3 4

•

I CON 2

G::u
GND

BLK

+12V

RED

" C3"

NOTE: Back light power is to be externally supplied.

Section

HITACHI

4

Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

178

I

EV66841

Technical Brief

APPENDIX " A "
The 9 pin video cable " C1 " translation is shown below :
( EV66841 )
~C~R~T~-------------------------------1'. BOARD _

" Cl "

Pin 1

Pin 1

Pin 2

Pin 2

Pin 3

Pin 3

Pin 4

Pin 4

Pin S

Pin S

Pin 6

Pin 6

Pin 7

Pin 7

Pin 8

Pin 8

Pin 9

Pin 9

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4177

;1]

EV66841

Technical Brief

HIT ACHI COLOR LCD TFf MODULE (TM16DOIHC) :
Refer to the display data sheet for detail. The page 14 of it shows how the sub-pixels are designated for L VIC
HD66841 interface with 160 dots (H) and 200 dots (V) resolution. The cable" C2 " provides the signals to
the display while cable "C3 "provides the back light power. The dispaly tilt and swivel angles provide different
contrast ratios in the ambient light, so it should be adjusted for the most desirable viewing angle.

SYSTEM DEBUG
First power up the system in CGA mode using the AMDEK color monitor and the EGA board effectively
disconnecting the 6.3" TFT LCD display and reconnecting the cable" Cl " to the monitor. After the system
is up in CGA mode, varify that it works correctly. Then, disconnect the cable" Cl " and connect it to the
EV66841 board input. Also, varify that the cable" C2 "is properly connected to the display, since there is
no key in the connector. If cable" C3 " is properly connected, back florescent light should come on and it is
clearly visible.
If every thing is working correctly, one can execute all the DOS commands when appropriate prompts are
displayed on the LCD screen.

NOTE:
If the LCD screen is split and shows unreadable data, then disconnect and reconnect the cable" C2 " to the
color TFT display when the power is on. This dynamic reset should cause the correct data to be displayed.

DEMONSTRATION SOFfWARE
After DOS 3.2 or later is installed, load any CGA graphics package such as PRINTS HOP or file management
package XTREE for the video color display. With EV66841 evaluation board in the system, the color video
display will be replaced by the color TFT LCD display. Both, XTREE and PRINTSHOP were used for the
system display demonstration. By running Kaleidoscope 1, differrent colored dot patterns can be shown on
the LCD screen. When Kaleidoscope 2 is run, various colored geometric patterns are displayed on the screen.
For scanned color image files (*.GIF) for display, call Hitachi America Ltd., office at Sierra Point. CA.

Section

H ITACH I

4

Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

176

EV66841

Technical Brief

1.0 SWITCH" 0 ": It is set for digital input.

pos

---4

2

3

1

L~
ON

I

2.0 SWITCH" 1 ": This is set for LYIC mode" 13H ".

- -

3.0 SWITCH "2 "

1

2

3

4

POS

OFF
ON

Set for CGA mode and 200 vertical lines.

- - - -

e

poa

5

4

2

3

ilJ

1

OFF

ON

4.0 SWITCH" 3" : Dynamic fuctions saettings - 25 MHz and regenerated dot clock.

pas

8

7

e

5

4

3

2

1

----- - --

OFF

ON

NOTE : 1.0 Make sure that cable" Cl " is corectly connected at the display side. There is no cable key.
2.0 The attached schematic is only for reference so do not copy it for your design.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4175

EV66841

Technical Brief

SYSTEM COMPONENTS
The hardware components are described in this section while the" C1 ", and " C2 " cable wiring diagrams are
shown in the Appendices.
PC-AT: ASTPremium 286 model 70 was operating at 10 MHZ, with 512KB memory, 20MB hard disk drive,
and 1.2 MB, 5.25 " floppy drive. It was also running DOS version 3.2.
VIDEO CONTROLLER: Paradise Autoswitch EGA is card used in the CGA mode at (640H x 200V)
resolution providing TIL level signals to the CRT monitor. The switch settings for 80 column, RGB monitor
in CGA mode are listed below:
-

poe

---- -6

5

4

3

2

1

OflF
ON

NOTE: 1.0 For more details refer to the Paradise CRT controller manual.
2.0 Make sure this switch is correctly set.

EV66841 LVIC EVALUATION BOARD
This board has numerous switches and its settings are complex. So, please refer to the EV66841 User's Guide
for details. Only the 6.3" TFT LCD switch settings are addressed in this section.
The EV66841 board accepts TIL level input signals carried by the 9 pin cable" C1 " from the video controller
board. The R,G,B, HSYNC, and VSYNC signals are used to regenerate the CRT dot clock, and sample the
incoming video data. The output signals are sent over the cable" C2 " to the 6.3" TFT, 8 colors, Hitachi display.
This board also provides +12 Volts required by the back light through the cable" C3 ". The switch settings
of this board are shown on the following page:

Section

HITACHI

4

Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

174

---

------------

EV66841

Technical Brief

SYSTEM CONFIGURATION

The development system was configured with IBM PC-AT or compatible machine; Paradise Autoswitch EGA
480 card, EV66841 LVIC Evaluation Board, Smartscan Amdek 735 digital color monitor, and Hitachi TFf
active matrix, 8 color, 6.3", LCD display TM16DOIHC from the ELT division. A custom cable is required
to provide TIL level input video signals to the EV66841 board and is not provided. The LVIC Evaluation'
board output connector to the 6.3" TFf display is provided to make the display connection task easier. A
separate +12V DC cable is also required for the back light option (#BLS-006M). The back light is easily
mounted with the four corner screws of the 6.3" TFf display.
The system diagram is shown below:

.

\.
I

I

I"\olII3B4 I
LVIC
I:VALUA IIU N

CIII
(.,VN I HOLLl:ll

I

TTl

nAr.-K I I G liT
OPTION
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......................................... " " - -• C-1-"- - - '
a.s" II- I
I)I~I'IJW

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"c.:;>.

NOTE:

1.0 ,. Cl ,. = ,. C3 ,. = Cables not provided.
2.0 ,. C2" Cable provided.

HITACHI
Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300

Section

4

173

March, 1991

EV66841
Technical Brief

LVIC Evaluation Board

Kash Yajnik

The EV66841 LYlC Evaluation Board was designed by
Eurodesc, Hitachi Europe Ltd., and can be ordered through
liitachi America Ltd. in U.S.A. The board is shipped with
cables for multiple Liquid Crystal Modules from Hitachi.

provide the design implementation detail. A system diagram
is also included to high light the laboratory environment.
Similarly, each user may tailor display subsystem requirements for the desired application.

Black and white as well as color information can be displayed
depending upon the selected LCD panel from Hitachi's ELT
Division. The EV6684 I LVIC Evaluation Board can reside
inside IBM PC-AT or a compatible system running later than
DOS version 2.0. It is also possible to run the EV66841 Board
with external power supply. A User's Guide is also provided
to customize the board for many applications.

The scope of this document is to help make the customization
task easier and quicker. The circuit minimization tasks are left
to each user and are not attempted. This is intended as an
illustrative example for the Hitachi field and technical staff,
and their customers.

This technical brief is written to complement the EV6684 I
User's Guide for ODe specific application using the 6.3" color
TFr module (TM16DOIHC) from Hitachi's Electron Tube
Division (ELT). A copy of the schematic is also included to

The following pages cover system configuration and componenents, EV66841 Board set up, System debug, and Demonstration software. The Appendix" A" covers 9pin Video cable
translation and the Appendix "B" shows the Back light power
connections. The Appendix "C" lists the schematic.
Refer to the subsequent pages for more detail.

Section
172 4

HITACHI
Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300

HD66841 / LMGS060

Technical Brief

LVle Proto Type Board
'Ibis document presents information for a 6.3" color active matrix or black and white LCD subsystem implementation using Hitachi
controller HD6684I. Its major components include IBM PC-AT, LVIC Proto Type Board, Paradise or Oak Video Controller Board,
and the LCD display (TMI6DOIHC or LMGS060XUFC ) from Hitachi's ELT Division. It can be further enhanced by adding
demonstration software that runs on the mM PC-AT or a compatible machine.

•

FEATURES.

--Hardware-(1) mM PC-AT or compatible machine
(2) HD66841 LYlC Proto Type Board from Hitachi
(3) Color LCD Active Matrix or Black and White display from Hitachi with Back Light
(4) Paradise or Oak Video Controller Board
.
--Software(I) DOS 3.2 Version or later
(2) "XTREE", WINDOWS, or PRINTSHOP package
(3) Any CGA color or VGA demonsttation package
(4) • .GIF files for color LCD or VGA type panel display

•

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(2) To demonstrate 8 colors or 8 shades of grey on LCD panel

(3) To show application software running on the HD66841 LYlC Proto Type Board
(4) To high light PC-AT Bus Interface

•

ADDmONAL INFORMATION

'Ibedetails of the system configuration and its design along with the associated software, are available in the Hitachi
·America Ltd. Technical Brief #TBOI03.

HITACHI
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'<~ It~ u z a: Section 1664 CD u CJ u.. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 HD66841 / LMG5060 Technical Brief 0 ~ a: 0 a: ..J ..J U '"0 ~ ~ ..J 0 := ~ Z 0 tIl u Kl:l1001 .. '"'"~ ..J ~ '" "'JIOa ..! .-•. 0 > ~ ;; ,"1 "II • CL C OL -, •• .: C_ .'",.. ...•. C> ;;: :: a: ~ .... .. a ~ z c": 0-' ~ ...c L C> .... + .!z~ ..."'.:; ~ . co", 1ft ~ 'V • c-a •• ;: O • • a.. •• ac:c 2~ 0 0 .. L~N :c ---- .. '"'" .; .~ 0:0:: 0 __ "'DLa 0"110. c.......,-. VI =" • • • • . . . a..&.;) • c _ •• >••• ......... '" C-L..Ia:: • 2 .~ ... or:oo-' .... ....,. ....a:::a:a ... CICIC ...... ........ 0 . . . . . a:c\ICIt-_u_ :0:::0::0 III .. ZO .. a: . . ~ ::> a: a: :c u a:-- Z-c Vf""L.I-c.:ILCI "' .....c.D::SI'CIt.NU vwm:r-ca::l =trto--,.,J-CI :I'tI.U> .... UZ ,...~ZLZ;- -'----~'UI"'" '" a:: II: lC III a:: a: u o HITACHI Hitachi America, Ltd,' San Francisco Center" 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 u.. Section 4165 lEI ~ rn "I (") :r. :» ,. . A I '\ __ 5 L_ '.• .....,~ nsuc U218 +SY -,-- 3 ~ REO ";' P' !::;: OJ il ~ '"~ ,oo ~'Llt---+------+---~--~ " (") (ii' C") CD :::l 0 "" 0 ~J: !~ ~,O ~ . :;J: ~ OJ t,;;" c- .- L-J .... ,1 I-- . ., +5Y -r "'1.29. .., __ ~ ~~~ ~~~~ " :' '5' _____trr::: ~. "''' . ~O: o th ~: _/C ~ .,,~- ~ .IC~ us tZ~ ~J ~ r:~~ '- ... N ~.;r12- ... ~1l"2~­ 1.11 , .,11 Ll.··.... tl I I [ ~ e\ .. ""1,(, '.1' 'WOl l to.." ~ tit .A r,wu I._II t-C = = "J ','f" ,u, "c GREEN c .... ·1 IIo." . - e ~ ~~"STNCL -....- l:::::-~~im~~ . .1i :it:: ,':i '" 8 ~ ~ '"~ ,oo ,oo B QC +5' GlLUYI.-15 en :::l e\ e\ RD9SBSBQ. RNALDG DEVICE. IS DIP ICLBBB9CCZQ2. "AX I". TO"9Z Ploollc, CAL22VIB-IS. 2q DIP OBI5 tor An.loQ IVCAI. oB9 For TTL Inpul. S) Analoo eND I • • • • para t.d ground plan •. ~ '"-n == ~ 6 HE"AAKS. II 21 31 ql ~'~ ~'--------------------------------====J ~ \'f'.! 1·........,...U21A -~,,~,~,c~---------=:1~ 1IIA :I: s: _3__ ----"2__ - ' -_ _........L_ _ N-IIP2C ....... SW25 ,.,1 .......11:;25,,11 ' ......... 11 N ~ftP2fr ':' oSY h '" :::l !" ~~ ~~ C") ~ :» ....to :5 aUf '!:. ~ to E ~ 01 co 'f' co <0> 0 0 tUrKHI IlellO nS. ~~ , ~ ~ ~l~! ~f 5' F OATf. IIJIIIlI 11ttffT, 21 [ = :I. !2. Technical Brief HD66841 / LMG5060 APPENDIX "B" This section shows a copy of the schematic supplied by Hitachi Micro System Inc., San Jose, California. It is merely included for reference and is not intended to be copied. .. .. co N a: ...., .... lD . ::r .. N_e . ;; ~ u ri c ~ 6.a "';0,;;0,; a: ;; . " ddddw:!. 0.. ; ; ~ ; '" i . F- ~ . ::c ,;; i ."' '"a: "I "! 'S = ~ .. N ...u C\I z ::c " .. .'"'" a: a: , ,. . ... (O·~.'U" • E I .. <0. ;OUQ:I jH iiiiiiiiiiUiiii till C8 2-~81 ~II :-- ~. " -F=~~~ - .. 5 ." =~lll I" 1111111 IlIln :: . 8 i u'. .... . $I..1U ~ -3; - M "" " u 8 a: : ., ffd "1" i ~-~ ;r "" =t ~W~:d jj , ~ ii ii i N s ft j , .... . ':. ".. LI.nI >:l c old .. .... ...iii,!:;: 91 . .. . "':;a",=- u .. ~~~~ i."Hi.... ~ ~ ".au." .. ,. • ~~ ,' >I ~~ 'i.0I.. ~ . 'Xl u 11.'. ~I 'lU =n -l-r ~ ': u ~r~~ . ,' ~;: t , 1%11 i! (II. ;:) .". Cl ... ---1 :c .. ,.. !law ;§;i~ .:r! Uil cc j1 ~I\.jf - ua.. '" I. . . . . CD CD > ~ _.. =; :::t' I--f eD In Ir ~! ~ .... .... ........ U " ~ i a ~~;~ ;;;; I;:::: :=::: dddd~· =N .; . : :;;;:= ...... > 1... .... ~ : Lt~;-" I III. 51.;-" ~ u.. HITACHI Hitachi America, Ltd.· San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4163 HD66841 7LMG5060 Technical Brief APPENDIX" A " The 9 or IS pin male to male video cable" Cl "is shown below: 1.0 CRT CONTROLLER J .....----------------t(_ LVleBOARD PROTO _ " Cl" 2.0 The cables" C2 " and .. C3 " are provided with as a part of the panel inter connect kit. 3.0 The LCD panel displays are to be ordered from Hitachi's Electron Tube Division. Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 162 HD66841 / LMG5060 Technical Brief HITACHI COLOR LCD TFTMODULE (TM16DOIHC) : Refer to the display data sheet for detail, The page 14 of it shows how the sub-pixels are designated for LVIC HD66841 interface with 160 dots (H) and 200 dots (V) resolution. The cable" C2 " provides the signals to the display while cable" C3 "provides thebacklightpower. The display tiltand swivel angles provide different view angles in the ambient light, so it should be adjusted for the most desirable viewing angle. HITACHI B/W FILM LCD MODULE (LMG5060XUFC) : The mechanical, electrical, and optical specifications of this panel are stated in its data sheet, so , please refer to it. Its resolution is 640 dots (W) and 480 dots (H), with Ifl40 duty cycle. Cold Cathode FIourescent back light is built inside the display. SYSTEM DEBUG First power up the system in CGA mode using a CRT color monitor and the Paradise EGA board effectively disconnectingthe6.3"TFTLCDdisplayandreconnectingthecable"CI " to the monitor. After the system is up in CGA mode, verify that it works correcdy. Then, disconnect the cable" Cl " and reconnect it to the LVIC Proto Board 9 pin input. Also, verify that the cable " C2 " is properly connected to the display, since there is no key in the connector. If cable" C3 " is properly connected, florescent back light should come on and it is clearly visible. Also, verify the " SW 1 " and " SW2 " settings on the LVIC Proto Board. The system must come up with " C" prompt. Similarly, change the "Cl " cable to analog IS pin male cable and test the VGA panel LMGS06O. The "SWl" and "SW2" switch settings change as shown earlier. Create VGA directoryundertheC;\. Then, copy VGAMODE.EXE flle from the Oak software diskette in it. Run the VGAMODE.EXE file for different screen resolutions. However, for LMGS060 panel select 640 x 480 resolution. If every thing is working correcdy, one can execute all the OOS commands when appropriate prompts are displayed on ,the LCD screen. . DEMONSTRATION SOFTWARE After DOS 3.2 or later is installed, load any CGA or VGA graphics package such as PRINTSHOP, WINDOWS flle management package XTREE for the LCD display demonstration. With the LVIC proto Board in the system, the color video display will be replaced b~ the color TFT~CD display. ~ The black and white display Will show shades of gr~. By i= running Kaleidoscope 1 and 2, under PRINT SHOP, different fil dot and line patterns can be shown on either LCD screen. CI) 4 To display scanned image files (* .GIF), call Hitachi America Ltd., office at Sierra Point, CA. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4161 ) HD66841 / LMGS060 Technical Brief LVle PROTO BOARD The User Manual for this board describes all switches and their settings along with thePALequations forLMG5060XUFC and TMl6DOlHC panels. In this section. only the switches areaddressed. So. please refer to theLVIC Proto Board User's Guide for more details. The CNl and CN4 connector artwork is on the PCB. but they are not to be poppulated or used by the customer. If the power cables are short. they may be extended. The external power connector and bench power supplies are to be used as shown in the system block diagram. The nominal power consumption of this board is stated below so that ~ 7 I. 6 5 3 2 ••• • • adequate power can be externally provided: +5V@ I A, +12V@ 0.17 A, -12V@0.13 A The LVIC Proto Board accepts analog level input signals carried by the 15 pin male cable" Cl .. from theOak VGA videocontroUerboardinsidethePC-AT. TheR,G,B.HSYNC. and VSYNC signals are used to regenerate the CRT dQt clock, and sample the incoming video data. The output signals are sent over the cable" C2 .. to the black and white LMG5060 Hitachi display. This board· also provides 330 Volts RMS required by the backlight through the cable" C3 ". The switch settings of this board are shown below in Figure 4 : 3 6 IG • 2 • • 0 ~.------.---.------.------.~ ~ .~ 1 R'RISERVID SWI SW2 FIGURE 4 The LVIC Proto Board also accepts TTL level input signals carried by the 9 pin cable" Cl .. from the Paradise video controUer board. The R,G,B. HSYNC, and VSYNCsignals are used to regenerate the CRT dot clock. and sample the incoming video data. The output signals are sent over the ~ 8 7 I. 6 4 ••• 3 • • • 0 1 cable" C2 " to the 6.3" TFT. 8 colors, Hitachi display TMI6DOIHC. This board also provides +12 Volts required by the back light through the cable" C3 ". The switch settings of this board are shown under in Figure 5 : B 3 2 I" " • • • • • "10 ~ ~ RESERVED SWI SW2 NOTE: The attached schematic is only for reference, so do not copy it for your design. FIGURE 5 Section 160 4 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 HD66841 / LMGS060 Technical Brief SYSTEM COMPONENTS The hardware components are described in this section while the "Cl ", and " C2 " cable details are shown in the Appendix "Alf. MHZ, with 512KB memory; 20MB hard disk drive, and 1.2 MB.5.25 " floppy drive. It was also running OOS version 3.2. PC·AT : AST Premium 286 model 70 was operating at 10 board refer to its User's VIDEO CONTROLLERS : ForOAKVGAcottroller manual. The settings for the the six jumpers on the board are shown below in Figure 2 : JUMPERS ..J 4 CJ [;] ON ..J 2 ..J :3 ..J CJ CJ [;] CJ 7 ..J 5 CJ CJ CJ CJ CI CI OFF ON OFF ..J 1 OFF OFF FIGURE 2 CRT monitor. The switch settings for 80 column, RGB monitor in CGA mode are listed below in Figure 3 : Paradise Autoswitch EGA is card used in the CGA mode at (640H x 2OOV) resolution providing TTL level signals to the POS --- - - 6 5 4 3 2 1 OFF ON NOTE: 1.0 For more details refer to the Paradise CRT controller manual. 2.0 Make sure this switch is correctly set. FIGURE 3 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4159 HD66841 / LMG5060 Technical Brief SYSTEM CONFIGURATION The development system was configured with IBM PC-AT or compatible machine, OAK VGA or Paradise Autoswitch EGA 480 card, LVIC Proto Board, and Hitachi B/W LCD panel LMG5060 or TFl' active matrix, 8 color, 6.3", LCD display TM16DOIHC from the ELT division. The cables required to provide TTL or analog level input video signals to theLVICProtoboardarenotprovided. TheLVIC Proto board output connectors to the 6.3" TFT or Black and white display are provided to make the display conneCtion task easier. A separate AC high voltage cable is also required for the back light of each type of display. The back light is easily mounted with the four comer screws ofthe6.3" TFl' display. TheLMG 5060 display has built in back light. The system diagram for the LMG5060 LCD panel is shown below: POWER SUPPLY OAK "VGA" CRT CONTROLLER BOARD ANALOG SIGNALS .. C 1 .. B I W BACK LIGHT FILM DISPLAY LMG5060XUFC .. C 3" "C 2" NOTE: "C2" ="C3 " Cables are provided. FIGURE 1 The wagram shown above in Figure 1 is to be modified for a TFl' color display. The OAK VGA controller is replaced by the Paradise Autoswitch EGA 480 Board and the LCD panel LMG5060 is replaced by the Color panel TM16DO IHC. The analog level input and CMOS level output cables for the LVIC proto board will be likewise changed to drive the color module. • Section HITACHI 4 Hitachi America, Ltd .• San Francisco Center· 2000Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 158 January. 1992 HD66841 / LMG5060 '!echnical Brief LVle Proto Board Kash Yajnik The HD66841 LVIC Proto Board was designed by Hitachi Micro Systems Inc., San Jose, and can be ordered through Hitachi America Ltd., in U.S.A. The board is shipped with cables kit for multiple Liquid Crystal Modules from Hitachi. Black and white as well as color information can bedispbyed depending upon the selected LCD panel from Hitachi's ELT Division. This board is designed to display a black and white image with eight shades of grey using LCD panel LMG5060XUFC having VGA (640Hx480V) resolution. It can also display an eight colors CGA (640Hx240V) image when used with colorTFT LCD display panel TM16DOIHC. The L VIC Proto Board resides outside the IBM PC-AT or a compatible system running later than DOS version 2.0. It requires external power supply. The back light power is also provided by this board. A special prototype space is reserved on this board for customer circuit design and development in the critical areas of LVIC HD66841 based implementation. LVIC Proto Board User Manual is also provided to customize this board for many applications. This technical brief is written to complement the LVIC Proto Board User Manual for one specific application using the6.3" color TFT module (TM16DOIHC) or VGA module (LMG5060XUFC) from Hitachi's Electron Tube Division (ELT). A copy of the schematic is also included to provide the design implementation detail. A system diagram is also included to high light the laboratory environment. Similarly, each user may tailor display subsystem requirements for the desired application. The scope of this document is to help make the customization task easier and quicker. Thecircuitminimization tasks are left to each user and are not attempted. This is intended as an illustrative example for the Hitachi field and technical staff, and their customers. The following pages cover system configuration and components, the LVIC Proto Board set up, system debug, and demonstration software. The Appendix "A" covers analog I digital cable connection and the Appendix "B" shows lists the z . 0 schematic. t UJ en Refer to the subsequent pages for more detail. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4157 II .4 HD6473258 / LM016XML Technical Brief APPENDIX "C" LMOl6XML • '6 chlnc:ter x 2 lin.. INTERNAL PIN CONNEcnON • controll., LSI HD44780 il built-in (Sel page 971'. I +fJV single po_r lupply I Color tone ....••••••....•..••....... N_ grlY PInHo. SvtnboI 2 MECHANICAL DATA (Nominlldlmlnsiansl Moduluiu ••••••••••• 84W x 44H x 12T (max.1 mm EtflCtiw displlY 81W x 1&.8H mm C/II1'ICtII' sizi (Ii x 7 dotsl •.••••.• 2.98W x 4.86H ChlrlCtlr pitch. • . . • • . • . • • . . . . . • • • . • .• 3.5& mm DotsiZI ..••.•••..•••..•.... 0.56W x 0.66H mm W.ight . . . . . . . . . . . . . . . . . . . . . . . . . . . about 35, 3 Vss Vea Vo I,.. ............ ABSOLUTE MAXIMUM RATINGS min. Power Nllply for logic IVoo-Vss I ••••• " 0 power supply for LCD drive (Voo-Vol ......... ·••••••.••. 0 Input voltagl (Vii ••••••••••••..••• Vss Operlting tlmlpraturl (Til •••••••••••• 0 StorIgI lImperlNrl (Tstll •••••.•••• -20 , I mm '-..,..., +6V - H/L L: In_'IIft'" inIIUt H: Da. incIut IS AIW H/L H: Da..... CLeO _le-oMPUI L: OItIwme CLeO _le_PU 8 E 7 080 I 8 9 10 11 12 081 082 083 014 .6.5 V Voo V 5O·C 7rfC OV AS I 6.1i V functIOn -- • I mix. U. H/L H/L H/L H/L 13 o. o. HlL I. 017 H/L ELECTRICAL CHARACTERISTICS T•• :ZS-C. Voo • 5.0 V 1: 0.25 V Input "high" voltagl (VI ... ) •••.•••••.••.• 2.2 V min. Input "'ow" voltlgl (VII.I ..•••••••••••• 0.8 Vmlx. OutPUt:high'VOltll' (vo ... ) (-10... ·0.2 mAl .• 2.4 V min. OutPUt low'voltage (Vo\.l (1oL.· 1.2 mAl ••.. 0.4 Vmlx. PoWer supply current 1100 I (Voo • 5.0 V) " 1.0 mA typ. 3.omAmax. Power supply for LCD drive (Recommended) (Voo-V o ) Duty -1118 RlngeofVoo -Vo····· ••...•... 1.&-5.25V T. ·O·C ....•••..•.• " 4.8 V typo TI·2!tC .•.•••.••••.. 4.4 V typo T.·50·C .•.••..•••.•• 4.2 V typo EIIIbI...... H. H-+I. I H/L DatI bulline Hotl 111. I:rl H/L - .... Ut ,,- ~CN ~ •.M I !II . . :I II : \ ,.... In ,lie H044780. tile ....·an be _ itt 11th. 4011 Z-aon Of 8ob1t 10 tllet It ............ to lIOtIlo6 lIId 8 bit UPU·I. 111 WIlen 1m. . . . . . . I... bItI \Ont. _·11 t ..""'....... ulifll only" l1li_ of 08.-08. and 08.-08, ... not ulld. 01. nMf. tile HD44710 end II" MPIJ COIIIII _ _ 401t .... is ....,..,... twia. Oato' of ,lie ....... ani• • bltl 1 _ of 08. -08, ~ im.m. dea. il 8 bill 10..1 II trI/IIfarnd flm 1nd1lleft .......... bltllcom_of 08.-08, _Imerf_ '_ian a.- . . il8b1t1 ..... IZl WIlen im.m. cIoIiI II 8 bl....... ..... 010.. -08•• is U8Mf..... u.... 8 dati ""-'0...... ..- Section HITACHI 4 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 156 ---~--~ -------------------- HD6473258/ LM016XML Technical Brief i~'" u>c..J cc"'= ... _Cl APPENDIX "B" _CDO - ,-... .... > .... ::lI:lI: ILl' GI:= ..J W ....J ::;:) c:::l Cl ~ ....J ~ X w Lt) N (T) ....... 00 ::c I HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4155 HD6473258 7LM016XML Technical Brief APPENDIX " A " The H8/325 Evaluation Board Kit (US328EVBOIH) includes the following items: this application. The associated steps are listed below for clarity: o o o o o o o 1.0 2.0 3.0 4.0 5.0 H8 / 325 Evaluation Board Power cable for the board Board Stand Offs (Q=4) Five HMSI Demonstration Programs Diskette for PC-AT Software Agreement Copy Hardware Manual (M21T133 ) from HMSI Software User Manual ( HSM325EMSIlSE) from HMSI The board factory jumpers, switch settings, and other details are shown in the hardware manual. They may be changed for The 20 MHz crystal is to be replaced by 16 MHz crystal. The" SWI " is set for ROM position. Jumper" J5 " is set for 32KB ROM space. Jumper" J6 " for RAM space is not installed. Jumpers" J3 "and" J4 " for mode selection are set for mode" 2 .. i.e. " 13 " is installed while the jumper' J4 " is removed. These are shown below in the Figure 2 : RAM ROM o ~ o o 64K o 32K JS 64K 32K J6 SWt RAM • MOO MDt o o o o J4 J3 ROM FIGURE 2 Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 154 Technical Brief HD6473258 / LM016XML SUB SYSTEM COMPONENTS The LCD display subsystem components such as H8 I 325 Evaluation Board, LM016XML display, LCD Interconnect Board; Hitachi Laptop Computer, External Power Supply and the related software are described in this section. H8/ 325 Evaluation Board: This board was designed by Hitachi Micro Systems, San Jose, CA. It is provided as a demonstration and development tool. On-board EPROM contains the Hitachi Monitor firmware used for single line assembly, disassembly ,line editing, and debug purposes. Of the two serial ports, only the Terminal port is used to down load, up load, and run the programs. The I/O extention connectors "11" and "12" are used to connect to the LCD InterconnectBoard. The partially decoded, extented I/O space is further decoded on the LCD Interface Board. This board is designed to run at 10 MHz and uses a 20 MHz crystal for that purpose. However, in this application a 16 MHz crystal is used to provide 1 MHz "E" clock to the LCD Controller HD44780 located on the LCD panel. All the jumpers on this board are not set to the factory defaultstates. Refer, to the Appendix" A" for the H8/325 Evaluation Board details including the switch and jumper settings. LCD Panel Display (LM016XML): This display is provided by the Hitachi's ELT Division. It is capable of displaying 2 lines of eight 5x7 alpha numeric characters. It is 40 dots wide and 16 dots high. It has 1/16 duty cycle. The parallel data is clocked in at 1MHz "E" clock rate. It runs from +5V power supply. The customer has to solder 14 pins on LM016XML panelCor the appropriate connector used on the LCD Interconnect Board. The LM016XML LCD panel mounting and the proper viewing angles are critical to a strain free LCD display. Please, handle the panels according to the care recommended by the LCD display manufacturer. The logic signals sent to the LCD panel are at CMOS levels. Refer to the Appendix" C " for more information on the panel. LCD Interconnect Board: A wire wrap board was built to send parallel data, control signals, and power to the LCD panel over the "Ll" cable. The I/O extention cables "Jl" and "12" were connected to the H8 I 325 Evaluation Board. The LM016XML LCD panel contrast adjust potentiometer was also put on this board. The data bus buffer and gating logic were also located on this board. The power on reset pulse was provided by the H8 I 325 Evaluation Board. Refer to the Appendix" B " for its schematic. Hitachi Laptop Personal Computer" HL320": It is connected to the serial terminal port of the H81 325 Evaluation Board. The connector RJ-12 is attached to the Terminal port while a male to female 25 pin adapter cable is required at the Laptop PC end. The Hitachi" HL320" PC provides the software development tools for the user programs. The demonstration program up load and down load capability is also provided by the laptop PC. The communication link is full duplex, 9600 baud, 8 bits, 1 stop bit, and no parity check. Power Supply: Open frame switcher power supply from Kepco, Model # ECM-021K-CB is used to power up the H8 1325 Evaluation Board. Its rating is +5V @ 2A, +12V @ 0.3A, and -12V @ 0.2A. The Interconnect Board as well as the LCD display are also powered by it. Software: The laptop PC resident software development tools, packages, and utilities are described very briefly: H8 I 325 Cross Assembler: It is designed for DOS environment inside the laptop Personal Computer. When the user program is submitted as the source file, it assembles the code. Consequently, it produces Object and ~i:t/::: :::::~~: :::~us 811 object code segments (" *.OBJ !' extention) developed in parallel fora larger program. ~ The linked file has ",*.ABS" extention. Motorola" S "record C/) conversion utility is also included with the linker, and is used as output file with" S " record format. Upload: To up Load" S "Record file, push" EDIT SHIFf n Key down. Depress the " PG UP "key when using "PROCOMM " package for communications. Also, select ASCII format. Demonstration File: Motorola" S " record file " INIT78OC.ABS " is uploaded to the H8 I 325 Evaluation Board. The uploaded file i.e. " INIT78OC.ABS " is run for display demonstration. Screen Editor: Any word processing package is acceptable. In this application, Microsoft "WORD" package is used. The source programs are created and edited with this package. The source program files have" *.SRC " extensions. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4153 HD6473258 / LM016XML Technical Brief SUB SYSTEM CONFIGURATION The display subsystem was configured with HS/32S BvaluationBoard, LCD display Inten:onnectBoard,andLM01SXML panel from the BLT division. The required cable lengths are shown in the schematic for CMOS signal levels. The LCD power pins are a part of the 14 pin panel cable, so a separate power cable is not required. The subsystem block diagram for the Interconnect Board is shown below in Figure 1 : H8/825 EVALUATION BOARD I LM016XML HITACHI LAPTOP COMPUTER I ,...... H8/326 J2 '--' ,...... EVAL. BOARD I INTERCONNECT I POWER BOARD ,........ DATA BUS P2 1--1 BUFFER ----, ; : : (DECODER Jl P1 '--' '--' ,,-.. h 1 L1 LCD PANEL LM016XML '-" I BLOCK DIAGRAM NOTE: The required cables cables may be buUt or purchased by the user, from other vendors. FIGURE 1 Section HITACHI 4 Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 152 February, 1992 HD6473258 / LM016XML Thchnical Brief HS/325 Evaluation Board & LCD Display Kash Yajnik , I The H8/325 Evaluation Board(US328EVBOIH) was designed by Hitachi Micro Systems Inc., San Jose, and can be ordered through Hitachi America Ltd., in U.S.A. The board is shipped with power cable header, stand off hardware, demonstration programs, and associated manuals. This technical brief is written to complement the H8/325 Evaluation Board Manuals for one specific application i.e. interfacing to aperipheral. In this case,LCD paneiLM016XML from Hitachi's Electron Tube Division (ELT). Black and white character information can be displayed depending upon the selected LCD panel from Hitachi's ELT Division. Among the many products offered by the Hitachi's ELT Division, for this application, LCD panel LMOl6XML was selected. An Inter Connect Board is required to enable the H8/325 Evaluation Board to talk to the LCD display LMOI6XML. The character data is sent to the LCD panel for processing as well as display. The HD44780 LCD Controller Driver from Hitachi, SICD,located on the LMOl6XML panel, processes the data sent by the H8/325 Evaluation Board for display. The H8/325 Evaluation Board resides on a bench connected to the LCD interface board. The other end of the interface board is connected to the panel. It requires external power supply. After power on, a demonstration program is down loaded and run, to display a character message. A copy of the schematic is included to provide the design implementation detail. A system diagram is also included to high light the laboratory environment. Similarly, each user may tailor other subsystem requirements for the desired application. The scope of this document is to help make the customizing task easier and quicker. The circuit minimization tasks are left to each user and are not attempted. This is intended as an illustrative example for the Hitachi field and technical staff, and their customers. I] The following pages cover sub system configuration and components, H8/325 Evaluation Board set up, System Debug, and Demonstration Software. The Appendix" A " covers H8/ z 325 Evaluation Board details, and the Appendix" B "shows Q the Interconnect Board schematic. Also, Appendix" C "lists @ the LCD Panel data sheet. CI) Refer to the subsequent pages for more detail. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300 Section 4 151 j 5.0 For more details. refer to the lines for addresses 608 and 70H iIi the code sample is shown below: ADDRESS HEXADECIMAL _0 _1 _2 _3 _4 _5 _8 _7 _8 _9 _A _B _C _0 _E _F 00000000 02 OE OC 07 01 OB 02 07 04 00 OB 05 02 03 DB 00 OOOOOOtO 000000 00 00 00 00 00 00 00 00 00 00.00 00 00 00000020 03 DE DC 07 01 DB 02 07 04 00 DB 05 02 OS OB 00 00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000040 03 De 00 OF 05 'OB 02-'0704 00 04 05 02 00 09 00 00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060 09 oe.OD OF 05 DB 02 07 0400 04 05 02 00 08 00 00000070 07(0CI02 05 08 07 08 ONOOJoO 0000 0000 00 00 00000080 FF~ FF FF FF FF FF FF_ FF FF FF FF FF FF FF 00000080 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF OOOOOOAO FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF OOOOOOBO FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF OOOooOCO 'FF FF FF FF FF FF FF FF FF FF FF FF FF FF 'FF FF 00000000 FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF OOOOOOEO FF FF FF FF FF FF FF FF FF FF FF FF lIP FF FF FF OOOOOOFO FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Sectton 150 4 HITACHI Hitachi America, Ltd.· San 'Francisco,Genter • 2000 Sierra Point Pkwy.· Brisbane, GA 94005·1819 • (415) 589~8300 February, 1992 HD66841 LVle-IT ROM Programming Mode Tech Notes Application Engineering Kash Yajnik Palette Registers Access The palette registers inside the HD66841 (Pl-P8) are provided for different shades of 13 level grey scale. The palette registers are not to be used for color LCD display. To use these palette registers, the following procedure is suggested along with sample code for it : 1.0 Connect HD66841 address A4 (Pin 100) to the EPROM I ROM address A4. 2.0 Afterpoweron, the HD6684 1 will continuously cycle the addresses AO-A4. Thecontents of the EPROM I ROM where the programming information is stored will be continuously read by the HD66841. However, the EPROM I ROM contents will only be loaded, when the power on reset pulse is applied. 3.0 Therefore, if the LCD display register settings are to be changed dynamically, a power on reset pulse is required to reload the new EPROM I ROM data in the LVIC II. 4.0 The details of the palette register select (PS) bit i.e. Register RO bit 2 for the ROM Programming method are shown in the dk JCam below: Data bit No. o (ROM addresses $0000 1 2 3 ~ +-RO AQ-A4) Internal data registers III PSbit I7A Not ~ used $0010 +-RO ] ,.;0018 $0019 $001F Hitachi America. Ltd. ~ San Francisco Center 1. Pal~tte registerS ~ ~ %~ ~~~ ~ HITACH' 0 2000 Sierra Point Pkwy. 0 Brisbane. CA 94005-1819 Section 0 (415) 589-8300 r 4 149' HQ44780 - ROM MASK CHANGE FOR CHARACTER GENERATION CHARACTER ADDRESS MAP FOR 32 (5XIO) CODES UPPER EH FH NIBBLE (4 BITS) NOT USED OH IH 2H JIlo. •••••••••••••••••••••••••••••••••••••••••••••••••••.•••••••••••••••••.••.•••••••.•••••••.•••••••••..•..••••..•••••.••.•.••.•.••••••.•....•.••.•••••••.•.•••...•••••••••••••••••.••••••••••••••.••••••••.••••.••••• 3H 4H 5H 6H 7H BH 9H AH BH CH DH EH FH Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 148 HD4478Q •. ROM MASK CHANGE FOR CHARACTER GENERATION 2.0 Sixteen EPROM addresses for one 5xlO character. Therefore, for 32 character codes: EPROM addresses used = 16 x 32 = 512. Character font or matrix for letter"y" is shown by the EPROM dot pattern listed below: EPROM ADDRESS EPROM DD RAM DATA CHARACTER CG RAM CODES ADDRESS Ata A9 AS A7 A6 A.5 A4 AS 1 1 1 1 1 OUTPUT 0 0 1 .A2 At AO + + 04 03 02 01 00 000 o 0 001 o 0 o 1 o 1 a o 1 1 1 000 1 0 1 a 1 1 100 o 1 1 a 1 0 0 a a a a l' 0 a a 1 o 1 11 o 0 001 1 o 1 1. 1 o a a a a 110 1 0 0 1 1 ............................... ~k ...... k .................................................................................................................................................................... o 0 o 0 o 000 o 1 o o o 1 a o .. 011 100 101 NOTE: 1.0 2.0 3.0 1 1 0 1 1 1 "++" =Unused and unprogrammed EPROM outputs. "*" = Cursor 'OFF" code line 11. Fill with "0". "I" = LCD display dot "ON". HITACHI Section Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 4 147 H044780 - ROM MASK CHANGE FOR CHARACTER GENERATION CHARACTER ADDRESS MAP FOR 160 (5X7) CODES UPPER NIBBLE (4 BITS) 2H 3H 4H 5H 6H 7H AH BH CH DH / NOT USED OH lH 2H oj>. ..••..••.•......•....•....•.•..•.•..••.....•.•.•....•......••..•.•....••..•.....•.•....................................•..........••........•...•.....•.....•....••.•....•....•...•...•......••... 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 146 CHAR~CTER HQ44788 - ROM MASK CHANGE FOR 1.0 GENERATION Eight EPROM addresses for one 5x7 character. Therefore. for 160 character codes: EPROM addresses used = 8 x 160 = 1440. Character font or matrix for "P" is shown by the EPROM dot pattern listed below: EPROM ADDRESS EPROM DD RAM DATA CHARACTER CODES CG RAM ADDRESS AI0A9 AS A7 AS A5 A4 AS A2 Al AO 01010000000 1.0 2.0 3.0 04 03 1 02 1 01 00 110 10001 o 1 o 1 000 o 1. 1 1 1 110 0 1 0 0 1 100 1 NOTE: + + 001 o 1 .............. k. ... /..... i'V.... .. V .. ~V ... OUTPUT v. . . . Lh /........ . 0 0 1 0 o 0 11.0 1 0 0 0 0 1 o 0 0 0 0 1 1 "++" = Unused and unprogrammed EPROM outputs. "*" = Cursor 'OFF" code line 8. Fill with "0". "I" = LCD display dot "ON". HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 145 HD44780 - ROM MASK CHANGE FOR CHARACTER GENERATION HD44780 and HD 44780A have internal character generator ROM equivalent to Hitachi part # HD44780AOO. This character set has English as well as other symbols and is shown in the data sheet It can display 160 characters which are formed on 5X7 dot matrix with eighth row assigned for the cursor. Additionally, 32 different character patterns are possible with 5xlO character boxes at pre-assigned character addresses with eleventh row for the cursor display. In all, 160 plus 32 i.e. 192 different character codes can reside in the internal ROM. When a customer wishes to display special characters, the HD44780 / HD44780A masked ROM inside the part has to be changed. The dIlta sheet pages150 through 155 describe Hitachi's procedure for modifying character patterns. The character patterns are provided to Hitachi inside a 2Kx8 or larger EPROM. Mter pattern varification by Hitachi and the customer, trial sample parts are given to the customer for display and evaluation. Subsequently, the custom part with CO ROM change is made for volume production. NRE charge may be normally required for this change. A customer develops Character patterns using DATA I/O or other programming tools. If the EPROM is bigger than 2Kx8, only the first 2Kx8 partition is to be used. The unused locations may be programmed as O. The page 2 shows, character code for "P" on a 5x7 character box. EPROM outputs 05, 06, and 07 are unused and can be treated as don't cares. The DO RAM data provides the 8 bit character codes while the CO RAM address supplies (lower 3 address) bits for the line positions inside the character box. A logic "I" corresponds to LCD display dot "ON" condition. Since, the unused bits in an EPROM are logic high, they may tum the undesired display dots "ON". Therefore, when in doubt tum the unused character dots "OFF" i.e. program logic "0". The page 3 shows the pre-assigned character address map for the 160 (5x7) character codes. Similarly, page 4 shows the example of 5xlO character box for the character "y". Note that the eleventh line is programmed "0" for the cursor. EPROM outputs - the 12 th row address and beyond are programmed "0". Also, note that for 9th, 10th, and 11th row address, the A9, and A8 bits are programmed "0".. The page 5 shows the character address map for the 32 (5xlO) characters. No more than 32 characters can be accommodated. The-32 characters- will require the number of EPROM addresses shown below: With 16 addresses per character, the 32 characters will require 16x32 = 512 EPROM addresses. Therefote, an EPROM with 1440 + 512 = 1952 i.e. 2K bytes will be en,ough to contain the desired number of character patterns for this part. Since, the character address space inside the HD44780/HD44780A is pre-assigned only the character dot patterns can be changed. The character address space is not changeable. If a customer desires the flexibility of usfug an external EPROM for chareacter generation, please, recommend that HD66840 or other LCD controller or LCD module using HD66840 may be considered in the design. The Hitachi ELT Division, Schaumburg, Illinois, will be happy to provide RFQ for custom LCD modules. The details discussed L ' are expanded on the following pages. Section 144 4 HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 ---------------------- January. 1990 HD44780 LCD CONTROLLER ROM Mask Change Character Generation Kash Yajnik This technical brief covers custom character generation using LCD Controller HD44780. The data sheet specifies a standard character set using the C.O. ROM built inside the HD44780. Refer to the data sheet or the LCD Controller Manual # U74 formore information on the standard character set. For character sets that require other special characters such as Arabic, Hebrew, Katakana, or Kanji, to name a few, a mask change is required for the internal CO ROM. This informationis provided to augment the character developmentprocedure inside the HD44780 data sheet. The following pages describe this in greater detail. Itis suggested that the customer build a target subsystem using the HD44780 and the desired LCD display panel. Theinternal C.G. can then be used to display and develop a working character pattern tester. The.I:IWwD HD44780 prototype parts can be tested on this tester to check out the special character set. Normally, EPROM resident character patterns are used to transfer the information between Hitachi and the customer. Any EPROM which can store larger than 2K bytes, may be used to transport the character dot patterns. Commercially available EPROM programmers maybe used to program the character dot patterns inside the EPROM for submission to Hitachi America, Ltd., (HAL). Forrnore information, consult your nearest HAL,sales office or call the address listed below. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4143 Section 142 4 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 The literature and other documents used in this design are summarized below : o o o o o o o o o o o o o o H8/532 Cross Assembler Manual #S085CPC and" C " compiler for IBM PC H8/532 Evaluation Board User's Manual # US538EVB21H H8/532 Software User's Manual # HS538EMSS 1E MS "WORD" User Manual and other reference manuals " PROCOMM " User Manual and other reference manuals LCD Data Book #M24T013 from Hitachi America Ltd. Memory Data Books from Hitachi America Ltd. Hitachi Graphic Module Catalog # XX-E139 from ELT Division H8/532 Hardware User's Manual #M21 TOO2 from Hitachi H8/500 Programming Manual #M2l TOOl from Hitachi H8/500 Software Application Note #M21 T003 from Hitachi H8/532 Overview #M21 T173 from Hitachi Hitachi Laptop Personal Computer HL320 - Operator Manual Hitachi Laptop Personal Computer HL320 - MSDOS V3.2 User's Manual HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819- (415) 589-8300 Section 4 141 TUTORIAL • SOFTWARE DEVELOPMENT HJ)§18.lOB I LM200 LCD PANEL DESIGN APPENDIX· " C " REFERENCE LITERATURE Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 140 PAGE • - SEC110N DATA LIST STAAT SECTION ORA ,REL.coDE GEl. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane"CA 94005-1819 • (415) 589-8300 Section 4139 ,M H8I!OO ASSEIIlILiR (HSSOIOASAISF) 'M CI C2 C3 C4 Section 4 PAGE 5 CROSS REFERENCE LIST NAME 138 YEA 1.0 - 0:1'27180 17:S1A2 SECTION ATTR YALUE ORA ORA ORA ORA ORA ORA X XI XIO ORA ORA ORA XII ORA XU XI3 X2 X3 ORA ORA ORA ORA X4 XI ORA ORA X7 ORA XI XI ORA ORA SEOW«:E 0000EC8I 88'10 OOOOEOAF 7r71 0000E0C8 87' a7 OOOOEOCC 1r90 SCT coooocao 2' EXPT OOOOEOOO 3 r CIOOOEOIA 21' 23 0000E137 131' 133 0000E14E 138' 141 OOOOEIII "7' 14' OOOOEllC 155' 157 0000E0iI3 30'32 OOOOECWC 31' 41 CIOOOEOII ... ·50 OOOOEOlC 55'58 OOOOEGEI 102' 104 0000E107 114' III OOOOEIIE 122' 124 HITACHI Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1619 • (415) 569-6300 H8I5CIO ASSEMILER (HSIOIDASAISF) YEA 1.0 M. 0lIl27"17:51:42 PAOGIWoI NAME. GRA-ICS .M PAGE 4 ....'TOTAL EAAOAS 0 ....'TOTAL WNININOS 0 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section" 4137 ,M H8I5OO ASSEIotIILER (HS8CeOASAISF) VEA 1.0 GAAIICS PROORAM NAME • 115GAA 116GAA mGAA 118GRA 119GAA 120GRA 121 GRA 122GAA 123GRA 124GAA 125GAA 126GAA 127GAA 121GAA 129GAA 130GRA 131 GAA 132GRA 133GRA 134GAA 138GAA 138GAA 137GRA 138GRA 138GRA 140GRA 141 GRA 142GRA 143GRA 144GRA 145GRA 146GRA 147GRA l48GRA 149GRA 150GRA 151 GRA 152GAA 153GRA 184GRA 155GRA 155GRA lS7GRA 158GRA 15aGAA 180GRA 161 GRA 162GRA 163 184GRA 185GRA 161 187GRA 168GRA 168GRA 110GRA 171 Section 136 4 ~ 15:40:31 BTST CE1OCACF7 SHE CE1C£26F7 HOP C EIIOOO MOV:E C E111 5OC8 MOVTPE C E113157F1'100110 MOV:E C E1185204 MOVIPE CEliA 157FF000e2 HOP C El1FOO X9: MOYFPE C E120 157F1'10084 BTST CEI25ACF7 SHE C E127 26F7 NOP C EI2900 MOV:e CEI2A5ODC MOVIPE C EI2C 157FF100110 MOV:E CEI315100 MOVTPE C EI33157FFOOO111 C EI3800 HOP C EI39157FF10084 XIO: MOYFPE BTST CEI3EACF7 C EI4G26F7 BNE CE14200 NOP C EI43157FF100110 MOVTPE C E14851FF MOV:E C E14A 157FFOD091 MOVIPE CEI4FOO NOP C EI50 157FFI0D84 XII: MOYFPE BTST CEI55ACF7 CE15726F7 BNE CEI5900 HOP C EISA 157FF10080 MOVTPE CEI5F5161 MOV:E C EI81157FFOD091 MOVTPE C EI6600 NOP XI2: MOYFPE C EI67157FF10084 . BTST CEI8CACF7 CE16E26F7 BNE C El1000 HOP C EI71157FF100110 MOVTPE CE1785177 MOV:E C EI78157FFOOO111 MOVTPE CEI7DOO HOP CEI7E 157FF10084 XI3: MOVFPe CEI83ACF7 BTST C EI8526F7 BNE CE18700 HOP C Elsa 157FF10013 MOVTPE CEI8D5132 MOV:E C EI8F 157FfOOO81 MOVTPE CEI9400 CEli500 HOP CEli500 C E197 00 CElaelA CE1111100 HOP NOP HOP SLEEP PAGE 3 ;BIT TESTl7 OF A4 ;F &flAG,.z.1 GO TO XI ;BiF1.AG NOT SET ;RO-BH 'ffB.RO RO.@ff7FFI ;BHT07FFI ;R2-04H Iff4.R2 ;04HT07FFO R2"ff7FFO '7.114 XI @ff7FF1,R4 ;READ 7F1'1 DATA TO 114 .7.114 ;BIT TESTl7 OF A4 X9 ;F &flAG.z..l GO TO XI ;BIFlACI NOT SET IffC,RO ;RO-CH RO•.,ff7FFI ;CHTO 7FFI IffO,Rl ;Rl..OQH.G1W'H1C BYTE 11 RI,@ff7FFO ;OHT07FFO @ff7FF1,A4 ;READ 7F1'1 DATA TO A4 .7M :BlT TESTl7 OF A4 Xl0 ;F&flAG.z..l GOTOX10 ;BIFlACI NOT SET RO.@ff7FFl ;CHT07F1'1 IffFF.RI :RI ,.fF.GRAPHIC BYTE 112 ;'fFT07FFO Rl.0ff7FF0 ;READ 7FFI DATA TO 114 Off7FFI.R4 ;BIT TESTl7 OF 114 '7.114 XII :F &flAG,.z.1 GO TO XII ;BIFlACI NOT SET RO•.,ff7FFl ;CHT07FFI Iff6I.Rl :Rlo61oGRAPH1C BYTE 13 Rl.,ff7FFO ;61 TO 7FFO @ff7FF1.R4 ;READ7FFI DATA TO 114 ;BITTESTl7OF 114 .7.114 X12 ;F &flAG,.z.1 GO TO X12 ;BIFlACI NOT SET ;CHT07FF1 RO.@ff7F1'1 Iff77.R1 . ;Rl.77.aRAPHlCBYTEM :77T07FFO Rl.0ff7FFO :READ 7F1'1 DATA TO 114 @ff7FF1M .7.114 ;BIT TEST '7 OF 114 X13 :F &flAG.z..l GO TO X13 ;BIFlACI NOT SET R3.0K7FFI ~T07FF1 IK32.R1 ;LOAD RI-32KoDIIP.otI ;32HT01FFO Rl.0K7FFO ; DISPUY DOT UGHT-lOGICV : DISPUY DOT DARK • LOGIC ,. ;H8.!532 ASlEEP HOP HITACHI Hitachi America. Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA94005-1819 • (415) 589-8300 ... H8i500 ASSEMBI£R (HS5080ASA1Sf) VEA 1.0 N. GRA-BCS PROGRAM NAME • saGM 59GM 80GM 61GM S2GM 83GM 64 65 86GM S7GM 68GM 69GM IOGRA 71GRA 72GRA 13GRA 74GRA 75GRA 78GRA 17GRA 78GRA 18GRA 80GM 81GRA 82GRA 83GRA 84GM 85GM 86GM 87GRA 88GM 89GRA 80GRA 91GRA 92GRA 93GRA 84GRA 95GRA 86GRA 97GRA 98GRA CEC832SF7 HOP CE08600 C EOBIISOOI C E066157FF10Cl80 C E080 157FFOOQQZ HOP CE09200 04I00IIQ0 15;.0:31 SHE X6 MOV:E MOVI'PIl MOVI'PIl IH'9,Al RO,@If7FF1 R2.@1f7FFO ;1' B.fI.AO.z.1 GO TO X8 ;1!iFUG NOT SET ;~OADROo8H ;9HT07FFI ;OH TO 7FFO ; SCREEN Cl£AR ROUTIIE START C E093AnI3 CEOQSOO C E088157FF100N CE0Q8ACf7 CE09026F7 C E09I' 00 CEOAOSOOA C EOAZ157FF10Cl80 CE0A75100 C EOA8 157FF00081 CEOAEOO C EOAF 157FF10084 CE0B4ACF7 CEOB82SF7 CE0B800 CEOB85008 C EOBB 167FF10Cl80 CEOC05100 C EOC215l'FFOOO81 CEOC700 C EOC8 50FFFF CEOCBOO C EOCC 157FFIOON CEOOI ACF7 CEOO326F7 CEOO500 CEOO85OOC C E008157FF10Cl80 CeOOO5100 C EOOF 157FfOOO1l1 ceoe400 CECE501BOE3 CEOE800 NOP Cl; RS MO'IFPE BTST BNE @H7FF1,R4 '7,114 Cl NOP MOV:E MOVTPE MOV:E MOVTPE NOP CZ: ;CL.EARRS Cl.R.W MOVFPE BTST BNE NOP MOV:E MOVTPE MOY:£ MOVI'PIl ;READ 7FFI DATA TO 114 ;1i1T TE5117 OF 114 ;1' B.fI.AO.z.l GO TO Cl ;I!iFl.AG NOT SET ;Al-AH .1fA,RO ;All TO 7FF1 RO,@If7FFl ;Rl00H 'IfO,RI RI,@1f7FFO ;OH TO ~1A!oOH @H7FFI,R4 ;READ 7FF1 DATA TO 114 17,114 ;BIT TEST.7 OF 114 ;1' B.fI.AO.z.l GO TO C2 C2 ;1!iFUG NOT SET tlfB.RO ~ RO,@H7FF1 ;BHT07FFI ;Rl00H IIfO.Al ;OH TO ~ IWoCIH Rl,Olf7FFO NOP C3: C4: il] 1H'fFFF,R5;COUNT..RSooFFFFH MOV;I NOP MO'IFPE BTST SHE OH7FF1,R4 ,7,R4 C4 MOV:E MOVI'PIl MOV:£· MOVI'PIl ,Ife,RO RO,OIf7FF1 llfO,RI Rl,@1f7FFO SCM' RS,C3 ;READ 7FFI DATA TO 114 ;IIlT TESTt7 OF 114 ;1' B.fI.AO.z.1 GO TO C4 ;BiFlAG NOT SET NOP ;RQ.QI ;CHT07FFI ;RI...QH.OOOE FOR 1lOT OFP ;OHTO 7FFO NOP NOP ; SCREEN Cl£AR ROUTtE COMPlETED 99 100GM 101 GM I02GM I03GRA I04GAA IOSGAA I06GM 107GAA IOBGAA logGM IIOGM l11GAA 112GM 113GAA 114GM PAGE 2 CEOEiOO HOP CEOEAOO C EOEB I57FF100I4 X7: CEOFOACF7 C EOF228F7 C EOF400 NOP CEOF500 NOP CEIlF.800 NOP CE0F700 HOP CEOF85OOA C EOFA 157FFI 0Cl80 C EOFF51BO C El01157FfOOO1l1 CE10600 NOP C El07157FF100N XI: NOP MOYFPe BTST BNE @H7FFI,R4 '7,R4 X7 ;READ 7FF1 DATA TO 114 ;BIT TESTt7 OF 114 ;IF 1lI1UG.z.1 GO TO X7 ;I!iFl.AG NOT SET ;INlTW.lZATION DONE ;RO-AH RO,OIf7FFl ;AIIT07FFI lIfao,R1 ;Rl0B0H Rl,Olf7FFO ;OHT07FFO MOV:£ MOVI'PIl MOV:E MOVI'PIl 1IfA,Al MOVFPE OH7FF1,R4 ;READ 7FFI DATA TO 114 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4,35 PAGE I '" HMCIO ASSEMIILIR (HSIGIDASAISFl YEA 1.0 - 00I/CMII0 15:.lO:31 QAA.8CS PROGIWoIIIMIE • I 2GIlA 4 GIlA 5 .IEADNI 'GAA-8CS" caooo .SECTJQN ORA,CODE.ALJG/W .EXPORI' X CEOOQ .ORB ;LOC CNTR oEOOOH MEOOO ; BUSY FLAG CIECKED lORA a GIlA 100RA 11 ORA 120RA 130RA 14 ORA 150RA IBORA 170RA II ORA 190RA 20 ORA 21 ORA 22 GIlA 23GRA 2.GRA 25 ORA 26 ORA 27 ORA 21 ORA 29 ORA 30 ORA 31 ORA 32 ORA 33 ORA 34 ORA 36 ORA 36 ORA 370RA 38 ORA 39 ORA .0 ORA ., ORA 42 GIlA 43 ORA .. ORA 4S0RA 46 GIlA .7 ORA 46 ORA •• ORA so ORA 5tORA 52GRA 53 ORA 54GRA SSGRA 51 GIlA 57GRA X: C oaooEOOO CEOOQA013 CEOO2 A1I3 CEOO,",2t3 CEOOIA3t3 CEOOI .... ,3 NOP CEOOAOO HOP CEOOIOO HOP CEOOCOO C EOOO 157FF100a0 CEOI25112 C EOt',57FFOD091 CEOt.oo NOP C EOtA 157FFIOOM XI: CEOtFACF7 CE02126F7 CE02300 HOP CE0245001 C E026157FFlooao CE02B5107 C E020 157FFODOa1 CE03200 HOP C E033 t57FFlOOM X2: CE03IACF7 CE03A26F7 CE03COO HOP CE0305002 C E03F 157FFlooao CE044511D C E04e 157FF000h CE04BOO HOP CE04C 157FF100M X3: CE051 ACF7 CE05328F1 CEOSSOO HOP CEOSS5OOi:I C E05II57FF100a0 CE050511F C E05F 157FFOOOt11 CE0B400 HOP C EOSSI57FF.l00M lI4: CEOSAACF7 CEQ5C.., CEOBEOO HOP CE05F5OOI C E071 t57FFtooao C EO" t57FFOOOt12 CE07BOO HOP C E01C t57FFtOOM XI: CEQlt ACF7 .EQU cuu ;X .EOCOH RO CUI.a CLR.a CLR.B CLR.B ;CWARO AI R2 R3 114 ;CWAIII ;CWRR2 ;CWRR3 ;CWRR4 ; INmAI.IlAT1ON START MOVTPE MOV:E MOVTPE ;OHTQ7FFI RO,OM7FFI 1H'12,1II ;LOAO AI .12H ;12HT07FFO Al.'M7FFO MOVFPE BTST BNE OM7FFI.R4 .7,IW XI MOV:E MOVTPE MOV:E MOVTPE MOVFPE BTST BNE ;REAO 7FFI DATA TO 114 ;BIT TESTl70f 114 ;F IIofI.AQ.I GO TO XI ;1IOfI.AQ NOT SET ;LOAD RIIolH IH'1.RO ;IHT07FF1 RO.OIf7FFI ;LOAOIII.7H .M7.Rl ;7H TO 7FFO AI.OIf7FFO MOV:E MOVTPE MOV:E MOvrPE ;REAO 7FFI DATA TO 114 . OM7FFI.II4 ;BIT TESU70F 114 '7.114 ;F B.t'lAG.l GO TO X2 X2 ;8/F1AG NOT SET ;LOADRO-2H 1H'2.RO ;2HT07FF1 RO.'M7FF1 IH'ID.RI ;LOAD III.IDH ;IDHT07FFO Al.0M7FFO MOVFPE BTST BNE OM7FF1,R4 '7,IW X3 IIOV:E MOVTPE MOU MOVTPE MOVFPE BTST BNE ;READ 7FFI DATA TOA4 ;BIT TESU70f 114 ;F GO TO X3 ;8IFIAG NOT SET ;LOAOIID4f IH'3.RO RO.@If7FF1 ;3tT07FF1 IH'IF.A1 ;LOAD Rt.1FH ;IFHT07FFO AU~H7FFO ,1IofI.AQ., MOY:E MOVTPE MOVTPE ;READ7FFt DATA TOA4 OM7FFt.1I4 17.114 ;BIT TEST 17 Of 114 X4 ;f B.t'lAG.t GO TO M ;8/F1AG NOT SET IH'I,RO ;RWH ;8HT07FFI RO.OH7FF1 ;OHT07FFO R2.OH7FFO MOVFPE BTST OH7FFt,R4 '7,R4 ;READ 7FF1 DATA TO A4 ;BIT TEST 17 Of AI Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005·1819 • (415) 589-8300 '34 APPENDIX " B " 1.0 PROGRAM NAME . " GRA·BCS.MOT " 2.0 ADDRESS RANGE . " EOOOH . E199H " 3.0 PROGRAM DESCRIPTION . CLEARS SCREEN, CHECKS BUSY FLAG, AND DIS PLAYS 4 GRAPHIC BYTES ON THE LCD LM200 PANEL STARTING AT THE 1200TH CURSOR POSITION. HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 133 '" Ht.1CO ASSEMIIUlR (HSIOIOASA tSF) VB! 1.0 - o:w27180 t 7:4e:G3 PAGE • '" SECTIONOATAUST SECTION etA Section 132 4 ATTRIMi SIZE START REI..coDE OCt AF HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 'M H8IISOOASSEIotILiR (HSIOIOASA1Sf) VEIl 1.0 - 'M CROSS REFERENCe UST NAME A Cl C2 C3 C4 CHA XI Xl0 XII X12 X13 X2 X3 X4 X5 XI X7 XI XI SECTION ATTA VAlUE 03I27,w 17:48:011 PAGE 5 SEOlJ:NCE CHA EXPT ooooc:ooo 3 8' 0000CC80 " 81 CHR 00CI0C0C8 88'80 CHA CHA 00CI0CCE5 98' 108 oooocoee 911' 101 CHA CHR SCT OOOOOCOO 2' CIf! OOOOC01B 23' 25 0CIC0C151 143' 1~ CHA 0CIC0C188 151' 153 CHA CHA 0CIC0C17F 158' 181 OCICOCIIII 181' 188 CHR CHA 00CI0C034 32':1' CIf! acooc:cMD 41' 43 CHA 0000C088 SO'52 CHA 0CIC0C07F 50' 61 CIf! OOOOCCIIII 87' 88 CIf! OCICOCI04 113' 115 CHA 0CIC0C121 126' 128 CHA 0CIC0C138 1:1" 138 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Seelion 4131 .M HWXI ASSEMIIWI (HSICIIDASAISF) VEIl 1.0 PROGRAM NAME • .CHfI.8CS 172CHA 173CHA 17. 175CHR I7ICHA 177 I7ICHA Section 130 4 MOV~ CCIA5513C C ClA7157FR1CX181 MOVTPE CCIACOO CClAOOO PAGE • 'If3C,RI ;lOAD Alo3CI\oOlSPoOH AI.,If7fFO ;3CH TO 7FFO NOP NOP CCIAEIA :SWI" 171 180 'M"TOTM. EAAOAS -'TOTM. WARNINGS 0 03127190 17:41:l1li SWI" ; PROCESSOR HII132 .END HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 ,M HMOO ASSEMBLER (HS!08OASA 1SF) YEA 1.0 03127.-.:117:46:03 CHR-BCS PROGRAM NAr.E • 115CHR 116CHR 117CHR 118CHR l11CHR 120CHR 121CHR 122CHR 123CHR 124CHR 125CHR 126CHR 127CHR 126CHR 121CHR 130CHR 131 CHR 132CHR 133CHR 134CHR 135CHR 136CHR 137CHR 138CHR 131CHR 140CHR 141CHR 142CHR 143CHR 144CHR 145CHR 146CHR 147CHR 148CHR 149CHR lSOCHR 151 CHR IS2CHR IS3CHR 154CHR IS5CHR 156CHR lS7CHR 156CHR lsaCHR 160CHR 181CHR 162CHR 183CHR lMCHR I65CHR lMCHR 167CHR 168CHR lQCHR 170CHR mCHR SNE CC10B26f7 NOP C ClOD 00 NOP CC10E00 NOP CC1OFoo NOP CC11000 NOP CC111 00 MOV:E CC112500A MOVTPE CCl14157FF10010 MOV:E CCllUl08 MOVTPE CCllB 157FFOOO111 NOP CC12000 XI: MOVI'PE CCl21157FF100N BTST CCI28ACF7 SHE CC12828F7 NOP CCl2Aoo MOV:E CC12BSOOB MOVTPE CC120 157FF10010 MOVTPE CC132157FFOOO12 CC13700 NOP CCI38157FF100N XI: MOVFPE C C130 ACF7 STST C CI3F26f7 BNE CC141 00 NOP MOV:E CC142500C CC!44157FF!00I0 MOVTPE CCl4U148 MOV:E CC14B 157FFOOO111 MOVTPE NOP CCl5000 C CI51157FF100N Xl0: MOVFPE BTST CCI56ACF7 CCI5626f7 BHE CC15Aoo NOP CC15B 157FF100I0 MOVTPE CCI605141 MOV:E CC162 157FF00091 MOVTPE CC16700 NOP Xll: MOVFPE CCI681 S7FF10084 BTST CCI60AeF7 C CI6F26F7 BHE CCI7100 NOP C C172157FF100I0 MOVTPE CCln5153 MOV:E CCI7V 157FfOOO111 MOVTPE CCI7Eoo HOP CCl7F 157FF100IM XI2: MOVI'PE CCl84ACF7 BTST CCI8626f7 BNE CCl8600 NOP CCIII 157FFlooaD MOVTPE CC1IE5!48 MOV:E CCIao 157FFOOOa1 MOVTPE CCla500 NOP CCIM 157FFI 0084 XI3: MOVI'PE CCI9BACF7 BTST CClI026f7 BNE CClIFoo HOP CCIAO 157FFlooa3 MOVTPE X7 PAGE 3 ;IF IlifUG .z.1 GO TO YJ :1IifLAG NOT SET ; INITlAUZATION END .1fA,RO RO.OIf7FFl IH1.Rl Rl.01f7FF0 ~J.H ;All TO 7FFI ;Rl.eH ;8HT07FRI @1f7FF1.R4 :REAIl7FFl DATA TO R4 ;BIT TESTl7 OF R4 '7.1\4 X8 ;IF IlifUG .z.1 GO TO X8 ;1IifLAG NOT SET :AO.aH 'IfB.RO RO.@If7FF! :BHT07FFI ;OHTO 7FRI R2.01f7FFO OH'7FF1.R4 :READ 7FF1 DATA TOR4 :BIT TEST.7 OF R4 '7.R4 Xi :IF IlifUG.z.l GO TO X8 :Bn'\.AG NOT SET MC.AD :ROoCH ;CHT07FF1 RO.OIf7FF1 ,1f4B,R1 ;Rl..a.cooE FOR "'" Rl.01f7FF0 ;48T07FRI II] ;READ 7FFI DATA TOR4 OIf7FF1.R4 ;8IT TESH7 OF R4 '7.R4 Xl0 ;11' I!ifUG.z.I GO TO XIO ;Bn'\.AG NOT SET ;CHT07FF1 RO.OH'7FFI M41.RI ;Rl041.cooeFOR"A" Rl.01f7FRI :41 TO 7FF0 :READ 7FF1 DATA TO R4 ;BITTESTl7 OF R4 Xli :IFI!ifUG.z.l00TOXII . ;1IifLAG NOT SET ;CHT07FFI AD.OIf7FFl IH'53.RI :Rl.a.cooE FOR OS" ;53 TO 7FRI Rl.01f7FRI OIf7FF1.R4 '7.R4 ;READ7FF1 DATATOR4 OIf7FFI.R4 .7.1\4 ;BIT TESTl70f' R4 XI2 :F l!ifUG.z.l GO TO X12 :Bn'\.AG NOT SET RO.@If7FF1 :CHT07FFI 1If48.R1 :Rlo48oCOOE FOR,.,. ;48 TO 7FFO Rl.01f7FRI OIf7FF1.R4 '7.R4 X13 :READ 7FF1 DATATOR4 ;BIT TEST .7 OF R4 ;11' 1!ifUG.z.1 00 TO XI3 ;&1'lAG NOT SET R3.@If7FFl ;OHT07FF1 HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra PointPkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 Seelion 4129 '" HMOO ASSEM8LER (HSSlIOASA1Sf) VEA 1.0 CHR-IICS I'IIOClRAM NAME. saCHA saCHA 60CHA SICHR 62CHA 63CHA &lCHA 65CHR 66CHR 67CHA 66CHR 69CHR 70CHR 71CHR 72CHA 730HR 74CHR 75 CC07EOO C C07F 157FF10014 CC084N:.F7 ccoee 2eI'7 CC08800 CC0885008 CCQ88157FF100811 Ccogo 157FFoooa2 CCQ8500 C CQ88157FF10014 CCODBACF7 CC09D26F7 CC09FOO CCOA05OOI CCOA2 157FF10080 CCOA7157FFOOO92 CCON:OO NOP X5: r:tJI2719O 17:46jXJ MOVFPE BTST BNE NOP MOV:E MOVTPE MOVTPE PAGE 2 @H'7FF1.R4 ;ROO 7FFI OJ.TA TO R4 f7,R4 ;BITTESTl7 OF R4 X5 ;F I!IFlAG "z.1 GO TO X5 ;1!IFlAG NOT SET ;ROoaH M.RO RO.iH'7FFl ;8H TO 7FFI R2.@H'7FFO ;OHTO 7FFO NOP X8: MOVFPE BTST BNE NOP MOV:E MOVTPE MOVTPE ;ROO 7FFI DATA TO R4 ;BIT TESTl7 OF R4 ;F &flAG"z., GO TO XI X6 ;I!IFlAG NOT SET ;LOADROoaH 'H'9.RO RO.@H'7FFI ;9HT07FFI R2.@Iof7FFO ;OHT07FFO @H'7FFI.R4 '7.R4 NOP : SCREEN CLEAR ROUTIIE START 78 nCHR 78CHA 79CHR SOCHA 81CHR 82CHA 83CHR MCHA 85CHA 8&CHA STCHR saCHR 89CHR 90CHR 91 CHR 92CHR 93CHR 94CHR 95CHR 9&CHR S7CHR 98CHR 99CHA lOOCHA 101 CHA 100CHA l03cHA 104CHA 108CHA lOSCHA 107CHA 108CHA 109CHA 110 III CHR 112 113CHA 114CHA Section 128 4 CCOADADI3 CCOAFOO NOP C COSO 157FF10084 C1: CC085N:.F7 CCOB72&F7 NOP cccaaoo CC08ASOOA Ccoec 157FF10080 CCOC15100 C COC3 157fFoooai NOP ccocaoo Ccoca 157FFlOOI4 02: CCOCEACF7 CCOOO28F7 CCOD200 NOP CCOOO5008 CCOD& 157FF10080 CCODA5100 CCODe 151fFoooal NOP CCOE100 C COE2 5D01FF 03: CCOEIOO C COE8157FF10084 Col: CCOEBACF7 cCOED2e1'7 CCOEfOO CCOFOSOOC C COF2 157FF10080 CC0F751ZO C 00F9 157FFOOCi111 CCOFEOO CCOFF Ot BOb CCI0200 NOP ClA.W AS MOVFPE BTST BNE MOV:E MOVTPE MOV:E MOVTPE @H'7FF1.R4 ;ROO7FF1OJ.TATOR4 17,R4 ;BIT TESTl7 OF R4 Cl ;F &flAG"z., GO TO Cl ;1!IFlAG NOT SET ,tfA.RO ;ROoAH RO.@tf7FFl ;All TO 7FFI ;Rl.oH MO.RI RI.@Iof7FFO ;OH TO 7FF04JA I.AIooOH MOVFPE BTST SNE @H'7FFI.R4 '7.R4 C2 MOV:E MOVTPE MOV:E MOVTPE MOVj NOP MOVFPE BTST DIE NOP MOV:E MOVTPE MOV:E MOVTPE NOP Scs.f ; CLEAR AS ;ROO 7FFI DATA TO R4 ;81T TEST '7 OF R4 ;F &flAG"z.I GO TO C2 ;&flAQ NOT SET ;ROoIIH '1of8.RO ;8HT07FFI RO.OIof7FFl ;Rl.QH 'IofQ.RI Rl.OIof7FFO ;OH TO 7FF04JA HIWH IH'1FF.AS ;COUNT-RS-IFFH OH7FF1.R4 ,7,R4 Col ;ROO 7FFI OJ.TA TO R4 ;BIT TEST.7 OF R4 ;F &flAG "z.I GO TO Col ;8IFUQ NOT SET ;RO.CH ItfC.RO RO.ilof7FFt ;CHT07FFt IIH'2O.Rl ;Rt o2OIIoCODE FOR '8lN4k" RI,ttf7FFO ;2CHT07FFO AS,C3 ; SCREEN CLEAR ROUTtE COMPlETED CC10300 C C104IS7FFlOO84 CCtOIACF7 NOP X7; MOVFPE BTST tH'7FFI.R4 '7.R4 ;ROO 7FFI OJ.TA TO R4 :81T TESTl70F R4 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300 'M HIISOO ASSEIotILEA IHSIGIDASAtSF) YEA 1.0 N' OWIISIO tl:33:20 CHIlICS I'AOGAAM NAME. 1 2CHA 3 4CHR 5' 6 PAGE 1 .1EAD1IG "QIR.BCS" COOOO .SECllOII CHA,C0DE,AUGN.2 A .EJaIORT CCOOO .ORB A: 8CHR C OOOOCCOO cutB tCHR CCOOO.1013 10CHR CC002Att3 ttCHA CCODU213 12CHR CCDDU313 13CHR CCDaU413 14 15CHA CCODAOO HOP llCHA CCDOBOO HOP 17CHA ccaocoo HOP 18CHA ccaoooo HOP ttCHA C CODE 157FFtDOlO 20CHA CCDt3lttC 21CHA C CDt5157FFODOtt 22CHA CCDtAOO HOP 23CHA ·C CDIS 157FF1D011 XI: 24CHA CCD20N:iF7 25CHA CCD222f17 HOP 26CHA CCD2400 27CHA CCD255D01 28CHA C CD27 t57FFtDOlO 2tCHA CCD2CSIIIII 3ClCHA CCD2E 157FFDOD11 31CHA CCD3300 NOP 32CHR C CD34157FFtDOll X2: 33CHA CCD3tN:iF7 34CHA CCD3B2f17 35CHA CC03DOO HOP 36CHA CCOOE5D02 37CHA CCD40 157FFIDOIO 38CHA CCD455127 38CHA C CD47 157FFODOtt 4DCHA CCD4COO HOP 41 CHA C CD40 t57FFID084 lCt 42CHA CCD52N:iF7 43CHA CCD54'1fF1 44CHA ccaseoo HOP 45eHR CCD57SD01 48CHA C CDSIIS7FFIDOIO 47CHA CCDSESIIF 48CHA ccaao t57FFDOD1t 4tCHA ccassoo HOP X4: SOCHA ccaaatS7FFI. 51eHR CCD88N:iF7 52CHA CCDI026F7 53CHA CCD8FOO HOP 54CHA CCD705D04 SSCHR C CD72IS7FFIDOIO saCHA . CCD775108 57eHR C CD1I157FFODOtt ;LOC CNTR.cccatI IfCOQI ; BUSY FlAG ClECKEll ;A.COOQH .EOU ;CWRAO RO cutB cutB cutS cutS AI A2 A3 A4 ;Cl.EAAAt ;CWRA2 ;CWRR3 ;CWAA4 ; ~TION STAAT MOvrPE MOY:E MOvrPE ;QHT07FFt AO.OIf7FFt IItlC.At ;L.OAD At • at ;ICHT07FFD At,olt7FFD MOYFPE ,If7FFI.114 '7.A4 Xt STST StE MOY:E MOvrPE MOY:E MOvrPE MOYFPE BTST BNE MOV:E MOvrPE MOY:E MOvrPE MOYFPE . BTST 8NE MCMi MOVTPE MOY:E MOVTPE MOYFPE sm BNE MOV:E MOVTPE MOY:E MOvrPE ;AEAD lFFt DATA TO A4 ;BIT TEST .7OF A4 ~ 1IIRAO,.z., GO TO Xt ;a.fIAG NOT SET ;LOAD ROelH IIft.AO ;IHT07FF1 AO.OIflFFt 1IfIIII.At ;LOADAI-IIIIH ;95HT07FFD Al.,lt7FFD ill ;READ 7FFIDATA TO A4 tH'7I'Ft.A4 ;BIT TEST.7 OF A4 17.114 ;F &fI.AG,.z., GO TO X2 X2 ;I!IFI.AO NOT SET IIf2,AO ;L.OAD AO-2H ;2HTOlFFt AO.OIf7FFl 1If27.At ;L.OAD AI-27H ;27HT07FFD AI.OIf7FFD ;READ lFFt DATA TOA4 OIf7FFI.114 ;8IT TEST,7 OF A4 '7.114 ~ 8IF\AQ,.z., GO TO X:I X3 ;I!IFI.AO NOT SET ;LOAOAOo3H IIf3.AO ;3HT07fF.1 AO.OIflFFt IH'tF.AI ;LOAD AIeIFH ;IFHT07FFD AI.OIf7FFD 0If7FF1.A4 '7.114 X4 ;READ 7FFIDATA TO A4 ;8IT TEST 17 OF A4 ;F MUG,.z.t GO TO X4 ;a.fIAG NOT SET ;LOAD AQ.IH "'4,AO ;4HT07FF1 AO.,ltlFFt ;LOADRt. IH'8.At ;8HT07FFD AI.OIf7FFD HITACHI Hitachi America,Jtd .• San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300 Section 4127 - - - - - - - - - - - - - - -----_.._ - - - - APPENDIX" A " 1.0 PROGRAM NAME . " CHR·BCS.MOT " 2.0 ADDRESS RANGE • " COOOH . CIAEH " 3.0 PROGRAM DESCRIPTION • CLEARS SCREEN, CHECKS BUSY FLAG, AND DIS PLAYS 4 LETTERS " KASH " ON THE LCD LM200 PANEL STARTING AT THE 8TH CURSOR POSITION. Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94!>D5-1819 • (415) 589·8300 126 7.4.4 "S" Record Conversion: To convert a file to "S" record format execute the command shown; o Enter CNVS.EXE KY.ABS (The extentions are not necessary) As a result of the conversion process an ASCII coded file is. created with "·.MOT" extention. In this case, it will be KY. MOT. 7.4.5 To Up-load a File: Change directory to "PROCOMM" i.e. C:\PROCOMM. Then execute the following commands; Enter - " PROCOMM " ( Load the PROCOMM package) Set the serial communication line to 9600 Baud, NPTY, 8 Bits, 1 STOP Bit, Full Duplex, with ASch code. At the HMS > prompt, enter - TL ( For Terminal Load ) PUSH down" Shift/Edit "key. Press" Page Up" key. The list of upload protocols appears. PUSH up the " Shift/Edit " key. Choose " 7 " for " ASCII" protocol. Enter the file name that should be up-loaded in the window e.g. C:\H8-5O prompt will appear on the screen, if there are no line errors. e.g. . .............................. . Address Range COOO - C1AE HMS>. o o I o o o o o o o o I NOTE: 1.0 If there are any transmission errors, hit reset switch "SW3". 2.0 At the HMS > Prompt, Enter "TL" and repeat the upload process. 7.4.6 To run the " KY .MOT " program frorn the address range shown above, using the Hitachi Monitor System (HMS) on the H8/532 Evaluation Board, execute the following command; HMS > G COOO (Return) .•. [Refer to H8/532 Eval. Board Software Manual for more details]. 7.4.7 To run another program, push NMI switch "SW2" on the H8/532Eval. Board, and at the HMS > prompt, enter "TL" and upload a new ASCII file. HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy., Brisbane, CA ~4005~1819 • (415) 589-8300 Section 4125 4 7.4 Code Assembly Procedure: Software code development procedure for this application is described in greater detail in this sub-section. The development tools and other commercially available packages used in this project are briefly addressed. No attempt is made to describe these packages in detail. Please, refer to their User manuals when in doubt. A working knowledge of the MS "WORD", "PROCOMM", and MSDOS in the PC environment is assumed in describing this procedure. Multiple code development stations were built with identical tool environment and allow the execution of this procedure. 7.4.1 User program: 7.4.2 Invoke Assembler: To invoke the assembler the following steps are recommended; The source code is written in assembly language for the H8/532 micro processor. The data is entered at location counter H'COOO and a Microsoft "WORD" fIle is created with " *.DOC" extension under MSDOS operat ing system for the laptop PC. This file is copied to the C:\H8-500\ASM directory with "*.SRC" extension e.g. KY.SRC. Note: 1.0 The "*.DOC" file should be unformatted. 2.0 User program code space may vary from H'8000 to H'FOOO. o Change to the directory - C:\H8-500\ASM o Enter - H8ASM KY.SRC (The extension is not necessary) As a result of the assembly process, "KY.LIS and KY.OBJ" files are created. Also, the number and types of assembly errors are indicated. If the number of errors, exeeds 0, then go back to "WORD" and examine the "KY.LIS" file to see where the errors were made. Find the correspond ing errors in the source code file, and correct them. This process may have to be repeated many times until all the assembly errors are removed. 7.4.3 Linker: When there are no errors in the assembly process, generally, a hard copy of the "*.LIS" file is made for software documentation process. By providing adequate comments in the source file, software debug process is made easier. The multiple object fIles are then linked using the linker. To link a file execute the folowing command in the C:\H8-500\ASM directory ; o Enter - LNK KY.OBJ (The exension is not necessary) The linking process generates the file" KY.ABS ". It is to be converted to the Motorola "S" record format for up-loading to the H8/532 Evaluation Board for execution. Section HITACHI 4 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 124 7.3 Initialization Flow Chart : (CNT'D.) Write I/O Port "7FFIH" = BH Write I/O Port "7FFOH" = OH r-------------------, - I Select Instruction register "B" I IL _Set Cursor UlByte "O"H __ _ _Address ____ ___ _______ I - I Select Instruction register "c" I IL _Send Code "H_For" _ _Character ____ _ _"4B __ _ _K _"_ _ _ _ I - I Select Instruction register "0" I IL _Send Mode Contol register "3C"H DISP =ON __________________ I o Write I/O Port "7FFlH" = CH Write I/O Port "7FFOH" = 4BH r-------------------, o Write I/O Port "7FFlH" = OH Write I/O Port "7FFOH" = 3CH ~ ~ r-------------------, ~ o '-_Ini_·tl_·ali_·_za_tl_·o_n_C_o_m_p_l_et_e_ _ _- ' - [ Displays "K" =============J NOTE: 1.0 Busy Flag Check code sequence is indicated by" 0" 2.0 For code details in Graphics or Character mode, see the Appendices. 3.0 After Initialization, normally the display is cleared by writing character code for a blank "20 H" in the display buffer memory or by writing "0" in the graphics memory space. If the LCD screen is not cleared, power on random memory data will be displayed. 4.0 For programming details, refer to the HD61830B data sheet. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4123 7.3 Initialization Flow Chart : Power on initialization flow chart is shown in this sub-section. The consecutive I/O instructions and their brief description is also listed. POR - Initialization Start r------------------, Disp="OFF", Slave Mode, Hp=6 I I ~------------------~ Write I/O Port "7FFIH" = OH Write I/O Port."7FFOH" = 1CH o Write I/O Port "7FFIH" = IH Write I/O Port "7FFOH" = 95H o Write I/O Port "7FFlH" = 2H Write I/O Port "7FFOH" = 27H o Write I/O Port "7FFlH" = 3H Write I/O Port "7FFOH" = IFH Ir------------------, Select Instruction register "0" I Set Mode Control register to "I C"H ~------------------~ Ir------------------, Select Instruction register "1" I Set Character Pitch register to "95"H ~------------------~ Ir------------------, Select Instruction register "2" I Set # of Horiz. Characters register to "27"H ~------------------~ Ir-----------------, Select Instruction register "3" I L __ _Inverse _ _ _Duty _ _Cycle _ _ register _ _ _ to _ ''IF''H ___ Set ~ o Write I/O Port "7FFlH" = 4H Write I/O Port "7FFOH" = 8H r - SelectInstruction register "4"- - - - - , I I L __ _Cursor ___ _ _ _register _ _ _to_ ____ ~ Set Position "8"H o Write I/O Port "7FFIH" = 8H Write I/O Port "7FFOH" = OH o Write I/O Port "7FFIH" = 9H Write I/O Port "7FFOH" = OH o Write I/O Port "7FFIH" = AH Write I/O Port "7FFOH" = 8H r - Select Instruction register "8"- - - - - , Set Display Start Address L/Byte to "O"H ~-----------------~ I I r- --I SelectInstiiictionregister "9"- - Set Display Start Address UlByte "O"H ~-----------------~ r - "S"eIecTIiistrucnon regtster''A''''- - - - - , I Set Cursor Address L/Byte "8 t1 H I ~-----------------~ Section HITACHI 4 Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 122 7.0 SOFTWARE : Software section covers I/O addressing, Busy Flag Varification, Initialization Flow Chart, Code Assembly Procedure while Appendices show the program listings. 7.1 I/O Addresss : Referring to the H8/532 Evaluation Board Hardware Manual From Hitachi Micro Systems Inc. (HMSI), the Expansion Bus I/O space is located from H'7FFO to H'7FFF for expanded minimum mode 1· memory (64 KBytes) space. Read the H8/532 documentation for more details. On the LCD Interface Board this space is further decoded. "MOVTPE" and "MOVFPE" instructions to or from the1/0 addresses H'7FFO or H'7FFI are used for data transfers. These I/O addresses are memory mapped. The first write data to address H'7FFl specifies one of the 13 instruction registers inside the HD6I830B. It is followed by a second write to the I/O address H'7FFO which sends the data to the data input regiser inside the HD6I830B. Therefore, two sequential peripheral write commands are required. Fore more details, see the HD61830B data sheet. Similarly, reading the I/O address H'7FF1, allows the programer to check the Busy Flag before sending a a second instruction when the first instruction is being processed by the HD6I830B LCD Controller. In the same manner, reading the I/O address H'7FFO, provides the programer output data at the current cursor address. The I/O address (Hex) table for read or write operation is shown below: I/O ADD. 7FFl 7FFl 7FFO 7FFO OPERATION READ/WRlTE DATA BUS D7 D6 D5 D4 D3 D2 DI DO Write Instruction Reg. Bits (13-10) Read Busy Flag (B/F) Write Data,Character Code, or Graphics Byte(W7-WO) Read Data, Character Code,or Graphics Byte (R7-RO) 00001312I11O B/F D D D D D D D W7 W6 W5 W4 W3 W2 WI WO R7 R6 R5 R4 R3 R2 Rl RO NOTE: "D" implies Don't Care. 7.2 Busy Flag Check: Emperically, his determined that if the MPU processes consecutive I/O data instructions faster than FOUR "CL2" cycle times, the Busy Flag Check is required. In this application, f CLZ is 500KHz i.e. 2us cycle time. The four cycle times would make the HD61830B instruction execution time of 2x4 = 8us. The H8/532 MPU operating with 16 MHz crystal provides 8MHz (T=125ns) "Phi" clock. From the Instruction Execution Table, "MOVFPE" or "MOVTPE" instruction requires 13 to 20 "Phi" clocks. With, faster time, i.e. 13 "Phi" clocks, it will take 13x 125ns = 1.625 micro-seconds. The two consecutive I/O Instructions will require at least l.625 us x 2 = 3.25 micro-seconds. Since, MPU Instruction time (3.25us) is substantially faster than 61830B instruction execution time (8us) the Busy Flag Check is required in this application. This was also varified in the laboratory. HITACHI Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 121 ~..~ iii TUTORIAL-80FTWARE DEVELOPMENT HD61830B/LM200 LCD Panel Desien--Schematic U1 eND. PIN 7 u? vee, PIN 14 J * A2 .0 "'3 •• A4 A'I Aft 0' :!o I.~rU..L: ~ A !YO ...,.,..:;:;. lVl IV2 IV] -:0 vc~ ::t! Ie Ie ~~ 24 21" ct . III * • o. 04 D'S 0' 0' HM6116 1 •• 21 0 T1 ru • .. .0 II £XIIIO . . . . . II :: ~ * 8c J2 ARE FROM H8/53 2 EVRLURTION BORRD *U ,U* 1 2 , U3 , U4 , US, U6 AND Y\ EACH HAVE A 0.01 uF CAPACITOR BETWEEN VCC AND ~ROUN D. T3 . :: :H= ~lr~""'i''''''~!~~I.:i •• :f~ ='- c. ;;f:' .• "' ~ ;f ~l, 1 AOER ,.u, n 10 ~ ,JJ£;0 ~ J1 •• hL. LCD v.....v PO WE R • •••, 2. ~ffL.:~CC ••,• • ..fi'l; • I-- ~Iffi IlL 1)2 03 ~ ",ec~ 1J2 ';ol~JJ~11IIII ILEe. ELEC. CI r ....... vuu NU uo OU•• LI "'1 ::;: ~~ u'" I l'iK.l/4W "'L:::=i:======:::::::.J ~ ::~ :~ :~ ~ :~o .~~ p ~ I HITACHI L.CD PANEL LM200 NOTE: 1.0 Test Connectors Tl,T2, and 1'3 are for test and debug. 2.0 After power on reset, Display is "OFF", Slave Mode "ON" ,and Hp =6. Section 1204 HITACHI Hitachi America. Ltd.' San Francisco Center' 2000 Sierra Point Pkwy., Brisbane. CA 94005-1819 • (415) 589-8300 HD61830B/LM200 DESIGN-SPLIT LEVEL SCANNING LCD Interface Board-Schematic NOTE. U7 GROUND. PIN 7 U7 +SY. PIN 14 U2" U6" T2 AD Al A2 113 A4 AS A6 A7 A8 J 1* A' Al0 (RED E R/W f-L-hH.- PHI GROUND (alACK) M ao Bl 12 B3 84 81 HITACHI LCD PANEL B6 87 -LM212l12l A 8 110 1'1'0 1'1'1 1'1'2 1'1'1 lC ZVO itO 2'1'2 ZC 2'1'1 2'1'3 U4" *Jl AND J2 ARE FROM BOARD. H8/532 EVAL. ** EACH I.C. HAS A 12l.11I1 CAP BETWEEN vec AND GROUND. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 119 5.2 LCD Display Timing: LCD panel LM200 feature highlights are summarized along with some of the timing calculations for 1/32 duty cycle. 5.2.1 LMlOO Features: Its pertinent features are listed below; 5.2.1.1 Power Supply - ( VDD - Vss ) = 7V Max - (VDD -YEa) = 13.5 V Max 5.2.1.2 Input Signals: 0.7 x5 =3.5 V (High), 0.3x5 = 1.5V (Low) 5.2.1.3 fCL2 Dot Clock Frequency - 390KHz (Min.), 460KHz (Typ.), and 520KHz (Max.) 5.2.1.4 Duty Cycle - 1/32 5.2.1.5 Power Supply For LCD Drivers - 8.1 V (Ta=O°C), 7.4V (Ta=25°C), and 6.5V (Ta=50°C) 5.2.1.6 Scanning - Split with top half panel during "01" and bottom half panel during "02". 5.2.3 LCD Interface Board Design: To meet the features shown above, the design data is presented in the following description : o Power Supply - VDD = +5V, Vss=O, and VFP. = -5V o Input Signals - CMOS levels o fCL1(2 - 500KHz o Duty Cycle - 1/32 o Scanning - Split as provided by the LCD Controller HD61830B o LCD Driver Voltage - 4.7SV ( V0) , variable through contrast adjustment pot. 5.2.4 LCD Timing: All the calculations are based upon the data provided above. They are summa rized as follows : o <; = FCL1(2 = 500 KHZ implies that if a 8 MHz crystal oscillator used, a divide by16 counter is required to produce a square waveform signal. Therefore, the dot clock time is 2us. This is an external oscillator and the jumper "110" is set to "C-2" position. See the schematic in section 6.0. o T CL1 = Row scan time for 240 dots horizontally, is 240x2 = 480 us = 0.48 ms o With Duty Cycle = 1/32, LCD AC drive = MA = 32 x 0.48 ms = 15.36 ms o ~ = = = = 2H 2x15.36 ms 30.72 ms. Therefore, MB Frequency 32.55 Hz. Since, it is not a h~.·Jnic of the line frequency, there will not be any visible flickering of the LCD display. Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 118 5.0 LM200LCD PANEL DISPLAY CRITERIA: This section describes the display buffer memory capacity calculations and the LCD Display Timing related information for the LM200 LCD display panel. For the LM200 panel specifications, refer to the Graphics Panel Catalog from the Hitachi, ELT division. 5.1 Display Buffer Capacity: LM200 panel can display 64 dots vertically, and 240 dots horizontally. This implies a display of 64 x240 = 15,360 bits in graphics mode where a dot represents one LCD pixel on the panel. This would be lesser than ·16,000 pixels that would be provided by a 2K by 8 SRAM in one bit per pixel mode. Allowing for scrolling, and other software overhead, this space was increased to 4K bytes. Therefore, the LCD Interface Board was designed for 4K bytes using two HM6116ALP-12 SRAM parts. Character Mode: The built in character ROM inside the HD61830B Controller is used. 5 dots(W) by 7 dots(H) character matrix is used with 6th column, 8th, and 10th rows as inter-character space. The cursor is set for the 9 th row. With this data, 240/6 =40 characters can be displayed per line. There can be 64 /10 =6.4 i.e. 6 lines of character display resulting in 4Ox6 = 240 characters per panel. By changing the charac ter definition matrix , different numbers of characters can be displayed. Also, note that the HD61830B LCD Controller allows display 002 different 5dots(w) x 1Odots(h) characters. By using an external EPROM, special characters can also be displayed. Graphics Mode: By defining horizontal pitch (Hp) to be 8 dots, and 1 bit per pixel, 1 byte in the display memory would represent 8 LCD dots in a row. Note that, the horizontal pitch can be 6,7, or.8 dots per byte to be displayed. With Hp=8, 240 / 8 = 30 bytes of graphics data can be displayed per a row of dots. Since, there are 64 rows, a total of 64 x 30 = 1,920 bytes of memory can be displayed on the LM200 panel. Note that even though LM200 panel is a split panel scanned as "D 1", and "D2" halves, with 1/32 duty cycle, the display memory space is contiguous. Observe, the buffer data inversion when it is displayed on the LM200 panel. For example, buffer data "33H" is displayed as "CCR" on the panel. Therefore, desired display data has to be inverted and then written to the display buffer. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra POint Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 117 §~ w I] .4 4.3 Display Memory Read Timing: Refer to the SRAM data sheet for Read Cycle (1) timing diagram. The timing comparision between the HD61803Band the HM6116ALP-12 SRAMparameters is done below. Only the critical parameters are addressed: PARAMETERS Sym~l HM6116ALP HD61830B UNITS 4.3.1. Read Access Time 120 650(Max.) ns 4.3.2 Data Setup Time 65(Max.) 50 ns 4.3.3 Data Hold Time lO(Min.) 40 ns NOTE: Any EPROM or SRAM with access time faster than 450 ns and meeting the above parameters would be sufficient for memory read in this application. EPROM may be used as a external a custom character generator for special characters. 4.4 Conclusion : Since, the external clock frequency "CR" in this design is only 500KHz, no critical memory parameters are voilated. However, for faster panels, th;~ analysis is very important. Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 116 4.0 DISPLAY MEMORY TIMING : This section describes the display buffer memory read and write timing. The Hitachi HM6116ALP-12 SRAMS ( Q=2 ) with 120 ns access time make up the 4096 byte buffer. For the detailed read I write timing diagrams and their parameters refer to the HD61830B data sheet. To see the SRAM data sheet refer to the Hitachi Memory Data Book :IIMI1. 4.1 Timing Data : o If the External Clock "CR" (Refer to the schematic in section 6.0) on the LCD Interface Bow is set to 2 MHz, then Tca. = 500 ns . o Tl = Memory Data Refresh Time for Upper Screen = 4Tca. (For Horizontal1\. = 8) = 4x500=2,OOOns=2us. Note: For 1\. = 7, T1 = 1.5 us, while For 1\.=6, Tl = 1.0 us. 1'2 = Memory Data Refresh Time for Lower Screen = 2Tca. = 2 x 500 = 1,000 =1 us. T3 = Memory Read I Write Time = 2 x TCR = 2 x 500 ns =Ius. o o 4.2 Display Memory Write Timing: In the SRAM data sheet, use the Write Cycle (1) timing diagram. The comparisi(m of the HM6116ALP-12 parameters and the Hitachi HD61830B memory write timing is listed below: PARAMETERS --Symbol HM6116ALP HD61830B UNITS 4.2.1. Write Cycle Time fwc 120(Min.) 1000 ns les To Write End lew 70(Min.) 600 ns 4.2.3 Write Recovery Time lwa O(Min.) 350 ns 4.2.4 Write Pulse Width ~ 70(Min) 150 ns 4.2.5 Data To Write Overlap low 35 (Min) 150 ns 4.2.6 Data hold From Write Time foo O(Min) 10 ns 4.2.7 Address Setup Time tAS O(Min) 350 ns 105(Min) 450 ns 4.2.2 4.2.8 Address Valid To Write End tAW HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 I ill Section 4 115 3.0 MPU READ / WRITE TIMING : This section describes the various H8/532 Evaluation Board and the HD61830B Hitachi LCD Controller specifications and arrives at the design trade-offs. Refer to the timing diagrams in the HD61830B and the H8/532 single chip MPU data sheets for more details. PARAMETERS Symbol H8/532 EYAL. BOARD HD61830B UNITS 3.1 "E" Clock Cycle Time tcyc 800 * 1000 (Min.) ns 3.2 "E" High Pulse Width twm 370 * 450 (Min.) ns 3.3 "E" Low Pulse Width lwa 370 * 450 (Min.) ns 3.4 Address Hold time tAli 20 10 (Min.) ns Address Setup Time tAS 180 140 (Min.) ns 3.6 Write Data Hold Time ~HW 30 10 (Min.) ns 3.7 Write Data Setup Time ~ 440 225 (Min.) ns 3.8 Read Data Hold Time ~H o (Min.) 20 ns 3.9 Read Data Setup Time ~DR 40(Min.) 225 ns . 3.5 NOTE: * Timing specifications of the HD61830B are violated. Problem: The H8/532 Evaluation Board running with 20 MHz crystal produces a 10 MHZ "PHI" clock. It is further divide: ',,\wn and results in 1.25 MHz " E " clock with 50% duty cycle. Solution: Run the H8/532 Evaluation Board with a 16 MHz crystal. This results in 1 MHz "E " clock. In this manner, by slowing down the " PHI " clock, the problem mentioned above is res()lved. This is the reason for installing the 16 MHz crystal on the H8/532 Evaluation Board. Section HITACHI 4 Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 114 HD61830B I LM200 SOFTWARE DEVELOPMENT STATION HITACHI LAPTOP COMPUTER LCD INTERFACE BOARD (*) I r-- ".-.. HD H8/532 EVAL. J1 4" !---'- J1 I- - 61830sJ1-{ 4 KB BUFFER ~~ '-' r-- (""'I 4" BOARD J2 !---'- J2'I'-' I IpOWER I '-' ,J~~ , ( L-, EXT. LCD POWER • NOTE: LM200 '--' ( J4 .. LCD PANEL 12" J 1.0 8 MHZ OSC. DIVIDED DOWN. 2.0 SET "J1" JUMPER TO "C-2" POSITION. BLOCK DIAGRAM HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 113 2.0 DESIGN OVERVIEW: (CNTD.) 2.5\ Software Tools : The laptop PC resident software development tools, packages, and utilities are described very breifly. H8 /532 Cross Assembler: It is designed for DOS environment inside the laptop Personal Computer. When the user program is submitted as the source file, it assembles the code. Consequently, it produces Object and List fIles of the source program. The list fIles with " *.LIS " extentions are reproduced in the appendices for the programs developed on the software work station. H8/532 Linker: To link various object code segments (" *.OBI " extention) developed in parallel for a larger program. The linked file has" *.ABS " extention. Motorola" S "record Conversion Utility: It is used to convert the machine code into Motorola" S " record format for uploading it to the H8/532 Evaluation Board. The converted file has" *.MOT " extention. Up Loading Of Laptop PC "S" Record fIle: Push" EDIT SHIFf" Key down. Depress the " PO UP " key when using" PROCOMM " package for communications. Also, select ASCII format. Screen Editor: Any word processing package is acceptable. In this application, Microsoft "WORD" package is used. The source programs are created and edited with this package. The source program files have " *.SRC " extentions. File Management Utilities: To help aid the program development, packages such as" XTREE ", or " TREE86 " may also be used. Back -Up Utility: It is a good practice to back up program fIles. Such packages as "FASTBACK ", OR " FASTBACK PLUS" can also be used. The software development station block diagram is shown on the next page. Section HITACHI 4 Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 112 2.0 DESIGN OVERVIEW: The LCD display subsystem components such as H8 / 532 Evaluation Board, LM200 display, LCD Interface Board, Hitachi Laptop Computer, and the related software are described in this section. At the end, a subsystem block diagram is also presented. Forthe HD61830B LCD Controller, and the LM200 LCD panel data sheets, as well as other related documentation refer, to the Appendix "C" . . 2.1 H8I532 Evaluation Board: This board was designed by Hitachi Micro Systems. It is provided as a training and development tool. On-board EPROM contains the Hitachi Monitor ftrmware used for single line assembly, disassembly, line editing, and debug purposes. Of the two serial ports, only the Terminal .port is used to down load, up load, and run the programs. The 1/0 extention connectors "JI" and "J2" are used to connect to the LCD Interface Board. The partially decoded extented 1/0 space is further decoded on the LCD. Interface Board, This board is designed to run at lOMHz and uses a 20 MHz crystal for that purpose. However, in this application a 16 MHz crystal is used to provide 1MHz "E" clock to the LCD Controller HD61830B. All the jumpers on this board are set at the factory according to their default states. 2.2 LM200LCD Panel display: This display is provided by the Hitachi ELT Division. It is capable of displaying alpha-numeric characters as wellas the graphics data. It is 240 dots wide and 64 dots high. It has 1/32 duty cycle. The serial data is clocked in at 500KHz. It runs from +5V, and-5V power supply. The customer has to solder the pins on LM200 for the appropriate connector used on the LCD Interface Board. The LM200 LCD panel mounting and the proper viewing angles are critical to a strain free LCD display. Please, handle the panels according to the care recommended by the LCD display manufacturer. The logic signals sent to the LCD panel are at CMOS levels. External power supply was used for the LCD panel. 2.3 LCD Interface Board : Awire wrap board was built to control the LCD panel LM200. It also exchanged data with the H8/532 Evaluation Board over the 1/0 extention cables "Ji'" and "J2". The Hitachi LCD controller HD61830B was used on the LCD Interface Board. A 4,096 byte display buffer memory was also designed to store the character or graphics data. The 500KHz dot clock required by the display was also provided on this board. The LM200 LCD panel contrast adjust potentiometer was also put on this board. Set the jumper "JIO" on this board to the "C-2" position. Test connectors were also provided to help debug this board. 2.4 Hitachi Laptop Personal Computer "HL320" : It is connected to the serial terminal port of the H8/532 Evaluation Board. 1Jle connector RJ-12 is attached to the Terminal port while a male to female 25 pin adapter cable is required at the Laptop PC end. The Hitachi "HL320" PC provides the software development tools for the user programs. The program up load and down load capability is also provided by the laptop PC. The communication link is full duplex, 9600 baud, 8 bits, 1 stop bit, and no parity check. HITACHI Hitachi America, Ltd .• San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Section 4 111 1.0 INTRODUCTION: This section describes the design goals, LCD display subsystem with its components, provides a general overview of this presentation, along with a software development station block diagram, and the organization of the other sections in this document. The design goals established for this project are briefly listed below: 1.1 To use H8/S32 Evaluation Board with Monitor Software. 1.2 To provide LCD display with LM200 panel from Hitachi. 1.2 Alpha-Numeric and Graphic display capability. 1.4 To design Interface Board for the LM200 LCD panel. 1.S To write programs for debug and test. 1.6 To Use Hitachi Laptop Personal Computer "HL320". 1.7 To use readily available software at Hitachi Field Offices for development. 1.8 To build multiple HD61830B programming stations. 1.9 To generate HD61830B / LM200 panel design tutorial. A brief description of the LCD display subsystem components listed above is provided in the next section as general overview. To complete the overview, a subsystem block diagram is also presented. The rest of the sections described in the Table Of Contents are expanded in greater details along with their technical data. The Appendices give the program listings, and also list the referenced literature. A copy of the LCD Interface Board schematic is also provided to illustrate the implementation details of this application. Section HITACHI 4 Hitachi America, ltd. ~ San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 110 TABLE OF CONTENTS TOPICS PAGE 1.0 INTRODUCI'ION ------------------------------------~----------------------------------------- 110 2.0 DESIGN OVERVIEW 111 3.0 MPU READ I WRITE TIMING 114 4.0 DISPLAY MEMORY TIMING 115 5.0 LM200 LCD PANEL CRITERIA ------------------------------------------------------------- 117 6.0 LCD INTERFACE BOARD SCHEMATIC 119 7.0 SOFIWARE 121 8.0 APPENDICES ---------------------------------------------------------------------------------- 126 APPENDIX "A" -. CJiR-BCS.LIS ------------------------------------------------- (CHARACI'ER MODE - FOUR BYTE DISPLAY) 126 APPENDIX "B" - GRA-BCS.LIS ------------------------------------------------- (GRAPHICS MODE - FOUR BYTE DISPLAY) 133 - REFERENCE LITERATURE 140 , APPENDIX "c" -------------.------------------ HITACHI Hitachi America, ltd .• San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 109 Section 108 4 HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589;8300 May, 1990 HD61830B / LM200 Panel Design TUTORIAL Kash Yajnik: This tutorial presents in depth design process for a LCD subsystem.ltsmajorcomponems include HB/S32Evaluation boardas the local processor,LCDControllerHD61830B, and the display paDel LM200 from Hitachi ELT Division. The HD61830B controller is designed to run in the c:haracter or graphic:smode. The H8!S32 EvaluationBoard is designed by HitachiMk:rosystems. TheLM200LCDpanelc:andisplay 240 Dots(W) by 64 Dots(H) character or graphics data. Hitac:hiMonitorfirmwareresidenton theH8/S32 Evaluation Board provides the program debugging and bost computer c:ommunicationfac:ilities. . Byaddingalaptopcomputertodownloadtheprogramsto the Evaluation Board, a program development station can be readily builL TheH8/S32Cross Assembler,Linker, anyword processor package e.g. "WORD" as screen editor, and Motorola "S" record conversiQn utility inside the Hitachi laptop PC comp1et.etbe software development environment. The ''PROCOMM''c:ommunic:ation package is used to facilitate down load or up load of programs to the H8/S32 Evalu- ation board. Theseprograms arelistedintheAppendices "A" and "B". No eft'ort Is spent in either code or logic minimization. \, This tutorial is intended for the technical staff at customer sites andotherHitachi employees who are fairly familiar with LCD design guide lines. Therefore. baSic LCD design principles are not covered. \ The HD61830B LCD Controller design tutorial includes Introduction, Design Overview. MPU Read! Write Timing, Display Memory Timing.LM200 Panel Criteria. LCD interface Board Schematic, and the associated Software. While a lot of programs were developed. only two are listed as examples in their respective Appendices. The Appendix "A" shows the listing of the Cbaracter Modedisplay while the Appendix "B" shows the Graphics Mode listing. The Appendix "C" covers the reference literature. Only the details not available in the reference literature are explained at greater length in this article. The page 2 shows ~ the Table Of Contents. 13 In this manner, a number of software development stations were built to debug HD61830B /LM200 display programs. Refer to the susequent pages for more details of this design. HITACHI Hitachi America~ Ltd.' San Francisco Center· :::000 Sierra Point Pkwy., Brisbane, CA 94005-1819 • (415) 589-8300 ( SectIon 4 107 ~ 4 The literature and other documents used in this design are summarized below : H8/532 Cross Assembler Manual #S085CPC and" C " compiler for IBM PC H8/532 Evaluation Board User's Manual # US538EVB21H H8/532 Software User's Manual # HS538EMSSIE MS "WORD" User Manual and other reference manuals " PROCOMM " User Manual and other reference manuals LCD Data Book #M24T013 from Hitachi America Ltd. Memory Data Books from Hitachi America Ltd. Hitachi Graphic Module Catalog # XX-E139 from ELT Division H8/532 Hardware User's Manual #M21TOO2 from Hitachi America, Ltd. H8/500 Programming Manual #M21TOOl from Hitachi America, Ltd. H8/500 Software Application Note #M21 T003 from Hitachi America, Ltd. H8/532 Overview #M21 T173 from Hitachi America, Ltd. Hitachi Laptop Personal Computer HL320 - Operator Manual Hitachi Laptop Personal Computer HL320 - MSDOS V3.2 User's Manual Hitachi HD61830B / LM200 Panel Design Tutorial Part I (in this manual) o o o o o o o o o o o o o o o SecUon HITACHI 4 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300 106 APPENDIX" C " REFERENCE LITERATURE HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4105 TUTORIAL - PART II HD6J830B I LMlOO DESIGN. CUSTOM CHARACTER GENERATIDN CHARACTER GENERATOR EPROM HN27C256AG-15 ADDRESS DATA 053FH OH 0480H 82H lH 82H 2H 82H 3H 82H 4H 82H 5H 82H 6H 82H 7H FEH BH 82H 9H CHARACTER II S II "H" 82H ·····1· AH 82H BH 82H CH 82H ···········1· ................ I DH ...... . 82H Section HITACHI 4 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 104 TUTORIAL - PART II HD61830B I LM200 DESIGN· CUSTOM CHARACTER GENERATION CHARACTER GENERATOR EPROM HN27C256AG-15 ADDRESS DATA 020AH OH f CHARACTER .............................................................................. BH 1·+ OH ............................................. . CH OH 1 "BLANK " DH-..................................................... OH ... -................... . EH .......... OH ........................................ . ..... rn OH 0530H FEH ~~ 1H 02H 2H 02H 3H 02H 4H 02H 5H 02H 6H 02H 7H FEll BH BOH 9H 80H AM 80H BH 80H CH 80H "Sn ............................................................. _ ...... DH 80H ..•................................•.............•.._.......•............_. \1/ EH FEll \1/ HITACHI Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 103 TUTORIAL • PART II HDfi l 8.1OB I tMlOO PESIDN. CUSTOM CHARACtER GENERATIDN CHARACTER GENERATOR £PROW HN27C258AG-15 ADDRESS DATA 0415H 82H 8H 82H ?H 82M BH FER 9H 82H All 82H 8H 82M eH 82M DH 82M CHARAcrER "A" OH 0200H OH .__.-..._._........._....--_.- .-_..- r-'-' 1H OH 2M OH 3M OH 4H OH 5H OH 8M OH - - ---- r-._.- -_.--It BLANK H -_.- --+---+--; 7H OH 8M OH OH SectIon HITACHI 4 Hitachi America. Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 102 .• ~.~ . .= .=~=~~~-----------------~ TUTORIAL· PART II HD6lpm I LMlOQ DESIGN. CUSTOM CUARACTER GENERATIDN CHARACTER GENERATOR EPROM HN27C256AG-15 ADDRESS DATA O4BOK B2H lH 42H 2M 22H 3H 12M 4H OAB 5H 06H 8H 08H 06H CHARACTER "K" 8H 06H _- 9H 06H --- AB OAK BH 12M CH 22H Ell 82M .............. .........;;........ ............•. ....•........ ..••. .•.__........_._............._.-_.._. ....._.. ..-....- .._.........._- .-...._..- ...-.---OK 42M OR ········04i·iiH············· ······~·iiH··· .........~-...-... r·----1H 2M , 4........ __.................. 3H r----.-t---t---1 28H "A" _._._~....... ....____ ............. B2H HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 SectIOn, 4 101 APPENDIX" B " 1.0 EPROM FONT DATA 2.0 ADDRESS RANGE . " OOOH . 3FFH '~ 3.0 PROGRAM DESCRIPTION· CUSTOM CHARACTER FONT PATTERN LISTING FOR "K" ,It A" ,"S", "H", AND "BLANK". 4.0 CHECK SUM • 7F3CAD Section HITACHI 4 Hitachi America, ltd.' .SanFrancisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 100 TUTORIAL • PART II HD§JI.lOB I LM200 DESIGN. CUSTOM CHARACTER GENERATION I7ICHI '''CHI "'CHI C"'" IS7FFIOGI3 CIIAlSI3D CIIAlII1FFCOOII I"CHI 177 CHI CatADGO CIIAIGO rat rat ....'" Cat""" SLEEP ," I"CHI ; I. lat ""'TOTAL . . . . . 0 ""'TOTAL WMNIIIII 0 IIDVI'PII 11M MOVTPI .END HITACHI Hitachi America. Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 SectiOn 4 99 TUTORIAL • PART II H061gBl LM100 DESIGN. CUSTOM CHARACTER GENERATION "SCHR ".CHR tt1CHR It'CHI! Itt CHI! 120CHR 121 CHI! t.CKI lZ1CK1 tZtCKI laCKI laCKI tUCKI tZiCKI tZiCKI t30CKI 131 CKI t.CKI I.CKI IXCKI I.CHR t.CHR 137CK1 I.CHR I.CKI 1«1CK1 14tCHR tcaCHR ,42CHR '6ICHR I.CKI ,.CHR 147CHR I.CKI ,.CKI ISOCHR ,IICHR 152CHR lSI CHIt tYCKI tSSCHR lIS CHIt 187 CHIt tIS CHIt lIS CHIt I. CHIt 111 CHI taCHlt I.CHI IIICHI lIS CHIt tIS CHIt t87CH1t lIS CHIt 11S0IA I711 CHIt InOlA 98 ellGAAa'7 ellOC21F7 ellOEOII ellCFOII elllDOII C.m OIl Cl1tZOll el1tUOIIA C l1is 157FF10D1Q CI1IASICF e I1tC tS7FFOODIt CI121 OIl C11.IS7FFIQQ1M C1121.1Cf7 CI1Z121F7 cl1.aa el1acSODll C11. tS7FFIODIQ C1131 tS1FFOCDla cl1.aa ell. tS7FFtQQ1M CI1 • .ICf7 CI1«121F7 CI1CZOll CI142ac C11. tS7FFIODIQ ... 811T HOP HOP HOP HOP HOP X7 .,. TUT 17 Of ... ;F Ul.AQ.,z.t QO TO X7 J,fUG NOT SET ; INTlAUZATlON END IIOVS IIOVTPe IIOV! IIOVTPe MOP XI: IIf'AoAl All.1H7FF1 IIf'F.At At.1H7FFO ;FIWH :AI!AD 7FFt DATA TO '" :IIf TUT '701' '" ;F BIFI.AG.,z.t QO TO XI ;&f\NJ NOT SET MOP XI: MOP Itf7I'FI .... '7"" XI IIOV! IIOVTPe IIOVTPe IIf'I.AO AII...,7FFt A2,..,7FRI IIOVFPE OH'7I'Ft.A4 811T 11"" XI ;fIUD",,1 DATA TO '" :II1'lI1U7Of ... , ltf\AG.,z.t QO TO XI IIf'C,AI -.at .. NaP NaP ~TOJIIFt IIOVTPI At.1H1FFO ;RI-4IoCCIDIFOII 'It" ;4ITO"" .. .. .. .. IIf7I'Ft.A4 MAD7I'I'1DATATO'" 11"" :lIT 'lIlT I10f '" AII.""",, Mt,llt At.1H1FFO ;IIt.toCClllFOIl 0A" ;4t TO"" XtO ,,",,'.A4 11"" Xtt JlItf\AG.t QO TO XlO ;ItfUG NOT lET ~TOJIIFt MADJllFtDATATO ... :II1''IIIT 11 Of AI ,MUG.t QO TO Xlt iIUG NOT lET IIOVIIII AO.IH7I'I'1 ~T07I'I'1 IIOd IIOVTPI tIIW.Rt ;RI..cclllFOII'W' tlTOJAII IIO\fIII tfflfF1.A1 At,ltf7Fl'll _ JIIFt DATA TORI 1111' 'Xt. 7"" :II1''IIIT I10f AI , u u a . t QO TO XII IIOVIIII IIOV:E IIOVTPI IIOAIH'Im M&Rt ~T07I'I'1 Xtll: IIO\f1II 1111' NaP iIUG NOT lET All.IIf7I'Ft 1111' XI~ ~T01FFO 1If'4IJII Xtt: IIO\fIII NaP "T07FFt IIOVTPE IIOVTPI IIOV:E IIOVTPI NaP .... II)q MOP XtO: IIOVIIPI 81ST NDP IHT01FFO IIOVFPE II)q MOP ;NITO 7FFI ,AtJlt 81ST IN! MOP CI1~It41 ellc,mRaDIt CI1,t OIl C1152 tS7FFtOQU CI187 .ICf7 CI1.21F7 CI1.OII C I1SC 1S7FFt0llD CI1I1 't4t el1.t.,...., Cl1lSaa C illS tl7FFtOQU CI1.11J17 CI171121F7 CII7II0II Cl1l1tmf1al CI1?..t. CI17At. . . . . c.nFOO CII. tl7FFtOQU CIIISIIJI7 CII8721F7 CIIlSaa C11M 117FFt0llD CII."4I ClIl1t. . . . . CI1.00 C1117 tl7FFtOQU CI1CIIJI7 CII.21F7 CII.OO .,.... MUa NOTIIT At.eenM ;RI.tIoCCIII FOIl" ;41 TO JAIl """".AI :111'1111'11 Of AI '7"" XtS ;IIiID 71'1'1 DATA TO RI ;F..ue.t QO TO XIS MUaIDTIII' Section HITACHI 4 Hitaclli America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 TUTORIAL - PART II HP618JOB I LMlOO DESIGN. CUSTOM CHARACTER GENERATIDN 51CHA 58CHA IICHA II CHA e2CHR S3CHR 66CHR MCHR 8ICHR a1CHR MCHR &lCHR 70CHR 11CHR 1ZCHA i'3CHR 1CCHR 7SCHA C117A 157R'OOc181 CII" 00 NOlI CI0IO 157FF1CQ14 XI: C"~ CIII121F7 cacaeoo NOlI CIllASOOI C8C8C 157FF100e0 C., 157FFOOO82 caeoo NOlI C., 157FF1CQ14 XI: C8C8C~ CllllE21F7 ClW)oo HOP CllA15OQ1 CIIA2 '57FF100e0 C1llA4157I'F00082 CIDAD 00 HOP WOVTl'E Rl,0H7fFO ;&ITO 1m WOVFPE BTST SHE OH'/FFl,R4 .7,A1 XI :AEAD 7FFI OATA TO R4 .BIT TESTl1 OF R4 WOV:e WOVTl'E WOVTl'E IHI,AO AO,O.,7FFI A2.OH7fFO :. &1'I.AG"z.1 GO TO X5 Irf'\AG NOT SET :AIWH ;IHT07FFI :QHTO 1m WOVFPE BTST SHE OH'/FF1,R4 ",AI :8IT TESTl1 OF R4 XI ;. &f1.AG"z., GO TO XI ;M'IJ,(l NOT SET 'WOV:e WOVTl'E 1IOVTl'E IH'IJIO ;I.QAI)~ RD.OH7FFI A2.OH7fFO ;III TO 7FFI 11 11 71CHA IICHR IICHA I1CHA aCHA S3CHA MCHA 8ICHA 8ICHA .7CHA 8ICHA &lCHA IICHA ttCHA aCHA IIICHA MCHA .CHA .CHA 17CM1 .CMI • CMI lOOCHA 101CM1 IOICMI IOICMI 100CMI lCIICM1 ICllCMI I07CM1 IOICMI IOICMI 110CMI CllAUI)13 C1DII000 NOlI C1I81157FF1CQ14 01: C. . N:F7 C. . '11F7 ClllAoo NOlI C. . IIGIIA CIIaI,57FFlcao CIIC25I00 Ceoc. 157FFaOOII C1llCl00 NOlI CIIICA Isml. C2: CIOCI' N:F7 CIIIDI wr CIllDlOO NOlI CIIIM . . C"''''''CDO C".'OO C1DQ01"""'" CII800 HOP C._lIP CI: C"OO Col; CIlE7IS7FFtOllM eaa:1IS7 e. . wr eMOO e..,1OOC e1IIF11S7FFtCDO e....,11 HOP ClAW AI ;CI.1AARS IIOVFPE BTST OH'7FF1,R4 ,7,A1 :lIT TUlI7 Of R4 BNE 01 1IOV:e IIOVI'PI IIOV:e IIOVTPI IHA,AO RD.0H7FI'1 ;.UI.AO"z.,ooTOCl ;UUG HOT SET AWH ;AHTO 7FI'I M.RI ;RtoGH R1,OH7fFO :QHTO ~1AoGM IIOVFPE ;II!AI) 7FI'I BNE OH'7FFI,AI ",AI c:a IIOYI IHIJII ~ IIOV'I'PI IIOYS IIOVI'PI ~ ;lMT07FI'I M.RI ;RtoGH R1.1H7F" :QHTO~"'" am 11M HOP IIO\'FIII .. am C4 ;II!AI) 7FF1 DATA TO AI ill DATA TO R4 ;lIT TEST 17 Of AI ;.UI.AO-l.olooTOc:a ;I.fWI HOT 8IET ~"""'14 ;II!AI) 7FI'I DATA TO AI :811' 11S1'''Of AI ., IIIUG .01 00 TO C4 ;l.fWl1IOt lEI' IIO~ IH'C.NI M.OH7FI'1 IH'II.RI ;ADoCH ;QtT07IIP1 ;Rt..aaHoCCDl!FClA ....... IIOV'I'PI R1.1H71'D :2IIM TO "'" sc:u Rl,CI 1IO'n IIOV'I'PI C. .Al.",... C..,OO HOP CI10001.CI10100 HOP .,,"'... "'"""'.... .... ; SCI&N CUNI AOUTIII CCIIU1'ED CI1Ol00 HOP 113 l1cCMI :QHT07FFO ; SCMEN CI.1AA ROU1'1IE START 111 I1ZCMI ;READ 7FFI DATA TO R4 C11011S7FFt0llM X7: IIOWPE '"""'.At ~ 1fF1 DATA TO AI HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 97 TUTORIAL· PART II 8061gB I LMlOO DESIGN. CUSTOM CHARACTER GENERATION I 2CHA 3 ,CHA 5 caaao CIOOQ .1tiD1NQ 'XCG" .SECTION Of\COOUIJQH.2 .ElIPOAT A ORO ~ ~ CHTR o8OCOH ; BUSY F\.AG CHOCKED 7 I CHI! C oocoeooo 'CHI! C8OCOA013 10CHR C1002 AI 13 II CHA C lO0oI A213 12CHR CIOOIA313 13CHR CIOOIAoI13 "lSCHA CIOQAOO llCHR 1·7CH11 ,. CHI! ,.CHA lOCHA 2tCHA 2ZCHA 23CHA :MCHA 2SCHA lIICHR f1CHR lIICHR lIICHR lOCHR :ltCHR 3ZCHA 33CHR "CHR SCHR SCHR 37CHR 3ICHR 3ICHR CCHR "CHR 42CHA 43CHR "CHR 4ICHR 4ICHR '7CHR 4ICHR 4ICHR !IIICHR SICHR UCHR 53CHR .. CHR !IIICHR !IIICHR 57CHR Section 96 4 caaoo CIOOCOO CIOOOOO CIOOEOO CIOOF 157FF100110 CIOIUt10 ClOll 157FROO111 C1011 00 CIOIC ti7FFlOOM CD K:FI CasW7 C_OO C. . IGDI C. . Il7FFlOOIO C1III)51F7 C_ 157FFaCaII CIGI&OO C_1I'IFFIOOM CClAK:FI CIOICW7 C.-OO CfI1II1G112 C10&1 157FF10010 CIO'''''D A: CLR8 $ ;A.eoccH CLR8 CLR8 CLR8 CLR8 All AI A2 A3 IW ;Cl!NI All ;Cl!NI AI ;Cl!NI A2 ;Cl!NI A3 ;Cl!NI1W HOP HOP HOP HOP HOP ; INTlAUATION STAAT ; EXlERM CO ENABlED WOVTPE AO,~t WOV~ IH'ID,RI At.1If7I'1'Q WOVTPE HOP XI; WOVFPI '7~ 8NE XI ;MAD 7PF1 MTA TO IW ;II1'lUT.7OFIW ;F&fUO.z.looTOXI WOVTPE Il0'l:1 IIOVTPE IH'I.AD AO,fH7FF1 1Hf7.R1 AI.1If7I'1'Q ;1.OAI)IIDoIH ;IHT07FF1 ;1.OAI) Rlof7H :F7HT07FFO WOVFPI 8TST ttmFI.II4 IINi! X2 :AEAD 'lFFI MTA TO 114 ;II1'lUTnOFII4 ;F&fUO.z., 00 10 XI IIOY;£ IIfZ.RII IIOVTPE IUH'7FF1 IIOY;£ IIOVTPE IH'ID.R1 AI.1If7I'1'Q IIIMPI tH'7FF1.11& ttmFI.II4 AfUGNOTIET WOY~ HOP X2: 17~ ;I.fUO NOT lIT HOP CIOIOOO NDf' C. . ,I7FF1.... XI: c. .1t:I7 NDf' .. am 17~ XI YOY:I IIOVTPE IIO'tI IIOVTPE NDf' X&: ;011 TO 7FFt ;1.OAI) AI .1111 ;1I11T07FFO am HOP C_I5~ C. . " " Cal. C. . . . CaA'l7FF1OO1O C..-,," CDI'''''''' C. . . Call17FF1.... CIOICIt:I7 C_W7 CIIIIII • CIl7'lIOIM C eon l5'IFFIOOIO CID7I5ICII .eou IIMft 8'IIT 8NE ;1.OAI) IIIWH :2HT07FF1 ;1.OAI) RI.IIII ;1111 TO 7FFO ;MAD7FF1 MTA'ION ;111'1111' 1M ;l'MUG.z., 00 10 XI new ...... ;I.CW) IIIWH AO.IImFI ~T07FF1 IH'IF.R1 AI...".,. i.OIGRI.,PH ;1FMTO"" tH'7FF1.11& .7.11& x. ;MAD"" MTA TO till ;lll'TEII'newtlll ;II 1flM.z., 00 10 X. IIM,AD ;I.QMI . . . . IqH7FF1 ;4HT07FFI i.OIGRlo8I AfUGNOTIIT AfUGNOTIIT HOP IIOY:I WOVTPE WOY;£ IHE.Rt HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300 APPENDIX" A " 1.0 PROGRAM NAME • " XCG.MOT" 2.0 ADDRESS RANGE • " 8000H • 81AFH " 3.0 PROGRAM DESCRIPl'ION • CLEARS SCREEN, CHECKS BUSY FLAG, AND DIS· PLAYS 4 CUSTOM CHARACTERS ON THE LCD LMlOO PANEL STARTING AT THE 8TH CURSOR POSITION. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point P~wy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 4 95 H8/330 Application Note Listing 3· :tNPJ]'f LIS U. HS/lOO ASSEMBLER PROGRAM NAMB - YER 1.1 03/20/91 08111:34 Date Input Routine PAGE "Oate Input Routine" ; H8/330 Print Buffer Routine ; version 2.0 ;wdtten by: Tom Hampton HitaChi Ameriea# Ltd. Application Engineering 8 • 10 248 249 250 251 252 253 proqram 25. 255 256 251 proqram. 258 pro9ram. 259 260 261 proqram 262 proqram • output • print .qlObal C 0000 266 progl'Ul 267 proqr. . 268 proqraa 269 pro9rua 270 proqraa 271 proqraa 272 proqraa 273 proqraJll 274 pro9raa 275 proql'aJI 276 pro9ram 271 proqrUl 278 279 280 281 282 283 284 proqru • section program, code : Input /STB Interrupt Routine C 0000 C 0000 1F827040 input int: - baet.b e : qet input data qet data: JIIov.b Unyort,rOh 0004 C 0004 20BE 263 264 265 proql'AlIl dbg,obj nocret,nosct C 0006 rIFF C 0001 3881 C 0001. 3083 C DOOe 30B6 c 000& 35BF C C C C 0010 4804 0012 0012 rlO2 0016 4002 0016 C 0016 FIOl c C 0011 C 0011 31BA C 001A F.Ol proqr . . C ODIC 31BA. program C OOlB 0805 fibusy_blt, Un_h. ; write data into memory butter IllOv.b 'write, rOl mov.b rOl,lmem dir mov.b rOh,Imem-data IIlOv.b rSl, laddr 10 IIlOv.b rSh,laddr:hi blat wr_cal wr_C80t IIlOv.b twrcaO,rOl bra wr_cont wr_cs1: mov.b twrcal,rOl wr_cont: mov.b rOl,Imem ctrl mov.b .7,rOl mov.b rOl,lmem ctrl adds n, rS - ;set input busy signal : read data :set port direction for write ;.at data ;output butfer address ;write to U3 ;write to U4 :activate write pulse nie-activate write pulae : increment input pointer program C 0020 ODS3 proqram. C 0022 1963 285 proqralll. C 0024 4108 ; test for bufter full IIlOV.W rS, r3 sub.w r6, r3 beq buH_Cull 286 281 288 289 290 291 292 proqr. . C 0026 noe C 0021 7F821240 C ooze 4006 ;butfer i8 not full, but cannot be empty either bclr.b tbuf mt flag, r41 ;clear buffer empty flag bclr.b fibu;y bit,Un hs ;clear IBUSY signal bra clean_ret - program C 002E buff_full: proqr.l.lD. prog-ram. 293 program. C 002B 1Glc bset.b 2 •• 295 program 296 e belr.b 0030 7F827220 300 program ; reset input delay timer clean_ret; mev.w tO,rO rO,@Crt_fre ; reset delay timer C 003e 1F911230 ; enable delay timer interrupts bclr.b t3,@frt_tcsr :clear 301 302 303 pro9ram tbuf_fl_flaq,r41 ;set buffer full flag : IBUSY remains set tbuf_tul_bit,lstatyort ;turn Buffer Full LED ON C 0034 C 0034 79000000 C 0038 6B80l!"F92 2" 298 proqram 299 proqram. :is lOP" COP 1 :yes co~pare flag 30. 305 program C 0040 5610 306 301 rte .end *****TOTAL ERRORS * * * * *TOTAL WARNINGS HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 67 HS/330 Listing 4' ,..,.. * Application Note otr.rPtJT LtS H8/300 ASSEMBLER 03/20/91 08:11:43 Data OUtput Routine VER 1.1 PROGRAM NAME - PAGE "Data output Routine" • heading 188/330 Print BuUer Routine ;verdon 2.0 ;written by: Tom. Hampton Hitachi Amedca, Ltd. Application &nqineerinq • 10 241 2 •• 250 251 252 253 program 25. 255 256 257 2S1 program • output • print dbg,obj nocret, nOlet . global c . section 0000 program, code :Data OUtput Service i input delay timer interrupt C 0000 C 0000 1F827040 output int: - bnt.b 260 261 262 program 263 program 2" 265 . C 0004 7JOe C 0006 464E ;test for buffer empty btst.b fbut mt t'lag,r41 bne ret1-- ; is buffer empty ? ;yes 266 program C 0008 7£877300 267 program 2 •• 2" 270' program C DOOe 46U :test for output busy but.b lobusy_bit,@out_hs bne retl : output busy ? ;yes 271 program. c C OOOE ?3lC 0010 4644 Iteat tor output hold bUt.b lohold flag,r41 bne retl- :output on hold? : yes 259 pro9ram 272 273 274 275 27' 271 27' 27, 280 281 program C 0012 FlOO program C 0014 )8Bl program program progralll. program program 282 prograll C OOlC rlOEi COOlS 4002 302 program 3Q3 proq .... C 0038 FlU C 003A 38Ca C oozo raos 0022 C 0022 31BA r61,hddr 10 r6h,laddr-hl rel_csl- mav.b bra frelc.O,rOl rel_cont lread frOJll, Ul Irdcs1,rOl ; read from U4 e C 0028 38BA C02A OB06 mov.b rd cant: mov.b mov.b mov.b mov.b adds C 002e 3088 :output data. to port mov.b rOh,@outyort e C 0024 20B3 C 0026 riO? C 002E C 0030 raoo lice C 0032 2ac, C 0034 F816 C 0036 38ct : output buffer address rOl, Imam ctrl :activate chip select pulse ' . .m data, rOh : !Jet outpu~ data 17,rQl rOI.lmam ctrl Ide-activate write pulse fl, r6 ;-increment output pointer : generate output data strobe m.ov.b tO,r01 mov. b r01.@tmrO tent mov.b @tmrO tcs;,rOl m.ov.b th'16-;-rOl mov.b rOl,@tmrO_tcsr mov.b mov.b Ih'4l.rOl rOl,@tmrO_tcr :output data : clear counter tread flags :generate a negative strobe : 2.4 usee wide and clear flags :enable compare A interrupt C 003e 0700 ;enable interrupts for strobe generation ldc fO,ccr tenable interrupts C 003E 0180 :wait for output strobe interrupt sleep 307 308 310 311 I C 0040 0780 313 314 315 proqram C 0042 0063 316 proqram C 0044 1953 68 : set port direction for read mov.b mov.b DIal 0020 304 305 312 progrilftl. ; set input busy 81qnal C OOlC e 309 program. Iqet output butfer data mov.b Ire.d,rOI mov~b rOl,@mem_dir C 0016 3U' e 0011 301' C DOlA 4804 283 program 284 proqram. 285 program 286 program 287 proqram 288 program 289 program. 290 program 291 2.2 293 program 2 •• 295 296 program 297 program 298 program 299 program 300 program 301 306 program tibusy_bit. Un_hI d.isable interrupts ld.c fh'aO,ccr ;test for buffer empty mov.w r6,r3 sub.w r5, r3 :mask interrupts I temporary work register lDP ? lis ODP - Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589-8300 HS/330 Application Note Lhti-nq 4' pP'J:PQT LIS (conti-nu@dl 317 proqull boq C 0046 noc 318 .... H8/300 ASSEMBLER VER 1.1 ••• : teat for in full area 320 program 321 proqralll 322 323 proqull 324 proqram 325 prooram 320 327 328 program 329 program 330 331 332 pro9uIl 333 program 334 program. 33. 336 pro9r&JI 337 pro9rall 331 330 340 341 342 343 344 3.' 346 PAGE Data OUtput Routine PROGRAM NAME - 319 03/20/9108:11;43 e 0041 OI4B C aOtA 451& actd.b be. C aOte 1Z1e COOtS 11'821020 bclr.b tbuf n baet.b bra tbu()ul_bit,htatyort ;turn Buffer Full LED OFF retl e 0052 4002 C 0054 e r4h, r31 : h buffer at ill full? ;yea ret2 flaq,r41 ;clear buffer full flag : set buffer empty flag buff_lilt: : set buffer empty flag 0054 'JOOC C 0056 0056 '34C c 0051 nOI e : should lOUSY be cleared '] retl: btat.b tonlin. flaq,r41 beq ret2btat. b C 005A 73le c DOSe 4604 bne I ; is butter full '1 tbuf fl fla9, r41 ret2-- lye. proqr&JI C 005& 71'827240 : clear laUSY aignal bclr.b tibusy_bit, Un_h. program C 0062 ret2; proqull. C 0062 79000000 program C 0066 6Sl0FF92 341 progrUl C Q06A 7F917230 mov.w to,rO rO,@frt_trc : enable delay timer interrupts bclr.b t3, ffrt_tcsr is buffer online '1 :no ; .et IBUSY injlctive : reset delay timer :clear compare flag 348 349 proCJulIl C 006s 5610 350 351 ... ···TOTAL BRRORS ...... -TOTAL "ARNINGS rto • end. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 69 HS/330 Application Note Listing 5' OUT-ST» LIS u. H8/300 ASSEMBLER PROGRAM NAME - VER 1.1 03/20/9108;11:54 output STa Routine . heading PAGE "Output STB Routine" ;88/330 Print Buffer Routine ;version 2.0 ;written by: Tom Hampton Hitachi America, Ltd. Application Engineering 10 248 240 2S0 2S1 2S2 • output dbg,obj . print nocret, n08et . global 253 program . section C 0000 2S4 2SS 256 program C 0000 257 program. 258 program C 0000 FeOl C 0002 31Ce 2S0 260 program 261 program 262 program 263 C 0004 zac' C 0006 rllA C 0008 3aC' mav. b mov.b mov.b program C OOOA 5610 rto 264 program, code :Output strobe interrupt oatb_lnt I mov.b tltrO! mov.b 'rOl,ltmro_tcr 2.S 2 •• @tmrO tesr. r01 fh'1a;rOl rOl,@tmrO_tcsr ;diaable further timer interrupts : read flags ;clear flags, outputs to high level .end ... "TOTAL ERRORS u'" "'TOTAL WARNINGS Listing 6' IN-INtT LtS ...... H8/300 ASSEMBLER PROGRAM NAME - VER 1.1 PAGE 03/20/91 08: 12: 01 lnput INIT Pulse Service Routine . heading "Input INIT Pulse Service Routine" ;H8/330 Print Buffer Routine ; version 2.0 :written by; TOIIl Hampton Hitachi America, Ltd. Application Engineering 10 2.' 240 2S0 2S1 2S2 253 2S. 2SS 256 257 258 259 260 2., program program program program program program 2.2 263 program 2.' 26S C 0000 C C C C C 0000 0000 0002 0004 0006 FlO! 3.C' 38DO 3890 C 0008 5AOOOOOO . output • print dbg,obj nocre!. nasct • global Unit_int, start . section program, code ; disable any timer interrupts Hnit_int: mov.b 'l,rOI mov.b rOI, ItmrO tcr mQv.b rOI,@tmrl-tcr mov.b rOI,ffrt_tier ;disable output strobe interrupts I disable init pulse interrupts ; disable input delay interrupts : jump to beginning jmp Istart I jump to initialbation routine .end """TOTAL ERRORS ..... "'TOTAL WARNINGS 70 Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 H8/330 Application Note Lilting 7· om:-;rN;[T US .u H8/300 ASSItMBLZR PROGRAM NAME - VBI 1.1 PAGE 03/20/91 08:12:08 INI'!' PuIs. Output Routine "INIT pulse output Routine" .he.dinq :88/330 Print Buffer Routine : veraion 2.0 :written by: Tom Hampton Hitachi America. Ltd. Application Engineering • 10 24. 24' 250 251 252 253 program 254 255 25' proqram 251 258 program 259 proqral'D. 260 261 262 program 263 264 265 program. 266 proqram dbg,obj nocre!, nOBet • global C 0000 program, code .section C 0002 39DO : output INIT signal interrupt oinit lnt: ;disable further timer interrupts m.oy.b n,rtl mov.b rll,@tmrl_tcr ;use phi/a, no interrupts e ; clear match flag bclr.b '6,@tmrl_tcsr C 0000 C 0000 F901 0004 1F017260 C 0008 F900 C DODA 39Dl 261 26. 269 program • output . print C DOOe 722C 210 271 program C 0001 5670 212 213 "'···"'TOTAL BJ\ROR.S ;clear compare match a flag : clear CINIT\ signal mov.b 'O,rll l'IIov.b rll,@tmrl_tcsr ;no more strobes ;clear oinit flag bclr.b 'buf_init_flag,r41 ;clear oinit !lag rto . end "',., "' .. "'TOTAL "AJUfIliGS HITACHI Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 71 HS/330 Application Note Li,'I;,ipq a; QMLP'I LIS ... al'300 Al8&HBUQl YBR 1.1·" PIlOGRAII RAMI - 03/20/'1 01112116 Online Pushbutton service Routine .haadlnq PACla "online Pu.hbutton Service Routin.- lHI/330 .rint Buffer Routine IV.raion 2.0 • :written by: TOIl lWIpton 1 •• Hitachi Alledoa, Ltd. Application Bn91n•• dng -lO 241 241 250 251 212 .ou.tput .print 254 255 256 proqrall 251 251 259 provr .. 200 261 26Z proqralll C 0000 ••• ction C 0000 , on line puahbutton t ••t online_lnt: e 0000 UN'040 l8et input patt buay ba.t ob tibuay_bit, Un_h. C 0004 263 praCJulI e 0004 264 pro9ua C 0001 265 2. . 267 2" 2" pr09ra C GOGA 210 pr09r. . C DODe 271 272 213 progr. . e OOOB 21. prOCJr. . e OOOB 2'75 proqr_ e 0012 271 21'1 proqr. . e 0014 218 progra. e 0014 211 210 211 program. e 00 . . 2.2 proqr. . e 00" 213 prOCJr•• C DOIA 2 .. 215 Z., prograa progr. . 21'1 2'~ 21t 290 proqraa 291 'J'BCU320 nFA * *'rO'l'AL •• III. *TO'l'AL provra., cod. Ite.t online .witch teat aw: btstob .online sw bit,lin hs2 beq teat_• .,- - , ••t IBUIY active rtest online switch ; atill 10v ..,111 not 90 further : until releAsed "; teat online statu. bt.tob 'online flag, r41 beq put_onlIne : test online status ,curr.ntly offline ,_,010 124e lcurrently online put_offline: b ••t.b 'online_bit,htat'-port bclrob 'onUne_flaq,r41 , clear Online LED ; clear online statua 5"0 ju8t_Z'et;" ,to ,_,210 ?OeC :currently offline put online: bolr.b .0nUne_bit, htat'-port baet.b 'onUne_flag,r41 :sat online LSD l8at online at.tus cOOle 1nc COOl_ .'rt ,should lBUSY be cleared '1 bt.tob .buf fl flaq .. r41 brut juat:ret ,18 buffer full :yes .. JBUSY should remaln active e 0020 '_'240 : clear input port busy bolr.b Ubuay_bU,Un_hs ;set IBUSY inactive uee 4701 292 pr09raa e 0024 5010 293 294 72 nocref, nOBet • global 253 prograa • • III dbV,Obj bits. Since the on-chip oscillator is stopped during this mode of opera~on, enough time must be allowed to allow the oscillator to re-start (AC parameter loscJ. The user can control this time by programmingtbese three bits. By setting them to different values, the usercontrolshow many clock cycles the CPU delays between .recognizing the external interrupt signal and starting the Since the on-chip peripherals are not operating dur3.,the software standby mode, itis only external interrupts (NMI or IRQz-IRQ.) that can awaken the H8/330 and return it to its nonnaloperating sequence. This is bandledjustlike any other exception sequence. The interrupting device is serviced after the oscillator settling time delay by the exception processing routine and operationisretumed to the locationfoUowing the SLEEP instruction. exception processing service routine (see Table 3). This mode is probably the most useful of the power-down modes ofoperationbecause it offers themostpowerconsumption savings. The CPU and on-chip peripherals are stopped whileextemaldevices (andon-chip UOports) arestiUallowed to function. This allows the user tobave the rest ofhis system monitor external events while the CPU remains inactive. Unlike the hardware standby mode, this mode of operation maintaiDs the registers of the CPU. This allows program execution to continue at the location following the SLEEP instruction when the H8/330 is released from the software standby mode. Also during this mode of operation, the UO ports are maintained in their current sWes instead of being re-initialized. But, the on-chip peripherals (such as timers, serial channel, etc.) are reset and must be re-initialized whenever the H81330 is released from software standby mode. Sealing lime Of course, you can always leave the software standby Diode of operation by resetting the H8/330 or by entering the hardware standby mode. System Clock Frequency (MHz) STS2 STS STSO 10 8 6 4 2 1 0 0 0 8192 0.8 1.0 1.3 2.0 4.1 8.2 0.5 leA 0 0 1 16384 1.6 2.0 2.7 4.1 8.2 leA 32.8 0 1 0 32768 3.3 4.1 5.5 8.2 leA 32.8 65.5 0 1 1 65536 6.6 8.2 10.9 leA 32.8 65.5 131.1 1 - - 131072 13.1 16.4 21.8 32.8 65.5 131.1 262.1 Table 3: Standby Timer Select Values HITACHI Hitachi America. Ltd.' San Francisco Center· 2000 Sierra Point Pkw¥.• Brisbane. CA 94005-1819 • (415) 589-8300 SectIon 5 79 HS/330 Application Note SLEEP MODE The "Sleep" mode ofpower-down operation is controlled by software. During this mode, operation of the H8/300 CPU core is halted while the rest of the on-chip functions remain active. Because of this, the "Sleep" mode offers the least amount of power consumption savings. Though the CPU is halted, the system clock is still allowed to run. This means that the on-chip peripherals can still function; the timers, the serial channel, the No converter, and the Dual-Port RAM can still do all theirnormal operations. In fact the H8/330 device gets out of the sleep mode of operation. This mode of operation is controlled by executing the SLEEP instruction during the nonnal program operation. When this occurs, the H8/300 CPU is placed into a "halt" state with no further activity taking place. This haIt state is similar to the situation where the CPU may be in an indefinite "wait" state except that no control signals are active. Whenever any of the on-chip peripherals generate an interrupt or an external interrupt is input to the device, the CPU is awakened from its sleep mode and processing continues as normal (see Figure I for flow details). The interrupting device is serviced during the exception processing routine and operation is returned to the location following the SLEEP instruction. Since the CPU is halted, no change in the I/O ports will occur (meaning that their current values will be held). Though the CPU is no longer running, all values in the registers are held in their current state. By doing this, the CPU is allowed to continue its operations directly from the location following the SLEEP instruction (after processing a return from the sleep mode). Like the Software Standby Mode, you can always leave the sleep mode of operation by resetting theH8/330 orbyentering the hardware standby mode. SPECIAL CONSIDERATIONS RAMRETENnON The H8/330 also offers the ability for the user to maintain the contents of the on-chip RAM and CPU registers with a low voltage input to the device. During either of the standby modes (hardware or software) of operation, the user can drop his supply voltage to +2.0 volts DC and still be assured that the contents of the on-chip RAM will not be lost. To use this feature correctly, the user must ensure that he disables the on-chip RAM (by clearing the RAME bit in the SYSCR) just before entering the standby mode. While in the standby modes of operation, the user can now reduce his supply voltage (thus further reducing current consumption in his system). During the software standby mode of operation, the user cannot only maintain the RAM contents but also the contents of the CPU's registers while the low voltage is applied. Before releasing the H8/330 from either standby mode of operation, it is the responsibility of the user to ensure that the proper operating voltage (Va:=+S,OV ±1O%) be available. 80 EXTERNAL OsCllLATOR In most systems (or microcontrollers), it is the oscillator that is the main concern when attempting to reduce power consumption. Though peripheral and CPU functions are stopped, since the oscillator continues to operate small power savings are observed. The H8/330 overcomes this concern by providing its own on-chip oscillator that is stopped during the standby mode of operation. If your system uses an external oscillator to dri ve the H8/330 device and you still wish to enjoy the power consumption savings that the H8/330 offers, you still can. In instances such as this, the H8/330 would accept the external clock input and stop the internal clock from being provide to the on-chip peripherals during thepower-downmodes. Here the oscillator stabilization time (AC parameter tos e ) becomes effectively 0 ms. You can now program the StandbyTimerSelectbits inthe SYSCR to "000" to reduce the delay when coming out of the software standby mode to its absolute minimum. Section HITACHI 5 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-t819 • (415) 589-8300 88/330 Application Note APPLICATION EXAMPLE SOFIWARESTANDBYMODE In this example, we will use the NMi'i.nput to suggest when the H8/330 should be in a power-down state. Since the NMI input is high, we would like the H8/330 to continue normal operations. When the NMI input goes low, we want to enter the software standby mode. This is possible because we can sensebothedgesoftheNMIinputontheHS/330.Forthesake of programming the Standby Timer Select bits,lets assume thattheH8/330is operating at a clock frequency of6MHz.In discussion of the software, we will talk only about programming that is required andnotdiscuss peripheral initialization at all (refer to Figure 4 for a flow chart of the operations sequence). During the normal operating sequence, the H8/330 would go through the process of initializing all its peripherals and other functions for normal operation. Since the System Control Register defaults tohavmg the NMledge selection for falling edge, no programming of that bitis necessary at this time. We will take this opportunity to program the SYSCR for the proper STS values. We know that the loso value is 10 msec from the AC characteristics of the H8/330. This ca1culatesout to 60,000 t-states at6MHz. To allow for this number ofclock cycles, we must program STS.-STS. to a valueof"Oll."This will allows 10.9 msec to elapse for oscillator stabilization. Whenever the falling edge of the NMI signal is recognized, the H8/330 will begin the processing of the NMI exception processing service routine. During this service routine we must do three basic operations; figure out whether we are going into oroutofsoftware standby mode, change the state of the NMI edge selection, and execute the SLEBP instruction (if we are going into the standby mode). Optionally we could also enable or disable the on-chip RAM if we were going to reduce voltage to the H8/330. After that we would return from ,this exception processing service routine toournorma1 operation (a flow chart of the NMI service routine is shown in Figure 5). rM Servlc» Rc:utlrw L 8a~ 8T_ Ml1i toM Service RCIUII,.. 01>11 .... Norlllll q,oratlcn For our discussion of the software, please refer to Listing 1. In the main routine, the only thingwereal1y ~ need to do is to program the SYSCR with the values t; necessary for the NMI edge seleCtion and the standby ~ timer selection (for oscillator stabilization time). Initially we want to capture the falling edge of the NMl input and set the STS bits for a count of 65536. This requires the programming of "lOlllOXl" into the SYSCR (refer to Figure 3 for a description). With this programmed into the SYSCR,we can continue withour normal processing. Whenever the falling edge of the NMI signal is observed (see Figure 6), the H8/330 will begin processing the NMI exception processing service routine. Since this routine must handle both placing the H8/330 into the software standby mode as well as recovering from it, we must first decide which one ilis. To do this we cantestthe state of the NMIEG bit. If this bit is a "0," then we can assume that we have detected the falling edge and that we are going to go Figure 4: Application Example Processing Flowchart HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 81 I I H8/330 Application Note into the software standby mode. Before we execute the SLEEP instructionwe would need toprogram theNMIBG bit to "1" so that we.C8Il now monitor for the rising edge of the NMisignal. Optionally, ifweare going to reduce the Va: level we would need to clear the RAMS bit in the SYSCR now before we execute the SLEEP instruction. After executing the SLEEP insttuction the H8/330 is now in the software standbymodeofoperation awaiting the inputof the rising edge on the Nm signal. When the rising edge is detected (see Figure 7), theH8/330starts theintemalcowlter for the standby timer and delays further processing until the coWlter has timed out At this point the H8!330 begins processing the NMI exception processing service routine agaUL . We still need to test the NMIBG bit to decide whether we are .going into the standby mode or coming out of it If this bit is a "1," then we can assume that we are comingJmlpf the standby mode. Here, we would want to change the NMI edge selection from rising edge to falling edge. If we had disabled the on-chip RAM, we would want to make sure that we re-enabled it for use. Afterward we merely retum from the NMI serviceroutine (which incidentally retums us to theNMI service routine that we were performing to go into standby NMI lL-___________ --.l/ NMIEG NMI I+-Servlce+l+Routln mode). Software Standby Mode Figure 6: AppUcationExample NMI Falling Edge Timing Oscillator . A1fill1111111l11l111111l1111 Clock NMI Dhcble O>OIlpR.tM ,< L NMIEG Software Standby Mode Figure 5: Application SoftwareHowchart (NMI Service Routine) 82 Clock NMI -1"~IIOIII"'I---Settllngl--~"MI"'I-Servlce~ Time Routln Figuie 7: Application Example NMI Rising Edge Timing Section HITACHI 5 Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 HS/330 Application Note Lilt;ing1' _Ugation 1l""IP1a IM% _"1oe 'APt!." 181/330 Pover-Down Application &xUlpla I NHI •• rvictl Routine btat.b boq t2,lh' ftc' tall1n,_8d,8 ,t..t nmi89 bit in SYICR 19oin, into power-down I COJI1n" ou.t of poHr-dOVll rb1D9_..... bolE.b tI.lh'fret , ••t "'et.b .O,lb' ffot ,ena»18 on-chip RAN ,nturn from. proc...1ftq , to prevlou.. NHI rou.tine tz,lh' ffc" .O.lb' ffet , ..t nmieg for rbine) ad9. n. NIle; for '&111n9 selV8 , voinv into power-clown fall1lUJ_"98I b ••t.b bcl<.b 11_ rh on-chip RAM '90 to power-down mode I dhabla I return from proc...1DV ; to nomal operation HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 83 Section 84 5 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 March,1992 HS/3XX Instruction Timing Tech Notes Application Engineering Carol Jacobson While benchmarks can provide a good estimate of a controllers CPU performance, they seldom give us enough information to determine a part's suitability for a particular application or the relative performance of a peripheral. A good approximation of a controllers ability to execute a particular function, within an allotted time, can be obtained by adding module overhead (inteITUpt latency, AI D conversion, serial bit rates) to the time required to execute the modules driver routine. Using information shown in the H8!300 Series Programming Manual, instruction execution times for any combination of addressing modes and memory access types can be calculated. Instruction Fetch H8!3xx devices have three possible data paths: a 16-bit internal data bus for RO to R7 and on-chip memory, an 8-bit internal bus for on-chip peripherals and an 8-bit external bus. The H8!300 CPU uses a 16-bit word instruction set. The number of cycles needed to fetch an instruction equals the number words in the instruction times the number of cycles needed to fetch each word. This later value depends upon the data path used. These numbers are given in Tables Cl and C2 of Appendix C in the Programming Manual. For Example: From on-chip ROM: hex code mov.b rOl,@h'2000 6A88 2000 # words x #Clocks I 16-bits = 2 2 instruction fetch time 4clks From external memory: wait states (m) cam be included for access to slower peripherals requiring additional time to complete the transfer: hex code mov.b rOl,@h'2000 6A882000 # bytes x #Clocks 18-bits = 4 3+m instruction fetch time 12+4mclks Execution Like the instruction fetch, the number ofcycles needed to execute each part of the instruction depends upon the operation and memory location. Additional cycles, represented in table C2 as columns J through N, can be defined as follows: HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 85 HS/3XX Instruction Timing Tech Notes Branch Address Read: Cycles needed to fetch the destination address during an 8-bit indirect jump or jump to subroutine (JMP,JSR @@aa:8). Stack Operation: Additional cycles for incrementing or decrementing the stack pointer and storing the program counter on the stack. Byte Data Access: Time required to obtain non-immediate (or indirect) 8-bit data or address locations. Word data Access: Time required to obtain non-immediate (or indirect) 16-bit data or address locations. Internal Qperation: Additional cycles for arithmetic address or data calculations. The total instruction cycle time is the sum of the instruction fetch time plus any additional cycle time needed to complete execution of the instruction. Appendix B of the H8/300 Programming Manual gives the number of clock cycles for each instruction, for all supported addressing modes, when all operations are on-chip. For instructions fetched from off-chip memory, timing can be calculated from table Cl and C2 values. Note:Table CI, On-chip Reg. Field, refers to on-chip I/O and module registers not to registers RO - R7 or the CCR. Table Calculatiops From tables Cl & C2: int: ext: mov.b rOl,@h'2000 mov.b rOl,@h'2000 (# of cycles) hex code 6A882ooo 6A882ooo I 2 4 (clks/cyc) instruction fetch time Si 4clks 2 12 +4mclks 3+m Eumples 1. a. MOV.B @Rl+,RlH where the instruction resides in off-chip memory requiring no wait states and Rl contains an off-chip address value. frpmCI fromC2 1= 1 Si= 6 + 2 x 0 = 6 ;instruction fetch L= 1 Sl= 3 +2 xO=3 ;indirect address access cycle N= 1 Sn=2 ;time to increment Rll Total = (1 x 6) + (1 x 3) + (1 x 2) = 11 clocks = 1.1 us @ lOMHz Section 86 5 HITACHI Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 HS/3XX Instruction Timing Tech Notes b. If the same instruction bad been stored on-chip and the address in Rl was on-chip' RAM, from App. B we read: 6 states or clocks = 0.6 us @ 10MHz or: I=L=N= 1 Si=SI=Sn=2 Total = (1 x 2) + (1 x 2) + (1 x 2) = 6clocks 2. a. BCLR @R3L,@H'8031 where the instruction resides in external ROM requiring 1 wait state and the destination is off-chip RAM requiring one wait state. fromC2 fromC1 1=2 Si=6+2x 1 = 8 ;off chip access L=2 SI=3+2xl=S ;byte access to off chip memory Total = (2 x 8) + (2 x S) = 26 clocks = 2.6 us @ 10 MHz b. BCLR #03,@FRT_TCR where the instruction resides in external ROM requiring 1 wait state and the destination is the on-chip register field. frpmC2 fromC1 1=2 Si=6+2x 1 =8 ;fetch from off chip memory L=2 SI=3 ;byte access to on chip register field Total = (2 x 8) + (2 x 3) = 22 clocks = 2.2us @ 10 MH HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 87 November, 1991 HS/320 Family Device EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Seeurity The H8/320 Family ofmicrocontrollers (except the H8/324 which is a masked programmed device only) have an EPROM security feature that can be used by the customer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the H8/320 from being read by means other than his own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory Configuration The memory matrix of the H8/320 Family of microcontrollers is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64 byte segment to have the option of the sCfurity feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the H8/320 Family device is placed into, EPROM programming mode or CPU operation mode. EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "I" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. 88 Section HITACHI 5 Hitachi America, ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 88/320 Family Device EPROM Security security bit security bit Tech Notes EPROM data can be read (nonnal) "00" data is always read 1 0 CPU Operating Modes In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bit is a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. security bit security bit 1 0 EPROM data can be read by CPU (nonnal) After RESET, the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or internal RAM). Once an instruction is executed outside the internal EPROM memory area, then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM. Programming the Security Bit There exists two EPROM programming mode; Nonnal and Security. The nonnalEPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/320 device. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: Programming Mode Nonnal Security H8/320 Device I/O Port Pin P7/0S P7JiS 1 1 1 0 Again, thisfeature cannot be tested by Hitachi and thus remains unguaranteed. It is up to the user to determine whether or not to implement the junction of this feature and accept sole responsibility for its outcome. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 89 November, 1991 H8/350 Device EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/350 Microcontroller has an EPROM security feature that can be used by the customer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the H8/350 from being read by means other than his own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to detennine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory Configuration The memory matrix of the H8/350 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64 byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the H8/350 device is placed into, EPROM programming mode or CPU operation mode. EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. Section 90 5 HITACHI Hitachi America, LId.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 H8/350 Device EPROM Security security bit security bit 1 0 Tech Notes EPROM data can be read (nonnal) "00" data is always read CPU Operating Modes In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "I" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bit is a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. security bit security bit 1 0 EPROM data can be read by CPU (nonnal) After RESET, the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or internal RAM). Once an instruction is executed outside the internal EPROM memory area, then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM. Programming the Security Bit There exists two EPROM programming mode; Nonnal and Security. The nonnal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/350 device. The "security" programming mode is used to program the security bits of the . EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: Programming Mode Nonnal Security H8/350 Device I/O Port Pin P8/RS/iOS P8JRSJE 1 1 1 0 Again, thisfeature cannot be tested by Hitachi and thus remains unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Bri~bane, CA 94005-1819 • (415) 589-8300 Section 5 91 June, 1991 HS/330 Microcontroller EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/330 Microcontroller has an EPROM security feature that can be used by the application programmer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the H8/330 from being read by means other than his or her own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory Configuration The memory matrix of the H8/330 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64 byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the H8/330 device is placed into, EPROM programming mode or CPU operation mode. EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. security bit security bit 92 1 0 EPROM data can be read (normal) "00" data is always read Section HITACHI 5 Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 H8/330 Microcontroller EPROM Security Tech Notes CPU Operating Modes In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bitis a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. security bit security bit 1 0 EPROM data can be read by CPU (normal) After RESET, the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or intemal RAM). Once an instruction is executed outside the intemal EPROM memory area, then the EPROM becomes disabled and cannot be accessed any further. This prohibits an extemal program from being able to "dump" the contents of the on-chip EPROM. Programming the Security Bit There exists two EPROM programming mode; Normal and Security. The normal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/330. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: H8I330 1/0 Port Pin P80 P81 Normal 1 1 Security 1 0 Programming Mode Again, thisleature cannot be tested by Hitachi and thus remains unguaranteed. It is up to the user to determine whether or not to implement the /unction 01 this feature and accept sole responsibility lor its outcome. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 93 May, 1991 H8/300 CPU DIVXU Instruction Tech Notes Application Engineering Tom Hampton The H8/300 CPU provides an instruction to perform a 16/8 divide operation to yield an 8-bit result. The H8/300 Programming Manual incorrectly describes the flag results during the execution of this instruction. The text of the instruction states the following: "Valid results are not assured if division by zero is attempted or an overflow occurs. Division by zero is indicated in the Zero flag. Overflow can be avoided by the coding shown on the next page." This is in error. While it is true that valid results cannot be assured if the division by zero is attempted or an overflow should occur, it is incorrect in stating that the Zero flag will indicate that a divide by zero operation was attempted. The text should read: "Valid results (remainder, quotient, and flag operation) are not assured if division by zero is attempted or an overflow occurs. Overflow can be avoided by the coding shown on the next page. " The text for the flag description currently states: Z: Set to "I" if the divisor is zero; otherwise cleared to "0." This text should read: Z: 94 Unpredictable if the divisor is zero; otherwise cleared to "0." Section HITACHI 5 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 May, 1991 HS/300 CPU SUBX Instruction Tech Notes Application Engineering Tom Hampton The H8/300 CPU provides an instruction for subtracting two bytes from each other along with the value of the Carry flag. This instruction is useful when performing subtraction operations that are greater than 16-bits (an instruction is already available that can do either 8-bit or 16-bit subtractions with no problems). Lets take the example of a 32-bit subtraction as follows: H' 40000000 - HI 3rBf2 J5§ H'0070DCAA (result) If we look are each operation individually, the result is easily explained. 1. In subtracting the low order bytes from each other (56 from 00), we get a result of AA with a borrow from the next higher byte. 2. In subtracting the next higher order bytes from each other (23 from FF because of the bolTOw), we get a result of DC with the borrow continuing to the next higher byte. 3. In subtracting the next higher order bytes from each other (8F from FF because of the borrow), we get a result of 70 with the borrow continuing to the next higher byte. 4. In subtracting the highest order bytes from each other (3F from 3F because of the bolTOw), we get a result of 00 with no borrow. If no borrow operations were never to occur, then we could code this very simply with two word subtract operations. But since this is not the case, we must code the sequence so as to keep track of the borrow operations. If we code this in the same sequence as the operation described above, it might look something like this: mov.w mov.w mov.w mov.w sub.b sub>< sub>< sub>< 'h'4000, rl IO,r2 Ih' 3£8£, r3. 'h'2356, r4 r2l, r4l r2h, r4h rll, r31 rlh,r31 ;00-56 ; 00-23-borrow ; 00-8f-borrow ; 40-3£-borrow (We could also replace the ftrst two subtraction instructions with a subtract word operation to reduce code size and execution time but this method makes it easter to read for now.) sub.w sub>< sub>< r2,r4 rll,r31 rIh, r31 ;0000-2356 100-Sf-borrow ; 40-3f-borrow HITACHI Hitachi America, Ltd .• San FranCisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589-8300 Section 5 95 HS/300 CPU SUBX Instruction Tech Notes The trick in using the SUBX instruction is to pay attention to the flag operations. During execution of a nonnal subtraction operation, the Zero flag is used to detennine if the result of the operation is zero or not. However, the execution of the SUBX instruction is a little bit different. If the result of the operation(is zero, then the Zero flag remains unchanged from the previous instruction. If the result is non-zero, then the Zero flag is cleared to correctly indicate a non-zero result. While this sounds a lot like what it is supposed to be, look at a scenario where the previous instruction would clear the zero flag (this may be something as simple as a MOV instruction). If the SUBX instruction were to follow this operation and the result were zero, then the Zero flag would remain at "0," clearly not indicating the result of the operation. Because of this, it is extremely important that the SUBX instruction be used IMMEDIATELY following other SUB or SUBX instructions. This sequence allows the H8/300 CPU to properly keep track of borrows, and maintain the Zero flag in the correct state. To illustrate this problem, lets assume that our variables are stored in memory rather than registers. In this example, we have to move the data into our registers in order to perfonn the operation. varl var2 1- 2. 3. 4. .equ .equ mov.b mov.b sub.b mov.b mov.b mov.b subx mov.b mov.b mov.b sub>< mov.b mov.b mov.b sub>< mov.b H' 40000000 H' 3f8f2356 @(var2+3) @(varl+3) ,rlh ,rll rlh, rll rH,@ (var1+3) @(var2+2), rlh @(varl+2), rll rlh, rll rll,@ (varl+2) @(var2+l), rlh @(varl+ l) , rll rlh, rll rll,@ (varl+l) @(var2) ,rlh @(varl) ,rll rlh, rll rll,@(varl) ;get 56 ;get 00 ; 00-56, Zero=O, Carry~l ;store 1st result (M), Zero=O, Carry~l ;get 23, Zero-O, Carry=l ;get 00, Zero=1, Carry~l ;OO-23-borrow, Zero=1, Carry~l ; store 2nd resul t (DC), Zero=O, Carry=l ;get 8F, Zero=O, Carr~l ;get 00, Zero=l, Carry~l ; 00-8F-borrow, Zero=1, Carry=l ; store 2nd resul t (70) , Zero=O, Carry=l ;get 3F, Zero=O, Carry~l ;get 40, Zero=O, Carry~l ; 40-3F-borrow, Zero==O, Carry~O ; store 2nd result (00) , Zero=1, Carry~O Since the result of the SUB and SUBX operations are not 00 (until number 4), the flags behave as we wish them to. During the 4th subtraction operation, the Zero flag remains clear even though the result of the subtraction operation was zero. While this is the correct flag value for the entire operation, it would not be correct if we test the flag after the MOV instruction. Lets change our variables so that the result of the subtraction operation should be zero (H'40000000 -H'40000000) and again follow the code sequence. Since each of the substraction operations (SUBX) would result in a zero value, the contents of the Zero flag would remain as it was prior to the execution of the instruction. In the 4th subtraction operation, we need only look at the values transfered by the MOV instructions. Since both values are non-zero in nature, then the contents of the Zero flag would be cleared as a result of that instruction. This allows the final value of the Zero flag (before the MOV instruction) to be 0, and this would be incorrect for the entire operation. Of course it would be correct after the MOV operation, but our previous example showed it to be opposite of this example. 96 Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 88/300 CPU SUBX Instruction 4. mov.b mov.b mov.b subx mov.b rH,@ (varl+l) ,rlh @(varl) , rH rlh, rll rH, @(varl) @(var2) Tech Notes ; store 2nd result (70) , Zero-O, Carry-l ;get 40, Zero=O, Carry=l ;get 40, Zero.. O, Carry-l ; 40-3F-borrow, Zero=O, Carry-O ; store 2nd result (00) , Zero... l, Carry-O In the final analysis, to make things much simpler for the user, it is recommended that the SUBX instructions always follow other subtraction instructions IMMEDIATELY. The resulting Zero flag status would also the user to detennine the status of his complete result. HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 97 Section 98 5 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819'· (415) 589-8300 Section 5 H8 Family H8/5XX Series HITACHIf) Section 100 5 HITACHI Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 I HS/SOOCPU Application Note Technical Q & A How to Use Microcomputer Technical Questions and Answers Technical Questions and Answers has been created by arranging technical questions actually asked by users of Hitachi microcomputers in a question-and-answer format. It should be read for technical reference in conjunction with the User's Manual. Technical Questions and Answers can be read before beginning a microcomputer application design project to gain a more thorough understanding of the microcomputer, or during the design process to check up on difficult points. HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 101 Section 102 5 HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-~300 Contents Q&ANo. Page Registers (1) Register contents after power-up reset QA8500 - OOlB (2) Page registers in single-chip mode and expanded minimum modes QA8500 - OO2B (3) DP contents in unconditional jump within page QA8500 - 036A 105 106 107 Interrupts (1) (2) (3) (4) (5) (6) (7) (8) (9) Interrupt sampling and acceptance Holding of disabled external interrupts Disabling of invalid instruction exceptions Interrupt contention while waiting for instruction execution to end Time of clearing of IRQn interrupt request signal Requirements for enabling interrupts Maximum wait after BREQ Clearing of interrupt request enable bits and pending interrupts Acceptance ofNMI during NMI handling QA8500 - 004B QA8500 - OO6B QA8500 - 008A QA8500 - 028A QA8500 - 030A QA8500 - 031A QA8500 - 032A QA8500 - 034A QA8500 - 035A 108 109 110 11\ 113 115 1\6 117 118 QA8500 - 009B QA8500 - OIOB QA8500 - 037A 119 121 122 QA8500 - 011B QA8500 - 013B QA8500 - 014B QA8500 - 016B QA8500 - 019B QA8500 - 020B QA8500 - 021B QA8500 - 027A 123 124 125 126 127 128 129 130 QA8500 - 023B 131 QA8500 - 033A 132 QA8500 - 029A 133 Reset (1) NMI sampling and acceptance immediately after a reset (2) Stack pointer initialization immediately after a reset (3) Pin states at power-up reset Power-down state (1) (2) (3) (4) (5) (6) (7) (8) Hardware standby mode entry timing Instruction execution at changeover to hardware standby mode Mode pins in hardware standby mode Recovery from hardware standby mode Notes on entering sleep mode Interrupts during fetching and execution of SLEEP instruction Sampling and acceptance of interrupts during sleep mode Execution time for entering software standby mode 1m Instructions (I) BRN instruction Software (1) Reserved addresses in interrupt vector area Miscellaneous (1) Access to on-chip registers while bus is released HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 103 SectIon 104 II HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (411\ 589-8300 Technical Question and Answer IQ&A No·1 Product H8/500 CPU Topic Register contents after power-up reset QA8500 - 001 B Classlflcation-H8/S00 Question 1. What are the CPU register contents after a power-up reset? 0 Registers Read tim ina Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Miscellaneous Related Manuals Manual Title:] Answer 1. In minimum mode. the program counter is loaded from the vector table. The interrupt mask bits (12. 1\. 10) in the status register (SR) are set to 1. and the trace bit (n is cleared to O. Registers RO to R7, the base register (BR). and the other Other Technical SR bits have undetermined values. Documentation In maximum mode the code page register (CP) is loaded from the vector table. Other page registers have undetermined values. Registers other than the page registers are the same as in minimum mode. Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5105 Technical Question and Answer IQ&A No·1 Product HS/SOO CPU Topic Page registers in single-chip mode and expanded minimum modes QA8S00 - 0028 Question 1. Can the DP, EP, and TP page registers be used as data registers in the single-chip mode and expanded minimum modes? 0 Classlflcatlon-H8/SOO Reaisters Readtiming Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer l. I Yes, but since the page registers are control registers, they can only be accessed by system control instructions (LDC, STC). Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I Section 106 5 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/S00 CPU Topic DP contents in unconditional jump within page QA8S00 - 036A Classlflcatlon-H8/S00 Question 1. If the JMP @RO unconditional in-page jump instruction is executed in expanded maximum mode, are the data page (DP) register contents used in calculating the effective address? 0 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Miscellaneous Answer 1. The DP contents are not used in calculating the effective address of an unconditional jump within the same page. If the JMP @RO instruction is executed to jump within the same page, the RO contents are loaded into the program counter (PC), but the code page (CP) register value does not change. The DP contents are therefore ignored. Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5107 Technical Question and Answer JQ&A No·1 Product H81500CPU Topic Interrupt sampling and acceptance QA8500· 0048 Classlflcatlon-H8/S00 Registers Read timing auestlon l. When are external interrupts (NMI, IRQn) sampled? Wr~etiming 0 Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer l. Level-sensitive interrupts (IRQo) are sampled on the rising edge of the system clock. Edge-sensitive interrupts (external interrupts other than IRQo) are sampled 01\ the falling edge of the system clock. Miscellaneous Related Manuals Manual Tltla: I Other TechnIcal Documentation Document Name: I Related MIcrocomputer TechnIcal Q&A ~ AdditIonal InformatIon SeclJon 108 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer . IQ&A No·1 QA8500· 0068 Product H81500 CPu Topic Holding of disabled external interrupts Question 1. In the following two cases, are external interrupts (IRQn) held pending'? (1) IROn enable bit is cleared to 0 in on-chip register field (2) IRQn interrupt priority level S; interrupt mask level set in status register (SR) Classlflcatlon-H8lSOO Registers Readtimina Writetimina Interrupts . 0 Reset External expansion Power-down state Instructions Software Development tools Answer 1. I (1) In this state. the interrupt request signal is not sampled and the interrupt is not held pending. Interrupt requests made in this state will be ignored even. if the IROn enable bit is later set to 1. (2) An interrupt that is requested in this state is held pending in the CPU's intel"11lPt controller. If the interrupt request mask level is later reduced to a value lower than the external (IRQn) interrupt priority level. the interrupt will be accepted. IROo is level-sensitive. however. so it is not held pending. Miscellaneous Related Manuals Manual TItle: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ..!!!!!:J AddltlonallnformatlonJ The interrupt request mask level is set in bits 12 to 10 in the status register (SR). HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-83QO Section 15.109 Technical Question and Answer IQ&A No·1 Product H8/500 CPU Topic Disabling of invalid instruction exceptions QA8500· 008A Question 1. Can exception handling of invalid instructions be disabled? How does the exception handling routine terminate? Classlfication-H8I500 Registers Read timing Write timing 0 Interrupts Reset External expansion Power-down state Instructions Software Development tools Miscellaneous Related Manuals Manual Titie: I Answer 1. No, it cannot be disabled. The invalid instruction exception handler cannot be terminated by returning with an RTE instruction. Use some Other Technical other software technique, such as jumping to the reset Documentation routine. Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I Section 110 5 HITACHI Hitachi America, Ltd. 0 San Francisco Center 0 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0(415) 589-8300 Technical Question and Answer IQ&A No·1 QA8500· 028A - Product H81500 CPU Topic Interrupt contention while waiting for instruction execution to end 1 Classlflcatlon-H8/S00 Question 1. Suppose an interrupt occurs during execution of an instruction, then during the waiting state before the instruction ends another, higher-priority interrupt occurs. Which interrupt does the CPU accept? 0 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Miscellaneous Answer 1. The CPU accepts the interrupt with the highest priority level four states before the time of acceptance. (See the next page.) The interrupt mask level in bits 12 to 10 is not changed until the status register (SR) has been saved onto the stack. Related Manuals Manual ntle: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section • 111 ~ I\) en 011 ::r: ~ §" CD 9 ~ Internal address bus ~. ~ iil :::J x::= N o 8J: ~;t ~~ :a I: ~- ~ '"'" ::!. f" ~ ~ ~ ~ Internal data bus (16 bits) ~ ; ::J: 8::J Gi ao· Interrupt source 1 (priority level 8 6) Interrupt source 2 (priority level = 7) I~~J . ~~r..----------------~----------- ICL a s: 0 0 () " C :> ~ If;····-.... (;' - S» ... :i" 4cJ I bits (A) Interrupt source 1 is level before interrupt inSR input but not accepted because of instruction execution. Stack (8) Interrupt sources 1 Waiting for interrupt Internal and 2 contend. priority decision and cycle Interrupt source 2 end of instruction is selected. 1)' (C) The instruction being Interrupt accepted executed ends. The CPU accepts interrupt source 2. (D) The I bits in the status register are changed to level 7. : (D) )i( Priority level of accepted interrupt ~~--~~----~~~.r'-------------------~------~~---Il)Ierrupt vector Note: Conditions: minimum mode with the program and stack areas both in on-chip memory and interrupt handler starting at an even address. g :r sa 2 !l o· ::J ~ CD 0 0 110 •z 0 ~ ex> S U1 0 0 8" 0 N CD > o· :> :> Q. " C CD co (C) ';;} n ::r ::::I ~ iD' ~ __---,(8) <0 .£! [ !!! 2 -g. (; Vector address ~~---:S:-:P::--4~"';""---'X ~. I "c .. n C"> "nI~·I~ ex> I N (I) 0' ::::I S» ::::I Q. .~ ::::I (I) :e CD ~ Technical Question and Answer IQ&A No·1 QA8500 - 030A - Product H81500 CPU Topic Time of clearing of IRQn interrupt request signal Que.tlon 1. There are no interrupt request flags for edge-sensitive extemal interrupts (IRQn)' When are these requests cleared? 1 Classlflcatlon-H8ISOO Registers Read timing Write timing Interrupts 0 Reset External expansion Power-down state Instructions Software Development tools Answer 1. The interrupt request is cleared during the internal cycle in which the interrupt is accepted, as indicated by the arrow in the diagram on the next page. If the same interrupt request signal (IRQn) occurs after this time, it will be latched again. Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 113 Technical Question and Answer Product H81500 CPU Topic Timing of clearing of IRQn interrupt request signal Answer Internal address bus IRQ n (edge-sensed) Internal data bus (16 bits) Internal read signal u Internal write signal Internal cycle Interrupt accepted (1) Instruction prefetch address (2) Instruction code Taken from the User's Manual Section 1145 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/500 CPU Topic Requirements for enabling interrupts QA8500 - 031A Classlflcation-Hs/SOO Registers Question 1. Why do we fail to get an interrupt even though the interrupt request enable bit (lRQnE) is set to 1 and the interrupt request signal (lRQn) is asserted? Readtimi~ Wr~etiming 0 Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. To enable interrupts to be accepted, software must: (I) Set the interrupt enable bits for the desired interrupt sources to 1. (2) Set values in the interrupt priority registers (IPRs). (3) Set the desired interrupt request mask level in bits 12 to 10 in the status register (SR). Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Check the above points. Related Microcomputer Technical Q&A ~ Additional Information I A reset initializes all IPR values to 0 and sets bits 12 to 10 all to I, masking all interrupts except NMI. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5115 Technical Question and Answer· Product H81500 CPU Topic Maximum wait after BREQ IalA No·1 QA8500· 032A aueatlon 1. What is the maximum waiting time from input of an external bus request signal (BREQ) until the CPU replies (BACK)? Classlflcatlon-H8l5OO Registers Read timing Write timing Interrupts 0 Reset External expansion Power-down state Instructions Software Development tools Answer 1. The maximum waiting time is 10 to 17 states. This occurs if the CPU started executing the MOVFPE or MOVTPE instruction (which transfers data in synchronization with the E clock) just before BREQ was asserted. Because MOVTPE and MOVFPE execute in synchronization with the E clock, the number of states varies depending on the timing of the start of execution. Miscelianeous Related Manuals Manual ntle: I Other Technical DocumentatIon Document Name: I Related MicroComputer Technical alA ~ Addltlonallnforrnatlon I Section HITACHI S Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 116 Technical Question and Answer JQ&A No·1 QA8500· 034A Product H8J500CPU Topic Clearing of interrupt request enable bits and pending interrupts Cla8S1fJcatlon-H8I500 Registers Readtimina Write timing Interrupts 0 Reset External expansion Power-clown state auestlon 1. While an IRQ" interrupt is being held pending because its priority is equal to or less than the interrupt request mask level in the status register (SR), does clearing the IRQ" enable bit (IRQnE) also clear the lRQn interrupt request? Instructions Software Development tools Answer 1. When an IRQ" interrupt request is held pending because of the interrupt request mask level (12 to 10), the request remains pending even if IRQ"E is cleared to O. The IRQn interrupt will be accepted later when the interrupt request mask level is reduced to a value less than the IRQ" priority level Interrupt request Level 4 Level 2 ):i masklavel ! IRanE ~ (priority level 3) ~ if 1 X ~ Miscellaneous Related Manuals Manual ntle: I Other Technical Documentation Document Name: I X 0 ,, Related Microcomputer Technical Q&A ~ if Interrupl request Interrupt requested I AddJtJonalJnformetlon IRQo is level-sensitive, so it is not held pending, regardless of whether IRQoE is set or cleared. HITACHI Hitachi America, Ltd.· San FranCisco Center • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section 117 a Technical Question and Answer IQ&A No·1 Product H8/S00 CPU Topic Acceptance of NMI during NMI handling QA8S00 - 03SA Question 1. NMI has the highest priority and is always accepted. During the NMI interrupt handling routine, if another NMI interrupt occurs will it also be accepted? Classlflcatlon-H8/S00 Registers Read timing Write timing Interrupts 0 Reset External expansion Power-down state Instructions Software Development tools Answer 1. If another NMI request is made during the NMI interrupt handling routine, the second request will also be accepted. Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 118 Technical Question and Answer , Q&A NO.' QA8500 - 0098 - 1 Product H8/s00CPU Topic NMI sampling and acceptance immediately after a reset Classlflcation-H8l5OO auestlon 1. When is the NMI signal first sampled after a reset? 0 Registers Read timing Wrketiming Interrupts Reset External expansion Power..cJown state Instructions Software Development tools Miscellaneous Answer 1. Sampling of the NMI signal SLans from the first falling edge of the system clock at which the reset signal is high. The NMI interrupt becomes acceptable when the first instruction has been executed after the chip comes out of reset (See next page) Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical QU ~ I Additional Information The reset and NMI signals are both sampled on the falling edge of the system clock. HITACHI Hitachi America. Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 58~83QO SectIon IS 119 / Technical Question and Answer Product H81500 CPU Topic NMI sampling and acceptance immediately after a reset Question [Example] " : 1ress 1 High res~1 signal s mpled ! • .. • NMI nol sampled Section 120 5 . NMlsampled HITACHI Hitachi America, Ltd.' San Francisco Center. 2000 Sierra Point PkWy.' Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product H8/500 CPU Topic Stack pointer initialization immediately alter a reset 'Q&A NO.' QA8500 - 0108 Classlflcstlon-H8/S00 Question 1. Registers Read timing Why is it necessary to initialize the stack pointer immediately after a reset? Wr~etiming 0 Interrupts Reset, External expansion Power-down state Instructions Software Development tools Miscellaneous Answer 1. If the NMI request signal is active when the chip comes out of reset, the NMI interrupt will be accepted as soon as the first instruction has been executed. To prevent program crashes, you should therefore initialize the stack pointer immediately after the reset. Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd,· San Francisco Center· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819 • (415) 589·8300 Section 5 121 Technical Question and Answer ) IQlA NO., QA8500 - 037A Product H81500CPU Topic Pin states at power-up reset Question 1. What needs 10 be noted about pin staleS at a power-up resel? Classlflcatlon-H8I500 Reaisters Read tim ina Write timing Interrupts 0 Reset Extemal expansion Power-down state Instructions Software Development tools Miscellaneous Related Manuala Anawer Manual Title: I 1. At a power-up reset. the mode pins (M02 10 MOo) must be tied 10 the desired mode setting and the STBY pin must be held high. Output from the" and E pins is unpredictable until the clock oscillator seules inoo steady oscillation. Other Technical Documentation Document Nama: I \ Related Microcomputer Technical QlA ~ I Additional information When using a microcontroller that multiplexes the 1'1 and E pins with general-purpose input ports. connect aresjslOr with a resiSLance of several kilohms in series with these pins. SectIon 122 • Hitachi America, Ltd. ° San Francisco Center HITACHI ° 2000 Sierra Point Pkwy. ° Brisbane, CA 94005,1819 o. (415t 589-8300 Technical Question and Answer IQ&A No-1 Product H8/500 CPU Topic Hardware standby mode entry timing QA8500· 011B Question 1. Are there any restrictions on times tl and t2 in the diagram below for entering hardware standby mode? STBY t1 ---- t2 tascl Instructions Software Development tools '///////, RES Miscellaneous Related Manuals Manual Title: I Answer 1. The following restrictions apply. (1) To hold RAM contents, t1 must be at least 10 system clock cycles. The minimum value of t2 is 0 ns. (2) When it is not necessary to hold RAM contents, there is no restriction on t1 and t2. STBY t1 RES t2 Classlflcatlon-H8/S00 Registers Read timirlll Write timing Interrupts Reset External expansion 0 Power·down state losc r--- Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ 111// / Additional Information HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5123 Technical Question and Answer Product H81500 CPU IQ&A No.1 QA8500· 0138 Instruction execution at changeover to hardware standby mode C....lflcatlon-H8l5OO Queatlon Registers 1. When a low STBY input drives the chip into hardware Read timing standby mode, what happens to the instruction currently Write timing being executed? Interrupts Reset External exD8llsion 0 Power-down state Topic Instructions Software Development tools ( Anawer 1. The instruction being executed is aborted, without being completed. Nonnal execution of the instruction is not assured. Miscellaneous Ralated Manuala Manual m..: J Othar Technical Documentation Document Nama: I Ralated Microcomputer Technical Q&A ~ Additional Information SectIon 124 II I HITACHI Hitachi America, Ltd •• San Francisco Canter· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No-l QA8500 - 014B Product H81500CPU Topic Mode pins in hardware standby mode auestlon 1. What happens if the states of the mode Jines (MDz to MOo) are changed during hardware standby mode? Claselflcatlon-H8I500 Reaisters Read timing Write timing Interrupts Reset External expansion 0 Power-down state Instructions Software Development tools Answer 1. Hardware standby mode will not operate correctly. Do not change the state of the mode Jines during hardware standby mode. Miscellaneous Related Manuals Manual Tltle:J Other Technical Documentation Document Name: I Releted Microcomputer Technical Q&A ~ Addltlonallnformetlon I HITACHI Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005'1819 • (415) 589-8300 Section 5125 Technical Question and Answer IQ&A No·1 QA8S00· 0168 Product H8/S00CPU Topic Recovery from hardware standby mode Question 1. The chip must be recovered from hardware standby mode by holding RES low, then driving STBY high. How long before STBY goes high does RES have to go low? Classlflcatlon-H8/S00 Registers Read timing Write timing Interrupts Reset External expansion Power-down state 0 Instructions Software Development tools Answer 1. I To recover from hardware standby mode, drive RES low at least 100 ns before driving STBY high. Other Technical Documentation Document Name: STBY RES Miscellaneous Related Manuals Manual Title: I ,--- \\\\\\\\\\\\ Related Microcomputer Technical Q&A 100 ns Additional Information I lose ~ I Section HITACHI 5 Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 126 Technical Question and Answer IQ&A No·1 QA8500· 0198 Product H81500 CPU Topic Notes on entering sleep mode Question 1. Are there any points to note about entering sleep mode? Classlflcatlon-H8ISOO Registers Read timing Wrketiming Interru()ts Reset External expansion 0 Power-down state Instructions Software Development tools Answer 1. The points listed below should be noted, depending on the method used to recover from sleep mode. Miscellaneous Ralatad Manuals Manual ntla: I Racovary Method NMllnterrupt IRQn Interrupt Clear all interrupt enable bks to 0, or set bks 12 to 10 in SR all to 1. Set bits 12 to 10 in SR to a level lower than the priority level of the interrupt used for recovery, clear interrupt enable bks to 0 except for interrupts used for recovery, and make sure NMI is not requested. AddHlonallnformatlon Other Technical Documentstlon Document Nama: I Ralatad Microcomputer Technical Q&A ~ I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5127 Technical Question and Answer Ia&A No·1 QA8500 - 0208 Product H81500 CPU Topic Interrupts during fetching and execution of SLEEP instruction auestlon 1. What happens if an interrupt is accepted while the SLEEP instruction is being executed? Classlflcatlon-HS/500 Reaisters Read timing Write timing Interrupts Reset External exoansion 0 Power-down state Instructions Software Develooment tools Answer 1. Sleep mode is released to handle the interrupt. At the end of interrupt handling. the next instruction after the SLEEP instruction is executed. Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical a&A ~ Addftlonallnformatlon Section 128 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 QA8500· 021 B Product H81500 CPU Topic Sampling and acceptance of interrupts during sleep mode Classlflcatlon-H8I500 Registers Read timing Question 1. When are external interrupts sampled during sleep mode? Wr~etiming 2. If an interrupt is sampled, how many system clock cycles later does the chip wake up? 0 Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. Level-sensitive interrupts (IRQo) are sampled on the rising edge of the system clock and edge-sensitive interrupts (external interrupts other than IRQo) are sampled on the falling edge of the system clock, just as in active mode. 2. The chip exits sleep mode six system clock cycles after the interrupt is sampled. Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ..!!!!!:J Additional Information I HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5129 Technical Question and Answer IQ&A No·1 QA8500· 027A Product H81500 CPU Topic Execution time for entering software standby mode Clasalflcatlon-H8I500 Registers Read timing Write iiming Interrupts Reset External expansion Power-down state 0 Question 1. How many states does it take to enter software standby mode by executing the SLEEP instruction? Instructions Software Development tools Miscellaneous Related Manuals Manual Title: I Answer 1. Two states. Other Technical Documentation Document Name: ~ I , Related Microcomputer Technical Q&A ~ Additional Information I Section HITACHI 5 Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589·8300 130 Technical Question and Answer Product H81500CPU Topic BRN instruction JQ&A NO.J QA8500· 023B Classlflcatlon-H8I500 Registers Read tim ina Write timinll_ Interrupts Reset External expansion Power-down state Question What sort of instrUction is BRN (or BF)? 1. a Answer l. BRN is similar to a NOP instruction, but it has a different byte length and executes in a different number of states. See below. BRN NOP Byte Length Number of States Required for Execution d:8 2 3* d:16 3 3* 1 2* • When instruction is fetched from on-chip ROM Instructions Software Development tools Miscellaneous Related Manuals Manual Title:J Other Technical Documentation Document Name: I Relatad Microcomputer Technical Q&A BRN has the same byte length as Bee, for example, which ~ makes it useful in debugging. Additional Information I HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 Section 5 131 Tech nlcal Question and Answer IQ&A No·1 QA8500· 033A Product H81500CPU Topic Reserved addresses in interrupt vector area Classlfication-H8l500 Registers Read timing Write timing Interrupts Reset External expansion Power-down state Question 1. Can \he reserved addresses in the interrupt vector area be used to store program code? 0 Miscellaneous Related Manuals Manual ntle: I Answer 1. Instructions Software Development tools Yes, they can. Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ AddHlonallnformatlon Section 132 5 I HITACHI Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No.1 QA8500 - 029A Product H81500CPU Topic Access to on-chip registers while bus is released Question 1. When the H8/S00 CPU releases the bus to an external device, can the external device (bus master) access the H8/S00's on-chip registers? Classlflcatlon-H8ISOO Registers Read timing Write timing Interrupts Reset External expansion Power-down state Instructions Software Development tools Answer 1. No. On-chip registers cannot be accessed externally under any circumstances. 0 Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I \ HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 ---" -----.--------~---- .. --'-~--.,------ ... ~ Section 5133 Section 134 5 HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 H8/500 Series Application Note Technical Q & A Preface The H8/S00 Series is a series of highly integrated single-chip microcontrollers. Their CPU core has an internal 16-bit architecture. and each chip includes diverse high-performance peripheral hardware. These technical questions and answers relate to the H8/510. H8/520. H8/532. H8/534. and H8!536. U8/500 Family Item HS/51 0 H8I520 CPU HS/SOO HS/SOO 16 kbytes Ves Memory ROM Masked ROM ZTAT"'*2 No H8I532 H8I534 H8IS36 HS/500 HS/500 H8/S00 32 kbytes 32 kbytes 62 kbytes Ves Ves Ves 2 kbytes 2 kbytes 512 bytes 1 kbyte 16 M 1M 1M External data bus width (bits) 8116 S 8 Timers 2ch 2ch 3ch 3ch 3ch 8-bit timer 1 ch 1 ch 1 ch 1 ch 1 ch Watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch 3 ch 3ch 3ch 1 ch 2 ch 2 ch RAM Address space (bytes) 16-bit free-running timer PWMtimer Serial communication interface (async/sync) 2ch 2ch 1M ·S 1M 8 AID converter External trigger input Interrupts External interrupts 5 9 3 7 7 Internal interrupts 18 18 19 23 23 I/O ports 60 50154"' 65 65 65 Packages QFP-112 LCC-84 DILC-64S LCC-S4 LCC-84 (windowed) (windowed) (windowed) (windowed) ~I ~ 10 bits. 4 or 10 bits. 10 bits. 10 bits. 10 bits. 4 channels. S* channels. 8 channels. 8 channels. 8 channels. trigger trigger no trigger no trigger no trigger DILP-64S PLCC-84 PLCC-68"' QFP-80 PLCC-84 PLCC-84 QFP-80 QFP-80 QFP-64 Notes: 1. PLCC-68 package 2. zt:AT'" is a registered trademark of Hitachi. Ltd. / HITACHI Hitachi America. Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300 Section 5 135 How to Use These Technical Questions and Answers Technical Questions and Answers has been created by arranging technical questions actually asked by users of Hitachi microcomputers in a question-and-answer format. It should be read for technical reference in conjunction with the User's Manual. Technical Questions and Answers can be read before beginning a microcomputer application design project to gain a more thorough understanding of the microcomputer, or during the design process to check up on difficult points. (For questions and answers about the H8/500 CPU, see 1/8/500 CPU Microcomputer Technical Questions and Answers.) Section 136 5 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Contents Q&ANo. Page On-chip ROM (1) Address bus, data bus, and control line states during access to on-chip address space (2) Programming the H8/536 ZTAT QA500 -OOlB 139 QA500-046A 140 QA500-002B QA500-047A QA500 -OO3B QA500-048A 141 142 143 144 Clock (1) (2) (3) (4) EXTAL and system clock output line External clock speCifications External clock input External clock input (2) Timers (1) External clock input to 16-bit FRT (2) Input capture signal for l6-bit FRT (3) Access timing to FRC in 16-bit FRT (4) TCNT of 8-bit timer (5) WDT when system clock stops (6) NMI requested by WDT 145 QA500-006B 146 QA500 - 007B QA500 - 009B - I 147 QA500 - 009B - 2 148 149 QA500 - OllB 150 QASOO - 012B 151 QA500 - Ol3B Serial communication interface (SCI) (I) Input/output designation of SCI clock pin (2) Serial I/O line status (3) RDRF bit set timing (4) TDRE bit set timing (5) (6) (7) (8) (9) (10) (11) (12) RDR and DTR utilization when SCI is not used RDRF bit in SCI SCI receive error 1 SCI receive error 2 (clocked synchronous mode) SCI RxD input example (asynchronous mode) SCI transmit start (asynchronous mode) Simultaneous transmit/receive in clocked synchronous mode Clearing the SCI's TDRE bit QA500 -OlgB QA500 -019B QA500 - 021B QA500 - 021B QA500 - 022B QA500 - 022B QA500 -023B QA500 -049A QA500-050A QA500 -05IA QA500 - 052A QA500 -053A QA500-054A QA500 -OSSA 1 2 1 2 152 153 154 155 156 157 158 159 160 161 162 163 164 165 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 ~E frl CI) Section 5137 Q&ANo. Page AiD converter (1) (2) (3) (4) (5) (6) Start of AID conversion Non-use of NO converter reference voltage lines (AVcc. AVss) Changing AID conversion mode or channels during conversion Resistor ladder in NO converter Rise time of power supplies (AV cc. Vcd Allowable impedance of NO signal sources QA500-024B QA500 - 025B. QA500-027B QA500-028B QA500-029B QA500-056A 166 167 168 169 170 QA500 -031B QA500-057A 172 173 QA500 -032B QA500 -033B 174 175 QA500 -035B QA500 -037B QA500 -039B QA500-040B 176 177 178 179 QA500 - 0418 180 QA500-058A 181 QA500-059A 182 QA500-060A 183 171 PWMtimer (1) OTR of PWM timer (2) PWM pin assignments Data transfer controller (DTC) (1) Interrupts during DTC operation (2) OTCusage VO ports (1) (2) (3) (4) Analog input part data register during NO conversion Port output after reset AS and RO signal timing Unused I/O lines Power-down modes (1) Power dissipation in hardware and software standby modes Bus controller (1) State of Do to 0 7 with 8-bit data bus Bus interface (1) State of Do to 0 7 during byte access in 16-bit data bus mode Miscellaneous (I) RAM standby voltage Section 138 5 HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 QASOO - 001B Product H8/S00 Topic Address bus, data bus, and control line states during access to on-chip address space Question 1. What values are output on the following lines when on- chip memory or the on-chip register field is accessed? (1) Address bus (2) Data bus (3) Bus control signals Answer (1) The address bus carries the address data, regardless of whether the access is to an on-chip or off-chip address. (2) The data bus is in the high-impedance state for both read and write access by the CPU to an on-chip address. RtW signal is low for write access and high for read access. The other control signals (AS, OS, RD, WR) are high. (3) The Claeslflcatlon-H8ISOO Software On-chipROM 0 On-chip RAM 0 Clock Timers Serial 110 AID PWM DTC 1/0 POrts Power-down modes Elec. characteristics Exception handlina Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A f-!!!!!!J . Additional Information I HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 SectiOn 5139 Technical Question and Answer IQ&A No·1 Product H81536 Topic Programming the H81536 ZTAT QA500· 046A Question 1. We are having trouble programming the ZTAT version of the H8/536. Are there any precautions we may be missing? Answer 1. When programming the H8/536. you must set your PROM writer to memory type HN27ClOi and either write H'FF data in addresses H'P680 to H'IFFFF or set H'P67P as the end address. Be sure to use byte programming mode. The H8/536 does not support page programming. Classlflcatlon-H8/536 Software On-chip ROM 0 On-chip RAM Clock Timers Serial 1/0 AID PWM DTC 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title:-T Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I Some PROM writers do not support byte programming for the HN27CIOL Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 140 Technical Question and Answer Product H81500 , Q&A NO.' QA500· 002B Topic EXTAL and system clock output line Que.tlon 1. During external clock input, what is the phase relationship between EXTAL and the system clock output line (~ output)? Classlflcatlon-H8I500 Software On-chipROM On-chip RAM 0 Clock limers Serial 1/0 AID Answer 1. During external clock input, the phase relationship between EXTAL and the system clock output line is as shown below. EXTAL PWM DTC VOports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual TItle: I Other Technical Documentation Document Name: ,, ,,, , "outPut~~ ~-, I Related Microcomputer Technical Q&A ...!!!!!.:J Approx. 40 ns internal delay Additional Information I The internal delay value is not guaranteed. HITACHI Hitachi America, Ltd .• San Francisco Center • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 5S9-S300 SectIOn 5 141 Technical Question and Answer IQ&A No·1 QASOO - 047A Product H8J500 Topic External clock specifications Question 1. When an external clock is supplied to the EXTAL pin, what are the rise-time and fall-time requirements? Classlflcetlon-H8J500 Software On-chiDROM On-chipRAM 0 Clock Timers 8erlaill0 AID Answer 1. For a 20-MHz clock, the rise time (ter) and fall time (ter) should both be approximately 5 ns. External clock (EXTAL) PWM DTC 110 DOnS Power-down modes Elec. characteristics ExceDtion handlina Bus interface External eXDansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: tCI I tCr Related Microcomputer Technical Q&A ...!!!!!:J \ AddHlonallnformetlon Section 142·5. I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product H8P.520,S32,534,536 Topic External clock input IQ&A No.l OASOO - 003B auestlon 1. For external clock input, the Hardware Manual shows an example of a circuit using a 74HC04 (see below). Why is the 74HC04 necessary? EXTAL . .JUUL External clock input LJ74HC04 XTAL Anawer 1. If the XTAL pin open is left open, operation may become unstable. Claalflcatlon-H8I532 Software On-ch~ROM On-chipRAM 0 Clock limers Serial 110 AID PWM OTC 110 ports Power-c:lown modes Elec. characteristics Exception handling Bus interface External e~ansion OeveiQll.ment tools Misceilaneous Related Manuala Manual nile: I The 74HC04 is necessary to assure stable operation at high Other Technical clock rates. Documentation Document Name: J Related Microcomputer Technical QaA I-.!!!!!:J Additional Information I Note: The XTAL pin can be left open if the external clock rate is 16 MHz or less. For maskedROM versions and the H8/510, the XTAL pin can be left open for external clock rates up to 20 MHz. HITACHI Hitachi America, Ltd.' San FranCisco Center • 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300 Sectton 8143 Technical Question and Answer Product H8/520, 532, 534, 536 Topic External clock input (2) IQ&A No·1 QA500 - 048A Question 1. The H8/500 Series User's Manuals (except H8/51O) show a circuit using a 74HC04 for external clock input. (See diagram on previous page.) Can an ALS-TIL, for example, be used instead? Answer 1. An ALSoTIL device can be used if its propagation delay time and drivability are equivalent to the 74HC04. Classlflcatlon-H8I532 Software On-chip ROM On-chip RAM 0 Clock Timers Serial 110 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~. Additional Information Section 144 5 I HITACHI Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product He/SOO Topic External clock input to IS-bit FRT - Question 1. QASOO - OOSB When the external clock source is selected for the 16-bit free-running timer, what is the minimum pulse width of the external clock (Fl'CI)? Answer 1. The minimum pulse width of the external clock is 1.5 system clock cycles. Other Technical Documentation Document Name: " FTC, Ciasslflcation-HBISOO Software On-chip ROM On-chip RAM Clock Timers 0 Serial 110 AID PWM DTC 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I """'I. I I Related Microcomputer Technical Q&A .1 ~ I.S system clocks Addltlonallnformatlon I I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5145 Technical Question and Answer IQ&A No.1 QA500 - 007B Product H81500 Topic Input capture signal for 16-bit FRT Question 1. If an FRT input capture line (FTI) is multiplexed with a general-purpose inpul/output port that is used for output, will the rise and fan of the output data update the input capture register? Claaslflcatlon-H8I500 Software On-chipROM On-chip RAM Clock 0 Timers Serial 1/0 AID Answer 1. Yes. The input capture register will be updated by output on the inpul/output line, on the edge selected by the input edge select bit (IEDG) in the timer controVstatus register (TCSR). PWM DTC 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interlace External expansion Development tools Miscellaneous Related Manuals Manual TItle: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I Section HITACHI 8 Hitachi America. Ltd.· San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300 146 Tech nical Question and Answer Product H8/S00 , alA NO., QASOO - 0098 - 1 Topic Access timing to FRC in 16-bit FRT auestion 1. What is the read and write timing of the free-running counter (FRC) in the 16-bit free-running timer (FRT)? Classlflcatlon-H8I500 Software On-chip ROM On-chip RAM Clock 0 Timers Serial 110 AiD PWM DTC I/O~rts Answer 1. The access timing of the 16-bit timer's FRC is shown on the next page. Word access (or two successive byte accesses) should be used. The upper byte has to be accessed first. Power-down modes Elec. characteristics Exception handli~ Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name:J Related Microcomputer Technical alA ~ Additional Information I HITACHI Hitachi America. Ltd.· San FranCisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819. (415) 589-8300 Section 5147 Technical Question and Answer Product H81500 Topic Access timing to FRC in 16-bit FRT QASOO - 0098 - 2 Answer " Internal address bus Internal read signal Internal data bus (FRCL'" TEMP) FRC N FRC Access Timing (read) Operation when register is read When the upper byte is read. the upper byte value is passed to the CPU and the lower byte value is transferred to TEMP. Next. when the lower byte is read. the lower byte value in TEMP is passed to the CPU. " Internal address bus Internal write signal He/soo CPU write: Internal data bus High data (High data'" TEMP) FRC He/soo CPU write: : Low data (Low data ... FRCL. TEMP. ... FRCH) N FRC Access Timing (write) Operation when register is written When the upper byte is written. the upper byte value is stored in TEMP. Next. when the lower byte is written. it is combined with the upper byte value in TEMP and all 16 data bits are written in the register. Section 148 5 HITACHI Hitachi America. ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/S00 Topic TCNT of 8-bit timer QASOO· 011B Question 1. When a compare-match signal clears the timer counter (TCNT) to H'OO, does TCNT remain at H'OO, or does it start counting up from H'oo? Answer 1. TCNT starts counting up from H'OO. Classlflcatlon-H8I500 Software On-chip ROM On-chip RAM Clock 0 Timers Serial I/O AID PWM DTC I/OjlOrts Power·down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ..!!!!!:J Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 149 Technical Question and Answer IQ&A NO., QA500· 012B Product H8/500 Topic WDT when system clock stops Question 1. If the system clock stops, will the watchdog timer (WDT) detect anything wrong? Answer 1. If the system clock for the whole chip stops, the WDT count also stops, so the WDT cannot detect the failure. Classlflcatlon-H8/500 Software On-chipROM On-chipRAM Clock Timers 0 Serial I/O AID PWM DTe I/O ports Power-down modes Elec. characteristics Exception handling. Bus interface External expansion Development tools Miscellaneous Related Manuals Manual TItle: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information Section 150 5 I HITACHI Hitachi America, Ltd.· San Francisco Center • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/532 Topic NMI requested by WOT Question 1. How can you distinguish between an NMI interrupt requested from the NMI pin and an NMI interrupt requested by the watchdog timer (WDn? QASOO - 013B Classlflcatlon-H8I532 Software On-chipROM On-chip RAM Clock 0 limers Serial 1/0 AID PWM OTC 1/0 ports Answer 1. When the WDT requests an NMI interrupt, it sets the overflow bit (OVP) in the WDT timer status/control register (TCSR) to 1. You can detect this by software. NMI requested by input signal from pin NMI requested by WOT Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I OVF Bit In TCSR Other Technical Documentation 0 Document Name: 1 I Related Microcomputer Technical Q&A ~ Additional Information I When the WDT is used in interval timer mode, IRQo interrupts can be discriminated in the same way. (H8/520, H8/532) HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 151 Technical Question and Answer IQ&A No·1 OASOO· 018B Product H81500 Topic Input/output designation of SCI clock pin Question 1. When the SCI is used, is the serial clock pin designated for input or output by writing a 0 or } in the data direction register (DDR) of the corresponding port? Answer 1. When you use the SCI, the input or output setting of the clock line depends on the communication mode bit (CiA.) in the serial mode register (SMR) and the clock enable I and 0 bits (CKE} and CKEO) in the serial control register (SCR) .. You don't have to set the DDR. Classlflcatlon-H8ISOO Software On·chipROM On-chip RAM Clock Timers Serial 1/0 0 AID PWM DTC I/0perts Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I other Technical Documentation Document Nam.e: I Related Microcomputer Technical Q&A ~ Additional Information Section 152 5 I HITACHI Hitachi America, Ltd.• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/S00 Topic Serial I/O line status QASOO· 019B Question 1. After input/output ports multiplexed with TxD, RxD, and SCK lines have been used for serial communication, suppose they are redesignated as I/O ports by settings made in the serial control register (SCR) or serial mode register (SMR). What values will the corresponding data direction register (DDR) contain? Answer 1. SCI operations do not affect the contents of the DDR bits of input/output pons. Given the conditions you describe, the DDR bits will retain the values they had before the pins were used for serial communication. Classlflcatlon-H8/S00 Software On·chipROM On·chipRAM Clock Timers Serial I/O 0 AID PWM DTC I/O ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous' Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 153 Technical Question and Answer 'Q&A Product H8/S00 Topic RDRF bit set timing No., QASOO· 021B-1 Question 1. When data reception is completed, the receive data register full bit (RDRF) in the serial status register (SSR) is set 10 1. At what timing does this occur in asynchronous mode? 2. At what timing does this occur in clocked synchronous mode? Answer See the next page. CIa..Hlcatlon-H8l5OO Software On-chiDROM On-chipRAM Clock Timers Serial I/O 0 AID PWM DTC I/O POrts Power-down modes Elec. characteristics ExceDiion handli~ Bus interface External expansion Development tools Miscellaneous Related Manua.. Manual ntle: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ..:rn!!:..J Addltlonellnformetlon SectIon 154 II I HITACHI Hitachi America, Ud.• San FranciSCO Center • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product H81500 Topic RDRF bil selliming Answer 1. The RDRF bit is set to 1 after the fall of the next data sampling clock after the MSB of the data is received. (See the diagram below.) 1 23456789101112131415161 2345678910111213141516 Basic clock Receive data 07 STOP Data sampling ------' RDRF _____________~...:.....JF 0:5 to 1.59 8·Bit Data, 1 Stop Bit, Internal Clock 2. The RDRF bit is set to 1 after the rising edge of the serial clock cycle in which the MSB of the data is received. (See the diagram below.) Serial clock Receive data RDRF ____________-'--'F 0.510 1.50 8·Bit Data HITACHI Hitachi America, Lid.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5155 Technical Question and Answer , Q&A NO., QA500· 022B - 1 Product H81500 Topic TORE bit set timing Question 1. When eight data bits have been transmitted, the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1. At what timing does this occur in asynchronous mode? 2. At what timing does this occur in clocked synchronous mode? Answer The TDRE bit is set to 1 at different times depending on whether the transmit shift register (TSR) contains transmit data or not. 1. MMulM_ Asynchronous mode 1.1 Transmit data present in TSR (see diagram below) Basic clock Receive dal. TORE I Stop bil ~ I Start b~ C Classlflcatlon-H8ISOO Software On-chip ROM On-chip RAM Clock Timers Serial 110 0 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Fo.510l,5. The timing of the start of transmission after the transmit enable bit (TE) is set is similar. Additional Information I Continued on next page. Section 156 a HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product H8/500 Topic TDRE bit set timing Answer 1.2 No transmit data in TSR (see diagram below) " Internal write signal Basic clock TORE TORE is set in interval from 8 basic clocks + 0.5" to 24 basic clocks + 1.5" 2. Clocked synchronous mode 2.1 Transmit data present in TSR (see diagram below) Serial clock Transmit data TORE ____________--'--IF 0.5 to 1.5" 2.2 No transmit data in TSR (see diagram below) " Internal write signal TORE TORE is set in interval from 2" to 0.5 basic clock + 1.5" HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5157 Technical Question and Answer IQ&A No·1 Product H8/S00 Topic RDR and DTR utilization when SCI is not .used QASOO· 023B Question 1. When the serial communication interface is not used, can the foIlowing be utilized as data registers? (1) RDR (receive data register) (2) TDR (transmit data register) AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title:! Answer l. Classlflcatlon-H8/500 Software On-chip ROM On-chip RAM Clock limers Serial 110 0 The answer is as follows: (1) RDR is a read-only register, so it cannot be used as a data register. (2) TDR can be used as a data register. Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A f.!!!!!.!J Additional Information Section 158 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 QASOO - 049A Product H81500 Topic RDRF bit in SCI Classlflcatlon-H8JSOO Software On-chipROM On-chipRAM Clock Timers Serial 110 0 AID PWM DTC 1I0perts Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Answer 1. The RDRF bit retains its 1 value and is not cleared to O. An Manual ntle: I overrun error occurs at completion of receiving the next data. Question 1. To receive serial data. the receive data register full bit (RDRF) in the serial status register (SSR) must be cleared to O. What happens if 0 is written in the bit directly. without first reading I? Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ...!!!!!=J Additional Information I Similar considerations apply to the transmit data register empty bit (TDRE). HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 Section 5159 Technical Question and Answer IQ&A NO., Product HS/500 Topic SCI receive error 1 QA500 - 050A Question 1. If the receive-error interrupt handler returns to the main program without clearing the overrun flag (ORER), framing error flag (FER), or parity error flag (PER) in the serial status register (SSR) to 0, will a receive error occur again? Answer 1. I After one more instruction is exec,uted in the main program the receive error will occur again, because the error flag itself is the interrupt source. Classificatlon-H8/S00 Software On-chip ROM On-chip RAM Clock Timers Serial 1/0 0 AID PWM DTC I/O ports Power-down modes Elec. characteristics Exception handlinQ Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I This holds for all on-chip supporting modules, excluding only the external interrupts. Section 160 5 HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.·' Brisbane,CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product H8/S00 Topic SCI receive error 2 (clocked synchronous mode) QASOO - OS1A Question 1. When the SCI is used in clocked synchronous mode, at what time is an overrun error detected? Answer 1. The overrun error bit CORER) is set to 1 after the rise of the serial clock when the most significant data bit (bit 7) is received. I Serial clock Receive data Bit 6 I Other Technical Documentation Document Name: I Bit 7 --ORER Classlflcatlon-H8/S00 Software On-chipROM On-chip RAM Clock Timers 0 Serial 110 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I 4- O.S to 1.S0 II Related Microcomputer Technical Q&A ~ Reception of 8·Bit Data AddHlonallnformation I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5161 Technical Question and Answer I No·1 Product H8/S00 Topic SCI RxD input example (asynchronous mode) Q&A QASOO - OS2A Classlflcatlon-H8IS32 Question 1. Suppose the RxD pin is being used as an input port and is now low. Do any precautions have to be taken in order to switch this pin over to its RxD function and recei ve ·serial data correctly? 2. Do any precautions have to be taken in order to receive data correctly after detecting the break condition? 0 Answer 1. Change the RxD input to high before setting the SCI's receive enable bit (RE) to 1. 2. Before reception of the first data, supply high input to the RxD line for at least one frame. Software On-chip ROM On-chip RAM Clock Timers Serial I/O AID PWM DTC I/O ports Power-down modes Elec. characteristics Exception handling Bus interface External e~ansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ...!!!!!J J AddHlonallnformation Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 162 Technical Question and Answer IQ&A No·1 QASOO· OS3A Product H8/500 Topic SCI transmit start (asynchronous mode) Question 1. Answer 1. The delay time is eight basic clock cycles (O.5!/l to 1.5!/l). See the diagram below. :JiMM~ Basic clock TORE Transm~ data Classlflcatlon-H8/500 Software On-chipROM On-chip RAM Clock Timers Serial 110 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I In the SCI transmitting sequence, following the transfer of data from TOR to TSR, the transmit data register empty bit (TORE) in the serial status register (SSR) is set to I, then the SCI starts transmitting data. How much delay is there from the time when the TORE bit is set to 1 until output of 0 the start bit? - I-- 0.5 to 1.50 I Stop bit Start bit I 8 basic clock cycles (0.5" to 1.5,,) Other Technical Documentation Document Name: I I Related Microcomputer Technical Q&A ...!!!!!.:.J Additional Information I The same timing applies when transmission starts from the setting of the transmit enable bit (TE). HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589-8300 Section 5 163 Technical Question and Answer IQ&A No.1 OASOO - OS4A Product H8/S00 Topic Simultaneous transmit/receive in clocked synchronous mode Data cannot be transferred. Classlflcation-H8ISOO Software On-chipROM On-chip RAM Clock Timers Serial I/O 0 AID PWM DTC I/O POrts Power-down modes Elec. characteristics Exception handlina Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I In simultaneous transmitting and receiving in clocked synchronous mode, transmitting or receiving cannot proceed independently before the ORER and TORE bits are both.cleared to O. Other Technical Documentation Document Name: Question 1. During simultaneous transmitting and receiving in clocked synchronous mode, can data be transferred in the state when an overrun error has occurred? Answer 1. I I Related Microcomputer Technical Q&A ~ Additional Information Section 164 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 QASOO· OSSA Product H8/S00 Topic Clearing the SCI's TORE bit Question I. When transmitting data, will there be any data transfer problem if we wait until after writing transmit data in the transmit data register (TOR) to read the 1 value of the TORE bit, then clear this bit to O? \ Answer I. No problem will occur. Classlflcatlon-H8/S00 Software On-chipROM On-chip RAM Clock Timers 0 Serial 110 AID PWM DTC I/Oports Power-down modes Elec. characteristics Exception handling External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I If you write in TOR while the TDRE bit is 0, however, you will destroy the previous TDR data. HITACHI Hitachi America, Ltd.· San Francisco Genter· 2000 Sierra Point PkWy.· 8risbane, GA 94005·1819 • (415) 589·8300 Section 5165 Technical Question and Answer IQ&A No.1 OASOn - 0248 Product H81500 Topic Start of AID conversion Question 1. Software can select the start of AID conversion by setting the AID start bit (ADS1) in the AID controVstatus register (ADCSR) to 1. What happens if 1 is written in the ADST bit again while AID conversion is in progress? 2. What happens if AID conversion starts by detection of the falling edge of the extemaltrigger signal (ADTRG), then ADTRG goes high while AID conversion is in progress? (H8/510, H8/520, H8/534, H8/536) Answer 1. If the ADST bit is set to 1 again during AID conversion, it will be ignored and AID conversion will continue. Classlflcatlon-H8ISOO Software On-chipROM On-chipRAM Clock Timers Serial VO 0 AID PWM DTe 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual TItle: I - 2., Operation will be normal if the ADTRG signal is low for at least 1.5 cycles. Mter that, if the ADTRG signal goes high Other Technical Documentation again during AID conversion, it will be ignored and AID Document Name: I conversion will continue. Related Microcomputer Technical Q&A ..!!!!!:..l AddHionallnformatlon Section 1665 I HITACHI Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 QASOO - 025B Product H81500 Topic Non-use of AID converter reference voltage lines (AVec. AVss) Question 1. When the AID converter is not used. what should be done with the AVee and AVss pins? -- Answer 1. Even when the AID converter is not used. AVec should be connected to Vee andAVss to VSS' Classlflcetlon-H8ISOO Software On-chipROM On-chipRAM Clock limers Serial If0 0 AID PWM DTe IfO~rts Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual TItle: I 10 bit DlA (Reference) AVec AVec ~ -- AVss Comparator .... Other Technlcel Documentation Document Name: I + Vss AVss (1) If AVee is left open. voltage potentials in the interface to the digital circuits in the AID converter will be unstable. Related Microcomputer Technical Q&A ~ (2) AVss and V ss are shorted inside the chip., Any potential difference between them will cause excessive current drain. J Additional Information HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-83QO Section 5167 Technical Question and Answer IQ&A No·1 QASOO - 027B Product H8I500 Topic Changing AID conversion mode or channels during conversion Question During AID conversion, what happens if you: 1. Change the AID conversion mode? 2. Change the channel selection? Answer 1. Avoid changing the AID conversion mode during AID conversion. Conversion accuracy will be degraded. 2. Avoid changing the channel selection during AID conversion. The same problem will occur as in 1. Classlflcatlon-H8/SOO Software On-chip ROM On-chip RAM Clock Timers Serial 110 0 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface Extemal expansion Development tools Miscellaneous Related Manuals Manual TItla: I Other Technical Documentation Document Name: I " Related Microcomputer Technical Q&A ~ Additional Information I Note: Check the AID end flag (ADF) in the ND controVstatus register (ADCSR), then: 1. Change the AID conversion mode. 2. Select the channel(s).\ Seello", 168 5 HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1· QASOO - 028B Product H81500 Topic Resistor ladder in AID converter Claaalflcatlon-H8ISOO Software On-chipROM On-chip RAM Clock Timers Serial VO Question 1. Are the analog power supplies of the NO converter connected only to the resistor ladder? AID PWM DTC 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I 0 Answer 1. The analog power supplies are connected not only to the resistor ladder but also to analog circuits in the comparator etc. They also power the interface to digital circuits in the NO converter. Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ...!!!!!:..J Additional Information I HITACHI Hitachi America, Ltd.' San Francisco Center· 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819' (415) 589-8300 Section 5169 Technical Que,stion and Answer \ IQ&A No·1 QASOO - 029B Product H81500 Topic Rise time of power supplies (AVec, Vec) Classlflcatlon-H8ISOO Software On-chipROM On-chipRAM Clock Question 1. Will any problems occur if there is a difference in rise times between the analog power supply (AV cd and digital power_supply (Vcc)? Time~ Serial VO 0 Answer 1. There is no restriction on the order in which AVcc and V cc are powered up. During the interval marked A in the diagram below, voltage potentials in the interface to digital circuits in the AID converter are unstable, which may cause fluctuations in current drain. AID PWM DTC I/O ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscelianeous Related Manuals Msnual Tltla: I , Other Technical Documentation Document Name: I A Vcc J Related Microcomputer Technical Q&A ~ / AVec Additional Information V / I section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 110 Technical Question and Answer Ia&A No·1 Product H8/500 Topic Allowable impedance of AID signal sources QA500· 056A auestlon l. Does the allowable signal source impedance remain 10 ill even if the NO conversion time is changed? Answer l. The low-speed conversion mode should operate even at 20 ill, but this is not guaranteed. Classlflcatlon-H8/500 Software On-chip ROM On-chip RAM Clock Timers Serial 1/0 AID 0 PWM DTC 1/0 ports Power·down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name:J Related Microcomputer Technical a&A ~ Additional Information , I HITACHI Hitachi America, Ltd.· San FranCisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589·8300 Section 5171 Technical Question and Answer Product H81532, H8/534, H8/536 Topic DTR of PWM timer IQ&A No.1 QA500 - 031 B Classlflcation-H8l532 Software On-chipROM On-chip RAM Clock Timers Serial 1/0 Question 1. The duty register (DTR) of thePWM timer is set to H'OO for pulses with 0% duty cycle, H'7D for pulses with 50% duty cycle, and H'FA for pulses with 100% duty cycle, but what if a value from H'FB to H'FF is written in DTR? AID 0 Answer 1. If a value from H'FB to H'FF is written in DTR, pulses are output with a 100% duty cycle. PWM DTe 1/0 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ AddHlonallnformatlon Section 172 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product HS/534, HS/536 Topic PWM pin assignments IQ&A No·1 QA500 - 057A Classlflcation-H8/534 Software On-chipROM On-chip RAM Clock Timers Serial 110 Question 1. The PWM timer outputs (pW 1 10 PW3) are can be assigned 10 P6 1 10 P6:l (multiplexed with IRQ3 to IRQs) or P9 z 10 P9 4 (multiplexed with SCK z, RxDz, and TxDz). Can all six pins be used for PWM output? AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External e~ansion Devel",,-ment tools Miscellaneous Related Manuals Manual Title: I 0 Answer 1. Yes, they can. Other Technical Documentation Document Name:J Related Microcomputer Technical Q&A ~ Additional Information I P61 to P6:l can be used for both PWM output and IRQ input. P9 2 to P94 can be used for either PWM output or SCI functions, but not both. HITACHI Hitachi America, Ltd.· San FranCisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5173 Technical Question and Answer IQ&A No·1 QASOO - 032B Product H8/S00 Topic Interrupts during DTC operation auestlon I. During operation of the data transfer controller (DTC), what happens if an interrupt is requested with a priority higher than the interrupt the DTC is serving? Answer I. While the DTC is operating the CPU hall~, so no other interrupts can be accepted. The DTC therefore completes its interrupt service, after which one instruction is executed; then the pending interrupt-handling sequence begins. Classlflcatlon-H8I500 Software On-chip ROM On-chip RAM Clock Timers Serial 110 AID PWM DTC 0 I/Operts Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I If the instruction executed after the conclusion of DTC operations is LDC or another instruction that inhibits interrupts, the interrupt-handling sequence will not start until the next instruction after that has been executed (and if that next instruction also inhibits interrupts, another instruction will be executed). Section 1745 HITACHI Hitachi America, Ltd.· San Francisco Center. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product He/SOO Topic DTCusage IQ&A No·1 OASOO - 0338 Classlflcation-H8I500 Software On-chip ROM On-chip RAM Clock Timers Serial I/O Question 1. Can DTC register information be located on ROM? 2. After a DTC data transfer, the data transfer count register (DTCR) is decremented by I, and if the result is 0, the DTC will no longer be activated. If DTC register information is stored on ROM with the DTCR value set to I, will an interrupt occur after the DTC data transfer? Answer 1. DTC register information can be located on ROM. 2. An interrupt will be generated. The decision as to whether DTCR =0 is made when the DTCR value is decremented. AID 0 PWM DTC I/O POrts Power-down modes Elec. characteristics Exception handling External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 175 Technical Question and Answer IQ&A No·1 QASOO - 03SB Product H8/S00 Topic Analog input port data register during AID conversion Question 1. During NO conversion, what happens to the values in the data register (DR) of the input port that is also used for analog input? Answer 1. Pins used for analog input return the value 1 if read during NO conversion, regardless of the actual input voltage. Classlflcatlon-H8/S00 Software On-chip ROM On-chip RAM Clock Timers Serial I/O A/D PWM DTC 0 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ...!!!!!J Additional Information Section 176 5 I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer IQ&A No·1 Product HB1500 Topic Port output after reset QA500· 037B Classlflcatlon-H8I500 Software 1. To use an input/output port line to output data after a reset, On-chipROM whieh should be set fllSt: the port's data register (DR) or its On-chip RAM dats direction register (DDR)? Clock limers Serial 110 AID PWM DTC 1I0perts 0 Power-down modes Elee. characteristics Exception handlina Bus interface External expansion Development tools Miscellaneous Related Manuals Answer Manual Title: 1. Set these registers in the following order. Question r (I) Set the output data in the output port's data register. (2) Set the DDR bit of the output line to I. Other Technical Documentation Document Name: I Related Microcomputer Technical QU ~ Additional Information I Note: A reset initializes the port data registers to O. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300 Section 177 5 Technical Question and Answer IQ&A No·1 Product H81500 Topic ~ and Ri5 signal timing QASOO - 039B Question l. Are the AS and RD signals synchronized with the falling edge of the system clock (16), or with output on the address lines? Classlflcatlon-H8I500 Software On-chioROM On-chip RAM Clock Timers Serial VO AID Answer l. The AS and RD signals are synchronized with the falling edge of the system clock in the T 1 state. The AS and RD signals never go low before ttie falling edge in the T 1 state. Case A in the diagram below cannot occur. ~T, T2 T3.,----, II Ao to A,s ----J - lAD PWM DTC IIOporls 0 Power-down modes Elec. characteristics ExcePtion handlina Bus interface External expansion Development tools Miscellaneous Related Manuals Manual TItle: I Other Technical Documentation Document Name: I '---I~~n Related Microcomputer Technical Q&A ..!!!!!J - ..... loso, lAS' AS. RD Case A ~ _____ Additional Information Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 178 Technical Question and Answer IQ&A No.1 QA500 - 0408 Product H8J500 Topic Unused 110 lines Question 1. What should be done with unused 1/0 port lines? Claaslflcatlon-H8lSOO Software On-chipROM On-chip RAM Clock Timers SeriallJO AID Answer 1. (1) Pull unused input/output port lines up or down through an approximately lO-ill resistor. (2) PWM DTe IJOports 0 Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Do the same for input-only port lines. Other Technical Documentation Document Nama: I Related Microcomputer Technical Q&A ~ AddHlonallnformatlon I Connect a separate pull-up or pull-dOwn resistor to each line. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy~. Brisbane, CA 94005-1819 • (415) 589-8300 Section 5179 Technical Question and Answer IQ&A No·1 QA500 - 041 B Product HS/520, 532, 534, 536 Topic Power dissipation in hardware and software standby modes Question 1. Is there any difference in current dissipation between hardware standby and software standby? Answer 1. Current dissipation satisfies the relationship: Classlflcatlon-H8/532 Software On-chipROM On-chip RAM Clock Timers Serial 1/0 AID PWM DTC 110 ports Power-down modes 0 Elec. characteristics Exception handling Bus interface External expansion DeveloFment tools Miscellaneous Related Manuals Manual Title: I hardware standby $ software standby. In hardware standby mode, all lines are placed in the highimpedance s):ate, which reduces current dissipation. In software standby mode I/O ports hold their previous states, so current dissipation varies depending on the state of the Other TechnIcal Documentation Document Name:] port. Related Microcomputer Technical Q&A ...!!!!!J Additional Information I Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 180 Technical Question and Answer IQ&A No.1 QASOO - OS8A Product H81510 Topic State of Do to 0 7 with 8-bit data bus auestlon 1. In 16-bit data bus mode (mode 2 or 4), during access to the area accessed via an eight-bit bus, what are the states of the unused data bus lines (Do to ~) and control signals? Clasalflcatlon-H8IS10 Software On-chipROM On-chipRAM Clock limers Serial 1/0 AID PWM DTe 1I0~rts Answer 1. Do to ~ are in the high-impedance state, and LWR is always 1. Power-down modes Elec. characteristics Exception handling Bus interface Development tools Bus controller 0 Miscellaneous Related Manuals Manual Title: I Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A f-TI!!!;J Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5181 Technical Question and Answer IQ&A No·1 Product HS/Sl0 Topic State of Do to 0 7 during byte access in 16-bit data bus mode QASOO - OS9A Question 1. What are the pin states during access to byte data in 16-bit data bus mode (mode 2 or 4)? Answer 1. (1) In write access, the upper data bus (0 15 to Os) and lower data bus (~ to Do) both output the same data. Classlflcatlon-H8I500 Software On-chip ROM On-chip RAM Clock TImers Serial I/O AID PWM DTe I/O flOrts Power-down modes Elec. characteristics Exception handling 0 Bus interface External expansion Development tools Miscellaneous Related Manuals Manual Title: I Control signal states are as follows: (2) Access to even address Access to odd address LWR=l LWR=O HWR=O HWR=1 In read access, the states differ depending on the external circuit configuration. Control signal states are as follows: RD=O Additional Information 1. Section 182 5 Other Technical Documentation Document Name: I Related Microcomputer Technical Q&A ~ I The minimum RAM standby voltage (VRAM) is specified at 2.0 V. What voltage should be supplied to AVec? HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Technical Question and Answer Product H8/520, 532, 534, 536 Topic RAM standby voltage IQ&A No·1 OA500 - 060A Question Answer 1. AVec should be the same as the RAM standby voltage: 2 V. Setting AVec to 5 V or VSS will cause excessive current drain. Cla8slflcatlon-H8/532 Software On-chipROM On-chip RAM Clock Timers Serial 110 AID PWM DTC 110 ports Power-down modes Elec. characteristics Exception handling Bus interface External expansion Development tools Miscellaneous 0 Related Manuals Manual ntle: I Other Tachnical Documentation DOcument Nama: I Related Microcomputer Technical Q&A ~ Additional Information I HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 183 Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 184 April,1992 H8/520 Device EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/520 Microcontroller has an EPROM security feature that can be used by the customer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the device from being read by means other than his own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory ConfigUration The memory matrix of the H8/520 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64-byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the device is placed into; EPROM programming mode or CPU operation mode. EPROM Programming Mode r In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "I" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. bit=1 bit=O EPROM data can be read (normal) ''00'' data is always read HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5185 H8/520 Device EPROM Security Tech Notes CPU Operating Mode In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit isa "I" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bit is a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. bit=l bit=O EPROM data can be read by CPU (normal) After RESET, the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or internal RAM). Once an instruction is executed outside the internal EPROM memory area, then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM. Programming the Security Bit There exists two EPROM programming modes; normal and security. The normal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/520 device. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: H8I520 Programming Mode Device 1/0 Port Pin P50/TMCI P51/FTI1 Normal 1 1 Security 1 0 Again, thisfeature cannot be tested by Hitachi and thus remains unguaranteed. II is up to the user to detennine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Section HITACHI 5 Hitachi America, Ltd .• San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 186 April,1992 H8/534 Device EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/534 Microcontroller has an EPROM security feature that can be used by the customer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the device from being read by means other than his own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory Configuration The memory matrix of the H8/534 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64-byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the device is placed into; EPROM programming mode or CPU operation mode. EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This ind i;;ates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. bit=1 bit=O EPROM data can be read (normal) ''00'' data is always read HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5187 H8/534 Device EPROM Security Tech Notes CPU Operating Mode In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bit is a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. bit=1 bit=O EPROM data can be read by CPU (normal) After RESET. the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or internal RAM). Once an instruction is executed outside the internal EPROM memory area. then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM. Programming the Security Bit There exists two EPROM programming modes; normal and. security. The normal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/534 device. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: H8/534 Device 110 Port Pin Programming Mode P60/-IR02lA16 P61/PW1/-IR03/A 17 Normal 1 1 Security 1 0 Again, thisfeature cannot be tested by Hitachi and thus remains unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Section 188 5 HITACHI Hitachi America, Ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 April,1992 H8/536 Device EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/536 Microcontroller has an EPROM security feature that can be used by the customer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the device from being read by means other than his own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole responsibility for its outcome. Memory Configuration The memory matrix of the H8/536 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes of data (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64-byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions / ~E The security function had two different operations depending upon the mode of operation that the device is placed into; EPROM programming mode or CPU operation mode. b 'W en EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit If the security bit is a "I" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. bit=1 bit=O EPROM data can be read (normal) ''00'' data is always read . HITACHI Hitachi America. Ltd.' San Francisco Center' 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819 • (415) 589-8300 Section 5189 H8/536 Device EPRdM Security Tech Notes CPU Operating Mode In the CPU operating modes, the ability of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "I" (unprogrammed state), then the data in the EPROM can always be read by the CPU. If the security bit is a "0" (programmed), then the read state of the EPROM (from the CPU), depends upon where instruction execution is occurring from. bit=l bit=O EPROM data can be read by CPU (normal) After RESET, the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory or internal RAM). Once an instruction is executed outside the internal EPROM memory area, then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM; Programming the Security Bit There exists two EPROM programming modes; normal and security. The normal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8!536 device. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address corresponding to the memory line location. Setting the programming modeis done by setting certain I/O port pins to the following states: H8/536 Device 110 Port Pin Programming Mode P60/-IR02lA16 P61/PW1/-IR03/A 17 Normal 1 1 Security 1 0 Again, thisfeature cannot be tested by Hitachi and thus remains unguaranteed. It is up to the user to determine whether or not to implement the junction of this feature and accept sole responsibility for its outcome. Section HITACHI 5 Hitachi America, Ltd.· San FranciSCO Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 190 March,1992 H8/510 Instruction Timing Tech Notes Application Engineering Carol Jacobson Although the H8/5 lOuses the same instruction set as the rest ofthe H8/500family, thefonnulasused to calculate instruction fetch and execution times are somewhat different. The H8/510 address range is sectioned by the Three-state Area Top Register (AR?T ,) defining two state or three state access field, and Byte Area Top Register (ARBT), defining 16-bit or 8-bitdata bus fields. Locations with address values greater than the ARBTregistervalue are accessed via an 8-bit bus. Locations with address values greater than or equal to the AR3Tvalue are accessedusing three states, two access plus one additional state for slowerperipherials. H8610 (XXX) [XXX) 16 bit 2 state acx::ess 4---8 bit 2 state access FFFF 8 bit 3 state access Access times forinstructions fetched from each area are claculatedusing slightly differentfonnulas. Therefore, it's importantto understand the contents ofthe AR3T& ARBTbefore tt'ying todetennine execution times. Formulas are given in the H8/500 programming manual section 2.6.4. EXAMPLES: 1. Mode 3 Expanded Maximum 8-bitdata bus (ABRT register is ignored) AR3T=H'90 DPRegister=H' AO HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5 191 H8/510 Instruction Timing Tech Notes address opcode operands 00000100 MOV.W Rl,@H'AOOO2O The instruction is fetched via an 8-bitdata bus from a location accessed in two cycles. Word data is moved to a location accessed in three cycles via an 8-bit bus. From section 2.6.4: Total CPU states (cycles)= (Value in Table 2-8) + 21 + J + K T= 6 + 2 (2) + 1 + 3 = 14 clocks 2. Mode4 Expanded Maximum 16-bitdatabus AR3T=H'AO ARBT=H'A2 address opcode OOA00100 MOV.W operands The instruction is fetched via a 16-bit bus from a location accessed in three cycles. Word data is moved to the on-chip register field which is always accessed in three cycles via an 8-bit bus. . From section 2.6.4: . Total CPU states (cycles)= (Value in Table 2-8) + (Value in Table 2-9) + 21 + (J+K)/2 T= 6 +1+2(2) +(1+3)/2= 13 clocks. Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415)589-8300 192 March, 1992 H8/500 Instruction Timing Tech Notes Application Engineering Carol Jacobson Individual instruction execution times for the HS/532, HS/534, HS/536, HS/520 can be calculated using tables 2-S (1 thru 6) and table 2-9 of the HS/500 Series Programming Manual. Formulas for the H8/532, H8/534, H8/536, and H8/520 are given in section 2.6.1. HS/51O Instruction timing is discussed in TN-0039. The main steps used to determine instruction execution timing are: 1. determine the instruction addressing mode, location and operand location. (note: for indirect addressing modes the operand location is the location of the data) 2. from section 2.6.1 determine the which formula to use 3. apply values from Table 2.S & 2.9 to the formula EXAMPLES: 1. Mov.w ;addressing mode: @AA:16 #H'DAFE,@FASO a.1f the instruction and operands reside in on-chip RAM or ROM, the number of CPU clock cycles is the value from the body of Table 2.S plus the value from Table 2.9. Table 2.S # cycles = 9 from Table 2.9 the 'adj. value' = 2 (even address) execution time. =11 CPU clocks total b. If the instruction resides in on-chip memory and the operands are from an on-chip module (peripberal) or off-cbip, the number of CPU clock cycles is the value from the body ofTable 2.S plus 2x the I value plus the adj. value from Table 2.9. Table 2.8 #cycles= 9 + 2(2) plus the 'adj. value' ,2 (even address) = 15 clocks c. If the instruction resides in off-chip memory and the operands are from on-chip, the number of CPU clock cycles is the value from the body of Table 2.8 plus 2 x the J and K values from Table 2.8. r HITACHI Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 5193 88/500 Instruction Timing Tech Notes Table 2.8 #Cycles= 9, K= 3 and J= 3 ; Total execution time = 9 + 2(3 + 3) = 21 clocks d. If the instruction resides in off-chip memory and the operands are from off-chip memory or onchip modules the number of CPU clock cycles is the value from the body of Table 2.8 plus 2 x the I, J and K values from Table 2.8. Table 2.8 #Cycles= 9, 1= 2, K= 3 and J= 3 ; Total execution time = 9 + 2(3 + 3 + 2) = 25 clocks 2. BSR ;addressing mode @aa:16 a. If the instruction resides off-chip and the destination is an off-chip 16-bit location and the branch is taken: Table 2.8 # cycles= 7,1= 2, J+K= 5; Total execution time = 7 + 2(2 + 5) = 21 clocks b. If the instruction resides on-chip and the destination is an on-chip 16-bit location and the branch is taken: Table 2.8 #Cycle= 7, Frpm Table 2.9 'adj. value'= 0 (even address); Total execution time: 7 + 0 =7 clocks Section HITACHI 5 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300 194 June, 1991 H8/532 Microcontroller EPROM Security Tech Notes Application Engineering Tom Hampton EPROM Security The H8/532 Microcontroller has an EPROM security feature that can be used by the application programmer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on-chip EPROM of the H8/532 from being read by means other than his or her own program. This feature cannot be tested by Hitachi and, due to this, is unguaranteed. It is up to the user to determine whether or not to implement the function of this feature and accept sole , responsibility for its outcome. Memory Configuration The memory matrix of the H8/532 Microcontroller is configured as a dual matrix, one with even addresses and the other with odd addresses. The configuration of each matrix appears as lines of memory 32 bytes wide (32 x 8, 256 bits). This configuration allows an individual memory line to consist of 64 bytes ofdata (including both even and odd addresses). Each memory line has 1 security bit thus allowing every 64 byte segment to have the option of the security feature. The address of this security bit is the same as the starting address for the memory line. Security Functions The security function had two different operations depending upon the mode of operation that the H8/532 device is placed into, EPROM programming mode or CPU operation mode. EPROM Programming Mode In the EPROM programming mode, the ability of the EPROM programmer to read the EPROM contents is limited by the state of the security bit. If the security bit is a "1" (unprogrammed state), then the data in the EPROM can always be read. If the security bit is a "0" (programmed), then any read operation to the EPROM will result in a "00" being read. This indicates that once the security bit is programmed, the user will be unable to verify the contents of the EPROM. security bit security bit I 1 0 EPROM data can be read (normal) "00" data is always read HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 Section 5195 Tech Notes H8/532 Microcontroller EPROM Security CPU Operating Modes In the CPU operating modes, the abil~ty of any device to read the EPROM contents is limited by the state of the security bit. If the security bit is a "I " (unprogriunmed state), then the data in the EPROM can always be read by the CPU. Ifthe security bitis a "0" (programmed), then the read state of the EPROM (from the CPU). depends upon where instruction execution is occurring from. security bit security bit 1 0 EPROM data can be read by CPU (normal) After RESET. the CPU can read EPROM data until it executes an instruction outside the internal EPROM area (either external memory Or internal RAM). Once an instruction is executed outside the internal EPROM memory area. then the EPROM becomes disabled and cannot be accessed any further. This prohibits an external program from being able to "dump" the contents of the on-chip EPROM. Programming tbe Security Bit There exists two EPROM programming mode; Normal and Security. The normal EPROM programming mode is used to program the code/data area of the on-chip EPROM memory for the H8/532. The "security" programming mode is used to program the security bits of the EPROM's memory area. The security function is then implemented by programming a "0" into the address Corresponding to the memory line location. Setting the programming mode is done by setting certain I/O port pins to the following states: H8I532 VO Port Pin Progranvning Mode P60 P6l Normal 1 1 Security 1 0 Agaill, thisfeature call1lot be tested by Hitachialld thus remaillsullguartmteed.lt is up to the user to determille whether or 1I0t to implemellt the /unctioll 01 this leature alld accept sole respollsibility lor its outcome. Section 196 5 HITACHI Hitachi America,ltd." San FranciSCO Center" 2000 Sierra Point Pkwy." Brisbane, CA 94005-1819 " (415) 589-8300 Section 6 Memory HITACHI@ 2 SectIon HITACHI 8 Hitachi America, ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 June, 1992 Word-wide DRAMs Tech Notes Application Engineering Gomer A. Serang Introduction Hitachi has introduced an assortment ofword-wide4Meg DRAMs. This Briefwill describe the main purpose and application of word wide devices. Table 1.0 below lists the various x 16 offerings. Part Number Refresh Rate Control Vee 1ec1 Current Consumption HM514260-8 512 cycles/ 8ms 2CAS 5.0V +/-10 % 150mA HM514270-8 512 cycles/ 8ms 2WE 5.0V +/-10% 150mA HMS14170-8 1024 cycles/ 16ms 2WE 5.0V +/-10% 120mA HMSIV4160-8 1024 cycles/ 16ms 2 CAS 3.3V +/- 10% 105mA Table 1.0 Hitachi I s 256kx16 parts list. Applications The 256kx16 device can be used either to upgrade systems that are based on the older generation. 256kx4 DRAMs or to give better performance to new systems thatimplementword wide busses. The distinction is made when choosing one of the two available refresh rates. The 512cycles ISms is a directreplacementforoldergeneration 256kx4 DRAMs. This implies that the DRAM controller does not have to be redesigned. While the 1024 cycles/16ms part consumes less current but will require HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 6 3 Word-wide DRAMs TechNotes ' anew DRAM controller, and hence is targetedfornew systems. The current reduction is due to the fact that fewer sense amplifiers are used and hence the overall current consumption is decreased. Another system design variable is memory bank selection. Some designers prefer to use common /RAS while the/CAS signal serves as a bank select. Hitachi offers the 2CAS signal option precisely forthose systems. Hitachi also offers 2WE parts which are best used in graphics applications, since it offers easier control of upper and lower bytes. In particular, thex16 DRAMpartis used as az-buffer while expensive VRAMs would be used as the main graphics buffer. Lasdy, the obvious advantages ofdesigning with 256kx16 devices insteadof256kx4 parts should not be overlooked; less board space is used, memory cost is reduced, and the reliability is higher. Consequendy,anoldermemory system based on bank selection of256kx4 DRAMs and their8ms refresh requirement can be upgraded with either the HM514260 or HM514270. Word wide write cycles for the multiple/WEand multiple/CAS type devices can be confusing. To preventconfusion,itis important to understand that address and data is latched internally onawordwide basis at the fall of!RAS and /WE or /CAS regardless of whether the write cycle is a byte write orawordwrite. This means thatthex16device does NOT permit writing upper and then lower bytes in sequence within the same write cycle. More specifically, early write cycles cannot be mixed with late write cycles in the same cycle. On the other hand, a word can be written with the fall of both upperand lower byte control signals at the same time, and one byte can be written with the fall of either the upper or lower control select signals. In addition, fast page mode byte read cycles ~permittedas long as there is a minimum tCP time separation between thefirst/UCAS being de-asserted and the s~ondL-CAS becoming asserted as shown in Figure 1.0 RAS UCAS ~~------------~~ LCAS Figure 1.0 Page mode cycle 4 'Section HITACHI 0 Hitachi America, ltd.' San Francisco Center' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300 March, 1992 Mask History of HN58C256 Tech Notes Application Engineering Oomer A. Serang The original HN58C256, 256k EEPROM was introduced in 1989 as anRO mask. Since that time the device has gone through 2 mask revisions and this Brief will summmarize the modifications. The frrstrevision was done in late 1990 to counter potential data destruction due to noise on ICE or!WEwhileVcc was powering up or down. Normal program mode dictates that/CE and !WEbe low while Vcc and/OE are high. However, while powering on and off unknown levels on/CE or !WE can inadvertently cause erroneous data to be written. Figure 1.0 below, shows the conditions that may lead to an inadvertent program cycle. Vcc ICE _---'4 Figure 1.0 Conditions that may cause incorrect write. Consequently. if a user could guarantee that!WEand/CE are high when Vcc was stabilizing then there could be no possibility of an inadvertent write occuring. Nonetheless, Hitachi decided to improve the chip by decreasing the programming voltage sensitivity level so that any glitches that occurred on/CEor!WE while Vcc was stabilizing were locked out. From a specification standpoint, the only parameter that changed due to the Rl mask revision was an increase in the Icc 1standby current. from 20lJAmaximum to 501JA typical and 200lJAmaximum. Other than the Icc 1 change, all other AC and DC parameters remained the same. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 6 5 Mask History of HN58C256 Tech Notes The second mask revision. called appropriately enoughR2. was implemented in the October 1991 timeframe. The R2revision fixed a rarely occuring problem that caused random address locations to change to FFh. The culprit was found to be a combination of residual voltages coupled with specific rise times on Vcc. The details are best described by looking at Figure 2.0 below. tRISE = 0.5 to 50ms !<- ->I vcc~ pin GND - : - - - - - - - - - - 0.1 to 0.3 volt residual I voltage Figure 2.0 Conditions that may cause data to change to FFh. If aresidual voltage in the 0.1 to 0.3 volt range existed on the Vcc pin it would increase the internal capacitance coupling on the IRESETpin. This prevented the reset timer circuits from functioning properly. In fact. the internal reset signal would abort prematurely which briefly activated the write and erase circuits. The presently availableR2 mask has countered the aformentionedpeculiarityand results in a highly reliable device. 6 Section HITACHI 6 Hitachi America. Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819 .(415) 589-8300 February, 1992 1M Flash Software Modification Tech Notes Application Engineering Oomer A. Serang Intel presently offers customers some general 1M Flash code for use in 10Mhz 80186 based systems. This Note will point out the modifications that need to be made to Intel's code so itcan support Hitachi's 1M Flash device. The major differences between Hitachi and Intel are shown in Table 1.0 Parameter Intel Hitachi Write operation duration lOpsec min 25psec max 25ps min Erase operation duration 9.5ms min lO.5ms max 9msmin 11ms max Multiple chip erase After erase verification of any chip, send reset command (FFH), until all chips have erased. After erase verification of any chip, send verify command (AOH), until all chips have erased. Multiple chip programming After programming completion of any chip, send reset command (FFH) while waiting for all chips to complete programming. After programming verification of any chip, program and verify chip again hut sendFFHas program data. Repeat, until all chips have completed programming. Table 1.0 Major differences between Intel and Hitachi 1M Flash. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 Section 6 7 1M Flash Software Modification Tech Notes Table 1.0indicates that the programming Pulse Width and Erase Time duration for Hitachi's .device is different from Intel's. However, if minor code modifications of the original Intel code are done, a Hitachi device can plug into an Intel socket Forexample, in Intel generated code the following instructions are recommended for Programming Pulse Generation in a 10Mhz 80186: % '" define (WAIT I Ous) push ex ; save old counter register contents mov ex, 6 ; put 6 into counter register loop S ;oecrementuntil 0 popcx ;restore old counter contents 1becode above completes execution in 10us by counting down from 6, after which a control pulse is generated. To generate a 2Suspulse width,the number ofT states foreachinstruction is determined and then the appropriate counter value to generate a 25us execution time is calculated. In this case the value required is 17, so I movcx,6 changes to movcx,I7 The tinalcode would look like: %"'define(WAIT2Sus) push ex movcx,I7 loopS popcx Lastly, the erase code supplied by Intel generates a tOms wait and is as follows: %"'detine(WAlT IOms) pushcx movcx,10 loop%WIOms popcx Since the IOms meets Hitachi '·s erase time specification as well, there is no need to modify any ofthe above code. Section 8. HITACHI Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589·8300 January, 1992 1M to 4M Flash Memory Upgrade Tech Notes Application Engineering Oomer A. Serang Introduction It seems like it was only yesterday when the Hitachi 1M Flash device was introduced and promoted. The differences between our 1M device and a rival's was repeated and re-iterated often. Hence, it is probably very surprising to already begin dicussions on the 4M Flash device. Nonetheless, the 4Meg is here now and the aspects of replacing the 1M device is the topic of this Note. 4MFeatures * Automatic chip and BLOCK erase * Status polling '. * Command register based control * Automatic and Manual Programming 1M to 4M Upgrade A lot of design effort went into making the 4M Flash as compatible as possible with the 1M Flash device. Consequently, it is no coincidence that the 4M Flash package size is identical to the 1M Flash package size. In addition, the pins between the 1M and 4M devices are similar except for the fact that the 4M Flash has, of course, 2 additional address pins and more importantly no /WE pin. The figure below shows the pin-out difference. 31 t - - Al8 :I)-Al7 Figure 1.0 Difference in pin configurations between 1M and 4M Hash HITACHI Hitachi America, Ltd,· San Francisco Genter· 2000 Sierra Point Pkwy,· Brisbane, GA 94005-1819 • (415) 589-8300 Section 6 9 Tech Notes 1M to 4M Flash Memory Upgrade Consequently, in the 1M device an address is latched when both the/WE andiCE golow while data is latched when either /WE or ICE goes high. In comparison, the 4M device has address and data latching when ICE goes high. A lot of additional expense and effort can be avoided if customers. design in for the 4M while they are designing in the 1M Flash. The customer should be told that if their 1M system has a trace that selVes as either an address line or /WE line, depending upon a jumper position, then the 4M Flash will fit easily into the socket when an upgrade is required. The other address line required for the 4M can be laid out as a trace going to the NC pin of the 1M. As far as the logic is concerned, the 4M Flash has easier timing in many cases because there is no longer a need to toggle a /WE pin as was the case with the 1M Flash device. In addition, the block select operation is simply controlled by A 14-A 18 so that incoporating the block select feature consists of only applying a new address and latching it in by the rising edge of ICE. In fact, block accesses can be implemented by "false" CPU write cycles. They are labeled as "fruse" write cycles because data is not actually written to the device even though the write cycle timing is implemented. An important restriction on the,false write cycles is to make sure that the data on the bus is anything EXCEPT fFh when ICE rises. Putting FFh on the data bus will reset the device since FFh is the reset command. When all the items are taken into account a pre-liminary analysis of the 1M to 4M upgrade yields the following steps: 1) Run an address line trace into the NC of the 1M. When using the 4M the trace will serve as A17. 2) Place a jumper on the board so that the /WE for the 1M can change to A18 for the 4Meg. 3) Modify PAL equations and incorporate false write cycles during block accesses and make sure the data on the bus is 1\ot FFh. As a whole, the above steps indicate that although the 4M upgrade is not trivial, the upgrade is not excessively complicated either. 10 Section HITACHI 6 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300 December, 1991 Low Voltage RAMs Tech Notes Application Engineering Oomer A. Serang In the past, speed and memory organization were critical parameters in memory system designs. The popularity of notebook computers has now made power consumption of equal if not more importance. A previous note discussed extended refresh cycles as a means to decrease power consumption. This Note will introduce Hitachi's wide variety oflow voltage RAM memory products. Config. Operating Voltage Access Time 4M 512kx8 256kx16 256kx18 2.7 to 3.6 70/80/100 PSRAM 4M 5l2kx8 2.7 to 3.6 120/150 SRAM 1M 128kx8 2.7 to 5.5 150 Family Density DRAM Table 1.0 Hitachi's low voltage RAMs All of the 4M low voltage DRAMs are manufactured using the same 0.5 pm process that is used to manufacture 16Meg DRAMs. Consequently, the low voltage 4M DRAMs are NOT just high voltage parts that are screened for low voltage operation. In fact, even the low voltage 4MPSRAM is NOT a 5.0 volt PSRAM screened for low voltage operation, but is instead a re-design of the standard part. As can be imagined, low voltage operation introduces a gamut of potential problems like decreased noise margin and potential increase in soft errors. Noise margin aside, soft errors are most dependent on cycle times and power supply voltages. For a given DRAM cell, decreasing the power supply voltage increases the SER. An effective counter against the SER degradation is to increase the cell capacitance during the chip design stage or to use better dielectrics. Although no reliability data is yet available on the low voltage 4M DRAMs one calp assume the SER to be comparable to standard voltage parts. HITACHI Hitachi America, Ltd." San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Section 6 11 November, 1991 Extended Refresh DRAMs Tech Notes Application Engineering Oomer A. Serang Introduction The explosive growth of notebook computers has not only elevated computing convenience to an unprecedented level but it has also stimulated mainstream suppliers to offer specialized parts for the portable market. For example, 2W' hard disk drives, super-twist color LCDs and miniaturized keyboards are direcr consequences of the portable computer revolution. One of the most important objectives of notebook manufacturers is to minimize system power consumption. With reduced system power consumption the end-user can be assured oflonger battery life and maximum operating time, thereby making the portable that much more appealing. Consequently, vendors who want to supply the notebook market are aggressively studying and implementing methods to reduce power consumption. One particularly power hungry aspect of computers is their memory systems. Typical memory systems can consume as much as 30% of the total system power. In particular, the additional overhead of DRAM refresh cycles not only uses precious active bandwidth but also consumes scarce battery current. With this in mind, battery life can be extended if the frequency of memory refresh cycles were decreased. That was the motivating reason to develop and offer extended refresh DRAMs. Extended refresh DRAMs are DRAMs that have dramatically relaxed refresh requirements. Since cycle times and power consumption are directly related it is possible to reduce power consumption by decreasing refresh frequency. In fact, when compared to standard DRAMs, the extended refresh DRAMs can go as much as 16 times longer without a refresh cycle. Another attraction of extended refresh DRAMs is that Hitachi doesn't consider them to be a low priority product in the memory chain but instead assigns them the same important status as standard 4Meg DRAM products. When low DRAM data retention currents are combined with the high volume manufacturing assurance of Hitachi, then advanced notebook computers, hand-held instruments and other power sensitive applications can become a reality. Table 1 compares battery life between standard and extended refresh DRAMs. Although no system is going to be in data-retention mode 100% of the time the point to be made is that a SL based system can have a far longer battery life than a system based on standard 4Meg parts. 12 Section HITACHI 6 Hitachi America, Ltd.· San Francisco Center· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Extended Refresh DRAMs Part Number Tech Notes Active Current (80 nsec part) Data Retention Current Battery Life (1 pc., 500 mAh) HM514100/400ASL (1 K cyclesl256 msec) 90mA 100 IJA (typ.) 208 days (typ.) HM514100/400A (1 K cyclesl16 msec) 90mA 1 mA (typ.) 21 days (typ.) Table 1: Standard vs. Extended Refresh Battery Life Trench vs STC Although standard 4Meg DRAMs are offered by a variety of suppliers as well as a variety of countries the same cannot be said of extended refresh DRAMs. Only a handful of vendors have processes and chip designs superior enough to guarantee extended refresh times. When a DRAM isn't being accessed or refreshed the amount of time required for the stored charge to dissipate is a function of the dielectric material, cell to cell isolation, parasitic losses and even the cell structure. For example, an analysis of first generation trench cells revealed that they could not meet extended refresh requirements because of leakage between trenches. Since the storage node is directly in the silicon substrate, stress and crystallographic defects were manifested as leakage current. Consequently, the trench cell insulation characteristics was hnproved upon by depositing an additional SiOzlayer around each trench and then staggering, rather than lining up in a single file, the cells, to get less cell to cell interaction as well as increased cell density. The improved cell leakage characteristics came at the expense of additional fabrication steps and increased production cost of the trench device. Even Hitachi's first generation stacked capacitor architecture could not meet the stringent extended refresh specifications. However, Hitachi's second generation" A" mask stacked capacitor architecture yielded minimum leakage specifications primarily because the smaller junction area reduced the rate of leakage current. Another advantage of extended refresh parts is that they aren't manufactured on special lines or under special circumstances. Hence