1992_Hitachi_LCD_Controller_Driver_LSI_Data_Book 1992 Hitachi LCD Controller Driver LSI Data Book
User Manual: 1992_Hitachi_LCD_Controller_Driver_LSI_Data_Book
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LCD CONTROLLERIDRIVER LSI
DATA BOOK
HITACHI®
M24T013
When using this document, keep the following in mind:
1. This document may, wholly or panially, be subject to change without
notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in
any fonn, the'whole or part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this documenL
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
S. No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLlCATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLlCAnONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLlCAnONS.
MUch 1992
C>Copyright 1992, Hitachi America, LId.
Printed in U.S.A.
INDEX
LCD Controller/Driver LSI Data Book
General Information I
General Information II
DATA SHEETS
General Type LCD Driver
Character Display LCD Controller/Driver
Graphic Display LCD Controller/Driver
Segment Type LCD Controller Driver
Special Application Driver
New Product Information
HITACHI
CONTENTS
LCD CONTROLLERIDRIVER LSI DATA BOOK
I SECTION 1
I General Information I
• GENERAL INFORMATION ....................................................................................................................................................
7
• Quick Reference Guide ..... ... ...... ..... ...... ....... ... ....... ....... .... ...... ..... ..... ....... ... ....... ........ ....... ... ........ ...... .... .... ....... ... ..... ..........
9
• Type Number Order ............................................................................................................................................................
12
• Selection Guide. ........... ... ......... ....... ........ ..... ........................... .......... ..... .......... .......... ..... ........ ........... ......... .... ....... .......... ...
13
• Differences Between Products ............................................................................................................................................
16
I General Information II
SECTION 2
• TCP (Tape Carrier Package) ................. ..... ... ...... .... .... ... .... ... ......... .... ..... ........ .... ..... ..... ... ..... ... ........... ....... ........ ... ....... ... ....
24
• Package Information............................................................................................................................................................
44
• Reliability and Quality Assurance.......................................................................................................................................
49
• Reliability Test Data of LCD Drivers .................................................................................................................................
56
• Flat Plastic Package (QFP) Mounting Methods ..................................................................................................................
60
• Liquid Crystal Driving Methods .........................................................................................................................................
63
SECTION 3
I General Type LCD Driver
• DATA SHl:E:rs.........................................................................................................................................................................
75
HD44 IOOH
LCD Driver with 40-Chimnel Outputs.......................................................................
77
HD66 IOOF
LCD Driver with 80-Channel Outputs.......................................................................
87
SECTION 4
I Character Display LCD Controller/Display
HD43I 60AH
Controller with Built-in Character Generator ............................................................ 100
HD44780. HD44780A (LCD-II) Dot Matrix Liquid Crystal Display Controller & Driver ........................................... 114
HD66780 (LCD-IIA)
Dot Matrix Liquid Crystal Display Controller & Driver ........................................... 167
'--SE_C_T_I_O_N_S----li Graphic Display LCD Controller/Driver
HD44I 02CH
Dot Matrix Liquid Crystal Graphic Display Column Driver..................................... 216
HD44103CH
Dot Matrix Liquid Crystal Graphic Display Common Driver................................... 239
HD44105H
Dot Matrix Liquid Crystal Graphic Display Common Driver ................................... 247
HD6II00A
LCD Driver with 80-Channel Output ........................................................................ 256
HD61102
Dot Matrix Liquid Crystal Graphic Display Column Driver..................................... 268
HD61103A
Dot Matrix Liquid Crystal Graphic Display Common Driver ................................... 296
HD6II04. HD61104A
Dot Matrix Liquid Crystal Graphic Display Column Driver..................................... 320
HD61105. HD61105A
Dot Matrix Liquid Crystal Graphic Display Common Driver ................................... 332
CONTENTS (Continued)
L-S_E_C_T_IO_N_5----11 (Continued)
HD6 I 200
LCD Driver with 80-Channel Output ...........................................................•............ 350
HD6 I 202
Dot Matrix Liquid Crystal Graphic Display Column Driver ...·.................................. 363
HD61203.
Dot Matrix Liquid Crystal Graphic Display Common Driver................................... 394
HD61830
LCTC (LCD Timing Controller) ............................................................................... 418
HD61830B
LCTC (LCD Timing Controller) ............................................................................... 443
HD63645F/HD64645F
LCD Timing Controller (LCTC) ............................................................................... 466
HD64646FS
LCD Timing Controller (LCTC) ............................................................................... 506
HD66J06F
LCD Driver for High Voltage .................................................................................... 516
HD66J07T
LCD Driver for High Voltage ..................................................................................... 531
HD66J08T
Ram-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics .. 551
HD66840F
LCD Video Interface Controller (LVIC) ................................................................... 604
HD6684IF
LCD Video Interface Controller II (LVIC-II) ........................................................... 652
HD66850F
Color LCD Interface Engine (CLINE) ...................................................................... 708
SECTION 6
I Segment Type LCD Controller/Driver
HD6 I 602/HD61 603
Segment Type LCD Driver .............................................................. :......................... 778
HD6 1604/HD6 I 605
Segment Type LCD Driver ........................................................................................ 807
SECTION 7
I Special Application Drivers
HD66300T
Horizontal Driver for TFT -Type LCD Color TV ...................... :............................... 833
HD663 I OT
TFT-Type LCD Driver for VDT ................................................................................ 894
SECTION 8
New Product Information
HD66 I lOT
Column Driver ........................................................................................................... 916
HD66204
Dot Matrix Liquid Crystal Graphic Display Column Driver
with 80-Channel Outputs ............................................................ :.,............................
Dot Matrix Liquid Crystal Grapnic Display Column Driver
with 80-Channel·Outputs ...........................................................................................
Micro-TAB 80-Channel Column Driver in Micro-TCP ............................................
Dot Matrix Liquid Crystal Display Controller and Driver ........................................
HD66205
HD66214T/HD662l4TL
HD66702LCD-lI/E20
931
945
959
975
• HITACHI SALES OFFICES .................................................................................................................................................... 1024
LCD CONTROLLERIDRIVER LSI DATA BOOK
Section One
General Information I
• Quick Reference Guide
• 1YPe Number Order
• Selection Guide
• Difference Between Products
HITACHI
Quick Reference Guide
Type
Column Driver
Type Number
HD44100H HD418100F HD81tOOA H081200
5
5
5
5
Power supply for
internal circuits (V)
Power supply for
LCD Drive Circuit (V)
11
Power
DiSSIpation (mW)
Operating
Temperature (C)
HD81104
5
HD81104A HD88108F HD418107T
5
5
5
6
17
17
26
28
37
37
5
5
5
10
10
15
25
-20 to +75" -20 to +75't -20 to +75't -20 to +75 -2010+75 -2010+75 -2010+75 -2010+75
ROM (bit)
Memory
RAM (bit)
LCD Driver
Common
'20
Column
40 (20)
80
80
160
80
80
80
80
80
160
2.5
2.5
3.5
3.5
6
8
Instruction Set
Operation
Frequency (MHz)
0.4
Duty
Static-l 132 Static-l 116 Static-l/1oo 1/32-11128 1/64-1/2001/64-1/2401/100-1/4801/100-1/480
Package
FP-60
FP-l00
FP-l00
FP-l00
FP~I00
FP-l00
FP-l00
192pin
rcp
TFP-l00
Column Driver (TFT)
Type
Column Driver (RAM)
Type Number
Power supply for
internal circuits (V)
Power supply for
LCD Drive Circuit (VI
Power
Dissipation (mW)
Operating
Temperature rC)
HD441D2CH
5
HD81102
5
HD81202
5
HD88108T
5
HD86300T
5
HD88310T
5
11
15.5
17
15
15
23
5
5
5
5
160
100
-20 to +75
-20 to +75
-20 to +75
-20 to +75
-20 to +75
-20 to +75. 2
(-20 to +65)
200xB
512xS
512xS
165x65
160
,64
7
0.4
64
7
0.4
0-65
100-165
7
4
120
50
6
0.2S
4.S
12/15
1/S.1/12.
1/16.1/24.
1/32
Stetic-l/64
1/4S.1/64.
1/96.1/12S
FP-SO
FP-l00
FP-l00
1/32.1/34.
1/36.1/4S.
1/50.1/64.
1/66
20Spin TCP
156pin TCP
236pin TCP
ROM (bit)
RAM (bit)
Memory
LCD Driver
Common
Column
Instruction Set
Operation
Frequency (MHz)
Duty
Package
* 1 -40 to +85'C (Special request). Please contact Hitachi agents.
*2 -20 to +75'C in 12 MHz Version, -20 to +65'C in 15 MHz Version.
* 3 Under development
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
9
Quick Reference Guide
Type
Sagnwn,t Display
Type Number
Power supply for
internal circuits (V)
Power supply for
LCD Drive Circuit (V)
Power
Dissipation (mW)
Operating
Temperature rC)
Memory
ROM (bit)
RAM (bit)
3 to 5
HD61603
3 to 5
HD61604
3 to 5
HD61605
3 to 5
5
5
5
5
0.5
0.5
0.5
0.5
-20 to +75. 1
-20 to +75. 1
-20 to +75. 1
-20 to +75. 1
204
64
204
64
4
51
64
51
64
Instruction Set
4
4
4
4
Operation
Frequency (MHz)
0.52
0.52
0.52
0.52
Duty
Static. 1/2.
1/3.1/4
FP-80.
FP-80A
TFP-80· 2
Static
Static.ll2.
1/3.1/4
FP-80
Static
LCD Driver
Common
Column
Package
HD61602
4
FP-80
* 1 -40 to +85°C (Special request).
* 2 Under development
FP-80
Please contact Hitachi agents.
Type
Common Driver
Type Number
Power supply for
internal circuits (V)
Power supply for
LCD Drive Circuit (V)
Power
Dissipation (mW)
Operating
Temperature ( °C)
ROM (bit)
Memory
RAM (bit)
HD44103CH HD44105H HD61103A HD61203
5
5
5
5
HD61105
5
HD61105A
5
11
11
17
17
26
28
4.4
4.4
5
5
5
5
LCD Driver
20
Common
-20 to +75 -20 to +75 -20 to +75 -20 to +75 -20 to +75 -20 to +75
32
64
64
80
80
2.5
2.5
0.1
0.1
Column
Instruction Set
Operation
Frequency (MHz)
Duty
Package
1/8.1/12. 1/8.1/12. Static-l/10.
1/16.1/24.1/32.1/48 1/64
1/32
FP-60
FP-60
FP-l00
1/32-1/1281/64-1/2001/64-1/240
FP-l00
FP-l00
FP-l00
TFP-l00
* 1 -40 to +85°C (Special request). Please contact Hitachi agents.
* 2 Under development
HITACHI
10
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Quick Reference Guide
GI'IIPhIc Dt.pIay
a-.ctar Dllplay
Type
Type NUIIIbM'
Power supply for
internal circuita (V)
Power supply for
LCD Drive Circuit (V)
Power
Dissipation (mW)
Operating
Temperature ('C)
ROM (bit)
Memory
RAM (bit)
LCD Driver
HD44780
HD43180AH (LCD-It)
HD88780
(LCD-itA)
HD81830
5
5
5
5
HD83846F
HD8484IF HD88840F
HD84848FS HD68841F HD888IIO
HD81830B LCTC
LYIC
CLINE
5
5
5
5
11
5
2
2
30
50
10
250
500
-20 to +75 -2010 +75" -2010 +75
-20 to +75 -2010 +75" -20 to +75 "':20 to +75 -20 to +75
6420
7360
80x8
7200
80x8,
64x8
12000
80x8,
64x8
Common
16
16
Column
40
40
Instruction Set
50
7360
9762
11
6
0.25/0.375 0.25
11
12
12
15
16/24
63
0.25
1.1
2.4
10
30
32
Duty
1/8,1/12,
1/16
1/8,1/11,
1/16
1/8,1/11,
1/16
Static
1/128
Static
1/128
Static
1/512
Static
1/1024
1/480
Package
FP-54
FP-80,
FP-80A
TFP-80,2
FP-80A
FP-80B
FP-60
FP-60
FP-80,
FP-80B
FP-l00A
FP-136
Operation
Frequency (MHz)
* 1 -40 to +85'C (Special request). Please contact Hitachi agents.
*2 Under development
HITACHI
HitachLAmerica, Ltd.' Hitachi Plaza ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
11
Type Number Order
Type
Function
HD43160AH
LCD Controller
HD44100H
LCD Driver with 40 Channel Output
HD44102CH
LCD Column Driver with 50 Channel Output
216
HD44103CH
LCD Common Driver with 20 Channel Output
239
HD44105H
LCD Common Driver with 32 Channel Output
247
HD44780 LCD-II
LCD Controller/Driver
114
HD6110A
LCD Column Driver with 80 Channel Output
256
HD61102
LCD Column Driver with 64 Channel Output
268
HD61103A
LCD Common Driver with 64 Channel Output
296
HD61104
LCD Column Driver with 80 Channel Output
320
Reference Page
100
77
HD61104A
LCD Column Driver with 80 Channel Output
320
HD61105
LCD Common Driver with 80 Channel Output
332
HD61105A
LCD Common Driver with 80 Channel Output
332
HD61200
LCD Column Driver with 80 Channel Output
350
HD61202
LCD Column Driver with 64 Channel Output
363
HD61203
LCD Common Driver with 64 Channel Output
394
HD61602
Segment Display Type LCD Driver
778
HD61603
Segment Display Type LCD Driver
778
HD61604
Segment Display Type LCD Driver
807
HD61605
Segment Display Type LCD Driver
807
HD61830 LCTC
LCD Timing Controller
413
HD61830B LCTC
LCD Timing Controller
443
HD63645F LCTC
LCD Timing Controller
466
HD64645F LCTC
LCD Timing Controller
466
HD64646FS LCTC
LCD Timing Controller
506
HD66100F
LCD Driver with 80 Channel Output
HD66106F
LCD Column/Common Driver with 80 Channel Output
516
HD66107T
LCD Column/Common Driver with 160 Channel Output
531
HD66108T
Graphic LCD Controller/Driver
551
HD66110T
Column Driver
916
HD66204
LCD Column Driver with 80 Channel Output
931
87
HD66205
LCD Common Driver with 80 Channel Output
945
HD66214T
Micro-TAB 80-Channel Column Driver
959
HD66214TL
Micro-TAB SO-Channel Column Driver
959
HD66300T
TFT Alalog Column Driver
833
HD66310T
TFT Digital Column Driver
894
HD66702 LCD-II
Dot Matrix Liquid Crystal Display Controller and Driver
975
HD66780 LCD-IIA
LCD Controller/Driver
167
HD66840F LVIC
LCD Video Interface Controller
604
HD66841F LVIC-II
LCD Video Interface Controller
652
HD66850F CLINE
Color LCD Interface Engine
708
HITACHI
12
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
Driver Output
160
I
I
::I:
I.
I
~
CD
~.
Controll~r/Dri;';]
HD61604
HD61602
HD44780
H
(LCD-II)
1
1
HD66780
(LCD-II A)
!:;
~
•
::I:
I
~
2:
3!
·
I
fJ)
(ij"
;) ~
? d
a ~
I
1/480
1/200
Duty 1/240
1/128
1/64
1/100
I
I
1/32
1/16
1
! ~ ::I
~
eo.
HD61202
1
I
[~mn
Driver
(Built in RAM)
HD44102H
20
'"o
:3
I
HD61102
40
&l
i
80
HD61603+
HD61605
HD44103CH
HD44105CH
_
I
1/8
I
Static
I
I
I
1/8
1/16
1/32
1/64
I
1/128
1/100
1/200
1/480
Duty 1/240
G)
HD44100H
c
6:
CD
~.
liS
::I
I HD61103A
§;
§
':t.
~
<0
~
.£!
U1
!
c.>
:3
......
c.>
I HD61203
HD66205/
60
I
I HD66100F
I
HD61105
HD611~,,0~5A:.!I~=====I--t
1-
80
HD66106F
1
IHD61100A
HD61200
HD611041
HD66204/HD61104A 1
1
HD66106F
1
HD66107T
Common Driver
160
Driver Output
-I.
=
32
c:>
5D
en
CD
o
20
~40
•
I
[Col~mn Driv';-j
I
HD66107T
Selection Guide
Hitachi LCD Driver System
s-
Rar-Type
.... (mul
Figure
TFT
(800x3) x 520
dots
Full Color
System
LIneup
HD66310T(Drain)
HD61105(Gate)
HD66205(Gata)
ApplIcatIon
Personal Computer
Terminal Workatation
Navigation System
STN
Full Color
System
(720x 3) x 480
dots
HD66850F(Controller) Personal ComHD66107T
puter
(Column, Common)
Terminal
Work-station
Color
LCD-TV
System
720 x 480 dots
HD66300T(Drain)
HD61105(Gate)
HD66205(Gate)
LCD-TV
Portable Video
Video to
LCD
converter
720x512 dots
Personal Computer, Terminal,
OHP
Display
System
for CRT
Compatible
640 x 400 dots
Graphic
Display
System
Character
80X16
Graphic
480x 128 dots
HD66840F, HD66841F
HD66106F(Driver)
HD661 07T(Driver),
HD61104(Column)/
61105(Common)
HD66204(Column)/
66205(Common)
HD63645F/64645F/
64646FS(Oontroller)
HD61104(Column)/
61105(Common)
HD66204(Column)/
66205(Common)
HD66106F(Driver)
HD611 OOA(Column),
HD61830B(Controiler)
HD61200(Column)
HD61103A(Common),
HD61203(Common)
Graphic
Display
System
(Bitmap)
480 x 128 dots
HD44102CH(CoIumn)/
61102(Column)
HD44103CH(Common)
HD61202(CoIumn)
HD44105H(Common)/
61103A(Common)
HD61203(Common)
HD66108T
(Column/Common)
HD44780(LCD- II )
(Controller/Driver)
HD66780(LCD-1I A)
(Controller/Driver)
HD44100H(CoIumn)
HD66100F(Columnt
Laptop Computer,
Handy Wordprocassor, Toy
HD61602
(Controller/Driver)
HD61604
(Controller/Driver)
HD61603
(Controller/Driver)
HD61606
(Controller/Driver)
ECR, MeeeurementSystem,
Telephone
Industrial MeaIUramentSystem
Character
Display
System
Sagment
Display
System
8-l
HD44'ao
I~
I
HDO,I02,H08''''
lCofttI'OIIIr.lDriver1
40 Charae-
7O"VO
~
I ters
x2 Columns
80 Charac-
HD86100F1
HD44100H
ters
ICoIuINnDri¥lrl
xl Column
~
u
25 Digits
xl Column
Personal Computer, Wordprocessor, Terminal
laptop Computer,
Facsimile, Telex,
Copy machine
Electrical Typewriter, Multifunction Telephona,
Handy Terminal
HITACHI
14
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819- (415) 589-8300
Selection Guide
Application
Character and Graphic Display
1 character=7 X 8 dot (15 X 7 dot
Character
Line
8
16
I
+ cursor)
20
24
I
32
40
I
I
Over 80
1
HD66100F
2
3
HD44100H
4
6 to 8
r
12 to 15
HD61200 (Column) + HD61203 (Common)
16 to 25
HD61104 (Column) + HD61105 (Common)
HD66204 (Column) + HD66205 (Common)
HD66106F, HD66107T
26 to 50
Graphic Display
Horizontal
Vertical
48
I
96
I
120
I
180
I
240
I
480
Over 640
16
32
HD61202 (Column) + HD61203 (Common)
48
64
128
400
HD61104 (Column) + HD61105 (Common)
HD66204 (Column) + HD66205 (Common)
HD66106F, HD66107T
Over 400
Note: Applications on this page are only examples, and this combination of devices is not the best.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
15
Differences Between Products
1. HD66100F and HD44100H
3 to 6
Static to 1/16
100 pin plastic QFP
HD44100H
20x2
4.5 to 11
Static to 1/32
60 pin plastic QFP
HD61100A
HD61200
80
80
1/32 to 1/128
HD66100F
80
LCD drive circuits
Power supply for internal logic (V)
Display duty
Package
2. HD61100A and HD61200
LCD drive circuits
common
column
static to 1/128
o to 17
Display duty
Power supply for LCD drive circuits (V)
Power supply limits of LCD driver
circuit voltage
8 to 17
shown in figures below
Vee to VEE
(no limit)
Resistance between terminal Y and terminal
V (one of V1L, V1R, V2L, V2R, V3L, V3R, V4L,
and V4R) when load current flows through
one of the terminals Y1 to Y80 is specified
under the following conditions:
Vee-VEE=17V
V1L=V1R, V3L=V3R=Vee-2/7 (Vee-VEE)
V2L=V2R, V4L=V4R=VEE+2/7 (Vee-VEE)
Ro~
Vll.V1R
0
V3L,V3R
0
~
V4L,V4R
0
~
V2L,V2R
,..
A
'V
~
-
-
_ Terminal Y
(Y, to Yool
AN
,..
V/"
Figure 1 Resistance between Y ard V Terminals
The following is a description of the range of
power supply voltage for liquid crystal display drives. Apply positive voltage to V1L =
V1R and V3L = V3R and negative voltage to
V2L=V2R and V4L=V4R within the t:.~ range. This range allows stable impedance on
driver output (RON). Notice the t:. V depends
on power supply voltage Vec-VEE.
.,-------,=:=-"'-"'-"'-'""."'- ~ie(Vl L=Vl R)
i'V
The Range of P!>Wer Supply
Voltage for Liquid Crystal
Display Drive
--- V3 (V3L=V3R)
5.5
~
>
V4 (V4L=V4R)
V2 (V2L=V2R)
.'V
Correlation between "Driver
Output Waveform and Power
supply Voltages for Liquid
Crystal Display Drive
------J'\
V4L,V4R
Figure 4 Resistance between Y and V Terminals
The follOwing is a description of the range of
power supply voltage for liquid crystal display drives. Apply positive voltage to V1L=
V1R and V3L=V3R and negative voltage to
V2L=V2R and V4L=V4R within the IlV ran-
ge. This range allows stable impedance on
driver output (RON). Notice that IlV depends
on power supply voltage Vee-VEE.
The Range of Power Supply
Voltage for Uquid Crystal
Display Drive
Vee
Vl (Vl L=Vl R)
V3 (V3L=V3R)
5.0
~
>
.V
Figure 5 Power Supply Voltage Range
HITACHI
18
Hitachi America, Ltd.· Hitachi
Plaz~·
2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Differences Between Products
6. HD61103A and ·HD61203
HD61103A
HD61203
Recommended voltage between
Vee and VEE (V)
4.5to17
8 to 17
Power supply limits of LCD drive
circuits voltage
Vee to VEE (no limit)
shown in figures below
Output terminal
shown in following figure 4
shown in following figure 5
Resistance between terminal Y and terminal
V (one of V1L, V1R, V2L, V2R, V5L, V5R, V6L
and V6R) when load current flows through
one of the terminals Xl to X64. This value is
specified under the following conditions:
V1L,V1R
0
V6L,V6R
0
V5L,V5R
0
Vee-VEE=17V
V1L=V1R, V6L=V6R=Vee-l/7 (Vee-VEE)
V2L=V2R, V5L=V5R=VEE+l/7 (Vee-VEE)
Terminal V
(V, to VS4 )
V2L,V2R
Figure 6 Resistance between Y and V Terminals
Here is a description of the range of power
supply voltage for liquid crystal display drive.
Apply postive voltage to V1L=V1R and V6L=
V6R and negative voltage to V2L = V2R and
V5L=V5R within the ilV range.
This range allows stable impedance on driver
output (RON). Notice that ilV depends on
power supply voltage Vee-VEE.
The Range of Power Supply
Voltage for Liquid Crystal
Display Drive
3.5----------------
Vee
V1 (V1L,=V1R)
V6 (V6L=V6R)
~
>
2------
teS: 1, Mark snail be
on pohirog ._n.
2. Dirnen.;Of1a1toIer&rlcesIre ±O.1 mm
unless otM1W1" noted
3. The figure below thows • erotII-HCliollollt
view of Ihl! outer lead booding ••e6
~
C_''''f
Adhe5iYe~1
Film
O.IJ±O.OS
Figure 11 Hitachi Standard TCP 8 - HD66300TOO -
HITACHI
36
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819 - (415) 589-8300
TCP
1
i
I
I1
IrIIaII:t.'1iIIeranoII . . SO'l ............. iIIcIIcIIId.
2. TMIMdCl'Oll ...... aI . . . . . cone.d ...... iI~ ..........
Figure 12 Hitachi Standard TCP 9 - HD66310TOO -
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
37
TCP
2.2 Product Delivery Specifications
Specifications for product delivery to customers is described below.
2.2.1 Tape Joint (Including Lead Tape Joint)
TCP tape is cut into strips for aging and other purposes, after which they are again joined together.
Joint specifications are given below (figure 13).
o
[~
0 [] 0
User
[] 0 0 0 0 0
/user!
pattern
pattern
[
:::J 0 0 [] [] [~ 0 0 0 0 0 0
Joint tapes
=g<
. I I. 3.35,6.0 or 12.2 mm
Note:
Units: mm
Joint tape is affixed to both top and bottom surfaces of the joint. The
joint must not be twisted or subjected to a large stresses.
Figure 13 Tape Joint
2.2.2 Mark
Hitachi control code, made up of three or six digits, is marked on potting resin as shown in figure
14. The HD66108TOO is marked on top of the solder resist.
('..--------------- . . . . ------------.. .1
!
Die center
!,,,
:
i',,----- -----------
V
Molding area
i
---------------_#,'
Figure 14 Mark Pattern
"
38
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
TCP
2.2.3 Packing
Antistatic sheet
Reel
Figure 15 Packing
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
39
TCP
(1) Delivery
A reel wound with carrier tape is sealed in an opaque antistatic sheet with N2 and packed into a
carton before delivery.
(2) Thpe
I.
Carrier tape:
40m
II.
Lead tape:
2+0/-1 m added to both ends of the carrier tape
III. Conductive tape:
40m
IV. Separator:
40m
V.
Tape is wound with its pattern surface on the inside.
Note: The length of I, III, and IV may vary slightly depending on the number of products
contained on the tape.
(3) Request for Recovery of Packing Material
Please return the separator, lead tape, and reel to us after using the TCP product.
Detailed return procedures will be advised by our Sales Department.
HITACHI
40
Hitachi America, Ltd. e Hitachi Plaza e 2000 Sierra Point pkwy.. e Brisbane, CA 94005-1819 e (415) 589-8300
TCP
(3) Reel
3
'"
d
.. .
0-
+1
~ -en
ui
'"
4
~
37
3
LJ[
e- f - - - f -
Dc
Note: The shaft hole of the reel is slightly greater than the specified shaft size.
mm
Unit:
Material: Styrole
Figure 16 Reel Dimensions
Note: LSls dtermined defective during classification, assembly, or other processes are punched
out.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
41
TCP
2.2.4 Storage Conditions
(1) When storing in the original packing
Store in nOmlal atmospheric conditions, and use within 6 months of delivery.
(2) Storage after opening
Storage in a nitrogen atmosphere with a dew point of -30°C or below is recommended.
2.2.5 Usage Notes for TCP Products
(1) Prevention of Static Damage
In addition to nOmlal static preventive measures for IC circuits, observe the following precautions
for TCP products.
• Since TCP products have a film layer on their base, they acquire a static charge easily. In
handling TCP products exert extra caution in the installation of ion blowers and grounding so
that the fIlm does not become charged.
• At the same time as handling the circuits in a manner such that static electricity is not applied to
the package leads, carry out static electricity damage prevention measures in the equipment,
especially in the parts of the tape guide which contact the lead pins.
(2) Lead Outer Coating
The lead spacing of TCP products is signifIcantly narrower than that of other products and
shorting problems are more easily caused by conductive foreign elements such as stray solder or
machinings. We recommend an outer coating of resin over the leads as a preventive measure.
AlSo, to enable TCP products to be mounted at a high density, a conductive foil is bonded to the
fllm, and wiring and leads are fOmled by precision manufacturing techniques. Therefore, it is
possible that contamination of the foil with, for example, solder flux, may result in corrosion and
broken connections. Thus, special care should be taken to avoid wiring and lead contamination
when mounting TCP products by soldering or other methods.
(3) Mechanical and Electrical Handling
To reduce thickness, the back surface of the chip is exposed in TCP products. To prevent chip
cracking or static damage, mount TCP products in a manner which results in no mechanical or
electrical contact with the back surface of the chip:
Since the wiring and leads on the TCP tape is fabricated from extremely thin copper foil, its
mechanical strength is reduced. Mounting techniques and structures which apply strong external
forces to the copper foil should be avoided.
Also, to assure electrical characteristics, avoid direct exposure to sunlight.
HITACHI
42
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
TCP
(4) Unpacking
• The copper foil is plated. To assure good solderability, use the products as soon after unpacking
as possible.
• Since TCP products use polyimide as their base film, the film expands when it absorbs
moisture. Although the packaging is moisture proof, TCP products should be used as soon after
opening as possible.
(5) Other Items
• We recommend the use of the sprocket holes in the stamped product parts in positioning TCP
products during individual punching.
• Since lead tape has a poor ability to withstand heat, and shrinks when heated, do not apply high
temperatures to the lead tape.
• Bending TCP products can introduce cracks in the solder resist. Care should be taken to avoid
bending when handling TCP products.
• When stacking TCP product boxes (the original packaging) for storage, do not stack more than
10 high.
• Do not apply large mechanical shocks to TCP product packaging.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
43
Package Information
Package Information
The Hitachi LCD driver devices use plastic
flat packages to reduce the size of the
equipment in which they are incorporated
and provide higher density mounting by utilizing the fe~tures of thin liQl.lid crystal display
elements.
Package Dimensions .
Scala: 3/2
FP-54
25.6tO.4
~
00
+1
,..0
'"
",;
..;
+1
~
",;
Code
1. 70tO.30
FP-54
EIAJ
JEDEC
HD43160AH
Applicable LSI
FP-60
25.6tO.4
Code
1. 70tO.30
Applicable LSI
FP-60
EIAJ
JEDEC
HD44100H, HD44103CH, HD44105H
HD61830, HD61830B
./
HITACHI
44
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
Package Information
FP-80
~~"" ...ttInOnnnnnnn~
.,
o
-
0 lif
o
1. 70tO.30
Code
FP-80
EIAJ
JEOEC
H061602, H061603, HD61604, HD61605
HD44780, HD66780, HD63645F, HD64645F
HD44102CH
Applicable LSI
17 2tO 3
014.0
FP-80A
60
411
61
40
80
21
'".,
~I
0
""~
1
0.30tO.05
20
II *10.13IM
o.
N_
00
+1
"
'"
a
~ ~
1.60
c-i '"
Code
0.80
FP-80A
EIAJ
JEOEC
HD66780, HD44780, HD61602
Applicable LSI
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
45
Package Information
24 .S+O
- .4
20.0
FP-80B
65 funnnnn""""n""""""""n"n""!1
L
~
0
::!:
~
25
SO
0;35to.!~1.'0.!51191
24
o.
o.
...
~l~o .ftInnnnDnnnnbbDDDb~
+1
1.20tO.
20 II
Code
FP-80B
EIAJ
JEDEC
,HD64646FS. HD66780
Applicable LSI
FP-100
o.
o·
co
.
... ..;2•
+I
0
IN
2
Applicable LSI
~~
~""""".:tr
ii
.
1. 70tO.30
Code
FP -100
EIAJ
JEDEC
HD61100A. HD61102. HD61103A. HD61104. HD66204
HD61105. HD66205. HD61200. HD61202. HD61203
HD66100F
HITACHI
46
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
Package Information
.-.
24 8+0 4
20.0
FP-100A
511
80
50
81
1
0
~
•
~
31
lOO=.,.
0.30tO.I~ II .10.131~1
30
o.
N00
+I
...
0
IN
."
~
..;
""~l
J6nlmlnmDBmmn~
:;;
+1
~
0-1~
o
~
~
1.20tO.20
0
II
Code
FP-l00A
EIAJ
JEDEC
HD66106F. HD66840F. HD66841F
Applicable LSI
.-.
FP-100B
16 0+0 3
014.0
75
51
50
76
~
1
26
100
~
25
0.20.10.101191
~L~1.00
.•
0-5
o
0.50
Code
EIAJ
JEDEC
FP-l00B
HD66100F
Applicable LSI
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
.~~--~---
--~----
47
Package Information
15.6
014.0
TFP-100
75
51
76
50
~l
"!
:!;
100
26
~
0.20
25
:.10.10If!lll
0.50
t
.
"
""
-~
5
0
-
"" =.
E""
,~ o."11:"
0.30
0
0-5"
>y
Code
EIAJ
JEDEC
HD61104TF, HD61105TF
Applicable LSI
FP-136
-
TFP-100
---
.- .
028.0
69
102
103
68
1
~
35
136
1 0.35tO.10
111.10.151~1
34 o.
1.60
~l~ AnnnononnnnbDOUObDononnnnnnnnnnnooh.!{
o
+1
Code
EIAJ
JEDEC
0.80
Applicable LSI
FP-136
HD66850F
HITACHI
48
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Reliability and Quality Assurance
1. Views on Quality and Reliability
Hitachi's basic quality aims are to meet individual user's purchase purpose and quality
required. and to be at a satisfactory quality
level considering general marketability.
Quality required by users is specifically clear
if the contract specification is provided. If not.
quality required is not always definite. In
both cases. Hitachi tries to assure reliability
so that semiconductor devices delivered can
perform their function in actual operating
circumstances. To realize this quality in the
manufacturing process. the key points should
be to establish a quality control system in the
process and to enhance the quality ethic.
In addition. quality required by users of
semiconductor devices is going toward
higher levels as performance of electronic
system in the market is increasing and
expanding in size and application fields. To
cover the situation. Hitachi is performing the
following:
1. Building in reliability in design at the stage
of new product development.
2. Buliding in quality at the sources of the
manufacturing process.
3. Executing stricter inspection and reliability confirmation of final products.
4. Making quality levels higher with field
data feedback.
5. Cooperating with research laboratories for
higher quality and reliability.
With the views and methods mentioned
above. utmost efforts are made to meet users'
requirements.
2. Reliabillty Design of Semiconductor
Devices
2.1 Reliability Targets
The reliability target is the important factor
in manufacture and sales as well as performance and price. It is not practical to rate
reliability targets with failure rates under
certain common test conditions. The reliability target is determined corresponding to the
character of equipment taking design. manufacture. inner process quality control.
screening and test method. etc. into consideration. and considering the operating circumstances of equipment the semiconductor
device is used in. reliability target of the
system. derating applied in design. operating
condition. maintenance. etc.
2.2 Reliability Design
To achieve the reliability required based on
reliability targets. timely study and execution
of design standardization. device design (including process design. structure design).
design review. reliability test are essential.
2.2.1 Design Standardization
Establishment of design rules. and standardization of parts. material and process are
necessary. To establish design rules. critical
quality and reliability items are always studied at circuit design. device design. layout
design. etc. Therefore. as long as standardized process. material. etc. are used. reliability
risk is extremely small even in newly developed devices. except in cases where special
functions are needed.
2.2.2 Device Design
It is important in device design to consider
the total balance of process design. structure
design. circuit and layout design. Especially
when new processes and new materials are
employed. careful technical study is executed
prior to device development.
2.2.3 Reliability Evaluation by Test Site
Test site is sometimes called test pattern. It is
a useful method for design and process reliability evaluation of les and LSls which have
complicated functions.
Purposes of test site are:
· Making fundamental failure mode clear
· Analysis of relation between failure mode
and manufacturing process condition
· Search for failure mechanism analysis
· Establishment of QC point in manufacturing
Evaluation by test site is effective because:
· Common fundamental failure mode and
failure machanism in devices can be
evaluated.
· Factors dominating failure mode can be
picked uP. and comparison can be made
with processes that have been experienced
in field.
· Relation between failure causes and manufacturing factors can be analyzed.
· Easy to run tests.
· Etc.
2.3 Design Review
Design review is an organized method to
confirm that a design satisfies the required
performance (including users') and that
design work follows the specified methods.
and whether or not improved technical items
accumulated in test data of individual major
HITACHI
Hitachi Amer:i~. Ltd. • Hitachi PI~z~·JQQ.Q. Sierra P~ir1t Pkwy.......I3risbane. CA.~005-18!~~. (i1~5) 589-830L __!~
Reliability and Quality Assurance
fields and field data are effectively built in. In
addition, from the standpoint of enhancement of the competitive power of products,
the major purpose of the design review is to
ensure quality and reliability of the products.
In Hitachi, design reviews are performed
from the planning stage for new products
and even for design changed products. Items
discussed and determined at design review
are as follows:
1. Description of the products based on
specified design documents.
2. From the standpoint of the specialties of
individual participants, design documents
are studied, and if unclear matter is found,
calculation, experiments, investigation,
etc. will be carried out.
3. Determine contents of reliability and
methods, etc. based on design documents
and drawings.
4. Check process ability of manufacturing
line to acl1ieve design 99al.
5. Discussion about preparation for production.
6. Planning and execution of subprograms
for design changes proposed by individual
specialists, and for tests, experiments and
calculation to confirm the design changes.
7. Reference of past failure experiences with
similar devices, confirmation of methods to
prevent them, and planning and execution
of test programs for confirmation of them.
These studies and decisions are made
using check lists made individually de-·
pending on the objects.
3. Quality Assurance System of Semiconductor Devices
3.1 Activity of Quality.Assurance
General views of overall quality assurance in
Hitachi are:
1. Problems in an individual process should
be solved in the process. Therefore, at final
product stage, the potential failure factors
have been already removed.
2. Feedback of information should be used to
ensure lIatisfactory level of process capability.
3. To assure required reliability as a result of
the items mentioned above is the purpose
of quality assurance.
The following discusses device design, quality approval at mass production, inner process quality control, product inspection and
reliability tests.
.
3.2 Quality Approval
production stage of device deSign and the
mass production stage based on reliability
design as described in section 2.
Hitachi's views on quality approval are:
1. A third party must perfOriq approval
objectively from the standpoint of customers.
2. Fully consider past failure experiences and
information from the field.
3. Approval is needed for design change or
work change.
4. Intensive approval is executed on parts
material and process.
.
5. Study process capability and variation
factor, and set up control points at mass
production stage.
Considering the views mentioned above,
figure 1 shows how quality approval is performed.
3.3 Quality and RellabUlty Control at
Mass Production
For quality assurance of products in mass
production, quality control execution is
divided organically by function between
manufacturing department and quality
assurance department, and other related
departments. The total function flow ,is
shown in figure 2. The main points are described below.
3.3.1 Quality Control of Parts and Mate·
rial
As the performance and the reliability of
semiconductor devices improve, the importance of quality control of material and parts
(crystal, lead frame, fine wire for wire bonding, package) to build products, and materials
needed in manufacturing process (mask pattern and chemicals) increases. Besides quality
approval on parts and materials stated in
section 3.2, the incoming inspection is also
key in quality control of parts and materials.
The incoming inspection is performed based
on an incoming inspection specification, following purchase specification and drawings,
and sampling inspection is· executed based
mainly on MIL-STD-105D.
The other activities of quality assurance are
as follows:
,1. Outside vendor technical information
meeting
2. Approval on outside vendors, and guid.
ance of outside vendors
3. Physical chemical analysis and test
The typical check points of parts and materials are shown. in table 1.
To ensure required quality and reliability,
.quality approval is carried· out at the trial
HITACHI
50
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Reliability and Quality Assurance
3.3.2 Inner Process Quality Control
manufacturing process is tightly executed:
Strict check on each process and each lot,
100% inspection to remove failure factor
caused by manufacturing variation, and
necessary screening, such as high temperature aging and temperature cycling.
Contents of inner process quality control
are:
· Condition control on individual equipment and workers, and sampling check
of semifinal products.
· Proposal and carrying-out of work
improvement
• Education of workers
• Maintenance and improvement of yield
• Detection of quality problems, and execution of countermeasures
· Transmission of information about quality
Inner process quality control performs a very
important function in quality assurance of a
semiconductor devices. The follOwing is a
description of control of semifinal products,
final products, manufacturing facilities,
measuring equipments, circumstances and
submaterials. The quality control in the
manufacturing process is shown in figure 3
corresponding to the manufacturing process.
1. Quality Control of Semifinal Products and
Final Production Products
Potential failure factors of semiconductor
devices should be removed in manufacturing process. To achieve this, check
points are setup in each process, and
products that have potential failure factors
are not transferred to the next process. For
high reliability semiconductor devices,
especially manufacturing line is carefully
selected, and the quality control in the
Step
I
I
I
Target
Specification
,
2. Quality Control of Manufacturing Facilities
and Measuring Equipment
Equipment for manufacturing semicon-
Contents
Purpose
Design Review
J
Design
Trial
Production
Materials, Parts
Approval
Characteristics Approval
~
Characteristics of Material
and Parts
Appearance
Dimension
Heat Resistance
Mechanical
Electrical
Others
f--
Electrical Characteristics
Function
Voltage
Current
Temperature
Others
Appearance, Dimension
1
Confirmation of Target
Spec. (Mainly Electrical
Characteristics)
11
Confirmation of Quality
and Reliability in Design
Confirmation of
Characteristics and
Reliability of Materials
and Parts
.
I
Quality Approval (1)
Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Mechanical Stress
Others
I
Quality Approval (2)
Reliability Test
Process Check (same as
Quality Approval (1) )
I
Mass Production
Confirmation of Quality
and Reliability in Mass
Production
I
Figure 1 Quality Approval Flowchart
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589~8300
51
Reliability and Quality Assurance
ductor devices have been developing
extraordinarily, with required high performance devices and production inprovements. They are important factors to
determine quality and reliability. In Hitachi, automation of manufacturing equipment is promoted to improve manufacturing variation, and controls maintain proper
operation and function of high performance equipment. Maintenance inspection for quality control is performed daily
based on related specifications, and also
periodical inspections. At the inspection,
inspection points listed in the specification
are checked one by one to avoid any omissions. During adjustment and maintenance of measuring equipment, mainte-
Process
nance number and specifications are
checked one by one to maintain and
improve quality.
3. Quality Control of Manufacturing Circumstances and Submaterials
Quality and reliability of semiconductor
devices is greatly affected by manufacturing process. Therefore, manufacturing circumstances (temperature, humidity, dust)
and the control of submaterials (gas, pure
water) used in manufacturing process are
intensively controlled. Dust control is described in more detail below.
Dust control is essential to realize higher
integration and higher reliability of
devices. In Hitachi, maintenance and
Quality Control
Material,
Parts
Inspection on Material and
Parts for Semiconductor
Devices
Method
Lot Sampling,
Confirmation of
Quality Level
Manufacturing Equipment,
Environment. Submaterial.
Worker Control
Inner Process Quality
Control
100% Inspection of
Appearance and Electrical
Characteristics
Products
Sampling Inspection of
Appearance and Electrical
Characteristics
I
I
I
I
IL _____ _
Reliability Test
r-----------------,
:
I
I
Quality Information
I
Claim
:
Field Experience
I
General Quality
I
~ __ ~!.~~a.!!~n________ J
Feedback of
Information
Figure 2 Flowchart of Quality Control in Manufacturing Process
HITACHI
52
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
Reliability and Quality Assurance
improvement of cleanness and manufacturing site cleanness are executed paying
close attention to buildings, facilities, airconditioning systems, packaging materials, clothes, work, etc., and periodical
inspection for floating dust in room, falling
dust, and floor dust.
3.3.3 Final Product Inspection and Rellability Assurance
1. Final Product Inspection
Lot inspection is done by quality assurance department for products that were
judged to be 100% good in tests, which is
the final process in the manufacturing
department. Though 100% good products
is expected, sampling inspection is
executed to prevent inclusion of failed
products by mistake, etc. The inspection is
executed not only to confirm that the
products meet users' requirements, but to
consider potential trouble factors. Lot
inspection is executed based on MIL-STD105D.
1. Reliability Assurance Tests
To assure reliability of semiconductor
devices, periodical reliability tests and.
reliability tests on individual manufacturing lots required by user are performed.
Table 1 Quality Control Check Points of Material and Parts
(Example)
Material, Parts
Wafer
Mask
Fine wire for wire bonding
Frame
Ceramic package
Plastic
Important Control Items
Appearance
Dimension
Sheet resistance
Defect density
Crystal axis
Appearance
Dimension
Registration
Gradation
Appearance
Dimension
Purity
Elongation ratio
Appearance
Dimension
Processing accuracy
Plating
Mounting characteristics
Appearance
Dimension
Leak resistance
Plating
Mounting characteristics
Electrical characteristics
Mechanical strength
Composition
Electrical characteristics
Thermal characteristics
Molding performance
Mounting characteristics
Points to Check
Damage and contamination on surface
Flatness
Resistance
Defect numbers
Defect numbers, scratch
Dimension level
Uniformity of gradation
Contamination, scratch, bend, twist
Purity level
Mechanical strength
Contamination, scratch
Dimension level
Bondability, solderability
Heat resistance
Contamination, scratch
Dimension level
Airtightness
Bondability, solderability
Heat resistance
Mechanical strength
Characteristics of plastic material
Molding performance
Mounting characteristics
HITACHI
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53
Reliability and Quality Assurance
Control point
Process
Purpose of control
Y Purchase of material
.-------'
f-Wafer _ _
Characteristics. Appearance
Scratch. removal of crystal
defect wafer
(
Surface oxidation
[
Inspection of surface
oxidation
(
Photo resist
[~
Inspection of photo resist
Assurance of resistance
Oxidation
Appearance, Thickness of
oxide film
Pinhole. Scratch
Dimension, Appearance
Dimension level
Diffusion depth, Sheet
resistance
Diffusion status
Gate width
Control of basic parameters
(VrH, etc.) cleanness of surface
Prior check of VrH
Breakdown voltage check
Photo
resist
pac level check
(
Diffusion
[
Inspection of diffusion
Check of photo resist
Diffusion
pac level check
(
Evaporation
Characteristics of oxide
film. Breakdown voltage
Evaporation
Thickness of vapor film,
Scratch, Contamination
Assurance of standard
thickness
Prevention of cracks,
Quality assurance of scribe
~
r
Inspection of evaporation
[
Wafer inspection
Wafer
Thickness, VrH characteristics
[
Inspection of chip
electrical characteristics
Chip
Electrical characteristics
POC level check
(
Chip scribe
[
Inspection of c~ip
appearance
Appearance of chip
POC lot judgement
t-Frame ____
(
Assembling
Assembling
Appearance after wire
bonding
Pull strength, Compression
width. Shear strength
pac level check
[
Appearance after chip
bonding
Quality check of chip
Bonding
Quality check of wire
Bonding
Prevention of open and
short
Appearance after assembling
Inspection after .assembling
POC lot judgement
'-Package_
(
Sealing
pac level check
Sealing
Appearance after sealing
Outline, Dimension
Marking
Marking strength
Guarantee of appearance
and dimension
Final electrical inspection
Failure analysis
Analysis of failures. Failure
mode. Mechanism
Feedback of analysis information
Appearance inspection
Sampling inspection of
products
)
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
HITACHI
54
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
Reliability and Quality Assurance
(Failures, Information)
Sales Dept.
Sales Engineering Dept.
r------------------- - - - - - - - - - -- - --- -----------,
I
I
I
Failure Analysis
Quality Assurance Dept.
I
I
I
I
II
Countermeasure,
Execution of
Countermeasure
I
I
I
I
:I
I
I
I
I
Report
I
I
I
I
I
I
I
:
I
I
I
I
Quality Assurance Dept.
Follow-up and Confirm-
:
ation of Countermeasure
I
I
Execution
I
I
Report
IL ________________________________________________
JI
Sales Engineering Dept.
Reply
Customer
Figure 4 Process Flowchart of Field Failure
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
55
Reliability Test Data of LCD Drivers
1. Introduction
based on test data and failure analysis
results.
The use of liquid crystal displays with microcomputer application systems has been
increasing, because of their low power consumption, freedom in display pattern design,
and thin shape. Low power consumption and
high density packaging have been achieved
through the use of the CMOS process and the
flat plastic packages, respectively.
This chapter describes reliability and quality
assurance data for Hitachi LCD driver LSIs
2. Chip and Package Structure
The Hitachi LCD driver LSI family uses low
power CMOS technology and flat plastic
package. The Si-gate process is used for high
reliability and high density. Chip structure
and basic circuit are shown in figure 1, and
package structure is shown in figure 2.
Gate
Si02 Source
Drain
FET2
Figure 2 Package Structure
P-channel
EMOS
N-channel
EMOS
Figure 1 Chip Structure and Basic
Circuit
HITACHI
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Reliability Test Data of LCD Drivers
3. Reliability Test Results
The test results of LCD driver LSI family are
shown in Tables 1, 2, and 3.
Table 1 Test Result 1, Higb Temperature Operation
(Ta=125°C, Vcc=5.5V)
Device
Sample Size
Component Hour
Failure
HD44100H
HD44102H
HD44103H
HD44780
HD66100F
HD61100A
HD61102
HD61103A
HD61200
HD61202
HD61203
HD61104
HD61105
HD61830
HD61830B
HD63645
HD64645
HD61602
HD61603
HD61604
HD61605
HD66840
40
40
40
90
45
80
50
50
40
50
40
45
45
40
40
32
32
38
32
32
32
45
40,000
40,000
40,000
90,000
45,000
80,000
50,000
50,000
40,000
50,000
40,000
45,000
45,000
40,000
40,000
32,000
32,000
38,000
32,000
32,000
32,000
45,000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2 Test Result 2
Teat Item
Teat Condition
Sample
Size
Component
Hour
High temp, storage
Low temp, storage
Steady state humidity
Ta=150'C, 1000 h
Ta=-55'C, 1000 h
65'C, 95% RH, 1000 h
180
140
860
180,000
140,000
860,000
Steady state humidity, biased
85'C, 90% RH, 1000 h
165
170,000
Pressure cooker
121'C, 2 atm.l00 h
200
20,000
Failure
0
0
1*
2*
0
Note: ·Aluminum corrosion
HI1ACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
57
Reliability Test Data of LCD Drivers
Table 3 Test Results 3
Test Items
Test Condition
Sample Size
Failure
Thermal shock
o to
108
o
678
o
283
o
o
o
Temperature cycling
Soldering heat
Resistance to VPS
Solderability
100'C
10 cycles
-55'C to 1 50'C
10 cycles
260'C, ~O seconds
21 5'C, 30 seconds
230'C, 5 seconds
4. Quality Data from Field Use
Field failure rate is estimated in advance
through production process evaluation and
reliability tests. Past field data on similar
devices provides the basis for this estimation.
Quality information from the users is indispensable to the improvement of product
88
140
quality. Therefore, field data on products
delivered to the users is followed up carefully.
On the basis of information furnished by the
user, failure analysis is conducted and the
results are quickly fed back to the design and
production divisions.
Failure analysis results on MOS LS1s returned
to Hitachi is shown in figure 3.
Damaged by
excessive
voltage
and/or
Figure 3 Failure Analysis Result
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Reliability Test Data of LCD Drivers
5. Precautions
6.1 Storage
It is preferable to store semiconductor
devices in the following ways to prevent
deterioration in their electrical characteristics, solderability, and appearance, or breakage.
~
1. Store in an ambient temperature of 5 to 30'
C, and in a relative humidity of 40 to 60%.
2. Store in a clean air environment, free from
dust and reactive gas.
3. Store in a container that does not induce
static electricity.
4. Store without any physical load.
5. If semiconductor devices are stored for a
long time, store them in unfabricated form.
If their lead wires wires are formed
beforehand, bent parts may corrode during storage.
6. If the chips are unsealed, store them in a
cool, dry, dark, and dustless place.
Assemble them within 5 days after
unpacking. Storage in nitrogen gas is
desirable. They can be stored for 20 days
or less in dry nitrogen gas with a dew
point at -30'C or lower. Unpackaged
devices must not be stored for over 3
months.
7. Take care not to allow condensation during storage due to rapid temperature
changes.
5.2 Transportation
As with storage methods, general precautions for other electronic component parts are
applicable to the transportation of semiconductors, semiconductor-incorporating units .
and other similar systems. In addition, the
following considerations must be taken, too:
1. Use container!! or jigs whCh will not induce
static electricity as the result of vibration
during transportation. It is desirable to use
an electrically conductive container or
aluminium foil.
2. Prevent device breakage from clothes-in-
duced static electricity.
3. When transporting the printed circuit
boards on which semiconductor devices
are mounted, suitable preventive measures against static electricity induction
must be taken; for example, voltage builtup is prevented by shorting terminal circuit. When a conveyor belt is used, preven;t
the conveyor belt from being electricRl!y
charged by applying some surface t~at
ment.
4. When transporting semiconductor devices
or printed circuit boards, Diinimize
mechanical vibration and shoc}f.
5.3 Handling for Measurement
Avoid static electricity, noise, and surge
voltage when measuring semiconductor
devices are measured. Jt is possible to prevent breakage by shorting their terminal
circuits to equalize electrical potential during
transportation. However, when the devices
are to be measured or mounted, their terminals are left open providing the possibility
that they may be accidentally touched by a
worker, measuring instrument, work bench,
soldering iron, conveyor belt, etc. The device
will fail if it touChes something that leaks
current or has a static charge. Take care not
to allow curve tracers, synchroscopes, pulse
generators, D.C. stabilizing power supply
units, etc. to leak current through their terminals or housings.
Especially, while testing the devices, take
care not to apply surge voltage from the
tester, to attach a clamping circuit to the
tester, or not to apply any abnormal voltage
through a bad contact from a current source.
During measurement, avoid miswiring and
short-circuiting. When inspecting a printed
circuit board, make sure that there is no soldering bridge or foreign matter before turning on the power switch.
Since these precautions depend upon the
types of semiconductor devices, contact
Hitachi for further details.
HITACHI
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59
Flat Plastic Package (QFP) Mounting Methods
Surface Mounting Package Handling Precautions
1. Package temperature distribution
The most common method used for mounting
a surface mounting device is int:rared reflow.
Since the package is made of a black epoxy
resin, the portion of the package directly
exposed to the infrared heat source will
absorb heat faster and thus rise in temperature more quickly than other parts of the
package unless precautions are taken. As
shown in the example in figure 1, the surface
directly facing the infrared heat source is 20·
to 30·C higher than the leads being soldered
and 40· to 50·C higher than the bottom of the
package. If soldering is performed under
these conditions, package cracks may occur.
To avoid this type of problem, it is recommended that an aluminum infrared heat
shield be placed over the resin surface of the
package. By using a 2-mm thick aluminum
heat shield, the top and bottom surfaces of
the resin can be held to 175·C when the peak
temperature of the leads is 240·C.
2. Package moisture absorption
The epoxy resin used in plastic packages will
absorb moisture if stored in a high-humidity
environment. If this moisture absorption
becomes excessive, there will be sudden
vaporization during soldering, causing the
interface of the resin and lead frame to
spread apart. In extreme cases, package
cracks will occur. Therefore, especially for
thin packages, it is important that moistureproof storage be used.
To remove any moisture absorbed during
transportation, storage, or handling, it is
recommended that the package be baked at
125·C for 16 to 24 hours before soldering.
3. Heating and cooling
One method of soldering electrical parts is
the solder dip method, but compared to the
reflow method, the rate of heat transmission
is an order of magnitude higher. When this
method is used with plastic items, there is
thermal shock resulting in package cracks
and a deterioration of moisture-resistant
characteristics. Thus, it is recommended that
the solder dip method not be used.
Even with the reflow method, an excessive
rate of heating or cooling is undesirable. A
rate in temperature change of less than 4·C/
sec is recommended.
4. Package contaminants
It is recommended that a resin-based flux be
used during soldering. Acid-based fluxes
have a tendency of leaving an acid residue
which adversely affects product reliability.
Thus, acid-based fluxes should not be used.
With resin-based fluxes as well, if a residue is
left behind, the leads and other package
parts will begin to corrode. Thus, the flux
must be thoroughly washed away. If cleansing solvents used to wash away the flux are
left on the package for an extended period of
time, package markings may fade, so care
must be taken.
The precautions mentioned above are general points to be observed for reflow. However, specific reflow conditions will depend
on such factors as the package shape, printed
circuit board type, reflow method, and device
type. For reference purposes, an example of
reflow conditions for a OFP infrared reflow
furnace is given in figure 2. The values given
in the figure refer to the temperature of the
package resin, but the leads must also be
limited to a maximum of 260·C for 10 seconds
or less.
Of the reflow methods, infrared reflow is the
most common. In addition, ~here is also the
paper phase reflow method. The recommended conditions for a paper phase reflow
furnace are given in figure 3.
For details on surface mounting small thin
packages, please consult the separate manual available on mounting. If there are any
additional questions, please contact Hitachi,
Ltd.
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
Flat Plastic Package (OFF) Mounting Methods
30 sec. max.
(Resin)
300
250
~
i~
Infrared rays
215"C
"'-......r------1
l&SUrfaee)
~_L~
~ T2 T,
150-190"C
~,...,...,,~-{
1"'60see I
(Solder)
200
1-5"C/see
time _ _
150
100
Figure 3 Example Vapor-phase Reflow
Conditions
time (sec)
Figure 1 Temperature Profile During
Infrared Heat Soldering
(Example)
~
~
I
140-160"C
"-
~/.-----~
"'60see
1-4"C/see.
I
I
E
~~__________1_-_5_"_C/_s_ee_______________
time-
Figure 2 Recommende.d Reflow
Conditions for OFP
HITACHI
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61
Flat Plastic Package (OFP) Mounting Methods
Soldering iron method
Reflow method
(Spare solder)
Reflow method
(Solder paste)
Board
Board
Solder
Board
Solder paste
Spare
solder
L-_-,_ _'"
parts
Soldering
-260·C
(1 0 seconds)
Preheating
1ooto 150·C
(20 seconds)
Preheating
100to 150·C
(20 seconds)
Reflow
235·C
(10 seconds)
Reflow
235·C
(10 seconds)
(Resin coating)
¢
Figure 4 Recommended Paper Phase Reftow Conditions
HITACHI
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Hitachi America,Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Liquid Crystal Driving Methods
1. Static Driving Method
Driving a liquid crystal at direct current triggers an electrode reaction inside the liquid
cell, degrading display quality rapidly. The
liquid crystal must be driven by alternating
current. The AC driving method includes the
static driving method and the multiplex driving method, each of which has features for
different applications. Hitachi has developed
different LCD driver devices corresponding to
the static driving method and the multiplex
driving method. The following sections
describe the features of each driving method,'
the driving waveforms, and how to apply
bias.
Figure 1 shows the driving waveforms of the
static driving method and an example in
which "4" is displayed by the segment
method. The static driving method is the
most basic method by which good display
quality can be obtained. However, it is not
suitable for liquid displays with many segments because one liquid crystal driver circuit is required per segment.
The static driving method uses the frame
frequency (lit!) of several tens to several
hundreds Hz.
Uquid Crystal Display
and Terminal Connection
Voo
COMo
Voo
,,,
,
Voo
SEG n + 1
r--
d d+
III W
N
-
I--
r-
r--
r--
+
dW
W
III
III
n=O. 1........... 5
(n=O. 1......... ·.7)
OV
COMo-SEG n + 1
Selected waveform
- - ..-, - ,
'--
-
'-
-
-V3
1 frame
tf
COMo-SEG n + 1
Non-selected waveform - - - - - - - - - - - - - - -
~igure
1
OV
Example of Static Drive Waveforms (Example of HD61602/HD61603)
HITACHI
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63
Liquid Crystal Driving Methods
2. Multiplex Driving Method
The multiplex driving method is effective in
reducing the number of driver circuits, the
number of connections between the circuit
and the display cell, and the cost when driving many display picture elements. Figure 2
shows a comparision of the static drive with
the multiplex drive (1/3 duty cycle) in an 8dight numeric display. The number of liquid
crystal driver circuits required is 65 for the
former and 27 for the latter. The multiplex
drive reduces the number of driver circuits.
However, greater multiplexing reduces the
driving voltage tolerance. Thus, there are
limits to the extent of multiplexing.
.
There are two types of multiplex drive
waveforms: A type and B type. A type, shown
in figure 3, is used for alternation in 1 frame. B
type is used for alternation in between 2
frames (figure 4). B type has better display
quality than A type in high multiplex drive.
c~moo J·-f.!~1J)b)I. ~:.··J.y~1
Static driving
method
••••
i~~rl~
~~:
l··t·TmJ'Il··F'Fn··
J
le
ld lc 10.P 2d 2c20.P
Multiplex driving
method
(1/3 duty cycle)
52
S35. S5
Example of Comparision of Static Drive with Multiplex Drive
common~
common~
\'
l
Segment
Common-segment
lflJ1J1J1JlJUl
hnnhnnn
iU j UU L
U
U
,,
: 1 frame
Figure 3
8d 8c 80.P
.,--~---
S,
Figure 2
8e
Segment :
I
Common-segment
,
,,
"
: 1 frame:
'!
A Type Waveforms
(1/3 duty cycle, 1/3 bias)
I
Figure 4
B Type Waveforms
(1/3 duty cycle, 1/3 bias)
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Liquid Crystal Driving Methods
2.1. 1/2 Bias, 1/2 Duty Drive
pIe of the connection to display '4' on a liquid
crystal display of 7-segment type, and the
output waveforms.
In the 1/2 duty drive method, 1 driver circuit
drives 2 segments. Figure 5 shows an exam-
Liquid Crystal Display
and Terminal Connection
COMo
II
Veo
V,
V2
COM,
Veo
V,
COM,
V2
COMo
Veo
SEGn
SEGn+,
N
+
c3
UJ
III
+
c3
UJ
III
V2
Voo
M
+
c3
UJ
V2
III
n=0.1 ......... ·.11
V2
V,
COMo-SEGn----~--_+~--~~~~_+----+__
(Selected waveform)
OV
-V,
-V2
V,
+,
COMo-SEGn
(Non-selected waveform)
Figure 5
OV
V,
Example of Waveforms in 1/2 Duty Cycle Drive (B type) (Example of
HD61602)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
65
Liquid Crystal Driving Methods
2.2 1/3 Bias, 1/3 Duty Cycle Drive
In the 1/3 duty cycle drive, 3 segments are
driven by 1 segment output driver. Figure 6
Liquid Crystal Display
and Terminal Connection
shows an example of the connection to display '4' on a liquid crystal display of 7-segment type, and the output waveforms.
COMo
:
:
:
LJill-hnf
,
,I
I .
,
. - - - C O M2
COM,
'
'
:
I
,
:
,
:
:
-----COM,
I
'
'
V,
V2
!
V3
:
Voo
I
V,
I
--1II...._-COM o
V3
Voo
COM 2
V2
V3
Voo
V,
SEG n
V2
V3
I
I
,
!
:
:
:
:
V3
'
'
,
Voo
SEGn
+ , l If u i l l' r u : Voo
,
V,
,,
V2
I
,
SEG n + 2
d
w
II)
+
d
w
II)
V,
V2
N
+
d
w
V3
II)
n=O, 1, ......... , 16
V3
V2
V,
---;----;---~r----OV
COMo-SEG n + 2
(Selected waveform)
-V,
-V2
-V3
,
=J
COMo-SEG n
(Non-selected waveform)
,,
I-I--~F ~~,
~:- -....-.i-t:
1 frame
Figure 6
Example of Waveforms in 1/3 Duty Cycle Drive (B type) (Example of
HD61602)
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Liquid Crystal Driving Methods
2.3 1/3 Bias, 1/4 Duty Cycle Drive
In the 1/4 duty cucle drive, 4 segments are
driven by 1 segment output driver. Figure 7
shows an example of the connection to display '4' on a liquid crystal display of 7-se9ment type, and the output waveforms.
COMo
Liquid Crystal Display
and Terminal Connection
I
I
,
til
-{5dl.
CDM 3
I
,
i
: ~~D
: .
:
COM'ifl--hnJ:
:
COM 2
,
I
.!
I
V2
V3
i
COM2i-Jlhn-l
,
,
COM,
I
I
I
:
:
I
V3
COMo
+,
SEGn
SEGn
V3
n=0.1.·········.24
V2
V,
COM3-SEGn----r---+---~--~---r--OV
I
I
I
I
I
COMo-SEG n
(Non-selected waveform)
I
h riWnq t _;~
~ U·
V,
,
I
,
,
I
,
: 1 frame!
~
:
Figure 7
I
:
:
Example of Waveforms In 1/4 Duty Cycle Drive (B type) (Example of
HD61602)
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67
Liquid Crystal Driving Methods
2.41/4 Blas,/ 1/8 Duty Cycle Drive
VCC
v,
COM, V2(Va)
V4
Uquid Crystal Display
V5
1112131
4
III IIII I ____ II j II f
1
COM,
COM2
COMa
••••
0-
-a.ooa-a.ooa-
COM4~
CaMs
COMe
~O::
Vec
COM,
--DIIDOa-
;;;;r
1
hl
~I--~r----------~I----,--
"~I III II II I u__ II i
V5
-a.ooa-
1...............181112
I
1
~c -+1-r---------~-r~I....,.---.-
sm,
"~I !II
V5
----) B-1
I
,
I
I
VCC
V,
SEG 2 V2(Va)
V4
V5
illlllll--Jlm
,
,
I
V, =VcC-%VLCD
V2(Va) =VcC-l1!VLCD
V4 =VCC-%VLCD
Vs = Vcc - VLCD
COM,-SEG,
(Selected waveform)
VLCD
1
----r'-++------------ -=~=i~ F-F---t-++---------------,-.- - -
%VLCD -~~~_r,-~._--~~_+~,-
Li'
-VLCD
.1
-t--'------------ll--'--1
-->:--------_._-....,:------
... Example of LCD II.
V2 is same voltage as Va.
-'1-------_·_---'--_·-
'No~:~; -::-:-i1-1--.1--,.1-I-lI-_-___·-,-If~!jff
-l1!VLCD
!:
:
. Figure 8
~.----1 frame
'
Example of Waveforms In 1/8 Duty Cycle Drive (A type) (Example of LCD·
II)
HITACHI
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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point ~kwy. • Brisbane, CA 94005-1819. (415) 589-8300
Liquid Crystal Driving Methods
2.5 1/5 Bias, 1/8 Duty Cycle Drive
1
~
2-<
3-<
Common
4
5
6
7
}-
I
8
1/8 duty.
1/5 bias
41
~~______________~r-l~____
1
i
Segment
Common 1
Common 2
_---'n
~
Segment 1
-~II~------~II
~
----I"I
L J l_ _
Segment 2
Common 1
Common 2
Segment 1
Between segment 1
and common 1
(Display off)
Between segment 1
and common 2
(Display on)
Figure 9
Example of Waveforms in 1/8 Duty Cycle Drive (A type) (Example of
HD44100H)
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69
Liquid Crystal Driving Methods
2.6 1/5 Bias, 1/16 Duty Cycle Drive
I 1I 2 I 3 I 4
I1I
1~------116
Uquid Crystal Display
COM,rl-+-+-III=11=+--+---'-I---r-IIn=··
COM,
••••
0-
Vs
--aa.o---DIIOOa-
~~~: B---DIIOOa-
I
~c-~---,~---__________-+'____
COM3~
COM4
COM 5
,
1
1
COM2~
COM2
f
~~ --t-t--TI,---t---tIH-t--1I---+-+-+-111+--+-1
~ -+,--~~------------~,--~~
1
COMs
:
I
,
~C-r',------------------~I~----
COMg
COM,o--...aooaCOM"
--DOCJOa-
COM'2~
SEG'~~~'II
~ !II
~ -+I~~--------------~!-L~.~
1
I
COM'3--DD11DO-
~C-T'~~~-r,-~~-----4'-r~'-
~:::COM'6
-r9999-
"EG,
~ =--+-+-+-t-IIII=-t-t-+'-t--lIll===i=I--+____ .--=~!
III
I
,I
1
I
,
I
I
v, = Vcc -
J,iiVLCO
V2=VCC-%VLCO
--
COM,-SEG,
(Selected waveform) - J,iiVLCo
1
I
I
I
L-.I
V3=VCC-%VLCO
V4=VCC-%VLCO
Vs=VCC-VLCO
I
I
I
1
VLCO -+__________________~I------
~------------------~:-----
%VLCO -r'----~------------~'----,_
(--:M~, =:: =~! II_~~:'
=_1::
.........
[=_'=_-=_1=_'
=_'
:-+-i
1:. . .
=---&'
1
i
1
=$'~====~~~~====~'~====
-VLCO·
1-
1 frame
.,
Figure 10 Example of Waveforms in 1/16 Duty Cycle Drive (A type) (Example of LCDII)
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Liquid Crystal Driving Methods
2.7 1/5 Bias, 1/32 Duty Cycle Drive
V2
V5
V3
,,
,,
V6
V,
L
V4
COM,
,,
._-
I
:
,,
:
._-t=r--
I
~ ItI ~ Lg
V2
Vs
SEG,
:
:
!
i
m1
~::j
._.=r=
V6
:
'
~ -4--------~,-----------
'
~6!
~,=+VLCD
II
-+'--------+---------,,
,
,,
:
._-
,
COM, to SEG,
- YsVLCD
(Non-selected waveform)
it
__
I
I,
,
,,
I
L
:
---,
-
L
-V~D-+----~--~---------
VLCD - - t - - - - - - - -......, - - - - - - - - - -
COM, toSEGa
(Selected waveform)
- YsVLCD--irl------~L..------ - r--
-VLCD --!.......------"!":--------'........-
,
1 frame
Figure 11
-1
Example of Waveforms in 1/32 Duty Cycle Drive (Example of HD44102CH,
HD44103CH)
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71
Liquid Crystal Driving Methods
3. Power Supply Circuit for
Crystal Drive
Liquid
Table 1 shows the relationship between the
number of driving biases and display duty
cycle ratios.
3.1 Resistive Dividing
Driving ~ias is generally generated by a
resistive divider (figure 12).
The resistance value settings are determined
Table 1
by considering operating margin and power
consumption. Since the liquid crystal display
load is capacitive, the drive waveform itself is
distorted due to charge/discharge current
when the liquid crystal display drive
waveform is applied. To reduce distortion, ·the
resistance value should be decreased but this
increases the power consumption because of
the increase of the current through the dividing resistors. Since larger liquid crystal display panels have larger capac~tance,the
resistance value must be decreased proportionally.
Relationship between the Number of Display Duty Cycle Ratio and the
Number of Driving Biases
Display
duty ratio
Number of
driving biases
Static
1/2
2
344
(1/2 bias) (1/3 bias)
1/3 1/4 1/7 1/8 1/11 1/12 1/14 1/16 1/24 1/32 1/64
5
5
(1/4 bias)
5
5
Vec
Vee
V,
V,
R
~
6
-,-
R
V2
R
VlCD
VlCD
V3
R
R
V.
V.
R
R
V5
V5
V.
...< VR
-5V
~-'-
.../VR
-5V
1/4 Bias (1/8, 1/11 duty cycle)
Figure 12
6
R
R
V3
6
Vec (+5V)
Vee ( +5 V)
V2
6
6
(1/5 bias)
1/5 Bias (1/16 duty cycle)
Example of Driving Voltage Supply
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Liquid Crystal Driving Methods
It is efficient to connect a capacitor to the
resistors in parallel as shown in figure 13 in
order to improve charge/discharge distortion.
However, the effect is limited. Even if it is
attempted to reduce the power consumption
with a large resistor and improve waveform
distortion with a large capacitor, a level shift
occurs and the operating margin is not improved.
Since the liquid crystal display load is in a
matrix configuration, the path of the charge/
discharge. current through the load is com-
plicated. Moreover, it varies depending on
display condition. Thus, a value of resistance
cannot be simply determined from the load
capacitance of liquid crystal display. It must
be experimentally determined according to
the demand for the power consumption of
the equipment in which the liquid crystal
display is incorporated.
Generally, R is 1 kn to 10 ItO, and VR is 5kO to
50 kn. No capacitor is required. A capacitor of
0.1 uF is usually used if necessary.
V,cc (+5V)
Vcc
R
J,
V,
Common non-selected high level
C
R
V2
Segment non-selected high level
C
Segment non-selected low level
C
R
j
R
1
V3
v..
R
v&
Common/segment selected high level
C
t
Common non-selected low level
C
Common/segment selected low level
VR/. V
-5V
For contrast adiustment
Large C and R cause
a level shift.
Figure 13
Example of Capacitor ConnectIon for Improvement of Liquid Crystal
Display Drive Waveform Distortion (1/6 bias) (Example of LCD-II)
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73
Liquid Crystal Driving Methods
3.2 Drive by Operational Amplifier
In graphic displays, the size of the liquid
crystal becomes larger and the display duty
ratio becomes smaller, so the stability of liquid crystal drive level is more important than
in small display system.
Since the liquid crystal for graphic displays is
large and has many picture elements, the
load capacitance becomes large. The high
impedance of the power supply for liquid
crystal drive produces distortion in the drive
waveforms, and degcades disiplay quality.
For this reason, the liquid crystal drive level
impedance should be reduced with operational amplifiers. Figure 14 shows an example
of an operational amplifier configuration.
No load current flows through the dividing
resistors because of the high input impedance of the operational amplifiers. A high resistance of R = 10 kO and VR = 50 kO can be
used.
3.3 Generation of Liquid Crystal Drive
Levels in LSI
drive level may be incorporated in the LSI,
such as one for a portable calculatof with
liquid crystal display.
HD61602, HD61603 for small display systems
has a built-in power suply circuit for liquid
crystal drive levels.
3.4 Precaution on Power Supply Circuits
The LCD driver LSI has two types of power
supplies: the one for logical circuits and the
other for the liquid crystal display drive circuit. The power supply system is complicated
because of several liquid crystal drive levels.
For this reason, in the power supply design,
take care not to deviate from the voltage
range assured in the maximum rating at the
rise of power supply and from the potential
sequence of each power supply. If the input
terminal level is indefinite, through current
flows and the power consumption increases
because of the use of CMOS process in the
LCD driver.
Simultaneously, the potential sequence of
each power supply becomes wrong, which
may cause latch-Up.
The power supply circuit for liquid crystal
( +5V)Vcc
Common/segment selected ~igh level
...v
R
R
R
R
R
VR
--t:-
Segment non-selected high level
--{>-
Segment non-selected low level
~
r-..
rcontr~t
adjustment
-i>Figure 14
Common non-selected high level
Common selected low level
Common/segment selected low level
For liquid crystal drive logic circuits
Operational amplifier voltage follower
Drive by Operational Amplifier (l/5 bias)
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LCD CONTROLLERlDRNER LSI DATA BOOK
I DATA SHEETS I
Section Three
General1)rpe
LCD Driver
HITACHI
~--
... _-
__._---_.. _-
--- .
-.---~~
HD44100H-----------(LCD Driver with 40-Channel Outputs)
Pln Arrangement
Description
The HD44100H has two sets of 20-bit bidirectional shift registers, 20 data latch flipfiops
and 20 liquid crystal display driver circuits. It
receives serial display data from a display
control LSI, converts it into parallel data and
supplies liquid crystal display waveforms to
the liquid crystal.
The HD44100H is a highly general liquid
crystal display driver which can drive a static
drive liquid crystal and a dynamic drive liquid
crystal, and can be applied as a common
driver or segment driver.
~
.. .
~
»»>
v.
v,
v.
v,
v,
v,
FCS
SHL,
SHLI
M
NC
DR,
DL,
DR,
DL,
GND
CL,
CL,
y,
y,
Yl1 1
Y,
y,
y,
y,
Features
VEE
y.,23
•
•
•
•
•
•
•
Liquid crystal display driver with serial/
parallel conversion function
Serial transfer facilitates board design
Capable of interfacing to liquid crystal
display controllers: HD43160AH, LCTC
(HD61830), LCD II (HD44780),
LCDm{HD44790).
40 internal liquid crystal display drivers
Internal serial/parallel conversion circuits:
-20-bit shift registerx 2
-20-bit shift latchx 2
Display bias: Static to 1/5
Power supply:
-Intemallogic: + 5 V
-Liquid crystal display driver circuit:
~ lQ
~
.;';';>.;~
•
'" •
PO'" __
>- >- >-»
>-
(Top View)
-5V
•
•
•
Separation of internal logic from liquid
crystal display driver circuit increases
applicable controllers and liquid crystal
types
CMOS process
60-pin flat plastic package
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HD44100H
Block Diagram
v,
r-----------------1
I
V1. V2
I
LCD Drivers .
V3. V4
f~
Latch signal
CL1
I Shift
2Q-bit latch
DL1
CL2
---
DL2
FCS
~tching circuit
--,
20-bit bidirectional shift register
..!.~
.J...Data
,
DR1
Data
I
DR2
SHL2
Shift
~
LCD Drivers
I
SHL1
I direction
2Q-bit latch
tl[)-,. . SWitch:~9 circuit
V1. V2
V5.V6
Data
I
I
20-bit bidirectional shift register
-~.
M
direction
ii"
Data
·Slgna
~nl
I
I
I
t----~-----------i
V40
Absolute Mulmum Ratings
Item
Supply
Logie
Vee·'
Value
- 0.3 to + 7.0
V
voltage
LCD drivers
VEE U
Vee - 13.5 to Vee +·0.3
V
Symbol
Unit
Input voltage
Vr,·'
- 0.3 to Vee + 0.3
V
Input voltage
Vr:!*3
Vee + 0.3 to VEE - 0.3
V
Operating temperature
Topr
- 20 to + 75
Tstg
- 55 to + 125
'C
'C
Storage temperature
Notes:
*1
All voltage values are referred to GND.
2 Connect a protection resistor of 220 n ± 5 % to VEE power supply in series.
*3 Applies to VItO Ve.
.
*
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HD44100H
Electrical Characteristics
(Vee
=6 V
± 10 %, VIIB
=-
6V
± 10 %, GND
= 0 V, T. = Typ Max
ltam
Symbol Applicable Terminal.
Input voltage
VIH
CL1, CL2, DL1, DL2,
DR1, DR2, M, SHL 1,
0.7 Vee
Vee
Vil
SHL2, FCS
0
0.3 Vee V
DL1, DL2, DR1, DR2
Vee - 0.4-
Output voltage VOH
Min
20 to
+ 75°C)
Unit T88t Condition
V
V
IOH = - 0.4 mA
0.4
V
1.1
V
1.5
V
Vi-Vi voltage
descending
VOl
Input leakage
current
ill
CL1, CL2, DL 1, DL2,
DR1, DR2, M, SHL 1,
SHL2, FCS, NC
- 5.0
5.0
JJA
= + 0.4 mA
=0.1 rnA for one of Vi
ION =0.05 rnA for each Vi
\l;n = 0 to Vee
Vi leakage
current
IVl
*3
- 10.0
10.0
JJA
\l;n
= Vee to VEE
Power supply
current
lee
*2
1.0
mA
feL2
10
JJA
fell
= 400 kHz
= 1 kHz
VOL
Notes: *1
*1
V02
lEe
Vi-Vj (Vi
IOl
ION
= 1 to 6, j = 1 to 40) equivalent circuit
Vi~
III
R2
'-v-'
Power
8witch
'-v-'
Data
switch
y'
J
R1
R2
= 1 kO max.
= 10kOmax.
Input/output current is excluded; when input is at the intermediate level with CMOS,
excessive current flows through the input circuit to the power supply. To avoid this, input
level must be fixed at high or low.
Output V1 to V40 open.
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79
HD44100H
Timing Characteristics
(Vee
= 5 V ± 10 %, VEE = -
5V
± 10 %, GND = 0 V, T. = - 20 to + 75°C)
Applicable Terminals
fCl
CL2
Clock
high level
tcwH
CL1, CL2
800
ns
width
Low level
tCWl
CL2
800
ns
Data set-up time
tsu
DL1, DL2, DR1, DR2,
FLM
300
ns
Clock set-up time
tSl
CL1, CL2
500
ns
(CL2-CL1 )
Clock set-up time
tlS
CL1, CL2
500
ns
(CL1-CL2)
Data delay time
tpd
DL1, DL2, DR1, DR2
500
ns
Cl = 15 pF
Clock rise/fall time let
CL1, CL2
200
ns
Data hold time
DL1, DL2, DR1, DR2,
FLM
Item
tOH
Min
Typ Mex
Symbol
Data shift
frequency
400
300
Unit
Teat Condition
kHz
ns
\~----tCWL----l
CL2
t ct
1---------tDH
Data in
(oLI. oL2. oRl, _---1
DR2) _ _-'
---+-----001
I o - - - - - t SL-------H
Io------t~---~
Data out
(oLI, DL2. oRI. oR2)
-----'
CLI
~-----tcWH------~
FLM
VIH
VIL
Figure 1 Timing Waveform
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HD44100H
Terminal Function
Table 1 Functional Description of Terminals
Signal
Name
Number
of Linea
Input/
Connected to
Function
Vee
power supply
Power supply for logical circuit
GND
Power supply
OV
VEE
Power supply
Power supply for liquid crystal display drive
Output
YI-Y20
20
Output
Liquid crystal
Liquid crystal driver oulput (Channell)
Y21-Y40
20
Output
Liquid crystal
Liquid crystal driveJAlutput (Channel 2)
VI, V2
2
Input
Power supply
Power supply for"liquid crystal display drive (Select level)
V3, V4
2
Input
Power supply
Power supply for liquid crystal display drive (Non-select
level for channell)
V5, V6
2
Input
Power supply
Power supply for liquid crystal display drive (Non-select
level for channel 2)
Input
Vee or GND
Selection of the shift direction of channel 1 shift register
SHL1
SHL2
Input
Vee or GND
SHLl
DLl
Vee
Out
DRl
In
GND
In
Out
Selection of the shift direction of channel 2 shift register
SHL2
DL2
Vee
Out
DR2
In
GND
In
Out
DL1,DR12
Input/
output
Controller
or HD44100H
Data input/output of channel 1 shift register
DL2,DR2 2
Input/
output
Controller
or HD44100H
Data input/output of channel 2 shift register
M
Input
Controller
Alternated signal for liquid crystal driver output
CL1
Input
Controller
Latch signal for channel 1 (~)
1
Used for channel 2 when FCS is GND
CL2
Input
Controller
Shift signal for channel 1 (~)
1
Used for channel 2 when FCS is GND
FCS
Input
Vee or GND
Mode select signal of channel 2. FCS signal exchanges the
latch signal and the shift signal of channel 2 and inverts M
for channel 2. Thus, this signal exchanges the function of
channel 2.
*
*
Channel 2
FCS Level
Latch signal
Shift signal
M Polarity Function
Vee
CL2
---.r
CL1
---.1
M
For common drive
GND
CL1
~
CL2
~
M
For segment drive
Don't connect any wires to this terminal.
NC
Notes:
*1
-1 and ~ indicate the latches at rise and fall
times, respectively.
*2 The output level relationship between channel 1 and channel 2 based on the FCS signal
level is as follows:
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81
HD44100H
Output Level
FCB
Data
M
Vee
(Select)
0
(1 )
0
(Non-select)
Channel 1 (Y1-Y 20)
Channel 2 (YZ1-Y40)
V,
V2
V2
V,
1
V3
Va
0
V4
V5
1
V,
V,
GND
(Select)
0
V2
V2
(0)
0
1
V3
V5
(Non-select)
0
V4
Va
1 and 0 indicate high and low levels. respectively.
Applications
Segment Driver
When the HD44100H is used as a segment
driver, FCS is set to GND to transfer display
data with the timing shown in figure 2. In this
7
(FLM)
case, both channel 1 and channel 2 shift data
at the fall of CL2 and latch it at the fall of CLI.
Va and Vs, V4 and V6 of the liquid crystal
display driver power supply are short-circuited, respectively.
81234567812
____~r_l~____________~____~r_l~___
M
CL1
Output of
latch
(Y,-Y40)
------------- ....---
M
CL1
________~rl~___
Lf1SLfl..JlS"-----Lf1SLfl..JlS"
Shift
CL2
DL1/DR1 ~-----~
DL2/DR2~-----~
Figure 2
Segment Data Waveforms (A Type Waveforms, 1/8 Duty Cycle)
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HD44100H
display data with the timing shown in figure
3.
In this case, channel 2 shifts data at the rise of
CLl and latches it at the rise of CL2. Channel
1 shifts and latches as shown in figure 2.
Common Driver
In this case, channel 1 is used as a segment
driver and channel 2 as common driver.
When channel 2 of HD44l00H is used as
common driver, FCS is set to Vcc to transfer
8
r.=.r:.'
2
. II
DL2/DR2(FLM~ . : r
3
4
5
6
7
8
1
2
11L.._ __
: Shift'+j-----------'
CL 1
Y21
(Y~)
Y22
(Y3S)
I jJ__ ~ I
I I I
Non-select
/F
r-lL.._________
~~
r
I
I
i
to
Y28
:
(Y33)
:
Select
~
Non-select
L ---L
Select
--------11
Non-select
Select
n
Select
------n
Select
SelectL..---
Enlarged view \
\
DL2/DR2(FLM) ' M
CL1
CL2
Figure 3
Common Data Waveforms (A Type Waveforms of Channel 2, 1/8 Duty
Cycle)
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83
HD44100H
Both Channel 1 and Channel 2 Used as
Common Drivers (FCS = GND)
the fall of CL2 and latched at the fall of CL1.
The frequency of CLl becomes the frame
frequency of the liquid crystal display driver.
The signal applied terminal M must have
twice the frequency of CLl and be synchronized at the fall of CLl. The power supply for
liquid crystal display driver is used by shortcircuiting Vl, V4 and V6, and V2, V3, and V5
respectively.
One of the liquid crystal display driver output
terminals can be used for a common output.
In this case, FCS is set to GND and data is
transferred so that 0 can be always latched in
the latch corresponding to the liquid crystal
display driver output terminal used as the
common output. If the latch signal corresponding to the segment output is 1, the
segments of LCD light. They also light for
common side = 1, and segment side O.
When both of channel 1 and channel 2 of
HD44100H are used common drivers, FCS is
set to GND and the signals (CL1, CL2, FLM)
from the controller are connected as shown in
figure 4.
In this case, connection of the liquid crystal
display driver power supply is different from
that of segment driver, so refer to figure 4.
•
Vl, V2: Select level of segment and common
•
V3, V4: Non-select level of segment
•
V5, V6: Non-select level of common
Static Drive
When the HD44l00H is used in the. static
drive method (figure 5), data is transferred at
-
Cll
V3 ----------+t-+--,
I
II
HD44100H
Segment
driver
!
Y1 -Y40
HD44l00H
Segment
driver
>~:>'->-5';:
>~:>'->-5';:
1 I I I I
1 I I I L
~] ~ ~61----------~-------+------~-~------
~ g'C
II>
Figure 4
Connection When Both Channels Are Common Drivers
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HD44100H
First
Second
Tenth
figure figure - - - - - - - - - - - - - - - - - - - - - - - - - - - - - figure
n
n
9
I... 0
COM signal
CMOS
I~e
~
l ~ inverter
r=
D
00-
FCS
SHL,
SHL2
.:i
U
DR,
HD44100H
DL2
DR2
VEE
2
~
U
....
N
M
»»
I I
CL,
..,-- 40 -r-SEG4,-SE Gao
40 ---r-SEG,-SEG40
Y,-Y40
DL,
~
fu
I--
~
FCS
SHL,
SHL2
-"
.
>'" >
dd~
I
I
CL2
Y,-Y40
DR,
HD44100H
DR2
DL,
DL2
VEE
_
tJ
I--
N
»
M'ltlOU)
»»
I
M
Vcc
GND
Figure 5
Static Drive Connection
Timing Chart of Input Waveforms
1
2
3
78
79
80
CL2~""" ~
D
XSEG8<)(SEG7~SEG78 .•.•••.• ~
(Shift Clock)
(Display Data)
~l:onO:off
CL, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ (Latch Clock)
Notes:
1. Input square waves of 50% duty cycle (about
30-500 Hz) to M. The frequency depends
on the specifications of LCD panels.
2. The drive waveforms corresponding to the
new displayed data are output at the fall of
CL 1 . Therefore, when the alternating signal
M and CL 1 do not fall synchronously, DC
elements are produced on the LCD drive
waveforms. These DC elements may shorten
the life span of the LCD, if the displayed data
frequently changes (e.g. display of hours,
minutes, and seconds of a clock). To avoid
this, have CL 1 fall synchronously with the
one edge of M.
3. In this example, the CMOS inverter is used as
a COM signal driver in consideration of the
large display area. (The load capacitance on
COM is large because it is common to all the
displayed segments.)
Usually, one of the H 0441 OOH outputs can
be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in
that case.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
85
HD44100H
39
CO~ ,
40
CL2~________~
LCD
/').
V,
I
V2 -V40
SHL',2
HD44100H
I1r
D~-----~
\.
y
Data transformed
to V2 to V40
)
\
Data 0 corresponding to
V, (COM signal)
IL
CL,
HITACHI
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Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005~1819· (415) 589-8300
HD66100F-----(LCD Driver with SO-Channel Outputs)
The HD66100 description segment driver
with 80 LCD drive circuits is the improved
version of the no longer current HD44100H
LCD driver with 40 circuits.
It is composed of a shift register, an 80-bit
latch circuit, and 80 LCD drive circuits. Its
interface is compatible with the HD44100H.
It reduces the number of LSI's and lowers the
cost of an LCD module.
Pin Arrangement
;;;f;I~~:!l:l!P;~IIt~.~;:I~:~':5l
»
»»»»»»»»»
,~. i ~ i ~ • • ~ ; • • • • • • • " " :;;.,
~
,
~
~
~
~
~
~
~
~
•
•
•
•
•
•
.
...
,
...
.
•
LCD driver with serial/parallel converting
function
Interface compatible with the HD44100H;
connectable with HD43160AH, HD61830,
HD61830B, LCD-U (HD44780), LCD-Ul
(HD44790)
Internal output circuits for LCD drive: 80
Internal serial/parallel converting circuits:
-80-bit bidirectional shift register
-80-bit latch circuit
Power supply
-Internal logic circuit: + 5 V ± 10%
-LCD drive circuit: 3.0 V to 6.0 V
CMOS process
100-pin plastic OFP (FP-l00)
v"
~
~
R.
~
~
~
~
~
n
~
n
~
"
~
:t= ~:
~: ~~
Features
•
.JlJLJlJLJL
v,.
~
g
..
~
Yl1
14
171=
Y 16
F 16
v"
••
1141 1=
Vv....
Y16F='8
~::F::
~
Yll
~
~
~
~
~
~
~
~
~
V,
:~~:
g
....
..
.
•
~
81
Y70
.,
~
...
20
M
..
..
v
30
~
~
~
~
~
"
~
51
Yeo
~
~
;;;f;I::I;Jj:!l:S:::;IlIl!:i;*~:I!f;!;:':S
..JUL
~»»~d~~dog~~~~~~~~
(FP-80A)
(Top View)
Comparison with HD44100H
Table 1 shows the main differences between
HD66100 and HD44100H.
Table 1
Comparison of HD66100 and
HD44100H
HD861 00
LCD Drive Outputs 80 x 1 Channel
Supply Voltage
3 to 6 V
for LCD Drive
Circuits
. Multiplexing
Static to 1/16
Duty Ratio
duty
Package
100-pin flat
plastic package
HD44100H
20 x 2 channels
4.5 to 11 V
static to 1/32
duty
60-pin flat
plastic package
HITACHI
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87
HD66100F
Pin Description
Vee. GND. VEE: Vcc supplies power to the
internal logic circuit. GND is the logic and
drive ground. VEE supplies power to the LCD
drive circuit.
V1. Vz. V3. and V4: VI to V4 supply power for
driving an LCD (figure 2).
CL1: HD66100 latches data at the negative
edge of CLl.
CL2: HD66100 receives shift data at the negative edge of CL2.
01: Inputs data to the shift register.
DO: Output data from the shift register.
SHL: Selects a shift direction of serial data.
When the serial data is input in order of Dl, D2,
... , 079, DBO, the relation between the data and
the output Y is shown in table 3.
YI-Yeo: Each Y outputs one of the four voltage
levels-VI, Vz, V3, or V4-according to the combination of M and display data (figure 2).
M: Changes LCD drive outputs to AC.
NC: Do not connect any wire to these terminals.
Table 2 Pin Function
Table 3
SymbolPin No.
Vee
GNO
Vee
Pin Name
46
36
31
Relation Between SHL and
Data Output
I/O
Vee
SHL
V1
Vz
V3 ••••••
V79
Ground
High
01
02
03 ......
079 080
Low
080
079
078 .....
02
Veo
Vee
32
33
V2
34
V3
35
V4
CL1
37
40
CL2
44
M
01
41
DO
42
SHL
39
Y1-Yao 1-30,51-100
NC
38.43.45.47-50
V1
V1
01
V2
V3
V4
Clock 1
Clock 2
M
Date In
Date Out
Shift Left
Y1-Yao
I
I
0
I
0
No Connection
M~
I
0
0
y output I"
level
V,
.. I... V3 ..I... v ..I.. V ..I
2
4
When used as a common driver
Figure 1 Selection of LCD Drive Output
==::
~
.
-----V4
-----V2
V,. V2 : Selected level
V3 , V4 :
Non-selected level
Figure 2 Power Supply for Driving an LCD
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66100F
Block Functions
LCD Drive Circuits
Bidirectional Shift Reigster
Select one of four levels of voltage V 1, V2, V3,
and V4 for driving a LCD and transfer it to the
output terminals according to the combination of M and the data in the latch circuit.
Shifts the serial data at the fall of CL2 and
transfers the output of each bit of the register
to the latch circuit. When SHL = GND, the
data input from DI shifts from bit 1 to bit 80 in
order of entry. On the other hand, when SHL
= Vee, the data shifts from bit 80 to bit-l. In
both cases, the data of the last bit of the
register is latched to be output from DO at
the rise of CL2.
Latch Circuit
Latches the data input from the bidirectional
shift register at the fall of CLl and transfer its
outputs to the ,LCD drive circuits.
SHL=GND
LCD drive outputs
Yl Y2
Y79 Y80
Latch circuit
Shift register
----I
DI
DO----------------------~
SHL=Vcc
LCD drive outputs
YI Y2
CLI---o-f
Y79 Y80
Latch circuit
CL2---~~r-----~S~h~ift~r=eg=i.~te~r----r~
DI---~------------------~
DO
Figure 3 Relation between SHL and the Shift Direction
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
89
HD66100F
. . . .. ... . . . . . .. .
LCD drive outputs
Yl Y2
'1'1
M
(alter nating signal)
LCD drive circuit
Y79 Y~O
1"1'"
. . . . . . ... . . . . .. .
1'1'1
. .. . . .. .. . . .. . ..1"1"J
DI
(in put data)
. . . .. . . . . . . . . . . .1"1"1
~1.:i'I'1
V~, v~,
V4
LCDd rive circuit)
Level shifter
'1'J
C Ll
(J. tch clock)
VI,
(power supply for
Latch circuit
Bidirectional shift register
~J
1"1"1::'
.~
-
-
1"
r--
Vee
I--GND
I-- VEE
DO
(output data)
j
...l
I
'T
C L2
( shift clock)
SHL
(selects
a shift direction)
Figure 4
Block Diagram
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-.1819· (415) 589-8300
HD66100F
Primary Operations
Shifting Data
The input data DI shifts at the fall of CL2 and
the data delayed 80 bits by the shift register
is output from the DO terminal. The output of
DO changes synchronously with the rise of
CL2. This operation is completely unaffected
by the latch clock CL1.
Latching Data
The data of the shift register is latched at the
negative edge of the latch clock CL1. Thus,
the outputs Y1-Yao change synchronously
with the fall of CL1.
Switching Data Shift Direction
When the shift direction switching signal
SHL is connected with GND, the data 080,
immediately before the negative edge of CL1,
is output from the output terminal Y1. When
SHL is connected with Vcc, it is output from
Yeo.
Shift dock eL2
Input data
Output data
DI
DO
Figure 5 Timing of Receiving and Outputting Data
Shift clock eL2
Latch clock
.~ ............~
____rL
eLl
--'[
Outputs VI" Y80
Figure 6 Timing of Latching Data
HITACHI
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91
HD66100F
SHL=GND
JULrL. . . . . . . . . . . . .SLfUl..-
Shift clock
CL2
Input data
OJ
~
Dl
02
Latch clock
CLI
- - - -.........................~
YI
Outputs
to
Y80
.........................
..........................
~
-----.: ::
.••...•. ..•••.•.....•.•..•.•.•.•.•••••.
- - - - -.........................
D19
080
-----'~
---~V-O;-
- -_____......................... _ _ _ _.....A...:.:...-
SHL=Vcc
YI
Outputs
to
Y80
-----
..................................................
----~
-----:::::::::::::::::::::::::----~
Figure 7 SHL and Waveforms of Data Shift
HITACHI
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Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
HD66100F
Absolute Maximum Ratings
Item
Supply
Voltage
Logic Circuits
Symbol
Ratings
Unit
Note
Vee
-0.3 to +7.0
V
*1
-0.3 to +7.0
V
LCD Drive Circuits Vee-VEE
Input Voltage (1)
V,.,
-0.3 to Vee + 0.3
V
*1
Input Voltage (2)
Vr2
Vee + 0.3 to ~E - 0.3
V
*2
Operation Temperature
Topr
+20 to +75
'C
Storage Temperature
Tstg
-55 to +125
'C
*1 A
reference point is GND (= 0 VI
*2 Applies to V, -V4.
Note: If used beyond the absolute maximum ratings, LSls may be permanently destroyed. It is best to
use them at the electrical characteristics for normal operations. If they are not used at these
conditions, it may affect the reliability. of the device.
HITACHI
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93
HD66100F
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, Vee-VEE=3.0 to 6.0 V, GND
Item
Symbol
Terminals Min.
Input. High Voltage
VIH
CL1, Cl2
Input low Voltage
Typ.
0.8 x Vce-
Vil
M, 01, SHl 0
Output High Voltage
VOH
DO
Output low Voltage
VOL
On Resistance
Vi-Vj
RON'
-20 to +75'C)
Max.
Unit
Vcc
V
Input leakage Current III
Test condition
Noes
0.2 x VceV
= -0.4 mA
= +0.4 mA
ION = 0.1 mA to
V
10H
0.4
V
10l
11
kO
V,-V4
30
kO
ION = 0.05 mA to
each Y terminal
CL1, Cl2, -5.0
M, 01, SHl
-5.0
V,-V4
5.0
~A
\l;n
5.0
~A
Output Y,-Yso open
Vin = Vce to VEE
Vcc-0.4 -
Y,-Yso
RON2
C
= 0 V, T. =
one Y terminal
= 0 V to Vce
Vi leakage Current
Ivl
Current Dissipation
IGND
2.0
mA
fCL2
lEE
0.1
mA
fCLl
= 1.0 MHz
= 2.5 kHz
*1
*1 Input/output currents are excluded; when an input is at the intermediate level in CMOS, excessive
current flows from the power supply through the input circuit.
To avoid this, VIH and Vil must be fixed at Vce and GND level respectively.
AC Characteristics
(Vee = 5 V ± 10%, Vee-VEE = 3.0 to 6.0 V, GND = 0 V, T. = -20 to +75'C)
Item
Symbol
Terminals
Data Shift Frequency
fCl
Cl2
Clock High level Width
Min.
Typ.
Max.
Unit
Note
MHz
tCWH
Cll,CL2
450
ns
Clock low level Width
tCWl
Cl2
450
ns
Data Set-Up Time
fsu
01
100
ns
200
ns
*1
Clock Set-Up Time (2)
tsl
tLS
Cl2
CL1
200
*2
Output Delay Time
ns
ns
Clock Set-Up Time (1)
tpd
DO
Data Hold Time
tOH
01
Clock Rise/Fall Time
fcr
CL1 ,Cl2
250
100
*3
ns
50
ns
* 1 Set-up time from the fall
of CL2 to that of CL 1 .
* 2 Set-up time from the fall CL 1 to that of CL2.
*3 Test terminal
CL (Load capacitance on outputs) = 30pF
(I ncluding jig capacitance)
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66100F
tCWL
CL2
'DR
DI
.S!
DO
CLl
tCWH
Figure 8 Timing Chart of HD66100F
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
95
HD66100F
Typical Applications
Connection with the. LCD Controller HD44780
COMlCOMl6
SEGl-
SEG.o
0
..............
~
{
40
01
SHL
I~
y, y..
DO
f0-
HD66100F
II "
eLl
M
Ol
SHL
I~
DOf-----
YI-¥SO
HD66100F
R
ad:2~~~>:>~>
aa2~~~;»»
CL2
.....-.......
LCD
I
1111
I
R
-------
Vee
HD44780
R
R
y,
y.
y,
V.
y.
eND
.w-
~
GND
R
ItContrast
'--- -v
Figure 9 Example of Connection (1/16 duty cycle, 1/5 bias)
...............
COMl-~
COMS
SEGl-
{
SEG.O
0
.0
01
SHL
CLl
Cl..2
I~
oof-:-
y, y..
DI
SHL
HD66100F
I~
00_---
YI-¥IO
HD66100F
aa2~~~»»
aa:E~~~»»
! III
1111
I
M
Vee
y,
y.
HD44780
..............
LCD
I
R
R
-------
I
y,
v.
y.
eND
.Ir
Iri~;o
R
ntrast
-v
For LcOPS;fve]
GND
--~.;:>
aa::a~~~>==>:>
III
III
Vee
R
v,
v.
V.
H00790
vee:
J
II
J;-e
GND
R
R
( wer
-v
t'r LCD'PJ':rve)
8
Figure 11 Example of Connectlon (1/3 duty cycle, 1/3 bias)
Static DrIve
First
figure
COM signal
4~
~~.~S.r
Secoud
fiture.
n
n C
I"
D
,.--
•
•
••
Tenth
fipre
n
C
{~
DI
Y,-Y..
SHL
HD66100F
SEGl- SEGBO
DO
:::l~::S~~:=»»
uu
::;; ,,:So
I
CLI
CL2
M
Vee
GND
Figure 12 Example of Connection (SO-segment display)
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97
HD66100F
• Timing Chert of Input Waveform.
78
79
80
Shift clock CL2
Inpuldala
DI
Latch clock CLl
~
••••••••
~
------------------~
Figure 13 Timing Chart of Input Waveforms
Notes:
1. Input square waves of 50% duty cycle (about
30-500Hz) to M. The frequency depends on
the specifications of LCD panels.
2. The drive waveforms corresponding to the
new displayed data are output at the fall of
CL 1 . Therefore, when the alternating signal M
and CL1 do not fall synchronol!Sly, DC elements are produced on the LCD drive
waveforms. These DC elements may shorten
the life span of the LCD, if the displayed data
frequently changes (e.g. display of hours,
minutes, and seconds of a clock). To avoid
this, make CL 1 fall synchronously with the
one edge of M.
3. In this example, the CMOS inverter is used as
a COM signal driver in consideration of the
large display area. (The load capacitance on
COM is large because it is common to all the
displayed segments.)
Usually, one of the HD66100F outputs can
be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in
that cilse.
Figure 14 Example of Connection
---'LrU ........ ~
'"
CU
DI
CLI
x=x= ....
80
~
------~-----~
Figure 16 Timing Chart (wben Ylls used as a COM signal)
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza .2000SierraPoint,Pkwy.• Brisbane, CA 94005-1819 ,. (415) 589-8300
LCD CONTROLLERIDRIVER LSI DATA BOOK
Section Four
Character Display
LCD Controller/Display
HITACHI
-
--
-
----------
_.-----_ ..-
-
-
---~~-----------
II
HD43160AH - - - - - - For Maintenance Only
(Controller with Built in
Character Generator)
Display Controller and Character
Generator for Dot Matrix Liquid
Crystal Display System
•
The HD43160AH receives character data
written in ASC II code or JIS code from a
microcomputer and stores them in its RAM
which has 80 words capacity.
Number Of Characters
The HD43160AH converts these data into a
serial character pattern, then transfers them
to LCD drivers.
•
160 characters in internal character generator (ROM)
(Max 256 characters in external ROM)
4, 8, 16, 24, 32, 40, 64, or 80 characters in 1
or 2 lines
Font
•
5 x 7
+
Cursor or 5 x 11
+ Cursor
It also generates other control signals for the
LCD. The HD44100H LCD driver can be combined with this controller.
Oth~r Function Controlled By
Micr;ocomputer
Display Characters Types
•
•
•
•
Alphanumeric characters: A-Z, a-z,
&, etc.
Japanese characters (katakana)
@,
#, %,
•
•
Display clear
Cursor onloff
Cursor position preset (character position)
Cursor return
Block Diagram\
eso
eNO
eNl
eSl
eS2
eS3
eURS
ROMS
RSO
M
~----~-------+--FlM
R/W
ell
counter
ROM
DBO
o
to
DB6
DB7
RST -
Busy Flag
TEST-
AbsolutEl Maximum Ratings
Item
Symbol
Supply voltage
Input voltage
Operating temperature
Storage temperature
Vee
Value
, -0.3 to +7.0
Topr
Tstg
-0.3 to Vee + 0.3
-20 to +75
-55 to +125
Unit
V
V
'c
'c
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD43160AH
Electrical Characteristics (Vee
Item
Symbol
I~ut
VIH
(
voltage
l compatible)
Vil
Input voltage
VIHC
VllC
Output voltall:'
(TTL compatl Ie)
VOH
typ
Terminal No.
min
CSO-CS3, E, R/W, 2.0
DBO-DB7, RSO
0
OSC1, TEST, RST, FNTS, 0.7 Vcc
CURS, DlN, ROMS,
CNO-CN2, 0,-05 0
FlM, M, D, Cl1, Cl2, Vcc-l.0
XO-X7, YO-Y3
Input leak current
III
All inputs
Output leak current
!Lo
DB7
V
-
-5
V
-10
= -0.205 mA
= 1.6 mA
hoad = ±0.4 mA
V
IOH
V
IOl
V
1.0
V
5
pA
10
pA
fcp,
130
192
250
kHz
RI = 200 kO ±2%, 5
x 7 + Cursor
fcP2
200
288
375
kHz
RI = 130kO ±2%, 5
x 11 + Cursor
10
20
pA
10
mW
frequency
CSO-CS3, RSO, RNI, 2
·DBO-DB7
Input pull up current Ipl
*
Vcc
0.4
VOlC
Power dissipation
Unit T8IIt condition
V
0.3 Vcc V
VOHC
Oscillation
max
Vcc
0.8
2.4
DB7
VOL
Output voltage
= 5 V ± 5%, GND = 0 V, Ta = -20 to+75°C)
Pr
*
Yin
= OV
Ta = 25'C, fcp =
400 kHz
(external clock)
Input/output current is excluded. When an input is at the intermediate level in CMOS, excessive
current flows through the input circuit to the power supply. To avoid this, input level must be fixed
at high or low, CSO-CS3, ASO, A/W, OBO-OB7.
Pin Arrangement
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
'-eup.
ose
Input
Output
GND (-)
X4
X3
X2
X1
XO
N.C.
N.C.
N.C.
CURS
FNTS
DlN
CNO
CN1
CN2
Cl2
CL1
M
Pin
No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
'-eup.
ose
Input
OSC1
OSC2
RST
TEST
E
Vcc(+)
R/W
RSO
CSO
CSl
CS2
CS3
DBO
DBl
DB2
Output
0
FIM
t/>A
Pin
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Powweup.
ose
Input
Output
DB3
DB4
DB5
DB6
DB7
ROMS
05
04
03
DB7
02
01
Y3
Y2
Yl
YO
X7
X6
X5
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005·1819- (415) 589-8300
101
(
HD43160AH
Pin Function
Pin
,name
Vee
GND
CNO
CN1
CN2
N~of
tarminala
Connected to
2
Power supply
Function
+ 5 V ± 10% Power supply
OV
3
GND or Vee
Total displayed character number select
No. 4
8
16 24 32 40 64
CNO GND Vcc GND Vcc GND Vcc GND
CN1 GND GND Vee Vee GND GND Vec
CN2 GND GND GND GND Vee Vee Vee
CURS
GND or Vee
DlN
GND or Vee
FNTS
GND or Vee
RST
TEST
E
Vee
GND
MPU
R/W
MPU
CSO
CS1
CS2
CS3
RSO
4
DBO
to
DB7
8
0
Cl2
Cl1
I/O
80
Vee
Vce
Vee
Cursor select
Vee: 5 dots • • • • •
GND: 1 dot
Display line number select
Vee: 2 lines
GND: 1 line
Font select
Vee: 5 x 11 + Cursor
GND: 5 x 7 + Cursor
•
Only for test. Normally Vee.
Only for test. Normally GND.
Strobe signal
Write mode: The HD43160AH latches the data on DBODB7 at the falling edge of this signal
Read mode: Busy/Ready signal is active on DB7 while this
signal is high
(low: Ready, High: Busy)
Read/Write signal
l: HD43160AH gets the data from MPU
H: MPU gets the Busy/Ready signal from HD43160AH
Chip select
When all of CSO-CS3 are 'H', HD43160AH is selected.
MPU
MPU
MPU
I
I/O
(DB7)
HD44100H
HD44100H
HD44100H
0
0
0
Register select
HD43160AH has 2 registers. One is for character code and
another is for instruction code. Each register latches the data
on DBO-DB7 at the falling edge of E, when CSO-CS3 are
high and R/W is low.
High: Character code register is selected
low: Instruction code register is selected
Data bus
Inputs for character code and instruction code from MPU
Output for Busy/Ready flag (DB7)
Serial dot data of characters for LCD drivers
Dot data shift signal for LCD drivers
Dot data latch signal for LCD drivers
HITACHI
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Hitachi America,ltd.· Hitachi Plaza· 2000 Sierra Point PkWy.· Brisbane, CA 94005-1819· (415) 589-8300
HD43160AH
Pin
name
M
FLM
XO
to
X7
Number of
tarminala
Connected to
I/O
1
1
HD44100H
HD44100H
ROM
0
0
0
8
Function
Alternate signal for LCD drivers
Signal for common plates scanning
Character code outputs for external character generator (for
ext ROM)
X7: MSB
ex: character 'A'
XO: LSB
T= High
'0'- Low
Character row code for external character generator
IMSBI
o
YO
Y1
Y2
Y3
4
ROM
0
11010101010
5 x 7
+
Cursor
.""
I LSB I
1
5 x 11
+
Cursor
Y~Y2YIYlt
• A"
010305
02 04
t/JA
ROM
01
to
05
ROMS
5
OSC1
OSC2
2
NC
3
o 0 1
o 1 0
0 0 1 1
1 0
o 1 0 1
o 1 1
o 1 1 1
1 0 0 0
1001
1 0 1
1 0 1 1
"j"
0
Clock signal for external character generator (dynamic ROM
etc.) if necessary
Dot data inputs from external character generator
1 (High): On
o (Low): Off
Select internal or external ROM
High: External ROM
Low: Internal ROM
(I)
(0)
Oscillator
ROM
GND or Vce
5 x 7 + Cursor: Rf = 200 kO (typ)
5 x 11 + Cursor: Rf = 130 kO (typ)
Don't connect any signal to these terminals
HITACHI
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103
HD43160AH
Character Dot Patterns
5X7
The bottom lines of the English small characters "g, i, p, q, y," are on the cursor line (Figure
1).
Only the English small character "g, j, p, q, y,"
are displayed as below. The others are the
same as for 5 x 7 (Figure 2).,
Cursor 5 dots: •••••
ldot:
5 X 11
•
The cursor is displayed on the 8th or 12th line.
.
, .,:. ,
# $ l.:-:
Character code lower 4 bits (hexadecimal)
9
A
4
5
6
7
8
:+: + , - • .'
..
'
;a .."
a= ... .., l::;a • ,
• ...,.• - • .•.~1 1 ......
.;) 4 ._1 f.:, I· c· _. •
-@RB I:: [) EF 6 HI ...T~.'••• L tl1 ~~ I)
.
I."I .....
7 [ ¥ ] ."..
S F' Q Fe: c T IJ 1...1IJ.I
-'
•
•
...
0
2
1
2
I
II
•
3
•
•••
B
C
0
E
•• ••
I.
••
•
••
3
F
.)
I_I
~
764
E
'0
--
''0
I .."
I··'
5
;S
..
·3 1::1 1:- c.~ t-:-· f· -I;' ~"I 1 ..1 ~•• 1 1'1 t1 I-I
Iii
- ·1I· -a. ..;.. +~
.•
••••
.....
t) 1:;1 .:. t. I..~ 1.1.1 •••• I...J z • I .1 • •
8Iii
r
::;t
~A
·1·
J ••• • • 7
r::t ::t: ::at t.a .::L :I I !.I
a
.f!
~6
r·
.. 7
'0
.t:
(J
-
.,- :r
,
..,
-'I
=
..
:::t :tl =t= ..- • :J - ..... ~ ':.J
.~
- ..ya. ::it •.1 1·1 t: -, ..•••.. ;t;.:. -:,•
.. =f- III•• T ~. +
•
a
••1
-I1
o -..
•••• =e 1-' .1 3 • •• III l.·· DIJ
-
B-
C
Y ·1··
-
"
.p]
- ..,
Figure 1
-
.1
5 X 7 Characters
•
9 .JP I~ !:I
Figure 2
Special 5 X 11 Characters
HITACHI
104
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819 - (415) 589-8300
HD43160AH
Application
Setting Up
1.
2.
3.
4.
These terminals should be connected to Vee
or GND according to the LCD display system.
RST and TEST should be connected to Vee
and GND respectively.
Total character number: CNO-CN2
Cursor pattern: CURS
Display line number: DLN
Font: FNTS
Interface to the Controller
1. Example 1 Interface to HD6800
In this example (Figure 3), the addresses of
HD43160AH in the address area of the
HD6800 microcomputer are:
#'E"''''
(R/W=O)
Instruction code register
Character code register
#'F"'''' ""
(R/W=O)
#'E*"'·' or #'F"'''' (R/W=l)
Busy flag
"': don't care
#": hexadecimal
HD 8800 (MPU)
AB15
eS3
AB14
AB13
VMA
eS2
eS1
AB12
RSO
R/W
,,2
R/W
eso
E
DBO
DBO
DB1
DB1
DB2
DB2
DB3
DB3
DB4
DB4
DB5
DB5
DB6
DB6
DB7
DB7
Figure 3
HD43180AH
HD6800 Interface
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105
HD43160AH
2. Example of display program
Read Busy flag
from 1* 'E''''
or # 'F*n,
Check Busy or Ready
Y: Busy
Figure 4
Display Program Example
3. Time length of Busy
write Inst. or Charact. code
E
-~I.....--------"'---
Busy
(Internal)
-t=Tb~Y
Operation start
__~~-'-d
operation en
T busy
min
Max
400
410
Display clear
--r,;;;-
Other function
--r,;;;-
10
Unit
--r,;;;-
s
20
--r,;;;-
Figure 5
HD43160AH begins the operation from the
rising edge of E (Figure 5).
Instruction code register and character code
s
Busy timing
register latch the data on DBO-DB7 at the
falling edge ()f E.
HITACHI
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HD43160AH
4. Timing chart
Write sequence
Read sequence
(MPU ....HD43160AH)
(MPU .... HD43160AH)
,
tevc
I-
I
PWEL
,-
E
to
eS3
RSO
R/W
-I-
tcvc
PWEH
I
-
L
: [
ItDDWI
"
E
tH
-1'"1--1-
I,.....-_.....;,...._ _-----.....!.,
II
J
eso
to
eS3
. RSO
I
I
J
~----Jr-
t
Read
l,,--_Wri_te
I
DBO
to
DB7
.. I
-I
1~1,,...----...,,
I _ tAS
eso
I
____ =:ct.
Inst.
Figure 6
DB7
~
~
I
HDf$800 Interface Timing
5. Timing characteristics
Item
Cycle time of E
Pulse width of E
Symbol
Min
tcyc
1.0
0.45
0.45
140
High level
FWEH
Low level
FWEL
Set up time of CS
Write
tAS
Data delay time
Write
toow
Read
toOR
Hold time
tH
Typ
Max
pS
25
pS
pS
ns
225
300
10
Unit
ns
ns
ns
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
107
HD43160~H
6. EXample 2 Interlace to 8085A (Intel)
51
101M
RD
WR
A15
A14
A13
A12
8085A
R/W
CS3
E
-r
-
CS2
CS1
CSO
RSO
--L»- 0
(MPU)
ALE
...
,...~
...
a
ClK
ClR
ClK ----b"
READY
ADO
r
HD43160AH
Q
Q~D
°1
ClK
1
DBO
to
to
DB7
AD7
Figure 7
BOB5A Interface
7. Timing chart
.,
ClK
~
I
j
I
I
~
101M. S1
A12 A15
,--
ALE
-
\
,
READY
I
1 "-
r\
\
T1
T2
Figure B
Pulse widths of RD and WR signals of the
8085A are 400 ns min, while the pulse width
of the E signal of the HD43160AH is 450 ns
TWAIT
T4
BOB5A Timing
min (Figure 8).
Therefore, in this example, RD and WR signal
pulse widths are widened by the TWAlT cycle.
HITACHI
108
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
HD43160AH
Display Commands
Display Control Instructions
Operation: The cursor moves to the Nth
(nth, mth) digit.
N ;;;; the total character number
n, m ;;;; 1/2 total character
number
ex 1: 1 line
Set the cursor at digit 55. The
code is 10110110.
ex 2: 2 lines
Set the cursor at digit 35 of
upper or lower line.
The code is 10100010 (upper).
11100010 (lower).
These instructions should be written into the
instruction register of HD43160AH by the
microcomputer. (RSO = Low, R/W = Low)
1. Display clear
Code:
MSB
LSB
I0 I0 I0 I0 I0 I0 I0
11
I
Operation: The screen is cleared and the
cursor returns to the 1st digit.
Display Character Command
2. Cursor return
MSB
Code:
LSB
I0 I0 I0 I0 I0 I0
11
I0 I
Operation: The cursor returns to the 1st
digit and the characters being
displayed do not change.
When the character code is written into the
character register of HD43160AH, the character with thiscode appears where the cursor
wasdisplayed and the cursor moves to the
next digit. (RSO = High, R/W = Low)
LSB
MSB
code:
3. Cursor on/off
I
(Character code)
ex. 1
LSB
MSB
Code:
0
0
0
0
0
1
0
0
On)
0
0
0
0
0
1
0
1
Off)
before
I ABCD
after
I ABCDE
'---~~----'
Read Busy Flag
Operation: The cursor appears (on) or disappears (off).
4. Set cursor position
MSB
Code: 1 line
LSB
(N - 1)
1
2 lines upper 1 0 (n lower 1
When CSO-CS3 = High, R/W = High and E
= High (RSO = 'don't care'), the Busy/Ready
signal appears on DB7.
DB 7 High: Busy
Low: Ready
binar~
l)binar~
1 m -1)
bina~
N, n, m: digit number
Table 1
Time Length of Busy (oscillation frequency = 200 kHz)
Display clear
Other operations
Min
Max
2.0
50
2.05
100
Unit
ms
"s
(depends on the operating frequency)
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Poi~t Pkwy.· Brisbane, CA 94005-1819 ·~415) 589-8300
109
a
HD43160AH
Interface to External ROM
1. Example
LSB XO
X1
Character
code
X2
X3
X4
X5
HD43160AH
X6
>~SBX7
LSB VO
Row
V1
code
V2
MSBV3
;A
01
02
03
04
05
ROMS
Address
External
ROM
ROMS
1: Ext.
0: Int.
------
*;A is used as the
*
precharge signal for
dynamic ROM if necessary.
j-
Interface to External ROM
Figure 9
2. Row code
Row code
01020304 05 V3
V2
V1
VO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Row code
0102030405
V3 V2 V1 VO
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
(Cursor)
1
0
0
0
0
,
0
0
5x11 + Cursor
5x7+Cursor
Figure 10
Row Code
HITACHI
110
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819-(415) 589-8300
HD43160AH
3. Timing chart
CL2
r-:--1
1_1_1
1 fep
I
(
XO-X7
YO-Y3
I
1 •
,
"I
2
q,A
To;;-
r
1Effective data
01-05
ROMS
.1
I-
MAX~
fep
Figure 11
Display Timing
Interface to LCD Drivers
I
1. Example
HD44100H
FlM
HD43160AH
D
Cll ~-----------4---4--~--------------~--4---~
CL2~--------------~--r-----------------~--r--
M~------------------~------------------~~
Figure 12
Interface to HD44100H
HITACHI
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111
HD43160AH
2. Waveforms (5 x 7
+ Cursor 1 line)
2
8
3
4
5
6
7
8
2
FLM
CLl
M
Enlargod
.
tEnla~~
FLM
--_......
CLl ~______________________
L
__--InL-__
M
CL2.
D
One row of a character
One row of 80 characters (400 dots)
Figure 13
Tlmlng
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD43160AH
Dot Matrix Liquid Crystal Display
System
Figure 14. Typical Application 5 X 7
+ Cursor, 2
Lines, 40 Characters
HITACHI
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113
HD44780,HD44780A--(LCD-II) .
(Dot Matrix Liquid Crystal Display
.Controller & Driver)
Pin Arrangement
Description
The LCD-II (HD447S0, HD447S0A) dot matrix
liquid crystal display controller 8t driver LSI
displays alphanumerics, kana characters, and
symbols. It drives a dot matrix liquid crystal
display under 4-bit or S-bit microcomputer or
microprocessor control. All the functions
required for dot matrix liquid crystal display
drive are internally provided on one chip. The
USer can complete dot matrix liquid crystal
display systems with low chip count by using
the LCD-II (HD447S0, HD447S0A).
If an HD44100H driver LSI is connected to the
HD447S0, up to SO characters can be displayed.
The LCD-II is produced by the CMOS process.
Therefore, the combination of the LCD-II with
a CMOS microcontroller or microprocessor
can complete a portable battery-driver
device with low power dissipation.
I
SEG.. ,
SEG" •
SEG...
.. SEG..
.. SEG..
COM"
61 COMls
SECI' ..
COM"
SEG" •
SEG ..
SECt.
COM"
COM ..
COMu
·COM ..
COM.
50 COM.
.. COM.
.. COM,
COM.
COM.
COM.
• COM.
"COM •.
DB,
.. DB.
.. DB,
... DB4
DB.
7
SECls.
SEG" ,
SEGI3
SEG"
SEGu,
SEGlo II
SEG.
SEG.
SEG. M
SEG, I
SEG...
SEG. '
SEG...
SEG. ft
SEG. D
GND
OSC ...
• oBt
Feautures
(FP-SO)
(Top View)
•
•
•
•
•
•
•
•
5 x 7 and 5 x 10 dot matrix liquid crystal
display controller driver
Capable of interfacing to 4-bit or S-bit
MPU
Display data RAM: SO x S bits
(SO characters, max.)
Character generator ROM:
--Character font 5 x 7 dots: 160 characters
--Character font 5 x 10 dots: 32 characters
Character generator RAM
--Character font 5 x 7 dots: S characters
--Character font 5 x 10 dots: 4 characters
Both display data and character generator RAMs can be read from the MPU
Intemalliquid crystal display driver:
-16 common signal drivers
-40 segment signal drivers (Can be
externally extended to 360 segments
by liquid crystal display driver
HD44100H)
.
Duty factor (selected by program):
-l/S duty: 1 line of 5 x 7 dots + cursor
-1/11 duty: 1 line of 5, x 10 dots + cursor
SEG20
, a~I!j::~:eIt~I:t:::21.fij:.'II2D • •
COM,.
:~~~:
!
:
g:~:
SEG17
SEGI.
..
I
,
•
..
COM.!
COM'2
COMn
$EGIS
SEG,.
SEG'3
SEG'2
SEG,.
IS
Sol
13
12
•
10
"
S::c:: ::
SeG.
SEG7
SEGe
SEGs
8£0.
:
13
..
I.
47
Iii
UI
:
~
..
~
SEGal- "
::~~:.
,q
;; R ~
~
=I
~
I
=K •
AR X• R
~
KI
COM10
COM,
COM,
COM7
g::
COM.
COMa
COM2
COM,
08,
OS,
= g::
r
(FP-SOA)
(Top View)
HITACHI
114
Hitachi Ameri~a, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD44780, HD44780A (LCD-II)
•
•
•
-1/16 duty: 2 line of 5 x 7 dots + cursor
Wide range of instruction functions:
Display clear, Cursor home, Display on/
off, Cursor on/off, .
Display character blink, Cursor shift,
Display shift
Internal automatic reset circuit at power
on (Internal reset circuit)
Internal oscillation circuit
(with external resistor or ceramic filter)
(External clock operation possible)
•
CMOS process
•
Logic power supply:
A single +5 V (excluding power for
liquid crystal display drive)
Operation temperature range:
-20 to +75'C (Device for -40 to +85'C
available upon request)
SO-pin plastic QFP (FP-SO, FP-SOA)
SO-pin thin plastic OFP (TFP-SO: under
development)
•
•
lIIIaldmwn Number of Display Characters
No. of
Dhlplay
Lin.
Duty
Factor
1-line
display
1/S
1/11
duty
cycle
1/16
duty
cycle
2-line
display
Extension
LCD-II
Not
provided
Porovided
1
No. of Dlepley
C....ct.s
HD44100H
S characters x 1 line
9
(S characters/each)
SO characters x 1 line
S characters x 2 lines
Not
provided
Provided
4
(S characters x 2 lines/each)
40 characters x 2 lines
Ordering Information
~Typa~~N~o~.
________________~O~PM~~~~tio~n~F~~~~~~~~v~______~~~c~~~~___________________
HD447S0SA*·H
HD447S0SA*·FH
HD44780SA**TF
1.0 MHz
HD44780SA· * FA
1.5 MHz
----------------------
SO-Pin plastic OFP (FP-SO)
SO-Pin plastic OFP (FP-SOA)
80-pin thin plastic QFP (TFP-80:
under development)
SO-Pin plastic OFP (FP-80)
Note: * * = ROM Code No.
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
115
II
HD44780, HD44780A (LCD-II)
Block Diagram (LCD-II Interior)
II>
i
o
~
(,)
en
I
I
c5
~
8
.~
o
"
.:t
.:t
11
0
0
~t5
-.
(,)(,)
en en
00
en ~
a:
a: w
"
III
...
III
III
III
0
I
0
'"
0
I
0
0
HITACHI
116
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD44780, HD44780A (LCD-II)
Electrical Characteristics
Absolute Maximum Ratings
Item
Power Supply Voltage (1)
Power Supply Voltage (2)
Input Voltage
Operating Temperature
Storage Temperature
Symbol
Vee
V1 to V5
Topr
Tstg
Limit
Unit
Note
-0.3 to +7.0
V
V
V
3
Vee-13.5 to Vee+0.3
-0.3 to Vee+0.3
-20 to +75
-55 to +125
·C
'C
Note 1: If LSI's are used above absolute maximum ratings. they may be permanently destroyed. Using
them within electrical characteristic limits is strongly recommended for normal operation. Use
beyond these conditions will cause malfunction and poor reliability.
Note 2: All voltage values are referenced to GND = 0 V.
Note 3: Applies to V1 to V5. Must maintain Vee ii: V1 ii: V2 ii: V3 iii: V4 ii: V5
(high <-+ low)
II
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117
HD44780, HD44780A (LCD.;.n)
Eleetrical Characteristics
(Vee = 6 V ± 10%, T.= -20 to +7S·C)
@=Vcc- V&
@=Vcc- v,
@E: 1.6V
@:iiO.26x@
The conditions of Vt, V6 voltages are for
proper operation of the LSI and not for the
LCD output level The LCD drive voltage
condition for the LCD output level is specified
in "LCD voltage Vr.co".
HD44780
ltam
Input High Voltage (1)
Input Low Voltage (1)
OutPut High Voltage (1)
(TIL)
VILI
LImit
Min
2.2
-0.3
VOHI
2.4
Symbol
V.Hl
Typ
Output Low Voltage (11 VOLI
(TIL)
Output High Voltage (2) VOH2
(CMOS)
Max
Vee
0.6
0.4
0.9Vee
Unit
V
V
Teet ConditIon
V
-loH .. 0.205 rnA
(3)
V
IOL = 1.2 rnA
(3)
V
-loH .. 0.04 mA
(4)
Note
(2)
(2)
Output Low Voltage (2) VOL2
(CMOS)
0.1 Vee
V
LoL = 0.04 mA
(4)
Driver Voltage Descend- VeoM
ing (COM)
2.9
V
Id=0.05 mA
(10)
Driver Voltage Descend- VSEG
ing (SEG)
3.8
V
Id=0.05 mA
(10)
(5)
Input Leakage Current
-1
1
pA
V.n = 0 to Vee
125
250
pA
Power Supply Current (1 ) ICCI
0.55
0.8
mA
Power Supply Current (2) lee2
0.35
0.6
mA
Vee=5V
Ceramic filter
oscillation
Vee = 5 V. fose =
250 kHz
Rf oscillation
External clock
operation
Vee" 5 V. fose ..
fcp = 270 kHz
Pull-Up MOS Current
IlL
-tp
50
(6)
(6)
(11 )
~~.~.~~~..VtHl
. VtLl
V 1Hl
l\'IHl
~
PWEH
E
te,-
lv.L1
V 1Ll
VtHl
V 1Ll
VtLl -
I-tOOR
VOHl
V OLl
1
C- tEl
::;
valid Data
VOHl
V OLl
tcvcE
Figure 2
Bus Read Operation Sequence
(Reading out data from LCD-II to MPU)
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- - _ . _ ' ..
_.
" - ' - ' - - ' .•....
_.
123
HD44780, HD44780A (LCD-II)
Interface Signal with Driver LSI H044100H
Figure 3
Sending Data to Driver LSI HD44100H
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HD44780, HD44780A (LCD-II)
Bus Timing Characteristics (Vee = 5.0 V ± 10%, GND = 0 V, T. = -20 to +75'C)
HD44780
Write Operation (Writing data from MPU to LCD-II)
Enable Cycle Time
Enable Pulse Width
leveE
Umlt
Min
1000
PWEH
450
Symbol
Item
High
level
Enable Rise/Fall Time
Max
25
tEr, tEl
ns
Teat Condition
Fig. 1
Fig. 1
ns
Fig. 1
Unit
ns
tAs
140
ns
Fig. 1
Address Hold TIme
tAH
Fig. 1
tosw
Data Hold Time
tH
10
195
10
ns
Data Set-up Time
Address Set-up Time
RS, R/W
E
ns
Fig. 1
ns
Fig. 1
Unit
ns
Teat Condition
Fig. 2
Fig. 2
ns
Fig. 2
ns
Fig. 2
Read Operation (Reading data from LCD-II to MPU)
Item
Symbol
Enable Cycle Time
leveE
Enable Pulse Width
High
level
Enable Rise/Fall Time
PWEH
Umlt
Min
1000
450
140
Address Hold TIme
tAH
10
Data Delay Time
tOOR
Data Hold Time
tOHR
RS, R/W
E
ns
25
tEr, tEl
tAS
Address Set-up Time
Max
320
20
ns
Fig. 2
ns
Fig. 2
ns
Fig. 2
Unit
ns
Teat Condition
Fig. 1
Fig. 1
HD44780A
Write Operation (Writing data from MPU to LCD-II)
Item
Symbol
Enable Cycle Time
leveE
Enable Pulse Width
High
level
PWEH
Limit
Min
666
300
Max
ns
ns
Fig. 1
tAS
60. 1
100. 2
ns
ns
Fig. 1
Address Hold Time
tAH
Fig. 1
tosw
ns
Fig. 1
Data Hold TIme
tH
10
100
10
ns
Data Set-up Time
ns
Fig. 1
Enable Rise/Fall Time
Address Set-up Time
25
tEr, tEl
RS,R/W
E
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125
HD44 780,HD44 780A (LCD-U)
Read Operation (Reading data from LCD-n to MPU)
ltam
Symbol
Enable Cycle Time
tcyc E
Enable Pulse Width
High
level
Enable Rise/Fall Time
Address Set-up Time
PWEH
Umlt
Min
25
tEr. let
RS.R/W
E
Max
666
300
60'"
100"2
10
lAs
Address Hold Time
tAH
Data Delay Time
tOOR
Data Hold Time
tOHR
Unit
ns
Ta.t Condition
Fig. 2
ns
Fig. 2
ns
Fig. 2
ns
190
20.
Fig. 2
ns
Fig. 2
ns
Fig. 2
ns
Fig. 2
Unit
* 1. a-bit interface mode
*2. 4-bit interface mode
Notes:
Interface Signal with HD44100H Timing Characteristics
(Vee
6.0 V :!: 10%, GND
0 V, T.
-20 to +75"C)
=
=
=
HD44780
Umit
",
ltam
Symbol
Min
Clock Pulse Width
High
level
tcwH
800
ns
Ta.t CondItIon
Fig. 3
Clock Pulse Width
Low
level
tcwL
800
ns
Fig. 3
tcsu
tsu
500
300
300
-1000 1000
ns
Fig. 3
ns
Fig. 3
ns
Fig. 3
ns
Fig. 3
Clock Set-up Time
Data Set-up Time
Data Hold Time
tOH
M Delay Time
tOM
Max
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HD44780, HD44780A (LCD-II)
HD44780A
Umit
Symbol
Min
Clock Pulse Width
High
level
tcwH
800
Unit
ns
Test Condition
Fig. 3
Clock Pulse Width
Low
level
tcwL
800
ns
Fig. 3
Clock Set-up Time
tcsu
Fig. 3
tsu
ns
Fig. 3
Data Hold Time
tOH
ns
Fig. 3
M Delay Time
tOM
500
300
300
-1000 1000
ns
Data Set-up Time
ns
Fig. 3
Item
Max
Notes:
Loading Circuit (TTL load): DBa to DB,
Test Point
0 -_ _......1--...
C
5.0V
HD44780A
5.0V
HD44780
Test Point - _......--toII-....
R
C
C=130pF
R= 11 kO
All Diodes: 152074(8)
R
C=50pF
R=20kO
All Diodes: 152074(8)
a
Loading Circuit (CMOS Load): Cll. C12. D. M
Test Point 0 - - - - - ,
±'OPF
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127
HD44780, HD44780A (LCD-II)
Power Supply Conditions Using Internal Reset Circuit
LCD-II
Item
Power Supply Rise Time
Symbol
Power Supply OFF Time
tOFF
Limit
Min
0.1
tree
Max
10
Unit
ms
Taat Condition
ms
Since the internal reset circuit will not operate normally unless the preceding conditions
are met, initialize by instruction. (Refer to
"Initializing by Instruction")
Vcc - - - - - "
tOFF·
tOFF;'; 1 ms ......----Ool
O.lms;';trcc ;';10ms
(Note)
tOFF stipulates the time of power off for momentary power supply
dip or when power supply cycles on and off.
Figure 4
Intemal Power Supply Reset
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HD44780, HD44780A (LCD-ll)
Terminal Function
Table 1 FunctIonal Description of Terminals
SignIIl
No. of Input!
Connected
Name
RS
U-
Output
to
Input
MPU
Input
MPU
Input
Input/
Output
MPU
MPU
Input!
Output
MPU
CL,
Output
HD44100H
CL2
M
Output
HD44100H
Output
HD44100H
0
Output
HD44100H
Output
Uquid
crystal
display
Output
Uquid
crystal
display
Power
supply
Power
supply
R/W
E
DB4-DB,
4
DBa-DB3
4
SEG,-SEG40 40
5
Vee. GND
2
Function
Signal to select registers.
0: Instruction register
(for write)
Busy flag: address counter
(for read)
1: Data register (for read and write)
Signal to select read (R) and write (W).
0: Write
1: Read
Operation start signal for data read/write.
Higher order 4 bidirectional three-state data bus lines.
Used for data transfer between the MPU and the LCDII. DB, can be used as a BUSY flag.
. Lower order 4 bidirectional three-state data bus lines.
Used for data transfer between the MPU and the LCDII. These four are not used during 4-bit operation.
Clock to latch serial data 0 sent to the driver LSI
HD44100H.
Clock to shift serial data D.
Switch signal to convert liquid crystal drive waveform
toAC.
Sends character pattem data corresponding to each
common signal serially.
0: Non selection
1 : Selection
Common signals that are not used are changed to nonselection waveforms. That is. COMg-COM,6 are nonselection waveforms at 1/8 duty factor. and COM'2COM'6 are non-selection waveforms at 1/11 duty
factor.
Segment signal.
Power supply for liquid crystal display drive.
Vee: +5 V. GND: 0 V."
Terminals connected to resistor or ceramic filter for
internal clock osillation.
For external clock operation. the clock is input to
OSC,.
OSC,.OSC2 2
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---~
.---.~--~
......-.-
.. - -
...
_-
-.-~.-----
129
HD44780, HD44780A (LCD-II)
Function Of Each Block
from the MPU. Register selector (RS) signals
make their selection from these two registers.
Register
The HD44780 has two 8-bit registers, an
instruction register (IR) , and a data register
(DR).
The IR stores instruction codes such as display clear and cursor shift, and address
information for display data RAM (DD RAM)
and character generator RAM (CG RAM). The
IR can be written from the MPU but not read
by the MPU.
The DR temporarily stores data to be written
into the DD RAM or the CG RAM and data to
be read out from DD RAM or CG RAM. Data
written into the DR from the MPUis automatically written into the DD RAM or the CG
RAM by internal operation. The DR is also
used for data storage when reading data is
read from the DD RAM or the CG RAM. When
address information is written into the IR,
data is read into the DR from the DD RAM or
the CG RAM by internal operation. Data
transfer to the MPU is then completed by the
MPU reading DR. After the MPU reads the DR,
data in the DD RAM or CG RAM at the next
address is sent to the DR for the next read
Table 2
R/W Operation
0
0
o
When the busy flag is 1, the HD44780 is in the
internal operation mode, and the next
instruction will not be accepted. As table 2
shows, the busy flag is output to DB7 when RS
= 0 and R/W = 1. The next instruction must
be written after ensuring that the busy flag is
O.
Address counter (AC)
The address counter (AC) assigns addresses
to DD and CG RAMs. When an instruction,for
address is'written in IR, the address information is sent from IR to AC. Selection of either
DD or CG RAM is also determined concurrently by the instruction.
After writing into (or reading from) DD or CG
RAM display data, AC is automatically incrementedby +1 (or decremented by -1). AC
contents are output to DBo - DBs when RS = 0
and R/W = 1, as shown in table 2.
Register Selection
RS
0
Busy flag (BF)
IR write as internal operation (Display
clear, etc.)
Read busy flag (DB7) and address
counter (DBo-DBs)
DR write as internal operation (DR to DO
or CG RAM)
DR read as internal operation (DO or CG
RAM to DR)
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HD44780, HD44780A (LCD-II)
Display data RAM (DD RAM)
eral data RAM. Relations between DD RAM
addresses and positions on the liquid crystal
display are shown below.
The DD RAM address (ADD) is set in the
address counter (AC) and is represented in
hexadecimal.
The display data RAM (DD RAM) stores display data represented in 8-bit character
codes. Its capacity is 80 x 8 bits, or 80 characters. The display data RAM (DD RAM) that
is not used for display can be used as a gen-
+ Upper Order
Lower Order
Bits
Bits
\.- Hexa
decimal
Hexadecimal
oJ L..
..
oJ
DO RAM address 4E
(Example)
1-Line Display (N = 0)
1. When there are fower than 80 display
characters, the display begins at the head
position. For example, 8 characters using
1 HD44780 are displayed as:
(digit)
2
3
4
5
79
l-line
80
+ Display
Position
+ DO RAM
Address
(digit)
2
3
4
5
6
7
+
8
l-lina
Display
Position
DO RAM
Address
When the display shift operation is performed, the DD RAM address moves as:
(Left
Shift
Display)
101 102 103 104 105 06·1 07 08
1
1
1
(Right
Shift
Display)
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131
HD44780. HD4478QA (LCD-U)
2. 16-character dispJay using an HD447S0
and an HD44100H is as shown below:
(digit)
2
3
4
5
6
7
S
9
10 11 12 13 14 15 16
Hine
+ Display
Position
+ DO RAM
Address
L--
HD447S0 Display
---lL-.
HD44100H Display
---J
When the display shift operation is performed, the DD RAM address moves as:
~~
lo~ 10210310410510610710sI0910AloeiocioDIOEIOFl 10 1
Display)
'J
(Right
~~~~ay)
14F I 001 01 1021031041051061 0710sI0910Aloe 10ciODIOE I
3. The relation between display position
and DD· RAM address when the number
of display digits is increased. through the
use of one HD447S0 and two or more
HD44100H's can be considered an exten-
(digit)
sion of 2.
Since the increase can be S digits for each
additional HD44100H, up to So, digits can
be displayed by externally connecting 9
HD44100H's.
1234567 S 91011121314151617181920
73 74 75 76 77 78 79 80
1-line
.. DO RAM
Address
L
HD447S0
Display
2-Une Display (N
(digit)
Display
.. Position
-.J L HD44100H (1) ...JL HD44100H .JL HD44100H (9) .....J
Display
, (2) - (S)
Display
Display
= 1)
234
5
39
1-line
40
I:: I:: I
2-line
+ Display
Position
+ DO RAM
Address
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HD44780, HD44780A (LCD-II)
1.
When the nwnber of display characters is
less than 40 x 2 lines, the 2 lines are
displayed from the head. Note that the
first line end address and the second line
(digit)
start address are not consecutive. For
example, when an HD44780 is used, 8
characters x 2 lines are displayed as:
2
3
4
5
6
7
8
+-
Display
Position
+-
DO RAM
Address
1-line
00
01
02
03
04
05
06
07
2-line
40
41
42
43
44
45
46
47
When display shift is performed, the DD
RAM address moves as:
(Left
Shift
Display)
(Right
Shift
Display)
2.
01
02
03
04
05
06
07
08
41
42
43
44
45
46
47
48
27
00
01
02
03
04
05
06
67
40
41
42
43
44
45
46
16 characters x 2 lines are displayed
when an HD44780 and an HD44100H are
used.
10 11 12 13 14 15 16
+-
Display
Position
1-line
00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF
+-
DO RAM
Address
2-line
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 40 4E 4F
(digit)
2
L--
3
4
5
6
HD44780 Display
7
8
9
---.JI....-
HD44100H Display
~
When display shift is performed, the DD
RAM address moves as follows:
(Left
Shift
Display)
01 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF 10
(Right
Shift
Display)
27 00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE
41 42 43 44 45 46 47 48 49 4A 4B 4C 40 4E 4F 50
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 40 4E
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133
HD44780; HD44780A (LCD-II)
3. The .. relation betweeI). display position
and DD RAM address when the number
of display digits is increased by using one
HD44780 and two or more HD44100H's,
can be considered an extension of 2.
(digit)
Since the increase can be 8 digits X 2
lines for each additional HD44100H, up to
40 digits 2 lines can be displayed by connecting 4 HD44780's extemally.
123456 7891011121314151617181920
I-line 0001 0203 04 05 06 07 0809 DAOB ocloo OE OF 1011 1213
---------
2-line 4041 4243 4445 4647 4849 4A4B 4C4D 4E 4F 50 5152 53
-------_.
L HD44780 --.lL HD44100H(I) ..JL HD44100H i
Display
Display
(2), (3)
Display
33 34 35 36 37 38 39 40 .. Display
position
2021 2223 2425 2627 .. DO RAM
address
6061 6263 64 65 6667 (Hexadecimal)
HD44100H(4)
Display
-.J
Character Generator ROM (CG ROM)
Character Generator RAM (CG RAM)
The character generator ROM generates 5 x
7 dot or 5 x 10 dot character patterns from 8bit character codes. It can generate 160 5 x 7
dot character patterns and 32 5 x 10 dot
character patterns. Table 3 shows the relation between character codes and character
patterns in -the Hitachi standard
HD44780AOO. User defined character patterns are also available by mask-programmed
ROM.
In the character generator RAM, the user can
rewrite character patterns by program. With
5 x 7 dOts, 8 character patterns can be
written and with 5 x 10 dots, 4 characters
can be written.
Write the character codes in the left column
of table 3 to display character patterns stored
inCGRAM.
Table 4 shows the relation between CG RAM
addresses and data and display patterns.
As table 4 shows, an area that is not used for
display can be' used as a general data RAM.
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HD44780, HD44780A (LCD-II)
Table 3
Correspondence between Character Codes and Character Pattern
(Hitachi Standard HD44780AOO)
Note: The user can specify any pattern for character-generator RAM.
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135
HD44780, HD44780A (LCD-II)
Table 4
Relatlonbetween CG RAM Addresses and Character Codes (DD RAM) and
Character Pattems (CG RAM Data)
For 5 x 7 dot character patterns
0 0
0 1
0
1
0 0
0 1
1 0
o
'0
10
10
0 1,0
11
I1
,1
,
0 0
0 1
0
1 1
0 0
0
0
Character
Pattern
Example (1)
Cursor
+- Position
Character
Pattern
Example (2)
:1
10 0 0
10 0
1 1 1,;
0 0
1
I1 0
0
11
,1
*No effect
Notes: 1. Character code bits 0-2 correspond to CG RAM address bits 3-5 (3 bits: 8 types).
2. CG RAM address bits 0-2 designate character pattern line position. The 8th line is the cursor
position and display is formed by logical OR with the cursor.
Maintain the 8th line data, corresponding to the cursor display position, in the 0 state for
cursor display. When the 8th line data is 1 , bit 1 lights up regardless of cursor presence.
3. Character pattern row positions correspond to CG RAM data bits 0-4, as shown in the figure
(bit 4 being at the left end).
Since CG RAM data bits 5-7 are not used for display, they can be used for the general data
RAM.
4. As shown in table 3, CG RAM character patterns are selected when character code bits 47 are all O. However, since character code bit 3 has no effect, the "R" display in the
character pattern example is selected by character code "00" (hexadecimal) or "08" (hexadecimal).
5. 1 for CG RAM data corresponds to display selection and 0 to non-selection.
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HD44780, HD44780A (LCD-il)
For 5 x 10 dot character patterns
haracter Codes
(DO RAM Detal
7 6 6 432 1 0
Higher
Order
Bits
Lower
Order
Bits
'0
:0
:0
:0
:0
0 O!O
:0
10
I
I 1
:1
I1
....
I 1
:1
:1
11
:1
0 0 0
0 0
0
0
0 1 1
0 0
0 1
0
1 1
0 0 0
0 0
01 0
0 1 1
0 0
0 1
0
1 1
--- ------ ---
0 0 0
••
Character
Pattern
Example
0 0 0
0 0 0
·..:.....
• _~_!JO ~_~_~_~
Cursor
+ Position
I
I
I
I
••
I
.1 •
••
••••
0~:!:::::::;:::~~1;:::::::::;:::"r
___ L~.P_LQ.
• • ·1
1 1I 1 0
11 0 1 1
:1
0 0
:1
0 1
1
11
0
1 1
I
.--.-.,.-.-.-.-.
:
I
:
• • • ,• • • • •
.No Effect
Notes: 1. Character code bits 1, 2 correspond to CG RAM address bits 4, 5 (2 bits: 4 types).
2. CG RAM address bits 0-3 designate character pattem line position. The 11th line is the
cursor position and display is formed by logical OR with the cursor.
Maintain the 11 th line data corresponding to the cursor display position in the 0 state for
cursor display. When the 11th line data is 1, bit 1 lights up regardless of cursor presence.
Since the 12th-16th lines are not used for display, they can be used for general data RAM.
3. Character pattem row positions are the same as 5 x 7 dot character pattern positions.
4. CG RAM character patterns are selected when character code bits 4-7 are all O. However,
since character code bit 0 and 3 have no effect, .p- display in the character pattern example
is selected by character codes ·00·, ·01-, ·OS- and ·09· (hexadecimal).
5. 1 for CG RAM data corresponds to display selection and 0 to non-selection.
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137
HD44780, HD44780A(LCD-II)
TUning Generation Circuit
serially through a 40·bit shift register and
latched when all needed data has arrived.
The .latched data controls the driver for
generating drive waveform outputs. The
serial data can be sent to HD44100Hs, externally connected in cascade, used for' display
digit number extension.
.
Serial data send always starts at the display
data·character pattern corresponding to the
last address of the display data RAM (DD
The timing generation circuit generates timing signals to operate intemal circuits such as
DD RAM, CG ROM, and CG RAM. RAM read
timing needed for display and internal operation timing by MPU access are separately
generated so they do not interfere with each
other. Therefore, when writing data to the
DD RAM, for example, there will be no undesirable influence, such as flickering, in
areas other than the display area. This circuit
also generates timing signals to operate the
externally connected driver LSI HD44100H.
RAM).
Since serial data is latched when the display
data character pattern corresponding to the
starting address enters the internal shift register, the HD447S0 drives the head display.
The rest displays, corresponding to latter
addresses, are added with each additional
HD44100H.
Liquid Crystal Display Driver' Circuit
The liquid crystal display driver circuit consists of 16 common signal drivers and 40
segment signal drivers. When character font
and number of lines are selected by a program, the required common signal drivers
automatically output drive waveforms, the
other common' signal drivers continue to
output non-selection waveforms.
The segment signal driver has essentially the
same configuration as the driver LSI
HD44100H. Character pattern data is sent
Cursor/Blink Control Circuit
The cursor/blink control circuit generates the
cursor or blink. The cursor or the blink appear
in the digit at the display data RAM (DD
RAM) address set in the address counter
(AC).
When the address counter is (OShe, the cursor
pOsition is:
AC6 AC5 AC4 AC3 AC2 AC1 ACO
AC
0
0
0
000
In a I-line display
(digit)
2
I
3
4
5
6
7
8
111 11H H
00
01
02
03
04
00
r I 1(
9
10
11
1..
OA
Display
.. Position
.. DO RAM
Address
(Hexadecimal)
the cursor position
In a 2-line display
Display
(digit)
lin/
2nd linl
l
1st
2
3
4
5
6
7
8
9
10
11
00
01
02
03
04
05
06
07
~
09
OA
40
41
42
43
44
45
46
47{ 48
49
4A
/
.. Position
)
~
.. DO RAM
Address
(Hexadecimal)
the cursor position
Note:
The cursor or blink appears when the address counter (AC) selects the character generator RAM
(CG RAM). But the cursor and blink are meaningless.
The cursor or blink is displayed in the meaningless position when AC is a CG RAM address.
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HD44780, HD44780A (LCD-II)
Interfacing To MPU
In the HD44780, data can be sent in either 2
4-bit operations or 1 8-bit operations so it can
interface to both 4- and 8-bit MPUs.
1.
When interface data is 4-bits long, data is
transferred using only 4 buslines: DB4-DB
7. DBo-DB3 are not used. Data transfer
between the HD44780 and the MPU
completes when 4-bit data is transferred
twice. Data of the higher order 4 bits
(contents of D~-DB 7 when interface data
is 8 bits long) is transferred first, then the
lower order 4 bits (contents of DBo-DB3
when interface data is 8 bits long) is
transferred.
Check the busy flag after 4-bit data has
been transferred twice (one instruction).
Two 4-bit operations will then transfer
the busy flag and address counter data.
2.
When interface data is 8 bits long, data is
transferred using the 8 data buslines
DBo-DB7.
Rs-------------------~I
R/W-------'
E
DB6~@~R6.@.
DB5~m~R.@.
DB4~@~DR4.Q.!!9.
I
I
Instruction (lR)
Write
Busy Flag (BF) and
Address Counter (AC)
Read
Data Register (DR)
Read
Figure 54-Bit Data Transfer Example
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HD44780, HD44780A (LCD-U)
Reset Function
InIt1aU&IDg by Internal Reset CIrcuit
4.
The HD44780 automatically initializes (resets) when power is turned on using the
internal reset circuit. The following instructions are executed during initialization. The
busy flag (BF) is kept in busy state until
initialization ends (SF = 1). The busy state is
10 ms after Vee rises to 4.5 V.
1. Display clear
2. FunCtion set:
DL = 1: 8 bit long interface data
N = 0: 1-line disPlay
F = 0: 5 x 7 dot character font
3. Display' on/off control:
D = 0: Display off
C = 0: Cursor off
B == 0: Blink off
Entry mode set:
lID = 1: +1 (increment)
S = 0: No shift
Note:
When conditions in "Power Supply
Conditions Using Internal Reset Circuit"
are not met, the internal reset circuit will
not operate normally and initialization
will not be performed. In this case
initialize by MPU according to "Initializing by Instruction".
initializing by InstructioD
If the power supply conditions for correctly
operating the internal reset circuit are not
met, initialization by instruction is required.
Use the procedure in figures 6 and 7 for
initialization.
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HD44780, HD44780A (LCD-II)
1:
Wait more than 15 ms
after Vee rises to 4.5 V
[I
RS R/W DB) DBa DBs DB, DB3 DB2 OBI DBo
o
0
0
0
1
1
*
*
*
*
*
*
*
SF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
Wait more than 4.1 ms
[
1
*
SF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
Wait for more than 100ps
RS R/W DB) DBa OBI DB, DB3 DB2 OBI DBo
o
0
001
1
*
*
*
*
SF cannot be checked before this instruction.
[ L - - - -_ _- - - - - - - J
Function set (Interface is 8 bits long.)
SF can be checked after the following instructions. When SF is not checked. the waiting
time between instructions is longer than the
execution instruction time. (See table 5)
RS R/W DB) DBa OBI DB, DB3 DB2 OBI DBo
000011NF**
o
o
0
0
0
0
0
0
0
0
0
0
000
0
0
0000000
0
1
liDS
Function Set (Interface is 8 bits long.
Specifiy the number of display lines and
character font.)
The number of display lines and character font
cannot be changed afterwards.
Display off
Display clear
Initialization ends
Entry mode set
Figure 6 8-Bit Interface
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-.-.-.---.,,-:._---_......
..,,--"-- '",--::-:---
-"~~--------"'--.
--------~.~.--~~,,,..-.--,~=--
141
~-------
HD44780, HD44780A (LCD-II)
2:
Wait more than 15 ms
after Vee rises to 4. 5 V
[
SF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
[
SF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
[
SF cannot be checked before this instruction.
Function set (Interface is 8 bits length.)
RS R/W DB7 DBs DB; DB.
o
0
0
0
1
0
0
0
0
1 0
0
N F
0 0 0
0 0 1 0 0
0 0 0 0 0
0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
* 0*
0
0
0
1
I/O S
SF can be checked after the following instructions. When SF is not checked, the waiting
time between instructions is longer than the
execution instruction time. (See table 5)
Function Set (Set interface to be 4 bits long.)
Interface is 8 bits length.
Function Set (Interface is 4 bits long. Specify
the number of display lines and character font.)
The number of display lines and character font
cannot be changed afterwards.
Display off
Display clear
Entry Mode Set
Initialization ends
Figure 7 4·Bit Interface
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HD44780, HD44780A (LCD-II)
Instructions
Outline
3. Perform data transfer with internal RAM
4. Others
In normal use, category 3 instructions are
used most frequently. However, automatic
incrementing by +1 (or decrementing by -1)
of HD44780 internal RAM addresses after
each data write lessens the MPU program
load. The display shift especially can perform
concurrently with display data write, enabling the user to develop systems in minimum time with maximum programing efficiency. Foran explanation of the shift function in its relation to display, see table 7.
When an instruction is executing during
internal operation, no insruction other than
the busy flag/address read instruction will be
executed.
Because the busy flag is set to 1 while an
instruction is being executed, check to make
sure it is 1 before sending an instruction from
the MPU.
Only two HD44780 registers, the instruction
register (IR) and the data register (DR) can be
directly controlled by the MPU. Prior to
internal operation start, control information is
temporarily stored in these registers, to allow
interface from HD44780 internal operation to
various types of MPUs that operate in different speeds or to allow interface to peripheral
control les. HD44780 internal operation is.
determined by signals sent from the MPU.
These signals include register selection signals (RS), read/write signals (R/W) and data
bus signals (OBo-DB7), and are here called
instructions. Table 5 shows the instructions
and their execution time. Details are explained in subsequent sections.
Instructions are of 4 types, those that,
1. Designate HD44780 functions such as
display format, data length, etc.
2. Give internal RAM addresses
Notes: 1. Make sure the H044780 is not in the busy state (BF = 0) before sending the instruction
from the MPU to the H044780. If the instruction is sent without checking the busy flag, the
time between first and next instructions is much longer than the instruction time. See table
5 for a list of each instruction execution time.
2. After execution of a CG RAM/DO RAM data write or read instruction, the RAM address
counter is increased or decreased by 1 . The RAM address counter is updated after the busy
flag turns off. In figure 7 boo is the time elapsed after the busy flag turns off until the address
counter is updated.
Busy signa'
(OB 7 pin)
B~N~4
~,-----------------------
Address counter ---A---+j'----'V,
(DBa to OB 6 pins)
:J\.
--------~----~
14
-I
A+l
~--------------
tAOO depends on the operation frequency
tAOO = 1.5/(fcp or fosd seconds
Figure 8
Address Counter Update
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HD44780, HD44780A (LCD-II)
Table 5 Instructions
Execution Time
(mexl
Code
Instruction
Clear
Display
Return
Home
Iwhen fcp or
RS R/W DB7 DBe OBI DB4 DB3 DB2 DB, ORo Description
foac is 250 kHzl
Clears entire display and sets DO
0
0
0
0
1
1.64 ms
0
0
0
0
0
RAM address 0 in address counter.
Sets DO RAM address 0 In address
counter. Also returns display being
0
0
0
0
0
0
0
0
1
1.64 ms
shifted to original position. DO
RAM contents remain unchanged.
Sets cursor move direction and
specifies shift of display. These
0
0
0
1 I/O S
0
0
0
0
40"s
operations are performed during
data write and read.
Sets ON/OFF of entire display (0).
0
1
0
C
B cursor ON/OFF (C). and blink of
0
0
0
0
0
40"s
cursor position character (B).
Moves cursor and shifts display
0
1 SIC R/L
without changing DO RAM con0
0
0
0
40"s
tents.
Sets interface data length (DL).
0
1 DL N
number of display lines (L) and
0
0
F
0
40"s
character font (F).
Sets CG RAM address. CG RAM
0
1
ACG
data is sent and received after this
0
0
40"s
setting.
Sets DO RAM address. DO RAM
1
data is sent and recevied after this
ADD
0
0
40"s
setting.
Reads Busy flag (BF) indicating
internal operation is being perfor0
1 BF
AC
O"s
med and reads address counter
contents.
Writes data into DO RAM or CG
40"s
Write Data
RAM.
1
0
tADD = 6 "s (Note 2)
*
Entry
Mode Set
Display
On/Off
Control
Cursor or
Display
Shift
Function
Set
Set CG RAM
Address
Set DO RAM
Address
Read
Busy Flag
& Address
Write Data
to CG or
DO RAM
Read Data
from CG or
DO RAM
* *
* *
1
I/O =
I/O =
S =
SIC =
S/C=
R/L =
R/L =
DL =
N =
F =
BF =
BF =
1
1:
0:
1:
1:
0:
1:
0
1
1
1
1
0
Reads data from DO RAM or CG
RAM.
Read Data
Increment
Decrement
Accompanies display shift
Display shift
Cursor move
Shift to the right
Shift to the left
8 bits, DL= 0: 4 bits
2 lines, N= 0: 1 line
5x10 dots, F= 0: 5x7 dots
Internally operating
Can accept instruction
DO RAM: Display data RAM
CG RAM: Character generator
RAM
ACG: CG RAM address
ADD: DO RAM address:
Corresponds to cursor address
AC: Adresscounter used for both
DO and CG RAM address.
40"s
tADD = 6 "s (Note 2)
Execution time
changes when
frequency changes
Example:
When fcp or fosc
is 270 kHz:
250
401'$ x 270 = 371's
* No effect
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HD44780, HD44780A (LCD-II)
Description of Details
1.
Clear Display
RS R/W OB7
Writes space code 20 (hexadecimal)
(character pattem for character code 20
must be blank pattem) into all DD RAM
addresses. Sets DD RAM address 0 in
address counter. Returns display to its
original.status if it was shifted. In other
2.
words, the display disappears and the
cursor or blink go to the left edge of the
display (the first line if 2 lines are displayed). Set liD = 1 (increment mode) in
entry mode. S of entry mode doesn't
change.
Return Home
RS R/W OB 7 - - - - - - - - - _ O B o
o
Code
o
Sets the DD RAM address 0 in address
counter. Returns display to its original
status if it was shifted DD RAM contents
do not change.
o
o
* Don't care
The cursor or blink go to the left edge of
the display (the first line if 2 lines are
displayed).
3. Entry Mode Set
RS R/W OB 7
------------
1/0: Increments (liD = 1) or decrements
(liD = 0) the DD RAM address by 1
when a character code is written
into or read from the DD RAM.
The cursor or blink moves to the
right when incremented'by 1 and to
the left when decremented by 1.
The same applies to writing and
reading of CO RAM.
S:
OBo
Shifts the entire display either to
the right or to the left when S is 1; to
the left when liD = 1 and to the
right when liD = O.
Thus it looks as if the cursor stands
still and the display moves. The
display does not shift when reading
from the DD RAM when writing
into or reading out from the CO
RAM causes a shift when S = O.
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HD44780, HD44780A (LCD-II)
4.
Display On/Off Control
_
RS R/W DB7
Code
D:
C:
00000
0
I
The display is on when D = 1 and off
when D = O. When off due to D = 0,
display data remains in the DD
RAM. It can be displayed instantly
by setting D = 1.
The cursor is displayed when C = 1
and is not displayed when C = O.
Even if the cursor disappears, the
function of I/D, etc. does not change
during display data write. The cursor is displayed using 5 dots in the
8th line when the 5 x 7 dot character font is selected and 5 dots in the
11th line when the 5 x 10 dot char-
1
B:
I I
5 x 10 dot character font
Cursor Display Example
Figure 9
C
IB
acter font is selected (Figure 9).
The character indicated by the cursor blinks when B = 1 (Figure 9).
The blink is displayed by switching
between all blank dots and display
characters at 409.6 roB intervals
when fep or fosc = 250 kHz. The
cursor and the blink can be set to
display simultaneously. (The blink
frequency changes according to
the reciprocal of fcp or fose. 406.9 x
250
270
379.2 roB when fcp = 270
kHz.)
=
Cursor_
5 x 7 dot character font
D
DBo
-
Alternating display
Blink Display Example
Cursor and Blink
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HD44780, HD44780A (LCD-TI)
5.
Cursor or Display Shift
RS R/W DB7 - - - - - - - - - - - DBo
Code
o
0
0
0
0
Shifts cursor position or display to the
right or left without writing or reading
display data (Table 6). This function is
used to correct or search for the display.
In a 2-line display, the cursor moves to the
2nd line when it passes the 40th digit of
the 1st line. Notice that the 1st and 2nd
line displays will shift at the same time.
6.
* Don't care
When the displayed data is shifted
repeatedly each line only moves horizontally. The 2nd line display does not shift
into the 1st line postion.
Address counter (AC) contents do not
change if the only action performed is
display shift.
Function Set
RS R/W DB7 - - - -________ DBo
Code
DL:
*Don't care
Sets interface data length, Data is
sent or received in 8 bit lengths
(Dl3?-DBo) when DL = 1 and in 4 bit
lengths (Dl3?-DBd when DL = O.
N:
F:
When the 4 bit length is selected,
data must be sent or received twice.
Sets number of display lines,
Sets character font.
Note: Perform the function at the head of the program before executing any instructions
(except "Busy flag/address read"). From this point. the function set instruction
cannot be executed unless the interface data length is changed.
Table 6
SIC
R/L
o
0
Shift Func:tlon
Shifts the cursor position to the left.
(AC is decremented by one.)
Shifts the cursor position to the right.
(AC is incremented by one,)
Shifts the entire displey to the left. The
cursor follows the display shift.
Shifts the entire display to the right.
The cursor follows the display shift.
o
o
Table 7
N
F
o
o
o
Func:tlon Set
*
No. of
DI8pIay Un..
2
Character
Duty
Font
5 x 7 dots
Factor
1/8
5 x 10dots
5x7dots
1/11
1/16
Cannot display 2 lines with 5 x 10 dot character font
* Don't care
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-~--~---'----' .-----~ ,-'70""W""'~"'" BusY~/I&.
Instruction
Write
I
Busy Flag
Check
I
Busy Flag
Check
I
Busy Flag
Check
I
Instruction
Write
Figure 10 Example of Busy Flag Cbeck Timing Sequence
A,5
HD68BOO
A'4
A,3
A,
Ao
R/W
VMA
'1>2
DB o -DB 7
~
8
cS 2
PA2
CS,
CSo
PAl
RS,
RSo
PAo
R/W
HD68B21
E
PB o -PB 7
0 0 -0 7
RS
COM,COM'6
R/W
E
8
2!}
HD44780
40
SEG,- --+SEG40
Connected
to Uquid
Crystal
Display
DBo -DB 7
HD68BOO: 8 bit CPU
Figure 11
Example of Interface to HD68BOO Using PIA (HD68B21)
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HD44780, HD44780A (LCD-U)
Connecting directly to the 8-bit MPU bus
line
VMA
~2
~
I
-I
A'5
H06800
COM,COM'6
E
,
16
H044780
Ao
R/W
RS
R/W
00- 0 7
080-0B 7
8
Figure 12
Connected
to LCD.
SEG,SEG 40
40
8-Blt MPU Interface
Example of interfacing to the HD6805
Ao- A7
H06B05
8
OBo-OB7
E
RS
R/W
Co
C,
Cz
COM,COM'6
16
H044780
SEG,SEG40
40
Connected
to LCD.
Figure 13 HD6806 Interface
Example of interfacing to the HD6301
RS
R/W
E
PM
P35
P3S
COM,COM,s
16
Connected
to LCD.
HD44780
H06301
P,o-P H
OBo-OB7
8
SEG,
SEG40
40
Figure 14 HD6301 Interface
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HD44780, HD44780A (LCD-II)
2.
bits). In the latter case, the timing
sequence becomes somewhat complex.
(See figure 15)
Figure 15 shows an example of interface
to the HMCS43C.
Note that 2 cycles are needed for the
busy flag check as well as the data transfer. 4-bit operation is selected by program.
Interface to 4-bit MPU
The HD44780 can be connected to a 4-bit
MPU through the 4-bit MPU I/O port. If
the I/O port has enough bits, data can be
transferred in 8-bit lengths, but if there
are insufficient bits, the transfer is made
in two operations of 4 bits each (with
designation of interface data length for 4
AS
____---1/
A/W
\1...._-----
E
Internal
Internal Operation
No
DB7
~Busy\~BUSY~
Instruction
Write
Note:
I
Busy Flag
Check
I
Busy Flag
Check
I
Instruction
Write
IA7, IA3: Instruction 7th bit, 3rd bit
AC3: Address Counter 3rd bit
Figure 15
An Example of 4-Bit Data Transfer Timing Sequence
HMCS43C
0 15
AS
0 14
A/W
0 13
E
4
A1O- A13
COM1COM 16
~
HD44780
DB4- DB7
SEG1SEG 40
~
1
Connected
to Uquid
Crystal
Display
HMCS43C: Hitachi 4-bit single-chip microcontroller
Figure 16
Example of Interface to the HMCS43C
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HD44780, HD44780A (LCD-II)
Interface to Liquid Crystal Display
1.
Character Font and Number of Lines
The HD44780 can perform. 2 types of
display, 6 x 7 dots and 6 x 10 dots character font, with a cursor on each.
Up to 2 lines are displayed with 6 x 7 dots
and 1 line with 6 x 10 dots. Therefore,
three types of common signals are available (Table 8).
Number of lines and font types can be
selected by program.
(See to Table 6, Instructions)
2.
Connection to HD44780 and Liquid Crystal Display
Figure 17 shows connection examples.
Table 8 Common Signals
Number of
Li_
C. .racter Font
6 x 7 dots + Cursor
6 x 10 dots + Cursor
6 x 7 dots + Cursor
2
COM' _ _ _
Number of
Convnon Signals
Duty
8
11
16
1/8
1/11
1/16
Factor
~J1J
COMa
HD44780
S~G, ~~~~~
______________________ _
SEG~,I---------------------------------------J
(a)
Uquid Crystal
Display Panel
(8 characters
. xl line)
Example of a 5x7 dot, 8 character x 1 line Display (1/4 Bias, 1/8 Duty Cycle)
SEG,
~
_____________________ _
SEG~r_------------------------------------~
(b)
UquidCrystal
Display Panel
(8 characters
xl line).
Example of a 5x 10 dot, 8 character x 1 line Display (1/4 Bias, 1/8 Duty Cycle)
Figure 17 . Llquld .Crystal Display end Connections to HD44780
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HD44780, HD44780A (LCD-II)
Since 5 SEG signal lines can display one
digit, one HD44780 can display up to 8
digits for 1-line display and 16 digits for 2line display.
In Figure 15 examples (a) and (b), there
are unused common signal terminals,
which always output non-selection
waveforms. When the liquid crystal display panel has unused extra scanning
lines, avoid undesirable influences due to
crosstalk in the floating state by connecting the extra scanning lines to these
common signal terminals (Figure 18).
COM,
CaMs
COMg
COM,6
HD44780
SEG,
----------------------
Liq uid Crystal
Di splay Panel
(8 characters
x 2 lines)
SEG40
(c)
Example of 5x7 dot, 8 characterx2 lines Display (1/5 Bias, 1/16 Duty Cycle)
Figure 17 Liquid Crystal Display and Connections to HD44780 (cont)
11_ __
COM,
caMs
COMg
HD44780
i-J
SEG'IiII
SEG40r-------------------------------------~
5x7 dot, 8 character x 1 line Display (1/4 Bias, 1/8 Duty Cycle)
Figure 18
Using COMe to Avoid Crosstalk on Unneeded Scanning Line
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HD44780, HD44780A (LCD-II)
3.
Connection of Changed Matrix Layout
layout. Display characteristics and the
number of liquid crystal display characters depend on the number of common
signals (or duty factor). Note that the
display data RAM (DD RAM) addresses
for 8 characters x 2 lines and 16 characters x 1 line are the same as shown in
figure 15.
In the preceding examples, the number of
lines matched the number of scanning
lines. The display types figure 17 are
made possible by changing the matrix
layout in the liquid crystal display panel.
In either case, the only change is the
5 x 7 dot, 16 character x 1 line Display
(1/5 Bias, 1/16 Duty Cycl!')
SEG,
SEG 20
-- -
--
---
--
COM,
COMs
HD44780
SEG 2 ,
SEG 40
5 x 7 dot, 4 character x 2 line Display
(1/4 Bias, 1/8 Duty Cycle)
Figure 19
Changed Matrix Layout ·Dlsplays
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HD44780, HD44780A (LCD-II)
Power SUpply for Liquid Crystal Display
Drive
must be changed according to dUty factor.
Table 9 shows the relation ..
Various voltage levels must be applied to
HD44780 terminals Vt to Vs to obtain liquid
crystal display drive waveforms. The voltages
VLCD gives the peak values for liquid crystal
display drive waveforms. Resistance dividing
provides each voltage as shown in figure 20.
Table 9. Duty Factor and Power Supply
for Liquid Crystal Display
Drive
~ Duty Factor
Po_~
Supply
VI
1/8, 1/11
1/16
1/4
1/5
Vcc-1/4 VLCD
Vcc -1 /5 VLCD
V2
Vcc -1 /2 VLCD
Vcc - 2/5 VLCD
V3
Vcc-1/2 VLCD
Vcc-3/5 VLCD
V4
Vcc-3/4 VLCD
Vcc-4/5 VLCD
V5
VCC-VLCD
VCC-VLCD
Vcd+5V)
Vcd+5V)
vcc
Vcc
R
R
VI
VI
R
V2
V2
V LCD
V3
V3
R
v4
V4
R
V5
Vs
R
R
R
VR
VR
-5V
1/4 Bias
(l/B. 1/11 Duty Cycle)
Figure 20
VLCD
R
-5V
1/5 Bias
(1/16 Duty Cycle)
Drive Voltage Supply Example
HITACHI
156
Hitachi America, Ltd.· Hitachi Plaza "2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD44780, HD44780A (LCD-II)
Relation between OscUlation Frequency
and Liquid Crystal Display Frame Frequency
The examples in figure 21 of liquid crystal
display frame frequency apply only when
1.
oscillation frequency is 250 kHz (1 clock = 4
ps).
1/8 Duty Cycle
~400CIOCks
I
COM,
1
I
2 1 3 /
4
/------1
8
11
2 /
~~e --'--rl-ilr--......:....-~--'---.!....---!.~-.--+----'!...---V2 (Va)
V4
Vs
--t:-+[-++I
I++-1I -----l]H-1_- + - - + - I
/.
1 frame
'1
1 frame = 4 (/ls) x 400 x 8 = 12800 (/ls) = 12.8 (m9)
1
= 12.8(ms)
= 78.1 (Hz)
Frame frequency
2.
1/11 Duty Cycle
~4oo clocks
COM,
Vee
V,
V2 (Va)
V4
V6
m
I
2
II I
1 3 1
1
4
I1I
,.
I1
1------111
2 1
III
.,
1 frame
1 frame = 4 (/ls) x 400 x 11 = 17600 (/l9) = 17.6(ms)
1
Frame frequency = 17.6 (ms) = 56.8 (Hz)
3.
1/16 DUty Cycle
r.- 200 clocks
COM,
Vee
V,
V2
Va
V4
V6
r:J1
II
I
I·
2 1 3
1 4
1------1 16 1 1
II II I
1 frame
II
I
.,
2 1
I
1 frame = 4 (/ts) x 200 x 16 = 12800 (.us) = 12.8(ms)
1
Frame frequency = 12.8 (ms) 78.1 (Hz)
Figure 21 Frame Frequency
HITACHI
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157
HD44780, HD44780A (LCD-II)
Connection with Driver LSI HD44100H
You can increase the number of display digits
by externally connecting an HD44100H liquid
crystal display driver LSI to the HD44780.
When connected to the HD44780, the
HD44100H is used as segment signal driver.
The HD44100H can be connected to the
HD44780 directly since it supplies CLI, CL2, M,
and D signals and power for liquid crystal
display drive. Figure 22 shows a connection
example.
Caution: Connection of voltage supply terminals VI through Ve for liquid crystal display
drive is complicated.
Up to 9 HD44100H units can be connected for
1-line display (duty factor 1/8 or 1/11) and up
to 4 units for the 2-line display (duty factor 1/
16). RAM size limits the HD44780 to a maximum of 80 character display digits. The connection method in figure 22 remains unchanged for both 1-1ine and 2-line display or 5
x 7 and 5 x 10 dot character fonts.
HITACHI
158
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD44780, HD44780A (LCD-II)
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Ve
Vs
V4
GND
Vee
M
1II.:i..J Cl2
~~~ Cl1 f...-
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Example of Connecting H044100H to HD44780
HITACHI
Hitachi America, Ltd. ol-\itachi Plaza ° 2000 Sierra Point Pkwy. ° Brisbane, CA 94005-1819 0(415) 589-8300
159
HD44780, HD44780A (LCD-II)
Instruction and Display Correspondence
1.
8-bit operation, 8-digit x 1-line display
(using internal reset)
Table 10 shows an example of 8-bit x 1line display in 8-bit operation. The
HD44780 functions must be set by funtion
set instruction prior to display. Since the
display data RAM can store data for 80
characters, as explained before, the RAM
can be used for displays like a lighting
board when combined with display shift
operation.
Since the display shift operation changes
display position only and DD RAM contents remain unchanged, display data
entered first can be output when the
retum home operation is performed.
2.
operation. Since nothing is connected to
DBo-DB3, a rewrite is then required.
However, since one operation is completed in two accesses of 4-bit operation,
a rewrite is needed as a function (see
table 11). Thus, DB4-DB7 of the function set
is written twice.
4-bit operation, 8-digit x 1-line display
(using internal reset)
The program must set functions prior to
4-bit operation. Table 11 shows an example. When power is turned on, 8-bit
operation is automatically selected and
the first write is performed as an 8-bit
3.
8-bit operation, 8-digit x 2-line display
For 2-line display, the cursor automatically moves from the first to the second
line after the 40th digit of the 1st line has
been written. Thus, if there are only 8
characters in the first line, the DD RAM
address must· again be set after the 8th
character is completed. (See table 12).
Note that the first and second lines of the
display shift are performed. In the example, the display shift is performed when
the cursor is on the second line. However,
if the shift operation is performed when
the cursor is on the first line, both the first
and second lines move together. When
you repeat the shift, the display of the
second line will not move to the first line,
the same display will only move within
each line many times.
Note: When using the internal reset, the conditions in "Power Supply Condition Using Internal
Reset Circuit" must be satisfied. If not, the HD44780 must be initialized by insruction. (See
"Initializing by Instruction")
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HD44780, HD44780A (LCD-II)
Table 10 8-Bit Operation, 8-Digit I-Line Display Example
(Using Internal Reset)
No. lnatruetion
Operation
Diaplay
1
Power supply on (HD44780 is initialized by
the internal reset circuit)
2
Function Set
RS R/W DB70
0 0
1
0
1
-
DBa
0
0
* *
1
1
1
1
Initialized. No display appears.
Sets to 8-bit operation and selects 1line display lines and character font.
(Number of display lines and character
fonts cannot be changed after this.)
Turns on display and cursor. Entire
display is in space mode because of
initialization.
Sets mode to increment the address
by one and to shift the cursor to the
right at the time of write to the DD/CG
RAM.
Display is not shifted.
Write "H". The DO RAM has already
been selected by initialization when
the power is turned on.
The cursor is incremented by one and
shifted to the right.
3
Display On/Off Control
0
0
0
0
0
0
1
1
1
0
1
I
4
Entry Mode Set
0
0
0
0
0
1
1
0
1
1
5
Write Data to CG RAM/DO RAM
1
1 0
0
0
0
1
0
0
0
IH
1
6
Write Data to CG RAM/DO RAM
1 0
1 0
0
0
1
0
0
1
1
HI
I' Writes "I".
0
1
1
HITACHI
1
1
1
1
HITACHI
0
0
0
1
0
.
7
Write Data to CG
1
1
0
0
Entry Mode Set
9
0
0
0
0
Write Data to CG
10
1 0
0
0
Write Data to CG
11
1 0
0
1
8
0
RAM/DO RAM
0
0
1 0
0
1
0
0
RAM/DO RAM
1 0
0
0
RAM/DO RAM
1
1
0
0
IITACHI
=
ITACHIM
12
I
I
1
Writes "I".
Sets mode for display shift at the time
of write.
Writes "Space" .
Writes "M".
.
HITACHI
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161
HD44780, HD44780A (LCD-II)
No. Instruction
Write Data to CG
13
1 0
0
1
Cursor or Display
14
0
0
0
0
Cursor or Display
15
0
0
0
0
Write Data to CG
16
1
1 0
0
Cursor or Display
17
0
0
0
0
Cursor or Display
18
0
0
0
0
Write Data to CG
19
1 0
0
1
RAM/DO RAM
1
1
0
0
Shift
1 0
0
0
Shift
0
1 0
0
RAM/DO RAM
0
0 0
0
Shift
0
1
1
1
Shift
1 0
0
1
RAM/DO RAM
0
0
1
1
0
0
1
1
1
Operation
I MICROKO_I
Writes "0".
I MICROKO
* *
* *
1
Display
I MICROKO
IICROCO
1
Shifts only the cursor position to the
left.
Shifts only the cursor position to the
I left.
Writes "C" (correction).
I The display moves to the left.
Shifts the display and cursor position
to the right.
Shifts the display and cursor position
to the right.
I
1
I
I MICROCO I
IICROCOM= I
Writes "M".
0
I HITACHI
Returns both display and cursor to the
original position (Address 0).
I MICROCO
* *
* *
20
21
Return Home
0
0
0
0
0
0
0
I
Table 11 4-Bit Operation, a-Digit I-Line Display Example
(Using Intemal Reset)
No. Instruction
Diaplay
Power supply on (HD44780 is initialized by
1
I
the internal reset circuit)
Operation
I
2
Function Set
RS R/W DB7 I"...J DB4
0
0
0
1 0
0
I
3
Function Set
0
0
0
0
0
0
0
I
I
Display On/Off Control
0
0
0
0
0
0
0
1
1
1 0
I
I
Entry Mode Set
0
0
0
0
0
1
1=
I
IH
I
4
5
6
0
1
0
* *
0
0
0
0
1
0
0
Write Data to CG RAM/DO RAM
1 0
1 0
0
0
1
1 0
0 0
0
I
Initialized. No display appears.
Sets to 4-bit operation.
In this casEi, operation is handled as 8
bits by initialization, and only this
instruction completes with one write.
Sets 4-bit operation and selects 1-line
display and 5 x 7 dot character font.
4-bit operation starts from this point
on and resetting is needed.
(Number of display lines and character
fonts cannot be changed hereafter.)
Turns on display and cursor. Entire
display is in space mode because of
initialization.
Se~'rnode to increment the address
by one and to shift the cursor to the
right, at the time of write, to the 00/
CG RAM. Display is not shifted.
Writes "H".
The cursor is incremented by one and
shifts to the right.
Hereafter, control is the same as S-bit operation.
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HD44780, HD44780A (LCD-II)
Table 12 S-Bit Operation, S-Diglt X 2-Line Display Example
(Using Intemal Reset)
No. Instruction
Operation
Display
1
Power supply on (HD44780 is intialized by the
internal reset circuit)
2
Function Set
RS R,tWDB71
0
0
0
0
DBo
I
I
I
I
1
1
0
* *
3
Display On/Off Control
0
0
0
0
0
0
1
1
1
0
I
I
4
Entry Mode Set
0
0
0
0
0
1
'1
0
I
I
Write Data to CG RAM/DO RAM
1 0
1 0
0
0
1 0
0
0
IH
I
5
0
0
Sets to 8-bit operation and selects 2line display and 5 x 7 dot character
font,
Turns on display and cursor, All display is in space mode because of
initialization,
Sets mode to increment the address
by one and to shift the cursor to the
right, at the time of write, to the 00/
CG RAM, Display is not shifted,
Writes "H", The DO RAM has already
been selected by initialization when
the power is turned on.
The cursor is incremented by one and
shifted to the right.
·
,.
··
6
Initalized, No display appears,
·
·
IHITACHI
7
Write Data to CG RAM/DO RAM
1 0
1 0
0
1 0, 0
0
1
8
Set DO RAM Address
1
1 0
0
0
0
0
0
9
Write Data to CG RAM/DO RAM
1 0
1 0
1
1
0
0
0
1
11
Write Data to CG RAM/DO RAM
1
1
0
1 0
1
0
0
1
1
, MICROCO
,
,
12
Entry Mode Set
0
0
0
0
1
1
, HITACHI
, MICROCO
J,
Sets mode for display shift at the time
of write,
13
Write Data to CG RAM/DO RAM
1
1 0
1
1 0
0
0
,
1
'ITACHI
'ICROCOM
Writes MM", Display is shifted to the
right,
The first and second lines' shift operate at the same time,
0
0
IHITACHI
I
I
I ~ITACHI
Writes "I",
Sets RAM address so that the cursor is
positioned at the head of the 2nd line.
Writes "M",
I
10
0
0
0
1
I HITACHI
0
·
··
·
14
15
Return Home
0
0
0
0
0
0
0
0
1
0
J
,
, HITACHI
'MICROCOM'
Writes "0",
Returns both display and cursor to the
original position (Address 0),
HITACHI
Hitachi America, Ltd,. Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
163
II
HD44780, HD44780A (LCD-II)
Modifying Character Patterns
1.
Character Pattern Development Procedure
Hitachi
@
®
>.;.:N.:..O_
Back to
start
@
Flgure 23 Character Pattern Development Procedure
HITACHI
164
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HD44780, HD44780A (Le'D-II)
firmed that character patterns are correctly written, Hitachi starts mass production of the LSI.
The numbers in figure 17 correspond to the
following operations:
a,
b.
c,
Determine the correspondence between
character codes and character patterns.
2.
Progranuning Character Patterns
This section explains the correspondence
Create a listing indicating the correspondence between EPROM addresses
and data.
between addresses and data used to
program character patterns in EPROM.
The LCD-II character generator ROM can
generate 160 5 x 7-dot character patterns
and 32 5 x 10-dot character patterns for a
total of 192 different character patterns.
Program character patterns in the
EPROM.
d. Send the EPROM to Hitachi.
a.
e.
f.
Hitachi performs computer processing
with the EPROM to create a character
pattern listing and sends it to the user.
5 x 7-dot Character Pattern
For a 5 X 7-dot character pattern, EPROM
address data and character pattern correspond with each other as shown below.
Table 13 is an example of the correspondence between EPROM address data and
character pattern (5 X 7 dots).
If there is no problem in the character
pattern listing, Hitachi creates a trial LSI
and sends samples to the user. The user
evaluates the samples. When it is con-
Table 13 Example of Correspondence between EPROM Address Data and Character
Pattem (5 X 7 dots)
EPROMadel....
Character code
I
Data
Une position
(1) EPROM addresses Ato to A3 correspond to a character code.
(2) EPROM addresses A2 to Ao specify a
line position of character pattern.
(3) EPROM data 04 to 00 correspond to
character pattern data.
(4) A lit display position (black) corresponds to 1.
(5) Fill line 8 (cursor position) of character pattern with O.
(6) EPROM data Os to 07 are not used.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
165
HD44780, HD44780A (LCD-II)
b.
5
X
10-dot Character Pattern
(2) EPROM data in CG RAM area
Ignored by the character generator
ROM for display operation so it can be
o or 1.
(3) EPROM data used when the user
does not use any LCD-II character
pattern
Handled in one of the two ways explained below. Select one of the two
ways according to the user application.
(a) When unused character patterns
are not programed
If an unused character code is
written in the LCD-II DD RAM, all
dots are lit. No programming for a
character pattern is equivalent to
all bits lit. (This is because EPROM
is filled with 1 when the EPROM is
erased.)
(b) Program 0 for unused character
patterns
Nothing is displayed even if unused character codes are written
in LCD-II DD RAM. (This is equivalent to space).
For a 5xl0-dotcharacterpattern,EPROM
address data and character pattern correspond with each other as shown in
table 14.
(1) EPROM addresses AlO to A3 correspond to a character code. Set As and
A9 of character pattern line 9 and
later lines to O.
(2) EPROM addresses A2 to Ao specify a
line position of character pattern.
(3) EPROM data 04 to 00 correspond to
character pattern data.
(4) A lit display position (black) corresponds to 1.
(5) Fill line 11 (cursor position) of character pattern with O.
(6) EPROM data 05 to 0, are not used.
c.
Handling Unused Character Patterns
(1) EPROM data outside the character
pattern area
Ignored by the character generator
ROM for display operation so it can be
o or 1.
Table 14 Example of Correspondence between EPROM Address Data and Character
Pattern (5 X 10 dots)
EPROM addresa
AIO As As A7 As A5
~
Data
A3 A2 Al Ao 04 03 02
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
~~ ~~.
---.-- .------. ---.---- -.. --
------------._--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Character code
0
0
J
Fill line 11 (cursor position)
with O.
0
Line position
HITACHI
166
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
H D66780 (LCD- I I A ) - - (Dot Matrix Liquid Crystal Display
Controller and Driver)
Description
Features
5 x 7 and 5 x 10 dot matrix liquid crystal
display controller driver
Can interface to 4-bit or S-bit MPU
Display data RAM: SO x S bits (SO characters, max)
Character generator ROM: 12000 bits;
Character font 5 x 10 dots: 240 characters
Character generator RAM: 64 x S bits;
Character font 5 x S dots: S characters or
character font 5 x 11 dots: 4 characters
Both display data and character generator RAMs can be read from the MPU
Internal liquid crystal display driver
-16 common signal drivers
-40 segment signal drivers (Can be
externally extended to 360 segments by
liquid crystal display driver HD44100H or
HD66100F)
Duty factor selection (selectable by program)
-l/S duty: 1 line of 5 x 7 dots + cursor
-1/11 duty: 1 line of 5 x 10 dots + cursor
-1/16 duty: 2 lines of 5 x 7 dots + cursor
Maximum number of display characters
as shown in table 1
Wide range of instruction functions: Display clear, cursor home, display on/off,
cursor on/off, display character blink,
cursor shift, display shift
Internal automatic reset circuit at power
on (internal reset circuit)
Internal oscillation circuit
- External resistor or ceramic filter
- External clock operation possible
CMOS process
Single +5 V logic power supply (excluding power for liquid crystal display drive)
Operation temperature range: -20'C to
+75'C (-40'C to +S5'C device available
upon request)
SO-pin plastiC flat package (FP-SOB, FPSOA)
Low power consumption
The LCD-IIA (HD667S0) a dot matrix liquid
crystal display controller and driver LSI displays alphanumerics, kana characters, and
symbols. It drives a dot matrix liquid crystal
display under 4-bit or S-bit microcontroller or
microprocessor control. All the functions
required for driving a dot matrix liquid crystal
display are internally provided on one chip.
Designers can complete dot matrix liquid
crystal display systems with low chipcount
by using the LCD-IIA (HD667S0). If a driver
LSI (HD44100H or HD66100F) is connected to
the HD667S0, up to SO characters can be
displayed.
The LCD-IIA is produced by the CMOS process. Therefore, the combination of the LCDIIA with a CMOS microcontroller or microprocessor can complete a portable batterydriven device with low power dissipation.
Ordering Information
Type No.
Package
HD66780FS 80-pin plastic QFP (FP-80B)
HD66780FH 80-pin plastic QFP (FP-80A)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
167
I
".da~~c~~w~mm~
~~~
(FP-80)
~
ceoo
(FP-80A)
(Top-View)
Pin Description
No. of
Lines
1
Signal
RS
R/W
E
1
DB7-DBo
8
I/O
Connected to
Input
Input
Input
I/O
MPU
MPU
MPU
MPU
Function
Selects register
Selects read or write
Starts data read or write
Bidirectional data bus
Cl,
Output
Driver lSI
Serial data latch clock
Cl2
M
0
Output
Driver lSI
Serial data shift clock
Driver lSI
Driver lSI
LCD
LCD waveform AC switch signal
Character pattern data
Common signals
COM,-COM'6
16
Output
Output
Output
SEG,-SEG40
40
Output
LCD
Segment signals
V,-Vs
5
Power supply
LCD drive voltages
Vcc,GND
2
2
Power supply
OSC,-OSC2
+ 5 V and ground
System clock
HITACHI
168
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66780 (LCD - II A)
Pin Function
RS (Register Select)
D (Serial Data)
RS selects the register that the MPU is accessing. RS = 0 selects the instruction register
for MPU writes, and the busy flag and address
counter for reads. RS = 1 selects the data
register for MPU reads and writes.
The LCD-IIA outputs serial character pattern
data corresponding to the common signals to
the HD44100H or HD66100F driver LSIs on D.
R/W (Read/Write)
COMI-COMI6 are the LCD common lines.
Common signals that are not used are deselected. At 1/8 duty factor COMg-COMI6 are
not used, so they output non-selected
waveforms. At 1/11 duty factor COMI2-COMI6
are not used, so they output non-selected
waveforms.
R/W selects whether the MPU will read from
(R/W = 1) or write to (R/W = 0) the LCD-IIA.
E (Enable)
COMt-COMt6 (Common)
The MPU sets the E input high to signal the
start of the read/write operation.
SEGt-SEG40 (Segment)
DB.,..DBo (Data Bus)
SEGI-SEG40 are the LCD segment lines.
The bidirectional, three-state data bus, DBoDB7, transfers data between the MPU and the
LCD-IIA. DB7 can be used as the busy flag.
The lower-order four lines, DBo-DB4, are not
used in four-bit interface operation.
Vt-Va (LCD Voltages)
The LCD-IIA requires the Vl-VS voltages to
output LCD-driving waveforms.
Vee. GND (Power Supply. Ground)
CLt. CLz (Clock 1. Clock 2)
The CLI output signals the HD44100H or
HD66100F driver LSI to latch the serial data
sent on line D. The CLz output signals it to
shift the data.
M (Master AC Signal)
The HD44100H or HD66100F driver LSIs use
the M output to convert the LCD drive
waveform to AC.
Vcc is the LCD-IIA's logic power supply. GND
is the power supply ground.
OSCt. OSCz (Oscillator 1. OscUlator 2)
OSCI and OSC2 are the connections for
LCD-IIA system clock. The LCD-IIA can
its internal oscillator if OSCI and OSCz
connected to a resistor or ceramic filter.
external clock can be input to OSCI.
the
use
are
An
Table 1 Number of Display Characters
No. of
Diaplay Duty
Lin..
factor
l-line
display
2-line
display
1/8,
d/uty11
1/16
duty
Extension
Not
provided
Provided
Not
provided
Provided
HD44100H
HD66100F
9 pes.
(8 characters/ pc. )
5 pes.
(16 characters/pc.)
No. of Display
Characters
8 characters x 1 line
80 characters x 1 line
8 characters x 2 lines
4 pes. (8 characters
x 2 lines/pc.)
2 pcs.(16 characters x 2 lines/pc.)
40 characters x 2 lines
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
169
I
HD66780 (LCD - II A)
H066780 Block Diagram
...
'"
III
III
C
b.
III
C
I
•
"it
j jill
ID
....
C")
N
~
III
w a:
C
C
II)
a:
UU
C
~ :g ~ ~
IIII
"it
I/O Buffer
.-
> > > > >
,....
Character
Generator
RAM
(CG RAM)
512 bits
Character
Generator
ROM
(CG ROM)
III
co
Display Data
RAM
(DO RAM)
SOxs bits
12000 bits
L-~o====~r~~~~~~~~~JC!';§CD
"it
Cursor Blink
Control CirCuit
C
.~·S
Ee
t=u
Driver
C
HITACHI
170
Hitachi America,
Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66780 (LCD - II A)
Block Function
Registers
The HD66780 has two 8-bit registers, an
instruction register (IR) and a data register
(DR).
The IR stores instruction codes such as display clear and cursor shift, and address
information for display data RAM (DD RAM)
and character generator RAM (CG RAM). The
IR can be written from the MPU but not read
by the MPU.
The DR temporarily stores data to be written
into the DD RAM or the CG RAM and data to
be read out from DD RAM or CG RAM. Data
written into the DR from the MPU is automatically written into the DD RAM or the CG
RAM internally. The MPU also uses the DR for
data storage when reading data from the DD
RAM or the CG RAM. When the MPU writes
address information into the IR, the LCD-IIA
sends data to the DR from the DD RAM or the
CG RAM by internal operation. Data transfer
to the MPU is then completed by the MPU
reading DR. After the MPU reads the DR, the
LCD-IIA sends data in the DD RAM or CG
RAM at the next address to the DR for the
next read from the MPU. Register selector
(RS) signals select these two registers (table
2).
Busy Flag (BF)
When the busy flag is 1, the HD66780 is in the
internal operation mode, and instructions will
not be accepted. As table 2 shows, the busy
flag is output to DB 7 when RS = 0 and R/W
= 1. The next instruction must be written
after confirming that the busy flag is O.
to DD and CG RAM. When an instruction -for
address is written in IR, the address information is sent from IR to AC. Selection of either
DD or CG RAM is also determined concurrently by the instruction.
After writing into (or reading from) DD or CG
RAM display data, AC is automatically incremented by 1 (or decremented by 1). AC
contents are output to DBc-DBs when RS = 0
and R/W = 1, as shown in table 2.
Display Data RAM (DD RAM)
The display data RAM (DO RAM) stores display data represented in 8-bit character
codes. Its capacity is 80 x 8 bits, or 80 characters. The display data RAM (OD RAM) that
is not used for display can be used as general
data RAM. Relations between DD RAM addresses and positions on the liquid crystal
display are shown in figure 1.
The DO RAM adress (ADD) is set in the address
counter (AC) and is represented in hexadecimal.
When there are fewer then 80 display characters, the display begins at the head positon.
For example, 8 characters using an HD66780
are displayed as shown in figure 2.
When the display shift operation is performed, the DD RAM address moves as shown in
figure 3.
A 16-character display using an HD66780 and
an HD44100H is shown in figure 4.
Address Counter (AC)
The relation between display position and OD
RAM address when the number of display
digits is increased through the use of one
HD66780 and two or more HD44100Hs can be
considered an extension of figure 4.
The address counter (AC) assigns addresses
Since the increase can be 8 digits for each
Table 2 Register Selection
RS
R/W
o
o
o
Operation
IR write as internal operation (Display clear, etc)
Read busy flag (DB7) and address counter (DBo-DB6)
o
DR write as internal operation (DR to DO or CG RAM)
DR read as internal operation (DO or CG RAM to DR)
HITACHI
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171
I
HD66780 (LCD- II A)
Higher Order
+-Bits
AC
Lower Order --+
Bits
IAC61AC51AC41AC31AC21AC11ACoI
L
.---.!
Hexa- ~
decimal
Hexadecimal
Example : DO RAM address
4E
10 1
111010111
" - - 4 ---.../\'---- E --~I
1-line Display (N=O)
(Digit)
1
2
Hne
3
4
79 80
5
Display
+-Position
4E I 4F I+-00 RAM
.
.
. Address
(Hexadecimal)
I
I 00 I 01 I 02 I 03 104 1
Figure 1 DD RAM Address
(Digit)
2
1-line
3
4
5
6
7
8
I 00 I 01 I 02 I 03 I 04 I 05 I 06 I 07 I
Display
=~~~e~~
(Hexadecimal)
Figure 2 Eight-Character Display Example
kL~~
Display)
I 01 I 02 I 03 I 04 I 05 I 06 I 07 I 08 I
Figure 3 Display shift
(Digit)
1-line
2
3
4
5
6
7
a
g 10 11 12 13 14 15 16
~
Display
~~~::
I 00 I 01 I 02 103 104 105 106 107 1oal 09 1OA I 08 I OC I OD I OE I OF I
" - - - HD667aO Display ~ HD441 OOH Display - - f ' (Hexadecimal)
(Left
Shift
Display)
101 1021031041051061071 oal 09 1OA I 08 I OC I OD I OE I OF 110 I
(Right
Shift
Display)
14F I 00 I 01 I 02 103 104 105 106 107 1 Os I 09 1OA 1 08 I OC 1 OD 1 OE
1
Figure 4 Sixteen-Character Display Example
HITACHI
172
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66780 (LCD - II A)
fewer than 40 x 2 lines, the 2 lines from the
head are displayed. Note that the first line
end address and the second line start address
are not consecutive. For example, when an
HD66780 is used, 8 characters x 2 lines are
displayed as shown in figure 6.
additional HD44100H, up to 80 digits can be
displayed by externally connecting 9
HD44100Hs.
The same holds when HD66100Fs are used as
display drivers. Consisting of 80 outputs, one
HD66100F can display 16 digits (figure 5).
When display shift is performed, the DD RAM
address moves as shown in figure 7.
When the number of display characters is
(Digit)
1
2
3
4
5
6
7 8
Display
9 1011 121314151617 18 192021222324
l-line
Address
(Hexadecimal)
~
__________________
A
~A
HD661OOFIII
Display
I
HD66100F12H41
HD66100FISI
Display
Display
The last 40 outputs of the HD66100F(S)
are not ueed,
Figure 5 Extended Display
I
2-line Display (N = 1)
(Digit)
2
1-line
2-line
3
4
39
5
3 04
1 1 °422 1 °4 314
°400 1 °4 1
41
40
1 26 ! 271
..............................
Display
=:;~i~~~
~~~:.~~:.:~~:.~~~:.~~~:.~~~~~~..~..~..~..~..~..~..~..~.. ~.. ~...~..~..~..~.~~~~~:~6~6~:~6~7: f~:::~:cimal)
1
:.
(Digit)
2
3
4
5
6
7
1-line
00
01
02
03
04
05
06
2-line
40
41
42
43
44
45
46
8
Display
-POSition
07 -DO RAM
Address
(Hexadecimal)
47
Figure 6 Two-Line by Eight-Character Display Example
(Left
Shift
Display)
(Right
Shift
Display)
01
02
03
04
05
06
07
08
41
42
43
44
45
46
47
48
27
00
01
02
03
04
05
06
67
40
41
42
43
44
45
46
Figure 7 Two-Line Display Shift
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
173
HD66780 (LCD - II A)
16 characters x 2 lines are displayed as in
figure 8 when an HD66780 and an HD44100H
are used.
(Note: In a 5 x 7 dot + cursor display, only
the upper part, that is, 5 x 7 dots of 5 x 10
dots, is displayed.)
The relation between display position and DD
RAM address when the number of display
digits is increased by using one HD66780 and
two or more HD44100Hs, can be considered
an extension of figure 9.
Table 3 shows the relation between character codes and character patterns in the Hitachi standard HD66780AOO. User-defined
character patterns are also available by
mask-programmed ROM.
Since the increase can be 8 digits x 2 lines for
each additional HD44100H, up to 40 digits x
2 lines can be displayed by connecting 4
HD66780s (or 2 HD66100Fs) externally.
Character Generator RAM (CG RAM)
With the character generator RAM, the user
can rewrite character patterns by program.
With 5 x 7 dots, 8 character patterns can be
written and with 5 x 10 dots 4 patterns can
be written.
Character Generator ROM (CG ROM)
The character generator ROM generates 5 x
7 dot or 5 x 10 dot character patterns from 8bit character codes. A CG ROM has 240 types
of 5 x 10 dot character patterns built-in.
(Digit)
Write the character codes in the left columns
of table 3 to display character patterns stored
in CGRAM.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1-line
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
2-line
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
16
Display
-Position
OF -DO RAM
Address
4F
(Hexadecimal)
\~--- HD66780 Display ----'I\~---HD441 OOH Display _ _ _...II
(Left
Shift
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
Display)
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
(Right
27
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
67
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
Shift
Display)
Figure 8 Two-Line by Sixteen-Character Display Example
(Digit)
l-line
1
2
3
4
5
6
7
8
33 34 35 36 37 38 39 40
9 1011121314151617181920
00 01 0203 04 05 06 07 0809 OA 08 OC 00 OE OF 1011 1213
..........
Display
Position
2021 2223 2425 2627
~DD
RAM
address
2-line
4041 4243 4445 4647 4849 4A 48 4C 40 4E 4F 5051 52 53
L
HD667780
-L
Display
HD441 OOHII I
--L
Display
HD441 OOHI21131
Display
6061 6263 6465 6667
~ HD441 OOHI41 ~
Display
HD66100FIII ~ HD66100FI21
\
........_ -
Display
(Hexadecimal)
Display
/
----'
Figure 9 Two-Line Extended Display Example
HITACHI
174
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66780 (LCD - II A)
Table 3
Correspondence between Character Codes and Character Pattern
(Hitachi Standard HD66780AOO)
,~ 0000 00011001010011
x x x xOOOl
-
x x x xOOll
.5.
(4)
x x x xOl0l
-
-
xxxxOll0
(5)
(7)
(8)
-
xxxxl000
(1)
-
xxxxl001
(2)
-
x x x xl0l0
(3)
I--xxxxl0ll
x x x xll00
xxxxll01
x x x x 1110
(4)
-
-
:1:1: ::::;
·......-.-,..:-
-
.....
•-!
.. !
i..:!
I
I ••:.
:
(5)
(6)
(7)
(8)
.
8i-....
.=:::-.... ·i.....!
.... : :
·....
: : ....:
!- ...... : .: .:::=. i.:J
·.:.:..
·:::=.
··...:: .. ..:: ...ar: ::........... ..::I::· I::: i::::.:.: :•••::
.... ...:: J...••;
i :
••••5 -5-:
I •••:
.1 •••
~: to::: [ io:: -::
..1--
::
..:
••••• !i·:·i
..... .....
-! ..1
: =
::
..... ......
•
x x X x 1111
C: ::::; c· ............
(6)
-
xxxxOlll
·;-...
(3)
-
x x x xOl00
..... .... ...
E.:.! ·:::5 ·......:
-5
(2)
x x x xOO10
0100 0101 0110101 11 10001001 1010 1011 1100 1101 11101111
I
r··i
.....
...... ·..... ·I·..5
.... ·... I···
..... i···;
...:···5 ·:::i
-•••1
.
.:.:- ,:::: ·5···'
.......
..... ...... ...
-i···
... ..... .·....
··1·· 5 ·:···Ii .i ...=
... .....
5 r· i .. II.. ....
...
...
.
...
·
:::1· ::1·· ...1. ..... ·=.....:
.....
-I··:
.......: ..
.: .: .....••• .....••••....:1
. ........
..... .....
..:..
I a.
II
.:.-
5
..
..:
I •••••
........... .1.:-.e )
: I .. !
! i.:
-.,..... ....1 i ! t.··
·-1··
.....: :.:
...
:.
: .
...! .·~:I· i::: .
I •••:
..:
..:
•••••
..
I .. ::••1
·1···
:::::
.-.....
-.'....: ::;:: i) ..!... .....
.1•••
::-
I ••
-i
a•
. :i
...: r··1...
•••••
.
···:1 .... ..
......!. .....
....: :i:.. ......
··i·· .... ...
I
::i
•••1
...
n:
t:
Ii:
•••, I:!
....I ..:
I.
I ••
f i
..:.... I
Note: • The user can specify any pattern for character-generator ROM.
HITACHI
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175
HD66780 (LCD - II A)
As table 4 shows, an area that is not used for
display can be used as general data RAM.
Table 4 shows the relation between CG RAM
addresses and data and display patterns.
Table 4
Relation between CG RAM Address and Character Codes (DD RAM) and
Character Patterns (CG RAM Data)
For 5 x 7 -dot character patterns
Charac:terCodea
COD RAM Datal
6 5 4 3 2 1
7
Higher
---Order
Bits
0
0 0
CGRAM
Add.....
5 4 3 2 1 0
Lower
Order
Bits
0
*
Character Patterns
(CG RAM Datal
7 6 5 4 3 2 1 0
Higher
Lower
Order
Bits
0 0
0
0
0
0
0 0
0 1
1 0
1
Character
Pattern
Example (I)
1
1 0 0
1 0 1
1 1 0
1 1 1
0
0 0
0
*
0
0
1
o
0 1
o
*
1
*
*
1
0 0 0
0 0 1
o
0 0
0
*
1
1 1
Cursor
---Position
0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1
o
o
*
*
I
Notes:
Character
Pattern
Example (2)
*
*
0
1
*No effect
(Don't care)
1 0
1
Lower
1
*
*
1. Character code bits 0-2 correspond to CG RAM address bits 3-5 (3 bits: 8 characters).
2. CG RAM address bits 0-2 designate character pattern line position. The 8th line is the
cursor position and display is performed by logical OR with the cursor.
Maintain the 8th line data, corresponding to the cursor display position, in the 0 state for
cursor display. When the 8th line data is 1, bit 1 lights up regardless of cursor presence.
3. Character pattern row positions correspond to CG RAM data bits 0-4, as shown in the
figure (bit 4 being at the left end).
Since CG RAM data bits 5-7 are not used for display, they can be used for the general data
RAM.
4. As shown in table 3 and 4, CG RAM character patterns are selected when character code
bits 4-7 are all O. However, since character code bit 3 is ineffective, the R display in the
character pattern example, is selected by character code 00 (hexadecimal) or 08 (hexadecimal).
5. 1 for CG RAM data corresponds to selection for display and 0 for non-selection.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66780 (LCD - II A)
Table 4
Relation between CG RAM Address and Character Codes (DD RAM) and
Character Patterns (CG RAM Data) (Cont)
For 5 x 10 -dot character patterns
Character Cod..
IDD RAM Data)
6 5 4 3 2 1 0
Higher
Lower
---Order
Order --+
Bits
Bits
0 0 0 0 * 0 0 *
7
---------------.--------------------- ---------
CGRAM
Add.....
Character Patterns
ICG RAM Data)
7 6 5 4 3 2 1 0
2 1 0
Higher
Lower
Lower
Order ~
Order
Order
Bits
Bits
Bits
0 0 0
* * * 0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
1 0 1 0
* * *
--------------------------- --------- ------------------------------"-----.
1011
********
5 4 3
Higher
Order
Bits
0 0 0
0
0
0
0
0
0
0
1
1
11 11 00 01
1 1 1 0
111 1
0000
000 1
*
111001
101 0
o
1
1
100
1 0 1
1 1 0
1 1 1
Notes:
!
Character
Pattern
Example
Cursor
<-Position
t
* * * * * * * *
***
* * *
* * * * * * * *
1
1
* * * * * * * *
*No effect
(Don't care)
1. Character code bits 1, 2 correspond to CG RAM address bits 4, 5 (2 bits: 4 characters).
2. CG RAM address bits 0-3 designate character pattern line position. The 11th line is the
cursor position and display is performed by logical OR with cursor.
Maintain the 11 th line data corresponding to the cursor display position in the 0 state for
cursor display. When the 11th line data is 1, bit 1 lights up regardless of cursor presence.
Since the 12nd-16th lines are not used for display, they can be used for the general data
RAM.
3. Character pattern row positions are the same as 5 x 7 dot character pattern positions.
4. CG RAM character patterns are selected when character code bits 4-7 are all O. However,
since character code bit 0 and 3 are ineffective, P display in the character pattern example
is selected by character code 00, 01, 08 and 09 (hexadecimal).
5. 1 for CG RAM data corresponds to selection for display and 0 for non-selection.
HITACHI
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177
HD66780 (LCD -'- II A)
Timlng generation Circuit
The timing generation circuit generates timing signals to operate internal circuits such as
DD RAM, CG ROM, and CG RAM. RAM read
timing needed for display and internal operation timing by MPU access are separately
generated so that they may not interfere
with each other. Therefore, when writing
data to the DD RAM for example, there will
be no undesirable influence, such as flickering, in areas other than the display area. This
circuit also generates timing signals to operate the externally connected drivers
(HD44100H or HD66100F).
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 16 common signal drivers and 40
segment signal drivers. When the character
font and number of lines are selected by a
program, the required common signal drivers
automatically output drive waveforms. The
other common signal drivers continue to
output non-selection waveforms.
The segment signal driver has essentially the
same configuration as the driver LSI
HD44100H. Character pattern data is sent
serially through a 40-bit shift register and
latched when all needed data has arrived.
The latched data controls the driver for
generating drive waveform outputs.
The serial data can be sent to HD44100H or
HD66100Fs, externally connected in cascade,
to display an extended number of characters.
The LCD-IrA always starts sending serial
data at the display data character pattern
corresponding to the last address of the display data RAM (DD RAM).
Since serial data is latched when the display
data character pattern, corresponding to the
starting address, enters the internal shift
register, the HD66780 drives the head of the
display. The rest of the display, corresponding
to later addresses, are added with each additional HD44100H or HD66100F.
Cursor/Blink Control Circuit
The cursor/blink control circuit generates the
cursor or blinking. The cursor or blinking
appear in the digit residing at the display
data RAM (DD RAM) address set in the
address counter (AC).
When the address counter is (08)16, the cursor
position is as shown in figure 10.
HITACHI
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HD66780 (LCD -: II A)
AC6 AC5 AC4 AC3 AC2 AC1
o
ACO
o
o
In a 1-line display
(Digit)
2
3
4
5
6
7
8
9
1 00 1 01 1021031041051061071
T
10
11
1 09 1 OA 1
Cursor Position
Display
+-Position
DO RAM
+-Address
(Hexadecimal)
In a 2-line display
(Digit)
2
3
4
5
6
7
8
9
10
11
~
09
OA
1st line
00
01
02
03
04
05
06
07
2nd line
40
41
42
43
44
45
46
47
1/48 49 4A
Display
+-Position
DO RAM
+-Address
(Hexadecimal)
I
Cursor Position
Note: The cursor or blink appears when the address counter lAC) selects the character generator RA
ICG RAM). But the cursor and blink are meaningless.
The cursor or blink is displayed in the meaningless position when AC is the CG RAM address.
Figure 10 Cursor or Blink
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179
HD66780 (LCD - II A)
MPU Interface
The HD66780 can send data in either two 4bit operations or one 8-bit operation so it can
interface to both 4-and 8-bit MPU's.
transferred first, then the lower order 4 bits
(contents of DBo-DB3 when interface data is
8 bits long) is transferred.
When interface data is 4 bits long, data is
transferred using only 4 bus lines: DB4 - DB7.
DBo- DB3 are not used. Data transfer between
the HD66780 and the MPU completes when
4-bit data is transferred twice.
Check the busy flag after 4-bit data has been
transferred twice (one instruction). Two 4-bit
operations will then transfer the busy flag
and address counter data (figure 11).
Data of the higher order 4 bits (contents of
DB4 - DB7 when interface data is 8 bits long) is
When the interface is 8 bits long, data is
transferred using the 8 data bus lines DBoDB7.
Reset Function
Initializing by Internal Reset Circuit
The HD66780 automatically initializes (resets) when power is turned on using the
internal reset circuit. The following instructions are executed at initialization. The busy
flag (BF) is kept in busy state until initialization ends(BF = 1). The busy state lasts 10 ms
after Vcc rises to 4.5 V.
1. Display clear
2. Function set
a. DL = 1: 8-bit long interface data
b. N = 0: i-line display
c. F = 0: 5x7-dot character font
3. Display on/off control
a. D = 0: Display off
b. C = 0: Cursor off
c. B = 0: Blink off
4. Entry mode set
a. l/D = 1: + l(increment)
b. S = 0: No shift
Note: When power supply conditions in the
electrical characteristics are not met using
internal reset circuit, the internal reset circuit
will not operate normally and initialization
will not be performed. In this case initialize
by MPU according to initializing by instruction.
RS ____________________________
~/
R/W _ _ _ _ _~/
E
IR3
DB,
DBe
DB5
IRl
DB4
SF
AC3
AC6
AC2
DR2
AC5
AC4
Instruction (I R)
Write
DR6
ACO
Busy Flag (BF) and
Address Counter (AC)
Read
Data Register (DR)
Read
Figure 11 4-Bits Data Transfer Example
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HD66780 (LCD- II A)
InstructioDS
Only two HD66780 registers, the instruction
register (IR) and the data register (DR) can be
directly controlled by the MPU. Prior to
internal operation start, control information is
temporarily stored in these registers, to allow
interface from HD66780 internal operation to
various types of MPU's which operate at
different speeds or to allow interface to
peripheral control Ie's. HD66780 internal
operation is determined by signals sent from
the MPU. These signals include register
selection signals (RS), read/write signals
(R/W), anti. data bus signals (DBo-DB7), and
are here called instructions. Table 5 shows
the instructions and their execution time.
Details are explained in subsequent sections.
used most frequently. However, automatic
incrementing by 1 (or decrementing by 1) of
HD66780 internal RAM addresses after each
data write lessens the MPU program load.
The display shift especially can be performed
concurrently with display data write, enabling the designer to develop systems in
minimum time with maximum programing
efficiency. For an explanation of the shift
function in its relation to display, see table 7.
During internal operation, no instruction
other than the busy flag/address read
instruction will be executed. Because the
busy flag is set to 1 while an instruction is
being executed, check to make sure it is on 0
before sending an instruction from the MPU.
Instructions are of 4 types, those that:
1. Designate HD66780 functions such as
display format, data length, etc
2. Give internal RAM addresses
3. Perform data transfer with internal RAM
4. Others
In normal use., category 3 instructions are
Note: Make sure the HD66780 is not in the
busy state (BF = 0) before sending the
instruction from the MPU to the HD66780. If
the instruction is sent without checking the
busy flag, the time between first and next
instructions is much longer than the instruction execution time. See table 5 for a list of
each instruction's execution time.
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181
"~-'---~-'-
----
HD66780 (LCD- II A)
Table 5 Instructions
Execution Time
Code
(fcp
J,NJ:t 250
kHz)
Ina1rUetion
Clear
Display
o
0
0
0
0
0
0
0
Return
Home
o
0
0
0
0
0
0
0
Entry
Mode Set
o
0
0
0
0
0
0
Display
On/Off
Control
Cursor or
Display
Shift
Function
Set
o
0
0
0
0
0
0
o o o o
0
o o o
Set CG RAM 0
Address
o o
Set DO RAM 0
Address
o
Read
Busy Flag
& Address
Write Data
to CG or
DO RAM
Read Data
from CG or
DO RAM
Notes: 1.
o
1
*
I/O S
0
SIC R/L
OL N·
F
C
B
* *
* *
ACG
ADD
BF
0
0
AC
Write Data
Clears entire display and sets DO
RAM address 0 in address
counter
Sets DO RAM address 0 in
address counter. Also returns
display being shifted to original
position. DO RAM contents
remain unchanged
Sets cursor move direction and
specifies shift of display.
These operations are performed
during data write and read
Sets entire display on/off (D),
cursor on/off (C), and blink of
cursor pOSition character (B)
Moves cursor and shifts display
without changing DO RAM
contents
Sets interface data length (DL),
number of display lines (N) and
character font (F)
Sets CG RAM address. CG RAM
data is sent. and received after
this setting.
Set DO RAM address. DO RAM
data is sent and received after
this setti ng.
Reads Busy flag (BF) indicating
internal operation is being performed and reads address
counter contents
Writes data into DO RAM or CG
RAM
Read Data
I/O
I/O
S
SIC
SIC
R/L
R/L
DL
N
F
Reads data from DO RAM or CG
RAM
= 1: Increment
= 0: Decrement
= 1: Accompanies display shift
= 1: Display shift
= 0: Cursor move
= 1: Shift to the right
= 0: Shift to the left
= 1: 8 bits, DL = 0: 4 bits
= 1: 2 lines, N = 0: 1 line
=1:5x10dots,F=0:5x7dots
1.64 ms
1.64 ms
40 /is
40/is
40/iS
40/is
40/iS
40/is
o /is
46 /is
46 /is
BF
= 1: Internally operating
BF
= 0: Can accept instruction
DO RAM: Display data RAM
CG RAM: Character generator RAM
AcG: CG RAM address
ADD : DO RAM address
Corresponds to cursor
address
AC : Address counter used
for both DO and CG RAM
*
2.
No effect (Don't care)
3. Execution time changes when freguency changes.
Example: When fcp or fosc is 270 kHz:
250
40 /is x 270 = 37 /is
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HD66780 (LCD - II A)
Clear Display
1 when a character code is written into or
read from the DD RAM. The cursor or blink
moves to the right when incremented by 1
and to the left when decremented by 1. The
same applies to writing and reading of CG
RAM.
Clear display (figure 12) writes space code 20
(hexadecimal)(character pattern for character code 20 must be blank pattern) into all DD
RAM addresses. Sets DD RAM address 0 in
address counter. Returns display to its original status if it is shifted. In other words, the
display disappears and the cursor or blink
goes to the left edge of the display (the first
line if 2 lines are displayed). Sets l/D = 1
(increment mode) of entry mode. S of entry
mode does not change.
S: Shifts the entire display either to the right
or to the left when S is 1; to the left when l/D
= 1 and to the right when l/D = O. Thus it
looks as if the cursor stands still and the
display moves. The display does not shift
when reading from the DD RAM. Writing into
or reading out of the CG RAM does not shift
the display. When S = 0, the display does not
shift.
RetumHome
Return home (figure 13) sets the DD RAM
address 0 in address counter. Returns display
to its original status if it was shifted. DD RAM
contents do not change. The cursor or blink
go to the left of the display (the first line if 2
lines are displayed).
Display On/Off Control.
D: The display is on when D = 1 and off when
D = 0 (figure 15). When off 'due to D = 0,
display data remains in the DD RAM. It can be
displayed immediately by setting D = 1.
En~ModeSet
I/D: l/D (figure 14) increments (l/D
C: The cursor is displayed when C = 1 and is
not displayed when C = O. Even if the cursor
disappears, the function of lID, etc does not
= 1) or
decrements (l/D = 0) the DD RAM address by
RS
Code
1
0
DBo
R/W DB7
1
0
1
0
1
0
0
0
0
0
0
1
1
1
Figure 12 Clear Display Instruction
RS
Code
1
0
R/W DB7
1
0
·1
0
DBo
1
0
0
0
0
0
*
1
* Don't care
Figure 13 Return Home Instruction
RS
Code
I
0
R/W OB7
1
0
1
Figure 14
RS
0
OBo
I
0
En~
0
0
0
11/0
1
S
1
Mode Set Instruction
R/W DB7
OBo
cOdelolololo
0
0
Figure 16 Display On/Off Control Instruction
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.-
..
~-
..•..
-.---.~---
183
HD66780 (LCD - II A)
change during display data write. The cursor
is displayed using 5 dots in the 8th line when
the 5 x 7-dot is selected and 5 dots in the
11th line when the 5 x 10-dot character font is
selected (figure 16).
B: The character indicated by the cursor
blinks when B = 1. The blink is displayed by
switching between all blank dots and display
characters at 409.6 ms intervals when fcp or
fosc = 250 kHz (figure 15). The cursor and the
blink can be set to. display simultaneously.
(The blink time changes according to the
reciprocal of fcp or fosc. For example, 409.6 x
~~g
= 379.2 ms when fcp = 270 kHz.)
writing or reading display data. This function
is used to correct or search the display. In a 2line display, the cursor moves to the 2nd line
when it passes the 40th digit of the 1st line.
Notice that the 1st and 2nd line displays will
shift at the same time. When. the displayed
data is shifted repeatedly each line only
moves horizontally. The 2nd line display does
not shift into the 1st line postion.
Table 6 shows how SIC and R/L control
shifting.
Address counter (AC) contents do not change
if the only action performed is shift display.
Function Set
Cursor or Display Shift
Cursor or display shift (figure 17) shifts cursor
position or display to the right or left without
DL: DL (figure 18) sets interface data length.
Data is sent or received in 8-bit length (DB7DBa) when DL = 1 and in 4-bit lengths (DBT
Table 6 Cursor or Display Shift Control
SIC
R/L
o
o
Function
Shifts the cursor position to the left
(AC is decremented by one)
Shifts the cursor position to the right
(AC is incremented by one)
Shifts the entire display to the left. The cursor follows the display shift
Shifts the entire display to the right. The cursor follows the display shift
o
o
Ii
I-
--Cursor
arm
_
......
5 x 7 -dot character
5 x 1O-dot character
font
Alternating display
font
Cursor Display Example
Blink Display Example
Figure 16 Cursor and Blink Display
RS
Code
o
R/W DB7
o
o
DBa
o
o
ISIC IRill * I * I * Don't care
Figure 17 Corsor or Display Shift Instruction
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HD66780 (LCD - II A)
DB4) when DL = O.
When the 4-bit length is selected, data must
be sent or received twice.
from the MPU for the CG RAM.
N: N sets number of display lines.
Set DO RAM address (figure 20) sets the DO
RAM address binary AAAAAAA into the
address counter. Data is then written or read
from the MPU for the DO RAM.
Set DD RAM Address
F: F sets character font. See table 7.
Note: Perform the function set at the head of
the program before executing any. instructions (except "Busy flag/address read"). From
this point, the function set instruction cannot
be executed unless the interface data length
is changed.
However, when N = 0 (l-line display),
AAAAAAA is 00-4F (hexadecimal), when N
= 1 (2-line' display), AAAAAAA is 00-27
(hexadecimal) for the first line, and 40-67
(hexadecimal) for the second line.
Set CO RAM Address
Read Busy Flag and Address
Set CG RAM address (figure 19) sets the CG
. RAM address binary AAAAAA into the
address counter. Data is then written or read
Read busy flag and address (figure 21) reads
the busy flag (BF) that indicates the system is
now internally operating on a previously
Table 7 Function Set N and F
No. of
Dleplay Lines Character Font
1
5x7 dots
1
5x10dots
2
5x7 dots
NF
00
01
1
*
Note:
Duty
Factor
1/8
1/11
1/16
* Don't care
RS
Code
Remarks
Cannot display 2 lines with 5 x 1O-dot character font
R/W DB7
DBo
I DL I N
I0 I0 I0 I0
F
* I * I * (Don't care)
Figure 18 Function Set Instruction
RS
cOdelO
DBo
R/W DB7
0
0
Higher
-Order Bits
Lower
Order Bits
Figure 19 Set CO RAM Address Instruction
RS
R/W DB7
DBo
Higher
-Order Bits
Lower
Order Bits
Figure 20 Set DD RAM Address Instruction
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185
HD66780 (LCD - II A)
received instruction. BF = 1 indicates that
internal operation is in progress. The next
instruction will not be accepted until BF is set
to O. Check the BF status before the next
write operation (figure 22).
tion of CG RAM or DD RAM address setting.
After writing, the LCD-ITA automatically
increments or decrements the address by 1,
according to entry mode.
Read Data from CG or DD RAM
At the same time, the value of the address
counter expressed in binary (AAAAAAA) is
read out. The address counter is used by both
CG oEUld DD RAM addresses, and its value is
determined by the previous instruction.
Address contents are the same as in set CG
RAM address and set DD RAM address.
Write Data to CG or DD RAM
Write data to CG or DD RAM (figure 23)
writes binary 8-bit data DDDDDDDD to the
CG or the DD RAM.
Whether the CG or DD RAM is to be written
into is determined by the previous specifica-
RS
Read data from CG or DD RAM (figure 24)
reads binary 8-bit data DDDDDDDD from the
CGorDDRAM.
The previous designation determines
whether the CG or DD RAM is to be read.
Before entering the read instruction, you
must execute either the CG RAM or DD RAM
address set instruction. If you do not the first
read data will be invalidated. When serially
executing read instructions, the next address
data is normally read from the second read.
The address set instruction need not be
executed just before the read instruction
when shifting the cursor by cursor shift
R/W OB?
OBo
Code ,----[0-,--1---,-IB_F-'.-I_A
~A~A--"--A--,--A-L-A--,--IA--,I
Lower
Order Bits
Higher
-Order Bits
Figure 21 Read Busy Flag and Address Instruction
RS
R/W
___-J!
\~----
E
Internal
Internal Operation
No
DB7 ~B-U-S""'y~r7T.""T1I'"B-us"i?/i7:>"707~Tm77\BUS~
Instruction
Write
I
Busy Flag
Check
I
Busy Flag
Check
I
Busy Flag
Check
I
Instruction
Write
Figure 22 Example of Busy Flag Check Timing Sequence
RS
Code
OBo
R/W OB7
I0 I0 I0
0
0
0
0
0
I0 I
Lower
Order Bits
<- Higher
Order Bits
Figure 23 Write Data to CG or DD RAM Instruction
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HD66780 (LCD- II A)
instruction (when reading out of DD RAM).
The cursor shift instruction operation is the
same as that of the DD RAM's address set
instruction.
After a read, the entry mode automatically
increases or decreases the address by 1.
However, display is not shifted no matter
what the entry mode is.
Note: The address counter (AC) is automatically incremented or decremented by 1 after
write instructions to either CG RAM or DD
RAM. RAM data selected by the AC cannot
then be read out even if read instructions are
executed. The conditions for correct data
read out are: execute either the address set
instruction or cursor shift instruction (only
with DD RAM), then just before reading out,
execute the read instruction from the second
time the read instruction is sent.
How to Use the H066780
Interface to 8-Bit MPU
When Connecting to 8-Bit MPU Through
PIA: Figure 25 is an example of using a PIA or
I/O port (for a microcontroller) as an interface
device. Input and output of the device is TTL
compatible.
In the example, PBa to PB? are connected to
the data buses DBa to DB? and P Aa to P A2 are
connected to E, R/W and RS respectively.
I
Connecting Directly to the 8-Bit MPU Bus:
Figure 26 shows the LCD-IIA connected
directly to an HD6800.
Example of Interfacing to the HD6805: Figure 27 shows the LCD-IIA connected directly
to an HD6805.
R!W DB7
RS
Code
Pay attention to the timing relation between
E and other signals when reading or writing
data and using PIA as an interface.
I
1
DBa
I DID I
D
D
D
D
D
I D I
Lower
Order Bits
<- Higher
Order Bits
Figure 24 Read Data from CG or DD RAM Instruction
HD68BOO
A'5
A'4
A'3
A,
Ao
R!W
VMA
Q..
!.!!!
0
Iu
:2
:>
CT
::J
><
·c
1;;
II
I
I
0:
o
0
~
0
q.
1\
J:
8
;q.
I
0
J:
;;::
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I
I
I
I
I
I
I
I
I
I
I
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Va
V5
V4
V3
V2
v,
VEE
GND
Vee
M
(/) .::; .:1 ell
.::;
U J: J: el, I - u-(/)(/)
0
III
:E
0
.. n
. -
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v,
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u J: J: el,
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----'
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f\r-
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~
0
q.
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uu
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u u
w
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CIO
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CD
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c5
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Figure 36 Example of Connecting HD44100H to HD66780
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HD66780 (LCD - II A)
0
II
C
~
0IX)
\
V4
u..
~3
8
V~
VEE
GND
iii
CD
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::t:
-;:
Vee
M
-I
::t:
C
III
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C~
ClI I---
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~
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V~
VI
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CD
CD
-;:
GND
Vee
M
::t:
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::t:
C
C~
ClI
III
I--
I
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15
c
a
0
C
V
~
/").
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-;:
~2
V~
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UU
III
ii
00
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w
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8
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Figure 37 Example of Connectlng HD66100F to HD66780
HITACHI
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195
- - - - - - - - - - - - - - --------------------- - - - - - - - - - - - - - - - -
~-------------
---~-~--
HD66780 (LCD- II A)
Instruction and Display Correspondence
8-blt Operation, 8-digit x l-line Display
(UsJng Internal Reset): Table 10 shows an
example of an 8-bit x 1-line display in 8-bit
operation. The HD66780 functions must be
set by the function set instruction prior to
display. Since the display data RAM can store
data for 80 characters, as explained before,
the RAM can be used for advertising displays
when combined with display shift operation.
Since the display shift operation changes
display position only and DD RAM contents
remain unchanged, display data entered first
can be output when the return home operation is performed.
4-blt .Operation, 8-dlgit x l-line Display
(Using Internal Reset): The program must set
functions prior to 4-bit operation. Table 11
shows an example. When power is turned on,
8-bit operation is automatically selected and
the LCD-IIA attempts to perform the first
write as an 8-bit operation. Since nothing is
connected to DBo-D~, a rewrite is then
required. However, since one operation is
completed in two 4-bit accesses, a rewrite is
needed to set the functions (see table 11 step
moves from the first to the second line after
the 40th digit of the first line has been written. Thus, if there are only 8 characters in the
first line, the DD RAM address must be set
after the eighth character is completed (see
table 12). Note that the first and second lines
of the display are shifted.
In the example, the display is shifted when
the cursor is on the second line. However, if
the shift operation is performed when the
cursor is on the first line, both the first and
second lines move together. When you repeat
the shift, the display of the second line will
not move to the first line, the same display
will only move within each line many times.
Note: When using the internal reset, the
conditions in "Power Supply Condition Using
Internal Reset Circuit" must be satisfied. If
not, the HD66780 must be initialized by
instruction. (See "Initializing by Instruction")
Initializing by Instruction
Thus, DB4-DB7 of the function set is written
twice.
If the power supply conditions for correctly
operating the internal reset circuit are not
met, the LCD-ITA must be Initialized by
instruction.
When interface is 8 bits long, use the initialization procedure in figure 38.
8-blt Operation, 8-digit x 2-lIne Display:
For a 2-line display, the cursor automatically
When interface is 4 bits long, use the initialization procedure in figure 39.
3).
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HD66780 (LCD - II A)
Table 10
a-Bit Operation, a-Character
Reset)
x
1-Line Display Example (Using Internal
Step
No.
2
InlltrUction
Power Supply On (HD66780 is
initialized by the internal reset circuit)
Function Set
RS R;WDB 7'
DBo
o
3
0 0 0
0
Entry Mode Set
1 0
Write Data to CG RAM/DO RAM
100
6
Sets to 8-bit operation and selects 1line display and one of the three character fonts. (Number of display lines
and character font cannot be changed
after this.)
Turns on display and cursor. Entire
display is on space mode because of
initialization.
Sets mode to increment the address by
one and to shift the cursor to the right
at the time of write to the DD/CG
RAM. Display is not shifted.
Writes "H". The DO RAM has already
been selected by initialization when the
power is turned on.
The cursor is incremented by one and
shifted to the right.
Writes "I".
Display On/Off Control
0 0 0 0 0 0 001
5
Operation
Initialized. No display appears.
00* *
0000001
4
Display
1 001
000
Write Data to CG RAM/DO RAM
100
1 001
0
0
7
8
Write Data to CG RAM/DO RAM
100
9
1 001
0
0
Entry Mode Set
000
0
0
0
IHITACHI
0
10
Write Data to CG RAM/DO RAM
11
Write Data to CG RAM/DO RAM
1000100000
100 1
001
IHITACHI
1 0
II TACH I
iTACHI
M
Writes "I".
Sets mode for display shift at the time
of write.
Writes space.
Writes "M".
12
13
Write Data to CG RAM/DO RAM
100100111
14
Cursor or Display Shift
00000100**
15
Cursor or Display Shift
00000100**
16
Write Data to CG RAM/DO RAM
17
Cursor or Display Shift
100
1 000
0000011
18
Cursor or Display Shift
0000010
19
0
1
* *
**
Write Data to CG RAM/DO RAM
100
1 001
1 0
MICROKO
MICROKO
MICROKO
ICROCO
MICROCO
MICROCO
ICROCOM
Writes "0".
Shifts only the cursor position to the
left.
Shifts only the cursor position to the
left.
Writes "C" (correction).
The display moves to the left.
Shifts the display and cursor position to
the right.
Shifts only the cursor position to the
right.
Writes "M".
20
21
Return Home
0000000010
IHITACHI
Returns both display and cursor to the
original position (address 0).
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197
HD66780 (LCD- II A)
Table 11
4-Bit Operation, a-Character
Reset)
x I-Line Display Example (Using Intemal
Step
No.
2
o
3
4
o
o
0
o
0
0
0
0
o
o
o
*
*
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
0
Entry Mode Set
0
0
0
0
Write Data to CG RAM/DD RAM
1
1
0
0
0
1
1
0
0
0
Oparation
Initialized. No display appears.
Sets to 4-bit operation.
In this case, operation is handled as 8
bits by initialization, and only this
instruction completes with one write.
Sets to 4-bit operation and selects 1line display and one of the three character fonts. 4-bit operation starts from
this point on and resetting is needed.
(Number of display lines and character
font cannot be changed after this.)
Turns on display and cursor. Entire
display is in space mode because of
initiaUzation.
Sets mode to increment the address by
one and to shift the cursor to the right,
at the time of write, to the DO/CG
RAM. Display is not shifted.
Writes "H". The DD RAM has already
been selected by initialization when the
power is turned on. The cursor is incremented by one and shifted to the
right.
Display On/Off Control
0
0
6
0
Function Set
0
0
5
Display
Instruction
Power Supply On (HD66780 is
initialized by the internal reset circuit)
Function Set
RS R/W DB7
0
0
After this, control is the same as 8-bit operation.
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HD66780 (LCD - II A)
Table 12
8-Blt Operation, 8-Character X 2-Llne Display Example (Using Internal
Reset)
Step
No,·
lnatruction
1
Power Supply On (HD66780 is
intialized by the internal reset circuit)
2
Function Set
RS ~DB 7'
0 0 0 0
0
Display On/Off Control
0 0 0 0 0 0 1
3
4
5
Dieplay
Entry Mode Set
0 0 0 0 0
0
0
Sets to 8-bit operation and selects 2line display and one of the three character fonts.
DBo
* *
0
1
0
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 0 0 0
IH
6
7
8
9
10
11
12
13
14
15
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 0 0
Set DO RAM Address
0 0 1 1 0 0 0
0
0
IHITACHI
0
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 1 0
Entry Mode Set
0 0 0 0 0
0
0
HITACHI
MICROCO
HITACHI
MICROCO
1
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 1 0
Return Home
0 0 0
0
0
0
0
0
IHITACHI
I~ITACHI
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 1. 1
1
ITAC H I
ICROCOM
0
Operation
Initialized. No display appears.
HITACHI
MICROCOM
Turns on display and cursor. All display
is in space mode because of initialization.
Sets mode to increment the address by
one and to shift the cursor to the right,
at the time of write, to the DD/CG
RAM. Display is not shifted.
Writes "W. The DO RAM has. already
been selected by initialization when the
power is turned on.
The cursor is incremented by one and
shifted to the right.
Writes "I".
Sets RAM address so that the cursor
may be positioned at the head of the
2nd line.
Writes "M".
Writes "0".
Sets mode for display shift at the time
of write.
Writes HM". Display is shifted to the
left.
The first and second lines' shift is
operated at the same time.
Returns both display and cursor to the
original position (address 0).
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199
HD66780 (LCD - II A)
(
Power on
Wait more than 15 ms
after Vcc rises to 4.5 V
RS R/W DB7 DBe DBs DB4 DB3 DB2 DB, DBc
I BF cannot be checked before this instruction
0
Function set (Interface is 8 bits long)
0
0
0
1
1
*
*
*
*
Wait more than 4.1 ms
RS R/W DB7 DBe DB5 DB4 DB3 DB2 DB, DBc
0
0
0
0
1
1
*
*
*
*
I BF cannot be checked before this instruction
Function set (Interface is 8 bits long)
Wait more than 100 ps
RS R/W DB7 DBe DBs DB4 DB3 DB2 DB, DBc
0
0
0
1
1
0
*
*
*
*
IBF cannot be checked before this instruction
Function set (Interface is 8 bits long)
BF can be checked after the following instructions.
When BF is not checked, the waiting time between
instructions is longer than the execution instruction
time (see table 5).
RS R/W DB7 DBe DBs DB4 DB3 DB2 DB, DBc
0
0
0
1
1
F
N
0
* *
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
I/D
S
!
Initialization ends
0
Function set (Interface is 8 bits long.
Specifiy the number of display lines and character font.)
The number of display lines and character font cannot
be changed afterwards.
Display off
Display Clear
Entry Mode Set
Figure 38 Initialization by Instruction, Eight-Bit Interface
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HD66780 (LCD - II A)
(
Power on,
I
Wait more than 15 ms
after V cc rises to 4.5 V
I
1
RS R/W DB7 DBe DB5 DB4
I SF
0
Function set (Interface is 8 bits long)
0
0
0
1
1
I
I
Wait more than 4.1 ms
I
I SF ,cannot be checked before this instruction
RS R/W DB7 DBe DB5 DB4
0
0
0
0
cannot be checked before this instruction
1
1
1
Function set (Interface is 8 bits long)
I
Wait more than 100 J.ls
I
RS R/W DB7 DBe 'DB5 DB4
I SF cannot be checked before this instruction
0
Function set (Interface is 8 bits length)
0
0
0
1
1
II
I
RS R/W DB7 DBe DB5 DB4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
F
0
0
N
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
I/O
S
~
*
Initialization ends
*
SF can be checked after the following instructions.
When SF is not checked, the waiting time between
instructions is longer than the execution instruction
time (see table 5).
Function set (Set interface to be 4 bits long.)
Interface is 8 bits long.
Function set (Interface is 4 bits long. Specify the number of display lines and character font.)
The number of display lines and character font cannot
be changed afterwards.
Display off
Display Clear
Entry Mode Set
Figure 39 Initialization by Instruction, Four-Bit Interface
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201
HD66780 (LCD- II A)
LCD-II and LCD-IIA
Table 13 shows the differences between the
LCD-II and LCA-IIA.
There are two types of multiplex waveforms
for LCD driving: A and B. A type, shown in
figure 40, is used for alternation in 1 frame,
and B type, shown in figure 41, for alternation
in 2 frames. B type has better display quality
in highly multiplexed drive.
Table 13 Functions Comparison between LCD-II and LCD-IIA
Item
Display RAM
(Maximum number of
display characters)
* Character generator ROM
(Kinds of characters)
Character generator RAM
(Number of characters)
LCD driving terminals
(Maximum number of
display characters/
unit)
Character font
(with a cursor)
Multiplexing duty ratio
* LCD driving voltage
1/4 bias
1/5 bias
* LCD driving waveform
*Bus timing
Instruction codes
Power-on reset circuit
Oscillator
(Frequency)
Interface
Package
Pin arrangement
Note:
LCD-II (HD44780)
80 bytes (80 characters)
LCD-IIA (HD66780)
Same as LCD-II
7200 bits
192 characters
5 x 7: 160 characters
5 x 10: 32 characters
64 bytes
(8 characters)
16 COMs
40 SEGs
(16 characters)
12000 bits
240 characters
5 x 10: 240 characters
Note
Same as LCD-II
Same as LCD-II
5x8 dots
5x11 dots
1/8.1/11.1/16
3.0 to 11 (v)
Same as LCD-II
4.6 to 11 (v)
3.0 to Vee (v)
A waveform
1. 1.5 MHz
11 instructions
Yes
Ceramic filter. Rf.
external clock
(250 kHz)
HD44100H
FP-80. FP-80A
Refer to p.98
B waveform
2 MHz
Same as LCD-II
Same as LCD-II
Same as LCD-II
3.0 to Vee (V)
Vec to V5 (V)
See figures 40.41
HD44100H or HD66100F
Same as LCD-II
Same as LCD-II
* indicates the modified items on LCD-IIA.
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HD66780 (LCD - II A)
Common
I
,
I
Segmentl!-- - - - I
Common-segment
,,
""'1.0----,....----: 1 frame
1 frame
I
I
1
Figure 40 A-Type Waveforms (1/3 Duty Factor, 1/3 Bias)
Common
Segment
Common-segment
f1rv1rn-r1'
I
,
,
I
I
I
lrUlrlIUUUl
,
I
,
I
n
n n n
n n n
rUULfUUU[
,
,
1
1
I.
.,
.1
1 frame ,
Figure 41 B-Type Waveforms (1/3 Duty Factor, 1/3 Bias)
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203
HD66780 (LCD- II A)
Character Pattern Development
Procedure
The numbers in the above figure correspond
to the following operations:
1. Determime the correspondence between
character codes and character patterns.
2. Create a listing indicating the correspondence between EPROM addresses and
data.
3. Program character patterns in the
EPROM.
4. Send the EPROM to Hitachi.
5. Hitachi performs computer processing
with the EPROM to create a character
pattern listing and sends it to the user.
6. If there is no problem in the character
pattern listing, Hitachi creates trial LSIs
and sends samples to the user. The user
evaluates the samples. When it is confirmed that character patterns are correctly writte.n, mass production of LSI is
started.
Hitachi
CD
Back to
start
®
Figure 42 Character Pattern Development Procedure
HITACHI
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HD66780 (LCD - II A)
Character Pattern Program Method
The relationship between the EPROM
address and character pattern is shown in
table 14.
In order to evaluate ROM patterns, we recommend to use our LCD controller HD61830.
We also supply LCD control board (CB1026R).
Table 14 Character Data in EPROM
Data
EPROMAcklreea
(right sile up)
All
(LSB)
AID As
As
A7
As
0
0
A6
0
A4,
A3
A2
AI
Ao
0
0
0
0
0
0
0
0
0
0
0
00
01
02
03
04
06
06 07
0
0
0
0
0
0
0
a
0
0
000
o
0
o
0
o
o
0
o
o
Character code
Notes: 1.
2.
3.
4.
Line code
EPROM Data 06-07 are invalid
Data uOu must be programed at 11th line (cursor position).
Data at 12-1 6th line are invalid
Data at 00 locate at the left side of screen. (The, relation between the bit number and position
is reversed, compared with H044780. )
.
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205
HD66780 (LCD - II A)
Handling Unused Character Patterns
a. When unused character patterns are
not programed
1. EPROM data outside the character pattern area
If an unused character code is written
in the LCD-II DO RAM, all dots are lit.
Ignored by the character generator ROM
for display operation so it can be 0 or 1.
No programming for a character pattern is equivalent to all bits lit. (This is
because the EPROM is filled with 1
when the EPROM is erased.)
2. EPROM data in CG RAM area
Ignored by the character generator ROM
for display operation so it can be 0 or 1.
b. Program 0 for unused character patterns
3. EPROM data used when the user does not
use any LCD-II character pattern
Nothing is displayed even if unused
character codes are written in LCD-II
DO RAM. (It is equivalent to space.)
Handled in one of the two ways explained
below. Select one of two ways according
to the user application.
Absolute Maximum Ratings
Item
Symbol
RatIng
power Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
VT
-0.3 to Vee + 0.3
V
Operating Temperatura
Topr
-20 to +75
"C
Storage Temperature
Tstg
-55 to +125
·c
Unit
Notes: 1.lf LSls are used above the absolute maximum ratings, they may be permanently destroyed.
USing them within electrical characteristic limits is strongly recommended for normal operation. Use beyond these conditions will cause malfunction and poor reliability.
2.AII voltage values are referred to GND = 0 V.
3. Applies to V1 to V5. The relation: Vee~V1 ~V3~V4~V5~GND must be maintained.
(high
to
low)
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HD66780 (LCD - II A)
Electrical Characteristics
DC Electrical Characteristics (Vee
Item
Input High Voltage (1)
Input Low Voltage (1)
=5V
Symbol Min
VIH'
Input High Voltage (2)
VIL1
VIH2
Input Low Voltage (2)
VIL2
Output High Voltage (1 )(TTL)
VOH'
± 10%, Ta
Typ
2.3
Max
Vee
0.6
Vee -1.0 -
Vee
1.0
2.4
0.4
= -20 to
Unit
V
(12)
V
-loH = 0.205 mA
(3)
V
10L
= 1.6 mA
(3)
V
-loH = 0.04 mA
(4)
10L = 0.04 mA
±Id = 0.05 mA
to each COM Pin
±Id = 0.05 mA
to each SEG Pin
Vin = 0 to Vee
(4)
Output Low Voltage (2)(CMOS)
VOL2
Driver On Resistance (COM)
ReoM
O.1Vee V
20
kCl
Driver On Resistance (SEG)
RSEG
30
kCl
125
250
,..A
0.55
0.8
mA
0.35
0.6
mA
-1
-Ip
50
Power Supply Current (1)
Power Supply Current (2)
lce2
(12)
V
VOH2
Pull up MOS Current
(2)
V
VOL1
Input Leakage Current
Note
(2)
Output High Voltage (2)(CMOS)
-
Test Condition
V
Output Low Voltage (1 )(TTL)
O.9Vee
+75 ·C)
,..A
Vee = 5 V
Ceramic filter oscillation
Vee = 5 V,
fose = 250 kHz
Rf oscillation,
External clock operation
Vee = 5 V,
fose = fcp = 270 kHz
(10)
(10)
(5)
(6)
(6)
(11 )
.~~~~~.~~.~~?~~_.~::>J
IIIII!I/!
~
Ie Ii!
;!
1! t:! ;: gJJBllOJm!L
Each bit data of display RAM corresponds to on/off
state of each dot of a liquid crystal display to provide
more flexible than character display.
The HD441 02CH is produced by the CMOS process.
Therefore, the combination of HD441 02CH with a
CMOS microcontrollercan complete portable batterydriven unit ntilizing the liquid crystal display's low
power dissipation.
The combination of HD44102CH with the row
(common) driver HD44103CH facilitates dot matrix
liquid crystal graphic display system configuration.
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HD44102CH
Features
•
•
•
•
•
•
•
•
•
•
•
Dot matrix liquid crystal graphic display
column driver incorporating display RAM
Interfaces with 4-bit or 8-bit MPU
RAM data directly displayed by internal display
RAM
RAM bit data 1: On
RAM bit data 0: Off
Display RAM capacity: 50 x 8 x 4 (1600 bits)
Internal liquid crystal display driver circuit
(segment output): 50 segment signal drivers
Duty factor (can be controlled by external input
waveform)
- Selectable duty factors: 1/8, 1/12, 1/16,
1/24, 1/32
Wide range of instruction functions
- Display Data Read/Write, Display On/Off,
Set Address, Set Display
- Start Page, Set Up/Down, Read Status
Low power dissipation
Power supplies: Vee 5 V ± \0%, VEE 0 to -5 V
CMOS process
80-pin flat plastic package
HITACHI
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217
HD44102CH
Block Diagram
>~
~
>~
~
f
'(3
::Iii
~
!!!.
~
'(3
~
!!!.
0
I
'(3
.c
ilr
I:!
!
0
~
i
0
3
i0
,
i;
0
ii
co
...xx
~
N
):
HITACHI
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HD44102CH
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
-0.3 to +7.0
V
1
VEE
Vep-13.5 to Vep + 0.3
V
Vu
VT2
-0.3 to Vep + 0.3
V
1,2
VEE -0.3 to Vep + 0.3
V
3
Operating temperature
Tep!
-20 to +75
·C
Storage temperature
TBIg
-55 to +125
·C
Supply voltage (1)
Vep
Supply voltage (2)
Input voltage (1)
Input voltage (2)
Notes: 1. Referenced to GND = O.
2. Applied to input terminals (except V1, V2, V3, and V4), and I/O common terminals.
3. Applied to terminals V1. V2. V3, and V4.
Electrical Characteristics
(Vee
= +5 V ±10%, GND = 0 V. VEE =0 to -5.5 V. Ta =-20 to 75 °C) (Note4)
Item
Symbol
Min
Input high voltage (CMOS)
VIHC
0.7xVep
-
Vile
VIIff
-
V
Vee
0.3 x Vee V
5
0
2.0
Vee
+0.8
6
0
-
V
V
6
Output high voltage
VILT
VOH
V
IOH=-250~A
7
Output low voltage
VOL
- +0.4
V
IOL" +1.6 mA
7
Vi-Xj ON resistance
RON
-
7.5
kn
VEE =-5 V ± 10%,
1
~A
VIN .. Vep to GND
8
2
~
kHz
VIN = Vep to VEE
,1, ,2 frequency
9
~
felk = 200 kHz frame .. 11
Input low voltage (CMOS)
Input high voltage (TTL)
Input low voltage (TTL)
Typ Max
+3.5
Unit Test condition
Note
5
Load current 100 ~A
Input leakage current (1)
IILl
-1
Input leakage current (2)
111.2
-2
Operating frequency
feLK
25
Dissipation current (1)
lepl
-
- 100
280
10
65 Hz during display
Dissipation current (2)
lep2
-
500
~
Access cycle 1 MHz
12
at access
HITACHI
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219
HD44102CH
Notes: 4.
5.
6.
7.
8.
Specified within this range unless otherwise noted.
Applied to M, FRM, CL, BS, RST,cjl1, cjl2.
Applied to CS1 to CS3, E, 0/1, RIW and DBO to DB7.
Applied to DBa to DB7.
Applied to input terminals, M, FRM,CL, BS, RST, cjl1, cjl2, CS1 to CS3, E, 0/1 and RIW,
and· 1/0 common terminals DBa to DB7 at high impedance.
9. Applied to V1, V2, V3, and V4.
10. cjl1 and cjl2 AC characteristics.
Symbol
Min
Typ
Max
Unit
Duty factor
Duty
20
25
%
Fall time
~
t,
30
100
100
Rise time
Phase difference time
t12
Phase difference time
~1
0.8
0.8
ns
J.lS
I1s
40
Tl + Th
il
ns
J.lS
l
O.7Vec
cjl1 O.5Vec
O.3Vec
.
112
1I t ,
cjl2
felK " -11i
T
O.7Vec
O.5Vee
O.3Vec
O.5Vec
1+ h
DuTY= TT11i xI00(%)
1+ h
t,
It
11. Measured by Vee terminal at no output load, at 1/32 dury factor, and frame frequency.
of 65 Hz, in checker pattern display. Access from the CPU is stopped.
12. Measured by Vec terminal at no output load, 1/32 duty factor and frame frequency of
65 Hz.
HITACHI
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HD44102CH
Interface AC Characteristics
Typ
Item
Symbol
Min
Ecycle time
'eye
1000
E high level width
PWEH
E low level width
PWEL
E rise time
E fall time
\
\
Address setup time
Max
Unit
Note
ns
13,14
450
ns
13,14
450
ns
13,14
25
ns
13,14
25
ns
13,14
tAS
140
ns
13,14
Address hold time
tAH
10
ns
13,14
Data setup time
tosw
200
ns
13
ns
14,15
Data delay time
tOOR
Data hold time at write
tOHW
10
ns
13
tDHR
20
ns
14
Data hold time at read
320
Notes:
13. At CPU write
14. At CPU read
+----~~====~
E
E
R/W
R/W
CS1-CS:!
CS1-GS3
011
011
OBo-DB7
OBo-OB7
15. DBO to DB7 load circuits
:rrl
1
Test Point
Cr
R
RL .. 2.4 kn
RL
02
03
04
R
=11 kn
C
=130 pF (including jig capacitance)
Diodes 0 1 to 0 4 are all 182074
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HD44102CH
Notes: 16. Display off at initial power up.
.
The HD441 02CH can be placed in the display off state by setting terminal RST to low
at initial power up.
No instruction other than the Read Status can be accepted while the RST is at the low
level.
Symbol
Min
Reset time
..
1.0
Rise time
t,
Typ
Max
Unit
200
ns
Pin Description .
Pin
Name
Pin
Number
110
Function
Y1- Y50
50
o
liquid crystal display drive output.
Relationship among output level, M and display data (0):
CS1-CS33
r
M
J
0
.fT1..Lf11.Lf
Output
t.evel
I_ VI +vs+ V2+ V4~1
o
Chip select
CS1
CS2
CS3 State
L
L
L
L
H
H
H
H
L
L
H
H·
L
L
H
H
L
H
L
H
[
H
L
H
Non-selected
Non-selected
Non-selected
Selected readlwrite enable
Selected write enable onl~
Selected write enable onl~
Selected write enable on~
Selected readlwrite enable
Enable
E
At write (RIW - Low): Data of OBO to OB7 is latched at the fall of E.
At read (RIW • High): Data appears at DBO to DB7 while E is at high
level.
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HD44102CH
Pin Name
Pin
Number
1/0
Function
RIW
ReadlWrite
RIW = High: Data appears at DBO to DB7 and can be read
by the CPU when E = high and CS2, CS3 = high.
RIW = Low: DBO to DB7 can accept input when CS2, CS3 = high or
CS1 =high.
011
Data/Instruction
011 = High: Indicates that the data of DBO to DB7 is display data.
011 = Low:
Indicates that the data of DBO to DB7 is display control
data.
DBO-DB7
8
I/O
Data bus, three-state I/O common terminal
E
RfW
H
H
L
CS3
State of DBO to DB7
H
H
Output state
H
H
High impedance
CS1 CS2
Input state,
H
L
Others
High impedance
M
Signal to convert liquid crystal display drive output to AC.
CL
Display synchronous signal
At the rise of CL signal, the liquid crystal display drive signal
corresponding to display data appears.
FRM
Display synchronous signal (frame signal)
This signal presets the 5-bit display line counter and
synchronizes a common signal with the frame timing when
the FRM signal becomes high.
$1,$2
2
2-phaseclock signal for internal operation
The $1 and $ 2 clocks are used to perform the operations
(input/output of display data and execution of instructions)
other than display.
RST
Reset signal
The display disappears and Y address counter is set in the up
counter state by setting the RST Signal to low level. After
releasing reset, the display off state and up mode is held until
the state is changed by the instruction.
BS
Bus select signal
BS =Low:
DBO to DB7 operate for 8-bit length.
BS =High: DB4 to DB7 are valid for 4-bit length only.
8-bit data is accessed twice in the high and low order.
V1, V2,
V3, V4
4
Power supply for liquid crystal display drive
V1 and V2: Selection voltage
V3 and V4: Non-selection voltage
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HD44102CH
, Pin Name
Pin
Number
3
110
Function
Power supply
Vco-GND:
Power supply for intemallogic
Vco-Vee:
Power supply for liquid crystal display drive circuit logic
Function of Each Block
Interface Logic
The HD441 02CH can use the data bus in 4-bit or 8-bit
word length to enable intetface to a4-bit or 8-bit CPU.
1.
The data bus uses the high order 4 bits (DB4 to
DB7). First, the high order 4 bits (DB4 to DB7
in 8-bit data length) are transferred and then the
low order 4 bits (DBO to DB3 in 8-bit data
length).
=
4 bit mode (BS High)
8-bit data is transferred twice for every 4 bits
through the data bus when the BS signal is high.
-Jrr-,. . . _____---'r~
Busy Flag _ _ _ _ _ _
011
------------------~------~
RIW
E
OBe
Busy flag
check
(Status
read)
Address
high order
write
Address
low order
write
Busy flag
check
Data high
order write
Data low
order write
(Stetus
read)
Figure 1 4-Bit Mode Timing
Note:
Execute instructions other than status read in 4-bit length each. The busy flag is set at the
fall ofthe second E signal. The status read is executed once. After the execution ofthe status
read, the first 4 bits are considered the high order 4 bits. Therefore, if the busy flag is checked after the transfer of the high order 4 bits, retransfer data from the higher order bits. No
busy check is required in the transfer between the high and low order bits.
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HD44102CH
2.
8-bit mode (BS = Low)
If the BS signal is low, the 8 data bus lines (DBO to
DB7) are used for data transfer.
DB7: MSB (Most significant bit)
DBO: LSB (Least significant bit)
For AC timing, refer to note 12 to note 15 of"Electrical
Characteristics".
Input Register
8-bit data is written into this register by the CPU. The
instruction and display data are distinguished by the
8-bit data and D/I signal and then a given operation is
performed. Data is received at the fall of the E signal
when the CS is in the select state and R/W is in write
state.
Output Register
The output register holds the data read from the
display data RAM. After display data is read, the
display data at the address now indicated is set in this
output register. After that, the address is increased or
decreased by 1. Therefore, when an address is set, the
correct data doesn't appear at the read of the first
display data. The data at a specified address appears
at the second read of data (figure 2).
x, Y Address Counter
The X, Y address counter holds an address forreadingl
writing display data RAM. An address is set in it by
the instruction. The Y address register is composed of .
a 50-bit up/down counter. The address is increased or
decreased by 1 by the read/write operation of display
data. The up/down mode can be determined by the
instruction or RST signal. The Y address register
counts by looping the values of0 to 49. The X address
register has no count function.
Display On/Off Flip/Flop
This f1ip/flop is set to on/off state by the instruction or
RST signal. In the off state, the latch of display data
RAM output is held reset and the display data output
is set to O. Therefore, display disappears. In the on
state, the display data appears according to the data in
the RAM and is displayed. The display data in the
RAM is independent of the display on/off.
UplDown FIip/Flop
This flip/flop determines the .count mode of the Y
address counter. In the up mode, the Y address
register is increased by 1. 0 fQllows 49. In the down
mode, the register is decreased by 1. 0 is followed by
49.
011 _ _ _ _ _ _ _ _ _ _--'
R!W
E
Address _ _ _ _ _ _ _...J.._ _ _-.:;N=--_ _......J._ _-..!N!.:±~1!...._._ _L_..!N!.:±~2=_~_
Output
Data at address N
register
Busy
OBO- OB7 1 check
Write
1 Busy
1address N check
Read data 1 Busy
check
1(dummy)
I Data at address N ±1
IRead data 1 Busy 'I Data read
check
address
at
address N
N±1
Figure 2 Data Output
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225
HD44102CH
Display Page Register
Z Address Counter
The display page register holds the 2-bit data that
indicates a display start page. This value is preset to
the high order 2 bits of the Z address counter by the
FRM signal. This value indicates the value of the
display RAM page displayed at the top of the screen.
The Z address counter is a 5-bit counter that counts up
at the fall of CL signal and generates an address for
outputting the display data synchronized with the
common signal. 0 is preset to the low order 3 bits and
a display start page to the high order 2 bits by the FRM
signal.
Busy Flag
Latch
After an instruction other than status read is accepted,
the busy flag is set during its effective period, and
reset when the instruction is not effective (figure 3).
The value can be read out on DB7 by the status read
instruction.
The HD441 02CH cannot accept any other instructions
than the status read in the busy state. Make sure the
busy flag is reset before issuing an instruction.
The display data from the display data RAM is
latched at the rise of CL signal.
Liquid Crystal Driver Circuit
Each of 50 driver circuits is a multiplex circuit
composed of 4 CMOS switches. The combination of
display data from latchs and the M signal causes one
of the 4 liquid crystal driver levels, VI, V2, V3 and
V4 to be output.
---'n. . .______
E __
Busy
-----f~TBUSY~
J...<1i
<.1F~ = BUSY = F~
F~
is
~1. ~2
frequency (half of HD441 03CH oscillation frequency)
Figure 3 Busy Flag
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HD44102CH
Display RAM
(Yaddress)
Figure 4 Relationship between Data in RAM and Display
(Display start page 0, 1/32 duty)
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HD44102CH
Display Control Instructions
ReadlWrite Display Data
MSB
RIW 011
Set XlY Address
DB
DB
MSB
LSB
LSB
RIW 011
7 6 5 4 3 2 1 0
(Display data)
0
0
0 0
Read (CPU +- HD44102CH)
0
o~
0 1 Binary numbers of Q-49
(Display data)
0
0
0
0
7 6 5 4 3 2 1 0
0
Write (CPU
~HD44102CH)
0
'---,--i
X address
(page)
Sends or receives data to or from the address of the
display RAM specified in advance. However, a
dummy read may be required for reading display data.
Refer to the description of the output register in
Function of Each Block.
Yaddress
o 1 ....
DB
LSB
RIW 011
7 6 5 4 3 2 1 0
0
0
0 0 1 1
0
0
0
o
0
o
1
Display on
1 1 1 0 0 0
Display off
Turns the display on/off. RAM data is not affected.
48 49
L
00 M
L
01 M
10 L
M
11 L
M
Display On/OtT
MSB
Yaddress
(address)
Page 0
Page 1
Page 2
Page 3
Display Data RAM
Display Start Page
MSB
DB
LSB
RIW 011
7 6 5 4 3 2 1 0
0
0
o0
0
0
o
0
0
1 0 1 1 1 1 1 0
0
0
1 1 1 1 1 1 1 0
-,......
1 1 1 1 0
Refer to figure 5 (a)
1 1 1 1 1 1 0
Refer to figure 5 (b)
Refer to figure 5 (e)
Display start page
......
Refer to figure 5 (d)
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HD44102CH
Specifies the RAM page displayed at the top of the
screen. Display is as shown in figure 4. When the
display duty factor is more than'I/32 (For example, 1/
24, 1/16), display begins at a page specified by the
display start page only by the number of lines.
Start page .. page 0
(a)
A
Page 0
A
N
N
B
Page 1
B
C
Page 2
C
0
Page 3
0
Displayed up to
here when display
duty is 11N.
(N-B. 12. 16.24.32)
Display Data RAM
Uquid Crystal Screen
Start page .. page 1
(b)
A
Page 0
B
B
Page 1
C
C
Page 2
0
0
Page 3
A
N
Display Data RAM
Uquid Crystal Screen
Start page .. page 2
(e)
A
Page 0
B
Page 1
C
Page 2
0
Page 3
Display Data RAM
~~
C
N
0
A
B
Liquid Crystal Screen
Start page .. page 3
(d)
A
Page 0
B
Page 1
C
Page 2
0
Page 3
Display Data RAM
r
~~
0
N
A
B
C
Liquid Crystal Screen
Figure 5 Display Start Page
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229
HD44102CH
Up/DownSet
MSB
RIW 011
DB
LSB
7 6 5 4 3 2 1 0
1 Up mode
0
0
0 0
0
0
0 011101 0 Down mode
0
Sets Y address register in the up/down counter
mode.
Status Read
MSB
DB
LSB
RlWO/176543210
o
B UOROOOO
U P F E
S I F S
Y 0 I E
OOT
~
N
-'--_--+.
L . I_ _ _ _
Goes to 1 when RST is in the reset state
(Busy also goes to 1).
Goes to 0 when RST is in the operating state.
Goes to 1 in the display off state.
Goes to 0 on the display on state.
Goes to 1 when address counter is in the up mode.
Goes to oWhen address cOunter Is In the dOwn
mode.
.
Goes to 1 while all other instructions are being
executed.
.
While 1, none of the other instructions are
accepted.
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HD44102CH
Connection Between LCD Drivers (Example of 1/32 Duty Factor)
h I
CR R C
Xl h -
i To liquid
! crystal display
Xso
SHL
MIS
FS
OSl
OS2
OS3
HD44103CH
(Master)
f-!--
To liquid crystal display
~Vcc
r---
GNO
r---------------.r
Yl
Yso
FRM
I
FRM
M
OL DR 4>1 «1>2 CL
M
I
HD44102CH
No.1
CL
~II
4>1
4>2
OJ" OJ" OJ"
OL OR «1>1 «1>2 FRM M
CL
Xl
Ope"
To liquid crystal display
....-
r---------------.r
i To liquid
! crystal display
HD44103CH
(Slave)
X12
SHL
MIS
FS
OSl
OS2
OS:!
f-!--
Vee
Yl
L....,.
Yso
FRM
GNO
M
CL
HD44102CH
No.2
4>1
CR R C
I ~"O~"
«1>2
Vee
Figure 6 1/32 Duty Factor Connection Example
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231
HD44102CH
Interface to CPU·
I. Example of connection to HD6800
In the decoder given in this example, the addresses of
HD44102CH in the address space of HD6800 are:
Read/write of display data: $'FFFF
Write of display instruction: $'FFFE'
$'FFFE'
Read of status:
Tbus, the HD441 02CH can be controlled by reading!
writing data at these addresses.
oecoder
At5
to
At
VMA
II
.s;- CSt
r--"\
r---'
Vee .....
Ao
011
RIW
HD6800
RIW
HD44102CH
,2
Do
to
07
CS2
CS3
E
I
I
OBo
to
OB7
£VCC
RES
b.
RST
FIgUre 7 Example of Connection to HD6800 Series
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HD44102CH
2. Example of connection to H06801
• The H0680 I is setto mode 5. PI O-Pl4 are used as
output ports, and P30-P37 are used as the data bus.
• The 74LSl54 is a4-to-l6 decoder that decodes 4
bits ofPIO-Pl3 to select the chips.
• Therefore, the HD44102CH can be controlled by
selecting the chips through PI O-Pl3 and specifying
the 0/1 signal through Pl4 in advance, and later
conducting memory read or write for external
memory space $0100 to $OIFF of H06801. The
lOS signal is output to SCI, and the R/W signal is
output to SC2.
• For further details on H06800 and H06801, refer
to their manuals.
74LS154
P10
P11
P12
P13
(lOS) SC1
Yo
A
Y1 r.B
I
C
Y;s
D
G1G2
.
r!-
I
.s;- CS1
~
-
f J.
R/W
(R/W) SC2
HD6801
D/I
P14
E
P30
P31
(Data Bus)
!
P37
CS2
CS3
HD44102CH
No.1
E
;
I
!
DBo
DB1
Dk7
Figure 8 Example of Connection to HD6801
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233
HD44102CH
Connection to Liquid Crystal Display
r-:::C
Xl
0..:-
S
G)
~T-gj
~:::a:
L..-o-
l
X2
;
1
2
i,
I
~ xm~
!
:::c
Liquid crystal display panel
i 20
Xl
~g?X2
TIII
l
~Ci5
32 x 150 dots
21
,22
'!
O-XI2Lk.
:::c
'32
l-----------l
1------------1
. 1------------1
Y 1 ________ Y50
Y 1 ________ Y50
Y 1 ________ Y50
HD44102CH
No.1
HD44102CH
No.2
HD44102CH
No.3
Figure 9 Example of Connection to 1132 Duty Factor, I·Screen Display
Xl
r- :::c
0..:-
.-S!l(/) X2I
C5 e XIS
:::c
r- ...,.111
-
X16
1
2
i
Liquid crystal display panel
16 x 100 dots
15
16
1------------1
1------------1
Y 1 ________ Y50
Y 1 ________ Y50
HD44102CH
No.1
HD44102CH
No.2
Figure 10 Example of Connection to 1/16 Duty Factor, l-Screen Display
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HD44102CH
HD44102CH
No.6
Vl",-""""V50
1------------1
HD44102CH
-........................... HD44102CH
No.7
No. 10
Vl ...-........V.,
C
·e
'i5
1=
u;
f
I--
...
'"
(J)
g>
II..
x"' .... I--
--
CD
C>
:3"
I
x
ii
i8~
~·5... I--
OO:::J
I
>
>'"
I
C\I
.,...
.e...
:!l!
·0
c5
>-
0!601
1
(.)
II:
(.)
II:
L
I
I
I
I
>~~
8C w
>~~
II
..J
C
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HD44103CH
Absolute Maximum Ratings
Item
Symbol
Rated Value
Unit
Note
Supply voltage (1)
Vee
-0.3 to +7.0
V
Supply voltage (2)
Vee -13.5 to Vee + 0.3
V
Terminal voltage (1)
Vee
VT1
-0.3 to Vee + 0.3
V
1.2
Terminal voltage (2)
VT2
Vee -0.3 to Vee + 0.3
V
3
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-55 to +125
°C
°C
Notes: 1.
2.
3.
4.
4
Referenced to GND = O.
Applied to input terminals (except V1, V2, V5. and VS) and 1/0 common terminals.
Applied to terminals V1. V2. V5. and VS.
Connect a protection resistor of 220 n ± 5% to VEE power supply in series.
Electrical Characteristics
(Vee
= +5 V ±10%, GND = 0 V, VEE = 0 to -5.5 V, Ta = -20 to +75 °C) (NoteS)
Item
Symbol Min
Input high voltage
V,H
Input low voltage
Output high voltage
V,L
VOH
Output low voltage
VOL
0.4
Vi· Xj on resistance
RON
500
J.lA
V,N " Vee to GND
TypMax
-
Note
6
Vee
0.3 x Vee V
0
Vee -0.4
Unit Test condition
V
0.7 x Vee
6
IOH =-400J.lA
7
V
IOL =+400 J,1A
7
Q
Vee =-5 ± 10%,
V
Load current ±150 J.lA
Input leakage current (1)
I'Ll
-1
-2
Input leakage current (2)
111.2
Shift frequency
f8FT
Oscillation frequency
fose
2
50
300
430 560
8
VIti = Vrs. to VEE
kHz In slave mode
9
kHz R, =68 k.Q ± 2%
11
J.lA
10
C,= 10 pF±5%
External clock. operating
f""
50
External clock duty
Duty
45
External clock rise time
t...,
560
kHz
55
%
12
50
ns
12
12
frequency
50
External clock fall time
t,."
50
ns
Dissipation power (master)
PWl
Pw2
4.4
mW CR oscillation", 430 kHz 13
1.1
mW Frame frequency -70 Hz14
Dissipation power (slave)
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241
HD44103CH
Notes: 5.
S.
7.
8.
Specified within this range unless otherwise noted.
Applied to CR. FS. OS1 to OS3. M. SHL. MIS. CL. DR. and OL.
Applied to DL. DR. M. FRM. CL. ~1 and ~2.
Applied to input terminals CR. FS. OS 1 to OS3. SHL and M/S. and I/O common terminals
.DL. DR. M. and CL at high impedance.
9. Applied to V1. V2. V5. and VS.
10. Shift operation timing
CL
Min
0.7Vcc
0.3Vec
DLJDR
0.7Vec
0.3Vec
t,
Typ
Max
Unit
tsu
5
~
tH
5
~
t,
100
ns
~
100
ns
t,
11. Relationship between oscillation frequency and RIC,
CR:~.
~
The values of R, and C, are typical values.
The oscillation frequency varies with the mounting
condition. Adjust oscillation frequency to the
required value.
~
~ec=Sv
'~
Ta =.+2S·C
"'
SOO
400
300
fose 200
......... "'-..
.......
"--
Cf= 6pF
Cf-1 OpF
(kHz) 100
so
100
150 (kG)
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HD44103CH
12.
Th--l.....DUTY-
t IqI
Th + T.
tlcp
open=[
Open
R
Extemal Clock _
CR
13. Measured by Vco terminal at output non-load of f\ - 68 kn ± 2% and C, = 1OpF ± 5%, 11
32 duty factor in the master mode. Input terminals must be fixed at VcC or GND while
measuring.
14. Measured by Vco terminal at output non-load, 1/32 duty factor, frame frequency of 70 Hz
in the slave mode. Input terminals must be fixed at Vco or GND while measuring.
Pin Description
Pin Name
Pin
Number
I/O
Function
X1-X20
20
0
Liquid crystal display driver output.
RelationShi~ amjna o~ut Irel, ~' an}data (0) in shift register:
D~
CR,R,C
M
3
Oscillator
I/O
R,
C,
fAlCR--
Signal for converting liquid crystal display driver signal into AC.
Master: Output terminal
Slave: Input terminal
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243
HD44103CH
Pin Name
Pin
Number
1/0
Function
CL
1/0
Shift register shift CiOCK.
Master: Output terminal
Slave: Input terminal
FRM
o
Frame signal, Display synchronous signal.
DS1-DS3
Display duty ratio select.
3
Display
Duty Ratio
1/24
1112
1/16
1/8
DS1
L
H L H
L
H L H
L H H
L
DS2
L
L H H
DS3
L
L
H
H H H
FS
FS
SHL
1132
L
L
Frequency select.
The relationship between the frame frequency fFRM and the
oscillation frequency fosc is as follows:
FS
DL,DR
X
2
I/O
=High:
= Low:
fosc
fosc
=6144 X fFPM
= 3072 X fFRM
(1)
(2)
Example (1)
When FS = high, adjust Rf and Cfso that the
oscillation frequency is approx.
430 kHz if the frame frequency is 70 Hz.
Example (2)
When FS = low, adjust Rf and Cf so that the
oscillation is approx. 215 kHz, in order to obtain the
same display waveforms as example 1. When
compared with example 1, the power dissipation is
reduced because of operation at lower frequency.
However, the operating clocks $1 and $2 supplied to
the column driver have lower frequencies. Therefore,
the access time of the column driver HD44102CH
becomes longer.
Data I/O terminals of bidirectional shift register.
Shift direction select of bidirectional shift register.
SHL
Shift Direction
H
DL~DR
L
DL +- DR
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HD44103CH
Pin Name
Pin
Number
I/O
Function
Master/slave select.
MIS
MIS = High: Master mode
The oscillator and timing generation circuit supply display
timing signals to the display system. Each of I/O common
terminals, DL, DR, M, and CL is placed in the output state.
M/S = Low: Slave mode
The timing generation circuit stops operating. The oscillator is
not required. Connect terminal CR to Vcc.
Open terminals C and R. One (determined by SHL) of DL and
DR, and terminals M and CI are placed in the input state.
Connect M, CL and one of DL and DR of the master to the
respective terminals.
Connect FD, DS1, DS2, and DS3 to Vcc'
When display duty ratio is 1/8, 1/12, or 1/16, one HD44103CH is
required. Use it in the master mode.
When display duty ratio is 1/24 or 1/32, two HD44103CHs are
required. Use the one in the master mode to drive common signals 1
to 20, and the other in the slave mode to drive common signals 21 to
24 (32).
cp1,cp2
2
0
Operating clock output terminals for HD441 02CH.
The frequencies of cp1 and cp2 become half of oscillation frequency.
V1, V2,
V5,V6
4
Vee
GND
VEe
3
Liquid crystal display driver level power supply.
V1 and V2: Selected level
V5 and V6: Non-selected level
Power supply.
Vcc-GND:Power supply for internal logic
Vcc-Vee: Power supply for driver circuit logiC
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245
HD44103CH
Block Functions
Bidirectional Shift Register
Oscillator
20-bit bidirectional shift register. The shift direction
is determined by SHL. The data input from DL or DR
performs a shift operation at the rise of shift clock CL.
The oscillator is a CR oscillator attached to an
oscillation resistor Rf ans osckIlation capacity Cf.
The oscillation frequency varies with the values of Rf
and Cf and the mounting conditions. Referto Electrical
Characteristics (Note 10) to make proper adjustment.
Timing Genaration Circuit
The timing generation circuit divides the signals from
the oscillator and generates display timing signals (M,
CL, and FRM) and operating clock (~I and ~2) for
HD44102CH according to the display duty ratio set
by DS I to DS3. In the slave mode, this block stops
operating. It is meaningless to set FS, DS1 to DS3.
However, connect them to Vcc to prevent floating
current.
Liquid Crystal Display Driver Circuit
Each of 20 driver circuits is a multiplex circuit
composed of four CMOS switches. The combination
of the data from the shift register with M signal allows
one of the four liquid crystal display driver levels V I,
V2, V5, and V6 to be transferred to the outputterminals.
Applications
Refer to the applications of the HD441 02CH.
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HD44105H-----------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Features
Description
The HD4410SH is a common signal driver for
l.CD dot matrix graphic display systems. It
generates the timing signals required for display
with its internal oscillator and supplies them to the
column driver (HD44102H) to control display, also
automatically scanning the common signals of the
liquid crystal according to the display duty cycle.
It can select 7 types of display duty cycle 118, 1/12,
1/16, 1/24,1/32, 1/48, and 1/64. It provides 32
driver output lines and the impedance is low (1 len
max) enough to drive a large screen.
Dot matrix graphic display common driver
including the timing generation circuit
Internal oscillator (Oscillation frequency is
selectable by attaching an oscillation resistor
and an oscillation capacitor)
Generates display timing signals
32-bit bidirectional shift register for generating
common signals
32 liquid crystal driver circuits with low
impedance
Selectable display duty ratio: 1/8, 1/12, 1/16,
1/24, 1/32, 1/48, 1/64
Low power dissipation
Power supplies:
V cc =+5 V ± 10%
VEE =0 to-5.5 V
CMOS process
6O-pin flat plastic package
Absolute Maximum Rating (Ta =25°C)
Item
Symbol
Ratings
Unit
Supply voltage (1)
Vee
..,0.3 to +7.0
V
Supply voltage (2)
VEE
Vee -13.5 to Vee +0.3
V
Terminal voltage (1)
Vn
-0.3 to Vee +0.3
V
1,2
Terminal voltage (2)
VT2
VEE -0.3 to Vee +0.3
V
3
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-55 to +125
·C
·C
Notes: 1.
2.
3.
Note
Referred to GND • 0 V.
Applied to input terminals (except for V1, V2, V5, and V6) and 110 common terminals.
Applied to terminals V1, V2, V5, and V6. Connect a protection resistor of 47 n ± 10% to each
terminal in series.
HITACHI
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247
HD44105H
Pin Arrangement
~ ~
N
....0 )(
.... )(....
)(
'It
.... )(
.... )(
.... )(....cg. )(
".... )(....CD
(I)
II)
)(
X19
X7
X6
X20
X21
X5
X22
X4
X23
X3
X2
X1
X24
X25
X26
DL
X27
X28
X29
FS2
DS1
X30
X31
DS2
DS3
0
X32
V6
V5
R
OR
STB
V2
V1
VEE
...J
:J:
en
~
....
N
....
::IE
ff
0
~
(.)
Z
::IE
~
...J
a: (.)
Z
(.) 0
(Top View)
Note:
NCs show unused terminals.
Don't connect any lines to
them in using this LSI.
HITACHI
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-=
'0
~
::J:
;::;:
A>
...o
n
=-
>
~
3a>
~
a
::!.
n
V1V2V5V6
1»
!:;
x;
·
?-
::J:
ff
=-3!
~
·
8
I
Vee
GND
VEE
N
CD'
iii l:
~~
a n
"l:
~-
·
aI
::!.
en
C'
A>
:::I
".
I
I
DL
-
I
f
Log'
1
r-
2
-
Bidirectional shift
register
30
31
32
_. Log'
DR
SHL
-
Oscillator
Timing generation circuit
~
$I>
C')
>
....
~
I
liquid crystal display
driver circuits
-
0
en
-
-
32 output terminals
X2 ----
B-
M
CL
FRM
<0
R.R~
0
~
<0
STB
At
.~.
Cf
C
MIS
FS1 FS2
DS2
DS1 DS3
,1,2
•
~
::z:
~
(J1
0
~
~
....
::z:
co
<0
clo
c,,)
.....
o(J"I
o·
N
<0
II
HD44105H
Electrical Characteristics
(V CC = +5 V ± 10%, GND
(Note 4)
=0 V, VEE =0 to -5.5 V, Ta =-20 to +75°C)
Item
Symbol Min
Input high voltage
VIH
Typ
0.7 x Vee
Input low voltage
»
VOH
Output high voltage
5
0.3xVee V
5
Vee -
=.
3
~
~-
a
t:
!=l-
·
~
:J:
•
DS3
FSl
FS2
~
<=>
<=>
<=>
en
~m
SHI.
CD-
-.
""tJ
0
a
""tJ
~
n
:x::
f---j-I
I
I
I
I
I
I
I
I
I
I
I
~
8
.-
I
I
I
I
~
:x::
f
COM1
I
X32
~
F
R
CL M Ms1 J2
Vee
(470)
:::l_
en
D>
::::J
~
~V3
C")
»
CO
~V6
<=>
<=>
--w,....V1
""'=>"
UI
COM32
SEG1 ------- SEG50 --------------------- SEG201·----- SEG250
M
FRM R D R D
81
I I S B
82EWITO
~V4
c::r
t
I
I
1
f
V<4
Cl
~V5
CD
=
c
32 Ie 250 Dots
1132 Duty Cycle
I
Y1 --------- Y50
V1
HD44102CH
(1)
~
~V2
J:
ig
1
MIS
J:
·-
~
w
DS2
G~
D>
8·
I
I
I
V5
Vee- Vee
Vcc- DSl
Dr
N
1
R
X1
V1
VI
aJriS-.-i.. ~
=.
""tJ
iiJ
1 I'
C CR
~
Vee
~D
cO:
~ B S0S2
D
73as
,
i
Y1 --------- Y50
V1
HD44102CH
VI
(5)
va
V4
Vee
Va
-Cl
..--- M
FRM R D R D
D
81
I I S B ~ B S0S2
r82EWITO
73as
If
=
~
'-'2
cC:
V1
VI
113
V4
.~
Va!
=2...
=
""'"
=>
N
n
=
~
~
~
(20 n)
CO
:!:::
~
U1
CD
%
(.0)
0
0
I
VEE
{
To CUP
AIW
011
RBT
D~
,
DB7
CS1
•
CS5
~
~
~
o
en
~
U1
U1
::r:
HD61100A----~
(LCD Driver with SO-Channel Output)
Features
Description
Liquid crystal display driver with serial/parallel
conversion function
Intemalliquid crystal display driver: 80 drivers
Display duty cycle
Any duty cycle is selectable according to
combination of transfer clock and latch clock
Data transfer rate: 2.5 MHz max.
Power supply
Vee: +5 V ± 10% (Internal logic)
VEE: 0 to -1.5 V (Liquid crystal display
driver circuit)
Liquid crystal driving level: 17.0 V max.
CMOS process
loo-pin flat plastic package (FP-l00)
The HD61100A is a driver LSI for liquid crystal
display systems. It receives serial display data from
a display control LSI, HD61830, etc., and generates
liquid crystal driving signals.
It has liquid crystal driving outputs which
correspond to internal 80-bit flip/flops. Both static
drive and dynamic drive are possible according to
the combination of transfer clock frequency and
latch clock frequency.
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Supply voltage (1)
Vee
-0.3to +7.0
V
2
Supply voltage (2)
VEE
Vee - 19.0 to Vee + 0.3
V
Terminal voltage (1)
Vn
- 0.3 to Vee + 0.3
V
2,3
Terminal voltage (2)
VT2
VEE - 0.3 to Vee + 0.3
V
4
Operating temperature
Topr
-20to+75
·C
Storage temperature
Tstg
-55to+125
·C
Notes:
1.
2.
3.
4.
LSls may be permanently destroyed if used beyond the absolute maximum ratings. In ordinary
operation, it is desirable to use them within the limits of electrical characteristics, because
using it beyond these conditions may cause malfunction and poor reliability.
All voltage values are referred to GND - 0 V.
Applies to input terminals, FCS, SHL, CL1, CL2, DL, DR, E, and M.
Applies to Vll, Vl R, V2l, V2R, V3l, VaR, V4l and V4R. Must maintain:
Vee ~ Vll- V1R ~ V3l- V3R ~ V4l" V4R ~ V2l- V2R ~ VEE.
Connect a protection resistor of 15 n
± 10% to each terminals in series.
HITACHI
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HD61100A
Pin Arrangement
Y5l
Y52
Y53
Y54
YSS
Y56
Y57
Y58
Y59
Y60
Y6l
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y7l
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
(Top view)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
257
HD61100A
Electrical Characteristics
DC Characteristics
(V cc = 5 V ± 10%, GND = 0 V, VEE = 0 to -11.5 V, Ta = -20 to +7S°C)
Item
Symbol
Min
Max
Unit Test Condition Note
Input high voltage
VIH
0.7xVcc
Vcc
V
Input low voltage
VIL
0
0.3xVcc
V
Vcc-o.4
Typ
1
Output high voltage
VOH
V
1ai--400~
2
Output low voltage
Va..
0.4
V
1a..-+400~
2
Driver resistance
Ret.!
7.5
kG
VEE--10V,
Load current-
3
+1
~
VIN- Oto Vcc
+2
~
VIN - VEE to Vcc
!GND
1.0
rnA
5
lEE
0.1
rnA
5
100~
Input leakage current
hL1
.,.1
Input leakage current
hL2
-2
Dissipation current (1)
. Dissipation current (2)
Notes: 1.
2.
3.
4.
5.
4
Applies to CL1, CL2, FCS, SHL, E, M, DL, and DR.
Applies to DL, DR, and CAR.
Applies to Y1-Y80.
Applies to V1L, V1R, V2L, V2R, V31. V3R, V4L, and V4R.
Specified when display data is transferred under following conditions:
CL2 frequency fCP2 • 2.5 MHz (data transfer rate)
CL1 frequency fCP1 • 4.48 kHz (data latch frequency)
M frequency fM - 30 Hz (frame frequencyl2)
Specified when VIH - Vcc, VIL • GND and no load on outputs.
!GND: currents between Vcc and GND.
lEE: currents between Vcc and VEE.
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HD61100A
AC Characteristics
(V cc = 5 V ± 10%. GND = 0 V, VEE = 0 to -11.5 V, Ta = -20 to +75°C)
Typ
Max
Symbol Min
Clock cycle time
tevc
400
ns
Clock high level width
tCWH
150
ns
Clock low level width
tcW\.
150
ns
Clock setup time
tSCl
100
ns
Clock hold time
tHCl
100
ns
Clock riselfall time
tCt
Clock phase different time
tCl
100
ns
Data setup time
tosu
80
ns
Data hold time
ns
30
ns
tOH
100'
Esetuptime
tESU
200
Output delay time
tOCAR
300
ns
M phase difference time
tcM
300
ns
Note:
1.
Test Condition Note
Unit
Item
ns
The following load circuits are connected for specification:
test point
0
}30 PF
CL1-----"""l
CL2
DL(DR)
HITACHI
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259
1::1
I\)
01
o
6f
(')
=-
V1L v2L V3L V4L
~
CD
Y80
Y1 Y2
V1RV2RV3RV4R
U~uid ~rystal display
M
it
::J:
;:;:
driver CIrcUit
~
=-
-0
.
~
CL1
I\)
-,
3:
o
8
(J)
5"
~:
II
~;
:~
;
,HI., HI..
:1
'
1
2
l
1
So_
>t
1
GND
VCC
VEE
rL
1
20
C")
»
~
E
II
~
~
<0
~
~
U1
ex>
~
o
FCS
eo
Test input
,.---,
I
I
I
I
I
:
"
I
t
I
-CAR
I
~
L------------------------COntrol circuit
S
en
I»
o
o
~
~.
~
~
'"....o
::J:
~
~
»
HD61100A
Block Function
Liquid Crystal Display Driver Circuit
Selector
The combination of the data from the latch circuit 2
and M signal causes one of the 4 liquid crystal
driver levels, VI, V2, V3 I'...d V4 to be output
The selector decodes output signals from the
counter and generates latch clock.l to +20. Wher
the LSI is not active, +1 to .20 are not generated,
so the data at latch circuit 1 is stored even if input
data (DL, DR) changes.
80·bit Latch Circuit 2
The data from latch circuit 1 is latched at the fall of
CLI and output to liquid crystal display driver
circuit
SIP
Seria1/ParaIlel conversion circuit which converts 1bit data into 4-bit data. When SID.. is "L" level,
data from DL is converted into 4-bit data and
transferred to the latch circuit I. In this case, don't
connect any lines to terminal DR which is in the
output status.
When SID.. is "H" level, input data from terminal
DR without connecting any lines to terminal DL.
80·bit Latch Circuit 1
Control Circuit
Controls operation: When E-F/F (enable F/F)
indicates "1", Stp conversion is started by
inputting "L" level to E. After 8O-bit data has been
all converted, CAR output turns into "L" level and
E-F/F is reset to "0", and consequently the
conversion stops. E-F/F is RS flip-flop circuit
which gives priority to SET over RESET and is set
at "H" level of CLI.
Counter consists of 7 bits, and the output signals
of upper 5 bits are transferred to the selector. CAR
signal turns into "H" level at the rise of CLI and
the number of bit which can be Stp-converted
increases by connecting CAR terminal with E
terminal of the next HD61100A.
The 4-bit data is latched at +1 to +20 and output to
latch circuit 2. When SID.. is "L" level, the data
from DL are latched one in order of 1-.2-+3 ... -+
80 of each latch. When SID.. is "H" level, they are
latched in a reverse order (80-+79-+78 ... -+1).
HITACHI
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261
HD61100A
Terminal Functions Description
Terminal
Name
Number of
,Terminals
Vee
GND
VEE
1
1
1
8
Vll-V4L
V1R-V4R
1/0
Connected
to
Power
supply
Power
supply
Functions
Vet; - GND: Power supply for intemallogic
Vet; - VeE: Power supply for LCD drive circuit
Power supply for liquid crystal drive.
V1L (V1R), V2l (V2R): Selection level
V3l (V3R), V4L (V4R): Non-selection level
Power supplies connected with V1L and V1R (V2l & V2R,
V3l & V3R, V4L & V4R) should have the same voltages.
Y1-Y80
80
0
LCD
Liquid crystal driver outputs.
Selects one of the 4 levels, V1, V2, V3, and V4.
Relation among output level, M and display data (D) is as
follows:
01
D~
M
Controller
Switch signal to convert liquid crystal drive waveform into
AC.
CL1
Controller
Latch clock of display data (fall edge trigger).
Liquid crystal driver signals corresponding to the display
data are output synchronized with the fall of CL1.
CL2
Controller
Shift clock of display data (D).
Falling edge trigger.
DL,DR
2
110
Controller
Input of serial display data (D).
(D)
Liquid Crystal
Driver Output
Liquid Crystal
Display
1 (High)
Selection level
On
o(Low)
Non-selection level
Off
VO status of DL and DR terminals depends on SHL input
level.
SHL
DL
High
0
Low
DR
0
HITACHI
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HD61100A
Terminal Functions Description (cont)
Terminal
Name
Number of
Terminals
110
SHL
Connected
to
Functions
Vee or GND
Selects a shift direction of serial data.
When the serial data (D) is input in order of 01 -+ ... -+ 080,
the relations between the data (D) and output Yare as
follows.
SHL
Y1
Y2
Y3
Y80
Low
01
D2
D3
080
High
080
079
078
01
When SHL is low, data is input from the terminal DL. No
lines should be connected to the terminal DR, as it is in the
output state.
When SHL is high, the relation between DL and DR
reverses.
o
FCS
GNDorthe
terminal
OAR" of the
HD61100A
Controls the SIP conversion.
The operation stops when E is high, and the SIP
conversion starts when E is low.
Input
terminalE
of the
HD61100A
Used for cascade connection with the HD611 OOA to
increase the number of bits which can be SIP converted.
GND
Input terminal for test.
Connect to GND.
Operation of the HD61100A
The following describes an LCD panel with 64 x
240 dots on which characters are displayed with
1/64 duty cycle dynamic drive. Figure 1 is an
example of liquid crystal display and connection to
HD61100A's. Figure 2 is a time chart of
HD61100A I/O signals.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
263
5
HD61100A
COM 1
COM2
COM3
-
1,
1
1,
2
2,
1
2,
2
3,
1
3,
2
I
I
I
------I
I
I
1,
80
1,
81
1,
82
2,
80
2,
81
2,
82
3,
80
I
I
I
I
I
I
I
I
I
I
I
I
------------
1,
160
1,
240
1,
161
2,
2,
160 161
-------- :-2,
-------- 3,240
240
--------i---
i---
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD-PANEL (64 x 240 Dots)
COM63
--
COM64
I
I
I
63,
I
I
I
-
63,
1
2
64,
1
64,
2
I
I
I
I
I
I
I
I
I
I
I
I
63,
80
64,
80
64,
81
64,
82
----Y1
Y2
Y80
:;j
~
-J
a:1~
Iwcnu..::Eooooo
ill
-
M
CL1 .....
CL2
DATE
64,
160
I
I
I
--------- -63,
240
--------- -64,
240
-----
-----
HD61100A (No.1)
:f ~
----------
I
I
I
!
w
a..
0
Y1
Y80
Y2
Y1
HD61100A (No.2)
:f ~
:;j
~ -J
a: I~
Iwcnu..::EOOooo
11
!
w
a..
0
Y80
HD61100A (No.3)
-J
~
.-
~
a:la:
1W~u..::E~OiSo(§
11
!!
ww
00
a.. a..
Cascade three HD611 OOAs. Input data to the terminal DL of No.1, No 2, and
No.3. Connect Eof No.1 to GND. Don't connect any lines to CAR of No.3.
Connect common signal terminals (COM1-cQM64) to X1-X64 of common driver
HD61103A. (m,n) in LCD panel is the address corresponding to each dot.
Figure 1 LCD driver with 64 x 140 dots
HITACHI
264
Hitachi America, Ltd. 0 Hitachi Plaza 0 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0 (415) 589-8300
i
::r:
;::;:
M
CL1
s:»
C'>
~
»
-
·
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~
~
3!
cICi"
s:»
·
I:
en
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...='
&l
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-
~. i
::;;0
-
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0-
s:»
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0
CD
0
'!:.
~
CD
~
~
~
01
00
CD
do
w
0
0
Y1-Y80
N
iil
50
!I
I
I
ri-
III
I
I
I
I
nr.--
I
C
II
I
I
I
I
I
=l
r+-
I
I
I
I
'"
I\J
·
II
I
Timing
chart
of
horizontal
direction
I
I
I
:
_________________________________________________________ J
I
I
..r1
~
""I
0
0
0
~
I
CAR(No. 1)...J I E(No. 2)
I
CAR(No. 2)...J : E(No. 3)
I
CAR(No.3)J I
!:::;:
!"-
ii;-
I
L.fu1.nrt---.IlJ1.11.JLI1Ju---.Il.I111..fUl.h---JUUUUl..fl..
.?'
':"
I
CL2
I
I
~
DL::l!;OO;OO;OC·---~---~---~
3
~
n·
~.
I
--J
Ji
...
=
=
~
000)
i"
M~
CL1
CL2
Dl
""I
I
I
x::=: --- ::=::x
1 Frame
I
M~
I
Y1(No.1) ~
Y2(No.1) ~
I
I
I
_____________________________ _
I
I,
I
I
I
t::
x
Timing
chart
of
vertical
direction
:
j-----
I
CL1
lIUU\h.
I
*
~
I
(")
=-
~
IL..- --- --11
n
- --- -.rtnruU1JUU1 --- .1lUU1J1JUUU1- -- J1IUU1IUUt -----
_-----~-----~--- ~~-- ~-----1mI:
I
;"
IIQ
D:I
.fUUL ---- -.JUUU1.fU1IL
I
Y1-Y80
~
~
:
------
60,1 61.1 62,1 63.1 64,1
------
60.
61.2 62.2 $3.
64,2
I
I
I
I
I
------~
------~
:x:x:x:x:x:x:x:
Y80(No.1)~
Y80(No.3)~
I
r
I
1~
~
~
I
I
Timing chart for the example of connection in figure 1.
DL input (m, n) is the data that corresponds to each address (m, n) of LCD panel.
Timing
chart
of
liquid
crystal
display
driver
output
::r::
t::I
en
.....
.....
o
o
»
I\J
0>
01
II
HD61100A
Application Examples
An Example 01 128 x 240 Dot Liquid Crystal Display (1/64 Duty Cycle)
/ r - - - - - - - - 240 dots
Yl-YBO
HD61100A No.1
5!U)
... ~
IWU)~:E5
J,J,J,
DATE (1)
M
clea:~
Yl-Yeo
Yl-Y80
HD61100A No.2
HD61100A No.3
.... fj ... ~ a:1~
,wiu.:E5 cleo
' ,J,,J,
f
"-
1
5! U)
...
IWU)~:E5
' ,1,,1,
~
I
a:1~
cleo
1
Cll
CL2
DATE (2)
fff
IW 5! fj :E
U) u.
!
d d cl25l~0
!
,f8f
IW ~
~ :E d ~ cllSl~
ff
IW 5! fj :E
U) U.
d ~ cllSl~0
HD61100A No.4
HD61100A No.5
HD61100A No.6
yeo-Yl
YBO-Yl
Y80-Yl
Figure 3 128 x 240 Dot Liquid Crystal Display
The liquid crystal panel (figure 3) is divided into
upper and lower parts. These two parts are driven
separately. HD6l100As No. 1 to No.3 drive the
upper half. Serial data, which are input from the
DATA(l) terminal, appear at YI -+ Yz -+ -- Yso
terminal of No.1, then at YI -+ Y2 -+ -- Yso of
No.2 and then at YI -+ Yz -+ -- Yso of No.3 in
the order ip which they were input (in the case of
SHL =low). HD61100As No.4 to No.6 drive the
lower half. Serial data, which are input from the
DATA(2) terminal, appear at Yso -+ Y79 -+ -- YI
of No.4, then at Y80 -+ Y79 -+ -- YI of No. 5 and
then Yso -+ Y79 -+ -- YI of No. 6 in the order in
which they were input (in the case of SHL =high).
As shown in this example, PC board for display
divided into upper and lower half can be easily
designed by using SHL terminal effectively.
HITACHI
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HD61100A
Example of 64 x 150 Dot Liquid Crystal Display (1164 Duty Cycle, SHL = Low)
150 dots
Liquid crystal display panel
Y1
I I
_ _ _ _ Y80
64 dots
I
Y1 ______ Y70
HD61100A No.1
HD61100A No.2
Figure 4 64 x 150 Dot Liquid Crystal Display
4-bit parallel process is used in this LSI to lessen the power dissipation.
Thus, the sum of the dots in horizontal direction should be multiple of 4.
If not, as this example (figure 4), consideration is needed for input signals (figure 5).
CL1
DATE
-Ili....-___________----InL-_---.;_
J00(!
""'1-------Eff8CtIVe data--------t·I~~~myr
Figure 5
Input Dots, 150 Horizontal Dots
As the sum of dots in lateral direction is ISO, 2 more dummy data bits are transferred (152 =4 x 38).
Dummy data, which is output from Y71 and Y72 of No.2, can be either 0 or 1 because these terminals do
not connect with the liquid crystal display panel.
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
------------------------------------
--
267
HD61102~----------(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Features
Descri ption
HD61102 is a column (segment) driver for dot
matrix liquid crystal graphic display systems. It
stores the display data transferred from a 8-bit
micro-controller in internal display RAM and
generates dot matrix liquid crystal driving signals.
Each data bit of display RAM corresponds to the
on/off state of a dot of the liquid crystal display.
As it is internally equipped with 64 output drivers
for display, it is available for liquid crystal graphic
displays with many dots.
The HD61102, which is produced by the CMOS
process, can complete a portable battery drive
equipment in combination with a CMOS microcontroller, utilizing the liquid crystal display's low
power dissipation.
Moreover it can facilitate dot matrix liquid crystal
graphic display system configuration in
combination with the row (common) driver
HD61103A.
Dot matrix liquid crystal graphic display
column driver incorporating display RAM
RAM data direct display by internal display
RAM
RAM bit data I: On
RAM bit data 0: Off
Internal display RAM address counter:
Preset, increment
Display RAM capacity: 512 bytes (4096 bits)
8-bitparallelinterface
Internal liquid crystal display driver circuit: 64
Display duty:
Combination of frame control signal and
data latch synchronization signal make it
possible to select static or optional duty
cycle
Wide range of instruction function:
Display Data ReadIWrite, Display On/Off,
Set Address, Set Display Start Line,
Read Status
Lower power dissipation: during display 2mW
max
Power supply:
Vee: +5 V ± 10%
VEE: 0 V 10-10 V
Liquid crystal display driving level: 15.5 V
max
CMOS process
lOO-pin flat plastic package (FP-lOO)
HITACHI
268
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61102
Pin Arrangement
ADC
M
vee
V4R
V3R
V2R
V1R
VEE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
(Top view)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
269
HD61102
Absolute Maximum Ratings
Item
Symboi
Value
Unit
Note
Supply voltage
Vee
-0.3to +7.0
V
2
VEE
Vcc -16.5to Vee + 0.3
V
3
Terminal voltage (1)
VTl
VEE - 0.3 to Vee + 0.3
V
4
Terminal voltage (2)
VT2
-{).3to Vcc+ 0.3
V
2,5
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
~5to+125
°C
Notes:
1.
2.
3.
4.
LSls may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended operating conditions.
Use beyond these conditions may cause malfunction and poor reliability.
All voltage values are referenced to GND - 0 V.
Apply the same supply voltage to VEEl and VEE2.
Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R.
Maintain
Vcc~V1L- V1R~V3L- V3R~V4L- V4R~V2L- V2R~VEE
5.
Applies to M, FRM,CL, RST, ADC, +1, +2, CS1, CS2, CS3, E, ANI, Oil, ADC, and DBO-DB7.
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD61102
Electrical Characteristics
(GND = 0 V, Vee = 4.5 to 5.5 V, VEE
= 0 to -lOV, Ta = -20
to +75°C)
Limit
Item
Symbol Min
Input high voltage
VIHC
VIHT
Input low voltage
VILC
Output high voltage
Output low voltage
Va..
Input leakage current
IlL
-1.0
+1.0
High impedance off
input current
ITSL
-5.0
Liquid crystal supply
leakage current
ILSL
-2.0
Driver on resistance
Ra.!
Dissipation current
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Typ
Max
Unit
0.7 xVcc
Vcc
V
2.0
VCC
V
0
0.3xVcc
V
V1LT
0
0.8
V
Va-t
2.4
V
Test Condition
Note
2
2
IOH
=-205 J.LA
3
V
IOL-1.6mA
3
4
+5.0
J.LA
J.LA
Vin .. GND-Vcc
Vin .. GND-Vcc
5
+2.0
J.LA
Vin .. VEE-Vee
6
7.5
Kn
VCC- VEE=15V
±ILOAD =0.1 mA
7
ICC(1)
100
8
500
J.LA
J.LA
During display
Icc(2)
During Access
access cycle ..
1 MHz
8
0.4
Applies to M, FRM, CL, RST, ADC, fj)1, and fj)2.
Applies to CS1, CS2, CS3, E, ANI, OIl, and DBO-DB7.
Applies to DBa-DB7.
Applies to terminals except for DBa-DB7.
Applies to DBa-DB7 at high impedance.
Applies to V1 L-V4L and V1 R-V4R.
Applies to Y1-Y64.
Specified when liquid crystal display is in 1/64 duty.
feu<" 250 kHz (fj)1 and fj)2 frequency)
Operation frequency:
Frame frequency:
fM" 70 Hz (FRM frequency)
Specified in the state of
Output terminal: Not loaded
Input level:
VIH .. Vee (V)
VIL-GND(V)
Measured at Vee terminal
H.TACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
271
HD61102
Interface AC Characteristics
MPU Interface
(GND = 0 V, Vee
= 4.5 to 5.5 V, VEE = 0 to -10
V, Ta = -20 to +75°C)
Item
Symbol
Min
Unit
Note
Ecycletime
tcvc
1000
ns
1,2
E high level width
PWEH
450
ns
1,2
E low level width
PWEL
450
ns
1,2
E rise time
tr
25
ns
1,2
E fall time
tf
25
ns
1,2
Address setup time
tAS
140
ns
1,2
Address hold time
tAH
10
ns
1,2
Data setup time
tosw
toOR
200
ns
Data delay time
Data hold time (Write)
toHw
10
ns
Data hold time (Read)
toHR
20
ns
Typ
Max
320
ns
2,3
2
Notes: 1.
tCYC
E
PWEH
PWEL
. t,
tAH
tr
RtW
CS1-CS3
011
2.0 V
2.0 V
O.SV
tosw
DBO-DB7
2.0 V
O.SV
Figure 1 CPU Write Timing
HITACHI
272
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD61102
2.
~----------tc~y£c==========~
v----- PWEL---~---PWEH ---<>-110
E
RIW
0.8V
CS1-CS3
2.0 V
D/I
0.8 V
DBO-DB7
0.4V
Figure 2
3.
CPU 'Read Timing
DBO-DB7: load circuit
RL-2.4kO
D1
Test
point
RL
R -11kO
C =130 pF (including jig capacitance)
°1
R
D2
D3
D4
Diodes D1 to D4 are alllS2074
®.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
273
HD61102
Clock Timing
(GND
V, Vee
= ..
=4.5 to 5.5 V, VEE = 0 to -IOV, Ta = -20
to +7S°C)
Limit
Max
Unit
Te.t Condition
20
~s
Fig. 3
625
ns
Fig. 3
tWl+2
625
ns
fig. 3
Item
Symbol
Min
+1, t2 cycle time
tcyc
2.5
+1 low level width
tWl+1
+2 low level width
Typ
+1 high level width
tWJi+1
1875
ns
Fig. 3
+2 high level width
tWH+2
1875
ns
Fig. 3
+1-+2 phase difference
1012
625
ns
Fig. 3
+2.....1 phase difference
t021
625
ns
Fig. 3
+1, ~ rise time
tr
150
ns
Fig. 3
+1, +2 fall time
tf
150
ns
Fig. 3
81
tWl.81
t012
t021
82
tWH82
Figure 3 External Clock Waveform
HITACHI
274
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61102
Display Control Timing
(GND = 0 V, Vee = 4.5 to 5.5 V, VEE
=0
to -IOV, Ta
= -20
to +7S0C)
Limit
Item
Symbol
Min
FRM delay time
toFRM
Mdelaytime
tOM
-2
-2
CL low level width
tWlCL
CL high level width
tWHCL
CL
Max
Unit
+2
ILS
Fig. 4
+2
ILS
FIQ.4
35
ILs
FIQ.4
35
ILs
FIQ.4
Typ
Teat Condition
O. 7Vcc \~---I"
FRM
M
Figure 4
Display Control Signal Waveform
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
275
HD61102
Block Diagram
a:
a: a:
.... a:
C\lC')'It
-1-1-1-1
.... C\lC')'It
»»
»»
--------------
L.......-..t .... 1C\l1 C') I
M
L~uid ~ry~al display
driver circuit
~
.... 1C\l1C')1
~
fal;1;l-
C\I'1/,t-
Display date latch
eo eo eo
'It
eo
r-
...CD
<
a:
III
III
~
"'0
:E
i
01
~
I!!
"'0
"2
>X
::l
8
:t.
eo
III
III
I!!
~
~
.!12
0
\be -
L
~
1: ...
1\1 CD
UiUi
N
>"0
'---
~~c
.-
1\1 CD
0=
co
co
----- ---- -----
------
01
CL
FRM
$
c
::l
8
GND - VEE1 - VEE2 - I--
...
.:1:
'E
ADC
.---
:r
----------
-
-jttt
iQ f..._z
00
T
Instruction
register
~
8
~
CD
,
Input
register
Output
register
all
cot
.51
110 buffer
1
1
1
1______ - - - - - C') f---
- co-
---
~
flag
i
:
"""-- ______1
~
-
~
-
HITACHI
276
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
HD61102
Terminal Functions
Connected
Terminal Number of
Functions
Terminals 1/0 to
Name
2
Vee.
GND
Power
supply
Power supply for intemallogic.
Recommended voltage is
GND-aV
Vee.-+ 5V ±10%
VEE1
VEE2
2
Power
supply
8
Power
supply
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is Vee. -15 to GND.
Connect the same power supply to VEE1 and VEE2'
VEE1 and VEE2 are not connected to each other in the LSI.
V1L.
V2L,
V3L,
V4L,
V1R
V2R
V3R
V4R
Power supply for liquid crystal display drive.
Apply the voltage specified for the liquid crystals within the
limit of VEE through Vee..
VIL (V1 R). V2L (V2R):
V3L (V3R), V4L (V4R):
Selection level
Non-selection level
Power supplies connected with V1 L and V1 R (V2L & V2R,
V3L & V3R. V4L & V4R) should have the same voltages.
3
MPU
Chip selection.
Data can be input or output when the terminals are in the
following conditions:
E
1
MPU
Terminal name
CSl
CS2
CS3
Condition
L
L
H
Enable
At write(RIW - low):
At read(RIW • high):
MPU
Data of DBa to DB7 is latched
at the fall of E.
Data appears at DBa to DB7
while E is high.
ReadlWrite.
RIW .. High: Data appears at DBO to DB7 and can be
read by the CPU when E • high, CS1. CS2
• low and CS3 • high.
RIW.Low: DBa to DB7 accepted at fall of E when
OSl, ~-low and CS3 - high.
011
MPU
Data/Instruction.
011 • High:
011. Low:
VcoG-lD
Indicates that the data of DBa to DB7 is
display data.
Indicates that the data of DBa to DB7 is
display control data
Address control signal determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC - High: Y1-$O, Y64-$63
ADC - Low: Y64-$O, Y1~63
HITACHI
Hitachi America,Ltd:· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819. (415) 589-8300
---
~---------.--.--.-----
..---.-------
277
HD61102
Terminal Functions (cont)
Terminal Number of
Connected
Name
Terminals 110 to
Functions
DBO-OB7
8
M
110
MPU
I
HD61103A
Data bus, three-state 110 common terminal.
Switch signal to convert liquid crystal drive waveform into
AC.
FRM
HD61103A
Display synchronous signal (frame signal). Presets the 6-bit
display line counter and synchronizes a common signal with
the frame timing when the FRM signal becomes high.
a..
HD61103A
Synchronous signal to latch display data. The rising edge of
the CL signal increments the display output address
counter and latches the display data.
HD61103A
2-phase clock signal for internal operation. The ,1 and ,2
clocks are used to perform operations (110 of display data
and execution of instructions) other than display.
Y1-Y64
64
o
Liquid
crystal
display
Liquid crystal display column (segment) drive output.
These pins output light on level when 1 is in the display
RAM, and light off level when 0 is in it.
Relation among output level, M, and display data (D) is as
follows:
M---l1
Or
o JTl..QJTl...Q.J
CPU or
external
CR
The following registers can be initialized by setting the RST
signal to low level:
1. On/off register set to 0 (display off)
2. Display start line register set to line 0 (displays
from line 0)
After releasing reset, this condition can be changed only by
instruction.
o
NC
Note:
2
Open
Output terminal for test. Normally, don't connect any lines
to this terminal.
Open
Unused terminals. Don't connect any lines to these
terminals.
1 corresponds to high level in positive logic.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61102
Function of Each Block
Interface Control
1.
I/O butter
Data is transferred through 8 data buses (DBO-OB7).
OB7: MSB (most significant bit)
OBO: LSB (least significant bit)
Oata can neither be input nor output unless CST to
CS3 are in the active mode. Therefore, when CST
to CS3 are not in active mode it is useless to
switch the signals of input terminals except RST
and ADC, that is namely, the internal state is
maintained and no instruction excutes. Besides, pay
attention to
and AOC which operate
irrespectively by CST to CS3.
m
2. Register
Both input register and output register are provided
to interface to MPU whose the speed is different
from that of internal operation. The selection of
these registers depend on the combination of R/W
and 0/1 signals.
a. Input Register
The input register is used to store data
temporarily before writing it into display data
RAM. The data from MPU is written into input
register, then into display data RAM
automatically by internal operation.
Table 1
DII
R/W
When CST to CS3 are in the active mode and
0/1 and R/W select the input register as shown
in table 1, data is latched at the fall of E signal.
b. Output Register
The output register is used to store data
temporarily that is read from display data RAM.
To read out the data from the output register,
CST to CS3 should be in the active mode and
both 0/1 and R/W should be 1. The read display
data ins1ruction outputs data stored in the output
register while E is high. Then, at the fall of E,
the display data at the indicated address is latched
into the output register and the address is
increased by 1. The c::ontents in the output
register is rewritten with READ instruction,
while is held with address set inS1ruction, etc.
Therefore, the data of the specified address cannot
be output with the read display data instruction
right after the address is set, but can be output at
the second read of data. That is to say, one
dummy read is necessary. Figure 5 shows the
CPU read timing.
Register Selection
Operation
Reads data out of output register as internal operation (display data RAM -+
output register).
o
o
o
Writes data into input register as internal operation (input register -+ display
data RAM).
Busy check. Read of status data.
o
Instruction.
HITACHI
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279
HD61102
+
C\I
Z
III
III
+
"tJ
z
iCD
III
o.. III
as! .....
1ij"tJ +
! ciz
i
1ij
~1
:J.c
~
a:lc.l
C
III
1ij1ll
+
Z
z ill'l!
CD1ij:g
III
III
a::"tJII'IZ
!"tJ
i
1ij
~~
til
1ij ~-6
c
>:
E
itllE
CD 1ij :J
a::"tJ:2.
Z
~~
:J.c
a:lc.l
III
CD
~
-E'l::J
~iz
>-t$
III CD
:J.c
a:I c.l
,....
C§
~
W
III
III
!
"tJ
o..
-CD
:J_
o...!a
~ 05~
...
Figure 5
a:I
~
a:I
C
CPU Read Timing
Busy Flag
Busy flag =1 indicates that HD61102 is operating
and no instructions except status read can be
accepted (figure 6). The value of the busy flag is
read out on DB7 by the Status Read instruction.
Make sure that the busy flag is reset (0) before
issuing an instruction.
HITACHI
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HD61102
1
E
I
I
Busy
flag
~
TBusy
-I
11f ClK ~ T Busy ~31 f elK
f ClK is "1, ,,2 frequency
Figure 6
Busy Flag
Display On/Orr Flip/Flop
X, Y Address Counter
The display On/off flip/flop selects one of two
states, on state and off state of segments YI to
Y64. In on state, the display data corresponding to
that in RAM is output to the segments. On the
other hand, the display data at all segments
disappear in off state independent of the data in
RAM. It is controlled by the display on/off
instruction. RST signal = 0 sets the segments in
off state. The status of the flip/flop is output to
DB5 by the status read instruction. The display
On/off instruction does not influence data in RAM.
To control display data latch by this flip/flop, CI
signal (display synchronous signal) should be input
correctly.
A 9-bit counter that designates addresses of internal
display data RAM. X address counter (upper 3 bits)
and Y address counter (lower 6 bits) should be set
by the respective instructions.
2. Y address counter
An address is set by instruction and it is increased
by I automatically by display data R/W operations.
The Y address counter loops the values of 0 to 63
to count.
Display Start Line Register
Display Data RAM
The register specifies a line in RAM that
corresponds to the top line of the LCD panel, when
displaying contents in display data RAM on the
LCD panel. It is used for scrolling the screen.
Dot data for display is stored in this RAM. I-bit
data of this RAM corresponds to light on (data = I)
and light off (data = 0) of I dot in the display panel.
The correspondence between Y addresses of RAM
and segment PINs can be reversed by ADC signal.
6-bit display start line information is written into
this register by the display start line set instruction,
with high level of FRM signal signalling the start
of the display, the information in this register is
transferred to the Z address counter, which controls
the display address, and the Z address counter is
1. X address counter
Ordinary register with no count functions. An .
address is set by instruction.
As the ADC signal controls the Y address counter,
a reverse of the signal during the operation causes
malfunction and destruction of the contents of
register and data of RAM. Therefore, always
connect ADC pin to Vee or GND when using.
preset
Figure 7 shows the relations between Y address of
RAM and segment pins in the cases of ADC = 1
and ADC = 0 (display start line = 0, 1/64 duty
cycle).
HITACHI
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281
HD61,102
--COM1
--COM2
--COM3
--COM4
--COM5
--COM6
--COM7
-l-W-t-"'--- COMS
-+-W-t--- COM9
LCD
display pattem
:r:OJ--- COM62
-l-W-t--- COM63
.J...,.l.,.JW-- COM64
(HD61103A X1)
(HD61103A X2)
(HD61103A X3)
(HD61103AX4)
(HD61103A X5)
(HD61103A X6)
(HD61103A X7)
(HD61103A XS)
(HD61103A X9)
(HD61103A X62)
(HD61103A X63)
(HD61103A X64)
---I HD611 02 Pin Name I
Line 0
Line 1
Line 2
DBO(LSB)
-1!.IJ!.l.!~.t-tI---- DB1
UQ.WU---tin---- DB2
--~!..j.l.~W-iii"1--- DB3
-lLl.2+!-t-Ll1ii11--- DB4
..:CU.Q..UW1-H-H-Hr-:--- DB5
-CU.Q..U;W1-H-H-H-h-- DB6
-CU.Q..U;!.JQ..Hiiii-ti'- DB7(MSB)
Display
RAM data
X.7
.- ....... rr
o
1 o 0 o 0
Line 62 ----- 1 1 1 1 1 0
Line 63 --~-- o 0 o 0 o 0
r--
I I I I I I
o
---I
1 2 3 4 5
RAM Y Address
ADC • 1 (Connected to VCC )
Figure 7· Relation between RAM Data and Display
HITACHI
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HD61102
-----------------------------------------
LCD
display pattern
.....
I
Y1
UneO
Une 1
Une2
000
000
100
010
001
0 0
0 0
000
0
x.
o
o
Display
RAM data
o
......
o
..-,-
o
o
0
1
0
Une 62 ----- 1 1 1 1 1 0
Une 63 ----0
0
0
o o o
I I I I I I
o 1 2 345
COM62
COM63
COM64
(HD61103AX62)
(HD61103AX63)
(HD61103AX64)
,...e:.
J
X .. 7
(HD61103A X1)
(HD61103A X2)
(HD61103A X3)
(HD61103A X4)
(HD61103A X5)
(HD61103A X6)
(HD61103A X7)
(HD61103A X8)
(HD61103A X9)
---.,-
.....
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
----
r-- ........
o
~HD61102 Pin Name
_1..--1---'
I
DBO(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MS8)
1
1
1
1
1
1
1
0
0
I I
I I
I I
I I
I
I
I
I
----=~
616263
RAM Y Address
ADC - 1 (Connected to GND)
Figure 7
Relation between RAM Data and Display (cont)
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. 283
HD61102
Z Address Counter
Liquid Crystal Display Driver Circuit
outputting the display data synchronized with the
common signal. This counter consists of 6 bits and
counts up at the fall of the CL signal. At FRM
high, the contents of the display start line register
are preset in the Z counter.
signal causes one of the 4 liquid crystal driver
levels, VI, V2, V3, and V4 to be output
The combination of latched display data wId lvl
Reset
The system can be initialized by setting RST
terminal to low when turning power on.
I . Display off
Display Data Latch
2.
The display data latch stores the display data
temporarily that is output from display data RAM
to the liquid crystal driving circuit
Data is latched at the rise of the CL signal. The
display on/off instruction controls the data in this
latch and does not influence data in display data
RAM.
Table 2
Item
While RS'i' is low level, no instruction except
status read can be accepted. Therefore, carry out
other instructions after making sure that DB4 = 0
(clear RESET) and DB7 = 0 (ready) by status read
instruction.
The conditions of the power supply at initial power
up are as in table 2.
Power Supply Initial Conditions
Symbol
Reset time
Set display start line register
line 0
Min
Typ
Max
1.0
Unit
~s
Rise time
200
ns
Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off register and in RAM.
Vee
HITACHI
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HD61102
Display Control Instructions
Outline
Table 3 shows the instructions. Read/write (J{IW)
signal, data/instruction (0/1) signal and data bus
signals (DBO to DB7) are also called instructions
because the internal operation depends on the
signals from MPU.
These explanations are detailed in the following
pages. Generally, there are the following three
kinds of instructions.
1. Instruction to set addresses in the internal
RAM
2. Instruction to transfer data from/to the
internal RAM
3. Other instructions
In general use, the second type of instruction are
used most frequently. Since Y address of the
internal RAM is increased by 1 automatically after
writing (reading) data, the program can be
shortened. During the execution of an instruction,
the system cannot accept instructions other than the
status read instruction. Send instructions from
MPU after making sure that the busy flag is 0,
which is the proof that an instruction is not being
excuted.
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285
N
8en
CI)
0)
:J:
~
~
~
2:
o
Code
):0
3
Instructions
CD
.::3.
~
R/W DII
Display on/off
~
•
:J:
,
iii'
n
2:
til
DB7 DB6 DBS DB4 DB3 DB2 DB1 DBD Functions
1/0
Display start line
iSDlav start line (0-63)
Controls display on/off. RAM data and internal
status are not affected. 1: on, 0: off.
Specifies the RAM line displayed at the top of the
screen.
Set page (X address)
0
Sets the page (X address) of RAM in the page (X
N
Set Y address
o
Sets the Y address in .the Y address counter.
en
a;.
Status read
•
8<=>
-
address) register.
Reads the status.
::: :I
RESET
~i
1: Reset
0: Normal
ONtOFF
1: Display off
0: Display on
•
Busy
1: Executing internal oPeration
0: Ready
..,
::;n
~ 3:
CD
::!.
en
go
.::::s
Write display data
o
Write data
51>
(")
):0
CD
.j>.
<=>
<=>
~
--•
CI)
CD
~
:!::
~
c.n
CI)
%
Co>
<=>
<=>
Note: 1. Busy time varies with the frequency (fCU<> of +1, and +2.
(1/ fCLK s TBUSY S 3/ fcLK>
Writes data DBO (LSB)
to DB7 (USB) on the
data bus into display
RAM.
~
Ii"
CM
ia
0'
I:
HD61102
Detailed Explanation
1.
Display on/off
D/I
Code
DBO
DB7 - - - - - - -........
o
D
-
Iow-order bit -
high-order bit
The display data appears when D is 1 and disappears when D is O. Though the data is not on the screen
when D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into
D=l.
2.
Display start line
D/I
Code
o
DB7 -
o
-
.......
A
high-order bit
A
low-order bit -
Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed at
the top of the screen.
Figure 7 shows examples of display (1/64 duty cycle) when the start line = 0-3. When the display duty
cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCD screen, from the line
specified by display start line insttuctioo, is displayed.
HITACHI
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287
HD61102
COM1
COM2
.COM3
COM4
COMS
COMa
COM7
COMS
COM9
COM1
COM2
COMa
COM4
COMS
COM6
COM7
COMS
COM9
COM60
COM61
COM62
COM63
COM64
Start line. 0
COM1
COM2
COM3
COM4
COMS
COM6
COM7
COMS
COM9
Start line - 1
COM1
COM2
COW
COM4
COMS
COM6
COM7
COMS
COM9
Start line. 3
Start line. 2
Figure 7 Relation Between Start Line and Display
HITACHI
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HD61102
3. Set page (X address)
RIW
011
OB7
-------
..........
OBO
o
A
.- high-order bit
A
Iow-order bit -
X address AAA (binary) of the display data RAM is set in the X address register. After that, writing or
reading to or from MPU is executed in this specified page until the next page is set. See figure 8.
4. Set Y address
Code
RIW
011
OB7
0
0
0
I
-------
...........
A
A
OBO
A
.- high-order bit
A
A
low-order bit -
Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Yaddress
counter is increased by 1 every time the data is written or read to or from MPU.
Yaddress
o 1 2 ---------------------------- 61
62 63
OBO
Page 0
OB7
~~------------------------~
OBO
Page 1
OB7
1x.o
1
X-1
~~~~==~~--------~
,....,
~
OBO
OB7
OBO
Page 6
Page 7
OB7
Figure 8
1
1
X.6
X.7
Address Configuration 01 Display Data RAM
HITACHI
Hitachi America, ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
289
HD61102
5.
Status Read
PlW
Code
I
ON/OFF:
RESET:
6.
OB7
0
IBusy I
I
-
Busy:
O/!
'0
I g~~ IRESETI
high-order bit
DBO
0
I
0
I
0
I
0
low-order bit -
When Busy is 1, the LSI is executing internal operations. No instructions are accepted while
Busy is 1, so you should make sure that Busy is 0 before writing the next instruction.
Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is 1, the display is in off condition.
When ON/OFF is 0, the display is in on condition.
RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation
condition.
Write Display Data
RtN
011
CodeI·1
-
DB7
............
DBO
10101010101010
high-order bit
°
low-order bit -
Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1
automatically.
7.
Read Display Data
RtN
Code
011
I
-
DB7
............
DBO
101010101010101
high-order bit
°
low-order bit -
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1
automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of oulput
register in "FUNCTION OF EACH BLOCK".
HITACHI
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-------------------------------------------HD61102
Use of HD61102
Interface with HD61l03A (1164 duty cycle)
1-------..... COM1
Vee>----tVee
V1
V1L,V1R
V6
V6L, V6R
V5
V5L, V5R
V2
V2L, V2R
VEE
VEE
.----1GND
Vee
LCD panel
) ) -
X1
~
I------------..... COMM~
w
L -__~~~----~cn~--~
XM
HD61103A
SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STS
DL
DR
Y1"'-"""'" Y64
M
CL2
FRM
,,1
,,2
Power supply circuit
-----------------1
+5 V (Vee)
R V1
Open
Open
1
1
1
1
1
1
1
Vee
M
CL
FRM
,,1
,,2
HD61102
ADC
Vee
V1L,V1R
V2L,V2R
V3L,V3R
V4L,V4R
VEE1, VEE2
GN
Vee
V1
V2
V3
V4
VEE
RST
I
1
1
.1
I
1
1
R3V2
VEE
I
I
I
I
I
I
I
I
Extemal CR
\
I
0
CPU
: R3=1Sn
1
1
-10V
I
I
I
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
291
HD61102
,,1
~-------".r--
,,2
~-----~
------------------
\\
Input
I
FRM
M
I
! H
X1
I
I
I
--I-t,
I I I
! ! 'I
-+-t-I
I
I
I
I
I
COM
---------
\
~-----~-----_R_f1L
CL
I
I
I
V5!
II
I
I
I
!I
I
:I
I
I
I
I
I
I
I
I
I
I
I
I
I
! H
------4-1
I I
I
I
I
r
I
-----=r-t;11
1 frame
i i -,
I
I
I
I
I
!I
:I
I
11
iI
I
I
II
I
------+-t
I I
frame
I
I
I
t-I
I
I
I
I
I
I
I
I
I
_____ ~
I V6
_____ II I 11
X2
I
I
I
I
I
I
I
I
TTl
I
I
I
I
I
I
I
I
I
I V1
I I
.m
~ ! i~~I~~'-------
I
I
I V1 I
~~I~V~5~--------~
IV6 1
X64
I
~
I
- - --- ::::f'I !=f
I
I
I
!
V6
I
! H
I
I
I
I
I
I
I V1
I!~
Y1
SEG
~ -!
III
II II II
I
I
V1
II
------t-H
lin
! I
il~
II
II
I
I I
JJ11-+------rrw-+-1
V1
I
Y64
i
I
I
I
I
I
I
41
I•
I
I
I
I
.
I
I.
1
I
Selected
I" '1·
I
I
I
I
1
1
I.
I
V3
I
I
I
V
,
I
•
•
Non-selected
YL __ ~
I
II
jJJll
V1
•
V4
-----
I
t
I
!
.
I
I
I
I
The waveforms of Y1 to Y64 outputs vary with the display .date. In this
example, the top line of the panel lights up and other dots do not.
Figure 9 LCD Driver Timing Chart (1164 duty cycle)
HITACHI
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HD61102'
Interface with CPU
1.
Example of connection with 8D6800
Decoder
A15
~
"-./
A1 -L
I
VMA
AO
I
-
,r;- ~
CS2
CS3
Vcc 011
ANI
HD6800
ANI
,,2
DO
I
07
E
I
I
I
HD61102
DBO
I
DB7
fVCC
RES
Figure 10
~
RST
Example of Connection with 8D6800 Series
In this decoder (figure 10), addresses ofHD61102 in the address area ofHD6800 are:
Read/write of the display data
$FFFF
Write of display inslruction
$FFFE
Read out of status
$FFFE
Therefore, you can control HD61102 by readinglwriting the data at these addresses.
HITACHI
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293
HD61102
2.
Example or connection with HD'80l
74LS154
P10
P11
P12
P13
(lOS) SC1
(RIW) SC2
A
YO
B
v.I1 ~
I
I
C
I
Y15
r.!...
0
G1 G2
I
CS1
-*
- ~
Vcc- CS3
t '"
RIW
P14
011
H061102
No.1
H06801
E
E
P30
P31
(Date bus)
I
I
I
I
I
P37
Figure 11
OBO
OB1
I
I
I
OB7.
Example 01 Connection with HD'80l
Set HD6801 to mocle 5. PI0 to P14 are used as
the output port and P30 to P37 as the data bus
(table 11).
•
74LS 154 4-to-16 decoder generates chip select
signal to make specified HD61102 active after
•
•
decoding 4 bits of PI0 to P13.
Therefore, after enabling the operation by PI0
to P13 and specifying DII signal by P14,
read/write from/to the exterruil memory area
($0100 to $OIFE) to control HD61102. In this
case, lOS signal is output from SCI and RIW
signal from SC2.
For details of HD6800 and HD6801, refer to
their manuals.
HITACHI
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HD61102
Example of Application
HD61102
No.9
Y1--Y64
HD61102
No. 10
Y1--Y64
HD61102
No. 16
Y1--Y64
l-------l
l-------l
1-------
COM1
COM2
COM3
i
I
I
<
X1
r-S'iX2"'1ijX3-
r"'as
I
I
II
~~ X64t---==~
l
COMS4
..... :r:
<
1
LCD Panel
128 x 480 dots
X1
COMSS
C') __ X2 r-_~CO~MS~6.
~! X3 t - _....:;...
CDoMS"-I,
~~ l
X64-
:r:
COM128
1-------1
1-------1
1-------1
Y1--Y64
HD61102
No.1
Y1--Y64
HD61102
No.2
Y1--Y64
HD61102
No.8
Figure 12
Note:
Application Example
In this example (figure 12). two HD611 03As output the equivalent waveforms. So. stand-alone
operation is possible. In this case. connect COM1 and COM65 to X1. COM2 and COM66 to X2 •...•
and COM64 and COM128 to X64. However. for the large screen display. it is better to drive in 2
rows as in this example to guarantee the display quality.
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295
HD61103A-----------(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Descri ption
Features
The HD61103A is a common signal driver for dot
matrix liquid crystal graphic display systems. It
generates the timing signals (switch signal to
convert LCD waveform to AC, frame synchronous
signal) and supplies them to the column driver to
control display. It provides 64 driver output lines
and the impedance is low enough to drive a large
Dot matrix liquid crystal graphic display
common driver with low impedance
Low impedance: 1.5 leO max
Intemalliquid crystal display driver circuit: 64
circuits
Internal dynamic display timing generator
circuit
Selectable display duty ratio factor 1/48, 1/64,
1/96, 1/128
• . Can be used as a column driver ttansferring data
serially
Low power dissipation: During display: 5 mW
Power supplies:
Vee: +5 V ± 10%
VEE: 0 to -11.5 V
LCD driver level:
17.0 V max
CMOS process
l00-pin flat plastic package (FP-l00)
screen.
As the HD61103A is produced by a CMOS
process, it is fit for use in portable battery drive
equipments utilizing the liquid crystal display's low
power consumption. The user can easily construct a
dot matrix liquid crystal graphic display system by
combining the HD61103A and the column
(segment) driver HD61102.
Absolute Maximum Ratings
Item
Symbol
Limit
Unit
Note
Power supply voltage (1)
Vee
-0.3 to +7.0
V
2
Power supply voltage (2)
VEE
Vee-19.O to Vee + 0.3
V
5
Terminal voltage (1)
Vn
-0.3 to Vee + 0.3
V
2,3
Terminal voltage (2)
VT2
VEE - 0.3 to Vee + 0.3
V
4,5
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-55 to 125
°C
°C
Notes: 1.
2.
3.
4.
5.
H lSls are used beyond absolute maximum ratings, they may be permanently destroyed. We
strongly recommend you to use the lSI within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
Based on GND .. 0 V.
Applies to input terminals (except V1l, V1 R,. V2l, V2R, V5l, V5R, V6l, and V6R) and 110
common terminals at high impedance.
Applies to V1l, V1 R, V2l, V2R, V5l, V5R, V6l, and V6R.
Apply the same value of voltages to V1l and V1 R, V2l and V2R, V5l and V5R, V6l and V6R,
VEE (23 pin) and VEE (58 pin) respectively.
Maintain Vee ~ V1l = V1 R ~ V6l .. V6R ~ V5l = V5R ~ V2l .. V2R ~ VEE
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HD61103A
Pin Arrangement
X22
X21
X20
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
VEE
V6l
V5l
V2l
V1l
Vee
Dl
FS
(Top view)
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HD61103A
Electrical Characteristics
DC Characteristics (Vee:: +5 V ± 10%, GND :: 0 V, VEE:: Oto -11.5 V,
Ta
=-20 to +7S0C)
Specifications
Test Item
Symbol Min
Input high voltage
VIH
0.7 x VCC
Vee
V
Input low voltage
VIL
GND
0.3 x Vee
V
Output high voltage
Va-!
Vee- O.4
V
1ai-~·4mA
2
Output low voltage
Va.
+0.4
V
1o!-+O.4mA
2
Vi-Xj on resistance
RoN
1.5
kn
Vee-VEE -10V
Load current
±1501lA
3
Input leakage current
1111
-1.0
+1.0
Vin - OtoVee
4
Typ Max
Unit
Test Conditions Note
1
Input leakage current
IIL2
-2.0
+2.0
IlA
IlA
Vin - VEE to Vee
5
Operating frequency
fopr1
50
600
kHz
In master mode
External clock
operation
6
Operating frequency
fopr2
50
1500
kHz
In slave mode
Shift register
7
Oscillation frequency
fosc
315
585
kHz
Cf-20pF±5%
Rf-47kCH2%
8, 13
Dissipation current (1)
IGG1
1.0
mA
In master mode
11128 duty cycle
Cf-20pF
Rf-47kn
9, 10
Dissipation current (2)
IGG2
200
IlA
In slave mode
1/128 duty cycle
9,11
Dissipation current
lEE
100
IlA
In master mode
1/128 duty cycle
9, 12
Notes: 1.
2.
3.
450
Applies to input terminals FS, 081, 082, CR, S'I1.f. SHL, MIS, FCS, CL1, and TH and 110
common terminals DL, M, DR and CL2 in the input state.
Applies to output terminals, +1, ~, and FRM and I/O eommon terminals DL, M, DR, and CL2 in
the output status.
Resistance value between terminal X (one of X1 to X64) and terminal V (one of V1 L, V1 R, V2L,
V2R, V5L, V5R, V6L, and V6R) when load current is applied to each terminal X.
Equivalent circuit between terminal X and terminal V.
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HD61103A
""L, ""R
RON
~L'~R
-----0
\tL,\tR
----~o
VsL,VsR
-----0
+---0 Terminal X (Xl-X64)
t
Connect one of the lines
4.
5.
6.
m.
Applies to input terminals FS, OSl, OS2, CR,
SHl, MIS, FCS, CL1, and TH,lIOcommon
terminals OL, M, DR and CL2 in the input status and NC terminals.
Applies to V1L, V1R, V2L, V2R, V5L, V5R, V61, and V6R.
Don't connect any lines to Xl to X64.
External clock is as follows.
TH
TH
Duty cycle. TH + TL x 1000/0
External clock
waveform
Min
Typ
Max
Unit
45
50
55
0/0
trcp
50
ns
tfcp
50
ns
b:!:t
eye
trcp
External
tfcp
i"]~~
CR R
7.
8.
C
Applies to the shift register in the slave mode. For details, refer to AC Characteristics.
Connect oscillation resistor (Rt) and oscillation capacitance (Cf) as shown in this figure.
Oscillation frequency (fose) is twice as much as the frequency (f.) at.l or +2.
"1, ,,2
Cf.20pF
Rf-47kC
fosc.2 xfs
9.
No lines are connected to output terminals and current flowing through the input circuit is
excluded. This value is specified at VIH • Vee and VIl- GNO.
10. This value is specified for current flowing through GNO in the following conditions: Internal
oscillation circuit is used. Each terminal of OSl, OS2, FS, SHl, MIS, STB, and FCS Is
connected to Vee and each of CLl and TH to GNO. Oscillator is set as described in note 8.
11. This value Is specified for current flowing through GNO under the following conditions: Each
terminals of OS1, OS2, FS, SHL, STB, FCS and CR is connected to Vee, CL1, TH, and MIS to
GNO and the terminals CL2, M, and OL are respectively connected to terminals CL2, M, and OL
of the HD611 03A under the conditions described in note 10.
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299
HD61103A
12. This value is specified for current flowing through VEE under the condition described in note
10. Don't connect any lines to term ina! V.
13. This figure shows a typical relation among oscillation frequency, Rf and Ct. Oscillation
frequency may vary with the mounting conditions.
f
I
I
I
I
I
I
600
--r--------~---I
I
400
-------- --------f----
I
J 200
o
Cf -20pF
I
I
I
I
I
I
I
I
I
I
I
I
50
100
--------~-------I
I
Rf (kn)
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HD61103A
AC Characteristics
(Vee = +5 V ± 10%, GND = 0 V, VEE = 0 to -11.5 V, Ta = -20 to +75°C)
1. Slave Mode (MIS = GND)
CL2
(FCS.GND)
(Shift clock)
tr
tr
CL2
(FCS. Vcc)
(Shift clock)
0.7Vee
DL (SHL • Vee)
DR (SHL • GND)
Input data
DR (SHL • Vee)
DL (SHL • GND)
Output data
0.7Vee
0.3Vee
Item
Symbol
CL2 low level width (FCS • GND)
tWlCl21
450
ns
Typ
Max
Unit
CL2 high level width (FCS • GND)
tWHCL2l
150
ns
CL2 low level width (FCS ., Vee)
tWlCl2H
150
ns
CL2 high level width (FCS • Vee)
tWHCl2H
450
ns
Data setup time
tos
100
ns
Data hold time
tOH
100
Data delay time
too
Data hold time
tOHW
Note
ns
200
ns
ns
10
CL2 rise time
tr
30
ns
CL2falltime
tf
30
ns
Note: 1. The following load circuit-ls oonnected for specification.
Output O~----------~
Terminal
1
;J;
30 pF (Includes jig capacitance)
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301
HD61103A
2. Master Mode (MIS
CL2
= Vee. FCS = Vee. Ct =20 pF. Rt =47 kn)
O.7Vcc
DL (SHL - Vcc)
DR (SHL • GND)
DR(SHL.~)
DL (SHL - GND)
tOFRM ~~~_~:IrtOFRM
FRM
M
O.7Vcc
O.3Vcc
111
,,2
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HD61103A
Item
Symbol
Min
Typ
Max
Unit
Data delay time
too
20
40
5
FRM delay time
tOFRM
-2
+2
Ils
M delay time
Cl2 low level width
Cl2 high level width
tOM
+2
Ils
tWLCL2
tWHCL2
-2
35
35
cp1 low level width
tWl+l
700
Ils
ns
cp2 low level width
tWl+2
700
ns
cp1 high level width
tWH+l
2100
ns
cp2 high level width
tWH+2
2100
ns
cp1-cp2 phase difference
t012
700
ns
cp2- cp1 phase difference
t021
700
ns
cp1, cp2 rise time
tr
150
ns
cp1, cp2 fall time
If
150
ns
Data setup time
los
Data. hold time
tOH
Note
Ils
Ils
Ils
Ils
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303
= 8en
2
~
•.
::E:
;::+
V2L V6L
V1L V5L
X1
l!:
a:
l>
X2 ----
64 output terminal
~----
~
V2R V6R
V1R V5R
X62 X63 X64
I\)
~
3
CD
~.
Vee
...
GN
~
•
::E:
-
~
--
Liquid crystal display
driver circuits
"""'-
VEE
"=.
"'tJ
r
~
•
§
en
CD
CL
lH
il l:
~~
:;;0
r---
o
r--
1~
•
~
~
!"
~
1
Logic:
Bidirectional shift
register
2
....
62
Logic ri-
T
~~
FCS
..
~
......
STB
OsCIllator
~
r--
Timing generation circuit
g-
~
co
•
~
~
~
;
UI
o.
DR
~I-
SH
~
63
64
RtCf
RIQ~
C
MIS
FS
OS10S2
81
82
M
CL2
FRM
~
~
o
eN
»
HD61103A
Block Functions
Oscillator
The CR oscillator generates display timing signals and operating clocks for the HD6ll02. It is required
when the HD6ll03A is used with the HD6ll02. An oscillation resistor Rf and an oscillation capacitor Cf
are attached as shown in figure 1 and terminal STU" is cormected to the high level. When using an external
clock, input the clock into terminal CR and don't cormect any lines to terminal R and C.
CR
f
Rf
Figure 1
I
External Open
clock
Cf
Oscillator Connection with HD61102
The oscillator is not required when the HD61103A is used with the HD61830. Connect terminal CR to the
high level and don't connect any lines to terminals R and C (figure 2).
I
S
ciI
Open
Vee
Open
CR
Figure 2
Oscillator Connection with HD61830
Timing Generator Circuit
The timing generator circuit generates display timing and operating clock for the HD6ll02. This circuit is
required when the HD61l03A is used with the HD6l102. Connect terminal MIS to high level (master
mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from
HD6l830. In this case connect the terminals PS, DSl, and DS2 to high level and MIS to low level (slave
mode).
Bidirectional Shift Register
A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from
DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the
bidirectional shift register, which is on the DL side, corresponds to Xl and the highest order bit on the DR
side corresponds to X64.
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305
HD61103A
Liquid Crystal Display Driver Circuit
The combination of the data from the shift register with the M signal allows one of the four liquid crystal
display driver levels VI, V2, V5 and V6 to be transferred to the output terminals (table I).
Table 1 Output Levels
Data from the
Shift Register
M
Output Level
V2
o
o
V6
o
o
V1
V5
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HD61103A
HD61103A Terminal Functions
Terminal
Name
Number of
Terminal. 110
Connected
to
Function
Voc
1
1
2
Power
supply
Vcc;- GND: Power supply for internal logic.
Power
Liquid crystal display driver level power supply.
V1 L (V1 R), V2L (V2R):
Selected level
V5L (V5R), V6L (V6R):
Non-selected level
GNO
VEE
V1L, V2L,
VSL, V6L,
V1R, V2R,
V5R, V6R
8
Vcc; - VEE: power supply for driver circuit logic.
supply
Voltages of the lavel power supplies connected to V1 L
and V1 R should be the same.
(This applies to the combination of V2L & V2R, VSL &
V5R and V6L & V6R respectively)
MIS
VeeorGND
Selects master/slave.
MIS • Vcc;: Master mode
When the HD61103A is used with the HD61102, timing
generation circuit operates to supply display timing
signals and operation clock to the HD611 02. Each of
ItO common terminals Dl, DR, CL2, and M is in the
output state.
MIS. GND: Slave mode
The timing operation circuit stops operating. The
HD61103A is used in this mode when combined with the
HD61830. Even if combined with the HD611 02, this
mode is used when display timing signals (M, data, CL2,
etc.) are supplied by another HD61103A in the master
mode.
Terminals M and CL2 are in the input state.
When SHL is Vee, DL is in the input state and DR is in
the output state.
When SHL is GND, DL is in the output state and DR is in
the input state.
FCS
Vee or GND
Selects shift clock phase.
FCS • Vee: Shift register operates at the rising
edge of CL2. Select this condition
when HD61103A is used with HD61102
or when MA of the HD61830 connects
to CL2 in combination with the
HD61830.
FCS • GND: Shift register operates at the fall of
CL2. Select this condition when CL1 of
HD61830 connects to CL2 in
combination with the HD61830.
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307
HD61103A
HD61103A Terminal Functions (cont)
Terminal
Name
Number of
Terminals 1/ 0
FS
DS1,DS2
2
Connectod
to
Function
Vee or GND
Selects frequency.
When the frame frequency is 70 Hz, the oscillation
frequency should be:
fose • 430 kHz at FCS - Vee
fose - 215 kHz at FCS - GND
This terminal is active only in the master mode. Connect
it to Vee in the slave mode.
VeeorGND
Selects display duty factor.
Display Duty Factor
1/48
1/64
DS1
GND
DS2
GND
1196
1/128
GND
Vee
Vee
Vee
GND
Vee
These terminals are valid only in the master mode.
Connect them to Vee in the slave mode.
STB
Vee or GND
1H
OL1
Input terminal for testing.
Connect STS to Vee.
Connect TH and OL1 to GND.
OR,R,O
3
Oscillator.
In the master mode, use these terminals as shown
below.
Usage of these terminals in the master mode:
Internal oscillation
External clock
In the slave mode, stop the oscillator as shown below:
Open
Vee
I
I
IR
2
o
HD61102
OR
Open
I
oI
Operating clock output terminals for the HD611 02.
Master mode: Connect these terminals to terminals
.1 and 4>2 of the HD611 02
respectively.
Slave mode: Don't connect any lines to these·
terminals.
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HD61103A
HD61103A Terminal Functions (cont)
Terminal
Name
Number of
Terminals 1/0
FRM
0
Connected
to
Function
Frame signal.
HD61102
Master mode: Connect this terminal to terminal FRM
of the HD611 02.
Slave mode:
M
1/0
Don' connect any lines to this
terminal.
Signal to convert LCD driver signal into AC.
MBof
HD618300r
Master mode: Output terminal
MofHD61102
Connect this terminal to terminal M of
the HD61102.
Slave mode: Input terminal.
Connect this terminal to terminal MB
ofthe HD61830.
CL.2
110
CL10rMA
of HD61830
orCLof
HD61102
Shift clock.
Master mode: Output terminal
Connect this terminal to terminal CL of
the HD61102.
Slave mode: Input terminal
Connect this terminal to terminal CL 1
or MA of the HD61830.
DL,DR
2
110
OpenorFLM
ofHD61830
Data ItO terminals of bidirectional shift register.
DL corresponds to X1's side and DR to X64's side.
Master mode: Output common scanning signal.
Don' connect any lines to these
terminals normally.
Slave mode:
Connect terminal FLM of the HD61830
to DL (when SHL. Vee) or DR (when
SHL.GND)
GND
Vee
MIS
t-C
SHL
5
Vee
GND
Output
Input
Output
Out~ut
Out~ut
In~ut
SHL
Vee
GND
DL
Output
[R
Out~ut
Open
Not used.
Don' connect any lines to this terminal.
VeeorGND
Selects shift direction of bidirectional shift register.
SHL
Shift Direction
Common Scanning Direction
Va;
DL-+DR
X1-+X64
GND
DL+-DR
X1 +- X64
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309
II
HD61103A
HD61103A Terminal Functions (cont)
Tsrm!na!
Name
Number of
Terminals 1/ 0
Xl·X64
64
0
COiiii&eiid
to
Function
Liquid crystal Liquid crystal display driver output.
display
Output one of the four liquid crystal display driver levels
Vl, V2, V5, and V6 with the combination of the dat from
the shift register and M signal.
r
~....;o~....
Data~
g~~ut
14 V2.14 V6 .1.Vl.I.V5 _I
Data 1: Selected level
0: Non-selected level
When SHL is Vee, Xl corresponds to COMl and X64
corresponds to COM64.
When SHL is GND, X64 corresponds to COMl and Xl
corresponds to COM64.
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H: vee }Fixed
L: GND
::I:
~
§"
en
2:
::t: ....
en en ....
C\I
"-" means "open".
.1
.2
FRM
M
CL2
SHL
DL
H
fromFLM
of
HD61830
::!.
~
fromMB from CL1
of
of
HD61830 HD61830
LLLLHHHHH--
Ji!
g<=>•
B
fromMB fromMA
of
of
HD61830 HD61830
LLLHHHHHH--
L
H
L
W-
:!:
~~
;0
ii
C
L L L
H
fromMB from MA
of
of
HD61830 HD61830
H H H H H --
·
tD
::!.
'"~
o
HLLHH
}D
LL
or
LH
H
Rf
Cf
RfCf
~
~
'i:
~
co
LL
E
•
~
~
HLLHH
or
LH
...
~
F
to~
COM1-COM64
10.2
lOFRM
10M
toCL
H
of
of
of
of
of
HD61102 HD61102 HD61102 HD61102 HD61102
L
. from FLM COM64-COM1
of
HD61830
from FLM 10 DUDR
ofHD61103A COM1-C0M64
of
HD61830
No.2
10 DLJDR of from FLM
HD61103A
of
COM64-COM1
No.2
HD61830
from DUDRof
COM65-COM128
HD61103A
No.1
a
"CI
~
I'D
n
S-
o
II
II
ft
cII
..•
~
"CI
"CI
n
~
e
1:1
from DLJDR
of HD61103A COM128-C0M65
No.1
COM1-COM64
COM64-COM1
10 DLJDR
10.1
to.210 FRM
10M
10 CLofo H
of HD61103A COM1-C0M64
H
Rf Cf
of
of
of
of
HD61102
No.2
Cf
HD61102 HD61102 HD61102 HD61102 to CL2 of
to DLJDR
HD61103AHD61103A L ofHD61103A
COM64-COM1
No.2
Rf
C11
!g
H
L
~~
X1-X64
~
fD
ft2:
Sl
DR
~
.. >•-.
.-•.
I-'
I-'
0
m a:
1
~t-c3flu..~~t;qa:o
A
10
0-
Cf: OscIllation capacitor
CD
~
•
::I:
=~
Rf: Oscillation resister
L L L H H H H H H --
from DLJDR
COM1-COM64
from M from CL2 H of HD61103A
of
of
____~N~0~.~1_____________________
HD61103A HD61103A
from DLJDR
No.1
No.1
L
ofHD61103A COM64-COM1
No.1
:r:
o
en
~
~
o
w
>
HD61103A
Outline of HD61103A System Configuration
1.
Use with HD61830
a. When display duty ratio of LCD is more than 1/64
H061830EbH
No.1
COM 1
LCD
I
a..:CO=M~64.;:;..._--,.
One H061103A drives
common signals.
Refer to
Connection list A
One H0611 03A drives
common signals for
upper and lower
panels.
Refer to
Connection list A
Two H0611 03As drive
upper and lower
panel separately
to ensure the
quality of display.
No. 1 and No.2
operate in parallel.
For both of No. 1
and No.2. refer to
Connection list A
H061830
Upper
Lower
H061830
--t-----.
LCD
Upper
Lower
b. When display duty ratio of LCD is from 1/65 to 1/128
LCD
Two H061103As
connected serially
drive common signals.
Refer to
Connection list B
for No.1.
Refer to Connection
list C for No.2.
Two H06l1 03As
connected serially
drive upper and
lower panels in
parallel.
Refer to
Connection list B
for No. 1.
Refer to Connection
list C for No.2.
Two sets of
H061103As connected
serially drive upper
and lower panels in
parallel to ensure
the quality of display.
Refer to
Connection list B
for No. 1 and 3.
Refer to
Connection list C
for No.2 and 4.
LCD
LCD
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HD61103A
2.
Use with HD61102 (1164 duty ratio)
COM1
COM64
H061102
LCD
LCD
COM1
Upper
COM64
COM1 Lower
H061102,,-,C...0,,,,,M:.;.;:64;..:..._--,
Upper
Lower
One H0611 03A drives
common signals and
supplies timing
signals to the
H061102s.
Refer to
Connection list 0
One H061103A drives
upper and lower
panels and supplies
timing signals to
the H0611 02s.
Refer to
Connection list 0
Two H061103As drive
upper and lower
panels in parallel
to ensure the
quality of display.
No. 1 supplies
timing signals to
No.2 and the
H061102s.
Refer to
Connection list E
for No.1
Refer to
Connection list F
for No.2
I
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313
HD61103A
Connection Example 1
Use with HD6i i02 (RAM type segment driver).
a. 1/64 duty ratio (See Connection List D)
Cf
Rf
+5 V (V e)
Rt
-
R
Vee
F\~ Vt
VtL, VtR
C;;::l R3 V6 V6L, V6R
...
R1
R3V5
R3V2
COM64
M
CL
FRM
,,1
,,2
M
CL
FRM
,,1
,,2
a
1ii
~
~
V5L, V5R
S
.,...
V2L,V2R
0
J:
co
VEE
(-::reontrast
GNo
J,
X64
(Xt)
...J
.!Il
VEE
-10V
OV
~
...J
LCD panel
en
~F!V4
I,
) )
J:
~R3
Rt
COMt
)
' - - CR
Rt t:i;t1R3
---V3
R2
Xt
(X64)
r-- C
Open- oL
Open- DR
Vee
Ho6tt02
a: a: a: a:
>~~~
,.j ,.j ,.j ,.j 0 ~
v~Jvl~ ~~ L
SHL I--OS1 I DS2 i - .....,
TH ' Cll
FS
I-
~C)~
-
-
MIS
FCS
STB
....., i .....,
.....,
Ii-
R3 -150
~
Figure 1 Example 1
Note:
1.
The values of R1 and R2 vary with the LCD panel used.
When bias factor is 1/9, the values of R1 and R2 should satisfy
Rt
t
4Rt + R2-9
For example,
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314
w
>~~~~C)~
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD61103A
a
1
C?
e.
cc
..J
I
j
8c
!
~
"'0
CD
18
.c
Q.
I
..Ja:
ce.
N
III
I
I
CDI
EI
l!1
-I
I
.... 1
I
I
1
I
- -----~ ---.-..;......
(,)
....III
Figure 2
Example 1 Waveform (RAM type, 1/64 duty cycle)
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Blisbane, CA 94005-1819· (415) 589-8300
~~~~~--"-"---"------
".-
315
HD61103A
Connection Example 2
Use with HD61830 (Display controller).
a. 1/64 duty ratio (See Connection list A)
Open
Vee
Open
C
CR
R
X1
(X64)
Vee
Vee
X64
(X1)
c:
.2
~c:
c:
) )
)
V1
V1L, V1R
V6
V6L, V6R
E
~
w
COM1
~
LCD panel
COM64
R
..J
::J:
fJ)
1ii
.!!!
V5
V2
8
II)
II)
V5L, V5R
c(
V2L, V2R g
C\I
a;
c
M
CL2
DL(DR)
DR(DL)
VEe
VEE
GND
GND
Open
Open
Open
FRM
,,1
,,2
Open
HD61830
(Display Controller)
Vee
::J:
fJ)
MB
CL1
FLM
SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STB
Figure 3
Example 2 (1164 duty ratio)
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HD61103A
1~
~
;1;
.~.----------r-=-----------~!l)~
-----
. ------- ---------- ------------
...j
...
- - - - - - - - - - - -...CQ~--I
.....
~~
>
-------- ! §:
'"'---------~/
O£8l90H wOJ:I
Figure 4 Example 2 Waveform (1/64 duty ratio)
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8~00
317
HD61103A
b. 1/100 duty ratio (See Connection list B, C)
Vee
Opi" torn
;'Vee - - - - - - - - . - t Vee
~
V6
a:
50
SHLI-fOS1 "-IOS2 "-ITHI-
~L~R
...---'"T""I-H V6L. V6R
....--t+-I-HV5L. V5R
r--_H-I-HV2L. V2R
---~
VEE
r-+-H-I-HGNO
V5------.I
;_
.;
• MlSI-
~ FCSI--
~ CI) STB I-~
1i
eD ....!II X1 1----,
o ci ~ (X64
V 2 - - - -......
J:Z
e-:J
00
::Ed~~
VEE-----+
GNO'-----44
r--H-+++t-It---I--i
~
fro
MB-
~
LCD
COM64 Panel
{
J
{
J
r- COM100
X36.1--_...J1
(X29
SHL...J~ OS1OS2...J TH-
1 .
~
Open- C
Vee- CR
Open- R
~
)
-
L-f----tVEE
I------IGNO
~ ~
....-----<--t COM65
X1
(X64
...Ja:
Vee 0 0
V1L. V1R
V6L. V6R
V5L.V5R
'----IV2L. V2R
~COM1
1--_ _....
oe.e.
FLM -
)
&~~f-
::E~C[:::r
MA-
CL1 "FS"-I-
...J~
'i
/ee
g...
~
CL1-
FS-fMIS"FCS"-I1...-_ _ _....;:;..;.;:;.,1
STBI-I-
eD
'"
C\I .!II
Oo~
J: Z ~
Vee
Figure 5
Example 2 (1/100 duty ratio)
HITACHI
. 318
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61103A
-j
N~------1-£ ~ ~
>
- -----.,....
,
----- -
&I)
>
> --------
&I)
-------
> ---
------ -- ------- ------- --------- ~
I
I
I
I
I
I
I
I
I
-------~-..,
--------'--..,
--------r--....
GI
E
!
1
~
--------
4(
CD
--~
..J .....
,
CO
2
2
..J
LL.
OE8~9aH
4(
c"""""" x;Z
-- ----- ;z-If!.
~
xx
......
2 .... ,CJ:~
~
·oN
VEO~~9aH
~
~
>
------- -------
....
,
•
..J
J:
en
~i
CDG)
X~ ---- ~s.
....
~
·ON
VEO~~9aH
Figure 6 Example 2 (1/100 duty ratio)
HITACHI
HJtachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
319
/
HD61104,HD61104A--(Dot Matrix Liquid Crystal Graphic
Display Column' Driver)
Description
Ordering Information
HD61l04, HD61104A is a column (segment)
driver for large-area dot matrix liquid crystal graphic
display systems.
Type No.
Level (V)
Package
HD61104
+10to+26
100 pin plastic
LCD Driving
_ _ _ _ _ _ _ _ _aFP (FP-100)
Features
Display duty cycle: 1/64--1/200
Intemalliquid crystal display driver: 80 drivers
4-bit bus, bidirectional shift data transfer
Cascade connection with enable format
Data transfer rate: 3.5 MHz
Power supply for logic circuit 5 V ±10%
Power supply for LCD drive circuits :
10 to 26 V (HD6l104)
10 to 28 V (HD61104A)
Standby function
CMOS process
loo-pin flat plastic package
HD61104A
+10 to +28V
HD61104lF
+10 to +28V
100 pin plastic TaFP (lFP-100)
Absolute Maximum Ratings
Item
Supply voltage (1)
Symbol
Value
Unit
Note
2
Vee
-0.3 to +7.0
V
HD61104
VEE
Vee - 28.0 to Vee + 0.3
V
HD61104A
VEE
Vee - 28.5 to Vc;c + 0.3
Terminal voltage (1)
Vn
-0.3 to Vee + 0.3
V
2,3
Terminal voltage (2)
VT2
VEE - 0.3 to Vee + 0.3
V
4
Operating temperature .
Top!'
-20 to +75
°C
Storage temperature
Talg
. -65to+125
°C
Supply voltage (2)
Notes: 1•
2.
3.
4.
LSls may be permanently destroyed if used beyond the absolute maximum ratings. In
ordinary operation, it Is desirable to use them within the limits of electrical characteristics,
because using them beyond these conditions may cause maHunc1lon and poor reliability.
All voltage values are referenced to GND • 0 V.
Applies to input terminals, SHL, CL 1, CL2, 00-03,1:. and M.
Applies to V10 V2. Va. and V4. Must maintain
Vee ~ V1 ~ Va~ V4~ V2~ VEE
Connect a protection resister of 15 n ± 1O"A. to each terminal In series.'
HITACHI
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HD61104, HD61104A
Pin Arrangement
(Top View)
(FP-100fTFP-100)
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321
W
N
N
'==
:I:.
ill:'
en
.....
.....
Q
n
:::I:
Sf
n
V1 V2 V3 V4
:!.
Y1 Y2
C
...0
Y80
0
~
D)
»
~
3CD
;
:J.
n
Jl>
S
en
.....
~
.....
:::I:
s=
0
M
n
:!.
~
~
~
'"•
I
CL1
VCC
GNO
VEE
N
0
0
0
en
~-
J:
Do
~. ~.
01
~
iil
~
;;
~ J:
~
·-
OJ
CD
~.
SHL
c:r
CL2
-''"D
(")
»
:::J
<0
0
"""
0
'i:
~
·
<0
~
~
en
0:>
<0
do
w
0
0
E
CAR
Control circuit
>
HD61104, HD61104A
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, GND = 0 V, Vee - VEE = 10 to 26 V (HD61104), Vee - VEE = 10
to 28 V (HD61104A), Ta
-20 to +75°C)
=
Max
Unit
0.7 x Vee
Vee
V
0
0.3 x Vee
V
Typ
Te.t Condition
Note
1oH--400~
2
kn
VEE - -1 OV.Load
current -100 ~
5
~
VIN-OtoVee
25
~
VIN - VEE to Vee
rnA
rnA
Item
Symbol Min
Input high voltage
VIH
Input low voltage
Vil
Output high voltage
V(Ji
Vee- 0.4
Output low voltage
Va..
0.4
V
Driver on resistance
Po!
7.5
Input leakage current
IlL 1
-1
Input leakage current
11L2
-25
V
Dissipation current (1)
IGND
2.0
Dissipation current (2)
lEE
0.2
Notes:
1.
2.
3.
4.
5.
6.
1ST
100
4
HD61104
4
HD61104A
0.4
Dissipation current (3)
3
~
4
5
Applies to CL1. Cl2. SHL. E. M. and Do-Ca.
Applies to CAR.
Applies to VI. V2• V3. and V4.
Specified when display data is transferred under following conditions:
Cl2 frequency fcp2 • 2.5 MHz (data transfer rate)
CL1 frequency fcp1. 14.0 kHz (data latch frequency)
fM • 35 Hz (frame frequencyl2)
M frequency
Display duty ratio 11200
Specified when VIH • Vee. VIl- GND and no load on outputs.
IGND:
currents between Vee and GND
lEE:
currents between Vee and VEE
Currents between Vee and GND at standby (E input. high).
Resistance between terminal V (one of V1 to V80) and terminal V (one of VI. V2. V3. and V4)
when load current flows through one of the terminals V1 to V80. This value is specified under
the following conditions:
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323
HD61104, HD61104A
\bc- VEE- 26 V
V1 • V3- Vcc-2110 (Vee- VEE)
V2 • V4- VeE+ 2110 (Vce- VEE)
RON
V1L. V1R
0
VJL.VJR
0
V4L. V4R
0
+---0 Terminal Y
(Y1-Y80)
'O---">JV''v----t
V2L. 'l2R
The following is a description of the range of power supply voltage for liquid crystal display drives. Apply
positive voltage to Viand V3. and negative voltage to V2 and V4. within the flV range. This range allows
stable impedance on driver output (RoN). Notice that fl V depends on power supply voltage Vcc -VEE.
---,..-_______ Vec
-------- V1
IN
---- Va
~ 5.5
a ----------A
------------ V4
-------------- ~E
10
26
"cC-'VEE (V)
Correlation between Power
Supply Voltage VCC- VEE and JjJ
Correlation between Driver
Output Waveform and Power
Supply Voltages for Liquid
Crystal Display Drive
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61104, HD61104A
Terminal Configuration
Input Tennlnal
Applicable Tennlnals :
CL1. SHL, E. M
Vr;c
~+---PMOS
~
NMOS
Input Tennlnal (controUed by Enable signal)
Applicable Tennlnals :
CL2. Do-Da
Vr;c
Vr;c
CL2
"':':
Enable
OUtput Tennlnal
Applicable Terminal :
CAR
Vee
PMOS
NMOS
r-
Output Tennlnal
Applicable Terminals:
Y1-Y80
.J:'""" PMOS
PMOS
V1
V3
Vee
.J:'""" NMOS
:1:-
NMOS
V4
V2
VEE
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra POint Pkwy.· Brisbane. CA94005"1819· (415) 589-8300
\
325
HD61104, HD61104A
AC . Characteristics
(V cc 5 V ± 10%, GND
=
=0 V, Ta =·20 to ±7SOC)
Typ
111 ax
Item
Symbol
IIln
Unit
Clock cycle time
tcve
285
ns
Clock high level width
tcwH
ns
Clock low level width
tcwL
110
110
ns
Clock setup time
tSCl
80
ns
Clock hold time
lHcL
80
ns
Clock riselfall time
Data setup time
tcr
tosu
80
ns
80
75
ns
Data hold time
tOH
Esetuptime
tESU
Output delay time
tOCAR
M phase difference time
!eM
CL1 cycle time
tcL1
Note:
1.
30
ns
ns
180
300
tcvc x10
Note
ns
ns
ns
The following load circuit is connected for specification:
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H.itachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61104, HD61104A
Test point
0-0- - - - ,
tCL1
CL1
------'1"
CL2
CL1
CL2
M
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
327
HD61104, HD61104A
Terminal Number of
Connected
Terminals 1/0 to
Name
Functions
Y1-Y80
80
o
Power
supply
Vee- GND:
Power supply for internal logic
Vee-VEE:
Power supply for LCD drive circuit
Power
supply
Power supply for liquid crystal drive.
V10 V2: selection level
V3 • V4: non-selection level
LCD
Liquid crystal driver outputs.
Selects one of the 4 levels. V1• V2 • V3• and V4• Relation
among output level. M. and display data (D) is as follows:
M~
D~
M
Controller
CL1
Controller
Switch signal to convert liquid crystal drive waveform into
AC.
Latch clock of display data (falling edge triggered).
Synchronized with the fall of CL 1. liquid crystal driver
signals corresponding to the display data are output.
Cl2
Controller
Shift clock of display data (D).
Failing edge triggered.
4
Controller
Input of 4-bit display data (D)
o
Liquid Crystal
Driver Output
Liquid Crystal
Display
1
(High level)
Selection
level
On
o
Non-selection
level
Off
(Low level)
Truth table (Positive logic)
SHL
Input data and latch circuit 1
o
~ ~2 ~6~
10 -- ~74 ~78
Do ~4~8 ~ 12 -- ~ 76 ~80
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61104, HD61104A
Connected
Terminal Number of
Name
Terminals 1/0 to
Functions
Truth table (Positive logic) (cont)
Input data and latch circuit 1
SHL
Da -+80 -+76 -+72 --- -+ 8-+4
02 -+ 79 -+ 75-+ 71 --- -+ 7 -+ 3
0 1 -+78 -+ 74 -+ 70 - -+ 6-+2
Do -+n -+73 -+69 --- -+ 5 -+ 1
When SHL - 0, the data that is input to 03 is
ex:
latched to each bit of the latch circuit 1 in order of 1 -+ 5 -+
9 --- -+n.
SHL
Vcc or GNO
I:
GNOorthe
Enable input.
terminal CAR The operation stops at high level, and is enabled at low
of the
level.
Selects a shift direction of display data.
H061104
CAR
NO
0
3
Enable output.
Input
terminal E of Used for cascade connection.
the H061104
Unused. No wire should be connected.
HITACHI
,
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
329
HD61104, HD61104A
Typical Application
Figure 1 is an LCD panei with 200 x 640 dots on which characters are dispiayed with 1/200 duty cycle
dynamic drive.
COM1
COM2
COM3
--
1,
1
1,
2
1,
80
1,
81
82
2,
1
2,
2
2,
80
2,
81
2,
82
3,
1
3,
3
I
I
I
---I
I
I
---- I
I
I
I
~
------
I
I
I
I
I
I
~
~
------ I-
I
I
I
I
I
640
-------- -2,
640
f--- -------- 3,
r-- -------- ~
I
I
I
f---
2,
------
3,
80
I
I
1,
1,
1,
I
I
I
I
II
I
I
I
I
LCD Panel (200 x 640 Dots)
COM199
COM200
-
-
I
I
I
I
I
I
199, 199,
1
2
200, 200,
1
2
I
----
I
I
I
----
I
I
I
I
I
I
I
I
199,
80
200, 200, 200,
80
81
82
----Y2
Y1
Y80
d')
~
11
------ r-200,
I
I
I--
f--~
I--
I
I
-------- f--199,
-------- ,640
200,
640
160
Y2
Y1
----Y80
HD61104 (No.2)
IF
~ I
:i5000 ~
.-
------
I
I
I
-----
HD61104 (No.1)
:r
IWI/)
I
I
I
~
:r
IWI/)
d')
~
I
:i5000 ~
.-
1
IF
HD61104 (No.8)
0<'1
-----
~
:r
IWI/)
L_____ ~ 1
-------------
M J..
1_
CL
CL2
Y80
Y1
-~ I
:i5ocP
If~
i
0
-----
DATA
Figure 1 200 x 640 Dot LCD Panel Example
Cascade eight HD6l104s. Input data to the DcrD3 tenninals of Nos. 1-8. Connect E of No.1 to GND.
Connect no lines to CAR of No.8. Connect common signal tenninals (COMI-COM200) to the
common driver HD61105. (m,n) of LCD panel is the address corresponding to each dot. Figure 2 shows
timing.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
:x:
i i i
M~
J
J
s=
n
2:
I
3CD
:::!.
1"
?-
•
:x:
s:
n
2:
-0
;;;-
'!!J
o'Q'
N
..
'"•
c:
"t
N
0
0
0
N
en
iil
:I
~
a
-0 n
-0
0
.
[
':'"
tD
I
<
CS'
"t
Ii!
~
I»
'"cr
"C
'"
:::J
(")
:t-
eo
.".
0
0
~
~
.!
..
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HD61105,HD61105A~-(Dot Matrix Liquid Crystal Graphic
Display Common Driver)
Description
Pin Arrangement
The HD61105, HD61105A is a common signal
driver for dot matrix liquid crystal graphic
display systems. It provides 80 driver output
lines and the impedance is low enough to
drive a large screen.
As the HD61105, HD61105A is produced in a
CMOS process, it is fit for use in portable
battery drive equipments utilizing the liquid
crystal display's low power consumption.
JJ:JJJJJJJJJJJJJJJJJ
I
...x......
.......
x,.
......
••
I
I
x.
Xu
,~
Xu
x..
x..
Xu
x..
x..
x..
x..
x..
x..
x..
• x••
x..
x"
x"
x••
x"
x"
x••
I
1
x"
x..
XI. II
Features
x"
Xu
x,.
•
x,
X.
x,
•
•
•
•
•
•
•
1 Xu
x"
x"
x"
x"
x"
x"
x"
x"
x"
" x••
X, ..
Dot matrix liquld crystal graphic display
common driver with low impedance
Internal liquid crystal display driver circuit: 80 circuits
Display duty ratio factor: 1/64-1/200
Internal BO-bit shift register
Power supply for logic circuit: 5 ± 10%
Power supply for LCD drive circuits:
-10 to 26 V (HD61105)
-10 to 28 V (HD61105A)
CMOS process
100-pin plastic QFP (FP-100)
x,
X.
x.
x.
x,
x..
x..
x..
71 Xu
,. x..
~~.~.~~.~~.-~,~,~.~.~.~~~.r'
i~~~a~iG~~3~8~~~>~~~
FP-1 00/TFP-1 00
(TopViewl
Ordering Information
Type No;
LCD Driving
Level (V)
HD61106
10 to 26
HD61106A
10 to 28
HD61106TF
10 to 28
Package
100 pin
plastic
QFP (FP-100)
100 pin
plastic
T-OFP (TFP-100)
HITACHI
332
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
HD61105, HD61105A
Block Diagram
80 output terminals
Vee
GNO
__
Uquid crystal
L:J~L:~ ~di~SP~la~Y~d~n~·v~er~C~ir~Cu~it~-1::t:J::F======~~____f.- M
VEE
Bidirectional
shift register
01--11----1
t--;--oo
SHL~------~-------+~--------------------------------------~
CL-II---I
FCS--t----t
Absolute mazimum ratings
Item
Symbol Value
Supply voltage (1)
Vee
VEE
HD61105
Supply voltage (2)
HD61105A
Unit
Note
- 0.3 to + 7.0
V
2
Vee - 28.0 to Vee + 0.3
V
5
Vee - 28.5 to Vee + 0.3
Terminal voltage (1)
Vn
- 0.3 to Vee +0.3
V
2. 3
Terminal voltage (2)
Vr2
VEE - 0.3 to Vee +0.3
V
4. 5
Operating temperature
Topr
- 20 to + 75
·C
Storage temperature
Tstg
- 55 to + 125
·C
Notes: 1. LSls may be permanently destroyed if used beyond the absolute maximum ratings. In
ordinary operation. it is desirable to use them within the limits of electrical characteristics.
because using them beyond these conditions may cause malfunction and poor reliability.
2. All voltage values are referred to GND = 0 V.
3. Applies to input terminals except Vl. V2. Vs. and Va.
4. Applies to V" V2. V5. and Ve.
5. Vee ~ Vl ~ Va ~ Vs ~ V2 ~ VEE must be maintained.
HITACHI
Hitachi America, Ltd.· Hitachi PI.aza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
333
HD61105, HD61105A
Electrical Characteristics
DC Cbaracteristlc8
(Vee = 5 V ± 10%, GND = 0 V, Vee - Va = 10 to 26 V (H061105), Vee - Va = 10 to 28 V
(HD61105A), T.
20 to + 75'C)
=-
Specifications
Teatltam
Symbol
Min
Input high voltage
VIH
Input low voltage
Typ
Max
Unit
0.7 x Vee
Vee
V
VIL
GND
0.3 x Vee
V
Output high voltage
VOH
Vee - 0.4
Output low voltage
VOL
0.4
V
Vi-Xj on resistance
RON
2.0
kG
V
Teat Condition
Note
= - 0.4mA
10L = 0.4mA
Vee - VEE = 10V
2
IOH
2
5
Load current
± 150 pA
Input leakage current
hLl
- 1.0
1.0
pA
VIN = 0 to Vee
Input leakage current
hL2
- 25
25
pA
VIN
Clock frequency
fCl
100
kHz
Transfer clock CL
Dissipation current (1)
IGGl
200
pA
at 1/200 duty
cycle operation
6
Dissipation current (2)
lEE
100
pA
at 1/200 duty
cycle operation
7
Notes:
= VEE to Vcc
3
4
1. Applies to input terminals FCS. SHL. 01. M. and CL.
2.
3.
4.
5.
Applies to output terminal of ~O.
Applies to the terminals NC. and the input terminals FCS. SHL. 01. M. and CL.
Applies to Vl. V2. V6. and Va. No wire should be connected to Xl-Xao.
Resistance value between terminal X (one of Xl to Xso) and terminal V (one of Vl. V2. Vs.
and Va) when load current is applied to one of terminals Xl to Xso. This value is specified
under the following conditions:
Vec -VEE =26V
v1• Ve=Vec- 1/ 10 (Vee-VEE)
V2 • V5=VEE +1/10 (Vee-VEE)
~_=-==_-o:~
The following is a description of the range of
power supply voltage for liquid crystal display drives. Apply positive voltage to VI and
Va. and negative voltage to V2 and V6. within
Terminal X
(Xl-X80)
the .0. V range. This range allows stable
impedance on ,driver output (RoN). Notiee
that .0. V depends on power supply voltage
Vee-VEE.
HITACHI
334
Hitachi America, Ltd.· Hitachi Plaza- 2000 Sierra Point Pkwy.· Brisbane. CA 94005~1819· (415) 589-8300
HD61105, HD61105A
__
~
_________________ Vcc
n--------
I
AV
v,
~----. Va
4.5 ----------------------------
u:----------- ~
.~----------VI
2 ------- -----
V5
VEE
Correlation between Driver Output
Waveform and Power Supply Voltages for
Liquid Crystal Display Drive
Correlation between Power Supply Voltage
Vee-VEE and l:;. V
6. The currents flowing through the GND terminal. Specified when display data is transferred
under following conditions:
CL frequency
fCL = 14kHz (data transfer rate)
M frequency
fM == 35 Hz (frame frequency/2) 1/200
Display duty ratio
VIH
Vec. VIL
GND
No load on outputs
7. The currents flowing through the VEE terminal in the conditions of note 6. No line should be
connected to the V terminal.
=
=
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
335
HD61105~
HD61105A
AC Characterlstlcs (Vee
= 6 V ± 10%, GND = 0 V, T. = -
20 to + 76'C)
CL
(FCS=GNO)
(shift clock)
CL
(FCS= Vcd
(shift clock)
tOH
01
input data
too
O. 7Vcc
DO
output data
O. 3Vcc
tOHW
Item
Symbol
Min
Clock low level width (FCS = GND)
twLl
5.0
pS
twHl
125
ns
twL2
125
ns
twH2
5.0
pS
Data setup time
tos
100
ns
Data hold time
tOH
100
ns
Output delay time
too
Output hold time
toHW
Clock rise time
t,-
30
ns
Clock fall time
tf
30
ns
= GND)
Clock low level width (FCS = Vee)
Clock high level width (FCS = Vee!
Clock high level width (FCS
Note:
Typ
Max
3.0
100
Unit
Note
ps
ns
1. The following load circuits are connected for specification:
*
Output terminal .....- - - ,
30pF (including jig capacitance)
HITACHI
336
Hitachi America; Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005"1819· (415) 589-8300
HD61105, HD61105A
Terminal Configuration
Input Terminal
Applicable Terminals: Dr, CL, SHL, FCS, M
Vee
PMOS
NMOS
Output Terminal
Applicable Terminal: DO
Vee
PMOS
o--------t
NMOS
~
r
Output Terminal
Applicable Terminals: Xl-XSO
..c
PMOS
PMOS
V,
Ve
Vee
...r::-
NMOS
NMOS
Vs
V2
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
337
HD61105, HD61105A
Block Diagram
V, V2 V5 Va
80 output terminals
--------------Vee
1
GN 0
2
3
Uquid crystal
display driver
circuit
I-78
79
80
VEE
---------------Level shifter
---------------~
_~rrt'
oI
SH L
2
3
tnifirectlonal
shift register
SR
.---
78
Logic
----------------
,Logic
FCS
'---
HITACHI
338
M
~ ~
79 80
T
t
CL
l7J
.
shifter
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
o
HD61105, HD61105A
Block Functions
Bidirectional Shift Register
Liquid Crystal Display Driver Circuit
This is a 80-bit bidirectional register. The data
from the Dl terminal is shifted by the shift
clock CL. The output terminal DO outputs the
last shifted data. In case of serial cascade
connection, terminal DO functions as the data
input to the next LSI. Terminal SHL selects
the data shift direction (table i), and the
terminal FCS selects the shift clock phase
(table 2).
The combination of the data from the shift
register with M signal allows one of the four
liquid crystal display driver levels Vi, V2, V5,
and V6 to be transferred to the output terminals (table 3).
Table 1 SHL Truth Table
(Positive logic)
SHL
Data Shift Direction
DI
-->
SR1
o
DI
-->
SR80
-->
SR2
-->
-->
SR79
SR3 ........................... SR79
-->
SR78
-->
........................ SR2
SR80
-->
DO
SR1
-->
DO
-->
Table 2 FCS Truth Table
FCS
Shift Clock Phase
o
Shifted at the falling edge of Cl
Shifted at the rising edge of Cl
Table 3 M Truth Table
(Positive logic)
Data from tha Shift Ragister
M
output leval
o
o
V5
o
v,
o
Ve
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
339
HD61105, HD61105A
HD61105 Terminal Functions
Tarmir.al
Number'vf
Nama
Terminals
ConnllCteci
to
Functions
Power
supply
Vee - GND: Power supply for internal logic
Vee - VEE: Power supply for LCD drive circuit
Liquid
crystal
drive
level power
supply
Power supply for liquid crystal drive
V" V2: selection level
Vs, Va: non-selection level
FCS
Vee or GND
Selects shift clock phase.
FCS = Vee Shift register operates at the rise of CL
FCS = GND Shift register operates at the fall of CL
M
Controller
Signal to convert LCD driver signal into AC
CL
Controller
Shift clock
FCS = Vee Shift register operates at the rise of CL
FCS = GND Shift register operates at the fall of CL
DI
Controller or
terminal DO of
HD6ll05
Shift register data input
In case of cascade connection, the terminal DI is connected
to the terminal DO of the preceding LSI.
Open or
terminal DI of
HD6ll05
Shift register data output
In case of cascade connection, the terminal DO is connected to the terminal DI of the next LSI.
Vee or GND
Selects shift direction of bidirectional shift register.
I/O
Vee
GND
VEE
4
a
DO
SHl
X,-Xso
80
a
Liquid
crystal
display
SHl
Shift Direction
Common Scannin{,
Direction
Vee
DI-+ SRl -+ SR2 -+ SR80
X, -+ Xso
GND
DI-+ SR80 -+ SR79 -+ SRl
Xso -+ X,
liquid crystal display driver output
Outputs one of the four liquid crystal display driver levels
V" V2, V5, and Va with the combination of the data from
the shift register and M signal.
M~
Data
~
Output
level
Data 1 : Selection level
Data 0: Non-selection level
When SHl is Vee, X, corresponds to COMl and Xso corresponds to COM80.
When SHL is GND, Xso corresponds to COMl and X,
corresponds to COM80.
NC
7
Open
Unused.
No line should be connected.
HITACHI
340
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61105, HD61105A
Outline of HD61105 System Configuration
When display duty ratio of LCD is 1/80
LCD
Controller
COM1
80
COM80
Controller
LCD
80
COM1
Upper
COM80
80
-----------------COM1
Lower
COM80
When display duty ratio of LCD is 1/100
Controller
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
341
HD61105, HD61105A
When display duty ratio of LCD is 1/160
Controller - .
LCD
HD61105
(1 )
I
I
80
HD61105
I
80
(2)
I
I
•
I
COM1
COM160
When display duty ratio of LCD is 1/160
Controller
LCD
80
COM1
Upper
80
COM160
-----------------
80
COM1
Lower
80
COM160
HIt"ACHI
342
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415)589-8300
HD61105, HD61105A
When display duty ratio of LCD is 1/200
Controller
LCD
1---'8r--0----<~ COM1
80
40
COM200
Controller
LCD
80
COM1
80
Upper
40
COM200
40
------------------
COM1
80
Lower
80
COM200
HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
343
HD61105, HD61105A
Example of Connection
1/200 duty ratio
Vee
+5V
Rl
Rl
>
~
tl
R3
v,j
R3
V6
+'" ~'"
R3
V3
-A,/\, v
R2
R3
'"
Rl
>Rl
+
Vee
V1
V6
Vs
V2
Vee
GNO
,- M
CL
,....
V4
r-
-"v v
R3
~
10
-co
0
Vee
c
:I:
01
LCD
Xeo
SHL
~
W
COMl
I
I
I
I
I
I
I
I
I
FCSr}
V5
J>.A
R3
COM SO
V2
Vee
V1
V6
Vee
r1c'-
V5
IIGNO
OV
I
I
I
I
I
I
I
I
I
;=
0
r- OO
. ../\,
-20V
X1
V2
Vee
GNO
M
CL
X1
N
ci
10
0
:I:
r- OO
R3 = 150
IIIII~
Open
Vee
V1
VB
Vs
V2
Vee
GNO
M
CL
01
Xeo
COM160
Vee
c
~ 01
I
I
I
I
I
I
I
I
I
I
1
I
~
-co
COMSl
I
I
I
I
SHL
FCS
W
I1
COM161
,.-
I
I
I
COM200
X1
I
I
I
,M
X40
0
~1
-
Xeo
:I:
SHL
~
I
I
I
10
0
Vee
co
c
DO
W
FCSrJr
MController
CL
01
Note:
1. The values of R1 and R2 vary with the LCD panel used.
When bias factor is 1/15, the values of R1 and R2 should satisfy
R1
4R1+R2
1
15
For example, R1 = 3 KO, R2 = 33 KO
Figure 1
Example of Connection (SHL = Vee. FCS = GND)
HITACHI
344
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD61105, HD61105A
~~~ r!
'I'll
I
,
,,
I
'i~
I
,IEI'::.
I.,
I
II
f ,f F F ,~~
" , '"
I
I
I
I
I I
I
,, I:
I
1
,
I'
~~ ~
I
"
~~ ~~'
'I
1
1
II
I1 I1
1
1
1
I
I1
I'
,
,
I
I
"' I
,
I'
~
r'
"I
I
I,
'i~
I~
'I,
"
~~~ ~ ~ ~ ~ ~ ~ ,~~ ~
:1')1
I
~~
I
.,1
EI
.. I
.::1
' I
I
"
,
:
I
I :
,
I
I
I
,
II
I
:i~
I
1
II
I
I
r;1
-
,'-_ _ _--.J/
,
,
_:!!
Xo
;1
c;:;
gOO
8
xo----x~
!L ·ON)
;1
N
. 0
co
co
-:!! "':!!
2~
Xo xo ____ x~
;::
CD
!:!.!:!.
~
,'-_ _- - - - - - - . J /
90~~9aH
Figure 2
~",I ~",I ~I
.. I
;1;1
5
"':!!
II
I
1
1
d
I
I1
I
::~:
:
J
1~:
f.l
:
,=
.
~
"
,
I
~
~
N
I
,,~ ~ ~ 4' ,
I
I
8
I
"~ ~~~
:I II ;I
I
1
!:!.!:!.
()
90~ ~9aH
::>:>'
co:;j
"'-8
",ox:!! x:!!
~N
0
0
o _____ x~
,'--_ _ _ _ _ _
- ____/ ,
(z ·ON)
~ ~
... _
!:!.!:!.
()
- /
(£ ·ON) 90~ ~9aH
Waveform Ezample
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
345
HD61105, HD61105A
+5V~T---r-------~~cc~~__----~·lvcc
R3
V,
V6
Vs
V2
VEE
V,
V"
R1
R3
.1\1'
R1
R3
R2
R3
-AIV'
R1
R3
V6
GNO
,.-.. M
,.- CL
01
r-- 00
V3
-
V4
x,
;:::
0
LCO
~
III
~
0
J:
,,
,
L. COM1
0
;0
SO
~
--.l.
FCS -;J,.
I
I
I
I
SHL
Vs
I
I
I
Upper
I
I
R1
R3 V2
"vv-
Vee
V,
V6
Vs
V2
VEE
VEE
-12 V
h~,,-
f-f-- GNO
f-- M
f-- CL
L. 01
r-- 00
GNO
OV
COMSO
COMS1
X,
I
I
N
0
~
III
0
;0
0
J:
I
X20
COM 100
X2'
COM1
I
I
I
I
I
---------------
I
I
I
I
I
I
XSO
SHL
I
COM60
COM61
~~r
Lower
I
I
FCS~
I
I
I
I
I
I
R3
Vee
V,
V6
Vs
f-- V2
I- VEE
= 15Q
f-- GNO
f-- M
f-- CL
L., 01
Open
00
X,
r---
r-
COM100
I
I
I
M
0
~
III
~
;0
0
I
I
X40
X4'
I
I
I
I
Xeo
J:
SHL
Vee
l-J
FCS'1
M
Controller
CL
01
Note:
Figure 3
1. The values of R1 and R2 vary with the LCD panel used.
When bias factor is 1/11, the values of R1 and R2 should satisfy
R1
1
.
4R1+R2 11
For example, R1 = 3 KO, R2 = 21 KO
Example of Connection 1 (SHL
= Vee. FCS
=
GND)
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61105, HD61105A
Figure 4
Waveform Example
HITACHI
1-litachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
.
-
_
•... ....
~-
... -
.. - _....
_
..
--~.---
347
HD61105, HD61105A
+5V 0
, ,
Vee
R3
~
-
Vl
Va
V5
V2
Vl
R3
~-A/'. V'
R2$
R3
~-A. vV'
Rl
R3
.,--A/''\r
Rl'
R3
V3
VEE
GNO
M
CL
,.
r-
-
V4
01
00
-
rr
I
I
I
I
I
I
I
I
I
I
I
I
~
ci
~
'"~
a;
0
:r
I
I
s:,~
--
FCS
V5
V2
V'
-12V
xBO
.. Vee
:::J.~JV'vV'
R3
V,
a
Rl
>
Rl.
,
VEE
Contrast
GNO
Vee
Vl
Va
V5
V2
VEE
GNO
M
CL
-----
01
00
I
I
0
:r
OV
I
I
COM 100
Xao
COM1
--------------
I
I
I
I
I
'"
~
Upper
X al
~
a;
I
I
I
I
I
I
I
I
I
I
I
I
COM SO
COMSl
XBOI
N
ci
LCO
COMl
I
I
I
I
I
I
Xl
Lower
COM60
COM61
Vee
SHL~
FCS
I
I
I
I
I
T17
I
I
I
Vee
Vl
V6
V5
--ti. V2
R3
........--
= 150
Open
----
XBO f - -
r-
COM100
I
I
I
I
M
ci
VEE
GNO
M
CL
~
01
00
:r
I
X4l
X40
I
'"~
a;
0
I
I
I
;~~'
FCS
T17
Mr--Controller
CL ' - - -
01
Note:
1. The values of R1 and R2 vary with the LCD panel used.
When bias factor is 1/11, the values of R1 and R2 should satisfy
R1
1
4R1 +R2 11
For example, R1 = 3 KO, R2 = 21 KO
Figure 5
Example of Connection 2 (SHL = GND, FCS = Vee)
HITACHI
348
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61105, HD61105A
"
E
£
I
I
I
I
I
I
I
I
I
I
I
I
I
~~~ 1~~ ~ ~~L 1~ ~ ~t
I
I
, '~~ ~ ~ , " ",
""
I
,
1('1')1.
'!~
I
•
IMI
I
I
I
t
I
•
I
I
I
I
I
I
I
I
I
I f '
,
I
I
I
t
•
I
I
I
I
I
I
I
I
I
I
I:
:
I
I
I
I
I
I:
I
I
I
I
I
I
I
I
I
I ,
I
'!~
I
I
I
•
I
I
I
I
I
I
I
:
I
I
I
I
I
I
I
I
:
~I:~I ~",I~-:f!' ~I~
I
:>
;5'
§
;5'
0
~
d
,'-----...-;/
JallOJluo:>
N
(J'1
~
~
0>
::J:
s=
I:j
0
V1L V2 L V3L V4 L
~
»
Y1 Y2
Y80
;"
V1RV2RV3RV4R
~
3
CD
a
::I.
n
p>
~
Li~uid ~stal display
M
dnver circuit
::J:
s=
n
~
-0
.
Ii>
N
",
CL1
=E
-,
""
0
0
0
en
~.
iil
Vcc
GND
VEE
:I
~
a n
-0
0
-0
~ 3;;
•
CD
::I.
(/)
cr
",
:::>
II
:~ ,H!.,
~~: : ; :1 1
~~
1
H
2
1.2
I
»
.,..
CD
E
0
0
'i:.
~
CD
~
~
(J'1
00
'f'
00
c.>
0
0
I
rl2'
I
20
>(
_CD
(")
I
s.-,
1
. __.I
"
FCS
- Test input
I
I
I
I
I
... ------------------------ Control circuit
-CAR
a:
t1
en
.....
~
o
o
HD61200
Block Function
Liquid Crystal Display Driver Circuit
Selector
The combination of the data from the latch circuit 2
and M signal causes one of the 4 liquid crystal
driver levels, VI, V2, V3, and V4 to be output.
The selector decodes output signals from the
counter and generates latch clock, 1 to ,20. When
the LSI is not active, ,1~20 are not generated, so
the data at latch circuit 1 is stored even if input data
(DL, DR) changes.
80-bit Latch Circuit 2
The data from latch circuit 1 is latched at the fall of
CL1 and output to liquid crystal display driver
circuit.
SIP
Serial/parallel conversion circuit which converts 1bit data into 4-bit data. When SHL is low level,
data from DL is converted into 4-bit data and
transferred to the latch circuit 1. In this case, don't
connect any lines to terminal DR.
When SHL is high level, input data from terminal
DR without connecting any lines to terminal DL.
80-bit Latch Circuit 1
The 4-bit data is latched at ,1-+20 and output to
latch circuit 2. When SHL is low level, the data
from DL are latched in order of 1-+2-+3 ... -+80 of
each latch. When SHL is high level, they are
latched in a reverse order (80-+79-+78 ... -+1).
Control Circuit
Controls operation: When E-F/F (enable F/F)
indicates 1, SIP conversion is started by inputting
low level to E. After 80-bit data has been all
converted, CAR output turns into low level and EF/F is reset to 0, and consequently the conversion
stops. E-F/F is RS flip-flop circuit which gives
priority to SET over RESET and is set at high
level of CLI.
The counter consists of 7 bits, and the output
signals upper 5 bits are transferred to the selector.
CAR signal turns into high level at the rise of
CLl. The number of bits that can be S/P-converted
can be increased by connecting CAR terminal with
E terminal of the next HD61200.
HITACHI
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357
HD61200
Terminal Functions Description
Terminal
Name
Terminals
I/O
Connected
to
Functions
1
1
1
Power
supply
Vee - GND: Power supply for intemallogic
8
Power
supply
Power supply for liquid crystal drive.
Vee - VEE: Power supply for LCD drive circuit
V1l (V1R). V2l (V2 R): Selection level
V3l (V3R), V4L (V4R): Non-selection level
Power supplies connected with V1L and V1 R (V2l & V2R,
V3l & V3R, V4L & V4R) should have the same voltages.
Y1-Y80
80
o
LCD
liquid crystal driver outputs.
Selects one of the 4 levels, V1, V2 V3, and V4.
Relation among output level, M, and display data (D) is as
follows:
M
J
0/
D~
~~Jtut
M
Controller
1:'1.1:'3.1:'~IY~
Switch signal to convert liquid crystal drive waveform into
AC.
CL1
Controller
Synchronous signal (a counter is reset at high level).
Latch clock of display data (falling edge triggered).
Synchronized with the fall of CL1. liquid crystal driver
signals corresponding to the display data are output.
Cl2
Controller
Shift clock of display data (D).
Falling edge triggered.
DL,DR
SHL
2
Controller
Vee or GND
Input of serial display data (D).
(D)
liquid Crystal
Driver Output
1 (High level)
Selection level
On
o (low level)
Non-selection level
Off
liquid Crystal
Display
Selects the shift direction of serial data.
When the serial data (D) is input in order of 01-+ ... -+080,
the relations between the data (D) and output Yare as
follows:
SHL
Y1
Y2
Y3
Y80
low
01
D2
D3
080
High
080
079
078
01
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HD61200
Terminal Functions Description (cont)
Terminal Number of
Name
Terminals 1/0
Connected
to
Functions
SHL
Vccor GND
I
When SHL is low, data is input from the DL terminal. No
lines should be connected to the DR terminal.
(cont)
When SHL is high, the relation between DL and DR
reverses.
CAR
FCS
o
GND or the
Controls the SIP conversion.
t~~inal CAR
~cis~200
The operation stops on high level, and the SIP conversion
starts on low level.
Input terminal Used for cascade connection with the HD61200 to
increase the number of bits that can be SIP converted.
HD61200
E of the
GND
Input terminal for test.
Connect to GND.
. Operation of the HD61200
The following describes an LCD panel with 64 x 240 dots on which characters are displayed with 1/64 duty
cycle dynamic drive. Figure 1 is an example of liquid crystal display and connection to HD61200s. Figure 2
is a time chart ofHD61200 I/O signals.
HITACHI
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359
HD61200
COM 1
COM2
COM3
-
--
1,
1
1,
2
2,
1
2,
2
3,
1
3,
2
-
I
I
I
I
I
I
1,
80
1,
81
1,
82
1,
160
1,
161
2,
80
2,
81
2,
82
2,
160
2,
161
----
3,
80
---- I
I
I
I
I
I
I
I
I
I
I
I
----- I
1,
240
:---
-----
2,
240
:--3,
240
~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD Panel (64 x 240 Dots)
COM63
COM64
-
-
I
I
I
63,
1
64,
1
I
I
I
63,
2
64,
2
I
I
I
I
I
I
I
I
I
I
I
I
64,
64,
80
81
Y80
HD61200 (No.1)
:i~...Ja:I~
M
-------
64,
160
Y1
64,
240
-----
Y2
Y80
Y1
HD61200 (No.2)
~~
240
~
:i ~...J a:1~
Y80
HD61200 (No.3)
~~
:i~...Ja:I~
1 11
W
1 11
W
11
0
0
00
IWCJ)U.::::iOOooo
111
63,
-----
Y2
~~
~
-
64,
82
----Y1
-
63,
80
-
I
I
I
IWCJ)U.::::iOOooo
a.
IWCJ)U.::::iOOooo
a.
ww
a. a.
CL 1
-
Cl2 "
DATE "
Figure 1 LCD Driver with 64 x 240 Dots
Cascade three HD61200s. Input data to the DL tenninal of No. I, No.2, and No.3. Connect E of No. 1 to
GND. Don't connect any lines to CAR of No.3. Connect common signal tenninals (COMI-COM64) to
XI-X64 of common driver HD61203. (m, n) of LCD panel is the address corresponding to each dot
HITACHI
360
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
::J:
s=
""2:
§"
M
CL1
Cl2 L..t
~
n'
~
-
::J:
""2:
I'!!j
-0
;q.
.
ii>
N
=
...
I»
0
0
0
I
.
Y1-Y80
0
a
-0
:::t
IJ::J
:::!.
(f)
0"
I»
~
!"
C")
»
<0
~
0
0
'i:.
~
<0
~
~
(TO
co
c::>
~
ii"
s·
CL 1
C12
.s1
~
I
WIII/IMM--- ~ -----lIIIU1It
I
----- ~ --- ~ --- ~ -'----~
~
I
*
I
' - - - - - - - - - 1 Frame
III
...."'I
~.
r
=r
M
Cl1
x::::= ---
I
(JQ
C":l
"---- ---
.fUUl-----.IWUl/UU1 -----.I\JlIlIlMM ---
DL_----- ~
Y1-Y80
I
I
I
4
i
I
I
I
I
I
I
---v
Timing
chart
for
vertical
direction
-------:.1------ _----------------------------Jr
Y1(No.1) ~
Y2(No.1) ~
Y80(No.1)~
Y80(No.3)
~
:
~
I
•
60,1 61.1 62.1 83,1 ".1
60,2 61.
1.
~
.
63.
64.2
::x:x:x:::::x=x
------ ::x:x:x:::::x=x
::x:x:x:::::x=x
::x:x:x:::::x=x
I
I
______
I
I
Timing chart for example of connection in figure 1.
DL input (m. n) is the data that corresponds to each address (m. n) of LCD panel.
w
~
II
I
I
I
I
Timing
chart
for
liquid
crystal
display
driver
output
8m
~
~
o
o
HD61200
Application Example
/r---------
Yl-Y80
HD61200 No. 1
..J
l1 -
III:
N
,wiaLL.2dddlS~
,J,.,J,.,J,.
t
DATE (1)
M
240 dots
"-
Yl-Y80
Y1-Y80
HD61200 No.2
HD61200 No.3
l1 ..J..J
- N 11:<
III:
IW Ch LL. 2 0 0 is C 0
I,J,.,J,.
,w~~2dadlSl~
..J
:E:
,J,.,J,.
I
I
J
Cll
Cl2
DATE (2)
0
1'9 1'l12 0
IW ..J
iaLL.
~ ..J
!
11:111:
doCC~
HD61200 No.4
Y80-Y1
981'
1
l12 0
:i ~ is 11:111:
ChLL.
0
c~
IW ~
0
0
91'
l12 :i
~ is 11:111:
ChLL.
00
c~
IW ~
HD61200 No.5
Y80-Y1
HD61200 No.6
Y80-Y1
j
Figure 3 Example of 128 x 240 Dot Liquid Crystal Display (1/64 duty cycle)
The liquid crystal panel is divided into upper and lower parts. These two parts are driven separately.
HD61200s No.1 to No.3 drive the upper half. Serial data, which are input from the DATA (1) terminal,
appear at Y 1 -+ Y2 -+ -- Y80 terminal of No. I, then at Y 1 -+ Y2 -+ -- Y80 of No.2 and then at Y 1-+ Y2 -+
-- Y80 of No.3 in the order in which they were input (in the case of SHL = low). HD61200s No.4 to No.
6 drive the lower half. Serial data, which are input from DATA (2) terminal, appear at Y80 -+ Y79 -+ -- Y 1
of No.4, then at Y80 -+ Y79 -+ -- Y 1 of No. 5 and then Y80 -+ Y79 -+ -- Y 1 of No. 6 in the order in which
they were input (in the case of SHL = high).
As shown in this example, a PC board for a display divided into upper and lower half can be easily designed
by using the SHL terminal effectively.
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane,
cA 94005-1819' (415) 589-8300
HD61202------------(Dot Matrix Liquid Crystal Graphic
Display Column Driver)
Description
Features
HD61202 is a column (segment) driver for dot
matrix liquid crystal graphic display systems. It
stores the display data transferred from a 8-bit
micro controller in the internal display RAM and
generates dot matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to the
on/off state of a dot of a liquid crystal display to
provide more flexible than character display.
As it is internally equipped with 64 output drivers
for display, it is available for liquid crystal graphic
display with many dots.
The HD61202, which is produced in the CMOS
process, can complete portable battery drive
equipment in combination with a CMOS microcontroller, utilizing the liquid crystal display's low
power dissipation.
Moreover it can facilitate dot matrix liquid crystal
graphic display system configuration in
combination with the row (common) driver
HD61203.
Dot matrix liquid crystal graphic display
column driver incorporating display RAM
RAM data direct display by internal display
RAM
RAM bit data 1: On
RAM bit data 1: Off
Internal display RAM address counter preset,
increment
Display RAM capacity: 512 bytes (4096 bits)
8-bit parallel interface
Intemalliquid crystal display driver circuit 64
Display duty cycle:
Drives liquid crystal panels with 1/32-1/64
duty cycle multiplexing
Wide range of instruction function:
Display Data Read/Write, Display On/Off, Set
Address, Set Display Start Line, Read Status
Lower power dissipation: during display 2 mW
max
Power supply: Vee: 5 V ± 10%
Liquid crystal display driving voltage: 8 V to
17.0 V
CMOS process
loo-pin flat plastic package (FP-loo)
I
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
363
HD61202·
Absolute Maximum Ratings
Note
item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
2
VEEl
VEE2
Vee -19.0 to Vee + 0.3
V
3
VTl
VEE - 0.3 to Vee + 0.3
V
4
2,5
Terminal voltage (1)
Terminla voltage (2)
VT2
-0.3 to Vee + 0.3
V
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +125
°C
Notes:
1.
2.
3.
4.
5.
lSls may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended operation
conditions.
Using them beyond these conditions may cause malfunction and poor reliability.
All voltage values are referenced to GND ,. 0 V.
Apply the same supply voltage to VEE1 and VEE2.
Applies to V1 l, V2l, VSl, V4l, V1 R, V2R, V3R, and V4R.
Maintain
Vee~V1l- V1R~V3l .. V3R~V4l- V4R~V2l- V2R~ VEE
Applies to M, FRM, Cl, RST, ADC, ,1, ,2, CS1, CS2. CS3, E, RI'N, Oil, and DBa-DB7.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61202
Pin Arrangement
ADe
M
vee
V4R
V3R
V2R
V1R
VEE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
(Top view)
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
365
HD61202
Electrical Characteristics
=
'(GND
O,V, Vee
+75°C)
=4.5 to 5•.5 V, Vee -
VEE
=8 to 17.0 V, Ts.:: -20 to
Limit
Item
Symbol Min
Input high voltage
VIHC
VIHT
Vile
Input low voltage
Max
Unit
0.7 x Vee
Vee
V
1
2.0
Vee
V
2
0
0.3 x Vee
V
0.8
V
2
V
Typ
V/lT
0
Output high voltage
VQi
2.4
Output low voltage
Va.
Input leakage current
IlL
-1.0
+1.0
Three-state (off)
input current
!rSL
-5.0
+5.0
Liquid crystal supply
leakage current
ItSL
-2.0
+2.0
Driver on resistance
~
7.5
Dissipation current
Icc (1)
Icc (2)
500
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
0.4
100
Test Condition
Note
V
lett - -205 ""
lot. .1.6 mA
3
""
Vin - GND-Vee
Vin • GND-Voc:
4
5
Vin. VEE -Vee
6
kn
Vee-VEE-15 V
±ILOAO - 0.1 mA
8
""""
During display
7
During aoc:ess
access cycle - 1 MHz
7
""
""
3
Applies to M, FRM, Cl, RST, .1, and ~.
Applies to CS1, CS2, CS3, E, RIW, DII, and D80-087.
Applies to D80-087.
Applies to terminals except for D80-087.
Applies to D80-087 at high impedance.
Applies to V1 l-V4L and V1 R-V4R.
Specified when liquid crystal display is in 1/64 duty cycle mode.
Operation frequency
fCLl( - 250 kHz (.1 and ~ frequency)
Frame frequency
fM - 70 Hz (FRM frequency)
Specified in the state of
Output terminal: not loaded
Input level:
Vii - Vee (V)
.
VIL·- GND (V)
Measured at Vee terminal
Resistance between terminal Yand terminal V (one of V11, V1 R, V2l, V2R, V3l, V3R, V41,
and V4R) when load current flows through one of the terminals Y1 to Y64. This value is
specified under the following condition:
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HD61202
\be- VEE- 15.5 V
V1l - V1R. V3l - V3R- Vee- 217 (Vee- VEE)
~l - V2R • V4L - V4~ Vee + 218 (Vec - VEE)
RON
--------<0
-----0
--------<0
t---o
~--JVV'\r-----+
Terminal Y
(Y1-Y64)
The following is a description of the range of power supply voltage for liquid crystal display drive. Apply
positive voltage to VIL =VIR and V3L =V3R and negative voltage to V2L =V2R and V4L =V4R
within the ~V range. This range allows stable impedance on driver output (RON). Notice that ~V depends
on power supply voltage Vee - VEE'
.....,r---------Vee
-------- V1 (V1 l • V1 R)
flV
Range of Power Supply
Voltage for liquid Crystal
Display Drive
---- V3 (Val· V3R )
~5.0
~
~
3· ----------
------------ V4 (V4l - V4R)
------.------- V2 (V2l • V2R)
VEE
(V)
Correlation between Driver
Output Waveform and Power
Supply V'?ltages for Liquid
Crystal Display Drive
Correlation between Power
Supply Voltage Vee- VEE and flV
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HD61202
Terminal Configuration
Input Terminal
Applicable terminals :
M, FRM, Cl, RST, ~ 1, ~ 2, CS1, CS2, CS3,
E, RIW, OIl, AOC
Vee
PMOS
NMOS
InputlOutput Terminal
Applicable terminals: OBa-OB7
Vee
,------- ---1
I
:--Enable
:I PMOS
I
fr-I Data
I
:
I
' -_ _ _ _ _ _--':NMOS
I
I
:
I
I
L _________ ! (Output circuit)
[three state))
Output Terminal
..c-
Applicable Terminals:
Y1-Y64
PMOS
V1l,V1R
Vee
..c-
PMOS
V3l, V3R
Vee
..c-
NMOS
V4l, V4R
VEE
..c-
NMOS
V2l,V2R
VEE
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HD61202
Interface AC Characteristics
MPU Interface
(GND
=0
V. Vee
= 4.5
to 5.5 V. Ta
= -20
to +75°C)
Item
Symbol
Min
Unit
Note
E cycle time
tCYC
1000
ns
1.2
E high level width
PWEH
450
ns
1.2
E low level width
PWEL
450
ns
1.2
E rise time
tr
25
ns
1,2
25
E fall time
tf
Address setup time
tAS
Max
Typ
ns
1,2
140
ns
1,2
Address hold time
tAH
10
ns
1,2
Data setup time
tosw
200
ns
1
Data delay time·
tooR
ns
2,3
Data hold time (Write)
tOHw
10
ns
1
Data hold time (Read)
tDHR
20
ns
2
320
Notes: 1.
tCYC
E
PWEH
PWEL
tl
tAH
tr
RIW
2.0V
CS1-CS3
2.0V
DII
0.8V
tosw
DBo-DB7
2.0V
0.8 V
Figure 1 CPU Write Timing
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369
HD61202
Notes:
2.
~----------tc~~~========~
\1+---- PWEl--~---PWEH-
E
RIW
0.8 V
CS1-CS3
2.0 V
011
0.8 V
OBO-DB7
0.4 V
Figure 2
3.
CPU Read Timing
OBO-DB7: load circuit
RL .. 2.4kn
Test
point
01
A .. 11 kn
RL
C .. 130 pF (including jig capacitance)
1
C
A
Diodes 01-04 are all 1S2074
02
03
04
®.
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HD61202
Clock Timing
(GND
=0
V, Vee
= 4.5 to
=-20 to +75°C)
5.5 V, Ta
Limit
Max
Unit
Test Condition
20
I1s
Fig. 3
625
ns
Fig. 3
twt+2
625
ns
Fig. 3
Item
Symbol
Min
+1, t2 cycle time
tcyc
2.5
+1 low level width
tWL+1
~
low level width
Typ
tWJ-t+1
1875
ns
Fig. 3
+2 high level width
tWJ-t+2
1875
ns
Fig. 3
.1--+2 phase difference
.1 high level width
t012
625
ns
Fig. 3
t2-+1 phase difference
t021
625
ns
Fig. 3
.1, +2 rise time
tr
150
ns
Fig. 3
.1, t2 fall time
tf
150
ns
Fig. 3
91
92
tWHa2
Figure 3
External Clock Waveform
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371
HD61202
. Display Control Timing
(GND = OV, Vee = 4.5 to 5.5 V. Ta = -20 to +75 °C)
Limit
Max
Unit
Te.t Condition
-2
+2
J's
Fig. 4
toM
-2
+2
Fig. 4
CL low level width
tWLCL
35
J1S
J's
CL high level width
tWHCL
35
J's
Fig. 4
Item
Symbol
Min
FRM delay time
toFRM
Mdelaytime
CL
Typ
Fig. 4
O. 7Vce " ..- - - . . I I
O.3VeC
FRM
M
Figure 4
Display Control Signal Waveform
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HD61202
Block Diagram
...J...J...J...J
....
»»
a:
.... a: a: a:
»»
.... NC')
>->->- --------------
NC')~
'---f ....
1NI C') I Li~uid ~rys~al
(2;
display
dnver CircUit
M
~
N
Display date latch
.... INIC')I
NC')~
CD
f31(2;1-f31~t-
~
CD
r---
...
$
::3
8
~::3
III
"0
11
"0
.J:l
CD
}'
0
~
en
!
"0
11
0
N
-
L
en
VEE2,- f--
til
til
~
i-
>X
8
.t:
1ii
III ~
l!!
Vee,- f-GND - f-VEE1 - f--
...
::::i:
«
a:
c
ADC
r---
00
00
--- -----
------
1----1
1
Instruction
1
1
register
_I
el
C I1
Input
1
register
1
1111
tl
$1
~
t:: ...
-
liiU;
,---
III
Q)
}'.~
g.Q)
tII--
c=
Co
:r T
---------Output
register
.E.
•
i
1/0 buffer
1
1____________
1
C') ~-
-
-~00
~
flag
oo~
oot
>.
-!:a fo.f.- c
.- C
,
8
8
CL
FRM
:
I------.,..-----.J
......
RST
~
,,1
~
,,2
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373
HD61202
Terminal Functions
Terminal Number of
Connected
Function.
Name
Terminal. 1/0 to
t'.
Vcc
GND
2
Power
supply
Power\ supply for internal logic.
Recommended voRage is:
GND.OV
Vcc· 5V ±10%
VEE1
VEE2
2
Power
supply
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is Vcc - VEE. 8 to 17.0
V. Connect the same power supply to VEE1 and VEE2. VEE1
and VEE2 are not connected each other in the LSI.
V1L, V1R
V2L. V2R
)l3L. V3R
V4L. V4R
8
Power
supply
Power supply for liquid crystal display drive.
Apply the voRage specified depending on liquid crystals
within the limit of VEE through Vee.
V1L (V1R). V2L (V2R): Selection level
V3L (V3R). V4L (V4R): Non-selection level
Power supplies connected with V1 L and V1 R (V2L & V2R.
V3L & V3R. V4L & V4R) should have the same voltages.
3
MPU
Chip selection.
Data can be input or output when the terminals are in the
following conditions:
Terminal Name
CS3
Condition
E
MPU
L
Enable.
At. wrlte(RIW • Low):
At. read(RIW • High):
MPU
011
LfJU
L
H
Data of DBO to DB7 is latched at
the fall of E.
Data appears at DBO to DB7 while
E is at high level.
Readlwrlte.
RIW - High:
Data appears at DBO to DB7 and can be
read by the CPU.
When E • high. 051. CS2 • low and CS3 high.
RIW • Low:
DBO to DB7 can accept at fall of E when
051. CS2 • low and CS3 • high.
Data/instruction.
011 • High:
Indicates that the data of DBO to DB7 is
display data.
011 • Low:
Indicates that the data of DBO to DB7 is
display control data.
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HD61202
Terminal Functions (cont)
Terminal Number of
Connected
Name
Terminals 1/0 to
Functions
MX:,
VccJGND
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ACe. High:
ACe. Low:
DB1-DB7
8
M
Y1: $0, Y64: $63
Y64: $0, Y1: $63
1/0
MPU
Data bus, three-state 110 common terminal.
I
HD61203
Switch signal to convert liquid crystal drive waveform into
AC.
HD61203
Display synchronous signal (frame signal).
FfIM
Presets the 6-bit display line counter and synchronizes the
common signal with the frame timing when the FRM signal
becomes high.
CL
2
• 1,.2
HD61203
Synchronous signal to latch display data. The rising CL
signal increments the display output address counter and
latches the display data•
HD61203
2-phase clock signal for internal operation.
The.1 and.2 clocks are used to preform operations (ItO of
display data and execution of instructions) other than
display.
Y1-Y64
64
0
Liquid
crystal
display
Liquid crystal display column (segment) drive output.
These pins outputs light on level when 1 is in the display
RAM, and light off level when 0 is it.
Relation among output level, M, and display data (D) is as
follows;
M
0
Output
level
RST
CPU or
extemalCR
J
0
I
~
IY~ly3·IY~IY11
The following registers can be initialized by setting the RST
signal to low level.
1.
On/off register 0 set (display off)
2.
Display start line register line 0 set (displays from
line 0)
After releasing reset, this condition can be changed only by
instruction.
t-c
Note:
3
Open
Unused terminals. Don't connect any lines to these
terminals.
1 corresponds to high level in positive logic.
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---_._------
------
---
375
HD61202
Function of Each Block
Interface Control
1. I/O buffer
Data is transferred through 8 data bus lines (DBaOB7).
OB7:
m
MSB (Most signifICant bit)
OBO:
LSB (Least significant bit)
Oata can neither be input nor oulput unless
m to
CS3 are in the active mode. Therefore, when m
to CS3 are not in active mode it is useless to
switch the signals of input terminals except RST
and ADC; that is namely, the internal state is
maintained and no instruction excutes. Besides, pay
attention to RST and AOC which operate
to CS3.
irrespectively of
m
2.
b. Output register
The output register is used to store data temporarily
that is read from display data RAM. To read out the
data from output register,
to CS3 should be in
the active mode and both 0/1 and RIW should be 1.
With the read display data instruction, data stored in
the output register is output while E is high level.
Then, at the fall of E, the display data at the
indicated address is latched into the output register
and the address is increased by 1.
The contents in the output register are rewritten by
the read display data instruction, but are held by
address set instruction, etc.
Register
Both input register and output register are provided
to interface to an MPU whose speed is different
from that of internal operation. The selection of
these registers depend on the combination of RIW
and 0/1 signals (table I).
Therefore, the data of the specified address cannot
be output with the read display data instruction
right after the address is set, but can be output at
the second read of data. That is to say, one dummy
read is necessary. Figure 5 shows the CPU read
timing.
a. Input register
The input register is used to store data temporarily
before writing it into display data RAM.
The data from MPU is written into the input
register, then into display data RAM automatically
by internal operation. When m to CS3 are in the
active mode and Oil and R/W select the input
register as shown in table I, data is latched at the
fall of the E signal.
Table 1
DII
Register SeledioD
R/W
Operation
Reads data out of output register as internal operation (display data RAM -+ output
register)
o
o
o
Writes data into input register as internal operation (input register -+ display data RAM)
Busy check. Read of status data.
o
Instruction
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:::J:
s=
n
2:
»
3CD
~.
n
}>'
!::;
P-
o
:::J:
Sf
n
2:
011
"0
~
"I:l
tiQ"
""<=><=><=>
fD
0
c:
...
VI
en
~.
;;3
J:
a 0~
"0
0
"0
~
':<
0
~
en'
C"
'"
:::l
~
~
C"'l
."
«=
~
fD
------------------~
RIW
E
AddressOutput
register
I\)
Q,
~
iii"
S"
!IQ
DBO-DB?
N
N+1
Data at address N
I
I
Busy
check
Write
address
N
Busy
check
Read
data
(dummy)
I
Busy
check
Read
data at
address
N
N+2
Data at address N + 1
Busy
check
I
Data read
address
N+1
C")
»
<0
<=>
""'"
<=>
'!;.
~
<0
~
~
t11
00
<0
0,
W
<=>
<=>
W
--oJ
--oJ
::r:
t:I
0')
~
I:\)
oI:\)
HD61202
Busy Flag
Busy flag = 1 indicates that HD61202 is operating
and no instructions except status read instruction
can be accepted. The value of the busy flag is read
E _ _.....
out on DB7 by the status read instruction. Make
sure that the busy flag is reset (0) before issuing
instructions.
f
BUSy _ _ _ _.....1
I--
flag
1lfCLK ~T
TBusy
Busy ~3IfCLK
fCLK is 91. 92 frequency
Figure 6
Display On/Ofr Flip/Flop
The display on/off flip/flop selects one of two
states, on state and off state of segments YI to
Y64. In on state, the display data corresponding to
that in RAM is output to the segments. On the
other hand, the display data at all segments
disappear in off state independent of the data in
RAM. It is controlled by display on/off
instruction. RST signal = 0 sets the segments in
off state. The status of the flip/flop is output to
DB5 by status read instruction. Display on/off
instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL
signal (display synchronous signal) should be input
correctly.
. Display Start Line Register
The display start line register specifies the line in
RAM which corresponds to the top line of LCD
panel, when displaying contents in display data
RAM on the LCD panel. It is used for scrolling of
the screen.
6-bit display start line information is written into
this register by the display start line set
instruction. When high level of the FRM signal
starts the display, the information in this register is
Busy Flag
transferred to the Z address counter, which controls
the display address, presetting the Z address
counter.
x,
Y Address Counter
A 9-bit counter which designates addresses of the
internal display data RAM. X address counter
(upper 3 bits) and Y address counter (lower 6 bits)
should be set to each address by the respective
instructions.
1. X address counter
Ordinary register with no count functions. An
address is set by instruction.
2. Y address counter
An address is set by instruction and is increased by
1 automatically by R/W operations of display data.
The Y address counter loops the values of 0 to 63
to count.
Display Data RAM
Stores dot data for display. I-bit data of this RAM
corresponds to light on (data = 1) and light off (data
= 0) of I dot in the display panel. The
correspondence between Y addresses of RAM and
segment pins can be reversed by ADC signal.
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HD61202
As the ADC signal controls the Y address COWlter,
reversing of the signal during the operation causes
malfunction and destruction of the contents of
register and data of RAM. Tberefore, never fail to
connect ADC pin to Vcc (]I' GND when using.
Figure'7 shows the relations between Y address of
RAM and segment pins in the cases of ADC = 1
and ADC = 0 (display start line = 0, 1/64 duty
cycle).
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HD61202
--COM1
--COM2
--COM3
--COM4
--COM5
LCD
display pattern
(HD61203
(HD61203
(HD6l203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
~-COM6
_____
~-
COM7
~~,=-~~:~,=-~~:=====±±t~== ~~~
..........
_--
'I
I
COM62
C0M63
COM64
(HD61203 X62)
(HD61203 X63)
(HD61203 X64)
yy
2 3 Y64
Line
Line 01 ----.-UftiTrirn-I7t~.
Line 2 __ .___ I..r."~~~~t--
o
o
0 0 1
0 0 1
1 0 0 1
o 1 0 1
X.
o0
1
0 0
000
o0 0
o0 0
o
Display
RAM data
1
1
1
0
0
I
.....-1HD61202 Pin Name
DBO(LSB)
DBl
DB2
DB3
DB4
DB5
DB6
DB7(MSB)
I
I
I
I
X.7 L .... rJ
01
0 0 0
Line 62 ----- 1 1 1 1 1 0
Line 63 ----- o 0 o 0 o 0
X1)
X2)
X3)
X4)
X5)
X6)
X7)
X8)
X9)
I
I
I
I
I
I
I
I
I'
o
I I I I I I
o
1 2 3 4 5
616263
RAM Y Address
ADC • 1 (Connected to Vee>
Figure 7
Relation between RAM Data and Display
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HD61202
~---~
...-
..- - - - - . - - -..- . - . - - - . - - - . - - - - -..... - . . .-
-~
---COM1
---COM2
---COMa
--COM4
---COMS
---COM6
---COM7
LCD
display pattern
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
(HD61203
I-~=±=ti=tjt=~~~=tj=}=====COM8
COM9
X1)
X2)
X3)
X4)
XS)
X6)
X7)
X8)
X9)
'-----'---..,..- ,..-'-
yyyy
63
Line 0 ----- o 1 1
Line 1 ----- 1 0 0
Line 2 ----0 0
0 0
X.O
1 1
0 0
Display
0 0
RAM date
0 0 0
0 0 o
Y3 v.! 1
0 0 0 1
0 0 0 1
1 0 0 1
o1 0 1
0 o 1 1
0 0 0 1
0 0 0 1
o0 0 0
o0 0 0
9
o 0
1 0
1 0
1 0
0
0
0
0 0
0 0
'--
X=1
....... -11
~HD61202 Pin Namel
DBO(LSB)
DB1
DB2
DB3
DB4
DBS
DB6
DB7(M SB)
__ I---'--
I
I
I
I
I
I
I
I
I
I
I
I
r--
010 o 0 0
Line 62 ----- 1 1 1 1 1 0
Line 63 ----- o 0 o 0 o 0
I I I I I I
o
(HD61203 X62)
(HD61203 X63)
(HD61203 X64)
y
1
1
0
0
0
1
0
0
0
0
COM62
COM63
COM64
1 2 3 4 S
o
o 0
o
0
616263
~ RAM Y Address
ADC = 0 (Connected to GND)
Figure 7
Relation between RAM Data and Display (cont)
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381
HD61202
Z Address Counter
Reset
The Z address counter generates addresses for
outputting the display data synchronized with the
common signal. This counter consists of 6 bits and
counts up at the fall of the CL signal. At the high
level of FRM, the contents of the display start line
register is preset at the Z counter.
The system can be initialized by setting RST
terminal at low level when turning power on.
Display Data Latch
The display data latch stores the display data
temporarily that is output from display data RAM
to the liquid crystal driving circuit. Data is latched
at the rise of the CL signal. The display· on/off
instruction controls the data in this latch and does
not influence data in display data RAM.
I. Display off
2. Set display start line register line O.
While RST is low level, no instruction except
status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear
RESET) and DB7
0 (Ready) by status read
instruction. The conditions of power supply at
initial power up are shown in table 1.
=
Liquid Crystal Display Driver Circuit
The combination of latched display data and M
signal causes one of the 4 liquid crystal driver
levels, VI, V2, V3, and V4 to be output.
Table 1
Item
Power Supply Initial Conditions
Symbol
Reset time
Min
Typ
Max
1.0
Unit
J.1S
Rise time
200
ns
Do not fail to set the system again because RESET during operation may destroy the data in all the
registers except on/off register and in RAM.
Vee
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HD61202
Display Control Instructions
Outline
Table 2 shows the instructions. Read/write (R/W) signal, data/instruction (DII) signal, and data bus signals
(DBO to DB7) are also called instructions because the internal operation depends on the signals from the
MPU.
These explanations are detailed in the following pages. Generally, there are following three kinds of
instructions:
1. Instruction to set addresses in the internal RAM
2. Instruction to transfer data from/to the internal RAM
3. Other instructions
In general use, the second type of instruction is used most frequently. Since Y address of the internal RAM
is increased by 1 automatically after writing (reading) data, the program can be shortened. During the
execution of an instruction, the system cannot accept instructions other than status read instruction. Send
instructions from MPU after making sure that the busy flag is 0, which is proof that an instruction is not
being excuted.
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383
Co>
S
en
Table 2 InstructioDs
Q>
.".
~
::z:
s=
N
2:
N
o
n
l>
Code
3
CD
:::!.
n
po
!:;
Instructions
R/W DII
DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO Functions
!"-
Display on/off
o
0
0
~
Display start line
o
0
~
'"
Set page (X address)
0
0
Set address
o
0
0
Yaddress (0-63)
0
Busy 0
ON!
•
::z:
2:
·
0
1/0
Display start line (0-63)
Specifies the RAM line displayed at the top of the
screen.
Page (Goo7)
0
Sets the page (X address) of RAM at the page (X
address) register.
N
0
0
0
en
a;.
~
:I
Status read
Reset 0
OFF
~
a-c n
-c
0
• -
Controls display onloff. RAM data and internal
status are not affected. 1: on. 0: off.
Sets the Y address in the Y address counter.
0
0
o
Reads the status.
RESET
~ :I
ON.OFF
tD
Busy
ii"
cr
'"
:::!
!D
(")
Write display data
o
Write data
l>
co
.".
0
0
~
~
co
•
~
..2:!
01
Q>
%
Co>
·0
0
Note: 1. Busy time varies with the frequency (fClK) of +1. and +2,
(lIfCLK s; TBUSY S; MCW
1: Reset
0: Normal
1: Display off
0: Display on
1: Internal operation
0: Ready
Writes data DBO (lSB)
to DB7 (MSB) on the
data bus into display
RAM.
HD61202
Detailed Explanation
Display onloff
ANI
Code
D/I
DB7 - - - - - - - - ...........
DBO
o
D
-
low-order bit -
high-order bit
The display data appears when 0 is 1 and disappears when 0 is O. Though the data is not on the screen
with 0 = 0, it remains in the display data RAM. Therefore, you can make it appear by changing 0 = 0 into
0=1.
Display start line
Code
RIW
D/I
o
o
4-
DB7
...........
high-order bit
low-order bit -
Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed
the top of the screen. Figure 8 shows examples of display (1/64 duty cycle) when the start line = 0-3.
When the display duty cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCO
screen, from the line specified by display start line instruction, is displayed.
at
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
385
HD61202
COM1
COM2
COM3
COM4
COMS
COM6
COM7
COM8
COM9
COM1
.COM2
COM3
COM4
COMS
COM6
COM7
COM8
COM9
COM60
COM61
COM62
COM63--I.
COM64
Start line - 0
COM1
COM2
COM3
COM4
COMS
COM6
COM7
COM8
COM9
Start line - 1
COM1
COM2
COM3
COM4
COMS
COM6
COM7
COM8
COM9
COM60--I.
COM61
COM62
COM63
COM64
Start line - 3
Start line - 2
Figure 8
Relation Between Start Line and Display
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61202
Set page (X address)
Code
ANI
D/I
0
0
I
-
------------~~
DB7
DBO
o
A
A
Iow-order bit -
high-order bit
X address AAA (binary) of the display data ~ is set in the X address register. Mter that, writing or
reading to or from MPU is executed in this specified page until the next page is set. See figure 9.
Set Y address
Code
ANI
D/I
DB7
0
0
0
I
-
------------~"
A
A
DBO
A
A
high-order bit
A
low-order bit -
Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Y address
counter is increased by 1 every time the data is written or read to or from MPU.
o1
Yaddress
2 ------------------- 61 62 63
DBO
Page 0
1x.o
Page 1
1
DB7
DBO
DB7
X.1
r~~====~~--------~
,..,DBO
Page 6
DB7
DBO
Page 7
DB7
Figure 9
----- }x.,
1
X.7
Address Configuration of Display Data RAM
HITACHI
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387
HD61202
Status Read
RIW
-
011 OB7 ------..............
high-order bit
OBO
Iow-order bit -
Busy:
When Busy is I, the LSI is executing internal operations. No instructions are accepted while
Busy is I, SO you should make sure that Busy is 0 before writing the next instruction.
ON/OFF:
Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is I, the display is in off condition.
When ON/OFF is 0, the display is in on condition.
RESET:
RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET =0 shows. that initializing has finished and the system is in the usual operation
condition.
Write Display Data
011 087
.......
080
Codelol 101010101010100
RIW
-
high-order bit
Iow-order bit -
Writes 8-bit data DDDDDDDD (binary) irito the display data RAM. Then Y address is increased by 1
automatically.
Read Display Data
RIW
Code
-
011 087
......
080
1 101010101010101 °
high-order bit
Iow-order bit -
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1
automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of output
register in "FUNCTION OF EACH BLOCK".
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
.' '
HD61202
Use of HD61202
Interface with HD6U03 (1'64 duty cyde)
VCC
COM1
X1
Vee
V1l, V1R
V61, V6R
V5l, V5R
V2l,V2R
VEE
GND
Vee
V1
V6
V5
V2
VEE
)
lCDPanel
54 x 54 dots
i'!
COM54 ....
X54
fa
fa
C/)
C/)
HD61203
SHL
DS1
DS2
TH
Cl1
FS
MIS
FCS
S'ii
Dl
DR
~
Open
Open
Y1 ~Y54
M
CL2
FRM
til 1
t112
M
Cl
FRM
til 1
82
Vee
V1l, V1R
V2L, V2R
V3l, V3R
V4l,V4R
HD61202
VEElo V EE2
----------,
Power supply circuit
+5V Vee)
Vee
ADC
RST
GND
I
R3V1
R1
R1
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Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy, 0Brisbane,CA 94005-1819 0(415) 589-8300
- - - - - _ .. __ . .-_..
--
...... _..
~--.
--'-~--'-'
.~---~
._._-
389
HD61202
81
-----u---u--u----------"s--
82
~-----~
-----------:...-----------
,
'\
\
Input
CL
FRM
M
~-----~-----~
-Wl ! ! ------4-n ! ! ------W1'! I '. I
I -----""TT9. I 11 frame
1....,.--+-+-t
1 frame
I I -----:::f!:I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I·
I I
I I
I
I
I
I
I
I
I I
X1
X2
,
(
)
I
1+WT
II
II
I I
COM
I
IIIV6
I I1
I
V2
I
I
IIIv61
~
TTl
I I V1
I I
II
I
I
I
I
1
V6
F------
I
I
!
I,
I I
I V6 I
I
I
I
I
I
I
I
I V1
!
!!
I
I
~I
~
~IV1
X64 V5
-----
,
I
I
II
II
II
_____
j'"l1V2
I
IIv6
I I r1
-----TTl I
!! !
IV1,
I
V5
1
II~
I
I
I
I
I
I
I
rr-uL
-----~!
i
I
I
I
I
I
I
I
I
I
I
I
V1
Y1
Y64
V1
~-----+H ! !
YL---Ufl
ii~"
I I I
I I
I I I
linllV1
I
I I
I
I
I YL__ I
,
III
SEG
I
I
I
I
I
I
IV1 1
V3
41
I
I
I
I
V2
!!
Selected
I· "I·
I
I
Non-selected
"
I
!
I
I
I
!
The waveforms of Y1 to Y64 outputs vary with the display date. In this
example, the top line of the panel lights up and other dots do not.
Figure 10 LCD Driver Timing Chart (1/64 duty cycle)
HITACHI
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Hitachi America, Ltd." Hitachi Plaza" 2000 Sierra Point Pkwy." Brisbane, CA 94005-1819" (415) 589-8300
HD61202
Interface with CPU
1.
Example or connection with 8D6800
Decoder
A15
I
A1
VMA
AO
r-r ~
.- mCS2
I
L
-
J
VCC -
011
ANI
H06800
ANI
HD61202
1/J2
DO
I
07
CS3
E
I
I
I
080
I
OB7
fVCC
RES
Figure 11
t
Jm
Example or Connection with 8D6800 Series
In this decoder, addresses of HD61202 in the address area of HD6800 are:
Read/write of the dispJay data
$FFFF
write of dispJay inslrUction $FFFE
$FFFE
Read out of status
Therefore, you can conbOl HD61202 by reading/writing the data at these addresses.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
--~-
._.
------
391
HD61202
1.
Example or connection with HD6801
74L8154
P10
P11
P12
P13
(108)(8C1)
(RIW) (8C2)
YO
Y1 I
I
A
B
I
.
I
I
C82
Vcc- C83
I
C
I
..!..
Y15
D
G1 G2
,
.- em
RIW
P14
D/I
HD61202
No.1
HD6801
E
E
P30
P31
(Date bus)
DBO
DB1
I
I
I
l
I
I
I
I
P37
DB7
Set HD6801 to mode 5. PIO to P14 are used
as the output port and P30 to P37 as the data
bus.
74LSI54 4-to-16 decoder generates chip select
signal to make specified HD61202 active after
decoding 4 bits of PIO to P13.
Therefore, after enabling the operation by PI0
to P13 and specifying DII signal by P14,
read/write from/to the external memory area
($0100 to $OIFE) to control HD61202. In this
case, lOS signal is output from SCI and R/W
signal from SC2.
For details of HD6800 and HD6801. refer to
their manuals.
.
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415} 589-8300
HD61202
Example of Application
HD61202
No.9
V1--V64
!-------
HD61202
No. 10
V1--V64
-----------
!-------
HD61202
No. 16
V1--V32
! -------
COM1
OOM2
COM3
i
X1
r-
8-cX2 rN CD X3
r--
t- ~2
-. I
L-
:::r:~X"
1
8 ......
X1
X2
~1 X3
I
I
I
I
I
I
I
I
C0M64
LCD Panel
128 )( 480 dots
C0M65
COM66
C0M67
co (I) I
o~
:::r:
X64 r-
,
COM128
Note:
1-------1
1-------1
V1--V64
HD61202
NO.1
V1--V64
HD61202
No.2
1-------1
-----------
V1--V32
HD61202
No.8
In this example. two HD61203s output the equivalent waveforms. So. stand-alone operation is
possible. In this case. connect COM1 and COM65 to X1. COM2 and COM66 to X2 •..•• and COM64
and COM128 to X64. However. for the large screen display. it is better to drive in 2 rows as in this
example to guarantee the display quality.
HITACHI
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393
HD61203--------~--(Dot Matrix Liquid Crystal Graphic
Display Common Driver;
Description
Features
The HD61203 is a common signal driver for dot
matrix liquid crystal graphic display systems. It
generates the timing signals (switch signal to
convert LCD waveform to AC, frame synchronous
signal) and supplies them to the column driver to
contrcil display. It provides 64 driver output lines
and the impedance is low enough to drive a large
screen.
As the HD61203 is produced by a CMOS process,
it is fit for use in portable battery-driven equipment
utilizing the liquid crystal display's low power
consumption. The user can easily construct a dot
matrix liquid crystal graphic display system by
combining the HD61203 and the column (segment)
driver HD61202.
Dot matrix liquid crystal graphic display
common driver with low impedance
Low impedance: 1.5 ill max
Internal liquid crystal display driver circuit: 64
circuits
Internal dynamic display timing generator
circuit
Display duty cycle
When used with the column driver HD61202:
1/48, 1/64, 1/96, 1/128
When used with the column driver HD61200:
Selectable out of 1/32 to 1/128
Low power dissipation: During display: 5 mW
Power supplies: Vee: 5 V ± 10%
Power supply voltage for liquid crystal display
drive: 8 V to 17 V
CMOS process
loo-pin flat plastic package (FP-loo)
Absolute Maximum Ratings
Item
Symbol
Limit
Unit
Note
Power supply voltage (1)
Vee
-0.3 to +7.0
V
2
Power supply voltage (2)
VEE
Vee -19.0 to Vee + 0.3
V
5
Terminal voltage (1)
Vn
- 0.3 to Vee + 0.3
V
2,3
4,5
Terminal voltage (2)
VT2
VEE - 0.3 to Vee + 0.3
V
Operating temperature
Topr
-20 to +75
'C
Storage temperature
Tstg
-55 to +125
'C
Notes:
1.
2.
3.
4.
5.
If LSls are used beyond absolute maximum ratings, they may be permanently destroyed. We
strongly recommend you to use the lSI within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
Based on GND .. OV.
Applies to input terminals (except V1l, Vi R, V2l, V2R, V5L, V5R, VSl, and VSR) and 110
terminals at high impedance.
Applies to Vi L, Vi R, V2L, V2R, V5L, VSR, V6l, and V6R.
Apply the same value of voltages to V1l and Vi R, V2l and V2R, VSl and VSR, V6l and VSR,
VEE (23 pin) and VEE (58 pin) respectively.
Maintain Vee ~ Vi L .. Vi R ~ VSl- VSR ~ VSl = VSR ~ V2l .. V2R ~ VEE
HITACHI
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Hitachi America:Ud.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
Pin Arrangement
X22
X21
X43
X44
~O
X~
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X46
X47
X48
X49
X50
X51
X52
X53
X54
X55
X56
X57
X58
X59
X60
X61
X62
X63
X64
VEE
VEE
V6L
V5L
V2L
V1L
V6R
V5R
V2R
V1R
Vee
DL
TH
Cl2
FS
CU
(Top view)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
395
HD61203
Electrical Characteristics
DC Characteristics
(Vee = 5 V ± 10%, GND
= 0 V,
Vee - VEE
= 8.0
to 17.0 V, Ta
= -20
to +75°C)
Specifications
Test Item
Symbol Min
Max
Unit
Input high voltage
VIH
0.7xVcc
Vee
V
Input low voltage
VIL
GND
0.3 x Vee
V
Output high voltage
VOH
Vee -O.4
Output low voltage
VOL
Vi-Xj on resistance
~
Input leakage current
IlL 1
-1.0
Typ
Test Conditions Note
V
IOH --0.4 mA
2
0.4
V
IOL= 0.4 mA
2
1.5
kn
Vee - VEE = 17V
Load current
±150 J.IA
13
1.0
Vin= Oto Vee
3
Input leakage current
IIL2
-2.0
2.0
J.IA
J.IA
Vin - VEE to Vee
4
Operating frequency
foprl
50
SOO
kHz
In master mode
external clock
operation
5
Operating frequency
fopr2
0.5
1500
kHz
In slave mode
shift register
S
Oscillation frequency
fosc
315
585
kHz
Cf .. 20pF±5%
Rf-47kn±2%
7, 12
Dissipation current
(1 )
IGGl
1.0
rnA
In master mode
1/128 duty cycle
Cf-20pF
Rf=47kn
8,9
Dissipation current
(2)
IGG2
200
J.IA
In slave mode
1/128 duty cycle
8, 10
Dissipation current
lEE
100
J.IA
In master mode
1/128 duty cycle
8, 11
Notes:
1.
2.
3.
4.
5.
450
Applies to input terminals FS, DS1, DS2, CR, SHL, MIS, and FCS and 110 terminals DL, M, DR,
and CL2 in the input state.
Applies to output terminals, "1, "2, and FRM and 110 common terminals DL, M, DR, and CL2in
the output state.
Applies to input terminals FS, DS1, DS2, CR,
SHL, MIS, FCS, CU, and TH. I/O terminals
DL, M, DR, and CL2 in the input state and NC terminals.
Applies to V1 L, V1 R, V2L, V2R, V5L, V5R, VSL, and VSR. Don't connect any lines to X1 to
XS4.
External clock is as follows.
sm,
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
TH
Tl
TH
Outy Cycle. TH tTl
External clock
waveform
Min
Typ
Max
Unit
45
50
55
%
trcp
50
ns
tfcp
50
ns
DU~
~e
trcp
External
tfcp
R C
- , "]CR""r~
6.
7.
x 100%
Applies to the shift register in the slave mode. For details, refer to AC Characteristics.
Connect oscillation resister (Rf) and oscillation capacitance (Cf) as shown in this figure.
.
Oscillation frequency (fose) is twice as much as the frequency (flJ) at 1J1 or 1J2.
1J1, 1J2
Cf.20pF
Rf - 47 kCl
fosc .2
X
flJ
No lines are connected to output terminals and current flowing through the input circuit is
excluded. This value is specified at VIH '" Vee and Vil - GNO.
9. This value is specified for current flowing through GNO in the following conditions: Internal
oscillation circuit is used. Each terminal of OS1, OS2, FS, SHL, MIS, STB, and FCS is
connected to Vee and each of CL1 and TH to GNO. Oscillator is set as described in note 7.
10. This value is specified for current flowing through GNO under the following conditions: Each
terminals of OS1, OS2, FS, SHL, STB, FCS, and CR is connected to Vee, CL1, TH, and MIS to
GNO and the terminals CL2, M, and OL are respectively connected to terminals CL2, M, and
OL of the H061203 under the condition described in note 9.
11. This value is specified for current flowing through VEE under the condition described in note 9.
Don' connect any lines to terminal V.
12. This figure shows a typical relation among oscillation frequency, Rf and Cf. Oscillation
frequency may vary with the mounting conditions.
8.
I
I
I
I
j
I
I
I
600
--~--------~---I
I
400
-------- --------t----
I
Cf '" 20 pF
I
I
I
I
I
I
200 --------~-------I
I
I
o
I
I
I
I
I
50
100
Rf (ke)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
397
HD61203
13. Resistance between terminal X and terminal V (one of V1 L. V1 R, V2L, V2P., VSL, VSR, V6L.
and V6R) when load current flows through one of the terminals X1 to X64. This value is
specifi~ under the foRowing conditions:
Vcc - VEE - 17 V
V1l - ~R' V6l- V6R - Vee -1n (Vee- VEE)
V2l - V2R ' VSl- VSR- VEE +1n (Vee- VEE)
V1L, ViR
0
V6L, \tR
0
\5L,\SR
0
'---0
,"o--J\N\,-----+
Terminal X
(X1 to X64)
~L,\2R
The following is a description of the range of power supply voltage for liquid crystal display drive. Apply
positive voltage to VIL =VIR and V6L =V6R and negative voltage to V2L =V2R and V5L =VSR
within the l!V range. This range allows stable impedance on driver output (RON). Notice that l!V depends
on power supply voltage Vcc -VEE.
---,r---------Vee
-------- V1 (V1 L - V1 R )
---- V6 (V6L - V6R )
Range of Power Supply
Voltage for Liquid Crystal
Display Drive
2 --------------------- VS (VsL - VSR )
-------------- V2 ("2L • V2R )
VEE
8
Vee - VEE (V)
17
Correlation between Power
Supply Voltage Vee- VEE and AV
Correlation between Driver
Output Waveform and Power
Supply Voltages for Liquid
Crystal Display Drive
HITACHI·
398
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point P~.• Brisbane,CA 94005-1819· (415) 589-8300
HD61203
Terminal Configuration
Input Terminal
Applicable Terminals:
CR, MIS, SHl, FCS, DS1, DS2, FS
Vee
Applicable Terminals: DL. DR, CL2, M
VOTerminai
r'lee
Input circuit)
PMOS
NMOS
Vee
r------ ---r---:I PMOS
Enable
Jt-:
I
:
:
I
I
II
:
: Output circuit
(tristate)
I
L..-_ _ _ _ _ _--I,'NMOS
Data
L ________ -1
Output Terminal
Applicable Terminals:
81, 82, FRM
PMOS
NMOS
Output Terminal
V1l,V1R
Applicable Terminals:
X1 toX64
Vee
..c-
PMOS
VSl, VSR
Vee
..c-
NMOS
NMOS
V5l, V5R
V2l, V2R
VEE
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
399
HD61203
AC Characteristics (Vee = 5 V ± 10%, GND = 0 V, Ta ::: -20 to +7S0C)
In the slave mode (MIS = GND)
CL2
(FCS ",GND)
(Shift clock)
CL2
(FCS '" Vcc)
(Shift clock)
DL (SHL '" Vcc)
DR (SHL '" GND)
Input data
DR (SHL '" Vee)
DL (SHL '" GND)
Output data
Item
Symbol
Min
CL2 low level width (FCS..GND)
tWLCL2L
450
ns
CL2 high level width (FCS-GND)
tWLCL2H
150
ns
CL2low level width (FCS.Vcc)
tWHCl21
150
ns
CL2 high level width (FCS.Vcc)
tWHCL2H
450
ns
Data setup time
tos
100
ns
Data hold time
tOH
100
ns
Data delay time
too
Output data hold time
tOHW
CL2 rise time
tr
30
ns
CL2 fall time
tf
30
ns
Notes: 1.
Typ
Max
200
Unit
Note
ns
ns
10
The following load circuit is connected for specification:
Output 0
Terminal
l
J
30 pF (Includes jig capacitance)
HITACHI
400
Hitachi America, Ltd.· Hitachi Plaza· 2000~ierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
2.
In the master mode (MIS. Vex;. FCS. Vex;. Cf. 20 pF. Rf. 47 kn)
CL2
tOH
tOH
0.7Vex;
DL (SHL - Vex;)
DR (SHL • GND)
I
0.3Vee
too
DR (SHL. Vee)
DL (SHL • GND)
tOFRM -~~:.....-=~-r--tDFRM
FRM
M
0.7Vex;
O.3Vee
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 SierraPoint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
401
HD61203
Data setup time
tos
20
Unit
J.l.s .
Data hold time
toH
40
J.l.s
Item
Symbol
Min
Typ
Max
Data delay time
too
5
FRM delay time
toFRM
-2
2
M delay time
tOM
-2
2
tWCL2l
35
J.l.s
au low level width
au high level width
J.l.S
J.l.s
J.l.s
tWCL2H
35
J.l.s
,,1 low level width
tW81L
700
ns
,,2 low level width
tW82L
700
ns
,,1 high level width
tW81H
2100
ns
,,2 high level width
tW82H
2100
ns
,,1-e2 phase difference
t012
700
ns
,,2-e1 phase difference
t021
700
ns
"1, ,,2 rise time
tr
150
ns
"1, ,,2 fall time
tf
150
ns
HITACHI
402
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-830Q
=
~
::r:
iif
C">
V2L V6l
V1l V5l
X1
2:
?3
X2 ----
•~•.
t:::I
V2R V6R
64 output terminal 5
.
V1R V5R
----- X62 X63 X64
.
a
CD
~.
!»
!::;
Vee
•
GND
I-I--
VEE
f-
<:>
""
<:>
CL1
I--
en
TH
I--
!"-
::r:
iif
C">
=-
Liquid crystal display
driver circuits
'---
2:
"'0
~
·
<:>
CD·
iii :I
~~
:;;0
.--DL
~~
~
•
aI
:::1.
U>
0-
1
t--- Logic
2
r---
Bic;lirectional shift
register
62
63
64
logic
I-
DR
i'4t-
.-
:r
s»
::::J
5"
n
»
~
<:>
<:>
~
~
·
<0
~
~
C11
co
%
SHl
STB
.~
Oscillator
_
RIQ~
f--
Timing generation circuit
FCS
8-
M
CL2
FRM
...... C
Rf Cf
MIS
FS
DS1 DS2
G1
G2
::r:
t1
~
0)
.,.
o
~
<:>
t..)
w
~
II
HD61203
Block Functions
Oscillator
The CR oscillator generates display timing signals and operating clocks for the HD61202. It is required
when the HD61203 is used with the HD61202. An oscillation resister Rf and an oscillation capacitor Cf
are attached as shown in figure 1 and terminal STB is connected to the high leveL When using an external
clock, input the clock into terminal CR and don't connect any lines to terminals R and C.
CR
f
Rf
Figure 1
I
External Open
clock
Cf
Oscillator Connection with 8D61202
The oscillator is not required when the HD61203 is used with the HD61830. Then, connect terminal CR to
the high level and don't connect any lines to tenninals R and C (figure 2).
CR
Figure 2
I
J
Open
Vee
ciI
Open
Oscillator Connection with 8D61830
Timing Generator Circuit
The timing generator circuit generates display timing and operating clock for the HD61202. This circuit is
required when the HD61203 is used with the HD61202. Connect tenninal MIS to high level (master
mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from
HD61830. In this case connect the tenninals Fs, DSl, and DS2 to high level and MIS to low level (slave
mode).
Bidirectional Shilt Register
A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from
DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the
bi~tional shift register, which is on the DL side, corresponds to Xl and the highest order bit on the DR
side corresponds to X64.
HITACHI
404
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
Liquid Crystal Display Driver Circuit
The combination of the data from the shift register with the M signal allows one of the four liquid crystal
display driver levels VI, V2, V5 and V6 to be transferred to the output terminals (table 1).
Table 1
Data from the
Shift Register
Output Levels
M
Output level
V2
o
o
V6
o
V1
o
V5
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
405
HD61203
HD61203 Terminal Functions
Terminal Number of 1/0 Connected
Function
Name
Terminals
to
Vcc;-GND: Power supply for interoallogic.
Vee
1
Power
GND
supply
1
Vcc-Vee:Power supply for driver circuit logic.
Vee
2
V1L, V2l
V5L, V6l
V1R.V2R
V5R.V6R
8
Power
liquid crystal display driver level power supply.
supply
V1 l (V1 R). V2l (V2R): Selected level
V5l (V5R). V6l (V6R): Non-selected level
Voltages of the level power supplies connected to V1 l and
V1 R should be the same: (This applies to the combination
of V2l & V2R. V5l & V5R and V6l & V6R respectively)
Vee or GND
Selects master/slave.
MIS. Vee: Master mode
When the HD61203 is used with the HD61202. timing
generation circuit operates to supply display timing signals
and operation clock to the HD61202. Each of I/O common
terminals Dl. DR. CL2. and M is in the output state.
MIS - GND: Slave mode
The timing operation circuit stops operating. The HD61203
is used in this mode when combined with the H061830.
Even if combined with the HD61202. this mode is used
when display timing signals (M. data. CL2. etc.) are
supplied by another HD61203 in the master mode.
Terminals M and CL2 are in the input state.
When SHl is Vee. Dl is in the input state and DR is in the
output state.
When SHl is GND. Dl is in the output state and DR is in
the input state.
FCS
Vee or GND
Selects shift clock phase.
FCS - Vee: Shift register operates at the rising edge
of CL2. Select this condition when
H061203 is used With H061202 or when
MA of the HD61830 connects to CL2 in
.combination with the HD61830.
FCS • GND: Shift register operates at the fall of CL2.
Select this condition when Cl1 of
HD61830 connects to CL2 in combination
with the HD61830.
FS
VeeorGND
Selects frequency.
When the frame frequency is 70 Hz. the oscillation
frequency should be:
fose - 430 kHz at FCS - Vee
fose - 215 kHz at FCS • GND
This terminal is active only in the master mode. Connect it
to Vee in the slave mode.
HITACHI
406
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
HD61203 Terminal Functions (cont)
Terminal
Name
Number of 1/0 Connected
to
Function
Terminals
DS1,DS2
2
VeeorGND
Selects display duty factor
Display Duty Factor
1/96
1/128
GND
Vee
Vee
Vee
GND
Vee
1/48
1/64
DS1
GND
DS2
GND
These terminals are valid only in the mastEIr mode.
Connect them to Vee in the slave mode.
STB
lH
CL1
1
1
Vee or GND
Input terminal for testing.
Connect to STB Vee.
Connect TH and CL1 to GND.
CR,R,C
3
Oscillator.
1
In the master mode, use these terminals as shown below:
Internal oscillation
Rf
External clock
Cf
~~
R
CR
C
Open
II
I
R
External
Clock Open
I
CR
I
ci
In the slave mode, stop the oscillator as shown below:
Open
I
IR
1IJ1,IIJ2
2
o
HD61202
Vee
I
CR
Open
I
CI
Operating clock output terminals for the HD61202.
Master mode: Connect these terminals to terminals 1IJ1
and 1IJ2 of the HD61202 respectively.
Slave mode:
o
HD61202
Don' connect any lines to these
terminals.
Frame signal.
Master mode: Connect this terminal to terminal FRM of
the HD61202.
Slave mode:· Don' connect any lines to this terminal.
M
I/O
MBof
HD61830
orMof
HD61202
Signal to convert LCD driver signal into AC.
Master mode: Output terminal.
Connect this terminal to terminal M of the
HD61202.
Slave mode:
Input terminal.
Connect this terminal to terminal MB of
the HD61830.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
407
HD61203
HD61203 Terminal Functions (cont)
Terminal Number of 110 Connected
Name
Terminals
to
Function
Cl2
110
Shift clock
Cl1 or MAof
HD618300r
CLof
HD61202
Master mode: Output terminal
Connect this terminal to terminal CL of
the HD61202.
Slave mode:
2
DL,DR
1/0
Open or FLM
of HD61830
Input terminal
Connect this terminal to terminal CL1 or
MA of the HD61830.
Data 110 terminals of bidirectional shift register.
DL corresponds to X1 's side and DR to X64's side.
Master mode: Output common scanning signal. Don't
connect any lines to these terminals
normally.
Slave mode:
Connect terminal FLM of the HD61830 to
DL (when SHL .. Vcc) or DR (when SHL ..
GND)
MIS
GND
GND
SHL
NC
5
Open
Vee
GND
DL
Output
Output
Input
Output
DR
Output
Output
Output
Input
Not used.
Don't connect any lines to this terminal.
SHL
Vee or GND
X1-X64
64
o
Liquid
crystal
display
Selects shift direction of bidirectional shift register.
SHL
Shift Direction
Common Scanning Direction
Vee
DL~DR
X1
GND
DL .... DR
X1 .... X64
~X64
Liquid crystal
."
."
t')
~
Q
from DUDR
of HD61203 COM128-COM65
No.1
COM64-COM1
toM
toCLof
to t1
to +2
to FRM
L L
RfRf
HD61202
o
of
of
of
HLLHH
H
Cf HD61202 HD61202 HD61202 HD61202 to CL20f
LO~
Cf
HD61203 HD61203
H
to DUDR
of HD61203 COM1-COM64
No.2
L
toDUDR
of HD61203
No.2
COM64-COM1
from M fromCL2
of
of
HD61203 HD61203
No.1
No.1
H
from DUDR
of HD61203
No.1
COM1-COM64
»
-....
Q
COMGS-COM128
L
C")
~
a
."
COM64-COM1
COM1-COM64
L L
Rf Rf
toFRM
toM
toCL
to +1
to +2
or H
of
of
of
of
of
Cf
Cf HD61202 HD61202 HD61202 HD61202 HD61202
L H
=
1:1
fD
H
H L L H H
=
~
n
from FLM
of
HD61830
H
X1-X64
<":l
fromFLM
of
HD61830
L
en::>
from MB from MA
of
of
HD61830 HD61830
:I
~
C"
from MB fromMA
of
of
HD61830 HD61830
l:
'"
~ ~
:;0
!
LLLHHHHHH--
DL
L
n
'"
~
=
....'='
Rf: Oscillation resister
Cf: Oscillation capacitor
to
~
0
0
c.n
,
~
~
to
E
•
~
~
c.n
co
to
0,
w
0
0
F
L L L H H H H H H --
~
0
to
II
L
::r::
d
0")
from DUDR
of HD61203 COM64-COM1
No.1
....
~
0
W
HD61203
Outline of HD61203 System Configuration
1.
Use with HD61830
a. When display duty ratio of LCD is 1/64
HD61830~
No 1
•
COM1
LCD
I
-.;:CO=M~64
___--,.
One HD61203 drives
common signals.
Refer to
Connection list A.
One HD61203 drives
common signals for
upper and lower
panels.
Refer to
Connection list A.
Two HD61203s drive
upper and lower
panels separately
to ensure the
quality of display.
No. 1 and No.2
operate in parallel.
For both of No. 1
and No.2, refer to
Connection list A.
HD61830
Upper
Lower
HD61830
Upper
Lower
b. When display duty ratio of LCD is from 1/65 to 1/128
Two HD61203s
connected serially
drive common signals. '
Refer to Connection
list B for No.1.
Refer to Connection
list C for No.2.
Two HD61203s
connected serially
drive upper and
lower panels in
parallel.
Refer to Connection
list B for No.1.
Refer to Connection
list C for NO.2.
Two sets of
HD61203s connected
serially drive upper
and lower panels in
parallel to ensure
the quality Qf
display.
Refer to Connection
list Bfor No.1
and 3.
Refer to Connection
list C for No.2
and 4.
HITACHI
410
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005~1819· (415) 589-8300
HD61203
2.
Use with HD61202 (1164 duty ratio)
COM1
COM64
LCD
One HD61203 drives
common signals and
supplies timing
signals to the
HD61202s.
Refer to
Connection list D.
One HD61203 drives
upper and lower
panels and supplies
timing signals to
the HD61202s.
Refer to
Connection list D.
HD61202
Upper
Lower
Upper
Lower
Two HD61203s drive
upper and lower
panels in parallel
to ensure the
quality of display.
No. 1 supplies
timing signals to
No.2 and the
HD61202s.
Refer to
Connection list E
for No.1.
Refer to
Connection list F
for No.2.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
411
HD61203
"
Connection Example 1
Use with HD61202 (RAM type segment driver)
a. 1/64 duty ratio (See Connection List D)
Ct
Rt
C
X1
(XS4)
CR
)
R
VCC
R3V1
V1L,V1R
R3VS
VSL,VSR
+5V (VCC)
COM1
) )
XS4
(X1)
COMS4
M
CL2
FRM
81
82
M
CL
FRM
81
82
LCD panel
~
•
..J
J:
CJ)
'lii
.!!l
S
C\I
R3V2
VEE
-10V
OV
VEE
GND
Open
Open
VCC
«i
V2L, V2R
DL
DR
Cl
J:
HDS1202
SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STB
V1 V3V4V2 o~ w
o w
>Cl>
R3 ",15 n
Figure 1 Example 1
Note:
The values of R1 and R2 vary with the LCD panel used.
When bias factor is 119, the values of R1 and R2 should satisfy
R1
1
4R1 + R2-9
For example,
R1 - 3 kn, R2 -15 kn
HITACHI
412
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
I
I
GIl
EI
e!1
-I
..... 1
I
I
I
I
-
~
-----
~
-.......~.... ....:x:•
CJ)
1ii
o
Figure 2
Example 1 Waveform (RAM Type, 1/64 Duty Cycle)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
413
HD61203'
Connection Example 2
Use with HD6183G (Dispiay conlroller)
a. 1/64 duty ratio (See Connection List A)
X1
(X64)
Open - C
CR
Vee
Open - R
V,..,..
COM1
) )
)
Vee
V1 - V1L. V1R ~
X64
(X1)
LCD panel
COM64
6 - V6L. V6R ~
J:
I
CJ)
I
c
.!II
M
CL2
DL(DR)
C\I
DR(DL) -Open
16
c
8
5 - V5L. V5R
V
V2 - V2L.V2R
-a
CD
!
MB
CL1
FLM
c
SHL
DS1
DS2
TH
CL1
FS
MIS
FCS
STB
ND- GND
Open - FRM
Open - 81
Open - 82
(Display Controller)
VCC
J:
E E - VEE
HD61830
-
f-
-
~
l
Figure 3
Example 2 (1/64 Duty Ratio)
HITACHI
414
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.'; Brisbane, CA 94005-1819· (415) 589-8300
HD61203
_______..a....._..,..
N
___________
~ -----...--..;......1
N
------- ----------
------------.~~-~
.....
>
~~
t3 -------- x~ ~
......
,~------~/
oe8~90H wOJJ
Figure 4
Example 2 Waveform (1/64 Duty Ratio)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
415
HD61203
b. 1/100 duty ratio (See Connection List B, C)
Vee
OPT
/ V e e - - - - - - - - . - I V e e cc
V1
V1L,V1R
1r----++--I-I V6L,V6R
V6 _ _----I ...--_H-HV5L, V5R
r--_H-I-HV2L, V2R
....-1-4-1-1-1-1 VEE
.-I-~I-I-IGND
V5------I
t'fen
5 <.>
f.I Vee
SHLt-rDS1 t-IDS2 -ITH-
V2----...J
VEE - - - - - - - 1
GNDI------I....
l...--.
L...-_ _- . j
:E~oc::J
FLMIMAr-MB"--
<.>e.e.
...JCC
eOM1
LCD
COM64 Panel
...-----1 eOM65
X1
(X64
W
~
(
I
(
I
r- eOM100
Vee 0 0
V1L, V1R
X36.1-_----I1
'-- V6L, V6R
(X29
' - - V5L, V5R
'----IV2L, V2R
SHLt-L-I----IVEE
~ DS1 r-...J
'-----IGND
'i'
N DS2t-~
...J
THt!!t :I:
C/J eL1 tOpen- e
~ 10 FSt-tCD (\I .!!l
Vee- eR
0 0 - MIStOpen- R
:I: Z ...... FeSt-rSTBt-rI.-
I
Figure 5
Vee
Example 2 (11100 Duty Ratio)
HITACHI
416
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61203
9 ~N -----1£ ~ ~ 1
- -----.,....
~
----- - > -------
---
~ -----~
~
------ -- ------- ------- ---------
--------'---,
_______ ------::;;..1
CD
j
_a
...IN
,~
:::E
It
~I'
O£8~90H
Figure 6
----- x~~
~d xi
~
.....
,C:X:Z
~
·ON £O~~90H
1"
x~i
---~
~
com
(,)N
x~
I'
·ON £O~~90H
Example 2 Waveform (1/100 Duty Ratio)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
417
HD61830-------------
LeTe (LCD Timing Controller)
Pin Arrangement
Description
The HD61830 is a dot matrix liquid crystal
graphic display controller LSI that stores the
display data sent from an 8-bit microcontroller in the external RAM to generate dot
matrix liquid crystal driving signals. It has a
graphic mode in which l-bit data in the
external RAM corresponds to the on/off state
of 1 dot on liquid crystal display and a c~ar
acter mode in which characters are displayed
by storing character codes in the external
RAM and developing them into the dot patterns with the internal character generator
ROM. Both modes can be provided for various
applications. The HD61830 is produced by the
CMOS process. Thus, combined with a CMOS
microcontroller it can complete a liquid crystal qisplay device with low power dissipation.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
..
III)
CD""IIO CD
UUiUUU
54 MAIO
MAn
MAI2
MAIS
MAl.
MAIS
A
CPO
D 2·
DI
CL 2
AD 0
AD I
43 RD 2
....", .. -Cto
....
:!l:!l:!l:!l~n~
UUii
CD . . . ", ..
(Top View)
Dot matrix liquid crystal graphic display
controller
Display control capacity
-Graphic mode: 512k dots (216 bytes)
-Character mode: 4096 characters (21 2
characters)
Internal character generator ROM: 7360
bits
-160 types of 5 x 7 dot characters
-32 types of 5 x 11 dot characters
Total 192 characters
-Can be extended to 256 characters (4k
bytes max.) by external ROM
Interfaces to 8-bit MPU
Display duty cycle (Can be selected by a
program)
-Static to 1/128 duty cycle
Various instruction functions
-Scroll, Cursor on/off/blink, Character
blink, Bit manipulation
Display method: Selectable A or B types
Internal oscillator (with external resistor
and capacitor)
Operating frequency: 1.1 MHz
Low power dissipation ,
Power supply: Single + 5 V ± 10%
CMOS process
Package: 60-pin plastic OFP (FP-60)
HITACHI
418.
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
td
8pr
x
Sf
n
=-»
52
SYNC CLI MA M B FLM
~...
3
CD
5"
WE
p>
C
x•
Sf
n
=-
OBO- OB7
i•
~s ~
N
R/W
en
RES
m·
iii 1:
"U
a
"U
~
•
-r
cs )
0
0
.0
0
~
;!;
8
I.~
MO
8
~
I r;-;:::::
8
Ita
out···~
f6
hl' II;~~}
---.
'---
D
M~
control
register
IMCR}
;1..§s
~ ..
Busyi
.flag
»
Character
... --:
I
h I rrLl J
~-eiij
1: c
8·~' - - _..,
-~.6>~
I!!::.
§
I
Hgenerator
8
(")
~
V
01
isCT
I»
B
____o-,
g:J
~
R~
r---
!'L
ROM
(CGROM)
M07
8X1ernal
:
ROM
I
L.---T-----J
i
I
____ -'-_.JI
signal
aenerator
ROo -R0 7
Control
signal
i
01
(BF)
0
0
en
~-+---D2
.!.
~
c.o
•
~
.2!
en
CD
%
Co)
0
0
CL2
CPO
*When extended external ROM is used. MAo-MA"
are applied to RAM. MA12 -MA'5 are applied to
extended external ROM.
6en
~
(X)
....
~
c.o
W
o
HD61830
Block Functions
Registers
Refresh Address Counters (RAC1/RAC2)
The HD61830 has the five types of registers:
instruction register (IR), data input register
(DIR), data dutput register (DOR), dot registers (DR), and mode control register (MCR).
The refresh address counters, RACl and
RAC2, control the addresses of external RAM,
character generator ROM (CGROM), and
extended external ROM. The RACl is used for
the upper half of the screen and the RAC2 for
the lower half. In the graphic mode, 16-bit
data is output and used as the address signal
of external RAM. In the character mode, the
high order 4 bits (MA12 - MA15) are ignored.
The 4 bits of line address counter are output
instead and used as the address of extended
ROM.
The IR is a 4-bit register that stores the
instruction codes for specifying MCR, DR, a
start address register, a. cursor address register, and so on. The loWer order 4 bits DBO to
DB3 of data buses are written in it.
The DIR is an 8-bit register used to temporarily store the data written into the external
RAM, DR, MCR, and so on.
.
The DOR is an 8-bit register used to temporarily store the data read from the external
RAM. Cursor address information is written
into the cursor address counter (CAC)
through the DIR. When the memory read
instruction is set in the IR (latched at the
falling edge of E signal), the data of external
RAM is read to DOR by an internal operation.
The data is transferred to the MPU by reading
the DOR with the next instruction (the contents of DOR are output to the data bus when
E is at the high level).
Character Generator ROM
The character generator ROM has 7360 bits in
total and stores 192 types of character data. A
character code (8 bits) from the external RAM
and a line code (4 bits) from the line address
counter are applied to its address signals, and
it outputs 5-bit dot data.
The character font is 5 x 7 (160 characters) or
5 x 11 (32 characters). The use of extended
ROM allows 8 x 16 (256 characters max.) to
be used.
Cursor Address Counter
The DR are registers used to store dot information such as character pitches and the
number of vertical dots, and so on. The
information sent from the MPU is written into
the DR via the DIR.
The MCR is a 6-bit register used to store the
data which specifies states of display such as
display on/off and cursor on/off/blink. The
information sent from the MPU is written in it
via the DIR.
The cursor address counter is a 16-bit counter
that can be preset by instruction. It holds an
address when the data of external RAM is
read or written (when display dot data or a
character code is read or written). The value
of the cursor address counter is automatically
increased by 1 after the display data is read or
written and after the set/clear bit instruction
is executed.
Cursor Signal Generator
Busy flag (BF)
The busy flag = 1 indicates the HD61830 is
performing an internal operation. Instructions cannot be accepted. As shown in Control Instruction, read busy flag, the busy flag
is output on DB7 under the conditions of RS =
1, R/W = 1, and E = 1. Make sure the busy flag
is 0 before writing the next instruction.
Dot Counters (DC)
The dot counters are counters that generate
liquid crystal display timing according to the
contents of DR.
The cursor can be displayed by instruction in
character mode. The cursor is automatically
generated on the display specified by the
cursor address and cursor position;
Parallel/Serial Conversion
The parallel data sent from the external RAM,
character generator ROM, or extended ROM
is converted into serial data by two parallel!
serial conversion circuits and transferred to
the liquid crystal driver circuits for upper
screen and lower screen simultaneously.
HITACHI
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HD61830
Terminal Functions
Name
Function
DBO-DB7
Data bus: Three-state I/O common terminal
Data is transferred to MPU through DBO to DB7
Chip select: Selectli'd state with CS = 0
R/W
Read/Write: R/W = 1: MPU .... HD61830
R/W = 0: MPU -+ HD61830
RS
Register select: RS = 1: Instruction register
RS = 0: Data register
E
Enable: Data is written at the fall of E
Data can be read while E is 1
CR. R.C
CR oscillator
MAO-MA15
External RAM address output
In character mode. the line code for external CG is output through MA 12 to MA 15
(0: Character 1st line. F: Character 16th line)
MDO-MD7
Display data bus: Three-state I/O common terminal
RDO-RD7
ROM data input: Dot data from external character generator is input
Reset: Reset = 0 results in display off. slave mode and Hp = 6
Write enable: Write signal for external RAM
Cl2
Display data shift clock for LCD drivers
Cll
Display data latch signal for LCD drivers
FlM
Frame signal for display synchronization
MA
Signal for converting liq~id crystal driving sign!!1 into AC. A type
MB
Signal for converting liquid crystal driving signal into" AC. B type
01.02
Display data serial output
01: For upper half of screen
02: For lower half of screen
CPO
Clock signal for HD61830 in slave mode
Synchronous !lignal for parallel operation
Three-state I/O common terminal (with pull-up MOS)
Master: Synchronous signal is output
Slave: Synchr()nous signal is input
HITACHI
.. Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
421
HD61830
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Supply voltage
Vee
- 0.3 to + 0.7
V
1,2
Terminal voltage
Vr
- 0.3 to Vee + 0.3
V
1.2
Operating temperature
Topr
- 20 to + 75
·c
Storage temperature
Tstg
- 55 to + 125
·c
. Notes: 1. All voltages are referenced to GND = 0 V.
2. If LSls are used beyond absolute maximum ratings, they may be perr,nanently destroyed. We
strongly recommend that you use the LSls within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
HITACHI
422
Hitachi America, Ltd. - Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD61830
Electrical Characteristics
(Vee
=5V ±
5 %, GND
=0
V, T.
=
- 20 to +75·C)
Item
Symbol
Min
Input high voltage (TIL)
VIH
Input low voltage (TIL)
Typ
Max
Unit
Test Condition
Note
2.2
Vee
V
VIL
0
0.8
V
2
Input high voltage
VIHR
3.0
Vee
V
3
Input high voltage (CMOS)
VIHe
0.7 Vee
Vee
V
4
Input low voltage (CMOS)
VILe
0
0.3 Vee
V
4
Output high voltage (TIL)
VOH
2.4
Vee
V
-loH = 0.6 mA
5
Output low voltage (TIL)
VOL
a
0.4
V
IOL = 1.6 mA
5
Output high voltage (CMOS)
VOHe
Vee - 0.4
Vee
V
-loH = 0.6 mA
6
Output low voltage (CMOS)
VOLe
a
0.4
V
IOL ';' 0.6 mA
6
Input leakage current
liN
- 5
5
",A
VIN = a-Vee
7
Three-state leakage current
hSL
- 10
10
",A
VOUT = O-Vce
8
Power dissipation (1)
Pw1
10
15
mW
CR oscillation
fosc = 500 kHz
9
Power dissipation (2)
Pw2
20
30
mW
. External clock
fcp = 1 MHz
9
Internal clock operation
----_.-.-.------------.-._---------------------------------------------------------------------------------------.------------------------------------_.
Clock oscillation frequency
fosc
400
500
External clock operation
-------------------------------.----------------.-------------------------_.-------
600
kHz
Cf =15 pF ± 5% 10
Rf = 39 kO ± 2%
--------------- --------------------------------------------------_.
External clock operating
frequency
fcp
100
500
1100
kHz
11
External clock duty
Duty
47.5
50
52.5
%
11
External clock rise time
t,cp
0.05
",s
11
External clock fall time
tfcp
0.05
",s
11
Pull-up current
IpL
20
",A
2
10
VIN = GND
12
Note: The I/O terminals have the following configuration:
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
423
HD61830
Input Terminal
Output Terminal
Applicabie terminai: es, E, RS, R/W, RES, CR
(Without pull-up MOS)
Appiicabie terminal: CL1, CL2, MA, MB, FLM,
CPO, D1, D2, WE, OE, CE, MAO-MA15
Vee
r1e
Vee
s
~~NM~
Applicable terminal: RDO-RD7 (With pull-up
MOS)
Vee
Vee
HITACHI
424
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD61830
I/O Common Terminal
Applicable terminal: DBO-DB7, SYNC (with
pull-up MOS), MDO-MD7 (without pull-up
MOS)
Vee
Vee
H
r----- ---1)t-i
Vee
(Pull-up MOS)
Enable
:PMOS
I
(Input circuit)
Data
I
:
~--------------~I
I
I
L ________
J
(Output circuit)
(Three state)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
~ied
to input terminals and I/O common terminals, except terminals SYNC, CR, and
RES.
Applied to input terminals and I/O common terminals, except terminals SYNC and CR.
Applied to terminal RES.
Applied to terminals SYNC and CR.
Applied to terminals OBO-OB7, WE, MAO-MA15, and MOO-M07.
Applied to terminals SYNC, CPO, FLM, CL1, CL2, 01,02, MA, and MB.
Applied to input terminals.
Applied to I/O common terminals. However, the current which flows into the output drive
MOS is excluded.
The current which flows into the input and output circuits is excluded. When the input of
CMOS is in the intermediate level, current flows through the input circuit, resulting in the
increase of power supply current. To avoid this, input must be fixed at high or low.
The relationship between the operating frequency and the power dissipation is given
below.
~ 50
.s
cl
/'
40
max
/'
/'
30
L
typ
...... V
~
/" ~
/' ~
20
10
0
~
,/~
.,?/
250
500
750
1000
1250
1500
fosdkHz)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
425
HD61830
1O. Applied to the operation of the internal oscillator when oscillation resistor Rf and oscillation
capacity Cf are used.
Cf= 15pF± 5%
R,=39kQ±2%
(when fosc=
500kHz typ)
.-------1 R
C
'----4---1 CR
The relationship among oscillation frequency,
Rf and Cf is given below.
Ta=25'C Vcc=5V
fosc (kHz)
800
\
\ \
600
\
'\.
"---"
.......
400
.............
........ r-
200
o
40
60
80
--100
120
C,= 10pF
C, = 15pF
140
160
180
R,(kQ)
11. Applied to external clock operation.
Open
R
Open
C
CR
0. 7Vcc
0. 5Vcc
0. 3Vcc
12. Applied to SYNC, 080-087, and ROO-R07.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830
Timing Characteristics
MPU Interface
Typ
Item
Symbol
Min
Enable cycle time
tCYC
1.0
ps
High level
twEH
0.45
ps
Low level
twEL
0.45
ps
Enable pulse width
Max
Unit
Enable rise time
tE,
25
ns
Enable fall time
tEf
25
ns
Setup time
tAS
140
ns
Data setup time
tosw
225
ns
Data delay time
225
tOOR
(Note)
ns
Data hold time
tH
10
ns
Address hold time
tAH
10
ns
Data hold time
tOH
20
ns
Note:
The following load circuit is connected for specification:
Vee
Test
point
R
RL=2.4kO
R =11kO
C "" 130pF
Diodes 0, to 0 4
:
1S2074HD61830)
DBo-DB7
(MPU-HD61830)
HITACHI
428
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1&19· (415) 589-8300
HD61830
External RAM and ROM Interface
Item
Symbol
SYNC delay time
toSY
SYNC pulse width
High level
Typ
Max
Unit
200
ns
twSY
900
ns
tccpo
900
ns
High level
twCPOH
450
ns
Low level
twCPOL
450
ns
CPO cycle time
CPO pulse width
Min
MAO to MA 15 refresh delay time \
tOMAR
200
ns
MAO to MA 1 5 write address delay time
tOMAW
200
ns
MOO to M07 write data delay time
tOMOW
200
ns
MOO to M07, ROO to R07 setup time
tSMO
900
ns
Memory address setup time
tSMAW
250
ns
Memory data setup time
tSMDW
250
ns
WE delay time
tOWE
WE pulse width (low level)
twwE
Notes:
200
450
ns
ns
1. No load is applied to all the output terminals.
2. "*" indicates the delay time of RAM and ROM.
HITACHI
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429
HD61830
LCD Driver Interface
Item
Symbol
Min
Clock pulse width (high level)
twCLl
450
Clock delay time
tOCL2
Clock cycle time
twCL2
900
ns
High level
twCH
450
ns
Low level
twCL
450
ns
Clock pulse width
Typ
Max
Unit
ns
200
ns
MA. MB delay time
tMO
300
ns
FLM delay time
tOF
300
ns
Data delay time
too
200
ns
Data setup time
tso
250
ns
Note: No load is applied to all the output terminals (MA. MB. FLM. 01. and 02).
CL1
CL2
MA. MB
FLM
D1
tOD-f--j4--
D2
HITACHI
430
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830
Display Control Instructions
Display is controlled by writing data into the
instruction register and 13 data registers. The
RS signal distinguishes the instruction register from the data registers. a-bit data is
written into the instruction register with RS
= 1, and the data register code is specified.
After that, the a-bit data is written in the
data register and the specified instruction is
executed with RS = O.
Register
During the execution of the instruction, no
new instruction can be accepted. Since the
busy flag is set during this, read the busy flag
and make sure it is 0 before writing the next
instruction.
1. Mode control
Code $"00" (hexadecimal) written into the
instruction register specifies the mode control register.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
0
0
0
0
Mode control reg.
0
0
0
0
Cursor/blink
DB5
DB4
DB3
DB2
DB1
DBO
I/O
I/O
0
0
0
0
Mode data
CG
Cursor off
(!)
0
1
Cursor on
1
0
Cursor off, character blink
1
1
Cursor blink
0
0
0
1
Cursor on
1
0
Cursor off, character blink
1
1
Cursor blink
0
0
1
u
Graphic/character
display
Character display
(Character mode)
fti
E
$
.E
Cursor off
(!)
1
0
u
fti
E
S
Graphic mode
~
:t::
0
"c:
0
>
!
1: Disp la y on
0: Display off
HITACHI
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431
HD61830
2. Set character pitch
Vp indicates the number of vertical dots per
character. Tne space between the verticallydisplayed characters is included in the
determination. This value is meaningful only
during character display (in the character
mode) and becomes invalid in the graphic
mode.
Hp indicates the number of horizontal dots
per character in display, including the space
between horizontally-displayed characters.
In the graphic mode, the Hp indicates the
number of bits of i-byte display data to be
displayed.
There are three Hp values (table 1).
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
0
0
0
1
Character pitch reg.
0
0
Register
Table 1
Hp
6
7
8
(Vp - 1) binary
0
(Hp - 1) binary
Hp Values
DB2
DB1
DBO
o
Horizontal character pitch
6
o
7
8
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830
3. Set number of characters
HN indicates the number of horizontal characters in the character mode or the number of
horizontal bytes in the graphic mode. If the
total sum of horizontal dots on the screen is
taken as n,
Register
n = Hp x HN
HN can be set to an even number from 2 to
128 (decimal).
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
.0
1
0
0
0
0
0
0
1
0
Number-of-characters reg.
0
0
0
4. Set number of time divisions (inverse
of display duty ratio)
Nx indicates the number of time divisions in
Register
R/W
Instruction reg.
0
N umber-of-time-divisions
reg.
0
RS
DB6
DB5
DB4
DB3
DB2
DBl
DBO
1
0
0
0
0
0
0
1
1
0
0
Cp indicates the position in a character
where the cursor is displayed in the character
mode. For example, in 5 x 7 dot font, the
cursor is displayed under a character by
specifying Cp = 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch Hp. A value of 1 to 16 (decimal)
R/W
RS
Instruction reg.
0
,
Cursor position reg.
0
0
(Nx - ') binary
can be set to Cpo If a smaller value than the
vertical character pitch Vp is set (Cp :;; Vp),
and a character overlaps with the cursor, the
cursor has higher priority of display (at cursor
display on). If Cp is greater than Vp, no cursor
is displayed. The cursor horizontal length is
equal to Hp.
DB7
DB6
DB5
DB4
DB3
0
0
0
0
0
0
0
0
0
6. Set display start low order address
Cause display start addresses to be written in
the display start address registers. The display start address indicates a RAM address at
which the data displayed at the top left end
on the screen is stored. In the graphic mode,
Register
multiplex display.
l/Nx is the display duty ratio.
A value of 1 to 128 (decimal) can be set to Nx.
DB7
5. Set cursor position
Register
(HN -1) binary
DB2
,
(Cp
-
')
DB'
DBO
0
0
binary
the start address is composed of high/lOW
order 16 bits.. In the character display, it is
composed of the lower 4 bits of high order
address (DB3 - DBa) and 8 bits of low order
address. The upper 4 bits of high order
address are ignored.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
1
0
0
0
Display start address reg.
(low order byte)
0
0
(Start low order address) binary
HITACHI
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433
HD61830
Set display start high order address
I",negist6i
.
I
"I\AI
n/yv
I
nil'"
n~
Instruction reg.
0
,
Display start address reg.
(high order byte)
0
0
I
"'n""t
LID I
0
I
I
LI
0
0
I
I
LIDO
0
I
LID.....
I
0
I
I
LID.;)
,
I
I
LID"
0
I
I
LJD I
0
I
I
ueu
,
(Start high order address) binary
7. Set cursor address (low order) (RAM
write low order address)
Cause cursor addresses to be written in the
cursor address counters. The cursor address
indicates and address for sending or receiving display data and character codes to or
from the RAM.
That is, data at the address specified by the
cursor address are read/written. In the character mode, the cursor is displayed at the
character specified by the cursor address.
address (8 bits) and the high-order address (8
bits). Satisfy the following requirements setting the cursor address (table 2).
The cursor address counter is a lS-bit upcounter with set and reset functions. When
bit N changes from 1 to 0, bit N + 1 is inclemented by 1. When setting the low order
address, the LSB (bit 1) of the. high order
address is inclemented by 1 if the MSB (bit 8)
of the low order address changes from 1 to O.
Therefore, set both the low order address and
the high order address as shown in the table
2.
A cursor address consists of the low-order
Register
R/W
RS
Instruction reg.
0
,
Cursor address counter
(low order byte)
0
0
DB7
DBS
DBS
DB4
0
0
0
0
DB3
,
DB2
0
,
DBO
DB'
DBO
DB'
0
(Cursor low order address) binary
Set cursor address (high order) (RAM write high order address)
Register
R/W
RS
Instruction reg.
0
,
Cursor address counter
(high order byte)
0
0
DB7
DB6
DBS
DB4
0
0
0
0
DB3
,
DB2
0
, ,
(Cursor high order address) binary
Table 2 Cursor Address Setting
Condition
Requirement
When you want to rewrite (set) both the low order
address and the high order address.
Set the low order address and then set the high
order address.
When you want to rewrite only the low order
address.
Don't fail to set the high order address again after
setting the low order address.
When you want to rewrite only the high order
address.
Set the high order address. You don't have to set
the low order address again.
HITACHI
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HD61830
8. Write display data
After the code $"OC" is written into the
instruction register with RS = 1, 8-bit data
with RS = 0 should be written into the data
register. This data is transferred to the RAM
specified by the cursor address as display
data or character code. The cursor address is
increased by 1 after this operation.
R/W
RS
DB7
DBS
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
1
1
0
0
RAM
0
0
Register
MSB (pattern data, character code) LSB
9. Read display data
Data can be read from the RAM with RS = 0
after writing code $"OD" into the instruction
register. Figure 1 shows the read procedure.
This instruction outputs the contents of data
output register on the data bus (DBO to DB7)
Register
and then transfers RAM data specified by the
cursor address .to the data output register,
also increasing the cursor address by 1. After
setting the cursor address, correct data is not
output at the first read but at the second one.
Thus, make one dummy read when reading
data after setting the cursor address.
R/W
RS
DB7
DBS
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
1
1
0
1
RAM
1
0
CS~~
MBS (pattern data, character code) LSB
__________________________________________
E
DB
B_ Curaor Curaor B_
check addraaa high
check.
set
ordor
ordor
mod. add....
add....
Busy
Cursor
~k
add.... low
lOt
mode
Cursor
write
Oata Dummy Busy N
read
check add....
read
data
mode
read
Busy N + 1
check add....
data
read
write
Cursor
address .
N
N+l
N+2
IN+3
Data
output
register
Figure 1 Read Procedure
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy: • Brisbane, CA 94005-1819 • (415) 589-8300
435
HD61830
10. Clear bit .
The clear/set bit instruction sets 1 Olt m a
byte of display data RAM to 0 or 1, respectively. The position of the bit in a byte is
specified by NB and RAM address is specified
by cursor address. After the execution of the
instruction, the cursor address is automatically increased by 1. NB is a value from 1 to 8.
NB = 1 and NB = 8 indicates LSB and MSB,
respectively.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
1
1
1
0
Bit clear reg.
0
0
0
0
0
0
0
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
1
1
1
1
Bit set reg.
0
0
0
0
0
0
0
Register
(NB - 1) binary
Set bit
Register
11. Read busy flag
When the read mode is set with RS = 1, the
busy flag is output to DB7. The busy flag is set
to 1 during the execution of any of the other
instructions. After the execution, it is set to O.
The next instruction can be accepted. No
instruction can be acceped when busy flag =
1. Before executing an instruction or writing
data, perform a busy flag check to make sure
Register
R/W
RS
DB7
Busy flag
1
1
I/O
(NB - 1) binary
the busy flag is O. When data is written in the
register (RS = 1), no busy flag changes. Thus,
no busy flag check is required just after the
write operation into the instruction register
with RS = 1.
The busy flag can be read without specifying
any instruction register.
DB6
I DB5 I DB4 I DB3 I DB2 I DBl
lOBO
HITACHI
436
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD61830
t---------HN (digit)--------!
Symbol Nama
Meaning
Value
H~
Horizontal character pitch
Horizontal character pitch
6 to 8 dots
HN
Number of horizontal
characters
Number of horizountal characters per line (number 2 to 128 digits
of digits) in the character mode or number of bytes (an even number)
per line in the graphic mode.
Vp
Vertical character pitch
Vertical character pitch
1 to 16 dots
Cp
Cursor position
Line number on which the cursor can be. displayed
1 to 16 lines
Nx
Number of time divisions
Inverse of display duty ratio
1 to 128 lines
Note: If the number of vertical dots on the screen is m, and the number of horizontal dots is n,
1/m = 1/Nx = display duty ratio
n = Hp x HN, m/Vp = Number of display lines
Cp :ii Vp
Figure 2
Display Variables
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
437
.".
c..>
ex>
Display Mode
Display Data
from MPU
Character
display
Character code
(8 bits)
:J:
s:
=->
n
b7 be bs b4 b 3 b2 b, bo
3
,, .,, ,, ,,, ,, ,
, , , , ,,
,
I
I
CD
::l.
n
P'
a
I
I
:J:
s=
Start
address
n
=-
-c
;;;
....c :I:
Liquid Crystal
Display Panel
RAM
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-=
1ft
'0
.. C
A
B
f
C
CD
0111010101 0 10 11
~ 011101010101 110
N
,
,
I
I
I
D>
I
N
I
I
I
I
, .,,
•
I
0
0
0
I
I
I
t
I
I
I
I
I
I
I
,, , , ,
I
.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
..
I
I
I
I
I
I
Hp : 6, 7, or 8 dots
en
iii'
;a :I
~
~
a
-c 0
~ :I
-c
0
.
Graphic
Display pattern
(8 bits)
bo
CP
::l.
b 7 b 6 b s b 4 b 3 b 2 b, bo
en
0-
I
I
D>
~
51>
(")
>
'R
0
0
'i;.
~
<0
~
~
01
ex>
<0
Co
c..>
0
0
Start
address
--
,
I
,,
I
I
.,
,
,, ,, , ,,
,
, ,, , . ., ,,
,,
,,,
,
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,
Hp
b7 1
I
I
8 dots
8 dots
I
011101110111 0 11
111111111J11111
, , , , ,
,
I
I
I
I
,
I
I
I
I
,
I
i
I
I
I
I
I
I
I
I
I
I
.
I
I
I
I
~
I
I
I
I
I
I
,
I
I
I
I
I
Hp : 8 dots
tJ
m
~
00
c.u
o
HD61830
Internal Character Generator Patterns and Character Codes
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane,CA 94005-1819· (415) 589-8300
439
.".
.".
0
~
'tS
:J:
n
-
Sf
n
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~
H061830
H06800
~
CD
J"
A12
A'3
A'4
A,s
VMA
Do
!::
!=>-
•
:J:
s=
n
~
-0
I»
·
07
N
0
0
0
t/>2
en
R/W
CD·
~
iil
t~
CS
S
I
J:
en
Open:
cr
I»
::::I
:0
Vcc -
01
FlM
MB
Cll
Cl2
02
MA
SYNC
CPO
RES
C")
»
<0
.".
0
0
R
':!;.
~
<0
~
~
U1
00
cp
00
c.>
0
0
+5V
GNO
-5V
WE
Ao
I
OE
RAM(2)
HM6116
AlQ
::s
t!- r
0
f-r-
...~
...
f
CS
T
....
CD
Ilo
!'
Ao- A 2
A
...,
R07
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t
M0 7
ROo
CD
L
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Do
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07
I.zJ
-v.
I
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J:
:::I.
OE~
I
a 0~
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L...."
WE
Ao RAM(1)
I
HM6116
AlQ _
CS
MA'4
MA'5 j---.
MOo
OB7
E
-0
0
-0
I
MA"
MA'2
OBo
I
6r
N
WE
MAo
I-I
MAIO
RS
Ao
:::I.
n
::.
0
ROM
HN462716
e.
CE
~Fi
f-- Open
CR
l,~C1
"9
;
A 3 -AlQ
Y
C'l
01
FlM
MB
Cll
Cl2
02
+5V
GNO
-5V
,Vo
p
C'l
::r
LCD Module
lM 200
~
I»
...
n
...CD
I'Ij
0
...
::s
CO
X
CO
:r:0
en
~
(X)
w
0
HD61830
Application 2 (Graphic Mode)
1----------·------81
NI
I - ...
...
I
r-C>
C>
:;
:;
-..
I
I
I
I
I,
,
I
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:J:
:J:
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-
0
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iI
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....I
:J:
:J:
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I
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g
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f-o ...:;
t- :J:o
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:J:
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il u "> I-r- ~H· ~
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r--
~r--
r
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L---- I----
~-------- t - - - - -
-- t- I -IH~
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u~
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0
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0
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:2
«a::
:2
.~
~
co
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5"
LO
C
~
5"
LO
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w
~
C/l
0
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u
~
0
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I~~I~
0
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0
8
:8:;)
OD..
:r::2
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
441
HD61830
Configuration Examples
Graphic Mode
Liquid crystal
display module
Character Mode (1) (Internal Character Generator)
Liquid crystal
display module
Character Mode (2) (External Character Generator)
liquid crystai
display module
Parallel Operation
Liquid crystal
Liquid crystal
display module (1) display module (2)
Driving both of two
module by same
common signal
HITACHI
442
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830B-----------LCTC (LCD liming Controller)
Pin Arrangement
Description
The HD61830B is a dot matrix liquid crystal
graphic display controller LSI that stores the
display data sent from an 8-bit microcontroller in the external RAM to generate dot
matrix liquid crystal driving signals.
It has a graphic mode in which 1-bit data in
the external RAM' corresponds to the on/off
state of 1 dot on liquid crystal display and a
character mode in which characters are displayed by storing character codes in the
external RAM and developing them into the
dot patterns with the internal character
generator ROM. Both modes can be provided
for various applications.
The HD61830B is produced by the CMOS
process. Thus, combined with a CMOS microcontroller it can complete a liquid crystal
display device with lower power dissipation.
...
N
N
N
N
N
(Top View)
(FP-60)
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dot matrix liquid crystal graphic display
controller
Display control capacity
-Graphic mode: 512k dots (216 bytes)
-Character mode: 4096 characters (212
characters)
Internal character generator ROM: 7360
bits
-160 types of 5 x 7 dot characters
-32 types of 5 x 11 dot characters
Total 192 characters
-Can be extended to 256 characters (4k
bytes max.) by external ROM
Interfaces to 8-bit MPU
Display duty cycle (Can be selected by a
program)
Static to 1/128 duty cycle
Various instruction functions
-Scroll, Cursor on/off/blink, Character
blink, Bit manipulation
Display method: Selectable A or B types
Operating frequency: 2.4 MHz
Low power dissipation
Power supply: Single +5 V ± 10%
CMOS process
Package: 60-pin plastic OFP (FP-60)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
443
....
........
b:I
g :r:mt1
...tj oW
II;"
::c
s=
SYNC Cl, MA MB FlM
(')
2:
ID
»
'a
3CD
:::!.
B
Fl
!:;
!"'-
::c
;::;:
'"2:
(')
DB o - DB 7
iSS
-0
~
•
N
0
0
0
RS
R/W
RES
II
I
RAM
8
II IIi ,._J~~:=MD7
I
1
*'
I
J1
~
i _.
Extended
I L -f external
!
6
,
i
L ROM
I
iil :I
I
CD'
Mode
a 0~
~
g-m
c: c:
-0
.-
~ :I
control
register
I
I
--r---~
en
I
-1-----...1
RDo-RD7
(MCR)
00l
U'(ij
2;'
• D,
c;;'
er
'"
::I
5"
1---+--~D2
C")
»
....
'!:.
0
0
~
Cl2
CR
:::
~
0"1
00
do
w
0
0
~
Q)
CE
*When extended external ROM is used, MAo -MA I1 are
applied to RAM, MA'2-MA'5 are applied to extended
external ROM.
OJ
HD61830B
Block Functions
Registers
Refresh Address Counters (RAC1/RAC2)
The HD61830B has the five types of registers:
instruction register (IR), data input register
(DIR), data output register (DaR), dot regis- ;
ters (DR), and mode control register (MCR).
The refresh address counters RAC1 and RAC2
control the addresses of external RAM, character generator ROM (CGROM), and
extended external ROM The RAC1 is used for
upper half of the screen and the RAC2 for the
lower half. In the graphic mode, 16-bit data
is output and used as the address signal of
external RAM. In the character mode, the
high order 4 bits (MA12-MA15) are ignored.
The 4 bits of line address counter iU'e output
instead and used as the addresS' of extended
ROM.
The IR is a 4-bit register that stores the
instruction codes for specifying MCR, DR, a
start address register, a cursor address register, and so on. The lower order 4 bits DBO to
DB3 of data buses are written in it.
The DIR is an 8-bit register used to temporarily store the data written into the external
RAM, DR, MCR, and so on.
The DaR is an 8-bit register used to temporarily store the data read from the external
RAM. Cursor address information is written
into the cursor address counter (CAC)
through the DIR. When the memory read
instruction is set in the IR (latched at the
falling edge of E segnal), the data of external
RAM is read to DaR by an internal operation.
The data is transferred to the MPU by reading
the DaR with the next instruction (the contents of DaR are output to the data bus when
E is at the High level).
The DR are registers used to store dot information such as character pitches and the
number of vertical dots and so on. The information sent from the MPU is written into the
DR via the DIR.
The MCR is a 6-bit register used to store the
data which specifies states of display such as
display on/off and cursor on/off/blink. The
information sent from the MPU is written in it
via the DIR.
The busy flag = 1 indicates the HD61830B is
performing an internal operation. Instructions cannot be accepted. As shown in Control Instruction, read busy flag, the busy flag
is output on DB7 under the conditions of RS =
1, R/W = 1, and E = 1. Make sure the busy
flag is 0 before writing the next instruction.
Coun~ers
The character generator ROM has 7360 bits in
total and stores 192 types of character data. A
character code (8 bits) from the external RAM
and a line code (4 bits) from the line address
counter are applied to its address signals, and
it outputs 5-bit dot data.
The charater font is 5 x 7 (16() characters) or
5 x 11 (32 characters). The use of extended
ROM allows 8 x 16 (256 characters max.) to
be used.
Cursor Address Counter
The cursor address counter is a 16-bit counter
that can be preset by instruction. It holds an
address when the data of external RAM is
read or written (when display dot data or a
character code is read or written). The value
of the cursor address counter is automatically
increased by 1 after the display data is read or
written and after the set/clear bit instruction
is executed.
Cursor Signal Generator
Busy Flag (BF)
Dot
Character Generator ROM
(DC)
The dot counters are counters that generate
liquid crystal display timing according to the
contents of DR.
The cursor can be displayed by instruction in
character mode. 'I'he cursor is automatically
generated on the display specified by the
cursor address and cursor position.
Parallel/SerialConversion .
The parallel data sent from the external RAM,
character generator ROM, or extended ROM
is converted into serial data by two parallel/
serial conversion circuits and tranSferred to
the liquid crystal driver circuits for upper
screen and lower screen simultaneously.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
.------.-....
.•.. ...-.
-.-.~-
.~,.,
445
HD61830B
Terminal Functions
Name
Function
DBO-DB7
Data bus: Three-state I/O common terminal
Data is transferred to MPU through DBO to DB7.
Chip select: Selected state with CS = 0
R/W
Read/Write: R/W = 1: MPU +- HD61830B
R/W = 0: MPU .,.. HD61830B
RS
Register select: RS = 1: Instruction register
RS = 0: Data register
E
Enable: Data is written at the fall of E
Data can be read while E is 1
CR
External clock input
Reset: RES = 0 results in display off, slave mode and Hp = 6
MAO-MA15
External RAM address output
In character mode, the I,me code for external CG is output
through MA12 to MA15 (0: Character 1st line,
F: Character 16th line)
MDO-MD7
Display data bus: Three-state I/O common terminal
RDO-RD7
ROM data input: Dot data from external character generator is input
Write enable: Write signal for external RAM
Cl2
Display data shift clock for LCD drivers
CL1
Display data latch signal for LCD drivers
FlM
Frame signal for display synchronization
MA
Signal for converting liquid crystal driving signal into AC, A type
MB
Signal for converting liquid crystal driving signal into AC, B type
01,02
Display data serial output
01: For upper half of screen
02: For lower half of screen
Synchronous signal for parallel operation
Three-state I/O common terminal (with pull-up MOS)
Master: Synchronous signal is output
Slave: Synchronous signal is input
Chip enable
CE = 0: Chip enables make external RAM in active
Output enable
OE = 1: Output enable informs external RAM that HD61830B requires data bus
NC
Unused terminal. Don·t connect any wires to this terminal
HITACHI
446
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
HD61830B
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Supply voltage
Vee
- 0.3 to + 0.7
V
1,2
Terminal voltage
Vr
- 0.3 to Vee + 0.3
V
1, 2
Operating temperature
Topr-
- 20 to + 75
'C
Storage temperature
Tstg
- 55 to + 125
'C
Notes:
1. All voltage is referred to GNO = 0 V.
2. If LSls are used beyond absolute maximum ratings, they may be permanently destroyed. We
strongly recommend that you use the LSls within electrical characteristic limits for normal
operation, because use beyond these conditions will cause malfunction and poor reliability.
Electrical Characteristics
ltam
Symbol
Min
Input high voltage (TTL)
VIH
Input low voltage (TTL)
Unit
2.2
Vee
V
VIL
o
0.8
V
2
Input high voltage
VIHR
3.0
Vee
V
3
.Input high voltage (CMOS)
VI He
0.7 Vee
Vee
V
4
Input low voltage (CMOS)
VILe
o
0.3 Vee V
4
Output high voltage (TTL)
VOH
2.4
Vee
V
- 10H
Output low voltage (TTL)
VOL
o
0.4
V
10L
Output high voltage (CMOS)
VOHe
Vee - 0.4
Vee
V
- 10H
Output low voltage (CMOS)
VOLe
o
0.4
V
101 = 0.6 mA
6
Input leakage current
hN
-5
5
JlA
VIN = O-Vee
7
Three-state leakage current
ITSL
- 10
10
JlA
VOUT
Pull-up current
IPL
2
20
JlA
Vin
Power dissipation
Pw
50
mW
External clock
fop = 2.4 MHz
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
10
Test Condition
Note
Max
Notes:
Typ
= 0.6 mA
= 1.6 mA
= 0.6 mA
= O-Vee
= GNO
5
5
-6
I
8
9
10
~ied
to input terminals and I/O common terminals, except terminals SYNC, CR, and
RES.
Applied to input terminals and I/O cOmmon terminals, except terminals SYNC and CR.
Applied to terminal RES.
Applied to terminals SYNC and C~
_
_
Applied to terminals OBO-OB7, WE, MAO-MA15, OE, CE, and MOO-M07.
Applied to terminals SYNC, FLM, CL1, CL2, 01, 02, MA, and MB.
Applied to input terminals.
Applied to I/O common terminals. However, the current which flows into the output drive
MOS is excluded.
Applied to SYNC, OBO-OB7, and ROO-R07.
The current which flows into the input and output circuits is excluded. When the input of
CMOS is in the intermediate level, current flows through the input circuit, resulting in the
increase of power supply current. To avoid this, input must be fixed at high or low.
HITACHI
Hitachi America, Ltd. ·~itachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
447
HD61830B
Input Terminal
Applicable terminal: CS, E, RS, R/W, RES, CR
(Without pull-up MOS)
Applicable terminal: RDO-RD7 (With pull-up
MOS)
Vee
Vee
Vee
Output Terminal
Applicable terminal: CL1, CL2, MA, MB, FLM,
01, D2, WE, OE, CE, MAO-MA1S
.
Vec
r1C
Y~NM~
I/O Common Terminal
Applicable terminal: DBO-DB7, SYNC, MDOMD7 (MDO - MD7 have no pull-up MOS)
Vee
H
(Pull-up MOS)
Vee
PMOS
t----i
NMOS
r-----
Vee
---j--Enable
:PMOS
I
If-I.
: .
I
(Input circuit)
~--------------~I
I
L ________
Data
I
I
I
JI
(Output circuit)
(Three state)
HITACHI
448
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830B
Clock Operation
Item
Symbol
Min
External clock operating
frequency
fcp
100
External clock duty
Duty
47.5
External clock rise time
Typ
Max
Unit
2400
kHz
52.5
%
t rcp
25.0
ns
External clock fall time
tfcp
25.0
ns
SYNC output hold time
tHSYO
SYNC output delay time
toSY
SYNC input hold time
tHSYI
SYNC input set-up time
tSSY
Notes:
50
30
210
10
180
Note
ns
2,3
ns
2, 3
ns
2
ns
2
1. Applied to external clock input terminal.
lj
0. 7Vcc
0. 5Vcc
0. 3Vcc
lj
Duty cycle = ~ x 100%
'h+'1
2. Applied to SYNC terminal.
CR
I
SYNC
(Output:
at master mode)
~__t~sS~y__-+t~H~SYI~__t~SS~Y__~
0. 3Vcc
(Input: at slave mode)
3. Testing load circuit.
1
Test 0 - - - - - .
point
IC
L
CL = 30pF
(C L includes iig capacitance)
HITACHI
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HD61830B
MPU Interface
Item
Symbol
Min
Enable cycle time
tCYC
1.0
ps
High level
twEH
0.45
ps
Low level
twEL
0.45
ps
Enable pulse width
Typ
Max
Unit
Enable rise time
tEr
25
ns
Enable fall time
tEt
25
ns
Setup time
tAS
140
ns
Data setup time
tosw
225
ns
Data delay time
tOOR
Data hold time
tOHW
10
ns
Address hold time
tAH
10
ns
Data hold time
tOH
20
ns
Note:
225
ns (Note)
The following load circuit is connected for specification:
eye
tWEH
tWEL
2.2V
E
t~
CS, R/W, RS
=>
/
\
O.BV /
tEf-
I--tEr
r-- tAH
~
2.2V
O.BV
~
tOHW
~
~
DBo-DB7
(MPU~HD61B30B)
2.2V
O.BV
tOOR
J
DBo-DB7
(MPU~HD61B30B)
2.4V
O.4V
}~
~
K
Vee
D1
Test
point
RL
D2
R
D3
D4
RL=2.4kQ
R = 11 kQ
C = 130 pF (C includes iig capacitance)
Diodes D1 to D4: 1S2074@
HITACHI
450
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD61830B
External RAM and ROM Interface
Max
Unit
Note
300
ns
1,2,3
ns
1, 2, 3
ns
1,2,3
ns
1,2, 3
ns
1, 3
ns
1, 3
ns
1, 3
ns
1, 3
ns
1, 3
150
ns
1, 3
tZMOF
10
ns
1, 3
MD output high impedance
time (2)
tZMOR
50
ns
1, 3
RD data set-up time
tSRo
50
ns
2
RD data hold time
tHRO
40
ns
2
MD data set-up time
tSMO
50
ns
2
M D data hold time
tHMO
40
ns
2
Item
Symbol
MAO - MA 15 delay time
tOMA
MAO-MA15 hold time
tHMA
CE delay time
tOCE
CE hold time
tHCE
DE delay time
tOOE
DE hold time
tHOE
MD output delay time
tOMO
MD output hold time
tHMOW
WE delay time
towe
WE clock pules width
twwe
MD output high impedance
time (1)
Notes:
1. RAM
Typ
Min
40
300
40
300
40
150
10
150
write timing
T1
T2
T3
T1
CR
....______________~~~_r~--r_~IO.6V
tOMA
tHMA
2.4V
O.6V
tOOE
tHOE
2.4V
O.6V
MDo-MD7 _____________(~H~ig~h_i_m~p_ed_a_n_ce~)________~~~
(Output)
~=~i-Jr
T1: Memory data refresh timing for upper screen
T2: Memory data refresh timing for lower screen
T3: Memory read/write timing
HITACHI
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451
HD61830B
Notes: 2. ROM/RAM read timing
T,
T,
CR
I
('2) I
('2)
~~--~~------~--------
0.6V-+--------------------~~--------_*----------+r-------tOMA
tHMA
Address for upper screen
2.2V
0.8V
MD o -MD 7
(Input)
Data for the upper screen
tSRO
2.2V
lower .screen
0.8V
*1
This figure shows the timing for Hp = 8. .
..
For Hp = 7, time shown by Hb becomes zero. For Hp = 6, time shown by Ha and Hb H
become zero.
Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of Hp =
8, Hp = 7, or Hp = 6 respectively.
.
2 The waveform for instructions with memory read is shown with a dash line. In other cases,
the Waveform shown with a solid line is generated.
3 When an instruction with RAM read/write is excuted, the value of cursor address is
output. In other cases, invalid data is output.
4 When an instruction with RAM read is excuted, HD61830B latches the data at this timing.
In other cases, this data is invalid.
R
*
*
*
R
3. Test load circuit
Vee
Test
point
R
RL =2.4kO
R =J1 kQ
C '7'50 pF (C includes jig capacitance)
Diodes 0, to 0 4 : 1S2074®
HITACHI
452
Hitachi America, ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830B
LCD Driver Interface
Unit
Note
416
ns
1, 3
tWCH
150
ns
1,3
Clock pulse width
(Low level)
tWCL
150
ns
1, 3
Data delay time
too
ns
1, 3
Data hold time
tOH
100
ns
1,3
Clock phase difference (1)
tCL1
100
ns
1, 3
Clock phase. difference (2)
tCL2
100
ns
1,3
Clock phase difference (3)
tCL3
100
ns
1, 3
MA, MB delay time
tOM
-200
ns
1, 3
FLM set-up time
tSF
400
ns
2, 3
FLM hold time
tHF
1000
ns
2, 3
MA set-up time
tSMA
400
ns
2, 3
MA hold time
tHMA
1000
ns
2, 3
Item
Symbol
Min
Clock cycle time
tWCL2
Clock pulse width
(High level)
Typ
Max
50
200
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
453
HD61830B
Notes:
1.
tWCl2
tWCH
-.I
II'
tWCL
I
\;
0.7Vcc
0.3Vcc
\
tCLl
to.7VCC
0.3Vcc
Cl,
tWCH
tDH
too
) I'
tCL3
tCl2
0.7Vcc
0.3Vcc
tOM
).
MA,MB
0.7Vcc
0.3Vcc
2.
0.7Vcc
I\- 0.3Vcc
Cl,
I
tSF
FlM
)
tHF
0.7Vcc
0.3Vcc
\
tSMA
tHMA
I
to.7Vcc
"1
0. 3VCC
MA
3. Test load circuit
Test
point
0-----,
~
;J;
Cl
Cl = 100 F (C L includes ii 9 )
p
capacitance
HITACHI
454
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830B
Display Control Instructions
Display is controlled by writing data into the
instruction register and 13 data registers. The
RS signal distinguishes the instruction register from the data registers. 8-bit data is
written into the instruction register with RS
= 1, and the data register code is specified.
After that, the 8-bit data is written in the
data register and the specified instruction is
exe.cuted with RS = O.
During the execution of the instruction, no
new instruction can be accepted. Since the
busy flag is set during this, read the busy flag
and make sure it is 0 before writing the next
instruction.
1. Mode control
Code $"00" (hexadecimal) written into the
instruction register specifies the mode control register.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
Instruction reg.
0
1
0
0
0
0
0
0
0
0
Mode control reg.
0
0
0
0
Cursor/blink
Register
DB5
DB4
DB3
DB2
DBl
DBO
I/O
I/O
0
0
0
0
Mode data
CG
Cursor off
(!)
0
1
Cursor on
1
0
Cursor off, Character blink
1
1
Cursor blink
0
0
0
1
Cursor on
1
0
Cursor off, character blink
1
1
Cursor blink
0
0
Graphic/character
display
Character display
(Character mode)
u
(ij
E
j!l
..s:
1
Cursor off
(!)
u...
u...
0
"-
z
0
>
-a
Ci'"
1
0
...
~
.,~
.,~
~
!l.,
~
(!)
.c.
0
iii
.:.I.
5
iii
u
~
.S
:::l
I
(ij
E
j!l
~
/
I
Graphic mode
U
"0
:E
-------
u
..;
c:
Q.-o
"-
(!)E
LU
Q)
~ 0
>i
1: Master mode
0: Slave mode
-+
1: Display ON
0: Display OFF
HITACHI
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455
HD61830B
2. Set character pitch
Vp indicates the number of vertical dots per
character. The space het\'V'een the vsr+..ically..
displayed characters is considered for
determination. This value is meaningful only
during character display (in the character
mode) and becomes invalid in the graphic
mode.
Hp indicates the number of horizontal dots
per character in display, including the space
between horizontally-displayed characters.
In the graphic mode, the Hp indicates the
number of bits of 1-byte display data to be
displayed.
There are three Hp values (Table 1).
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
0
0
0
1
Character pitch reg.
0
0
Register
(Vp - 1) binary
IHp - 1) binary
0
3. Set number of characters
HN indicates the number of horizontal characters in the character mode or the number of
horizontal bytes in the graphic mode. If the
total sum of horizontal dots on the screen is
taken as n,
n = Hp x HN
HN can be set to an even number from 2 to
128 (decimal).
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
0
0
1
0
Number-of-characters reg.
0
0
0
Register
Table 1
. Hp
6
7
8
(HN -1) binary
Hp Values
DB2
DB1
DBO
o
Horizontal character pitch
6
o
7
8
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD6183QB
4. Set number of time divisions (inverse
of display duty ratio)
ratio.
Nx indicates the number of time divisions in
multiplex display. l/Nx is the display duty
A value of 1 to 128 (decimal) can be set to Nx.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instrl,lction reg.
0
1
0
0
0
0
0
0
1
1
Number-of-time shares reg.
0
0
0
Register
5. Set cursor position
Cp' indicates the position in a character
where the cursor is displayed in the character
mode. For example, in 5 x 7 dot font, the
cursor is displayed under a character by
specifying Cp = 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch Hp. A value of 1 to 16 (decimal)
Register
(Nx - 1) binary
can be set to Cpo If a smaller value than the
vertical character pitch Vp is set (Cp ~ Vp),
and a character overlaps with the cursor, the
cursor has higher priority of display (at cursor
display on). If Cp is greater than Vp, no cursor
is displayed. The cursor horizontal length is
equal to Hp.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
0
1
0
0
Cursor position reg.
0
0
0
0
0
0
6. Set display start low order addres
Cause display start addresses to be written in
the display start address registers. The display start address indicates a RAM address at
which the data displayed at the top left end
on the screen is stored. In the graphic mode,
Register
(C p
-
1) binary
the start address is composed of high/low
order 16 bits. In the character display, it is
composed of the lower 4 bits of high order
address (DB3-DBo) and 8 bits of low order
address. The upper 4 bits of high order
address are ignored.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
1
0
0
0
Display start address reg.
(low order byte)
0
0
(Start low order address) binary
Set display start high order address
Register
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
1
0
0
1
Display start address reg.
(high order byte)
0
0
(Start high order address) binary
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
457
HD61830B
7. Set cursor address (low order) (RAM
write low order address)
Cause cursor addresses to be vvritteu iil the
cursor address counters. The cursor address
indicates an address for sending or receiving
display data and character codes to or from
the RAM.
That is, data at the address specified by the
cursor address are read/written. In the character mode, the cursor is displayed at the
character specified by the cursor address.
address (8 bits) and the high-order address (8
bits). Satisfy the following requirements
when setting the cursor address Crable 2).
The cursor address counter is a 16-bit upcounter with set and reset functions. When
bit N changes from 1 to 0, bit N + 1 is incremented by 1. When setting the low order
address, the LSB (bit 1) of the high order
address is added by 1 if the MSB (bit 8) of the
low order address changes from 1 to O.
Therefore, set both the low order address and
the high order address as shown in table 2.
A cursor address consists of the low-order
Register
Instruction reg.
Cursor address counter
(low order byte)
R/W
RS
DB7
DB6
0
1
0
0
0
DB5
DB4
DB3
DB2
DB1
DBO
0
0
1
0
1
0
(Cursor low order address) binary
0
Set cursor address (high order) (RAM write high order address)
Register
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
1
0
1
1
Cursor address counter
(high order byte)
0
0
(Cursor high order address) binary
Table 2· Cursor Address Setting
Condition
Requirement
When you want to rewrite (set) both the low order
address and the high order address.
Set the low order address and then set the high
order address.
When you want to rewrite only the low order
address.
Don't fail to set the high order address again after
setting the low order address.
When you want to rewrite only the high order
address.
Set the high order address. You don't have to set
the low order address again.
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD61830B
8. Write display data
After the code $"OC" is written into the
instruction register with RS = 1, 8 bit data
with RS = 0 should be written into the data
Register
register. This data is transferred to the RAM
specified by the cursor address as display
data or character code. The cursor address is
increased by 1 after this operation.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBa
Instruction reg.
a
1
a
a
0
a
1
1
a
0
RAM
0
a
MSB (pattern data, character code) LSB
9. Read display data
Data can be read from the RAM with RS = 0
after writing code $"OC" into the instruction
register. Figure 1 shows the read procedure.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBa
Instruction reg.
0
1
a
0
0
a
1
1
a
1
RAM
1
0
Register
MBS (pattern data, character code) LSB
This instruction outputs the contents of data
output register on the data bus (DBO to DB?)
and then transfers RAM data specified by the
cursor address to the data output register,
also increasing the cursor address by 1. After
CS-'~
setting the cursor address, correct data is not
output at the first read but at the second one.
Thus, make one dummy read when reading
data after setting the cursor address.
_________________________________________
E
---II__-.JIl. . . _-----'1LJ
R/W
RS
DB
Busy
Busy Cursor Cursor
check
check address low
order
set
address
mode
Cursor
address
Cursor
address
set
mode
Cursor Busy
high
check
order
address
Data Dummy
read
read
mode
Busy N
Busy
check address check
data
read
N+ 1
address
data
read
write
write
N+l
N
I
Data
output
register
N address
Figure 1
N+2
IN+3
datal ~a~a1 address IN + 2 ...
Read Procedure
HITACHI
Hitachi America, Ltd. • Hitachi Plaza ·2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589c8300
459
HD61830B
10. Clear bit
The clear/set bit instruction sets 1 bit in a
byte of display data RoA.M to 0 or 1, respectively. The position of the bit in a byte is
specified by NB and RAM address is specified
by cursor a'ddress. After the execution of the
instruction, the cursor address is automatically i..creased by 1. NB is a vai.ue from 1 io 8.
NB = 1 and NB = 8 indicates LSB and MSB,
respectively.
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
Instruction reg.
0
1
0
0
0
0
1
1
1
0
Bit clear reg.
0
0
0
0
0
0
0
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
Instruction reg.
0
1
0
0
0
0
1
1
Bit set reg.
0
0
0
0
0
0
0
Register
INa - 1) binary
Set bit
Register
11. Read busy flag
When the read mode is set with RS = 1, the
busy flag is output to DB7. The busy flag is set
to 1 during the execution of any of the other
instructions. After the execution, it is set to O.
The next instruction can be accepted. No
instruction can be accepted when busy flag
= 1. Before executing an instruction or writing data, perform a busy flag check to make
Register
R/W
RS
DB7
Busy flag
1
1
I/O
'DB1
1
DBO
1
INa - 1) binary
sure the busy flag is o. When data is written
in the register (RS = 1), busy flag doesn't
change. Thus, no busy flag check is required
just after the write operation into the
instruction register with RS = 1.
The busy flag can be read without specifying·
any instruction register.
DB6 lDB5
I DB4 I DB3 I DB2 I DB1 I DBO
*
HITACHI
460
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61830B
x
z
8888··
.000
00
00
00
.000.000
0 ••• 0000
00000000
--'--"""00 0000
~--------------HN--------------~
(digit)
Symbol Name
Meaning
Value
6 to 8 dots
Hp
Horizontal character fitch
Horizontal character pitch
HN
Number of horizontal
characters
Number of horizontal characters per line (number of 2 to 1 28 digits
digits) in the character mode or number of bytes per (an even numline in the graphic mode
ber)
Vp
Vertical character pitch
Vertical character pitch
1 to 16 dots
Cp
Cursor position
Line number on which the cursor can be displayed
1 to 16 lines
Nx
Number of time divisions
Inverse of dispqay duty ratio
1 to 128 lines
Note: if the number of vertical dots on the screen is m, and the number of horizontal dots is n,
1/m = l/Nx = display duty ratio
n = Hp x HN, m/Vp = Number of display lines
Cp
;;;
Vp
Figure 2
Display Variables
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
461
"""
~
from MPU
Character
display
Character code
(8 bits)
Display Panel
RAM
:r:
~
=-l>
.a 8
tJ
Liquid Crystal
Display Data
Dieplay Mode
l :=
Ii:
~.
$l
~
:r:
Start
/
address
=-J;!
.&j
•
o
g
N
en
~. :::t
Dl _
~il
:;; 0
.i ~
.
Graphic
~
Display pattern
(8 bits)
IX!
b 7 bo bs b4 b3 b2 b , bo
~.
en
,
:if
::::J
ii'
r
I
I
I
I
50
~
r
i!
~
.!.
!:2
co
~
~
&:
i
~
00
W
8.CD ~
3
CD
Sf
n
m
i
bo
b 71
8 dots I 8 dots
Start
address
r
I
I
I
r.
Hp
,
Hp: 8 dots
HD61830B
Internal Character Generator Patterns and Character Codes
~
bits
igher
Lower
0010001101000101011001111010101111001101 11101111
··..i···.....
4 bits
x x x xOOOl
-,
fWw. ...,
:
i.... ....:
••••; : a.- __
••••mu
; __
••• : .
1-;
.
~L-~~~~-uuu
~
ii.···.:···.:···.:
X X X
x0010
••••
~
x x x x0011
xxxxOl00
i···: S·::- 1···1
I··
xxxXl000
X X X x 1001
~
•••••
=
••:
-:::5
: II···· I····
•••:.•••• ••••
••••
.i.!. ..::-
-I-a-
le:.·.1
i:::i
.::1.·.. :1:::
• .::•••••
·...·....
...
:: ::
·.
1:::- :
: :
i.L_::__
-1
.
.:...
I... • .i. ..1.·.. .
::
i...· ...
.......
..
.
.
. .I •••. ......
.... ........... ...... ......: I.••...i. ..•..
I. I ····1 E.: I :.. ··i·· :.:
•-1·· ••-1 i
.:1:' •••;- :
.wI
.1.
.....:
W
••:
••• 'I··.il
*:1· ••• 1
I
r--'"--L__L...JUU__~-L~~. .~-H.......~L-~. .LL...L__'-'~~: •••
w·
I •••
: .i
I
···i-i-Lo.:.:...I..1..__uu",iiLj
..: ••••
1.::_
i i-·
II.
J...:..·_·...
.1 ••••
: -:••:
• ••••: a.' .1
II •••••• ::..
•••
••
•
1••
••••
:
••
•••••: w· :
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HITACHI
Hitachi America. Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
463
HD61830B
Application (Character Mode, External CG, Character Font 8x 8)
H06303
H061830B
~
Al
I
Al5
Do
I
07
FDDecoder
E
cs
LM
u... Ao RAM(2)
OE
RAM(1) Dot,......
I I:IM6116 I jv
MAo
I
f----'
MAIO
A IO
cf7
OE ,
CE
MAll
d
MAl2
I
MA 15
MOo
I
M0 7
Ao-A3
A4 -A 11
ROo
Dr
ROM
OE
I
07
HN482732A CE
R0 7
01
FlM
'MB
Cl1
Cl2
O2
MA -Open
1
OE
Do ~
"---v' I HM6116
A IO
d/. . . .
CS
~-
CS
OBo
I
OB 7
E
R/W
~WE
~
WE"
RS
-H-
R/W
~
Open_ SYNC
Vcc- iiE§"
External- CR
clock
Pi
LtS
I
+5V
GNO
-5V
01
FlM
MB
Cl1
Cl2
02
+5V
GNO
lCO Module
lM-200
Vo5V
Application (Graphic Mode)
~----------------
H06303
MPU
OB oDB7
CS E
RSR/W
RES -
0-1
Cl 1 , Cl2
MB, FlM
M~MA 15
DE
MOoM0 7
16K bits
H0611oo~
i
!
I
WE
RAM
a
'-
r0611004---~------ -
I
02
H061830B
Controller
-T
lCO
--2-r.0;
'I
l-
I,
CMOS
GNO
I
Voo (5V)
I
VEE (-5V)
.1-
l'
IH0611oo1------------ H061100A!
a
ISUDDV -V
V for
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~?S~~;'rn~~
I
•
r
L ________
----
-
HITACHI
464
Hitachi America, Ltd,· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819" (415) 589-8300
HD61830B
Example of Configuration
Graphic Mode
Liquid crystal
display module
Character Mode (1) (Internal Character Generator)
Liquid crystal
display module
MAo-MA"
Character Mode (2) (External Character Generator)
Liquid crystal
display module
Parallel Operation
(Master)
I.=~I-----,r..f=:::==~--~ Liquid crystal
Liquid crystal
(2)
display module ( 1) display module
Driving both of two
module by same
common signal
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA94005"1819· (415) 589-8300465
HD63645F/HD64645F-LCD Timing Controller (LCTC)
Pin Arrangement
Description
The HD63645F /HD64645F LCTC is a control
LSI for large size dot matrix liquid crystal
displays. The LCTC is software compatible
with the HD6845 CRTC, since its programming method of internal registers and memory addresses is based on the CRTC. A display
system can be easily converted from a CRT to
an LCD.
~g~ ~
MD2
~g~
~
F.
MD5 •
MD6 ~
MD7 ..-
The LCTC offers a variety of functions and
performance features such as vertical and
horizontal scrolling, and various types of
character attribute functions such as reverse
video, blinking, nondisplay (white or black),
and an OR function for simple superimposition of character and graphic displays. The
LCTC also provides DRAM refresh address
output.
MOB
[!
MD9 ITci
MD10[l]
MD11r;;
MD12@
MD13ill
MD14!)i
MD15'"
V ee 1
LD3 '"
LD2
LD1 r,;
LOO ~
IE
m
t~~ ~
A compact LCD system with a large screen
can be configured by connecting the LCTC
with the HD61104 (column driver) and the
HD61105 (common driver) by utilizing 4-bit x
2 data outputs. Power dissipation has been
lowered by adopting the CMOS process.
lU1
2.
..
"
"
..
..
RAO
RA1
RA2
RA3
RA4
.. GND1
"G~
" AT
" 'LS
" DIS"
.. WIDE
" ON/W
" MODE
'I-'ODB7
BLE
49
DBs
., DB6
D
46
DB4
DB3
., DB2
... DB,
..., OBo
" RiWiRoI
.1
E(WR)
) is for HD64645F
Features
•
•
•
•
•
•
•
•
•
•
Software compatible with the HD6845
CRTC
Programmable screen size:
-Up to 1024 dots (height)
-Up to 4096 dots (width)
High-speed data transfer:
-Up to 20 Mbits/s in character mode
-Up to 40 Mbits/s in graphic mode
Selectable single or dual screen configuration
Programmable multiplexing duty ratio:
static to 1/512 duty cycle
Programmable character font:
-1-32 dots (height)
-8 dots (width)
Versatile character attributes: reverse
video, blinking, nondisplay (white),
nondisplay (black)
OR function: superunposing characters
and graphics display
Cursor with programmable height, blink
rate, display position, and on/off switch
Vertical smooth scrolling and horizontal
scrolling by the character
•
•
•
•
•
•
•
•
Versatile display modes programmable
by mode register or external pins: display
on/off, graphic or character, normal or
wide, attributes,' and blink enable
Refresh address output for dynamic RAM
4- or 8-bit parallel data transfer between
LCTC and LCD driver
Recommended LCD driver: HD61104
(column) and HD61105 (common),
HD66204 (column) and HD66205
(common), HD66106, HD66107T (common/column)
CPU interface: 68 family (HD63645F),
80 family (HD64645F)
CMOS process
Single +5 V ±10%
80-pin plastic QFP (FP-80)
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
HD63645F /HD64645F
Ordering Information
Type No.
Bus Timing
Bus Interface
Package
HD63645
2MHz
68 System
80-pin Plastic QFP (FP-80)
HD64645
4MHz
80 System
80-pin Plastic QFP (FP-80)
HD64646
4MHz
80 System
80-pin Plastic QFP (FP-80B)
Note:
See HD64646 data sheet in this data book.
Pin Description
Symbol
Pin Number
Nama
Vee 1 , Vee2
17,32
Vee
GND1, GND2
37,59
Ground
LUO-LU3
22-25
LCD Up Panel Data 0-3
LDO-LD3
18-21
LCD Down Panel Data 0-3
CL1
28
Clock One
CL2
29
Clocl< Two
o
o
o
o
FLM
27
First Line Marker
o
M
26
M
MAO-MA15
65-80
Memory Address 0-1 5
RAO-RA4
60-64
Raster Address 0-.4
o
o
o
MDO-MD7
1-8
Memory Data 0-7
MD8-MD15
9-16
Memory Data 8-1 5
DBa-DB7
43-50
Data Bus 0-7
CS
39
Chip Select
E
41
Enable (HD63645 Only)
R/W
42
Read/Write (HD63645 Only)
WR
41
Write (HD64645 Only)
RD
42
Read (HD64645 Only)
RS
40
Register Select
RES
38
Reset
DCLK
33
o Clock
MCLK
34
M Clock
DISPTMG.
35
Display Timing
CUDISP
36
Cursor Display
sKO
30
Skew 0
SK1
31
Skew 1
ON/OFF
53
On/Off
BLE
51
Blink Enable
AT
57
Attribute
G/C
58
Graphic/Character
WIDE
54
Wide
LS
56
Large Screen
D/S
55
Dual/Single
MODE
52
Mode
I/O
I/O
o
o
o
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
467
HD63645F /HD64645F
Pin Functions
Power Supply (Veel, Vcc2, GND)
Power Supply Pin (+5 V): Connect Vee l
and Vcc 2 with +5 V power supply circuit.
Ground Pin (0 V): Connect GNDl and
GND2 with OV.
LCD Interface
LCD Up Panel Data (LUO-LU3), LCD
Down Panel Data (LDO-LD3): LUO-LU3
and LDO-LD3 output LCD data as shown in
table 1.
Chip Select (CS): CS selects a chip. Low
level enables MPU read/write of the LCTC
internal registers.
Enable (E): E receives an enable clock.
(HD63645F only).
Read/Write (R/W): R/W enables MPU read
of the LCTC internal registers when R/W is
high, and MPU write when low (HD63634F
only).
Write (WR): WR receives MPU write signal
(HD64645F only).
Clock One (CLI): CLl supplies timing clocks
for display data latch.
Read (RD): RD receives MPU read signal
(HD64645F only).
Clock Two (CL2): CL2 supplies timing clock
for display data shift.
Register Select (RS): RS selects registers.
(Refer to table 5.)
First Line Marker (FLM): FLM supplies
first line marker.
Reset (RES): RES performs external reset of
the LCTC. Low level of RES stops and zero~
clears the LCTC internal counter. No register
contents are affected.
M (M): M converts liquid crystal drive output
to AC.
Timing Signal
Memory Interface
Memory Address (MAO-MAI5): MAOMA15 supply the display memory address.
Raster Address (RAO-RA4):
supply the raster address.
RAO-RA4
Memory Data (MDO-MD7): MDO-MD7
receive the character dot data and bitmapped data.
Memory Data (MD8-MDI5): MD8-MD15
receive attribute code data and bit-mapped
data.
M Clock (MCLK): MCLK indicates memory
cycle; DCLK is divided by four.
Display Timing (DISPTMG): DISPTMG
high indicates that the LCTC is reading display data.
Cursor Display (CUDISP): CUDISP supplies cursor display timing; connect with
MD12 in character mode.
Skew 0 (SKO)/Skew I (SKI): SKO and SKl
control skew timing. Refer to table 2.
MPU Interface
Data Bus (DBO-DB7): DBO-DB7 send/
receive data as a three-state I/O common
bus.
Table I
D Clock (DCLK): DCLK inputs the system
clock.
Mode Select
The mode select pins ON/OFF, BLE, AT, G/C,
LCD Up Panel Data and LCD Down Panel Data
Single Screen
a-Bit Data
Pin name
4-Bit Data
LUO-LU3
LDO-LD3
Data output
Disconnected
Data output
Data output
Dual Screen
Data output for upper screen
Data output for lower screen
HITACHI
468
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD63645F /HD64645F
and WIDE are ORed with the mode register
(R22) to determine the mode.
normal and wide display mode (high = wide
display, low = normal display).
On/Off (ON/OFF): ON/OFF switches dis-
Large Screen (LS): LS controls a large
screen. LS high provides a data transfer rate
of 40 Mbits/s for a graphic display. Also used
to specify a-bit LCD interface mode. For more
details, refer to table 10.
play on and off (High
= display on) .
Blink Enable (BLE): BLE high level enables
attribute code "blinking" (MD13) and provides normal/blank blinking of specified
characters for 32 frames each.
attribute functions.
Dual/Single (D/S): D/S switches between
single and dual screen display (dual screen
display when high).
Graphic/Character (G/C): G/G switches
between graphic and character display mode
(graphic display when high).
Mode (MODE): MODE controls easy mode.
Attribute (AT): AT controls character
Wide (WIDE): WIDE switches between
Table 2
Skew Signals
SKO
SK1
Skew Function
o
o
No skew
1-character time skew
2-character time skew
Prohibited combination
1
o
1
o
1
MODE high sets duty ratio, maximum number of rasters, cursor start/end rasters, etc.
(Refer to table 9.)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
469
HD63645F /HD64645F
Function Overview
LCD and CRT Display Systems
Main Features of HD63645F IHD64645F
Figure 1 shows a system using both LCD and
CRT displays.
Main features of the LCTC are:
High-resolution liquid crystal display
screen control (up to 720 X 512 dots)
Software compatible with HD6845
(CRTC)
Built-in character attribute control circuit
. Table 3 shows how the LCTC can be used.
Table 3
Functions, Application, and Configuration
Claeeification
Item
Description
Functions
Screen Format
• Programmable horizontal scanning cycle by the character clock
period
• Programmable multiplexing duty ratio from static up to 1/512
• Programmable number of vertical displayed characters per character
row
• Programmable number of rasters per character row (number of
vertical dots within a character row + space· between character
rows)
Cursor Control
• Programmable cursor display position, corresponding to RAM
address
• Programmable cursor height by setting display start/end rasters
• Programmable blink rate, 1/32 or 1/64 frame rate
Memory Rewriting
• Time for rewriting memory set either by specifying number of
____________________________________ ~?!!~_~~~!_~~~!_~~~~~~_~_?~_~X_~~I~_~!~~!_~~~I!~!~~_~_~_~~___________ _
Memory Addressing
• 16-bit memory address output, up to 64 kbytes x 2 memory accessible'
• DRAM refresh address output
Paging and Scrolling
• Paging by updating start address
• Horizontal scrolling by the character, by setting horizontal virtual
screen width
• Vertical smooth scrolling by updating display start raster
----------------------------------------------.-----------------------.-----.------.-----------------------.---.---------_._--Character Attributes
• Reverse video, blinking, nondisplay (white or black), display ON/
OFF
OR Function
• Enables superimposing display of character screen and graphic
screen
LCTC Configuration
• Single 5 V power supply
.1/0 TIL compatible except RES, MODE, SKO, SK1
• Bus connectable with HMCS 6800 family (HD63645)
• Bus connectable with 80 family (HD64645)
.CMOS process
.Internal logic fully static
.80-pin flat plastic package
Application
Configuration
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD63645F jHD64645F
Uquid crystal
display
CRT
(monochrome)
LCD display signals
MPU
6301
Figure 1
LCD and CRT Displays
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
471
HD63645F /HD64645F
Internal Block Diagram
s: J.\:f UL~
.
"'" Ii:) C1 IJIV\.,in,
.
u.J.a~.I.a..u .L
V.L
----
... .L,U::; .L.I'-'.1.
v.
CL2
M
Gte
AT
~
;f,l~
RAo-RA4~==~======~============~
MODE
LE
CUDISP
SKO SKl
) is for HD64645 (80 types bus interface)
Flgure2
LCTC Block Diagram
HITACHI
472
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD63645F /HD64645F
~ystem
Block Configuration
Examples
Figure 3 is a block diagram of a character /
graphic display system. Figure 5 shows two
examples using LCD drivers.
HD63645/HD64645
MPU Bus
(WR) (RD)
E.R/W
DBO-DB7
II)
.c
iii
c::
01
'iii
G/C
AT
LS
MAO-MA15
D/S
WIDE
MODE
ON/OFF
MCLK
BLE
DISPTMG
CS.RS
::l
II)
::l
.c
~
'g
~
II)
::l
.c
B
II>
2
1·---
Display On/off
Blink enable
C
Reset
CUDISP
LUO-3
LDO-LD3
CL2r---AJ
~L1 f----"II
L.::=-=~=:::jRAO-MD4
Figure 3
LCD
Module
FLM
Character/Graphic Display System Example
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
473
HD63645F IHD64645F
Interface to MPU
RS
P10-P17
I
11
Decoder
t---<
SC2 (R/W)
CS
R/W
HD63645F
LCTC
HD6301
MPU
E
E
Pao -P a7
DBo-DB7
RES
RES
RESET
Note: HD6301 is set in mode 5. P1 0-P17 are used as output ports, and
P30-P37 as data buses. SC2 outputs R/W here.
Interface between H06301 and HD63645F
Ao-A'5
10E
-
I
~
~
RO
HD641BO
MPU
II
Decoder
RS
•
::J
WR
0 0 -0 7
CS
RD
HD64645F
LCTC
WR
DBo-DB7
RES
RES
RESET
Note: In 80 family MPUs, I/O space is separate from memory space in
software. Thus the LCTC, a part of I/O, needs the ORed signals
of the interface signals and 10E. So 10E and RD, and 10E and
WR should be ORed to satisfy tAS, the timing of CS, RD, and
WR.
Interface between H064180 and HD64645F
Figure 4
Interface to MPU
HITACHI
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HD63645F /HD64645F
I
Dual screen
I
LUOLU3
FLMI-----I
400 x 640 dots
CL1~_---1
CL2~_--r
M
LCTC
I
Single screen
I
LUOLU3
CL1r.-.-~
CL2r.-._ _--'
M
LCD panel
200 x 640 dots
1/200 duty ratio
LCTC
Figure 5
LCD Driver Examples
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
475
HD63645F /HD64645F
Registers
-nune'l snows me reQlSter mapping. Table b
describes their function. Table 6 shows the
Table 4
differences between CRTC and LCTC registers.
Registers Mapping
Ad*RegiIter Reg.
Ci RS 432 1 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DatIl Bit
RegiIter Name
110.
- ----0 ----- AR
1 00000 RO
1 00001 Rl
1 01001 R9
1 01010 RIO
o1 0 1 1 Rl1
o1 1 00 R12
o11 0 1 R13
01 11 0 R14
o1 1 1 1 R15
1 00 1 0 RIB
1 00 1 1 R19
1 0 1 0 0 R20
1 0 1 0 1 R21
1 0 1 1 0 R~2
Program Unit SymboIR/W
Invalid
Address Register
Horizontal Total Characters Character3
Nht
Horizontal Displayed Char. S Character
Nhd
Maximum Raster Address
Raster
Nr
Cursor Start Raster
Ncs
Raster4
Cursor End Raster
Raster
Nee
Start Address (H)
Memory Address Start Address (L)
Memory Address Cursor Address (H)
Memory Address Cursor Address (L)
Memory Address Horizontal Virtuel Screen WidthCharacter
Nir
Multiplexing Duty Ratio (H) Raster3
Ndh
Multiplexing Duty Ratio (L) Raster3
Ndl
Display Start Raster
Raster
Nsr
Mode Register
-NoteS
7
8
&
4
3
2
0
W
W
W
W
W
W
R/W
R/W
R/W
R/W
W
W
W
W
W
Notes: 1. . . . . : Invalid data bits
2. R/W indicates whether write aCcess or read access is enabled to/from each register.
W:
Only write accessible
R/W: Both read and write accessible
3. The ·value to be specified minus 1· should be programmed in these registers: RO. R1 and
R20.
4. Data bits 5 and 6 of cursor start register control the cursor status as shown below.
(For more details. refer to page 27).
B
o
o
1
1
P
Cursor BUnk Mod.
0
1
0
1
Cursor on; without blinking
Cursor off
Blinking once every 32 frames
Blinking once every 64 frames
5. The OR of mode pin status and mode register data determines the mode.
6. Registers R2-R8. R16. and R17 a~ not assigned for the LCTC. Programming to these
registers will be ignored.
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HD63645F /HD64645F
Table 5
Internal Register Description
Reg.
No.
Raglater Name
Size(Bita)
Description
AR
Address Register
5
Specifies the internal control registers (RO. R1.
R9-R15. R18-R22) address to be accessed
RO
Horizontal Total Characters
8
Specifies the horizontal scanning period
R1
Horizontal Displayed Characters
8
Specifies the number of displayed characters per
character row
R9
Maximum Raster Address
5
Specifies the number of rasters per character row.
including the space between character rows
R10
Cursor Start Raster
5+2
Specifies the cursor start raster address and its
blink mode
R11
Cursor End Raster
5
Specifies the cursor end raster address
R12
R13
Start Address (H)
Start Address (L)
16
Specify the display start address
R14
R15
Cursor Address (H)
Cursor Address (L)
16
Specify the cursor display address
R18
Horizontal Virtual Screen Width
8
Specifies the length of one row in memory space
for horizontal scrolling
R19
R20
Multiplexing Duty Ratio (H)
Multiplexing Duty Ratio (L)
9
Specify the number of rasters for one screen
R21
Display Start Raster
5
Specifies the display start raster within a character
row for smooth scrolling
R22
Mode Register
5
Controls the display mode
Note: For more details of registers. refer to Ulnternal Registers u
•
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HD63645F /HD64645F
Table 6
...""".
Internal Register Comparison between LCTC and CRTC
No.
LCTC HD63645/HD64645
Comparison
CRTC HD6645
AR
Address Register
Equivalent to CRTC
Address Register
RO
Horizontal Total Characters
Rl
Horizontal Displayed Characters
Horizontal Total Characters
Horizontal Displayed Characters
R2
Particular to CRTC ;
Horizontal Sync Position
R3-
unnecessary for LCTC
Sync Width
R4
Vertical Total Characters
R5
-R6
Vertical Total Adjust
R7
Vertical Sync Position
Vertical Displayed Characters
Interlace and Skew
RS
Equivalent to CRTC
Maximum Raster Address
R9
Maximum Raster Address
Rl0
Cursor Start Raster
Rl1
Cursor End Raster
Cursor End Raster
R12
Start Address (H)
Start Address (H)
Cursor Start Raster
R13
Start Address (L)
Start Address (L)
R14
Cursor Address (H)
Cursor (H)
R15
Cursor Address (L)
Cursor (L)
R16
Particular to CRTC ;
Light Pen (H)
R17
unnecessary for LCTC
Light Pen (L)
R1B
Horizontal Virtual Screen Width
R19
Multiplexing Duty Ratio (H)
R20
Multiplexing Duty Ratio (L)
R2l
Display Start Raster
R22
Mode Register
Additional registers for LCTC
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HD63645F /HD64645F
Functional Description
Programmable Screen Format
Figure 6 illustrates the relation between LCD
display screen and registers. Figure 7 shows a
timing chart of signals output from the LCTC
in mode 5 as an example.
t - - - - - - - - - - H o r i z o n t a l Total Chara~rs(RO)----------_I
(R21)
Start
Raster
Horizontal Displayed Chars. (Rl) - - - - -...
~=~~-~
Stert Address (R12)
CPU
Memory Write Time
Display Period
----'---'----'"' Display
Stert
Raster
Address
(R21)
Figure 6
Relation between Display Scteen and Registers
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HD63645F /HD64645F
lTu-u-u-u-U-L____J-U-U-U-U-U-U-U-L.J-U-U-U-LJ-U-U-U-U-U-U-
MCLK
DISPTMG
J
CUDISP
Jl
C
(Timing
latCh)
MAO-MA15
0
1
2
~
3
4
5
~~~~FH2IJ..~'f2f2f2fJJ:i
RAO-RA4
____________________________
FLM
_ _ _ _ _ _ _ _ _ _ _ _....., - ~~L;:l~ - , ' - -_ _ _ _ __
M
____________________________ ___________
~x~
___________
~x~
CL1
eL2
---.l11UlflJ1J1 ____ JlfUlIUlI1JlL...-.---_ _ _-----Iflf
LUO
______~~~~~~~~_-_'_____________XX
LUl
LU2
____
~:~~~~~t
________________YJ
______~~~~JQOOJll~2__--------~----------~XX
-----vvvvvw
\fV
LU3
_ _ _---'~ ____ ~2...3_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~M
LDO
-----'~~~~~JJJJJJj,_ _ _ ___''IJ
LDl
_'IJ'ffJJJJJJJJl:~~~JJJJJJj,
YJ
LD2
_~~~~~JJJJJJj,
'IJ
LD3
__'IJJ'fJJJJJJJfJ ::~~JJJJJJj,
YJ
Figure 7
LCTC Timing Chart (In Mode 5: Single Screen, 4·Blt Transfer, Normal
Character Display)
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Hitachi America, Ltd. - Hitachi Plaza- 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD63645/HD64645
HD63645F /HD64645F
Cursor Control
Cursor height
Cursor blink mode
The following cursor functions (figure 8) can
be controlled by programming specific registers.
A cursor can be displayed only in character
mode. Also, CUDISP pin must be connected to
MD12 pin to display a cursor.
Cursor display position
Cursor
Start Raster
Cursor
Height
Cursor
End Raster
Figure 8
Cursor Display
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HD63645F /HD64645F
Graphic Mode 1: Graphic mode 1 directly
Character Mode and Graphic Mode
displays data stored in a graphic memory
ThA T.r.Tr.
Q;l1!'!'nrh:z 'turn tunl::u::.!
nf
niC!!,1~~7
modes; character mode and graphic mode.
Graphic mode 2 is provided to utilize software for a system u,sing the CRTC (HD6845).
The display mode is controlled by an OR
between the mode select pins (D/S, G/C, LS,
WIDE, AT) and mode register (R22).
Character Mode: Character mode displays
characters by using CG-ROM. The display
data supplied from memory is accessed in 8bit units. A variety of character attribute
functions are provided, such. as reverse video,
blinking, nondisplay (white or black) ,by storing the attribute data in attribute RAM (ARAM).
hnf'f'..o.'r T'ho.
-- - - - - - "
----
~;C!'I"'\lo~J'
---- ..- - - - "
1"'10+0
C!'I'I_""H.o.~
------- -
~JI>r---
f''''I'''\YW''O ......,,0...-_
-- - - - - - - - - - - - - -
ory is accessed in 16-bit units. Character
attribute functions or wide mode are not
provided. Figure 10 illustrates the relation
between graphic display screen and memory
contents.
Graphic Mode 2: Graphic mode 2 utilizes
software for a system using the CRTC
(HD6845). The display data supplied from
memory is accessed in 16-bit units. Character
attribute functions or wide mode are not
provided. The same memory addresses are
output repeatedly the number of times specified by maximum raster register (R9). The
raster address is output in the same way as in
character mode.
Figure 9 illustrates the relation between
character display screen and memory contents.
VRAM
(Char.
code)
Blinking
+
~8-bit
Start
7
address ...
1st
1st
Row
Row
I
2nd
Row
2nd
Row
\
code)
_8-bit
41
08
Reverse Video
42
20
Blinking
43
00
,.
\
ARAM
(Attr.
,,,
44
00
45
00
46
00
,,
,,
,I
I
I
I
I
Figure 9
Relation between Character Screen and Memory Contents
HITACHI
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HD63645F /HD64645F
Horizontal Virtual Screen Width
direction by the character, by setting the
horizontal virtual screen width and updating
the start address. This function is enabled by
programming the horizontal virtual screen
width register (R18).
Horizontal virtual screen width can be specified by the character in addition to the number of horizontal displayed characters (figure
11).
Figure 12 shows an example.
The display screen can be scrolled in any
MM
M
1st Une
2nd Une
0
7
VRAM
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I
I
I
I
I
I
.
VRAM
DO ARAM
015
I
I
I
I
I
I
I
I I
I I
I
I
I I
I I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,8-bit ... ... 8-dit
I
I
I,
I I
I I
, I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,,
I
I
I
I
I I
I I
I I
I
I
I
I
I
I
I
I
I I
I I
I
I
I I
1'1
/
1st
Lin
\
(
2n
Line
\
FF
55
33
I
I
I
I
I
I
I
I
00
AA
I
I
I
CC
I
I
I
I
I
I
I
Display Screen
I
I
I
I
I
I
I
I
I
I
I
I
I
Figure 10
ARAM
Relation between Graphic Screen and Memory Contents
i<---HOnzorltal virtual
Figure 11
screen width(R18)--..j
Horizontal Virtual Screen Width
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· HD63645F /HD64645F
fl18
Example:
R18 (Horizontal Virtual Screen Width) 10
R1 (Horizontal Displayed Charactars) - 6
=
5
6
7
8
9
Displayed Area
u
Performing horizontal
scroll by updating
the start address
0U14
o
10
11
2
3
12
13
9
New
LeT
Figure 12
Ezample of Horizontal ScroD by Setting Horizontal Virtual Screen Width
HITACHI
484
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HD63645F /HD64645F
Smooth Scroll
Wide Display
Vertical smooth scrolling (figure 13) is performed by updating the display start raster,
as specified by the start raster register (R21).
This function is offered only in character
mode.
The character to be displayed can be doubled
in width, by supplying the same data twice
(figure 14). This function is offered only in
character mode, and controlled either by bit 2
of the mode register (R22) or by the WIDE
pin.
1
Raster
0
Address 1
2
2
3
4
5
3
4
5
6
7
6
7
Display start raster address
(R21) = 0
Figure 13
(R21) = 1
(R21) = 2
Example of Smooth Scroll by Setting Display Start Raster Address
I
122334455667788
WIDE
= low
WIDE
Figure 14
= High
Example of Wide Display
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485
/
HD63645F /HD64645F
Attribute Functions
-
The attribute functions are offered only in
character mode, and controlled either by bit 0
ot me moae re91ster \H:'::':j or tne AT pm. AS
shown in figure 15, a character attribute can
be specified by placing the character code on
MDO-MD7, and the attribute code on MDllMD15. MDS-MD10 are invalid.
---
A vanety 01 cnaracter attrwute lUnCtlons
such as reverse video, blinking, nondisplay
(white) or nondisplay (black) can be implemented by storing the attribute data in ARAM (attribute RAM). Figure 15 shows a
display example using each attribute function.
2. White
1. Black
D
3. Blinking
4. Cursor
5. Reverse Video
m
Figure 15
Display Example Using Attribute Functions
MD Input
15
14
13
12
11
10-S
7-0
Function
Nondisplay
(black)
Nondisplay
(white)
Blinking
Cursor
Reverse
video.
***
Character Code
': Invalid
Figure 16
Attribute Code
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HD63645F /HD64645F
OR Function -Superimposing Characters and Graphics
this data as 1 byte.
The OR function (figure 17) generates the OR
of the data entered into MDO-MD7 (e.g.
character data) and the data into MD8-MD15
(e.g. graphic data) in the LCTC and transfers
This function is offered only- in character
mode, and controlled by bit 0 of the mode
register (R22) or by the AT pin. Any attribute
functions are disabled when using the OR
function.
Graphic data
(Character data)
Character data
(Graphic data)
I MD15 MD14 - - - r - - - - - -
MD9
- - - - - -
MOl;
'MD7
- - -/- - -
MD6 - - - -
- - -
MD1
- - - - - -
MDO
- -
I
-/- - - - - -
-
~
- - - - -
Y""-
-
a-bit
data
.....
- -
-
- - - -
-
-
-
-
-
-
-
-
-
-
-
- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
7
-
- -
-
- - -
-
_I
Figure 17 _ OR Function
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HD63645F /HD64645F
DRAM Refresh Address Output Function
rTI'l-_
Tn"",...
___ "' ___ ... _
... \..._
... .-.3...1 __ .......
& __
T"\'DA'I. •
.......- -_ ... - -_ ..Z"........ ......- --_.. __..... _- -- .... --,,refresh while CLl is high, as shown in figure
18. The 16 refresh addresses per scanned line
are output 16 times, from $OO-$FF.
zontal character display period, the access is
retarded to the next cycle by inserting a latch
... _ _ ..... . - ............ 9
...
...:I...:I ....... "1'!t ...... , .. +_'1,+
~_A
h"of.f,o.r
'I"Y"I,oTn_
~-;Y-~~tP~t. -Th~ -~k;;-f~~~~~ --r;t~ds the
CUDISP, DISPTMG, CL2 outputs, and MD
inputs in the LCTC to match phase with the
display data signal.
Skew Function
The LCTC can specify the skew (delay) for
CUDISP, DISPTMG, CL2 outputs and MD
inputs.
If buffer memory and character generator
By utilizing this function, a low-speed memory can be used as a buffer RAM or a character generator ROM.
This function is controlled by pins SKO and
SKl as shown in table 7.
ROM cannot be accessed within one hori-
Table 7
Skew Function
SKO
SK1
Skew Function
o
o
No skew
1 character time skew
2 character time skew
Inhibited combination
o
1
o
1
1
DISPTMG
L
CL1
MCLK
MAO-MA7
Display
Memory
Address
.1 ~
Figure 18
DRAM Refresh
Address
.I~ ~:~~~
Address
DRAM Refresh Address Output
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HD63645F /HD64645F
Easy Mode
Automatic Correction of Down Panel
Raster Address
This mode utilizes software for systems using
the CRTC (HD6845). By setting MODE pin to
high, the display mode and screen format are
fixed as shown in table 8. With this mode,
software for a CRT screen can be utilized in a
systeII!- using the LCTC, without changing
the BIOS.
Table 8
When the LCTC mode is set for character
display and dual screen, memory addresses
(MA) and raster addresses (RA) are output in
such a way as to keep continuity of a display
spread over the two panels. Therefore users
can use the LCTC without considering the
multiplexing duty ratio (the number of vertical dots of a screen) or the character font.
(See figure 19.)
Fixed Values in Easy Mode
Reg. No.
Register Name
Fixed Value (decimel)
R9
R10
R11
R18
R19
R20
R21
R22
Maximum raster address
Cursor start raster
Cursor end raster
Horizontal virtual screen width
Multiplexing duty ratio (H)
Multiplexing duty ratio (l)
Display start raster
Mode register
7
6
7
Same value as (R1)
99 (in dual screen mode)
199 (in single screen mode)
o
o
Up panel
-~---AB8------
Characters are continuous in spite of
the break of a screen.
Down par:Iel
Figure 19
Example of the Display in the Character Mode
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HD63645F /HD64645F
~stem
Setting
Configuration and Mode
LCD System Configuration
Hardware Configuration and Mode Setting
The screen configuration, single or dual, must !
be specified when using the LCD system
(figure 20).
Using the single screen configuration, you
can construct an LCD system with lower cost
than a dual screen system, since the required
number of column drivers is smaller and the
manufacturing process for mounting them is
simpler. However, there are some limitations,
such as duty ratio, breakdown voltage of a
driver, and display quality of the liquid crystal, in single screen configuration. Thus, a
dual screen configuration may be more suitable to an application.
The LCTC also offers an 8-bit LCD data
transfer function to support an LCD screen
with a smaller interval of signal input terminals. For a general size LCD screen, such as
640 x 200 single, or 640 x 400 dual, the usual
4-bit LCD data transfer is satisfactory.
The LCTC supports the following hardware
configurations:
Single or dual screen configuration
4-or 8-bit LCD data transfer
and the following screen format:
Character, graphic 1, or graphic 2 display
Normal or wide display (only in character
mode)
OR or attribute display (only in character
mode)
Also, the LCTC supports up to 40 Mbits/s of
large screeen mode (mode 13) for large
screen display. This mode is provided only in
graphic 1 mode.
Table 9 shows the mode selection method
according to hardware configuration and
screen format. Table 10 shows how they are
specified.
4
Column Driver (Upper panel)
...
~
·c
o
LCD Upper Panel
c
o
E
4or8
o~a--~~/~i:____~C~o~lu~m~n~o~n~'v~e~r____J
~
Single screen
Dual screen
Figure 20
Hardware Configuration According to Screen Format
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HD63645F /HD64645F
Table 9
Mode Selection
Hardwara Configuration
Screen Format
Maximum
Screen
LCD Data
Transfer
Configuration
Screen
Size
Character/ Normal/
Graphic
Wide
4-bit
Single
Normal
Character
Normal
Attribute/
OR
AT
data transfer
speed (Mbps) Mode No.
20
5
10
6
OR
Wide
AT
OR
Dual
Normal
Graphic 1
20
7
Graphic 2
20
8
Character
Normal
AT
20
OR
Wide
AT
10
2
OR
8-bit
Single
Graphic 1
20
3
Graphic 2
20
4
Large
Graphic 1
Normal
Character
Normal
AT
40
13
20
9
10
10
OR
Wide
AT
OR
Note:
Graphic 1
20
11
Graphic 2
20
12
Maximum data transfer speed indicates amount of the data read out of a memory. Thus, the
data transfer speed sent to the LCD driver in wide function is 20 Mbps.
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HD63645F /HD64645F
Mode List
Table 10
Mode List
Pin Name
No. ModeN.....
1 Dual-screen
character
2
Dual-screen
wida character
3
4
6
Dual-screen graphic 1
Dual-screen graphic 2
Single-screen
character
6
Single-screen
wide character
7
Single-screen
graphic 1
Single-screen
graphic 2
8-bit character
8
9
10 8-bit wide
character
11 8-bit graphic 1
12 8-bit graphic 2
13 Large screen
DIS GIC LS WIDE AT
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0,
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
ao-.
Canfg.
a...:tar
Graphic/
Data
TI'IIIIIfar
Dual
screen
Character
4-bit
x2
WIde
DiIpIIy
AtIIibute
Normal
OR
Wide
OR
AT
AT
1
0
0
1
0
Graphic
Single
screen
Character
4-bit
Normal
OR
Wide
OR
AT
AT
Graphic
Single
screen
Character
8-bit
Normal
OR
Wide
OR
AT
AT
1
0
Graphic
Dual
screen
4-bit
x2
The LCTC display mode is determined by pins DIS (pin 55), G/C (pin 58), LS (pin 56), WIDE (pin 54),
and AT (pin 57). As for G/C, WIDE, and AT, the OR is taken between data bits 0,2, and 3 ofthe mode
register (R22). The display mode can be controlled by either one of the extemal pins or the data bits of
R22.
Note:
The above 5 pins have 32 status combinations (high and low) . Any combinations other than the
above are prohibited, because they may cause malfunctions. If you set an prohibited combination, set the right combination again.
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HD63645F /HD64645F
Internal Registers
The fDD63645F/fDD64645F has one address
register and fourteen data registers. In order
to select one out of fourteen data registers,
the address of the data register to be selected
must be written into the address register. The
MPU can transfer data to/from the data register corresponding to the written address.
To be software compatible with the CRTC
(HD6845), registers R2-R8, R16, and R17,
which are not necessary for an LCD are
defined as invalid for the LCTC.
Address Register (AR)
AR register (figure 21) specifies one out of 14
data registers. Address data is Written· into
the address register when RS is low. If no
register corresponding to a specified address
exists, the address data is invalid.
Horizontal Total Characters Register
(RO)
RO register (figure 22) specifies a horizontal
scanning period. The total number of horizontal characters less 1 must be programmed
into this 8-bit register in character units. Nht
indicates the horiZontal scanning period including the period when the CPU occupies
memory (total number of horiZontal characters minus the number of horizontal
displayed characters). Its units are, then,
converted from time into the number of
characters. This value should be specified
according to the specification of the LCD
system to be used.
Data Bit
-
Character
::iii Nht
+1
m
2
4
Horizontal Displayed Characters Register (Rl)
R1 register (figure 23) specifies the number of
characters displayed per row. The horiZontal
character pitches are 8 bits for normal character display and 16 dots for wide character
display and graphic display.
Nhd must be less than the total numbel of
horizontal characters.
.
Maldmwn Raster Address Register (R9)
R9 register (figure 24) specifies the number
of rasters per row in characters mode, consisting of 5 bits. The programmable range isO (1
raster/row) to 31 (32 rasters/row).
Cursor Start Raster Register (RIO)
R10 register (figure 25) specifies the cursor
start raster address and its blink mode. Refer
to table 11.
Data Bit
I
Program Unit R/W
716151413121110
W
Nhd (Displayed charactars)
Figure 23
Program Unit R/W
716151413121110
Nht (Total characters - 1)
+ ~
5,9
1,6,7,8,10,11,12,13
2,3,4
Address Register
Data Bit
Figure 22
Nhd
Mode No.
Program Unit R/W
716151413121110
-1-1 -I Register address
Figure 21
Note the following restrictions
Horizontal Total
Characters Register
716151413121110
Nr
-1-1-1
Figure 24
W
Horizontal Displayed
Characters Register
Data Bit
W
Charactar
Program Unit R/W
Raster
W
Maldmum Raster Address
Register
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493
HD63645F /HD64645F
< ..... >
Horizontal Virtual Screen Width Regis-
32- or 64-frame
R18 register (figure 29) specifies the memory
width to determine the start address of the
next row. By using this register, memory
width can be specified larger than the number of horizontal displayed characters. Updating the display start address facilitates
scrolling in any direction within a memory
space.
tAr (RiA)
Cursor End Raster Register (Rll)
Rll register (figure 26) specifies the cursor
end raster address.
Start Address Register (H/L)(RI2/RI3)
R12/R13 register (figure 27) specifies a buffer
memory read start address. Updating this
register facilitates paging and scrolling. R14/
R15 register can be read and written to/from
the MPU.
Cursor Address Register (H/L) (RI4/RI5)
R14/R15 register (figure 28) specifies a cursor
display address. Cusor display requires setting R10 and Rll, and CUDISP should be
connected with MD12 (in character mode).
This register can be read from and written to
the MPU.
The start address of the next row is that of
the previous row plus Nir. If a larger memory
width than display width is unnecessary, Nir
should be set equal to the number of horizontal displayed characters.
Multiplexing Duty Ratio Register (H/L)
(RI9/R20)
R19/R20 register (figure 30) specifies the
number of vertical dots of the display screen.
The programmed value differs according to
the LCD screen configuration.
In single screen configuration:
(Programmed value) = (Number of vertical
dots)- 1.
Table 11 Cursor Blink Mode
B
P Cursor blink mode
o
o
1
1
0
1
0
1
Data Bit
Cursor on; without blinking
Cursor off
Blinking once every 32 frames
,Blinking once every 64 frames
7 1 6 1 5 1 4 1 3J 2J 1J 0
Memory address (H) (R12)
Memory address (L) (R13)
Figure 27
Data Bit
Figure 25
R/W
Start Address Register
Data Bit
Raster
W
7
Memory address(L) (R15)
Figure 28
Program Unit R/W
Program Unit R/W
I 6 I 5 I 4 I 3\ 211 J 0
Memory address (H) (R14)
Cursor Start Raster Register
Data Bit
Memory
address
Program Unit R/W
716151413121'10
-I B 1 P 1Ncs (Raster address)
Program Unit R/W
Memory
address
R/W
Cursor Address Register
716151413121110
-I - 1-I Nee (Raster address)
Figure 26
Raster
W
Cursor End Raster Register
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD63645F /HD64645F
In dual screen configuration:
should be equal or less than the maximum
raster address. Updating this register allows
smooth scrolling in character mode.
(Programmed value) =
(Number of vertical dots) _ 1.
2
Mode Register (R22)
Display Start Raster Register (R21)
R21 register (figure 31) specifies the start
raster of the character row displayed on the
top of the screen. The programmed value
Program Unit R!W
Data Bit
71 6 I 5 I 4 I 3 I 2 I 1 I 0
Nir (No. of chars. of virtual width)
Figure 29
Character
Figure 31
W
Raster
Display Start Raster Register
Data Bit
Program Unit R!W
716151413121110
-1 -1-l-1-1- h~JNdh'
Program Unit R!W
Data Bit
716151413121110
- I- I- I Raster address
W
Horizontal Virtual Screen
Width Register
Data Bit
The Or of the data bits of R22 (figure 32)
register and the external tenninals of the
same name determines a particular mode.
(figure 33)
Program Unit R!W
7
Raster
w
W
Ndl (Number of rasters - 1) (R20)
* : Number of rasters
Figure 30
Multiplexing
Register
Duty
Figure 32
Mode Register
Ratio
II
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
495
HD63645F /HD64645F
6 6 ~
I)
I
AT
(data bit 0)
BLE
(data bit 1)
WIDE
(data bit 2)
G/C
(data bit 3)
ON/OFF
(data bit 4)
Mode Register
(R22)
Notes: 1.
ON/Im'
G/C
(Pin 53)
(Pin 58)
BLE
(Pin 51)
=
2.
BlE (valid only when G/e is low (character mode))
BlE = High: Blinking enable on the character specified by attribute RAM
BlE = low: No blinking
3.
WIDE (valid only when G/e is low (cheracter mode))
WIDE = High: Wide display enabled
WIDE = low: Normal display
=
G/C High: Graphic 1 display (when AT
G/C = low: Character display
5.
AT
(Pin 57)
AT (valid only when G/e is low (cheracter mode»
AT High : Attribute functions enabled, OR function disabled.
AT = low: OR function enabled, attribute functions disabled.
4. G/e
Figure 33
WIDE
(Pin 54)
= low) or Graphic 2 display (when AT = High)
ON/OFF
ON/OFF = High: Display on state
ON/OFF = Low: Display off state
Correspondence between Mode Register and External Pins
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD63645F IHD64645F
Restrlct10ns on Programming Intemal
Registers
Note when programming that the values you
can write into the internal registers are
restricted as shown in Table 12.
Table12
Restrictions on Writing Values into the Internal Registers
Function
Restrictions
Display Format
1 < Nhd < Nht
Nhd +
16
m *1
Register
+
RO, Rl
1 ::iii 256
::iii Nht + 1
(No. of vertical dots) x (no. of horizontal dots) x
(frame frequency;fFRM) ::iii (data transfer speed; V)
{i} * 2 x (Nd +
Cursor Control
1) x Nhd x { 186}
Rl,R19,R20
* 3 fFRM ::iii V
Nhd::iii Nir
Rl, R18
o ::iii Nd ::iii 511
o ::iii Ncs ::iii Nee
Rl0, Rll
R19, R20
Nee:li Nr
Rl0, R9
Smooth Scroll
Nsr ::iii Nr
R21, R9
Memory Width Set
O::iii Nir ::iii255
R18
Notes'
*1
m varies according to the modes. See the following table.
Mode No.
5,9
1,6,7,8,10,11,12,13
2,3,4
*2
*3
m
2
4
Set 1 when an LCD screen is a single screen, and set 2 when dual. Modes are classified as
shown in the following table.
Mode No.
Val. .
5,6,7,8,9,10,11,12
1,2,3,4,13.
2
Set 8 when a character is constructed with 8 dots, and set 16 when with 16 dots. Modes
. are classified as shown in the following table.
Mode No.
1,5,9
2,3,4,6,7,8,10,11,12,13
8
16
HITACHI
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497
HD63645F /HD64645F
Reset
2.
RES pin determines the internal state of LSI
3.
Fixed at high level:
MT.l"!J(
counters and the like. This pin does not affect
register contents nor does it basically control
output terminals.
Reset is defined as follows (Figure 34):
•
•
•
•
At reset: the time when RES goes low
During reset: the period while RES
remains low
After reset: the period on and after the
RES transition from low to high
Make sure to hold the reset signal low for
at least 1 Jls
RES pin should be pulled high by users during operation.
Preserve states before reset or fixed at
low level according to the timing when
the reset signal is input:
DISPTMG, CUDISP, MAO-MA15
4. Fixed at high or low according to mode:
CL2
5. Unaffected:
DBa-DB?
Reset State of Registers
RES pin does not affect register contents.
Therefore, registers can be read or written
even during a reset state; their contents will
be preserved regardless of reset until they
are rewritten to.
Notes for HD63645F /HD64645F
Reset State of Pins
1.
RES pin does not basically control output
pins, and operates regardless of other input
pins.
1.
Preserve states before reset:
LUO-LU3, LDO-LD3, FLM,CL1, RAO-RA4
2.
The HD63645/HD64645 are CMOS LSls,
and it should be noted that input pins
must not be left disconnected, etc.
At power-on, the state of internal registers becomes undefined. The LSI operation is undefined until all internal registers have been programmed.
)r-V
Vee - O.5V
~ __________________J
During reset
After reset
At reset
Figure 34
Reset Definition
HITACHI
498
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD63645F /HD64645F
Absolute Maximum Ratings
Item
Symbol
Value
Supply voltage
Vee
-0.3 to +7.0V
Terminal voltage
Vin
-0.3 to Vee +0.3 V
Operating temperature
Topr
-20"C to +75·C
Storage temperature
Totg
- 55·C to + 125·C
Note
2
Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation
should be under recommended operating conditions (Vee = 5.0V ±10%, GND = OV, Ta
= - 20·C to + 75·C). If these conditions are exceeded, it could afhct reliability of LSI.
2. With respect to ground (GND = 0 V)
Electrical Characteristics
DC Characteristics (Vee
otherwise noted)
= 5.0V ±10%,
GND
= OV,
T.
= -20·C
to
+ 75·C,
unless
Teat
Item
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Symbol Min
RES,
SK1
MODE,
SKO,VIH
Typ
Max
Unit
Vee-0.5
Vee+0.3
V
DCLK, ON/O'FF
2.2
Vee+0.3
V
All others
2.0
Vee+0.3
V
All others
-0.3
O.s
V
TTL interface 1
VOH
-C-M-O-S-in-t-erf-a-e-e""'"1--
2.4
All inputs except
DBo-DB7
Three state (off-state) DBo-DB7
leakage current
ITSL
Current dissipation 2
Ice
V
V
Vee-O.S
0.4
TTL interface
VOL
-C-=-M"""""O-=-S-in-t-erf-:a-c-e--
Condition
V
O.S
V
-2.5
+2.5
pA
-10
+10
pA
10
mA
Notes: 1. TTL Interface; MAO-MA15, RAO-RA4, OISPTMG, CUOISP, 080-087, MCLK
.C-MOS Interface; LUO-LU3, LDO-LD3, CL 1, CL2, M, FLM
2. Input/output current is excluded. When input is at the intermediate level with CMOS,
excessive current flows through the input circuit to power supply. Input level must be fixed
at high or low to avoid this condition.
3. If the capacitive loads of LUO-LU3 and LDO-LD3 exceed the rating, noise over 0,8 V may
be produced on CUOISP, DISPTMG, MCLK, FLM and M. In case the loads of LUO-LU3 and
LDO-LD3 are larger than the ratings, supply signals to the LCD module through buffers.
HITACHI
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499
HD63645F /HD64645F
AC Characteristics
:::~;;
: .... i.V&
'&a\;.
\niJo~oor:f:5
- - 06 ramuy)
Typ
Item
Symbol
Min
Unit
Figure
Enable cycle time
tCYCE
500
ns
35
Enable pulse width (high)
PwEH
220
ns
Enable pulse width (low)
PWEL
220
Enable rise time
tEr
Enable fall time
tEl
es.
es.
Max
ns
25
ns
25
ns
tAS
70
ns
tAH
10
ns
DBo-DB7 setup time
tos
60
ns
DBo-DB7 hold time
tOHW
10
RS. R/W setup time
RS. R/W hold time
DBo-DB7 output delay time
tOOR
DBo-DB7 output hold time
tOHR
t-------tCyCE
ns
150
20
ns
ns
-------+1
tEl
E
2.0V
l"'--
O.8V
CS
RS
R/W
DBo-DB7
(input)
DBo-DB7
(output)
Figure 35
CPU Interface (HD63645)
HITACHI
500
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD63645F /HD64645F
CPU Interface (HD64645 -
80 family)
Item
Symbol
Min
Unit
Figura
RD high level width
tWROH
190
ns
36
tWROl
190
ns
RD low level width
Typ
Max
WR high level width
tWWRH
190
ns
WR low level width
tWWRl
190
ns
CS, RS setup time
tAS
ns
CS, RS hold time
tAH
0
0
DBo-DB7 setup time
tosw
100
ns
DBo-DB7 hold time
tOHW
0
ns
DBo-'oB7 output delay time
tOOR
DBo-DB7 output hold time
150
2.0V \
o.sv?
RS
tOHR
-
rr1\
~
tAS
twROL
2.0V
ns
20
1/
CS
ns
ns
\
...
...;
I-
-J
......
tAS
~
tAH
~
f-
1\
tWROH
O.SV
J
\
tWWRH
J
B7
-
tWWRl
1/
J
\
2.0V
-
.. --
tOOR
2.4V
I
O.SV
\
tOHR
,
If
Output
O.4V
r-..
Figure 36
I
tosw
1/
>-- ~
O.SV..lr-..
-
tOHW
\
Input
I
CPU Interface (HD64645)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
501
HD63645F /HD64645F
AC Characteristics (Cont)
• • _______
--------- I
y_~
__ Z ___
- -..._- - - - -
Item
Symbol
Min
Unit
Figure
DCLK cycle time
tCYCO
100
ns
37
DCLK high level width
twOH
30
ns
DCLK low level width
twOL
30
ns
DCLK rise time
tOr
20
DCLK fall time
to!
20
ns
MCLK delay time
tOMO
60
ns
MCLK riSe time
tMr
30
ns
MCLK fall time
tM!
30
ns
MAO-MA 1 5 delay time
tMAO
150
MAO-MA 15 hold time
tMAH
RAO-RA4 delay time
tRAO
RAO-RA4 hold time
tRAH
DISPTMG delay time
tOTo
DISPTMG hold time
tOTH
CUDISP delay time
tcoo
CUDISP hold time
tCOH
Typ
Max
10
ns
ns
ns
150
10
ns
ns
150
10
ns
ns
150
10
ns
ns
CL 1 delay time
tCL10
CL 1 hold time
tCL1H
CL 1 rise time
tCL1r
50
ns
CL1 fall time
tcL1f
50
ns
MDO-MD15 setup time
tMoS
30
ns
MDO-MD15 hold time
tMOH
15
ns
150
10
ns
ns
HITACHI
502
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD63645F /HD64645F
tCYCD
DCLK
MCLK
CUDISP
CL1
MDO-MD15
(input)
Figure 37
Memory Interface
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
503
HD63645F /HD64645F
AC Characteristics (Cont)
._- .. .
"''''&.1 .L""""'.La"CI
Symbol
Min
Display data setup time
tlDS
Display data hold time
tLDH
CL2 high level width
Item
Unit
Figure
50
ns
38
100
ns
Typ
Max
twCL2H
100
ns
CL2 low level width
twCL2L
100
ns
FLM setup time
tFS
500
ns
FLM hold time
tFH
300
ns
CL1 rise time
tellr
50
ns
CL1 fall time
tCL1f
50
ns
CL2 rise time
tCL2r
50
ns
tCL2f
50
ns
CL2 fall time
Note: At fCL2
= 3 MHz
;
LUo-LU3
LOo-L03
'/
vcc- o .SV
,\
O.SV
_tLOS_
tLOH
Vcc- o .sv
CL2
o.sv
~
1\
twCL2H
twCL2l
tCL2f
tCl2r
\
Cl1
...
O.SV
tFS
4-
tFH
tcUf
tcUr
..,
FLM
vec- o .SV
t
vee-o.SV
~
O.SV
Figure 38
,
LCD Interface
HITACHI
504
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
HD63645F /HD64645F
AC Characteristics
TTL Load
Terminal
RL
OBo-OB7
2.4kO
MAO-MA15, RAO-RA4, OISPTMG, CUOISP
2.4kO
MClK
2.4 kO
11 kO
30 pF
R
C
Remarks
11 kO
130pF
tr, tf: Not specified
11kO
40pF
tr, tf: Specified
All diodes: 1S2074(\3)
Capacitive Load
Terminal
C
Remarks
Cl2
150pF
tr, tf: Specified
CL1
200pF
lUO-lU3, lOO-l03, M
150pF
FlM
50pF
1-.
0----
tr, tf: Not specified
c
r
Refer to user's manual (No. 68-1-160) and application note (No. ADE-502-003) for detail of this
product.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
505
HD64646FS-----LCD Timing Controller (LCTC)
Pin Arrangement
Description
The HDEi4646F LCTC is a modified version of
the HD64645F LCTC with different LCD
interface timing.
O_NM.q-\l)
~< ~~~~~~~«««
~~
i ~
The HD64646F is a control LSI for large size
dot matrix liquid crystal displays. The LCTC is
software compatible with the HD6845 CRTC,
since its programming method of internal
registers and memory addresses is based on
the CRTC. A display system can be easily
converted from a CRT to an LCD.
MOO
MD1
~~~~~~~~~~~~~
/:::,:e
~ ~
~ $!'II~
R ,
~
~
'$
~
~g~ ~
f.j =~~
~ RA3
tl:
ffi G/C"
MD4 ,
MD5 [I
MD6 r,
MD7
MD8 r;
MD9 c!!!
~
RA4
~GND1
~ AT
~LS
f.i~~E
MD10~
~gg~
The LCTC offers a variety of functions and
performance features such as vertical and
horizontal scrolling, and various types of
character attribute functions such as reverse
video, blinking, nondisplay (white or black),
and an OR function for simple superimposition of character and graphic displays. The
LCTC also provides DRAM refresh address
output.
A compact LCD system with a large screen
can be configured by connecting the LCTC
with the HD61104 (column driver) and the
HD61105 (common driver) by utilizing 4-bit x
2 data outputs. Power dissipation has been
lowered by adopting the CMOS process.
rD~ ~
LD2
LD1
LDO
Features
•
•
•
•
•
•
•
•
Software 'compatible with the HD6845
CRTC
Programmable screen size:
-Up to 1024 dots (height)
-Up to 4096 dots (width)
High-speed data transfer:
-Up to 20 Mbits/s in character mode
-Up to 40 Mbits/s in graphic mode
Selectable single or dual screen configuration
Programmable multiplexing duty ratio:
static to 1/512 duty cycle
Programmable character font:
-1-32 dots (height)
-8 dots (width)
Versatile character attributes: reverse
video, blinking, nondisplay (white),
nondisplay (black)
OR function: superimposing characters
and graphics display
Cursor with programmable height, blink
rate, display position, and on/off switch
•
•
•
•
•
•
•
50
DB?
-49
DBe
... DBs
., OB4
~
.. DBJ
.5 DB2
.·08,
"
~
LU3 2i
LU2 23
LU1 2-4
•
•
" ON/OFF
" MODE
51 BLE
MD13:E
MD14:!!
MD15~
•
:a
.. RAO
I
430Bo
.2
AD
4'WR
Vertical smooth scrolli1lg and horizontal
scrolling by the character
Versatile display modes programmable
by mode register or external pins: display
on/off, graphic or character, normal or
wide, attributes, and blink enable
Refresh address output for dynamic RAM
4- or 8-bit parallel data transfer between
LCTC and LCD driver
Recommended LCD driver: HD61104
(column) and HD61105 (common),
HD66204 (column) and HD66205 (common), HD66106 (column/common)
CPU interface:
80farnily
CMOS process
Single +5 V ±10%
80-pin plastic OFP (FP-80B)
Ordering Information
Type No.
Bus Tmlng Bus Interface Package
HD63645F
2 MHz
68 System
FP-80
4 MHz
80 System
FP-80
HD64646FS 4 MHz
80 System
FP-80B
HD64645F
HITACHI
506
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
HD64646FS
Differences Between HD64645F
and HD64646FS
Figure 1 and figure 2 show the relation
between display data transfer period, when
display data shift clock CL2 changes, and
display data latch clock CL1. Figure 1 shows
the case without skew function and figure 2
shows the case with skew function.
In figure 1, high period between CL2 and CLl
of HD64645F overlap. HD64646FS has no
overlap like HD64645F, and except for this
overlap. HD64646FS is the same as HD64645F
functionally.
Also for the skew function, phase relation
between CLl and CL2 changes. As figure 2
shows, data transfer period and CLl high
period of HD64646FS never overlap with the
skew function.
MCLK
________________ ______________
DISPTMG
~~
CL1
(HD64645)
---'
CL1
(HD64646)
_____________. . r.
I
~~
~r--
5S
MCLK x 16
MCLK x 11
~~------4»~----------------CL2
n nnnn nnn
(fcL2 = 2fMcLK).J
U U U U U U U 1'--------~5J---------------
Notes: f McLK = Output frequency of MCLK
fCL2 = Output frequency of CL2
Figure 1 Differences between HD64645F and HD64646FS (no skew)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
507
HD64646FS
~______________~ij________________~r--
DISPTMG
Cll
(HD64645F)
r--------------------------~~~--------------~
~
MClK x 16
Cll
_________________________.....I~5
(HD64646FS)
!
MClK x 11
1 character skew
MClK
DISPTMG
Cll
(HD64645F)
~
__________ __________________
~~~
~r--
-.Ir---~~--~--------------~~--------------~
MClK x 16
-.J'
Cll
(HD64646FS) _______________________
~
MClK x 11
Cl2
(fcL2
= f MCLK)
2 character skew
Figure 2 Differences between HD64645F and HD64646FS (skew)
HITACHI
508
Hitachi America, Ltd." Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD64646FS
Absolute Maximum Ratings
Item
Symbol
Supply voltage
Vee
Value
-0.3 to +7.0V
Terminal voltage
Yin
-0.3 to Vee +0.3 V
Operating temperature
Top.
-20'C to +75'C
Storage temperature
Tstg
-55'C to +125'C
Note
2
2
Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation
should be under recommended operating conditions (Vee = 5.0V ± 10%, GND = 0 V, Ta
= -20'C to +75'C). If these conditions are exceeded, it could affect reliability of LSI.
2. With respect to ground (GND =.0 V)
Electrical Characteristics
DC Characteristics (Vee = S.OV ±10%, GND=OV, T. = -20'C to +7S'C, unless
otherwise noted)
Item
Input high voltage
Symbol Min
RES, MODE, SKO,
SK1
VIH
DCLK, ON/OFF
All others
Input low voltage
All others
VIL
Output high voltage
TIL Interface 1
VOH
Output low voltage
CMOS Interface 1
TIL Interface
Typ Max
Vee-0.5
Vee+0.3
Unit
V
2.2
Vee+0.3
V
2.0
Vee+ 0 .3
V
-0.3
0.8
V
2.4
V
ioH=-400 ",A
Vee-0.8
V
ioH= -400 ",A
VOL
CMOS Interface
0.4
V
ioL= 1.6 rnA
0.8
V
ioL=400 ",A
Input leakage current
All inputs except
DBo-DB7
IlL
-2.5
+2.5
",A
Three state (off-state)
leakage current
DBo-DB7
ITsL
-10
+10
",A
10
rnA
Current dissipation 2
Test
Condition
Icc
Notes: 1. TIL Interface: MAO-MA15, RAO-RA4, DISPTMG, CUDISf>, DBO-DB7, MCLK
CMOS Interface: LUO-LU3, LDO-LD3, CL1, CL2, M, FLM
2. Input/output current is excluded. When input is at the intermediate level with CMOS,
excessive current flows through the input circuit to power supply. Input level must be fixed
at high or low to avoid this condition.
3. If the capacitive loads of LUO-LU3 and LDO-LD3 exceed the rating, noise over 0.8 V may
be produced on CUDISP, DISPTMG, MCLK, FLM and M. In case the loads of LUO-LU3 and
LDO-LD3 are larger than the ratings, supply signals to the LCD module through buffers.
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509
HD6.4646FS
AC Characteristics
~'PT' Tn~~~~~~
Item
Symbol
RD high level width
twAOH
Min
190
RD low level width
Typ
Max
Unit
ns
twAOL
190
ns
WR high level width
twwAH
190
ns
WR low level width
twwAL
190
ns
es,
es,
RS setup time
tAS
tAH
0
0
ns
RS hold time
tosw
100
ns
tOHW
0
ns
DBo-DB7 setup time
DBo-DB7 hold time
DBo-DB7 output delay time
tooA
DBo-DB7 output hold time
tOHA
CS
2.0V
RS
0. 8v
i
150
-\
r-
~
J
~
fAs
ns
ns
20
~ f-
ns
~
r--\
;...
-
-
J
tAS
tAH
twROL
..:
2.0V
twROH
\
0.8V
twwRL
tWWRH
-
J
B7
Figure
3
I
2.0V
-
0.8V
..
tOOR
2.4Vj
\
If
--,
Output
0.4V1\
Figure 3
~
J
tOHR
)
tosw
V
~
0.8 V"'"
-
tOHW
Input
)
CPU Interface
HITACHI
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HD64646FS
AC Characteristics (Cont}
Memory Interface
Item
DCLK cycle time
Symbol
Min
Unit
Figure
ns
4
ns
tCYCO
100
DCLK high level width
twOH
30
DCLK low level width
twOL
30
DCLK rise time
tOr
Typ
Max
ns
20
ns
ns
DCLK fall time
tOf
20
MCLK delay time
tOMO
60
ns
MCLK rise time
tMr
30
ns
MCLK fall time
tMf
30
ns
MAO-MA 15 delay time
tMAO
MAO-MA 15 hold time
tMAH
RAO-RA4 delay time
tRAO
RAO-RA4 hold time
tRAH
DLSPTMG delay time
tOTO
DISPTMG hold time
tOTH
CUDISP delay time
tcoo
CUDISP hold time
tCOH
150
ns
ns
10
150
10
ns
ns
150
10
ns
ns
150
10
ns
ns
CL 1 delay time
tCL10
CL 1 hold time
tCL1H
CL 1 rise time
teL1r
50
ns
CL1 fall time
teLIf
50
ns
MDO-MD15 setup time
tMOS
30
ns
MDO-MD15 hold time
tMOH
15
ns
150
10
ns
ns
I
HITACHI
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511
HD64646FS
tCYCD
DCLK
MCLK
CLl
MDO-MD15
(input)
Figure 4
Memory Interface
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HD64646FS
AC Characteristics (Cont)
LCD Interface 1 (at
fCL2
= 3 MHz)
Item
Typ
Symbol
Min
FLM stetup time
tFs
500
FLM hold time
tFH
300
M delay time
tOM
CL 1 high level width
tCL1H
300
ns
Clock setup time
tSCL
500
ns
Clock hold time
tHCL
100
ns
Phase difference 1
tp01
100
ns
Phase difference 2
tp02
500
ns
CL2 high level width
tCL2H
100
ns
CL2 low level width
tCL2L
100
Max
Unit
Figure
ns
5
ns
200
ns
ns
CL2 rise time
tCL2r
CL2 fall time
tCL2f
Display data setup time
tLDS
80
ns
Display data hold time
tLDH
100
ns
Display data delay time
tLOO
LCD Interface 2 (at
Item
fCL2
ns
50
ns
30
ns
=5 MHz)
Symbol
Min
FLM setup time
tFs
500
FLM hold time
tFH
500
M delay time
tOM
CL 1 high level width
50
Typ
Max
Unit
Figure
ns
Figure 5
ns
200
ns
tCL1H
300
ns
Clock setup time
tSCL
500
ns
Clock hold time
tHCL
100
ns
Phase difference 1
tp01
70
ns
Phase difference 2
tp02
500
ns
CL2 high level width
tcL2H
50
ns
tCL2L
50
ns
CL2 low level width
CL2 rise time
tcL2r
50
ns
CL2 fall time
tCL2f
50
ns
Display data setup time
tLDS
30
ns
Display data hold time
tLDH
30
ns
Display data delay time
tLDO
30
ns
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513
HD64646FS
L~~,~~~~~;~'8V
FlM
CLl
__--J/
M
____________________
_
Vcc~
O.8V _ _ _ _ _ _ _ _ _ _ __
tDM)(
Vcc-O.8V
_________
.~O~.8~V~
tCL1H---.t
Cll
1+If----tSCL--~
i4----tpD2----+I
CL2
lUO-lU4------~ ~--~~~ r-------------~~~~~ r------~
r----
LDO-lD4 ____J 1"----"1
Figure 5
LCD Interface
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HD64646FS
AC Characteristics
TTL Load
R
Terminal
RL
DBo-DB,
2.4kO
MAO-MA15, RAO-RA4, DISPTMG, CUDISP
2.4kO
MCLK
2.4kO
11 kO
30pF
C
Remarks
11 kO
130pF
tr,
11kO
40pF
~:
Not specified
tr, tf: Specified
All diodes: 1S2074®
Capacitive Load
Terminal
C
Remarks
CL2
150pF
tr, tf: Specified
CLl
200pF
LUO-LU3, LDO-LD3, M
150pF
FLM
50pF
o
tr, tf: Not specified
1
:r
HITACHI
Hitachi America, Ltd.· Hitachi Plaz'l· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
515
HD66106F----------~
(LCD Driver for High Voltage)
Pin Arrangement
Description
The HD66106F LCD driver has a high duty ratio
and many outputs for driving a large capacity dot
matrix LCD panel.
Y30
It includes 80 LCD drive circuits and can drive at up
to 1/480 duty cycle. For example, only 14 drivers
are enough to drive an LCD panel of 640 x 480 dots.
It also easily interfaces with various LCD control·
lers because of its internal automatic chip enable
signal generator.
gg;~ s.~ ~;;~~ ;;~~ ~:nQ ~~ ~~~;;Q
1......
80
2
Using this LSI sharply lowers the cost of an LCD
system.
Features
Column and row driver
80 LCD drive circuits
Multiplexing duty ratios: 1/100 to 1/480
4-bit parallel data transfer
Internal automatic chip enable signal generator
Internal standby function
Recommended LCD controller LSIs:
HD63645F and HD64645F (LCTC)
Power supply: +5 V ± 10% for the internal logic,
and 14.0 V to 37.0 V for LCD drive circuits
Operation frequency: 6.0 MHz (max.)
CMOS process
1~O-pin flat plastic package (FP-lOO)
y.
y,
y,
y,
y.
y,
y,
YI
<0 r-.. co 0"> 0 .... N M ..,. I.l';> <0 t--- co 0'> 0 51
MMC'<:I MMM ~..,...,...,. ..,...,...,...,....,. "<:I'll')
30...... N M ..,. an
MMM
(Top view)
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HD66106F
Pin Description
Power supply
Control signals
Vec, GND: Vcc supplies power to the internal
logic circuit. GND is the logic and drive ground.
CLl: The LSI latches data at the negative edge of
CLl when the LSI is used as a column driver. Fix
to GND when the LSI is used as a row driver.
VLcn : VLCO supplies power to the LCD drive cir·
cuit.
CL2: The LSI latches display data at the negative
edge of CL2 when the LSI is used as a column
driver, and shifts line select data at the negative
edge when it is used as a row driver.
VI, V2, Va, and V4: Vj·V4 supply power for driving
LCD (figure 1).
M: M changes LCD drive outputs to AC.
0 0 -0 3 : 0 0 .03 input display data for the column
driver (table 2).
Table 1 Pin Function
Symbol
Pin No.
Pin Name
Vee
49
Vee
GNO
37
Ground
V LCD
31,36
V LCD
VI
32
LCD voltage 1
V,
33
V, LCD voltage 2
V. LCD voltage 3
V.
34
V.
35
V. LCD voltage 4
CLl
38
Clock 1
CL2
40
Clock 2
M
42
M
0 0 .0.
46·43
Data 0 to data 3
SHL
39
Shift left
E
47
Enable
CAR
48
Carry
CHl
41
Channell
YI·Y. o
30·1,100·51
orive outputs 1-80
NC
50
No connection
o
a
Table 2 Relation between Display Data and
LCD State
~----~~----~--~-.v'
~
I/O
----va
------+v.
----------v,
Display Data
LCD Outputs
LCD
1 (= high level)
Selected level
On
o (=
Nonselected level
Off
low level)
V I , V,: Selected level
V., V.: Nonselected level
Figure 1 Power Supply for Driving LCD
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517
HD66106F
SBL: SHL controls the shift direction of display
data and line select data (figure 2, table 3).
LSI is used as a column driver (CHI = Vcd. CAR
outputs scan data when the TST i~ " ...1'1 ". " "0"!
driver (CHI = GND). When HD66106Fs are con·
nected in cascade, CAR connects with E of the next
LSI.
E: E inputs the enable signal when the LSI is used
as a column driver (CHI = Vcd. The LSI is dis·
abled when E is high and enabled when low. E in·
puts scan data when the LSI is used as a row driver
(CHI = GND). When HD66106Fs are connected in
cascade, E connects with CAR of the preceding LSI.
CHI: CHI selects the driver function. The chip
drives columns when CHI = Vee, and rows when
CHI =GND.
CAR: CAR outputs the enable signal when the
Y I .y80: Each Y outputs one of the four voltage
levels-VI, V2 , V 3 , or V4 -according to the com·
bination of M and display data (figure 3).
NC: NC is not used. Do not connect any wire.
Table 3 Relation between SHL and Scan Direction of Selected Line (When LSI is Used 88 a Row Driver)
SHL
Shift Oireetion of Shift Register
E
GND
-+1
E
-+2
.... 80
.... 79
Scan Oireetion of Selected Line
-+ 3 •••••••••••••••-+ 80
VI
-78.··············....·1
Yeo .... V,. .... Va ........................ VI
.... V.
F
o
.... V. • ••••••••••••••••••• -+ V.·o
00
. __
---~
DI
D2
D3
When SHL - Vee
When SHL = GND
Figure 2 Relation between SHL and Data Output (When LSI is Used
88
a Column Driver)
-I-
v,
D
D
Y output level
I
v,
I
v.
I
v.
I. v. I
Y output level
I.
v.
I
v,
+
v.
'1
When Used as a Row Driver
When Used as a Column Driver
Figure 3 Selection of LCD Drive Output Level
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HD66106F
Internal Block Diagram
LCD Drive Circuits
Latch Circuit 1
The HD66106F (figure 4) begins latching data when
tion. It latches 4 bits of data simultaneously at the
fall of CL2 and stops automatically (= standby
state) when it has latched 80 bits.
Latch circuit I is composed of twenty 4-bit parallel
data latches. It latches the display data 0 0 -0 3 at
the fall of CL2 when the LSI is used as a column
driver. The signals sent from the selector determine which 4-bit latch should latch the data.
Latch Circuit 2
Selector
When the LSI is used as a column driver, latch
circuit 2 functions as an 80-bit latch circuit. It
latches the data sent from latch circuit 1 at the
fall of CLl and transfers its outputs to the LCD
drive circuits.
The selector is composed of a 5-bit up and down
counter and a decoder. When the LSI is used as a
column driver, it generates the latch signal to be
sent to latch circuit 1, incrementing the counter at
the negative edge of CL2.
E goes low, which enables the data latching opera·
When the LSI is used as a row driver, this circuit
functions as an 80-bit bidirectional shift register.
The data sent from the E pin shifts at the fall of
CL2. When SHL = VCC, the data shifts from bit 1
to bit 80 in order of entry. When SHL = GND, the
data shifts from bit 80 to bit I.
~L.l
-
CHI
SHL
I~
It
The controller operates when the LSI is used as a
column driver. It stops data latching when twenty
pulses of CL2 have been input (= power-down
function) and automatically generates the chip
enable signal anhouncing the start of data latching
into the next LSI.
t" t t t
t t
II IJ
I
M
Controller
1123H
r Logic.
~G~2~1
CL2
I......- Logic
CLl
1,2,3,4
,", ,'1
..5~
D,-
D.
Logic
=0- ~~
II
-
-
771 7811
LCD drive circuits
79 80
1'1
t-- YLCD
t-- Vee
I-- GND
Logic
80-bit latch circuit and bidirectional
shift register (Latch circuit 2)
771781791~ I--
(j
771 1791
Latch circuit 1 (4·bit x 20)
78
80
1'1'
"t,>
II
Selector
I
Controller
Figure 4 Block Diagram .
.
HITACHI
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519
HD66106F
Functional Description
"ArL __ .T __
jI
UU""" ..,~U GiS
_
Data out!,utR ch:,"!p' :ot thp. f:oll nf f'T 1 T "t~h~-:!
data d l is transferred to the output pin YI and
d lo to Y 80 when SHL = GND. Conversely, d so is
transferred to Y I and d l to Y 80 when SHL = Vee.
The output level is selected out of V I-V4 according to the combination of display data and the
alternating signal M (figure 5).
•
a. ,""UIUUIU U£IVC£
The HD66106F begins latching data when E goes
low, which enables the data latching operation. It
latches 4 bits of data simultaneously at the fall of
CL2 and stops automatically (= standby state)
when it has latched 80 bits.
CL2
3
2
D.
~
d.
X
d,
X
D.
~
d.
X
d,
X
0,
~
d,
X
d.
X
D.
~
d.
X
d.
X
E
J
19
20
_____"X
d"
X
daD
X
-----"'1.
d"
X
d"
X
d"
X
d"
X
d"
X
d"
X
_____ -X
-----)
n
CLI
When SHL =GND
__________________~----------~X~--d.-v..
______________________________~X~--da.--
When SHL = VCIC
Y.
__________________________
v..
__~____'_____________________X
~x
daD
d.
Figure 5 Column Driver Timing Chart
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415)589-8300
HD66106F
When Used as a Row Driver
The HD66106F shifts the line scan data sent from
the pin E in order at the fall of CL2. When SHL =
Vee. data is shifted from Yl to Y80 and Y80 to Yl
when SHL = GND.
In both cases, the data delayed for 80 bits by the
shift register is output from the CAR pin to be-
come the line scan data for the next LSI (figure 6).
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819· (415) 589-8300
521
HD66106F
near GND (figure 7). Each voltage must be within
tN. tN determines the range within which RON,
i.ll1p~UilllCe or uriver's OUtput, IS stable. Note that
AV depends on power supply voltage VLCO-GND
LCD Power Supply
Thi~
~r.t1nn
p.ynh,inv thA ro!Jnl'rA nf'
...
-
-.-
-
---p-
--
f t " ..........
r-"--
,,,, .. _ _
1..,
""'-rr"J
voltage for driving LCD. V~ and V3 voltages
should be near VLCD , and V2 and V4 should be
(figure 8).
n-----~-- ~:-'"
I
av I
L------ vs
LC_-_-_-~~~~~~~~~::
- - - ' - - - - - - - - - GND
Figure 7 Driver's Output Waveform and Each Level of Voltage
Range of power supply voltage
E
6.2
>
<.....
160
40
CL2
CLl
"
Horizontal retrace period
..
f
xxxxx
~
n
CAR(LSI8)-.J
Latches LSI 8 dataIL_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---.J
~
-
::I
-.J
Latches LSI 9 data 1
~-------------------------------~
CAR(LSII0)-.1
Latches LSI 10 data I~_ _ _ _ _ _ _ _ _ _ _ _ _ ___I
CAR(LSlll)J
Latches LSI 11 data I'--_ _ _ _ _ _ _ _ _ _ _ _.......l
~
~
!"
III
~
~....
.".
g
~
Latches LSI 7 data 11..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....1
..
t:;
~
~
....
....
CAR(LSI12)J
Latches LSI 12 data
1...'_ _ _ _ _ _ _ _ _ _---1
______
. -- y,-y8~;==========
===;;================X~
~
co
~
~
~
(11
ex>
co
do
c..>
o
o
~
CAR(LSI13)J
g.
::n0'Cl
<1>
[go So
o <1>
~ ~.
:::J
.-J
i[
5'
CAR(LSI 7)~
~
....
<1>
Line
~
~
~
~
0
-. $>l
ti
g 5. g
»
""0
:::: .....
g
~
$"
OQ
Latches LSI 13 data 1....____---'
~
a.
=
<1>
J
_
<1>
S
m
m
~
o
m
'"%j
HD66106F
00
~
:>
~
;:J
u
I~
:2i
~
:>
:>
~
:)i
~
'-----v-----' '-----v-----'
:;:
:;:;
:>
~
I~(J
N
~
:>
~
:;::
Figure 11 Timing Waveform for Row Drivers (LSI 1·LSI 5)
HITACHI
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525
HD66106F
Absolute Maximum Ratings
Supply
Voltage
Item
Symbol
Rating
Unit
Logic circuits
Vee
-0.3 to +7.0
V
LCD drive circuits
V LCD
-0.3 to +38
V
Notes
I nput voltage (Logic)
-0.3 to Vcc + 0.3
V
1,2
I nput voltage (LCD drive)
-0.3 to VLCD + 0.3
V
1,3
°c
°c
Operation temperature
Topr
-20 to +75
Storage temperature
T stg
-55 to +125
Notes: 1.
2.
3.
4.
Reference point is GND (= 0 V).
Applies to the input pins for logic circuits.
Applies to the input pins for LCD drive circuits.
Using an LSI beyond its maximum rating may result in its permanent destruction. LSls should usually be used
under electrical characteristics for normal operations. Exceeding any of these limits may adversely affect reliability.
HITACHI
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HD66106F
Electrical Characteristics
DC Characteristics (VCC
=S V ± 10 %, VLCD =14 V to 37 V, Ta =_20°C to 7SoC unless otherwise noted)
Item
Symbol
Input high voltage
V IH
Pin
Input low voltage
VI!.
00-03. E. CHl
Output high voltage
VOH
CAR
Output low voltage
VOL
Vi·Yj on resistance
Min
Typ
CL 1. CL2. M. SHL. 0.8 x Vee 0
Max
Unit
Vcc
V
Tast Condition
NotH
0.2 x VCC V
VCC - 0.40.4
V
IOH = -0.4 mA
V
IOl = 0.4 mA
4
Y1-YaO. V1-V 4
3.0
kO
ION = 100 JlA
CL1.CL2.M.SHL. -5.0
5.0
IJ,A
VIN = VCC to GNO
50.0
p.A
VIN = VLCD to GNO
3.0
mA
fCL2 - 6 MHz.
(2) ILCD1
0.5
mA
fCL1 = 28 kHz
(3) 1ST
0.2
mA
At the standby state
fCL2 = 6 MHz.
fCL1 = 28 kHz
(4) ICC2
0.2
mA
fCl1 = 28 kHz.
1
(5) ILCD2
0.1
mA
fm = 35 Hz
3
RON
Input leakage current(l) IIL1
00-03. E. CHl
Input leakage current (2) IIL2
V1-V 4
-50.0
Current consumption (1) ICCl
2
Notes: 1. Input and output current is excluded. When the input is at the intermediate level in CMOS. excessive current
flows from the power supply through the input circuit. VIH and VIL must be fixed at VCC and GNO respectively
to avoid it.
2. Applies when the LSI is used as a column drivar.
3. Applies when the LSi is used as a row driver.
4. Indicates the resistance between Y pin and V pin (one of V 1. V2. V3. and V 4) when it supplies load current to
one of Y1-YaO pins.
Conditions: VLCD - GNO = 37 V
Vl. V3 = VLCD - 2/20 (VLCD - GNO)
V2. V4 = GNO + 2/20 (VLCD - GNO)
~
v,------>->>>>>>-
'---r--'
'---r--'
1st data
2nd data
F
O
01
02
03
----dL----D Fm-dL----D
'---r--'
Last data
Last data
'---r--'
'---r--'
2nd data
1st data
01
02
03
When
SHL~GNO
When
SHL~Vcc
Figure 2 Relation between SHL and Da.ta Output
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66107T
CAR outputs scan data when the LSI is used
as a row driver (CH1=GND). When
HD66107Ts are connected in cascade, CAR
connects with E of the next LSI.
BS: BS selects the number of input data bits.
When BS = Vcc, the chip latches S-bits data.
When BS = GND, the chip latches 4-bits data
via Do to D3. Fix D4 through D, to GND. .
CRt: CHI selects the driver function. The chip
TEST: Used for testing. Fixed to GND, other
devices are columns when CHI = Vcc, and
cQmmons when CHI = GND.
wise.
LCD Drive Interface
CR2: CH2 selects the number of output data
bits. The number of output data bits is 160
when CH2 = GND, and SO when CH2 = Vcc.
Table 3
SHL
Vee
GND
Yl-Yl60: Each Y outputs one of the four voltage levels-Vl, Vz, V3, V4-according to the
combination of M and display data (figure 3).
Relation between SHLand Scan DIrection of Selected Line (When LSI Is Used
as Common Driver)
Scan DIrectIOn Of Selected Line
V1....
V2....
V3....
V4------....V160
V160 .... V159 .... V15S .... V157------....Vl
Shift DIrection of Shift Register
E.... 1....
2....
3....
4 - - - - - - .... 160
E.... 160.... 1 59- 1 58- 157 - - - - - - .... 1
o
Y output level
o
I.. v, .. I" V3 ·1" V2 ·1 .. V4 ..I
I
I
I
I
Y output
level"V2 ·"V3·"V1·"V4·
I
When used as a common driver
When used as a column driver
Figure 3 Selection of LCD Driver Output Level
HITACHI
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533
3) is latched at the
falling edge of CL2. Other operations are
performed in the same way as described in
"Column Driving (i)". See figure 5 .
~ _________
CL2
E\ 1
2
.Jl5LJL ________
3
39
40
41
i~~~~~~~~~~~~~====------
D3~ _________ ~ ____________
__~________~r-\~__
Cll
CAR---------------
\~
__-.lr-
SHl= GND
yl __________________________________________________~~
\-----
~
Y160
SHl = Vee
YI __________________________________________________~~
\
YISO
--------------------------------------------------......I~
Figure 5 Column Driver Timing Chart (2)
HITACHI
...
Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
--.-.-~---.-.----
537
HD66107T
Column Driving (3)
Yl through Y40 and Y121 through Y160 remain
uncnangea .
. CH2 = Vee (SO-bit data output mode)
.• BS = Vee (S-bit data latch mode)
When CH2 is high (Vee), the HD66107T can be
used as an SO-bit column driver. In this case,
Y41 through Y120 are enabled, the states of
CL2
~
When SHL = GND, data dl is output to pin
Y41 and dao is output to Y120. Conversely, when
SHL = Vee, data d60 is output to Y41 and dl is
output to Y120. See figure 6.
_________ S1SLJL ______ _
E ~~_1_____2______3 ___
9
10
11
\~~~~~~~~~~~~~====---
D7~ _________ ~ _________
_____________-Inl.....__
Cll
-...Jr-
CA1f - - - - - - - - -
\I..-_ _
SHL = GND
y41 ______________________________________________________--J~
\
y120 ____________________
~______~----------------------__--J~·
SHL = Vee
y41 __
~----------------------------------------~----------J~
\
y120 _________________________________________________________ ~
Figure 6 Column Driver Timing Chart (3)
HITACHI
538
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane,'CA 94005-1819· (415) 589-8300
HD66107T
Column Driving (4)
• CH2 = Vcc (SO-bit data output mode)
• BS = GND (4-bit data latch mode)
CL2
When CH2 = Vee and BS = GND, 4-bit parallel data is latched, while SO-bit data is output.
The output of latched data is performed in
described in "Column Driving (3)". See figure
7.
JULJL_________ SUlJL
1
2
19
3
E\'-_____
20
21
----------------------
.i~~~~~~~~~~~~~~~~=------
D3~ _________ ~ ____________
CL1 ______________________________________-Jr-\~
____
CAR~
\\-_ _ _--11
SHL=GND
y41 __________________________________________________~~
y,l--...,.-----------------~
SHL=Vcc
~1
__________________________________________________
~~
Y120 __________________________________________________
--'~
\
II
Figure 7 Column Driver Timing Chart (4)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
539
HD66107T
When
SHL___=
Vee, l60-bit data is shifted from
v .... _ "
'I... _ _ _ _ _ _ _ _
Common Driving (1)
'1 ____
"l. .......
. CH2 = GND (tSO-bit data output mode)
The H066t07T shifts line scan data input
through E at the falling edge of CL2.
""QUI
..........g ... QQ.Q
..,. .. -
_
9 .......0 ...... t.,lI.I..&..L.I
-
.. _ .
(next stage)
SHL=Vcc
3
2
4
158
159
160
1
CL2
E
V,
n
n
V2
~
V,eo
IL
CAR
SHL=GND
(next stage)
2
3
CL2
V,eo
V'69
158
4
159
160
1
------
E
------
n
n
V,
L
CAR
Figure 8 Common Driver Timing Chart (1)
HITACHI
540
•
""""'''U, UCI.&.d Itt
shifted from Y160 to Y1. In both cases the
HD66t07T outputs the data delayed for 160
bits by the shift register through CAR,
becoming line scan data for the next IC
driver. See figure 8.
Hitachi America, Ltd. - Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD66107T
Common Driving (2)
. CH2
= Vcc (SO-bit data output mode)
When CH2 is high, the HD66107T can be used
as an SO-bit row driver. In this case, Y41 to
Y120 are enabled, while the other bits remain
unchanged.
Line scan data input through E is shifted at
the falling edge of CL2. When SHL = Vcc,
data is shifted from Y41 to Y120. Conversely,
when SHL = GND, data is shifted from Yl20 to
Y41. In both cases the HD66107T outputs the
data delayed for SO bits by the shift register
through CAR, becoming line scan data for the
next LSI. See figure 9.
(next stage)
SHL=Vcc
4
3
2
78
79
80
1
CL2
E
Y41
n
n
Y 42
)
Y 120
IL
CAR
SHL=GND
(next stage)
2
3
78
4
79
80
1
CL2
E
Y 120
Y 119
------
n
n
Y 41
IL
CAR
Figure 9
Common Driver Timing Chart (2)
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819 - (415) 589-8300
541
HD66107T
LCD Power Supply
This
SAction
Ay!",l!:linC!
'tho
!'~~!;--=-
-::~
should be near GND (figure 10). Each voltage
must be within /:;. V. /:;. V determines the range
-..;;!:~~. . V-y~~v~'" nON, i.ll.lptniance or arlvers
output, is stable. Note that /:;. V depends on
power supply voltage VLCD-GND (figure 11).
. .::::
~-=9
supply voltage for driving LCD. VI and V3
voltages should be near VLDC, and V2 and V4
n-------- ~:"
I L------ V3
!J.V
!J.V --,
r
------------v.
, LJ _______________ V
2
GND
Figure 10 Driver's Output Waveform and Each Level of Voltage
Range of power supply voltage
6.2
>
>
...
2.3 - - - - - - - - - - -
14
37
Figure 11 Power Supply Voltage VLcD-GND and /:;.V
HITACHI
542
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589·8300
al~:1
s=
n
='-
l>
I
~
III
3
o·
~ttt
1"
s=n
FLM
='-
""0
CLl
.
;;r
N
CL2
'"
N
C>
C>
C>
M
0 0 -07
:I
a 0~
""0
+37 V
t">-
0
""0
,.,.
.-
~
J:
c:;;: :t
Rl
~~
~
R2
Rl
::J
Rl
tn·
.'"'"
~
Rl
0"
l
~
Ph
l>
.j>.
~
(£:)
~
~
CJ"I
co
'f'
co
w
C>
C>
CJ"I
.j>.
W
n
,if
~
-
",-<
0
+5V
o
-a......
:r: ::1. ~
com 1
com 2
ml
HD66107T
O.e.
<0 ..... -.
,",0::S
SHL. TEST. CH2
CH1, BS
HD66107T
E
ICI7)
CAR
V LCO
Vee
~ 1 >;»
GND
..-N?'
dd:E &
I
I
11II
C>
C>
T.
000-
CD
EP ~
»»od:2 &
C")
(£:)
III
V,
V,
~
:c
;;J
~
'tI
~
~:§~~ml~~ ~
!::
!'l-
en
ro'
CD '" .....
-Ill
::s~
:c
V"~
Notes 1. R1 and R2 are specified depending on the type of LCD panel. When using an LCD panel with 1/20 bias, R1/(4R1 + R2)
must be 1/20, i.e., R1 = 3kQ and R2 = 4BkQ.
Notes 2. When designing a board, place capacitors close to each LSI in order to stabilize power supply. It is recommended to use
two O.l#F capacitors per LSI; one is connected between Vce and GND, and the other between VLCD and GND.
Figure 12 Application Example
s
0')
0')
.....
o-...]
t-3
HD66107T
Waveform Ezamples
,.._, •• __ n_I_I __
----- -------.
o
"'I
1
1
...J
U
....
o
2
-;:
1
o·
o
1
-;:
FigUre13 ColUmn Driver Timing Chart (1)
HITACHI
544
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66107T
Common Driving
CD
0
~
.,
E
!!
u.
en
~
co
~
§
I
I
I
I
§
~
u
::;;
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
.. ->
;; >' >.. >N ;; >'" >
I
Ia:5
N
§
I
I
I
I
I
I
I
;; >' :>
;;:
->
Figure 14 Common Driver Timing Chart
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
545
HD66107T
Absolute Maximum Rating
Svmbol
Ratina
Unit
Vcc
VLCD
-0.3- +7.0
V
-0.5-+38
V
Input voltage (1)
Vn
-0.3- Vcc+0.3
V
1, 2
Input voltage (2)
VT2
V
1, 3
Operation temperature
Topr
-0.3-VLCD+0.3
-20-+75
'C
Storage temperature
T.'9
-55-+125
'C
Item
Power supply voltage
Logic circuit
LCD drive circuit
Notes: 1.
2.
3.
4.
NotA
Reference point is GND (= OV).
Applies to input pins for logic circuit.
Applies to input pins for LCD drive circuits.
If the LSI is used beyond absolute maximum ratings, it may be permanently damaged. It
should always be used within the above electrical characteristics to prevent malfunction or
degradation of the LSI's reliability.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66107T
Electrical Characteristics
DC Characteristics (Vcc
Item
Input high voltage
=S V
± 10%, VLCD
= 14 to 37 V, Ta = -20 to 7S0C)
Output high voltage
Symbol Pins
Min.
CL1, CL2, M 0.8 x Vcc
SHL, as, CH2,
TEST, 00-07, 0
Vil
E, CH1
CAR
Vcc-0.4
VOH
Output low voltage
VOL
Vi - Vj on resistance
RON
Input leak current (1 )
IILl
Input leak current (2)
hl2
Input low voltage
Power dissipation (1)
Power dissipation (2)
Power dissipation (3)
VIH
Y1-Y160,
V1-V4
-5.0
CL1, CL2, M
SHL, as, CH2,
TEST, 00-07,
E, CH1
V1-V4
-100
Max.
Vcc
Unit
V
V
10H=-0.4 mA
0.4
V
10L =0.4 mA
3.0
kO
10N= 150 pA
5.0
pA
VIN=Vcc-GNO
100
pA
VIN=VLCO-GNO
Icc,
5.0
mA
fcL2=8 MHz
IlCO'
1ST
2.0
mA
tCLl =28 kHz
2
0.5
mA
In standby
mode:
fcl2=8 MHz,
tCLl =28 kHz
1
2
tfel' =28 kHz
tm=35 Hz
3
Power dissipation (4)
ICC2
1.0
mA
IlC02
0.5
mA
2.
3.
Nota
0.2 x Vcc V
Power dissipation (5)
Notes:1.
Condition
1
Input and output current is excluded. When an input is at the intermediate level is CMOS,
excessive current flows from the power supply though the input circuit. To avoid it, VIH and
\til must be fixed to Vcc and GND respectively.
Applies to column driving.
Applies to row driving.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
547
HD66107T
AC Characteristics (Vee = 5 V ± 10%, VLCD = 14 to 37 V,I Ta = -20 to 75'C)
,.._'1 ________ ••
_ " . . . . . . . . . . . . . . . & V •••
y
Item
Symbol
Pin name
Min.
Clock cycle time
teye
CL2
125
Clock high-level width
Max.
Unit
tcwH
CL2
30
ns
Clock low-level width
tCWL
CL2
30
ns
Clock setup time
tSCL
CL2
200
ns
tHCL
tct
CL2
200
ns
CL1, CL2
tosu
00-07
30
Clock hold time
Clock rising/falling time
Data setup time
Note
ns
30
ns
ns
Data hold time
tOH
00-07
30
ns
E setup time
tESU
E
25
ns
Output delay time
tOCAR
CAR
70
ns
M phase difference
tCM
M, CL1
300
ns
Notes: 1. Specified when connecting the load circuit shown in figure 15.
Test point Or-----,
ISO"
Figure 15 Test Circuit
HITACHI·
548
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66107T
I~"-"'"'v:t_L__.,. -__
CL1 _ _ _ _ _ _ _
CL2
-----",
tCWH
tCt
tCt
00-7
CL1
CL2
CAR ______________
~-J
M
Figure 16 Controller Interface of Column Driver
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005 c1819 • (415) 589-8300
549
HD66107T
Common Driving
MAY,
Symbol
Pin nama
Min,
Clock low-level width
twL1
CL2
5
ps
Clock high-level width
twHl
CL2
60
ns
Data setup time
tos
tOH
100
30
ns
Data hold time
E
E
Data output delay time
too
CAR
Data output hold time
tOHw
CAR
Clock rising/falling time
tet
CL2
Item
I'ni.
III ......
ns
3
pS
30
ns
30
ns
CL2
Input data
CAR
Output data
---+--_--/
Figure 17 Controller Interface of Common Driver
HITACHI
550
Hitachi America, Ltd.· Hitachi Plaza ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T-----(RAM-Provided 165-Channel LCD Driver
for Liquid-Crystal Dot Matrix Graphics)
Description
The HD66 108T under control of an 8-bit MPU
can drive a dot matrix graphic LCD (liquid-crystal
display) employing bit-mapped display with support
of an 8-bit MPU.
Use of the HD66 108T enables a simple LCD system
to be configured with only a small number of chips,
since it has all the functions required for driving the
display.
The HD66108T also enables highly-flexible display
selection due to the bit-mapped method, in which one
bit of data in a display RAM turns one dot of an LCD
panel on or off. A single HD66108T can display a
maximum of 100 x 65 dots by using its on-chip 165
x 65-bit RAM. Also, by using several HD66108T's,
a display can be further expanded.
The HD66 108T employs the CMOS process and
TAB package. Thus, if used together with an MPU, it
can provide the means for a battery-driven pocketsize graphic display device utilizing the low current
consumption of LCDs.
• Seven types of multiplexing duty ratios can be
selected: 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, 1/66
Notes: The maximum number of row outputs is 65.
• Built-in bit-mapped display RAM: 10 kbits (165 x
65 bits)
• The word length of display data can be selected
according to the character font: 8-bit or 6-bit
• A standby operation is available
• The display can be extended through a multi-chip
operation
• A built-in CR oscillator
• An 80-system CPU interface: cI> = 4 MHz
• Power supply voltage for operation: 2.7 V to 6.0 V
• LCD driving voltage: 6.0 V to 15.0 V
• Low current consumption: 400 ~A max (at fose =
500 kHz, fose is external clock frequency)
• Package: 208-pin TCP (Tape-Carrier Package)
Features
• Four types of LCD driving circuit configurations
can be selected:
Configuration Type
No. of
Column No. of Row
Outputs Outputs
Column outputs only
165
0
Row outputs from the
left and right sides
100
65 (from left: 32,
from right: 33)
Row outputs from the
right side 1
100
65
Row outputs from the
right side 2
132
33
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
551
HD66108T
Chip terminals
..
~------------------------------------------~
~49
159
93
Xl15
208
24
X164
I
I
o
I
Note: The above view is seen from the grinded surface of the chip. not TCP.
HITACHI
552
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
Pin Description
Classification
Power
Supply
CPU
Interface
No.
of Pins
8,9,35,36
12 - 14
1,43
2, 7
37,42
4,5
6,39,38
3,40,41
23
Symbol
1/0
No.
of Pins
Voo 1- Voo4
GND1-GND3
Vee 1, Vee2
4
V6L, V1L,
V1R, V6R,
V4, V3,
VMH1-VMH3,
VML1-VML3
12
3
2
CS
25
26
24
27-34
WR
RD
RS
DBO-DB7
1/0
1
8
LCD Driving
Output
44-208
XO-X164
0
165
LCD
Interface
21
FLM
I/O
20
CL1
1/0
22
M
1/0
10
11
OSC1
OSC2
I
0
19
CO
0
18
MIS
17
RESET
15,16
TESn,
TEST2
Control
Signals
2
Function
Connect these pins to V00.
Ground these pins.
These pins supply power to the LCD driving
circuits and should usually be set to the V6
level.
Apply an LCD driving voltage V1 to V6 to
these pins.
Input a chip select signal via this pin. A CPU
can access the HD66108Ts internal
registers only while the CS signal is low.
Input a write enable signal via this pin.
Input a read enable signal via this pin.
Input a register select signal via this pin.
Data is transferred between the HD66108T
and a CPU via these pins.
These pins output LCD driving signals.
The XO-X31 and X100-X164 pins are
column Irow common pins and output row
driving signals when so programmed. X32X99 pins are column pins.
This pin outputs a first line marker when the
HD66108T is a master chip and inputs the
signal when the chie is a slave chip.
This pin outputs latch clock pulses of display
data when the chip is a master chip and
inputs clock CL1 pulses when the chip is a
slave chip.
This pin outputs or inputs an M signal, which
converts LCD driving outputs to AC; it
outputs the signal when the HD66108T is a
master chip and inputs the signal when the
chip is a slave chip.
Input system clock pulses via this pin.
This pin outputs clock pulses generated by
the internal CR oscillator.
This pin outputs the same clock pulses as
the system clock pulses, the OSC1 pin of a
slave chip.
Connect with the OSC1 ~in of a slave chi~.
This pin specifies masterlslave. Set this pin
low when the HD66108T is a master chip
and set high when the chip is a slave chip;
must not be changed after power-on.
Input a reset signal via this pin. Setting this
Qin low initializes the HD66108T.
These pins input a test signal and should
usually be set low.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
---
---~----
553
I
HD66108T
Internal Block Diagram
VMl1 VMH1
Vee1 V6l V4
V3
V1 Vee1
Xo
X31X32
X99X100
X164
VMH3 VML3
V6 R
Vcc4 V1 VMH2 VHL2 Vcc2
Data latch circuit
2
165 x 65·bit display memory
Y decoder
3
Vcc2·Vcc3 - - - - [ >
GND1·GND3
-----.7),
M"
CL1 ..
FLM ..
MS
RESET
...
..
.
CO
OSC2
OSC1
TEST1
TEST2
..
CS WRRD RS
DB7·DBO
HITACHI
554
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
HD66108T
Register List
~
Reg. No. Reg.
Register Read,f-_..,--_--r-_-.-_-r=-----,_ _,-_..,--_---j
CS RS 2 1 0 Symbol Name Wrl
Invalid
0
0
- -
-
AR
0
1
0
0
o
DRAM Display
Memory
0
1
0
0
1 XAR
0
1
0
1
o
YAR
Address
0
1
1 FCR
Control
0
1
1
0
o
Mode
0
1
1
0
1 CSR
C select
o
1
1
1
0 -
Invalid
8 clocks max
None
1.5 clocks max
YAD
Y
address
1
01111-
DO
X
address
0
MDR
time
-
None
1.5 clocks max
DUTY
DWS
None
None
None
Invalid
Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading
these bits returns O.
2. DRAM is not actually a register but can be handled as one.
3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits ofthe display memory
register.
4. DRAM must not be written to or read from until a time period of tell has elapsed rewriting
the DUTY bit of FCR or the FFS bit of MDR. tCLl can be obtained from the following
equation; in general, a time period of 1rns or greater is sufficient if the frame frequency is
60-90 Hz.
tCL1 =
Ni.fc~~kHZ) (ms) --- Equation 1
D2 (duty correction value 2) : 192 (duty = 1/32, 1/34, or 1/36)
128 (duty = 1/48 or 1/50)
96 (duty = 1/64 or 1/66)
Ni (frequency-division ratio specified by the mode register's FFS bits)
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
Refer to "6. Clock and Frame Frequency."
fClK :
Input clock frequency (kHz)
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555
I
HD66108T
System Description
The HD6610RT
p~n ~CC~!!~ ~ ~~~~~~~ :;~ ~5 :;~!
of 165 channels to row outputs for LCD driving
. It also incorporates a timing generator and display
memory, which are necessary to drive an LCD.
If connected to an MPU and supplied with LCD
driving voltage, one HD66I08T chip can be used
to configure an LCD system with a 100 x 65 dot
panel (figure 1). In this case, clock pulses should
be supplied by the internal CR oscillator or the
MPU.
CLi, rLM, ana M
enables the display size to be expanded. In this case,
LCD expansion signal pins output corresponding
signals when pin MIS is set low for master mode
and conversely input corresponding signals when
pin MIS is set high for slave mode; LCD expansion
signal pins of both master chip and slave chips must
be mutually connected. Figure 2 shows a basic
system configuration using two HD66108T chips.
!].;i.l.l6 ~C::) ~A..,uu~ivlI ~igllai.s
100 x 65-dot LCD
100-column output
MPU
HD66108T
LCD driving
power supply
Figure 1 Basic System Configuration (1)
HITACHI
556
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HD66108T
[
265
x 65-dot LCD
MPU
Figure 2 Basic System Configuration (2)
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HD66108T
Functional Description
1. Display Size Programming
A variety of display sizes can be programmed by
changing the system configuration and internal
register settings.
(1) System Configuration Using 1 HD66108T
Chip
When the 65-row-output mode is selected by internal
register settings, a maximum of 100 dots in the X
direction can be displayed (figure 3 (a». Display
size in the Y direction can be selected from 32 ,
34, 36, 48, 50, 64 , and 65 dots according to display
duty setting. Note that Y direction settings does not
affect those in the X direction (100 dots).
When the 33-row-output mode is selected by internal
register settings, a maximum of 132 dots in the X
direction can be displayed (figure 3 (b».
sizes and the control register's (FCR) ROS and
DUTY bits. ROS and DUTY bit settings determine
the function of X pins. For more details, refer to
.. 4.1 Row Output Pin Selection."
(2) System Configuration Using 1 HD66108T
Chip and 1 HD61203 Chip as Row Driver
A maximum of 64 dots in the Y direction and 165
dots in the X direction can be displayed. 48 or 64
dots in the Y direction can be selected by HD61203
pin settings (figure 3 (c».
(3) System Configuration Using 2 or more
HD66108T Chips
X direction size can be expanded by 165 dots per
chip. Figure 3 (d) shows a 265 x 65-dot display.
Y direction size can be expanded up to 130 dots
with 2 chips; a 100 x 130-dot display provided by
2 chips is shown in figure 3 (e).
Table 1 shows the relationship between display
Table 1 Relationship between Display Size and Register Settings (No. of Dots)
ROS Bit Setting
(Xo-X164 Pin Function)
Duty Bit Setting (Multiplexing Duty Ratio)
1132
1/34
1/36
1/48
1/50
1164
1/66
165-column-output
Specified by a row driver
55-row-output from the
right side
X: 100
Y: 32
X: 100
Y:34
X: 100
Y:36
X: 100
Y:48
X: 100
Y: 50
X: 100
Y: 64
X: 100
Y:55
65-row-output from the
left and right sides
X: 100
Y: 32
X: 100
Y:34
X: 100
Y: 36
X: 100
Y:48
X:100
Y:50
X: 100
Y: 64
X: 100
Y:65
33-row-output from the
right side
X: 132
Y:32
X: 132
Y:33
X: 132
Y: 33
X: 132
Y:33
X: 132
Y:33
X: 132
Y: 33
X: 132
Y:33
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HD66108T
~X: 100dots-?!
~rr---X: 132 dots----?l~
T
Y: 65
~
I
J33
~
____________~ 1do~
________----'. .J.. do~
(b) Configuration Using 1 HD66108T Chip (2)
(33-Row Output from the Right Side)
(a) Configuration Using 1 HD66108T Chip (1)
(65-Row Output from the Right Side)
IE-~- - - - X : 165 do~ ---~~
T
Y: 64
L-________________________
~1 oo~
(e) Configuration Using 1 HD66108T Chip and 1 HD61203 as Row Driver
(165-Column Output)
IE-~-----------------X: 265 do~ -----------------il~
:
I
Area displayed by
~_____e_h_iP_1_______·________~!
___
Area displayed by
T
Y: 65
m
__iP_2________~ldo~
(d) Configuration Using 2 HD66108T Chips (1)
IE--- X:
100 dots ~
Area displayed by
chip 1
I
'-------' I
______________ Y: 130
dO~
Area displayed
by chip 2
(e) Configuration Using 2 HD66108T Chips (2)
Figure 3 Relationship between System Configurations and Display Sizes
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559
HD66108T
2. Display Memory Construction and Word
Length Setting
the right side, and is X32 in the 65-row-output mode
from the left and right sides.
The HD66108T has a bit-mapped display memory
of 165 x 65 bits. As shown in figure 4, data from
the MPU is stored in the display memory, with the
MSB (most significant bit) on the left and the LSB
(least significant bit) on the right.
Each display area contains the number of dots shown
in table 1, beginning from each start address.
The sections on the LCD panel corresponding to
the display memory bits in which 1 's are written
will be displayed as on (black).
Display area size of the internal RAM is determined
by control register (FCR) settings (refer to table 1).
The start address in the Y direction for the display
area is always YO, independent of the register setting.
In contrast, the start address in the X direction is
XO in the modes for 165-column-output, 65 -rowoutput from the right side, and 33-row-output from
For more detail, refer to .. 4.2 Row Output Data
Setting, .. figures 15 to 19.
In the display memory, one X address is assigned
to each word of 8 or 6 bits long in X direction.
(Either 8 or 6 bits can be selected as word length
of display data.) Similarly, one Y address is assigned
to each row in Y direction.
Accordingly, X address 20 in the case of 8-bit word
and X address 27· in the case of 6-bit word have
5 and 3 bits of display data, respectively.
Nevertheless, data is also stored here with the MSB
on the left (figure 5).
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HD66108T
Disp'layon
I
COM1 ~~~~~~~_
CO~2r+~~-r~-r~
165 x 65 -dot LCD
COM65~:~.~.~.~.~.~.~.------------------~
; ~ 1 ~ ~ i 1
.
···· ......
......
..
..
..
..
..
. ....
XOX1 X2X3X4X5X6X7
YO
Xl64
1101110101110111
087
080
(MSS;·················· (LSB)
165x65-bit
display memory
YM~
____________________________
~
Figure 4 Relationship between Memory Construction and Display
($00)
0
0($00)
1($01)
($01)
1
($02)
2
11111111
8 bit
.........................
.....................
X address
($13) ($14)
19
20
($12)
18
11111
.......................
I
I
I
......................
62($3E)
63($3F)
Yaddress
.....................
.....................
(a) Address Assig ment When 1 Word is 8 Bits Long
I
I
I
($00) ($01) ($02) ($03)
0
1
2
3
.................
I
I
X address
($18) ($19) ($1 A)($1 B)
24
25 26 27
..................... -.
1($01) 1""11
6bit
0($00)
....................
I
1"1
..................
62~~) I I I I I .................
...................... I I
II
·
·
..
..
63($3F)
Yaddress
.
..
I I I
I
(b) Address Assignment When 1 Word is 6 Bits Long
Figure 5 Display Memory Addresses
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561
HD66108T
3. Display Data Write
(4)
..A..:
(1)
Access
Figure 6 shows the relationship between the
address register (AR) and internal registers
and display memory in the HD661 08T. Display
memory shall be referred to as a data register
since it can be handled as other registers.
To access a data register, the register address
assigned to the desired register must be written
into the address register's Register No.bits.
The MPU will access only that register until
the register address is updated.
(2)
(3)
Busy Check
A busy time period appears after display
memory read/write or X or Y address register
write, since post-access processing is
performed synchronously with internal clock
pulses. Updating data in registers other than
the address register is disabled during this
time. Subsequent data must be input after
confirming ready mode by reading the address
register. The busy time period is a maximum
of 8 clock pulses after display memory read/
write and a maximum of 1.5 clock pulses after
X or Y address register write (figure 7).
Limitations on Access
:;!;~-.-. .-;:;.~;., ~6~&-~ ~,
i.;l";;;
";i~"~i1)'
UICIIJUCY
must not
be rewritten until a time period of tCLl or longer
has elapsed after rewriting the control register's
DUTY bits orthe mode register's FFS bits. However,
display memory and registers other than the control
register and mode register can be accessed even
during this time period. tCLl can be obtained from
the following equation. If using an LSI with a frame
frequency of 60 Hz or greater, a time period of 1
ms should be sufficient.
t
=
CLI
D2
Ni.fCLK (kHz)
(ms) ... Equation 1
D2 ( duty correction value 2 ) :
192 (duty = 1/32, 1/34, or 1/36)
128 (duty = 1/48 or 1/50 )
96 (duty = 1/64 or 1/66 )
Ni ( frequency-division ratio specified by the mode
register's FFS bits)
2, I, 1/2, 1/3, 1/4, 1/6, or 1/8
fCLK
: Input clock frequency (kHz)
Dummy Read
When reading out display data, the data which
is read out immediately after setting the X and
Y addresses is invalid. Valid data can be read
out after one dummy read, which is performed
after setting the X and Y addresses desired
(figure 8).
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HD66108T
Registers accessible with pin RS .. 0
Address register
o
2
Bit
Register No.
Registers accessible with pin RS .. 1
Data re isters
Figure 6 Relationship between Address Register and Register No.
I
HD66108T
:
I
I
esc:
I
I
I
I
BUSY FLAG
--II
!-I------
i-!_ _
I
I
:
Ready
:
~;..
Busy 8 clock pluses max
: Ready
~; . .
i
1--------
I
Intemal :
operation Ii-I---':':---1
Operates intemally
•
--------'---------:--------..:..-..j.j
.......-~----...:....,__--..~'*i ---------------CPU
: :
WR
~i~---------------------_4--------------
Ur:
u
RS
DB7
u
u
u
iI
n
n~~n~__~n~~________
Figure 7 Relationship between Clock Pulses and Busy Time ( Updating Display Data )
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------- ..
~-
563
..--.- ..~~~~~
c.n
.,..
8
C>
0)
0)
::I:
.....
s=
o
n
2:
00
l=-
~
3
CD
:::l.
n
!"
!::;
?-
CS
::I:.
~
2:
""1:J
;;;-
Iri
&l
•
i')
0
0
t:I
a;.~.
~ ~.
;g :-I ~
;s. ~
WR
a:
II
DB
~ - ~51
(Accessed
register)
~
Output data
..
tD
::::!.
en
(")
r::r
l
::::I
_CD
cii"
'"
(")
l=-
.,..eo
0
0
'!:.
~
eo
~
~
c.n
co
%
w
0
0
ULJ
ULJ
U
RD
~ J: EI
.-+
~--,r-
RS
CO
~
I~---------------------------------
XandY
addresses
---------«
(lIm.-)
X.
(lIm.Yn)
X
(Xm+l.Yn)
X
(Xm<2,Vn)
X
HD66108T
Rewriting DUTY or FFS bits
Accessing other registers
Rewriting display memory
Figure 9 Rewriting Display Memory after Rewriting Registers
3.2 X and Y Address Counter Auto-Incrementing
Function
As described in "2. Display Memory Construction
and Word Length Setting, " the HD66108T display
memory has X and Y addresses. Internal X address
counter and Y address counter both employ an autoincrementing function. After display data is read or
written, the X or Y address is incremented according
to the address increment direction selected by internal
register.
Although X addresses up to 20 are valid when 8 bits
make up' one word ( up to 27 when 6 bits make up one
word ), the X address counter can count up to 31 since
it is a 5-bit free counter. Similarly, although Y addresses
up to 64 are valid, the Y address counter can count up
to 127. Consequently, X or Y address must be re-set
at an appropriate point as shown in figure 10.
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HD66108T
X address counted
•
o
+
+
2
1
L
l
Set address
Write display data
Valid addresses
+
20--1
Re-set X address
+
21
Dummy readlwrite
Invalid addresses
31
V
~------------------~
(1) Example of X Address Counter Increment
(Word Length: 8 bits)
Y address counted
~
+
1
Set address
Write display data
+
2
Valid display area
+
31--1
+
32
Re-set Y address
Dummy readlwrite
I
I
I
I
I
I
I
Invalid display area
I
I
I
I
I
+
~
127
I~------------------~
(2) Example of Y Address Counter Increment
(Multiplexing duty ratio: 1132)
Figure 10 X/'l Address Counter Increment
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HD66108T
4. Selection for LCD Driving Circuit Configuration
4.1 Row Output Pin Selection
The HD 661 08T can assign a maximum of 65 pins for
row outputs among the 165 pins named XO-Xl64.
The XO-X 164 pins can be classified into four blocks
labeled A, B, C, and D (figure 11 (a)). Blocks A, C,
and D consist of row/column common pins and block
B consists of column pins only. The output function
of the LCD driving pins and the combination of
blocks can be selected by internal registers.
Figure 11 shows an example of 165-column-output
mode. This configuration is useful when using more
than 1 HD66108T chip or using the HD66108T as a
slave chip of the HD61203.
Figure 12 shows an example of 65-row-output mode
from the right side. Blocks A and B are used for
column output and blocks C andD (X100-Xl64 pins)
for row output. This configuration offersan easy way
of connecting row output lines in the case of using one
or more HD66108T chips.
Figure 13 shows an example of 65-row-output mode
from the left and right sides. 32 pins of XO-X31 and
33 pins ofX132-Xl64 are used for row output here.
This configuration offers an easy way of connecting
row output lines in the case of using only one
HD66108T chip.
Figure 14 shows an example of 33-row-output mode
from the right side. Block D, i.e., X 132-Xl64 pins, is
used for row outputs. This configuration provides a
means for assigning many pins to column outputs
when 1/32 or 1/34 multiplexing duty ratio is desired.
In all modes, it is row data and multiplexing duty ratio
that determine which pins are actually used among the
pins assigned to row output. Y values shown in table
1 indicate the numbers of pins that are actually used.
Pins not used must be left disconnected.
I
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567
HD66108T
X132------------ X164
~ ------------------. ~9
X100------------ X131
XO ------------ X31
t
i
+
4
Column driver
Column driver
Column driver
Column driver
Block A
BlockB
BlockC
Block D
(a) LCD Driving Circuit Configuration
r - - - - - - - --.
I
I
I
I
I
I,
, ___ I \
I
I
I
Row
driver
\
:
"
I
I
I
I
I
r - -""
I
LCD
I
V
L ________ _I
HD66108T
(b) System Configuration
Figure 11 165-Column-Output Mode
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HD66108T
f ------------
~
X3.
-----------------_.
X132------------ Xl64
~
Xl00 ------------ X131
i
+
Column driver
Column driver
Row driver
Row driver
Block A
Block B
BlockC
Block 0
(a) LCD Driving Circuit Configuration
LCD
HD66108T
(b) System Configuration
Figure 12 65.Row·Output Mode from the Right Side
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I
HD66108T
~------------------.~
•
XI32- - - -- - --- - - -XUI"
Xl00 ------------ X131
XO ------------ X31
•
+1
Rowdrive~
Column driver
Column driver
Row driver
Block A
BlockB
BlockC
Block 0
(a) LCD Driving Circuit Configuration
LCD
HD66108T
(b) System Configuration
Figure 13 65-Row-Output Mode from the Left and Right Sides
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HD66108T
r- - - - - - 1
~------------------.~
x31
ro------------
X132-------- ----X164
X13i
Column driver
Column driver
Column driver
Row driver
Block A
Block B
BlockC
Block 0
(a) LCD Driving Circuit Configuration
LCD
HD66108T
(b) System Configuration
I
Figure 14 33-Row-Output-Mode from the Right Side
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571
HD66108T
4.2 Row Output Data Setting
and protected areas.
If certain LCD driving output pins are assigned to row
output, data must be written to display memory for
row output. The specific area to which this data must
be written depends on the row-output mode and the
procedure of writing row data to the display memory
(0 or 1 to which bits?) depends on which X pin drives
which line of the LCD. Row data area is determined
by the control register's (FCR) ROS and DUTY bits
and is identical to the protected area, which will be
described below. (165-column-output mode has no
protected area, thus requiring no row data to be
written (figure 15).)
Procedure of writing row data to the display memory
is as follows. First, 1 must be written to the bit at the
intersection between line Yj and line (column) Xi
(column). Line Yj is filled with data to be displayed
on the first line of the LCD and line Xi is connected to
pin Xn, which drives the first line of the .LCD.
Following this, Os must be written to the remaining
bits on line Yj in the row data area. This rule applies
to subsequent lines on the LCD.
Figure 16 shows the relationship between row data
and display. Here the mode is 65-row output from the
right side. Display data on YO is displayed on the first
line of the LCD and data on Y64 is displayed on the
65th line of the LCD. IfXI64 is connected to the first
line of the LCD and Xl 00 is connected to the 65th line
of the LCD, Is must be written to the bits on the
diagonal line between coordinates (XI64, YO) and
(Xl00, Y64) and Os to the remaining bits. Row data
protect function must be turned off before writing row
data and be turned on after writing row data. Turning
on the row data protect function disables read/write of
display memory area corresponding to the row output
pins, i.e., prevents row data from being destroyed. In
figure 16, display memory area corresponding to pins
Xl00 to XI64 is protected.
Figures 17 to 19 show examples of row data settings.
Some multiplexing duty ratios result in invalid display
areas. Although an invalid display area can be read
from or written to, it will not be displayed.
Table 2 shows the relationship between FCR settings
Table 2 Relationship between FCR Settings and Protected Areas
Control Register (FCR)
ROS
LCD Driving Signal Output Pins Connected to
PON 4 3 Mode
0 0 165-column
0
65-row (R)
Protected Area of Display Memory
Figures
No area protected
15
X100-X164
16,19
0 65-row (LlR)
XO-X31 and X132-X164
17
1 33-row (R)
X132-X164
18
65-row (R)
: 65-row-output mode from the right side
65-row (LlR) : 65-row-output mode from the left and right sides
33-row (R)
: 33-row-output mode from the right side
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HD66108T
Control register ROS bit = 00
DUTY bit = 101
LCD dnving voltages:
VMH1 = V3, VML 1 = V4,
VMH2 = V3, VML2 = V4,
VMH3 = V3, VML3 = V4
X31~••
XO
Column driver
:
,
Block A (32 bits)
Column driver
:
,
Xl64
• ••X99 Xl00•••
Block B (68 bits)
,,
,
,
Column driver
Block C (32 bits)
,,
,
,,,
,,
Column driver
Block 0 (33 bits)
,, 4 bits + 3 bytes + 4 bits + 3 bytes +
X address:
:
,
, 4 bits
:
4 bytes
:
8 bytes + 4 bits
5 bits
11
I
17 I 18 I 19 I 20
4
I
I
......;0~1~1'-.L1-=2...L.1~3-I1-.-:!...L_____.L-!.!...JL...!i:.....L-:.:::.....L....!.:!.-1-..!:!....l-r-J.....!.!....J....!!:....J.~...L.T_.J
8 bits/1 word 1
1:2 I 13 I 14 I 15 I
I
, 5 words + 2 bits : 4 bits + 10 words + 4 bits ,, 2 bits + 5 words , 5 words + 3 bits ,
6 bitsJ1 wordiI--::-0'1-'1:-01-:2:-110::,-~-..,.----,-:-;;-~~:;:;-r-:-;:-..-::-r:;;::-r-:::-iI-;;;;-.-:;::-r;;-:-r~r;;::-r';;:;"1
3 "'1-4;-01"-;:'51
I 15 I 161 17118 119 I 20 I 211 22 1 231 24 I 25 I 281 '271
6 I
t6
,
,
,
165 x 64-dot LCD
--------------------------H-+_+_
--------------------------H-+__
1
Yl
0 0
0 -------------------------Y21-:-H
1 HlH....,o:+--------- ------------------t-:-+--:+--:H~
Y31-1:+::1
1 -'0*- - - - - - - - - - - - - - - - - - - - - - - - 0 1-::10r-:i
-I-:-t-::I-::I-::lf-::-l
Y41-1:+",0MOf-:ll""0'+-- ------ -------------- ----hhl-:::l--=lh:-!
H-+-+-+-+--------------------------r--;H-+-I--I
Display data
Valid
display area
I+-!-+--!--!--!-----!-~J
Y62
Y63 I-=-HI-:-li-:-l-,:+Y64'--_ _ _ _ _ _....::.:.:..==:==c..::::=-_ _ _ _ _ _--'
Invalid
display area
Figure 15 Relationship between Row Data and Display
(165-Column Output, 1/64 Multiplexing Duty Ratio)
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HD66108T
Control register ROS bit =01
DUTY bit = 110
LCD driving voltages:
VMH1 = V3, VML 1 =V4,
VMH2 = V2, VML2 = V5,
VMH3 =V2, VML3 =V5
xo•.•
Column driver
X address ,
:
,
:
..)(131 X13a
•• 2<99 X100 .•.
•••X31X3a ••
Row driver
Column driver
Row driver
,
;--8 bYles + 4 bits
: 4 bits + 3 bytes +
' 4 bits
:
4 b~tes
:
'
5 words + 2 bits
:
4 bits + 10 words + 4 bits
2 bits + 5 words
:
8 bitsJ1 word 1-1"""0:--11--';'1':::;"'1=::-2-'-1"""3=-11--:4-01-::_:::::
6 bitsl1 word 1-10"""1-1"-"'1-:2-r1-:3-'-1"-4'1..i.'5:-T1-'6:-T"1-::::::==
..1<164
Row data pro
ad blocks
'
I 11 I 1~ I 13 1 14 I 15 I 1:6 I 17 I 18
:
---i
4 bits+ 3 bytes+
:
5b i t s :
19 I 20
5 words + 3 bits
!
115 11~ 117118 119 I 20 I 21122 123 I 24 I 251 261'271
100 x 65·dot LCD
--------------------+-+-+-+-
i-"-1-'-i1-"1r-11-"+ - - - - - - - - - - - - - - - - - - - - +'-+'-+'-+-"-+-"-1-"-11-"-11-"+
I-'-I-"-II-""HI-"+ - - - - - - - - - - - - - - - - - - - - +'-¥-+"-+-'-I-"-I-"-II-"-II-"+
I-'-I-'-iI-"1HI-"+ ____________________ +''-1-,,-1+1,+><+,,,+,,+,,+,,+
I-'-I-"-II-"-ir-l-"+ ____________________ +''-1-,,-0+,o"-+><+,,,+,,+,,+,,+
1-Y..lI..j-.lI..j-J..J-lI+ ____________________ +'4l04.l!-f-!!+"-l-"-lfJ4..l4Display
,
f,..!.f,.l4',"-+"-+'''--1 memory
: Row data:
Display data
Y62
H-+-I--i-+====== ========= =====+-HH-+-i--i-++
Y63 ~f-!-'Mf-!-l~ ----- - - - - - - - -- - - ---- -r-+'-+=-+-i-'-r-Hr+
Accessible area
Area protected with PON =1
Figure 16 Relationship between Row Data and Display
(65·Row Output from the Right Side, 1/66 Multiplexing Duty Ratio)
HITACHI
574
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
Control register ROS bit = 10
DUTY bit = 110
LCD driving voltages:
VMH1 =V2, VML 1 =V5,
VMH2 =V3, VML2 =V4,
VMH3 =V2, VML3 =V5
:
X address!
:
I
Row driver
Column driver
Block A (32 bits)
Row data
Block B (68 bits)
I
8 bitS/l word
..l$99 X100
•••X31X32•••
XO•••
0
protected blocks
4 bytes
I 1 I 2 I 3
I
11
4 bits + 10 words + 4 bits
,
I ::::::::
6bitsll word 10 11 12 13 14 15 16
X1!l.~.
Column driver
Row driver
Block C (32 bits)
Block D (33 bits)
:
I
!-Row data
--!:
: 4 bits + 3 bytes +
:
protected blocks
8 bytes + 4 bits
I::::::::
4
5 words + 2 bits
:
i
.)5131
115
' 4 bits
13 I 14
I 1~ I
!
4 bits + 3 bytes + 5 bits :
17 I 18 I 19 I 20
I 1~ I
15
2 bits + 5 words
:
I,,;
I
5 words + 3 bits
:
i
117118 119 120121122 123 124 125 126 1:17 1
:, 100 x 65-dot LCD :I
XO
rtiti:
I X1
YO
Y1
o
1
-
Row data
'I
.
Y2 10- '0 ---
Y82
1
0
0
0
--10- '0 --10- "0 --10 "0
-
I- I
I
I
I
I
I
0
1
0
0
I
I
Y63 m = = = 10 10
Y64 o 0
Lo_Lo
,~
I X133
X164
X1631
I
o 11 11 10 101
1111 11 10 10 o 101 __ ~~
1010
1010 1 10 10 1 101 ================11 10 10 11 0 0101 ___ 0 0
I .
I
Y3
Y4
X127 I X129 I X131
IX31 IX33IX35 I
________
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Display data
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1 0 0 1 0 ---------------- 1 0 0 0 0 0 0 --- lo're
1 0 0 1 0 ---------------- 1 0 0 0 0 0 0 --- 'a "0
0 0 1 0 0 ---------------- 0 0 0 0 1 o 0 ---10'1
1 0 0 0 1 ---------------- 0 0 1 0 0 o 0 --- f-;- fo
--- ..........
---------------: Row data :
011 Jo 1 10 ---------------- 01010 11 11 011
===AA
1 10 10 011 ---------------- 010 11 10 I 0 110
______________________________
________
~/,~
Area protected
with PON 1
=
I
I
J/,~
Accessible area
~/
Area protected
with PON 1
=
Figure 17 Relationship between Row Data and Display
(65-Row Output from the Left and Right Sides, 1/66 Multiplexing Duty Ratio)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
575
HD66108T
I. . (:D'
Control register ROS bit = 11
DUTY bit = 001
LCD driving voltages:
VMH 1 =V3, VML 1 =V4,
VMH 2 = V3, VML.2 = V4,
VMH 3 =V2, VML 3 = V5
xo.•
••.X31 X32•..
Column driver
Column driver
: Block A (32 bits) :
X address !
,
:
i
4 bytes
:
:
•..X131 Xl32 ...
... X99 Xl00...
•.. Xl64
Column driver
Block B (68 bits)
: Block C (32 bits) : Block 0 (33 bits) :
8 bytes + 4 bits
!
. ! -Row data· -!
' 4 b!ts + 3 bytes +, protected block'
8 bits/1 word -':o:-r-I-1"--'-1-=-2""1-::"3-11--:-4"'1r-::::::::
1 11 1
1-1
4 bits + 3 bytes+ 5bils
~ 1
: 4 bits
1~
1 13 1 14 1 15 1 1:6 1 17 1 18 1 19 1
: 5 words + 2 bits : 4 bits + 10 words + 4 bits: 2 bits + 5 words : 5 words + 3 bits :
6bits/1word\
0111213141'5161
::::::::
11511(1117118119120121\221231241251261271
132 x 33-dot LCD
-----------------------------i-i-i--t-
r
YO
I
I fll
0 1 1 0 0
Yl
1
Y2
1 1 1 1 0
o
C 1 0
,, ,, ,, ,, ,,
,,,,,
Y29
0 0 1 0 0
Y31
Y32
0 1 0 1 0
1 0 0 0 1
0 o ( 0 0
Y33
Y34
,, , ,, ,,
-------------------------------------------------------
1 1 1 0 0 0 0 0
1 1 1 0 0 0 0 0
,, ,, ,, ,, ,, ,, ,, Row data2.~~
,
: ,
,
,,,,, ,
---------------------------- 0 0 0 0 1 0 0 1 ----- -0-1---------------------------- 0 0 0 1 1 0 1 0 ----- _2..~
Display data
I
----------------------------------------------------------------------------------
Y63
Y64
,~
I
I
0 0 1
------ o~o
.. _---- -f--r-
1 0 0 1 0 0 0 0
-----------------~----------
I
I
------ .!E..~
o0 0
oora
----- :--1,, , , , ,, , , ------,---I,,
",
I
I
I
I
, I
----------------------------, , I I ,
,
__________________________________
_J/,
Accessible area
I
I
I
I
I
display area
I
0 0 1 0 0 1 0 0
0 0 0 0.0 0 0 0
I
Invalid display data
I
I
, , , I ----------------------------, L I
I
Xl62 Xl64
IX11S31
x1rl X11291 X,31 I X1133 1
I
: :::::::8f
/
±
r-
Area protected with
PON .. 1
Figure 18 Relationship between Row Data and Display
(33·Row Output from the Right Side, 1/34 Multiplexing Duty Ratio)
HITACHI
576
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
HD66108T
Control register ROS bit = 01
DUTY bit = 011
LCD driving voltages:
VMH 1 V3, VML 1 = V4,
VMH 2 - V2, VML 2 = V5,
VMH 3 - V2, VML 3 - V5
0=
XO...
48-row
driver used
...X31 X32...
... X99 Xl00...
H
+
I Column driver I
Block A (32 bits) :
!
X address
4 bytes
:
1
I
Column driver
Block B (68 bits)
8 bytes+ 4 bits
8 bitsl1 word I-O....,...I-l-rI-2~-3-+1-4--r1-========
10111213141 ' 51&1
t
I
Row driver
: Block C (32 bits) : Block 0 (33 bits) :
: 4 bits + 3 bytes + : 4 bits + 3 bytes + :
1 4 bits
15bits
1
I 11 I 1;2 I 13 I 14 I 15 I 1& I 17 I 18 I 19 I
========'
1
Row driver
•..XI64
!-- Row data prdtected biocks --!
1 5 words + 2 bits :4 bits + 10 words + 4 bits :
6 bits/1 word
...XI31 XI32...
+
2 bits + 5 words :
~
I
5 words+ 3 bits :
11511~117118119120121122123124126126IZrI
1
: 100 x 48-dot LCD :
1
1
-------------------t-i--t-i-
VO
VI
Y2
)(95 I )(971 ><,99 I
~1 I X3 I
I
0
1
1
Xll&I X118 1
XI62 XI64
I XI831
T
--- 00 00 00 00 ------ ~~.!...
--- 0 0 0 0 ----- ~r!2..
r!~.E.
1 1 1 1 1
1 1 1 1 1
1--- 1 Row data 1 1 1
1 1 1
1 Display data
1 1 1 1 1
Valid
1
1
'Valid row data 1 display area
1
1 1 1 1 1
1 1 1 1 1
1
---_
..
--- 0 0 0 1
0 0 1 0 0 ------------------- 0 0 0 0 1 0
0
--- 0 0 1 0 ----- "oro
"""f0 1 0 1 0 ------------------- 0 0 0 1 1 0
~~
--- 0 1 0 0 ----- o 0 00
1 0 0 0 1 ------------------- 0 0 1 0 il 0
------- - f - -------------------f------------------------1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1
1 1 1- Invalid
1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1
1 1 1
1 1 0 0
0 0 1 0
1 1 1 0
-------------------------------------
1 1 1 0 0 0
1 0 0 1 0 0
.1 1 1 0 0 0
I
Y45
Y48
Y47
V48
Y49
1 1 1 1 1
ye3
V64
1 1 1 1 1 1 1
1 1 1 1
1 1 1 1 1-------------------1 1 1 1 1 1 1---I 1 1 1
1 1 1 1---I 1 1 1
1
1 1 1-------------------1 I 1 __JI'
__________________________
,~
Accessible area
+
'- - :m
display area
--_ ... -
I
~
Area protected with PON = 1
Note: Pins X1 00-X116 are left disconnected here.
Figure 19 Relationship between Row Data and Display
(65·Row Output from the Right Side, 1/48 Multiplexing Duty Ratio)
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
577
HD66108T
4.3 LCD Driving Voltage Setting
There are 6 levelS of tCD driving voltages ranging
from VI to V6; VI is the highest and V6 is the lowest.
As shown in figure 20, column output wavefonn is
made up of a combination of VI, V3, V4, and V6
while row outputwavefonn is made up of VI, V2, V5,
and V6. This means that VI and V6 are common to
both wavefonns while mid-voltages are different.
To accommodate this situation, each block of the
HD66108T is provided with,power supply pins for
mid-voltages as shown in figure 21~ Each pair of VIR
and VIL and V6R and V6L are internally connected
and must be applied the same level of voltage. Block
B is fixed for column output and must be applied V3
and V4 as mid-voltages. The other blocks must be
applied different levels of voltages according to the
function of their LCD driving output pins; if the LCD
driving output pins are set for row O\1tput, VMHn and
VMLn must be applied V2 and V5, respectively,
while they must be applied V3 and V4, respectively,
if the pins are set for column output (n =1 to 3).
Table 3 Relationship between FCR settings and LCD Driving Voltages
Control Register (FCR)
LCD Driving Voltage Pins
R0S4 ROS3 Mode
VIRNll
0
0
0
0
V3 V4
VMH1 VMl1 VMH2
165-column
V1
V3 V4
V3
V4
V3
VML2 VMH3 VML3 V6RN6l
V4
V3
V4
V6
65-row (R)
V1
V3 V4
V3
V4
V2
V5
V2
V5
V6
65-row (UR)
V1
V3 V4
V2
V5
V3
V4
V2
V5
V6
33-row(R)
V1
V3 V4
V3
V4
V3
V4
V2
V5
V6
65-row (R)
: 65-row-output mode from the right side
65-row (UR) : 65-row-output mode from the left arid right sides
33-row (R)
: 33-row-output mode from the right side
578
HITACHI
,
Hitachi America, Ltd. 0 Hitachi Plaza 0 2000 Sierra Point Pkwy." Brisbane, GA 94005-1'819 0 (415) 589-8300
HD66108T
I
,2,3,4:
:2:3:4:
------------- '--'
--'
..:=".::"::"--,
=r- + j ====T ~ '!:
:: : :
~-~~-~~~---COM1
V2
V3
=:!
:
W-~
V5
va
=CI=====~
I
I
I
,-:-T
I
I
I
I
I
,
I
-rT~~=~=I
I
I
I
I
~-~~-~+~----~
V32
COM2 V
I
I
~-----r--:-:_ii---I
I
==:
---
~~---------
:t,: ::t,! = = = = ~
.l- ..l '::::::':.:::.:
,: ,:
W
V5
~~----
W
~~----~~-~T~-----,
I
I
I
I
I
I
~ ~
V1
V2
SEG1 V3
V4
-
-
-
-,
-
,-
,
~~---,
:-: i~ nnnnnn~~ ~~~
I
I
I
I
.!.... -..!. _ _ _ _
w-~~-~~~----~
--: _
~
I
I
I
I
I
I
13 F=
••••••••••••
___ _
~~---------
+ -+ - - - - - - - - w-~~-~+~----~~-~+~--------I : : : : ............. ] --: - :- T -: - - - -1
SEG2 V4 ---I. _: _
_ _ _ _
: : : : ............ ___ _
va -
-+ --: - r-- + -r - - - - -+
I
t _
--
, ••• •••••••••
I
I
~-~~-~~~----~~-~~~---------
V3
~ ~ ~
w-~~-~~~----~~-~+~---------
w-~~-~~~----~~-~~~---------
-4 -:- ~ +- -+ -- ---+ -:-1::: ±:::i- - -- --- --VLCD
=~~=~~~====~ i=~±~=-==-- __ ~m~oo
SEG2-COM1 =
= := ::::= ::::j: = = = = : : : : -: = ~ ± ~ = = = =
=~ ~ ~== == ~ =:=t= ±::±= ===
- =
--119VLCD
(Non J
............
_ '- -'- ....J. ..:::::: •.:=.•.::.. _ = =
=-119VLCD
~
=
i ~~~
~tg
~
=
:
:
:
:
=:
=
:=
::::= ::::j: = = = = : : : : =, = ~ ± ~ = = = = = = = = =-7/9VLCD
-~~-~~~----~~-~+~---------~~
=
selected
_ ::::t
-+
I
I
±:::i====:±~=i=:±::±=====
....1-......I. _ _ _ _ .....1.._,_L,..-....L.........&. _ _ _ _ _
==1:
±::±=====I:~=t=±::±=====
=~
±~====~~=~±~=====
SEG1-COM2- _,_ '- -'-....J.
'::::::::::':.:
- - ' _ ..... -'- ...... - -=~
:_t=±::±====~
(W~ J =~~=~±~====~
from
--~-:-~±~----~
: -'-I I , - - - - :
,
,
j<
1frame
>:
~~
_~--'_'--'-....J. _ _ _ _ ~
=VLCD
~
119VLCD
±~ ···········-====~-119VLCD
±~=========
±~=========
±,
~,=========-VLCD
Figure 20 LCD Driving Voltage Waveforms
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane,CA 94005·1819· (415) 589-8300
579
HD66108T
LCD driving output pins
xo -----
X31
Block A
1L V6L
MH1
X32- - - - - X99
X100- - - - - X131
X132- - - - - X164
BlockB
Block C
Block 0
ML1
ML2
MH3
ML3
6R
1R
LCD driving power supply pins
Figure 21 Relationship between Blocks and LCD Driving Voltages
5. Multiplexing Duty Ratio and LCD Driving
Waveform Settings
A multiplexing duty ratio and LCD driving wavefonn
can be selected via internal registers.
A multiplexing duty ratio of 1/32, 1/34, 1/36, 1/48, 1/
50, 1/64, or 1/66 can be selected according to the LCD
panel used. However, since there are only 65 rowoutput pins, only 65 lines will be displayed even if 1/
66 multiplexing duty ratio is selected.
There are three types of LCD driving wavefonns, as
shown in figure 22: A-type wavefonn, B-type
wavefonn, and C-type wavefonn.
The A-type wavefonn is called per-half-line inversion.
Here, the wavefonns of M signal and CL 1 signal are
the same and alternate every LCD line.
The B-type wavefonn is called per-frame inversion;
in this case, the M signal inverts its polarity every
frame so as to alternate every two LCD frames. This
is the most common type.
The C-type wavefonn is called per-n-line inversion
and inverts its polarity every n lines (n can be set as
needed within 1 to 31 via the internal registers). The
C-type wavefonn combines the advantages of the Aand B-types of wavefonns. However, some lines will
not be alternated depending on the multiplexing duty
ratio and n. To avoid this, another C-type wavefonn
is available which is generated from the EOR of the Ctype wavefonn M signal mentioned above and the Btype wavefonn M signal. Since the relationship
between n and display quality usually depends on the
LCD panel, n must be detennined by observing actual
display results.
The B-type wavefonn should be used if the LCD
panel specifies no particular type of wavefonn.
However, in some cases, the C-type wavefonn may
create a better display.
HITACHI
580
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
I
----------r
(I)
E
~
,....
---~
___ .:'t
C')
---C\i
~
It)
I I I
I I I
E(I)
.2.5_
(I) I ' r::
E
....
.2(1)-
r::
(0 (0.::..
.... (/)
U
r::
--
--
«
I I I
xc
E
....
o
~E§
:>- ....
(I)~(I)
0.(1»
>,0.. .5
I I I
:::lE
>:t:: 0
:i=.c: f!?
(0 (0.-
L
I I I
~
(I)~(I)
:::J_
-10
0..(1»
>.0...5
cr. II
Or::
w_
I
m
r::
0
-(1)-
~r::r::
=0
:i= c'!?!
(0
(I)~(I)
-0.(1»
>.0..
:::lE
.5
I
0
0
r::
0
U
r::
:::J_
-10
cr. II
w_
Or::
Figure 22 LCD Driving Waveforms
(Row Output with a 1/32 Multiplexing Duty Ratio)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415)589-8300
581
HD66108T
6. Clock and Frame Frequency
7. Display Offfune,tion
An input clock with a 200-kHz to 4-MHz frequency
can be used for the HD66108T. Note that raising clock
frequency increases current consumption although it
reduces busy time and enables high-speed operations.
An optimum system clock frequency should thus be
selected within 200 kHz to 4 MHz.
The HD661 08Thas a display offfunction which tums
off display by rewriting the contents of the intemal
register. This prevents random display at power-on
until display memory is initialized.
The clock frequency driving the LCD panel (= frame
frequency) is usually 70 Hz to 90 Hz. Accordingly,
the HD66108T is so designed that the frequencydivision ratio of the input clock can be selected. The
HD66108T generates around 80-Hz LCD frame
frequency if the frequency-division ratio is 1. The
frequency-division ratio can be obtained from the
following equation.
The HD66108T has a standby function provinding
low-power dissipation. Writing a 1 to bit 6 of the
address register starts up the standby function.
Ni=
~ x
8. Standby Function
The LCD driving voltages, ranking from VI to V6,
must be set to Vcc to prevent DC voltage from beging
applied to an LCD panel during standby state.
The HD661 08T operates as follows in standby mode.
x D1
500
fCLK
80
: Frequency-division ratio
: Frame frequency required for the LCD
panel (Hz)
fCLK : Input clock frequency (kHz)
Dl : Duty correction value 1
D1 =1 when multiplexing duty ratio is 1/32,
1/48 or 1/64
Dl = 32/34 when multiplexing duty ratio is
1/34
Dl =32/36 when multiplexing duty ratio is
1/36
D1 =48/50 when multiplexing duty ratio is
1/50
Dl = 64/66 when multiplexing duty ratio is
1/66
Ni
fF
The frequency-division ratio nearest the value obtained
from the above equation must be selected; selectable
frequency-division ratios by intemal registers are 2.
1, 1/2, 1/3, 1/4, 1/6, and 1/8.
(1)
(2)
Stops oscillation and external clock input
Resets all registers to O's except the STBY bit
Here, note that the display memory will not preserve
data if the standby function is tumed on; the display
mempry as well as registers must be set again after the
standby function is terminated.
Table 4 shows the standby status of pins and table 5
shows the status of registers after standby function
termination.
Writing a 0 to bit 6 ofthe address register terminates
the standby. function. Writing values into the DISP
and Register No. bits at this time is ignored; these bits
need to be set after the standby function has been
completely terminated.
Figure 23 shows the flow for start-up and termination
of the standby function and related operations.
Table 4 Standby Status of Pins
Pin
Status
High
·OSC2
CO
Low
CL1
Low (master chip) or high-impedance (slave chip)
FLM
Low (master Chip) or high-impedance (slave chip)
M
Low (master chip) or high-impedance (slave chip)
Xn (column output pins)
V4
Xn' (row output pins}
V5
HITACHI
582
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005~1819· (415) 589-8300
HD66108T
Table 5 Register Status after Standby Function Termination
Register Name
Status after Standby Function Termination
Address register
Reset to a's except for the STBY bit
X address register
Reset to a's
Y address register
Reset to a's
Control register
Reset to a's
Mode register
Reset to a's
C select register
Reset to a's
Display memory
Data not preserved
Start-up
Set the LCD driving voltages to Vcc level
j
.(.
Set the STBY bit to 1
(turn on the standby function)
.(.
I
*1
Wait until external clock pulses stabilize
.(.
Termination
Set the STBY bit to a
(turn off the standby function)
.(.
(
Supply the LCD driving voltages
)
.(.
(
Set registers again
)
.(.
(
Wait for a time period of tCL 1 or longer
(
Set the display memory again
+
)
*2
)
.(.
(
Set the DISP bit to 1 (turn on LCD)
)
Notes: 1. Not necessary in the case of using internal oscillation
2. Refer to equation 1 (section 3.1).
Figure 23 Start-Up and Termination of Standby Function and Related Operations
HITACHI
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HD66108T
9. Multi.Chip Operation
(5)
The following bits for slave chips must always
be set:
INC, WLS, PON, and ROS (control register)
FFS (mode register)
It is not necessary to set the control register's
DUTY bits, the mode register's DWS bits, or
the C select register. Forotherregisters' settings,
refer to table 6.
All chips must be set to LCD off in order to tum
off the display.
The standby function of slave chips must be
started up first while that of the master chip
must be terminated first.
Using multiple HD66108T chips (= multi-chip
operation) provides the means for extending the
number of disply dots. Note the following items when
using the multi-chip operation.
(I)
(2)
(3)
(4)
The master chip and the slave chips must be
determined; the MIS pin of the master chip must
be set low and the MIS pin of the slave chips
must be set high.
All the HD66108T chips will be slave chips if
HD61203 or its equivalent is used as a row
driver.
The master chip supplies the FLM, CL I, and M
signals to the slave chips via the corresponding
pins, which synchronizes the slave chips with
the master chip.
Since a master chip outputs synchronization
signals, all data registers must be set.
(6)
(7)
Figure 24 to 26 show the connections of the
synchronization signals for different system
configurations and table 6 lists the differences between
master mode and slave mode.
Row
output
LCD
t--
Column
output
Column
output
HD66108T
Slave mode
HD66108T
Master mode
M
M
t:>scl FLM Cll
t
-
OSCl FLM Cll
f
I
I
Clock
Note:
Clock pulses for the slave chip can be supplied from the master chip CO pin.
Figure 24 Configuration Using 2 HD66108T Chips (1)
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HD66108T
Row
output
LCD
~
Column
output
Column
output
I-
HD66108T
Master mode
HD66108T
Slave mode
M
M
OSC1 FLM
iosC1 FLM CL1
t
I
I
>--
CL1
1
Clock
Note: Clock pulses for the slave chip can be supplied from the master chip CO pin.
Figure 2S Configuration Using 2 HD66108T Chips (2)
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HD66108T
LCD
Row output
Column output
HD61203
Row driver
HD66108T
Slave mode
M
CR
M
OSC1 FLM
FRM CL2
t
I
I
CL1
1
Clock
No~e:
1. The slave chip can oscillate CR clock pulses. In this case, the clock pulses must be
supplied to the HD61203 from the HD66108T's CO pin.
2. The HD61203's control pins must be set in accordance with the type of RAMs.
Figure 26 Configuration Using 1 HD66108T Chip with Another Row Driver (HD61203)
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HD66108T
Table 6 Comparison between Master and Slave Mode
Item
Pin:
Master Mode
Slave Mode
Must be set high
MIS
Must be set low
OSC1,OSC2
Oscillation is possible
Oscillation is possible
CO
=OSC1
=OCS1
FLM, CL1, M
Register:
Output signals
Input signals
AR
Valid
Valid
XAR
Valid
Valid
YAR
Valid
Valid
FCR
Valid
Valid except for the DUTY bits
MDR
Valid
Valid except for the DWS bits
CSR
Valid (only if the DWS bits are
set for the C-tye waveform)
Invalid
Notes
Valid
Needs to be set
- Invaid: Need not be set
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HD66108T
Internal Registers
All H066108T's registers can be read from and
written into. However, the BUSY FLAG 'and invalid
bits cannot be written to and reading invalid bits or
registers returns O's.
1. Address Register (AR) (Accessed with RS = 0)
BUSY FLAG bit, STBY bit, and DISP bit. Register
No. bits select one of the data registers according to
the register number written. The BUSY FLAG bit
indicates the internal operation state if read. The
STBY bit activates the standby function. The DISP
bit turns the display on or off. This register is selected
when RS pin is O.
This register (figure 27) contains Register No. bits,
Bits 04 and 03 are invalid.
D7
D6
D5
BUSY
FLAG
STBY
DISP
(1)
D4
D3
D2
D1
DO
Register No.
STBY
- 1: Standby function on
- 0: Normal (standby function off)
• When standby function is on, all registers are reset to O's
(2) DlSP
-1: LCD on
- 0: LCD off
(3) Register No.
Bit
2 1 0
Register
0
1
2
3
4
0
0
0
0
1
1
Display memory
X address register
Y address register
Control register
Mode register
C select register
5
(4)
-
No.
0
0
1
1
0
0
0
1
0
1
0
1
BUSY FLAG (Can be read only)
- 1: Busy state
- 0: Ready state
Figure 27 Address Register
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HD66108T
2. Display Memory (DRAM) (Accessed with RS
=1, register number =(000)2)
This register (figure 29) contains 3 invalid bits (07 to
05) and 5 valid bits (04 to 00). It sets X addresses and
confirms X addresses after writing or reading to or
from the display memory.
Although display memory (figure 28) is not a register,
it can be handled as one. 8- or 6-bit data can be
selected by the control register WLS bit according to
the character font in use. If 6-bit data is selected, 07
and 06 bits are invalid.
4. Y Address Register (Y AR) (Accessed with RS =
1, register number =(010)2)
This register (figure 30) contains I invalid bit (07) and
7 valid bits (06 to 00). It sets Y addresses and
confirms Y addresses after writing or reading to or
from the display memory.
3. X Address Register (XAR) (Accessed with RS
= 1, register number = (001)2)
07
06
05
04
03
01
02
DO
a-Bit Data
*
6-Bit Data
*
Reading bits marked with· return Os and writing them is invalid.
Figure 28 Display Memory
07
06
05
04
03
02
01
DO
XAO
XAO: 0 to 20 ($OO to $14) when display data is 8 bits long and 0 to 27 ($OO to $1 B) when display data
is 6 bits long. A maximum of $1 F is programmable.
Figure 29 X Address Register
07
[
06
05
04
[
03
02
01
DO
YAO
YAO: 0 to 128 ($OO to $7F)
Figure 30 Y Address Register
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HD66108T
5. Control Register (FCR) (Accessed with RS
1, register number =(011)2)
=
This register (figure 31). containing eight bits. has a
variety offunctions such as specifying the method for
accessing RAM. detennining RAM valid area. and
selecting the function of the LCD driving signal
output pins. It must be initialized as soon as possible
07
06
05
04
03
02
01
(1)
INC (Address increment direction select)
- 1: X address is.incremented
- 0: Y address is incremented
(2)
WLS (Word length (of display data) select)
- 1: 6-bit word
- 0: 8-bit word
(3)
PON (Row data protect on)
- 1: Protect function on
- 0: Pretect function off
afterpower-on since itdetennines the overall operation
of the HD66108T. The PON bit may have to be re-set
afterwards. If the DUTY bits are rewritten after
initialization at power-on (if values other than the
initial values are desired). the display memory will
not preserve data; the display memory must be set
again after a time period of tCLI or longer. For
deterniining tCLI' refer to equation I (section 3.1).
DO
(4) ROS (Row output (function of LCD driving output pins) select)
Bit
(5)
No.
43
Contents
o
1
2
00
01
10
165 column outputs
65 row outputs from the right side
3
11
65 row outputs from the left and right sides
33 row outputs from the right side
DUTY (Multiplexing duty ratio)
Bit
No.
0
1
2
3
4
5
6
7
2
0
0
0
0
1 0
Multiplexing
Duty Ratio
0 0 1/32
0 1 1/34
1 0 1/36
1 1 1/48
1 0 0 1/50
1 0 1 1/64
1 1 0 1/66
1 1 1 Testing mode
Figure 31 Control Register
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HD66108T
6. Mode Register (MDR) (Accessed with RS =1,
register number =(100)2)
the FFS bits are rewritten after initialization at poweron (if values other than the initial values are desired),
the display memory will not preserve data; the display
memory must be set again after a time period of to-lor
longer. For determining teLl' refer to equation 1
(section 3.1).
This register (figure 32), containing 3 invalid bits (D7
to DS) and S valid bits (D4 to DO), selects a system
clock and type of LCD driving waveform. It must
also be initialized after power-on since it determines
overall HD661 08T operation like the FCR register.· If
07
06
05
04
01
00
OWS
FFS (Frame frequency select)
Bit
-
(2)
02
FFS
I
(1 )
03
Frequency-
No.
4 3 2 Division Ratio
0
1
2
3
4
5
6
7
0
0
0
()
1
1
1
1
0
0
1
1
()
()
1
1
0
1
0
1
0
1
0
1
1
1/2
1/3
1/4
1/6
1/8
2
OWS (LCO driving waveform select)
No.
0
1
2
3
Bit
1 0
0
0
0
1
1 0
1 1
Driving Waveform
A-type waveform
B-type waveform
C-type waveform
Figure 32 Mode Register
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HD66108T
7. C Select Register (CSR) (Accessed with RS=
1, register numbe.- (101)2)·
=
This register (figure 33) contains 2 invalid bits (07
07
06
05
04
03
02
01
andD6) and 5 valid bits (05 to DO). It controls C-type
waveforms and is activated only whenMDR register's
OWS bits are set for this type of wavefonn.
DO
(1)
EOR (B-type waveform M signal ® no. of counting lines onIoff)
- 1: EOR function on
- 0: EOR function off
(2)
CLN (No. of counting lines in C-type waveform)
1 to 31 should be set in these bits; 0 must not be set.
Figure 33 C Select Register
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HD66108T
Reset Function
The RESET pin starts the HD66108T after poweron. A RESET signal must be input via this pin for
at least 20 fls to prevent system failure due to
excessive current created after power-on. Figure 34
shows the reset definition.
or register bits except for the address register's
STBY bit and the X and Y address registers,
which are reset to O's by the signal. Table 8
shows the reset status of registers.
(3)
(1)
Reset Status of Pins
(2)
Status after Reset
Table 7 shows the reset status of output pins.
The pins return to normal operation after reset.
The display memory does not preserve data
which has been written to it before reset; it
must be set again after reset.
Reset Status of Registers
A RESET signal terminates the standby mode.
The RESET signal has no effect on registers
Table 7 Reset Status of Pins
Pin
Status
OSC2
Outputs clock pulses or oscillates
CO
Outputs clock pulses
CL1
Low (master chip) or high-impedance (slave chip)
FLM
Low (master chip) or high-impedance (slave chip)
M
Low (master chip) or high-impedance (slave chip)
Xn(column output pins)
V4
Xn' (Row output pins)
V5
Table 8 Reset Status of Registers
Register
Status
Address register
Pre-reset status with the STBY bit reset to 0
X address register
Reset to O's
Y address register
Reset to O's
Control register
Pre-reset status
Mode register
Pre-reset status
C select register
Pre-reset status
Display memory
Preserves no pre-reset data
RESET
/~
At reset
0.15 x Vee
During reset
(Reset status)
/
0.15 x Vee
After reset
Figure 34 Reset Definition
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HD66108T
Precautionary Notes When Using the HD66108T
(I)
(2)
(3)
(4)
(5)
Install a O.l-~F bypass capacitor as close to
the LSI as possible to reduce power supply
impedance (V cc-GND and Vcc-VEE)'
Do not leave input pins open since the
HD66I08T is a CMOS LSI; refer to "Pin
Functions" on how to deal with each pin.
When using the internal oscillation clock,
attach an oscillation resistor as close to the
LSI as possible to reduce coupling capacitance.
Make sure to input the reset signal at poweron so that internal units operate as specified.
Maintain the LCD driving power at Vccduring
standby state so that DC is not applied to an
LCD, in which Xn pins are fixed at V4 or V5
level.
(2)
(3)
Programming Restrictions
(I)
address is not incremented until 0.5-clock
time has passed. If an X or Y address is read
during this time period, non-updated data will
be read. (The addresses are incremented even
in this case.) In addition, the address increment
direction should not be changed during this
time since it will cause malfunctions.
Although the maximum output rows is 33
when 33-row-output mode from the right side
is specified, any multiplexing duty ratio can
be specified. Therefore, row output data
sufficient to fill the specified duty must be
input in the Y direction. Figure 35 shows how
to set row data in the case of 1/34 multiplexing
duty ratio. In this case, Os must be set in Y33
since data for the 34th row (Y33) are not
output.
Do not set the C select register's CLN bits
to 0 for the M signal of C-type waveform.
After busy time is terminated, an X or Y
X132
X131 X133
X164
X163
r1-
YO
0 0 __________
Y1
Y2
Y3
0 0 __________ ~ ~
~
0 0 __________ ~ ~
0 0 __________ ~..Q.
1 1
1 I
1 1
+-1--11 -+1 __________ \-::-1-,:-
Y30
Y31
Y32
Y33
Display data area
o
o
0
0 0
----------COO
----------COO
1
1 0
o 0 ----------
roo_
- - - - - - - - - - 1---
All O's
Row data area
Figure 35 How to Set Row Data for 33·Row Output from the Right Side
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HD66108T
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Power Supply Voltage (1)
Vee 1 to V ee 3
-0.3 to +7.0
V
Power Supply Voltage (2)
Vee - VEE
-0.3 to +16.5
V
Input Voltage
V ln
-0.3 to
Operating Temperature
Top
-20 to + 75
Storage Temperature
TBto
-20 to +85
vee
+ 0.3
V
°e
·e
Notes: 1. Permanent LSI damage may occur if the maximum ratings are exceeded.
Normal operation should be under recommended operating conditions (Vee = 2.7
to 6.0 V, GND = 0 V, Ta = -20 to + 7S0C). If these conditions are exceeded,
LSI malfunctions could occur.
2. Power supply voltages are referenced to GND = 0 V. Power supply voltage (2)
indicates the difference between Vee and VEE.
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HD66108T
Electrical Characteristics
DC Characteristics (1) (Vee =5V±20%,GND = 0 V, VCC - VEE = 6.0 to 15 V, Ta =-20 to+75°C,
unless otherwise noted)
Item
Symbol Min
Input High
Voltage
Input Low
Voltage
Output High
VOltage
OSC1
V..1
0.8xVcc
MIS. CL1. FLM.
M. TEST1. TEST2
V~
0.7 x Vcc
Typ
Max
Unit
-
Vcc +0.3
V
Vcc +0.3
V
-
Teet Conditions
Notea
Vcc .. 5V±10%
5
V
Vcc .. 5V±10%
6
V
-1011 ,"0.1 mA
V
-1011. 0.2 mA
FiESE'F
V..s
O.85xVcc -
Vcc +0.3
V
The other inputs
V..4
2.0
Vcc +0.3
V
OSC1
V..1
-0.3
0.2 x Vcc
V
MIS. CL1. FLM.
M. TEST1. TEST2
V..2
-0.3
0.3 x Vcc
V
RESET
Va.3
-0.3
0.15xVcc V
0.8
The other inputs
V..4
-0.3
CO. CL1. FLM. M
VOH1
0.9xVcc
DB7-D80
V~
2.4
-
7
Vcc ·5V±10%
Output Low
Voltage
CO. CL1. FLM. M
V0I.1
0.1 xVcc
V
DB7-DBO
V0I.2
0.4
V
101.-0.1 mA
101.=1.6 mA
8
Vcc ·5V±10%
Input Leakage
Current
All except OB7-080.
CL1. FLM.M
TrI-8tate
OB7-0BO. CL1. FLM.
Leakage Current M
I...
-2.5
2.5
pA
VIn-OtoVcc
I.
-10
10
pA
VIn-OtoVcc
-10
10
pA
Vin-Vee to Vcc
V Pins Leakage
. Current
V1. V3, V4, V6,
VMHn,VMLn
I...
Current
Consumption
During display
Icc1
400
pA
External clock
foac .. 500 kHz
1c02
1.0
mA
Internal oscillation
Rf.91 kQ
During star\d:)y data
188
10
pA
ON Resistance
Xo-X164
between Vi and Xj
f\w
10
kg
V Pins Voltage
Range
IN
35
%
Oscillating Frequency
foac
585
kHz
315
450
1.2
±ILO-SOpA
Vcc - VI£ -10 V
3
4
Rf.91 kQ
Notes: 1. When voltage applied to input pins is fixed to Vcc or to GNO and output pins have no load capacity.
2. When the LSI is not exposed to light and Ta. 0 to 4QOC wI\h the STBY bit - 1. If using external clock pulses.
input pins must be fixed high or low. Exposing the LSI to light increases current consumptton.
3. ILO indicates \he current supplied to one measured pin.
4. AV - 0.35 x (Vcc - V1£). For levels V1. V2. and
the voltage empioyed should fall between the Vcc and the
IN and for levels V4. V5. and V6. the voltage employed should fall between the VI£ and the AV (figure 36).
5. V..3 (min). 0.7 x Vcc when used under conditions o\herthan Vcc .5v±10%.
6. V..3 (max) = 0.15 x Vcc when used underoonditions other \han VccOO 5 V±10%.
7. V~ (min) .; 0.9 x VCC HOII .. 0.1 mAl when usld under concIItIons other \han Vcc .. 5 V ±10%.
8. V01.2 (max) .. 0.1 x Vcc (101. .. 0.1 mAl when used under condI1ions other than Vcc • 5 V ±10'1'0.
va.
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HD66108T
DC Characteristics (2) (Vee
unless otherwise noted)
=2.7 to 4.0 V, GND =0 V, Vcc - VEE =6.0 to 15 V, Ta =-20 to +75°C,
Item
Symbol Min
Typ
Max
Unit
Input High
RESET
VIH 1
0.85 x Vee -
Vee + 0.3
V
Voltage
The other inputs
VIH2
0.7 x Vee
Vee + 0.3
V
Input Low
Voltage
MIS, OSC1, CL1, FLM,
TEST1, TEST2, M
VI. 1
-0.3
0.3 x Vee
V
The other inputs
V..2
-0.3
0.15 x Vee
V
Output High
Voltage
Vol 1
0.9 x Vee
Output Low
Voltage
Vol1
Input Leakage
Current
All except OB7-0BO,
CU, FLM, M
Teat Conditions
V
-IOH - 5O I1A
0.1 x Vee
V
IOL =50 I1A
Inl
-2.5
2.5
pA
V.. = Oto Vee
Tri-State
OB7-0BO,CL1,FLM,
Leakage Current M
ITSl
-10
10
pA
V.. = Oto Vee
V Pins Leakage
Current
V1, V3, V4, V6,
VMHn, VMLn
IYl
-10
10
pA
V.. - VEE to Vee
Current
Consumption
During display
lee 1
260
pA
External clock
'ose = 500 kHz'
lee 2
700
pA
Internal oscillation
R'=75kn
During standby state
ISB
10
pA
ON Resistance Xo-X164
between Vi and Xj
RON
10
kG
V Pins Voltage
Range
/lV
35
0/0
Oscillating Frequency
'osc
585
kHz
315
450
Notes
1,2
±lw=50pA
Vee -VEE -10V
3
4
Rf=75kn
Notes: 1. When voltage applied to input pins is fixed to Vee or to GNO and output pins have no load capacity. Exposing
the LSI to light increases current consumption.
2. When the LSI is not exposed to light and Ta =0 to 40°C with the STBY bit = 1. If using external clock pulses,
input pins must be fixed high or low.
3. 110 indicates the current supplied to one measured pin.
4. /lV = 0.35 x (Vee - VEE)' For levels V1, V2, and V3, the voltage employed should 'all between the Vee and
the /lV and for levels V4, V5, and V6, the voltage empioyed should 'all between the VEE and the /lV (figure
36)
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597
II
HD66108T
Vcc----------------------~
tN
V1, V2, V3 Levels
tN
V4, V5,
va Levels
Ve ----------------------~
Figure 36 Driver Output Waveform and Voltage Levels
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HD66108T
AC Characteristics (1) (Vee = 4.5 to 6.0 V, GND = 0 V, Ta = -20 to +75°C, unless otherwise noted)
1. CPU Bus Timing (figure 37)
Item
Symbol
Min
RD High-Level Pulse Width
tWRH
190
RD Low-Level Pulse Width
Max
Unit
ns
tWRL
190
ns
WR High-Level Pulse Width
tWWH
190
ns
WR Low-Level Pulse Width
tWWL
190
ns
WR-RD High-Level Pulse Width
twwRH
t AS
190
ns
CS, RS Setup Time
0
ns
CS, RS Hold Time
tAH
0
ns
Write Data Setup Time
tosw
100
ns
Write Data Hold Time
tOHW
0
ns
Read Data Output Delay Time
tOOR
Read Data Hold Time
tOHR
20
External Clock Cycle Time
External Clock High-Level Pulse Width
tCYC
t WCH
0.1
J.lS
External Clock Low-Level Pulse Width
t WCL
0.1
J.lS
External Clock Rise and Fall time
tr, If
150
0.25
5.0
20
ns
Note
ns
Note
J.lS
ns
Note: Measured by test circuit 1 (figure 39).
2.
LCD Interface Timing (figure 38)
Item
MIS =0
MIS = 1
Notes: 1.
2.
3.
4.
5.
Max
Notes
Symbol
Min
1,4,5
Low-Level Pulse Width
IwcH1
tWCL 1
35
35
1,4,5
FLM
Delay Time
tOFL 1
-2.0
+2.0
4,5
FLM
Hold Time
tHFL 1
-2.0
+2.0
4,5
M Output Delay Time
tOM01
-2.0
+2.0
4,5
CL1
High-Level Pulse Width
IwOH2
35
4,5
CL1
Low-Level Pulse Width
IwOL2
11 x love
2,4,5
FLM
Delay Time
tOFL2
-2.0
1.5 x love
3,4,5
FLM
Hold Time
tHFL2
-2.0
+2.0
4,5
CL1
High-Level Pulse Width
CL1
-2.0
4,5
M Delay Time
+2.0
tOM I
When Rose is 91 kn (Vcc = 4.0 to 6 V) or 75 kn (Vco = 2.0 to 4.0 V) and bits FFS are set for 1.
When bits FFS are set for 1 or 2. The value is 19 x tcve in other cases.
When bitgs FFS are set for 1 or 2. The value is 8.5 x love in other cases.
Measured by test circuit 2 (figure 39).
Units are IlS.
HITACHI
Hitachi America, Ltd .• 'Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819" (415) 589-8300
599
----
-
---
HD66108T
AC Characteristics (2) (Vee =2.7 to 4.5 V, GND =0 V, Ta
=-20 to +75°C, unless otherwise noted)
1. CPU Bus Timing (figure 37)
Item
Symbol
Min
RD High-Level Pulse Width
tWRH
1.0
J,lS
RD Low-Level Pulse Width
tWRL
1.0
J,ls
WR High-Level Pulse Width
J,lS
Max
Unit
tWWH
1.0
WR Low-Level Pulse Width
twwL
1.0
J.lS
WR-RD High-Level Pulse Width
twwRH
1.0
J.lS
CS, RS Setup Time
J.lS
tAS
0.5
CS, RS Hold Time
tAH
0.1
J.lS
Write Data Setup Time
tosw
1.0
J,ls
Write Data Hold Time
tOHW
0
Read Data Output Delay Time
tOOR
Read Data Hold TIme
tOHR
J,lS
0.5
20
External Clock Cycle Time
tCYC
1.6
External Clock High-Level Pulse Width
tWCH
0.7
External Clock Low-Level Pulse Width
t WCl
0.7
External Clock Rise and Fall time
tr, tf
5.0
Note
J.lS
ns
Note
J.lS
J.lS
J.lS
0.1
J.lS
Note: Measured by test circuit 2 (figure 39).
2.
LCD Interface Timing (figure 38)
Item
MIS =0
MIS = 1
Min
Max
Notes
CL1
High-Level Pulse Width
iwCH 1
35
1,4,5
CL1
Low-Level Pulse Width
tWCL 1
35
1,4,5
FLM
Delay TIme
tOFL 1
-2.0
+2.0
4,5
FLM
Hold Time
tHFL 1
-2.0
+2.0
4,5
M Output Delay Time
tOM01
-2.0
+2.0
4,5
CL1
High-Level Pulse Width
35
4,5
CL1
Low-Level Pulse Width
iwcH2
tweL2
11xteve
2,4,5
tOFL2
-2.0
1.5 x tevc
3,4,5
tHFL2
-2.0
+2.0
4,5
tOMI
-2.0
+2.0
4,5
FLM
Delay Time
FLM
Hold Time
M Delay Time
Notes: 1.
2.
3.
4.
5.
Symbol
When Rose is 91 kn (Vcc = 4.0 to 6 V) or 75 kn (Vee = 2.7 to 4.0 V) and bits FFS are set for 1.
When bits FFS are set for 1 or 2. The value is 19 x lcvc in other cases.
When bits FFS are set for 1 or 2. The value is 8.5 x lcve in other cases.
Measured by test circuit 2 (figure 39).
Units are J.lS.
HITACHI
600
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
VI~j
V
CS
RS
1L
r-
twwt.
tAS
~
V1HV1L r
-'
'-
....,
r-
tAH
~
....;
tAS
~
i-=-
-
ftwwH
twwRH
V1H --'
V1L r
...,1-
/
080-7
L
~RL
~RH
tosw
t
tAH
toHW
~
V1H
....,
-
V1L
-
...., "-
to DR
I-Votr; '-
VOL ,
r
~
II
toHR
~
-r
~'-
Figure 37 CPU Bus Timing
CL1
FLM
I
_ _ _ _ _ _-J
-------------~~
M
Figure 38 LCD Interface Timing
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
601
HD66108T
5.0V
C
All diodes are 152074 ®
RL =2.4kn
R = 11kn
C= 130pF
Test Circuit 1
Test Circuit 2
Figure 39 Load Circuits
HITACHI
602
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66108T
TCP Sketches and Mounting
The following shows TCP sketches and TCP mounting on a printed circuit board. These drawings do not restrict
TCP shape.
Potting resin
Solder resist
r--------+---~-""7
Pattern-formed
surface
t
(-4i~.~-f---rA'
Tape base
TCP Rough Sketch
Wiring-pattem-plated
P tt'
.
Pattern-formed surface
w_~~"
)-'
I
,,""
t -- Tapebase
(Chip back-grinded surface)
~"~"~'
Tape base
A-A' Cross-Sectional View
I
Chip back-grinded surface
Solder
I
!
o:so
Tape base
Tape base
(
i
PC board
Pattern-formed surface
TCP Mounting on PC Board
HITACHI
HitachiAmerica, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
603
HD66840F---- For Maintenance Only
For new designs please see
data sheet for H 06684 tF
LCD Video Interface
Controller (LVIC)
Description
•
The HD66840F LVIC interface controller
converts the standard video signals R, G, B for
CRT display into LCD data. It enables a CRT
display system to be replaced by an LCD
system without any changes. It also enables
the software originally intended for CRT display to control the LCD.
Pin Arrangement
Since the LVIC can control TFT-type LCDs in
addition to the current TN-type LCD, it can
support color display as well as monochrome
display. It can program screen size and can
control a large-panel LCD of 720 dots x 512
dots (max).
100-pin plastic OFP (FP-l00A)
lm;AOIXDOT
Al/YLO
A2/YLl
A3/YL2
DO/FO
•
•
•
•
•
•
•
•
•
•
•
Converts video R, G, B signals for CRT
display into LCD data:
-Monochrome display data
-8-level gray scale display data
-8-color display data
Can select LVIC control method:
-Pin programming method
-Internal register programming method
(either with MPU or ROM)
Can program screen size:
-200, 350, 400, 480, 512, or 540 dots
(lines) in height and 640, or 720 dots (80,
or 90 characters) in width by pin programming method
--4-1024 dots (lines) in height and 324048 dots (4-506 characters) in width by
internal register programming method
Can regene~ate the display timing signal
from HSYNC and VSYNC
Internal PLL circuit can generate the dot
clock (external charge pump, low pass
filter (LPF), and voltage-controlled oscillator (VCO) required)
Can control both TN-type LCD and TFTtype LCD
Maximum operating frequency: 25 MHz
(dot clock for CRT display)
LCD driver interface: 4-, 8-, or 12-bit (4 bits
each for R, G, B) parallel data transfer
Recommended LCD drivers: HD61104
(column) and HD61105 (common),
HD66204 (column) and HD66205 (common), HD66106 and HD66107T (column/
common)
CMOS 1.3 ,urn process
Single power supply: +5 V ± 10 %
19
3
78
17
76
DOTE
PMODl
PMODO
LDOTCK
V cc 3
01/Fl
DZ/F2
74
D3!F3
73
CL4
CL3
eL2
GND2
72
ell
MAO
Features
1 §g:m:;;:gg:;:;:~a;~g:::;;:ll~;:\:;::;:;;;8D
15
71
FLM
MAl
MA2
"
70
M
69
RD/LUO
MA3
13
68
Rl/LUl
'4
67
R2!LU2
MA4
MA5
MA6
MA7
MAS
MA9
MAlO
MAll
MA12
GND3
MA13
MA14
10
15
66
R3/lU3
,e
"
65
64
GND6
GO/LOO
63
GliLDl
,8
6<
G2!LD2
20
61
G3!LD3
21
60
n
59
80
B1
n
58
82
24
57
B3
19
25
56
MA15
26
Meso
55
B07
Bo6
17
54
53
BD5
BD4
52
BD3
51
BD2
MCSl
'M'WE
Vcc2
2B
29
30 ;;;
~ ~
;;
~ ~
:;;
~ ~
'f ;;
~
':j
~
'!i '!i ;;
~ ~
:;:
II
O-(~M.m.~~O-NM.~~~O_~
00000000000000000000
~~~~~~z~~~~~~~~~~mmz
~
~
Ordering Information
Dot clock
Type No.
(MHz)
HD66840F
25 MHz
Package
100-pin
Plastic QFP (FP-100Al
HITACHI
604
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Pin Description
Table 1 describes the pins.
Table 1
Pin Description
Symbol
Pin Number
Pin Name
Vcc1-Vec3
96, 30, 76
Vee 1 , Vee 2, Vee 3
GND1-GND6
88,9,23,
37,50,65
Ground 1-6
R, G, 8 1
91,92,93
Red, green, blue serial data
HSYNC
89
Horizontal synchronization
VSYNC
90
Vertical synchronization
DISPTMG2
95
Display timing
DOTCLK
94
Dot clock
I
RO-R3 3
LUO-LU3 4
69-66
69-66
LCD red data 0-3
LCD up panel data 0-3
0
0
GO-G3 3 ,5
LDO-LD34 ,5
64-61
64-61
LCD green data 0-3
LCD down panel data 0-3 .
0
0
80-83 3 ,6
60-57
LCD blue data 0-3
0
CL1
72
LCD data line clock
I/O
CL2
73
LCD data shift clock
CL3 7
74
Y-driver shift clock 1
0
0
0
CL4 7
75
V-driver shift clock 2
0
FLM
71
First line marker
M
70
LCD driving signal alternation
0
0
LDOTCK
77
LCD dot clock
I
27,28
Memory chip select 0, 1
0
MWE9
29
Memory write enable
0
MAO-MA159
10-22,
24-26
Memory address 0-1 5
0
RDO-RD79
31-36,
38-39
Memory red data 0-7
I/O
GDO-GD79, 10
40-47
Memory green data 0-7
I/O
800-807 9 ,10
48,49
51-56
Memory blue data 0-7
I/O
MCSO,
MCS1 8
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
605
HD66840F
Table 1
Pin Description (cont)
Symbol
PMODO, PMOD1
DOTE
SPS
DMO-DM3
Pin Number
Pin Name
78, 79
Program mode 0, 1
80
Dot clock edge change
81
Synchronization polarity select
82-85
Display mode 0-3
CS (MPU programming)11
MSO (pin programming)"
98
98
Chip select
Memory select 0
WR (MPU programming)",'2
MS1 (pin programming)"
99
99
Write
Memory select 1
Read
Address 0
X-dot
RD (MPU programming)'2
AO (ROM programming)
XDOT (pin programming)
I/O
I
o
I
RS (MPU programming)"
ADJ (pin programming)"
100
100
Register select
Adjust
00-03 (MPU programming)
00-03 (ROM programming)
FO-F3 (pin programming)
5-8
5-8
5-8
Data 0-3
Data 0-3
Fine adjust 0-3
A1-A3 (ROM programming)'3
VLO-VL2 (pin programming)'3
2-4
2-4
Address 1-3
V-line 0-2
RES'4
97
Reset
CD
86
Charge down
0
CU
87
Charge up
0
I/O
I
I
o
I
Notes: 1. When CRT display data is monochrome, G and B pins should be fixed low.
2. Fix high or low when regenerating the display timing signal internally.
3. For 8-color display modes.
4. For monochrome and 8-level gray scale display modes.
5. Leave disconnected in 4-bit/single screen data transfer modes.
6. Leave disconnected in monochrome and 8-level gray scale display modes.
7. Leave disconnected when controlling TN-type LCD.
8. Leave disconnected when using no buffer memories.
9. Leave disconnected when using no buffer memories.
10. In monochrome display modes, the LVIC writes the OR of R, G, B signals into R-plane
RAMs. Thus, no RAMs are required for G and B planes in these modes.
Pull up these pins with 20-kO resistance. If G and B plane RAMs are connected in
monochrome display modes, the LVIC writes G and B signals into each RAM. However, it
does not affect the display or the contents of R-plane RAM whether G- and B-plane RAMs
are connected or not.
11. Fix high or low when controlling the LVIC by ROM programming method.
12. WR and RD must not be low at the same time.
13. Fix high or low when controlling the LVIC by MPU programming method.
14. Make sure to input RES signal after power-on.
HITACHI
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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Power Supply
Buffer Memory Interface
Vccl-Vcc3: Connect Vccl-Vcc3 with +5 V.
MCSO, MCS1: MCSO and MCSl output the
buffer memory chip select signal.
GNDI-GND6: Ground GNDl-GND6.
CRT Display Interface
MWE: MWE outputs the write enable signal
of buffer memories.
R, G, B: Input CRT display R, G, B signals on
MAO-MAI5: MAO-MA15 output buffer
R, G and B respectively.
memory addresses.
HSYNC: Input the CRT horizontal synchronization on HSYNC.
RDO-RD7: RDO-RD7 transfer data between R
data buffer memory and the LVIC.
VSYNC: Input the CRT vertical synchronization on VSYNC.
GDO-GD7: GDO-GD7 transfer data between
DISPTMG: Input the display timing signal,
which announces the horizontal or vertical
display period, on DISPTMG.
BDO-BD7: BDO-BD7 transfer data between B
data buffer memory and the LVIC.
G data buffer memory and the LVIC.
Mode Setting
DOTCLK: Input the dot clock for CRT display
on DOTCLK.
PMODO, PMODI: The PMODO-PMODl input
signals select a programming method (table
LCD Interface
6).
RO-R3:' RO-R3 output R data for the LCD.
DOTE: The DOTE input signal switches the
LUO-LU3: LUO-LU3 output LCD up panel
data.
timing of the data latch. The LVIC latches R,
G, B signal at the falling edge of DOTCLK
when DOTE is high, and at the rising edge
when low.
GO-G3: GO-G3 output G data for the LCD.
SPS: The SPS input signal selects the polarity
LDO-LD3: LDO-LD3 output LCD down panel
data.
of VSYNC. (The polarity of HSYNC is fixed.)
VSYNC is high active when SPS is high, and
low active when low.
BO-B3: BO-B3 output B data for the LCD.
CLI: CLl outputs the line select clock for LCD
DMO-DM3: The DMO-DM3 input signals
select a display mode (table 8).
data.
CL2: CL2 outputs the shift clock for LCD
data.
MSO-MSI: The MSO-MSl input signals select
the kind of buffer memories (table 2).
XDOT: The XDOT input signal specifies the
CL3: CL3 outputs the line select and shift
clock when a Y-driver is set on one side of an
LCD screen (see "LCD System Configuration").
CL4: CL40utputs the line select and shift
clock when Y-drivers are set on both sides of
an LCD screen (see "LCD System Configuration").
FLM: FLM outputs the first line marker for a
Y-driver.
M: The M output signal converts the LCD
drive signal to AC.
LDOTCK: LDOTCK outputs the LCD dot
clock.
number of horizontal displayed characters.
The number is 90 when XDOT is high, and 80
when low.
YLO-YL2: The YLO-YL2 input signals specify
the number of vertical displayed lines (table
3).
ADJ: The ADJ input signal determines
whether FO-F3 pins adjust the number of
vertical displayed lines or the display timing
signal. FO-F3 pins adjust the display timing
signal when ADJ is high, and adjust the
number of vertical displayed lines when low.
FO-F3: FO-F3 input data for adjusting th~
number of vertical displayed lines (table 4), or
the display timing signal (see MFiI1e
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
607
I
HD66840F
DO·D3: 00-03 transfer internal register data
between the MPU and LVrC.
Adjustment of Display Timing Signal").
MPU Interface
RES: RES inputs the external reset signal.
CS: The MPU selects the LVrC when CS is
low.
WR: The MPU inputs the WR write signal to
write data into internal registers of the LVIC.
The MPU can write data when WR is low and
cannot write data when high.
RD: The MPU inputs the RD read signal to
read data from internal registers of the LVIC.
The MPU can read data when RO is low and
cannot read data when high.
RS: The MPU inputs the RS signal together
with CS to select internal registers. The MPU
selects data registers (RO-R15) when RS is
high and CS is low, and selects the address
register (AR) when RS is low and CS is low.
Table 2 Memory Type and MS1, MBO
Pins
MS1
MSO
Memory Type
0
0
0
1
0
No memory
8-kbytes memory
32-kbytes memory
64-kbytes memory
ROM Interface
AO-A3: AO-A3 output address 0 to address 3
to an external ROM.
DO·D3: 00-03 input data from an external
ROM to internal registers.
PLL Circuit Interface
CD: CD outputs the charge down signal to an
external charge pump.
CU: CU outputs the charge up signal to an
external charge pump.
Table 4 Fine Adjustment of Vertical
Displayed Lines
F3
F2
F1
FO
Number
Adjusted
0
0
0
0
0
0
0
0
0
1
0
±O
+ 1
+2
0
+ 14
+ 15
Table 3 Number of Vertical Displayed
Lines and YLO· YL2 Pins
YL2
YL1
YLO
Number of Vertical
played Lines
0
0
0
0
0
0
0
1
0
1
0
1
0
350
400
480
512
540
Prohibited
1
0
0
of
Dis·
200
HITACHI
608
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Lines
-
I
:x:
s=
n
2:
~
CD
:::!.
~
~
2:
·
~
o
o
t
t
I
I
HSYNC
VSYNC
OISPTMG
-+-+-......
J
~~
en
C"
;
-'"
~
~
o
~
~
<0
•
~
~
8l
<0
Write address
counter
l
Timing clock
r
OOTCLK
DOTE
1
CRT display/ 1 ' - - ,
R +--Ibuffermemorylc::::;G - f - - -..mterface
B
Vee
GNO
l
I~
Ie;-
~~
Read counter
(Horizontal.
vertical counter)
J-r
rl
IF
IU
~~
f- 8
.-~
~
IJ
I
-
~
~
===
,1--76 ~
~
;g
Read address
counter
2
~
• - - - - - - -- ,
:
~ li?:
is
T
I
8. g. ¥-
1
..
-<
I
h
,..........._ - . . . ,
I
I
'"
CD
~
r------------ ---,
I
I
I
I
~,........;,-
'f
~_.CI)O
:l
nga g.
r--:--v0 _
I
~P" §. ~."...
'1
I
0 _
_.m O
ag~
~ £t~ ~
i
~~
{r{l
I
I
~ __ ~_:_~ __ J
MO-OM3
--+-
reo (")
r ....
cc
r
i:'
~~:
~ ..
IT "-
'"
'" a. '" co
-,---,...>
MODO. PMOOI
ES
. ------- --
''''''I
I
~
~
V-
~. ~
CD
Address multiplexer
MCS.MWEI
generator
_
rr===
I
~;,~
r;::=::d
I
generator
r1
r
3
,..-..1-.=---"'0£...,••
1
t
1
::;0
~~
:::J
CD
Write counter
(Horizontal.
vertical counter)
H
OISPTMG
~ ~
·
rl
generator
-tt--- RO-R3/LUO-LU3
} GO-G3/LOO-L03
4 ) BO-B3
13
~~
ROO-RD7
GOO-G07
BOO-B07
Meso
MAO-MA 12
MCSI
MAI3-MAI5
MWE
~
g
:r:o
en
en
ex>
~
o
0>
~
~
II
HD66840F
Registers
Table 5 lists the internal registers and figure 1
illustrates the bit assignment to the registers.
Register List
Table 5
CS
RS
AdcIras Register
2
1
0
3
Reg.
No.
Program
Unit
Register Name
Read/
Write
Invalid
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RO
Control register 1
R/W
R1
Control register 2
R/W
R2
Vertical displayed lines register (middle-order)2
Line
R/W
R3
Vertical displayed lines register (low-order)2
Line
R/W
R4
Vertical displayed lines register (high-order)2
Line
R/W
CL3 period register (high-order)3
Char
'R/W
R5
CL3 period register (low-order)3
Char
R/W
R6
Horizontal displayed characters register (highorder)4
Char
R/W
R7
Horizontal displayed characters register (low-order)
Char
R/W
R8
CL3 pulse width register
Char
R/W
R9
Fine adjust register6
Dot
R/W
0
R10
PLL frequency-dividing ratio register (high-order)6
R11
PLL frequency-dividing ratio register (low-order)6
0
R12
Vertical backporch register
R13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Address register'
AR
0
0
0
0
Notes: 1.
2.
3.
4.
5.
6.
7.
R/W
R/W
Line
R/W
Vertical backporch register (low-order)2. 7
Line
R/W
R14
Horizontal backporch register (high-order)2. 7
Dot
R/W
R15
Horizontal backporch register (low-order)2. 7
Dot
R/W
(high-order)2. 7
If you attempt to read data from the register with RS = 0, the bus is driven to highimpedance state and the output data is indefinite.
(The specified value - 1) should be written into these registers.
Valid only in 8-color display modes with horizontal stripes.
The most significant bit is invalid in dual screen configuration modes.
Valid only when the display timing signal is supplied externally.
Valid only when generating the dot clock.
Valid only when generating the display timing signal internally.
H.ITACHI
610
Hitachi America, Ltd. 0 Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300
HD66840F
Register No.
Control register 1
Control register 2
Note: ~ indicates invalid bits. Attempting to read data from these register bits
returns indefinite output data.
Figure 1
Register Bit Assignment
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
"'-"'------"-~-
--. ---
_.------_.
611
..-.-----_.
HD66840F
System Configuration
Figure 2 is the block diagram of a system in
which the LVIC is used outside of a personal
computer.
circuit, using HSYNC as a basic clock. The
frequency of the dot clock is specified by the
PLL frequency-dividing ratio register (RiO,
Rll).
The LVIC converts the R, G, B serial data sent
from the personal computer into parallel data
and writes them into the buffer memories
once. It reads out the data in turn and outputs them to LCD drivers to drive an LCD.
Here the latch clock of the serial data, namely
the dot clock (DOTCLK) is generated by a PLL
DOTCLK
r-1
CU
R, G, B serial data
Personal
computer
The user may also configure a system without
VCO and LPF if supplying the dot clock
externally and may configure a system without the MPU if the LVIC is controlled by the
pin programming method.
~;~.
II
MPU
11
CD
~
1
HSYNC
VSYNC
0.--1L-;----CD1
LVIC
U
Buffer
memory
r
I
Simultaneous LCD and CRT display
is possible
I
VCO = Voltage-controlled oscillator
LPF = Lowpass filter
Figure 2
System Block Diagram (MPU Programming Method, Regenerates DOTCLK)
HITACHI
612
Hitachi America, Ltd.· Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66840F
Functional Description
Programming Method
The user may select one of two methods to
control the LVle functions: by pin programming method or by internal registers (internal
register programming method). The internal
register programming method can be divided
into the MPU programming method and the
ROM programming method. The MPU writes
data into internal registers in the MPU programming method and ROM writes the data
in the ROM programming method. Table 6
lists the relation between programming
method and pins.
Table 6
Pin Programming Method: LVle mode
setting pins control functions in the pin programming method.
Internal Register Programming Method:
In the internal register programming method,
an MPU or ROM writes data into internal
registers to control functions. Figure 3 illustrates the connections of MPU or ROM and
the LVle. Figure 3 (1) is an example of using
a 4-bit microprocessor, but since the LVle's
MPU bus is compatible with the 4-MHz 80family controller bus, it can also be connected
directly with the bus of host MPU.
Programming Method Selection
Pins
PMOD1 PMDDO Programming Method
o
o
o
Pin programming
Internal register
With MPU
Programming
With ROM
-------
o
Prohibited (Notel
Note: This combination is for a test mode and
disables display.
4-bit MPU
BO
B1
B2
B3
ROM
.CS
RS
WR
RO
00-03
AO-A3
/4
'"
00-03
4
'"
00-03
LVIC
"
4
AO-A3
LVIC
(1) Connection of MPU and LVIC
Figure 3
.
AO-A3
(2) Connection of ROM and LVIC
Connection of MPU or ROM and LVle
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613
HD66840F
Screen Size
Screen size can be programmed either by
pins or internal registers.
In the pin programming method, the user
may select either 640 dots or 720 dots (80
characters or 90 characters) as the number of
horizontal displayed characters with the
XDOT pin, and 200, 350, 400, 480, 512, or 540
lines as the number of vertical displayed lines
with YL2-YLO pins. The number of vertical
displayed lines can be adjusted with ADJ and
F3-FO pins within +0 to +15 lines. -,
the user may select any even number from 32
dOt$ to 4048 dots (= 4 characters up to 506
characters) with the horizontal displayed
characters register (R6, R7), and any even
number from 4 lines up to 1028 lines with the
vertical displayed lines register (R2, R3 and
the high-order two bits of R4). However, odd
number of lines can also be selected when
screen configuration is single and a Y-driver (scan driver) is set on one side of an LCD
screen.
Figure 4 illustrates the relation between an
LCD screen and pins and internal registers
controlling screen size.
In the internal register programming method,
Number of horizontal displayed characters
Pin:XDOT
Register: Horizontal displayed characters
register (R6. R71
T
Number of vertical displayed lines
Pin: YL2-YLO. ADJ. F3-FO
Register: Vertical displayd lines
register (R2. R3. highorder 2 bits of R41
1
LCD screen
L -____________________________
Figure 4
------~
Relation between LCD Screen and Pins and Internal Registers
HITACHI
614
Hitachi America, Ltd.·,Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005,1819· (415) 589-8300
HD66840F
Memory Selection
Nvd: number of vertical displayed lines
The user may select 8-, 32-, or 64-kbyte
SRAMs as buffer memory for the LVIC. Since
the LVIC has a chip selector for these memories, no external decoder is required. The
user selects the memory with pins MSl and
MSO or with data bits MSl and MSO of the
control register 2 (Rl). Table 7 lists the kinds
of memories and pin address assignments.
Memory capacity required depends on screen
size and can be obtained with the following
expression:
Memory capacity (bytes) = Nhd x Nvd
Nhd: number of horizontal displayed characters
Table 7
For example, a screen of 640 x 200 dots
requires 16-kbyte memory capacity since 80
characters x 200 lines is 16 kbytes. (8 dots
compose a character.) Therefore, each plane
needs two HM6264s, which have 8-kbyte
memory capacity, in 8-level gray scale display
modes. Connect MCSO with one of the memories of each plane and MCSl with the other
(figure 5 (a)).
When the screen size is 640 x 400 dots, 32kbyte memory capacity is required (figure 5
(b)). Therefore, each plane needs a HM62256,
which have 32-kbyte memory capacity.
Connect MCSO with CS of the memories here.
Memories and Pin Address Assignment
Pins orBits
MS1
MSO
Memory
0
0
No memory'
8-kbytes
0
0
32-kbytes
64-kbytes
Note:
Address Output Pins
Chip Select Pins
Address Assignment
MAO-MA12
MCSO
$0000-$1 FFF
McsT
$2000-$3FFF
MA13
$4000-$5FFF
MA14
$6000-$7FFF
MA15
$8000-$9FFF
MCSO
$00000-$07 FFF
MCS1
$08000-$OFFFF
MA15
$10000-$17FFF
MCSO
$OOOOO-$OFFFF
MCS1
$10000-$1 FFFF
MAO-MA14
MAO-MA15
1 . There are some limitations when the user uses no memory. Refer to "User Precautions."
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
615
HD66840F.
Ex. 640x200dot
Ex. 640 x 400 dot
CSHM6264 B
CS HM6264G
MCSO-....-~~CS
R
HM6264
MCS1
-.....-1.~-.tccs~=~1
HM6264
(a)
16-kbytes Memory system
Figure 6
(b) 32-kbyte& Memory system .
Relation between Display Screen Memories
HITACHI
616
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
l
HD66840F
Display Modes
The LVIC supports 16 display modes, depending on the state of the DM3-DMO pins. The
display mode consists of display color, type of
LCD data output, how to set LCD drivers
around an LCD screen, how to arrange color
data (= type of stripes), and how to output M
signal (= type of alternating signal). Table 8
lists display modes.
Table 8 Modes List
Mode
No.
1
2
3'
4
5'
6
7
8
91
10 1
111
121
13 1
141
15 1
16 1
LCD Data Output
Display Data
SCI'Mn LCD Driver
DM3 DM2 DM1 DMO Color
TI'IIIISfer Config. X-Driver2
Monochrome 4-bits
Dual
One side
0
0
0
0
1
Single
0
0
0
0
0
0
1
1
8-bits
0
0
0
0
0
Pins
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
8-level
4-bits
Dual
gray scale
Single
8-bits
8-color
12-bits
(4 bits
for R,G,B
each)
Notes: 1.
2.
3.
4.
Stripe4
Alternating
Per frame
Vertical
Per line
Both sides
One side
Both sides
One side
Both sides
One side
Both sides
0
Setting
Y-Drivr
One side
Both sides
One side
Both sides
One side
Both sides
One side
Both sides
Horizontal
For TFT-type LCD
Data output driver
Scan driver
Refer to "Display Color, 8-Color Display·
I
HITACHI
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617
HD66840F
Display Color
The LVIC converts R, G, B, the color data for
CRT display, into the monochrome, 8-level
gray scale, or 8-color display data.
1\IIonochrome Display (1\IIode 1 to 1\IIode 5):
In monochrome modes 1-5, the LVIC displays
two colors, namely black (= display on) and
white (= display off). As shown in table 9, the
OR of CRT display R, G, B data determines the
display color.
8-Level Gray Scale Display (1\IIode 6 to
lIIIode 8): In 8-level gray scale modes 6-8, the
LVIC thins out data on certain lines to display
an 8-level gray scale according to CRT display
Table 9
1
0
0
0
1
0
0
1
1
0
0
0
0
Table 10
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
CRT Display Color
LCD
Color
On/Off
On
On
On
On
On
On
On
Off
Black
Black
Black
Black
Black
Black
Black
White
Color
LCD
Contrast
High
Black
Strong
Low
White
Weak
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
8-Level Gray Scale Display
CRT Display Data
R
G
B
0
0
8-Color Display (1\IIode 9 to 1\IIode 16): In 8color modes 9-16, the LVIC displays 8 colors
with red (R), green (G), and blue (B) filters on
liquid crystal cells. The eight colors are the
same as those provided by CRT display. As
illustrated in figure 5, 8-color display has of
two stripe modes: horizontal stripe mode and
vertical stripe mode. In the former mode, the
LVIC arranges R. G, B data horizontally, with
horizontal filters. In the latter mode, the LVIC
arranges R, G, B data vertically, with vertical
filters. Three cells express a dot in' both
modes.
1\IIonochrome Display
CRT Display Data
R
G
B
1
color (luminosity). Table 10 shows the relation
between CRT display color (luminosity) and
LCD color (contrast).
0
1
0
1
0
CRT
Color
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
HITACHI
618
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
X-driver
1 dot
~
ilUU
f---r'--
I
I
>-~
~
I
:----
r
I
R filter
B filter
I
I
I
I
I
G
I
B
I
I
I
I
I
HH.....-- -- - - - - ------
G filter
I
I
I
X-driver
1 dot
R
R
II
I
I
I
I
Horizontal Stripe
Figure 6
G
B
LBfilter
G filter
R filter
Vertical Stripe
Stripe Modes in 8-Color Display
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
619
HD66840F
•
LCD System Configuration
How to set LCD drivers around LCD
screen:
-X-driver: On one side or on both sides'
- Y-driver: On one side or on both sides
The LVIC supports the following system configurations for LCD:
•
Figure 7 illustrates these system configurations by mode.
Types of LCD data output:
-Data transfer: 4-bit, a-bit, or 12-bits (4
bits for R, G, Beach)
-Screen configuration: Single or dual
4-bit
Data
4-,8-, 12-bit
.1
">I
-
I- -
~CD lup ~an~1
1
1
1
- foo
~
>
1
LCD down panel
I I
X-driver
.--
I--t-I-I-r
1-1-
1
Data
LL L L
~I'1:
Up panel X-driver
I I
LCD screen - ..
'1:
..
i'
I
>-
1 1 1
-
f f t t
_I Down panel X-driver
Data
4-bit
System Configuration for Modes 2,4,7,8,9, and
13 (4-, 8-, or 12-Bits Data Transfer, Single Screen,
X-Driver and V-Driver on One Side Each)
System Configuration for Mode 1 and Mode 6 (4Bits Data Transfer, Dual Screen, X-Driver and VDriver on One Side Each) (Note)
4-,8-, 12-bit
Data
12-bit
Data
X driver
f
.~
~
~
Up X-driver
-
---.
~
~
'1:
">-I
LCD screen
'1:
.l:
--
LCD screen
">-I
.2'
I
-
.....
II:
.1
Data
Down X-driver
12-bit
System Configuration for Modes 3,5, 10, and 14
(4-,8-, or 12-Bits Data Transfer, Single Screen, XDriver on One Side and V-Driver on Both Sides)
Note:
System Configuration for Mode 11 and Mode 15
(12-Bits Data Transfer, Single Screen, X-Driver on
Both Sides and V-Driver on One Side)
Although there are two X-drivers, the X-driver is considered to be set on one
side, not on both sides, because the LCD up panel and down panel are each
regarded as one screen.
Figure 7
System Configurations by Mode
HITACHI
620
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD66840F·
Calculation of LDOTCK
fF: FLM frequency
LDOTCK frequency fL is calculated from the
following expression:
Here fL must hold the following relation,
where fo is frequency of dot clock for CRT
display (= DOTCLK).
fL = (Nhd + 6) x 8 x Nvd x fp
Nhd: number of horizontal characters displayed on LCD
Nvd: number of virtical displayed lines on
LCD
fL
fL
< fo
x 15/16 or
= fo (The LDOTCK phase must be inverse
of the DOTCLK phase in this case)
12 -b·t
I
Data
Up X-driver
f
-
• •
.~
~CD scr~en
"t:I
1
>-
.~
-~
"t:I
1
>-
~
.E
"--
-
.S!'
IX:
J
Data
r--
I
Down X-driver
12-bit
System Configuration for Mode 12 and Mode 16
(12-Bit Data Transfer, Single Screen, X-Driver
and V-Driver on Both Sides Each)
Notes: 1.
2.
X-drivers on both sides: Data output wires run from up and down X-drivers
alternately, which widens the interval between wires to twice that for an X-driver an
one side (figure 8).
V-drivers on both sides: Line select signal output wires run from right and left Vdrivers alternately, which widens the interval between wires to twice that for Vdriver on one side (figure 9).
Figure 7
System Configurations by Mode (cont)
Up X-driver
~_ _ _
Data output
wires
Signal output wires
Data
Down X-driver
Figure 8
X-Drivers on Both Sides
Figure 9
V-Drivers on Both Sides
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Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point PkWy.· Brisbane, CA 94005-1819· (415) 589-8300
621
HD66840F
Display Timing Signal Generation
CRT display data is classified in1;O display
period data and retrace period data. Only
display period data is necessary for LCD.
Therefore, the LVIC needs a signal announcing whether the CRT display data transferred
is for the display period or not. This signal is
the display timing signal.
The LVIC can generate the display timing
signal from HSYNC and VSYNC. Figure 10
illustrates the relation between HSYNC, VSYNC, the display timing signal (DISPTMG),
and display data. Y lines and X dots in the
figure are specified by the vertical backporch
register (R12, R13) and the horizontal backporch register (R14, R15) respectively.
__ _________________________________________________
v~Cn
~
1--1
Y tines (= Vertical backporch)
HSYNC
~~----------~n. . ----------------'nL..-----_----x dots (= Horizontal backporCh)
---.IJ
o-----____-tI...
DISPTM-G-----1I...
Display period
(= No. of horizontal
displayed characters)
Retrace period
~!:~--.F---:-------~I.------~I.------~----------:~I.------~I.-::-.:--=.:--::
.
Figure 10
Valid
Invalid
Valid
Invalill
Valid
Relation between HSYNC. VSYNC. DISPTMG. and Di8play Data
HITACHI
622
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Dot Clock Generation
The dot clock, which is a data latch clock, is
not a standard video signal and does not
appear from the CRT display plug. Thus it is
necessary to generate the dot clock. The
LVIC has a programmable counter .and a
phase comparator which are parts of a PLL
circuit, and ~ generate the dot clock from
HSYNC if a charge pump, a lowpass filter
(LPF), and a voltage-controlled oscillator
(VCO) are externally attached.
Figure 11 is a block diagram of a PLL circuit. A
PLL (phase-locked loop) circuit is a feedback
controller regenerating a clock whose frequency and phase are the same as those of a
basic clock. The basic clock is HSYNC here.
At power-on, VCO outputs to the programmable counter a signal whose frequency
depends on the voltage at the time. The
counter divides the frequency of the signal
according to the value in the PLL frequencydividing ratio register (Rl0, Rl1) and outputs
it to the phase comparator. This is the
frequency-divided clock.
The comparator compares the ed~ of the
clock and HSYNC and outputs CU or CD
signal to the charge pump and LPF according
to the result. The comparator outputs CU
when the frequency of the clock is lower than
that of HSYNC or when the phase of the clock
is behind that of HSYNC, while it outputs CD
in the contrary case. The charge pump and
LPF apply voltage to the VCO according to
CU or CD signal.
This operation is repeated until the phase
and the frequency of the frequency-divided
clock coincide with those of HSYNC, making
it a stable dot clock.
!
HSYNC
co
Inside LVIC
~
Phase
comparator
CD
Charge pump
LPF
Frequencydivided clock
Written value in
PLL frequency-dividing ratio
register (R10, R11)
q
Programmable
counter
VCO
Timing clock generator
DOTCLK
Figure 11
PLL Circuit Block Diagram
HITACHI
Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300
623
HD66840F
Doubled-In-Height Display
Doubled-in-height display doubles characters
and pictures in height as illustrated in figure
12.
In TN-type LCD modes (= modes 1, 2, 4, 6, 7,
and 8), CL3 frequency is twice as high as CLl
frequency (figure 13). As a result, using CL3
in~tead of CLl as a shift clock (figure 14)
enables two lines to be selected while an Xdriver (data output driver) is outputting the
same data, realizing doubled-in height dis-
,
play. However, the following procedures are
necessary in this display since multiplexing
duty ratio becomes twice as great as the
value specified as the number of vertical
displayed lines.
1.
Halve the frequency of the LCD dot
clock (= LDOTCK)
2. Halve the number of vertical displayed
lines
This function is provided only for TN-type
LCD.
••
II
I
I
I
:.:
Itt"
.~ ~
•• ••
••••••••
••••••••
•• ••
•• ••
• •
••
•• ••
••••••
I• I•
I
I..l
..
r.-,
. .•
I
I
I
:.J
•
Normal display
Doubled-in-height display
Figure 12
Doubled-In-Height Display Example
HITACHI
624
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
r
r.
CL1
CL3
~
X-driver
output
)l
r
r.
/
r
r
r
)(
}.
\
V-driver
\
Figure 13
Relation between CL1 aDd CL3 In Modes 1.
2. 4, 6. 7. aDd 8
4 (or 8) bits
LUO-LU3. LoQ-Lo3 ---"""_'----.....- - - - - - - - - - - - - ,
CL1:============~~_r_~x~~riV~e~~(d~ats::ou~tP~u:t~dr~iw:~~)~-J
C~
•
11
M
~
r---
CL3
FLM
M
LCD Panel
Figure 14
ConnectloD for Doubled-In-Height Display
HITACHI
Hita~hi
America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
625
HD66840F
Display Timing Slgnfll Fine Adlusment
When the display timing signal is supplied
externally, a phase .shift .might appear
between CRT data and the display timing
signal. This is because each signal has its own
peculiar lag. The LVIC can adjust the display
timing signal with the FO-F3 pins or the fine
adjust register (R9) to correct this phase shift.
Table 11 shows the relation between F3-FO
pins, data bit 3 to data bit 0 of the fine adjust
register, and fine adjustment. Concerning the
polarity of the number of dots adjusted, indicates advancing the phase of the display
timing signal and + iDdicates delaying it. F3
Table 11
Pin:
R9 Bit:
Note:
pin or data bit 3 of R9 selects the polarity. The
adjustment reference point is the display
start position.
Figure .15 shows examples of adjusting the
display timing signal. Since the signal is two
dots ahead of the display start position in
case (1), (F3, F2, Fl, FO) or (data bits 3, 2, 1, 0 of
R9) should be set to (1, 0, 1, 0) to delay the
signal for two dots. Since the signal is two
dots behind the display start position in case
(2), they should be set to (0,0, 1, 0) to advance
the signal for. two dots. When there is no need
to adjust the signal, settings of either (0, 0, 0,
0) or (1, 0, 0, 0) will do.
Pins, Data Bits of R9, and Fine
Adlustment
F3
3
0
F2
F1
1
2
0
0
0
0
1
1
0
0
1
0
0
FO
0
0
Number of Dots
AdjU8t8d
0
- 1
0
1
0
-6
-7
0
+ 1
0
+6
+7
When adjusting the display timing signal
with pins, set ADJ pin to 1 .
HITACHI
626
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66840F
I+-- .Displav start position
I
CRT data
I
---
two dots advanced
DISPTMG
before adjustment
,
Displav Timing Adjust
(F3. F2. F1. FO.)/
(Data bits 3. 2. 1.0 of R9)
.
;----------------1
=(1.0.1.0)
OISPTMG
after adjustment
(1)
Delaying DISPTMG
\ . - - DisplaV start position
I
CRT data
two dots delayed
DISPTMG
before adjustment
Displav Timing Adjust
(F3. F2. F1. FO)/
(Data bits 3. 2. 1.0 of R9)
= (0.0.1.0)
DISPTMG _"""""_ _ _ _ _ _ _ _ _ _ _ _--'
after adjustment
(2) Advancing DISPTMG
Figure 16
Adjustment of Display TlmlDg SlgDal
HITACHI
Hitachi America, Lid .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
627
HD66840F
Internal Registers
The LVIC has an address register (AR) and.
sixteen data registers (RO-R15). In order to
specify one of the sixteen data registers,
write its register address into the address.
register. The MPU transfers data to the data
register corresponding to the written
address.
All the registers are valid only when the LVIC
is controlled by the internal register progranuning method and are invalid (don't
care) when by the pin programming method.
Control Register 1 (RO)
Control register 1 (figure 17) is composed of
four bits, including two invalid bits. Each of
two valid bits has its own function. Reading
from and writing into invalid bits are possible.
However, these operations do not affect the
LSI function.
•
timing signal
-DSP = 0: LVIC does not generate the
display timing signal
(If DCK = 1, the display timing signal is
generated in spite that DSP = 0)
Address Register (AR)
The address register (figure 16) is composed
of four bits and specifies one data register out
of sixteen. This register is selected by the
MPU when RS pin is low and specifies any
data register with the register address written by the MPU.
DSP Bit
-DSP = 1: LVIC generates the display
•
DCK Bit
-DCK = 1: LVIC generates the dot clock
-DCK = 0: LVIC does not generate the
dot clock
AR
Data Bit
Value
Figure 16
Address Register
RO
Data Bit
Function
Figure 17
~
1
DSP
I
D~KJ
Control Register 1
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HD66840F
Control Register 2 (RO)
Control register 2 (figure 18) is composed of
four bits and has three functions.
•
MC Bit
-MC = 1: M signal alternates per line
-MC = 0: M signal alternates per frame
•
DON Bit
-DON = 1: Display on
-DON = 0: Display off
•
MSl and MSO Bits
-Select the memory type (table 12)
Vert1c:al Displayed Lines Register (R2,
R3, High-Order 2 Bits of R4), CL3 Period
Register (Low-order 2 Bits of R4, R6)
The vertical displayed lines register (figure
19) is composed of ten bits (R2 + R3 + high-
Table 12
MS'
0
0
order two bits of R4) and specifies the number of vertical displayed lines. This register
can specify both even and odd numbers in
modes for a Y-driver on one side and single
screen configuration, but even numbers only
in the other modes. The value to be written
into this register is (Nvd - 1), where Nvd =
number of vertical displayed lines.
The CL3 period register is composed of six
bits (low-order two bits of R4 + RS) and
specifies the period of CL3 in 8-color display
modes with horizontal stripes. Thus this register is invalid in the other modes. CL3 is a
clock for the LVIC to output R, G, B data
separately to LCD drivers. The value to be
written into this register is (Nhd + 6) X 1/3 1, where Nhd
number of horizontal displayed characters. When (Nhd + 6) is not
divisible by 3, the quotient should be rounded
up or rounded down.
=
Memory Type and Mal, MSO
Memory Type
No memory
8-kbytes
32-kbytes
64-kbytes
MSO
0
1
0
Data Bit
Function
Figure 18
. R4
Data Bit
Value
Control Register 2
R2
;-\/
31 2 1 3
R3
_\L
1 2 1 1 10131 2
Nvd - 1 (Unit: Lines)
J 1 1°
Vertical Displayed lines Register
Flgure19
R4
R6
\/\/
\
11013121110
(Nhd + 6) x 1/3 -1
(Unit: Characters)
Cl3 Period Register
Vertical Displayed Lines Register and CL3 Period Register
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629
HD66840F
Horizontal Displayed Characters Register (R6. R7)
CL3 Pulse Width Register (RS)
The CL3 period'register (figure 22) is composed of four bits and specifies the high-level
pulse width of CL3. When controlling TFTtype LCDs, each gate of the LCD has to hold
data from the time a Y-driver' outputs the line
select and shift signal to the time an X-driver
the outputs next display data. Data must be
held while CL3 is high. However, even when
the LVIC is not controlling TFT-type LCDs,
CL3 appears with the high-level pulse width
specified by this register.
The horizontal displayed characters register
(figure 20) is composed of eight bits (R6 + R7)
and specifies the number of horizontal displayed characters. This register can specify
even numbers only. The most significant bit
of R6 is invalid in the modes for dual screen
configuration. When writing into this, register, shift (Nhd - 1) in the low-order direction
for one bit to cut off the least significant bit.
Figure 20 shows how to write a value into the
register when Nhd = 90.
R6
R7
/
\/
\
Data Bit
Value
Horizontal Displayed Characters Register
Figure 20
R7
R6
I
I
\/
/
Data Bit
Value
I
3
I
2
I
I
0
I
0
I
I
I
0
0
31 2
11 1
\
1 1 1°j
1°1 O j
r
t
Cut off
L-I
90 - 1 = 89
Figure 21
0
0
0
How to Write The Number of Horizontal Displayed Characters
R8
I
I
/
Data Bit
Value
\
I
I
I-- TN-type,LCD modes: Npw
'-- TFT-type LCD modes: Npw - ,5 (Unit: Characters)
,Npw = number of horizontal characters while CL3 is high
Figure 22
CL3 Pulse Width Register
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630
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Fine Adjust Register (R9)
Rl1) and specifies the PLL frequency-dividing
ratio for generating a dot clock by a PLL
circuit. The value to be written into this register is determined by the ratio of the frequency of HSYNC to that of the dot clock
which the user wants. This register is invalid
when the dot clock is supplied externally and
is valid only when the LVIC is controlled by
the internal register programming method
and the DCK bit of control register 1 (RO) is 1.
The written value in this register (NPLL) is
obtained with the following expression:
The fine adjust register (figure 23) is composed of four bits and adjusts the externally
supplied display timing signal to synchronize
its phase with that of LCD data. The value to
be written into this register is determined by
the interval between the positive edge of the
display timing signal and the display start
position. For more details, refer to "Display
Timing Signal Fine Adjustment." This register
is invalid when the display timing signal is
generated internally.
NPLL =Ncht x 8 - 731
Ncht: total number of characters for CRT
Ncht can be obtained as follows from the
specifications of a CRT monitor:
Ncht = 1/8 x (DOTCLK frequency)/
(HSYNC frequency)
PLLFrequency-Dlviding Ratio Register
(R10, Rl1)
The PLL frequency-dividing ratio register
(figure 24) is composed of eight bits (R10 +
R9
/
1
1
Data Bit
Value
\
1 3 1 2 1 1 1 0 1
1
1
1
I.......
Absolute value of Nda (Unit: Dots)
. {O: + (Advance the display timing signal)
Selects polarity
...
.
.
1: - (Delay the display timing signal)
Nda = number of dots adjusted
Figure 23
Fine Adjust Register
R10
R11
V
/
1
1
Data Bit
Value
\
3121 1 1013121 1 101
J
\
3
0
0
0
1
1
1
2
1
0
Frequency-Dividing Ratio
HSYNC : Dot Clock
0
0
0
3
0
0
0
0
0
0
0
0
1
0
1
0
1 : 731
1 : 732
1 : 733
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1 : 984
1 : 985
1 : 986
2
1
0
0
0
0
0
0
0
1
1
1
1
1
1
Figure 24
PLL Frequency-Dividing Ratio Register
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631
HD66840F
Vertical Backporch Register (RI2, R13)
Horizontal Backporch Register (RI4, R15)
The vertical backporch register (figure 25) is
composed of eight bits (R12 + R13) and specifies the vertical backporch. The vertical
backporch is the number of lines between the
positive edge of VSYNC and that of the display timing signal (DISPTMG). For more
details, refer to "Display Timing Signal Generation." This register is invalid when the
display timing signal is supplied externally
and is valid only in a system which controls
the LVIC by the internal register programming method and where the DSP bit of control register 1 (RO) is 1. (If the DCK bit of
control register 1 (RO) is 1, DISPTMG will
always be regenerated and the register is
enabled even when DSP = 0.)
The horizontal backporch register (figure 26)
is composed of eight bits (R14 + R15) and
specifies the horizontal backporch. The horizontal backporch is the number of characters
between the positive edge of HSYNC and
that of the display timing signal (DISPTMG).
For more details, refer to "Display Timing
Signal Generation". This register is invalid
when the display timing signal is supplied
externally and is valid only in a system which
controls the LVIC by the internal register
programming method and where the DSP bit
of control register 1 (RO) is 1. (If the DCK bit of
control register 1 (RO) is 1, DISPTMG will
always be generated and this register is
enabled even when DSP = 0.)
R12
/
I
Data Bit
I
Value
R13
\/
I
I
\
0
I
I
I
L
Ncvbp - 1 (Unit: Lines)
Ncvbp = number of lines between the positive edge ofVSYNC and
that of DISPTMG
Figure 25
Vertical Backporch Register
R14
I
l
/
R15
\/
Data Bit
Value
I
I
I
\
0
I
I
L
Nchbp x 8 - 1 (Unit: Dots)
Nchbp = number of characters between the positive edge of HSYNC and
that of DISPTMG
Figure 26
Horizontal Backporch Register
HITACHI
632
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Reset
RES pin resets and starts the LVIC. Make 'sure
to hold the reset signal low for at least 1 pS
after power-on.
Reset is defined as shown in figure 27.
Fixed low: MAO-MA12, RO-R3, GO-G3, BOB3, CS, CLl, CL3, FLM. AO-A3. CU
5. Fixed high or low depending on the
memory in use (table 13): MA13-MA15,
MCSO
State of Pins During Reset
State of Registers During Reset
RES basically does not control output pins
and operates regardless of the other input
pins. Output pins can be classified into the
following five groups depending on their reset state.
RES pin does not affect register contents.
Therefore, registers can be both read and
written by the MPU even during reset. Registers keep the contents they had before reset
until they are rewritten.
1.
2.
Memory Clear Function
3.
Keeps state before reset: CL2
Driven to high-impedance state (fixed
low when using no memory): RDO-RD7,
GDO-GD7, BDO-BD7
Fixed high: MWE, CL4, M, CD, MCSl
Table 13
4.
After reset, the LVIC writes 0 in the memory
area specified by MSELO and MSELl (table 7)
regardless of R, G. B data.
Memory Type and State of Pins During Reset
Kind of Memorlee
MA13
MA14
MA15
No memory
Low
Low
High
MeSO
High
8-kbyte memory
High
High
High
Low
32-kbyte memory
Low
Low
High
Low
64-kbyte memory
Low
Low
Low
Low
~-~
At::::
r
During reset
(Reset stete)
Figure 27
t-
After reset
Reset Definition
HITACHI
Hitachi America, Ltd.· Hitachi Plaza • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
633
HD66840F
User Precautions
1.
There are the following limitations when
the user uses no memory (MSELO = 0,
MSELl = 1).
•
•
The display modes for dual screen
configuration (= mode 1 and mode 6)
are disabled.
.
The LVIC cannot support the LCD
systems with Y-drivers on both sides.
Even if the user selects the mode for a
system with Y-drivers on both sides
(= mode 3, 5, 10, 12, 14, or 16), the
operation of the LVIC is exactly the
same as that in the mode for the system with a Y-driver on one side (=
mode 2, 4, 9, 11, 13, or 15).
2.
The LVIC might operate irregularly until
the internal registers have been written
after reset in the system which controls
the LVIC by internal register programmingme$od.
3.
Memory clear function might not work
normally at power-on or after reset if
MSELO and MSELl are not properly set to
the value corresponding to the memories
in use.
4.
Since the LVIC is a CMOS LSI, input pins
must not be left disconnected. Refer to
table 1 concerning how to deal with each
pin.
Leave CL4 terminal disconnected iIi this
case.
Programming
The values written in internal registers have
the limits listed in table 14. The symbols in the
Table 14
Limit on Values Written in Registers
Function
Screen
Configuration
CL3 Control
DISPTMG
Regeneration
Without
Buffer Memory
Notes: 1.
2.
3.
4.
5.
6.
7.
B.
table are defined as shown in table 15 and
figure 27.
Limit
Notea Applicabl. RlI9iBt11r.
~4~~~N~v~d~~~(N~~~b~p~+~N~cv~S~p~)~-~1~~~1~0~24~~=-__~=-__ R2, R3, R4, R6, R7
4 ~ Nhd .:ii (Nchbp x 1In + Nchsp) - 1 ~ 506
1, 8
R2, R3, R4, R6,
2, 8
(Nhd + 6) x n x Nvd XfF ~ fo :ii 30 MHz
71~~~N~p~w~~~(~N~hd~+~6~)~X_1~/~2~-~1_____________3~____ R4,R5, R6, R7.
~ Npw.:ii Nhd
4
~ Npw :a Npc - 1
5
:a Nchbp ~256
6
R12, R13, R14,
~ N~bp ~ 256
6
7
4 :ii Nhd ~ Nchsp - 4
R2, R3, R4, R6.
4.:ii Nvd .:ii Ncvsp - 4
7
R7
R8
R15
R7
Nhd ~ 256 in dual screen configuration (= mode 1 and mode 6)
fF:FLM frequency·, fo: frequency of CRT dot clock, fL: frequency of LCD dot clock for LCD
fL < fo x 15/1'6, OrfL = fo
·In modes 1, 2, 4, 6, 7, and B
In modes 3, 5, 9, 10, 11, and 12 (Npw = (value in RB) '+ 5)
In modes 13,14,15, and 16 (Npw = (value in RB) + 5)
Value in R14, R15 ~ (Nchsp x n + Nchbp) - Nhd x n - 2
Value in R12, R13 :ii (Ncvsp + Ncvbp) - Nvd - 2
Nht = Nchsp + Nchbp x 1/n, Nd = Ncvbp + Ncvsp
(Nht = Nhd + 6, Nd = Nvd when using buffer memory)
n: Horizontal character pitch (the number of horizontal dots in one character).
HITACHI
634
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589·8300
HD66840F
Table 15
Symbol
Symbol Definition
DefInition
Nchd
Number of horizontal displayed characters on CRT display
Nchsp
Number of characters between the positive edge of DISPTMG and that of HSYNC (= Horizontal sync position)
Nchbp
Number of dots between the positive edge of HSYNC and that of DISPTMG (= horizontal
backporch)
.
Ncvbp
Number of lines between the negative edge (positive edge when VSYNC is high in active state)
of VSYNCand the first positive edge of DISPTMG (= vertical backporch)
Ncvsp
Number of lines between the first positive edge of DISPTMG and the next negative edge of
VSYNC (= vertical sync position)
Ncvd
Number of vertical displayed lines on CRT display
Nhd
Number of horizontal displayed characters (on LCD)
Npc
Number of characters during CL3 period (= CL3 pulse cycle)
Npw
Number of characters while CL3 is high (= CL3 pulse width)
Nht
Total number of horizontal characters
Nvd
Number of vertical displayed lines (on LCD)
HITACHI
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HD66840F
I
I
DOTCLK
DISPTMG
LJLJLJL------JLJ1---..fL _______ ~
I
~
I
I
I"
1
HSYNG
.1
Nchd
1
I
1
I" + - - - - - - - - - N C h s P - - - - - - - - o - f I••---Nchbp---oooll
1
I
I
VSYNC
DISPTMG
I
1
I
JUlJUlL.."I---.!..:- - --Ir--------tfU1Jlfl-----1
ot.,
Ncvsp
I
0,
Ncvbp
I"
I
I
I
I
CL2
Cl1
I
:"
.1
Ncvd
:
:LflJIl-----Jl~I--------------~~
,
,rl--------------------+I------~
' r - l~----------------:"
Nhd
.:
Cl1
- , __________________________________
Cl3
--,
I~.
n
~
~
___
----------------~,
I
t.-- Npw-+J
I
I
I
rl
:
"''''~-----Npc----'---~ol
I
,
I
,~,,,~--------------Nht------------~.II
FlM
Cl1
I~
____________________________
~r_l~
___
-fLJUl---------------I
,"
I
Nvd---------...;°l
I
I
Figure 28
Symbol Definition
HITACHI
636
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Absolute Maximum Ratings
Symbol
Ratings
Unit
Power supply voltage
Vee
- 0.3 to + 7.0
V
Input voltage
Vin
- 0.3 to Vee + 0.3
V
Operating temperature
Topr
- 20 to + 75
'C
Storage temperature
Tstg
- 55 to + 125
·C
Item
Notes: 1.
2.
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation
should be under recommended operating conditions (Vee =5.0 V ± 10%, GNO = 0 V, Ta
= -20'C to +75·C). If these conditions are exceeded, it could affect reliability of the LSI.
All voltages are referenced to GNO = 0 V.
Electrical Characteristics
DC Characteristics 1 (Vee
= 5.0 V
± 10 %, GND
= 0 V, Ta = -
20'C to
+ 75'C, unless otherwise
noted)
Item
Input high voltage
RES
Symbol
Min
Max
VIH
Vee - 0.5
2.0
2.2
0.7 Vee
Vee
Vee
Vee
Vee
-0.3
-0.3
-0.3
0.8
0.6
0.3 Vee
TTL interface'
TTL interface 4
CMOS interface'
Input low voltage
TTL interface', RES "Il
TTL interfaces
CMOS interface'
Output high voltage
TTL interface2
VOH
CMOS interface 2
Output low voltage
TTL interface2
VOL
V
V
10H = - 200 pA
10H = -200 pA
0.4
0.8
V
10l = 1.6 rnA
IOl = 200 pA
Input leakage current
All inputs except
I/O common pins 3
III
-2.5
2.5
pA
Three state (off-state)
leakage current
I/O common pins3
iTSl
-10.0
10.0
pA
250
rnA
Current consumption
Notes: 1.
2.
3.
4.
5.
Icc
Teat Conditions
+ 0.3 V
+ 0.3
+ 0.3
+ 0.3
2.4
Vee - 0.8
CMOS interface2
Unit
fooTelK = 25 MHz
Output pins left
disconnected
TTL interface inputs: R, G, B, HSYNC, VSYNC, OISPTMG, ROO-R07, GOO-G07, BOOB07, 00-03, AO!RO/XOOT, RS/AOJ, CS/MSO
CMOS interface inputs: OMO-OM3, DOTE, PMOOO, PM001, A1/YLO-A2/YL2
TTL interface outputs: AO/RO/XOOT, A1/YLO-A3/YL2, 00-03, ROO-R07, GOO~G07,
BOO-B07, MAO-MA 15, MCSO, MCS1, MWE
CMOS interface outputs: CU, CD, RO!LUO-R3/LU3, GO/LOO-G3/L03, BO-B3, M, FLM,
CL1, CL2, CL3, CL4
I/O common pins: AO/RO/XOOT, A1/YLO-A3/YL2, 00-03, ROO-R07, GOO-G07, BOOB07
Inputs except I/O common pins: HSYNC, VSYNC, PMOOO, PM001, RS/AOJ, CS/MSO,
WR/MS1, RES, DOTE, OMO-OM3, LOOTCK, OOTCLK, R, G, B, OISPTMG
TTL interface: WR/MS1, LOOTCK, OOTCLK
TTL interface: WR/MS1
HITACHI
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637
I
HD66840F
DC Characteristics 2 (Vee = 5.0 V ± 5 %, GND = 0 V, Ta = - 20·C to + 75·C, unless otherwise
noted)
Item
Svmbol
Min
Max
Unit
Input high voltage
RES
VIH
TTL interface', RES
CMOS interface'
Vee - 0.5 Vee + 0.3 V
2.0
Vee + 0.3
0.7 Vee
Vee + 0.3
Input low voltage
TTL interface'
CMOS interface'
VIL
-0.3
-0.3
Output high voltage
TTL interface 2
CMOS interface 2
VOH
2.4
Vee - 0.8
Output low voltage
TTL interface 2
CMOS interface 2
VOL
Input leakage current
All inputs except
I/O common pins 3
IlL
Three state (off-state)
leakage current
I/O common pins 3
ITSl
Current consumption
Notes: 1.
2.
3.
0.8
0.3 Vee
Test Conditions
V
V
IOH = - 200 pA
IOH = - 200 pA
0.4
0.8
V
IOL
IOL
-2.5
2.5
Il A
-10.0
10.0
Il A
250
mA
lee
= 1.6 mA
= 200 IlA
fooTeLK = 30 MHz
Output pins left
disconnected
TIL interface inputs: R, G, B, HSYNC, VSYNC, OISPTMG, OOTCLK, LOOTCK, ROO-R07,
GOO-G07, BOO-B07, 00-03, AO/RO/XOOT, RS/AOJ, CS/MSO, WR/MS1
CMOS interface inputs: OMO-OM3, OOTE, PMOOO, PM001, Al/YLO-A2/YL2
TIL interface outputs: AO/RO/XOOT, A1/YLO-A3/YL2, 00-03, ROO-R07, GOO-G07,
BOO-B07, MAO-MA15, MCSO, MCS1. MWECMOS interface outputs: CU, CO, RO/LUO-R3/LU3, GO/LOO-G3/L03, BO-B3, M, FLM,
CL1, CL2, CL3, CL4
I/O common pins: AO/RO/XOOT, A1/YLO-A3/YL2, 00-03, ROO-R07, GOO-G07, BOOB07
Inputs except I/O common pins: HSYNC, VSYNC, PMOOO, PM001, RS/AOJ, CS/MSO,
WR/MS1, RES, OOTE, OMO-OM3, LOOTCK, OOTCLK, R, G, B, OISPTMG
HITACHI
638
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66840F
Video Signal Interface
Symbol
Min
Max
Unit
DOTCLK cycle time
Item
tCYCO
40
1000
ns
Remark
DOTCLK high-level pulse width
twOH
20
ns
DOTCLK low-level pulse width
twOL
20
ns
DOTCLK rise time
tOrl
5
ns
DOTCLK fall time
tOIl
5
ns
R, G, B, setup time
tvos
10
ns
R, G, B, hold time
tvoH
10
ns
DISPTMG setup time
tOTS
10
ns
DISPTMG hold time
tOTH
10
ns
HSYNC setup time
tHSS
10
ns
HSYNC hold time
tHSH
10
ns
Phase shift setup time
tpos
2 tCYCO
ns
Phase shift hold time
tpOH
2 tCYCO
ns
Input signal rise time
tOr2
10
ns
Exc;ept DOTCLK
Input signal fall time
tOl2
10
ns
Except DOTCLK
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
639
HD66840F
,....
tOt.
DOTCLK
~2.0V
-- ;H:
I""
O.8V
tvos
I
tHSH
tWDH
~
DOTC LK
~
tHSS
tHSH
IHSS
Ir-
'\...
-(.OV
O.8V
100
2.0V
O.8V
HSYNC
f\-
1M
tors
tOTH
DISPTMG
....
K
...,1o!;;"2.0V
O.8V
HSYNC
~
1.5V
lVOH
~ ~~:~~
R. G. B
..,if
tWDL
tOTH
lors
...
Ji:""
=-
\
/
lPOH
VSYNC
2 ov
O.8V
- - - - - - - - - - - - - \ ."\..........._ _ _ _ _ _ _ _ __
Figure 29
Video Signal Interface
HITACHI
640
Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
HD66840F
Buffer Memory Interface
Item
Symbol·
Min
Read cycle time
tRC
5 !eYCD - 50
ns
RDO-RD7, GDO-GD7, BDO-BD7
data setup time
tsMD
25
ns
RDO-RD7, GDO-GD7, BDO-BD7
data hold time
tHMD
0
ns
Write cycle time
twc
6 !eYCD - 50
ns
Address setup time
lAs
!eYCD - 30
ns
Address hoid time
twR
!eYCD - 30
ns
Chip select time
tew
4 tCYCD - 40
ns
Write pulse width
twp
4 tCYCD - 40
ns
RDO-RD7, GDO-GD7, BDO-BD7
output setup time
TSMDW
2 !eYCD - 25
ns
RDO-RD7, GDO-GD7, BDO-BD7
output hold time
tHMDW
0
ns
Max
Unit
Note: tCYCD indicates DOTCLK cycle time (min 40 os, max 1000 os).
I
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
641
HD66840F
I-
-
ia:
....1:1
.a
~
!
·c
~
11
II
-~§
I...
i
I
N
-0
m
a:
..
t
III
0
C')
'Q
]
'"
II
i
-
l1li
-0
:B
II:
'"=<
:E
I
~
:E
~
...:
0
C1
I
0
0
~
~ OO(
:::0
C1
...:,..t
a:
I
III
I
OO:!
IilfilHITACHI
642· Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
::c
s=
<>
:!:
:l>-
3
'"<>::l.
.?'
!::;
?-
T2 (= 5teyeD)
::c
s=
<>
:!:
OOTCLK
"
.
r-',
_J
6)
r-,L_-'r
'---'
, r-, r-,
'---'
\"_-1
N
'"r->
MAO-MA15
2.4V"O.SV,.
~
MCSO. MCSl (Read )
2.4V
O.sv
. -J:
MCSO. MCSl (Writ, ,)
0
0
0
T3 (=6teYeD)
r-,
L_J
r-"'\
\._J
r-,
L_...1
\...._-'
r
,
T, (= 5 eyeD)
r-,
\...._J
'--
twe
,K
en
(ij'
iil
J:
"a
(')
~
0
,...
"
~
I"
twp
~AS
0"
-''"C?"
tWR
tew
'\ 2.4V
O.SV
~
c;;'
:::l
~
tAS
MWE
~
tWR
2.4V
O.SV
:l>-
co
tSMDW
""'0 "
~
~
co
ROO-R07. GOO-G07
BOO-B07
(LVIC - Memory)
·~.4V
O.SV
~
:x:
~
o
en
t11
00
co
do
Co)
en
ex)
0
0
a>
""'"
Co)
,tHMDW
~
Figure 31
•
Buffer Memory Interface (RAM Write Timing)
o"%j
HD66840F
LCD Driver Interface (TN-Type LCD Driver)
Item
Symbol
Min
CL2 cycle time
twCL2
166
ns
CL2 high-level pulse width
twCL2H
50
ns
CL2 low-level pulse width
twCL2L
50
ns
CL2 rise time
Max
Unit
tCL2r
30
ns
CL2 fall time
tCL2f
30
ns
CL 1 high-level pulse width
twCLlH
CL 1 rise time
tCLlr
30
ns
CL1 fall time
tcL1f
30
ns
CL1 setup time
tsCLl
500
ns
CL1 hold time
tHCL1
200
ns
FLM hold time
tHF
200
ns
M output delay time
tOM
Data delay time
too
- 20
LDOTCK cycle time
twLOOT
41
Note: All the values are measured at fCL2
=6
200
ns
300
ns
20
ns
ns
MHz.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
HD66840F
LCD Driver Interface (TFT-Type LCD Driver)
Item
Symbol
Min
CL2 cycle time (X drivers on one side)
tTCL2S
CL2 high-level width (X drivers
on one side)
Unit
Remark
160
ns
Figure 34, 35
tTCl2HS
30
ns
CL2 low-level width (X drivers
on one side)
tTCl2LS
30
ns
CL2 cycle time (X drivers on both side)
tTCL20
320
ns
CL2 high-level width (X drivers
on both side)
tTCL2HO
80
ns
CL2 low-level width (X drivers
on both side)
tTCL2l0
80
ns
CL2 rise time
tel2r
30
ns
CL2 fall time
tCl2!
30
ns
CL 1 high-level width
tTCL1H
CL1 rise time
teL1r
30
ns
CL1 fall time
tell!
30
ns
Data delay time
tOOl
-20
20
ns
Data set up time
tlOS
15
ns
Data hold time
tLDH
15
ns
CL 1 setup time
tTSCL1
500
ns
CL1 hold time
tTHCll
200
ns
CL3 delay time
tOCL3
50
Max
ns
200
ns
M delay time
tOM
FLM hold time
tTFH
200
ns
LDOTCK cycle time
twlOOT
40
ns
300
ns
I
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
645
e
~
'"
twcuH tWCI2L
en
en
:J:
~
CU
00
2:
~
~
CD
,Jex .:;~~ __ \..,
RO-R3. GO-G3,
80-83
::l.
~
'1
..... ,
'"
.... ,
!:::;
po.
•
tHCU
tWCL1H
:J:
iii'
n
tsel1
2:
"1J
CLl
~
•
!eLfr
I\)
0
0
0
0. 7Vcc
i>l :I
2.
a
"1J
tHF
FLM
en
Qi.
"1J
teltf
ij
-I
I..
toM
O.7 V cc
0.3 Vee
M
(')
f• :I:
Figure 32
!XI
LCD Driver Interface (TH7Type LCD Driver Interface)
::l.
en
cr
I»
::s
!D
n
l>
Cll
~
0
~
FLM
~
<0
•
MIMCbit-O)
~
~
~
en
0>
I I I 1 I I· I· I 1 1nl 1 1 I 1 1 1 I 1 I ~{I 1 1 I I 1 I I 1
~~
n---,
11
--1
~r--flL.---n-.-J
.~
MIMC bit=l)
cp
0>
c.>
0
0
Figure 33
Clot, FUll and III (Reduced View of Figure 32)
"
~
HD66840F
X drivers on one side
CL2
RO-R3
GO-G3
80-83
X drivers on
both sides
CL2
RO-R3
GO-G3
80-83
trsCL1
tTCL1 H
tTHCl1
0.7 Vee
0.3 Vee
CLl
tellr
tCL1f
tDCL3
CL3
FLM
M
Figure 34
CL1 ______
LCD Driver Interface (TFT-type LCD Driver Interface)
~rlL
I
____________________________________~rlL________
CL3
CL4
~L_ _ _ _ _ _ _ _ _ _...J
f.--'-
j ~',.
L
divided
from CL3
FUM ______________________~rl----------------------~~
M
Figure 35
CLI, CL3, CL4, FLM, M (Reduced view of figure 34 in the horizontal stripe
mode)
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
647
HD66840F
Register Programming, MPU Write
Item
Symbol
Min
RO high-level pulse width
twROH
190
ns
RO low-level pulse width
twROL
190
ns
WE high-level pulse width
twwEH
190
ns
WE low-level pulse width
twwEL
190
ns
CS, RS setup time
!AS
0
ns
CS, RS hold time
tAH
0
ns
ns
ns
00-03 setup time
tosw
100
00-03 hold time
tOHW
0
00-03 output delay time
to DR
00-03 output hold time
tOHR
ns
10
ns
K:
8
o.sv
lAs
twtlDl
J
-'
2.0~J\
O.SV
tAH
I,t
L
tAS
tAH
tWWEH
tWWEl
tDD.
2.0V 1\
O.SV
tDH.
I
tosw
~
2.4V
O.SV
~
tWRDH
I
00-03
Unit
150
2.0~~
RS
Max
2.0V
O.SV
Output
Figure 36
tDHW
Input
lIIIPU Interface
HITACHI
648
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra· Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
HD66840F
Register Programming, ROM Write
Item
Symbol
Min
A cycle time
tcYCA
528
A rise time
tAr
100
ns
A fall time
tAf
100
ns
o ROM data setup time
o ROM data hold time
Note: tCYCA ""
16
Unit
Max
ns
toswo
120
ns
tOHWO
0
ns
tCYCO
tA~ tAf
AO-A3
(LVIC-+ROM)
2.4V)<
X
toswo
00-03
(ROM-+LVIC)
Valid
Valid
Figure 37
~
2.0V
O.8V
Valid
tDHWO
K
ROM Interface
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
------~---- ..........
-
649
HD66840F
PLL Interface
Item
Symbol
Max
Unit
tUI
80
ns
tUr
80
ns
CD fall delay time
tOI
80
ns
CD rise delay time
tOr
80
ns
Max
Unit
CU fall delay time
CU rise delay time
Min
Reset Input
Item
Symbol
RES input pulse width
tRES
Min
JiS
DOTCLK
HSYNC
Figure 38
PLL Interface
RES----------------------~·~ ~~.8-V---------------------Figure 39
Reset Input
HITACHI
650
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD6684.0F
Load Circuits
TTL Load
Pin
Remarks
R
MAO-MA15, MWE, MCSO,MCS1,
RDO-RD7, GDO-GD7, BDO-BD7
2.4 kO
11 kO
40 pF
tr, tf: Not specified
AO/RD/XDOT, A 1 /yLO-A3/YL2
2.4 kO
11 kO
40 pF
tr, tf: Specified
Capacitive Load
Pin
c
Remarks
CL1, CL2, CL3, CL4
40pF
tr, tf: Specified
RO-R3, GO-G3, BO-B3,
FLM CU, CD, M
40pF
tr, tf: Not specified
5.0V
All diodes
= 1S2074®
'M'L Load Circuit
Figure 40
I
0----1...,
.c
r
Figure 41
Capacitive Load Circuit
Refer to application note (No. ACE-S02-011) for detail of this product.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
651
HD66841 F-~----LCD Video Interface Controller II
(LVIC-II)
Description
The HD66841F LCD video interface controller
(LVIC-II) converts standard RGB video signals for
CRT display into LCD data. It enables a CRT
display system to be replaced by an LCD system
without any changes. and it also enables software
originally intended for CRT display to control an
LCD.
Since the LVIC-II can control TFT-type LCDs in
addition to current 1N-type LCDs. it can support
monochrome. 8-level gray-scale. and 8-color
displays. Thanks to a gray-scale palette. any 8
levels can be selected from 13 gray-scale levels.
depending on the LCD panel used.
The LVIC-II also features a programmable screen
size and can control a large-panel LCD of up to 720
x 512 dots.
Features
.' Conversion of RGB video signals used for CRT
display into LCD data:
- Monochrome display data
- 8-level gray-scale data
- 8-color display data
• Selectable LVIC-II control method:
- Pin programming method
- Internal register programming method (either
with MPU or ROM)
• Programmable screen size:
- 640 or 720 dots (80 or 90 characters) wide by
200. 3S0. 400. 480. S12. or S40 dots (lines)
high. using the pin programming method
- 32 to 4048 dots (4 to S06 characters) wide by
4 to 1024 dots (lines) high. using the internal
register programming method
• Double-height display capability
• Generation of display timing signal (DISPTMG)
from horizontal synchronization (HSYNC) and
vertical synchronization (VSYNC) signals
• Internal PLL circuit capable of generating a CRT
display dot clock (DOTCLK) (external charge
pump. low pass filter (LPF). and voltagecontrolled oscillator (VCO) required)
• Control of both 1N-type LCDs and TFT-type
LCDs
• Gray-scale level selection from gray-scale
palette
• Maximum operating frequency: 30MHz
(DOTCLK)
• LCD driver interface: 4-. 8-. or 12-bit (4 bits
each for R. G. and B) parallel data transfer
• Recommended LCD drivers: HD61104
(column). HD6110S (row). HD61106 and
HD66107T (column/row)
• Direct interface with buffer memory (no external
decoder required)
• 1.3-J.U1l CMOS processing
• Single power supply: +SV ± 10%
• Package: l00-pin plastic QFP (FP-lOOA)
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819. (415) 589-8300
HD66841F
Pin Arrangement
RD, AlJIXDOT
A1NLO
A2Nl1
DOTE
PMOD1
PMOOO
LDOTCK
A31Vl2
DO/FO
Voo3
CL4
D1IF1
D2IF2
CL3
D3JF3
Cl2
GND2
MAO
MA1
MA2
Cl1
FlM
M
ROILUO
R11lU1
R2ILU2
R3JLU3
MA3
MA4
MAS
MAS
MA7
MAS
GND6
GOILOO
G11lD1
G2JLD2
G3JLD3
MA9'
MA10
MA11
MA12
GND3
MA13
MA14
MA1S
eo
B1
B2
B3
807
806
80S
MC$O
BD4
MCS1
MWE
Vcc2
I
803
802
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
653
HD66841F
Pin Description
The LVle-II's pins are listed in table 1 and their
functions are described below.
Table 1 Pin Description
Classification
Symbol
Pin Number
Power supply
Vcc1-Vcc3
96,30,76
Pin Name
110
Note{s}
Vcc1 to Vcc3
~~~~----------------~~--~------------------------Ground 1 to Ground 6
GND1-GND6
88,9,23,
37,50,65
Video signal
interface
LCD interface
Buffermemo~
interface
Mode setting
R,G,B
91,92,93
Red, green, and blue serial data
HSYNC
89
Horizontal synchronization
VSYNC
90
Vertical synchronization
DISPTMG
95
Display timing
DOTCLK
94
Dot clock
Ro-R3
69-66
LCD red data 0-3
o
3
LUo-LU3
69-66
LCD upper panel data 0-3
0
4
2
LDo-LD3
64-61
LCD lower panel data 0-3
o
4,5
Bo-B3
60-57
LCD blue data 0-3
3,6
CL1
72
LCD data line select clock
CL2
73
LCD data shift clock
CL3
74
Y-driver shift clock 1
o
o
o
o
CL4
75
Y-driver shift clock 2
o
7
FLM
71
First line marker
M
70
LCD driving signal alternation
o
o
LDOTCK
77
LCD dot clock
7
_M=C==SO~,~M~C~S~1~__2~7~,~2~8________~M~e~m~0~~_c~h~ip~s~e~le~d~0~,~1_________0~__~8~___
-=
MWE
29
Memo~
write enable
0
8
MAo-MA15
10-22, 24-26
Memo~
address 0-15
0
8
RDo-RD7
31-36,38, 39
Memo~
red data 0-7
VO
8
GDo-GD7
40-47
Memo~
green data 0-7
BDo-BD7
48, 49, 51-56
Memo~
blue data 0-7
VO
VO
8, 9
PMODO, PMOD1 78, 79
Program mode 0, 1
DOTE
80
Dot clock edge change
SPS
DMo-DM3
81
Synchronization polarity seled
82-85
Display mode 0-3
MSO, MS1
98,99
Memo~
XDOT
YLo-YL2
2-4
seled 0, 1
8, 9
10, 11
X-dot
10
Y-line0-2
10,12
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Table 1 Pin Description(cont)
Classification
Symbol
Pin Number
Pin Name
Mode setting
ADJ
100
Adjust
10
Fo-F3
5-8
Fine adjust 0-3
10
CS
98
Chip select
10, 11
WR
99
Write
10,11,13
Read
10,13
Register select
10
MPU interface
1m
RS
100
00-03
5-8
·97
Oata0-3
110
ROM interface
00-03
5-8
Oata0-3
PLL interface
~
86
Charge down
o
CU
87
Charge up
o
Notes:
Note(s)
10
14
RES
Ao-M
1-4, 100
Reset
Address 0-4
I/O
o
10
10
Fix G and B pins low if CRT display data is monochrome.
Fix high or low if the display timing signal is generated Internally.
For 8-oolor display modes.
For monochrome or 8-level gray-scale display modes.
Leave disconnected in 4-bitlsingle-screen data transfer modes.
Leave disconnected in monochrome or 8~level gray-scale display modes.
Leave disconnected in TN-type LCO modes.
Leave disconnected if no buffer memory Is used.
Pull up with a resistor of about 20 kn in monochrome display modes.
The LVIC-lIwrites the OR of RGB signals into R-plane RAM, so no RAM is required for the G
and B planes in these modes. (H G- or B-plane RAM Is connected in monochrome display
modes, the LVIC-II writes G or B signals into each RAM. However, this does not affect the
display or the contents of R-plane RAM.)
10. Multiplexed pins.
11. Fix high or low when using the ROM programming method.
12. Fix high or low when usi~he MPU programming method.
13. Do not set pins WR and RO low simultaneously.
14. A reset signal must be input after power-on.
1.
2.
3.
4.
5.
6.
7.
8.
9.
HITACHI
Hitachi America, Ltd. - Hita?hi Plaza - 2000 Sierra Point Pkwy.- Brisbane, CA 94005-1819 - (415) 589-8300
655
HD66841F
Power Supply
FLM: Outputs a first line marker for Y-drivers.
Vccl-Vcc3: Must be connected to a +5V power
supply.
M: Outputs an alternation signal for converting
LCD driving signals to AC.
GNDl-GND6: Must be grounded.
LDOTCK: Inputs LCD dot clock pulses.
CRT Display Interface
Burrer Memory Interface
R, G, B: Input R, G, and B signals for CRT
display.
MCSO, MCSl: Output buffer memory chip select
signals.
HSYNC: Inputs the CRT horizontal synchronization signal.
MWE: Outputs the buffer memory write enable
signal.
VSYNC: Inputs the CRT vertical synchronization
signal.
MAO-MAlS: Output buffer memory addresses.
DISPTMG: Inputs the display timing signal which
indicates the horizontal or vertical display period.
DOTCLK: Inputs dot clock pulses used for CRT
display.
RDO-RD7: Transfer data between R-data buffer
memory and the LVIC-II.
GDO-GD7: Transfer data between G-data buffer
memory and the LVIC-II.
LCD Interface
BDO-BD7: Transfer data between B-data buffer
memory and the LVIC-II.
RO-R3: Output LCD R data
ModeSeUing
LUO-LU3: Output LCD upper panel data.
PMODO, PMODl: Select the. programming
method for the LVIC-II (table 2).
GO-G3: Output LCD G data.
DOTE: Switches data latch timing. The LVIC-II
latches RGB signals at the falling edge of
OOTO..K pulses if the DOTE pin is set high, or at
the rising edge if it is set low.
LDO-LD3: Output LCD lower panel data.
B0-83: Output LCD B data.
CLI: Outputs line select clock pulses for LCD
data.
CL2: Outputs shift clock pulses for LCD data. .
SPS: Selects the polarity of the VSYNC signal.
(The HSYNC signal's polarity is fixed.) The
VSYNC signal is active-high if SPS is set high, or
. active-low if it is set low.
CL3: Outputs line select and shift clock pulses for
LCD data if Y-drivers are positioned on one side of
the LCD screen. Refer to the LCD System
Configuration section for details.
DMO-DM3: Select the display mode (table 8).
CL4: Outputs line select and shift clock pulses for
LCD data if Y-drivers are positioned on both sides
of the LCD screen. Refer to the LCD System
Configuration section for details.
XDOT: Specifies the number of characters
displayed on the LCD screen in the horizontal
direction (called the horizontal displayed
characters). The number is 90 (720 dots) if XOOT
is set high, or 80 (640 dots) if it is set low.
MSO-MSI: Select the buffer memory type (table
3).
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
HD66841F
YLO-YL2: Specify the number of lines displayed
on the LCD screen in the vertical direction (called
the vertical displayed lines) (table 4).
ADJ: Determines whether the FO-F3 pins adjust
the display timing signal or the number of vertical
displayed lines. They pins adjust the display
timing signal if ADJ is set high, or the number of
vertical displayed lines if it is set low.
FO-F3: Adjust the number of vertical displayed
lines (table 5) or the display timing signal. Refer to
the Display Timing Signal Fine Adjustment section
for details.
RS: An MPU inputs the RS signal through this pin
to select the LVIC's internal registers. An MPU
can access data registers (RO-R15) while this
signal is high and the CS signal is low, and can
select the address register (AR) while both this
signal and the CS signal are low.
DO-D3: Transfer LVIC-II internal register data
between an MPU and the LVIC-ll.
RES: Externally resets the LVIC-II.
ROM Interrace
AO-A4: Output external ROM addresses.
MPU Interface
CS: An MPO inputs the CS signal through this pin
to select the LVIC. An MPU can access the LVICII while this signal is low.
WR: An MPU inputs the WR signal through this
pin to write data into the LVIC-II's internal
registers. An MPU can write data while this signal
is low.
DO-D3: Input external ROM data to the LVIC-II's
internal registers.
PLL Circuit Interrace
CD: Outputs charge-down signals to an external
charge pump.
CU: Outputs charge-up signals to an external
charge pump.
RD: An MPU inputs the RD signal through this pin
to read data from the LVIC-II's internal registers.
An MPU can read data while this signal is low.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
657
HD66841F
Table 2 Programming Method Selection
PMOD1
PMODO Programming Method
0
0
Pin programming
0
Internal register
programming
1
Inhibited (Note)
0
1
Table 4 Number of Vertical Displayed Lines
MPU
ROM
Note: This combination is for test mode: it disables
display.
YL1
YLO
0
0
0
0
0
0
1
0
400
1
0
0
512
1
0
0
540
Inhibited
MSO
MemorY"FYpe
0
0
No memory
0
1
8-kbytes memory
0
32-kbytes memory
64-kbytes memory
200
350
0
480
Table 3 Memory Type Selection
MS1
Number of Vertical
Displayed Lines
YL2
(Note)
Note: 480 lines are displayed, but they are practically indistinguishable.
Table 5 Fine Adjustment of Vertical Displayed
Lines
F3
F2
F1
FO
Number of Adjusted Lines
o
o
o
0
0
0
±o
0
0
0
1
0
+2
o
+14
1
+15
+1
HITACHI
658
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
=
i
I
r!
~
==
~
CU
:::L
jJ
.... E~nter, rI
I
g
phase
IComparator)
==
i•
•tI
SPS
HSVNC
I\:)
g
.1 DlSPTMG
.1 generator
VSYNC
DISPTMG
rn
~
c;;"
J:
-
generator
;5
~~
·
ii-
aJ
~
~
~
~
.!..
~
co
•
~
~
(TO
!p
~
0>
(TO
co
t
DOTClK
DOTE
R
(horizontal, II")
vertical counter
eG:
Y/
G
B
Vee
H
+
Write address
counter
-p:.
I
GND 6'
F>
F>
I Y
r-
F
"1-~8
V
RDo-RD7
GDO-GD7
BDo-BD7
IF
~
I
I
I,
~
...
MPUIROM
2
'f
interface
'=
,Lleis"
___ ..IL ___ ..II
PMODO, PMOD1
1'lJ.
limi
sig:::3
genera1Dr
Synchronizer
F=F:> cw~tch
I ::;
I
DMo-DM3
RES
~
~
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[T7 M
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~tch
ar-
cuit
cuit
'"'---
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I
I
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:
I
1..-------------.1
generator
~.
IIL.
Ei
--..
141~
rJ'
LCD
inter-
lace
RO-R3IL.UO-LU3
~GO-G3ILDO-lD3
k~
T~ BO-B3
-...
~I- 13
'V.., 'V"
MCSO
MCS1
MA13-MA15
MWE
3
I
----- . -. --, ~~scaJe
fij k
Fbrr--
I
,~ 6
~4
',Displayl
'
I'mode I n
' pallete I'decod- '
,I regIS""
I LCD
I aer
I
coooter
Data
I
I
~
/I
r----,,----.,
~
f
RS, CS, WR
8-1eve1
IMCS,MWE
I
generator
Ie:::=II:'"
}1
Read address
Address multiplexer
n
1
~
3
Read counter If)
(horizontal,
vertical counter
I
~
CRT
rI
Write counter
T,,"~~
~" d
00-03
~5
DOTCLI<
?t•
-C
CD
t t
CD
~
Ao-M
MAo-MA12
::x:
o
0')
0')
0)
~
~
"z:I
HD66841F
Registers
The LVle-II's registers are listed in table 6 and the
bit assignments within the registers are shown in
figure 1.
Table 6 Register List
Reg. Address
CS RS PS1 3
2 1 0
Reg.
No. Register Name
0
AR
Address register
W
RO
Control register 1
RIW
R1
Control register 2
RIW
R2
Vertical displayed lines
register (middle-order)
lines
Nvd
RIW
4
R3
Vertical displayed lines
register (low-order)
lines
Nvd
RIW
4
R4
Vertical displayed lines
register (high-order)!
Cl3 period register
(high-order)
lines!
Chars.
Nvd!
Npc
RIW
4,5,6
R5
Cl3 period register
(Iow-order)
Chars.
Npc
RIW
4,5,6
R6
Horizontal displayed
characters register
(high-order)
Chars.
Nhd
RIW
6
R7
Horizontal displayed
characters register
(Iow-order)
Chars.
Nhd
RIW
6
RS
Cl3 pulse width register Chars.
Npw
RIW
6
R9
Fine adjust register
Nda
RIW
7
NpLL
RIW
S
NpLL
RIW
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Program
Unit
Dots
R10 Pll frequency-division
ratio register (high-order)
Specified
Readl
Value Symbol Wrlte2 Note(s)
3
R11
Pll frequency-division
ratio register (/ow-order)
R12
Vertical backporch
register (high-order)
lines
Ncvbp
RIW
4, 9
R13
Vertical backporch
register (low-order)
lines
Ncvbp
RIW
4,9
R14
Horizontal backporch
register (high-order)
Dots
Nchbp
RIW
4, 9
R15
Horizontal backporch
register (low-order)
Dots
Nchbp
RIW
4,9
HITACHI
660
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66841F
Table 6 Register List (cont)
Reg.
CS RS PS1 3 2
1
Add~ess
1 0
0
0
0
0
0
0
1
0
0
0
0
Reg.
No. Register Name
P1
Black palette register
0
P2
Blue palette register
1
P3
Red palette register
0
0
0
0
P4
Magenta palette register
0
0
0
1
PS
Green palette register
0
0
1
0
P6
Cyan palette register
0
0
0
0
0
0
0
0
0
1
P7
Yellow palette register
P8
White palette register
Program Specified
Readl
,Unit
Value Symbol Wrlte 2
Note(s)
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
Reserved
Reserved
0
Notes:
1. Corresponds to bit 2 of control register 1 (RO)
2. W indicates that the register can only be written to; RIW indicates that the register can both be
read from and written to.
3. Attempting to read data from this register when RS • 0 drives the bus to high-impedance state;
output data becomes undefined.
4. Write (the specified value - 1) into this register.
5. Valid only in 8-color display modes with horizontal stripes.
6. One character consists of eight horizontal dots.
7. Valid only if the display timing signal is supplied extemally.
8. Valid only if the dot clock signal is generated intemally.
9. Valid only if the display timing signal is generated intemally.
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661
HD66841F
Reg.
PS1 3 2 1 0
,1 I- I.~. 10 1o 11 1- o 0 0 0
o 11 10 0 0 0 1
o 11 !o o 0 1 0
o 11 :0 o 0 1 1
o 11 '0 o 1 o 0
o 11 '0 o 1 o 1
o 11 0 01 j 0
o 11 0 o 1 1 1
o 11 0 1 0 0 0
o 11 0 1 o 0 1
o 11 0 1 o 1 0
01
0
1 o 1 1
01
0
1 1 o 0
01
0
1 1 o .1
o 1 0 1 1 1 0
01
0
1 1 1 1
01
1 10 0 0 1
o 1 1 o 0 1 0
01
1
o 0 1 1
0 1 o 0
10 1 11
0 1 o 1
10 1 11
0 1 1 0
10 1 11
o 1 1 1
10 1 11
1 000
10 1 11
1
1 o 0 1
10
11
i
i
Ii
Ii
m RS
0
1
---- - --
1
Notes: 1.
2.
3.
4.
5.
1
1
1
1
Reg.
No; 13
Data Bits
12
-
11
10
_2
AR
RO OIZ PS
OSP DCK
R1
MC DON MS1 MSO
R2
R3
R4
R5
R63
R7
RS
R9
Rl0
Rl1
R12
£!1:3
R14
R15
P1 4 0
P24 0
P3 4 0
P44 0
P54 0
P64 1
P74 1
PS4 1
+- Address register
+- Control register 1
+- Control register 2
+- Vertical displayed lines register
+- CL3 period register
+- Horizontal displayed characters
register
+- Cl3 pulse width register
+- Fine adjust register
+- PLL frequency-division ratio
register
+- Vertical backporch register
+- Horizontal backporch register
10
10
11
11
11
:0
10
11
10
11
11
'0
10
10
11
10
11
10
'0
0
l1
'0
10
lQ..
_5
+- Black palette register
+- Blue palette register
+- Red palette register
+- Magenta palette register
+- Green palette register
+- Cyan palette register
+- Yellow palette.register
+- White palette register
+- Reserved registers
-
Corresponds to bit 2 of control register 1 (RO).
Invalid bits. Attempting to read data from these bits returns undefined data.
The most significant bit is invalid in dual-screen configuration modes.
Bit values shown are default values at reset.
Reserved bits. Any attempt to write data into the register is invalid, although it has no affect
on LSI operations. Any attempt to read data from the register returns undefined data.
Figure 1 Register Bit Assignment
HITACHI
662
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005·1819· (415) 589-8300
HD66841F
System Description
cricuit from the horizontal synchronization signal
(HSYNC). The DOTCLK signal frequency is
specified by the PLL frequency-division ratio
register (RlO, Rll).
Figure 2 is a block diagram of a system in which
the LVIC-IT is used outside a personal computer.
The LYIC-II converts the RGB serial data sent
from the personal computer into parallel data and
temporarily writes it to the buffer memory. It then
reads out the data in order and outputs it to LCD
drivers to drive the LCD. In this case, the CRT
display dot clock (DOTCLK), which is a latch
clock for serial data, is generated by the PLL
Dot CIOn
The system can be configured without a YCO and
LPF if the DOTCLK signal is supplied externally,
and it can be configured without an MPU if the
LVIC-II is controlled by the pin programming
method.
II
vco
LPF
CU I I C D
Personal
computer
RGB serial data
-.
HSYNC
MPU
~
/
LVIC-II
VSYNC
~
1-'
memory
I
lh
LCD
t
7
Simultaneous display
possible
1
G
VCO: Voltage-controlled oscillator
LPF: Low-pass filter
Figure 2 System Block Diagram (with MPU programming method
and DOTC~K generated internally)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
663
HD66841F
Functional Description
Pin Programming Method: The LVIC-Irs modesetting pins control functions.
Programming Method
One of two methods of controlling LVIC-II
functions can be selected by setting pins PMODO
and PMODI. Control by pins is called the pin
programming method and control by internal
registers is called the internal register programming
method. The internal register programming
method can be further divided into the MPU
programming method and the ROM programming
method; an MPU is used to write data into internal
registers in the MPU programming method and
ROM is used to write data into internal registers in
the ROM programming method.
Internal Register Programming Method: An
MPU or ROM is used to write data into the LYlCIrs internal registers to control functions. Figure 3
shows the connection of either an MPU or ROM to
the LVIC-II. Although figure 3 (1) shows an
example of the use of a 4-bit microprocessor, the
LYlC-IT can alSo be connected directly to the host
MPU bus since the LYlC-1I MPU bus is compatible
with the 4-MHz bus of SO-series microcomputers.
ROM
4·bitMPU
BO
B1
B2
B3
1\
RS
WR
RO
, 7
, 1-
00-D3
00-D3
..~
/10
~5
AO-A4
LVle-1I
LVIC-II
(1) Connection of MPU to LVIC-II
4
...H'4
;k4
CS
AO-A4
00-03
AO-A3
(2) Connection of ROM to LVIC-II
Figure 3 Connection of MPU or ROM to LVIC-n
HITACHI
664
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Screen Size
Screen size can be programmed either by pins or
internal registers.
In the pin programming method, either 640 dots or
720 dots (80 characters or 90 characters) can be
selected with the XDOT pin as the number of
horizontal displayed characters, and either 200,
350,400, 480, 512, or 540 lines can be selected
with the YL2-YLO pins as the number of vertical
displayed lines. The number of vertical displayed
lines can be adjusted by from +0 to +15 lines with
the ADI and F3-FO pins.
In the internal register programming method, any
even number of characters from 4 to 506 (from 32
to 4048 dots) can be selected with the horizontal
displayed characters register (R6, R7), and any
even number of lines from 4 to 1028 can be
selected with the vertical displayed lines register
(R2, R3, and the high-order two bits of R4).
However, note that an odd number of lines can also
be selected if the screen configuration is singlescreen and Y-drivers (scan drivers) are positioned
on one side of the LCD screen.
The relationship between the LCD screen and the
pins and internal registers cO!ltrolling screen size is
shown in figure 4.
Number of horizontal displayed characters
Pin: XDOT
Register: Horizontal displayed characters
register (R6, R7)
T
Number of vertical displayed
LCD screen
L...-_ _ _ _ _ _ _ _ _ _ _ _ _- - - '
lines
Pins: YL2-YLO, ADJ, F3-FO
Register: Vertical displayed
lines register
(R2, R3, high-order 2
bits of R4)
1
Figure 4 Relationship between LCD Screen and Pins and Internal Registers
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665
'HD66841F'
Memory Selection
8-, 32-, or 64-kbytes SRAMs can be selected as
buffer memory for the LVIC-II. Since the LVIC-ll
has a chip select circuit for memory, no ,external
decoder is. required. The memory type can be
selected with the Ms 1 and MSO pins or the MS 1
and MSO bits of control register 2 (RI). Memory
types and corresponding pin address assignments
are listed in table 7.
The memory capacity required depends on screen
size and can be obtained from the following
equation:
,Memory capacity (bytes) =Nhd x Nvd
For example, a screen of 640 x 200 dots requires a
16-kbytes memory capacity since 80 characters x
200 lines is 16 kbytes. Consequently, each plane
requires two HM6264s (8-kbytes memories) in 8level gray-scale display modes. The ~ pin
must be connected to the ~ pin of one of the
memory chips in each plane. and the ~ pin
must be connected to the CS" pin of the remaining
memory chip in each plane (figure S (a».
. A screen of 640 x 400 dots requires a 32-kbytes
(256-kbit) memory capacity, so each plane requires
an HM622S6, which is a 32-kbytes memory. In
this case, the MCSO pin must be connected to the
pin of each memory chip. (figure 5 (b».
a-
Nhd: Number of horizontal displayed characters
(where one character consists of 8 horizontal
dots)
Nvd:
Number of vertical displayed lines
Table 7 Memories and Pin Address Assignments
Pins or Bits
MS1
MSO
0
0
' Address
Address Pins
Chip Select Pins
0
Memory
No memory (Note)
1
8-kbyte
MAo-MA12
~
$OOO0-$1FFF
MCS1
$2000-$3FFF
MA13
$4000-$5FFF
MA14
$6000-$7FFF
MA15
$800o-$9FFF
~
$OOOOo-$07FFF
~
$08000-$0FFFF
MA15
$10000-$17FFF
~
$OOOOo-$OFFFF
MCS1
$10000-$1FFFF
0
32-kbyte
64-kbyte
MAo-MA14
MAo-MA15
Assignment
Note: There are some limitations if no memory is used. Refer to the User Notes section for details.
HITACHI
666
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
640 x 200 dots
/
cs
/
f
/
640 x 400 dots
B
CS
G
R
CS
Il-
HM6264
cs
~
I-
HM6264
(a) 16-kbytes Memory Configuration
(b) 32-kbytes Memory Configuration
Figure 5 Screen Size and Memory Configuration
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
667
HD66841F
Display Modes
The LVIC-n supports 16 display modes, depending
on the states of the DM3-DMO pins. The display
mode controls display color, type of LCD data
output, positions of LCD drivers for the LCD
screen, arrangement of color data (type of stripes),
and method of M signal output (type of alternation
signal). Display modes are listed in table 8.
Table 8 Display Mode List
Mode
Pins
Display
No.
DM3 DM2 DM1 DMO Color
0
0
0
2
0
0
0
31
0
0
4
0
0
51
0
0
6
0
0
7
0
8
0
91
1
0
Monochrome
Data Transfer
Type
4-bit
. Dual
One side
Alternation
Every frame
One side
Single
0
Both sides
8-b1t
One side
0
1
Both sides
8-level
4-bit
grayscale
Dual
One side
Single
0
8-bit
0
0
101
0
0
111
0
121
0
1
8-oo1or
12-b1t
Single
(4 bits each
for R, G, and B)
141
0
Onseside
Vertical
Every line
Both sides
Both sides One side
Both sides
0
One side
0
Both sides 'One side
One side
~th
16
Dual
1.
2.
3.
4.
One side
1
0
151
0
0
131
Notes:
Screen LCD Driver Positions
ConDg. Xodrlver! V-Driver! Stripe'
One side
Horizontal
sides
Vertical
Every frame
For TFT-type LCDs.
Data output driver.
Scan driver.
Refer to the 8-coIor Display section.
HITACHI
668
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Display Color
The LVIC-II converts the ROB color data nonnally
used for CRT display into monochrome, 8-level
gray-scale, or 8-color display data.
Monochrome Display (Modes 1 to 5): The LVICII displays two colors: black (display on) and white
(display oft). As shown in table 9, the CRT display
ROB data is ORed to detennine display on/off.
8-Level Gray Scale Display (Modes 6 to 8): The
LVIC-II thins out data on certain lines or dots to
provide an 8-level gray-scale display based on CRT
display color (luminosity). The relationship
between CRT display color (luminosity) and LCD
gray scale (contrast) is shown in table 10.
This relationship corresponds to the default values
in palette registers; the correspondence between
color and gray scale can be changed by writing
data into palette registers.
8-Color Display (Modes 9 to 16): The LVIC-II
displays 8 colors through red (R), green (0), and
blue (B) filters placed on liquid-crystal cells. The
eight colors are the same as those provided by a
CRT display. As shown in figure 6, 8-color display
has two stripe modes: horizontal stripe mode in
which the LVIC-II arranges ROB data horizontally
for horizontal filters and vertical stripe mode in
which it arranges ROB data vertically for vertical
filters. Three cells express one dot in both modes.
Table 9 Monochrome Display
Table 10 8-Level Gray.Scaie Display
CRT Display Data
R
G
o
o
o
o
B
CRT
Color
Luminosity
LCD
Gray Scale
Contrast
White
High
Black
Strong
Low
White
Weak
o
Yellow
o
Green
Cyan
o
o
o
o
o
o
Magenta
Red
Blue
Black
HITACHI
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669
HD66841F
X·drivers
1 dot
RR R
GG G
B BB
-r--.
r--
~
l
>
'I' ,,
I : ,
, ,
, , ,
, , ,
, , ,
,,
,
,,,
,
I
I
X·drivers
I
1dot RGB
Rlilter
G filter
Bfilter
R
G
B
..
-r---~
~
>
. .. .
.
...•....•........
R~ B···············
t!t
LBlilter
LGfilter
RAter
Vertical Strlpea
Horizontal Strlpea
Figure 6 Stripe Modes in a·Color Display
HITACHI
670
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 940Q5·1819· (415).589-8300
HD66841F
LCD System Configuration
The LVIC-II supports the following LCD system
configurations:
• 'JYpes of LCD data output:
- Data transfer: 4-bit, 8-bit, or 12-bit (4 bits
each for R, G, and B)
- Screen configuration: Single or dual
Data
4-bits
r-
Ii
4-,8-, 12-bits
Data
~ ~ ~ ~
f- -lCDlu
I
System configurations for different modes are
shown in figure 7, and configurations of X- and Ydrivers positioned on both sides of an LCD screen
are shown in figure 8.
I
Upper panel X-driver
J
• LCD driver positions around LCD screen:
- X-drivers: On one side or on both sides
- Y-drivers: On one side or on both sides
I
I
I an~
I
Pljf
X-driver
r-..
Ii
-{-T-l-t--{--
~ f- -lCDI~~~ _ ..
~
>
-
......
1 1 1 'I 1
t t f f t
LCDpanel -
..
Lower panel X-drlver
Data
4-bits
System configuration for mode 1 and mode 6
(4-blt data transfer, dual acreen, X-drlver and
Y-drlver each on one side) Note
Data
4-, 8-, 12-b1ts
X-driver
Data
r--
r-
!I!
ioJ
-
"C
LCD panel
12-bits
Upper X-driver
r--
i
~
~
System conflgureatlon for modes, 2, 4, 7, 8, 9,
and 13 (4-, 8-, or 12-blt data transfer, single
acreen, X-driver and Y-drlver each on one side) .
~
!I!
~
"C
LCDP~eI
-
..
~
1:
Q
if
"'-
"'-
Lower X-driver
Data
12-bits
System conflguraaton fo rmode. 3, 5, 10,
and 14 (4-, 8-, or 12-blt data transfer, .Ingle
acreen, X-driver on one side and Y-drlver on
both sides)
System conflgureatlon for mode 11 and mode
15 (12-blt data transfer, single acreen, X-edrlver
on both sides and Y-drlver on one side)
Note: Since the LCD upper panel and lower panel are each regarded as
one screen, the X-drivers are considered to be positioned on one
side, not on both sides.
Figure 7 System Configurations by Mode
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
671
HD66841F
Data
12-blt
Upper X-driver
r--
~
l&
.f;
~
.1
I
LCD panel
-
Iii
~>-
...
1:
i...J
.21
a:
'--
Data
'--
Lower X-driver
12-blt
I
System configuration for mode 12 (12-bH
data transfer, single screen, X-drlver
and V-driver each on both sides)
System configuration for mode 16 (12-blt
data transfer, dual screen, X-drlver and
V-drlver each on one slde)Not.
Note: Since the LCD upper panel and lower panel are each regarded as
one screen, the X-drivers are considered to be positioned on one
side, not on both sides.
Figure 7 System Configurations by Mode (cont)
Upper X-driver
-
Data output
lines
~r+
~ ,......
>-
f4-
2nd line
3rdllne
3
'--~
-
1st line
~
4th line
5th line
~
/
~
>-
i
-
/
"-Signal output lines
Lower X-driver
(1) X-drivers set on both sides
(2) V-drlvers set on both sides
Data output lines run alternately
from upper and lower X-drivers,
increasing the pitch of the lines to twice
that for X-drivers positioned on one side.
Line select signal output lines run
alternately from right and left Y-drivers,
increasing the pitch of the lines to twice
that for V-drivers positioned on one side.
Figure 8
x- and V-Drivers Set OD Both Sides
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HD66841F
LDOTCK Frequency Calculation
Display Timing Signal Generation
The frequency fL of the LCD dot clock (LOOTCK)
can be obtained from the following equation:
CRT display data is divided into display period
data and rettace period data, so the LVIC-II needs a
signal indicating whether the CRT display data
that has just been transferred is display period data
or noL This signal is called the display timing
signal.
fL= (Nhd+ 6)x8xNvdxfp
Nbd: Number of horizontal displayed characters
on LCD =(number of horizontal displayed
dots on LCD) x 1/8
Nvd: Number of vertical displayed lines on LCD
fp:
Frame frequency (FLM frequency)
The LVIC-IT can generate the display timing signal
from the HSYNC and VSYNC signals. The
relationships between HSYNC, VSYNC, the
display timing signal (DISPTMG). and display data
are shown in figure 9. Y lines and X dots in the
figure are specified by the vertical backporch
register (R12. R13) and the horizontal backporch
register (R14. RI5), respectively.
In this case, fL must satisfy the following
relationships, where fD is the frequency of the dot
clock for CRT display (OOTCLK):
fL < fD x 15/16 or
fL =fD (the phase of LOOTCK must be opposite to
that of OOTCLK. in this case)
n~
VSYNC
HSYNC
_____________________________
1+----1
Y lines (. Vertical backporch)
--II
n
n....___
~
X dots (. Horizontal backporch)
DISPTMG _ _ _~I
I.. Display period
I
I
~..Retrace.1period
II
:::X,:::.::
(. No. of horizontal
displayed characters)
Display
data
_XX:X:X:::::::X,
:::X,::::::::::X,.,4
..,...
......4
Valid
Invalid
Valid
~
Invalid
Valid
Figure 9 Relationships between HSYNC, VSYNC, DISPTMG, and Display Data
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._------_.-
-
_..... _-_._-
673
HD66841F
Dot Clock Generation
The dot clock, which is a data latch clock, is not a
standard video signal, so it is not usually output
from the CRT display plug. Therefore, the LYICII must generate it. The LYIC-II has a
programmable counter and a phase comparator
which are parts of a phase-locked loop (PLL)
circuit, and it can generate the dot clock from the
HSYNC signal if a charge pump, a low-pass filter
(LPF), and a voltage-controlled oscillator (yCO)
are externally attached.
A block diagram of the PLL circuit is shown in
figure 10. A PLL circuit is a feedback controller
that generates a clock whose frequency and phase
are the same as those of a basic clock. The basic
clock is the HSYNC signal in this case.
At power-on, the YCO outputs to the programmable counter a signal whose frequency is
determined by the voltage at that time. The counter
divides the frequency of the signal according to the
value in the PLL frequency-division ratio register
(RIO, Rll), and outputs it to the phase comparator.
This is the frequency-divided clock.
The comparator compares the edges of the clock
the HSYNC signal pulses and outputs
the CU or CD signal to the charge pump and LPF
according to the result. The comparator outputs the
CU signal if the frequency of the clock is lower
than that of the HSYNC signal or if the phase of
the clock is behind that of the HSYNC signal;
otherwise it outputs the CD signal. The charge
pump and LPF~plL.8 voltage to the YCO
according to the CU or CD signal.
pul~and
This operation is repeated until the phase and
frequency of the frequency-divided clock match
those of the HSYNC signal, making it a stable dot
clock.
!
HSYNC
CU
Phase
comparator
Inside LVIC
CD
Charge pump
LPF
Frequencydivided clock
Value written in
PLL frequency-division ratio
register (R1 0, R11)
Q
Programmable
counter
VCO
Timing clock generator
DOTCLK
Figure 10 PLL Circuit Block Diagram
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HD66841F
Gray-Scale Palette
The HD66841F thins out LCD data on certain dots
or lines of an LCD panel every frame, changing
integral voltages applied to Iiquid-crystal cells, to
generate intermediate levels of luminosities.
Consequently, the difference in depth between
adjacent gray-scale shades may not be uniform in
some cases since voltage-transmittance
characteristics vary with different panels. To allow
for this, the HD66841F is designed to generate 13
gray-scale levels and provide palette registers that
assign desired levels to certain of the eight CRT
display colors.
The relationships between gray scales and
corresponding effective applied voltages are shown
in figure 11 (a). Each gray scale is displayed
according to the characteristics of its effective
applied voltage and the optical transmittance of the
Using the palette registers to
panel (figure 11
select any 8 out of 13 levels of applied voltages
enables an optimal gray-scale display conforming
to the characteristics of the LCD panel. The palette
registers can also be used to provide 4-level grayscale display and reverse display.
(b».
Table 11 Default Values of Palette Registers
Register
No.
P1
P2
P3
P4
P5
P6
P7
CRT Dls~lal Data
R
G
B
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
P8
Register Name
Black palette
Default Value
0
0
0
0
Blue palette
Red palette
Magenta palette
Green palette
0
0
0
0
1
0
0
0
1
0
1
0
Cyan palette
Yellow palette
0
0
0
1
0
0
1
White palette
1
0
0
•
•
•
r-------
-----=-r__
• I
I
I
I
•
3
5
7
9
11
13
Transmittance
(b)
Gray-scale number
(a)
Figure 11 Relationships between Gray Scale, Transmittance, and Effective App6ed Voltage
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675
HD66841F
Pin Programming Method
address $0010 (pS bit) before writing palette
register values to addresses $0011-$0018.
The paleue registers cannot be used in the pin
programming method.
MPU Programming Method
To change the contents of palette registers in the
MPU programming method. set bit 2 (the PS bit) of
control register 1 (RO). to 1. Since data registers
(R1-R1S) cannot be accessed while this bit is 1. set
in to 0 before accessing the data registers again.
However. note that control register I (RO) can be
accessed regardless of the setting of the PS bit if $0
is set in the address register (AR).
ROM Programming Method
In the ROM programming method. the HD6684IF
accesses ROM sequentially from address $()()()() to
$00 IF. In this case, write 0 to bit 2 of address
$()()()() (pS bit) before writing data register values
to addresses $OOOI-$OOOF, and write I to bit 2 of
/
Gray scale 1 (1 dot)
DIZ Function
The HD66841F thins out data on certain lines or
dots every frame to enable gray-scale display. If a
checker-board pattern consisting of alternately
arranged gray scales of different levels (figure 12)
is displayed by a simple dot-basis gray-scale
display control method, the display might
sometimes seem to "flow" horizontally, depending
on the gray"scale and LCD panel characteristics.
The HD66841F automatically checks for such a
checker-board section and changes the gray-scale
display control method of dot-based data thinning
to that of frame-based data thinning, to reduce
display flow. Setting bit 3 (DIZ) of control register
1 (RO) to 1 enables this function. In frame-based
data thinning, however, flickering might appear
with some LCD panels; in that case, select the
control method that generates the better display.
Gray scale 2 (1 dot)
Figure 12 Checker-Board Display.
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HD66841F
Double-Height Display
The LVIC-II provides double-height display which
doubles the vertical size of characters and pictures
(figure 13).
1. Halve the LCD dot clock (LOOTCK) frequency
calculated from the number of vertical displayed
lines of the LCD pane1.
In the 1N-type LCD modes (display modes I, 2, 4,
and 6-8), the CL3 signal period is half as long as
the CLI signal period, as shown in figure 14.
Consequently, using the CL3 signal instead of the
CLI signal (figure 15) as a line shift clock enables
two lines to be selected while X-drivers (data
output drivers) are outputting identical data, thus
realizing double-height display. However, it should
be noted that this display requires the following
procedure since the LVIC-II displays twice as
many lines as specified by pins or internal
registers:
2. Specify half the number of vertical displayed
lines of the LCD panel as the number of vertical
displayed lines. (For instance, if the number of
vertical displayed lines of the LCD panel is 400,
specify 200 with the YL2-YLO pins or the
vertical displayed lines register.)
,,;
I
I
r::':'I • •
~
This function is available only in the 1N-type LCD
modes; it is disabled in the TFf-type LCD modes.
~
.••
....
,.,
~
••
•• ••
•• ••
•• •••••
•••••
••• •••
••• •••
••
••••••••••
• •
Normal display
Double-height display
Figure 13 Double-Height Display Example
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677
HD66841F
CL1
--.r.,\
CL.3
~
r
I),
X-driver
/
J
output
r
r
r-
r-
)
r)
\.
Y-driver
(If connected as
shown in figure 15)
\'
Figure 14 Relationship between CLl and CL3 in Modes 1,1,4, 6, 7, and 8
4 (or 8) bits
LDO-LD3,LUO-LU3
,
I
CL1
~
CL2
M
CL3
FLM
M
-
eI
X-drive1'8
(Data output drivers)
--.
CD·c
.~ "0
~!
LCD panel
--.
Figure 15 Connection for Double-Height Display
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HD66841F
Display Timing Signal Fine Adjustment
If the display timing signal is supplied extemally, a
phase shift between CRT data and the display
timing signal may appear. This is because each
signal has its own specific lag. The LVIC-ll can
adjust the display timing signal according to pins
FO-F3 or the fme adjust register (R9) to correct the
phase shifL
The relationships between pins F3-PO, data bits 3
to 0 of the fme adjust register, and the resultant fme
adjustments are shown in table 12. The polarity of
the number of dots adjusted is given by - (minus)
indicating advancing the phase of the display
timing signal or + (Plus) indicating delaying it. Pin
F3 or data bit 3 of R9 selects the polarity. The
adjustment reference point is the display start
position.
Examples of adjusting the display timing signal are
shown in figure 16. Since the signal is two dots
ahead of the display start position in case (1), F3.
F2, Fl, and PO or data bits 3, 2, 1. and 0 of R9
should be set to (I, 0, 1,0) to delay the signal by
two dots. Conversely, since the signal is two dots
behind the display start position in case (2). they
should be set to (0, 0, I, 0) to advance the signal by
two dots. If there is no need to adjust the signal. a
setting of either (0, 0, 0, 0) or (I, 0, 0, 0) will do.
Table 12 Pius, Data Bits of R9, and Fine Adjustment
Pin
F3
R9Blt 3
0
F2
2
F1
FO
1
0
0
0
0
0
0
o
o
Number of Dots
Adjusted
0
-1
o
~
1
-7
0
0
0
0
1
+1
o
+6
1
+7
I
Note: To use pins to adjust the display timing signal.
set the ADJ pin to 1.
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679
HD66841F
,
:..... Display start position
,
I
___x_~x:=
~~x~~~~~x~~x
CRT data
:..
,
~
Two dots advanced
I
DISPTMG
before adjustment
~
Display timing adjustment
(F3, F2, F1, FO) or
(Data bits 3, 2, 1, 0 of R9)
• (1,0, 1,0)
DISPTMG
after adjustment
~------------------------
(1) Delaying DISPTMG
I
,,
: . - Display start position
CRT data
:::x
X~__~X~__~~~I
,
,
__~X~__~~~__~
.'
,
_________________________~T_WO~d.ots
___
de_l_ay_ed~~---------------DISPTMG
.
before adjustment
Display timing adjustment
(F3, F2, F1, FO) or
/
(Data bits 3, 2, 1, 0 of R9)
• (0, 0,1,0)
DlSPTMG
after adjustment
(2) Advancing DISPTMG
Figure 16 Adjustment of Display Timing Signal
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HD66841F
Internal Registers
Control register 1 (figure 18) is composed of four
bits whose functions are described below.
The HD66841F has an address register (AR), 16
data registers (RO-RI5), and 8 palette registers
(PI-PS). Write the address of a register to be used
into the address register (AR), but only after setting
the PS bit of control register 1 (RO) to 0 for a data
register or 1 for a palette register. The MPU
transfers data to the register corresponding to the
written address.
• DIZ bit: Changes the method used to control the
gray-scale display of a checker-board pattern.
- DIZ = 0: Data thinned out on a dot basis every
frame
- DIZ = 1: Data thinned out on a frame basis
every frame
Registers are valid only in the internal register
programming method, they are invalid (don't care)
in the pin programming method.
• PS bit: Specifies access to data registers
(RO-RI5) or palette registers (PI-P8).
In MPU programming mode:
- PS = 0: Specifies access to data registers
(RO-RI5) only.
- PS = 1: Specifies access to palette registers
(PI-P8) only.
The 4-bit address register (figure 17) is used to
select one of the 16 data registers or 8 palette
registers. It can select any data register or palette
register according to the register address written to
it by the MPU. The addres register itself is
selected if the RS signal is set low.
Address Register (AR)
,
AR
/
Data bit
3
I
I
2
1
I
0
Value
'-
Register address
Figure 17 Address Register
Control Register 1 (RO)
,
RO
/
Data bit
Function
3
2
1
0
DIl
PS
DSP
DCK
Figure 18 Control Register 1
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681
HD66841F
This register can be always accessed regardless of
the PS bit setting, but it cannot be read after the PS
bit is set to 1. Read it when PS is O.
In ROM programming mode: Data for LVIC-II
internal data registers can be written into $000 1 to
$OOOF when bit 2 (the PS bit) of $0000 is set to O.
Data to be set into palette registers can be written
into $0011 to $0018 when the PS bit of $0010 is set
to 1 (figure 19 (a».
(ROM
addresses
AD-A4)
• DSPbit
- DSP = 1: The DISPTMG signal is generated
internally.
- DSP = 0: The DISPTMG signal is supplied
externally. (However, note that if DCK is I,
the DISPTMG signal is generated internally
even if DSP is 0.)
• DCKbit
- DCK = 1: The OOTCLK signal is generated
internally.
- DCK = 0: The DOTCLK signal is supplied
externally.
$0000
Internal
data
registers
iii PS b'it
B3 Not
used
$0010
:tm
:'S,,,,
$0018
$0019
f- RO
JPa~~
registers
$001F
Figure 19 PS Bit Functions in ROM Programming Method
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HD66841F
Control Register 1 (Rl)
Control register 2 (figure 20) is composed of four
bits whose functions are described below.
• MC bit: Specifies M signal alternation.
- MC 1: The M signal alternates every line.
- MC =0: The M signal alternates every frame.
=
• DON bit: Specifies whether the LCD is on or
off.
- DON = 1: LCD on
- DON 0: LCD off
=
• MS I, MSO bits: Specify buffer memory type.
- (MS1, MSO) (0, 0): No memory
- (MS1, MSO) (0,1): 8-kbytes memory
- (MSl, MSO) =(I, 0): 32-kbytes memory
- (MS1, MSO) (1,1): 64-kbytesmemory
=
=
=
Vertical Displayed Lines Register (R1, R3, HighOrder 1 Bits of R4)
The vertical displayed lines register (figure 21) is
composed of ten bits (R2, R3, and the high-order
two bits of R4). It specifies the number of lines
displayed from top to bottom of the screen, called
the number of vertical displayed lines. This
register can specify both even and odd numbers in
single screen modes with V-drivers positioned on
one side, i.e., in display modes 2, 4, and 7-9, but
can specify only even numbers in other modes.
The value to be written into this register is Nvd - I,
where Nvd is the number of vertical displayed
lines.
eL3 Period Register (Low-Order 2 Bits of R4, RS)
The CL3 period register (figure 21), is composed
of six bits (R5 and the low-order two bits of R4). It
specifies the CL3 signal period in 8-color display
modes with horizontal stripes (display modes
13-15), so it is invalid in other modes. CL3 is the
clock signal used by the LVIC-ll to output RGB
data separately to LCD drivers. The value to be
written into this register is Npc - I, i.e., (Nhd + 6)
x 1/3 - I, where Nhd is the number of horizontal
displayed dots x 1/8. If (Nhd + 6) is not divisible
by 3, round it off.
R1
/
Data bit
Function
\
3
2
1
0
Me
DON
MS1
MSO
~---------F-~-~--1O--C-o-n-tto--I-R-e~-.-t-~-1-----~----------~
. -_____________
______--,
Data bit
Value
Npc-1
=(Nhd +6)x 1/3-1
Nvd-1
Ver1icaI displayed lines register (Unit: lines)
CL3 period register
(Unit: characters)
Nvd: Number of vertical displayed lines
Npc: CL3 period =(Nhd + 6) x 1/3
Nhd: Number of horizontal displayed characters
(number of horizontal displayed dots x 1/8)
Figure 11 Vertical Displayed Lines Register and CL3 Period Regist~
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.. _ - - - _..
--~--.-------
683
~
HD66841F
This register can specify even numbers only. In
dual-screen modes (display modes I, 6, and 16),
the most significant bit of this register is invalid.
When writing into this register, shift (Nhd - 1) in
the low-order direction for one bit to cut off the
least significant bit Figure 23 shows how to write
a value into the register when Nhd = 90.
Horizontal Displayed Characters Register (R6,
R7)
The horizontal displayed characters register (figure
22) is composed of eight bits (R6, R7). It specifies
the number of characters displayed on one
horizontal line, called the number of horizontal
displayed characters.
AS
R7
Data bit
Value
Nhd - 1 without its least signifiant bit (Unit: characters)
Figure 22 Horizontal Displayed Characters Register
RS
R7
Data bit
3
2
1
0
Value
0
0
1
0
90-1 =89
\
\1
/
..
o
3
2
1
0
1
1
0
0
~I
10-
-
I
Cut off
I
o
o
Figure 23 How to Write the Number of Horizontal Displayed Characters
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HD66841F
CL3 Pulse Width Register (R8)
Fine Adjust Register (R9)
The 4-bit CL3 pulse width register (figure 24)
specifies the high-level pulse width of the CL3
signal. In 1Ff-type LCD modes, a data hold time
is necessary and it is determined by the high-level
pulse width of the CL3 signal. The CL3 signal is
output with the high-level pulse width specified by
this register even when the LVIC-II is not in a 1Fftype LCD mode.
The 4-bit fine adjust register (figure 25) adjusts the
externally supplied display timing signal
(DISPTMG) to synchronize its phase with that of
LCD data. The value to be written into this register
depends on the interval between the rising edge of
the DISPTMG signal and the display start position.
For more details, refer to the Display Timing
Signal Fine Adjustment section and table 12. This
register is invalid if the DISPTMG signal is
generated internally, that is, if either the DCK bit or
the DSP bit of control register I (RO) is 1.
RS
/
Data bit
\
I2 I 1I0
3
(Unit: Characters)
Value
I - - In TN-type LCD modes: Npw
' - - In TFT-type LCD modes: Npw - 5
Npw: High-level pulse width ofthe CL3 signal
(number of dots while the CL3 signal is high x 1/8)
Figure 24 CL3 Pulse Width Resister
R9
/
Data bit
3
Function and Value
2
I 1I
I
\
0
I
L
Absolute value of Nda (Unit: Dots)
' - - Polarit y selection
{
0: - (advances the DISPTMG signal)
1: + (delays the DISPTMG signal)
Nda: Number of dots adjusted
Figure 2S Fine Adjust Register
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685
HD66841F
PLL Frequency-Division Ratio Register (RIO, Rll)
The 8-bit PLL frequency-division ratio register
(figure 26) specifies the PLL frequency-division
ratio used for generating dot clock pulses by a PLL
circuit. The PLL frequency-division ratio is the
ratio of the DOTCLK signal's frequency to the
horizontal synchronization signal's (HSYNC)
frequency. The LYlC-I1 generates the DOTCLK
signal according to this ratio. This register is
invalid if the DOTCLK signal is supplied
externally, i.e., it is valid only in the internal
register programming method when the DCK bit of
control register 1 (RO) is O.
The value to be written into this register is NpLL 731, where NpLL is the PLL frequency-division
ratio which can be obtained from the following
equation:
NpLL -731 = Ncht x n -731
Ncht: Total number of horizontal characters on
CRT (Total number of horizontal dots on
CRT x lin)
n:
Horizontal character pitch (number of
horizontal dots making up a character)
Ncht can be also obtained from the CRT monitor
specifications as follows;
Ncbt = lin x (DOTCLK frequency/HSYNC
frequency)
Vertical Backporch Register (R12, RI3)
The 8-bit vertical backporch register (figure 27)
specifies the vertical backporch which is the
number of lines between the active edge of the
vertical synchronization signal (VSYNC) and the
rising edge of the display timing signal
(DISPTMG), if the DISPTMG signal is generated
internally. For details on the vertical backporch,
refer to the Display Timing Signal Generation
section and figure 9.
This register is invalid if the DISPTMG signal is
supplied externally. It is valid only in the internal
register programming method when the DSP bit of
control register 1 (RO) is 1. However, note that if
the DCK bit of control register 1 (RO) is I, the
DISPTMG signal will always be generated
internally so this register is enabled even if the DSP
bit of control register 1 (RO) is O.
R11
R10
Data bit
Value
NPLL: PLL frequency-division ratio
= DOTCLK frequency/HSYNC frequency
Figure 26 PLL Frequency-Division Ratio Register
R13
R12
Data bit
Value
Ncvbp-1
(Unit: Lines)
Ncvbp: Vertical backporch = number of lines between the active edge of
the VSYNC signal and the rising edge of the DISPTMG signal (the
SPS pin must be set high if the VSYNC signal is active-high or
low if it is active-low)
Figure 27 Vertical 8ackporch Register
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HD66841F
Horizontal Backporch Register (R14, R15)
The 8-bit horizontal backporch register (figure 28)
specifies the horizontal backporch which is the
number of dots between the rising edge of the
HSYNC signal and that of the display timing signal
(DISP1MG), if the DISP1MG signal is generated
internally. For details on the horizontal backporch,
refer to the Display Timing Signal Generation
section and figure 9.
This register is invalid if the DISPTMG signal is
supplied externally. It is valid only in the internal
register programming method when the DSP bit of
control register 1 (RO) is 1. However, note that if
the DCK bit of control register 1 (RO) is 1, the
DISPTMG signal will always be generated
internally so this register is enabled even if the
DSP bit of control register 1 (RO) is O.
R14
R15
~
/
Data bit
Value
Nchbp:
3
121
1
I0 I3
121
1
Nchbp-1
I0
\
(Unit: Dots)
Horizontal backporch =number of dots between the rising edge of
the HSYNC Signal Oust before the rising edge of the DISPTMG
signal) and the rising edge of the DISPTMG signal
Figure 28 Horizontal Backprocb Registers
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HD66841F
Palette Registers (PI-PS)
The eight 4-bit palette registers (figure 29) each
specify one of 13 gray-scale levels for one of the
eight colors provided by RGB signals. Use ihese
registers to enable an 8-level gray-scale display
appropriate to the characteristics of the LCD panel.
P1-P8
Grayscale
Figure 29 Palette Registers
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Reset
The RES signal resets and starts the LVIC-II. The
reset signal must be held low for at least I J1S after
power-on.
Reset is dermed as shown in figure 30.
State of Pins after Reset
In principle, the RES signal does not control output
signals and it operates regardless of other input
signals. Output signals can be classified into the
following five groups, depending on their reset
states:
• Retains pre-reset state: CL2, AO-A4
• Driven to high-impedance state (or fixed low if
no memory is used): RDO-RD7, ODO-GD7,
BDO-BD7
• Fixed high: MWE, CL4, M, CU, CD, MCSl,
• Fixed low: MAO-MAl2, RO-R3, 00-03,
BO-B3, CL3, FLM
• Fixed high or low, depending on memory used
(table 13): MAl3-MA15, MeSO
State of Registers after Reset
The RES signal does not affect data register
contents, so the MPU can both read from and write
to data registers, even after reset Registers will
retain their pre-reset contents until they are
rewritten.
The palette registers, however, are usually set to
their default values by a reset. For the default
values, refer to the Gray-Scale Palette section and
table 11.
Memory Clear Function
After a reset, the LVIC-II writes Os in the memory
area specified by pins or register bits MSO and
MSl (table 7).
During reset
(Reset state)
5
After reset
'------~-~
Figure 30 Reset Def"mition
Table 13 State of Pins after Reset and Memory Type
Memory Type
MA13
MA14
MA15
Meso
No memory
Low
Low
High
High
8-kbytes memory
High
High
High
Low
32-kbytes memory
Low
Low
High
Low
Low
Low
Low
Low
64-kbytes memory
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689
HD66841F
User Notes
1. The following limitations are imposed if no
memory is used (MSO = 0, MSI = 0):
• Dual-screen display modes (modes 1,6, and
16) are disabled.
• LCD systems with Y-drivers on both sides are
disabled, even if a mode for a system with Ydrivers on both sides (mode 3, 5, 10, 12, or
14) is selected; the LVIC-II operates in exactly
the same way as in the corresponding mode
for a system with V-drivers on one side (mode
2, 4, 9, 11, or 13). The CL4 pin must be left
disconnected in this case.
2. With the internal register programming method,
the operation of the LVIC-II after a reset cannot
be guaranteed until its internal registers have
been written to.
3. The memory clear function might not work
normally at power-on or after a reset if the MSO
and MS 1 pins or bits are not set correctly to the
value corresponding to the type of memory
being used.
4. Since the LYlC-II is a CMOS LSI, input pins
must not be left disconnected. Refer to the Pin
Description and table 1 for details on pin
handling.
Programming Restrictions
The values written into the LVIC-II's internal
registers have the limits listed in table 14. The
symbols used in table 14 are defined in table 15
and figure 31.
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Hitachi America', Ltd,. Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Table 14 Limits on Register Values
Applicable
Item
Limits
Screen
configuration
4 S Nvd ~ (Ncvbp + Ncvsp) -1 S 1024
Notes
Register.
4 S Nhd S (Nchbp x 1/n + Nchsp) -1 ~ 506
1,2
R2, R3, R4,
R6, R7
(Nhd + 6) x n x Nvd x fFlM S f DOTClK S
1,3
R2, R3, R4,
R6,R7
1 S Npw S (Nhd + 6)/2 - 1
4
1 S NpwS Nhd
5
R4, R5, R6,
R7,RS
1 S Npw S Npc - 1
6
1 S Nchbp S 256
7
R12,R13
30MHz
CL3signai
control
DISPTMG signal
generation
No memory
1 ~ Ncvbp ~ 256
7
R14,R15
4 ~ Nhd ~ Nchsp - 4
S
R2, R3, R4,
4 ~ Nvd ~ Ncvsp-1
S
R6,R7
Notes: 1. Lowercase n indicates the horiZontal character pitch which is the number of horizontal dots
composing a character.
2. Nhd S 250 in the dual screen modes (display modes 1, 6, and 16).
3. fFlM is the FLM signal frequency and fOOTClK is the CRT display dot clock (DOTCLK) frequency.
flOOTCK < fOOTClK x 15/16 or flooTCK - fOOTClK
(flOOTCK is the LCD dot clock (LDOTCK) frequency)
4. In display modes 1, 2, 4, and 6-8
5. In display modes 3, 5, and 9-12 when Npw - (value in RS) + 5
6. In display modes 13-15 when Npw - (value in RS) + 5
7. (Value in R14 and R15) S (Nchsp x n + Nchbp) - Nhd x n - 2
(n - horizontal character pitch)
(Value in R12 and R13), (Ncvsp + Ncvbp) - Nvd - 2
S. Nht - Nchsp + (Nchbp x 1/n), Nvd < Ncvbp + Ncvsp
(Nht - (Nhd + 6) if buffer memory is used)
(n - horizontal character pitch)
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691
HD66841F
Table 15 Symbol Definitions
Symbol
DeflnHlon
Nchd
Number of horizontal displayed characters on the CRT display (number of horizontal
displayed dots on the CRT display x 1/8)
Nchsp
Number of characters between the rising edge of the DISPTMG signal and that of the HSYNC
signal (number of dots between the rising edge of the DISPTMG signal and that of the
HSYNC signal x 1/8) (- horizontal synchronization position)
Nchbp
Number of dots between the rising edge of the HSYNC signal and that of the DISPTMG
signal (just after the rising edge of the HSYNC signal) (- horizontal backporch)
Ncvbp
Number of lines between the active edge of the VSYNC signal and the rising edge of the
DISPTMG signal (just after the active edge of the V$YNC signal) (- vertical backporch)
Ncvsp
Number of lines between the rising edge of the DISPTMG signal and the active edge of the
VSYNC signal (.. vertical synch position)
Ncvd
Number of vertical displayed lines on the CRT display
Nhd
Number of horizontal displayed characters on the LCD (number of horizontal displayed dots
on the LCD x 1/8)
Npc
Number of characters during one CL3 signal period (number of dots during one CL3 signal
period x 1/8)
Npw
Number of characters while the CL3 signal is high (number of dots while the CL3 signal is
high x 1/8)
Nht
Number of characters during a CL 1 signal period (number of dots during a CL 1 signal period
x 1/8)
Nvd
Number of vertical displayed lines on the LCD
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HD66841F
------~---~---------~
DOTCLK
DISPTMG
-
Nchd
I
HSYNC
Nchsp
Nchbo
VSYNC
DISPTMG
Ncvs
Ncvd
r1JlSl ___ ___ n~_____---JnIL
CL2
CL1
-t----------------t----~r-l~-----------4
CL1
Cl3
Nhd
~
I~------------------------~~
-
I
Npw
I
Npc
Nht
FLM
CL1
I
II~
___
~--------------------~
Nvd
I
I.
I
4
(Note)
~
Note: For a dual screen, the Nvd period is doubled.
Figure 31 Symbol Definitions
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693
HD66841F
Comparisons with HD66840F
Mode number:
Pin setting:
Gray-Scale Generation Method
The HD66840F shifts display data so that data on
different lines will be thinned out in different
frames, but the HD66841F shifts display data
further so that data on different dots will be thinned
out in different frames. This reduces deterioration
of display contrast.
Display Mode
Mode 16 of the HD66840F (for 8-color display
with horizontal stripes and X- and Y-drivers
positioned on both sides of the LCD) has been
modified into the following new mode in the
HD6684 IF:
16
(DM3, DM2, DMl, DMO) =
(1, 1, 1, 1)
Display colors:
8 colors
LCD data output:
-12-bit-based data transfer
- Dual screen configuration
LCD driver settings: X-drivers and Y-drivers set
on one side
Stripes:
Vertical
Every frame
Alternation mode:
In this mode, the HD66841F outputs upper screen
data and lower screen data alternately, as shown in
figure 32. In this case, the CL2 frequency is one
quarter of the LDOTCK frequency.
Cl2
U
X
L
X
U
X
L
X
U
X
L
>C
U
X
L
X
U
X
L
X
U
X
L
>C
U
X
L
X
U
X
L
X
U
X
L
>C
U: Upper screen data
L: Lower screen data
Figure 32 Operation in New HD66841F Mode 16
Table 16 Gray-Scale Palette
Numbers of registers
HD66840F
HD66841F
16
24
(palette registers have been added to the
HD66840's registers)
between CRT display colors
Possible
(any of 13 levels assignable to each
and gray-scale levels
of 8 colors)
Selection of correspondence
Impossible
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HD66841F
Absolute Maximum Ratings
Item
Symbol
Ratings
Un"
Power supply voltage .
Vee
-0.3 to 7.0
V
Input voltage
Vln
-0.3 to Vee + 0.3
V
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +125
°C
Notes:
1. Permanent LSI damage may occur if maximum ratings are exceeded.
Normal operation should be under recommended operating conditions (Vee. 5.0V ± 10%,
GND • 0 V, Ta _ -20°C to +75°C). "these conditions are exceeded, LSI reliability may be
affected.
2. All voltages are referenced to GND • 0 V.
Electrical Characteristics
DC Characteristics (Vee
=5.0 V ± 10%, GND =0 V, Ta =_20°C to +75°C, unless otherwise noted)
Item
Symbol
Min
Max
Unit
VIH
Vee -0.5
Vee + 0.3
V
Test Conditions
Note(s)
Input high voltage
--
RES pin
TTL interface pins
2.0
Vee + 0.3
1
TTL interface pins
2.2
Vee + 0.3
4
CMOS interface pins
0.7 Vee
Vee + 0.3
Input low voltage
-0.3
O.S
TTL interface pins
TTL interface pins, RES pin
-0.3
0.6
CMOS interface pins
-0.3
0.3 Vee
VIL
V
5
Output high voltage
TTL interface pins
VOH
CMOS interface pins
V
2.4
Vee- O.S
IOH • -200
JJA
IoH - -200
J1A
2
Output low voltage
TTL interface pins
0.4
VOL
V
IoL -1.6mA
2
IOL .. 200~A
O.S
CMOS interface pins
Input leakage current
All inputs expect
IlL
-2.5
2.5
~A
3
ITSL
-10.0
10.0
JJA
3
250
mW
1/0 common pins
Three-state (off-state)
leakage current
1/0 common pins
Power dissipation
Icc
fOOTeLK .. 30 MHz,
output pins left
disconnected
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
695
-----,-------
HD66841F
Notes: 1. TIL interface inputs: R, G, B, HSYNC, VSYNC, DISPTMG, RDo-RD7, GDo-GD7, BDo-BD7,
Do-D3, AOiRDlXDOT, RS/ADJlA4, CSlMSO
CMOS Interface inputs: DMo-DM3, DOTE, PMODO, PMOD1, A11YL0-A31Y12.
2. TIL interface Inputs: AOJRDIXDOT, A1IYLo-A3IYL2, Do-D3, RDo-RD7, GDo-GD7, BDo-BD7,
MAo-MA15, MOSO, MOS1, MWE, Rs/ADJ/A4
CMOS interface inputs: CU, CD, ROILUo-R3ILU3, GOILDo-G3!lD3, B0-B3, M, FLM, CL1, CL2,
CL3,CL4
3. VO common pins: AOJRDIXDOT, A1IYLo-A3IYL2, Do-D3, RDo-RD7, GDo-GD7, BDo-BD7,
RS/ADJ/A4
Inputs other than 00 common pins: HSYNC, VSYNC, PMODO, PMOD1, CSlMSO, WRlMS1,
RES, DOTe, DMo-DM3, LDOTCK, DOTCLK, R, G, B, DISPTMG
4. m Interface inputs: WRlMS1, LDOTCK, DOTCLK
5.
interface inputs: WRlMS1
m
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
AC Characteristics (Vee
=5.0 V ± 10%, GND =0 V, 18 =-20°C to +75°C)
Video Signal Interface
Item
Symbol
Min
Max
Unit
Reference
DOTCLK cycle time
tevco
33
1000
ns
Figure 33
DOTCLK high-level pulse width
tWOH
16.5
tWOL
16.5
DOTCLK low-level pulse width
OOTCLK rise time
ns
ns
tor1
5
ns
DOTCLK fall time
tDl1
5
ns
RGB setup time
tvos
10
ns
ns
tVDH
10
DISPTMG setup time
tOTS
10
ns
DISPTMG hold time
tOTH
10
ns
HSYNC setup time
RGB hold time
tHSS
10
ns
HSYNC hold time
tHSH
10
ns
Phase shift setup time
tPDS
2tevco
ns
Phase shift hold time
tPDH
2tCYCO
ns
Input signal rise time
t0r2
10
ns
too
10
ns
Input signal fall time
Figure 33
except for OOTCLK
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
697
HD66841F
tWOl.
tWOH
DOTCLK
R,G,B
tHSS
HSYNC
DOTCLK
DISPTMG
HSYNC
VSYNC
Jl;t
~
\
I
I
\
\
r
\
O.SV
Figure 33 Video Signal Interface
HITACHI
698
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
Burrer Memory Interface
Hem
Symbol
Min
Unit
Reference
tRC
5tcvco-5O
ns
Figures 34 and 35
RDo-RD7. GDO-GD7. BDo-BD7
data setup time
tSMD
25
ns
RDo-RD7. GDO-GD7. BDo-BD7
data hold time
ltiMO
0
ns
Read cycle time
Write cycle time
twc
6tcvco-5O
ns
Address setup time
lMAs
tcvco-30
ns
Address hold time
tWR
tcvco- 3O
ns
Chip select time
lew
4tcvco-4O
ns
Write pulse width
twp
4tcvco-40
ns
RDo-RD7.GDO-GD7.BDo-BD7
output setup time
tSMDW
2tcvco- 25
ns
RDo-RD7. GDO-GD7. BDo-BD7
output hold time
ltiMDW
0
ns
Note: tcvco is the DOTCLK cycle time (min 33 nSf max 1000 ns).
Read 1
Read 2
Write
Read 1
MAO-MA15
RIJO...RD7,
G~D7
BDO-BD7
(Memory .... LVIC)
Figure 34 Burrer Memory Interface (RAM read timing)
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699
HD66841F
T1 (= 51o.co)
2
OOlOJ(
,.. ....
- ,--/'
I
fIN'O-MI'.15
-- ,.. .... -- .... -- ,.. .... -- -"" ... - .... --
....,
,
I
I
,..
,
,
I
I
,
I
,.. ,
I
,.. r..,
tw::
I
,
-~K
2AV
O.8V""
2.4V
O.8V
Is...
tMlS
M:SO, M::S1
(Write)
,.. ....
-- ---
""'
tMlS
~
tON
2.4V
O.8V
~
two
"'"'
2.4V
O.8V
l~fWN..
tSM:!N
ROO-RDl, GDO-GD~
r2.4V
O.8V
BIJO.-8D7
(LVIC-IH Memol}')
~
Figure 3S Buffer Memory Interrace (RAM write timing)
LCD Driver Interrace
TN-Type LCD Driver
Item
Symbol
Min
Cl2 cycle time
tWCL2
Cl2 high-level pulse width
Max
Unit
Reference
166
ns
Figures 36 and 37
tWCL2H
50
ns
Cl2 low-level pulse width
tWCl2L
50
ns
Cl2 rise time
teL2r
30
ns
Cl2 fall time
teL2f
30
ns
Cl1 high-level pulse width
tWCL1H
Cl1 rise time
tellr
30
ns
Cl1 fall time
tell!
30
ns
Cl1 setup time
tSCll
500
ns
Cl1 hold time
tHCL1
200
ns
FlM hold time
tHF
200
ns
M output delay time
toM
Data delay time
too
-20
lDOTCK cycle time
tWLDOT
41
ns
200
300
ns
20
ns
ns
Note: All values are measured at fCl2 .. 6 MHz.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
TFT-Type LCD Driver
Item
Symbol
Min
CL2 cycle time
(X-drivers on one side)
trcl2s
CL2 high-level pulse width
(X-drivers on one side»
Max
Unit
Reference
133
ns
Figures 38 and 39
trCl2HS
30
ns
CL2 low-level pulse width
(X-drivers on one side)
trCl2LS
30
ns
CL2 cycle time
(X-drivers on both sides)
trcl20
266
ns
Cl2 high-level pulse width
(X-drivers on both sides)
trCl2HO
80
ns
CL2 low-level pulse width
(X-drivers on both sides)
trCl2LO
80
ns
CL2 rise time
teL2r
30
ns
CL2 fall time
teL2f
30
ns
Cl1 high-level pulse width
trCL1H
Cl1 rise time
teL1r
30
ns
Cl1 fall time
teL1!
30
ns
Data delay time
20
ns
200
ns
tOOl
-20
Data setup time
tLDS
15
ns
Data hold time
ttOH
15
ns
Cl1 setup time
trscL1
500
ns
Cl1 hold time
trHcLl
200
ns
Cl3 delay time
tocL3
50
ns
Mdelaytime
tOM
FlM hold time
trFH
200
ns
tWLDOr
33
ns
lDOTCK cycle time
300
ns
HITACHI
Hitachi America, ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
701
C12
,,04t3, GO-G3
B0-B3
tWCLlH
'-1
tacLI
Cll
O.7Vcc
FLM
M
Figure 36 TN·Type LCD Driver Interface
I I I I I I I I I ISS I I I I I I I I I ISS' , , , , , , , ,
CL1
~--------~s~~----~s~------
FLM
M (MC bit
=0)
M (Me bit
=1)
ss---J
--u-uLS1J1s{L..S1.JlJlJU-U-U-U..J
S~
Figure 37 CLl, FLM, and M (expanded detaO of figure 36)
HITACHI
702
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
X-drivers on
one side
CL2
R0-R3
GO-G3
BO-B3
X-drivers on
both sides
tTCL2D
CL2
R0-R3
GO-G3
BO-B3
CLl
CL3
o. 7Vcc
FlM
M
Figure 38 TYr·Type LCD Driver Interface
Cll
__~n~________________~n~____
Cl3
Cl4
-----,
(CL3divided
IL._ _ _ _ _ _..J
by 2)
J
J
L
I..-tTfH
~----------~
FlM
M
Figure 39 CLl, CL3, CL4, FLM, and M in Horizontal Stripe Modes (expanded detail of figure 38)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
703
II
HD66841F
Register Programming
MPU Interface
Item
Symbol
Min
RD high-level pulse width
tWROH
RD low-level pulse width
Max
Unit
Reference
190
ns
Figure 40
tWRDL
190
ns
WR high-level pulse width
tWWRH
190
ns
WR low-level pulse width
twwRL
190
ns
es, RS setup time
es, RS hold time
tAS
0
ns
tAH
0
ns
00-03 setup time
tosw
100
ns
00-03 hold time
tOHw
0
ns
00-03 output delay time
tOOR
00-03 output hold time
tOHR
CS
ns
10
<-'~ ..,..
2.0V ~ ~
o.sv
RS
ns
150
~
tAS
Wi
tWRDL
"
-"
.."
J
2.0V,,~
o.sv
)
tWWEH
I
tOOR .....-
00-03
2.4 V
O.SV
_11k.
tWRDH
~
I
~
Wi
WI
twweL
-
2.0 V
o.sv
'4-
1\
c
"-
Output
-
~
toHR
2.0 V
O.SV
Input
tOHW
~
Figure 40 MPU Interface
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HD66841F
ROM Interface
Item
Symbol
Min
A signal cycle time
tcYCA
528
A signal rise time
tAr
100
ns
A signal fall time
tAl
100
ns
D signal ROM data setup time
tOSWD
120
ns
D signal ROM data hold time
tOHWO
0
ns
Note:
Max
Unit
Reference
ns
Figure 41
tCYCA - 16 tCYCO (tCYCO: DOTCLK cycle time)
-
tCVCA
AO-A4
(LVIC .... ROM)
2.4 V
")<
tAr-tAl
~
toswo
DO-D3
(ROM .... LVIC)
~
Valid
)<
Valid
2.0 V
O.BV
tllHWO
Valid
K
Figure 41 ROM Interface
PLL Interrace
Max
Unit
Referenc2
tUI
80
ns
Figure 42
CU rise delay time
tUr
80
ns
CD fall delay time
tDf
80
ns
CD rise delay time
tOr
80
ns
Max
Unit
Reference
~
Figure 43
Item
Symbol
CU fall delay time
Min
Reset Input
Item
Symbol
Reset input pulse width
tRES
Min
HITACHI
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705
HD66841F
DOTCLK
HSYNC
Figure 42 PLL Interrace
.r
1.
tRES
--
--X'----~~·8V
Figure 43 Reset Input
Load Circuits
TTL Load
Pins
R
c
Remarks
MAO-MA15, MWE, MCSO, MCS1,
BDO-BD7, GDO-GD7, RDO-RD7
2.4kn
11 kn
40 pF
tr, tf: Not specified
AO/RDIXDOT, A 1IYLo-A3IYL2,
A4/RS/ADJ
2.4kn
11 kn
40 pF
tr, tf: Specified
Pins
c
Remarks
CL1, CL2
40pF
tr, tf: Specified
Ro-R3,GO-G3,BO-B3,FLM,
M, CU, CD, CL3, CL4
40pF
tr, tf: Not specified
Capacitive Load
HITACHI
706
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66841F
All diodes - 1S20748
Figure 44 TIL Load Circuit
~c
I
Figure 45 Capacitive Load Circuit
HITACHI
Hitachi America,
Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
707
HD66850F-----Color LCD Interface Engine (CLINE)
Description
Features
The HD66850F CLINE interface controller
converts multi-color video signals for CRT display
into color or monochrome LCD data.
•
•
This device enables an LCD system to replace a
CRT display system without any changes to the
original display system. It automatically adapts to
display modes of the IBM-VGA (Video Graphics
ArrayTM) system, facilitating the configuration of
an LCD system.
The CLINE can control1N-type (Twisted rematic)
color and monochrome LCDs and can display a
maximum of 4096 color levels or 16 gray levels.
•
•
Note: Video Graphics Array is a trademark of
International Business Machines Corporation, U.S.A.
•
•
Various LCD panel sizes supported
- 640 or 720 dots wide
-- 32 to 512 lines high
Programmable display size
- 32 to 720 dots wide
- 32 to 512 lines high
Easy-to-see display
-Centering
- Stretching (display stretched to fill out the
panel)
Improved gradation display quality using the
pulse width modulation method
Desired gradation levels assignable to each
display color through the use of internal
gradation level palettes
Changeable LCD frame frequency
- Through the use of a multi-port RAM frame
buffer
- Within the range of 1/2 to 2 times of CRT
display dot clock frequency
High-speed operating frequency: 32 MHz
(CRT display dot clock)
Recommended LCD drivers: HD66106 and
HD66107T (column and common drivers)
Single power supply: +5 V
I 36-pin flat plastic package (FP-136)
HITACHI
708
Hitachi America, Ltd.· HitachiPlaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
HD66850F
Pin Arrangement
GND6
LOO
LD2
LD1
LOO
GND5
XCl1
YCl1
Cl2
FlM
M
SCLK
DATAE
DISPON
VCC5
LMODE4
LMODE3
LMODE2
LMODE1
LMODEO
GND4
HSIZE
VSIZE
VMODE
MMODE1
MMODEO
VCC4
PMODE1
PMODEO
SYNC
TEST1
TESTO
GND3
MD15
Note: Pin No.9 is not used; must be fixed low.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
709
II
HD66850F
Pin Description
Symbol
Pin No.
Power
supply
Vcc 1 Vcc7
14,34,53,76,
88, 115, 124
All of these pins must be
connected to a +5V supply
GN01 GN08
GN01-GN07
16,46,70,82,
97,102,131,136
All of these pins must be grounded.
DO - 07'1
(M) 116 - 123
MPUIROM
or program
interface
Pin Name
110
'TYpe
OataO-7
Function
110
Transfer data between internal
registers and MPU
-------------------------------------------------------------------------00-07'1 (R) 116-123
OataO-7
Input data to internal registers from
external ROM
DOTE
(P) 130
Dot clock edge
change
Switches RGB data latch timing
High: Data latched at the rising
edge of OOTCLK pulses
Low: Data latched at the falling
edge of OOTCLK pulses
~D-------(M)130----------R;;d---------------i~p~~-;~;;d;~~~li~;r~~di~g----
data from internal registers
-------------------------------------------------------------------------AS
(R) 130
Address 5
0
Outputs external ROM address 5
SP
(P) 129
Spread display
select I
Selects either of the following
display size modes
High: Double - width display
Low: Normal display
VVR-------(M)129---------vvri~----------------i;ptrt;~-;;i;;ig~-~f~;~;~~g-----
______________________________________________
A4
(R) 129
Address 4
AJ3
(P) 128
Adjust 3
0
_________ _
~~_~~o_~~!~~~!~~!!~
Outputs external ROM address 4
Adjusts the display timing signal
(table 1)
-~--------(M)-128---------C-hip~~I~------~----i~p~t;-;~h~-;;I;.ct;~~~t~~~i;ct-
the CLINE
High: The CLINE not selected
Low: The CLINE selected
AJ2
(P) 127
Adjust 2
Adjusts the display timing signal
(table 1)
RS
(M) 127
Register select
Inputs a register select signal to
select either CLINE data registers
or index register
High: Data registers
Low: The index register
--------------------------------------------------------------------------A2
(R) 127
Address 2
0
Outputs external ROM address 2
AJO, AJ1'2 (P) 125, 126
Adjust 0, 1
______________________________________________
AO, A1*2
(R) 125, 126
Address 0.1
o
Adjust the display timing signal
~~~-!t--
___________________ _
Output external ROM addresses 0
and 1, respectively
(M): For MPU programming method (R): For ROM programming method (P): For pin programming method
110: Input/Output
HITACHI
710
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Pin Description (cont.)
Symbol
CRT
interface
RO-R3'3
1-4
Red serial data 0 - 3
Input CRT display R data
GO-G3"3
5-8
Green serial data 0 - 3
Input CRT display G data or
monochrome data
BO-B3'3
10-13
Blue serial data 0 - 3
Input CRT display B data: For
monochrome display. B1 selects 16gray-scale display and BO indicates
the type of CRT display data input.
B1 • high: Prohibited
B1.low: 16-level gray scale
display
BO - high: 64-color data input
BO • low: 16-level gray scale
data input
DOTCLK
15
Dot clock
Inputs the dot clock pulses for CRT
display
HSYNC
134
Horizontal
synchronization
Inputs the CRT horizontal synchronization signal
VSYNC
133
Vertical
synchronization
Inputs the CRT vertical synchronization signal
BLANK
135
Blanking
Inputs a display timing siganl
indicating horizontal or vertical
display period. or a blank signal
indicating the display period with
border area period
UD4UD7'4
111 -114
LCD upper panel data
4-7
0
Output LCD upper panel data or
Rdata
UDOUD3'4
107-110
LCD upper panel data
0-3
0
Output LCD upper panel data or
Gdata
LD4LD7'4
103 -106
LCD lower panel data
4-7
0
Output LCD lower panel data or
Bdata
LDOLD3'4
98-101
LCD lower panel data
0-3
0
Output LCD lower panel data or
I data
XCL1'4
96
X-driver latch clock
0
Outputs the LCD data latch clock
pulses for X-drivers
YCL1
95
Y-driver shift clock
0
Outputs the LCD data line shift
clock pulses for Y-drivers
Cl2
94
Y-driver shift clock
0
Outputs the LCD data line shift
clock pulses for Y-drivers
FLM
93
First line maker
0
Outputs the first line maker for
Y-drivers
LCD
interface
Pin No.
Pin Name
1/0
Type
Function
1/0: Input/Output
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
711
I
HD66.850F
Pin Description (cont.)
1\'Pa
Symbol
Pin Noo
Pin Nama
LCD
interface
M
92
M
110 Function
0
Outputs a signal for converting LCD
SCLK
91 .
Shift lock
0
DATAEo4
90
Dataenable
0
Indicates LCD data display period
DISPON·4
89
Display on
0
Controls LCD onloff
Buffer
memory
interfae.
Mode
control
drive signals to AC
Outputs clock pulse with a
frequency identical to CL2 but
without a retrace period
LOOTCK
17
LCD dot clock
I
Inputs LCD dot clock pulses
MDOMD15·S
54-69
Memory data 0 - 15
0
Output data to be written to buffer
memory
MSOMS15·s
18-33
Memory serial data
0-15
MAOMA7·s
38-45
Memory address
0-7
0
Output buffer memory addresses
0-7
MA8/
SOE1·s
37
Memory address 8/
serial output enable 1
0
Outputs buffer memory address 8
when 1-Mbit RAMs are used or
outputs a serial data output enable
signal when 256-kbit RAMs are
used
SOEO·s
36
Serial output enable 0
0
Output a serial data output enable
signal for buffer memory
WE·s
48
Writeenable
0
Outputs a write enable signal for
buffer memory
DTIOE·s
47
Data transfer/output
enable
0
Outputs a data transfer signal or
an output enable signal ~or buffer
memory
RASO,
RASi·s
51,52
Row address strobe 0,
row address strobe 1
0
Outputs a row address strobe signal
for buffer memory
CAS,
CASL·S
49,50
Column address
strobe
0
Outputs a column address strobe
signal for buffer memory
SC·s
35
Serial clock
0
Outputs serial read clock pulses for
buffer memory
PMODEO,
PMODE1
74, 75
Program mode 0,
program mode 1
Select a CLINE programming
method (table 2)
LMODEO- 83-87
LMODE4
LCD modeO-4
Select a display mode (table 7)
MMODEO,
MMODE1
77, 78
Memory mode 0, 1
Select a memory configuration
(table 3)
SYNC
73
Synchronization
Select a basic clock for LCD
High: OOTCLK
Low: LOOTCK
Input data read from buffer memory
00: InpUVOutput
HITACHI
712
Hitachi America,ltd~. Hitachi Plaza· 2000 Sierra Point P.kwy.· Brisbane, CA 94005-1819. (415) 589-8300
HD66850F
Pin Description (cont.)
Type
Symbol
Pin No.
Pin Name
110
Function
Mode
control
(cont)
VMODE
79
VGAmode
I
Specifies a CRT display system
High: Non-VGA system
Low: VGA system
VSIZE
80
LCD vertical size
Specifies the vertical size of the
LCD panel
High: 480 lines
Low: 400 lines
HSIZE
81
LCD horizontal size
Specifies the horizontal size of the
LCD panel
High: 720 dots
Low: 640 dots
RES
132
Reset
Inputs an external reset signal
TESTO,
TEST1
71, 72
Test 0,1
Used for tests; Must be grounded
110: InputlOutput
Notes: 1.
2.
3.
4.
5.
6.
Must be fixed low for pin programming method.
Must be fixed low for MPU programming method.
Must be fixed low when not used.
Must be left disconnected when not used.
Must be left disconnected when buffer memory is not used.
Must be fixed low when buffer memory is not used.
Table 1 Display Timing Signal Fine Adjustment
Pin
AJ3
AJ2
AJ1
AJO
0
0
0
0
0
0
0
0
0
Number of Dots
Adjusted
0
1.1
-1
0
-2
0
0
0
0
0
0
0
1
0
+2
0
0
+4
+1
+3
0
+5
0
0
+6
Note: - (minus) indicates advancing the phase of the display timing signal,
+ (plus) indicates delaying the phase of the display timing signal.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
713
HD66850F
Table 2 Programming Method Selection
Pin
PMODE1
PMODEO
Programming Method
0
0
Pin
0
1
Internal registers (MPU)
1
0
Internal registers (ROM)
1
Prohibited
Table 3 Memory Configuration Selection
Pin
MMODE1
MMODEO
Memory Configuration
o
o
0
1·Mbit RAM
1
256·kbit RAM
1
0
No memory
No memory (when the CRT controller
supports dual screen display)
HITACHI
714
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300
HD66850F
Block Diagram
VMODE-+--------~~~-LL-~~-L~~~~~I
LCD interface
VSIZE
HSIZE -+--'
Line buffer memory
(R, G, B)
LMODE4LMODEO
Gradation
MSO-MS15
control
Bus
control
Frame
MDO-MD15
buffer
memory
control
i
.~
~
(R, G, B)
Stretch!
Serial to
parallel
centering
control
~
MAO-MA7
MASlSOE1
SOEO
DTIOE
WE
SC
RASO/RAS1
CASICASL
converter
MMODE 1/0
RES
LDOTCK
Gradation level
Timing
reducing circuit
Internal
register
DOTCLK
SYNC
MPUIROM
Interface
PMODE11O
D7-DO
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
7-15
...,.
.....
Table 4 Register List
m
~
:J:
s:<>
2:
CS RS 3
»
Index Reg
2
1
ii
Reg.
No. Register Name
Program
Units
Readl
Write
3
'"
:::I.
C>
6
5
*
*
*
*
1
0
*
*
*
*
1A3
IA2
IA1
lAO
SP
OISP
ON
AJ2
AJ1
AJO
OH3 OH2
OH1
OHO
a
OV8
g.
IR
Index
W
0
RO
Control
RIW
STE
R1
Input timing control
Dot
RIW
DOTE AJ3
0
R2
Horizontal display size
Character
RIW
1
1
R3
Vertical c:isplay size (high-order)
Line
RIW
0
R4
Vertical c:isplay size (Iow-order)
Line
RIW
OV7
OVS
OV5 DV4
OV3
OV2
OV1
OVO
(i'
R5
Centering raster
RIW
CR7
CRS
CR5 CR4
CR3 CR2
CR1
CRO
~
AS
Centering character
CC4
CC3 CC2
CC1
CCO
BM
BCI
BCR
BCG
BCB
0
0
0
0
0
0
0
0
0
0
~
·
0
0
0
N
0
0
0
en
0
0
0
0
0
CRE CCE
:J:
"'0
0
0
0
~.
iil
:I
~~
0
~O
0
~
•
0:1
0
0
0
0
0
0
0
0
0
0
~
~.
CT
'"
50
::::>
C')
»
-
:I
0
1
0
0
0
0
0
0
Character
OH5 OH4
RIW
R7
Border color control
AS
Stretching control
Line
RIW
SF3
SF2
SF1
5FO
R9
Stretching index (high-order)
Line
RIW
5115 5114
5113 SI12
Sl11
SI10
519
Sl8
RIW
517
SIO
R10 Stretching index (Iow-order)
R11
0
·Une
(Raster)
OHS
RIW
line
Gradation level palette address
R12 Gradation level palette data
515
SI4
SI3
SI2
SI1
W
PS1
PSO
PA3
PA2
PA1
PAD
RIW
PD5 PD4
P03 P02
P01
POD
51S
<0
"""
0
0
'!:
S'
0
~
0
·
<0
~
U1
0>
<0
do
c.>
0
0
Notes:
~
0
0
::T
~
0
!:::;:
'"<>_.
'"
0
!"
;:;:
~.
2
0
0
P-
0
7
Data Bits
4
3
0
R13 Gradation c:isplay clock period
(high-order)
Dot
RIW
R14 Gradation c:isplay clock period
(Iow-order)
Dot
RIW
GCa
GC7 GCS
R15 Reserved
1. Bits marked with • cannot either read from or written to.
2. Bits marked with - are invalid and must be initialized to Os; they cannot be read.
GC5 GC4
GC3 GC2
GC1
GCO
c:
'"
8
8
~.
5'
~
....
....
.,
....t"'4
....
I'D
(JQ
fIl
I'D
fIl
:r:
0
en
en
c.n
(X)
0
":ti
HD66850F
System Description
Addition of an external frame buffer memory
(dual-port RAM) allows the LCD frame frequency
to be increased above that of a CRT. This enables
easy-to-see gradation display and the control of
LCDs having a dual screen configuration.
Figure 1 shows an example of a VGA-compatible
display system implemented with the CLINE. In
this system, a color palette HD153119 (Hitachi),
which is capable of digital output, is used with a
VGA-compatible CRT controller. The CLINE
receives digital color data and display sychronization signals from the color pallette and the
CRT controller, respectively, and displays 4096color images on a color LCD, or 16-level
gmyscale images on a monochrome LCD. With
minor mOdification of the existing CRT display
system, simultaneous LCD and CRT display is
possible.
CLINE operation may be controlled by internal
registers through the 80-family MPU bus or an
external ROM (as shown in the figure), or simply
by pins.
I
MPU or ROM
RO-R3
GO-G3
IPO-P!
VGA
compatible
CRT controller
Color
palette
HD153119
BO-B3
f--
~
CLINE
HSYNC,VSYNC
DOTCLK, BLANK
H
LCD
/
B
Frame buffer
memory
Analog data
CRT
Figure 1 System Block Diagram
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
717
HD66850F
Functional Description
Programming Methods
To control CLINE functions, set the appropriate
pins and/or internal registers according to the
functions used. Controlling methods include pin
and internal register programming methods.
Internal register programming includes the MPU
and ROM programming methods. Any of the
three methods can be selected by the combined
setting of pins PMODEO and PMODE I (table 2).
The pin programming method uses pins to control
CLINE functions, and the internal register
programming method uses data written to the
internal registers to control the functions.
Address bus
Data bus
lOW
lOR
Figure 2 (a) shows a connection 'example of the
CLINE and MPU buses for the MPU programming method. The CLINE bus, which is compatible with the 80-family microprocessor bus, can
be directly connected to the host MPU bus.
Figure 2 (b) shows a connection example of the
CLINE and ROM for the ROM programming
method. In this case, data is automatically loaded
into internal registers from the external ROM
attached for this purpose. Note that with the ROM
programming method, the reset signal must be
applied before rewriting the internal registers or
gradation level palettes.
II
==t~
I
1
ROM
~
I--
Decoder
cs
AD-AS
00-07
I
,
RS
WR
RO 00-07
HD66850F
(a) Connection of MPU bus With CLINE
AD-AS
00-07
HD66850F
(b) Connection of ROM With CLINE
Figure 2 Connection of MPU Bus or ROM with CLINE
HITACHI
718
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Automatic Adaptation to VGA Display Modes
VGA CRT display system display size varies
depending on the display mode. (VGA display
sizes are: 320, 360, 640, or 720 dots wide and 350,
400, or 480 lines high.) The CLINE identifies the
current display mode from VSYNC and HSYNC
signal polarities and the display period length, and
changes the display size automatically (tables 5
and 6). This function is enabled by setting the
VMODE pin low. The CLINE, based on this
function, automatically sets the necessary registers
(RO, R2, R3, R4, R5, R6, R8, R9, and/or RIO)
corresponding to the parameters of the display
size, double-width display, gradation display
clock, and stretching/centering display functions.
(In MPU or ROM programming method, selection
of vertical centering (bit 3 of RO) or stretching (bit
4 of RO) is not automatic.) Consequently, in VGA
display modes, rewriting these registers is disabled.
Note that display stretching and centering are
unavailable when buffer memory is not used in the
system, even in VGA display modes. In these
cases, a display of different vertical size would be
placed in the upper section of the LCD panel,
resulting in a blank area in the lower section.
Centering the display in a system without memory
requires external circuits or BIOS tuning.
When displaying an image 720 dots wide (9 dots x
80 characters) on an LCD panel 640 dots wide, the
CLINE removes the ninth horizontal dot of each
character to prevent losing the far-right portion of
the image.
TableS Automatic Vertical Display Size Settings for VGA Display Modes
VSYNC
HSYNC
Display Size
Border Rasters
Displayed Rasters
Negative
Positive
350 lines
1-6
7-356
Positive
Negative
400 lines
1-7
8-407
Negative
Negative
480 lines
1-8
9-488
Table (; Automatic Horizontal Display Size Settings for VGA Display Modes
BLANK Signal High Level
Pulse Width
Display Size
Border Dots
Displayed Dots
256-335 dots
320 dots (256-color)
1-5
6-325
336-359 dots
320 dots (16-color)
1-8
9-328
360-511 dots
360 dots
1-9
10-369
640-703 dots
640 dots
1-8
9-648
704-767 dots
720 dots
1-9
10-729
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
719
HD66850F
LCD Panel Size
LCD panel size is specified by either pins or
internal registers.
For VGA modes, vertical panel size of 400 or 480
lines can be selected by the VSIZE pin and
horizontal panel size of 640 or 720 lines by the
HSlZEpin.
For non-VGA modes, the panel size is also
specified by the VSIZE and HSIZE pins in pin
programming method. In internal register
programming method, vertical display size is
specified by the vertical display size register (R3
and R4), within the range of 2 to 512 lines. Here,
note that the vertical display size specified by R3
and R4 is the CRT display vertical size. When this
size differs from the LCD panel vertical size,
centering or stretching function must be used.
Refer to the following equations for calculating
the number of centering rasters and the stretching
ratio. For the defmition of the centering rasters,
S{:e figure 23, Centering Rasters,
" For centering
LCD panel vertical size (line) =
CRT display vertical size (line) + centering
rasters (lines) x 2
" For stretching
LCD panel vertical size (line) =
CRT display vertical size (line) x stretching
ratio
Since LCD panel horizontal size is limited to 640
or 720 dots even in internal register programming
method, centering function must be used as well
so that the total number of horizontal dots
including the CRT display area and border areas
become 640 or 720. Refer to the following
equation to calculate the number of centering
characters. For the defmition of the border areas
and centering characters, see figure 25, Centering
Characters.
LCD panel horizontal size (dot) =
{number of horizontal display characters +
(number of centering characters x 2)} x 8
Double-Width Display
Some CRT display systems have a low-resolution
display mode of 320 horizontal dots in addition to
a high-resolution display mode of 640 horizontal
dots. In this case, the CRT display system lowers
the dot clock frequency to reduce one line of data
to 320 dots. If such data is supplied to the LCD
system of 640 horizontal dots as-is, the entire
display will be placed on the left section of the
panel with the right half blank. To accommodate
this situation, the CLINE doubles the width of the
low-resolution display. This function is enabled
by the SPlWRlA4 pin in pin programming method
or the SP bit (bit 1) of the control register (RO) in
internal register programming method (table 7). In
either method, for VGA display systems, the
CLINE detects low-resolution display mode and
automatically enables double-width display.
Table 7 Double-Width Display Usage
Programming Method
CRT System Mode
Setting
Pin: SP
VGA
Automatic
Non-VGA
0: Normal display
1: Double-width display
Internal register:
Control register bit 1
. (SP bit)
VGA
Automatic
Non-VGA
0: Normal display
1: Double-width display
HITACHI
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Hitachi America, Ltd." Hitachi Plaza' 2000 Sierra Point Pkwy." Brisbane, CA 94005-1819" (415) 589-8300
HD66850F
Stretching and Centering Display
When the display size differs from the LCD panel
size, data will be displayed on the upper-left
section of the LCD panel with blank space to the
right and/or below if no countermeasures are taken.
To provide a user-friendly display, the CLINE can
stretch a display to fill out the panel or center a
display. Both stretching and centering functions
are enabled by control register (RO) bits 2, 3, and 4.
Stretching function is controlled by the stretching
control register (R8) and the stretching index
register (R9 and RIO) so as to double the vertical
display size at most
Figure 3 shows display examples using stretching/
centering functions. In these examples, a display
of 640 dots x 350 lines is displayed on an LCD
panel of 720 dots x 400 lines, using
stretching/centering functions.
Note that stretching and centering functions are
available only in a system where buffer memory is
used. This is because these functions are realized
through adjustment of memory access. Similarly,
stretching and centering functions are unavailable
in non- VGA modes when the CLINE is controlled
by the pin programming method. Simultaneous
use of the vertical centering and stretching
functions is also impossible.
For VGA modes, in both internal register
programming and pin programming methods,
necessary parameters are automatically calculated
from the relationship between display size and the
LCD panel size and set in the appropriate registers.
Consequently, there is no need to account for
display size.
In the internal register programming method,
horizontal centering function is controlled by the
centering character register (R6) within the range of 1
to 32 characters (8 to 256 dots), while vertical
centering function is controlled by the centering
raster register (R5) within the range of 1 to 256 lines.
However, the vertical centering or stretching
function can be selected in. the internal register
programming method. (In pin programming
method, the· stretching function is automatically
selected.) Table 8 describes the use of the
stretching and centering function.
...~ Vertical
t--..;..;;:;~~--
--t-t-... centering
lines
350
Horizontal centering
Horizontal centering
(a) Horizontal Centering and
Vertical Centering
(b) Horizontal Centering and
Vertical Stretching
Figure 3 Display Examples Using Stretching/Centering Functions
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
721
HD66850F
Table 8 Stretching and Centering Function Usage
Direction
Programming
Method
Mode
Display Arranging Function
Vertical
Pin
VGA
Stretching
Automatic.
Non-VGA
None
_'1
Internal register
Horizontal
Pin
Internal register
Notes:
CRT System
Setting
VGA
Stretching or centering
Automatic '2
Non-VGA
Stretching or centering
Necessary
VGA
Centering
Automatic
Non-VGA
None
_'1
VGA
Centering
Automatic
Non-VGA
Centering
Necessary
1. Display size must be LCD panel size.
2. Either stretching or centering function must be selected by the internal register.
HITACHI
722
Hitachi America, Ltd:- Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD66850F
Display Modes
Display Mode Settings and LCD Module
Configurations: The CLINE supports 20 display
modes, depending on the settings of the LMODE4
to LMODEO pins. The display mode includes
display color mode (color or monochrome), screen
configuration (single or dual), gradation display
method, and width of data transfer to LCD drivers.
Table 9 lists the display modes and figures 4 (a) to
4 (g) show the corresponding LCD module
configurations.
Table 9 Display Modes and LCD Module Configurations
Pln:LMODE
4
3
2
1
0
Display Color Mode
(Gradation DIsplay Method)
Screen
Conflg.
Data
Width
LCD Module
Conflg.
0
0
0
0
0
Monochrome: black and white
Single
4
Fig. 4 (a)
2
0
0
0
0
1
Dual
4
Fig. 4 (b)
3
0
0
0
0
Single
8
Fig. 4 (c)
4
0
0
0
1
Dual
8
Fig. 4 (d)
5
0
0
0
Single
4
Fig. 4 (a)
6
0
0
0
Dual
4
Fig. 4 (b)
7
0
0
1
0
Single
8
Fig. 4 (c)
8
0
0
1
Dual
8
Fig. 4 (d)
9
0
0
0
10
0
0
0
1
Mode
. No.
11
0
0
12
0
0
13
1
0
0
Monochrome: 16 gray levels
(Frame-based data thinning)
Monochrome: 16 gray levels
(112 pulse width modulation)
Single
4
Fig. 4 (a)
Dual
4
Fig. 4 (b)
0
Singale
8
Fig. 4 (c)
1
Dual
8
Fig. 4 (d)
Single
2
Fig. 4 (e)
Single
4
Fig. 4 (f)
0
0
0
0
14
0
0
1
0
15
0
0
1
8 colors
Single
8
Fig. 4 (g)
16
0
0
0
Single
2
Fig. 4 (e)
17
0
0
4096 color levels
(Frame-based data thinning)
Single
4
Fig. 4 (f)
18
0
1
Single
8
Fig. 4 (g)
Sing;le
4
Fig. 4 (f)
Single
8
Fig. 4 (g)
19
0
0
20
0
1
Note:
16 colors
4096 color levels
(112 pulse width modulation)
Modes 15, 18, and 20 are interleaving structure modes.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
723
HD66850F
4~
'---7'-v1
4 bits
~~______H_D6_6_1_06____~
HD66106
I.
[m-mmto&mmnmJ
LCD
4~L
_ _ _ _ _~
~_ _ _HD66106
(b) Dual screen, 4-bit data width
(a) Single screen, 4-bit data width
8 bits
~I~
8~
'---7'-v1
_____
H_D_6_61_o_7____~
HD66107
I.
f------- ----to& -----------J
LCD
8~L.
_ _ _ _ _~
'---7'-v1 _ _ _HD66107
(d) Dual screen, 8-bit data width
(c) Single screen, 8-bit data width
2 bits
4 bits
~§i
;~
Color drivers
=========:
~
I
.
I
Color drivers
=========:
~
LCD
.
(e) Single screen, 2-bit data width, color drivers
LCD
(1) Single screen, 4-bit data width, color drivers
8 bits
~I
HD66107
'--r----V1L.,--,..-.------I
i
RGBRGB
, , ,
1 1 1
: : :
LCI
8~L._____H_D_6_6_10_7___
__J
(g) Single screen, 8-bit data width, interleaving
structure
Figure 4 LCD Module Configurations by Display Modes
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Gradation Level Reduction: Although a CRT
display system can represent infonnation for over
100,000 color levels, an LCD cannot handle so
much information.
The BO pin must be set to I; and the B1 pin to
O. Unused display data input pins must be
fIXed to O. See figure 5 (a).
-
Consequently, CRT color or gradation level
information must be reduced in order for the
CLINE to display it. Reduction methods vary
depending on the input color or gradation level
information, the LCD panel (color or monochrome), and other factors. Table 10 lists
gradation level reduction for CLINE modes, where
, "Input Bits" indicates au display color data and
"Reduced Data" indicates input to the gradation
level palettes.
16-level grayscale input and 16-level
grayscale output (modes 5-12)
Both BO and B1 pins must be set to O. Unused
display data input pins must' be fIXed to O. See
fIgure 5 (b).
• When color LCD panel is used (LMODE4 = 1)
-
64-color input and 16- or 8-color output
(modes13-IS)
Input Display Data Connection: Input display
, data connection and pin settings depend on the
CRT input mode (color or gradation level
information) and the LCD panel used.
Two-bit R, G, and B data must be input to the
R2-R3, 02-03, and B2-B3 pins, respectively.
Unused display data input pins must be fixed
to 0). See figure 6 (a).
• When monochrome LCD panel is used
(LMODE4=O)
- 4096-color input and 4096-color output (modes
16-20) .
- 64-c0lor input and 16-level grayscale output
(modes 5-12)
Four-bit R, 0, and B data must be input to the ROo
R3, 00-03, !lIld BO-B3 pins, respectively. If the
input has more than 4096 colors, use the highorder four bits of each color. See figure 6 (b).
Table 10 Gradation Level Reduction for CLINE Display Modes
Input
Mode
Input Bits
2
1
0
LCD
Panel
Gradation Level
Reduction (BHs)
4096 color
levels
03
02
01
DO
Color
12 -+ 12
2
16 colors
R
G
B
Color
6-+4
2
16 gray levels
03
02
01
DO
Monochrome 6 .... 4
02
01
DO
Monochrome 4-+4
G
B
4096
colors
4
4
4
64
colors
2
2
64
colors
2
2
CLINE Display
Mode
Reduced Data
3
R
16 gray
levels
4
16 gray levels
03
16 gray
levels
4
Monochrome
(black & white)
AliOsorall1s
Monochrome 4 .... 1
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy;· Brisbane, CA 94005-1819· (415) 589-8300
-- -
o
-~~-~
-----
---
725
HD66850F
RO, R1
GO, G1
R2,R3
G2, G3
BO, B1
B2, B3
B1
BO
o
CLINE
~
16-level grayscale
LCD data
(a) 64-c0lor input and 16-level grayscale output
16-level grayscale data
=======01 Go-G3
CLINE
o
o
----~B1
~
r----v
16-level grayscale
LCD data
-----+180
(b) 16-grayscale input and 16-level grayscale output
Figure 5
Input Display Data Connection and Pin Settings when a Monochrome
LCD Panel is Used
HITACHI
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Hitachi America,Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
RO,R1
GO,G1
BO,B1
======~R2, R3
======~G2, G3
======~ B2, B3
CLINE
F==>
Color LCD data
(a) 64-color input and 16- or 8-color output
Ro-R3
======~Ro-R3
Go-G3
Bo-B3
======~Go- G3
======~Bo- B3
CLINE
F==>
Color LCD data
(b) 4096-color input and 4096-color output
Figure 6 Input Display Data Connection and Pin Settings when a Color LCD Panel is Used
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
727
HD66850F
LCD Data Output: The CLINE uses pins
UD7-UDO and LD7-LDO for display data output.
Output data from these pins depend on the display
mode, as shown in table 11. However, data output
timings are basically the same in all display
modes. Display data output timing for modes 15
and 18 (8-bit color data transfer, bidirectional
connection, without pulse width modulation) is
shown in figure 7. Display data output timing for
the LCD display modes with pulse width
modulation is slightly different. This type of
example is shown in figure 8. Figure 8 shows the
display data output timing in mode 10 (1/2 pulse
width modulation, 4-bit monochrome data transfer,
and dual screen configuration).
However, I,.CD lower panel data LD3-LDO are not
shown in the figure.
Tab.le 11 LCD Data Output Pins and Display Data by Display Modes
Monochrome Modes
8-BIt!
Single
Screen
8-BIt!
Dual
Screen
U07
07
U07
R3
R15
G10
B5
U06
06
U06
R2
B15
R9
G4
U05
05
U05
R1
R1
G14
B9
R3
U04
04
U04
RO
RO
R13
G8
B3
4-BltI
Single
Screen
Pin
4-BltI
Dual
Screen
2·Blt
4-Blt
Color Modes
8-Blt
U03
03
U03
03
U03
G3
B13
R7
G2
U02
02
U02
02
U02
G2
G12
B7
R1
U01
01
U01
01
U01
G1
G1
R11
G6
B1
UOO
DO
UOO
DO
UOO
GO
GO
B11
R5
GO
L07
L07
B3
G15
B10
R4
L06
L06
B2
R14
G9
B4
L05
L05
B1
B1
B14
R8
G3
L04
L04
BO
BO
G13
B8
R2
L03
L03
L03
(13)
R12
G7
B2
L02
L02
L02
(12)
B12
R6
G1
L01
L01
L01
(11 )
(11 )
G11
B6
RO
LOO
LOO
LOO
(10)
(10)
R10
G5
BO
Notes:
1.
2.
3.
4.
The left bit corresponds to MSB.
U and L indicate upper panel and lower panel data, respectively.
Data in parentheses are for 16-color display.
- indicates that the corresponding pins are not used; must be left disconnected.
HITACHI
728
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
,
1st
2nd
dot
dot
,
3rd
4th
dot
dot
LCD screen
,,,
,,
,
_ _ _ _ _ _ _ _ _ _ ... .J. .... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ... -'I .. _________ I..... ________ IL. ____ .. ______ .. _________ .. ___ I
I
;
YCL1
XCL1
I
;
:
I
I
;
:
I
~
Jl
Jl
~
CL2
U07
U06
UOS
U04
U03
UD2
UD1
UDO
LD7
L06
LOS
L04
LD3
LD2
LD1
LDO
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Figure 7 Display Data Output Timing in Display Modes Without Pulse Width Modulation
(Modes IS and 18)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
729
HD66850F
In figure 8, data PO-O, P4-0, ... P636-0 make up
the first set of data for one line to be output to
LCD drivers via pin UD3. Likewise, data PO-l,
P4-1, ... P636-1 make up the second set of data.
The combination of the first and second sets of
YCL1
11
XCL1
Jl
data determines the display status as follows: (first
data, second data) = (0, 0): display off; (I, 0): 1/2
pulse width modulation; and (I, 1): display on.
For more details, refer to the Gradation Display
Methods section.
rL
IL
n
CL2
~
UD3
~
X
!]3§:!!
~
UD2
~
X
!]az-!!
~
UD1
~
X
!]38.:!!
~
UDO
~
X
PIlaB:!!
~
r-LJlJL
~
-=:J.
-=:J.
-=:J.
-=:J.
!]3§:1
Pllaz-1
!]38.:1
Plla!1-1
Figure 8 Display Data Output Timing in Display Modes with Pulse Width Modulation
(Mode 10)
HITACHI
730
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Gradation Display Methods
The CLINE supports the frame-based data
thinning method and pulse width modulation
method for gradation display.
Frame-Based Data Thinning Method: In the
frame-based data thinning method, the CLINE
thins out the display data in line or dot units in the
specified frames.
Pulse Width Modulation Method: In the pulse
width modulation method, the CLINE combines
1/2 pulse width modulation and frame-based data
thinning. In this case, data is output from X-drivers
twice in one line-selection period (figure 9).
Consequently, the X-driver latch clock must be
YCL1
n
---J
different from the Y-driver shift clock, and a
conventional LCD module configuration cannot be
used. Therefore, clock XCLI must be supplied to
X-drivers and clock YCLI to Y-drivers (figure
10).
The XCLI period is specified by the gradation
display clock period register (R13 and R14) when
no buffer memory is used in non-VGA modes and
in the internal register programming method.
(Pulse width modulation is unavailable when
buffer memory is not used in non-VGA modes, pin
programming method.) In the other cases, the
register is automatically set, since the YCLI
period is fixed (table 12).
Linen
n
~_----'
Line n + 1
' - - - - _
XCL1
X-driver
input data
Line n
1st data
X-driver
output data
Figure 9 Driver Clock and Display Data Timing for Gradation Display
with Ji2 Pulse Width Modulation
HITACHI
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731
HD66850F
~-------------------------
XCL1
X-drivers
VCl1
LCD module
Figure 10
x- and V-Driver Clock Connection for Pulse Width Modulation Method
Table 12 XCLl Period Setting
Memory Mode
XCLPerlod
Setting
W~h-memory
Half of VCl1 period for 1/2 pulse with
modulation method
Automatic
Half of vel1 period for 112 pulse width
modulation method
Automatic
(See note below)
Conforms to gradation display clock
register (R13, R14) settings
Required (R13, R14)
Without-memory
VGA
Non-VGA
Internal register
programming
Pin programming
Note: Total number of horizontal dots must be 400, 450, 800, or 900 for displaying 320, 360, 640, or 720
dots, respectively.
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Gradation Level Palettes
Gradation display quality depends greatly on LCD
panel characteristics.
Consequently, uniform gradation display may be
impossible for some panels. To accommodate this
situation, the CLINE incorporates a set of
gradation level palettes that can assign any
gradation level to any CRT display color as
desired.
16 levels are available for gradation display using
the frame-based data thinning method and 31
levels using 1/2 pulse width modulation method.
Appropriate levels can be selected for the LCD
panel used.
The R-, G-, and B-palettes are used for color level
display modes, while only the R-palette is used for
16-level grayscale display modes.
In pin programming and MPU programming
methods, these palettes are automatically loaded
after reset with appropriate data for frame-based
data thinning modes and 1/2 pulse width
modulation modes. The automatically set data
cannot be rewritten in the pin programming
method, but can be rewritten, any time after 100
J.1S have elapsed after reset, in MPU programming
method.
By contrast, in the ROM programming method,
these palettes are not automatically set. Thus
writing the necessary data to the palettes is always
required.
Table 13 shows the relationship between the
values set in the palettes (through R12) and
gradation levels. Values other than those shown
here disable correct display.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
733
HD66850F
Table 13 Relationship between Gradation Levels and Palette (R12) Values
(a) Frame-based data thinning modes
(b) 1/2 pulse width modulation modes
Gradation
Level
Palette Data (R12 Data Bits)
1
No.
S
4
3
0
2
Gradatlon
Level
Gradation
Level
Palette Data (R12 Data Bits)
No.
S
4
3
2
1
0
Gradatlon
Level
0
0
0
0
0
0
0.00
0
0
0
0
0
0
0.00
1
0
0
0
0
1
0.14
1
0
0
0
0
1
0.07
2
0
0
0
1
0
1
0
3
0
0
0
1
4
0
0
0
5
0
0
0
1
0.20
2
0
0
0
0.29
3
0
0
0
0.33
4
0
0
1
0
0
0.17
0.40
5
0
0
0
1
0.20
0
0.43
6
0
0
1
0
0.21
1
0.50
7
0
0
1
0.25
0
0.10
0.14
6
0
0
7
0
0
8
0
0
0
0
0.57
8
0
1
0
0
0
0.29
9
0
0
0
1
0.60
9
0
1
0
0
1
0.30
10
0
0
0
0.66
10
0
0
1
0
0.33
11
0
0
1
0.71
11
0
0
12
0
0
0
0.75
12
0
0
13
0
0
0.80
13
0
0
14
0
1
0
0.86
14
0
1
15
0
1
1.00
15
0
0.36
16
0
0
0
17
0
0
0
18
0
0
19
0
0
20
0
1
0
0.38
0.40
0
0.43
1
0.50
0
0.50
0.57
0
0.60
0.64
0
0
0.67
0.71
21
0
0
22
0
1
0
23
0
24
1
0
0
0
25
0
0
1
0.80
26
0
1
0
0.83
27
0
0
0
0.88
28
0.70
0.75
0.79
0.86
29
1
0
1
0.90
30
1
1
0
0.93
1
1.00
31
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Display On/Off Control
When the LCD drivers used have an LCD on/off
control pin, display can be controlled with the
CLINE DISPON signal. When the LCD drivers
used do not have an LCD on/off control pin, the
CLINE can turn off display by transferring all-O
display data to the drivers.
tion (single or dual), data transfer width (bit
count), and gradation display methods. For
example, the data transfer rate will be doubled for
Itl pulse width gradation display. This is because
data must be transferred two times during one lineselection period. The data transfer rate (fcu: CL2
frequency) is calculated from the following
equation (fLooTCK = fDOTCLK for synchronous
mode):
Display will be turned on with the DISPON pin =
1, turns the display off while DISPON = O. The
DISPON pin is equivalent to the DISPON bit (bit
0) of the control register.
In the pin programming method, display is on
except for four frames after reset. The four frame
display-off time period prevents random display at
power-on. In the MPU programming method,
display is turned off at reset, but can be freely
turned on or off after four frames after reset by
rewriting the corresponding register bit. In the
ROM programming method, a 1 must be written to
the DISPON bit to turn on display. Like in other
programming methods, display is off for four
frames after reset.
fCL2 -
fLDOTCKX 1
-':::::"n':"':"":x;.:;m~-
n: Number of panels composing one screen
- 1 for modes 1,3,5,7,9, 11, 13-20
- 2 for modes 2, 4, 6, S, 10, 12
m: Number of bits transferred at one time
- 2 for modes 13, 16
-4 for modes 1,2,5,6,9,10,14,15,17-20
- S for modes 3, 4, 7, 8, 11, 12
I: Constant for each gradation display
- I for modes I-S, 13-IS
-2formodes9-12,19,20
LDOTCK Frequency and Data Transfer Rate
The LOOTCK frequency (fLDOTCIU for asynchronous mode is calculated from the following
equation:
fLDOTCK = (Nhd + 4S) x Nvd x fF
Nhd: Number of dots contained in one
horizontal line of the LCD panel
Nvd: Number of horizontal lines from the LCD
panel top to bottom
fF: Frame frequency
In this case, the following relationship must hold
true:
1/2 X fOOTCLK < fLDOTCK < 2 X fOOTCLK
fOOTCLK: Dot clock frequency
The data transfer rate to LCD drivers depends on
the mode in which the CLINE is used.
Specifically, the rate depends on screen configura-
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
735
HD66850F
Synchronous!Asynchronous Modes and
Memory
The CLINE has two timing modes: asynchronous
and synchronous.
In asynchronous mode, dot clock pulses for the
CRT system (DOTCLK) are different from those
for the LCD system (LDOTCK) in frequency to
accommodate frame frequency conversion. This
requires buffer memory as shown in figure 11 (a).
In this mode, dual screen LCD panels can be used.
In synchronous mode, dot clock pulses for the CRT
system are identical to those for the LCD system,
thus requiring no buffer memory in principle
(synchronous without-memory mode (figure II
(b». However, synchronous without-memory
mode cannot support dual screen LCD panels.
Table 14 summarizes these modes.
~
II Gradation
processing ~
DOTCLK
HD66850
HD66850
HD66850
c RT
The CLINE has another mode in which dual
screen LCD panels can be used and fewer memory
devices are required. This is called "synchronous
with-memory mode" (figure 11 (c». In this mode,
the number of memory devices can be reduced to a
half or a third that of asynchronous mode. This is
because ROB data sent from the CRT system is
processed for gradation display before being
written into buffer memory. (In asynchronous
mode, on the other hand, R, 0, and B data sent
from the CRT system is separately written into the
R-plane, O-plane, and B-plane memories,
respectively.)
T
-
Gradation
processing
I
oOTCLK
LDOTCK
Memory
(a) Asynchronous Mode
H
LC
DOTCLK
Memory
(b) Synchronous WithoutMemory Mode
(c) Synchronous
With-Memory Mode
Figure 11 Signal Flow for Synchronous!Asynchronous With-/without-Memory Modes
HITACHI
736
Hitachi America, Ltd." Hitachi Plaza." 2000 Sierra Point Pkwy." Brisbane, CA 94005-1819" (415) 589-8300
o
HD66850F
The CLINE uses dual port RAMs for buffer
memory. enabling high-speed display and
independent use of an LCD dot clock and a CRT
dot clock.
The ClINE supports three types of memory
configurations: 64k x 4 bits (256 k). 256 k x 4 bits
(1 M). and 128 k x 8 bits (1 M). any of which can
be selected with the MMODEO and MMODEI
pins (table 3).
The number of memory devices required depends
on the LCD panel size and the display mode.
However. it depends only on LCD panel vertical
size and not on horizontal size since the CLINE
uses memory as shown in figure 12. For example.
one 256-kbit memory device is required for the
panel having 256 or less lines and two for that
having 257 to 512 lines. Table 15 lists the number
of memory devices required for each mode.
Table 14 Memory Mode Summary
Asynchronous WlthMemory Mode
Synchronous With·
Memory Mode
Synchronous Without
Memory Mode
Centering/stretching
Possible
Possible
Impossible
Max number of gray levels
16
16
16
Max number of color levels
16
4096 (frame-based
data thinning)
4096 (pulse width
modulation)
Dual screen
Possible
Possible
Impossible
Max number of
display lines
512
512
1024
Frame frequency
conversion
Possible
Impossible
Impossible
r
I
Not
used
256
l
64 k x 4 bit memory
Figure 12 Display Sizes and Memory Area Used
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
737
HD66850F
Table 15 Number or Memory Devices for Different Display modes
Number of Memory Devices Required
Asynchronous
Synchronous
Display Mode
64kx4
256kx4
128kx8
64kx4
256kx4
Monochrome
Modes 1-4
2
1
1
2
1
16-level grayscale
(frame-based)
Modes 5-8
8
4
2
2
16-level grayscale
(112 pulse width)
Modes 9-12
8
4
2
4
2
8-color Mode 15
6
3
2
6
3
2
16-color Modes 13,14
8
4
2
8
4
2
6
3
2
4096-color-scale
(frame-based)
Modes 16-18
128kx8
Frame-based: Frame-based data thinning method
112 pulse width: 112 pulse width modulation method
Note: With-memory mode does not support color level display using the pulse width modulation method.
HITACHI
738
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415)589-8300
HD66850F
Display Timing Signal Fine Adjustment
When the display timing signal is supplied
externally, a phase shift may appear between CRT
data and the display timing signal, since each
signal has its own peculiar lag. The CLINE can
adjust the display timing signal with pins AJ3-AIO
(in pin programming method) or with the input
timing control register (Rl) (in internal register
programming method) to compensate the phase
shift (table 1).
Figure 13 (a) shows an example of adjusting a
display timing signal that is two dots ahead of the
display start position. In this case, pins (AI3, AI2,
AIl, AIO) or data bits (3, i, 1,0) ofRI must be set
to (1, 0, I, 0) to delay the signal for two dots.
Conversely, they must be set to (0,0, 1,0) to
advance the signal for two dots for the case of
figure 13 (b), where the display timing signal is
two dots behind.
When there is no need to adjust the signal, a
setting of either (0, 0, 0, 0) or (I, 0, 0, 0) will
work.
It should be noted that the VGA CRT system
applies the BLANK signal, which includes the
border area period, as the display timing signal,
and that the CLINE removes the border area
period. Consequently, the border area period must
be considered for adjusting the display timing
signal.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
739
HD66850F
~ Display start position
CRT display
data
Display timing
signal before
adjustment
Display timing
signal after
adjustment
X
/
2 dots ahead
~
Fine adjustment
- (1, 0, 1,0)
(a) Delaying Display Timing Signal
Display start position ---..
CRT display
data
Display timing
signal before
adjustment
Display timing
signal after
adjustment
)C
)(
I
2 dots behind
~
Fine adjustment
- (0, 0, 1,0)
(8) Advancing Display Timing Signal
Figure 13 Display Timing Signal Fine Adjustment
HITACHI
740
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
HD66850F
Border Color Control
In the internal register programming method, the
CLINE can specify the color of a blank area that is
left on a centered display (figure 14). Any of 16
colors or the color of the dot immediately before
the valid display data can be specified by the
border color control register (R7). However, the
desired color can be specified only in asynchronous mode.
In the pin programming method, the specified
color is always the same color as the dot
immediately before the valid display data.
Vertical
centering
LCD panel
Figure 14 Border Area and an LCD Panel
I
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
741
HD66850F
Internal Registers
The CLINE has one index register (1R) and 15 data
registers (RO-RI4). In the MPU programming
method, the desired register address must be
written in one cycle into the index register before
writing or reading data to/from the register in the
following cycle. By contrast, in the ROM
programming'method, the index register is not
used; the CLINE automatically reads data from the
ROM, in which data has been written to the ROM
addresses corresponding to the desired data
registers, and writes it to the data register.
Registers are valid only for the internal register
programming method and are invalid (don't care)
for the pin programming method. Since all data
registers are reset to Os, they must be rewritten
after reset.
Register Access for MPU Programming Method
First write the desired data register address into the
index register with ~ = 0, RS = 0, and WR = 0,
then write/read data to/from the register with ~
0, RS 1, and WR
or RD 0. Figure 15
shows the timing for writing data into an internal
register.
=°
=
=
CS,
RS
, ' - -_ _--'
~------------------~--------~
Write (01)H to
the index register.
Write (02)H to
the index register.
Write data to R1
Write data to R2
Figure 15 Internal Register Write by MPU
HITACHI
742
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra POint Pkwy.- Brisbane, CA 94005-1819 - (415) 589-8300
=
HD66850F
ROM Data Setting for ROM Programming
Method
The desired data must have been previously
written to the ROM addresses corresponding to the
data register addresses; that is, to ROM addresses
$OOOO-$OOOF. Data for the gradation level palettes
must have been written to ROM addresses
$OOI0-$003F. Consequently, data written for
internal registers Rll and R12 are invalid. Figure
16 shows the ROM address map.
$0000
$0001
$0002
Internal registers
$0010
$0011
R-palettes
$0020
$0021
G-palettes
$0030
$0031
B-palettes
$0040
Not used
I
$FFFF
Figure 16 ROM Address Map
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
743
HD66850F
Register Function
Index Register (IR): The index register (figure 17),
composed of four valid bits, selects one of the 15
data registers. The index register itself is selected
by the MPU while the RS signal is low and selects
a data register with the register address written.
and STE bits are set to 1 at the same time, correct
display will be disabled.
•
CCE bit
- CCE = 1: Horizontal centering function
enabled
- CCE = 0: Horizontal entering function
disabled
•
SPbit
- SP 1: Double-width display
- SP = 0: Normal display
•
DISPONbit
- DISPON 1: Display on
- DISPON = 0: Display off
Control Register (RO): The control register (figure
18) is composed of five valid bits, each with a
particular function.
•
STE bit
- STE =1: Stretching function enabled
- STE =0: Stretching function disabled
•
CRE bit
- CRE = I: Vertical centering function
enabled
- CRE 0: Vertical centering function
disabled
=
=
=
DISPON is always cleared at reset. In the MPU
programming method, rewriting this bit can
always be rewritten. However, display will be off
for four frames after reset, regardless of the status
of this bit
Simultaneous use of stretching and vertical
centering functions is impossible; if both the CRE
IR
/
Data bit
7
6
5
4
Value
-
-
-
-
3
I
-
2
I
1
I
\
0
Register address
Figure 17 Index Register
RO
\
/
Data bit
7
6
5
4
Function
-
-
-
SrE
3
2
CRE CCE
1
0
SP
DISP
ON
Figure 18 Control Register
HITACHI
744
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66850F
Input Timing Control Register: The input
timing control register (figure 19) has five valid
bits, having two different functions.
•
•
DOTE bit : Switches ROB data latch timing.
- DOTE 1: Latches data at the rising edge
of the dot clock pulses
- DOTE 0: Latches data at the falling edge
of the dot clock pulses
=
=
AJ3-AJO bits: Adjust the externally supplied
display timing signal to synchronize its phase
with that of LCD data. Write the shift,
represented in dots, between the display timing
signal and the display start position to these
bits. The absolute value of the number of dots
to be shifted must be written to the AJ2-AJO
bits and shift polarity to the AJ3 bit. If there is
no need to adjust the display timing signal,
these bits may be set to either (1, 0, 0, 0) or (0,
0,0,0).
R1
\
/
Data bit
7
6
5
4
3
2
1
0
Value
-
-
-
DOTE
AJ3
AJ2
AJ1
AJO
/
/
3
2
1
0
0
0
0
0
0
0
1
-1
0
1
0
-2
0
0
0
0
0
0
1
+1
0
1
0
+2
0
1
1
+3
1
0
0
+4
1
0
1
+5
1
1
0
+6
1
Number of Dots
Adjusted
0
Note: - (minus) and + (plus) in the Number of Dots Adjusted column indicate advancing and delaying
the display timing signal, respectively.
Figure 19 Input Timing Control Rc:gister
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
745
HD66850F
Horizontal Display Size Register: The horizontal display size register (figure 20), composed
of seven valid bits, specifies the horizontal display
size in units of characters (eight dots). The value
to write to this register is "number of characters
displayed on one horizontal line - 1." A
maximum of 90 characters (720 dots) can be
specified.
This register is set automatically in VGA mode.
Vertical Display Size Register: The vertical
display size register (figure 21), composed of nine
valid bits, specifies the vertical display size in
units of lines. The value to write to this register is
"number of lines displayed from display screen
top to bottom - I." A maximum of 512 lines can
be specified.
This register is set automatically in VGA mode.
R2
\
/
Data bit
7
-
Value
6
5
4
3
2
1
0
DH6
DH5
DH4
DH3
DH2
DH1
DHO
Figure 20 Horizontal Display Size Register
R3
/
\
I I •I I I I I I
7
Data bit
Value
5
4
3
2
7
6
5
4
3
2
1
0
DV7
DV6
DV5
DV4
DV3
DV2
DV1
DVO
\'-----~------'/
R4
Figure 21 Vertical Display Size Register
HITACHI
746
Hitachi America, Ltd.' Hitachi Plaza 02000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66850F
Centering Raster Register: The centering raster
register (figure 22), composed of eight bits,
specifies the number of rasters for vertically
centering the display within the range of 1 to 256.
The value to write to this register is "number of
rasters for centering - 1." As shown in figure 23,
the number here indicates the number of rasters in
either the upper border area or lower border area, not
the total number. Since the LCD panel size is
detennined by this number and the display size, the
number of rasters must be correctly written if the
display size differs from the LCD panel size.
Incorrect setting disables correct display. This
register is enabled the control register's CRE bit is 1.
This register is set automatically in VGA mode.
R5
\
/
Data bit
Value
7
6
5
4
3
2
1
0
. CR7
CR6
CR5
CR4
CR3
CR2
CRr
CRO
Figure 22 Centering Raster Register
Border area
(upper)
Number of rasters
(upper)
Display
Number of rasters
(lower)
Border area
(lower)
Figure 23 Centering Rasters
I
HITACHI
Hitachi America, Ltd." Hitachi Plaza" 2000 Sierra Point Pkwy. "Brisbane, CA 94005-1819" (415) 589-8300
747
HD66850F
or right border area, not the total number. Since
the LCD panel size is determined by this number
and the display size, the number of characters must
be correctly written when the display size differs
from the LCD panel size. Incorrect setting
disables correct display. This register is enabled
when the control register's CCE bit is 1.
This register is set automatically in VGA mode.
Centering Character Register: The centering
character register (figure 24), composed of five
valid bits, specifies the number of characters for
horizontally centering the display within the range
of 1 to 32. The value to write to this register is
"number of characters for centering - 1." As
shown in figure 25, the number here indicates the
number of characters in either the left border area
R6
\
/
Data bit
7
6
5
Value
-
-
-
4
CC4
3
2
1
0
CC3
CC2
CC1
cco
Figure 24 Centering Character Register
Number of characters
(left)
Border area
(left)
Border area
(right)
Figure 2S Centering Characters
HITACHI
748
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Border Color Control Register: The border
color control register (figure 26), has five valid
bite having two different functions. These
functions are available only in with-memory
mode.
•
•
Stretching Control Register: The stretching
control register (figure 27), composed of four valid
bits, is used in combination with the stretching
index register (R9 and RIO). It specifies the
period for stretching in units of lines. The value to
write to this register is "number of lines -1." This
register is enabled when the control register's S1E
bit is 1.
This register is set automatically in VGA mode.
BM bit: Specifies border control mode; reset to
O. This bit must be 1 in asynchronous mode.
- BM = 1: Displays the color specified by the
BCI, BCR, BCG, and BCB bits in the
border area (disabled in synchronous mode)
-
BCI, BCR, BCG, and BCB bits: Specify the
color to be displayed on the border area. These
bits are enabled when the BM bit is 1; reset to
Os.
BM = 0: Displays the color of the dot
immediately before .the display period on
the border area
R7
\
/
Data bit
7
6
5
4
3
Value
-
-
-
BM
BCI
2
1
BCR BCG
0
BCB
Figure 26 Border Color Control Register
/
RS
\
IData blt
Value
Figure 27 Stretching Control Register
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
749
HD66850F
be displayed twice. Although this register has 16
bits, only the bits within the period specified by
R8 are enabled. For example, when R8 is set to
four, only five bits of SIO to SI4 of this register are
enabled (figure 29).
This register is set automatically in VGA mode.
Stretching Index Register: The stretching index
register (figure 28), composed of 16 valid bits, is
used in combination with the stretching control
register (R8). It specifies the lines to be displayed
twice among those specified by R8. The lines
represented by the SI bits which are set to Is will
R9
I
\
Data bit
, Value
7
6
5
4
3
2
1
0
SI15
SI14
SI13
SI12
Sill
SilO
SI9
SI8
7
6
5
4
3
2
1
0
SI7
SI6
SI5
SI4
SI3
SI2
Sil
SIO
Data bit
Value
\~----------------~/
Rl0
Figure 28 Stretching Index Register
R9! Rl0}
Stretching
period
(R8.4)
SIO.O
____l,Ln!~ ___ _
____Lln!~ __ _
S11.l
___ .,.I·l!'!!L __ _
_ ___Lln!~ __ _
SI2 .1
____Lln!!L __
SI3 .0
Line C
---------____Li..!'!!L __
SI4.0
Line E
SIO.O
____lJ.n!.E __ _
S11.l
___ J..!!'!~L __
____L.!!1!Q __ _
~ ====;~===
____Lln!.E ___ _
----------Figure 29 Stretching Display
HITACHI
750
Hitachi America, Ltd.· Hitachi Plaza. 2000 SierraPoint Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Gradation Level Palette Address Register: The
gradation level palette address register (figure 30)
is composed of six valid bits with two different
functions.
•
PA3-PAO bits: Specify the desired gradation
level palette using the address written to these
bits. After palette address specification, data is
read from or written to the specified palette and
the address is automatically incremented by 1.
The address increment manner depends on PS 1
and PSO settings.
•
PS 1 and FSO bits: Specify a method of
selecting the plane of the gradation level
palettes (R, G, or B).
-
- (pSI, PSO) = (0, 0): Gradation level palette
address is automatically incremented by 1
after reading/writing data from/to R, G, and
B gradation level palettes in that order,
through the gradation level palette data
register
(PS 1, PSO) = (0, 0): Every time the
gradation level palette data register (R12) is
read from or written to, either R-, G-, or Bpalette is automatically selected, in that
order
- (pS 1, PSO) = (0, 1): R-palette is selected
-Other settings: Gradatiol'l level palette
address is automatically incremented by 1
after reading/writing data from/to anyone
gradation level palette, through the
gradation level palette data register
- (pS 1, PSO) = (1,0): G-palette is selected
- (pS 1, PSO) = (1, 1): B-palette is selected
R11
\
I
Data bit
7
6
5
4
3
2
1
0
Value
-
-
PS1
PSO
PA3
PA2
PA1
PAO
Figure 30 Gradation Level Palette Address Register
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
751
HD66850F
Gradation Level Palette Data Register: The
gradation level palette data register (figure 31),
composed of six valid bits, contains data which is
read from or written to the gradation level palette
specified with the gradation level palette address
register (RU).
have elapsed after reset. Note that display is
scattered dming palette read/write.
In the MPU programming method, gradation level
palettes are not directly read from, but are read
from via this register. Consequently, any data that
happens to be in this register at that time is read
out in the first read cycle, and then data
corresponding to the specified address is
transferred to this register and read from this
register in the following read cycle. The address is
incremented (or R-, G-, and B-palettes are
switched) at the same time. In other words, after
addreSs setting, the first data read is incorrect, and
the second data read is correct Consequently, one
dummy read is required after setting a gradation
level palette address. Figure 32 shows the timing
for reading a gradation level palette.
Gradation level palettes must be set according to
the display mode used (16-level grayscale display
or 4096-color-scale display); the R-palette must be
used for 16-level grayscale display, and R-, G-,
and B-palettes for 4096-color-scale display. PD5
bit must be 1 and PD4 bit must be 0 in framebased data thinning mode. PD4 bit must be 1 in
1/2 pulse width modulation mode. Show table 13.
In the MPU programming method, the gradation
level palettes must be read/written after 100 ms
R12
\
/
Data bit
7
6
5
4
3
2
1
0
Value
-
-
PD5
PD4
PD3
PD2
PD1
PDO
Figure 31 Gradation Level Palette Data Register
(N+2)
(N+ 1)
00-07
Address
Gradation level
palette data register
•
X
N
•
X
•
X
X
N+1
X N+2 XN+3 )C
(N)
X
(N+1)
X
(N+2)
)C
(N): Data for address N
Figure 32 Gradation Level Palette Data Read
HITACHI
752
Hitachi America, Ltd .•. Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66850F
Gradation Display Clock Period Register: The
gradation display clock period register (figure 33),
composed of nine valid bits, specifies the period of
XCLl, the LCD data latch clock, when pulse
width modulation method is used for gradation
display. The value to write to this register is
"specified number - l,~ in units of dots. Eight
through 512 dots can be specifIed. Note that this
register is invalid in with-memory mode.
This register is set automatically in VGA mode.
• GC8-GCO bits: Specify the number of dots for
Tl; Tl is the period of XCLl for III pulse
width gradation display. When the total
number of dots for one period of the YCLI
clock pulse cannot be divided by two for III
pulse width gradation display, the remainder is
added to T1 as Tl', where Tl' TL - T1
(flgUre 34).
=
R13
I
Data bit
Value
\
7
6
5
4
3
2
1
0
GC7
GC6
GCS
GC4
GC3
GC2
GC1
GCO
\~--------~------~I
R14
Figure 33 Gradation Display Clock Period Register
YCL1
J1~L..E=================_T_L_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~r=L-+I
...J~E----...,.- T1'
XCL1~
---:j-*"E- - - - T1 ---:j--+t
I'-----------'n<---_IL
(112 pulse width)
Figure 34 T.., Tl, and T'
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
753
-"--"-""" -""-" - - - - - - - - - - - - - - - - ---------"""--""-"
"
"-~~----"-"---"---"-"-""--
HD66850F
Reset Description
The RES signal resets and starts the CLINE. The
RES signal must be supplied at each power-on.
Reset is defined as shown in figure 35.
•
Pin: In principle, the RES signal does not control
output signals and it operates regardless of other
input signals. The reset states of input/output pins
are described below.
Registers: The contents of all internal registers are
lost and cleared; the desired data must be rewritten
after reset.
•
DO-D7: Not affected by reset. These pins
output data even during the reset state when
RD = 0, CS = 0, RS = 1, and WR = 1, in the
MPU programming method.
o.s
AO-A5: Always output Os during the reset state
in the ROM programming method. Otherwise,
these pins serve as input pins.
Palettes: Palettes are automatically loaded after
reset with the appropriate data according to the
display mode. When data different from the
automatically set data is needed, the data must be
overwritten 100 J.1S or more after reset. (100 J.1S is
required for automatic data setting.)
~ '\:
/Vo.s V
~----------------/
Reset state
After reset
Figure35 Reset Definition
HITACHI
754
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
HD66850F
There are some restrictions and notices in the
HD66850F. Please check the following content,
and use it.
Input Signal Timing
HSYNC, VSYNC Asserted Width: The HSYNC
and VSYNC input signals have the minimum
asserted width to operate correctly, please keep the
asserted width with the below value or more.
HSYNC to VSYNC, HSYNC to BLANK Phase
Shift: There are some restrictions between
HSYNC and VSYNC, and HSYNC and BLANK.
Don't input them within the restricted phase shift.
Table 16 HSYNC, VSYNC Asserted Width
Condition
Item
Symbol
Minimum Dots
All mode
Asserted HSYNC
a
12 dots or more
Asserted VSYNC
b
2 rasters or mode
Table 17 VSYNC, BLANK Phase Shift
Condition
Item
Symbol
Available Dots
All mode
VSYNC
c
3 dots or less, 16 dots or
more
BLANK
d
1 dot or more
Note: In VGA mode, the polarities of HSYNC and VSYNC depend on the display resolution on CRT, but
we will explain them as the active-high input in this document.
+ll+a
HSYNC
VSYNC
J1,-----!n
n
fL
~b---+lL
_ _--'1- .
Figure 36 HSYNC, VSYNC Asserted Width
HSYNC
n...
!--_ _ _ _ _
VSYNC
BLANK
Figure 37 VSYNC, BLANK Phase Shift
HITACHI
Hitachi America, Ltd. -Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
755
HD66850F
Total Horizontal Dots: HD66850F needs 48 dots
for the horizontal retrace period. and the HSYNC
period must be 688 dots or more when 640 dots
display. 768 dots or more when 7'lJJ dots display.
Horizontal Front Porch: There is a restriction
about the horizontal front porch (from negated
BLANK to asserted HSYNC) as the below in
VGA mode. Please input them with the minimum
value or more. Especially in 320 or 360 dots wide.
period of the front porch is usually just 3 or 4 dots.
Please delay HSYNC asserted timing. and hold the
minimum value. Otherwise the first line on a panel
will be incorrect.
Table 18 Total Horizontal Dots
Condition
Symbol
All mode
e
Minimum Dots
688 dots. (when 640 dots display)
768 dots. (when 720 dots display)
Table 19 Horizontal Front Porch
Dot Adjust
Condition
Symbol
VGAmode
f
Horizontal 320 or
1 dot or more
3 dots or more
640 dots display
Horizontal 360 or
720 dots display
1 dot or more
7 dots
or
more
5 dots or more
Note: The BLANK 'High' width (g) must be 328 or 336 dots in 320 dots display, 376 dots in 360 dots
display, 656 dots in 640 dots display, and 738 dots display in 720 dots display.
~I(--- e --~)I
HSYNC
Jl'--_____~
Figure 38 Total Horizontal Dots
Figure 39 Horizontal Front Porch
HITACHI
756
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
When it displays 720 dots wide (text mode) on
640 dots panel in VGA mode, HD66850F removes
1 dot from each 9 dots. It may not display
correctly according to the combination of the dot
ajust and the period from negated BLANK to
asserted HSYNC (h in figure 4). In this case,
please change the dot adjust, or delay asserted
timing of HSYNC.
This restriction causes trouble when the below
equation is satisfied. When the total horizontal dot
is 900 dots wide, and the period between negated
BLANK to asserted HSYNC is 'h' dots,
4 x [(h - 2)/4 i] =9 x M + A
(i: revaluation, M and A: integer)
The 'A' which causes trouble depends on the dot
ajust as below.
Table 20 Display Period + Horizontal Front Porch
Dot Adjust
Condition
Symbol
-1
±O
+1
+2
+3
+4
+5
+6
NG ok
ok
ok
ok
NG ok
ok
ok
747 to 750 dots
NG ok
ok
ok
NG ok
ok
ok
ok
751 to 754 dots
ok
ok
ok
ok
NG ok
ok
ok
NG
755 to 758 dots
ok
ok
ok
NG ok
ok
ok
ok
NG
759 to 762 dots
ok
ok
ok
NG ok
ok
ok
NG ok
763 to 766 dots
ok
ok
NG ok
ok
ok
ok
NG ok
743 to 764 dots
ok
NG ok
ok
ok
ok
NG ok
747 to 750 dots
ok
NG ok
ok
ok
NG ok
751 to 754 dots
NG ok
ok
ok
ok
NG ok
755 to 758 dots
NG ok
ok
ok
NG ok
ok
NG ok
ok
ok
NG
ok
ok
NG
-2
Item
Monochrome
or 8/16 colors
mode
VGA mode h
& with
buffer
memory
mode, 720
dots display
on 640 dots
panel
64/512/4096
colors mode
743 to 746 dots
759 to 762 dots
ok
ok
ok
ok
763 to 766 dots
ok
ok
ok
NG ok
ok
ok
ok
ok
ok
ok
ok
ok
NGte: The total horizontal dot must be 900 dots wide.
Dot Adjust
Parameter
Item
A
Monochrome or 8/16
colors mode
64/51214096 colors
mode
-2
6
-1
±O
+1
+2
+3
+4
+5
+6
2
3
4
5
6
7
8
0
7
8
0
1
2
3
4
5
2
3
4
5
6
7
8
7
8
0
2
3
4
0
5
6
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
757
I
HD66850F
Automatic Judgement of VGA Display
Resolution: In VGA mode, HD66850 judges ~
current display resolution from the polarities of
Table 21
VSYNC, and HSYNC, and the width of BLANK
'H' automatically. Please input these signals as
below to judge the correct resolution.
BLANK 'High' Level Width
Condition
Symbol
VGAmode
j
VGA Mode No.
Horizontal Resolution
lii:ANR H Width
011
360 wide
378 dots
213,7
720 wide
738 dots
415
320 wide
336 dots
6, F, 10, 11, 12
640 wide
656 dots
13 (256 col)
320 wide
328 dots
Table 22 Polarities of HSYNC and VSYNC
Condition
VGAmode
VGA Mode No.
Vertical Resolution
HSYNC
VSYNC
F,10
350 raster high
Positive
Negative
011,213,415,6,7,13
400 raster high
Negative
Positive
11,12
480 raster high
Negative
Negative
L
Figure 40
BLANK High Level Width
HITACHI
758
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Border Area: In VGA mode, there is border area
around display area. When the border and display
area is scanned, BLANK is 'high' level. HD66850
internally generates the display timing which
indicates just the display area from BLANK input
So, please input the BLANK with the horizontal
border dot wide and vertical border high raster as
below.
Table 23 Number or Horizontal Border Dot
Condition
Symbol
VGAModeNo.
Resolution
Border
VGAmode
k
0/1
360
9 dots
213,7
720
9 dots
4/5
320
8 dots
6, F, 10, 11, 12
640
8 dots
13 (256 col)
320
4 dots
Table 24 Number or Vertical Border Raster
Condition
Symbol
VGA Mode No.
Resolution
Border
VGAmode
m
F,10
350
6 rasters
0/1,213,415,6,7,13
400
7 rasters
11,12
480
8 rasters
Border
Border
.,k~isplaY-+l
BLANK
-.J
L
Figure 41 Number or Horizontal Border Dot
HSYNC
BLANK
Figure 42 Number or Vertical Border Raster
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
759
HD66850F
When 64 k x 4 bit (256 k) or 128 k x 8 (1M) bit
memory is attached for buffer memory, please
satisfy the below relationship about vertical
display and border raster.
Usually, the vertical 480 rasters mode (VGA mode
11, 12) has 6 or 7 border rasters, so this limitation
will be no problem.
]+[ Vertical border ] S 512
[Vertical
display raster
raster after display
raster
Table 25 Vertical Display Raster + Vertical Border Raster After Display
Condition
Symbol
Vertical Display Raster +
Vertical Border Raster after Display
VGA and with memory mode
n
512 rasters or less
VSYNC
BLANK
Figure 43 Vertical Display Raster
HITACHI
760
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Asynchronous~ode
In asynchronous mode, the set data in the
gradation palette is broken owing to the dot adjust
during display. To avoid this problem, in MPU and
ROM programming method, please write '1' to bit
4 (BM mode) of the border control register (R7),
and all '0' to bit 3-0 (border color) of R7. The
register R7 must be '10H'. In pin programming
method, please adjust display timing with AJ3-
AJO pins, and start to display just from left edge
on an LCD panel without border dot, rise the
BLANK input at same OOTCLK edge as change
of the video data (RIG{B).
In 8/16 colors mode, this restriction is no problem
in any mode because HD66850F does not access
the gradation palette. In 64/ 512/4096 colors
mode, it does not support asynchronous mode.
same edge for DOTCLK
DOTCLK
BLANK
RlGIB
Figure 44 Countermeasure in the Pin Programming ~ethod
HITACHI
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761
HD66850F
Frame Period
In synchronous with-memory mode, DOTCLK
and !tame period for CRT are same as one for
LCD. When it displays on a full screen with
stretching or centering function, HD66850F needs
to extend the frame period for displaying on LCD.
If this frame period for LCD were longer than one
for CRT, HD66850F can not work correctly.
HD66850F needs 48 dots period for the horizontal
retrace, and number of the total horizontal dot for
LCD is number of the horizontal display dot + 48
dots. This minimum frame period which is
necessary to display on LCD is shown as below.
~imum frame = (~umber of horizontal + 48)
penod for LCD
display dot
x Vertical panel size [dotsJ
The frame period for CRT must be longer than the
above minimum one for LCD.
For example, when HD66850F stretchs CRT
resolution with 640 x 350 dots to the LCD panel
with 640 x 480 dots, the minimum frame period
for LCD is (640 + 48) x 480 = 330, 240 dots.
On the other hand, when number of the total
horizontal dot for CRT is 800 dots wide, 330,
240/800 = 412.8 rasters, so HD66850F needs 413
or more rasters high as the total vertical raster for
CRT.
In asynchronous mode, HD66850F separates LCD
clock (LOOTCK) from CRT clock (OOTCK), and
the both frame period are different. So, this
limitation is no problem.
LCD Alternating Signal M
When LCD alternating signal M is changed at
same line in each frame, brightness of the line
differs from one of another line. To avoid this
problem, the signal M is ususally controlled to
change at different line in each frame. But period
of the signal M may synchronize with the frame
period according to the total vertical mster. In this
case, adjust period of the M, and don't synchronize
them.
Especially, it is easy to synchronize them in VGA
720 x 400 dots mode. For example, when it
displays 720 x 400 dots in synchronous withmemory mode, usaually number of the total
horizontal dot for CRT is 900 dots wide, and
number of the total vertical raster is 448 rasters
high, so the frame period for CRT is 900 x 448 =
403,200 [dotsJ. On the other hand, number of the
total horizontal dot for LCD is 720 + 48 = 768
dots wide,and the frame period (403,200 dots)
divided by a total horizontal dot for LCD (766
dots) is 512 which is interger. So, when line
number of period of the M equals to the following
divisor of 512:
[1,3,5,7, 15,21,25,35,75,105, 175J (lines),
period of the M synchronizes with the frame
period, and a horizontal bright line is appeared
when the M is changed.
Vertical Centering
Number of vertical centering line depends on 'the
value in register (R5) + l' in non-VGA mode, or
on the VSIZE pin and display resolution in VGA
mode. But when '0' is written in the register (R5)
and the vertical centering is enabled, HD66850F
can not works correctly. Don't set '0' in the register
(R5). And when number of vertical display raster
is same as the vertical panel size (VSIZE), the,
vertical centering enable bit (bit 3 in RO) must be
cleared. Especially in VGA mode, please update
the enable bit according to selected VGA display
mode.
When stretching function is selected, there is no
restriction about setting '0' in the stretching
registers (R8, R9, RIO).
HITACHI
762
Hitachi America, Ltd.· HitaChi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Table 26 Notes on VGA Mode Usage by LCD Panel Size
Horizontal
Size (dot.)
Vertical
Size (line.)
Nota.
640
• In VGA text modes (0/1, 213, 7), there is no space between characters.
720
• In VGA graphic modes (415, 6, F, 10, 11, 12, 13), horizontal cantering is
necessary. (Display is automatically cantered horizontally in withmemory mode. See note below.)
400
• Data on line 401 through line 480 in VGA 640-by-480 graphic modes
(11,12) are not displayed.
• Vertical centering or stretching is necessary for VGA 640-by-350 graphic
modes (F, 10). (Display is automatically stretched in with-memory mode.
See note below.)
480
• Vertical centering or stretching is necessary for VGA text modes
(0/1, 213, 7). (Display is automatically stretched in with-memory mode.
See note below.)
• Vertical cantering or stretching is necessary for VGA 640-by-200 or
320-by-200 graphic modes (415, 6, 13). (Display is automatically
stretched in with-memory mode. See note below.)
• Vertical centering or stretching is necessary for VGA 640-by-350 graphic
modes (F, 10). (Display is automatically stretched in with-memory mod••
See note below.)
Note: For without-memory mode, external circuits or BIOS tuning are required.
I
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
763
HD66850F
Table 27 Notes on Internal Register Settings
Notes
Non-VGA
Register
No_
Bits
Register or Bit Function
RO
STE
Stretching enable
RO
CRE
Vertical centering enable
2
2
RO
CCE
Horizontal centering enable
3
4
RO
SP
Double-width display set
5
4
RO
DISPON
Display on
6
6
Rl
DOTE
Dot clock phase select
4
4
Rl
AJ3-AJO
Display timing adjust
4
4
VGA
1
R2
DH6-DHO
Display horizontal size set
7
4
R3-R4
DV8-DVO
Display vertical size set
8
4
Rs
CR7-CRO
Centering raster set
8
4
R6
CC4-CCO
Centering character set
3
4
R7
BM
Border control mode select
9
9
R7
BCI, BCR, BCG, BCB
Border color select
10
10
R8
SF3-SFO
Stretching period
8
4
11
11
7
12
R9-Rl0
SI1~IO
Stretching index set
Rll
PS1-PSO
Gradation display palette select
Rll
PA3-PAO
Gradation display palette address set
R12
PDS-PDO
Gradation level palette data set
GC8-GCO
Gradation display clock period set
Rl3-R14
Notes:
Simultaneous use with vertical centering function is impossible.
Simultaneous use with stretching function is impossible.
Automatically set for a 640- or 320-dot-wide display on a 720-dot-wide LCD panel; cannot be
rewritten.
4. Must be set after reset.
5. Automatically set for a middle-resolution display; cannot be rewritten.
6. Display will turn on four frames after reset. Display will not turn on during four frames after
reset.
7. Automatically set a~rding to the horizontal panel size and number of displayed hOrizontal
dots; cannot be rewritten.
8. Automatically set aCcording to the vertical panel size and polarity of HSYNC and VSYNC
signals; cannot be rewritten.
9. Available only.in with-memory mode.
10. Available only in asynchronous with-memory mode.
11. In the MPU programming method, automatically set for 16-level display after reset; can be
rewritten 100 ~ after reset. In ROM programming method, appropriate data must be written.
12. In with-memory mode, automatically set according to the horizontal panel size and number of
displayed horizontal dots; cannot be rewritten. For without-memory mode, appropriate data
must be written after reset.
1.
2.
3.
HITACHI
764
Hitachi America, Ltd.· Hitaohl Plaza· 2000 Slerra~Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
Table 28 Limits on Register Values
Register Function
Applied to .
LImits
Horizontal display
size control
R2
4 s Nchd s (R2 + 1) s 90 (HSIZE. 1)
4S Nchd s (R2 + 1) s 80 (HSIZE. 0)
Vertical display
size control
R3. R4
4S Ncvd S (R3. R4+ 1) S512
Vertical centering
R3. R4. R5
2s(R5+1)S256
(AS + 1) x 2 + Ncvd • (R3. R4 + 1)
Horizontal centering
R2. R6
2S(R6+1)S32
(R6+ 1)x2 + Nchd. (R2+1)
Gradation display
clock period control
R13. R14
(R13. R14 + 1). (Ncht x 8Vn (MMODE1 .1)
n: 2 for 112 pulse width gradation display
(R2 + 1) + 8 S Ncht (NMODE1 .0)
Miscellaneous
R2. R3. R4
112fOOTClK S {(R + 1) + 6} x 8 x
(R3. R4 + 1) x fFlM S 2fOOTCLK
(SYNC .0)
Ncht:
Total number of characters on a CRT horizontal line
(total number of dots on a CRT horizontal line x 1/8)
Number of characters displayed on a CRT horizontal line
Nchd:
(number of dots displayed on a CRT horizontal line x 1/8)
Number of lines displayed from screen top to bottom on the CRT display
Ncvd:
f LDOTCK: LCD dot clock frequency
fDOTCLK: CRT dot clock frequency
Frame frequency
fFLM:
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Power supply voltage
Vee
-0.3 to 7.0
V
Input voltage
Vin
-0.3 to Vee + 0.3
V
Operating temperature
T!1I!r
-20 to +75
°C
Storage temperature
-55 to +125
°C
Tali
Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded.
Normal operation should be under recommended operating conditions (Vee. 5.0 ± 10%.
GND _ OV. Ta _ -20°C to +75°C. (H these conditions are exceeded. LSI reliability may be
affeeled.
2. AU voltages are referenced to GND • 0 V.
HITACHI
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765
HD66850F
Electrical Characteristics
DC Characteristics (Vee = 5.0 V ± 10%, GND = 0 V, Ta = -20 to +7SOC, unless otherwise specified)
Hem
Symbol
Input highlevel
voltage
RES pin
VIH
OOTEIRO/AS, SPIWRlA4
Other input pins'1
Input low-level
voltage
Min
TTL interface pins'2
Vee -0.5
V
V
Output Iowlevel voltage
TTL interface pins'2
CMOS interface pins's
0.&
2.4
CMOS interface pins'S
Three-state leakage current
In.
IrSL
Current consumption
lee
Input leakage current
V
V
IoH--200~
V
IOH--200~
0.4
V
Ia... -1.6 mA
1oL-200~
Vc6-o.&
Va...
Test Condition
V
2.0
VQi
Unit
2.2
VII.
Output highlevel voltage
Max
0.&
V
-2.5
+2.5
~
-10.0
10.0
~
100
mA
Output pins open
Notes: 1. Other input pins: DOTClK, HSYNC, VSYNC, BLANK, MSo-MS15, lDOTCK, 00-07,
AJ3/cS/A3, AJ2IRS/A2, AJ1/A1, AJO/AO, R0-R3, Go-G3, B0-83, PMOOE1, PMOOEO,
lMOOEO-lMOOE4, MMOOE1, MMOOEO, SYNC, VMOOE, VSIZE, HSIZE, TEST1, TESTO
2. TTL interface output pins: 00-07, DOTEIRO/AS, SPIWRlM, AJ3/CS/A3, AJ2IRS/A2, AJ1/A1,
AJO/AO, MOo-M015, MAo-MA7, MA&ISOE1, SOEO, WE, OTIOE, RAS1, RASO, CAS, CASl,
SC
3. CMOS interface output pins: UOO-U07, lOO-l07, XCl1, YCl1, CL2, FLM, M, SCLK, OISPON,
OATAE
HITACHI
766
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point PkwY.· Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
AC Characteristics (Vee =S.O V ± 10%, GND =0 V, Ta =-10 to +7SoC, unless otherwise specified)
Video interface
No.
Item
Symbol
Min
Max
Unit
Reference
62.5
ns
Figure 45
1
DOTCLK cycle time
TCYCD
31.2
2
DOTCLK low-level pulse width
tWOL
15
3
DOTCLK high-level pulse width
tWOH
15
4
DOTCLK rise time
tor
ns
ns
5
ns
5
ns
5
DOTCLK fall time
tor
6
Video data setup time
tvos
10
ns
7
Video data hold time
tVOH
10
ns
8
BLANK setup time
tBLs
10
ns
9
BLANK hold time
tBLH
10
.ns
10
BLANK low-level pulse width
~w
12
~
11
BLANK phase shift
~PD
2Tc
ns
12
Phase shift setup time
tPDS
2Tc
ns
13
Phase shift hold time
tPOH
2Tc
ns
Tc: DOTCLK cycle time
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
767
HD66850F
DOTCLK
Ro-R3
GO-G3
80-83
HSYNC
VSYNC
~
-:1,/'o.SV
---I-E-'::®=--1
~2~.O~V~---------------------~----~o~.S~V~
_______________________________
\'-----
HSYNC
VSYNC
Figure 45 Video Interface
HITACHI
768
Hitachi America, Ltd. - Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD66850F
Memory interface
Max
No.
Item
Symbol
Min
14
RAS cycle time
tAC
12Tc-10
15
RAS low-level pulse width
tRAS
5Tc
16
RAS high-level pulse width
tRP
4Tc-40
17
CAS hold time
tcSH
6Tc-50
ns
18
RAS, CAS delay time
tReD
3Tc-40
ns
19
CAS low-level pulse width
teAs1
3Tc-35
ns
20
CASL low-level pulse width
tcAS2
2Tc-30
ns
tcP1
1Tc-20
ns
tcP2
tpc
2Tc-20
ns
4Tc-20
ns
ns
128Tc-20
Unit
Reference
ns
Figure 46
ns
ns
21
CAS high-level pulse width
22
CASL high-level pulse width
23
CAS cycle time
24
RAS hold time
tRSH
4Tc-40
25
Row address setup time
tASR
2Tc-50
ns
26
Row address hold time
tRAH
2Tc-30
ns
27
Column address setup time
tASC
1Tc-30
ns
28
Column address hold time
tcAH
2Tc-40
ns
29
WE setup time
tws
2Tc-50
ns
30
WE hold time
tWH
2Tc-40
ns
31
Memory data setup time
~
1Tc-30
ns
32
Memory data hold time
~
2Tc-35
ns
33
Data transfer DT/oE setup time
tDTS
2Tc-50
ns
34
Data transfer DT/OE hold time
tDTH
6Tc-50
ns
35
Phase shift between CAS and
DTiOE
tcDH
2Tc-40
ns
36
Phase shift between CAS and
DT/oE
torR
2Tc-50
ns
37
CAS setup time
tcsR
2Tc-50
ns
38
CAS hold time
tcHR
6Tc-50
ns
39
Phase shift between RAS and CAS
tRPC
2Tc-50
ns
40
SC cycle time
tsec
4TL -10
ns
41
SC high-level pulse width
tsc
2TL -50
ns
42
SC low-level pulse width
tscp
2TL -50
ns
43
Memory data read setup time
tRDS
40
ns
44
Memory data read hold time
tRDH
5
ns
45
Phase shift between SOE and SC
lose
20
ns
Figure 47
Figure 48
Figure 49
Tc: DOTCLK cycle time
IL: LDOTCK cycle time (. Tc for synchronous mode)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
_~ _ _ _ _ _ • _ _ _ _ _ _ ••• ___ 0_ _ _ _ _ _ _ _ ~ __ • _ _
.. " " . 0 . _ .. _ _ -
~
____
~_
.. _"
769
...
__
._-_._-
HD66850F
@
J..§t
..... 2.4V
RAS
1\0.8 V
"l
@
@
([Ill
CAS
CASL
2.4V -
....,
1<-0.8 V
f-
It
I(@)
)
-K2.4V
"l
O.8V
I\.
-
®,®
~ ~~ ~
MAO-8)~
~~
@'@
@
0.8V ....
1\
~~
--'
-'
....,
K
<-
1\
~~
)
MD0-15
r- 2.4 V
~
IL
I\"'
~ ~
WE
.'L
@
®
~
- K2.4V
r-
)
0.8V
t-
~
....
" K
I"-
Figure 46 Memory Interface (write)
-
2.4V
t-0.8 V
-
k'
~ rO.8V
@
I~
~ ..... 0.8V
8
~
0.8V _
IL
2.4 V
Figure 47 Memory Interface (data transfer)
HITACHI
770
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD66850F
V
/
@
2.4 V
0.8 V
@
~
2.4 V
/
~0.8V
Figure 48 Memory Interface (refresh)
sc
~ '\ 0.8 V
@
f-
7
@)
MSo-15
J-
@
~ 2.0 V
.... 0.8V
-'
2.4 V
<-0.8 V
r
"}
~
....1
@
~
)
f- 2.0 V
0.8 V
9
;C
f+-+@
2.4 V -'
0.8 V ...,
SOEO-1
K
Figure 49 Memory Interface (serial read)
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
771
HD66850F
LCD driver interface
No.
Item
46
CL2 cycle time
Symbol
Min
tWCl2
2TL -10'1
Max
Unit
Reference
ns
Figure 50
4TL -10'2
8TL -10'3
16TL -10'4
47
CL2 high-level pulse width
tWCL2H
1TL -40'l
ns
2TL -40'2
4TL -40'3
8TL -40'4
48
CL2 low-level pulse width
tWCl2L
1TL - 40'1
ns
2TL -40'1
4TL -40'2
8TL -40'4
49
CL1 high-level pulse width
tWCL1h
150
50
LCD data delay time
too
51
CL1 setup time
tSCL1
200
52
CL1 hold tirne
tHCL1
200
53
M output delay time
tOM
54
FLM setup time
tHF
100
55
LDOTCK cycle time
leVCL
31.2
56
LDOTCK high-level pulse width
tWLL
15
57
LDOTCK low-level pulse width
tWLH
15
58
LDOTCK rise time
tLr
5
ns
59
LDOTCK fall time
tLf
5
ns
ns
30
ns
ns
ns
100
ns
ns
100
ns
ns
ns
TL: LDOTCK cycle time (- Tc for synchronous mode)
Notes: 1.
2.
3.
4.
For display modes 9, 13, 16, 19, and 20
For display modes 1, 5, 10, 11, 14, 15, 17, and 18
For display modes 2,3,6, 7, and 12
For display modes 4, and 8
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HD66850F
@
~@
CL2
)
-~0.3
/
Vee
~
~
UDO-7
LDO-7
....,It
0.7 Vee \
-;
f"
~
)r-
) Ir-
0.7 Vee
0.3 Vee
\
,.;
@'- -
®
~
~
CL1
@jo.7vee
0.3 Vee
E
<9 ~.I
0.7 Vee
FLM
@
.1
1\
~kee
_ _ _ _ _ _ _-'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
E
~
~ee
M
Figure SO LCD Driver Interface
MPU interface
No.
Item
Symbol
Min
60
RD low-level pulse width
tWROL
4Tc
61
RD high-level pulse width
tWROH
4Tc
ns
62
WR low-level pulse width
tWWRL
4Tc
ns
63
WR high-level pulse width
tWWRH
4Tc
ns
64
RD input inhibited time
tRIH
4Tc
ns
65
WR input inhibited time
tWIH
4Tc
ns
66
Address setup time
tAS
0
ns
67
Address hold time
tAH
0
ns
68
Data delay time
tooR
69
Data output hold time
tOHR
10
70
Data setup time
tosw
0
ns
71
Data hold time
tOHw
0
ns
Max
100
Unit
Reference
ns
Figure 51
I
ns
ns
Tc: DOTCLK cycle time
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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
773
HD66850F
RS
CS
DO _ 07 - - - - - - < 1 2.4 V
0.8V
I}---(I 2.4 V
0.8 V
Figure 51 MPU Interface
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Hitachi America, Ltd.- Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819. (415) 589-8300
HD66850F
ROM interface
No.
Item
Symbol
Min
72
ROM address cycle time
tcVCA
16Tc -20
73
ROM data setup time
toswo
150
ns
74
ROM data hold time
tOHWO
10
ns
Max
Unit
Reference
ns
Figure 52
Tc: OOTClK cycle time
AO-AS
00-07
Figure 52 ROM Interface
RES timing
No.
Item
75
RES low-level pulse width
Symbol
. Min
Max
Unit
Reference
I1s
Figure 53
~_o@_~,.----.
.• v
-
Figure 53 Reset Timing
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
775
HD66850F
Load circuit
Pins
Reference
,
MAO - MA7, MA8ISOE1, OT/oE, WE, CAS, CASl,
2.4 kQ
11 kQ
40 pF
Figure 54
40 pF
Figure 55
RASO, RAS1, SOEO, MOO - M015, DO - 07, AO/AJO,
A1/AJ1, A21RS/AJ2, A31CS/AJ3, A4IWRlSP, ASIROIDOTE
DlSPON, OATAE, SCLK, M, FlM, CL2, VCl 1, XCl1,
lOO - l07, UOO - U07
Rl
C:
40pF
R:
11 kn
Rl: 2.4kn
All diodes are
1S2074 (8)
R
Applicable
pins:
MAo-MA7, MAS/sOE1, OT/oE, WE, CAS, CASl, RASO, RAS1, SOEO, MOo-M015,
00-07, AO/AJO, A1/AJ1, A2/RS/AJ2, A31CS//lJ3, A4IWRlSP, ASIROIDOTE
Figure 54 TTL Load Circuit
o-----------.±
~~
Applicable pins: OISPON, OATAE, SClK, M, FlM, CL2, VCl1, XCl1, lOO - l07, UOO - U07
Figure 55 Capacitive Load Circuit
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LCD CONTROLLERlDRNER LSI DATA BOOK
Section Six
Segment TYPe
LCD Controller/Driver
,
I
HITACHI
HD61602/HD61603--(Segment Type LCD Driver)
Descripition
Features
The HD61602 and the HD61603 are liquid
crystal display driver LSIs with a TTL and
CMOS compatible interface. Each of the LSIs
can be connected to various microprocessors
such as the HMCS6S00 series.
.
•
•
The HD61602 incorporates the power supply
circuit for the liquid crystal display driver.
Using the software-controlled liquid crystal
driving method, several types of liquid crystals can be connected according to the
applications.
The HD61603 is a liquid crystal display driver
LSI only for static drive and has 64 segment
outputs that can display S digits per chip.
•
Wide-range operating voltage
-Operates ina wide range of supply
voltage: 2.2 V to 5.5 V
-Compatible with TTL interface at 4.5 V
to 5.5 V
Low current consumption
-Can run from a battery power supply
(100 pA max. at 5 V)
-Standby input enables standby operation at lower current consumption (5
pA max. on 5 V)
Internal power supply circuit for liquid
crystal display driver (HD61602)
-Internal power supply circuit for liquid
crystal display driver facilitates the
connection to a microprocessor system
Versatile segment driving capacity
Frame Fraq. (Hz)
at t ... = 100 kHz
Package
33
80-pin
- . . , . - - - - . , . . - - - - - - - - - - " - - - - - - - " - - - - - - -__-----Plastic
65
QFP
~-----~--~----------~~--------~----------2-0-8-------- FP-80
-:-'-;':--':-'---'----=-=-':-----::--"---'-----::-::---::-":----:---:----=-:=----- (FP-80A)
223
TFP-SO
33
80-pin
Plastic
QFP
(FP-80)
Ordering Information
Type No.
HD61602R
HD61602RH
HD61602TF
HD61603R
Package
SO-pin plastic QFP (FP-80)
SO-pin plastic QFP (FP-80A)
80-pin thin plastic QFP (TFP-80)*
80-pin plastic QFP (FP-80)
• Under development
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HD61602/HD61603
Pin Arrangement (Top View)
HD61602
HD61603
VDD 1=
READY F=
~E L..
vvc r-
'
'
a1!l!!I:l!I!!:!~J:!;::=?'llDll8
SEG"
F=
001=
"F=
"1=
"1=
"1=
"1=
SEG"
031= SEG,.
"
.,
., 1= SEG,.
ltr~ 5
58 •
D,~ ,
0, L.. •
0, r- •
Do 1= ,.
Vssl= "
V, L.. "
COM. ~ "
SEG03 L.. "
SEG., C "
SEG., r "
..
"1=
"
t=1=
..
,.t=
.,
~~g: C::
SEG•• r- "
SEG"
SEG5. r- 21
SEG.. 22
SEG,. r- 23
SEG., 1= "
.. =
SEG 17
SEG,.
SEG"
SEG,o
SEG21
SEG"
SEG"
SEG..
SEG,.
SEG,.
SEG"
SEG,.
:: == ~~g~~
'81=
"F=
C,.
C
"t=
"F=
"t=
~~~"~g;;;RR~~~~~=i1
.JUUUUUUUUL
"
SEG 31
SEG"
SEG"
SEG,.
SEG,.
SEG,.
II II II II II
(Top View)
(FP-80)
(FP-80)
HD61602
ii~~~~~'~""~m$~~m~~~.
Cl:
6Ot=: SEGIS
WE
::r= ~~~:;
::1= ~~~::
R[
S8
0,
Do
SEG20
0,
SEG21
D.
Vss
0,
0,
0,
53
F"
SEG22
&2
SEG23
60
SEG2S
49
SEG26
SEG2?
SEG24
"
Do
VREFI
VREf2
SEG2S
SEG29
SEG30
SEG31
VC,
VC,
v,
43
~~ ~~:
I
SEG32
:~F ~~~::
(FP-80A)
(Top View)
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
779
HD61602/HD61603
Block Diagram
HD61602
Common output
(4 lines)
Segment output
(51)ines)
HD61603
Common
output
it
00-03
Segment
output
(64 lin..)
S8
Va
Absolute Maximum Ratings
Symbol
Limit
Unit
VOO, V1, V2, V3
0.3 to + 7.0
V
v,.
0.3 to Voo - 0.3
V
Operating temperature
Topr
-20 to +75
·C
Storage temperature
Tstg
-55 to +125
·C
Item
Power supply voltage
Terminal voltage
*
*
*
Value referenced to Vss = 0 V.
Note: If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using
them within electrical characteristics limits is strongly recommended for normal operation. Use
beyond these conditions will cause malfunction and poor reliability.
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61602/HD61603
Recommended Operating Conditions
Limit
Item
Symbol
Min
Power supply voltage
Voo
Typ
Max
Unit
2.2
5.5
V
V,. V2. V3
0
Voo
V
Terminal voltage *
Vr
0
Voo
V
Operating temperature
Topr
-20
75
'C
* Value referenced to Vss = 0 V.
Electrical Characteristics
DC Characteristics (1)
(Vss
= 0 V, VDD = 4.5 to 5.5 V, Ta =
-20 to +75'C, unless otherwise noted)
Symbol Min
Item
Limit
Typ
Max
Unit
-
Voo
V
Test Condition
Input high voltage
OSC,
VIH'
Others
VIH2
0.8Voo
2.0
Input low voltage
OSC,
VIU
0
V
Voo
0.2Voo V
Others
VIL2
0
0.8
V
JlA
Vo = Voo
Output leakage
current
Output low
voltage
Input leakage
current
*1
LCD driver voltage
drop
READY
IOH
5
READY
VOL
0.4
V
IOL = 0.4 mA
Input
terminal
hu
-1.0
1.0
JlA
VIN = O-Voo
V,
11L2
-20
20
JlA
V2. V3
11L3
-5.0
5.0
COMo-COM3
Vd'
0.3
JlA
V
SEGo-SEG50
Vd2
0.6
V
± Id = 3 JlA for each
SEG. V3 = Voo-3 V
100
100
JlA
During display·
Rosc = 360 kO
100
5
JlA
VTR
0.4
V
At standby
VREF2 = Voo-1 V.
C,-C4 = 0.3JlF.
RL = 3 MO
Power supply current
Internal driving
voltage drop
V,. V2. V3
± Id = 3 JlA for each
COM. V3 = Voo-3 V
-------'~
*
*1
Except the transfer operation of display data and bit data.
Vl. V2: apply only to HD61602.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
781
I
•
HD61602/HD61603
DC Characteristics (2)
(Vss = 0 V, VDD = 2.2 to 3.S V, Ta = -20 to +75·C, unless otherwise noted)
Item
Symbol Min
limit
Typ
Max
Input high voltage
VIH
-
Voo
Input low voltage
Output leakage
current
Output low
voltage
Input leakage
current
*1
LCD driver voltage
drop
*
*1
Unit
V
Teat Condition
READY
IOH
0.1Voo V
5
"A
VIN
= Voo
READY
VOL
0.1Voo V
IOl
= 0.04 mA
Input
terminal
hL!
-1.0
1.0
JlA
VIN
= O-Voo
VIN
= 0-V3
Vil
0
V,
hl2
-20
20
"A
V2, V3
hl3
-5.0
5.0
COMo-COM3
Vd'
0.3
"A
V
SEGo-SEG5o
Vd2
0.6
V
Iss
50
"A
Iss
5
VrR
0.4
"A
V
Power supply current
Internal driving
voltage drop
0.8Voo
0
V" V2, V3
. ±Id = 3 JlA for each
COM, V3 = Voo-3 V
± Id = 3 JlA for each
SEG, V3 = Voo-3 V
During display·
Rose = 330 kO
At standby
VREF2 = Voo -1 V,
C,-C4 = 0.3 "F
RL = 3 MO,
Voo = 3-3.8 V
Except the transfer operation of display data and bit data.
V" V2: apply only to HD61602.
HITACHI
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Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD61602/HD61603
AC Characteristics (1)
(Vss
= 0 V. Voo = 4.5 to 5.5 V. Ta =
Item
-20 to+75'C. unless otherwise noted)
Symbol Min
Limit
Typ
Max
Unit
Test Condition
Oscillation frequency
OSC2
fosc
70
100
130
kHz
Rosc=360 kO
External clock
frequency
External clock duty
OSC,
fosc
70
100
130
kHz
OSC,
Duty
40
50
60
%
ts
400
ns
tH
10
ns
twH
300
ns
twl
400
ns
twR
400
I/O signal timing
ns
1.0
tOl
Input signal rise time and fall time
Jls
tEN
400
top,
9.5
10.5
Clock
toP2
2.5
3.5
Clock
25
ns
Figure 5
ns
t" tf
For display
data transfer
For bit and mode
data tra nsfer
AC Characteristics (2)
(Vss
= 0 V. Voo = 2.2 to 3.8 V. Ta =
Item
-20 to+75'C. unless otherwise noted)
Symbol Min
Limit .
Typ
Max
Unit
Test Condition
Oscillation frequency
OSC2
fosc
70
100
130
kHz
Rosc=330 kO
External clock
frequency
External clock duty
OSC,
fosc
70
100
130
kHz
OSC,
50
60
%
Duty
40
I/O signal timing
ts
1.5
JlS
(Voo = 3.0-3.8 V)
tH
1.0
Jls
tWH
1.5
JlS
twl
1.5
Input signal rise time and fall time
Jls
2.0
tOl
Jls
twR
1.5
tEN
2.0
top,
9.5
10.5
Clock
toP2
2.5
3.5
Clock
25
ns
t" tf
Figure 6
Jls
I
JlS
For display
data transfer
For bit and mode
data transfer
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
783
HD61602/HD61603
0 0 -0 7
>---------<1
Figure 1
.
Write Timing
(RE is fixed at high level, and SYNC at low level)
Figure 2
Figure 3
Reset/Read Timing
(CS and SYNC are fixed at low level)
READY Timing
(When the READY output is always available)
HITACHI
784
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD61602/HD61603
"ADY
f~ F=-:~~~~-~\~--W-it-hi-n-j~"
_
1 clock
V1H
SYNC
V1H
V1L
\,.,._ _ _ _ _ _ _ _ _ __
Figure 4
SYNC Timing
Voo
Voo
47kQ
470kO
10kQ
Measurement
terminal
Measurement
terminal
(READY)
(READY)
30pF:
120kO
o--~
1S2074H
Vss
Figure 5
Bus Timing Load Circuit
(LS-TTL Load)
Figure 6
Bus Timing Load Circuit
(CMOS Load)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
785
HD61602/HD61603
Terminal Functions
HD61602 Terminal Functions
Terminal
Name
No. of
Lines
Input/Output
Connected
to
Function
Voo
Power supply
READY
NMOS open
drain output
MCU
While data is being set in the display data RAM and
mode setting latch in the LSI after data transfer, low
is output from the READY terminal to inhibit the
next data input.
There are two modes: one in which low is output
only when both of CS and RE are low, and the other
in which low is output regardless of CS and RE.
Input
MCU
Chip select input. Data can be written only when
this terminal is low.
Input
MCU
Write enable input. Input data of DO to 07 is latched at the rising edge of WE.
Input
MCU
Resets the input data byte counter. After both CS
and RE are low, the first data is recognized as the
1st byte data.
Input
MCU
High level input stops LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
Input
MCU
Data input terminal for a-bit x 2-byte data.
SB
a
Positive power supply.
Power supply
Vss
Output
Input
2
Output
Negative power supply.
External
R
Reference voltage output. Generates LCD driving
voltage.
External
R
Divides the reference voltage of VREFl with external
R to determine LCD driving voltage. VREF2 .. Vl.
External
C
Connection terminals for boosting C of LCD driving
voltage generator. An external C is connected
between VCl and VC2.
3
Output
(Input)
External
C
LCD driving voltage outputs. An external C is connected to each terminal.
COMo-COM3 4
Output
LCD
LCD common (backplate) driving output.
SEGo-SEG50
Output
LCD
LCD segment driving output.
Input
MCU
Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high
input. LCD is off.
Input
Output
External
R
Attach external R to these terminals for oscillation.
An external clock (100 kHz) can be input to OSC 1 .
51
SYNC
OSCl
OSC2
2
Note: Logic polarity is positive. 1
= high = active.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61602/HD61603
HD61603 Terminal Functions
Terminal
Name
No. of
Lin..
Input/Output
Connected
to
Function
Voo
Power supply
READY
NMOS open
drain output
MCU
While data is being set in the display data RAM and
mode setting latch in the LSI after data transfer, low
is output from the READY terminal to inhibit the
next data input.
There are two modes: one in which low is output
only when both of CS and RE are low, and the other
in which low is output regardless of CS and RE.
Input
MCU
Chip select input. Data can be written only when
this terminal is low.
Input
MCU
Write enable input. Input data of Do to 03 is latched
at the rising edge of WE.
.
Input
MCU
Reset the input data byte counter. After both of CS
and RE are low, the first data is recognized as the
1st byte data.
Input
MCU
High level input stops the LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
Input
MCU
Data input terminal from where 4-bit x 4 data are
input.
SB
00-03
4
Positive power supply.
Vss
Power supply
V3
Input
Power
supply
Power supply input for LCD drive. Voltage between
Voo and V3 is used as driving voltage.
COMo
Output
LCD
LCD common (backplate) driving output.
Output
LCD
LCD segment driving output.
Input
MCU
Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high
input. LCD is off.
Input
Output
External
R
Attach external R to these terminals for oscillation.
An external clock (100kHz) can be input to OSC, .
SEGo-SEG63
64
SYNC
OSC,
OSC2
2
Note: Logic polarity is positive. 1
Negative power supply.
= high = active.
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HD61602/HD61603
Display RAM·
HD61602 Display RAM
The HD61602 has an internal display RAM
shown in figure 7. Display data is stored in
the RAM, or is read· according to the LCD
driving timing to display on the LCD. One bit
of the RAM corresponds to 1 segment of the
LCD. Note that some bits of the RAM cannot
be displayed depending on LCD driving
mode.
Common address
(COMo-COMa)
I ~{L_ _~I
-::
:----
Display RAM
\.
•
.
I
51 bits
Segment address (SEG o-SEG 50)
Figure 7
Display RAM
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HD61602/HD61603
is reproduced on the LCD panel.
Reading Data from Display RAM: A display RAM segment address corresponds to a
segment output. The data at segment
address SEGn is output to segment output
SEGn terminal.
When a 7-segment type LCD driver is connected, for example, the correspondence
between the display RAM and the display
pattern in each mode is as follows:
A common address corresponds to the output
timing of a common output and a segment
output. The same common address data is
simultaneously read. The data of display RAM
1.
Static drive
In the static drive, only the column of
COMo of display RAM is output. COMl to
COM3 are not displayed.
LCD connection
'"
(!)
c5w
'"
(!)
w CJ)
w
CJ)
2.
CJ)
(!)
W
CJ)
JJJc5
wwww
CJ) CJ)
SEG.
SEG.
SEG,.
SEG"
SEG,2
SEG"
SEG,.
SEG,.
CJ) CJ)
1/2 duty cycle drive
COMo and COM1 of display RAM are output in time sharing. The columns of COM2
and COM3 are not displayed.
In the 1/2 duty cycle drive, the columns of
LCD connection
a
Display RAM
COM,
a
9
c
b
e
d
DP
SEG 5
SEGe
SEG 7
COMo
... (!)"'
(!)
w
CJ)
3.
w
CJ)
~
w
CJ)
G
w
CJ)
SEG 4
1/3 duty cycle drive
In the 1/3 duty cycle drive, the columns of
COMo to COM2 are output in time sharing.
No column of COMJ is displayed.
SEGs
SEG 9
"Y" cannot be rewritten by display data
(input on an a-segment basis). Please use
bit manipulation to tum on/off the display of "Y".
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I
HD61602/HD61603
LCD connection
Display RAM
COM3
4.
/
/
~/
/
COM2
Y
a
b
COM,
f
9
c
COMo
e
d
DP
SEG 3
SEG 4
SEG 5
SEG B
1/4 duty cycle drive
In the 1/4 duty cycle drive, all the col-
umns of COMo to COM3 are displayed.
fl
LCD connection
a
Display RAM
~------COM3
,
/-
b
----COM2
.~~~ --'---COM,
d
DP-r
- - - ' ) - - - COMo
N
(,!)
'"
(,!)
(/)
(/)
w
COMa
f
a
COM2
9
b
COM,
e
c
COMo
d
DP
w
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HD61602/HD61603
Writing Data into Display RAM: Data is
written into the display RAM in the following
five methods:
1. Bit manipulation
Data is written into any bit of RAM on a
bit basis.
2. Static display mode
8-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of static drive.
3. 1/2 duty cycle display mode
8-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/2 duty cycle drive.
4. 1/3 duty cycle display mode
8-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/3 duty cycle drive.
5. 1/4 duty cycle display mode
(2)
(1) Static
8-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of 1/4 duty cycle drive.
The RAM area and the alocation of the segment data for 1-digit display depend on the
driving methods as described in "Reading
Data from Display RAM".
8-bit data is written on a digit basis corresponding to the above duty cycle driving
methods. The digits are allocated as shown
figure 8 (allocation of digits). As the data can
be transferred on a digit basis from a microprocessor, transfer efficiency is improved by
allocating the LCD pattern according to the
allocation of each bit data of the digit in the
data RAM.
Figure 8 shows the digit address (displayed
(3)
1/2 duty cycle
display
COM oCOM,COM 2
(4)
1/3 duty cycle
display
COM oCOM,COM 2 COM 3
COM oCOM,COM2COM 3
SEGo
SEGo
SEGo
SEG,
SEG,
SEG,
SEG2
SEG2
SEG2
SEG2
SEG3
SEG3
SEG3
SEG 3
.-~--./
SEGo
AdO
Ad1
SEG4
SEGs
SEG5
SEGs
SEG s
SEGs
SEGs
SEG7
SEG a
SEG7
SEG7
SEGa
SEG8
SEGs
SEGg
SEGg
SEGg
SEGg
SEG,o
SEG,o
SEG"
SEG l1
SEGl1
SEG'2
SEG 12
SEG'3
I--+-i/
SEG'3
SEG4
Ad3
Ad4
SEG,o
Ad5
SEGl1
SEG 12
Ad4
SEG'4
SEG'4
SEG'4
SEG,s
SEG'5
SEG'5
Ad5
Ad6
Ad7
SEG.s
AdS
SEG 17
SEG 17
SEG'8
Ad3
SEG7
SEG'5
SEG'8
Ad2
SEG s
Ad2
SEG'3
SEG. 4
SEG 17
Ad1
SEGs
SEG'2
SEG'3
AdO
SEG,
SEG4
SEG4
Ad6
SEG'8
~
SEG 50
Figure 8
Ad16
1/4 duty cycle
display
SEG 50
Ad24
Ad25
Allocation of Digit (HD61602)
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791
HD61602/HD61603
as Adn) to specify the store address of the
transferred 8-bit data on a digit basis.
Figure 9 shows the correspondence between
each segment in an Adn and the 8-bit input
data.
When data is transferred on a digit basis, 8bit display data and digit address should be
specified as described above.
In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, l-bit display data, a segment addr~ss (6 bits) and a common address
(2 bits) should be specified.
HD61603 Display RAM
The HD61603 has an internal display RAM an
shown in figure 10. Display data is stored in
the RAM and output to the segment output
terminal.
However, when the digit address is Ad6 for
static, Ad12 for 1/2 duty cycle, or Ad25 for 1/
4 duty cycle, display RAM does not have
enough bits for the data.
Thus the extra bits of the input a-bit data are
ignored.
(1 )
(2)
Static display
1/2 duty display
1/3 duty display
COMo COM 1 COM2
COM o COM 1
COMo
SEGs
(3)
Bit
7
SEG:!n
Bit
7
6
Bit
7
6
SEGsn+1
6
SEG4n +1
5
4
SEG3n+l
5
4
3
SEGSn + 2
5
SEG4n+2
3
2
SEG3n+2
2
1
Bit
SEGSn +3
4
SEG4n+3
1
Bit
SEGSn+4
3
SEGSn+5
2
0
0
(4)
1/4 duty display
SEGSn +6
SEGSn +7
Bit
0
SEG2n+1
Figure 9
Bit
7
6
5
4
3
2
1
Bit
0
Bit ASSignment in an Adn (HD61602)
1 bl
(C~Mo){Ll::::::::=============D=is:PI:aY~RA==M::====::::::======::::~J
~~----------------------~
64 bits
Segment address (SEGo-SEG S3)
Figure 10
Display RAM (HD61603)
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HD61602/HD61603
Reading Data from Display RAM: Each
bit of the display RAM corresponds to an LCD
segment. The data at segment address SEGn
is output to segment output SEGn terminal.
Figure 11 shows an example of the correspondence between the display RAM bit and
the display pattern when a 7-segment type
LCD is connected.
Writing Data into Display RAM: Data is
written into the display RAM in the following
two methods:
1. Bit manipulation
Data is written into any bit of RAM on a
2.
bit basis.
Static display mode
8-bit data is written on a digit basis
according to the 7-segment type LCD
pattern of static' drive.
The 8-bit data is written on a digit basis into
the digit address (displayed as Adn) shown in
figure 12. When data is transferred from a
microprocessor, four 4-bit data are needed to
specify the digit address and an 8-bit display
data. Figure 13 shows the correspondence
between each segment in an Adn and the
transferred 8-bit data.
LCD connection
Display RAM
SEGa SEGg SEG lO SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16
Figure 11 Example of Correspondence between Display RAM Bit and Display Pattern
(HD61603)
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HD61602/HD61603
In bit manipulation, anyone bit of display
RAM can be written. When data is transfer-
red on a bit basis, i-bit display data and a
segment address (6 bits) should be specified.
COMo
SEGo
SEG ,
SEG2
SEG3 AdO
SEG4
SEGs
SEG8 .
SEG7
SEG s
SEG g
SEG '0
SEG I1 Ad1
SEG 12
SEG '3
SEG'4
SEG'5
SEG '8
SEG 17
SEG ,S
COMo
SEGan
Bit
7
SEG4S
SEG48
SEG Sn +1
6
SEG47
SEG 48
SEGsn +2
5
SEG Sn +3
4
SEG Sn +4
3
SEG Sn +5
2
SEG 49
SEG~
SEG S1 Ad6
SEG52
SEG 53
SEG 54
SEGss
SEG5e
SEG S7
SEGsn +e
SEGSn +7
·Bit
0
SEGsa
SEG'9 Ad2 SEG59 Ad7
SEG 60
SEG20
SEGel
SEG21
SEGe
SEG22
SEG83
SEG23
SEG24
Figure 12 Allocation of Digits
(HD61603)
Figure 13 Bit Assignment in an Adn
(HD61603)
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HD61602jHD61603
OPERATING MODES
HD61602 Operating Modes
The HD61602 has the following operating
modes:
1. LCD drive mode
Determines the LCD driving method.
a. Static drive mode
LCD is driven statically.
b. 1/2 duty cycle drive mode
LCD is driven at 1/2 duty cycle and 1/
2 bias.
c. 1/3 duty cycle drive mode
LCD is driven at 1/3 duty cycle and 1/
3 bias.
d. 1/4 duty cycle drive mode
LCD is driven at 1/4 duty cycle and 1/
3 bias.
2.
Data display mode
Determines how to write display data
into the data RAM.
a. Static display mode
8-bit data is written into the display
RAM according to the digit in static
a.
READY is mode always available.
drive.
1/2 duty cycle display mode
8-bit data is written into the display
RAM according to the digit in 1/2
duty cycle drive.
c. 1/3 duty cycle display mode
8-bit data is written into the display
RAM according to the digit in 1/3
duty cycle drive.
d. 1/4 duty cycle display mode
8-bit data is written into the display
RAM according to the digit In 1/4
duty cycle drive.
b.
3.
READY output mode
Determines the READY output timing.
After a data set is transferred, the data is
processed internally. The next data cannot be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
the READY is output can be selected from
the following two modes:
,"----
________-.J/
tI
WE~
:~
I
READY
Data transfer
period
b.
'~----------------------------J11
I
I
- - -__..,I..._ - - - - - - - l n p u t i n h i b i t - - - - - -.......
-!'
I
I
period
I
I
I
I-- Next data
I
transfer
READY is mode available by CS and
RE.
-----....,,/
~
1
:1
).I
I
I
\.1I
READY-------------+I----------~,
/
'-...._----~
I
AI
\I
I ~~--------~~
I
'---Y
~--tl
Data transfer --"'--+1...- - - - - - - - I n p u t i n h i b i t - - - - - -.......
period
4.
I
period
LCD OFF mode
In this mode, the HD61602 stops driving
LCD and turns it off.
5.
I
I
1
1
.1-- Next data
transfer
External driving voltage mode
A mode for using external driving voltage
(V1, V2, and V3).
•
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HD61602/HD61603
The above 5 modes are specified by mode
setting data. The modes are independent of
each other and can be used in any combina-
tion. Bit manipulation is independent of data
display mode and can be used regardless of it.
HD61603 Operating Modes
not be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:
The HD61603 has the following modes:
1. READY output mode
Determines the READY output timing.
After a data set is transferred, the data is
processed internally. The next data cana.
READY is always available.
______---.J/
\l-r
~
READY - - - - - " " ' \ . .
~i-------------------------~11
I
I
Data transfer---.ootl....- - - - - - - - I n p u t i n h i b i t - - - - - -....~l
period
period
I
I
I
I
I
' - -Next data
transfer
b. READY is mode available by CS and
RE.
cs
"R"E
I
I
READY
Data transfer
period
I
I
I
I
-I"
/
I
I
~I
WE
2.
~
/
"
I
I
I
I
I
I
/f'
I
~
Input inhibit
period
"
/
\r
'---./1r
I
-,
f'-/
,
Ir
r
I
r
I-- Next data
transfer
LCD OFF mode
In this mode, the HP61603 stops driving
the LCD and turns it off.
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HD61602/HD61603
INPUT DATA FORMATS
HD61602 Input Data Formats
Input data is composed of 8 bits X 2. Input
them as 2-byte data after READY output
changes from low to high or low pulse is
entered into RE terminal.
1.
3.
Mode setting data
1st byte
Display data (Updates display on an 8segment basis)
7
1st byte
3
2
1
o
7
2nd byte
I :
7
a.
6
4
3
2
1
0
6
5
4
3
2
1
0
5
4
3
Display mode bits:
00: Static display mode
01: 1/2 duty cycle display mode
10: 1/3 duty cycle display mode
11: 1/4 duty cycle display mode
b. OFF ION bit:
1: LCD off (set to 1 when SYNC is
entered.)
0: LCD on
c. Drive mode bits:
00: Static drive
01: 1/2 duty cycle drive
10: 1/3 duty cycle drive
11: 1/4 duty cycle drive
d. READY bit:
0: READY bus mode; READY outputs 0 only while CS and RE are
O. (reset to 0 when SYNC is
entered.)
1: READY port mode; READY
outputs 0 regardless of CS and
RE.
e. External power supply bit:
0: Driving voltage is generated
internally.
1: Driving voltage is supplied
externally. (set to 1 when SYNC
is entered.)
:o I
2
Bit manipulation data (Updates display
on a segment basis)
1st byte
7
5
a.
Display address: Digit address Adn in
accordance with
display mode
Display data:
Pattern data that is
written into the
display
RAM
according to display
mode and the
address
b.
2.
6
6
2nd byte
Display address
(Digit address Adn)
4
External
power
supply
5
4
3
2
1
0
2nd byte
7
6
5
432
o
a. Display data:
Data that is written
into 1 bit of the
specified display
RAM
b. COM address:
Common address of
display RAM
c. SEG address:
Segment address of
display RAM
4.
l-byte instruction
1st byte
I I I I I I I I
7
1
6
x
5
x
4
x
3
x
x
2
x
0
The first data (first byte) is ignored when
bit 6 and bit 7 in the byte are 1.
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I
HD61602/HD61603
HD61603 Input Data Formats
Input data is composed of 4 bits x· 4. Input
them as four 4-bit data after READY output
changes from low to high or· low pulse is
entered into RE terminal.
1st byte
I
Display data (Updates display on an 8segment basis.)
1.
Mode setting data
3.
2nd byte
1 : 0
3
2
x
I
0
0
II
x
I~EADYI
3
2
x : x
1st byte
3
01
o
2
3
o
2
OFFION bit:
1: LCD off (set to 1 when SYNC is
entered.)
0: LCD on
b. READY bits:
0: READY bus mode; READY outputs 0 only while CS and RE are
O. (reset to 0 when SYNC is
entered.)
1: READY port mode; READY
outputs 0 regardless of CS and
RE.
a.
3rd byte
Bitl7
Display data
6
5
4
.3
2
0
a.
Display address: Digit address Adn
shown in figure 12.
b. Display data:
Pattem data that is
written into the
display RAM as
shown in figure 13.
2.
Bit manipulation data (Updates display
on a segment basis.)
1at byte
2nd byte
I 0:
3
I~!:ayl
2
1st byte
l' >Ix >I
r---r - - :
0
1~~~:'dr:1
3
l-byte instruction
4.
x II x xr--I0 ""--'0
3
2
0
4th bytC\
a.
2
1
0
Display data:
b. SEG address:
Bit3
3
320
The first data (4 bits) is ignored when bit
3 and 2 in the data are 1.
SEG address
0
1
.2
2
0
Data that is written
into 1 bit of the
specified display
RAM.
Segment address of
display RAM (segment output).
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HD61602/HD61603
How To Input Data
How to Input HD61602 Data
Input data is composed of a bits x 2. Take
care that the data transfer is not interrupted,
because the first a-bit data is distinguished
from the second one by the sequence only.
If data transfer is interrupted, or at power on,
the following two methods can be used to
reset the count of the number of bytes (count
of the first and second bytes):
1. Set CS and RE inputs low (no display data
changes).
Input 2 or more "l-byte instruction" data
in which bit 7 and 6 are 1 (display data
may change).
The data ~ut method via data input terminals (CS, WE, Do to D7) is similar to that of
static RAM such as HM6116. An access of the
LSI can be made through the same bus line as
ROM and RAM. When output ports of a
microprocessor are used for an access, refer to
the timing specifications and figure 14.
2.
Power on
WE' *6
RE~~*4
,.----,...----1----~
*5
* 1"
'----',...."..
.,-_.1
*3
'----',------..-."'---
READY .. ___
oJ
*5
SYNC------------I~---------------J~
*5
*2
SB----------~~--------------------------------------Do-D7~~al~stDX(2~n!dIX::::::::::I~i~§t~X(25M~Xr:::::::]Xll~.tJI~2n~d]X::=
Mode setting data
Mode setti ng data
Display data
* 1:
READY output is indefinite during 12 clocks after the oscillation start
at power on (clock: OSC 2 clock).
*2: High pulse should be applied to SYNC terminal when using two or more
chips synchronously.
*3: In the mode in which READY is always available, READY outP\lt is
in definite while SYNC is high.
4: Reset the byte counter after power on.
5: READY output period is within 3.5 clocks in the mode setting operation
and bit manipulation or within 10.5 clocks when the display data (8
bits) is updated.
6: Connect a pull-up resister if WE or RE may be floating.
7: It is not always necessary to follow this example.
*
*
*
*
Figure 14
Example of Data Transfer Sequence
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799
HD61602/HD61603
How to Input HD61603 Data
Input data is composed of 4 bits x 4. Take
care that data transfer is not interrupted,
because the first 4-bit data to the fourth 4-bit
data are distinguished from each other by the
sequence only.
If data transfer is interrupted, or at power on,
the following two methods can be used to
reset the count of the number of data (count
of the first 4-bit data to the fourth 4-bit data):
1.
2.
Set CS and RE low.
Input 4 or more "i-byte instruction" data
(4-bit data) in which bit 3 and 2 are 1
(display data may change).
The data !!!E.ut method via data input terminals (CS, WE, DO to D3) is similar to that of
static RAM such as HM6116. An access of the
LSI can be made through the same bus line as
ROM and RAM. When output ports of a
microprocessor are used for an access, refer to
the timing specifications and figure 15.
Power on
WE
1*6
RE~*4
READY L~:::7~~~:~~/------~'---1r----------~~
* 1
*5
*3
*5
*5
SYNC ________-(n~~------------~r\~·*~2~----------------------SB--------~~~----------------------------------------------
Do-D3~~~h~'AX=~~X~~~X~4~"AX________~X~1"~X~2~·X~'=riAX~4"~X~____~X~1·~,X~W=X~~~X~"~bXLMode setting data
Mode setting data
Display data
* 1: READY output is indefinite during 12 clocks after the oscillation start
at power on (clock: OSC 2 clock).
*2: High pulse should be applied to SYNC terminal when using two or more
chips synchronously.
* 3: In the mode in which READY is always available, READY output is indefinite while SYNC is high.
* 4: Reset the 4-bit data counter after power on.
* 5: READY output period is within 3.5 clocks in the mode setting operation
and bit manipulation or within 10.5 clocks when the display data (8
bits) is updated.
* 6: Connect a pull-up resister if WE or RE may be floating.
* 7: It is not always necessary to follow this example.
Figure 15
Example of Data Transfer Sequence
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HD61602/HD61603
Notes on READY Output
Note that the READY output will be unsettled during 1.5 clocks (max) after in~tting
the first 2-byte data for setting the mode
after turning the power on. This is because
the READY bit data of mode setting latches
and the mode of READY pin (READY bus or
port mode) are unsettled until the completion
of mode setting.
There are two kinds of the READY output
waveforms depending of the modes:
1.
READY bus mode (READY bit = 0)
2.
READY port mode (READY bit
= 1)
However, if you input SYNC before mode
setting, waveform will be determined; when
you choose READY bus mode, (1) a in figure
16 will be output, and when you choose
READY port mode, (2) a will be output. The
figures can be applied both to HD61602 and
HD61603.
Power on
t
Do-D7~------------------------~~1~&;-' ~-;2~nd~~~~-----------------
~, READY output is unsettled.
V/J1
Mode setting data
(2-byte data)
r1 .5 .clocks
(max)
Mode setting latch is unsettled.
Mode setting data are
latched.
Power on
+
/
a
,
,\--------b
,
READY
'- _ _ _ _ _ _ _ J
Note: CS = low
Power on
(1)
~
READY Bus Mode 1.5 clocks (max)
/
READY
\
Note: CS
= low,
RE
(2)
Figure 16
= high
a
----"\
,
\
,
b
--------T
I
1 .5 clocks (max)
READY Port Mode
3.5 clocks (max)
READY Output According to Modes
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801
HD61602/HD61603
Standby Operation
Standby operation with low power consumption can be activated when pin SB is
used. Normal operation of the LSI is activated
when pin SB is low level, and the LSI goes
into the standby state when pin SB is high
level. The standby state of the LSI is as follows:
1.
2.
LCD driver is stopped (LCD is off).
Display data and operating mode are
held.
3.
4.
The operation is suspended while display
c~nges (while READY is outputting
low.) In this case, READY outputs high
within 10.5 clocks or 3.5 clocks after
release from the standby mode.
Oscillation is stopped.
When this mode is not used, connect pin SB to
Vss.
Multichip Operation
every SYNC operation.
When an LCD is driven with. two or more
chips, the driving timing of the LCD must be
synchronized. In this case, the chips are
synchronized with each other by using SYNC
input. If SYNC input is high, the LCD driver
timing circuit is reset. Apply high pulse to the
SYNC input after the operating mode is set.
If a power on reset signal is applied to the
SYNC pin, the LCD can be off-state when the
power is turned on.
A high pulse to the SYNC input changes the
mode setting data. (The OFF ION bit is set
and the READY bit is reset. See 3. Mode
Setting Data in "Input Data Formats".) Transfer the mode setting data into the LSI after
When SB input is used, after standby mode is
released, a high pulse must be applied to the
SYNC input, and mode setting data must be
set again.
When SYNC input is not used, connect pin
SYNC to Vss.
Restriction on Usage
Minimize the noise by insetting a noise bypass capacitor (;;; 1 )IF) between Voo and
Vss pins. (Insett one as near chip as possible.)
Liquid Crystal, Disj)lay Drive Voltage Circuit (HD61602)
What is LCD Voltage?
HD61602 drives liquid crystal display using
four levels of voltages (figure 17); Voo, Vl, V2,
and V3 (Voo is the highest and V3 is the
lowest). The voltage between Voo and V3 is
called VLCD and it is necessary to apply the
appropriate VLCO according to the liquid
crystal display. V3 always needs to be supplied regardless of the display duty ratio since it supplies the voltage to the LCD drive
circuit of HD61602.
Voo
Figure 17
LCD Output Waveform and
Output Levels
HITACHI
802
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD61602/HD61603
When Internal Drive Power Supply
is Used
When the internal drive power supply is
used, attach Cl-C4 for charge pump circuits
and variable resistance Rl for deciding display drive voltage to HD61602 as shown in
figure 18.
Internal voltage is available by setting
external voltage switching bits of mode setting data O.
Figure 19 shows voltage characteristics
between Voo and VREF1. Voltage is divided at
R1, and then input into VREF2. Voltage
between Voo and VREF2 is equivalent to a V in
figure 19, and so VLCO can be changed by
regulating the voltage.
VREF2 is usually regulated by variable resistance, but when replacing Rl with two
nonvariable resistances take VREFl between
max and,min into consideration as shown in
figure 19.
Internal drive power supply is generated by
using capacitance, and so large current cannot flow. When large liquid crystal display
panel is used, examine the external drive
power supply.
Power _~__-t__-41 Voo
11 Vss
I
Regulator
---,L-_
_
_ _----'
Voltage follower
19 VC 2
C2
C3
C4
20 V,
21
V2
22
V3
23-26 COM
77
SEGo
76
SEG,
75
SEG 2
LCD
Charge
pump
circuit
HD61602
R, = 1 MQ Variable
C,=0.3I'F
C2-C4=0.3I'F
C5 =0.1 to 0.31'F
C6 <;; 11'F
Flgure 18
Example
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
803
(
HD61602/HD61603
When External Drive Power Sup-
ply Is Used
An external power supply can be used by
setting extemal voltage switching bits of
mode setting data to 1. When a large'liquid
crystal display panel is used. in multichip
designs. which heed accurate liquid crystal
drive voltage. use the extemal power supply.
See figure 20.
Rs is connected in series between VDD
R2 -
and Vss. and by these resistance ratio each
voltage of Il.V and VLCD is generated and then
supplied to V1. V2. and V3. C2-C4 aresmoothing capacitors.
When regulating brightness. change the
resistance value by setting Rs variable resistance.
Voo-Vss (V)
2
~
3 4
I
1=
\
_'
I
I
5
6
:
I
i
.~
I
G 1.6 ------ ·---+--min
!
i
1.7
~
1.9 ____ "\~n__
\
> 1.8
c 2 .O
'=
\
> 2.1
I
i
typ
:
''.
:
------!:"' ....~---max
2.2
2.3
Voltage Characteristics
between VDD and Vraf1
Figuret9
Positive
Pcsltive
power
supply
Voo
V..
power
supply
C.
Vee
V..
VAEF1
VREF1
VA...
Ve,
Ve2
V,
V2
Va
VREF2
R:I
C.
Positive
power
Vee
V..
C.
supply
V"EF1
VREF2
Ve,
Ve2
V,
C2 R2
NC
NC
Ve,
VC2
V,
V2
V2
Va
Va
R.
ee;;: 1 pF
sa
sa
(1 )
Static Drive
(2)
1/2 DLity Cycle Drive
(3)
1/3 and 1/4 Duty Cycle Drive
Note: 1. When standby mode is used, a transistor is required.
2. R2-R5 should be some kQ-some tens of kQ, and C2-C4 should be 0.1 pF-0.3pF.
Figure 20
,
804
Example when External Drive Voltage is Used
HITACHI
.
Hitachi America, Ltd.· Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005~1819· (415) 589-8300
HD61602/HD61603
Liquid Crystal Display Drive Voltage (HD61603)
As shown in figure 21, apply LCD drive voltage from the external power supply.
Osclllation Circuit
When Internal Oscillation Circuit is Used
When External Clock is Used
When the internal oscillation circuit is used,
attach an external resister Rose as shown in
figure 22. (Insert Rose as near chip as possible,
and make the OSCl side shorter.)
When an external clock of 100 kHz with
CMOS level is provided, pin OSCl can be used
for the input pin. In this case, open pin OSC2.
C6
Positive power --_--t----t
supply
R,
-,
I
IT,
SB
I
_.J
Note: When standby mode is used, a transistor is required.
Figure 21
Example of Drive Voltage Generator
Rose
Rose
BOr
OSC,
791
OSC 2
801
OSC,
79[
OSC 2
"-
HD1~049UB
etc.
801
OSC,
---~c
I
79
OSC 2
Multichip operation
Figure 22
Example of Oscillation Circuit
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
805
HD61602/HD61603
Applications
+ 5V
-m
HD~:'
Au
C
Address bus
D,Do
R/W
r::e::
~
B
A'5
E
BA
~
A
AI4
.!i.....r
Data bus
I
Do
1
~bJ 11f /
+5V
I~ I~ I~ ~>-
Veo
READY
-,!,
~
....
I
0 0 -0, u OSC2
~ V REfl
(/)
so
Vss
Vee I-- +5V
Vss
HDBBOS
II
I
VAEF2
HD61602
"
I
+5V
~
CPU
+5V
-.
Voo
1 f~rOY
v..
V2
V3
---- SEG50
....,
I
"'~/ ~.~.'.-~-.=
V1
V COMo
V C2 COM3 SEGo
I I
>-
VREF 1 -
(I)
VAEF2 _
r
+5V
v,
HD61602
V
V,
"
V"
SEG 1 ~
_ ________
"
SE G50 V3
--------
--------.
--------
----- .... - ..
"
)
Uquid Crystal
Figure 23
5Vl11
A
A,
A,
..
HD74LS138
~
§
A
0
C
"
rrD
Address bus
0,
Data bus
Do
1
Do
'~ r1-/
B
+5V
R/W
Vee
V..
---.,.
!f
HDBBO9
CPU
JT 1
I~ I~ I~ ~ Do-D,
VOO
BEADY
SO
Vss
COM
+5V
Example (1)
Ir=
~
....
u
&
~~
+sv
HD14U /
rv..
M
V,
HD61603
~
rf
~
SEGo - .......... SEG83
------
-------
Figure 24
~!
I~ I~ It ~
--,
Do-D,
U>
I
~M
DY
HD61603
V,
SEGo -- - - - - - SEG",
--------
1
---------
)
Example (2)
HITACHI
806
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605--(Segment Type LCD Driver)
Description
Features
The HD61604 and the HD61605 are liquid
crystal display driver LSIs with TTL and
CMOS compatible interface. Each of the LSIs
can be connected to various microprocessors
such as the HMCS6800 series.
•
Low current consumption
-Can drive from a battery power supply
(100 JiA max on 5 V).
-Standby input enables a standby oper·
ation at lower current consumption (5
JiA max on 5 V).
•
Versatile segment drive capacity
Several types of liquid crystal displays can be
connected to the HD61604 according to the
applications because of the softwarecontrolled liquid crystal dispay drive method.
The HD61605 is a liquid crystal display driver
LSI only for static drive and has 64 segment
outputs that can display 8 digits per chip.
Display
Drive Method
Segments
Static
51
1/2 bias 1/2 duty cycle 102
1/3 bias 1/3 duty cycle 153
1/4 duty cycle 204
64
Static
Type No.
HD61604
HD61605
Frame Freq (Hz)
Example of Use
8 segments x 6 digits + 3 marks
8 segments x 12 digits + 6 marks
9 segments x 17 digits
8 segments x 25 digits + 4 marks
8 segments x 8 digits
at to.c=100 kHz
98
195
521
781
98
Pin Arrangement
HD61604
HD61605
i~rer::.~:ertJ:!~~~!:$S$$
Voo L..
64p. SEG"
'
3
"t: SEG'4
SEG"
RE ~ •
~~g:'s
r-
READY
1=
CSL..
WE'"
2
63
,..
4
611=
SEG,s
:p.
1=
,sp. SEG,.
"1= SEG,o
"1= SEG"
551= SEG"
641= SEG"
"1= SEG,.
62p. SEG"
S8,- '
0, j: ,
0, '- •
d. [ •
D.::: '0
v55 [ "
o
r
12
O~ 1= "
D,
14
51
Do
16
49r-
~~~ = ::
VC 1 == ,.
V, = '0
V
V' =
COM
1
==
SEG26
SEG"
SEG
.. 1= SEG~:
V
COM~
F
50 ...
V R£Fl
21
47F=
SEG 30
..
SEG"
SEG"
44
22
43
23
24
.2
.,
:!l~~:sreg;;;~::l~~:il:;:e:~~
II II
II II II 1111 II II II II
SEG 33
=' SEG,.
= SEG"
SEG,s
(Top View)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
807
HD61604/HD61605
Block Diagram
HD61604
LCD drive
timing
generator
READY __~_--,
Common output
(4 lines)
RAM write
timing generator
Parallel/serial
converter
Segment output
(51 lines)
Address
de~er
Operation
mode
LCD drive
voltage
Drive
voltage
selection
Figure 1 HD61604 Block Diagram
HD61605
LCD drive
timing
generator
.cs..
~
0 0 -03
58
Common
output
RAM write
timing generator
Parallel/serial
converter
Segment
output
(64 lines)
Address
decoder
Figure 2 HD61605 Block Diagram
HITACHI
808
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Pin Functions
Table 1 shows the HD61604 pin description..
Table 2 shows the HD61605 pin description.
VDD: Positive power supply.
Vss: Negative power supply.
H061604 Pin Function
H061605 Pin Function
READY (Ready): During data setting in the
display data RAM and mode setting latch in
the LSI after data transfer, low is output to
the READY pin to inhibit the next data input.
There are two modes: one in which low is
output only when both of CS and RE are low,
and the other in which low is output regardless of CS and RE.
CS (Chip Select): Chip select input. Data can
be written only when this pin is low.
WE (Write Enable): Write enable input.
Input data of Do to D7 is latched at the positive
edge of WE.
RE (Reset): Resets the input data byte
counter. After both of CS and RE are low, the
first data is recognized as the 1st byte data.
SB (Standby): High level input stops the LSI
operations.
1.
2.
3.
Stops oscillation and clock input.
Stops LCD driver.
Stops writing data into display RAM.
READY (Ready): During data setting in the
display data RAM and mode setting latch in
the LSI after data transfer, low is output to
the READY pin to inhibit the next data input.
There are two modes: one in which low is
output only when both of CS and RE are low,
and the other in which low is output regardless of CS and RE.
CS (Chip Select): Chip select input. Data can
be written only when this pin is low.
WE (Write Enable): Write enable input.
Input data of Do to Da is latched at the positive edge of WE.
RE (Reset): Resets the input data byte
counter. After both of CS and RE are low, the
first data is recognized as the first byte data.
SB (Standby): High level input stops the LSI
operations.
1.
2.
3.
00-07 (Data Bus): Data input pin from
which a-bit x 2-byte data is input.
SYNC (Synchronous): Synchronous input
for 2 or more chip applications. LCD drive
timing generator is reset by high input. LCD
is off.
COMo -COM 3 (Common): LCD common
(backplate) drive output.
SEGo -SEG60 (Segment): LCD segment
drive output.
Stops oscillation and clock input.
Stops LCD driver.
Stops writing data into display RAM.
00- 03: Data input pin from which 4-bit x 4byte data is input.
SYNC (Synchronous): Synchronous input
for 2 or more chips application. LCD drive
timing generator is reset by high input. LCD
is off.
COMo (Common): LCD common (backplate)
drive output.
SEGo -SEGsa (Segment): LCD segment
drive output.
Vt, Vz, V3 (LCD Voltage): Power supply for
LCD drive.
OSC1, OSC2 (Oscillator): Attach external R
to these pins for oscillation. An external clock
(100 kHz) can be input from eSC1.
OSC1, OSC2 (Oscillator): Attach external R
to these pins for oscillation. An external clock
(100 kHz) can be input from eSC1.
V3 (LCD Voltage): Power supply input for
LCD drive.
Vet, Vcz: Do not connect any wire.
VRBF1: Connect this pin to Vl pin.
Voltage between
voltage.
VRD'z: Hold at
Vss: Negative power supply.
VDD
level.
VDD
and Va is used as drive
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
809
HD61604/HD61605
VDD: Positive power supply.
Table 1
Table 2
HD61604 Pin Description
Do-D7
No.of
Lines Input/Output
NMOS open
drain output
Input
Input
Input
1
Input
Input
8
SYNC
1
COMoCOM3
4
Input
Output
SEGoSEGso
51
Output
LCD
SEGo-SEG63
OSC1,
OSC2
VI, V2, V3
OSC1,
OSC2
3
Power supply
External R
2
Input, output
External R
Vel, VC2
2
Output
Pin
Name
READY
CS
WE
RE
S8
Connected
to
MCU
Pin
Name
READY
MCU
MCU
MCU
MCU
MCU
CS
WE
RE
S8
MCU
LCD
SYNC
VREFI
Input
VI
VREF2
Input
Voo
Voo
Power supply
Vss
Power supply
Do-£>:!
HD61605 Pin Description
No.of
Lines Input/Output
NMOS open
drain output
Input
Input
Input
Input
Input
4
Connected
to
MCU
MCU
MCU
MCU
MCU
MCU
Input
Output
MCU
LCD
64
Output
LCD
2
Input, output
External R
V3
Input
Power
supply
Vss
Power supply
Voo
Power supply
COMo
Note: Logic polarity is positive.
1 = high = active.
Note: Logic polarity is positive.
1 = high = active.
HITACHI
810
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Display RAM
8D61604 Display RAM
The HD61604 has an internal display RAM
shown in figure 3. Display data is stored in
the RAM, or is read according to the LCD
drive timing to display on the LCD. One bit of
the RAM corresponds to 1 segment of LCD.
Note that some bits of the RAM cannot be
displayed depending on LCD drive modes.
timings of a common output and a segment
output. The same common address data is
simultaneously read. The data of display RAM
is reproduced on the LCD panel.
The following shows the correspondence
between the 7-segment type LCD connection and the display RAM in each mode.
1.
Reading Data from HD61604 Display
RAM
Static Drive: In static drive, only the
column of COMo of display RAM is output.
COMl to COM:! are not displayed (figure
4).
A display RAM segment address corresponds
to a segment output. The data at segment
address SEGn is output to segment output
SEGn pin.
2.
A common address corresponds to the output
1/2 Duty Cycle Drive: In the 1/2 duty
cycle drive, the columns of COMo and
COM 1 of display RAM are output in time
sharing. The columns of COM2 and
COM:! are not displayed (figure 5).
Common address
(COM o-COM 3 )
l~·~{L_~
"
,----
Display RAM
~~----------------------v.----------------------~j
51 bits
Segment address (SEG o-SEG 50 )
Figure 3
Display RAM (8D61604)
LCD connection
Dis~lay
RAM
COM3
COM2
COM,
COMo
Figure 4
f
e
d
c
DP
g
b
a
Example of Correspondence between LCD Connection and Display RAM
(Static Drive, 8D61604)
HITACHI
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811
HD61604/HD61605
3. 1/3 Duty Cycle Drive: In the 1/3 dutv
cycle drive, the columns of COMo to COM
2 are output in time sharing. No column of
COM:! is displaved. "V" cannot be rewritten bV displav data (input on an 8-segment basis). Please use bit manipulation
in turning on/off the displaV of "V" cvcle
(figure 6).
.
4. 1/4 Duty Cycle Drive: In the 1/4 dutV
cy~le
drive, all the columns of COMo to
COM:! are displaved (figure 7).
LCD connection
a
Display RAM
COM,
a
9
c
COMo
fed
b
DP
. ..
lil lil
II)
II)
FigureS
Example of Correspondence between LCD CODllection and Display RAM
(1/2 Duty Cycle, 8D61604)
LCD connection
Display RAM
COM3
Figure 6
V 1/ /
COM 2
y
a
b
COM,
f
9
c
COMo
e
d
DP
Example of Correspondence between LCD Connect1on and Display RAM
(1/3 Duty Cycle, 8D61604)
LCD connection
a
Figure 7
,-------COMa
Display RAM
COM 3
f
a
COM2
9
b
COM,
e
c
COMo
d
DP
Example of Correspondence between LCD Connection and Display RAM
(1/4 Duty Cycle, 8D61604)
HITACHI
812
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Writing Data into HD61604 Display RAM
Data is written into the display RAM in the
following five methods:
4. 1/3 Duty Cycle Display Mode: 8-bit
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/3
duty cycle drive.
1.
5. 1/4 Duty Cycle Display Mode: 8-bit
Bit Manipulation: Data is written into
any bit of RAM on a bit basis.
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/4
duty cycle drive.
2. Static Display Mode: 8-bit data is written on a digit basis according to the 7segment type LCD pattern of static drive.
3. 1/2 Duty Cycle Display Mode: 8-bit
data is written on a digit basis according
to the 7-segment type LCD pattern of 1/2
duty cycle drive.
.
(1)
(2) 1/2 Duty Cycle
Ststic
The RAM area and the allocation of the segment data for i-digit display depend on the
drive methods as described in the section of
"Reading Data from Display RAM".
8-bit data is written on a digit basis corresponding to the above duty drive methods.
The digits are allocated as shown in figure 8.
(3) 1/3 Duty Cycle
Display
COMoCOM ,COM2
(4) 1/4 Duty Cycle
Display
Display
COM oCOM,COM2
COM oCOM,COM2COM 3
SEGo
SEGo
SEGo
SEG,
SEG,
SEG,
SEG2
SEG2
SEGz
SEG3
SEG3
SEG3
SEG4
SEG4
SEG4
SEGs
SEG5
SEG5
SEGB
SEGB
SEG8
SEG7
SEGB
SEG7
SEG7
SEGs
SEG s
SEG g
SEG g
SEGg
SEG,o
SEG,o
SEG,o
SEG"
SEG"
SEG"
SEG'2
SEG'2
SEG'2
SEG'3
SEG'3
SEG'3
SEG'4
SEG'4
SEG'4
SEG'6
SEG'5
SEG'7
SEG 17
SEGo
AdO
/-+--+--i/
Ad1
1-+-+--1
Ad2
I-+--+---f
Ad3
/-+--+--i/
SEG2
Ad1
SEG3
SEG4
Ad2
SEGs
SEGs
Ad3
SEG7
SEG8
Ad4
SEG g
SEG,o
Ad5
SEG"
SEG'2
Ad4
1-+-+--1
Ad6
SEG'3
SEG'4
Ad7
SEG'5
Ad5
SEG'8
SEG'8
AdO
SEG,
1-+-+--1
Ad6
SEG'B
Ad8
SEG 17
SEG,s
1'1.
SEG 60
L..-_...K...~
Figure 8
SEG 60
Ad16
Ad24
Ad25
Allocation of Digits (HD61604)
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813
HD61604/HD61605
As the data can be transferred ona digit basis
from a microprocessor, transfer efficiency is
improved by allocating the LCD pattern
according to the allocation of each bit data of
the digit in the data RAM.
However, when the digit address is Ad6 of
static, Ad12 of 1/2 duty cycle, or Ad25 of 1/4
duty cycle, display RAM does not have
enough bits for the data. Thus the extra bits
of the input 8-bit data are ignored.
Figure 8 shows the digit address (displayed
as Adn) to specify the store address of the
transferred 8-bit data on a digit basis.
In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, I-bit display data, a segment address (6 bits)s and a common address
(2 bits) should be specified.
Figure 9 shows the correspondence between
each segment in an Adn and the 8-bit input
data.
HD61606 Display RAM
When data is transferred on a cUgit basis, 8bit display data and digit address should be
, specified as described ab~ve.
(1)
Static Display
(2)
1/2 Duty Display
COMo
SEG8
The HD61605 has an internal display RAM as
shown in figure 10. Display data is stored in
the RAM and output to the segment output
pin.
(3)
COM o COM 1
Bit
7
SEG4n
SEG8n+l
SEG4n+2
SEG8n+2
SEG4n+3
SEG8n+3
7
6
SEG3n+l
5
4
3
SEG3n+2
2
1
Bit
6
SEGsn
5
4
3
2
1
Bit
0
0
1/4 Duty Display
Bit
7
6
5
4
3
2
1
Bit
SEG8n+7
SEG2n+l
Figure 9
8it
8it
7
(4)
1 bit
1/3 Duty Display
0
Bit Assignment In an Adn (HD61604)
{I
I
(COM~ t,::::::::::::::::::::::D:iS:P:I~~y:R:A:M::::::::::::::::::::::::~;
64 bits
Segment address (SEGo-SEGnl
Figure 10
Display RAM (8061606)
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HD61604/HD61605
Reading Data from HD61605 Display
RAM
Each bit of the display RAM corresponds to
an LCD segment. The data at segment
address SEGn is output to segment output
SEGn pin. Figure 11 shows the correspondence between the 7-segment .type LCD
connection and the display RAM.
Writing Data into HD61605 Display RAM
Data is written into the display RAM in the
following two methods:
1.
Bit Manipulation: Data is written into
any bit of RAM on a bit basis.
2.
Static Display Mode: 8-bit data is written on a digit basis according to the 7segment type LCD pattern of static drive.
The 8-bit data is written on a digit basis into
the digit address (displayed as Adn) shown in
figure 12. When data is transferred from a
microprocessor, four 4-bit data are needed to
specify the digit address and an 8-bit display
data. Figure 13 shows the correspondence
between each segment in an Adn and the
transferred 8-bit data.
In bit manipulation, anyone bit of display
RAM can be written. When data is transferred on a bit basis, 1-bit display data and a
segment address (6 bits) should be specified.
LCD connection
Display RAM
Figure 11
Example of Correspondence between LCD Connection and Display RAM
(HD61605)
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815
HD61604/HD61605
COMo
SEGo
SEG ,
SEGz
SEG3 AdO
SEG4
SEGe
SEG8.
SEG7
SEGa
SEG8
SEG '0
SEGl1 Ad1
SEG12
SEGan
SEG45
SEG48
SEG47
SEG48
SEG48
SEG50
SEG51 Ad6
SEG&2
SEG 63
SEG'3
SEG54
SEG'4
SEG55
SEG'5
SEG 51
SEG'8
SEGI7
SEGe7
SEG ,
SEG51
SEG '8 Ad2 SEG&8 Ad7
SEGzo
SEG80
COMo
Bit
7
SEG8n +1
6
SEG8n+3
4
SEG 8n +4
3
SEG 8n +6
2
SEGZI
SEG22
SEG23
SEG24
Figure 12 AllOcation of Digits
(HD61605)
Figure 13 Bit Assignment in an Adn
(HD 61605)
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HD61604/HD61605
Operating Modes
HD61604 Operating Modes
· 1/2 duty cycle display mode: a-bit data
is written into the display RAM according to the digit in 1/2 duty cycle drive.
The HD61604 has the following operating
modes:
·1/3 duty cycle display mode: a-bit data
is written into the display RAM according to the digit in 1/3 duty cycle ~rive.
LCD Drive Mode: Determines the LCD
1.
drive method.
· 1/4 duty cycle display mode: a-bit data
is written into the display RAM according to the digit in 1/4 duty cycle display
drive.
· Static drive mode: LCD is driven
statically.
· 1/2 duty cycle drive mode: LCD is driven
with 1/2 duty cycle and 1/2 bias.
READY Output Mode: Determines the
3.
READY output timing.
· 1/3 duty cycle drive mode: LCD is driven
with 1/3 duty cycle and 1/3 bias.
After a data set is transferred, the data is
processed internally. The next data cannot be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:
·1/4 duty cycle drive mode: LCD is driven
with 1/4 duty cycle and 1/3 bias.
2.
Data Display Mode: Determines how to
write display data into the data RAM.
• Static display mode: a-bit data is written into the display RAM according to
the digit in static drive.
· READY is always available (figure 14).
· READY is made available by CS and RE
(figure 15).
------...,/
''I-I- - I
WE~
READY
Data transfer
:"--/
I
"~
__________________________--J,II
I
1
I
I
I
I
I
- - - _• ..j'...._ - - - - - - - I n p u t i n h i b i t - - - - - -......
oo-!'
~ri~
~ri~
I
I
f-- Next data
transfer
Figure 14 READY Output Timing (When It is Always Available)
,I
cs
,I
).
I
~
WE
I
RE
I
I
READY
Data transfer
period
I
I
I
I
"I-
'\
I
'\
1
I
I
I
I
I,
~
I
AI
1
"--.V.
Input inhibit
peri~
,I
)..
,I
'-./lI
-I
I
I
I
I
i
I
I
I-
Next data
transfer
Figure 15 READY Output Timing (When It is Made Available by CS and RE)
HITACHI
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817
HD61604/HD61605
After a data set is tranSferred, the data is
processed internally. The next data cannot be acknowledged during the processing period. The READY output reports
the period to the MPU. The timing when
READY is output can be selected from the
following two modes:
4. LCD Off Mode: In this mode, the
HD61604 stops driving the LCD and turns
it off.
The above 4 modes are ,specified by mode
setting data. The modes are independent of
each other and can be used in any combination. The bit manipulation is independent of
data display mode and can be used regardless of it.
• READY is always available (figure 16).
• READY is made available by CS and RE
(figure 17).
HD6160& Operating lIIodes
The HD61606 has the following operating
modes:
1.
2: LCD Off lIIode: In this mode, the
HD61606 stops driving the LCD and turns
it off.
READY Output Mode: Determines the
READY output timing.
\~I
------".--;/
/!
READY - - - - -....,
I
~I-------------~
I
I
I
Data transfer--..,.....
I ••- - - - - - - l n p u t i n h i b i t - - - - - - - o..
-.l1
period
period
I
I
14- Next data
transfer
Figure 16 READY Output Timing (When It is Always Available)
cs
/
~I
WE
~
READY
Data transfer
period
I
I
I
I
I
I
-I-
/
\.
II
\
f\.-./
I
\
I
I
I
I
-1
I
'---...V
Input inhibit
period
/
).
I
I
'--./1I
"I
II
I
I
I
I
I-- Next data
transfer
Figure 17 READY Output TIming (When It Is Made Available by CS and
D.)
HITACHI
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Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Input Data Formats
HD61604 Input Data Formats
3.
Input data is composed of 8 bits X 2 bytes.
Input them as 2-byte data after READY output changes from low to high or low pulse
enters into RE pin.
Mode Setting Data:
1st byte
7
1.
x I
0
6
5
4
x
x
5
4
1:~Dy~~e :model
3
2
1
0
Display Data: Updates display on an 82nd byte
segment basis.
x
Display address
(Digit address Adn)
765
4
3
o
2
• Display address: Digit address Adn in
accordance with display mode
· Display data: Pattern data written into
the display RAM according to display
mode and the address
Bit Manipulation Data: Updates display
on a segment basis.
1st byte
I I
0
7
I~!:~YI
x
x
x
5
4
3
2
6
~~~ss I
1
0
2nd byte
I I I
x
7
S~G ad~ress :
x
6
5
4
3
2
x
6
I
I
x
3
IOFF/oi
Disp;ay . I
bit
mode bits
2
1
0
· Display mode bits:
00: Static display mode
01: 1/2 duty cycle display mode
10: 1/3 duty cycle display mode
11: 1/4 duty cycle display mode
• OFF/ON bit:
1: LCD off (set to 1 when SYNC is
entered)
0: LCD on
· Drive mode bits:
00: Static drive
01: 1/2 duty cycle drive
10: 1/3 duty cycle drive
11: 1/4 duty cycle drive
· READY bit:
0: READY bus mode: READY outputs 0
only while CS and RE are 0 (reset to
o when SYNC is entered)
1: READY port mode: READY outputs
o regardless of CS and RE
2nd byte
I :
I
7
43210
2.
0
Note: Input the same data to display mode bits
and drive mode bits.
4.
0
• Display data: Data written into 1 bit of
the specified display RAM
· COM address: Common address of display RAM
· SEG address: Segment address of display RAM
1-Byte Instruction: The first data (first
byte) is ignored when the bit 6 and bit 7
in the data are 1.
1st byte
7
6
5
4
3
2
o
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819
HD61604/HD61605
Mode Setting Data:
3.
HD61605 Input Data Formats
I1
: 0
3
2
Display Data: Updates display on an 8-
1.
3rd
segment basis.
I
1st byte
I :
0
0
3
2
x
x
x
0
3
3rc! byte
Display data
4
Bit 17 6
5
0
2
3
Display address
(Digit address Adn)
0
2
Bit3
2
0
· Display address: Digit address Adn
shown in figure 12.
· Display data: Pattern data written into
the display RAM as shown in figure 13.
4.
Bit Manipulation Data: Updates display
2.
on a segment basis.
1st byte
I 03
:
2
x
1
0
II
3rc! byte
I
0
0
byte
x : x
3
I
0
x
I~~DYI
3
2
x : x
0
4th byte
byte
<
x : x : x
3
II
II x ~~F/OJ
3
0
2
0
2
<
2
1~~~5a~d~1
0
I : I
x
>
I
0
1
0
SEG address
Bit3
3
2
2
1
0
0
· Display data: D~ta written into the 1 bit
of the specified display RAM.
· SEG address: Segment address of display RAM (segment output).
HITACHI
820
0
bits) is ignored when the bit 3 and bit 2 in
the data are 1.
320
2
0
I-Byte Instruction: The first data (4
4th byte
x
3
I
1st byte
2nd
I~:~·vl
x
byte
. OFF/ON bit:
1: LCD off (It is set to 1 when SYNC is
entered)
0: LCD on
. READY bit:
0: READY bus mode: READY outputs 0
only while CS and RE are 0 (reset to 0
when SYNC is entered)
1: READY port mode: READY outputs 0
regardless of CS and RE
Display data
1
0
2
3
2nd
1st byte
Input data· is composed of 4 bits x 4 bytes.
Input them as four 4-bit data after READY
output changes from low to high or low pulse
enters into RE pin.
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
How to Input Data
Bow to Input Data Into B061604
1.
Input data is composed of 8 bits x 2 bytes.
Take care that the data transfer is not inter- .
rupted because the first 8-bit data is distinguished from the second one by the sequence
only.
When data transfer is interrupted, or at
power on, the following two methods can be
used to reset the count of the number of
bytes (count of the first and second bytes):
Set CS and RE to ldyv (no display data
changes).
2. Input 2 or more 1-byte instruction data
whose bit 7 and 6 are high (display data
may change).
The data input method via data input pins
(CS, WE, Do to D,) is similar to that of static
RAM such as HM6116. Access to the LSI can
be made through the same bus line as ROM
and RAM. When output ports of a microprocessor are used for access, refer to the
timing specifications and figure 18.
Power on
~
~
I
CS
WE
RE
.,
I
,
r-
'*6
'*6
READY
I
~*4
C::::,/ * 1
SYNC __________~n--------------~r--\~*-2---------------------11
58
.
1st 2nd
1st 2nd
1st 2nd
0 0 -07 ~~r~x~~x~--------~xr=;x~~x~------~X~~X~~x~-Mode setting data
Mode setting data
Display data
* 1: READY output is indefinite during 12 clocks after the oscillation starts at power on (clock:
OSC2 clock).
* 2: High pulse should be applied to SYNC pin when using two or more chips simultaneously.
*3: In the mode in which READY is always available, READY output is indefinite while high
is being applied to SYNC.
*4: Reset the byte counter after power on.
* 5: READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated.
*6-: Connect a pull-up resistor if WE or RE is floating.
*7: It is not always necessary to follow this example.
Figure 18 Example of Data Transfer Sequence
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821
HD61604/HD61605
How to Input Data into HD61605
1.
Input data is composed of 4 bits x 4 bytes.
Take care that the data transfer is not interrupted because the first 4-bit data to the
fourth 4-bit data are distinguished from each
other by the sequence only.
2.
Set CS and RE to low (no display data
changes.)
Input 4 or more i-byte instruction data
(4-bit data) whose bit 3 and 2 are high
(display data may change).
The data input method via data input pins
(CS, WE Do to D3) is similar to that of static
RAM such as HM6116. Access to the LSI can
be made through the same bus line as ROM
and RAM. When output ports of a microprocessor are used for access, refer to the
timing specifications and figure 19.
When data transfer is interrupted, or at
power on, the following two methods can be
used to reset the count of the number of data
(count of the first 4-bit data to the fourth 4bit data):
Power on
~r------~I'~~______-Jlr------'\~____-Jlr-----'\~____-JrWE
'*6
RE
~~*~4---------------------------------------
R~Dy[:::~S~--------~~~::'T/--~--,~r--------.~
*1
SYNC
*5
*3
*5
*5
________~»~---------------Jr\~*~2~-----------------------
58
1st 2nd 3rd 4th
0 0 -0 3 ----<:::)-iJ---('-..&.X~X:lo...LX:lo...LX~
Mode setting data
1st 2nd 3rd 4th
1st 2nd 3rd 4th
____...t.X~-...t.X~X:lo...Lx.....,'£;X~__---I.X~X:lo...LX~X"",X~
Mode setting data
Display data
* 1: READY output is indefinite during 12 clocks after the oscillation starts at power on (clock:
OSC2 clock).
*2: High pulse should be applied to SYNC pin when using two or more chips simultaneously.
*3: In the mode in which READY is always available, READY output is indefinite while high
is being applied to SYNC.
4: Reset the 4-bit data counter after power on.
*5: READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated.
*6: Connect a pull-up resistor if WE or RE is floating.
7: It is not always necessary to follow this example.
*
*
Figure 19 Example of Data Transfer Sequence
HITACHI
822
Hitachi America, Ltd. 0Hitachi Plaza 0,2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0 (415) 589-8300
HD61604/HD61605
Notes on READY Output
Note that the READY output will be. unsettled during 1.5 clocks (max) after inputting
the first 2-byte data for setting the mode
after turning the power on. This is because
the READY bit data of mode setting latches
and the mode of READY pin (READY bus or
port mode) are unsettled untill the completion of mode setting.
1.
READY bus mode (READY bit = 0)
2.
READY port mode (READY bit = 1)
However, if you input SYNC before mode
setting, waveform will be determined; when
you choose READY bus mode, (1) a in figure
20 will be output, and when you choose
READY port mode, (2) a will be output. The
figures can be applied both to HD61604 and
HD61605.
There are two kinds of the READY output
waveforms depending on the modes.
Power on
~
Do- D7 r---------------------__--<
1st
2nd
~,. READY output is unsettled.
V//i
Mode setting data
(2-byte data)
f 1.5 .clocks
(max)
Mode setting latch is unsettled.
Mode setting data
are latched.
Power on
t
'---_-{I
READYr-----------------------------~,-,- ---~----/~
'" _ _ _ _ _ _ _ J
I
\ ' - -_ _J
Note; CS = low
(1 )
READY
Bus Mode 1.5 clocks (max)
Power on
~
/
/
a
READY
------~
\ \~ __b____\
Note; CS
I
= low, RE = high
(2)
/
\
1 .5 clocks (max)
READY
Port Mode
3.5 clocks (max)
Figure 20 READY Output According to Modes
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823
HD61604/HD61605
Standby Operation
Standby operation with low power consumption can be activated when pin SB is
used Nonnal operation of the LSI is activated
when pin SB is low level, and the LSI goes
into the standby state when pin SB is high
level. The standby state of the LSI is as follows:
1.
2.
LCD driver is stopped (LCD is off).
Display data and operating mode are
3.
4.
held.
The operation is suspended while display
changes (while READY is outputting
low.) In this case, READY outputs high
within 10.S clocks or 3.S clocks after
release from the standby mode.
Oscillation is stopped.
When this mode is not used, connect pin SB to
Vss.
Multi Chip Operation
When an LCD is driven with the two or more
chips, the driving timing of LCD must be
synchronized. In this case, the chips are
synchronized with each other by using SYNC
input. If SYNC input is high, the LCD driver
timing circuit is reset. Apply high pulse to the
SYNC input after the operating mode is set.
A high pulse to the SYNC input changes the
mode setting data. (The OFF ION bit is set
and the READY bit is reset. See (3) Mode
Setting Data in "Input Data Formats".) Transfer the mode setting data into the LSI after
every SYNC operation.
If a power on reset signal is applied to the
SYNC pin, the LCD can be off-state when the
power is turned on.
When SYNC input is not used, connect pin
SYNC to Vss.
When SB input is used, after standby mode is
released, high pulse must be applied to the
SYNC input, and mode setting data must be
set again.
Restriction on Usage
Minimize the noise by inserting a noise bypass capacitor (~ 1 pF) between VDD and
Vss pins. (Insert one as near chip as possible.)
Liquid Crystal Display Drive Voltage CirCUIt (HD61604)
What is LCD Voltage?
ce it supplies the voltage to the LCD drive
circuit of HD61604.
HD61604 drives liquid crystal display using
four levels of voltages (figure 21); VDD, Vl, V2,
and V3 (VDD is the highest and V3 is the
lowest). The voltage between VDD and V3 is
called VLCD and it is necessary to apply the
appropriate VLCD according to the liquid
crystal display. V3 always needs to be supplied regardless of the display duty ratio sin-
Connecting R2 - RS in series between VDD
and Vss (figure 22) generates fj. V or VLCD by
using the resistance ratio to supply these
voltage to pins Vl, V2, V3. C2-C4 are the
smoothing capacitors. Connect a trimmer
potentiometer for RS and change its resistance value to control the contrast.
HITACHI
824
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Voo
Figure 21
LCD Output Waveform and
Output Levels (1/3 Duty
Cycle, 1/3 Bias)
Positive
C.
power
supply
R,
C.
VDD
Vss
Positive
C.
power
supply
Vee
Vss
Positive
power
supply
Vee
Vss
C.
VREF1
V REFl
V REF2
V REF1
Ve,
VC2
V,
V,
Ve,
VC2
V,
V3
V,
V,
Va
V3
V REF2
VREF2
C, R,
NC
NC
Ve,
Ve,
V,
C s ;;;; 1 pF
S8
(1 )
Static Drive
(2)
1/2 Duty Cycle Drive
(3)
1/3 and 1/4 Duty Cycle Drive
Note: 1 When standby mode is used, a transistor is required.
2 R2-R5 should be some kCl-some tens of kCl, and C2-C4 should be 0.1 .uF-0.3 .uF.
Figure 22 Example when External Drive Voltage is Used
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
825
HD61604/HD61605
Liquid Crystal Display Drive Voltage (HD61605)
As shown in figure 23, apply LCD drive voltage from the external power supply.
Oscillation Circuit
When Internal Oscillation Circuit is
Used
When External Clock is Used
When an external clock 6.£ 100 kHz V'lith
CMOS level is provided, pin eSCl can be used
for the input pin. In this case, open pin OSC2.
When the internal oscillation circuit is used,
attach an external resistor Rose as shown in
figure 24. (Insert Rose as near ehip as possible,
and make the OSCl side shorter.)
Cs
Positive power -----...~..-__4
supply
SB
Note: When standby mode is used, a transistor is required.
Figure 23 Example of Drive Voltage Generator
Rose
Rose
"
v
801
OSC1
791
OSC2
801
OSC1
HD14049UB
79{
etc.
OSC2
801
OSC1
79~IC
OSC2
Multichip operation
Figure 24 Example of Oscillation Circuit
HITACHI
826
Hitachi America, Ltd.· Hitachi Plaza • 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
Applications
HD74LS138
,..--
+5
:;
V-m
A
A"
A"
A"
B
C
Address bus
.!i....t
-::D
=
D,H-~D~.~W~bus----~Q~.----~-----+-r--~~r----------------------r-r--~~---------;,
~H-~~~--~----~----~-4I~~-------------------+4-~I~------~
.
II
+5V
J-/I~I~I~~
i
>
en
Voo
~~---fREADY
Vee- +5V
V"-;J,.
HD6809
~~
r
;;-
+5 V-
I
...
0, D,u DSC2
~
V AEf1
r;
I~
+5V
I -
v,,.!
f
i*
V2
~---SEG50
I I
I
i
"'1~1~~D,-D,OSC'OSC2
vt /
r--~Voo
READY
VAEF 2
HD61604
COMo
V e1
I
VC2COM3SEGo
HD~D49UB
V3:....~
~:
>
en
V REfl [
VAEF2
HDBI6D4
V
V,
V2
Cl
t-;SV
Va
SEG,-- ________ SEG60V3
...........-......--------HI+t+------'t----itl-----'
CPU
)
Uquid cryswl
Figure 25 Example (1)
-
HD74LS138
5Vlll
..
A,
A,
,
Address bus
0,
RiW
~
cf-
Ve
Vss
fir
[fD
rL/ I I
!f
+5V
I~ I~ I~ ~
Voo
READY
SB
Vss
+5V
Ir=
~
....
I
0,-0,
I
/'
/"
0,
Ve,
V"
COM
HDB809
CPU
~
--
G
Data bus
0,
BA
:;:
A
B
C
A,
~ '"
0
N
0
0
:
HD61605
V,
+5V
_~
I~ I~ I~ ~
HDI4D4p /
r-:
~
SEGc------ SE<>.:,
rf
~
Veo
~=s
Ve,
Ve,
DY
OO-D3
N
ou
~~
'"
HD61B05
V,
SEGo -- - - - - - SEGel
-------
--------
... ------
--.------
)
Figure 26 Example (2)
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
827
HD61604/HD61605
Absolute Maximum Ratings
Item
Symbol
Limit
Unit
-0.3 to + 7.0
v
Pin voltage'
-0.3 to Voo + 0.3
v
Operating temperature
-20 to + 75
Power supply voltage'
Storage temperature
-55 to + 125
=
*Value referenced to Vss 0 V.
Note: If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using them within electrical
characteristics limits is strongly recommended for normal operation. Use beyond these conditions will cause
malfunction and poor reliability.
Recommended Operating Conditions
Limit
Item
Symbol
Min
Max
Unit
Voo
4.5
5.5
V
0
Voo
V
Pin voltage'
0
Voo
V
Operating temperature
-20
+75
°c
Power supply voltage'
*Value referenced to Vss
Typ
=0 V.
Electrical Characteristics
DC Characteristics
(Vss = 0 V, Voo = 4.5 V to 5.5 V, Ta = -20·C to +75·C, unless otherwise noted)
Symbol Min
Item
Input high voltage
Input low voltage
Limit
Typ
Max
Unit
-
VOD
V
V
OSC1
VIH1
Others
VIH2
2.0
VOD
OSC1
VIL1
0
0.2VOD V
0
0.8Voo
Test Condition
Others
VIL2
0.8
V
Output leakage
current
READY
IOH
5
pA
Pull up the pin to VOO
Output low
voltage
Input leakage
current
*1
READY
VOL
0.4
V
IOL=0.4 rnA
Input
pin
IIL1
-1.0
1.0
pA
LCD driver voltage
drop
V1
hL2
-20
20
pA
V2, V3
hL3
-5.0
5.0
pA
COMo-COM3
Vd1
0.3
V
± Id = 3 pA for each
COM, V3=VOO to 3 V
SEGo-SEG5o
Vd2
0.6
V
± Id;'" 3 pA for each
SEG, V3=VOO to 3 V
100
100
pA
During display *
Rosc=360 kO
IDO
5
pA
At standby
Current consumption * 2
, Except the transfer operation of display data and bit data.
'1 V1• V2 : applied only to HD61604.
'2 Do not connect any wire to the output pins and connect the input pins to Voo or Vss.
HITACHI
828
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD61604/HD61605
AC Characteristics
(Vss = 0 V, Voo = 4.5 V to 5.5 V, Ta = -20·C to +75·C, unless otherwise noted)
Limit
Symbol
Item
Min
TvP
Malt
Unit
Test Condition
Rose = 360 k{l
Oscillation frequency
OSC2
fosc
70
100
130
kHz
External clock frequency
OSC1
fosc
70
100
130
kHz
External clock duty
OSC1
Duty
40
50
60
ts
400
ns
tH
10
ns
tWH
300
ns
tWl
400
ns
tWA
400
ns
110 signal timing
1.0
tOl
Input signal rise and fall time
%
Ils
Figure 31
ns
tEN
400
t OP1
9.5
10.5
Clock
For display data transfer
tOP2
2.5
3.5
Clock
For bit and mode
data transfer
25
ns
tf'tf
CS
t-----twH-----t
t----twL--_-I
t----ts'--..-..j
Figure 27
Write Timing (RE is fixed high and SYNC low)
twR----t
I
tOL
READY
Figure 28
ResetlRead Timing (CS and SYNC are fixed low)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
829
HD61604/HD61605
READY
t - - - - - - - - - - t O P 1 , t O P 2 ' - - - - - - - -___
Figure 29
(READY Timing (When the READY Output is Always Available)
READY~---~-~-~~~~-W-"";"jV~
~ JV:'" - ~'_~H
SYNC
1_CI_O_Ck_ _ _ _ _ _ _ __
__
Figure 30
SYNC Timing
Voo
47kQ
10kQ
Measurement
pin
(READY)
30 PF
T
120 kQ , 1S2074H
'--~--.4---t-vss
Figure 31
Bus Timing Load Circuit (LS-TTL Load)
HITACHI
830
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
LCD CONTROLLER/DRIVER LSI DATA BOOK
Section Seven
Special Application
Drivers
HITACHI
HITACHI
832
Hitachi America, ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T-----------(Horizontal Driver for TFT -Type LCD
Color TV)
The HD66300T is a horizontal driver used for TFftype (Thin Film Transistor) LCD color TVs. Specifically, it drives the drain bus signals of a TFf-type LCD
panel.
Features
TheHD6630OTreceivesasinput~~video2ignalsR,
•
G, B, and their inverted signals R, G and B. Internal
sample and hold circuitry then samples and holds
these signals before outputting them via voltage followers to drive a TFf-type LCD panel.
•
•
•
•
The HD66300T can drive LCD panels from 480 x 240
pixels middle-resolution up to 720 x 480 pixels highresolution. It has 120 LCD drive outputs and enables
designofa compact LCD TV due to TCP (Tape Carrier
Package) technology.
•
•
•
•
•
•
Available in TCP packaging only.
Recommended for high volume applications only.
LCD drive outputs: 120
Internal sample and hold circuits: 480 (4 circuits
per output)
Support of single-rate sequential drive mode and
double-rate sequential drive mode
Support of various types of color filter arrangements through an internal color sequence controller
Vertical pixels: 240 (middle-resolution) or 480
(high-resolution)
Horizontal pixels: 480 to 720
Support of monodirectional connection mode and
interleaved connection mode through a bidirectional shift register
Dynamic range: 15 Vpp
Package: 156-pin TCP
Power supply: +5 V and -15 V
CMOS process
Pin Arrangement
Oc:nCO,....c.OLn~MN
.....
~::::::::::::::::::::::::::::
0000000000
•••••••••••••••••••••••••••••••••••••••••••
~O"ICO,....I.DL(')oo::t'MN.0000000000
~~~~~~:!~~:: .....•.•••••••••••••••••.••.••••.••••....•• ~cnClOr-!,.QU")...,MN-I
-- ............... ---.........
I
(Top View)
Note: This does not apply to Tep dimensions.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
833
HD66300T
Pin Description
Pin List
Pin Name
D1 - D120
HCK1, HCK2,
Number of Pins
Input/Output
Connected to
Functions (Refer to)
120
0
LCD panel
1.
Controller
2.
Controller or
3.
3
HCK3
DL, DR
2
110
next HD66300T
FD
Controller
4.
RS
GND
5.
OE
Controller
6.
SHL
Vee orGND
7.
DIS
Vee or GND
8.
UF
Vee or GND
9.
MSF1, MSF2
2
VeeorGND
10.
TEST1, TEST2
2
GND
11.
Vx1, Vx2, Vx3,
6
Inverter
12.
Power source
13.
Vy1, Vy2, Vy3
VbO
VbsS ' VbsH
2
Power source
14.
. Vle 1, Vle2,
Vle3, Vle 4
4
Power source
15.
Vee 1, Vce2,
Vce3
3
Power source
16.
Power source
17.
Power source
18.
GND
Vss 1, VBs 2,
Vss3, Vss4
4
HITACHI
834
Hita"chi Am~rica, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbarie,CA 94005-1819· (415) 589-8300
HD66300T
Pin Functions
1. 01 - 0120: These pins output LCD drive signals.
2. HCK1, HCK2,HCK3:These pins input three-phase
clock pulses, which detennine the signal sampling
timing for sample and hold circuits.
3. OL, DR: These pins input or output data into or
from the internal bidirectional shift register. The state
of pin SHL determines whether these pins input or
output data.
SHL
DL
DR
Output
Input
Input
Output
6. OE: This pin inputs the signal which controls the
controller of the shift matrix circuit; it changes the
selection of a sample and hold circuit and the shift
matrix (combination of color data), at its rising edge.
It also switches the bias current of the output buffer, as
shown in the following table.
OE
Bias Current of Output Buffer
High
Large current (determined by VbsB)
Low
Small current (determined by VbsH)
7. SHL: This pin selects the shift direction of the shift
register.
4. FD: This pin inputs the field determination Signal,
which allows the sample and hold circuitry and the
shift matrix circuit to operate synchronously with TV
Signals, at its rising and falling edge.
SHL
Shift Direction
High
DL~
Low
DL
~
DR
DR
8. DIS: This pin selects the LCD drive mode.
FD = high: First field
DIS
Mode
High
Double-rate sequential drive mode
When a non-interlace signal is applied, it must be
inverted every field.
Low
Single-rate sequential drive mode
When an interlace signal is applied in double-rate
sequential drive mode with per-line inversion (mode
1, 2, 3), the signal must be set high in both fields. The
signal must be set low, however, in each field's horizontal retrace period.
9. LIF: This pin selects the inversion mode of LCD
drive signals.
FD =low: Second field
5. RS: This pin inputs a test signal and should be
connected to pin GND.
LlF
Mode
High
Per-line inversion mode
Low
Per-field inversion mode
fJ
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
835
HD66300T
10. MSFl, MSF2: These pins select the function of the shift matrix circuit; they should be set according to both the
type of color filter arrangement on a TFr-type LCD panel and the drive mode.
Filter Arrangement
Drive Mode
MSF1
MSF2
Diagonal mosaic
Single-rate
GND
VccfGND
pattern
Double-rate
GND
VccfGND
Vertical stripe
Single-rate
Vee
Vee
pattern
Double-rate
Vee
Vee
Unicolor triangular
Single-rate
Vee
Vee
pattern
Double-rate
Vee
GND
Bicolor triangular
Single-rate
Vee
GND
pattern
Double-rate
Vee
GND
Single-rate: Single-rate sequential drive mode
Double-rate: Double-rate sequential drive mode
11. TESTl, TEST2: These pins input test signals and
should be connected to pin GND.
15. V~cl, VLc;2, V L~' V LC4: +5 V LCD drive voltage
is applied to these pins.
12. VXl, Vx2, Vx3, Vyl, Vy2, Vy3: Video signals are
applied to these pins; in general, positive video signals are connected to pins Vxi and negative video
signals to pins Vyi.
16. Vcc1, Vcc;2, Vc~, Vcc4: +5 V is applied to these
pins for the logic and the analog units.
13. Vbo: Bias voltage is applied to this pin for the
differential amplifier in the sample and hold circuitry.
14. VbaB' VbrM Bias voltage is applied to this pin for
the two power sources of the output buffer.
VbsB: The voltage for driving a capacitive load
VbsH: The voltage for holding the output voltage
17. GND: 0 V is applied to this pin for the logic unit.
18. Vuu l, Vuu2:-15 Vis applied to these pins for the
LCD drive unit.
19. Vuu3,Vuu4: -15 V is applied to these pins for the
LCD drive unit.
HITACHI
836
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
--e=
-=t il
::I:
s:n
I»
=.
»
~~ !. =.
i
~'~
1 ~~1
3
<1>
:::!.
HCKZ
n
.?'
controller.
HCK3
SHL
!::;:
·
?-
::I:
;::;:
n
I
RS ....
'"=.
·
'"
0
0
0
~
-0
0
a
-0
':<
CD
:::!.
~.
~
I~
~
~
~~O
:J-oV
I
D1
a
cc
Sample and hold circuit
oaIection gate
Sample and hold
circuitry
MSF1
MSF2
FD
::::1
OEU-r::!;:rr:fJ=
'"
OOR
9120
I:
CT
:0
! ..L"
*LF=m=FF~f=f~$F~======i*m=m~=tt~~l-~
I:
·'" -
[
I
er--tJ 0--8
N
en
CD·
~!
Bid.rectJonal shift _
~
-0
6l
N
;;;
I
0
n
»
co
~
0
0
'!:.
v...
~
co
~
.£!
n
Vb ••
TEsn-
r:;.;-,
TEST2~
U1
LS:lewlshifter
():)
%
Co)
0
0
():)
Co)
-.J
111
01
o
02
[
03
0118
5"'"2
.n:.
Output buffer (amp.)
[
0119
0120
::x:
t1
en
en
w
o
o
"
HD66300T
Block Functions
Shift Register: The shift register generates the sampling timing for video signals. It is driven by threephase clocks HCK1, HCK2, and HCK3, whose phases
are different from each other by 120°; each clock
determines the sam piing timing for one color signal so
that three clocks support the three color signals R, G,
and B. The shift direction of this register canbechanged.
Level Shifter: The level shifter changes 5-V signals
into 20-V signals.
Sample and Hold Circuitry: In double-rate sequential drive mode, two sample and hold circuits are
selected to sample video signals during one horizontal scanning period out of the four circuits attached to
one LCD drive signal. One of the two selected circuits
is read out in the first half of the following horizontal
scanning period, and the other selected circuit is read
out in the second half. While the two circuits are being
read out, the other two circuits sample signals and are
alternately read out in the same procedure mentioned
above.
In Single-rate sequential drive mode, one sample and
hold circuit samples a signal during one horizontal
scanning period, and is read out in the following
horizontal scanning period. While it is being read out,
one circuit out of the other three samples a signal.
Shift Matrix Circuit: The shift matrix circuit, a color
sequence controller, changes over the sampled video
signal every horizontal scanning period.
Output Buffer: The output buffer consists of a source
follower circuit and can change the through-rate of an
output signal by changing the external bias voltage.
HITACHI
838
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
System Block Configuration Example
Antenna
Video
input 0-----0
R,G, B
R,G,B
TFT-type color LCD panel
720 x 480 pixels
HITACHI
Hitaehi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
839
HD66300T
Example of HD66300T Connection to LCD Panel
'"a
0120 I-0119 I--
.---
-
FD
DE
r---- HCK3
:-- HCK2
HCKI
Vy3
M~
~~
a
'"a
FD
DE
HCK3
HCK2
HCKI
Vy3
Vy2
Vyl
Vx3
Vx2
Vxl
~~
Q~
:z:
E-oo
(!l~~
'" "l/.:~
Cll\ m co
., '" I.,r\ "''-5
0201-
0120
0119
~-(!)
OJ /
5-a:
" /r\ "
_:.
>.
;:
~
8 ~8~
:x:::r
::r::
:t:
II)
>1
Synchronizing
isolator
~
0119
0120
. FD
DE
HCK3
HCK2
HCKI
Vy3
Vy2
Vyl
Vx3
Vx2
Vxl
'"
a
......... ill~
x .........
~
HD6110S
(No.3)
81--15
0
a
~~
...J
diJi:!:
(f)
~
>~ >1.1'd~~
>
S SS3
PLll
~
~
~
I
a
:z:
)(
>~ >! >~~
!
UJ
3 ......... %
~ ~ d~ ~ ~
Video
input
;1;
z
:
~
Tuner
~
LLJ···UJ
..J
1--01
I-- 02
a
02
01
15
'"a
M..,
HD6110S
•
\ ~~~
/
z
:J
:i ·········~I
x ......... ~
¥
:
FDDEHCK3HCKZ
HCKI
Vy3
VyZ
Vyl
Vx3
Vx2
Vxl
:(\a)-~
N
UJ
Q
al:
I-- 0119
I-- 0120
.,~f-
"'z
a
I
g~
M"'l
:z:
..J
I Sound
I IF
..J
a
0-
Q~
Vyl
Vx3
Vx2
Vxl
-
t;:~&l~
f- 0.'<1" 0.
g~
Vy2
=
-
N
~_XCl)
f-
-
-
I-- 02
1--01
0
'. >.
...J
(/)
~ d~ ~ ~
;:
~
1·1 ~ ~
> >
>
wooooc
OI.L.----
"''' ,,""""-,1,.,1
Controller
I
Z
.....
f'>JM
~~~~
I
1
Inverter
+.,1
[Chroma
r corrector
Figure 1 Example of HD66300T Connection to LCD Panel
HITACHI
840
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
--u-~.-or--''--U--''--U-~'-0I--~-..--cr--Lr_3-u-,34~
II I
Video
STH
OE
rLSl--D-
II
"0
a; FD
Ii=
e
Dl-D120
i!: CL
D
Ga-l
----------~r;-1~--------------------------------~r----------
G~-2
______________~r;rJL__~
__~
__-__-___-__-_------------------~~----------
Ga-240
----------------------------------------------~~~
Video
STH
.,
,,
OE
.,
"0
a; FD
Ii=
"0
Dl-D120
.,
CL
c:
0
()
til
D
Ga-l
Ga:'2
Ga-240
Video
III
.
HCK2
.f
HCK3
~r1I1~
______________________
------------::-=-=--o::!--'I! _________
h
~~-----------
~l
---------------------------------------------------~w~--~~
F
-ur------ii
:ei[STH
HCKI
.§ ~
~
____________________
Valid disploy:;;eriod
____~in~~~----~-----
"
~~ 11[:::1
HCK2
.f
HCK3
•
HCK2
E.f
HCK3
i
,'
"
! 1[:::1 ~
,,
HCK1, HCK2, and HCK3 are
three-phase clocks having a
mutual phase difference of
120° .
Due to a 1.5-pixel position shift
between even number lines
and odd number lines, a 1.5pixel phase shift must be generated between the clocks for
even number lines and those
for odd number lines when an
LCD panel of unicolor triangular pattern is used.
""
~
; 11[:::1
~
HCK2
.f
HCK3
Figure 2 Timing chart
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point PkWy.' Brisbane, CA 94005-1819' (415) 589-8300
841
HD66300T
Functional Description
One line of an LCD panel is driven every horizontal
scanning period in this mode.
Screen Size
Number of horizontal pixels:
- 120, 240, 360, 600, and 720 in monodirectional connection mode
- 240, 480, and 720 in bidirectional connection mode
Number of vertical pixels:
- 240 in single-rate sequential drive mode
- 480 in double-rate sequential drive mode
Single-Rate Sequential Drive Mode and DoubleRate Sequential Drive Mode
Single-Rate Sequential Drive Mode: A typical TV
signal (Note) has 525 scanning lines, 480 of which are
part of the valid display period. In interlace scanning
mode, 480 scanning lines are equally divided into a
first field and a second field.
In single-rate sequential drive mode, a 240-pixel-high
LCD panel is used. 240 scanning lines of the first and
second fields of the TV signal are respectively assigned to the 240 lines of the LCD panel.
Double-Rate Sequential Drive Mode: To obtain a
high-resolution display, a 480-pixel-high LCD panel
is used. If 480 scanning lines are respectively assigned
to the 480 lines of the LCD panel, the LCD alternating
frequency becomes 15 Hz, which causes flickering
and degrades display quality. To avoid this problem,
the following method is employed. In the first field,
the first scanning line is assigned to the first and
second lines of the LCD panel, the second scanning
line is assigned to the third and fourth lines, and so on.
In the second field, the first scanning line is assigned
to the second and third lines, the second scanning line
is assigned to the fourth and fifth lines, and so on.
Two lines of an LCD panel are driven every horizontal
scanning period in this mode.
Note:
Refer to the index for the further information ofNTSC
TV system signals and LCD.
HITACHI
842
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
Supportable Types of Color Filter Arrangements
The order and timing for the HD66300T to output
color signals depend on the color filter arrangement
on a TFT-type LCD panel. The HD663OOI' can support
TFT-type LCD panels having the following color filter
arrangements by specifying the operation of the internal color sequence controller and by changing the
external signals to be supplied.
(a) Diagonal from top-left to bottom-right mosaic
pattern
(d) Unicolor triangular pattern
(b) Diagonal from top-right to bottom-left mosaic
pattern
(e) Bicolor triangular pattern
(c) Vertical stripe pattern
Figure 3 Supportable Types of Color Filter Arrangements
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
843
HD66300T
=low)
Mode Setting Pins
Per-Field InveJ:Sion (available with lJF
Mode setting pins MSF1, MSF2, and DIS must be set
according to both the type of color filter arrangement
ontheTFI'-type LCD panel and thedrivemode(singlerate sequential drive mode or double-rate sequential
drive mode). These pins activate the internal color
sequence controller, which changes the sequence of
color video signals corresponding to each sample and
hold circuit and allows the LSI to output color data in
the right order for the LCD panel being used.
In a certain field, all LCD drive signals have one
polarity and in the following field, they all have the
inverted polarity.
Per-Field Inversion and Per-Line Inversion
Per-Line Inversion (available with UF
=high)
In a certain field, all LCD drive signals have positive
polarity in odd number lines and negative polarity in
even number lines, while in the following field, the
situation is reversed, that is, negative polarity in odd
number lines and positive polarity in even number
lines.
The inversion mode of LCD drive signals can be
selected by pin L/F.
Table 1 Mode Setting Pins,
Filter Arrangement
Drive Mode
DIS
MSFl
MSF2
Referential Timing Charts
Diagonal mosaic
Single-rate
GND
GND
Vee' GND
MODES 15,,16, 18, and 19
pattern
Double-rate
Vee
GND
Vee' GND
MODES 1, 2, 5, 6, 8, 9,
12, and 13
Vertical stripe
Single-rate
GND
Vee
Vee
MODES 17 and 20
pattern
Double-rate
Vee
Vee
Vee
MODES 3,7, 10, and 14
Unicolor triangular
Single-rate
GND
Vee
Vee
MODES 17 and 20
pattern
Double-rate
Vee
Vee
GND
MODES 4 and 11
Bicolor triangular
Single-rate
GND
Vee
GND
MODE 17
pattern
Double-rate
Vee
Vee
GND
MODES 4 and 11
Single-rate: Single-rate sequential drive mode
Double-rate: Double-rate sequential drive mode
HITACHI
844
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
Interface
output pins, refer to the following example.
Video Signals Connection
In the case of Diagonal from top-left to bottom-right
mosaic pattern.
Video signals must be connected to pins Vxl, Vx2,
Vx3, Vyl, Vy2, and Vy3; in principle, positive video
signals R, G, and B signals must be input to pins Vxl,
Vx2, and Vx3, and negative video signals R, G, and B
to pins Vyl, Vy2, and Vy3. For actual connection
between an LCD panel and the LCD drive signal
This example describes the case in which an LCD
panel having a diagonal from top-left to bottom-right
mosaic pattern is driven in double-rate sequential
drive mode and monodirectional connection mode.
H066300T
101 0203
1st line
2nd line
The Color Sequence for Each Output Pin
3rd line
4th line
II I
R
B
G
R
G
R
B
G
B
G
R
B
03k+1 03k+2 03k+3
!r1
R
B
G
R
G
R
B
G
(k=O ~39)
B
G
R
B
Color Sequence
Output Pin
01 (=D3k+ 1)
R~B~G~R~
02 (=D3k+ 2)
G~R~B~G~
03 (=D3k + 3)
B~G~R~B~
The Signal Sequence for Each Output Pin
Output Pin
Color Sequence
01 (=D3k + 1)
Vx1
02 (=D3k+ 2)
Vx2 ~ Vx1 ~ Vx3 ~ Vx2 ~
03 (-D3k + 3)
Vx3
~.
~
Vx3
Vx2
~
~
Vx2
Vx1
~
~
Vx1
Vx3
~
~
(Refer to MODE 5)
The Connection of Signals
Signal
Color
Vx1
R
Vx2
G
Vx3
Vy1
8
R
Vy2
G
Vy3
8
fJ
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
845
HD66300T
In the case of Diagonal from top-right to bottom-left
mosaic pattern, Vertical stripe pattern
The sameproc:edure for video signal connection applies
to the case in which a TFr-type LCD panel having a
diagonal from top-right to bottom-left mosaic pattern
or a vertical stripe pattern is used, as well as to the
cases where a panel of any pattern is used through the
bidirectional connection mode.
Triangular Pattern, Single-Rate Sequential Drive
Mode
The following procedures are required when a panel
of unicolor or bicolor triangular pattern is used:
1. UnicolorTriangular Pattern, Single-Rate Sequential
Drive Mode
The clock phase must be changed every line because
of the 1.S-pixel phase shift between even number lines
and odd number lines. (Refer to the explanation of
sampling clocks.)
The connection of signals here is the same as that
described above.
2. Bicolor Triangular Pattern, Single-Rate Sequential
Drive Mode
The clock phase must be changed every line because
of the O.S-pixel phase shift between even number lines
and odd number lines. (Refer to the explanation of
sampling clocks.>
The connection of video signals in the second field
must be changed from that in the first field. See the
following tables.
The Color Sequence for Each Output Pin
Output Pin
01 (,.03k + 1)
02 (",03k + 2)
03 (=03k + 3)
Color Sequence
R~ B~ R~
B~
G~ R~ G~
R~
B~ G~ B~
G~
The Signal Sequence for Each Output Pin
Output Pin
01 (..03k+1)
02 (-03k + 2)
03 (-03k+ 3)
2nd
01 (.. 03k + 1)
field
02 (.. 03k + 2)
03 (-03k+ 3)
(Refer to Mode 17)
Signal Sequence
Vx1 ~Vy1 ~Vx1 ~Vy1 ~
Vx2 ~ Vy2 ~ Vx2 ~ Vy2 ~
Vx3 ~ Vy3 ~ Vx3 ~ Vy3 ~
Vy1 ~ Vx1 ~ Vy1 ~ Vx1 ~
Vy2 ~ Vx2 ~ Vy2 ~ Vx2 ~
Vy3 ~ Vx3 ~ Vy3 ~ Vx3 ~
1st
field
The Connection of Signal In Each Field
Per-Field Inversion
Mode (UF low)
1st Field
2nd Field
R
B
R
G
G
B
R
B
R
G
G
B
=
Vx1
Vx2
Vx3
Vy1
Vy2
Vy3
Per-Line Inversion
Mode (UF =hlgh)
1st Field
2nd Field
R
B
R
G
G
8
B
R
R
G
G
B
HITACHI
846
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
Triangular Pattern, Double-Rate Sequential Drive
Mode
Changing the phase of the sampling clocks is sufficient when the panel is driven in single-rate sequential
drive mode. However, when the panel is driven in
double-rate sequential drive mode, the above counter-
measure does not work, since the display data for two
lines is sampled at one time here. Consequently, delaying the input video signal for a time period corresponding to the shift between pixels is required.
HD66300T
1st line
A shift in pixel pOSition
exists between the lines.
2nd line
3rd line
4th line
Figure 4
Video
signal
For the 2nd line
i
i Delay
I
!
I
i
Delayed video
signal
:
For the 1st line
iI
I
I
I
I
I
I
I
I
I
Sampling
clocks
--------~r-l~~r_---2 - -__________~~~_____
Figure 5
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
847
HD66300T
1. Unicolor Triangular Pattern, Double-Rate Sequential Drive Mode
The Color Sequence for Each Output Pin
Output Pin
Color Sequence
01 (.03k + 1)
R -+ R -+ R -+ R -+
02 (-03k+2)
G -+G -+G -+ G -+
03 (-03k + 3)
B -+ B -+ B -+ B -+
The Signal Sequence for Each Output Pin (In Interlace mode)
Output Pin
Signal Sequence
1st
01 (-03k + 1)
Vx1 -+ Vy1 -+ Vx1 -+ Vy1 -+
field
02 (-03k+ 2)
Vx2 -+ Vy2 -+ Vx2 -+ Vy2 -+
03 (-03k + 3)
Vx3 -+ Vy3 -+ Vx3 -+ Vy3 -+
2nd
01 (-03k + 1)
Vy1 -+ Vx1 -+ Vy1 -+ Vx1 -+
field
02 (-03k+2)
Vy2 -+ Vx2 -+ Vy2 -+ Vx2 -+
03 (-03k+3)
Vy3 -+ Vx3 -+ Vy3 -+ Vx3 -+
(Refer to MODE 4)
The Signal Sequence for Each Output Pin (In non-Interlace mode)
Output Pin
Signal Sequence
1st
01 (.03k + 1)
Vx1 -+ Vy1 -+ Vx1 -+ Vy1 -+
field
02 (.. 03k+ 2)
Vx2 -+ Vy2 -+ Vx2 -+ Vy2 -+
03 (.. 03k+ 3)
Vx3 -+ Vy3 -+ Vx3 -+ Vy3 -+
2nd
01 (=03k+ 1)
Vx1 -+ Vy1 -+ Vx1 -+ Vy1 -+
field
02 (-03k + 2)
Vx2 -+ Vy2 -+ Vx2 -+ Vy2 -+
03 (-03k + 3)
Vx3 -+ Vy3 -+ Vx3 -+ Vy3 -+
(Refer to MODE 11)
HITACHI
848
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
1. Unicolor Triangular Pattern, Double-Rate Sequential Drive Mode (Cont.)
The Connection of Signals In Each Field In Interlace Mode
Per-Field Inversion
Per-Line Inversion
Mode (L1F = low)
Mode (L1F =hlgh)
1st Field
2nd Field
1st Field
2nd Field
Vx1
Delayed R
R
Delayed R
R
Vx2
Delayed G
G
Delayed G
G
Vx3
Delayed B
B
Delayed B
B
Vy1
R
Delayed R
R
Delayed R
Vy2
G
DelayedG
G
Delayed G
Vy3
B
Delayed B
B
DelayedB
The Connection of Signals In Each Field In Non-Interlace Mode
Per-Field Inversion
Per-Line Inversion
Mode (L1F = low)
Mode (L1F =hlgh)
1st Field
2nd Field
1st Field
2nd,Fleld
Vx1
Delayed R
Delayed
R
Delayed R
Delayed R
Vx2
DelayedG
DelayedG
DelayedG
DelayedG
Vx3
Delayed B
Delayed B
Delayed B
Delayed B
Vy1
R
R
R
R
Vy2
G
G
G
G
Vy3
B
B
B
B
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
849
HD66300T
2. Bicolor Triangular Pattern, Double-Rate Sequential Drive Mode
The Color Sequence for Each Output Pin
1st line
YY+""'-'r'-
2nd line
3rd line
YY+hr'-
4th line
Output Pin
Color Sequence
01 (-03k+ 1)
R~R~R~R~
D2 (-03k + 2)
G~
03 (-03k + 3)
B~G~B~G~
R-4G~R~
The Signal Sequence for Each Output Pin (In Interlace mode)
OUtput Pin
Signal Sequence
1st
01 (=03k+ 1)
Vx1
~
Vy1
~
Vx1
~
Vy1
~
field
02 (.. 03k+2)
Vx2
~
Vy2
~.
Vx2
~
Vy2
~
03 (-03k + 3)
Vx3
~
Vy3
~
Vx3
~
Vy3,
~
2nd
01 (..03k + 1)
Vy1
~
Vx1
~
Vy1
~
Vx1
~
field
02 (..03k + 2)
Vy2
~
Vx2
~
Vy2
~
Vx2
~
03 (-03k + 3)
Vy3
~
Vx3
~
Vy3
~
Vx3
~
(Refer to MODE 4)
The Signal Sequence for Each OUtput Pin (In non-Interlace mode)
OUtput Pin
Signal Sequence
1st
01 (-03k+1)
Vx1
~
Vy1
~
Vx1
~
Vy1
~
field
02 (-03k+ 2)
Vx2
~
Vy2
~
Vx2
~
Vy2
~
03 (-03k+3)
Vx3
~
Vy3
~
Vx3
~
Vy3
~
2nd
01 (-03k+1)
Vx1
~
Vy1
~
Vx1
~
Vy1
~
field
02 (-03k + 2)
Vx2
~
Vy2
~
Vx2
~
Vy2
~
03 (-03k+ 3)
Vx3
~
Vy3
~
Vx3
~
Vy3
~
(Refer to MODE 11)
HITACHI
850
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
2. Sicolor Triangular Pattern, Double-Rate Sequential Drive Mode (Cont.)
The Connection of Signals In Each Field In Interlace Mode
Per-Field Inversion
Per-Line Inversion
Mode (UF = low)
Mode (UF =hlgh)
1st Field
2nd Field
1st Field
2nd Field
Vx1
Delayed R
B
Delayed R
B
Vx2
Delayed G
R
DelayedG
R
Vx3
Delayed B
G
Delayed 8
G
Vy1
B
DelayedR
B
DelayedR
Vy2
R
DelayedG
R
DelayedG
Vy3
G
Delayed
B
G
Delayed 8
The Connection of Signals In Each Field In Non-Interlace Mode
Per-Field Inversion
Per-Line Inversion
Mode (UF = low)
Mode (UF =hlgh)
1st Field
2nd Field
1st Field
2nd Field
Vx1
Delayed R
Delayed R
Delayed R
Delayed R
Vx2
DelayedG
Delayed G
DelayedG
Delayed G
Vx3
Delayed 8
Delayed 8
Delayed B
Delayed B
Vy1
B
B
8
B
Vy2
R
R
R
R
G
G
G
Vy3
G
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
851
HD66300T
Connection to LCD Panels
There are t\yO modes of connecting HD66300T chips
to an LCD panel:
In the former mode, the HD66300Ts are set on either
the upper side or lower side of the panel, while in the
latter mode, the HD66300Ts are set on both sides and
the upper drivers and the lower drivers are alternately
connected to each pixel-column.
1) monodirectional connection mode
2) interleaved connection mode
DR
DR I - - - - - I D L
HD66300T
HD66300T
Figure 6 Monodhectional Connection Mode
DR
DRI-----iDL
H066300T
H066300T
HD66300T
HD66300T
OL
D L t - - - - - t DR
SHL
~cc
Figure 7
Vee
Inte~leaved
Connection Mode
HITACHI
852
Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0(415) 589-8300
HD66300T
Internal Operation
The HD66300T has four sample and hold circuits for
each outputs as shown in the block diagram, and its
internal bidirectional shift register controls which
circuits to sample data.
It has three-phase shift clocks with mutual phase
difference of 120° to drive the shift register, which
enables driving an LCD panel with mosaic pattern
and triangular pattern.
The operation of sample and hold circuits and sampling operation are described below followeii by the
description of the relationship between three-phase
shift clock phases and frequencies.
After the above description, determination of bias
voltage is described; bias voltage controls driving
characteristics of a differential amplifier and output
buffer of the sample and hold circuits.
Finally, the OE and FD signals are described; they
determine the operation of the sample and hold shift
matrix circuit. Timing charts for each mode follow the
description.
Sample and Hold Circuitry
Operation of Sample and Hold Circuitry
The HD66300T has four sample and hold circuits A, B,
C, and 0 per LCD drive signal output. Sample and
hold circuit pair A and B is supplied with the same
sampling clock pulses as circuit pair C and O. One of
the signals output by these circuits is connected to an
output driver.
These sample and hold circuits repeat sampling and
outputting of signals alternately to drive an TFf-type
LCD panel.
Video
signals
input
Output driver
Output
Sampling
clock 1
Sampling 0----1
clock 2
Figure 8 Sample and Hold Circuitry
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
---- --------
853
. . --=------~- ..
.----~~~~~
HD66300T
In single-rate sequential drive mode, sample and hold
circuits A and D are alternately used; circuits Band C
perform sampling operation, but are not used since
they are not connected to the output driver.
In single-rate sequential drive mode, one sample and
hold circuit samples the signal during one horizontal
scanning period, and outputs it as an LCD drive signal
in the following horizontal scanning period.
In double-rate sequential drive mode, all sample and
,.
lH
hold circuits A, B, C, and D are alternately used.
In double-rate sequential drive mode, two sample and
hold circuits sample two signals during one horizontal scanning period, and output one of them as an LCD
drive signal in the first half of the following horizontal
scanning period, and output the other signal in the
second half.
The following shows the timing charts of sampling
and outputting operation.
·1
OE
A
Sample
w:ta
~wfif#la
SAMPLING
B
Not used
c
Not used
SAMPLING
~
and
hold
circuits
SAMPLING
D
OUTPUT
==X~
__
-,X,-___
A_ _~X,-
D_ _
___
D_ _ _
X::=:
Figure 9 Sampling Timing charts of Single-Rate Sequential Drive Mode
1-
lH
--j
OE
SAMPLING
A
Sample
and
hold
circuits
B
c
D
~
SAMPLING
W~fJa
~O§J.@~
SAMPLING
ft11f11f~
SAMPLING
SAMPLING
SAMPLING
OUTPUT
Figure 10 Sampling Timing charts of Double-Rate Sequential Drive Mode
HITACHI
854
Hitachi America, Ltd.· Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
HD66300T
Sampling Operation
register activates in tum the sample and hold circuits
corresponding to each LCD drive signal output pin.
The HD66300T has a bidirectional shift register composed of 120 bits and each bit of the shift register
generates the sampling pulses to control the sampling
operation of the four sample and hold circuits connected to each LCD drive signal output pin. When a
bit of the shift register is 1, the corresponding sample
and hold circuits are in the sampling state; when it is
0, the corresponding sample and hold circuits are in
the hold state. Consequently, shifting a 1 into the shift
01
02
03
04
Figure 11 is a shift register sketch illustrating the
relationship between the shift register and the shift
clocks HCK1, HCK2, and HCK3. Note that the order
of sampling pulse generation depends on the state of
pin SHL. D1 corresponds to DL and 0120 to DR.
Figure 12 is a timing chart of sampling pulses generated by the shift register.
0117 0118 0119 0120
Output pins
Sample and hold circuitry
OL
DR shift register
SHL
HCK1 O---~--+-~-r~
HCK2 0 - - - - 1 - - - '
HCK3 0-------4----'
Figure 11 Shift Register Sketch
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
855
HD66300T
HCK2~
~fLJL..J
ILJU
~
L.fLJl-.
HCKl
HCK3
(o3~PUT)-----)~s-L-.SRl
--)~~
SR2
_ _~~s-1-
SR3
--))~
SRl18
---.r-L))_____
SRl19
~)~----
SR120
~))-----
(IN~~T)
n
))----(8)
(IN~~T)
SHL= High
n
))----
SR2
~~)--~S)---
SR3
~)),----
SRl18
-------'S)~
SRl
---'))s-1-
SR119 _ _ _ _
SR120
-----))~
(08~PUT)-----))s-L-.(b) SHL=Low
Figure 12 Sampling Pulse Timing Chart
HITACHI
856
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
Three-Phase Shift Clocks
operation starts when 1 is input from pin DL or DR at
a rising edge of the HCK1 clock pulse.
Three-Phase Shift Clocks and Sample Start Signal
Shift clocks HCK1, HCK2, and HCK3, which are
operation clocks for the shift register, must be threephase clocks with 50-percent duty. The HCK2 clock
must be generated 1200 after the HCK1 clock, and the
HCK3 clock 2400 after the HCK1 clock. Sampling
HCKl
In monodirectional connection mode, all the
HD66300T chips must be supplied with the same
three-phase shift clock pulses. In interleaved connection mode, the frequency of the three-phase shift
clocks must be halfofthat in monodirectional connectipn mode, and the phase shift between the upper
drivers clocks and the lower drivers clocks must be
one pixel.
~
!
HCK2
I
I
HCK3
-n
I
i
DL/DR
II
(a)
HCKl
-1i
I
I
I
HCK2
For upper
drivers
In Monodirectional Connection Mode
II
I
HCK3
'--___. . .1
II
I
I
mI!
I
I
DL/DR
I
I
i
HCKl
HCK2
For lower
drivers
HCK3
DL/DR
I
Pixe~,
L
f
I
I
I
I
I
i
n
I
The lower driver clock pulses follow the upper driver clock pulses by one pixel.
(b)
In Interleaved Connection Mode
Figure 13 Three-Phase Shift Clocks and Sample Start Signal
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
857
HD66300T
Some position shift exists between the pixels of even
number lines and those of odd number lines for LCD
panels having triangular patterns. This requires generating a phase shift between the three-phase clocks
1st line
""--=r--'?-T"---r- §
I:
2nd line
l
.! r
~
;"-:!--::!:>o--:::!>---'"- c; ~
u. '"'
for even number lines and those for odd number lines.
The required phase shift is 1.5 pixels for LCD panels
having a unicolor triangular pattern, while it is 0.5
pixels for those having a bicolor triangular pattern.
HCKl
!,--,
HCI<2
~
r--l
l..--.-..J
I
,-
L----.J
HCK3:
:
DL/DR
lTlL--------------: 1 .5-pixel delay
1..----...:;-:_ _-,
4th line
m
HCKl
.0
E
:>
HCK2
I:
I:
~
~ gf
o I:
u..:.:
HCK3
n
DL/DR
(a)
.,
HCKl
~
1st line
.0
2nd line
I:
"0
"0
E
HCK2
:>
.,
0",
01:
~
Unicolor Triangular Pattern
HCK3
LL:.:
3rd line
DL/DR
I
I
I
I
JTl
: O.5-pixel delay
~
4th line
.,"'
I:
HCKl
.,1:'"'
HCK2
o~ E
:>
HCK3
~
i;1l
u.1:
DL/DR
(b)
~
Bicalor Triangular Pattern
Figure 14
HITACHI
858
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
How to Generate Three-Phase Shift Clocks
Three-phase shift clocks can be generated by dividing
the base clock, which is generated from a horizontal
synchronizing clock, through the use of a frequency
multiplier such as a PLL circuit.
The number of horizontal pixels of the LCD panel and
the valid display ratio determines the base clock
frequency f.
If the number of horizontal pixels is 480 and the
valid display ratio is 95% in the NfSC system, the
base clock frequency fis about 9.59 MHz according
to the following equation.
f .. (1lValid display period) x (no. of horizontal
pixelslValid display ratio)
.. 480/(52.7 fJ.sec x 0.95)
.. 9.59 (MHz)
The three-phase clocks can be generated by dividing f by 3 (in the monodirectional connection mode)
or 6 (in the interleaved connection mode).
Video
signals
,
,,
I
I
I
!Horizontal
I
retrace period
!.,
,
. ,:.
Valid display period
!
-I
,
Figure 15 Base Clock
HITACHI
Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819- (415) 589-8300
859
HD66300T
HCKl
HCK2
HCKl
For lower
drivers
HCK2
(a)
In Monodirectional Connection Mode
(b)
In Interleaved Connection Mode
~
l
HCK3
Figure 16 Three-Phase Shift Clocks
HITACHI
860
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
Bias Voltage
Voltages VbaB' VbsH' and Vbo control the drive capability of the output buffer and differential amplifier.
'
Here the LSI must be used in the range of
VbaB controls the drive current capability of the output
buffer when OE is high (lVsB) and VbsH controls the
leakage correction current of when OE is low (IVsH),
Figure 17 and figure 18 show the relationship between
IVsB and VbaB and the relationship between IVsH and
VbsH ' respectively.
VbsB and VbsH should be to an appropriate level for
the electrical characteristics of the LCD panel used.
The rise time (tODR) and the fall time (toDF) of the
output buffer depend on the input level of VbsB'
Figure 19 shows the relationship between toDR' tOOF
and VbsB'
Vbo controls the bias current of the differential amplifier (IVbo)'
Figure 20 shows the relationship between the rise and
fall times (tOOR' to~ of the output buffer and VboO
Vbo should be adjusted to an appropriate level for the
electrical characteristics of the LCD panel used.
The increase of total current consumption is 120 times
larger than that of IVbaB' IVbsH and IVbo' because
figure 17, 18 and 21 each shows the case of one output
and HD66300T has 120 outputs.
Figure 17, 18, 19,20and21 are just for reference and do
not guarantee the characteristics.
I v•••
(,.,A)
IV•••
(,.,A)
1,000
800
600
400
200
80
/
60
40
20
5
/
2
Vee-V... (V)
3
4
5 Vee -V••• (V)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
861
HD66300T
t DO ,
(ps)
10
t DOR
(PS)
V.. =Vrx-3V
CL= 100pF
V•• =Vcc -3V
CL =100pF
Vb •• (V)
Vb •• (V)
Figure 19 ~DR' ~DF VS Vba.
tOoR
tODF
(Ps)
5
/
(Ps)
5
Vbse=Vrx-3V
CL=100pF
Z
~
Z
3 Vb. (V)
V••• =Vcc -3V
CL =100pF
3
V•• (V)
Figure 20 ~DR' ~DF VS Vbo
HITACHI
862
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66300T
IV..
C.uA)
50
40
30
20
10
1
2
3
4
5 Vee -Vb. (V)
,
OE
tDOR
90%(Vin=Vee -3.5V)
01-0120
10%(Vin=V•• +1.5V)
Figure 22 Definition of too.. and toop
HITACHI
Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0 (415) 589-8300
863
HD66300T
OESignal
OE - high: Drives with large current (300 ILA. typ)
OE - low: Drives with small current (20 I1A. typ)
The OE signal has the following functions:
Clock for internal circuits: Controls the sample and
hold circuitry and the controller of the shift matrix
circuit, and switches the output signal at the OE signal
rising edge.
Switching of drive capability of the output buffer:
Determines the current drive capability of the output
buffer;
This function allows the output buffer to operate with
large current during the transition of an output signal,
thus shortening its falling time. At the same time it
allows the output buffer to operate with small current
while an output signal is stable,lowering current consumption.
The drive current is controlled by bias voltages VbsB
(large current) and VbsH (small current).
Output
signal
large
current
Small
current
.,
Figure 23 Switching of Drive Capability of the Output Buffer
HITACHI
864
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
FD Signal
The FD signal is the field determination signal; a field
is determined by the state of this signal at the rising
edge of the OE signal. This signal synchronizes the
internal controllers with TV signals.
The order of outputting signals is determined at the
fourth rising edge of the OE signal after the rising or
falling edge of the FD signal in double-rate sequential
drive mode, while it is determined at the third rising
edge in single-rate sequential drive mode; hereinafter,
as long as the FD signal is not changed, signals will be
output in the determined order at most every 12
pulses of the OE signal in double-rate sequential drive
mode, while at most every 6 pulses in single-rate
sequential drive mode.
The FD signal should usually be high in the first field
and low in the second field. In some modes, however,
it should be high in both fields, but low for at least onepulse time period of the OE signal during the horizontal scanning period.
The order of outputting signals and the timing of
inputting the FD signal vary depending on the mode.
For more details, refer to the appropriate timing
charts.
Timing Charts for Each Mode
Table 2 Reference timing charts for each mode
Single (DIS
=Low)
Double (DIS = High)
Interlace
Filter Arrangement
Mosaic Topleft to
bottomright
Per-Line
Non-Interlace
Per-Field
Per-Line
Per-Field
Per-Line
Per-Field
MODE1S MODE 18
MODE 2
MODE 6
MODE 9
MODE 13
Monodi- MODE 16 MODE 19
MODE 1
MODES
MODE 8
MODE 12
MODE 16 MODE 19
MODE 1
MODES
MODE8
MODE 12
Monodi- MODE1S MODE 18
MODE 2
MODES
MODE 9
MODE 13
Interleaved
rectional
Topright to
bottomleft
Interleaved
rectional
Vertical stripe
MODE 17 MODE 20
MODE 3
MODE 7
MODE 10
MODE 14
Unicolor triangular
MODE 17 MODE 20
MODE 4
MODE 4
MODE 11
MODE 11
Bicolor triangular
MODE 17 MODE 17
MODE 4
MODE 4
MODE 11
MODE 11
Single: Single-rate sequential drive mode
Double: Double-rate sequential drive mode
Per-Une: Per-line inversion mode
Per-Field: Per-fie1c\ inversion mode
Interleaved: Interleaved connection mode
Monodirectional: Monodirectional connection mode
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
865
HD66300T
MODE 1
DIS
Vee
L/F
Vee
MSFI
GND
MSF2
Vee
(Video
I~~
DE
~
LJ-'u""'uurLrljLJ-'u'1__r'urLJ"'uLJLr'uurLJ1J'Lru')~_rLrJ-LJLJLfL_
FD
~r------------------~----------~S~\--------'L-
Sample and
hold circuits
I SAMPLE lOUT I
I SAMPLE lOUT I
['
SAMPLE
B
~
U
SAM
SAMPLE
I SAMPLE IOUTI
OUT SAMPLE
E
SAMPLE
I SAMPLE I
OUT
IOUTI SAMPLE I
I SAMPLE lOUT I
OUT SAMPLE
SAMPLE OUT
IOUTI SAMPLE I
I
S~
OUT
SAMPL
IOUTI
\ I
OUT
IOUTI
\ I SAMPLE louT!
lOUT I SAMPLE I
I
)~
I SAMPLE I
lOUT I
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D3k+2 ____~-u~~~..J,~V'J2"V~ylJ~'~3,~~,~~V~y37~V,~2"V~y~1~V~'3/~Vy~Z"V~'IJ~V~y3/~~,V~YJ1.,V~'371
VIC3 V'IZ
D3k+3
Ga-l
______
~IIL
VIC!
V 3 Vx2
Vyl
Vlt3 Vyl VIII
Vy3 Vx2 Vyl
VIC3
VyZ
Vx1
________________________
-;~~
_____________
Ga-Z
-----------------~IlL---~~~-------------------1%~--------------
Ga-480
------------------------------~s~
Video
282
..
.-------,r-----,r-~~
283
I
DL/DR
DE
---..Jr----------------------------------------~(~~----------,L-...
FD
I SAMPLE lOUT I
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['
B
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hold circuits ~
il
'"
"C
C
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AMPLE
OUT
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lourl SAMPLE I
I ~~
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I
OUT
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8
c1l D3k+l
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Vyl
Vx3
'12 VIC! VyJ
x X
YxZ
XX
XX
D3k+Z
D3k+3
Vy3 Vx2 Vyl
Vx3 Vy2
Vxl
Vy3 Vx2
Ga-l
--------------~II~--------------------------------~S~\--------------------
Ga-Z
-----------------------~r}~_.~._.. --------------------------~(~h--------------------
G~-480
~\
II~----'----
HITACHI
866
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODE 2
D/S
Vee
L/F
Vee
MSFI
GND
MSF2
GND
Video
DL/DR
OE
FD
~
Sample and
hold circuits
D3k+l
r
B
~
I SAMPLE loutl
I SAMPLE I
I SAMPLE IOUTI
IOUTI SAMPLE I
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I SAMPLE I
Vxl
I SAMPLE IOUTI
IOUTI SAMPLE I
I SAMPLE IOUTI
lOUT I SAMPLE I
I S(-~T.IO"'"U"'TI"'-'----'
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SAMPlElOUTI ~\ I SAMPLE IOUTI
SAMPLE I
I ~~ I SAMPLE I
lourl
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louT! SAMPLE I
I SAMPLE IOUTI
IOUTI SAMPLE I
I
lour!
lOUT!
V,2 Vx3 V,I Vx2 V,3 Vxl
D3k+2
Vx2 V,3
D3k+3
Vx3 V,I Vx2 V,3 Vxl v,2
Vxl V'I'l. Vx3 V,I Vx2
n
Ga-l
ss
n
Ga-2
«II
Ga-480
--------------------------------~·s~
Video
282
DL/DR
OE
FD
:s!
[
~
"'"c
j
I SAMPLE
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hold circuits ~
lOUT I
I SAMPLE I
I
SAMPLE lOUT I
lOUT I SAMPLE
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I
lourl SAMPLE I
I
SAMPLE lOUT I
I
I SAMPLE IOUTI
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lourl SAMPLE I
x X
D3k+l
XX
XX
D3k+2
D3k+3
Ga-l
--------------~n~--------------------~Si~S-------------
Ga-2
___________-Jn~..~._~--------------~~~i---------------
GA-480
---------------------------------·~·s~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
867
HD66300T
--------MODE 3
r
DIS
Vee
L/F
V"
MSF1
Vee
MSF2
Vee
Video
DL/DR
S\
OE
FD
Sample and
l
B
I
SAMPLE
10UTI
hold circuits ~
l2
'""
e
u::
D3k+l
I
OUT
SAMPLE
SAMPLE
10UTI
au
SAMPLE
I
SAMPLE
I
I SAMPLE 10UTI
OUT
SAMPLE
OUT
SAMPLE
10UTI
SAMPLE
I
I SAMPLE 10UTI
OUT
SAMPLE
SAMPLE
10UTI
SAMPLE
I St-\"lo"'u;TTrl-,-----,
~ I 10UTI
OUT
SAMP E OUT
\ I SAMPLE I duf!
I 10UTI SAMPLE I I ~\ I SAMPLE I 10UTI
OUT
SAMPLE
~~~~~~~~~~~~cv.~~~~~~~~
V,1 Vyl V,1 Vyl
V,1
Vyl
Vyl V,1 Vyl V,1
V"
Vyl
Vyl Vd
V,1
D3k+Z
V,2
D3k+3
V,3 Vy3 V,3 Vy3 V,3 Vy3 VII.3 Vy3 Vx3 v 3 Vx3 Vy3 V,3 Vy3 V,3
V,2
Vy2 V,2
f,
Ga-l
S(
n
Ga-2
Ga-480
V,2 Vy2
((
J)
--------------------------------~s~
Video
DL/DR
OE
FD
Sample and
['
B
hold circuits ~
J
"l!0
I SAMPLE lOUT I I
SAMPLE
OUT
lour!
SAMPLE
lourl
SAMPLE
OUT
SAMPLE
I SAMPLE I
SAMPLE
I
I
UT
SAMPLE
10UTI
SAMPLE
SAMPLE
lour!
OUT
SAMPLE
OUT
I lour!
SAMPLE
SAMPLE
I ~~ lOUT I
~ I lOUT I
OUT \ I SAMPLE 10UTI
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u
c1l D3k+l
Vyl
V,1
Vyl
~ X X
V,1
D3k+Z
VX2~ X X
D3k+3
V,3
Ga-l
Ga-Z
Ga-480
~ X X
--------------~IIL----------------------s~s-------------------------Jr-l~._~_~------------~~r_---------
----------------------------------~--s~
HITACHI
868
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66300T
MODE 4
Dis
Vee
L/F
VeclGND
MSFI
Vee
MSF2
GND
Video
OL/OR
OE
FO
['
I SAMPLE lOUT I
SAMPLE
Sample and B
hold circuits ~
II
~
'"~
u:
I SAMPLE I
03k+l
Yxl
03k+2
_L>---<>--'-"'-.L>......./ Vxl
OUT SAMPLE
SAMPLE OUT
SAMPLE
C=I
I SAMPLE IOUTI
I SAMPLE lOUT I
OUT SAMPLE
Vyt
lOUT I SAMPLE I
Vxl
V)'t
Vxl Vyl
I SAMPLE lOUT I
au
OUT SAMPLE
SAMPLE OUT
IOUTI SAMPLE I
Vxl Vy1 Yxl
SAM LOUT
lOUT I SAMPLE I
\ I SAMPlE IOUTI
I
)~
I SAMPLE I
IOUTI
Yyl Vxl
yZ VxZ 11),2 VxZ Vft "xl IIf2 V.,.2 "-VY",Z,,,,,V'~Z "V",yZ""=,,,",-=,,,,,,,,,
Vxl VyJ Vxl Vy3 Vxl V)'3 Vxl VyJ Vxl V 3 Vxl Vy3 VK3 Vy3
03k+3
Ga-l
______~!lL________________________~~~------------
Ga-2
-------______~r-lL____~~-------------------------(~h-----------------
Ga-480
------------------------------~·-·s~
Video
282
r---Lr---'S--~
283
I
OL/OR
OE
FO
---,
['
~
'""2
I SAMPLE, lOUT I
I SAMPLE lourl
Sample and B
hold circuits ~
SAMPlE
OUl
SAMPLE
SAMPlE OUT
I SAMPLE I
lourl SAMPLE I
I SAMPLE IOUTI
T SAMPlE
SAMPlE OUT
lOUT I SAMPLE I
I
SAMPLE OUT
IOUTI SAMPLE I
I
u
,J! 03k+l
Vyl V,I
Vyl Vxl Vyt Vxl
03k+2
Vy2 Vxl
Vy2 Vxl Vyt Vxl Vyt Vxl VyZ V,Z VyZ
03k+3
Vy3 Vxl Vy3 Vxl Vy3 Yxl Vy3 Vxl Vy3 Vxl Vy3 Yxl
Vyl
V,I
Vyl
IOUTI
I
louT!
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0
Vyt Vxl
~
~
OUT
V,I
S~
I SAMPLE I
I
~
X X
~
X X
vxz~ X X
Ga-l
____________________~r!L_________________________~___~~------------------
Ga-2
------------------------~I!~
.. ~----------------------------~~~-------------------
Ga-480
------------------------------~.,s~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
869
HD66300T
MODE 5
r
DIS
Vee
L/F
GND
MSFI
GND
MSF2
Vee
Video
DL/DR
OE
FD
S\ I
LrLJ'u,...,u,...,u'L.r.u,....,u,...,u'L.J1..Tu,...,uuUl..ru,...,u,...,u'LJ1wu,...,u'LSU1-lr-1L
-.-J
S\
I
-~-r
r-~I~Sr.AM~~~E'I~ou~t~I~Ir.~~M~P~LE~I~o~UT~1--Ir.s~Arr.MP~LE~lo~UT~I--rl~SAnMP~L~Er-lo~U~TIr-.--rl15r~rrlo~uT~I--.---,
SAMPLE
hokl circuits C
:l!
:l
i!!
Ii:
I
AM~E
UT
OUT SAMPLE
SAMPLE
SAMPLE
I SAMPLE I
0
lOUT I ~MPLE I
~MPLE
OUT
OUT
OU
SAMPLE OUT
lOUT I SAMPLE I
SA PL
\ I
OUT
lOUT I SAMPLE I
\ I
I
~~
louT!
~MPLE louT!
I SAMPLE I
lOUT I
D3k+l --~~~~~~V'~,~V'~3£.V~'2'~V'~I·/.V~'3~C~r.~·~·~~r.~/.~~~~r.~~V'~2!
D3k+2 --~~~~O-~V,~ZvV~,~I~V~'3~V,~2'/.V~"~V'~3V.V~'2~V.~IV.V~.3~fuV.~2UV~.~I·~~~~~~?J3
D3k+3
Ga-l
Ga-2
~'-'-.L>.--L>.--"'--' Vx3
V,,2
Vxl
Vx3 VxZ
.,
'--" =" "'''' VI( 1
Vx3 VxZ
--------~!I~-------------------------4%t-------------------------~r-l~----~~~-----------------------1~lr----------------
Ga-480
------------------------------~··s~
Video
282
283
DL/DR
OE
---,
FD
Sample and
[
B
hold circuits ~
:l!
~
OJ:
"8
c1l D3k+l
I SAMPLE lour!
I SAMPLE I
I SAMPLE IOUTI
I OUr!
SAM~E I
I SAMPLE IOUTI
I SAMPLE I
lour! SAMPLE I
I
lour! SAMPLE
SAM~E
IOUTI
IOUTI SAMPLE I
Vyl Vy3 Vy2 Vyl Vy3 VyZ Vyl
D3k+2
Vy2 Vyl
D3k+3
Vy3 Vy2 Vy 1 Vy3
Vy3
I SAMPLE IOUTI
Vy
I
lOUT I
Vy
!~
~~
loutl
I
)~
I
loun
I SAMPLE IOUTI \\ I SAMPLE loun
lour! SAMPLE I
Vyl Vy3 Vy2 Vyl
I
I
S~
I
~M~E1
I
xX
XX
XX
Ga-l
--------------~r-lL---------------------4S~\------------
Ga-2
____________________--J~~
•.~.~------------------__--~q~,--------------
G~-480
__
---------------------------------···~··s~
HITACHI
870
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
HD66300T
MODE 6
Dis
Vee
L/F
GND
MSFI
GND
MSFZ
GND
Video
DL/DR
OE
FD
Sample and
hold circuits
I SAMPLE IOUTI
['
B
SAMPLE
~
I SAMPLE IOUTI
OUT
SAMPLE
SAMPLE OU
I SAMPLE I
I SAMPLE IOUTI
OUT SAMPLE
SAMPLE
OUT
lOUT I SAMPLE I
I SAMPLE IOUTI
OUT SAMPLE
SAMPLE OUT
lour! SAMPLE I
I
OUT
SAMPLE OUT
lOUT I SAMPLE I
S~~Tlo"'U""T"'I-r----'
~ I
IOUTI
\1 SAMPLE IOUTI
I
~~
I SAMPLE I
lOUT I
~
'"
~
D3k+Z
VxZ Vx3
D3k+3
Vx3
Ga-l
Vx2 Vl!3 Vxl
Vxl Vx2
D3k+l
________
x3
VI( 1 VxZ
~IIL
Vx3
Vx 1
Vxl
Vx2
x2 Vx3 Vx 1 Vx2 Vx3 Vx 1 Vx2 Vx3
__________________________
~~------------
Ga-Z
_____________~r_lL____~~~----------------------~%~----------------
Ga-480
-------------------------------·~-s~
Video
DL/DR
OE
FD
--,
if
r--r--,-~-rl~SA~M~P~LE~I~o~UT~I-TI's~AMWP"L.....L>.-L"---O--J>;.Y::';'I, ""Y';:,l
03k+Z
Ga-l
I SAMPLE 10UTI
SAMPLE
SAMPLE
our
I lourl
1 Yx 1 VIC 1
xl
x2 Vx2 VxZ Vx2
x3
1t3 Vd Vd VIC3 Yx
our
SAMPLE
\I
PL
SAMPLE I
SAMPLE
I DUTJ
I )~ I SAMPLE I
IOUTI
xl Vx 1 VIC 1 Vx 1 'Ix 1
x2 Vx2
xl VxZ
Yx2
x2
VIC] Vx3 Vd Val Vd
______~!lL_____________~~~----------______~rlL__-=~~------------------~%~r-------------
.
----------------------------~s~
Video
OL/OR _ _ _ _ _ _L-_...I-_-L_ _L-_...I-_---L_---l_ _..L--I,\---L_ _ _ _ __
OE
li-
; :~P:rc~:---"!~5~~~~m~
~PLE:
~PL£:
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r
S\
A
:
]
cBo
FO
I . I SAMPLE lourl
:
I SAMPLE lour I
lour:
03k+Z
Z Z Z Z Z Z Z
Z Z X X XX X
03k+3
g g X g g g g
03k+l
Ga-l
G~-Z
SAMPLE:
SAMPLE oun
SAMPLE ourl
lour I SAMPLE I lour I SAMPLE I lourl
-,
I SAMPLE I
I SAMPLE lourl
lour:
I
lour:
SAMPLE
SAMPLE
I ~~ lour I
:
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I I SS
I
I lourl
I SAMPLE lourl
I SAMPLE I I
-~
-~
-~
n
X Z
X Z
Z X
SS
n ....
'J;
G~-480
SS
n
HITACHI
872
Hitachi America, Ltd.• Hitachi Plaia. 2000 Sierra Point Pkwy. it Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODE 8
D/S
Vee
L/F
Vee
MSFl
GNO
MSF2
Vee
Video
DL/DR
OE
FD
~
Sample and B
hold circuits ~
D3k+l
D3k+2
ISAMPLE lOUT I I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE lourl
I S\ lourl
ISAMPLE I lOUT I SAMPLE I lourl SAMPLE I lOUT I SAMPLE I lour I I)~ I IOUTI
I I SAMPLE lour! I SAMPLE lourl I SAMPLE IOUTI I SAMPLE IOUTI S\ I SAMPLE IOUTI
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I I S< I SAMPLE I IOUTI
~/~~,~~,v
--~~~r-~~~~~C~/~.~~C~~~~C.~/~~~£.~,~~~~~l
D3k+3
A~-~~~~'~
Ga-l
______~!I~--------------------------*~------------
Ga-2
________~I1~__===_----------------~~------------
Ga-480
-----------------------------------~--S~
Video
DL/DR
VUlJUUUL
OE
FD
I
---[:
hofd circuits C
il
'"'"
"
D
I SAMPLE lourl I SAMPLE IOUTI I SAMPLE
I SAMPLE I lourl SAMPLE I lourl SAMPLE
~S
I S~
I II
IOUTI I SAMPLE IOUTI II
I IOUTI SAMPLE I 11\
I SAMPLE lOUT I I SAMPLE lOUT I I SAMPLE lourl I SAMPLE lOUT I
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I lOUT I SAMPLE I IOUTI
lour I
I IOUTI
I SAMPLE IOUTI
I SAMPLE I IOUTI
0
'*
D3k+l
Vyl
D3k+2
Vy2
D3k+3
Vy3
Ga-l
--______~I1L_________________________~\rl------------
Ga-2
----------~rI~----~~------------------_1II\._------~----
Ga-480
----------------------------------~-i~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
873
HD66300T
MODE 9
Dis
Vee
L/F
Vee
MSFl
GND
MSF2
GND
(Video
OL/oR
OE
FD
[
Sample and B
hold .Circuits ~
I SAMPLE lour!
I SAMPLE lour I I SAMPLE lourl I SAMPLE lourl
I S~
I SAMPLE I lour! SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl I S\
I SAMPLE lourl I SAMPLE IOUTI I SAMPLE !ourl ! SAMPLE lour! S~
I SAMPLE I lOUT I SAMPLE I lourl SAMPLE I IOUTI SAMPLE I I S<
D3k+l
louTI
I lourl
I SAMPLE !ourl
I SAMPLE! IOUTI
~'~~'~~'~J~V~yl~~V~'2,~Vy~3"V~'~1 ~V~y2~~=,
03k+Z --tr~~r-~~~A.-.~A.~'~~~~~(~~,r.~~v.~V~Y~2f.V~'3~kV~Yl~V'~2~~~
03k+3 ~D-~-L~~J,V~,37~V~yl/~V'~Z~Y~~~~J~~'~'~Jx~'~'~'J3.~V~yl~~~~
Ga-l
________~!lL------------------------_;~r-----------
Ga-Z
----------~,,~--~==------------------~~)-------------
G~-480
Video
------------------------------------------------------------~--~~
--Ir--~r_--OJ----Lr--_CS_----u---u
--lJ ._--. .
---u-~~
DL/DR
OE
FD
I
Sample and
l
B
hold circuits ~
:!2
Q)
'"8"
c:
Jl
D3k+l
I SAMPLE lourl
I SAMPLE IOUTI I SAMPLE lourl I SAMPLE IOUTI
! S\
I SAMPLE! lourl SAMPLE I lourl SAMPLE I lOUT I SAMPLE I IOUTI 11\
I SAMPLE IOUTI
I SAMPl.E louTI I SAMPLE lourl
I SAMPLE IOUTI II
I SAMPLE I lourl SAMPLE I lour! SAMPLE I lourl SAMPLE I I S\
louTI
I IOUTI
I SAMPLE lourl
I SAMPLE I IOUTI
D3k+Z
.D3k+3
Ga-l
________
Ga-l
__________~rJL___~~--------------------~II\~-----------
G~-480
---------------------------------------------_-i~
~"L
____________________________
~\)I-------------
HITACHI
874
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODE10
D/S
Vee
L/F
Vee
MSFI
Vee
MSF2
Vee
Video
DL/DR
OE
FD
~
Sample and B
hold circuits ~
I SAMPLE lOUT I
I SAMPLE I
I
I SAMPLE IOUTI
lOUT I SAMPLE I
I SAMPLE IOUTI
I SAMPLE I
I SAMPLE IOUTI
lour! SAMPLE I
I SAMPLE IOUTI
IOUTI SAMPLE I
I SAMPLE-loUTI
lOUT I SAMPLE I
I SAMPLE IOUTI
IOUTI SAMPLE I
lOUT I
I
~\
I
S\ I
I SAMPLE IOUTI
IOUTI SAMPLE I
I
lourl
lOUT I
S\ I SAMPLE IOUTI
SS
I SAMPLE I
IOUTI
D3k+l ~~~~~~~V~'I~VY~I~V'~I·/'V7Y~I~~~/.~~V'-~~~V'-~~-~~~
D3k+Z
--~~~r-~-v.V~'2~~V~Y2~~~2V'-~~Z~~~~~~AV~~~~~~~~
Vx3 Vy3
D3k+3
Vx3 Vy3 VIIJ Vy3 Vx3 Vy3 Vx3 Vy3 Vx3
)'3 Vd Vy3
x3
Ga-l
______~!IL------------------------~~r----------
Ga-Z
---------~!lL--~==------------------~~r-----------------------
G~-480
----------------------------------------------------------------~--S~
Video
U
-~
IJ
S~ I
DL/DR
OE
_·t
FD
I
hold circuits
~
-g
8G
(I)
I SAMPLE IOUTI
I SAMPLE I
C
I SAMPLE lourl
0
I SAMPLE I
D3k+l
D3k+Z
D3k+3
I SAMPLE IOUTI
IOUTI SAMPLE I
--'''--''---LC''--'~J
I SAMPLE lourl
IOUTI SAMPLE I
I SAMPLE
lOUT I
IOUTI SAMPLE I
Vyl
V.I
Vyl
Vy2
V,2 Vy2
I SAMPLE loun
IOUTI SAMPLE I
Vxl Vyl VitI Vyl VitI
,2 Vy2
I
S\
lourl
I
~\
I
I SAMPLE lourl
S\
I SAMPLE IOUTI
S\
I SAMPLE I
I SAMPLE IOUTI
IOUTI SAMPLE I
vyl
,2 Vy2 v,2
Vxl
IOUTI
IOUTI SAMPLE I
yyl
Vxl
I
IOUTI
IOUTI
Yyl
y2 V,2 Vy2 V,2 ~y2
Vy3
Ga-l
--------~rlL--------------------------_;l~!------------
Ga-Z
----______~r-lL____~~--------------------~!rl----------------------------
G~-480
----------------------------------------------------4-i~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
875
HD66300T
MODEll
DIS
Vee
L/F
Vee/GND
MSFI
Vee
MSF2
GND
(Video
DL/DR
OE
FD
[
Sample and B
hold circu~. ~
~;;
I SAMPLE lOUT I I SAMPLE lOUT I I SAMPLE IOUTI I SAMPLE 10UTI
I Sl-~T:lo"'u"'rlr-.----,
I SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I lOUT I SAMPLE I 10UTI I S\ I 10UTI
I SAMPLE 10UTI I SAMPLE lourl I SAMPLE 10UTI I SAMPLE 10UTI S\ I SAMPLE 10UTI
I SAMPLE I IOUTI SAMPLE I 10UTI SAMPLE I IOUTI SAMPLE I I S~ I SAMPLE I 10UTI
.~
u.
D3k+l
D3k+Z
V,1
V,1
Vyl V,1
Vyl V,1
Vyl
V,1
Vyl
V,1
Vyl
V,1
VyZ VIIZ Vy2 V,Z VyZ Vx2 VyZ V,Z VyZ V,Z
V,Z
~o-~-L~O_J~~~/~~\~.~/~~\~~/~~\~~rwCJ\~~~~~~~
V,3 Vy3
D3k+3
V,3
n
Ga-l
II
n
Ga-Z
Ga-480
Vyl
~~~-£~a_J~~~/~~~~/~~~~~~~~/~CY\~~~~~
S\
--------------------------------~--s~
Video
DL/DR
OE
FD
I
Sample and
l
B
hold circuits ~
!I
.!
"8c
.
(J)
D3k+l
D3k+Z
I SAMPLE 10UTI I SAMPLE lourl I SAMPLE 10UTI I SAMPLE 10UTI
I S\
I SAMPLE I lourl SAMPLE I 10UTI SAMPLE I 10UTI SAMPLE I 10UTI I S~
I SAMPLE 10UTI I SAMPLE lourl I SAMPLE 10UTI I SAMPLE lourl S~
I SAMPLE I 10UTI SAMPLE I lourl SAMPLE I 10UTI SAMPLE I I S~
Vx'
Vyl
Vxl
yl VKl
VxZ V'IZ Vxl
y2 VxZ
'11
Vxl
'I'll Vxl
,'11 Vxl
\I'll Vxl
'11
Vxl
Vx2 \lyZ Vxl "'12 Vxl
yZ VxZ
"-='
=,n,,,J'
D3k+3
10UTI
I 10UTI
I SAMPLE 10UTI
I SAMPLE I 10UTI
Ga-l
--------~!I~----------------------------~Il~-------------
Ga-Z
----------~nL-----~--------------------~IIr_-------------
Ga-480
-------------------~-------------~-\~
HITACHI
876
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODEl2
DIS
Vee
L/F
GNO
GNO
MSFI
- MSF2
--- ----Vee
Video
DL/DR
OE
FD
A
Sample and
8
[
hold ci«uit. ~
ISAMPlE lOUT I I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE IOUTI
I Sf-~"'IO"'U"'TIr-..,---.,
ISAMPLE I lOUT I SAMPLE I IOUTI SAMPLE I lOUT I SAMPLE I lOUT I I S\ I IOUTI
I SAMPLE IOUTI I SAMPLE IOUTI I SAMPLE lOUT! I SAMPlE IOUTI S\ I SAMPLE IOUTI
I SAMPLE I lour! SAMPLE I IOUTI SAMPLE I IOUTI SAMPLE I I S~ I SAMPLE I IOUTI
Vxl
D3k+l
Vx3 VxZ Vxl Vx3 Vx2 Yxl
D3k + 2 ~<::r"--v-';:"'<::r"-v.V;:::'2>.A.V::-;'Iv.::
V,""3v.7
Vx2
VJ(J Vx2
Vxl
Vx3 Vx2 Vxl
VII 1 Vx3 VxZ V)( 1
D3k+3
--'.~..a..-LC"---,,-,-.,,V:.:.:.;'3:r,,,V,,,,2,~V,,,,1",V=lC3
Ga-l
___--'n
~\
Ga-2
-------'"
SS
Ga-480
---------------------·-------~---S~
VItZ Vxl
Vx3 Vx2 Vxl Vlt3 Vx2
Video
DL/DR
OE
FD
~~~~~~~~~~~~;=~~~~~S~~~~==~--Ar I
IOUTI I
IOUTI I
IOUTI I
IOUTI
I S\ IOUTI
SAMPLE
Sample and
[B
hold circuits
CD
SAMPLE
ISAMPlE I
SAMPLE
lOUT I SAMPLE I
I
I SAMPLE louT!
I
I SAMPLE I
D3k+l
Vyl
D3k+3
V 3 Vy2
Vy3
I SAMPLE louTt
IOUTI SAMPLE I
Vy2
Vyl
SAMPLE
lour! SAMPLE !
I S~ I
lOUT I SAMPlE I
lOUT I
SAMPLE lOUT!
I
SAMPLE
loun
IOUTI
SAMPlE
I
I
!oUTI
SAMPLE
I
lOUT I
~~ I SAMPLE IOUTI
I S\ I SAMPLE I
IOUTI
Vy3 Vy2 V 1 "'"'-"''''-"-,''-'-'A=:/"-,-,-,,,-,-Y,\::2::/,,,,,,,,,
2 "",-,,,,""-=r
Vyl ",VY",3"V'-'-'=r
Ga-l
-----'n~--------------------------l!rl-----------
Ga-2
---------'!lL--~~-----------~--~IIIr_------------
Ga-480
-------------------------------------'l-\~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
877
HD66300T
MODEll
DiS
Vee
L/F
GND
MSFI
GND
MSF2
GND
Video
OL/DR
OE
FD
~.~~:
hold circuits C
0
i
'"
~
I SAMPLE 10uTi I SAMPLE lour! I SAMPLE lourl I SAMPLE lourl I· I S\ lour!
I SAMPLE I 10uTi SAMPLE I lourl SAMPLE I lourl SAMPLE I lourl I S\ I lourl
I SAMPLE lourl I SAMPLE lour! I SAMPLE lour! I SAMPLE lour! S~ I SAMPLE lourl
I SAMPLE I lour! SAMPLE I lourl SAMPLE I lourl SAMPLE I I S~ I SAMPLE I lourl
03Hl ~~~-o~r-V"-VX~1j,V~x2~vx~~V~X~~~2V.V~XJ~~~lV.V~x2~Vx~~~~~~~~M
D3k+2 ~~>T-o~r-~V~x~2j,V~xJ~Vx~1~x2~~~V~x~1~Vx~2V.V~x~3j,V~xlV"-~~~~~Av.~
D3k+3
~0-~~~~,~VxJJ,~V~xl~~Vx~2AV~x7~~~1"V~xJ2~V~xJ"V~xJl~V~x2,=VXJJxV~Xl,~vxJ2.~V~x3~~~~1,~~~
Ga-l
------~,,~------------------------~~-----------
Ga-2
--~----~!I~--~~----------------~~\--------------~--------~---
Gl-480
------------------------------~--~~
Video
DLIOR
OE
FD
---,
Sample and
['
B
hold circuits ~
.
!'"
1 D3Hl
II
D3H2
D3H3
ISAMPLE lour! I SAMPLE lourl I SAMPLE louT! I SAMPLE lour!
I ~\
I SAMPLE I lour! SAMPLE I lour! SAMPLE I lourl SAMPLE I lourl I \<
I SAMPLE lour! I SAMPLE 10UTI I SAMPLE 10UTI I SAMPLE lour! S~
I SAMPLE I louT! SAMPLE I louT! SAMPLE I 10UTI SAMPLE I I S\
V 1 V 2 Vy3 Vyl Vy2 V 3 V I
--',",,-.£>...~-J->...J
Vy2 VyJ Vyl
Vyl
y2 VyJ
y2 VyJ
louT!
I lourl
I SAMPLE 10Un
I SAMPLE I lour!
2 Vy
yl V Z VyJ
yl vy2 Vy3 vyI
Ga-l
________~r!L___________________________~"------------
G~-2
----------~rlL----~~------------~----_1«I~----------------------- -- .. - ..... _.. --. ----
Gj-480
-------------------------------------------·----~·i~
HITACHI
878
Hitachi America, ltd.· Hitachi Plaza - 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819- (415) 589-8300
HD66300T
-~----
MODE14
DIS
Vee
L/F
GND
MSFI
Vee
MSF2
Vee
Video
OL/OR
DE
FD
A
Sample and
hold circuits
03k+l
[
B
~
I SAMPLE lOUT I I SAMPLE 10UTI I SAMPLE 10UTI I SAMPLE lOUT I
I ~~
I SAMPLE I 10UTI SAMPLE I 10UTI SAMPLE I 10UTI SAMPLE I 10UTI I ~\
I SAMPLE 10UTI I SAMPLE 10UTI I SAMPLE lOUT I I SAMPLE 10UTI II
I SAMPLE I 10UTI SAMPLE I 10UTI SAMPLE I 10UTI SAMPLE I I ~~
-J.:>"-.£>..-C'-'~J"-V::;'l",-V::.:'l/,,-VlIl
VxZ Vxl
03k+2
Yx2
lourl
I 10UTI
I SAMPLE 10UTI
I SAMPLE I 10UTI
Vx 1 Vx 1 VII 1 VII 1 Yx 1 VII 1 VI( 1 Vx 1 Yx 1 Vx 1 VII. 1
V.,2 Vx2 VxZ VxZ V·1.2 VxZ Vxl Yx2 VxZ YxZ YxZ
D3k+3 ---"~...L>.-L.'---'<..LJ VIIl Vx3 Vxl Vlll Vxl Vxl Vxl Vxl Vx3 Vxl Yxl """'~::J"=''-'=
Ga-l
______
Ga-2
________~J1L__~==~--------------~~>-----------
Ga-480
-----------------------4---S'~
~IIL
________________________
~\r\-----------
Video
OL/OR
OE
FO
~L~~~~~~~~~~~~~~~~~h~~==~-A r I
10UTI I
10UTI I
10UTI I
10UTI
I S\ 10UTI
SAMPLE
Sample and
[B
SAMPLE
I SAMPLE I
hold circuits CD
I
10UTI
SAMPLE
lourl
I SAMPLE I
03k+l
03k+2
V}/1
---,,<..L-L>--L>..-L>-J
SAMPLE
V}l1
V,2 V,2
SAMPLE
I
SAMPLE
I SAMPLE louT!
10UTI
V)l1
10UTI
Vyl
SAMPLE
I
SAMPLE
I
I
10UTI
lourl SAMPLE I
SAMPLE IOUTI
SAMPLE
V 1 V}l1 V 1 V)l1 V}l1
I
I
10UTI
10UTI
11\ I
SAMPLE IOUTI
SAMPLE
I
~~ I
10UTI
SAMPLE IOUTI
I S) I SAMPLE I
10UTI
Yyl Vyl ",V,-"l/",--,/,,:L:../"-l.:~'
~~V~'2~~~~~'~
V 2 v,2
Ga-l
________
Ga-2
__~---~r-L----~~-------------~II\r_----------
~IIL
__________________________
~!~I------
____- -
Ga-480 ___________________________________
--~--\~
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
879
HD66300T
MODElS
GND
DIS
l/F
Vee
MSfl
GND
MSf2
Vee
Video
DL/OR
DE
FD
::PIe
hold
circuits
i
'"
~
~MPLEI OUT ISAMPlE lOUT ISAMPLE! OUT I SAMPLE I OUT ISAMPLEI OUT ISAMPLEI
B
Not used
C
Not used
r
0
I SAMPLE lOUT I SAMPLE lOUT I SAMPLE! OUT I SAMPLE lOUT I SAMPLE I (lUT I
S~I(lUTI
S~
I SAMPLE I
M
I
~
03k+1
V,1
Vy2
V,J
Vyl
V,2
VyJ
V,1
Vy2
V,J
03k+2
V,2
VyJ
V,1
Vy2
V,J
Vyl
V,2
VyJ
V,1
Vy2
~
03k+3
V,J
Vyl
V,2
VyJ
V,I
Vy2
VxJ
V.I
V,2
VJ
~
Ga-l
__________~r__l~__________________________________r~~-------------
Ga-2
----__--------~r--l~--~__----------------------~'~A------------n - - _________ "" ___ " n ____
Ga~240
"""""~
Video
OL/OR
DE
---,
FO
~
I SAMPLE I OUT ISAMPLEI OUT ISAMPLEI OUT !sAMPLEI
~~P/. B
l!
o!
hold
J
C
Not used
circuits '0
."
\\ I SAMPLE I OUT I
Not used
I
I
03k+1
X
X
X
03k+2
X
X
X
D3k+3
X
X
X
I SAMPLE I
OUT I SAMPLE I OUT ISAMPLE! OUT ISAMPLll OUT I
SS
lOUT I
Ga-l
____________________~-Jr--l~----~----------------~~Ir-------------
Ga-2
-"""-~___ C_________________ """ ___________ "_~~~
Ga~240
HITACHI
880
Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66300T
MODEI6
DIS
GND
L/F
Vee
MSFI
GND
MSF2
GND
Video
DL/DR
OE
FD
A
$1
I SAMPlE! OUT ISAIII'lE lOUT I SAMPlE , OUT I SAMPLE! OUT I SAMPLE lOUT I SAMPLE I
Sample
OUT I
Not used
and
[B
hold
C
circuits D
Not used
ISAMPlE! OUT I SAMPLE' OUT (SAMPLE! OUT I SAMPLE ( OUT ( SAMPLE (
D3k+1
V,I
D3k+Z
v,3
D3k+3
Vy3.
V,Z
Vyl
V.3
Vyl
V,3
VyZ
V,I
V2
V,I
v,3
V,Z
out (
~\ ( SAMPLE! OUT (
VZ
V,I
Vy3
V,Z
VI
~
Vyl
Vx3
VZ
V,I
V3
~
Ga-l
__________-Jr__IL________________________________~~~------------
Ga-Z
--------------~r--I~--~.~~_.-
... __-._-.._-.-__-__------------------~~b----------------------n---... ___ . ______ ...
Ga~Z40
n~
Video
DL/DR
OE
--,
FD
[
I SAMPLE I OUT I SAMPLE , OUT ISAMPLEI OUT ISAMPLEI
~ndmple B
~
"20
'*
hold
circuits
C
0
(
Not used
(
D3k+1
X
X
X
D3k+Z
X
X
X
D3k+3
X
X
X
Ga-l
Ga~Z
I SAMPLE I OUT
1SA!!'lE1
OUT (SAMPLEI OUT ISAMPLE( OUT (
\\ lOUT I
------------------~r-I~------------------~~r----------
----------------~~.h~~
__
Ga~Z40
\\ ISAMPLE lOUT I
Not used
.~_~~~--.-_--1---'---
___
- __
- _ _- _ _ _
- _ _- _ _ _
- _ _- - - __
_
- _ _- _ _ _
- ___
-._
__
-
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
.- ..-.- ....
----------.--.-.--.-.--~-
881
HD66300T
MODE17
DIS
GND
l/F
Vee
M~FI
Vee
MSF2
Vee
--.
Video
DL/OR
OE
FD
A
I SAMPLE lOUT ISAMPLE lOUT ISAMPLE lOUT I SAMPLE I OUT I SAMPLE I OUT ISAMPLEI
~:pI. B
Not used
hold
C.
circuits 0
Not used
[
D3k+l
I SAMPLE I OUT I SAMPLE I OUT ISAMPLE! OUT I SAMPlE I OUT I SAMPLE I
-"'~-L>.._..l>...---'''-..:.:V.,
. Vyl
V.,
Vyl
V.,
Vyl
V,I
Yyl
V,I
ouf
I
SS lOUT
I
S~ I SAMPLE I
ouf
I
YI
D3k+2
D3k+3
Ga-l
_ _ _ _ _~r__l~____________________________~----~~-------------
GaTZ
--------~r--l~-~~~-----------l~h---------------h-------------------J,~
Ga-240
Video
DL/DR
OE
FD
Sample
and
.
'"
1ell
l!
~
I SAMPLE lOUT I SAMPLE I OUT ISAMPLE! OUT I SAMPLE ,
hold
C
circuits 0
Not used
I SAMPLE , OUT I SAMPLE! OUT ,SAMPLE lOUT
D3k+l
X
D3H2
X
D3H3
X
Ga-l
Ga-2
Ga~Z40
\\ ISAMPLE lOUT I
Not used
B
_ _ _ _ _ _ _ _---Ir--l
!SAMPLE!
OUT,
s\ , OUT ,
S~
--.. -c=!h-________ ~---------m--------------~~
HITACHI
882
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODE18
DIS
GND
L/F
GND
MSFl
GND
MSF2
Vee
Video
DL/DR
OE
0l-fLJLJ1
S\
FD
A
I SAMPLE lOUT ISAMPLE lOUT I SAMPLE! OUT I SAMPlE lOUT I SAMPlE lOUT I SAMPLE I
Sample
and
[B
Not used
hold
C
Not used
circuits
0
I SAMPLE! OUT I SAMPlEI OUT I SAMPlE! OUT I SAMPLE! OUT I SAMPLE lOUT
D3k+l
Vxl
VxZ
VII3
Vxl
VxZ
Vx3
Vxl
Vx2
Vx3
I
SS
lOUT I
S~ I SAMPLE! OUT I
Vxl
D3k+2
D3k+3
.Ga-l
____________~r__lL__________________________________~\,~~--------------
Ga-2
--------------~r--lL--~~------------------------~~r_------------
.. _.--~-J~
Ga:240 ________________________________-_--_--_--_--_--_--_--_--_
~
Video
I ~S
DL/DR
I
OE
FD
Sample
and
hold
. circuits
~
I SAMPLE I OUT I SAMPLE I OUT I SAMPLE I OUT ISAMPLEI
\\ IsAlJPlE lOUT I
Not used
B
C
Not used
0
I SAMPlE I OUT I §l!MPlE lOUT ISAMPLE lOUT ISAMPlE I OUT I
S~
I OUT I
D3k+l
X
X
X
X
X
X
~
D3k+2
X
X
X
X
X
X
~~
D3k+3
X
X
X
X
X
X
~~
Ga-l
________________________~r__lL________________________~~~\--------------
Ga-2
__________________~~r-!~--------------~~._-----------------u---___________ u_
Ga:240
--S~
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
883
HD66300T
MODEl9
DIs
GND
L/F
GND
MSFI
GND
MSFZ
GND
Video
OL/oR
OE
FO
:~~Ple
hold
:s!
r
Not used
C
Not used
circuits 0
o!
~
ISAMPLfIOUT ISAMPlE lOUT 'SAMPlE' OUT ISAMPlEI OUT 'SAMPlE' OUT 'SAMPlE I
B
, SAMPlE , OUT , SAMPlE , OUT , SAMPlE lOUT I SAMPlE lOUT I SAMPlE lOUT I
03k+1
Vlcl
03k+2
Vx3
03k+3
Ga-l
V,l
vxz
V.l
V.l
Vlcl
V,l
v.z
V,l
v.z
V,l
. Yx3
v.z
S~IOUT'
S\ I SAMPlE I OUT
,
v.z
V.l
V.l
v.z
V.l
P<=
V.l
V.l
V'Z
VXI
Vlcl
~
----------~r--l~----------------------------~----~~r------------
Ga;2
__________~r__l~__~..~
...~
...~
...-...-..-...-..-._.-._-_._-.__-..-...-..-.. ___-__-. ..-...~~~
...-.. - - - - - - - Ga:240
Video
OL/OR
OE
FO
:s!
o!
I
-~
'SAMPlE' OUT 'SAMPlE' OUT I SAMPlE , OUT ISAMPlE'
Not used
I SAMPlE I OUT ISAItPLEI OUT 'SAMPlE' OUT
03k+1
X
03k+2
X
03k+3
Ga-l
Ga~2
Ga~240
\\ 'SAMPlE' OUT ,
Not used
and
B
hold
C
circuits D
x
X
X
X
X
X
______________________
'SAMI'U'
OUT'
S~, OUT I
>GiDGiDGiDGiDGI:X:YiDGDC::$::X:EX:~X=::X:
~r--l
~
.....C!_. __ ._~.---.-.--...-.... -....._. ___ ._~~
HITACHI
884
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
MODEZO
Dis
GND
L/F
GND
MSFI
Vee
MSF2
Vee
Video
DL/DR
OE.
FO
I SAMPlq OUT ISAMPlE lOUT ISAMPlE lOUT I SAMPlE lOUT I SAMPlE lOUT I SAMPlE I
Sample [ :
and
hold
C
circuits 0
SS lOUT
I
Not used
Not used
S\ I SAMPLE lOUT
I SAMPLE lOUT I SAMPlE lOUT I SAMPlE! OUT I SAMPlE lOUT I SAMPlE lOUT I
I
D3k+1
D3k+2
D3k+3
Ga-l
__________~r__lL__________________________________,~~------~-----
Ga-2
------------~r-I~--_==------_-
Ga~240
___-__-__-__-__-_--------~~,r-----------
---------------------------------------------.--~
Video
DL/DR
OE
FD
.
..,
l!
'"
15
'*
-~
I SAMPlE I OUT I SAMPLE I OUT I SAMPlE I OUT ISAMPlEI
\\ ISAMPLE lOUT I
Not used
and
B
hold
C
circuhs 0
Not used
I SAMPLE I OUT
ISAMPl~1
OUT ISAMPlE lOUT ISAMPLE lOUT
I S~ I
OUT
I
D3k+1
X X
X
X
X
X ~~
D3k+2
X
X
X
X
X
X
~~
D3k+3
X
X
X
X
X
X
~~
Ga-l
Ga,2
------~~I ' l
- - - - - - - - - : : - - - - - ' · - - - - - - - - - - - - - - - - - - - - __ •
Ga~240
~S~
__ u
~
_________________ • __
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
885
~
__
HD66300T
NTSC System TV Signals and LCD
can be driven likewise by the second field. In this case,
if one pixel of the LCD panel is considered, it is recognized that the pixel is driven by signals with opposite
polarity every frame. This lowers the alternating frequency to 15 MHz, which is only half of the frame
frequency. Driving LCD elements with signals of such
low alternating frequency causes flickering and degrades display quality. To raise the alternating frequency to 30 MHz, a method can be employed in
which LCD e1ements are driven once every field instead of once every frame.
A TV screen display, which is updated 30 times pel
second, is called a "frame" and is composed of 525
scanning lines. One frame contains two fields; scanning lines 1 to 262.5 scan the display in the first field,
and scanning lines 262.5 to 525 scan the display in the
second field to fi.11 the gaps which are left unscanned
in the first field. This scanning mode is called an
"inteJ;lace scan."
The time period in which one scanning line scans the
display is called a ''horizontal scanning period" and is
about 63.S /.Ls. Within the horizontal scanning period,
the time period that display operation is actually
performed is called the "valid display period". The
other period is called the "horizontal retrace period".
Specifically, in the first field, the first and second lines
of the LCD panel are driven respectively during the
first half and second half of the complete horizontal
scanning period. The same rule is repeated for the
following lines. In the second field, on the other hand,
the combination of two lines is different. The first line
is driven during the second half of the horizontal
scanning period, and then the second and third lines
are driven respectively during the first and second
half of the following horizontal scanning period. The
same rule is repeated for the following lines.
There are two modes fordisplayingaTV screen image
on an LCD panel. In the first mode, each scanning line
in the two fields is assigned to one line of the LCD
panel; thus, each of the 240 lines of the panelaredriven
by the positive signal in the first field and by the
negative signal in the second field. Here, 3O-Hz alternating frequency is available, but the number of vertical pixels is limited to 240.
Employing thj.s method enables the implementation
of 480 vertical pixels.
(Single-rate sequential drive mode)
3
Item
Symbol
Min
Input high-level voltage
Input low-level voltage
VIH
Vil
0.7 Vee
GNO
:::t:
Output high-level voltage
VOH
Vee -O.4
n
Output low-level voltage
Val
"U
Input leakage current (1)
IU1
-10
Input leakage current (2)
IU2
-10
Output current (1 )
lOUT
CI>
:::::!.
n
"Fl
~
·
s=
2:
ii>
1>1
·
~
0
0
0
Typ
CD'
~
a 0~ Output current (2)
·-
~
':'"
c:J
~.
Vee
0.3Vee
C"
'"
-I OH =0.3 rnA
IOl = 0.3 mA
+10
IJA
VI=OV,V ee
1
+10
-150
IJA
2
-10
IJA
VI = Vaa' Vee
Vee - Vaa = 20 V
Apply Yin to Vxand Vy.
+150
IJA
= (Vee - VBB)12
Voo =Vee -3V
+10
IJA
VbsH=Vee-3V
VbsB = Vee - 3 V
3.0
rnA
fCk
30
rnA
IJA
liN
IGNO
15
(")
>
'f
0
~
~
Ok = Yin - 0.5 V
OE= Vee 5
OE=GNO
OK = Yin + 0.5 V
= 2.5 MHz, Voo = Vee - 3 V
OE = Vee
OE=GNO
6
VbSH = Vee - 3 V, VbSB = Vee - 3 V
OE = 33 kHz,
OE duty = 7/32
'i.
<0
4
FO = 30 Hz
0
~
3
V
V
IBB
:l
5"
Notes
Yin
:I
Current consumption
Test Conditions
V
:I
"U
0
"U
Unit
V
0.4
en
iil
Max
Bias voltage
Vb
Vcc -4.0
Dynamic range
VOY
VBB + 1.5
01
00
<0
do
Co>
Vee -3.0
Vee -3.5
V
Voo = VbSH = VbsB,
Cl = 100 pF, tOOR:S 6.3 IJs
V
Vee - VBB = 20 V,
Ta = -10 to +60°C
-0.5 V < Voll < +0.5 V
0
0
Voo = VbSH = VbsB = Vee - 3 V
00
00
<0
5,7,9
S
en
en
w
o
o
t-3
11
00
DC Characteristics (VLCO = Vcc=5 V ±10%,GND=OV, Vcc -
VBB = 16 to 20 V, Ta =-20 to +75 °C) (Cont.)
::r:
Hem
Max
Unit
Test Conditions
Notes
5,8,9
~
~
Offset voltage
=l>
Symbol
Min
VOff{L)
-5-180
-5 + 180
mV
VCC -V BB =20V
VOff{H)
+55-180
+55 + 180
mV
fCk
Typ
Yin
=-11 V
Yin
= -1 V
Ta = -10 to + 60°C
3
~
~.
= 2.5 MHz
Voo = VbsH = VbSB
~
= Vcc -3 V
::r:
s:n
=""0
.
Ii>
N
Notes:
'"
""
0
0
0
en
~.
iil
:I
a 0~
""0
1.
2.
3.
4.
5.
6.
0
Mode setting: L/F =VCC' DIS =VCC' MSFI
""0
~ ~
.
co
:::>.
'"
0-
'"
::l
S1'
(")
l>
CD
"""
0
0
~
5'
CD
::::
~
01
00
'P
00
c..>
0
0
Applies to pins HCK1, HCK2, HCK3, DL, DR, FD, RS, OE, SHL, DIS, L/F, MSFl, MSF2, TESTl, TEST2, Vbo' VbsH' and VbsB·
Applies to pins Vx1, Vx2, Vx3, Vy1, Vy2, and Vy3.
Applies to pins HCK1, HCK2, HCK3, DL, DR, FD, RS, OE, SHL, DIS, L/F, MSFl, MSF2, TESTl, and TEST2.
Applies to pins DL and DR.
Applies to pins 01 - 0120.
The shift register is constantly shifting one 1.
7.
8.
9.
=GND, MSF2 =VCc
(The other input pins must be Vcc or GND level.)
The operations are the same as those when offset voltage is measured .
Definition of "offset voltage" is shown figure 27.
These characteristics are defined within the temperature which is shown in the test condition.
S
m
m
w
o
o
..,
HD66300T
AC Characteristics(VLCD = VCC=5 V ± 10%, GND = OV, V CC -
V BB = 16to 20 V, Ta = -20 to+75°C)
Item
Symbol
Min
Max
Unit
Three-phase clock period
tCKCK
210
1000
ns
Three-phase clock
pulse width
tCWH
100
ns
30
ns
20
ns
Test Condition
Notes
tcwL
Interval between three-phase
tlr1
clock falling edge and rising
edge
tlr2
t lr3
Interval between three-phase
trl
2
clock rising edge and falling
edge
30
ns
Clock rise and fall times
tel
DL, DR input setup time
tsu
50
ns
DL, DR input hold time
tHLI
20
ns
DL, DR output delay time
tpd
DL, DR output hold time
t HLO
5
OE input period
tcvco
30
80
J.l.s
OE input high-level pulse
width
tOWH
3
15
J.l.s
OE rise and fall times
tor
30
ns
90
ns
CL = 15 pF
ns
tol
FD input setup time
t FS
100
ns
FD input hold time
tFH
100
ns
Note:
1.
2.
Necessary for preventing the three-phase shift register from racing.
trf must satisfy the DR and DL input hold time (~I) of the next horizontal driver.
(trf + tHLo > t HLI)
HITACHI
Hitachi America, ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
891
HD66300T
DE
~~~~"~-----;~'----~)-----1 ~ lOps
_,
I
I
:
:
:
I
I
1-
60",5
."
:
'1
I
I
:
I
I
I
I
"":•...--=:;;"'---~
60",5
I
•!
_" -':---"::n---1;----JI nnn:: ____':":nnl ___ mnn ___
!
IVOff(H)
Dout
-11V
Voff(L)
n
_______________________ n_
)~
------------
---------------
Figure 27 Offset Voltage
HCKl
HCK2
HCK3
Figure 28 Three-Phase Clock Timing
HITACHI
892
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66300T
O.7Vcc
O.3Vcc
HCK1
HCK2
HCK3
O.7Vcc
O. 3Vcc
OL
OR
(OUTPUT)
1<-----11-------------
OL
OR
(INPUT)
tsu
Figure 29 Input and Output Timing
t.,
--
~
tOWH
O.7Vcc
OE
~
O.3Vcc
t,s
t,"
Z~0.7Vcc
FO
'-'rO.3Vcc
tODR
r 90%(V,"=Vcc -3.5V)
01-0120
X
10%(Vin=V•• +1.5V)
Figure 30 OE, FD Input Timing, Driver Output Timing
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
893
HD66310T-----(TFT -Type LCD Driver for VDT)
Description
The HD66310T is a drain bus driver for TFf-type
(thin film transistor) LCDs. It receives 3-bit digital
data for one dot, selects a level from eight voltage
levels, and outputs the level to an LCD.
The HD66310T can drive an LCD panel with an
RGBW filter to display a maximum of 4096
colors.
•
•
•
Features
•
Full color display: a maximum of 4096 colors
RGB color· filter: 512 colors, 8 gray scales
RGBW color filter: 4096 colors, 8 gray scales
High-speed operation
Number of input data bits: 3 bits x 4
Maximum operation clock frequency:
- 12 MHz (HD6631OT**12)
- 15 MHz (HD6631OT**15)
Maximum pixels: 480 x 640 dots
160 internal driver circuits
Bidirectional shift
Internal chip enable signal generator
Stand-by function
LCD driving voltage: 15 V to 23 V
CMOS process
Package: 203-pin TCP
Available in TCP packaging only.
Recommended for high volume applications only.
Difference between HD66310T**12 and HD66310T**15
Item
HD66310T**12
HD66310T**15
Maximum operating clock frequency
12 MHz
15 MHz
Power supply for logic unit
5 V±10%
5V±5%
Operating temperature
-20 to +75°C
-20 to +65°C
HITACHI
894
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
HD66310T
Pin Arrangement
Y2 Y4 Y6 Y8
Yl Y3 Y5 Y7
Yl54 Yl56 Yl58 Yl60
Y1S3 Yl55Yl57Yl59
------------------
(Top view)
1 VOL
2 Vll
3 V2l
4 V3l
5 V4l
6 VSl
7 V6l
8 V7L
9 VCC1
10 VCC2
11 EIOl
12 RVS
13 DOO
14001
15002
16 D03
17 DMYO
18010
19011
20 012
21 013
22 DMVl
23 D20
24021
25 022
26 023
27 DMY2
28 CLl
29 CL2
30BS
31 SHl
32 EI02
33 TEST
34 GNO
35
36
37
38
39
40
41
42
43
VEE
V7R
V6R
VSR
V4R
V3R
V2R
V1R
VOR
Note: This does not apply to TCP dimensions.
Pin Description
Pin List
Pin Name
Number of Pins
Input/Output
Functions (Refer to)
Vcc 1, Vcc2
2
Power supply
1.
GNO
Power supply
VEE
Power supply
VOL-V7L,
VOR-V7R
Power supply
2.
CL1
Input
3.
CL2
Input
4.
Input
5.
Input
6.
Input
7.
Input/output
8.
000, 010, 020,
to
003,013,023
16
12
RVS
SHL
EI01, EI02
2
TEST, BS
2
Input
9.
Y1-Y160
160
Output
10.
OMYO-OMY2
3
11.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
895
HD66310T
Pin Functions
1. Vee1, Vee2, GND, VEE: These pins are used
for the power supply.
Vcc'-GND: Power supply of low voltage
Vce-VEE: Power supply of high voltage
2. VOL-V7L, VOR-V7R: 8-level LCD driving
voltage is applied to these pins. One of the eight
levels is selected according to the value of the 3-bit
input display data. The L and R pins of the same
voltage level are connected in the driver.
3. eLl: Inputs clock pulses, which determine the
output timing of the LCD driving voltage. The
output changes at the CL 1 rising edge.
4. CL2: Inputs clock pulses, which determine the
input timing of display data. The driver samples
data at the CL2 falling edge.
Table 1 Voltage Level Selection According to Display Data Value
Display Data
Voltage Level
D2J
D1J
DOJ
RVS=1
RVS=O
0
0
0
VO
V7
0
0
1
V1
V6
0
0
V2
V5
0
1
V3
V4
0
0
V4
V3
0
1
V5
V2
0
V6
V1
1
V7
VO
Vee 1-...,.-----,
+
GND
VEE 1 - - - - - - - '
Figure 1 Power Supply for the Device
HITACHI
896
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
5. DOO-D03, DlO-DI3, DlO-D23: Input display
data. See table 1 for the voltage level selection by
the display data.
6. RVS': Determines if logical I/O display data is
reversed. Display data is reversed when RW is
low.
or output. When the chip enable input signal is
low, data input starts. When display data corresponding to 160 outputs are input, the chip enable
output signal changes from high to low.
9. TEST, BS: Used for test purposes only.
Connect to a low level for normal operation.
7. SHL: Selects the shift direction of display data.
10. YI-Y160: Output LCD driving signals.
8. EIOI, EI02: Inputs/outputs chip enable signals. The Sm.. signal selects which pin is for input
11. DMYO-DMY2: Reserved pins that should be.
left open.
Table 2 Input/Output Selection for EIOI and
EI02
SHL
EI01
EI02
GND
Input
Output
Output
Input
Vee
Output Direction
SHL
GND
Vee
i.0-2
DiO
Di1
Di2
Di3
(12 bits)
1-0-2
DiO
Di1
Di2
Di3
(12 bits)
d03,d13,d23
d02, d12, d22
d01,d11,d21
dOO, d10, d20
5
Y1
Y2
Y3
Y4
d03,d13,d23
d02,d12,d22
d01,d11,d21
dOO,d10,d20
Y157
Y158
Y159
Y160
dOO,d10,d20
d01,d11,d21
d02,d12,d22
d03,d13,d23
Y1
Y2
5
dOO,d10,d20
d01,d11,d21
d02,d12,d22
d03,d13,d23
Y3
Y4
Y157
Y158
Y159
Y160
Figure 2 Display Data and Output Direction
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
897
HD66310T
Internal Block Diagram
Y156 V158 V160
Y157 V159
Y1 Y2Y3Y4V5
VOL, V1l
V2l, V3l - - - - - - - - ' ' \ 1
V4l, V5l
V6L, V7l
-------v
lCO driving circuit
VCC1, VCC 2 - -••
GNO
..
VEE
~ Test circuit
VOR,V1R
V2R,V3R
V4R,V5R
V6R,V7R
TEST ----i.~I....:I_ ___11
1WS"-----,
Cl1
BS
Data reverse
circuit
000, 010, 020
001,011,021
002, 012, 022
003,013,023
---===il
SHl
CL2----.,
EI01
EI02
Latch address selector
HITACHI
898
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589c8300
HD66310T
Block Functions
Latch Address Selector: Contains a 6-bit up/
down counter and a decoder, and sends the latch
signals to latch circuit (1) at the CL2 falling edge.
Latch Circuit (2): Consists of three planes of
I60-bit latch circuit, which latches the data from
latch circuit (1) at the timing determined by CLI,
and holds the data for one line scanning period.
Data Reverse Circuit: Reverses the input display
0, and does not reverse data
data when RYS
whenRYS = 1.
Level Shifter: Raises the driving voltage of 5 Y
to the appropriate LCD driving voltage.
=
Latch Circuit (1): Consists of three planes of
160-bit latch circuit. Each bit of 3-bit data is separately latched in its corresponding plane depending
on its significance. Each plane is divided into
forty 4-bit blocks, and all four bits are latched into
the block at once, as specified by the latch signal
from the address selector. In total, the 3-plane circuit latches 12 bits of data at one time.
LCD Driving Circuit: Outputs an 8-level LCD
driving voltage. This circuit receives 3-bit data for
one dot from latch circuit (2) and selects one level
from eight voltage levels.
Test Circuit: Generates test signals.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
899
HD66310T
System Configuration
A block configuration of the TFf-type color display system using the HD66310 is shown in figure .
3.
The HD66310 receives 3-bit data for one pixel and
selects one of the eight LCD driving voltage levels
to send to the LCD. The LCD driving output
circuit, which is produced by the CMOS structure,
can use any LCD driving voltageS level from Vcc
to V BE. When the LCD panel uses an RGB color
filter (the Triad arrangement), 512 (8 3) colors can
be displayed. When using an RGBW color ftlter
(the Quad arrangement), 4096 (84) colors can be
displayed.
CPU
Una synchronization signal, data sampling signal,
3 alternating signal
Controller
Dis
12
3
2
Frame synchronization signal,
line synchronization Signal
HD61105
No.1
TFT-type color LCD panel
Triad arrangement
512 colors
640 x 480 pixels
HD61105
No.6
12
Figure 3 TFT-'IYPe Multiple Color Display System
HITACHI
900
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
Internal Operation
8-Level Output
The HD66310 internal circuit unit for one data output is shown in fIgure 4. The circuit receives 3-bit
data (DOj, Dlj, D2j) and selects one of eight voltage levels (VO--V7) to output to the LCD.
The transfer gates of the output circuit are produced by the CMOS structure. Therefore, any
voltage level between Vcc to VEE can be applied
to lines VO to V7.
The HD66310 has 160 of the above circuits.
Operation Timing
The HD66310 operation timing is shown in fIgure
5.
When the SHL signal is at the GND level, data
input is started by a low EIOI (data input enable)
signal. At the CL2 falling edge, 12 bits of data,
which are for four outputs (3 bits for gray scales x
4 outputs), are input together. When the data input
corresponding to 160 outputs are completed, the
HD66310 automatically enters the stand-by mode,
and the EI02 signal changes to low.
The LCD driving output changes at the CLl rising
edge. The voltage level selected by data dl is output from pin Yl, and the level selected by dl60 is
output from YI60. See table 1 for the voltage
level selection by the input data.
When the SHL signal is at the Vee level, data
input is started by a low EI02 signal. When the
data input for 160 outputs are completed, the EIOI
signal changes to low. The voltage level selected
by data dl is output from pin YI60, and the level
selected by dl60 is output from YI.
Vn
P: P-MOS
N: N-MOS
CL1
CL2
....
RVS------~~------~+_------~r_
Display data
(DOj)
Display data
(D1j)
II
Display data
(D2j)
Figure 4 LCD Driving Circuit
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
901
HD66310T
~
CL1
CL2
~ ___
1
234
~
~
5
U
~
$
~
~
000
to
--::::v-:;;;v-:
003
(Lower bit)
~____.
000
~
to
013
~
020
~
to
--::::v-:;;;v-:
023
(Upper bit)
~
SHL=GNO
EIOl , ' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
EI02
Y1
to
Y160
------------------------------~~
----------------------------------~~
SHL = Vee
EI02
11-______________________
EI01
Y1
to
Yl60
------~--------------------------------------~
------------------------------------~
Figure 5 Basic Operation Timing Chart
HITACHI
902
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
the next HD66310. Figure 6 shows a connection
example.
Cascade Connection
When the SHL signal is at the GND level. the
HD66310 begins to input data when the EIOI signal goes low. When the data input is completed.
the EI02 signal changes to low. By connecting the
EI02 pin of the fIrst HD66310 to the EIOI pin of
the next HD6631O. the low EI02 signal activates
When the SHL signal is at the Vee level. the EI02
pin of the fIrst HD663I 0 is connected to GND. and
the EIOI pin is connected to the next HD663IO
EI02pin.
DATA----~~~------------~------------~----
CL2--------;--+-----------+~~--------~--+_---
SHL
SHL
Driver 1
EI01
EI01
EI02
EI01
Driver 3
EI02
~\..._____________
CL2
___
Jl.JlJlSLJl
EI02
A
}
Driver 2
signals
Driver 2 input enabled
B
Figure 6 Chip Enable Operation (SHL = GND)
fJ
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
903
HD66310T
LCD Driving Power Supply Circuitry
Multiple-Level Driving Voltage Method
AC voltage must be applied to the LCD, since DC
voltage deteriorates the LCD. To display eight
gray scales, 16 voltage levels, shown in figure 7,
must be applied.
Although the HD66310 has eight LCD driving
voltage input levels, it can output 16 driving voltage levels using the level selector shown in figure
8, since the transfer gates of the output circuit are
produced by the CMOS structure.
External Power Supply Circuitry
Figures 8 and 9 show the external power supply
circuit when displaying 512 colors in the Triad
arrangement, and figure 10 shows the circuit for
displaying 64 .colors in the Triad arrangement.
Table 3 shows the specifications of the LCD panel
and the HD66310 pins for each power supply circuit.
The circuit shown in figure 8 is the basic one used
when displaying 512 colors in the Triad arrangement. However, the HD66310 can dispense with
the level selector, as shown in figure 9, using the
internal RVS" (output reverse) pin. See table 1 for
detailed RVS functions.
When displaying 64 colors in the Triad arrangement, the RVS pin functions as the alternating signal input pin, as shown in figure 10.
Vee
V1
V2
V3
V4
V5
V6
V7
va
V9
V10
V11
V12
V13
V14
V15
V16
----------------------------------------- VEE
Figure 7 HD66310 Output Waveform
HITACHI
904
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
Table 3 Color Display and Pin Specifications
Display Data
Output
Level
Panel Spec.
DI2
DI1
DIO
RVSpln
Powe, Supply
(Refe, to)
Sx2
(AC)
Quad: 4096 colors
Triad: 512 colors
1/0
(upper bit)
1/0
1/0
(lower bit)
1
Fig.S
Sx2
(AC)
Quad: 4096 colors
Triad: 512 colors
1/0
(upper bit)
1/0
1/0
Alternating
signal
Fig. 9
(lower bit)
4x2
(AC)
Quad: 256 colors
Triad: 64 colors
1
1/0
(upper bit)
1/0
(lower bit)
Alternating
signal
Fig. 10
1: Vee level voltage
0: GND level voltage
Alternating
signal - - - - - . . . ,
Vee
Vee
...-.1--.., VI
V16 ,..V-7----,
V2 V15 V6
V3 V14 V5
Level
selector
V4 V13
V5. V12
V6 VII
V7 Vl0
V4
V3
V2
VI
va, V9
VO
110
110
110
Vee
Figure 8 External Power Supply Example 1
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA94005-1819 • (415) 589-8300
,905
HD66310T
VEE
Figure 9 External Power Supply Example 2
Alternating
signal
Vee
Vee
Vl
V2
V3
V4
V5
V6
V7
va
V7
V6
V5
V4
V3
V2
Vl
VO
RVS
Oi2
Oil
OiO
1/0
1/0
VEE
Figure 10 External Power Supply Example 3
HITACHI
906
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
Design for Timing
11. However, the power supply lines immediately reverses polarity after a transition of the
RVS signal, as shown in figures 9 and 10.
Therefore, the HD66310 outputs invalid data
during the last CLl of a frame period.
When using the RVS pins to simplify the power
source, as shown in figures 9 and 10, it is recommended to add a vertical retrace period, (a scanning period in which no scan electrode is selected)
at the end of a frame scanning period, as shown in
figure 12, for the following two reasons.
In the power supply circuits shown in figures 9
and 10, voltage temporarily becomes unstable
just after the RVS transition, causing the LCD
display to become jumbled.
As shown in figure 4, the data reverse circuit is
before the latch circuit (1). The LCD driving
output is reversed one CLl period after a
transition of the RVS signal, as shown in figure
CL1
-1lL..___.....JnL-____rL
::x"____(+---_
RVS
------Jx~
LCD output
Figure 11
m- and LCD Driving Signals Timing
_--------Oneframeperiod-------_.
rL
Frame synchronization signal
Jl
Line synchronization signal (CL1)
~
Alternating signal
..
~oo~i~5ilectrodes
~
(j ~~~
X1
./ .
X2,'
"
X480 - - . . : - - - - -.....: - -
,
HD66310T
__ _
:\
__
=~:=====--...:
::-_-~~T
--------~----,~.-
---~
J_~fEiIi===ijii~.
Y1-Y160 . ,
Figure 12 Vertical Retrace Period
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
907
>
:g
~~ =:
~~
cc
0
CO
~::;:;
::z:
;:;:
n
2:
»
V~
3
CD
5"
P'
!::::
I ,-=====I+li::t:ttf:;
T
I
I
I II
""n"
1'"
•
~ 11111111
?-
•
::z:
g
"
Frame synchronlzallon signal
Un••ynchRm~aIIon.ignai
•
Data felch signal
Display data ( _ numbel)
Display data (odd nurnbeI)
~
D>
N
0
0
0
~!l
.~~
i~
LCD panel
AhrnaIIng signal
en
~
VI""
g~
2:
CD'
~~
ConIroIIer
:I
v.
(l~C
a i0
"
~ :E
"8
·
iii-
Nu...,.,"' ......: 512
Color arrangemanl: Triad type
Display capaciIy: 480 x 640 dots
IC for OCIIIInIng: HD61105
Fl t I .Note~ ;V7
V4
c-
u~
D>
::I
!"
-5cr
...
~'"
fg-
V5
a:J
~~
crQ.g
,-oGND
'" (OY)
n
»
1g'
;.
~
0
0
Ei"
~
Qq
cc
[
~
~
~
tn
co
%
~:
1. An operational ampIIIer ohouId be III8IaIIad on "'"'" level 01 the pcIWa' suppIr 1M (VO-V7) 10 lower the in1Jedance.
2. Conden... should be III8IaIIad . - the ICs 10 IlablIIze the pcIWa' oupplywllage.
T... D.1-1/f condensen ens reconmooldecllo be insIalIed on one IC: one ~ Vee and GiNO, and one ~ Vee and V...
3. ThIs system _12 HD66310T chIpe ancI12 HD61105 chIpe.
Co>
g
Figure 13 Application System Connection Example
Sf
g-
j
8
ag" .....
..,o
0')
0')
fA)
::J:
~
:2:
»
3
C1>
:::!.
~
c:
·
?-
· t'IOn--1l •
F.rame synchronrza
signal
Line synchronization
signal
-tl
r-l-
One frame period
Line 1
n
Line 2
n
Vertical
Line 3
rL- •••••••• ~
Alternating signal
::J:
X1
~
:2:
-0
~
·
o
""
Scanning
electrodes
(H061105)
X2
X3
~
co·
__
X~O
~ ~
~ ~
:;0
·-
""" :I
~
~
iiiil
____-+______
CD
:::!.
r
r:::r
~
'"
______
,~
A
~ One line period ~r-----
(/.I
______
.,
~~~~~~~"
H066310T Y1-Y160
~
~
~
_____________
::::I
!"
~
co
~
o
o
Data fetch signal
~
~
oOO I I I I I ITTl ITl I I I I I I I I I
co
~
~
n
~~~a?nchronizatio~
Display data
12 bit
L _ __
........ J1flIlJ1I1I1.IL
DJTIl 11- I rrl
{ 001 1 I 1 I I I I I I I I I I I I I 1 I I I I
S
I I II I I I I
II II
::r:
t11
00
co
~
o
023111111111111111111111
DIIIIlT-ITTI
o0>
0>
W
.,o
~
~
co
Figure 14 Timing Chart
HD66310T
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Notes
Power supply for
logic unit
Vee
-0.3 to +7.0
V
2
Power supply for
LCO driving unit
VEE
Vee - 25 to Vee + 0.3
V
Input voltage (1)
Vn
-0.3 to Vee + 0.3
V
Input voltage (2)
VT2
VEE - 0.3 to Vee + 0.3
V
Operating temperature
Topr
-20 to +75 (H06631 OT**12)
-20 to +65 (H06631 0T**15)
°C
Storage temperature
Tstg
-40 to +125
°C
2,3
Notes: 1. Exceeding the absolute maximum ratings could result in permanent damage to the LSI. The
recommended operating conditions are within the electrical characteristic limits listed on the
following pages. Exceeding these limits may cause malfunctions and affect reliability.
2. Values are in reference to GNO • 0 V.
3. Applies to input pins SHL, CL 1, CL2, BS, RVS, TEST, and 000-023. Also applies to input!
output pins EI01 and EI02 when these pins function as input pins.
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
Electrical Characteristics
DC Characteristics
(Vee +5 V ±10%, GND 0 V, Vee - VEE 15 to 23 V, T. -20 to +75°C in 12 MHz version)
(Vee +5 V ±5%, GND 0 V, Vee - VEE 15 to 23 V, T. -20 to +65°C in 15 MHz version)
=
=
=
=
Item
Symbol
LCD driving power
supply voltage
Vee - VEE
=
=
Min.
=
=
Typ.
Max.
Unit
23
V
Test Conditions
Notes
Input .high·level
voltage
0.8 x Vee
Vee
V
2
Input low-level
voltage
o
0.2 x Vee V
2
Output high-level
voltage
Vee- 0.4
0.4
Output low-level
voltage
V
IOH - -0.4 mA
3
V
IOL -0.4 mA
3
Input leakage
current (1)
-5.0
+5.0
V1N - Vee to GND
4
Input leakage
current (2)
-10
+10
VIN - Vee to GND
5
Input leakage
current (3)
-100
+100
V1N - Vee to VEE
6
2.5
kO
Current
consumption (1)
25
30
mA
mA
Data fetch 12 MHz
Data fetch 15 MHz
8, 10
Current
consumption (2)
2
mA
mA
Stand-by 12 MHz
Stand-by 15 MHz
8, 10
mA
mA
12MHz
15 MHz
9, 10
LCD driver on
resistance
Current
consumption (3)
RON
2.5
-lp3
3
3.7
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
Voltage between Vee and VEE.
Applies to CL1, CL2, SHL, Dij, RVS, EI01 (input), EI02 (input), TEST, and BS.
Applies to EI01 (output) and EI02 (output).
Applies to CL1, CL2, SHL, RVS, Dij, TEST, and BS.
Applies to EI01 (input) and EI02 (input).
Applies to VOL to V7L and VOR to V7R.
Applies to Y1 to Y160.
Current between Vee and GND under the conditions of V 1H • Vee, V1L - 0 V, and no load on the
output pins.
9. Current between Vee and VEE under the conditions of V 1H - Vee, V1L .. 0 V, and no load on the
output pins.
10. fel2 and fell are 15 MHz, 37.5 kHz respectively in 15 MHz version.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
911
HD66310T
AC Characteristics
(Vee +5 V ±10%, GND 0 V, Ta -20 to +75°C in 12 MHz version)
(Vee +5 V ±5%, GND 0 V, Ta -20 to +65°C in 15 MHz version)
=
=
=
=
=
=
Typ.
Max.
Unit
Test Conditions
Symbol
Min.
Clock period
tcvc
83 (66)
ns
Clock high-level
pulse width
tcWH
30 (23)
ns
Clock low-level
pulse width
tcWL
30 (23)
ns
Clock rise time
tR
10 (10)
ns
2
Clock fall time
tF
10 (10)
ns
2
Clock setup time
tsu
100 (100)
ns
2
Clock hold time
tH
100(100)
ns
2
Item
Notes
Data setup time
tosu
20 (10)
ns
3
Data hold time
tOH
30 (25)
ns
3
Enable input
setup time
tESU
20 (10)
ns
4
Enable output
delay time
tED
CL 1 high-level
pulse width
tWH
100 (100)
ns
5
RVS setup time
tRsu
50 (50)
ns
6
RVS hold time
tRH
50 (50)
ns
6
53 (46)
ns
See figure 16
for test load
4
Data in ( ) is the characteristics in 15 MHz version.
Notes: 1.
2.
3.
4.
5.
6.
Applies to
Applies to
Applies to
Applies to
Applies to
Applies to
CL2.
CL1 and CL2.
Dij and CL2.
EI01, EI02, and CL2.
CL1.
RVS and CL2.
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912
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66310T
Cl2
Dij
CL1
CL2
Enable output
Enable input
LCD output
Figure 15 Timing Chart
Chip enable
output
:-:l
30 PF;;;:
Figure 16 'fest Load
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
~.
.--~
913
"~-""---.---
LCD CONTROLLER/DRIVER LSI DATA BOOK
Section Eight
New Product
Information
HITACHI
HD66110T-------Column Driver
Description
Features
The HD66110T, the column driver for a large
liquid crystal display (LCD) panel, features as
many as 160 LCD outputs powered by 160
internal LCD drive circuits, and a high duty cycle.
This device can interface to various LCD
controllers by using an internal automatic chip
enable signal generator. Its strip shape enables a
slim tape carrier package (TCP).
• 186-pin TCP
• CMOS fabrication process
• High voltage
- LCD drive: 28 - 40 V
• High speed
- Maximum clock speed: 12 MHz
• 4- and 8-bit data bus interface
• Display offfunction
• Standby function
• Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LYlC series: HD66840, HD66841
- CLINE: HD66850
Pin Arrangement
.,.. N
»
0'10
11)«)
...........
..................................................................................... »
..- C\I •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
!.....................
11)«)
«)1I)~MC\I..-om~~«)II)~MC\I..-om~~«)II)~MC\I..
~~~~~~~~~~~~~~~~~«)«)«)«)«)«)«)«)«)
.,...,...,...,...,...,...,...,...,...,...,...,...,...,...,...,...,...,.. .................. .,...,...,...,...,..
Note:
This is just an example of TCP; other TCP shapes are also possible.
HITACHI
916
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66110T
Pin Description
Symbol
Pin No.
Pin Name
Input/Output
Classification
Vcc
175
Vcc
Power supply
GND
186
GND
Power supply
VLCD
164
VLCD
V1
166
V1
Input
Power supply
V2
162
V2
Input
Power supply
V3
165
V3
Input
Power supply
Power supply
V4
163
V4
Input
Power supply
CL1
179
Clock 1
Input
Control signal
CL2
178
Clock 2
Input
Control signal
M
180
M
Input
Control signal
0 0-07
167-174
Data o-data 7
Input
Control signal
SHL
183
Shift left
Input
Control signal
EI/o1, EI/02
177,176
Enable 10 1, enable 102
Input/output
Control signal
DISP
181
Display off
Input
Control signal
BS
184
Bus select
Input
Control signal
TEST1, TEST2
182, 185
Test 1, test 2
Input
Control signal
Y1-Y 160
1-160
Y 1-Y160
Output
LCD drive output
HITACHI
Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0 Brisbane,CA 94005-1819 0(415) 589-8300
917 '
HD66110T
Pin Functions·
Power Supply
Vcc' VLCP' GND: Vcc - GND supplies power to
the intemallogic circuits. VLCD - GND supplies
power to the LCD drive circuits. See figure 1.
VI, V2, V3, V4: Supply different levels of power
to drive the LCD. VI and V2 are selected levels,
and V3 and V4 are non-selected levels.
Control Signals
CLI: Inputs display data latch pulses for latch
circuit 2. Latch circuit 2 latches display data input
from latch circuit I, and outputs LCD drive signals
corresponding to the latched data, both at the
falling edge of each CLl p\llse.
CL2: Inputs display data latch pulses for latch
circuit 1. Latch circuit 1 latches display data input
via Do-D7 at the falling edge of each 0.:2 pulse.
M: Changes LCD drive outputs to AC.
Do-D7: Input display data. High-vpltage level
(Vcc level) of data corresponds to a selected level
and turns an LCD pixel on, and low-voltage level
(GND level) data corresponds to a non-selected
level and turns an LCD pixel off.
1
T
SHL: Shifts the destinations of display data
output, and determines which chip enable pin
.(EItOI or EIt02) is an input and which is an
output. See figUre 2.
EIIOI, EII02: If SHL is GND level, EltOI inputs
the chip enable signal, and Elt02 outputs the
signal. If SHL is Vcc level, EltOI outputs the
chip enable signal, and Elt02 inputs the signal.
The chip enable input pin of the first HD66110T
must be grounded, and those of the other
HD66110Ts must be connected to the chip enable
output pin of the previous HD66110T. The chip
enable output pin of the last HD66110T must be
open.
DISP: A low DISP sets LCD drive outputs
y 1-Y 160 to V21evel.
BS: Selects either the 4-bit or 8-bit display data
bus interface. If BS is Vee level, the 8-bit bus is
selected, and if BS is GND level, the 4-bit bus is
selected. In 4-bit bus mode, data is latched via
Do-D3; D4-l>] must be grounded.
TEST I, TEST2: Used to test the LSI, and must
be connected to Vee level.
LCD Drive Output
y 1-Y160: Each Y outputs one of the four voltage
levels VI, V2, V3, or V4, depending on a
combination of the M signal and display data
levels. See figure 3.
VLCD
....c- Vee
I
GND
Figure I Power Supply for Logic and LCD Drive Circuits
HITACHI
918
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66110T
SHL
= GNO, BS =GNC
Y1
Y3
Y2
Y5
Y4
Y7
Y6
Y153
Y155
Y157
Y159
Y154
Y156
Y158
Y160
Y8
103102101 100103102101100 1 ..._ ......_ ..... 103102101 100103102101 100
'\.
/
EliOt: chip enable input
1st data
"
I
/
Last data
ElI02: chip enable output
SHL = Vcc, BS = GNC
Y1
Y3
Y2
Y5
Y4
Y7
Y153
Y155
Y157
Y159
Y154
Y156
Y158
Y160
Y8
Y6
100 101 1021031001011021031 ..._ ......_ ..... 100 101 102103100101 102 103 1
/
'\.
EliOt: chip enable input
Last data
SHL
"
ElI02: chip enable output
'/
1st data
=GNO, BS =Vce
Y1
Y3
Y2
Y5
Y4
Y7
Y6
Y153
Y155
Y157
Y159
Y154
Y156
Y158
Y160
Y8
107 106 105 104 103 102 101 I 00 1 ..._ ......_ ..... 107 106 105 104 103 102 101 100 1
/.
'\.
1st data
'\.
EliOt: chip enable output
/
Last data
ElI02: chip enable input
SHL
=Vcc, BS =VC(
Y1
Y3
Y2
Y5
Y4
Y7
Y6
Y153
Y155
Y157
Y159
Y154
Y156
Y158
Y160
Y8
1001011021031041051061071 ..._ ......_ ..... 100 101 1021031041051061071
/
'\.
Last data
'\.
EII01: chip enable output
/
1st data
ElI02: chip enable input
Figure 2 Selection of Destinations of Display Data Output
HITACHI
Hitachi America, Ltd.· Hitachi Plaza ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
919
HD66110T
o
Y output leve
1
0
1
0
rV1 >rV3 tV2 >rV4 >1
Figure 3 Selection of LCD Drive Output Level
HITACHI
920
Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
HD66110T
Block Functions
. Latch Circuit 1
160-bit latch circuit 1 latches 4-bit or 8-bit parallel
data input via the Do to D7 pins at the timing
generated by the shift register.
LCD Drive Circuit
The 160-bit LCD drive circuit generates four
voltage levels VI, V2, V3, and V4, for driving an
LCD panel. One of the four levels is output to the
corresponding Y pin, depending on a combination
of the M signal and the data in the latch circuit 2.
Shift Register
The 40-bit shift register generates and outputs data
latch signals for latch circuit 1 at the falling edge
of each clock 2 (CL2) pulse.
Level Shifter
Data Shifter
The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.
The data shifter shifts the destinations of display
data output, when necessary.
Latch Circuit 2
Test Circuit
160-bit latch circuit 2 latches data input from latch
circuit I, and outputs the latched data to the level
shifter, both at the falling edge of each clock 1
(CLl) pulse.
The test circuit divides the external clock pulses
and generates test signals (TEST! and TEST2).
Block Diagram
Y1-Y160
V1-V4
LCD drive circuit
M------~
VLCD~
~
GND~
Vee
CL1
Latch circuit
~
DO-D7
SHL--------~----~~----~------~S~h~ift~ffi~g~is~te~r~----~~--~~--~--~
CL2-------------+----r--------------------+--~
TEST1
TEST2
HITACHI
Hitachi America, ltd.' Hitachi Plaza • 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
921
HD66110T
Comparison of the HD661l0T with the HD66107T
Item
HD66110T
Common LCD drive circuits
Not provided
160
Column LCD drive circuits
160
1600r 80
LCD drive voltage range
28 to 40 V
14to 37 V
Speed
12MHz
8 MHz
Clock hold time (tHcd definition
From the falling edge of CL 1 to
the rising edge of CL2 (figure 1)
From the falling edge of CL 1 to
the falling edge of Cl2 (figure 1)
Test pin level at normal operation
Vcc
Provided
GND
Display off function
TCP shape
Can be thin
Cannot be thin
CL1
~
i,
;:
\-
v
v
v==-
mfih ~~~~
vcc~:~
:
:
:
LCD panel cI 64Ck 480 dots;
1/480 duly 'Yd.
:
DIS
~
iii
>,
M
eL
eLl
v.
HD66110T
I\- m :d
~~
V"'~ ~
:
~
."""
If;:
:
eL
CL
HD66110T
I-
V3
v
~h
Q
Vl
r::=:
""""
DIS
II
Notes:
1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1120 bias, R1 and R2 must be 3 kQ and 48 kQ, respectively. That
is, R1/(4· R1 + R2) should be 1120.
2. To stabilize the power supply, place two O.1-I!F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the VLCD and GND pins.
3. The load must be less than 30 pF between the EI/O~ and EI/01 conn~tions of
HD66110Ts.
HITACHI
926
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66110T
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Note
Power supply voltage for logic circuits
Vcc
-0.3 to +7.0
V
1,5
Power supply voltage for LCD drive circuits
VlCD
-0.3 to +42
V
1,2,5
Input voltage 1
VT1
-0.3 to Vcc + 0.3
V
1,3
1,4
Input voltage 2
VT2
-0.3 to VlCD + 0.3
V
Operating temperature
To~r
-20 to +75
°C
Storage temperature
TSIII
-40 to +125
°C
Notes:
1. The reference point is GND (0 V).
2. Indicates the voltage between GND and VlCD'
3. Applies to input pins for logic circuits, that is, control signal pins.
4. Applies to input pins for LCD drive level voltages, that is, V1-V4 pins.
5. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.
Electrical Characteristics
DC Characteristics (Vcc
=5 V ± 10%, V LCD -
=28 to 40 V, and Ta = -20 to +7SoC, unless
GND
otherwise noted.)
Item
Symbol
Pins
Input high voltage
VIH
Input low voltage
VIL
1
Output high voltage
Vcc-O.4
VOH
2
Output low voltage
VOL
2
Vi-Yj on resistance
RON
3
Input leakage current 1
11L1
Input leakage current 2
IIL2
4
Min.
Condition
Max.
Unit
0.8 x VCC
VCC
V
0
0.2 x Vee
V
V
IOH= -0.4 mA
0.4
V
IOl = 0.4 mA
3.0
Note
kn
ION = 150 jJ.A
-5.0
5.0
IlA
VIN = Vee to GND
-100
100
IlA
VIN = VLCD to GND
mA
fCl2 = 12 MHz
fCL1 = 28 kHz
2
Current consumption 1
Icc
5.0
Current consumption 2
ILCD
3.0
mA
Same as above
2
Current consumption 3
1ST
0.7
mA
Same as above
2,3
Pins and notes on next page.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
927
HD66110T
Pins:
1. CL1, CL2, M, SHL, BS, EI/o1, EI/02,
V1 and V3 should be near VlCD level,
and V2 and V4 should be near GNO
level (figure 7). All voltage must be
within flV. flV is the range within
which RON, the LCO drive circuits'
output impedance, is stable. Note that
fl V depends on power supply voltage
VlCD-GNO (figure 8).
""DlSP; TESTf, ~, 0 0-07
2. "EOO1,"EIi02
3. Y'-Y'60, V1-V4
4. V1-V4
Notes:
1. Indicates the resistance between one
pin from Y'-Y'60 and another pin from
V1-V4 when load current is applied to
the Y pin; defined under the following
conditions.
GNO)}
2. Input and output current is excluded.
When a CMOS input is floating,
excess current flows from the power
supply through the input circuit. To
avoid this, V1H and V1L must be held to
Vcc and GNO levels, respectively.
GNO)}
3. Applies to standby mode.
VlCO - GNO = 40 V
= VlCD - {1/20(VlCD V2, V4 = VlCD + {1/20(VlCD V1, V3
~----~==·~···~··~··~V1VLCD
tJ.V
•••• V3
tJ.V
•••••••••••- V4
=
...=..=
...=..=
...~V~2GND
~--~~.=
..
Figure 7 Relation between Driver Output Waveform and Level Voltages
tJ.V (V)
6. 21···················,········7.1
4.0 I-·············~Wh
28
Level voltage rang«
40
VLCD-GND (V)
Figure 8 Relation between VLCD - GND and tJ.V
HITACHI
928
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane,
C~
94005-1819· (415) 589-8300
HD66110T
AC Cbaracteristics(Vcc = 5V± 10%, VLCD-GND = 28 to 40 V, and T. =-20 to +75°C, unless
otherwise noted.)
Item
Symbol
Pins
Clock cycle time
CL2
83
ns
CL2
20
ns
CL2
20
ns
Clock high-level width 2
tcvc
tcwH2
tcWl2
tcWH1
CL1
50
ns
Clock setup time
tSCL
CL1, CL2
100
ns
Clock hold time
100
Clock high-level width 1
Clock low-level width
Min.
tHCL
CL1, CL2
Clock rise time
tr
CL1, CL2
Clock fall time
tf
CL1, CL2
tos
toH
tcM
0 0-07 , CL2
20
0 0-0 7, CL2
20
Data setup time
Data hold time
M phase difference time
Note:
M,CL1
Max.
Unit
ns
20
20
ns
ns
ns
ns
300
ns
The load must be less than 30 pF between the'EJ702 and E70i connections of HD6611 OTs.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
929
HD66110T
tr
tCWH2
tf
tCWL2
tCYC
CL2
tOS
tOH
O.BVcc
00-07
0.2Vcc
CWH1
CL1
CL2
O.BVcc
M
0.2Vcc
tCM
Figure 9 LCD Controller Interface Timing
HITACHI
930
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66204
(Dot Matrix Liquid Crystal Graphic Display
Column Driver with 'SO-Channel Outputs)
Description
Features
The HD66204F/HD66204FL/HD66204 TF/HD
66204TFL, the column driver for a large liquid
crystal graphic display, features as many as 80
LCD outputs powered by 80 internal LCD drive
circuits. This device latches 4-bit parallel data
sent from an LCD controller, and generates LCD
drive signals. In standby mode provided by its
internal standby function, only one drive circuit
operates, lowering power dissipation. The
HD66204 has a complete line-up: the HD66204F,
a standard device powered by 5 V ± 10%; the
HD66204FL, a 2.7-5.5 V, low power dissipation
device suitable for battery-driven portable
equipment such as "notebook" personal computers
and palm-top personal computers; and the
HD66204TF and HD66204TFL, thin package
devices powered by 5 V ± 10% and 2.7-5.5 V,
respectively.
•
•
•
•
•
•
Duty cycle: 1/64 to 1/240
High voltage
- LCD drive: 10-28 V
High clock speed
- 8 MHz max under 5-V operation
(HD66204F/HD66204TF)
- 4 MHz max under 3-V operatioJ.l
(HD66204FL/HD66204TFL)
Display off function
Internal automatic chip enable signal generator
Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD66850
Ordering Information
Type No.
Voltage Range
Package
HD66204F
5 V± 10%
FP-100 (flat package)
HD66204TF
5 V± 10%
TFP-100 (thin flat package)
HD66204FL
2.7-5.5 V
FP-100 (fiat package)
HD66204TFL
2.7-5.5 V
TFP-100 (thin flat package)
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
931
HD66204
Pin Arrangement
Y51
Y52
Y53
Y54
Y55
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y15
Y67
Y14
Y68
Y69
Y13
Y12
Y11
Y70
Y71
Y10
Y72
Y73
Y9
Y8
Y74
Y7
Y6
Y75
Y76
Y77
Y78
Y79
Y80
Y5
Y4
Y3
Y2
Y1
Top view
HITACHI
932
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66204
Pin Description
Symbol
Pin No.
Pin Name
Input/Output
Classification
Vee
40
Vee
Power supply
GNO
38
GNO
Power supply
VEE
35
VEE
Vl
32
V1
Input
Power supply
V3
33
V3
Input
Power supply
V4
34
V4
Input
Power supply
CL1
37
Clock 1
Input
Control signal
CL2
49
Clock 2
Input
Control signai
M
36
M
Input
Control signal
0 0-0 3
48-45
Data O-data 3
Input
Control signal
SHL
41
Shift left
Input
Control signal
Power supply
E
31
Enable
Input
Control signal
CAR
50
Carry
Output
Control signal
OISPOFF
39
Display off
Input
Control signal
Y1-Yeo
51-100, 1-30
Y1-Y80
Output
LCD drive output
NC
42,43,44
No connection
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
933
HD66204
Pin Functions
Power Supply
Vee, VEE' GND: Vec-GND supplies power to
the internal logic circuits. Vcc-VEE supplies
power to the LCD drive circuits.
VI, V3, V4: Supply different levels of power to
drive the LCD. VI and VEE are selected levels,
and V3 and V4 are non-selected levels. See figure
l.
Do-D3: Input display data. High-voltage level of
data corresponds to a selected level and turns an
LCD pixel on, and low-voltage level data
corresponds to a non-selected level and turns an
LCD pixel off.
SHL: Shifts the destinations of display data
output. See figure 2.
E: A low E enables the chip, and a high E disables
the chip.
CAR: Outputs the E signal to the next HD66204 if
Control Signal
HD66204s are connected in cascade.
CLI: Inputs display data latch pulses for the line
data latch circuit. The line data latch circuit
latches display data input from the 4-bit latch
circuit, and outputs LCD drive signals
corresponding to the latched data, both at the
falling edge of each CLl pulse.
DISPOFF: A low DISP sets LCD drive outputs
Y1-Y80 to VI level.
CL2: Inputs display data latch pulses for the 4-bit
latch circuit. The 4-bit latch circuit latches display
data input via Do-D3 at the falling edge of each
CL2pulse.
LCD Drive Output
Y1-YSO : Each Y outputs one of the four voltage
levels VI, V3, V4, or VEE, depending on a
combination of the M signal and display data
levels. See figure 3.
NC: Must be open.
M: Changes LCD drive outputs to AC.
V1
V3
V4
VEE
Figure I Different Power Supply Voltage Levels for LCD Drive Circuits
HITACHI
934
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66204
(,)"'"11)
COl'com 0
>:>:>: >:>:>:>: ~
SHL
:::::::::::~
. . . .,.", . .----...........
;;:;r
= low
(,)"'"11) COl'com 0
1'1' I ' 1'1' I ' I ' co
>->->- >->->->- >-
SHL = higt
:::::::::::~
&!03 ......1-st--2-n-d-· ••••••••••
Last
Figure 2 Selection of Destinations of Display Data Output
M~
lOr
D~
Y output leve
1
~E~rV:rvtrv:1
Figure 3 Selection of LCD Drive Output Level
HITACHI
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
935
HD66204
Block Functions
Level Shifter
LCD Drive Circuit
The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.
Controller: The controller generates the latch
signal at the falling edge of each CL2 pulse for the
4-bit latch circuit.
LCD Drive Circuit
The 80-bit LCD drive circuit generates four
voltage levels VI, V3, V4, and VEE, for driving
an LCD panel. One of the four levels is output to
the corresponding Y pin, depending on a
combination of the M signal and the data in the
line data latch circuit.
4-Bit Latch Circuit
The 4-bit latch circuit latches 4-bit parallel data
input via the Do to D3 pins at the timing generated
by the control circuit.
Line Data Latch Circuit
The 80-bit line data latch circuit latches data input
from the 4-bit latch circuit, and outputs the latched
data to the level shifter, both at the falling edge of
each clock 1 (eLl) pulse.
Block Diagram
Y1-Y8C
DmpOFF --------~--~r--~----~~~~~~~~----~--I
CL1----------~>~L--~~------------------~~--~
SHL------------~
CL2------------~
Controller
-----------------------J
E----------~>·L-----__
CAR~------------------------------------------------~
HITACHI
936
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66204
Comparison of the HD66204 with the HD61104
Item
HD66204
HD61104
Clock speed
8.0 MHz max.
3.5 MHz max.
Display off function
Provided
Not provided
LCD drive voltage range
10-28 V
10-26 V
Relation between SHL and
LCD output destinations
See figure 4
See figure 4
Relation between LCD output
levels, M, and data
See figure 5
See figure 5
LCD drive V pins
V1,V3, V4
(V2 level is the same as VEE level)
V1,V2,V3,V4
SHL = low
SHL
=low
2nd
1st
SHL .. high
HD61104
HD66204
Note the exact reverse relation for the two devices.
Figure 4 Relation between SHL and LCD Output Destinations for the HD66204 and HD61104
M...Jr--:;-1-"L--.!OL.Jr
M~r-~1~~__~o~.Jr
D~
D~
HD66204
HD61104
Figure 5 Relation between LCD Output Levels, M, and Data for the HD66204 and HD61104
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
\
937
HD66204
Operation Timing
i
~
I
Line
>
I.
I
I
CL2
Data 0
Data 3
~
I
1
2
._••_••_•.
~
3
19 201
CAR
(No.1)
~
I
I
I
,""""",.1 ~ _.._. :xxtx=
=tx=x=x=
.-.._. _. ---.
J.J..fAi i i
=tx=x=x=
._. . . _. =x=x:rx= . . _. =x=x±:x=
Jt
i
i f1-I
CL1
21
J
i
I
HD66204 no. 1 latches dat
I
t-
>1
i
I
•
i
!
CAR
(No.2)
CAR
(No.3)
CAR
(No. n)
~
I
!
~i
:
>1
j
.~
II
• •1
HD66204 no. n
i
i
~~~
=:)
I
t-
I
•
HD66204 no. 3
latches data
I
Y1-Y8C
I
>1
•
HD66204 no. 2
~~~
i
rIi
,I
r:::=
I
i
I
i
HITACHI
938
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66204
Application Example
_.
CA.
...... }oegeoo
~I
>:
HDee204
DISl'OPF
D0-D3
M
Clf
Cl.
(0)
V.I-----.
V.=SrIl.7TEi~:;;:~~~~---,
V3-
\-
Ie=:::CA.
LCD panel
0'
640c 240 dolS;
11240 duty cycle
-
I
GND Va!
Notes:
R1
Rt
R2
Rt
A1
-=--=-
VEE
1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kil and 33 kil, respectively. That
is, R1/(4· R1 + R2) should be 1/15.
2. To stabilize the power supply, place two O.1-J.1F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
939
HD66204
Absolute Maximum Ratings
Item
Power supply voltage for logic circuits
Symbol
Rating
Unit
Vee
-0.3 to +7.0
V
Note
Power supply voltage for LCD drive circuits
Vee - 30.0 to Vee + 0.3 V
Input voltage 1
-0.3 to Vee + 0.3
V
1,2
Input voltage 2
Vee - 0.3 to Vee + 0.3
V
1,3
Operating temperature
-20 to +75
Storage temperature
-55 to +125
Notes:
1. The reference point is GNO (0 V).
2. Applies to pins CL 1, CL2, M, SHL, E, 0 0-03 , OISPOFF.
3. Applies to pins V1, V3, and V4.
4. H the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.
Electrical Characteristics
DC Characteristics for the HD66204F/HD66204TF (Vee
to 28 V, and Ta =-20 to +7SoC, unless otherwise noted.)
Item
Symbol
Input high voltage
VIH
Pins
Min.
=S V ± 10%, GND =0 V, Vee -
Typ. Max.
Unit Condition
0.7x Vee
V
0.3 x '¥ee V
Input low voltage
Vil
1
0
Output high voltage
VOH
2
Vee- 0.4
Output low voltage-
V
IOH=-0.4 mA
IOl
2
0.4
V
RON
3
4.0
kn
ION .. 100 j.LA
Input leakage current 1
11L1
-1.0
1.0
j.LA
VIN
Input leakage current 2
IIl2
-25
Current consumption 1
IGND
lEE
Current consumption 3
1ST
150
Note
=0.4 mA
VOL
Current consumption 2
=~O
V
Vi-Vj on resistance
4
VEE
= Vee to GNO
25
j.LA
VIN .. Vee to Vee
3.0
mA
fel2 .. 8.0 MHz
tel' =20 kHz
Vee - VEE =28 V
500
j.LA
Same as above
2
200
j.LA
Same as above
2,3
2
Pins and notes on next page.
HITACHI
940
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Paint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD66204
DC Characteristics for the HD66204FLIHD66204TFL (Vee
10 to 28 V, and Ta -20 to +75°C, unless otherwise noted.)
=
Item
Symbol
Input high voltage
Pins
=2.7 to 5.5 V, GND =0 V, Vee - VEE =
Min.
Max.
Unit
V
V1H
0.7 x Vcc
Vcc
Input low voltage
VIL
0
0.3 x Vcc V
Output high voltage
VOH
Output low voltage
VOL
Vi-Yj on resistance
RoN
Condition
V
IOH=-o.4 mA
2
0.4
V
IOL·O.4mA
3
4.0
k.Q
ION = 100 J.LA
2
Vcc- 0.4
Note
Input leakage current 1
11L1
1
-1.0
1.0
IIL2
4
-25
25
J.LA
J.LA
V1N - Vcc to GND
Input leakage current 2
Current consumption 1
IGND
1.0
mA
fCL2 =4.0 MHz
fCl1 - 16.8 kHz
fM .. 35 Hz
Vcc" 3.0 V
Vce- VEE .. 28 V
Checker-board
pattern
2
Current consumption 2
lEE
500
2
1ST
J.LA
J.LA
Same as above
50
Same as above
2,3
Current consumption 3
Pins:
V1N = Vcc to VEE
1. CL 1, CL2, M, SHL, E, Do-D3' DISPOFF
2. CAR
3. Y1-YSO, V1, V3, V4
4. V1, V3, V4
Notes:
1. Indicates the resistance between one pin from Y1-YSO and another pin from V1, V3, V4, and
VEE' when load current is applied to the Y pin; defined under the following conditions.
Vcc-GND =28 V
V1, V3 ... Vee - {211 O(Vcc - VEE)}
V4 .. VEE + {211 O(Vee - VEE)}
V1 and V3 should be near Vec level, and V4 should be near VEE level (figure 6). All voltage
must be within tN. llV is the range within which RON, the LCD drive circuits' output
impedance, is stable. Note that llV depends on power supply voltage Vee-VEE (figure 7).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows
from the power supply through the input circuit. To avoid this, V1H and V1L must be held to Vee
and GND levels, respectively.
3. Applies to standby mode.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
941
HD66204
Vee
V1
IN
•••••. V3
•••••••••••••• V4
IN
-L--~~---------VEE
Figure a ({elatiOJi between Driver Output Waveform and Level Voltages
IN (V)
2.0
•••••••.
Level voltage rang.
28
Vee-VEE (V)
Figure 7 Relation between Vcc - VEE and t1V
HITACHI
942
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD66204
AC Characteristics for the HD66204F/HD66204TF (Vee =S V ± 10%, GND
+7So C, unless otherwise noted.)
=0 V, and Ta =-20 to
Max.
Symbol
Pins
Min.
Clock cycle time
tevc
CL2
125
ns
Clock high-level width 1
teWH
CL1. CL2
45
ns
Clock low-level width
tCWL
CL2
45
ns
Clock setup time
tSCL
CL1. CL2
80
ns
Clock hold time
tHcL
CL1. CL2
80
Clock rise time
tr
CL1. CL2
Clock fall time
Item
tf
CL1. CL2
Data setup time
tos
Do-D3. CL2
Dala hold lime
IOH
Enable (E) selup lime
tEsu
Carry (CAR) output delay time
Unit
ns
Note 1
Note 1
ns
ns
20
ns
Do-D3. CL2
20
ns
E.CL2
30
ns
tCAR
CAR. CL2
80
ns
M phase difference time
tCM
M. CL2
300
ns
CL 1 cycle time
tcu
CL1
AC Characteristics for the HD66204FL/HD66204TFL (Vee
to +7SoC, unless otherwise noted.)
=2.7 to S.SV, GND =0 V, and Ta =-20
Max.
Symbol
Pins
Min.
tcve
CL2
250
ns
Clock high-level width 1
Unit
ICWH
CL1. CL2
95
ns
Clock low-level width
teWL
CL2
95
ns
Clock setup time
tSCL
CL1. CL2
80
ns
80
Clock hold time
tHCL
CL1. CL2
Clock rise time
tr
CL1. CL2
Clock fall time·
ns
Nole 1
tf
CL1. CL2
tos
Do-D3. CL2
50
Data hold time
tOH
Do-D3. CL2
50
ns
65
ns
ns
Enable (E) selup time
tEsu
E. CL2
Carry (CAR) oulput delay lime
teAR
CAR. CL2
155
ns
300
ns
ICM
M. CL2
CL 1 cycle lime
Icu
CL1
Notes:
Note
Nole 1
~ata setup time
M phase difference time
2
ns
Icvc x 50
Clock cycle time
Item
Note
Icvc x 50
2
ns
1. t r• tf < (Icve - tewH - tewdl2 and t r• If ~ 50 ns
2. The load circuit shown in figure 8 is connected.
HITACHI
Hitachi America. Ltd:· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
943
HD66204
Test poinl
O~--...,
±30 pF
Figure 8 Load Circuit
tr
tCWH
tf
tCYC
tCWL
CL2
tOS
tDH
0.7Vcc
00-03
0.3Vcc
tCWH
tCL1
CL1
CL2
CAR
E
14--......;~
M
tCM
0.7Vcc
0.3Vcc
Figure 9 LCD Controller Interface Timing
HITACHI
944
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66205
(Dot Matrix Liquid Crystal Graphic Display
Column Driver with 80-Channel Outputs)
Description
Features
The HD66205F/HD66205FL/HD66205TF/HD
66205TFL/HD66205T/HD66205TL, the row LCD
driver, features low output impedance and as many
as 80 LCD outputs powered by 80 internal LCD
drive circuits, and can drive a large liquid crystal
graphic display. Because this device is fabricated
by the CMOS process, it is suitable for batterydriven portable equipment, which fully utilizes the
low power dissipation of liquid crystal elements.
The HD66205 has a complete line-up: the
HD66205F, a standard device powered by 5 V ±
10%; the HD66205FL, a 2.7-5.5 V, low power
dissipation device; the HD66205TF and
HD66205TFL, thin film package devices each
powered by 5 V ± 10% and 2.7-5.5 V; and the
HD66205T and HD66205TL, tape carrier package
(TCP) devices powered by 5 V ± 10% and 2.7-5.5
. V, respectively.
•
•
Duty cycle: 1/64 to 1/240
High voltage
- LCD drive: 10-28 V
• Display off function
• Internal 80-bit shift register
• Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LVIC series: HD66840, HD66841
- CLINE: HD66850
Ordering Information
Type No.
Voltage Range
Package
HD66205F
5 V± 10%
Fp·100 (flat package)
HD66205FL
2.7-5.5 V
FP-100 (flat package)
HD66205TF
5 V± 10%
TFP-100 (thin flat package)
HD66205TFL
2.7-5.5 V
TFp·100 (thin flat package)
HD66205T
5 V± 10%
TCp·92 (tape carrier package)
HD66205TL
2.7-5.5 V
TCp·92 (tape carrier package)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005·1819. (415) 589·8300
945
HD66205
Pin Arrangement
X30
X29
X28
X27
X26
X25
X24
X23
X22
X21
X20
X19
X18
X17
X16
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X51
X52
X53
X54
X55
X56
X57
X58
X59
X60
X61
X62
X63
X64
X65
X66
X67
X68
X69
X70
X71
X72
X73
X74
X75
X76
X77
X78
X79
X80
000
WLO(O ....
O
..JO cO 0
zoz w » > z
Oz·
>
Z
Z
Top view
HITACHI
946
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66205
Pin Description
Classification
Pin No.
Vee
40
Vee
Power supply
GND
42
GND
Power supply
VEE
V1
34
37
VEE
V1
Input
Power supply
V5
35
V5
Input
Power supply
V6
VB
Input
Power supply
CL
36
46
Clock
Input
Control signal
M
44
M
Input
Control signal
01
48
32
Data in
Input
Control signal
Data out
Output
Control signal
SHL
41
Shift left
Input
Control signal
DISPOFF
39
51-100, 1-30
Display off
Input
Control signal
X1-X80
Output
LCD drive output
DO
X1-Xao
NC
31,33,38,43,
45,47,49,50
Pin Name
Input/Output
Symbol
Power supply
No connection
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
947
HD66205
Pin Functions
DO: Outputs display data. DO of the last
HD66205 must be open, and those of the other
HD66205s must be connected to DI of the next
HD66205.
Power Supply
Vee, VEE' GND: Vec-GND·suppUes power to the
internal logic circuits. Vec-VEE supplies power to
the LCD drive circuits.
VI, V5, V6: Supply different levels of power to
drive the LCD. VI and VEE are selected levels,
and V5 and V6 are non-selected levels. See figure
1.
Control Signal
CL: Inputs data shift clock pulses for the shift
register. At the falling edge of each CL pulse, the
shift register shifts display data input via the DI
pin.
SHL: Selects the data shiftt direction for the shift
register. See figure 2.
DISPOFF: A low DISP sets LCD drive outputs
X1-XSO to VI level.
LCD Drive Output
XI-XSO: Each X outputs one of the four voltage
levels VI, V5, V6, or VEE' depending on a
combination of the M signal and display data
levels. See figure 3.
Other
NC: Must be open.
M: Changes LCD drive outputs to AC.
01: Inputs display data. DI of the first HD66205
must be connected to an LCD controller, and those
of the other HD66205s must be connected to DI of
the previous HD66205.
V1
V6
V5
VEE
Figure I Different Power Supply Voltage Levels for LCD Drive Circuits
HITACHI
948
Hitachi America, Ltd. -Hitachi Plaza - 2000 Sierra Po.int Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD66205
SHL level
Common signa
scan direction
Data shift directior
Low
DI~SR1
High
DI
~
SR2
~SR80
~ SR80~SR79~
X1
~
X80
X80~X1
SR1
Figure 2 Selection of Display Data Shift Direction
M--.J
1
0
I
D~
X output leve
rvrrvtrvE~rvtl
Figure 3 Selection of LCD Drive Output Level
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA'94005-1819· (415) 589-8300
949
HD66205
Block Functions
Shift Register
LCD Drive Circuit
The 80-bit shift register shifts data input via the DI
pin by one bit, and the one bit of shifted-out data is
output from the DO pin. Both actions occur
simultaneously at the falling edge of each shift
clock (CL) pulse
The 80-bit LCD drive circuit generates four
voltage levels VI, V5, V6, and VEE, for driving an
LCD panel. One of the four levels is output to the
corresponding Y pin, depending on a combination
of the M signal and the data in the shift register
Level Shifter
The level shifter changes 5-V signals into highvoltage signals for the LCD drive circuit.
Block Diagram
X1-X80
DISPOFF
CL
Shift register
01
SHL
DO~----------------------------------------------~
HITACHI
950
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66205
Comparison of the HD6620S with the HD6110S
Item
HD66205
HD61105
Display off function
Provided
Not provided
LCD drive voltage range
10-28 V
10-26 V
Shift clock phase selection function
Not provided
Provided (FCS pin)
Relation between SHL and
LCD output destinations
See figure 4
See figure 4
Relation between LCD output
levels, M, and data
See figure 5
See figure 5
LCD drive V pins
Vl, V5, V6
(V2 level is the same as VEE level)
Vl,V2,V5,V6
SHLlevel
Data shift directior
Low
D1~SRl
~
~SR80
High
01 ~ SR80~SR79~ SRl
SR2
Common signa
scan direction
Xl
~
X80
X80~Xl
HD66205
Common signa
scan direction
SHLlevel
Data shift directior
Low
01 ~ SR80~SR79~ SRl
X80~Xl
High
DI~SRl
Xl
~SR2 ~SR80
~
X80
HD61105
Note the exact reverse relation for the two devices.
Figure 4 Relation between SHL and LCD Output Destinations for the HD6620S and HD6110S
M...J
1
0
r
M-1
D~
X output leve ~V1 ..~V5 ..!yE~~V6"1
1
0
r
D~
X output leve ~V2.~V6.I..V1"I.. V5.1
HD66205
HD61105
Figure 5 Relation between LCD Output Levels, M, and Data for the HD66205 and HD61105
HITACHI
Hitachi America, ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
951
HD66205
Operation Timing
Figure 6 shows the operation timing for the Application Example.
~~~
~~~
··
'.
.
...
.
~~ '~~~
~~d?r d
..
~~. ~~.~
.
..
..
...
.
.
..
.
: C')
:
:
:
:
.
~~~·
·
E
~
:
:
··
..
~~~
.. .
..
:
11):
..
..
.
:
.
;; ;
~il ~ ~> ~~ ;~ ~ ~ .f ~ ~
~d4~>;
···
:::E
..
...
.
~d~>l>
~i
CD
,
.
.
.
.
.
.
.
.
.
.
..
.. .
is
d;
N
~
/O""':::E:::E
0
. . ._--;::...--'.
!!!
ee
~§~
~
~
,x(~)
8
...... ·····0
~::-
x
x
/
SOZ990H
...
...
...
O~
N
O~
~
0
0:::E
~..... 8
0
:;
,.~(Z)
0
~
Q)
~
-
x
/
0
~
C\I
0
0;
~
~
"",:::E:::E
8_
8 ·····8
--
- -
~
~
SOZ990H
~
x
/
(&) SOZ990H
Figure 6 Relation between SHL and LCD Output Destinations
HITACHI
952
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD66205
Application Example
MgU.
Mg63.
Mg638
f~
;:
"".
DI8POFr
0C>-D3
M
HO.....
CL2
CL.
(e)
"".
f.,....du........
LCD panel of MCk 240 dotI;
~ ~~
M
0
~,
;::
HD662Or$
(1)
Ii \-
iH
.............. '-........ ............. ~
i X'-X8C i Voc lX'-X~r
HO.....
(')
00 _::
~~
HOO....
CL2
elf
~~I-+I-Hf-H
1!~3~
Voc':"H..
~.~
DC
(3)
R1
GNOVoc
Notes:
DI8PO"lImm
00-03
s0g3
leg2
leg1
Rt
R2
R1
R1
VEE
1. The resistances of R1 and R2 depend on the type of the LCD panel used.. For example,
for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kil and 33 kil, respectively. That
is, R1/(4'. R1 + R2) should be 1115.
2. To stabilize the power supply, place two O.l-~F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.
HITACHI
Hitachi America, Ltd,· Hitachi Plaza· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819· (415) 589-8300
953
HD66205.
Absolute MaximumRat~ngs
Item
Symbol
Rating
Unit
Power supply voltage for logic circuits
Vee
-0.3 to +7.0
V
Note
Power supply voltage for LCO drive circuits
Vee - 30.0 to Vee + 0.3 V
Input voltage 1
-0.3 to Vee + 0.3
V
1,2
Input voltage 2
VEE - 0.3 to Vee + 0.3
V
1,3
Operating temperature
-20 to +75
°C
-55 to +125
°C
Storage temperature
Notes:
T s1g
4
1. The reference point is GNO (0 V).
~=-o-==
2. Applies to pins CL, M, SHL, 01, OISPOFF.
3. Applies to pins V1, V5, and VS.
4. -40 to + 125°C for TCP devices.
5. H the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.
Electrical Characteristics
DC Characteristics for the HD6620SF/HD6620STF/HD6620ST (Vee = 5 V ± 10%, GND = 0 V, Vee
- VEE = 10 to 28 V, and Ta= -20 to + 7SoC, unless otherwise noted.)
Item
Symbol
Input high voltage
VIH
Input low voltage
Vil
Output high voltage
Pins
Vee
0
0.3 x Vee V
Vee- O.4
2
VOL
2
Vi-Vj on resistance
RoN
3
Input leakage current 1
i ll1
Input leakage current 2
IIl2
Current consumption 2
lEE
4
V
iOH =-0.4 mA
0.4
V
IOl'" 0.4 mA
JJ.A
2.0
kn
ION = 100
-1.0
1.0
-25
25
100
JJ.A
JJ.A
JJ.A
VIN = Vee to GNO
500
J.1A
150
Note
V
0,7 x Vee
VOH
IGND
Unit Condition
1
Output low voltage
Current consumption 1
Typ. Max.
Min.
VIN = Vee to VEE
fel = 20 kHz
Vee -VEE =28V
2
Same as above
2
Pins and notes on next page.
HITACHI
954
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66205
DC Characteristics for the HD66204FL/HD66204TFL/HD66204TL (Vee
Vee - VEE = 10 to 28 V, and Ta = -20 to +75°C, unless otherwise noted.)
Item
Symbol
Input high voltage
VIH
Input low voltage
VIL
Output high voltage
VOH
Output low voltage
Max.
Unit
0.7xVee
Min.
Vee
V
1
0
0.3 x Vee V
2
Vee -O.4
Pins
IOH .-0.4 mA
IOL - 0.4 mA
VOL
2
0.4
V
RON
3
2.0
kn
Input leakage current 1
11L1
-1.0
1.0
~
-25
25
~
~
11L2
Current consumption 1
IGND
100
Current consumption 2
lee
250
Pins:
4
Condition
V
Vi-Vj on resistance
Input leakage current 2
=2.7 to 5.5 V, GND =0 V,
Note
VIN - Vee to GNO
fel" 16.8 kHz
f M .. 35 Hz
Vee=3.0V
Vee - Vee" 28 V
2
Same as above
2
1. CL, M, SHL, 01, OISPOFF
2.00
3. X,-Xao, V1, V5, V6
4. V1, V5, V6
Notes:
1. Indicates the resistance between one pin from X,-Xao and another pin from V1, V5, V6, and
Vee, when load current is applied to the X pin; defined under the following conditions.
Vee - Vee'" 28 V
V1, V6 '" Vee - {1/10(Vee - Vee)}
V5 .. Vee + {1/10(Vee - Vee)}
V1 and V6 should be near Vee level, and V5 should be near Vee level (figure 7). All voltage
must be within t.V. t.V is the range within which RON, the LCO drive circuits' output
impedance, is stable. Note that t.V depends on power supply voltage Vee-Vee (figure 8).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows
from the power supply through the input circuit. To avoid this, VIH and VIL must be held to Vee
and GNO levels, respectively.
3. Applies to standby mode.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
955
HD66205
Vee
V1
tN
V6
•••••••••••••• V5
IN
-i._--'-_'--_ _ _ _ _
VEE
Figure 7 Relation between Driver Output Waveform and Level Voltages
2.8 ••••.•.•••..•••••••.
IN (V)
1.0 ••••••••
10
Level voltage rangl
28
. Vee-VEE (V)
Figure 8 Relation between Vee - VEE and AV
HITACHI
956
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66205
AC Characteristics for the HD66205FIHD6620STFIHD66205T (Vee
Ta -20 to +75°C, unless otherwise noted.)
=
Hem
Symbol
Pins
Clock cycle time
=5 V ± 10%, GND =0 V, and
Min.
Max.
Unit
tcvc
CL
10
~s
Clock high-level width 1
tcWH
CL
50
ns
Clock low-level width
tcWL
tr
CL
1.0
Clock rise time
Clock fall time
CL
tf
CL
Data setup time
tos
DI,CL
100
Data hold time
100
tOH
DI,CL
Data output delay time
too
DO,CL
Data output hold time
tOHW
DO,CL
ns
'30
ns
ns
ns
100
=
Item
~s
30
3.0
AC Characteristics for the HD6620SFLIHD6620STFLlHD6620STL (Vee
and Ta -20 to +7SoC, unless otherwise noted.)
~s
ns
=2.7 to 5.5 V, GND =0 V,
Max.
Unit
Symbol
Pins
Min.
Clock cycle time
tcvc
CL
10
~s
Clock high-level width 1
tcwH
CL
80
ns
Clock low-level width
tcwL
CL
1.0
Clock rise time
t,
CL
30
ns
Clock fall time
tf
CL
30
ns
Data setup time
tos
DI,CL
100
Data hold time
tOH
DI,CL
100
Data output delay time
too
DO,CL
100
DO,CL
tOHW
1. The load circuit ~hown in figure 9 is connected.
test point
Note
~s
ns
ns
7.0
Data output hold time
Notes:
Note
~s
ns
Ol----l-,
;J;
30 pF
Figure 9 Load Circuit
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
957
HD66205
~
Cl
tCWl
tCWH
l..lI:
tOO
tOS
~
DI
tCYC
-K ....
~
O.7VCC-',
O.3Vec "' ....
~
O.7Vcc
O.3Vcc
~
\~
tOH
:K
tOHW
. DO
O.SVcc"l
O.2Vcc'2
~:
Figure 10 LCD Controller Interface Timing
HITACHI
958
Hitachi America, Ltd. o Hitachi Plaza 0 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 0 (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)(SO-Channel Column Driver in Micro-TCP)
Description
Features
The HD66214TIHD662141L, the column driver
for a large liquid crystal graphic display, features
as many as 80 LCD outputs powered by 80
internal LCD drive cin:uits. This device latches 4bit parallel data sent from an LCD controller, and
generates LCD drive signals. In standby mode
provided by its internal standby function, only one
drive circuit operates, lowering power dissipation.
The HD66214, packaged in an 8-mm-wide microtape carrier package (micro-TCP), enables a
compact LCD system with a narrower frame
(peripheral areas for LCD drivers) -about half as
large as that os an existing system. The HD66214
provides HD66214T, a standard device powered
by5 V ± 10%, andHD662141L, a low power
dissipation device powered by 2.7-5.5 V suitable
for battery-driven portable equipment such as
nOJebook personal computers and palm-top
personal computers.
• Duty cycle: 1/64 to 1/240
• High voltage
- LCD drive: 10-28 V
• High clock speed
- 8 MHz max under 5-V operation
(HD66214T)
- 4 MHz max under 3-V operation
(HD662441L)
• Display off function
• Internal automatic chip enable signal generator
• Various LCD controller interfaces
- LCTC series: HD63645, HD64645,
HD64646
- LYlC series: HD6684O, HD66841
- CLINE: HD66850
• 98-pinTCP
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
959
HD66214T/HD66214TL (Micro-TAB)
Pin Arrangement
~~ummY
V~~1
E
2
DO
3
D1
4
98
97
96
02
5
03
6
CL2
7
CL1
8
M
9
DISPOFF
CAR
Vee
SHL
GNO
VEE
V4
V3
V1
Y1
Y2
Y3
10
11
12
13
14
15
16
17
18
21
20
19
Y78
Y79
Y80
1
Dummy
J
Top view
HITACHI
·960
Hitachi America, Ltd. - Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
Pin Description
Symbol
Pin No.
Pin Name
Vee
Vee
CL2
1,12
14
15
18
17
16
8
7
M
GND
VEE
V1
V3
V4
Input/Output
Classification
Power supply
GND
Power supply
VEE
V1
V3
V4
Power supply
Input
Power supply
Input
Power supply
Input
Power supply
Input
Control signal
Input
Control signal
9
1
Clock 2
M
Input
Control signal
0 0-0 3
3-6
Data O-data 3
Input
Control signal
SHL
13
2
11
10
19-98
Shift left
Input
Control signal
Enable
Input
Control signal
Carry
Output
Control signal
Display off
Input
Control signal
Y1-Y80
Output
LCD drive output
Cl1
E
CAR
DISPOFF
Y1-Yao
Clock
HITACHI
Hitachi America,ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
961
HD66214T/HD66214TL (Micro-TAB)
Pin Functions
M: Changes LCD drive outputs to AC.
Power Supply
Do-D3: Input display data. High-voltage level of
data corresponds to a selected level and turns an
LCD pixel on, and low-voltage level data
corresponds to a non-selected level and turns an
LCD pixel off.
Vee, VEE' GND: Vcc-GND supplies power to the
internal logic circuits. Vee-VEE supplies power
to the LCD drive circuits.
VI, V3, V4: Supply different levels of power to
drive the LCD. VI and VEE are selected levels,
and V3 and V4 are non-selected levels. See figure
i.
SHL: Shifts the destinations of display data
output See figure 2.
E: A low E enables the chip, and a high E disables
the chip.
Control Signal
CAR: Outputs theE signal to the next HD66214 if
HD66214s are connected in cascade.
CLI: Inputs display data latch pulses for the line
data latch circuit.· The line data latch circuit
latches display data input from the 4-bit latch
circuit, and outputs LCD drive signals
corresponding to the latched data, both at the
falling edge of each CLl pulse.
LCD Drive Output
CL2: Inputs display data latch pulses f.or the 4-bit
latch circuit. The 4-bit latch circuit latches display
data input via Do-D3 at the falling edge of each
CL2pulse.
y 1-Y so: Each Y outputs one of the four voltage
levels VI, V3, V4, or VEE, depending On a
combination of the M signal and display data
levels. See figure 3.
DISPOFF: A low DISP sets LCD drive outputs
y l-Y 80 to VI level.
V1
V3
V4
VEE
Figure I Different Power Supply Voltage Levels for LCD Drive Circuits
HITACHI
962
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
C')VIt)
SHL
= low
SHL
= higt
co ..... co 0)
0
>:>:>: >:>:>:>: ~
>~~)!:~~>:~
:::::::::::~
I-r-=--------------:;g[
Figure 2 Selection of Destinations of Display Data Output
M~
1
lor
D~
Y output leve
bE~rV:rvtrv:1
Figure 3 Selection of LCD Drive Output Level
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
963
HD66214T/HD66214TL (Micro-TAB)
Block Functions
Level Shifter
Controller: The controller generates the latch
signal at the falling edge of each CL2 pulse for the
4-bit latch circuit.
The level shifter changes 5~V signals into highvoltage signals for the LCD drive circuit.
4-Bit Latch Circuit
The 4-bit latch circuit latches 4-bit parallel data
input via the DO to D3 pins at the timing generated
by the control circuit.
Line Data Latch Circuit
LCD Drive Circuit
. The 80-bit LCD drive circuit generates four
voltage levels VI, V3, V4, and VEE, for driving
an LCD panel. One of the four levels is output to
. the corresponding Y pin, depending on a
combination of L'te ~Y1 signal and the data in the
line data latch circuit.
The SO-bit line data latch circuit latches data input
from the 4-bit latch circuit, and outputs the latched
data to the level shifter, both at the falling edge of
each clock I (CLI) pulse.
Block Diagram
Y1-Y8C
DmpefF~----~--~r--~----~~~~~~----~--,
>
C
SHL------------~
CL2------------~
Controller
E
CAR~----------------------------------------------~
HITA.CHI
964
Hitachi America, Ltd. -Hitachi Plaza- 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
Ordering Information
lYpeNo.
Voltage Range
Outer Lead Pitch 1
Outer Lead Pitch 2
Device Length
HD66214TA1
5 V± 10%
0.15 mm
0.80 mm
3 sprocket holes
HD66214TA1L
2.7-6.5 V
0.15 mm
0.80 mm
3 sprocket holes
HD66214TA2
5V± 10%
0.18 mm
0.80 mm
3 sprocket holes
HD66214TA2L
2.7-6.5 V
0.18 mm
0.80 mm
3 sprocket holes
HD66214TA3
5 V± 10%
0.20mm
0.80 mm
3 sprocket holes
HD66214TA3L
2.7-6.5 V
0.20 mm
0.80 mm
3 sprocket holes
HD66214TA4
5 V± 10%
O.22mm
0.80mm
3 sprocket holes
HD66214TA4L
2.7-6.5 V
O.22mm
0.80 mm
3 sprocket holes
HD66214TAS
5 V± 10%
0.25 mm
0.80mm
3 sprocket holes
HD66214TASL
2.7-6.5 V
0.25 mm
0.80mm
3 sprocket holes
HD66214TA6
5V± 10%
0.20 mm
0.45 mm
3 sprocket holes
HD66214TA6L
2.7-6.5 V
0.20 mm
0.45 mm
3 sprocket holes
HD66214TA7
5V± 10%
0.22 mm
0.45mm
3 sprocket holes
HD66214TA7L
2.7-6.5 V
0.22 mm
0.45mm
3 sprocket holes
HD66214TA8
5 V± 10%
0.25 mm
0.55mm
3 sprocket holes
HD66214TA8L
2.7-6.5 V
0.25 mm
0.S5mm
3 sprocket holes
Notes:
1. Outer lead pitch 1 is for LCD drive output pins, and outer lead pitch 2 for the other pins.
2. Device length includes test pad areas.
3. Spacing between two sprocket holes is 4.75 mm.
4. Tape film is Upirex (a trademark of Ube Industries, Ltd.).
5. 35-mm·wide tape is used.
6. Leads are plated with Sn.
HITACHI
Hitachi America, Ltd. - Hitachi Plaza -2000 Sierra Point Pkwy. - Brisbane, CA 94005"1819 - (415) 589-8300
965
HD66214T/HD66214TL (Micro-TAB)
Comparison of the HD66214 with the HD61104
Item
HD66214
HD61104
Clock speed
8.0 MHz max.
3.5 MHz max.
Display off function
Provided
Not provided
LCD drive voltage range
10-28 V
10-26 V
Relation between SHL and
LCD output destinations
See figure 4
See figure 4
Relation between LCD output
See figure 5
See figure 5
LCD drive V pins
V1,V3, V4
(V2 level is the same as VEE level)
V1, V2, V3, V4
Storage temperature
-40 to 125°C
-55 to 125°C
Package
TCP (tape carrier package)
QFP (quad flat package)
lavals, .,,1, and data
SHL .. low
SHL .. low
1st
2nd
SHL
Last
= high
2nd
Last
SHL
1 st
= high
HD61104
HD66214
Note the exact reverse relation for the two devices.
Figure 4 Relation between SHL and LCD Output Destinations for the HD66214 and HD61104
HITACHI
966
Hitachi America, Ltd.' Hitachi Plaza '2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
M .....Jr---:.L--..J;0LJr
M ......J1-:;--"'L--.QO~..Jr
D~
D~
Y output leve
~E~~V4 .,l\,~V3 .,
Y output leve
~V1
.,.l3 .,l2.,l4 .,
HD61104
HD66214
Figure 5 Relation between LCD Output Levels, M, and Data for the HD66214 and HD61104
HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
967
HD66214T IHD66214 TL (Micro-TAB)
Operation Timing
I
.r
I
Line
~
I
---lruu1:- .._. __. ~ _. _. ~
I
CL2
I
1
2
3
19 201
=r=x=x== -_. _._. --,,--v-hr-- ._. -=x=::xrx=
=fx=x=x= -- =x=x:l:x= ---=x=x:l:x=
i
. Data 0
Dm. 3
k
CAR
(No.2)
CAR
(No.3)
CAR
(No. n)
I
-l1I
CAR
(No.1) ~
'
I
--1
i
i
i
I
~
:
CL1
I
21
i
i
i
I
HD66214 no. 1 latches dal
;;oj
-<
-J.
,
~I
,
!I
i
,
HD66214 no. 3
latches data
!I
i'
-<
I
Y1-Y8C ==:l
I
»I
~~~
I
i
i
-<~I
HD66214 no. n
I
r--
~
HD66214 no. 2
latches data
--;1'
rt..
I
I
I
r==
I
i
I
i
HITACHI
968
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
Application Example
-
... l-
e...
" ",
"",
~
DIIIPOYF
DO-
HD6621.
""
f-
HD66214
(2)
LCD panel of &t0l: 240 dolS;
1/240 duty cyde
a.
a.l
(8)
.!.
>-
Hl
"'"t"DF
CL
a.l
CA>
:::
i
~
sag1
~*
NN
eE
88
E1:1~
888
~'-X>r ~'-X>r
\
,--
Vee
~ ~\"
HD68205
11)
~ ~\"
DC ••
HD60205
(3)
HD&e214
el)
Hl
"'"t"DF
Cl.
CL 1
>-
W:~+t~H
V3
VIr-
;SrHL'--ijB~ ~~~~~~_=:!:lH
,;1:!!
DC
I
R1
GND Vee
Notes:
A1
R2
R1
R1
VEe
1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example,
for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kO and 33 kO, respectively. That
is, R1/(4· R1 + R2) should be 1115.
2. To stabilize the power supply, place two O.1-I1F capacitors near each LCD driver: one
between the Vee and GND pins, and the other between the Vee and VEE pins.
HITACHI
Hitachi America,ltd.· Hitachi Plaza· 2000 Sierra Point P~wy.• Brisbane, CA 94005-1819· (415) 589-8300
969
HD66214T/HD66214TL (Micro-TAB)
Absolute Maximum Ratings
Item
Power supply voltage for logic circuits
Symbol
Rating
Unit
Vee
-0.3 to +7.0
V
Note
Power supply voltage for LCD drive circuits
VEE
Vee - 30.0 to Vee + 0.3
V
Input voltage 1
VT1
-0.3 to Vee + 0.3
V
1.2
Input voltage 2
1.3
VT2
VEE - 0.3 to Vee + 0.3
V
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tsta
-40 to +125
°C
Notes:
1. The reference point is GNO (0 V).
2. Applies to pins CL 1. CL2. M. SHL. E. Do-Os. OISPOFF.
3. Applies to pins V1. V3. and V4.
4. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.
Electrical Characteristics
DC Characteristics for the HD66214T (Vee = 5 V ± 10%, GND = 0 V, Vee - VEE = 10 to 28 V, and
Ta = -20 to +75°C, unless otherwise noted.)
Typ. Max.
Unit Condition
Item
Symbol Pins
Min.
Input high voltage
V1H
0.7 x Vee
Vee
Input low voltage
V1L
0
0.3 x Vee V
Output high voltage
VOH
Output low voltage
2
Vee- O.4
Note
V
V
IOH =-0.4 rnA
VOL
2
0.4
V
IOL= 0.4 rnA
Vi-Vj on resistance
RON
3
4.0
kn
Input leakage current 1
11L1
-1.0
1.0
-25
25
I!A
I!A
3.0
rnA
= 100 I!A
VIN = Vee to GNO
V1N = Vee to VEE
feL2 = 8.0 MHz
feL1 = 20 kHz
Vee - VEE =28 V
500
IlA
Same as above
2
200
I!A
Same as above
2,3
Input leakage current 2
IIL2
Current consumption 1
IGND
Current consumption 2
lEE
Current consumption 3
1ST
4
150
ION
2
Pins and notes on next page.
HITACHI
970
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66214T/HD66214TL (Micro-TAB)
DC Characteristics for the HD66214TL (Vee = 2.7 to 5.5 V, GND = 0 V, Vee - VEE = 10 to 28 V,
and Ta = -20 to +75°C, unless otherwise noted.)
Item
Symbol
Input high voltage
VIH
Pins
Min.
Max.
'Unlt
0.7xVee
Vee
V
0.3 x Vee V
Input low voltage
VIL
1
o
Output high voltage
VOH
2
Vee -O.4
Output low voltage
VOL
2
0.4
Vi-Yj on resistance
RoN
3
4.0
Input leakage current 1
Condition
V
IOH"-O.4 mA
V
IOL" 0.4 mA
~
VIN = Vee to GNO
Note
IIL1
1
-1.0
1.0
Input leakage current 2
1112
4
-25
25
Current consumption 1
IGND
1.0
mA
feL2 = 4.0 MHz
feL1 = 16.8 kHz
fM =35 Hz
Vee =3.0V
Vee- VEE = 28 V
Checker-board
pattern
2
Current consumption 2
lEE
500
~
Same as above
2
50
~
Same as above
2, 3
Current consumption 31sT
Pins:
1. CL 1, CL2, M, SHL, E, 0 0-03 , OISPOFF
2. CAR
3. Y1-Y80 , V1, V3, V4
4. V1, V3, V4
Notes:
1. Indicates the resistance between one pin from Y1-YSO and another pin from V1, V3, V4, and
VEE, when load current is applied to the Y pin; defined under the foilowing conditions.
Vcc-GNO
V1, V3
=28 V
=Vee -
{2/1 O(Vee - VEE}}
V4 .. VEE + {2110(Vee - VEE}}
V1 and V3 should be near Vee level, and V4 should be near VEE level (figure 6). Ail voltage
must be within t.V. t.V is the range within which RON, the LCD drive circuits' output
impedance, is stable. Note that t.V depends on power supply voltage Vee-VEE (figure 7).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows
from the power supply through the input circuit. To avoid this, V1H and VIL must be held to Vee
and GNO levels, respectively.
3. Applies to standby mode.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
971
HD66214TIHD66214 TL.(Micro-TAB)
Vee
•••••••••• V1
AV
••••• ' V3
•••••••••••••• V4
AV
-Z.._-'--.l.._ _ _ _ _
VEE
Figure 6 Relation between Driver Output Waveform and Level Voltages
AV(V)
2.0
••••••••
Level voltage rangl
28
Vee-VEE (V)
Figure 7 Relation between Vee - VEE and AV
HITACHI
972
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD66214 T IHD66214 TL (Micro-TAB)
AC Characteristics for the HD66214T (Vee = 5 V ± 10%, GND = 0 V, and Ta = -20 to +75°C, unless
otherwise noted.)
Item
Max.
Symbol
Pins
Min.
Clock cycle time
tevc
CL2
125
ns
Clock high-level width 1
Unit
teWH
CL1, CL2
45
ns
Clock low-level width
teWl
CL2
45
ns
Clock setup time
ns
tscL
CL1, CL2
80
Clock hold time
lHcL
CL1, CL2
80
Clock rise time
tr
CL1, CL2
Clock fall time
tf
CL1, CL2
Data setup time
tos
0 0-03, CL2
Data hold time
Note
ns
Note 1
ns
Note 1
ns
20
ns
tOH
0 0-03, CL2
20
ns
Enable (E) setup time
tEsu
E, CL2
30
ns
Carry (CAR) output delay time
teAR
CAR, CL2
80
ns.
M phase difference time
teM
M,CL2
300
ns
CL 1 cycle time
teu
CL1
2
ns
tCYC x50
AC Characteristics for the HD66214TL (Vee = 2.7 to 5.5 V, GND = 0 V, and Ta = -20 to +75°C,
unless otherwise noted.)
Item
Max.
Symbol
Pins
Min.
Clock cycle time
tevc
CL2
250
ns
Clock high-level width 1
Unit
teWH
CL1, CL2
95
ns
Clock low-level width
tcwL
CL2
95
ns
Clock setup time
tSCL
CL1, CL2
80
ns
Clock hold time
tHCL
CL1, CL2
120
Clock rise time
tr
CL1, CL2
-
Clock fall time
ns
Note1
ns
Note1
ns
tf
CL1, CL2
Data setup time
tos
50
ns
Data hold time
50
ns
65
ns
tOH
00-03, CL2
0 0-03, CL2
Enable (E) setup time
tESU
E,CL2
Carry (CAR) output delay time
teAR
M phase difference time
CAR, CL2
155
ns
M,CL2
300
ns
teM
CL1
teu
1. tr, tf < (tcvc - tCWH - tcwdl2 and t r, tf S 50 ns
CL 1 cycle time
Notes:
tCYC x 50
Note
1
2
ns
2. The load circuit shown in figure 8 is connected.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
973
HD66214T/HD66214TL (Micro-TAB)
Test poinl 01-------.
i30 pF
Figure 8 Load Circuit
tr
tCWH
tf
tCWL
tCYC
CL2
lOS
tDH
0.7Vec
00-03
0.3Vec
tCWH
tCl1
CL1
Cl2
CAR
O.aVee
E
tCM
M
0.7Vec
0.3Vec
Figure 9 LCD Controller Interface Timing
HITACHI
974
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-II/E20----(Dot Matrix Liquid Crystal Display
Controller and Driver)
-PreliminaryDescription
Features
The LCD-II/E20 (HD66702) dot matrix liquid
crystal display controller and driver LSI displays
alphanumerics, kana characters, and symbols. It
drives a dot matrix liquid crystal display under 4bit or 8-bit microprocessor control. Since all the
functions required for dot matrix liquid crystal
display drive are internally provided on one chip, a
small system can be configured with this LSI.
•
A single LCD-II/E20 can display up to two lines,
each of 20 characters. The addition of driver LSI
HD44100s enables a maximum display of two
lines, each of 40 characters.
The LCD-II/E20 of 3-V power supply (whose
development is under consideration) is suitable for
any portable battery-driven apparatus requiring
low power dissipation.
•
•
•
•
•
•
•
Ordering Information
Operating
Voltage
lYpeNo.
Package
HCD66702
144-pin bare chip
4.5 to 5.5 V
HCD66702L
144-pin bare chip
2.7 to 3.3 V
•
•
•
5 x 7 and 5 x 10 dot matrix liquid crystal
display controller and driver
Internal display RAM of 80 x 8 bits (SO
characters max.)
Internal character generator ROM of 7200 bits:
160 character fonts of 5 X 7 dots
32 character fonts of 5 X 10 dots
Internal character generator RAM of 64 x 8 bits:
8 character fonts of 5 X 7 dots
4 character fonts of 5 X 10 dots
Internal liquid crystal display driver with 16
common signal drivers and 100 segment signal
drivers
Programmable duty cycles
- 1/8 for 1 line of 5 X 7 dots + cursor
- 1/11 for 1 line of 5 X 10 dots + cursor
- 1/16 for 2 lines of 5 X 7 dots + cursor
Maximum display characters
Wide range of instruction functions:
- Display clear, Cursor home, Display
On/Off, Cursor On/Off, Display character
blink, Cursor shift, Display shift
Wide range of power supply (Vcd: 4.5 to 5.5 V
(standard version), 2.7 to 3.3 V (low Vcc
version)
Internal automatic reset circuit after power on
(provided by standard version only)
Independent LCD drive voltage on the logic
power supply (Vcc): 3.0 to 6.0 V
Display lYpe
Duty Cycle
When not Extended
When Extended
with an HD44100H
Maximum extension
1-line display
1/8
1/11
20 characters X 1 line
20 characters x 1 line
28 characters x 1 line
28 characters x 1 line
80 characters x 1 line
80 characters x 1 line
2-line display
1/16
20 characters x 2 lines
28 characters x 2 lines
40 characters x 2 lines
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
975
HD66702 LCD-II/E20
Block Diagram (LCD.II/E20 Interior)
EXT
OSC1 OSC2
. . . - - - - - - -. . . CL1
. . . - - - - - - -...... CL2
. . . - - - - - -. . . M
o
7
Instruction
COM1COM16
Display data
RAM (DD RAM)
80 x 8 bits
8
8
11lO-bit
8hift
register
8
7
8
Character
generator RAM
(CGRAM)
64 bytes
SEG1SEG100
circuit
8
Character
generator ROM
(CGROM)
7200 bytes
Cursor
blink
controHer
Liquid crystal
display drive
voltage
selector
100
V~--L----.--~-~--e--~~------------~
GND~
V1
V2
V3
V4
V5
HITACHI
976
Hitachi America, Ltd.· Hitachi Piaza· 2000 Sierra Poini Pkwy.· Brisbane, GA 94005-1819' (415) 589-8300
HD66702 LCD-IIIE20
LCD·DlE20 Pad Arrangement
SEG34 II
SEG33 II
SEG32 II
SEG31 II
SEG30 II
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG16
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEGS
SEG7
SEGS
SEGS
SEG4
SEG3
SEG2
SEG1
106 II SEG71
107 III SEG72
106 II SEG73
105 II SEG74
104 II SEG75
103 III SEG76
102 III SEG77
, 101 III SEG78
100 II SEG79
99 II SEGSO
98 III SEG81
97 III SEG82
96I11SEG83
95I1SEG84
94 II SEG85
93I111SEG86
92 III SEGa7
91 III SEG88
901IISEG89
69I11SEG90
88 III SEG91
87 III SEG92
86 III SEG93
85 III SEG94
64 III SEG95
83 II SEG96
82 II SEG97
81 II SEG98
80 II SEG99
79 II SEG100
7811 COM16
77 II COM15
76 III COM14
75 II COM13
74 III COM12
73 III COM11
1
2
3
4
5
III 6
II 7
II 8
II 9
1110
l1li11
1112
1113
1114
1115
1116
11117
l1li16
l1li19
1120
1121
1122
1123
1124
1125
1126
1127
1128
l1li29
l1li30
l1li31
l1li32
11133
11134
GND .35
(TopWlW)
r1)peoode
HD88702
0SC2 1136
* : Test pins; to be grounded.
o ~ supply pins
• Po_ supply pins (ground)
B: Input pins
&I: OUtput pins
•
Input/output pins
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589·8300
977
HD66702 LCD-IIIE20
LCD-II Family Comparison
Item
LCD-II
(HD44780)
LCD·IIIA
(HD66780)
LCD-II/E20
(HD66702)
Power supply voltage
5V±10%
5V± 10%
5 V ± 10% for standard version;
3 V ± 10% for low Vet; version
1/4 bias
3.0 to 11 V
3.0 V to Vet;
3.0 to 6.0 V
1/5 bias
Liqu id crystal drive
voltage VLCD
4.6 to 11 V
3.0 V to Vet;
3.0 to 6.0 V
Max display digits per chip
16 digits
(8 digits x 2 lines)
16 digits
(8 digits x 2 lines)
40 digits
(20 digits x 2 lines)
Display duty cycle
1/8,1/11 and 1/16
1/8,1/11 and 1/16
1/8,1/11 and 1/16
CGROM
7,200 bits
12,000 bits
(160 character fonts of (240 character fonts of
5x 7 dots and
5x10dots)
32 character fonts of
5 x 10 dots)
7,200 bits
(160 character fonts of
5x 7 dots and
32 character fonts of
5 x 10 dots)
CGRAM
64 bytes
64 bytes
64 bytes
DO RAM
80 bytes
80 bytes
80 bytes
Segment signals
40
40
100
Common signals
16
16
16
Liquid crystal drive waveform
A
B
B
Ladder resistor for liquid
crystal drive power supply
External
External
External
Clock source
External resistor,
external ceramic filter,
or external clock
External resistor,
external ceramic filter,
or external clock
External resistor,
or external clock
Rf oscillation frequency
(frame frequency)
270 kHz ± 30%
(59 to 110 Hz for 1/8
and 1/16 duty cycles;
43 to 80 Hz for 1/11
duty cycle)
270 kHz±30%
(59 to 110 Hz for 1/8
and 1116 duty cycles;
43 to 80 Hz for 1/11
duty cycle)
320 kHz ± 30%
(69 to 128 Hz for 1/8
and 1/16 duty cycles;
50 to 93 Hz for 1/11
duty cycle)
Rf resistance
91 kO±2%
83kO±2%
68 kO (T.B.D.) for standard version;
56 kO (T.B.D.) for low Vet; version
Instructions
Fully compatible within the LCD-II family
CPU bus timing
1 MHz
2MHz
1 MHz
Package
OFP1420-80,
OFP1414-80, and
80-pin bare chip
OFP1420-80 and
OFP1414-80
144-pin bare chip (no package)
Note: Development of OFP2020-144 (144-pin quad flat package) is under consideration.
HITACHI
978
Hitachi America, Ltd.· Hitachi Piaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-II/E20
Electrical Characteristics
Absolute Maximum Ratings for Low Vee Version
Item
Symbol
Unit
Rating
Power supply voltage (1)
Vcc
V
-0.3 to +7.0
Note
Power supply voltage (2)
V1 to Vs
V
-0.3 to +7.0
Input voltage
Vt
V
-0.3 to Vee + 0.3
Operating temperature
Topr
Tstg
°C
°C
-20 to + 75
Storage temperature
3
4
-55 to + 125
Notes: 1. If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using them
within electrical characteristic limits is strongly recommended for normal operation. Use beyond these
conditions will cause malfunction and poor reliability.
2. All voltage values are referenced to GND = 0 V.
3. Applies to VI to Vs; must maintain Vee ~ V1 ~ V2 ~ V3 ~ V4 ~ VS; see below.
Vee
V,
I;
®
1
®=Vee - Vs
®=Vee -v,
®;;;
The conditions of V1 and Vs voltages are for proper
operation of the LSI and not for the LCD output level. The
LCD drive voltage condition for the LCD output level is
specified in "LCD voltage VLCD."
1.5V
®~O.25X®
4. This temperature is for packaged devices; +7SoC is the guaranteed operating temperature for bare chip devices.
DC Characteristics for Low Vee Version (Vee =3 V ± 10%, Ta =-20°C to +7soC*1)
Item
Symbol
Unit
Input high voltage (1 )
VIHI
V
Input low voltage (1)
Test Conditions
min.
typo
max.
Note
T.B.D.
Vee
2
T.B.D. 2
VIL1
V
-0.3
Input high voltage (2) (OSC1)
VIH2
V
T.B.D.
Input low voltage (2) (OSC1)
VIl2
V
Output high voltage (1) (D80-0B7)
VOH1
V
Vcc
11
T.B.D. 11
-IOH = 0.1 rnA
T.B.D.
3
Output low voltage (1) (DI3(rDB7)
VOL1
V
IOL= 0.1 rnA
Output high VOltage (2) (except DBa-DB7)
VOH2
V
-IOH = 0.04 rnA
Output low voltage (2) (except DBa-DB7)
VOl2
V
IOL = 0.04 rnA
T.B.D. 4
Driver ON resistance (COM pin)
RCOM
kn
± Id = 0.05 rnA
20
9
30
9
T.B.D. 3
T.B.D.
4
(all COM pins)
Driver ON resistance (SEG pin)
kn
RSEG
± Id = 0.05 mA
(all SEG pins)
Input/Output leakage current
III
~
Yin =Oto Vee
-1
Pull-up MOS current (RS, R/W)
-Ip
~
Vcc =3 V
T.B.D. T.B.D. T.B.D.
Power supply current
lee
rnA
Rf oscillation, extemal
clock operation, Vee = 3 V
fOSC = 320 kHz
LCD voltage
VLCD1
V
Vee-VS
115 bias
3.0
6.0
12
VLCD2
V
Vce-VS
1/4 bias
3.0
6.0
12
5
T.B.D.
6,10
Notes for DC Characteristics on pages 983 and 984.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
979
m
HD66702 LCD-IIIE20
AC C~aracteristics for Low Vee Version (Vee
=3 V ± 10%, Ta =-20°C to +7soC*1)
Clock Characteristics
Item
External clock operating frequency
EX1ernal clock duty cycle
External clock rise time
External clock fall time
Rf oscillation internal clock operating frequency
Notes on pages 983 and 984
Symbol
fep
Duty
trep
trcp
fOSC
Unit
kHz
0/0
Il s
Il s
kHz
Test Conditions min. typo max.
125
410
45
50 55
0.2
0.2
230 320 410
AI =T.B.D.
Note
7
7
7
7
8
Bus Timing Characteristics
Write Operation
Item
Enable cycle time
Enable pulse high level width
Enable riselfall time
Setup time for RS. RIW. E
Address hold time
Data setup time
Data hold time
Symbol
tCYCE
PWEH
tEr. tEl
tAS
tAH
tosw
tH
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
min.
1000
450
Unit
ns
ns
ns
ns
ns
Test Conditions
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
min.
1000
450
ns
ns
Figure 2
Figure 2
typo
max.
25
40
10
195
10
Read Operation
Item
Enable cycle time
Enable pulse high level width
Enable riselfall time
Setup time for RS. RIW. E
Address hold time
Data delay time
Data hold time
Symbol
tCYCE
PWEH
tEr. tEl
tAS
tAH
tOOR
tOHR
typo
max.
25
40
10
320
20
Segment extension signal timing
max.
Test Conditions
Item
Symbol
Unit
min.
typo
800
Clock pulse high level width
ns
Figure 3
tCWH
Clock pulse low level width
ns
Figure 3
800
tCWL
Figure 3
Clock setup time
ns
500
tcsu
Data setup time
ns
Figure 3
300
tsu
ns
Figure 3
300
Data hold time
tOH
-1000
1000
M delay time
ns
Figure 3
tOM
Figure
3
100
Clock riselfall time
ns
tet
Power supply conditions for using internal reset circuit
Since the Internal reset circuit will not operate normally in the 3-V Vee LCD-11JE20. initialize the LSI by instruction.
HITACHI
sao
Hiiachi America. Ltd.· Hitachi Piaza· 2000 Sierra Point Pkwy.· Brisbane, GA 94005-i8i9· (4i5i 589-8300
HD66702 LCD-IIIE20
Bus Timing Characteristics
Absolute Maximum Ratings for Standard Vee Version
Item
Symbol
Unit
Rating
Power supply voltage (1)
Vee
V
-0.3 to +7.0
Power supply voltage (2)
VI to Vs
V
-0.3 to +7.0
Input voltage
Vt
V
-0.3 to Vee + 0.3
Operating temperature
Topr
Tstg
°C
°C
-20 to + 75
Storage temperature
Note
3
4
-55 to + 125
Notes: 1. If LSls are used above absolute maximum ratings, they may be permanently destroyed. Using them
within electrical characteristic limits is strongly recommended for normal operation. Use beyond these
conditions will cause malfunction and poor reliability.
2. All voltage values are referenced to GND = 0 V.
3. Applies to VI to Vs; must maintain Vee VI ~ V2 ~ V3 ~ V4 ~ VS; see below.
Vee
V,
f
+
®=Vee - V5
®=Vee - V,
The conditions of VI and Vs voltages are for proper
operation of the LSI and not for the LCD output level. The
LCD drive voltage condition for the LCD output level is
specified in "LCD voltage VLCD."
®~ 1.5V
®~O.25x®
4. This temperature is for packaged devices; +7SoC is the guaranteed operating temperature for bare chip devices.
DC Characteristics for Standard Version (Vee =5 V ± 10%, Ta =-20°C to +7soC*1)
Item
Symbol
Unit
Test Conditions
min.
typo
max.
Note
Input high voltage (1)
VIHt
V
2.2
Vee
2
Input low voltage (1)
VILt
V
-0.3
O.S
2
Input high voltage (2) (OSC1)
VIH2
V
Vee-1
Vee
11
Input low voltage (2) (OSC1)
VIL2
V
Output high voltage (1) (D80-0B7)
VOHI
V
-IOH = 0.205 mA
Output low voltage (1) (DBo-DB7)
VOLI
V
IOL= 1.SmA
Output high voltage (2) (except DBa-DB7) VOH2
V
-IOH = 0.04 mA
Output low voltage (2) (except DBa-DB7)
VOL2
V
IOL=0.04 mA
0.1 Vee 4
Driver ON resistance (COM pin)
ROOM
kn
± Id = 0.05 mA
20
9
30
9
1
5
1.0
2.4
11
3
0.4
3
4
0.9 Vee
(all COM pins)
Driver ON resistance (SEG pin)
RSEG
kn
± Id = 0.05 mA
(all SEG pins)
Input/Output leakage current
III
Pull-up MOS current (RS, R/W)
-Ip
I!A
I!A
Power supply current for RS, R/W
Icc
mA
Yin = Oto Vee
-1
Vee=5V
T.B.D.
At oscillation, external
125
T.B.D.
T.B.D.
S, 10
clock operation, Vee = 5 V
fOSC = 320 kHz
LCD voltage
VLCDI
V
Vee - Vs
1/5 bias
3.0
S.O
12
VLCD2
V
Vee - Vs
1/4 bias
3.0
S.O
12
Notes for DC Characteristics on pages 983 and 984.
HITACHI
Hitachi America, Ltd.' Hitachi Plaza· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
981
II
HD66702 LCD-IIIE20
AC Characteristics for Standard Version (Vee
=5 V ± 10%, Ta =-20°C to +75°C*1)
Clock Characteristics
Item
Symbol
External clock operating frequency
External clock duty cycle
fcp
Duty
External clock rise time
External clock fall time
Rt oscillation internal clock operating frequency
trcp
trcp
fose
Un"
kHz
Test CondItIons mIn. typo max. Note
%
I1s
I1s
kHz
Rf = T.B.D.
125
45
410
55
50
230
0.2
0.2
320 410
7
7
7
7
8
Notes on pages 983 and 984
Bus Timing Characteristics (see note on page 14 for load circuits)
Write Operation
Symbol
Unit
Test ConditIons
min.
Enable cycle time
Enable pulse high level width
teveE
PWEH
ns
ns
Figure 1
1000
Figure 1
450
Enable riselfall time
tEr. tEl
ns
Setup time for RS. RIW. E
Address hold time
tAS
ns
ns
Figure 1
Figure 1
40
Item
Data setup time
Data hold time
tAH
typo
max.
25
Figure 1
10
195
tosw
tH
ns
ns
Figure 1
Figure 1
10
Read Operation
Item
Symbol
Unit
Test Conditions
min.
Enable cycle time
Enable pulse high level width
teveE
PWEH
ns
ns
Figure 2
1000
Figure 2
450
Enable riselfall time
tEr. tEf
ns
Figure 2
Setup time for RS. RIW. E
tAS
ns
Figure 2
40
Address hold time
Data delay time
Data hold time
tAH
tOOR
tOHR
ns
ns
ns
Figure 2
Figure 2
Figure 2
10
Item
Clock pulse high level width
Symbol
Unit
tewH
ns
Test Conditions
Figure 3
Clock pulse low level width
tewL
ns
Figure 3
800
Clock setup time
tesu
tsu
ns
Figure 3
500
ns
M delay time
tOH
tOM
Figure 3
Figure 3
300
ns
ns
Clock riselfall time
tct
ns
typo
max.
25
320
20
Segment extension signal timing
Data setup time
Data hold time
Figure 3
Figure 3
min.
typo
max.
800
300
-1000
1000
100
HITACHI
982
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
HD66702 LCD-II/E20
Power supply conditions for using Internal reset circuit
Item
Symbol
Unit
Test Conditions
min.
Power supply rise time
trCe
ms
Figure 4
0.1
Power supply off time
tOFF
ms
Figure 4
1
Note:
1. The following are
typo
max.
10
va terminal configurations except for liquid crystal display output.
• Input Terminal Applicable Terminals: E
(MaS without pull up)
• Applicable Terminals: RS, FVW
(MaS with pull up)
Vee
Vee
Vee
PMOS
PMOS
NMOS
NMOS
• Output Terminal
Applicable Terminals: Clt, Cl2, M, 0
Vee
PMOS
NMOS
• 1/0 Terminal
Applicable Terminals: DBO to DB7
Vee (Pull Up MOS)
t-I
PMOS
Vee
PMOS
Vee'
NMOS
(Three State
Output Circuit)
Note:
Note:
Note:
Note:
Note:
2.
3.
4.
5.
6.
Input terminals and I/O terminals. Excludes OSC1 terminals.
110 terminals.
Output terminals.
Current flowing through pull-up MOSs and output drive MOSs is excluded.
Input/output current is excluded. When CMOS input is at an intermediate level, excessive current flows
through the input circuit to the power supply. To avoid this, input level must be fixed at high or low.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
983
HD66702 LCD-II/E20
Note:
7. External clock operation.
OSC,
Open
OSC 2
Th
TI
Duty cycle = -=:-,-T-'-'.h=-" x 100%
Th+Tl
Note:
8. Internal oscillator operation using oscillation resistor Rf.
R,
cb
Rr. 56 ill ± 2% (Vec = 3 V)
Rr. 68 ill ± 2% (Vee = 5 V)
SC
'.
osc2
Reference values (T.B.D.)
Since oscillation frequency varies depending on OSC1 and·OSC2 terminal capacitance. wiring length
for these terminals should be minimized.
Note: 9. Applies to both VCOM and VSEG voltage drops.
VCOM: From power suply terminal Vee. V1. V4. Vs to each common signal terminal
(COM1 to COM1S)
VSEG: From power suply terminal Vee. V2. V3. Vs to each segment signal terminal
(SEGl to SEG40)
Note: 10. Relation between operation frequency and current consumption is shown in this diagram (Vee = 5 V).
1.8
1.6
1.4
fee2
(mAl
1.2
1.0
0.4
0.2
./
V
---
max
./V
0.8
0.6
"
V
/
V __ v---
----
::... ~
typ
0
100
200
300
400
500
fosc or fcp (kHz)
Note: 11. Applied to OSCl terminal.
Note: 12. The condition for COM pin voltage drop (VCOM) and SEG pin voltage drop (VSEG).
HITACHI
984
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Paint Pk\A.nJ.' Brisbane, CA 94005-1819· (415) 589 8300
0
HD66702 LCD-IIIE20
Timing Characteristics
Write operation
RS
).
V IH ,
V IH ,
V IL1
VIL'
tAH
-
tAS
R/W
\
V IL1
K
(VIL'
PW EH
1/
E
V IL1
tosw
I
IeF
V IH 1
V IH ,
V IL1
r-
~
~
VIH')
VIL'
-
(,V IL1
tH
Vaild Data
KV'H1
V IL1
tCVCE
I
Figure 1 Write Operation
Read operation
RS
}
<~
V IH1
VIH1
VIL1}
V IL1
~
tAs
R/W
V IH1
r\IH'
~
PW EH
VI.~2. f4- IeF
VIL'
V IH1
E
K
VIL'
tE,"
,.
~
tOOR
VOH~)
V OL1
1/
V IL1
K
V OH1
V OL1
I\:
tcVCE
Figure 2 Read Operation
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005,1819· (415) 589-8300
985
HD66702 LCD-IVE20
Interface signals with driver LSI HD44100H
CLl
C~
o
M
Figure 3 Extension Driver Interface Timing
Power on sequence
*2
2.7V14.5 V
O.2V
V e e - - - - -J
O.lms;:;;; tree;;;; lOms
toF.*l
tOFF ;;;
1 ms 1+-----001
Figure 4 Power on Sequence
Notes: 1. toff defines the time of power off for momentary power supply dip or when power supply is repeatedly
turned on and off.
2.2.7 when Vee = 5 V, and 4.5 V when Vee = 3 V.
3. Since the internal reset circuit will not operate normally if the above conditions are not satisfied,
initialize the LSI by instruction. Refer to "Initializing by Instruction."
HITACHI
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Hitachi America. ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, C,I!., 94005-1819· (415) 589-8300
HD66702 LCD-IIIE20
Note: Load Circuits
Data bus DBo-DB7
VC0=5V
Vcc=5V
Vcc=3V
2.4 kG
Test
Test o-----...--_~1_4
point
l
D-D_ _ _- - ,
point
Diodes:
IS2074®
90pF
T
""5F'"
Segment extention signals
l
Test D_----,
point
1
30PF
-=-
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
987
HD66702 LCD-II/E20
Terminal Function
Table 1 Functional Description of Tenninals
Signal
Name
No. of Input/
Lines Output
Connected to
Function
RS
Input
MPU
Signal to select registers.
0: Instruction register (for write)
Busy flag: address counter (for read)
1: Data register (for read and write)
RIW
Input
MPU
Signal to select read (R) and write (W).
n.
\A/.:+_
v ........ I"I:J
1: Read
E
Input
MPU
Operation start signal for data read/write.
DB4-DB7
4
Input/Output
MPU
Higher order 4 bidirectional three-state data
bus lines. Used for data transfer between
the MPU and the LCD-II/E20. DB7 can be
used as a BUSY flag.
DBo-DB3
4
Input/Output
MPU
Lower order 4 bidirectional three-state data
bus lines. Used for data transfer between
the MPU and the LCD-llIE20. These four
are not used during 4-bit operation.
CL1
Output
HD44100H
Clock to latch serial data D sent to the
driver LSI HD44100H.
CL2
Output
HD44100H
Clock to shift serial data D.
M
Output
HD44100H
Switch signal to convert liquid crystal drive
wav~form to AC.
D
Output
HD44100H
Sends character pattern data corresponding
to each common signal serially.
COM1-COM16 16
Output
Liquid crystal display
Common signals that are not used are
changed to non-selection waveforms. That
is, COMg-COM1O are non-selection
waveforms at 1/8 duty factor, and
COM12-COM16 are non-selection
waveforms at 1/11 duty factor.
SEG1-SEG100 100
Output
V1-VS
5
Vee,GND
2
Liquid crystal display Segment signal.
Power supply
Power supply
Power supply for liquid crystal display drive.
Vee: +5 V, GND: 0 V.
TEST
Input
Test pin; to be grounded.
EXT
Input
Test pin; to be grounded.
HITACHI
988
Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589~83()()
HD66702 LCD-II/E20
Function Of Each Block
signals make their selection from these two
registers.
Register
The HD66702 had two 8-bit registers, an
instruction register (IR), and a data register (DR).
The IR stores instruction codes such as display
clear and cursor shift, and address information for
display data RAM (DD RAM) and character
generator RAM (CG RAM). The IR can be
written from the MPU but not read by the MPU.
The DR temporarily stores data to be written into
the DD RAM or the CG RAM and data to be read
out from DD RAM or CG RAM. Data written
into the DR from the MPU is automatically
written into the DD RAM or the CG RAM by
. internal operation. The DR is also used for data
storage when reading data is read from the DD
RAM or the CG RAM. When address information
is written into the IR, data is read into the DR
from the DD RAM or the CG RAM by internal
operation. Data transfer to the MPU is then
completed by the MPU reading DR. After the
MPU reads the DR, data in the DD RAM or CG
RAM at the next address is sent to the DR for the
next read from the MPU. Register selector (RS)
Busy flag (BF)
When the busy flag is I, the HD66702 is in the
internal operation mode, and the next instruction
will not be accepted. As table 2 shows, the busy
flag is output to DB7 when RS = 0 and R/W = 1.
The next instruction must be written after ensuring
that the busy flag is O.
Address counter (AC)
The address counter (AC) assigns addresses to DD
and CG RAMs. When an instruction for address is
written in IR, the address information is sent from
IR to AC. Selection of either DD or CG RAM is
also determined concurrently by the instruction.
Mter writing into (or reading from) DD or CG
RAM display data, AC is automatically incremented by +1 (or decremented by -1). AC
contents are output to DBo-DB6 when RS = 0 and
R/W = I, as shown in table 2.
Table 2 Register Selection
RS
RIW
o
o
o
Operation
iR write as internal operation (Display clear, etc.)
Read busy flag (OB7) and address counter (OBo-OB6)
o
DR write as internal operation (DR to DO or CG RAM)
DR read as internal operation (DO or CG RAM to DR)
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589·8300
989
HD66702 LCD-IIIE20
Display data RAM (DD RAM)
The display data RAM (DD RAM) stores display
data represented in 8-bit character codes. Its
capacity is 80 x 8 bits. or 80 characters. The
display data RAM (DD RAM) that is not used for
display can be used as a general data RAM.
Relations between DD RAM addresses and
positions on the liquid crystal display are shown
below.
.
The DD RAM address (ADD) is set in the address
counter (AC) and is represented in hexadecimal.
Lower Order
Bits
+ Upper Order
Bits
"- Hexa
decimal
(Example)
-I ' -
Hexadecimal
...
-I
DD RAM address 4E
I-Line Display (N = 0)
(digit)
234
79
5
l-line
80
+
Display
Position
+ DD RAM
Address
1. When there are fewer than 80 display characters. the display begins at the head position.
For example. 20 characters using an HD66702
are displayed as:
L.-L~~~~~'--~~d-J-~-'--L~~~~~,--~~DDRAM
address
(hexadecimal)
When the display shift operation is performed. the
DD RAM address moves as:
HITACHI
nnn
2
A,e
HD6800
E
Ao
R/W
COM,COM,6
HD66702
RS
R/W
0 0 -0 7
SEG,-
OB o -OB 7
8
16
Connected
to LCD.
100
SEG,oo'
Figure 11 8·Bit MPU Interface
Example of interfacing to the HD6805
Ao- A7
8
OB o -OB7
COM,COM,6
16
HD66702
H06805
E
RS
R/W
Co
C,
C2
SEG,-
100
CO.nnected
to LCD.
SEG,oo
Figure 12 HD680S Interface
HITACHI
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1007
HD66702 LCD-IIIE20
Example of interfacing to the HD6301
RS
R/W
E
P34
P35
P36
16
COM,COM'6
Connected
to LCD.
HD66702
HD6301
PlO - PH
DBo-DB7
8
100
SEG,SEG,oo
Figure 13 HD6301 Interface
How To Use The HD66702
interface device. Input and output of the device
is TIL compatible.
Interface t~ MPU
In the example, PBO to PB? are connected to
the data buses DBO to DB? and PAO to PA2 are
connected to E, R/W and RS respectively.
1. Interface to 8-Bit MPU
When connecting to 8-bit MPU through PIA
Pay attention to the timing relation between E
and other signals when reading or writing data
and using PIA as an interface.
Figure 15 is an example of using a PIA or I/O
port (for single chip microcomputer) as an
RS
R/W
___---J!
,'------
E
Internal
Internal Operation
No
DB7
~rB-U-Sy"''W&d~'"'''''''f''7TB-u-~y'''W''''~''''''''~'''~''''' BUSY~d
Instruction
Write
I
Busy Flag
Check
I
Busy Flag
Check
I
Busy Flag
Check
I
Instruction
Write
Figure 14 Example of Busy Flag Check Timing Sequence
HITACHI
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Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-WE20
A,5
A,4
A,3
A,
Ao
HD68BOO
R/W
VMA
"'2
DBo-DB7
==D8
CS2
PA2
CS,
CSo
PA,
RS,
RSo
PAo
R/W
HD68B21
E
PB o -PB 7
0 0 -0 7
RS
COM,COM'6
R/W
E
}
HD66702
SEG,SEG,oo
8
16
r+100
f-+-
Connected
to Uquid
Crystal
Display
DBo-DB7
HD68BOO: 8 bit CPU
Figure 15 Example of Interface to HD68BOO Using PIA (HD68B21)
Figure 17 shows an example of interface to the
HMCS43C.
2. Interface to 4-bit MPU
The HD66702 can be connected to a 4-bit MPU
through the 4-bit MPU I/O port. If the 110 port
has enough bits, data can be transferred in 8-bit
lengths, but if there are insufficient bits, the
transfer is made in two operations of 4 bit each
(with designation of interface data length for 4
bits). In the latter case, the timing sequence
becomes somewhat complex (See fIgure 16).
Note: that 2 cycles are needed for the busy flag
check as well as the data trnsfer. 4-bit
operation is selected by program.
RS
____-If
R/W
\'-------
E
Internal
Internal Oparation
No
DB7
~Busv\~BUSV~
Instruction
Write
Note:
I
Busy Flag
Check
I
I
Busy Flag
Check
I
Instruction
Write
IR7, IR3: Instruction 7th bit, 3rd bit
AC3: Address Counter 3rd bit
Figure 16 An Example of 4·Bit Data Transfer Timing Sequence
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
1009
HD66702 LCD-II1E20
HMCS43C
015
RS
0 14
R/W
0 13
E
4
COM1COM 16
HD66702
DB4- DB 7
Rl0- R13
16
f-+-
SEG 1SEG100
100
r---
1
Connected
to Uquid
Crystel
Display
HMCS43C: Hitachi 4-bit single-chip microcontroller
Figure 17 Example of Interface to the HMCS43C
Interface to Liquid Crystal Display
1 line with 5 x 10 dots. Therefore, three types
of common signals are available (Table 10).
1. Character Font and Number of Lines
!
Number of line and font types can be selected
by program. (See Table 7, Instructions).
•
The HD66702 can perform 2 types of display, 5
x 7 dots and 5 x 10 dots character font, with a
cursor on each.
2. Connection to HD67702 and Liquid Crystal
Display
Up to 2 lines are displayed with 5 x 7 dots and
Figure 18 shows connection examples.
Table 10 Common Signals
Number of
Line.
2
Number of
Duty
Faetor
Character Font
Common Signal.
5
x 7 dots + Cursor
x 10 dots + Cursor
5 x 7 dots + Cursor
8
1/8
5
11
1/11
16
1/16
HITACHI
1010 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra PoinIPkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-II/E20
COM1COMa __~!!!!!!IJ
HD66702
S~Gl ~~~~W
-----------------------
Liquid Crystal
Display Panel
(20 characters
x 1 line)
SE·G 4ol - - - - - - - - - - - - - - - - - - - - '
(a)
Example of a 5x7 dot, 8 character x 1 line Display (1/4 Bias, 1/8 Duty Cycle)
C~Ml.1III11
COM"~
HD66702
SEG1~
SEG'oo!--------...,.----------......J
Liquid Crystal
Display Panel
(20 characters
x 1 line)
(b) Example of 5 x 10 dot, 20 character x 1 line Display (1/4 Bias, 118 Duty Cycle)
Figure 18 Liquid Crystal Display and Connections to HD66702
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
1011
HD66702 LCD-II1E20
Since 5 SEG signal lines can display one digit,
one HD66702 can display up to 20 digits for 1line display and 40 digits for 2-line display.
In Figure 19 examples (a) and (b), there are
unused common signal terminals, which always
output non-selection waveforms. When the
liquid crystal display panel has unused extra
scanning lines, avoid undesirable influences
due to crosstalk in the floating state by
connecting the extra scanning lines to these
common signal terminals (Figure 20).
il!UTi mu
COM,I
COM8~--~-H+H~H+--------------------~r-
COM9~~~
COM'6·~
HD66702
SEG,
1iIiI----------------------
Liquid Crystal
Display Panel
(20 characters
x 2 lines)
~Gl00~--------------------------------~
(c) Example of 5 x 7 dot. 20 character x 2 lines Display (1/5 Bias, 1116 Duty Cycle)
Figure 19 Liquid Crystal Display and Connections to HD66702 (Cont'd.)
COM'~_=
COM8~
COM.
HD66702
,-J
SEG'I!II
~Gl00r---------------------------------~
5 x 7 dot, 20 character x 1 line Display (1/4 Bias, 1/8 Duty Cycle)
Figure 20 Using COM9 to Avoid Crosstalk on Unneeded Scanning Line
HITACHI
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Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-IIIE20
3. Connection of Changed Matrix Layout
the layout. Display characteristics and the
number of liquid crystal display characters
depend on the number of common signals (or
duty factor). Note that the display data RAM
(DD RAM) addresses for 10 characters x 2
lines and 40 characters x 1 line are the same as
shown in Figure 19.
In the preceding examples, the number of lines
matched the number of scanning lines. The
display types Figure 21 are made possible by
changing the matrix layout in the liquid crystal
display panel. In either case, the only change is
COMal----~~#+--------~-
----------
SEG,
HD66702j
r=~~~~~~~~~~~~~~
----------
SEG,oo~----------------~~--------------~
COM9~~~~~~~~~~~~~~~~~~~~~~~
Co"M'6
~
___________________________________---l
5 x 7 dot, 40 character x 1 line Display
(115 Bias, 1/16 Duty Cyde)
SEG,
SEGso
-
COM,
COMa
HD66702
SEGs,
--
-
SEG,oo
5 x 7 dot, 4 character x 2 line Display
(1/4 Bias, 1/8 Duty Cycle)
Figure 21 Changed Matrix Layout Displays
HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
1013
HD66702 LCD-IIIE20
Power Supply for Liquid Crystal
Display Drive
must be changed according to duty factor. Table
11 shows the relation.
Various voltage levels must be applied to
HD66702 terminals V 1 to V S to obtain liquid
crystal display drive waveforms. The voltages
VLCO gives the peak values for liquid crystal
display drive waveforms. Resistance dividing
provides each voltage as shown in Figure 22.
Table 11 Duty Factor and Power Supply for Liquid Crystal
Display Drive
Duty Factor
1/8, 1/11
1/16
1/4
1/5
VI
Vcc -1/4 VLCO
Vcc -1/5 VLCO
V2
Vcc- 1/2 VLCO
Vec - 2/5 VLCO
V3
Vcc -l/2 VLCO
Vee - 3/5 VLCO
V4
Vcc- 3/4 VLCO
Vec-4/5VLCO
Vs
Vcc - VLCO
Vec:...VLCO
Power SUpply
Bias
Ved+5V
V3
Vee
R
V,
V2
Ved+5V)
.-
Vee
r-
/
R
V2
V LeD
V:j
R
V4
V4
~VR
Cycle)
VLeD
R
VR
-5V
1/4 Bias
(1/8, 1/11 Duty
R
V5
I-/.
R
R
R
V5
R
V,
--5V
1/5 Bias
(1/16 Duty
Cycle)
Figure 22 Drive Voltage Supply Example
HITACHI
1014
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-II1E20
Relation between Oscillation Frequency and Liquid
Crystal Display Frame Frequency
The examples in Figure 23 or liquid crystal display
frame frequency apply only when oscillation
frequency is 320 kHz (1 clock pulse =3.125 ~).
1. 1/8 Duty Cycle
~400CIOCks
COM,
Vee
V,
V2 (V3 )
V4
VS
1
2
1
[
I'
I
I
3
I
4
1------1
[J [] I
11
8'
1[
2
I,
2
I
I
1frame
'1
1 frame =3.125 ~) x 400 x 8 =10000 ~) == 10 (ms)
Frame frequency =
1
= 100 (Hz)
10 (ms)
2. 1/11 Duty Cycle
r:- 400 clocks
COM,
Vee
V,
V2 (V3 )
V4
Vs
mI
2
1 3 1 4 1--- ___ 111 I 1
IIIII
I
,.
1
I
II
I
frame
1 frame =3.125 ~) x 400 x 11 = 13750~) =13.75 (ms)
Frame frequency =
1
=72.7 (Hz)
13.75 (ms)
3. 1/16 Duty Cycle
~200cloeks
I 1 I 2 1 3 1 4 1- ---- -116 1 1 2 I
~~~Irl~~~----~~~~----
COM,
~
~
•
IIIII
1 frame
II
I
I
1 frame =3.125 ~) x 200 x 16 = 10000 ~) =10 (ms)
Frame frequency =
1
=100 (Hz)
10 (ms)
Figure 23 Frame Frequency
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
1015
HD66702 LCD-II1E20
Connection with Driver LSI HD44100H
You can increase the number of display digits by
extemaIly connecting an HD44100H liquid crystal
display driver LSI to the HD66702. When
connected to the HD66702. the HD44100H is used
as segment signal driver. The HD44100H can be
connected to the HD66702 directly since it supplies
CLI. CL2. M. and D signals and power for liquid
crystal display drive. Figure 24 shows a connection
example.
COM,-COM,. ~
ICOM,-COM.I I
•
SEG,-8EG,.
100
Caution: Connection of voltage supply terminals VI
through V6 for liquid crystal display drive
is complicated. The EXT pin must be
fixed low if the HD44100H is connected
to the HD66702.
Up to 8 HD44100H units can be connected for 1line display (duty factor 1/8 or 1/11) and up to 3
units for the 2-line display (duty factor 1/16). RAM
size limits the HD66702 to a maximum of 80
character display digits. The connection method in
figure 22 remains unchanged for both I-line and 2line display or 5 x 7 and 5 x 10 dot character fonts.
Dot Matrix lJquid Crystal Display Panel
~
i-=-
40
'?-.
~...L-_ _.L.H-D..,44100H
o 1----------lDl,
V, ------- V40 DR2 _
~~~,
SHl2
Cl
40
40
DL.,
DR,
P~~~[~~~~~<
~
1--1
HD44100H
.--+-_...,.,J.:H;.;,:D:..:.,44100H
Dl, V, ----- V40 DR2i-------- _
~~~,
SHL.,
Cl
Dl2
DR,
b
Dl, V, ------ V40 DR2
1= ~~t,
I- SHL.,
PP~~~{~$$~$~
Dl2
DR,
b
p~~g~Rl~~~~
~~: t--------f_I4+-1+++++++++--'----11--4+--11+!-+++-H++-~~~=--=
d
Mr_------_+---+~H+H+~--~--~~~~-----~
~cr_------_+----~~H+~--~---+~~~-----~----~~
GNDr_------~-----+H_H+~--~----~_H~------4-----~
~r---------------H-~~--------~~~--------~--4+~~
~r_--------------H_~--------~_H-L~------------_4~~
~r_--------------~-------------U----------------~
HD66702
Figure 24 Example of Connecting HD44100H to HD66702
HITACHI
1016
/
Hitachi Am6iica, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HD66702 LCD-II/E20
Instruction and Display Correspondence
1. 8-bit operation, 20-digit x I-line display (using
internal reset)
rewrite is needed as function (see table 13). Thus,
DB4-DB7 of the function set is written twice.
3. 8-bit operation, 20-digit x 2-line display
For 2-line display, the cursor automatically
moves from the first to the second line after the
40th digit of the 1st line has been written. Thus,
if there are only 20 characters in the first line,
the DD RAM address must again be set after
the 20th character is completed. (See table 14).
Note that the first and second lines of the
display shift are performed. In the example, the
display shift is performed when the cursor is on
the second line. However, if the shift operation
is performed when the cursor is on the first
line, both the first and the second lines move
together. When you repeat the shift, the display
of the second line will not move to the first
line, the same display will only move within
each line many times.
Table 12 shows an example of 8-bit x I-line
display in 8-bit operation. The HD66702
functions must be set by function set instruction
prior to display. Since the display data RAM can
store data for 80 characters, as explained before,
the RAM can be used for displays like a lighting
board when combined with display shift
operation.
Since the display shift operation changes
display position only and DD RAM contents
remain unchanged, display data entered first
can be output when the return home operation
is performed.
2. 4-bit operation, 20-digit x I-line display (using
internal reset)
The program must set functions prior to 4-bit
operation. Table 13 shows an example. When
power is turned on, 8-bit operation is
automatically selected and the first write is
performed as an 8-bit operation. Since nothing is
connected to DBO-DB3, a rewrite is then
required. However, since one operation is
completed in two accesses of 4-bit operation, a
Note: When using the internal reset, the
conditions in "Power Supply Condition
Using Internal Reset Circuit" must be
satisfied. If not, the LCD-II/E20 must be
initialized by instruction. (As the internal
reset does not function correctly in the 3-V
LCD-Il/E20, it must always be initialized
by instruction.) See "Initializing by
Instruction."
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1017
HD66702 LCD-II/E20
Table 12 8·Bit Operation, 20·Digit I·Line Display Example (Using Internal Reset)
Step
No. Instruction
Display
Operation
1
Power Supply On (HD66780 is
initialized 'by the internal reset circuit)
Initialized, No display appears.
2
Function Set
RS R/WDB 7 •
0 0 0 0
Sets to 8-bit operation and selects 1line display and one of the three character, fonts. (Number of display lines
and character font cannot be changed
after this. )
3
4
5
DBo
0
0
* *
Display On/Off Control
0 0 0 0 0 0 1
Entry Mode Set
0 0 0 0 0 0
0
0
0
1
1
Turris on display and cursor. Entire
display !s on space mode because of
initialization,
L_
Sets mode to increment the address by
one and to shift the cursor to the right
at the time of write to the DD/CG
RAM. Display is not shifted.
Writes "H". The DO RAM has already
been selected by initialization when the
power is turned on,
The cursor is incremented by one and
shifted to the right.
Writes "1".
0
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 0 0 0
IH
6
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 0 0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 0 0
~ntry Mode Set
o 0 0 0 0 0 0
Write Data to CG RAM/DD RAM
1 0 0 0 1 0 0 0 0
Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 1 0
Write Data to CG
1 0 0 1 0
Cursor or Display
0 0 0 o 0
Cursor or Display
0 0 0 0 0
Write Data to CG
1 0 0 1 0
Cursor or Display
0 0 0 0 0
Cursor or Display
0 0 0 0 0
Write Data to CG
1 0 0 1 0
Return Home
0 0 0 0
0
HITACHI
HITACHI
0
RAM/DD RAM
0 1 1 1
Shift
1 0 0
Shift
1 0 0
RAM/DO RAM
0 0 0 1
* *
* *
0
0
Writes "0",
Shifts only the cursor position to the
left,
IMICROKO
Shifts only the cursor position to the
left.
IMICROCO
IMICROCO
ICROCOM
0
Writes "M".
IMICROKO
I I CROCO
Shift
1 1
Shift
1 0
RAM/DO RAM
0 1 1 0
0
M:J
IMICROKO
* *
* *
Sets mode for display shift at the time
of write.
W rites space.
ITACHI
TACH I
Writes ''I''.
HITACHI
Writes "C" (correction).
The display moves to the left.
Shifts the display and cursor position to
the right.
Shifts only the cursor pOSition to the
right.
Writes "M".
Returns both display and cursor to the
original position (addfess 0).
HITACHI
1018
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Poini Pkwy.· Brisbane, GA 94005-1819' (415) 589-8300
HD66702 LCD-II/E20
Table 13 4-Bit Operation, 20-Digit I-Line Display Example (Using Internal Reset)
Step
No.
1
2
3
4
5
6
Display
Instruction
Power Supply On (HD66780 is
initialized by the internal reset circuit)
Function Set
• DB4
RS R/W DB7
0
0
0
0
0
Function Set
0
0
0
0
0
0
0
0
Display On/Off Control
0
0
0
0
1
1
0
0
Entry Mode Set
0
0
0
0
1
0
0
0
Sets to 4-bit operation.
In this case, operation is handled as 8
bits by initialization, and only this
instruction completes with one write.
Sets to 4-bit operation and selects 1line display and one of the three character fonts. 4-bit operation starts from
this point on and resetting is needed.
(Number of display lines and character
font cannot be changed after this.)
Turns on display and cursor. Entire
display is in space mode because of
initialization.
Sets mode to increment the address by
one and to shift the cursor to the right,
at the time of write, to the DD/CG
RAM. Display is not shifted.
Writes "H". The DD RAM has already
been selected by initialization when the
power is turned on. The cursor is incremented by one and shifted to the
right.
0
*
*
0
1
0
0
0
1
0
0
Operation
Initialized. No display appears.
Write Data to CG RAM/DD RAM
100
1
0
0
1
0
1
0
0
0
After this, control is the same as 8-bit operation.
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1019
HD66702 LCD-II/E20
Table 14 8-Bit Operation, 20-Digit x 2-Line Display Example (Using Internal Reset)
No. InBtnlction
Display
1
Power supply on ( HD66702 is intialized by the
internal reset circuit)
2
Function Set
RS R;WD B7 1
0
0
0
0
3
,
DBo
1
1
0
* *
Display On/Off Control
0
0
0
0
0
0
1
1
1
0
,
I
I
I
Operation
I
Initalized. No display appears.
I
Sets to 8-bit operation and selects 2line display and 5 x 7 dot character
font.
I
Turns on display and cursor. All displa:Y is in space mode because of
initialization.
,
E_J
Sets mode to increment the address
by one and to shift the cursor to the
right, at the time of write, to the DO/
CG RAM. Display is not shifted.
Writes "H". The DO RAM has already
been selected by initialization when
the power is turned on.
The cursor is incremented by one and
shifted to the right.
4
Entry Mode Set
0
0
0
0
1
1
0
5
Write Data to CG RAM/DO RAM
1
1
1
0
0
0
0
0
0
0
Write Data to CG RAM/DO RAM
1
0
0
1
1
0
0
0
0
1
Set DO RAM Address
1
1
0
0
0
0
0
0
0
Write Data to CG RAM/DO RAM
1
1
1
0
0
0
0
1
0
1
Write Data to CG RAM/DO RAM
1 0
1
0
0
1
1
0
1
1
I HITACHI
I MICROCO
J
12
Entry Mode Set
0
0
0
0
1
1
I HITACHI
I MICROCO
I
I
13
Write Data to CG RAM/DO RAM
1
1
0
1
0
0
1
0
J right.
0
1
IITACHI
IICROCOM
I
The first and second lines' shift operate at the same time.
Return Home
0
0
0
0
1
0
I HITACHI
I
I MICROCOM I
Returns both display and cursor to the
original position (Address 0).
0
0
0
IH
I
6
7
8
9
0
IHITACHI
Writes'T'.
I
IHITACHI
I
~ACHI
I
Sets RAM address so that the cursor is
positioned at the head of the 2nd line.
Writes "M".
10
11
0
0
0
1
Writes "0".
I
Sets mode for display shift at the time
of write.
Writes "M". Display is shifted to the
14
15
0
0
0
0
HITACHI
1020
Hitachi Ameiica, Ltd.· Hitachi Piaza· 2000 Sierra PQini Pkwy.· Brisbane, CA 940U5-1819· (415) 589-8300
HD66702 LCD-IIIE20
Initializing by Instruction
If the power supply conditions for correctly
operating the internal reset circuit are not met,
initialization by instruction is required. Use the
procedure in Figures 25 and 26 for initialization.
1:
(
Power on
Wait more than 15 ms
after Vee rises to 4.5 V
I
RS R/W DB, DB6 DBs DB4 DB3 DB2 DB, DBo
0
l
0
0
0
1
1
* * * *
[
BF cannot be checked before this instruction.
[
B F cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
Wait more than 4.1 ms
RS R/W DB, DB6 DBs DB4 DB3 DB2 DB, DBo
0
0
0
0
1
1
* * * *
1Wait for more than 100
jlS
RS R/W DB, DB6 DBs DB4 DB3 DB2 DB, DBo
0
0
0
0
1
1
Function set (Interface is 8 bits long.)
* * * *
[
BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)
,
BF can be checked after the follow.ing instructions. When BF is not checked, the waiting
time between instructions is longer than the
execution instruction time. (See table 7)
RS R/W DB, DB6 DBs DB4 DB3 DB2 DB, DBo
0
0
0
0
1
1
N
F
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 liD S
l
Initialization ends
* 0*
1
Function Set (Interface is 8 bits long.
Specifiy the number of display lines and
character font.)
The number of display lines and character font
cannot be changed afterwards.
Display off
Display clear
Entry mode set
Note: As the internal reset does not function correctly in the 3-V LCD-lItE20, it must be initialized by instruction.
Figure 25 8-Bit Interface
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1021
HD66702 LCD-II/E20
!
2:
Wait more than 1 5 ms
after Vee rises to 4.5 V
B F cannot be checked before this instruction.
[
Function set (Interface is B bits long.)
[
BF cannot be checked before this instruction.
Function set (Interface is B bits long.)
[
B F cannot be checked before this instruction.
Function set (Interface is 8 bits length.)
RS R/W DB, DBs DB5 DB.
0
0
0
0
0
0
0
0
0
0 0
0 0
0 N
0 0
0
0 0
0 0
0 0
0 0
0
0
F
0
0
0
0
0
1
0
0
* 0*
0
0
0
0
0
I/O
0
0
0
S
BF can be checked after the following instructions. When' BF is not checked, the waiting
time between instructions is -longer than the
execution instruction time - (See table 7)
Function Set (Set interface to be 4 bits long.)
Interface is B bits length_
Function Set (Interface is 4 bits long. Specify
the number of display lines and character font.)
The number of display lines and character font
cannot be changed afterwards_
Display off
Display clear
Entry Mode Set
Initialization ends
Note: As the internal reset does not function correctly in the 3-V LCD-UtE20, it must be initialized by instruction.
Figure 26 4.Bit Interface
HITACHI
"IInnl'\
IUL'"
Hitachi America, Lid .• Hiiachi Piaza • 2000 Sierra Point Pkwy. • Bnsbane. CA 94005-1819 • (415) 589-8300
NOTES
HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1023
•
Hitachi America, Ltd.
SEMICONDUCTOR & I.C. DIVISION
Hitachi Plaza
2000 Sierra Point Parkway
Brisbane, CA 94005-1819
Telephone: 415-589-8300
Fax:415-583~4207
REGIONAL OFFICES
NORTHEAST REGION
SOUTHEAST REGION
PACIFIC MOUNTAIN REGION
Hitachi America, Ltd.
77 South Bedford Street
Burlington, MA 01803
Telephone: 617-229-2150
Fax: 617-229-6554
Hitachi America, Ltd.
5511 Capital Center Drive, Suite 204
Raleigh, NC 27606
Telephone: 919-233-0800
Fax: 919-233-0508
Hitachi America, Ltd.
4600 S. Ulster Street, Suite 700
Denver, CO 80237
Telephone: 303-740-6644
Fax: 303-740-6609
NORTH CENTRAL REGION
SOUTH CENTRAL REGION
AUTOMOTIVE REGION
Hitachi America, Ltd.
500 Park Boulevard, Suite 415
Itasca, IL 60143
Telephone: 708-773-4864
Fax: 708-773-9006
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
Telephone: 214-991-4510
Fax: 214-991-6151
Hitachi America, Ltd.
330 Town Center Drive, Suite 311
Dearborn, MI48126
Telephone: 313-271-4410
Fax: 313-271-5707
SOUTHWEST REGION
Hitachi America, Ltd.
325 Columbia Turnpike, Suite 203
Florham Park, NJ 07932
Telephone: 201-514-2100
Fax: 201-514-2020
NORTHWEST REGION
Hitachi America, Ltd.
1900 McCarthy Boulevard, Suite 310
Milpitas, CA 95035
Telephone: 408-954-8100
Fax: 408-954-0499
Hitachi America, Ltd.
2030 Main Street, Suite 450
Irvine, CA 92714
Telephone: 714-553-8500
Fax: 714-553-8561
TELECOM REGION
DISTRICT OFFICES
CANADA
MINNESOTA
TEXAS
Hitachi (Canadian) Ltd.
320 March Road, Suite 602
Kanata, Ontario, Canada K2K 2E3
Telephone: 613-591-1990
Fax: 613-591-1994
Hitachi America, Ltd.
3800 W. 80th Street, Suite 1050
Bloomington, MN 55431
Telephone: 612-896-3444
Fax: 612-896-3443
Hitachi America, Ltd.
10777 Westheimer, Suite 1040
Houston, TX 77042
Telephone: 713-974-0534
Fax: 713-974-0587
FLORIDA
NEW YORK
IBM ENGINEERING
Hitachi America, Ltd.
4901 N.W. 17th Way, Suite 302
Fort Lauderdale, FL 33309
Telephone: 305-491-6154
Fax: 305-771-7217
Hitachi America, Ltd.
2f Old Main Street, Suite 104
Fishkill, NY 12524
Telephone: 914-897-3000
Fax: 914-897-3007
Hitachi America, Ltd.
9600 Great Hills Trail, Ste. 150W
Austin, TX 77042
Telephone: 512-345-9983
Fax: 512-343-2759
MANUFACTURING FACILITY
ENGINEERING FACILITY
Hitachi Semiconductor (America) Inc.
6321 East Campus Circle Drive
Irving, TX 75063-2712
Hitachi Micro Systems, Inc.
179 East Tasman Drive
San Jose, CA 95134
Technical product or priCing questions can be answered by your nearest Hitachi office.
You may order product literature either by calling your nearest Hitachi office or by calling 1-800-285-1601.
1024
HITACHI®
·.-
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