1992_Hitachi_Nonvolatile_Memory_Data_Book 1992 Hitachi Nonvolatile Memory Data Book
User Manual: 1992_Hitachi_Nonvolatile_Memory_Data_Book
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NONVOLATILE MEMORY
DATA BOOK
HITACHI®
-.------.-.~.~-------
M13T012
-----
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without
notice.
2.. All rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
5. No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.
May 1992
ii
©Copyright 1992, Hitachi America. Ltd.
Printed in U.S.A.
INDEX
Nonvolatile Memory Data Book
\
D
Introduction
IDATA SHEETS I
EEPROM
Flash Memory
II
EPROM (UV Erasable and OTP)
Mask ROM
HITACHI
iii
.. .,,, .. n,,'\1
I'IV.'
ATII
~
.1I~.lIl'\nV
v v ...,............v.....v.vn
I
..,,..\1 ,.....
nATA n l ' \ l ' \ v
JUVI'\
TABLE OF CONTENTS
SECTION 1
Introduction
QUICK REFERENCE GUIDE ....................................................................................... xi
PACKAGE INFORMATION ........................................................................................... 1
RELIABILITY OF HITACHI MEMORIES ................................................................. 1-16
QUALITY ASSURANCE OF HITACHI MEMORIES ................................................ 1-22
OUTLINE OF TESTING METHOD .......................................................................... 1-2S
APPLICATION ......................................................................................................... 1-29
SECTION 2
EEPROM
DATA SHEETS
I
64K
SKxS
SKxS
HN5SC65 Series ............................................ 2-1
HN5SC66 Series .......................................... 2-15
256K
32KxS
32KxS
HN5SC256 Series ........................................ 2-29
HN5SC257 Series ........................................ 2-40
1M
12SK x S
12SK x S
HN5SC1001 Series .............. ;....................... 2-54
HN5SV1001 Series ...................................... 2-70
SECTION 3
Flash Memory
1M
12SK x S
HN2SF101 Series .......................................... 3-1
4M
512K x S
HN2SF4001 Series ...................................... 3-13
SECTION 4
EPROM (UV Erasable and OTP)
256K
32K x S
32K x S
HN27C256A Series ...................................... .4-1
HN27C256H Series ..................................... 4-11
512K
64KxS
64KxS
HN27512 Series ......................................... .4-21
HN27C512 Series ........................................ 4-2S
1M
64K x 16
12SK x S
12SK x S
HN27C1024H Series ., ................................. 4-35
HN27C101A Series ..................................... 4-47
HN27C301A Series .................................... .4-59
4M
256K x 16
256K x 16
512K x S
HN27C4096 Series ...................................... 4-63
HN27C4096H Series .................................. .4-77
HN27C4001 Series ...................................... 4-91
iv
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589-8300
HITACHI
SECTIONS
Mask ROM
1M
12SKxS
12SKxS
12SK x S
HN62321/HN62331 Series ............................ 5-1
HN62321 E Series .......................................... 5-4
HN62321A1HN62331A Series ....................... 5-7
2M
12SK x 16, 256K x S
12SK x 16
256Kx S
HN62412/HN62422 Series .......................... 5-11
HN62442B Series ........................................ 5-17
HN62302B Series ........................................ 5-23
4M
256K x 16, 512K x S
256K x 16, 512K x S
256K x 16, 512K x S
256K x 16
256Kx 16
512K x S
512KxS
512K x S
HN62414/HN62434 Series .......................... 5-27
HN62415 Series .......................................... 5-34
HN62444 Series .......................................... 5-41
HN62444B Series ........................................ 5-47
HN62444BN Series ..................................... 5-52
HN62314B/HN62334B Series ..................... 5-5S
HN62315B Series ........................................ 5-62
HN62344B Series ........................................ 5-66
8M
512Kx16,1MxS
512Kx16,1MxS
512K x 16, 1M x S
1MxS
1MxS
HN6241S Series .......................................... 5-69
HN6242S Series .......................................... 5-76
HN6243SN Series ........................................ 5-S2
HN6231SB Series ........................................ 5-S9
HN6232SB Series ........................................ 5-92
16M
1M x 16, 2M xS
1Mx 16, 2M xS
1M x 16, 2M x S
1M x 16, 2MxS
HN624017 Series ........................................ 5-95
HN624116 Series ...................................... 5-101
HN624116L Series .................................... 5-107
HN624316N Series ................................. ~ .. 5-113
32M
2M x 16, 4M xS
HN624032 Series ...................................... 5-120
Hitachi Sales Offices ...........................................................................................5-126
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819, (415) 589-8300
v
D
vi
NONVOLATILE MEMORY DATA BOOK
D
Section One
Introduction
• Quick Reference Guide
• Package Information
• Reliability of Hitachi Memories
• Quality Assurance of Hitachi Memories
• Outline of Testing Method
• Application
HITACHI
vii
viii
• QUICK REFERENCE GUIDE TO HITACHI MEMORIES
Type
Total
Bits
Part No.
Process
Access
Time
(ns)
Organi·
zation
HN58C65
64K
HN56C66
8Kx8
HN56C256
256K
EEPROM
HN58C257
CMOS
32Kx8
128Kx8
HN58Vl001
Type
Total
Bits
Part No.
Process
Organi·
zation
FP
250
28
28
250
28
28
20il
28
28
HN28Fl01
128Kx8
t--;so
32
32
32
2·54
32
32
32
2·70
250
3.0
Access
Time
(ns)
Supply
Voltage
(V)
Part No.
Process
FP
TFP
32
32
32
32
3·1
32
32
32
32
3·1
32
32
32
32
3·1
32
32
32
3·13
150
32
32
32
3·13
~
32
32
32
3·13
r--;-sor---
Organi·
zation
1~~i
SU~IY
vo(~ge
r-w-
HN27C256A
32Kx8
1M
FP
28
28
28
r--ro-
28
28
28
28
28
28
28
28
HN27512
~
28
28
~
28
28
~
250
HN27C512
r--m-
HN27Cl024H
r--wo
64Kx8
64Kx16
CMOS
r--wr--;so
100
r--w-
HN27Cl01A
5.0
~
r--wo
HN27C301A
r--wr--;so
HN27C4096
~
100
256Kx16
HN27C4096H
HN27C4001
512Kx8
CC
Page
Mainte·
CP
nance
TIP
40
40
44
44
40
40
44
32
32
Only
··
··
·
28
f--a5
128Kx8
4M
DP
~
85
EPROM
Only
Packaaes (No. of Pins)
DG
28
28
HN27C256H
512K
nance
CP
100
256K
Mainte·
Packages (No. of Pins)
DP
Access
B~s
2·40
2·54
5.0
512Kx8
Total
2·29
32
32
120
4·91Type
2·15
32
CMOS
HN28F4001
2·1
32
32
200
4M
Page
120
r--FLASH
TFP
5.0
120
1M
Mainte·
nance
Only
Packages (No. of Pins)
DP
200
HN58Cl00l
1M
Supply
Voltage
(V)
44
··
···
Page
4·1
4·1
4·1
4·11
4'.11
4·11
4·21
4·21
4·28
4·28
44
4·35
4·35
44
44
4·35
4·35
32
32
32
4·47
4·47
32
32
32
32
32
4·47
32
32
32
32
4·59
4·59
4·59
40
40
44
44
40
40
44
44
r--wo
40
40
44
'120
100
32
32
32
4·91
4·91
150
32
32
4·91
r--;so
r--ro
fgs
4-63
4·63
44
44
4·63
4·77
4·77
4·77
44
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589·8300
ix
o
QU!CK REFERENCE
GU!!)E--------------------------
Total
Type
Bits
Part No.
Process
Access
Time
(ns)
150
Organi·
zation
HN~321
1M
128Kx8
HN62321E
HN62331A
HN62412
28
28
5·1
120
28
28
5·1
28
28
5-4
5-7
200
40
44
5-11
~
40
44
5·11
HN62302B
256Kx8
170
32
32
256Kx16
HN62334B
CMOS
512Kx8
HN62315B
HN62344B
HN62418
8M
512Kx16
lMx8
HN62438N
HN62318B
HN62328B
lMx8
HN624017
HN624116
lMx16
2Mx8
16M
HN624116L
32M
HN624032
40,46
44,64
5·27
40,46
44,64
5·27
""""""i5il
40
40,48
44,64
----;sQ7
40
40,48
44
44
44
5·34
20il
40
40,48
44
44
44
5·34
100
40
48
44
44
100
40
44
44
5-47
40
44
44
5-52
170
32
32
5·58
200
32
32
5·58
""""""i5il
- 150
32
32
32
32
32
5·62
20il
- 100
32
32
32
5-62
32
32
150
42
44,46
44,64
150
42
44,48
44
~
42
44,46
44
I 120/60
42
44,46
44
5-62
I 150m
42
44,48
44
5·82
150
32
32
~
32
32
170
42
44,48
44
44
5·95
~
42
44,48
44
44
5·95
~
42
44,46
5-101
20il
42
44,48
5·101
5·107
- 120flO
5.0
DP: Plastic Duallnline Package (PDIP)
DG: Ceramic Duallnline Package (CerDIP)
CP: Plastic J·Leaded Chip Carrier (PLCC)
5·27
5-41
5·58
5-66
44
5-69
5·76
5-76
5·89
5·92
250
3.5
42
44,48
300
3.0
42
44,46
5-107
42
44,48
5·113
42
44,48
5·113
42
44
5-120
1sOi7O
2Mx16
4Mx8
5-17
5·23
40
120/60
HN624316N
44
40
,..--'--
HN62428
44
170
-
HN62314B
5-7
~
-
HN62444BN
5.0
150
CC: Ceramic J·Leaded Chip Carrier (LCC)
FP: Plastic Small Outline Package (SOP)
QFP: Plastic Quad Flat Package
TOFP: Plastic Thin Quad Flat Package
TFP: Plastic Thin Flat Package (TSOP-Type I)
TTP: Plastic Thin Flat Package (TSOP-Type II)
HITACHI
x
P~
5·1
32
40
HN62444B
TIP
32
40
HN62444
TQFP
32
100
,
OFP
32
128Kx16
256Kx16
512Kx8
CP
~
~
~
HN62442B
HN62415
MaskROM
~
HN62422
HN62434
Maintenanoe
Only
FP
28
128Kx16
256Kx8
HN62414
4M
P ICkaaI s (No. of Pinsi
"DP
28
I---
HN62331
HN62321A
2M
Supply
vo:e
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
D
Package
Information
HITACHI
1-1
ii PACKAGE iNFORiviATiON
Unit: mm
• Plastic Dual In-line Package (DIP)
• Dp·28
28
2.54%0.25
(0.100:1:0.010)
0.48:1:0.10
0.019:1:0.004)
• Dp·32
41.911.650)
32
42.5max\1.673max)_
cnx
171ii~
D
'"-..............,.I....I,'...
·4o:<1(0"".05...5l'"""f"lI~.
]l~
I~
!8
5•24 O.
)
~ ~ ~
8
0.2'
". 'if(O.OIO!Um
~O-1
• Dp·40
HITACHI
1-2
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589·8300
- - - - - - - - - - - - - - - - - - - - - - - P A C K A G E INFORMATION
• Plastic Dual In-line Package (DIP)
(Cont'd.)
Unit: mm
• DP-42
D
APPLICABLE ICs
DP-28
• HN58C65-Series
• HN58C66-Series
• HN58C256-Series
• HN27C256A-Series
• HN27C256H-Series
• HN27512-Series
• HN27C512-Series
• HN62321-Series
• HN62331-Series
• HN62321E-Series
DP-32
• HN58Cl00l-Series
• HN58VlOOl-Series
• HN28FlOl-Series
• HN27F4001-Series
• HN27C 10 1A-Series
• HN27C301A-Series
• HN62321A-Series
• HN62331A-Series
• HN62302B-Series
• HN62314B-Series
• HN62334B-Series
• HN62315B-Series
• HN62344B-Series
• HN62318B-Series
• HN62328B-Series
DP-40
• HN62412-Series
• HN62422-Series
• HN62442B-Series
• HN 62414-Series
• HN62434-Series
• HN62415-Series
• HN62444-Series
• HN62444B-Series
• HN62444BN-Series
DP-42
• HN62418-Series
• HN62428-Series
• HN62438N-Series
• HN6240l7-Series
• HN624116-Series
• HN624116L-Series
• HN624316N-Series
• HN624032-Series
HITACHI
Hitachi America, Ltd .• 2000 Sierra' Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
1-3
PACKAa~ :NfO~~~AT:Ot~
-------------------------------
• Ceramic Dual In-Line Package (DIP)
Unit: mm
• DG-28
36.83 (1.450)
28
IS
0
..........
... ',:::'",
-~
14
I 1.30(0.osItn
15.24
(0.600)
c
.5
'E
0.2S!g:6~
0.48:t0.I
0.Ol9±D.O04)
2.54:tO.25
(O.IOO±O.OlO
(o.olO! :8ga)
·DG-32
41.91(1.650)
17
32
]
0
r
16
1 1.32(0.OS2tn
2.S4:t0.2S
(O.100:to.olO
.......
'",
:!s.
15.24
(0.600)
O.48±O.1
0:Ol9:tO.004)
HITACHI
1-4
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
I ·Ceramic Dual In-Line Package (DIP) I (Cont'd.)
Unit: mm
• DG-40A
o
52.07 .050
40
21
0
.......
.......
....
:!.s.
20
15.24
(0.600)
APPLICABLE ICs
00-28
• HN27C256A-Series
• HN27C256H-Series
00-32
• HN27C 10 1A-Series
• HN27C301A-Series
• HN27C4001-Series
oo-40A
• HN27ClO24H-Series
• HN27C4096-Series
• HN27C4096H-Series
• HN27512-Series
• HN27C512-Series
HITACHI
Hitachi America. Ltd .• 2000 Sierra Point Pkwy.· Brisbane. CA 94005·1819· (415) 589-8300
~---.----.-----.---
1-5
- - - - - - - - - - - - - - - - _ . _ - - - _ •... _ - - - - - ... _------ ...
-
..
PACKAGE ::-':~C~~.~AT:O~': - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
• Plastic Small Outline Package (SOP)
Unit: mm
• Fp·28D
• FP·28DA
18.3 0.72)
18.75max(0.75max)
......
....
00,8.
• FP·32D
20.45(0.805 )
20.95ma,,(0.825max)
17
xx
....-
~ ~
....
::~
s
16
1.0max
(0.039max
0.4~:~
(0.0 16~:gg~)
XX
....
E E
-
",N
0"';
'0
...
0.15 0.006
HITACHI
1-6
Hitachi America. Ltd. ·2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
• Plastic. Small Outline Package (SOP)
• FP-40D
26.00(1.024)
Unit: mm
Cont'd.
I 26.20max(1.031 max) I
40 ;.u-wLJ..U..U.1llJ..UJJ..W.UJ.WJ..U..l.WLJ..U..U.ll.I21
3;:-
o
~ ~
$28
'-mnrrmrmm1TT!TmmT'lTTT'rrmrrr'20
~~
16~
Ng
1413.030
(0.556.0.012)
1.715
(0.068)
0-8
I
I 1.27(0.050) I
.5
~
0.80•. 20
(0.031.0.008)
~;;;~~8
Os
""'f
!13.34!0.525! !
• FP-44D
M,
t: : : :
:~: : : : : :I~I
48
I
1.72
~~!I~~I
~(O"
\DC
0.80.0.20
0.40.0.10
• FP-48DA
16.04.0.30
20.0
20.4max
I"
I25
~]
24
.,"
8..;
0.40
15.24
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589·8300
1·7
PACKAGE INFORMATION
j
I •Plastic Small Outline Package (SOP) ICont'd.
APPLICABLE ICs
<,';
,
FP-28D
• HN58C65-Series
• HN58C~-Series
• HN58C256-Series
FP-28DA
• HN62321-Serles
• HN6233I-Series
• HN6232IE-Series
FP-28DA
• HN58C65-Series
• HN27C256A-Series
• HN27C256H-Series
FP-32D
• HN58CI00I-Series
• HN58VI001-Series
• HN28FI0I-Series
• HN28F400 I-Series
• HN27C 10 1A-Series
• HN27C301A-Series
.• HN6232IA-Series
• HN6233IA-Series
FP-40D
• HN6244~B-Series
• HN624I4-Series
• HN62434-Series
• HN62415-Series
FP-44D
• HN62444B-Series
• HN62444BN-Series
• HN624I8-Series
• HN62428-Series
• HN62438N-Series
• HN6240I7-Series
• HN624116-Series
• HN624I16L-Series
• HN624316N-Series
• HN624032-Series
FP-48DA
• HN624I4-Series
• HN62434-Series
• HN624I5-Series
• HN62444-Series
• HN624I8-Series
• HN62428-Series
• HN62438N-Series
• HN624017-Series
• HN6241I6-Series
• HN6241I6L-Series
• HN6243I6N-Series
• HN62302B-Series
• HN623I4B-Series
• HN62334B-Series
• HN62315B-Series
• HN62344B-Series
• HN62318B-Series
• HN62328B-Series
HITACHI
1-8
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
Unit: mm
- - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
Unit: mm
• Plastic Quad Flat Package (QFP)
17 2:!:0 3
014.0
• FP-44A
33
23
D
22
34
~l
.,'"
0
'"
....
12
44
II
0.35:!:0.05 Jl.,0.15191
00
N~
co
t I
o
~.,
N
'"
....
::
I!
0
0-5'
.:;
• FP-64B
32
~
0.15 0.006
APPLICABLE ICs
FP-44A
• HN62412-Series
• HN62422-Series
• HN62442B-Series
• HN62414-Series
• HN62434-Series
FP-64B
• HN62414-Series
• HN62434-Series
• HN62418-Series
• HN62415-Series
• HN62444-Series
• HN62418-Series
• HN62428-Series
• HN6240 17 -Series
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
1-9
PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - -
• Plastic Thin Quad Flat Package (TQFP)
• TFp·44
15.610.614)
014.0100.551
33
23
~
...
34
"I
;:l
oft
-44
I
0.3510.014>.11.
II
=
12
0.15 0.OO6JIMI
"
APPLICABLE ICs
TFP-44
• HN62414-Series
• HN62434-Series
• HN62415-Series
• HN62418-Series
• HN62428-Series
• HN624017-Series
HITACHI
1-10
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
Unit: mm
- - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
o
Plastic Thin Small-Outline Package (TSOP)-Type-I
·TFP-32D
Unit: mm
8(0.3151.
7
32
D
..
....N
e...
:!!
1
11.11.
0.2tO.l
(0.008to.004)
0.1:0 0.02011
0.08 0.003)IMI
C:oI0.l010.00411
oTFP-32DR
8.0
8.2...
17
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HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589·8300
1-11
PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - -
I •Plastic Thin Small-Outline Package (TSOP)-Type-I. ICont'd.
• TFP-32DAR
Unit: mm
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APPLICABLE ICs
TFP-32D
• HN28FlOl-Series
• HN28F4001-Series
TFP-32DR
• HN28FIOl-Series
• HN28F4001-Series
TFP-32DA
• HN58C66-Series
• HN58C257-Series
• HN58ClOOl-Series
• HN58VlOOI-Series
• HN28FIOI-Series
TFP-32DAR
• HN58C257-Series
• HN58ClOOI-Series
• HN58VlOOl-Series
• HN28FlOl-Series
I·Plastic Thin Small-Outline Package (TSOP)-Type-II I
• TTP·32D
2095
21.35 max
32
10
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HITACHI
1-12
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
Unit: mm
- - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
I •Plastic Thin Small-Outline Package (TSOP)-Type-II I Cont'd.
Unit: mm
2(1.95
·TTP·32DR
D
32
O.4CU: 0.10
0.21
·TTp·44D
To Be Advised
APPLICABLE ICs
TIP-32D
• HN27CIOIA-Series
• HN27C400l-Series
TIP-32DR
• HN27CIOIA-Series
• HN27C400l-Series
TIP-44D
• HN62415-Series
• HN62438N-Series
HITACHI
Hitachi America, Ltd. ·2000 Sierra'Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
1-13
PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - -
• Ceramic Leaded Chip Carrier (LCC)
• CC-44
)8
CI. 02 ?"!"'''''''''"'''''':)1'!7
APPLICABLE ICs.
CC-44
• HN27C1024H-Series
• HN27C4096-Series
• HN27C4096H-Series
HITACHI
1-14
Hitachi America, Ltd.' 2000 Sierra POint Pkwy.' Brisbane, CA94005-1819' (415) 589-8300
Unit: mm
- - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
• Plastic Leaded Chip Carrier (PLCC)
Unit: mm
• CP-32
D
;;;
0
0
;= =3,
20
S30
-.
.. 0
.
o .,
;111
-
0
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~ f:l"!
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·CP-44
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016.5 0
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29
APPLICABLE ICs
CP-32
• HN28F101-Series
CP-44
• HN27ClO24H-Series
• HN27C4096-Series
• HN27C4096H-Series
• HN62442B-Series
• HN62444B-Series
• HN62444BN-Series
(
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005·1819· (415) 589-8300
1-15
• RELIABILITY OF HITACHI IC MEMORIES
RELIABILITY CHARACTERISTICS FOR
SEMICONDUCTOR DEVICES
Hitachi semiconductor devices are designed, manufactured and inspected so as to achieve a high level
of reliability. Accordingly, system reliability can be
improved by combining highly reliable components
along with proper environmental conditions. It is
important to examine semiconductor device characteristics in light of their reliability.
• Semiconductor devices are essentially structure
sensitive as seen in surface phenomenon. Fabricating the device requires precise control of a large
number of process steps.
• Device reliability is partly governed by electrode
materials and package materials, as well as by the
coordination of these materials with the device
materials.
• Devices employ thin-film and fine-processing techniques for metallization and bonding. Fine materials
and thin film surfaces sometimes exhibit physically
different characteristics from the bulks.
• Semiconductor device technology advances drastically: Many new devices have been developed
using new processes over a short period of time.
Thus, conventional device reliability data cannot be
used in some cases.
.
• Semiconductor devices are characterized by volume production. Therefore, variations should be an
important consideration.
• Initial and accidental failures are only considered to
be semiconductor device failures based on the fact
that semiconductor devices are essentially operable semi permanently. However, wear failures
caused by worn materials and migration should
also be reviewed when electrode and package
materials are not suited for particular environmental
conditions.
• Component reliability may depend on device mounting, conditions for use, and environment. Device
reliability is affected by such factors as voltage,
electric field strength, current density, temperature,
humidity, gas, dust, mechanical stress, vibration,
mechanical shock, and radiation magnetic field
strength.
Initla~failure
region
: Declining failure rates (m<1)
11
IE
Random failure region
: Constant failure rates (m=1)
-
Useful longevity
I m: Weibull distribution
I Ionn parameter
.. I
T ime(t)
Figure 1 Typical failure rate curve
Device reliability is generally represented by the
failure rate. 'Failure' means that a device loses its
function, including intermittent degradation as well as
complete destruction.
Generally, the failure rate of electric components and
equipment is represented by the bathtub curve shown
in Figure 1. For semiconductor devices, the configuration parameter of the Weibull distribution is smaller
than 1, which means an initial failure type. Such
devices ensure a long lifetime unless extreme environmental stress is applied. Therefore, initial and
accidental failures can become a problem for semiconductor devices. Semiconductor device reliability
can be physically represented as well as statistically.
Both aspects of failures have been thoroughly analyzed to establish a high level of reliability.
SEMICONDUCTOR FAILURE TYPES AND
THEIR MECHANISM
Semiconductor device failures are categorized as
disconnection, short-circuit, deterioration and miscellaneous failures. These are summarized in Table
1. Typical failure mechanisms are:
Surface Deterioration
The pn junction has a charge density of 1014-102°/
cm 3 • If charges exceeding the above den~ity are
accumulated on the pn junction surface, particularly
adjacent to the depletion layer, electric characteristics of the junction tend to be easily varied. Although
the surface of such devices as planar transistors is
generally covered with a Si02 film and is in an inactive
state, the possibility of deterioration caused by surface channels still exists. Surface deterioration depends heavily on applied temperature and voltage
and is often handled by the reaction model.
HITACHI
1-16
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - Reliability of HltachllC Memories
Table 1 Failure Modes, Mechanisms and Related Causes
Failure modes
Failure mechanisms
Failure related causes
Withstanding voltage
reduced, Short, Leak
current increased, hFE
degraded, Threshold
voltage variation, Noise
Pin hole, Crack, Uneven.
thickness, Contamination,
Surface inversion, Hot
carrier injected
Passivation
Surface oxide film,
Insulating film between
wires
Open, Short, Resistance
increased
Flaw, Void, mechanical
damage, Break due to
uneven surface,
Non-ohmic contact,
Insufficient adhesion
strength, Improper
thickness,
Electromigration,
Corrosion
Metallization
Interconnection, Contact,
Through hole
Open, Short Resistance
increased
Bonding runout,
Compounds between
metals, Bonding position
mismatch, Bonding
damaged
Connection
Wire bonding, Ball
bonding
Open, Short
Disconnection, Sagging,
Short
Wire lead
Internal connection
Withstanding voltage
reduced, Short
Crystal defect,
Crystallized impurity,
Photo resist mismatching
Diffusion, Junction
Junction diffusion,
Isolation
Open, Short, Unstable
operation, Thermal
resistance increased
Peeling, chip, Crack
Die bonding
Connection bertween die
and package
Short, Leak current
Increased, Open,
Corrosion disconnection,
Soldering failure
Integrity, moisture ingress,
Impurity gas, High
temperature, Surface
contamination, Lead rust,
Lead bend, break
Package sealing
Packaging, Hermetic Seal,
Lead plating, Hermetic
package & plastic package,
Filler gas
Short, Leak current
increased
Dirt, Conducting foreign
matter, Oranic carbide
Foreign matter
Foreign matter in package
Short, Open, Fusing
Electron destroyed
Input/output pin
Electrostatics, Excessive
Voltage, Surge
Soft error
Electron hole generated
Disturbance
alpha particle
Leak current increased
Surface inversion
D
High electric field
HITACHI
Hitachi America, Ltd. '2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
1-17
Reliability of Hitachi Ie Memories - - - - - - - - - - - - - - - - - - - - - - - One example is surface deterioration caused by hot
carriers. Hot carriers are generated when such devices as MOS dynamic RAMs are operated at a
voltage near the minimum breakdown voltage (BVos)
by raising internal voltage and when a strong electric
field is established near the MOS device's drain
resulting from reduced device geometry from 2 ~m to
0.8 ~m. Generated hQt carriers may affect surface
boundary characteristics on a part of the gate oxide
film, resulting in degradation of threshold voltage
(VTH) and counter conductance (gm). Hitachi devices
employ improved design and process techniques to
prevent these problems. However, as processes
becomes finer, surface deterioration may possibly
become a serious problem.
Electrode-Related Failures
Electrode-related failures have become increasingly
important as multi-layer wiring has become more
complicated. Noticeable failures include
electromigration and AI wiring corrosion in plastic
sealed packages.
ELECTROMIGRATION
This is a phenomenon in which metal atoms are
moved by a large current of about 106 Alcm 2 supplied
to the metal. When ionized atoms collide with the
current of scattering electrons, an 'electron wind' is
produced. This wind moves the metal atoms in the
opposite direction from the current flow, which generates voids at a negative electrode, and hillock and
whiskers at an opposite one. The generated voids
increase wiring resistance and cause excessive currents to flow in some areas, leading to disconnection.
The generated whiskers may cause shortcircuits in
multi-metal line.
Figure 2 Categorized AI corrosion mode
failure can be generated when the adhesion surface
between an element and resin is separated or when
foreign materials are attached to the element with
human saliva. Under a bias-applied, high-temperature, high-humidity condition, corrosion is generated
in higher potential areas while in lower potential
areas, grain corrosion occurs. Once this failure occurs in part of a device, the device can become worn
out in a relatively short time. This failure proves to
depend on the hydroscopicc- volume resistivity of
sealed resin. The AI line corrosion mechanism described above is summarized in Figure 3.
MULTI-METAL LINE RELATED FAILURES
Major failures associated with multi-metal line include increased leak currents, shortcircuits caused
by a failed dielectric interlayer, and increased contact
metal resistance and disconnection between metal
wirings.
AL LINE CORROSION AND DISCONNECTION
When plastic encapsulated devices are subjected to
high-temperatures, high-humidity or a bias-applied
condition, AI electrodes in devices can cause corrosion or disconnection (Figure 2). Under high-temperature and high-humidity, corrosion is randomly
generated over the element surface. However, after
an extended period of time, the corrosion has not
significantly increased. Accordingly, this failure is
possibly due to an initial failure associated with
manufacturing. It is also verified that this type of
Figure 3 Plastic package section and AI corrosion mechanism
HITACHI
1-18
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - Reliability ot HltachllC Memories
Bonding Related Failures
DEGRADATION CAUSED BY INTERMETALLIC
FORMATION
Bonding strength degradation and contact resistance increase are caused by compounds formed,Jn
connections between Au wire and AI film. This is the
most serious problem in terms of reliability. The
compounds are formed rapidly during bonding and
are increased through thermal treatment. Consequently, Hitachi products are subjected to a lowertemperature, shorter-period bonding whenever possible.
WIRE CREEP
Wire creep is wire neck destruction in an Au ball along
an intergranular system occurring when a plastic
sealed device is subjected to a long-term thermal
cycling test. This failure results from increased crystal grains due to heat application when forming a ball
at the top of an Au wire, or from an impurity introducing to the intergranular system. Bonding under usual
conditions with no loop configuration failures does
not cause this failure unless a severe long-term
thermal cycling test is applied. Accordingly, wire
creep is not a problem in actual usage.
CHIP CRACK
With the increase in chip size associated with the
increased number of incorporated functions, more
problems can occur during assembly, such as chip
cracks during bonding. Bonding methods include Ausilicon eutectic, soldering and Ag-paste. Soldering
and Ag-paste exhibit few chip crack problems. For
Au-silicon eutectic, in contrast, large stress is applied
to a pellet due to its strength and high temperature'
resistance for attachment, which may result in critical
chip defects. Today, the chip destruction limit can be
determined by finite-element analysis and by distortion measurement using a fine accuracy gauge.
Ideally, Au-silicon eutectic should be evenly applied
over the entire surface. However, this is difficult due
to the existence of a silicon oxide film on the silicon
back surface. Therefore, specifications for Au-silicon
eutectic have been established based on stress
analysis and thermal cycling test results.
Sealing Related Failures
Hermetically sealed packages, including metal, glass,
ceramic, and all other types, have the possibility ofthe
following failures.
1. AI line corrosion on the chip surface due to slight
moisture and reaction between different ionized
materials.
2. Intermittent moving foreign metals short.
3. AI line corrosion due to extraneous H20 caused by
, hermetic failure.
Moving foreign matter, even if it is a non-active solid,
can be charged up within a cavity during movement,
thereby inducing parastic effects and metal shorts.
The for~ign matter detection method is specified by
MIL-STD-883C, PINt) (Particle Impact Noise Detection) Test. The PIND test consists offiltering a particle
impact waveform (ultrasonic waveform), detecting it
with a microphone and then amplifying it.
Disturbance
ELECTROSTATIC DISCHARGE
DESTRUCTION
Destruction caused by electrostatic discharge is a
problem common to semiconductor devices. A recent
report introduced three modes of this failure; the
human body model, charged device model and field
induced model.
The human body is easily charged. A person just
walking across a carpet can be charged up to 15000
V. This voltage is high enough to destroy a device. An
equivalent circuit of the human body model is shown
in Fig. 4. The human body's capacitance Cb and
resistance Rb are 100 to 200 pF and 1000 to 20000,
respectively. Assuming a body is charged with 2000V,
the dissipated energy is' obtained as follows: With a
time constant of 10-7 sec, the dissipated energy is 2
KW, which is enough to destroy a small area of a Chip.
REDUCED MAXIMUM POWER DISSIPATIONS
Heat fatigue due to thermal expansion coefficient
mismatch among different materials deteriorates thermal resistance, resulting in decreased maximum
power dissipations.
Cb-Human Body capacity
Rb-Human Body Aealstance
Rd-Devtce Reslstanoe
Rc -Ae8lSUVlce Between Device and Ground
E = !CbV3 _ 0_2
X
10-3J
Figure 4 Equivalent circuit 01 human body modal
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94oo5-1819· (415) 589-8300
,1-19
?
Rellabillty.of Hitachi IC.Memories - - - - - - - - - - - , . - - - - - - - - - - -
In the charged device model, charges are accumulated in a device, not a human body, and discharged
through contact resistance during a short time. The
equivalent circuit of this model is shown in Fig. 5.
Device size and device position relative to GND are
important parameters in this model since the model
depends on device cap~city.
In the field induced model, a device is left under a
strong electric field or is affected by neighboring high
voltage material. Since the capacitor of device or lead
of device acts like an antenna, the following cases will
possibly cause destruction: 1) a device is incorporated into a high electric field such as a CRT, 2) a
device is left under a high-frequency electric field and
3) a device is moved with a container charged at high
voltage, such as a tube.
Much effort should be made in designing circuits to
prevent latch-up. Latch-up triggering input or output
currents start to flow under the following conditions:
V < In Vee or Vln < GND for input level
V > out Vee orVout < GND for input level
Therefore, circuits should be designed so that no
forward current flows through the input protection
diodes or output parasitic diodes.
Soft errors
When a particles are generates from uranium or
thorium in a package the silicon surface of an LSI
chip, electron-hole pairs are formed which act as
noise to data lines and other floating modes, causing
temporary soft errors. This phenomenon is shown in
Fig. 6. Only electrons from among the electron-hole
pairs are only collected to a memory cell. As a result,
the cell changes from a state of 1 to 0, which is a soft
error.
Hitachi devices have been subjected to simulation
and irradiation tests to prevent soft errors: In some
cases, organic material, Pia, is applied to the surface
of the device.
J
Figure 5 Equivalent clrcu" of charging model
a
LATCH-UP
Latch-up is a problem unique to CMOS devices. This
problem is a thyristor phenomenon caused by a
parasitic PNP or NPN transistor formed in the CMOS
configuration. Latch-Up can occur when: 1) an accidental surge voltage exceeds the maximum rating, 2)
there is a power supply ripple, 3) an unregulated
power supply and noise is applied or 4) a device is
operated from two sources having different set-up
voltages. These cases can cause input or output
current to flow in the opposite direction from usual
flow, which triggers parasitic thyristors. This results in
excessive current flowing between a power supply
and ground. This phenomenon continues until the
power is tumed off or the flowing current reduced to a
certain level. Once latch-up occurs in an operating
device, the device will be destroyed.
Figure 6 Soft error caused by ex particles In dynamic memory
. HITACHI
1-20
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (41§) 589-8300
- - - - - - - - - - - - - - - - - - - - - - Reliability of HltachllC Memories
FINE GEOMETRY RELATED PROBLEMS
In response to higher integration requirements for
memories and microcomputers, LSI geometry has
been reduced in the way of 3 I'm ~ 2 I'm ~ 1.3 I'm
The problems associated with finer geometry are
shown in Table 2.
~O.8I'm.
Table 2 Finer geometry related problems
Item
Problems
5V single supply
• Breakdown voltage of gate oxide films
voltage
• Si02 defects
Horizontal dimension
reduction
Vertical & horizontal
dimension reduction
• Soft errors by alpha particles
• Al reliability reduced
• CMOS latch up
• Mask alignment margin reduced
• Hot carriers
• Higher breakdown voltage not pennitted
• Electrostatic discharge resistance reduced
D
Countenneasure
Oxide film fonnation process
improved
• Cleaning
• Gettering
• Screening
Surface passivation film improved
• Metallization improved
• Design/layout improved
• Process improved
Use of low voltage examined
• Configuration improved
• Protection circuits enhanced
HITACHI
Hitachi America, Ltd.' 2000 Sierra 'Point Pkwy.· Brisbane, CA94005-1819' (415) 589-8300
1-21
• QUALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Hitachi basic views on quality are to meet individual
users' purpose and required quality level and maintain that level for general application. Hitachi has
made efforts to assure the standardized reliability of
our IC memories in actual usage. To meet users'
requests and to cover expanding application, Hitachi
perform.s the followings:
(1) Design reliability in during new product development.
(2) Establish quality at all steps in the manufacturing
process.
(3) Intensify th~ inspection and the assurance of
reliability of all products.
(4) Improve the product quality based on marketing
data.
Furthermore, to get higher quality and reliability, we
cooperate with our research laboratories.
With the views and methods mentioned above, Hitachi
makes the best efforts to meet the users' requirements.
2. RELIABILITY DESIGN OF SEMICONDUCTOR
DEVICES
2.1 Reliability Target
,
Establishments of reliability target is important in
manufacturing and marketing as well as function and
price. It is not practical to determine the reliability
target based on the failure rate under Single common
test condition. So, the reliability target is determined
based on many factors such as each characteristics
of equipment, reliability target of system, derating
applied in design, operating condition and maintenance.
2.2 Reliability Design
Timely study and execution are essential to achieve
reliability based on targets. The main items are the
design standardization, device design including process and structural deSign, design review and reliability test.
(1) Design Standardization
Design standardization requires establishing design rules and standardizing parts, material, and
process. When design rules are established on
circuit, cell, and layout design, critical items
about quality and reliability should be examined.
Therefore, in using standardized process or
material, even newly developed products would
have high reliability.
(2) Device Design
It is important for device design to consider total
balance of process design, structure deSign,
circuit and layout design. Especially in case of
applying new process or new material, we study
the technology prior to development of the device in detail.
(3) Reliability Test by Test Pattern
Test Pattern is useful method for evaluating
reliability of designing and processing lOs with
complicated functions.
1. Purposes of Test Patterns are as follows:
• Making clear about fundamental failure mode:
• Analysis of relation betw.een failure mode and
manufacturing process condition.
• Analysis of failure mechanism.
• Establishment of QC point in manufacturing.
2. Effects of evaluation by Test Patterns are as
follows:
• Common fundamental failure mode and failure
mechanism in devices can be evaluated.
• Factors dominating failure mode can be picked
up, and compared with the process having been
experienced in field.
• Able to analyze relation between failure causes
and manufacturing factors.
• Easy to run tests.
2.3 Design Review
Design review is a method to confirm systematically
whether or not design satisfies the performance required including by users, follows the specified ways,
and whether or not the technical items accumulated
in test data and application data are effectively applied.
In addition, from the standpoint of competition with
other products, the major purpose of design review is
to insure quality and reliability of the product. In
Hitachi, design review is performed in designing new
products and also in changing products.
The followings are the items to consider at design
review.
(1) Describe the products based on specified design
documents.
(2) ConSidering the documents from the standpoint
of each participant, plan and execute the subprogram such as calculation, experiments and
investigation if unclear matter is found.
(3) Determine the contents and methods of reliability test based on design document and drawing.
(4) . Check process ability of manufacturing line to
achieve design goal.
HITACHI
1-22
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - Quality Assurance of IC Memory
(5) Arrange the preparation for production.
(6) Plan and execute the sub-programs of design
changes proposed by individual specialists, for
tests, experiments and calculation to confirm the
design change.
(7) Refer to the past failure experiences with similar
devices, confirm the prevention against them,
and plan and execute the test program for confirmation of them.
In Hitachi, these study and decision at design review
are made using the individual check lists according to
its objects.
3. QUALITY ASSURANCE SYSTEM OF
SEMICONDUCTOR DEVICES
3.1 Activity of Quality Assurance
The following items are the general views of overall
quality assurance in Hitachi.
(1) Problems is solved in each process so that even
the potential failure factors will be removed at
final stage of production.
(2) Feedback of information is made to insure-satisfied level of process ability.
At the result, we assure the reliability.
Step
Contents
I!arget
I
SoecHlcallon
Design Review
I
Materials, Parts
eslgn
w
I~,~nn
A~~roval
Purpose
Ir-
Characteristics of Material and Parts
Appearance
Dimension
Heat ReSistance
Mechanical
Electrical
Others
Confirmation of
Characteristics and Rellabllty of
Materials and Parts
Electrical
Characteristics
Function
Voltage
Current
Temperature
Others
Appearance, Dimension
Confirmation of Target
Spec. Mainly about
Electrical
Characteristics
Reliability Test
LHe Test
Thermal Stress
Moisture Resistance
Mechanical Stress
Others
Confirmation 01 Quality
and Reliability In Design
Reliability Test
Process Check same as
Quality Approval (1)
Confirmation of Quality
and Reliability In Mass
Production
II
Characteristics Approval
I~
II
Quality Approval (1)
I~
II
Quality Approval (2)
I~
ass
W
Production I
Figure 1 Flow Chart of QualHlcatl0n3.2
HITACHI
Hitachi America, Ltd.• 2000 Sierra 'Point Pkwy., Brisbane, CA 94005-1819 • (415) 589-8300
1-23
D
Quality Assurance of IC Memory ----------------~-......- - - -
3.2 Qualification
To assure the quality and reliability, the qualification
tests are done at each stage of trial production and
mass production based on the reliability design described in section 2.
The followings are the views on qualification in Hitachi:
(1) From the standpoint of customers, qualify the
products objectively by a third party.
(2) Consider the failure experiences and data from
customers.
(3) Qualify every change in deSign and work.
(4) Qualify intensively on parts and materials and
process.
(5) Considering the process ability and factor of
manufacturing fluctuation, establish the control
points in mass production.
Consider the views mentioned above, qualification
shown in Fig. 1 is done.
Quality Control
Process
Material
Parts
Inspection on Material and
Parts for Semiconductor
Devices
Method
---
Manufacturing Equipment,
Environment, Sub-material,
Worker Control
-
Confirmation of
Quality Level
-
Lot Sampling,
Confirmation of
Quality Level
100% Inspection on
Appearance and Electrical
Characteristics
-
Testing,
Inspection
Sampling Inspection on
Appearance and Electrical
Characteristics
-
Inner Process
Quality Control
-----
Lot Sampling,
Confirmation of
Quality Level
Reliability Test
r----------.
Quality Information
1
1
1
Claim
1
Field Experience
General Quality
1
1
l_ ~fOrmatiO~ _ _ _ _I
-
Lot Sampling
Confirmation of
Quality Level, Lot
Sampling
Feedback of
Information
Figure 2 Flow Chart of Qualhy Control In Manufacturing Process
H,TACHI
1-24
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - Q u a l i t y Assurance of IC Memory
3.3 Quality and Reliability Control In Mass
Production
To assure quality in mass production, quality is controlled functionally by each department, mainly by
manufacturing department and quality assuran~e
department. The total function flow is shown in Fig. 2.
3.3.1 Quality Control on Parts and Materials
With the tendency toward higher performance and
higher reliability of devices, quality control of parts
and materials becomes more important. The items
such as crystal, lead frame, fine wire for wire bonding,
package and materials required in manufacturing
process like mask pattern and chemicals, are all
subject to inspection and control.
Besides qualification of parts and materials stated in
3.2, quality control of parts and materials is defined in
incoming inspection. Incoming inspection is performed
based on its purchase specification, drawing and
mainly sampling test based on MIL-STO-10S0.
The other activities for quality assurance are as
follows:
• Table 1. Quality Control Check Points of Parts and Materials
(example)
Material,
Parts
Important
Conlrol Items
Appearance
Wafer
Mask
Fine
Wire for
Wire
Bonding
Frame
Ceramic
Package
Plastic
Dimension
Sheet Resistance
Defect Density
Crystal Axis
Appearance
Dimension
Resistoration
Point for Check
Damage & Contamination
on Surface
Flatness
Resistance
Defect Numbers
Defect Numbers, Scratch
Dimension Level
Gradation
Uniformity of Gradation
Appearance
Contamination, Scratch, Bend,
Twist
Dimension
Purity
Elongation Ratio
Appearance
Dimension
Processing
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Accuracy
Plating
Mounting
Characteristics
Bondability. Solderability
Heat Resistance
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrical
Characteristics
Contamination, Scratch
Dimension Level
Airtightness
Bondability, Solderability
Heat Resistance
~:~a;1.cal
Mechanical Strength
Composition
Characteristics of
Plastic Material
Electrical
Characteristics '
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics
Molding Performance
(1) Technology Meeting with Vendors
(2) Approval and Guidance of Vendors
(3) Analysis and tests of physical chemistry.
The typical check points of parts and materials are
shown in Table 1.
3.3.2 Inner Process Quality Control
To control inner process quality is very significant for
quality assurance of devices. The quality control of
products in every stage of production is explained
below. Fig. 3 shows inner process quality control.
(1) Quality Control of Products in Every Stage of
Production
Potential failure factors of devices should be removed
in manufacturing proces.s. Therefore, check points
are set up in each process so as not to move the
products with failure factors to the next process.
Especially, for high reliability devices, manufacturing
lines are rigidly selected in order to control the quality
in process. Additionally we perform rigid check per
process or per lot, 100% inspection in proper processes so as to remove failure factors caused' by
manufacturing fluctuation, and screenings depending on high temperature aging ortemperature cycling.
Contents of controlling quality under processing are
as follows:
• Control of conditions of equipmenrand workers and
sampling test of uncompleted products.
• Proposal and execution of working improvement.
• Education of workers
• Maintenance and improvement of yield
• Picking up of quality problems and execution of
countermeasures toward them.
• Communication of quality information.
(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing facilities have been developed with
the need of higher devices in performance and the
automated production. It is also important to determine quality and reliability.
In Hitachi, automated manufacturing is promoted to
avoid manufacturing fluctuation, and the operation of
high performance equipment is controlled to function
properly.
As for maintenance inspection for quality contrOl,
daily and periodically inspections are performed based
on specification on every check point.
As for adjustment and maintenance of measuring
eqUipment, the past data and specifications are clearly
checked to keep and improve qu~lity.
Mounting Characteristics
HITACHI
Hitachi America, Ltd .• 2000 Sierra 'Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
1-25
Quality Assurance of IC Memory ----------------------~
(3) Quality Control of Manufacturing Circumstances
and Sub-material.
Quality and reliability of devices are affected
especially by manufacturing process. Therefore, we thoroughly control the manufacturing
circumstances such as temperature, humidity,
dust, and the sub-materials like gas or pure
water used in manufacturing process.
Process
Control Point
T" Purchase of Material
Wafer
Wafer_
<> Surface Oxidation
Characteristics, Appearance
Oxidation
Inspection on Surface
Oxidation
Photo Resist
Appearance, Thickness of
Oxide Film
Photo
Resist
Inspection on Photo Resist
~PQC Level Check
Diffusion
Diffusion
Inspection on Diffusion
OPQC Level Check
c Evaporation
(
Dust control is essential to realize higher integration and higher reliability of devices. To maintain
and improve the clearness of manufacturing site,
we take care buildings, facilities, air-conditioning
system, materials, clothes and works. Moreover,
we periodically check on floating dust in the air,
fallen dust or dirtiness on floor.
Inspection on Evaporation
~PQC Level Check
Wafer Inspection
Dimension, Appearance
Diffusion Depth, Sheet
Resistance
Gate Width
Characteristics of Oxide Film,
Breakdown Voltage
Purpose of Control
Scratch, Removal of Crystal
Defect Wafer
Assurance of Resistance
Pinhole, Scratch
Dimension Level
Check of Photo Resist
Diffusion Status
Control of Basic Parameters
(VTH' etc) Cleaness of surface
Prior Check of V1H
Breakdown Voltage Check
Assurance of Standard
Thickness
Evaporation
Thickness of Vapor Film
Scratch, Contamination
Wafer
Thickness, VTH Characteristics Prevention of Crack,
Quality Assurance of Scribe
Electrical Characteristics
Inspection on Chip
Electrical Characteristics
Chip Scribe
Inspection on Chip
Appearance
oPQC Lot Judgement
Chip
Assembling
Assembling
Appearance of Chip
Bonding
Appearance after Wire
Bonding
Pull Strength, Compression
Width, Shear Strength
Appearance after Assembling
Sealing
Sealing
oPQC Level Check
Final Electrical Inspection
Failure Analysis
Marking
Appearance after Sealing
Outline, Dimension
Marking Strength
Guarantee of Appearance
and Dimension
Analysis of Failures, Failure
Mode, Mechanism
Feedback of Analysis Information
Appearance of Chip
Frame ...
~PQC
Level Check
Inspection after
Assembling
OPQC Lot Judgement
lpackage.-
,Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short
Appearance Inspection
II-Sampiing Inspection on
Products
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
HITACHI
1-26
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - Quality Assurance of Ie Memory
3.3.3 FInal Test and Reliability Assurance
The inspection is executed not only to confirm
that the products me.et users requirement, but to
consider potential factors. Our lot inspection is
based on MIL-STO-10S0.
(2) Reliability Assurance Tests
To assure reliability, the reliability tests are performed periodically, and performed on each
manufacturing lot if user requires.
(1) Final Tests
Lot inspection is done by quality assurance department for the product passed in 100% test in
final manufacturing process. Though 100% of
passed products is expected, sampling inspection is subjected to prevent mixture of failed
products by mistake.
I
I
Customer
Claim
(Failures, Information)
Dept.
I
I Sales
Sales Engineering Dept.
-----------~-----------------~
I Quality Assurance Dept. I
I
I Manufacturing Dept.J
f
L
I
I
Failure Analysis
Report
1
Design Dept.
~
Quality Assurance Dept.
~
Report
Countermeasure
Execution of
Countermeasure
FOllow-up and Confirmation
of Countermeasure Execution
'
~-----------------~
I
Sales Engineering Dept.
I
Reply
I
Customer
I
Figure 4 Process Flow Chart of Coping with Failure to iI Customer
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1-27
1
• OUTLINE OF TESTING METHOD
1. INSPECTION METHOD
2. MARCHING PATTERN
In memory IC inspection, quality cannot be judged by
DC test on external pins only, because the number of
elements (such as a transistor) which can be judged
in the DC test is only 111000 of all elements. The
following are the address patterns proposed to inspect whether the internal circuits are functioning
correctly.
(1) All "Low·, All "High"
(2) Checker Flag
(3) Stripe Pattern
(4) Marching Pattern
.(5) Galloping
(6) Waling
(7) Ping-Pong
Those are not all, but representative ones. There are
also patterns to che~k the mutual interference of bits
and patterns fot maximum power dissipation. Among
the above mentioned patterns, numbers 1 to 4 are
called N pattern, which can check one sequence of N
bit IC memory with the several times of N patterns at
most. Numbers 5 to 7 are called N2 patterns, which
need several times of N2 patterns to check one
sequence of N bit IC memory. Serious problem arises
in using N2 pattern in a large-capacity memory. For
example, inspection of 16K memory with galloping
pattern takes a lot of time-about 30 minutes. (1), (2)
and (3) are rather simple and good methods, however, they are not perfect to find any failure in decoder
circuits. Marching is the most simple and necessary
pattern to check the function of IC memories.
The marching pattern, as its name indicates, is a
pattern in which "1"s march into all bits of "O"s. For
example, a simple addressing of 16 bit memory is
described below.
(1) Clear all bits. See Fig. 1 (a).
(2) Read "0" from Oth address and check that the
read data is "0·. Hereafter, "Read" means "cbecking and judging data"
(3) Write "1" on Oth address. See Fig. 1 (b).
(4) Read "0" from 1staddress.
(5) Write "1" on 1st address .
(6) Read "0" from nth address.
(7) Write "1" on nth address. See Fig. 1 (c).
(8) Repeat (6) to (7) to the last address. Finally, all
data will be "1".
(9) After all data is "1", repeat from (2) to (8) replacing "0" and "1".
With this method, 5N address patterns are necessary
for the N-bit memory.
a
c
b
o
0
0
0
1
0
0
0
1
1
1
o
0
0
0
o
0
0
0
1
1
1
o
0
0
0
o
0
0
0
1
1
0
0
o
0
0
0
o
0
0
0
o
0
0
0
Figure 1 Addressing method offor 16bltmemory in the Marching
pattem
HITACHI
1-28
1
HitachiAmerica, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
• APPLICATION
1. EEPROM
1.1 EEPROM Memory Cell
An EEPROM is an electrically erasable and programmable ROM which can be erased or written remotely
while the system is in operation.
Hitachi EEPROM memory cells are MNOS-type (Metal
Nitride Oxide Semiconductor) as shown in Figure 1-1.
A MNOS memory cell consists of two layers of oxide
film and nitride film. The thickness of the oxide film is
about 20 Aand the nitride film is 300 to 500 A. There
are traps in the boundary of the oxide and nitride films
to catch electrons. The electrons move by the tunneling phenomenon between the substrate and traps.
1.2 64-kblt CMOS EEPROM Function
Page Write Function: The 64-kbit HN58C65 can
latch 32 bytes (max.) and write them in one write
cycle. The write cycle time is specified as 10 ms
(max.) The effective byte write speed of HN58C65 in
page write mode is 10 ms/32 bytes = 0.31 mslbyte.
Thus it takes only 2.56 seconds to write the entire
HN58C65. Figure 1.2 shows the internal operation.
The following describes the operation sequence:
1. The 32-byte memory cell data at the row address
selected by address pins A5-A12 are latched.
2. Latched data at the column address specified by
address pins Ar,-A4 are altered with write data, which
is put into the Din buffer from va pins 1/00-1/07•
The 32 bytes (max.) of latched data are altered by
repeating this operation 32 times.
3. 32 bytes of memory cell data in the selected row
1 are erased (all set to 1).
4. Latched data is written into the selected row 3.
5. CPU acknowledges completion of the write cycle
based on the intemal timer. The HN58C65 provides RDYIBUSY and DATA polling to indicate
the write completion.
Internal Timer: The HN!;i8C65 indicates the completion of a data write to the CPU by using an internal
timer. The HN58C65 enters the next cycle as soon as
the completion of the write is detected. This function
offers a high system throughput as the CPU can
access other devices during a write cycle. The
HN58C65 has two functions, RDY/BUSY and DATA
polling, to indicate the completion of data write.
The RDY/BUSYapproach indicates the completion of
data write by using pin 1. It is low when the HN58C65
is in data write operation (BUSY) and turns to the high
impedance state at the end of data write (RDY). The
RDY/BUSY pin should be pulled up as it uses open
drain output. The RDYIBUSY pins can be OR-wired
when using several HN58C65's.
The DATA polling approach, implemented in software, indicates the completion of data write through
pin 19 (1/07 ). While the data write is not completed,
1/07 shows an inverted version of what was written in
the last cycle. In using this approach, the RDY/BUSY
pin should be opened or grounded. The DATA polling
approach can acknowledge the completion of a data
write in an individual HN58C65, even if several
HN58C65's are used in the system.
Data ProtectIon: The EEPROM perforins a data write
with a highervol!age (Vpp) than the power supply voltage
(Vcc>. The HN58C65 internally generates Vpp by a high
vo~~rator with the combination of control pins
(CE,OE, WE).ltsuppo~thefollowingfunctionstoavoid
accidental data write (data protection).
1. Data ~tection against noise on the control pins
(CE, OE, WE) during operation.
2. Data protection against noise at power on/off.
MNOS memory coil
/SIO:1
P-W811
N Substrate
Figure 1·2 HN58C65 Psgs Writs
Figure 1·1 MHOS-Type Memory Transistor
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94oo5-1819· (415) 589-8300
1-29
1
Application - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2. EPROMIOTPROM
2.1 EPROM Programming
Figure 2-1 shows the sectional structure of an EPROM
memory cell. The upper gate, one of the gates made of
two-layered polycrystalline silicon, is called the control
gate and is connected to a word line. The lower layer is
called the floating gate and is not connected. This memory
cell is programmed as follows.
Si02
VIZ//71Z(
~
\J ---- --
Sour~
the necessary information. The higher the Vpp voltage
and the longer the program pulse width tpw , the more
electrons can be programmed in as shown in Figure
2-3. If Vpp exceeds the rated value, such as by
overshoot, the pn junction of the memory may yield to
permanent breakdown. To avoid this, check Vpp overshoot of the PROM programmer. Also, check negative-voltage-induced noise at other terminals, which
10
Control Gate
v?2ZI?A/FloatingGate
/Draln
N+
Figure 2·1 Cross Section of a EPROM Memory Cell
With the substrate and source grounded, apply a high
voltage between the drain and control gate. An electrical potential incline will occur between the source
and drain so that the intensity of the electric field will
become high near the drain. Because of this electric
field, electrons are accelerated and the so-called hot
electrons will be generated, which jump over the
energy barrier of Si02 film. The hot electrons are
pulled by the electric potential of the control gate and
poured into the floating gate. Electrons stored in the
floating gate remain stable as they fall into a well
surrounded by an energy barrier of Si02 film. Therefore, it is evident that the quality of the Si02 film
surrounding the floating gate is essential for good
data retention characteristics. To keep data retention
in the 5- or 10-year range, high quality Si02 film is
needed.
Figure 2-2 shows the fundamental characteristics of the
EPROM transistor. While 10 in a non-programmed transistor begins to flow with VG of about 1 V, the current in a
programmed transistor does not flow until VG rises to 7 to
10 V. Therefore, if the voltage of the word line applied to
the control gate is about 5 V in the readout, a nonprogrammed memory transistor will be on, and the
programmed memory transistor will be off. This means
that the data can be read out by means of the same
structure as a NOR-type mask ROM.
2.2 Erasing EPROM
When shipped, all bits of the EPROM are at logic 1
with all electrons in the floating gate released (erased).
Changing the logic 1 to logic 0, through the application of the specified waveform and voltage, programs
' - - " " " ' - - - - - - - - - ' ' - - - - - - VG
Figure 2-2 Fundamental Characteristics of a EPROM
Memory Cell
can create a parasitic transistor effect and reduce the
yield voltage. Hitachi's EPROMS can usually be written and erased more than 100 times.
EPROMS are erased by ultraviolet light exposure
through a transparent window on the package. Electrons in the floating gate get energy from photons and
become hot electrons again with enough energy to go
over the energy barrier of Si02 film. The hot electrons
go through to the control gate or the substrate and
erasure is completed. Therefore, light with enough
energy to get the electrons over the energy barrier of
Si02 film is needed for erasure. Light energy is proportional to its frequency, and described as E '" hu. E
is the energy of light, h is Planck's constant, and u is
light frequency. Erasure is not caused by light o~er
certain wavelengths and under certain wavelengths.
However, the erasure time depends upon the quantity
of photons, therefore the erasure time cannot be
HITACHI
1-30
Hitachi America,
ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Application
8
Figure 2-5 shows the EPROM standard erasure
characteristics.
Programming Conditions:
Vcc=6.0V,
Vpp=12.5V
10
Figure 2-3 Standard Programming Characterlatlcs of EPROMs
2.3 EPROM Data Retention Characteristics
About 2 to 20 x 10-14 coulombs of electrons are
accumulated in the floating gate when programmed.
However, these electrons dissipate with time and the
data may be inverted. The mechanism of electron
dissipation is generally explained as follows.
Data Dissipation by Heat: The electrons at the
floating gate are in a non-equilibrium state, so the
dissipation of electrons by thermal energy is unavoidable. Therefore, the data retention time depends on
temperature. Figure 2-6 shows typical data retention
characteristics. The data retention time is proportional to the reciprocal of absolute temperature.
shortened by using a shorter wavelength. Figure 2-4
shows the relation between wavelength and erasure
effectiveness. Erasure starts at about 4000 Aand is
saturated at about 3000 A.
For erasure, the wavelength and minimum irradiation
rate of ultraviolet light must be 2537 A. and 15 W-sl
cm2 respectively. These conditions can be met by
placing the device 2 to 3 cm below a 12,000 W/cm 2 UV
lamp for about 20 minutes.
The UV transmittance of the transparent lid materials
is about 70%. However, it is influenced by contamination or foreign materials on the lid surface. The contamination or foreign materials should be removed
with a solvent such as alcohol that does not damage
the package.
9
\
\
/
V
\I
\
/
,\/ /
2 3
4 5
W-Irradiation /YtI- sec/cm2)
Figure 2-5 Standard Erasure Characteristics
v
107
V
1! 106
t
Ii 10
/
105
4
103
/
V
Stored Temperature (0C)
Figure 2-6 EPROM Data Retention Characteristics
Wavelength
Figure 2-4 Erasure Efficiency of EPROM
Data Dissipation by Ultraviolet Light: Ultraviolet
light at a wavelength no greater than 3000 to 4000 A
is capable of releasing the electric charge at the
floating gate of the EPROM with varying efficiencies.
Fluorescent light and sunlight contain some ultraviolet light, and so prolonged exposure to these lights
can cause data corruption as a result of electric
charge dissipation. Figure 2-7 shows the standard
data retention time under an ultra-violet eraser, sunlight, and fluorescent lighting.
HITACHI
Hitachi America, Ltd. - 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300
1-31
o
Application - - - - - - - - - - - - - - - - - - - - - - - - - - 10"
4f1N ftourescent
.m~
10"/
1i 10"
Direct sunlight
i1Q3~
.§
li
)10"
Figure 2·7 EPROM Data Retention Time
2.4 Optimized High Speed Programming
With the increase of EPROM density, the time for
programming becomes more important. Methods for
high speed programming have been developec;l and
put into practical use for each EPROM generation.
There are three methods for high speed programming.
Figure 2·8 shows the relative programming times of
these methods.
, Please refer to the data sheet about each program·
ming method.
2.5 Device identifier Code
EPROMprogrammingconditionsdependonthe EPROM
manufacturers' standards and specific device types.
Confusion on the properuseofvarying methods required
may cause poor or faiting operation. As a countenneasure, some EPROMSprovide embedded device identifiercodes including such infonnation asthe manufacturer
and device type. Some newly developed commercial
EPROM programmers can set write conditions automatically by recognizing this code.
Different programming conditions are as follows.
1. Program voltage
2. Program timing
3. High perfonnance programming algorithm
4. Pin configuration
The Hitachi EPROM has a device identifier code area
adjacent to the· memory access area as shown in
Figure 2-9.
Table 2-1 describes how to use the device identifier
code. Setting Ag at 12 V and A,-Ag and A,o-A'3 at VIL ,
access the device identifier code area and 11°0-11°7,
and output the programming condition code with VIL
orVIH of Ag.
·2.6 Shielding Label
When using an EPROM in.ari environment where it
can be exposed to ultraviolet light, Hitachi recommends placing a shield label, over the transparent lid
to absorb the ultraviolet light. In choosing a ,shielding
label, the following points should be carefully checked.
,
,,,
,
_ 50me programming
10
1mB High-speed •
progranvning "
Page mode
1
programming
0.2mB Hlg~-speed
2
programming
~~
O~~--~--~--~--~~~--~--~~
~~
~
Storage capacity ( x 8 orgenlzation)
(bit)
Note: Actual programing time differs depe~ding on the programmar.
Figure 2-8 ComparilOll of ShorieneCI Progremmlng TIme
HITACHI
1-32
HilachiAmerica, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589·8300
----------------------------Appllcatlon
rr====~~~~~~~~..- Device identifier code area
Address~
Data access area
Figure 2-9 Device Identifier Code
1. Adhesiveness (mechanical strength)
Avoid repeated removal and reattachments, or
exposure to dust that may reduce the adhesive
strength. Ultraviolet erasure and reprogramming
are recommended after stripping off an attached
label. (When the need arises to change a label, it
is advisable to place a new one over the old one
since peeling may create a static charge.)
2. Allowable temperature range
Use the shielding label in an environment where
temperature is stable within the specified allowable temperature range. Beyond the specified
temperature range, the paste on the label may
harden or stick too tightly. When it hardens, the
label may come off easily. When it sticks too
tightly, the paste may remain on the window glass
after the label has been removed.
3. Moisture resistance
Use the shielding label in an environment where
humidity is stable within the specified allowable
humidity range.
2.7 EPROM Programmer
The EPROM programmer stores the user's program
in its internal RAM and writes the program in the
EPROM. For this programming, at least three functions are necessary: the blank check function prior to
programming, programming function, andverifyfunction after programming. Figure 2-10 shows the programming flowchart. Some programmers check for
pin contact failure or reverse insertion before the
blank check.
The outline of each check is a follows.
1. Pin contact check
In the ROM pin and socket connection test, checking is normally performed by detecting forward
current at each EPROM pili. Care is necessary as
this forward biased resistance differs in products
of each company.
2. Reverse insertion check
This check detects the reverse insertion of the
device, then places the equipment in reset mode
and protects the device and equipment if the
condition is found.
Table 2-1 Hitachi EPROM Device Identifier Code
1/°2
V'H
-
0
0
0
0
0
1
11O,
1
V",
VIR
Vm
VIR
VIH
Viii
V'H
Vm
Vrn
VIH
-
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
Ao 11°8-11°'5
Hitchi
Manufacturer
Code
ROM code
HN27128A
HN27256
HN27C256
HN27C256H
HN27C256A
HN27512
HN27C1024H
HN27C101A
HN27C301A
HN27C4096
-
-
-
1/°7 11°6
1/°5 110. 11°3
11°0 Hex Data
1 07
1
0
0
1
1
0
0
0
1
0
00
10
BO
31
31
94
BA
38
B9
A2
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
1-33
Application - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3. Blank check
This check is performed before programming. It
checks whether the device is an erased EPROM,
or it prevents EPROM reprogramming. Since output data in the erased condition is high, the check
is for whether the data in the EPROM are all 1s. It
will fail even if one bit is O. Normally, it is designed
to provide a warning with a lamp or buzzer.
4. Programming
The function of programming the data from the
internal RAM of the programmer into the EPROM
will fail when programming cannot be done. The
normal flow is as shown in Figure 2-11. The
EPROM data for a target location will be read out
prior to programming and compared with the programming data intended for that location. If the
data matches, programming will be skipped. If
they differ, programming will be performed. Then,
the data will be read back and compared with the
original programming data, and if they match, the
programmer will progress to the next address.
5. Verify
This function checks after programming completion whether or not the programming is correct
when comparing with the data in the internal RAM
of the programmer. It will fail when they do not
match. Normally, when it fails, it lights the fail lamp
and displays the address and data.
6. How to input a program
Table 2-2 shows several methods for inputting the
program data to the internal RAM of the programmer. Normally, papertape input and teletypewriter
input are preferred options.
2.8 Handling EPROMs
If touched by a charged human body or rubbed with
plastics or dry cloth, the glass window of an EPROM
generates static electricity with causes device malTable 2·2 EPROM Data Input
Method
Copy input
Content
Input by copying the master ROM.
Manual input
Input by the keyswitches on the
front pannel. Used for correction
or revision of programs.
Paper tape input
Paper tape furnished from the
host system is read with the tape
reader.
Teletypewriter
input
Input with the teletypewriter.
Preparation, correction, and list
preparation of the program can
be made.
,
,
( ' Check Pin ',.
,
, Contact
,
Figure 2-10 Programming
Flowchart of EPROM
Programmer (1)
Figure 2-11 Programming
Flowchart of EPROM
Programmer (2)
functions. Typical malfunctions are faulty blanking
and write margin setting that give the false impression
that information has been correctly written in. As
already reported at international conferences concerning the reliability of LSI chips, this is due to the
prolonged retention of electric charge (resulting from
static electricity) on the glass window. Such malfunctions can be eliminated by neutralizing the charges by
irradiating the EPROM with ultraviolet rays for a short
time. The EPROM should be reprogrammed after this
irradiation since it also reduces the electric charges in
the floating gates. The basic countermeasure is to
prevent the charging of the window, which can be
achieved by the following methods, as in the prevention of common static breakdown of les.
1. Ground operators who handle the EPROM.
Avoid using things such as gloves that may generate static electricity.
2. Avoid rubbing the glass window with plastic or other
materials that may generate static electricity.
3. Avoid the use of coolant sprays which may contain some free ions.
4. Use shielding labels (especially those containing
conductive substances) that can evenly distribute
any established charge.
HITACHI
1-34
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Application
2.9
Ensuring OTPROM Reliability
The one-time-programmable ROM (OTPROM) has
two forms: standard dual in-line package (DIP) and
small outline package (SOP). It is only one-time
programmable ~ause it has no window for ultraviolet light exposure; testing by programming and erasure cannot be performed after it is assembled.
As a means of improving reliability, Hitachi performs
screening tests for programming, access time, and
data retention on OTPROM wafers during the manufacturing process.
However, rare defects may occur in the assembly
proCess that cannot be completely removed in the
final test screening which is only a reading test.
Therefore, Hitachi recommends that users perform
high temperature baking after programming these
devices to ensure the highest reliability.
Detailed conditions and procedures for screening are
s!1own in Figure 2-12. First, program and verify the
devices. Then leave them without bias at 125 to
150°C for 24 to 48 hours.
After that, check the readout function, and discard
chips with data retention failures.
From the results of devices in which the recommended screening test is properly performed, we find
the data retention characteristics of OTPROMs are
generally equal to EPROMs.
3. Mask ROM Programming Instruction
The writing of custom program code into mask ROMs
is performed by a CAD system on a large-scale
computer. ROM code data should conform to the
specifications given below, using either EPROM or
floppy disk. Additional instructions, such as chip
select or customer part numbers, should be noted on
the "ROM ~pecification Identification Sheet."
Programming,
Reading-Out
Data
Retention
D
Wafer Screening
Program and
Verify
by Programmer
Baking at
125 to 150°C
for 24 to 48hrs
I
Ensuring
Read-out
~
Recommended
Screening Conditions
Figure 2·12 Sc_nlng Flowchart of OTPROM
HITACHI
Hitachi America, Ltd.• 2000 SiEm8 Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
1-35
Application - - - - - - - - - - - - - - - - - - - - - - - - - - - Customer
ROM
Code
Ust
Hitachi
''Customer
Part Numbe('
Chip Select
rd()t!1e~
OK
/
Sample
@
OK
Figure 3-1 Mask ROM Development Flowchart
HITACHI
1-36
HitachiAmerica, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
NONVOLATILE MEMORY DATA BOOK
DATA SHEETS
Section Two
EEPROM
HITACHI
HN58C65 Series
64K (SK x 8-blt) EEPROM
•
DESCRIPTION
The Hitachi HN58C65 is a 64-Kilobit CMOS Electrically Erasable
Programmable R.ead Only Memory (EEPROM) organized as 8,192
x 8-bits. The HN58C65 is capable of in-system electrical Byte and
Page reprogrammability.
The HN58C65 achieves high speed access, low power
consumption, and a high level of reliability by employing advanced
MNOS memory technology and CMOS process and circuitry
technology.
The HN58C65 has a 32-Byte Page Programming function to
make its erase and write 0.E!.rations faster. The HN58C65 features
Data Polling and a Re~dy/Busy signal to indicate completion of erase
and programming operations.
The HN58C65 provides several levels of data protection.
Hardware data protection is provided noise protection on the WE
signal and write inhibit on power on and off.
The HN58C65 is designed for high reliability in the most
demanding applications. Data retention is specified for 10 years and
eraselwrite endurance is guaranteed to a minimum of 100,000
cycles in the Page Mode.
The HN58C65 is offered in JEDEC-Standard Byte-Wide EEPROM
pinouts in 28-pin Plastic DIP and 28-lead Plastic SOP packages.
•
(DP-28)
II
(FP-28DA)
FEATURES
• Single Power Supply:
Vcc =5V±10%
• Fast Access Time:
250 ns (max)
• Low Power Dissipation:
Active Current: 20 mWIMHz (typ)
Standby Current: 2 mW (max)
• Automatic Programming:
Automatic Page Write: 10 ms (max)
32 Byte Page Size
Automatic Byte Write: 10 ms (max)
• Data Polling and ReadylBusy Signals
• Data Protection Circuitry on Power On/Off
• Data Retention: 10 years
• EraselWrite Endurance:
100,000 cycles in Page Mode
• Pinouts:
JEDEC Standard Byte-Wide EEPROM
• Packages:
28-pin Plastic DIP
28-lead Plastic SOP
HITACHI
Hitachi America, ltd.· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 .
2-1
HN68C66 Series
•
ORDERING INFORMATION
Type No.
HN58C65P-25
Access Time
250ns
HN58C65FP-25
250ns
•
Package
28-pin Plastic DIP
(DP-28)
32-lead Plastic SOP
(FP""28DA)
PIN ARRANGEMENT
•
HN58C65P Series
HN58C65FP Series
PIN DESCRIPTION
Pin Name
Function
Ao - A12
Address
1/00 -1/07
Input/Output
ROY/Busy
Vee
OE
Output Enable
A12
A7
WE
NC
CE
Chip Enable
AS
AS
AS
A4
A3
A2
A1
AO
1/00
.1/01
1/02
Vss
28·PIN
DIP
28-LEAD
SOP
TOP VIEW
WE
Write Enable
A9
A11
Vee
Power Supply
Vss
Ground
DE
RdylBusy
ReadylBusy
NC
No Connection
A10
CE
1/07
1/06
1/05
1L04
1/03
(PinD28.HN58C65)
HITACHI
2-2
l::Iitachi America. Ltd. - 2000 Sierra Point Pkwy.- Brisbane. CA94005-1819 ~ (415) 589-8300
HN58C85 Series
•
BLOCK DIAGRAM
VVCCss
__
0
- _~ High Voltage Generator
o~:L
IlOO -
1107
Ready/Busy
----J
110 Buffer
and
Input Latch
Control logic and Timing
AO
'! Decoder.
fJ
A4
Address
Buffer and
latCh
X Decoder
Memory Array
AS
I
A12
Data Latch
(BD.HN58C65)
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-3
HN58C65 Series
•
MODE SELECTION
Mode .
CE
OE
WE
ROY/Busy
I/O
VIL
VIL
VIH
High-Z
Dour
Standby
VIH
X
X
High.Z
High-Z
Write
VIL
VIi!
VIL
High-Z"VOL
Deselect
VIL
VIH
VIH
High-Z
DIN
High-Z
X
X
VIH
-
-
X
VIL
X
-
-
VIL
VIL
VIH
VOL
Data Out (1/07)
,
Read
Write Inhibit
Data Polling
Note:
•
1.
X = Don't Care
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage 1
Input Voltage 1
Operating Temperature Range 3
Storage Temperature Range
Notes:
•
1.
2.
3.
Symbol
Value
Unit
Vee
-0.6 to +7.0
V
VIN
-0.52
to +7.0
V
TOPR
Oto+70
°C
TSTG
-55 to +125
°C
Relative to Vss'
VI Nmin = -3.0V for pulse width :s; 50 ns.
Including electrical characterisitics and data retention.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
Symbol
Min.
Typ.
Max.
Unit
Input Capacitance
CIN
-
pF
VIN =OV
COUT
-
6
Output Capacitance
12
pF
Vour= OV
Test Condition
HITACHI
2-4
Hitachi America, Ltd .. " 2000 Sierra Point Pkwy." Brisbane, CA94005-1819 " (415) 589-8300
HN58C65 Series
•
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%, T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
-
2
~
Vcc = 5.5 V, VIN = 5.5 V
Output Leakage Current
ILO
-
-
2
~
Vcc = 5.5 V, VOUT = 5.5 V/0.4 V
-
200
1
~
mA
C'E = Vee
CE = VIH
-
8
mA
lOUT = 0 mA, Duty = 100%,
Cycle = 11JS
-
-
25
mA
lOUT = 0 mA, Duty = 100%,
Cycle = 250 ns
VIL
-0.3 1
VIH
2.2
VH
Vcc- 0.5
VOL
-
VOH
2.4
-,
-
Item
Standby Vcc Current
Iccl
Icc2
Operating Vcc Current
Input Voltage
Output Voltage
Notes:
•
1.
IcC3
0.8
V
Vcc + 1
V
Vcc + 1
V
0.4
V
IOL = 2.1 mA
-
V
IOH = -400
~
VI Lmin = -1.0 V for pulse width s 50 ns.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(T. = 0 to 70°C, Vcc = 5V ± 10%)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 V to 2.4 V
S20 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0 V
HN58C66·25
Item
Symbol
Min.
Max.
Unit
250
ns
Test
Condition
tce
-
250
ns
OE = VIL' WE = VIH
Output Enable Access Time
foe
10
100
ns
CE = VIL, WE =VIH
Output Hold to Address
Change
~
0
-
ns
CE = OE = VI L, WE = VIH
Output Disable to High-Zl
IoF
0
90
ns
CE = VIL, WE = VIH
Address Access Time
tACC
Chip Enable Access Time
Note:
CE = OE = VIL, WE = VIH
1.tDF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
2-5
HN58C65 Series
•
READ TIMING WAVEFORM
)<
Address
)<
tACC
/
CE
tOH
1.=.:..+
tCE
""
OE
/
tDF
toE
High
WE
////.
Data Out
Data Out Valid
"""'"
1-<.." 1"0..
IC: V
(TD.R.HN58C65)
•
AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
Item
Symbol
Min. 1
Typ.
Max.
Unit
Address Setup Time
tAS
0
-
ns
Chip Enable to Write Setup Time
-
-
tes
0
Write Pulse Width
tew
200
Address Hold Time
tAH
150
Data Setup Time
tos
100
Data Hold Time
tOH
20
Chip Enable Hold Time
teH
0
Output Enable to Write Setup Time
toes
0
Output Enable Hold Time
toeH
0
Write Cycle Time
!we
-
Byte Load Window
tal
100
Time to Device Busy
toa
120
Note:
1.
Test Condition
ns
ns
ns
ns
ns
ns
ns
-
ns
10
ms
-
!IS
-
I1s
Use this device in a longer cycle than this value.
HITACHI
2-6
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
HN58C65 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (WE Controlled)
Address
CE
tOES
Din
tos
Rdy/Busy
(TD.BE1.HN58C65)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-7
HN58C65 Series
•
BYTE,ERASE AND BYTE WRITE TIMING WAVEFORM (CE Controlled)
Address
CE
WE
tOES
DE
Din
tOB
Rdy/Busy
(TD.BE2.HN58C65)
HITACHI
2·8
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
HN58C65 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PAGE ERASE AND PAGE WRITE OPERATIONS
Item
Symbol
Min. 1
Typ.
Max.
Unit
-
-
ns
-
ns
-
ns
-
-
-
-
tAS
0
Chip Enable to Write Setup Time
Ics
0
Write Pulse Width
1wP2
200
Icw3
200
Address Hold Time
tAH
150
Data Setup Time
Address Setup Time
tos
100
Data Hold Time
tOH
20
Chip Enable Hold Time
IcH
0
Output Enable to Wr~e Setup Time
toes
0
Output Enable Hold Time
IoeH
0
Data Latch Time
tOl
100
Write Cycle Time
!we
-
Byte Load Window
tel
100
Byte Load Cycle
talC
0.3
-
Time to Device Busy-
toe
120
-
Notes:
1.
2.
3.
'Test Condition
ns
ns
ns
ns
ns
ns
ns
-
ns
10
ms
-
I1S
30
J1S
-
ns
Use this device in longer cycle than this value.
WE controlled operation.
CE controlled operation.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
2-9
HN58C65 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (WE Controlled)
Address
AO to A16
WE
Din
Rdy/Busy
(TD.PE1.HN58C65)
HITACHI
2-10
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C65 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (CE Controlled)
Address
AOto A16
Din
Rdy/Busy
(TD.PE2.HN58C65)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-11
HN.58C65 Series
•
AC ELECTRICAL CHARACTERISTICS FOR DATA POLLING OPERATION
Symbol
Min.
Typ.
Max.
Unit
Output Enable Hold Time
tOEH
100
-
~
Output Enable to Output Delay
tOE
10
90
ns
output Enable to Write Setup Time
tOES
0
tow
150
-
ns
Write Start Time
Write Cycle Time
lwc
-
-
10
ms
Item
•
Test Condition
ns
DATA POLLING TIMING WAVEFORM
Address
An
xxxxxxxxxxx~txxxx
An
XXXX
WE
1107
twc
(TD.DP .HN58Cl001)
HITACHI
2-12
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C65 Series
•
FUNCTIONAL DESCRIPTION
Automatic Page Write
The Page Write feature allows 1 to 32 Bytes of
data to be written into the EEPROM in a single write
cycle andthe undefined data within 32 Bytes to be
written corresponding to the undefined address (Ao to
A4). Each additional Byte load cycle must be started
within ~ from the preceding falling edge of WE or
CEo If CE and WE are kept high for 100 IlS after data
input, the EEPROM automatically enters erase and
write mode and only the input data is written into the
EEPROM. Data can be written and accessed 105
times in 32 Byte units.
Data Polling
Data Polling allows the status of the EEPROM to
be determined. If the EEPROM is set to Read mode
during a Write cycle, an inversion of the last Byte of
data to be loaded outputs from 1/07 to indicate that the
EEPROM is performing a Write operation.
WE _ _ _~·
CE
5V
Whh_h
___ h__ 0 V
,,
'
,,,
,,,
,
OE
Ready/Busy Signal
The Ready/Busy signal also allows the status of
the EEPROM to be determined. The Ready/Busy
signal is high impedence except in the write cycle and
is lowered to VOL after the first write signal. At the end
of a write cycle, the Ready/Busy signal changes to
high impedence.
___~~--h----h ~ ~
,,,
,,
~
,,
,,,
,,
,,:~
20 ns max
(DP.HN58Cl00l )
WE and CE Pin Operation
During a write cycle, addresses are latched by the
falling edge of WE or CE, and data is latched by the
rising edge of WE or CEo
Write/Erase Endurance and Data Retention
The endurance with page programming is 105
cycles (1% cumulative failure rate) and the data
retention time is more than 10 years when a device is
programmed less than 104cycles.
Data Protection
To protect the data during operation and power
on/off, the HN58C65 has:
1. Data ..e!:.0tection against Noise on Control Pins
(CE, OE, WE) during Operation.
During readout or standby, noise on the control
pins may act as a trigger and turn the EEPROM to
programming mode by mistake. To prevent this
phenomenon, the HN58C65 has a noise
cancellation function that cuts nOise if its width is
20 ns or less in programming mode. Be careful not
to allow noise of a width of more than 20 ns on the
control pins.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
2-13
HN58C65 Series
(Example)
Vcc
RES
J
.
·
,
\~!
..
\:
,
..
.
···· ,
*unprogrammable
,1.,.- __ ...,
,,
tc---..-I
'
*unprogrammable
(DPexe.HN58C 1001)
• FUNCTIONAL DESCRIPTION (continued)
Data Protection (continued)
2. Data protection at Vcc on/off
When Vee is turned on or off, noise on the control
pins generated by external circuits (CPU, etc) may
turn the EEPROM to programming mode by
mistake. To prevent this unintentional
programming, the EEPROM must be kept in an
unprogrammable state while the CPU is in an
unstable state.
In addition, when RES is kept high at V~on/off
timing, the input level of control pins (CE, OE, WE)
must be held as CE=Vcc or OE=Low or WE=Vcc
level.
HITACHI
2-14
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
64K (8K
Preliminary
x 8-bil) EEPROM
•
DESCRIPTION
The Hitachi HN58C66 is a 64-Kilobit CMOS Electrically Erasable
Programmable Read Only Memory (EEPROM) organized as 8,192
x 8-bits. The HN58C66 is capable of in-system electrical Byte and
Page reprogrammability.
The HN58C66 achieves high speed access, low power
consumption, and a high level of reliability by employing advanced
MNOS memory technology and CMOS process and circuitry
technology.
The HN58C66 has a 32-Byte Page Programming function to
make its erase and write operations faster. The HN58C66 features
Data Polling and a Ready/Busy signal to indicate completion of erase
and programming operations.
The HN58C66 provides several levels of data protection.
Hardware data protection is provided with the RES pin, in addition to
noise protection on the WE signal and write inhibit on power on and
off.
The HN58C66 is designed for high reliability in the most
demanding applications. Data retention is specified for 10 years and
erase/write endurance is guaranteed to a minimum of 100,000
cycles in the Page Mode.
The HN58C66 is offered inJEDEC-Standard Byte-Wide EEPROM
pinouts in 28-pin Plastic DIP and 28-lead Plastic SOP packages. The
HN58C66 is also offered in a 32-lead Plastic TSOP package.
•
FEATURES
• Single Power Supply:
Vee = 5V± 10%
• Fast Access Time:
250 ns (max)
• Low Power Dissipation:
Active Current: 20 mW/MHz (typ)
Standby Current: 2 mW (max)
• Automatic Programming:
Automatic Page Write: 10 ms (max)
32 Byte Page Size
Automatic Byte Write: 10 ms (max)
• Data Polling and Ready/Busy S~ls
• Hardware Data Protection with RES pin
• Data Protection Circuitry on Power On/Off
• Data Retention: 10 years
• Erase/Write Endurance:
100,000 cycles in Page Mode
• Pinouts:
JEDEC Standard Byte-Wide EEPROM
• Packages:
28-pin Plastic DIP
28-lead Plastic SOP
32-lead Plastic TSOP (Type I)
(DP-28)
(FP-28DA)
(TFP-32DA)
HITACHI
Hitactli America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-15
HN58C66 Series
•
ORDERING INFORMATION
Type No.
HN58C66P-25
Access Time
250 ns
HN58C66FP-25
250ns
HN58C66T-25
250 ns
•
Package
28-pin Plastic DIP
(OP-28)
28-lead Plastic SOP
(FP-280A)
32-lead Plastic TSOP
(TFP-320A)
PIN ARRANGEMENT
•
HN58C66P Series
HNS8C66FP Series
ROYIBusy
A12
A7
A6
AS
A4
A3
A2
A1
AO
1/00
1/01
1/02
Vss
3
4
5
6
7
8
9
10
11
12
13
14
28-PIN
' DIP
SOP
TOP VIEW
22
21
20
19
18
17
16
15
Vcc
WE
RES
A8
A9
A11
OE
A10
CE
1/07
1/06
1/05
1/04
1/03
PIN DESCRIPTION
Pin Name
Function
Ao - A'2
1/00 -1/07
Address
Input/Output
OE
Output Enable
CE
Chip Enable
WE
Write Enable
Vee
Power Supply
Vss
RdylBusy
ReadylBusy
RES
Reset
Ground
(PinD28.HN58C66)
HN58C66T Series
A2
A1
AO
NC
1/00
1/01
1/02
Vss
1/03
1/04
1/05
1/06
1/07
A3
A4
A5
A6
A7
A12
NC _
ROYIBusy
Vcc
STANDARD PINOUT
32-LEAD
TSOP
TOP VIEW
~
~~
o
CE
A10
RES
A8
A9
~k1
(PinT132.HN58C66T)
HITACHI
2-16
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
•
BLOCK DIAGRAM
Vcc
Vss
g :1
1/00 -
High Voltage Generator
1/07
ReadylBusy
1/0 Buffer
OE
and
Input Latch
CE
Control Logic and Timing
WE
RES
AO
I
A4
Address
Buffer and
Latch
X Decoder
Memory Array
AS
I
A12
Data Latch
(BD.HNS8C66)
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005--1819· (415) 589·8300
2·17
HN58C66 series
•
MODE SELECTION
Mode
CE
OE
WE
RES
RDYIBusy
1/0
Read
V,L
V,L
V,H
VH
High-Z
Standby
V,H
X
X
X
High-Z
DoUT
High-Z
V'L
V,L
V,H
V,L
VH
High-Z+VoL
V,H
V,H
VH
High-Z
X
X
V,H
X
-
X
V,L
X
X
-
V,L
V,L
VOL
Data Out (1/07)
X
V'H
X
VH
X
V,L
High-Z
High-Z
· Write
Deselect
Write Inhibit
Data Polling
Program
Note:
•
D'N
High-Z
X = Don't Care
1.
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage 1
Input Voltage
1
Operating Temperature Range 3
Symbol
Value
Unit
Vee
V,N
-0.6 to +7.0
V
-0.52 to +7.0
V
TOPR
oto +70
°c
Storage Temperature Range
Notes:
•
1.
2.
3.
-55 to +125
TSlG
Relative to VSS.
V, N min =-3.0V for pulse width $ 50 ns.
Including electrical characterisitics and data retention.
°C
CAPACITANCE (Ta = 25°C, f = 1MHz)
Item
Input Capacitance
Output Capacitance
Symbol
Min.
Typ;
Max.
Unit
Test Condition
C'N
-
-
6
pF
V,N =OV
12
pF
VOUl =OV
COUl
HITACHI
2-18
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
•
DC ELECTRICAL CHARACTERISTICS
(Vee =5V ± 10%, T. =0 to 70°C)
Item
Min.
Typ.
Max.
Unit
Test Condition
-
-
2
Vee = 5.5 V, VIN = 5.5 V
200
I1A
I1A
I1A
1
mA
8
mA
-
-
25
mA
VIL
-0.3 2
V
2.2
Vec + 1
V
VH
VCC- 0.5
VOL
-
VOH
2.4
-
0.8
VIH
Symbol
1
Input Leakage Current
III
Output Leakage Current
ILO
Standby Vee Current
leel
lee2
Operating Vee Current
Input Voltage
Output Voltage
Notes:
•
1.
2.
Icc3
III on RES = 100 I1A max.
VI Lmin =-3.0 V for pulse width
~
2
= 5.5 V, VOUT =5.5 V/O.4 V
rn= = Vee
CE= VIH
lOUT = 0 mA, Duty = 100%,
Cycle = 1 j.l.S
lOUT = 0 mA, Duty = 100%,
Cycle =250 ns
Vee
Vcc + 1
V
0.4
V
IOL =2.1 mA
-
V
IOH = -400 I1A
50 ns.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(T. = 0 to 70°C, Vce = 5V ± 10%)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 Vt02.4 V
~20 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0 V
HN58C66·25
Symbol
Item
Test
Condition
Min.
Max.
Unit
250
ns
CE =OE = VIL.WE
250
ns
OE = VIL. WE
tCE
-
Output Enable Access Time
toE
10
100
ns
CE = VI L. WE = VIH
Output Hold to Address
Change
tOH
0
-
ns
CE =OE = VIL.WE
Output Disable to High-Zl
tOF
0
90
ns
CE = VIL. WE
tOFR
0
350
ns
CE =OE = VIL. WE
tRR
0
450
ns
Address Access Time
Chip Enable Access Time
RES to Output Delay
Note:
tACC
=VIH
= VIH
=VIH
=VIH
=VIH
CE =OE =VI L. WE = VIH
1.tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-19
HN58C66 series
•
READ TIMING WAVEFORM
)<
Address
)<
tACC
/
~
tCE
/
I toE
tOF
High
////
Data Out
tRR
"-
Data Out Valid
""'"""'""''
V
~
/
tOFR
(TO.R.HN58Cl00l)
•
AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
Item
Symbol
Min.'
Typ.
Max.
Unit
Address Setup Time
tAS
0
ns
Chip Enable to Write Setup Time
-
tOEH
0
-
Write Cycle Time
lwc
10
-
Byte Load Window
tel
100
Time to Device Busy
toe
120
tRP
tREs
100
-
tcs
0
Write Pulse Width
tcw
200
Address Hold Time
tAH
150
Data Setup Time
tos
100
Data Hold Time
tOH
0
Chip Enable Hold Time
tCH
0
Output Enable to Write Setup Time
toES
0
Output Enable Hold Time
RES to Write Setup Time
Vcc to RES Setup Time
Note:
1.
1
..
.
Test Condition
ns
ns
ns
ns
ns
,
ns
ns
ns
ms
lIS
ns
lIS
lIS
Use this device in a longer cycle than this value.
HITACHI
2-20
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (WE Controlled)
Address
CE
WE
II
t ES
OE
tos
tOH
Din
tOB
Rdy/Busy
tRP
RES
Vee
(TD.BE1.HN58Cl00l)
!II
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy•• Brisbane, CA 94005-1819· (415) 589-8300
2-21
HN58C66 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (CE Controlled)
Address
CE
WE
tOES
OE
Din
tOB
Rdy/Busy
RES
(TD.BE2.HN58Cl 001)
HITACHI
2-22
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
HN58C66 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PAGE ERASE AND PAGE.WRITE OPERATIONS
Symbol
Min.1
Address Setup Time
tAS
0
Chip Enable to Write Setup Time
les
Write Pulse Width
lw.o
2
Item
Typ.
Max.
Unit
-
ns
0
-
ns
200
-
-
ns
lew3
200
-
-
ns
tAH
150
Data Setup Time
los
100
-
Data Hold Time
-
Address Hold Time
taH
0
Chip Enable Hold Time
leH
0
OUtput Enable to Write Setup Time
lees
0
OUtput Enable Hold Time
ioeH
0
Data Latch Time
tal
100
Write Cycle Time
!we
10
Byte Load Window
tal
100
Byte Load Cycle
taLC
q.3
Time to Device Busy
loa
120
RES to Write Setup Time
tRP
100
Vee to RES Setup Time
tRES
1
Notes:
1.
2.
3.
-
-
-
Test Condition
ns
ns
ns
ns
ns
FJ
ns
ns
ms
-
lIS
30
Ils
-
ns
lIS
-
lIS
Use this device in longer cycle than this value.
WE controlled operation.
CE controlled operation.
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589·8300
2-23
HN58c66 Series
•
PAGE ERASE AND PAGE WRITE-TIMING WAVEFORM (WE Controlled)
Address
AOto A16
Din
Rdy/Busy
(TO.PE1.HN58C1001 )
HITACHI
2-24
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (CE Controlled)
Address
AO to A16
Din
Rdy/Busy
(TD.PE2.HN58C1 001)
HITACHI
Hitachi America. Ltd. ·2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
2-25
HN58C66 Series
•
AC ELECTRICAL CHARACTERISTICS FOR DATA POLLING OPERATION
Symbol
Min.
Typ.
Max.
Unit
Output Enable Hold Time
tOEH
100
-
~
Output Enable to Output Delay
-
90
ns
-
ns
10
ms
Item
tOE
10
Output Enable to Wr~e Setup, Time
tOES
0
Write Start Time
tow
150
fwc
-
Write Cycle Time
•
Test Condition
ns
DATA POLLING TIMING WAVEFORM
Address
_An---JXXXXXXxxxxx~txxxx
An XXXX
CE
WE
1107
twc
(TD.DP.HN58Cl00l)
HITACHI
2-26
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C66 Series
•
FUNCTIONAL DESCRIPTION
Automatic Page Write
The Page Write feature allows 1 to 32 Bytes of
data to be written into the EEPROM in a single write
cycle andthe undefined data within 32 Bytes to be
written corresponding to the undefined address (0\ to
A4 ). Each additional Byte load cycle must be started
within ~ from the preceding falling edge of ~ or
CEo If CE and WE are kept high for 100 IlS atter data
input, the EEPROM automatically enters erase and
write mode and only the input data is written into the
EEPROM. Data can be written and accessed 105
times in 32 Byte units.
WE - - - - - - " \ .
CE
,, ,
,
W ___
________
5V
0V
I
I
I
,
,
I
I
I
I
I
I
I
Date Polling
Data Polling allows the status of the EEPROM to
be determined. If the EEPROM is set to Read mode
during a Write cycle, an inversion of the last Byte of
data to be loaded outputs from 1/°7 to indicate that the
EEPROM is performing a Write operation.
m
OE
-----'Ji;:---- - - - ~ ~
I
I
I
I
I
.......:
I
I
I
,
I
I
I
:4I
I
20 ns max
Ready/Busy SIll!!!'
The Ready/Busy signal also allows the status of
the EEPROM to be determined. The Ready/Busy
signal is high impedence except in the write cycle and
is lowered to VOL atter the first write signal. At the end
of a write cycle, the Ready/Busy signal changes to
high impedence.
(DP.HN58Cl00l)
WE and CE Pin Operation
During a write cycl~ddresses are latched by the
falling edge of WE or CE, and data is latched by the
rising edge of WE or CEo
Write/Erase Endurance and Data Retention
The endurance with page programming is 105
cycles (1% cumulative failure rate) and the data
retention time is more than 10 years when a device is
programmed less than 104 cycles.
Data Protection
To protect the data during operation and power
on/off, the HN58C66 has:
1. Data protection against Noise on Control Pins
(CE, OE, WE) during Operation.
During readout or standby, noise on the control
pins may act as a trigger and turn the EEPROM to
programming mode by mistake. To prevent this
phenomenon, the HN58C66 has a noise
cancellation function that cuts noise if its width is
20 ns or less in programming mode. Be careful not
to allow noise of a width of more than 20 ns on the
control pins.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-27
HN58C66 Series
,,
(Example)
Vcc
RES
J
,
\.,..!-,
\:
,
--'--II
,,
,
,,
,,
*unprogrammable
,....... - --''
,,
''
*unprogrammable
1. . - - - . ,
(DPexe.HN58Cl 001)
• FUNCTIONAL DESCRIPTION (continued)
Data Protection (continued)
2. Data protection at Vee on/off
When RES is low, the EEPROM cannot be erased
and programmed. Therefore, data can be
protected ~ keeping RES low when Vee is
switched. RES should be high during programming
because it does not provide a latch function.
When Vee is turned on or off, noise on the control
pins generated by external circuits (CPU, etc) may
turn the EEPROM to programming mode by
mistake. To prevent this unintentional
programming, the EEPROM must be kept in an
unprogrammable, standby or readout state by
using a CPU reset signal to RES pin.
In addition, when RES is kept high..& ~on/off
timing, the input level of control pins (CE, OE, WE)
must be held as CE=Vee or OE=Low or WE=Vee
level.
HITACHI
2-28
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN58C256 Series
256K (32K x 8-bit) EEPROM
•
DESCRIPTION
The Hitachi HN58C256 is a 256-Kilobit CMOS Electrically
Erasable Programmable Read Only Memory (EEPROM) organized
as 32,768 x 8-bits. The HN58C256 is capable of in-system electrical
Byte and Page reprogrammability.
The HN58C256 achieves fast address access, low power
consumption, and a high level of reliability by employing advanced
MNOS memory technology and CMOS process and circuitry
technology.
The HN58C256 has a 64-Byte Page Programming function to
make its erase and write operations faster. The HN58C256 features
Data Polling to indicate completion of erase and programming
operations.
The HN58C256 provides several levels of data protection.
Hardware data protection is provided with noise protection on the
WE signal and write inhibit on power on and off..
The HN58C256 is designed for high reliability in the most
demanding applications. Data retention is specified for 10 years and
eraselwrite endurance is guaranteed to a minimum of 100,000
cycles in the Page Mode.
The Hitachi HN58C256 is offered in JEDEC-Standard ByteWide EEPROM pinouts in 28-pin Plastic DIP and 2B-lead SOP
packages .
•
(DP-2B)
(FP-2BD)
FEATURES
• Single Power Supply:
Vee =5V± 10%
• Fast Access Time:
200 ns (max)
• Low Power Dissipation:
Active Current:
20 mW/MHz (typ)
Standby Current: 200 JlW (typ)
• Automatic Programming:
Automatic Page Write: 10 ms (max)
64 Byte Page Size
Automatic Byte Write: 10 ms (max)
• Data Polling
• Data Protection Circuitry on Power On/Off
• Data Retention: 10 years
• Erase/Write Endurance:
100,000 cycles in Page Mode
• Pin Arrangement:
JEDEC Standard Byte-Wide EEPROM
• Packages:
28-pin Plastic DIP
28-lead Plastic SOP
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-29
HN58C256 Series
•
ORDERING INFORMATION
Type No.
Access Time
Package
HN58C256P-20
200 ns
28-pin Plastic DIP
HN58C256FP-20
200 ns
(DP-28)
28~lead
Plastic SOP
(FP-28D)
•
PIN ARRANGEMENT
•
HN58C256P Series
HN58C256FP Series
A14
A12
A7
A6
A5
A4
A3
A2
A1
AO
1/00
1/01
1/02
Vss
VCC
2
3
4
5
28·PIN
6
DIP
28·LEAD
7
SOP
8
TOP VIEW
9
10
11
12
13
14
WE
A13
A8
A9
A11
OE
A10
CE
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
Pin Name
Function
Ao - A14
Address
1/00 - 1/07
Input/Output
OE
Output Enable
CE
Chip Enable
WE
Write Enable
Vee
Power Supply
Vss
Ground
1/07
1/06
1/05
1/04
1/03
(PinD32.HN58C256)
•
BLOCK DIAGRAM
VVCssC~
~
1100 -
High Vohage Generator
1107
Ready/Busy
'--------'
CE
~~:hr__,----------,---}-------t_----~
RES
AD
I
All
Address
Buffer and
latch
A7
I
A16
(BD.HN58C1001)
HITACHI
2-30
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589-8300
HN58C256 Series
•
MODE SELECTION
Mode
~
~
~
1/0
Read
VIL
VIL
VIH
Standby
Vii
X
X
DOUT
High-Z
Write
Deselect
VIL
VIL
VIH
VIH
VIL
VIH
DIN
High-Z
Write Inhibit
X
X
VIH
-
X
VIL
VIL
X
Data Polling
Note:
•
VIL
1.
VIH
Data Out (1/07 )
X .. Don't Care
ABSOLUTE MAXIMUM RAnNGS
Item
Supply Voltage 1
Input Voltage
1
Operating Temperature Range' 3
Symbol
Value
Unit·
Vee
VIN
-0.6 to +7.0
V
-0.52
V
to +7.0
oto +70
TOPR
°C
-55 to +125
TSTG
Relative to Vss.
VI Nmin .. -3.0V for pulse width S 50 ns.
Including electrical characterisitics and data retention.
Storage Temperature Range
Notes:
•
1.
2.
3.
°C
CAPACITANCE (T... 25°C, f .. 1MHz)
Item
Input Capacitance
Output Capacitance
Symbol
Min.
Typ.
Max.
Unit
Test Condition
CIN
COUT
-
-
6
pF
VIN=OV
-
12
pF
VOUT=OV
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.. Brisbane, CA 94005-1819 • (415) 58~
- - - - - - ._-_.._._--_ .•...
2-31
HN58C256 Series
•
DC ELECTRICAL CttARACTERISTICS
(Vcc = 5V ± 10%, T. = 0 to 70°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
-
-
'2
~
Vee =5.5 V, VIN =5.5 V
Output Leakage Current
ILO
-
2
~
Vcc =5.5 V,Vour =5.5 VlO.4 V
Standby Vcc Current
Iccl
"
-
-
200
~
1
rnA
rn: = Vee
rn: =VIH
12
rnA
lour =0 rnA, Duty = 100%,
Cycle = 1 ~
-
-
30
rnA
lOUT =0 rnA, Duty = 100%,
Cycle = 200 ns
VIL
-0.3 1
-
0.8
V
VIH
2.2
-
Vee + 1
V
0.4
V
IOL =2.1 rnA
-
V
IOH = -400 ~
Icc2
Operating Vcc Current
Input Voltage
Output Voltage
Notes:
•
1.
lee3
VOL
-
VOH
2.4
~
VI Lmin = -3.0 V for pulse width :50 50 ns.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(T. = 0 to 70°C, Vee = 5V ±10%)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 V to 2.4 V
~20 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0V
HN58C257·20
Item
Symbol
Min.
Max.
Unit
Test
Condition
tACO
-
200
ns
CE = OE =VI L. WE
Chip Enable Access Time
tee
-
200
ns
OE = VIL. WE .. VIH
Output Enable Access Time
toe
10
90
ns
CE .. VIL. WE .. VIH
Output Hold to Address
Change
taH
0
-
ns
CE .. OE =VIL. WE =VIH
Address Access Time
=VIH
0
70
ns
C'E' .. VIL. WE .. VIH
tOF
1.tOF IS defined as the time at which th'e output becomes an open circuit and data is no
longer driven.
Output Disable to High-Zl
Note:
HITACHI
2-32
Hitachi America,
Ltd;· 2000 Sierra Point Pkwy.' Brisbane, CA94005-1819' (415) 589-8300
'.
HN58C256 Series
•
READ nMING WAVEFORM
x
Address
)<
tACC
/
tOH
~
tCE
""
/
tOF
toE
High
////.
Data Out
Data Out Valid
""
...
",
"
'/
(TO.R.HN58C256)
•
AC ELECTRICAL CHARACTERIBnCS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
Symbol
Min.1
Typ.
Max.
Unit
Address Setup Time
tAS
-
Write Pulse Width
tcs
tow
Address Hold Time
tAH
-
ns
Chip Enable to Write Setup Time
ns
Data Setup Time
tos
0
0
150
150
100
0
0
0
0
10
100
-
ns
-
ns
Item
Data Hold Time
toH
Chip Enable Hold Time
~
Output Enable to Write Setup Time
toes
Output Enable Hold Time
~
Write Cycle Time
twc
Byte Load Window
tat.
Note:
1.
-
-
Test Condition
ns
ns
ns
ns
ns
ms
p.s
Use this device in a longer cycle than this value.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane,
CA 94005~1819· (415) 589-8300
2-33
HN58C256 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (WE Controlled)
Address
CE
tOES
Din
(TD.BE1.HN58C256)
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (CE Controlled)
Address
CE
tOES
OE
tos
I----'::..::..J
tOH
Din
(TD.BE2.HN58C256)
HITACHI
2-34
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C256 Series.
•
AC ELECTRICAL CHARACTERI8nCS FOR PAGE ~RASE AND PAGE WRITE OPERATIONS
Item
Address Setup Time
Chip Enable to Write Setup Time
Write Pulse Width
Symbol
Min. 1
Typ.
Max.
Unit
tAS
0
-
lea
lwP2
lcw3
0·'
-
150
-
150
-
.
-
ns
-
ns
-
ns
ms
30
I1S
tAH
150
-
Data Setup Time
tas
100
Data Hold Time
tOH
0
Chip Enable Hold Time
tCH
0
Write Cycle Time
lees
toefl
lot.
lwc
0
-
Byte Load Window
tal
100
talC
0.3
Address Hold Time
Output Enable to Write Setup Time
Output Enable Hold Time
Data Latch Time
Byte Load Cycle
Notes:
1.
2.
3.
0
200
10
-
-
Test Condition
ns
ns
ns
ns
ns
ns
ns
ns
I1S
Use this device in longer cycle than this value.
WE controlled operation.
CE controlled operation.
HITACHI
Hitac!1i America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-35
HN58C256 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (WE Controlled)
Address
AO to A16
Din
(TD.PE1.HN58C256)
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (CE Controlled)
Address
AO to A16
Din
(TD.PE2.HN58C256)
HITACHI
2-36
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
HN58C256 Series
•
AC ELECTRICAL CHARACTERISTICS FOR DATA POLLING OPERATION
Item
Output Enable Hold Time
Symbol
Min.
Typ.
Max.
Unit
-
90
IJS
ns
-
ns
-
ns
10
ms
tOEH
100
Output Enable to Output Delay
leE
10
Output Enable to Write Setup Time
tOES
0
Write Start Time
tow
150
Write Cycle Time
twe
-
•
Test Condition
DATA POLLING TIMING WAVEFORM
Address
An
xxxxxxxxxxx~txxxx
An
XXXX
WE
1/07
twe
(TD.DP.HN58Cl 001)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 ' (415) 589-8300
2-37
HN58C256 Series
•
FUNCTIONAL DESCRIPTION,
Automatic Page Write
The Page Write feature allows 1 to 64 Bytes of
data to be written into the EEPROM in a single write
cycle. Following the initial Byte cycle, an additional 1
to 63 Bytes can be written in the same manner. Each
additional Byte load cycle must be started within 30 jlS
from the preceding falling edge of WE or CEo When
WE or CE is high for 100 jlS after data input, the
EEPROM enters erase and write mode automatically
and only the input data is written into the EEPROM.
Data can be written and accessed 105 times in 64 Byte
units.
Data POlling
Data Polling allows the status of the EEPROM to
be determined. If the EEPROM is set to Read mode
during a Write cycle,an inversion of the last Byte of
data to be loaded outputs from 1/07 to indicate that the
EEPROM is performing a Write operation.
WE - - - - - " .
CE
~ __ . ___
,
m
5V
0V
______________ 5 V
DE
,.,r-"---
-:,
,
WE and CE Pin Operation
During a write cycle, addresses are latched by the
falling edge of WE or CE, and data is latched by the
rising edge of WE or CEo
0V
,,
:,
,
20 ns max
(DP.HN58C1001)
Writjil/Erase Endurance and Data Retention
The endurance with page programming is 105
cycles (1% cumulative failure rate) and the data
retention time is more than 10 years when a device is
programmed less than 104 cycles.
Data Protection
To protect the data during operation and power
on/off, the HN58C256 has:
1. Data protection against Noise on Control Pins
(CE, OE, WE) during Operation.
During readout or standby, noise on the control
pins may act as a trigger and turn the EEPROM to
programming mode by mistake. To prevent this
phenomenon, the HN58C256 has a noise
cancellation function that cuts noise if its width is
20 ns or less in programming mode. Be careful not
to allow noise of a width of more than 20 ns on the
control pins.
HITACHI
2-38
_____
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN58C256 Series
(Example)
Vec
RES
,,,
Jr-------.\'--!
__-+,-J;('r----------------~~ :
,
.... -I
,
,
1
1
I
I
I
I
I
I
I
f
..... -- - .....
~
I
·unprogrammable
·unprOQrammable
(DPexe.HN58Cl 001)
• FUNCTIONAL DESCRIPTION (continued)
Data Protection (continued)
2. Data protection at Vcc on/off
When Vcc is turned on or off, noise on the control
pins generated by external circuits (CPU, etc) may
tum the EEPROM to programming mode by
mistake. To prevent this unintentional
programming, the EEPROM must be kept in an
unprogrammable state while the CPU is in an
unstable state.
In addition, when Vcc is turned on or off, the input
level ofthe control pins (CE, OE, WE) must be held
as CE=Vcc or OE=Low or WE=Vcclevel.
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
2-39
HN58C257 Series
256K (32K x a-bit) EEPROM
•
DESCRIPTION
The Hitachi HN58C257 is a 256-Kilobit CMOS Electrically
Erasable Programmable Read Only Memory (EEPROM) organized
as 32,768 x 8-bits. The HN58C257 is capable of in-system electrical
Byte and Page reprogrammability.
The HN58C257 achieves high speed access, low power
consumption, and Ii high level of reliability by employing advanced
MNOS memory technology and CMOS process and circuitry
technology.
The HN58C257 has a 64-Byte Page Programming function to
make its erase and write operations faster. The HN58C257 features
Data Polling and a Ready/Busy signal to indicate completion of erase
and programming operations.
The HN58C257 provides several levels of data protection.
Hardware data protection is provided with the RES pin, in addition to
noise protection on the WE signal and write inhibit on power on and
off.
The HN58C257 is designed for high reliability in the most
demanding applications. Data retention is specified for 10 years and
eraselwrite endurance is guaranteed to a minimum of 100,000
cycles in the Page Mode.
The HN58C257 is offered in a 32-lead Plastic TSOP package in
both standard and reverse bend pinouts .
•
(TFP-32DA)
(TFP-32DAR)
FEATURES
• Single Power Supply:
Vcc =5V±10%
• Fast Access Time:
200 ns (max)
• Low Power Dissipation:
Active Current: 20 mW/MHz (typ)
Standby Current: 200 ~W (typ)
• Automatic Programming:
Automatic Page Write: 10 ms (max)
64 Byte Page Size
Automatic Byte Write: 10 ms (max)
• Data Polling and ReadylBusy Signals
• Hardware Data Protection with RES pin
• Data Protection Circuitry on Power On/Off
• Data Retention: 10 years
• EraselWrite Endurance:
100,000 cycles in Page Mode
• Packages:
32-lead Plastic TSOP (Type I)
HITACHI
2-40
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
HN58C257 Ser,ies
•
ORDERING INFORMATION
Type No.
HN5SC257T-20
Access Time
200 ns
HN5SC257R-20
200 ns
•
Package
32-lead Plastic TSOP
(TFP-320A)
32-lead Plastic TSOP
(TFP-32 OAR)
Reverse bend
PIN ARRANGEMENT
HN5SC257T Series
A2
A1
AO
NC
1/00
1/01
1/02
Vss
1/03
1/04
1/05
1/06
1/07
NC
CE
A10
A3
A4
A5
A6
A7
A12
A14
ROY/Busy
STANDARD PINOUT
32-LEAD
TSOP
TOP VIEW
~
0
RES
WE
A13
AS
A9
A11
OE
(PinT132.HN58C257T)
HN5SC257R Series
A3
A4
A5
A6
A7
A12
A14
ROY/Busy
REVERSE PINOUT
32-LEAD
TSOP
TOp, VIEW
~
R~E
A13
AS
A9
A11
OE
A2 ,
A1 '
AO
NC
1/00
1/01
1/02
Vss
1/03
1/04
1/05
1/06
1/07
NC
~
0
A10
(PinT132.HN58C257R)
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
2-41
HN58C257 Series
•
•
PIN DESCRIPTION
Pin Name
Function
Ao - AI,
Address
"00 - 1/°7
Input/Output
OE
Output Enable
CE
Chip Enable
WE
Write Enable
Vee
Power Supply
Vss
Ground
Rdy/Busy
Ready/Busy
RES
Reset
BLOCK DIAGRAM
Vee
1100 -
High Voltage Generator
1/07
Ready/Busy
Vss
110 Buffer
and
Control Logie and TIming
AO
I
AS
Address
Buffer and
Lateh
X Decoder
Memory Array
AS
I
A14
(BD.HN58C257)
HITACHI
2-42
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58C257 Series
•
MODE SELECTION
Mode
CE
OE
WE
RES
ROY/Busy
Read
VIL
VIL
VIH
VH
High-Z
DOUT
Standby
VIH
X
X
X
High-Z
High-Z
Write
VIL
VIH
VIL
VH
High-Z-VOL
Deselect
VIL
VIH
VIH
VH
High-Z
DIN
High-Z
X
X
VIH
X
High-Z
-
X
VIL
X
X
High-Z
VIL
VIL
VIH
VH
VOL
Data Out (1/07)
X
X
VIL
High-Z
High-Z
Write Inhibit
IJaia Polling
X
Program
Note:
•
X = Don't Care
1.
fJ
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
VIN
-0.6 to +7.0
V
-0.5 to +7.0
V
Operating Temperature Range 3
TOPR
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Supply Voltage
Input Voltage
Notes:
•
I/O
1.
2.
3.
1
1
2
Relative to VSS.
VI Nmin = -3.0V for pulse width :5 50 ns.
Including electrical characterisitics and data retention.
CAPACITANCE (T. = 25°C, f = 1MHz)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Capacitance
CIN
-
6
pF
VIN =OV
Output Capacitance
COUT
-
-
12
pF
VOUT = OV
Item
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-43
HN58C257 Series
•
DC ELECTRICAL CHARACTERISTICS
(Vee =5V ± 10%, T. =0 to 70°C)
Symbol
Item
Typ.
Max.
Unit
Test Condition
l1A
l1A
Vee =5.5 V, VIN =5.5 V
200
J.lA
lec2
.
1
rnA
CE = Vee
CE,. VIH
Icc3
-
-
2
lecl
-
12
rnA
lOUT" 0 rnA, Duty = 100%,
Cycle,. 1 J.1S
-
-
30
rnA
lOUT" 0 rnA, Duty,. 100%,
Cycle,. 200 ns
VIL
-0.3 2
VIH
2.2
VH
Vcc - 0.5
VOL
VOH
-
-
III
Output Leakage Current
ILO
Standby Vee Current
Operating Vce Current
Input Voltage
Output Voltage
Notes:
•
Min.
1
Input Leakage Current
1.
2.
2.4
2
Vee =5.5 V, VOUT " 5.5 V/0.4 V,
0.8
V
Vcc + 1
V
Vce + 1
V
0.4
V
IOL" 2.t rnA
-
V
IOH = -400 l1A
III on A'ES = 100 rnA max.
VI Lmin =-3.0 V for pulse width::; 50 ns.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(T. =0 to 70°C, Vee" 5V ± 10%)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 Vt02.4 V
::;20 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0 V
HN58C257·20
item
Test
Condition
Symbol
Min.
Max.
Unit
tAec
200
ns
CE = DE = VI L. WE
200
ns
OE,. VIL. WE,. VIH
Chip Enable Access Time
tCE
-
Output Enable Access Time
tOE
10
90
ns
CE,. Vll, WE,. VIH
Output Hold to Address
Change
tOH
0
-
ns
CE ,. OE ,. VI L, WE = VIH
Output Disable to High-Zl
tOF
0
70
ns
tOFR
0
350
ns
CE',. VIL. WE = VIH
CE' =OE = VIL, WE = VIH
tRR
0
450
ns
CE = DE ,. VI L. WE ,. VIH
Address Access Time
RES to Output Delay
Note:
=VIH
1.toF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
2-44
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN58C257 Series
•
READ TIMING WAVEFORM
x
Address
)<
tACC
/'
~
tCE
../
I toE
tOF
High
////
Data Out
"
.......
Data Out Valid
............... ........
tRR
.".
~
/'
tOFR
(TD.R.HN58Cl 001)
•
AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
Symbol
Min.'
Typ.
Max.
Unit
Address Setup Time
tAS
0
-
ns
Chip Enable to Write Setup Time
les
0
lew
150
tAH
tDS
150
100
Data Hold Time
IoH
0
-
Chip Enable Hold Time
tCH
0
Output Enable to Wrne Setup Time
-
-
ns
Write Pulse Width
-
Item
Address Hold Time
Data Setup Time
lees
0
Output Enable Hold Time
leeH
0
Write Cycle Time
!wc
10
Byte Load Window
let.
100
Time to Device Busy
tDe
120
RES to Write Setup Time
Vcc to RES Setup Time
~p
100
tRES
1
Note:
1.
Test Condition
ns
ns
ns
ns
ns
ns
ns
ms
IJ.S
ns
I1S
IJ.S
Use this device in a longer cycle than this value.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
2-45
.HN58C257 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (WE Controlled)
Address
CE
tOES
tos
Din
toe
Rdy/Busy
RES
Vee
(TO.BE1.HN58Cl00l )
HITACHI
2-46
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN58C257 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (CE Controlled)
Address
CE
WE
fJ
tOES,
OE
tos
tOH
Din
toe
Rdy/Busy
tRP
tRES
RES
Vee
(TO.BE2.HN58Cl00l)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
2-47
HN58C257 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PAGE ERASE AND PAGE WRITE OPERATIONS
Item
Symbol
Min.'
Typ.
Max.
Unit
Address Setup Time
tAS
0
tes
Write Pulse Width
fw.,2
0
150
-
-
ns
Chip Enable to Write Setup Time
tew
150
Address Hold Time
tAH
150
Data Setup Time
3
tos
100
Data Hold Time
tOH
0
Chip Enable Hold Time
tCH
0
Output Enable to Write Setup Time
toes
0
Output Enable Hold Time
toeH
Data Latch Time
tOL
0
200
Write Cycle Time
two
10
Byte Load Window
tBL
Byte Load Cycle
~c
100
0.3
Time to Device Busy
120
RES to Write Setup Time
tOB
tRP
100
Vee to RES Setup Time
tRES
1
Notes:
1.
2.
3.
30
-
Test Condition
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
I1s
I1S
ns
I1S
I1S
Use this device in longer cycle than this value.
WE controlled operation.
CE controlled operation.
HITACHI
2-48
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. CA 94005,1819· (415) 589·83QO
HN58C257 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (WE Controlled)
Address
AOto A16
Din
Rdy/Busy
(TD.PE1.HN58Cl00l)
HITACHI
Hitachi America. Ltd.' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
2-49
HN58C257 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (CE Controlled)
Address
AO to A16
Din
Rdy/Busy
(TD.PE2.HN58Cl00l )
HITACHI
2-50
,Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA94005-1819· (415) 589-8300
HN58C257 Series
•
AC ELECTRICAL CHARACTERISTICS FOR DnA POLLING OPERAnON
Item
Output Enable Hold Time
Output Enable to Output Delay
Output Enable 10 Wrhe Setup Time
Write Start Time
Write Cycle Time
Min.
toeH
toe
100
-
-
10
.
90
J1S
ns
-
ns
-
ns
10
ms
toes
0
low
Iwc
150
-
Typ.
Max.
Symbol
Unit
Test Condition
• DATA POLLING TIMING WAVEFORM
Address
An
XXXXXXXXXXX~~XXXX
An
XXXX
1107
twc
(TD.DP.HN58C1001)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA9400S-1819· (41S) 589-8300
2-51
HN58C257 Series
•
FUNCTIONAL DESCRIPTION
Automatic Page Write
The Page Write feature allows 1 to 64 Bytes of
data to be written into the EEPROM in a single write
cycle. Following the initial Byte cycle, an additional 1
to 63 Bytes can be written in the same manner. Each
additional Byte load cycle must be started within 30 ~
from the preceding falling edge of WE or CE. Data can
be written and accessed 105 times in 64 Byte units.
WE - - - - - - - " I .
CE
,
,,
,,
,,
,,
,,
Data Polling
Data Polling allows the status of the EEPROM to
be determined. If the EEPROM is set to Read mode
during a Write cycle, an inversion of the last Byte of
data to be loaded outputs from 1/07 to indicate that the
EEPROM is performing a Write operation.
5V
Wmuumuu 0 V
OE
Ready/Busy Signal
The Ready/BUSy signal also allows the status of
the EEPROM to be determined. The Ready/BUSy
signal is high impedence except in the write cycle and
is lowered to VOL after the first write signal. At the end
of a write cycle, the Ready/SiiSy signal changes to
high impedence.
____~m-,mu- ~~
,,
,
,,
----:,
,,
,
,,
:---
, ,,
20 ns max
(DP.HN58Cl00l)
WE and CE Pin Operation
During a write cycle, addresses are latched by the
falling edge of WE or CE, and data is latched by the
rising edge of WE or OE.
Write/Erase Endurance, and Data Retention
The endurance with page programming is 105
cycles (1% cumulative failure rate) and the data
retention time is more than 10 years when a device is
programmed less than 1Q4 cycles.
Data Protection
To protect the data during operation and power
on/off, the HN58C257 has:
1. Data protection against Noise on Control Pins
(CE, OE, WE) during Operation.
During readout or standby, noise on the control
pins may act as a trigger and turn the EEPROM to
programming mode by mistake. To prevent this
phenomenon, the HN58C257 has a noise
cancellation function that cuts noise if its width is
20 ns or less in programming mode. Be careful not
to allow noise of a width of more than 20 ns on the
control pins.
HITACHI
2-52
Hitachi America, Ltd,
·2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
HN58C257 Series
(Example)
Vcc
,
RES
,
--'---II
...
\,---+-,,
,,
,
,
,,
·unprogrammable
L.oI- _ - ....
--~
·unprogrammable
(DPexe.HN58Cl 001)
• FUNCTIONAL DESCRIPTION (continued)
Data Protection (continued)
2. Data protection at Vee on/off
When RES is low, the EEPROM cannot be erased
and programmed. Therefore, data can be
protected ~ keeping RES low when Vee is
switched. RES should be high during programming
because it does not provide a latch function.
When Vco is turned on or off, noise on the control
pins generated by external circuits (CPU, etc) may
turn the EEPROM to programming mode by
mistake. To prevent this unintentional
programming, the EEPROM must be kept in an
unprogrammable, standby or readout state by
using a CPU reset~al to RES pin.
In addition, when RES is kept high..& ~on/off
timing, the input level of control pins (CE, OE, WE)
must be held as CE=Vcc or OE'=Low or WE=V cc
level.
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
2-53
HN58C1001 Series
- - - - - - - - - - - - - Preliminary
1M (12aK x a-bit) EEPROM
•
DESCRIPTION
The Hitachi HN58C1001 is a 1-Megabit CMOS Electrically
Erasable Programmable Read Only Memory (E!:PROM) organized
as 131,072 x 8-bits. The HN58C1001 is capable of in-system
electrical Byte and Page reprogrammability.
.
The HN58C1001 achieves high speed access, low power
consumption, and a high level of reliability by employing advanced
MNOS memory technology and CMOS process and circuitry
technology.
The HN58C1 001 has a 128-Byte Page Programming function to
make its erase and write operations faster. The HN58C 1001 features
Data Polling and a Ready/Busy signal to indicate completion of erase
and programming operations.
The HN58C1001 provides several levels of data protection.
Hardware data protection is provided with the RES pin, in addition to
noise protection on the WE signal and write inhibit on power on and
off. Software data protection is implemented using the JEDEC
Optional Standard algorithm.
The HN58C1001 is designed for high reliability in the most
demanding applications. Data retention is specified for 10 years and
erase/Write endurance is guaranteed to a minimum of 100,000
cycles in the Page Mode.
The HN58C1001 is offered in 32-pin Plastic DIP and 32-lead
PlastiC SOP and TSOP packages. The HN58C1 001 TSOP is offered
in both standard and reverse bend pinouts .
•
FEATURES
• Single Power Supply:
Vcc=5V± 10%
• High Speed Access Times:
120 ns/150 ns (max)
• Low Power Dissipation:
Active Current: 20 mW/MHz (typ)
Standby Current: 100 IlW (max)
• Automatic Programming:
Automatic Page Write: 10 ms (max)
128 Byte Page Size
Automatic Byte Write: 10 ms (max)
• Data Polling and Ready/Busy Signals
• Hardware Data Protection with RES pin
• Data Protection Circuitry on Power On/Off
• Software Data Protection Algorithm
• Data Retention: 10 years
• EraselWrite Endurance: .
100,000 cycles in Page Made
• Packages:
32-pin Plastic DIP
32-pin Plastic SOP
32-lead Plastic TSOP (Type I)
(DP-32)
(FP-32D)
(TFP-32DA and TFP-32DAR)
HITACHI
2-54
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN58C1001 Series
•
ORDERING INFORMATION
Type No.
HN58C1001 P-12
HN58C1001 P-15
HN58C 1001 FP-12
HN58C 1001 FP-15
HN58C1001T-12
HN58C1001T-15
HN58C1 001 R-12
HN58C1001 R-15
•
Access Time
120 ns
150 ns
120 ns
150 ns
120 ns
150 ns
120 ns
150 ns
Package
32-pin Plastic DIP
(DP-32)
32-lead Plastic SOP
(FP-32D)
32-lead Plastic TSOP
(TFP-32DA)
32-lead Plastic TSOP
(TFP-32DAR)
Reverse bend
PIN ARRANGEMENT
•
HN58C1001P Series
HN58C1001FP Series
RdylBusy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AO
1/00
1/01
1/02
Vss
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16
32·PIN
DIP
32·LEAD
SOP
TOP VIEW
PIN DESCRIPTION
Pin Name
Function
·Ao - A16
Address
1/00 - 1/07
Input/Output
Vee
OE
Output Enable
A15
RES
WE
A13
AS
A9
A11
OE
A10
CE
1/07
1/06
1/05
1/04
1/03
CE
Chip Enable
WE
Write Enable
Vee
Power Supply
Vss
Ground
Rdy/Busy
Ready/Busy
RES
Reset
(PinD32. HN58C 1001)
HITACHI
Hitachi America. ltd .• 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819 • (415) 589-8300
2-55
HN58C1001 Series
•
PIN ARRANGEMENT (cont.)
HN58C1001T Series
A4
A3
A2
AS
A6
A1
AO
A7
A12
1/00
1/01
1/02
Vss
1/03
1/04
1/05
1/06
I/QZ
CE
A10
A14
A16
ROYIBusy
Vcc
A15
RES
WE
A13
A8
A9
A11
STANDARD PINOUT
32-LEAD
TSOP
TOP VIEW
o
OE
(PinT132.HN58C1001T)
HN58C1001R Series
A4
__
r---------------------------------~
17
AS
A6
18
19
20
A7
M2
A14
~
A16
ROYIBusy
Vec
A
15
22
23
24
25
6
REVERSE PINOUT
32-LEAD
TSOP
TOP VIEW
R~
WE
A13
A8
A9
A11
27
28
29
30
31
32
0
A3
A2
A1
AO
1/00
1/01
1/02
Vss
1/03
1/04 .
1/05
1/06
1/07
CE
A10
OE
(PinT132.HN58C1 001 R)
•
BLOCK DIAGRAM
yyCC
ss
0----f1.
cr--+j
1100 -- 1107
High Voltage Generator
ReadylBusy
'---------'
CE
We~~-,------,--r----_t--~
REs
AO
I
AS
Add---+I....____________
-'
IlOO -
1/07
_ss
Buffer and
Latch
A7
I
A16
(BD.HN58Vl00l )
HITACHI
2-72
Hitachi America. Ltd .• 2000 Sierra Point Pkwy.· Brisbane. CA 94005·1819 • (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN58V1001 Series
•
MODE SELECTION
Mode
CE
OE
WE
RES
RDYIBusy
1/0
DOUT
High-Z
Read
V,L
V,L
V,H
VH
High-Z
Standby
V,H
X
X
X
High-Z
Write
V,L
V,H
V,L
VH
High-Z-VoL
Din
Deselect
V,L
v',H
V,H
VH
High-Z
High-Z
Write Inhibit
X
X
V,H
X
-
X
V,L
X
X
-
Data Polling
V,L
V,L
V,H
VH
Data Out (1/07 )
X
X
X
V,L
VOL
High-Z
Program
Note:
•
1.
X = Don't Care
FJ
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Vee
V,N
-0.6 to +7.0
V
-0.5 to +7.0
V
Operating Temperature Range 3
TOPR
oto +70
°C
Storage Temperature Range
TSTG '
-55 to +125
°C
Item
Supply Voltage
Input Voltage
Notes:
•
High-Z
1.
2.
1
1
2
Relative to V55'
V,N min =-3.0V for pulse width:S; 50 ns.
CAPACITANCE (T. =25°C, f = 1MHz)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Capacitance
C'N
pF
V,N =OV
COUT
-
6
Output Capacitance
-
12
pF
VOUT =OV
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
2-73
HN58V1001 Series
•
DC ELECTRICAL CHARACTERISTICS
(Vee = 2.7 to 5.5 V, T. = 0 to 70°C)
Item
Typ.
Max.
Unit
Test Condition
-
-
2
~
Vee = 3.6 V, VIN = 3.6 V
ILO
-
-
2
/-lA
Vee = 3.6 V, Vour = 3.6 V/O.4 V
Ice,
-
~
lee2
1
mA
CE = Vee
CE = VIH
Icc3
-
-
20
-
10
mA
lOUT = 0 mA, Duty = 100%,
Cycle = 1 !-lS
-
-
25
mA
lOUT = 0 mA, Duty = 100%,
Cycle = 250 ns
VIL
-0.3 2
V
1.9 3
Vee+ 0 .3
V
VH
Vee -1.0
Vee + 1
V
VOL
-
0.4
V
IOL = 2.1 mA
VOH
VccxO.8
-
0.8
VIH
-
V
IOH = -400 ~
,
III
Output Leakage Current
Standby Vee Current
Operating Vee Current
Input Voltage
Output Voltage
Notes:
•
Min.
Symbol
Input Leakage Current
1.
2.
2.
III on RES = 100 ~ max.
VI Lmin = -1.0 V for pulse width::; 50 ns.
V,Hmin = 2.2 V for Vee = 3.6 to 5.5 V.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(T. = 0 to 70°C, Vec = 5V ± 10%)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 V to 2.4 V
::;20 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V, 1.8 V
HN58V1001·25
Item
Symbol
Test Condition
Min.
Max.
Unit
250
ns
CE = OE = VI L. WE = VIH
teE
-
250
ns
OE = VIL. WE = VIH
Output Enable Access Time
tOE
10
90
ns
CE = V,L.WE = VIH
Output Hold to Address
Change
tOH
0
-
ns
cr = OE = VI L. WE = VIH
Output Disable to High-Z'
tOF
0
70
ns
cr = VIL. WE = VIH
tOFR
0
350
ns
CE = DE = VI L. WE = VIH
tAR
0
450
ns
CE = OE = VIL. WE ='VIH
Address Access Time
Chip Enable Access Time
RES to Output Delay
Note:
tACC
1.tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
2-74
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN58V1001 Series
•
READ TIMING WAVEFORM
x
Address
X
tACC
/
~
tCE
t
/
tOF
JOE
High
////
Data Out
r-...
Data Out Valid
"""
tRR
V
........
~
/
tOFR
(TO.R.HN58Cl00l)
•
AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
Item
Symbol
Min.'
Typ.
Max.
Unit
Address Setup Time
tAS
0
-
ns
Chip Enable to Write Setup Time
-
tes
0
Write Pulse Width
tew
250
Address Hold Time
tAH
150
Data Setup Time
tos
100
Data Hold Time
loH
0
Chip Enable Hold Time
lcH
0
Output Enable to Wrne Setup Time
tOES
0
Output Enable Hold Time
tOEH
0
Write Cycle Time
lwc
10
Byte Load Window
tal
100
Time to Device Busy
loa
tRP
120
tRES
1
RES to Write Setup Time
Vee to RES Setup Time
Note:
1.
J
100
Test Condition
ns
ns
ns
ns
ns
ns
ns
ns
ms
Ils
ns
Ils
Ils
Use this device in a longer cycle than this value.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-75
HN58V1001 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (WE Controlled)
Address
CE
WE
tOES
OE
tos
tOH
Din
tos
Rdy/Busy
tRP
tRE
RES
Vee
(TD.BE1.HN58C1001)
HITACHI
2-76
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA94005-t819' (415) 589-8300
HN58V1001 Series
•
BYTE ERASE AND BYTE WRITE TIMING WAVEFORM (CE Controlled)
Address
CE
WE
tOES
OE
tos
tOH
Din
toe
Rdy/Busy
tRP
tR
RES
Vee
(TD.BE2.HN58C1 001)
HITACHI
Hitachi America. Ltd. ·2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
2-77
HN58V1001Serles
•
-,
AC ELECTRICAL CHARACTERISTICS FOR PAGE ERASE AND PAGE WRITE OPERATIONS
Item
Symbol
Min. 1
Typ.
Max.
Unit
Address Setup Time
tAS
0
-
-
ns
Chip Enable toWrite Setup Time
tcs
!wp2
0
-
-
ns
250
ns
tcw3
250
-
-
-
-
ns
-
ns
-
ms
J.1S
ns
Write Pulse Width
Address Hold TIme
tAH
150
Data Setup Time
fos
100
Data Hold Time
tOH
0
Chip Enable Hold TIme
tCH
0
-
Output Enable to Wr~e Setup Time
tOEs
0
-
Output Enable Hold Time
tOEH
0
Data Latch Time
Iol
300
Write Cycle Time
!wc
15
-
tal
100
Byte Load Cycle
tSlC
0.55
-
30
Time to Device Busy
toe
120
RES to Write Setup Time
tRP
100
-
Vco to RES Setup Time
tRES
1
-
-
Byte Load Window
Notes:
1.
2.
3.
Test Condition
ns
ns
ns
ns
ns
ns
J.1s
J.1S
J.1S
Use this device in longer cycle than this value.
WE controlled operation.
CE controlled operation.
HITACHI
2-78
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58V1001 Series
•
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (WE Controlled)
Address
AOto A16
WE
Din
Rdy/Busy
(TD.PE1.HN58Cl00l)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
2-79
HN58V;1001Series' - - - - - - - - - - - - - - - - - - - •
PAGE ERASE AND PAGE WRITE TIMING WAVEFORM (CE Controlled)
Address
AOto A16
Din
Rdy/Busy
(TD.PE2.HN58Cl 001)
HITACHI
2-80
Hitachi America, Ltd.· ~OOO Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN58V1001 Series
•
AC ELECTRICAL CHARACTERlsncs FOR DATA POLLING OPERAnON
Item
Output Enable Hold Time
OUtput Enable to Write Setup TIme
Write Start Time
Write Cycle Time
Symbol
Min.
Typ.
Max.
Unit
1o.:H
1o.:s
0
-
-
ns
0
-
-
ns
tow
150
-
-
ns
1wc
-
-
15
ms
Test Condition
• DAn POLLING TIMING WAVEFORM
Address
An
XXXXXXXXXXX~~XXXX'
An
XXXX
1/07
twc
(TD.DP.HN58C1001)
HITACHI
. Hitachi America, Ltd.· 2000 Sierra.Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
2-81
HN58V100t Series···· - - - - - . . , . . - - - - - - - - - - - - - - •
AC ELECTRICAL CHARACTERISTICS FOR SOFTWARE
DATA PROTECTION CYCLE OPERATION
Item
Byte Load Cycle Time
Write Cycle Time
Symbol
Min.
Typ.
Max.
1m.c
twc
0.35
-
30
IlS
-
ms
10
Unit
Test Condition
• . SOFTWARE DATA PROTECTION TIMING WAVEFORM (Protection Mode)
VccJ>~
tBLC
Address
Data
5555
AA
twc
~
2AAA
55
5555
AO
Write Address
Write Data
(TD.SD1.HN58Cl00l)
•
SOFTWARE DATA PROTECTION TIMING WAVEFORM (Non-Protection Mode)
Vcc----f.~~'
twc
Normal
1----="----1 mode
Address
Data
5555 2AAA 5555
AA
55
80
5555 2AAA
AA
55
~~
5555
20
(TD.SD2.HN58Cl00l )
HITACHI
2-82
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN58V1001Serles
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment. the device will automatically match its
own erase and programming algorithm.
•
HN58V1001 SERIES IDENTIFIER CODE
Identifier
AD
1/°7
1/°6
1/°5
1/°4
1/°3
Manufacturer Code
V1L
0
0
0
0
0
1
Device Code
V1H
0
1
0
1
1
0
Notes:
1.
2.
3.
Vee =2.7 to 5.5 V
Ag= 12.0V±0.5V
1/°2
1/°0
Hex Data
1
1
07
0
0
58
110,
_
A,-Ag. A,0-A,6' CE'. OE = V1L• WE = V1H
HITACHI
Hitachi America. Ltd .• 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
2-83
HN58V1oo1 series
•
FUNCTIONAL DESCRIPTION
Automatic Page Write
The Page Write feature allows 1 to 128 Bytes of
data to be written into the EEPROM in a single cycle
and allows the undefined data within 128 Bytes to be
written corresponding to the undefined address (Ao to
As). Loading the first Byte of data, the data load
window of 30 J1S opens for the second. In the same
manner each additional Byte of data can be loaded
within 30 J1S. In case CE' and WE are kept high for 100
J1S after data input, the EEPROM enters erase and
write automatically and only the input data are written
into the EEPROM. In Page mode the data can be
written and accessed 105 times per page, and in Byte
mode 1()4 times per Byte.
Data Polling
Data Polling allows the status of the EEPROM to
be determined. If the EEPROM is set to Read mode
during a Write cycle, an inversion of the last Byte of
data to be loaded outputs from 1/07 to indicate that the
EEPROM is performing a Write operation.
Write Protection
(1) Noise protection: Noise on a write cycle will
not act as a trigger with a iiVE pulse of less
than 20 ns.
(2) Write inhibit: Holding O"E" low, WE high, or CE
high, inhibits a write cycle during power on/off.
Data Protection
To protect the data during operation and power
on/off, the HN58V1001 has:
1. Data protection· against Noise on Control Pins
(CE, OE, WE) during Operation.
During readout or standby, noise on the control
pins may act as a trigger and tum the EEPROM
to programming mode by mistake. To prevent
this phenomenon, the HN58V1001 has a noise
cancellation function that cuts noise if its width is
20 ns or less in programming mode. Be careful
not to allow noise of a width of more than 20 ns
on the control pins.
WE - - - - - - , .
CE
5V
W-------------- 0 V
OE
WE and CE Pin Operation
During a write cycle, addresses are latched by the
falling edge of WE or CE, and data is latched by the
rising edge of WE or CE.
Write/Erase Endurance and Data Retention
The endurance with page programming is 105
cycles (1% cumulative failure rate) and the data
retention time is more than 10 years when a device is
programmed less than 104 cycles.
----'~---------- ~.~
,,
,,,
--1,
:......, ,,
20 ns max
,,
(DP.HN58C1001)
HITACHI
2-84
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN58V1001 Series
(Example)
VCC
,
,
RES
--!-----'!r--_\'-+-:_
,
,
:-----i
,
,
*unprogrammable
,
I
I
I
.... ----:,
*unprogrammable
I
(DPexe.HN58Cl00l)
• FUNCTIONAL DESCRIPTION (continued)
Data Protection (continued)
2. Data protection at Vcc on/off
When RES is low, the EEPROM cannot be erased
and programmed. Therefore, data can be protected by keeping RES low when Vcc is switched.
RES should be high during programming because
it does not provide a latch function.
When Vcc is turned on or off, noise on the control
pins generated by external circuits (CPU, etc) may
turn the EEPROM to programming mode by mistake. To prevent this unintentional programming,
the EEPROM must be kept in an unprogrammable,
standby or readout state by using a CPU reset
signal to
pin.
In addition, when RES is kept high at Von/off
timing, the input level of control pins (CE,
WE)
must be held as CE=vcc or OE=Low or WE=vcc
level.
3. Software data protection
To prevent unintentional programming caused by
noise generated by external circuits, HN58V1001
has a Software data protection function. In
Software data protection mode, 3 Bytes of data
must be input before the Write data. These Bytes
can switch the Non-Protection mode to the
Protection mode.
Address
Data
5555
M
m
&,
.u.
.u.
2AAA
55
.u.
.u.
5555
AO
.u.
.u.
Write Address Write Data
(Normal Data Input)
The Software data protection mode can be
cancelled by inputting the following 6 Bytes. This
changes the HN58V1001 turns to the NonProtection mode and it can write data normally.
When the data is input during the cancelling cycle,
the data cannot be written.
Address
Data
5555
AA
.u.
.u.
2AAA
55
.u.
.u.
5555
80
.u.
.u.
5555
AA
.u.
.u.
2AAA
55
.u.
5555'
.u.
20
HITACHI
Hitachi America,
Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
2-85
NONVOLATILE MEMORY DATA BOOK
Section Three
Flash Memory
HITACHI
HN28F101 Series
- - - - - - - - - - - - - - Preliminary
1M (128K x 8-blt) Flash Memory
•
DESCRIPTION
The Hitachi HN28F101 isa 1-Megabit CMOS Flash
Memory organized as 131,072 x 8-bit. The HN28F101 is
capable of in-system electrical chip erasure and
reprogramming.
The HN28F101 programs and erases data with a 12 V
Vpp supply and a 5 V Vee supply. The HN28F101 conforms
to the JEDEC Standard Dual-Supply EEPROM Command
Set. Its fast, high-reliability programming algorithm is initiated
with Command Inputs. There are two methods of erasing
the HN28F1 01: Manual and Automatic, both are initiated
with Command Inputs.
The Manual Chip Erase method follows a fast, highreliability erase algorithm. The Automatic Chip Erase function
erases all data automatically without external control; Status
Polling is used to inform the CPU of erase completion. Both
erase methods provide a fast erase time without voltage
stress to the device or deterioration in data reliability.
Hitachi's HN28F1 01 is offered in JEDEC-Standard ByteWide EPROM pinouts in 32-pin Plastic DIP and 32-lead
PLCC, TSOP, and SOP packages. This allows an easy
upgrade to the HN28F4001, 4 Megabit Flash Memory, as
well as socket replacement with EPROMs and Mask ROMs.
The HN28F1 01 TSOPpackage is offered in both standard
and reverse bend pino~ts .
•
FEATURES
• Dual Power Supply:
Vcc =5V±10%
Vpp = 12.0 V ± 0.6 V (Erase/Program)
• Fast Access Times:
120 ns/150 ns/200 ns (max)
• Low Power Dissipation:
Read Current:
30 mA (typ)
Standby Current: 20 IIA (max)
• Byte Programming:
Programming Time: 25 lIS/Byte (typ)
Address, Data, Control Latch Function
• Automatic Chip Erase Function:
Erase Time: 1 sec (typ)
Internal Pre-Write and Erase Verify
Status Polling FunMion
• Erase Endurance:
10,000 times (min)
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
EPROM and Mask ROM Compatible
• Packages:
32-pin Plastic DIP
32-lead PLCC
32-lead Plastic TSOP (Type I)
32-lead Plastic SOP
(DP-32)
(CP-32)
(TFP-32D and TFP-32DR)
(TFP-32DA and TFP-32DAR)
(FP-32D)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.' Brisbane, CA9400S-1819· (41S) 589-8300
3-1
HN28F101 Series - - - - - - - - - - - - - - - - - - - - •
ORDERING INFORMATION
Type No.
HN28F101P-12
HN28F1 01 P-15
HN28F101 P-20
HN28F101CP-12
HN28F101CP-15
HN28F1 01 CP-20
HN28F101TD-12
HN28F101TD-15
HN28F1 01 TD-20
HN28F1 01 RD-12
HN28F101RD-15
HN28F1 01 RD-20
Access Time
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
HN28F101T-12
HN28F101T-15
HN28F101T-20
HN28F101R-12
HN28F1 01 R-15
HN28F1 01 R-20
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
HN28F101FP-12
HN28F1 01 FP-15
HN28F1 01 FP-20
120 ns
150 ns
200 ns
•
Package
32-pin Plastic DIP
(DP-32)
32-lead PLCC
(CP-32)
32-lead Plastic TSOP
(TFP-32D)
8x20mm
32-lead Plastic TSOP
(TFP-32DR)
8 x 20 mm
Reverse bend
32-lead Plastic TSOP
(TFP-32DA)
8 x 14 mm
32-lead Plastic TSOP
(TFP-32DAR)
8 x 14 mm
Reverse bend
32-lead Plastic SOP
(FP-32D)
PIN ARRANGEMENT
HN28F1 01 P Series
HN28F1 01 FP Series
HN28F101CP Series
\lpp
vee
A16
A15
A12
A7
AS
AS
A4
A3
WE
NC
A2
Al0
~'!!.~&:8IW()
«<»3:z
A7
A6
A5
A4
A3
A2
Al
AO
1/00
A14
A13
AS
A9
All
OE
Al
AO
1/00
1/01
1/02
CE
1/07
Vss
1/03
1/06
5
6
7
8
9
10
11
12
13
32·LEAD
PLCC
TOP VIEW
A14
A13
A8
A9
All
OE
Al0
CE
1/07
1/05
1104
(PinD32.HN28F1 01)
(PinQ32.HN28F1 01)
HITACHI
3-2
Hitachi America, Ltd. '2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN28F101 Series
•
PIN ARRANGEMENT (continued)
HN28F10HD Series
HN28F1 OH Series
A11
A9
A8
A13
A14
NC
WE
Vee
Vpp
A16
A15
A12
A7
A6
AS
A4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
STANDARD PINOUT
32-LEAD
TSOP
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DE
A10
CE
1/07
1/06
1105
1104
1/03
Vss
1/02
1/01
1100
AO
A1
A2
A3
(PinT132.HN28F101T)
HN28F1 01 RD Series
HN28F1 01 R Series
DE
A10
CE
1/07
1/ 06
1105
1/04
1/03
Vss
1/02
1/01
1/00
AO
A1
A2
A3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
~
REVERSE PINOUT
32-LEAD
TSOP
TOP VIEW
(Top view)
•
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
Vee
Vpp
A16
A15
A12
A7
A6
AS
A4
(PinT132.HN28F101 R)
PIN DESCRIPTION
Pin Name
Function
Ao - A16
Address
1/00 - 1/07
Input/Output
C"E
Chip Enable
OE
Output Enable
WE
Write Enable
Vee
Power Supply
Vpp
Programming Supply
Vss
Ground
NC
No Connection
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-3
HN28F101 Series - - - - - - - - - - - - - - - - - - - - - - •
BLOCK DIAGRAM
'1 o - - - - - - - l
x-
A9
1024 x 1024
Memory Matrix
Decoder
AI2
I o-------IH
AIS
UOOo--r--H
I
1/07o---+---..-H
Ceo--rl
Oe O-~H
A/W/E
Control
ArI"--r"LJ
AO-A4,
AIO, All
WE o...+-H
Vee
0++-+-
[!3>- :High Threshold Inverter
Vpp
Vss
(BD.HN28F1 01)
•
MODESELECTION
Mode
CE
OE
WE
Ag
1/00 to 1/07
VIL
VIL
VIH
Vee
VIL
VIH
VIH
Ag
XS
DOUT
High-Z
Standby
Vee
VIH
X
X
X
High-Z
Identifier I
Vee
VIL
VIL
VIH
10
Read 3,5
Vpp
VIL
VIL
VIH
VH2
Ag
Output Disable
Vpp
VIL
VIH
VIH
X
DOUT
High-Z
Standby
Vpp
X
X
X
High-Z
Vpp
Read
Command
Read
Vee
Output Disable
Write4
Notes:
1,
2,
3,
4,
5.
6,
6
VIH
VIL
Vpp
A9
DIN
Device Identifier Code can be output in Command Program Mode, Refer to Command
Address and Data Input Table,
11.4 V S VH S 12.6 V
Data can also be read when 12 V is applied to Vpp' Device Identifier Code can be output by
Command Inputs. See Device Identifier Mode Description Table for more details.
Refer to Command Address and Data Input Table. Data is programmed, erased, or verified
after inputting Commands.
Status of Automatic Erase can be verified in this. mode by Status Polling on 1/07' I/0s to 1/06
are in high impedance states.
X = Don't Care. Vpp =0 V to Vee'
VIL
VIH
HITACHI
3-4
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN28F101 Series
•
COMMAND ADDRESS AND DATA INPUT
First Cycle
Bus Cycles Operation Address 2 Data 3
Required
Mode 1
Command
Read
1
Write
X
OOH
Read
RA
Read Identifier Codes
2
Write
X
90H
Read
IA
DoUT
ID
Set-up Erase/Erase 5
2
Write
X
20H
Write
X
20H
Erase Verify
4
2
Write
EVA
AOH
Read
X
EVD
Setup Auto Erase/Auto Erase 6
2
Write
X
30H
Write
X
30H
Setup Program/Program 7
2
Write
X
40H
Write
PA
PD
Program Verify 7
2
Write
X
COH
Read
X
PVD
Reset
2
Write
X
FFH
Write
X
FFH
Notes:
1.
2.
3.
4.
5.
6.
7.
•
Refer to Command Program Mode in Mode Selection about operation mode.
Refer to Device Identifier Mode. IA =Identifier Address, PA = Programming Address, EVA =
Erase Verify Address, RA = Read Address.
Refer to Device Identifier Mode. PA are latched by Programming Command. ID = Identifier
Output Code, PD =Programming Data, PVD =Programming Verify Output Data, EVD =Erase
Verify Output Data.
Command latch default value when applying 12 V to Vpp is "OOH". Device is in Read Mode after
Vpp is set to 12 V (before other Command is input).
All data in the chip is erased. Erase data according to the Manual Chip Erase Flowchart.
All data in the chip is erased. Data is automatically programmed to OOH and erased
automatically by internal logic circuitry. External Manual Erase Verify is not necessary.
Erasure completion is verified by Status Polling on I/Or
Program data according to the Programming Flowchart.
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
-0.6 to +7.0
V
Vpp
-0.6 to +14
V
VIN,VOUT
-0.6 to +7.0
V
°C
Storage Temperature Range 3
TOPR
TSTG
oto +70
-55 to +125
°C
Temperature Under Bias
Ts,AS
-10 to +80
°C
Supply Voltage 1
Programming Voltage
1
All Input and Output Voltage 1,2
Operating Temperature Range
Notes:
•
Second Cycle
Operation Address 2 Data 3
Mode 1
1.
2.
3.
Relative to Vss'
V1N and VOUT = -2.0V for pulse width S 20 ns.
Device storage temperature range before programming.
CAPACITANCE (Vee = 5V ± 10%, Vss = OV, T. = 0 to 70°C, f = 1MHz)
Item
Input Capacitance
Output Capacitance
Symbol
Min.
Typ.
Max.
Unit
Test Condition
C1N
-
-
6
pF
V1N = OV
12
pF
VOUT = OV
COUT
HITACHI
Hitachi America, Ltd.· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-5
HN28F101 Series - - - - - - - - - - - - - - - - - - - - •
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vpp = Vee - t to Vee' T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
2
IlA
IlA
VIN = 0 V to Vee
ILo
-
2
Output Leakage Current
VOUT = 0 V to Vee
6
15
mA
louT = 0 mA, f = 1 MHz
25
50
mA
lOUT = 0 mA, f = 8 MHz
-
1
mA
CE = VIH
20
CE = Vce
Ippl
-
Item
Operating Vec Current
Icci
Icc2
Standby V cc Current
ISBI
ISB2
VppCurrent
Input Voltage 3
Output Voltage
Notes:
1.
2.
3.
•
VIL
-0.3 '
VI"
2.2
VOL
VOH
2.4
20
IlA
IlA
0.8
V
Vcc + 12
V
0.45
V
IOL = 2.1 mA
-
V
IOH = -400 IlA
Vpp= 5.5 V
VI Lmin = -2.0 V for pulse width ~ 20 ns.
VIH max = Vcc + 1.5 V for pulse width ~ 20 ns. If V1H is over the specified maximum value,
Read operation can not be guaranteed.
Only defined for DC and long cycle function test. VI Lmax = 0.45 V, V1H min = 2.4 V for AC
function test.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ±10%, Vpp = Vss to Vee' T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V12.4 V
~10 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V 12.0V
HN28Fl01-12
Item
Max.
Min.
Max.
Min.
Max.
Test
Unit
tAec
120
-
150
ns
CE = OE = V1L
-
150
200
ns
QE"V1L
60
-
70
-
200
120
80
ns
CE = V1L
0
50
0
60
ns
CE = V1L
5
-
5
-
ns
CE=OE=V 1L
teE
Output Enable Access
Time
tOE
-
Output Disable to High-Z 1
tOF
0
40
taH
5
-
Output Hold to Address
Change
Note:
1.
HN28Fl0l·20
Min.
Chip Enable Access Time
Address Access Time
HN28Fl0l·15
Symbol
.
Condition
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
3-6
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN28F101 Series
•
READ TIMING WAVEFORM
Address
~
CE
Standby Mode
)
Active Mode
L
tCE
\
OE
I
Standby Mode
I
High
WE
tOF
tOE
~
tACC~
2
////.
Data Out
Data Out Valid
\\\\
~
r/
(TD.R.HN28F101)
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING AND ERASE OPERATIONS
(Vcc = 5V ± 10%, Vpp = 12.0 V ± 0.6 V, T. = 0 to 70°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
2
!LA
!LA
VIN = 0 V to Vcc
ILO
-
2
Output Leakage Current
-
Vour=OVtoVcc
6
15
mA
lOUT = 0 mA, f = 1 MHz
25
50
mA
lOUT = 0 mA, f = 8 MHz
2
10
mA
mA
Operating
Read
Program
IcC3
-
Erase
1CC4
-
10
40
Icc5
-
5
15
mA
Manual Erase
-
1
.rnA
CE = VIH
1SB2
-
20
Ippl
-
-
200
!LA
!LA
CE = Vcc
Read
Program
IpP2
5
30
mA
Programming
35
80
mA
Automatic Erase
Ipp4
-
10
30
mA
Manual Erase
0.8
V
VccCurrent
Ic02
Standby Vcc Current
VppCurrent
Erase
Input Voltage 3
Output Voltage
Notes:
1.
2.
3.
4.
5.
Iccl
IS81
IpP3
VIL
-0.34
-
VIH
2.2
VOL
-
-
VOH
2.4
-
Automatic Erase
Vpp= 12.6 V
Vcc + 15 'V
0.45
V
IOH = 2.1A
-
V
IOH = -400 jIA
vcc must be applied before V
and removed after Vpp'
Vpp must not exceed 14 V, including overshoot.
Device reliability maybe adversely affected if the device is installed or removed while Vpp =
12V.
VI L min = -1.0 V for pulse width S 20 ns.
If VIH is over the specified maximum value, programming operation cannot be guaranteed.
pp
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-7
HN28F101 Series - - - - - - - - - - - - - - - - - - - - •
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING AND ERASE OPERATIONS
(Vce = 5V ± 10%, Vpp = 12.0 v ± 0.6 V, T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V 12.4 V
~10 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V 12.0V
HN28F101-12
Symbol Min.
Item
Programming Cycle Time
fcwc
HN28F101-15
Min.
Max.
Min.
Max.
Unit
120
-
150
200
100
-
100
70
-
80
20
0
-
0
-
ns
100
-
6
-
6
-
!lS
tAS
0
-
0
Address Hold Time
tAH
60
60
Data Setup Time
tos
50
Data Hold Time
Address Setup Time
HN28F101-20
Max.
fwEP
70
Write Enable High Time
fwEH
20
Output Enable Setup Time
Before Command Prog.
tOEWS
0
-
Output Enable Setup Time
Before Verify
tOERS
6
-
tOH
10
Chip Enable Setup Time
tCES
0
Chip Enable Hold Time
Vpp Setup Time
tCEH
tvps
100
Vpp Hold Time
tVPH
100
Write Enable Pulse Width
0
50
10
0
0
0
60
50
10
0
0
100
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tVA
-
120
-
150
-
200
ns
Output Enable Setup Time
Before Status POlling
toeps
20
-
20
-
20
-
ns
Status Polling Access Time
tSPA
-
120
-
150
-
200
ns
Standby Time Before Prog.
tppw
25
-
25
-
25
-
~s
Erase Standby Time
Verify Access Time
tEr
9
11
9
11
9
11
ms
Output Disable Time
tOF
0
40
0
50
0
60
ns
Automatic Erase Time
tAEr
0.5
30
0.5
30
0.5
30
s
Notes:
1.
2.
3.
CE, OE, WE must be fixed high during VPP transition from 5 V to 12 V or from 12 V to 5 V.
Except for sending a Command Program, a Read operation at Vpp = 12 V is similar to a
Read operation at Vpp =VCC.
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
3-8
Hitachi America,
Ltd.' 2000 Sierra Point Pkwy.' Brisbane,CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN28F101 Series
•
PROGRAMMING FLOWCHART
The HN28F101 can be programmed with the fast, high-reliability programming algorithm shown in the
following flowchart. This algorithm provides faster programming time without volt~ stress to the device or
deterioration in reliability of programmed data. Random transition of CE, OE, and WE are not permitted when
executing this algorithm.
Write Setup Program Command
Write Program Command
Write Program Verify Command
Address + 1~Address
NO
YES
(FC.P.Flash)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94oo5-1819· (415) 589-8::100
3-9
HN28F101 Series - - - - - - - - - - - - - - - - - - - - •
MANUAL CHIP ERASE" FLOWCHART
The HN28F1 01 can be erased with the fast, high-reliability erase algorithm shown in the following flowchart.
This algorithm provides a fast erase time without volt~ stress to the device or deterioration in reliability ot
programmed data. Random transition of CE, OE, and WE are not permitted when executing this algorithm.
Program All Bytes to DOH (Note 1)
Write Setup Erase/Erase Command
Write Erase Verify Command
Address + 1~ Address
NO
NO
YES
Note 1. Refer to Programming Flowchart
(FC.E.Flash)
HITACHI
3-10
Hitachi America,
Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN28F101 Series
•
PROGRAMMING TIMING WAVEFORM
Setu Pro ram
Pro ram
Vee
5.0V--~--------------~--------------------_+--------------~--------
V
12 V
pp
5.0 V
Address
OE
1I00tOI/~
(TD.P.HN28F101)
•
MANUAL CHIP ERASE TIMING WAVEFORM
Setup Erase
5.0 V
Vee
Erase
Erase Verify
--+---------+-----+-----------+---
12 V
Vpp
5.OV
Address
(TD.E.HN28F1 01)
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.• Brisbane, CA94005-1819 • (415) 589-8300
3-11
HN28F101 Series - - - - - - - - - - - - - - - - - - - - •
AUTOMATIC CHIP ERASE TIMING WAVEFORM
The fast Automatic Erase algorithm shown in the following timing waveform can be applied. All of the data
in the chip is erased. External pre-write and erae verify are not required because the cells are pre-written, erased
and verified automatically by internal control circuitry. Erasure completion can be verified by Status POlling after
the Automatic Erase starts. Erasure completion can be verified by Status Polling. This algorithm provides a fast
erase time without any voltage stress to the device or deterioration in data reliability.
i-_~S_e_t_u'__p_A_u_to~E_ra_s_e~~__+_~A-'-u-"'to'--Erase & Status Polling.
Vec 5.0 V
V.
12 V
. 5.0V
PP
Address
CE
DE
WE
(TD.AE.HN28F1 01)
•
STATUS POLLING
The HN28F101 features Status Polling as a method to indicate that the embedded algorithms are either in
progress or completed. While the Automatic Chip Erase algorithm is in operation, the 1/°7 pin is lowered to VOl
until the erase operation is completed. Upon completion of the erase operation, the 1/°7 pin is set to VOH' The
Status POlling feature is only active during the Automatic Chip Erase algorithm.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN28F101 SERIES IDENTIFIER CODE
Identifier
AD
1/°7
1/°6
Manufacturer Code
VIL
0
Device Code
VIH
0
Notes:
11O,
1/°0
Hex Data
1
1
1
07
0
0
1
19
1/°5
1/°4
1/°3
1/°2
0
0
0
0
0
0
1
1
The HN28F101 Series Identifier Codes can be read by two methods:
1. Write 90H to the device with CE = VIL and AD =
= VIH (all other addresses are Don't
Care). The Device Code of 19H will appear after the fall of OE. The Manufacturer Code of
07H will appear after AD transitions to VI L'
2. Apply 12.0 V ± 0.6 V to A9 .with AD = VIH (all other addresses are LOW), Vpp = VcC' CE =
= VI Land WE = VIH' The Device Code of 19H will appear. After AD transitions to VI L the
Manufacturer Code of 07H will appear on the 110 lines.
m:
m:
HITACHI
3-12
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
HN28F4001 Series
- - - - - - - - - - - - - Preliminary
4M (512K x B-blt) Flash MemC)fY
•
DESCRIPTION
The Hitachi HN28F4001 is a 4-Megabit CMOS Flash
Memory organized as 524,288 x 8-bit. The HN28F4001 is
capable of in-system electrical chip and block erasure and
reprogramming.
The HN28F4001 programs and erases data with a 12 V
Vpp supply and a 5 V Vcc supply. The HN28F4001 conforms
to the JEDEC Standard Dual-Supply EEPROM Command
Set. Its Automatic Commands do not require complicated
external control to program or erase data because of its
automatic verify programming, chip erase and block erase
functions.
The block architecture of the HN28F4001 segments the
device into 32 blocks of 16KBytes each. This feature allows
the user to erase and reprogram one random block of data
and more than one block of data simultaneously.
Hitachi's HN28F4001 is offered in JEDEC-Standard
Byte-Wide EPROM pinouts in 32-pin Plastic DIP and 32lead SOP and TSOP packages. This allows an easy upgrade
from the HN28F101, 1 Megabit Flash Memory, as well as
socket replacement with EPROMs and Mask ROMs. The
HN28F4001 TSOP is offered in both standard and reverse
bend pinouts .
•
FEATURES
• Dual Power Supply:
Vcc =5V±10%
Vpp = 12.0 V ± 0.6 V (Erase/Program)
• Fast Access Times:
120 ns/150 nsl200 ns (max)
• Low Power Dissipation:
Read Current:
30 mA (typ)
Standby Current: 20 IlA (max)
• Automatic Byte Programming:
Programming Time: 10 lIS/Byte (typ)
Address, Data, Control Latch Function
Internal Automatic Program Verify
Data Polling Function
• Automatic Chip and Block Erase:
Erase Time: 1 sec (typ)
Internal Pre-Write and Erase Verify
Status POlling Function
• Block Architecture:
Block Size: 16KBytes x 32 Blocks
Simultaneous Erase of Multiple Blocks
• Erase Endurance:
10,000 times (min)
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
EPROM and Mask ROM Compatible
• Packages:
32-pin Plastic DIP
32-lead Plastic SOP
32-lead Plastic TSOP (Type I)
(DP-32)
(FP-32D)
(TFP-32D) and (TFP-32DR)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-13
HN28F4001Series----------------------•
ORDERING INFORMATION
Type No.
HN28F4001 P-12
HN28F4001 P-15
HN28F4001 P-20
HN28F4001FP-12
HN28F4001 FP-15
HN28F4001 FP-20
HN28F4001T-12
HN28F4001T"15
HN28F4001 T-20
HN28F4001 R-12
HN28F4001 R-15
HN28F4001 R-20
•
Access Time
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
Pilckage
32-pin Plastic DIP
(DP-32)
32-lead Plastic SOP
(FP-32D)
32-lead Plastic TSOP
(TFP-32D)
32-lead Plastic TSOP
(TFP-32DR)
Reverse bend
PIN ARRANGEMENT
•
Pin Name
HN28F4001 P Series
HN28F4001 FP Series
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
Vee
1
2
3
4
5
6
PIN DESCRIPTION
27
7
26
8 TOPsOP
25
VIEW
9
24
10
23
32·PIN
DIP
32-LEAD
11
12
22
21
13
20
1/00
1/01
1/02
14
19
15
18
VSS
16
17
Function
AD - AlB
Address
1/00 - 1/07
Input/Output
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vpp
Programming Supply
Vss
Ground
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
1/07
1/06
1/05
1/04
1/03
(PinD32.HN28F4001 )
HITACHI
3~ 14
Hitachi America,
Ltd .• 2000$ierra Point PkWy.- Brisbane, CA 94005-1819 • (415) 589-8300
----~--------------- HN28F4001
•
Series
PIN ARRANGEMENT (continued)
HN28F4001 T Series
Al1
A9
A8
A13
A14
A17
A18
1
32
31
30
!O
5
6
STANDARD PINOUT
32-LEAD
TSOP
TOP VIEW
7
Vee
Vpp
8
9
A16
A15
A12
A7
A6
AS
A4
10
11
12
13
14
15
16
OE
A10
CE
29
1107
28
27
26
25
24
23
1/06
1/05
1/04
1/03
Vss
22
1/02
1/01
21
20
19
18
17
AO
A1
A2
A3
1/00
(PlnT132.HN28F400H)
HN28F4001 R Series
OE
Al0
CE
1/07
1106
1105
1104
1103
Vss
1102
1/01
1100
AO
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
REVERSE PINOUT
32-LEAD
TSOP
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
B
All
A9
A8
A13
A14
A17
A18
Vee
Vpp
A16
A15
A12
A7
A6
AS
A4
(PinT132.HN28F4001 R)
HITACHI
Hitachi America, Ltd.· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-15
HN28F4001 S e r i e s - - - - - - - - - - - - - - - - - - - - •
BLOCK DIAGRAM
x-
AO-A7
Al0.A12
1/00
Decoder
1024 x 4096
Memory Matrix
o-~---H
\
1/07
o--+-~-H
CE
0---..---1
o--t--r--l ::>O-t~-L")
OE
R/W/E
Control
AO-A4.
Al0. All
Vee
Vpp
0-+--1--118><::>1
[B>- : High Threshold Inverter
Vss
(BD.HN2BF4001)
•
MODE SELECTION
Mode
Read
CE
OE
Ag
Ao
Read
VIL
V1L
Ag
Ao
Vpp
Vcc6
Output Disable
V1L
V1H
X
X
Vee
1/°0 to 1/°7
Dour
High-Z
Standby
V1H
X
X
X
Vee
High-Z
Identifier 1
V1L
V1L
V1L
Vee
Code"07"
V1L
VIL
VH2
VH2
V1H
Vee
Code"08"
Dour
High-Z
Command
Read 3.5
V1L
VIL
Ag
Ao
Vpp
Program
Standby
V1H
X
X
X
Vpp
Write 4
Notes:
1.
2.
3.
4.
5.
6.
V1L
V1H
Ag
Vpp
Ao
DIN
Device Identifier Code can be output in Command Program Mode. Refer to Command
Address and Data Input Table.
11.4 V ~ VH ~ 12.6 V
Data can also be read when 12 V is applied to VPP' Device Identifier Code can be output by
Command Inputs. See Device Identifier Mode Description Table for more details.
Refer to Command Address and Data Input Table. Data is programmed, erased, or verified
after inputting Commands.
Status of Programming and Erase can be verified in this mode. Status Outputs on 1/°7 ,
1/°0 to 1/°6 are in high impedance states.
X = Don't Care. Vpp = OV to Vcc'
HITACHI
3-16
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN28F4001 Series
•
COMMAND ADDRESS AND DATA INPUT
First Cycle
Second Cycle
Bus Cycles Operation Address 2 Data 3 Operation Address
Model
Required
~odel
Command
Read (Memory)
2
Data 3
1
Write
X
OOH
Read
RA
Read Identifier Codes
2
Write
X
90H
Read
IA
DOUT
10
Set-up Chip Erase/
Chip Erase 5
2
Write
X
20H
Write
X
20H
Set-up Block Erase/
Block Erase B
2
Write
X
60H
Write
BA
60H
Erase Verify 5
2
. Write
EVA
AOH
Read
X
EVD
Setup Auto Chip Erase/
Auto Chip Erase 6
2
Write
X
30H
Write
X
30H
Setup Auto Block Erase/
Auto Block Erase 9
2
Write
X
20H
Write
BA
DOH
Setup Program/Program 7
2
Write
X
40H
Write
PA
PO
Program Verify 7
2
Write
PA
COH
Read
X
PVD
Setup Auto Program/
Auto Program 10
2
Write
X
10H
Write
PA
PO
1 or 2
Write
X
FFH
Write 11
X
FFHll
Reset
Notes:
4
Refer to Command Program Mode in Mode Selection about operation mode.
Refer to Device Identifier Mode. IA = Identifier Address, PA = Programming Address, EVA =
Erase Verify Address, RA = Read Address, BA = Block Address. Addresses are latched on the
rising edge of chip-enable pulse.
3. Refer to Device Identifier Mode. PA are latched by Programming Command. 10 = Identifier
Output Code, PO =Programming Data, PVD =Programming Verify Output Data, EVD =Erase
Verify Output Data.
4. Command latch default value when applying 12 V to Vpp is "OOH". Device is in Read Mode after
Vpp is set to 12 V (before other Command is input).
5. All data in the chip is erased. Erase data according to the Manual Chip Erase Flowchart.
6. All data in the chip is erased. Data is automatically programmed to OOH and erased
by internal logic circuitry. External Manual Erase Verify is not required. Erasure completion
must be verified by Status Polling on I/Or·
7. Program data according to the Manual Programming Flowchart.
8. Block data indicated by BA is erased. Erase data according to the Manual Block Erase
Flowchart.
9. Block data indicated by BA is erased. Data is automatically programmed to OOH and erased
by internal logic circuitry. External Manual Erase Verify is not required. Erasure completion
must be verified by Status Polling on 1/07.
10. One Byte of data is programmed. Data is programmed automatically by internal logic circuit.
External program verify is not required. Program completion must be verified by Data Polling
on 1/07.
11. Write Reset Command twice to exit from program setup state or auto verify program setup
state. Write it once to exit from others.
1.
2.
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
3-17
3
HN28F4001 S e r i e s - - - - - - - - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Vee
-0.6 to +7.0
V
Vpp
-0.6 to +14.0
V
Ag Voltage 1,2
VIO
-0.6 to +13.5
V
All Input and Output Voltage 1,2
VIN, VOUT
-0.6 to +7.0
V
Operating Temperature Range
TOPA
o to +70
°C
TSTG
-65 to +125
°C
TBIAS
-10 to +80
°C
1
Storage Temperature Range
3
Storage Temperature Under Bias
Notes:
1.
2.
3.
Relative to Vss.
VIN' VOUT and VI 0 min = -2.0V for pulse width s; 20 ns.
Device storage temperature range before programming.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
Input Capacitance
Output Capacitance
•
Unit
Programming Voltage 1
Supply Voltage
•
Value
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
CIN
-
-
6
pF
VIN=OV
12
pF
VOUT = OV
COUT
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vpp = Vss to Vee' T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Input Leakage Current
III
-
2
Output Leakage Current
ILO
-
!lA
!lA
VOUT = Vss to Vee
Operating Vee Current
leel
-
lee2
ISB2
-
Ippl
-
-
VIL
-0.3 '
-
0.8
V
VIH
2.2
-
Vee + 12
V
Item
Standby Vee Current
Vpp Current
Input Voltage 3
Output Voltage
Notes:
1.
2.
ISBl
2
VIN = Vss to Vee
30
mA
lOUT = 0 mA, f = 1 MHz
100
mA
louT = 0 rnA, f = 8 MHz
1
mA
CE = VIH
20
!lA
!lA
CE = Vee ± 0.3V
20
Vpp = 5.5 V
VOL
-
-
0.45
V
IOL = 2.1 rnA
VOH
2.4
-
-
V
IOH = -400 !lA
VI Lmin = -1.0 V for pulse width s; 50 ns.
VIH max = Vee + 1.5 V for pulse width S; 20 ns. If VIH is over the specified maximum value,
Read operation can not be guaranteed.
HITACHI
3-18
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN28F4001 Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(V cc =5V ± 10%, Vpp =V55 to VcC' Ta =0 to 70 DC)
Test Conditions
• input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V 12.4 V
:;;10 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0 V
HN28F400H2
Item
HN28F4001-20
Test
Conditions
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address Access Time
tACC
120
150
ns
CE = OE = V1L
tCE
150
200
ns
OE = V1L
60
70
-
200
Chip Enable Access Time
-
80
ns
CE
Output Enable Access
Time
tOE
-
Output Disable to High-Z'
tOF
0
30
0
35
0
40
ns
CE = V1L
Output Hold to Address
Chance
tOH
5
-
5
-
5
-
ns
CE = OE = V1L
Note:
•
HN28F4001·15
1.
120
= V1L
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven .
READ TIMING WAVEFORM
Address
CE
x
>-
Standby Mode
Active Mode
I
OE
/
tCE
\
/
tOF
to_H
--::.
tOE
~
t ACC --=-=-Data Out
Standby Mode
////.
\\\\
Data Out Valid
l\.
r/
(TD.R.HN28F4001 )
HITACHI
Hitachi America, Ltd. ·2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-19
HN28F4001· S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - •
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING AND ERASE OPERATIONS
(Vee = 5V ± 10%, Vpp = 12.0 V ± 0.6 V, T. = 0 to +70°C)
Symbol
Item
4.
5.
6.
VOUT = Vss to Vee
30
mA
lOUT = 0 mA, f = 1 MHz
100
mA
IOliT = 0 mA, f = 8 MHz
30
mA
Programming
30
mA
Erasing
15
mA
Programming Verify
Icc6
-
-
15
mA
Erase Verify
IS61
-
1
mA
CE = VIH
-
20
20
JlA
JlA
CE = Vcc ± 0.3 V
-
50
mA
Programming
50
mA
Automatic Erase
10
mA
Programming Verify
10
mA
Erase Verify
Icc3
Erase
IpP3
Program
Verify
Ipp4
-
Erase
Verify
Ices
-
-
VIL
-0.3 5
-
IS62
1.
2.
3.
VIN = Vss to Vee
JlA
Erase
Verify
Standby Vcc Current
Notes:
JlA
2
Test Conditions
lec5
Icc1
Icc2
Program
Output Voltage
Unit
2
Program
Verify
Read
Current
Input Voltage
Max.
-
Icc4
ILO
Vpp Current
Typ.
Erase
ILl
Output Leakage Current
Operating Vcc
Min.
-
Input Leakage Current
Read
Ipp1
Program
Ipp2
VIH
2.2
VOL
-
VOH
2.4
Vpp =12.6V
0.8
V
VCC +16
V
0.45
V
IOL = 2.1 mA
-
V
IOH = -400
JlA
Vcc must be applied before Vpp and removed after Vpp'
Vpp must not exceed 14 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while Vpp
= 12 V.
When CE = VIL. do not change Vpp from VIL to 12 V or 12 V to VIL.
VI Lmin = -1.0 V for pulse width $; 20 ns.
If VIH is over the specified maximum value, programming operatien cannot be guaranteed.
HITACHI
3-20
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589·8300
- - - - - - - - - - - - - - - - - - - - H N 2 8 F 4 0 0 1 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING AND ERASE OPERAnONS
(Vcc = 5V ± 10%, VPP =12.0 v ± 0.6 V, T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fal\ times:
• Output load:
• Reference levels for measuring timing:
0.45 V /2.4 V
:;;10 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V, 2.0V
HN28F400,.,2
Item
Max.
Min.
Max.
Min.
Max.
Unit
-
100
-
100
-
100
-
50
10
-
ns
100
100
-
ns
0
ns
typs
100
toES
100
Chip Enable Hold Time
teEH
20
Chip Enable Pulse Width
teEP
50
Address Setup Time
tAS
50
Address Hold Time
tAH
10
Data Setup Time
tos
50
Data Hold Time
tOH
10
teESP
100
CE Setup Time before
Status POlling
HN28F4001-20
Min.
Output Enable Setup Time
Vpp Setup Time
HN28F4001·15
Symbol
20
50
50
10
50
10
100
20
50
10
50
ns
ns
ns
ns
ns
ns
ns
teES
0
Chip Enable Setup Time
before Command Write
teESC
100
-
100
-
100
-
Chip Enable Setup Time
before Verify
teESv
6
-
6
-
6
-
VPP Hold Time
tyPH
100
100
-
100
30
35
-
40
Status Polling Access Time
-
120
-
150
.
-
ns
IoF
tSPA
-
200
ns
Verify Access Time
tvA
-
120
-
150
-
200
ns
tAETC
0.5
30
0.5
30
0.5
30
s
tAETB
0.5
30
0.5
30
0.5
30
s
Total Auto Verify Programming Time
tAVT
10
400
10
400
10
400
f.1S
Standby Time Before Programming
tppw
10
9.5
-
f.1S
ms
Block Address Load Cycle
~T
tBALC
9.5
-
10
9.5
-
10
70
300
70
300
70
300
ns
Block Address Load Time
~L
1
.
1
-
1
-
f.1S
Chip Enable Setup Time
Output Disable
Time3
Total Auto Chip Erase Time
Total Auto Block Erase Time
Erase Standby Time
Notes:
1.
2.
3.
0
ns
/.Ls
ns
CE and OE must be fixed high during VPP transition from 5 V to 12 V or from 12 V to 5 V.
Except for sending a Command Program, a Read operation at VPP =12 V is similar to a
Read operation at Vpp = Vcc.
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
3-21
HN28F4001 S e r i e s - - - - - - - - - - - - - - - - - - - - •
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One Byte of data is programmed. External programming verification is not required because these
operations are executed automatically by internal control circuitry. Programming completion can be verified
by Data Polling after the Automatic Programming starts. Device outputs reverse input data during auto
programming on 1/°7 , 1/00 to 1I0s are high impedance.
Setup Auto Program
Vcc 5V
Auto Program & Data Polling
------/--------+------------if----
12V
Vpp
OV
AO - A18
CE
OE
1107
Data Polling
1100-1106 ------<1
Data in
Command 10H
(TD.AP.HN28F4001 )
HITACHI
3-22
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
- - - - - - - - - - - - - - ' - - - - - - - - HN28F4001 Series
•
AUTOMATIC CHIP ERASE TIMING WAVEFORM
The fast Automatic Chip Erase algorithm shown in the following timing waveform can be applied. All of the
data in the chip is erased. External pre-write and erase verify are not required because the cells are pre-written
and data is erased automatically by internal control circuitry. Erasure completion can be verified by Status
Polling after the Automatic Erase starts. This algorithm provides a fast erase time without any voltage stress
to the device or deterioration in data reliability.
Setup Auto Chip Erase
Auto Chip Erase & Status Polling
Voo 5V----------;----------------+-----------------------+---------vpp
12V
OV
AO -A18
1/07 --------:-{I
Status Polling
1/00-1/06 - - - - - - - - - ( 1
Command 30H
Command 30H
(TD.ACE.HN28F4001 )
•
STATUS POLLING
The HN28F4001 features Status Polling as a method to indicate that the embedded algorithms are
either in progress or completed. While the Automatic Chip or Block Erase algorithm is in operation, the 1/07
pin is lowered to VOl.. until the erase operation is completed. Upon completion of the erase operation, the 1/07
pin is set to VOH•
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
3-23
HN28F4001Serles-------------------•
AUTOMATIC BLOCK ERASE TIMING WAVEFORM
The fast Automatic Block Erase algorithm shown in the following timing waveform can be applied. All of the
data in the block (16KBytes) indicated by A14 to A,s is erased. External pre-write and erase verify is not required
because the cells are pre-written and data in the block is erased automatically by internal control circuitry.
Erasure completion can be verified by Status Polling after the automatic erase starts. This algorithm provides
a fast erase time without any voltage stress to the device or deterioration in data reliability.
As indicated below, asingle random block or any combination of multiple blocks can be erased simultaneously.
Setup Auto Block Erase
v~
Vpp
Auto Block Erase &
Status Polling
5V----------r-------------------------------------+---------------+------12V
ov
A14-A18
1107
Status Polling
1100-1106 --------H~=L_-l
1/00
VOl
~
AO-A3
Al0 - A11
-j;I>o
High Threshold
Inverter
(BD.HN27C256H)
•
MODE SELECTION
Mode
Vpp
Vee
CE
OE
Ag
1/0
Read
Vee
Vee
VIL
VIL
X'
VIL
VIH
X
Dour
High-Z
Output Disable
Vee
Vee
Standby
Vee
Vee
VIH
X
X
Program
Vpp
Vee
VIL
VIH
X
DIN
Program Verify
Vpp
Vee
VIH
VIL
X
Dour
Optional Verify
Vpp
Vee
V
V
X
DQur
Program Inhibit
Vpp
Vee
VH
VIH
X
High-Z
VIL
VH2
ID
Identifier
Notes:
Vee
1.
2.
Vee
VIL
-High-Z
X = Don't Care.
11.5 V '5, VH$. 12.5 V
HITACHI
4-2
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C256A Series
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Vcc
-0.6 to +7.0
V
Programming Voltage 1
Vpp
-0.6 to +13.5
V
VIN,vooT
-0.6 to +7.0
V
VIO
TOPR
-0.6 to +13.5
V
oto +70
°C
Storage Temperature Range
TSTG
-65 to +125 3
-55 to +125 4
°C
Storage Temperature Under Bias
TB,AS
-10 to +80
°C
All Input and Output Voltage 1.2
Operating Temperature Range
Notes:
1.
2.
3.
4.
Relative to V55'
VI N' VOUT' and VIO min = -1.0V for pulse width:;; 50 ns.
HN27C256AG.
HN27C256AP and HN27C256AFP.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
•
Unit
Supply Voltage 1
Ag Input Voltage 2
•
Value
Symbol
Typ.
Max.
Unit
Test Condition
Input Capacitance
CIN
4
8
pF
VIN = OV
Output Capacitance
COOT
8
12
pF
VooT = OV
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vpp = V55 to VcC' T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
2
IlA
VIN = 0 V to Vcc
Output Leakage Current
ILO
-
Item
Standby Vcc Current
ISB
VppCurrent
Ippl
-
Input Voltage
VIH
2.2
Vil
-0.3 1
VOH
2.4
VOL
-
Operating Vcc Current
Iccl
Icc2
Icc3
Output Voltage
Notes:
1.
2.
2
IlA
VOUT=OVtoVcc
30
rnA
lOUT = 0 rnA, CE = Vil
30
rnA
lOUT = 0 rnA, f = 10 MHz
5
15
rnA
lOUT = 0 rnA, f = 1 MHz
-
1
rnA
CE =VIH
1
20
IlA
Vpp= 5.5 V
-
Vcc + 12
V
0.8
V
-
V
IOH = 1.0 rnA
0.45
V
IOl = 2.1 rnA
VI l min = -1.0 V for pulse width:;; 50 ns.
VIH max = Vcc + 1.5 V for pulse width:;; 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-3
HN27C256A Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vpp = Vcc ' T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fa" times:
• Output load:
• Reference levels for measuring timing:
0.45 V 12.4 V
~ 10 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V 12.0 V
-10
Symbol Min. Max. Min. Max. Min. Max.
Item
-
100
tOF
tOH
Address Access Time
tACC
Chip Enable Access Time
tCE
Output Enable Access
Time
tOE
Output Disable to High-Z 1
Output Hold to Address
Change
Note:
•
-15
-12
1.
120
100
-
60
-
0
35
5
-
Test
Condition
Unit
150
ns
CE = OE = VIL
150
ns
OE=V
60
-
70
ns
CE = VIL
0
40
0
50
ns
CE = VIL
5
-
5
-
ns
CE = OE = VIL
120
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
READ TIMING WAVEFORM
~
Address
CE
Standby Mode
K
~
\
OE
.
Data Out
Active Mode
tCE
V Standby Mode
V
tOE
tACcl~
///
~~\I\.
tDF
-:--=tOH
Data Out Valid
\
(TD.R.HN27C256A)
HITACHI
4"4
Hitachi America,
Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - - HN27C256A Series
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.0 V ± 0.25 V, Vpp = 12.5 V ± 0.5 V, T. = 25°C ± 5°C)
Item
Input Leakage Current
Operating Vee Current
Icc
-
30
rnA
Vee +.5 6
V
0.8
V
-
-
VIL
- 0.15
VOH
2.4
VOL
-
-
5.
6.
•
-
2.2
4.
VIN = 0 Vto Vee
-
Ipp
1.
2.
3.
I!A
rnA
III
VIH
Notes:
2
30
Typ.
Input Voltage
Output Voltage
Test Condition
Min.
Operating Vpp Current
3
Unit
Symbol
Max.
CE = VIL
-
V
IOH = -400 I!A
0.45
V
IOH = 2.1 rnA
Vee must be applied before Vpp and removed after Vpp'
Vpp must not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
Do not change Vpp from VIL to 12.5 V or 12.5 V to VI L when CE = low.
VI L min = -0.6 V for pulse width :5 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.0 V ± 0.25 V, Vpp = 12.5 V ± 0.5 V, T. = 25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V I 2.4 V
:5 20 ns
0.8 V I 2.0V
Symbol Min.
Address Setup Time
Address Hold Time
tAS
2
tAH
0
Data Setup Time
tos
2
Vpp Setup Time
Typ.
Max.
-
-
Unit
~
I1s
~
tyPS
2
-
Vcc Setup Time
tyes
2
Output Enable Setup Time
tOES
2
Output Disable Time
tOF
0
-
130
I1S
ns
CE Initial Programming Pulse Width
tpw
0.95
1.0
1.05
ms
CE Overprogramming Pulse Width
topw
2.85
ms
tOE
-
78.75
0
150
ns
Data Valid from Output Enable Time
Note:
1.
-
Test Condition
~
~
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-5
HN27C256A Series
•
FAST HIGH-RELIABILITY PROGRAMMING FLOWCHART
The Hitachi HN27C256A can be programmed with the Fast High-Reliability Programming algorithm shown
in the following flowchart. This algorithm provides a fast programming time without voltage stress to the device
ordeterioration in reliability of programmed data. This algorithm theoretically provides one-tenth the programming
time of the conventional High Performance Programming algorithm.
SET PROGNERIFY MODE
Vpp = 12.5 ± 0.5V Vcc = 6.0 ± 0.25 V
Program tpw = 0.2 ms ± 5%
Address + 1-+ Address
NOGO
NO
YES
SET READ MODE
Vcc =5.0 ± 0.5 V Vpp =Vcc
NOGO
(FC.P.HN27C256A)
HITACHI
4-6
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C256A Series
•
FAST HIGH-RELIABILITY PROGRAMMING TIMING WAVEFORM
J
.
Program
Address
Data
=><
=><
Vpp
vpp
v'~
Vcc
Vcc+ 1
V
.
Program Verify
K=
tAH
• tAS •
Data In Stable
Data Out Valid
1/
tOF
~
tos
I"
tvps
~
tvcs
t;r
tpw
. .
toes
""
~
./
(TD.P.HN27C256A)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
4·7
HN27C256A Se'rles
•
HIGH PERFORMANCE PROGRAMMING FLOWCHART
The Hitachi HN27C256A can be programmed with the High Performance Programming algorithm shown in
the following flowchart. This algorithm provides a fast programming time without voltage. stress to the device or
deterioration in reliability of programmed data.
SET PROGNERIFY MODE
Vpp = 12.5 ± 0.5 V Vcc = 6.tr"± 0.25 V
Program tpw
=1.0 ms ± 5%
Address + 1~ Address
NOGO
NO
YES
SET READ MODE
Vcc =5.0 ± 0.5 V Vpp =Vcc
NOGO
(FC.PP.HN27C256A)
HITACHI
4-8
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
/
- - - - - - - - - - - - - - - - - - - HN27C256A Series
•
HIGH PERFORMANCE PROGRAMMING TIMING WAVEFORM
Program
Program Verify
)C
)(
Address
.
)(
Data
tAS
.
tAH
vpp
vee
Vee
Vee+ 1
Vee
~
./
"
~
tos
Vpp
./
"
Data In Stable
Data Out Valid
'"
./
tOF
~
tvps
~
~
tves
'" ,.
/
tpw
V
.
toes
toe
~
~
/
I'"
(TO.PP.HN27e256A)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-9
HN27C256A Series
•
ERASING THE HN27C256A
The Hitachi HN27C256A Ceramic DIP package allow the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C256A SERIES II;)ENTIFIER CODE
Identifier
Aa
1/°7
I/Oe
Manufacturer Code
V
0
Device Code
V1H
0
Notes:
1.
3.
1/°4
0
II0s
0
1/°2
1
1/°1
1
1/°0
1
Hex Data
0
1/°5
0
0
1
1
0
0
0
1
31
07
Ag =12.0 V ± 0.5V
A1-As' A1.0-A14'
CE", OE =V1L
•
HN27C256AP/FP RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C256A plastic packages, please make the following screening (baking without
bias) shown below:
(RSC.EPROM)
HITACHI
4-10
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819. (415) 589-8300
HN27C256H Series
256K (32K
- - - - - - - - - - Maintenance Only
x 8-blt) UV and OTP EPROM
•
DESCRIPTION
The Hitachi HN27C256H is a 256-Kilobit Ultraviolet Erasable
and One-Time Programmable Electrically Programmable Read Only
Memory organized as 32,768 x 8-bits.
The HN27C256H features fast address access times and low
power dissipation. This combination makes the HN27C256H suitable
for high speed microcomputer systems. The HN27C256H also offers
high speed programming.
Hitachi's HN27C256H is offered in JEDEC-Standard Byte-Wide
EPROM pinouts in 28-pin Ceramic and Plastic DIP and 28-lead
Plastic SOP packages.
The Ceramic DIP package is erasable by exposure to Ultraviolet
light. The Plastic DIP and SOP packaged devices are One-Time
Programmable and once programmed, can not be rewritten.
•
•
(DG-28)
FEATURES
• Fast Access Times:
70 nsl85 nsl100 ns (max)
• Single Power Supply:
Vee = 5 V± 10%
• Low Power Dissipation:
30 mW/MHz (typ)
Active Mode:
Standby Mode: 15 mA (max)
• High Speed Programming
• Programming Power Supply:
Vpp=12.5V±0.5V
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
• Packages:
28-pin Ceramic DIP
. 28-pin Plastic DIP
28-lead Plastic SOP
(DP-28)
(FP-28DA)
•
ORDERING INFORMATION
Type No.
HN27C256HG-70
HN27C256HG-85
HN27C256HP-85
HN27C256HP-10
HN27C256HFP-85T
HN27C256HFP-10T
Access Time
70ns
85ns
85ns
100 ns
85ns
100 ns
Package
28-pin Ceramic DIP
(DG-28,)
28-pin Plastic DIP
(DP-28)
28-lead Plastic SOP
(FP-28DA)
PIN ARRANGEMENT
HN27C256HG/P Series
HN27C256HFP Series
Vee
Vpp
A12
A14
A13
A7
A6
AS
AS
All
AS
A4
6E
A3
A2
Al
Al0
CE
AO
1.107
1/00
1/06
1/05
1101
1/02
1/04
1103
Vss
(PinO 8.HN27C256H)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 9400S-1819· (41S) 589-8300
4-11
HN27C256H Series
•
PIN DESCRIPTION
Pin Name
•
Function
Ao - A'4
Address
1/00 - 1/07
Input/Output
CE
Chip Enable
OE
Output Enable
Vcr.
Power Supply
Vpp
Programming Supply
Vss
Ground
BLOCK DIAGRAM
512 x 512
Memory Matrix
A4·A9 (
A12·A14 )
Address O--i-~=l_--1
1100
V07
~
AO·A3
Al0·All
+
High Threshold
Inverter
(BD.HN27C256H)
•
MODE SELECTION
Mode
Vpp
Read
Vee
Vee
CE
OE
As
110
Vee
VIL
VIL
X'
VIL
VIH
X
DOUT
. High-Z
High-Z
Output Disable
Vee
Vee
Standby
Vee
Vee
VIH
X
X
Program
Vpp
Vee
VIL
VIH
X
DIN
Program Verify
Vpp
Vee
VIH
VIL
X
DOUT
Optional Verify
Vpp
Vr.r.
V
V
X
DOIlT
Program Inhibit
Vpp
Vee
VIH
VIH
X
High-Z
Identifier
Vee
Vee
VIL
VIL
V 2
H
10
Notes:
1.
2.
X = Don't Care.
11.5 V ~ VH~ 12.5 V
HITACHI
4-12
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C256H Series
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage 1
Vcc
-0.6 to +7.0
V
Programming Voltage 1
Vpp
-0.6 to +13.5
V
VIN,vOUT
VIO
-0.6 to +7.0
V
-0,6 to +13.5
V
Operating Temperature Range
TOPA
o to +70
°C
Storage Temperature Range
TSTG
-65 to +125 3
-55 to +125 4
°C
Storage Temperature Under Bias
TBIAS
-10 to +80
°C
All Input and Output Voltage 1,2
Ag Input Voltage 2
Notes:
1.
2.
3.
4.
Relative to VSS.
VI N' VOUT' and VIO min = -1.0V for pulse width
HN27C256HG.
HN27C256HP and HN27C256HFP.
50 ns.
CAPACITANCE (T. = 25°C, f = 1MHz)
•
Item
Symbol
Input Capacitance
Output Capacitance
•
:0;
Typ.
Max.
Unit
Test Condition
CIN
4
8
pF
VIN = OV
COUT
8
12
pF
VOUT = OV
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vpp
Item
=Vssto Vcc' T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
-
-
2
JlA
VI N= 0 V to Vcc
Output Leakage Current
ILO
-
-
2
JlA
VOUT = 0 V to vcc
Operating Vcc Current
Iccl
-
30
mA
lOUT = 0 mA,.CE = VIL
-
40
mA
lOUT = 0 mA, f = 11.8 MHz
5
15
mA
lOUT = 0 mA, f = 1 MHz
Standby Vcc Current
ISB
-
-
15
mA
CE = VIH
VppCurrent
IpPl
-
1
100
JlA
Vpp= 5.5 V
-
VCC +12
V
0.8
V
-
V
IOH = -400
0.45
V
IOL = 2.1 mA
Icc2
Icc3
Input Voltage
Output Voltage
Notes:
1.
2.
VIH
2.2
VIL
-0.3 '
VOH
2.4
Vm,
-
JlA
VI Lmin = -1.0 V for pulse width :0; 50 ns.
VIH max = Vcc + 1.5 V for pulse width 5 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
HITACHI
Hitachi America, Ltd .• 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
4-13
HN27C256H Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc =5V ± 10%, Vpp = Vcc' T. =0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V 12.4 V
~ 10 ns
1 TIL Gate + 100 pF (Including scope and jig)
1.5 VI 1.5V
·70
Address Access TIme
Chip Enable Access Time
Output Enable Access
Time
Output Disable to High-Z 1
Output Hold to Address
Change
Note:
•
-10
·85
Symbol Min. Max. Min. Max. Min. Max.
Item
1.
70
tCE
-
tOE
-
tDF
tOH
tACC
85
40
-
0
30
5
-
70
Unit
Test
Condition
-
100
ns
CE = OE
85
100
ns
OE = V1L
45
-
55
ns
CE = V1L
0
30
0
35
ns
CE = V1L
5
-
5
-
ns
CE = OE
= V1L
= V1L
tDF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
READ TIMING WAVEFORM
CE
X
X-
Address
Standby Mode
1
Active Mode
tCE
\
OE
Data Out
Standby Mode
I
tOE
.
I
.
tACcl~
///
\.\\\
tDF
----=-'-tOH
Data Out Valid
(TD.R.HN27C256H)
HITACHI
4-14
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C256H Series
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.0 V ± 0.25 V, Vpp = 12.5 V ± 0.5 V, T. = 25°C ± 5°C)
Item
Symbol
Min.
Typ.
Input Leakage Current
III
Operating Vee Current
lee
-
Operating Vpp Current
Ipp
-
Input Voltage 3
VIH
2.2
VIL
- 0.15
VOH
2.4
Output Voltage
-
Notes:
1.
2.
3.
4.
5.
6.
•
Max.
Unit
Test Condition
VIN = 0 Vto Vee
2
I!A
30
mA
30
mA
Vee +.5 6
V
0.8
V
-
V
0.45
V
CE = VIL
IOH = -400 I!A
IOH = 2.1 mA
VOL
Vee must be applied before Vpp and removed after Vpp'
Vppmust not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
Do not change Vpp from VIL to 12.5 V or 12.5 V to VI L when CE = low.
VI L min = -0.6 V for pulse width :s; 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.0 V ± 0.25 V, Vpp = 12.5 v ± 0.5 V, T. = 25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V / 2.4 V
:s; 20 ns
0.8 V / 2.0V
Symbol Min.
Typ.
Max.
Unit
-
~s
130
ns
tOES
2
Output Disable Time
tOF
0
-
CE Initial Programming Pulse Width
tpw
0.19
0.20
0.21
ms
CE Overprogramming Pulse Width
topw
0.19
ms
tOE
-
5.25
0
150
ns
tAS
2
Address Hold Time
Address Setup Time
tAH
0
Data Setup Time
tos
2
Vpp Setup Time
!yps
2
Vee Setup Time
!Yes
2
Output Enable Setup Time
Data Valid from Output Enable Time
Note:
1.
Test Condition
~s
~
~s
~
~s
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-15
HN27C256H Series
•
FAST HIGH·RELIABILITY PROGRAMMING FLOWCHART
The Hitachi HN27C256H can be programmed with the Fast High-Reliability Programming algorithm shown
in the following flowchart. This algorithm provides a fast programming time without voltage stress to the device
or deterioration in reliability of programmed data. This algorithm theoretically provides one-tenth the programming
time of the conventional High Performance Programming algorithm.
SET PROGNERIFY MODE
Vpp = 12.5 ± 0.5V Vcc = 6.0 ± 0.25 V
Program tpw
= 0.2 ms ± 5%
Address + 1~ Address
NOGO
NO
YES
SET READ MODE
Vcc = 5.0 ± 0.5 V Vpp = Vcc
NOGO
(FC.P.HN27C256H)
HITACHI
4-16
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C256H Series
•
FAST HIGH-RELIABILITY PROGRAMMING TIMING WAVEFORM
.
Program
Address
Data
Vpp
=><
=><
~
tAH
• tAS •
Data In Stable
Data Out Valid
~
tos
V
Vee
"
/
tOF
'U~
,
, tvps ,
Vee
.
Program Verify
Vee+ 1
V~~
tves
tpw
.
tOES
.
'"
~
/
(TD.P.HN27C256H)
II
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
4-17
HN27C256H Series
•
HIGH PERFORMANCE PROGRAMMING FLOWCHART
The Hitachi HN27C256H can be programmed with the High Performance Programming algorithm shown
in the following flowchart. This algorithm provides a fast programming time without voltage stress to the device
or deterioration in reliability of programmed data.
SET PROGNERIFY MODE
Vpp = 12.5 ±0.5 V Vee =6.0 ±0.25 V
Program tpw = 1.0 ms ± 5%
Address + 1~ Address
NOGO
NO
YES
SET READ MODE
Vee = 5.0 ± 0.5 V Vpp = Vec
NOGO
(FC.PP.HN27C256H)
HITACHI
4-18
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589·8300
- - - - - - - - - - - - - - - - - - - - HN27C256H Series
•
HIGH PERFORMANCE PROGRAMMING TIMING WAVEFORM
Program
)
Address
)
K
,
Vpp
Vpp
Vee
Vee
Vee+ 1
V
Vee
/'
-
tAS
tAH
,
tos ,
v
.......
Data In Stable
I.......
./
-.!!lli...
.......
Data Out Valid
.
tOF
,
"
/V
, tvps ,
.
CE
)C
K
,
Data
Program Verify
tves ,
V
"'---./
,
,
tpw
tOES
~
" '-
./ it'
(TO.PP.HN27e256H)
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-19
HN27C256H Series.
•
ERASING THE HN27C256H
The Hitachi HN27C256H Ceramic DIP package allow the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C256H SERIES IDENTIFIER CODE
Identifier
AD
1/07
IIOs
1/°5
1/°4
1/°3
1/°2
11O,
1/°0
Hex Data
Manufacturer Code
V1L
0
0
0
0
0
1
1
1
07
Device Code
VIti
0
0
1
1
0
0
0
1
31
Notes:
1.
3.
A. = 12.0 V ± 0.5V
A,-As' A,o-A'4' CE, OE
=V1L
•
HN27C256HP/FP RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C256H plastic packages, please make the following screening (baking without
bias) shown below:
(RSC.EPROM)
HITACHI
4-20
Hitachi America, Ltd. - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819 - (415) 589-8300
HN27512 Series
Maintenance Only
512K (64K x a-bit) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27512 is a 512-Kilobit Ultraviolet Erasable and
One-Time Programmable Electrically ProgrammablEt Read Only
Memory organized as 65,536 x 8-bits.
The HN27512. features low power dissipation and high speed
programming.
Hitachi's HN27512 is offered in JEDEC-Standard Byte-Wide
EPROM pinouts in a 28-pin Ceramic and Plastic DIP packages.
•
•
FEATURES
• Fast Access Times:
250 ns/300 ns (max)
• Single Power Supply:
Vcc =5V±10%
• Low Power Dissipation:
Active Mode:
45 mA (typ)
Standby Mode: 40 mA (max)
• High Speed Programming
• Programming Power Supply:
Vpp = 12.5 V ± 0.3 V
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
• Package:
28-pin Ceramic DIP
28-pin Plastic DIP
(DP-28)
ORDERING INFORMATION
Type No.
HN27512G-25
HN27512G-30
HN27512P-25
HN27512P-30
•
(DG-28)
Access Time
250 ns
300 ns
250 ns
300 ns
Package
28-pin Ceramic DIP
(DG-28)
28-pin Plastic DIP
(DP-28)
PIN DESCRIPTION
Pin Name
Function
Ao - A,s
Address
1100 - 1107
Input/Output
CE
Chip Enable
OE
Output Enable
PIN ARRANGEMENT
HN27512G/P Series
A15
A12
A7
A6
A5
A4
A3
A2
Al
AO
1/00
1/01
1/02
1
2
3
4
5
6
Vee
28·PIN
DIP
22
28·LEAD 21
SOP
TOPVIEW 20
19
Programming Supply
A14
A13
A8
A9
All
OEIVpp
Al0
CE
1/07
1106
1/05
1104
V..
Power Supply
V""
Vpp
•
1/03
(PinD28.HN27C512)
' Ground
Vss
HITACHI
Hitachi America,
Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
4-21
EI
HN27512 Series
•
BLOCK DIAGRAM
A5-A9
o----t~==:::::j
x-
Decoder
1,024X512
Memory Matrix
Al1-A15o---+t<~==:=:j
Ce~------;I/V'I
OENpp
o----f>c>f4-L
Ao-A4, Al0
f8:>o :High Threshold Inverter
(BD.HN27512)
•
MODE SELECTION
Mode
Vee
CE
OEIVpp
Read
Vee
VIL
VIL
Output Disable
Vee
VIL
VIH
X
Dour
High-Z
Standby
High-Z
Vee
VIH
X
X
Program
Vee
VIL
Vpp
X
DIN
Program Verify
Vee
VIL
VIL
X
Program Inhibit
Vee
VIH
Vpp
X
Dour
High-Z
Vee
V
V
V~2
10
Identifier
Notes:
•
1/0
Ag
Xl
1.
2.
X = Don't Care.
11.5 V S VHS 12.5 V
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage 1
Value
Unit
Vee
-0.6 to +7.0
V
Vpp
-0.6 to +13.5
V
VIN, VOUT
-0.6 to +7.0
V
VIO
TOPA
-0.6 to +13.5
V
oto +70
°C
Storage Temperature Range
TSTG
-65 to +125 2
-55 to +125 3
°C
Storage Temperature Under Bias
TBIAS
-10 to +80
°C
Programming Voltage
1
All Input and Output Voltage 1
As Input Voltage
Operating Temperature Range
Notes:
1.
2.
3.
Relative to Vss'
HN27512G.
HN27512P.
HITACHI
4-22
Hitachi America, Ltd.' 2000. Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN27512 Series
•
CAPACITANCE (Ta = 25°C, f = 1MHz)
Symbol
Typ.
Max.
Unit
Test Condition
Input Capacitance
CIN
4
6
pF
VI N= OV, all pins except OENpp
Output Capacitance
COUT
8
12
pF
VOUT = OV
Item
•
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Ta = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
10
ILO
10
I!A
I!A
VI N= 0 V to Vec
Output Leakage Current
45
100
mA
CE
Item
Standby Vee Current
IS8
-
-
40
mA
Input Voltage
VIH
2.2
-
Vee + 12
V
VIL
-0.1'
-
0.8
V
VOH
2.4
-
-
V
IOH = 1.0 mA
VOL
-
-
0.45
V
IOL = 2.1 mA
Operating Vee Current
Output Voltage
Notes:
•
1.
2.
Icc
VOUT = 0 V to Vcc
= OE = VIL
CE = VIH
VI Lmin = -0.6 V for pulse width ~ 20 ns.
VIH max = Vee + 1.5 V for pulse width ~ 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V /2.4 V
~20 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V /2.0 V
·25
·30
Symbol Min. Max. Min. Max.
Item
Unit
Test
Condition
Output Enable Access
Time
icE
-
Output Disable to High-Z '
tOF
0
60
0
105
ns
CE = VIL
Output Hold to Address
Change
tOH
0
-
0
-
ns
CE = OE = VIL
Address Access Time
tACC
Chip Enable Access Time
tCE
Note:
1.
300
ns
300
ns
100
-
120
ns
= OE = VIL
OE = VIL
CE = VIL
250
250
CE
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-23
HN27512 Series
•
READ TIMING WAVEFORM
X
Address
CE
Standby Mode
K
}.
OE
Active Mode
tCE w
/ Standby Mode
\
)
tOF
tOH
tOE
t ACc--:::.oo.
///1
\.\.\\
Data Out
~
-
:\.
'/
Data Out Valid
(TD.R.HN27512)
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee =6.0 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V, T. =25°C ± 5 °C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
ItA
VIN = 5.25 V
lee
-
10
Operating Vee Current
-
100
mA
35
50
mA
-
Vee +.5 2
V
0.8
V
-
V
IOH = -400 ItA
0.45
V
IOH = 2.1 mA
Operating Vpp Current
Ipp
Input Voltage 1
VIH
2.0
V
- 0.11
VOH
2.4
VOL
-
Output Voltage
Notes:
1.
2.
CE = VIL
VI Lmin =-0.6 V for pulse width ~ 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
HITACHI
4-24
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589·8300
- - - - - - - - - - - - - - - - - - - - H N 2 7 5 1 2 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee =6 V ± 0.25 V, Vpp = 12.5 V ± 0.5 V, T. =25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V / 2.4 V
!> 20 ns
0.8 V /2.0V
Symbol . Min.
Typ. . Max.
tAH
0
Data Setup Time
tos
2
Vpp Setup Time
!yps
2
Vee Setup Time
!Yes
2
-
Output Enable Hold Time
tOEH
2
-
Address Setup Time
tAS
2
Address Hold Time
Unit
-
~
-
~
-
~s
-
~
~s
~
Output Disable Time
tOF
0
-
130
ns
CE Initial Programming Pulse Width
tpw
0.95
1.0
1.05
ms
CE Overprogramming Pulse Width
-
78.75
ms
tOPw
2.85
Data Hold Time
tOH
2
Vpp Recovery Time
tVR
2
1.
~s
~s
~s
tov
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
Data Valid from Chip Enable
Note:
-
Test Condition
1
II
HITACHI
Hitaehi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane,CA 94005-1819· (415) 589-8300
4-25
HN27512 Series
•
HIGH PERFORMANCE PROGRAMMING FLOWCHART
The Hitachi HN27512 can be programmed with the High Performl:,lnce Programming algorithm shown in the
following flowchart. This algorithm provides a fast programming time without voltage stress to the device or
deterioration in reliability of programmed data.
Address + 1-4Address
(FC.P.HN27512)
•
HIGH PERFORMANCE PROGRAMMING TIMING WAVEFORM
Program
Address
Program Verify
=><
pC
tAH
tAS
I"='
Data
Vpp
OE/vpp
i'i..
Data In Stable
./
tov
~
.tos.
DataOu Valid
I.........
1,/
tOF
~
~io;..
-./
!vp~
Vee
Vee+ 1 /
V~
tOEH
,
.tve~
CE
tVR
..:-;.;
t;{
/~
tpw
(TD.PP.HN27512)
HITACHI
4-26
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
- - - - - - - - - - - - - - - - - - - H N 2 7 5 1 2 Series
•
ERASING THE HN27512
The Hitachi HN27512 Ceramic DIP package allows the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27512 SERIES IDENTIFIER CODE
Identifier
Aa
Manufacturer Code
V1L
Device Code
V1H
Notes:
1.
3.
1/°7
0
1/06
0
1/°5
0
0
0
1/°4
0
1/03
0
0
1/°2
1
1/00
1
Hex Data
1
0
0
94
I/O,
07
Ag = 12.0 V ± 0.5V _
A,-A" A,0-A'5' CE, OENpp = V1L
•
HN27512P RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27512P package, please make the following screening (baking without bias) shown
below:
(RSC.EPROM)
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
4-27
- - - - - - - - - - Maintenance Only
HN27C512 Series
512K (64K x a-bit) UV EPROM
•
DESCRIPTION
The Hitachi HN27C512 is a 512-Kilobit Ultraviolet Erasable and
Electrically Programmable Read Only Memory organized as 65,536
x 8-bits.
The HN27C512 features fast address access times and low
power dissipation. This combination makes the HN27C512 suitable
for high speed microcomputer systems. The HN27C512 also offers
high speed programming.
Hitachi's HN27C512 is offered with the JEDEC-Standard ByteWide EPROM pinout in a 28-pin Ceramic package.
(DG-28)
•
FEATURES
• Fast Access Times:
170 ns/200 ns (max)
• Single Power Supply:
Vee =5V±10%
• Low Power Dissipation:
Active Mode:
35 mA (typ)
Standby Mode: 250 I!A (max)
• High Speed Programming
• Programming Power Supply:
Vpp = 12.5 V±0.3 V
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
• Package:
28-pin Ceramic DIP
•
ORDERING INFORMATION
Type No.
HN27C512G-17
HN27C512G-20
•
Access Time
170 ns
200 ns
Package
28-pin Ceramic DIP
(DG-28)
PIN DESCRIPTION
Pin Name
Function
Ao - A,s
Address
1/00 - 1/07
Input/Output
CE
Chip Enable
OE
Output Enable
•
PIN ARRANGEMENT
HN27C512G Series
Vcc
A15
A12
A7
A6
AS
A4
A3
A14
A13
A8
A9
All
A2
Al0
Al
AO
CE
OENpp
1107
1/00
1/01
Vee
Power Supply
Vpp
Programming Supply
Vss
Ground
1/06
1/05
1/04
1/03
1102
Vss
(PinD28.HN27C512)
HITACHI
4-28
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C512 Series
•
BLOCK DIAGRAM
A6
o-------{~=====i
x-
Decoder
1.024X512
Memory Matrix
---Th~==:j
A'5 0.'
IIOOO-_--H'>----r-=~\oi~:_:::;:~~--,
\
II07o-+-~-H
>1----1
AD-A5
iB>o :High Threshold Inverter
(BD.HN27C512)
•
MODE SELECTION
Mode
Vee
Read
OENpp
Ag
1/0
Vee
VIL
VIL
X'
Output Disable
Vee
VIL
VIH
X
DoUT
High-Z
Standby
High-Z
Vee
VIH
X
X
Program
Vee
VIL
Vpp
X
DIN
Program Verify
Vee
VIL
VIL
X
Program Inhibit
Vee
VIH
Vpp
X
DOIJT
High-Z
Identifier
Vee
VIL
VL
V/
10
Notes:
1.
2.
•
CE
X = Don't Care.
11.5 V S; VHS; 12.5 V
II
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage'
Vee
-0.6 to +7.0
V
Programming Voltage'
Vpp
-0.6 to + 13.5
V
VIN,vOUT
-0.6 to +7.0
V
V
Operating Temperature Range
VIO
TOPA
-0.6 to +13.5
oto +70
°C
Storage Temperature Range
T5TG
-65 to +125
°C
Storage Temperature Under Bias
TSIAS
-10 to +80
°C
Item
All Input and Output Voltage'
As Input Voltage
Notes:
1.
Relative to V55'
HITACHI
Hitachi America. Ltd.' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
4-29
HN27C512 Series
•
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
•
Symbol
Typ.
Max.
Input Capacitance
CIN
6
Output Capacitance
COUT
8
Test Condition
10
pF
VIN = OV, all pins except OENpp
14
pF
VOUT = OV
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, T. = 0 to 70°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
-
-
10
ItA
ItA
VIN=OVtoVcc
10
35
50
mA
f = 6 MHz, CE = OE = VIL
CE = VIH
Input Leakage Current
III
Output Leakage Current
ILO
Operating Vcc Current
Icc
Standby Vcc Current
Input Voltage
ISB
VIH
2.2
VIL
-0.11
Output Voltage
VOH
2.4
VOL
-
Notes:
•
Unit
1.
2.
-
VOUT=OVtoVcc
500
mA
Vcc + 1 2
V
0.8
V
-
V
IOH = 1.0 mA
0.4
V
IOL = 2.1 mA
VI Lmin = -0.6 V for pulse width:;; 20 ns.
VIH max = Vcc + 1.5 V for pulse width:;; 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(V'(;c = 5V ± 10%, T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.4 V 12.4 V
:;;20 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V 12.0 V
-17
Item
-20
Symbol Min. Max. Min. Max.
200
ns
CE = OE = VIL
200
ns
OE = VIL
75
75
ns
CE = VIL
0
60
0
60
ns
CE = VIL
0
-
0
-
ns
CE = OE = VIL
-
170
Chip Enable Access Time
tce
170
Output Enable Access
Time
lee
-
Output Disable to High-Z 1
tOF
tOH
Output Hold to Address
Test
Condition
-
tACC
Address Access Time
Unit
HITACHI
4-30
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
---------~----------
•
HN27C512 Series
READ TIMING WAVEFORM
~
Address
Standby Mode
CE
K
1
I
Active Mode
ICE
\
OENpp
I
tOF
tOH
tOE
r:--=-
tACC~
-
///.
\.'\'\\
Data Out
Standby Mode
\.
/
Data Out Valid
(TD.R.HN27C512)
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.0 V ± 0.25 V. Vpp = 12.5 V ± 0.3 V. T. = 25 °C ± 5 °C)
Item
Symbol
Min.
Typ.
Max.
Input Leakage Current
III
-
Operating Vee Current
lee
35
50
Operating Vpp Current
Ipp
-
Input Voltage 1
VIH
2.2
V
- 0.11
VOH
2.4
V01.
-
Output Voltage
Notes:
1.
2.
-
Unit
Test Condition
10
IlA
VIN = 0 V to Vcc
50
mA
VCC +·5
mA
2
CE = VIL
V
O.S
V
-
-
V
IIJH = ~400 IlA
-
0.4
V
IOH= 2.1 mA
VI Lmin = -0.6 V for pulse width S; 20 ns.
If VIH is over the specified maximum value. programming operation can not be guaranteed.
HITACHI
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane.
CA 94005-1819· (415) 589-8300
4-31
HN27C512 Series
•
AC EL,ECTRICAL CHARACTERISTICS FOR !'R.OGRAMMING OPERATIONS
(Vee 7' 6.0 V ± 0.25 V, Vpp =12.5 V ± 0.3 V, T. =, 25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fa" times:
• Reference levels for measuring timing:
Item
0.4 V 12.4 V
:=:20 ns
0.8 V 12.0V
SymbOl Min.
Address Setup Time
Address Hold Time
tAS
2
tAH
0
Data Setup Time
los
2
Vpp Setup Time
\,ps
2
Vee Setup Time
\'cs
2
Output Enable Hold Time
ioeH
Output Disable Time
CE Initial Programming Pulse Width
CE" Overprogramming Pulse Width
Unit
-
lIS
-
~s
lIS
tOF
0
-
130
lIS
ns
~
0.95
1.0
1.05
ms
-
78.75
ms
-
-
-
lIS
ns
~
2
Vpp Rise Time
tR
00
Vpp Recovery Time
tVR
2
-
Test Condition
~s
-
2.85
1.
-
Max.
2
topw
Data Valid from Chip Enable
.
-
Data Hold Time
. Note:
Typ.
lIS
~s
1
~s
tov
tOF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
4-32
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
- - - - - - - - - - - - - - - - - - - - HN27C512 Series
•
HIGH PERFORMANCE PROGRAMMING FLOWCHART
The Hitachi HN27C512 can be programmec;t with the High Performance Programming algorithm shown in
the following flowchart. This algorithm provides a fast programming time without voltage stress to the device or
deterioration in reliability of programmed data.
SET PROGNERIFY MODE
V pp
=12.5 ±0.3V
Vee
=6.0 ±0.25V
Program tpw = 1ms ± 5%
Address + 1--+ Address
NOGO
Program topw = 3 ms
NO
YES
SET READ MODE
Vee =5.0 ± 0.25 V
NOGO
(FC.P.HN27C512)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, eA94005-1819· (415) 589-8300
4-33
HN27C512 Series
•
HIGH PERFORMANCE PROGRAMMING TIMING WAVEFORM
Program
Program Verify
---x
Address
C
tAH
I~
Data
Vpp
OENpp
-
~
.!mi.
tR ,tos,
I'..
v
tOF
~
~~
!vp~
VCC+1 / "
-
Vcc
Data 0 tValid
tov
/
V1L
Vcc
'"
Data In Stable
tVR
toEH
~
,
I.tvc.
CE
/
tpw
(TD.PP.HN27C512)
•
ERASING THE HN27C512
The Hitachi HN27C512 Ceramic DIP package allows the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTlFII:;R MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C512 SERIES IDENTIFIER CODE
Identifier
1/°7
I/Oa
1/°5
Manufacturer Code
Ao
V1L
1
0
0
Device Code
V1H
1
0
0
Notes:
1.
3.
1/°4
1/03
1/°2
1/°1
1/00
Hex Data
0
0
0
1
1
1
97
1
0
Ag = 12.0 V± 0.5V _
A1-As' A10-A15 , CE, OE = V1L
HITACHI
4-34
Hitachi America, Ltd. ·2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819' (415) 589-8300
85
HN27C1024H Series
1M (64K x 16-blt) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27C1024H is a 1-Megabit Ultraviolet Erasable
and One-Time Programmable Electrically Programmable Read Only
Memory organized as 65,536 x 16-bits.
The HN27C1024H features fast address access times of 85,
100, 120 and 150 ns and low power dissipation. This combination
makes the HN27C1024H suitable for high speed 16 and 32-bit
microcomputer systems. The HN27C1024H offers high speed
programming using page programming mode.
Hitachi's HN27C1024H is offered in JEDEC-Standard WordWide EPROM pinouts in 4O-pin Ceramic DIP and 44-lead Ceramic
and Plastic LCC packages. This allows socket replacement with
Mask ROMs.
The Ceramic DIP and Ceramic LCC packages are erasable by
exposure to Ultraviolet light. The PLCC packaged device is OneTime Programmable and once programmed, can not be rewritten.
•
•
FEATURES
• Fast Access Times:
85 nsl100 nsl120 nsl150 ns (max)
• Single Power Supply:
Vcc =5V±10%
• Low Power Dissipation:
Active Mode:
60 mW/MHz (typ)
Standby Mode: 25 mA (max)
• High Speed Page and Word Programming:
Page Programming Time: 14 sec (typ)
• Programming Power Supply:
Vpp = 12.5 V±0.3 V
• Pin Arrangement:
JEDEC Standard Word-Wide EPROM
Mask ROM Compatible
• Packages:
40-pin Ceramic DIP
44-lead Ceramic LCC
44-lead PLCC
(DG-40A)
(CC-44)
(CP-44)
ORDERING INFORMATION
Type No.
HN27C1024HG-85
HN27C1 024HG-1 0
HN27C1024HG-12
HN27C1024HG-15
HN27C1024HCC-85
HN27C1024HCC-10
HN27C1024HCC-12
HN27C1024HCC-15
HN27C1 024HCP-1 0
HN27C1024HCP-12
HN27C1024HCP-15
Access Time
85 ns
100 ns
120 ns
150 ns
85 ns
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
Package
40-pin Ceramic DIP
(DG-40A)
44-lead Ceramic LCC
(CC-44)
44-lead PLCC
(CP-44)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
---------
4-35
--------------------.---~---
,HN27C1024HSeries--------------~------•
PIN ARRANGEMENT
HN27C1024HG Series
HN27C1024HCC Series
HN27C1024HCP Series
Vcc
Vpp
CE
1/015
1/014
1/013
1/012
1/011
1/010
1/09
1/08
4O-PIN
DIP
TOP VIEW
Vss
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
OE
PGM
NC
A15
A14
A13
A12
A11
A10
A9
1/0131/0141/015 CE VppNC VccPGM NC A15 A14
1/012
1/011
1/010
1/09
IIOS
Vss
NC
,1/07
1106
1/05
1/04
Vss
AS
A7
A6
AS
A4
A3
A2
A1
TOP VIEW
1/03 1/02 1/01 1/00 OE NC AO A1 A2 A3 A4
AO
(Pln044.HN27Cl024H)
(PinD40.HN27Cl024H)
•
44-LEAD
JLCC and PLCC
PIN DESCRIPTION
Pin Name
Function
Ao - A'5
Address
1/00 - 1/0'5
Input/Output
CE
Of
Chip Enable
Vee
Vpp
Output Enable
Power Supply
Programming Supply
Ground
Vss
PGM
PrOgramming Enable
NC'
No Connection
HrrACHI
4~36
HitachiAmerica, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - : - - - - - - - - - - - - - . . . . - - - HN27C1024H Series
•
BLOCK DIAGRAM
A6o-----D~==~
)
A15
1/00
I
0015
O----+IA===~X-Decoder
1024 X 1024
Memory Matrix
o---.---H ')_ _ _-f-==-r---r~:_;;::;::...L.-r_--,
0--+--_-+-1
CE
0----1
DE
0----1
PGM
0----1
>1-----1
.:>Vt-t-'I'""'---"
iB>o :High Threshold Inverter
(BD.HN27C1024H)
•
MODE SELECTION
Mode
Vpp
Vee
CE
OE
PCm
As
1/0
Read
Vcc
Vee
VIL
VIL
VIH
Xl
Dour
Output Disable
Vcc
Vee
VIL
VIH
VIH
X
High-Z
X
X
X
High-Z
DIN
Standby
Vcc
Vcc
VIH
Program
Vpp
Vee
VIL
VIH
VIL
VIL
VIH
X
X
DoUT
V
VIH
X
DIN
Program Verify
Vpp
Vee
VIL
Page Data Latch
Vpp
Vee
VIH
Page Program
VDD
V,.",
V,~
V,..
V
X
High-Z
Vcc
Vee
VIL
VIL
VIL
High-Z
Vpp
Program Inhibit
Identifier
Notes:
1.
2.
Vcc
VIL
VIH
VIH
X
X
Vpp
Vcc
VIH
VIL
VIL
X
High-Z
Vpp
Vee
VIH
VIH
VIH
X
High-Z
Vee
Vcc
VIL
VIL
VIH
VH
10
High-Z
X = Don't Care. Vpp = 0 V to Vcc'
11.5 V ~ VH~ 12.5 V
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94oo5-1819· (415) 589-8300
4-37
HN27C10241i s e l ' l e s - - - - - - - - - - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RAnNGS
Symbol
Value
Unit
Vee
-0..6 to +7.0.
V
Vpp
-0..6 to +13.5
V
VIN,vOOT
VIO
-0..6 to +7.0.
V
-0..6 to +13.0.
V
Item
Supply Voltage 1
Programming Voltage
1
All Input and Output Voltage 1.2
As and OE Voltage 2
Operating Temperature Range
TOPR
o.to.+70
°C
Storage Temperature Range 3
TSTG
-65 to +125 4
-55 to +125 5
°C
Storage Temperature Under Bias
TBIAS
0. to +80.
°C
Notes:
1.
2.
Relative to Vss'
VI I!I' VOOT' and VIO min = -2.o.V for pulse width S 20. ns.
Device storage temperature range before programming.
HN27C1o.24HG and HN27C1o.24HCC.
HN27C1o.24HCP.
3.
4.
5.
•
CAPACITANCE (T. = 25°C, f = 1MHz)
HN27C1024HG/HCC
Item
•
HN27C1024HCP
Symbol
Min.
Max.
Min.
Max.
Unit
Test Condition
Input Capacitance
CIN
12
-
6
pF
VIN = DV
Output Capacitance
COUT
-
15
-
12
pF
VOUT = o.V
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10.%, VPP = Vss to Vcc' T. = 0. to 7o.oC)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
-
-
2
~
VIN = 5.5 V
Output Ll;lakage Current
ILO
2
~
VOUT = 5.5 V/o..45 V
Operating Vee Current
Iccl
Icc2
-
Item
lee3
-
-
25
mA
louT = 0. mA, f = 1 MHz
Standby Vcc Current
lsa
-
-
25
mA
CE = VIH
VppCurrent
Ippl
-
1
20.
~
Vpp= 5.5 V
Input Voltage
VIH
2.2
-
Vee + 1 2
V
V
-0..3 1
-
0..8
V
V""
2.4
V
In. = -4o.o.~
VOL
-
-
-
0..45
V
IOL =2.1 mA
Output Voltage
Notes:
1.
2.
50.
mA
lOOT = 0. mA, CE = VIL
10.0.
mA
lOUT = 0. mA, f = 10. MHz
VI Lmin = -1 .0. V for pulse width s 50. ns.
VIH max .;. Vcc + 1.5 V for pulse width S 20. ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
HITACHI
4-38
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C1024H Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc" 5V ± 10%, Vpp" Vss to VCC' T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V 12.4 V
s; 10 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V12.0 V
·85
toe
-
loF
toH
Address Access Time
tACe
Chip Enable Access Time
teE
Output Enable Access
Time
Output Disable to High-Z 1
Output Hold to Address
Change
Note:
•
-15
·12
·10
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
Item
1.
Test
Condition
100
-
120
-
150
ns
CE=OE=V1L
100
-
150
ns
OE = V1L
50
-
120
45
-
60
-
60
ns
CE = V1L
0
30
0
50.
0
50
0
50
ns
CE =V1L
0
-
0
-
0
-
0
-
ns
CE = OE = V1L
85
85
~ is defined as the time at which the output becomes an open circuit and data is no
longer driven.
READ TIMING WAVEFORM
Address
CE
OE
K
~
Standby Mode
1
Active Mode
tCE
\
Standby Mode
I
tOE
tACC~
Data Out
I
///
'\.\.\.\.
tOF
tOH
.-
t-:--=-
Data Out Valid
\1\
W
(TD.R.HN27Cl024H)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94oo5-1819· (415) 589-8300
4-39
~------------.
HN27e1024Hserles--------------------~
•
DC ELECTRICAL CHARACTERlSnCS FOR PROGRAMMING OPERAnONS
(Vee = 6.25 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V, T. = 25°C ± 5 0C)
Item
Symbol
Min.
Typ.
Max.
Unit
,.est Condition
-
2
~
VIN = 6.5 VI 0.45 V
Operating Vcc Current
lee
-
50
mA
Operating Vpp Current
Ipp
-
-
40
mA
-
Vee +.5 6
V
0.8
V
-
V
IOH= -400 ~ .
0.45
V
100 =2.1 mA
Input Leakage Current
Input Voltage 3
Output Voltage
Notes:
1.
2.
3.
4.
5.
6.
III
VIH
2.2
V
- 0.15
Voo
2.4
VdL
-
CE = PGM = VIL
Vcc must be applied before Vpp and removed after Vpp'
Vppmust not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
Do not change Vpp from VIL to 12.5 Vor 12.5 V to VIL when CE = low.
VI Lmin = -0.6 V for pulse width s; 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
HITACHI
4-40
Hitachi America, Ltd. - 2000 Sierra Point Pkwy. -Brisbane, CA9400S-1819 - (41S) 589-8300.
- - - - - - - - - - - - - - - - - - - HN27C1024H Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.25 V ± 0.25 V, Vpp = 12.~ V ± 0.3 V, T. =25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V 12.4 V
20 ns
0.8 V 12.0V
:S
Symbol Min.
Typ.
Max.
Unit
lIS
tAS
2
-
-
Address Hold Time
tAH
0
Data Setup Time
tos
2
Data Hold Time
-
-
Address Setup Time
tOH
2
Chip Enable Setup Time
tees
2
Vpp Setup Time
typs
2
Vcc Setup Time
tyes
2
Output Enable Setup Time
toes
2
Output Disable Time
tOF
-
lIS
lIS
I1s
lIS
I1s
-
lIS
-
I1s
0
-
130
ns
\Pw
tapw
0.19
0.20
0.21
ms
0.19
ms
toe
0
150
ns
Output Enable Pulse During Data Latch
~w
1
-
5.25
Data Valid from Output Enable Time
Output Enable Hold Time
PGM Initial Programming Pulse Width
PGM Overprogramming Pulse Width
toeH
2
-
Chip Enable Hold Time
teeH
2
PGM Setup Time
\PGMS
2
-
Note:
1.
-
Test Condition
I1s
I1s
lIS
I1s
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
•
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
4-41
HN27C1024Hserle$------------------•
PAGE PROGRAMMING FLOWCHART
The Hitachi I-:IN27C1024H can be programmed with the high performance Page Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
.
SET PAGE PROG. LATCH MODE
Vpp=12.5±O.3V VCc=6.0±O.25V
NO
SET PAGE PROG.NERIFY MODE
Vpp=12.5±O.3V, VCC=6.0±O.25V
YES
Address + 1--+Address
SET PAGE MODE
Vcc=5.0±O.25 V Vpp=VCC
NOGO
(FC.PP .HN27C1024H)
HITActt.
4-42
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300
- - - - - - - - - - - - - - - - - - - HN27.Ct024H Se~les
•
PAGE PROGRAMMING TIMING WAVEFORM
Page data latch
Page program
Program verify
A1 toA15
AO
Data
Data Out Valid
Vpp
Vee
Vee
(TD.PP.HN27C1024H)
HITACHI
Hitachi America, Ltd •• 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589-8300
4·43
HN27C1024H Serles-----'-------------------•
WORD PROGRAMMING FLOWCHART
The Hitachi HN27C1024H can be programmed with the high performance Word Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
SET PROGNERIFY MODE
Vpp=12.5±O.3V Vcc=6.0±O.25V
Program tpw=O.2ms±5%
Address + 1 ~Address
NOGO
NO
YES
SET READ MODE
Vcc=5.0V±O.25V Vpp=Vcc
NOGO
(FC.P.HN27Cl024H)
HITACHI
4-44
Hitachi America. Ltd .• 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C1024H Series
•
WORD PROGRAMMING nMING WAVEFORM
Program Verify
Program
Address
--X
C
-
tAH
tAS
...,;...:::;..
Data
Data In Stable
./
tos
Vpp
Vpp
Vee
Vee
Vee+ 1
."
Data Out "alid ' /
tOF
.....::.:....
tOH
-.::..:..:..
tvps
~
/
---
Vee
"-
".
~
tves
~
~
tees
tpw
~~
-
toe
.......
/
(TD.P.HN27Cl024H)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, eA 94005·1819· (415) 589·8300
._------- - - - - - - - - - - - - - - -
4-45
HN27C1024H.Serl.es----------------~--
•
ERASING THE HN27C1024H
The Hitachi HN27C1024H Ceramic DIP and Ceramic LCC packages allow these devices to be erased by
exposure to ultraviolet light of 2537A. All of the data is changed to "1 " after this erasure procedure. The minimum
integrated dose (UV intensity x exposure time) for erasure is 15 W-sec/crrf2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device ldentif.ier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C1024H SERIES IDENTIFIER CODE
Identifier
Ao
Manufacturer Code
V
Device Code
V1H
Notes:
1/°8-1/°15 1/°7
X
0
X
1
1/08
1/05
0
0
1/°3
0
1/°4
0
1
1
0
1/°2
1
1/°1
1
1
0
1
1/00 Hex Data
1
07
0
BA
1. . Vee =5.0 V ± 10%
2. Aa=12.0V:t:0.5V _
__
3. AtAa, A10-A15 , CE, OE = V1L , PGM = V1H
4. X = Don't Care
•
HN27C1024HCP RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C1 024HCP package, please make the following screening (baking without bias)
shown below:
(RSC.EPROM)
HITACHI
4-46
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
HN27C1 01 A Series
1 M (128K x 8-bit) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27C 101 A is a 1-Megabit Ultraviolet Erasable and
One-Time Programmable Electrically Programmable Read Only
Memory organized as 131,072 x 8-bits.
The HN27C101A features fast address access times and low
power dissipation. This combination makes the HN27C 101 A suitable
for high speed microcomputer systems. The HN27C 101 A offers high
speed programming using page programming mode.
Hitachi's HN27C1 01 A is offered in JEDEC-Standard Byte-Wide
EPROM pinouts in 32-pin Ceramic and Plastic DIP and 32-lead
Plastic SOP and TSOP packages. This allows socket replacement
with Flash Memory and Mask ROMs. The HN27C101A TSOP
package is offered in both standard and reverse bend pinouts.
The Ceramic DIP package is erasable by exposure to Ultraviolet
light. The Plastic DIP, SOP and TSOP packaged devices are OneTime Programmable and once programmed, can not be rewritten .
•
FEATURES
• Fast Access Times:
100 ns/120 ns/150 ns/200 ns (max)
• Single Power Supply:
Vcc =5V±100/0
• Low Power Dissipation:
Active Mode:
50 mW/MHz (typ)
Standby Mode: 5 IlW (typ)
• High Speed Page and Word Programming:
Page Programming Time: 14 sec (typ)
• Programming Power Supply:
Vpp = 12.5 V ± 0.3 V
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
Flash Memory and Mask ROM Compatible
• Packages:
32-pin Ceramic DIP
32-pin Plastic DIP
32-lead Plastic SOP
32-lead Plastic TSOP (Type II)
(DG-32)
(DP-32)
(TIP-32D)
(TIP-32DR)
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-47
HN27C101A Series . - - - - - - - - - - - - - - - - - - •
ORDERING INFORMATION
Type No.
HN27C101AG-10
HN27C101AG-12
HN27C101AG-15
HN27C101AG-20 .
HN27C1 01 AP-12
HN27C101AP-15
HN27C101AP-20
HN:27C101AFP-12
HN27C101AFP-15
HN27C101 AFP-20
HN27C1 01 ATI-12
HN27C101ATI-15
HN27C101ATI-20
HN27C101ARR-12
HN27C101ARR-15
HN27C1 01 ARR-20
•
Access Time
100 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
Package
32-pin Ceramic DIP
(DG-32)
32-pin Plastic DIP
(DP-32)
32-lead Plastic SOP
(FP-32D)
32-lead Plastic TSOP
(TIP-32D)
32-lead Plastic TSOP
(TIP-32DR)
Reverse bend
PIN ARRANGEMENT
HN27C101AG/P Series
HN27C101AFP Series
HN27C101ATI Series
Vpp
A16
A15
A12
A7
A6
AS
A4
A3
A2
A1
AO
1100
1/01
1/02
Vss
HN27C101ARR Series
Vee
VPP
PGM
A16
A15
A12
A7
A6
AS
A4
A3
Vee
PGM
32·PINOIP
32·LEADSOP
32·LEAD TSOP
TOP VIEW
NC
NC
A14
A13
AS
A9
A11.
A14
A13
AS
A9
A11
OE
OE
A10
A10
CE
CE
1107
1106
1/07
1/05
1/04
1/03
1/05
1/04
1/03
26
7
25 REVERSE PINOUT S
24
23
22
32·LEAD TSOP
TOP VIEW
9
10
A1
AO
1/00
1106
1/01
1/02
Vss
(PinT2.HN27C101A)
(PinD32.HN27C101A)
HITACHI
4-48
A2
Hitachi America. Ltd.• 2000 Sierra Point Pkwy.· Brisbane. eA 94005·1819 • (415) 589·8300
- - - - - - - - - - - - - - - - - - - - HN27C101A Series
•
PIN DESCRIPTION
Pin Name
Function
Ao - A16
Address
1100 - 1107
Input/Output
CE
OE
Chip Enable
Output Enable
Power Supply
Vee
Vpp
•
Programming Supply
Vss
Ground
PGM
Programming Enable
NC
No Connection
BLOCK DIAGRAM
A5
\
A9
X- Decoder
1024 X 1024
Memory Matrix
Input
Data
Control
Y - Decoder
~12 o-----t{:~==~
A16
1/00 o---4~---H
\
1/07o---It--_--f-'i
Y -Gating
CE 0 - - - - 1
OE 0 - - - - 1
PGM
0----1
":>o+f+=L-j---Ir---l
AD-A4
A10,A11
~~-.=I
Vee 0 - Vpp
O-l:=-fHool
[B>o :High Threshold Inverter
Vsso-(BD.HN27C101A)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-49
HN27C101A Series
•
MODE SELECTION
Mode
Vpp
Vee
OE
Read
Vee
Vee
PGM
As
I/O
V'L
V;L
V'L
V,H
V,H
V,H
X'
X
Output Disable
Vee
Vee
Dour
High-Z
Standby
Vee
Vee
V,H
X
X
X
High-Z
Program
Program Verify
Vpp
Vee
V'L
V,H
X
D'N
Vpp
Vee
V'L
X
Dour
Page Data Latch
Vpp
Vee
V'L
V,H
V'L
V,H
Vpp
Vee
V,H
V,"
V
X
Page Program
V'L
V,H
X
D'N
High-Z
Program Inhibit
Vee
Vee
V'L
High-Z
Vee
V'L
V,H
X
Vpp
V'L
V,H
X
High-Z
V'L
V,H
X
High-Z
X
High-Z
V,H
VH
ID
Identifier
Notes:
•
Vpp
Vee
V'L
V,H
Vpp
Vee
V,H
V'L
V,H
Vee
Vee
V'L
V'L
,
1. X = Don't Care. Vpp = 0 V to Vee'
2.11.5VS;VH S;12.5V
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage'
Vee
-0.6 to +7.0
V
Programming Voltage'
Vpp
-0.6 to +13.5
V
V,N. Voor
-0.6 to +7.0
V
All Input and Output Voltage '.2
As and OE Voltage 2
V,D
-0.6 to +13.0
V
Operating Temperature Range
TOPR
oto +70
°c
Storage Temperature Range
TSTG
-65 to +125 3
-55 to +125 4
°C
Storage Temperature Under Bias
T81AS
oto +80
°C
Notes:
•
CE
1.
2.
3.'
4.
Relative to Vss'
V, N' VOUT' and V,D min = -1.0V for pulse width S; 20 ns.
HN27C101AG.
HN27C101AP, HN27C101AFP, HN27C1 01 AT! and HN27C101ARR.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
Input Capacitance
Output Capacitance
Symbol
Min.
Max.
Unit
C'N
Cour
-
10
pF
V'N = OV
15
pF
Voor= OV
Test Condition
HITACH'
4-50
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane.CA 94005·1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C101A Series
•
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%,Vpp = Vssto Vw Ta = 0 to 70°C)
Item
Input Leakage Current
Output Leakage Current
Operating Vcc Current
Symbol
Min.
Typ.
Max.
Unit
Test Condition
ILl
ILO
~
VIN = 5.5 V
Icc2
-
-
2
Iccl
-
Standby Vcc Current
IS8
VppCurrent
Ippl
-
Input Voltage
VIH
·2.2
V
-0.3
Icc3
Output Voltage
Notes:
•
1.
2.
VOH
2.4
VOL
-
1
2
~
VOUT = 5.5 V/0.45 V
30
mA
louT = 0 mA, CE = VIL
30
mA
lOUT = 0 mA, f = 5 MHz
50
mA
louT = 0 mA, f = 10 MHz
1
mA
CE = VIH
1
20
~
Vpp= 5.5 V
-
Vcc + 1 2
V
0.8
V
-
V
IOH = -400 ~
0.45
V
IOL = 2.1 mA
VI Lmin = -1.0 V for pulse width s; 50 ns.
VIH max = Vcc + 1.5 V for pulse width S; 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vpp = Vss to Vcc ' Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
0.45 V /2.4 V
s; 10 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V/2.0 V
·10
100
toe
-
Output Disable to High-Z 1
tOF
Output Hold to Address
Change
tOH
Address Access Time
tACC
Chip Enable Access Time
Ice
Output Enable Access
Time
Note:
·15
·12
·20
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
Item
1.
120
60
-
0
50
0
-
100
150
60
-
0
50
0
-
120
Test
Condition
200
ns
200
ns
OE = VIL
70
-
70
ns
CE = VIL
0
50
0
50
ns
CE = VIL
0
-
0
-
ns
CE = OE = VIL
150
CE = OE = VIL
!oF is defined as the time at which the output becomes an open circuit and data is no longer
driven.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589·8300
4-51
HN27C101A Series
•
READ TIMING WAVEFORM
~
Address
CE
K
Standby Mode
}
Active Mode
tCE
tOF
r:--=tOH
tOE
-
tACcl~
///
\.\\
Data Out
....
,;
\
OE
,; Standby Mode
Data Out Valid
(TD.R.HN27C101A)
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.25 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V, Ta = 25 °C ± 5°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
-
2
J.lA
VIN = 0 V to Vee
Operating Vee Current
lee
-
30
rnA
Operating Vpp Current
Ipp
-
Input Voltage 3
VIH
2.2
VIL
- 0.15
Output Voltage
VOH
2.4
Notes:
1.
2.
3.
4.
5.
6.
-
40
rnA
Vee +.5 6
V
0.8
V
-
V
CE= PGM = VIL
IOH = -400 J.lA
0.45
V
IOH = 2.1 rnA
VOL
Vee must be applied before Vpp and removed after Vpp.
Vppmust not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V,
Do not change Vpp from VIL to 12.5 Vor 12.5 V to VIL when C"E = low.
VI L min = -0.6 V for pulse width ~ 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
HITACHI
4-52
Hitachi America,ltd.· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C101A Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.25 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V, T. = 25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V I 2.4 V
~ 20 ns
0.8 V 12.0V
Symbol Min.
Typ.
Max.
Unit
-
J.lS
tAS
2
Address Hold Time
tAH
0
Data Setup Time
tos
2
tOH
2
leES
tvps
2
2
-
Vee Setup Time
tves
2
-
Output Enable Setup Time
Address Setup Time
Data Hold Time
Chip Enable Setup Time
Vpp Setup Time
J.lS
J.lS
J.lS
J.lS
I1s
I1s
tOES
2
-
-
Output Disable Time
tOF
0
-
130
I1s
ns
PGM Initial Programming Pulse Width
tpw
0.19
0.20
0.21
ms
PGM Overprogramming Pulse Width
-
5.25
ms
150
ns
-
I1s
topw
0.19
Data Valid from Output Enable Time
tOE
0
Output Enable Pulse During Data Latch
tlW
1
Output Enable Hold Time
loEH
2
Chip Enable Hold Time
teEH
tpGMS
2
PGM Setup Time
Note:
1.
2
Test Condition
-
J.lS
-
I1s
I1s
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
II
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
4-53
HN27C1 01 A Series.
•
PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C1 01 A can be programmed with the high performance Page Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
SET PAGE PROG. MODE
Vpp= 12.S±0.3V Vcc=6.0±0.2SV
NO
Address+1
SEI PAGE PROG.I
VERIFY MODE
~Address
Vpp=12.S±0.3V,
Vcc=6.0±0.2SV
B
NO
SET PAGE MODE
Vcc=S.0±0.2S V, Vpp=Vcc
NOGO
(FC.PP.HN27C101A)
HITACHI
- 4-54
Hitachi America, Ltd. ·2000 Sierra PO,int Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300
- - - - - - - - - - - - - - - - - - - HN27C101A8erles
•
PAGE PROGRAMMING TIMING WAVEFORM
Page data latch
Page program
Program verify
A2 toA1S
AO,Al
Data
Data Out Valid
\I
vcc
Vpp
VCC
VCC VCC+l
vee
icES
toEH
CE
(TD.PP.HN27Cl01A)
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819 • (415) 589-8300
4-55
----~
HN27C1 01 A Series
•
BYTE PROGRAMMING FLOWCHART
The Hitachi HN27C101A can be programmed with the high performance Byte Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
SET PROOIVERIFY MODE
Vpp=12.S±O.3V Vcc=6.0±O.2SV
Program tpw=1 ms±S%
Address + 1 ~Address
NOGO
Program topw=O.2 ms
NO
YES
SET READ MODE
Vcc=S.O±O.2SV Vpp=Vcc
NOGO
(FC.P.HN27Cl01A)
HITACHI
4-56
HilachiAmerica, Ltd.· 2000 Sierra Point Pkwy.· Brisbane,CA 94005-1819· (415) 589.8300
- - - - - - - - - - - - - - - - - - - HN27C101A Series
•
BYTE. PROGRAMMING TIMING WAVEFORM
Program
Address
Program Verify
----x
~
tAH
tAS
....:.=..
Data
Vpp
Vee
~
"Data Out Valid /
'
Data In Stable
vpp
vee
-
V
V~~+1
-
-
-
tos
/
tOF
-...=...
tOH
.....=.:-:.
tvps
.;.;..::0;
/~
tves
~
"'teEs
't;f
tpw
~~ ~
r....
/
(TD.P.HN27C101A)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819· (415) 589·8300
4·57
HN27C101 A Series
•
ERASING THEHN27C101A
The Hitachi HN27C1 01 A Ceramic DIP package allow the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type .of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C101A SERIES IDENTIFIER CODE
Identifier
Ao
1/°7
I/Os
1/°5
1/°4
1/03
1/°2
110,
1/°0
Hex Data
Manufacturer Code
V
0
0
0
0
0
1
1
1
07
Device Code
VIH
0
0
1
1
1
0
0
0
38
Notes:
1.
2.
3.
4.
Vee = 5.0 V ± 10%
Ag= 12.0V±0.5V _
__
A,-A8, A,o-A,s' CE, OE = V1L , PGM = VIH
X = Don't Care'
•
HN27C101AP/FPITT/RR RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C1 01A plastic packages, please make the following screening (baking without
bias) shown below:
(RSC.EPROM)
HITACHI
4-58
Hitachi America. Ltd. -2000 Sierra Point Pkwy. - Brisbane. CA 94005-1819 - (415) 589·8300
HN27C301 A Series
1M (128K x 8-blt) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27C301 A is a 1-Megabit Ultraviolet Erasable and
One-Time Programmable Electrically Programmable Read Only
Memory organized as 131,072 x a-bits.
The HN27C301A features fast address access times and low
power dissipation. This combination makes the HN27C301 A suitable
for high speed microcomputer systems. The HN27C301 A offers high
speed programming using page programming mode.
Hitachi's HN27C301 A is offered in 32-pin Ceramic and Plastic
DIP packages.
The Ceramic DIP package is erasable by exposure to Ultraviolet
light. The Plastic DIP packaged device is One-Time Programmable
and once programmed, can npt be rewritten.
•
•
FEATURES
• Fast Access Times:
100 ns/120 nsl150 nsl200 ns (max)
• Single Power Supply:
Vcc =5V±10%
• Low Power Dissipation:
Active Mode:
50 mWIMHz (typ)
Standby Mode: 5 JlW (typ)
• High Speed Page and Word Programming:
Page Programming Time: 14 sec (typ)
• Programming Power Supply:
Vpp = 12.5 V ± 0.3 V
• Packages:
32-pin Ceramic DIP
32-pin Plastic DIP
(DG-32)
(DP-32)
ORDERING INFORMATION
Type No.
HN27C301 AG-1 0
HN27C301 AG-12
HN27C301 AG-15
HN27C301 AG-20
HN27C301 AP-12
HN27C301 AP-15
HN27C301AP-20
Access Time
100 ns
120 ns
150 ns
200 ns
120 ns
150 ns
200 ns
Package
32-pin Ceramic DIP
(DG-32)
II
32-pin Plastic DIP
(DP-32)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-59
HN27C301 A Series
•
PIN ARRANGEMENT
HN27C301 AG Series
HN27C301AP Series
Vpp
Vee
OE
A15
A12
A7
A6
A5
PGM
NC
A14
A13
A8
A9
A11
A16
A10
CE
1/07
1/06
1/05
1/04
1/03
32-PIN DIP
TOP VIEW
A4
A3
A2
A1
AD
1/00
1/01
1/02
Vss
(PinD32.HN27C301A)
•
PIN DESCRIPTION
Pin Name
Function
Ao - A'B
1/00 - 1/07
Address
Input/Output
CE
Chip Enable
OE
Output Enable
Vcc
Power Supply
Vpp
Programming Supply
Vss
Ground
PGM
Programming Enable
NC
No Connection
HITACHI
4-60
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - H N 2 7 C 3 0 1 A Series
•
BLOCK DIAGRAM
A5
\
1024 X 1024
A9
Memory Matrix
X-Decoder
~12 o-----t-D:===~
AI6
1/00 o-__-----1H
\
1I07o--+--.----jH
>----~I::::np:u-:tr-r~_;;:=.l..-r_--__,
Data
> f - - - - - - I Control
CE 0-----1
OE 0 - - - - 1
7V"H-.........----
AQ-A4
Ala, All
PGM 0-----1 X>--+-;=l
Vee 0 - - Vpp o-~::.JfDc>l
iB>o :High Threshold Inverter
Vss 0 - - -
(BD.HN27C30IA)
•
MODE SELECTION
Mode
Vpp
Vcc
CE
OE
PGM
Read
Vee
Vee
VIL
VIL
VIH
Output Disable
Vee
Vee
VIL
VIH
X
I/O
Ag
X1
Dour
VIH
X
High-Z
X
X
High-Z
Standby
Vee
Vee
VIH
Program
Vpp
Vee
VIL
VIH
VIL
X
DIN
Program Verify
Vpp
Vee
VIL
VIL
VIH
X
Dour
Page Data Latch
Vpp
Vee
VIH
V
VIH
X
Page Program
VPI'
Vee
VIH
VIH
V
X
DIN
High-Z
Vee
Vee
VIL
VIL
VIL
X
High-Z
Vpp
Program Inhibit
Identifier
Notes:
1.
2.
Vee
VIL
VIH
VIH
X
High-Z
Vpp
Vcc
VIH
VIL
VIL
X
High-Z
Vpp
Vcc
VIH
VIH
VIH
X
High-Z
Vcc
Vcc
VIL
VIL
VIH
VH
ID
X = Don't Care. Vpp = 0 V to Vcc'
11.5 V ~VH~ 12.5 V
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-61
HN27C301 A Series
•
ELECTRICAL CHARACTERISTICS
REFER TO HN27C101A DATASHEET
•
ERASING THE HN27C301 A
The Hitachi HN27C301 A Ceramic DIP package allow the device to be erased by exposure to ultraviolet
light of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-sec/cm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C301 A SERIES IDENTIFIER CODE
Identifier
Ao
Manufacturer Code
V
Device Code
Notes:
1.
2.
3.
4.
1/°7
0
1/06
0
1/°5
0
1/°4
0
1
0
1
1
V'H
Vcc =5.0V±10%
Ag = 12.0 V ± 0.5V _
__
A(As' Al0-A16 , CE, OE = V'L' PGM = V'H
X = Don't Care
1/°2
1
1/°1
1
1/00
Hex Data
0
1
07
1
0
0
1
B9
1/03
•
HN27C301 AP RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C101AP, please make the following screening (baking without bias) shown
below:
Mount
(Rse.EPROM)
HITACHI
4-62
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN27C4096 Series
4M (256K x 16-blt) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27C4096 is a 4-Megabit Ultraviolet Erasable and
One-Time Programmable Electrically Programmable Read Only
Memory organized as 262,144 x 16-bits.
The HN27C4096 features fast address access times of 100, 120
and 150 ns and low power dissipation. This combination makes the
HN27C4096 suitable for high speed 16 and 32-bit microcomputer
systems. The HN27C4096 offers high speed programming using
page programming mode.
Hitachi's HN27C4096 is offered in JEDEC-Standard Word-Wide
EPROM pinouts in 40-pin Ceramic DIP and 44-lead Ceramic and
Plastic LCC packages. This allows socket replacement with Mask
ROMs.
The Ceramic DIP and Ceramic LCC packages are erasable by
exposure to Ultraviolet light. The PLCC packaged device is OneTime Programmable and once programmed, can not be rewritten.
•
•
FEATURES
• Fast Access Times:
100 nsJ120 ns/150 ns (max)
• Single Power Supply:
Vee = 5 V± 10%
• Low Power Dissipation:
Active Mode:
35 mW/MHz (typ)
Standby Mode: 5 IJ.W (max)
• High Speed Page and Word Programming:
Page Programming Time: 3.5 sec (min)
• Programming Power Supply:
Vpp= 12.5 V± 0.3 V
• Pin Arrangement:
JEDEC Standard Word-Wide EPROM
Mask ROM Compatible
• Packages:
40-pin Ceramic DIP
44-lead Ceramic LCC
44-lead PLCC
(DG-40A)
(CC-44)
(CP-44)
ORDERING INFORMATION
Type No.
HN27C4096G-10
HN27C4096G-12
HN27C4096G-15
HN27C4096CC-10
HN27C4096CC-12
HN27C4096CC-15
HN27C4096CP-12
HN27C4096CP-15
Access Time
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
120 ns
150 ns
Package
40-pin Ceramic DIP
(DG-40A)
44-lead Ceramic LCC
(CC-44)
44-lead PLCC
(CP-44)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-63
HN27C4096 Series
•
PIN ARRANGEMENT
HN27C4096G Series
HN27C4096CC Series
HN27C4096CP Series
Vpp
VCC
CE
A17
A16
A15.
A14
A13
A12
A11
A10
A9
1/015
1/014
1/013
1/012
1/011
1/010
1/09
1/08
40-PIN
DIP
TOP VIEW
Vss
1/0131/0141/015 CE Vpp NC Vee A17 A16 A15 A14
44-LEAD
JLCC and PLCC
TOP VIEW
VSS
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
A8
A7
A6
OE
AO
AS
A4
A3
A2
A1
1/03 1/02 1/01 1/00 OE NC AO A1 A2 A3 A4
(Pin044.HN27C4096)
(PinD40.HN27C4096)
•
PIN DESCRIPTION
Pin Name
Function
Ao - A17
Address
1/00 - 1/°15
Input/Output
CE
Chip Enable
DE
Output Enable
Vee
Power Supply
Vpp
Programming Supply
Vss
Ground
NC
No Connection
HITACHI
4-64
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
BLOCK DIAGRAM
~~----~~====~ xDecoder
2048 x 2048
Memory Matrix
A17o-----tC~====l
1/000--,----H
>-----r=:-r----i-';.::-;;::;:;-"r-----,
\
1/015 o--+--~~-+-I
>1------1
CE 0----1
OEo--~bo~~)--t~
AO ,.--...... AS
119- :High Threshold Inverter
(BD.HN27C4096)
•
MODE SELECTION
Mode
Vpp
Vee
CE
OE
Ag
I/O
Read
Vss-Vee
Vee
V'L
V'L
X'
Output Disable
VssVee
Vee
V'L
V'H
X
DOUT
High-Z
V'H
X
X
High-Z
V'H
VH2
VH
X
High-Z
X
V'H
V
X
D'N
High-Z
DOUT
High-Z
Standby
VssVee
Vee
Page
Page Prog. Set
Vpp
Prog.
Page Data Latch
Vpp
Vee
Page Program
Vpp
Vee
V'L
Page Prog. Verify
Vpp
Vee
V'H
Page Prog. Reset
Vee
Vee
V'H
V'H
X
Word
Program
Vpp
Vee
V'L
V'H
X
D'N
Prog.
Program Verify
Vpp
Vee
V'l
X
DoUT
Optional Verify
Vpp
Vee
V'L
X
DoUT
High-Z
10
Program Inhibit
Identifier
Notes:
1.
2.
Vee
V'L
V'H
V'L
X
Vpp
Vee
V'H
V'H
X
Vss-Vee
Vee
V'L
V'L
VH
X = Don't Care. Vpp =0 V to Vee'
11.5 V ::; VH::; 12.5 V
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-65
HN27C4096 Series
•
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Vee
-0.6 to +7.0
V
Vpp
-0.6 to +13.5
V
V'N. VOUT
-0.6 to +7.0
V
V,o
Item
Supply Voltage
1
Programming Voltage
1
All Input and Output Voltage
1.2
Ag and DE Voltage 2
-0.6 to +13.0
V
Operating Temperature Range
TOPR
oto +70
°C
Storage Temperature Range 3
TSTG
-65 to +125 4
-55 to +125 5
°C
Storage Temperature Under Bias
TBIAS
oto +80
°C
Notes:
•
1.
2.
3.
4.
5.
Relative to Vss'
V, N' VOUT' and V,o min = -2.0V for pulse width:;; 20 ns.
Device storage temperature range before programming.
HN27C4096G and HN27C4096CC.
HN27C4096CP.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
Symbol
Min.
Typ.
Max.
Unit
C'N
-
-
12
pF
V'N = OV
20
pF
VOUT = OV
Input Capacitance
Output Capacitance
•
COUT
Test Condition
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vec = 5V ± 10%, Vpp = Vssto Vee' T. = 0 to 70°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
-
2
~
V'N = 5.5 V
2
~
VOUT = 5.5 V/0.45 V
30
rnA
lOUT = 0 rnA, f = 1 MHz
100
rnA
lOUT = 0 rnA, f = 10 MHz
1
rnA
CE = V'H
1
20
~A
CE = Vcc ± 0.3 V
1
20
~
Vpp= 5.5 V
-
Vcc + 12
V
0.8
V
-
V
IOH = -400 ~
0.45
V
IOL = 2.1 rnA
Input Leakage Current
III
-
Output Leakage Current
ILO
-
Operating Vee Current
Iccl
Ippl
-
V'H
2.2
V'L
VOH
-0.3
VOL
-
Icc2
Standby Vcc Current
ISBl
1SB2
VppCurrent
Input Voltage
Output Voltage
Notes:
1.
2.
2.4
1
VI Lmin =-1.0 V for pulse width:;; 50 ns.
V, Lmin = -2.0 V for pulse width:;; 20 ns.
V'H max = Vcc + 1.5 V for pulse width:;; 20 ns.
If V'H is over the specified maximum value. Read operation can not be guaranteed.
HITACHI
4-66
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%. Vpp = Vss to Vee. T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
HN27C4096-10
HN27C4096-12
HN27C4096-12
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address Access Time
tACC
100
120
150
ns
CE = OE = V1L
Chip Enable Access Time
100
-
150
ns
OE=V1L
70
ns
CE = V1L
Item
Test
Condition
leE
-
Output Enable Access
Time
toe
-
60
-
60
-
Output Disable to High-Z '
tOF
0
35
0
40
0
50
ns
CE = V1L
Output Hold to Address
Change
too
5
-
5
-
5
-
ns
CE=OE=V1L
Note:
•
0.45 V /2.4 V
:s; 10 ns
1 TTL Gate + 100 pF (Including scope and jig)
0.8 V/2.0 V
1.
120
tOF is defined as the time at which the output becomes an oeen circuit and data is no
longer driven.
READ TIMING WAVEFORM
)~
Address
Standby Mode
OENp P
K
1
Active Mode
tCE
\
I
I
tOF
tOE
tACC~
Data Out
Standby Mode
L/'/L
'\. \.'\
~
Data Out Valid
tOH
I\r\.
LV
(TD.R.HN27C4096)
HITACHI
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.' Brisbane, CA94005-1819' (415) 589-8300
4-67
HN27C4096 S~ries
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.25 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V, T. =25 °C ± 5 °C)
Item
Symbol
Min.
III
Operating Vee Current
lec
Operating Vpp Current
Ipp
-
Input Voltage 3
Input Leakage Current
Output Voltage
Notes:
1.
2.
3.
4.
5.
6.
7.
Typ.
Max.
Unit
Test Condition
VIN = 6.5 VI 0.45 V
-
2
~A
50
mA
VIH
2.2
VIL
- 0.15
-
VH
11.5
12.0
12.5
V
VOH
2.4
-
-
V
70 7
Vcc +·5
0.8
mA
6
CE = VIL
V
V
IOH = -400 ~
0.45
V
IOH = 2.1 mA
VOL
Vcc must be applied before Vpp and removed after Vpp'
Vpp must not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
_
Do not change Vpp from VIL to 12.5 V or 12.5 V to VIL when CE = low.
VI L min =-0.6 V for pulse width:;; 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
Ipp = 40 mA in Word Programming Mode.
HITACHI
4-68
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee =6.25 V ± 0.25 V, Vpp =12.5 V ± 0.3 V, T. =25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V 12.4 V
~ 20 ns
0.8 VI 2.0V
Symbol Min.
Typ.
Max.
Unit
-
I1S
130
ns
toes
2
Output Disable Time
tOF
0
-
Programming Pulse Width
Address Setup Time
tAS
2
Address Hold Time
tAH
0
Data Setup Time
tos
2
Data Hold Time
tOH
2
Chip Enable Setup Time
~ES
tvps
2
Vpp Setup Time
Vee Setup Time
tvcs
2
Output Enable Setup Time
2
I1s
I1s
I1s
I1S
I1S
I1S
I1S
tpw
47.5
50.0
52.5
I1s
Data Valid from Output Enable Time
tOE
0
150
ns
Chip Enable Pulse Width During Data Latch
tLw
1
-
I1s
Output Enable =VHSetup Time
-
tOHS
2
Output Enable =VHHold Time
tOHH
2
Output Enable Hold Time
toeH
2
tvRS
1
tvLW
1
Vpp Hold Time
Page Programming Reset Time
Note:
1.
2.
Test Condition
I1s
I1S
I1S
I1S
I1S
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
Page Program Mode will be reset when Vpp is set to Vee or less.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane. CA 94005·1819· (415) 589-8300
4-69
HN27C4096 Series
•
PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4096 can be programmed with the high performance Page Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
Note:
1.
2.
To set the device into Page Programming, apply 12.5 V toVpp then followed by applying
12 V to CE. The device operates in Page Program Mode until reset.
To reset the Page Program Mode, set Vpp = Vcc or less.
SET PAGE PROG. LATCH MODE
Vpp=12.5±0.3V Vcc =6.25±0.25V
0E=12.0±0.5V
Address + 1 --> Adress
Address + 1 --> Adress
SET PAGE PROGNERIFY MODE
Vpp=12.5±0.3V Vcc =6.25±0.25V
Address + 1 --> Adress
YES
(FC.PP .HN27C4096)
HITACHI
4-70
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
PAGE PROGRAMMING TIMING WAVEFORM
Page Program Mode
Program Data Latch..
Page Program ••
Program Verify
A2-A17
AO,A1
--~
Data
Data Out Valid
Vpp
Vpp
Vcc
(TD.PP.HN27C4096)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-71
HN27C4096 Series
•
WORD PROGRAMMING FLOWCHART
The Hitachi HN27C4096 can be programmed with the high per:formance Word Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
SET PROGIVERIFY MODE
Vpp=12.5±O.3V Vcc=6.25±O.25V
Program tpw=50IJs±5%
Address + 1 ~Address
NOGO
YES
SET READ MODE
Vcc=5.0±O.5V Vpp=Vcc
NOGO
(F.C.P.HN27C4096)
HITACHI
4-72
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
WORD PROGRAMMING TIMING WAVEFORM
Address
-
. . Program Verify
Program
,
,
pC
)<
tAH
~
Data
r-
Data In Stable
-
VPP
V'cc
Vee
V
~~+1.2~~
V
<
~I
~E
Data Out Val d /"-'
lt~
~
..!llli..
tos
Vpp
~
/f-
!vp§
I,tve,
CE
V
tpw
~
./
(TD.P.HN27C4096)
II
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, eA 94005-1819· (415) 589-8300
4-73
HN27C4096 Series
•
OPTIONAL PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4096 can be programmed with the high performance Optional Page Programming
algorithm shown in the following flowchart. This algorithm provides a fast programming time without voltage
stress to the device or deterioration in reliability of programmed data.
This programming algorithm is acombination of Page Programming and Word Verify. It can be used to avoid
the increased programming verify time when a programmer with a slower machine cycle is used and shorten
the total programming time.
Please refer to the timing specifications for page programming and word programming.
Address + 1 ---. Address
(FC.OPP.HN27C4096)
HITACHI
4-74
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005·1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096 Series
•
OPTIONAL PAGE PROGRAMMING TIMING WAVEFORM
Word Program Mode
Page Program Mode
)
Program Data Latch Page Program
Program Verify
Program
A2-A17
AO,A1
Data
Vpp
vPP
Vee
tVRS
tVLW
(TD.OPP.HN27C4096)
HITACHI
Hitachi America. Ltd. - 2000 Sierra Point Pkwy. -Brisbane. CA 94005-1819 - (415) 589-8300
4-75
HN27C4096 Series
1---------------------
•
ERASING THE HN27C4096
The Hitachi HN27C4096 Ceramic DIP and Ceramic LCC packages allow these devices to be erased by
exposure to ultraviolet light of 2537A. All of the data is changed to "1" afte,rthis erasure procedure. The minimum
integrated dose (UV intensity x exposure time) for erasure is 15 W-seclcm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment. the device will automatically match its
own erase and programming algorithm.
•
HN27C4096 SERIES IDENTIFIER CODE
Identifier
Ao
11°7
0
11°6
0
1/°4
1/°3
1/°2
110,
V1L
1I0s-1I0,5
X
1/°5
Manufacturer Code
0
0
0
1
1
1
07
Device Code
VH
X
1
0
1
0
0
0
1
0
A2
Notes:
1.
2.
3.
4.
Vee = 5.0 V ±.10%
A9 = 12.0 V ± 0.5V _
A,-As• A,o-A'7' CEo OE
X = Don't Care
1/°0 Hex Data
=V1L
•
HN27C4096CP RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C4096CP package. please make the following screening (baking without bias)
shown below:
(RSC.EPROM)
HITACHI
4-76
Hitachi America. Ltd .• :;!OOO Sierra Point Pkwy.· Brisbane. CA 94005-1819 • (415) 589-8300
HN27C4096H Series-------- Preliminary
4M (256K x 16-blt) UV EPROM
•
DESCRIPTION
The Hitachi HN27C4096H is a 4-Megabit Ultraviolet Erasable
and Electrically Programmable Read Only Memory organized as
262,144 x 16-bits.
The. HN27C4096H features high speed access times of 70 and
85 ns and low power dissipation. This combination makes the
HN27C4096H suitable for high speed 16 and 32-bit microcomputer
systems. The HN27C4096H offers high speed programming using
page programming mode.
Hitachi's HN27C4096H is offered in JEDEC-Standard WordWide EPROM pinouts in 40-pin Ceramic DIP and 44-lead Ceramic
LCC packages. This allows socket replacement with Mask ROMs.
•
•
FEATURES
• High Speed Access Times:
70 ns/85 ns (max)
• Single Power Supply:
Vcc =5V±100/0
• Low Power Dissipation:
Active Mode:
35 mW/MHz (typ)
Standby Mode: 30 mA (max)
• High Speed Page and Word Programming:
Page Programming Time: 3.5 sec (min)
• Programming Power Supply:
Vpp = 12.5 V ± 0.3 V
• Pin Arrangement:
JEDEC Standard Word-Wide EPROM
Mask ROM Compatible
• Packages:
40-pin Ceramic DIP
44-lead Ceramic LCC
(DG-40A)
(CC-44)
ORDERING INFORMATION
Type No.
HN27C4096HG-70
HN27C4096HG-85
HN27C4096HCC-70
HN27C4096HCC-85
Access Time
70 ns
85 ns
70 ns
85 ns
Package
40-pin Ceramic DIP
(DG-40A)
44-lead Ceramic
(CC-44)
mc
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-77
HN27C4096HSeries-------------------•
PIN ARRANGEMENT
HN27C4096HG Series
HN27C4096HCC Series
Vpp
CE
1/015
1/014
1/013
1/012
1/011
1/010
1/09
1/08
40-PIN
DIP
TOP VIEW
Vss
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
Vee
A17
A16
A15
A14
A13
A12
A11
A10
A9
Vss
A8
A7
A6
1/0131/0141/015 CE Vpp NC Vee A17 A16 A15 A14
44-LEAD
PLCC
TOP VIEW
AS
A4
A3
A2
A1
1/03 1/02 1/01 1/00 OE NC AO A 1 A2 A3 A4
AO
OE
(Pin044.HN27C4096H)
(PinD40.HN27C4096H)
•
A13
A12
All
Al0
A9
Vss
NC
A8
A7
A6
A5
PIN DESCRIPTION
Pin Name
Function
Ao - A17
Address
1/00 - 1/015
Input/Output
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vpp
Programming Supply
Vss
Ground
NC
No Connection
HITACHI
4-78
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096H Series
•
BLOCK DIAGRAM
I--
A7
xDecoder
,.:::J
>-
A17
2048 x 2048
Memory Matrix
I--
2
~
1/00
V(
\
1/015
Input
Data
Control
L--(
n
r
V-Gating
r
V- Decoder
I
r
.l
,.
y
I
r
I
'---
k: -----:-fl.
V
0--
•
T-
AO ------ AS
~ . H'gh Threshold Inverter
(BD.HN27C4096H)
MODE SELECTION
I/O
Mode
Vpp
Vce
CE
OE
Read
Vss-Vcc
Vee
V'l
V'l
Ag
X'
Output Disable
Vss-Vee
Vee
V'l
V'H
X
Dour
High-Z
Standby
Vss-Vee
V'H
X
X
High-Z
V'H
V2
H
VH
X
High-Z
X
V,
X
D'N
High-Z
V
X
DnllT
High-Z
Vce
Page
Page Prog. Set
Vpp
Prog.
Page Data Latch
Vpp
Vee
Page Program
Vpp
Vee
V'l
V,
Page Prog. Verify
Vpp
Vee
V,~
Vce
Page Prog. Reset
Vee
Vee
V'H
V'H
X
Word
Program
Vpp
Vee
V'l
V'H
X
D'N
Prog.
Program Verify
Vpp
Vee
V'l
X
Dour
Optional Verify
Vpp
Vee
V'l
X
Dour
High-Z
10
Program Inhibit
Identifier
Notes:
1.
2.
V'H
V'l
Vpp
Vee
V'H
V'H
X
Vss-Vee
Vee
V'l
V'l
VH
x = Don't Care. Vpp = 0 V to Vec'
11.5 V ~ VH~ 12.5 V
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point .Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
4-79
II
HN27C4096H Series - - - - - - - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Value
Unit
Vee
-0.6 to +7.0
V
Vpp
-0.6 to +13.5
V
VI NYouT
V,O
-0.6 to +7.0
V
-0.6 to +13.0
V
TOPR
oto +70
°C
TSTG
-65 to +125
°C
TBIAS
o to +80
°C
1
Programming Voltage
1
All Input and Output Voltage 1.2
Ag and OE Voltage 2
Operating Temperature Range
Storage Temperature Range
3
Storage Temperature Under Bias
Notes:
•
1.
2.
3.
Relative to Vss'
V, N' VOUT' and V,O min = -2.0V for pulse width :0; 20 ns.
Device storage temperature range before programming.
CAPACITANCE (T. = 25°C, f = 1MHz)
Item
•
Symbol
Min.
Typ.
Max.
Unit
Input Capacitance
C'N
V,N = OV
COUT
-
pF
Output Capacitance
-
12
20
pF
VOUT =' OV
Test Condition
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc= 5V ± 10%, Vpp = Vss to VcC' T. = 0 to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
Item
III
2
ILO
I!A
.I!A
V,N = 5.5 V
Output Leakage Current
Operating Vce Current
Iccl
1
VppCurrent
Ippl
-
Input Voltage
V,H
2.2
-
Vec + 12
V
0.8
V
-
V
IOH = -400 I!A
0.45
V
IOL = 2.1 mA
Icc2
Standby Vee Current
Output Voltage
Notes:
1.
2.
ISB
V,L
-0.3 '
-
VOH
2.4
VOL
-
-
2
VOUT = 5.5 V/0.45 V
30
mA
lOUT = 0 mA, f = 1 MHz
140
mA
lOUT = 0 mA, f = 14.3 MHz
30
mA
CE = V,H
20
I!A
Vpp= 5.5 V
V, Lmin = -1.0 V for pulse width :0; 50 ns.
V, Lmin = -2.0 V for pulse width :0; 20 ns.
V,H max = Vcc + 1.5 V for pulse width :0; 20 ns.
If V,H is over the specified maximum value, Read operation can not be guaranteed.
HITACHI
4-80
Hitachi America.
Ltd. ·2000 Sierra Point Pkwy.· Brjsbane. CA 94005-1819· (415) 589-8.300
,
- - - - - - - - - - - - - - - - - - - - HN27C4096H Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(VCC = 5V ± 10%. Vpp = Vss to Vcc' T. = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
Item
HN27C4096H·70
HN27C4096H·85
Symbol
Min.
Max.
Min.
Max.
Unit
85
ns
CE = OE = V1L
85
ns
OE = V1L
45
ns
CE = V1L
Test
Condition
tACC
-
70
Chip Enable Access Time
tCE
Output Enable Access
Time
tOE
-
70
40
-
Output Disable to High-Z 1
toF
0
30
0
30
ns
CE = V1L
Output Hold to Address
Change
tOH
5
-
5
-
ns
CE=OE=V,L
Address Access Time
Note:
•
0.45 V / 2.4 V
$10 ns
1 TTL Gate + 100 pF (Including scope and jig)
1.5 V
1.
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
READ TIMING WAVEFORM
Address
CE
OE
K
X
Standby Mode
1
Active Mode
tCE
V Standby Mode
\
V
tOE
tACC I--=+
Data Out
////
\.\.\\
II
tOF
tOH
~
Data Out Valid
\
/
(TD.R.HN27C4096H)
HITACHI
Hitachi America. Ltd .• 2000 Sierra Point Pkwy.· Brisbane. CA94005-1819· (415) 589-8300
4-81
HN27C4096H S e r i e s . , . . - - - - - - - - - - - - - - - - - - - - - -
• DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee = 6.25 V ± 0.25 V, Vpp
Item
= 12.5 V ± 0.3 V, Ta = 25 °C ± 5°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
V,N = 6.5 VI 0.45 V
Input Leakage Current
III
Operating Vee Current
Icc
Operating Vpp Current
Ipp
-
Input Voltage
V,H
2.2
V,L
- 0.15
-
VH
11.5
12.0
12.5
V
VOH
2.4
-
V
IOH = -400 I1A
VOL
-
-
0.45
V
IOH = 2.1 mA
3
Output Voltage
Notes:
1.
2.
3.
4.
5.
6.
7.
2
I1A
50
mA
70 7
mA
Vee +·5 6
0.8
V
CE = V,L
V
Vee must be applied before Vpp and removed after Vpp'
Vpp must not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
_
Do not change Vpp from V,L to 12.5 V or 12.5 V to V,L when CE = low.
V, Lmin = -0.6 V for pulse width ~ 20 ns.
If V,H is over the specified maximum value, programming operation can not be guaranteed.
Ipp = 40 mA in Word Programming Mode.
HITACHI
4-82
Hitachi Am~rica, Ltd.• 2000 Si~rra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - HN27C4096H Series
•
AC ELECTRICAL CHARACTERlsncs FOR PROGRAMMING OPERAnONs
(Vee =6.25 V ± 0.25 V, Vpp =12.5 V ± 0.3 V, T. =25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise .and fall times:
• Reference levels for measuring timing:
Item
0.45 V 12.4 V
S20 ns
0.8 V 12.0V
Symbol Min.
Typ.
Max.
Unit
teES
tvps
2
·
Vee Setup Time
"es
2
·
·
·
·
·
·
·
·
~
2
·
·
·
·
·
Output Enable Setup Time
toES
2
~
toF
tpw
·
·
·
0
130
ns
47.5
50.0
52.5
~
Data Valid from Output Enable Time
toE
0
·
150
ns
Chip Enable Pulse Width During Data Latch
tLW
1
·
~
Output Enable = VHSetup Time
·
·
~s
·
~
·
~
·
~
·
~
Address Setup Time
tAS
2
Address Hold Time
tAH
0
Data Setup Time
tos
2
tOH
2
Data Hold Time
Chip Enable Setup Time
Vpp Setup Time
Output Disable Time
Programming Pulse Width
toos
2
·
Output Enable = VHHold Time
toHH
2
Output Enable Hold Time
taeH
2
"RS
1
·
·
·
·
Vpp Hold Time
Page Programming Reset Time
Note:
1.
2.
tVLW
1
Test Condition
~
~
~
~
~s
~
~ is defined as the time at which the output becomes an open circuit and data is no
longer driven.
Page Program Mode will be reset when Vpp is set to Vee or less.
II
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA94005·1819· (415) 589-8300
4-83
HN27C4096H·Serles---------------------...:..--•
PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4096H can be programmed with the high performance Page Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
/~ device or deterioration in reliability of programmed data.
Note:
1.
2.
To set the device into Page Programming, apply 12.5 V to Vpp then followed by applying
12 V to OE. The device operates in Page Program Mode until reset.
To reset the Page Program Mode, set Vpp =Vee or less.
SET PAGE PROG. LATCH MODE
Vpp=12.5±0.3V Vcc =6.25±0.25V
0E=12.0±0.5V
Address + 1 -> Adress
Address + 1 -> Adress
SET PAGE PROGNERIFY MODE
Vpp=12.5±0.3V Vcc=6.25±0.25V
Address + 1 -> Adress
YES
(FC.PP.HN27C4096H)
HITACHI
4-84
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - . . . . , . . . . - - - - - - - - - - - HN27C4096H Series
•
PAGE PROGRAMMING TIMING WAVEFORM
Page Program Mode
. Program Data Latch..
Page Program .•
Program Verify •
A2-A17
AO, A1
Data
Data Out Valid
Vpp
Vpp
Vcc
(TD.PP.HN27C4096H)
HITACHI
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-85
HN27C4096H S e r i e s - - - - - - - - - - - - - - - - - - . . - - - •
WORD PROGRAMMING FLOWCHART
The Hitachi HN27C4096H can be programmed with the high performance Word Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
d~_or deterioration in reliability of programmed data.
SET PROGIVERIFY MODE
Vpp= 12.5±O.3V Vcc=6.25±O.25V
Program
tpw=50~s±5%
Address + 1 ~Address
NOGO
NO
YES
SET READ MODE
Vcc=5.0±O.5V Vpp=Vcc
NOGO
(FC.P.HN27C4096H)
HITACHI
4-86
Hitachi America,
Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4096H series
•
WORD PROGRAMMING TIMING WAVEFORM
Address
-
•
Program
Program Verify
IE
•
.
pC.
X
tAI-1
I~
Data
~
Data In Stable
~
Vpp
VPP
/~
V'~
Vee
V~~+1.2~~
V
Data Out Val d ."-/
to
I'"
...
,tOH,
~vP§
I.tve.
tr;f
~I
~
~E
./
(TD.P.HN27C4096H)
HITACHI
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. eA94005-1819· (415) 589-8300
4-87
-----------
HN27C4096H Series~-------------------•
OPTIONAL PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4096H can be programmed with the high performance Optional Page Programming
algorithm shown in the following flowchart. This algorithm provides a fast programming time without voltage
stress to the device or deterioration in reliability of programmed data.
This programming algorithm is a combination of Page Programming and Word Verify. It can be used to avoid
the increased programming verify time when a programmer with a slower machine cycle is used and shorten
the total programming time.
Please refer to the timing specifications for page programming and word programming.
Address + 1 ---+ Address
(FC.OPP.HN27C4096H)
HITACHI
4-88
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589·8300
- - - - - - - - - - - - - - - - - - - HN27C4096H Series
•
OPTIONAL PAGE PROGRAMMING TIMING WAVEFORM
.
,
'-,
A2-A17
.
Page Program Mode
Word Program Mode
,
Program Data Latch Page Program
t·s
Program Verify
t
~H
"\
,
--'
tAS
ft;lH
f-';;:;
lr
I\--~
,_ .,!QH
AO,A1
-- tAt>
tvps
.~
I- tvps
Vpp
Vpp
LJ
vee
Vee + 1.25
I-
11- ~ tOH
ltiaiaout~
Data In stable
l....JaIIid..
T
tOE to
-
.....
~H tCES
vee
I-
tVRS tVLW
tvcs
vcc
r-
r
It~s
, Data n
'II:
tA~
...J
-t~---r:r..
Data
--
Program
~ES
tOHS
..=..:.+
--.
-th'Y\fV H
I tpw I
---1
~
toES
1-;;;-
A
~
(TD.OPP.HN27C4096H)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
4-89
/
HN27C4096H Serles-----....;..-.......,-------------•
ERASING THE HN27C4096ti
The.Hitachi HN27C4096H is erased by exposure to ultraviolet light of 2537A. All of the data is changed to
"1" after this erasure procedure. The minimum integrated dose (UV intensity x exposure time) for erasure is 15
W-sec/cm2.
'
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device: Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
•
HN27C4096H SERIES IDENTIFIER CODE
Identifier
Aa
Manufacturer Code
V
Device Code
V1H
Notes:
1.
2.
3.
4.
1/°8-1/°,5 1/°7
X
0
X
1
1/06
0
1/°5
0
1/°4
0
0
1
0
1/03
1/0,
0
1/°2
1
0
0
1
1
"°0 Hex Data
1
07
0
Vee =5.0 V ± 10%
Ag= 12.0V±0.5V_
A,-As, A,0-A,7 , CE, OE = V1L
X = Don't Care
HITACHI
4-90
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
A2
Preliminary
HN27C4001 Series
4M (512K x 8-bit) UV and OlP EPROM
•
DESCRIPTION
The Hitachi HN27C4001 is a 4-Megabit Ultraviolet Erasable and
One-Time Programmable Electrically Programmable Read Only
Memory organized as 524,288 x 8-bits.
The HN27C4001 features fast address access times of 100, 120
and 150 ns and low power dissipation. This combination makes the
HN27C4001 suitable for high speed 16 and 32-bit microcomputer
systems. The HN27C4001 offers high speed programming using
page programming mode.
Hitachi's HN27C4001 is offered in JEDEC-Standard Byte-Wide
EPROM pinouts in 32-pin Ceramic DIP. This allows socket
replacement with Mask ROMs and Flash Memory. The HN27C4001
is also available in 32-lead Plastic TSOP packages with both
standard and reverse bend leads.
The Ceramic DIP package is erasable by exposure to Ultraviolet
light. The TSOP packaged device is One-Time Programmable and
once programmed, can not be rewritten.
•
•
FEATURES
• Fast Access Times:
100 ns/120 ns/150 ns (max)
• Single Power Supply:
Vcc =5V±10%
• Low Power Dissipation:
Active Mode:
35 mW/MHz (typ)
Standby Mode:
5 IlW (max)
• High Speed Page and Word Programming:
Page Programming Time: 3.5 sec (min)
• Programming Power Supply:
Vpp = 12.5 V ± 0.3 V
• Pin Arrangement:
JEDEC Standard Byte-Wide EPROM
Mask ROM and Flash Memory Compatible
• Packages:
32-pin Ceramic DIP
32-lead Plastic TSOP (Type II)
(DG-32)
(TTP-32D)
(TTP-32DR)
ORDERING INFORMATION
Access Time
Package
HN27C4001G-10
100 ns
32-pin Ceramic DIP
HN27C4001 G-12
120 ns
(DG-32)
HN27C4001 G-15
150 ns
Type No.
HN27C4001TT-12
120 ns
HN27C4001TT-15
150 ns
(TTP-32D)
HN27C4001 RR-12
120 ns
32-lead Plastic TSOP
HN27C4001 RR-15
150 ns
32-lead Plastic TSOP
(TTP-32DR)
Reverse bend
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-91
HN27C4001 series
•
PIN ARRANGEMENT
HN27C4001 G Series
HN27C4001TT Series
Vpp
A16
A15
A12
A7
A6
AS
A4
A3
4
5
6
7
8
9
A2
A1
AO
1/00
1/01
1/02
Vss
31
30
29
28
27
26
32-PIN '
DIP
25
TOPVIEW 24
23
22
21
20
19
18
17
Vee
Vpp
A18
A17
A14
A13
A8
A9
A11
A16
A15
A12
A7
A6
AS
A4
A3
A2
A1
AD
1/00
OE
A10
CE
1/07
1/06
1/05
1/04
1/03
4
5
6
7
8
9
1/01
1/02
Vss
31
30
29
28
27
STANDARD 26
PINOUT
32-LEAD 25
TSOP
TOPVIEW 24
23
22
21
20
19
18
17
Vee
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
1/07
1/06
1/05
1/04
1/03
(PinT232.HN27C4001T)
(PlriD32.HN27C4001)
HN27C4001 RR Series
Vpp
Vee
•
A18
A17
A14
A13
A8
A9
A11
PIN DESCRIPTION
Pin Name
Function
Ao - Ale
Address
1/00 -1/07
Input/Output
CE
Chip Enable
~
Output Enable
OE
Vee
Power Supply
A10
Vpp
Programming Supply
Vss
Ground
CE
1/07
1/06
1/05
1/04
1/03
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
7
8
9
10
STANDARD
PINOUT
32-LEAD
TSOP
TOPVIEW
A16
A15
A12
A7
A6
AS
A4
A3
A2
A1
AD
1/00
1/01
1/02
Vss
(PinT232,HN27C4001 R)
HITACHI
4-92
Hitachi America. Ltd_· 2000 Sierra Point Pkwy.· Brisbane. eA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4001 Series
•
BLOCK DIAGRAM
XDecoder·
A6-A9 )
A11 -A18
.
4096 x 1024
Memory Matrix
. .......
1/00
S
1/07
S
Input
Data
Control
V-Gating
V-Decoder
CE
~
OE
AO - AS, A10
Vcc
Vpp
High Threshold
Inverter
Vss 0 - - -
•
(BD.HN27C4001 )
MODE SELECTION
Mode
Vpp
Vee
CE
OE
Read
Vss-Vee
Vee
VIL
VIL
Ag
XI
V1H
X
DoUT
High-Z
1/0
Output Disable
Vss-Vee
Vee
VIL
Standby
Vss-Vee
Vee
VIH
X
X
High-Z
V2
H
VH
X
High-Z
X
DIN
High-Z
Page
Page Prog. Set
Vpp
Vee
VIH
Prog.
Page Data Latch
Vpp
Vee
V1L
Page Program
Vpp
Vee
V
VIH
X
Page Prog. Verify
Vpp
Vee
V1H
V
X
Page Prog. Reset
Vee
Vee
V1H
VIH
X
DOUT
High-Z
Word
Program
Vpp
Vee
VIL
V1H
X
DIN
Prog.
Program Verify
Vpp
Vee
VIL
X
001"
Optional Verify
Vpp
Vee
VIH
VIL
VIL
X
DOLI
Program Inhibit
Vpp
Vee
Higt
Vee
VIH
VIL
X
Vss-Vee
VIH
VIL
Identifier
Notes:
1.
2.
VH
10
X = Don't Care. Vpp = 0 V to Vee'
11.5 V :s VH :s 12.5 V
HITACHI
Hitachi America. Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-93
HN27C4001 Series
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Vee
-0.6 to +7.0
V
Programming Voltage 1
Vpp
-0.6 to +13.5
V
VIN.VOUT
VIO
-0.6 to +7.0
V
-0.6 to +13.0
V
Operating Temperature Range
TOPR
o to +70
°C
Storage Temperature Range a
TSTG
-65 to +125 4
-55 to +125 5
°C
Storage Temperature Under Bias
TBIAS
-20 to +80 4
-10 to +80 5
°C
All Input and Output Voltage 1,2
Notes:
1.
2.
3.
4.
5.
Relative to Vss'
VI N' VOUT' and VIO min = -2.0V for pulse width ~ 20 ns.
Device storage temperature range before programming.
HN27C4001 G.
HN27C4001TI and HN27C4001RR.
CAPACITANCE (T. =25°C, f =1MHz)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
CIN
COUT
-
-
12
pF
VIN=OV
20
pF
VOUT= OV
Input Capacitance
Output Capacitance
•
Unit
Supply Voltage 1
As and OE Voltage 2
•
Value
-
DC ELECTRICAL CHA~ACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vpp = Vssto VCC' T. = 0 to 70°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Condition
-
-
2
2
I!A
I!A
VOUT = 5.5 VlO.45 V
30
mA
lOUT = 0 mA, f = 1 MHz
100 3
90 4
mA
mA
lOUT = 0 mA, f = 10 MHz
lOUT = 0 mA, f = 8.4 MHz
-
1
mA
CE=VIH
1
20
CE = Vcc ± 0.3 V
Input Leakage Current
lu
Output Leakage Current
ILO
Operating Vee Currerit
leel
1002
Standby Vee Current
ISBl
-
-
VIN =5.5 V
VppCurrent
Ippl
.1
20
I!A
I!A
Input Voltage
VIH
VIL
2.2
-
Vee + 12
V
-0.3 1
V
2.4
-
V
IOH = -400 I!A
VOl.
-
-
0.8
VOH
0.45
V
101. = 2.1 mA
1882
Output Voltage
Notes:
1.
2.
3.
4.
Vpp =5.5 V
VIL min = -1.0 V for pulse width ~ 50 ns.
VI Lmin = -2.0 V for pulse width ~ 20 ns.
VIH max = Vee + 1.5 V for pulse width ~ 20 ns.
If VIH is over the specified maximum value, Read operation can not be guaranteed.
HN27C4001G.
HN27C4001 TI and HN27C4001 RR.
HITACHI
4-94
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4001 Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(VCC =5V ± 10%. Vpp = Vss to Vcc' T. =0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference levels for measuring timing:
HN27C4001-10
HN27C4001-12
HN27C4001-15
Symbol
Min.
Max.
Min.
Max.
Min.
Address Access Time
tACC
100
tCE
Output Enable Access
Time
toE
60
-
120
Chip Enable Access Time
-
Output Disable to High-Z 1
tOF
0
35
Output Hold to Address
Change
toH
5
-
Item
Note:
•
0.45 V 12.4 V
~ 10 ns
1 TIL Gate + 100 pF (Including scope and jig)
0.8 V/2.0 V
1.
100
Max. Unit
Test
Condition
150
ns
CE
150
ns
60
-
70
ns
=OE = V1L
OE = V1L
CE = V1L
0
40
0
50
ns
CE = V1L
5
-
5
-
ns
CE
120
-
=OE = V1L
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
READ TIMING WAVEFORM
Address
CE
OE
X
Standby Mode
K
1
Active Mode
~CE
\
V
tOE
tACC--==+
Data Out
V Standby Mode
////
\.\\\
tDF
tOH
~
Data Out Valid
\1\
/
(TD.R.HN27C4001 )
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
4-95
HN27C4001 .Series
•
DC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vec = 6.25 V ± 0.25 V, Vpp = 12.5 V ± 0.3 V,T. = 25°C ± 5 0c)
Symbol
Min.
Typ.
Operating Vcc Current
'l
Icc
Operating Vpp Current
Ipp·
-
Input Voltage 3
Item
Input Leakage Current
Output Voltage
Notes:
1.
2.
3.
4.
5.
6.
VIH
2.2
VIL
- 0.15
-
VH
11.5
VOH
2.4
VOL
-
Max.
Unit
Test Condition
2
~
mA
VIN = 6.5 VI 0.45 V
mA
CE = VIL
50
70
Vcc +·5
6
V
0.8
V
12.0
12.5
V
-
-
V
IOH = -400 ~
0.45
V
IOH = 2.1 mA
Vcc must be applied before Vpp and removed after Vpp'
Vppmust not exceed 13 V, including overshoot.
Device reliability may be adversely affected if the device is installed or removed while
Vpp= 12.5 V.
_
Do not change Vpp from VIL to 12.5 V or 12.5 V to VI Lwhen CE = low.
VI L min = -0.6 V for pulse width:;; 20 ns.
If VIH is over the specified maximum value, programming operation can not be guaranteed.
HITACHI
4-96
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - . - - - - - HN27C4001Series
•
AC ELECTRICAL CHARACTERISTICS FOR PROGRAMMING OPERATIONS
(Vee =6.25 V ± 0.25 V, Vpp =12.5 v ± 0.3 V, T. =25°C ± 5°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Reference levels for measuring timing:
Item
0.45 V 12.4 V
20 ns
0.8 V 12.0V
~
Symbol Min.
Typ.
Max.
Unit
-
IlS
130
ns
lyps
2
Vee Setup Time
tves
2
Output Enable Setup Time
toes
2
Output Disable Time
tOF
0
-
Programming Pulse Width
tpw
47.5
50.0
52.5
IlS
Data Valid from Output Enable Time
-
150
ns
-
IlS
Address Setup Time
tAS
2
Address Hold Time
tAH
0
Data Setup Time
tos
2
Data Hold Time
loH
2
Chip Enable Setup Time
teES
2
Vpp Setup Time
tOE
0
Chip Enable Pulse Width During Data Latch
tLW
1
Output Enable =VHSetup Time
taHS
2
tOHH
2
loEH
tvRS
2
lyLW
1
Output Enable =VHHold Time
Output Enable Hold Time
Vpp Hold Time
Page Programming Reset Time
Note:
1.
1
Test Condition
IlS
Ils
IlS
Ils
IlS
IlS
IlS
IlS
IlS
IlS
IlS
IlS
tOF is defined as the time at which the output becomes an open circuit and data is no
longer driven.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
4-97
HN27C4001 Series
•
PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4001 can be programmed with the high performance Page Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time without voltage stress to the
device or deterioration in reliability of programmed data.
Note:
1.
2.
To set the device into Page Programming, apply 12.5 V to Vpp then followed by applying
12 V to OE. The device operates in Page Program Mode until reset.
To reset the Page Program Mode, set Vpp = Vee or less.
SET PAGE PROG. LATCH MODE
Vee = 6.25 ± 0.25 V
OE = 12.0 ± 0.5 V
vpp = 12.5 ± 0.3 v,
NO
Address + 1-> Address
SET PAGE PROGNERIFY MODE
Vpp =12.5±0.3V, Vcc=6.25±0.25V
YES
(FC.PP.HN27C4001)
HITACHI
4-98
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415)589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4001 Series
•
PAGE PROGRAMMING TIMING WAVEFORM
Page Program Mode
• Program Data Latch..
A3-A18
__
Page Program.
Program Verify •
~~~--~---_+-----~-~--------J
AO, A2 ---If-'''-+--f-II'I...-J
Data
Ypp
VPP
tYRS
(TD.PP.HN27C4001 )
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
4-99
HN27C4001Serles
•
BYTE PROGRAMMING FLOWCHART
The Hitachi HN27C4096H can be programmed with the high performance Byte Programming algorithm
shown in the following flowchart. This algorithm provides a fast programming time witho!Jt voltage stress to the
device or deterioration in reliability of programmed data.
SET PROGNERIFY MODE
Vpp= 12.5 ± 0.3V, Vee = 6.25 ± 0.25 V
Program t PW = 50 I.IS ± 5%
Address + 1~ Address
NOGO
NO
YES
SET READ MODE
Vee = 5.0 ± 0.5 V, Vpp= Vee
NOGO
(FC.P.HN27C4001)
HITACHI
4-100
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. eA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN27C4001.Serles
•
BYTE PROGRAMMING TIMING WAVEFORM
Program
Address
Data
=><
=><
•
Vpp
Vr~~
Vee
Vee+1.25
V£L/~
K=
tAH
• tAS •
Vpp
.
Program Verify
Data In Stable
Data Out Valid
tDF
~
tDS
"-
/
tvps
.
tves
CE
'ti
.
toES
OE
~I
'"
~
/
(TD.P.HN27C4001)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
4-101
HN27C4001 Series
•
OPTIONAL PAGE PROGRAMMING FLOWCHART
The Hitachi HN27C4001 can be programmed with the high performance Optional Page Programming
algorithm shown in the following flowchart. This algorithm provides a fast programming time without voltage
stress to the device or deterioration in reliability of programmed data.
This programming algorithm is a combination of Page Programming and Byte Verify. It can be used to avoid
the increased programming verify time when a programmer with a slower machine cycle is used and shorten
the total programming time.
Please refer to the timing specifications for page programming and byte programming.
(FC.OPP.HN27C4001 )
HITACHI
4-102
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
- - - - - - - - - - - - - - - - - - - HN27C4001 Series
•
OPTIONAL PAGE PROGRAMMING TIMING WAVEFORM
Page Program Mode
Program Data Latch Page Program
A3-A18
AO,A2
.
Byte Program Mode
Program
Veri
Program
--~r~-~--------_P---_+~
--+-,'~-+"'I'-.....I
Data
Vpp
Vpp
Vee
(TD.OPP.HN27C4001)
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
4-103
HN27C4001 Series
•
ERASING THE ttN27C4001
The Hitachi HN27C4001 Ceramic DIP package allows the device to be erased by exposure to ultraviolet light
of 2537A. All of the data is changed to "1" after this erasure procedure. The minimum integrated dose (UV
intensity x exposure time) for erasure is 15 W-sec/cm2.
•
DEVICE IDENTIFIER MODE DESCRIPTION
The Device Identifier Mode allows binary codes to be read from the outputs that identify the manufacturer
and the type of device. Using this mode with programming equipment, the device will automatically match its
own erase and programming algorithm.
'
•
HN27C4001 SERIES IDENTIFIER CODE
Identifier
Ao
Manufacturer Code
V
Device Code
V1H
Notes:
1.
2.
3.
4.
1/°7
0
0
1/06
I/O~
1/°4
1/03
0
0
0
0
1
0
1/°1
1
1/00
Hex Data
0
1/°2
1
1
07
0
0
0
0
20
Vcc = 5.0 V ± 10%
Ag = 12.0 V ± 0.5V_
A1-Aa, A10-A18 , CE, OE = V1L
X =Don't Care
•
HN27C4001TT/RR RECOMMENDED SCREENING CONDITIONS
Before mounting the HN27C4001 TT/RR packages, please make the following screening (baking without
bias) shown below:
(RSC.EPROM)
HITACHI
4-104
Hitachi America, Ltd.• 2000 Sierra Point
pkwy;. Brisbane, CA 94005-1819 • (415) 589-8300
NONVOLATILE MEMORY DATA BOOK
Section Five
Mask ROM
HITACHI
HN62321 Series
HN62331 Series
1 M (128K x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62321/HN62331 Series is a 1-Megabit CMOS
Mask Programmable Read Only Memory organized as 131,072 x 8bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high speed
provides enough capacity and high performance to be used as a
character generator in laser printers.
Hitachi's HN62321/HN62331 Series is offered with pinouts in 28pin Plastic DIP and 28-lead Plastic SOP packages.
•
FEATURES
• Single Power Supply:
Vee =5V±10%
• Fast Access Times:
120/150/200 ns (max)
• Low Power Consumption:
Active Current:
100 mW (typ)
Standby Current: 5 IlW (typ)
• Byte-Wide Data Organization
• TIL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Packages:
28-pin Plastic DIP
28-lead Plastic SOP
•
(FP-28DA)
•
•
Access Time
120 ns
150 ns
200ns
120 ns
150 ns
200 ns
PIN ARRANGEMENT
HN62321 1331 P Series
HN62321 BP Series
HN62321/331 F Series
HN62321 BF Series
ORDERING INFORMAnON
Type No.
HN62331P-12
HN62321P-15
HN62321 BP-20
HN62331F-12
HN62321F-15
HN62321 BF-20
(DP-28)
Package
28-pin
Plastic DIP
(DP-28)
28-lead
Plastic SOP
(FP-28DA)
Vee
A15
A12
A7
A6
A5
A4
A3
A14
A13
A8
A9
A11
A16
A10
A2
CE
A1
AO
07
DO
OS
01
02
05
04
03
Vss
PIN DESCRIPTION
Pin Name
Function
Aa - A'6
Address
Do- D7
Output
CE
Chip Enable
Vee
Power Supply
Vss
Ground
(PlnD28.HN62321J331 )
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA9400S-1819· (415) 589·8300
5-1
m
HN62321/HN62331 Series - - - - - - - - - - - - - - - - - - "
•
BLOCK DIAGRAM
AO
3-State
~
Memory
Output
Array
Bufler
DO
~
07
A16
(BD.HN62321/331)
CE
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
-0.3 to +7.0
V
Supply Voltage'
VT
-0.3 to Vee + 0.3
V
Operating Temperature Range
TOPR
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TslAS
-20 to +85
°C
Terminal Voltage'
Notes:
•
1.
With respect to VSS.
CAPACITANCE
(Vee = 5V ± 10%, Vss = OV, T. = 25°C, VIN = 0 V, I = 1MHz)
Symbol
Min.
Max.
Unit
Input Capacitance'
CIN
10
pF
Output Capacitance'
COUT
-
15
pF
Item
Notes:
•
1.
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vss = 0 V, Ta = 0 to 70°C)
Symbol
Min.
Max.
Unit
Test Condition
Input Leakage Current
III
10
ILO
10
IJA
IJA
VIN = 0 to Vee
Output Leakage Current
50
mA
Vcc = 5.5 V, IDOUT = 0 mA, t RC = Min.
Vee = 5.5 V, CE
Item
Standby Vce Current
Iss
-
30
IJA
Input Voltage
VIH
2.2'
Vee +0.3
V
VIL
-0.3
0.8'
V
Output Voltage
VOH
2.4
-
V
IOH = -205
VOL
-
0.4
V
IOL = 3.2 mA
Operating Vee Current
Notes:
1.
lee
CE = 2.2' V,NOUT = 0 to Vee
~
Vce-0.2V
IJA
HN62331 Series is VIH = 2.4 V (min.) and VI L = 0.45V (max.).
HITACHI
5-2
Hitaehi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
HN62321/HN62331 Series
•
AC ELECTRICAL CHARACTERISTICS FOR·READ OPERATION
(Vcc = 5V ± 10%, Vss = 0 V, Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Input/Output Timing Reference level:
HN62321 Series:
HN62331 Series:
0.8 V 12.4 V
0.45 V 12.4 V
S 10 ns
1 TTL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
HN62331
Item
Min.
HN62321
Max.
Min.
HN62321B
Max.
Min.
Max.
Unit
Read Cycle Time
t AC
120
-
150
-
200
-
ns
Address Access Time
tM
-
120
150
-
200
ns
CE Access Time
tACE
-
120
-
150
-
200
ns
Output Hold Time from
Address Change
tOHA
0
-
0
-
0
-
ns
Output Hold Time
from CE
t OHC
0
-
0
-
0
-
ns
CE to Output in High Z
tCHZ
-
60
-
70
-
100
. ns
CE to Output in Low Z
tCLZ
5
-
10
-
10
-
ns
Notes:
•
Symbol
1
tCHZ defines the time at which the output becomes an open circuit and is not referenced to
output voltage levels.
1.
READ TIMING WAVEFORM
Address
'V
,
CE
-
tM
1\
tCHZ
tCLl
HighZ
I-tDHA
I
t ACE
Data Out
K
~
tDHC-
I-
Data Out Valid )
K>¢
HJghZ
(TD.R.HN62321/331 )
Note:
1.
2.
t OHA ' t OHC are determined by the faster time.
tM , tACE are determined by the slower time.
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
5-3
HN62321 E Series
1M (128K x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62321 E Series is a 1-Megabit CMOS Mask
Programmable Read Only Memory organized as 131,072 x 8-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high speed
provides enough capacity and high performance to be used as a
character generator in laser printers.
Hitachi's HN62321 E is offered with pinouts in 28-pin Plastic DIP
and 28-lead Plastic SOP packages.
(DP-28)
•
FEATURES
• Single Power Supply:
Vee =5 V± 10%
• Fast Access Time:
200 ns (max)
• OE Access Time:
100 ns (max)
• Low Power Consumption:
Active Current:
100 mW (typ)
• Byte-Wide Data Organization
• TIL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Packages:
28-pin Plastic DIP
28-lead Plastic SOP
•
(FP-28DA)
•
HN62321 EP Series
HN62321 EF Series
ORDERING INFORMATION
Type No.
HN62321 EP-20
Access Time
200 ns
HN62321 EF-20
200 ns
•
Package
28-pin Plastic
DIP (DP-28)
28-lead Plastic
SOP (FP-28DA)
Function
Ao - Ale
Address
00 - 07
Output
OE
Output Enable
Vee
Power Supply
Vss
Ground
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
DO
01
02
Vss
PIN DESCRIPTION
Pin Name
PIN ARRANGEMENT
2
3
4
5
6
7
8
9
28-PIN
DIP
28-LEAD
SOP
TOP VIEW
(PinD28.HN62321 E)
HITACHI
5-4
Vee
A14
A13
A8
A9
A11
A16
A10
OE
07
06
05
04
03
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN62321E Series
•
BLOCK DIAGRAM
AO
~
Address
Buffer
3-State
Output
Buffer
Memory
Array
A16
DO
~
07
(BD.HN62321 E)
OE
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
VT
-0.3 to +7.0
V
-0.3 to Vec + 0.3
Supply Voltage 1
Terminal Voltage
Operating Temperature Range
TOPR
o to +70
V
DC
Storage Temperature Range
T5TG
-55 to +125
DC
Temperature Under Bias
TB1AS
-20 to +85
DC
Notes:
•
1.
1
With respectto V55'
CAPACITANCE
(Vee =5V ± 10%, Vss =OV, T. =25DC, V1N =0 V, f =1MHz)
Item
Input Capacitance
Output Capacitance
Notes:
•
1.
Symbol
Min.
Max.
Unit
C1N
-
10
pF
15
pF
1
1
COUT
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee =5V ± 10%, Vss =0 V, T. =0 to 70DC)
Symbol
Min.
Max.
Unit
Test Condition
Input Leakage Current
Item
lu
10
V1N =0 to Vee
OUtput Leakage Current
ILO
10
IJA
IJA
50
mA
Vee =5.5 V, looUT =0 mA, tRe= min.
Operating Vee Current
Icc
-
Input Voltage
V1H
2.2
Vee+0.3
V
V1L
-0.3
0.8
V
VOH
2.4
-
V
IOH =-2051JA
VOL
-
0.4
V
IOL =3.2 mA
Output Voltage
OE =2.2V, VOUT =0 to Vee
HITACHI
Hitaehi Ameriea, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
5-5
HN62321E Series - - - - - - - - - - - - - - - - - - - - •
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vss = 0 V, Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Input/Output Timing Reference level:
0.8 V 12.4 V
$10 ns
1 TTL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
Symbol
Min.
Max.
Unit
Read Cycle Time
tAC
200
-
ns
Address Access Time
tM
200
ns
OE Access Time
Item
toE
-
100
ns
Output Hold Time from
Address Change
tOHA
0
-
ns
Output Hold Time
from OE
tOHO
0
-
ns
OE to Output in High Z
tOHZ
-
100
ns
OE to Output in Low Z
tou
10
-
ns
Note:
•
1
10Hz defines the time at which the output becomes an open circuit and is not referenced to
output voltage levels.
1.
READ TIMING WAVEFORM
Address
\1(
\1(
jr\
)~
-
tAA
..,
)
r\
tOHZ
tOE
tOLZ
Data Out
HighZ
-tOHA
tOHO-
(XX)
Data Out Valid
IV\>.
HighZ
IVY
(TD.HN62321 E)
Note:
1.
2.
tOHA ' tpHO are determined by the faster time.
tM , tOE are determined by the slower time.
HITACHI
5-6
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN62321 A Seri·es
HN62331 A Series
1M (128K x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62321 AlHN62331 A Series is a 1-Megabit CMOS
Mask Programmable Read Only Memory organized as 131,072 x 8bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high speed
provides enough capacity and high performance to be used as a
character generator in laser printers.
Hitachi's HN62321 AlHN62331 A Series is offered in
JEDEC-Standard Byte-Wide EPROM pinouts in 32-pin Plastic DIP
and 32-lead Plastic SOP packages. This allows socket replacement
with Flash Memory and EPROMs.
•
FEATURES
• Single Power Supply:
V cc =5V±10%
• Fast Access Times:
120/150 ns (max)
• Low Power Consumption:
100 mW (typ)
Active Current:
Standby Current: 5 IlW (typ)
• Byte-Wide Data Organization
• TIL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Pin Arrangements:
JEDEC Standard Byte-Wide EPROM
Flash and EPROM Compatible
• Packages:
32-pin Plastic DIP
32-lead Plastic SOP
•
(DP-32)
(FP-32D)
•
PIN ARRANGEMENT
HN62321 AP Series
HN62331AP Series
HN62321 AF Series
HN62331AF Series
ORDERING INFORMATION
Access Time
Package
HN62331AP-12
120 ns
32-pin Plastic DIP
HN62321AP-15
150 ns
(DP-32)
HN62331AF-12
120 ns
32-lead Plastic SOP
HN62321 AF-15
150 ns
(FP-32D)
Type No.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA94005-1819' (415) 589-8300
5-7
HN62321A1HN62331A Series - - - - - - - - - - - - - - - - •
•
PIN DESCRIPTION
Pin Name
Function
Ao - A16
Address
Do - 0 7
Output
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
BLOCK DIAGRAM
AO
~
Address
Buffer
Memory
Array
3-8tate
Output
Buffer
DO
~
D7
A16
CE
OE
(BD.HN62321A.331A)
HITACHI
5-8
Hitachi America. Ltd.' 2000 Sierra Point Pkwy.' Brisbane. CA94005-1819' (415)589-8300
- - - - - - - - - - - - - - - - - HN62321A1HN62331A Series
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
-0.3 to +7.0
V
Supply Voltage 1
Terminal Voltage 1
VT
-0.3 to Vee + 0.3
V
TOPR
o to +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TBIAS
-20 to +85
°C
Operating Temperature Range
Notes:
•
1.
With respect to VSS.
CAPACITANCE
(Vee = 5V ± 10%, Vss = OV, T. = 25°C, VIN = 0 V, f = 1MHz)
Item
Symbol
Min.
Max.
Unit
Input Capacitance 1
CIN
10
pF
Output Capacitance 1
COUT
-
15
pF
Notes:
•
1.
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR REAd OPERATION
(Vee = 5V ± 10%, Vss = 0 V, T. = 0 to 70°C)
Item
Symbol
Min.
Max.
Unit
Test Condition
Input Leakage Current
III
IJA
VIN=OtoVee
ILO
-
10
Output Leakage Current
10
IJA
CE = 2.2V, VOUT = 0 to Vee
Operating Vee Current
lee
-
50
mA
Vee = 5.5 V, IDOUT = 0 mA, t Re= Min.
Vee = 5.5 V, CE ~ Vee-0.2V
Standby Vee Current
19B
-
30
IJA
Input Voltage
VIH
2.21
V
VIL
-0.3
Vee +0.3
0.8 1
V
Output Voltage
VOH
2.4
-
V
IOH = -205
VOL
-
0.4
V
IOL = 3.2 mA
Notes:
1.
IJA
HN62331 A Series is VIH = 2.4V (min) and VIL = 0.45V (max).
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
5-9
HN62321A1HN62331A Series - - - - - - - - - - - - - - _ - •
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vss = 0 V, T. = 0 to 70°C)
.
Test Conditions
• Input pulse levels:
• Input rise and fali times:
• Output load:
• InpuVOutput Timing Reference level:
HN62331A Series:
HN62321A Series:
O.S V 12.4 V
0.45 V 12.4 V
S10ns
1 TIL Gate + CL.= 100 pF (Including jig capacitance)
1.5 V
HN62331A
Item
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
tAC
120
-
150
-
ns
Address Access Time
tM
-
120
150
ns
CE Access Time
tACE
120
150 .
ns
60
-
70
ns
OE Access Time
tOE
-
Output Hold Time from
Address Change
tOHA
0
-
0
-
ns
output Hold Time from CE
tOHC
0
0
-
ns
tOHO
-
0
Output Hold Time from OE
-
60
-
70
ns
70
ns
-
10
-
ns
tCHZ
1
OE to Input in High Z
tOHZ
1
CE to Output in Low Z
tCLZ
5
OE to Output in Low Z
tOLZ
5
CE to Input in High Z
Note:
•
HN62321A
Symbol
1.
60
0
10
ns
ns
tCHZ and tOHZ define the time at which the output becomes an open circuit and are not
referenced to output voltage levels.
READ TIMING WAVEFORM
Address
'IV
'M'
I~
/~
,
CE
-
tAA
)
tCHZ
t ACE
tCLZ
tOHC-
OE
/
'E
tOLL
Note:
1.
2.
3.
HighZ
tOHZ
tOE
Data Out
I-- tOHA
tOHO-
00<) V
Data Out Valid
tOHA ' tOHC ' toHo are determined by the faster time.
tM , tACE ' tOE are determined by the slower time.
tCLZ ' taLZ are determined by the slower time.
-
0¢
HighZ
(TD.HN62321A.331A)
HITACHI
5-10
Hitachi America. ltd.' 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1819' (415) 589-8300
HN62412 Series
HN62422 Series
2M (128K x 16-blt) and (256K x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN624121HN62422 Series is a 2-Megabit CMOS
Mask ROM organized as 132,072 x 16-bit and 262,144 x 8-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN624121HN62422 Series is packaged in 40-pin Plastic
DIP and 44-lead Plastic QFP packages.
•
•
(DP-40)
FEATURES
• Single Power Supply:
Vee =5 V ± 10% (HN62412)
Vco = 5 V ±. 5% (HN62422)
• Fast Access Times:
150 nsl200 ns (max)
• Low Power Consumption:
Active Current:
100 mW (typ)
Standby Current: 5 ~W (typ)
• User Selectable Organization:
128K x 16-bit (Word-Wide)
256K x 8-bit (Byte-Wide)
Switchable with BHE pin
• TTL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Packages:
40-pin Plastic DIP
44-lead Plastic QFP
(FP-44A)
ORDERING INFORMATION
Type No.
HN62422P-15
HN62412P-20
HN62422FP-15
HN62412FP-20
Access Time
150 ns
200 ns
150 ns
200 ns
Package
40-pin Plastic DIP
(DP-40)
44-lead Plastic QFP
(FP-44A)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
5-11
HN62412/HN62422 Series - - - - - - - - - - - - - - - - •
PIN DESCRIPTION
Pin Name
•
Function
Ao - A'6
Address
A.,
Address (Word-Wide)
Do - 0'5
CE
Output
Chip Enable
OE
Output Enable
BHE
Byte Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
BLOCK DIAGRAM
AO
it
3-State
Address
Memory
Hexl
Output
Buffer
Array
Byte
Buffer
A16
DO
it
015/(07)
CE
BHE
(A-1 )*
OE
(BD.HN62412,422)
Notes: 1.
2.
*: A., is the Least Significant Address bit in Byte-Wide Mode.
BHE=V,H : 16-bit (0'5 - Do)
BHE=V1L : 8-bit (07 - Do)
When BHE is low, 0'4 - 0 8 are in high impedance states.
HITACHI
5-12
Hitachi America, ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN624121HN62422 Series
•
PIN ARRANGEMENT
HN62412FP Series
HN62422FP Series
HN62412P Series
HN62422P Series
NC
A7
A6
A5
A4
A3
A2
A1
AO
CE
Vss
DE
DO
08
01
09
02
010
03
011
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
10
2
3
4
5
6
7
8
40-PIN
DIP
9
TOP VIEW
10
11
12
13
14
15
16
A4 A5 A6 A7 NC NC A8 A9 A10 A11 A12
A3
A2
A1
AO
CE
NC
Vss
Vss
015/(A-1)
07
014
06
013
05
012
04
21
44-LEAD
OFP
TOP VIEW
DE
00
08
01
09 02 010 03 011 NC Vee 04 012 05 013
Vee
(PinD40.HN62412, 422)
(Pin044.HN62412,422)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
5-13
HN62412/HN62422 Series - - - - - . . ; . - - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
VT
-0.3 to +7.0
V
All Input and Output Voltage 1
-0.3 to Vee + 0.3
V
Operating Temperature Range
TOPR
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TBIAS
-20 to +85
°C
Supply Voltage
Note:
1.
1
Relative to Vss'
• CAPACITANCE
(Vee =5V ± 10%2, VSS =OV, Ta =25°C, VIN =OV, f =1MHz)
Item
Input Capacitance
Symbol
Min.
Typ.
Max.
Unit
CIN
-
-
15
pF
1
Output Capacitance 1
Note:
•
pF
COUl
This parameter is sampled and not 100% tested.
HN62422 Series is 5V ± 5%.
1.
2.
15
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%1, Vss =OV, Ta = 0 to +70°C)
Item
Input Leakage Current
Symbol
Min.
Typ.
Max.
Unit
'l
-
-
10
Output Leakage Current
,LO
Active Current
lee
Standby Current
Input Voltage
ISB
VIH
2.2
VIL
-0.3
Output Voltage
VOH
2.4
Note:
1.
VOL
HN62422 Series is 5V ± 5%.
Test Condition
J.1A
VIN =0 to V ee
10
J.1A
CE =2.2 V, VOUT =0 to Vee
50
mA
Vee =5.5 V, 'ooUT =0 mA, tRe=min
Vee =5.5 V,CE;:: Voo - 0.2V
30
J.1A
Vee +0.3
V
0.8
V
-
V
'OH =-205 J.1A
0.4
V
IOL = 1.6 mA
HITACHI
5-14
HitaehiAmeriea, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN62412/HN62422 Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
. (Vee = 5V ± 10%2, Vss = OV, T. = 0 to +70·C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Input/Output Timing Reference level:
0.45t02.4V
S 10 ns
1 TIL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
HN62412
HN62422
Item
Symbol Min.
Max.
Min.
Max.
Test
Unit
Read Cycle Time
tRC
150
-
200
Address Access Time
tM
150
200
ns
200
ns
100
ns
ns
Chip Enable Access Time
tACE
-
Output Enable Access
Time
~
-
70
-
BHE Access Time
IeHE
-
150
-
200
ns
Output Hold Time from
Address Change
IoHA
0
-
0
-
ns
Output Hold Time from
Chip Enable
tOHC
0
-
0
-
ns
Output Hold Time from
Output Enable
IoHo
0
-
0
-
ns
Output Hold Time from
BHE
Iot.e
0
-
0
-
ns
Chip Enable to Output
in High-Z 1
IeHZ
-
70
-
70
ns
Output Enable to Output
in High-Z 1
~
-
70
-
70
ns
BHEto Output in High-Z 1
IeHz
-
70
70
ns
Chip Enable to Output
in Low-Z
IelZ
10
-
10
-
ns
Output Enable to Output
in Low-Z
lou
10
-
10
-
ns
BHE to Output in Low-Z
leu
10
-
10
-
ns
Note:
1.
2.
150
IeHZ' ~, and IeHz
are defined as the time at which the output becomes
an open circuit and are not referred to output voltage levels.
HN62422 series is 5V± 5%
HITACHI
Hitachi America,
Ltd.· 2000 Sierra Point Pkwy.·
Brisbane, CA94005-1819· (415) 589-8300
5-15
HN62412/HN62422 Series - - - - - - - - - - - - - - - - - •
READ TIMING WAVEFORM
Word Mode (BHE = VIH) or Byte Mode (BHE = VI L)
"V
'\
Address
,~
JI\.
,
CE
-
tAA
I\.
/
tCHZ
t ACE
tCLl
OE
I-tOHA
tOHC-
I/
'\
/
tOHZ
tOE
tOll
HighZ
Data Out
tOHO-
00(>1
Data Out Valid)
-Q¢
HighZ
(TD.R.HN62412,422)
Note: 1.
2.
3.
tOHA ' t OHC ' tOHO are determined by the faster time.
tAA , tAce ' lee are determined by the slower time.
tCLZ ' tOLZ are determined by the slower time.
Word Mode/Byte Mode Switch
HighZ
Data Valid
Data Valid
tBHE
tBHZ
(TD.R1.HN62412,422)
Note:
1.
2.
If CE and OE are enabled, A16 to Ao are valid.
_
_
D1JA-1 pin is in the output state when BHE is High, CE and OE are enabled. Therefore,
the input signals of opposite phase to the output must not be applied to them.
HITACHI
5-16
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN62442B Series - - - - - - -
Preliminary
2M (128K x 16-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62442B is a 2-Megabit CMOS Mask
Programmable Read Only Memory organized as 131,072 x 16-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN62442B is offered with JEDEC-Standard pinouts in
4O-pin Plastic DIP and 4O-lead Plastic SOP packages. The HN62442B
is also packaged in a 44-lead PLCC and a 44-lead Plastic QFP.
•
•
FEATURES
• Single Power Supply:
Vcc =5V±100/0
• High Speed Access Time:
100 ns (max)
.' Low Power Consumption:
Active Current: 150 mW (typ)
Standby Current: 5 jlW (typ)
• Word-Wide Data Organization
• TTL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Pin Arrangements:
JEDEC Standard Word-Wide EPROM Pinout
• Packages:
40-pin Plastic DIP
44-lead PLCC
44-lead Plastic QFP
40-lead Plastic SOP
(FP-44A)
ORDERING INFORMATION
Type No.
HN62442BP-10
Access Time
100 ns
HN62442BCP-10
100 ns
HN62442BFP-10
100 ns
HN62442BFA-10
100 ns
Package
4O-pin Plastic DIP
(DP-40)
44-lead PLCC
(CP-44)
44-lead Plastic QFP
(FP-44A)
40-lead Plastic SOP
(FP-40D)
(FP-40D)
HITACHI
Hitachi America, Ltd. ·2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
5-17
HN62442B Series
•
PIN ARRANGEMENT
HN62442BP Series
HN62442BCP Series
013 014 015 CE NC NC VCC NC A16 A15 A14
NC
CE
015
014
013
012
011
010
09
08
Vss
07
06
05
04
03
02
01
00
OE
11
12
13
14
15
16
17
18
19
20
4O-PIN
DIP
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
NC
A16
A15
A14
A13
A12
A11
A10
A9
Vss
A8
A7
A6
A5
A4
A3
A2
A1
AO
44-LEAD
PLCC
TOP VIEW
03 02 01 00 OE NC AO A1 A2 A3 A4
(PlnD40.HN62442B)
HN62442BFA Series
(PIn044.HN62442B)
HN62442BFP Series
013 014 015 CE NC NC VCC NC A16 A15 A14
NC
CE
015
014
013
012
011
010
D9
08
Vss
07
06
05
04
03
02
01
00
OE
40-PIN
SOP
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
NC
A16
A15
A14
A13
A12
A11
A10
A9
Vss
44-LEAD
QFP
TOP VIEW
AS
A7
A6
A5
A4
A3
A2
A1
AO
03 02 01 DO OE NC AO A 1 A2 A3 A4
(PlnT240.HN62442B)
(Pin044.HN62442B1)
HITACHI
5-18
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN62442B Series
•
•
PIN DESCRIPTION
Pin Name
Function
Ao - A'6
Address
Do - 0'5
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
Output
BLOCK DIAGRAM
AO
~
3-State
Address
Memory
Output
Buffer
Array
Buffer
DO
~
D15
A16
CE
OE
(BD.HN62442B)
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819' (415) 589-8300
5-19
HN62442B8erles - - - - - - - - - - - - - - - - - - - - - - •
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage 1
Item
Vee
-0.3 to +7.0
V
All Input and Output Voltage 1
Vr
-0.3 to Vee + 0.3
V
Operating Temperature Range
TOPR
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
,Temperature Under Bias
TBIAS
-20 to +85
°C
Note:
•
1.
Relative to Vss'
CAPACITANCE
(Vee = 5V ± 10%, Vss = OV, T. = 25°C, VIN = OV, f = 1MHz)
Item
Input Capacitance
Min.
Typ.
CIN
-
-
15
pF
-
15
pF
1
Output Capacitance1
Note:
•
;
Symbol
Max.
Unit
COUT
This parameter is sampled and not 100% tested.
1.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vss = 0 V, T. = 0 to 70°C)
Item
Symbol
Input Leakage Current
IlL
Output Leakage Current
IOL
Operating Vee Current
lee
Standby Vee Current
1581
1582
Input Voltage
Output Voltage
Min.
Typ.
Max.
Unit
Test Condition
-
-
10
j1A
VIN = 0 to Vee
,
-
10
j1A
CE = 2.4V, Vour= 0 to Vee
-
100
mA
Vee = 5.5 V, IDour= OmA, tAC= Min.
30
j1A
Vee = 5.5 V, CE ¢
HighZ
tOHA ' t OHC ' tOHO are determined by the faster time.
tAA , tACE ' tOE are determined by the slower time.
tCLZ ' tOLZ are determined by the slower time.
(TD.R.HN62442B)
HITACHI
5-22
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN623028 Series
2M (256K x a-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62302B is a 2-Megabit CMOS Mask Programmable
ROM organized as 262,144 x 8 bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN62442B is offered with JEDEC-Standard pinouts in
32-pin Plastic DIP and 32-lead Plastic SOP packages.
(DP-32)
•
FEATURES
• Single Power Supply:
Ycc=5V±10%
• Fast Access Times:
170 ns/200 ns (max)
• Low Power Consumption:
Active Current: 100 mW (typ)
Standby Current: 5 IlW (typ)
• Byte-Wide Data Organization
• TIL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Pin Arrangements:
JEDEC Standard Byte-Wide EPROM
• Packages:
32-pin Plastic DIP
32-lead Plastic SOP
(FP-32D)
•
PIN ARRANGEMENT
HN62302BP/BF Series
HN62302BP/BF Series
•
ORDERING INFORMATION
Access Time
Package
NC
HN62302BP-17
170 ns
32-pin Plastic DIP
HN62302BP-20
200 ns
(DP-32)
HN62302BF-17
170 ns
32-lead Plastic SOP
HN62302BF-20
200 ns
(FP-32D)
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
DO
01
02
Vss
Type No.
10
11
12
13
14
15
16
32·PIN
DIP
32·LEAD
SOP
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vec
NC
A17
A14
A13
AS
A9
A11
OE
A10
CE
07
06
05
04
03
(PinD32.HN62302B)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
5-23
II
HN62302B Series
•
BLOCK DIAGRAM
AO
~
3-State
Output
Buffer
Memory
Array
Buffer
DO
~
07
A17
CE
OE
(BD.HN62302B)
•
•
PIN DESCRIPTION
Pin Name
Function
Ao - A17
Address
Do - 0 7
Output
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage 1
Vee
-0.3 to +7.0
V
All Input and Output Voltage 1
VT
-0.3 to Vee + 0.3
V
Operating Temperature Range
TOPA
Oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TBIAS
-20 to +85
°C
Item
Note:
•
1.
Relative to V55'
CAPACITANCE
(Vee'" 5V ± 10%, Vss '" OV, T. '" 25°C, VIN '" OV, f '" 1MHz)
Item
Input Capacitance 1
Output Capacitance 1
Note:
1.
Symbol
Min.
Typ.
Max.
Unit
CIN
-
-
15
pF
-
-
15
pF
COUT
This parameter is sampled and not 100% tested.
HITACHI
5-24
Hitachi America. Ltd.· 2000 Sierra Point Pkwy.· Brisbane. CA 94005-1819· (415) 589-8300
HN62302B Series
•
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vss = OV, T. = 0 to +70°C)
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input Leakage Current
III
10
IlA
IlA
VIN = 0 to Vcc
ILO
Operating Vcc Current
Icc
-
10
Output Leakage Current
-
50
mA
Vcc = 5.5 V, IDoUT = 0 mA, tRc=min.
30
IlA
Vcc = 5.5 V, CE
Vcc +0.3
V
0.8
V
-
V
IOH = -205 IlA
0.4
V
IOL = 1.6 mA
Item
Standby Vcc Current
Input Voltage
Output Voltage
•
Isa
VIH
2.2
VIL
-0.3
VOH
2.4
VOL
-
CE = 2.2 V, VOUT = 0 to Vcc
~
Vee - 0.2V
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = 5V ± 10%, Vss = OV, T. = 0 to +70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Reference level for measuring timing:
0.8/2.4V
~ 10 ns
1 TTL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
HN62302B-17
HN62302B-20
Min.
Max.
Min.
tRc
170
-
200
Address Access Time
tAA
ns
200
ns
Output Enable Access
Time
tOE
70
-
200
tACE
-
170
Chip Enable Access Time
100
ns
Output Hold Time from
Address Change
tOHA
0
-
0
-
ns
Output Hold Time from
Chip Enable
t OHC
0
-
0
-
ns
Output Hold Time from
Output Enable
tOHO
0
-
0
-
ns
Chip Enable to Output
in High-Z 1
tCHZ
-
70
-
70
ns
Output Enable to Output
in High-Z 1
tOHZ
-
70
-
70
ns
Chip Enable to Output
in Low-Z
feLZ
10
-
10
-
ns
Output Enable to Output
in Low-Z
loLZ
10
-
10
-
ns
READ Cycle Time
Note:
1.
170
Max.
Test
Unit
Symbol
Item
ns
tCHZ and tOHZ are defined as the time at which the output becomes
an open circuit and are not referenced to output voltage levels.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
5-25
HN62302B Series - - - - - - - - - - - - - - - - - - - •
READ TIMING WAVEFORM
w
Address
../1\.
-
tM
CE
I
tCHZ
tACE
tCLZ
OE
tOHC-
tOHZ
tOLZ
HighZ
l-
I
I\.
tOE
Data Out
~tOHA
tOHO-
00<) v
Data Out Valid
r~
HighZ
IY
(TD.R.HN62302B)
Note:
1.
2.
3.
toHA' tOHC ' tOHO are determined by the faster time.
tM , tACE , lot: are determined by the slower time.
IeLZ' lou are determined by the slower time.
HITACHI
5-26
Hitachi America, Ltd .• 2600 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
HN62414 Series - - - - - - - - - HN62434 Series
4M (256K x 16-bit) and (512K x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62414/HN62434 Series is a 16-Megabit CMOS
Mask Programmable Read Only Memory organized as 262,144 x
16-bit and 524,288 x 8-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN62414/HN62434 Series is offered with
JEDEC-Standard pinouts in 40-pin Plastic DIP and 4O-lead Plastic
SOP packages as we" as 44-lead Plastic QFP and TQFP, 48-lead
Plastic SOP and 64-lead Plastic QFP packages.
•
FEATURES
• Single Power Supply:
Vcc =5V±10%
• Fast Access Times:
150 ns/170 ns/200 ns (max)
• Low Power Consumption:
Active Current:
100 mW (typ)
Standby Current: 5 JlW (typ)
• User Selectable Organization:
256K x 16-bit (Word-Wide)
512K x 8-bit (Byte-Wide)
Switchable with BHE pin
• TTL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Pin Arrangements:
JEDEC Standard
• Packages:
40-pin Plastic DIP
40-lead Plastic SOP
44-lead Plastic QFP
44-lead Plastic TQFP
48-lead Plastic SOP
64-lead Plastic QFP
(DP-40)
(FP-40D)
(FP-44A)
(TFP-44)
(FP-48DA
(FP-64B)
HITACHI
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.' Brisbane. CA 94005-1 't19 • (415) 589-8300
5-27
HN62414/HN62434 Series - - - - - - - - - - - - - - - - - •
ORDERING INFORMATION
Type No.
Access Time
Package
150 ns
40-pin Plastic
HN62434/414P-17
170 ns
DIP (OP-40)
HN62434/414P-20
200 ns
HN62434/414FA-15
150 ns
40-lead Plastic
HN62434/414FA-17
170 ns
SOP (FP-400)
HN62434/414FA-20
200 ns
HN62434/414FP-15
150 ns
44-lead Plastic
HN62434/414FP-17
170 ns
QFP (FP-44A)
HN62434/414FP-20
200 ns
HN62434/414TFP-15
150 ns
44-lead Plastic
HN62434/414TFP-17
170 ns
TQFP (TFP-44)
HN62434/414TFP-20
200 ns
HN62434/414P-15
HN62434/414F-15
150 ns
48-lead Plastic
HN62434/414F-17
170 ns
SOP (FP-480A)
HN62434/414F-20
200 ns
HN62434/414FS-15
150 ns
64-lead Plastic
HN62434/414FS-17
170 ns
QFP (FP-64S)
HN62434/414FS-20
200 ns
•
PIN ARRANGEMENT
HN62414/434P Series
A17
A7
A6
A5
A4
A3
A2
A1
AO
CE
Vss
OE
DO
08
01
09
02
010
03
011
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40·PIN
DIP
TOP VIEW
HN62414/434FA Series
31
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
SHE
A17
A7
A6
A5
A4
A3
A2
A1
AO
CE
Vss
015/A-1
07
014
06
013
05
012
04
Vss
OE
DO
08
01
09
02
010
03
011
Vce
(PinD40.HN62414.434)
40·LEAD
sOP
TOP VIEW
13
14
15
16
17
18
19
20
A8
A9
A10
A11
A12
A13
A14
A15
A16
SHE
Vss
015/A-1
07
014
06
013
05
012
04
Vee
(PinT240.HN62414.434)
HITACHI
5-28
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - HN62414/HN62434 Series
•
PIN ARRANGEMENT (conI.)
HN62414/434F Series
NC
A17
A7
A6
A5
A4
A3
A2
Al
AO
NC
NC
NC
CE
Vss
OE
DO
08
01
09
02
010
03
011
NC
A8
A9
Al0
All
A12
A13
A14
A15
A16
NC
NC
NC
BHE
Vss
015/A-l
07
014
06
013
05
012
04
Vcc
46
45
44
43
42
41
40
39
48-LEAD 38
SOP
37
TOPVIEW 36
35
34
33
32
31
30
29
28
27
26
25
Note:
Pins 11,12,13,36,37,
and 38 are connected
to the inner lead frame.
•
PIN DESCRIPTION
Pin Name
Function
Ao - A'7
Address
A.,
. Address (Word-Wide)
Do - 0'5
Output
CE
Chip Enable
OE
Output Enable
BHE
Byte Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
(PinT248.HN62414,434)
HN62414/434FPrrFP Series
""'Ii)CO""~UCX)O)~:::~
c(c(c(c(c(zc(c(c(c(c(
A3
~~~~~~~~~~~
1
33
32
31
30
29
28
27
26
25
24
23
A2
A1
AO
44-LEAD
QFPand TQFP
TOP VIEW
CE
NC
Vss
OE
DO
08
01
10
11
C\I C') "'"
Ii)
co ,...
CX)
0)
0
...-
A13
A14
A15
A16
BHE
NC
Vss
015/A-1
07
014
06
C\I
~~,.....-,.....-,...,.....C\lC\lN
(Pin044.HN62414,434)
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.' Brisbane, CA 94005-.1819' (415) 589-8300
5-29
HN62414/HN62434 Series - - - - - - - - - - - - - - - - - - •
PIN ARRANGEMENT (cont.)
HN62414/434FS Series
()LOCEiCEi
(PIn044.HN62415)
HITACHI
5-36
Hitachi America,
Ltd.• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
L'_ ., _ .:.
~":.
•..
_._~,-,-,-"-, ,--"--,..>...¢
HighZ
(TD.R.HN62344B)
Note:
1.
2.
3.
t OHA ' tOHC ' tOHO are determined by the faster time.
tM , tACE ' tOE are determined by the slower time.
tCLZ ' tOLZ are determined by the slower time.
HITACHI
5-68
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN62418 Series - - - - - - - - - 8M (512K x 16-blt) and (1 M x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62418 Series is an 8-Megabit CMOS Mask
Programmable Read Only Memory organized either as 524,288 x
16-bit or as 1,048,576 x 8-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN62418 is offered with JEDEC-Standard pinouts in
42-pin Plastic 01 P and 44-lead Plastic QFP packages. The HN62418
is also packaged in a 44-lead TQFP, a 44-lead PLastic SOP, a 48lead PLastic SOP and a 64-lead Plastic QFP .
•
(DP-42)
FEATURES
• Single Power Supply
Vcc =5V±100/0
• Fast Access Time:
150 ns (max)
• Low Power Consumption:
100 mW (typ)
Active Current:
Standby Current: 5 JlW (typ)
• User Selectable Organization:
1M x 16-bit (Word-Wide)
2M x 8-bit (Byte-Wide)
Switchable with BHE pin
• TIL-Compatible Inputs and Outputs
• Three-State Data Outputs
.
• Pin Arrangements:
JEDEC Standard Word-Wide/Byte-Wide Pinout
• Packages:
42-pin Plastic DIP
44-lead Plastic OFP
44-lead TOFP
44-lead Plastic SOP
48-lead Plastic SOP
64-lead PLastic OFP
(FP-44A)
(TFP-44)
(FP-44D)
(FP-48DA)
(FP-64B)
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005-1819· (415) 589-8300
5-69
HN62418 Series ----.;~---------------.;---------•
ORDERING INFORMATION
Type No.
HN62418P-15
•
•
Access Time
150 ns
HN62418FP-15
150 ns
HN62418TFP-15
150 ns
HN62418FB-15
150 ns
HN62418F-15
150 ns
HN62418FS-15
150 ns
Package'
42-pin Plastic DIP
(oP-42)
44-lead PlasticQFP
(FP-44A)
44-lead TQFP
(TFP-44)
44-le.ad Plastic SOP
(FP-44o)
48-lead Plastic SOP
(FP-48oA)
64-lead Plastic QFP
(QFP-64)
PIN DESCRIPTION
Pin Name
Function
Ao - Ale
Address
A.l
Address (Word-Wide)
Do -015
Output
CE
Chip Enable
OE
Output Enable
BHE
Byte Enable
Vee
Power Supply
Vss
NC
Ground
No Connection
BLOCK DIAGRAM
00
Address
Buffer
~
Memory
Array
0151(07)
'A18
CE
BHE
(A'1) 1
- - - - - I ::X>-+----:-'
Oe
Notes:
1.
2.
(BD.HN62418)
• : A.l is the Least Significant Add{eSsbit in Byte-Wide Mode.
BHE=V,H : 16-bit (ola - Do> .
.
BHE=V1L : 8-bit (07 -Do)
.
When BHE is low, 0 14 - o&~re ii'! hiph impedance states.
HITACHI
5-70
HitachiAmerica, Ltd. 2000 Sierra POint PJ0C;0C;
(PInQ44.HN62418)
HN62418FS Series
o
Z
,...co
........
0
0
....
~co""
O
~~ ........
O
ctc(c(c(zz
c(c(z
NC
A12
A13
A14
A15
A16
NC
BHE
NC
NC
NC
A4
A3
A2
A1
NC
AO
CE
NC
NC
NC
64-LEAD
OFP
TOP VIEW
Vss
Vss
0151A·1
NC
07
014
NC
06
013
Vss
OE
NC
DO
08
NC
01
09
N O I0 0
o o(')""082!j c;zoz
zOzC;0C;z:;>
ON
(PlnQ64.HN62418)
HITACHI
5-72
Hitachi America,
Ltd .• 2000 Sierra Point Pkwy.·
Brisbane, CA 94005·1819 • (415) 589·83Ooooo
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
-0.3 to +7.0
V
Supply Voltage 1
All Input and Output Voltage
VT
-0.3 to Vee + 0.3
V
TOPA
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TelAs
-20 to +85
°C
1
Operating Temperature Range
Notes:
•
(Pin044.HN62428)
1.
With respect to VSS •
CAPACITANCE
(Vee = 5V ± 10%, Vss =OV, T. =25°C, VIN = 0 V, f = 1MHz)
Item
Input Capacitance
1
Output Capacitance
Notes:
1.
1
Symbol
Min.
Max.
Unit
CIN
-
15
pF
15
pF
COUT
This parameter is sampled and not 100% tested.
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819 • (415) 589-8300
5-79
HN62428 Series
•
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vss =0 V, Ta =0 to 70°C)
Item
Symbol
Min.
Max.
Unit
10
j.tA
VIN
10
j.tA
CE = 2.2V, Your
Vee
Input Leakage Current
III
Output Leakage Current
ILO
Operating Vee Current
lee
-
50
mA
19B
-
30
j.tA
VIH
2.2
Vcc +0.3
V
VIL
-0.3
0.8
V
VOH
2.4
-
V
VOL
-
0.4
V
Standby Vec Current
Input Voltage
Output Voltage
•
Test Condition
=0 to Vee
=0 to Vee
IDOur =0 mA, tRe = Min.
= 5.5 V,
Vcc =5.5 V, CE;;:: Vcc-0.2V
= -205 j.tA
IOL = 1.6 mA
IOH
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc =5V ± 10%, Vss =0 V, Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• InpuVOutput Timing Reference level:
0.8 V 12.4 V
:510 ns
1 TIL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
HN62428-15
Item
Symbol
Min.
HN62428-20
Max.
Min.
Max.
Unit
tRC
150
-
200
-
ns
Address Access Time
tAA
150
200
ns
CE Access Time
tACE
200
ns
OE Access Time
tOE
70
ns
150
-
200
ns
Read Cycle Time
BHE Access Time
tBHE
-
Output Hold Time from
Address Change
tOHA
0
-
0
-
ns
Output Hold Time
from CE
tOHC
0
-
0
-
ns
Output Hold Time
from OE
t OHO
0
-
0
-
ns
Output Hold Time
from BHE
tOHB
0
-
0
-
ns
CE to Output in High Z
tCHZ
-
70
70
ns
70
ns
70
-
70
ns
-
ns
OE to Output in High Z
10Hz
BHE to Output in High Z
t8HZ
CE to Output in Low Z
1
1
1
150
70
70
tCLZ
10
-
10
OE to Output in Low Z
~
10
-
10
BHE to Output in Low Z
tBLZ
10
-
10
Note:
1.
ns
ns
teHz ' toHZ ' and taHZ define the time at which the output becomes an open circuit and are not
referenced to output voltage levels.
HITACHI
5-80
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - - HN62428 Series
•
READ TIMING WAVEFORM
Word Mode (BHE V'H) or Byte Mode (BHE
=
=V'L)
'I'
"
Address
-
tM
CE
-tOHA
)
tCHZ
tACE
tClZ
tOHC-
'l
OE
tOHZ
tOE
toLZ
'HighZ
Data Out
--
O<)¢/
tOHO-
r-
Data Valid
~
HighZ
(TD.R.HN62428)
Note:
1.
2.
3.
tOHA ' tOHC ' tOHO are determined by the faster time.
tM , tACE ' tOE are determined by the slower time.
tCL2 ' loL2 are determined by the slower time.
Word Mode/Byte Mode Switch
H;ghZ
~._ _ _ _ _ _~
HighZ
I· "·I.'!!.~
BHE
Data Valid
High Z
tBHE
tBHZ
Note:
1.
2.
Data Valid
(TD.R1.HN82428)
CE and OE are of select status. A'8 to A. are fixed:....
_
D,JA., terminal is of output state when BHE =V'H' CE and OE are of selected state. At
this time, an input signal that is of the inverse phase to the output should not be
impressed.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
5-81
HN62438N Series--------- Preliminary
aM (512K x 16-bit) and (1M x a-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62438N Series is an 8-Megabit CMOS Mask
Programmable Read Only Memory organized either as 524,288 x
16-bit or as 1,048,576 x 8-bit.
The high density and high speed Nibble Access provide enough
capacity and high performance to be used in a system using a high
speed 16-bit or 32-bit microcomputer. In addition the low power
consumption of this device makes it ideal for battery powered,
portable systems.
Hitachi's HN62438N is offered with JEDEC-Standard pinouts in
42-pin Plastic DIP and 44-lead Plastic SOP packages. The HN62438N
is also packaged in a 44-lead Plastic TSOP and a 48-lead Plastic
SOP.
•
FEATURES
• Single Power Supply
Vcc =5V±100/0
• Fast Access Times:
120 ns/150 ns (max)
• Nibble Access Times:
60 ns/70 ns (max)
• Low Power Consumption:
100 mW (typ)
Active Current:
Standby Current: 5 IlW (typ)
• User Selectable Organization:
512K x 16-bit (Word-Wide)
1M x 8-bit (Byte-Wide)
Switchable with BHE pin
• TIL-Compatible Inputs arid Outputs
• Three-State Data Outputs
• Pin Arrangements:
JEDEC Standard Word-Wide/Byte-Wide Pinout
• Packages:
42-pin Plastic DIP
44-lead Plastic SOP
44-lead Plastic TSOP (Type II)
48-lead Plastic SOP
•
(DP-42)
(FP-44D)
ORDERING INFORMATION
Type No.
Access Time
Package
HN62438PN-12
120 ns
42-pin Plastic DIP
HN62438PN-15
150 ns
(DP-42)
HN62438FBN-12
120 ns
44-lead Plastic SOP
HN62438FBN-15
150 ns
(FP-44D)
HN62438TTN-12
120 ns
44-lead Plastic TSOP
HN62438TIN-15
150 ns
(TIP-44D)
HN62438FN-12
120 ns
48-lead Plastic SOP
HN62438FN-15
150 ns
(FP-48DA)
HITACHI
5-82
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819· (415) 589-8300
HN62438N Series
•
•
PIN DESCRIPTION
Pin Name
Function
Au - AlB
Address
A.l
Address (Word-Wide)
Do - 0 15
Output
CE
Chip Enable
OE
Output Enable
BHE
Byte Enable
Vee
Power Supply
Vss
NC
Ground
No Connection
BLOCK DIAGRAM
AO
A1
A2
~
Address
Buffer
Memory
Array
Nibble
Decoder
Hex!
Byte
3-State
Output
Buffe~)
DO
~
015
1(07)
A18
Ce
BHE
(A-1)·
OE
(8D.HN82438N)
Notes:
1.
2.
• : A'1 Is the Least Significant Address bit In Byte-Wide Mode.
BHE-VIH : 16-blt (015 - Do)
BHE-VIL : 8-blt (07 • Do)
When BHE Is low, 0 14 • 0, are In high Impedance states.
HITACHI
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA94005·1819· (415) 589·8300
5·83
HN62438N Series
•
PIN ARRANGEMENT
HN62438PN Series
A18
A17
A7
A6
42
41
40
39
38
37
36
35
AS
A4
A3
A2
A1
AO
CE
HN62438FBN Series
HN62438TTN Series
42-PIN
DIP
TOP VIEW
V~
OE
DO
08
01
09
02
010
03
011
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
A8
A9
A10
A11 '
A12
A13
A14
A15
A16
BHE
Vss
015/A-1
07
014
06
013
05
012
04
Vee
NC
A18
A17
A7
A6
AS
A4
44-LEAD
SOP
44-LEAD
TSOP
TOP VIEW
A3
A2
A1
AO
CE
Vss
OE
DO
08
01
09
02
010
03
011
34
33
32
31
30
29
28
27
26
25
24
23
(PinD42.HN62438N)
HN62438FN Series
NC
AS
A2
Note:
Pins 11,12, 13,36,37
,and 38 are connected
to the inner lead frame.
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
Vss
015/A-1
07
014
06
013
05
012
04
Vee
(PlnD44.HN62438N)
A18
A17
A7
A6
A5
A4
A3
A1
AO
NC
NC
NC
CE
Vss
OE
DO
08
01
09
02
010
03
011
44
43
42
41
40
39
38
37
36
35
48-LEAD
SOP
TOP VIEW
A9
A10
A11
A12
A13
A14
A15
A16
NC
NC
NC
BHE
Vss
015/A-1
07
014
06
013
05
012
04
Vee
(PlnT248.HN62438N)
5-84
HITACHI
Hitachi America, Ltd.· 20()O Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HN62438N Series
•
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Value
Unit
Vee
VT
-0.3 to +7.0
V
1
All Input and Output Voltage
1
Operating Temperature Range
°C
TOPR
TSTG
-55 to +125
°C
Temperature Under Bias
TBIAS
-20 to +85
°C
1.
With respect to VsS'
CAPACITANCE
(Vee = 5V ± 10%, Vss = OV, T. =25°C, VIN = 0 V, f = 1MHz)
Item
Input Capacitance
Notes:
1.
Symbol
Min.
Max.
Unit
CIN
-
15
pF
15
pF
1
Output Capacitance
•
V
oto +70
Storage Temperature Range
Notes:
•
-0.3 to Vee + 0.3
1
COUT
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee = 5V ± 10%, Vss = 0 V, T. = 0 to 70°C)
Item
Input Leakage Current
Output Leakage Current
Operating Vee Current
Standby Vee Current
Input Volta.Qe
Output Voltage
Symbol
Min.
Max.
Unit
Test Condition
ILl
ILO
-
10
VIN = 0 to Vee
10
!LA
!LA
CE = 2.~V, VOUT = 0 to Vee
50
mA
Vee = 5.5 V, looUT = 0 mA, tRe = Min.
ISB
VIH
-
30
!LA
Vee = 5.5 V, CE;?: Vee-0.2V
2.4
Vee +0.3
V
VIL
-0.3
0.45
V
VOH
2.4
-
V
VOL
-
0.4
V
lee
=-205 !LA
IOL =1.6 mA
IOH
HITACHI
Hitachi America, Ltd.• 2000 Sierra Polnl Pkwy.' Brisbane, CA 94005-1819 • (415) 589-8300
5-85
HN62438N Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc =5V ± 10%, Vss = 0 V, T. =0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Input/Output Timing Reference level:
0.8 V 12.4 V
$10 ns
1 TIL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
.
HN62438N-12
HN62438N·15
Symbol
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
tRC
120
120
tNC
60
-
ns
Nibble Read Cycle Time
-
Address Access Time
tM
-
120
-
150
ns
70
ns
120
150
ns
70
ns
120
-
150
ns
Item
Nibble Address Access
Time
tNA
CE Access Time
tACE
OE Access Time
tOE
60
70
ns
BHE Access Time
tBHE
-
Output Hold Time from
Address Change
tOHA
0
-
0
-
ns
Output Hold Time
from CE
tOHC
0
-
0
-
ns
Output Hold Time
from OE
tOHO
0
-
0
-
ns
Output Hold Time
from BHE
tOHB
0
-
0
-
ns
CE to Output in High Z
tCHZ
1
-
70
ns
tOHZ
-
60
1
60
-
70
ns
BHE to Output in High Z
tBHZ
1
-
60
-
70
ns
CE to Output in Low Z
-
ns
OE to Output in High Z
60
tCLZ
10
-
10
OE to Output in Low Z
tOLZ
10
10
BHE to Output in Low Z
tBLZ
10
-
Note:
1.
10
ns
ns
tCHZ ' taHZ' and t8HZ define the time at which the output becomes an open circuit and are not
referenced to output voltage levels.
HITACHI
5-86
Hitachi America, Ltd.· 2000 Sierra POint Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
- - - - - - - - - - - - - - - - - - - - HN62438N Series
•
READ nMING WAVEFORM
Word Mode (BHE = VIII) or Byte Mode (BHE = VI L)
"
Address
j
j\,
"
CE
-
tAA
-tOHA
~
tCHZ
tACE
tCLZ
-
tOHC-
~'{
OE
tOliZ
tOE
tOLZ
HighZ
Data Out
-(>¢
tOHO-
OOOL/
Data Valid
HighZ
(TD.R.HN62438N)
Note:
tOHA ' toHC' tOtlO are determined by the faster time.
tAA • tACE • toe are determined by the slower time.
leu. fotz are determined by the slower time.
1.
2.
3.
Word Mode/Byte Mode Switch
H;ghZ~_ _ _~
•
'I\.
SHE
8
M
.
HighZ
,OH'1
/-E
r-"\..Axxxxxxxxx
I/'
.
I-/~~~ Data Valid
~OH.
x
/'Xy
AX'
xx
xxx 1/
~I' Data Valid
•
teHE
HighZ
•
')0
Data Valid
1teHE
Note:
1.
2.
(TO.Rl.HN62438N)
CE and OE are of select status. AlB to Ao are fixed:.._
D,iA., terminal is of output state when SHE = VIH • CE and OE are of selected state. At
this time, an input signal that is of the inverse phase to the output should not be
impressed.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane,CA94005-1819' (415) 589-8300
5-87
HN62438N Series
Nibble Mode
Data Out
(TD.RN.HN62438N)
Note:
CE and OE are enable.
HITACHI
5-88
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
HN623188 S e r i e s - - - - - - - - 8M (1 M x 8-bit) Mask ROM
•
DESCRIPTION
The Hitachi HN62318B Series is an 8-Megabit CMOS Mask
Programmable Read Only Memory organized as 1,048,576 x 8-bit.
The low power consumption of this device makes it ideal for
battery powered, portable systems. In addition, the high density and
high speed provide enough capacity and high performance to be
used as a character generator in laser printers.
Hitachi's HN62318B is packaged in 32-pin Plastic DIP and 32lead Plastic SOP packages.
•
•
•
(DP-32)
FEATURES
• Single Power Supply:
Vcc =5V±10%
• Fast Access Time:
150 ns (max)
• Low Power Consumption:
Active Current:
100 mW (typ)
Standby Current: 5 JlW (typ)
• Byte-Wide Data Organization
• TTL-Compatible Inputs and Outputs
• Three-State Data Outputs
• Packages:
32-pin Plastic DIP
32-lead Plastic SOP
(FP-32D)
•
PIN ARRANGEMENT
HN62318BP Series
HN62318BF Series
ORDERING INFORMATION
Type No.
HN62318BP-15
Access Time
150 ns
HN62318BF-15
150 ns
Package
32-pin Plastic
DIP (DP-32)
32-lead Plastic
SOP (FP-32D)
PIN DESCRIPTION
Pin Name
Function
Ao - A'9
Address
Do - 0 7
Input/Output
CE
Chip Enable
OE
Output Enable
Vee
Power Supply
Vss
NC
Ground
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
DO
01
02
Vss
Vcc
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
07
06
05
04
03
(PinD32.HN62318B)
No Connection
HITACHI
Hitachi America. Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
5-89
HN62318BSeries - - - - - - . . . , . - - - - - - - - - - - - - - - - •
BLOCK DIAGRAM
AO
DO
!;
!;
A19
07
CE
(BD.HN62318B)
OE
•
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Value
Unit
Vee
VT
-0.3 to +7.0
V
1
Terminal Voltage
1
Operating Temperature Range
Storage Temperature Range
TOPA
TsTa
Temperature Under Bias
TelAs
Notes:
•
1.
V
oto +70
°C
-55 to +125
°C
-20 to +85
°C
With respect to Vss'
CAPACITANCE
(Vee =5V ± 10%, Vss =OV, T. =25°C, VIN =0 V, f =1MHz)
Item
Symbol
Min.
Max.
Unit
C1N
COUT
-
15
pF
-
15
pF
Input Capacitance 1
Output Capacitance 1
Notes:
•
-0.3 to Vee + 0.3
1.
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vec '" 5V ± 10%, Vss '" 0 V, T•• 0 to 70°C)
Item
Symbol Min.
Max.
Unit Test Condition
Input LBakage Current
IlL
-
10
~
10
~
mA
VIN • Oto Vec
CE 2.2V, VOUT • 0 to Vee
Output Leakage Current
IOL
Operating Vce Current
lee
Standby Vcc Current
ISB
VIH
VIL
-0.3
Vec +0.3
0.8
VOH
2.4
-
V
IOH- -20511A
VOL
-
0.4
V
IOL .1.6 mA
Input Voltage
...
Output Voltage
2.2
50
30
~
V
OIl
Vee· 5.5 V,l ooUT ~ 0 mA, tRC • Min.
Vee '" 5.5 V, CE ~ Vce-0.2V
V
HITACHI
5..90
Hitachi America, Ltd.• 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 • (415) 589·8300
- - - - - - - - - - - - - - - - - - - - - - - - HN62318B Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc =5V ± 10%, Vss = 0 V, T. =0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• Input/Output Timing Reference level:
Item
Min.
ns
1 TIL Gate + CL = 100 pF (Including jig capacitance)
1.5 V
~10
Max.
Unit
Read Cycle Time
tRC
150
-
ns
Address Access Time
tM
150
ns
CE Access Time
tAcE
-
150
ns
OE Access Time
tOE
-
70
ns
Output Hold Time from
Address Change
tOHA
0
-
ns
Output Hold Time
from CE
tOHC
0
-
ns
Output Hold Time
from OE
tOHO
0
-
ns
CE to Output in High Z
tCHZ
1
ns
tOHZ
1
-
70
OE to Output in High Z
70
ns
CE to Output in Low Z
lcL2
tou
10
-
ns
OE to Output in Low Z
Note:
•
Symbol
0.8 V /2.4 V
1.
10
ns
tCHZ ' and tOHZ define the time at which the output becomes an open circuit and are not
referenced to output voltage levels.
READ TIMING WAVEFORM
I
Address
-
tM
CE
I
tCHZ
t ACE
,
OE
tCLZ
tOHC-
--
1\
tOHZ
tOE
toLZ
Data Out
-toHA
~
HighZ
tOHO-
JO
EOE
(Pln044.HN624017)
HITACHI
5-96
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300
- - - - - - - - - - - - - - - - - - - - - - - - HN624017 Series
•
PIN ARRANGEMENT (cont.)
•
HN624017F Series
A18
A17
A7
A6
A5
A4
A3
A2
A1
AO
NC
NC
NC
CE
Vss
OE
DO
OS
01
09
02
010
03
011
48
47
46
45
44
43
42
41
40
39
38
48-LEAD 37
SOP
36
TOPVIEW 35
34
33
32
31
30
29
28
27
26
25
PIN DESCRIPTION
Pin Name
Function
Ao - AI9
Address
A.I
Address (Word-Wide)
Do - 0 15
Output
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
NC
NC
BHE
Vss
0151A-1
07
014
06
013
05
012
04
Vee
CE
Chip Enable
OE
Output Enable
BHE
Byte Enable
Vee
Power Supply
Vss
Ground
NC
No Connection
(PlnT248.HN624017)
Note: Pins 11, 12, 13, 36, 37 and 38 are
connected to the inner lead frame.
•
BLOCK DIAGRAM
AO
~
Address
Buffer
Memory
Array
Hex!
Byte
3-State
OutPut
Buffer
DO
~
015/(07)
A19
CE
BHE
(A-1) 1
OE
Notes:
1.
2.
(BD.HN624017)
* : A.I is the Least Significant Address bit in Byte-Wide Mode.
BHE=V,H : 16-bit (0 15 - OJ
BHE=V1L : 8-bit (07 - OJ
When BHE is low, 0 14 - De are in high impedance states.
HITACHI
Hitachi America, Ltd .• 2000 Sierra Point Pkwy. • Brisbane; CA 94005-1819· (415) 589-8300
5-97
HN624017 Series --------------~----•
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Vee
VT
-0.3 to +7.0
V
-0.3 to Vee + 0.3
V
TOPR
oto +70
°C
Storage Temperature Range
TSTG
-55 to +125
°C
Temperature Under Bias
TBIAS
-20 to +85
°C
Item
Supply Voltage
1
Terminal Voltage
1
Operating Temperature Range
Notes:
•
1.
With respect to VSS.
CAPACITANCE
(Vee = 5V ± 10%, Vss =OV, T.:; 25°C, VIN =0 V, f = 1MHz)
Item
Symbol
Min.
Max.
Unit
CIN
-
15
pF
15
pF
Input Capacitance 1
Output Capacitance
Notes:
•
1.
1
COUT
This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vee =5V ± 10%, Vss = 0 V, T. =0 to 70°C)
Item
Symbol
Min.
Max.
Unit
Test Condition
10
10
!lA
!lA
50
mA
=0 to Vee
CE =2.2V, VOUT = 0 to Vee
Vee =5.5 V, IOOUT =0 mA, tRe= min.
Vee =5.5 V, CE ~ Vee-0.2V
Standby Vee Current
ISB
-
30
!lA
Input Voltage
VIH
2.2
Vee +0.3
V
VIL
-0.3
0.8
V
Output Voltage
VOH
2.4
-
V
IOH
VOL
-
0.4
V
IOL = 1.6 mA
Input Leakage Current
ILl
Output Leakage Current
ILo
Operating Vee Current
lee
VIN
=-205 !lA
HITACHI
5-98
Hitachi America, Ltd.· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300
HN624017 Series
•
AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(Vcc = SV ± 10%, Vss = 0 V, Ta = 0 to 70°C)
Test Conditions
• Input pulse levels:
• Input rise and fall times:
• Output load:
• InpuVOutput Timing Reference level:
0.8 V / 2.4 V
:S 10 ns
1 TTL Gate + CL = 100 pF (Including jig capacitance)
1.S V
HN624017·17
Item
Symbol
Min.
Max.
Unit
tRC
170
-
ns
Address Access Time
tM_
-
170
ns
CE Access Time
tACE
-
170
ns
OE Access Time
tOE
-
70
ns
BHE Access Time
tSHE
-
200
ns
Output Hold Time from
Address Change
tOHA
0
-
ns
Output Hold Time
from CE
t OHC
0
-
ns
Outpu.!.!i0ld Time
from OE
tOHO
0
-
ns
Output Hold Time
from BHE
t OHS
0
-
ns
CE to Output in High Z
tCHZ
1
ns
tOHZ
70
ns
tSHZ
1
-
70
1
70
ns
tCLl
1
10
ns
tOll
1
10
tSLl
1
10
-
Read Cycle Time
OE to Output in High Z
BHE to Output in High Z
CE to Output in Low Z
OE to Output in Low Z
BHE to Output in Low Z
Note:
1.
ns
ns
tCHZ ' tOHZ ' and laHZ are defined as the time at which the output becomes an open circuit and
are not referenced to output voltage levels.
HITACHI
Hitachi America, Ltd.' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300
5-99
HN624017 series
•
-----------------~----:
READ TIMING WAVEFORM
Word Mode (BHE VI..) or Byte Mode (BHE
=
=Vi L)
...
Address
W
r\
I
-
tAA
-tOHA
I
tCHZ
tACE
tCLZ
"
OE
HighZ
,
Dataqut,
tOHC~
-
tOHZ
tOE
tOlZ
tOHO-
O
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