1992_IDT_High_Performance_Logic_Data_Book 1992 IDT High Performance Logic Data Book
User Manual: 1992_IDT_High_Performance_Logic_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 770
| Download | |
| Open PDF In Browser | View PDF |
1992
DATA
BOOK
HIGH,
PERFORMANCE
LOGIC
INCLUDES ~. ~V AND
DOUBLE ... DENSITY LOGIC
Integrated Device Technology. Inc.
1992
HIGH·PERFORMANCE
LOGIC
DATA BOOK
2975 Stender Way, Santa Clara, California 95054-3090
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674
GENERAL INFORMATION
II
CONTENTS OVERVIEW
For ease of use for our customers, Integrated Device Technology provides four separate data books:
High-Performance Logic, Specialized Memories and Modules, RISC and RISC SubSystems, and Static
RAM.
lOTs 1992 Logic Data Book is comprised of new and revised data sheets on Double-Density standard
SV logic, standard SV logic, 3.3V logic, 3.3V-to-SV translators, and complex logic products. Also included
is a current packaging section for the products included in this book.
The 1992 High-Performance Logic Data Book's Table of Contents contains a listing of the products
contained in this data book only (in the past, we have included products that appeared in other lOT data
books). The numbering scheme for the book is consistent with the 1990-91 data books. The number at
the bottom center of the page denotes the section number and the sequence of the data sheet within that
section, (i.e., S.S would bethefifth data sheet in the fifth section). The numberin the lower right-hand corner
is the page number for that particular data sheet.
Integrated Device Technology, Inc. is a recognized leader in high-speed CMOS technology and
produces a broad line of products. This enables us to provide a complete CMOS solution to designers of
high-performance digital systems. Not only do our product lines include industry standard devices, they
also feature products with faster speeds, lower power, and package and/or architectural benefits that allow
designers to significantly improve system performance.
To find ordering Information: Ordering Information for all products in this book appears in Section
1, along with the Package Outline Index, Product Selector Guides, Ordering Information, and Standard
Logic Timing Diagrams. Reference data on our Technology Capabilities and Quality Commitments is
included in separate sections (2 and 3, respectively).
To find product data: Start with the Table of Contents, organized by product line (page 1.2), or with
the Numeric Table of Contents (page 1.4). These indexes will direct you to the page on which the complete
technical data sheet can be found. Data sheets may be of the following type:
ADVANCE INFORMATION-contain initial descriptions (subject to change) for products that are in
development, including features and block diagrams.
PRELIMINARY-contain descriptions for products soon to be, or recently released to production,
including features, pinouts, and block diagrams. Timing data are based on simulation or initial characterization and are subject to change upon full characterization.
FINAL-contain minimum and maximum limits specified over the complete supply and temperature
range for full production devices.
New products, product performance enhancements, additional package types, and new product
families are being introduced frequently. Please contact your local lOT sales representative to determine
the latest device specifications, package types, and product availability.
ABOUT THE COVER
The cover features a High-Performance Double-Density wafer shown at approximately 3x magnification with a sampling of both standard, octal and Double-Density FCT-T packaged units shown at slightly
larger than actual size. lOT's high-speed logic products are excellent for use in high-performance data
processing systems. The new 3.3V members of the Double-Density family were specifically designed to
address the low-power, low~noise requirements of battery operated systems, such as laptop and notebook
computers. lOT also offers a SV-to-3.3V translator chip that interfaces today's higher-voltage systems with
next-generation low-voltage systems.
1.1
II
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components In life support devices or systems
unless a specific written agreement pertaining to such Intended use Is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are Intended for surg Ica limp lant Into the body or (b) support
or sustain life and whose failure to perform, when properly used In accordance with Instructions for use provided In the
labeling, can be reasonably expected to result In a significant InJury to the user.
2. A critical component Is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect Its safety or effectiveness.
Nota: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any circuitry described other than the circuitry
embodied in an lOT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device
Technology, Inc.
The lOT logo is a registered trademark, and BUSMUX, Flexi-pak, BiCEMOS, CacheRAM, CEMOS, FASTX, Flow-thruEOC, 10T/c, lOT/envY, 10T/sae, lOT/
sim, 10T/ux, MacStation, REAL8, RISC SubSystem, RISControl\er, RISCore, SmartLogic, SyncFIFO, TargetSystem, R3051 , and R3081 are trademarks of
Integrated Device Technology, Inc.
All other trademarks are trademarks of their respective companies.
1.1
2
1992 LOGIC DATA BOOK
TABLE OF CONTENTS
PAGE
GENERAL INFORMATION
Contents Overview ........................................................................................................,.......................................
Table of Contents .................................................................................................................................................
Numeric Table of Contents .................................................................................................................................~.
Ordering Information..... ....................... ........... ........ ............ ........... ............ .............. ....................... ........ ..............
IDT Package Marking Description ........................................................................................................................
Standard Logic Timing Diagrams .......................................................................................... ...............................
Logic Product Selector Guide ...............................................................................................................................
1.1
1.2
1.3
1.4
1.5
1.6
1.7
TECHNOLOGY AND CAPABILITIES
IDT... Leading the CMOS Future ............................ ...............................................................................................
IDT Military and DESC-SMD Program ...................................................................................................................
Radiation Hardened Technology ..................................................................................................,.......................
lOT Leading Edge CEMOS Technology .................................................................;.............................................
Surface Mount Technology ...................................................................................................................................
State-of-the-Art Facilities and Capabilities .....................................................;......................................................
Superior Quality and Reliability ..............................................................................................................................
2.1
2.2
2.3
2.4
2.5
2.6
2.7
QUALITY AND RELIABILITY
Quality, Service and Performance ......................................................................................................................... 3.1
IDT Quality Conformance Program .....................................................................................................................; 3.2
Radiation Tolerant/Enhanced/Hardened Products for Radiation Environments ................................................... .3.3
PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for IDT's Packages ............................................. :......................................... 4.1
Package Diagram Outline Index .........................................................................................;........... '....................... 4.2
Monolithic Package Diagram Outlines .................................................................................................................. . 4.3
DOUBLE DENSITY STANDARD 5V LOGIC PRODUCTS
DOUBLE DENSITY WITH HIGH OUTPUT DRIVE
IDT54/74FCT16240T
IDT54/74FCT16244T
IDT54/74FCT16245T
IDT54/74FCT16373T
IDT54/74FCT16374T
IDT54/74FCT16500T
IDT54/74FCT16501 T
IDT54/74FCT16543T
IDT54/74FCT16646T
IDT54/74FCT16652T
IDT54/74FCT16952T
IDT54/74FCT16823T
IDT54/74FCT16827T
IDT54/74FCT16841T
16-8it Inverting 8uffer/Line Driver ............................ ~................................................ 5.1
16-8it Non-inverting 8uffer/Line Driver ...................................................................... 5.2
16-8it Non-inverting Transceiver ......... :..................................................................... 5.3
16-8it Non-inverting Transparent Latch w/3-State .................................................... 5.4
16-8it Non-inverting Register w/3-State .................................................................... 5.5
18-8it Non-inverting Neg. Edge Triggered Registered Transceiver .......................... 5.6
18-8it Non-inverting Pos. Edge Triggered Registered Transceiver ...........................5.7 .
16-8it Non-inverting Latched Transceiver .......... .................. ................... .................. 5.8
16-8it Non-inverting Registered Transceiver ............................................................. 5.9
16-8it Non-inverting Registered Transceiver ............ ~ ................... :.......... ;................. 5.10
16-8it Non-inverting Registered Transceiver ...................... ........... ............ ................ 5.11
18-8it Non-inverting Register w/Clear & Reset.. .............. ................. ........................ 5.12
20-8it Non-inverting 8uffer w/3-State ................ .................................. ...................... 5.13'
20-8it Non-inverting Latch .....................................................................:................... 5.14
DOUBLE DENSITY WITH BALANCED OUTPUT DRIVE
IDT54/74FCT162240T
IDT54/74FCT162244T
IDT54/74FCT162245T
IDT54/74FCT162373T
IDT54/74FCT162374T
16-8it Inverting 8uffer/Line Drive w/Resistors .......... ............ ........ ...... ...... ..... ............
16-8it Non-inverting 8uffer/Line Drive w/Resistors ........ ............................... ...... ......
16-8it Non-inverting Transceiver w/Resistors ...........................................................
16-8it Non-inverting Transparent Latch w/Resistors & 3-State ............ :...... ...... ........
16-8it Non-inverting Register w/Resistors & 3-State .............................................. :..
1.2
5.1
5.2
5.3
5.4
5.5
II
1992 LOGIC DATA BOOK (CONTINUED)
DOUBLE DENSITY WITH
IDT54/74FCT162500T
IDT54/74FCT162501 T
IDT54/74FCT162543T
IDT54/74FCT162646T
IDT54/74FCT162652T
IDT54/74FCT162952T
IDT54/74FCT162823T
IDT54/74FCT162827T
IDT54/74FCT162841 T
PAGE
BALANCED OUTPUT DRIVE (CONTINUED)
18-Bit Non-inverting Neg. Edge Triggered Registered Transceiver w/Resistors .......
18-Bit Non-inverting Pas. Edge Triggered Registered Transceiver w/Resistors .......
16-Bit Non-inverting Latched Transceiver w/Resistors .............................................. .
16-Bit Non-inverting Registered Transceiver w/Resistors ..........................................
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
18-Bit Non-inverting Registerw/Resistors, Clear, & Reset .... ;..................................
20-Bit Non-inverting Buffer w/Resistors & 3-State ............. ;........ ...... ........ ...... ...........
20-Bit Non-inverting Latch w/Resistors .....................................................................
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
STANDARD 5V LOGIC PRODUCTS
IDT29FCT52T
IDT29FCT53T
IDT29FCT520T
IDT29FCT521 T
IDT54/74FCT138T
IDT54/74FCT139T
IDT54/74FCT151T
IDT54/74FCT251T
IDT54/74FCT157T
IDT54/74FCT257T
IDT54/74FCT161T
IDT54/74FCT163T
IDT54/74FCT191 T
IDT54/74FCT193T
IDT54/74FCT240T
IDT54/74FCT241T
IDT54/74 FCT244T
IDT54/74FCT540T
IDT54/74FCT541T
IDT54/74FCT245T
IDT54/74 FCT640T
IDT54/74FCT645T
IDT54/74FCT273T
IDT54/74FCT299T
IDT54/74FCT373T
IDT54/74FCT533T
IDT54/74FCT573T
IDT54174FCT374T
IDT54174FCT534T
IDT54174FCT574T
IDT54174FCT377T
IDT54174FCT399T
IDT54174FCT521 T
IDT5417 4FCT543T
IDT54/74FCT646T
IDT54/74FCT648T
IDT54/74FCT651 T
IDT54/74FCT652T
IDT54/74FCT620T
IDT54/74FCT623T
IDT54/74FCT621 T
IDT54174FCT622T
IDT54/7 4FCT821 T
Non-inverting Octal Registered Transceiver .......................................... .................... 6.1
Inverting Octal Registered Transceiver ..................................................................... 6.1
Multi-level Pipeline Register ...................................................................................... 6.2
Multi-level Pipeline Register ............. ......................................................................... 6.2
1-of-8 Decoder .......... ...... ........................................ ........... ......... ............................... 6.3
DuaI1-of-4 Decoder ........................................................ .................. ......................... 6.4
8-lnput Multiplexer.. .............. ............ ........................................................ ................. 6.5
8-lnput Multiplexer w/3-State ..................................................................................... 6.5
Quad 2-lnput Multiplexer ......................................................................... .................. 6.6
Quad 2-lnput Multiplexer w/3-State ........................................................... ................ 6.6
Synchronous Binary Counter w/Asynchronous Master Reset .......................... ,........ 6.7
Synchronous Binary Counter w/Synchronous Reset .............................. ................... 6.7
Up/Down Binary Counter w/Preset and Ripple Clock................................................ 6.8
Up/Down Binary Counter w/Separate Up/Down Clocks ............................ ................ 6.9
Inverting Octal Buffer/Line Driver .............................................................................. 6.10
Non-inverting Octal Buffer/Line Driver.. ........ ...... ...... ...... .................................... ....... 6.10
Non-inverting Octal Buffer/Line Driver ...................... ................................................. 6.10
Inverting Octal Buffer/Line Driver .. ........ ...... .............. ...... ...... ........ ...... ........ .............. 6.10
Non-inverting Octal Buffer/Line Driver ....................................................................... 6.10
Non-inverting Octal Transceiver ................................................................................ 6.11
Inverting Octal Transceiver ................................................ :............................... ;....... ·6.11
Non-inverting Octal Transceiver ................................................................................ 6.11
Octal D Flip-Flop w/Common Master Reset ....................................... ;...................... 6.12.
8 Input Universal Shift Register w/Common Parallel I/O Pins .......... ~........................ 6.13
Non-inverting Octal Transparent Latch w/3-State ..................................................... 6.14
Inverting Octal Transparent Latch w/3-State ........................................................... ~. 6.14
Non-inverting Octal Transparent Latch w/3-State .. ........ ...... ...... ........ ............ ........... 6.14
Non-inverting Octal D Register .................................................................................. 6.15
Inverting Octal D Register ........ :................................................................................ 6.15
Non-inverting Octal D Register .................................................................................. 6.15
Octal D Flip-Flop w/Clock Enable .............................................................................. 6.16
Quad Dual-Port Register .................. :.......................... .............................................. 6.17
a-Bit Identity Comparator ............................................................................................ 6.18
Non-inverting Octal Latched Transceiver ...................................... ;........................... 6.19
Non-inverting Octal Registered Transceiver .................. ~........................................... 6.20
Inverting Octal Registered Transceiver .... ~................................................................ 6.20
Inverting Octal Registered Transceiver ..................................................................... 6.20
Non-inverting Octal Registered Transceiver ............. ~;............................................... 6.20
Inverting Octal Bus Transceiver w/3-State ................................................................ 6.21
Non-inverting Octal Bus Transceiver w/3-State ......................................................... 6.21
Non-inverting Octal Bus Transceiver (Open Drain) ..............................................;.... 6.22
Inverting Octal Bus Transceiver (Open Drain) .......................................................... 6.22
10-Bit Non-inverting Register w/3-State .......... ...... ...... .............. ...... .......................... 6.23
1.2
2
1992 LOGIC DATA BOOK (CONTINUED)
PAGE
STANDARD 5V lOGIC PRODUCTS (CONTINUED)
IDT54/74FCT823T
9-Bit Non-inverting Register w/Clear & 3-State ..........................................................
IDT54/74FCT825T
8-Bit Non-inverting Register w/Clear & 3-State .........................................................
IDT54/74FCT826T
8-Bit Inverting Register w/Clear & 3-State .................................................................
IDT54/74FCT827T
10-Bit Non-inverting Buffer ........................................................................................
IDT54/74FCT828T
10-Bit Inverting Buffer ................................................................................................
IDT54/74FCT841T
10-Bit Non-inverting Latch .........................................................................................
IDT54/74FCT843T
9-Bit Non-inverting Latch ...........................................................................................
IDT54/74FCT845T
8-Bit Non-inverting Latch ...........................................................................................
IDT29FCT52
IDT29FCT53
IDT29FCT520
IDT49FCT805
IDT49FCT806
IDT54/74FCT138
IDT54/74FCT139
IDT54/74FCT161
IDT54/74FCT163
IDT54/74FCT182
IDT54/74FCT191
IDT54/74FCT193
IDT54/74FCT240
IDT54/74 FCT241
IDT54/74FCT244
IDT54/74FCT540
IDT54/74FCT541
IDT54/74FCT245
IDT54/74FCT640
IDT54/74FCT645
IDT54/74FCT273
IDT54/74FCT299
IDT54/74FCT373
IDT54/74FCT533
IDT54/74FCT573
IDT54/74FCT374
IDT54/74FCT534
IDT54/74FCT574
IDT54/74FCT377
IDT54/74FCT399
IDT54/74FCT521
IDT54/74FCT543
IDT54/74FCT646
IDT54/74FCT821
IDT54/74FCT823
IDT54/74FCT824
IDT54/74FCT825
IDT54/74FCT827
IDT54/74FCT833
IDT54/74FCT841
IDT54/74FCT843
IDT54/74FCT844
IDT54/74FCT845
IDT54/74FCT861
IDT54/74FCT863
IDT54/74FCT864
Non-inverting Octal Registered Transceiver ..............................................................
Inverting Octal Registered Transceiver .....................................................................
Multi-level Pipeline Register ......................................................................................
Buffer/Clock Driver w/Guaranteed Skew ...................................................................
Inverting Buffer/Clock Driver w/Guaranteed Skew ....................... ;........................... .
1-of-8 Decoder .........................................................................................,................ .
Dual 1-of-4 Decoder .................... ,.. ,................................. ,....................................... .
Synchronous Binary Counter w/Asynchronous Master Reset ................................. ..
Synchronous Binary Counter w/Synchronous Reset ................................................ .
Carry Lookahead Generator .................................................................,............ ,...... .
Up/Down Binary Counter w/Preset and Ripple Clocks ............................................. .
Up/Down Binary Counter w/Separate Up/Down Clocks ........................................... .
Inverting Octal Buffer/Line Driver ................................................................... '" ....... .
Non-inverting Octal Buffer/Line Driver ......................................................................•
Non-inverting Octal Buffer/Line Driver .......................................................................
Inverting Octal Buffer/Line Driver ..............................................................................
Non-inverting Octal Buffer/Line Driver ...................................................................... .
Non-inverting Octal Transceiver ................................................................................
Inverting Octal Transceiver ........................................................................................
Non-inverting Octal Transceiver ........................................................... '" ................. .
Octal D Flip-Flop w/Common Master Reset .............................................................
8-lnput Universal Shift Register w/Common Parallel I/O Pins ...................................
Non-inverting Octal Transparent Latch ...... ,...............................................................
Inverting Octal Transparent Latch .............................................................................
Non-inverting Octal Transparent Latch ......................................................................
Non-inverting Octal 0 Flip-Flop .................................................................................
Inverting Octal D Flip-Flop w/3-State ............... ,'" '" .......... ,.. ,................... ,................ .
Non-inverting Octal 0 Register w/3-State ..................................................................
Octal D Flip-Flop w/Clock Enable .................. ,...........................................................
Quad Dual-Port Register ................................. '" .............. '" ..................................... .
8-Bit Identity Comparator ...................... '" .............................................................,... .
Non-inverting Octal Latched Transceiver ..................................................................
Non-inverting Octal Registered Transceiver ..............................................................
1O-Bit Non-inverting Register w/3-State ................. ,................................................. .
9-Bit Non-inverting Register w/Clear & 3-State ... ,.. ,................................................. .
9-Bit Inverting Register w/Clear & 3-State .................................................................
8-Bit Non-inverting Register ......................................................................................
10-Bit Non-inverting Buffer ........................................................................................
~~~~i;~~~_~~~:~i~~~~i~.:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
9-Bit Non-inverting Latch ...........................................................................................
9-Bit Inverting Latch ...................................................................................................
8-Bit Non-inverting Latch ......................................................................... '" .............. .
10-Bit Non-inverting Transceiver ............................................. ~ ............................... ..
9-Bit Non-inverting Transceiver .................................................................................
9-Bit Inverting Transceiver .........................................................................................
1.2
II
6.23
6.23
6.23
6.24
6.24
6.25
6.25
6.25
6.26
6.26
6.27
6.28
6.28
6.29
6.30
6.31
6.31
6.32
6.33
6.34
6.35
6.35
6.35
6.35
6.35
6.36
6.36
6.36
6.37
6.38
6.39
6.39
6.39
6.40
6.40
6.40
6.41
6.42
6.43
6.44
6.45
6.46
6.46
6.46
6.46
6.47
6.48
6.49
6.49
6.49
6.49
6.50
6.50
6.50
3
1992 LOGIC DATA BOOK (CONTINUED)
PAGE
STANDARD 5V LOGIC PRODUCTS (CONTINUED)
IDT54/74FBT2240
Inverting Octal Buffer/Line Driver w/25o. Series Resistor ..........................................
IDT54/74FBT2244
Inverting Octal Buffer/Line Driver w/25o. Series Resistor .. '" ..... ... ... ...... ... ..... ... ...... ...
IDT54/74FBT2373
Octal Transparent Latch w/3-State & 250. Series Resistor .......................................
IDT54/74FBT2827
Non-inverting 1O-Bit Buffers/Driver w/25o. Series Resistor .......... '" ......... '" ..... ... ......
IDT54/74FBT2828
Inverting10-Bit BufferslDriver w/25o. Series Resistor .... :...........................................
IDT54/74FBT2841
1O-Bit Memory Latch w/25o. Series Resistor .................................................... ;........
6.51
6.52
6.53
6.54
6.54
6.55
STANDARD 5V LOGIC MODULES (Please refer to the 1992 Specialized Memories and Modules Data Book)
IDT7MP9244T/AT/CTZ
Fast CMOS 32-Bit Buffer/Line Driver Module............................................................ 7.43
IDT7MP9245T/AT/CTZ
Fast CMOS 32-Bit BidirectionallTransceiver Module ................................................ 7.43
3.3V LOGIC AND 3.3V TO 5V TRANSLATORS
3.3VLOGIC
IDT54/74FCT163244
IDT54/74FCT163245
IDT54/74FCT163373
IDT54/74FCT16337 4
IDTS4/74FCT163S01
IDT54/74FCT163646
IDTS4/74FCT3244
IDT54/74FCT324S
3.3V 16-Bit Non-inverting Buffer/Line Driver w/Resistors ..... '" ........... ... ........ ... ... ... ....
3.3V 16-Bit Non-inverting Transceiver w/Resistors ....................................................
3.3V 16-Bit Non-inverting Transparent Latch 21Resistors & 3-State .........................
3.3V 16-Bit Register w/Resistors and 3-State ......................................................:....
3.3V 18-Bit Non-inverting Registered Transceiver w/Resistors.................................
3.3V 16-Bit Non-inverting Registered Transceiverw/ Resistors ........................ :.......
3.3V Octal Buffer/Une Driver .....................................................................................
3.3V Octal Transceiver ..............................................................................................
7.1
7.2
7.3
7.4
7.S
7.6·
7.7
·7.8
BIDIRECTIONAL 3.3V TO 5V TRANSLATORS
IDT54/74FCT16424ST
SV to 3.3V 16-Bit Translating Transceiver .................................................................. 7.9
UNIDIRECTIONAL 3.3V TO 5V TRANSLATORS
IDT54/74FCT163244
SV to 3.3V 16-Bit Translating Buffer/Line Driver ........................................................
IDT54/74FCT163373
SV to 3.3V 16-Bit Translating Transparent Latch ........................ ~.............................
SV to 3.3V 16-Bit Translating Register .............................. ........................................
IDT54/74FCT16337 4
IDT54/74FCT3244
SV to 3.3V Octal Translating Buffer/Line Driver ............. ~...........................................
7.10
7;10
7.10
7.10
COMPlEX LOGIC PRODUCTS
DSP AND MICROSLICETM PRODUCTS
IDT39C10
12-Bit Sequencer ....................................................................................................... 8.1
IDT49C402
16-Bit Microprocessor Slice ........................................................................................ 8.2
IDT49C410
16-Bit Sequencer ....... :...................................................... :......................................... 8.3
IDT7210L
16 x 16 Parallel Multiplier-Accumulator ......................... ~.... ....................................... 8.4
IDT7216L
16 x 16 Parallel Multiplier ................................................ ~......................................... 8.S
IDT7217L
16 x16 Parallel Multiplier (32 Bit Output) .................................................................. 8.S
IDT7381 L
16-Bit CMOS Cascadable ALU ................................................................................. .8.6
IDT7383L
16-Bit CMOS Cascadable ALU ................................................................................. 8.6
READIWRITE BUFFER/BUS MULTIPLEXER PRODUCTS
IDT73200L
16-Bit CMOS Multilevel Pipeline Register .................................................................
IDT73201 L
16-Bit CMOS Multilevel Pipeline Register .................................................................
IDT73210
Fast Octal Register Transceiver w/Parity .. .......................... ................... ............... ....
IDT73211
Fast Octal Register Transceiver w/Parity ........................ ;.........................................
IDT73720
16-Bit 3-Port Latched Bus Exchanger ............................................. :.........................
8.7
8.7
8.8
8.8
8.9
ERROR DETECTION AND CORRECTION PRODUCTS
IDT39C60
16-Bit Cascadable EDC.............................................................................................
lOT49C460
32-Bit Cascadable EDC .............................................................................................
IDT49C465
32~Bit CMOS Flow-ThruEDC Unit .............................................................................
IDT49C466
64-Bit CMOS Flow-ThruEDC Unit .............................................................................
8.10
8.11
8.12
8.13
IDT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS
1.2
4
NUMERICAL TABLE OF CONTENTS
PAGE
PART NO.
IDT29FCT52
IDT29FCT520
IDT29FCT520T
IDT29FCT521T
IDT29FCT52T
IDT29FCT53
IDT29FCT53T
IDT39C10
IDT39C60
IDT49C402
IDT49C410
IDT49C460
IDT49C465
IDT49C466
IDT49FCT805
IDT49FCT806
IDT54/74FBT2240
IDT54/74FBT2244
IDT54/74FBT2373
IDT54/74FBT2827
IDT54/74FBT2828
IDT54/74FBT2841
IDT54/74FCT138
IDT54/74FCT138T
IDT54/74FCT139
IDT54/74FCT139T
IDT54/74FCT151T
IDT54/74FCT157T
IDT54/74FCT161
IDT54/74FCT161T
IDT54/7 4FCT162240T
IDT54/74FCT162244T
IDT54/74FCT162245T
IDT54/74FCT162373T
IDT54/7 4FCT16237 4T
IDT54/74FCT16240T
IDT54/74FCT16244T
IDT54/74FCT16245T
IDT54/74FCT162500T
IDT54/74FCT162501T
IDT54/74FCT162543T
IDT54/74FCT162646T
IDT54/74FCT162652T
IDT54/74FCT162823T
IDT54/74FCT162827T
IDT54/7 4FCT162841 T
IDT54/74FCT162952T
IDT54/74FCT163
IDT54/74FCT163244
IDT54/74FCT163244
IDT54/74FCT163245
IDT54/74FCT163373
IDT54/74FCT163373
IDT54/74FCT163374
Non-inverting Octal Registered Transceiver ..............................................................
Multi-level Pipeline Register .................................................................................... ..
Multi-level Pipeline Register .................................................................................... ..
Multi-level Pipeline Register .................................................................................... ..
Non-inverting Octal Registered Transceiver ............................................................ ..
Inverting Octal Registered Transceiver ................................................................... ..
Inverting Octal Registered Transceiver ................................................................... ..
12-Bit Sequencer .......................................................................................................
16-Bit Cascadable EDC .............................................................................................
16-Bit Microprocessor Slice .......................................................................................
16-Bit Sequencer .......................................................................................................
32-Bit Cascadable EDC .............................................................................................
32-Bit CMOS Flow-ThruEDC Unit ............................................................................ .
64-Bit CMOS Flow-ThruEDC Unit ............................................................................ .
Buffer/Clock Driver w/Guaranteed Skew ...................................................................
Inverting Buffer/Clock Driver w/Guaranteed Skew .................................................. ..
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ........................................ ..
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ........................................ ..
Octal Transparent Latch w/3-State & 25Q Series Resistor ...................................... .
Non-inverting 10-Bit Buffers/Driver w/25Q Series Resistor ..................................... ..
Inverting10-Bit Buffers/Driver w/25Q Series Resistor ................................................ .
1O-Bit Memory Latch w/25Q Series Resistor ............................................................ .
1-of-8 Decoder ...........................................................................................................
1-of-8 Decoder ...........................................................................................................
Dual 1-of-4 Decoder ..................................................................................................
Dual 1-of-4 Decoder ..................................................................................................
8-lnput Multiplexer .....................................................................................................
Quad 2-lnput Multiplexer ...........................................................................................
Synchronous Binary Counter w/Asynchronous Master Reset .................................. .
Synchronous Binary Counter w/Asynchronous Master Reset .................................. .
16-Bit Inverting Buffer/Line Drive w/Resistors ...................................................;...... .
16-Bit Non-inverting Buffer/Line Drive w/Resistors ...................................................
16-Bit Non-inverting Transceiver w/Resistors .......................................................... .
16-Bit Non-inverting Transparent Latch w/Resistors & 3-State ................................ .
16-Bit Non-inverting Register w/Resistors & 3-State .................................................
16-Bit Inverting Buffer/Line Driver ............................................................................ .
16-Bit Non-inverting Buffer/Line Driver ......................................................................
16-Bit Non-inverting Transceiver ...............................................................................
18-Bit Non-inverting Neg. Edge Triggered Registered Transceiver w/Resistors ...... .
18-Bit Non-inverting Pas. Edge Triggered Registered Transceiver w/Resistors ...... .
16-Bit Non-inverting Latched Transceiver w/Resistors ..............................................
16-Bit Non-inverting Registered Transceiver w/Resistors ........................................ .
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
18-Bit Non-inverting Register w/Resistors, Clear, & Reset ...................................... .
20-Bit Non-inverting Buffer w/Resistors & 3-State .....................................................
20-Bit Non-inverting Latch w/Resistors ................................................................... ..
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
Synchronous Binary Counter w/Synchronous Reset.. ...............................................
3.3V 16-Bit Non-inverting Buffer/Line Driver w/Resistors ........................................ ..
5V to 3.3V 16-Bit Translating Buffer/Line Driver ...................................................... ..
3.3V 16-Bit Non-inverting Transceiver w/Resistors ................................................. ..
3.3V 16-Bit Non-inverting Transparent Latch 2/Resistors & 3-State ........................ .
5V to 3.3V 16-Bit Translating Transparent Latch ..................................................... .
5V to 3.3V 16-Bit Translating Register ......................................................................
1.3
6.26
6.27
6.2
6.2
6.1
6.26
6.1
8.1
8.10
8.2
8.3
8.11
8.12
8.13
6.28
6.28
6.51
6.52
6.53
6.54
6.54
6.55
6.29
6.3
6.30
6.4
6.5
6.6
6.31
6.7
5.1
5.2
5.3
5.4
5.5
5.1
5.2
5.3
5.6
5.7
5.8
5.9
5.10
5.12
5.13
5.14
5.11
6.31
7.1
7.10
7.2
7.3
7.10
7.10
II
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
IDT54/7 4FCT16337 4
IDT54/74FCT163501
IDT54/74FCT163646
IDT54/74FCT16373T
IDT54/74FCT16374T
IDT54/74FCT163T
IDT54/74FCT164245T
IDT54/74FCT16500T
IDT54/74FCT16501 T
IDT54/74FCT16543T
IDT54/74FCT16646T
IDT54/74FCT16652T
IDT54/74FCT16823T
IDT54/74FCT16827T
IDT54/74FCT16841T
IDT54/74FCT16952T
IDT54/74FCT182
IDT54/74FCT191
IDT54/74FCT191T
IDT54/74FCT193
IDT54/74FCT193T
IDT54/74FCT240
IDT54/74FCT240T
IDT54174FCT241
IDT54/74FCT241 T
IDT54/74FCT244
IDT54/74FCT244T
IDT54/74FCT245
IDT54/74FCT245T
IDT54/74FCT251T
IDT54/74FCT257T
IDT54/74FCT273
IDT54/74FCT273T
IDT54/74FCT299
IDT54/74FCT299T
IDT54/74FCT3244
IDT54/74FCT3244
IDT54/74FCT3245
IDT54/74FCT373
IDT54/74FCT373T
IDT54/74FCT37 4
IDT54/74FCT37 4T
IDT54/74FCT377
IDT54/74FCT377T
IDT54/74FCT399
IDT54/74FCT399T
IDT54/74FCT521
IDT54/74FCT521 T
IDT54/74FCT533
IDT54/74FCT533T
IDT54/74FCT534
IDT54/74FCT534T
IDT5417 4FCT540
IDT54/74FCT540T
PAGE
3.3V 16-Bit Register w/Resistors and 3-State ...........................................................
3.3V 18-Bit Non-inverting Registered Transceiver w/Resistors .................................
3.3V 16-Bit Non-inverting Registered Transceiver w/ Resistors ..... ...........................
16-Bit Non-inverting Transparent Latch w/3-State ....................................................
16-Bit Non-inverting Register w/3-State ..................................................... '" ... ... ......
Synchronous Binary Counter w/Synchronous Reset .......... ~ ....... , '" ... ...... ..... ...... .......
5V to 3.3V 16-Bit Translating Transceiver .................................................................
18-Bit Non-inverting Neg. Edge Triggered Registered Transceiver ..........................
18-Bit Non-inverting Pas. Edge Triggered Registered Transceiver ...........................
16-Bit Non-inverting Latched Transceiver ............. ...... ......... ........... ... ... ..... ... ... ... ......
16-Bit Non-inverting Registered Transceiver .......................................... ...................
16-Bit Non-inverting Registered Transceiver .. .............. ... ........... ... ... ...... ..... ... ... ... .....
18-Bit Non-inverting Register w/Clear & Reset ............. ............................................
20-Bit Non-inverting Buffer w/3-State ....................'....................................................
20-Bit Non-inverting Latch .........................................................................................
16-Bit Non-inverting Registered Transceiver .............................................................
Carry Lookahead Generator ......................................................................................
Up/Down Binary Counter w/Preset and Ripple Clocks ..............................................
Up/Down Binary Counter w/Preset and Ripple Clock................................................
Up/Down Binary Counter w/Separate Up/Down Clocks ............................................
Up/Down Binary Counter w/Separate Up/Down Clocks ............................................
Inverting Octal Buffer/Line Driver ........................................................................, .....
Inverting Octal Buffer/Line Driver ..............................................................................
Non-inverting Octal Buffer/Line Driver ..... ..................................... .............................
Non-inverting Octal Buffer/Line Driver ..... ..... ... ... ...... ... ..... ... ... ... ... ........ ... ... ... ..... ... ....
Non-inverting Octal Buffer/Line Driver ................................................. ' ... ... ... ..... ... ....
Non-inverting Octal Buffer/Line Driver ..... ........... .............. ...... ...... ..... ... ... ... ... ..... ... ....
Non-inverting Octal Transceiver ................................................................................
Non-inverting Octal Transceiver ................................................................................
8-lnput Multiplexer w/3-State .............................................. ;......................................
Quad 2-lnput Multiplexer w/3-State .. ". .............. ... ........ ...... ...... ..... ... ... ...... ... .............
Octal D Flip-Flop w/Common Master Reset .............................................................
Octal D Flip-Flop w/Common Master Reset ................................ .'.............................
8-lnput Universal Shift Register w/Common Parallel I/O Pins ...................................
8 Input Universal Shift Register w/Cbmmon Parallel I/O Pins ...................................
3.3V Octal Buffer/Line Driver .................................................... ;................................
5V to 3.3V Octal Translating Buffer/Line Driver .........................................................
3.3V Octal Transceiver ..............................................................................................
Non-inverting Octal Transparent Latch ......................................................................
Non-inverting Octal Transparent Latch w/3-State .....................................................
Non-inverting Octal D Flip-Flop ........ ........ ...... .......................................... ............ .....
Non-inverting Octal D Register ................... :..............................................................
Octal D Flip-Flop w/Clock Enable ..............................................................................
Octal D Flip-Flop w/Clock Enable..............................................................................
Quad Dual-Port Register ............. ...... ......... ........ ...... ........ ......... ..... ...... .............. .......
Quad Dual-Port Register ........................... ~...............................................................
8-Bit Identity Comparator .............. :..................... ......... ..... ...... ...... ........ ......... ..... .......
8-Bit Identity Comparator ...........................................................................................
Inverting Octal Transparent Latch ......................... ;...................................................
Inverting Octal Transparent Latch w/3-State .. ...... ..... ... ............ .............. ........ ...........
Inverting Octal D Flip-Flopw/3-State .........................................................................
Inverting Octal D Register ..... ........ ...... ........... ...... .............. ......... .............. ......... .......
Inverting Octal Buffer/Line Driver .......... ......... ...... ........ ...... .............. ...... ........ ...........
Inverting Octal Buffer/Line Driver ................... ...... ..... ...... .............. ............ ........... .....
1.3
7.4
7.5
7.6
5.4
5.5
6.7
7.9
5.6
5.7
5.8
5.9
5.10
5.12
5.13
5.14
5.11
6.32
6.33
6.8
6.34
6.9
6.35
6.10
6.35
6.10
6.35
6.10
6.36
6.11
6.5
6.6
6.37
6.12
6.38
6.13
7.7
7.10
7.8
6.39
6.14
6.40
6.15
6.41
6.16
6.42
6.17
6.43
6.18
6.39
6.14
6.40
6.15
6.35
6.10
2
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PAGE
PART NO.
IDT54/74FCT541
IDT54/74FCT541 T
IDT54/74FCT543
IDT54/74FCT543T
IDT54/74 FCT573
IDT54/74FCT573T
IDT54/74 FCT574
IDT54/74FCT574T
IDT54/74FCT620T
IDT54/74FCT621T
IDT54/74 FCT622T
IDT54/74FCT623T
IDT54/74FCT640
IDT54/74 FCT640T
IDT54/74 FCT645
IDT54/74FCT645T
IDT54/74FCT646
IDT54/74FCT646T
IDT54/74 FCT648T
IDT54/74FCT651T
IDT54/74FCT652T
IDT54/74FCT821
IDT54/74FCT821T
IDT54/74FCT823
IDT54/74 FCT823T
IDT54/74 FCT824
IDT54/74FCT825
IDT54/74FCT825T
IDT54/74FCT826T
IDT54/74 FCT827
IDT54/74 FCT827T
IDT54/74FCT828T
IDT54/74FCT833
IDT54/74FCT841
IDT54/74FCT841T
IDT54/74FCT843
IDT54/74FCT843T
IDT54/74FCT844
IDT54/74FCT845
IDT54/74FCT845T
IDT54/74FCT861
IDT54/74FCT863
IDT54/74FCT864
IDT7210L
IDT7216L
IDT7217L
IDT73200L
IDT73201L
IDT7321a
IDT73211
IDT73720
IDT7381L
IDT7383L
Non-inverting Octal Buffer/Line Driver .......................................................................
Non-inverting Octal Buffer/Line Driver .................... ,. ........ ... ...... ........... ......... ..... .......
Non-inverting Octal Latched Transceiver .....................•............................................
Non-inverting Octal Latched Transceiver ..................................................................
Non-inverting Octal. Transparent Latch ......................................................................
Non-inverting Octal Transparent Latch w/3-State ....................................... ..............
Non-inverting Octal D Register w/3-State ..................................................................
Non-inverting Octal D Register ..................................................................................
Inverting Octal Bus Transceiver w/3-State .................................................................
Non-inverting Octal. Bus Transceiver (Open Drain) ...................................................
Inverting Octal Bus Transceiver (Open Drain) ..........................................................
Non-inverting Octal Bus Transceiver w/3-State .........................................................
Inverting Octal Transceiver ........................................................................................
Inverting Octal Transceiver ........................................................................................
Non-inverting Octal Transceiver ..... ...........................................................................
Non-inverting Octal Transceiver ................................................................................
Non-inverting Octal Registered Transceiver ..............................................................
Non-inverting Octal Registered Transceiver ..............................................................
Inverting Octal Registered Transceiver .....................................................................
Inverting Octal Registered Transceiver .....................................................................
Non-inverting Octal Registered Transceiver ..............................................................
10-Bit Non-inverting. Register w/3-State ....................................................................
10-Bit Non-inverting Register w/3-State ........... ,. ...... ................. ... ...... ..... .............. ....
9-Bit Non-inverting Register w/Clear & 3-State .. ........ ... ...... ... ........ ... ...... ........ ... ... ....
9-Bit Non-inverting Register w/Clear & 3-State ........................................................ ,
9-Bit Inverting Register w/Clear & 3-State .................................................................
8-Bit Non-inverting Register ................................... , ............ ,................. , ..... , ... ..........
8-Bit Non-inverting Register w/Clear & 3-State ............................................... ..........
8-Bit Inverting Register w/Clear & 3-State .................................................................
10-Bit Non-inverting Buffer ........................................................................................
10-Bit Non-inverting Buffer ........................................................................................
10-Bit Inverting Buffer ................................................................................................
8-Bit Transceiver w/Parity ...... :..................................... : ...... ;......................................
1a-Bit Non-inverting Latch ...................................................,. ...... ..... ... ... ...... ........ .....
10-Bit Non-inverting Latch ....................................................................., ......... ..... .....
9-Bit Non-inverting Latch .......... ............................. ........ ...... ... ........... ... ...... ... ........ ....
9-Bit Non-inverting Latch ... ,.............................. ,. ...... ..... ... ...... ... ........... ...... ...... .........
9-Bit Inverting Latch .................:..................................................................................
8-Bit Non-inverting Latch .......................................................................,. ... ... ..... ... ....
8-Bit Non-inverting Latch .................................. ,.............................. ,........... ,... , .........
10-Bit Non-inverting Transceiver ................................................................... ............
9-Bit Non-inverting Transceiver .................................................................................
9-Bit Inverting Transceiver .........................................................................................
16 x 16 Parallel Multiplier-Accumulator .....................................................................
16 x 16 Parallel Multiplier ......................................................................................; .. :
16 x 16 Parallel Multiplier (32 Bit Output) ..................................................................
16-Bit CMOS Multilevel Pipeline Register .................................................................
16-Bit CMOS Multilevel Pipeline Register .................................................................
Fast Octal Register Transceiver w/Parity ..................................................................
Fast Octal Register Transceiver w/Parity ..................................................................
16-Bit 3-Port Latched Bus Exchanger ................................................................ .......
16-Bit CMOS Cascadable ALU .................................................................................
16-Bit CMOS Cascadable ALU .......... ...... ......... ........ ...... ...... ..... ...... .................... .....
1.3
6.35
6.10
6.44
6.19
6.39
6.14
6.40
6.15
6.21
6.22
6.22
6.21
6.36
6.11
6.36
6.11
6.45
6.20
6.20
6.20
6.20
6.46
6.23
6.46
6.23
6.46
6.46
6.23
6.23
6~47
6.24
6.24
6.48
6.49
6.25
6.49
6.25
6.49
6.49
6.25
6.50
6.50
6.50
8.4
8.5
8.5
8.7
8.7
8.8
8.8
8.9
8.6
8.6
3
ORDERING INFORMATION
FCTXXX, FCTXXXT
IDT74
FCT
Temp. Range
74 = Com'l Std:
OC to +70CJ
Com'13.3V: -40C to +85C
54 = Mil: -S5C to 125C
49 = Com'l Std:
OC to +70C
Com'l 3.3V: -40C to +85C
Mil: -55C to + 125C
29 = 29FCTXXX functions only:
Com'l Std:
OC to +70C
Com'13.3V: -40C to +85C
Mil: -S5C to +125C
240
P
T
A
Family Device Type Speed Output Package Process
L
Blank =Comm
B = Mil-STD-883, Class B
P = Plastic DIP
D =CERDIP
(*)
E =CERPACK
" - - - - - - l = leadless Chip Carrier
SO = Small Outline IC
py =SSOP
PX = EIAJ
Blank= Standard
3 = 3.3 Volts---------'
4 = 3.3 to 5V Translator
Device n u m b e r - - - - - - - - - - - - . I
(*)
T= TIL output
' - - - - - - - - - - Blank = CMOS
output
Blank = Standard
A= Fast
Fast _ _ _
(*) _ _ _ _ _ _ _ _ _ __J
B = Very
~
C = Super Fast
D = Ultra Fast
*Please refer to the corresponding data shoet for speed, package and output availability
FCT16XXX, 16XXXT (Double Density)
FCT1G 2
lOT 74
Temp. Range
Family
74 = Com'l: -40C to +85C
54 = Mil: -55C to + 125C
A
240
T
PV
Device Type Speed Output Package
~I.
Process
L=
Blank= High Drive
64mA 1-32mA (IOL IIOH)
2 = Balanced Drive
24m AI-24m A (IOl IIOH)
3 = 3.3 volts
4 = 3.3v to 5v Translator
Blank = Comm
B = Mil-STD-883, Class B
PV = Shrink Small Outline IC
E = CERPACK (Mil pkg only)
(*)
T=TIloutput
' - - - - - - - - - - B l a n k = CMOS output
Blank = Standard
(*)
A = Fast
'--_ _ _ _ _ _ _ _'-'-__ B = Very Fast
C = Super Fast
D = Ultra Fast
* Please refer to the corresponding data sheet for speed and output availability
Device number - - - - - - - - - - - - - '
1.4
ORDERING INFORMATION
II
NON-FCT DEVICES
lOT 7381L
20
Device Type
Speed
G
Package Temp Rangel Process
L'
'I .
'·
.'
Non-FC T deVice number----.J
Blank = Std _.:...:(*)_ _ _- - - 1
Blank = Com'l: DC to +70C
B = Mil-STD-883, Class B: -55C to +125C
D=
CERDIP
P=
Plastic DIP (PDIP)
J=
PLCC
L=
LCC
F=
Flat-Pack (FP)
(*)
L..-_ _ _ _--.;..~_ PQF = Plastic Quad r=lat-Pack
FF = Fine Pitch Flat-Pack
G=
PGA
C=
Sidebraze DIP
TC = Thin Sidebraze DIP
C=
Topbraze DIP
Y=
SOIC J-Bend (SOJ)
* Please refer to table below for speed and package availability
NON-FCT DEVICE REFERENCE TABLE
S~eed
Device
Commercial
Military
Package
39C10
B,C
B,C
CERDlP, PDIP, PLCC, LCC
FP, PLCC, PDIP, CERDIP
39C60
Std., -1, A, B
Std., ';"'1, A, B
49C402
Std. A B
Std. A B
FP PGA PLCC
49C410
Std., A
Std., A
PDIP SIDEBRAZE, PLCC, FP
49C460
Std.,
A.
B, C, D
Std., A. B, C, D
FP PGA. PLCC
49C465
Std., A
Std., A
PQF PGA
49C466
Std.
Std.
PQF PGA
7210L
25,35,45,55;65
30,40,55;65,75
FP, PGA. PDIP, PLCC, To~braze
7216L
20,25,35 45,55,65
25,3040,55;65,75
FP PGA. PDIP, PLCC, Topbraze
7217L
20,25,35,45,55,65
25,30,40,5565,75
FP PGA, PDIP, PLCC, Topbraze
73200L
10 12 15
12 15 20
73201L
10, 12, 15
12,15,20
73210
Std., A. B
Std.,
A. B
SOJ Thin-Sidebraze
73211
Std. A B
Std. A B
SOJ Thin-Sidebraze
7381L
20 25 30 40 55
25 30 35 45 65
PLCC PGA FF
7383L
20,25 30,40,55
25,30,35,45,65
PLCC, PGA, FF
73720
Std.
Std.
PQF, PLCC
1_4
,
PDIP PLCC Sidebraze
PDIP, PLCC, Sidebraze
2
lOT PACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION
4. A device speed identifier, when applicable, is either alpha
characters, such as "A" or "B", or numbers, such as 20 or
45. The speed units, depending on the product, are in
nanoseconds or megahertz.
5. A package identifier, composed of one or two characters.
The data sheet should be consulted to determine the
packages available and the package identifiers for that
particular product.
6. A temperature/process identifier. The product is available
in either the commercial or military temperature range,
processed to a commercial specification, or the product is
available in the military temperature range with full
compliance to MIL-STD-883. Many of lOT's products
have burn-in included as part of the standard commercial
process flow.
7. A special process identifier, composed of alpha characters,
is used for products which require radiation enhancement
(RE) or radiation tolerance (RT).
lOT's part number identifies the basic product, speed,
power, package(s) available, operating temperature and
processing grade. Each data sheet has a detailed description,
using the part number, for ordering the proper product for the
user's application. The part number is comprised of a series
of alpha-numeric characters:
1. An "lOT" corporate identifier for Integrated Device
Technology, Inc.
2. A basic device part number composed of alpha-numeric
characters.
3. A device power identifier, composed of one or two alpha
characters, is used to identify the power options. In most
cases, the following alpha characters are used:
"S" or "SA" is used for the standard product's power.
"L" or "LA" is used for lower power than the standard
product.
Example for Monolithic Devices:
lOT
XXX .. .xXX
xx
X..x
X... X
Special Process
Processffemperature*
Package*
Speed
Power
Device Type*
* Field Identifier Applicable To All Products
2507drw 01
ASSEMBLY LOCATION DESIGNATOR
MIL-STD-883C COMPLIANT DESIGNATOR
lOT uses various locations for assembly.· These are
identified by an alpha character in the last letter of the date
code marked on the package. Presently, the assembly
location alpha character is as follows:
. ,
A i.i Anam, Korea
I = USA
P = Penang, Malaysia
lOT ships military products which are compliant to the latest
revision ,of MIL-STO-883C. Such products are identified by a
"C" designation on the package. The location ofthis designator
is specified by internal documentation at lOT.
EXAMPLE FOR SUBSYSTEM MODULES
See Ordering Information (section 1.4), page 2.
1.5
TEST CIRCUITS AND WAVEFORMS
FCTXXX, FCTXXXT, FCT16XXXT - 5V FAMILIES
II
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
Open
All Other Tests
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
PULSE WIDTH
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
zxt
j
-
tsu~-~
TIMING ----_.1.,...--1--INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUSCONTzxtROL
PRESETCLEAR
CLOCK ENABLE
tsu
ETC.
-
-
3V
1.5V
OV
3V
1.5V
LOW-HIGH-LOW
PULSE
OV
_ 3V
1.5V
- OV
-
3V
1.5V
-
OV
HIGH-LOW-HIGH
PULSE
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
- - - - 3V
- - - 1.5V
SAME PHASE
INPUT TRANSITION
,..--~,+--
OUTPUT
DISABLE
-
~-,.+----
VOH
1.5V
VOL
OV
3.5V
VOL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
1.6
VOH
SWITCH
OPEN
OV
TEST CIRCUITS AND WAVEFORMS
FCT3XXX AND FCT163XXX - 3.3V FAMILY
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
~
v cc
6V
• Open
500Q
I-=
GND
Test
Switch
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
6V
GND
Open
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZouTol the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
I~~~~ vvT,
',.J ~..J~!IooO~ - r~v
~I-tsu..
ov
.TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
-
3V
1.5V
_
ETC.
-
SYNCHRONOUS CONX&;tTROL
PRESET
j)
CLEAR
tsu
CLOCK ENABLE
ETC.
-
LOW-HIGH-LOW
PULSE
OV
3V
1.5V
OV
HIGH-LOW-HIGH
PULSE
3V
10'V5V
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
3V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
OV
OV
~-~.-f-- VOH
OUTPUT
-
DISABLE
3V
1.5V
VOL
OPPOSITE PHASE
INPUT TRANSITION
VOL
3V
1.5V
OUTPUT
NORMALLY
HIGH _ _ _.
OV
1.6
VOH
OV
2
High-Speed CEMOS Logic Products -
Bus Interface Devices
FCT and FCT-T CEMOS families are the fastest in the industry
with maximum propagation delays as low as 4.1 ns.
2.
24mA balanced output drive with on-chip resistors for
internal bus and point to point driving.
• The FCT-Tfamily offers the lowest-power solution. No other logic
family uses less dynamic power, standby power, or static high or
low power.
3.
3.3V bus interface logic for systems with 3.3V regulated
supplies.
•
• The EDC (Error Detection and Correction) devices can detect
multiple errors as fast as 10ns and correct as fast as 14ns.
• The FBT BiCEMOS Memory Drivers with 25Q resistors reduce
overshoot and undershoot when driving CMOS RAMs.
•
• The new Double-Density bus interface family offers users significant board area savings, power savings, higher speeds, guaranteed low noise, and a choice of output drive characteristics.
Three configurations are available:
1.
lOT features a series of read-write buffers with 8-bit bidirectional
registers and 16-bit pipeline registers.
• The DSP Building Blocks are composed of 16-bit ALUs, Multipliers, and Multiplier-Accumulators with speeds as fast as 20ns.
Standard 64mA high drive device for bus and backplane
interface.
Part Number
Max. Speed (ns)
Mil.
Com'!.
Description
Typ.
Power
(mW)
Data
Book
Page
DOUBLE-DENSITY FAMILY
IDT54174FCT16240T/AT/CT
IDT54/74FCT162240T/AT/CT
16-Bit Buffer/Line Driver
4.7
4.3
0.01
5.1
5.1
IDT54/74FCT16244T/AT/CT
IDT54/74FCT162244T/AT/CT
IDT54/74FCT163244/A
16-Bit Buffer/Line Driver
4.6
4.1
0.01
5.2
5.2
7.1
4.5
4.1
0.01
5.3
5.3
7.2
5.1
4.2
0.006
5.4
5.4
7.3
6.2
5.2
0.006
5.5
5.5
7.4
IDT54/74FCT16245T/AT/CT
IDT54/74FCT162245T/AT/CT
IDT54/74FCT1632451A
IDT54/74FCT164245T
IDT54/74FCT16373T/AT/CT
IDT54/74FCT162373T/AT/CT
IDT54/74FCT163373/A
3.3V 16-Bit Buffer/Line Driver
16-Bit Bidirectional Transceivers
3.3V 16-Bit Bidi rectional Transceivers
Mixed Supply (3.3/5.0V) Translator
16-Bit Transparent Latches
7.9
3.3V 16-Bit Transparent Latches
16-Bit Register (3-State)
IDT54/74FCT16374T/ATlCT
IDT54/74FCT162374T/AT/CT
IDT54/74FCT163374/A
3.3V 16-Bit Register (3-State)
IDT54/74FCT16646T/AT/CT
IDT54/74FCT162646T/AT/CT
IDT54/74FCT1636461A
16-Bit Bus Transceiver/Registers
(3-State)
3.3V 16-Bit Bus Transceiver/Registers
6.0
5.4
0.006
5.9
5.9
IDT54/74FCT16500AT/CT
IDT54/74FCT162500AT/CT
18-Bit Registered Bus Transceiver
(3-State)
4.6
4.6
0.006
5.6
5.6
IDT54/7 4FCT16501 AT/CT
IDT54/7 4FCT162501 AT/CT
IDT54/74FCT163501/A
18-bit Registered Bus Transceiver
(3-State)
3.3V 18-Bit Registered Bus Transceiver
4.6
4.6
0.006
5.7
5.7
7.5
IDT54/74FCT16543T/AT/CT/DT 16-Bit Latched Transceiver
IDT54/74FCT162543T/AT/CT/DT
6.1
4.4
0.006
5.8
5.8
IDT54/74FCT16952T/AT/CT/DT 16-Bit Registered Transceivers
IDT54/74FCT162952T/AT/CT/DT
7.3
4.5
0.006
5.11
5.11
7.6
IDT54/74FCT16652T/AT/CT
IDT54/7 4FCT162652T/A T/CT
16-Bit Transceiver/Registers
6.0
5.4
0.006
5.10
5.10
IDT54/74FCT16823AT/BT/CT
IDT54/74FCT162823AT/BT/CT
18-Bit Bus Interface Registers
7.0
6.0
0.006
5.12
5.12
IDT54/7 4FCT16841 AT/BT/CT
20-Bit Transparent Latch
IDT54/7 4FCT162841 AT/BT/CT
6.3
5.5
0.006
5.14
5.14
IDT54/74FCT16827AT/BT/CT
20-Bit Buffers
IDT54/7 4FCT162827AT/BT/CT
5.0
4.4
0.006
5.13
5.13
1.7
II
High-Speed CEMOS Logic Products
Max. Speed (ns)
Mil.
Com'l.
Typ.
Power
,mWl
Data
Book
Pase
Part Number
FCT/FCT-T FAMILY
Descrletion
IDT29FCT52A1B/C
IDT29FCT52AT/BT/CT
Non-Inverting Octal Registered
Transceiver
7.3
6.3
1.0
6.26
6.1
IDT29FCT53A1B/C
IDT29FCT53AT/BT/CT
Inverting Octal Registered
Transceiver
7.3
6.3
1.0
6.26
6.1
IDT29FCT520AlB/C
IDT29FCT520AT/BT/CT/OT
Multilevel Pipeline Register
7.0
5.2
1.0
6.27
6.2
Octal Multilevel Pipeline
Register (level 1 replaced)
7.0
5.2
1.0
6.2
IDT49FCT805/A
Clock Driver w/Guaranteed Skew
6.8
5.8
1.0
6.28
IDT49FCT806/A
Inverting Clock Driver
w/Guaranteed Skew
6.8
5.8
1.0
6.28
6.0
5.1
1.0
6.29
6.3
OuaI1-of-4 Decoder
6.2
5.0
1.0
6.30
6.4
. IDT29FCT521AT/BT/CT/OT
. IDT54/74FCT138/AiC
IDT54174FCT138T/AT/CT
IOT54/74FCT139/AiC
IOT54/74FCT139T1AT/CT
1-of-8 Decoder
/'
<
IOT54/75FCT151T/AT/CT
8-lnput Multiplexer
6.2
5.6
1.0
6.5
IOT54/74FCT157T/AT/CT
Quad 2-lnput Multiplexer
5.0
4.3
1.0
6.6
IOT54/74FCT161/AiC
IDT54/74FCT161T/AT/CT
Synchronous Binary Counter
w/Synchronous Reset
6.3
5.8
1.0
6.31
6.7
IOT54/74FCT163/AlC
IOT54174FCT163T/AT/CT
Synchronous Binary Counter
w/Asynchronous Master Reset
6.3
5.8
1.0
6.31
6.7
IOT54/74FCT1821A
Carry Lookahead Generator
10.7
7.0
1.0
6.32
IOT54/74FCT191/A
IOT54/74FCT191T/AT
Up/Down Binary Counter
10.5
7.8
1.0
6.33
6.8
IOT54/74FCT193/A
IOT54/74FCT193T/AT
Up/Down Binary Counter
6.9
6.5
1.0
6.34
6.9
IOT54/74FCT240/AlC
IOT54/74FCT240T/AT/CT/OT
Inverting Octal Buffer/Line Driver
4.7
3.6
1.0
6.35
6.10
IOT54/74FCT241/AlC
IDT54/74FCT241T/AT/CT/DT
Inverting Octal Buffer/Line Driver
4.6
3.6
1.0
6.35
6.10
IOT54/74 FCT244/AiC
IOT54/74FCT244T/AT/CT/OT
IOT54/74FCT3244/A
Inverting Octal Buffer/Line Driver
4.6
3.6
1.0
6.35
6.10
7.7
4.5
3.8
1.0
6.36
6.11
7.8
3.3V Inverting Octal Buffer/Line Driver
Inverting Octal Bidirectional Transceiver
IOT54/74FCT245/AiC
IOT54/74FCT245T/AT/CT/OT
IDT54174FCT3245/A
3.3V Inverting Octal Buffer Transceiver
IOT54/74FCT251T/AT/CT
8-lnput Multiplexer with OE
6.2
5.6
1.0
6.5
IOT54/74FCT257T/AT/CT
Quad 2-lnput Multiplexer w/OE
5.0
4.3
1.0
6.6
IOT54/74FCT273/AiC
IOT54/74FCT273T/AT/CT
Octal 0 Flip-Flop with Reset
6.5
5.8
1.0
6.37
6.12
IOT5417 4FCT299/AlC
IOT54/74FCT299/AT/CT
Octal Universal Shift Register
w/Common Parallel I/O Pins
7.5
6.5
1.0
6.38
6.13·
IOT54174FCT373/AiC
IOT54/74FCT373T/AT/CT/OT
Octal Transparent Latch
5.1
3.8
1.0
6.39
6.14
IOT54174FCT374/AiC
IOT54/74FCT37 4T/AT/CT/OT
Octal 0 Register
6.2
4.2
1.0
6.40
6.15
IDT54/74FCT3771AlC
IOT54/74FCT377T/AT/CT
Octal D Flip-Flop w/Clock Enable
5.5
5.2
1.0
6.41
6.16
IOT54/74FCT399/AiC
IOT54/74FCT399T/AT/CT
Quad Dual-Port Register
6.6
6.1
7.0
6.42
6.17
1.7
2
Hiah-Seeed CEMOS Loalc Products
Part Number
IDT54/74FCT5211A1B/C
IDT54/74FCT521T/AT/BT/CT
Max. Speed (ns)
Com".
Mil.
4.5
5.1
Oescrletlon
8-Bit Identity Comparator
Typ.
Power
!mW!
1.0
Data
Book
Pase
6.43
6.18
IDT54/74FCT5331A1C
IDT54/74FCT533T1AT/CT
Inverting Octal Transparent
Latch w/3-State
5.1
4.2
1.0
6.39
6.14
IDT54/74FCT5341A1C
IDT54/74FCT534T/AT/CT
Inverting Octal 0 Register
6.2
5.2
1.0
w/3State
6.40
6.15
IDT54/74FCT540lAlC
IDT54/74FCT540T/AT/CT
Inverting Octal Buffer/Line Driver
4.7
4.3
1.0
6.35
6.10
IDT54/74FCT541 lAIC
IDT54/74FCT541 T/A TlCT
Non-Inverting Octal Buffer/Line
Driver
4.7
4.3
1.0
6.35
6.10
IDT54/74FCT5431A1C
IDT54/74FCT543T/AT/CT/DT
Non-Inverting Octal Latched
Transceiver
6.1
4.4
1.0
6.44
6.19
IDT54174FCT5731AlC
Octal Transparent Latch
5.1
3.8
1.0
6.39
6.14
Octal 0 Register w/3-State
6.2
4.2
1.0
6.40
6.15
Inverting Octal Bus Transceiver
5.1
4.5
1.0
6.21
Non-Inverting Octal Bus
Transceiver w/Open Drain
12.5
12.0
1.0
6.22
Inverting Octal Bus Transceiver
12.5
12.0
1.0
6.22
IDT54/74FCT573T/ATlCT/DT
IDT54/74FCT5741A1C
IDT54/75FCT574T/AT/CT/DT
IDT54174FCT620T/AT/CT
w/3-State
IDT54174FCT621T/AT
IDT54/74/FCT622T/AT
w/Open Drain
IDT54/74FCT623T/AT/CT
Non-Inverting Octal Bus
Transceiver w/3-State
5.4
4.8
1.0
6.21
IDT54/74FCT640lAlC
IDT54/74FCT640T/AT/CT
Inverting Octal Transceiver
4.7
4.4
1.0
6.36
6.11
IDT54174FCT6451A1C
Non-Inverting Bidirectional
Transceiver
4.5
3.8
1.0
6.36
6.11
IDT54/74FCT6461A1C
IDT54/74FCT646TIAT/CT/DT
Octal Transceiver/Register
6.0
4.4
1.0
6.45
6.20
IDT54/74FCT648T/AT/CT
Octal Transceiver/Register
6.0
5.4
1.0
6.20
IDT54/74FCT651T1ATlCT
Inverting Octal Registered
Transceiver
6.0
5.4
1.0
6.20
IDT54/74FCT652T/AT/CT/DT
Non-Inverting Octal Registered
Transceiver
6.0
4.4
1.0
6.20
IDT54/74FCT821 AlBIC
1O-Bit Non-Inverting Register
IDT54/74FCT821 A T/BT/CT/DT
7.0
4.2
1.0
6.46
6.23
IDT54/74FCT823A1B1C
7.0
5.0
1.0
6.46
6.23
IDT54174FCT645TIAT/CT/DT
9-Bit Non-Inverting Register
IDT54174FCT823AT/BT/CT/DT
IDT54/74FCT824A1B1C
9-Bit Inverting Register
7.0
6.0
1.0
6.46
IDT54/74FCT825A1B1C
IDT54/74FCT825AT/BT/CT
8-Bit NOI1-lnverting Register
7.0
6.0
1.0
6.46
6.23
IDT54/74FCT826AT/BT/CT
8-Bit Inverting Register w/Multiple Enable
7.0
6.0
1.0
6.23
IDT54/74 FCT827AlBIC
10-Bit Non-Inverting Buffer
5.0
3.8
1.0
6.47
6.24
6.24
IDT54/74FCT827AT/BT/CT/DT
IDT54174FCT828AT/BT/CT
10-Bit Inverting Register
5.0
4.4
1.0
IDT54/74FCT833A1B
8-Bit Transceiver w/Parity
10.0
7.0
1.0
6.48
IDT54174FCT841 AlBIC
10-Bit Non-Inverting Latch
IDT54174FCT841 AT/BT/CT/DT
6.3
4.2
1.0
6.49
6.25
IDT54/74FCT843A1B1C
IDT54/74FCT843AT/BT/CT
6.3
5.5
1.0
6.49
6.25
9-Bit Non-Inverting Latch
1.7
3
High-Speed CEMOS Logic Products
Part Number
Descrletlon
Max. Speed (ns)
Com'l.
Mil.
IDT54/74FCT844A1B/C
9-Bit Inverting Latch
6.3
5.5
Typ.
Power
,mW~
1.0
IDT54/74FCT845A1B/C
IDT54/74FCT845AT/BT/CT
8·Bit Non-Inverting Latch
6.3
5.5
1.0
Data
Book
Page
6.49
6.25
6.49
IDT54/74FCT861A1B
1a-Bit Non-Inverting Transceiver
6.5
6.0
1.0
6.50
IDT54/74FCT863A1B
9-Bit Non-Inverting Transceiver
6.5
6.0
1.0
6.50
IDT54/74FCT864A1B
9-Bit Invertina Transceiver
6.5
6.0
1.0
6.50
IDT54/74FBT2240/A
BiCEMOS Inv. Octal Memory Driver
5.1
4.8
1.0
6.51
IDT54/74FBT2244/A
BiCEMOS Non-Inv. Memory Driver
5.1
4.8
1.0
6.52
IDT54/74FBT2373/A
BiCEMOS Octal Transparent
Latch Drivers
5.6
5.2
1.0
6.53
IDT54/74FBT2827 AlB
BiCEMOS Non-Inverting 10-Bit
Memory Driver
6.5
5.0
1.0
·6.54
IDT54/74FBT2828A1B
BiCEMOS Inv. 1a-Bit Memory Driver
6.5
5.5
1.0
6.54
IDT54/7 4FBT2841 AlB
BiCEMOS Non-Invertina 10-Bit Latch
7.5
6.5
1.0
6.55
Typ.
Power
,mW~
Data
Book
Paa e
50
8.2
FBT FAMILY
Part Number
Max. Speed (ns)
Com'l.
Descrletlon
MICROSLICETM PRODUCTS
= 47ns
= 37ns
= 28ns
IDT49C402
IDT49C402A
IDT49C402B
16-Bit JlP Slice. quad 2901
with 8 additional destination
fUnctions and 64 x 16 register file
capacity - superset of Am29C1 01.
CY7C91 01. WS 159016
A.B addr to Y
A.B addr to Y
A.B addrto Y
IDT39C10B
IDT39C10C
12-bit Sequencer with 33-deep stack
- replaces AM291 0/A. CY7C910
D to Y = 20ns
D to Y = 12ns
175
8.1
IDT49C410
IDT49C410A
16-bit Sequencer with 33-deep stack
address u~ to 64K microcode
D to Y
D to Y
= 20ns
= 12ns
175
8.3
Typ.
Power
,mW~
Data
Book
Page
Part Number
Max. Speed (ns)
Com'l.
Mil.
Descrietion
DSP BUILDING BLOCKS
IDT7381 L20/25/30/40/55
16-bit Cascadable ALU
(replaces Logic Devices' L4C381)
25
20
10
8.6
IDT7383L20/25/30/40/55
16-bit Cascadable ALU
(32 instructions)
25
20
10
8.6
IDT7210L25/35/45/55/65
16 x 16-bit with 35-bit output.
replaces TDC1010J
30
25
20
8.4
IDT7216L20/25/35/45/55/65
16 x 16-bit. replaces Am29516
25
20
20
8.5
IDT7217L20/25/35/45/55/65
16 x 16-bit with Single-Clock
Architecture. reelaces Am29517
25
20
20
8.5
READ-WRITE BUFFERS AND BUS MULTIPLEXERS
73200L 1OIL 121L 15
16-bit 8-level-deep Pipeline
Register; replaces four Am29520s
12
10
10
8.7
73201 L 1OIL 121L15
16-bit 7 -level-deep Pipeline
Register with pass-through mode
12
10
10
8.7
73210/AiB
8-bit Bidirectional Registers with
parity; one register and one latch
from BtoA
7.5
6.0
0.1
B.8
1.7
4
High-Speed CEMOS Logic Products
Typ.
Power
(mW)
Data
Book
Page
6.0
0.1
8.8
7.5
1.0
8.9
Max. Speed (ns)
Com'l.
Mil.
Part Number
Description
73211/AiB
8·bit Bidirectional Registers with
parity; two latches from B to A
73720
16-Bit 3-Port Latched Bus Exchanger
7.5
Detect Time
ERROR DETECTION AND CORRECTION
IDT39C60
IDT39C60·1
IDT39C60A
IDT39C60B
16·bit Cascadable EDC
Replaces Am2960, -1, A; N2960,
MC74F2960, -1, A
36
28
24
22
32
25
20
18
15
8.10
8.10
8.10
8.10
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
32-bit Cascadable EDC
Replaces Am29C660.
44
33
28
21
16
40
30
25
16
12
15
8.11
8.11
8.11
8.11
8.11
IDT49C4651A
32-bit Flow-thruEDCno-two separate
bidirectional 32-bit buses; expandable
to 64-bit, 144-pin PGA.
20
15
25
8.12
IDT49C466
64-bit Flow-thruEDC-two separate
bidirectional 64-bit busesj 208-pin PGA
20
15
8.13
1.7
5
TECHNOLOGY AND CAPABILITIES
fI
IDT... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor
industry today. A new technology is rapidly displacing older
NMOS and bipolar technologies as the workhorse of the '80s
and beyond. Thattechnology is high-speed CMOS. Integrated
Device Technology, a company totally predicated on and
dedicated to implementing high-performance CMOS products,
is on the leading edge of this dramatic change.
Beginning with the introduction of the industry's fastest
CMOS 2K x 8 static RAM, lOT has grown into a company with
multiple divisions producing a wide range of high-speed
CMOS circuits that are, in almost every case, the fastest
available. These advanced products are produced with lOT's
proprietary CEMOSTM technology, a twin-well, dry-etched,
stepper-aligned process utilizing progressively smaller
dimensions.
From inception, lOT's product strategy has been to apply
the advantages of its extremely fast CEMOS technology to
produce the integrated circuit elements required to implement
high-performance digital systems. lOT's goal is to provide the
circuits necessary to create systems which are far superior to
previous generations in performance, reliability, cost, weight,
and size. Many of the company's innovative product designs
offer higher levels of integration, advanced architectures,
higher density packaging and system enhancement features
that are establishing tomorrow's industry standards. The
company is com mitted to providing its customers with an everexpanding series of these high-speed, lower-power ICsolutions
to system design needs.
lOT's commitment, however, extends beyond state-of-theart technology and advanced products to providing the highest
2.1
level of customer service and satisfaction in the industry.
Manufacturing products to exacting quality standards that
provide excellent, long-term reliability is given the same level
of importance and priority as device performance. lOT is also
dedicated to delivering these high-quality advanced products
on time. The company would like to be known not only for its
technological capabilities, but also for providing its customers
with quick, responsive, and courteous service.
lOT's product families are available in both commercial and
military grades. As a bonus, commercial customers obtain the
benefits of military processing disciplines, established to meet
or exceed the stringent criteria of the applicable military
specifications.
lOT is the leading U.S. supplier of high-speed CMOS
circuits. The company's high-performance fast SRAM , FCT
logic, high-density modules, FIFOs, multi-port memories,
BiCEMOSTM ECl 1/0 memories, RISC SubSystems, and the
32- and 64-bit RISC microprocessor families complement
each other to provide high-speed CMOS solutions for a wide
range of applications and systems.
Dedicated to maintaining its leadership position as a stateof-the-art IC manufacturer, lOT will continue to focus on
maintaining its technology edge as well as developing a
broader range of innovative products. New products and
speed enhancements are continuously being added to each
of the existing product families, and additional product families
are being introduced. Contact your lOT field representative or
factory marketing engineer for information on the most current
product offerings. If you're building state-of-the-art equipment,
lOT wants to help you solve your design problems.
lOT MILITARY AND OESC-SMO PROGRAM
lOT is a leading supplier of military, high-speed CMOS
circuits. The company's high-performance Static RAMs, FCT
logic Family, Complex logic (ClP), FIFOs, Specialty
Memories (SMP), ECl 1/0 SiCMOS Memories, 32-bit RISC
Microprocessor, RISC Subsystems and high-density
Subsystems Modules product lines complement each otherto
provide high-speed CMOS solutions to a wide range of
military applications and systems. Most of these product lines
offer Class S products which are fully compliant to the latest
revision of Mll-STO-883, Paragraph 1.2.1. In addition, lOT
offers Radiation Tolerant (RT), as well as Radiation Enhanced
(RE), products.
lOT has an active program with the Defense Electronic
Supply Center (OESC) to list all of lOT's military compliant
devices on Standard Military Drawings (SMO). The SMO
program allows standardization of militarized products and
reduction of the proliferation of non-standard source control
drawings. This program will go far toward reducing the need
for each defense contractor to make separate specification
control drawings for purchased parts. lOT plans to have
SMOs for many of its product offerings. Presently, lOT has 88
devices which are listed or pending listing. The devices are
from lOT's SRAM, FCT Logic family, Complex Logic (CLP),
FIFOs and Specialty Memories (SMP) product families. lOT
expects to add another 20 devices to the SMO program in the
near future. Users should contact either lOT or OESC for
current status of products in the SMO program.
SMO
SMO
SMO
SRAM
lOT
LOGIC
lOT
CLP
lOT
84036/E
5962-88740
841321B
5962-86015/A
5962-86859
5962-86705/D
5962-85525/B
5962-885521B
5962-886621A
5962-88611/A
5962-88681/A
5962-88545
5962-89891
5962-89892
5962-89690
5962-38294/B
5962-89692
5962-89712
6116
6116LA
6167
7187
6198/719817188
6168
7164
71256L
712565
71682L
712585
71258L
7198
6198
6116
7164
7188
71982
39C10B & C
49C460AlBlC
39C60A
49C410
7216L
7217L
7210L
54FCT843A1B1C
54FCT193/A
29 FCT52A1B/C
lOT
5962-86875/B
5962-87002lC
5962-88610/A
5962-88665/A
713017140
713217142
7133S!71435
7133U7143L
FIFO
lOT
5962-87531
5962-86846/A
5962-88669
5962-89568
5962-89536
5962-89863
5962-89523
5962-89666
5962-89942
5962-89943
5962-89567
7201 LA
72404
72035
7204L
7202L
72015
72403L
7200L
72103L
72104L
7203L
54 FCT244/A
54 FCT245/A
54 FCT299/A
54 FCT373/A
54 FCT374/A
54 FCT377/A
54FCT138/A
54 FCT240/A
54 FCT273/A
54FCT861AlB
54 FCT827A1B
54FCT841AlB
54FCT821AlB
54FCT521/A
54FCT161/A
54 FCT573/A
54FCT823A1B
54FCT163/A
54 FCT825A1B
54 FCT863A1B
29FCT520AlB
54 FCT646
54FCT139/A
54FCT824A1B
54 FCT533/A
54FCT1821A
54 FCT645A1B
54 FCT640AlB
54 FCT534/A
54 FCT540/A
54FCT541/A
54FCT191/A
54FCT241/A
54 FCT399/A
54 FCT574/A
54FCT833A1B
54 FCT845A1B
54 FCT543/A
5962-8770BlA
5962-88533/A
5962-88613/A
5962-88643/A
5962-86893
5962-87686
5962-88733/A
5962-89758
5962-90669
5962-90901
SMP
5962-87630/B
5962-87629/C
5962-868621B
5962-87644/A
5962-87628/C
5962-87627/B
5962-87654/A
5962-87655/A
5962-876561A
5962-89533
5962-89506
5962-88575
5962-88608
5962-88543/A
5962-88640/A
5962-88639/A
5962-88656
5962-88657/A
5962-88674
5962-88661
5962-88736/A
5962-88775
5962-89508
5962-89665
5962-88651
5962-88652
5962-88653
5962-88654
5962-88655
5962-89767
5962-89766
5962-89733/A
5962-89732
5962-89652
5962-89513
5962-89731
5962-88675
5962-89730
/
2509 tbl 01
2.2
RADIATION HARDENED TECHNOLOGY
lOT manufactures and supplies radiation hardened products
for military/aerospace applications. Utilizing special processing
and starting materials, lOT's radiation hardened devices survive
in hostile radiation environments. In Total Dose, Dose Rate,
and environments where single event upset is of concern, lOT
products are designed to continue functioning without loss of
performance. lOT can supply all its products on these
processes. Total Dose radiation testing is performed in-house
2.3
on an ARACOR X-Ray system. External facilities are utilized
for device research on gamma cell, LlNAC and other radiation
equipment. lOT has an on-going research and development
program for improving radiation handling capabilities (See
"lOT Radiation ToleranVEnhanced Products for Radiation
Environments" in Section 3) of lOT products/processes.
fI
lOT LEADING EDGE CEMOS TECHNOLOGY
HIGH-PERFORMANCE CEMOS
From lOT's beginnings in 1980, it has had a belief in and a
commitment to CMOS. The company developed a highperformance version of CMOS, called enhanced CMOS
(CEMOS), that allows the design and manufacture of leadingedge components. It incorporates the best characteristics of
traditional CMOS, including low power, high noise immunity
CEMOS I
and wide operating temperature range; it also achieves speed
and output drive equal or superior to bipolar Schottky TTL.
The last decade has seen development and production of four
"generations" of lOT's CEMOS technology with process
improvements which have reduced lOT's electrical effective
(Left) gate lengths by more than 50 percent from 1.3 microns
(millionths of a meter) in 1981 to 0.6 microns in 1989.
CEMOS II
A
C
CEMOS III
CEMOS V
CEMOS VI
Calendar Year
1981
1983
1985
1987
1989
1990
Drawn
Feature Size
2.5J.1
1.7J.1
1.3J.1
1.2J.1
1.0J.1
0.8J.1
Left
Basic
Proces
Enhancements
1.3J.1
1.1 J.1
O.9J.1
Dual-well.
Wet Etch,
Projection
Aligned
Dry Etch.
Shrink.
Spacer
Stepper
O.8J.1
Silicide,
BPSG.
BiCEMOS I
O.6J.1
O.45J.1
BiCEMOS II
BiCEMOS III
2514 drw 01
CEMOS IV = CEMOS III - scaled process optimized for high-speed logic.
Figure 1.
Continual advancement of CEMOS technology allows lOT
to implement progressively higher levels of integration and
achieve increasingly faster speeds maintaining the company's
established position as the leader in high-speed CMOS
integrated circuits. In addition, the fundamental process
technology has been extended to add bipolar elements to the
CEMOS platform. lOT's BiCEMOS process combines the
ultra-high speeds of bipolar devices with the lower power and
cost of CMOS, allowing us to build even faster components
than straight CMOS at a slightly higher cost.
CEMOS I
CEMOS II
CEMOS III
1981
1983
1987
SEM photos (miniaturization)
CEMOS V CEMOS VI
1989
1990
2514 drw 02
Figure 2. FlHeen-Hundred·Power Magnification Scanning Electron
Microscope (SEM) Photos of the Four Generations of lOTs CEMOS
Technology
2.4
Potential
O
+rITi_
-
G~
1
G
.... 1
1
-3V
G'
G
fI
NMOS
Potential
+5V
CEMOSTM
2514drw04
2514 drw 03
Figure 3. lOT CEMOS Device Cross Section
Figure 4. lOT CEMOS Bullt·ln High Alpha Particle Immunity
Input/Output Pad
ALPHA PARTICLES
1,000
lII-
Random alpha particles can cause memory cells to
temporarily lose their contents or suffer a "soft error." Traveling
with high energy levels, alpha particles penetrate deep into an
integrated chip. As they burrow into the silicon, they leave a
trail of free electron-hole pairs in their wake.
The cause of alpha particles is well documented and
understood in the industry. lOT has considered various
techniques to protectthe cells from this hazardous occurrence.
These techniques include dual-well structures (Figures 3 and
4) and a polymeric compound for die coating. Presently, a
polymericcompoundisusedinmanyofIDT'sSRAMs;however,
the specific techniques used may vary and change from one
device generation to the next as the industry and lOT improve
the alpha particle protection technology. '
n-Substrate
i1fV--J\
~
w_
(a)
Section A-A
~
\
lI-,
l-
.~~
III-
tro.
I~
1\
I~
.~
'.
01234567
(b) Collector Supply Voltage Vee (V)
Typieal~.
2514 drw 05
Figure 5. lOT CEMOS Latchup Suppression
LATCHUP IMMUNITY,
A combination of careful design layout, selective use of
guard rings and proprietary techniques have resulted in virtual
elimination of latchup problems often associated with older
CMOS processes (Figure 5). The use of NPN and N-channel
lID devices eliminates hole injection latchup. Double guard
ring structures are utilized on all input and output circuits to
absorb injected electrons. These effectively cut off the current
paths into the internal circuits to essentially isolate lID circuits.
Compared to older CMOS processes which exhibit latchup
characteristics with trigger currents from 10-20mA, lOT
products inhibit latchup at trigger currents substantially greater
than this.
2.4
2
SURFACE MOUNT TECHNOLOGY
AND
IDT'S MODULE PRODUCTS
Requirements for circuit area reduction, utilizing the most
efficient and compact component placement possible and the
needs of production manufacturing for electronics assemblies
are the driving forces behind the advancement of circuit-board
assembly technologies. These needs are closely associated
with the advances being made in surface mount devices
(SMO) and surface mount technology (SMT) itself. Yet, there
are two major issues with SMT in production manufacturing of
electronic assemblies: high capital expenditures and complexity of testing.
The capital expenditure required to convert to efficient
production using SMT is still too high for the majority of
electronics companies, regardless of the 20-60% increase in
the board densities which SMT can bring. Because of this high
barrier to entry, we will continue to see a large market segment
[large even compared to the exploding SMT market] using
traditional through-hole packages (i.e. DIPs, PGAs, etc) and
assembly techniques. How can these types of companies
take advantage of SMO and SMT? Let someone else, such
as IDT, do it for them by investing time and money in SMT and
then in return offer through-hole products utilizing SMT processes. Products which fit this description are mUlti-chip
modules, consisting of SMT assembled SMOs on a throughhole type substrate. Modules enable companies to enjoy SMT
density advantages and traditional package options without
the expensive startup costs required to do SMT in-house.
Although subcontracting this type of work to an assembly
house is an alternative, there still is the other issue of testing,
an area where many contract assembly operations fall short
of IDT's capability and experience. Prerequisites for adequate module testing sophisticated high-performance parametric testers, customized test fixtures, and most importantly the experience to tests today's complex electronic
devices. Companies can therefore take advantage of lOT's
experience in testing and manufacturing high-performance
CMOS multi-chip modules.
At lOT, SMO components are electrically tested, environmentally screened, and performance selected for each lOT
module. All modules are 100% tested as if they are a separate
functional component and are guaranteed to meet all specified parameters at the module output without the customer
having to understand the modules' internal workings.
2.5
Other added benefits companies get by using lOT's CMOS
module products are:
1) a wide variety of high-performance, through-hole products utilizing SMO packaged components,
2) fast speeds compared with NMOS based products,
3) low power consumption compared with bipolar technologies, and
4) low cost manufacturability compared with GaAs-based
products.
lOT has recognized the problems of SMT and began
offering CMOS modules as part of its standard product portfolio. lOT modules combine the advantages of:
1) the low power characteristics of lOT's GEMOSTM and
BiCEMOSTM products,
2) the density advantages of first class SMO components
including those from lOT's components divisions, and
3) experience in system level design, manufacturing, and
testing with its own in-house SMT operation.
lOT currently has two divisions (Subsystems and RISC
Subsystems) dedicated to the development of module products ranging from simple memory modules to complex VME
sized application specific modules to full system-level CPU
boards. These modules have surface mount devices assembled on both sides of either a multi-layer glass filled epoxy
(FR-4) or a multi-layer co-fired ceramic substrate. Assembled
modules come available in industry standard through-hole
packages and other space-saving module packages. Industry proven vapor-phase or IR reflow techniques are used to
solder the SMOs to the substrate during the assembly process. Because of our affiliation with lOT's experienced semiconductor manufacturing divisions, we thoroughly understand and therefore test all modules to the applicable datasheet specifications and customer requirements.
Thus, lOT is able to offer today's electronic design engineers a unique solution for their "need-more-for-Iess"
problem.modules. These high speed, high performance
products offer the density advantages of SMO and SMT, the
added benefit of low power CMOS technology, and throughhole packaged electronics without the high cost of doing it inhouse.
STATE-OF-THE-ART FACILITIES AND CAPABILITIES
Integrated Device Technology is headquartered in Santa
Clara, California-the heart of "Silicon Valley." The company's
operations are housed in six facilities totaling over 500,000
square feet. These facilities house all aspects of business
from research and development to design, wafer fabrication,
assembly, environmental screening, test, and administration.
In-house capabilities include scanning electron microscope
(SEM) evaluation, particle impact noise detection (PIND),
plastic and hermetic packaging, military and commercial
testing, burn-in,lifetest, and a full complement of environmental
screening equipment.
The over-200,OOO-square-foot corporate headquarters
campus is composed of three buildings. The largest facility on
this site is a 100,000 square foot, two-building complex. The
first building, a 60,OOO-square-foot facility, is dedicated to the
Standard logic and RISC Microprocessor product lines, as
well as hermetic and plastic package assembly, logic products'
test, burn-in, mark, QA, and a reliability/failure analysis lab.
lOT's Packaging and Assembly Process Development
teams are located here. To keep pace with the development
of new products and to enhance the lOT philosophy of
"innovation," these teams have ultra-modern, integrated and
correspondingly sophisticated equipment and environments
at their disposal. All manufacturing is completed in dedicated
clean room areas (Class 10K minimum), with all preseal
operations accomplished under Class 100 laminar flow hoods.
Development of assembly materials, processes and
equipment is accomplished under a fully operational production
environment to ensure reliability and repeatable product. The
Hermetic Manufacturing and Process Development team is
currently producing custom products to the strict requirements
ofMll-STD-883. The fully automated plastic facility is currently
producing high volumes of USA-manufactured product, while
developing state-of-the-art surface-mount technology
patterned after Mll-STD-883.
Thesecond building ofthe complex houses sales, marketing,
finance, MIS, and Northwest Area Sales.
The RISC Subsystems Division is located across from the
two-building complex in a 50,OOO-square-foot facility. Also
located at this facility are Quality Assurance and wafer
fabrication services. Administrative services, Human
Resources, International Planning, Shipping and Receiving
departments are also housed in this facility.
2.6
lOT's largest and newest facility, opened in 1990 in San
Jose, California, is a mUlti-purpose 150,OOO-square-foot, ultramodern technology development center. This facility houses
a 25,000 square foot, combined Class 1 (a maximum of one
particle-per-cubic-foot of 0.2 micron or larger), sub-half-micron
R&D fabrication facility and a wafer fabrication area. This fab
supports both production volumes of lOT products, including
some next-generation SRAMs, and the R&D efforts of the
technology development staff. Technology developm ent efforts
targeted for the center include advanced silicon processing
and wafer fabrication techniques. A test area to support both
production and research is located on-site. The building is
also the home of the FIFO, ECl, and Subsystems product
lines.
lOT's second largest facility is located in Salinas, California,
about an hour south of Santa Clara. This 95,000-square-foot
facility, located on 14 acres, houses the Static RAM Division
and Specialty Memory product line. Constructed in 1985, this
facility contains an ultra-modern 25,000-square-foot highvolume wafer fabrication area measured at Class 2-to-3 (a
maximum of 2 to 3 particles-per-cubic-foot of 0.2 micron or
larger) clean room conditions. Careful design and construction
of this fabrication area created a clean room environment far
beyond the 1985 average for U.S. fab areas. This made
possible the production of large volumes of high-density
submicron geometry, fast static RAMs. Thisfacility also houses
shipping areas for lOT's leadership family of CMOS static
RAMs. This site can expand to accommodate a 250,000square-foot complex.
To extend our capabilities while maintaining strict control of
our processes, lOT has an operational Assembly and Test
facility located in Penang, Malaysia. This facility assembles
product to U.S. standards, with all assemblies done under
laminar flow conditions (Class 100) until the silicon is encased
in its final packaging. All products in this facility are
manufactured to the quality control requirements of Mil-STD883.
All of lOT's facilities are aimed at increasing our
manufacturing productivity to supply ever-larger volumes of
high-performance, cost-effective, leadership CMOS products.
SUPERIOR QUALITY AND RELIABILITY
Maintaining the highest standards of quality in the industry
on all products is the basis of Integrated Device Technology's
manufacturing systems and procedures. From inception,
quality and reliability are built into all of lOT's products. Quality
is "designed in" at every stage of manufacturing - as opposed
to being "tested-in" later - in order to ensure impeccable
performance.
.
Dedicated commitment to fine workmanship, along with
development of rigid controls throughout wafer fab, device
assembly and electrical test, create inherently reliable products.
Incoming materials are subjected to careful inspections. Quality
monitors, or inspections, are performed throughout the
manufacturing flow.
lOT military grade monolithic hermetic products are designed
to meet or exceed the demanding Class B reliability levels of
MIL-STD-883 and MIL-M-38510, as defined by Paragraph
1.2.1 of MIL-STD-883.
Product flow and test procedures for all monolithic hermetic
military grade products are in accordance with the latest
revision and notice of MIL-STD-883. State-of-the-art production
techniques and computer-based test procedures are coupled
with tight controls and inspections to ensure that products
meet the requirements for 100% screening. Routine quality
conformance lot testing is performed as defined in MIL-STD883, Methods 5004 and 5005.
For lOT module products, screening of the fully assembled
substrates is performed, in addition to the monolithic level
screening, to assure package integrity and mechanical
reliability. All modules receive 100% electrical tests (DC,
functional and dynamic switching) to ensure. compliance with
the "subsystem" specifications.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, lOT
ensures that com mercial, industrial and military grade p rodu cts
consistently meet customer requirements for quality, reliability
and performance.
.
SPECIAL PROGRAMS
Class S. lOT also has all manufacturing, screening and
test capabilities in-house (except X-ray and some Group 0
tests) to perform complete Class S processing per MIL-STD883 on all lOT products and has supplied Class S products on
several programs.
Radiation Hardened. lOT has developed and supplied
several levels of radiation hardened products for military!
aerospace applications to perform at various levels of dose
rate, total dose, single event upset (SEU), upset and latchup.
lOT products maintain nearly their same high-performance
levels built to these special process requirements. The
company has in-house radiation testing capability used both
in process development and testing of deliverable product.
lOT also has a separate group within the company dedicated
to supplying products for radiation hardened applications and
to continue research and development of process and products
to further improve radiation hardening capabilities.
2.7
QUALITY AND RELIABILITY
II
QSP-QUALlTY, SERVICE AND PERFORMANCE'
Quality from the beginning, is the foundation for lOT's
commitment to supply consistently high-quality products to
our customers. lOT's quality commitment is embodied in its all
pervasive Continuous Quality Improvement (CQI) process.
Everyone who influences the quality of the product-from the
designer to the shipping clerk-is committed to constantly
improving the quality of their actions.
lOT QUALITY PHILOSOPHY
liTo make quantitative constant improvement in the quality
of our actions that result in the supply of leadership products
in conformance to the requirements of our customers."
lOT's ASSURANCE STRATEGY FOR CQI
Measurable standards are essential to the success of CQI.
All the processes contributing to the final quality of the product
need to be monitored, measured and improved upon through
the use of statistical tools.
DEVELOPMENT
I
I
ASSEMBLY
I
Productivity Improvement
Using constant improvement teams made up' from
employees at all levels of the organization.
Leadership
Focusing on quality as a key business parameter and
strategic strength.
'
Total Employee Participation
Incorporating the CQI process into the lor Corporate
Culture.
People Excellence ,
'
Committing to growing, motivating and retaining people
through training, goal setting, performance measurement
and review.
TEST
I
SHIP
Our customers receive the benefit of our optimized systems.
Installed to enhance quality and reliability, these systems
provide accurate and timely reporting on the effectiveness of
manufacturing controls and the reliability and quality
performance of lOT products and services.
ORDER ENTRY
I
PRODUCTION CONTROL
SERVICE FLOW
Documentation
Documenting and training in policies, procedures,
measurement techniques. and updating through
characterization! capability studies.
Customer Service
Supporting the customer, as a partner, through
performance review and pro~active problem solving.
FAB
PRODUCT FLOW
Standardization
Implementing policies, procedures and measurement
techniques that are common across different operational
areas.
'
I
SHIPPING
I
CUSTOMER SUPPORT
These systems and controls concentrate on CQ I by focusing
on the following key elements:
Statistical Techniques
Using statistical techniques, including Statistical Process
Control (SPC) to determine whether the product!
processes are under control.
3.1
PRODUCT FLOW
Product quality starts here., IDT has mechanisms 'an'd
procedures in place that monitor and control the quality of our
development activities. From the calibration of design capture
libraries 'through process technology and product
characterization that establish, whether the performance,
ratings and reliability criteria have been met. This includes
failure analysis of parts that will improve the prototype product.
Atthe pre-production stage once again in-house qualification
tests assure the quality and reliability of the product. All
specifications and manufacturing flows are established and
personnel trained before the product is placed into production.
Manufacturing
To accomplish CQI during the manufacturing stage, control
items are determined for major manufacturing conditions.
Data is gathered and statistical techniques are used to control
specific manufacturing processes that affect the quality of the
product.
II
In-process and final inspections are fed back to earlier
processes to improve product quality. All product is burnedin (where applicable) before 100% inspection of electrical
characteristics takes place.
Products which pass final inspection are then subject to
Quality Assurance and Reliability Tests. This data is used to
improve manufacturing processes and provide reliability
predictions of field applications.
Inventory and Shipping
Controls in shipping focus on ensuring parts are identified
and packaged correctly. Care is also taken to see that the
correct paperwork is present and the product being shipped
was processed correctly.
SERVICE FLOW
Quality not only applies to the product but to the quality-ofservice we give our customers. Service is also constantly
monitored for improvement.
Order Procedures
Customer Support
IDT has a worldwide network of sales offices and Technical
Development Centers. These provide local customer support
on business transactions, and in addition, support customers
on applications information, technical services, benchmarking
of hardware solutions, and demonstration of various
Development Workstations.
'
The key to CQI is the timely resolution of defects and
implementation of the corrective actions. This is no more
important than when product failures are found by a customer.
When failures arefound atthe customer's incoming inspection,
in the production line, or the field application, the Division
Quality Assurance group is the focal point for the investigation
of the cause of failure and implementation of the corrective
action. IDT constantly improves the level of support we give
our customers by monitoring the response time to customers
who have detected a product failure. Providing the customer
with an analysis of the failure, including corrective actions and
the statistical analysis of defects, brings CQI full circle-full
, support of our customers and their designs with high-quality
products.
Checks are made at the order entry stage to ensure the
correct processing ofthe Customer's product. Afterverification
and data entry the Acknowledgements (sent to Customers)
are again checked to ensure details are correct. As part of the
CQI process, the results of these verifications are analyzed
using statistical techniques and corrective actions are taken.
Production Control
Production Control (P.C.) is responsible for the flow and
logistics of material as it moves through the manufacturing
processes. The quality of the actions taken by P .C. greatly
influences the quality of service the customer receives.
Because many of our customers have implemented Just-inTime (JIT) manufacturing practices, IDT as a supplier has
adopted these same disciplines. As a result, employees
receive extensive training and the performance level of key
actions are kept under constant review. These key actions
include:
Quotation response and accuracy.
Scheduling response and accuracy.
Response and accuracy of Expedites.
Inventory, management, and effectiveness.
On-time delivery.
3.1
SUMMARY
In 1990, IDT made the commitment to "Leadership through
Quality, Service, and Performance Products".
We believe by following this credo IDT and our customers
will be successful in the coming decade. With the
implementation of the CQI strategy within the company, we
will satisfy our goal...
"Leadership through Quality, Service and Performance
Products".
2
lOT QUALITY CONFORMANCE PROGRAM
A COMMITMENT TO QUALITY
Integrated Device Technology's monolithic assembly
products are designed, manufactured and tested in accordance
with the strict controls and procedures required by Military
Standards. The documentation, design and manufacturing
criteria of the Quality and Reliability Assurance Program were
developed and are being maintained to the most current
revisions of MIL-38S1 0 as defined by paragraph 1.2.1 of MILSTD-883 and MIL-STD-883 requirements.
Product flow and test procedures for all Class B monolithic
hermetic Military Grade microcircuits are in full compliance
with paragraph 1.2.1 of MIL-STD-883. State-of-the-art
production techniques and computer-based test procedures
are coupled with stringent controls and inspections to ensure
that products meet the requirements for 100% screening and
qu ality conformance tests as defined in MIL-STD-883, Methods
S004 and SOOS.
Product flow and test procedures for all plastic and
commercial hermetic products are in accordance with industry
practices for producing highly reliable microcircuits to ensure
that products meet the lOT requirements for 100% screening
and quality conformance tests.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, lOT
ensures that our products consistently meet customer
requirements for quality, reliability and performance.
4.
Wire Bond Monitor: Product samples are routinely
subjected to a strength test per Method 2011 , Condition
0, to ensure the integrity of the lead bond process.
5.
Pre-Cap Visual: Before the completed package is
sealed, 100% of the product is visually inspected to
Method 2010, Condition B criteria.
6.
Environmental Conditioning: 100% of the sealed
product is subjected to environmental stress tests.
These thermal and mechanical tests are designed to
eliminate units with marginal seal, die attach or lead
bond integrity.
7.
Hermetic Testing: 100% of the hermetic packages
are subjected to fine and gross leak seal tests to
eliminate marginally sealed units or units whose
seals may have become defective as a result of
environmental conditioning te~ts.
8.
Pre-Burn-In Electrical Test: Each product is 100%
electrically tested at an ambient temperature of +2SoC
to lOT data sheet or the customer specification.
9.
Burn-In: 100% of the Military Grade product is
burned-in under dynamic electrical conditions to the
time and temperature requirements of Method 1015,
Condition D. Except for the time, Commercial Grade
product is burned-in. as applicable to the same
conditions as Military Grade devices.
10.
Post-Burn-In Electrical: After burn-in, 100% of the
Class B Military Grade product is electrically tested to
lOT data sheet or customer specifications over the
-SsoC to +12SoC temperature range. Commercial
Grade products are sample tested to the applicable
temperature extremes.
SUMMARY
Monolithic Hermetic Package Processing Flow(l)
Refer to the Monolithic Hermetic Package Processing Flow
diagram. All test methods refer to MIL-STO-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requ irem ents. All critical workstations are maintained
at Class 100 levels or better.
11. Mark: All product is marked with product type and lot
code identifiers. MIL-STD-883 compliant Military
Grade products are identified with the required
compliant code letter.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.
Die Visual Inspection : Wafers are cut and separated
and the individual die are 100% visually inspected to
strict lOT-defined internal criteria.
3.
Die Shear Monitor: To ensure die attach integrity,
product samples are routinely subjected to a shear
strength test per Method 2019.
12. Quality Conformance Tests: SamplesoftheMilitary
Grade product which have been processed to the
100% screening tests of Method S004 are routinely
subjected to the quality conformance requirements of
Method SOOS.
NOTE:
1. For quality requirements beyond Class B levels such as SEM analySis, X-Ray inspection, Particle Impact Noise Reduction (PIND) test, Class S screening
or other customer specified screening flows, please contact your Integrated Device Technology sales representative.
3.2
SUMMARY
Monolithic Plastic Package Processing Flow
6.
Post Mold Cure: Plastic encapsulated devices are
baked to ensure an optimum polymerization of the
epoxy mold compound so as to enhance moisture
resistance characteristics.
7.
Pre-Burn-In Electrical: Each product is 100%
electrically tested at an ambient temperatu re of +25°C
to lOT data sheet or the customer specification.
8.
Burn-In: Except for MSI Logic family devices where
it may be obtained as an option, all Commercial
Grade plastic package products are burned-in for 16
hours at +125°C minimum (or equivalent), utilizing
the same burn-in conditions as the Military Grade
product.
9.
Post-Burn-In Electrical: After burn-in, 100% of the
plastic product is electrically tested to lOT data sheet
or customer specifications at the maximum
temperature extreme. The minimum temperature
extreme is tested periodically on an audit basis.
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods refer to MIL-STO-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.
Topside silicon nitride passivation is all applied to all
wafers for better moisture barrier characteristics.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.
Die Visual Inspection: Wafers are 100% visually
inspected to strict lOT defined internal criteria.
3.
Die Push Test: To ensure die attach integrity,
product samples are routinely subjected to die push
tests, patterned after MIL-STO-883, Method 2019.
4.
5.
10. Mark: All product is marked with product type and lot
code identifiers. Products are identified with the
assembly and test locations.
Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull and ball sr'3ar tests to
ensure the integrity ofthe wire bond process, patterned
after MIL-STO-883, Method 2011, Condition O.
11. Quality Conformance Inspection: Samples of the
plastic product which have been processed to the
100% screening requirements are subjected to the
Periodic Quality Conformance Inspection Program.
Where indicated, the test methods are patterned after
MIL-STO-883 criteria.
Pre-Cap Visual: Before encapsulation, all product
lots are visually inspected (using LTPO 5 sampling
plan) to criteria patterned after MIL-STO-883, Method
2010, Condition B.
3.2
2
TABLE 1
This table defines the device class screening procedures for lOTs high reliability products in conformance with MIL-STD-883C.
Monolithic Hermetic Package Final Processing Flow
CLASS-S
OPERATION
CLASS-C(1)
CLASS-B
TEST METHOD
RQMT
TEST METHOD
RQMT
TEST METHOD
RQMT
1015 Condo 0,
240 Hrs @ 125°C or
equivalent
100%
1015 Condo 0,
160 Hrs. @ 125°C min
or equivalent
100%
Per applicable
device specification
100%
POST BURN·IN
ELECTRICAL:
Static (DC), Functional
and Switching (AC)
Per applicable
device specification
+25, ·55 and 125°C
100%
Per applicable
device specification
+25, ·55 and 125°C
100%
Per applicable (2)
device specification
100%
Group A ELECTRICAL:
Static (DC), Functional
and Switching (AC)
Per applicable
device specification
and 5005
Sample
Per applicable
device specification
and 5005
Sample
MARK/LEAD
STRAIGHTENING
lOT Spec
100%
lOT Spec
100%
lOT Spec
100"10
FINAL ELECTRICAL
TEST
Per applicable
device specification
+25°C
100%
Per applicable
device specification
+25°C
100%
Per applicable
device specification
+25°C
100%
lOT Spec
100%
lOT Spec
100%
lOT Spec
100%
Sample
lOT Spec
Sample
100%
lOT Spec
100%
BURN·IN
FINAL VISUAUPACK
QUALITY CONFORMANCE
INSPECTION
5005 Group B, C, D.
QUALITY SHIPPING
INSPECTION
(Visual/Plant Clearance)
lOT Spec
Sample
100%
5005 Group B,C,D.
lOT Spec
Per applicable (2)
Sample
device specification
NOTES:
1. Class-C = lOT commercial spec. for hermetic and plastic packages
2. Typical O°C, 70°C, Extended -55°C +125°C
3.2
3
RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
INTRODUCTION
Radiation
Category
The need for high-performance CMOS integrated circuits
in military and space systems is more critical today than ever
before. The low power dissipation that is achieved using
CMOS technology, along with the high complexity and density
levels, makes CMOS the nearly ideal component for all types
of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may
be encountered. The implication of a device failure within a
military or space system clearly is critical. lOT has made a
significant contribution toward providing reliable radiationtolerant systems by offering integrated circuits with enhanced
radiation tolerance. Radiation environments, lOT process
enhancements and device tolerance levels achieved are
described below.
Primary
Particle
Source
Effect
Total Dose
Gamma
Space or
Nuclear
Event
Permanent
Dose Rate
Photons
Nuclear
Event
Temporary
Upset of Logic
State or
Latch-Up
SEU
Cosmic
Rays
Space
Temporary
Upset of
Logic State
Neutron
Neutrons
Nuclear
Event
Device Leakage
Due to Silicon
Lattice Damage
2510 drw 01
Figure 1.
THE RADIATION ENVIRONMENT
There are four different types of radiation environments
that are of concern to builders of military and space systems. DEVICE ENHANCEMENTS
Of the fOllr radiation environments above, lOT has taken
These environments and their effects on the device operation,
considerable data on the first two, Total Dose Accumulation
summarized in Figure 1, are' as follows:
Total Dose Accumulation refers to the total amount of and Dose Rate. lOT has developed a process that significantly
accumulated gamma rays experienced by the devices in the improves the radiation tolerance of its devices within these
system, and is measured in RADS (SI) for radiation units environments. Prevention of SEU failures is usually
experienced at the silicon level. The physical effect of gamma accomplished by system-level considerations, such as Error
rays on semiconductor devices is to cause threshold shifts (Vt Detection and Correction (EDC) circuitry, since the occurrence
shifts) of both the active transistors as well as the parasitic field of SEUs is not particularly dependent on process technology.
transistors. Threshold voltages decrease as total dose is . Through lOT's customer contracts, SEU has been gathered
accumulated; at some point, the device will begin to exhibit on some devices. Little is yet known about the effects of
parametric failures as the input/output and supply currents neutron-induced damage. For more information on SEU
increase. At higher radiation accumulation levels, functional testing, contact lOT's Radiation Hardened Product Group.
Enhancements to lOT's, standard process are used to
failures occur. In memory circuits, however, functional failures
create radiation enhanced and tolerant processes. Field and
due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of gate oxides are "hardened" to make the device lesssusceptible
radiation, usually photons or electrons, experienced by the to radiation damage by modifying the process architecture to
devices in the system due to a pulse event, and is measured allow lower temperature processing. Device implants and Vts
in RADS (Si) per second. The effect of a high dose rate or adjustments allow more Vt margin. In addition to process
burst of radiation on CMOS integrated circuits is to cause changes, lOT's radiation enhanced process utilizes epitaxial
temporary upset of logic states and/or CMOS latch-up. Latch- substrate material. The use of epi substrate material provides
a lower substrate resistance environment to create latch-up
up can cause permanent damage to the device.
Single Event Upset (SEU) is a transient logic state change free CMOS structures.
caused by high-energy ions, such as energetic cosmic rays,
striking the integrated circuits. As the ion passes through the RADIATION HARDNESS CATEGORIES
silicon, charge is either created through ionization or direct
Radiation Enhanced (RE) or Radiation Tolerant ('RT)
nuclear collision. If collected by a circuit node, this excess versions of lOT products follow lOT's military product data
charge can cause a change in logic state of the circuit. sheets whenever possible (consult factory). lOT's Total Dose
Dynamic nodes that are not actively held at a particular logic Test plan exposes a sample of die on a wafer to a particular
state (dynamic RAM cells for example) are the most susceptible. Total Dose level via ARACOR X-Ray radiation. This Total
These upsets are transient, but can cause system failures Dose Test plan qualifies each 'RE or' RTwafer to a Total Dose
level. Only wafers with sampled die that pass Total Dose level
known as "soft errors."
Neutron Irradiation will cause structural damage to the tests are assembled and used for orders (consult factory for
silicon lattice which may lead to device leakage and, ultimately, more details on Total Dose sample testing). With regard to
functional failure.
Total Dose testing, clarifications/exceptions to MIL-STD-883,
3.3
Methods 5005 and 1019 are required. Consult factory for
more details.
The 'RE and 'RT process enhancements enable lOT to
offer integrated circuits with varying grades of radiation
tolerance or radiation "hardness".
• Radiation Enhanced process uses Epi wafers and is able
to provide devices that can be Total Dose qualified to 10K
RADs (Si) or greater by lOT's ARACOR X-Ray Total Dose
sample die test plan (Total Dose levels require negotiation,
consult factory for more details).
• Radiation Tolerant product uses standard wafer/process
material that is qualified to 10K RADs (Si) Total Dose by
lOT's ARACOR X-Ray Total Dose sample die test plan.
Integrated Device Technology can provide Radiation
Tolerant/Enhanced versions of all product types (some speed
grades may not be available as 'RE).
Please contact your lOT sales representative or factory
marketing to determine availability and price of any lOT
3.3
product processed in accordance with one of these levels of
radiation hardness.
CONCLUSION
There has been widespread interest within the military and
space community in lOT's CMOS product line for its radiation
hardness levels, as well as its high-performance and low
power dissipation. To serve this growing need for CMOS
circuits that must operate in a radiation environment, lOT has
created a separate group within the company to concentrate
on supplying products for these applications.Continuing
research and development of process and products, including
the use of in-house radiation testing capability, will allow
Integrated Device Technology to offer continuously increasing
levels of radiation-tolerant solutions.
2
II
PACKAGE DIAGRAM OUTLINES
II
THERMAL PERFORMANCE CALCULATIONS FOR lOT'S PACKAGES
Since most of the electrical energy consumed by
microelectronic devices eventually appears as heat, poor
thermal performance of the device or lack of management of
this thermal energy can cause a variety of deleterious effects.
This device temperature increase can exhibit itself as one of
the key variables in establishing device performance and long
term reliability; on the other hand, effective dissipation of
internally generated thermal energy can, if properly managed,
reduce the deleterious effects and improve component
reliability.
A few key benefits of lOT's enhanced CEMOSTM process
are: low power dissipation, high speed, increased levels of
integration, wider operating temperature ranges and lower
quiescent power dissipation. Because the reliability of an
integrated circuit is largely dependent on the maximum
temperature the device attains during operation, and as the
junction stability declines with increases injunction temperature
(TJ), it becomes increasingly important to maintain a low (TJ).
CMOS devices stabilize more quickly and at greatly lower
temperature than bipolar devices under normal operation.
The accelerated aging of an integrated circuit can be expressed
as an exponential function of the junction temperature as:
4.
Tightly controlled the assembly procedures to meet or
exceed the stringent criteria of MIL-STD-883_to ensure
maximum heat transfer between die and packaging
materials.
The following figu res graphically illustrate the thermal values
of lOT's current package families. Each envelop (shaded
area) depicts a typical spread of values due to the influence of
a number of factors which include: circuit size, package
materials and package geometry. The following range of
values are to be used as a comprehensive characterization of
the major variables rather than single point of reference.
When calculating junction temperature (TJ), it is necessary
to know the thermal resistance of the package (SJA) as
measured in "degree celsius per watt" . With the accompanying
data, the following equation can be used to establish thermal
performance, enhance device reliability and ultimately provide
you, the user, with a continuing series of high-speed, lowpower CMOS solutions to your system design needs.
SJA = [TJ - TA]/P
TJ = TA + P[SJA] = TA + P[SJC + SCA]
where
tA
= to exp
[
§.
k
(.J... -.J...\]
\ To
9JC
TJ)
= TJ- Tc
P
SCA
= Tc- TA
P
where
9
J
P
TA
TJ
Tc
SCA
tA
lifetime at elevated junction (TJ) temperature
normal lifetime at normal junction (To) temperature
to
Ea
activation energy (ev)
Boltzmann's constant (8.617 x 10-5ev/k)
k
i.e. the lifetime of a device could be decreased by a factor of
2 for every 1Qoe increase temperature.
To minimize the deleterious effects associated with this
potential increase, lOT has:
1. Optimized our proprietary low-power CEMOS
fabrication process to ensure the active junction
temperature rise is minimal.
2. Selected only packaging materials that optimize heat
dissipation, which encourages a cooler running device.
3. Physically designed all package components to
enhance the inherent material properties and to take
full advantage of heat transfer and radiation due to
case geometries.
SJC
SJA
Ref. MIL-STD-883C, Method 1012.1
JEDEC ENG. Bulletin No. 20, January 1975
1986 Semi. Std., Vol. 4, Test Methods G30-86, G32-86.
4.1
=
=
=
=
Thermal resistance
Junction
Operational power of device (dissipated)
Ambient temperature in degree celsius
Temperature of the junction
Temperature of case/package
Case to Ambient, thermal resistance-usually a
measure of the heat dissipation due to natural or
forced convection, radiation and mounting
techniques.
Junction to Case, thermal resistance-usually
measured with reference to the temperature at a
specific point on the package (case) surface.
(Dependent on the package material properties
and package geometry.)
Junction to Ambient, thermal resistance-usually
measured with respect to the temperature of a
specified volume of still air. (Dependent on SJC +
SJA which includes the influence of area and
environmental condition.)
Theta JA vs. Airflow
160 Pin Quad Flatpacks
_ _ Normal PQFP
_ _ Enhanced PQFP
- - MQUAD
~
..,
c(
]l"
t-
50
45
40
35
30
25
20
15
10
5
~::::j;;;:\-M~~;=
.......................:........
:
~
••• . . . . . . . .:. •••••••••••
~u •••••••••
·::::;::~j::::~:t::::l:~:::+~:::::
0+-~~~~-+~~~4-~
o
200 400
600· 800 1000
Airflow (LFM)
AIRFLOW (LFM)
Measurements done with Delco Temp09 Thermal Ole (.250"sq.)
Delco Temp 09.Thermal Ole (.250"sq.)
Parts mounted to standard 3" sq. test board.
THETA JA vs. AIR FLOW
32 pin J-bend SOIC
THETA JA vs. AIRFLOW
179 PIN PGA - R4000 PACKAGE
INTEGRAL CuW HEATSINK - NO FIN ATTACHED
55.-----r----,----~----,---~-----,
20r-.--,-.--~~~-,~~~~
~
.., 10
15
c(
c(
tW
i!:
5
0
50~--~~---+----~----+---~----~
o
:::j~;=::·l···rl·· ::tt:~
0
................................ ·················j··········..·····t················j··.................
~45
!',
200
400
600
800
!i'40
..,
~ 35
i!:
··__·_··:=::;-::!::::::I::===
30
25 ...................................................1"...............1" .............."]" .................
1000
AIRFLOW (LFM)
20
Delco Temp09 Thermal Ole Array (.500"sq.)
applied power = 3W
o
400
200
600
800
1000
AIR VELOCITY (LFM)
Theta JC was measured to be 17°CNI- Ole size (.150"x.250·1
Theta JA vs. Airflow
PLASTIC SSOP PACKAGES
THETA JA VS. AIRFLOW
84 PLCC
50r-~~--~~~~--~~~~
I: *Itffi!::~~
·······\·······t·······j·..····t·······l······+······j·······t······· ........
t-
10
!
:
!
:
:
!
!
!
·······t······-j--·····t·······l·······t·······j········[·······1···············
0+-~-+~~+-~-4--~4-~~
o
400
600
800
1000
AIRFLOW (LFM)
Delco Temp09 Thermal Ole (.250"sq.)
AIRFLOW (LFM)
THETA JC: 20/24 PIN
48/56 PIN
200
=35-40 °CIW
=16-20 °CIW
4.1
2
Theta JA - Still Air 16-20 Lead Ceramic Dips
Theta JA vs. Airflow
84 pin PGA - Cavity Down w/CuW heatslnk
110~-----------~.
105
100
95
40~~~--~~~~~~~~,-~~
~ 80~~
:: 1-\11····[····i······il······I+·
~:
\
i.
., i
~
j
...
i
1s+~H±I·+··ljl
10
75
70
65
60
55
.
sl··· -···I-i·····l·····!···!I·t··
50~~.-~~~~~~~~
a
Ole Size (1000's sq. mils)
O-l--t--t--+----+-+--+--i--+---+--+---l
o
200
400
600
800
5 10 15 20 25 30 35 40 45 50
1000
Airflow (11m)
Measurements were done using Temp09 Delco Thermal Ole (.250sq.)
GD 208 THETA JA VS. AIRFLOW
II
Theta JC 16-20 Lead Ceramic Dip
30~---------------,
25
~ 20
~
.,o 15
r=~ 10
5
o 0 5 10 15 20 25 30 35 40 45 50
AIRFLOW (LFM)
Ole Size (1000's sq. mils)
Delco Temp09 Thermal Ole (.250"sq.)
Theta JC 22-40 Lead Ceramic Dips
Theta JA - Still Air 22-40 Ceramic Dips
20~--------------------~
80~------------~
18
16
~ 14
~ 12
~ 10
~
60
55
~ 50
]1 45
40
35
-
~
8
r= 6
...
4
2
o
75
70
65
30~~~~~~~~~~~
0 5 10 15 20 25 30 35 40 45 50
o 5 10 15 20 25 30 35 40 45 50
Ole Size (1000's sq. mils)
Ole Size (1000's sq. mils)
4.1
3
Theta JA Ceramic FlatpackslCerpacks
Theta JC Pin Grid Arrays
7.-------------------~~
180.-----------------------~
160
140
120
100
80
60
40
20
~
~
~
~
f3.
6
~ 5
~4
.,o
~
3
r:
2
O~~~~~~~~~~~~~
o
8
16 24 32 40 48 56 64
O+-~--r_~~--~~--~~
Lead Count
o
50
100
150
200
Ole Size (1000's sq. mils)
PLASTIC DIPS: 16,18 & 20 PINS
Theta JC Ceramic Flatpacks/Cerpacks
18.-----------------------~
16
14
~ 12
o 10
~
8
Gi
6
r:
~
~
fI)
()
c
'"
]i
~
a:
4
~
r:
2
fI)
00
8
16 24 32 40 48 56 64
Lead Count
100
90
80
70
60
50
40
30
20
10
0
~
~/~
~Z'ZZZIIZZZZa
0 5 10 15 20 25 30 35 40 45 50
Ole Size (1000's sq. mils)
Thermal Resistance of Ceramic LCC's
PLASTIC SOICS: 24,28 & 32 PINS
100~---------------------,
100.---------------------~
t:
~
o
~
~
~
r:
90
80
70
60
50
40
30
20
10
~
fI)
()
c
'"
1ii
1ia:
iU
E
....
fI)
.c
ejo
O~~~~~~~~
16
24
3240
48
56
64
LEAD COUNT
90
80
70
60
50
40
30
20
10
0
~
~/~
~z~J7zzzzz22z~
0 5 10 15 20 25 30 35 40 45 50
Ole Size (1000's sq. mils)
4.1
4
PLASTIC DIPS: 22,24 & 28 PINS
~
at
u
c
~
S!
II:
~
III
~
100
90
80
70
60
50
40
30
20
10
0
~
at
u
~/lZ/ZZZ2J
c
IG
.i
S!
II:
~
~Z'ZZ7ZZZZZZd
III
~
PLASTIC PLCCS: 44,52,68 & 84 PINS
100
90
80
70
60
50
40
30
20
10
o
0 5 10 15 2025 30 35 4045 50
Ole Size (1000's sq. mils)
Ii
.i
81
II:
~
GI
~
60
50
40
30
20
10
0
~
~
~ela
CI)
()
22.7"0Z027~
c
IG
.ien
GI
II:
iO
~ 9Jc
. 27227722//ZZJ
E
GI
.c
I-
CI)
()
c
IG
'Iii
Ui
GI
60
50
40
30
20
10
II:
iO
E
!I-
o
2
Z2
2 Z1
0 5 10 15 20 25 30 35 40 45 50
Theta JA vs. Airflow
Plastic Quad Flatpacks
60.-__8rO~,1_4~4,~1_60~,2,0_8_I_ea,d_s__, - - .
50 .. ::::::::: :::::::::::
80
70
20
10
[2Qzz Z 2~c2 2 2 Z I
Ole Size (1000's sq. mils)
100
90
60
50
40
30
Ell
80
70
0
0 5 101520253035404550
PLASTIC DIPS: 40,48 & 64 PINS
~
91c • 44,52,68,84 pins
0 10 20 30 4050 60 70 80 90100
100
90
Ole Size (1000's sq. mils)
~
u
~Z2Z~aZ·;4;;ZZZI
PLASTIC SOICS: 16 & 20 PINS
100
90
80
70
~
Ole Size (1000's sq. mils)
PLASTIC PLCCS: 28 & 32 PINS
~8
~44'52,"PI"
::::::::::r::::::::r::::::::r:::::::::
................ ········· . ·i··..········r······. . ··+···········
.....................[........... \........... \...........
~bL/ZZZJ
20 ·································t··········T
IQzzzzz }P: z2 Z 7 Z Z Z 21
o ................................. j............("........ r-..........
o
0 10 20 30 40 50 60 70 80 90 100
200 400
600 800 1000
AIRFLOW (LFM)
Ole Size (1000's sq. mils)
THETA JC: 15-25°C/W
4.1
5
PACKAGE DIAGRAM OUTLINE INDEX
SECTION PAGE
MONOLITHIC PACKAGE DIAGRAM OUTLINES ........................................................ 4.3
PKG.
P16-1
P18-1
P20-1
P22-1
P24-1
P24-2
P28-1
P28-2
P28-3
P32-1
P32-2
P32-3
P40-1
P48-1
P64-1
D16-1
D18-1
D20-1
D22-1
D24-1
D24-2
D24-3
D28-1
D28-3
D32-1
D40-1
C20-1
C22-1
C24-1
C24-2
C28-1
C28-2
C28-3
C32-1
C32-2
C32-3
C40-1
C48-1
C48-2
C64-2
CG8-1
DESCRIPTION
16-PinPlastic DIP (300 mil) .................................................. ;.: ..... ; .................... :....................
18-Pin Plastic DIP (300 mil) ..... :'..............................................................................................
19
20
'~~~~:~ ~::~!:~ g:~ ~~~~ ~m : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : . ~~.
24-Pin Plastic
24-Pin Plastic
28-Pin Plastic
28-Pin Plastic
28-Pin Plastic
32-Pin Plastic
32-Pin Plastic
32-Pin Plastic
40-Pin Plastic
48-Pin Plastic
.64-Pin Plastic
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
(300
(600
(600
(300
(400
(600
(300
(400
(600
(600
(900
mil) ..............................................................................................:.....
mil) ............................................................... ; ......................... ;..........
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ....................................................................................................
mil) ............................................... :....................................................
16-Pln CERDIP (300 mil) ................................................................................:................ ;.......
18-Pin CERDIP.(300 mil)........................................................................................................
20-Pin CERDIP (300 mil) ...................................... ~ ....... : .............................................. ,..........
22-Pin CERDIP (300 mil) ............................................................................................~...........
24-Pin CERDIP (300 mil) .................................................................................. ;.;...................
24-Pin CERDIP (600 mil(.................................................................................................,......
24-Pin CERDIP (400 mil) .......... :......................................................................................:......
28-Pin CERDIP (600 mil) .....................................................................................................:..
. 28-Pin CERDIP (300 mil) .:......................................................................;....... ~ ..................... ;..
32-Pin CERDIP (wide body) .........................................; ......................................................::..
,.40-Pin .CERDIP (600 m,il) ;..................................................,......................................................
'20-Pin
22-Pin
24-Pin
24-Pin
28-Pin
28-Pin
28-Pin
32-Pin
32-Pin
32-Pin
40-Pin
48-Pin
48-Pin
64-Pin
68-Pin
Sidebraze DIP (300 mil) ..............................................................................................
Sidebraze DIP (300 mil) ..............................................................................................
Sidebraze DIP (300 mil) ..............................................................................................
Sidebraze DIP (600 mil) ..............................................................................................
Sidebraze DIP (300 mil) .................................... :.........................................................
Sidebraze DIP (400 mil) ..............................................................................................
Sidebraze DIP (600 mil) ..............................................................................................
Sidebraze DIP (600 mil) ..............................................................................................
Sidebraze DIP (400 mil) .........................................................................,'.,...................
Sidebraze DIP (300 mil) ................................................................."., .... : ......... ,...........
Sidebraze DIP (600 mil) ..............................................................................................
Sidebraze DIP (400 mil) ...........................................................................................,..
Sidebraze DIP (600 mil) ......................................................................................;.......
Topbraze DIP (900 mil) ...............................................................................................
Sidebraze DIP (600 mil) ..............................................................................................
20
22
22
19
21
22
19
21
22
22
23
1
1
1
1
1
2
2
2'
1
2
2
3
3
3
5
3
4
5
5
4
3
5
4
5
6
5
G68-1
G68-2
G68-3
G144-2
G208-2
68-Lead Pin Grid Array (cavity up) ............................. : ..................... ,.................; .. : ..-.:............
68-Lead Pin Grid Array (cavity down) ............................... ;...............................<: ....... ,............
68-Lead Pin Grid Array (small outline - cavity up) ................................: ............... ;...............
144-Lead Pin Grip Array (cavity up - R3001) ............................................:.:........................
208-Lead Pin Grid ArraY' (cavity down) .............................,........................ ;; ...............
>............
14
16
15
17
18
S016-1
S016-6
16-Pin Small Outline IC (gull wing) ....................................................................:....................
16-Pin Small Outline IC (EIAJ -1.27 lead pitch) ...................................................................
24
26
4.2
SECTION PAGE
MONOLITHIC PACKAGE DIAGRAM OUTLINES {Continued} ............. ~ ....................~4.3
PKG.
DESCRIPTION
5018-1
5020-1
5020-2
5020-6
5020-7
5024-2
5024-4
5024-6
5024-7
5024-8
5028-2
5028-3
5028-5
5032-2
5048-1
5056-1
18-Pin Small Outline IC (gull wing) .........................................................................................
20-Pin Small Outline IC (J-bend - 300 mil) ......................................;....................................
20-Pin Small Outline IC (gull wing) .........................................................................................
20-Pin Small Outline IC (EIAJ - 1.27 lead pitch) ..................................................................
20-Pin Small Outline IC (EIAJ - .65 lead pitch) ....................................................... ~ .......... ..
24-Pin Small Outline IC (gull wing) .........................................................................................
24-Pin Small Outline IC (J-bend - 300 mil) ......................................................................... ..
24-Pin Small Outline IC (EIAJ - 1.27 lead pitch) ..................................................................
24-Pin Small Outline IC (EIAJ - .65 lead pitch) .................. ;................................ ~ .............. ..
24-Pin Small Outline IC (J-bend - 300 mil) ...........................................................................
28-Pin Small Outline IC (gull wing) ....... ~ .................................................................................
28-Pin Small Outline IC (gull wing) .........................................................................................
28-Pin Small Outline IC (J-bend - 300 mil) ...........................................................................
32-Pin Small Outline IC (J-bend - 300 mil) ...........................................................................
48-Pin Small Outline IC ..........................................................................................................
56-Pin Small Outline IC ..........................................................................................................
24
27
24
26
27
24
27
26
29
27
25
25
27
27
28
28
J18-1
J20-1
J28-1
J32-1
J44-1
J52-1
J68-1
J84-1
18-Pin Plastic Leaded Chip Carrier (rectangular) ...................................................................
20-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
28-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
32-Pin Plastic Leaded Chip Carrier (rectangular) ...................................................................
44-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
52-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
68-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
84-Pin Plastic Leaded Chip Carrier (square) ..........................................................................
32
31
31
32
31
31
31
31
L20-1
L20-2
L22-1
L24-1
L28-1
L28-2
L32-1
L44-1
L48-1
L52-1
L52-2
L68-1
L68-2
20-Pin
20-Pin
22-Pin
24-Pin
28-Pin
28-Pin
32-Pin
44-Pin
48-Pin
52-Pin
52-Pin
68-Pin
68-Pin
Leadless Chip Carrier (rectangular) ............................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (rectangular) ............................................................................
Leadless Chip Carrier (rectangular) ............................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (rectangular) ............................................................................
Leadless Chip Carrier (rectangular) ............................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (square) ...................................................................................
Leadless Chip Carrier (square) ...................................................................................
13
11
13
13
11
13
13
11
11
12
12
12
12
E16-1
E20-1
E24-1
E28-1
E28-2
E48-1
E56-1
16-Lead CERPACK ................................................................................................................
20-Lead CERPACK ................................................................................................................
24-Lead CERPACK ................................................................................................................
28-Lead CERPACK ................................................................................................................
28-Lead CERPACK ................................................................................................................
48-Lead CERPACK ................................................................................................................
56-Lead CERPACK ................................................................................................................
9
9
9
9
9
10
10
F48-1
F64-1
F68-2
48-Lead Quad Flatpack ................................................................................................'" ..... ..
64-Lead Quad Flatpack ..........................................................................................................
68-Lead Quad Flatpack ..........................................................................................................
7
7
8
4.2
II
2
SECTION PAGE
MONOLITHIC PACKAGE DIAGRAM OUTLINES (Continued) ................................... 4.3
PKG.
DESCRIPTION
PQ80-1
PQ144-2
PQ160-2
PQ20B-2
BO-Lead Plastic Quad Flatpack (EIAJ) ....................................................................................
144-Lead Plastic Quad Flatpack (EIAJ) .................................................................................
160-Lead Plastic Quad Flatpack (EIAJ) .................................................................................
20B-Lead Plastic Quad Flatpack (EIAJ) .................................................................................
30
30
30
30
MODULE PACKAGE DIAGRAM OUTLINES
Module package diagrams are located at the back of each Subsystems data sheet.
4.2
3
PACKAGE DIAGRAM OUTLINES
Integrated Device Technology. Inc.
DUAL IN-LINE PACKAGES
r-
L
F================R
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.
3. THE MINIMUM LIMIT FOR DIMENSION b1 MAY BE .023 FOR CORNER LEADS.
16- 28 LEAD CERDIP (300 MIL)
D18-1
D16-1
DWG #
# OF LDS eN)
SYMBOL
A
b
b1
C
D
E
E1
e
L
L1
Q
S
S1
€X
16
MIN
.140
.015
.045
.009
.750
.285
.290
.100
.125
.150
.015
.020
.005
0"
18
MAX
.200
.021
.060
.012
.830
.310
.320
Bse
.175
.055
.080
15"
MIN
.140
.015
.045
.009
.880
.285
.290
.100
.125
.150
.015
.020
.005
0"
MAX
.200
.021
.060
.012
.930
.310
.320
BSC
.175
.055
.080
15"
D20-1
20
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
.935 1.060
.285 .310
.290 .320
.100 Bse
.125 .175
.150
.015 .060
.020 .080
.005
0"
15"
4.3
D22-1
22
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
1.050 1.080
.285 .310
.300 .320
.100 sse
.125 .175
.150
.015 .060
.020 .080
.005
0"
15"
D24-1
24
MIN MAX
.140 .200
.015 .021
.045 .065
.009 .014
1.240 1.280
.285 .310
.300 .320
.100 Bse
.125 .175
.150
.015 .060
.030 .080
.005
15·
0"
D28-3
28
MIN MAX
.140 .200
.015 .021
.045 .065
.009 .014
1.440 1.485
.285 .310
.300 .320
.100 sse
.125 .175
.150
.015 .060
.030 .080
.005
15·
o·
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24-40 LEAD CERDIP (400 & 600 MIL)
1#
DWG #
OF LDS eN)
SYMBOL
A
b
b1
e
D
E
E1
e
L
l1
Q
S
S1
ex
D24-3
24
MIN
MAX
.130 .175
.015
.021
.045 .065
.009 .014
1.180 1.250
.350 .410
.380 .420
.100 sse
.125 .175
.150
.015 .060
.030 .070
.005
O·
15·
D24-2
24
MIN
MAX
.090 .190
.014 .023
.045 .060
.008 .012
1.230 1.290
.500 .610
.590 .620
.100 sse
.125 .200
.i50
.015 .060
.030 .080
.005
O·
15·
D28-1
28
MIN
MAX
.090
.200
.014
.023
.045
.065
.014
.008
1.440 1.490
.600
.510
.590
.620
.100 Bse
.125
.200
.150
.060
.020
.080
.030
.005
o·
15·
-
D40-1
40
MIN
MAX
.160 .220
.014 .023
.045 .065
.008 .014
2.020 2.070
.510 .600
.590 .620
.100 sse
.125 .200
.150
.020 .060
.030 .080
.005
15·
o·
32 LEAD CERDIP (WIDE BODY)
OWG #
# OF LOS eN)
SYMBOL
A
b
b1
e
D
E
E1
e
L
l1
Q
S
S1
tY..
032-1
32
MIN
MAX
.120
.210
.014
.023
.045
.065
.008
.014
1.625 1.675
.570
.600
.590
.620
.100 sse
.125
.200
.150
.020
.060
.030
.080
.005
o·
15·
4.3
2
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
20-32 LEAD SIDE BRAZE (300 MIL)
C
--..!il1-4-
E1
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG #
# OF LDS (N)
SYMBOL
A
b
b1
C
D
E
E1
e
L
L1
Q
S
S1
S2
C20-1
20
MIN
MAX
.090
.200
.014
.023
.045
.060
.008
.015
.970 1.060
.260
.310
.290
.320
.100 sse
.125
.200
.150
.015
.060
.030
.065
.005
.005
-
C22-1
22
MAX
MIN
.100
.200
.014.023
.045
.060
.008
.015
1.040 1.120
.310
.260
.290
.320
.100 SSC
.200
.125
.150
.015
.060
.030
.065
.005
.005
-
-
C24-1
24MIN
MAX
.200
.090
.015
.023
.045
.060
.008
.015
1.180 1.230
.220
.310
.290
.320
.100 SSC
.125
.200
.150
.015
.060
.030
.065
.005
.005
-
4.3
C28-1
28
MAX
MIN
.090
.200
.014.023
.045
.060
.008
.015
1.380 1.4-20
.220
.310
.290
.320
.100 SSC
.125
.200
.150
.015
.060
.030
.065
.005
.005
-
C32-3
32
MIN
MAX
.090
.200
.014.023
.045
.060
.008
.014
1.580 1.640
.280
.310
.320
.290
.100 SSC
.175
.100
.150
.030
.060
.030
.065
.005
.005
-
-
3
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
28-48 LEAD SIDE BRAZE (400 MIL)
48 LEAD OPTION
S2
Q
1L
-_r------I--!----...r::::::=:~~
r-=t=
SEATING PLANE
i
~
..-
C
E1
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
1#
DWG #
OF LOS (N)
SYMBOL
A
b
b1
C
0
E
E1
e
L
L1
Q
S
S1
S2
C28-2
28
MIN
MAX
.090
.200
.014
.023
.060 .
.045
.008
.014
1.380 1.420
.380
.420
.390
.420
.100 BSC
.100
.175
.150
.030
.060
.030
.065
.005
.005
-
C32-2
32
MIN
MAX
.090
.200
.014
.023
.045
.060
.008
.014
1.580 1.640
.380
.410
.390
.420
.100 BSC
.100
.175
.150
.030
.060
.030
.065
.005
.005
-
C48-1
48
MIN
MAX
.085
.190
.014
.023
.045
.060
.008
.014
1.690 1.730
.380
.410
.390
.420
.070 BSC
.125
.175
.150
.070
.020
.030
.065
.005
.005
4.3
4
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24- 68 LEAD SIDE BRAZE (600 MIL)
68 LEAD OPTION
II
~S~2__~~========~====~~
¢=,
L1 T
~--
E1
----i.,j
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG #
# OF LDS (N)
SYMBOL
A
b
bl
e
D
E
E1
e
L
L1
Q
S
S1
S2
C24-2
24
MIN
MAX
.090
.190
.015
.023
.045
.060
.008
.012
1.180 1.220
.575
.B10
.595
.620
.100 Bse
.175
.125
.150
.020
.060
.030
.065
.005
.005
-
e28-3
C32-1
28
32
MIN
MAX
MIN
MAX
.085
.190
.100
.190
.015
.022
.015
.023
.045
.045
.060
.060
.008
.012
.008
.014
1.380 1.430 1.580 1.B40
.580
.610
.580
.610
.595
.620
.590
.620
.100 Bse
.100 sse
.100
.175
.125
.175
.150
.150
.020
.020
.060
.060
.065
.030
.030
.065
.005
.005
.005
.005
-
-
4.3
e40-1
C68-1
C48-2
40
48
68
MIN
MAX
MIN
MAX
MIN
MAX
.085
.190
.085
.190
.100
.190
.015
.023
.015
.023
.015
.023
.OBO
.045
.OBO
.045
.OBO
.045
.008
.012
.008
.012
.008
.012
1.980 2.030 2.370 2.430 2.380 2.440
.580
.580
.610
.610
.550
.610
.595
.620
.595
.620
.590
.620
.100 sse
.100 Bse
.070 Bse
.125
.175
.125
.175
.125
.175
.150
.150
.150
.020
.020
.060
.020
.060
.070
.030
.030
.065
.065
.030
.065
.005
.005
.005
.005
.005
.005
-
5
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
64 LEAD TOP BRAZE (900 MIL)
1.1--------..
D ---'\-r·---~·I
fN
E
l~~
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG
#
# OF LOS eN)
SYMBOL
A
b
b1
C
D
E
El
E2
-~----
e
L
1--_----1:L
Q
-~.--
S
S1
52
C64-2
64
MIN
MAX
.120
.180
.015,
.021
.0~5
.060
.009
.012
3.170
3~240
;790
.810
;,.880
.915
.640
.660
.100 Bse
.125
.160
.150
.020 ' .100
.030
.065
.005
.005
-
4.3
6
PACKAGE DIAGRAM OUTLINES
FLATPACKS (Continued)
48-64 LEAD QUAD FLATPACK
.---- E
--~
f---E1
I-- L -
E2
r--
L -
A2
I
I
I
o
D2
1
01
J
'--.
.-~
~
L
[
:!
D
1
e
~
t
r;.;.
~
b
f
I
I
I
PIN 1 ID
j
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
OWG #
# OF LOS (N)
SYMBOL
A
A1
A2
b
C
-.O/E
01/E1
--- 02/E2
e
-_._----.
L
-----N 0 /N(-.--
F48-1
48
MIN
MAX
.089
.108
.079
.096
.058
.073
.018
.022
.008
.010
.750
.100 REF
.550 BSC
.050 BSC
.350
.450
12
F64-1
64
MAX
MIN
.090
.070
.078
.060
.030
.045
.020
.016
.012
.009
.915
.885
.075 REF
.750 BSC
.050 BSC
.350
.450
16
4.3
7
PACKAGE DIAGRAM OUTLINES
FLATPACKS (Continued)
68 LEAD QUAD FLATPACK (FINE PITCH)
ffiiEl
E
L
~
V
PIN 1
INDEX CORNER
45· X .01 5
D3
I
I
I
1
I
I
/
01
III
I
D
j
E3
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.
#
DWG #
OF LOS (N)
SYMBOL
A
A1
b
e
D/E
01/E1
D2/E2
e
L
NO/NE
F68-2
68
MIN
MAX
.084
.064
.054
.070
.008
.013
.0045
.008
.860
1.100
.460
.500
.400 REF
.025 Bse
.200
.300
17
4.3
8
PACKAGE DIAGRAM OUTLINES
CERPACKS
16-28 LEAD CERPACK
D
t-----
-ft--
----.j
Q
S1
b
L
t
N
E
E1
K
--1-
II
I
I I
I
--ef--
tL
--S
NOTES:
1. ALL DIMENSION ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
1#
OWG #
OF LOS eN
SYMBOL
A
E16-1
16
MIN
MAX
E20-1
20
MAX
MIN
.055
.085
.019
.045
.015
.006
.0045
.092
b
.015
C
D
E
E1
.0045
.370
.430
-
.019
.006
.540
.245
.285
.245
.300
e
.305
.050 BSC
K
.008
L
.250
Q
.026
S
S1
-
.015
.370
.040
.045
.005
-
.305
.050 BSC
.015
.008
.250
.370
.040
.026
.005
.045
-
E24-1
24
MIN
MAX
.045
.090
.015
.019
.0045 .006
.300
.640
.420
.440
.050 BSC
.008
.015
.250
.370
.026
.040
.045
.005
-
4.3
E28-1
28
MIN
MAX
.045
.115
.015
.0045
.460
-
E28-2
28
MAX
MIN
.045
.015
.090
.019
.006
.0045
.740
.520
.550
.340
.006
.740
.380
.400
.050 BSC
.008
.015
.250
.370
.026
.045
.045
.000
-
-
.019
.050 BSC
.015
.008
.250 .370
.026 .045
.045
.005
-
9
PACKAGE DIAGRAM OUTLINES
CERPACKS (Continued)
48-56 LEAD CERPACK (.025" LEAD PITCH)
4i~
-i
S1
c-ir-
~
5
E
T
-t
4
L
K
e
S -
NOTES: (UNLESS OTHERWISE SPECIFIED)
1. ALL DIMENSIONS ARE IN INCHES.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "Nil REPRESENTS THE NUMBER OF LEADS.
4. THIS DWG REPRESENTS A 48 LEAD CERPACK.
DWG #
# OF LDS (N)
SYMBOL
A
b
C
D
E
e
K
L
Q
S
S1
T
E48-1
48
MIN MAX
.065 .086
.008 .013
.0045 .006
.614 .626
.370 .390
.025 BSC
.003 .007
.312 .405
.035 .045
.045
.005
.995 1.200
E56-1
56
MIN MAX
.065 .086
.008 .013
.0045 .006
.713 .727
.370 .390
.025 BSC
.003 .007
.312 .405
.035 .045
- .045
.005
.995 1.200
4.3
10
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS
J
X 45"
iA1i
h X 45"
3 PL
E
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.
. f!-r
B3
--1
0
20-48 LEAD Lee (SQUARE)
1#
DWG #
OF LOS eN)
SYMBOL
A
A1
B1
S2
83
D/E
D1/E1
D2/E2
D3/E3
e
e1
h
J
L
L1
L2
L3
ND/NE
L20-2
20
MIN
MAX
.064
.100
.054 .066
.022 .028
.072 REF
.006 .022
.342 .358
.200 SSC
.100 Bse
.358
.050 Bse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003
.015
5
L28-1
28
MIN
MAX
.064
.100
.050 .088
.022 r-:D28
.072 REF
.006 .022
.442 .460
.300 sse
.150 SSC
.460
.050 SSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003
.015
7
L44-1
44
MIN
MAX
.064
.120
.054 .088
.022 .028
.072 REF
.006 .022
.640 .660
.500 BSC
.250 SSC
.560
.050 BSC
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003
.015
11
4.3
L48-1
48
MIN
MAX
.055
.120
.045 .090
.017
.023
.072 REF
.006 .022
.554 .572
.440 Bse
.220 SSC
.500 .535
.040 sse
.015
.012 RADIUS
.020 REF
.033 .047
.033 .047
.077 .093
.003
.015
12
11
L3
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS (Continued)
52-68 LEAD LCC (SQUARE)
DWG#
1# OF LDS (N)
SYMBOL
A
A1
B1
B2
B3
DIE
D1/E1
D2/E2
D3/E3
e
e1
h
J
L
l1
L2
L3
ND/NE
L52-1
52
MAX
MIN
.087
.061
.051
.077
.022 .028
.072 REF
.006 .022
.761
.739
.600 Bse
.300 Bse
.661
.050 Bse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.015
.003
13
L52-2
52
MIN
MAX
.082
.120
.072 .088
.022 .028
.072 REF
.006
.022
.739
.761
.600 Bse
.300 Bse
.661
.050 Bse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.075
.093
.003
.015
13
L68-2
68
MIN
MAX
.082 .120
.072 .088
.022 .028
.072 REF
.006 .022
.938 .962
.800 Bse
.400 Bse
.862
.050 Bse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.075 .095
.003
.015
17
4.3
L68-1
68
MIN
MAX
.120
.065
.055
.075
.014
.008
.072 REF
.006
.022
.554 .566
.400 Bse
.200 Bse
.535
.025 Bse
-.
.015
.040 REF
.020 REF
.045
.055
.045 .055
.077
.093
.003
.015
17
12
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS (Continued)
h X 45'
3 PL
J X 45', A1[
-+--+--
f
--l
A
D3
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN CENTERS.
20-32 LEAD LCC (RECTANGULAR)
#_
DWG #
OF LOS (N
SYMBOL
A
A1
Sl
S2
S3
D
01
D2
D3
E
E1
E2
E3
e
e1
h
J
L
L1
L2
L3
ND
NE
L20-1
20
MIN
MAX
.060 .075
.050 .065
.022 .028
.072 REF
.006 .022
.284 .296
.150 sse
.075 SSC
.280
.420 .435
.250 sse
.125 sse
.410
.050 sse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.080 .095
.003
.015
4
6
L22-1
22
MIN
MAX
.064 .100
.054 .063
.022 .028
.072 REF
.006 .022
.284 .296
.150 sse
.075 Bse
.280
.480 .496
.300 sse
.150 sse
.480
.050 Bse
.015
.012 RADIUS
.012 RADIUS
.039
.051
.039
.051
.083 .097
.003
.015
4
7
L24-1
24
MIN
MAX
.064 .120
.054 .066
.022 .028
.072 REF
.006 .022
.292 .308
.200 SSC
.100 BSC
.308
.392 .408
.300 sse
.150 SSC
.408
.050 sse
.015
.025 REF
.015 REF
.040 .050
.040 .050
.077 .093
.003
.015
5
7
4.3
+
L28-2
28
MIN
MAX
.120
.060
.050 .088
.022 .028
.072 REF
.006 .022
.342 .358
.200 sse
.100 sse
.358
.540 .560
.400 Bse
.200 sse
.558
.050 sse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003 .015
5
9
-
.
~L3
B3~
0
L32-1
32
MAX
MIN
.060
.120
.050 .088
.022 .028
.072 REF
.006 .022
.442 .458
.300 Bse
.150 Bse
.458
.540 .. 560
.400 sse
.200 sse
.558
.050 sse
.015
.040 REF
.020 REF
.045 .055
.045 .055
.077 .093
.003
.015
7
9
-
13
II
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS
68 PIN PGA '(CAVITY UP)
TOP VIEW
1 2 3
L
K
J
H
4
5
7
9 10 11
0000
00000
00
00
00
G
F H-&-++-e-I-----
+
00
000
C 00
B aJ0000
A
0000
E
1~14
#
8
E1
E
~1_j
G68-1·
DWG #
OF PINS eN)
·6B .
.' MIN
SYMBOL
MAX
.' .070 .. 145
A
f6B
.016
.020
f6B1
.OBO·
.060
f6B2
.040
1.140
1.180
DIE
'1.000 BSC
D1/E1
e
.100BSC
.120 . .140
L
M
11
Q
.040
.060'
-
-,
PIN 1 10
NOTES:
. 1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL· "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMB'OL "N" REPRESENTS THE NUMBER OF PINS
'5~ CHAMFERED CORNERS ARE lOT'S OPTION.
4.3
14
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
68 PIN PGA (SMALL OUTLINE - CAVITY UP)
TOP VIEW
¢B1
1
2
3
4
5
7
8
9 10 11
+
E1
E
-I
PIN 1 10
SEATING PLANE
#
DWG #
OF PINS eN)
SYMBOL
A
¢B
¢B1
¢B2
DIE
D1/E1
e
L
M
Q
G68-3
68
MIN
MAX
.070
.145
.016
.020···
. 040
.080
.040
.060
1.080
1.135
1.000 BSC
.100 BSC
.120
.140
11
.040
.060
NOTES:
,
1. ALL DIMENSIONS ARE IN,INCHES, UNLESS:'OTHERWISE
' .'
,.:'
,.
.
SPECIFIED.
2.
3.
4.
5.
BSC - BASIC LEAD SPACING BETWEEN CENTERS.
SYMBOL "M" REPRESENTS THEPGA MATRIX' SIZE •
SYMBOL "N" REPRESENTS THE' NUMBER OF PINS
CHAMFERED CORNERS,· ARE lOT'S OPTION.
4.3
15
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
68 PIN PGA (CAVITY DOWN)
TOP VIEW
¢B1
12345
L
0000
K00000
J00
H00
G00
F-++&--I+&--~-
+
-I
E1 E
E00
00
000
00
c00
00
Bffi0000 0000EB
A
0000 000EB-+-+-......LI.~I.--- ~1 ---~.I.I
PIN 1 ID
...---------,
[01
I .
~ f ~~nrmnnf~
SEATING PLANE
¢B2~ ~ ~~¢B
DWG #
D_ OF PINS (Nl
SYMBOL
A
¢B
¢B1
¢B2
DjE
D1/E1
e
L
M
01
G68-2
68
MIN
MAX
.077
.095
.016
.020
.060
.080
.040
.060
1.098 1.122
1.000 BSC
.100 BSC
.120
.140
11
.025
.060
I
~
~ e~
A
I
NOTES:
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOT'S OPTION.
1.
4.3
16
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
144 PIN PGA (CAVITY UP -
R3001)
TOP VIEW
BOTTOM VIEW
1234567
R0000000
p0000000
N0000000
M000
L000
K000
J000
H000
c000
EXTRA PIN
E000 /
000
00000
000
c0000000 0000000
80000000 0000000
000000 000000
+
PIN 1 I D J
J1
DWG #
OF PINS (N)
SYMBOL
A
¢B
¢B1
¢B2
OLE
D1/E1
e
L
M
Q
G144-2
145
MIN
MAX
.082
.125
.016
.020
.060
.080
•040
.060
1.559 1.590
1.400 BSC
.100 BSC
.120
.140
15
.040
.060
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS .
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDr'S OPTION •
6. EXTRA PIN (D-4) ELECTRICALLY CONNECTED TO D-3 .
4.3
17
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
208 PIN PGA (CAVITY DOWN)
~81
BOTTOM VIEW
--~~~~~E1E
I~._I.._______ ~1 ========-=--=--:~
#
DWG #
OF PINS (N)
SYMBOL
A
¢B
¢B1
¢B2
DIE
D1/E1
e
, L
M
Q1
G208-2
208
MIN
MAX
.070
.145
.020
.016
.080
.040
.060
1.732
1.780
1.600 BSC
. .100 BSC
. 140
.120
17
.025
.060
TOP VIEW'
4----------
+
PIN 1
IDJ
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED:
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE lOT'S OPTION .
4.3
18
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES
16-32 LEAD PLASTIC DIP (300 MIL)
Ur-fS
----+-+--------.
01
TI
~
II
PLANE
L
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
1#
DWG #
OF LDS (N)
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
O!
S
Q1
MIN
.140
.015
.015
.050
.008
.745
.300
.247
.090
.310
.120
0'
.015
.050
P16-1
16
MAX
.165
.035
.022
.070
.012
.760
.325
.260
.110
.370
.150
15'
.035
.070
P22-1
P28-2
22
28
MIN
.145
.015
.015
.050
.008
1.050
.300
.240
.090
.310
.120
0'
.020
.055
MAX
.165
.035
.022
.065
.012
1.060
.320
.270
.110
.370
.150
15'
.040
.075
4.3
MIN.145
.015
.015
.045
.008
1.345
.300
.270
.090
.310
.120
0'
.020
.055
P32-2
32
MAX
.180
.030
.022
.065
.015
1.375
.325
.295
.110
.400
.150
15'
.042
.065
MIN
.145
.015
.016
.045
.008 '
1.545
.300
.275
.090
.310
.120
0'
.020
.055
MAX
.180
.030
.022
.060
.015
1.585
.325
.295
.110
.4·00
.150
15'
.060
.065
19
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
18-24 LEAD PLASTIC DIP (300 MIL -
[ : : : :0: : : ~
US
FULL LEAD)
,t
E1
E
t t
i
1
~
Q1
TI
PLANE
L
C
-qe~
I
----I
eA
NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2. 0 & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
OWe, #
P18-1
P20-J
# OF LOS \N)
18
20
SYMBOLS
L
MIN
.140
.015
.015
.050
.008
.885
.300
.247
.090
.310
.120
S
Q1
.040
.050
A
Al
b
bl
C
0
E
El
e
eA
a
O·
MAX
.100
.035
.020
.070
.012
.910
.325
.260
.110
.370
.150
15·
.060
,070
MIN
.140
.015
.015
.050
.008
1.022
.300
.240
.090
.310
.120
O·
.025
.055
P24-1
24
MAX
.100
.035
.020
.070
.012
1.040
.325
.280
.110
.370
.150
15·
.070
,075
4.3
MIN
.140
.015
.015
.050
.008
1.240
.300
.250
.090
.310
.120
O·
.055
.055
MAX
.100
.035
.020
.065
.012
1.255
.320
.275
.110
.370
.150
15·
.075
.070
20
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
28 & 32 LEAD PLASTIC DIP (400 MIL)
~ Et
t t
E1
US
Ell
b~
Q1
TI
PLANE
L
C
Ljef-
I
---i
I
eA
~
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
#
DWG :It
OF LEADS (N
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
Oc:
S
Q1
P?8-3
28
MAX
MIN
.210
.015
.014
.022
.045
.065
.009
.015
1.380 1.420
.390
.425
.340
.390
.100 BSC
.400 BSC
.115
.160
O·
15·
.040
.070
.060
.090
P~?-3
32
MIN
-
.015
.014
.045
.009
1.610
.390
.340
.100
.400
.115
o·
.040
.060
MAX
.200_
-
.022
.065
.015
1.620
.425
.390
BSC
SSC
.160
15·
.070
.090
4.3
21
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
24-48 LEAD PLASTIC DIP (600 MIL)
t Et
t t
E1
US
~----------~~------------~
01
~
TIL.
I
~
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
1#
I1WG JJ
OF LEADS (N
SYMBOLS
A
A1
b
b1
C
0
E
E1
e
eA
L
ex
S
01
P?4-?
24
MIN
MAX
.160
.185
.015
.035
.015
.020
.050
.065
.008
.012
1.240 1.260
.600
.620
.530
.550
.090
.110
.610
.670
.120
.150
O·
15·
.060
.080
,080
.060
P32-1
'32
MIN
MAX
.190
.170
.050
.015
.020
.016
.045
.055
.012
.008
1.645 1.655
.625
.600
.530
.550
.090
.110
.610
.670
.125
.135
15·
.080
.070
.075
.065
P?8-1
28
MIN
MAX
.160
.185
.015
.035
.015
.020
.050
.065
.008
.012
1.420 1.460
.600
.620
.530
.550
.090
.110
.610
.670
.120
.150
o·
15·
.055
.080
.060
.080
o·
4.3
P40-1
40
MAX
MIN
.185
.160
.035
.015
.020
.015
.065
.050
.008
.012
2.070
2.050
.620
.600
.530
.550
.090
.110
.610
.670
.120
.150
o·
15·
.085
.070
.080
.060
P48-1
48
MIN
MAX
.170
.200
.015
.035
.015
.020
.050
.065
.008
.012
2.420 2.450
.600
.620
.530
.560
.090
.110
.610
.670
.120
.150
O·
15·
.060
.075
.060
.080
22
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
64 LEAD PLASTIC DIP (900 MIL)
I~
D
)
~
,t
E1
\
"'"\..r"
"'"\..r"
E
t t
"'"\..r"
PLANE
. I
~
eA
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED."
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
#
DWG #
OF LEADS (N)
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
ex
S
Q1
" P64-1
64
MIN
MAX
.1BO
.230
.015
.040
" .015
.020
.050
.065
.OOB
.012
3.200
3.220
.900
.925
.790
.B10
.090
.110
.910
1.000
.120
.150
O·
15·
.045
.065
.OBO
.090
4.3
23
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE Ie
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE .
•
PIN 1
e
immJ=t
-i I-B
hft~~~
A1 " -
SEATING PLANE
--l IL
ex
J
16-24 LEAD SMALL OUTLINE (GULL WING - JEDEC)
DWG
'#
#
OF LOS (N)
S016-1
S018-1
S020-2
S024-2
16 (.300)
18 (.300)
20 (.300")
24 (.300")
SYMBOL
MIN
MAX
A
.095
.1043
A1
.005
B
MIN
MAX
MIN
MAX
MIN
MAX
.095
.1043
.095
.1043
.095
.1043
.0118
.005
.0118
.005
.0118
.005
.0118
.014
.020
.014
.020
.014
.020
.0.14
.020
e
.0091
.0125
.0091 .0125
.0091
0125
.0091 .0125
D
.403
.413
.447
.497
.511
e
.050 8se
.462
.050 8se
E
.292
.2992
h
.010
.020
.010
H
.400
.419
L
.018
.045
ex
o·
S
.023
.292 .2992
;050 8se
.600
.614
.050 Bse
.292
.2992
.292
.2992
.020
.010
.020
.010
.020
.400
.419
.400
.419
.400
.419
.018
.045
.018 ' .045
.018
.045
8·
o·
8·
o·
8·
o·
8·
.035
.023
.035
.023
.035
.023
.035
4.3
24
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE •
•
PIN 1
e
~r, frlt-~=]
h
----11-8
Ii:
AlIT
SEATING
PLA~E J
28 LEAD SMALL OUTLING (GULL WING DWG #
1#
S028-2
28 (.300")
28 (.330")
MIN
MAX
MIN
MAX
A
.095
.1043
.110
.120
A1
.005
.0118
.005
.014
B
.014
.020
.014
.019
e
.0091
.0125
.006
.010
D
e
.700
.712
.718
.728
E
.292
.2992
.050 BSe
JEDEC)
S028-3
SYMBOL
OF LDS (N)
----kl-
.050 BSe
.340
.350
h
.010
.020
.012
.020
H
.400
.419
.462
.478
L
.018
.045
.028
.045
8'
.035
ex
0'
8'
O·
S
.023
.035
.023
4.3
25
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
•
PIN 1
e
~=th~w~§J
----11-8 . A1"- ~
-IL~
SEATING
PLA~E J
'
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS' AND TO BE
MEASURED FROM THE BOTTOM OF THE PACKAGE.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER
WITHIN .004" AT THE SEATING PLANE.
16-24 LEAD SSOP (EIAJ tiL
DWG #
OF LDS iN)
SYMBOLS
A
A1
B
C
D
E
e
H
L
ex
S016-6
16
MIN
MAX
1.70 2.10
.08
.35
.45
.12
.18
10.10 10.30
5.00 5.60
1.27 BSC
7.60 8.00
.65
.85
12· REF
1.27 LEAD PITCH)
S020-6
20
MIN
MAX
1.75
2.10
.05 TYP
.30
.50
.15
.25
12.20 12.80
5.20
5.60
1.27 Bse
7.62
8.10
.25
O·
8·
S024-6
24
MAX
MIN
1.75
2.10
.05 TYP
.50
.30
.15
.25
14.70 15.30
5.20
5.60
1.27 Bse
7.62
8.10
.25
8·
O·
4.3
26
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
m
N
E1
E
~.~lli
~----
NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. D1 & E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSION AND TO BE MEASURED
FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004';
AT THE SEATING PLANE
II
01------.;
-~c
.. I
20-32 LEAD SMALL OUTLJNE (J- BEND, 300 MIL)
#
OWG #
OF LOS (N)
SYMBOLS
A
A1
B
B1
e
D1
E
E1
E2
e
h
S
S020-1
20
MAX
MIN
.120
.140
.078
.095
-
-
.014
.020
.008
.013
.500
.512
.335
.347
.292
.300
.262
.272
.050 Bse
.010
.020
.023
.035
S024-4
24
MIN
MAX
.130
.148
.082
.095
.026
.032
.015
.020
.007
.011
.620
.630
.335
.345
.305
.295
.260
.280
.050 sse
.010
.020
.032
.043
S024-8
24
MIN
MAX
.120
.140
.078
.091
-
-
.014
.019
.0125
.0091
.602
.612
.335
.347
.292
.299
.262
.272
.050 sse
.010
.016
.032
.043
4.3
S028-5
28
MIN
MAX
.140
.120
.078
.095
-
-
.020
.014
.013
.008
.712
.700
.335
.347
.292
.300
.262
.272
.050 sse
.020
.012
.023
.035
S032-2
32
MIN
MAX
.130
.148
.095
.082
.032
.026
.016
.020
.008
.013
.820
.830
.330
.340
.295
.305
.260
.275
.050 sse
.012
.020
.032
.043
27
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
48 & 56 LEAD SSOP (JEDEC)
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE.
N
SEATING
DWG
#
#
OF LDS (N)
~! ~--...r.~
PLA~E
S048-1
MIN
-II-
56 (.300")
MAX
MIN
A
.095
.110
.095
.110
A1
.008
.016
.008
.016
b
.008
.012
.008
.012
MAX
C
.005
.009
.005
.009
D
.620
.630
.720
.730
E
.291
.299
.291
.299
e
.025 BSC
.025 BSC
H
.395
.420
.395
.420
h
.015
.025
.015
.025
L
.020
.040
.020
.040
O·
8·
O·
8·
ex
L
S056-1
48 (.300")
SYMBOL
]
4.3
28
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
•
PIN 1
e
~f,
8
----11-
hX45'~H=fI
E
t
A,tT
SEATING
II
=finE
=kJ
-t
I-
PLA~~J
-lL
a
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .10mm AT THE SEATING PLANE.
20 & 24 LEAD SSOP (EIAJ -
lit
DWG #
OF LOS iN)
SYMBOLS
A
A1
B
C
D
E
e
H
L
ex.
S020-7
20
MIN
MAX
1.73
1.99
.05
.21
.25
.38
.13
.22
7.07
7.33
5.20
5.38
.65 SSC
7.65
7.90
.55
.95
0'
8'
.65 LEAD PITCH)
S024-7
24
MIN
MAX
1.73
1.99
.05
.21
.38
.25
.13
.22
8.07
8.33
5.20
5.38
.65 SSC
7.65
7.90
.95
.55
0'
8'
4.3
29
PACKAGE DIAGRAM OUTLINES
PLASTIC QUAD FLATPACKS (Continued)
80-208 LEAD SQUARE PLASTIC QUAD FLATPACK (EIAJ)
NOTES:
1. ALL DIMENSIONS ARE IN METRIC, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. 01 & E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS .254 PER SIDE.
4. NO & NE REPRESENT NUMBERS OF LEADS IN D & E DIRECTIONS RESPECTIVELY.
1#
DWG #
OF LOS (N)
SYMBOLS
A
A1
A2
C
DIE
D1/E1
D3/E3
L
NDJNE
P
W
ZD/zE
PQ80-1
PQ144-2
PQ160-2
PQ208-2
144
160
208
80
MIN
MAX
MIN
MAX
MIN
MAX
MAX
MIN
2.45
3.45
4.07
3.45
4.07 3.45 4.07
.25
.25
.25
.25
3.65
1.75
2.25
3.18
3.65
3.18
3.65
3.18
.13
.20
.13
.20
.13
.20
.13
.20
16.95 17.45 31.80 32.00 31.80 32.00 31.80 32.00
13.90 14.10 27.90 28.10 27.90 28.10 27.90 28.10
12.35 REF
22.75 REF
25.35 REF
25.50 REF
.65
.95
.95
.65
.95
.95
.65
.65
40/40
20/20
36/36
52/52
.65 BSC
.65 BSC
.65 BSC
.50 BSC
.22
.35
.22
.35
.22
.35
.22
.35
.82
2.62
1.32
1.25
-
>
4.3
30
PACKAGE
DIAGRA~
OUTLINES
PLASTIC LEADED CHIP CARRIERS
20-84 LEAD PLCC (SQUARE)
14---t----
45'
D
D1
---~
A1
-----I
x .045
C
E1
8
II
SEA liNG PLANE
HEATSINK OPTIONAL ONJ84-1
NOTES:
1.
2.
3.
4.
ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
BSC - BASIC LEAD SPACING BETWEEN CENTERS
0 & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE
ANOTHER WITHIN .004" AT THE SEATING PLANE.
ND & NE REPRESENT NUMBER OF LEADS IN D & E DIRECTIONS
RESPECTIVEL Y.
D1 & E1 SHOULD· BE MEASURED FROM THE BOTTOM OF THE PKG.
5.
6.
DWG #
OF LOS
SYMBOL
A
A1
B
b1
C
C1
D
01
02/E2
D3/E3
E
E1
#
e
NO/NE
J20-1
20
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.OOB .012
.385 .395
.350 .356
.290 .330
.200 REF
.385 .395
.350 .356
.050 BSC
5
J28-1
28
MIN MAX
.165 .1BO
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.485 .495
.450 .456
.390 .430
.300 REF
.485 .495
.450 .456
.050 BSC
7
J44-1
44
MIN MAX
.165 .1BO
.095 .115
.026 .032
.013 .021
.020 .040
.OOB .012
.685 .695
.650 .656
.590 .630
.500 REF
.685 .695
.650 .656
.050 BSC
11
J52-1
52
MIN MAX
.165 .1BO
.095 .115
.026 .032
;013 .021
.020 .040
.OOB .012
.785 .795
.750 .756
.690 .730
.600 REF
.785 .795
.750 .756
.050 BSC
13
4.3
J68-1
68
MIN MAX
.165 .1BO
.095 .115
.026 .032
.013 .021
.020 .040
;008 .012
.985 .995
.950 .956
.890 .930
.800 REF
.985 .995
.950 .956
.050 BSC
17
J84-1
84
MIN MAX
.165 .1BO
.095 .115
.026 .032
.013 .021
.020 .040
;008 .012
1.185 1.195
1.150 1.156
1.090 1.130
1.000 REF
1.185 1.195
1.150 1.156
.050 BSC
21
31
PACKAGE DIAGRAM OUTLINES
PLASTIC LEADED CHIP CARRIERS (Continued)
18-32 LEAD PLec (RECTANGULAR)
t
-H---
m
-----18-
E1
E
B
~ ~N_D)----t
SEATING
PLANE~
r--
I
DWG
#
OPTIONAL FEATURE
ADHESIVE PEDESTAL
(32 LD ONLY)
#
J18-1
18
OF LOS
SYMBOL
I
D2---j
MIN
J32-1
32
MAX
MIN
MAX
A
.120
.140
.120
.140
A1
.075
.095
.075
.095
8
.026
.032
.026
.032
b1
.013
.021
. 013
.021
C
.015
.040
.015
.040
C1
.008
.012
.008
.012
C2
-
-
.005
. 015
,495
0
.320
.335
.485
D1
.289
.293
.449
.453
02
.225
.265
.390
.430
03
E
.150 REF
.520
.535
.595
E1
.489
.493
.549
.553
.422
.465
.490
.530
E3
.200 REF
. .400 REF
e
.050 BSC
.050 BSC
4/5
o
o
.300 REF
.585
E2
ND/NE
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED .
2; BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
& E DO NOT INCLUDE MOLD FLASH OR
3.
PROTRUSIONS .
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE.
.
5 . NO & NE REPRESENT NUMBERS OF LEADS IN
& E DIRECTIONS RESPECTIVELY.
6. 01 & E1 SHOULD BE MEASURED FROM THE
BOTTOM OF THE PACKAGE .
7 /
9
4.3
32
DOUBLE DENSITY STANDARD 5V
LOGIC PRODUCTS
DOUBLE DENSITY STANDARD 5V LOGIC PRODUCTS
The demand for higher integration and higher speed continues to push the need for high-performance, high-density
logic families. IDT has recently introduced a new series of
extra-quiet, high-performance, 16-, 18-, and 20-bit logic functions. This exciting new Double Density family offers users
significant board area savings, power savings, higher speeds,
excellent guaranteed low noise characteristics, and guaranteed low output skew. The Double Density family is the premiere octal upgrade and is considered the high-speed, lownoise replacement for all existing CMOS and BiCMOS wide
bus width products. Because of increased system bus widths,
these bus and backplane drivers represent the next logical
step in system integration.
To better accomodate various design applications, two
output drive options are available.
64mA, High Drive Outputs
The first configuration, designated 54174FCT16XXXT, is
intended to act as a direct replacement for two high-drive octal
devices. These TTL-compatible, high drive (IOH = -32mA and
IOl = 64mA) functions were designed for use in bus and
backplane applications where heavy DC loads or termination
may exist. These high drive devices meet or exceed all
competitive BiCMOS double-wide and IDT's octal FCT-T DC
specifications.
24mA, Balanced Drive Outputs
The second configuration, designated 54174FCT162XXXT,
has new balanced drive outputs (IOH =-24mA and IOl=24mA)
with on-chip resistors. The combination of high dynamic drive
and reduced DC drive makes these low-noise, balanced drive
parts excellent for use in internal bus or motherboard designs,
where overshoot and undershoot can be a problem.
Both configurations are available in the very small 48- and
56-pin Shrink Small Outline Packages (SSOP) and ceramic
flatpacks. These fine-pitch SSOPs use approximately half the
board area of two standard octal SOICs. All devices have
been designed with flow-through pinouts and output edge rate
control circuitry, providing up to a 70% improvement in ground
bounce characteristics over older FCT octal devices. Pinouts
are compatible with existing CMOS and SiGMaS double-wide
families making system upgrades easy.
IDT's FCT-T double density devices use 40% less dynamic
power, at all operating frequencies, than any advanced
BiCMOS bus interface family, and, unlike their bipolar and
BiCMOS counterparts, do not use any power in high impedance or static states (ICCl, ICCl, ICCH).
These devices are offered in several industry standard
speed grades, FCT-T, FCT-AT, FCT-CT, and FCT-DT. All
speed specifications are consistent with IDT's octal FCT and
low-noise FCT-T devices, and are now guaranteed over an
extended temperature and voltage range.
No other technology or product family offers the performance
advantages that IDT's new Double Density family does. IDT
plans on expanding this family with additional Double Density
functions.
5.0
II
TABLE OF CONTENTS
PAGE
DOUBLE DENSITY STANDARD 5V LOGIC PRODUCTS
DOUBLE DENSITY WITH HIGH OUTPUT DRIVE
IDT54/74FCT16240T
16-Bit Inverting Buffer/Line Driver .............................................................................
IDT54/74FCT16244T
16-Bit Non-inverting Buffer/Line Driver ......................................................................
IDT54/74FCT16245T
16-Bit Non-inverting Transceiver ...............................................................................
IDT54/74FCT16373T
16-Bit Non-inverting Transparent Latch w/3-State ....................................................
IDT54/74FCT16374T
16-Bit Non-inverting Register w/3-State ....................................................................
IDT54/74FCT16500T
18-Bit Non-inverting Neg. Edge Triggered Registered Transceiver ..........................
IDT54/74FCT16501 T
18-Bit Non-inverting Pas. Edge Triggered Registered Transceiver ...........................
IDT54/74FCT16543T
16-Bit Non-inverting Latched Transceiver .................................................................
IDT54/74FCT16646T
16-Bit Non-inverting Registered Transceiver .............................................................
IDT54/74FCT16652T
16-Bit Non-inverting Registered Transceiver .............................................................
IDT54/74FCT16952T
16-Bit Non-inverting Registered Transceiver .............................................................
IDT54/74FCT16823T
18-Bit Non-inverting Register w/Clear & Reset .........................................................
IDT54/74FCT16827T
20-Bit Non-inverting Buffer w/3-State ........................................................................
IDT54/74FCT16841T
20-Bit Non-inverting Latch .........................................................................................
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
DOUBLE DENSITY WITH
IDT54/74FCT162240T
IDT54/74FCT162244T
IDT54/74FCT162245T
IDT54/74FCT162373T
IDT54/74FCT162374T
IDT54/74FCT162500T
IDT54/74FCT162501T
IDT54/74FCT162543T
IDT54/74FCT162646T
IDT54/74FCT162652T
IDT54/74FCT162952T
IDT54/74FCT162823T
IDT54/74FCT162827T
IDT54/74FCT162841 T
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
BALANCED OUTPUT DRIVE
16-Bit Inverting Buffer/Line Drive w/Resistors ...........................................................
16-Bit Non-inverting Buffer/Line Drive w/Resistors ...................................................
16-Bit Non-inverting Transceiver w/Resistors .................................................. .........
16-Bit Non-inverting Transparent Latch w/Resistors & 3-State .................................
16-Bit Non-inverting Register w/Resistors & 3-State .................................................
18-Bit Non-inverting Neg. Edge Triggered Registered Transceiver w/Resistors .......
18-Bit Non-inverting Pas. Edge Triggered Registered Transceiverw/Resistors .......
16-Bit Non-inverting Latched Transceiver w/Resistors ..............................................
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
16-Bit Non-inverting Registered Transceiver w/Resistors .........................................
18-Bit Non-inverting Register w/Resistors, Clear, & Reset .......................................
20-Bit Non-inverting Buffer w/Resistors & 3-State .....................................................
20-Bit Non-inverting Latch w/Resistors .....................................................................
5.0
II
3
f;J
FAST CMOS 16-BIT
BUFFER/LINE DRIVER
IDT54/74FCT16240T/AT/CT
..' . .
,
.
IDT54/74FCT162240T/AT/CT
'
,
.
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
The - IDT54/74FCT16240T/AT/CT and IDT541
74FCT162240T/AT/CT 16-bit buffer/line drivers are built
using advanced CEMOS, dual metal CMOS technology. 'These
high-speed, low-power devices offer bus/backplane interface
capability with improved packing density. These devices have
a flow-through organization for ease of board layout. The
three-state controls are designe9 to operate these devices in
a Quad~Nibble, Dual-Byte or single 16-bit word mode. All
inputs are designed with hysteresis for improved noise margin.
.
The IDT54/74FCT16240T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off disable papabilityto allow "live insertion" of boards when used as backplane
drivers ..
. The IDT54174FCT162240T/AT/CT have balanced .output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled outputfall timesreducing the need for external series terminating resistors.
The IDT54174FCT162240T/AT/CT are plug-in replacements
for 'I DT54/74FCT16240T1AT/CT and 54/74ABT16240 for on, board interface applications. '
-
0.5 MICRON CEMOSTM Technology
High-speed, low-power CEMOS replacement for
ABT functions
- Typical tSK(O) (Output Skew) < 250ps
- ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
Vee = 5V±100/0
- Speed grades same as FCT-T Octals
• Features for FCT16240TlAT/CT:
- High drive outputs (-32mA IOH, 64mA loL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162240T/AT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
FUNCTIONAL BLOCK DIAGRAM
10E
1A1
1A3
1A4
20E
2A1
2Y1
2A2.
2Y2
2A3
2Y3
2A4
2Y4
4Y3
2541 drw 02
2541 drw 01
CEMOS is a trademark of Integrated Devioe Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<1:)1992 Integrated Devioe Technology. Inc.
5.1
MAY 1992
DSC-422613
1
5
IDT54174FCT16240T/AT/CT,162240T/AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
10E
1Y1
2
47
20E
10E
1
48
20E
1A1
1'(1
2
47
lAl
1Y2
3
46
1A2
GND
4
45
GND
1YS
5
44
1'(4
6
Vee
2Yl
2'(2
1'(2
3
46
lA2
GND
4
45
GND
lAs
1'(3
5
44
lA3
43
.lA4
lY4
6
43
lA4
7
42
Vee
Vee
7
42
Vee
8
41
2Al
2'(1
8
41
2Al
9
40
2A2
2Y2
9
40
2A2
GND
10
39
GND
GND
10
39
GND
2'(S
1.1
38
2Aa
{Ya
11
38
2A3
2Y4
12 8048-1
37
2A4
2'14
12
a'(l
13
36
aA1
aYl
a'(2
14
35
aA2
GND
15
34
GND
a'13
16
33
3A3
s'14
17
32
aA4
Vee
18
31
Vee
30
4A1
4'(1
37
2A4
13
36
3Al
aY2
14
35
aA2
GND
15
34
GND
a'(a
16
33
aA3
aY4
17
32
3A4
Vee
18
31
Vee
19
30
4Al
4Y2
20
29
4A2
GND
21
28
GND
E48-1
4'11
19
4'12
20
29
4A2
GND
21
28
GND
4'13
22
27
4Aa
4'1a
22
27
4Aa
4Y4
23
26
4A4
4Y4
23
26
4A4
45E
24
25
aGE
40'E'
24
25
30E
2541 drw 03
2541drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
5.1
2
IDT54174FCT16240T/AT/CT, 162240TIAT/CT
FAST CMOS 16·BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
In~ uts
xAx
Outputs
x\{x
L
L
H
L
H
L
H
X
Z
Description
Pin Names
xOE
3-State Output Enable Inputs (Active LOW)
xAx
x\{x
Data Inputs
3-State Outputs
xOE"
2541 tblOl
NOTE:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Ratin~
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
VTERM(2) Terminal Voltage
with Respect to
GND
-{l.5 to +7.0
-{l.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect to
GND
-{l.5 to Vee
-{l.5 to Vee
V
Symbol
2541 tbl02
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
4.5
6.0
pF
GoUT
Output
Capacitance
VOUT= OV
5.5
8.0
pF
Symbol
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TSIAS
Temperature
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
2541 Ink 04
Under Bias
TSTG
Storage
II
Temperature
PT
Power Dissipation
lOUT
DC Output
1.0
1.0
W
-60 to +120
-60 to +120
rnA
Current
NOTES:
2541 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speCification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.1
3
IDT54174FCT16240T/AT/CT,162240T/AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, Vee = 5.0V +
- 10%; Military: TA = -55°C to +125°C , Vee= 5 OV +
- 10%
Parameter
Input HIGH Level
Test Conditlons(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IiH
Input HIGH Current (Input pins)
Vee = Max.
Symbol
VIH
VI = Vee
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
VI = GND
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
los
Short Circuit Current
Vee = Max., VA
Vee = Max .. VA = 2.5V(3)
10
Output Drive Current
input Hysteresis
leeL
leeH
leel
Quiescent Power Supply Current
-
-
Input LOW Current (1/0 pins)
VH
Min.
2.0
Vee = Max.
Vo= 2.?V
Vo= 0.5V
= GND(3)
Vee = Max .• VIN
= GND or Vee
TVp.(2)
Max.
-
-
V
0.8
V
-
±5
~
±15
-
Unit
±5
±15
-
-D.?
-1.2
V
-80
-140
-200
-50
-
-180
rnA
rnA
-
100
-
mV
0.05
1.5
rnA
±10
~
±10
2541 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16240T
Symbol
VOH
Parameter
Output HIGH Voltage
Vee= Min.
Test Condltlons(1)
10H=-3mA
10H = -12mA MiL.
10H .. -15mA COM'L.
10H = -24mA MIL.
10H = -32mA COM'U4)
Vee = Min.
10L= 48mA MIL.
10L= 64mA COM'L.
VIN = VIH or VIL
Vee = OV, VIN or Va::; 4.5V
VIN = VIH or VIL
VOL
Output LOW Voltage
10FF
Input/Output Power Off Leakage
Min.
2.5
Typ,(2)
2.4
Max.
Unit
V
3.5
-
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
3.5
V
V
~
2541 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162240T
Symbol
10DL
Parameter
Output LOW Current
Test Conditlons(1)
Vee = 5V. VIN = VIH or VIL. VOUT = 1.5V(3)
Min.
60
TVp'(2)
115
Max.
150
10DH
Output HIGH Current
Vee = 5V. VIN = VIH or V IL. VOUT = 1.5V(3)
-60
-115
-150
VOH
Output HIGH Voltage
2.4
3.3
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
Vee = Min.
VIN = VIH or VIL
-
0.3
IOH =-16mA MIL.
10H = -24mA COM'L.
10L= 16mA MIL.
IOL =24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.1
0.55
Unit
rnA
rnA
V
V
2541 Ink 07
4
IDT54n4FCT16240T/AT/CT,162240T/AT/CT
FAST CMOS 16·BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Alee
leeD
Typ.(2)
Max.
Unit
-
0.5
1.5
rnA
VIN = Vee
VIN = GND
-
60
100
VIN =- Vee
VIN = GND
-
0.7
2.5
VIN = 3.4V
VIN = GND
-
0.9
3.3
VIN = Vee
VIN = GND
-
2.5
5.5(5)
VIN = 3.4V
VIN = GND
-
6.5
17.5(5)
Test Condltlons(1)
Parameter
Quiescent Power Supply Current
TIL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
xOE=GND
Min.
IlAi
MHz
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
Vee = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
x"OE= GND
rnA
One Bit Toggling
Vee = Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
x"OE=GND
Sixteen Bits Toggling
2541 tblOS
NOTES:
1.
2.
S.
4.
5.
6.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TTL driven input (VIN = S.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .alcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCL, ICCH and Iccz)
t.lcc = Power Supply Current for a TTL High Input (VIN = S.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
II
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16240Tl162240T
Com'l.
Symbol
Parameter
FCT16240ATI162240AT
Mil.
Com'l.
FCT16240CT/162240CT
Com'l.
Mil.
Mil.
Conditlon(l) Min.<2) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Unit
1.5
B.O
1.5
9.0
1.5
4.B
1.5
5.1
1.5
4.3
1.5
4.7
ns
Output Enable Time
1.5
10.0
1.5
10.5
1.5
6.2
1.5
6.5
1.5
5.B
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
9.5
1.5
10.0
1.5
5.6
1.5
5.9
1.5
5.2
1.5
5.7
ns
tSK(O)
Output Skew(3)
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
ns
tPLH
tPHL
Propagation Delay
xAx to x'(x
tPZH
tPZL
CL = 50pF
RL = 500n
NOTES:
2541 tbl09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
S. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.1
5
~
FAST CMOS 16-BIT
BUFFER/LINE DRIVER
IDT54174FCT16244TIAT/CT
IDT54/74FCT162244T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
- 0.5 MICRON CEMOSTM Technology
- High-speed, low-power CEMOS replacement for
ABT functions
- . Typical tSK(O) (Output Skew) < 250ps
- ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF,R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
Vee = 5V±10%
- Speed grades same as FCT-T Octals
• Features for FCT16244T/AT/CT:
- High drive outputs (-32mA IOH, 64mA IOL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162244T/AT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
The IDT54/74FCT16244T/AT/CT and IDT541
74FCT162244T/AT/CT 16-bit buffer/line drivers are built
using advanced CEMOS, dual metal CMOS technology. These
high-speed, low-power devices offer bus/backplane interface
capability with improved packing density. These devices have
a flow-through organization for ease of board layout. The
three-state controls are designed to operate these devices in
a Quad-Nibble, Dual-Byte or single 16-bit word mode. All
inputs are designed with hysteresis for improved noise margin.
The IDT54/74FCT16244T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off disable capability to allow "live insertion" of boards when used as backplane
drivers.
The IDT5417 4FCT162244T/AT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54174FCT162244T/AT/CT are plug-in replacements
for the IDT54/74FCT16244T/AT/CT and 54/74ABT16244 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
sOE
10E
1A1
1Y1
3A1
3Y1
1A2
1Y2
3A2
3Y2
1A3
1Y3
3A3
3Y3
1A4
1Y4
3A4
3Y4
20E
40E
2A1
2Y1
4A1
4Y1
2A2
2Y2
4A2
4Y2
.... 2A3
2Y3
4A3
4Y3
2Y4
4A4
2A4
2544drwOl
4Y4
, 2544 drw 02
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101992 Integrated Device Technology, Inc.
5.2
MAY 1992
OSC-422713
1
IDT54174FCT16244T/AT/CT,162244T/AT/CT
FAST CMOS 16·BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
lOE
20E
10E
1
48
20E
1Y1
2
47
1A1
1Y1
2
47
1A1
1Y2
3
46
1M
1Y2
3
46
1A2
GND
4
45
GND
lY3
5
44
1A3
GND
4
45
GND
1Y3
5
44
1A3
1Y4
6
43
1A4
1Y4
6
43
1A4
Vee
7
42
Vee
Vee
7
42
Vee
2Y1
8
41
2A1
2Y1
8
41
2A1
2Y2
9
40
2A2
2Y2
9
40
2A2
GND
1Q
39
GND
GND
10
39
GND
2Y3
11
38
2A3
2Y3
11
38
2A3
2Y4
12 S048-1 37
2A4
2Y4
12
37
2A4
3Y1
13
36
3A1
3Y1
13
36
3A1
3Y2
14
35
3A2
GND
15
34
GND
3Y3
16
33
3Y4
17
Vee
18
E48-1
3Y2
14
35
3A2
GND
15
34
GND
3A3
3Y3
16
33
3A3
32
3A4
3Y4
17
32
3A4
31
Vee
Vee
18
31
Vee
4Y1
19
30
4A1
4Y1
19
30
4A1
4Y2
20
29
4A2
4Y2
20
29
4A2
GND
21
28
GND
GND
21
28
GND
4Y3
22
27
4A3
4Y3
22
27
4A3
4Y4
23
26
4A4
4Y4
23
26
4A4
40E
24
25
30E
40E
24
25
30E
2544 drw03
2544 drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
5.2
2
II
IDT54174FCT16244T/AT/CT,162244T/AT/CT
FAST CMOS 1s.:.BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xUE
xAx
xYx
xAx
Outouts
xYx
L
Im:uts
Descrllttlon
3-State Output Enable Inputs (Active LOW)
x'OE
Data Inputs
L
L
3-State Outputs
L
H
H
H
X
Z
2544 tbl 01
2544tbl02
NOTE:
1. H '" HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Rating
Commercial
Symbol
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage. --0.5 to Vee
with Respect to
GND
-40 to +85
Operating
TA
Temperature
":'55 to +125
TBIAS
Temperature
Under Bias
TSTG
PT
lOUT
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Military
-0.5 to +7.0
Unit
V
-0.5 to Vee
V
-55 to +125
°C
-65 to +135
°C
-65 to +150
°C
ov
Storage
Temperature
Power Dissipation
-~5
1.0
1.0
W
DC Output
Current
-60 to +120
-60 to +120
mA
to +125
Parameter(1)
Typ. Max. Unit
Conditions
Symbol
6;0
4.5
pF
Input
CIN
VIN = OV
Capacitance
VOUT ...
8.0
5.5
pF
CoUT
Output
Capacitance
NOTE:
_
2544 Ink 04
1. This parameter is measured at characterization but not tested.
NOTES: 2544 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated In the operational sections of this specification is
not implied. E;xposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
.-
5.2
3
IDT54n4FCT16244T/AT/CT,162244T/AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to + 125°C, Vcc= 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditlons(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee = Max.
VI = Vee
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
VI= GND
Input LOW Current (1/0 pins)
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
Vee = Max.
Vo= 2.7V
I··
Min.
2.0
-
-
Typ.(2)
Max.
-
-
Unit
V'
-
' 0.8
V
-
' ±5
~
-
±15
±5±15
±10
~
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
-
100
-
mV
0.05
1.5
rnA
10
Output Drive Current
VH
Input Hysteresis
leeL
leeH
leel
Quiescent Power Supply Current
Vo= 0.5V
Vee = Max., VIN = GND or Vee
±10
-0.7
-1.2
V
-140
,-200
rnA
mA
2~41nk05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16244T
Symbol
VOH
Parameter
Output HIGH Voltage
Vee = Min.
Test Condltlons(1)
10H=-3mA
VIN = VIH or VIL
VOL
Output LOW Voltage
10FF
InpuVOutput Power Off Leakage
10H = -12mA MIL.
10H = -15mA COM'L
10H = -24mA MIL.
10H = -32mA COM'U4)
10L= 48mA MIL.
Vee= Min.
VIN = VIH or VIL
10L= 64mA COM'L.
Vee = OV, VIN or Vo ::;; 4.5V
Min.
2.5
Typ'<2)
3.q
-
Unit
V
2.4
3.5
-
V
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
Max.
V
~
2544 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162244T
Symbol
10DL
Parameter
Output LOW Current
Test Condltlons(1)
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min.
60
Typ'<2)
115
Max.
150
Unit
rnA
10DH
Output HIGH Current
Vee = 5V, VIN= VIHor VIL, VOUT= 1.5V(3)
-60
-115
.:-150
rnA
VOH
Output HIGH Voltage
2.4
3.3
-
V
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
Vee= Min.
VIN = VIH or VIL
-
0.3
IOH=-16mAMIL.
IOH=-24mA COM'L.
,IOL= 16mA MIL.
10L = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable deviCe type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.2
0.55
,v
2544 Ink 07
4
II
IDT54174FCT16244T/AT/CT,162244T/AT/CT
FAST CMOS 16·BIT BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Condltlons(1)
Typ'(2)
Max.
Unit
-
O.S
1.S
rnA
VIN = Vee
VIN = GND
-
60
100
Vee = Max.
Outputs Open
fi=10MHz
VIN = Vee
VIN = GND
-
0.7
2.S
SO% Duty Cycle
xOE=GND
One Bit Toggling
VIN = 3.4V
VIN = GND
-
0.9
3.3
Vee = Max.
Outputs Open
fi =2.SMHz
SO% Duty Cycle
xOE=GND
Sixteen Bits Toggling
VIN = Vcc
VIN = GND
-
2.S
5.5(5)
VIN = 3.4V
VIN = GND
-
6.S
17.S(5)
Parameter
Symbol
~Iee
Quiescent Power Supply Current
TIL Inputs HIGH
Vee = Max.
VIN = 3.4v(3)
IceD
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
x'OE" = GND
Min.
f!N
MHz
One Input Toggling
SO% Duty Cycle
Ie
Total Power Supply Current(6)
rnA
25441bl08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven Input (ViN .. 3.4V); all other Inputs at Vce or GND.
4. This parameter Is not directly testable, but is derived for use In Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formUla. These limits are guaranteed but not tested.
6. Ic .laulEscENT + IINPUTS + IDYNAMIC
Ic. Icc + Alec DHNT + IceD (fcpNcp/2 + fiNI)
Icc - Quiescent Current (leeL, leeH and leez)
Alec .. Power Supply Current for a TTL High Input (VIN .. 3.4V)
DH - Duty Cycle for TTL Inputs High
NT .. Number of TTL Inputs at DH
ICCD .. Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp .. Number of Clock Inputs at fop
fi .. Input Frequency
Ni .. Number of Inputs at fi
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16244T/162244T
Com'l.
Symbol
Paramoter
FCT16244AT/162244AT
Com'l.
Mil.
FCT16244CTI162244CT
Mil.
Com'l.
Mil.
Condltlon(1) Mln.!2) Max. Mln.!2) Max. Min.!2) Max. Min.!2) Max. MinP) Max. Min.(2) Max. Unit
1.S 4.8
1.5 S.1
1.S 4.1
1.S 4.6 ns
CL = SOpF
1.S 6.S
1.S 7.0
RL = soon
1.5 5.8
1.5 6.5 ns
1.5 8.S
1.5 6.2
1.5 6.S
1.S 8.0
tPLH
tPHL
tPZH
tPZL
Propagation Delay
xAxto xYx
Output Enable Time
tPHZ
tPLZ
tSK(O)
Output Disable Time
1.S
7.0
1.5
7.S
1.S
S.6
1.S
S.9
1.5
5.2
1.S
S.7
Output Skew(3)
-
0.5
-
O.S
-
0.5
-
O.S
-
0.5
-
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.2
ns
ns
2544 Ibl 09
5
~®
FAST CMOS 16-BIT
BIDIRECTIONAL
TRANSCEIVERS
IDT54/74FCT16245T/AT/CT
IDT54174FCT162245T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
The IDT54/74FCT16245T/AT/CT and IOT541
74FCT162245T/AT/CT 16-bit transceivers are built using
-
0.5 MICRON CEMOSTM Technology
-
High-speed, low~power CEMOS replacement for
ABT functions
Typical tSK(O) (Output Skew) < 250ps
-
advanced CEMOS, dual metal CMOS technology. These
high-speed, low-power transceivers are ideal for synchronous
communication between two busses (A and B). The Direction
and Output Enable controls are designed to operate these
devices as either two independent 8-bit transceivers or one
16-bit transceiver. The direction control pin (xDIR) controls
the direction of data flow. The output enable pin (xOE)
overrides the direction control and disables both ports. All
inputs are designed with hysteresis for improved noise margin.
The IDT54/74FCT16245T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
.
The IDT54174FCT162245T/AT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled outputfall timesreducing the need for external series terminating resistors.
The IDT54174FCT162245T/AT/CT are plug-in replacements
for the IDT54/74FCT16245T/AT/CT and 54/74ABT16245 for
on-board interface applications.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
25 mil Center SSOP and Cerpack Packages
Extended commercial range of -40°C to +85°C
Vee = 5V ±10%
Speed grades same as FCT-T Octals
• Features for FCT16245T/AT/CT:
-
High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit "live insertion"
Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162245T/AT/CT:
-
Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
FUNCTIONAL BLOCK DIAGRAM
1 DIR
2DIR
20E
10E
2A1
1A1
181
'281
1A2
2A2
182
282
1A3
2A3
283
183
1A4
2A4
284
184
1A5
2A5
285
185
1As
2As
28s
18s
1A7
2A7
187
287
1As
2As
18s
CEMOS is a trademark 01 Integrated Device Technology, Inc.
28s
2545 drwOl
2545 drw02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
te1992 Integrated Device Technology, Inc.
5.3
MAY 1992
DSC-422B13
1
5
IDT54174FCT16245T/AT/CT, 162245T/AT/CT
FAST CMOS 16·BIT BIDIRECnONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
10E
1DIR
1
48
10E
1B1
2
47
1A1
1B1
2
47
1A1
1B2
3
46
1A2
182
3
46
1A2
GND
4
45
GND
GND
4
45
GND
183
5
44
1A3
183
5
44
1A3
1B4
6
43
1A4
184
6
43
1A4
Vee
7
42
Vee
Vee
7
42
Vee
185
8
41
1As
185
8
41
1A5
18s
9
40
1As
186
9
40
1A6
GND
10
39
GND
GND
10
39
GND
187
11
38
1A7
187
11
38
1M
18a
12
5048·1 37
1Aa
18a
12
37
1Aa
281
13
36
2A1
281
13
36
2A1
282
14
35
2A2
282
14
35
2A2
GND
15
34
GND
GND
15
34
GND
283
16
33
2A3
283
16
33
2A3
284
17
32
2A4
284
17
32
2A4
E48-1
Vee
18
31
Vee
Vee
18
31
Vee
285
19
30
2As
285
19
30
2A5
28s
20
29
2As
286
20
29
2A6
GND
21
28
GND
GND
21
28
GND
287
22
27
2A7
287
22
27
2A7
28a
23
26
2Aa
28a
23
26
2Aa
2DIR
24
25
20E
2DIR
24
25
20E
2545 drw 03
2545 drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
5.3
2
IDT54174FCT16245T/AT/CT, 162245T/AT/CT
FAST CMOS 16-81T BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xOE"
xDIR
xAx
xBx
Inputs
Description
Output Enable Input (Active LOW)
xOE
xDIR
L
L
Direction Control Input
Outputs
Bus B Data to Bus A
Side A Inputs or 3-State Outputs
L
H
Bus A Data to Bus B
Side B Inputs or 3-State Outputs
H
X
High Z State
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
2545 Ibl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA=+25°C, f= 1.0MHz)
Svmbol
Ratin~
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
Operating
TA
Temperature
Commercial
-0.5 to +7.0
Militarv
-0.5 to +7.0
Unit
V
-0.5 to Vee
-0.5 to Vee
V
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
2545 tbl 02
Parameter(1)
Symbol
GiN
Input
Capacitance
Gila
I/O
Capacitance
Conditions
VIN = OV
Typ.
4.5
Max.
6.0
Unit
pF
VOUT= OV
5.5
8.0
pF
NOTE:
1. This parameter is measured at characterization but not tested.
1.0
1.0
W
-60 to +120
-60 to +120
rnA
2545 Ink 04
iii
NOTES:
2545 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
5.3
3
IDT54174FCT16245T/AT/CT, 162245T/AT/CT
FAST CMOS 16·BIT BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA =-40°C to +85°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to +125°C, Vcc = 5.0V± 10%
Min.
TVp.<2)
Max.
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH CUrrent (Input pins)
Vee='Max.
-
0.8
IIH
±5
~
-
±15
-
±15
-
±10
...{J.7
-1.2
V
-140
-200
mA
Symbol
VIH
Test Condltlons(1)
Parameter
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current,
Vee = Max., Vo .. GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
mA
-
100
-
mV
0.05
1.5
mA
VI = Vee
Input HIGH CUrrent (1/0 pins)
IlL
Input LOW Current (Input pins)
VI =GND
Input LOW Current (1/0 pins)
10
Output Drive Current
VH
Input Hysteresis'
lecL
lecH
lecl
Quiescent Power Supply Current
Vee = Max.
Vo=2.7V
Vo=0.5V
VCC", Max., VIN .. GND or Vec
±5
±10
~
2545 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16245T
Symbol
VOH
Min.
Typ.(2)
Vce .. Min.
10H .. --3mA
2.5
3.5
-
V
VIN '" VIH or VIL
10H '" -12mA MIL.
10H '" -15mA COM'L.
2.4
3.5
-
V
10H = -24mA MIL.
10H", --32mA COM'U4)
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
Test Condltlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
10FF
InpuVOutput Power Off Leakage
Vee", Min.
10L= 48mA MIL.
10L", 64mA COM'L.
VIN '" VIH or VIL
Vee = OV, VIN or Vo ::; 4.5V
Max.
Unit
V
~
2545 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162245T
Min.
Typ)2)
Max.
Unit
10DL
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT", 1.5V(3)
60
115
150
mA
10DH
Output HIGH Current
Vee = 5V, VIN = VIH or VIL, VOUT .. 1.5V(3)
~O
-115
-150
mA
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or VIL
10H = -16mA MIL.
10H = -24mA COM'L.
2.4
3.3
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
10L= 16mA MIL.
10L = 24mA COM'L.
-
0.3
Symbol
Parameter
Test Condltlons(1)
0.55
V
V
2545 Ink 07
NOTES:
1.
2.
3.
4.
-
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.3
4
IDT54174FCT16245T/AT/CT, 162245T/AT/CT
FAST CMOS 16·BIT BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Test Conditlons(1)
Parameter
Typ.(2)
Max.
Unit
-
o.s
1.S
rnA
60
100
Min.
~Iee
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
IceD
Dynamic Power Supply Current(4)
Vcc = Max.
Outputs Open
xOE = xDIR = GND
One Input Toggling
SO% Duty Cycle
VIN = Vee
VIN = GND
-
Vcc = Max.
Outputs Open
fi = 10MHz
SO% Duty Cycle
xOE = xDIR = GND
One Bit Toggling
VIN = Vee
VIN = GND
-
0.7
2.S
VIN = 3.4V
VIN = GND
-
0.9
3.3
VIN = Vee
VIN = GND
-
2.S
S.S(5)
VIN = 3.4V
VIN = GND
-
6.S
17.S(5)
Ie
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fi = 2.SMHz
SO% Duty Cycle
xOE = xDIR = GND
vAl
MHz
rnA
Sixteen Bit Toggling
2545tbl08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + illcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
illcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
II
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16245T/162245T
Symbol
tPLH
Parameter
tPHL
Propagation Delay
A to B BtoA
tPZH
tPZL
FCT16245AT/162245AT
Mil.
Com'!,
FCT16245CT/162245CT
Mil.
Com'l.
Mil.
Com'l.
Condition{l) Min,!2) Max. Min.<2) Max. Min,!2) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Unit
CL = SOpF
1.S
7.0
1.S
7.S
1.S
4.6
1.S
4.9
1.S
4.1
1.S
4.S
ns
Output Enable Time
xCJf: to A or B
1.S
9.5
1.5
10.0
1.S
6.2
1.S
6.S
1.S
5.8
1.S
6.2
ns
tPHZ
tPLZ
Output Disable Time
xOEto Aor B
1.S
7.S
1.S
10.0
1.S
s.o
1.S
6.0
1.5
4.8
1.S
S.2
ns
tPZH
tPZL
Output Enable Time
xDIR to A or B(3)
1.S
9.S
1.5
10.0
1.5
6.2
1.S
6.5
1.S
5.8
1.S
6.2
ns
tPHZ
tPLZ
Output Disable Time
xDIR to A or B(3)
1.S
7.5
1.5
10.0
1.S
5.0
1.S
6.0
1.S
4.8
1.S
S.2
ns
tSK(O)
Output Skew(4)
-
o.s
-
O.S
-
O.S
-
O.S
-
O.S
-
O.S
ns
RL=
soon
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.3
2545 tbl 09
5
..
. t;).
FAST CMOS 16-BIT
TRANSPARENT LATCHES
IDT54/74FCT16373TIAT/CT
IDT54/74FCT162373T/AT/CT
Integrated DeVice Technology, Inc.
FE~TURES: ;
DESCRIPTION:
• Common features:
- 0.5'MICRON CEMOSTM Technology
- High-speed; low-power CEMOS replacement for
ABT functions'
- Typical tSK(O) (Output Skew) < 250ps
- ESD> 2000V per MIL-STD-883, Method 3015;
> 200Vusing machine model (C = 200pF, R "" 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
Vee';' 5V±10%
l
- Speed grades same as FCT-T Octals
,. Features for FCT16373T/AT/CT:
- High drive outputs (-32mA IOH, 64mA loL)
- Power off disable outputs permit "live insertion"
- Typical VOlP (Output Ground Bounce) < 1.0V at
'. Vee = 5V; TA = 25°C
"
• Features for FCT162373T/AT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOlP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
The I DT54/74FCT16373T/AT/CT and IDT541
74FCT162373T/AT/CT 16-bit transparent D-type latches are
built using advanced CEMOS, dual metal CMOS technology.
These high-speed, low-power latches are ideal for temporary
storage of data. They can be used for implementing memory
address latches, 1/0 ports, and bus drivers. The Output
Enable and Latch Enable controls are organized to operate
each device as two 8-bit latches or one 16-bit latch. Flowthrough organization of signal pins facilitates ease of layout.
All inputs are designed with hysteresis for improved noise
margin.
The IDT54/74FCT16373T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
The IDT54174FCT162373T/AT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54174FCT162373T/AT/CT are plug-in replacements
for the IDT54/7 4FCT16373T/AT/CT and 54/7 4ABT16373 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
10E
2~
------ 4.5V
Max.
-
. Unit
V
V
~
2543 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162373T
Max.
Unit
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min.
60
Typ'(2)
100L
115
150
mA
100H
Output HIGH CUrrent
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or VIL
2.4
3.3
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
-
0.3
Symbol
Parameter
Test Condltlons(1)
IOH=-16mA MIL.
10H = -24mA COM'L.
10L= 16mA MIL.
10L= 24mA COM'L.
0.55
V
V
2543 Ink 07
NOTES:
1.
2.
3.
4.
-
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.4
4
II
IDT54174FCT16373T/AT/CT, 162373T/AT/CT
FAST CMOS 16-91T TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Typ.(2)
Max.
Unit
-
0.5
1.5
rnA
VIN = Vee
VIN = GND
-
60
100
Vee =Max.
Outputs Open
fi =10MHz
50% Duty Cycle
xOE"= GND
xLE = Vee
One Bit Toggling
VIN = Vee
VIN = GND
-
0.7
2.5
VIN = 3.4V
VIN = GND
-
0.9
3.3
Vee = Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
xOE=GND
xLE = Vee
Sixteen Bits Toggling
VIN = Vee
VIN = GND
-
2.5
5.5(5)
VIN = 3.4V
VIN = GND
-
6.5
17.5(5)
Test CondltJons(1)
Parameter
~Iee
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
IceD
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
xOE"= GND
One Input Toggling
50% Duty Cycle
Total Power Supply Current(6)
Ie
Min.
NOTES:
1. 'For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc a 5.0V; +25°C ambient.
3. Per TTL driven Input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie .. IQUIESCENT + !iNPUTS + IDYNAMIC
Ie = Icc + .ilcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (Iccl, IccH and Iccz)
.ilcc = Power Supply Current for a TTL High Input (VIN .. 3.4V)
DH = Duty Cycle for TTL Inputs High
NT .. Number of TTL Inputs at DH
lecD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
Ii .. Input Frequency
Ni = Number of Inputs at fi
5.4
~N
MHz
rnA
2543tbl08
5
IDT54174FCT16373TfATfCT, 162373TfATfCT
FAST CMOS 16-81T TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16373Tf162373T
Symbol
Parameter
FCT16373ATf162373AT
Mil.
Com'l.
FCT16373CTf162373CT
Mil.
Com'l.
Mil.
Com'l.
Condltlon(1) Mln,<2) Max. Mln,<2) Max. Mln,<2) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Unit
1.5
8.0
1.5
8.5
1.5
5.2
1.5
5.6
1.5
4.2
1.5
5.1
ns
Propagation Delay
xLE to xOx
2.0
13.0
2.0
15.0
2.0
8.5
2.0
9.8
2.0
5.5
2.0
8.0
ns
tPZH
tPZL
Output Enable Time
1.5
12.0
1.5
13.5
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
tPHZ
tPLZ
tsu
Output Disable Time
1.5
7.5
1.5
10.0
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
Set-up Time HIGH
or LOW, xDx to xLE
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH
or LOW xDx to xLE
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
tw
xLE Pulse Width
HIGH
Output Skew(3)
6.0
-
6.0
-
5.0
-
6.0
-
5.0
-
6.0
-
ns
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
tPLH
tPHL
Propagation Delay
xDx to xOx
tPLH
tPHL
tSK(O)
CL = 50pF
RL = 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
ns
2543 tbl 09
II
I
5.4
6
(;J
FAST CMOS 16-81T
REGISTER (3-STATE)
IDT54/74FCT16374T/AT/CT
IDT54174FCT162374T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
- 0.5 MICRON CEMOSTM Technology
- High-speed, low-power CEMOS replacement for
ABT functions
" Typical tSK(O) (Output Skew) < 250p~
- ESD > 2000V per MIL-STD-883, Method 3015;
:> 200V using machine model (C = 200p'F, R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of-40°C to +85°C
- Vee = 5V ±10%
- Speed grades same as FCT-T Octals
• Features for FCT16374T/AT/CT:
- High drive outputs (-32mA IOH, 64mA IOL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162374T/AT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
The IDT54/74FCT16374T/AT/CT and IDT541
74FCT162374TIAT/CT 16-bit edge:"triggered D-type registers
are built using advanced CEMOS, dual metal CMOS technology. These high-speed, low-power registers are ideal for
use as buffer registers for data synchronization and storage.
The'Output Enable (xO'E) and clock (xCLK) controls are organized to operate each device as two 8-bit registers or one
16-bit register with common clock~Flow-through organization
of signal pins facilitates ease of layout. All inputs are designed
with hysteresis for improved noise margin. :
The IDT54/74FCT16374T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
The IDT54174FCT162374T/AT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54174FCT162374T/AT/CT are plug-in replacements
for the IDT54/74FCT16374T/AT/CT and 54/74ABT16374 for
on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
10E - - - - - - - < i
20E
1CLK
------<1
2CLK
lDl - - - - 4 - - - 1
201
----+-~
D
201
_---O"J~C
'~-------~-------~'
'~--------~r------~'
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2542 drw01
2542 drw01
CEMOS is a trademar\( of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C01992 Integrated Device Technology. Inc.
5.5
MAY 1992
DSC-4230J3
1
IDT54174FCT16374T/AT/CT, 162374T/AT/CT
FAST CMOS 16-BIT REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1CLK
10E
1
48
1CLK
47
101
101
2
47
101
10E
101
2
102
3
46
102
102
3
46
102
GNO
4
45
GNO
GNO
4
45
GNO
103
5
44
103
103
5
44
103
104
6
43
104
104
6
43
104
Vee
7
42
Vee
Vee
7
42
Vee
105
8
41
105
105
8
41
105
106
9
40
106
106
9
40
106
GNO
10
39
GNO
GNO
10
39
GNO
107
11
38
107
107
11
38
107
108
12 8048-1
37
108
108
12
37
108
201
13
36
201
201
13
36
201
202
14
35
202
202
14
35
202
GNO
15
34
GNO
GNO
15
34
GNO
203
16
33
203
203
16
33
203
204
17
32
204
204
17
32
204
Vee
18
31
Vee
Vee
18
31
Vee
205
19
30
205
205
19
30
205
206
20
29
206
206
20
29
206
GNO
21
28
GNO
GNO
21
28
GNO
22
27
207
E48·1
207
22
27
207
207
208
23
26
208
208
23
26
208
20E
24
25
2CLK
20E
24
25
2CLK
2542 drw 03
2542 drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
5.5
2
II
IDT54n4FCT16374T/AT/CT, 162374T/AT/CT
FAST CMOS 16-81T REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xDx
Inputs
Description
xCLK
xCLK
xOE
xOx
X
L
H
Z
X
H
H
Z
Load
L
L
L
Register
H
i
i
i
i
L
H
H
Z
Hi-Z
Clock Inputs
xOx
3-State Outputs.
xOE
3-State Output Enable Input (Active LOW)
2542 tbl 01
Outputs
xDx
Function
Data Inputs
L
H
H
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z m High Impedance
. i = LOW-to-HIGH Transition
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Ratinll
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
2542tb102
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Symbol
CIN
CoUT
TA
Operating
Temperature
-40 to +85
.:..55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
1.0
1.0
W
-60 to +120
-60 to +120
rnA
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions
Typ.
Max.
Unit
VIN = OV
4.5
6.0
pF
5.5
8.0
pF
VOUT=
ov
NOTE:
1. This parameter is measured at characterization but not tested.
2542 Ink 04
NOTES:
2542 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 110 terminals.
3. Output and 110 terminals for FCT162XXXT. .
5.5
3
IDT54n4FCT16374T/AT/CT, 162374T/AT/CT
FAST CMOS 16-81T REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
CommerCla:
. I TA=-40°C to + 85°C V cc= 5 OV ± 10 oYc0,• MT
Iitary: TA=-"55 °C to+ 125°C , vcc= 5 OV '±10%
Min.
Typ.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee = Max.
-
-
Symbol
Test Condltlons(1)
Parameter
VI = Vee
-
Input HIGH Current (I/O pins)
III
Input LOW Current (Input pins)
VI=GND.
"'-
Max.
Unit
-
V
0.8
V
±5
~
-
±15
±5
lOll
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18rnA
-
los
Short Circuit Current
Vee - Max., Vo .. GND(3)
-80
Vee = Max., Vo =.2.5V(3)
-50
-
. -180
mA
-
100
-
mV
-
0.05
1.5
mA
Input LOW Current (I/O pins)
10lH
High Impedance Output Current
10
Output Drive Current
VH
Input Hysteresis
leel
leeH
leel
Quiescent Power Supply Current
Vee= Max.
Vo=.2.7V
Vo= 0.5V
Vee
=Max., VIN =GND or Vee
-
±15
-0.7
±10
. ±10
-140
-200
:
~
-1.2
V
mA '
.,
25421nk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16374T·
Symbol
VOH
Min.
Typ.(2)
Vee= Min ..
10H=-3mA
2.5
3.5
-
VIN = VIH or Vil
10H = -12mA MIL.
10H = -15mA COM'L.
IOH = -24mA MIL. .
IOH = -32mA COMU 4}
2.4
3.5
-
2.0
3.0
-
V
-
0.2
0.55
V
-
-
±100'
Test 'Condltlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage
Vee= Min.
IOl= 48mA MIL.
VIN = VIH or Vil
IOl= 64mA COM'L.
Vee = OV, VIN or Vo S 4.5V
Unit:
Max.
V
'.
V
~
25421nk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162374T
SY1l1 boi
10Dl
Min.
Typ.<2}
Vee = 5V, VIN= VIHorVll, VOUT= 1.5V(3)
60
115
Max.
150
Unit
Output LOW CUrrent
IODH
Output HIGH CUrrent
Vee = 5V, VIN= VIHor Vil. VOUT= 1.5V(3}
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or Vil
IOH = -16mA MIL.
IOH = -24mA COM'L.
2.4
3.3
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or Vil
IOl = 16mA MIL.
10l = 24mA COM'L.
-
0.3
Parameter
Test Condltlons(1}
0.55
V
V
2542 Ink 07
NOTES:
1.
2.
3.
4.
-
mA
For conditions shown as Max. or Min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V. +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.5
4
II
IDT54!74FCT16374T/AT/CT, 162374T/AT/CT
FAST CMOS 16-BIT REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Typ,(2)
Max.
Unit
-
0.5
1.5
rnA
VIN = Vce
VIN = GND
-
60
100
Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
x'OE = GND
fi =5MHz
50% Duty Cycle
One Bit Toggling
VIN = Vee
VIN = GND
-
0.7
2.5
VIN = 3.4V
VIN = GND
-
1.2
4.0
Vec = Max.
Outputs Open
fep = 10MHz
50% Duty Cycle
xOE=GND
Sixteen Bits Toggling
fi =2.SMHz
50% Duty Cycle
VIN = Vee
VIN =GND
-
3.1
6.5(5)
VIN = 3.4V
VIN = GND
-
7.6
20(5)
Test Conditlons(1)
Parameter
~Iee
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
ICCD
Dynamic PoWer Supply
Current(4)
Vee = Max.
Outputs Open
x'OE= GND
One Input Toggling
SO% Duty Cycle
Total Power Supply Current(6)
Ie
Min.
rnA
2542tbl08
NOTES:
1.
2.
3.
4.
5.
6.
IlN
MHz
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ie = laulEscENT + IINPUTS + IDYNAMIC
Ie = Icc + Alcc DHNT + ICCD (fcpNcp/2 + fiN i)
lec = Quiescent Current (ICCL, ICCH and Iccz)
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
lecD:" Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
5.5
5
IDT54174FCT16374T/AT/CT, 162374T/AT/CT
FAST CMOS 16-BIT REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16374T/162374T
Symbol
Parameter
FCT16374AT/16237 4A T
Mil.
Com'l.
FCT16374CT/162374CT
Mil.
Com'l.
Mil.
Com'l.
Condltlon(l) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
CL = 50pF
RL =500n
2.0
10.0
2.0
11.0
2.0
6.5
2.0
7.2
2.0
5.2
2.0
6.2
ns
Output Enable Time
1.5
12.5
1.5
14.0
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.2
ns
tPHZ
tPLZ
Output Disable Time
1.5
8.0
1.5
8.0
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.7
ns
tsu
Set-up Time HIGH
or LOW xDx to xCLK
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH
or LOW xDx to xCLK
xCLK Pulse Width
HIGH or LOW
Output Skew(3)
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
7.0
-
7.0
-
5.0
-
6.0
-
5.0
-
6.0
-
ns
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
tPLH
tPHL
tPZH
tPZL
Propagation Delay
xCLKto xOx
tw
tSK(O)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.5
ns
2542tbl09
6
G®
FAST CMOS
18-81T REGISTERED
TRANSCEIVER
IDT54/74FCT16500AT/CT
IDT54/74FCT162500AT/CT
Integrated Device Technology, Inc.
These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow
data flow in transparent, latched and clocked modes. Data
flow in each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA) and clock (CLKAB
and CD 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
-
-
25 mil Center SSOP and Cerpack Packages
Extended commercial range of -40°C to +85°C
Vee = 5V ±10%
• Features for FCT16500AT/CT:
-
High drive outputs (-32m A IOH, 64mA IOL)
Power off disable outputs permit "live insertion"
Typical VOLP (Output Ground Bounce) < 0.8V at
Vee = 5V, TA = 25°C
• Features for FCT162500AT/CT:
-
Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.5V at
Vee = 5V,TA = 25°C
DESCRIPTION:
The
IDT54/74FCT16500AT/CT
and
IDT541
74FCT162500AT/CT 18-bit registered transceivers are built
using advanced CEMOS, dual metal CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
OEAB
--~
CLKBA - - - < l
LEBA --~ ?------------------------------------------~
OEBA
CLKAB
--~
--~ ;;---+---+----------~--...
LEAB - - - - l :>---4-0--4---"
B1
A1
----~~--4---+-~------~
~,--------------------~----------------------'~
CEMOS is a trademar1< of Integrated Device Technology, Inc.
TO 17 OTH ER CHANN ELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
5.6
2548 dlW 01
MAY 1992
DSC-463012
1
IDT54174FCT16500AT/CT, 162500AT/CT
FAST CMOS 18·BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEA8
GND
OEA8
LEA8
2
55
CLKA8
A1
3
54
81
1
56
GND
LEA8
2
55
CLKA8
A1
3
54
81
GND
4
53
GND
GND
4
53
GND
A2
5
52
82
A2
5
52
82
A3
6
51
83
A3
6
51
83
Vee
7
50
Vee
Vee
7
50
Vee
A4
8
49
84
A4
8
49
84
A5
9
48
85
A5
9
48
85
A6
10
47
86
A6
10
47
86
GND
11
46
GND
GND
11
46
GND
A7
12
45
87
A7
12
45
87
Aa
13
44
8a
Aa
13
A9
14 5056-1 43
89
A9
14
A10
15
42
810
A10
A11
16
41
811
A11
44
813
43
89
15
42
810
16
41
811
E56-1
A12
17
40
812
A12
17
40
812
GND
18
39
GND
GND I
18
39
GND
A13
19
38
813
A13
19
38
813
A14
20
37
814
A14
20
37
814
A15
21
36
815
A15
21
36
815
Vee
22
35
Vee
Vee
22
35
Vee
A16
23
34
816
A16
23
34
816
A17
24
33
817
A17
24
33
817
GND
25
32
GND
GND
25
32
GND
A1B
26
31
81B
A1B
26
31
818
OE8A
27
30
CLK8A
OE8A
27
30
CLK8A
LE8A
28
29
GND
LE8A
28
29
GND
2548 drw 03
2548 drw 02
CERPACK
TOP VIEW
550P
TOP VIEW
5.6
2
II
I
IDT54n4FCT16500AT/CT, 162500AT/CT
FAST CMOS 18·BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1,4)
PIN DESCRIPTION
Pin Names
Description
Inputs.
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
Outputs
Ax
Bx
X
CI:KAB
X
X
Z
OEAB
LEAB
LEAB
A-to-B Latch Enable Input
L
LEBA
B-to-A Latch Enable Input
H
H
X
L
L
C1:JESA to Ax.
Mln.!2)
FCT16500CTI162500CT
Mil.
Mln.!2)
Com'l.
Mln.(2)
Mil.
Mln.!2)
Max.
. Unit
-
150
-
150
-
150
-
150
MHz
1.5
5.1
1.5
5.6
1.5
4.6
1.5
4.6
ns
1.5
5.6
1.5
6.0
1.5
5.3
.1.5
5.6
ns
1.5
5.6
1.5
6.0
1.5
5.3
1.5
5.4
ns
Output Enable Time
OEAB to Bx
1.5
6.0
1.5
6.4
1.5
5.6
1.5
6.0
ns
tPHZ
tPLZ
Output Disable Time
DEBAto Ax. OEAB to Bx
1.5
5.6
1.5
6.0
1.5
5.2
'1.5
5.6
ns
tsu
Set-up Time HIGH or LOW
Ax to CD 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
25 mil Center SSOP and Cerpack Packages
Extended commercial range of -40°C to +85°C
Vee = 5V ±10%
• Features for FCT16501AT/CT:
-
High drive outputs (-32m A IOH, 64mA loL)
Power off disable outputs permit "live insertion"
Typical VOLP (Output Ground Bounce) < 0.8V at
Vee = 5V, TA = 25°C
• Features for FCT162501AT/CT:
-
IDT54/74FCT16501 AT/CT
IDT54/74FCT162501AT/CT
Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.5V at
Vee = 5V,TA = 25°C
DESCRIPTION:
The
IDT54/74FCT16501AT/CT
and
IDT541
74FCT162501 AT/CT 18-bit registered transceivers are built
using advanced CEMOS, dual metal CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
Bl
~..--------------------
~~
CEMOS is a trademarK of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1992 Integrated Device Technclogy, Inc.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
5.7
~
2547 drwOl
MAY 1992
DSC·4629J2
1
IDT54n4FCT16501AT/CT,162501AT/CT
FAST CMOS 18-81T REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEA8
GND
OEA8
1
56
GND
LEA8
2
55
CLKA8
Al
3
54
81
GND
4
53
GND
LEA8
2
55
CLKA8
Al
3
54
81
GND
4
53
GND
A2
5
52
82
A2
5
52
82
A3
6
51
83
A3
6
51
83
Vee
7
50
Vee
Vee
7
50
Vee
A4
8
49
84
A4
8
49
84
As
9
48
85
A5
9
48
85
A6
10
47
86
A6
10
47
86
GND
11
46
GND
GND
11
46
A7
12
45
87
A7
12
45
As
13
44
88
A8
13
A9
14 8056-1 43
89
A9
14
Ala
15
42
810
Ala
15
42
810
All
16
41
811
All
16
41
811
A12
17
40
812
A12
17
40
812
GND
18
39
GND
GND
18
39
GND
A13
19
38
813
A13
19
38
813
A14
20
37
814
A14
20
37
A15
21
36
815
A15
21
36
Vee
22
35
Vee
Vee
22
35
Vee.
A16
23
34
816
A16
23
34
816
E56-1
GND
]
87
44
88
43
89
814
_I
815 .
A17
24
33
817
A17
24
33
817
GND
25
32
GND
GND
25
32
GND
A18
26
31
818
A18
26
31
81B
OE8A
27
30
CLK8A
oa3A
27
30
CLK8A
LE8A
28
29
GND
LE8A
28
29
GND
2547 drw 03
2547drw 02
CERPACK
SSOP
TOP VIEW
TOP VIEW
5.7
2
II
IDT54174FCT16501AT/CT,162501AT/CT
FAST CMOS 18·BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE(1,4)
Description
Pin Names
OEAB
A-to-B OutPjJt Enable Input
"C5EBA
B-to-A Output Enable Input (Active LOW)
LEAB
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
A-to-B Latch Enable Input
L
X
X
X
Z
LEBA
B-to-A Latch Enable Input
H
H
X
L
L
CLKAB
A-to-B Clock Input
H
H
X
H
H
t
t
L
L
H
CLKBA
B-to-A Clock Input
H
L
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
H
L
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs
2547tbl01
H
L
L
X
H
B(2)
H
L
H
X
B(3)
NOTES:
2547tbl02
1. A-to-B data flow isshown. B-to-Adata ftowis similar but uses OEBA, LEBA,
and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
t = LOW-to-HIGH Transition
CAPACITANCE (TA=+25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
1.0
1.0
W
-60 to +120
-60 to +120
rnA
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
4.5
6.0
pF
ClIO
I/O
Capacitance
VOUT= OV
5.5
8.0
pF
Symbol
NOTE:
1. This parameter is measured at characterization but not tested.
2547 Ink 04
NOTES:
2547 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
5.7
3
IDT54n4FCT16501AT/CT,162501AT/CT
FAST CMOS 18-81T REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Com mercia
. I: T A= - 40°C to + 85°C V cc= 5 OV +
- 10°;;0; MTIitary: TA=Symbol
0+
cc= 50V
Test Conditlons(1)
VIH
Parameter
input HiGH Level
Guaranteed Logic HIGH Level
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vcc= Max.
Min.
2.0
10lH
High Impedance Output Current
lOll
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Va = GND(3)
-80
Vee = Max., Va = 2.5V(3)
-50
VI = Vee
Input HIGH Current (1/0 pins)
III
Input LOW Current (Input pins)
VI = GND
Input LOW Current (1/0 pins)
10
Output Drive Current
VH
Input Hysteresis
leel
leeH
leel
Quiescent Power Supply Current
Vee= Max.
Vo= 2.7V
Vo=0.5V
Vee = Max., VIN = GND or Vee
-
Yc
± 10°0
Typ.(2)
Max.
Unit
V
-
-
-
0.8
V
-
±5 .
~
±15
-
±5
-
±15
±10
~
±10
-0.7
-1.2
V
-140
-200
rnA
-
-180
rnA
100
-
mV
0.05
1.5
rnA
2547 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16501T
Symbol
VOH
Min.
Typ.(2)
Vee = Min.
10H=-3mA
2.5
3.5
VIN = VIH or Vil
IOH=-12mA MIL.
IOH=-15mA COM'L.
2.4
10H = -24mA MIL.
10H = -32mA COM'U4)
Test Conditlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
10FF
InpuVOutput Power Off Leakage
10l= 48mA MIL.
Vee= Min.
10l= 64mA COM'L.
VIN = VIH or Vil
Vee = OV, VIN or Va ~ 4.5V
Max.
Unit
V
3.5
-
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
V
V
~
2547 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162501T
Max.
Output LOW Current
Vee = 5V, VIN = VIH or Vll, VOUT= 1.5V(3)
Min.
60
TvpJ2)
iOOl
115
150
rnA
100H
Output HIGH Current
Vee = 5V, VIN = VIH or Vll, VOUT= 1.5V(3)
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or Vil
10H = -16mA MIL.
10H = -24mA COM'L.
2.4
3.3
Val
Output LOW Voltage
Vee = Min.
VIN = VIH or Vil
10l= 16mA MIL.
10l = 24mA COM'L.
-
0.3
Symbol
Parameter
Test Conditlons(1)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.7
0.55
Unit
V
V
2547 Ink 07
4
IDT54n4FCT16501AT/CT,162501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
dlee
IceD
Parameter
' Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4),
.Ic
Total Power Supply Current(6)
Test Condltlons(1)
Min.
Typ.(2)
Vee= Max.
VIN .. 3.4V(3)
-
0.5
Max.
1.5
Unit
rnA
Vee", Max., Outputs Open
VIN = Vee
OEAB = O'EBA = Vee or GND VIN= GND
One Input Toggling
50% Duty Cycle
-
75
120
~
MHz
Vee = Max., Outputs Open
fep = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA =Vee
LEAB = GND
One Bit Toggling
fi ';;'5MHz
50% Duty 'Cycle
VIN = Vee
VIN = GND
-
0.8
2.7
rnA
VIN = 3.4V
VIN =GND
-
1.3
4.2
Vee = Max., Outputs Open
fep = 10MHz (CLKAB)
50% Duty Cycle
OEAB '" O'EBA =Vee
LEAB .. GND
Eighteen Bits Toggling
fi=2.5MHz
50% Duty Cycle
VIN = Vee
VIN = GND
-
3.8
7.5(5)
VIN = 3.4V
VIN =GND
-
8.6
21.8(5)
2547tbl08
NOTES:
1.
2.
3.
,4.
5.
6.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc .. 5.0V, +25°C ambient.
Per TTL driven Input (VIN .. 3.4V); all other Inputs at Vcc or GND.
This parameter is not directly testable, but Is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. ,These limits are guaranteed but not tested.
Ic .. IQUIESCENT + IINPUTS + IDYNAMIC
Ic - Icc + .ilcc DHNT + ICCD (fcpNcp/2 + fiNi) ,
Icc .. Quiescent Current (ICCl, ICCH and Iccz)
.ilcc .. Power Supply Current for a TTL High Input (VIN .. 3.4V)
DH .. Duty Cycle for TTL Inputs High
NT- Number of TTL Inputs at DH
ICCD .. Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp - Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp .. Number of Clock Inputs at fcp
fi .. Input Frequency
Ni .. Number of Inputs at fi
5.7
5
IDT54n4FCT16501AT/CT, 162501AT/CT
FAST CMOS 18-81T REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16501AT/162501AT
Com'l.
Conditlon(1 )
Symbol
Parameter
fMAX
CLKAB or CLKBA frequency(3)
tPLH
tPHL
Propagation Delay
Ax to Bx or Bx to Ax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
'O'EBA to Ax. OEAB to Bx
tPHZ
tPLZ
Min. (2 )
FCT16501CT/162501CT
Mil.
Min.(2 )
Com'l.
Mil.
Max.
Unit
-
150
-
150
-
150
MHz
1.5
5.1
1.5
5.6
1.5
4.6
1.5
4.6
ns
Propagation Delay
LEBA to Ax. LEAB to Bx
Propagation Delay
CLKBA to Ax CLKAB to Bx
1.5
5.6
1.5
6.0
1.5
5.3
1.5
5.6
ns
1.5
5.6
1.5
6.0
1.5
5.3
1.5
5.4
ns
Output Enable Time
1.5
6.0
1.5
6.4
1.5
5.6
1.5
6.0
ns
Output Disable Time
'O'E'9Ato Ax, OEAB to Bx
1.5
5.6
1.5
6.0
1.5
5.2
1.5
5.6
ns
tsu
Set-up Time HIGH or LOW
Ax to CLKAB Bx to CLKBA
3.0
-
3.0
-
3.0
-
3.0
-
ns
tH
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
a
-
a
-
a
-
a
-
ns
Clock
LOW
3.0
-
3.0
-
3.0
-
3.0
-
ns
Ax to LEAB,
Clock
HIGH
Bxto LEBA
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
-
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
ns
tw
LEAB or LEBA Pulse Width
HIGH(3)
3.0
-
3.0
-
3.0
-
3.0
-
ns
tw
CLKAB or CLKBA Pulse Width
HIGH or LOW(3)
3.0
-
3.0
-
3.0
-
3.0
-
ns
Output Skew(4)
-
0.5
-
0.5
-
0.5
-
0.5
tsu
tH
tSK(O)
Set-up Time
HIGH or LOW
Max.
Min.(2 )
150
CL = 50pF
RL = 500n
Max.
Min.(2)
-
Max.
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.7
ns
2547tbl09
6
11
~~
."-
Integrated Device Technology, Inc.
FAST· CMOS
16·81T LATCHED
TRANSCEIVER
IDT54/74FCT16543T/AT/CT/DT
IDT54/74FCT162543T/AT/CT/DT
These high-speed, low-power devices are organized as
FEATURES:
• Common features:'
two independent 8-bit D-type latched transceivers with separate input and output control for each set to permit indepen_ 0.5 MICRON CEMOS~ Technology
_ High-speed, low-power CEMOS replacement for
dent control of data flow in either direction. For example, the
ABT functions'
A-to-B Enable (xCEAB) must be LOW in order to enter data
from Aport or to output data from the B port. xLEAB controls
_ .. Typical tSK(O) (Output Skew) < 250ps
the latch function. When xLEAB is LOW, the latches are
_ ESD> 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C .;. 200pF, R = 0)
transparent; a subsequent LOW-to-HIGH transition of xLEAB
signal puts the A latches in the storage mode. xOEAB
_ 25 mil Center SSOP and Cerpack Packages
_. Extended commercial range of -40°C to +85°C
performs output enable function on the B port. Data flow from
_ Vee = 5V ±10%
B port to A port is similar but requires using xCEBA, xLEBA,
· _ Speed grades same as FCT-T Octals
and xOEBA inputs. Flow-through organization of signal pins
• Features for FCT16543T/AT/CT/DT:
facilitates ease of layout. All inputsare designed with hyster- - High drive outputs (-32mA IOH, 64mA loL)
esis for improved noise margin.
.
The IDT54/74FCT16543T/AT/CT/DT are ideally suited for
, - Power off disable outputs permit "live insertion"
- Typical VOlP (Output Ground Bounce) < 1.0V at
,driving high capacitance loads and low impedance backplanes.
Vee = 5V, TA = 25°C
The output buffers are designed with Power-Off Disable
,. Felitures for FCT162543T/AT/CT/DT:
capability to allow "live insertion" of boards when used as
- Balanced Output Drivers: ±24mA (commercial),
backplane drivers.
.
±16mA (military)
The IDT54/74FCT162543T/AT/CT/DT have balanced out_ Reduced system switching n o i s e ' put drive with current limiting resistors. This offers low grourid
' bounce, minimal undershoot, and controlled output fall times_ Typical VOlP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
reduCing the need for external series terminating resistors.
DESCRIPTION:
The IDT54174FCT162543T/AT/CT/DT are plug-in replace-'
The IDT54r74FCT16543T/ATICT/DT and IDT541 ments for the IDT54/7.4FCT16543T/AT/CT/DT and 54/
74ABT16543 for on-board bus interface applications.
74FCT162543T/AT/CT/DT 16-bit latched transceivers are built.
using advanced CEMOS, dual metal CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
10EBA - - - < l
20EBA
lCEBA
2CEBA
lLEBA
---<1
2LEBA
10EAB
---Q
20EAB
2CEAB
lCEAB
lLEAB
---a
2lEAB
C
2Al
lAl
o
lBl
281
C
o
~~------~\rr------~I
~~----------\r-------~I
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2618 drw 01
2618 drw02
CEM05 is a trademark 01 Integrated Device Technology. Inc,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101992 Integrated Device Technology. Inc,
5.8
MAY 1992
05C-4239/1
1
IDT54174FCT16543T/AT/CTIDT,162543T/AT/CT/DT
FAST CMOS 16-81T LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
lOEAEf
lOEE3A
10EAB
1
56
10EBA
lLEAB
2
55
lLEBA
lLEAB
2
55
lLE8A
lCEAB
3
54
lCEBA
lCEAB
3
54
lCEBA
GND
4
53
GND
GND
4
53
GND
lAl
5
52
181
lAl
5
52
·181
lA2
6
51
182
lA2
6
51
182
Vee
7
50
Vee
Vee
7
50
Vee,
lA3
8
49
lB3
lA3
8
49
183
lA4
9
48
184
lA4
9
48
184
lAs
10
47
lBs
lAs
10
47
18s
GND
11
46
GND
GND
11
lA6
12
45
lB6
lA6
12
lA7
13
44
187
lA7
13
lAa
14 8056-1 43
lBa
lAa
14
GND
46
.186
45
'.,
"
'
,~
.
'
E56-1
44
18T
43
18a
42
281
2Al
15
42
281
2Al
15
2A2
16
41
282
2A2
16
41
282
17
40
283
."
~
2A3
17
40
283
2A3
GND
18
39
GND
GND
18
39
GND
2A4
19
38
284
2A4
19
38
284·
2As
20
37
28s
2As
20
37:
28s
2A6
21
36
286
2A6
21
36
286
Vee
22
35
Vee
Vee
2A7
23
34
287
2A7
2Aa
24
33
28a
GND
25
32
GND
2CEAB
26
31
2LEA8
27
30
,.,
Vee'
22
35
23
34
2Aa
24
33
28a
GND
25
32
GND:
2CEBA
2CEAB
26
31
2CE3A
2LEBA
2LEAB
27
30
2LEBA
20EAB
28
29
20EBA
..
.,
287
"
2Dru
28
29
20EBA
2618 drw04
2618 drw 03
CERPACK
SSOP
TOP VIEW
TOP VIEW
5.8
2
II
IDT54174FCT16543T/AT/CT/DT,162543T/AT/CT/DT
FAST CMOS 16-81T LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1, 2)
PIN DESCRIPTION
For A-to-8 (Symmetric with 8-to-A)
Description
Pin Names
xIT'EA'B
A-to-S Output Enable Input (Active LOW)
xOESA
S-to-A Output Enable Input (Active LOW)
xCEA'S
A-to-S Enable Input (Active LOW)
A-to-S Latch Enable Input (Active LOW)
xAx
A-to-S Data Inputs or S-to-A 3-State Outputs
S-to-A Enable Input (Active LOW)
S-to-A Latch Enable Input (Active LOW)
S-to-A Data Inputs or A-to-S 3-State Outputs
Output
Buffers
xC'EAB x1:EAB" xOEAB
xAx to xBx
xBx
X
X
Storing
HighZ
H
xC'EBA
x[EAg
xrEBA
xBx
Latch
Status
Inputs
X
H
X
Storing
X
X
X
H
X
HighZ
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous· A Inputs
NOTES:
2618tbl02
1.· Before x[EA8 LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
xCEI37\, x D:E3A and xOEBA.
2618 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Rating
Symbol
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
Operating
TA
Temperature
Commercial
Military
-0.5 to +7.0
-0.5 to +7.0
Unit
V
-0.5 to Vee
-0.5 to Vee
V
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Sias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
Symbol
CIN
a/a
Parameter(1)
Input
Capacitance
I/O
Capacitance
Conditions
Typ.
4.5
Max.
6.0
Unit
VIN = OV
VOUT= OV
5.5
8.0
pF
NOTE:
1. This parameter is measured at characterization but not tested.
1.0
1.0
W
-60 to +120
-60 to +120
mA
pF
2618 Ink 04
2618 Ink 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other Conditions above those ind icated in the operational sections of this speCification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 110 terminals for FCT162XXXT.
5.8
3
IDT54174FCT16543T/AT/CT/DT,162543T/AT/CT/DT
FAST CMOS 16·81T LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
C ommercla:
. I TA= -4 0 0 C to +8 50 C Vcc= 5.0 V ±10%; MT
Iitary:
Symbol
TA = -55 0 C to +125 0 CV cc = 5.0V ± 10%
Test Conditlons(1)
Parameter
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee = Max.
IlL
Input LOW Current (Input pins)
VI = Vee
Input HIGH Current (I/O pins)
Typ.(2)
Max.
Unit
-
-
V
0.8
V
-
±5
J.IA
-
-
±15
-
±5
-
±15
-0.7
-1.2
-140
-200
rnA'
Min.
2.0
-
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
rnA
-
100
-
mV
-
0.05
1.5
rnA
VI = GND
Input LOW Current (I/O pins)
10lH
High Impedance Output Current
lOlL
(3·State Output pins)
10
Output Drive Current
VH
Input Hysteresis
leeL
leeH
leel
Quiescent Power Supply Current
Vee = Max.
Vo= 2.7V
Vo= 0.5V
Vee = Max., VIN = GND or Vee
-
±10
-
±10
J.IA
V
2618 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16543T
~~mbol
VOH
Test Conditlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
10FF
Input/Output Power Off Leakage
Min.
Typ.(2)
Max.
Unit
Vee = Min.
10H=-3mA
2.5
3.5 ,
-
V
VIN= VIH or VIL
10H,= -12mA MIL.
10H = -15mA COM'L.
2.4
3.5
-
V
10H = -24mA MIL.
10H = -32mA COM'U 4)
2.0
3.0
-
:V
-
0.2
0.55
-
-
±100
Vee= Min.
10L= 48mA MIL.
VIN = VIH or VIL
10L= 64mA COM'L.
Vee = OV, VIN or Vo ~ 4.5V
V
J.IA
2618 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162543T
Min.
Typ.(2)
Max.
Unit
10DL
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
60
115
150
rnA
10DH
Output HIGH Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5v(3)
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
10H = -16mA MIL.
10H = -24mA COM'L.
2.4
3.3
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
10L= 16mAMIL.
10L= 24mA COM'L.
-
0.3
Symbol
Parameter
Test Conditions(1)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Not more than one output shoUld be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.8
0.55
V
V
2618 Ink 07
4
II
IDT54n4FCT16543T/AT/CT/DT,162543T/AT/CTIDT
FAST CMOS 16-BIT LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Typ.(2}
Max.
Unit
-
0.5
1.5
rnA
VIN = Vee
VIN = GND
-
60
100
Vee = Max., Outputs Open
fi = 10MHz
50% Duty Cycle
xCEAB, xcru and
x~=GND
xCE"9A= Vee
One Bit Toggling
VIN = Vee
VIN = GND
-
0.7
2.5
VIN = 3.4V
VIN = GND
-
0.9
3.3
Vee = Max., Outputs Open
fi= 2.5MHz
50% Duty Cycle
xCEAB", xCEAe and
xO"EA"S= GND
xC"ESA=Vee
Sixteen Bits Toggling
VIN = Vee
VIN = GND
-
2.5
5.5(5)
VIN = 3.4V
VIN = GND
-
6.5
17.5(5)
Test Conditlons(1}
dice
Quiescent Power Supply
Current TIL Inputs HIGH
Vee= Max.
VIN = 3.4V(3)
IceD
Dynamic Power Supply Current(4)
Vee = Max., Outputs Open
xCEAe and xC5EAB = GND
xC"ESA=Vee
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
Min.
NOTES:
{ For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc .. 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter Is not directly testable, but Is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + I,NPUTS + IDYNAMIC
Ic .. Icc + Alcc DHNT + ICCD (fcpNcP/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
lilcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
h .. Input Frequency
Ni = Number of Inputs at fI
5.8
flAJ
MHz
rnA
26181bl08
5
IDT54174FCT16543T/AT/CT/DT,162543T/AT/CT/DT
FAST CMOS 16-81T LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16543T/162543T
Com'l.
Symbol
Parameter
FCT16543AT/162543AT
Com'l.
Mil.
Mil.
Conditlon(1)
Mln,!2)
Max.
Mln,!2)
Max.
Mln,!2)
Max.
Mln,!2)
Max.
Unit
CL = 50pF
RL = 500n
2.5
8.5
2.5
10.0
2.5
6.5
2.5
7.5
ns
tPLH
tPHL
Propagation Delay
Transparent Mode
xAx to xBx or xBx to xAx
tPLH
tPHL
tPZH
tPZL
Propagation Delay
xITBA to xAx, x[EA8 to xBx
2.5
12.5
2.5
14.0
2.5
8.0
2.5
9.0
ns
Output Enable Time
xOEBA or xOEAB to xAx or xBx
xCEBA or x'CEAB to xAx or xBx
2.0
12.0
2.0
14.0
2.0
9.0
2.0
10.0
ns
tpHZ
tPLZ
Output Disable Time
x"OE"BA or x'OEAS to xAx or xBx
xCEBA or x'CEAB to xAx or xBx
2.0
9.0
2.0
13.0
2.0
7.5
2.0
8.5
ns
tsu
Set-up Time HIGH or LOW
xAx or xBx to x[EA8 or xITBA
3.0
-
3.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH or LOW
xAx or xBx to x[EliJ3 or xLEBA
2.0
-
2.0
-
2.0
-
2.0
-
ns
tw
xLEBA or xLEAB Pulse Width
5.0
-
5.0
-
5.0
-
5.0
-
ns
-
0.5
-
0.5
-
0.5
-
0.5
LOW
tSK(O) Output Skew(3)
ns
2618 Ibl 09
FCT16543CT/162543CT
Com'l.
Svmbol
Parameter
FCT16543DT/162543DT
Com'l.
Mil.
Mil.
Conditlon(1)
Mln,!2)
Max.
Min,!2)
Max.
Mln,!2)
Max.
Mln,!2)
CL = 50pF
RL = 500n
1.5
5.3
1.5
6.1
2.5
4.4
-
-
ns
Max.
Unit
tPLH
tPHL
Propagation Delay
Transparent Mode
xAx to xBx or xBx to xAx
tPLH
tPHL
Propagation Delay
x'CESA to xAx, xLEAB to xBx
1.5
7.0
1.5
8.0
2.5
5.0
-
-
ns
tPZH
tPZL
Output Enable Time
xOESA or x0'EAI3 to xAx or xBx
x'CEBA or x'CEA"S to xAx or xBx
1.5
8.0
1.5
9.0
2.0
5.4
-
-
ns
tPHZ
tpLZ
Output Disable Time
xOE3A or xOEAB to xAx or xBx
xCEBA or x'CEAB to xAx or xBx
1.5
6.5
1.5
7.5
2.0
4.3
-
-
ns
tsu
Set-up Time, HIGH or LOW
xAx or xBx to xrE"BA or x[EAJ'3
2.0
-
2.0
-
1.5
-
-
-
ns
tH
Hold Time HIGH or LOW
xAx or xBx to x[E"9A or x[EAJ'3
2.0
-
2.0
-
1.5
-
-
-
ns
tw
x[E"9A or xrEA'B" Pulse Width
5.0
-
5.0
-
3.0(4)
-
-
-
ns
-
0.5
-
0.5
-
0.5
-
-
LOW
tSK(O) Output Skew(3)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5.8
ns
2618tbl10
6
II
..
(;)
Integrated Device Technology, Inc.
FAST CMOS 16-BIT BUS
TRANSCEIVER!
REGISTERS (3-STATE)
IDT54174FCT16646T/AT/CT
IDT54/74FCT162646TIAT/CT
FEATURES:
These high-speed, low-power devices are organized as
two independent 8-bit bus transceivers with 3-state D-type
registers. The control circuitry is organized for multiplexed
- 0.5 MICRON CEMOSTM Technology
transmission of data between A bus and B bus either directly
- High-speed, low-power CEMOS replacement for
or from the internal storage registers. Each 8-bit transceiverl
ABT functions
register features direction control (xDIR), over-riding Output
- Typical tSK(O) (Output Skew) < 2S0ps
Enable control (xOE) and Select lines (xSAB and xSBA) to
- FSD > 2000V per MIL-STD-883, Method 3015;
select either real-time data or stored data. Separate clock
> 200V using machine model (C = 200pF, R = 0)
inputs are provided for A and B port registers. Data on the A
- 25 mil Center SSOP and Cerpack Packages
or B data bus, or both, can be stored in the internal registers
- Extended commercial range of -40°C to +85°C
by the LOW-to-H IGH transitions at the appropriate clock pins.
Vee = 5V±10%
Flow-through organization of signal pins facilitates ease of
- Speed grades same as FCT-T Octals
layout. All inputs are designed with hysteresis for improved
• Features for FCT16646T/AT/CT:
noise margin.
- High drive outputs (-32mA IOH, 64mA loL)
The IDT54/74FCT16646T/AT/CT are ideally suited for
- Power off disable outputs permit "I,ive insertion"
driving high capacitance loads and low impedance backplanes.
- Typical VOLP (Output Ground Bounce) < 1.0V at
The output buffers are designed with Power-Off Disable
Vee = 5V, TA = 25°C
capability to allow "live insertion" of boards when used as
• Features for FCT162646T/AT/CT:
backplane drivers.
- Balanced Output Drivers: ±24mA (commercial),
The IDT54174FCT162646T/AT/CT have balanced output
±16mA (military)
drive with current limiting resistors. This offers low ground
- Reduced system switching noise
bounce, minimal undershoot, and controlled output fall times- Typical VOLP (Output Ground Bounce) < 0.6V at
reducing the need for external series terminating resistors.
Vee = SV,TA = 25°C
'
The IDT54174FCT162646T/AT/CT are plug-in replacements
DESCRIPTION:
. for the IDT54/74FCT16646T/AT/CT and 54/74ABT16646 for
The IDT54/74FCT16646T/AT/CT and IDT541 on-board bU's interface applications.
74FCT162646T/AT/CT 16-bit registered transceivers are built
using, advanced CEMOS, dual metal CMOS .technology.
,. Common features':
FUNCTIONAL BLOCK DIAGRAM
2<5E
2DIR
2CLKBA---f---------I ><>-------1-.
.1CLKBA---f---------1 :><>-----1-.
2SBA ---+-----1
lSBA ---+-------1
1CLKAB
2CLKAB
2SAB --1-+-----1 /--,--.., ...--.
lSAB --+-+--~
1B1
1A1
~--------~--------------~I
~,--------~~------------~I
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2540 a-w02
2540 drw 01
CEMOS is a trade marl< of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101992 Integrated Device Technology, Inc,
5.9
MAY 1992
DSC·423113
1
IDT54174FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
1DIR
1
56
10E
1CLKAB
2
55
1CLKBA
10E
1CLKAB
2
55
1CLKBA
1SAB
3
54
1SBA
1SAB
3
54
1SBA
GND
4
53
GND
GND
4
53
GND
1A1
5
52
1B1
1A1
5
52
1B1
1M
6
51
1B2
1A2
6
51
1B2
Vee
7
50
Vee
Vee
7
50
Vee
1A3
8
49
1B3
1A3
8
49
1B3
1A4
9
48
1B4
1A4
9
48
1B4
1A5
10
47
1B5
1A5
10
47
1B5
GND
11
46
GND
GND
11
46
GND
1As
12
45
1Bs
1As
12
45
1Bs
1M
13
44
1B7
1A7
13
44
1B7
1AB
14 S056-1 43
1BB
1AB
14
43
1BB
E56-1
2A1
15
42
2B1
2A1
15
42
2B1
2A2
16
41
2B2
2A2
16
41
2B2
2A3
17
40
2B3
2A3
17
40
2B3
GND
18
39
GND
GND
18
39
GND
2A4
19
38
2B4
2A4
19
38
2B4
2A5
20
37
2B5
2A5
20
37
2B5
2As
21
36
2B6
2A6
21
36
2B6
Vee
22
35
Vee
Vee
22
35
Vee
2A7
23
34
2B7
2A7
23
34
2B7
2AB
24
33
2BB
2AB
24
33
2BB
GND
GND
25
32
GND
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2DIR
28
29
20E
GND
25
32
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2DIR
28
29
20E
2540 dJW 03
CERPACK
TOP VIEW
SSOP
TOP VIEW
5.9
2540 dJW04
2
II
IDT54174FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA =
Description
Pin Names
Parameter(1)
+25°C,
f = 1.0MHz)
Conditions
Typ.
Data Register A Inputs
Data Register B Outputs
CIN
Input
Capacitance
VIN = OV
4.5
Max.
6.0
Unit
xAx
xBx
Data Register B Inputs
Data Reqister A Outputs
ala
I/O
Capacitance
VOUT= OV
5.5
8.0
pF
~ ~'-
Symbol
xSAB, xSBA
xDIR,x"OE
2540 tbl 02
NOTE:
xCLKAB, xCLKBA Clock Pulse Inputs
pF
1. This parameter is measured at characterization but not tested.
Output Data Source Select Inputs
Output Enable Inputs
2540 tbl 01
FUNCTION TABLE(2)
Data 110(1)
Inputs
Operation or Function
xOE
xDIR
xCLKAB
xCLKBA
xSAB
xSBA
xAx
xBx
H
H
X
X
H or L
H or L
X
X
Input
i
Isolation
Store A and B Data
L
L
L
L
L
H
Output
Input
H orL
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
X
X
X
X
X
X
X
Input
i
L
H
X
X
Output
H or L
X
X
Input
H
Real Time A Data to B Bus
Stored A Data to B Bus
NOTES:
X
.
2634 tbl 03
1. The data output functions may be enabled or disabled by various signals at the xOE" or xDIR inputs. Data
Inputfunctions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock Inputs.
2. H = HIGH Voltage Level
L - LOW Voltage Level
X = Don't Care
t= LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS(1)
: Commercial
Rating
Svmbol
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to Vee
with Respect to
GND
Operating
TA
:-40 to +85
Ternperature
-55 to +125
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output
Current
NOTES:
-55 to +125
Military
Unit
-0.5 to +7.0
V
-0.5 to Vee
V
-55 to +125
°C
-65 to +135 ~
°C
-65 to +150
°C
1.0
1.0
W
-60.to +120
-60 to +120
rnA
..
2540 tbl 04
1. Stresses greaterthan those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
5.9
3
IDT54174FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
rl I i i
B~,S
'II
l IIB
E
'..
,
rl rl
/'
B~S
I II I
BUJ---'----I.::1-----,:
:. ' , .B,B
fU,[
S'
IA ~
JA
I I I I
I III I
L-....J
I'L-....J
I I
I I
~:I~:
2540 drw 06
, 2540 drvl 05'
xDIR
L
xOE"
L
,xCLKAB
xCLKBA
~SAB
xSBA
xDIR
X
X
L
H
X
xOE
L
xCLKAB
X
xCLKBA
X.
xSAB
L
xSBA
X
REAL·TIME TRANSFER
BUSATOB
REAL·TIME TRANSFER
BUS BTOA
II
n
I
]1 B
.
I
B
2540 drw07
xDIR
xCLKAB
xCLKBA
l'
X
L
xOE
L
L
X
X
H
l'
l'
l'
H
xSAB
X
X
X
xSBA
xDIR (1)
xOE
xCLKAB
xCLKBA
xSAB
xSBA
X
X
L
L
X
H or L
X
H
H
L
H or ~
X
H
X
X
STORAGE FROM
A AND/OR B
TRANSFER STORED
DATA TO A AND/OR B
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
5.9
4
IDT54n4FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = -55°C to +125°C, Vcc = 5.0V +
- 10%
SY!l1bol
VIH
Parameter
Input HIGH Level
Test Condltlons(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee = Max.
VI = Vee
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
VI =GND
Min.
2.0
-
-
Input LOW Current (1/0 pins)
Typ.(2)
Max.
-
-
Unit
V
0.8
V
±5
~
-
±15
-
±5
-0.7
±15
-1.2
V
-140
-200
mA
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Vo .. GND(3)
-80
10
Output Drive Current
Vee = Max., Vo = 2.5V(3)
-50
-
-180
mA
VH
Input Hysteresis
-
100
-
mV
leeL
leeH
leel
Quiescent Power Supply Current
-
0.05
1.5
mA
Vee = Max.
Vo= 2.7V
Vo= 0.5V
Vee = Max., VIN = GND or Vee
±10
~
±10
2540 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16646T
~ymbol
VOH
Parameter
Output HIGH Voltage
Test Condltlons(1)
Vee= Min.
10H=-3mA
VIN = VIH or VIL
VOL
Output LOW Voltage
10FF
InpuVOutput Power Off Leakage
10H = -12mA MIL.
10H = -15mA COM'L.
10H = -24mA MIL.
10H = -32mA COM'U4)
10L= 48mA MIL.
Vee= Min.
10L = 64mA COM'L.
VIN = VIH or VIL
Vee = OV, VIN or Vo ~ 4.5V
Min.
2.5
Typ.(2)
2.4
3.5
-
2.0
3.0
-
-
0.2
0.55
-
-
±100
3.5
Max.
Unit
V
V
V
V
~
2540 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162646T
Symbol
10DL
Parameter
Output LOW Current
Test Condltlons(1)
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min.
60
Typ.(2)
115
Max.
150
Unit
mA
-60
-115
-150
mA
2.4
3.3
-
V
-
0.3
0.55
V
10DH
Output HIGH Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
Vee= Min.
VIN = VIH or VIL
10H = -16mA MIL.
10H =-24mA COM'L.
10L= 16mA MIL.
10L = 24mA COM'L.
2540lnk07
NOTES:
1.
2.
3.
4.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.9
5
IDT54174FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Test Condltlons(1)
Parameter
Max. , Unit
1.5
=Vee
=GND
-
75
120
VIN = Vee
VIN =GND
-
0.8
2.7
VIN = 3.4V
VIN =GND
-
1.3
4.2
Vee = Max.
VIN = Vee
Outputs Open
VIN = GND
fep = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE = GND
,VIN =3.4V
Sixteen Bits Toggling
VIN = GND
fi =2.5MHz
50% Duty Cycle
-
3.8
7.5(5}
-
8.3
21(5)
Vee = Max.
VIN .. 3.4V(3)
leeD
Dynamic Power Supply Current(4)
Vee = MaX.
Outputs Open
xDIR = xOE= GND
One Input Toggling
50% Duty Cycle
VIN
VIN
Vee = Max.
Outputs Open
fep = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE =GND
One Bit Toggling
fi =5MHz
50% Duty Cycle
Total Power Supply Current(6)
Typ,(2)
0.5
Quiescent Power Supply Current
TTL Inputs HIGH
Ie
Min.
-
~Iee
Ji.A!
MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + dlcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
dlcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at 1;
5.9
rnA
rnA
2540tb108
6
II
IDT54174FCT16646T/AT/CT, 162646T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16646T/162646T
Com'l.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
Bus to Bus
tPZH
tPZL
FCT16646AT/162646AT
Mil.
Com'l.
FCT16646CT/162646CT
Mil.
Com'l.
Mil.
Condltlon(1) Mln,(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln,(2) Max.
CL = 50pF
RL = 500n
Unit
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
5.4
1.5
6.0
ns
Output Enable Time
xDIR or xOE to Bus
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
1.5
7.8
1.5
8.9
ns
tPHZ
tPLZ
Output Disable Time
xDIR or xOE to Bus
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
6.3
1.5
7.7
ns
tPLH
tPHL
Propagation Delay
Clock to Bus
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
1.5
5.7
1.5
6.3
ns
tPLH
tPHL
Propagation Delay
xSBA or xSAB to Bus
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
1.5
6.2
1.5
7.0
ns
tsu
Set-up Time HIGH or
LOW Bus to Clock
4.0
-
4.5
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH or
LOW Bus to Clock
2.0
-
2.0
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
WI
Clock Pulse Width
HIGH or LOW
Output Skew(3)
6.0
-
6.0
-
5.0
-
5.0
-
5.0
-
5.0
-
ns
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
tSK(O)
ns
2540tbl09
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.9
7
t;)
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTER
IDT54/74FCT16652T/AT/CT
IDT54/74FCT162652T/AT/CT
Integrated Device Technology, Inc.
FEATURES:
• Common features:
- 0.5 MICRON CEMOSTM Technology
- High-speed, low-power CEMOS replacement for
ABT functions
- Typical tSK(O} (Output Skew) < 2S0ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
- Vee = 5V ±10%
- Speed grades same as FCT-T Octals
• Features for FCT16652T/AT/CT:
- High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162652T/AT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
DESCRIPTION:
The
IDT54/74FCT16652T/AT/CT and IDT541
74FCT162652T/AT/CT 16-bit registered transceivers are built
using advanced CEMOS, dual metal CMOS technology. These
high-speed, low-power devices are organized as two independant 8-bit bus transceivers with 3-state D-type registers.
For example, the xOEAB and xOEBA signals control the
transceiver functions.
xSAB and xSBA control pins are provided to select either
real time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real
time data. A LOW input level selects real-time data and a
HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins facilitates ease of layout. All inputs are designed
with hysteresis for improved noise margin.
The IDT54/74FCT16652T/AT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
The IDT54174FCT162652T/AT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54174FCT162652T/AT/CT are plug-in replacements
for the IDT54/7 4FCT16652T/AT/CT and 54/7 4ABT16652 for
on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
20EAB
10EAB
20EBA
2CLKBA----=:-I---------;"-.o------h
10EBA
lCLKBA--"':'-~-------I
lSBA -----I"-------l
2SBA - - - - - 1 - - - - - - i
lCLKAB
2CLKAB
2SAB --..J---l---{
lSAB--+-~---1
2Bl
lAl
~~--------------~--------------~I
~~--------------~--------------~I
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2549 drwOl
2549 drw 02
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
5.10
MAY 1992
DSC·463112
1
II
IDT54174FCT16652T1AT/CT, 162652T/AT/CT
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
10EA8
10E8A
10EA8
1
56
10E8A
1CLKA8
2
55
1CLK8A
1CLKA8
2
1CLK8A
1SA8
3
1S8A
1SA8
3
54
1S8A
GND
4
GND
GND
4
53
GND
1A1
5
181
1A1
5
52
181
, 1A2
6
182
1A2
6
51
182
Vee
7
Vee
Vee
7
50
Vee
1A3
8
183
1A3
8
49
183
1A4
9
184
1A4
9
48
184
1A5
10
185
1A5
10
47
185
.GND
11
GND
GND
11
46
GND
. 1A6
12
186
1A6
12
45
186
1M
13
187
1M
13
44
187
1Aa
14 S056-1
18a
1Aa
14
43
18a
2A1
15
281
2A1
15
42
281
E56-1
2A2
16
282
2A2
16
41
282
2A3
17
283
2A3
17
40
283
GND
18
GND
'GND
18
39
GND
2A4
19
284
2A4
19
38
284
2A5
20
285
2A5
20
37
285
2A6
21
286
2A6
21
36
286
Vee
22
Vee
Vee
22
35
Vee
2A7
23
287
2A7
23
34
287
2Aa
24
28a
2Aa
24
33
28a
GND
25
GND
GND
25
32
GND
2SA8
26
2S8A
2SA8
26
31
2S8A
2CLKA8
27
2CLK8A
2CLKA8
27
30
2CLK8A
20EA8
28
20E8A
20EA8
28
29
20E8A
2549 drw 04
2549 drw 03
CERPACK
SSOP
TOP VIEW
TOP VIEW
5.10
2
IDT54174FCT16652T/AT/CT, 162652T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Pin Names
xAx
Description
xBx
Data Register B Inputs
Data Rellister A OutQuts
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA
xOEAB, xOEBA
Parameter{l)
Symbol
Data Register A Inputs
Data Register B Outputs
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
4.5
6.0
pF
ClIO
1/0
Capacitance
VOUT= OV
5.5
8.0
pF
NOTE:
2549 Ink 02
1. This parameter is measured at characterization but not tested.
Output Data Source Select Inputs
Output Enable Inputs
2549 Ibl 01
FUNCTION TABLE(3)
Data 1/0(1)
Inputs
Operation or Function
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xAx
xBx
L
L
H
H
H or L
H or L
X
H
H
X
X
X
X
Input
i
X
X
X
X(2)
Input
i
i
i
L
L
X
H orL
i
X
X
X
X(2)
Unspecified(l)
L
Output
Input
Input
Hold A, Store B
Store B in both Registers
L
L
L
L
X
X
L
H
Output
Input
H or L
Real Time B Data to A Bus
Stored B Data to A Bus
H
H
H
H
X
X
X
X
X
L
H
X
X
Input
Output
H orL
Real Time A Data to B Bus
Stored A Data to B Bus
H
L
H or L
H orL
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H
H or L
i
i
i
X
Isolation
Store A and B Data
Unspecified(l) Store A, Hold B
Output
Store A in Both Registers
Input
Input
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEf:lA inputs.
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
3. H = HIGH Voltage Level
~: ~~~t 6~:ge Level
i
=
ABSOLUTE MAXIMUM RATINGS(1)
LOW-to-HIGH Transition
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vec
-0.5 to Vee
V
-40 to +85
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
NOTES:
1.0
1.0
W
-60 to +120
-60 to +120
rnA
2549 Ink 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.10
3
IDT54174FCT16652T/AT/CT, 162652T1AT/CT
. FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IIIII
BUS
I
I I I I
I I
I I
_--'-_--1.._--1
D
I I
2549 drw 06
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
X
X
L
xOEAB
H
xOEBA
H
, REAL-TIME TRANSFER
BUSB.TOA
xCLKAB
X
xCLKBA
xSAB
xSBA
X
L
X
REAL-TIME TRANSFER
BUSATO B
2549 drw 08
~?,
. ~OEAB xOEBA ,.xCLKAB
xCLKBA
X
·H
i
X
L,
X
X
L
H
i
i
i
,
. xSAB
X
X
X
xSBA
xOEAB
X
H
xOEBA xCLKAB
L
H or L
xCLKBA
H or L
xSAB
H
xSBA
H
X
X
TRANSFER STORED
DATA TO A AND/OR B
STORAGE FROM
AAND/OR B
5.10
4
IDT54n4FCT16652T/AT/CT, 162652T/AT/CT
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +BSoC, Vcc = S.OV ± 10%; Military: TA = -SsoC to +12SoC,Vcc = S.OV ± 10%
Symbol
Test Condltlons(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
VIL
Input LOW Level
Guaranteed Logic LOW Level
Vee = Max.
-
V
Input HIGH Current (Input pins)
-
0.8
IIH
±5
~
-
±15
-
-
±15
-
-
±10
VI = Vee
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
VI=GND
Input LOW Current (VO pins)
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
Vee = Max.
Vo= 2.7V
Vo = 0.5V
VIK
Clamp Diode Voltage
Vee = Min., liN = -:-18mA
los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo == 2.5V(3}
-50
10
Output Drive Current
VH
Input Hysteresis
IceL
leeH
leel
Quiescent Power Supply Current
-
Vee = Max., VIN = GND or V~e
,V
±5
~
±10
-0.7
-1.2
V
-140
-200
-
. -180
rnA
rnA
100
-
mV
0.05
1.5
rnA
2549 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16652T
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
Vee= Min.
10H=-3mA
VIN = VIH or VIL
IOH = -12mA
10H = -15mA
. 10H = -24mA
IOH'i:: -32mA
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
IOFF
InpuVOutput Power Off Leakage
Vee = OV, VIN or Vo ::; 4.5V
MIL.,
COM'L.
MIL.
COM'U4)
10L= 48mA MIL.
IOL= 64mA COM'L.
Min.
Typ.(2)
2.5
3.5
2.4
Max.
Unit
V
3.5
-
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
V
V
~
2549 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162652T
Symbol
10DL
Parameter
Output LOW Current
Min.
60
Typ.<2)
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3}
115
Max.
150
IOOH
Output HIGH Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3}
-60
-115
-150
VOH
Output HIGH Voltage
Vec=Min.
VIN = VIH or VIL
IOH=-16mAMIL.
IOH = -24mA COM'L.
2.4
3.3
VOL
Output LOW Voltage
Vec= Min.
VIN = VIH or VIL
10L= 16mAMIL.
IOL = 24mA COM'L.
-
0.3
Test Condltlons(1)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.10
0.55
Unit
rnA
rnA
V
V
2549 Ink 09
5
IDT54174FCT16652T/AT/CT, 162652T/AT/CT
FAST CMOS 16·BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Svmbol
.:\Iee
Parameter
Quiescent Power Supply Current
TIL Inputs HIGH
IceD
Dynamic Power Supply Current(4)
Ie
Total Power Supply Current(6)
Test Conditlons(1)
Min.
'fm,(2)
Vee = Max.
VIN = 3.4v(3)
-
0.5
Max.
1.5
Vee = Max.
VIN = Vee
Outputs Open
VIN = GND
xOEAB = x'CfESA=GND
One Input Toggling
50% Duty Cycle
-
75
120
Vee = Max.
Outputs Open
fep = 10MHz (xCLKBA)
50% Duty Cycle
xOEAB = xOESA=GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VIN = Vee
VIN = GND
-
0.8
2.7
VIN = 3.4V
VIN = GND
-
1.3
4.2
VIN = Vee
VIN = GND
-
3.8
7.5(5)
VIN = 3.4V
VIN = GND
-
8.3
21(5)
Vee = Max.
Outputs Open
fep = 10MHz (xCLKBA)
50% Duty Cycle
xOEAB = x'OESA=GND
Sixteen Bits Toggling
fi =2.5MHz
50% Duty Cycle
IlAl
MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic= laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
Alcc a Power Supply Current for a TIL High Input (VIN = 3.4V)
DH .. Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD a Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp .. Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fj = Input Frequency
Ni .. Number of Inputs at fi
5.10
Unit
mA
rnA
2549 Ibl 08
6
IDT54174FCT16652T/AT/CT, 162652T/AT/CT
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16652T/162652T
Com'l.
Symbol
Parameter
FCT16652AT/162652AT
Com'l.
Mil.
FCT16652CT/162652CT
Mil.
Com'l.
Mil.
Condition(1 ) MlnP) Max. MlnP) Max. MinP) Max. Min.<2) Max. Min.<2) Max. Min.<2) Max. Unit
=50pF
=500n
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
5.4
1.5
6.0
ns
Output Enable Time
xOEAB or x'O'E'S'A to Bus'
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
1.5
7.8
1.5
8.9
ns
tPHZ
tPLZ
Output Disable Time
xOEAB or x'OEBA to Bus
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
6.3
1.5
7.7
ns
tPLH
tPHL
Propagation Delay
Clock to Bus
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
1.5
5.7
1.5
6.3
ns
tPLH
tPHL
Propagation Delay xSBA or
xSAB to Bus
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
1.5
6.2
1.5
7.0
ns
tsu
Set-up Time HIGH or LOW
Bus to Clock
4.0
-
4.5
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH or LOW
Bus to Clock
2.0
-
2.0
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
6.0
-
6.0
-
5.0
-
5.0
-
5.0
-
5.0
-
ns
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
tPLH
tPHL
Propagation Delay
Bus to Bus
tPZH
tPZL
Clock Pulse Width
HIGH or LOW
tSK(O) Output Skew(3)
tw
CL
RL
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.10
ns
2549 tbl 09
7
t;5
FAST CMOS
16-81T REGISTERED
TRANSCEIVER
IDT54/74FCT16952AT/BT/CT/DT
IDT54/74FCT162952AT/BT/CT/DT
Integrated Device Technology, Inc.
FEATURES:
• Common features:
-
0.5 MICRON CEMOSTM Technology
High-speed, low-power CEMOS replacement for
ABT functions
- Typical tSK(O) (Output Skew) < 250ps
- ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
- Vee = 5V ±10%
- Speed grades same as FCT-T Octals
• Features for FCT16952AT/BT/CT/DT:
- High drive outputs (-32mA IOH, 64mA IOL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162952AT/BT/CT/DT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
DESCRIPTION:
The IDT54/74FCT16952AT/BT/CTIDT and IDT541
74FCT162952AT/BT/CT/DT 16-bit registered transceivers
are built using advanced CEMOS, dual metal CMOS technology. These high-speed, low-power devices are organized as
two independent 8-bit D-type registered transceivers with
separate input and output control for each set to permit
independent control of data flow in either direction. For
example, the A-to-B Enable (xCEAB) must be LOW in order
to enter data from the A port. xCLKAB controls the clocking
function. When xCLKAB toggles from LOW-to-HIGH, the data
present on the A port will be clocked into the register. xOEAB
performs the output enable function on the B port. Data flow
from B port to A port is similar but requires using xCEBA,
xCLKBA, and xOEBA inputs. The flow-through organization
of signal pins facilitates ease of layout. Full 16-bit operation
can be achieved by tying the control pins of the independent
transceivers together. All inputs are designed with hysteresis
for improved noise margin.
The IDT54174FCT16952AT/BT/CT/DT are ideally suited
for driving high capacitance loads and low impedance
backplanes. The output buffers are designed with Power-Off
Disable capability to allow "live insertion" of boards when used
as backplane drivers.
The IDT54174FCT162952AT/BT/CT/DT have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times-reducing the need for external series terminating
resistors. The IDT54174FCT162952AT/BT/CT/DT are plug-in
replacements for the IDT54174FCT16952AT/BT/CT/DT and
54/74ABT16952 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
2CEBA
1CLKBA
--~ >-----~
2CLKBA
20EAB
2CEAB
1CLKAB
--~ >--~
2CLKAB
20EBA
1A1
--.....-<
I-+--.J--I--I
181
~~-------,,~------~I
TO 7 OTHER CHANNELS
2A1
LJll---t--t--f--__-
~~-------,,~------~,
25t5dIW Ot
TO 7 OTHER CHANNELS
281
25t5dIW 02
CEM05 is a trademark 01 Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
et992 Integrated Device Technology. Inc.
5.11
MAY 1992
05C-463312
1
IDT54n4FCT16952AT/BT/CT/DT, 162952AT/BT/CT/DT
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
10EAB
10EBA
10EAB
1
56
10EBA
1CLKAB
2
55
1CLKBA
1CLKAB
2
55
1CLKBA
1CEAB
3
54
1CEBA
1CEAB
3
54
1CEBA
GND
4
53
GND
GND
4
53
GND
1A1
5
52
1B1
1A1
5
52
1B1
1A2
6
51
1B2
1A2
6
51
1B2
Vee
7
50
Vee
Vee
7
50
Vee
1A3
8
49
1B3
1A3
8
49
1B3
1A4
9
48
1B4
1A4
9
48
1B4
1A5
10
47
1B5
1As
10
47
1B5
GND
11
46
GND
GND
11
46
GND
1A6
12
45
1B6
1A6
12
45
1B6
1M
13
44
1B7
1M
13
44
1B7
1Aa
14 8056-1 43
1Ba
1Aa
14
43
1Ba
2A1
15
42
2B1
2A1
15
42
2B1
2A2
16
41
2B2
2A2
16
41
2B2
2A3
17
40
2B3
2A3
17
40
2B3
GND
18
39
GND
GND
18
39
GND
2A4
19
38
2B4
2A4
19
38
2B4
2As
20
37
2Bs
2As
20
37
2Bs
E56-1
2A6
21
36
2B6
2A6
21
36
2B6
Vee
22
35
Vee
Vee
22
35
Vee
2A7
23
34
2B7
2A7
23
34
2B7
2Aa
24
33
2Ba
2Aa
24
33
2Ba
GND
25
32
GND
GND
25
32
GND
2CEAB
26
31
2CEBA
2CEAB
26
31
2CEBA
2CLKAB
27
30
2CLKBA
2CLKAB
27
30
2CLKBA
20EAB
28
29
20EBA
20EAB
28
29
20EBA
2515 drw 04
2515 drw 03
CERPACK
SSOP
TOP VIEW
TOP VIEW
5.11
2
II
IDT54174FCT16952AT/BT/CT,/DT 162952AT/BT/CT/DT
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1,3)
PIN DESCRIPTION
Inputs
Description
Pin Names
Outputs
xOEAB
A-to-8 Output Enable Input (Active LOW)
xCEAB
xCLKAB
xOEAB'
xAx
xOEBA
B-to-A Output Enable Input (Active LOW)
H
X
L
xCEAB
A-to-8 Clock Enable Input (Active LOW)
X
L
L
X
X
B-to-A Clock Enable Input (Active LOW)
L
L
L
L
t
t
L
A-to-8 Clock Input
L
H
H
X
X
H
X
Z
, x'C'E37\
xCLKA8
xCLK8A
8-to-A Clock Input
xAx
A-to-8 Data Inputs or B-to-A 3-State Outputs
xBx
8-to-A Data Inputs or A-to-8 3-State Outputs
2515 tbl 01
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to .
GND
8(2)
NOTES:
2515tbl02
1. A-to-B data flow is shown: B-to-A data flow is similar but uses, xC'I:l3A,
xCLKBA, and xOEt3A'.
2. Level of B before the indicated steady-state input conditions were
established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
i =LOW-to-HIGH Transition
Z = High Impedance
CAPACITANCE (TA= +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
xBx
8(2)
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Symbol
CIN
ClIO
Parameter(1}
Conditions
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
4.5
6.0
pF
110
VOUT= OV
5.5
8.0
pF
Capacitance
NOTE:
2515 Ink 04
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
Pr
Power Dissipation
lOUT
DC Output
Current
1.0
1.0
W
-60 to +120
-60 to +120
rnA
NOTES:
2515 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 110 terminals.
3. Output and 110 terminals for FCT162XXXT.
5.11
3
IDT54174FCT16952AT/BT/CT/DT, 162952AT/BT/CT/DT
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Parameter
Input HIGH Level
Min.
Typ.(2)
Max.
VIH
Guaranteed Logic HIGH Level
2.0
-
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
-
0.8
V
IIH
Input HIGH Current (Input pins)
Vee = Max.
VI = Vee
-
-
±5
~
-
±15
VI = GND
-
-
±5
±15
Vo=2.7V
-
-
±10
-
±10
-0.7
-1.2
V
-140
-200
rnA
Symbol
Test Condltlons(1)
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
Input LOW Current (1/0 pins)
Unit
V
10ZH
High Impedance Output Current
10ZL
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
rnA
-
100
-
mV
-
0.05
1.5
rnA
10
Output Drive Current
VH
Input Hysteresis
ICCL
ICCH
Icez
Quiescent Power Supply Current
Vee= Max.
Vo= 0.5V
Vee = Max., VIN = GND or Vee
~
2515 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16952T
Symbol
VOH
Min.
Typ'(2)
Vee= Min.
10H=-3mA
2.5
3.5
VIN = VIH or VIL
IOH = -12mA MIL.
IOH = -15mA COM'L.
2.4
IOH = -24mA MIL.
IOH = -32mA COM'L.(4)
Test Condltlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage
Vee= Min.
IOL= 48mA MIL.
IOL = 64mA COM'L.
VIN = VIH or VIL
Vee = OV. VIN or Vo :s; 4.5V
Max.
Unit
V
3.5
-
2.0
3.0
-
V
-
0.2
0.55
-
-
±100
V
V
~
2515 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162952T
Max.
Unit
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min.
60
Typ.(2)
IOOL
115
150
rnA
IOOH
Output HIGH Current
Vce = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or VIL
IOH = -16mA MIL.
IOH = -24mA COM'L.
2.4
3.3
-
V
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
IOL= 16mA MIL.
IOL = 24mA COM'L.
-
0.3
0.55
V
Symbol
Parameter
Test Condltlons(1)
2613 Ink 07
NOTES:
1.
2.
3.
4.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.11
4
II
I
IDT54174FCT16952AT/BT/CT,/DT 162952AT/BT/CTIDT
FAST CMOS 16·BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
.1lce
leCD
Parameter
' Quiescent Power.Supply.:
CUrrent TIL Inputs HIGH
o.ymlrnic Power Supply Current(4)
Total Power Supply Current(6)
Ie
,,,
"
:
",
:
..
"
Test Condltlons(1)
Min.
Vee = Max;
VIN "" 3.4V(3)
Typ.(2)
-
0.5
Max.
1.S
75
120
Vee = Max., Outputs Open
x"OEAS or x"OESA =GND
One Input Toggling
SO% Duty Cycle
VIN = Vee
VIN = GND
-
Vee = Max., Outputs Open
fep = 10MHz (xCLKAB)
SO% Duty Cycle
xQE]iJJ .. xCEAEr.. GND
xOESA=Vee
One Bit Toggling
fi= 5MHz
SO% Duty Cycle
VIN = Vee
VIN = GND
-
O.B
2.7
VIN"; 3.4V
VIN = GND
-
1.3
4.2
Vee = Max., Outputs Open
fep= 10MHz (xCLKAB)
SO%' Duty Cycle
xQE]iJJ .. x~= GND
xOESA=Vee
Sixteen Bits Toggling
fi = SMHz
SO% Duty Cycle
VIN = Vee
VIN = GND
-
3.B
7.S(5)
VIN =3.4V
VIN = GND
-
B.3
21(5)
v.N
MHz
NOTES:
1: For conditions shown as Max. or Min" use' appropriate value specified under Electrical Characteristics for the applicable device type.
'2. Typical villuesare at Vee = S,OV, +25°C ambient.
3. Per TIL driven input (VIN';' 3.4V); all other inputs at Vee or GND.
4: This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values fo'r these conditions are examples'of the Icc formula: These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + liN PUTS + IDYNAMIC
','
,
Ic = Icc + Alec DHNT + lecD (fcpNcp/2+ fiNi)
Icc = Quiescent Current (ICCl, lecH and Iccz)
Alec = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH"
,
IceD = Dynamic Current Caused by an input Transition Pair (HLH or LHL)
fcp =' Clock Frequency for Register Devices (Zero for Non-Register Devices)
Nep = Number of Clock Inputs at fep
fi = Input Frequency
Ni = Number of Inputs at fi '
5.11
Unit
rnA
rnA
2515 tbl 08
5
IDT54n4FCT16952AT/BT/CT/DT, 162952AT/BT/CTIDT
FAST CMOS 16-BIT REGISTERED TRANSCBVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES,
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16952AT/162952AT
Com'l.
Symbol
Parameter
FCT16952BT/162952BT
Com'I.'
Mil.
Mil.
Condltlon!l)
Mln.l2)
Max.
,Jlln.l2)
Max.
Mln.l2)
Max.
MlnP)
Max.
Unit
CL =50pF
RL = 500n
2.0
10.0
2.0
11.0
2.0
7.5
2.0
8.0
ns
tPLH
tPHL
Propagation Delay
xCLKAB xCLKBA to xBx xAx
tPZH
tPZL
Output Enable Time
xTIEB7\, xOEAB'to xAx, xBx
1.5
10.5
1.5
13.0
1.5
8.0
1.5
8.5
ns
tPHZ
tpLZ
Output Disable Time
xTIEB7\, xOEAB'to xAx,xBx
1.5
10.0
1.5
10.0
1.5
7.5
1.5
8.0
ns
tsu
Set-up Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
2.5 '
-
2.5
-
2.5
-
2.5
-,
ns
tH
Hold Time HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
2.0
-
2.0
-
1.5
-
1.5
-
ns
tsu
Set-up Time, HIGH or LOW
xCEAl3; xCEBA to xCLKAB,
3.0
-
3.0
-
3.0
-
3.0
-
ns
2.0
-
2.0
-
2.0
-
2.0
-
ns
Pulse Width HIGH or LOW
xCLKAB or xCLKBA(3)
3.0
-
3.0
-
3.0
-
3.0
-
ns
Output Skew(4)
-
0.5
-
0.5
-
0.5
-
0.5
xCLKBA
tH
Hold Time HIGH or LOW
xCEAB, xCESA to xCLKAB,
xCLKBA
tw
tSK(O)
ns
2515tbl09
FCT16952CT/162952CT
Com'l.
Symbol
Parameter
Condition!l)
Mln.l2)
CL = 50pF
RL = 50 on
2.0
Max.
MlnP)
6.3
2.0
iii
FCT16952DT/162952DT
Mil.
Com'l.
Mil.
Max.
Mln.(2)
Max.
7.3
2.0
4.5
-
-
ns'
Mln.(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
xCLKAB xCLKBA to xBx xAx
tPZH
tPZL
Output Enable Time
xTIEB7\, xQEliJj to xAx, xBx
1.5
7.0
1.5
8.0
1.5
5.6
-
-
ns
tPHZ
tPLZ
Output Disable Time
x~, xOEAB'to xAx, xBx
1.5
6.5
1.5
7.5
1.5
4.3
-
-
ns
tsu
Set-up Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
2.5
-
2.5
-
1.5
-
-
-
ns
tH
Hold Time HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
1.5
-
1.5
-
1.0
-
-
-
ns
tsu
Set-up Time, HIGH or LOW
xC'EAi3, xcrsA to xCLKAB,
3.0
-
3.0
-
2.0
-
-
-
ns
2.0
-
2.0
-
1.0
-
-
-
ns
3.0
-
3.0
-
3.0
-
-
-
ns
-
0.5
-
0.5
-
0.5
-
-
xCLKBA
tH
Hold Time HIGH or LOW
x'CEAS, xCEBA to xCLKAB,
xCLKBA
tw
Pulse Width HIGH or LOW
xCLKAB or xCLKBA(3)
tSK(O) Output Skew(4)
NOTES:
1.
2.
3.
4.
ns
2515tbll0
See test circuits and waveforms.
Minimum limits are guaranteed but not tested on Propagation Delays.
This parameter is guaranteed but not tested.
Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5.11
6
G
I DT54/74FCT16823AT/BT/CT
IDT54/74FCT162823AT/BT/CT
FAST CMOS 18-81T
REGISTER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
The IDT54/74FCT16823AT/BT/CT and IDT541
74FCT162823AT/BT/CT 18-bit bus interface registers are
built using advanced CEMOS, dual metal CMOS technology.
These high-speed, low-power registers with clock enable
(xCLKEN) and clear (xCLR) controls are ideal for parity bus
interfacing in high-performance synchronous systems. The
control inputs are organized to operate the device as two 9-bit
registers or one 18-bit register. Flow-through organization of
signal pins facilitates ease of layout. All inputs are designed
with hysteresis for improved noise margin.
The IDT54/74FCT16823AT/BT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed· with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
The IDT54/7 4FCT162823AT/BT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54/74FCT162823AT/BT/CT are plug-in replacements
for the IDT54/74FCT16823AT/BT/CT and 54/74ABT16823
for on-board interface applications.
-
0.5 MICRON CEMOSTM Technology
High-speed, low-power CEMOS replacement for
ABT functions
- Typical tSK(O) (Output Skew) < 250ps
- ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of -40°C to +85°C
- Vec= 5V±10%
- Speed grades same as FCT-T 9-bit functions
• Features for FCT16823AT/BT/CT:
- High drive outputs (-32mA IOH, 64mA IOL)
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA = 25°C
• Features for FCT162823AT/BT/CT:
- Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce)< 0.6V at
Vec = 5V,TA = 25°C
FUNCTIONAL BLOCK DIAGRAM
20E--------------------~ >---~
10E
lClR
2ClR
lClK
-----------0
>----.....,
2ClK ----------------,
lCLKEN
2ClKEN
,....:.__________.....: r----------:...J/
,~----------~V r----------~/
TO 8 OTHER CHANNELS
V
TO 8 OTHER CHANNELS
2772 drw 01
2772drw02
CEMOS is a trademarll of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
l:
xCLK
Clock Inputs
H
X
xCIKEf\J
Clock Enable Inputs (Active LOW)
L
L
X
X
xCffi
Asynchronous clear Inputs
(Active LOW)
L
H
H
H
H
L
H
H
L
L
H
L
L
H
L
I
xOE
Output Enable Inputs (Active LOW)
xOx
3-State Outputs
2772tblOt
Outputs
xCLK
xDx
xQx
Function
X
X
X
X
X
X
Z
HighZ
L
Clear
0(2)
Hold
i
i
i
i
L
Z
Load
H
Z
L
L
H
H
NOTES:
2772 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
2. Output level before indicated steady-state input conditions were established.
CAPACITANCE (TA= +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Commercial
Military
Unit
VTERM(2) Terminal Voltage
with Respect to
GND
Symbol
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect to
GND
-0.5 to Vee
-0.5 to Vee
V
TA
Rating
Operating
Symbol
Parameter{l)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
4.5
6.0
pF
CoUT
Output
Capacitance
VOUT= OV
5.5
8.0
pF
2772 Ink 04
NOTE:
1. This parameter is measured at characterization but not tested.
-40 to +85
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output
1.0
1.0
W
-60 to +120
-60 to +120
rnA
Current
NOTES:
2772 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
5.12
3
IDT54n4FCT16823AT/BT/CT, l62823AT/BT/CT
FAST CMOS l8-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions AfJply Unless Otherwise Specified:
C ommercla:
. I TA= -40 0 C to + 85 0 C , Vcc= 5 OV ±10%; MT
Iitary: T A = -55 0 C to +125 0 C , VCC= 5.0V + 10%
Parameter
Input HIGH Level
Test Condltlons(l)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee = Max.
Symbol
VIH
VI = Vee
Input HIGH Current (1/0 pins)
IlL
Input LOW Current (Input pins)
VI =GND
Min.
2.0
-
-
Tvp'(2)
Max.
-
±15
-
±15
~
Unit
V
0.8
V
±5
~
±5
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
mA
-
100
-
mV
-
0.05
1.5
mA
Input LOW Current (1/0 pins)
10
Output Drive Current
VH
Input Hysteresis
leeL
leeH
leel
Quiescent Power Supply Current
Vee = Max.
Vo=2.?V
Vo= 0.5V
Vee = Max., VIN = GND or Vee
-
±10
~
±10
-D.?
-1.2
V
-140
-200
mA
2772 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16823T
Symbol
VOH
Parameter
Output HIGH Voltage
Vee = Min.
Test Condltlons(l)
10H=-3mA
VIN = VIH or VIL
VOL
Output LOW Voltage
10FF
InpuVOutput Power Off Leakage
10H = -12mA MIL.
10H = -15mA COM'L.
10H =-24mA MIL.
10H = -32mA COM'U 4)
Vee= Min.
10L= 48mA MIL.
10L= 64mA COM'L.
VIN = VIH or VIL
Vee = OV, VIN or Vo ::; 4.5V
Min.
2.5
Tvp.(2)
2.4
3.5
-
2.0
3.0
-
V
-
0.2
0.55
V
-
-
±100
3.5
Max.
Unit
V
V
~
2772 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162823T
Symbol
100L
Parameter
Output LOW Current
Test Condltlons(l)
Vee = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
Min.
60
Tvp.(2)
115
Max.
150
Unit
mA
-60
-115
-150
mA
2.4
3.3
-
V
-
0.3
100H
Output HIGH Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
Vee = Min.
VIN = VIH or VIL
10H = -16mA MIL.
IOH = -24mA COM'l.
10L= 16mA MIL.
10L = 24mA COM'L.
V
2772 Ink 07
NOTES:
1.
2.
3.
4.
0.55
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
Duration of the condition can not exceed one second.
5.12
4
II
IDT54n4FCT16823AT/BT/CT, 162823AT/BT/CT
FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS'
,
Test Condltlons(1)
Symbol
.6lcc
Parameter
Quiescent power Supply Current
TfL'lnputs HIGH
lecD
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
xOC= xCD 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R= 0)
- 25 mil Center SSOP and Cerpack Packages
- Extended commercial range of ~40°C to +85°C
- Vee = 5V ±10%
- Speed grades same as FCT-T 1O-bit functions
• Features for FCT16827AT/BT/CT:
- High drive outputs (-32mA IOH, 64mA, loL). .
.
- Power off disable outputs permit "live insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V,TA = 25°C
'
• Features for FCT162827AT/BT/CT:
...: ~Balanced Output Drivers:±24mA (commercial),
±16mA (military)
- Reduced system switching noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
'FUNCTIONAL BLOCK DIAGRAM,
10El - - - - - - d
10E2
-----n
lAl
--------I
2CJE'1 - , - - - - - - 0
20E'2
::>-----+------lYl
------0
2A1------I
~~-------,,~------~/
TO 9 OTHER CHANNELS
2n3 drw01
>----f------2Y1
~~-------,,~-----~/
TO 9 OTHER CHANNELS
2773 drw 02
CEMOS is a 1rademarK of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1Il1992 Integrated Device Technology, Inc.
5.13
MAY 1992
DSC-4237/1
1
IDT54174FCT16827AT/BT/CT, 162827AT/BT/CT
FAST CMOS 20-BIT BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
10E1
1Y1
2
56
10E2
55
1A1
10E1
1
56
10E2
1Y1
2
55
1A1
1Y2
3
54
1A2
1Y2
3
54
1A2
GND
4
53
GND
GND
4
53
GND
1Y3
5
52
1A3
1Y3
5
52
1A3
1Y4
6
51
1A4
1Y4
6
51
1A4
Vee
7
50
Vee
Vee
7
50
Vee
1Y5
8
49
1A5
1Y5
8
49
1As
1YS
9
48
1As
1Ys
9
48
1Y7
10
47
1A7
1Y7
10
47
1As
.'1M
GND
11
46
GND
GND
11
46
GND
1Aa'
1Ya
12
45
1Aa
1Ya
12
45
1Y9
13
44
1Ag
1Yg
13
44
1Ag
,
1Y1o
14 8056-1 43
1A10
2Y1
15
42
2A1
2Y1
2Y2
16
41
2A2
2Y2
2Y3
17
40
2A3
GND
18
39
GND
2Y4
19
38
2Y5
20
1Y10
14 , E56-1
43
1A10
15
42
2A1
16
41
2M.
2Y3
17
40
2A3
GND
18
39
GND
2A4
2Y4
19
38
2A4 .
37
2A5
2Y5
20
37
'2As
21
36
2As
, ,
2YS
21
36
2As
2Ys
Vee
22
35
Vee
Vee
22
35
Vee
2Y7
23
34
2A7
2Y7
23
34
2A7
2Ya
24
33
2Aa
2Ya
24
33
2Aa
GND
25
32
GND
2Y9
26
31
2Ag
2Y1o
27
30
20E1
28
29
~,
GND
25
32
GND
2Y9
26
31
2Ag
2A10
2Y10
27
30
2A10
20E2
20E1
28
29
2773 drw 03
2OE2
2773 drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
5.13
2
II
IDT54n4FCT16827ATIBTICT, 162827AT/BT/CT
FAST CMOS 20-BIT BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
xOl:x
xAx
xYx
Outputs
InDuts
DescrlDtlon
Pin Names
X0E1
x0E2
xAx
Data Inputs
L
L
L
L
3·State Outputs
L
L
H
H
H
X
X
X
H
X
Z
Z
Output Enable Inputs (Active LOW)
2773tblOl
xYx
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z =High Impedance
CAPACITANCE (TA= +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Commercial
Military
Unit
VTERM(2) Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect to
GND
-0.5 to Vee
-0.5 to Vee
V
Symbol
Rating
2773tb102
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
4.5
6.0
pF
cauT
Output
Capacitance
VOUT= OV
5.5
8.0
pF
Svmbol
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TSIAS
Temperature
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
2773 Ink 04
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output
1.0
1.0
W
-60 to +120
-60 to +120
rnA
Current
2773 Ink 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
notimplied. Exposureto absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and I/O terminals for FCT162XXXT.
5.13
3
IDT54174FCT16827ATIBTICT, 162827ATIBTICT
FAST CMOS 20-BIT BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
"
Commercial: TA = -40°C to +85°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to + 125°C, Vcc= 5.0V ± 10%
Symbol
Test Condltlons(1)
Parameter
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
'VIL
Input LOW Level
Guaranteed Logic LOW Level
Input HIGH Current (Input pins)
Vee = Max.
Min.
2.0
TVp.(2)
Max.
Unit
-
-
V
-
0.8
V
-
±5
~
-
±15
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
-
, los
Short Circuit Current
Vee = Max., Vo = GND(3)
-80
Vee = Max., Vo = 2.5V(3)
-50
-
-180
mA
-
100
-
mV
0.05
1.5
mA
IIH
VI = Vee
Input HIGH Current (I/O pins)
IlL
Input LOW Current (Input pins)
VI = GND
Input LOW Current (VO pins)
10ZH
High Impedance Output Current
10ZL
(3-State Output pins)
10
Output Drive Current
VH
Input Hysteresis
leeL
leeH
leez
Quiescent Power Supply Current
Vee = Max.
Vo= 2.7V
Vo= 0.5V
Vee = Max., VIN = GND or Vee
-
±5
±15
±10
~
±10
--0.7
-1.2
V
-140
-200
mA
2773 Ink 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16827T
Symbol
VOH
Min.
TVp.(2)
Vee= Min.
10H=..:..JmA
2.5
3.5
-
V
VIN = VIH or VIL
10H = -12mA MIL.
10H = -15mA COM'L.
2.4
3.5
-
V
10H = -24mA MIL.
10H = ..:..J2mA COM'U 4)
2.0
3.0
-
V
10L= 48mA MIL.
10L= 64mA COM'L.
-
0.2
0.55
-
-
±100
Test Condltlons(1)
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
10FF
InpuVOutput Power Off Leakage
Vee = OV, VIN or Vo S 4.5V
Max.
Unit
V
J.IA
2773 Ink 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162827T
Max.
Unit
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min.
60
Typ.(2)
100L
115
150
mA
100H
Output HIGH Current
Vee = 5V, VIN = VIH or VIL. VOUT= 1.5V(3)
-BO
-115
-150
mA
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
IOH=-16mA MIL.
10H = -24mA COM'L.
2.4
3.3
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
10L= 16mA MIL.
10L= 24mA COM'L.
-
0.3
Symbol
Parameter
Test Condltlons(1)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.13
0.55
V
V
27731nk07
4
II
IDT54174FCT16827AT/BT/CT, 162827AT/BT/CT
FAST CMOS 20-BIT BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Svmbol
Alec
IceD
Parameter
Quiescent Power Supply Current
TIL Inputs HIGH
Dynamic Power Supply Current(4)
Test Condltlons(1)
Min.
Typ.(2)
-
0.5
Max.
1.5
VIN = Vee
VIN = GND
-
60
100
Vee = Max.
Outputs Open
fi=10MHz
50% Duty Cycle
X0I:1 = X0I:2 = GND
One Bit Toggling
VIN = Vee
VIN = GND
-
0.7
2.5
VIN = 3.4V
VIN = GND
-
0.9
3.3
Vee = Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
X0I:1 = X0E2 = GND
Twenty Bits Toggling
VIN = Vee
VIN = GND
-
3.1
6.5(5)
VIN = 3.4V
VIN = GND
-
8.1
21.5(5)
Vee = Max.
VIN = 3.4v(3)
Vee = Max.
Outputs Open
Unit
mA
~N
MHz
GND
One Input Toggling
50% Duty Cycle
X"C5E1 = X"C5E2 =
Ie
Total Power Supply Current(S)
2773 tbl 08
NOTES:
1.
2.
3.
4.
5.
6.
mA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc m 5.0V, +25°C ambient.
Per TTL driven Input (V IN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Ico formula. These limits are guaranteed but not tested.
Ie - laulEscENT + IiNPUTS + IDYNAMIC
Ic .. Icc + ~Icc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (lcCl, lOCH and Iccz)
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HlH or lHL)
fcp .. Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
5.13
5
IDT54174FCT16827AT/BT/CT,162827AT/BT/CT
FAST CMOS 20-BIT BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16827AT/162827AT
Com'l.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
xAx to xYx
FCT16827BT/162827BT
Com'l.
Mil.
FCT16827CT/162827CT
Mil.
Com'l.
Mil.
Condltlons(l) MlnJ2) Max. MlnJ2) Max. Mln.(2) Max. Mln.(2) Max. MlnJ2) Max. MlnJ2) Max.
CL= 50pF
RL = 500.a
CL = 300pF(3)
1.5
8.0
1.5
9.0
1.5
5.0
1.5
6.5
1.5
4.4
1.5
5.0
1.5
15.0
1.5
17.0
1.5
13.0
1.5
14.0
1.5
10.0
1.5
11.0
Unit
ns
RL= 500n
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
xOEx to xYx
Output Disable Time
xOI:x to xYx
CL = 50pF
RL = 500n
CL = 300pF(3)
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
1.5
7.0
1.5
8.0
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
1.5
14.0
1.5
15.0
RL= 500n
CL = 5pF(3)
1.5
9.0
1.5
9.0
1.5
6.0
1.5
7.0
1.5
5.7
1.5
6.7
1.5
10.0
1.5
10.0
1.5
7.0
1.5
8.0
1.5
6.0
1.5
7.0
-
0.5
-
-
0.5
-
0.5
-
0.5
-
0.5
0.5
ns
27731bI09
NOTES:
1.
2.
3.
4.
ns
RL = 500n
CL = 50pF
RL = 500n
tSK(O) Output Skew(4)
ns
See test circuit and waveforms.
Minimum limits are guaranteed but not tested on Propagation Delays.
These conditions are guaranteed but not tested.
Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
II
5.13
6
~
.IDT54/74FCT16841AT/BT/CT
IDT54/74FCT162841AT/BT/CT
FAST CMOS 20-81T
TRANSPARENT
LATCHES,
Integrated Device Technology, Inc•
..
'
FEATURES:
DESCRIPTION:
The IDT54/74FCT16841AT/BT/CT and IDT541
74FCT162841 AT/BT/CT 20-bit transparent D-type latches
are built using advanced CEMOS, dual metal CMOS technol'ogy. These high-speed, low-power latches are ideal for
temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers. The
Output Enable, and Latch Enable controls are organized to
operate each device as two 1O-bit latches or one 20-bit latch.
Flow-through organization of signal pins facilitates ease of
layout. All inputs are designed with hysteresis for improved
noise margin.
'
The IDT5417 4FCT16841 AT/BT/CT are ideally suited for
driving high capacitance loads and low impedance backplanes.
The output buffers are designed with Power-Off Disable
capability to allow "live insertion" of boards when used as
backplane drivers.
The IDT54/74FCT162841 AT/BT/CT have balanced output
drive with current limiting resistors. This offers low ground
bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
The IDT54/7 4FCT162841 AT/BT/CT are plug-in replacements
for the IDT54/74FCT16841AT/BT/CT and 54174ABT16841
for on-board interface applications.
.: Common ,features:
'- 0.5 MICRON CEMOSTM ,Technology
..:... High-speed, low-power CEMOS replacement for
ABT fonctions
- Typical tSK{O) (Output Skew) < 2S0ps
.-
ESD> 2000V per MIL-STD-883, Method 3015;
. > 200V using machine model (C = 200pF, R = 0)
25 mil Center SSOP and Cerpack Packages
Extended commercial range of -40°C to +85°C
Vee = 5V ±10%
Speed grades same as FCT-T 10-bit functions
• Features for FCT16841AT/BT/CT:
-
High drive outputs (-32m A IOH, 64mA loL)
Power off disable outputs permit "live insertion"
Typical VOLP (Output Ground Bounce) < 1.0V at
Vee = 5V, TA= 25°C
• Features for FCT162841 A T/BT/CT:
-
Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at
Vee = 5V,TA = 25°C
FUNCTIONAL BLOCK DIAGRAM
10E
2m; --------<1
-------------------
DEB
Bo
A
Q1K
Q2
Q3
B1
B2
B3
Reg.
~: ~
~:
QS:r
Q7 v
Bs
B7
~Qo
Oor---01 \--'"----1
----1-- Q1
L..---C~~Q2
02~----~
L..----<:s- Q3
B 03 ~---~
~ Q4 Reg. 04
~----_ _
P 07
Q7 CrE ClL-_ _ _____________
CPB
L..----------------------CEB
2629 drw 01
NOTE:
1. IDT29FCT52T function is shown. IDT29FCT53T is the inverting option.
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
elay
E1 or E2 to On
tPLH
tPHL
Prop~ation Delay
E3 to On
Mil.
IDT54n4FCT138AT
IDT54n4FCT138CT
Com'l.
Com'l.
Mil.
Mil.
Mln.(2) Max. Mln.(2) Max. Mln. (2) Max. Mln.(2) Max. Mln.(2) Max. Mln.l2) Max.
Unit
1.5
9.0
1.5 12.0
1.5
5.B
1.5
7.B
1.5
5.1
1.5
6.0
ns
1.5
9.0
1.5 12.5
1.5
5.9
1.5
8.0
1.5
5.2
1.5
6.1
ns
1.5
9.0
1.5 12.5
1.5
5.9
1.5
8.0
1.5
5.2
1.5
6.1
ns
NOTES:
2570tbl08
1. See test circuit and waveforms.
2. Minimum Umits are guaranteed but not tested on Propagation Delays.
6.3
4
(;)
Integrated Device Technology, Inc.
IDT54/74FCT139T
IDT54/74FCT139AT
IDT54/74FCT139CT
FAST CMOS DUAL
1-0F-4 DECODER
WITH ENABLE
FEATURES:
DESCRIPTION:
• IDT54/74FCT139T equivalent to FASTTM speed
The IDT54/74FCT139T/AT/CT are dual 1-of-4 decoders
built using advanced CEMOSTM, a dual metal CMOS technology. These devices have two independent decoders, each of
which accept two binary weighted inputs (Ao-A!l aQif provide
four mutually exclusive active LOW outputs (00-03). Each
decoder has an active LOW enable {E). When E is HIGH, all
outputs are forced HIGH.
• IDT54174FCT139AT 35% faster than FAST
• IDT54174FCT139CT 45% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 4BmA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST
(51lA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-BB3, Class B
FUNCTIONAL BLOCK DIAGRAM
Ea
AOa
Ala
PIN CONFIGURATIONS
AOb
Alb
Ea
Vee
Aoa
Ala
Mb
Eb
OOa
Alb
01a
02a
Gob
OSa
01b
02b
GND
OSb
2566 cnv· 01
DIP/SOIC/CERPACK
TOP VIEW
INDEX
cba
u 8
z > ILfl
~
« ILfi
Dab
I II I I
............ I
2566 cnY" 03
3 2
Ala
:1 4
Ooa :1 5
NC :16
Dla :1 7
02a :1 8
II II I
I......,......,
L..!
20 19
18[:
17[:
16[:
L20-2
15[
14[
9 10 11 12 13
1
AOb
Alb
NC
Dab
Dlb
r-1 r-1 r-1 r-1 r-1
I II I I I I II I
n!
10
t§
Z
~
t3
,0 ,0
2566 cnv· 02
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11;)1992 Integrated Device Technology. Inc.
OU
6.4
MAY 1992
DSC-420&J3
1
IDT54n4FCT139T/AT/CT FAST
FAST CMOS DUAL 1-0F-4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1}
PIN DESCRIPTION
Inputs
Description
Pin Names
Out luts
AO,A1
Address Inputs
E
Ao
A1
00
01
02
03
E
Enable Input (Active LOW)
H
X
X
H
H
00- 03
Outputs (Active LOW)
L
L
L
L
H
H
H
H
25661bl 07
H
L
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
NOTE:
25661bl06
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
ABSOLUTE MAXIMUM RATINGS(1}
SYmbol
Ratln~
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Commercial
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
-0.5 to +7.0 -0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
o to +70
-55 to +125
°C
Conditions
T~p.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
Symbol
Unit
Parameter(l)
NOTE:
2566 Ibl 02
1. This parameter is measured at characterization but not tested.
Temperature
TSIAS
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
NOTES:
25661blOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. this is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
6.4
2
IDT54n4FCT139T/AT/CT FAST
FAST CMOS DUAL 1-0F-4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
.Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Parameter
Input HIGH Level
Test Condltlons(1)
Guaranteed Logic HG-l Level
VIL
Input LOW Level
Guaranteed Logic LON Level
IIH
Input HIGH Current
Vee = Max.
II L
Input LOW Current
II
Input HIGH Current
VIK
Clamp Diode Voltage
= Max.
= Max., VI = Vee (Max.)
Vee = Min., IN = -1 SmA
Vee = Max.(3), Vo = GND
10H = -SmA MIL.
Vee = Min.
VIN = VIH or VIL
10H = -SmA COM'L.
10H =-12mA MIL.
10H =-15mA COM'L.
IOL = 32mA MIL.
Vee = Min.
VIN = VIH or VIL
10L = 4SmA COM'L.
Vee = Max.
VIN = GND or Vee
Symbol
VIH
los
Short Circuit Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power Supply Current
= 2.7V
VI = 0.5V
VI
Vce
Vee
Min.
2.0
-
-
TVp.(2)
Max.
Unit
V
-
-
-
O.S
V
-
5
IlA
IlA
-5
-
-{J.7
-1.2
IlA
V
-60
-120
-225
mA
2.4
3.3
-
V
2.0
3.0
-
V
-
0.3
0.5
V
-
200
-
mV
0.2
1.5
mA
NOTES:
20
25661bl03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. .
6.4
3
IDT54174FCT139T/AT/CT FAST
FAST CMOS DUAL 1-0F-4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
dice
leeD
Ie
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current(6)
TVp.(2)
Max.
Unit
-
0.5
2.0
rnA
-
0.15
0.3
mAl
MHz
-
1.7
4.5
rnA
-
2.0
5.5
VIN = Vee
VIN =GND
-
3.2
7.5(5)
VIN = 3.4V
VIN = GND
-
3.7
9.5(5)
Test Condltlons(1)
Vee = Max.
VIN = 3.4V(3)
Vee = Max.
VIN = Vee
Outputs Open
VIN = GND
One Bit Toggling
50% Duty Cvcle
Vee = Max.
VIN = Vee
Outputs Open
VIN = GND
fo = 10MHz
50% Duty Cycle
VIN = 3.4V
One Output Toggling
VIN = GND
Vee = Max.
Outputs Open
fo = 10MHz
50% Duty Cycle
One Output Toggling
on Each Decoder
Min.
NOTES:
1.
2.
3.
4.
5.
6.
2566tbl04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TTL driven Input (VIN .. 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic .. IQUIESCENT + IINPUTS + IDYNAMIC
Ic .. Icc + alcc DHNT + ICCD (fcp/2 + foNo)
Icc .. Quiescent Current
alcc .. Power Supply Current for a TTL High Input (VIN .. 3.4V)
DH = Duty Cycle for TTL Inputs High
NT .. Number of TTL Inputs at DH
ICCD - Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp .. Clock Frequency for Register Devices (Zero for Non-Register Devices)
fa = Output Frequency
No .. Number of Outputs at fa
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT139T
Com'l.
Parameter
Description
Condltlon(1)
tPLH
tPHL
Propagatio~Delay
CL = 50pF
Aoor A1 to On
RL= 500n
tPLH
tPHL
frop!.gation Delay
Eto On
Mil.
Mln.(2) Max.
IDT54174FCT139AT
IDT54174FCT139CT
Com'l.
Mil.
Com'l.
Mil.
Mln.(2) Max.
Mln.(2) Max.
Mln,(2) Max.
Mln.(2) Max. Mln.(2) Max.
Unit
1.5
9.0
1.5 12.0
1.5
5.9
1.5
7.8
1.5
5.0
1.5
6.2
ns
1.5
8.0
1.5
1.5
5.5
1.5
7.2
1.5
4.8
1.5
5.8
ns
NOTES:
9.0
2566 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.4
4
~
FAST CMOS
a-INPUT MULTIPLEXER
IDT54/74FCT151 TI AT/CT
IDT54174FCT251TIAT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT151T/251T equivalent to FASTN speed
and drive
The IDT54174FCT151T/AT/CTand IDT54174FCT251TI ATI
CT are high-speed 8-input multiplexers built using advanced
CEMOSN, a dual metal CMOS technology. They select one
bit of data from up to eight sources under the control of three
select inputs. Both assertion and negation outputs are
provided.
The IDT5417 4FCT151 T/AT/CT has a common Active-LOW
enable (E) input. When E is LOW, data from one of eight inputs is routed to the complementary outputs according to the
3-bit code applied to the Select (SO-S2) inputs. A common
application of the 'FCT151 is data routing from one of eight
sources.
The IDT54174FCT251 T/AT/CT has a common Active-LOW
Output Enable (OE) input. When OE is LOW, data from one
of eight inputs is routed to the complementary outputs. When
OE is HIGH, both outputs are in the high-impedance state.
This feature allows multiplexer expansion by tying several
outputs together.
• IDT54/74FCT151AT/251AT25%fasterthan FAST
• IDT54174FCT151 CT/251 CT 50% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
.
• TTL input and output level compatible
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
.J.
FUNCTIONAL BLOCK DIAGRAM
17
'\
J
1
I
.-- ~
"'\
J
Is
I
)-
15
1
~
14
I
13
Z
1-
I
)-
12
1
'\
./
11
I
~~
"'\
J
10
.-
82
81
80
E for 151
DE for 251
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology, Inc.
-Z
n~")
)---lFi'
1==1
6.5
r-
I
I
I
I
1--
-j
I
I
I
I
I
r-J
L_FCT25~nIY J
2635 drw 03
MAY 1992
DSC-421212
1
IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS a·INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
()
N
13
Vee
12
14
11
10
15
I
~~.::!:
C'l
II
II
II II I
I L-I L-I
L-I L-I I
11
10
16
NC
3
:1 4
:1 5
:1 6
2
,U
1
20 19
18[:
17[:
15
16
16[:
NC
L20·2
Z
17
Z
So
Z ]7
15[:
17
*E or OE
S1
]8
14[:
Sl
GND
S2
Z
9 10 11 12 13
r-t r-t r-t r-t ,...,
I
II
I
I
II
II
I
I~ ~ ~ OJ en
DIP/SOIC/CERPACK
TOP VIEW
o
2635 drw 01
(!)
1!o1l
2635 drw 02
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND'
VTERM(3) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
Temperature
PT
lOUT
PIN DESCRIPTION
Pin Names
TA
TSTG
*E for 151 only. OE for 251 only.
-55 to +125
-65 to +150
°C
Power Dissipation
0.5
0.5
W
DC Output
Current
120
120
rnA
Symbol
CIN
COUT
Parameter(1)
Data Inputs
So- S2
Selects Inputs
E
Enable Input (Active LOW)-FCT151
OE
Output Enable Input (Active LOW)-FCT251
Z
Data Output
Z
Inverted Data Output
2635tbl01
FUNCTION TABLE(2)
NOTES:
2635 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and ,Vee terminals only.
3. Outputs and 1/0 terminals only.
CAPACITANCE (TA =
Description
10 - 17
Inputs
+25°C, f = 1.0MHz)
Conditions
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
6
10
pF
Output
Capacitance
VOUT= OV
8
12
Outputs
S2
S1
So
E/OE(1)
Z
Z
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
L(151)
Z(251)
10
H(151)
Z(?51)
10
11
11
12
13
14
15
16
17
i2
is
14
15
16
T7
NOTES:
26351bl02
1. E for 151, OE for 251.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't care, Z =
High Impedance.
pF
NOTE:
26351bl04
1. This parameter is measured at characterization but not tested.
6.5
2
IDT54174FCT151T/AT/CT, IDT54174FCT251 T/AT/CT
FAST CMOS a-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V ± 10%
Min.
Typ,!2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
VI =2.7V
II l
Input LOW Current
Vee = Max.
VI = 0.5V
-
-
10ZH
High Impedance Output Current
Vee = Max.
Va = 2.7V
Sy_mbol
Test Condltlons(1)
Parameter
10Zl
Va = 0.5V
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vce = Min., IN = -18mA
los
Short Circuit Current
Vee = Max.(3), Va = GND
VOH
Output HIGH Voltage
-
Max.
-
V
0.8
V
5
J.IA
J.IA
J.IA
-
-5
-
-10
-
Unit
10
20
J.IA
~.7
-1.2
V
-60
-120
-225
rnA
2.4
3.3
-
V
10H = -12mA MIL.
2.0
3.0
-
V
=-15mA COM'L.
10l =32mA MIL.
-
0.3
0.5
V
200
-
mV
0.2
1.5
rnA
Vee = Min.
10H = -6mA MIL.
VIN = VIH or Vil
10H = -SmA COM'L.
10H
Val
Output LOW Voltage
Vee = Min.
VIN
VH
Input Hysteresis
Icc
Quiescent Power Supply Current
=VIH or Vil
10l = 48mA COM'L.
-
Vee = Max.
VIN = GND or Vee
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
263StbiOS
POWER SUPPLY CHARACTERISTICS
Svmbol
Parameter
Alec
QuiescentPower Supply Current
TTL Inputs HIGH
IceD
Dynamic Power Supply Current(4)
Test Condltlons(1)
Vee = Max.
VIN = 3.4V(3)
Vee = Max.
VIN = Vee
Qutputs Open
EorOE= GND
VIN = GND
Min.
-
Tvp.(2)
Max.
Unit
0.5
2.0
rnA
0.15
0.25
mAl
MHz
One Bit Toggling
50% Duty Cycle
Ie
Total Power Supply Current(5)
Vee = Max.
VIN = Vee
Outputs Open
VIN = GND
-
3.2
6.5
-
3.5
7.5
rnA
fi = 10MHz
§..O% Duty Cycle
EorOE= GND
VIN = 3.4V
VIN = GND
One Input Toqqlinq
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + dlcc DHNT + ICCD (fcp/2 + fiNo)
Icc = Quiescent Current
dlcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
No = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.5
2635tbl06
3
IDT54174FCT151T/AT/CT,IDT54174FCT251T/AT/CT
FAST CMOS S-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - IDT54/74FCT151T/AT/CT
IDT54174FCT151 T
Com'l.
", Parameter
Symbol
Condltlon(1)
tPLH
tPHL
prop~ation Delay
CL= 50pF
SNtoZ
RL =
tPLH
tPHL
propagation Delay
SNtoZ
tPLH
tPHL
.!:"o~gation Delay
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
propagation Delay.
'EtoZ
'
soon
EtoZ
prop~ation
Delay
INtoZ
propagation Delay
IN to Z
Mil.
IDT54174FCT151AT
Com'l.
Mil.
IDT54174FCT151 CT
Com'l.
MIl.
Mln.(2)
Max.
Mln,!2)
Max.
Mln,!2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Unit
1.5
9.0
1.5
10.0
1.5
6.6
1.5
7.4
1.5
5.6
1.5
6.2
ns
1.5
10.5
1.5
11.5
1.5
6.8
1.5
7.6
1.5
5.8
1.5
6.5
ns
1.5
7.0
1.5
7.5
1.5
5.6
1.5
6.3
1.5
4.8
1.5
5.4
ns
1.5
9.5
1.5
11.0
1.5
5.8
1.5
6.6
1.5
5.0
1.5
5.7
ns
1.5
6.5
1.5
7.5
1.5
5.2
1.5
5.8
1.5
4.4
1.5
4.9
ns
1.5
7.5
1.5
9.0
1.5
5.5
1.5
6.1
1.5
4.7
1.5
5.2
ns
2635tbl07
SWITCHING CHARACTERISTICS OVER OPERATING RANGE -IDT54/74FCT251T/AT/CT
IDT54/74FCT251T
Com'l.
Parameter
Svmbol
tPLH
tPHL
propag,ation Delay
SNtoZ
tPLH
tPHL
propagation Delay
SNtoZ
tPLH
tPHL
tPLH
tPHL
prop~ation
Delay
Condltlon(1)
CL = 50pF
RL =
soon
Mil.
IDT54/74FCT251AT
Com'l.
Mil.
IDT54/74FCT251CT
Com'!.
Mil.
Mln.(2)
Max.
Mln,!2)
Max.
Mln,!2)
Max.
Mln.(2)
Max.
Mln,!2)
Max.
Mln,!2)
Max.
Unit
1.5
9.0
1.5
9.5
1.5
6.6
1.5
7.4
1.5
5.6
1.5
6.2
ns
1.5
11.0
1.5
14.0
1.5
6.8
1.5
7.6
1.5
5.8
1.5
6.5
ns
1.5
7.0
1.5
8.0
1.5
5.2
1.5
5.8
1.5
4.4
1.5
4.9
ns
propagation Delay
INtoZ
1.5
7.0
1.5
8.0
1.5
5.5
1.5
6.1
1.5
4.7
1.5
5.2
ns
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
Outpu.!..Enable Time
OEtoZ
1.5
9.0
1.5
10.0
1.5
6.7
1.5
7.4
1.5
5.7
1.5
6.3
ns
Output Disable Time
OEtoZ
1.5
7.5
1.5
8.5
1.5
6.0
1.5
6.4
1.5
5.0
1.5
5.4
ns
Output Enable Time
OEtoZ
1.5
9.0
1.5
10.0
1.5
6.7
1.5
7.6
1.5
5.7
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
OEtoZ
1.5
7.0
1.5
7.0
1.5
6.0
1.5
6.3
1.5
5.0
1.5
5.2
ns
INtoZ
NOTES:
2635tb108
1. See test circuit and waveforms.
2. Minimum limitS are guaranteed but not tested on Propagation Delays.
6.5
4
~®
IDT54174FCT157T/AT/CT
IDT54174FCT257T/AT/CT
FAST CMOS
QUAD 2-INPUT
MULTIPLEXER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT157T/257T equivalent to FASpM speed
and drive
• IDT54174FCT157AT/257AT 25% faster than FAST
• IDT54174FCT157CT/257CT 50% faster than FAST
• TTL input and output level compatible
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IDL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced Versions
• Military product compliant to MIL-STD-883, Class 8 and
DESC listed
The IDT54174FCT157T/AT/CT and IDT54174FCT257TI
AT/CT are high-speed quad 2-input multiplexers built using
advanced CEMOSTM, a dual metal CMOS technology. Four
bits of data from two sources can be selected using the
common select input. The four buffered outputs present the
selected data in the true (non-inverting) form.
The IDT54/74FCT157T/AT/CT has a common, activeLOW, enable input. When the enable input is not active, all
four outputs are held LOW. A common application of' FCT157T
is to move data from two different groups of registers to a
common bus. Another application is as a function generator.
The 'FCT157T can generate any four of the 16 different
functions of two variables with one variable common.
The IDT54/74FCT257T/AT/CT has a common Output
Enable (OE) input. When OE is HIGH, all outputs are switched
to a high-impedance state allowing the outputs to interface
directly with bus-oriented systems.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
s
Vee
S
EorDE"
lOA
11A
11 B -110 ---+-t-1f-t--+--+---I--'
ZB-Zo
lac
ZA
lOB
11e
Ze
11B
100
ZB
110
Zo
GND
/OB -100 ---++--11--+--+--+---1_
DIP/SOIC/CERPACK
TOP VIEW
11A ----t-II-t--+----I--'
ZA
I
lOA
I~
I
i--------------..J
1-
257 Dnly I DE
I
~--------------~
<
0 0 0
200 Z~IW
INDEX
2537 drw 02
....
'--' 0.._'1 1'--' '--'
3 2 I 120 19
18 [ lac
'1
11A
] 4
ZA
NC
] 5
] 6
lOB
] 7
15 [
Ze
I1B
] 8
14 [
9 10 11 1213
100
L20-2
17[ he
16 [ NC
1111.,,...,,....,
mOO Oo
N~ZN-=
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
• E for FCT157, OE for FCT257.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1992 Integrated Device Technology, Inc.
2537 drwOl
6.6
MAY 1992
DSC-4221J2
1
IDT54n4FCT157T/AT/CT,IDT54/74FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
Description
Inputs
Output ZN
lOA-laD
Source 0 Data Inputs
E/OE
S
10
11
157
257
11 A-I 1 0
Source 1 Data Inputs
H
X
X
X
L
Z
E
Enable Input (Active LOW)-FCT157T
L
H
X
L
L
L
OE
Output Enable (Active LOW)-FCT257T
L
H
X
H
H
H
S
Select Input
L
L
L
X
L
L
ZA-Zo
Outputs
L
L
H
X
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2537tbl05
2537tbl06
Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM( 2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
TA
with Respect
toGND
Operating
Temperature
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
f = 1.0MHz)
Conditions
Typ.
Max.
Unit
Input Capacitance
VIN= OV
6
10
pF
COUT
Output Capacitance
VOUT= OV
8
12
NOTE:
V
pF
2537 tbl 02
1. This parameter is guaranteed but not tested.
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
(TA = +25°C,
Parameter(1)
CIN
Symbol
2537tbiOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and I/O terminals only.
6.6
2
IDT54n4FCT157T/AT/CT, IDT54/74FCT257T/AT/CT
FAST CMOS QUAD 2·INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial' TA= OOG +70°C , Vcc = 5 OV +
- 5%', Military" TA = -55°C to +125°C, Vcc = 5 OV +
- 10%
to
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
0.8
V
IIH
Input HIGH Current
Vce = Max.
VI = 2.7V
-
5
!lA
!lA
!lA
Symbol
Test Condltlons(1)
Parameter
ilL
Input LOW Current
Vee = Max.
VI = 0.5V
-
10ZH
High Impedance Output
Vee = Max.
Vo= 2.7V
-
10ZL
Current
Vo= 0.5V
-
-
II
Input HIGH Current
Vee = Max., VI
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
-0.7
-1~2
V
los
Short Circuit Current
Vee = Max,!Sl, Vo = GND
-60
-120
-225
mA
VOH
Output HIGH Voltage
2.4
3.3
-
V
2.0
3.0
-
V
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
rnA
=
Vee (Max.) _
Vee = Min.
10H =-6mA MIL.
VIN = VIH or VIL
10H = -8mA COM'L.
10H =-12mA MIL.
-
-5
10
-10
20
!lA
10H = -15mA COM'L.
VOL
Output-LOW Voltage
Vee = Min.
10L = 32mA MIL.
VIN = VIH or VIL
10L = 48mA COM'L.
-
VH
Input Hysteresis
lee
Quiescent Power Supply
Vee = Max.
Current
VIN
=GND or Vee
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
_
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.6
25371b103
3
IDT54174FCT157T/AT/CT,IDT54174FCT257T/AT/CT
FAST CMOS QUAD 2-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Min.
Typ.<2)
-
0.5
Max.
2.0
Unit
rnA
VIN = Vee
VIN = GND
-
0.15
0.25
rnA/MHz
Vee = Max.
Outputs Open
fie 10MHz
§.O% Duty Cycle
EorOE= GND
One Bit Toggling
VIN = Vee
VIN = GND
-
1.7
4.0
rnA
VIN = 3.4V
VIN = GND
-
2.0
5.0
VIN .. Vee
Outputs Open
fie 2.5MHz
§.O% Duty Cycle
EorOE= GND
Four Bits Toggling
VIN "" Vee
VIN = GND
-
1.7
4.0(5)
VIN = 3.4V
VIN = GND
-
2.7
8.0(5)
Symbol
.1lcc
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Condltlons(1)
Vee = Max .
VIN = 3.4v(3)
IceD
Dynamic Power Supply Current(4)
Vee = Max.
Qutputs Open
EorOE= GND
One Bit Toggling
50% Duty Cyele
Ie
Total Power Supply Current(6)
NOTES:
1.
2.
3.
4.
5.
6.
2537tbl04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc ,. 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic - IQUIESCENT + liN PUTS + IDYNAMIC
Ic - Icc + £\Icc DHNT + ICCD (fcp/2 + toNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH ,. Duty Cycle for TIL Inputs High
NT .. Number of TIL Inputs at DH
ICCD - Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
h .. Input Frequency
Ni .. Number of Inputs at to
All currents are in milliamps and all frequencies are in megahertz.
6.6
4
IDT54n4FCT157T/AT/CT, IDT54/74FCT257T/AT/CT
FAST CMOS QUAD 2-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - FCT157T/AT/CT
54174FCT157T
Symbol
tPLH
tPHL
Parameter
Propagation Delay
IN to ZN
tPLH
tPHL
~ropagation Delay
tPLH
tPHL
Propagation Delay
Sto ZN
54174FCT157AT
Mil.
Com'l.
Mil.
Com'l.
5417 4FCT157CT
Mil.
Com'l.
Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln,<2) Max. Mln.(2) Max. Mln.(2) Max. MinP) Max. Unit
CL= 50 pF
RL= 500n
1.5
6.0
1.5
7.0
1.5
5.0
1.5
5.8
1.5
4.3
1.5
5.0
ns
1.5
10.5
1.5
12.0
1.5
6.0
1.5
7.4
1.5
4.8
1.5
5.9
ns
1.5
10.5
1.5
12.0
1.5
7.0
1.5
8.1
1.5
5.2
1.5
6.0
ns
E to ZN
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - FCT257T/AT/CT
5417 4FCT257AT
54174FCT257T
Mil.
Com'l.
Symbol
Parameter
Mil.
Com'l.
5417 4FCT257CT
Com'l.
Mil.
Conditlon(1) Mln.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
1.5
6.0
1.5
7.0
1.5
5.0
1.5
5.8
1.5
4.3
1.5
5.0
ns
Propagation Delay
Sto ZN
1.5
10.5
1.5
12.0
1.5
7.0
1.5
8.1
1.5
5.2
1.5
6.0
ns
tPZH
tPZL
Output Enable
Time
1.5
8.5
1.5
10.0
1.5
7.0
1.5
8.0
1.5
6.0
1.5
6.8
ns
tPHZ
tPLZ
Output Disable
Time
1.5
6.0
1.5
8.0
1.5
5.5
1.5
5.8
1.5
5.0
1.5
5.3
ns
tPLH
tPHL
Propagation Delay
IN to ZN
tPLH
tPHL
CL= 50 pF
RL= 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2537tbl07
6.6
5
G®
Integrated. bevlce Technology, Inc.
FEATURES:
~
•
•
•
•
•
•
•
•
•
•
IDT54/74FCT161TIAT/CT
IDT54/74FCT163TIAT/CT
FAST CMOS
SYNCHRONOUS
PRESETTABLE
. BINARY COUNTERS·
,
DESCRIPTION:
IDT54/74FCT161T/163T equivalent to FAST"M speed
IDT54174FCT161ATI163AT 35% faster than FAST .
IDT54174FCT161CT/163CT 45% faster than FAST
Equivalent to FAST output drive over full temperature
and voltagesupply extremes
10L = 48mA (commercial), 32mA (rnilitary)
CMOS power levels (1 mW typo static).
True TTL input and output levels
Substantially lower input current levels than FAST
(5JlA max.) .
..
.
JEDECstandard pinout for DIP and LCC
Product available in Radiation Tolerant and·Radiation .
Enhanced versions
Military product compliant to MIL-STD-883, Class B
The IDT54174FCT161T/163T; IDT54174FCT161AT/163AT
and IDT5417 4FCT161 CT/163CT are high-speed synchronous. modul0-16 binary counters built using advanced
CEMOSTM, a dual metal CMOS technology. They are synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a terminal
count output for versatility in forming synchronous mUlti-stage
counters. The IDT54174FCT161T/AT/CT have asynchronous Master Reset inputs that override all other inputs and
force the outputs LOW. The IDT54174FCT163T/AT/CT have
Synchronous Reset inputs that override counting and parallel
loading and allow the outputs to be simultaneously reset on
the rising edge of the clock.
FUNCTIONAL BLOCK DIAGRAM
Po
P3
·PE~----a-~______________-.~__________~________~____________~
CEP-=~==~~~~
____~__~~______~~______~~____-.
CET------~~-----------+---+~--------~~------~~------~----_H_.
: 163
:ONLY
~
TC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CP
I
DETAIL
DETAIL
DETAIL
A
A
A
01
02
03
MR (,161)
SR ('163)
00
2611 drw01
CEMOS is a trademark 01 Integrated Device Technology, Inc.
FAST is a trademark 01 National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
te1992 Integrated Device Technology, Inc.
6.7
MAY 1992
DSC-4219t3
1
IDT54174FCT161T/AT/CT,IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
*R
CP
....... L....IIIL....IL...I
3
00
01
02
03
Po
PI
P2
P3
CEP
GND
~I~ ~ ~ ~
INDEX
Vcc
TC
Po ]
4
P1
5
]
NC
CET
PE
2 I I 20 19
l'
] 6
P2
]
P3
] 8
L20-2
7
18 [
00
17 [
01
16 [
NC
15 [
02
14 [
03
9 10 11 12 13
,......,,...,,......,,......,,......,
2611 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
*MRfor'161
*SR for '163
FUNCTION TABLE(2)
PIN DESCRIPTION
Pin Names
Description
Action on the Rising
Clock Edge(s)
SR(1)
PE
CET
CEP
Count Enable Trickle Input
L
X
L
X
X
X
X
Load (Pn~On)
Count (Increment)
CEP
Count Enable Parallel Input
CET
Reset (Clear)
CP
Clock Pulse Input (Active Rising Edge)
H
MR('1S1)
Asynchronous Master Reset Input (Active LOW)
H
H
H
H
SR ('163)
Synchronous Reset Input (Active LOW)
H
H
L
X
No Change (Hold)
PO-3
Parallel Data Inputs
H
H
X
L
No Change (Hold)
PE
Parallel Enable Input (Active LOW)
00-3
Flip-Flop Outputs.
TC
Terminal Count Output
NOTES:
2611 tbl06
1. For FCT163/163A only.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care.
2611 tbl05
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
TA
Operati~g
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
o to +70
-55 to +125
°C
Symbol
Parameter(1)
Conditions Typ.
CIN
Input Capacitance
VIN = OV
COUT
Output Capacitance VOUT= OV
Max.
Unit
6
10
pF
8
12
pF
NOTE:
2611 tbl02
1. This parameter is guaranteed at characterization but not tested.
Temperature
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
2611 tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vce by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 1/0 terminals only.
6.7
2
IDT54f74FCT161T/AT/CT, IDT54f74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Typ.(2)
Test Conditlons(1)
Symbol
Parameter
Min.
I COM'L(4)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0V
2.7V
I MIL
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
0.8
V
5
~
-
-
-5
~
-
20
~
Vee = Min., IN = -18mA
-
'-{J.7
-1.2
V
Vee = Max.(3), Vo = GND
-60
-120
-225
rnA
IOH = -6mA MIL.
IOH = -8mA COM'L.
2.4
3.3
-
~
IOH =-12mA MIL.
IOH = -15mA COM'L.
2.0
3.0
-
V
IOL= 32mA MIL.
IOL= 48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
0.2
1.5
rnA
Vee = Max.
VI = 2.7V
IlL
Input LOW Current
Vee = Max.
VI
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or VIL
VH
Input Hysteresis
Ice
Quiescent Power
Supply Current
Unit
V
V
-
Input HIGH Current
Output LOW Voltage
-
-
IIH
VOL
Max.
Vee= Min.
VIN = VIH or VIL
Vee = Max.
VIN == GND or Vee·
= 0.5V
,
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Clock pin requires a minimum VIH of 2.5V.
6.7
2611 tbl03
3
IDT54n4FCT161T/AT/CT,IDT54n4FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
-
0.5
2.0
rnA
VIN = Vee
VIN=GND
-
0.15
0.25
Vee = Max., Outputs Open
Load Mode
fep = 10MHz
50% Duty Cycle
CEP .. CET = PE ... GND
MRorSR .. Vee
One Bit Toggling
at fi =5MHz
50% Duty Cycle
VIN .. Vee
VIN= GND
-
1.7
4.0
VIN .. 3.4V
VIN= GND
-
2.2
6.0
Vee = Max., Outputs Open
Load Mode
fep = 10MHz
50% Duty Cyc~
CEP = CET = PE =GND
MRorSR= Vee
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle
VIN = Vee
VIN=.GND
-
4.0
7.8(5)
VIN .. 3.4V
VIN=GND
-
5.2
12.8(5)
Test Condltlons(1)
.6lee
Quiescent Power Supply Current
TTL Inputs HIGH
Vee .. Max.
VIN .. 3.4V(3)
IceD
Dynamic Power Supply Current (4)
Vee = Max., Outputs Open
Load Mode
CEP = CET .. PE - GND
MRorSR ... Vee
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
mAl
MHz
rnA
I
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc ~ 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other Inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT +I,NPUTS + IDYNAMIC
Ic = Icc + ~lccDHNT + ICCD(fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a.TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition ·Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni - Number of Inputs at to
All currents are in milliamps and all frequencies are in megahertz.
6.7
2611 tbl04
4
IDT54174FCT161T/AT/CT,IDT54174FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condltlon(1)
IOT54174FCT161T
IOT54174FCT161AT
IOT54174FCT163T
IOT54174FCT163A T
Com'l.
Com'l.
Mil.
IOT54174FCT161CT
IOT54174FCT163CT
Com'l
Mil.
Mil.
Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.
Unit
2.0
11.0
2.0
11.5
2.0
7.2
2.0
7.5
2.0
5.8
2.0
6.3
ns
2.0
9.5
2.0
10.0
2.0
6.2
2.0
6.5
2.0
5.8
2.0
6.3
ns
Propagation Delay
CPtoTC
2.0
15.0
2.0
16.5
2.0
9.8
2.0
10.8
2.0
7.4
2.0
8.3
ns
tPLH
tPHL
Propagation Delay
CETto TC
1.5
8.5
1.5
9.0
1.5
5.5
1.5
5.9
1.5
5.2
1.5
5.6
ns
tPHL
Propagation Delay
MR to On (,161)
2.0
13.0
2.0
14.0
2.0
8.5
2.0
9.1
2.0
6.0
2.0
6.6
ns
tPHL
Propagation Delay
MR to TC (,161)
2.0
11.5
2.0
12.5
2.0
7.5
2.0
8.2
2.0
7.0
2.0
7.7
ns
Set-up Time,
5.0
-
5.5
-
4.0
......:.
4.5
-
4.0
-
4.5
-
ns
tPLH
tPHL
Propagation Delay
CP to On
(PE Input HIGH)
tPLH
tPHL
Propagation Delay
CPtoOn
tPLH
tPHL
CL= 50pF
RL= 500n
(PE Input LOW)
tsu
HIGH or LOW
Pnto CP
tH
Hold Time,
HIGH or LOW
Pnto CP
1.5
-
2.0
-
1.5
-
2.0
-
1.5
-
2.0
-
ns
tsu
Set-up Time,
HIGH or LOW
PEorSRto CP
Hold Time,
HIGH or LOW
PEorSRto CP
11.5
-
13.5
-
9.5
-
11.5
-
9.5
-
11.5
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
tsu
Set-up Time,
HIGH or LOW
CEP or CET to CP
11.5
-
13.0
-
9.5
-
11.0
-
9.5
-
11.0
-
ns
tH
Hold Time,
HIGH or LOW
CEP or CET to CP
0
-
0
-
0
-
0
-
0
-
0
-
ns
WI
Clock Pulse
Width (Load)
HIGH or LOW
5.0
-
5.0
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
ns
WI
Clock Pulse
Width (Count)
HIGH or LOW
7.0
-
8.0
-
-
7.0
-
6.0
-
7.0
-
ns
tw
MR Pulse Width,
LOW (,161)
5.0
-
5.0
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
ns
tREM
Recovery Time
MR to CP (,161)
6.0
-
6.0
-
5.0
-
5.0
-
5.0
-
5.0
-
ns
tH
NOTES:
6.0 .
2611 tbl07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
6.7
5
t;)®
IDT54/74FCT191T
IDT54/74FCT191AT
FAST CMOS
UP/DOWN BINARY
COUNTER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT191T equivalent to FAST"'M speed
• IDT54174FCT191AT 35% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• True TTL input and output levels
• Substantially lower input current levels than FAST
(5~ max.)
• JEDEC standard pinout for DIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT191T and IDT54/74FCT191AT are
reversible modul0-16 binary counters, featuring synchronous
counting and asynchronous presetting and are built using
advanced CEMOSTM, a dual metal CMOS technology. The
preset feature allows the IDT54174FCT191T and IDT541
74FCT191AT to be used in programmable dividers. The
count enable input, terminal count output and ripple clock
output make possible a variety of methods of implementing
multiusage counters. In the counting modes, state changes
are initiated by the rising edge of the clock.
FUNCTIONAL BLOCK DIAGRAM
CP UID
1 I
y\~
Po
~
(
~
I
Ps
P2
CE
I
I
I
T
II
Jl
,~
Ie
T
l:f
I
1-.
1
J
-< PRESET
1
TC
CL~R
a
%91
I
J CLOCK K
o
RC
r
1
1-.
00
It
I
)
1
J CLOCK K
p-
-<
a
I
CL~R
a
p-
L--
QJ
It)
I
I
1-.
1
J CLOCK K
?
1
?
02
01
~
Ie
1
a
I
I
.1
1
I
I
A
CL~R
a
p-
L--
1°
J CLOCK K
-< PRESET
-< PRESET
PRESET
L--
?
T
a
1
CL~R
a
p-
L--
?as
2615 drw01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tilt992 Integrated Device Technology. Inc.
6.8
MAY 1992
DSC·4207J2
1
IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
UfO
02
03
GND
r
~
I I
I I
3
gIi:
L-J L-J
,
20 19
4
18
1
5
17
L20-2 16
6
7
15
8
14
9 10 11 12 13
II"""'''' ,....., r-1
00 ]
CE ]
NC ]
UfO ]
02 ]
8
DIPfCERPACKISOIC
TOP VIEW
2
w
[ CP
[ RC
[ NC
[ TC
[ PL
~
2615 drw 02
00M
'"
~za...a...
LCC
TOP VIEW
RC FUNCTION TABLE(2)
PIN DESCRIPTION
Pin Names
c..
L-J L-J
c5
INDEX
Vee
Po
CP
RC
TC
PL
P2
P3
P1
01
00
CE
Description
CE
Count Enable Input (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
Inputs
outputs
CE
CP
TC(1)
RC
L
-U-
H
LJ
PO-3
Parallel Data Inputs
H
X
X
H
PL
Asynchronous Parallel Load Input (Active LOW)
X
X
L
H
UfO
UpfDown Count Control Input
QO-3
Flip-Flop Outputs
RC
Ripple Clock Output (Active LOW)
TC
Terminal Count Output (Active HIGH)
26t5 tbl 06
MODE SELECT FUNCTION TABLE(2)
Inputs
2615 tbl 05
PL
CE
UfD
CP
H
L
L
H
L
H
i
i
Mode
L
X
X
X
Preset (Asynchronous)
H
H
X
X
No Change (Hold)
Count Up
Count Down
NOTES:
2615 tbl 07
1. TC is generated internally.
2. H = HIGH Voltage Level, L= LOW Voltage Level, X = Don't Care, t = LOWto-HIGH clock transition.
6.8
2
IDT54174FCT191 TIAT
FAST CMOS UPIDOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Operating
Temperature
o to +70
-55 to +125
°C
TelAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
Conditions Typ.
CIN.
Input Capacitance
VIN = OV
COUT
Output Capacitance VOUT = OV
Max.
Unit
6
10
pF
8
12
pF
NOTE:
2615 tbl 02
1. This parameter is guaranteed at characterization but not tested.
with Respect
to GND
TA
(TA= +25°C, f = 1.0MHz)
Parameter(1)
Symbol
NOTES:
2615 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speCification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals.
3. Outputs and 1/0 terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V
Symbol
VIH
Test Conditlons(1)
Parameter
Input HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
IlL
Input LOW Current
Vee
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee = Max.(3), Vo = GND
VOH
Output HIGH Voltage
Vee= Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power
Supply Current
I COM'L(4)
I MIL
Guaranteed Logic HIGH Level
Vee = Max.
VIN = GND or Vee
Max.
Unit
-
-
V
V
-
-
-
0.8
V
5
J.IA
J.IA
J.IA
-
-5
-D.7
-1.2
V
-60
-120
-225
rnA
IOH = -6mA MIL.
10H = -SmA COM'L.
2.4
3.3
-
V
10H = -12mA MIL.
IOH = -15mA COM'L.
2.0
3.0
-
V
IOL= 32mA MIL.
10L= 48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
rnA
VI
Vee= Min.
VIN = VIH or VIL
Typ.(2)
2.0V
2.7V
-
VI =2.7V
= Max.
± 10%
Min.
= 0.5V
20
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Clock pin requires a minimum VIH of 2.5V.
6.8
2615 tbl 03
3
IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
~Iee
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
IceD
Dynamic Power Supply Current(4)
Symbol
Ie
Total Power Supply Current(6)
Test Condltlons(1)
Min.
Vee = Max.
VIN = 3.4V(3)
Typ.(2)
-
0.5
Max.
2.0
0.15
0.25
Vee = Max., Outputs Open
Preset Mode
PL = CE = UJD = CP = GND
One Bit Toggling
50% Duty Cycle
VIN
VIN
= Vee
= GND
-
Vee = Max., Outputs Open
Preset Mode
PL = CE = UfO = CP = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN = Vee
VIN = GND
-
1.0
2.8
VIN = 3.4V
VIN = GND
-
1.2
3.8
Vee = Max., Outputs Open
Preset Mode
PL = CE = UfO = CP = GND
Four Bits Toggling
atfi = 5MHz
50% Duty Cycle
VIN
VIN
= Vee
= GND
-
3.2
6.5(5)
VIN
VIN
=3.4V
= GND
-
4.2
10.5(5)
~
rnN
MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + AlccDHNT + ICCD(fcp/2 + fiNi)
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.8
Unit
rnA
2615tbl04
4
IDT54174FCT191T/AT
FAST CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT191T
Com'l.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
CPto On
tPLH
tPHL
Conditlon(1)
CL= 50pF
RL= 500n
Min,(2) Max.
IDT54174FCT191AT
Com'l.
Mil.
Min.(2) Max.
Min.(2)
Mil.
Max. Min.<2) Max.
Unit
2.5
12.0
1.5
16.0
2.5
7.8
1.5
10.5
ns
Propagation Delay
CPtoTC
3.0
14.0
2.0
16.0
3.0
11.8
2.0
12.2
ns
tPLH
tPHL
Propagation Delay
CP to RC
2.5
8.5
1.5
12.5
2.5
8.5
1.5
10.0
ns
tPLH
tPHL
Propagation Delay
CEto RC
2.0
8.0
2.0
8.5
2.0
7.2
2.0
8.0
ns
tPLH
tPHL
~ropagation
Delay
4.0
20.0
4.0
22.5
4.0
13.0
4.0
14.7
ns
tPLH
tPHL
Propagation Delay
UfO to TC
3.0
11.0
3.0
13.0
3.0
7.2
3.0
8.5
ns
tPLH
tPHL
Propagation Delay
Pn to On
2.0
14.0
1.5
16.0
2.0
9.1
1.5
10.4
ns
tPLH
tPHL
Propagation Delay
PL to On
3.0
13.0
3.0
14.0
3.0
8.5
3.0
9.1
ns
tsu
Set-up Time, HIGH or LOW
Pn to PL
5.0
-
6.0
-
4.0
-
5.0
-
ns
tH
Hold Time, HIGH or LOW
Pn to PL
1.5
-
1.5
-
1.5
-
1.5
-
ns
tsu
Set-up Time LOW
CE to CP
10.0
-
10.5
-
9.0
-
9.5
-
ns
tH
Hold Time LOW
CE toCP
0
-
0
-
0
-
0
-
ns
tsu
§.et-up Time, HIGH or LOW
UfO to CP
12.0
-
12.0
-
10:0
-
10.0
-
ns
tH
Hold Time, HIGH or LOW
UJD to CP
0
-
0
-
0
-
0
-
ns
UfO to RC
tw
PL Pulse Width LOW
6.0
-
8.5
5.0
-
7.0
5.5
4.0(3)
-
6.0
-
ns
Clock Pulse Width HIGH or LOW
-
8.0
tw
tREM
Recovery Time PL to CP
6.0
-
7.5
-
5.0
-
6.5
-
ns
NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
ns
2615tbl08
6.8
5
IDT54174FCT191T/AT
FAST CMOS UPIDOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORMS
Typical load, count and inhibit sequences
Illustrated below is the following sequence:
Load (preset) to binary thirteen .
.
Count up to fourteen, fifteen (maximum), zero; one and
two
'Inhibit
Count down to one, zero (minimum), fifteen, fourteen
and thirteen
PL
~
I I
-.J
I
Po
:
I..... ...:-
I'Ir-
PI
DATA
INPUTS
P2
P3 '
I
I
I
--.J
--.J
I
I_
'I
II....._
I
L
I
I
----:
CP
um
CE
--,
--,
-II
II
II
II
I
II
II
II
I I
II
II
I
---I
Qo
DATA
OUTPUTS
01
I
I
II
__ ...J
--u--I
02
...;.._...J
03
_~J
TC
---,
RC
---
I
n
I
I
----I
I
13
I
14
~
U
15
____ ____ ____
0
~
2
~
2
2
I
I
1
~n~
0
u
________
15
14
13
1 1j.--cOUNT UPI-'----.·*"I·....INHIBIT--I 1..-COUNT DOWN---4
'--y-/
LOAD
2615 drw 05
6.8
6
t;)®
FAST CMOS
UP/DOWN
BINARY COUNTERS
Integrated Device Technology, Inc.
IDT54/74FCT193T
IDT54/74FCT193AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT193T equivalent to FASlTM speed
• IDT54n4FCT193AT 35% faster than FAST
The IDT54/74FCT193T and IDT54/74FCT193AT are upl
down modul0-16 binary counters built using advanced
CEMOSTM, a dual metal CMOS technology. Separate countup and count-down clocks are used and, in either counting
mode, the circuits operate synchronously. The outputs change
state synchronously with the LOW-to-H IGH transitions on the
clock inputs. Separate terminal count-up and terminal countdown outputs are provided that are used as the clocks for
subsequent stages without extra logic, thus simplifying
multistage counter designs. Individual preset inputs allow the
circuit to be used as a programmable counter. Both the
Parallel Load (PL) and the Master Reset. (MR) inputs
.
asynchronously override the clocks.
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST
(5~max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
P1
Po
--
~
~
~
00
[tI
I
v
I
I
K
CD
a
y
0
I
I
J
T
CP
So
a
[tI
I
I
~
l>-
V
CP
CD
a
~
?
~
?
I
I
J
T
K
02
So
D-
a
~
y
i
~
I
I
K
J
CP
CD
a
?
So
a
p-
~
+
03
2628 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1992 Integrated Device Technology. Inc.
6.9
MAY 1992
DSC-4211!12
1
IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
a a:: ~ ~ &
INDEX
L....JL-JIIL-JL....J
P1
01
00
CPO
CPU
02
03
GND
3
Qo ] 4
CPo ] 5
NC ] 6
CPu ] 7
Q2 ] 8
Vcc
Po
MR
TCo
TCu
PL
P2
P3
L20-2
17 [
16 [
15 [
14 [
MR
TCo
NC
TCu
PL
~~~~;;
2628 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
FUNCTION TABLE(1)
DEFINITION OF FUNCTIONAL TERMS
MR
PL
CPu
CPo
Mode
Count Up Clock Input (Active Rising Edge)
H
X
X
X
Reset (Asyn.)
Preset (Asyn.)
Description
Pin Names
CPu
2 I I 20 19
~
18 [
CPo
Count Down Clock Input (Active Rising Edge)
L
L
X
X
MR
Asynchronous Master Reset (Active HIGH)
L
H
H
H
No Change
PL
Asynchronous Parallel Load Input (Active LOW)
L
H
i
H
Count Up
L
H
H
i
Count Down
Pn
Parallel Data Inputs
Qn
Flip-flop Outputs
TCo
Terminal Count Down (Borrow) Output (Active
LOW)
TCu
Terminal Count Up (Carry) Output (Active LOW)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
i = LOW-to-HIGH Clock Transition.
2628 tbl 06
2628 tbl 05
CAPACITANCE (TA = +25°C , f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Rating
Symbol
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
Commercial
Military
Unit
-0.5 to +7.0 -0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
oto +70
-55 to +125
°C
Symbol
CIN
COUT
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions Typ.
VIN = OV
6
VOUT= OV
8
Max.
10
Unit
pF
12
pF
NOTE:
2628 tbl 02
1. This parameter is measured at characterization but not tested.
NOTES:
2628 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vce by +O.5V unless otherwise noted.
2. Input and Vcc terminals.
3. Output and 110 terminals.
6.9
2
IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE'
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V +10°/;
Typ.(2)
Test Condltlons(1)
Symbol
Parameter
Min.
COM'L(4)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0V
2.7V
I MIL
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
I
Max.
-
Unit
V
V
0.8
V
-
5
~
-
-5
IlA
20
J.tA
-{J.7
-1.2
V
-225
mA
ilL
Input LOW Current
Vee = Max.
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
los
Short Circuit Current
. Vee = MaxP), Vo = GND
-60
-120
VOH
Output HIGH Voltage
10H =-6mA MIL.
10H = -8mA COM'L.
2.4
3.3
-
V
10H =-12mA MIL.
10H = -15mA COM'L.
2.0
3.0
-
V
IOL= 32mA MIL.
lei= 48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
0.2
1.5
mA
IIH
Input HIGH Current
Vee= Max.
VI = 2.7V
VI
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power
Supply Current
Vee= Min.
VIN = VIH or VIL
Vee = Min.
VIN = VIH or VIL
Vee = Max.
VIN = GND or Vee
=O.5V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
,
4. Clock pin requires a minimum VIH of 2 . 5 V . ·
6.9
2628 tbl03
3
IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
dice
IceD
Ie
Test Condltlons(1)
Parameter
Quiescent Power Supply
Current TIL Inputs HIGH
Dynamic Power
Supply Current(4)
Total Power Supply
Current(6)
Typ.(2)
Max.
Unit
-
0.5
2.0
rnA
Min.
Vee = Max.
VIN = 3.4v(3)
Vee= Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo = GND
One Bit Toggling
50% Duty Cycle
VIN = Vee
VIN = GND
-
0.15
0.25
mAl
MHz
Vee = Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo
One Bit Toggling
at fi = 10MHz
50% Duty Cycle
VIN = Vee
VIN = GND
-
1.7
4.0
rnA
= 3.4V
= GND
-
2.0
5.0
VIN = Vee
VIN = GND
-
3.2
6.5(5)
VIN = 3.4V
VIN= GND
-
4.2
10.5(5)
Vee = Max.
Outputs Open
Preset Mode
PL = MR = CPu = CPo
Four Bits Toggling
at fi = 5MHz
50% Duty_ C~cle
= GND
VIN
VIN
= GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but Is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + liN PUTS + IDYNAMIC
Ic = Icc + £\Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
£\Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.9
2628tbl04
4
IDT54174FCT193T/AT
FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT193T
Com'l.
Symbol
Parameter
tPLH
tPHL
Propagation De~
CPu or CPo to TCu or TCo
tPLH
tPHL
Conditlon(1)
CL= 50pF
RL= 500n
Mln.(2) Max.
IDT54n4FCT193AT
Mil.
Com'l.
Mln.(2) Max.
Mln.(2) Max.
Mil.
Min.(2) Max.
Unit
2.0
10.0
2.0
10.5
2.0
6.5
2.0
6.9
ns
Propagation Delay
CPu or CPo to an
2.0
13.5
2.0
14.0
2.0
8.8
2.0
9.1
ns
tPLH
tPHL
Propagation Delay
Pn to an
2.0
15.5
2.0
16.5
2.0
10.1
2.0
10.8
ns
tPLH
tPHL
Propagation Delay
PL to an
2.0
14.0
2.0
13.5
2.0
8.8
2.0
9.1
ns
tPHL
Propagation Delay
MR to an
3.0
15.5
3.0
16.0
3.0
10.1
3.0
10.4
ns
tPLH
Propagation Delay
MRtoTCu
3.0
14.5
3.0
15.0
3.0
9.4
3.0
9.8
ns
tPHL
Propagation Delay
MRtoTCo
3.0
15.5
3.0
16.0
3.0
10.1
3.0
10.4
ns
tPLH
tPHL
Propagation Delay
PL to TCu or TCo
3.0
16.5
3.0
18.5
3.0
10.8
3.0
12.0
ns
tPLH
tPHL
Propa~tion Delay
Pn to TCu or TCo
3.0
15.5
3.0
16.5
3.0
10.1
3.0
10.8
ns
tsu
Set-up Time, HIGH or LOW
Pn to PL
5.0
-
6.0
-
4.0
-
5.0
-
ns
tH
Hold Time, HIGH or LOW
Pn to PL
2.0
-
2.0
-
1.5
-
1.5
-
ns
5.0
4.0(3)
-
6.5
-
ns
6.0
tw
PL Pulse Width LOW
6.0
-
CPu or CPo Pulse Width
5.0
-
7.5
tw
7.0
-
tw
HIGH or LOW
CPu or CPo Pulse Width LOW
(Change of Direction)
10.0
-
12.0
-
8.0
-
10.0
-
ns
tw
MR Pulse Width HIGH
6.0
5.0
7.0
-
ns
8.0
-
5.0
6.0
-
5.0
Recovery Time
PL to CPu or CPo
-
6.0
tREM
tREM
Recovery Time
MR to CPu or CPo
4.0
-
4.5
-
3.0
-
3.5
-
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
ns
ns
2628 tbl 07
6.9
5
IDT54n4FCT193T/AT
FAST CMOS UP/DOWNBINARV COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORMS
Typical clear, load and count sequences
Illustrated below is the following sequence:
• Clear outputs to zero. .
• Load (preset) to binary thirteen.
• Count up to fourteen, fifteen, carry zero, one and two.
• Count down to one, zero, borrow, fifteen, fourteen and
thirteen.
MR(2)~
1
J5[
1
I'
U
1
1
;-------,1 - - - -
~
Po
-
-
-
--
'---------
1
1
DATA
INPUTS
~----------
P1
_ _ _ _ _-----11, _ _ _ ....:..... ---:' _ _ _ _
P2
~
1
P3
~
1
.----------,1'---- - - -
-
-
'- ____.___ _
--.:...._
--
1---------
L-:.-.. _ _ _ _ _ _ _ _ _ _
'1' 1
CPU(l)
CPD(l)----------------------,
1
1
1
1
1
1
Qo
=~L--.:...
1
- DATA
OUTPUTS
Q1
1
_~
1
1
1
I~
________
~
Q2 __ ~
1,I
~
1
1.....-_ _......11
_ _I_:...I_--:"'-J
L--_ _ _ _~_...:.__ _ _ ____.:
. 1
1
..--_
_ _ _ _ __ _
Q3 . =~
1
1
TCU
U
1,:1
1 1
TCD
SEQUENCE
ILLUSTRATED
1
··1
1
1
1
10 1
13
1 1
~~
114150~
..-COUNTUP
.,
U
'
1
~ COUNTDOWN
0 15 '~
2628 drw 04
NOTES:
1. MR overrrides load, data, and count Inputs.
2. When counting up, CPO input must be HIGH; when counting down,
CPU input must be HIGH.
6.9
6
~
I DT54/74 FCT240TIAT/CT/DT
IDT54/74FCT241T/AT/CT/DT
I DT54/74 FCT244T/AT/CT/DT
I DT54/74 FCT540T/AT/CT
IDT54/74FCT541T/AT/CT
FAST CMOS OCTAL
BUFFER/LINE DRIVERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Fastest CMOS logic family available
• Std., A, C, and D speed grades with 3.6ns tPD
• Available in DIP, SOIC, SSOP, CERPACK and LCC
packages
• True TIL input and output compatible
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1 mW typo static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
The IDT octal buffer/line drivers are built using advanced
CEMOSTM, a dual metal CMOS technology. The IDT541
74FCT240T/AT/CT/DT, IDT54/74FCT241T/AT/CT/DT and
IDT54/74FCT244T/AT/CT/DT are designed to be employed
as memory and address drivers. clock drivers and busoriented transmitter/receivers which provide improved board
density.
The IDT54174FCT540T/AT/CT and IDT54174FCT541TI
AT/CT are similar in function to the IDT54/74FCT240T/ATI
CT/DT and IDT54174FCT244T/AT/CT/OT. respectively, except that the inputs and outputs are on opposite sides of the
package. This pinout arrangement makes these devices
especially useful as output ports for microprocessors and as
backplane drivers, allowing ease of layout and greater board
density.
FUNCTIONAL BLOCK DIAGRAMS
OEA----q
241 Only
.---,
OEA - - - - q
p-+--OEs
I
I
OEA - - - - - , , - - - - OEs
OEs *
OAo
DAo
OAo
Do
-:>0--+---- 00*
OBo
DBa
O~
D~
Dl
;>0--+---- 01*
DAl
OAl
DAl
OAl
D2
;>0--+---- 02*
OBl
DBl
OBl
DBl
D3
-:>0--+---- 03*
"">---1--- OA2
D4
"":>0--004---- 04*
D~
Ds
;>0--+---- 05*
0A3
D6
;>0--+---- 06*
D~
D7
;:.0.-+---- 07*
DAo
- - + - i ~-+---
DA2
OA2
DA2
OB2
DB2
O~
DA3
OA3
DA3
OB3
DB3
O~
IDT54174FCT240T
- - + - I ">---1---
--+--I
--+-I ">-----
IDT54174FCT241 T/244T
*OEs for 241T, OEs for244T
2565 cnv' 01
2565 cnv' 02
IDT54174FCT540T/541T
*Logic diagram shown for 'FCT540T.
'FCT541 T is the non-inverting option.
2565 cnv' 03
CEMOS is a lrademark 01 Integrated Device Technology. Inc.
FAST is a trademark 01 National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0
a,...
II
II
I
I~~
L..! 20 19
01
01
:]4
:] 5
1
18[: 07
17[: 06
02
02
:] 6
:] 7
L20-2
03
:]8
16[: 06
15[: Os
14[ Os
9 10 11 12 13
....,....,....,...., 1'"""1
I II II II I I I
8~~OQ
LE
CJ
2564 cov·03
IDT54174FCT573T
2564 cov·04
LCC
TOP VIEW
DIP/SOIC/SSOP/CERPACK
TOP VIEW
INDEX
o
Vee
OE
II
3 2
06
02
II
L-IL-II
06
o
a IW0
oo
o
81~
g 8
LJ LJ: I L..! L..!
Do
01
00
01
02
02
02
03
04
05
03
04
Os
03 ]5
04 :] 6
06
06
07
07
GNO
LE
3 2
05
L..! 20 19
1
18[: 01
17[ 02
L20-2
16 [: 03
15[: 04
14[: 05
:] 4
:] 7
06 :] 8
9 10 11 12 13
11 11 1111 11
I
II
II
o~
II
~
II
I
0 0
CJ
2564 cov·05
2564 cnv·06
LCC
TOP VIEW
DIP/SOIC/SSOP/CERPACK
TOP VIEW
IDT54174FCT533T
00
2
Do
01
01
3
18
4
5
6
P20-1 17
020-1 16
S020-2 15
02
02
03
03
GNO
INDEX
Vee
OE
&
7
8
9
10
E20-1
14
13
12
11
'(51
07
06
01
56
01
I I I II
L-IL-II
3 2
Os
Os
04
II
II
I
I~~
18[: 07
1
17[: 06
L20-2
16[:
06
15[: 05
14[ 05
:] 7
03 ]8
54
LE
gp
L..! 20 19
:] 4
:1 5
02 :16
02
o
8 K3 I~
9 10 11 12 13
r-"I r-'I r-"I r-"I
I
2564 cnv·07
II
II
II
18~ ~
r--.
II
I
p 0
2564 cnv·08
CJ
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
6.14
2
IDT54174FCT373T/AT/CT/DT, 533T/AT/CT, 573T/AT/CTIDT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (FCT533)(1)
ON
Inputs
LE
OE
H
H
L
H
X
X
FUNCTION TABLE (FCT373 and FCT573)(1)
Outputs
ON
ON
Inputs
LE
OE
Outputs
ON
L
L
H
H
L
H
L
H
L
H
L
L
H
Z
X
X
H
Z
NOTE:
1. H = HIGH Voltage Level
2564 tbl 05
NOTE:
1. H = HIGH Voltage Level
2564tb106
L = LOW Voltage Level
X a Don't Care
Z = High Impedance
L = LOW Voltage Level
X = Don't Care
Z a High Impedance
DEFINITION OF FUNCTIONAL TERMS
Description
Pin Names
DN
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
ON
3-State Outputs
ON
Complementary 3-State Outputs
2564tbll 07
6.14
3
IDT54n4FCT373T/AT/CT/DT, 533T/AT/CT, 573T/AT/CT/DT
FAST CMOS OCTAL TRANSPARENT LATCHES .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1}
Svmbol
Ratln~
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
mA
(TA
= +25°C,f = 1.0MHz)
Parameter(l)
Symbol
Conditions
Tvp.
Max.
Unit
CIN
Input
CapaCitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
2564 tbl 02
NOTES:
2564 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE'
Following Conditions Apply Unless Otherwise Specified:
Commercial· TA = O°C to +70°C Vcc = 5 OV+
- 5%', Military' TA = -55°C to +125°C, VCC ~5 OV -+ 10%
Symbol
Test Condltlons(l)
Parameter
Min.' Typ.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logie LOW Level
-
IIH
Input HIGH Current
Vee = Max.
VI = 2.7V
II L
Input LOW Current
Vee = Max.
VI = 0.5V
-
10ZH
High Impedance Output Current
Vee = Max.
Vo=2.7V
VA = 0.5V
10ZL
V
-225
mA
10H = -6mA MIL.
10H = -8mA COM'L.
2.4
3.3
-
V
10H = -12mA MIL.
10H = -15mA COM'L.
2.0
3.0
-
V
IOL = 32mA MIL.
IOL = 48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
mA
Vee = Max.(3), Vo= GND
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
Input HystereSis
Vee = Max.
VIN = GND or Vee
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.14
10
-120
Short Circuit Current
Quiescent Power Supply Current
!-tA
!-tA
!-tA
-60
los
Icc
V
5
20
Vee = Min., IN = -18mA
VH
-10
V
0.8
-1.2
Vee = Max., VI = Vee (Max.)
Vee = Min.
VIN = VIH or VIL
. -5
-
Unit
-
Input HIGH Current
Clamp Diode Voltage
Output LOW Voltage
-
-{J.7
II
VIK
VOL
-
Max.
-
!-tA
2564 tbl 03
4
IDT54174FCT373T/AT/CT/DT, 533T/AT/CT, 573T/AT/CT/DT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Svmbol
dice
IceD
Tvp.(2)
Max.
Unit
-
0.5
2.0
rnA
VIN = Vee
VIN = GND
-
0.15
0.25
Vee = Max.
Outputs Open
fi = 10MHz
VIN = Vee
VIN = GND
-
1.7
4.0
50% Duty Cycle
OE=GND
VIN = 3.4V
VIN = GND
-
2.0
5.0
VIN = Vee
VIN = GND
-
3.2
6.5(5)
VIN = 3.4V
VIN = GND
-
5.2
14.5(5)
Test Condltlons(1)
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN "" 3.4V(3)
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
OE= GND
Min.
mAl
MHz
One Input Toggling
50% Dut~Cycle
Ie
Total Power Supply Current(S)
rnA
LE = Vee
One Bit TOQQlinQ
Vee = Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
OE= GND
LE '" Vee
Eiqht Bits Toqqlinq
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = laulEscENT + IINPUTS + IDYNAMIC
Ie '" Icc + alcc DHNT + leeD (fcp/2 + fiNi)
lec '" Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
lecD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.14
2564 Ibl 04
5
IDT54n4FCT373T/AT/CT/DT, 533T/AT/CT, 573T/AT/CT/DT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR
FCT373T AND FCT573T' .
..
'
FCT373T/573T
Com'l.
'Svmbol
Parameter
tPLH
tPHL
Propagation Delay
ON to ON
tPLH
tPHL
Propagation Delay
LE to ON
tPZH
tPZL
Output Enable Time
tPHZ
tPLZ
Output Disable Time
tsu
Set-up Time HIGH
or LOW ON to LE
tH
Hold Time HIGH
or LOW. ON to LE
LE Pulse Width
HIGH
tw
Condltlons(1)
CL = 50pF
FCT373AT/573AT
Mil.
Com'l.
Mil.
Mln.!2)
Max.
Mln.l2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Unit
1.5
8.0
1.5
8.5
1.5
5.2
,1.5
5.6
ns
2.0
13.0
2.0
15.0
2.0
8.5
2.0
9.8
ns
1.5
,12.0
1.5
13.5
1.5
6.5
1.5
7.5
ns
1.5
' 7.5
1.5,
10.0
1.5
5.5
1.5,
6.5
ns
2.0
-
2.0
-
2.0
-
2.0,
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
ns
6.0
-
6.0
-
5.0
-
6.0
-
RL= 500n
ns
2564 tbl 08
FCT373CT/573CT
Com'l.
Svmbol
Parameter
tPLH
tPHL
Propagation Delay
ONto ON
tPLH
tPHL
Propagation Delay
LE to ON
Output Enable Time
tPZH
tPZL
tPHZ
tPLZ
Output Disable Time
tsu
Set-up Time HIGH
or LOW ON to LE
tH
Hold Time HIGH
or LOW. ON to LE
LE Pulse Width
HIGH(3)
tw
Conditlons(1)
CL = 50pF
FCT373DT/573DT
Mil.
Com'l.
Mil.
Mln.!2)
MlnP)
Max.
MlnP)
Max.
MlnP)
Max.
1.5
4.2
1.5
5.1
1.5
3.8
-
-
ns
2.0
5.5
2.0
8.0
2.0
4.0
-
-
ns
1.5
5.5
1.5
6.3
1.5
4.8
-
-
ns
1.5
5.0
1.5
5.9
1.5
4.0
-
-
ns
2.0
-
2.0
-
1.5
-
-
-
ns
1.5
-
1.5
-
1.0
-
-
-
ns
5.0
-
6.0
-
3.0
-
-
-
RL= 500n
NOTES:
Max.
Unit
ns
2564 tbl 09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
6.14
6
IDTS4174FCT373T/AT/CT/DT, S33T/AT/CT, 573T/AT/CT/DT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533T
FCT533T
Com'l.
Symbol
Parameter
Condltlons(1)
tPLH
tPHL
Propa~tion Delay
CL = 50pF
ON to ON
RL= 500n
tPLH
tPHL
Propallation Delay
LE to ON
tPZH
tPZL
Output Enable
Time
Output Disable
Time
Set-up Time HIGH
or LOW ON to LE
tPHZ
tPLZ
tsu
FCTS33AT
Mil.
Com'l.
FCT533CT
Mil.
Com'l.
Mil.
Min,(2) Max. Mln.(2) Max. Mln.l2) Max. Min,(2) Max. Mln.l2) Max. MlnJ2) Max. Unit
1.5
10.0
1.5
12.0
1.5
5.2
1.5
5.6
1.5
4.2
1.5
5.1
ns
2.0
13.0
2.0
14.0
2.0
8.5
2.0
9.8
2.0
5.5
2.0
8.0
ns
1.5
11.0
1.5
12.5
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5
7.0
1.5
8.5
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
ns
tH
Hold Time HIGH
or LOW, ON to LE
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
toN
LE Pulse Width
HIGH
6.0
-
6.0
-
5.0
-
6.0
-
5.0
-
6.0
-
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
ns
2564tbll0
6.14
7
~
FAST CMOS OCTAL D
REGISTERS (3-STATE)
IDT54/74FCT374TI AT/CT/DT
I DT54/74 FCT534TIAT/CT
I DT54/74 FCT574T/AT/CT/DT
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• Fastest CMOS logic family available
• Std., A, C, and D speed grades with 4.2ns tPD
• Available in DIP, SOIC, SSOP, CERPACK and LCC
packages
• True TTL input and output compatibility
- VOH = 3.3V (typ.)
- VOL = O.3V (typ.)
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common threestate control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
The IDT54174FCT374T/AT/CT/DT, IDT54/74FCT534T/ATI
CT and IDT54/74FCT574T/AT/CT/DTare a-bit registers built
using advanced CEMOSTM, a dual metal CMOS technology.
These registers consist of eight D-type flip-flops with a buffered common clock and buffered 3-state output control. When
the output enablEUQE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the highimpedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the 0 outputs on the LOW-toHIGH transition of the clock input.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374T AND IDT54/74FCT574T
2569 drw 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534T
2569 drw 02
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0
07
07
I II II
.....,....., I
3
:l4
:1 5
]8
2
II II I
11.....11.....1
LJ
1
20 19
18 [:
17 [:
D7
06
16 [:
06
15 [:
Os
14 [:
9 10 11 12 13
Os
L20-2
2569 drw 05
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
6.15
2
IDT54174FCT374T/AT/CT/DT, 534T/AT/CT, 574T/AT/CT/DT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
Description
ON
o flip-flop data inputs
CP
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
ON
3-state outputs, (true)
ON
3-state outputs, (inverted)
OE
Active LOW 3-state Output Enable input
2569 tbl 06
FUNCTION TABLE(1)
FCT534
Inputs
FCT374/574
outputs
Internal
Outputs
Internal
OE
CP
ON
ON
QN
ON
QN
HI-Z
H
H
L
H
X
X
Z
Z
NC
NC
Z
Z
NC
NC
LOAD REGISTER
L
L
H
H
l'
l'
l'
l'
L
H
L
H
H
L
L
H
L
H
L
H
H
Function
Z
Z
L
H
L
Z
Z
NOTE:
2569tbl05
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change
l' = LOW-to-HIGH transition
ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
Ratlna
VTERM(2) Terminal Voltage
with Respect to
GNO
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Mllltarv
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
= +25°C, f = 1.0MHz)
Unit
VIN = OV
TyP.
6
Max.
Input
Capacitance
Conditions
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
TA
Operating
Temperature
oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
~5 to +135
°C
TSTG
Storage
Temperature
-55 to +125
~5 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
OCOutput
Current
120
120
mA
NOTES:
(TA
Parameter(1)
CIN
Svmbol
2569 tbl 02
1. This parameter is measured at characterization but not tested.
2569 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
6.15
3
II
IDT54n4FCT374T/AT/CT/DT, 534T/AT/CT, 574T/AT/CT/DT
FAST CMOS OCTAL 0 REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military: TA =;".55°C to +125°C, Vee = 5.0V± 10%
Min.
TVp.(2)
Guaranteed Logic HIGH Level
2.0
-
-
Input LOW Level
Guaranteed Logic LOW Level
O.B
V
Vee = Max.
I1A
Input LOW Current
Vee = Max.
VI = 0.5V
10ZH
High Impedance Output Current
Vee = Max.
Vo= 2.7V
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
-
5
III
VIK
Clamp Diode Voltage
Vee = Min., IN = -1BmA
-
-
Input HIGH Current
los
Short Circuit Current
Vee = Max.(3), VO= GND
VOH
Output HIGH Voltage
Vec = Min.
VIN = VIH or Vil
Svmbol
Test Condltlons(1)
Parameter
VIH
Input HIGH Level
Vil
IIH
VI = 2.7V
Vo = 0.5V
10Zl
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power Supply CUrrent
Vee = Min.
VIN = VIH or Vil
Max.
Unit
V
-5
I1A
10
I1A
-10
20
I1A
-0.7
-1.2
V
-so
-120
-225
mA
10H = -SmA MIL.
10H = -BmA COM'L.
2.4
3.3
-
V
10H= -12mA MIL.
10H = -15ri1A COM'L.
2.0
3.0
-
V
10l = 32m A MIL.
10l ;., 4BmA COM'L.
-
0.3
0.5
V
-
200
-
mV
0.2
1.5
mA
Vee = Max., VIN = GND or Vee
NOTES:
"2569 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.15
4
IDT54174FCT374T/AT/CT/DT, 534T/AT/CT, 574T/AT/CT/DT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPL V CHARACTERISTICS
Svmbol
~Iee
leeD
Ie
Test Condltlons(1)
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current(6)
Vee = Max.
VIN = 3.4V(3)
TVD.(2)
Max.
Unit
-
0.5
2.0
mA
Min.
Vee = Max.
Outputs Open
OE= GND
One Input Toggling
50% Duty Cycle
VIN = Vee
VIN = GND
-
0.15
0.25
mAl
MHz
Vee = Max.
Outputs Open
fep = 10MHz
50% Duty Cycle
OE=GND
VIN = Vee
VIN = GND
-
1.7
4.0
mA
VIN = 3.4V
VIN = GND
-
2.2
6.0
VIN = Vee
VIN = GND
-
4.0
7.8(5)
VIN = 3.4V
VIN = GND
-
6.2
16.8(5)
fi = 5MHz
50% Duty Cycle
One Bit Toaalina
Vee = Max.
Outputs Open
fep = 10MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
fi =2.5MHz
50% Duty Cycle
NOTES:
1.
2.
3.
4.
5.
6.'
2569tbl04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.15
5
IDT54n4FCT374T/AT/CT/DT, 534T/AT/CT, 574T/AT/CT/DT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT374T/534T/574T
Com'l.
Mil.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
CP to ON(3)
tpzH
tPZL
Output Enable Time
tPHZ
tPLZ
tsu
Output Disable Time
tH
tw
Condltlons(1)
CL = 50pF
FCT374AT/534AT/574AT
Mil.
Com'l.
MlnJ2)
Max.
Mln.l2)
Max.
Mln.(2)
Max.
MinJ2)
Max.
Unit
2.0
10.0
2.0
11.0
2.0
6.5
2.0
7.2
ns
1.5
12.5
1.5
14.0
1.5
6.5
1.5
7.5
ns
1.5
8.0
1.5
8.0
1.5
5.5
1.5
6.5
ns
2.0
-
2.0
-
2.0
-
2.0
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
ns
7.0
-
7.0
-
5.0
-
6.0
-
RL= 50 on
Set-up Time HIGH
or LOW DN to CP
Hold Time HIGH
or LOW DN to CP
CP Pulse Width
HIGH or LOW
ns
2569 tbl 07
FCT374DT/574DT
FCT374CT/534CT/574CT
Mil.
Com'l.
Symbol
Parameter
Condltlons(1)
CL = 50pF
Min.<2)
Max.
Mln.<2)
Max.
Min.(2)
Max.
2.0
5.2
2.0
6.2
2.0
4.2
1.5
5.5
1.5
6.2
1.5
1.5
5.0
1.5
5.7
tPLH
tPHL
Propagation Delay
CP to ON(3)
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
tsu
Set-up Time HIGH
or LOW DN to CP
2.0
-
2.0
tH
Hold Time HIGH
or LOW DN to CP
1.5
-
tw
CP Pulse Width
HIGH or LOW(4)
5.0
-
NOTES:
Min.<2)
Max.
Unit
-
-
ns
4.8
-
-
ns
1.5
4.0
-
-
ns
-
2.0
-
-
-
ns
1.5
-
1.0
-
-
-
ns
6.0
-
3.0
-
-
-
RL= 500n
Output Disable Time
Mil.
Com'l.
ns
2569tbl08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. ON for FCT374 and FCT574, ON for FCT534.
4. This parameter is guaranteed but not tested.
6.15
6
~®
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
Integrated Device Technology, Inc.
IDT54/74FCT377T
I DT54/74FCT377AT
IDT54/74FCT377CT
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54/74FCT377T/AT/CT are octal D flip-flops built
using advanced CEMOSTM, a dual metal CMOS technology.
The IDT54174FCT377T/AT/CT have eight edge-triggered, Doutputs. The
type flip-flops with individual D inputs and
common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is
fully edge-triggered. The state of each D input, one set-up
time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop's output. The CE input must
be stable only one set-up time prior to the LOW-to-HIGH
transition for predictable operation.
•
•
•
•
•
•
IDT54/74FCT377T equivalent to FAS"f"M speed
IDT54n4FCT377AT 25% faster than FAST
IDT54n4FCT377CT 40% faster than FAST
True TTL input and output compatibility:
- VOH = 3.3V (typ.)
- VOL = 0.3V (typ.)
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1 mW typo static)
Octal D flip-flop with clock enable
Meets or exceeds JEDEC Standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class 8
a
a
FUNCTIONAL BLOCK DIAGRAM
00
02
01
03
04
06
05
PIN CONFIGURATIONS
INOEX
CE
00
Do
D1
01
02
02
03
03
GNO
2
3
4
5
6
7
8
18
P20-1 17
020-1
16
S020-2
15
&
E20-1 14
13
12
9
11
10
07
2630 drw 02
Vcc
07
D7
06
06
05
05
04
04
CP
o
0lw
g"
000>0
32: :2019
01
01
02
02
03
]
]
]
]
]
4
5
6
7
8
Y
18
17
L20-2 16
15
14
9 1011 1213
[
[
[
[
[
07
06
06
05
05
rlrlrlrlrl
MOIL
' a
~L.....JllL.....JL-J
3
lOA
11A
NC
11B
lOB
]
]
]
]
]
4
5
6
2 I I 20 19
~
18 [ 100
110
16[ NC
15[ 11C
14[ lac
H[
L20-2
7
8
9
10 11 12 13
r-1r-1r-1r-,r-1
IIlOOQ.O
Oz zOO
(!)
DIP/SOIC/CERPACK
TOP VIEW
2633 drw 02
LCC
TOP VIEW
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
Description
Inputs
Outputs
S
Common Select Input
5
10
CP
Clock Pulse Input (Active Rising Edge)
I
I
lOA-laD
Data Inputs from Source 0
I
h
11A-11O
Data Inputs from Source 1
h
X
I
L
QA-QO
Register True Outputs
h
X
h
H
2633tbl05
. NOTE:
1. H
L
h
LOGIC SYMBOL
x
lOA I1A lOB
h
X
X
Q
L
H
26331bl06
HIGH Voltage Level
LOW Voltage Level
HIGH Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
LOW Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
Immaterial
I1B lac I1c 100 110
S
CP
2633 drw03
6.17
2
IDT54174FCT399TIAT/CT
FAST CMOS QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25°C , f = 1 OM Hz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
S
12
pF
VTERM(2) Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect
toGND
-0.5 to Vee
-0.5 to Vee
V
NOTE:
2633 tbl 02
1. This parameter is measured at characterization data and not tested.
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
2633tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
C ommercla:
. I T A = 0° C to +70° C VCC = 5.0 V ± 5 oYc0,. MT
Iitary: TA = -55° C to +125° CV CC = 5.0 V ±10%
Typ.(2)
Test Conditlons(1)
Min.
Symbol
Parameter
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
VI =2.7V
IlL
Input LOW Current
Vee = Max.
VI = 0.5V
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vee = Min., IN = -1SmA
los
Short Circuit Current
Vee = Max(3)., Va = GND
VOH
Output HIGH Voltage
Vee = Min.
10H = -6mA MIL.
VIN = VIH or VIL
10H = -SmA COM'L.
10H = -12mA MIL.
Max.
Unit
-
-
V
O.S
V
5
~
-
-5
~
-
20
~
-0.7
-1.2
V
-60
-120
-225
rnA
2.4
3.3
-
V
2.0
3.0
-
V
-
0.3
0.5
V
-
200
-
mV
0.2
1.5
rnA
2.0
-
10H = -15mA COM'L.
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power
Supply Current
Vee= Min.
10L = 32mA MIL.
VIN =- VIH or VIL
10L = 4SmA COM'L.
Vee = Max.
VIN = GND or Vee
.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.17
2633tbl03
3
IDT54174FCT3S!lT/AT/CT
FAST CMOS QUAD DUAL·PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Typ.(2)
Max.
Unit
-
0.5
2.0
mA
VIN = Vee
VIN = GND
-
0.15
0.25
mAl
MHz
VIN = Vee
VIN = GND
-
1.7
4.0
mA
One Bit Toggling at fi = 5MHz
50% Duty Cycle
S = Steady State
VIN =3.4V
VIN = GND
-
2.2
6.0
Vee = Max., Outputs Open
fep = 10MHz, 50% Duty Cycle
VIN = Vee
VIN = GND
-
4.0
7.8(5)
Four Bits Toggling at fi = 5MHz
50% Duty Cycle
S = Steady State
VIN = 3.4V
VIN =GND
-
5.2
12.8(5)
Test Condltlons(1)
Parameter
.1lee
Quiescent Power Supply
Current TTL Inputs HIGH
Vee= Max.
VIN = 3.4V(3)
leeD
Dynamic Power Supply
Current(4)
Ie
Total Power Supply
Current(6)
Vee = Max., Outputs Open
One Input Toggling
50% Duty Cycle
Vee = Max., Outputs Open
fep = 10MHz, 50% Duty Cycle
Min.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fi Ni)
Icc a Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.17
2633tb104
4
IDT54174FCT399T/AT/CT
FAST CMOS QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54174FCT399T
Conditlon(l)
Parameter
tPLH
tPHL
Propagation Delay
CP to On
tsu
Set-up Time
HIGH or LOW
IntoCP
4.0
-
4.5
tH
Hold Time
HIGH or LOW
IntoCP
1.0
-
tsu
Set-up Time
HIGH or LOW
StoCP
9.0
tH
Hold Time
HIGH or LOW
tw
StoCP
CP Pulse Width
3.0
10.0
IOT54174FCT399CT
Mil.
Com'l.
Mln.(2) Max. Mln.(2)
Max. Min.(2) Max.
Unit
2.5
7.0
2.5
7.5
2.5
6.1
2.5
6.6
ns
-
3.5
-
4.0
-
3.5
-
4.0
-
ns
1.5
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
-
9.5
-
8.5
-
9.0
-
8.5
-
9.0
-
ns
a
-
0
-
0
-
a
-
a
-
a
-
ns
5.0
-
7.0
-
5.0
-
6.0
-
5.0
-
6.0
-
ns
3.0
11.5
Mil.
Com'l.
Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.
Symbol
CL= 50pF
RL= soon
IOT54174FCT399AT
Mil.
Com'l.
HIGH or LOW
NOTES:
26331b1 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
II
6.17
5
G
I DT54/74 FCT521 T
I DT54/74 FCT521 AT
IDT54/74FCT521 BT
IDT54/74FCT521CT
FAST CMOS a-BIT
IDENTITY COMPARATOR
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT521T equivalent to FASTTM speed
The IDT54/74FCT521T/AT/BT/CT are 8-bit identity comparators built using advanced CEMOSrn, a dual metal CMOS
technology. These devices compare two words of up to eight
bits each and provide a LOW output when the two words
match bit for bit. The expansion input IA = B also serves as an
active LOW enable input.
• IDT54174FCT521AT 35% faster than FAST
• IDT54/74FCT521BT 50% faster than FAST
• IDT54174FCT521CT 60% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial), and 32mA (military)
• CMOS power levels (1 mW typo static)
• True TIL input and output levels
• Substantially lower input current levels than FAST
(5JlA max.)
• 8-bit Identitiy Comparator
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
~~=c;:!>:l
~~=c;:!>:l
~:=c;:!>:l
2572 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<1:l1992 Integrated Device Technology. Inc.
6.18
MAY 1992
OSC-421013
1
IDT54174FCT521T/AT/BT/CT
FAST CMOS 8-BIT IDENTITY COMPARATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
Vee
TA=B
Ao
2
80
3
A1
4
81
5
A2
6
82
7
A3
8
I
UA=B
3
87
P20-1
D20-1
S020-2
S020-7
&
E20-1
II
II
L-.I L-.l1
A7
8s
As
85
A1
:] 4
81
:] 5
A2
:] 6
82
:] 7
A3
:] 8
A5
2
U
II II
I
I L-J L-J
20 19
18[:
1
17[:
L20-2
B7
A7
16[:
8s
15[:
As
14[:
85
9 10 11 12 13
....,....,....,...., r 1
83
GND
9
84
10
A4
I
II
II
II
I
dl ~..1: ci5 ~
2572 drw 02
2572 drw 03
C!)
DIP/SOIC/SSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
PIN DESCRIPTION
Pin Names
Description
Ao-A7
Word A Inputs
80- 87
Word 8 Inputs
Symbol
IA = B
Expansion or Enable Input (Active LOW)
OA= B
Identity Output (Active LOW)
Inputs
Output
A,B
OA=B
L
L
A = 8*
L
A*B
A = B*
H
H
H
A*B
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
·Ao = 80, A1 = 81, A2 = 82, etc.
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
FUNCTION TABLE(1)
IA=B
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
2572tbl 05
H
H
II
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
2572tbl06
NOTES:
2572 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input
Conditions
Typ.
Max.
Unit
VIN = OV
6
10
pF
VOUT= OV
8
12
pF
C~acitance
COUT
Output
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
6.18
2572 tbl 02
2
IDT54174FCT521 T/AT/ST/CT
FAST CMOS 8·BIT IDENTITY COMPARATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V +
- 10%
Test Condltlons(1)
Symbol
Parameter
Min. Typ.!2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
-
Max.
Unit
-
V
O.S
V
IIH
Input HIGH Current
Vce = Max.
VI =2.7V
-
-
5
JlA
IlL
Input LOW Current
Vee = Max.
VI = 0.5V
JlA
Input HIGH Current
Vec = Max., VI = Vee (Max.)
-
-5
II
20
VIK
Clamp Diode Voltage
Vee = Min., IN = -1SmA
-
-0.7
-1.2
JlA
V
-60
-120
-225
mA
2.4
3.3
-
V
2.0
3:0
-
V
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
mA
los
Short Circuit Current
Vee = Max.(3), Vo= GND
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power Supply Current
IOH = -6mA MIL.
10H = -SmA COM'L.
IOH = -12mA MIL.
10H = -15mA COM'L.
10L = 32mA MIL.
10L = 4SmA COM'L.
Vee = Min.
VIN = VIH or VIL
Vee = Max.
VIN = GND or Vee
NOTES:
2572tbl03
1. For conditions shown as Max.. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
POWER SUPPLY CHARACTERISTICS
Symbol
leeD
Ie
Total Power Supply Current (5)
~Iee
Typ.(2)
Max.
Unit
-
0.5
2.0
mA
VIN = Vee
VIN = GND
-
0.15
0.25
mAl
MHz
VIN
VIN
VIN
VIN
-
1.7
4.0
mA
-
2.0
5.0
Test Condltlons(1)
Parameter
Quiescent Power Supply
Current TTL
I~uts HIGH
Dynamic Power Supply Current (4)
Vee", Max.
VIN = 3.4V(3)
Vee = Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Vee = Max.
Outputs Open
f i= 10MHz
One Bit Toggling
50% DUty Cycle
= Vee
= GND
=3.4V
= GND
Min.
NOTES:
1.
2.
3.
4.
5.
2572tb104
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is notdirectly testable, but is derived for use in Total Power Supply calculations.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc +Alcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current· .
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
Df! = Duty Cycle for TTL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.18
3
IDT54174FCT521T/AT/BT/CT
FAST CMOS a·BIT IDENTITY COMPARATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT521T
Symbol
tPLH
tPHL
Parameter
Propagation
Delay
An or Bn to
IDT54174FCT521AT
IDT54174FCT521 BT
CL = 50pF
Mil.
Com'l.
Mil.
Com'l.
IDT54174FCT521 CT
Com'l.
Mil.
Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
Com'l.
Mil.
1.5 11.0 1.5 15.0 1.5
7.2
1.5
9.5
1.5
5.5
1.5
7.3
1.5
4.5
1.5
5.1
ns
1.5 10.0 1.5
6.0
1.5
7.8
1.5
4.6
1.5
6.0
1.5
4.1
1.5
4.5
ns
RL =5000
OA= B
tPLH
tPHL
Propagation
Delay
TA = B to
OA= B
9.0
1.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2572 tbl 07
6.18
4
(;)®
Integrated Device Technology, Inc.
IDT54/74FCT543T
IDT54/74FCT543AT
I DT54/74 FCT543CT
I DT54/74 FCT543DT
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
FEATURES:
DESCRIPTION:
• Fastest CMOS logic family available
• Std., A, C and D speed grades with 4.4ns tPD
• Available in DIP, SOIC, SSOP, CERPACK and LCC
packages
• Equivalent to FASTTM output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial), 4BmA (military)
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (1 mW typo static)
• Substantially lower input current levels than FAST
The IDT54/74FCT543T/AT/CT/DT are non-inverting octal
transceivers .built using advanced CEMOSTM, a dual metal
CMOS technology. These devices contain two sets of eight Dtype latches with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from Ao-A7
or to take data from Bo-B7, as indicated in the Function Table.'
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the 3-state B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses the CEBA, LEBA and OEBA inputs.
(5~max.)
• True TTL input and output levels
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-BB3, Class B
FUNCTIONAL BLOCK DIAGRAM
r--------------------------------------------------..,
I
o
I
I
DETAIL A
~----------~~r-Bo
I
I
I
I
I
I
I
I
Ao~--~~----------~<
Q
o
I
I
I
I
I
LE
I
I
I
I
I
__...JI
I
___ _________________
A1
B1
A2
A3
A4
A5
B2
B3
B4
B5
DETAILAx 7
As
Bs
A7
B7
OEBA -------a
I - -_ _ _ _ _ _ _ _ _ _ _ _-t-I~l:)------
OEAB
l J -_ _- - - -
CEAB
CEBA ------+--a
LEBA
'------ LEAB
26t3 drwOl
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOt 992 Integrated Device Technology, Inc.
6.19
MAY 1992
DSC-4203!3
1
IDTS4174FCTS43T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LEBA
OEBA·
Ao
A1
A2
A3
A4
As
A6
A7
CEAB
GND
2
3
4
S
6
7
8
9
10
11
12
CEBA
Bo
B1
B2
B3
B4
Bs
B6
B7
LEAB
OEAB
P24-1
024-1
S024-2
S024-7
&
E24-1
m 1«
mom
1«
1«
oWwOoWo
«O....JZ>Om
INDEX
Vee
1'--' L...J L.-J
43211282726
L.-JL.-J'--'I
L..J
]s
2S[
1
]6
24[
]7
23[
]8
22[
L28-1
]9
21[
]10
20 [
19 [
] 11
12
13 14 1S 16 17 18
.,.,,....,.,,....,,....,.,
A1
A2
A3
NC
A4
As
A6
:
LCC
TOP VIEW
6.23
2
IDT54174FCT821/823AT/BT/CT/DT, 825/826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(l)
I DT54/74FCT821 /823/825T
PRODUCT SELECTOR GUIDE
Device
10·Blt
9·Blt
I Non-inverting FCTB21AT/BT/CT/DT FCTB23AT/BT/CT/DT
I Inverting
Inputs
8·Blt
FCTB25AT/BTlCT
FCTB26AT/BT/CT
2567tbiOl
PIN DESCRIPTION
Description
Names
I/O
DI
I
The D flip-flop data inputs.
CLR
I
When the clear input is LOW and OE is
LOW, the QI outputs are LOW. When
the clear input is HIGH, data can be
entered into the reqister.
CP
I
Clock Pulse for the Register; enters
data into the register on the LOW-to·
HIGH transition.
YI
0
The register 3-state outputs.
EN
I
Clock Enable. When the clock enable is
LOW, data on the D I input is transferred
to the QI output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the QI outputs do not change
state, regardless of the data or clock
input transitions.
Output Control. When the OE input is
HIGH, the Y I outputs are in the high·
impedance state. When the OE input is
LOW, the TRUE register data is present
at the YI outputs.
OE
,'"
I
Internal!
Out Juts
QI
YI
OE
CLR
EN
01
H
H
'H
H
L
L
L
H
CP
t
t
H
L
L
L
X
X
H
L
H
H
H
H
X
X
X
X
X
X
X
X
L
L
NC
NC
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
t
,t
t
t
L
H
L
H
L
H
Function
Z
HighZ
Z
Z
Clear
L'
Z
Hold
NC
Z
z
Load
L
H
NOTE:
1. H = HIGH
L=LOW
X = Don't Care
NC = No Change
t = LOW-to-HIGH Transition
Z = High Impedance
2567tbl03
FUNCTION TABLE(l)
IDT54174FCT826T
Inputs
Internal!
Out Juts
QI
YI
CLR
EN
01
H
, H
H
H
L
L
L
H
CP
t
t
H
L
L
L
X
X
H
H
L
H
H
H
X
X
X
X
'X
X
X
X
NC
NC
NC
H
H
L
L
H
L
L
L
L
L
H
L
H
t
t
t
t
H
L
H
L
Z
Z
H
L
OE
25671bl02
H
H
H
NOTE:
1. H = HIGH
L=LOW
X = Don't Care
NC ;; No Change
t = LOW-to-HIGH Transition
Z = High Impedance
6.23
H
L
L
L
Z
Z
Z
Function
HighZ
Clear
L
Z
Hold
Load
, 2567tbll0
3
IDT54174FCT821/823AT/BT/CT/DT, 825/826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Ratln~
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
(TA ...
+25°C, f = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
eOUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
2567tbl05
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
mA
NOTES:
2567tb104
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vee ... 5.0V ± 10%
Min.
Typ.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
VI = 2.7V
-
-
Symbol
Test Condltlons(1)
Parameter
IlL
Input LOW Current
Vee = Max.
VI = 0.5V
-
IOZH
High Impedance Output Current
Vee = Max.
Vo=2.7V
-
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee = Max'<3), Va = GND
VOH
Output HIGH Voltage
Vee = Min.
10Zl
Va = 0.5V
VIN = VIH or Vil
Val
Output LOW Voltage
VH
Input Hysteresis
Icc
Quiescent Power Supply Current
Vee = Min.
VIN = VIH or Vil
Vee = Max.
VIN = GND or Vee
-
-
-
Unit
V
0.8
V
5
~
-5
~
10
~
-10
20
~
-0.7
-1.2
V
-60
-120
-225
mA
IOH = -6mA MIL.
IOH = -SmA COM'L.
2.4
3.3
-
V
IOH = -12mA MIL.
IOH = -15mA COM'L.
2.0
3.0
-
V
IOl = 32mA MIL.
IOl = 48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
mA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.23
Max.
2567tbl06
4
IDT54174FCT821/823AT/BT/CT/DT, 825/826AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Svmbol
Test Condltlons(1)
Parameter
~Iee
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
IceD
Dynamic Power Supply Current(4)
Vee = Max.
VIN = Vee
~utsOpen
VIN = GND
Min.
TVp.(2)
Max.
Unit
-
0.5
2.0
mA
-
0.15
0.25
mAl
MHz
OE= EN=GND
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
Vee = Max.
Outputs Open
fep= 10MHz
VIN = Vee
-
1.7
4.0
-
2.2
6.0
-
4.0
7.8(5)
-
6.2
16.8(5)
mA
VIN = GND
50% Duty Cycle
OE = EN = GND
VIN = 3.4V
One Bit Toggling
atfi '" 5MHz
50% Dutv Cvcle
VIN = GND
Vee = Max.
VIN = Vee
Outputs Open
fep= 10MHz
VIN = GND
50% Duty Cycle
DE= EN", GND
Eight Bits Toggling
VIN '" 3AV
VIN = GND
at fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3AV); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.23
2567 tbl 07
5
IDT54174FCT821/823AT/BT/CT/DT, 825/826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821 AT-826AT
Com'l.
tPHL
tsu
Com'l.
Mil.
Condltlon(1)
MlnJ2)
Max.
MlnJ2)
Max.
MlnJ2)
Max.
MlnJ2)
Max.
Unit
Propagation Delay
CP to VI (OE = LOW)
50pF
RL= 500n
CL = 300pF(4)
RL = 500n
CL = 50pF
RL= 500n
1.5
10.0
1.5
11.5
1.5
7.5
1.5
8.5
ns
1.5
20.0
1.5
20.0
1.5
15.0
1.5
16.0
4.0
-
4.0
-
3.0
-
3.0
-
ns
2.0
-
2.0
-
1.5
-
1.5
-
ns
Set-up Time HIGH or LOW
DltoCP
tH
Mil.
Parameter
Symbol
tPLH
FCT821 BT-826BT
CL =
Hold Time HIGH or LOW
DltoCP
tsu
Set-up Time HIGH or LOW
EN to CP
4.0
-
4.0
-
3.0
-
3.0
-
ns
tH
Hold Time HIGH or LOW
EN to CP
2.0
-
2.0
-
0
-
0
-
ns
tPHL
Propagation Delay. CLR to VI
1.5
tREM
Recovery Time CLR to CP
6.0
tw
Clock Pulse Width
7.0
1.5
15.0
1.5
9.0
1.5
9.5
ns
-
7.0
-
6.0
-
6.0
-
ns
-
7.0
-
6.0
-
6.0
-
ns
-
7.0
-
ns
ns
14.0
HIGH or LOW
tw
CLR Pulse Width LOW
tPZH
Output Enable Time OE to VI
tPZL
tPHZ
Output Disable Time OE
tPLZ
to VI
6.0
-
6.0
-
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
1.5
7.0
1.5
8.0
1.5
6.5
1.5
7.0
1.5
8.0
1.5
9.0
1.5
7.5
1.5
8.0
6.0
50pF
RL= 500n
CL = 300pF(4)
RL= 500n
CL = 5pF(4)
RL = 50 on
CL = 50pF
RL= 50 on
CL =
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
ns
2567tbl08
6.23
6
IDT54174FCT821/823AT/BT/CT/DT, 825/826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821CT·826CT
Parameter
Svmbol
tPLH
tPHL
tsu
tH
Propagation Delay
CP to VI (OE = LOW)
Set-up Time HIGH or LOW
DltoCP
Condltlon(1)
CL = 50pF
RL= 500n
CL = 300pF(4)
RL = 50 on
CL = 50pF
RL= 500n
Hold Time HIGH or LOW
Com'l.
Mln.(2) Max.
1.5
6.0
1.5
12.5
Mil.
Mln.(2) Max.
1.5
7.0
1.5
13.5
FCT821DT
FCT823DT
Com'l.
Mln,(2) Max.
1.5
4.2
Com'l.
Mln.(2) Max.
5.0
1.5
1.5
8.0
1.5
8.5
Unit
ns
3.0
-
3.0
-
2.0
-
2.0
-
ns
1.5
-
1.5
-
1.0
-
1.0
-
ns
3.0
-
3.0
-
3.0
-
3.0
-
ns
0
-
0
-
0
-
0
-
ns
DltoCP
tsu
Set-up Time HIGH or LOW
EN toCP
tH
Hold Time HIGH or LOW
EN to CP
tPHL
Propagation Delay, CLR to VI
1.5
8.0
1.5
8.5
1.5
5.0
1.5
5.0
ns
tREM
Recovery Time CLR to CP
6.0
-
6.0
-
3.0
-
3.0
-
ns
tw
Clock Pulse Width
HIGH or LOW(3)
6.0
-
6.0
-
3.0
-
3.0
-
ns
6.0
-
6.0
-
3.0
-
3.0
-
ns
1.5
7.0
1.5
8.0
1.5
4.8
1.5
4.8
ns
1.5
12.5
1.5
13.5
1.5
9.0
1.5
9.0
1.5
6.0
1.5
6.0
1.5
4.0
1.5
4.0
1.5
6.5
1.5
6.5
1.5
4.0
1.5
4.0
tw
CLR Pulse Width LOW(3)
tPZH
Output Enable Time OE to VI
tPZL
tPHZ
Output Disable Time OE
tPLZ
to VI
50pF
RL= 500n
CL = 300pF(4)
RL= 500n
CL = 5pF(4)
RL= 500n
CL = 50pF
RL= 500n
CL =
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
ns
2567tbl09
6.23
7
~
FAST CMOS 10-BIT
BUFFERS
I DT54/74 FCT827ATIBTICTIDT
IDT54/74FCT828AT/BT/CT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Fastest CMOS logic family available
• A, S, Cand 0 speed grades with 3.8ns tPD
• Available in DIP, SOIC, SSOP, CERPACK and LCC
packages
• 10L = 48mA (commercial), and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
• True TIL input and output level compatible
• Substantially lower input current levels than AMD's
bipolar Am29800 series (5jlA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class S
The IDT54/74FCT800 series is built using advanced
. CEMOSTM, a dual metal CMOS technology.
The IDT54174FCT827AT/STICTlOT and IDT54174FCT828AT/ST/CT 10-bit bus drivers provide high-performance bus
interface buffering for wide data/address paths or buses
. carrying parity. The 10-bit buffers have NAND-ed output
enables for maximum control flexibility.
All of the IDT54174FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
Yo
Y1
Y3
Y2
. Ys
Y4
Y6
Y7
Ya
Y9
2573 cnv· 01
PRODUCT SELECTOR GUIDE
I Non-inverting
I Inverting
10·Blt Buffer
IOT5417 4FCT827 AT/BT/CT/OT
IOT5417 4FCT828AT/BTlCT
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
2573tbiOl
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-~;"'-YO·9
Y2
Y3
Y4
NC
Ys
20[: Y6
07 :]11
19 [: Y7
12131415161718
nnnnnnn
co ClOO '" Cl co
oOzziW>->C!)
DIP/SOIC/SSOP/CERPACK
TOP VIEW
10
2573 cnv' 02-{)4
LCC
TOP VIEW
• FCT827AT/BT/CT/DT only.
PIN DESCRIPTION
01
I
Description
When both are LOW the outputs are
enabled. When either one or both are
HIGH the outputs are High Z.
1O·bit data input.
YI
0
1O-bit data output.
Names
OEI
1/0
I
2573 tbl 02
FUNCTION TABLES
IDT54/74FCT827T (NON-INVERTING)(1)
IDT54/74FCT828T (INVERTING)(1)
Output
Inputs
Inputs
Output
/
OE1
OE2
DI
YI
Function
OE1
OE2
DI
YI
Function
L
L
Transparent
H
Transparent
Three-State
H
L
L
X
L
H
H
Z
Z
L
L
X
L
H
X
X
L
H
L
L
X
X
H
NOTE:
1. H = HIGH, L = LOW, X
2573 tbl 03
= Don't Care, Z = High Impedance
H
L
X
X
Z
Z
NOTE:
1. H = HIGH, L = LOW, X = Don't Care, Z
6.24
Three-State
2573 tbl 04
= High Impedance
2
IDT54174FCT827 AT/BT/CT/DT, IDT54174FCT828AT/BT/CT
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Ratln~
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
(TA = +25°C,
Parameter(1)
Symbol
f = .1.0MHz)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
.10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
NOTES:
2573 tbl 06
1. This parameter is measured at characterization but not tested.
2573 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC= 5.0V ± 10%
Min.
Typ.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
VI =2.7V
-
III
Input LOW Current
Vee = Max.
VI = 0.5V
-
10ZH
High Impedance Output Current
Vee = Max.
Vo= 2.7V
-
-
Symbol
Test Condltlons(1)
Parameter
10Zl
Va = 0.5V
.
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
-
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
los
Short Circuit Current
Vee = Max.(3), Vo= GND
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or Vil
Val
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power Supply Current
Vee = Min.
VIN = VIH or Vil
Vee = Max.
VIN = GND or Vee
Max.
-
Unit
V
0.8
V
5
IlA
-5
IlA
10
IlA
-10
20
IlA
-0.7
-1.2
V
-60
-120
-225
mA
10H = -6mA MIL.
10H = -8mA COM'L.
2.4
3.3
-
V
10H = -12mA MIL.
10H = -15mA COM'L.
2.0
3.0
-
V
10l = 32rnA MIL.
10l = 48rnA COM'L.
-
0.3
0.5
V
-
200
-
rnV
0.2
1.5
rnA
NOTES:
2573tbl07
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
6.24
3
IDT54174FCT827ATIBTICTIDT, IDT54174FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Svmbol
~Iee
leeD
Test Condltlons(1)
Parameter
TTL IJ'lQuts HIGH
Vee = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vee = Max.
VIN = Vee
Outputs Open
OE1 = OE2 = GND
VIN = GND
Quiescent Power Supply Current
Min.
TVD.(2)
Max.
Unit
-
0.5
2.0
mA
-
0.15
0.25
mAl
MHz
One Input Toggling
50% Dutv Cvcle
Ie
Total Power Supply Current(6)
Vee = Max.
Outputs Open
=
VIN Vee
VIN = GND
-
1.7
4.0
VIN = 3.4V
VIN GND-
-
2.0
5.0
VIN = Vee
-
3.2
6.5(5)
-
5.2
14.5(5)
mA
fi = 10MHz
50%D~Cycle
OE1 = OE2
=GND
=
One Bit Tooolino
Vee = Max.
Outputs Open
VIN
=GND
fi = 2.5MHz
50%D~Cycle
OE1
=OE2 = GND
=
VIN 3.4V
VIN .. GND
EiQht Bits TOQQlinQ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs atVcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
,
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f i = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.24
. 2573tbl 08
4
IDT54174FCT827AT/BT/CT/DT, IDT54174FCT828AT/BT/CT
HIGH·PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT827 AT/828AT
Symbol
tPLH
tPHL
Parameter
Propagation Delay
DltoYI
IDTS4174FCTB27T (Non·
inverting)
tPLH
tPHL
Propagation Delay
DltoYI
IDTS4174FCT828T
(Inverting)
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OEltoYI
Output Disable Time
OEI to YI
Condltlons(1)
CL = SOpF
RL = soon
CL =300pF(3)
54/74FCT827BT/828BT
Mil.
Com'l.
Mil.
Com'l.
Mln.(2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Unit
1.S
B.O
1.S
9.0
1.S
S.O
1.S
6.S
ns
1.S
1S.0
1.S
17.0
1.S
13.0
1.S
14.0
1.S
9.0
1.S
10.0
1.S
S.S
1.S
6.S
1.S
14.0
1.S
16.0
1.S
13.0
1.S
14.0
1.S
12.0
1.S
13.0
1.S
8.0
1.S
9.0
1.S
23.0
1.S
2S.0
1.5
1S.0
1.S
16.0
1.S
9.0
1.S
9.0
1.S
6.0
1.S
7.0
1.S
10.0
1.S
10.0
1.S
7.0
1.S
8.0
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
ns
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SpF(3)
RL = Soon
CL = SOpF
RL = soon
ns
ns
2573tbll0
54/74FCT827CT/828CT
Symbol
tPLH
tPHL
Parameter
Propagation Delay
DltoYI
IDTS4174FCT827T (Non·
inverting)
tPLH
tPHL
Propagation Delay
DltoYI
I DTS4174 FCT828T
(Inverting)
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OEI to YI
Output Disable Time
OElto YI
Conditlons(1)
CL = SOpF
RL = soon
CL = 300pF(3)
54/74FCT827DT
Mil.
Com'l.
Mln.(2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
1.S
4.4
1.S
S.O
1.S
3.8
-
-
1.S
10.0
1.S
11.0
1.S
7.S
-
-
1.S
4.4
1.S
S.O
-
-
-
-
1.S
10.0
1.S
11.0
-
-
-
-
1.S
7.0
1.S
8.0
1.S
S.O
-
-
1.S
14.0
1.S
1S.0
1.S
9.0
-
-
1.S
S.7
1.S
6.7
1.S
4.3
-
-
1.S
6.0
1.S
7.0
1.S
4.3
-
-
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
RL = soon
CL = SOpF
RL = soon
CL = 300pF(3)
RL = Soon
CL= SpF(3)
RL = soon
CL= SOpF
RL = soon
Mil.
Com'l.
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These conditions are guaranteed but not tested.
Mln.(2)
Max.
Unit
ns
ns
ns
ns
2573tblll
6.24
5
(;)
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
Integrated Device Technology, Inc.
I DT54/74 FCT841AT/BT/CT/DT
I DT54/74 FCT843AT/BT/CT
IDT54/74FCT845AT/BT/CT
FEATURES:
DESCRIPTION:
• Fastest CMOS logic family available
• A, B, C and 0 speed grades with 4.2ns tPD
• Available in DIP, SOIC, SSOP, CERPACK and LCC
packages
• TRUE TTL input and output compatible
- VOH = 3.3V (typ)
- VOL = O.3V (typ).
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
Substantially lower input current levels than AMD's
bipolar Am29800 series (51lA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meet or exceed JEDEC Standard 18 specifications
The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT840 Series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider
address/data paths or buses carrying parity. The IDT541
74FCT841 AT/BT/CT/DT are buffered, 1O-bit wide versions of
the popular '373 function. The IDT54/74FCT843AT/BT/CT
are 9-bit wide buffered latches with Preset (PRE) and Clear
(CLR) - ideal for parity bus interfacing in high-performance
systems. The IDT54/74FCT845AT/BT/CT are 8-bit buffered
latches with all the '843 controls, plus multiple enables (OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
DMA and RD/WR. They are ideal for use as an output port
requiring high loUloH.
All of the IDT54174FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
Yo
Y1
Y2
Y3
Y4
Ys
YN-1
YN
2571 cnv' 01
PRODUCT SELECTOR GUIDE
Device
CEMOS is a trademark 01 Integrated Device Technology. Inc.
FAST is a trademark 01 National Semiconductor Co.
9-Bit
8-Bit
IDT54174FCT841
IDT54174 FCT843
IDT54174FCT845
AT/BT/CT/DT
AT/BT/CT
AT/BT/CT
2571 tbl 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
10-Bit
6.25
MAY 1992
DSC-420412
IDT54174FCT841AT/BT/CT/DT,843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT841T 10·81T LATCH
DE
Do
D1
D2
D3
D4
Ds
D6
D7
Da
D9
GND
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
Ya
yg
INDEX
11111 II
D2
D3
D4
NC
Ds
D6
D7
LE
:J5
:J6
I111111
~'3''t12a272s
25[:
24[:
23[:
:J7
:J8
22[:
L28-1
:]9
21[:
20[:
:J10
:J11
19[:
12131415161718
nnnnnnn
Y2
Y3
Y4
NC
Ys
Ys
Y7
D
Y
LE
DE
CS8~~~~>
(!)
2571 cnv' 02,03,08
LCC
TOP VIEW
DIP/CERPACKISOIC/SSOP
TOP VIEW
IDT54174FCT843T 9·81T LATCH
DE
Do
D1
D2
D3
D4
Ds
D6
D7
Da
CLR
GND
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
PRE
LE
INDEX
D2
D3
D4
NC
Ds
D6
D7
L28-1
Y2
Y3
Y4
NC
Ys
Y6
Y7
D
Y
LE
PRE
CLR
OE
nnnnnnn
CSIa:OOWI~~
d~Z--l c..
DIP/CERPACKISOIC
TOP VIEW
LCC
TOP VIEW
2571 cnv' 04,05,09
IDT54174FCT845T 8-81T LATCH
2571 cnv' 06,07,10
6.25
2
IDT54174FCT841AT/BT/CT/DT, 843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Name
CLR
I/O
I
Description
When CLR is low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data
Inter-
can be entered into the latch.
DI
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-ta-LOW
transition.
YI
0
The 3-state latch outputs.
OE
I
The output enable control. When OE is
LOW, the outputs are enabled. When OE
is HIGH, the outputs VI are in high-
PRE
I
irnj!edance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR.
2571 tbl02
Inputs
CLR PRE OE LE
nal
Output
01
QI
VI
X
X
X
Z
High Z
H
H
H
Function
H
H
H
H
L
L
Z
HighZ
H
H
H
H
H
H
Z
HighZ
H
H
H
L
X
NC
Z
Latched (High Z)
H
H
L
H
L
L
L
Transparent
Transparent
H
H
L
H
H
H
H
H
H
L
L
X
NC
NC
H
L
L
X
X
H
H
Preset
Latched
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched (High Z)
H
L
H
L
X
H
Z
Latched (High Z)
2571 tbl 03
NOTE:
1. H = HIGH, L= LOW, X = Don't Care, NC = No Change, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
RatlnQ
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Militarv
Unit
-0.5 to +7.0
-D.5to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
(TA
Parameter(1)
= +25°C, f = 1.0MHz)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
Symbol
NOTE:
1.This parameter is measured at characterization but not tested.
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
2571 tbl05
NOTES:
2571 tbl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vec terminals only.
3. Outputs and I/O terminals only.
6.25
3
IDT54174FCT841AT/BT/CT/DT,843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Com mercia
. I: TA= O°C t 0+ 70°C VCC = 5 OV + 5°/c0 MT
Iitary: TA=- 55°C to + 125 0 C VCC= 50V + 1000
Yc
Min.
Tvp.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
-
IIH
Input HIGH Current
Vee = Max.
VI = 2.7V
-
III
Input LOW Current
Vee = Max.
VI = 0.5V
10ZH
High Impedance Output Current
Vee = Max;
Vo= 2.?V
-
-
S~mbol
Test Condltlons(1)
Parameter
10Zl
Va = 0.5V
II
Input HIGH Current
Vee = Max., VI = Vee (Max.)
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee = Max.(3), Vo= GND
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or Vil
Val
Output LOW Voltage
VH
Input Hysteresis
lee
Quiescent Power Supply Current
Vee = Min.
VIN = VIH or Vil
Vee = Max.·
VIN = GND or Vee
-
Max.
-
Unit
V
0.8
V
5
J.tA
J.tA
J.tA
-5
10
-10
20
J.tA
-D.?
-1.2
V
-BO
-120
-225
mA
10H = -BmA MIL.
10H = -8mA COM'L.
2.4
3.3
-
V
10H =-12mA MIL.
10H = -15mA COM'L.
2.0
3.0
-
V
10l = 32mA MIL.
10l =48mA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
mA
NOTES:
25711bl06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. DUration of the short circuit test shOUld not exceed one second.
6.25
4
IDT54n4FCT841AT/BT/CT/DT, 843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Typ.(2)
Max.
Unit
-
0.5
2.0
rnA
VIN = Vee
VIN = GND
-
0.15
0.25
VIN = Vee
VIN = GND
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.0
5.0
VIN = Vee
VIN = GND
-
3.2
6.5(5)
VIN = 3.4V
VIN =GND
-
5.2
14.5(5)
Test Conditlons(1)
Parameter
Alec
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
IceD
Dynamic Power Supply Current(4)
Vee = Max.
Outputs Open
OE=GND
Min.
mAl
MHz
LE = Vee
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
Vee = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE=GND
rnA
LE = Vee
One Bit Toggling
Vee = Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
OE=GND
LE = Vee
Eight Bits Toggling
NOTES:
1.
2.
3.
4.
5.
6.
25711bl07
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + !iNPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN =3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.25
5
IDT54174FCT841AT/BT/CTIDT,843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARV AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841 AT/843AT/845AT
Com'l.
Symbol
tPLH
tPHL
Condltlons(l)
Parameter
Propagation Delay
01 t~ VI (LE = HIGH)
Propagation Delay
LEtoVI
tPLH
Propagation Delay, PRE to VI
tPHL
Max.
MlnJ2)
Max.
Mln.(2)
Max.
Unit
1.5
9.0
1.5
10.0
1.5
6.5
1.5
7.5
ns
1.5
13.0
1.5
15.0
1.5
13.0
1.5
15.0
1.5
12.0
1.5
13.0
1.5
8.0
1.5
10.5
1.5
16.0
1.5
20.0
1.5
15.5
1.5
18.0
1.5
12.0
1.5
14.0
1.5
8.0
1.5
10.0
1.5
,14.0
1.5
17.0
1.5
10.0
1.5
13.0
1.5
13.0
1.5
14.0
1.5
10.0
1.5
11.0
1.5
14.0
1.5
17.0
1.5
10.0
1.5
10.0
1.5
11.5
1.5
13.0
1.5
8.0
1.5
8.5
1.5
23.0
1.5
25.0
1.5
14.0
1.5
15.0
CL = 50pF
RL= 500n
CL= 300pP4)
RL= 500n
CL .. 50pF
Propagation Delay, CLR to VI
Output Enable lime OE to VI
"
,
tPHZ
tPLZ
.
Output Disable lime OE to VI
Mil.
MlnJ2)
tPLH
tPZH
tPZL
Com'l.
Max.
RL= 500n
tPHL
FCT8418T/8438T/8458T
Mln.(2)
CL= 50pF
RL = 500n
CL = 300pp4)
RL= 500n
tPLH
tPHL
Mil.
CL= 50pF
'RL .. 500n
CL = 300pp4)
RL .. 500n
CL':: 5pF(4)
ns
ns
ns
ns
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
CL =50pF
RL= 500n
1.5
8.0
1.5
10.0
1.5
7.0
1.5
7.5
2.5
-
2.5
2.5
-
ns
3.0
-
2.5
-
2.5
4.0
-
4.0
ns
4.0
-
4.0
-
4.0
-
ns
RL= 500n
tsu
Data to LE Set-up lime
CL= 50pF
2.5
tH
Data to LE Hold lime
RL = 500n
2.5
-
tw
LE Pulse Width(3)
4.0
-
5.0
-
7.0
-
5.0
-
4.0
-
4.0
-
4.0
HIGH
tw
PRE Pulse Width(3)
LOW
5.0
tw
CLR Pulse Width(3)
LOW
4.0
tREM
Recovery lime PRE to LE
4.0
tREM
Recovery lime CLR to LE
3.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
3.0
3.0
4.0
I-
3.0
-
ns
ns
ns
ns
ns
2571 tbl08
6.25
6
IDT54n4FCT841AT/BT/CT/DT, 843/845AT/BT/CT
CMOS BUS INTERFACE LATCHES
MILITARV AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841 CT/843CT/845CT
Com'l.
Symbol
Conditions(1)
CL = 50pF
Parameter
tPLH
Propagation Delay
tPHL
01 to VI (LE
= HIGH)
RL =
CL =
tPLH
Propagation Delay
tPHL
LE to VI
RL=
soon
CL =
50pF
RL=
soon
CL =
tPLH
Propagation Delay, PRE to YI
tPHL
tPHL
soon
300pp4)
Output Enable TIme OE to YI
Output Disable TIme OE to YI
tPLZ
1.5
5.5
1.5
6.3
1.5
4.2
-
-
1.5
13.0
1.5
15.0
1.5
8.0
-
-
1.5
6.4
1.5
6.8
1.5
4.0
-
-
1.5
15.0
1.5
16.0
1.5
8.0
CL =
50pF
1.5
7.0
1.5
9.0
-
-'
-
RL=
soon
1.5
9.0
1.5
12.0
-
CL =
50pF
RL=
soon
CL =
tPHZ
Mil.
Max. MinJ2) Max.
soon
Propagation Delay, CLR to YI
tPZL
Max. MinP)
RL=
tPLH
tPZH
Com'l.
Max. MinJ2)
MinJ2)
300pp4)
FCT841DT
Mil.
300pp4)
RL=
soon
CL =
5pF(4)
RL=
soon
ns
-
-
-
-
ns
ns
1.5
9.0
1.5
10.0
9.0
1.5
9.0
1.5
6.5
1.5
7.3
1.5
4.8
-
-
1.5
12.0
1.5
13.0
1.5
9.0
-
-
1.5
5.7
1.5
6.0
1.5
4.0
-
-
4.0
-
-
-
-
CL =
50pF
RL =
soon
1.5
6.0
1.5
6.3
1.5
-
1.5
-
1.0
3.0
-
-
-
-
-
Data to LE Set-up TIme
CL =
50pF
2.5
-
2.5
Data to LE Hold TIme
RL=
soon
2.5
2.5
tw
LE Pulse Width(3)
HIGH
4.0
tw
PRE Pulse Width(3)
LOW
4.0
tw
CLR Pulse Width(3)
LOW
4.0
tREM
Recovery TIme PRE to LE
4.0
tREM
Recovery TIme CLR to LE
3.0
-
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
4.0
4.0
4.0
4.0
3.0
ns
-
1.5
tH
ns
-
-
tsu
Unit
-
ns
ns
ns
ns
ns
ns
ns
ns
2571 tbl09
6.25
7
t;J®
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
Integrated Device Technology,lnc.
IDT29FCT52A/B/C
IDT29FCT53A/B/C
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am2952/53 and National's
29F52153 in pinout/function
• IDT29FCT52N53A equivalent to FAS"fI'M speed
The IDT29FCT52NB/C and IDT29FCT53NB/C are 8-bit
registered transceivers manufactured using advanced
CEMOSTM, a dual-metal CMOS technology. Two 8-bit backto-back registers store data flowing in both directions between
two bidirectional buses. Separate clock, clock enable and
3-state output enable signals are provided for each register.
Both A outputs and B outputs are guaranteed to sink 64mA.
The IDT29FCT52NB/C is a non-inverting option of the
IDT29FCT53NB/C.
• IDT29FCT528/538 25% faster than FAST
• IDT29FCT52C/53C 37% faster than FAST
IOL = 64mA (commercial) and 4BmA (military)
IIH and ilL only 51lA max.
CMOS power levels (2.5mW typo static)
TTL input and output level compatible
CMOS output level compatible
Available in 24-pin DIP, SOIC, 2B-pin LCCwith JEDEC
standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM(1)
cPA----------------------~
J
I
CEA
b
Ao
Do CE CP
A1 ------------1----101
A2
02
As
Os A
A4
04 Reg.
As
A6
A7
00 I-r;(-D~>----------01
02 ~
Os
04
0
[J
os~
05
06
07
06
07
II~~~
OEB
Bo
B1
B2
Bs
B4
Bs
B6
B7
00r--011------'
L.--C:C_---_-_-_-:_-_<--Jf 07
_ ___
~
06
CrE C,P 071--------------'
L--._ _ _ _ _ _ _ _ _ _ CPB
~---------------------CEB
NOTE:
1. IDT29FCT52 function is shown.
2533 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
cncn
L...J
I
I
L..J L-J L...J
4 3 2 I 128 27 26
LJ
]S
2S [
1
24[
J6
]7
23 [
, l28-1,
22 [
J8
]9
21 [
20 [
]10
19 [
] 11
12
13 14
1S 16
17 18
,...., ,.....,
,...., ,.....,
,...., ,.....,
.,-
O:J ~ gl~ ~)':
, () (!)
DIP/CERPACKl50lC
TOP VIEW
Yo
Y1
Y2
NC
Y3 '
Y4
Ys
2620 drw 02
.
LCC
TOP VIEW
REGISTER SELECTION
DEFINITION OF FUNCTIONAL TERMS
51
So
Register
On
Register input port.
0
0
82
elK
Clock input. Enter data into registers on lOWto-HIGH transitions.
0
1
8,1
1
0
A2
Instruction inputs. See Figure 1 and
Instruction Control Tables.
1
,1
A1
Pin Names
, 10,11
Description
So, 51
Multiplexer select. Inputs either register A1, A2,
81 or 82 data to be available at the output port.
OE
Output enable for 3-state output port
Yn
Register output port.
2620tbl02
2620 tbl 01
6.27
2
IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DUAL 2-LEVEL
SINGLE 4-LEVEL
c±J
[;E
1=2
2620 drw03
NOTE:
1. I = 3 for hold.
Figure 1. Data Loading In 2·Level Operation
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Und~r Bias
-55 to +125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
Conditions Typ.
Max.
Unit
Input Capacitance
VIN = OV
6
10
pF
COUT
Output Capacitance
VOUT= OV
8
12
pF
NOTE:
2620 tbl 04
1. This parameter is measured at characterization d~ta but not tested.
with Respect
toGND
TA
Parameter(1)
CIN
Symbol
NOTES:
2620 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals.
3. Outputs and 110 terminals.
6.27
3
IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Test Condltlons(l)
Symbol
VIH
Parameter
Input HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee
Guaranteed Logic HIGH Level
= Max.
Min.
2.0
-
= Vcc
VI = 2.7V
-
= 0.5V
-
VI
IlL
Input LOW Current
VI
VI=GND
-
10ZH
Off State (High Impedance) Vcc = Max.
Vo= Vcc
-
Output Current
Va
= 2.7V
VA
= 0.5V
10ZL
Va = GND
VIK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = Max.(3), Va
VOH
Output HIGH Voltage
Vcc = 3V, VIN
= GND
= VLC or VHC,
Vcc = Min.
VIN
VOL
Output LOW Voltage
IOH = -32J.lA
=-300J.lA
IOH =-12mA MIL.
IOH =-15mA COM'L.
IOH
= VIH or VIL
-
Unit
V
-
0.8
V
5
5(4)
J.lA
-
_5(4)
-5
10
10(4)
-10(4)
-
-10
-1.2
V
-60
-120
mA
VHC
Vcc
-
VHC
Vcc
2.4
4.3
2.4
4.3
GND
0.3
0.5
0.3
0.5
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM'L.
-
GND
V
VLC
VLC(4)
NOTES:
1.
2.
3.
4.
J.lA
-0.7
IOL = 300J.lA
IOL = 300J.lA
-
-
Vcc= Min.
= VLC or VHC,
Max.
-
-
-
Vcc = 3V, VIN
Typ.(2)
V
2620tbl05
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter Is guaranteed but not tested.
6.27
4
IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS VLC =
Symbol
O.2V, VHC ;.. VCC - O.2V
Test Condltlons(1)
Typ.(2)
Parameter
Quiescent Power
Supply Current
Vcc = Max.
VIN ~ VHC; VIN S;VLC
-
0.2
Max.
1.5
Unit
rnA
~Icc
Quiescent Power Supply
Current, TIL Input HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
rnA
ICCD
Dynamic Power Supply Current(4)
Vcc = Max., Outputs Open
OE= GND
One Input Toggling
50% Duty Cycle
VIN ~ VHC
VIN S; VLC
-
0.15
0.25
Vcc = Max., Outputs Open
fcp = 10MHz
50% Duty Cycle
VIN~ VHC
VIN S; VLC
. (FCT)
-
1.7
4.0
-
2.2
6.0
-
7.0
12.8(5)
-
9.2
21.8(5)
Icc
Ic
Total Power Supply Current(6)
Min.
OE=GND
VIN = 3.4V
One Bit Toggling
VIN = GND
at fi = 5MHz, 50% Duty Cycle
Vcc = Max., Outputs Open
fcp = 10MHz
50% Duty Cycle
VIN ~ VHC
VIN s; VLC
(FCT)
OE=GND
VIN = 3.4V
Eight Bits Toggling
VIN= GND
at fi = 5MHz, 50% Duty Cycle
NOTES:
1.
2.
3.
4.
5.
6.
mN
MHz
rnA
2620tbl06
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at VCC or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.27
5
IDT29FCT520AlB/C
MULTILEVEL PIPELINE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54174FCT520A
Mil.
Com'l.
Symbol
Parameter
tPHL
tPLH
Propagation Delay
ClKto Yn
tPHL
tPLH
IOT54174FCT520B
Mil.
Com'l.
IOT5417 4FCT520C
Com'l.
Condltlon(l) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2)
CL= 50pF
RL= 500n
Mil.
Max. Mln.(2) Max. Unit
2.0
14.0
2.0
16.0
2.0
7.5
2.0
8.0
2.0
6.0
2.0
7.0
ns
Propagation Delay
Soor S1 to Yn
2.0
13.0
2.0
15.0
2.0
7.5
2.0
8.0
2.0
6.0
2.0
7.0
ns
tsu
Set-up Time HIGH
or lOW On to ClK
5.0
-
6.0
-
2.5
-
2.8
-
2.5
-
2.8
-
ns
tH
Hold Time HIGH
or lOW On to ClK
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tsu
Set-up Time HIGH
or lOW 10 or 11
toClK
5.0
-
6.0
-
4.0
-
4.5
-
4.0
-
4.5
-
ns
tH
Hold Time HIGH
or lOW 10 or 11
toClK
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tPHZ
tPLZ
Output Disable Time
1.5
12.0
1.5
13.0
1.5
7.0
1.5
7.5
1.5
6.0
1.5
6.0
ns
tPZH
tPZL
Output Enable Time
1.5
15.0
1.5
16.0
1.5
7.5
1.5
8.0
1.5
6.0
1.5
7.0
ns
tw
Clock Pulse Width
HIGH or lOW
7.0
5.5
-
6.0
-
5.5
-
6.0
-
ns
-
-
8.0
NOTES:
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
2620tbl07
6.27
6
t;)
lOT49 FCTBOSIA
lOT49 FCTB06/A
FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Guaranteed low skew:
- 0.7ns (COM)
- 0.9ns (MIL)
• Very low duty cycle distortion
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1 mW typo static)
• TTL compatible inputs and outputs
• Rail-to-rail output voltage swing
• Two independent groups of buffers with 3-state control
• 5:1 fanout per group
• 'Heartbeat' monitor output
• 20-pin DIP, SOIC, SSOP (805 only), CERPACK and
LCC
• Military product compliant to MIL-STD-883, Class B
The IDT49FCT805tA and IDT49FCT806tA are clock
drivers built using advanced CEMOSTM, a dual metal CMOS
technology. The IDT49FCT805tA is a non-inverting clock
driver and the IDT49FCT806tA is an inverting clock driver.
Each device consists of two banks of drivers. Each bank
drives five output buffers from a standard TTL compatible
input. The devices feature a "heartbeat" monitor for diagnostics and PLL driving. The 805tA and 806tA offer low capacitance inputs with hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS
inputs.
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805
IDT49FCT806
OEA~
INA
~OA1-0As
INs
~081-085
OEA~
INA
5
5
~
5
~s
OEs
OEs
MON
2574 drw 03
-OA1-0A5
__
081-085
MON
2574 drw 06
CEMOS is a trademarK of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I
L-I L-I I
3
in
u
0
>
I
0
II II
I
I L-I L-I
OAs
:] 4
2 :...J 20 19
1
18[:
OB2
GNDA
:] 5
17[:
08s
15
OB4
OA4
:] 6
14
OBs
OAs
13
MON
:J 7
GNDa
]8
9
12
OEB
10
11
INB
16[:
GNDs
15[:
084
14[:
085
L20-2
9 10 11 12 13
,.....,,.....,,.....,,....., 1""""1
I
I
I
us
10
DIP/80lC/SSOP/CERPACK
TOP VIEW
II
II
II
I
« [!] [!] Z
ro
~ ~
~
LCC
TOP VIEW
2574 drw 01
2574 drw02
IDT49FCT806
« [!]
INDEX
VCCA
~1<8
0>
10
VCCB
I
OA1
2
OA2
3
OAs
4
GNOA
5
OA4
6
P20-1
020-1
8020-2
&
E20-1
OB1
18
OB2
UJ'\s
17
08s
GNDA
16
GNOB
OA4
:] 6
15
084
UJ'\s
]
GNDa
OAs
7
14
085
GNOa
8
13
MON
OEA
9
12
trEs
10
11
.INs
INA
II
II
II
II
I
I L-I L-I
L-I L-I I
19
3
8~
> p
:] 4
2:...J 20 19
1
18[:
082
:] 5
17[:
08s
L20-2
7
:J 8
16[:
GNDB
15[:
084
14[:
085
910111213
,.....,,.....,,.....,,....., 1""""1
I
II
I I
us ~
I0
II
II
I
z.[!] [!] \z
-
~ ~
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2574 drw04
2574 drw05
FUNCTION TABLE(1)
PIN DESCRIPTION
Outputs
Description
Pin Names
OEA,OEB
3-8tate Output Enable Inputs (Active LOW)
INA, INs
Clock Inputs
OAn,OBn
Clock Outputs (FCT805)
L
L
OAn,OBn
Clock Outputs (FCT806)
L
MON
Monitor Output (FCT805)
MON
Monitor Output (FCT806)
Inputs
49 FCT805
OEA,OEB INA,INB OAn,OBn
2574 tbl 05
OAn,OBn
MON
L
L
H
H
H
H
H
L
L
H
L
Z
L
Z
H
H
H
Z
H
Z
NOTE:
1. H = HIGH, L
6.2S
49FCT806
MON
L
2574tbl06
= LOW, Z = High Impedance
2
IDT49FCT805/8061A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(l)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
0.5
W
lOUT
DC Output
Current
120
120
rnA
(TA = +25°C, f = 1.0MHz)
Parameter(l}
Symbol
Conditions
Tvp.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
2574 tbl 02
NOTES:
2574tbiOt
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may
exceed Vee by +O.5V unless otherwise noted.
2. Input and Vce terminals.
3. Output and 1/0 terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLe = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to +70°C; Vee = 5.0V ± 5%, Military: TA = -55°C to +125°C; Vee= 5.0V
Sxmbol
Test Conditions(l}
Parameter
± 10%
Min.
Typ.(2}
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
-
0.8
V
5
J.tA
J.tA
J.tA
J.tA
-
-
-10
-0.7
-1.2
V
-60
-120
-
rnA
IIH
Input HIGH Current
Vee = Max.
VI = Vee
IlL
Input LOW Current
Vee = Max.
VI =GND
10ZH
Off State (High Z)
Vee = Max.
Va = Vee
-
10ZL
Output Current
Va =GND
VIK
Clamp Diode Voltage
Vee = Min., IIN= -18mA
los
Short Circuit Current
Vee = Max.(3), Vo= GND
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vee = 3V, VIN = VLe or VHe, 10H = -32J.tA
-5
10
VHe
Vee
Vee = Min.
10H = -300J.tA
VHe
Vee
VIN = VIH or VIL
IOH = -12mA MIL.
10H = -15mA COM'L.
3.6
4.3
-
10H = -24mA MIL.
IOH = -24mA COM'L.
2.4
3.8
-
-
GND
VLe
IOH = 300J.tA
GND
VLe(4)
IOL = 48mA MIL.
-
0.3
0.55
-
200
Vee = 3V, VIN = VLe or VHe, 10L= 300J.tA
Vee = Min.
VIN = VIH or VIL
V
V
10L = 64mA COM'L.
VH
-
Input Hysteresis for all inputs
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.28
-
mV
2574tbl03
3
IDT49FCT80S/8061A
FAST CMOS BUFFER/CLOCK DRIVER,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Min.
Typ.(2)
Max.
Unit
lee
Quiescent Power Supply Current
Vee = Max.
VIN = GND or Va;
-
0.2
1.5
rnA
alec
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
-
1.0
2.5
rnA
leeD
Dynamic Power Supply Current(4)
Vee = Max.
Outputs Open
OEA = OEB = GND
Per Output Toggling
50% Duty Cycle
VIN = Vee
VIN = GND
..:..
0.15
0.20
mAl
MHz
Ie
Total Power Supply Current(6)
Vee= Max.
Outputs Open
fi = 10MHz
VIN = Vee
VIN = GND
-
1.7
3.5
rnA
50%D~Cycle
VIN =3.4V
VIN =GND
-
2.2
4.8
VIN = Vee
VIN = GND
-
4.3
7.0(5)
VIN =3.4V
VIN =GND
-
5.3
9.5(5)
Symbol
-,
Test Condltlons(1)
Parameter
OEA = OEB =Vee
Mon. Output Toggling
Vee = Max.
Outputs Open
fi = 2.5MHz
50% D~ Cycle
OEA = OEB = GND
Eleven Outputs
Toggling
NOTES:
1.
2.
3.
4.
5.
6.
2574tbl04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V);all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ie = IQUIESCENT + IINPUTS + IDYNAMIC
IQ = Icc + t.lcc DHNT + ICCD (fcp/2 + fiNo)
Icc = Quiescent Current
t.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT a Number of TIL Inputs at DH
leCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep,= Clock Frequency for Register Devices (Zero for Non-Register Devices)
, fI" = Input Frequency
No = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.28
4
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SKEW CHARACTERISTICS OVER OPERATING RANGE(2)
IDT49FCT805/806
Symbol
tSK(O)
tSK(p)
tSK(t)
Parameter
Skew between two outputs of '
same package (same transition)"
Condltlon(1)
CL = 50pF
Mil.
Com'l.
Mln.(2)
Min.
Max.
Min.
Max.
-
0.7
-
0.9
-
0.7
-
1.0
-
1.1
-
-
1.5
-
1.5
-
RL = 500n
Skew between opposite transitions
(tPHL-tPLH) of same output
Skew between two outputs of
different package at same power
supply voltage and temperature .
(same transition)
IDT49FCT805A1806A
Mil.
Com'l.
Mln.(2)
.,
Max.
Unit
-
0.9
ns
1.0
-
1.1
ns
1.5
-
1.5
ns
Max.
NOTES:
2574tbJ07
1. See test circuit and waveforms.
2. Skew guaranteed across temperatLire range but measured at maximum temperature only.' Skew parameters apply to propagation delays only.
SWITCHING CHARACTERISTICS OVER OPERATING·RANGE(3)
IDT49FCT805/806
Mil.
Com't.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
INA to OAn, INs to OBn
tPZL
tPZH
Output Enable Time
OEA to OAn,
OEs to OBn
tPLZ
tPHZ
Output Disable Time
OEA to OAn,
OEs to OBn'
Condltlon(1)
CL = 50pF
IDT49FCT805A1806A
Mil.
Com't.
Min.(2)
Max.
Mln'<2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
6.5
,1.5
7.5
1.5
5.8
1.5
6.8
ns
RL = 500n
.
1.5
8.0
1.5
8.5
1.5
8.0
1.5
8.5
ns
1.5
7.0
1.5
7.5
1.5
7.0
1.5
7.5
ns
NOTES:
2574 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Propagation delay range indicated by Min. and Max. limit is due to Vee, operating temperature, and process parameters. These propagation delay limits
do not imply skew.
'
.
.
6.28
5
4L)~
Integrated Device Technology, Inc.
IDT54174FCT138
IDT54174FCT138A
IDT54174FCT138C
FAST CMOS
1-0F-8 DECODER
WITH ENABLE
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT5417 4FCT138/A/C are 1-of-8 decoders built using
advanced CEMOSTM, a dual metal CMOS technology. The
IDT54/74FCT138/A1C accept three binary weighted inputs
(Ao, A1, A2) and, when enabled, provide eight mutually
exclusive active LOW outputs (00 -07). The IDT54174FCT1381
AlC feature three enable inputs, two active LOW (E1, E2) and
one active HIGH (E3). All outputs will be HIGH unless E1 and
E2 are LOW and E3 is HIGH. This multiple enable function
allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four IDT54174FCT1381
AlC devices and one inverter.
•
•
•
•
•
•
•
•
•
IDT54/74FCT138 equivalent to FAST"'M speed
IDT54174FCT138A 35% faster than FAST
IDT54174FCT138C 40% faster than FAST
Equivalent to FAST speeds output drive over full temperature and voltage supply extremes
10L = 48mA (commercial) and 32mA (military)
CMOS power levels (1 mW typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5~ max.)
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Glass B
Standard Military Drawing # 5962-87654 is listed on this
function. Refer to section 2.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Ao
A1
A2
E1
E2
E3
07
GND
Vce
60
01
Q2
93
04
65
06
DIP/SOIC/CERPACK
TOP VIEW
<~ ~ ~IO
INDEX
L..JL_JlIWL..J
3 2
A2
E1
NC
E2
E3
2581 drw 02
]
]
]
]
]
4
5
6
7
8
I
I
Lf
20 19
18 [
01
17[ 02
L20-2
16 [
15 [
14 [
9 1011 1213
NC
03
04
,..., ,...., r-1 ,..., ,...,
""00 " ' I t )
10 ~ ZIOIO
2581 drw 01
LCC
TOP VIEW
CEMOS is a trademark 01 Integrated Device Technology, Inc.
FAST is a trademark 01 National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1992 Integrated Device Technology, Inc.
6.29
MAY 1992
DSC-462S!3
1
IDT54174FCT138/A1C
FAST CMOS 1-0F-8 DECODER-WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
Description
Arr-A2
Address Inputs
E1, E2
Enable Inputs (Active LOW)
E3
Enable Input (Active HIGH)
00-07
Outputs (Active LOW)
2581 tbl05
FUNCTION TABLE
Inputs
E1
H
X
X
L
L
L
L
L
L
L
L
E2
X
H
X
L
L
L
L
L
L
L
L
E3
X
X
L
H
H
H
H
H
H
H
H
Outputs
Ao
X
X
X
A1
X
X
X
A2
X
X
X
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
H
L
H
00
01
02
03
04
05
Os
07
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
2581 tbl 06
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
Temperature
TSIAS
Under Bias
Storage
TSTG
Temperature
PT
Power Dissipation
lOUT
DC Output Current
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
o to +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
0.5
120
0.5
120
mA
Symbol
Parameter{l)
Conditions
CIN
Input Capacitance
VIN = OV
COUT
Output Capacitance VOUT= OV
Typ. Max. Unit
6
10
pF
8
12
pF
NOTE:
2581 tbl 02
1. This parameter is guaranteed characterization data and not tested.
W
NOTES:
2581 tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vec terminals only.
3. Outputs and 110 terminals only.
6.29
2
IDT54174FCT138/A1C
FAST CMOS 1-0F-8 DECODER-WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V +
- 10%
Min.
Typ,(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logie HIGH Level
2.0
-
V
VIL
Input LOW Level
Guaranteed Logie LOW Level
-
ilH
Input HIGH Current
Vcc = Max.
~
ilL
Input LOW Current
0.8
5
5(4)
_5(4)
-1.2
Symbol
Test Condltlons(1)
Parameter
VI= 2.7V
-
VI= 0.5V
VI = GND
-
-
-
-Q.7
VI = VCC
VIK
Clamp Diode Voltage
los
Short Circuit Current
Vcc = Min., IN = -18mA
Vcc = Max.\3), Va = GND
VOH
Output HIGH Voltage
Vcc = 3V, VIN = VLC or VHC, 10H = -32~
10H =-300~
10H =-12mA MIL.
10H =-15mA COM'L.
VCC = Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
-
Vcc = 3V, VIN = VLC or VHC, IOL = 300~
VCC = Min.
10L = 300~
VIN = VIH or VIL
IOL = 32mA MIL.
10L = 48mA COM'L.
-60
-120
VHC
VCC
VHC
Vcc
-5
-
2.4
4.3
2.4
4.3
-
GND
GND
VLC
VLC(4)
0.3
0.5
0.3
0.5
-
NOTES:
1.
2.
3.
4.
V
V
rnA
V
V
2581 tbl03
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Typ.(2)
Max.
Unit
Icc
Quiescent Power Supply Current
Vee = Max.
VIN ~ VHC; VIN :;; VLC
-
0.2
1.5
rnA
f.lcc
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
-
0.5
2.0
rnA
lecD
Dynamic Power Supply Current(4)
Vee = Max.
Outputs Open
One Output Toggling
50% Duty Cycle
VIN ~ VHC
VIN:::; VLC
-
0.15
0.3
rnA/MHz
Ie
Total Power Supply Current\b)
Vee = Max.
VIN ~ VHC
VIN:::; VLC
(FCT)
-
1.7
4.5
rnA
VIN = 3.4V
VIN =GND
-
2.0
5.5
Symbol
Parameter
Test Condltlons(1)
Outputs_Op~n
Toggle El, E2 or E3
50% Duty Cycle
fo = 10MHz
One Output Toggling
Min.
NOTES:
1.
2.
3.
4.
5.
2581 tbl 04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Ie = laulEscENT + I INPUTS + IDYNAMIC
Ie = Icc + .:llcc DHNT + ICCD (fcp/2 + fONO)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fo = Output Frequency
No = Number of Outputs at fa
All currents are in milliamps and all frequencies are in megahertz.
6.29
3
IDT54174FCT138!AlC
FAST CMOS 1-0F-8 DECODER-WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54174FCT138
Mil.
Com'l.
Symbol
Parameter
tPLH
tPHL
Propajtation Delay
An to On
tPLH
tPHL
~ropa.9.atio~Delay
tPLH
tPHL
Propa,9..ation Delay
E3 to On
IOT54174FCT138A
Mil.
Com'l.
IOT54174FCT138C
Com'l.
Mil.
Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. MlnP) Max. Mln.(2) Max. MlnP) Max. Unit
CL = 50pF
RL = 500n
1.5
9.0
1.5
12.0
1.5
5.8
1.5
7.8
1.5
5.1
1.5
6.0
ns
1.5
9.0
1.5
12.5
1.5
5.9
1.5
8.0
1.5
5.2
1.5
6.1
ns
1.5
9.0
1.5
12.5
1.5
5.9
1.5
8.0
1.5
5.2
1.5
6.1
ns
E1 or E2 to On
NOTES:
2581 tbl07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.29
4
. . 1;)
'.
F~ST
CMOS DUAL
IDT54174FCT139
IDT54/74FCT139A
IDT54/74FCT139C
1·0F~4DECODER
'
.
I
Integrated Device Technology, Inc.
WITH ENABLE
FEATURES:
DESCRIPTION:
IDT54/74FCT139 equivalent to FASTrM speed
The IDT54174FCT139/A/C are duall-of-4 decoders built
using advanced CEMOSTM, a dual metal CMOS technology.
These devices have two independent decoders, each of
whi<::h accept two binary weighted inputs (Ao-A!l aQ9 provide
four mutually exclusive active LOW outputs (00-03). Each
decoder has an active LOW enable (E). When E is HIGH, all
outputs are forced HIGH.
~. IDT54/7~FCT139A 35% faster than FAST
• IDT54174FCT139C 45% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
.
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5~ max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Vee
1:a
Ea
AOa
Ala
AOb
Alb
Aoa
2
Ala
3
OOa
4
Ola
5
6
7
8
02a
03a
GND
Eb
P16-1
D16-1 14
5016-1 13
&
12
E16-1
11
10
9
AOb
Alb
OOb
alb
02b
03b
DIP/SOIC/CERPACK
TOP VIEW
2605 cnv' 01
INDEX
............. ...............
2605 cnv· 03
Ala
3 2 :...J 20 19
1
18[:
17[:
16[:
L20-2
15[:
:] 7
14[:
:] 8
10 11 12 13
:] 4
OOa :] 5
NC :] 6
AOb
ala
OOb
02a
az
Alb
NC
Olb
~ClO~.o
10
10
LCC
TOP VIEW
IB
2605 cnv' 02
CEMOS is a trade marl< of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1992 Integrated Device Technology, Inc.
6.30
MAY 1992
OSC4613/3
IDT54174FCT139!AlC
FAST CMOS DUAL 1-0F-4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE(1)
PIN DESCRIPTION
Inputs
Out outs
01
02
E
Ao
A1
H
X
X
H
H
L
L
L
L
H
H
H
L
H
L
H
L
H
L
L
H
H
H
H
H
H
L
L
H
H
00
NOTE:
Pin Names
03
Description
Address Inputs
Ao, A1
H
E
Enable Input (Active LOW)
H
H
H
00 -03
Outputs (Active LOW)
26051bl04
L
2605 tbl 05
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
(TA
Parameter(1)
= +25°C, f = 1.0MHz)
Conditions
Typ.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power
Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
mA
NOTES:
Symbol
26051bl 02
1. This parameter is measured at characterization but not tested.
2605 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
6.30
2
IDT54n4FCT1391A1C
FAST CMOS DUAL 1-QF·4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC '= Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc=5.0V ± 10%
Min.
TVp.(2)
VIH
Input HIGH Level
Guaranteed Logic HG-l Level
2.0
-
VIL
Input LOW Level
Guaranteed Logic LON Level
IIH
Input HIGH Current
Vcc = Max.
IlL
Input LOW Current
-
VIK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = Max.(3), Vo= GND
VOH
Output HIGH Voltage
Symbol
Test Condltlons{l)
Parameter
VI = Vcc
VI = 2.7V
VI = 0.5V
VI =GND
VOL
Output LOW Voltage
-
-
Max.
-
Unit
V
0.8
V
5
5(4)
JlA
-5(4)
-5
-0.7
'-1.2
V
-60
-120
rnA
Vcc = 3V, VIN = VLC or VHC, IOH = -32JlA
VHC
Vcc
-
Vcc", Min.
IOH '" -300JlA
VHC
Vcc
-
VIN = VIH or VIL
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.'4
4.3
-
Vcc = 3V, VIN = VLC or VHC, 10L = 300JlA
-
GND
VLC
VCC = Min.
-
GND
VLd 4)
IOL = 300JlA
VIN = VIH or VIL
IOL = 32mA MIL.
-
0.3
0.5
IOL = 48mA COM:L.
-
0.3
0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.30
V
V
2605 tbl 03
3
IDT54n4FCT139/A1C
FAST CMOS DUAL 1·0F·4 DECODER WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Svmbol
Icc
~Icc
ICCD
Ic
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TIL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current(6) .
VLC
= O.2V; VHC = VCC -
O~2V -
Test Condltlons(1)
Vcc;" Max.
VIN ;::: VHC' VIN S VlC
Vcc = Max.
VIN = 3.4V(3)
VIN ;:::VHC
Vcc =Max.
Outputs Open
VIN S VlC
One Bit Toggling
..
50.% Dutv Cvcle
VIN;::: VHC
Vcc= Max.
Outputs Open
VIN S VlC
(FCn
fa = 1aMHz
50.% Duty Cycle
VIN =3.4V
One Output Toggling
VIN = GND
Max.
Unit
-
0..2
1.5
rnA
-
0..5
2.0.
. rnA,
-
0..15
0..3
.'
mN
MHz
VIN;::: VHC'
VIN S VlC
(FCT)
VIN = 3.4V
VIN = GND
Vcc = Max.
Outputs Open
fa = 1aMHz
50.% Duty Cycle
One Output Toggling
on Each Decoder
TVDJ2)
Min.
-
1.7
4.5
-
2.0
5.5'
-
3.2
7.5(5)
-
3.7
9.5(5)
rnA
.
NOTES:
1.
2.
3.
4.
5.
6.
2605tb104
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + foNo)
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fo = Output Frequency
No = Number of Outputs at fo
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT139
Com'l.
Description
Parameter
tPlH
tPHl
Propagatio!!..Delay
Aoor A1 to On
tPlH
tPHl
frop~ation
Eta On
Delay
Conditlon!1)
Cl = 5o.pF
Rl = 5o.an
Mil.
IDT54n4FCT139A
. Com'l.
Mil.
IDT54174FCT139C
Com'l •
Mil.
Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Unit
1.5
9.0.
1.5 12.0.
1.5
5.9
1.5
7.8
1.5
5.0.
1.5
6.2
ns
1.5
8.0.
1.5
1.5
5.5
1.5
7.2
1.5
4.8
1.5
5.8
ns
NOTES:
9.0.
2605tbl07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.30
4
t;)®
IDT54/74FCT161/A1C
I DT54/74FCT1631AlC
FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT161 /163 equivalent to FASTTM speed
The IDT54/74FCT161/163, IDT54174FCT161N163A and
IDT54/74FCT161C/163C are high-speed synchronous modu10-16 binary counters built using advanced CEMOSTM, a dual
metal CMOS technology. They are synchronously presettable
for application in programmable dividers and have two types
of count enable inputs plus a terminal count output for versatility in forming synchronous multistage counters. The IDT54/
74FCT161/A/C have asynchronous Master Reset inputs that
override all other inputs and force the outputs LOW. The
IDT54/74FCT163/A/C have Synchronous Reset inputs that
override counting and parallel loading and allow the outputs to
be simultaneously reset on the riSing edge of the clock.
• IDT54174FCT161A/163A 35% faster than FAST
~ IDT54174FCT161A/163C 45% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• 10L = 48mA (commercial), 32mA (military)
• CMOS power levels (1mW typo static)
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5~max.)
.
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
FUNCTIONAL BLOCK DIAGRAM
Po
PE~----a-~
______________-.-;__________~________~____________~
CEP-=~~~=rlb------~--+-+------4~~----~~-----'
CET--~~~~-----------+---+~--------+-~------~+r------~-----H-.
: 163
:ONLY
04--
CP
I
DETAIL
A
DETAIL
A
DETAIL
A
Q1
Q2
Q3
I
L _____ ____ .9E!~I.!:~J
Qo
26t2 drw 01
CEMOS is a trade marl< of Integrated Device Technology. Inc.
FAST is a trademarl< of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
6.31
MAY 1992
DSC-4607/3
IDT54174FCT161/A1C, IDT5417 4FCT1631AlC
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
*R
80
Z>I-
o.
."
LJLJIILJLJ
3 2
Po
P1
NC
P2
P3
]
]
]
]
]
4
5
6
7
I I
Y
20 19
18 [
17
16
15
14
L20-2
8
[
[
[
[
00
01
NC
02
03
'"' ~;E,~~~
DIP/SOIC/CERPACK
TOP VIEW
fu
~ ~I~ tu
oc)
0
*MR for '161
2612 drw 02
LCC
TOP VIEW
*SR for '163
FUNCTION TABLE(2)
PIN DESCRIPTION
Pin Names
c...la: 0
INDEX
Vcc
TC
00
01
02
03
CET
PE
CP
Po
P1
P2
P3
CEP
GND
Description
Action on the Rising
Clock Edge(s)
SR(1)
PE
CET
CEP
Count Enable Trickle Input
L
X
X
X
Reset (Clear)
CP
Clock Pulse Input (Active Rising Edge)
H
L
X
X
Load (Pn-70n)
MR (,161)
Asynchronous Master Reset Input (Active LOW)
H
H
H
H
Count (Increment)
Synchronous Reset Input (Active LOW)
H
H
L
X
No Change (Hold)
Parallel Data Inputs
H
H
X
L
No Change (Hold)
CEP
Count Enable Parallel Input
CET
SR('163)
PO-3
PE
Parallel Enable Input (Active LOW)
00-3
Flip-Flop Outputs
TC
Terminal Count Output
NOTES:
2612tbl06
1. For FCT163/163A1163C only.
2. H = HIGH Voltage level, l = lOW Voltage level, X = Don't Care.
2612tbl05
6.31
2
IDT54174FCT161/A1C,IDT54174FCT163/A1C
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM( 3) Terminal Voltage
with Respect
toGND
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vcc
-0.5 to Vcc
(TA= +25°C, f = 1.0MHz)
Parameter(1)
Symbol
Conditions Typ.
CIN
Input Capacitance
COUT
Output Capacitance VOUT= OV
VIN = OV
Max.
10
pF
8
12
pF
NOTE:
V
Unit
6
2612 Ibl 02
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
2612tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This Is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.SV unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
C ommercla:
. IT
O° C to + 70° C , V cc= 5 . 0 V ± 5 oYc0,• MT
Iitary; T A=-5 5° C to + 1 2 5 ° C , V cc= 5 .0 V ±10%
A=
Typ.(2)
Test Condltlons(1)
Parameter
Symbol
Min.
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
I COM'L(5)
I MIL
2.0V
3.0V
Max.
-
-
-
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
IIH
Input HIGH Current
Vcc = Max.
VI = Vcc
-
VI =2.7V
III
Input LOW Current
-
-
-5
-(J.7
-1.2
-60
-120
VI =0.5V
VI=GND
VIK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = Max.(3), Vo = GND
VOH
Output HIGH Voltage
Vcc = 3V, VIN
VOL
Output LOW Voltage
=VlC or VHC, 10H = -321!A
-
VHC
VCC
Vcc= Min.
10H = -3001!A
VHC
Vcc
VIN = VIH or Vil
10H = -12mA MIL.
2.4
4.3
IOH = -15mA COM'L.
2.4
Vcc = 3V, VIN = VlC or VHC, 10l = 3001!A
Vec= Min.
10l = 3001!A
VIN = VIH or VIL
IOl = 32mA MIL.
IOl = 48mA COM'L.
V
V
0.8
V
5
5(4)
I!A
_5(4)
-
4.3
-
GND
VlC
GND
VLC(4)
-
0.3
0.5
0.3
0.5
NOTES:
1.
2.
3.
4.
S.
Unit
V
rnA
V
V
2612 tbl 03
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee ~ S.OV, +2S0C ambient and maximum loading.
Not more than one output shOUld be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
Clock pin requires a minimum VIH of 2.7V.
6.31
3
IOT54174FCT161!AlC, IOT54174FCT163!AlC
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
VLC
MILITARY AND COMMERCIAL TEMPERATURE RANGES
= O.2V, VHC = VCC -
Quiescent Power
Supply Current
Vcc = Max.
VIN ~ VHC; VIN
Alcc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max., VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
Vcc = Max., Outputs Open
Load Mode
CEP = CET = PE = GND
MR orSR = VCC
One Input Toggling
50% Duty Cycle
Vce = Max., Outputs Open
Load Mode
fcp = 10MHz
50% Duty Cyc~
CEP = CET = PE = GND
MRorSR = Vee
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
Icc
Ic
Total Power Supply Current(6)
O.2V
Typ.(2)
Max.
Unit
-
0.2
1.5
mA
-
0.5
2.0
mA
VIN ~ VHC
VIN ~ VLC
(FCT)
-
0.15
0.25
VIN ~ VHC
VIN ~ VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.2
6.0
VIN ~ VHC
VIN ~ VLe
(FCT)
-
4.0
7.8(5)
VIN = 3.4V
VIN = GND
-
5.2
12.8(5)
Test Conditlons(1)
~
Min.
VLC
Vee = Max., Outputs Open
Load Mode
fcp = 10MHz
50% Duty Cyc~
CEP = CET = PE = GND
MRorSR= Vee
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ic = Icc + .1lccDHNT + Icco(fcp!2 + fiNi)
Icc = Quiescent Current
.1lcc = Power Supply Current for a TTL High Input (VIN = 3.4 V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.31
mAl
MHz
mA
2612tbl04
4
IDT54174FCT161!AlC, IDT5417 4FCT163!AlC
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE'
IOT54174FCT161/163
Mil.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
CP to an
(PE Input HIGH)
tPLH
tPHL
Propagation Delay
CPto an
Condltlon(1)
CL= 50pF
RL= 5000.
IOT54174FCT161 A/163A
IOT54174FCT161 C/163C
Mil.
Com 'I.
MIl.
Mln.(2) Max. Mln.(2) Max. Mln,<2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.
Com'l.
Com'l.
Unit
2.0
11.0
2.0
11.5
2.0
7.2
2.0
7.5
2.0
5.8
2.0
6.3
ns
2.0
9.5
2.0
10.0
2.0
6.2
2.0
6.5
2.0
5.8
2.0
6.3
ns
(PE Input LOW)
tPLH
. tPHL'
Propagation Delay
CPto TC
2.0
15.0
2.0
16.5
2.0
9.8
2.0
10.8
2.0
7.4
2.0
8.3
ns
tPLH
tPHL
Propagation Delay
CETtoTC
1.5
8.5
1.5
9.0
1.5
5.5
1.5
5.9
1.5
5.2
1.5
5.6
ns
tPHL
Propagation Delay
MR to an (,161)
2.0
13.0
2.0
14.0
2.0
8.5
2.0
9.1
2.0
6.0
2.0
6.6
ns
. tPHL
Propagation Delay
MR to TC (,161)
2.0
11.5
2.0
12.5
2.0
7.5
2.0
8.2
2.0
7.0
2.0
7.7
ns
tsu
Set-up Time,
5.0
-.
5.5
-
4.0
-
4.5
-
4.0
-
4.5
-
ns
tH
HIGH or LOW
Pnto CP
Hold Time,
HIGH or LOW
Pn to CP
1.5
-
2.0
-
1.5
-
2.0
-
1.5
-
2.0
-
ns
11.5
-
13.5
-
9.5
-
11.5
-
9.5
-
11.5
-
ns
1.5
-
1.5
-
1.5
-
1:5
-
1.5
-
1.5
-
ns
11.5
-
13.0
-
9.5
-
11.0
-
9.5
-
11.0
-
ns
0
-
0
-
0
-
0
-
0
-
0
-
ns
tsu
Set-up Time,
HIGH or LOW
PEorSRtoCP
tH
Hold Time,
HIGH or LOW
PEorSRto CP
Set-up Time,
HIGH or LOW
CEP or CET to CP
tsu
tH
Hold Time,
HIGH or LOW
CEP or CET to CP
tw
Clock Pulse
Width (Load)
HIGH or LOW
5.0
-
5.0
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
ns
tw
Clock Pulse
Width (Count)
HIGH or LOW
7.0
-
8.0
-
6.0
-
7.0
-
6.0
-
7.0
-
ns
tw
MR Pulse Width,
LOW (,161)
5.0
-
5.0
-
4.0(3)
-
4.0(3)
-
4.0(3)
-
ns
tREM
Recovery Time
MR to CP (,161)
6.0
-
6.0
-
5.0
-
5.0
-
5.0
-
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4.d3) 5.0
-
2612 Ibl 07
6.31
5
t;)®
IDT54/74FCT182
IDT54174FCT182A
FAST CMOS
CARRY LOOKAHEAD
GENERATOR
Integrated Device Technology,lnc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT182 equivalent to FAS"fTM speed;
• IDT54/74FCT182A 30% faster than FAST
• Equivalent to FAST speeds and output drive over full
temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
The IDT54/74FCT182 and IDT54174FCT182A are highspeed carry lookahead generators built using advanced
CEMOSTM, a dual metal CMOS technology. The IDT54/
74FCT182 and IDT54/74FCT182A are carry lookahead
generators that accept up to four pairs of active LOW Carry
Propagate (Po, P1, P2, P3) and Carry Generate (Go, G1, G2, (3)
signals and an active HIGH carry input (Cn) and provides
anticipated HIGH carries (Cn+x, Cn+y, Cn+Z) across four groups
of binary adders. These products also have active LOW Carry
Propagate (P) and Carry Generate (G) outputs which may be
used for further levels of lookahead.
(5~max.)
• Carry lookahead generator
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
en
Go Po
P
PIN CONFIGURATIONS
2560 drw 02
INDEX
~-II-~
G1
P1
Go
Po
G3
P3
P
GNO
7
16
15
14
13
12
11
10
8
9
2
3
4
5
6
P16-1
016-1
S016-1
&
E16-1
VCC
Go ] 4
P2
(32
Cn
Cn+x
gn+y
G
Cn+z
Po ]
NC
]
G3 ]
P3 ]
5
6
7
3
2 I I 20 19
'1
L20-2
18 [
17 [
16 [
(32
Cn
NC
15[ Cn+x
8
14 [ C n + y
'§";E,~~~
2560 drw 01
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
CEMOS is a trademark of Integrated Devi09 Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1il1992 Integrated Devi09 Technology, Inc.
6.32
MAY 1992
DSC-462312
1
IDT54174FCT1821A'
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
Cn
Description
Carry Input
.... Garry Generate Inputs (Active LOW)
GO-G3
Po- P3
Carry Propagate Inputs (Active LOW)
. Cn+x- Cn+z
Carry OutpUts
G
Carry Generate Output (Active LOW)
P
. Carry Propagate Output (Active LOW)
2560 tbl 05
FUNCTION TABLE(1)
Outputs
Inputs
Cn
Go
Po
X
H
H
L
H
L
X
H
X
L
'X
X
H
H
H
X
X
X
H
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
L
X
X
X
H
L
L
X
X
X
X
X
L
X
X
P1
G2
G3
. P2'
P3
X
X
X
H
H
H
L
X
X
L
H
H
H.
H
X
X
X
·x
L
X
x·
x:
L
L
X
X
L
X
L
X
X
X
L
X
H
H
X
X
X
Cn+y
Cn+z
G
P
L
L
L
H
H
H
H
X
X
X
H
Cn+x
L
L
H
H
X
X
X
X
L
G1
x'
X
H
X
X
X
X
L
H
H
H
L
:X
X
X
L
'L
L
H
X
X
H
H
H
H
L
X
X
X
X
X
X
L
L
X
L
L
L
L
H
H
H
H
H
X
X
.X
X
H
X
X
X
X
H
X
H
X
X
L
L
L
H
H
H
H
L
X
X
X
X
H
X
X
X
L
L
L
X
X
X
X
X
H
L
NOTE:
1. H = HIGH Voltage Level
H
H
H
H
L
L
L
L
H
H
H
H
L
2560tbl06
L = LOW Voltage Level
X .. Don't Care
6.32
2
IDT54174FCT182/A
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
CAPACITANCE
Military
Unit
VTERM(2) Terminal Voltage
with Respect
toGND
-0.5 to +7.0 -0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect
toGND
-0.5 to Vcc
V
TA
Operating
Temperature
TSIAS
Symbol
CIN
COUT
-0.5 to Vcc
1.0MHz)
Typ. Max.
(TA = +25°C, f =
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = OV
6
10
Unit
pF
VOUT= OV
8
12
pF
NOTE:
2560 tbl 02
1. This parameter is guaranteed by characterization data and not tested.
o to +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
-65 to +150
NOTES:
2560tbiOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 110 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
C ommercla:
. I T A = 0° C to + 7 0° C V CC = 5.0 V ±5%; MT
I Ita/}': T A=-5 5° C to+ 125° C V CC= 5 OV ±
Symbol
Test Conditions(1)
Parameter
Min.
VI = 0.5V
-
VI=GND
-
-.
-
-0.7
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
IIH
input HiGH Current
Vcc = Max.
-
IlL
input LOW Current
VI = Vcc
VI = 2.7V
VIK
Clamp Diode Voltage
Vcc = Min., iN = -18mA
los
Short Circuit Current
Vcc = Max.(3), Vo = GND
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0%
Typ.(2)
-60
Max.
-
~
_5(4)
-5
-1.2
-120 .
mA
V
Vcc
VHC
vec
-
VIN = VIH or VIL
10H = -12mA MIL.
2.4
4.3
.-
10H = -15mA COM'L.
2.4
4.3
-
Vcc= Min.
IOL=300~
-
VIN = VIH or VIL
10L = 32mA MiL.
-
0.3
0.5
10L = 48mA COM'L.
-
0.3
0.5.
GND
GND
V
-
VHC
VLC
VLd 4)
NOTES:
1.
2.
3.
4.
V
5
5(4)
10H =-300~
Vcc = 3V, VIN = VLC or VHC, iOL = 300~
V
0.8
Vcc= Min.
Vcc = 3V, VIN = VLC or VHC, iOH = -32~
Unit
V
2560tbl03
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
6.32
3
IDT54174FCT182fA
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC
= O.2V; VHC = VCC -
0 2V
Min.
Typ.(2)
Max.
Unit
Icc
Quiescent Power Supply
Current
Vcc = Max.
VIN <'! VHC; VIN ::; VLC
-
0.2
1.5
mA
Alcc
Quiescent Power Supply
Current TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current(4)
Vcc = Max., Outputs Open
One Input Toggling
50% Duty Cycle
VIN <'! VHC
VIN::; VLC
-
0.15
0.3
mAl
MHz
Ic
Total Power Supply
Current(5)
Vcc = Max., Outputs Open
fi = 1OM Hz, 50% Duty Cycle
One Bit Toggling
VIN <'! VHC
VIN::; VLC
(FCT)
-
1.7
4.5
mA
VIN = 3.4V
VIN = GND
-
2.0
5.5
Symbol
Test Condltlons(1)
Parameter
NOTES:
1.
2.
3.
4.
5.
2560tbl04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcpf2 + fi Ni)
Icc =Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT =Number of TTL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5417 4FCT182
Com'l.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
Cn to Cn + x,
Cn+y,Cn+z
tPLH
tPHL
~roe..ag~ion Delay
tPLH
tPHL
f..r0~g~on Delay
tPLH
tPHL
~roe.?-g~ion Q..elay
tPLH
tPHL
f..r0pa~ation Delay
tPLH
tPHL
~ropaJ!ation Delay
Condltlons(1)
CL= 50pF
RL= 500n
IDT54174FCT182A
Com'l.
Mll.
Mll.
MlnP)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
MlnP)
Max.
Unit
2.0
10.0
2.0
16.5
2.0
7.0
2.0
10.7
ns
1.5
9.0
1.5
11.5
1.5
8.5
1.5
9.0
ns
1.5
9.5
1.5
11.5
1.5
8.5
1.5
9.0
ns
2.0
11.0
2.0
16.5
2.0
7.2
2.0
10.7
ns
2.0
11.5
2.0
16.5
2.0
7.6
2.0
10.7
ns
1.5
8.5
1.5
12.5
1.5
6.0
1.5
7.4
ns
Po, Pl, P2 to
Cn+x, Cn+y, Cn+z
Go, G1, G2to
Cn+x, Cn+y, Cn+z
Pl, P2, P3 to G
Gnto G
Pnto P
NOTES:
2560 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.32
4
(;)@
'IDT54/74FCT191
IDT54/74FCT191A'
FAST CMOS
UP/DOWN BINARY
COUNTER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT191 equivalent to FASTrM speed
• IDT54n4FCT19.1A 35% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 4BmA (commercial), 32mA (military)
• CMOS power levels (1 mW typo static)
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5JlA max.)
• JEDEC standard pinout for DIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-BB3, Class B
The IDT54/74FCT191 and IDT54/74FCT191A are
reversible modul0-16 binary counters, featuring synchronous
counting and asynchronous presetting and are built using
advanced CEMOSTM, a dual metal CMOS ~echnology. The
preset feature allows the IDT54/74FCT191 and IDT541
74FCT191 A to be used in programmable dividers. The count
enable input, terminal count output and ripple clock output
make possible a variety of methods of implementing
multiusage counters. In the counting modes, state changes
are initiated by the rising edge of the clock.
FUNCTIONAL BLOCK DIAGRAM
~
9~
P---
I
I
I
I
T
"
I
~~ ~
~
C
I~
T
1..
1
1
J CLOCK K
-(
PRESET
a
1
RC
Pa
P2
Po
CP DID
TC
CL~R
a
P-
t
1
1
a
00
a
P-
a
1
02
a
A
1°
J CLOCK K
-(
CL~R
1
I
I
"
1
01
)
'--c PRESET
L.......-
1
~
!(
I
I
J CLOCK K
1..
J CLOCK K
I
1
1
I
I
i
i
'--c PRESET
CL~R
.1
1
t")
J
1
L.......-
1
I
b-
L--
PRESET
a
1
CL~R
a
:r
L--
1
Oa
2616 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
80
1m
INDEX
Vee
OEA
TIEB
18
P20-1
D20-1
5020-2
&
E20-1
17
16
II II
L-IL-II
"DAo
D80
3
II
II
I
I ............
LJ
2
1
DAl :] 4
"DA1
D81
001 :] 5
15
14
OA2
13
D82
002
OA3
9
12
10
11
OA3
D83
DA2 :] 6
20 19
18[: "DAo
17[: D80
16[: "DA1
L20-2
15[ 081
:1 7
:1 8
14[: "DA2
9 10111213
....,....,....,...., 1""""1
I
II
II
II
II
I
Foo&l~cO
O~O
0
DIP/50lC/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54174FCT241 1244
INDEX
Vee
OEA
DAo
2
080
DAl
3
081
5
DA2
6
082
7
DAs
8
083
GND
4
TIEB*
18
P20-1
D20-1
5020-2
&
E20-1
17
'co
U
U
0
~
UUIILJU
3 2 U 20 19
OAo
D80
DA1
081 ] 5
15
14
OA2
13
D82
082 :] 7
DA3 :] 8
9
12
OA3
10
11
D83
DA2
1
:1 4
OA1
D81
16
« IUS
o
III
o 00>
:1
18[ OAo
17[
6
D80
16[: OAl
L20-2
15[: D81
14[: OA2
9 10111213
r1 r1 r1 r1 r-1
I
II
II
(') 0
III
o
DIP/50lC/CERPACK
TOP VIEW
Z
(!)
II
II
I
(') (') C\I
III « III
0 00
LCC
TOP VIEW
*OEB for 241, OEB for 244
IDT54174FCT540/541
UEA
Vee
Do
TIEB
00*
Dl
D2
INDEX
US U co
U lill
o~ 81 0 >
0
I II II
L-IL-II
U
2
3
1
01*
D3
02*
D4
03·
D5
04*
D6
05·
D7
GND
06*
II II
I
I ............
2019
18[: 00*
17[: 01·
16[: 02·
L20-2
15[ 03*
14[: 04*
9 10 11 12 13
....,.,....,...., 1""""1
I
07·
II
II
Ci ~
(!)
DIP/50lC/CERPACK
TOP VIEW
II
II
5~
LCC
TOP VIEW
"Ox for 540, Ox for 541
6.35
I
'10
0
2606 cnv· 04-09
2
IDT54174FCT240/241/244/540/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE
Pin Names
OEA,OEs
3-8tate Output Enable Inputs (Active LOW)
Description
OEA
OEB
Inputs(l)
OEB(2)
D
240
241
244
540
OES(l)
3-8tate Output Enable Input (Active HIGH)
L
L
H
L
H
L
L
H
L
Dxx
Inputs
L
L
H
H
L
H
H
L
H
Oxx
Outputs
H
H
L
X
Z
Z
Z
Z
NOTE:
1. OEB for 241 only.
NOTES:
1. H = High Voltage Level
X = Don't Care
L = Low Voltage Level
Z = High Impedance
2. OEB for 241 only.
2606tbl04
ABSOLUTE MAXIMUM RATINGS(l)
Commercial
Militarv
-0.5 to +7.0 -0.5 to +7.0
TSIAS
TSTG
lOUT
Unit
V
-0.5 to Vee
-0.5 to Vee
V
oto +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
Temperature
Power Dissipation
-55 to +125
-65 to +150
°C
DC Output
Current
0.5
0.5
W
120
120
rnA
Symbol
CIN
GoUT
Parameter
Input
Capacitance
Output
Capacitance
541
Z
2606tbl05
CAPACITANCE (TA =
Svmbol
Ratin!:l
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
Operating
TA
Temperature
PT
Outputs(l)
(1)
+25°C, f = 1.0MHz)
Conditions
VIN = OV
VOUT= OV
Typ.
6
Max.
10
Unit
pF
8
12
pF
NOTE:
2606 tbl 02
1. This parameter is measured at characterization but not tested.
NOTES:
2606 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.
6.35
3
IDT54174FCT240/241 /244/540/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = S.OV ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V ± 10%
Parameter
Input HIGH Level
Test Condltlons(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vcc = Max.
II L
Input LOW Current
Symbol
VIH
10ZH
Off State (High Impedance)
-
-
VI = GND
-
-0.7
-1.2
V
-60
-120
-
mA
Vo= 0.5V
Vo= GND
-
-
V
5
5(4)
J.l.A
-5(4)
-5
-
-
10
10(4)
-
-10(4)
-
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = Max,(3), Vo= GND
VOH
Output HIGH Voltage
Vcc = 3V, VIN = VLC or VHC, 10H = -32J.l.A
VHC
Vcc
Vcc = Min.
10H =-300J.l.A
VHC
Vcc
VIN = VIH or VIL
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
GND
VLC
GND
VLd 4)
0.3
0.55
0.3
0.55
Output LOW Voltage
Vce = 3V, VIN = VLC or VHC, 10L = 300J.l.A
Vee = Min.
10L = 300J.l.A
VIN = VIH or VIL
10L = 48mA MIL.
J.l.A
-10
Clamp Diode Voltage
10L = 64mA COM'L.
V
V
2606 tbl 03
NOTES:
1.
2.
3.
4.
0.8
VIK
VOL
Unit
V
VI = 2.7V
Vo=2.7V
10ZL
Max.
-
VI = 0.5V
Vo= Vcc
Output Current
Typ.(2)
-
VI = Vcc
Vcc = Max.
Min.
2.0
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
6.35
4
IDT5417 4FCT240/241/244/540/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =
0 2V· VHC = VCc-o 2V
Svmbol
Icc
Parameter
Quiescent Power Supply Current
dlcc
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
ICCD
Ic
Total Power Supply Current (6)
Test Condltlons(1)
Vcc =Max.
VIN ~ VHC· VIN
Vcc = Max.
VIN = 3.4V(3)
~
Min.
TvpJ2)
-
0.2
Max.
1.5
Unit
mA
-
0.5
2.0
mA
VHC
VLC
-
0.15
0.25
mAl
MHz
VIN ~ VHC
VIN ~ VLC
(FCT)
-
1.7
4.0
mA
VIN = 3.4V
VIN = GND
-
2.0
5.0
VIN ~ VHC
VIN ~ VLC
(FCT)
-
3.2
6.5(5)
-
5.2
14.5(5)
VLC
Vcc = Max.
Outputs Open
OEA = OEs =GND or
OEA=GND,
OEs = Vcc
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OEA = OEs = GND or
OEA = GND,
OEs = Vcc
One Bit Togglina
Vcc = Max.
Outputs Open
fi =5MHz
50% Duty Cycle
OEA = OEs = GND or
OEA = GND,
OEs = Vcc
Eight Bits Toggling
VIN
VIN
VIN
VIN
~
~
= 3.4V
= GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
.
All currents are in milliamps and all frequencies are in megahertz.
6.35
2606tbl06
5
IOT54174FCT240/241/244/540/541/AlC
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240{1,2)
54174FCT240
Com'l.
Symbol
tPLH
tPHL
IPZH
IPZL
IPHZ
tPLZ
Parameter
Condition
Propa~tion Delay
CL= 50pF
ON to ON
RL = 500n
54174FCT240A
Mil.
Com'l.
54174FCT240C
Mil.
Com'l.
Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.5
8.0
1.5
9.0
1.5
4.8
1.5
5.1
1.5
4.3
1.5
4.7
ns
Output Enable Time
1.5
10.0
1.5
10.5
1.5
6.2
1.5
6.5
1.5
5.8
1.5
6.5
ns
Output Disable Time
1.5
9.5
1.5
10.0
1.5
5.6
1.5
5.9
1.5
5.2
1.5
5.7
ns
2606tbl07
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT241 AND FCT244{1,2)
54174FCT241 Al244A
54174FCT241/244
Com'l.
Symbol
Parameter
tPLH
IPHL
Propagation Delay
ON to ON
tPZH
tPZL
tPHZ
tPLZ
Condition
CL = 50pF
Mil.
Com'l.
Mil.
54174FCT241 C/244C
Com'l.
Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
1.5
6.5
1.5
7.0
1.5
4.8
1.5
5.1
1.5
4.1
1.5
4.6
ns
Output Enable Time
1.5
8.0
1.5
8.5
1.5
6.2
1.5
6.5
1.5
5.8
1.5
6.5
ns
Output Disable Time
1.5
7.0
1.5
7.5
1.5
5.6
1.5
5.9
1.5
5.2
1.5
5.7
ns
RL = 50 on
2606tbl08
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT540 AND FCT541{1,2)
54174FCT540/541
Com'l.
Symbol
IPLH
IPHL
Parameter
Condition
Propagation Delay
ON to ON
CL = 50pF
IDT54/74 FCT540
RL = 500n
54174FCT540Al541A
Mil.
Com'l.
54174FCT540C/541 C
Com'l.
Mil.
Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
1.5
8.5
1.5
9.5
1.5
4.8
1.5
5.1
1.5
4.3
1.5
4.7
ns
IPLH
tPHL
Propagation Delay
ONto ON
IDT54/74FCT541
1.5
8.0
1.5
9.0
1.5
4.8
1.5
5.1
1.5
4.1
1.5
4.6
ns
tPZH
tPZL
Output Enable Time
1.5
10.0
1.5
10.5
1.5
6.2
1.5
6.5
1.5
5.8
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
9,5
1.5
10.0
1.5
5.6
1.5
5.9
1.5
5.2
1.5
5.7
ns
NOTES:
2606tbl09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.35
6
~®
Integrated Device Technology, Inc.
I DT54/74 FCT245/A/C
I DT54/74 FCT6401A/C
IDT54/74FCT645/A/C
FAST CMOS OCTAL
BIDIRECTIONAL
TRANSCEIVERS
FEATURES:
DESCRIPTION:
• IDT54/74FCT245/640/645 equivalent to FAST'M speed
The IDT octal bidirectional transceivers are built using
advanced CEMOSTM, a dual-metal CMOS technology. The
IDT54/74FCT245/A/C, IDT54/74FCT640/A/C and IDT541
74FCT645/A/C are designed for asynchronous two-way
communication between data buses. The transmiVreceive
(TiR) input determines the direction of data flow through the
bidirectional transceiver. Transmit (active HIGH) enables
data from A ports to B ports, and receive (active LOW) from B
ports to A ports. The output enable (OE) input, when HIGH,
disables both A and B ports by placing them in High-Z condition.
The IDT54/74FCT245/A/C and IDT54/74FCT645/A/C
transceivers have non-inverting outputs. The IDT541
74FCT640/A/C has inverting outputs.
•
•
•
•
•
•
•
•
•
•
•
and drive
IDT54/74FCT245A/640A/645A 25% faster than FAST
IDT54/74FCT245C/640C/645C 40% faster than FAST
TTL input and output level compatible
CMOS output level compatible
IDL = 64mA (commercial) and 48mA (military)
Input current levels only 51lA max.
CMOS power levels (2.5mW typical static)
Direction control and over-riding 3-state control
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class Band
DESC listed
Meets or exceeds JEDEC Standard 18 specifications
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
TlR
Vce
Ao
DE
A1
80
A2
As
82
A4
8s
As
As
A7
GND
8s
8s
81
84
87
DIP/SOIC/CERPACK
TOP VIEW
L.JL....JIIL.....JL....J
A2
As
] 4
] 5
A4
] S
A5
] 7
As
]
8
S 2' , 20 19
~
18 [
80
17 [
81
L20-2
lS [
82
15 [
8s
14 [
9 10 11 12 lS
84
r1 r I 1'1 11 r1
NOTES:
1. FCT245, 645 are non inverting options.
2. FCT640 is the inverting option.
LCC
TOP VIEW
2534 drw 02
CEMOS is a trademar1< of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
O
L-J
L..J'
3 2 '
D1
01
02
] 4
] 5
] 6
D2
D3
] 7
] 8
I L..J L......J
20 19
18 [
17 [
L20-2
16 [
Y
I
15 [
14 [
9 1011 1213
nnronn
"'oa..'
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 110 terminals only.
6.39
3
IDT54174FCT373/533/573/A1C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc= 5.0V ± 10%
Parameter
Input HIGH Level
Test Condltlons(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
II L
Input LOW Current
Symbol
VIH
VI = Vee
VI =2.7V
VI = 0.5V
VI =GND
Min.
2.0
-
-
Typ.(2)
-
Max.
-
Unit
V
0.8
V
5
5(4)
~
-5(4)
-5
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
los
Short Circuit Current
Vee = Max.(3) , Vo= GND
-60
-120
-
rnA
VOH
Output HIGH Voltage
Vee = 3V, VIN = VLe or VHe, 10H = -3211A
VHe
Vee
10H = -30011A
VHe
Vee
VIN = VIH or VIL
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
V
Vee = Min.
Vee = 3V, VIN = VLe or VHe, 10L = 300~
-
GND
Vee = Min.
10L = 3OO11A
-
GND
VLe
VLc'4)
VIN = VIH or VIL
10L = 32mA MIL.
-
0.3
0.5
0.3
0.5
10ZH
Off State (High Impedance)
Vee = Max.
Vo= Vee
Output Current
Vo= 2.7V
10ZL
Vo= 0.5V
Vo= GND
VOL
Output LOW Voltage
10L = 48mA COM'L.
~
-10(4)
-
-10
-0.7
-1.2
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.39
10
10(4)
V
2602tbl03
4
IDT54n4FCT373/533/573/A1C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
= O.2V; VHC = VCC - O.2V
VLC
Svmbol
Icc
~Icc
ICCD
Parameter
. Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4) .
Total Power Supply Current(6)
Ic
...
Test Condltlons(1)
Vcc = Max.
VIN ~ VHC' VIN ~ VLC
Vcc= Max.
VIN = 3.4V(3)
VIN ~VHC
Vcc = Max.
VIN ~ VLC
Outputs Open
OE=GND
One Input Toggling
50% Duty Cycle
VIN ~VHC
vcc == Max.
Outputs Open
VIN ~ VLC
(FCn
fi = 10MHz
50% Duty Cycle
VIN = 3.4V
OE=GND
VIN =GND
LE= Vcc
One Bit Toggling
VIN ~VHC
Vcc = Max.
OutpUts Open
VIN ~VLC
(FCn
fi = 2.5MHz
50% Duty Cycle
VIN = 3.4V
OE=GND
VIN = GND
LE= Vcc
Eight Bits Toggling
Min.
-
TVD.(2)
Max.
Unit
0.2
1.5
mA
-
0.5
2.0
mA
-
0.15
0.25
mN
MHz
-
1.7
4.0
-
2.0
5.0
-
3.2
6.5(5)
-
5.2
14.5(5)
NOTES:
1.
2.
3.
4.
5.
6.
mA
2602 Ibl 04
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable deVice type.
Typical values are at Vee ~ 5.0V, +25°C ambient.
Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + liN PUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.39
5
IOT54174FCT373!533!573!AlC
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT373/A1C/FCT573/A/C
FCT373A1573A
FCT373!573
Com'I.<2)
Symbol
Parameter
tPLH
tPHL
Propagation Delay
ONto ON
tPLH
tPHL
tPZH
tPZL
Propagation Delay
LE to ON
Output Enable Time
tPHZ
tPLZ
Output Disable Time
tsu
Set-up Time HIGH
or LOW ON to LE
tH
Hold Time HIGH
or LOW, ON to LE
tw
LE Pulse Width HIGH
Conditlons(1)
CL= 50pF
MilP)
Com'I.(2)
FCT373C!573C
MiI.(2)
Com'I.(2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
MilP)
Min. Max. Unit
1.5
8.0
1.5
8.5
1.5
5.2
1.5
5.6
1.5
4.2
1.5
5.1
ns
2.0
13.0
2.0
15.0
2.0
8.5
2.0
9.8
2.0
5.5
2.0
8.0
ns
1.5
12.0
1.5
13.5
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5
7.5
1.5
10.0
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
6.0
-
6.0
-
5.0
-
6.0
-
5.0
-
6.0
-
RL = 500n
ns
2602tb108
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533/A1C
. FCT533A
FCT533
Com'I.<2)
Symbol
Parameter
Propa~tion
tPLH
tPHL
ON to ON
tPLH
tPHL
Propa.9..ation Delay
LEta ON
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
tsu
Set-up Time HIGH
or LOW, ON to LE
tH
Hold Time HIGH
or LOW, ON to LE
LE Pulse Width HIGH
tw
Delay
Output Disable Time
Condltlons(1)
CL= 50pF
MilJ2)
Com'I.l2)
FCT533C
MilJ2)
Com'I.<2)
MiI.<2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.5
10.0
1.5
12.0
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
ns···
2.0
13.0
2.0
14.0
2.0
8.5
2.0
9.8
2.0
6.9
2.0
8.0
ns
1.5
11.0
1.5
12.5
1.5
6.5
1.5
7.5
1:5
5.5
1.5
6.3
ns
1.5
7.0
1.5
8.5
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
6.0
-
6.0
-
5.0
-
6.0
-
5.0
-
6.0
-
RL = 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
ns
2602 tbl 09
6.39
6
G
I DT54/74 FCT374/A/C
I DT54/74 FCT5341A/C
I DT54/74 FCT574/A/C
FAST CMOS OCTAL D
REGISTERS (3-STATE)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT374/534/574 equivalent to FASTTM speed
and drive
• IDT54174FCT374A/534A/574A up to 30% faster than
The IDT54/74FCT374/A/C, IDT54/74FCT534/A/C and
IDT54/74FCT574/AIC are 8-bit registers built using advanced
CEMOSTM, a dual metal CMOS technology. These registers
consist of eight D-type flip-flops with a buffered common clock
and buffered 3-state output control. When the output enable
(OE) is LOW, the eight outputs are enabled. When the OE
input is HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the a outputs on the LOW-toHIGH transition of the clock input.
The IDT54174FCT37 4/AlC and IDT54174FCT574/AI C have
non-inverting outputs with respect to the data at the D inputs.
The IDT54174FCT534/AIC have inverting outputs.
FAST
• IDT54174FCT374C/534C/574C up to 50% faster than
FAST
• 10l = 48mA (commercial) and 32mA (military)
• CMOS power levels (1 mW typo static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common threestate control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574
00
01
02
03
04
Os
06
07
2603 cnv' 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
00
01
02
03
04
Os
06
07
2603 cnv· 02
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0
Vee
L..J L-J I
07
D7
D6
06
05
D5
D4
04
CP
I L-J L....J
3 2 : : 20 19
18
l'
17
L20-2
16
15
14
9 10 11 1213
. , r I . , . , r-1
D1 ] 4
01 ] 5
02 ] 6
D2 ] 7
D3 ] 8
[
[
[
[
[
D7
D6
06
05
D5
2535 drw 01
"'oa.'0
2559 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
O
~
L..J
'--'11'--'
1 1 20
3 2
lOA
11A
NC
11B
108
] 4
L..J
19
L..J
1
] 5
18 [
L20-2
16 [
15 [
] 8
14 [
9 1011 12 13·
] 6
] 7
",..,,,,..,,,
NC
11c
loc
2559 drw 02
cocoa.:o
DIP/SOIC/CERPACK
TOP VIEW
100
17[ 110
O ZzoO
C!J
LCC
TOP VIEW
FUNCTION TABLE(1)
PIN DESCRIPTION
Inputs
Description
Pin Names
' Outputs
5
Common Select Input
5
10
11
CP
Clock Pulse Input (Active Rising Edge)
I
I
X
L
100-loD
Data Inputs from Source 0
I
h
X
H
!lA-I1D
Data Inputs from Source 1
h
X
I
L
QA-QD
Register True Outputs
h
X
h
H
2559 tbl 03
LOGIC SYMBOL
lOA
Q
NOTE:
2559 tbl 04
1. H .. HIGH Voltage Level
L ~ LOW Voltage Level
h .. HIGH Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition
X = Immaterial
S
CP
QA
Qs
Qe
QD
2559 drw 03
6.42
2
IDT54174FCT399!AlC
FAST CMOS QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
Unit
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
VTERM(2) Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect
toGND
-0.5 to Vcc
-0.5 to Vcc
V
Conditions Typ.
VIN =OV
6
VOUT= OV
Max.
Unit
10
pF
12
pF
8
NOTE:
2559 tbl 02
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
NOTES:
2559 tbl 01
1. Stresses greater
than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No termi nal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vec terminals only.
3. Outputs and 110 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Typ.(2)
Test Conditions(1)
Symbol
Parameter
Min.
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
VIL
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
Vcc = Max.
5
5(4)
~
IlL
Input LOW Current
-
0.8
IIH
-
VI = Vcc
VI = 2.7V
VI = 0.5V
VI = GND
-
VIK
Clamp Diode Voltage
Vce = Min., IN = -18mA
los
Short Circuit Current
Vee = Max.(3), Vo = GND
VOH
Output HIGH Voltage
Vee = 3V, VIN = VLC or VHC, 10H = -32~
VOL
Output LOW Voltage
-60
-0.7
_5(4)
-5
-1.2
-120
-
-
VHC
VCC
Vee = Min.
10H =-300~
VHC
Vcc
VIN = VIH or VIL
10H =-12mA MIL.
2.4
4.3
IOH = -15mA COM'L.
2.4
4.3
-
GND
VLC
GND
V Lc'4)
0.3
0.5
0.3
0.5
Vee = Min.
IOL = 300~
VIN = VIH or VIL
10L = 32mA MIL.
-
10L = 48mA COM'L.
-
Vee = 3V, VIN = VLC or VHC, 10L = 300~
V
mA
V
-
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short cirCUit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.42
V
V
2559 tblOS
3
IDT54174FCT399!AlC
FAST CMOS QUAD DUAL·PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
Parameter
Symbol
Test Condltlons(1)
Min.
Typ.(2)
Max.
Unit
Icc
Quiescent Power Supply
Current
Vcc = Max.
VIN ~ VHC; VIN s VLC
-
0.2
1.5
rnA
L\lcc
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
-
0.5
2.0
rnA
ICCD
Dynamic Power Supply
Current(4)
VCC= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
VIN ~ VHC
VIN S VLC
-
0.15
0.25
mAl
MHz
Ic
Total Power Supply
Current(6)
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
One Bit Toggling
atfi =5MHz
50% Duty Cycle
S = Steady State
VIN ~ VHC
VIN S VLC
(FCT)
-
1.7
4.0
rnA
VIN = 3.4V
VIN = GND
-
2.2
6.0
VCC= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
Four Bits Toggling
atfi = 5MHz
50% Duty Cycle
S = Steady State
VIN ~ VHC
VIN S VLC
(FCT)
-
4.0
7.8(5)
VIN = 3.4V
VIN = GND
-
5.2
12.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN =3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + liN PUTS + IDYNAMIC
Ic = Icc + L\lcc DHNT + ICCD (fCP!2 + fNi)
Icc c Quiescent Current
.
~Icc ,;, Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.42
2559 tbl 06
4
IDT54n4FCT399/A1C
FAST CMOS QUAD DUAL·PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54f74FCT399
Condltlon(1)
IDT54n4FCT399A
IDT54174FCT399C
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Mln.l2) Max. Mln.(2) Max. Mln.(2) Max. Mln.l2) Max. Mln.(2) Max. Mln.(2) Max.
Symbol
Parameter
tPLH
tPHL
Propagation Delay
CP to On
tsu
Set-up Time
HIGHorLOW
In to CP
4.0
-
4.S
tH
Hold Time
HIGH or LOW
IntoCP
1.0
-
1.5
tsu
Set-up Time
HIGH or LOW
StoCP
9.0
-
9.5
-
8.5
-
9.0
-
8.S
-
tH
Hold Time
HIGH or LOW
0
-
0
-
0
-
0
-
0
5.0
-
7.0
-
S.O
-
6.0
-
S.O
CL= SOpF
RL= soon
3.0
10.0
3.0
Unit
2.S
7.0
2.S
7.S
2.S
6.1
2.S
6.6
ns
-
3.S
-
4.0
-
3.S
-
4.0
-
ns
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
9.0
-
ns
-
0
-
ns
-
6.0
-
ns
11.S
:
StoCP
tw
CP Pulse Width
HIGH or LOW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2559tbl07
6.42
5
(;)
I DT54/74FCT521
FAST CMOS 8-BIT
IDENTITY COMPARATOR
IDT54/7 4FCT521 A
IDT54/74FCT521 B
IDT54/74FCT521C
Integrated Device Technology. Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B
IDT54/74FCT521 equivalent to FASrm speed
IDT54174FCT521A 35% faster than FAST
IDT54174FCT521B 50% faster than FAST
IDT54174FCT521C 60% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
10L = 48mA (commercial), and 32mA (military)
CMOS power levels (1 mW typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5/lA max.)
DESCRIPTION:
The IDT5417 4FCT521 IA/B/C are 8-bit identity comparators
built using advanced CEMOSTM, a dual metal CMOS technology. These devices compare two words of up to eight bits each
and provide a LOW output when the two words match bit for
bit. The expansion input IA = B also serves as an active LOW
enable input.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Vce
IA=B
Ao
80
A1
81
A2
82
A3
83
GND
19
18
17
2
3
4
5
6
7
8
9
10
OA=B
87
A7
86
A6
85
P20-1
020-1 16
S020-2 15
&
14
13
12
11
E20-1
As
84
A4
OA=B
DIP/SOIC/CERPACK
TOP VIEW
INDEX
2604 drw 01
CD
~
CD
0
<"
.... , .. .
~:=t>h
o
"
«.oS
L-I L-I •
2604 drw03
A1
81
A2
82
A3
>0 1°
"•
L-I L-I
3 2 L.: 20 19
1
18[:
:1 4
17[:
:1 5
16[:
L20-2
:16
15[:
:] 7
14[:
:] 8
9 10 11 12 13
87
A7
86
A6
85
......, ......, ......, ......, r - t
I II II I I I I
I
2604 drw 02
LCC
TOP VIEW
CEMOS is a trademark of Integrated Oevioe Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
VHC' VIN ::; VLC
Vcc = Max.
VIN = 3.4V(3)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + illcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
illcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
2604 tbl' 04
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT521
Com'l.
Symbol
Mil.
IDT54n4FCT521A
IDT54n4FCT521B
IDT54n4FCT521C
Com'l.
Com'l.
Com'l.
Mil.
Mil.
Mil.
Parameter Conditlon!l) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln,<2) Max.
tPLH
tPHL
Propagation CL= 50pF
Delay
RL = soon
An or Bn to
OA=B
tPLH
tPHL
Propagation
Delay
IA = B to
OA=B
1.5
11.0
1.5
1.5
10.0
1.5
Unit
15.0
1.5
7.2
1.5
9.5
1.5
5.5
1.5
7.3
1.5
4.5
1.5
5.1
ns
9.0
1.5
6.0
1.5
7.8
1.5
4.6
1.5
6.0
1.5
4.1
1.5
4.5
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2604 tbl' 07
6.43
4
~®
IDT54/74FCT543
IDT54/74FCT543A
IDT54174FCT543C
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
Integrated DevlceTechnology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54/74FCT543/A1C is a non-inverting octal transceiver built using advanced CEMOSTM, a dual metal CMOS
technology. These devices contain two sets of eight D-type
latches with separate input and output controls for each set.
For data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from Ao-A7
or to take data from Bo-B7, as indicated in the Function Table.
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the 3-state B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses the CEBA, LEBA and OEBA inputs.
•
•
•
•
•
•
•
•
•
IDT54/74FCT543 equivalent to FAST"M speed
IDT54n4FCT543A 25% faster than FAST
IDT54n4FCT543C 40% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
IOL= 64mA(commercial), 48mA (military)
Separate controls for data flow in each direction
Back-to-back latches for storage
CMOS power levels (1 mW typo static)
Substantially lower input current levels than FAST
(5J..LA max.)
TTL input and output level compatible
CMOS output level compatible
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
r---------------------------------------------------,
DETAIL A
o Q
~------------~~80
LE
Ao-+~~+-----------~
I
IL _______________ _
A1
A2
A3
A4
81
82
83
DETAIL Ax 7
.84
As
8s
A6
A7
86
87
OE8A - - - - - - - < I
1:)-------
OEA8
CE8A----~-d~~--_+------------------~
LE8A
~
__________________
_r~~~---CEA8
LEA8
2614 dlW 01
CEMOS Is a trademark of Integrated Device Technology, Inc.
FAST Is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1992 Integrated Device Technology, Inc.
6.44
MAY 1992
050-460213
1
IDT54174FCT543/A1C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
24
23
22
P24-1, 21
024-1, 20
S024-2
19
&
18
E24-1
17
16
LEBA
OEBA
Ao
A1
A2
A3
A4
As
A6
A7
CEA8
GND
10
11
12
VCC
~
CEBA
Bo
B1
82
83
84
Bs
86
B7
LEA8
OEA8
lS
14
13
A1
A2
A3
NC
A4
As
A6
L....J
L......JL..-II
~
1
]7
J8
L28-1
]9
] 10
] 11
12 13 14 lS 16 17 18
81
B2
B3
NC
B4
B5
86
LCC
TOP VIEW
FUNCTION TABLE (1,2)
PIN DESCRIPTION
For A-to-8 (Symmetric with 8-to-A)
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEAB
CEBA
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
ArrA7
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
2614 Ibl 02
LOGIC SYMBOL
Latch
Status
Inputs
LEAB
BrrB7
25 [
24[
23 [
22 [
21 [
20 [
19 [
2614 drw 02
DIP/SOIC/CERPACK
TOP VIEW
Pin Names
"-
IL....JL....JL....J
4 3 2 11282726
]5
J6
LEAB
OEAB
A-to-B
H
-
-
Storing
-
H
-
Storing
-
H
-
Output
Buffers
Bo-B7
HighZ
HighZ
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous· A Inputs
NOTES:
26141blOl
1.· Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
- = Don't Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.
LEAB CEAB CEBA LEBA
Ao
Bo
A1
B1
A2
B2
A3
B3
A4
B4
As
Bs
A6
86
A7
OEBA
B7
OEAB
2614 drw 03
6.44
2
rI
•
IDT54174FCT543/A1C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
CAPACITANCE (TA= +25°C, f =
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
Conditions Typ.
CIN
Input Capacitance
VIN = OV
6
10
pF
Cvo
110 Capacitance
VOUT = OV
8
12
pF
Max.
Unit
NOTE:
2614 tbl 04
1. This parameter is guaranteed by characterization data and not tested.
with Respect
to GND .
TA
1.0MHz)
Parameter(1)
Symbol
NOTES:
2614tbl03
1. Stresses greater than those listed' under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to .the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vcc terminals only ..
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
. Following Conditions Apply Unless Otherwise Specified: VLC ... O.2V, VHC = VCC - O.2V
Commercial: TA O°C to +70°C,Vcc ... 5.0V +
- 5%; Military: TA";' -55°C to +125°C, Vcc = 5.0V
=
Symbol
Test Condltlons(1)
Parameter
Typ.(2)
-
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
-
IlL
IIH
ilL
VI = Vec
(Except 110 pins)
VI = 2.7V
Input LOW Current
VI
(Except 110 pins)
VI=GND
Input HIGH Current
Vec= Max.
VI
= 0.5V
= Vee
(110 pins Only)
VI =2.7V
Input LOW Current
VI
(110 pins Only)
VI=GND
= O.5V
VIK
Clamp Diode Voltage
Vee .. Min., IN = -18mA
los
Short Circuit Current
Vee = Max.(3), Vo = GND
VOH
Output HIGH Voltage
Vee = 3V, VIN = VLe or VHe, IOH = -32~ .
VOL
Output LOW Voltage
+
- 10%
Min.
-
-
-15(4)
~
-
-15
-
-{).7
-1.2
V
-120
-
rnA
VLC
V Lc\4J
V
GND
0.3
0.55
0.3
0.55
4.3
2.4
IOL= 48mA MIL.(5)
IOL ... 64mA COM'L.(5)
-5
-60
2.4
VIN = VIH or VIL
~
-
10H = -15mA COM'L.
IOL=300~
~
~
10H = -12mA. MIL.
Vec= Min.
V
5
5(4)
15
15(4)
Vee
Vcc .. 3V, VIN = VLC or VHC, 10L ... 300~
V
0.8
_5(4)
Vec
VIN = VIH or VIL
Unit
-
VHe
IOH=-300~
-
-
VHC(4)
Vcc ... Min.
Max.
-
-
4.3
GND
V
NOTES:
2614 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is S12mA for commercial and 384mA
for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.
6.44
3
IDT54174FCT543/A1C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Icc
Quiescent Power
Supply Current
Alcc
ICCD
QuJescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
Ic
Total Power Supply Current(6)
VLC
= O.2V; VHC = VCC -
O.2V
Test Condltlons(1)
Vcc = Max.
VIN ~ VHC; VIN s VLC
Vcc = Max., VIN = 3.4V(3)
Min.
Typ.(2)
Max.
Unit
-
0.2
1.5
mA
-
0.5
2.0
mA
Vcc = Max., Outputs Open
CEAB and OEAB = GND
CEBA= Vcc
One Input Toggling
50% Duty Cycle
VIN ~ VHC
VIN s VLC
-
0.15
0.25
mAl
MHz
Vcc = Max., Outputs Open
fcp = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA= Vcc
One Bit Toggling
atfi = 5MHz
50% Duty Cycle
VIN ~ VHC
VIN s VLC
(FCT)
-
1.7
4.0
rnA
VIN = 3.4V
VIN = GND
-
2.2
6.0
Vcc = Max., Outputs Open
fcp = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA= Vcc
Eight Bits Toggling
atfi = 5MHz
50% Duty Cycle
VIN~
VHC
VIN::;; VLC
(FCT)
-
7.0
12.8(5)
VIN = 3.4V
VIN = GND
-
9.2
21.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IOYNAMIC
Ic = Icc + ;llcc DHNT + Icco(fcp/2 + fiNi)
Icc = Quiescent CUrrent
;llcc = Power Supply Current for a TTL High Input (VIN = 3.4 V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.44
2614 tbl 06
4
IDT54174FCT543/A1C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT543
Com'l.
Svmbol
Parameter
tPLH
Propagation Delay
Transparent Mode
tPHL
MIL
IDT54174FCT543A
Corn'l.
MIL
IDT54174FCT543C
Com'l.
MIL
Condltlon(1) Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. MinP) Max. Unit
2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns
CL= 50pF
RL =
soon
An to Bn or Bn to An
tPLH
tPHL
Propagation Delay
LEBA to An, LEAB to Bn
2.5
12.5
2.5
14.0
2.5
8.0
2.5
9.0
2.5
7.0
2.5
8.0
ns
tPZH
tPZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2.0
12.0
2.0
14.0
2.0
9.0
2.0
10.0
2.0
8.0
2.0
9.0
ns
tPHZ
tPLZ
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2.0
9.0
2.0
13.0
2.0
7.5
2.0
8.5
2.0
6.5
2.0
7.5
ns
tsu
Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB
3.0
-
3.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
tw
LEBA or LEAB Pulse Width
LOW
5.0
-
5.0
-
5.0
-
5.0
-
5.0
-
5.0
-
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2513tbl07
6.44
5
G@
FAST CMOS OCTAL
TRANSCEIVER/REGISTER
IDT54n4FCT646
IDT54n4FCT646A
IDT54n4FCT646C
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
IDT54/74FCT646 equivalent to FAST'IM speed;
IDT54174FCT646A 30% faster than FAST
IDT54174FCT646C 40% faster than FAST
Independent registers for A and B buses
Multiplexed real-time and stored data
IOL = 64mA (commercial) and 4BmA (military)
CMOS power levels (1 mW typical static)
TIL input and output level compatible
CMOS output level compatible
Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,
CERPACK and 2B-pin LCC
• Product available in Radiation Tolerant and Radiation
Enhanced Versions
• Military product compliant to MIL-STD-BB3, Class B
The IDT54174FCT6461A1C consists of a bus transceiver
with 3-state D-type flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the data bus or
from the internal storage registers.
The IDT54174FCT6461A1C utilizes the enable control (<3)
and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and realtime data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus or both can be stored in the
internal D flip flops by LOW-to-H IGH transitions at the
appropriate clock pins (CPAB or CPBA)· regardless of the
select or enable control pins.
•
•
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
G----e-a-~
DIR
--'---L---.J
CPBA--------r-----------~~----_;~
SBA---------+-----~
CPAB
SAB------+~-~
1 OF 8 CHANNELS
BREG
-
l
~-------------~y~---------------~
TO 7 OTHER CHANNELS
2536 drwOl
CEMOS Is a trademark 01 Integrated Device Technology, Inc.
FAST is a !rademark 01 National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11)1992 Integrated Device Technology, lno.
6.45
MAY 1992
DSC0462&12
1
IDT54n4FCT646fAlC
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
[Xl
CPA8
SA8
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
Vcc
CP8A
S8A
OU)
WL....IwllL....IL....IW
4 3211282726
A1
A2
A3
NC
A4
A5
A6
G
81
82
83
84
85
86
87
88
J5
J6
J7
J8
J9
L-J
1
L28-1
]10
J11
25 [
24[
23 [
22 [
21 [
20 [
19 [
G
81
82
NC
83
84
85
12 13 14 15 16 17 18
r I ,--, . , r-1 r I r-1 . ,
r--alClOalr--(O
>->-
Yo
Y1
Y2
Ys
Y4
Ys
Ye
Y7
Ys
Y9
CP
1111
II
I111111
~ ~ ~ ~1 2a272s
:]5
25[:
:]6
24[:
:]7
23[:
:]8
L28-1
22 [:
:J9
21 [:
:]10
20[:
:]11
19[:
12131415161718
D4 D Q~10
10
Y2
Y3
Y4
NC
Ys
Ye
Y7
CP
CP----'
I
Y
I
OE------.....I
nnnnnnn
88~~~~~
C!)
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv' 03
IDT54n4FCT823/824 9-81T REGISTERS
Vee
OE
Do
D1
D2
D3
D4
Ds
Ds
07
Os
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
Ys
ern
EN
GNO
CP
INDEX
,,-ofou80..-
OOOz»>-
IllillllUUU
~ 't 282726
:]5
25[:
D3 :]6
24[:
D4 :]7
23[:
NC :]8
22[:
L28-1
Ds :]9
21[:
Os :]10
20[:
:]11
19[:
12131415161718
1
Y2
Y3
Y4
NC
Ys
Ys
Y7
D
Y
CP
EN
CLR
OE
815~
~ ~\dj ~
uc!)
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
2608 cnv' 04
IDT54n4FCT825 8-81T REGISTER
OE1
OE2
Do
01
02
03
04
Os
De
07
CLR
GND
Vee
OE3
Yo
Y1
Y2
Y3
Y4
Ys
Ye
Y7
EN
CP
DIP/SOIC/CERPACK
TOP VIEW
INDEX
0
Y1
Y2
Ys
NC
Y4
Ys
Ye
Y
CP
EN
CLR
OE1
OE2
OE3
o III:....IZ
0
uc!)
Z )::
u~ IW
Z
LCC
TOP VIEW
6.46
2608 cnv' 05
2
IDT54n4FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
-IDT54/74FCT821 /823/825
PRODUCT SELECTOR GUIDE
Device
I Non-inverting
10·Blt
9·Blt
I Inverting
5417 4FCT824A1B1C
2608 tbl 01
PIN DESCRIPTION
Name
I/O
01
I
CLR
I
CP
I
YI,YI
0
EN
I
OE
I
InternaU
Inputs
a·Blt
54174FCT821A1B1C 5417 4FCT823A1B1C 54174FCT825A1B1C
Descrlctlon
The D flip-flop data inputs.
For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the 01 outputs are
LOW. When the clear input is HIGH,
data can be entered into the reoister.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.
The register three-state outputs.
Out~uts
OE
CLR
EN
DI
CP
QI
VI
'H
H
H
H
L
L
L
H
i
i
L
H
Z
Z
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
'X
X
X
X
X
X
X
X
L
L
NC
NC
L
H
i
i
L
t
H
i
Z
L
Z
NC
Z
Z
L
H
H
H
L
L
L
L
L
I-
H
L
H
NOTE:
Function
HighZ
Clear
Hold
Load
2608 tbl 02
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, t = LOW-to-HIGH
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54174FCT824
Clock Enable. When the clock enable
is LOW, data on the DI input is
transferred to the 01 output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the 01
outputs do not change
state,
regardless of the data or clock input
transitions.
Output Control. When the OE input is
HIGH, the YI outputs are i~he high
impedance state. When the OE input is
LOW, the TRUE register data is
present at the YI outputs.
-lnternaU
Inputs
2608 tbl 01
Out~uts
-OE
CLR
EN
DI
CP
QI
VI
H
H
H
H
L
L
L
H
i
i
H
L
Z
Z
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X __
X
X
X
X
X
L
H
L
H
i
i
i
i
L
L
NC
NC
H
L
H
L
Z
L
Z
NC
Z
Z
H
L
NOTE:
H
H
L
L
L
L
.
Function
HighZ
Clear ,.
Hold
Load
2608 tbl 03
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, t = LOW-to- ;
HIGH Transition, Z = High Impedance
6.46
3
IDT54174FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
Ratlna
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vcc
-0.5 to Vcc
V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Symbol
Conditions
TvP.
Max.
Unit
CIN
Input
Capacitance
VIN = OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
NOTES:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
TA
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
Commercial: TA = 0° C to +70° C , VCC = 5.0V + 5%; M'II itary: T A =-55° C to +125° C , Vcc= 5.0 V ±10%
Min.
TypJ2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
Vil
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vcc .. Max.
III
Input LOW Current
VI =0.5V
-
VI=GND
-
Va .. Vcc
-
-0.7
Symbol
Test Condltlons(1)
Parameter
VI .. VCC
VI = 2.7V
Max.
-
V
0.8
V
5
5(4)
f.l.A
-5(4)
-5
VIK
Clamp Diode Voltage
Vcc .. Min., IN .. -18mA
-
los
Short Circuit Current
Vcc = Max,<3), Va = GND
-75
-120
-
rnA
VOH
Output HIGH Voltage
Vcc
VHC
Vcc
-
V
VHC
Vcc
-
-
10ZH
Off State {High Impedance}
Vcc .. Max.
Vo=2.7V
Output Current
VO= 0.5V
10Zl
Vo=GND
Val
Output LOW Voltage
=3V, VIN = VlC or VHC, 10H =-32f.l.A
10
-
10(4)
-
-10(4)
-
10H =-300f.l.A
VIN = VIH or Vil
10H = -15mA MIL.
2.4
4.3
10H = -24mA COM'L.
2.4
4.3
Vcc .. 3V, VIN = VlC or VHC, 10l .. 300JlA
-
GND
VlC
Vcc .. Min.
10l =300f.l.A
-
GND
VlC(4)
10l .. 32mA MIL.
-
0.3
0.5
0.3
0.5
10l =48mA COM'L.
f.l.A
-10
-1.2
Vcc .. Min.
VIN .. VIH or Vil
NOTES:
1.
2.
3.
4.
Unit
V
V
2608 tbl 06
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vce • 5.0V, +25°C ambient and maximum loading.
Not more than one output shOUld be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
6.46
4
IOT54174FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
~mbol
lee
~Iec
leeD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Test Condltlons(1)
Vcc = Max.
VIN ~ VHC' VIN ~ VLC
Vcc = Max.
VIN = 3.4V(3)
Vec = Max.
Outputs Open
OE .. EN .. GND
VIN ~ VHC
VIN ~ VLC
Tvp'(2)
Max.
Unit
-
0.2
1.5
mA
-
0.5
2.0
mA
0.15
0.25
Min.
mAl
MHz
One Input Toggling
50% Duty Cycle
Ic
Total Power Supply Current(6)
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE= EN = GND
One Bit Toggling
atf 1= 5MHz
50% Duty Cycle
VIN ~VHC
VIN S VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.2
6.0
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE= EN =GND
VIN ~ VHC
VIN ~ VLC
(FCT)
-
4.0
7.8(5)
VIN = 3.4V
VIN = GND
-
6.2
16.8(5)
Eight Bits Toggling
at f i = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ..ilcc DHNT + ICCD (fcp/2 + fiN i)
Icc = Quiescent Current
..ilcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.46
mA
2608 tbl 07
II
5
IDT54114FCT821/823/824/825A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
,
Test
.Description
Parameter
tPLH.
tPHL'
Propagation Delay
CP to V I (OE = LOW)
CondIUons(1)
CL= SOpF
tsu
Set-up Time HIGH or LOW
DltoCP
IDT54174FCT821 BI
823A1824A1825A
823B/824B/825B
Com'l.
Mil.
Com'l.
IDT54174FCT821CI
823C1824C1825C
Mil.
Com'l.
Mil.
Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max. Mln.(2) Max.
soon
-
10.0
-
11.S
-
7.S
-
8.S
-
6.0
-
7.0
soon
-
20.0
-
20.0
-
1S.0
-
16.0
-
12.S
-
13.S
RL ...
CL = 300pF(3)
RL ...
IDT54174FCT821AI
CL .. SOpF
RL ...
Unit
ns
4.0
-
4.0
-
3.0
-
3.0
-
3.0
-
3.0
-
ns
Hold Time HIGH or. LOW
D ItoCP
2.0
-
2.0
-
1.S
-
1.S
-
1.S
-
1.S
-
ns
tsu
Set-up Time HIGH or LOW
EN to cpo
4.0
-
4.0
-
3.0
-
3.0
-
3.0
-
3.0
-
ns
tH
Hold Time HIGH or,LOW
EN to CP
Propagation Delay, CLR to
2.0
-
2.0
-
0
-
0
-
0
-
0
-
ns
-
9.0
-
9.5
-
8.0
-
8.S
ns
. tH
tPHL
soon
VI
-
tREM
Recovery Time CLR to CP
6.0
-
7.0
-
6.0
-
6.0
-
6.0
-
6.0
-
ns
m
7.0
-
7.0
-
6.0
-
6.0
-
6.0
-
6.0
-
ns
m
CP Pulse Width
HIGH or LOW
CLR Pulse Width
6.0
-
7.0
-
6.0
-
6.0
-
6.0
-
6.0
-
ns
tPZH
tPZL
LOW
Output E~able Time OE
to VI
-
12.0
-
13.0
-
8.0
-
9.0
-
7.0
-
8.0
ns
-
23.0
-
2S.0
-
1S.0
-
16.0
-
12.S
-
13.S
-
7.0
-
8.0
-
6.S
-
7.0
-
6.2
-
6.2
-
8.0
-
9.0
-
7.5
-
8.0
-
6.S
-
6.S
CL = SOpF
RL =
CL = 300pp3)
500n
soon
tPHZ
IPLZ
Output Disable Time OE
RL ..
CL = SpF(3)
to VI
RL ..
soon
CL ... SOpF
RL ...
soon
14.0
NOTES:
-
15.0
ns
2608tbl* 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter Is guaranteed but not tested.
6.46
6
(;J
HIGH-PERFORMANCE
CMOS BUFFERS
Integrated Device Technology, Inc.
IOT54174FCT827A
IDT54/74FCT827B
IOT54/74FCT827C
FEATURES:
DESCRIPTION:
• Faster than AMD's Am29827 series
• Equivalent to AMD's Am29827 bipolar buffers in pinouV
function, speed and output drive over full temperature
and voltage supply extremes
• IDT54/74FCT827A equivalent to FASTTM
The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT827A/B/C 10-bit bus drivers provide
high-performance bus interface buffering for wide datal
address paths or buses carrying parity. The 10-bit buffers
have NAND-ed output enables for maximum control flexibility.
All of the IDT54174FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
• IDT54174FCT8278 35% faster than FAST
• IDT54/74FCT827C 45% faster than FAST
IOL = 48mA (commercial), and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1 mW typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMD's
bipolar Am29800 series (5~ max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
2609 drw 01
PRODUCT SELECTOR GUIDE
10-BIt Buffer
IOT54/74FCT827AlBIC
2609 tbl01
CEMOS is a trademark 01 Integrated Device Technology. Inc.
FAST is a trademark 01 National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
6.47
MAY 1992
OSC-461212
1
IDT54n4FCT827 AlBIC
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Ys
Y7
YB
yg'
OE1
Do
D1
D2
D3
D4
Ds
Ds
. D7
DB
Dg
GND
LOGIC SYMBOL
INDEX
10T-l
DO-9 _ _ _ _
D2
D3
D4
NC
Ds
D6
D7
Y2
Y3
Y4
NC
Ys
Y6
Y7
nnnnnnn
OE2
2609 drw04
p >->-
a: -l Z Z -lIUJ!:::
00e:
1 UJOC,!)
<1:
2557 drw 02
c..
LCC
TOP VIEW
ERROR FLAG OUTPUT FUNCTION TABLE(1,2)
Description
Inputs
RECEIVE enable input.
VO
8-bit RECEIVE data input/output.
ERR
0
Output. from fault registers. Register
detection of odd parity fault on rising clock
edge (ClK). A registered ERR output
remains lOW until cleared. Open drain
output, requires pull up resistor.
I
432
1"1 r--1 . , ,.....,.., r-'I,-,
RI
ClR
L-JL..JL-JUL-JL..JLJ
NC
Rs
Rs
PARITY
OET
ClK
PIN DESCRIPTION
OER
a:a:OZ>1-1-
'Y
DIP/SOIC/CERPACK
TOP VIEW
Pin Name
~aIUJo8a~
INDEX
Vee
To
VO
8-bit TRANSMIT data input/output.
PARITY
VO
1-bit PARITY output.
Output
Pre-State
Output
ClR
ClK
Point "P"
ERRn-1
ERR
Function
H
H
H
t
t
t
-
H
H
l
-
H
l
l
Sample
(1 's
Capture)
l
-
-
-
H
Clear
l
NOTES:
1. OET is HIGH and OER is LOW.
Clears the fault register output.
TI
Internal
To Device
2557tbl02
2. H = HIGH
L= LOW
t = LOW·ta·HIGH transition of clock
- = Don't Care or Irrelevant
OET
I
TRANSMIT enable input.
ClK
I
External clock pulse input for fault register
flag.
2557 tbl 01
6.48
2
IDT54174FCT833A1B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(2)
Inputs
Outputs
TI Incl Parity
OET
OER
ClR
ClK
RI (r or H's)
(rof H's)
RI
TI
Parity
ERR(1)
L
L
L
L
H
H
H
H
H
H
H
H
H (Odd)
H (Even)
L(Odd)
L (Even)
NA
NA
NA
NA
NA
NA
NA
NA
H
H
L
L
L
H
L
H
H
L
H
L
Transmit data from R Port
to T Port with parity;
receiving path is disabled.
H
H
H
H
L
H
H
H
H
NA
NA
NA
NA
H (Odd)
H (Even)
L (Odd)
L (Even)
-
L
-
-
-
NA
NA
NA
NA
NA
Receive data from T Port
to R Port with parity test
resulting in flag:
transmitting path is disabled.
-
NA
NA
NA
NA
NA NA
H
L
L
L
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H or L (Odd)
H or L (Even)
-
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
H
H
L
L
L
L
L
L
L
L
H (Od~)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
NA
NA
NA
NA
H
H
L
L
H
H
H
H
H
L
H
L
L
H
L
H
L
H
H
H or L
-
t
t
t
t
t
t
-
H
H
L
L
L
L
H
L
Function
H
Clear the state of error flag
register.
*
80th transmitting and
receiving paths are disabled.
Parity logic defaults to
transmit mode.
Forced-error checking.
NOTES:
1. Output state assumes HIGH output pre-state.
2. H .. HIGH
L
.. LOW
t· .. LOW-to-HIGH transition of clock
*No change to stored Error State
2557tbl03
Z ..
NA ..
High Impedance
Not Applicable
Don't Care or Irrelevant
6.48
Odd..
Even..
I
Odd number of logic one's
Even number of logic one's
. 0, 1 , 2, 3, 4, 5, 6, 7
3
IDT54r/4FCT833A1B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vcc
-0.5 to Vcc
V
o to +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
Symbol Parameter(1)
CIN
CliO
Conditions
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
6
10
pF
1/0
VOUT= OV
8
12
pF
Capacitance
NOTE:
2557
1. This parameter is guaranteed by characterization but not tested.
tbl 05
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
2557tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.
2. Inputs and Vcc terminals.
3. Outputs and 110 terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
C ommercial: TA = 0° C to +70° CV cc = 5.0 V ± 5%; Military: TA = -55° C to + 125°C, Vcc = 5.0V ± 10%
Typ.(2)
Test Conditions(1)
Symbol
Parameter
Min.
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vcc = Max.
IlL
(Except 110 Pins)
Input LOW Current
VI = 2.7V
VI = 0.5V
-
(Except 1/0 Pins)
VI = GND
IIH
IlL
Input HIGH Current
VI =Vcc
Output HIGH Voltage
(Except ERR)
Output LOW Voltage
~
-5
-120
Vcc = 3V, VIN = VLC or VHC, 10H = -32~
Vcc = Min.
10H =-300~
VHC
VHC
Vcc
-
Vcc
-
2.4
4.3
2.4
4.3
GND
-
10H =-15mA MIL.
VIN = VIH or VIL
VOL
V
5
5(4)
_5(4)
-60
VI = 0.5V
VI = GND
Short Circuit Current
-
10H = -24mA COM'L.
Vcc = 3V, VIN = VLC or VHC, IOL = 300~
Vcc = Min.
VIN = VIH
or VIL
Except
ERR
IOL = 300~
IOL = 32 rnA MIL.
IOL = 48mA COM'L.
ERR
10L = 48mA
-
-
GND
0.3
0.3
15
15(4)
~
-15(4)
-15
-1.2
-
VLC
VLC(4)
0.3
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
6.48
Unit
V
0.8
-(J.7
Input LOW Current
(110 Pins Only)
los
VOH
-
Vcc = Min., IN = -18mA
Vcc = Max.(3), Vo = GND
VI = Vcc
VI = 2.7V
Clamp Diode Voltage
-
-
Vcc = Max.
(1/0 Pins Only)
VIK
-
Max.
-
V
rnA
V
v
0.5
0.5
0.5
2557 tbl06
4
IDT54n4FCT833A1B
FAST CMOS PARITY BUS TRANSCEIVER
POWER SUPPLV CHARACTERISTICS
Symbol
Icc
dlcc
ICCD
Ic
MILITARY AND COMMERCIAL TEMPERATURE RANGES
VLC
= O.2V; VHC = VCC -
O.2V
Test CondltJons(1)
Parameter
Quiescent Power Supply Current ' Vee = Max.; VIN ~ VHC, VIN :5 VLC
. Quiescent Power Supply Current
Vee.= Max.
VIN = 3.4V(3)
TTL Inputs HIGH
DynarniePower Supply Current(4) Vee'= Max.
VIN ~ VHC
VIN :5VLC
Outputs Open
OET = OER = GND
One Input Toggling
50% Duty Cycle
Total Power Supply Current(6)
VIN ~ VHC
Vee = Max.
VIN:5 VLC
Outputs Open
fcp = 10MHz
(FCT)
50% Duty Cycle
VIN = 3.4V
OET = GND
VIN' = GND
OER = Vcc
fi = 2.5MHz
One Bit TOQQlinQ
VIN ~ VHC
Vee = Max.
VIN:5 VLC
Outputs Open
fcp = 10MHz
(FCT)
50% Duty Cycle
VIN= 3.4V
OET = GND
VIN =GND
fi = 2.5MHz
OER = VCC
Eight Bits Toggling
Min.
Typ.(2)
-
-
0.2
0.5
Max.
1.5
2.0
Unit
rnA
rnA
-
0.15
0.25
mAl
MHz
-
1.4
3.4
rnA
-
1.9
5.4
-
4.0
7.8(5)
-
6.2
16.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN a 3.4V); all other inputs at Vcc or GND.
4...This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .1lcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
.1lcc';' Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Numberoflnputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.48
2557 tbl07
5
IDT54n4FCT833A1B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT833A
Com'l.
Condltlons(1)
Symbol
Parameter
tPLH
Propagation Delay
CL= SOpF
tPHL
RI to TI, TI to RI
CL = 300pF(3)
tPLH
Propagation Delay
CL= SOpF
tPHL
RltoPARITY
CL =300pF(3)
tPZH
Output Enable Time
CL = SOpF
tPZL
OER, OET to RI, TI
CL = 300pF(3)
tPHZ
Output Disable Time CL= SpF(3)
tPLZ
OER, OET to RI, TI
CL= SOpF
tsu
TI, PARITY to ClK
Set-up Time
CL= 50pF
tH
TI, PARITY to ClK
Hold Time
tREM
IDT54n4FCT833B
Com'l.
Mil.
Mil.
Mln.(2)
Mln.(2)
Max.
Mln.(2)
Max.
-
10.0
-
14.0
-
7.0
-
17.S
-
21.S
-
14.S
-
1S.0
20.0
-
10.S
-
14.0
-
22.S
-
27.S
-
18.0
23.S
-
16.0
-
10.7
-
14.7
-
16.0
-
7.2
12.0
-
21.S
16.0
12.0
19.5
Mln,<2)
Max.
8.S
8.5
Max.
Unit
-
10.0
ns
:--
17.S
11.0
ns
ns
18.S
9.8
ns
11.0
12.0
-
16.0
-
8.5
-
11.0
-
ns
0
-
0
-
0
-
0
-
ns
Clear Recovery Time
ClRtoClK
15.0
-
20.0
-
10.5
-
14.0
,-
ns
tw
Clock Pulse Width
HIGH or lOW
7.0
-
9.S
-
S.S
-
7.0
-
ns
tw
Clear Pulse Width
lOW
7.0
-
9.S
-
S.S
-
7.0
-
ns
tPHL
Propagation Delay
ClKto ERR
-
12.0
-
16.0
-
8.5
-
11.0
ns
tPLH
~agation Delay
-
16.0
-
20.0
-
15.0
-
18.0
ns
-
15.0
-
20.0
-
10.5
-
14.0
ns
22.5
-
27.5
-
18.0
-
21.5
ClRto ERR
tPLH
tPHL
Propagation Delay
CL= SOpF
OER to PARITY
CL = 300pF(3)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
2557 !bIOS
6.48
6
(;)
I DT54/74 FCT841 AlBIC
IDT54/74FCT843A1B/C
IDT54/74FCT844A1B/C
IDT54/74FCT845A1B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29841-46 bipolar registers in
pinout/function, speed and output drive over full temperature and voltage supply extremes
• IDT54/74FCT841A/843N844N845A equivalent to
FASTTM speed
• IDT54/74FCT841B/843B/844B/845B 25% faster than
FAST
• IDT54174FCT841C/843C/844C/845C 40% faster than
FAST
• Buffered common latch enable, clear and preset inputs
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1 mW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's
bipolar Am29800 series (5JlA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width forwider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 1O-bit wide version of the popular '373 function.
The IDT54174FCT843 and IDT54174FCT844 are 9-bit wide
buffered latches with Preset(PRE) and Clear (CLR)-ideal for
parity bus interfacing in high-performance systems.The IDT54/
74FCT845 is an 8-bit buffered latch with all the '843/4 controls,
plus multiple enables (OE1, OE2, OE3) to allow multiuser
control of the interface, e.g., CS, DMA and RD/WR. It is ideal
for use as an output port requiring high IOUIOH.'
All of the IDT54174FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
IDT54174FCT844
Do
IDT54174FCT841 /843/845
Do
DN
DN
Yo
YN
2607 cnv' 02
PRODUCT SELECTOR GUIDE
Yo
YN
2607 cnv· 01
Device
10-Blt
NonInverting
9-Blt
8-Bit
IOT54/74FCT841 IDT54/74FCT843 IOT54/74FCT845
AlBIC
AlBIC
AlBIC
IDT54/74FCT844
Invertln!1
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
2607tb10l
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
AlBIC
6.49
MAY 1992
DSC·460312
1
IDT54174FCT841/843/844/845A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54n4FCT84110·BIT LATCH
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9
LE
D1
D2
D3
D4
Ds
De
D7
Da
[)g
GND
INDEX
2 ~ 28 27 26
25[:
24[:
23[:
L28-1
22[:
21 [:
20[:
:]11
19[:
Y2
Y3
Y4
NC
Ys
Y6
Y7
D
Y
LE
OE
12 13 14 15 16 17 18
~~~~~:P~~
C!)
LCC
TOP VIEW
DIP/CERPACKISOIC
TOP VIEW
2607 cnv· 03,04,05
IDT54n4FCT843/844 9·BIT LATCHES
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
YB
PRE
LE
OE
Do
D1
02
D3
D4
Ds
De
D7
DB
CLR
GND
INDEX
2 ~ 28 27 26
02 :]5
03 :]6
04 :]7
NC :]8
Ds :]9
D6 :]10
D7 :]11
25[:
24[:
23[:
L28-1
22[:
21[:
20[:
19[:
Y2
Y3
Y4
NC
Ys
Y6
Y7
12 13 14 15 16 17 18
0
Y
LE
PRE
CLR
OE
nnnnnnn
~
W
10:...J()C!)CZZ...J
() W I0: ~
a..
LCC
TOP VIEW
DIP/CERPACKISOIC
TOP VIEW
2607 cnv· 06,07,08
IDT54n4FCT845 8·BIT LATCH
08
01:2
Do
D1
D2
D3
D4
Ds
De
D7
CLR
GND
Vee
INDEX
0E3
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
PRE
LE
0
'1' 28
2
25[:
24[:
23[:
L28-1
22[:
21[:
20[:
:]11
19[:
12 13 14 15 16 17 18
o 10:...J Z
0
() C!)
DIP/CERPACKISOIC
TOP VIEW
27 26
()
W
Z...J
Y
LE
PRE
CLR
08
01:2
0E3
I0:a.. :>:
W
LCC
TOP VIEW
6.49
Y1
Y2
Y3
NC
Y4
Ys
Y6
2607 cnv· 09,1 0,11
2
IDT54n4FCT841/843/844/845A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE(1)
IOT54/74 FCT841 1843/845
1/0
Description
Name
IDT54/74FCT841 18431845 (Non-Inverting)
CLR
I
01
I
LE
I
YI
0
OE
I
PRE
I
Inter-
WhenCLRis low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data
can be entered into the latch.
The latch data inputs.
Inputs
CLR PRE
H
The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
Theoutput enable control. When OE is
LOW, the outputs are enabled. When
OE is HIGH, the outputs (YI) are in the
hi~h-impedance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR
IDT54/74FCT844 (Inverting)
CLR
I
01
I
LE
I
YI
0
OE
I
PRE
I
H
oli
LE
DI
nal
QI
H
X
X
X
Function
High Z
H
H
H
L
L
Z
HighZ
H
H
H
H
H
Z
HighZ
H
H
H
L
X
NC
Z
Latched (High Z)
H
H
L
H
L
L
L
Transparent
Transparent
H
H
L
H
H
H
H
H
H
L
L
X
NC
NC
H
L
L
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
Latched
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched (High Z)
H
L
H
L
X
H
Z
Latched (High Z)
The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
FUNCTION TABLE(1)
IOT54/74FCT844
2607tb103
= Don't Care, NC = No Change,
Inter -
Out puts
DI
nal
Q\
H
H
H
X
X
X
Z
High Z
H
H
H
H
H
L
Z
High Z
H
H
H
H
L
H
Z
HighZ
H
H
H
L
X
NC
Z
Latched (High Z)
H
H
L
H
H
L
L
Transparent
H
H
L
H
L
H
H
Transparent
H
H
L
L
X
NC
NC
H
L
L
X
H
H
Preset
L
H
L
X
L
L
Clear
Inputs
CLR PRE OE LE
YI
Function
Latched
L
L
L
X
X
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched (High Z)
H
L
H
L
X
H
Z
Latched (High Z)
NOTE:
1. H = HIGH, L = LOW, X
Z = High Impedance
6.49
Z
H
When CLR is low, the outputs are LOW
if OE is LOW. When CLR is HIGH, data
can be entered into the latch.
The latch inverting data inputs.
2607tbl02
YI
H
NOTE:
1. H = HIGH, L = LOW, X
Z = High Impedance
The output enable control. When OE is
LOW, the outputs are enabled. When
OE is HIGH, the outputs (YI) are in the
high-impedance (off) state.
Preset line. When PRE is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides CLR
Outputs
2607tbl04
= Don't Care, NC = No Change,
3
IDT54174FCT841/843/844/845A1B/C
HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage -0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to Vee
with Respect to
GND
CAPACITAN CE
Military
Unit
-0.5 to +7.0
V
-0.5 to Vee
V
f=
1.0MHz)
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
6
10
pF
GoUT
Output
Capacitance
VOUT = OV
8
12
pF
Conditions
NOTE:
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output
Current
120
120
rnA
NOTE:
(TA = +25°C,
Parameter (1)
CIN
Symbol
2607 tbl 06
1. This parameter is measured at characterization but not tested.
2607 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
C am mercia
'IT
: A= 0° C to +70 0 CV cc = 5.0 V + 5%' Military: TA = -55° C to +125° C Vcc= 5.0V + 10%
Min.
Typ.(2)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max.
IlL
Input LOW Current
VI = 0.5V
-
VI =GND
-
-
10ZH
Off State (High Impedance)
Vo= Vee
-
Symbol
Test Conditions(l)
Parameter
VI = Vee
VI =2.7V
Vee = Max.
Vo=2.7V
Output Current
lozl
Vo= O.5V
Vo= GND
VIK
Clamp Diode Voltage
Vee = Min., IN = -18rnA
los
Short Circuit Current
Vee = Max.(3) , Va = GND
VOH
Output HIGH Voltage
Vee = 3V, VIN = VLe or VHe, 10H = -321lA
VOL
Output LOW Voltage
Max.
-
Il A
5(4)
-5(4)
-5
10
10(4)
-
-10(4)
-
VHe
Vee
Vee = Min.
10H = -3001lA
VHC
Vee
VIN = VIH or VIL
10H = -15mA MIL.
2.4
4.3
IOH = -24mA COM'L.
2.4
-1.2
-
4.3
Vec = Min.
10L = 300llA
-
VIN = VIH or VIL
10L = 32mA MIL.
-
0.3
0.5
IOL = 48mA COM'L.
-
0.3
0.5
Vee = 3V, VIN = VLC or VHC, 10L = 300JlA
IlA
-10
-0.7
GND
VLe
GND
V Le(4)
NOTES:
1.
2.
3.
4.
V
5
-
-120
V
0.8
-
-75
Unit
V
rnA
V
V
2607 tbl07
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
6.49
4
IDT54174FCT841/843/844/845A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
= VCC - O.2V
VLC .. O.2V; VHC
Svmbol
Icc
..1lcc
ICCD
Ic
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current(6)
TVp.(2)
Max.
Unit
-
0.2
1.5
rnA
-
0.5
2.0
rnA
VIN ~ VHC
VIN S VLC
-
0.15
0.25
mAl
MHz
VIN ~ VHC
VIN S VLC
(FCT)
-
1.7
4.0
rnA
VIN =3.4V
VIN =GND
-
2.0
5.0
VIN ~ VHC
VIN S VLC
(FCT)
-
3.2
6.5(5)
VIN .. 3.4V
VIN = GND
-
5.2
14.5(5)
Test Condltlons(1)
Vcc .. Max.
VIN ~ VHC' VIN S VLC
VCC= Max.
VIN = 3.4V(3)
Vcc= Max.
Outputs Open
OE=GND
LE = Vcc
One Input Toggling
50% Duty Cycle
Vcc .. Max.
Outputs Open
fi .. 10MHz
50% Duty Cycle
OE=GND
LE = Vcc
One Bit TOQQlinQ
Vcc .. Max.
Outputs Open
fi '" 2.5MHz
50% Duty Cycle
OE .. GND
LE", Vee
EiQht Bits TOQQlinQ
Min.
NOTES:
1.
2.
3.
4.
5.
6.
2607 tbl08
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at VCc - 5.0V, +25°C ambient.
Per TIL driven Input (VIN - 3.4V); all other Inputs at Vce or GND.
This parameter Is not directly testable, but is derived for use In Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ie" laulEseENT + !INPUTS + IDYNAMIC
Ie • Icc + Alec DHNT + IceD (fcp/2 + fiNi)
Icc .. Quiescent Current
Alec .. Power Supply Current for a TIL High Input (VIN .. 3.4V)
DH .. Duty Cycle for TIL Inputs High
NT .. Number of TIL Inputs at DH
IceD .. Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fep .. Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi " Input Frequency
Ni ,. Number of Inputs at fi
All currents are In milliamps and all frequencies are in megahertz.
6.49
5
IOT54174FCT841/843/844/845A1B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A1843A-
FCT841B/843B-
844A1845A
844B/845B
Com'l.
Symbol
DI to YI (LE
= HIGH)
tPLH
propagation Delay
DI to YI (LE
= HIGH)
tPLH
tPHL
tPLH
Propagation Delay
tPHL
LE toYI
tPLH
Propagation Delay, PRE to VI
tPHL
tPHL
SOpF
1.S
RL":' soon
CL = 300pF(4)
1.S
RL - soon
CL = SOpF
1.S
RL", soon
CL = 300pF(4)
1.S
RL - soon
CL = SOpF
1.S
RL = soon
CL = 300pF(4)
1.S
RL = soon
CL = SOpF
1.S
CL =
tPHL
(FCT844)
RL =
soon
Propagation Delay, CLR to VI
tPLH
tPZH
Output Enable Time OE to VI
tPZL
tPHZ
844C1845C
Mil.
Com'l.
Mil.
9.0
1.S 10.0 1.S
6.S
1.S
7.S
1.S
S.S
1.S
Unit
ns
6.3
13.0 1.S 1S.0 1.S 13.0 1.S 1S.0 1.S 13.0 1.S 1S.0
10.0 1.S 12.0 1.S
8.0
1.S
9.0
1.S
7.0
1.S
ns
8.0
13.0 1.S 1S.0 1.S 13.0 1.S 1S.0 1.S 13.0 1.S 1S.0
12.0 1.S 13.0 1.S
8.0
1.S 10.S 1.S
6.4
1.S
6.8
ns
16.0 1.S 20.0 1.S 1S.S 1.S 18.0 1.S 1S.0 1.S 16.0
1.S 10.0 1.S
7.0
1.S
1.S 14.0 1.S 17.0 1.S 10.0 1.S 13.0 1.S
12.0 1.S 14.0 1.S
8.0
9.0
1.S 12.0
9.0
1.S 13.0 1.S 14.0 1.S 10.0 1.S 11.0 1.S
9.0
1.S 10.0
1.S 14.0 1.S 17.0 1.S 10.0 1.S 10.0 1.S
9.0
1.S
ns
ns
9.0
SOpF 1.S 11.S 1.S 13.0 1.S 8.0 1.S 8.S 1.S 6.S 1.S 7.3 ns
soon
CL = 300pF(4) 1.S 23.0 1.S 2S.0 1.S 14.0 1.S 1S.0 1.S 12.0 1.S 13.0
RL = soon
CL= SpF(4)
1.S 7.0 1.S 9.0 1.S 6.0 1.S 6.S 1.S S.7 1.S 6.0 ns
RL = soon
CL = SOpF
1.S 8.0 1.S 10.0 1.S 7.0 1.S 7:S 1.S 6.0 1.S 6.3
RL = soon
CL = SOpF
2.S 2.5 2.5 2.5 2.S 2.5 ns
CL =
RL =
Output Disable Time OE to YI
tPLZ
tsu
Com'l.
Condltlons(1) Mln.!2) Max. MlnP) Max. MlnP) Max. Mln.!2) Max. Mln.!2) Max. Mln.!2) Max.
Parameter
(FCT841,843, Propagation Delay
845)
Mil.
FCT841 C/843C-
Data to LE Set-up Time
tH
Data to LE Hold Time
LE Pulse Width(3)
HIGH
4.0
-
3.0
tw
tw
PRE Pulse Width(3)
LOW
5.0
-
7.0
tw
CLR Pulse Width(3)
LOW
4.0
-
5.0
tREM
Recovery Time PRE to
LE
4.0
4.0
tREM
Recovery Time CLR to
LE
3.0
-
RL =
500n
2.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
5.0
3.0
-
2.5
-
2.5
-
2.5
4.0
-
ns
4.0
4.0
-
4.0
-
-
4.0
-
2.S
4.0
-
4.0
-
4.0
-
ns
4.0
-
4.0
-
4.0
4.0
-
ns
4.0
-
4.0
-
4.0
-
4.0
ns
3.0
-
3.0
-
3.0
-
3.0
-
ns
ns
2607 tbl09
6.49
6
~®
Integrated DeVice Technology, Inc.
HIGH·PERFORMANCE
CMOS BUS
TRANSCEIVERS
IDT54/74FCT861AJB
IDT54n4FCT863AJB
IDT54n4FCT864AJB
FEATURES:
DESCRIPTION:
'. Equivalent to AMD's Am29861-64 bipolar registers in
pinouVfunction, speed and 'output drive over full temperature and voltage supply extremes
·IDT54/74FCT861A/863A1864A equivalent to FASTI'M
speed
• IDT54174FCT861B/863B/864B 25% faster than FAST
• High-speed symmetrical bidirectional transceivers
• IOL - 48mA (commerCial) and 32mA (military) ,
• Clam'p diodes on all inputs for ringing suppression'
• CMOS power levels (1 mW tYpo static)
,. TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's
bipolar Am29800 Series(5~ max.}
'. Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, ClassB
The IDT54/74FCT800 series is built using advanced
CEMOSTM, a dual metal CMOS technology.
The IDT54174FCT860 series bus transceivers provide
high-performance bus interface buffering for wide
data/address paths or buses carrying parity. The
IDT54/74FCT863/864 9-bit transceivers have NAND-ed
output enables for maximum control flexibility.
All of the IDT5417 4FCT800 high-performance interface
family are designed for high-capacitance load drive capability
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the highimpedance state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54174FCT863/864
IDT54174FCT861
2610 drw 01
PRODUCT SELECTOR GUIDE
Device
I
I
Non-inverting
Inverting
10-8"
9-81t
IDT54174FCT861
IDT54174FCT863
IDT54174FCT864
2610 tbl 01
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
6.50
MAY 1992
D~2012
1
IDT54n4FCT861A1B, IDT54n4FCT863A1B, IDT54n4FCT864A;
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IOT54174FCT86110-BIT TRANSCEIVER
10:
0
.-owOo
INDEX
OER
Ro
R1
R2
R3
R4
Rs
R6
R7
Rs
R9
GND
'o:o:oz>~~
r
Vee
To
T1
T2
T3
T4
T5
T6
T7
Ts
T9
OET
L.J L...I L.J
I I L.J
I 128
LJ
L-J L.J
......
27 2S
. 25 [
]5
1
24 [
JS
]7
23 [
L28-1
22[
J8
]9
21 [
20 [
J10
19[
] 11
'12 13 14 15 16 17 18
........, ,......,,......,,......,,......,,......,........,
R2
R3
R4
NC
R5
R6
R7
"
OIP/CERPACKISOIC
TOP VIEW
4 3 2
0r-
T2
T3
T4
NC
T5
T6
T7
./
co 01 0
Ol co
O:O:ZZWI-I(!)
0
LCC
TOP VIEW
IOT54174FCT863/864 9-BIT TRANSCEIVERS
OER1
Ro
R1
R2
R3
R4
Rs
Rs
R7
Rs
OER2
GND
INDEX
Vee
To
T1
T2
T3
T4
Ts
Ts
T7
Ts
OET2
OET1
10:
.-owo
0
.-
oo
o:a:Oz>1-1-
L-JL-.JL.....JIIL-JL....JL.....J
43211282726
L.J
]5
25 [
1
]6
24[
]7
23 [
L28-1
22[
J8
]9
21[
] 10
20 [
19 [
] 11
12 13 14 1S 16 17 18
R2
R3
R4
NC
Rs
R6
R7
r I r I 1'1 r I r I r I r-t
" ~ , ;: ~ ~I;:I~ ~
~(!) ~~
OIP/CERPACKISOIC
TOP VIEW
T2
T3
T4
NC
Ts
T6
T7
II
./
2610 drw02
LCC
TOP VIEW
LOGIC SYMBOLS
IOT54174FCT863/864
IOT54174FCT861
OET1
OET2 -----4~J
10
T
9
T
OER1
OER2---UI
6.50
2610 drw 03
2
IDT54n4FCT861A1B, IDT54n4FCT863A1B, IDT54174FCT864A1B
HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Name
I/O
Description
IDT54174FCT861
OER
I
When LOW in conjunction with OET HIGH
activates the RECEIVE mode.
OET
When LOW in conjunction with OER HIGH
I
activates the TRANSMIT mode.
10-bit RECEIVE input/output.
RI
lID
1O-bit TRANSMIT input/output.
TI
lID
IDT54/74FCT861/863 (Non-inverting)
Inputs
Outputs
OET OER RI
TI
RI
TI
Function
N/A N/A
L
H
L
Transmitting
L
Transmitting
N/A N/A
L
H
H
H
Receiving
N/A
L
L
N/A
H
L
H
H
IDT54174FCT863/864
When LOW in conjunction with OETI HIGH
OERI
I
activates the RECEIVE mode.
When LOW in conjunction with OERI HIGH
OETI
I
activates the TRANSMIT mode.
9-bit RECEIVE input/output.
RI
lID
lID
9-bit TRANSMIT input/output.
TI
L
H
NOTE:
1. H = HIGH, L
Applicable.
H
X
N/A
H
Z
Z
Receiving
HighZ
2610tbl03
= LOW,
Z
= High
Impedance, X
= Don't Care, NIA = Not
FUNCTION TABLE(1)
IDT54174FCT864 (Inverting)
Inputs
Outputs
2610tbl02
OET
L
OER
H
L
H
H
H
L
L
H
N/A
L
N/A
H
H
X
NOTE:
1. H = HIGH, L
Applicable.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
with Respect
to GND
Operating
TA
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
Power Dissipation
PT
lOUT
DC Output Current
N/A
X
RI
L
RI
N/A
N/A
H
TI
H
L
N/A
Function
Transmitting
Transmitting
Receiving
H
X
L
Z
N/A
Z
Receiving
HighZ
TI
N/A
N/A
2610 tbl 04
= LOW, Z = High
Impedance, X = Don't Care, NIA
= Not
CAPACITANCE
Commercial
Military Unit
-0.5 to +7.0 -0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
V
oto +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
0.5
120
0.5
120
W
mA
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions Typ.
Max.
Unit
CIN
Input Capacitance
VIN = OV
6
10
pF
CliO
110 Capacitance
VOUT= OV
8
12
pF
Symbol
NOTE:
2610tbl06
1. This parameter is guaranteed by characterization but not tested.
2610tbl05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vce by +O.5V unless otherwise noted.
2. Inputs and Vce terminals only.
3. Outputs and 1/0 terminals only.
6.50
3
IDT54n4FCT861A1B,IDT54n4FCT863A1B,IDT54n4FCT864A1B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V, VHC = vcc - O.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc = 5.0V ± 10%
Typ.(2)
Test Condltlons(1)
Symbol
Parameter
Min.
VIH
VIL
Input HIGH Level
Input LOW Level
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current
(Except /10 pins)
Vcc= Max.
IlL
IIH
ilL
Input LOW Current
(Except /10 pins)
Input HIGH Current
(/10 pins Only)
VOL
Output LOW Voltage
VI = O.5V
VI=GND
-
Vcc = Min., IN =-18mA
Vcc = Max.(3), Vo = GND
Vcc = 3V, VIN =VLC or VHC, 10H = -32~
Vcc.:. Min.
10H =-300~
VIN = VIH or VIL
10H =-15mA MIL.
10H = -24mA COM'L.
Vcc = 3V, VIN = VLC or VHC, IOL = 300~
Vcc= Min.
IOL=300~
IOL = 32mA MiLl:»
VIN = VIH or VIL
IOL = 48mA COM'L.(5)
NOTES:
1.
2.
3.
4.
5.
-
VI = O.5V
VI= GND
Input LOW Current
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VI = Vcc
VI = 2.7V
VI = Vcc
VI = 2.7V
Vcc = Max.
(/10 pins Only)
VIK
los
VOH
2.0
-
-75
VHC
VHC
2.4
2.4
-
-
-
Max.
0.8
Unit
V
V
5
5(4)
~
-
_5(4)
~
-
-15(4)
-
-15
-1.2
-0.7
-120
Vcc
Vcc
4.3
4.3
GND
GND
0.3
0.3
-5
15
15(4)
-
V
rnA
V
VLC
VLC(4)
V
0.5
0.5
2610tbl07
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.
These are maximum IOLvalues per output, for 10 outputs turned on simultaneously. Total maximum IOL (all outputs) is 480mA for commercial and 320mA
for military. DerateloL for number of outputs exceeding 10 turned on simultaneously.
.
6.50
4
IDT54114FCT861 AlB, IDT54174FCT863A1B, IDT54174FCT864A1B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = VCC - O.2V
Symbol
Parameter
Test Condltlons(1)
Min.
Typ.(2)
Max.
Unit
Quiescent Power
Supply Current
Quiescent Power Supply
Current TIL Inputs HIGH
Vcc = Max.
VIN ~ VHC ; VIN s; VLC
-
0.2
1.5
rnA
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
rnA
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
OER or OET = GND
One Input Toggling
50% Duty Cycle
VIN ~ VHC
VIN s; VLC
-
0.15
0.25
rnA!
MHz
Ic
Total Power Supply Current(6)
Vcc = Max., Outputs Open
fi = 10MHz
50% Duty Cycle
VIN ~ VHC
VIN S; VLC
(FCT)
-
1.7
4.0
rnA
OER or OET = GND
One Bit Toggling
VIN
VIN
-
2.0
5.0
VCC = Max., Outputs Open
fi = 2.5MHz
50% Duty Cycle
VIN~
VHC
VIN S;VLC
(FCT)
-
3.2
6.5(5)
OER or OET = GND
Eight Bits Toggling
VIN = 3.4V
VIN = GND
-
5.2
14.5(5)
Icc
~Icc
= 3.4V
= GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 50V, +25°C ambient.
3. Per TTL driven input (VIN = 3AV); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT +IINPUTS + IDYNAMIC
Ie = Icc + AlccDHNT + ICCD(fcp/2 + fiNi)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.50
2610tbl08
5
IDT54174FCT861A1B, IDT54174FCT863A1B, IDT54174FCT864A1B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT861 Al863A1864A
Com'l.
Symbol
tPLH
tPHL
Parameter
Conditlon(1)
Mln.<2)
Propagation Delay
RI to TI or TI to RI
CL = SOpF
RL = soon
CL = 300pF(3)
RL= soon
FCT861/863
tPLH
tPHL
Propagation Delay
RI to TI or TI to RI
FCT864
CL = 50pF
RL= soon
CL = 300pp3)
RL =
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OET to TI or OER to RI
~ut Disable Time
OET to TI or OER to RI
Min.<2)
1.S
Max.
8.0
1.S
FCT8618/8638/8648
Com'l.
Mil.
Min.<2)
Max.
Min.<2)
1.S
Max.
9.0
1.S
6.0
1.S
Max.
6.5
15.0
1.5
17.0
1.5
13.0
1.5
14.0
1.5
7.5
1.5
9.0
1.5
5.5
1.5
6.5
1.5
14.0
1.5
16.0
1.5
13.0
1.5
14.0
1.S
12.0
1.5
13.0
1.5
8.0
1.5
9.0
1.5
20.0
1.5
22.0
1.5
15.0
1.5
16.0
1.S
9.0
1.S
9.0
1.S
6.0
1.S
7.0
1.5
10.0
1.S
10.0
1.S
7.0
1.S
8.0
Unit
ns
ns
soon
CL = SOpF
RL= soon
CL = 300pP3)
RL= soon
CL = 5pF(3)
RL=
Mil.
ns
ns
soon
CL = SOpF
RL= soon
NOTES:
2610tbl09
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This condition guaranteed but not tested.
6.50
6
'.
t;)®
PRELIMINARY
IDT54174FBT2240
IDT54/74FBT2240A
HIGH-SPEED BiCMOS
MEMORY DRIVERS
Integrated Devlc:e Technology, Inc:.
FEATURES:
DESCRIPTION:
• IDT54/74FBT2240 equivalent to the 54/74BCT2240
• IDT54n4FBT2240A 25% faster than the 2240
• 250 output resistors reduce overshoot and undershoot
when driving MaS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output .Ievels
• Higher static VOH for improved noise immunity and
reduced system power dissipation
• ±10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC packages
• Military product compliant to MIL-STD-883, Class B
The FBT series of BiCMOS Memory Drivers is built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54174FBT2240 series are octal buffers/line drivers
where each output is terminated with a 25,Q series resistor.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. The output
buffers are designed to guarantee a static VOH of 2.7V. This
higher output level in the high state results in a significant
reduction in overall system power dissipation and improved
noise immunity when driving DRAMS and SRAMS.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DEB
DAo
OAo
OBo
DBo
DAl
OAl
OBl
DBl
DA2
OA2
OB2
DB2
DA3
OA3
OB3
Vee
OEA
DAo
OBo
DA1
OB1
DA2
082
DA3
083
GND
19
2
18
3
P20-1 17
4
D20-1
5 S020-2 16
15
6
&
E20-1 14
7
13
8
9
12
11
10
OEe
DAo
DBo
OA1
DB1
OA2
D82
OA3
083
DIP/SOIC/CERPACK
TOP VIEW
INDEX
1m0 0
~IUJ
81m
0> 0
'Y
L....JL...J I
3
DAl ] 4
OBl ] 5
DA2 ] 6
OB2 ] 7
DA3 ] 8
DB3
2642drw 01
\..
IL...JL....J
2 : :
l'
"
20 19
lB [
H[
L20-2
16 [
15 [
14 [
9 1011 12 13
"....,,,....,,,
OAo
DBo
OAl
DBl
OA2
./
al ~ all< tIl
l0C!J000
Lec
2642 drw 02
TOP VIEW
BiCEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101992 Integrated Devloe Technology, Inc.
6.51
APRIL 1992
DSC·6001/1
1
IDT54n4FBT2240/A
HIGH-SPEED BICMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
Description
OEA,OEs
3-State Output Enable Inputs (Active LOW)
Dxx
Oxx
Output
Inr:uts
OEA,OEB
Dxx
Oxx
Inputs
L
L
H
Outputs
L
H
L
H
X
Z
2642tbl01
NOTE:
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
toGND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
-0.5 to Vee
2642 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
Parameter(1)
Conditions Type Max.
Unit
CIN
Input Capacitance
VIN= OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
2642 tbl 04
1. This parameter is measured at characterization but not tested.
2642 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vcc by +O.5V unless otherwise noted.
2. Input and Vce terminals only.
3. Outputs and 110 terminals only.
6.51
2
IDT54174FBT2240/A
HIGH-SPEED BICMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLe = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 10%; Military: TA = -55°C to +125°C, Vee = 5.0V ± 10%
Symbol
VIH
Vil
IIH
III
10lH
lOll
II
VIK
10DH
10Dl
los
VOH
VOL
VH
leeH
leel
leel
Min.
Typ.(2)
Max.
Unit
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
2.0
-
-
-
V
V
Vee = Max., VI = 2.7V
-
-
Test Condltlons(1)
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Input HIGH Current
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Vee = Max., VI.= 0.5V
Vee = Max.
-
Vee = Max., Vee (Max.)
Vee = Min., IN = -18mA
Vee = Min., Va = 2.25V
Vee = Min., Va = 2.25V
Vee = Max., VA = GND(3)
-
10H = -300jlA(4)
Vee= Min.
VIN = VIH or Vil
.IOH =-1mA
10H =-8mA
10H = -12mA
10L = 300jlA(4)
Vee= Min.
VIN = VIH or Vil
10l = 1mA
10l = 12mA
-
Input Hysteresis
Quiescent Power
Supply Current
Vo= 2.7V
VO= 0.5V .
-35
50
-75
VHe
2.7
2.4
2.0
-
-
Vee= Max.
VIN = GND or Vee
0.8
10
-10
50
-50
100
-1.2
-fJ.7
-
-
-
-225
-
Vee
3.8
3.3
3.2
GND
0.1
0.35
200
0.2
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This condition is guaranteed but not tested.
6.51
-
jlA
jlA
jlA
jlA
V
mA
mA
mA
V
VLC
0.5
0.8
V
-
mV
1.5
mA
2642tbl05
3
IDT54174FBT2240/A
HIGH-SPEED BICMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLV CHARACTERISTICS
Symbol
dice
IceD
Ie
Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)
Dynamic Power Supply
Current(4)
Total Power Supply
Current(6)
.
Test Condltlons(l)
Min.
Vee = Max.
VIN = 3.4V(3)
TypY'J
-
O.S
Max.
2.0
0.3
0.40
Vee = Max., Outputs Open
OEA = OEB = GND
One Input Toggling
SO% Duty Cycle .
VIN = Vee
VIN =GND
-
Vee = Max:, Outputs Open
VIN = Vee
VIN = GND
-
3.2
S.S
fi = 10MHz, SO% Duty Cycle
OEA = OEB = GND
One Bit Toggling
VIN = 3.4V
VIN = GND
-
3.S
6.S
Vee = Max., Outputs Open
VIN = Vee
VIN= GND
-
6.2
9.S(5)
fi = 2.SMHz, SO% Duty Cycle
OEA = OEB = GND
Eight Bits Toggling
VIN = 3.4V
VIN = GND
-
8.2
17.S(5)
Unit
rnA
mN .
MHz
rnA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + !iNPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni ~ Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz
2642tbl06
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54174FBT2240
Com'l.
Symbol
tPLH
tPHL
Parameter
Propag~ion
Delay
Dxxto Oxx
Condition(l)
IOT54174FBT2240A
Mil.
Com'l.
Mil.
Mln.(2) Max.
Mln,(2)
Max.
Mln.(2)
Max.
Mln.(2)
Max.
1.S
S.7
1.S
6.3
. 1.S
4.8
1.5
S.1
ns
CL= SOpF
RL= soon
Unit
tPZH
tPZL
Output Enable Time
1.5
8.0
1.5
8.5
1.5
6.2
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
7.0
1.5
7.5
1.5
S.6
1.5
5.9
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2642 tbl 07
6.51
4
G®
PRELIMINARY
I DT54174FBT2244
IDT54/74FBT2244A
HIGH-SPEED BiCMOS
MEMORY DRIVERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FBT2244 equivalent to the 54/74BCT2244
• IDT54174FBT2244A 25% faster than the 2244
• 250 output resistors reduce overshoot and undershoot
when driving MOS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TTL compatible input and output levels
• Higher static VOH for improved noise immunity and
reduced system power dissipation.
• ±10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC packages
• Military product compliant to MIL-STD-883, Class B
The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54174FBT2244 series are octal bufferslline drivers
where each output is terminated with a 250 series resistor.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. The output
buffers are designed to guarantee a static VOH of 2.7V. This
higher output level in the high state results in a significant
reduction in overall system power dissipation and in improved
noise immunity when driving DRAMS and SRAMS.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Vee
OEs
OEA
OEA
DAo
OBo
DAl
OBl
DA2
.0:
OEB
OAo
DBo
OAl
DBl
OA2
DB2
OA3
DB3
OB2
DAo
OAo
DA3
OB3
OBo
DBo
GND
DA1
OA1
OB1
DB1
DA2
OA2
OB2
DB2
DA3
OA3
DIP/SOIC/CERPACK
TOP VIEW
~
OB3
DAl ] 4
OBl ] 5
DA2 ] 6
OB2 ] 7
DA3 ] 8
DB3
32: :2019
l'
"-
18 [
17[
L20-2
16 [
15 [
14 [
9 1011 1213
OAo
DBo
OAl
DBl
OA2
250
2641 drw 01
2641 drw 02
LCC
TOP VIEW
BiCEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1992 Integrated Device Technology, Inc.
6.52
APRIL 1992
OSC-601212
1
IDT54n4FBT2244/A
HIGH·SPEED BICMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
OEA,OEs
3-State Output Enable Inputs
Dxx
Oxx
OEA, OEB
Dxx
Inputs
L
L
L
Outputs
L
H
H
X
Z
2641 tblOl
ABSOLUTE MAXIMUM RATINGS(1)
Military
Unit
VTERM(2) Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect
toGND
-0.5 to Vee
-0.5 to Vee
V
Rating
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care .
Z .. High Impedance
Oxx
2641 tbl 02
CAPACITANCE (TA= +25°C, f= 1.0MHz)
Commercial
Symbol
Outputs·
Inr:uts
Description
Pin Names
TA
Operating
Temperature
Oto +70
-55 to +t25
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
~C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
Symbol
Parameter(1)
Conditions Type Max. Unit
CIN
Input Capacitance
VIN= OV
6
10
pF
COUT
Output
Capacitance
VOUT= OV
8
12
pF
NOTE:
2641 tbl 04
1. This parameter is measured at characterization but not tested.
NOTES:
2641 tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal
voltage may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Outputs and 110 terminals only.
6.52
2
IDT54n4FBT2244/A
HIGH-SPEED BICMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
. Commercial: TA = O°C to +70°C, Vcc = 5.0V +
- 10%; Military: TA = -55°C to +125°C , Vcc = 5 OV +
- 10%
Symbol
VIH
VIL
IIH
IlL
10lH
lOlL
II
VIK
10DH
10DL
los
VOH
VOL
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Input HIGH Current
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Test Condltlons(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Vee = Max., VI = 2.7V
Vee = Max., VI = 0.5V
Vee= Max.
Vo =2.7V
Vo = 0.5V
Vee = Max., Vee (Max.)
Vee = Min., IN = -18mA
Vee = Min., Vo =2.25V
Vee = Min., Vo = 2.25V
Vee = Max., Vo = GND(3)
Vee =Min.
VIN = VIH or VIL
IOH
IOH =-1mA
IOH =-8mA
IOH =-12mA
IOL = 300jlA(4)
Vcc= Min.
IOL = 1mA
IOL = 12mA
VIN = VIH or VIL
VH
leeH
leel
leeL
Input Hysteresis
Quiescent Power
Supply Current
=-300jlA(4)
Vee= Max.
VIN = GND or Vee
Min.
2.0
-35
50
-75
VHe
2.7
2.4
2.0
-
-
Typ.(2)
Max.
-
0.8
10
-10
50
-50
100
-1.2
-
-{J.7
-
-225
Vee
3.8
3.3
3.2
GND
0.1
0.35
200
0.2
NOTES:
1.
2.
3.
4.
VLC
0.5
0.8
1.5
Unit
V
V
jlA
jlA
jlA
jlA
V
rnA
rnA
rnA
V
V
mV
rnA
2641 tbl05
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee .. 5.0V, +25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This condition is guaranteed but not tested.
6.52
3
IDT54174FBT2244!A
HIGH-SPEED BlCMOS MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
~Iee
IceD
Ie
Parameter
Quiescent Power Supply
Current (Inputs TIL HIGH)
Test Condltlons(1)
Min.
Vee = Max.
VIN = 3.4v(3)
Typ.!2)
-
0.5
Max.
2.0
0.3
0.40
Dynamic Power Supply
Current(4)
Vee = Max., Outputs Open
OEA = OEB .. GND
One Input Toggling
50% Duty Cycle
VIN = Vee
VIN =GND
-
Total Power Supply
Current(6)
Vee = Max., Outputs Open
fi = 10MHz, 50% Duty Cycle
VIN = Vee
VIN =GND
-
3.2
5.5
OEA =OEB =GND
One Bit Toggling
V:N = 3.4V
VIN = GND
-
3.5
6.5
Vee = Max., Outputs Open
fi =2.5MHz, 50% Duty Cycle
VIN = Vee
VIN = GND
-
6.2
9.5(5)
OEA = OEB = GND
Eight Bits Toggling
VIN = 3.4V
VIN .. GND
-
8.2
17.5(5)
rnA
mAl
MHz
rnA
NOTES:
1.
2.
3.
4.
5.
6.
Unit
2641 tbl06
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ie = Icc + ~Ice DHNT + ICCD (fcp!2 + fi Ni)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN =3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
AU currents are in milliamps and aU frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FBT2244
Com'l.
Symbol
Parameter
Condltlon(1)
IDT54174FBT2244A
Com'l.
Mil.
Mln.(2)
Max.
Mln.(2)
Max.
1.5
6.5
1.5
Mil.
Mln.(2)
Max.
Mln.(2)
7.0
1.5
4.8
1.5
5.1
ns
Max.
Unit
tPLH
tPHL
Propagation Delay
Dxxto Oxx
tPZH
tPZL
Output Enable Time
1.5
8.0
1.5
8.5
1.5
6.2
1.5
6.5
ns
tPHZ
tpLZ
Output Disable Time
1.5
7.0
1.5
7.5
1.5
5.6
1.5
5.9
ns
CL = 50pF
RL = soon
NOTES:
2641 tbl07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.52
4
(;)®
HIGH-SPEED BiCMOS
OCTAL· TRANSPARENT
LATCH DRIVERS
Int~grated Device Technology, Inc.
ADVANCE INFORMATION
. IDT54/74FBT2373
IDT54/74FBT2373A
FEATURES:
DESCRIPTION:
• 250 output resistors reduce overshoot and undershoot
when driving MO'S RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output levels
• Higher static VOH for improved noise immunity and
. reduced power dissipation.
• Low power in all .three states
• ±10% power supply for both military and commercial
. grades
• JEDEC standard pinout for DIP, SOIC and LCC'
packages
• Military product compliant to MIL-STD-883, Class B
The FBT series of BiCMOS Latch Drivers are built using
advanced BiCEMOSTM, a dual metal SiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54174FBT2373 series are 3-state, 8-bit latches
where.each output is terminated with a 250 series resistor .
The' latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the set-up times is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high-impedance state.
The FBT series of bus interface devices are ideal for driving
large capacitive loads with low static (DC) current loading. All
data inputs have a 200mV typical input hysteresis for improved noise rejection. The output buffers are designed to
guarantee a static VOH of 2.7V. This higher output level in the
high state will result in a significant reduction in overall system
power dissipation and in improved noise immunity when
driving DRAMS and SRAMS.
FUNCTIONAL BLOCK DIAGRAM
250
2640 drw 01
PIN CONFIGURATIONS
° °lw
INDEX
OE
Vee
00
07
D7
Do
32: :20~
D1
01
02
D2
Ds
Os
D1
01
02
D2
05
D5
D4
04
LE
D3
03
GND
8 ...
000>0
D3
] 4
] 5
l'
]s
L20-2
] 7
] 8
18 [
17 [
lS [
15 [
14 [
9 1011 1213
D7
Ds
Os
05
D5
.,rlrlrlrI
8~~Ob
2640 drw02
C!l
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
BiCEMOS is a trademark 01 Integrated Device Technology. Inc.
MILITARY.AND
COMMERCIAL
TEMPERATURE RANGES
.
,
<0199.2 Integrated Device Technology. Inc.
6.53
APRIL 1992
D5C·600312
1
IDT54174FBT2373/A
HIGH-SPEED BICMOS OCTAL TRANSPARENT LATCH DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
Description
Inputs
00-07
Data Inputs
LE
Latch Enables Input (Active HIGH)
OE
00-07
Outputs
Dn
LE
OE
On
H
H
L
H
Output Enables Input (Active LOW)
L
H
L
L
3-State Latch Outputs
X
L
L
NC
X
X
H
Z
2640tb105
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
Symbol
V
Parameter(1)
Conditions Type Max.
CIN
Input Capacitance
VIN = OV
COUT
Output
Capacitance
VOUT=
NOTE:
with Respect
toGND
OV
Unit
6
10
pF
8
12
pF
2640 tbl 02
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
rnA
NOTES:
2640tb106
2640 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 1/0 terminals only.
6.53
2
IDT54174FBT2373/A
HIGH·SPEED BICMOS OCTAL TRANSPARENT LATCH DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to +70°C, Vcc =·5.0V ± 10%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
,VIL'
IIH
III
10ZH
10Zl
II
VIK
100H
100l
los
VOH
VOL
VH
lecH
lecz
leCl
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Input HIGH Current
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Quiescent Power
Supply Current
Test Condltlons(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Vee ... Max., VI ... 2.7V
Min.
2.0
-
-
Vee = Max., VI = 0.5V
Vee = Max.
Va = 2.7V
VO= 0.5V
-
Vee = Max., Vee (Max.)
Vee = Min., IN = -18mA
Vee = Min., Va = 2.25V
Vee.;,. Min., Va"; 2.25V
Vee = Max., Vo = GND(3)
Vee = Min.
10H = -300J.IA (4)
VIN = VIH or Vil
IOH = -1 rnA
IOH =-8mA
IOH = -12mA
IOL = 300J.IA(4)
Vec= Min.
VIN = VIH or VIL
IOL = 1mA
IOL = 12mA
Vcc = Max.
VIN = GND or Vee
-
-35
50
-75
VHe
2.7
2.4
2.0
-
Typ.(2)
Max.
-
-
-
0.8
10
-
·10
50
·50
100
-1.2
-Q.7
-
-
-
-
-
-225
Vee
3.8
3.3
3.2
GND
0.1
0.35
-
VLC
0.5
0.8
200
0.2
1.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This condition is guaranteed but not tested.
6.53
Unit
V
V
J.IA
J.IA
J.IA
J.IA
V
rnA
rnA
rnA
V
-
-
-
V
mV
rnA
2640 tbl 03
3
IDT54n4FBT2373/A
HIGH-SPEED BlCMOS OCTAL TRANSPARENT LATCH DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Typ.l2)
Max.
Unit
-
0.5
2.0
rnA
VIN = Vee
VIN = GND
-
0.3
0.4
Vee = Max., Outputs Open
fi = 10MHz, 50% Duty Cycle
VIN = Vee
VIN= GND
-
3.2
5.5
OE = GND, LE = Vee
One Bit Toggling
VIN = 3.4V
VIN =GND
-
3.5
6.5
Vee = Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle
VIN = Vee
VIN = GND
-
6.2
9.5(5)
OE = GND, LE = Vee
Eight Bits Toggling
VIN = 3.4V
VIN = GND
-
8.2
17.5(5)
Test Condltlons(l)
Parameter
Alee
Quiescent Power Supply
Current (Inputs TTL HIGH)
Vee =Max.
VIN = 3.4V(3)
leeD
Dynamic Power Supply
Current(4)
Vee = Max., Outputs Open
OE = GND, LE = Vee
One Input Toggling
50% Duty Cycle
Total Power Supply
Current(6)
Ie
Min.
NOTES:
1.
2.
3.
4.
5.
6.
mAl
MHz
rnA
26401b104
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + Lilcc DHNT + ICCD (fcp/2 + fi Ni)
Icc = Quiescent Current
Lilcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = DUty Cycle for TIL Inputs High
NT = Number of TIll inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54174FBT2373
Com'l.
Symbol
Parameter
Conditlon(l)
CL= 50pF
RL= 500n
IOT54174FBT2373A
MIL
Com'l.
Mil.
Max.
Mln.(2)
Max.
Mln.(2)
Max.
Unit
1.5
8.5
1.5
5.2
1.5
5.6
ns
Min.(2)
Max.
Min.(2)
1.5
8.0
tPLH
tPHL
Propagation Delay On to On
tPLH
tPHL
Propagation Delay LE to On
2.0
9.3
2.0
10.1
2.0
8.5
2.0
9.8
ns
tPZH
tPZL
Output Enable Time
1.5
12.0
1.5
12.5
1.5
6.5
1.5
7.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
7.4
1.5
8.1
1.5
5.5
1.5
6.5
ns
tsu
Set-up Time HIGH or LOW
Onto LE
2.0
-
2.0
-
2.0
-
2.0
-
ns
tH
Hold Time HIGH or LOW
Onto LE
1.5
-
1.5
-
1.5
-
1.5
-
ns
tw
LE Pulse Width HIGH or
LOW
6.0
-
6.0
-
5.0
-
6.0
-
ns
NOTES:
2640 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.53
4
(;)
HIGH SPEED BiCMOS
10-BIT MEMORY DRIVERS
Integrated Device Technology, Inc.
ADVANCE
INFORMATION
IDT54174FBT2827AlB
I DT54/74FBT2828A/B
FEATURES
DESCRIPTION
• IDT54/74FBT2827N2828A is equivalent to
54/7 4BCT2827N2828A
• IDT54174FBT2827B/2828B is 30% faster than BCT
• 25Q output resistors reduce overshoot and undershoot
when driving MOS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output levels
• Higher static VOH for improved noise immunity and
reduced system power dissipation
• Low power in all three states
• ±10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC packages
• Military product compliant to MIL-STD-883, Class B
The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54174FBT2827NB and IDT54/74FBT2828NB are
3-state 1O-bit buffers where each output is terminated with a
25.Q series resistor. The output buffers are enabled when the
two Active-LOW output enable pins are logic LOW.
The FBT series of memory line drivers are ideal for use in
designs needed to drive large capacitive loads, with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. They are also
designed for rail-to-rail output switching. This higher output
level in the high state will result in significant reduction in
overall system power dissipation.
FUNCTIONAL BLOCK DIAGRAM
2516 drw 01
PRODUCT SELECTOR GUIDE
I
I
Non-inverting
Inverting
10·Blt Memory Driver
IDT 54174FBT2827A1B
IDT 54/74FBT2828A1B
2516tbl01
BiCEMOS is a trademark 01 Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
6.54
APRIL 1992
DSC-600711
1
IDT54174FBT2827AlBIIDT54174FBT2828A1B
HIGH SPEED BlCMOS 10-BIT MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC SYMBOL
INDEX
Vee
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7
Ya
Y9
OE2
OE.1
Do
01
02
03
04
Os
06
07
Oa
09
GNO
Oo-s
Y2
Y3
Y4
NC
Ys
Ye
Y7
<0
C
IW
O>""ON
c......
~Zo
2516 drw 02A
0>
OE1
OE2
o
10
~
Yo-s
2516 drw 03
<0
>- >-
2516 drw 029
LCC
TOP VIEW
OIP/CERPACKlSOIC
TOP VIEW
PIN DESCRIPTION
Name
OE1
OE2
I/O
I
01
YI
I
0
Description
When both are LOW, the outputs are
enabled. When either one or both are
HIGH the outputs are High Z.
10-bit data input.
1O-bit data output.
25161b102
FUNCTION TABLES
IDT54/74FBT2827AlB (Non-lnverting)(I)
OE1
L
L
H
X
Inputs
OE2
L
L
X
H
I DT54/74FBT2828A1B (Inverting)(I)
Output
01
L
H
X
X
VI
L
H
Z
Z
OE1
L
L
H
X
FUnction
Transparent
3-5tate
NOTE:
1. H = HIGH, L = LOW, X = Don't Care, Z = High Impedance
2516tbl03
Inputs
OE2
L
L
X
H
Output
01
L
H
X
X
VI
H
L
Z
Z
Function
Transparent
3-5tate
NOTE:
25161b104
1. H = HIGH, L = LOW, X = Don't Care, Z = High Impedance
6.54
2
IDT54174FBT2827AlBIIDT54174FBT2828A1B
HIGH SPEED BICMOS 10-BIT MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal
Voltage with
Respect to GND
VTERM(3) Terminal
Voltage with
Respect to GND
Com'l.
-0.5 to +7.0
CAPACITANCE
Mil.
Unit
-0.5 to +7.0
V
-0.5 to Vcc
-0.5 to Vcc
V
oto +70
-55 to +125
°C
TA
Operating
Temperature
TBIAS
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
PT
Temperature
Under Bias
Storage
Temperature
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
TSTG
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Symbol
Condition
Typ.
Unit
CIN
Input Capacitance
VIN= OV
6
pF
COUT
Output
Capacitance
VOUT= OV
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
2516 tbl 07
NOTES:
2516tbl06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those Indicated in the operational sections of this specification is not
Implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty. No terminal voltage may exceed Vee by +O.5V
unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = O.2V; VHC = VCC - O.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 10%; Military: TA = -55°C to +125°C, VCC ... 5.0V ± 10%
Symbol
Test Condltlon(1)
Parameter
Min.
2.0
Typ,(2)
-
Max.
Unit
-
V
VIH
Input HIGH Level
Guaranteed Logic High Level
VIL
Input LOW Level
Guaranteed Logic Low Level
IIH
III
10ZH
Input HIGH Current
Input LOW Current
High Impedance
Vcc= Max.
Vcc= Max.
Vcc = Max.
IOZl
Output Current
II
Input HIGH Current
Clamp Diode Voltage
Vee = Max., VI = 5.5V
Vee = Min., IN = -18mA
-
Output Drive Current
Vce = Min., Vo = 2.25V
-35
-
Output Drive Current
Vee = Min., Vo = 2.25V
Vee = Max., Vo = GND(3)
50
-
-
-
-225
VIK
100H
100l
los
Short Circuit Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VI =2.7V
VI = 0.5V
Vo = 2.7V
Vo = 0.5V
-60
Vee= Min.
VIN = VIH or Vil
Vee= Min.
VIN = VIH or Vil
-
Input Hysteresis
Quiescent Power
Supply Current
Vee = Max.
VIN = GND or Vee
-0.7
0.8
V
10
-10
50
-50
~
100
-1.2
~
V
mA
mA
mA
V
IOH = -300~(4)
VHC
Vce
-
IOH = -1mA
2.4
3.3
IOH = -12mA
IOl = 300~(4)
2.0
3.2
-
10l = 1mA
-
IOl = 12mA
VH
lecH
Iccz
lecl
-
-
GND
0.1
VlC
V
0.5
0.35
0.8
-
200
-
mV
-
0.2
1.5
mA
NOTES:
1. For condition shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This condition is guaranteed but not tested.
6.54
~
~
2516tbl05
3
IDT54174FBT2827 AlBIIDT5417 4FBT2828A1B
HIGH SPEED BICMOS 10-BIT MEMORY DRIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
~Iee
Quiescent Power Supply Current
(Inputs
-.. ---.-.
Test Condition(1)
Parameter
Vee = Max.
VIN = 3.4v(3)
TTL HIGH)
--~~~'-'
...
Min.
Typ.
Max.
Unit
-
0.5
2.0
mA
mAl
MHz
IceD
Dynamic Power Supply Current(4)
Vee = Max., Outputs Open
OEl = OE2 = GND
One Input Toggling
50% Duty Cycle
VIN= Vee
VIN = GND
-
0.15
0.25
Ie
Total Power Supply Current(6)
Vee = Max., Outputs Open
fi = 10MHz, 50% Duty Cycle
VIN = Vee
VIN = GND
-
1.7
4.0
OEl = OE2 = GND
One Bit Toggling
VIN = 3.4V
VIN = GND
-
2.0
5.0
Vee Max., Outputs Open
fi = 2.5MHz, 50% Duty Cycle
VIN = Vee
VIN = GND
-
4.0
7.8(5)
OEl = OE2 = GND
Ten Bits Toggling
VIN = 3.4V
VIN = GND
-
6.5
17.8(5)
=
NOTES:
1. For condition shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vce or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT = INPUTS + IDYNAMIC
Ic = Icc + t.lce DHNT + ICCD (fcP/2 + fi Ni)
Icc = Quiescent Current
t.lcc = Quiescent Current
DH = Duty Cycle for a TTL High Input (VIN = 3.4V)
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in MHz.
mA
2516 tbl 08
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FBT2827A
Symbol
Parameter
Commercial
Min,(2)
Max.
FBT2827B
Military
Min.(2)
Max.
Commercial
Min.(2)
Max.
Military
Mln.(2)
Max.
tPHL
tPLH
Prop Delay, Di to VI
1.5
7.0
1.5
7.5
1.5
5.0
1.5
6.5
tPZH
tPZL
Output Enable Time OE to VI
1.5
13.0
1.5
14
1.5
8.0
1.5
9.0
tPHZ
tPLZ
Output Disable Time OE to VI
1.5
13.0
1.5
14
1.5
7.0
1.5
8.0
FBT2828B
FBT2828A
Symbol
Parameter
Commercial
Min.(2)
Max.
Military
Mln.(2)
Max.
Commercial
Mln.(2)
Max:.
Military
Min.(2)
Max.
tPHL
tPLH
Prop Delay, Di to VI
1.5
8.0
1.5
8.5
1.5
5.5
1.5
6.5
tPZH
tPZL
Output Enable Time OE to VI
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
tPHZ
tPLZ
Output Disable Time OE to VI
1.5
14.0
1.5
15.0
1.5
7.0
1.5
8.0
NOTES:
2516tbl09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
6.54
4
~~
IDT54/74FBT2841 A
IDT54/74FBT2841 B
HIGH-SPEED BiCMOS
10-BIT MEMORY
LATCHES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 2S!! output resistors reduce overshoot and undershoot
when driving MaS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TTL compatible input and output levels
• Low power in all three states
• ± 10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD-883, Class B
The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54174FBT2841 series are 3-state, 10-bit latches
where each output is terminated with a 25Q series resistor.
The FBT series of memory line drivers are ideal for use in
designs needed to drive large capacitive loads with low static
(DC) current loading. They are also designed for rail-to-rail·
output switching. This higher output level in the high state will
result in a significant reduction in overall system power
dissipation.
FUNCTIONAL BLOCK DIAGRAM
01
Do
02
04
03
09
DB
250
Yo
Y2
Y1
YB
Y9
2599 drw01
PIN CONFIGURATIONS
DE
Do
01
D2
D3
04
D5
Ds
D7
DB
D9
GND
Vee
INDEX
Yo
Y1
Y2
V3
Y4
Y5
Ys
Y7
YB
Y9
LE
D2
D3
04
NC
D5
. Ds
D7
~
0
IUJ 0
g
0
~
ooOZ>>->L....JL-JL.....JIIL....JL.....JL....J
4 3 2 I 12B 27 2S
LJ
25 [
]5
1
24[
]S
23 [
J7
L28-1
22 [
]B
]9
21[
] 10
20[
19 [
J 11
12
13
14
15
lS
17
1B
rI,.....,'-" r-,,......,..,..,
a)
010 oUJ
Ola)
OOZZ"">->-
Y2
Y3
Y4
NC
Y5
Ys
Y7
2599 drw 02
(!)
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
BiCEMOS is a trademar1< of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101992 Integrated Device Technology, Inc.
6.55
APRIL 1992
DSC·601413
1
IDT54174FBT2841 AlB
HIGH-SPEED BiCMOS 10-BIT MEMORY LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Name
I/O
00-09
I
The latch data inputs.
LE
I
The latch enable input. The latches are transparent when LE is HIGH. Input data is latched
on the HIGH-to-LOW transition.
Description
Inputs
VO-V9
0
The 3-state latch outputs.
OE
I
The output enable control. When OE is LOW,
the outputs are enabled. When OE is HIGH,
the outputs VI are in the high-impedance (off)
state.
Internal
Outputs
OE
LE
01
QI
VI
H
X
X
X
Z
Function
HighZ
H
H
L
L
Z
HighZ
H
H
H
H
Z
HighZ
H
L
X
NC
Z
Latched (High Z)
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Latched
2599 tbl 05
NOTE:
2599 tbl 06
1. H = HIGH, L", LOW, X = Don't Care, NC = No Change, Z '" High
Impedance
LOGIC SYMBOL
D
D
LE
LE------'
OE _ _ _ _ _ _ _ _- - J
2599 dtw 03
CAPACITANCE (TA = +25°C, f"" 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
Operating
TA
Temp_erature
TBIAS
Temperature
Under Bias
Storage
TSTG
Temperature
Power Dissipation
PT
DC Output Current
lOUT
NOTES:
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to Vee
-0.5 to Vee
Symbol
Conditions
Input Capacitance
COUT
Output Capacitance VOUT= OV
NOTE:
V
Parameter(1)
CIN
VIN = OV
Typ.
Max. Unit
6
10
pF
8
12
pF
2599 tbl 02
1. This parameter is measured at characterization but not tested.
o to +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
0.5
120
0.5
120
rnA
___
W
2599 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vee by +O.5V unless otherwise noted.
2. Inputs and Vee terminals only.
3. Outputs and 110 terminals only.
6.55
, .
2
IDT54174FBT2841 AlB
HIGH-SPEED BICMOS 10-BIT MEMORY LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC ... O.2V; VHC = Vce. - O.2V
Commercial: TA = O°C to +70°C, Vcc = 5.0V ±10%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Symbol
VIH
Vil
IIH
ilL
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
10ZH'
IOZl
II
VIK
100H
100l
los
VOH
High Impedance
Output Current
Input HIGH Current
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Short Circuit Current
Output HIGH Voltage
VOL
VH
leeH
leez
leel
Output LOW Voltage
Input Hysteresis
Quiescent Power
Supply Current
Test Condltlons(1)
Guaranteed Logic HIGH Level
Guaranteed Logic lOW Level
Min.
Typ.(2)
Max.
Unit
2.0
-
-
-
-
V
V
-
Vee = Max., VI = 2.7V
Vee = Max., VI= 0.5V
-
Vee = Max.
Vo=2.7V
Vo= 0.5V
-
-
Vee = Max., Vee (Max.)
Vee = Min., IN = -18mA
Vee;" Min., Vo= 2.25V
Vee = Min., Vo = 2.25V
Vee = Max .. Vo = GND(3)
Vee = Min.
VIN = VIH or VIL
IOH = -300JlA (4)
IOH=-1mA
10H =-8mA
10H =-12mA
10L = 3001JA(4)
Vee= Min.
VIN = VIH or VIL
10L = 1mA
10L = 12mA
Vee= Max.
.VIN = GND or Vee
-35
50
-75
VHe
2.7
2.4
2.0
-
-
-0.7
-
0.8
10
-10
50
-50
100
-1.2
-
-225
Vee
3.8
3.3
3.2
GND
0.1
0.35
200
0.2
NOTES:·
.
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V,+25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This condition is guaranteed but not tested.
6.55
-
JlA
JlA
JlA
JlA
V
mA
mA
mA
V
VLe
0.5
0.8
1.5
V
mV
mA
2599tbl03
3
IDT54n4FBT2841AlB
HIGH·SPEED BICMOS 10-BIT MEMORY LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Test Condltlons(1)
Alec
Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)
IceD
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
Ie
Typ.(2)
Min.
Vee. Max.
VIN _ 3.4v(3)
-
0.5
Max.
2.0
0.3
0.4
Vee ... Max., Outputs Open
OE .. GND
One Input Toggling
LE ... Vee
50% Duty Cycle
VIN. Vee
VIN .. GND
-
Vee = Max., Outputs Open
1i ... 10MHz, 50% Duty Cycle
VIN = Vee
VIN =GND
-
3.2
5.5
OE .. GND, LE .. Vee
One Bit Toggling
VIN ... 3.4V
VIN- GND
-
3.5
6.5
Vee - Max., Outputs Open
1i = 2.5MHz, 50% Duty Cycle
VIN- Vee
VIN =GND
-
7.7
11.5(5)
VIN .. 3.4V
VIN=GND
-
10.2
21.5(5)
=
OE = GND, LE Vee
Ten Bits Toggling
Unit
mA
mAl
MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc ,. 5.0V, +25°C ambient
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT +IINPUTS + IOYNAMIC
Ic = Icc + alccDHNT + Icco(fcp/2 + fiNi}
Icc = Quiescent Current
alcc = Power Supply Current for a TIL High Input (VIN .. 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
mA
2599 tbl 04
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54174FBT2841B
54174FBT2841A
Com'l.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
01 to YI (LE .. HIGH)
Condltlon(1)
CL= 50pF
RL= soon
Mil.
Mln.(2)
Max.
Mln.(2)
1.5
9.0
1.5
-
3.0
tsu
Data to LE Set-up Time
2.5
tH
Data to LE Hold Time
2.5
tPLH
tPHL
Propagation Delay
LEtoYI
1.5
tw
LE Pulse Width(3)
HIGH
4.0
tPZH
tPZL
Output Enable Time
OE tOYI
1.5
tPHZ
tPLZ
Output Disable Time
OE toYI
1.5
10.0
-
Mil.
MlnJ2)
Max.
Mln.(2)
Max.
Unit
1.5
6.5
1.5
7.5
ns
2.5
-
2.5
-
ns
2.5
-
2.5
13.0
1.5
8.0
1.5
5.0
-
4.0
-
4.0
-
ns
11.5
1.5
13.0
1.5
8.0
1.5
8.5
ns
8.0
1.5
10.0
1.5
7.0
1.5
7.5
ns
-
10.5
ns
1.5
12.0
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed, but not tested.
2.5
Max.
Com'l.
ns
2599 tbl 07
6.55
4
3.3V LOGIC AND 5V-TO-3.3V
TRANSLATOR PRODUCTS
II
3.3V LOGIC AND 5V-3.3V TRANSLATOR PRODUCTS
The demand for 3.3V logic functions is increasing dramatically. In particular, the introduction of 3.3V processors,
coupled with the availability of 3.3V ASIC and RAM, has fueled
a rapid growth in 3.3V portable personal computer and workstation development. lOT's new 3.3V bus interface logic
devices, (74FCT163xxxand the 74FCT3xxx) and 5V-to-3.3V
translator (74FCT1642457) are designed to support the exploding demand generated by these new systems. The
translator chip, in particular, solves the designer's number one
problem when designing with 3.3V; how to interface 3.3V and
5V on a single bus. lOT offers 3.3V logic in both Octal and
Double Density configurations. Pinouts andACspecifications
of both configurations match those of available 5V functions.
3.3V Standard Logic Functions
lOT's new family of 3.3V logic devices has been developed
on today's advanced sub-half-micron CEMOS process, providing low-voltage compatibility without sacrificing high performance. The 3.3V family consists of functions offered in
20-, 24-, 48-, and 56-pin new fine-pitch Shrink Small Outline
Packages (SSOP). Both the Double Density and the Octal
3.3V functions have the same function and pin-outs as their 5V
counterparts, making it easy to upgrade existing designs. AC
specifications also match those of the 5V FCT functions.
Because of the high speeds, the 3.3V logic family is the ideal
choice for redesigned 5V systems, especially those that
maintain clock rates above 25M Hz. lOT's 3.3V products have
been designed to operate from a regulated 3.3V supply and
are not simply "recharacterized" or "derated" 5V CMOS products. All 3.3V products will also operate functionally with Vcc
as low as 2.5V, making them an excellent choice for nonregulated, battery operated system applications.
5V-to-3.3V Bidirectional Translator
The 5V-to-3.3V translator chip was developed to complement the 3.3V-only products, providing an immediate solution
to the problems incurred from interfacing 5V to 3.3V logic. It is
clear that not all components required to complete a 3.3V
system are immediately available. Therefore, initial systems
will require some combination of 3.3V and 5V components,
creating a need for logic voltage translation. In bidirectional
applications, there is an inherent problem; since all 3.3V
drivers have a parasitic diode to Vcc, there is a chance that a
5V signal will source current into the 3.3V device (specifically
when the 5V signal is >3.3V + Vd).lf maximum current ratings
are exceeded, the 3.3V device can be damaged. lOT's
translator can also serve as an interface between a 3.3V
system and 5V peripherals.
5V-to-3.3V Unidirectional Translators
In many applications, there is a need to communicate
directly from 5V components to 3.3V components. In these
unidirectional applications, standard unidirectional 3.3V-only
functions can operate as effective voltage translators. Because lOT's Octal and Double Density 3.3V logic has no input
clamp diodes to Vcc and high breakdown voltages, the inputs
can easily be driven by 5V signals without any system problems. lOT's unidirectional 3.3V devices make excellent oneway 5V-to-3.3V translators.
II
7.0
TABLE OF CONTENTS
PAGE
3.3V LOGIC AND 5V-to-3.3V TRANSLATORS
3.3V LOGIC
IDTS4174FCT163244
IDTS4/74FCT16324S
IDTS4/74FCT163373
IDTS4/74FCT16337 4
IDTS4/74FCT163S01
IDTS4/74FCT163646
IDTS4/74FCT3244
IDTS4/74FCT324S
3.3V 16-Bit Non-inverting Buffer/Line Driver w/Resistors ..........................................
3.3V 16-Bit Non-inverting Transceiver w/Resistors ...................................................
3.3V 16-Bit Non-inverting Transparent Latch 21Resistors & 3-State .........................
3.3V 16-Bit Register w/Resistors and 3-State ...........................................................
3.3V 18-Bit Non-inverting Registered Transceiver w/Resistors .................................
3.3V 16-Bit Non-inverting Registered Transceiverw/ Resistors................................
3.3V Octal Buffer/Line Driver .....................................................................................
3.3V Octal Transceiver ..............................................................................................
7.1
7.2
7.3
7.4
7.S
7.6
7.7
7.8
BIDIRECTIONAL 5V-to-3.3V TRANSLATORS
IDTS4/74FCT16424ST
SV-to-3.3V 16-Bit Translating Transceiver ................................................................
7.9
UNIDIRECTIONAL 5V-to-3.3V TRANSLATORS
IDTS4/74FCT163244
IDTS4/74FCT163373
IDTS4/74FCT163374
IDTS4/74FCT3244
SV-to-3.3V 16-BitTranslating Buffer/Line Driver .......................................................
SV-to-3.3V 16-Bit Translating Transparent Latch ......................................................
SV-to-3.3V 16-Bit Translating Register ......................................................................
SV-to-3.3V Octal Translating Buffer/Line Driver ........................................................
7.10
7.10
7.10
7.10
•
7.0
3
f;J
3.3V CMOS 16-BIT
BUFFER/LINE DRIVER
PRELIMINARY
IDT54/74FCT163244/A
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54174FCT163244/A 16-bit buffer/line drivers are
built using advanced CEMOS, dual metal CMOS technology.
These high-speed, low-power: devices offer buslbackplane
interface capability with improved packing density. These
devices have a flow-through organization for ease of board
layout. The three-state controls are designed to operate these
devices in a Quad-Nibble, Dual-Byte or single 16-bit word
mode. All inputs are designed with hysteresis for improved
noise margin.
The inputs of IDT54/74FCT163244/A can be driven from
either 3.3V or 5V devices. This feature allows the use of these
devices as translators in a mixed 3.3V/5V supply system.
Thus, the IDT54/74FCT163244/A can be used as buffers to
connect 5V components to a 3.3V bus.
•
•
•
•
•
•
•
•
0.5 MICRON CEMOSTM Technology
Typical tSK(O) (Output Skew) < 250ps
Can serve as 5V to 3.3V translator
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
25 mil Center SSOP and Cerpack Packages
Extended commercial range of -40°C to +85°C
Vee = 3.3V ±D.3V
CMOS power levels (0.16mW typo static)
Rail-to-Rail output swing for increased noise margin
Military product compliant to MIL-STD-883, Class B
Low Ground Bounce (0.3V typ.)
Inputs (except flO) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
10E
30E
1A1
1Y1
3A1
3Y1
1A2
1Y2
3A2
3Y2
1A3
1Y3
3A3
3Y3
1A4
1Y4
3A4
3Y4
40E
20E
2A1
2Y1
2A2
2Y2
2A3
2Y3
2A4
4A1
4Y1
4A2
4Y2
4A3
4Y3
4A4
2Y4
4Y4
2532 drw 02
2532 drw 01
CEMOS is a trademari< of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)·
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
.• Vce = 3.3V ±O.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
.• Low Ground Bounce (0.3V typ.)
• Inputs (except 1/0) can be driven by 3.3V !lr 5V
components
The IDT54!74FCT163245/A 16-bit transceivers are built
using advanced CEMOS, dual metal CMOS technology.
These high-speed, low-power transceivers are ideal for syn.. chronous communication between two busses (A and B). The
Direction and Output Enable controls are designed to operate
these devices as either two independent 8-bit transceivers or
one 16-bit transceiver. The direction control pin (xDIR)
controls the direction of data flow. The output enable pin
(xOE) overrides the direction control and disables both ports.
All inputs are designed with hysteresis for improved noise
margin:
The xDIR and xOE control inputs of these transceivers can
be driven from either 3.3V or 5V devices. This feature allows
added flexibility when used in a mixed 3.3V/5V supply environment.
FUNCTIONAL BLOCK DIAGRAM
1DIR
2DIR
20E
10E
2A1
1A1
1B1
2B1·
1A2
2A2
1B2
2B2
1A3
2A3
283
183
1A4
2A4
284
184
1As
2As
28s
18s
1As
2As
2Bs
18s
1A7
2A7
287
187
··1As
2As
28s
1Bs
2554 drw 02
2554 drw 01
CEMOS is a trademali< 01 Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
el~92
Integrated DeVice Technology, Inc.
7.2
MAY 1992
050-463412
1
IDT54174FCT163245!A
3.3V CMOS 16·BIT BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
10E
1DIR
1
48
1m:
181
2
47
1A1
181
2
47
1A1
182
3
46
1A2
GND
4
45
GND
183
5
44
184
6
43
Vee
7
185
8
186
182
3
46
1A2
GND
4
45
GND
1A3
183
5
44
1A3
1A4
184
6
43
1A4
42
Vee
Vee
7
42
Vee
41
1A5
185
8
41
1A5
9
40
1A6
186
9
40
1A6
GND
10
39
GND
GND
10
39
GND
187
11
38
1A7
187
11
38
1A7
18a
12
8048·1 37
1Aa
18a
12
37
1Aa
281
13
36
2A1
281
13
36
2A1
282
14
35
2A2
282
14
35
2A2
GND
15
34
GND
GND
15
34
GND
283
16
33
2A3
283
16
33
2A3
E48·1
284
17
32
2A4
284
17
32
2A4
Vee
18
31
Vee
Vee
18
31
Vee
285
19
30
2A5
285
19
30
2A5
20
29
2A6
GND
286
20
29
2A6
286
GND
21
28
GND
GND
21
28
287
22
27
2A7
287
22
27
2A7
28a
23
26
2Aa
28a
23
26
2Aa
2DIR
24
25
20E
2DIR
24
25
20E
2554drw 03
2554drw04
SSOP
TOP VIEW
CERPACK
TOP VIEW
7.2
2
•
IDT54J74FCT163245/A
3.3V CMOS 16-BIT BIDIRECTIONAL TRANSCEIVERS·
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xCJE
xDIR
Direction Control Input
xAx
Side A Inputs or 3-State Outputs
xBx
Inputs
Description
Output Enable Input (Active LOW)
xOE
xDIR
L
L
Side B Inputs or 3-State Outputs
2554 tbl Ot
Outputs
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H·
X
High Z State
NOTE:
2554 tbl 02
1. H a HiGH Voltage Level
L = LOW Voltage Level
X - Don't Care
Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage'
with Respect to
GND
VTERM(4) Terminal Voltage
with Respect to
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
Commercial
-0.5 to +4.6 -0.5 to +4.6
-0.5 to +7.0
-0.5 to +7.0
-0.5 to
Vcc+ 0.5
-0.5 to
Vcc+ 0.5
V
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Bias
Storage
Temperature
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
Power Dissipation
lOUT
DC Output
Current
NOTES:
1/0
Conditions
VIN = OV
Tyf!.
4.5
Max.
6.0
Unit
pF
VOUT= OV
5.5
8.0
pF
Capacitance
NOTE:
Operating
Temperature
PT
ala
V
TA
TSTG
Parameter(1)
Symbol
ON
Input
Capacitance
Unit
V
1.0
1.0
W
-60 to +60
-60 to +60
mA
2554 Ink 04
1. This parameter is measured at characterization but not tested.
2554 1M 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi, , tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Vee terminals.
3. Input terminals.
4. Output and 1/0 terminals.
7.2
3
IDT54n4FCT163245/A
3.3V CMOS 16-BIT BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 3.3V -+ O.3V; Military: TA = -55°C to +125°C, VCC = 3 3V ±O 3V
Symbol
VIH
Parameter
Input HIGH Level (Input pins)
Test Condltlons(1)
.Guaranteed Logic HIGH Level
Input HIGH Level (110 pins)
Vil
Input LOW Level
Min.
Typ.(2)
Max.
Unit
2.0
-
5.5
V
2.0
-
Vee+0.5
-D.5
-
0.8
V
±5
~
"""
Guaranteed Logic LOW Level
(Input and I/O pins)
IIH
III
Input HIGH Current (110 pins)
VI '" Vee
-
Input LOW Current (Input pins)
VI =GND
-
Input LOW Current (110 pins)
VI=GND
-
-"
-
Input HIGH Current (Input pins)
VI", 5.5V
Vee = Max.
10lH
High Impedance Output Current
lOll
(3-State Output pins)
Vee", Max.
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
100H
Output HIGH Current
Vee = 3.3V, VIN = VIH or Vil. Va = 1.5V(3)
100l
Output LOW Current
Vee = 3.3V, VIN = VIH or Vil. Va = 1.5V(3)
VOH
Output HIGH Voltage
Vee = Min.
VOa Vee
Vo=GND
.,
IOH=-D.1mA
10H = -6mA MIL.
10H = -SmA COM'L.
VIN = VIH or Vil "
Val
Output LOW Voltage
Vee = Min.
10l= 0.1mA
VIN = VIH or VIL
10L= 16mA
10L= 24mA
los
Short Circuit Current(4)
VH
Input Hysteresis
leel
leeH
leel
Quiescent Power Supply Current
Vee = Max., Va = GND(3)
Vee = Max., VIN = GND or Vee
±15
±5
±15
±10
~
±10
-
-D.7
-1.2
V
-36
-60
-110
rnA
50
90
200
rnA
Vee-O.2
-
-
2.4(5)
3.0
-
"-
-
0.2
0.2
0.4
-
0.3
0.5
-60
-135
-240
V
V
rnA
-
150
-
mV
-
0.05
1.5
rnA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 3.3V, +2SoC ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vee - O.6V at rated current.
2554 Irk 05
fI
7.2
4
IDT54174FCT163245/A
3.3V CMOS 16-BIT BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Svmbol
Parameter
..1lee
Quiescent Power Supply Current
Test Condltlons(1)
TTL Inputs HIGH
IceD
VIN = 2.4V(3)
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
xOE = xDIR = GND
Typ.(2)
Max .
Unit
-
2.0
30
IlA
70
500
50
75
'tJ. AI
MHz
-
0.6
2.3
rnA
-
0.6
2.5
Min.
VIN = Vee - 0.6V(3)
Vee = Max.
VIN = Vee
VIN = GND
One Input Toggling
50% Duty Cycle
Ie
Total Power Supply Current(6)
Vee = Max.
VIN = Vee - 0.6V
Outputs Open
VIN = GND
1i =10MHz
50% Duty Cycle
VIN = 2.4V
xOE = xDIR = GND
One Bit Toggling
VIN = GND
Vee = Max.
Outputs Open
1i =2.5MHz
VIN = Vee - 0.6V
VIN = GND
-
2.1
4.7(5)
50% Duty Cycle
xOE = xDIR = GND
Sixteen Bits Toggling
VIN = 2.4V
VIN = GND
-
2.6
8.5(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TIL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laUIEscENT + IINPUTS + IDYNAMIC
Ic = Icc + .1lcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCL. ICCH and Iccz)
.1lcc = Power Supply Current for a TIL High Input
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni= Number of Inputs at fi
2554 tbl 06
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163245
Com'l.
Symbol
Parameter
FCT163245A
Mil.
Com'l.
Mln.l2)
Max.
Condltlon(1)
Mln.l2)
Max.
Mln.(2)
Max.
CL = 50pF
RL= 500n
1.5
7.0
1.5
7.5
1.5
Mil.
Mln.l2)
Max.
Unit
4.6
1.5
4.9
ns
tPLH
tPHL
Propagation Delay
A to B, BtoA
tPZH
tPZL
Output Enable Time
xOEtoA or B
1.5
9.5
1.5
10.0
1.5
6.2
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
x'OEto A or B
1.5
7.5
1.5
10.0
1.5
5.0
1.5
6.0
ns
tPZH
tPZL
Output Enable Time
xDIR to A or B(3)
1.5
9.5
1.5
10.0
1.5
6.2
1.5
6.5
ns
Output Disable Time
xDIR to A or B(3)
tSK(O) Output Skew(4)
1.5
7.5
1.5
10.0
1.5
5.0
1.5
6.0
ns
-
0.5
-
-
0.5
-
0.5
tPHZ
tPLZ
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by deSign.
7.2
ns
2554tbl07
5
t;J
PRELIMINARY
IDT54/74FCT1633731A
3.3V CMOS
16-81T TRANSPARENT
LATCH
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CEMOSTM Technology
The IDT54/74FCT163373/A .16-bit transparent D-type
latches are built using advanced CEMOS, dual metal CMOS
technology. These high-speed, low-power latches are ideal
for temporary storage of data. They can be used for implementing memory address latches, 1/0 ports, and bus drivers.
The Output Enable and Latch Enable controls are organized
to operate each device as two 8-bit latches or one 16-bit latch.
Flow-through organization of signal pins facilitates ease of
layout. All inputs are designed with hysteresis for improved
noise margin.
The inputs of IDT54/74FCT163373/A can be driven from
either 3.3V or 5V devices. This feature allows the use of these
transparent latches as translators in a mixed 3.3V/5V supply
system. With xLE inputs HIGH, the IOT54/74FCT163373/A
can be used as buffers to connect 5V components to a 3.3V
bus.
• Typical tSK(O} (Output Skew) < 2S0ps
• Can serve as SV to 3.3V translator
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vee = 3.3V ±O.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Low Ground Bounce (0.3V typ.)
• Inputs (except 1/0) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
10E
20E
1LE
2LE
101
0
2D1
D
101
201
C
'~
C
________
,
,,_----~-J~
TO 7 OTHER CHANNELS
II
V
TO 7 OTHER CHANNELS
2601 drw02
2601 drwOl
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01992 Integrated Device Technology. Inc.
7.3
MAY 1992
05C·423612
1
IDT54174FCT1633731A
3.3V 16-BITTRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1LE
10E
1
48
1LE
47
101
101
2
47
101
10E
101
2
102
3
46
102
102
3
46
102
GNO
4
45
GNO
GNO
4
45
GNO
103
5
44
103
103
5
44
103
104
6
43
104
104
6
43
104
Vee
7
42
Vee
Vee
7
42
Vee
105
8
41
105
105
8
41
105
106
9
40
106
GNO
10
39
GNO
107
11
38
107
106
9
40
106
GNO
10
39
GNO
107
11
38
107
108
12 5048-1 37
108
108
12
37
108
201
13
36
201
201
13
36
201
202
14
35
202
202
14
35
202
GNO
15
34
GNO
GNO
15
34
GNO
203
16
33
203
203
16
33
203
204
17
32
204
204
17
32
204
E48-1
Vee
18
31
Vee
Vee
18
31
Vee
205
19
30
205
205
19
30
205
206
20
29
206
206
20
29
206
GNO
21
28
GNO
GNO
21
28
GNO
207
22
27
207
207
22
27
207
208
23
26
208
208
23
26
208
~
24
25
2LE
20E
24
25
2LE
2601 drw 03
2601 drw 04
SSOP
TOP VIEW
CERPACK
TOP VIEW
7.3
2
IDT54174FCT163373!A
3.3V 16·BIT TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
xDx
xLE
x~
xOx
Latch Enable Inputs (Active HIGH)
H
H
L
H
Output Enable Inputs (Active LOW)
L
H
L
L
3-State Outputs
X
X
H
Z
xDx
Data Inputs
xLE
xOE
xOx
Outputs
InDuts
Description
Pin Names
2601 tblOl
2601 tbl02
CAPACITANCE (TA= +25°C, f .. 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
VTERM(4) Terminal Voltage
with Respect to
GND
NOTE:
1. H .. HIGH Voltage Level
L .. LOW Voltage Level
X .. Don't Care
Z - High Impedance
Commercial
Military
Unit
-0.5 to +4.6
-0.5 to +4.6
V
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to
Vcc+ 0.5
-0.5 to
Vcc+ 0.5
V
Symbol
Parameter(1)
CIN
Input
Capacitance
CoUT
Output
Capacitance
Conditions
VIN ... OV
Typ.
Max.
6.0
Unit
4.5
Vour ... OV
5.5
8.0
pF
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
1.0
1.0
W
-60 to +60
-60 to +60
rnA
pF
2601 Ink 04
NOTES:
2601 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Vee terminals.
3. Input terminals.
4. Output and I/O terminals.
fI
7.3
3
IDT54174FCT163373/A
3.3V 16·BIT TRANSPARENT LATCH·
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions ARPly Unless Otherwise Specified: . .
Commercial: TA = -40°C to +85°C, Vcc = 3.3V ± O.3V; Military: TA = -55°C to +125°C, Vcc = 3.3V ± O.3V
.. Parameter
Input HIGH.Level (Input pins)
Symbol
VIH
Test Condltlons(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
-
Max.
5.5
2.0
-
Vee+0.5
Guaranteed Logic LOW Level
-0.5
-
0.8
V
±5
J.tA
Input HIGH Level. (I/O pins)
Input LOW Level
VIL
Unit
V
(Input and 110 pins)
Vee =Max.
VI = 5.SV
-
Input HIGH Current (1/0 pins)
VI = Vee
Input LOW Current (Input pins)
VI=GND
Input LOW Current (1/0 pins)
VI = GND
-
-
Vo= Vee
-
-
±10
Vo= GND
-0.7
±10
Input HIGH Current (Input pins)
IIH
IlL
±S
±15
IOZH
High Impedance Output Current
10ZL
(3-State.Output pins)
VIK
Clamp DiodeVoltage
Vee = Min .• liN = -18mA
-
-1.2
V
10DH
Outpu1 HIGH Current
Vee = 3.3V. VIN = VIH or VIL. Vo = 1.5V(3)
-36
-£0
-110
mA
Output LOW Current
Vee = 3.3V. VIN = VIH or VIL. Vo = 1.SV(3)
50
90
200
mA
Output HIGH Voltage
Vee = Min.
IOH = -O.1mA
3.0
Vee .. Min.
IOH = -£mA MIL.
IOH = -BmA COM'L.
IOL=0.1mA
-
V
VIN = VIH or VIL
Vec-0.2
2.4(5)
-
-
0.2
V
VIN = VIH or VIL
IOL= 16mA·
-
0.2
0.4
10DL
VOH
VOL
:
Vee = Max.
..
Output LOW Voltage
IOL=24mA
los
Short Circuit Current(4)
VH
Input Hysteresis
leeL
leeH
leez
Quiescent Power Supply Current
Vee = Max .• Vo = GND(3)
Vee = Max .• VIN = GND or Vee
J.tA
-
0.3
O.S
-£0
-135
-240
mA
-
150
-
mV
O.OS
1.5
mA
2601 Ink 05
NOTES:
1.
2.
3.
4.
5.
±15
For conditions shown as Max. or Min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 3.3V. +2SoC ambient.
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
This parameter is guaranteed but not tested.
VOH = Vcc - O.6V at rated current.
7.3
4
IDT54174FCT163373/A
3.3V 16·BITTRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
dlee
Quiescent Power Supply Current
Test Conditlons(1)
VIN = Vee - O.6V(3)
Vee = Max.
VIN = 2.4V(3)
TTL Inputs HIGH
leeD
Ie
Typ,(2)
Max.
Unit
-
2.0
30
JlA
70
500
50
75
Min.
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
xOE=GND
One Input Toggling
50% Duty Cycle
VIN = Vee
VIN = GND
-
Total Power Supply Current(6)
Vee = Max.
Outputs Open
fi =10MHz
VIN = Vee - 0.6V
-
0.6
2.3
50% Duty Cycle
xOE=GND
xLE= Vee
One Bit Toggling
VIN = 2.4V
VIN = GND
-
0.6
2.5
Vee = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE=GND
xLE = Vee
Sixteen Bits Toggling
VIN = Vee - 0.6V
VIN =GND
-
2.1
4.7(5)
-
2.6
8.5(5)
rnA
VIN = GND
VIN
VIN
=2.4V
=GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .ilcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
.1.lcc = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
7.3
JlAI
MHz
2601 tbl 06
II
5
IDT54n4FCT163373/A
3.3V 16-BIT TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
:
. FCT163373
Com'l.
Symbol
tPLH
tPHl
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu
tH
tw
tSK(O)
FCT163373A
Mil.
Com'l.
Condltlon(1)
Mln.<2)
Max.
Mln,<2)
Max.
Mln,<2)
CL = SOpF.
RL =soon
1.S
8.0
1.S
8.S
1.S
2.0
13.0
2.0
1S.0
1.S
12.0
1.S
Output Disable Time
1.S
7.S
Set-up Time HIGH
or LOW xDx to xLE
Hold Time HIGH
or LOW xDx to xLE
xLE Pulse Width
HIGH
Output Skew(3}
2.0
Parameter
Propagation Delay
xDxto xOx
Propagation Delay
xLEto xOx
Output Enable Time
.
Mil.
Mln.<2)
Max.
Unit
S.2: "
1.S
S.6
ns
2.0
8.S
2.0
9.8
ns
13.S
1.S
6.S
1.S
7.S
ns
1.S
10.0
1.S
S.S
1.S
6.S
ns
-
2.0
-
2.0
-
2.0
-
ns
1.S
-
1.S
-
1.S
-
1.S
-
ns
6.0
-
6.0
-
S.O
-
6.0
-
ns
.-
O.S
-
O.S
-
O.S
-
O.S
Max.
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew ,between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
7.3
ns
2601 tbl07
6
t;J
3.3V CMOS
16-81T REGISTER (3-STATE)
PRELIMINARY
IDT54174FCT163374/A
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CEMOSTM Technology
• Typical tSK(O) (Output Skew) < 2S0ps
The IDT5417 4FCT163374/A 16-bit edge-triggered O-type
registers are built using advanced CEMOS, dual metal CMOS
technology. These high-speed; low-power registers are ideal
for use as buffer registers for data synchronization and storage. The Output Enable (xOE) and clock (xCLK) controls are
organized to operate each device as two 8-bit registers or one
16-bit register with commonclock. Flow-through organization
of signal pins facilitates ease of layout. All inputs are designed
with hysteresis for improved noise margin.
The inputs of IDT54/74FCT163374/A can be driven from
either 3.3Vor 5V devices. This feature allows the use of these
devices as translators in a mixed 3.3V/5V supply system.
Thus, the IDT54174FCT163374/A can be used as an interfacebetween 5V components and a 3.3V bus.
• Can serve as SV to 3.3V translator
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vee = 3.3V ±O.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Low Ground Bounce (0.3V typ.)
• Inputs (except 1/0) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
10E
------- 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vee = 3.3V ±O.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Low Ground Bounce (0.3V typ.)
• Inputs (except 1/0) can be driven by 3.3V or 5V
components
DESCRIPTION:
The IDT5417 4FCT163501/A 18-bit registered transceivers
are built using advanced CEMOS, dual metal CMOS technology. These high-speed, low-power 18-bit registered bus
FUNCTIONAL BLOCK DIAGRAM
~------------------
-------------------~~
~
2776drw01
TO 17 OTHER CHANNELS
CEMOS is a 1rademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
iil1992 Integrated Device Technology, Inc.
7.5
MAY 1992
DSC-463611
1
IDT54174FCT163501/A
3.3\1 18781T REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
GND
OEA8
2
55
CLKAB
LEA8
3
54
B1
A1'
4
53
GND
GND
52
B2
A2
B3
A3
OEAB
LEAB
A1
,GND
51
56
GND
2
55
CLKA8
3
54
81
4
53
GND
5
52
82
6
51
83
1
,50
Vee
Vee
7
50
Vee
49
B4
A4
8
49
84
48
85
As
9
48
85
47
86
A6
10
47
86
46
GND
GND
11
46
GND
45
87
A7
12
45
87
44
8a
A8
13
44
88
14 8056-1 43
89
13
A9
14
43
89
15
42
B10
A10
15
42
810
16
41
811
A11
16
41
811
17
40
812
A12
17
40
812
18
39
GND
GND
18
39
GND
19
38
813
A13
19
38
813
20
37
814
A14
20
37
814
21
815
A15
21
36
815
22
Vee
Vee
22
35
Vee
23
816
A16
23
34
816
24
817
A17
24
33
817
25
GND
GND
25
32
GND
B18
:A18
26
31
818
CLK8A
OE8A
27
30
CLK8A
GND
LE8A
28
29
26
31
27
E56-1
2776drw02
GND
2776 drw 03
ssop
CERPACK
TOP VIEW
TOP VIEW
7.5
2
IDT54n4FCT163501/A
3.3V 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1,4)
PIN DESCRIPTION
Description
Pin Names
InDuts
LEAB
CLKAB
Outouts
Bx
OEAB
A·to-B Outout Enable Inout
'OESA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
L
X
X
X
B-to-A Latch Enable Input
H
H
L
L
H
X
X
H
H
t
t
L
L
H
LEBA
OEAB
Ax
Z
A-to-B Clock Input
H
CLKBA
B-to-A Clock Input
H
L
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
H
L
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs
H
L
L
X
H
B(2)
H
L
H
X
B(3)
CLKAB
2nstbl01
NOTES:
277S tbl 02
1. A-to-B dataflow is shown. B-to-A data flow is similar but uses OESA, LEBA,
and CLKBA.
2. Output level before the Indicated steady-state input conditions were
established.
3. Output level before the Indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
'
L - LOW Voltage Level
X = Don't Care
Z = High Impedance
t = LOW-to-HIGH Transition
CAPACITANCE (TA= +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Commercial
Military
Rating
Symbol
VTERM(2) Terminal Voltage
-0.5 to +4.6 -0.5 to +4.6
with Respect to
GND
VTERM(3) Terminal Voltage
-0.5 to +7.0 -0.5 to +7.0
with Respect to
GND
VTERM(4) Terminal Voltage
-0.5 to
-0.5 to
with Respect to
Vcc+ 0.5
Vcc+ 0.5
GND
-40 to +85 -55 to +125
Operating
TA
Temperature
Temperature
-55 to +125 -65 to +135
TBIAS
Under Bias
-55 to +125 -65 to +150
Storage
TSTG
Temperature
1.0
1.0
Power Dissipation
PT
Unit
V
-60 to +60
rnA
lOUT
NOTES:
DC Output
Current
-60 to +60
Parameter<1}
Svmbol
ON
Input
Capacitance
VO
ClIo
Capacitance
V
Conditions
VIN = OV
Typ.
4.5
Max.
6.0
Unit
pF
VOUT= OV
5.5
8.0
pF
NOTE:
277SInk04
1. This parameter is measured at characterization but not tested.
V
°C
°C
II
°C
W
2nSlnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Vee terminals.
3. Input terminals.
4. Output and 110 terminals.
7.5
3
IDT54n4FCT163501/A
3.3V 18·BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, Vcc = 3.3V ± O.3V; Military: TA
Symbol
VIH
Parameter
Input HIGH Level (Input pins)
=-55°C to +125°C, Vcc= 3.3V ± O.3V
Min.
2.0
Typ.(2)
Guaranteed Logic HIGH Level
-
Max.
5.5
2.0
-
Vcc+0.5
Guaranteed Logic LOW Level
-0.5
-
0.8
V
-.
-
-
±5
J.IA
±15
-
±15
-
±10
-
±10
-0.7
-1.2
V
-36
-60
-110
rnA
50
90
200
rnA
Vec-0.2
-
V
3.0
-
-
-
0.2
V
-
0.2
0.4
Test Condltlons(1)
Input HIGH Level (110 pins)
Vil
Input LOW Level
Unit
V
(Input and 1/0 pins)
IIH
III
Input HIGH Current (Input pins)
Vce= Max.
VI = 5.5V
Input HIGH Current (1/0 pins)
VI = Vce
Input LOW Current (Input pins)
VI =GND
Input LOW Current (1/0 pins)
VI = GND
10ZH
High Impedance Output Current
10Zl
(3·State Output pins)
Vee = Max.
Vo= Vee
Vo=GND
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
100H
Output HIGH Current
Vee = 3.3V, VIN = VIH or Vll, Vo = 1.5V(3)
100l
Output LOW CUrrent
Vee = 3.3V, VIN = VIH or Vll, Vo = 1.5V(3)
VOH
Output HIGH Voltage
Vee = Min.
IOH = -o.1mA
VIN = VIH or Vil
Vee = Min.
IOH = -6mA MIL.
IOH = -SmA COM'L.
IOl= 0.1mA
VIN = VIH or Vil
IOl= 16mA
Val
Output LOW Voltage
IOl= 24mA
los
Short Circuit Current(4)
VH
Input Hysteresis
Vee = Max., Vo = GNO(3)
-
2.4(5)
-60
-
J.IA
0.3
0.5
-135
-240
rnA
150
-
mV
1.5
rnA
Quiescent Power Supply Current
Vee = Max., VIN = GND or Vce
0.05
leel
leeH
leez
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 3.3V, +2S0C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vee - O.6V at rated current.
7.5
±5
2776 Ink 05
4
IDT54n4FCT163501/A
3.3V 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPL V CHARACTERISTICS
Svmbol
dice
Parameter
Quiescent Power Supply Current
Vee = Max.
Test Condltlons(1)
VIN = Vee - 0.SV(3}
VIN = 2.4V(3}
TTL Inputs HIGH
IceD
Ie
Min.
Typ.(2)
-
2.0
Max.
30
70
sao
SO
100
Dynamic Power Supply
Current<4}
Vee = Max.
Outputs Open
OEAB = OEBA = Vee
orGND
SO% Duty Cycle
One Input Toggling
VIN = Vee
VIN = GND
-
Total Power Supply Current<6}
Vee = Max.
Outputs Open
fep = 10MHz (CLKAB)
SO% Duty Cycle
OEAB = "O'ESA = Vee
LEAB = GND
fi = SMHz
SO% Duty Cycle
One Bit Toggling
VIN = Vee - O.SV
VIN = GND
-
0.7
2.S
VIN = 2.4V
VIN = GND
-
0.7
3.0
VIN = Vee - O.SV
VIN = GND
-
3.1
s.a(5}
VIN = 2.4V
VIN = GND
-
3.7
11.3(5}
Vee = Max.
Outputs Open
fep = 10MHz (CLKAB)
50% Duty Cycle
OEAB = 0E8A = Vee
LEAB = GND
fi =2.5MHz
SO% Duty Cycle
Eighteen Bits Toggling
~
!lAI
MHz
rnA
2776tb108
NOTES:
1.
2.
3.
4.
5.
6.
Unit
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, +25°C ambient.
Per TIL driven input; all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + .:llcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl, ICCH and Iccz)
.:llcc = Power Supply Current for a TIL High Input
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = DynamiC Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
7.5
II
5
IDT54n4FCT163501/A
3.3V 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163501
Com'l.
Symbol
Parameter
Condltlon(l)
fMAX
CLKAB or CLKBA frequency(3)
tPLH
tPHL
Propagation Delay
Ax to Bx or Bx to Ax
=50pF
RL =500n
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
OEBA to Ax,
Mln.l2)
FCT163501A
Mil.
Max.
Mln.(2)
Com'l.
Max.
Mln.l2)
Mil.
Max.
Mln.l2)
Max.
Unit
-
100
-
100
-
150
-
150
MHz
1.5
6.5
1.5
7.5
1.5
5.1
1.5
5.6
ns
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
1.5
7.5
1.5
8.0
1.5
5.6
1.5
6.0
ns
1.5
8.0
1.5
9.0
1.5
5.6
1.5
6.0
ns
Output Enable Time
OEAB to Bx
1.5
8.0
1.5
9.0
1.5
6.0
1.5
6.4
ns
Output Disable Time
OEAB to Bx
1.5
7.5
1.5
8.0
1.5
5.6
1.5
6.0
ns
Set-up Time HIGH or LOW
Ax to CLKAB Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
4.0
-
4.0
-
3.0
-
3.0
-
ns
0
-
0
-
0
-
0
-
ns
Set-up Time
HIGH or LOW
Clock
LOW
4.0
-
4.0
-
3.0
-
3.0
-
ns
Ax to LEAB,
Clock
Bxto LEBA
HIGH
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
-
1.5
-
1.5
-
1.5
-
ns
1.5
-
1.5
-
1.5
-
1.5
-
ns
tw
LEAB or LEBA Pulse Width
HIGH(3)
3.0
-
3.0
-
3.0
-
3.0
-
ns
tw
CLKAB or CLKBA Pulse Width
HIGH or LOW(3)
3.0
-
3.0
-
3.0
-
3.0
-
ns
Output Skew(4)
-
0.5
-
0.5
-
0.5
-
0.5
tPHZ
tPLZ
tsu
tH
tsu
tH
tSK(O)
CL
OEBA to Ax,
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
7.5
ns
2776tb107
6
(;)
3.3V CMOS
16-BIT BUS TRANSCEIVER/
REGISTERS
PRELIMINARY
I DT54/74FCT163646/A
Integrated Device Technology, Inc.
FEATURES:
These high-speed, low-power devices are organized as
two independant 8-bit bus transceivers with 3-state D-type
registers. The control circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly
or from the internal storage registers. Each 8-bit transceiverl
register features direction control (xDIR), over-riding Output
Enable control (xOE) and Select lines (xSAB and xSBA) to
select either real-time data or stored data. Separate clock
inputs are provided for A and B port registers. Data on the A
or B data bus, or both, can be stored in the internal registers
by the LOW-to-HIGH transitions at the appropriate clock pins.
Flow-through organization of signal pins facilitates ease of
layout. All inputs are designed with hysteresis for improved
noise margin.
The control inputs of IDTS4/7 4FCT163646/A can be driven
from either 3.3V or 5V devices. This feature allows added
flexibility when used in a mixed 3.3V/5V supply environment.
• 0.5 MICRON CEMOSTM Technology
• Typical tSK(O) (Output Skew) < 2S0ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vee = 3.3V ±0.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Low Ground Bounce (0.3V typ.)
• Inputs (except 1/0) can be driven by 3.3V or SV
components
DESCRIPTION:
The IDTS4174FCT163646/A 16-bit registered transceivers
are built using advanced CEMOS. dual metal CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
lOE
20E
lDIR
2DIR
lCLKBA
2CLKBA
lSBA
2SBA
lCLKAB
2CLKAB
lSAB
2SAB
lBl
lAl
II
2Bl
2Al
~,
~,---------------~~--------------_I
TO 7 OTHER CHANNELS
_______________
~~
_______________J
TO 7 OTHER CHANNELS
2778drwOl
2778drw02
CEM05 is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOt 992 Integrated Device Technology. Inc.
7.6
MAY 1992
05C·4635/1
1
IDT54174FCT163646/A
3.3V 16-BIT BUS TRANSCEIVER/REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
10E
1DIR
1
56
10E
1CLKAB
2
55
1CLK8A 1CLKA8
2
55
1CLK8A
1SAB
3
54
1S8A
1SA8
3
54
1S8A
GND
4
53
GND
GND
4
53
GND
1A1
5
52
181
1A1
5
52
181
1A2
6
51
182
1A2
6
51
182
Vee
7
50
Vee
Vee
7
50
Vee
1A3
8
49
183
1A3
8
49
183
1A4
9
48
184
1A4
9
48
184
1As
10
47
185
1As
10
47
185
GND
11
46
GND
GND
11
46
GND
1A6
12
45
186
1As
12
45
18s
1M
13
44
187
1M
13
44
187
1AB
14 S056-1 43
18B
1AB
14
43
18s
2A1
15
42
281
2A1
15
42
281
2A2
16
41
282
2A2
16
41
282
2A3
17
40
283
2A3
17
40
283
GND
18
39
GND
GND
18
39
GND
2A4
19
38
284
2A4
19
38
284
2As
20
37
285
2As
20
37
285
2A6
21
36
286
2As
21
36
28s
Vee
22
35
Vee
Vee
22
35
Vee
2A7
23
34
287
2A7
23
34
287
2AB
24
33
28B
2As
24
33
28s
GND
25
32
GND
GND
25
32
GND
2SA8
26
31
2S8A
26
31
2S8A
2CLKA8
27
30
27
30
2CLK8A
2DIR
28
29
28
29
20E
2SA8
2CLK8A 2CLKA8
20E
2DIR
E56-1
2778drw04
2778drw03
CERPACK
TOP VIEW
SSOP
TOP VIEW
7.6
2
IDT54174FCT163646/A
3.3V 16·BIT BUS TRANSCEIVER/REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA= +2SoC, f = 1.0MHz)
Parameter 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vee = 3.3V ±0.3V
• CMOS power levels (0.16mW typo static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
• Inputs (except I/O) can be driven by 3.3V or 5V
components
The IDT54/74FCT3244/A octal buffer/line drivers are built
using advanced CEMOS, dual metal CMOS technology. These
high-speed, low-power buffers are designed to be used as
memory data and address drivers, clock drivers, and busoriented transmitter/receivers. The three-state controls are
designed to operate these devices in a dual-nibble or singlebyte mode. All inputs are designed with hysteresis for improved noise margin.
The data(xAx) and output enable (xOE) inputs of these
buffers can be driven from either 3.3V or 5V devices. This
feature enables the IDT54!74FCT3244/A buffers to be used
as 5V to 3.3V unidirectional translators in a 5V/3.3V mixed
supply system.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
lA2
10E
lAl
2Y 4
lA2
2Y3
lA3
lA3
2Y2
lA4
10E
-c{>->-_ _+-_ _ _ 1Yl
lAl
Vee
P20-1
D20-1
8020-2
8020-7
&
lY3
2A2
E20-1
2Yl
GND
lA4
1Y4
2Al
DIP/SOIC/SSOP/CERPACK
TOP VIEW
20E
2Al
2A2
2Y2
2A3
2Y3
~~IQgl~
WWI
3 2
lA2
2A4
20E
lYl
2A4
lY2
2A3
---
2Y4
2Y3
2779 drw 01
IW U
LT
] 4
=]
20 19
18[
lYl
17[
2A4
16[
1Y2
15[
14[
2A3
5
lA3
-] 6
2Y2
J7
lA4
J8
2779 drw 02
L20-2
9 10111213
1Y3
>", C.!l
~<>-~
'" ~ cil
LCC
TOP VIEW
2779 drw 03
CEMOS is a trademarll of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1992 Integrated Device Technology, Inc.
7.7
MAY 1992
DSc-463211
1
IDT54174FCT3244!A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Inj:uts
Pin Names
xOE
3-8tate Output Enable Inputs (Active LOW)
Description
xAx
xYx
Outputs
xOE"
xAx
Data Inputs
L
L
L
3-8tate Outputs
L
H
H
H
X
Z
2779 Ibl 01
xYx
2779 tbl 02
NOTE:
1. H - HIGH Voltage Level
X ~ Don't Care
L - LOW Voltage Level
Z - High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
VTERM(4) Terminal Voltage
with Respect to
GND
CAPACITANCE (TA = +2SoC, f = 1.0MHz)'
Commercial
Military
Unit
-0.5 to +4.6
-0.5 to +4.6
V
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to
Vcc+ 0.5
-0.5 to
Vcc+ 0.5
V
Conditions
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
4.5
6.0
pF
caUT
Output
Capacitance
VOUT= OV
5.5
8.0
pF
Symbol
NOTE:
TA
Operating
Temperature
-40 to +85
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
8torage
Temoerature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
lOUT
DC Output
Current
NOTES:
Parameter(1)
CIN
1.0
1.0
W
-60 to +60
-60 to +60
mA
2779 Irk 04
1. This parameter Is measured at characterization but not tested.
2779 Irk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Vee terminals.
3. Input terminals.
4. Output and 110 terminals.
7.7
II
2
IDT54174FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA - -40°C to+85°C, Vee .. 3.3V ± O.3V; Military: TA ... -55°C to +125°C, Vee"" 3.3V ± O.3V
~mbol
VIH
Parameter
Input HIGH Level (Input pins)
Test CondltJons(1)
Guaranteed Logic HIGH Level
Min.
2.0
2.0 -
Input HIGH Level (VO pins)
Vil
Input LOW Level
(Input and VO pins)
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vee. Max.
-0.5
Typ.(2)
-
Max.
5.5
Unit
V
Vee+0.5
0.8
V
-
±5
!LA
-
±15
VIK
Clamp Diode Voltage
Vee .. Min., liN .. -18mA
-
-fJ.7
-1.2
V
10DH
Output HIGH Current
Vee - 3.3V, VIN. VIHor Vll, VOa 1.5V(3)
-36
-BO
-110
mA
10Dl
Output LPW Current
Vee .. 3.3V, VIN .. VIH or Vll, Va ... 1.5V(3)
50
90
200
mA
VOH
Output HIGH Voltage
Vee ... Min.
IOH ... -o.1mA
3.0
Vee .. Min.
10H=-BmA MIL.
10H .. -SmA COM'L.
IOl .. 0.1mA
-
V
VIN ... VIH or Vil
Vee-0.2
2.4(5)
-
0.2
V
VIN .. VIH or Vil
10l= 16mA'
0.2
0.4
III
VI- Vee
Input LOW Current (Input pins)
VI-GND
Input LOW Current (VO pins)
ViOl GND
10ZH
High Impedance Output Current
10Zl
(3·State Output pins)
Val
ViOl 5.5V
Input HIGH Current (VO pins) .
Output LOW Voltage
Vo- Vee
Vee - Max.
Va. GND
10l= 24mA
los
Short Circuit Current(4)
VH
Input Hysteresis
leel
leeH
leez
Quiescent Power Supply Current
Vee = Max., Va = GND(3)
Vee = Max., VIN .. GND or Vee
-
±10
IlA
±10
-
0.3
0.5
-BO
-135
-240
mA
-
150
mV
-
0.05
1.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee a 3.3V, +2SoC ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vce -O.6V at rated current.
7.7
±5
±15
mA
27791nk05
3
IDT54174FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Svmbol
~Iee
Test Condltlons(1)
VIN = Vee - 0.6V(3)
Parameter
Quiescent Power Supply Current
Vee = Max.
Tvp.(2)
-
2.0
Max.
30
70
500
VIN = Vee
VIN = GND
-
60
85
-
0.7
2.4
-
0.7
2.6
-
1.3
3.3(5)
-
1.5
5.2(5)
VIN = 2.4V(3)
TIL Inputs HIGH
leeD
Min.
Dynamic Power Supply
Current(4)
Vee = Max.
Outputs Open
50% Duty Cycle
xOE"=GND
Total Power Supply Current(6)
Vee = Max.
VIN = Vee - 0.6V
Outputs Open
VIN = GND
Unit
~
~
MHz
One Input Toggling
Ie
mA
fi = 10MHz
50% DLity Cycle
xOE"= GND
One Bit Toggling
VIN = 2.4V
VIN = GND
Vee = Max.
Outputs Open
fi =2.5MHz
VIN
VIN
= Vee = GND
50% Duty Cycle
xOE"= GND
Eight Bits Toggling
VIN
VIN
= 2.4V
= GND
0.6V
2779 tbl 06
NOTES:
1.
2.
3.
4.
5.
6.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, +25°C ambient.
Per TIL driven input; all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + I INPUTS + IDYNAMIC
Ic = Icc + .:llcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl. ICCH and Iccz)
.:llcc = Power Supply Current for a TIL High Input
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
II
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT3244
Com'l.
Symbol
Parameter
FCT3244A
Com'l.
Mil.
Mil.
Condltlon(l)
Mln.(2)
Max.
Mln.(2)
Max.
Mln.t2)
Max.
Mln.(2)
Max.
Unit
CL = 50pF
RL = 500n
1.5
6.5
1.5
7.0
1.5
4.8
1.5
5.1
ns
tPLH
tPHL
Propagation Delay
xAxto xYx
tPZH
tPZL
Output Enable Time
1.5
8.0
1.5
8.5
1.5
6.2
1.5
6.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
7.0
1.5
7.5
1.5
5.6
1.5
5.9
ns
2779 tbl 07
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
7.7
4
t;)®
PRELIMINARY
I DT54!74FCT3245!A
3.3V CMOS OCTAL
BIDIRECTIONAL
TRANSCEIVERS
Integrated DeVice Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CEMOSTM Technology
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
.• 25 mil Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• Vcc = 3.3V ±O.3V
.
• CMOS power levels (0.16mW typo static)
.• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class 8
• Inputs (except 1/0) can be driven by 3.3V or 5V
components
The IDT54/74FCT3245/A octal transceivers are built using
advanced CEMOS, dual metal CMOS technology. These
high-speed, low-power transceivers are ideal for synchronous
communication between two busses (A and 8). The direction
control pin (DIR) controls the direction of data flow. The output
enable pin (DE) overrides the direction control and disables
both ports. All inputs are designed with hysteresis for improved noise margin.
The DIR and DE control inputs of these transceivers can be
driven from either 3.3V or 5V devices. This feature allows
added flexibility when used in a mixed 3.3V/5V supply environment.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
OIR
OE
A1
81
A2
82
A3
83
OIR
Vce
A1
A2
A3
A4
A5
As
A7
As
.OE
81
82
83
84
85
8s
87
8a
P20-1
020-1
S020-2
S020-7
&
E20-1
GND
A4
84
DIP/SOIC/SSOP/CERPACK
TOP VIEW
As
8s
:i:
As
8s
.:;(
ex: 00
0 >
fa
2650 drw 02
LJLJIILJU
3 2 ~ 20 19
A7
87
A3 _J4
A4 =] 5
As - ] 6
As
J7
A7
J8
As
8a
·2650 drw 01
18[
17 [
L20-2
16[
15 [
.
14[
9 10111213
LCC
TOP VIEW
81
82
83
84
8s
2650 drw 03
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1992 Integrated Device Technology. Inc.
7.8
MAY 1992
D9C-423312
1
IDT54174FCT3245/A
3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Inputs
Description
Pin Names
OE'
DIR
L
L
DE
Output Enable Input (Active LOW)
DIR
Direction Control Input
Ax
Side A Inputs or 3-State Outputs
L
H
Bus A Data to Bus B
Bx
Side B Inputs or 3-State Outputs
H
X
High Z State
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X ~ Don't Care
Z = High Impedance
2650 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
Commercial
Military
Unit
-0.5 to +4.6
-0.5 to +4.6
V
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(4) Terminal Voltage
with Respect to
GND
-0.5 to
Vcc+ 0.5
-0.5 to
Vcc+ 0.5
V
Operating
Temperature
-40 to +85
-55 to+125
°C
TSIAS
Temperature
Under Bias
-55 to +125
--65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
--65 to +150
°C
Power Dissipation
DC Output
Current
Symbol
GiN
Gi/o
TA
PT
2650tb102
CAPACITANCE (TA='+25°C, f= 1.0MHz)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
lOUT
Outputs
Bus B Data to Bus A
1.0
1.0
W
--60 to +60
--60 to +60
mA
Parameter(1)
Conditions
=OV
Input
Capacitance
VIN
110
VOUT= OV
Typ.
Max.
Unit
4.5
6.0
pF
5.5
8.0
pF
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
,26501nk04
NOTES:
2650 Ink 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Vee terminals.
3. Input terminals.
4. Output and I/O terminals.
II
7.8
2
IDT54n4FCT3245/A
3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS 'OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -4O°C to +85°C, Vcc = 3.3V ± O.3V; Military: TA = -55°C to +125°C, Vcc = 3.3V ± O.3V
Symbol
VIH
Parameter
Input HIGH Level (Input pins)
Test Condltlons(1)
Guaranteed Logic HIGH Level
Input HIGH Level (VO pins)
VIL
Input LOW Level
Guaranteed Logic LOW Level
Typ,(2)
Max.
Unit
5.5
V
2.0
-
Vee+0.5
-D.5
-
0.8
V
-
±5
IlA
-
±15
Min.
2.0
(Input and I/O pins)
IIH
IlL
Input HIGH Current (I/O pins)
VI = Vee
Input LOW Current (Input pins)
VI =GND
-
-
±5
Input LOW Current (I/O pins)
VI = GND
-
-
±15
Vo= Vee
-
-
±10
Input HIGH Current (Input pins)
10lH
High Impedance Output Current
lOlL
(3-State Output pins)
Vee = Max.
VI = 5.5V
Vee = Max.
Vo= GND
VIK
Clamp Diode Voltage
Vee = Min., liN = -18mA
100H
Output HIGH Current
Vee = 3.3V, VIN = VIH or VIL, Vo= 1.5V(3)
100L
Output LOW Current
Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V(3)
VOH
Output HIGH Voltage
Vee= Min.
IOH=-D.1mA
VIN = VIH or VIL
10H = -6mA MIL.
10H = -8mA COM'L.
Vee = Min.
10L= 0.1mA
VIN = VIH or VIL
10L= 16mA
VOL
Output LOW Voltage
IOL=24mA
los
Short Circuit Current(4)
VH
Input Hysteresis
leeL
IceH
lecl
Quiescent Power Supply Current
Vee = Max., Vo = GND(3)
Vee = Max., VIN = GND or Vee
-D.7
-1.2
V
-36
-60
-110
mA
mA
50
90
200
Vec-0.2
-
V
2.4(5)
3.0
-
-
0.2
V
0.2
0.4
-
0.3
0.5
-135
-240
mA
-
150
-
mV
-
0.05
1.5
mA
-60
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 3.3V, +2SoC ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vcc - O.6V at rated current.
7.8
J.lA
±10
2650lnk05
3
IDT54174FCT3245/A
3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Svmbol
~Iee
Parameter
Quiescent Power Supply Current
Vee
Test Condltlons(1)
VIN = Vee - 0.6V(3)
=Max.
IceD
Ie
Dynamic Power Supply
Current(4)
Total Power Supply Current(6)
Vee .. Max.
Outputs Open
DIR .. GND
One Input Toggling
50% Duty Cycle
VIN ... Vee
VIN .. GND
Vee .. Max.
VIN .. Vee - 0.6V
VIN .. GND
m: ..
Outputs Open
fi .. 10MHz
50% Duty Cycle
Tvp.(2)
2.0
Max.
30
70
500
60
85
Unit
j.IA
'tJ.
AI
MHz
-
0.7
2.4
-
0.7
2.6
VIN .. Vee - 0.6V
VIN = GND
-
1.3
3.3(5)
VIN = 2.4V
VIN = GND
-
1.5
5.2(5)
VIN .. 2.4V
m: .. DIR .. GND
-
VIN .. 2.4V(3)
TTL Inputs HIGH
Min.
rnA
VIN .. GND
One Bit Toggling
Vee =Max.
Outputs Open
fi =2.5MHz
50% Duty Cycle
DE = DIR =GND
Eight Bits Toggling
NOTES:
1.
2.
3.
4.
5.
6.
2650 tbl 06
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, +25°C ambient.
Per TTL driven input; all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + alcc DHNT + ICCD (fcpNcp/2 + fiNi)
Icc = Quiescent Current (ICCl. IccH and Iccz)
alcc = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT3245
Symbol
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
NOTES:
Parameter
Propagation Delay
A to B Bto A
Output Enable Time
DEtoAor B
Output Disable Time
DEtoAor B
Condltlon(l)
. CL = 50pF
RL = 500n
Com'l.
Mln.<2)
Max.
fI
FCT3245A
Mil.
Mln.(2)
Max•
Com'l.
Mln.<2)
Max.
Mil.
Mln.(2)
Max.
1.5
7.0
1.5
7.5
1.5
4.6
1.5
4.9
Unit
ns
1.5
9.5
1.5
10.0
1.5
6.2
1.5
6.5
ns
1.5
7.5
1.5
10.0
1.5
5.0
1.5
6.0
ns
Output Enable Time
DIR to A or B(3)
1.5
9.5
1.5
10.0
1.5
6.2
1.5
6.5
ns
Output Disable Time
DIR to A or B(3)
1.5
7.5
1.5
10.0
1.5
5.0
1.5
6.0
ns
2650 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.8
4
f;J
FAST CMOS 16-BIT
BIDIRECTIONAL
3.3V TO 5V TRANSLATOR
PRELIMINARY
IDT54/74FCT164245T
Integrated Device Technology, Inc.
FEATURES:
This high-speed, low-power transceiver is designed to interface between a 3.3V bus and a 5V bus in a mixed 3.3V/5V
supply environment. This enables system designers to interface TTL compatible 3.3V components with 5V components.
The direction and output enable controls are designed to
operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. The A port interfaces with
the 3.3V bus; the B port interfaces with the 5V bus. The
direction control (xDIR) pin controls the direction of data flow.
The output enable (xOE) overrides the direction control and
disables both ports. These control signals can be driven from
either 3.3V or 5V devices.
The IDT54/74FCT164245T is ideally suited for driving high
capacitance loads and low impedance backplanes. The
output buffers are designed with Power-Off Disable capability
to allow "hot insertion" of boards when used as backplane
drivers. They also allow interface between a mixed supply
system and external 5V peripherals.
• 0.5 MICRON CEMOSTM Technology
• Bidirectional interface between 3.3V and 5V busses
• Control inputs can be driven from either 3.3V
or 5V circuits
• ESD >2000V per MIL-STD-883, Method 3015;
>200V using machine model (C .. 200pF, R .. 0)
• 25 MIL Center SSOP and Cerpack Packages
• Extended commercial range of -40°C to +85°C
• VCC1 .. 5V ±1 0%, VCC2 .. 3.3V ±O.3V
• High drive outputs (-32mA IOH, 64mA IOL) on 5V port
• Power-off disable on both poerts permits "live insertion"
• Typical VOLP (Output Ground Bounce) < 0.9V at
VCC1 .. 5V, VCC2 .. 3.3V, TA .. 25°C
DESCRIPTION:
The IDT5417 4FCT164245T 16-bit 3.3V-to-5V translator is
built using advanced CEMOS, dual metal CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
2DIR
1DIR
20E
10E
2A1
1A1
181
281
1A2
2A2
182
282
1A3
2A3
183
283
~
a: 1A4
0
a..
>
C')
cri
1A5
I-
a: 2A4
I-
184 a:
0
a..
185
0
a..
>
C')
>
LO
cri 2A5
1As
I-
284 a:
0
a..
>
LO
285
2A6
286
186
1M
2A7
187
287
1As
2As
18s
28s
2555 drw01
2555 drw02
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tI:l1992 Integrated Device Technology. Inc.
7.9
MAY 1992
OSC-423411
1
IDT54174FCT164245T
FAST CMOS 16-BIT BIDIRECTIONAL 3.3V-TO-SV TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
lDIA
lDIA
10E
1
48
lOE
181
2
47
lAl
181
2
47
lAl
182
3
46
lA2
182
3
46
lA2
GND
4
45
GND
GND
4
45
GND
183
5
44
lA3
183
5
44
lA3
184
6
43
lA4
VCCl
7
42
VCC2
185
8
41
lA5
184
6
43
lA4
VCCl
7
42
VCC2
185
8
41
lA5
18s
9
40
lAs
18s
9
40
lAs
GND
10
39
GND
GND
10
39
GND
187
11
38
lA7
187
11
18a
12
8048-1 37
lAa
18B
12
281
13
36
2Al
281
282
14
35
2A2
282
GND
15
34
GND
283
16
33
2A3
284
17
32
2A4
VCCl
18
31
VCC2
285
19
30
2A5
28s
20
29
2As
GND
21
28
GND
287
22
27
28a
23
2DIA
24
38
1A7
37
lAB
13
36
2Al
14
35
2A2
GND
15
34
GND
283
16
33
2A3
284
17
32
2A4
VCCl
18
31
VCC2
285
19
30
2A5
E48-1
28s
20
29
2As
GND
21
28
GND
2A7
287
22
27
2A7
26
2Aa
28B
23
26
2AB
25
20E
2DIA
24
25
20E
2555 drw03
2555 drw04
SSOP
TOP VIEW
CERPACK
TOP VIEW
POWER SUPPLY SEQUENCING
ThelDT54/74FCT164245Tinciudescircuitrythatwilipiace
both A and 8 ports in high impedance state if VCC2 ~ VCC1
-0.9volts. IfVcc2isappliedfirst, therewill be current flow from
7.9
VCC2 to VCC1 that will raise VCC1 to VCC2 - 0.6 volts and both
A and 8 ports will maintain high impedance state. In this
condition, the user must insure that absolute maximum ratings
are not violated.
2
II
IDT54174FCT164245T
FAST CMOS 16·BIT BIDIRECTIONAL 3.3V~T0-5V TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
xOE
xDIR
Inputs
Description
Output Enable Input (Active LOW)
xOE
xDIR
L
L
Bus B Data to Bus A
Direction Control Input
Outputs
xAx
Side A Inputs or 3·State Outputs (3.3V Port)
L
H
Bus A Data to Bus B
xBx
Side B Inputs or 3-State Outputs (5V Port)
H
X
High Z State
2555 tbl 01
NOTE:
25551bl03
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
ABSOLUTE MAXIMUMRATINGS(1)
Svmbol
RatlnQ
VTERM Terminal Voltage
with Respect to
GND
CAPACITANCE (TA =
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
-40 to +85
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
--65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
--65 to +150
°C
Power Dissipation
lOUT
DC Output
Current
NOTE.
GIN
CliO
TA
PT
Symbol
Parameter{1}
+25°C, f = 1.0MHz)
Conditions
Typ.
Max.
Unit
Input
Capacitance
VIN = OV
4.5
6.0
pF
110
VOUT= OV
5.5
8.0
pF
Cap_acitance
NOTE:
1.0
1.0
W
--60 to +120
--60 to +120
rnA
25551bl04
1. This parameter is measured at characterization but not tested.
2555 Ibl 02
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
7.9
3
IDT54174FCT164245T
FAST CMOS 16-BIT BIDIRECTIONAL 3.3V-T0-5V TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (A PORT - 3.3V)
Following Conditions Apply Unless Otherwise Specified:
VCC1 = 5V +
- 10%, VCC2 = 3.3V +
- 0.3V; Commercial: TA = -40°C to +85°C, Military: TA = -55°C to +125°C,
Symbol
VIH
VIL
IIH
IlL
Parameter
Input HIGH Level
(Input and I/O pins)
Test Condltlons(1)
Guaranteed Logic HIGH Level
Min.
2.0
Input LOW Level
(Input and 110 pins)
Input HIGH Current (Input pins)
Guaranteed Logic LOW Level
VCC1= Max.
VI= 5.5V
Input HIGH Current (I/O pins)
VCC2= Max.
-
Max.
5.5
Unit
V
-0.5
-
0.8
V
-
-
±5
~
VI= VCC2
-
±15
Input LOW Current (Input pins)
VI=GND
-
-
±5
Input LOW Current (110 pins)
VI= GND
-
-
±15
-D.?
-1.2
V
Vcc2-0.2
-
-
V
2.4(5)
3.0
-
VIK
Clamp Diode Voltage
VCC2= Min., liN = -18mA
VOH
Output HIGH Voltage
VCC1 = Min.
VOL
Typ.(2)
Output LOW Voltage
IOH=-o.1mA
VCC2= Min.
10H = -6mA MIL.
VIN= VIHorVIL
10H = -SmA COM'L.
VCC1 = Min.
10L= 0.1mA
VCC2= Min.
10L= 16mA
VIN= VIHor VIL
IOL=24mA
-
-
0.2
0.2
0.4
VCC1 = Max., VCC2= Max., Vo= GND(3)
-
-100
VCC1 = Max., VCC2= Max., Vo= 2.5V(3)
-
-
10FF
InpuVOutput Power Off Leakage
VCC1 = OV, VCC2 = OV, VIN or Vo S 4.5V
los
Short Circuit Current(4)
10
Output Drive Current
VH
Input Hysteresis
-
0.3
-
V
0.5
±100
~
rnA
-60
-
150
-
mV
2.0
rnA
0.35
VCC1 = Max., VIN= GND or VCC2
Quiescent Power Supply Current
ICC2L
VCC2= Max.
ICC2H
Icc2z
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC1 = 5.0V, VCC2 =3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC2 - O.6V at rated current.
rnA
2555 tbl 05
II
7.9
4
IDT54174FCT164245T
FAST CMOS 16·BIT BIDIRECTIONAL 3.3V·TO-SV TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE {B PORT - 5V}
Following Conditions Apply Unless Otherwise Specified:
0
0
0
VCC1a5iV +10%, VCC2'" 3.3 V ±0.3 V;, Commercla:
. I T
e
e
Iitary: T
A = -55e
,
to e
+85 0 , MT
to +125
A =-40
S~bol
VIH
Vil
IIH
Parameter
Input HIGH Level
(Input and 110 pins)
, Input LOW Level
(Input and 1/0 pins)
Input HIGH Current (Input pins)
Input HIGH Current (110 pins)
III
:
VIK
. VOH
Test Condltlons(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
-
Max.
5.5
Unit
V
Guaranteed Logic LOW Level
-0.5
-
O.B
V
~
VI= VCCl
VCCl = Max.
VCC2= Max.
Input LOW Current (Input pins)
VI=GND
,Input LOW Current (110 pins)
-
-
±5
-
±15
-
-
±15
-
..(J.7
-1.2
V
IOH =--3mA
2.5
3.5
-
V
VCC2= Min.
IOH = -12mA MIL.
2.4
3.5
-
VIN = VIH or Vil
IOH = -15mA COM'L.
2.0
3.0
-
-
0.2
0.55
-
Clamp Diode Voltage
VCCl = Min., liN
9utput HIGH Voltage
VCCl
=-1BmA
=Min .
IOH = -24mA MIL.
IOH = --32mA COM'U5)
IOL = 4BmA MIL.
IOL = 64mA COM'L.
'Input/Output Power Off Leakage
VCCl = Min.,
VCC2= Min.
VIN = VIHor VIL
VCCl = OV, VCC2 = OV, ' VIN or Va::;; 4.5V
±100
~
los
Short Circuit Current(4)
VCCl = Max., VCC2= Max., Vo= GND(3)
-80
-140
-200
mA
VCCl = Max., VCC2= Max., Vo= 2.5V(3)
-50
-75
-1BO
mA
-
150
-
mV
O.OB
1.5
mA
Val
'IOFF
Output LOW Voltage
10
Output Drive Current
VH
Input Hysteresis
ICCll
ICC1H
ICC1Z
Quiescent Power Supply Current
VCCl = Max., VIN = GND or VCC2
VCC2= Max.
-
V
2555 Ibl 06
NOTES:
1.
2.
3.
4.
5
±5
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at VCCl - 5.0V, VCC2 - 3.3V, +25°C ambient
Not more than one output should be tested at one time. Duration of the test should not exceed one second.
This parameter Is guaranteed but not tested.
Duration of the condition can not exceed one second.
7.9
5
IDT54174FCT164245T
FAST CMOS 16·BIT BIDIRECTIONAL 3.3V·T0-5V TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Svmbol
61cc
TTL Inputs HIGH
ICCD
Test Condltlons(1)
Parameter
Quiescent Power Supply Current
Dynamic Power Supply
Current(4)
VCC1 = Max., VCC2 = Max.,
VIN = VCC2 -0.SV(3)
VCC1 = Max., VCC2 = Max
VIN = VCC2
Outputs Open
xOE" = xDIR = GND
VIN = GND
TVD.(2)
Max.
Unit
-
12
30
~
-
75
120
Min.
JlA/
MHz
One Input Toggling
50% Duty Cycle
Ic
Total Power Supply Current(6)
VCCl = Max., VCC2 .. Max
VIN - VCC2 - O.SV
Outputs Open
VIN = GND
-
1.2
4.7
-
3.5
8.5(5)
rnA
fi=10MHz
50% Duty Cycle
xOE = xDIR = GND
One Bit Toggling
VCCl = Max., VCC2 = Max
VIN = VCC2 • O.SV
Outputs Open
VIN = GND
fi =2.5MHz
50% Duty Cycle
xOE = xDIR = GND
Sixteen Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC1= 5.0V, VCC2= 3.3V, +25°C ambient.
3. Per TIL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = ICCl + Icc2 + .1.lcc DHNT + ICCD (fcpNcp/2 + fiNi)
ICCl = Quiescent Current (lcc1 L, Icc1H and ICC1Z)
Icc2= Quiescent Current (ICC2L, ICC2H and Icc2z)
.1.lcc = Power Supply Current for a TIL High Input
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ncp = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
2555 tbl 07
II
7.9
6
IDT54174FCT164245T
FAST CMOS 16-BIT BIDIRECTIONAL 3.3V·TO-SV TRANSLATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Parameter
Propagation Delay
Ato 8
Propagation Delay
8to A
Output Enable Time
xOEto 8
Mil.
Condltlon(1)
Mln'<2)
CL= 50pF
RL= 500n
1.5
Max.
5.0
1.5
Mln.(2)
-
Max.
-
Unit
ns
5.0
-
-
ns
1.5
6.5
-
-
ns
Output Disable Time
xOEto 8
1.5
6.0
-
-
ns
Output Enable Time
xOEtoA
1.5
6.5
-
-
ns
Output Disable Time
xOEto A
Output Enable Time
xDIR to 8(3)
1.5
6.0
-
-
ns
1.5
6.5
-
-
ns
Output Disable Time
xDIR to 8(3)
1.5
6.0
-
-
ns
Output Enable Time
xDIR to A(3)
Output Disable Time
xDIR to A(3)
1.5
6.5
-
-
ns
1.5
6.0
-
-
ns
2555tbl08
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.9
7
G
IDT54/74 FCT3244
IDT54n4FCT163244
IDT54/74FCT163373
IDT54n4FCT163374
5V TO 3.3V UNIDIRECTIONAL
TRANSLATORS
Integrated Device Technology, Inc.
The following 8-bit and 16-bit, 3.3V bus interface parts
serve as unidirectional translators(1l. For detailed specifications, please refer to the individual data sheets for these parts.
5V to 3.3V Unidirectional Translators
Part Number
IDTS4/74FCT3244
IDTS4/74FCT163244
IDTS4/74FCT163373
IDTS4/74FCT163374
Description
Octal 3.3V Buffer/Line Driver
16-Bit 3.3V Buffer/Line Driver
16-Bit 3.3V Transparent Latch
16-Bit 3.3V Register
SV to 3.3V Unidirectional Translators provide a one-way
interface between SV components and 3.3V components
or between SV components and 3.3V bus in a mixed SVI
3.3V supply system as shown in Figure 1.
The Unidirectional Translators accept TTL- or CMOScompatible signals from SV components at the inputs and
provide TTL-compatible output levels. These translators
avoid any problems associated with a direct interface
between a SV component and a 3 .3V component or between
a SV component and a 3.3V bus.
3.3V
3.3V
BUS
SV
I
SV Components
3t
I
V
~
Z
w
Z
oa..
5Vto 3.3V
Unidirectional
Translator
:E
o
o
>
C')
c;w)
II
2662 drw 01
Figure 1. Mixed 5V13.3V System
NOTE:
1. For 3.3V/5V Bidirectional Bus Translators, please refer to the IDT54174FCT164245T data sheet.
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
: a
~ IS ~
6
~
2589 drw 03
PLCC/LCC
TOP VIEW
PIN DESCRIPTIONS
Pin Name
I/O
Description
DI
I
Direct input to register/counter
multiplexer Do is LSB.
and
II
I
Selects one-of-sixteen instructions.
CC
I
Used as test criterion. A LOW on CC
indicates "passed" test condition.
CCEN
I
Whenever the signal is HIGH, CC isJ.9.nored
and the device operates as though CC were
true (LOW).
CI
I
Low order carry input to incrementer for
microprogram counter.
RLD
I
When LOW forces loading of register/
counter regardless of instruction or
condition.
OE
I
Three-state control of YI outputs.
CP
I
Triggers all internal state changes at LOWto-HIGH edge.
YI
a
Address to microprogram memory.
LSB, Y11 is MSB.
FULL
PL
a
a
MAP
a
Can select #2 source (usually Mapping
PROM or PLA) as direct input source.
VECT
a
Can select #3 source (for example, Interrupt
Starting Address) as direct input source.
'ttl is
Indicates that 33 items are on the stack.
Can select #1 source (usually Pipeline
Register) as direct input source.
2589tbiOl
8.1
2
IDT39C10B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
The IDT39C1 Os are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed
microprogram mabie microprocessor applications. The
sequencers allow for direct control of up to 4K words of
microprogram.
The heart of the microprogram sequencers is a 4-input
multiplexer that is used to select one of four address sources
to select the next microprogram address. These address
sources include the register/counter, the direct input, the
microprogram counter or the stack as the source for the
address of the next microinstruction.
The register/counter consists of twelve D-type flip-flops
which can contain either an address or a count. These edgetriggered flip-flops are under the control of a common clock
enable, as well as the four microinstruction control inputs.
When the load control (RLD) is LOW, the data at the D inputs
is loaded into this register on the LOW-to-HIGH transition of
the clock. The output of the register/counter is available at the
multiplexer as a possible next address source for the microcode. Also, the terminal count output associated with the
register/counter is available at the internal instruction PLA to
be used as condition code input for some of the microinstructions. The IDT39C1 Os contain a microprogram counter
that usually contains the address of the next microinstruction
compared to that currently being executed. The microprogram counter actually consists of a 12-bit incrementer followed by a 12-bit register. The microprogram counter will
increment the address coming out of the sequencer going to
the microprogram memory if the carry-in input to this counter
is HIGH; otherwise, this address will be loaded into the
microprogram counter. Normally, this carry-in input is set to
the logic HIGH state so that the incrementer will be active.
Should the carry-in input be set LOW, the same address is
loaded into the microprogram counter. This is a technique that
can be used to allow execution of the same microinstruction
several times.
There are twelve D-inputs on the IDT39C10s that go
directly to the address multiplexer. These inputs are used to
provide a branch address that can come directly from the
microcode or some other external source. The fourth input
available to the multiplexer for next address control is the 33deep, 12-bit wide LIFO stack. The LIFO stack provides return
address linkage for subroutines and loops. The IDT39C10s
contain a built-in stack pointer that always points to the last
stack location written. This allows for stack reference operations, usually called loops, to be performed without popping
the stack.
The stack pointer internal to the IDT39C10s is actually an
up/down counter. During the execution of microinstructions
one, four and five, the PUSH operation may occur depending
on the state of the condition code input. This causes the stack
pointer to be incremented by one and the stack to be written
with the required return linkage (the value contained in the
microprogram counter). On the microprogram cycle following
the PUSH, this new return linkage data that was in the
microprogram counter is now at the new location pointed to by
8.1
the stack pointer. Thus, any time the multiplexer looks at the
stack, it will see this data on the top of the stack.
During five different microinstructions, a pop operation
associated with the stack may occur. If the pop occurs, the
stack pointer is decremented at the next LOW-to-HIGH
transition of the clock. A pop decrements the stack pointer
which is the equivalent of removing the old information from
the top of the stack.
The IDT39C10s are designed so that the stack pointer
linkage allows any sequence of pushes, pops or stack references to be used. The depth of the stack can grow to a full 33
locations. After a depth of 33 is reached, the FULL output goes
LOW. If further PUSHes are attempted when the stack is full,
the stack information at the top of the stack will be destroyed
but the stack pointer will not end around. It is necessary to
initialize the stack pointer when power is first turned on. This
is performed by executing a RESET instruction (Instruction 0).
This sets the stack pointer to the stack empty position - the
equivalent depth of zero. Similarly, a pop from an empty stack
may place unknown data on the Y outputs, but the stack
pointer is designed not to end around. Thus, the stackpointer
will remain at the 0 or stack empty location if a pop is executed
while the stack is already empty.
The IDT39C10s' internal 12-bit register/counter is used
during microinstructions eight, nine and fifteen. During these
instructions, the 12-bit counter acts as a down counter and the
terminal count (count = 0) is used by the internal instruction
PLA as an input to control the microinstruction branch test
capability. The design of the internal counter is such that, if it
is preloaded with a number N and then this counter is used in
a microprogram loop, the actual sequence in the loop will be
executed N + 1 times. Thus, it is possible to load the counter
with a count of 0 and this will result in the microcode being
executed one time. The 3-way branch microinstruction,
Instruction 15, uses both the loop counter and the external
condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way
branch may result in the next address coming from the 0
inputs, the stack or the microprogram counter.
The IDT39C10s provide a 12-bit address at the Y outputs
that are under control of the OE input. Thus, the outputs can
be put in the three-state mode, allowing the writable control
store to be loaded or certain types of external diagnostics to
be executed.
In summary, the IDT39C1 Os are the most powerful microprogram sequencers currently available. They provide the
deepest stack, the highest performance and the lowest power
dissipation for today's microprogrammed machine design.
IDT39C10 OPERATION
The IDT39C10s are CMOS pin-compatible implementations of the Am291 0 and 291 OA microprogram sequencers.
The IDT39C1 O's microprogram is functionally identical except
that it provides a 33-deep stack to give the microprogrammer
more capability in terms of microprogram subroutines and
microprogram loops. The definition of each microprogram
instruction is shown in the table of instructions. This table
3
II
IDT39C10B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
shows the results of each instruction in terms of controlling the
multiplexer, which determines the Y outputs, and in controlling
the signals that can be used to enable various branch address
sources (15[, ~,'ilE"CT). The operation of the registerl
counter and the 33-deep stack after the next LOW-to-HIGH
transition of the clock: . The internal multiplexer is used to
select which of the internal sources is used to drive the Y
outputs. The actual value loaded into the microprogram
counter is either identical to the Y output or the Y output value
is incremented by 1 and placed in the microprogram counter.
This function is under the control of the carry inputs. For each
of the microinstruction inputs, only one of the three outputs
(15[, fJAP, or 'ilE"CT) will be LOW. Note that this function is not
determined by any of the possible condition code inputs.
These outputs can be used to control the three-state selection
of one of the sources for the microprogram branches.
Two inputs, 'C'C' and ccm, can be used to control the
conditional instructions. These are fully defined in the table of
instructions. The 'R[[) input can be used to load the internal
register/counter at any time. When this input is LOW, the data
at the D inputs will be loaded into this register/counter on the
LOW-to-HIGH transition of the clock. Thus, the 'RII) input
overrides the internal hold or decrement operations specified
by the various microinstructions. The DE input is normally
LOW and is used as the three-state enable for the Y outputs.
The internal stack in the IDT39C10s is a last-in/first-out
memory that is 12-bits in width and 33 words deep. It has a
stack pointer that addresses the stack and always points to the
value currently on the top of the stack. When instruction 0
(RESET) is executed, the stack pointer is initialized to the top
of the stack which is, by definition, the stack empty condition.
Thus, the contents of the top of the stack are undefined until
the forced PUSH occurs. A pop performed while the stack is
empty will not change the stack pointer in any way; however,
it will result in unknown data at the Y outputs.
By definition, the stack is full any time 33 more pushes than
pops have occurred since the stack was last empty. When this
happens, the Full Flag will go LOW. This signal first goes LOW
on the microcycle after the 33 pushes occur. When this signal
is LOW, no additional pushes should be attempted or the
information on the top of the stack will be lost.
THE.lDT39C10 INSTRUCTION SET,
This data sheet contains a block diagram of the IDT39C1 0
microprogram sequencers. Ascan be seen, the devices are
controlled by a 4-bit microinstruction word (13 -10). Normally,
this word is supplied from one 4-bit field of the microinstruction
word associated with the entire state machine system. These
four bits provide for the selection of one of the sixteen powerful
instructions associated with selecting the address of the next
microinstruction. Unused Y outputs can be left open; however, the corresponding most significant D inputs should be
tied to ground for smaller microwords. This is necessary to
make sure the internal operation of the counter is proper
should less than 4K of microcode be implemented. As shown
in the block diagram, the internal instruction PLA uses the four
instruction inputs as well as the CC, CCEN and the internal
counter = 0 line for controlling the sequencer. This internal
8.1
instruction PLA provides all of,the necessary internal control
signals to control each particular part of the microprogram
sequencer. The next add ress at the Y outputs of the IDT39C1 Os
can be from one of four sources. These include the internal
microprogram counter, the last-in/first-out stack, the registerl
counter and the direct inputs.
The following paragraphs will describe each instruction
associated with the IDT39C1 Os. As a part of the discussion,
an example of each instruction is shown in Figure 1. The
purpose of the examples is to show microprogram flow. Thus,
in each example the microinstruction currently being executed has a circle around it. That is, this microinstruction is
assumed to be the contents of the pipeline register at the
output of the microprogram memory. In these drawings, each
of ,the dots refers to the time that the contents of the microprogram memory word would be in the pipeline register and is
currently being executed.
INSTRUCTION 0 JUMP 0 (JZ)
This instruction is used at power up time or at any restart
sequence when the need is to reset the stack pointer and jump
to the very first address in microprogram memory. The Jump
o instruction does not change the contents of the registerl
counter.
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine Instruction is the one
used to call· microprogram subroutines. The subroutine
address will be contained in the pipeline register and presented
at the D inputs. If the condition code test is passed, a
branch is taken to the subroutine. Referring to 'the flow
diagram forthe IDT39C1 Os shown in Figure 1, wesee that the
content of the microprogram counter is 68. This value is
pushed onto the stack and the top of stack pointer is
incremented. , If the test is failed, this Conditional Jump to
Subroutine instruction behaves as a simple continue. That is,
the content,of microinstruction address 68 is executed next.
INSTRUCTION 2 JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction
opcode., This is typically accomplished by using a mapping
PROM as an input to the D inputs on the microprogram
sequencer. The JMAP instruction branches to the address
appearing on the D inputs. In the flow diagram shown in
Figure 1, we see that the branch actually will be the contents
of microinstruction 85, and this instruction will be executed
next.
INSTRUCTION 3 CONDITIONAL JUMP PIPELINE (CJP)
The simplest branching control available in the IDT39C1 0
microprogram sequencers is that, of conditional jump to
address. In this instruction, the jump address is usually
contained in the microinstruction pipeline register and
presented to the D inputs. If the test is passed, the jump is
4
IDT39C10B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
taken. If the test fails, this instruction executes as a simple
continue. In the example shown in the flow diagram of Figure
1, we see that if the test is passed, the next microinstruction
to be executed is the content of address 25. If the test isfailed,
the microcode simply continues to the contents of the next
instruction.
INSTRUCTION 4 PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally
loaded during the same instruction that pushes the current
value of the microprogram counter on to the stack. Under any
condition independent of the conditional testing, the
microprogram counter is pushed on to the stack. If the
conditional test is passed, the counter will be loaded with the
value on the D inputs to the sequencer. If the test fails, the
contents of the counterwill not change. The PUSH/Conditional
Load Counter instruction is used in conjunction with the loop
instruction (Instruction 13), the repeat file based on the counter
instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).
INSTRUCTION 5 CONDITIONAL JUMP TO SUBROUTINE
R/PL (JSRP)
Subroutines maybe called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register.
In this instruction, the contents of the microprogram counter
are pushed on the stack and the branch address for the
subroutine call will taken from either the internal register/
counter or the external pipeline register presented to the D
inputs. If the conditional test is passed, the subroutine
address will be taken from the pipeline register. If the
conditional test fails, the branch address is taken from the
internal register/counter. An example of this is shown in the
flow diagram of Figure 1.
INSTRUCTION 6 CONDITIONAL JUMP VECTOR (CJV)
The Conditional Jump Vector instruction is similar to the
Jump Map instruction in that it allows a branch operation to a
microinstruction as defined from some external source, except that it is conditional. The Jump Map instruction is
unconditional. If the conditional test is passed, the branch is
taken to the new address on the D inputs. If the conditional test
is failed, no branch is taken but rather the microcode simply
continues to the next sequential microinstruction. When this
instruction is executed, the VECT output is LOW unconditionally. Th us, an external 12-bit field can be enabled on to the
D inputs of the microprogram sequencer.
INSTRUCTION 7 CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline
register always causes a branch in microcode. This jump will
be to one of two different locations in the microcode address
space. If the test is passed, the jump will be to the address
presented on the D inputs to the microprogram sequencer. If
the conditional test fails, the branch will be to the address
contained in the internal register/counter.
8.1
INSTRUCTION 8 REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address for the
loop would be initialized by using the PUSH/Conditional Load
Counter instruction. Then, when the repeat loop instruction is
executed, if the counter is not equal to 0, the next microword
address will be taken from the stack. This will cause a loop to
be executed as shown in the Figure 1 flow diagram. Each time
the microcode sequence goes around the loop, the counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from
the microprogram counter. This instruction performs a timed
wait or allows a single sequence to be executed the desired
number of times. Remember, the actual number of loops
performed is equal to the value in the counter plus 1.
INSTRUCTION 9 REPEAT PIPELINE COUNTER NOT EQUAL TO 0
(RPCT)
This instruction is another technique for implementing a
loop using the counter. Here, the branch address for the loop
is contained in the pipeline register. This instruction does not
use the stack in any way as a part of its implementation. As
long as the counter is not equal to 0, the next microword
address will be taken from the D inputs of the microprogram
sequencer. When the counter reaches 0, the internal multiplexer will select the address source from the microprogram
counter, thus causing the microcode to continue on and leave
the loop.
INSTRUCTION 10 CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating
subroutines. The fact that it is conditional allows the subroutine either to be ended or to continue. If the conditional test
is passed, the address of the next microinstruction will be
taken from the stack and it will be popped. If the conditional
test fails, the next microinstruction address will come from the
internal microprogram counter. This is depicted in the flow
diagram of Figure 1. It is important to remember that every
subroutine call must somewhere be followed by a return from
subroutine call in order to have an equal number of pushes
and pops on the stack.
INSTRUCTION 11CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a
technique for exiting a loop from within the middle of the loop.
This is depicted fully in the flow diagram for the IDT39C1 Os as
shown in Figure 1. The conditional test input for this instruction results in a branch being taken if the test is passed. The
address selected will be that on the D inputs to the microprogram sequencer and, since the loop is being terminated,
the stack will be popped. Should the test be failed on the
conditional test inputs, the microprogram will simply continue
to the next address as taken from the microprogram counter.
The stack will not be affected if the conditional test input is
failed.
5
II
IDT39C10B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INSTRUCTION 12 lOAD COUNTER AND CONTINUE (lDCT)
The Load Counter and Continue instruction is used to place
a value on the D inputs in the register/counter and continue to
the next microinstruction.
.
INSTRUCTION 13 TEST END OF lOOP (lOOP)
The Test End of Loop instruction is used as a last instruction
in a loop associated witn the stack. During this instruction, if
the conditional test input is failed, the loop branch address will
be that on the stack. Since we may go around the loop a
number of times, the stack is not popped. If the conditional test
input is passed, then the loop is terminated and the stack is
popped. Notice that the loop instruction requires a PUSH to
be performed at the instruction immediately prior to the loop
return address. This is necessary so as to have the correct
address on the stack before the loop operation. It is for this
reason that the stack pointer always points to the last thing
written on the stack.
INSTRUCTION 14 CONTINUE (CONT)
Continue is a simple instruction where the address for the
microinstruction is taken from the microprogram counter. This
instruction simply causes sequential program flow to the next
microinstruction in microcode memory.
depicted in Figure 1 showing the IDT39C1 D's flow diagram
and is also described in full detail in the IDT39C1 0'5 instruction
operational summary. Operation of the instruction is such that
any time the external conditional test input is passed, the next
microinstruction will be that associated with the program
counter and the loop will be left. The stack is also popped.
Thus, the external test input overrides the other possibilities.
Should the external conditional test input not be true, the rest
of the operation is controlled by the internal counter. If the
counter is not equal to 0, the loop is taken by selecting the
address on the top of the stack as the address out of the Y
outputs of the IDT39C10s. In addition, the counter is decremented. Should the external conditional test input be failed
and the counter also have counted to 0, this instruction "times
out". The result is that the stack is popped and a branch is
taken to the address presented to the D inputs of the IDT39C1 0
microprogram sequencers . .This address is usually provided
by the external pipeline register.
CONDITIONAL TEST
Throughout this discussion we have talked about microcode passing the conditional test. There are actually two inputs
associated with the conditional test input. These include the
and the 'CC inputs. The CCEi'\J input is a condition code
enable. Whenever the 'CCEN input is HIGH, the 'CC input is
ignored and the device operates as though the 'CC input were
true (LOW). Thus, a fail of the external test condition can
defined as 'CCEN equals LOW and 'CC equals HIGH. A pass
condition is defined as a 'CCEN equal to HIGH or a 'CC equal
to LOW. It is important to recognize the full function of the
condition code enable and the condition code inputs in order
to understand when the test is passed or failed.
cern
INSTRUCTION 15 THREE WAY BRANCH (TWB)
The Three-Way Branch instruction is used for looping while
waiting for a conditional event to come true. If the event does
not come true after some number of microinstructions, then a
branch is taken to another microprogram sequence. This is
8.1
6
IDT39Cl0B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTION OPERATIONAL SUMMARY
13 -10
Mnemonic
0
NC
1
JZ
CJS
2
3
JMAP
CJP
4
PUSH
5
JSRP
6
CJV
7
JRP
8
RFCT
9
RPCT
10
CRTN
11
CJPP
12
13
LDCT
LOOP
14
15
CONT
lWB
= No Change;
DEC
CC
Counter
Test
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
=0
NOT=O
=0
NOT=O
PASS
FAIL
PASS
FAIL
X
X
X
X
X
X
X
X
X
PASS
PASS
FAIL
FAIL
=0
NOT=O
=0
NOT=O
X
PASS
FAIL
X
X
PASS
FAIL
Stack
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC
= Decrement
Address
Source
0
D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK
Register!
Counter
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC
Enable
Select
PL
PL
PL
MAP
PL
PL
~
PL
PL
VECT
VECT
PL
PL
PL
PC
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
~
PL
PL
2589 tbl 02
II
8.1
7
IDT39Cl0BfC
12-BIT CMOS MICROPROGRAM SEQUENCER
o Jump Zero (JZ)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1 Cond JSB PL (CJS)
2 Jump Map (JMAP)
~!~8'
85
4 Push/Cond LD CNTR (PUSH)
3 Cond Jump PL (CJP)
6 5 t < 8 STACK
66
67 •
68
66
65t--67 •
!. 25
68
69
T 26
.
N
68
69
30
31
32
33
34
65
66
67
t
20
21
35
T 36
65r:
8 Repeat Loop, CNTR -:f. 0 (RFCT)
~ STACK
66
67
68
69 •
70
~::':~EPJ
COUNTER
11 Cond Jump PL & POP (CJPP)
40
41
42
43
44
30
31
9 Repeat PL, CNTR -:f. 0 (RPCT)
65
65
REGISTER!
COUNTER
7 Cond JUMP R/PL (JRP)
6 Cond Jump Vector (CJV)
66
65t--67 •
5 Cond JSB R/PL (JSRP)
~
10 Cond Return (CRTN)
COUNTER
(LDCT)
STACK
65
66
67
68
69
70
66
67 •
68
12 LD CNTR & Continue (LDCT)
30
31
34
35
36
37
65
66
~+-------~~
65
66 •
42
67
68
71
14 Continue (CONT)
66
•
65t
67
68
r
40
41
COUNTER
13 Test End Loop (LOOP)
65~
66
15 Three-Way Branch (TWB)
~
~STACK
: ~E~':~EPJ
67
68 •
STACK
(PUSH)
67
68
69
70
COUNTER
72
73
69
2551 drw 05
Figure 1. IDT39Cl0B Flow Diagrams
8.1
8
IDT39C10B/C
12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTIONS
13-10
Mnemonic
Regl
Cntr
Contents
Name
PASS
FAIL
~
Y
=LOW and CO =HIGH
0
Stack
CLEAR
PC
HOLD
~
=HIGH and CO =LOW
Y
Regl
Cntr
Enable
Stack
CLEAR
HOLD
PL
PUSH
HOLD
PL
JY:P
9
RPCT
Repeat PL, CNTR "I- 0
X
X
X
X
X
X
X
X
"1-0
.. 0
;/:0
HOLD
PC
HOLD
HOLD
CRTN
Cond RTN
-0
X
PC
10
PC
HOLD
F
POP
HOLD
PL
11
CJPP
Cond Jump PL & POP
X
PC
HOLD
0
POP
HOLD
PL
12
LDCT
LD Contr & Continue
X
PC
HOLD
PC
HOLD
LOAD
PL
13
LOOP
Test End Loop
X
F
HOLD
PC
POP
HOLD
PL
PL
0
JZ
Jump Zero
1
CJS
Cond JSP PL
2
3
JMAP
Jump Map
CJP
Cond Jump PL
4
PUSH
PUSH/Cond Ld Cntr
5
JSRP
Cond JSB R/PL
6
CJV
Cond Jump Vector
7
JRP
Cond Jump R/PL
8
RFCT
Repeat Loop, CNTR "I- 0
14
CO NT
Continue
15
TWB
Three-Way Branch
0
0
0
HOLD
0
HOLD
HOLD
PC
HOLD
0
HOLD
HOLD
PL
PC
PUSH
PC
PUSH
(1)
J5[
R
PUSH
0
PUSH
HOLD
PC
PC
HOLD
0
HOLD
HOLD
VECr
R
HOLD
0
HOLD
DEC
PL
F
HOLD
F
HOLD
DEC
PL
PC
POP
PC
POP
HOLD
PL
0
HOLD
0
HOLD
DEC
PL
PL
X
PC
HOLD
PC
HOLD
HOLD
;/:0
F
HOLD
PC
POP
DEC
PL
=0
0
POP
PC
. POP
HOLD
PL
NOTE:
1. If CCEliJ = LOW and CC = HIGH, hold; else load. X = Don't Care.
2589 tbl03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee
Rating
Power Supply
Voltage
Com'l.
Mil.
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-D.5to
Vee + 0.5
-D.5to
Vee+ 0.5
V
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
30
30
mA
VTERM
Terminal Voltage
with Respect to
GND
TA
Symbol
Parameter
(1)
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Typ.
Unit
VIN = OV
5
pF
VOUT= OV
7
NOTE:·
1. This parameter is sampled and not 100% tested.
pF
2589 Ibl05
II
NOTE:
2589 Ibl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
8.1
9
IDT39C1 DB/C
12·BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, Vcc = 5.0V +
- 10%
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level.
Guaranteed Logic HIGH Level(4)
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level(4)
-
-
0.8
V
IIH
Input HIGH Current
Vee = Max., VIN = Vee
-
0.1
5
I IL
Input LOW Current
Vee .. Max., VIN = GND
-
-0.1
-5
IlA
IlA
VOH
Output HIGH Voltage
Vee = Min.
IOH .. -12mA Mil.
2.4
4.3
IOH .. -15mA Com'l.
2.4
4.3
-
V
VIN .. VIH or VIL
Vcc = Min.
IOL .. 20mA Mil.
0.5
V
IOL .. 24mA Com'l.
0.3
0.5
Off State (High Impedance)
Output Current
Vcc .. Max.
Vo .. OV
-
0.3
VIN .. VIH or VIL
-0.1
-10
Vo .. Vcc (max.)
-
0.1
10
los
Output Short Circuit Current
VCC .. Max., VOUT .. OV (3)
-30
-
-
rnA
lecoH
Quiescent Power Supply Current
CP=H
Vcc = Max.
VHC:S;; VIH, VIL:S;; VLC
fcp = 0, CP .. H
-
35
50
rnA
lecoL
Quiescent Power Supply Current
CP .. L
Vec = Max.·
VHC:S;; VIH, VIL ::; VLC
-
35
50
rnA
lecT
Quiescent Input Power Supply(S)
CUrrent (per Input @ TIL High)
-
0.3
0.5
mAl
Input
ICCD
Dynamic Power Supply Current
Symbol
VOL
loz
Test Condltlons(1)
Parameter
Output LOW Voltage
IlA
fcp .. 0, CP = L
Vcc = Max., VIH = 3.4V, fcp = 0
Vee = Max.
MIL.
-
1.0
3.0
mAl
VHC::; VIH, VIL::; VLC
COM'L.
-
1.0
1.5
MHz
Vce = Max., fcp = 10MHz
MIL.
80
rnA
COM'L.
-
45
Outputs Open, OE = L
CP = 50 % Duty cycle
VHC::; VIH, VIL::; VLC
45
65
Outputs Open, OE = L
Icc
Total Power Supply Current(6)
Vce = Max., fcp = 10MHz
MIL.
-
50
90
Outputs Open, OE = L
CP = 50 % Duty cycle
VIH = 3.4V, VIL = O.4V
COM'L.
-
50
75
2589 tbl 06
NOTES:
1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = S.OV, + 25°C ambient and maximum loading, not production tested.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels should only be static tested in a noise-free environment.
5. lceT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out leeCH, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the QUiescent current and the Dynamic current (at either CMOS or TIL Input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = leeCH (CDH) +lcecL (1 - CDH) + lecT (NT x DH) + ICCD (fcp 12+foNo)
CDH = Clock duty cycle high period
DH = Data dUty cycle TIL high period (VIN = 3.4V)
NT= Number of dynamic inputs driven at TIL levels
fcp = Clock input frequency
fo = Ouput frequency
No = Number of Outputs switching at fo
8.1
1D
IDT39C10B/C
12·81T CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices in
an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of the capacitor set and the value of capacitors used
is critical in reducing the potential erroneous failures resulting from large Vcc current changes. Capacitor lead length
must be short and as' close to the OUT power pins as
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.
3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, lOT recommends using VIL ~ OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of mUlti-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All unused
interconnect pins must be properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.
IDT39C10C AC ELECTRICAL
CHARACTERISTICS
I. MINIMUM SET-UP AND HOLD TIMES
IDT39C10B AC ELECTRICAL
CHARACTERISTICS
I. MINIMUM SET-UP AND HOLD TIMES
t(S)
Inputs
DI~R
DI~
PC
10-3
CC
CCEN
CI
RLD
t(H)
Com'l.
Mil.
Com'l.
6
7
.0
13
15
23
15
15
6
11
25
18
18
7
12
t(S)
Mil.
Unit
t(H)
Com'l.
Mil.
Com'J.
Mil.
Unit
DI~R
16
16
a
a
a
a
a
a
ns
ns
0
0
ns
a
a
a
a
a
a
ns
Inputs
a
a
a
a
a
ns
DI~PC
30
30
ns
10-3
0
0
ns
CC
a
a
a
a
a
a
ns
CCEN
ns
CI
ns
RLD
35
24
24
18
19
38
35
35
18
20
ns
2589 !b107
II. MAXIMUM COMBINATIONAL DELAYS
y
FULL
j5[, \iECi, MAP
Inputs
D0-11
10-3
CC
CCEN
CP
OE(1)
Com'l.
Mil.
12
15
20
25
16
20
16
20
28
33
10/10 13/13
Com'l.
Mil. Com'J. Mil.
-
-
13
15
-
-
-
-
ns
ns
ns
2589 tblt 02589 tbl 07
II. MAXIMUM COMBINATIONAL DELAYS
y
j5[, \iECi, MAP
RJII
Unit
Inputs
-
ns
Do-11
ns
10-3
ns
CC
-
-
-
ns
CCEN
-
22
25
ns
CP
-
-
-
ns
DE(1)
Com'J.
Mil.
20
25
35
40
30
36
30
36
40
46
25/27 25/3C
Com'l.
Mil. Com'l. Mil.
Unit
-
-
30
35
-
-
-
-
-
-
-
ns
-
31
35
ns
-
-
-
-
ns
-
ns '
-
ns
-
ns
NOTE:
2589 tbl 08
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF, correlated to SpF.
NOTE:
2589 tbltt
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL = SOpF, correlated to SpF.
III. CLOCK REQUIREMENTS
III. CLOCK REQUIREMENTS
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period
Com'l.
Mil.
Unit
18
17
35
20
20
40
ns
Minimum Clock LOW Time
ns
Minimum Clock HIGH Time
ns
Minimum Clock Period
2589 tbl 09
8.1
Com'l.
Mil.
Unit
20
20
50
25
25
51
ns
ns
ns
2589 tblt2
11
IDT39C10B/C
12·BI1 CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10B INPUT/OUTPUT INTERFACE CIRCUIT
Vee
IIH ...
OUTPUTS
INPUTS 0--....1,
2589 drw 06
2589 drw 05
Flgur. 2. Input Structur.
Figure 3. Output Structure
TEST LOAD CIRCUIT
Test
Disable Low
Enable Low
Switch
Closed
All other Tests
Open
2589 !b114
DEFINITIONS
CL - Load capacitance: includes jig and probe capacitance
RT - Termination resistance: should be equal to ZOUT of the Pulse
Generator
Flgur. 4. SWitching Test Circuits
258~drwrr1
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input liming Reference Levels
Output Reference Levels
Output Load
GNDto3.0V
WIns
1.SV
1.SV
See Figure 4
2589 !b113
8.1
12
~®
IDT49C402
IDT49C402A
IDT49C402B
16-BIT CMOS
MICROPROCESSOR SLICE
Integrated Device Technology, Inc.
FEATURES:
• Functionally equivalent to four 2901 s and one 2902
• IDT49C402B is 60% faster than four 2901Cs and one
2902A
• Expanded two-address architecture with independent, simultaneous access to two 64 x 16 register files
• Expanded destination functions with 8 new operations
allowing Direct Data to be loaded directly into the dual-port
RAM and Q Register
• Clamp diodes on all inputs provide noise suppression
• Fully cascadable
• 68-pin ceramic PGA, Plastic Leaded Chip Carrier (PLCC),
and Ceramic Flatpack (25 mil centers)
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49C402s are high-speed, fully cascadable 16-bit
CMOS microprocessor slice units which combine the
standard functions of four 2901s and a 2902 with additional
control features aimed at enhancing the performance of bitslice microprocessor designs.
The IDT49C402s include all of the normal functions
associated with standard 2901 bit-slice operation: a) a 3-bit
instruction field (10, 11, 12) which controls the source operand
selection for the ALU; b) a 3-bit microinstruction field (13,14, 15)
used to control the eight possible functions of the ALU; c) eight
destination control functions which are selected by the
microcode inputs (16, 17, Is); and d) a tenth microinstruction
input, 19, offering eight additional destination control functions.
This 19 input, ill conjunction with 16, 17 and Is, allows for shifting
the Q Register up and down, loading the RAM or Q Register
directly from the D inputs without going through the ALU, and
having the RAM A data output port available at the Y output
pins of the device.
Also featured is an on-chip dual-port RAM that contains
64-words-by-16 bits-four times the number of working registers in a 2901.
The IDT49C402s are fabricated using CEMOSTM, a CMOS
technology designed for high performance and high reliability.
These performance-enhanced devices feature both bipolar
speed and bipolar output drive capabilities, while maintaining
exceptional microinstruction speeds at greatly reduced CMOS
power levels.
FUNCTIONAL BLOCK DIAGRAM
ALU
SOURCE
ALU
FUNCTION
DESTINATION
CONTROL
DATA OUT
CEMOS is a trademark of Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tll1992 Integrated Device Technology. Inc.
8.2
MAY 1992
09C·9011/4
1
IDT49C402lAlB
16-B11 CMOS MICROPROCESSOR SLICE
PIN CONFIGURATIONS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
o
~
0
~
0
N
M
~
•
~
~
~
~
~
0
'::!E
~
~
•
oo~~~~~~~~~UUO~~~
Pin 1 indicator
for PLCC
02
03
04
05
06
07
GNO
08
09
010
011
012
013
014
015
Y 15
Y14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A3
A2
A1
Ao
13
14
15
10
11
12
Vee
~
80
81
82
83
84
2728293031323334353637383940414243
2524 dlW 02
PLCC
TOP VIEW
A3
As
17
la
19
MSS
RAM 15
Q1S
C n+16
A4
Qo
RAMo
CP
Cn
Y7
Ya
Ys
Y6
Y3
Y4
Y1
J5"/OVR
GtF 15
F=O
yg
Y10
Y11
Y12
Y13
Y14
Y2
Yo
o
_
N
w
0
0
0
_
N
•
00000000 8 00;;;;;;;
~
~
~
~
~
~
~
~
2524 cbw03
PGA
TOP VIEW
8.2
2
lOT49C4021AlB
16·BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
o
:::E
Q~~;;;;;~;~~~O~<~
9 8 7 6 5 4 3 2 1 6867666564636261
D2
D3
D4
D5
D6
D7
GND
D8
D9
DlO
D11
D 12
D 13
D 14
D 15
Y15
Y 14
/0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
PIN 1 IDENTIFICATION
CALL FOR PKG DRAWING
(AVAILABLE ONLY FOR
MLiTARY PRODUCT)
44
A3
A2
Al
Ao
13
14
15
10
11
12
Vee
OE
80
81
82
83
84
2728293031323334353637383940414243
2524 drw04
(')
'"
~
0
010
>.;>.;>-
III
a:
<0
Illlllcn
u.1c;,1E ~
~:::E
II~>
'.;:oi
cn
Ol
CD
....
<0
----
III
m
FLATPACK
TOP VIEW
II
8.2
3
IDT49C402lAlB
16-BITCMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
110
Description
Ao -A5
I
Six address inputs to the register file which selects one register and displays its contents through the A port.
Bo -B5
I
Six address inputs to the register file which selects one of the registers in the file, the contents of which is
displayed through the B port. It also selects the location into which new data can be written when the clock
goes LOW.
10 - 19
I
Ten instruction control lines which determine what data source will be applied to the ALU 1(0, 1, 2), what function
the ALU will perform 1(3,4,5) and what data is to be deposited in the 0 Register or the register file 1(6,7,8,9).
Original 2901 destinations are selected if 19 is disconnected in this mode, proper 19 bias is achieved by an
external pullup resistor to Vee (47K ohms recommended).
Do- 015
I
Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU, 0
Register or RAM. Do is the LSB.
Yo -Y15
a
Sixteen three-state output lines which, when enabled, display either the sixteen outputs of the ALU or the data
on the A port of the register stack. This is determined by the destination code 1(6,7,8,9).
G/F15
a
A multipurpose pin which indicates the carry generate (Gl function at the least significant and intermediate
slices or as F15, the most significant ALU...Qutput (sign bit). G/F15 selection is controlled by the MSS pin. If MSS
= HIGH, F15 is enabled. If MSS = LOW, G is enabled.
F=O
a
Open drain output which goes HIGH if the Fo - F15 ALU outputs are all LOW. This indicates that the result of an
ALU operation is zero (positive logic).
Cn
I
Carry-in to the internal ALU.
Cn+16
a
Carry-out of the ALU.
015
1/0
Bidirectional lines controlled by 1(6,7,8,9). Both are three-state output drivers connected to the TTL-compatible
inputs. When the destination code on 1(6,7,8,9) indicates an up shift, the three-state outputs are enabled, the
MSB of the 0 Register is available on the 015, pin and the MSB of the ALU output is available on the RAM15
pin. When the destination code indicates a down shift, the pins are the data inputs to the MSB of the 0 Register
and the MSB of the RAM.
110
Both bidirectional lines function identically to 015 and RAM15 lines except they are the LSB of the 0 Register
and RAM.
OE
I
Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs
are enabled.
P/OVR
a
A multipurpose pin which indicates the carry propagate (P) output for performing a carry lookahead operation or
overflow (OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVA, at the most significant
end of the word, indicates that the result of an arithmetic two's complement operation has overflowed into the
sign bit. PIOVR selection is controlled by the MSS pin. If MSS = HIGH, OVR is enabled. If MSS = LOW, is'is
enabled.
CP
I
The clock input LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock
LOW time is internally the write enable time for the 64 x 16 RAM. While the clock is LOW, the slave latches on
the RAM outputs are closed, storing the data previously on the RAM outputs. Synchronous MASTER-SLAVE
operation of the register file is achieved by this.
MSS
I
When HIGH, enables OVR and F15 on the P/OVR and GlF15 pins. When LOW, enables G and P on these pins.
If left open, internal pullup resistor to Vcc provides declaration that the device is the most significant slice.
RAM15
00
RAMo
2524tbl01
8,2
4
IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEVICE ARCHITECTURE
The IDT49C402 CMOS bit-slice microprocessor is configured sixteen bits wide and is cascadable to any number of bits
(16, 32, 48, 64). Key elements which make up this 16-bit
microprocessor slice are the 1) register file (64 x 16 dual-port
RAM) with shifter; 2) ALU and 3) a Register and shifter.
REGISTER FILE - A 16-bit data word from one of the 64
RAM registers can read from the A port as selected by the
6-bit A address field. Simultaneously, the same data word, or
any other word from the 64 RAM registers, can be read from
the 8 port as selected by the 6-bit 8 address field. New data
is written into the RAM register location selected by the 8
address field during the clock (CP) LOW time. Two sixteenbit latches hold the RAM A port and 8 port during the clock
(CP) LOW time, eliminating any data races. During clock
HIGH, these latches are transparent, reading the data
selected by the A and 8 addresses. The RAM data input field
is driven from a four-input multiplexer that selects the ALU
output or the D inputs. The ALU output can be shifted up one
position, down one position or not shifted. Shifting· data
operations involves the RAM15 and RAMo I/O pins. For a shift
up operation, the RAM shifter MS8 is connected to an enabled
RAM15 1/0 output, while the RAMo· 110 input is selected as the
input to the LS8. During a shift down operation, the RAM
shifter LS8 is connected to an enabled RAMo 1/0 output, while
the RAM15 1/0 input is selected as the input to the MS8.
ALU - The ALU can perform three binary arithmetic and
five logic operations on the two 16-bit input words Sand R.
The S input field is driven from a 3-input multiplexer and the R
input field is driven from a 2-input mUltiplexer, with both having
a zero source operand. 80th multiplexers are controlled by
the 1(0,1,2) inputs. This multiplexer configuration enables the
user to select the various pairs of the A, 8, D, a and "a" inputs
as source operands to the ALU. Microinstruction inputs 1(3,4,
5) are used to select the ALU function. This high-speed ALU
cascades to any word length, providing carry-in (Cn), carry-out
(Cn+16) and an open-drain (F = 0) output. When all bits of the
8.2
ALU are zero, the pull-down device of F.,. 0 is off, allowing a
wire-OR of this pin over all cascaded devices. Multipurpose
pins G/F15 and PIOVR are aimed at accelerating arithmetic
operations. For intermediate and least significant slices, the
MSS pin is programmed LS}W, selecting the carry-generate
(G) and carry propagate (P) output functions to be used by
carry lookahead logic. For the most significant slice, MSS is
programmed HIGH, selecting the sign-bit (F15) and the two's
complement overflow (OVR) output functions. The sign bit
(F15) allows the ALU sign bit to be monitored without enabling
the three-state ALU outputs. The overflow (OVR) output is
high when the two's complement arithmetic operation has
overflowed into the sign bit, as logically determined from the
Exclusive -OR of the carry-in and carry-out of the most
significant bit of the ALU. The ALU data outputs are available
at the three-state outputs Y(0-15) or as inputs to the RAM
register file and a register under control of the 1(6, 7, 8, 9)
instruction inputs.
.
Q REGISTER - The a Register is a separate 16-bit file
intended for multiplication and division routines and can also
be used as an accumulator or holding register for other types
of applications. It is driven from a 4-input multiplexer. In the
no-shift mode, the multiplexer enters theALU Foutput or
Direct Data into the a Register. In either the shift up or shift
down mode, the multiplexer selects the a Register data
appropriately shifted up or down. The Qshifter has two ports,
ao and a15, which operate comparably to the RAM shifter.
They are controlled by the 1(6, 7, 8, 9) inputs~ ..
The clock input of the IDT49C402 controls the RAM, a
Register and A and 8 data latches. When enabled, the data
is clocked into the a Register on the LOW- to-H IGH transition.
When the clock is HIGH, the A and 8 latches are open and
pass data that is present at the RAM outputs. When the clock
is LOW, the latches are closed and retain the last data
entered. When the clock is LOW and 1(6, 7,8,9) define the RAM
as the destination, new data will be written into the RAM file
defined by the 8 address field.
5
IDT49C402lAlB
16-BITCMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ALU SOURCE OPERAND CONTROL
12
h
10
AO
AB
ZO
ZB
ZA
DA
DO
DZ
L
L
L
L
L
H
L
H
L
Octal
Code
L
H
H
H
L
L
0
1
2
3
4
H
L
H
5
H
H
H
R
S
A
A
D
D
D
0
B
0
B
A
A
0
0
0
0
6
L
H
Microcode
ALU Source
Operands
Microcode
Mnemonic
ALU FUNCTION CONTROL
7
H
0
Mnemonic
15
14
13
Octal
Code
ALU
Function
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
R Plus S
S Minus R
R Minus S
RORS
RANDS
'RAND S
R EX-ORS
R EX-NORS
Symbol
2524 tbl 02
ALU ARITHMETIC MODE FUNCTIONS
Octal
Cn= L
le,4,3
12,1,0
0
0
0
0
0
1
5
6
0
0
0
0
2
3
4
7
1
1
2
3
4
7
1
2
2
2
2
1
2
3
1
1
1
1
2
2
2
2
0
1
Group
ADD
PASS
Decrement
1's Compo
4
7
5
6
0
1
5
6
Subtract
(1's Comp)
A+O
A+B
D+A
0+0
0
B
A
0
0-1
B-1
A-1
0-1
-0-1
-B-1
-A-1
-0-1
0-A-1
B-A-1
A-0-1
0-0-1
A-0-1
A-B-1
0-A-1
0-0-1
Octal
Function
15,4,3
12,1,0
ADD
plus one
A+0+1
A+B+1
D+A+1
0+0+1
4
4
4
4
0
1
5
6
3
3
3
3
0
1
5
6
6
6
6
6
0
1
5
6
7
7
7
7
0
1
5
6
7
7
7
7
2
3
4
PASS
0+1
B+1
A+1
0+1
0
B
A
0
-Q
2's Compo
(Negate)
Subtract
(2's Comp)
RVS
RVS
ALU LOGIC MODE FUNCTIONS
Group
Increment
1111s
2524 tbl 04
Cn= H
Function
R+S
S-R
R-S
RVS
RIIS
-B
-A
-0
O-A
B-A
A-O
0-0
A-O
A-B
O-A
0-0
6
6
6
6
2524 tbl 03
3
3
3
3
4
4
4
4
5
5
5
5
Group
AND
OR
EX-OR
EX-NOR
2
PASS
4
7
2
3
4
PASS
7
2
3
"ZERO"
4
7
0
1
5
6
AIIO
AIIB
DIIA
DIIO
AVO
AVB
DVA
DVO
AVO
AVB
DVA
DVO
AVO
AVB
DVA
t5VCl
Q
INVERT
7
3
Function
MASK
g
A
IT
0
B
A
D
0
B
A
D
0
0
0
0
AIIO
AIIB
IT II A
IT II 0
2524 tbl 05
8.2
6
lOT49C4021AlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOURCE OPERAND AND ALU FUNCTION MATRIX (1)
12,1,0 Octal
a
Octal
ALU
15,4,3
Function
0
Cn= L
R Plus S
Cn= H
1
Cn = L
S Minus R
Cn= H
2
Cn= L
R Minus S
Cn=H
3
RORS
RANDS
RANDS
REX-OR S
REX-NOR S
4
5
6
7
1
2
4
3
ALU Source
O,B
O,A
8
A
5
6
7
O,A
D+A
D,a
0+0
0,0
A,a
A+O
A,B
A+8
0,0
A+O+ 1
0-A-1
A+8+1
8-A-1
0+1
0-1
8 +1
8-1
A+ 1
A-1
D+A+1
A-D-1
D+0+1
0-D-1
D+ 1
-0-1
O-A
A-0-1
8-A
A-8-1
0
-0-1
8
-8-1
A
-A-1
A-D
D-A-1
Q-D
D-0-1
-0
D-1
A-O
AVO
AIIO
AIIO
AVO
AVO
A-8
AV8
A II 8
AII8
AV8
-0
0
-8
-A
A
Q
0-0
DVO
DIIO
IT II 0
DV 0
'D'VQ
D
D
AVl3
D-A
DVA
DIIA
IT II A
DVA
I5"'V'A
0
8
0
0
0
0
0
8
8
g
A
A
A
D
0
0
D
IT
2524 tbl 06
NOTE:
1. + = Plus; -
= Minus; II = AND; V = EX-OR; V = OR.
ALU DESTINATION CONTROL(1)
RAM
Function
Microcode
Q Register
Function
Q
Shifter
RAM
Shifter
19
Ie
17
16
Hex
Code
Shift
Load
Shift
Load
Y
Output
RAMo
RAM15
Qo
OREG
H
L
L
L
8
X
NONE
NONE
F-+O
F
X
X
X
X
Existing 2901
NOP
H
L
L
H
9
X
NONE
X
NONE
F
X
X
X
X
Functions
RAMA
H
L
H
L
A
NONE
F-+B
X
NONE
A
X
X
X
X
RAMF
H
L
H
H
B
NONE
F-+B
X
NONE
F
X
X
X
X
RAMOD
H
H
L
L
C
DOWN
F/2 -+ B
F
Fa
IN15
00
IN15
RAMD
H
H
L
H
D
DOWN
F/2-+ B
X
RAMOU
H
H
H
L
E
UP
RAMU
H
H
H
H
F
UP
Mnemonic
DOWN 012-+0
Q15
NONE
F
Fa
IN15
00
X
2F -+ B
UP
20-+0
F
INa
F15
INa
015
2F -+ B
X
NONE
F
INa
F15
X
015
DFF
L
L
L
L
0
NONE
D-+B
NONE
F-+O
F
X
X
X
X
New Added
DFA
L
L
L
H
1
NONE
D-+B
NONE
F-+O
A
X
X
X
X
IDT49C402
FDF
L
L
H
L
2
NONE
F-+B
NONE
D-+O
F
X
X
X
X
Functions
X
IN15
FDA
L
L
H
H
3
NONE
F-+B
NONE
XODF
L
H
L
L
4
X
NONE
DOWN 012-+0
D-+O
A
X
X
X
F
X
X
00
DXF
L
H
L
H
5
NONE
D-+B
X
NONE
F
X
X
00
X
XOUF
L
H
H
L
6
X
NONE
UP
20-+0
F
X
X
INa
015
XDF
L
H
H
H
7
X
NONE
NONE
D-+O
F
X
X
X
015
NOTE:
1. X = Don't care. Electrically, the shift pin is a TIL input internally connected to a three-state output which is in the impedance state.
B = Register Addressed by B inputs.
UP Is toward MSB; DOWN is toward LSB.
8.2
2524 tbl 07
7
IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee
VTERM
Rating
Com'l.
Power Supply ,
Voltage
CAPACITANCE
Mil.
Unit
-0.5 to +7.0 -0.5 to +7.0
V
Terminal Voltage
with Resp~ct
to Ground
-0.5 to
Vee+ 0.5
-0.5 to
VCC + 0.5
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAs
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
(TA
= +25°C, f = 1.0MHz)
Parameter
Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = OV
5
pF
COUT
Output Capacitance
VOUT= OV
7
(1)
NOTE:
pF
2524tbl09
1. This parameter is sampled and not 100% tested.
PT
Power Dissipation
1.5
1.5
W
lOUT
DC Output Current
50
50
rnA
NOTE:
Symbol
2524 tbl 08
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Commercial: TA ... O°C to +70°C, Vcc ... 5.0V ± 5%; Military: TA .. -55°C to +125°C, Vcc .. 5.0V ± 10%
Symbol
Test Conditions (1)
Parameter
VIH
Input HIGH Level
Guaranteed Logic High Level (4)
VIL
Input LOW Level
Guaranteed Logic Low Level (4)
IIH
Input HIGH Current
Vee .. Max., VIN .. Vee
IlL
Input LOW Current
Vee .. Max., VIN .. GND
VOH
Output HIGH Voltage
VOL
loz
OUtput LOW Voltage
Off State (High Impedance)
Output Short Circuit Current
-
-
Max.
Unit
-
V
O.S
V
0.1
5
-0.1
-5
IlA
IlA
V
(2)
Vee .. Min.
IOH .. -6mA MIL.
2.4
4.3
-
10H = -SmA COM'L.
2.4
4.3
-
-
0.3
0.5
0.3
0.5
-0.1
-10
0.1
10
-30
-70
Vee .. Min.
10L .. SmA MIL.
VIN .. VIH or VIL
10L = 10mA COM'L.
Vee
=Max.
Vo .. OV
Vo .. Vee (Max.)
Vee .. Max., VOUT .. OV (3)
.-15
V
IlA
rnA
2524tbll0
NOTES:
1.
2.
3.
4.
Typ.
2.0
VIN .. VIH or VIL
OUtput Current
los
Min.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
Typical values are at Vcc - 5.0V, +25°C ambient and maximum loading, not production tested.
Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
These input levels should only be static tested In a, noise-free environment.
8.2
8
IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Commercla:
. I TA= O°C t0+ 70°C V CC= 5 OV + 5%; MT
Iitary: TA = -55° C to + 125°C, Vcc - 5.0V + 10%
Typ.(2)
Test Condltlons(l)
Parameter
Symbol
Min.
ICCQH
ICCQl
ICCT
Icc
Max.
Unit
-
10
rnA
-
10
Vcc"" Max.
MIL.
CP "" H (CMOS Inputs)
VIH "" Vcc, Vil "" OV
fcp"" 0, CP "" H
COM'L.
Quiescent Power Supply Current
Vcc"" Max.
MIL.
10
VIH"" Vcc, Vil "" OV
fcp "" 0, CP "" L
COM'L.
-
-
CP "" L (CMOS Inputs)
-
10
Quiescent Input Power Supply(6)
Vcc"" Max., VIH = 3.4V, fcp = 0
MIL.
-
COM'L.
-
Vcc = Max.
MIL.
VIH = Vcc, Vil = OV
Outputs Open, OE = L
COM'L.
-
Vcc = Max., fcp = 10MHz
MIL.
-
Outputs Open, OE = L
CP = 50 % Duty cycle
VIH = Vcc, Vil = OV
COM'L.
-
Vcc = Max., fcp = 10MHz
MIL.
Outputs Open, OE = L
CP = 50 % Duty cycle
VIH = 3.4V, Vil = O.4V
COM'L.
Current (per Input @ TTL High)
ICCD
-
Quiescent Power Supply Current
Dynamic Power Supply Current
Total Power Supply Current(7)
rnA
1.5
mN
0.85
Input
7.5
mN
4.5
MHz
-
85
rnA
-
-
130
-
-
95
55
2524tbl12
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading, not production tested.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
5. Guaranteed by design, not production tested.
6. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccOH, then dividing by the total number of inputs.
7. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input/evels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = lecoH (CDH) +ICCOL (1 - CDH) + ICCT (NT X DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fcp = Clock input frequency
ICCT = Quiescent Power Supply Current for TIL level inputs
ICCD =Dynamic Power Supply Current in mAlMHz
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account when applying high-speed CMOS products to the
automatic testing environment. Large output currents are
being switched in very short periods and proper testing
demands that test set-ups have minimized inductance and
guaranteed zero voltage grounds. The techniques listed
below will assist the user in obtaining accurate testing results:
1) All input pins should be connected to a voltage potential
during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical.
Each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. Capacitors should be
positioned using the minimum lead lengths. They should
8.2
also be distributed to decouple power supply lines and be
placed as close as possible to the OUT power pins.
3) Device grounding is extremely critical for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to the OUT interface board and wiring
unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for
power wiring, with twisted pairs being recommended for
minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To
allowfortesting and hardware-induced noise, lOT recommends using VIL ~ OV and VIH ;::: 3V for AC tests.
9
IDT49C402lAlB
16-B11 CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
IDT49C402
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the lOT49C402 over the -55°C to +125°C and O°C to +70°C
temperature ranges. Vcc is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current lo'ads.
Mil. (6)
Com'l.
Unit
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
50
48
ns
Maximum Clock Frequency to
shift 0 (50% duty cycle,
I = C32 or E32)
20
21
MHz
Minimum Clock LOW Time
30
30
ns
Minimum Clock HIGH Time
20
20
ns
Minimum Clock Period
50
48
ns
25241bl13
MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1) CL=50pF
To Output
(MSS = L)
G,P
V
From Input.
RAMo
Qo
RAM15
Q15
(MSS = H)
F15
Cn+ 16
OVR
F=O
Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l, Mil. Com'l. Mil. Com'l. Mil. Com'l, Unit
A, B Address
52
47
47
42
52
47
47
42
38
34
52
47
44
40
D
35
32
34
31
35
32
34
31
27
25
35
32
28
26
-
-
Cn
29
26
-
-
29
26
27
25
20
18
29
26
23
21
-
-
ns
10,1,2
41
37
30
27
41
37
38
35
29
26
41
37
30
27
-
ns
36
37
34
27
25
40
36
28
26
-
-
-
-
-
-
-
-
20
18
20
18
ns
-
-
-
-
-
-
-
-
38
41
37
30
27
. 38
41
13,4,5
40
36
28
26
40
16,7,8,9
26
24
-
-
A Bypass
ALU (I .. AXX,
1XX,3XX)
30
27
-
-
-
41
37
42
Clock
./
42
38
.
42
37
25
ns
ns
ns
ns
·23
ns
2524tbl14
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H -7 L
Input
"
Mil.
Com'l.
A, B Source Address
20
18
B Destination Address
20
18
D
_(1)
Cn
-
-
10,1,2
13,4,5
16,7,8,9
-
12
11
-
-
/
Hold Time
After H -7 L
Mil.
2 (3)
Com'l.
1 (3)
Set-up Time
Before L -7 H
Mil.
50 (4)
Com'l.
50 (4)
Do not change (2)
-
Hold Time
After L -7 H
Mil.
Com'!.
2
1
Unit
ns
2
1
ns
-
30/40 (5)
26/36 (5)
2
1
ns
35
32
0
0
ns
-
45
41
0
0
ns
45
41
0
0
ns
0
0
ns
Do not change (2)
0
0
RAMo,lS, 00,15
12
11
ns
NOTES:
2524tbl15
1. A dash indicates a propagation deiay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -7 L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B addreSs could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
..
4. The set-up time prior to the clock L -7 H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -7 H transition, regardless of when the H -7 L transition occurs.
5. First value is direct path (OATAIN -7 RAMIO Register). Second value is indirect path (OATAIN -7 ALU -7 RAMIO Register).
6. Guaranteed by design, not production tested;
8.2
10
IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
IDT49C402A
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the lOT49C402A over the -55°C to +125°C and O°C to +70°C
temperature ranges. Vcc is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
'1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond .. All outputs have
maximum DC current loads.
MU'(6)
Com'l.
Unit
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)(6)
.
23
22
ns
Maximum Clock Frequency to
shift Q (50% dut~ cycle,
I =C32 or E32)( )
35
41
MHz
Minimum Clock LOW Time
13
11
ns
Minimum Clock HIGH Time
13
11
ns
Minimum Clock Period(6)
36
31
ns
2524tbl16
MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1) CL = 50pF
To Output
(MSS = L)
y
From Input
(MSS = H)
G, j5
F15
OVR
Cn+16
F=O
RAMo
Qo
RAM15
QUI
Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. MU. Com'l. Unit
26
-
20
18
20
18
-
-
-
-
34
31
25
23
41
37
39
35
41
37
41
37
37
34
41
37
40
36
D
32
29
29
26
29
26
31
28
27
25
32
29
28
26
Cn
28
25
-
-
26
24
25
23
20
18
29
26
23
21
10,1,2
35
32
30
27
35
32
34
31
29
26
35
32
30
27
13,4,5
35
32
28
26
34
31
34
31
27
25
35
32
28
16,7,B,9
25
23
-
-
-
27
-
-
-
-
-
-
30
-
-
A Bypass
ALU (I = AXX,
1XX,3XX)
-
-
-
-
27
34
Clock
f
34
31
31
28
30
33
34
31
30
31
-
-
A. B Address
ns
ns
ns
ns
ns
ns
ns
ns
2524tbl17
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H ~ L
Input
A. B Source Address
B Destination Address
"
Mil.
Com'l.
11
10
11
_(1)
10
-
,/
Hold Time
After H ~ L
Mil.
2 (3)
Cn
-
-
10,1,2
-
-
-
11
10
13,4,5
16,7, B,9
-
Mil.
25 (4)
-
12122 (5)
Hold Time
After L ~H
Mil.
Com 'I.
Unit
2
1
ns
2
1
ns
10/20 (5)
2
1
ns
Com'l.
21 (4)
Do not change (2)
-
D
Com'l.
1 (3)
Set-up Time
Before L ~H
-
17
15
0
0
ns
-
28
25
0
0
ns
-
28
25
0
0
ns·
0
0
ns
Do not change (2)
-
RAMo,15, QO,15
11
12
0
0
ns
2524tb118
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3, Source addresses must be stable prior to the H ~ L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L ~ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It Includes
all the time from stable A and B addresses to the clock L ~ H transition, regardless of when the H ~ L transition occurs.
5. First value is direct path (DATAIN ~ RAMlQ Register). Second value is indirect path (DATAIN ~ ALU ~ RAMlQ Register).
6. Guaranteed by design, not production tested.
8.2
11
IDT49C402lAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
IDT49C402B
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of
the IDT49C402B over the -55°C to + 125°C and O°C to +70°C
temperature ranges. Vcc is specified at 5V ± 10% for military
temperature range and 5V ± 5% for commercial temperature
range. All times are in nanoseconds and are measured at the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC current loads.
MII.(6)
Com'J.
Unit
Read-Modify-Write Cycle (from
selection of A, 8 registers to end
of cycle)(6)
22
19
ns
Maximum Clock Frequency to
shift Q (50% dU~ cycle,
I = C32 or E32)( )
52
60
MHz
Minimum Clock LOW Time
11
9
ns
Minimum Clock HIGH Time
11
9
ns
Minimum Clock Period(6)
24
20
ns
2524tbl19
MAXIMUM COMBINATIONAL PROPAGATION DELAYS(1} CL = 50pF
To Output
= L)
G,P
(MSS
Y
From Input
(MSS
= H)
F15
OVR
F=O
Cn+ 16
RAMo
Qo
RAM15
Q15
MIL Com'l. Mil. Com'l. MIL Com'l. Mil. Com'l. Mil. Com'J. Mil. Com'l. Mil. Com'l. Mil. Com'J. Unit
A, B Address
33
28
31
26
31
28
31
28
28
26
31
28
32
29
-
-
ns
0
26
23
23
21
23
21
25
22
22
20
26
23
24
23
22
20
-
-
20
18
19
17
15
14
22
20
18
17
-
ns
Cn
10,1,2
28
26
24
22
28
26
27
25
23
21
28
26
26
24
-
-
ns
ns
13,4,5
28
26
22
21
27
25
27
25
22
20
28
26
25
23
-
-
ns
16,7,8,9
20
18
-
-
-
ns
-
-
-
14
-
-
16
-
-
14
22
-
16
24
-
-
A Bypass
ALU (I =AXX,
1XX,3XX)
-
-
-
-
-
25
22
26
24
27
25
-
-
27
25
27
25
-
-
Clock
.f
27
25
ns
ns
2524tbl20
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
CP:
Set-up Time
Before H -7 L
Input
A, 8 Source Address
8 Destination Address
Com'l.
10
9
10
_(1)
9
10,1,2
-
13,4,5
-
-
16,7,8,9
10
9
RAMo,15, QO,15
-
-
0
Cn
"
Mil.
;/
Hold Time
After H -7 L
Mil.
2 (3)
Com'l.
1 (3)
Set-up Time
Before L -7 H
Hold Time
After L -7 H
Mil.
Com'J.
Mil.
Com'l.
Unit
20 (4)
18 (4)
2
1
ns
2
1
ns
Do not change(2)
-
-
12122(5)
10/20(5)
2
1
ns
-
16
14
0
0
ns
-
-
26
24
0
0
ns
-
-
26
24
0
0
ns
0
0
ns
0
0
ns
Do not change(2)
-
-
12
10
NOTES:
2524 tbl21
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -4 L transition to allow time to access the source data before the latches close. The A address may then
be changed. The B address could be changed if it is not a destination: i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -4 H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes
all the time from stable A and B addresses to the clock L -4 H transition, regardless of when the H -4 L transition occurs.
5. First value is direct path (DATAIN -4 RAM/Q Register). Second value is indirect path (DATAIN -4 ALU -4 RAMlQ Register).
6. Guaranteed by design, not production tested.
8.2
12
IDT49C402fAlB
16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402B
MAX. OUTPUT ENABLE/DISABLE TIMES
IDT49C402A
MAX. OUTPUT ENABLE/DISABLE TIMES
(CL= 5pF, measured to O.5V change of VOUT in nanoseconds)
Tested at CL = 50pF, correlated to 5pF
(CL= 5pF, measured to O.5V change of VouTin nanoseconds)
Tested at CL a 50pF, correlated to 5pF
Enable
Input
DE
Output
y
Mil.
18
I
I
Enable
Disable
Com'l.
Mil.
16
15
I
I
Com'l.
Input
Output
Mil.
13
DE
y
22
I
I
Disable
Com'l.
Mil.
I
20
20
I
2524 tbl 22
IDT49C402
MAX. OUTPUT ENABLE/DISABLE TIMES
Enable
DE
Output
y
Mil.
25
I
I
Disable
Com'l.
Mil.
23
25
I
I
18
2524 tbl 23
CRITICAL SPEED PATH ANALVSIS
(CL= 5pF, measured to O.5V change of VOUT in nanoseconds)
Tested at CL = 50pF, correlated to 5pF
Input
Com'l.
Com'l.
23
Critical speed paths are for the IDT49C4028 versus the
equivalent bipolar circuit implementation using four 2901Cs
and one 2902A is shown below.
The IDT49C4028 operates faster than the theoretically
achievable values of the discrete bipolar implementation.
Actual speed values for the discrete bipolar circuit will
increase due to on-chip/off-chip circuit board delays.
2524tb124
TIMING COMPARISION: IDT49C402B vs 2901C w/2902A
Data Path
(Com'I.)
16-8lt
IlP System
AB ADDR
-7
F=0
Data Path
(Mil.)
AB AD DR
-7
RAMo, 15
AB AD DR
-7
F =0
AB ADDR
-7
RAMo, 15
Unit
~71
~71
~83.5
~83.5
ns
IDT49C402B
28
23
31
25
ns
Speed Savings
43
48
52
55
ns
Four 2901 Cs + 2902A
2524tb126
TIMING COMPARISION: IDT49C402A vs 2901Cw/2902A
Data Path
(Com'I.)
16-Blt
IlP System
AB AD DR
-7
F =0
Data Path
(Mil.)
AB ADDR
-7
RAMo, 15
AB AD DR
-7
F =0
AB ADDR
-7
RAMo, 15
Unit
~71
~71
~83.5
~83.5
ns
IDT49C402A
37
36
41
25
ns
Speed Savings
34
35
42.5
43.5
ns
Four 2901 Cs + 2902A
2524 tbl 27
II
TIMING COMPARISION: IDT49C402 vs 2901C w/2902A
Data Path
(Com'I.)
16-8lt
IlP System
AB AD DR
AB ADDR
RAMo, 15
Unit
AB AD DR -7 RAMo, 15
AB AD DR -7 F =0
~71
~71
~83.5
~83.5
ns
IDT49C402A
47
40
52
44
ns
Speed Savings
24
31
31.5
39.5
ns
Four 2901 Cs + 2902A
-7
F=0
Data Path
(Mil.)
-7
2524 tbl 28
8.2
13
IDT49C402lAlB
16·BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUIT LOAD
2524 drw 05
DEFINITIONS:
CL - Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 1. SWitching Test Circuit (All Outputs)
INPUT/OUTPUT INTERFACE CIRCUIT
Vee
ESD
PROTECTION
IIH
-..
OUTPUTS
2524 drw 06
2524 drw 07
Figure 2. Input Structure (All Inputs)
Figure 3. Outputs Structure (All Outputs Except F
=0)
AC TEST CONDITIONS
OUTPUTS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2524 drw 08
GND to 3.0V
Wins
1.5V
1.5V
See Figure 1
25241bl25
Figure 4. -Outputs Structure (F';' 0)
Test
Disable Low
Enable Low
All other Tests
Switch
Closed
Open
2524 tbl29
8.2
14
G
Integrated Device Technology, Inc.
16-81T CMOS
MICROPROGRAM
SEQUENCER
IDT49C410
IDT49C410A
FEATURES:
DESCRIPTION:
• 16-bit wide address path
- Address up to 65,536 words of microprogram memory
• 16-bit loop counter
- Pre-settable down-counter for counting loop iterations
and repeating instructions
• Low-power CEMOSTM
- Icc (max.)
Military: 90mA
Commercial: 75 rnA
• Fast
- IDT49C410 meets 2910A speeds
- IDT49C410A is a 30% speed upgrade
• 33-deep stack
- Accommodates highly nested microcode
• 16 powerful microinstructions
• Available in 48-pin, 600 mil plastic and sidebraze DIP,
52-pin PLCC and 48-pin Flatpack
• Three enables control branch address sources
• Four address sources
• 2910A instruction compatibility
• Military product available compliant to MIL-STD-883,
Class B
• Standard Military Drawing #5962-88643 is listed for this
function
The IDT49C410s are architecture and function code
compatible to the 2910A with an expanded 16-bit address
path, thus allowing for programs up to 65,536 words in length.
They are microprogram address sequencers intended for
controlling the sequence of execution of microinstructions
stored in the microprogram memory. Besides the capability of
sequential access, they provide conditional branching to any
microinstruction within their 65,536 microword range.
The 33-deep stack provides microsubroutine return linkage and looping capability. The deep stack can be used for
highly nested microcode applications. Microinstruction loop
count control is provided with a count capability of 65,536.
During each microinstruction, the microprogram controller
provides a 16-bit address from one of four sources: 1) the
microprogram address register (IlPC), which usually contains
an address one greater than the previous address; 2) an
external (direct) input (D); 3) a register/counter (R) retaining
data loaded during a previous microinstruction; or 4) a last-in/
first-out stack (F).
The IDT49C10s are fabricated using CEMOS, a CMOS
technology designed for high-performance and high-reliability.
The lOT49C41 Os are pin-compatible, performance-enhanced, easily upgradable versions of the 291 OA.
The IDT49C41Os are available in 48-pin DIP (600 mil x 100
mil centers), 52-pin PLCC and 48-pin flatpack.
FUNCTIONAL BLOCK DIAGRAM
. DECREMENT!
HOLD!LOAD
II
II
16
YI
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
((l1992 Integrated Device Technology, Inc.
8.3
2551
drw 02
MARCH 1992
DSC·901413
1
IDT49C410/A
16·81T CMOS MICROPROGRAM SEQUENCER
MILITARV AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
V13
012
V12
03
V3
02
V2
01
VI
013
, V4
04
V5
05
VECT
PC
MAP
13
12
Pin 1 Identifier
~
Do
VECT
PC
MAP
Vo
13
CI
CC
ALO
FULL
OE
11
10
VII
011
Vl0
010
CCEN
CC
ALO
FULL
Os
Vs
07
V7
V9
09
V8
08
014
V14
V15
015
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
10
11
12
Vee
GNO
11
10
CCEN
1
2
12
CP
Vee
484746454443424140393837
F48-1
01
VI
Do
Vo
CI
CP
GNO
OE
VII
011
Vl0
010
13 1415 1617 1819 20 21 2223 24
2551 drw 01
2551 drw 04
DIP
TOP VIEW
FLATPACK
TOP VIEW
IDT49C410 PIN DESCRIPTIONS
Pin Name
01
VEOT
J5[
W
13
12
46
45
NC
44
43
VI
42
41
Vo
01
Do
CI
CP
I/O
I
Description
Direct input to register/counter and
multiplexer Do is LSB.
II
I
Selects one-of-sixteen instructions.
CC
I
Used as test criterion. A LOW onCC
indicates "passed" test condition.
CCEN
I
Whenever the signal is HIGH,CC is.J9!lored
and the device operates as though CC were
true (LOW).
CI
I
Low order carry input to incrementer for
microprogram counter.
RLD
I
When LOW forces loading of register/
counter regardless of instruction or
condition.
Vee
11
10
40
39
~
~
38
37
roo:
Rrn
36
35
Vl0
OE
I
Three-state control of YI outputs.
NC
34
010
CP
I
Triggers all internal state changes at LOWto-H IGH edge.
YI
a
Address to microprogram memory. Yo is
LSB, Y15 is MSB.
FULL
PL
a
a
MAP
a
Can select #2 source (usually Mapping
PROM or PLA) as direct input source.
VECT
a
Can select #3 source (for example, Interrupt
Starting Address) as direct input source.
GNO
~
VII
011
21 22 23 24 25 26 27 28 29 30 31 32 33
2551 drw03
PLCC
TOP VIEW
Indicates that 33 items are on the stack.
Can select #1 source (usually Pipeline
Register) as direct input source.
25511b101
8.3
2
IDT49C41 OfA
16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
The IDT49C41Os are high-performance CMOS micropro- with the required return linkage (the value contained in the
gram sequencers that are intended for use in very high-speed microprogram counter). On the microprogram cycle following
microprogrammable microprocessor applications. The se- the PUSH, this new return linkage data that was in the
quencers allow for direct control of up to 64K words of microprogram counter is now at the new location pointed to by
microprogram.
the stack pointer. Thus, any time the multiplexer looks at the
The heart of the microprogram sequencers is a 4-input stack, it will see this data on the top of the stack.
multiplexer that is used to select one of four address sources
During five different microinstructions, a pop operation
to select the next microprogram address. These address associated with the ~tack may occur. If the pop occurs, the
sources include the register/counter, the direct input, the stack pointer is decremented at the next LOW-to-HIGH
microprogram counter or the stack as the source for the transition of the clock. A pop decrements the stack pointer
address of the next microinstruction.
which is the equivalent of removing the old information from
The register/counter consists of sixteen D-type flip-flops the top of the stack.
which can contain either an address or a count. These edgeThe IDT49C41 Os are designed so that the stack pointer
triggered flip-flops are under the control of a common clock linkage allows any sequence of pushes, pops or stack
enable, as well as the four microinstruction control inputs. references to be used. The depth of the stack can grow to a
When the load control (RDL) is LOW, the data at the D inputs full 33 locations. After a depth of 33 is reached, the FULL
is loaded into this register on the LOW-to-HIGH transition of output goes LOW. If further PUSHes are attempted when the
the clock. The output of the register/counter is available at the stack is full, the stack information at the top of the stack will be
multiplexer as a possible next address source for the destroyed but the stack pointer will not end around. It is
microcode. Also, the terminal count output associated with necessary to initialize the stack pointer when power is first
the register/counter is available at the internal instruction PLA turned on. This is performed by executing a RESET instructo be used as condition code input for some of the tion (Instruction O). This sets the stack pointer to the stack
microinstructions. The IDT49C41 Os contain a microprogram empty position - the equivalent depth of zero. Similarly, a
counter that usually contains the address of the next micro- pop from an empty stack may place unknown data on the Y
instruction compared to that currently being executed. The outputs, but the stack pointer is designed not to end around.
microprogram counter actually consists of a 16-bit incremen- Thus, the stack pointer will remain at the 0 or stack empty
ter followed by a 16-bit register. The microprogram counter location if a pop is executed while the stack is already empty.
wi II increment the address coming out of the sequencer going
The IDT49C410's internal 16-bit register/counter is used
to the microprogram memory if the carry-in input to this during microinstructions eight, nine and fifteen. During these
counter is HIGH; otherwise, this address will be loaded into the instructions, the 16-bit counter acts as a down counter and the
microprogram counter. Normally, this carry-in input is set to terminal count (count = O) is used by the internal instruction
the logic HIGH state so that the incrementer will be active. PLA as an input to control the microinstruction branch test
Should the carry-in input be set LOW, the same address is capability. The design of the internal counter is such that, if it
loaded into the microprogram counter. This is a technique that is preloaded with a number N and then this counter is used in
can be used to allow execution of the same microinstruction a microprogram loop, the actual sequence in the loop will be
several times.
executed N + 1 times. Thus, it is possible to load the counter
There are sixteen D-inputs on the IDT49C41 Os that go with a count of 0 and this will result in the microcode being
directly to the address multiplexer. These inputs are used to executed one time. The 3-way branch microinstruction,
provide a branch address that can come directly from the instruction 15, uses both the loop counter and the external
microcode or some other external source. The fourth input condition code input to control the final source address from
available to the multiplexer for next address control is the 33- the Y outputs of the microprogram sequencer. This 3-way
deep, 16-bit wide LIFO stack. The LIFO stack provides return branch may result in the next address coming from the D
address linkage for subroutines and loops. The IDT49C41 Os inputs, the stack or the microprogram counter.
contain a built-in stack pointer that always points to the last
The IDT49C41 Os provide a 16-bit address at the Y outputs
stack location written. This allows for stack reference opera- that are under control of the OE input. Thus, the outputs can
tions, usually called loops, to be performed without popping be put in the three-state mode, allowing the writable control
store to be loaded or certain types of external diagnostics to
the stack.
The stack pointer internal to the IDT 49C41 Os is actually an be executed.
up/down counter. During the execution of microinstructions
In summary, the IDT49C410s are the most powerful
one, four and five, the PUSH operation may occur depending microprogram sequencers currently available. They provide
on the state of the condition code input. This causes the stack the deepest stack, the highest performance and lowest power
pointer to be incremented by one and the stack to be written dissipation for today's microprogrammed machine design.
8.3
3
I
IDT49C410fA
16-BIT CMOS MICROPROGRAM SEQUENCER
o Jump Zero (JZ)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1 Cond JSB PL (CJS)
2 Jump Map (JMAP)
~~~::
3Cond Jump PL(CJP)
4 Push/Cond LD CNTR (PUSH)
65 K : : 6 , 8 STACK
66
66
65t-67 •
68
67 •
t
"
T
69
65
68
25
26
N
6 Cond Jump Vector (CJV)
REGISTER!
COUNTER
7 Cond JUMP R/PL (JRP)
30
65
66
67
66
65t-67 •
,.
69
I
'
5 Cond JSB R/PL (JSRP)
3'
T 36
8 Repeat Loop, CNTR:f. 0 (RFCT)
20
30
21
31
9 Repeat PL, CNTR :f. 0 (RPCT)
~ STACK
65r'"
~ ~
66
67
N
(PUSH)
COUNTER
REGISTER!
68
~'
65'
66
31
40
41
32
42
33
43
34
44
10 Cond Return (CRTN)
COUNTER
(LOCT)
65
67 •
66
68
67
69 •
68
70
69
70
11 Cond Jump PL & POP (CJPP)
12 LD CNTR & Continue (LDCT)
65
66
I}-+-----~
r,
40
41
65
66 •
42
67
68
71
COUNTER
13 Test End Loop (LOOP)
65~
STACK
(PUSH)
66
6st
67
: k1STACK
: :~:':~EPJ
68
68 •
14 Continue (CONT)
66 •
15 Three-Way Branch (TWB)
67
67
68
69
70
COUNTER
72
69
73
Figure 1. IDT49C410 Flow Diagrams
8.3
2551 drw05
4
IDT49C410/A
16·BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 OPERATION
The IOT49C41as are CMOS pin-compatible implementations of the Am291 a and 2910A microprogram sequencers.
The lOT49C41 a sequencers are functionally identical except
that they are 16 bits wide and provide a 33-deep stack to give.
the microprogrammer more capability in terms of microprogram subroutines and microprogram loops. The definition of ,
each, microprogram instruction is shown in the table of
instructions. This table shows the results of each instruction
in terms of controlling the mUltiplexer, which determines the Y
outputs, and in controlling the signals that can be used to
enable various branch address sou rces (pI, MAP, 'lECf). The
operation of the register/counter and the 33-deep stack after
the next LOW-to-H IGH transition of the clock are also shown.
The internal multiplexer is used to select which of the internal
sources is used to drive the Y outputs. The actual value
loaded into the microprogram counter is either identical to the
Y output or the Y output value is incremented by 1 and placed
in the microprogram counter. This function is under the control
of the carry inputs. For each of the microinstruction inputs,
only one of the three outputs (PL, MAP or \7ECT) will be LOW.
Note that this function is not determined by any of the possible
condition code inputs. These outputs can be used to control
the three-state selection of one of the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the
conditional instructions. These are fully defined in the table of
instructions. The RLO input can be used to load the internal
register/counter at any time. When this input is LOW, the data
at the 0 inputs will be loaded into this register/counter on the
LOW-to-HIGH transition of the clock. Thus, the RLO input
overrides the internal hold or decrement operations specified
by the various microinstructions. The DE input is normally
LOW and is used as the three-state enable for the Y outputs.
The internal stack in the lOT49C41 as is a last-in/first-out
memory that is 16-bits in width and 33 words deep. It has a
stack pointer that addresses the stack and always points to the
value currently on the top of the stack. When instruction a
(RESET) is executed, the stack pointer is initialized to the top
of the stack which is, by definition, the stack empty condition.
Thus, the contents of the top of the stack are undefined until
the forced PUSH occurs. A pop performed while the stack is
empty will not change the stack pointer in any way; howeve~,
it will result in unknown data at the Y outputs.'
.
By definition, the stack is full any time 33 more PUSHes
than pops have occurred since the stack was last empty.
When this happens, the FULL Flag will go LOW. This signal
first goes LOW on the microcycle after the 33 pushes occur.
When this signal is LOW, no additional pushes should be
attempted or the information on the top of the stack will be lost.
THE IDT49C410 INSTRUCTION SET
This data sheet contains a block diagram ofthe lOT49C41 a
microprogram sequencers. As can be seen, the devices are
controlled by a 4-bit microinstruction word (13 -10). Normally,
this word is supplied from one 4-bit field of the microinstruction
word associated with the entire state machine system. These
four bits provide for the selection of one of the sixteen powerful
8.3
instructions associated with selecting the address of the next
microinstruction. UnusedYoutputscanbe left open; however,
the corresponding most significant 0 inputs should be tied to
ground for smaller microwords. This is necessary to make
sure the internal operation of the counter is proper should less
than 64K of microcode be implemented. As shown in the block
diagram, the internal instruction PLA uses the four instruction
inputs as well as the ee, CCEi\J and the internal counter = 0
line for controlling the sequencer. This internal instruction
PLA provides all of the necessary internal control signals to
control each particular part of the microprogram sequencer.
The next address at the Y outputs of the lOT49C41 as can be
from one of four sources. These include the internal microprogram counter, the last-inlfirst-out stack, the register/counter
and the direct inputs.
The following paragraphs will describe each instruction
associated with the lOT49C41 as. As a part of the discussion,
an example of each instruction is shown in Figure 1. The
purpose of the examples is to show microprogram flow. Thus,
in each example the microinstruction currently being
executed has a circle around it. That is, this microinstruction is
assumed tobe the contents of the pipeline register at the
output of the microprogram memory. In these drawings, each
of the dots refers to the time that the contents of the microprogram memory word would be in the pipeline register and is
currently being executed.
.
INSTRUCTION 0 JUMP 0 (JZ)
This Conditional Jump is used at power-up time or at any
restart sequence when the need is to reset the stack pointer
and jump to the very first address in microprogram memory.
The Jump a instruction does not change the contents of the
register/cou nter.
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine, instruction is the one
used to call microprogram subroutines., The subroutine address will be contained in the pipeline register and - presented at the 0 inputs. If the condition code test is passed, a
branch is taken to the subroutine. Referring to the flow
diagram for the IOT49C41Os shown in Figure 1, we see that
the content of the microprogram counter is 68. This value is
pushed onto the stack and the top of stack pointer is
incremented. If the test is failed, this Conditional Jump to
Subroutine instruction behaves as a simple continue. That is,
the content of microinstruction address 68 is executed next.
INSTRUCTION 2 JUMP MAP (JMAP) .
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction
opcode. This is typically accomplished by using a mapping
PROM as an. input to the, 0 inputs on the microprogram
sequencer. The JMAP instruction branches to the address
appearing on the 0 inputs. In the flow diagram shown in Figure
1, we see that the branch actually will be, the contents .of
microinstruction 85 and this instruction will be executed next.
5
IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 INSTRUCTION OPERATIONAL SUMMARY
1
Mnemonic
JZ
CJS
2
3
JMAP
CJP
4
PUSH
5
JSRP
6
CJV
7
JRP
8
RFCT
9
RPCT
10
CRTN
11
CJPP
12
13
LDCT
LOOP
14
15
CONT
TWB
13-10
0
CC
X
Counter
Test
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
=0
NOT=O
=0
NOT=O
PASS
FAIL
PASS
FAIL
X
X
X
X
X
X
X
X
X
PASS
PASS
FAIL
FAIL
=0
NOT=O
=0
NOT=O
PASS
FAIL
X
X
PASS
FAIL
Stack
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC
Address
Source
0
D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK
Register
Counter
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC
Enable
Select
PL
PL
PL
MAP
PL
PL
PL
PL
PL
PL
VECT
VECT
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
2551 Tbl02
NC = No Change; DEC = Decrement
INSTRUCTION 3 CONDITIONAL JUMP PIPELINE (CJP)
The simplest branching control available in the IDT49C41
microprogram sequencers is that of conditional jump to
address. In this instruction, the jump address is usually
contained in the microinstruction pipeline register and
presented to the D inputs. If the test is passed, the jump is
taken while, if the test fails, this instruction executes as a
simple continue. In the example shown in the flow diagram of
Figure 1, we see that if the test is passed, the next
microinstruction to be executed is the content of address 25.
If the test is failed,· the microcode simply continues to the
contents of the next instruction.
a
INSTRUCTION 4 PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally
loaded during the same instruction that pushes the current
value of the microprogram counter on to the stack. Under any
condition independent of the conditional testing, the microprogram counter is pushed on to the stack. If the conditional test
is passed, the counter will be loaded with the value on the D
inputs to the sequencer. If the test fails, the contents of the
counterwill not change. The PUSH/Conditional Load Counter
8.3
instruction is used in conjunction with the loop instruction
(Instruction 13), the repeat file based on the counter
instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).
INSTRUCTION 5 CONDITIONAL JUMP TO SUBROUTINE R/PL (JSRP)
Subroutines may be called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register.
In this instruction the contents of the microprogram counter
are pushed on the stack and the branch address for the
subroutine call will be taken from either the internal register/
counter or the external pipeline register presented to the D
inputs. If the conditional test is passed, the subroutine
address will be taken from the pipeline register. If the
conditional test fails, the branch address is taken from the
internal register/counter. An example of this is shown in the
flow diagram of Figure 1.
INSTRUCTION 6 CONDITIONAL JUMP VECTOR (CJV)
The Conditional Jump Vector instruction is similar to the
Jump Map instruction in that it allows a branch operation to a
microinstruction as defined from some external source,
6
IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
except that it is conditional. The Jump Map instruction is
unconditional. If the conditional test is passed, the branch is
taken to the new address on the D inputs. If the conditional test
is failed, no branch is taken but rather the microcode simply
continues to the next sequential microinstruction. When this
instruction is· executed, the VECT output is LOW unconditionally. Thus, an external 12-bit field can be enabled on to the
D inputs of the microprogram sequencer.
INSTRUCTION 7 CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline
register always causes a branch in microcode. This jump will
be to one of two different locations in the microcode address
space. If the test is passed, the jump will be to the address
presented on the D inputs to the microprogram sequencer. If
the conditional test fails, the branch will be to the address
contained in the internal register/counter.
INSTRUCTION 8REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address for the
loop would be initialized by using the PUSH/Conditional Load
Counter instruction. Then, when the repeat loop instruction is
executed, if the counter is not equal to 0, the next microword
address will be taken from the stack. This will cause a loop to
be executed as shown in the Figure 1 flow diagram. Each time
'the microcode sequence goes around the loop, the counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from
the microprogram counter. This instruction performs a timed
wait or allows a single sequence to be executed the desired
number of times. Remember, the actual number of loops
performed is equal to the value in the counter plus 1.
INSTRUCTION 9 REPEAT PIPELINE, COUNTER NOT EQUAL TO 0
(RPCT)
This instruction is another technique for implementing a
loop using the counter. Here, the branch address forthe loop
is contained in the pipeline register. This instruction doesnot
use the stack in any way as a part of its implementation. As
long as the counter is not equal to 0, the next microword
address will be taken from the D inputs of the microprogram
sequencer. When the counter reaches 0, the internal multiplexer will select the address source from the microprogram
counter, thus causing the microcode to continue on and leave
the loop.
INSTRUCTION 10 CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating
subroutines. The fact that it is conditional allows the subroutine either to be ended or to continue. If the conditional test is
passed, the address of the next microinstruction will be taken
from the stack and it will be popped. If the conditional test fails,
the next microinstruction address will come from the internal
microprogram counter. This is depicted in the flow diagram of
Figure 1. It is important to remember that every subroutine
call must somewhere be followed by a return from subroutine
8.3
call in order to have an equal number of pushes and pops on
the stack.
INSTRUCTION 11CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a
technique for exiting a loop from within the middle of the loop.
This is depicted fully in the flow diagram for the IDT49C41 Os,
as shown in Figure 1. The conditional test input for this
instruction results in a branch being taken if the test is passed.
The address selected will be that on the D inputs to the
microprogram sequencer and, since the loop is being terminated, the stack will popped. Should the test be failed on the
conditional test inputs, the microprogram will simply continue
to the next address as taken from the microprogram counter.
The stack will not be affected if the conditional test input is
failed.
INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)
The Load Counter and Continue instruction is used to place
a value on the Dinputs in the register/counter and continue to
the next microinstruction.
INSTRUCTION 13 TEST END OF LOOP (LOOP)
The Test End of Loop instruction is used as a last instruction
in a loop associated with the stack. During this instruction, if
the conditional test input is failed, the loop branch 'address will
be that on the stack. Since we may go around the loop a
number of times, the stack is 110t popped. If the conditional test
input is passed, then the loop is terminated and the stack is
popped: Notice that the loop instruction requires a PUSHto
be performed at the instruction immediately prior to the loop
return address. This is necessary so as to have the correct
address on the stack before the loop operation. It is for this
reason that the stack pointer always points to the last thing
written on the stack.
INSTRUCTION 14CONTINUE (CONT)
The Continue instruction is a simple instruction whereby
the address for the microinstruction is taken from the microprogram counter. This instruction simply causes sequential
program flowtothe next microinstruction in microcode memory.
INSTRUCTION 15 THREE WAY BRANCH (TWB)
The Three Way Branch instruction is used for looping while
waiting for a conditional event to come true; If the event does
not come true after some number of microinstructions, a
branch is taken to another microprogram sequence. This is
depicted in Figure 1 showing the IDT49C41° flow diagrams
and is also described in full detail in the IDT49C41 O's instruction operational summary. Operation of the instruction is such
that any time the external conditional test input is passed, the
next microinstruction will be that associated with the program
counter and the loop will be left. The stack is also popped.
Thus, the external test input overrides the other possibilities.
Should the external test input not be true, the rest of the
operation is controlled by the internal counter. If the counter
7
I
IDT49C410/A
16-BITCMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
is not equal to 0, the loop is taken by selecting the address on
the top of the stack as the address out of the Y outputs of the
lOT49C41 O. In addition, the counter is decremented. Should
the external conditional test input be failed and the counter
also have counted to 0, this instruction "times out". The result
is thatthe stack is popped and a branch is taken to the address
presented to the 0 inputs of the IOT49C410 microprogram
sequencer. This address is usually provided by the external
pipeline register.
CONDITIONAL TEST
Throughout this discussion we have talked about microcode passing the conditional test. There are actually two inputs
associated with the conditional test input. These include the
'CC"EN and the CC inputs. The CCEl\f input is a condition code
enable. Whenever the 'CCEi'iJ input is HIGH, the CC input is
ignored and the device operates as though the CC input were
true (LOW). Thus, a fail of the external test condition can be
defined as 'CCEi'iJ equals LOW and CC equals HIGH. A pass
condition is defined as a 'CCEi'iJ equal to HIGH or a CC equal
to LOW. It is important to recognize the full function of the
condition code enable and the condition code inputs in order
to understand when the test is passed or failed.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee
VTERM
Rating
Com'l.
Power Supply
Voltage
Terminal Voltage
with Respect
to Ground
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Mil.
-0.5 to +7.0 -0.5 to +7.0
Unit
V
-0.5 to
Vcc+ 0.5
-0.5 to
Vcc+ 0.5
V
o to +70
-55 to +125
°C
Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = OV
5
pF
COUT
Output Capacitance
VOUT= OV
7
NOTE:
pF
2551 tbl 04
1. This parameter is sampled and not 100% tested.
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to +125 -65 to +135
°C
. TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
30
30
mA
NOTE:
Parameter(l)
Symbol
2551 tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
Implied,' Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Commercial' TA = O°C to + 70°C , Vcc = 5 OV +
- 5%; Military: TA = - 55°C to + 125°C, Vcc = 5.0V +- 10%
Min.
Typ. (2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level (4)
2.0
-
V
VIL
' Input LOW Level
Guaranteed Logic LOW Level (4)
-
-
0.8
V
0.1
5
~A
-0.1
-5
~A
2.4
4.3
-
V
2.4
4.3
-
-
0.3
0.5
0.3
0.5
-0.1
-10
0.1
10
-
-
Symbol
Test Conditions (1)
Parameter
Input HIGH Current
Vcc = Max., VIN
IlL
Input LOW Current
Vcc
VOH
Output HIGH Voltage
Vcc
IIH
I:
Vcc
=Max.; VIN = GND
=Min.
VIN = VIH or VIL
VOL
loz
Output LOW Voltage
Off State (High Impedance)
Vcc
IOH
=Min.
Output Short Circuit Current
=-15 mA COM'L.
IOL = 20 mA MIL
VIN = VIH or VIL
IOL
Vcc = Max.
Vo=OV
I:
24 mA COM'L
Vo = Vcc (Max.)
Output Current
los
IOH =-12 mA MIL
Vcc = Max., VOUT = OV (3)
-30
NOTES:
V
~A
mA
2551 tbl 05
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2.. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels shOUld only be static tested in a noise-free environment.
8.3
8
IDT49C410/A
16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd.)
Commercial: TA = O°C to + 70°C, Vcc = 5.0V ± 5%; Military: TA = - 55°C to + 125°C,Vcc = 5.0V ± 10%
Symbol
I eeOH
CP
I CCOl
Min.
Typ. (2)
Max.
Unit
Vee =Max.
VIN =Vcc or GND
fcp =a, CP =H
-
35
50
mA
Vcc= Max.
VIN =Vcc or GND
fcp = 0, CP = L
-
35
50
mA
-
0.3
0.5
mAl
Input
-
1.0
3.0
mAl
1.0
1.5
MHz
mA
Test Conditions (1)
Parameter
Quiescent Power Supply Current
=H (CMOS Inputs)
Quiescent Power Supply Current
CP
=L (CMOS Inputs)
I CCT
Quiescent Input Power Supply
Vcc =Max., VIH
Current (per Input @ TTL High) (5)
I CCD
Dynamic Power Supply Current
Icc
Total Power Supply Current (6)
=3.4V, fcp =0
Vcc =Max.
MIL
VIN =Vcc or GND
Outputs Open, OE = L
COM'L
VCC =Max., fcp
=10MHz
Outputs Open, OE= L
MIL
COM'L
-
45
80
45
65
-
50
90
50
75
CP =50 % Duty cycle
VHC!> VIH, Vll!> VlC
Vcc - Max., fcp - 10MHz
MIL
Outputs Open, OE =L
CP =50 % Duty cycle
COM'L
VIH
=3.4V, Vil =O.4V
NOTES:
2551 tbl06
5. I CCQT is derived by measuring the total current with all the inputs tied together at 3.4 V, subtracting out I CCQH, then dividing by the total number of inputs.
6. Total Supply Current Is the sum of the Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
I cc = I CCQH (CDH) + I CCQL (1 - CDH) + I CCT (N T x D H) + I cco (f cp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (VIN = 3.4V)
NT= Number of dynamic inputs driven at TTL levels
fcp = Clock Input frequency
CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices in
an automatic environment. These are:
1) Properdecoupling atthetesthead is necessary. Placement
of the capacitor set and the value of capacitors used is
critical in reducing the potential erroneous failures resulting
from large Vcc current changes. Capacitor lead length
must be short and as close to the OUT power pins as
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.
8.3
3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, lOT recommends using VIL::;OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
required. The ground plane must be sustained from the
performance board to the OUT interface board. All unused
interconnect pins mustbe properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.
9
II
IDT49C410/A
16·BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
IDT49C410A
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
t (H)
t (5)
Inputs
t (5)
Com'l.
Mil.
Com'l.
Mil.
Unit
6
7
0
0
ns
DI~R
I,
Inputs
t (H)
Com'l.
Mil.
Com'l.
DI~R
16
0
Mil.
0
Unit
16
ns
DI~PC
13
15
0
0
ns
OI~PC
30
30
0
0
ns
10-3
23
15
15
6
11
25
18
18
7,
0
0
0
0
0
0
0
0
0
0
ns
10-3
CC
ns
CCEN
ns
CI
ns
RLD
38
35
35
18
20
0
0
0
0
0
0
0
0
0
0
ns
ns
35
24
24
18
19
CC
CCEN
CI
RLO
12
ns
ns
ns
ns
25511bll0
2551 tbl07
II. COMBINATIONAL DELAYS
II. COMBINATIONAL DELAYS
y
PL, VECT, Jli35
Inputs
00-11
10-3
CC
CCEN
CP
OE(1)
Mil.
Com'l.
12
20
16
16
28
15
25
20
20
33
-
-
13
15
-
-
10/10 13/13
y
Mil. Com'l. Mil.
Com'l.
-
roo:
-
Unit
Inputs
-
-
ns
00-11
-
ns
10-3
ns
CC
-
ns
CCEN
22
25
ns
-
-
ns
CP
QE(1)
NOTE:
Com'l.
20
35
30
30 .
40
RJII
PL, VECT, 'fMiJ5
Mil. Com'l. Mil.
Mil.
25
Com'l.
-
-
40
36
36
46
30
35
-
-
25/27 25/30
-
-
ns
-
ns
31
35
ns
-
-
NOTE:
2551 tbl08
Unit
-
ns
ns
ns
2551 tblll
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL - SpF. Tested at CL - SOpF. correlated to SpF.
1. Enable/Disable. Disable times measure to O.SV change on output voltage
level with CL = SpF. Tested at CL .. SOpF. correlated to SpF.
III. CLOCK REQUIREMENTS
III. CLOCK REQUIREMENTS
Com'J.
Mil.
Unit
Com'l.
Mil.
Unit
Minimum Clock LOW Time
18
ns
Minimum Clock LOW Time
20
17
35
ns
Minimum Clock HIGH Time
ns
Minimum Clock Period
20 '
50
25
25
51
ns
Minimum Clock HIGH Time
20
20
40
Minimum Clock Period
ns
ns
2551 tbl12
2551 tbl 09
SWITCHING WAVEFORMS
INPUTS 3.0V
OV
:====~§§![g8~k:===:J~~!§§l
.3.0V
CLOCK· OV
CLOCK TO
OUTPUT DELAY
OUTPUTS
2551 drw 06
8.3
10
IDT49C410/A
16·81T CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
IIH
INPUTS
....
OUTPUTS
u---"
Figure 3. Output Structure
Figure 2. Input Structure
2551 drwoa
2551 drw 07
TEST LOAD CIRCUIT
Vcc
Test
Disable Low
Enable Low
Switch
Closed
All other Tests
Open
2551 tbl13
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator
Figure 4. Switching Test Circuits
2551 ->. ~>= Cl Cl
>-.>-.>- F. >-.>-.
8!rl£(f tt~aa~£J:££~££
X7
X8
X9
XlO
Xll
X12
X13
X14
X15
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
[J68_1
2
3
4
5
8
9
1011121314151617181920212223242526
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
2577 drw 03
~~Clmox>UuUuox~~~~
x~~~~~gggg~~~~~~
a.
00
0
PLCC
TOP VIEW
0
..... N
(1')"'-
L()
>-~$!. ~~~):.o .;::ff,!>-.>-.>-. >-:>=. >-.
rf.~~ £ .t~a:a ~.rt.£ J:J: ~
2577drw 02
Po, Yo
Xo
Xl
X2
X3
XXs4
X6
X7
Xa
X9
Xl0
Xll
X12
X13
X14
£
I::l.d~~~~~~~~~:::L\;J..48~
1::2
1::3
1::4
1::5
c: 6
C:7
1:: 8
1::9
1::10
1::11
1::12
c:13
C:14
1::15
1::16
47~
4~
4~
44~
F64-1
43:::1
42:::J
41~
40:::::1
39::::J
38~
37~
36:::J
35:::1
3~
33~
P16
P17
P18
P19
P20
P2l
P22
P23
P24
P25
P26
P27
P28
P29
P30
P3l
EI
FLATPACK
TOP VIEW
8.4
2
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
11
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NC
X15
RND ACC CLKv
TSL
SUB CLKx Vee
TC PREL CLKp P33
TSX TSM
10
X13
X14
09
X11
X12
P30
P31
08
X9
X10
P2B
P29
07
X7
XB
P26
P27
06
X5
X6
P24
P25
05
X3
X4
P22
P23
04
X1
X2
P20
P21
Xo
P1B
P19
PH
03
02
01
Yo,
Po
NC
t?
Pin1 / " "
Designator
A
P34
G68-2
P32
Y1,
P1
Y3,
P3
Y5,
P5
Y7,
P7
YB,
PB
Y10,
P10
Y12,
P12
Y14,
P14
P16
Y2,
P2
Y4,
P4
Y6,
P6
GND
Y9,
P9
Y11,
P11
Y13,
P13
Y15,
P15
NC
B
C
D
E
F
G
PGA
TOP VIEW
H
K
NC
L
2sndrw 05
PIN DESCRIPTIONS
Pin Name
XO-15
YO'15/Po-15
1/0
I
110
P16 - 32
110
P33 - 35
110
CLKX
I
Description
Data Inputs
Multiplexed 110 port. Yo -15 are data inpU1s and can be used to preload LSP register on PREL = 1. Po- 15
are LSP register outP.uts - enabled by TSL.
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when
PREL= 1.
Input data Xo - 15 loaded in X input register on CLKX rising edge.
CLKY
I
Input data Yo -15 loaded in Y input register on CLKY rising edge.
CLKP
I
Output data loaded into output register on rising edge of CLKP.
TSX
I
TSX = 1 enables XTP outputs, TSX = 0 tristates P33 - 35 lines.
TSM
I
TSM = 1 enables MSP outputs, TSM = 0 tristates P16 - 32 lines.
TSL
I
TSL = 1 enables LSP outputs, TSL = 0 tristates Po - 15 lines.
PREL
I
When PREL= 1 data is input on Po - 15 lines. When PREL = 0, inpU1s on these lines are ignored.
ACC
I
This inpU1 is loaded into the control register on the rising edge of (CLKX + CLKY).
When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a
subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a
simple multipler with no accumulation
SUB
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
This input is active only when ACC = 1. When SUB = 1 the contents of the outpU1 register are subtracted
from the result and stored back in the output register. When SUB = 0 the contents of the outpU1 register
are added to the result and stored back in the output register
TC
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When TC = 1, the X and Y input are assumed to be in two'S complement form. When TC = 0, X and Y
inputs are assumed to be in unsigned magnitude form
RND
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and
XTP data
2577tb101
8.4
3
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMP,?RATURE RANGES
PRELOAD TRUTH TABLE
NOTES ON TWO'S COMPLEMENT FORMATS
PREL
TSX
TSM
TSL
XTP
0
0
0
0
Q
Q
Q
0
0
0
1
Q
Q
HiZ
0
0
1
0
Q
HiZ
Q
0
0
1
1
Q
HiZ
HiZ
0
1
0
0
HiZ
Q
Q
0
1
0
1
HiZ
Q
HiZ
0
1
1
0
HiZ
HiZ
Q
0
1
1
1
HiZ
HiZ
HiZ
1
0
0
0
HiZ
HiZ
HiZ
1
0
0
1
HiZ
HiZ
PL
1
0
1
0
HiZ
PL
PL
HiZ
HiZ
HiZ
1
0
1
1
HiZ
1
1
0
0
PL
PL
PL
PL
1
1
0
1
1
1
1
0
1
1
1
1
MSP
LSP
PL
HiZ
PL
PL
PL
HiZ
PL
NOTES:
2577 tbl 02
Hi Z = Output buffers at high impedance (output disabled)
a = Output buffers at low impedance. Contents of output register will be
transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload data
supplied externally at output pins will be loaded into the output
register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS(1)
Rating
Symbol
Vee
Power Supply
Voltage
VTERM
Terminal Voltage
with Respect to
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz) .
Commercial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
-0.5 to
Vee +0.5V
":0.5 to
Vee +0.5V
V
a to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
Storage
Temperature
DC Output
Current
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
50
50
rnA
NOTE:
NOTE:
Output Capacitance
Conditions
Max.
VIN = OV
10
VOUT= OV
12
Unit
pF
pF
2577 tbl 04
1. This parameter is measured at characterization and not 100%tested. .
Operating
Temperature
lOUT
Parameter(1)
Symbol
CIN
Input Capacitance
COUT
TA
TSTG
1. In two's complement notation, the location of the binary
point that signifies the separation of the fractional and
integer fileds is just after the sign, between the sign bit
(-2°) and the next significant bit for the multiplier inputs.
This same format is carried over to the output format,
except that the extended significance of the integer filed is
provided to extend the utility of the accumulator. In the
case of the output rotation, the output binary point is
located between the2° and 21 bit positions. The location of
the binary point is arbitrary, as long as there is consistency
with both the input and output formats. The number filed
can be considered entirely integer with the binary point just
to the right of the least significant bit for the input, product
and the accumulated sum.
2. When in the non-accumulating mode, the first four bits (P34
to P31) will all indicate the sign of the product. Additionally,
the P30 term will also indicate the sign with one exception,
when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the -1 x -1 is a valid operation
that yields a +1 product.
3. In operations that require the accumulation of single products or sum of products, there is no change in format. To
allow for a valid summation beyond that available for a
single multiplication product, three additional significant
bits (guard bits) are provided. This is the same as if the
product was accu mulated off-chip ina separate 35-bit wide
adder. Taking the sign at the most significant bit position
will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand
portion of the accumulator, the sign will be extended into
the lesser significant bit positions.
II
2577lb103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
8.4
4
IDTI210L
16 x 16 PARALLEL CMOS MULTIPLlER·ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = S.OV ± 10%, TA = O°C to +70°C; Military:
Vee= SV ± 10%, TA = -SsoC TO +12S°C)
Commercial
Symbol
Test Condltlons(5)
Parameter
Min.
TVp. 55ns.
5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL
(Vee = SV± 10%, TA = 0° to +70°C)
7210L25
Parameter
Symbol
tMA
Multiply-Accumulate Time(2)
tD
Output Delay(2)
tENA
3-State Enable Time
tDIS
ts
7210L35
7210L45
7210L55
7210L65
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.0 45
55
65
2.0
2.0 35
2.0
2.0
ns
25
2.0
20
2.0
25
2.0
25
2.0
30
2.0
35
ns
20
-
30
-
30
ns
25
-
25
30
ns
Input Register Set-up Time
12
12
-
15
3
3
3
tpw
Clock Pulse Width
10
-
25
Relative Hold Time
0
-
0
-
20
tHCl
-
-
ns
3
-
25
Input Register Hold Time
-
20
tH
-
-
25
3-State Disable Time(1)
-
0
-
0
-
20
10
15
0
25
30
3
NOTES:
ns
ns
ns
2577tb106
1. Transition is measured ±500mV from steady state voltage.
2. Minimum delays guaranteed but not tested
AC ELECTRICAL CHARACTERISTICS MILITARY
Parameter
Symbol
tMA
Multiply-Accumulate Time(2)
(Vee = sv ± 10%, TA = -S5° to + 125°C)
7210L30 7210L40 7210L55 7210L65
2.0
20
2.0
25
2.0
30
2.0
35
2.0
35
ns
-
20
25
-
30
-
30
-
35
ns
-
20
-
25
-
25
-
20
-
-
30
-
25
3
-
3
20
-
25
tD
Output Delay(2)
tENA
3-State Enable Time
3-State Disable Time(1)
Input Register Set-up Time
12
-
15
tDls
ts
7210L75
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.0 40
2.0 55
2.0 65
2.0 75
ns
2.0
30
tH
tpw
Input Register Hold Time
3
-
3
Clock Pulse Width
10
15
tHCl
Relative Hold Time
0
-
NOTES:
0
0
0
-
30
ns
25
-
ns
3
-
ns
25
-
ns
0
ns
2577tb107
1. Transition is measured ±500mV from steady state Voltage.
2. Minimum delays guaranteed but not tested
8.4
5
ID17210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
AC TEST CONDITIONS
Test
Disable Low
Enable Low
Closed
A" Other Tests
Open
DEFINITIONS:
CL =
RT =
Input Pulse Levels
Switch
GND to 3.0V
Input Rise/Fa" Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
2577lb109
1.5V
Output Load
See Rgure 1
Load capacitance: includes jig and probe capacitance.
Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2577lb108
Figure 1. AC Test Load Circuit
Vee
ESD
PROTECTION
J
IIH -..
INPUTS o-"'V"--_........-I
IlL 4 - R
Figure 2. Input Interface Circuit
~H
...---0 OUTPUTS
t:L
Figure 3. Output Interface Circuit
8.4
6
IDT7210L
16 x 16 PARALLEL CMOS MULnPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
THREESTATE
CONTROL
3V
CLOCK
INPUT
OUTPUT
THREE·
STATE
1.SV
oV
Figure 8. Set-Up and Hold nma
+
. tDls
j~tENA
HIGH IMPEDANCE
Figura 9. Three-Stata Control Timing Diagram
INPUT
INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL
OUTPUT
Figure 10. Timing Diagram
8.4
7
0;6
...)(::1
BINARY POINT
~
(I)'"
"00
>r
~
r
r
m
r
(")
::
o
en
::
c
~
"0
r
SIGNAL
r--r--+--+--+--1---r--r--r--+--+--+-~---r--r--+--+--+--+-~~-r--r--+--+-~--+-~---r--r--+--+--+--4-~--~~DIGIT
L-~_ _~~_ _~_ _~~_ _~_ _L-~_ _~_ _~~_ _~_ _L-~_ _~~_ _~_ _~~_ _~_ _L-~_ _~_ _L-~_ _~~_ _~_ _~~_ _~_ _~~~VALUE
m
::tI
~
g
::
LSP
2577drw 10
c
>
a
::tI
Figure 4. Fractional Two's Complement Notation.
(I)
:.:.
BINARY POINT
::
r=
~
::tI
<
~
c
8
::
::
m
::tI
SIGNAL
~-+--+-~--~--+--4--~--~-+--4---~-+--+-~~-r--+--4--~--~-+--4---~-+--+-~~~--+--4--~--~-+--4-~~-+--4
DIGIT
L--L__~~__~__~~__~__~~__~__L--L__~~L-~__~~__-L__L-~__~__~~__~~__~__~~__~__~~__~~L--L~VALUE
XTP
LSP
2577drw 11
Figure 5. Fractional Unsigned Magnitude Notation
(")
);
r
iri
::
"0
m
::tI
~
::tI
m
~
Z
(I)
G')
m
en
iii
~6
x::j
BINARY POINT
;i
2°
;1
2°
I =~
~:a
:a
:.-
SIGNAL
e~crJE
SIGNAL
e~crJE
I~
==
0
I~~
"tI
!:
m
~SlGNAl
:a
~
e~crJE
2°
0
g
LSP
==
C
2517drw 12
E
Figure 6. Integer Two's Complement Notation
0
:a
CI)
:co
,
BINARY POINT
;i
;1
;l
~
~
2°
XTP
SIGNAL
DIGIT
VALUE
SIGNAL
DIGIT
VALUE
I~;!
~
~
Ii
m
:a
0
SIGNAL
:;
e~crJE
-4
LSP
2577drw 13
Figure 7. Integer Unsigned Magnitude Notation
I
r-
m
==
"tI
m
:a
~
:a
m
:a
:.Q)
zC)
m-
(J)
f;J
16 x 16 PARALLEL
CMOS MULTIPLIERS
IDT7216L
IDT7217L
Integrated Device Technology,lnc.
FEATURES:
DESCRIPTION: .
•
•
•
•
The IOT7216/10T7217 are high-speed, low-power
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications. Utilization of a modified Booths
algorithm and lOT's high-performance, submicron CEMOS
technology, has achieved speeds comparable to bipolar (20ns
max.), at 1/10 the power consumption.
The 10T7216110T7217 are ideal for applications requiring
high-speed multiplication such as fast Fourier transform
analysis, digital filtering, graphic display systems, speech
synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are
inadequate.
.
All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered Ootype flip-flop. In
the IOT7216, there are independent clocks (CLIO', CLKY,
CLKM, CLKL) associated with each of these registers. The
IOT7217 has only a single clock input (ClK) arid three register
enables. ENX and ENY control the two input registers, while
ENP controls the entire product.
The IOT7216/IOT7217 offer additional flexibility with the FA
control and MSPSEL functions. The FA control formats the
output for two's complement by shifting the MSP up one bit
and then repeating thesign bit in the MSB of the lSP. The
•
•
•
•
•
•
•
•
•
•
•
16 X 16 parallel multiplier with double precision product
20ns clocked multiply time
Low power consumption: 120mA
Produced with advanced submicron CEMOSm high
performance technology
IOT7216L is pin- and function compatible with TRW
MPY016H/K and AMO Am29516 .
IOT7217L requires a single clock with register enables
making it pin- and function compatible with AMO
Am29517
Configured for easy array expansion
User-controlled option for transparent output register
mode
Round control for rounding the MSP
Input and output directly TTL-compatible
Three-state output
Available in plastic and Top Braze, DIP, PLCC, Flatpack
and Pin Grid Array
,
Military product compliant to MIL-STO-883, Class B
Standard Military Drawing #5962-86873 is listed on this
function for IOT7216 and Standard Military Drawing
#5962-87686 is listed for this function for IOT7217.
Speeds available:
Commercial:· L20/25/35/45/55/65
Military:
L25/30i40/55/65175
FUNCTIONAL BLOCK DIAGRAMS
XM X15-0
10T7216
RND
XM X15-Q
CLKY __~~__~-;__~
CLKX - -.......H-lI~
10T7217
. RND
YM
CLK-.+-~__~~+-__~
Ef\JX -+--x 0:0 xxx
C/)
l
nnnnnnnnnnnnnnnn
0..0..
64636261 605956575655545352515049
P1S,
P14,
P13,
P12,
Pu,
PlO,
P9,
P8,
P7,
Pe,
Ps,
P4,
P3,
P2,
Pl,
Po,
P3l
P30
P29
P28
P27
P26
P2S
P24
P23
P22
P2l
P20
P19
P18
P17
P16
e 1
c: 2
c:3
e4
c:5
1::6
1::7
e 6
c:9
el
ell
c:l
1::1
1::1
e15
c:16
0..00
0
X
Z\W«f- ~zz 8 8:::: ::::zlz ~;! ~
\ W Ou.lJ... ..:(!l(!l»>-XO: WxxX
64636261605956575655545352515049
P1S,
P14,
P13,
Pl2,
Pll,
Pl0,
P9,
Pe,
P7,
P6,
P5,
P4,
P3,
P2,
Pl,
Po,
48:::1 X12
47:::1 XlI
46:::1 Xl0
45:::1 X9
44:::1 X8
43::J X7
42::J X6
41:::1 Xs
40:::1 X4
39:::1 X3
36:::1 X2
37:::1 Xl
36::J Xo
35::JOR
34:::1 CLKL
33:::1 ClKY
F64-1
P3l
P30
P29
P28
P27
P26
P2s
P24
P23
P22
P2l
P20
P19
P18
P17
P16
e l .r:;~~~~:::~~::~~::lU;::L46:::1
c:2
47:::1
c:3
46:::1
e4
45:::1
e5
44:::1
1::6
43::J
1::7
42::1
e6
41:::1
c:9
40:::1
c:l0
39:::1
ell
36:::1
e12
37:::1
1::13
36::1
1::14
35::1
e15
34:::1
c:16
33:::1
17161920212223242526272629303132
17181920212223242526272829303132
~~~~~~~~>~~~~~~~
~~~~~~~~f~t£~~i&
~~~~~~~~>~~~~~~~
UUUUUUUUUUUUUUUU
UUUUUUUUUUUUUUUU
,,;
~ ,,'-N':';
a::: a::: a::: a::: a::: a:::
0..0..0..0..0..0..
Bllf.- o:.-(f-cr.-rt.,-rr.- rr.-i&'
2580 drw 06
64-LEAO FLATPACK
TOP. VIEW
1017216
64-lEAO FLATPACK
TOP VIEW
1iil..J~
1017217
(,) N
~
605956 57565554 535251 50494647464544
~4
FT 5
....EA
34
33
32
31
30
29
28
27
S
7
8
NC 9
ce~M
NC
Po, Yo
Pl,Yl
P2, Y2
P3, Y3
P4, Y4
Ps, Y5
Ps, Y5
P7, Y7
Pa, Y8
P9, Y9
Pl0, Yl0
Pl1,Yll
PI2, Y12
P13, Y13
P14, Y14
P15, Y15
Ilf.£ ('fC\f.,.:
Ilf.£
'" 65ns.
.
8.5
6
IDT7216L,IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (Vee = 5V ± 10%, TA = 0° to +70°C)
Symbol
7216L20
7217L20
Max.
Min.
Parameter
7216L25
7217L25
Min.
Max.
7216L35
7217L35
Min.
Max.
Unit
tMUC
Unclocked Multiply Timet 4)
2
30
2
38
2
55
ns
tMC
Clocked Multiply Time(4)
2
20
2
25
2
35
ns
ts
X, Y, RND Set-up Time
11
-
ns
1
-
12
X, Y, RND Hold Time
3
-
ns
tPWH
Clock Pulse Width High
-
10
-
10
-
10
tPOSEL
Clock Pulse Width Low
~to Product Out(4)
9
9
10
tPWL
-
12
tH
2
18
2
20
2
25
ns
tpop
Output Clock to p(4)
2
18
2
20
2
25
ns
2
tPOY
Output Clock to y(4)
2
18
2
20
tENA
-
18
ts
Clock Enable Set-up Time (IDT7217 only)
10
-
-
20
to IS
3-State Enable Time
3·State Enable Time(2)
10
tH
tHCL
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(lDT7216 onIyJ(1,3)
0
0
-
2
0
Symbol
18
7216L45
7217L45
Min.
Max.
Parameter
-
ns
ns
25
ns
25
ns
20
-
22
ns
-
10
ns
-
3
0
-
2
-
7216L55
7217L55
Min.
Max.
7216L65
7217L65
Max.
Min.
ns
ns
Unit
tMUC
Unclocked Multiply Time(4)
2
65
2
75
2
85
ns
tMC
Clocked Multiply Time(4)
2
45
2
55
2
65
ns
20
-
20
-
3
15
15
20
-
20
'-
ns
3
25
2
30
ns
ns
ts
X, Y, RND Set-up Time
15
tH
X, Y, RND Hold Time
3
tPWH
Clock Pulse Width High
15
tPWL
15
tpOSEL
Clock Pulse Width Low
~ to Product Out(4)
-
2
25
2
tpop
Output Clock to p(4)
2
25
2
30
2
30
tPOY
Output Clock to y(4)
2
25
2
30
2
30
ns
tENA
-
25
-
30
-
35
ns
tolS
3·State Enable Time
3-State Enable Time(2)
22
-
25
-
25
ns
ts
Clock Enable Set-up Time (IDT7217 only)
10
10
3
0
-
ns
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(lDT7216only)(1,3)
-
10
tH
tHCL
-
NOTES:
3
0
-
3
0
ns
ns
ns
ns
ns
2S80tb106
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
8.5
7
£I
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS MILITARY (Vee = 5V ± 10%, TA = -55° to + 125°C)
Symbol
tMUC
tMC
ts
tH
tPWH
tPWL
tpoSEL
tpop
tPOY
tENA
tOIS
ts
tH
tHCL.
Symbol
tMUC
tMC
ts
tH
tPWH
tPWL
tPOSEL
tPDP'
tPDY
, tENA
tOIS
ts
. tH
tHCL
7216L25
7217L25
Max.
Min.
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low'
~ to Product Out(4)
Output Clock to p(4)
Output Clock to y(4)
3~State Enable Time
3-State Enable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT72160nly)(1,3)
2
2
12
2
10
10
2
2
2
'
-
-
20
-
20
20
20
22
10
2
0
'-
-
-
7216L55
7217L55
Max.
Min.
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
~ to Product Out(4)
Output Clock to p(4)
Output Clock to y( 4)
3-81ate Enable Time
3-State Enable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT72160nly)(1,3)
NOTES:,
38
25
2
2
20
3
15
15
2
2
2
15
3
0
.
75
55
30
30
30
25
25
-
-
7216L30
7217L30
Min.
Max.
2
43
2
30
12
2
10
10
2
20
20
2
20
2
20
22
10
2
0
7216L40
7217L40
Max;
Min.
2
2
15
3
15
15
2
2
2
-
-
-
-
7216L65
7217L65
Min.
Max.
2.
85
65
2
25
3
15
15
35
2
-
2
2
-
15
3
0
~
-
-
12
3
0
-
-
7216L75
7217L75
Min.
Max.
2
2
25
3
15
15
2
95
75
2
2
35
35
40
25
30
30
35
25
-
-
15
3
0
.
-
25
25
25
25
25
-
-
60
40
35
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2580 tbl 07
1. To ensure that the correct product Is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not prodUction tested.
8.5
8
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ClKX
ClKY
INPUT X1, Y1,
RND
ClKM
ClKl
OUTPUTY
ClKM
ClKl
OUTPUTP
+--------------tMuc--------------~
2580 drw 13
Figure 4. IDT7216 TIming Diagram
I+----- tPWH-----..I
ClK
X1, Y1,
RND
II
OUTPUTY
OUTPUTP
~-------------tMUC------_+------~
2580 drw 14
Figure 5. IDT7217 TIming Diagram
8.5
9
~6
)C:j
BINARY POINT
=~
fxlS P<14 X13 X12 ~11 fxl0 X9 Xa X7 X6 Xs X4 X3 X2 Xl Xo
_2 0 2-1 2-2 2-3 2-4 2~ 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
~lS 1Y14 Y13 Y12 Yll 1Y1Q Y9
X
_2 0 2-1 2-2 2-3 2-4
P31
*=
Y7
Ya
Y6
Y5
Y4
Y2
Y3
Yo
Yl
2-6 2-7 2-8 2-9 2-10 2-1,1 2-12 2-13 2-14 2-15
2~
~r
SIGNAL
:u-
DIGITAL VALUE
r-..l
1!~
rl<)
m ....
SIGNAL
or
::
DIGITAL VALUE
::
c
g
P30 P29 P2a P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 Pll Pl0 P9
_2 0 2-1 2-2 2-3 2-4
P7
P6
Ps
P4
2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 _2 0 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26
2~
MSP
Ip31
Pa
P3
~-27
P2
Pl
Po
2-28 2-29 2-30
Pa
P9
P7
P6
r
DIGITAL VALUE
m
:u
en
WA=OI
LSP
Pao P29 P2a P27 P26 P25 P24 P23 P22 P21 P20 P19 Pla P17 P16 P15 P14 P13 P12 Pll Pl0
~
"'0
SIGNAL
P5
P4
P3
P2
Pl
Po
SI GNAL
1 0 2-1 12-212-312-412~ 12-612-712-812-912-1012-11 12- 12 ~-laI2-1412-1512-1612-17 ~-laI2-1912-20 12-2112-2212-2al~4 ~-251~6 ~-27 ~-2a ~-29 12-30 1 ~ GITAL VALUE
1_2 12
MSP
!FA = 1 1
LSP
Figure 6. Fractional Two's Complement Notation
2580 chv 16
00
<.n
BINARY POINT
P<15 X14 X13
z-s
Xa
X7
XS
X4
X3
r r
X2
t
Xl
::
r=
Xo
SIGNAL
Z16
DIGITAL VALUE
~
:u
~ ~ z-4
r
Y14 Y13 1Y12 Yll
Vl0
Y9
Ya
Y7
Z-1
~
z-s
~
2:7
~
~ izl0 12"11 iz-12
P31
P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 Pla P17 P1S P1S P14 P13 P12 Pll Pl0
1-2'1
~
~
z-4
~-6 Z-7 ~ ~ ~o
XS
Z-1
15
X
~12 Xll flo X9
11
Y6 Ys
jz-12
Y4
13
4 2-15
<
~
C
Y3
Y2
Yl
Yo
SIGNAL
g
~13
~14
2-15
Z16
DIGITAL VALUE
::
m
f'
::
:u
z-3 z-4
z-s
~
Z-7
z-8
~
Z10
Zll
Z-12 ~13 Z-14
2-15 2-16 2-17
Z-18
Z-19
Z20 -z-21 2-22
P9
P8
P7
Ps
Z23
2'24
~25
~
LSP
MSP
P5
P4
'L27 ~
P3
P2
12-29 ~
Pl
Po
z-31 z-32
o
;
SIGNAL
r
DIGITAL VALUE
!FA = 1
1
MANDATORY
Figure 7. Fractional Unsigned Magnitude Notation
....CI
2580drw17
-I
m
::
"'0
m
:u
~
:u
m
:u
>
zC)
m
a;6
BINARY POINT
)(:::1
~N
,,0)
O)~
~.r
SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE
:u-
~~
I'""N
m~
1'"" .....
(')1'""
;:
g
;:
c
~
"
SIGNAL
I'""
in
-31
!fA = , I
LSP
MSP
DIGITAL VALUE
~
MANDATORY
Figure 8. Fractional Mixed Mode Notation
2580drw 18
BINARY POINT
Oil
U.
X15 X14 X13 X12 XII Xl0 Xg X8 X7 X6 X5 X4
r-~5
X
214 213 212 211
210
t
2
8
27
~
5
2
~
Y15 V14 V13 Y12 VII Yl0 Vg V8 V7 V6 V5 Y4
r-215 214 2 13 212 211 2 10 2 G 2 8 27
26 2
5 24
X3
X2 Xl Xo
~
22
21
2
0
Y3 Y2 VI
Vo
2 3 22
21
2
0
SIGNAL
DIGITAL VALUE
SIGNAL
;:
DIGITAL VALUE
:u
P8
P7
P6
P5
P4
P3
P2
PI
Po
SIGNAL
21G
'ZS
27
~
Z;
t
t
'£-
21
0
2
DIGITAL VALUE
Po
SIGNAL
t
DIGITAL VALUE
~ 2!B
'f' 2!B f5 il" 2?3
f2~
fl
~8
217
216 215 -~ 214 213
212 211
10
2
t
LSP
MSP
LSP
-<
~
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 PIG P18 P17 P16 P15 P14 P13 P12 P11 Pl0 PG
-to
~
c
IFA=o I
8;:
a::
m
:u
~
IFA= 1 I
I'""
-4
~
"!B
~
Figure 9. Integer Two's Complement Notation
~
~
* In this format an overflow occurs In the attempted multiplication of the two's complement number 1,000 ••• 0 with 1,000.0 yielding an erroneous
product of -1 in the fraction case and --fO In the integer case.
II
2580drw lG
~
.:u
m
:u
zQ~
m
;;;6
)(:::J
:;~
-a 01
::a-
».r
BINARY POINT
»0
X,5 X,4 Xu X,2 ~11 X,0 X9
~5
X
2'4 2'3 2'2 2"
Y,5 jY14 Y,3 Y,2
,is
tv"
2'0
'if!
Y,o Y9
X8 X7 X6 X5 X4
X3
28
t
Y8
27
Y7
2'4 2'3 2'2 2'.' 2'0 29 2 8 2 J
'it
2
5
Y6 Y5
~
X2 X, Xo
22 2' 20
r-:::J
r-I\)
mr-""
or-
I
SIGNAL
I
DIGITAL VALUE
c
y,
Yo
SIGNAL
3 22
2'
20
DIGITAL VALUE
Y3
2 6 2 5 24
2
o
en
::
Y2
Y4
::
~
-a
C
m
::a
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P2' P20 P'9 P'8 P17 P'6 P'5 P'4 P'3 P'2 P" P'0 P9 - P8
~1 ~
'2:0 2'9 12'8 217 2'6 2'5 2'4, 2'3 2'2 2" 2'0
t
f9 i 8 ,£-7 t£-6 is ~4 i 3 f2
~
t
MSB
en
P7
P6
P5
P4
P3
P2
P,
Po
SIGNAL.
'Z
6
2
2
5
Z
t
22
2'
~
DIGITAL VALUE
I FA;; 1 I
LSP
MANDATORY
Figure 10. Integer Unsigned Magnitude Notation
2580 drw 20
0)
en
BINARY POINT
SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE
SIGNAL
J---+--f--+-I---+--f--+---II--+--f--+~I--f--+---I---II (UNSIGN ED MAGN ITUDE)
DIGITAL VALUE
::
r=
~
~
~
o
8
::
::
m
::a
o
SIGNAL
DIGITAL VALUE
LSP
MSB
Figure 11. Integer Mixed Mode Notation
I\)
>
r-I
m
::
-a
I FA= 1 I
m
MANDATORY
2580aw21
::a
~
::a
m
::a
»
z
C)
rn
IDTI216L, IDTI217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Rgure 1
Output Load
2580 tbl 08
SWITCH POSITION
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
2580 tbl 09
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Figure 1. AC Test Load Circuit
Vee
ESD
PROTECTiON
IIH
INPUTS
J
-..
0
IlL +- R
Figure 2. Input Interface Circuit
\!H
OUTPUTS
t:L
Figure 3. Output Interface Circuit
II
8.5
13
(;)~
16-81T CMOS
CASCADA8LE ALU
IDT7381
IDT7383
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT7381 and IDT7383 are high-speed cascadable
Arithmetic Logic Unit (ALUs). Both three-bus devices have
two input registers, ultra-fast 16-bit ALUs and 16-bit output
registers. With IDT's high-performance CEMOS technology,
the IDT738117383 can do arithmetic or logic operations in
20ns. The IDT7381 functionally replaces four 54/74S381
four-bit ALUs in a 68-pin package.
The two input operands, A and B, can be clocked or fed
through for flexible pipelining. The F output can also be set
into clocked or flow-through mode. An output enable is
provided for three-state control of the output port on a bus.
The IDT7381 has three function pins to select 1 of 8
arithmetic or logic operations. The two Rand S selection pins
determine whether A, B, ForO are fed intotheALU. ThisALU
has carry-out, propagate and generate outputs for cascading
using carry look-ahead.
The IDT7383 has five function pins to select 1 of 32
arithmetic or logic operations. This ALU has a carry-out pin for
cascading.
The IDT7381 and IDT7383 are available in 68-pin PLCC or
PGA packages. Military grade product is manufactured in
compliant with the latest revision of MIL-STD-883, Class B, for
high reliability systems.
•
•
•
•
•
•
•
•
•
High-performance 16-bit Arithmetic Logic Unit (ALU)
20ns to 55ns clocked ALU operations
Ideal for radar, sonar or image processing applications
IDT7381:
.
- 54174S381 instruction set (8 functions)
- Replaces Gould S614381 or Logic Devices L4C381
- Cascadable with or without carry look-ahead
IDT7383:
- 32 advanced ALU functions
- Cascadable without carry look-ahead
Pipeline or flow-through modes
Internal feedback path for accumulation
Three-state outputs
TTL-compatible
Produced with advanced submicron CEMOSTM highperformance technology
Available in 68-lead PGA, 68-pin surface mount PLCC
and 68 pin fine-pitch Flatpack (7383 only)
Military product compliant to MIL-STD-883, Class B
Speeds available:
Commercial: L20/25/30/40/55
Military:
L25/30/35/45/65
FUNCTIONAL BLOCK DIAGRAM
AO-IS
10T7381
AO-IS
BO-IS
10T7383
BO-IS
ENB
L----9~~~~l== ClK
ClK
EFm
14--+.--
FTAB
FTAB
RSO-l
2
~4---~--~----~--'
G
~+--+~-
C16----~
OVF----~
Z ~-~'-----____,r__....J
N
10-2
CIS
OVF
Co
Z
~-------~I
: _______·r
~16
FO-IS
ENF
FTF
GND
Vee
OE
Ff,X I
GND
Vec
16
2525 drw 01
FO-IS
CEMOS is a trademarl< of Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0
0
Indicates the carry propagate output state to the AlU.
RSo- RS1
G
Indicates the carry generate output state to the AlU.
2525 tbl 02
IDT7383 PINS
Pin Name
1/0
Description
10-14
I
Five control pins to select the AlU function performed.
N
0
The sign bit of an AlU operation.
2525tbl05
IDT7381 ALU FUNCTION TABLE
IDT7381 RAND S MUX TABLE
RS1
RSo
R Mux
S Mux
12
h
10
0
0
A
F
0
0
0
F=O
0
1
A
0
0
0
1
F = R + S + Co
1
0
0
8
0
1
0
F=R+S+Co
1
1
A
8
0
1
1
F = R + S + Co
1
0
0
F = R xor S
1
0
1
F = R orS
1
1
0
F = Rand S
1
1
1
F = all1's
2525 tbl 03
Function
2525 tbl 04
8.6
5
1017381, 1017383
16-BIT CMOS CASCAOABLE ALU
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
IOT7383 ALU FUNCTION TABLE
14
13
12
11
10
Function
0
0
0
0
0
F=A+B+Co
0
0
0
0
1
F =A or B
0
0
0
1
0
F=A+ S+ CO
0
0
0
1
1
F=A+B+Co
0
0
1
0
0
F =A + Co
0
0
1
0
1
F =A or F
0
0
1
1
0
F=A-1 +Co
0
0
1
1
1
F =A-+ Co
0
1
0
0
0
F=A+ F+Co
0
1
0
0
1
F =A or F
0
1
0
1
0
F=A+'F+Co
0
1
0
1
1
F=A+F+Co
0
1
1
0
0
F=F+B+Co
0
1
1
0
1
F =A or B
0
1
1
1
0
F=F+S+Co'
'Symbol
Rating
Com'l.
Mil.
Unit
VTERM
Terminal Voltage
with Respect
to Ground
Power Supply
Voltage
-0.5 to
Vee + 0.5
-0.5 to
Vee + 0.5
V
Vee
TA
Operating
Temperature
TBIAS
TSTG
-0.5 to +7.0 -0.5 to +7.0
o to +70
V
-55 to +125
°C
Temperature
Under Bias
-55 to +125 -65 to +135
°C
Storage
Temperature
-55 to +125 -65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
2525 tbl 07
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. Under no
circumstances should an input of an 110 Pin be greater than Vcc O.SV.
0
1
1
1
1
F='F+B+Co
1
0
0
0
0
F =A xorB
1
0
0
0
1
F =A and B
1
0
0
1
0
F =Aand B
1
0
0
1
1
F =A xnor B
1
0
1
0
0
F =A xor F
Typ.
Unit
1
0
1
0
1
F =A and F
CIN
Input Capacitance
VIN =OV
10
pF
1
0
1
1
0
F =A and F
COUT
Output Capacitance
VOUT= OV
12
pF
1
0
1
1
1
F = all1's + Co
1
1
0
0
0
F=B+Co
1
1
0
0
1
F =A andS
1
1
0
1
0
F=S+Co
1
1
0
1
1
F=B-1 +Co
1
1
1
0
0
F=F+Co
1
1
1
0
1
F =A orS
1
1
1
1
0
F=F-1+Co
1
1
1
1
1
F=F+Co
+
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
NOTE:
2525 tbl 09
1. This parameter is sampled at initial characterization and Is not production
tested.
2525 tbl 06
II
8.6
6
IDT73S1,IDT73S3
16-BIT CMOS CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
= O°C to +70°C, Vcc = 5.0V ± 5%; Military:
TA = -55°C to +125°C, Vec
Commercial: TA
= 5.0V +- 10%
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
O.S
V
IIH
Input HIGH Current
Vee .. Max., VIN .. 2.7V
-
-
10
j.t.A
-10
j.t.A
-100
rnA
-0.1
-20
j.t.A
-0.1
20
Symbol
Test Condltlons(1)
Parameter
IlL
Input LOW Current
Vee = Max., VIN = 0.5V
losl~)
Short Circuit Current
Vee = Max., VOUT = GND
loz
Off State (High Impedance)
Vcc= Max.
Output HIGH Voltage
Vee= Min.
VIN
VOL
Output LOW Voltage
-
IOH =-4mA
2.4
-
-
V
IOL =4mA MIL.
-
-
0.5
V
=VIH or VIL
Vee= Min.
VIN
Vo= 2.7V
Va .. 0.5V
Output Current
VOH
-20
=VIH or VIL
IOL = SmA COM'L.
NOTES:
2525tbl08
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee .. 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
POWER SUPPLV CHARACTERISTICS
C ommercla:
. I T A .. 0° C to +7 0° C , V CC= 5 .0 V ±5%; MT
Iitary:
TA =-5 5° C to + 125°C
Test Condltlons(1)
Symbol
lecoe
Parameter
Quiescent Power Supply Current
Vcc .. Max.
COM'L.
VIN .. OV or Vcc
MIL.
lecoT(3)
Quiescent Power Supply Current
Vcc
=Max.
COM'l.
TIL Inputs HIGH
VIN
= 3.4V
MIL.
Dynamic Power Supply Current
Mode: FTAB = FTF = 1
Vec .. Max.
Outputs Disabled
fi = 10MHz
50% Duty Cycle
VIL = OV, VIH = Vee
lecD1
lecD2
Dynamic Power Supply Current
Mode: FTAB =FTF = 1
Vee =Max.
Outputs Disabled
fi =20MHz
50% Duty Cycle
VIL = OV, VIH = Vee
I
V CC= 50V ± 10 0 0
Typ.(2)
Min.
-
2
Max.
10
2
15
0.5
2
0.5
2.5
COM'L.
-
10
35
MIL.
-
10
55
COM'L.
-
30
60
MIL.
-
30
SO
NOTES:
1.
2.
3.
4.
5.
6.
Unit
rnA
rnA
rnA
rnA
2525tbl10
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vee = 5.0V, +25°C ambient.
Per TTL driven input (VIN = 3.4V); all other inputs at Vce or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = laulEscENT + liN PUTS + IDYNAMle
Ic .. Icc + ~Icc DHNT + ICCD (fep/2 + fiNi)
Icc .. Quiescent Current
lliec .. Power Supply Current for a TTL High Input (V IN = 3.4V)
DH .. Duty Cycle for TTL Inputs High
NT- Number of TTL Inputs at DH
ICCD .. Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fcp .. Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi .. Input Frequency
Ni .. Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
8.6
7
IDT7381,IDT7383
16-BIT CMOS CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL (Vee = 5V ± 5%, TA = OOG to +70°C)
Maximum Combinational Propagation Delays
From Input
FTAS
IDT7381L20
IDT7383L20
F0-15 P,G,N Z,OVF
ClK
11
20
-
-
-
18
20
18
20
20
Ao-A15, 80-815
ClK
10-4, RSo, RSl
Co
10-4, RSo, RSl (1)
20
14
20
20
14
18
13
22
-
-
18
20
14
20
20
14
18
27
22
22
-
16
20
17
11
-
-
-
14
20
14
18
20
14
20
17
14
18
26
22
22
-
-
Unit
30
20
28
28
20
28
ns
ns
ns
28
20
28
ns
ns
ns
26
16
22
22
16
22
20
28
-
-
22
26
16
22
22
16
22
33
28
28
28
30
20
28
-
18
25
22
-
24
30
28
13
-
-
-
19
-
-
-
-
-
16
22
-
22
16
22
-
-
-
28
20
28
20
28
ns
ns
ns
ns
25
16
22
22
16
22
32
28
28
24
30
20
28
28
20
28
ns
ns
ns
22
28
22
-
28
-
=1, FTF =0
Co
-
-
10-4, RSo, RSl (1)
-
18
20
18
20
16
FTAS
C16
=0, FTF =1
ClK
FTAS
C16
IDT7381L30
IDT7383L30
F0-15 P,G,N Z,OVF
=0, FTF =0
Co
FTAS
C16
IDT7381L25
IDT7383L25
F0-15 P,G,N Z,OVF
=1, FTF =1
Ao-A15, 80-815
Co
10-4, RSo, RSl (1)
18
18
22
28
NOTE:
1. Minimum propagation delays are guaranteed to be greater than or equal to 3ns although not production tested.
2525 tb 11
Maximum Combinational Propagation Delays
IDT7381L40
IDT7383L40
P,G,N Z,OVF
IDT7381L55
IDT7383L55
'f5,G,N Z,OVF
C16
F0-1!5
32
20
35
32
38
-
-
32
44
28
34
46
30
40
30
44
32
32
20
35
56
37
55
38
28
34
Ao-A15, 80-815
-
30
40
32
ClK
26
-
-
Co
-
-
10-4, RSo, RSl (1)
-
32
28
34
20
35
-
40
30
40
30
40
28
34
32
20
35
55
37
55
From Input
FT AS
F0-1!5
C16
Unit
53
34
42
36
22
42
ns
36
22
42
ns
42
53
34
42
-
36
46
37
ns
32
-
-
-
ns
34
42
22
ns
42
ns
46
34
42
37
22
42
ns
=0, FTF =0
ClK
26
30
Co
-
-
10-4, RSo, RS1
=
=
42
ns
ns
FTAS 0, FTF 1
ClK
Co
10-4, RSo, RSl (1)
FTAS
FT AS
-
ns
ns
=1, FTF =0
42
=1, FTF =1
Ao-A15,80-815
Co
10-4, RSo, RSl (1)
32
36
42
NOTE:
1. Minimum propagation delays are guaranteed to be greater than or equal to 3ns although not production tested.
8.6
ns
ns
2525tb 12
8
1017381, 1017383
16-BIT CMOS CASCAOABLE ALU
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL (Vcc = 5V ± 5%, TA ... O°C to +70°C)- (Cont'd.)
Minimum Set-up and Hold Times Relative to Clock (CLK)
IDT7381L20
IDT7383L20
Input
Set-up
Hold
IDT7381L25
IDT7383L25
Set-up
Hold
IDT7381L30
IDT7383L30
Set-up
Hold
IDT7381L40
IDT7383L40
Set-up
Hold
IDT7381L55
IDT7383L55
Set-up
Hold
Unit
FTAB = 0, FTF = X
5
0
6
0
6
0
6
0
8
0
ns
Co (2)
12
0
16
0
16
0
16
0
21
0
ns
10--4, RSo, RS1 (1) (2)
15
0
24
0
29
0
32
0
44
0
ns
5
0
6
0
6
0
6
0
8
0
ns
Ao-A15,80-815
OO,ENB,~
FTAB = 1, FTF =0
Ao-A15, 80-815
14
0
16
0
25
0
28
0
35
0
ns
Co
12
0
16
0
16
0
16
0
21
0
ns
10--4, RSo, RS1 (1)
15
0
24
0
29
0
32
0
44
0
ns
5
0
6
0
6
0
6
0
8
0
ENF
ns
25251bl13
Minimum Clock Cycle Times and Pulse Widths
IDT7381L20
IDT7383L20
IDT7381L25
IDT7383L25
IDT7381L30
IDT7383L30
IDT7381L40
IDT7383L40
IDT7381L55
IDT7383L55
Unit
Clock LOW Time
5
6
8
10
14
ns
Clock HIGH Time
5
6
8
10
14
ns
18
20
25
34
43
ns
Parameter
Clock Period
2525tbl14
Maximum Output Enable/Disable Times
IDT7381L20
IDT7383L20
IDT7381L25
. IDT7383L25
IDT7381L30
IDT7383L30
IDT7381L40
IDT7383L40
IDT7381L55
IDT7383L55
Enable Time
8
10
15
18
20
ns
Disable Time
8
10
15
18
20
ns
Parameter
NOTES:
1. For IDT7381 , pins 10 -12, RSo, RSl apply. For IDT7383, pins 10 -14 apply.
2. Only for FTF - O.
8.6
Unit
2525tbl15
9
1017381,1017383
16·81T CMOS CASCADA8LE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - MILITARY (Vcc = 5V ± 10%, TA = .:...55°C to +125°C)
Maximum Combinational Propagation Delays
FTAB
From Input
0, FTF 0
=
IDT7381L25
IDT7383L25
F0-15 P,G,N Z,OVF
C16
F0-15
IDT7381L35
IDT7383L35
P,G,N Z,OVF C16
Unit
=
ClK
14
Co
-
10-4, RSo, RSl (1)
FT AB
C16
IDT7381L30
IDT7383L30
F0-15 P,G,N Z,OVF
24
22
24
18
24
24
18
22
26
28
-
-
24
24
18
22
28
27
32
22
28
-
-
28
34
22
28
34
26
30
28
28
34
22
28
28
22
28
45
30
40
32
45
30
34
32
23
34
ns
32
23
34
ns
34
40
30
34
ns
ns
34
ns
ns
=0, FTF =1
25
21
25
22
24
18
24
Ao-A15, 80-815
-
20
25
22
-
28
28
28
-
30
35
32
ClK
14
-
-
26
-
-
-
27
-
-
-
ns
Co
-
-
18
24
18
22
-
22
28
-
30
34
23
34
ns
28
22
28
-
.-
-
25
18
24
22
18
22
30
26
30
28
28
22
28
28
22
28
40
30
40
30
30
34
32
23
34
ClK
Co
10-4, RSo, RSl (1)
FTAS
-
ns
=1, FTF =0
10-4,· RSo, RSl (1)
FTAB
-
22
34
ns
=1, FTF =1
Ao-A15, 80-815
Co
10-4, RSo, RSl (1)
25
21
25
22
22
28
30
34
NOTE:
ns
ns
ns
25251b 16
1. Minimum propagation delays are guaranteed to be greater than or equal to 3ns although not production tested.
Maximum Combinational Propagation Delays
FTAB
From Input
0, FTF 0
=
F0-15
IDT7381L45
IDT7383L45
P,G,N
Z,OVF
28
34
Co
-
-
10-4, RSo, RSl (1)
C16
Unit
63
42
48
45
25
48
ns
38
45
25
48
ns
ns
50
32
38
34
23
38
37
44
-
-
-
48
34
23
38
68
42
66
44
48
63
42
48
ns
ns
=0, FTF =1
ClK
Co
10-4, RSo, RSl (1)
FTAB
F0-15
=
ClK
FTAB
C16
IDT7381L65
IDT7383L65
P,G,N
Z,OVF
56
32
46
34
38
50
32
38
-
-
ns
ns
=1, FTF =0
Ao-A15,80-815
-
32
46
36
-
44
56
44
ClK
28
-
-
37
-
ns
-
32
38
23
38
-
-
-
Co
-
48
25
48
ns
-
42
48
46
32
38
36
23
38
65
42
66
44
56
42
48
44
25
48
ns
10-4, RSo, RSl (1)
FTAB
38
=1, FTF =1
Ao-A15,80-815
Co
10-4, RSo, RSl (1)
45
32
46
32
38
48
NOTE:
ns
ns
ns
25251b 17
1. Minimum propagation delays are guaranteed to be greater than or equal to 3ns although not production tested.
8.6
10
10T7381,10T7383
16-BIT CMOS CASCAOABLE ALU
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - MILITARY (Vee = sv ± 10%, TA - -SsoC to +12S0C) - (Cont'd)
Minimum Set-up and Hold Times Relative to Clock (CLK)
IDT7381L25
IDT7383L25
Input
Hold
Set-up
IDT7381L30
IDT7383L30
Set-up
Hold
IDT7381L35
IDT7383L35
Set-up
Hold
IDT7381L45
IDT7383L45
Set-up
Hold
IDT7381L65
IDT7383L65
Set-up
Hold
Unit
FTAB = 0, FTF = X
Arr-A15, 80-815
Co (2)
7
0
8
0
8
0
8
0
10
0
ns
14
0
18
0
19
0
20
0
25
0
ns
10-4, RSo, RS1 (1) (2)
19
0
30
0
32
0
36
0
50
0
ns
7
0
8
0
8
0
8
0
10
O·
ns
Arr-A15, 80-815
14
0
27
0
30
0
33
0
43
0
ns
Co
14
0
18
0
19
0
20
0
25
0
ns
10-4, RSo, RS1 (1)
19
0
30
0
34
0
36
0
50
0
ns
7
0
8
0
8
0
8
0
10
0
ENA,ENB,mF
FTAB = 1, FTF =0
ENF
ns
2525tbl18
Minimum Clock Cycle Times and Pulse Widths
Parameter
Clock LOW Time
Clock HIGH Time
Clock Period
IDT7381L25
IDT7383L25
IDT7381L30
IDT7383L30
IDT7381L35
IDT7383L35
IDT7381L45
IDT7383L45
IDT7381L65
IDT7383L65
8
12
13
15
20
. ns
ns
8
12
13
15
20
20
26
30
38
52
Unit
ns
2525tbl19
Maximum Output Enable/Disable Times
Parameter
Enable Time
Disable Time
IDT7381L25
IDT7383L25
IDT7381L30
IDT7383L30
IDT7381L35
IDT7383L35
IDT7381L45
IDT7383L45
IDT7381L65
IDT7383L65
Unit
14
18
19
20
22
ns
.. 18
19
20
22
14
NOTES:
. 1. For 10T7381, pins 10 -12, RSo, RS1 apply. For 10T7383, pins 10 -14 apply.
. 2. Only for FTF - O.
8.6
ns
2525 tbl 20
11
IDT7381,IDT7383
16-BIT CMOS CASCADABLE ALU
WAVEFORMS FOR FTAB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
=0, FTF =X
T2
T1
ClK
--Y
' . . .-'--'1
Set-up :
AO·15
' . . ._'--'y
Hold
DATA 1
80-15
Co
10-4,
RS0-1
ERA,""Efm
ENF
DATA 1
OE
F0-15
(FTF
=0)
F0-15
(FTF
=1)
lS, G
Z,OVF
II
Result
C16
2525drw 07
Prop. 1: Propagation delay with respect to the eLK
Prop. 2: Propagation delay with respect to b-4, RS0-2.
Prop. 3: Propagation delay with respect to OJ.
8.6
12
IDTI381, IDTI383
16-BIT CMOS CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORMS FOR FTAB
=1, FTF =X
T2
T1
yr----...'___..IY.,
ClK
(FTF
=0) ----"-
- Set-up
Hold
''-----'1
AO-15
DATA 1
80-15
Set-up
co
DATA 1
DATA 3
DATA21
Set-up
10-4,
DATA 1
DATA 2
DATA 3
RSO-1
ENF"
DATA 1
FO-15
(FTF = 0)
Prop. 2
FO-15
(FTF = 1)
P, G
Result
Result
Z,OVF
C16
Result
2525drW 08
Prop. 1:
Prop. 2:
Prop. 3:
Prop. 4:
Propagation delay with respect to the eLK.
Propagation delay with respect to b-4, RS0-2.
Propagation delay with respect to 01.
Propagation delay with respect to A, B.
8.6
13
10T7381,10T7383
16·BIT CMOS CASCAOABLE ALU
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
PROPAGATION DELAY CALCULATIONS FOR TWO IOT7381/73835
To Output
From Input
=
FTAB 0, FTF
ClK
Co
10-4, RSO-1 (1)
=0
As in 16·bit case
....
....
....
....
AO-15,80-15
ENA, EN8,ENF
=
=
FTAB 1, FTF 0
ClK
As in 16·bit case
Co
10-4, RSO-1 (1)
....
AO-15,80-15
....
ENA, ENB,ENF
....
'0
=
(Clk -? C16) + (Co -? flag)
(Co -? C16) + (Co -? flag)
(10-4, RS0-1 -? C16) + (Co -? flag)
. ...
....
=
FTAB 0, FTF 1
ClK
(Clk -? C16) + (Co -? Fo-15)
Co
(Co -? C16) + (Co -? Fo-15)
10-4, RSO-1 (1)
(10-4, RS0-1 -? C16)+ (Co -? Fo-15)
AO-15,80-15
....
ENA, EN8,ENF
.. ..
=
To Set PUT Time
Flags (2)
FO-15
••
(Clk -? C16) + (Co -? flag)
(Co -? C16) + (Co -? flag)
(10-4, RS0-1 -? C16) + (Co -? flag)
. ...
....
....
(Co -? C16) + (Co set-up time)
(10-4, RS0-1 -? C16) + (Co set-up time)
As in 16·bit case
As in 16·bit case
....
(Co -? C16) + (Co set-up time)
(10-4, RSO-1 -? C16) + (Co set-up time)
As in 16·bit case
As in 16·bit case
....
....
(Co -? C16) + (Co -? flag)
(10-4, RS0-1 -? C16) + (Co -? flag)
(Ao-15, 80-15 -? C16) + (Co -? flag)
(Co -? C16) + (Co set-up time)
(10-4, RS0-1 -? C16) + (Cq set-up time)
As in 16·bit case
As in 16·bit case
. ...
=
FTAB 0, FTF 1
Don't care condition
ClK
Co
(Co -? C16) + (Co -? FO-15)
10-4, RSO-1 (1)
(10-4, RSo-1 -? C16) + (Co -? Fo-15)
AO-15,80-15
(Ao-15, 80-15 -? C16) + (Co -? FO-15)
ENA, EN8,ENF
....
Relative to Clock (ClK)
Don't care condition
(Co -? C16) + (Co -? flag)
(10-4, RS0-1 -? C16) + (Co -? flag)
(Ao-15, 80-15 -? C16) + (Co -? flag)
....
NOTES:
1. For IDT7381, pins 10-2, RS0-2 apply. For IDT7383, pins 10-4 apply.
2. Flags are 15", G, OVF, Z, C16 for IDT7381. Flags are N, OVF, Z C16 for IDT7383.
....
.....
....
....
....
2525 Ibl 22
II
8.6
14
10T7381, 10T7383
16·BIT CMOS CASCAOABLE ALU
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
CASCADING THE IDT7381/3
Some applications require 32-bit or wider input operands.
Cascading is the hardware solution. It provides a high speed
alternative in handling more than 16-bit wide operands.
This section is divided in three parts:
1. Cascading the IDT7381
2. Cascading the IDT7383
3. Time delay considerations
3. Time Delay Considerations
Once cascading has taken place, time delays may become
critical in high performance systems. Our main interest here
is focused on "propagation delays", i.e. calculating the time
required for an input signal to propagate through several
cascaded devices up to a specific output in another device
within the cascaded system.
1. Cascading the IDT7381
. Cascading to 32-bitwide operands takes only two IDT7381 s
and no external hardware. However, cascading to data widths
greater than 32-bit can be done in two ways: without external
hardware (slow method) or by using a carry look ahead
generator like FCT182 (fast method).
a) Cascading the IDT7381 without a carry-look-ahead
generator: (Figures 2 and 3)
1. Connect the C16 output of the least significant device
into the Co input of the next most significant device.
. 2. Common lines to all devices are: RS0-1, 10-2, Clk, FTF,
FTAS, ENA, ENS, ENF.
3. TakeOVF, C16, P, G of the most significant device as
valid.
4. The system's zero flag (Z) is obtained by ANDing all
zero flag results.
b) Cascading three or more IDT7381s with carry-Iookahead (CLA) generator: (Figure 4)
1. Connect the P and G outputs of each device to the
CLA generator's corresponding inputs.
2. Take the CLA generator outputs into the Co inputs of
each device (except for the least significant one).
3. Common linestoall devices are: RS0-1, 10-2, Clk, FTF,
FTAS, ENA, ENS, ENF.
4. TakeOVF, C16, P, G of the most significant device as
valid.
5. Carry-in to the system should be connected to the Co
input of the least significant device and also to the
CLA generator.
.
Propagation Delay
The propagation delay for two devices between the input
and output of interest (input to output delay) is done as follows:
1. Calculate delay between the input and C16 in the first
device.
2. Calculate delay between Co and the output in the
second device.
3. Add both results.
The following table is an example on how to build a
propagation delay table for all inputs in a 32-bit IDT7381/3
cascaded system .
Propagation delay calculations can be extended to ncascaded devices as the sum of the delays in all devices
between the input and output of interest. That is:
(Input)1 --t (C16)1 = t1
2. Cascading the IDT7383
(Figures 5 and 6)
1. Connect the C16 output of the least significant device
into the Co input of the next most significant device.
2. Common linesto all devices are: 10-4, Clk, FTF, FTAS,
ENA, ENS, ENF.
3. Take OVF, C16, N of the most significant device as
valid.
4. The system's zero flag (Z) is obtained by ANDing all
zero flag results.
8.6
(CO)i --t (C16)i = ti
(CO)i + 1 --t (C16)1 + 1= ti + 1
(Co)n --t(Output)n = tn
Where the subscript i denotes the device number and the
arrow (--t) represents the delay in between. Notice that i + 1
is the immediate upper device from device i. Adding the
delays tl we get:
Propagation delay = t1 + t2 + ... + ti + ti + 1+ ... + tn
Total Delay
As seen from Figure 11 , the propagation delay is within the
IDT7381/3 devices only. A complete analysis should also
include the delay associated with the transmission line Li
(which depends on the line length and its impedance). This
line delay should then be added to the propagation delay to
obtain the total delay for the cascaded system:
Total delay = Propagation delay + Transmission line delay
15
IDT7381,IDT7383
16-BIT CMOS CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be
taken into account when testing high-speed CMOS devices in
an automatic environment. These are:
1) Proper decoupling at the test head is necessary.
Placement of the capacitor set and the value of capacitors
used is critical in reducing the potential erroneous failures
resulting from large Vcc current changes. Capacitor lead
length must beshort and as closetothe DUTpowerpinsas
possible.
2) All input pins should be connected to a voltage potential
during testing. If left floating, the device may begin to
oscillate causing improper device operation and possible
latchup.
3) Definition of input levels is very important. Since many
inputs may change coincidentally, significant noise at the
device pins may cause the VIL and VIH levels not to be met
until the noise has settled. To allow for this testing/board
induced noise, I Dr recommends using VIL $ OV and VIH ~
3V for AC tests.
4) Device grounding is extremely important for proper device
testing. The use of multi-layer performance boards with
radial decoupling· between power and ground planes is
required. The ground plane must be sustained from the
performance board to the DUT interface board. All unused
interconnect pins must be properly connected to the ground
pin. Heavy gauge stranded wire should be used for power
wiring and twisted pairs are recommended to minimize
inductance.
TEST LOAD CIRCUIT
2525 drw 09
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL
= Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 1. AC Test Load Circuit
AC TEST CONDITIONS
GNDto3.0V
Test
Input Rise/Fall Times
Wins
Disable Low
Input Timing Reference Levels
1.5V
Enable Low
Output Reference Levels
1.5V
All other Outputs
Input Pulse Levels
Output Load
Switch
Closed
II
Open
See Rgure 1
2525tbl23
2525 tbl21
8.6
16
1017381, 10T7383
16-BIT CMOS CASCAOABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Al6-31
816-31
Ao-15
80-15
~"'----I
11 RS F REG
I
I
H>GREGJ
I
,
MUX
OE
10-13
f
~EREG
L--.....t>OREG
SEL 0-SEL2~1
00-015
16
CONTROL
LOGIC
~t I
,
MUX
II
I
"-t> H REG I
~
I
POWER
SUPPLY
~GND
\--Vee
POWER
SUPPLY
10-13
YO-Y15
,GNO
!- Vee
CEN
2562 drw 01
2562drw02
10T73200
10T73201
eEMOS is a trademark 01 Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
->- >- >-
~
L...JL-JL-JL-JL-JL....JIIL....JL....JL....JL....JL-JL..J
7 6 5 4 3 2 I I 52 51 50 49 48 47
]
]
]
]
]
]
]
]
a
9
10
11
12
13
14
15
03
04
05
06
07
GNO
Vee
08
09
] 16
010
]17
011
012
] 18
] 19
] 20
NC
"
L.J
4S[
45[
44[
43[
42[
41 [
40[
39[
3a[
37[
36[
35[
34[
1
J52 -1
~ ~~ ~~ ~~ ~~ ~O~ ~~.
NC
GNO
Y4
Y5
Y6
Y7
Vee
GNO
Ya
Y9
Y1Q
Y11
GNO
~
C')~Lt)C\I~o::::c::::iaLt)~C')C\lO
~~~-I-I-I-IO~~~~
OOO~~~O
>->->->-2
2562 drw03b
PLCC
TOP VIEW
2562 drw 03a
PIN DESCRIPTIONS
110
Pin Name
Description
00- 015
I
Sixteen-bit data input port.
Yo- Y15
0
Sixteen-bit data output port.
10-:-13
SElo-SEl2
I
Four control pins to select the register operation performed.
I
Three control pins to select the register appearing at the output.
ClK
I
Clock input.
crf\J
I
Clock enable control pin. When this pin is low, the instruction 10-13 is performed on the registers.
When high, no register operation occurs.
'O'E
I
Output enable control pin. When this pin is high, the output port V is in a high impedance state.
When low, the output port Y is active.
Vee
Power supply pin, 5V.
GNO
Ground pins,
av.
2562tbl01
IDT732000UTPUT SELECTION
IDT73201 OUTPUT SELECTION
SEL2
SEL1
SELo
Y Output
SEL2
SEL1
SELo
Y Output
0
0
a
A-+YO-V15
0
a
A -+ YO-Y15
0
a
1
B -+ Vo- Y15
a
a
0
1
B -+ Yo- Y15
0
1
0
C -+ VO-V15
0
1
0
C -+ VO-V15
a
1
1
0-+ YO-V15
0
1
1
0-+ Yo-V15
1
0
a
E -+ VO-V15
0
a
E -+ Yo- V15
1
a
1
F -+ Vo- Y15
1
1
0
1
F -+ Yo- Y15
1
1
a
G -+ YO-Y15
1
1
a
G -+ Yo- Y15
1
1
1
H -+ Vo- Y15
1
1
1
2~t>i!tDI U~
U
DO-015-+Yo-Y15
2562tbl03
2
10T73200, 10T73201
16·BITCMOS MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT73200 INSTRUCTION TABLE
13
12
11
10
0
0
0
0
LOA
00- 015-+A
0
0
0
1
L08
00-015-+8
1
0
0
1
0
LOC
Do - 015 -+ C
1
0
0
1
1
LOO
lJO- 1.)15 -+
1
0
1
0
0
LOE
00- 015-+ E
1
0
1
0
LOF
00- 015 -+ F
1
0
1
1
1
0
LOG
00- 015 -+ G
1
0
1
1
1
LOH
00-015-+H
1
Mnemonic
Function
Pipeline Levels
1
I.)
1
0
0
0
LSHAH
Do - 015 -+ A -+ 8 -+ C -+ 0 -+ E -+ F -+ G -+ H
8
1
1
0
0
LSHAO
Do - 015 -+ A -+ 8 -+ C -+ 0
0
1
1
0
LSHEH
Do - 015 -+ E -+ F -+ G -+ H
4
4
1
0
1
1
LSHA8
00-015-+A-+8
1
1
0
0
LSHCO
Do - 015 -+ C -+ 0
1
1
0
1
LSHEF
00-015-+E-+F
1
1
1
0
LSHGH
00-015-+ G -+ H
2
1
1
1
1
HOLD
Hold All Registers
-
2
2
2
2562tbl04
IOT732011NSTRUCTION TABLE
13
12
11
10
0
0
0
0
LOA
00- 015-+A
1
0
0
0
L08
00-015-+8
1
0
0
1
1
0
LOC
00- 015 -+ C
0
0
1
LOO
00- 015 -+ 0
0
1
0
1
0
LOE
00-015-+ E
1
1
1
0
1
0
LOF
00- 015 -+ F
1
0
1
1
1
0
LOG
00- 015 -+ G
0
1
1
1
HOLD
Hold All Registers
-
1
0
0
0
LSHAG
Do - 015 -+ A -+ 8 -+ C -+ 0 -+ E -+ F -+ G
1
0
0
1
LSHAO
00- 015-+A -+ 8 -+ C-+ 0
7
4
1
0
1
0
LSHEG
Do - 015 -+ E -+ F -+ G
3
1
0
1
LSHA8
00-015-+A-+8
1
0
LSHCO
00- 015 -+ C -+ 0
1
1
1
1
0
0
1
LSHEF
00-015-+E-+F
1
1
1
0
LOG
00- 015 -+ G
2
2
2
1
1
1
1
1
HOLD
Hold All Registers
-
Mnemonic
Function
Pipeline Levels
1
2562tbl05
8.7
3
II
10T73200, 10T73201
16-91T CMOS MULTILEVEL PIPELINE REGISTERS
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
10T73200 PIPELINE CONFIGURATIONS
IOT73201 PIPELINE CONFIGURATIONS
Four 2-Level
Seven 1-Level
~~
~~
Two4-Level
+1=0
A
I
Three 2-Level
E
I
~
~
=11~=.13
E
A .
B
One B-Level
One 4-Level, One 3-Level
F
One 7-Level
!
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vce
VTERM
TA
TSIAS
TSTG
lOUT
Rating
Commercial
Power Supply
-0.5 to +7.0
Vohage
Terminal Vohage
-0.5 to
with Respect
Vcc+ 0.5
toGND
Operating
oto +70
Temperature
Temperature
-55 to +125
Under Bias
Storage
-55 to +125
Temperature
DC Output
50
Current
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Military
-0.5to+7.0
Unit
V
-0.5 to
Vcc+ 0.5
V
-55 to +125
°C
-65 to +135
°C
-65 to +155
°C
50
mA
Symbol
CIN
COUT
Parameter(1}
Input Capacitance
Output Capacitance
Conditions
VIN =OV
VOUT= OV
Max.
10
12
Unit
pF
pF
NOTE:
25621bl 07
1. This parameter is sampled at initial characterization and is not 100%
tested.
NOTE:
2562 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
8.7
4
10173200, 10173201
16·BIT CMOS MULTILEVEL PIPELINE REGISTERS
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
0 to +70
0 ,5 V ±5%; MT
Cornrnercla:
. I 0C
C
Iitary: - 550 C to + 1250C , 5V ± 100 0
Symbol
Test Condition
Parameter
Min.
Max
Unit
VIH
High-Level Input Voltage
Guaranteed Logic HIGH Level
2.0
-
Vil
Low-Level Input Voltage
Guaranteed Logic LOW Level
O.S
V
IIH
High Level Input Current
Vcc= Max.
VI= Vcc
1
VI=GND
-
V
III
Low-Level Input Current
Vcc= Max.
-1
IlA
IlA
VOH
High-Level Output Voltage
Vcc= Min.,
10H =·SmA(COM'L.), -6mA(MIL.)
2.4
-
V
Val
Low-Level Output Voltage
Vcc= Min.,
10l = 16mA(COM'L.), 12mA(MIL.)
-
0.4
V
los
Short Circuit Output
Current(2)
Vcc = Max., Vo = GND
VI = Vec or GND
-20
-200
mA
10ZH
High Impedance Output
Current
Vcc= Max.
VI= Vcc
-
1
IlA
10Zl
Low Impedance Output
Current
Vcc= Max.
VI=GND
-
-1
IlA
NOTES:
2562tb108
1. For conditions shown as Min. or Max., use appropriate value based on temperature range.
2. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed 100 milliseconds.
POWER SUPPLY CHARACTERISTICS
Min.
Typ.(2)
Max.
Unit
Iccac
Quiescent Power Supply Current
Vec= Max.
VIN = Vee or GND
-
2
10
mA
Iccar
Quiescent Power Supply Current
Inputs HIGH
Vcc= Max.
VI=3.4V
-
15
45
rnA
ICCD1(3)
Dynamic Power Supply Current
Vcc = Max.
Outputs Disable
fcp = 10MHz, 50% Duty Cycle
VIN = Vce or GND
-
10
30
rnA
10
40
Symbol
Parameter
Test Condltlons(1)
COM'L.
MIL.
NOTES:
2562 tbl 09
1. For conditions shown as Min. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading, not production tested.
3. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Iccac + (lccaT x DH x NT) + ICCD (fcp)
Iccac = Quiescent Current
IccaT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for each TIL Input High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Charge moved by an input transition pair (HLH or LH ) mAlMHz
fcp = Clock frequency
AU currents are in milliamps and aU frequencies are in megahertz.
8.7
5
10T73200, 10T73201
16-BIT CMOS MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Commerical: TA - O°C to +70°C, Vee ... 5V +5%'
- , Military: TA = -55°C to +125°C, Vee = 5V -+10%
Commercial
73200L10
73201L10
"
... Parameter
73200L12
73201L12
Military
73200L15
73201L15
73200L12
73201L12
73200L15
73201L15
73200L20
73201L20
Max.
Min.
Max•
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
elK to Yo-Y15
. Propagation Delay(3)
2.5
10
2.5
12
2.5
' 15
2.5
12
2.5
15
2.5
20
ns
SELo-SEL2 to Yo-Y15
Propagation Delay(3)
2.5
10
2.5
12
2.5
15
2.5
12
2.5
15
2.5
20
ns
D0-015 to eLK Set-up Time
3
-
_.
4
-
3
-
4
-
5
1
2
3
10-13 to eLK Set-up Time
3
-
4
-
5
4
-
-
ns
0
-
3
D0-015 to eLK Hold Time
6
-
ns
3
-
ns
-
4
6
-
ns
13
ns
M Disable Time(1)
-
13
ns
elK Pulse Width HIGH(4)
Min.
1
2
-
5
5
-
9
-
10
8
-
9
-
-
6
-
5
-
6
-
ns
5
-
5
-
12
-
15
-
20
-
ns
15
2.5
12
2.5
15
2.5
20
. ns
5
4
-
5
-
7
-
9
-
10
6
-
8
-
9
-
5
-
' 5
-
5
elK Pulse Width LOw(4)
5
-
5
5
elK Period
10
-
12
-
5
15
Data In to Data Out (2,3).
Flowthrough Prop. Delay
2.5
10
2.5
12
2.5
10-13 to elK Hold Time
1.5
'C'EfJ'to eLK Set-up Time
3
'C'EfJ'to elK Hold Time
M Enable Time(1)
1.5
2
2
NOTES:
1. Output Enable and Disable times. measured to 500mV change of output voltage level.
2. 73201 only.'
3. Minimum propagation delays are guaranteed, but not production tested.
4. Minimum pulse widths are guaranteed, but not production tested.
8.7
2
4
4
5
2
6
ns
ns
ns
2562tblll
6
10173200, 10173201
16-BIT CMOS MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2613 tbl 08
CL - Load capacitance: Indudes jig and probe capacitance.
RT a Termination resistance: should be equal to ZOUT of the Pulse '
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
~~
xxt
PULSE WIDTH
-= ~~V
J
-
OV
tsu~~~
LOW-HIGH-LOW
PULSE
-w
------,.1'--+----- _6~V
INPUT
ASYNCHRONOUS CONTROL
----IIII.I...r--+O--+---- -
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
CLOCK
-
:~~t~ vvir~~r17-t~JI;--r-:~~~i:~:~~
ETC.
~
su
3V
1.5V
OV
HIGH-LOW-HIGH
PULSE
=!J
V
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
_--_·---3V
CONTROL
INPUT
SAME PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
LOW
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
DISABLE
_---3V
----..t-
OUTPUT
NORMALLY
HIGH _ _ _
3.SV
VOL
VOH
~
OV
' -_ _" - - - - OV
NOTES
2613 drw 05
1. Diagram shown for Input Control Enable-LOW and Input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S 500; tF S 2.5n9;
tR S 2.5ns.
'
8.7
7
G®
Integrated Device Technology, Inc.
• 73210/211 Single-level pipeline register from Port A to
Port B
• 73210 Two level pipeline register from Port B to Port A
• 73211 Single level pipeline register from Port B to Port A
• Military product compliant to MIL-STD-883, Class B
• Available in 32-pin sidebraze DIP and surface mount
32-pin SOJ packages
FEATURES
•
•
•
•
•
PRELIMINARY
IDT73210/A/B
IDT73211/A/B
FAST CMOS OCTAL
REGISTER TRANSCEIVER
WITH PARITY
Two bidirectional 9-bit I/O paris
Available in standard, A, and B speed grades
High output drive capability: 64mA (Com'l), 48mA (Mil)
Low CMOS power: O,1mW typical
Parity Generation/Checking in both directions with
polarity control for A-to-B direction
IDT73210 FUNCTIONAL BLOCK DIAGRAM
AOE
PERRS
AEN
CP---~I>
QXo-a
9
POLARITY
+----+---....---..
Even Parity Even~Odd
Check
Pan~
Generation
9
9
QYo-a
Wo-a
L - - - - - - - - 4 - - - - - + - LE
' - - _ - - - " I r - - _ - - I t - - - - - - - - - - 4 - SEL
PERRA
BOE
2594 drw 1a
S
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1992 Integrated Device Technology, Inc.
8,8
MARCH 1992
DSC-903512
1
IDT73210/AlB,IDT73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT73211 FUNCTIONAL BLOCK DIAGRAM
P RRB
T
AEN
cP .......-~
L-~
Vee
__~-----t-----------BEN
QXo-a
9
POLARITY
-----f--_---,
9
Even Parity Evenl,Odd
Check
Pantx
Generation
9
Even Parity
Check
9
9
Yo-a
..--_-+-LE
~------------~~
'-----""1""'""-_....
SEL
2594 drw 1b
PERRA
BOE
EI
S.S
2
IDT7321 OfAlB, IDT73211fAlB
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION
error has occurred. When BEN is low, WO-8 is latched into
Register Z on the low-to-high CP transition. The previous
contents are held in Register Z if BEN is high or if there is no
low-to-high CP transition. The output data bus is AO-8 and is
enabled when AOE is low. When SEL is high, there is only a
one clock cycle latency.
. When SELis low, the incoming data is latched into Register
Y on the low-to-high CP transition, when BEN is low. Even
parity of the registered data is checked. If PERRB goes high,
a parity error has occurred. Even parity (OY8) is generated on
the contents in Register Y. When BEN is low, the contents of
register Yare transferred to Register Z on the low-to-high CP
transition. When BOE is low, the content of Register Z is made
available at output Port A. When SEL is low, there is a two
clock cycle latency.
Port B to Port A Path (10173211) is comprised of latch
(W), latch (Y), register (Z), an even parity generator/checker
and a parity bit latch complementor. The input data bus is on
the BO-8 lines.
When SEL is high, the incoming data is latched into Latch
W. When LE is high, Latch W is transparent; when LE is low,
Latch W is closed. The parity bit, B8, can be complemented
by the POLARITY pin. If POLARITY is low, the parity sense
remains the same. If POLARITY is high, the parity sense is
complemented. Parity is not generated in this path. Even
parity of latched data is checked. If PERRB goes high, a parity
error has occurred. When BEN is low, WO-8 is latched into
Register Z on the low-to-high CP transition. The previous
contents are held in Register Z if BEN is high or if there is no
low-to-high CP transition. The output data bus is AO-8 and is
enabled when AOE is low. When SEL is high, there is only a
one clock cycle latency.
When SEL is low, the incoming data is latched into Latch Y
when LE is hig h. Latch Y is closed when LE is low. Even parity
of latched data is checked. If PERRB goes high, a parity error
has occurred. Even parity (Y8) is generated on the contents
in Latch Y. When BEN is low, the contents of Latch Yare
transferred to Register Z on the low-to-high CP transition.
When BOE is low, the content of Register Z is made available
at output Port A. When SEL is low, there is a one clock cycle
latency.
The power pins are Vcc and GNOO-2. GN Do is internal quiet
ground, GN01 is Port B ground and GN02 is Port A ground.
The IOT7321 0/211 Octal Register Transceivers with parity,
are designed for high performance systems requiring bidirectional data transfer between two busses with parity support.
These transceivers are offered in several speed grades to
support data transfer in systems with up to 40 MHz data rates.
The output buffers have high drive capability for high capacitance driving and low impedence line driving.
The IOT73210/211 Register Transceivers provide Even/
Odd parity generation from Port A to Port B and Even parity
generation from Port B to Port A. Even parity checking with
ERROR flag is provided in both directions. The Even/Odd
parity and Generate/Checkoptions can be dynamically reconfigured.
The IOT7321 0/211 can be used as an interface between a
cache memory and the main memory in any RISC or CISC
microprocessor system. The pipelining feature makes these
devices ideal for use as Read/Write buffers. They can also be
used as high speed general purpose registers in any parity
based system. In this application, the IOT7321 0/211 replace
the equivalent of an FCT52 Bidirectional Register and two
F280 parity generator/checker devices.
DETAILED FUNCTIONAL DESCRIPTION
Port A to Port B Path (10173210 and 10173211) is
comprised of a register (X), an even/odd parity generator and
an eve~rity checker. The input data is on the AO-8 lines.
When AEN is low, AO-8 is latched into Register X on the lowto-high CP transition. Even parity of the latched data is
checked. If PERRA goes high, a parity error has occurred. A
new parity bit, B8, is generated. The output data bus is BO-8
and is enabled whenBOE is low.
Port B to Port A Path (10173210) is comprised of a latch
(W), two registers (Y and Z), an even parity generator/checker
and a parity bit latch complementor. The input data bus is on
the BO-8 lines.
When SEL is high, the incoming data is latched into Latch
W. When LE is high, Latch W is transparent; when LE is low,
Latch W is closed. The parity bit, B8, can be complemented
by the POLARITY pin. If POLARITY is low, the parity sense
remains the same. If POLARITY is high, the parity sense is
complemented. Parity is not generated in this path. Even
parity of latched data is checked. If PERRB goes high, a parity
8.8
3
IDT73210/AlB,IDT73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1)
BEN
BOE
Bo
B1
B2
B3
B4
GNDo
GND1
Bs
B6
B7
Ba
PERRB
LE
CP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P32-2,
C32-2
&
S032-2
SEL
AOE
Ao
A1
A2
A3
A4
Vee
GND2
As
A6
A7
Aa
PERRA
AEN
POLARITY
2594 drw02
DIP/SOJ
TOP VIEW
NOTE:
1. GNDo
GNDI
GND2
internal quiet ground
B Port ground
Port ground
A
PIN DESCRIPTIONS
Pin Name
1/0
Ao-a
AEN
AOE
1/0
I
I
Data Port A.
Clock enable (active low) for the register X.
3-state output enable for Port A.
BO-6
BEN
BOE
LE
1/0
SEL
I
Data Port B.
Clock enable (active low) for the registers Y and Z.
3-state output enable for Port B.
Latch enable input for Latch Y/Latch Wof Port B. The Latch Y/Latch W is open when LE is high. Data is latched
on the high-to-Iow transition of LE.
Input selection for Port B.
SEL =0 Register Y (73210); SEL = 1 LatchW
SEL =0 Latch Y (73211);
POLARITY
I
I
I
I
Description
Polarity selection input.
Polarity
A to 8 Direction
0
EVEN
1
ODD
PERRA
PERRB
0
0
Parity output error for Port A.
Parity output error for Port B.
CP
I
Input clock.
Vee
GNDo-2
8 to A Direction
Pass Parity
Complement Parity
II
+5 volts.
Ground.
25941bIOl
8.8
4
IDT73210/AlB,IDT73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODES SUMMARY
10173210/11 A TO 8 DIRECTION, SEL
=X
Output
Input
A0-8
Reg. X
PERRA
(Bs)
B0-8
Ao-s ~ QXo-s
Result of even
parity check
Even/odd parity bit
Bs .. POLARITY XOR
Even parity generate
from QXO-7
QXo-s ~ Bo-s
(BOE= 0)
~LotoHi)
(AEN = 0)
10173210/18 TO A DIRECTION WHEN SEL
2594tbl02
=1
Reg.Z
Input
B0-8
LatchW
Bo-s~
WO-8
(LE = 1)
PERRB
Result of even
parity check
{QZs}
Bit complemented
by POLARITY
(Even/odd parity
translation)
Output
QZ0-8
{As}
A0-8
Wo-s ~QZo-s
(CP = Lo to Hi)
(BEN =0)
As .. POLARITY XOR
Ws
QZo-s ~Ao-8
(AOE = 0)
2594 tbl 03
101732108 TO A DIRECTION WHEN SEL = 0
Output
Reg.Z
Input
B0-8
Reg. V
PERRB
Bo-s ~ QYo-s
Result of even
~LotoHi) parity check
(BEN = 0)
{QZs}
Even parity generated
bit
QZ0-8
{As}
A0-8
~
As = Even parity
generated from QYo-7
QZ{)-8 ~ Ao-s
(AOE = 0)
QYo-s
QZo-s
~LotoHi)
(BEN .. 0)
2594 tbl04
10173211 8 TO A DIRECTION WHEN SEL = 0
Output
Reg.Z
Input
B0-8
Latch V
BCH! ~ Yo-s
(LE = 1)
PERRB
{QZs}
QZ0-8
(As)
A0-8
Result of even
parity check
Even parity generated
bit
Yo-s ~ QZo-s
(CP = La to Hi)
(BEN = 0)
As = Even parity
generated from Yo-7
QZo-s ~Ao-8
(AOE = 0)
2594tbl05
8.8
5
IDT73210/AlB,IDT73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CACHE
R3000
MEMORY
36
34 "
4 x (74FCT823)
I
I
5 x (29FCT52
I
~
4...(
32 ... f-
4 x 280)
I
~
Address
+ Ace Type (0, 1)
Data Bus Chip Count
Application
usmg FCT52 and F280
Data
=9
Pin Count
= 176
CACHE
R3000
MEMORY
36
4
x (74!
CT823)
I
I
4
x
~
3210
I
Application using 73210
Address + Ace Type (0, 1)
Data
=
Pin Count
Data Bus Chip Count 4 .
Saves 10ns in the Critical Data Path
=128
2594 drw 04
II
Figure 1. R3000 System with No Parity Support in Main Memory
8.8
6
IDT7321 OfAlB, IDT73211fAlB
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CACHE
MEMORY
R3000
34 I-4x
'74t-l
36
MZ:f
I
I
5 x (29FCT52
I
4 ...
32 ...
-Parity
Error
4 x (280)
t
36 ...
Address + Ace Type (0, 1)
Data Bus Chip Count
Application
uSing FCT52 and F280
Data + Parity
=9
Pin Count
=176
CACHE
MEMORY
R3000
34 . .
36
4 x (7 4FCT823~
J
1'-----.,;:4~x:..:,7~32~1:..:::.0_
Parity
Error
__1
36 ... 1-Application using 73210
Address + Ace Type (0, 1) .
Data Bus Chip Count
=4
Data + Parity
Pin Count
=128
2594 drw05
Figure 2. R3000 System with Parity Support In Main Memory
8.8
7
10T73210/AlB,10T73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
32 + 4
FPU
CPU
Data 14-------'
AddrLol--------.....:1~8,L_~
Reset --.
Init
Init--. PAL
.
State
Optlons
Machine
Intr 5-0 - - .
I-----~~
Tag 14------,
20 + 1 + 3
(1 )
FCT240A
.---. .---.
B~
Ba-Q
W
Mem
Rd&Wr
73210/11
73210/11
u erea
Sys Clock.
t
t
Aa-o
Aa-Q
73210/11
73210/11
Aa-Q
CP
CP
LE
BUS
Rd & r
t
t
Aa-{)
Ba-Q
73210/11
AOE
73210/11
73210/11
PERRA,B
PAL State Machine
Address
AOE
XEn
Data + Parity
Figure 3. Read and Write BuHers Using Eight 10T73210/11
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Vee
Rating
Terminal Voltage
with Respect
to Ground
Power Supply
Voltage
TA
Operating
Temperature
TSIAS
TSTG
CAPACITANCE
Com'l.
Mil.
Unit
-0.5 to
Vee + 0.5
-0.5 to
Vee+ 0.5
V
-0.5 to +7.0 -0.5 to +7.0
Oto +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125 -65 to +135
°C
Storage
Temperature
-55 to +125 -65 to +150
°C
Conditions
Typ.
Unit
5
pF
VOUT= OV
7
pF
VOUT= OV
7
pF
CIN
Input
Capacitance
VIN
COUT
Output
Capacitance
CVO
Input - Output
Capacitance
V
NOTE:
PT
Power Dissipation
1.2
1.5
W
lOUT
Total Output
Current
200
250
mA
NOTE:
Symbol
(TA = +25°C, f = 1.0MHz)
Parameter(l)
=OV
2594 tbl 07
1. This parameter is not production tested.
2594 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This Is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speclflcatlon Is not Implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8.8
8
IDT73210/AlB,IDT73211/A1B
FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to + 125°C, Vcc
Symbol
Test Conditlons(1)
Parameter
Min.
5.0V± 10%
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
VIL
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
Vec = Max.
Except I/O
-
0.8
IIH
10
I-IA
VI = 2.7V
1/0 pins
IlL
Input LOW Current
Vee = Max.
Except I/O
VI = 0.5V
1/0 pins
-
-0.7
-1.2
V
PERRA, PERRB
-30
-
-150
mA
AO-8, BO-8
-20
-
-75
10H
= -12mA MIL.
10H =-15mA COM'L.
2.4
3.3
-
-
0.3
-
200
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee
VOH
Output HIGH Voltage
Vee = Min.
VIN
VOL
Output LOW Voltage
Input Hysteresis for CP only
= VIH or VIL
Vee= Min.
Ao-a
10L = 48mA MIL.
VIN = VIH or VIL
Bo-a
10L = 64mA COM'L.
Vee= Min.
PERRA
10L = 20mA MIL.
PERRB
10L = 24mA COM'L.
VIN
VH
= Max,--+~.-.-_14~. . YS:15
(Even Path)
LEYX--~--~+_--------------------~~
16
~--4~+--
XO:7 ~"""~-+--4P-<
BUS CONTROL
~-----+--
XS:15 ~"",,~-''--t-<
PATH
/4------+--- TiR
OEU
~--+--OEI
LEZX--~--~+_--------------------~~
16
OEZL
16
LEXZ--~--------------------------~~
">---~I--I4I--~ Za:15
OEZU
(Odd Path)
2527drw 01
Figure 1. 73720 Block Diagram
NOTE:
1. logic equations for bus control:
OEXU = TiFf* . CEO*; OEXl =T/R"* . QE[*; OEYU .. T/~ . PATH. CEO*
OEYl = T/R". PATH. QE[*; OEZU = T/R". PATH* . CEO*; OEZl a T/R". PATH* . QE[*
CEMOS. RISChpSet, RISController, R305x, R3051 , R3052 are trademarks of Integrated Device Technology, Inc.
MARCH 1992
COMMERCIAL TEMPERATURE RANGE
11:11992 Integrated Device Technology, Inc.
8.9
050-204&'3
1
IDT73120/A 16-BITTRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
GND
X8
Z9
Pin 1
Designator
X9
Z6
Z5
Z4
X10
X11
X12
X13
X14
X15
GND
VCC
PATH
OEU
lEYX
lEZX
YO
Y1
Z8
Z7
Z3
J68-1
21
Z2
Z1
ZO
GND
VCC
lEXZ
OEl
lEXY
TiFf
GND
PLCC
TOP VIEW
GND
NC
NC
X8
X14
X15
GND
VCC
PATH
OEU
lEYX
LEZX
YO
Y1
GND
Pin 1
Designator
PQ80-1
Z6
Z5
Z4
Z3
Z2
Z1
ZO
GND
VCC
lEXZ
OEl
LEXY
TIR
NC
NC
GND
PQFP
TOP VIEW
8.9
2527 drw 03
2
IDT73720 IA16-BITTRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Sianal
X(0:15)
Y(0:15)
Z(0:15)
I/O
I/O
I/O
I/O
Description
Bidirectional Data Port X. Usually connected to the CPU's AID (Address/Data) bus.
Bidirectional Data port Y. Connected to the even path or even bank of memory.
Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
LEXY
I
Latch Enable input for V-Write Latch. The V-Write Latch is open when LEXY is high. Data from the X-port
(CPU) is latched on the high to low transition of LEXY
LEXZ
I
Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is high. Data from the X-port
(CPU) is latched on the high to low transition of LEXZ.
LEYX
I
Latch Enable input for the V-Read Latch. The V-Read Latch is open when LEYX is high. Data from the even
path Y is latched on the high to low transition of LEYX.
LEZX
I
Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is high. Data from the odd
path Z is latched on the high to low transition of LEZX
PATH
I
Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the V-port (even
path). When low, PATH enables data transfer between the X-Port and the Z-Port (odd path).
T/R
I
TransmiVReceive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When low, Por
X is an output Port while Ports Y & Z are input Ports
'O"EIT
I
Output Enable for Upper byte. When low, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/R'.
OEL
I
Output Enable for Lower byte. When low, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/R' .
2527tbl02
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE
Symbol
Rating
Com'l.
Mil.
VTERM
Terminal Voltage
with Respect
toGND
Operating
Temperature
-0.5 to +7.0
-0.5 to +7.0
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
Power
Dissipation
-55 to +125
-65 to +125
°C
1.0
1.0
W
50
50
rnA
TA
PT
lOUT
NOTE:
DC Output
Current
Unit
Symbol
CIN
V
COUT
(TA= +25°C, F =
1.0MHz)
Parameter(1)
Input Capacitance
Conditions
VIN= OV
Max.
8
Output Capacitance
VOUT= OV
12
NOTE:
Unit
pF
pF
2527 tbl 04
1. This parameter is guaranteed by device characterization, but is not production tested.
TRUTH TABLE
OEU
Path
T/J=f
2527tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
L
L
L
QE[
L
Functionality
Z~X (16-bits)-Read Z(1)
L
H
L
L
X~Z (16 bits)-Write Zl1}
H
L
L
L
Y ~X (16-bits)-Read y(2)
H
H
L
L
X~Y (16 bits)-Write y(2)
X
X
H
H
All output buffers are
disabled
X
X
H
L
Transfer of lower 8 bits
(0:7) as per PATH & T/R'
X
X
L
H
Transfer of upper 8 bits
(8:15) as per PATH & T/R'
NOTES:
2527tbl01
1. For Z~X and X~Z transfers, V-port output buffers are tristated.
2. For V~X and X~V transfers, Z-port output buffers are tristated.
8.9
3
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
ARCHITECTURE OVERVIEW
The Bus Exchanger is used to service both read and write
operations between the CPU and the dual memory busses. It
includes independent data path elements for reads from and
writes to each of the memory banks (Y and Z). Data flow
control is managed by a simple set of control signals, analogous to a simple transceiver. In short, the Bus Exchanger
allows bidirectional communication between ports X and Y
and ports X and Z as illustrated in figure 1.
The data path elements for each port include:
Read latch: Each of the memory ports Y and Z contains a
transparent latch to capture the contents of the memory bus.
Each latch features an independent latch enable.
Write latch: Each memory port Y and Zcontains an independent latch to capture data from the CPU bus during writes.
Each memory port write latch features an independent latch
enable, allowing write data to be directed to a specific memory
port without disrupting the other memory port.
Data Flow Control Signals
T/R (Transmit/Receive). This signal controls the direction
of data transfer. A transmit is used for CPU writes, and a
receive is used for read operations.
OEU, OEl are the output enable control signals to select
upper or lower bytes of all three ports.
Path: The path control signal is used to select between the
even memory path Y and the odd memory path Z during read
or write operations. Path selects the memory port to be
connected to the CPU bus (X-port), and is independent of the
latch enable signals. Thus, it is possible to transfer data from
one memory port to the CPU bus (X) while capturing data from
the other memory port.
MEMORY READ OPERATIONS
latch Mode
In this mode the read operation consists of two stages.
During the first stage, the data present at the memory port is
captured by the read latch for that memory port. During a
subsequent stage, data is brought from a selected memory
port to the CPU AID port X by using outp'ut enable control.
The read operation is selected by driving Tiff low. The read
is managed using the Path input to select the memory port (Y
,or Z);the LEYXlLEZX enable the data capture into the
corresponding Read Latch.
In this way, memory interleaving can be performed. While
data from one bank is output onto the CPU bus, data on the
other bank is captured in the o~her memory port. In the next
:cycle, the Path input is changed, enabling the next data
COMMERCIAL TEMPERATURE RANGE
element onto the CPU bus, while the first bank is presented
with a new data element.
Transparent Mode
The Bus Exchanger may be used as a data transceiver by
leaving all latches open or transparent.
Memory Write Operations ,
Memory write operations also consist of two distinct stages.
During one stage, the write data is captured into the selected
memory port write latch. During a later stage, the memory is
presented on .the memory port bus
The write operation is selected by driving TIFt" high. Writes
are thus performed using the Path input to select the memory
port (Y or Z). The LEXY/LEXZ capture data in the corresponding Write Latch.
Note that it is possible to utilize the bus exchanger's write
resources as an additional write buffer, if desired; the CPU
AID bus can be freed up once the data has been captured by
the Bus Exchanger.
APPLICATIONS
Use as Part of the R3051 Family ChipSet
Figure 2 shows the use of the Bus Exchanger in a typical
R3051 based system.
In write transactions, the R3051 drives data on the CPU
bus. The latch enables are held open through the entire write;
thus, the bus exchanger is used like a transceiver. The
appropriate LEXY/LEXZ signal is derived from ALE (Logic
low- indicating that the processor is driving data) and the low
order address bit. The rising edge of Wr from the CPU, ends
the write operation.
During read transactions, the memory system is responsible for generating the input control signals to cause data to
be captured at the memory ports. The memory controller is
also responsible for acknowledging back to the CPU that the
data is available, and causing the appropriate path to be
selected.
The R3721 DRAM controller for the R3051 family uses the
transparent latches of the read ports. The R3721 directly
controls the inputs of the bus exchanger, during both rea,ds
and writes. Consult the R3721 data sheet for more information on these control signals.
Use in a general 32·bit System
Figures 3 and 4 illustrate the use of the Bus Exchanger in
a 32-bit microprocessor based system. Note the reduced pin
count achieved with the Bus Exchanger.
8.9
4
IDT73720 IA16-BIT TRI-PORT BUS EXCHANGER
Clk2xln
COMMERCIAL TEMPERATURE RANGE
IDT R3051 FAMILY
RISControlier
ADDRESS/DATA
CONTROL
IDT79R3721
. DRAM
CONTROLLER
Figure 2. Bus Exchanger Used in R3051 Family System
2527drw 04
Address
Address
Data Bus Chip Count = 2 Pin Count = 136
Data Bus Chip Count
=2
Pin Count = 136
II
Address
Data Bus Chip Count
Address
=8
Pin Count
=160
Data Bus Chip Count = 8 Pin Count = 192
2527 drw 05
Figure 3. CPU System with Transparent Data Path
(2-way Interleaving)
2527 drw 06
Figure 4. CPU System with Latched Data Path
(2-way Interleaving)
IDT73720/A 16-BITTRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, TA = O°C to +70°C)
Test Condltlons(1)
Symbol
VIH
VIL
IIH
Parameter
Ineut HIGH Level
Input LOW Level
Input HIGH Current
Vee = Max., VIH = 2.7V
IlL
Input LOW Current
Vee = Max., VIL = 0.5V
-
Inputs only
I/O pins
Inputs only
110 pins
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
All inputs
Vee = Min., liN = -18mA
Vee = Max., Vo = GND
Vee = Min., VIN = VIH or VIL, IOH = -12mA
Vee = Min., VIN = VIH or VIL, 10L = 12mA
Vee = 5V
Ice
Quiescent Power
Supply CUrrent
L\lce
VIK
105(3)
Min.
2.0
-
Typ.(2)
Max.
-
-
-
-
-
-
-
-
-0.7
0.8
5.0
5.0
-5.0
-5.0
-1.2
-200.0
Unit
V
V
jJA
jJA
-sO.o
-
2.4
-
3.3
0.3
200.0
0.5
-
V
mA
V
V
mV
Vee= Max.
VIN = GND or Vee
-
0.2
1.5
mA
Quiescent Power
Supply Current
Vee = Max.
VIN=3.4 V(4)
-
0.5
2.0
mAl
Input
IceD
Dynamic Power
Supply Current(5)
Vee = Max.
VIN = Vee or GND
Outputs Disabled
O"E=Vee
One Input Toggling
50 % Duty Cycle
-
0.25
0.5
mAl
MHz
Ie
Total Power Supply
Current(6)
Vee = Max.
VIN = Vee or GND
Outputs Disabled
50 % Duty Cycle
O'E=Vee
fi=10MHz
One Bit Toggling
-
2.7
S.5
mA
VOH
VOL
VH
2527tbl05
NOTES:
1.
2.
3.
4.
5.
6.
-
For conditions shown as max. or min., use appropriate Vcc value.
Typical values are at Vcc = 5.0V, +25°C ambient.
Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
Ic = IQUIESCENT + !INPuTS + IDYNAMIC
Ic = Icc + alcc DHNT + ICCD (fcp/2 + fiNi)
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH ., Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at Ii
All currents are in milliamps and all frequencies are in megaherz.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
GND to 3.0V
5ns
1.5V
1.5V
Output Load
See Figure 5
2527tbl06
8.9
6
10173720 IA16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0° to +70°C)
7:.Jn,U
7:.JTilUA
Symbol
Test Condltlons(1)
Parameter
Mln. I "}
Max.
Mln.I "}
Max.
Units
-
-
2.0
7.5
ns
-
-
2.0
7.5
ns
LEXYto Y
LEXZtoZ
-
-
2.0
8.5
ns
LEYXto X
LEZXto X
-
-
2.0
8.5
ns
-
-
2.0
8.5
ns
PATH, OEU, 0EC)(3)
-
-
2.0
9.5
ns
tzH
tzl
Y & Z Port Enable Time (TIR, PATH, OEU, 0EC)(3)
-
-
2.0
10.5
ns
tHZ
tLl
X-Port DisableTime (TIR,
-
-
2.0
9.5
tzH
tzl
tsu
X-Port Enable Time
tH
Port to LE Hold time
tPlH
tPHl
X to Y & X to Z Latches enabled
tPlH
tPHl
Y to X & Z to X Latches enabled
tPlH
tPHl
Latch Enable to Y & Z Port
tPlH
tPHl
Latch Enable to X
tPlH
tPHl
Path to X Port Propagation Delay
tHZ
tLl
Y & Z Port Disable Time
(T/R',
Cl = 50pF
Rl= 500 Ohms
OEU, 0EC)(3)
ns
.'
(TIR, OEU; 0EC)(3)
Port to LE Set-up time
-
-
2.0
-
-
2.0
-
1.5
10.5
-
NOTES:
1. All timings are referenced to 1.5 V.
2. This parameter is guaranteed by design, but not tested.
3. Bus turnaround times are guaranteed by design,but not tested. (T/R' enable/disable times).
TEST CIRCUITS AND WAVEFORMS
ns
ns
ns
2527tbl07
SWITCH POSITION
'-o.-7.0V
Test
Switch
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2527 tbl 08
CL .. Load capacitance: includes jig and probe capacitance.
RT m Termination resistance: should be equal to ZOUT of the Pulse
Generator.
II
Figure 5. Test Circuit for all outputs
8.9
7
IDT73720/A 16-BITTRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
=t-
PULSE WIDTH
zzt~~'
-f7--JH.....
--+-.--4~~hr;:~~"''!fJJ.~~ -'7~-= ~~V
- OV
Jft:1I1iC.
tsu
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONxxtTROL
J
tsu
~
- - 1.5V
LOW-HIGH-LOW
PULSE'
- 3V
1.5V
- OV
- 3V
1.5V
- OV
HIGH-LOW-HIGH
PULSE
.
~
_ _ 1.5V
1W
- 3V
-
~..,~~~~ -
2527drw 09
1.5V
OV
2527 drw 08
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
DISABLE
r----3V
SAME PHASE
INPUT TRANSITION
----1.5V
~--J~r--------OV
3.5V.
OUTPUT
VOL
OPPOSITE PHASE
INPUT TRANSITION
NO~~~~~
SWITCH
HIGH OPEN
2527 drw 10
.VOH
OV
2527 drw 11
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH.
2. Pulse Generator for All Pulses: Rate ~ 1.0 MHz; ZO ~ son; tF ~ 2.Sns; tR
~ 2.Sns.
8.9
8
(;)®
16-81T CMOS
ERROR DETECTION
AND CORRECTiON UNIT
Integrated Device Technology, Inc.
FEATURES
IDT39C60
IDT39C60-1
IDT39C60A
IDT39C60B
• Standard Military Drawing #5962-88613 available for this
function
• Low-power CEMOSTM
- Military: 100mA (max.)
- Commercial: 85mA (max.)
• Fast
- Data in to Error Detect
IDT39C60B: 18ns (max.), IDT39C60A: 20ns (max.)
IDT39C60-1: 25ns (max.), IDT39C60: 32ns (max.)
- Data in to Corrected Data out
IDT39C60B: 25ns (max.), IDT39C60A: 30ns (max.)
IDT39C60-1: 52ns (max.), IDT39C60: 65ns (max.)
• Improves system memory reliability
- Corrects all single-bit errors, detects all double and
some triple-bit errors
• Cascadable
- Data words up to 64 bits
• Built-in diagnostics
- Capable of verifying proper E DC operation via
software control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Available in 48-pin DIP, 52-pin PLCC and LCC
• Pin-compatible to all versions of the AMD2960
• Military product available compliant to MIL-STD-883,
Class B
DESCRIPTIONS
The IDT39C60 family are high-speed, low-power, 16-bit
Error Detection and Correction Units which generate checkbits on a 16-bit data field according to a modified Hamming
Code and correct the data word when checkbits are supplied.
When performing a read operation from memory, the
IDT39C60s will correct 100% of all single bit errors, will detect
all double bit errors and some triple bit errors.
The IDT39C60s are easily cascadable from 16 bits up to 64
bits. Sixteen-bit systems use 6 check bits, 32-bit systems use
7 check bits and 64-bit systems use 8 check bits. For all three
configurations, the error syndrome is made available.
All parts incorporate 2 built-in diagnostic modes. Both
simplify testing by allowing for diagnostic data to be entered
into the device and to execute system diagnostic functions.
The IDT39C60s are pin-compatible, performance-enhanced
functional replacements for all versions of the 2960. They are
fabricated using CEMOS, a CMOS technology designed for
high-performance and high-reliability. The devices are packaged in either 48-pin DIPs and 52-pin PLCC and LCCs.
Military grade product is manufactured in compliance to the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
LEoUT ~-------,
OEBYTEO L > - - - - . . . ,
C~~~r----r-~------------------'
DATJI.o-7
~~!L--o-.r~;:;;~l
DATAa-15 ~--P""I'L~~~J
OE BYTE 0,1 L>-t-~-+-----'
LEIN
L>--+-+-----I
ERROR
MULTERROR
LEoIAG
C>-------I
CODE ID D-~-1-----,
DIAG MODE c>-..,.r:,.-I~
CONTROL
PASSTHRU C>---=-I--J
LOGIC
GENERATE C>--~
CORRECT L J - - - " L_ _ _---1
2595 drw 01
CEM05 and MICR05L1CE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<{l1992 Integrated Device Technology, Inc.
8.10
MAY 1992
05C·901614
1
£I
IDT39C60/-1/A1B
16-BIT CMOS DETECnON AND CORRECnON UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CORRECT
DATA15
DATA14
DATA13
DATA12
LEIN
LEOIAG
OEBYTEl
DATAll
DATAl a
DATAg
DATAa
GND
DATA7
DATAs
DATA5
DATA4
OEBYTEo
LEoUT
DATA3
DATA2
DATAl
DATAo
SC1
1
2
3
4
5
6
7
8
9
10
11
12
P48-1
&
C48-2
13
48
47
46
45
44
43
42
41
40
39
38
37
PASSTHRU
DIAG MODEl
DIAG MODEo
CODE 102
CODE 101
CODE 100
GENERATE
CBs
CBo
CB5
CB4
CB3
36
Vee
32
CB2
CBl
MULT ERROR
ERROR
18
31
OEse
19
20
21
22
30
29
28
27
23
26
24
25
SCo
SC5
SC3
SC2
SC4
SCs
14
15
35
34
16
33
17
2595 drw 02
DIP
TOP VIEW
(600 mil x 100 mil Centers)
INDEX~
•••••••
I
I
I.
I
I
I"
1'1
I
I
I
I.
I
I
LJUUWULJ::LJLJLJULJU
7 6 5 4 37:: 525150494847
LEolAG
OEBYTEl
DATAll
DATAl 0
DATAs
DATAB
GND
DATA7
DATAs
DATAs
DATA4
OEBYTEo
Vee
:]
:]
:]
:]
:]
:]
:]
:]
:]
:]
:]
:]
:]
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
1
PIN 1
INDICATOR
FOR PLCC
JS2-1
[:
[:
[:
[:
[:
c:
[:
[:
GND
""'G""'EN"""E....RA=""'...
tE
CBs
CBo
CB5
CB4
CB3
Vee
c: CB2
[:
[:
c:
[:
CBl
MULTERROR
ERROR
OEs
e
21
2223 242526 27 28 29 30 31 3233
,..,,..,,..,,..,,..,,..,,..,,..,,..,,...,,...,,..,,...,
•
I
I
I"
I
I.
1'1'"
I.
I
II.
I
I
I
I
,
2595 drw 03
PLCC
TOP VIEW
(750 mil x 750 mil Centers)
8.10
2
IDT39C60/·1/AiB
16·BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
DATA0-15
I/O
VO
Description
16 bidirectional data lines provide input to the Data Input Latch and receive output from the Data Output Latch.
DATAo is the least significant bit; DATA15 the most significant.
CBD-6
I
Seven check bit input lines are used to input check bits for error detection. Also used to input syndrome bits
for error correction in 32- and 64-bit configurations.
LEIN
I
Latch Enable-Data Input Latch. Controls latching of the input data. When HIGH, the Data Input Latch and
Check Bit Input Latch follow the input data and input check bits. When LOW, the Data Input Latch and Check
Bit Input Latch are latched to their previous state.
GENERATE
I
Generate Check Bits input. When this input is LOW, the EDC is in the Check Bit Generate mode. When HIGH,
the EDC is in the Detect mode or Correct mode. In the Generate mode, the circuit generates the check bits
or partial check bits specific to the data in the Data Input Latch. The generated check bits are placed on the
SC outputs. In the Detect or Correct modes the EDC detects single and multiple errors and generates
syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch. In Correct mode,
single-bit errors are also automatically corrected - corrected data is placed at the input of the Data Output
Latch. The syndrome result is. placed on the SC outputs and indicates, in a coded form, the number of errors
and the bit-in-error.
SC043
0
Syndrome/Check Bit outputs hold the check/partial check bits when the EDC is in Generate mode and will hold
the syndrome/partial syndrome bits when the device is in Detect or Correct modes. These are 3-state outputs.
OEsc
I
Output Enable-Syndrome/Check Bits. When LOW, the3-stateoutput lines SCO-6 are enabled. When HIGH,
the SC outputs are in the high impedance state.
E1l1QP;
0
Error Detected output. When the EDC is in Detect or Correct mode, this output will go LOW if one or more
syndrome bits are asserted, meaning there are one or more bit errors in the data or check bits. If no syndrome
bits are asserted, there are no errors detected and the output will be HIGH. In Generate mode, El1RC)R" is
forced HIGH. (In a 64-bit configuration, ERROR must be implemented externally.)
MOLT ERROR
0
Multiple Errors Detected output. When the EDC is in Detect or Correct mode this output, if LOW, indicates
that there are two or more bit errors that have been detected. If HIGH, this indicates that either one or no errors
have been detected. In Generate mode, MULT ERROR is forced HIGH. (In a 64-bit configuration,
MOLT ERROR must be implemented externally.)
CORRECT
I
Correct input. When HIGH, this signal allows the correction network to correct any single-bit error in the Data
Input Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the
EDC will drive data directly from the Data Input Latch to the Data Output Latch without correction.
LEoUT
I
Latch Enable - Data Output Latch. Controls the latching of the Data Output Latch. When LOW, the Data
Output Latch is latched to its previous state. When HIGH, the Data Output Latch follows the output ofthe Data
Input Latch as modified by the correction logic network. In Correct mode, single-bit errors are corrected by
the network before loading into the Data Output Latch. In Detect mode, the contents of the Data Input Latch
are passed through the correction network unchanged into the Data Output Latch. The inputs to the Data
Output Latch are disabled with its contents unchanged if the EDC is in Generate mode.
OEBYTEo
OEBYTE1
I
PASSTHRU
I
DIAG MODE0-1
CODE ID0-2
I
I
LEDIAG
I
Output Enable - Bytes 0 and 1, Data Output Latch controls the 3-state outputs for each of the two bytes
of the Data Output Latch. When LOW, these lines enable the Data Output Latch and, when HIGH, these lines
force the Data Output Latch into the high impedance state. The two enable lines can be separately activated
to enable only one byte of the Data Output at a time.
PASSTHRU input, when HIGH, forces the contents of the Check Bit Input Latch onto the Syndrome/Check
Bit outputs (SC043) and the unmodified contents of the Data Input Latch onto the inputs of the Data Output
Latch.
Diagnostic Mode Select controls the initialization and diagnostic operation of the EDC.
Code Identification inputs identify the size of the total data word to be processed and which 16-bit slice of larger
data words a particular EDC is processing. The three allowable data word sizes are 16,32, and 64 bits and
their respective modified Hamming Codes are designated 16/22, 32139 and 64/72. Special CODE ID input
001 (ID2, ID1, IDo) is also used to instruct the EDC that the signals CODE IDo-2, DIAG MODE0-1, CORRECT
and PASSTHRU are to be taken from the diagnostic latch rather than the control lines.
Latch Enable - Diagnostic Latch. The Diagnostic Latch follows the 16-bit data on the input lines when HIGH.
When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch
holds diagnostic check bits and internal control signals for CODE IDo-2, DIAG MODE0-1, CORRECT and
PASSTHRU.
2595tbl01
8.10
3
II
IDT39C60f·1fAlB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
The IDT39C60 EDC Unit is a powerful 16-bit cascadable
slice used for check bit generation, error detection, error
correction and diagnostics. As shown in the Functional Block
Diagram, the device consists of the following:
-
Data Input Latch
Data Output Latch
Diagnostic Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Control Logic
ERROR goes low. If two or more errors are detected, both
ERROR and MULT ERROR go low. Both outputs remain high
when there are no errors detected.
For single bit errors, the correction logic will complement
(correct) the bit in error, whichcanthen be loaded into the Data
Out Latches under the LEoUT control. If check bit errors need
to be corrected, then the device must be operated in the
Generate mode.
CONTROL LOGIC
The control logic determines the specific mode of operation, usually from external control signals. However, the
Internal Control mode allows these signals to be provided
from the Diagnostic Latch.
DETAILED PRODUCT DESCRIPTION
The IDT39C60 EDC unit contains the logic necessary to
DATA INPUT/OUTPUT/DIAGNOSTIC LATCHES generate check bits on a 16-bit data input according to a
The LEIN, Latch Enable input, controls the Data Input which
can load 16 bits of data from the bidirectional DATA lines. The
input data is used for either check bit generation or error
detection/correction.
The 16 bits of data from the DATA lines can be loaded into
the Diagnostic Latch under control of the Diagnostic Latch
Enable, LEoIAG, giving check bit information in one byte and
control information in the other byte. The Diagnostic Latch is
used when in Internal Control mode or in one of the Diagnostics modes.
The Data Output Latch is split into two bytes and enabled
onto the DATA lines through separate byte control lines. The
Data Output Latch stores the result of an error correction
operation or is loaded directly from the Data Input Latch under
control of the Latch Enable Out (LEoUT). The PASSTHRU
control input determines which data is loaded.
CHECK BIT GENERATION LOGIC
This block of combinational logic generates 7 check bits
using a modified Hamming Code from the 16 bits of data input
from the Data Input Latch.
SYNDROME GENERATION LOGIC
This logic compares the check bits generated through the
Check Bit Generator with either the check bits in the Check Bit
Input Latch or 7 bits assigned in the Diagnostic Latch.
Syndrome bits are produced by an exclusive-OR of the two
sets of bits. A match indicates no errors. If errors occur, the
syndrome bits can be decoded to indicate the bit in error,
whether 2 errors were detected or 3 or more errors.
ERROR DETECTION/CORRECTION LOGIC
.The syndrome bits generated by the Syndrome Logic are
decoded and used to control the ERROR and
MOLTERROR outputs. If one or more errors are detected,
modified Hamming Code. The EDC can compare internally
generated check bits against those read with the 16-bit data
to allow correction of any single bit data error and detection of
all double and some triple bit errors. The IDT39C60 can be
used for 16-bit data words (6 check bits), 32-bit data words
(7 check bits) or 64-bit data words (8 check bits).
CODE AND BYTE SELECTION
The 3 code identification pins, 100-2, are used to determine
the data word size from 16, 32 or 64 bits and the byte position
of each 16-bit IDT39C60 EDC device.
Code 16/22 refers to a 16-bit data field with 6 check bits.
Code 32139 refers to a 32-bit data field with 7 check bits;
Code 64/72 refers to a 64-bit data field with 8 check bits.
The 100-2 of 001 is used to place the device in the Internal
Control mode as described later in this section.
Table 1 defines all possible identification codes.
CHECK AND SYNDROME BITS
The IDT39C60 provides either check bits or syndrome bits
on the three-state output pins, SC~. Check bits are generated from a combination ofthe Data Input bits, while syndrome
bits are an Exclusive-OR of the check bits generated from
read data with the read check bits stored with the data.
Syndrome bits can be decoded to determine the single
bit-in-error or that a double error was detected. Some triple bit
errors are also detected. The check bits are labeled:
Co, C1, C2, C3,
Co, C1, C2, C3,
Co, C1, C2, C3,
Co, C1, C2, C3,
C4
C4, Cs
C4, Cs, C6
C4, Cs, C6, C7
for the 8-bit configuration
for the 16-bit configuration
for the 32-bit configuration
for the· 64-bit configuration
Syndrome bits are similarly labeled So through S7.
8.10
4
IDT39C60/-1/A18
16-81T CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the
IDT39C60. The Diagnostic mode pins, DIAG MODE0-1, define 4 basic areas of operation, with GENERATE, CORRECT
and PASSTHRU, further dividing operation into 8 functions
with the 100-2 defining the ninth mode as the Internal mode.
Generate mode is used to display the check bits on the
outputs SCo-s. The Diagnostic Generate mode displays
check bits as stored in the Diagnostic Latch.
Detect mode provides an indication of errors or multiple
errors on the outputs ERROR and MOLTERROR. Single bit
errors are not corrected in this mode. The syndrome bits are
provided on the outputs SC0-6. For the Diagnostic Detect
mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with
check bits stored in the diagnostic latch rather than with the
check bit latch contents.
Correct mode is similar to the Detect mode except that
single bit errors will be complemented (corrected) and made
available as input to the Data Out Latch. Again, the Diagnostic
Correct mode will correct single bit errors as determined by
syndrome bits generated from the Data Input and contents of
the Diagnostic Latch.
The Initialize mode provides check bits for all zero bit data.
Data In Latch is set and latched to a logic zero and made
available as input to the Data Out Latch.
The Internal mode disables the external control pins DIAG
MODE0-1, CORRECT, PASSTHRU and CODE 10 to be
defined by the Diagnostic Latch. When in the internal control
mode, the data loaded into the diagnostic latch should have
the CODE 10 different from 001 as this would represent an
invalid operation.
CODE
102
CODE
101
CODE
100
Hamming Code
and Slice Selected
DIAG
MODE1
DIAG
MODE2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
Code 16/22
Internal Control Mode
Code 32139, Byte 0 and 1
Code 32139, Byte 2 and 3
Code 64/72, Byte 0 and 1
Code 64n2, Byte 2 and 3
Code 64n2, Byte 4 and 5
Code 64/72. Byte 6 and 7
0
0
Non-diagnostic mode. The EDC
functions normally in all modes.
0
1
Diagnostic Generate. The contents of
the Diagnostic Latch are substitUted for
the normally generated check bits when
in the Generate mode. The EDC functions normally in the Detect or Correct
modes.
1
0
Diagnostic DetecVCorrect. In the Detect or Correct mode, the contents of the
Diagnostic Latch are substituted for the
check bits normally read from the Check
Bit Input Latch. The EDC functions
normally in the Generate mode.
1
1
Initialize. The outputs of the Data Input
Latch are forced to zeroes and the check
bits generated correspond to the all zero
data. The latch is not reset, a functional
difference from the Am2960.
1
1
0
1
0
1
0
1
2595 tbl 02
Table 1. Hamming Code and Slice Identification
Diagnostic Mode Selected
2595 tDl 03
Table 2. Diagnostic Mode Control
II
I
8.10
5
IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT
Operating
Mode
DM1 DMo GENERATE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CORRECT
PASSTHRU
OATAOUT Latch
(LEoUT High)
=
SCo-s
(OEsc Low)
Check Bits Generated
from DATAIN Latch
=
ERROlf
MO[TERRoR
Generate
0
1
0
0
0
X
0
-
Detect
0
0
0
1
1
0
0
DATAIN Latch
Correct
0
0
0
1
1
1
0
PASSTHRU
0
0
1
0
1
0
X
X
1
DATAIN Latch
Check Bit Latch
High
Diagnostic
Generate
0
1
0
X
0
-
Check Bits from
Diagnostic Latch
High
Diagnostic
Detect
1
0
1
0
0
DATAIN Latch
Diagnostic
Correct
1
0
1
1
0
Initialization
Mode
1
1
X
X
X
Inlernal
Mode
Syndrome Bits DATAIN/
Check Bit Latch
OATAIN Latch with Syndrome Bits DATAIN/
Single Bit Correction Check Bit Latch
High
Error Dep\l)
Error Dep
Syndrome Bits DATAINI
Diagnostic Latch
Error Dep
DATAIN Latch with Syndrome Bits DATAIN/
Single Bit Correction Diagnostic Latch
Error Dep
DATAIN Latch
Set to 0000
Check Bits Generated
from DATAIN Latch
(0000)
-
100-2 = 001 (Control Signals 100-2, DIAG MODE0-1, CORRECT and PASSTHRU are taken from the Diagnostic
Latch)
NOTE:
25951bl 04
1. ERROR DEP (Error Dependent): El1ROFf will be low for single or multiple errors, with MOLT ERROR low for double or multiple errors. Both signals are
high for no errors.
Table 3. IDT39C60 Operating Modes
8.10
6
IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
16-BIT DATA WORD CONFIGURATION
Figure 1 indicates the 22-bit data format for two bytes of
data and 6 check bits.
A single IDT39C60 EDC unit, connected as shown in
Figure 2, provides all the logic needed for single bit error
correction and double bit error detection of a 16-bit data field.
The identification code 16/22 indicates 6 check bits are
required. The CBs pin is, therefore, a "Don't Care" and 102, 101,
100 = 000.
DATA
CHECK BITS
I BYTE1 I BYTEo I Co I Cl I C2 I C3 I C4 I Cs
15
87
0
2595 drw 04
Uses Modified Hamming Code 16/22
16 Data Bits with 6 Check Bits
Figure 1. 16-Blt Data Format
INPUT CHECK BITS
FOR 1S-BIT CONFIGURATION
A.
, - - - - - - - - - - - --------T-IE-T-~
Co
C1
C2
C3
C4
Cs Vcc
DATAo-15
DATAo-15
CBo CB1
CB2 CB3 CB4 CB5 CBs
IDT39CSO EDC
CODE ID
000
MULT
ERROR
SCo
SC1
SC2
SC3
SC4
SC5
SCs
,-------------V -------------/
So/Co
S2/C2
S4/C4
HIGH
SYNDROME/CHECK BIT OUTPUT
Figure 2. 16-Blt Configuration
Table 3 describes the operating modes available. The
output pin SCs, is forced high for either syndrome or check bits
since only 6 check bits are used for the 16/22 code.
Table 4 indicates the data bits participating in the check bit
generation. For example, check bit Co is the Exclusive-OR
function of the 8 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits are passed as stored in the PASSTHRU or
Diagnostic Generate Mode.
Syndrome bits are generated by an Exclusive-OR of the
generated check bits with the read check bits. For example,
SX is the XOR of check bits CX from those read with those
generated. Table 5 indicates the decoding of the six
syndrome bits to indicate the bit-in-errorfor a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.
In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or
multiple error detection, the data available as input to the Data
Out Latch is not defined.
Table 6 defines the bit definition for the Diagnostic Latch.
As defined in Table 3, several modes will use the diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SCo-s outputs. The Internal Mode substitutes the
indicated bit position for the external control signals.
8.10
7
II
IDT39C601-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Participating Data Blts(l)
Generated
0
Check Bits
Parity
Co
Even (XOR)
Cl
Even (XOR)
X
C2
Odd (XNOR)
X
Cs
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
1
2
3
X
X
X
X
X
4
6
7
X
X
X
X
X
X
X
5
X
X
8
9
X
X
10
X
X
X
X
X
X
12
13
X
X
14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
X
X
X
X
11
X
NOTE:
X
X
2595 tbl 05
1. The check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X· in the table.
Table 4. 16-Blt Modified Hamming Code - Check Bit Encode Chart
I Hex
Syndrome
Bits
.---Hex Ss S2 Sl
S5
S4
4
5
0
1
0
6
0
1
1
7
0
1
8
1
9
1
1
2
3
1
2
3
Data Bit
Internal Function
a
1
1
0
Diagnostic Check 8ito
1
a
1
So
a a 0
a a a 1
0 a 1 a
0 a 1 1
0
1 0 a
0
0
a
a
0
*
C4
C5
T
co
T
T
14
C1
T
T
M
T
2
8
T
C2
T
T
15
1
T
T
T
3
4
10
0
9
T
1
1
M
T
T
M
0
0
0
C3
T
T
M
0
0
1
T
5
T
M
A
1
0
1
0
T
6
11
12
8
1
0
1
1
1
T
T
C
1
1
0
0
T
7
13
T
D
1
1
0
1
M
T
T
M
E
1
1
1
0
0
T
T
M
F
1
1
1
1
T
M
M
NOTES:
* = No errors detected
1
Di
0
~~;-Q
16
:::I
o
Z
c
T
.£. . .
:::1-
cog.
(I)
!il'o
T
CB6 CBs CB4 CB3 CB2 CBl CBo D
0:::1"
o
o
:a
:a
T
1
CB6 CBs CB4 CB3 CB2 CBl CBo D
CB6CBsCB4CB3CB2CB1CBo D
CB6CBsCB4CB3CB2CB1CBo D
-(I)
_0
:::1"7'
~I»
~
-
5~
."
!e."O
a;
C
I»Ul
C)"O
:"'I
m
Q):T
cO
"'"
•
~
C)
tD
;;
g
a
cO
c
a0'
:::I
OEsc
r
5r 0'
(Q:::I"
ME
I-±-
IDT39C60
BYTE6AND7
sco so; so. SQ; sc;, sc,
o'81
OEsc
SCs SCs SC4 SC3 SC2 SCl
SCo
(I)
X
~ ~
sco
o Esc
~o
Z
I.£:-
IDT39C60
BYTE 2AND3
SCs SCs SC4 SC3 SC2 SCl
sco
OEsc
c:
Z
=t
IDT39C60
BYTE AND 1
o
SCs SCs SC4 SC3 SC2 SCl
sco
I
I
,.J
1---
I
MULT
ERROR
(I)
I.£:-
IDT39C60
BYTE4AND5
:::1":::1
"0
"0
r
cn~
...~16
... 16
16
~~
»
Z
~
g
m
IDT39C60/-1/AiB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Generated
Participating Data Blts(1)
Check Bits
Parity
Co
C1
C2
C3
C4
Cs
Cs
C7
Even (XOR)
0
Even (XOR)
X
Odd (XNOR)
X
Odd (XNOR)
X
1
2
3
X
X
X
X
X
4
X
7
X
X
X
X
6
X
X
X
Even (XOR)
5
X
8
9
X
X
10
X
X
X
X
X
X
Even (XOR)
Even (XOR)
X
X
X
X
X
X
X
X
Even (XOR)
X
X
X
X
X
X
X
X
13
X
X
X
14
15
X
X
X
X
X
12
X
X
X
11
X
X
X
X
X
X
X
X
X
X
X
X
2595tbl15
Participating Data Blts(1)
Generated
Check Bits
Parity
Co
C1
C2
C3
C4
Cs
Cs
C7
Even (XOR)
16
Even (XOR)
X
Odd (XNOR)
X
Odd (XNOR)
X
17
18
19
X
X
X
X
X
20
X
23
X
X
X
X
22
X
X
X
Even (XOR)
21
X
24
25
X
X
X
X
X
X
X
X
27
X
28
29
X
X
X
X
26
X
X
X
X
X
X
X
X
X
X
X
X
Even (XOR)
X
X
X
X
X
X
X
X
X
X
31
X
Even (XOR)
Even (XOR)
30
X
X
X
X
X
X
X
X
X
X
X
2595tb116
Participating Data Blts(1)
Generated
Check Bits
Parity
32
Co
C1
C2
C3
C4
Cs
Cs
C7
Even (XOR)
Even (XOR)
X
X
Odd (XNOR)
X
Odd (XNOR)
X
33
X
34
35
X
X
38
39
X
X
X
X
X
36
X
X
X
X
X
X
X
X
X
X
X
X
X
X
41
X
42
43
X
X
X
X
X
Even (XOR)
Even (XOR)
40
X
X
X
Even (XOR)
37
44
45
X
X
X
X
X
X
X
X
X
X
46
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
47
X
X
X
Even (XOR)
X
2595tbl17
Participating Data Blts(1)
Generated
Check Bits
Parity
48
Co
C1
C2
C3
C4
Cs
Cs
C7
Even (XOR)
X
Even (XOR)
X
Odd (XNOR)
X
Odd (XNOR)
X
49
X
50
51
X
X
52
54
55
X
X
X
X
X
X
X
Even (XOR)
X
X
53
X
X
X
X
X
X
X
X
X
X
X
Even (XOR)
X
X
X
X
X
X
X
NOTE:
1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an
57
X
Even (XOR)
Even (XOR)
56
58
60
61
X
59
X
X
X
X
X
X
X
X
X
X
X
62
X
X
X
X
X
X
X
X
X
X
X
X
X
63
X
X
X
X
ax· in the table.
2595tbl18
Table 13. 64-Blt Modified Hamming Code - Check Bit Encode Chart
8.10
15
II
IDT39C60/·1/AIB
16·BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Bit
Internal Function
Data Bit
0
Diagnostic Check Bito
31
Don't Care
Don't Care
Internal Function
1
Diagnostic Check Bit1
32-37
2
Diagnostic Check Bit2
38
3
Diagnostic Check Bit3
39
Don't Care
4
Diagnostic Check Bit4
40
Slice 4/5 -
CODE 100
5
Diagnostic Check Bits
41
Slice 4/5 -
CODE 101
6, 7
Don't Care
42
Slice 4/5 -
CODE 102
8
Slice 0/1 -
CODE 100
43
Slice 4/5 -
DIAG MODEo
9
Slice 0/1 -
CODE 101
44
Slice 4/5 -
DIAG MODE1
10
Slice 0/1 -
CODE 102
45
Slice 4/5 -
CORRECT
11
Slice 0/1 -
DIAG MODEo
46
Slice 4/5 -
PASSTHRU
12
Slice 0/1 -
DIAG MODE1
47
Don't Care
13
Slice 0/1 -
CORRECT
48-54
Don't Care
14
Slice 0/1 -
PASSTHRU
55
Diagnostic Check Bit?
15
Don't Care
56
Slice 6/7 -
CODE 100
16-23
Don't Care
57
Slice 6/7 -
CODE 101
24
Slice 213 -
CODE 100
58
Slice 6/7 -
CODE 102
25
Slice 213 -
CODE 101
59
Slice 6/7 -
DIAG MODEo
26
Slice 213 -
CODE 102
60
Slice 6/7 -
DIAG MODE1
27
Slice 213 -
DIAG MODEo
61
Slice 6/7 -
CORRECT
28
Slice 213 -
DIAG MODE1
62
Slice 6/7 -
PASSTHRU
29
Slice 213 -
CORRECT
63
Don't Care
30
Slice 213 -
PASSTHRU
Diagnostic Check Bit6
2595tbl20
2595 tbl19
Table 14. Diagnostic Latch Loading - 64·Bit Format
Some multiple errors will cause a data bit to be inverted.
For example, in the 16-bit mode where bits 8 and 13 are in
error, the syndrome 111100 (So, S1, S2, S3, S4, S5) is produced. The bit-in-error decoder receives the syndrome 11100
(So, S1, S2, S3, S4) which it decodes as a single error in data
bit 0 and inverts that bit. Figure 8 indicates a method for
inhibiting correction when a multiple error occurs.
DATA
IDT39C60
ERROR
CHECK BiTS
CORRECT
CORRECT
MULT
ERROR
2595 drw 11
Figure 8. Inhibition of Data Modification
8.10
16
IDT39C60/·1/AIB
16·BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL EQUATIONS
The following equations and tables describe in detail how
the output values of the IOT39C60 EOC are determined as a
function of the value of the inputs and the internal states. Be
sure to carefully read the following definitions of symbols
before examining the tables.
DEFINITIONS
01 f- OATAI if LEIN is HIGH or the output of bit I of the Oata Input Latch if LEIN is LOW
CI f- CBI if LEIN is HIGH or the output of bit I of the Check Bit Latch if LEIN is LOW
OLI f- Output of bit I of the Oiagnostic Latch
SI f- Internally generated syndromes (same as outputs of SCI if outputs enabled)
PA f- 00 EB 01 EB 02 EB 04 EB 06 EB 08 EB 010 EB 012
PB f- 00 EB 01 EB 02 EB 03 EB 04 EB 05 EB 06 EB 07
PC f- 08 EB 09 EB 010 EB 011 EB 012 EB 013 EB 014 EB 015
PO f- 00 EB 03 EB 04 EB 07 EB 09 EB 010 EB 013 EB 015
PE f- 00 EB 01 EB 05 EB 06 EB 07 EB 011 EB 012 EB 013
PF f- 02 EB 03 EB 04 EB 05 EB 06 EB 014 EB 015 EB 07
PG1 f- 00 EB 04 EB 06 EB 07
PG2 f- 01 EB 02 EB 03 EB 05
PG3 f- 08 EB 09 EB 011 EB 014
PG4 f- 010 EB 012 EB 013 EB 015
Error Signals
ERROR: f- (86' (101 + 102)) • S5' S4' S3' 52' 81· SO + GENERATE + INITIALIZE + PASSTHRU
MULT ERROR:
(16 and 32·Bit Modes) f- ((S6' 101) EB S5 EB S4 EB S3 EB S2 EB S1 EB SO) (ERROR) + TOME + GENERATE +
PASSTHRU + INITIALIZE
MULT ERROR: (64·Bit Modes) f- TOME + GENERATE + PASSTHRU + INITIALIZE
I Hex
Hex
a
8
1
9
2
A
3
4
B
C
5
0
6
E
F
7
5yndrome(1, 2)
Bits
52
51
50
a
a
a
a
a
a
a
1
1
a
1
a
a
a
1
1
a
1
1
1
a
a
a
a
a
56
55
54
53
1
a
a
a
1
2
a
a
a
a
1
1
1
a
1
1
3
a
a
a
1
1
1
1
1
1
1
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
5
4
a
1
1
a
a
1
a
a
1
1
1
1
a
1
1
1
1
7
6
1
1
1
1
1
1
1
1
a
a
a
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTES:
25951b121
1. 56,55, ... 50 are internal syndromes except in Modes 010,100,101,110,111 (CODE 102, 101, 100). In these modes, the syndromes are input over the
check bit lines. 56 f- C6, 55 f- C5, '" 51 f- Cl, 50 f- Co.
2. The 56 internal syndrome is always forced to 0 in CODE 10000.
Table 15. TOME (Three or More Errors)
Generate
CODE 100-2
Mode (Check Bits)
000
010
011
100
101
110
111
SCo~
PG2 EB PG3
PGl EB PG3
PG2 EB PG4
EB CBo
PG2 EB PG3
PG2 EB PG3
PG1 EB PG4
PGl EB PG4
PA
PA
PA
PlJ
PO
PE
PA
PO
PE
SC1~
PA
PA
SC2~
151)
151)
SC3~
P'E
f5E
PA EB CBl
PO EB CB2
PE EB CB3
f5E
PO
PE
SC4~
SCs~
PF
PC
PF
PC
PF EB CB4
PC EB CBs
PF
PC
PF
PC
PF
PC
PF
PC
SCs~
1
PB
PC EB CBs
PB
PB
PB
PB
Table 16. Generate Mode (Check Bits)
8.10
25951b122
17
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Detect and Correct
CODE ID0-2
011
Modes (Syndromes)
000
010
SCOf-
PG2 EEl PG3
EEl Co
PG1 EEl PG3
EEl Co
(1)
PG2 EEl PG4
EEl CBo
100
101
110
111
PG2 EEl PG3
EEl Co
PG2 EEl PG3
PG1 EEl PG4
PG1 EEl PG4
PA
SC1 f-
PA EEl C1
PA EEl C1
PA EEl CB1
PA EEl C1
PA
PA
SC2f-
'PO EEl C2
PE EEl C3
'J5U EEl C2
PE EEl C3
PO EEl CB2
Plj EEl C2
PO
PO
PO
PE EEl CB3
fSE EEl C3
PE
PE
PE
SC3fSC4f-
PF EEl C4
PF EEl C4
PF EEl CB4
PF EEl C4
PF
PF
PF
SCSfSC6f-
PC EEl Cs
PC EEl Cs
PC EEl CBs
PC EEl Cs
1
PB EEl C6
PC EEl CB6
PB
PC
PB
PC
PB EEl C6
PC
PB EEl C6
NOTE:
1. In CODE ID2-o 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
2595 tbl 23
Table 17. Detect and Correct Modes (Syndromes)
CODE ID0-2
Diagnostic Detect
011
and Correct Mode
000
010
SCOf-
PG2 EEl PG3
EEl OLo
PG1 EEl PG3
EEl OLo
SC1 f-
PA EEl OL1
PA EEl OL1
SC2f-
Plj EEl OL2
SC3f-
PE EEl OL3
'PO EEl OL2
PE EEl OL3
100
101
110
111
PG2 EEl PG4
EEl CBo
PA EEl CB1
PG2 EEl PG3
EEl OLo
PG2 EEl PG3
PG1 EEl PG4
PG1 EEl PG4
PA EEl OL1
PA
PA
PA
PO EEl CB2
Plj EEl OL2
PE EEl CB3
P'E EEl OL3
PO
PE
PO
PE
PO
PE
PF
PC
PB EEl OL6
PF
PC
(1)
SC4f-
PF EEl OL4
PF EEl OL4
PF EEl CB4
PF EEl OL4
PF
SCSf-
POL EEl OLs
PC EEl OLs
PC EEl CBs
PC EEl OLs
PC
SC6f-
1
PB EEl OL6
PC EEl CB6
PB
PB
NOTE:
1. In CODE ID2-o 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
PB EEl OL7
2595 tbl24
Table 18. Diagnostic Detect and Correct Mode
CODE ID0-2
Diagnostic
011
Generate Mode
000
010
100
101
110
111
SCOf-
OLo
OLo
CBo
OLo
SC1 fSC2f-
OL1
OL2
OL1
OL2
CB1
CB2
OL1
OL2
SC3f-
OL3
OL3
SC4f-
OL4
OL4
CB3
CB4
OL3
OL4
SCSf-
OLs
OLs
CBs
OLs
SC6f-
1
OL6
CB6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OL6
1
1
1
1
1
1
OL7
(1)
NOTE:
1. In CODE 102-0011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
2595 tbl 25
Table 19. Diagnostic Generate Mode
CODE 100-2
PASSTHRU
011
Mode
000
010
100
101
110
111
SCrif-
Co
Co
CBo
Co
1
1
1
SC1 f-
C1
C1
CB1
C1
SC2f-
C2
C2
CB2
C2
1
1
1
1
1
1
SC3f-
C3
C3
C4
Cs
C3
C4
Cs
CB3
SC4fSCSf-
CB4
CBs
C4
Cs
1
1
1
SC6f-
1
C6
CBs
1
1
1
1
1
C6
1
1
1
C6
(1)
NOTE:
1. In CODE ID2-o 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
2595 tbl 26
Table 20. PASSTHRU Mode
8.10
18
IDT39C60/·1/AiB
16·BIT CMOS DETECTION AND CORRECTION UNIT
52
51
0
0
0
55
54
53
1
1
0
1
1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
-
-
5
-
11
14
-
-
1
2
6
8
-
12
C2
C1
0
0
1
Cs
C5
C4
C3
0
1
0
0
0
1
0
1
8
11
12
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
14
-
-
-
-
5
-
-
-
1
2
6
-
-
-
3
7
-
0
4
-
0
1
1
0
-
3
7
9
13
15
-
0
0
4
-
10
-
-
-
1
0
9
13
15
1
1
10
-
-
2595 tbl 27
NOTE:
1. Unlisted S combinations are no correction.
NOTE:
1. Unlisted Cn combinations are no correction.
Table 21. CODE ID2-<1 = 000
Table 22. CODE ID2-<1
52
51
0
0
0
5s
55
54
53
1
1
0
1
1
Co
Cs
C5
C4
C3
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
=010
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
-
-
-
5
1
2
6
-
3
7
0
4
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
-
-
-
5
-
11
14
-
C2
C1
1
2
6
0
0
-
11
14
-
0
1
8
12
-
-
-
1
0
9
13
15
-
-
1
1
10
-
-
-
-
-
3
7
0
4
-
9
10
13
15
-
-
-
-
12
-
2595tbl29
NOTE:
1. Unlisted S combinations are no correction.
Table 24. CODE ID2-<1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
-
C2
C1
0
0
-
-
-
5
-
11
14
0
1
-
1
2
6
8
12
-
1
0
3
7
9
13
15
1
-
-
1
0
4
-
10
-
-
2595 1b131
NOTE:
1. Unlisted Cn combinations are no correction.
Table 25. CODE ID2-<1
-
NOTE:
1. Unlisted Cn combinations are no correction.
Table 23. CODE ID2-<1 = 011
Co
Cs
C5
C4
C3
2595 tbl 28
0
0
0
0
8
C2
C1
0
0
0
1
1
0
1
1
Co
Cs
C5
C4
C3
0
1
0
0
0
0
1
0
0
-
-
0
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
1
0
1
0
-
11
14
8
12
-
-
-
5
1
2
6
-
3
7
9
13
15
0
4
-
10
-
-
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
-
5
C2
C1
0
0
-
11
14
1
8
12
-
-
-
-
0
1
2
6
1
1
0
9
13
15
-
-
10
-
-
-
3
4
7
1
-
NOTE:
1. Unlisted en combinations are no correction.
Table 27. CODE ID2-<1
8.10
0
1
0
1
1
0
1
0
1
1
Table 26. CODE ID2-<1
Co
Cs
C5
C4
C3
=100
NOTE:
1. Unlisted Cn combinations are no correction.
=101
2595 1b130
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
2595lbl32
=110
II
2595tbl33
= 111
19
IDT39C60/·1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25°C; f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Vee
Rating
Terminal Voltage
with Respect
to Ground
Power, Supply
Voltage
Com'l.
Mil.
-0.5 to
Vee + 0.5
-0.5 to
Vee + 0.5
Unit
V
-0.5 to +7.0
-0.5 to +7.0
V
Operating
. Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
30
30
mA
TA
Parameter(1)
Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = OV
5
pF
COUT
Output Capacitance
VOUT= OV
7
Symbol
NOTE:
1. This parameter is sampled and not 100% tested.
pF
25951bl35
NOTE:
25951bl 34
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This Is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
VLC =0.2V; VHC = Vcc - 0.2V
Symbol
Test Condltlons(1)
Parameter
VIH
Input HIGH Level
VIL
Input LOW Level
Guaranteed Logic HIGH Level(4)
Guaranteed Logic LOW Level l4j
IIH
Input HIGH Current
Vee = Max., VIN = Vee
ilL
Input LOW Current
Vee = Max., VIN = GND
VOH
Output HIGH Voltage
Vee = Min.
VOL
Output LOW Voltage
Vee= Min.
Off State (High Impedance)
Vee= Max.
Output Current
los
Output Short Circuit Current
Vee = Max., VOUT = OV(3)
Typ.(2)
O.S
V
-
0.1
10
fJA
fJA
V
-
-
Unit
-
-0.1
-10
VHC
Vec
-
10H = -6mA MIL.
2.4
4.3
-
10H = -SmA COM'L.
2.4
4.3
10l = 300fJA
-
GND
Vle
0.3
0.5
V
-
10l = SmA COM'L.
-
0.3
0.5
Vo= OV
-
-0.1
-20
Va = Vee (Max.)
-
0.1
20
-20
-
-
NOTES:
1. For conditions shown as Max. or Min. use appropriate value specified under DC Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels should only be static tested in a noise-free environment. Guaranteed by design.
8.10
Max.
-
2.0
10H = -300fJA
1m = SmA MIL.
loz
Min.
V
fJA
mA
25951bl36
20
IDT39C60/·1/AiB
16-BIT CMOS DETECnON AND CORREcnON UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd.)
Commercial: TA = O°C to +70°C, Vcc ... 5.0V ± 5%; Military: TA ... -55°C to +125°C, VCC ... 5.0V ± 10%
VLC = 2.0V·, VHC = VCC - 0 2V
Min.
Typ.(2)
Max.
Unit
Iceo
Quiescent Power Supply Current
(CMOS) Inputs
Vee .. Max.
VIN .. Vec or GND
fop .. 0
-
3.0
5.0
rnA
leeT
Quiescent Input Power Supply
Current (per Input @ TTL High)(3)
Vee .. Max., VIN .. 3.4V, fop .. 0
-
0.3
2.0
mAl
Input
IceD
Dynamic Power Supply Current
Vee .. Max.
VIN .. Vee or GND
Outputs Open, 'OT: .. L
MIL.
-
5.0
8.5
mAl
MHz
COM'L.
7.0
Total Power Supply Current(4)
Vee .. Max., fop .. 10MHz
Outputs Open, 'OT: .. L
50% Duty Cycle
VIN .. Vee or GND
Vee ... Max., fop .. 10MHz
Outputs Open, 'OT: .. L
50% Duty Cycle
VIN .. 3.4V, VIN ... 0.4V
-
5.0
Icc
53
90
-
53
75
60
100
60
85
Symbol
Test Condltlons(1)
Parameter
NOTES:
1.
2.
3.
4.
MIL.
COM'L.
MIL.
COM'L.
rnA
2595 tbl37
For conditions shown as Max. or Min. use appropriate value specified under DC Electrical Characteristics.
Typical values are at Vee - 5.0V, +25°C ambient and maximum loading.
lecT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out leeo, then dividing by the total number of inputs.
Total Supply Current is the sum ofthe Quiescent Current and the DynamiC Current (at either CMOS orTTLinputlevels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc - leeo + leeT (NT X DH) + IceD (fop)
DH - Data duty cycle TTL high period (VIN - 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fop .. Operating frequency
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into
account when applying high-speed CMOS products to the
automatic test environment. Large output currents are being
switched in very short periods and proper testing demands
that test set-ups have minimized inductance and guaranteed
zero voltage grounds. The techniques listed below will assist
the user in obtaining accurate testing results:
1) All input pins should be connected to a voltage potential
during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical.
Each physical. set-up has different electrical char·
acteristics and it is recommended that various decoupling
capacitor sizes be experimented with. Capacitors should
be pOSitioned using the minimum lead lengths. They
should also be distributed to decouple power supply lines
and be placed as close as possible to the OUT power pins.
3) Device grounding is extremely critical for proper device
testing. The use of mUlti-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to the OUT interface board and wiring
unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for
power wiring, with twisted pairs being recommended for
minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To
allow for testing and hardware-induced noise, lOT
recommends using VIL ~ OV and VIH ~ 3V for AC tests.
8.10
21
II
IDT39C60f-1fAlB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
16·BIT CMOS DETECTION AND CORRECTION UNIT
lOT 39C60B AC ELECTRICAL CHARACTERISTICS
Guaranteed Commercial Range Performance: Temperature range: O°C to +70°C; VCC
The signals switch between OV and 3V with signal measured at 1.SV level.
MAXIMUM PROPAGATION DELAYS CL= 50pF
=
S.OV ± S%
To Output
From Input
SCo-s
~
MO[TERRoR
Unit
18
20
ns
DATAo-15
18
DATA0-15
·25(1)
CB0-6 (CODE ID = 000, 011)
12
22
17
20
ns
CB0-6 (CODE ID= 010,100,101,110,111)
12
16
17
20
ns
-
-
14
19
ns
15
-
CORRECT
(Not Internal Control Mode)
-
22
-
-
ns
DIAG MODE and PASSTHRU
(Not Internal Control Mode)
20
22
16
19
ns
'GENERATE
f
\.
20
22
22
24
ns
LEIN
From latched to transparent
f
20
28
20
22
ns
LEoUT
From latched to transparent
f
-
11
-
-
ns
LEOIAG
From latched to transparent
f
20
28
20
22
ns
Internal Control Mode: LEolAG
From latched to transparent
f
24
33
24
27
ns
33
24
27
ns
CODE 10
24
Internal Control Mode: DATAo-15
Via Diagnostic Latch
NOTE:
1. DATAIN to corrected DATAourmeasurement requires timing as shown below.
2595 tbl38
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latching Data)
Set-upTime
Hold Time
Unit
5
ns
5
3
3
24
2
ns
\.
\.
\.
\.
\.
\.
21
0
ns
21
0
ns
22
0
ns
22
22
0
0
ns
ns
25
0
ns
\.
28
0
ns
5
3
From Input
DATAo-15
\.
CBo-6 (not applic. to CODE 10 = 11)
\.
\.
DATAo-15
CB0-7 (CODE 10 = 000,011)
CBO-7 (CODE 10 = 010,100,101,110,111)
If
CORRECT
DIAG MODE
PASSTHRU
CODE 101,0
If
LEIN
LEIN
LEoUT
LEolAG
DATAo-15
ns
ns
2595tbl39
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = SpF and measured to O.SV change of output voltage level. Test performed with
CL = SOpF and correlated to CL = SpF.
From Input
OE Byteo, 1
OEsc
Enable
\.
\.
Disable
f
f
To Output
Enable
Max.
Disable
Max.
Unit
DATo-15
12
10
ns
SCO-7
12
10
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
.I\,
(Positive-going pulse)
8.10
I
I
Min.
8
ns
I
I
2595tbl40
ns
2595tbl41
22
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60B AC ELECTRICAL CHARACTERISTICS
Guaranteed Military Range Performance: Temperature range: -55°C to +125°C; VCC
The inputs switch between OV to 3V with signal measured at the 1.5V level.
= 5.OV ± 10%
MAXIMUM PROPAGATION DELAYS CL =50pF
To Output
E"R"ROR"
MD[TERRoR
Unit
22
DATAG-15
30(1)
22
25
ns
14
26
20
24
ns
14
19
20
24
ns
-
14
19
ns
15
-
-
CORRECT
(Not Internal Control Mode)
-
20
-
-
ns
DIAG MODE and PASSTHRU
(Not Internal Control Mode)
24
26
19
21
ns
From Input
SCo-s
DATAo-15
CBO-6 (CODE ID
=000, 011)
CBO-6 (CODE ID= 010,100,101,110,111)
/
"\.
GENERATE
24
29
26
29
ns
LEIN
From latched to transparent
/
24
34
24
26
ns
LEoUT
From latched to transparent
/
-
13
-
-
ns
Internal Control Mode: LEOIAG
From latched to transparent
/
24
34
24
26
ns
LEDIAG
From latched to transparent
/
29
40
29
32
ns
29
40
29
32
ns
CODE ID
Internal Control Mode: DATAo-15
Via Diagnostic Latch
2595tbl42
NOTE:
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
MINIMUM SET·UPAND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latching Data)
From Input
DATAo-15
CB0-6 (not applic. to CODE ID = 11)
DATAo-15
CBo-7 (CODE ID = 000, 011)
CBo-7 (CODE ID = 010,100,101,110,111)
1/
CORRECT
DIAG MODE
PASSTHRU
CODE 101,0
1/
LEIN
"\.
"\.
"\.
"\.
"\.
"\.
"\.
"\.
"\.
"\.
LEIN
LEoUT
Set-up Time
Hold Time
Unit
6
4
ns
6
4
ns
29
2
ns
25
0
ns
25
0
ns
-
26
26
26
30
LEolAG
ns
ns
0
ns
-
34
DATAo-15
ns
0
0
ns
4
6
ns
2595tbl43
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to O.5V change of output voltage level. Test performed with
CL = 50pF and correlated to CL = 5pF.
From Input
OE Byteo, 1
UE'sc
Enable
"\.
"\.
Disable
/
/
To Output
Enable
Max.
Disable
Max.
Unit
DATo-15
15
12
ns
SCo-7
15
12
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEDIAG
.F\"
(Positive-going pulse)
8.10
I
I
Min.
10
ns
I
I
25951bl44
ns
2595tbl45
23
II
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60A AC ELECTRICAL CHARACTERISTICS
Guaranteed Commercial Range Performance: Temperature range: O°C to +70°C; Vee
The signals switch between OV and 3V with signal measured at 1.5V level.
= 5.0V ± 5%
MAXIMUM PROPAGATION DELAYS CL = 50pF
To Output
From Input
SCG-S
"ER"ROR"
MOLt ERROR
Unit
20
23
ns
DATAo-15
20
DATA0-15
30(1)
CB0-6 (CODE ID = 000, 011)
14
25
20
23
ns
CB0-6 (CODE ID= 010,100,101,110,111)
14
18
20
23
ns
-
33
18
23
ns
15
-
CORRECT
(Not Internal Control Mode)
-
20
-
-
ns
DIAG MODE and PASSTHRU
(Not Internal Control Mode)
22
25
18
21
ns
f
GENERATE
\.
CODE ID
23
28
25
28
ns
LEIN
From latched to transparent
f
22
32
22
25
ns
LEoUT
From latched to transparent
f
-
13
-
-
ns
LEOIAG
From latched to transparent
f
22
32
22
25
ns
Internal Control Mode: LEolAG
From latched to transparent
f
28
38
28
31
ns
28
38
28
31
ns
Internal Control Mode: DATAo-15
Via Diagnostic Latch
NOTE:
2595tbl46
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
MINIMUM SET·UPAND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latching Data)
From Input
DATAo-15
\.
CB0-6 (not applic. to CODE ID = 11)
\.
\.
\.
\.
\.
\.
\.
\.
\.
DATAo-15
CBO-7 (CODE ID = 000, 011)
CBo-7 (CODE ID = 010,100,101,110,111)
If
CORRECT
DIAG MODE
PASSTHRU
CODE ID1,O
If
LEIN
DATAo-15
LEIN
LEoUT
LEolAG
Set-up Time
Hold Time
Unit
5
3
ns
5
3
ns
24
2
ns
21
0
ns
21
0
ns
22
0
ns
22
22
0
0
ns
ns
25
0
ns
28
5
0
3
ns
ns
2595tbl47
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to O.5V change of output voltage level. Test performed with
CL
= 50pF and correlated to CL = 5pF.
From Input
OE Byteo, 1
OEsc
Enable
\.
\.
Disable
f
f
To Output
Enable
Max.
Disable
Max.
DATo-15
24
21
ns
SCo-7
24
21
ns
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
(Positive-going pulse)
I
Min.
12
Unit
I
I
2595 tbl48
ns
2595tbl49
8.10
24
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60A AC ELECTRICAL CHARACTERISTICS
Guaranteed Military Range Performance: Temperature range: -55°C to + 125°C; Vcc = 5.0V ± 10%
The inputs switch between OV to 3V with signal measured at the 1.5V level.
MAXIMUM PROPAGATION DELAYS CL = 50pF
To Output
From Input
SC0-6
ERROR
MOLT ERROR
Unit
24
27
ns
ns
DATAO-15
22
DATA0-15
35(1)
CBo-6 (CODE 10 = 000, 011)
17
25
24
27
CBD--6 (CODE 10 = 010,100,101,110,111)
17
20
24
27
ns
-
28
21
25
ns
f
GENERATE
-
20
-
CORRECT
(Not Internal Control Mode)
-
25
-
-
ns
DIAG MODE and PASSTHRU
(Not Internal Control Mode)
25
28
21
24
ns
\.
26
31
28
31
ns
LEIN
From latched to transparent
f
24
37
26
29
ns
LEoUT
From latched to transparent
f
-
16
-
-
ns
LEolAG
From latched to transparent
f
24
37
26
29
ns
Internal Control Mode: LEolAG
From latched to transparent
f
30
43
32
35
n3
30
43
32
35
ns
CODE 10
Internal Control Mode: DATAo-15
Via Diagnostic Latch
NOTE:
2595 tbl 50
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latching Data)
From Input
DATAO-15
\.
CB0-6 (not applic. to CODE 10 = 11)
\.
\.
\.
\.
\.
\.
\.
\.
\.
DATAo-15
CBO-7 (CODE 10 = 000, 011)
CBO-7 (CODE 10 = 010,100,101,110,111)
If
CORRECT
DIAG MODE
PASSTHRU
CODE 101,0
If
LEIN
DATAo-15
LEIN
LEoUT
LEolAG
Set-up Time
Hold Time
Unit
5
3
ns
5
3
ns
27
2
ns
24
0
ns
24
0
ns
25
0
ns
25
25
0
0
ns
ns
28
0
0
ns
30
5
ns
ns
3
2595 Ibl 51
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to O.5V change of output voltage level. Test performed with
CL
= 50pF and correlated to CL = 5pF.
From Input
OE Byteo, 1
OEsc
Enable
\.
\.
Disable
f
f
To Output
Enable
Max.
Disable
Max.
DATo-15
24
21
ns
SC0-7
24
21
ns
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
(Positive-going pulse)
I
Min.
12
I
I
Unit
2595tbl52
ns
2595 tbl 53
8.10
25
II
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60-1 AC ELECTRICAL CHARACTERISTICS
Guaranteed Commercial Range Performance: Temperature range: O°C to +70°C; Vee = 5.0V ± 5%
The signals switch between OV and 3V with signal measured at 1.5V level.
MAXIMUM PROPAGATION DELAYS CL = 50pF
To Output
SC0-6
"EFfFfOFf
MOLt ERROR
25
50
ns
23
47
ns
DATAo-15
28
DATA0-15
52(1)
C8o-e (CODE ID = 000, 011)
23
50
C8o-e (CODE ID= 010,100,101,110,111)
28
34
29
34
ns
GENERATE
-
63
36
55
ns
35
-
CORRECT
(Not Internal Control Mode)
-
45
-
-
ns
DIAG MODE(Not Internal Control Mode)
PASSTHRU(Not Internal Control Mode)
50
36
78
44
59
29
75
46
ns
ns
From Input
f
\.
CODE ID
Unit
61
90
60
80
ns
LEIN
From latched to transparent
f
39
72
39
59
ns
LEoUT
From latched to transparent
f
-
31
-
-
ns
LEOIAG
From latched to transparent
f
45
78
45
65
ns
Internal Control Mode: LEolAG
From latched to transparent
f
67
96
66
86
ns
67
96
66
86
ns
Internal Control Mode: DATAo-15
Via Diagnostic Latch
NOTE:
2595tbl54
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
Data)
(Latchln~
From Input
DATAo-15
\.
C80-6 (not applic. to CODE ID = 11)
\.
\.
\.
\.
\.
\.
\.
\.
\.
DATAo-15
C8o-7 (CODE ID = 000, 011)
C8o-7 (CODE ID = 010 100 101 110 111)
If
CORRECT
DIAG MODE
PASSTHRU
CODE ID1,O
If
LEIN
LEIN
LEoUT
DATAo-15
LEolAG
Set-upTime
Hold Time
Unit
6
7
ns
5
6
ns
34
5
ns
35
0
ns
27
0
ns
26
1
ns
69
26
a
0
ns
ns
81
0
ns
51
5
ns
6
8
ns
2595tbl55
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to O.5V change of output voltage level. Test performed with
CL = 50pF and correlated to CL = 5pF.
From Input
Enable
OE 8yteo, 1
\.
OEsc
\.
Disable
f
f
To Output
Enable
Max.
Disable
Max.
DATo-15
30
30
ns
SCO-7
30
30
ns
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
. (Positive-going pulse)
I
Min.
15
Unit
I
I
2595tbl56
ns
2595 tbl57
8.10
26
IDT39C60/-1/AlB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60-1 AC ELECTRICAL CHARACTERISTICS
Guaranteed Military Range Performance: Temperature range: -SSOC to + 12SoC; VCC = S.OV ± 10%
The inputs switch between OV to 3V with signal measured at the 1.SV level.
MAXIMUM PROPAGATION DELAYS CL = 50pF
To Output
From Input
SC0-6
DATAo-15
31
DATA0-15
59(1)
CBo--£ (CODE ID = 000, 011)
25
55
CBo--£ (CODE ID= 010,100,101,110,111)
ERROR
MuLTERROR
28
56
ns
25
50
ns
Unit
30
38
31
37
ns
./
-
63
36
55
ns
\.
38
-
-
CORRECT
(Not Internal Control Mode)
-
49
-
-
ns
DIAG MODE(Not Internal Control Mode)
PASSTHRU(Not Internal Control Mode)
58
39
89
51
65
34
90
54
ns
ns
GENERATE
69
100
68
90
ns
LEIN
From latched to transparent
CODE ID
./
39
82
43
66
ns
LEoUT
From latched to transparent
./
-
33
-
-
ns
LEolAG
From latched to transparent
./
50
88
49
72
ns
Internal Control Mode: LEolAG
From latched to transparent
./
75
106
74
96
ns
75
106
74
96
ns
Internal Control Mode: DATAo-15
Via Diagnostic Latch
2595 tbl5B
NOTE:
1. DATAIN to corrected DATAourmeasurement requires timing as shown below.
MINIMUM SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latchlna Datal
From Input
DATAo-15
CBo--£ (not applic. to CODE ID = 11)
DATAo-15
CBO-7 (CODE 10 = 000, 011)
CBO-7 (CODE 10 = 010 100 101 110 111)
If
CORRECT
DIAG MODE
PASSTHRU
CODE 101,0
1./
LEIN
\.
\.
\.
\.
\.
\.
\.
\.
\.
\.
LEIN
LEoUT
LEolAG
DATAo-15
Set-up Time
Hold Time
Unit
7
7
ns
5
7
ns
39
5
ns
38
0
ns
30
0
ns
28
1
ns
84
30
0
0
ns
ns
89
0
ns
59
5
ns
7
9
ns
2595tbl59
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = SpF and measured to O.SV change of output voltage level. Test performed with
CL = SOpF and correlated to CL = SpF.
From Input
OE Byteo, 1
OEsc
Enable
Disable
To Output
Enable
Max.
Disable
Max.
Unit
\.
\.
./
./
DAT0-15
35
35
ns
SC0-7
35
35
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
(Positive·going pulse)
8.10
I
Min.
15
I
I
ns
2595 tbl60
ns
2595 tbl61
27
II
IDT39C60/·1/AiB
16·BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT 39C60 AC ELECTRICAL CHARACTERISTICS
Guaranteed Commercial Range Performance: Temperature range: O°C to +70°C; Vee ... 5.0V ± 5%
The signals switch between OV and 3V with signal measured at the1.5V level.
MAXIMUM PROPAGATION DELAYS CL .. 50pF
To Output
SC~
From Input
E"Ffmm
MOLT ERROR
32
50
ns
29
47
ns
DATA0-15
32
DATA0-15
65(1)
CB~ (CODE ID = 000, 011)
28
56
28
45
29
34
ns
-
63
36
55
ns
35
-
-
CORRECT
(Not Internal Control Mode)
-
45
-
-
ns
DIAG MODE(Not Internal Control Mode)
PASSTHRU(Not Internal Control Mode)
50
36
78
44
59
29
75
46
ns
ns
CB~
(CODE ID .. 010,100,101,110,111)
GENERATE
./
\.
CODE ID
Unit
61
90
60
80
ns
LEIN
From latched to transparent
./
39
72
39
59
ns
LEoUT
From latched to transparent
./
-
31
-
-
ns
LEOIAG
From latched to transparent
./
45
78
45
65
ns
Internal Control Mode: LEolAG
From latched to transparent
./
67
96
66
86
ns
67
96
66
86
ns
Internal Control Mode: DATA0-15
Via Diagnostic Latch
NOTE:
2595tbl62
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
-
MINIMUM SET UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latchln!1 Data)
From Input
DATA0-15
\.
CBo-6 (not applic. to CODE ID = 11)
\.
DATA0-15
\.
\.
\.
CBO-7 (CODE ID = 000, 011)
CBO-7 (CODE ID = 010 100 101 110 111)
CORRECT
LEoUT
Set-up Time
Hold Time
Unit
6
7
ns
5
6
ns
44
5
ns
35
a
a
ns
27
ns
If
\.
26
1
ns
69
26
ns
ns
81
a
a
a
ns
1./
\.
\.
\.
\.
51
5
ns
6
8
DIAG MODE
PASSTHRU
CODE ID1.0
LEIN
LEIN
DATA0-15
LEOIAG
ns
2595tbl63
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to O.5V change of output voltage level. Test performed with
CL = 50pF and correlated to CL ... 5pF.
Enable
Disable
To Output
Enable
Max.
Disable
Max.
OE Byteo, 1
\.
./
DATo-15
30
30
ns
OEsc
\.
./
SCo-7
30
30
ns
From Input
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
(Positive-going pulse)
I
Min.
15
Unit
I
I
2595tbl64
ns
2595 tbl65
8.10
28
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lOT 39C60 AC ELECTRICAL CHARACTERISTICS
Guaranteed Military Range Performance: Temperature range: -55°C to + 125°C; Vee = 5.0V ± 10%
The inputs switch between OV to 3V with signal measured at the 1.5V level.
MAXIMUM PROPAGATION DELAYS CL", 50pF
To Output
From Input
SC0-6
amoR"
MOLT ERROR
Unit
36
56
ns
DATAo-15
35
DATA0-15
73(1)
CBo-6 (CODE 10 '" 000, 011)
30
61
31
50
ns
CBo-6 (CODE 10", 010, 100,101,110, 111)
30
50
31
37
ns
-
63
36
55
ns
38
-
CORRECT
(Not Internal Control Mode)
-
49
-
-
ns
DIAG MODE(Not Internal Control Mode)
PASSTHRU(Not Internal Control Mode)
58
39
89
51
65
34
90
54
ns
ns
f
"\.
GENERATE
CODE 10
69
100
68
90
ns
LEIN
From latched to transparent
f
44
82
43
66
ns
LEoUT
From latched to transparent
f
-
33
-
-
ns
LEolAG
From latched to transparent
f
50
88
49
72
ns
Internal Control Mode: LEolAG
From latched to transparent
f
75
106
74
96
ns
75
106
74
96
ns
Internal Control Mode: DATAo-15
Via Diagnostic Latch
NOTE:
1. DATAIN to corrected DATAouTmeasurement requires timing as shown below.
2595 tbl 66
MINIMUM SET·UPAND HOLD TIMES RELATIVE TO LATCH ENABLES
To Input
(Latching Data)
From Input
Set-up Time
Hold Time
Unit
7
7
ns
5
7
ns
50
5
ns
CBO-7 (CODE 10 '" 000, 011)
"\.
"\.
"\.
"\.
38
0
ns
CBO-7 (CODE 10 '" 010 100 101 110 111)
"\.
30
0
ns
If
"\.
28
1
ns
84
30
0
0
ns
ns
ns
If
"\.
"\.
"\.
"\.
DATAo-15
CBo-6 (not applic. to CODE 10 '" 11)
DATA0-15
CORRECT
DIAG MODE
PASSTHRU
CODE 101,0
LEIN
LEIN
LEoUT
LEolAG
DATAo-15
89
0
59
5
7
9
, ,. ," EI
ns
ns
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
Output tests specified with CL = 5pF and measured to 0.5V change of output voltage level. Test performed with
CL = 50pF and correlated to CL = 5pF.
From Input
OE Byteo, 1
OEsc
Enable
"\.
"\.
Disable
f
f
To Output
Enable
Max.
Disable
Max.
Unit
DATo-15
35
35
ns
SC0-7
35
35
I
MINIMUM PULSE WIDTHS
LEIN, LEoUT, LEOIAG
A
(Positive-going pulse)
I
Min.
15
ns
I
I
2595tbl67
ns
2595tbl69
8.10
29
IDT39C60/-1/A1B
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
IDT39C60 - DATAIN TO CORRECTED
DATAoUT TIMING (Two cycles shown)
OEBYTE
J.
"
~2-
/
Timing Parameter
From
To
-~/
__~____,,~____3'~1'-~~_~11~~~,~~",~~=~_
DATA Bus
DATAIN
4
Min.!
Max.
1.-0EBYTE = High to DATAoUT Disabled
2.-0EBYTE = Low to DAT AOUT Enabled
3.-DATAlN to Corrected DATAoUT
Max.
Max.
Max.
4.-DATAlN Set-up to LEIN = Low
5.-DATAlN Hold to LEIN = Low
Min.
Min.
6.-LEIN = High to DATAoUT
Max.
LEIN
• = (Memory/System dependent)
to
to
to
8.10
2595 drw 12
30
IDT39C60/-1/AIB
16-BIT CMOS DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GND to 3.0V
Test
Switch
Input Rise/Fall Times
Wins
Input Timing Reference Levels
1.5V
Closed
Output Reference Levels
1.5V
Disable Low
Enable Low
All Other Outputs
Input Pulse Levels
Open
2595 tbl71
Output Load
See Figure 12
2595 tbl 70
IDT39C60 INPUT/OUTPUT INTERFACE CIRCUIT
Vee
ESD
PROTECTION
IIH
~
INPUTS 0 - - - "
OUTPUTS
2595 drw 19
2595 drw 20
Figure 10. Input Structure (All Inputs)
Figure 11. Output Structure
TEST CIRCUIT LOAD
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 12.
8.10
31
~®
Integrated Device Technology, Inc.
32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
FEATURES:
DESCRIPTION:
• Fast
Detect
•
•
•
•
•
•
•
•
•
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
Correct
-IDT49C460D
12ns (max.)
18ns (max.)
-IDT49C460C
16ns (max.)
24ns (max.)
25ns (max.)
- IDT49C460 8
30ns (max.)
30ns (max.)
- IDT49C460A
36ns (max.)
-IDT49C460
40ns (max.)
49ns (max.)
Low-power CMOS
- Commercial: 95mA (max.)
- Military: 125mA (max.)
Improves system memory reliability
-Corrects all single bit errors, detects all double and some
triple-bit errors
Cascadable
- Data words up to 64-bits
Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
Simplified byte operations
- Fast byte writes possible with separate byte enables
Functional replacement for 32- and 64-bit configurations of
the 2960
Available in PGA, PLCC and Fine Pitch Flatpack
Military product compliant to MIL-STD-883, Class 8
Standard Military Drawing #5962-88533
The IDT49C460s are high-speed, low-power, 32-bit Error
Detection and Correction Units which generate check bits on
a 32-bit data field according to a modified Hamming Code and
correct the data word when check bits are supplied. The
IDT49C460s are performance-enhanced functional replacementsfor32-bitversionsofthe2960. When performing a read
operation from memory, the IDT49C460s will correct 100% of
all single bit errors and will detect all double bit errors and
some triple bit errors.
The IDT49C460s are easily cascadable to 64-bits. Thirtytwo-bit systems use 7 check bits and 64-bit systems use 8
check bits. For both configurations, the error syndrome is
made available.
The IDT49C460s incorporate two built-in diagnostic modes.
80th simplify testing by allowing for diagnostic data to be
entered into the device and to execute system diagnostics
functions.
They are fabricated using CEMOSTM, a CMOS technology
designed for high-performance and high-reliability. The
devices are packaged in a 68-pin ceramic PGA, PLCC and
Ceramic Quad Flatpack.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class 8, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
CB~~--+-~----------------------------------------~
SC()-7
LEIN
1->+---+-..-------'
~
MOLT ERROR
LEOIAG
L...>----+---------'
LEoUT/~ D-----1:----l~---:-----""'-1------.
CORRECT ~--------l~
CODE 101.0 L...>--------l~
DIAG MODE1.0 L:>--------l~________ j - - - - - .
CEMOS is a 1rademark of Integrated Device Technology Inc.
2584 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IC1992 Integrated Device Technology, Inc.
8.11
MAY 1992
05C·9017/5
1
lOT49C460/AlB/C/O
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ww
0
0
0
~
0
£5 81~
Vee
02
03
04
05
06
07
Os
GNO
09
010
011
012
013
014
015
OEl
~d~
w-
o
~
00
~-
~
(!)w w
r-
0
m
-I
m
~
0
OJ
z
>
0
0
r0
"
C
:;
MD0-31
"T1~
r-cn
c
-n
c:
SY00-7 CJ" ~
~~
r-
m
I
w-
c
G')
:D
J>
3:
~
0
:0
:0
~
:::I
0
z
c
~
~
I\)
3:
r=
~
P0-3
:0
<
~
c
PERR CJr-+I-------'
83:
3:
IERR
INTERNALSYNCLK
SYNCLK ~>---~ )
SCLKEN o---J -CLEARD
m
:0
o
):
r-
~
••
D--¥1
PCBl0-7
3:
CODE 100,1
CONTRO~
MODE0-2 ~ LOGIC
J-.
-0
m
:0
~
:0
m
~
~
z
G)
m
(J)
IDT49C465/A
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various
configurations in an EDC system. The basic configurations
are shown below.
Figure 1 illustrates a bi-directional configuration, which is
most appropriate for systems using bi-directional memory
buses. It is the simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.
CPU
MEMORY
1/0
1/0
Figure 3 illustrates a third configuration which utilizes
external buffers and is also well suited for systems using
memory with separate lID buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in "bus-watch" mode. As in the
separate lID configuration, corrected data is output on the SO
outputs.
MEMORY
INPUT BUS
CHECKBIT
1/0
MEMORY
OUTPUT BUS
EDC
EDC
CBI~
CBO
CPU BUS
CHECKBITS
I---~
2552 drw 07
2552 drw05
Figura 3. Bypassed Separate I/O Configuration
Figure 1. Common I/O Configuration
Figure 2 illustrates a separate lID configuration. This is
appropriate for systems using separate lID memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SO outputs
for the system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.
Figure 4 illustrates the single-chip generate-only mode for
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straightforward, fast and requires no extra hardware for the
expansion.
CHECK
BITS OUT
MEMORY
INPUTS
SO
CHECK
BITS IN
MEMORY
INPUT BUS
II
~
MO
~
~
MEMORY
OUTPUTS
~
EOC
CBI
~
CHECKBITS
CPU BUS
2552 drw 08
CBO
2552drw 06
Figure 4. Separate Generate/Correction Units
with 64·BIt Checkblt Generation
Figure 2. Separate I/O Configuration
8.12
5
IDT49C465/A
32·BITFLOW·THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The error detection/correction codes consist of a modified
Hamming code; it is identical to that used in the IDT49C460.
32·BIT MODE (CODE ID 1,0=00)
Vcc ........I0000-......CHECKBITS-OUT
CBO'"""7----....
PCBI
I------I~
CBI7
CBI~
CHECKBIT5-IN
SYO ' " " " - - - -....
7 SYNDROME-OUT
7
EDC
2552 drw09
Figure 5. 32·Blt Mode
64-BIT MODE (CODE ID 1,0=10 & 11)
The expansion bus topology is shown in Figure 6. This
topology allows the syndrome bits used by the correction logic
to be generated simultaneously in both parts used in the
expansion. During a 64-bit detection or correction operation,
'a"
---.
CHECKBIT5-IN '
"
a
PCBI
CBO
'a"
CBI
SYO
'a"
"Partial-Checkbit" data and "Partial-Syndrome" data is simultaneously exchanged between the two EDC units in opposite
directions on dedicated expansion buses. This results in very
short 64-bit detection and correction times.
PARTIAL-CHECKBITS-OUT (11)
(CORRECTION ONLY)
PARTIAL-CHECKBIT5-0UT (10)
(GENERATE ONLY)
PARTIAL-SYNDROME
(DETECT/CORRECT ONLY)
PCBI
CBO
CBI
SYO
'a"
FINAL
CHECKBITS-OUT
-
LOWER EDC
ERR
UPPER EDC
(CODE ID 1,0 = 10)
(CODE ID 1,0 = 11)
(DETECT AND CORR ECT)
2552 drw 10
Figure 6. 64-Blt Mode - 2 Cascaded IDT49C465 Devices
64-BITGENERATE·ONLY MODE (CODE ID 1,0=01)
If the IdentitypinsCODE ID 1,0=01, asingle EDC is placed
in the 64-blt "Generate-only" mode. In this mode, the lower 32
bits of the 64·bit data word enter the device on the SD0-31
inputs and the upper 32-bits of the 64 bit data word enter the
, LOWER 32 BITS (0-31)
I
device on the MD0-31 inputs. This provides the device with the
full 64-bit word from memory. The resultant generated
checkbits are output on the CB00-7 outputs. The generate
time is less than that resulting from using a 2-chip cascade.
CBO
MD0-31
; 32
UPPER 32 BITS (32-63)
I
I
'a
CHECKBITS-OUT
SDG-31
; 32
EDC
2552 drw 11
Figure 7. 64·Blt "Generate·Only'· Mode (Single Chip)
8.12
6
IDT49C465/A
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
VO
Name and Function
VO Buses and Controls
SDO-7
SD8-15
SD16-23
SD24-31
VO
System Data Bus: Data from MDo-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The BEn inputs must be high and the 'SOE pin must be low to enable the SD
output buffers during a read cycle. (Also, see diagnostic section.)
Separate 1/0 memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on
SDn to n+7 forre-writing to memory, if BEn is high and ~ is low. The new bytes to be written to memory
are input on the SDn pins, for writing checkbits to memory, if BEn is low.
BI-dlrectlonal memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed
to the MD VO pins, if BEn is high, for checkbit generation and rewriting to memory via the MD 110 pins. 'SOE
must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written
are input on the SDn pins for checkbit generation and writing to memory. BEn must be low to direct input
data from the System Data bus to the MD 110 pins for checkbit generation and writing to the checkbit memory.
System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when
SLE is high; the data is latched when SLE is low.
SLE
Pipeline Latch Enable: '!5a: is an input which controls a pipeline latch, which controls data to be output
on the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent
when '!5a: is low; the data is latched when '!5a: is high.
System Output Enable: When low, enables System output drivers and Parity output drivers if corresponding Byte Enable inputs arehigh.
Byte Enables: In systems using separate 110 memory buses, BEn is used to enable the SD and Parity
outputs for byte n. The BEn pins also control the "Byte mux". When BEn is high, the corrected or uncorrected
data from the Memory Data latch is directed to the MD 110 pins and used for checkbit generation for byte
n. This is used in partial-word-write operations or during correction cycles. When BEn is low, the data from
the System Data latch is directed to the MD· VO pins and used for checkbit generation for byte n.
BEo controls SDO-7
.
BE2 controls SD16-23
BE1 controls SD8-15
BE3 controls SD24-31
BEo-3
110
Memory Data Bus: These VO pins accept a 32-bit data word from main memory for error detection and!
or correction. They also output corrected old data or new datato be written to main memory when the EDC
unit is used in a bi-directional configuration.
.
I
Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs.
The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper
slice ina 64-bit cascade, the checkbit latch is bypassed.
"fJOE"
I
Memory Output Enable: fVfOE enables Memory Data Bus output drivers when low.
PO-3
VO
MDo-31
MLE
Parity VO: The parity 110 pins for Bytes 0 to 3. These pins output the parity of their respective bytes when
that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating
the Parity ERRor (P"EfiR) signal under certain conditions (see Byte Enable definition). The parity is odd or
even depending on the state of the Parity SELect pin (PSEL).
I
Parity SELect:
CB10-7
I
CheckBlts-ln (OO)
CheckBits-ln-1 (10)
Partial-Syndrome-In (11):
In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits
from the c.heckbit memory. In the upper slice in a cascaded EDC system, these inputs accept the "PartialSyndrome" from the lower slice (Detect/Correct path).
PCBI0-7
I
Partial-CheckBits-ln (11):
Partlal-CheckBlts-ln (10)
In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC
system, the "Partial-Checkbits" used by the lower slice are accepted by these inputs (Correction path only).
In the upper slice of a cascaded EDC system, "Partial-Checkbits" generated by the lower slice are accepted
by these inputs (Generate path).
CODE ID1,o
I
CODE IDentity: Inputs which identify the slice position! functional mode of the IDT49C465.
(OO) Single 32-bit EDC unit
(10) Lower slice of a 64-bit cascade
(01) 64-bit "Checkbit-generate-only" unit
(11) Upper slice of a 64-bit cascade ..
PSEL
If the Parity SELect pin is low, the parity is even.
If the Parity SELect pin is high, the parity is odd.
Inputs
2552tb101
8.12
7
II
IDT49C465/A
32·BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS {Con't.}
Symbol
Name and Function
1/0
Inputs (Con't.)
MODE 2-0
MODE select: Selects one of four operating modes.
I
(x11)
(x10)
(000)
(x01)
(100)
"Normal" Mode: Normal EDC operation (Flow-thru correction and generation).
"Generate-Detect" Mode: In this mode, error correction is disabled. Error generation and detection are
normal.
"Error-Data-Output" Mode: Allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling
CI:EAR low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data
from the first error that occurs after they are reset by the crEAR" pin. The Syndrome Register and ErrorData Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (El1J1
= low), and the Error Counter indicates zero.
AII-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of
all-zero-data for hardware initialization of memory, if this desired.
Diagnostic-Output Mode: In this mode, the contents of the Syndrome R3gister , Error Counter and ErrorType Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read
by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated
when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates
zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred
after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling
crEAR" low. The Error Counter lets the system tell if more than one error has occurred since the last time
the Syndrome Register or Error-Data Register was read.
Checkblt-Injectlon Mode: In the "Checkbit-Injection" Mode, diagnostic checkbits may be input on System
Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).
CLEAR: When the CI:E:AR pin is taken low, the Error-Data Register, the Syndrome Register, the Error
Counter and the Error-Type Register are cleared.
SYNdrome CLocK: If Em is low, and the Error Counter indicates zero errors, syndrome bits are clocked
into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the
Error-Data Register on the low-to-high edge of SYNCLK. If E1R' is low, the Error Counter will increment on
the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.
SYNCLK
SynCLK ENable: The ~ enables the SYNCLK signal. SYNCLK is ignored if SCO ___
NOTE:
2552 drw 23
1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes high.
Figure 11. 64-Blt Detect TIming
8.12
32
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS - 64-BIT CONFIGURATION
NOTE:
Propagation Delay
To
From
Min.!
Max.
MOE = High to MDoUT Disabled
max.
MDIN Set-up to MLE = Low
min.
MDIN Hold to MLE = Low
min.
eBI Set-up to MLE = Low
min.
eBI Hold to MLE = Low
min.
MLEIN = High to SDoUT (1)
max.
2552 drw 24
1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes high.
Figure 12. 64-Blt Correct TIming (Lower Slice)
8.12
33
IDT49C465/A
32·BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
64-BIT CONFIGURATION
Propagation Delay
From
To
Min.!
Max.
MOE = High to MDoUT
Disabled
max.
MDIN Set-up to MLE = Low
min.
MDIN Hold to MLE = Low
min.
CBI Set-up to MLE = Low
min.
CBI Hold to MLE = Low
min.
MLEIN = High to SDOUT (1)
max.
MD0-31
CBI
MLE
PLE
= Low to SDOUT (1)
max.
BEN
BEN =High to SDOUT Enabled
max.
SOE = Low to SDOUT Enabled
CBI to Corrected SDOUT
MDIN to Corrected SDOUT
MDIN to Corrected SDOUT
max.
max.
max.
max.
MDIN to Parity Out
MLE = High to Parity Out
PLE = Low to Parity Out
BEN = High to Parity Out
SOE = Low to Parity Out
max.
max.
max.
max.
max.
SOE
tSESZX
tes
t MS
tMSY
S00-31
Corrected DATAoUT
tMP
tMLP
tPLP
t BEPZX
tSEP
P0-3
SYO
NOTE:
2552 drw 25
1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes high.
Figure 13. 64-Blt Correct Timing (Upper Slice)
8.12
34
IDT49C465/A
32-81T FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS - 64-BIT CONFIGURATION
Propagation Delay
From
' To
Min.!
Max.
SDIN Set-up to SLEIN = Low
min.
SDIN Hold to SLEIN = Low
min.
SLE = High to CBO(1)
max.
MDIN Set-up to MLEIN = Low
MDIN Hold to MLEIN = Low
min.
min.
Bits 32-63 to CBO
Bits 0-31 to CBO
MLEIN = High to CBO(2)
max.
max.
max.
CBOE = Low to CBO Enabled
max.
SLE
MOE
MDBus
MLE
COE
CBO
Final Checkbits Out
NOTE:
2552 drw 26
1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes high.
2. Assumes that Memory Data is valid at least 4ns (Com.) before MLE goes high.
Figure 14. 64-81t Single Chip "Generate Only" Timing
8.12
35
IDT49C465/A
32·BIT FLOW·THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS - DIAGNOSTIC TIMING
465
CBI
Min.!
1
2
4
51 Para mete
Propagation Delay
Max.
~~~t?___~I~i__~I~_~T~I___~L-_~I~r"___~I~I~I__N_am
__
e-r___F_ro_m_____________T_O____+_~
I
~ XXX ,--_C_he_c_kb_~_s_In_ _ _ _ _ _ _ _ _ _ 1: III ):~)))))
-,csc~
MO Bus
MLE
cscs
CBI Set-up to SYNCLK .. High
~MSCS-
t MSCS
MOIN Set-up to SYNCLK .. High
+--4 MLSCs-------.
t MlSCS
MLE .. High Set-up to SYNCLK = High min.
t SESCS
SCLKEN Set-up to SYNCLK .. High
min.
SCLKEN = Hold After SYNCLK = High min.
~ ~X'"7X~.X~
t
Memory OatalN
min.
hl_--,
t SESCH
min.
t CLEAR
SCLKEN Pulse Width
SCLKEN = High to SOOUT
CLEAR Pulse Width
tClR
CLEAR = Low to SOOUT
max.
t SYNClK
t
scs
max.
min.
/
SO Bus
ill m
ZC
SYNCLK
:a
:a
m
~9
•
0
c •
BE0-7 ~
g
0
Z
C
Z
::::j
0
SD0-63~
1111,,,
•••••••••••••••••••••••
_ ••
0.
",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,~b,....
I.
.1
ID
~
m
~
-lo ~
I.
I:::::::::::::::::::::ar{
MD0-63
}»
I I
----r----
~
'77Tl MOE
SDOLE
CBSEL
"'MEN
SCLK
WBEN~
WBREN
LI~
P0-7
PEAR
I
R:;~D
I'III~~
..
I __
(BI14, _
Reg)
n_._._.
~<
I I .......... • 1
•
~
CBSYU0-7
1
WBSEL
....
E:
m
:a
~
MDtoSDPath
I ~:!,~'!
I-!- Path A
=> Path B
BEn = 0
BEn = 1
~------~~--------
___________________________ MOBUS
PATH B
PATH A
64
SO
LATCH IN
64
BYTE
MUX
SO
LATCH OUT
M
U
'.
X·
BEo·7
~-------+-------------------WBSEL
WRITE BUFFER
2617drw 0$
Figure 1. Byte Merge
Memory Read
During a memory read, data and the corresponding input
checkbits are read from the MD bus and CBlo·7, respectively.
The memory data and CBI may both be latched as they come
in (MD latch In and MD Checkbit latch) by the MOllE signal.
Memory data is sent to the MD checkbit generator (where
checkbits corresponding to the input data are generated) and
to the error correct circuitry. The generated checkbits are XORed with the input checkbits to produce the syndrome word.
This is sent to the error correction circuitry which generates
the corrected data (normal mode). The corrected data is
output to the SO bus via either of two data paths. When
RBSEl is lOW, data flows through MD latch Out. Pulling
tvrnrn:E' HIGH latches this data. The output buffer is enabled
by asserting SOE and BE0-7. Corrected data can be written
back to memory by enabling the MD output buffer. In order to
ensure selection of the write back path (Path B in figure 1) at
the byte mux, BEO-? should be all 1's while WBSEl = O. If
WBSEl -1, buffered BEO-? from the output of the write FIFO
controls the byte mux.
If the read FIFO is selected (RBSEl HIGH), data is clocked
into the FIFO (Read_FIFO Write) when RBE"f\jis lOW, on the
rising edge of MClK. Data is clocked out of the FIFO
(Read_FIFO Read) when RBREN" is lOW on the rising edge
of SClK.
.
Clock Skew
A skew between the read and write clocks, as specified by
tskew, is recommended. This specification is not a stringent
one, in the manner of setup and hold times, but is important in
preempting latencies at FIFO boundaries. For example When a word is written to an empty FIFO, there is a finite delay
before the FIFO is recognized as no longer being empty and
hence allowing a read from the same FIFO. Similarly when a
word is read from a full FIFO, there is a delay before a write can
successfully be attempted. The tskew specification accounts
for these cases. During cycles other than on full/empty FIFO
boundaries, the clock skew is not required and the device
functions correctly even when the reads and writes occur
simultaneously. If the tskew specification is ignored and SClK
and MClK were permanently tied together, there is an extra
cycle latency in the cases mentioned above. One such case
is illustrated in Figure 11.
FIFO Write Latency
The first data written to either of the (read or write) FIFOs,
after the FIFO is reset, suffers a single clock latency. Data that
is set-up with respect to the first clock is ignored and the data
that is set-up with respect to the second clock edge after the
reset, is stored as the first data in the FIFO. The empty-flag
is deasserted after this second clock edge and 15 more data
words (in a 16 deep configuration) can be written to the FIFO
after this.
The latency can be reduced or eliminated by providing a
"dummy" or "set-up" clock edge (as shown in figure) before the
actual write to the FIFO. The dummy write clock can be
provided any time after reset and before the next buffer write
operation takes place. The latency described here (shown in
Figure 9) occurs only after a FIFO reset. In other cases where
the FIFO becomes empty there is no such latency.
8.13
9
IDT49C466 Flow-thruEDC'fId
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
Partial Word Write/Byte Merge
MODE REGISTER CONFIGURATION
7
6
5
4
3
2
a
Writing a word shorter than 64 bits to memory is treated as 15
a special case. The checkbits generated for a data word I UNUSED I RMODEI PSEL I RWBD I CLEAR I EDCMO-2 I
shorter than 64 bits and written to a particu lar memory location
differ from the checkbits that would be generated by the entire EDCM2 EDCM1 EDCMO
OPERATION
a
64-bit data word at the same location. Hence, the byte merge
a
0
ERROR-DATA OUTPUT MODE
0
0
1
DIAGNOSTIC-OUTPUT MODE
operation requires reading the contents of the memory location
0
1
0
GENERATE-DETECT MODE
to be written to, merging the bytelbytes being written (from SD
0
1
1
NORMAL MODE
1
X
side) with the other component bytes previously at that memory
CHECKBIT-INJECTION MODE
X
location (from MD side), generating a checkbit word for this
RMODE
OPERATION
composite word and writing both the composite data word and
o
NOP
the generated checkbits to memory. The BEn bits supplied by
1
READ MODE REGISTER ON SO BUS
the user determine the bytes that come from SD and those that
RWBD
come from MD, as illustrated in Figure 1.
OPERATION
DUAL FIFOS (a)
o
EDC Modes
SINGLE FIFO (16)
1
The IDT49C466 has 5 modes of operation. Refer to table
below for a description of the modes. The Error Data Output
CLEAR
OPERATION
mode is useful for memory initialization. On issuing a clear, the
NOP
0
Error Data register becomes an 'all-zero-data' source. All
CLEAR ALL DIAGNOSTIC
1
REGISTERS
diagnostic registers can be cleared in this manner.
In Checkbit Injection mode, the MD Checkbit Latch is
PSEL
OPERATION
loaded with data from the System Bus. This serves to verify the
EVEN PARITY·
functioning of the EDC. Any discrepancy between the injected
1
ODD PARITY
2617 drw 06
checkbits and generated checkbits should result in assertion of
the ERR or MERR signals.
These modes, and certain other features such as clear,
buffer configuration, etc., can be selected by appropriately
loading the Mode Register. The Mode Register can be written
to by asserting MEN. Then SDO-15 is clocked into the mode
register on the rising edge of SCLK.
a
OPERATING MODE DESCRIPTION
Mode
Description
MODEO
Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by setting the mode
register "'clear"-bit.
MODE 1
Diagnostic-Output Mode: In this mode, contents of latch and five internal registers are read by the system for
diagnostic and error logging purposes. Internal data paths allow output from the CBI LATCH to be read directly by the
system bus for diagnostic purposes. The contents of the internal diagnostic checkbit register, syndrome registers, error
count register and error-type register are also output on the SO bus.
MODE2
Generate-Detect Mode: (Detect-Only) The EDC performs checkbit generation during a memory write, and performs
error detection only during a memory read.
MODE3
Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during
memory reads.
MODE 4
Checkblt-lnJection Mode: In this mode, the checkbit latch is loaded with desired a-bit data from the SO bus.This eight
bit data passes through SO Latch in or write FIFO to the MD check bit latch. By inserting various checkbit values,
correct functioning of the EDC can be verified "on-board". The rest of the operation is similar to regular memory
reads. The EDC compares the injected checkbits against the internally generated checkbits. Any discrepancy in the
injected checkbits and the internally generated checkbits will cause the Em' / ~ to go LOW.
2617tb108
8.13
10
II
IDT49C466 Flow-thruEDCTM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DIAGNOSTIC OUTPUT DATA FORMAT
TOSD BUS
t
3713e13513413313213113c 29128 27126125124 23122121120119118117116 151141131121111101918 716151413121110
Error
Checkbit
Error
Syndrome
Checkbit
Syndrome
Type
(from checkbit latch)
Count
(on 1st error)
(on 1st error only)
(on every error)
(on
1st
error
only)
t
1
..
* Bit #28 = 1 If "Error" condition
FROM DIAGNOSTIC REGISTERS
Bit #29 = 1 If "Multiple bit Error" condition
2617drw 07
Diagnostics
The diagnostic ability of the lOT49C466 rests on a set of 6
registers that provide error logging information. These include
the checkbit register, error count register, error type register,
2 syndrome registers and the error data register. Data is
clocked into each of these registers by SYNCLK. The error
data register, checkbit register, error type register and one of
the syndrome registers are reloaded only in the case of the
first error after a clear. The other syndrome register and the
error count register are reloaded on every error condition
SYNCLK edge. The contents of the Error Data register can be
read only in Error Data Output mode. The contents of the other
diagnostic registers as well as the checkbit latch can be read
in Diagnostic Output mode.
Parity
The IDT49C466 provides a parity check and generation
facility. On a memory read the EDC generates parity bits for
each data word and outputs the parity byte on the parity bus,
POol. During a memory write, parity is checked by comparing
the parity bits input on POol and the parity bits generated from
the input data word. A discrepancy between these two causes
the PERR pin to be asserted.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vee
Rating
Power Supply Voltage
Com'l.
-0.5 to +7.0
Operating Temperature
oto +70
°C
TA
CONDITION
OUTPUT
CHECKBIT
SYNCLKi
ONLY ON 1st
ERROR
SD8-15
SYNDROME
(On 1st ERR)
SYNCLKi
ONLY ON 1st
ERROR
SD16-23
ERRCNT
SYNCLKi
ON EVERY
ERROR (Up to
15 ERRORS)
SD24-27
ERR TYPE
SYNCLKi
ONLY ON 1st
ERROR
SD28-29
SYNDROME
(On every
ERROR)
SYNCLKi
ON EVERY
ERROR
SD30-37
Symbol
CIN
V
V
Terminal Voltage with
Respect to Ground
LOADED
BY
CAPACITANCE
Unit
-0.5 to
VCC + 0.5
VTERM
DIAG.
REGISTER
TBIAS
Temperature Under Bias
-55 to +125
°C
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
30
rnA
= +25°C, f = 1.0 MHz)
Input
Output
Capacitance
Typ.
Unit
PGA
5
pF
PQFP
5
Conditions
VIN = OV
Capacitance
COUT
TSTG
(TA
Parameter(1)
VOUT= OV
PGA
7
PQFP
7
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2617tbll0
NOTE:
2617 tbl 09
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only. and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Ratings for
extended periods of time may affect reliability.
8.13
11
IDT49C466 Flow-thruEDCN
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 5%;
Test Condltlons(1)
Parameter
Input HIGH Level(4)
Min.
TyP.(2)
Max.
VIH
Guaranteed Loqic HIGH Level
2.0
-
V
VIL
Input LOW Level(4)
Guaranteed Loqic LOW Level
-
-
O.S
V
J.lA
J.lA
J.lA
Symbol
IiH
Input HIGH Current
Vee = Max., VIN = 2.7V
IlL
Input LOW Current
Vee = Max., VIN = 0.5V
Off State (Hi-Z)
Vee= Max.
loz
0.1
5.0
-0.1
-5.0
-
-0.1
-10
0.1
10
-20
-
-100
mA
IOH=-2mA
2.4
3.6
-
V
10L .. SmA
-
0.3
0.5
V
-
200
-
Vo=OV
Output Current
Vo=3V
los
Short Circuit Current
Vee = Max.(3), VOUT= OV
VOH
Output HIGH Voltage
Vee= Min.,
Unit
VIN = VIH or VIL
VOL
Output LOW Voltage
Vee= Min.
VIN = VIH or VIL
VH
Input Hysteresis on input control lines
NOTES:
mV
2617tbl11
1. For conditions shown as min. or max., use appropriate Vee value.
2. Typical values are at Vee .. 5.0V, +25°e ambient temperature.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't)
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V +
- 5%
Min.
Typ.(2)
Max.
Unit
leeae
Quiescent Power Supply Current
VIN = Vee, or VIN = GND
Vee= Max.
-
3.0
15
mA
leeaT
Quiescent Power Supply Current
TTL Input Levels
VIN =3.4V
Vee= Max.
-
0.3
1
mAl
Input
IceD
Dynamic Power Supply Current
VIN =Vee, or VIN =GND
Vee = Max. f = 10MHz Correct Mode
-
-
100
mA
Symbol
Parameter
Test Condltlons(1)
NOTES:
2617tbl12
1. For conditions shown as Min. or Max., use appropriate Vee value.
2. Typical values are at Vee = 5.0V, +25°e ambient temperature.
II
8.13
12
IDT49C466 Flow-thruEDCTM
ERROR DETECTION 'AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
AC PARAMETERS
PROPAGATION DELAY TIMES
Description
Number
From Input(1)
Parameter
To Output
Max.
Unit
20
16
10
22
22
16
ns
Refer to
Timing Diagram
Figure
GENERATE (WRITE) PARAMETERS
Without Write FIFO:
1
2
3
4
tBe
BEn
CBSYN (chkbit)
tBM
BEn
MOOUT
tPPE
" Pxin
tse
SOin
5
t5M
SOin
MOout
6
tSPE
SDin
TYrnR
PERR
CBSYN (chkbit)
ns
ns
ns
ns
ns
With Write FIFO:
7
8
tMe
MCLK (La-Hi)
CBSYN (chkbit)
tMMD
MCLK (La-Hi)
MOout
9
twBSEL
WBSEL
MOout
25
25
18
ns
ns
4
4
ns
DETECT (READ) PARAMETERS
Without Read FIFO:
10
11
12
13
14
-'-
twYe
SYNCLK (La-Hi)
CBSYN (syndr)
tME
MOin
E11R"
tMME
MOin
~
tCE
CBI
E11R"
tCME
CBI
~
tSSD
SCLK(Lo-Hi)
SOout
tRBSEL
RBSEL
SOout
16
20
22
13
13
ns
22
18
ns
ns
ns
ns
ns
ns
ns
With Read FIFO:
15
16
6
ns
CORRECT (READ)PARAMETERS
Without Read FIFO:
17
18
19
tes
CBI
SOout
tMP
MOin
Pxout
tMS
MOin
SOout
20
22
22
SCLK (La-Hi)
Pxout
22
With Read FIFO:
tsp
20
ns
ns
2617tb113
NOTES:
1. (Lo-Hi) Indicates LOW-to-HIGH transition and vice versa.
8.13
13
IDT49C466 Flow-thruEDCTM
ERROR DETECll0N AND CORRECll0N UNIT
COMMERCIAL TEMPERATURE RANGE
PROPAGATION DELAY TIMES
FROM LATCH ENABLES
Refer to
Timing Diagram
Description
Number
Parameter
From Input(1)
To Output
21
tMLE
MOlLE (Lo·Hi)
Em
Max.
Unit
16
ns
ns
22
tMLME
MOlLE (Lo-Hi)
MERR
18
23
tMLP
MOlLE (Lo-Hi)
24
ns
24
tMLS
MOlLE (Lo-Hi)
22
ns
18
ns
18
ns
25
tMOLS
~(Hi-Lo)
Px
SOout
SOout
26
tMOLP
~(Hi-Lo)
Px
27
tSLC
SOILE (Lo-Hi)
CBSYN (chkbit)
20
ns
28
tSLM
SOILE (Lo-Hi)
MOout
20
ns
29
tSOlC
SOME (Hi-Lo)
CBSYN (chkbit)
12
ns
30
tSOLM
soorr (Hi-Lo)
MOout
15
ns
Figure
NOTE:
2617tbl14
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
R/W FIFO TIMES
Refer to
Timing Diagram
Description
Number
Parameter
From Input(1)
To Output(1)
Min.
Max•.
Unit
Figure
31
tRSF
RS1 (Hi-Lo)
E= (Hi-Lo)/'FF' (Lo-Hi)
-
16
ns
7,10,11
32
tSKEW1
RCLK (Lo-Hi)
(SCLK or MCLK)
WCLK (Lo-Hi)
(SCLK or MCLK)
10
-
ns
3,5
33
tSKEW2
WCLK (Lo-Hi)
(SCLK or MCLK)
RCLK (Lo-Hi)
(SCLK or MCLK)
10
-
ns
4,6
34
tEF
RlWCLK (Lo-Hi)
(SCLK or MCLK)
E=
-
15
ns
4,6,10,11
35
tFF
RlWCLK (Lo-Hi)
(SCLK or MCLK)
'FF'
-
15
ns
3, 5
2617tbl15
NOTE:
1. (La-Hi) indicates LOW-to-HIGH transition and vice versa.
8.13
14
IDT49C466 Flow·thruEDCTM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
BYTE MERGE TIMES
Refer to
Timing Diagram
Description
Number
36
37
38
39
From(1)
Parameter
To
tSCM
SCLK (Lo-Hi)
MDout
tMDM
~(Hi·Lo)
MDout
tRBM
RBSEL
MDout
tSDM
SDILE (Lo-Hi))
MDout
Max.
Unit
25
18
23
18
ns
ns
Figure
9
ns
ns
9
NOTES:
1. (Lo-Hi) Indicates LOW-to-HIGH transition and vice versa.
2617tbl16
ENABLE.AND DISABLE TIMES
Refer to
Timing Diagram
Description
Number
Parameter
41
42
43
tBESxZ
44
tBEPxZ
84
85
45
46
47
48
49
50
tSEPZx
tBESZx
tBEPZx
From Input
BEN=
BEN=
SOE=
Pout
Low
Pout
HiQh
~=
Low
CBSYN
HiQh
~=
tMEMxZ
tSESZx
High
Low
MDout
SOE=
Low
High
SDout
Min.
Max.
Unit
Figure
-
22
22
15
15
14
14
10
10
32
18
16
20
ns
6
ns
6
-
*
-
Hi-Z
*
-
Hi-Z
-
*
-
Hi-Z
-
*
Hi-Z
HiQh
tSESxZ
~
Hi-Z
Low
tCECxZ
tMEMZX
To Output(1,2)
SDout
Low
tSEPxZ
tCECZx
High
*
Hi-Z
NOTES:
1. (High-Z) indicates high Impedence.
2. • indicates delay to both edges.
-
ns
ns
4
ns
4,9
ns
6
26171b117
8.13
15
IDT49C466 Flow-thruEDC'J1d
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
SET-UP AND HOLD TIMES
Refer to
Timing Diagram
Description
Number
Parameter
From Input
edge(1)
Min.
Unit
51
tCMLS
CBI Set-up
before MOlLE =
Hi-La
2
ns
5
52
tCMLH
CBI Hold
after MOlLE =
Hi-La
6
ns
5
To Input
Figure
53
tMMLS
MOIN Set-up
before MOlLE =
Hi-La
2
ns
5
54
tMMLH
MOIN Hold
after MOlLE =
Hi-La
6
ns
5
55
tCMOLS
CBI Set-up
before~=
Lo·Hi
10
ns
56
tCMOLH
CBI Hold
after 'fiiIDO'[E =
La-Hi
2
ns
57
tMMOLS
MOIN Set-up
before "f.iIDOCE" =
La-Hi
10
ns
ns
58
tMMOLH
MOIN Hold
after 'KillJO[E" =
La-Hi
4
59
tMMCS
MOIN Set-up
before MCLK =
La-Hi
10
ns
5
60
tMMCH
MOIN Hold
after MCLK =
La-Hi
4
ns
5
61
tSSLS
SOIN Set-up
before SOILE =
Hi-La
5
ns
62
tSSLH
SOIN Hold
after SOILE =
Hi-La
3
ns
63
tSSCS
SOIN Set-up
before SCLK
La-Hi
2
ns
3,10,11
64
tSSCH
SDIN Hold
after SCLK
La-Hi
6
ns
3, 10, 11
86
tSSOLS
SDIN Set-up
before SJ)Q[E =
La-Hi
8
ns
87
tSSOLH
SDIN Hold
after SDQ[E" =
La-Hi
0
ns
65
tSCSD
SCLK (La-Hi)
before
snoo: =
La-Hi
14
ns
(Write back path)
89
tMCSD
MCLK (La-Hi)
before~=
La-Hi
14
ns
(Write path) 4
66
tENs
RIW FIFO Enable Set-up
before S/M CLK =
La-Hi
4
ns
3,4,5,6,10
67
tENH
RIW FIFO Enable Hold
after s/M CLK =
La-Hi
4
ns
3,4,5,6
70
tRSS
RS1 (La-Hi)
RlWCLK =
La-Hi
6
ns
7
71
tMODS
Mode Data Set-up
before SCLK
La-Hi
4
ns
8
72
tMODH
Mode Data Hold
after SCLK
La-Hi
4
ns
8
73
tMENS
Mode Enable Set-up
before SCLK =
La-Hi
4
ns
8
74
tMENH
Mode Enable Hold
after SCLK ==
La-Hi
4
ns
8
~=
Hi-La
22
ns
90
tMSD
MDIN
DIAGNOSTIC SET-UP AND HOLD TIMES
75
tcscs
CBI Set-up
76
tMSCS
MDIN Set-up
77
tMLSCS
MOlLE Set-up
=
=
before SYNCLK = HIGH
= La-Hi
4
ns
4
ns
12
ns
NOTE:
2617tbl18
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
MINIMUM PULSE WIDTH
Refer to
Tim Ing Diagram
Description
Number
Parameter
Condition
Min.
Unit
6
ns
MD, CBI = Valid
6
ns
-
6
ns
to strobe new data
SD = Valid
6
ns
EN signal LOW
From Input
78
tRS
Min. RS1 LOW time
to reset buffers
79
tMLE
Min. MDILE HIGH time
to strobe new data
80
tMDOLE
Min. ~LOW time
to strobe new data
81
tSLE
Min. SDILE HIGH time
-
82
tCLK
Min. S/MCLK HIGH time
to clock in new data
6
ns
83
tSYNCLK
Min. SYNCLK HIGH time
to clock in new data
-
6
ns
88
tSDOLE
Min.
to clock in new data
-
6
ns
SDOt'E" LOW time
Figure
2617tbl19
8.13
16
IDT49C466 Flow-thruEOcm
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
AC Test Conditions
Input Pulse Levels
GNO to 3.0V
Input Rise/Fall Times
WIns
Input Timing Reference Levels
1.5V
Output Reference Levels
Out Load
1.5V
See Figure 14
2617tbl21
SOO-15
SO IN (Mode)
tMODH
SCLK
2617drw08
Figure 2. Mode Enable Timing
. WBSEL
SCLK
(WCLK)
SOO-63
~ ~--------------------~r-----'~------~~------------------------MCLK·
(RCLK)
,,'------/
2617drw09
Figure 3. Write FIFO Timing Table (Write Cycle)
8.13
17
IDT49C466 Flow-thruEDCN
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
MCLK
(RCLK)
WBREN
WBSEL
CBSEL
tMEMXZ
MOE
tMMD
MOout 01
MOO-63
tMC
CBSYNO-7
Valid Checkbits out
tSKEW2
SCLK
(WCLK)
Figure 4. Write FIFO Read and Checkblt Generate Timing (Write Cycle)
II
8.13
18
IDT49C466 Flow·thruEDCN
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
RBSEL
MDD-63
CBID-?
MDILE
MCLK
(WCLK)
tFF
tFF
SCLK
(RCLK)
Figure 5. Read FIFO Write Timing (Read Cycle)
8.13
19
IDT49C466 Flow·thruEDCN
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
SCLK
(RCLK)
tEF
MCLK
(WCLK)
RBSEL
tSSD
tSESZX
BEO·?
tBESZX
SOout (corrected data)
SOO·63
tSEPZX
PO·?
2617drw 12
Figure 6. Read FIFO Read Timing (Read Cycle)
II
8.13
20
IDT49C466 Flow·thruEDCJ'M
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
RS1
tRS
WCLK
(SCLK I MCLK)
dummy write
2617 drw 13
Figure 7. FIFO Reset TIming
DATA
(SD/MD)
dummy
write
WCLK
(SCLKlMCLK)
tENS
BU FFER ENABLE
(WBm'RBEN)
tRSF
FIFO RESET
(RS1)
BUFFER
EMPTY FLAG
(WBEF/RBEF)
tEF
2617drw 14
Figure 8. FIFO Write Latency TIming
8.13
21
IDT49C466 Flow-thruEDC'TM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
Valid BEO-?
BEO-?
SOO-63
I4I_: _-~=_-~-/_S -S_C: i_n_O~Y -{:-ws---cL
___
__
__
. SOILE
external tristate
MOO-63
MO IN Ox
MOOUT OXY
tMEMXZ
MOlLE
tMMOLH
RBSEL
WBSEL
2617drw 15
Figure 9. Partial Word Write/Byte Merge TIming
NOTE:
1. tMMOE is not a propagation delay. For partial word write operations tMOM may be taken as the minimum value for tMMOE.
II
8.13
22
IDT49C466 Flow·thruEDCTM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
invalid data
SOO-63
SOin2
dummy write
SCLK
(WCLK)
RS1
tEF
MCLK
(RCLK)
,,--------------------------2617 drw 20
Figure 10. Write FIFO Write TIming with Clock Skew Violation
MOin
500-63
tMSCS
CBO-7
CBin
tCSCS
MOlLE
tMLSCS
SYNCLK
2617 drw 21
Figure 11. Diagnostic TIming
8.13
23
IDT49C466 Flow·thruEDCTM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
Vee
INPUT/OUTPUT INTERFACE CIRCUITS
ESD
PROTECTION
IIH_ _ _
---
INPUTS l~----~---------'--~~
OUTPUTS
ilL
2617drw 16
Figure 12. Input Structure (All Inputs)
2617drw 17
Figure 13. Output Structure
e-o
7.0V
500n
SWITCH POSITION
500n
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
26171bl20
2617drw 18
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RT..
Termination resistance: should be equal to ZOUT of the Pulse
Generator
Figure 14. AC Test Circuit
II
8.13
24
DOMESTIC SALES REPRESENTATIVES
ALABAMA
lOT
555 Sparkman Dr.,
Ste.1200-D
Huntsville, AL 35816
(205) 721-0211
ALASKA
Thorson Co. Northwest
Bellevue, WA
(206) 455·9180
CANADA
(WESTERN)
Thorson Co. Northwest
Bellevue, WA
(206) 455-9180
COLORADO
lOT
(NW Regional Office)
1616 17th St., Sta. 370
Denver, CO 80202
(303) 628-5494
HAWAII
MAINE
NEBRASKA
lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
lOT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898·9266
lOT
(Central Headquarters)
1375 E. Woodfield Rd.,
Ste.380
Schaumburg,IL 60173
(708) 517·1262
IDAHO
(NORTHERN)
Anderson Associates
Bountiful, UT
(801) 292·8991
ARIZONA
Westem High Tech Mktg.
Scottsdale, Az
(602) 860·2702
ARKANSAS
lOT
(5. Central Regional
Office)
14285 Midway Rd., Ste.
100
Oallas, TX 75244
(214) 490·6167
CALIFORNIA
lOT
(Corporate Headquarters)
2975 Stender Way
P.O. Box 58015
Santa Clara, CA 95052
(408) 727-6116
lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
lOT
(SW Regional Office)
6 Jenner Dr., Sta. 100
Irvine, CA 92718
(714) 727-4438
lOT
(SW Regional Office)
16130 Ventura Blvd.,
Ste.370
Encino, CA 91436
(818) 981·4438
Quest-Rep
San Diego, CA
(619) 565-8797
Thorson Rocky Mountain
Englewood, CO
(303) 799-3435
CONNECTICUT
Llndco Associates
Woodbury, CT
(203) 266-0728
DELAWARE
lOT
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste.
201
Annapolis, MD 21403
(301) 858·5423
$oJ Mid Atlantic, Inc.
Mt. Laurel, NJ 08054
(609) 866·1234
FLORIDA
lOT
(SE Regional Office)
1413 S. Patrick Dr., Ste.
Thorson Rocky Mountain
Salt Lake City, UT
(801) 942·1683
ILLINOIS
lOT
(Central Headquarters)
1375 E. Woodfield Rd.,
Ste.380
Schaumburg,IL 60173
(708) 517-1262
Synmark Sales
Park Ridge, IL
(708) 390-9696
INDIANA
Arete Sales
Ft. Wayne, IN
(219) 423-1478
AreteSales
Greenwood, IN
(317) 882·4407
10
Indian Harbor Beach, FL
32937
(407) 773·3412
lOT
(SE Regional Office)
18167 U.S. 19 North
Ste.455
Clearwater, FL 34624
(813) 532·9988
lOT
(SE Regional Office)
1500 N. W. 49th St.,
Ste.500
Ft. Lauderdale, FL 33309
(305) 776-5431
CANADA
(EASTERN)
GEORGIA
CMT Renmark, Inc.
Kanata,ONT
(613) 591·9555
lOT
(SE Regional Office)
1413 S. Patrick Dr., Ste.
CMT Renmark, Inc.
Mississauga, ONT
(416) 612·0900
Indian Harbor Beach, FL
10
CMT Renmark, Inc.
Pointe Claire, Quebec
(514) 694·6088
IDAHO
(SOUTHERN)
32937
(407) 773-3412
IOWA
Rep Associates
Cedar Rapids, IA
(319) 373·0152
MARYLAND
lOT
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste. 201
Annapolis, MD 21403
(301) 858·5423
MASSACHUSETTS
lOT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898·9266
MICHIGAN
Tritech Sales
Farmington Hills, MI
(313) 442-1200
MINNESOTA
lOT
(N. Central Regional Office)
1650 W. 82nd Street
Ste.1040
Minneapolis, MN 55431
(612) 885-5777
OHMS Technology Inc.
Edina, MN
(612) 932-2920
MISSISSIPPI
KANSAS
Rush & West Associates
Olathe, KS
(913) 764-2700
lOT
(SE Regional Office)
1413 S. Patrick Dr.,
Ste.10
Indian Harbor Beach, FL
KENTUCKY
32937
AreteSales
Ft. Wayne, IN
(219) 423-1478
LOUISIANA
lOT
(5. Central Regional
Office)
14285 Midway Rd., Ste.
100
Dallas, TX 75244
(214) 490·6167
(407) 773-3412
MISSOURI
Rush & West Associates
st. Louis, MO
(314) 965·3322
MONTANA
Thorson Rocky Mountain
Englewood, CO
(303) 799-3435
NEVADA
(NORTHERN)
lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492·8350
NEVADA
(SOUTHERN)
Westem High Tech Mktg.
(Clark County, NV)
Scottsdale, AZ
(602) 860·2702
NEW HAMPSHIRE
lOT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898·9266
NEW JERSEY
lOT
(NE Regional Office)
One Greentree Centre,
Ste.202
Marlton, NJ 08053
(609) 596-8668
SJ Mid-Atlantic, Inc.
Mt. Laurel, NJ
(609) 866-1234
NEW MEXICO
Westem High Tech Mktg.
Scottsdale, Az
(505) 884-2256
NEW YORK
lOT
(NE Regional Office)
250 Mill St., Ste.107
,Rochester, NY 14614
(716) 777·4040
Quality Components
Buffalo, NY
(716) 837·5430
Quality Components
Manlius, NY
(315) 682·8885
SJ Associates
Rockville Centre, NY
(516) 536·4242
NORTH CAROLINA
Tingen Technical Sales
Raleigh, NC
(919) 870-6670
PENNSYLVANIA
(WESTERN)
Norm Case Associates
Rocky River, OH
(216) 333-0400
NORTH DAKOTA
OHMS Technology Inc.
Edina, MN
(612) 932-2920
OHIO
Norm Case Associates
Rocky River, OH
(216) 333-0400
PENNSYLVANIA
(EASTERN)
S-J Mid-Atlantic
Mt. Laurel, NJ 08054
(609) 866-1234
RHODE ISLAND
IDT
(Eastern Headquarters)
OKLAHOMA
#2 Westboro Business
Park
IDT
(S. Central Regional Office) 200 Friberg Pkwy.,
Ste.4002
14285 Midway Rd., Ste.
Westboro, MA 01581
100
(508)
898-9266
Dallas, TX 75244
(214) 490-6167
SOUTH CAROLINA
OREGON
Thorson Co. Northwest
Portland, OR
(503) 293-9001
lOT
(SE Regional Office)
1413 S. Patrick Dr., Ste. 10
Indian Harbor Beach, FL
SOUTH DAKOTA
UTAH
WASHINGTON
OHMS Technology Inc.
Edina, MN
(612) 932-2920
Anderson Associates
Bountiful, UT
(801) 292-8991
Thorson Co. Northwest
Bellevue, WA
(206) 455-9180
TENNESSEE
VERMONT
IDT
555 Sparkman Dr.,
Ste.1200-D
Huntsville, AL 35816
(205) 721-0211
IDT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898-9266
IDT
(NW Regional Office)
7981168thAve. N.E.,
Ste.32
Redmond, WA 98052
(206) 881-5966
TEXAS
IDT
(S. Central Regional Office)
14285 Midway Rd., Ste.
100
Dallas, TX 75244
(214) 490-6167
IDT
(S. Central Regional Office)
17314 State Hwy. 19
Ste.242
Houston, TX 77064
(713) 890-0014
VIRGINIA
IDT
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste.201
Annapolis, MD 21403
(301) 858-5423
WEST VIRGINIA
Norm Case Associates
Rocky River, OH
(216) 333-0400
WISCONSIN
Synmark Sales
Park Ridge, IL
(708) 390-9696
WYOMING
Thorson Rocky Mountain
Englewood, CO
(303) 799-3435
32937
(407) 773-3412
lOT TECHNICAL CENTERS
Integrated DevIce Technology, Inc.
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
Integrated Device Technology, Inc.
(Southwestern Regional Office)
6 Jenner Drive, Suite 100
Irvine, CA 92718
(714) 727-4438
Integrated Device Technology, Inc.
(South Central Regional Office)
14285 Midway Road, Suite 100
Dallas, TX 75244
(214) 490-6167
Integrated Device Technology, Ltd.
(European HeadquarterslNorthern Europe
Regional Office)
21 The Crescent
Leatherhead
Surrey, UK KT228DY
Tel.: 44-0372-363-339n34
Integrated Device Technology, Inc.
(Eastern Headquarters)
#2 Westboro Business Park
200 Friberg Parkway, Suite 4002
Westboro, MA 01581
(508) 898-9266
AUTHORIZED DISTRIBUTORS (U.S. and Canada)
Alliance
Future
Electronics
Contact your local office.
Hall-Mark
Hamilton!Avnet
Insight
Electronics
Vantage
Components
Zentronics
INTERNATIONAL SALES REPRESENTATIVES
AFRICA
Monte Vista International
5673 W. Los Positas Blvd.,
Ste.205
Pleasanton, CA 94588
Tel: 510-463-8693
AUSTRALIA
George Brown Group
Rydalmere, Australia
Tel.: 612-638-1999
George Brown Group
Hilton, Australia
Tel.: 618-352-2222
George Brown Group
Blackburn, Australia
Tel.: 613-878-8111
AUSTRIA
ElbatexAG
Hardstrasse 72
CH-5430 Wettingen
Switzerland
Tel.: 011-41-56275-777
BELGIUM
Scientec REA
Schwerwiller, France
Tel.: 33-88-82-5514
Jermyn GmbH
Nordersted~ Germany
Tel.: 49-4015282041
Lasi Electronica
Torino, Italy
Tel.: (3911) 328588
Scientec, REA
Saint-Etienne, France
Tel.: 33-77-79-7970
Jermyn GmbH
Nurnberg, Germany
Tel.: 49-911/425095
Microelit SPA & SRL
Milan, Italy
Tel.: 39-2-4817900
Scantec GmbH
Planegg, Germany
Tel.: 49-859-8021
Microelit SPA & SRL
Rome, Italy
Tel.: 39-6-8894323
Scantec GmbH
Kirchheim, Germany
Tel.: 49-70-215-4027
JAPAN
A2M
Brignolles, France
Tel.: 33-1-94-59-2293
A2M
Bron, France
Tel.: 33-1-72-37-0414
A2M
BUC, France
Tel.: 33-1-39-56-8181
A2M
Cesson-Sevigne, France
Tel.: 33-1-99-63-3232
A2M
Le Chesnay Cedex, France
Tel.: 33-1-39-54-9113
A2M
Merignac, France
Tel.: 33-1-56-34-1097
Betea S.A.
St.-Stevens-Woluwe,
Belgium
Tel.: 322-725-1080
Aquitech
Merignac, France
Tel.: 33-56-55-1830
DENMARK
Aquitech
Cedex, France
Tel.: 33-1-4-96-9494
ExatecAiS
Copenhagen, Denmark
Tel.: 45-31-191022
FINLAND
ComodoOy
Helsinki, Finland
Tel.: 358-0757-2266
FRANCE
lOT
(So. Europe Reg. Office)
15 Rue du Buisson aux
Fraises
91300 Massy, France
Tel.: 33-1-69-30-89-00
Scientec REA
Bordeaux, France
Tel.: 33-56-39-3271
Scientec REA
Chatillon, France
Tel.: 33-149-652750
Scientec REA
Cesson-Sevigne, France
Tel.: 33-99-83-9898
Scientec REA
Rognes, France
Tel.: 33-42-50-1805
Aquitech
Rennes, France
Tel.: 33-99-78-3132
Aquitech
Lyon, France
Tel.: 33-72-73-2412
GERMANY
Scantec GmbH
Ruckersdorf, Germany
Tel.: 49-91-157-9529
Topas Electronic GmbH
Hannover, Germany
Tel.: 49-51-113-1217
Topas Electronic GmbH
Quickborn, Germany
Tel.: 49-4106-73097
HONG KONG
lOT
(Hong Kong Reg. Office)
Rm.1505,
15/F The Centre Mark,
287-299 Queen's Road
Central
Hong Kong
Tel.: 852-542-0067
Lestina International Ltd.
Kowloon, Hong Kong
Tel.: 852-735-1736
INDIA
Malhar Corp.
Bryn Mawr, PA
Tel.: 215-527-5020
ISRAEL
lOT
Vectronics, Ltd.
(Central Europe Reg.
Herzlia, Israel
Office)
Gottfried-Von-Cramm-Str. 1 Tel.: 972-52-556070
8056 Neufahrn, Gennany
Tel.: 49-8165-5024
ITALY
Jermyn GmbH
Limburg, Germany
Tel.: 49-6431/508-0
Lasi Electronica
Bologna, Italy
Tel.: (3951) 353815
Jermyn GmbH
Berlin, Germany
Tel.: 49-3012142056
Lasi Electronica
Firenze, Italy
Tel.: (3955) 582627
Jermyn GmbH
Dusseldorf, Germany
Tel.: 49-211/25001-0
Lasi Electronica
Milano, Italy
Tel.: (39) 266-101370
Jermyn GmbH
Heimstetten, Germany
49-89/909903-0
Lasi Electronica
Roma, Italy
Tel.: (19396) 5405301
Jermyn GmbH
Herrenberg, Germany
Tel.: 49-7032/203-01
lOT
(Japan Headquarters)
U.S. Bldg. 201
1-6-15 Hirakarasho,
Chiyoda-Ku
Tokyo 102, Japan
Tel.: 813-3221-9821
Dia Semicon Systems
Tokyo, Japan
Tel.: 813-3439-2700
Kanematsu Semiconductor
Corp.
Tokyo, Japan
Tel.: 813-3551-7791
Marubun
Tokyo, Japan
Tel.: 813-3639-9805
Tachibana Tectron Co., Ltd.
Tokyo, Japan
Tel.: 813-3793-1171
KOREA
Eastern Electronics
Seoul, Korea
Tel.: 822-553-2997
Anatronic, S.A.
Barcelona, Spain
Tel.: 34-3-258-1906
SWEDEN
Svensk Teleindustri AB
Spanga, Sweden
Tel.: 46-8-761-7300
SWITZERLAND
ElbatexAG
Hardstrasse 72
CH-5430 Wettingen
Switzerland
Tel.: 011-41-56275-777
TAIWAN
Johnson Trading Company
Taipei, Taiwan
Tel.: 886-273-31211
World Peace Industrial Co.,
Ltd.
Taipei, Taiwan
Tel: 886-2788-5200
UTC
Taipei, Taiwan
Tel.: 886-2-7753666
UNITED KINGDOM
lOT
(European Headquarters!
No. Europe Reg. Office)
21 The Crescent
Leathemead
Surrey, UK KT228DY
Tel.: 44-0372-363-339/734
NETHERLANDS
Micro Call, Ltd.
Thame Oxon, UK
Tel.: 44-844-261-939
Auriema
Eindhoven, Netherlands
Tel.: 31-40-816565
The Access Group Ltd.
Hertfordshire, UK
Tel.: 0462-480888
NORWAY
EltronAiS
Oslo, Norway
Tel.: 47-2-500650
SINGAPORE
Data Source Pte. Ltd.
Lorong, Singapore
Tel.: 65-291-8311
SOUTH AMERICA
Intectra Inc.
Mountain View, CA
Tel.: 415-967-8818
SPAIN
Anatronic, S.A.
Madrid, Spain
Tel.: 34-1-542-5566
Integrated
Device Technology, Inc.
2975 Stender Way
Santa Clara, CA 95054-3090
(BOO) 345-7015 FAX: (408) 492-8674
(j
Recycled Paper
C Copyright 1992 Integrated Device Technology. Inc.
Printed in U.S.A .
DBK-LOGIC-00072
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:03 16:52:44-08:00 Modify Date : 2013:08:03 20:57:40-07:00 Metadata Date : 2013:08:03 20:57:40-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:e9171729-d749-1f4e-9853-a2f22ace7cdf Instance ID : uuid:5b81a5ce-fee2-7e4c-84db-005970acac21 Page Layout : SinglePage Page Mode : UseNone Page Count : 770EXIF Metadata provided by EXIF.tools