1992_IDT_Specialized_Memories_and_Modules 1992 IDT Specialized Memories And Modules
User Manual: 1992_IDT_Specialized_Memories_and_Modules
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1992
J
DATA
BOOK
'
Integrated Device Technology, Inc.
1992
SPECIALIZED MEMORIES
& MODULES
DATA BOOK
2975 Stender Way, Santa Clara, California 95054
Telephone: (408}727-6116 • TWX: 910-338-2070 • FAX: (408) 492-8674
Printed in U.S.A.
((:)1992 Integrated Device Technology, Inc.
GENERAL INFORMATION
CONTENTS OVERVIEW
For ease of use for our customers, Integrated Device Technology provides four separate data books
Logic, Specialized Memories and Modules, RISC and RISC SubSystems, and Static RAM.
lOT's 1992 Specialized Memories and Modules Data Book is comprised of new and revised data sheets
for the FIFO, Specialty Memory and Subsystem product groups. Also included is a current packaging
section for the products included in this book. This section will be updated in each subsequent data book
to reflect packages offered for products included in that book.
The 1992 Specialized Memories and Modules Data Book's Table of Contents contains a listing of the
products contained in that data book only. In the past we have included products that appeared in other
lOT data books. The numbering scheme for the book is consistent with the 1990-91 data books. The
number in the bottom center of the paga denotes the section number and the sequence of the data sheet
within that section, (i.e. 5.5 would be the fifth data sheet in the fifth section). The number in the lower right
hand corner is the page number of that particular data sheet.
Integrated 0 evice Technology, a recognized leader in hig h-speed CMOS technology, produces a broad
line of products. This enables us to provide a complete CMOS solution to designers of high-performance
digital systems. Not only do our product lines include industry standard devices, they also feature products
with faster speed, lower power, and package and/or architectural benefits that allow the designer to
achieve significantly improved system performance.
-
To find ordering information: Ordering Information for all products in this book appears in Section
1, along with the Package Outline Index, Product Selector Guides, and Cross Reference Guides.
Reference data on our Technology Capabilities and Quality Commitments is included in separate sections
(2 and 3, respectively).
To find product data: Start with the Table of Contents, organized by product line (page 1.2), or with
the Numeric Table of Contents (page 1.4). These indexes will direct you tothe page on which the complete
technical data sheet can be found. Data sheets may be of the following type:
ADVANCE INFORMATION - contain initial descriptions, subject to change, for products that are in
development, including features and block diagrams.
PRELIMINARY - contain descriptions for products soon to be, or recently, released to production,
including features, pinouts and block diagrams. Timing data are based on simulation or initial characterization and are subject to change upon full characterization.
FINAL - contain minimum and maximum limits specified over the complete supply and temperature
range for full production devices.
New products, product performance enhancements, additional package types and new product
families are being introduced frequently. Please contact your local lOT sales representative to determine
the latest device specifications, package types and product availability.
ABOUT THE COVER
The cover features an IDT7025. wafer shown at approximately 2.5x magnification along with an
IDT7MP6086 module shown at 1x magnification. The IDT7025 is a 30ns 8K x 16 dual-port which is the
deepest dual-port available in the industry, offering simultaneous access to memory from either port. The
IDT7MP6086 is one of lOT's CacheRAMTM modules. Available in a variety of configurations, and using
the IDT71589 Cache RAM as a base, these cache modules offer up to 256KBytes of secondary cache in
high-performance 486 microprocessor designs.
1.1
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components In life support devices or systems
unless a specific written agreement pertaining to such Intended use Is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical Implant Into the body or (b) support
or sustain life and whose failure to perform, when properly used In accordance with Instructions for use provided in the
labeling, can be reasonably expected to result In a significant Injury to the user.
2. A critical component Is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any circuitry described other than the circuitry
embodied in an lOT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use .. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device
Technology, Inc.
'
. ,
The IDTlogo is a registered trademiuk, and BUSMUX, Flexi-pak, BiCEMOS, CacheRAM, CEMOS, FASTX, Flow-thruEDC,IDT/c, IDT/envY, IDT/sae , lOTI
sim, IDT/ux, MacStation, REAL8, RISC SubSystem, RISController, RISCore, Smart Logic, SyncFIFO,TargetSystem, R3051 , and R3081 are trademarks of
Integrated Device Technology, Inc.
All other trademarks are trademarks of their respective companies.
1.1
2
1992 SPECIALIZED MEMORIES & MODULES DATA BOOK
TABLE OF CONTENTS
PAGE
GENERAL INFORMATION
Contents Overview............. ... ... ... ... ........ ... ... ... ..... ...... ... ... ........... ... ...... ................. ..... ...... ...... ... ..... ... ... ... ........... ...
Table of Contents ................. .............. ... ... ... ... ........ ...... ... ..... ... ... ... ........... ......... ........ ...... ... ... ... ..... ... ... ... ........ ... ....
Numeric Table of Contents ...................................................................................................................................
Ordering Information .......................................... ......................... ............... ..... .............................................. ........
lOT Package Marking Description ................ ......... ..... ............... ...................... ............ .............. ................. ..........
FIFO Product Selector Guide ...............................................................................................................................
Specialty Memory Product Selector Guide ...........................................................................................................
Subsystems Product Selector Guide ................................................................... ...... ................................. ..........
FIFO Cross Reference Guide ...............................................................................................................................
Specialty Memory Cross Reference Guide.. .............. ............................. ..............................................................
Subsystems Cross Reference Guide ....................................................................................................................
1 .1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
TECHNOLOGY AND CAPABILITIES
10T... Leading the CMOS Future ...........................................................................................................................
lOT Military and OESC-SMO Program .............................. ....................................................................................
Radiation Hardened Technology ..........................................................................................................................
lOT Leading Edge CEMOS Technology ...............................................................................................................
Surface Mount Technology ...................................................................................................................................
State-of-the-Art Facilities and Capabilities ............................................................................................................
Superior Quality and Reliability .............................................................................................................................
2.1
2.2
2.3
2.4
2.5
2.6
2.7
QUALITY AND RELIABILITY
Quality, Service and Performance ........................................................................................................................
lOT Quality Conformance Program ......................................................................................................................
Radiation Tolerant/Enhanced/Hardened Products for Radiation Environments ...................................................
3.1
3.2
3.3
PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for lOT's Packages .. ................. ......................................................... ...........
Package Diagram Outline Index ......................................................................... ..................................................
Monolithic Package Diagram Outlines ............. ............... .............. .................... .................................. ..................
4.1
4.2
4.3
FIFO PRODUCTS
IOT7200
IOT7201
IOT7202
IOT7203
IOT7204
IOT7205
IOT7206
IOT72005
IOT72015
IOT72025
IOT72021
IOT72031
IOT72041
IOT72103
IOT72104
IOT72105
IOT72115
IOT72125
256 x 9-Bit Parallel FIFO ...........................................................................................
512 x 9-Bit Parallel FIFO ...........................................................................................
1024 x 9-Bit Parallel FIFO .........................................................................................
2048 x 9-Bit Parallel FIFO .........................................................................................
4096 x 9-Bit Parallel FIFO ............. ........................................ ... ... .............. ................
8192 x 9-Bit Parallel FIFO .........................................................................................
16384 x 9-Bit Parallel FIFO .................................................. ......... ..... .................... ...
256 x 18-Bit Parallel First-In/First-Out FIFO .. ........ ... .................................................
512 x 18-Bit Parallel First-In/First-Out FIFO .......... ... ..................................... ............
1 K x 18-Bit Parallel First-In/First-Out FIFO ................................................................
1 K x 9-Bit Parallel Flagged FIFO with OE .................................................................
2K x 9-Bit Parallel Flagged FIFO with OE .................................................................
4K x 9-Bit Parallel Flagged FIFO with OE .................................................................
2048 x 9-Bit ConfigurableParaliel/Serial FIFO ...........................................................
4096 x 9-Bit Configurable Parallel/Serial FIFO ..... ... ...................... ... ... ... ........ ... ........
256 x 16-Bit Parallel-to-Serial FIFO ............. ......... ......................... ............... .............
512 x 16-Bit ParalieHo-Serial FIFO ...........................................................................
1024 x 16-Bit Parallel-to-Serial FIFO ............................................. ............................
1.2
5.1
5.1
5.1
5.2
5.2
5.2
5.2
5.3
5.3
5.3
5.4
5.4
5.4
5.5
5.5
5.6
5.6
5.6
II
1992 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED) ..................... PAGE
FIFO PRODUCTS (CONTINUED)
IDT72131
2048 x 9-Bit Parallel-to-Serial FIFO ................... ........................................................ 5.7
IDT72141
4096 x 9-Bit Parallel-to-Serial FIFO ........................................................................... 5.7
2048 x 9-Bit Parallel/Serial FIFO ............................................................................... 5.8
IDT72132
4096 x 9-Bit Parallel/Serial FIFO ............................................................................... 5'.8
IDT72142
256 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................... 5.9
IDT72200
512 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................... 5.9
IDT72210
1024 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ................................................... ; 5.9
IDT72220
2048 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................; 5.9
IDT72230
4096 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................... ........................... 5.9
IDT72240
64 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ................... .............. ....................... 5.9
IDT72420
256 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................... 5.10
IDT72201
512 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................... 5.10
IDT72211
1024 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) .................................................... 5.10
IDT72221
2048 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ........ ......................... ................... 5.10
IDT72231
4096 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) .................................................... 5.10
IDT72241
64 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ........................................................ 5.10
IDT72421
512 x 18-Bit Parallel Synchronous FIFO .................................................................... 5.11
IDT72215
1024 x 18-Bit Parallel Synchronous FIFO ............................................................ ,.... 5.1.1
IDT72225
256 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ............. ............... ........... ............. 5.12
IDT72205LB
512 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) .. ... ........ ....................................... 5.12
IDT72215LB
1024 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) .................................................. 5.12
IDT72225LB
2048 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ............. ............... ...................... .5.12
IDT72235LB
4096 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..... ........... .............. ................. ... 5.12
IDT72245LB
64 x 4-Bit Parallel FIFO ............................................................................................. 5.13
IDT72401
64 x 5-Bit Parallel FIFO ......................... ..... ............................................................... 5.13
IDT72402
64 x 4-Bit Parallel FIFO (w/Output Enable) ............................................................... 5.13
IDT72403
64 x 5-Bit Parallel FIFO (w/Output Enable) ............................................................... 5.13
IDT72404
64 x 5-Bit Parallel FIFO with Flags ............................................................................ 5.14
IDT72413
512 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO ...................................... 5.15
IDT7251
512 x 18-Bit -1 K x 9-Bit Bus Matching Bidirectional FIFO ...................................... 5.15
IDT72510
1024 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO .................................... 5.15
IDT7252
1024 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO .................................... 5.15
IDT72520
512 x 18-Bit Parallel Bidirectional FIFO ................................. .................................... 5.16
IDT72511
1024 x 18-Bit Parallel Bidirectional FIFO ................................................................... 5.16
IDT72521
256 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ........................... 5.17
IDT72605
512 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ..... ...................... 5.17
IDT72615
512 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO .......................... 5.18
IDT7271
1024 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ........................ 5.18
IDT7272
2048 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ........................ 5.18
IDT7273
FIFO MODULES
Please refer to Subsystems Products listing for FIFO Modules.
SPECIALTY MEMORY PRODUCTS
IDT7130SNLA
IDT7140SA/LA
IDT7030SNLA
IDT7040SNLA
IDT7132SA/LA
IDT7142SNLA
IDT7032SNLA
IDT7042SNLA
IDT71321 SNLA
IDT71421 SNLA
8K (1 K x 8) Dual-Port RAM (Master) .......................................... ...............................
8K (1 K x 8) Dual-Port RAM (Slave) .............................. :............................................
8K (1 K x 8) Dual-Port RAM (Master) .......... ...............................................................
8K (1 K x 8) Dual-Port RAM (Slave) ...........................................................................
16K (2K x 8) Dual-Port RAM (Master) ......................... ........... ...................................
16K (2K x 8) Dual-Port RAM (Slave) .........................................................................
16K (2K x 8) Dual-Port RAM (Master) ........ ........... ............................ ... ...... ...............
16K (2K x 8) Dual-Port RAM (Slave) .................................................. ...... .................
16K (2K x 8) Dual-Port RAM (Master with Interrupts) ...............................................
16K (2K x 8) Dual-Port RAM (Slave with Interrupts) .................................................
1.2
6.1
6.1
6.2
6.2.
6.3
6.3
6.4
6.4
6.5
6.5
2
1992 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED)
PAGE
SPECIALTY MEMORY PRODUCTS (CONTINUED)
IDT7012
18K (2K x 9) Dual-Port RAM .....................................................................................
IDT70121 S/L
18K (2K x 9) Dual-Port RAM (Master with Busy and Interrupt) .................................
IDT70125S/L
18K (2K x 9) Dual-Port RAM (Slave with Busy and Interrupt) .. ... ..... ...... ... ...... ... .......
IDT7133SAlLA
32K (2K x 16) Dual-Port RAM (Master) .....................................................................
IDT7143SAlLA
32K (2K x 16) Dual-Port RAM (Slave) " ................. ... ........ ......... ........... .............. .......
IDT7134SAlLA
32K (4K x 8) Dual-Port RAM .....................................................................................
IDT71342SAlLA
32K (4K x 8) Dual-Port RAM (with Semaphore) ........................................................
36K (4K x 9-Bit) Dual-Port RAM ................................................................................
IDT7014S
IDT7099S
36K (4K x 9) Synchronous Dual-Port RAM ...............................................................
IDT7005S/L
64K (8K x 8) Dual-Port RAM .....................................................................................
IDT7024S/L
64K (4K x 16) Dual-Port RAM....................................................................................
IDT7006S/L
128K (16K x 8) Dual-Port RAM ...................... ................................................... ........
IDT7025S/L
128K (8K x 16) Dual-Port RAM ......................................................................... ........
IDT7050S/L
8K (1 K x 8) FourPort™ Static RAM ...........................................................................
IDT7052S/L
16K (2K x 8) FourPort™ Static RAM .........................................................................
6.6
6.7
6.7
6.8
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
II
MULTI-PORT MODULES
Please refer to Subsystems Products listing for Multi-Port Modules
SUBSYSTEMS PRODUCTS
CUSTOM MODULES
Subsystem Custom Module Capabilities ..............................................................................................................
7.1
MULTI-PORT MODULES
IDT70M74
4K x 16 FourPort™ Static RAM Multichip Module ................................................... ..
IDT7M1002
16K x 32 Dual-Port Static RAM Module ....................................................................
4K x 36 BiCMOS Dual-Port Static RAM Module ...................................................... .
IDT7M1014
IDT7M1024
4K x 36 Synchronous Dual-Port Static RAM Module ............................................... .
IDT7M1012
2K x 36 Dual-Port Static RAM Module ......................................................................
IDT7MB6036
128K x 16 Dual-Port RAM (Shared Memory Module) .............................................. .
64K x 16 Dual-Port RAM (Shared Memory Module) ................................................ .
IDT7MB6046
IDT7MB1006
64K x 16 Dual-Port Static RAM Module ....................................................................
32K x 16 Dual-Port RAM (Shared Memory Module) ................................................ .
IDT7MB6056
32K x 16 Dual-Port Static RAM Module ....................................................................
IDT7MB1008
16K x 9 Dual-Port Static RAM Module ..................................................................... .
IDT7M1005
IDT7M1004
8K x 9 Dual-Port Static RAM Module ...................................................................... ..
IDT7M1001
128K x 8 Dual-Port Static RAM Module ....................................................................
IDT7MP1021
128K x 8 Dual-Port Static RAM Module ....................................................................
IDT7M1003
64K x 8 Dual-Port Static RAM Module ......................................................................
IDT7MP1023
64K x 8 Dual-Port Static RAM Module ......................................................................
7.2
7.3
7.4
7.5
7.6
7.7
7.7
7.8
7.8
7.8
7.9
7.9
7.10
7.11
7.10
7.11
FIFO MODULES
IDT7MP2009
IDT7MP2010
IDT7M208
IDT7M207
32K x 18 CMOS Parallel In-Out FIFO Module ......................................................... ..
16K x 18 CMOS Parallel In-Out FIFO Module .......................................................... .
64K x 9 Parallel In-Out FIFO Module ........................................................................
32K x 9 Parallel In-Out FIFO Module ...................................................................... ..
7.12
7.12
7.13
7.13
SRAM MODULES
IDT7MP4104
IDT7M4077
IDT7MB4067
IDT7MP4045
IDT7M4013
IDT7MP4036
1M x 32 BiCMOS/CMOS Static RAM Module ......................................................... ..
256K x 32 BiCMOS/CMOS Static RAM Module ...................................................... ..
256K x 32 Static RAM Module ...................................................................................
256K x 32 BiCMOS/CMOS Static RAM Module ....................................................... .
128K x 32 Static RAM Module ...................................................................................
64K x 32 BiCMOS/CMOS Static RAM Module ......................................................... .
7.14
7.15
7.16
7.17
7.18
7.19
1.2
3
1992 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED)
PAGE
SRAM MODULES (CONTINUED)
IDT7M4003
32K x 32 Static RAM Module.....................................................................................
IDT7MP4031
16K x 32 BiCMOS/CMOS Static RAM Module ..........................................................
IDT7MB4065
256K x 20 BiCMOS/CMOS Static RAM Module ........................................................
IDT7MP4047
512K x 16 Static RAM Module...................................................................................
IDT7MB4066
256K x 16 BiCMOS/CMOS Static RAM Module ........................................................
IDT7MP4046
256K x 16 Static RAM Module...................................................................................
IDT7MP4027
64K x 16 BiCMOS/CMOS Static RAM Module ..........................................................
IDT7MB4040
256K x 9 Static RAM Module .....................................................................................
IDT7MB4084
2M x 8 Static RAM Module ........................................................................................
IDT7MP4059
2M x 8 Static RAM Module ........................................................................................
IDT7M4048
512K x 8 Commercial BiGMOS/CMOS Static RAM Module......................................
IDT7MB4048
512K x 8 Commercial BiCMOS/CMOS Static RAM Module......................................
512K x 8 Military Static RAM Module ........................................................................
IDT7M4048
512K x 8 Static RAM Module .....................................................................................
IDT7MP4058
IDT7M4068
256K x 8 Commercial BiCMOS/CMOS Static RAM Module ......................................
256K x 8 Commercial BiGMOS/CMOS Static RAM Module ......................................
IDT7MB4068
256K x 8 Military Static RAM Module ........................................................................
IDT7M4068
256K x 8 Static RAM Module .....................................................................................
IDT7MP4034
7.18
7.20
7.21
7.22
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.27
7.28
7.29
7.30
7.30
7.31
7.32
SRAM MONOLITHICS
IDT71 M024
IDT71 M025
128K x 8 Static RAM Monolithic ................................................................................
128K x 8 Static RAM Monolithic ................................................................................
7.33
7.33
CACHE MODULES
IDT7MP6094
IDT7MP6084
IDT7MP6074
IDT7MP6087
IDT7MP6085
IDT7MB6089
IDT7MB6091
IDT7MP6086
IDT7MP6048
IDT7MP6068
4MB IDT79R4000 Secondary Cache Module Block Family......................................
1MB IDT79R4000 Secondary Gache Module Block Family......................................
256K IDT79R4000 Secondary Cache Module Block Family.....................................
256K Byte Secondary Cache Module for the Intel™ i486™ ......................................
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
128K Byte Secondary Cache Module for the Intel™ i486™ ......................... .............
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT79R4000 FLEXI-CACHETM Development Tool....................................................
IDT79R4000 FLEXI-CACHETM Development Tool....................................................
7.34
7.34
7.34
7.35
7.35
7.36
7.37
7.38
7.39
7.39
OTHER MODULES
Flexi-Pak Family
IDT7M7004
IDT7M7005
IDT7MP9244T/AT/CTZ
IDT7MP9245T/AT/CTZ
Modules with Various Combinations of SRAMs, EPROMs and EEPROMs ..............
32K x 32 EEPROM Module .......................................................................................
32K x 16 Static RAM/EEPROM Module ....................................................................
Fast CMOS 32-Bit Buffer/Line Driver Module............................................................
Fast CMOS 32-Bit Bidirectional Transceiver Module ................................................
7.40
7.41
7.42
7.43
7.43
IDT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS
1.2
4
NUMERICAL TABLE OF CONTENTS
PART NO.
IDT7005S/L
IDT7006S/L
IDT7012
IDT70121 S/L
IDT70125S/L
IDT7014S
IDT7024S/L
IDT7025S/L
IDT7030SNLA
IDT7032SNLA
IDT7040SNLA
IDT7042SNLA
IDT7050S/L
IDT7052S/L
IDT7099S
IDT70M74
IDT7130SNLA
IDT71321 SNLA
IDT7132SNLA
IDT7133SNLA
IDT71342SNLA
IDT7134SNLA
IDT7140SNLA
IDT71421SNLA
IDT7142SNLA
IDT7143SNLA
IDT71 M024
IDT71 M025
IDT72005
IDT7200S/L
IDT72015
IDT7201SNLA
IDT72021
IDT72025
IDT7202SNLA
IDT7203
IDT72031
IDT7204
IDT72041
IDT7205
IDT7206
IDT72103
IDT72104
IDT72105
IDT72115
IDT72125
IDT72131
IDT72132
IDT72141
IDT72142
IDT72200
IDT72201
IDT72205LB
IDT72210
PAGE
64K (8K x 8) Dual-Port RAM ..................................................................................... 6.13
128K (16K x 8) Dual-Port RAM .... ;................. :.......................................................... 6.15
18K (2K x 9) Dual-Port RAM ................ ...... ..................... ...... ........ ...... ................. ...... 6.6
18K (2K x 9) Dual-Port RAM (Master with Busy and Interrupt) ..... ;;.......................... 6.7
18K (2K x 9) Dual-Port RAM (Slave with Busy and Interrupt) .................................... 6.7
36K (4K x 9-Bit) Dual-Port RAM .. ........... ...... ........... ................. ......... ........ ................ 6.11,
64K (4K x 16) Dual-Port RAM ..................... ;.. ~ ..... ;......... ;........................................... 6:14
128K (8K x 16) Dual-Port RAM .........................................:....................................... 6.16,
8K (1 K x 8) Dual-Port RAM (Master) ............................................... :......................... 6.2
16K (2K x 8) Dual-Port RAM (Master) .......... '; .... ; ...................................................... ; 6.4
8K (1 K x 8) Dual-Port RAM (Slave) .............................. :............................................ 6.2
16K (2K x 8) Dual-Port RAM (Slave) .............................................................. ........... 6.4 .
8K (1 K x 8) FaurPart™ Static RAM ............................................... :........................... 6.17
16K (2K x 8) FourPart™ Static RAM .............................................................. ........... 6.18
36K (4K x 9) Synchronous Dual-Port RAM ..................;............................................ 6.12
4K x 16 FaurPort™ Static RAM Multichip Module ..................................................... 7.2
8K (1 K x 8) Dual-Port RAM (Master) ......................................................................... 6.1
16K (2K x 8) Dual-Port RAM (Master with Interrupts) ..... :......................................... 6.5
16K (2K x 8) Dual-Port RAM (Master) .............................'.......................................... 6:3
32K (2K x 16) Dual-Port RAM (Master) ..................................................................... 6.8'
32K (4K x 8) Dual-Port RAM (with Semaphore) ..................... ;.... ;.... :........................ 6.10
32K (4K x 8) Dual-Port RAM ........................ ; ................................... ;......................... 6.9
8K (1 K x 8) Dual-Port RAM (Slave) ................................................. ;......................... 6.1
16K (2K x 8) Dual-Port RAM (Slave with Interrupts) ................................................. 6.5
16K (2K x 8) Dual-Port RAM (Slave) ......................................................................... 6.3
32K (2K x 16) Dual-Port RAM (Slave) ........................... ~;........................................... 6.8
128K x 8 Static RAM Module ....... ;........................................ ;.................................... 7.33
128K x 8 Static RAM Module..................................................................................... 7.33'
256 x 18-Bit Parallel First-ln/First-Out FIFO ................................ :............................. 5.3
256 x 18-Bit Parallel First-ln/First-Out FIFO .............................................................. 5.1
512 x 18-Bit Parallel First-ln/First-Out FIFO .................................................. ............ 5.3
512 x 18-Bit Parallel First-ln/First-Out FIFO.............................................................. 5.1
1 K x 9-Bit Parallel Flagged FIFO with OE ................................................................. 5.4.
1 K x 18-Bit Parallel First-ln/First-Out FIFO .... : ........ :.................................................. , 5.3
1 K x 18-Bit Parallel First-ln/First-OutFIFO .:............... ;.............................................. 5.1
2048 x 9-Bit Parallel First-lnlFirstOut FIFO ............................................................... 5.2
2K x 9-Bit Parallel Flagged FIFO with OE ........ ;........ ~............................................... 5.4
4096 x 9-Bit Parallel First-ln/FirstOut FIFO ............. :................................................. ' . 5.2
4K x 9-Bit Parallel Flagged FIFO-with OE .......................... ;: ...................................... 5.4
8192 x 9-Bit Parallel First-lnlFirstOut FIFO ............................................................... 5.2,
16384 x 9-Bit Parallel First-ln/FirstOut FIFO .............................................................. 5.2
2048 x 9-Bit CanfigurableParaliellSerial FIFO ...... ;........................... :........................ 5.5'
4096 x 9-Bit Canfigurable Parallel/Serial FIFO ............. ;............................................ 5.5
256 x 16-Bit Parallel-to-Serial FIFO ................................. :: ........................................ ' 5.6'
512 x 16-Bit Parallel-to-Serial FIFO ............................................... ;........................... 5.6
1024 x 16~Bit Parallel-to-Serial FIFO .................... ;....... ~ ...... ;..................................... ' 5.6
2048 x 9-Bit Parallel-to-Serial FIFO .................... :...... ;............................................... 5.7
2048 x 9-Bit Parallel/Serial FIFO ..................................................;.;.......................... 5.8,
4096 x 9-Bit Parallel-to-Serial FIFO ............................... ;........................................... 5.7
4096 x 9-Bit Paraliel/Serial FIFO ......................... :..................................................... 5.8
256 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ...................................................... ,5.9
256 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) .... ;................................................. 5.10
256 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) .................................................... 5.12
512 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) .......... ~ ................. ;......................... ' 5.9,
1.3
II
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
IOT72211
IOT72215
IOT72215LB
IOT72220
IOT72221
IOT72225
IOT72225LB
IOT72230
10T72231
IOT72235LB
IOT72240
IOT72241
IOT72245LB
IOT72401
IOT72402
IOT72403
IOT72404
IOT72413
IOT72420
IOT72421
IOT7251
IOT72510
IOT72511
IOT7252
IOT72520
IOT72521
IOT72605
IOT72615
IOT7271
IOT7272
IOT7273
IOT7M1001
IOT7M1002
IOT7M1003
IOT7M1004
IOT7M1005
IOT7M1012
IOT7M1014
IOT7M1024
IOT7M207
IOT7M208
IOT7M4003
IOT7M4013
IOT7M4048
IOT7M4048
IOT7M4068
IOT7M4068
IOT7M4077
IOT7M7004
IOT7M7005
IDT7MB1006
IOT7MB1008
IOT7MB4040
IOT7MB4048
PAGE
512 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ................... '...................................
512 x 18-Bit Parallel Synchronous FIFO ...................................................................
512 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..... ............................ ...................
1024 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
1024 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ................ ............ ..... ...................
1024 x 18-Bit Parallel Synchronous FIFO ................ .................... .............................
1024 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..... ........... ......... .........................
2048 x 8-Bit Parallel SyncFIFOrM (Clocked FIFO) ........ ............................................
2048 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) .. .............. ......... ..... ............ ..........
2048 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ................... ...... .........................
4096 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
4096 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ........ .................... ..... ...................
4096 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..................................................
64 x 4-Bit Parallel FIFO .............................................................................................
64 x 5-Bit Parallel FIFO ................................................................ ............... ..............
64 x 4-Bit Parallel FIFO (w/Output Enable) ...............................................................
64 x 5-Bit Parallel FIFO (w/Output Enable) ..... ;.........................................................
64 x 5-Bit Parallel FIFO with Flags ............................................................................
64 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................... ...............................
64 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) .............................. ..........................
512 x 18-Bit -1 K x 9-Bit Bus Matching Bidirectional FIFO ......................................
512 x 18-Bit -1 K x 9-Bit Bus Matching Bidirectional FIFO ......................................
512 x 18-Bit Parallel Bidirectional FIFO .......... .................... ...... ......... ..... ...................
1024 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO .......... ....................... ...
1024 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO ........ ............................
1024 x 18-Bit Parallel Bidirectional FIFO ................................................................ ...
256 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ...........................
512 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ...........................
512 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ..........................
1024 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ........................
2048 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ........................
128K x 8 Dual-Port Static RAM Module ....................................................................
16K x 32 Dual-Port Static RAM Module ....................................................................
64K x 8 Dual-Port Static RAM Module ......................................................................
8K x 9 Dual-Port Static RAM Module ........................................................................
16K x 9 Dual-Port Static RAM Module ......................................................................
2K x 36 Dual-Port Static RAM Module ......................................................................
4K x 36 BiCMOS Dual-Port Static RAM Module .......................................................
4K x 36 Synchronous Dual-Port Static RAM Module ................................................
32K x 9 Parallel In-Out FIFO Module .......................................... ~.............................
64K x 9 Parallel In-Out FIFO Module ........................................................................
32K x 32 Static RAM Module.....................................................................................
128K x 32 Static RAM Module ...................................................................................
512K x 8 Commercial BiCMOS/CMOS Static RAM Module......................................
512K x 8 Military Static RAM Module ........................................................................
256K x 8 Commercial BiCMOS/CMOS Static RAM Module ......................................
256K x 8 Military Static RAM Module .......................................... ,.............................
256K x 32 BiCMOS/CMOS Static RAM Module........................................................
32K x 32 EEPROM Module .......................................................................................
32K x 16 Static RAM/EEPROM Module .................................•..................................
64K x 16 Dual-Port Static RAM Module ... ;................................................................
32Kx 16 Dual-Port Static RAM Module ....................................................................
256K x 9 Static RAM Module ....................... ;.............................................................
512K x 8 Commercial BiCMOS/CMOS Static RAM Module......................................
1.3
5.10
5.11
5.12
5.9
5.10
5.11
5.12
5.9
5.10
5.12
5.9
5.10
5.12
5.13
5.13
5.13
5.13
5.14
5.9
5.10
5.15
5.15
5.16
5.15
5.15
5.16
5.17
5.17
5.18
5.18
5.18
7.10
7.3
7.10
7.9
7.9
7.6
7.4
7.5
7.13
7.13
7.18
7.18
7.27
7.28
7.30
7.31
7.15
7.42
7.43
7.8
7.8
7.24
7.27
2
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
PAGE
IDT7MB4065
256K x 20 BiCMOS/CMOS Static RAM Module ........................................................
IDT7MB4066
256K x 16 BiCMOS/CMOS Static RAM Module ........................................................
IDT7MB4067
256K x 32 Static RAM Module...................................................................................
IDT7MB4068
256K x 8 Commercial BiCMOS/CMOS Static RAM Module......................................
IDT7MB4084
2M x 8 Static RAM Module ........................................................................................
IDT7MB6036
128K x 16 Dual-Port RAM (Shared Memory Module) ...............................................
IDT7MB6046
64K x 16 Dual-Port RAM (Shared Memory Module) .................................................
IDT7MB6056
32K x 16 Dual-Port RAM (Shared Memory Module) .................................................
IDT7MB6089
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT7MB6091
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT7MB6139
Dual (16K x 60) Data/lnstruction Cache Module for IDT79R3000 CPU ....................
IDT7MP1021
128K x 8 Dual-Port Static RAM Module ....................................................................
IDT7MP1023
64K x 8 Dual-Port Static RAM Module ............................ ......................... ... ...... ........
IDT7MP2009
32K x 18 CMOS Parallel In-Out FIFO Module...........................................................
IDT7MP2010
16K x 18 CMOS Parallel In-Out FIFO Module...........................................................
IDT7MP4027
64K x 16 BiCMOS/CMOS Static RAM Module..........................................................
IDT7MP4031
16K x 32 BiCMOS/CMOS Static RAM Module ..........................................................
IDT7MP4034
256K x 8 Static RAM Module.....................................................................................
IDT7MP4036
64K x 32 BiCMOS/CMOS Static RAM Module ............................................... ...........
IDT7MP4045
256K x 32 BiCMOS/CMOS Static RAM Module ........................................................
IDT7MP4046
256K x 16 Static RAM Module...................................................................................
IDT7MP4047
512K x 16 Static RAM Module...................................................................................
IDT7MP4058
512K x 8 Static RAM Module .....................................................................................
IDT7MP4059
2M x 8 Static RAM Module ........................................................................................
IDT7MP4104
1M x 32 BiCMOS/CMOS Static RAM Module ...........................................................
IDT7MP6048
IDT79R4000 FLEXI-CACHETM Development Tool....................................................
IDT7MP6068
IDT79R4000 FLEXI-CACHETM Development Tool....................................................
IDT7MP6074
256K IDT79R4000 Secondary Cache Module Block Family.....................................
IDT7MP6084
1MB IDT79R4000 Secondary Cache Module Block Family......................................
IDT7MP6085
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT7MP6086
128K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT7MP6087
256K Byte Secondary Cache Module for the Intel™ i486™ ......................................
IDT7MP6094
4MB IDT79R4000 Secondary Cache Module Block Family......................................
IDT7MP9244T/AT/CTZ
Fast CMOS 32-Bit Buffer/Line Driver Module............................................................
IDT7MP9245T/AT/CTZ
Fast CMOS 32-Bit Bidirectional Transceiver Module ................................................
Subsystem Custom Module Capabilities ..............................................................................................................
Flexi-Pak™ Family
Modules with Various Combinations of SRAMs, EPROMs and EEPROMs..............
1~
7.21
7.21
7.16
7.30
7.25
7.7
7.7
7.8
7.36
7.37
7.39
7.11
7.11
7.12
7.12
7.23
7.20
7.32
7.19
7.17
7.22
7.22
7.29
7.26
7.14
7.40
7.40
7.34
7.34
7.35
7.38
7.35
7.34
7.44
7.44
7.1
7.41
3
ORDERING INFORMATION,"
When ordering by TWX or Telex, the following format must be used:
AC (ACTIVITY CODE)'
F = Consult Factory
N = New Part
o = Obsolete Part
D = Decrease in Price'
I = Increase in Price' ,
W = Non Returnable'
• = Leadership Product
% = 5% Program (for
North American Distributors Only)
A. Complete Bin To.
B. Complete Ship To.
C. Purchase Order Number.
D. Certificate of Conformance. Y or N.
E. Customer Source Inspection. Y or N.
F. Government Source Inspection. Y or N ""
G. :Government Contract Number and Rating.
H. Requested Routing.
'
'
I. ' IDT Part Number -'
Each item ordered must use the complete part number exactly as listed in the price i>ook.
J. SCD Number- Specification Control Document (Internal Traveller).
'
K. Customer Part Number/Drawing Number/Revision Level- ,
,"
'
Specify whether part number is for reference only, mark only, or if extended processing to
customer specification is required.
,
'
L. ' Customer General Specification Numbers/Other Referenced Drawing Numbers/Revision Levels.
M~ 'Request DateWith Exact Quantity.
"
,
"
N.. Unit Price.
'
0, ,SpeCial Instructions,lncluding a.A. Clauses, Special Proce,~sing.
Federal Supply Code Number/Cage Number - 61772
Dun & Bradstreet Number - 03-814-2600
Federal Tax 1.0. - 9 4 - 2 6 6 9 9 8 5 " , "
TLX# - 887766
FAX# - 408-727-3468
PART NUMBER DESCRIPTION
A
IDT
= Alpha Character
, XXXXX
A
N = Numeric Character
X
DEVICE TYPE POWER
999
REVISION SPEED
_ _A_,_
A:
__
A_ _
PACKAGE - PROCESS/
SPECIAL
TEMT"T,URE,,'LE::.
,T
~Y'NK
,
B
RADIATION TOLERANT
COMMERCIAL - O°C to +70°C
COMMERCIAL - -55°C to + 125°C'
MILITARY ~ -55°C to + 125°C, (Fully compliant
, t,o MIL-STD-883, Method 5004, Class B)
SEE PACKAGE DESCRIPTION TABLE
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,
SPEED
A
GUARANTEED MINIMUM PERFORMANCE
MEASURED IN NANOSECONDS OR MHz
Blank
POWER
DEVICE
TYPE*"
S
L
-
STANDARD POWER
LOWPOWER
e.g, 6116
PACKAGE DESCRIPTION TABLE
C
D
F
G
J
L
P
Y
CERAMIC SIDEBRAZE
CERDIP
FLAT PACK
PIN GRID ARRAY
PLASTIC LEADED CHIP CARRIER
LEADLESS CHIP CARRIER
PLASTIC DIP
SOJ
PF
SO
TC
TP
QE
XE
XL
·Consult Factory
··For Logic, the "54" series (e,g.IDT54FCT138) - -55°C to +125°C
the "74" series (e.g, IDT74FCT138) - O°C to +70°C
1.4
PLASTIC FLATPACK
PLASTIC SMALL OUTLINE IC
SIDEBRAZE THINDIP (300 MIL)
PLASTIC THIN DUAL IN-LINE
CERQUAD GULL WING
CERPACK (F11 CONFfG, ONLY)
FINE-PITCH LCC
MODULE ORDERING INFORMATION
IDT7M
X
XXXX
x
xxx
xxx
x
-r-
SCDXXXX
IBlank........ Standard Product
~ XXXX........ Special Processing Required
Blank........ COMMERCIAL GRADE VERSION (O°C to +70°C)
B........... Military Grade Version (-55°C to +125°C) Semiconductor
Components Fully Compliant to MIL-STD-883, Class B
'------------1 Package .....
See Table for Package Options
'--------------1 Speed ....... Guaranteed Performance in Nanoseconds
(or Other Specified Parameter)
--I Power........ S - Standard Power
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _
L - Low Power
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I
Device Type
1XXX- Multiport RAM Module
2XXX - FIFO RAM Module
Organization .. 3XXX - DRAM Module
4XXX - SRAM Module
5XXX - Analog Module
6XXX - Application Specific RAM Module
7XXX - Non-volatile RAM Module
8XXX - ECL Module
9XXX - Logic Module
&
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 Substrate
Blank - Horizontally Mounted (Ceramic)
Orientation .... B - Horizontally Mounted (FR-4)
C - Vertically Mounted (Ceramic)
P - Vertically Mounted (FR-4)
Code
Substrate and Pin Type
Component Type
P
FR-4 DIP (Dual In-Line Package)
Plastic
C
CERAMIC DIP (Dual In-Line Package)
Ceramic
N
CERAMIC DIP (Dual In-Line Package)
Plastic
K
FR-4 QIP (Quad In-Line Package)
Plastic
CERAMIC QIP (Quad In-Line Package)
Ceramic
CK
H
CH
NH
G
S
CS
V
FR-4 HIP (Hex In-Line Package)
Plastic
CERAMIC QIP (Quad In-Line Package)
Ceramic
CERAMIC QIP (Quad In-Line Package)
Plastic
CERAMIC PGA (Pin Grid Array)
Ceramic
FR-4 SIP (Single In-Line Package)
Plastic
CERAMIC SIP (Single In-Line Package)
Ceramic
FR-4 DSIP (Dual Single In-Line Package)
Plastic
CERAMIC DSIP (Dual Single In-Line Package)
Ceramic
Z
FR-4 ZIP (Zip-zap In-Line Package)
Plastic
M
FR-4 SIMM (Single In-Line Memory Module)
Plastic
CV
NOTES:
1.
2.
3.
4.
FR-4 is a multi-layered, glass filled epoxy laminate substrate.
Ceramic is a multi-layered, co-fired ceramic substrate.
Plastic refers to all surface mount devices available in various non-hermetically sealed packages (i.e. SOIC, SOJ, Flat Packs, etc.).
Ceramic refers to all surface mount devices available in various hermetically sealed packages {i.e. LCC, ceramic Flat Packs, etc.}.
1.4
2
IDTPACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION
4.
lOT's part number identifies the basic product, speed,
power, package(s) available, operating temperature and
processing grade. Each data sheet has a detailed description,
using the part number, for ordering the proper product for the
user's application. The part number is comprised of a series
of alpha-numeric characters:
5.
1. An "lOT" corporate identifier for Integrated Dev'ice
6.
Technology, Inc.
2. A basic device part number composed of alpha-numeric
characters.
3. A device power identifier, composed of one or two alpha
characters, is used to identify the power options. In most
cases, the following alpha characters are used:
"S" or "SA" is used for the standard product's power.
"L" or "LA" is used for lower power than the standard
product.
7.
A device speed identifier, when applicable, is either alpha
characters, such as "A" or "B", or numbers, such as 20 or
45. The speed units, depending on the product, are in
nanoseconds or megahertz.
A package identifier, composed of one or two characters.
The data sheet should be consulted to determine the
packages available and the package identifiers for that
particular product.
A temperature/process identifier. The product is available
in either the commercial or military temperature range,
processed to a commercial specification, or the product is
available in the military temperature range with full
compliance to MIL-STD-883. Many of lOT's products
have burn-in included as part of the standard commercial
process flow.
A special process identifier, composed of alpha characters,
is used for products which require radiation enhancement
(RE) or radiation tolerance (RT).
Example for Monolithic Devices:
lOT
xxx .. .xxx
xx
x.. x
x... x
x
xx
TL:
Special Process
ProcessfTemperature*
Package·
Speed
Power
Device Type·
• Field Identifier Applicable To All Products
2507 drw 01
ASSEMBLY LOCATION DESIGNATOR
MIL-STD-883C COMPLIANT DESIGNATOR
lOT uses various locations for assembly. These are
identified by an alpha ch'aracter in the last letter of the date
code marked on the package. Presently, the assembly
location alpha character is as follows:
A = Anam, Korea
I = USA
P = Penang, Malaysia
lOT ships military products which are compliant to the latest
revision of MIL-STD-883C. Such products are identified by a
"C" designation on the package. The location of this designator
is specified by internal documentation at lOT.
EXAMPLE FOR SUBSYSTEM MODULES
See Ordering Information (section 1.4), page 2 ..
1.5
High-Speed CMOS FIFOs
• Broadest range of FIFOs in the industry
• 18-bit wide buses
• Highest performance FIFO products
• Read and write clocks can by asynchronous or coincident
• Most innovative FIFO products
• Separate clock and enable for each bus
• MIL-STO-883 compliant
• Programmable depths for Almost-Empty and Almost-Full flags
PARALLEL FIFOs
CLOCKED FIFOs
• Ultra-high performance -
Com'l. - 67MHz and Mil. - 50MHz
• Extremely high performance -
• 8-,9- and 18-bit wide buses fortoday's processors
• High density -
15ns
up to 16K x 9
• Separate clock and enable signals for read and write
• Asynchronous or simultaneous reads and writes
• Read and write clocks can be asynchronous or coincident
• Simple width and depth expansion
• Programmable depths for Almost-Empty and Almost-Full flags
• Space-efficient packaging
• Simple depth and width expansion
• Multiple flags -FUll, Empty and Half-Full
• Various densities -
FLAGGED FIFOs
64 to 4K
BIDIRECTIONAL FIFOs
• Output enable for direct bus connections
• Bus-matching BiFIFOsfor 18-to-9bit,36-to-9bitor36-to-18 bit
connections
• Multiple flags -
• Parallel BiFIFOs for 9-to-9 bit or 18-to-18 bit connections
• Dedicated PIS and SIP architectures in space-efficient
packages
FUll, Empty, Almost-Empty and Almost-Full
PARALLEUSERIAL FIFOs
• Bypass path for direct status/command interchange
• Built-in OMA handshake signals
• Configurable architecture flexibility
CLOCKED BIDIRECTIONAL FIFOs
• FLEXISHIFTfM allows easy serial word width selection
• Ultra-high performance -
• Multiple flags - Full, Full-1, Almost-Full, Half-Full, Almost
Empty, Empty+ 1, Empty
Max.
Data
Max. Speed (ns)
Power
Book
Avail.
Com'l.
Mil.
Pase
~mWl
• Programmable depths for Almost-Empty and Almost- Full flags
40MHz
PIS, SIP, PIP, SIS for design
Part Number
CLOCKED FIFOt
Descrietion
IOT72420
64 x 8
20
15
770
NOW
E 5.8
IOT72200
256 x 8
20
15
770
NOW
E 5.8
10T72210
512 x 8
20
15
770
NOW
E 5.8
10T72220
1K x 8
25
20
770
NOW
E 5.8
10T72230
2Kx 8
25
20
770
NOW
E 5.8
10T72240
4K x 8
25
20
770
NOW
E 5.8
10T72421
64 x 9
20
15
770
NOW
E 5.9
10T72201
256 x 9
20
15
770
NOW
E 5.9
10T72211
512 x 9
20
15
770
NOW
E 5.9
10T72221
1KX 9
25
20
770
NOW
E 5.9
10T72231
2Kx 9
25
20
770
NOW
E 5.9
10T72241
4K x 9
25
20
770
NOW
E 5.9
10T72215L
512 x 18
25
20
1375
NOW
E 5.10
IOT72225L
1K x 18
25
20
1375
NOW
E 5.10
IOT72215LB
512 x 18 (Depth Expandable)
25
20
1375
30'92
E 5.11
E 5.11
IOT72225LB
1K x 18 (Depth Expandable)
25
20
1375
30'92
IOT72235LB
2K x 18 (Depth Expandable)
25
20
1375
NOW
E 5.11
IOT72245LB
4K x 18 ~Oeeth Exeandablel
25
20
1375
NOW
E 5.11
BIDIRECTIONAL FIFOs
10T7251
512 x 18 -
1K x 9 Bus Matching
40
35
1210
NOW
E 5.14
IOT72510
512 x 18 -1 K x 9 Bus Matching
40
35
1210
NOW
E 5.14
IOT72511
512x18-512x18
40
35
1210
NOW
E 5.15
IOT7252
1K x 18 -
40
35
1210
NOW
E 5.14
t -
2K x 9 Bus Matchins
Clocked FIFO speeds are cycle times. All others are access times.
• = additional or new information exists since the publication of Data Book Update 1
1.6
HIGH-SPEED CMOS FIFO
40
35
Max.
Power
!mWl
1210
NOW
Data
Book
Pase
E 5.14
40
35
1265
NOW
E 5.15
512 x 9 Single Memory Bank
TBO
25
825
NOW
E 5.17
IOT7272
1K x 9 Single Memory Bank
TBO
25
825
NOW
E 5.17
IOT7273
2K x 9 Sinsle Memo!J: Bank
TBO
25
825
NOW
E 5.17
Max. Speed (ns)
Mil.
Com'l.
Part Number
Descrietion
IOT72520
IK x 18 -
10T72521
1Kx18-1Kx18
IOT7271
2K x 9 Bus Matching
Avail.
CLOCKED BIDIRECTIONAL FIFOs!
IOT72605
256 x 18 -
IOT72615
512x18-512x18
2562 x 18
30
25
1375
30'92
E 5.16
30
25
1375
NOW
E 5.16
PARALLEL FIFOs
IOT72401
64 x 4
35MHz
45MHz
192
NOW
E 5.12
IOT72402
64 x 5
35MHz
45MHz
192
NOW
E 5.12
10 T724 03
64 x 4 with DE
35MHz
45MHz
192
NOW
E 5.12
IOT72404
64 x 5 with DE
35MHz
45MHz
192
NOW
E 5.12
IDT72413
64 x 5 with DE, Almost-Empty, Almost-Full flags
35MHz
45MHz
192
NOW
E 5.13
IOT7200
256 x 9
20
15
770
NOW
E 5.1
IDT7201
512 x 9
20
15
770
NOW
E 5.1
IDT7202
1K x 9
20
15
770
NOW
E 5.1
IOT7203
2Kx 9
30
20
880
NOW
E 5.2
IDT7204
4K x 9
30
20
880
NOW
E 5.2
IOT7205
8Kx 9
30
20
770
NOW
E 5.2
IDT7206
16K x 9
30
20
880
NOW
E 5.2
IDT72021
IK x 9 with Half-Full, Almost-Empty,
Almost-Full flags and DE
30
25
660
NOW
E 5.3
IOT72031
2K x 9 with Half-Full, Almost-Empty,
Almost-Full flags and DE
40
35
660
NOW
E 5.3
IOT72041
4K x 9 with Half-Full, Almost-Empty,
Almost-Full flass and DE
40
35
660
NOW
E 5.3
FLAGGED FIFOs
PARALLEUSERIAL FIFOs
IOT72103
2K x 9 configurable ParalleVSeriall/O,
multiple flags, 50MHz serial rate and FLEXISHIFT
40
35
770
NOW
E5.4
IOT72104
4K x 9 configurable ParalleVSeriall/O,
multiple flags, 50 MHz serial rate and FLEXISHIFT
40
35
770
NOW
E 5.4
10T72105
256 x 16 dedicated Paraliel-to-SeriaII/O,
50MHz serial shift rate, multiple flags
30
25
550
NOW
E 5.5
IOT72115
512 x 16 dedicated Paraliel-to-SeriaII/O,
50MHz serial shift rate, multiple flags
30
25
550
NOW
E 5.5
IOT72125
1K x 16 dedicated Paraliel-to-SeriaII/O,
50MHz serial shift rate, multiple flags
30
25
550
NOW
E 5.5
IOT72131
2K x 9 dedicated Paraliel-to-SeriaII/O,
50MHz serial rate, multiple flags and FLEXISHIFT
40
35
770
NOW
E 5.6
IOT72132
2K x 9 dedicated Serial-to-ParalleII/O,
50MHz serial rate, multiple flags and FLEXISHIFT
40
35
770
NOW
E5.7
IOT72141
4K x 9 dedicated Paraliel-to-SeriaII/O,
50MHz serial rate, multiple flags and FLEXISHIFT
40
35
770
NOW
E 5.6
IOT72142
4K x 9 dedicated Serial-to-ParalleII/O,
50MHz serial rate, multi~le flass and FLEXISHIFT
40
35
770
NOW
E 5.7
t - Clocked FIFO speeds are cycle times. All others are access times.
• = additional or new information exists since the publication of Data Book Update 1
1.6
2
High-Speed CMOS/BiCMOS Multi-Port RAMs
• Now offering 15ns dual-p'ort SRAMs!
• World's first FourPort™ SRAMs.
• First synchronous dual-port is available and allows for
self-timed write cycles.
• Complete family of x8, x9 and x16 dual-ports.
• Oense dual-ports (128K).
• All dual-ports have true dual-ported memory cells which allow
simultaneous access from both ports.
Part Number
• MIL-STO-883 compliant
Max. Speed (ns)
Mil.
Com'l.
Description
Typical
Power
(mW)
Avail.
Data
Book
Page
DUAL-PORT RAMs
10T7130
8K (1 K x 8) MASTER: industry'S most
popular dual-port SRAM
30
25
325
NOW
E 6.1
IOT7140
8K (1 K x 8) SLAVE: functions with
IOT7130 to provide 16-bit words or
wider; pin-compatible with IOT7130
30
25
325
NOW
E 6.1
10T7030
8K (1 K x 8) MASTER: high-speed
dual-port in OIP package with center-pin ground
30
25
325
NOW
E6.2
IOT7040
8K (1 K x 8) SLAVE: high-speed dual-port
in 01 P package with center-pin ground
30
25
325
NOW
E 6.2
10T7132
16K (2K x 8) MASTER: fastest available
speeds in this industry standard product;
now multiple sources
30
25
325
NOW
E 6.3
10T7142
16K(2K x 8) SLAVE: functions with
IOT7132 to provide 16-bit words or
wider; pin-compatible with 10T7132
30
25
325
NOW
E 6.3
IOT7032
16K (2K x 8) MASTER: high-speed
dual-port in OIP package with center-pin ground
30
25
325
NOW
E6.4
10T7042
16K (2K x 8) SLAVE: high-speed dual-port
in OIP package with center-pin ground
30
25
325
NOW
E6.4
IOT71321
16K (2K x 8) MASTER: high-speed dual-port
with interrupt output
30
25
325
NOW
E 6.5
IOT71421
16K (2K x 8) SLAVE: functions with
IOT71321 to provide 16-bit words or
wider; pin-compatible with IOT71321
30
25
325
NOW
E 6.5
10T7133
32K (2K x 16) MASTER: high-speed
dual-port with busy
35
25
500
NOW
E 6.8
IOT7143
32K (2K x 16) SLAVE: functions with
IOT7133 to provide 32-bit words or wider
35
25
500
NOW
E 6.8
IOT7134
32K (4K x 8) high-speed operation in
systems where on-chip arbitration is not needed
35
25
500
NOW
E 6.9
10T71342
32K (4K x 8) with semaphores
45
35
500
NOW
E 6.10
10T7024
64K (4K x 16) with busy, interrupt
semaphore and master/slave select
35
25
750
NOW
E 6.14
IDT7005
64K (8K x 8) with busy, interrupt,
semaphore and master/slave select
45
35
750
NOW
E 6.13
IOT7025
128K (8K x 16) industry's largest monolithic dual-port RAM with busy, interrupt,
semaphores and master/slave select
35
25
750
NOW
E 6.16
10T7006
128K (16K x 8) with busy, interrupt,
semaphore and master/slave select
45
35
750
NOW
E 6.15
10T7012
18K (2K x 9) high-speed operation in
systems where on-chip arbitration is not needed
30
25
400
NOW
E 6.6
a = additional or new information exists since the publication of Data Book Update 1
1.7
High-Speed CMOS/SiCMOS Multi-Port RAMs
Part Number
IDT70121
Description
18K (2K x 9) MASTER: high-speed dual-port
with busy and interrupt
Max. Speed (ns)
Mil.
Com'l.
30
25
Typical
Power
(mW)
Data
Book
Page
400
Avail.
NOW
E 6.7
18K (2K x 9) SLAVE: functions with
IDT70121 to provide 18-bit words or wider
with busy and interrupt
30
25
400
NOW
E 6.7
IDT7050
8K (1 K x 8) FourPort SRAM offers
increased system performance in
multiprocessor systems that have a need
to communicate in real time
30
25
750
NOW
E 6.17
IDT7052
16K (2K x 8) FourPort SRAM offers added
benefits for high-speed systems in which
multiple access is required in the same cycle
30
25
750
NOW
E 6.18
NOW
E 6.12
NOW
E 6.11
IDT70125
FourPort RAMs
SYNCHRONOUS DUAL·PORT RAM
IDT7099
36K (4Kx 9) Synchronous dual-port with
registered data input, address, and control
lines. Speeds listed are cycle time
BICMOS DUAL·PORT RAM
IDT7014
36K (4K x 9) hjgh~speed; dual-port
prOCessed using our BiCEMOS process
• = additional or new information exists since the
1.7
20
15
publication of Data Book Update 1
2
High-Speed CMOS and BiCMOS Module Products
• High-density, high-performance module products for commercial and military applications
• Standard module products are used in a wide range of applications, such as personal computers, workstations, video systems, data communications, telecommunications, add-on VMEtype cards, test systems, DSP systems, electronic surveillance,
guidance systems, and intelligent controller systems.
• Fully customized module solutions are available to achieve
optimum system integration and performance. Custom modules take advantage of lOT's experienced design, test, and
manufacturing teams all working with the highest- performance
components available.
Part Number
• Modules are built using state-of-the-art techniques in surfacemounttechnology. Typically, monolithic components are doublesided surface mounted onto multi-layered FR-4 epoxy laminate
substrates or co-fired ceramic substrates
• A wide variety of module packages are available offering the
optimum combination of pin count and board area. Some of
these packages include industry standard DIPs, ZIPs, SIMMs
and PGAs, in addition to other unique module packaging, such
as SIPs, DSIPs, QIPs, HIPs, and advanced high-density connectors
• FourPort multichip module available, as well as custom multichip
module capabilities
Max. Speed (ns)
Mil.
Com'l.
Description
Avail.
Data
Book
Pase
CUSTOM MODULES AND MULTICHIP MODULES
Memory-based Modules - SRAM, DRAM, non-volatile RAM
NOW
CPU-based Modules - RISC, CISC, DSP. custom ASIC
NOW
Please consult factory or call your local sales representative for more details.
SRAM MONOLITHICS
IDT71 M024
128K x 8 Static RAM
60
60
NOW
E 7.33
IDT71M025
128K x 8 Static RAM
60
60
NOW
E 7.33
SRAM MODULES
IDT7MP4104
1M x 32 Static RAM Module
20
3Q'92
E 7.14
IDT7MP4045
256K x 32 Static RAM Module
20
NOW
E 7.17
IDT7M4077
256K x 32 Static RAM Module
20
NOW
E 7.15
IDT7MB4067
256K x 32 Static RAM Module
20
NOW
E 7.16
IIDT7M4013
128K x 32 Static RAM Module
20
NOW
E 7.18
IDT7MP4036
64K x 32 Static RAM Module
12
NOW
E 7.19
25
25
25
20
NOW
E 7.18
10
NOW
E 7.20
20
NOW
E 7.21
70
NOW
E 7.22
NOW
E 7.22
IDT7M4003
32K x 32 Static RAM Module
DT7MP4031
16K x 32 Static RAM Module
IDT7MB4065
256K x 20 Static RAM Module
IDT7MP4047
512K x 16 Static RAM Module
IDT7MP4046
256K x 16 Static RAM Module
70
IDT7MB4066
256K x 16 Static RAM Module
20
NOW
E 7.21
IDT7MP4027
64K x 16 Static RAM Module
12
NOW
E 7.23
IDT7MB4040
256K x 9 Static RAM Module
12
NOW
E 7.24
IDT7MB4084
2M x 8 Static RAM Module
55
3Q'92
E 7.25
IDT7MP4059
2M x 8 Static RAM Module
IDT7M4048
512K x 8 Static RAM Module
IDT7MB4048
55
3Q'92
E 7.26
25
NOW
E 7.27
512K x 8 Static RAM Module
25
NOW
E 7.27
IDT7MP4058
512K x 8 Static RAM Module
70
NOW
E 7.29
IDT7M4068
256K x 8 Static RAM Module
IDT7MB4068
256K x 8 Static RAM Module
IDT7MP4034
256K x 8 Static RAM Module
486 MICROPROCESSOR SECONDARY CACHE
30
30
25
NOW
E 7.30
20
NOW
E 7.30
12
NOW
E 7.32
MODULES
IDT7MB6091
128KB Secondary Cache Module forthe 486 CPU
33MHz
NOW
E 7.37
IDT7MB6089
128KB Secondary Cache Module for the 486 CPU
33MHz
NOW
E 7.36
• = additional or new information exists since the publication of Data Book Update 1
1.8
High-Speed CMOS and BiCMOS Module Products
Part Number
Deserietlon
Avail.
Data
Book
Paa e
IDT7MP6085
128KB Secondary Cache Module for the 486 CPU
50MHz
NOW
E 7.35
IDT7MP6086
128KB Secondary Cache Module for the 486 CPU
50MHz
NOW
E 7.38
IDT7MP6087
256KB Secondary Cache Module forthe 486 CPU
50MHz
NOW
E 7.35
17
NOW
E 7.40
25
2H'92
E 7.40
15
2H'92
E 7.34
17
2H'92
E 7.34
25
2H'92
E 7.34
Max. Speed (ns)
Mil.
Com'l.
R4000 MICROPROCESSOR SECONDARY CACHE MODULES
IDT7MP6048
Flexi-Cache™ Development Tool for the
IDT79R4000 CPU (1 MB version)
IDT7MP6068
Flexi-Cache™ Development Tool for the
IDT79R4000 CPU (4MB version)
IDT7MP6074
256KB Secondary Cache Module Block
for the IDT79R4000 CPU
IDT7MP6084
1MB Secondary Cache Module Block
for the IDT79R4000 CPU
4MB Secondary Cache Module Block
for the IDT79R4000 CPU
DUAL-PORT MODULES
IDT7MP6094
IDT7M1014
4K x 36 Dual-Port Module
20
15
40'92
E 7.4
IDT7M1024
4K x 36 Synchronous Dual-Port Module
25
20
40'92
E 7.5
IDT7M1012
2K x 36 Dual-Port Module
35
30
NOW
E 7.6
IDT7M1002
16K x 32 Dual-Port Module
40
35
NOW
E 7.3 .
IDT7MB6036
128K x 16 Dual-Port (Shared Memory) Module
40
NOW
E 7.7
IDT7MB1006
64K x 16 Dual-Port Module
35
NOW
E 7.8
IDT7MB6046
64K x 16 Dual-Port (Shared Memory) Module
40
NOW
E 7.7
IDT7MB1008
32K x 16 Dual-Port Module
35
. NOW
E 7.8
IDT7MB6056
32K x 16 Dual-Port (Shared Memory) Module
40
NOW
E 7.8
IDT7M1005
16K x 9 Dual-Port Module
45
35
NOW
E 7.9
IDT7M1004
8K x 9 Dual-Port Module
45
35
NOW
E 7.9
IDT7M1001
128K x 8 Dual-Port Module
50
40
NOW
E 7.10
40
10'93
E 7.11
50
40
NOW
E 7.10
IDT7MP1021
128K x 8 Dual-Port Module
IDT7M1003
64K x 8 Dual-Port Module'
IDT7MP1023
64K x 8 Dual-Port Module
40
NOW
E 7.11
IDT7M137
32K x 8 Dual-Port Module
55
40
NOW
B 8.3
4K x 16 FourPort Multichip Module
30
25
1H'93
E 7.2
FourPort MODULES
IDT70M74
FIFO MODULES
IDT7M208
64K x 9 FIFO Module
35
25
NOW
E 7.13
·IDT7M207
32K x 9 FIFO Module
35
25
NOW
E 7.13
IDT7MP2009
32K x 18 FIFO Module
25
NOW
E 7.12
IDT7MP2010
16K x 18 FIFO Module
30
NOW
E 7.12
Flex/-Palen<
MODULES
IDT7M7004
1M EEPROM Module
IDT7M7005
512K SRAM/512K EEPROM Module
95
25/95
75
NOW
E 7.42
20/75
NOW
E 7.43
LOGIC MODULES
IDT7MP9244
32-bit Buffer/Driver Module
C
NOW
E 7.44
IDT7MP9245
32-bit Bidirectional Transceiver Module
C
NOW
E 7.44
a = additional or new information exists sin~e the publication of Data Book Update 1
1.8
2
(;)®
FIFO
CROSS REFERENCE GUIDE
Integrated Device Technology, Inc.
AMO
Am7200
Am7200-2SPC
Am7200-3SPC
Am7200-S0PC
Am7200-6SPC
Am7200-80PC
Am7200-2S0C
Am7200-3S0C
Am7200-S00C
Am7200-6S0C
Am7200-800C
Am7200-2SRC
Am7200-3SRC
Am7200-S0RC
Am7200-6SRC
Am7200-80RC
Am7200-2SJC
Am7200-3SJC
Am7200-S0JC
Am7200-6SJC
Am7200-80JC
Am7200-40/BXA
Am7200-S0/BXA
Am7200-6S/BXA
Am7200-80/BXA
Am7201
Am7201-2SPC
Am7201-3SPC
Am7201-S0PC
Am7201-6SPC
Am7201-80PC
Am7201-2SRC
Am7201-3SRC
Am7201-S0RC
Am7201-6SRC
Am7201-80RC
Am7201-2SJC
Am7201-3SJC
Am7201-S0JC
Am7201-6SJC
Am7201-80JC
Am7201-2S0C
Am7201-3S0C
Am7201-S00C
Am7201-6S0C
Am7201-800C
Am7201-40/BXA
Am7201-S0/BXA
Am7201-6S/BXA
Am7201-80/BXA
Am7202
Am7202-2SPC
Am7202-3SPC
Am7202-S0PC
Am7202-6SPC
Am7202-80PC
Am7202-2SRC
Am7202-3SRC
lOT
10T7200S/L
2STP
3STP
SOTP
6STP
80TP
2S0
3S0
SOO
6S0
800
2STP
3STP
SOTP
6STP
80TP
2SJ
3SJ
SOJ
6SJ
80J
400B
SOOB
6S0B
800B
IOT7201 SNLA
2SP
3SP
SOP
6SP
80P
2STP
3STP
SOTP
6STP
80TP
2SJ
3SJ
SOJ
6SJ
80J
2S0
3S0
SOO
6S0
800
400B
SOOB
6S0B
800B
IOT7202SNLA
2SP
3SP
SOP
6SP
80P
2STP
3STP
AMO
Am7202
Am7202-S0RC
Am7202-6SRC
Am7202-80RC
Am7202-2SJC
Am7202-3SJC
Am7202.
Am7202-S0JC
Am7202-6SJC
Am7202-80JC
Am7202-2S0C
Am7202-3S0C
Am7202-S00C
Am7202-6S0C
Am7202-800C
Am7202-40/BXA
Am7202-S0/BXA
Am7202-6S/BXA
Am7202-80/BXA
Am7203
Am7203-2SPC
Am7203-3SPC
Am7203-S0PC
Am7203-6SPC
Am7203-80PC
Am7203-2SRC
Am7203-3SRC
Am7203-S0RC
Am7203-6SRC
Am7203-80RC
Am7203-2SJC
Am7203-3SJC
Am7203-S0JC
Am7203-6SJC
Am7203-80JC
Am7203-3S0C
Am7203-S00C
Am7203-6S0C
Am7203-800C
Am7203-40/BXA
Am7203-S0/BXA
Am7203-6S/BXA
Am7203-80/BXA
Am7204
Am7204-2SPC
Am7204-3SPC
Am7204-S0PC
Am7204-6SPC
Am7204-80PC
Am7204-2SJC
Am7204-3SJC
Am7204-S0JC
Am7204-6SJC
Am7204-80JC
Am7204-3S0C
Am7204-S00C
Am7204-6S0C
Am7204-800C
lOT
IOT7202SNLA
SOTP
6STP
80TP
2SJ
3SJ
IOT7202SNLA
SOJ
6SJ
80J
2S0
3S0
SOO
6S0
800
400B
SOOB
6S0B
800B
IOT7203S/L
2SP
3SP
SOP
6SP
80P
2STP
3STP
SOTP
6STP
80TP
2SJ
3SJ
SOJ
6SJ
80J
3S0
SOO
6S0
800
400B
SOOB
6S0B
800B
IOT7204S/L
2SP
3SP
SOP
6SP
80P
2SJ
3SJ
SOJ
6SJ
80J
3S0
SOO
6S0
800
1.9
AMO
Am7204
Am7204-40/BXA
Am7204-S0/BXA
Am7204-6S/BXA
Am7204-80/BXA
67C401
67C401-3SN
67C401-2SN
67C401-1SN
67C401-10N
67C401-3SJ
67C401
67C401-2SJ
67C401-1SJ
67C401-10J
67401
67401A-N
67401-N
67401A-J
67401-J
C67401
C67401A-N
C67401-N
C67401A-J
C67401-J
S7C401
S7C401-12J
S7401
S7401A-J
S7401-J
CS7401
CS7401A-J
CS7401-J
67C402
67C402-3SN
67C402-2SN
67C402-1SN
67C402-10N
67C402-3SJ
67C402-2SJ
67C402-1SJ
67C402-10J
67402
67402A-N
67402-N
67402A-J
67402-J
C67402
C67402A-N
C67402-N
C67402A-J
C67402-J
S7C402
S7C402-12J
S7402
S7402A-J
S7402-J
CS7402
lOT
IOT7204S/L
400B
SOOB
6S0B
800B
IOT72401L
3SP
2SP
1SP
10P
3S0
IOT72401L
2S0
1S0
100
1SP
10P
1S0
100
1SP
10P
1S0
100
1S0B
100B
100B
100B
100B
IOT72402L
3SP
2SP
1SP
10P
3S0
2S0
1S0
100
1SP
10P
1S0
100
1SP
10P
1S0
100
1S0B
100B
100B
FIFO CROSS REFERENCE
AMO
C57402
57402A-J
57402-J
C57402
C57402A-J
C57402-J
67C4013
67C4013-35N
67C4013-25N
67C4013-15N
67C4013-10N
67C4013-35J
67C4013-25J
67C4013-15J
67C4013-10J
57C4013
57C4013-12J
67C4023
67C4023-35N
67C4023-25N
67C4023-15N
67C4023-10N
67C4023-35J
67C4023-25J
67C4023-15J
67C4023-10J
57C4023
57C4023-12J
67C4033
67C4033-15N
67C4033-10N
67C4033-15J
67C4033-10J
67C413
67C413-40N
67C413-40J
67413
67413-25N
67413A-35N
67413-25J
67413A-35J
57C4033
57C4033-12J
lOT
IOT72402L
1008
1008
1008
1008
IOT72403L
35P
25P
15P
10P
350
250
150
100
1508
IOT72404L
35P
25P
15P
10P
350
250
150
100
1508
IOT72413L
25P
25P
250
250
45P
450
25P
35P
250
350
2508
MOSEL
MS7200
MS7200-25NC
MS7200-35NC
MS7200-50NC
MS7200-80NC
MS7200-25JC
MS7200-35JC
MS7200-50JC
MS7200-80JC
MS7200L-25NC
MS7200L-35NC
MS7200L-50NC
MS7200L-80NC
MS7200L-25JC
MS7200L-35JC
MS7200L-50JC
MS7200L-80JC
MS7201
MS7201-50PC
MS7201-65PC
MS7201-80PC
MS7201-120PC
MS7201A
MS7201 A-25JC
MS7201A-35JC
MS7201 A-50JC
MS7201A-80JC
MS7201 A-25NC
MS7201 A-35NC
MS7201A-50NC
MS7201A-80NC
MS7201 A-25PC
MS7201 A-35PC
MS7201 A-50PC
MS7201A-80PC •
MS7201 AL-25JC
MS7201 AL-35JC
MS7201 AL-50JC
MS7201 AL-80JC
MS7201 AL-25NC
MS7201 AL-35NC
MS7201 AL-50NC
MS7201 AL-80NC
MS7201 AL-25PC .
MS7201 AL-35PC
MS7201 AL-50NC
MS7201AL-80PC
MS7202A
MS7202A-25JC
MS7202A-35JC
MS7202A-50JC
MS7202A-80JC
MS7202A-25NC
MS7202A-35NC
MS7202A-50NC
MS7202A-80NC
MS7202A-25PC
MS7202A-35PC
1_9
lOT
IOT7200
25TP
35TP
50TP
80TP
25J
35J
50J
80J
25TP
25TP
25TP
25TP
25J
35J
50J
80J
10T7201
50P
65P
80P
120P
25J
35J
50J
80J
25TP
35TP
50TP
80TP
25P
35P
50P
80P
25J
35J
50J
80J
25TP
35TP
50TP
80TP
25P
35P
50P
80P
10T7202S/L
25J
35J
50J
80J
25TP
35TP
50TP
80TP
25P
35P
MOSEL
MS7202A
MS7202A-50PC
MS7202A-80PC
MS7202AL-25JC
MS7202AL-35JC
MS7202AL-50JC
MS7202AL-80JC
MS7202AL-25NC
MS7202AL-35NC
MS7202AL-50NC
MS7202AL-80NC
MS7202AL -25PC
MS7202AL-35PC
MS7202AL-50PC
MS7202AL-80PC
MS7203
MS7203-35JC
MS7203-50JC
MS7203-80JC
MS7203-35NC
MS7203-50NC
MS7203-80NC
MS7203-35PC
MS7203-50PC
MS7203-80PC
MS7203L-35JC
MS7203L-50JC
MS7203L-80JC
MS7203L-35NC
MS7203L-50NC
MS7203L-80NC
MS7203L-35PC
MS7203L-50PC
MS7203L-80PC
lOT
10T7202S/L
50P
80P
25J
35J
50J
80J
25TP
35TP
50TP
80TP
25P
35P
50P
80P
10T7203
35J
50J
BOJ
35TP
50TP
80TP
35P
50P
80P
35J
50J
80J
35TP
50TP
80TP
35P
50P
80P
2
FIFO CROSS REFERENCE
SGS
MK4501
MK4501N-65
MK4501N-80
MK4501N-10
MK4501N-12
MK4501N-15
MK4501N-20
MK4501K-65
MK4501K-80
MK4501K-10
MK4501K-12
MK4501K-15
MK4501K-20
MK4503
MK4503N-50
MK4503N-65
MK4503N-80
MK4503N-10
MK4503N-12
MK4503N-15
MK4503N-20
MK4503K-50
MK4503K-65
MK4503K-80
MK4503K-10
MK4503K-12
MK4503K-15
MK4503K-20
Dallas
OS2009
OS2009-35
OS2009-50
OS2009-65
OS2009-80
OS2009R-35
OS2009R-50
OS2009R-65
OS2009R-80
OS2010
OS2010-35
OS2010-50
OS2010-65
OS2010-80
OS2010R-35
OS2010R-50
OS2010R-65
OS2010R-80
OS2011
OS2011-35
OS2011-50
OS2011-65
OS2011-80
OS2011 R-35
OS2011 R-50
OS2011 R-65
OS2011 R-80
lOT
10T7201 SNLA
65P
80P
80P
120P
120P
120P
65J
80J
80J
120J
120J
120J
IOT7203S/L
50P
65P
80P
80P
120P
120P
120P
50J
65J
80J
80J
120J
120J
120J
lOT
i0T7201 SNLA
35P
50P
65P
80P
35J
50J
65J
80J
IOT7202SNLA
35P
50P
65P
80P
35J
50J
65J
80J
IOT7203S/L
35P
50P
65P
80P
35J
50J
65J
80J
aSI
QS8201
QS8201-15
QS8201-20P
QS8201-25P
QS8201-35P
QS8201-50P
QS8201-80TP
QS8201-15JR
QS8201-20JR
QS8201-25JR
QS8201-35JR
QS8201-50JR
QS8201-80JR
QS8201-25P6
QS8201-35P6
QS8201-50P6
QS8201-80P6
QS8201-15S3
QS8201-20S3
QS8201-25S3
QS8201-35S3
QS8201-50S3
QS8202
QS8202-15
QS8202-20P
QS8202-25P
QS8202-35P
QS8202-50P
QS8202-80TP
QS8202-15J R
QS8202-20JR
QS8202-25JR
QS8202-35JR
QS8202-50JR
QS8202-80JR
QS8202-25P6
lOT
10T7201 SNLA
15TP
20TP
25TP
35TP
50TP
80TP
15J
20J
25J
35J
50J
80J
25P
35P
50P
80P
15S0
20S0
25S0
35S0
50S0
IOT7202SNLA
15TP
20TP
25TP
35TP
50TP
80TP
15J
20J
25J
35J
50J
80J
25P
TI
lOT
54/74ALS236
SN74ALS236-30N
SN54ALS236-25J
54/74ALS234
SN74ALS234-30N
SN54ALS234-25J
54/74ALS235
SN74ALS235-25N
SN74ALS235-250W
SN54ALS235-20J
IOT72401L
35P
2508
IOT72403L
35P
2508
10T72413L
25P
25S0
2508
1.9
Samsung
KM75C01A
KM75C01 AP-15
KM75C01 AP-20
KM75C01 AP-25
KM75C01 AP-35
KM75C01 AP-50
KM75C01 AP-80
KM75C01 AJ-15
KM75C01 AJ-20
KM75C01 AJ-25
KM75C01 AJ-35
KM75C01 AJ-50
KM75C01 AJ-80
KM75C01 AN-15
KM75C01 AN-20
KM75C01 AN-25
KM75C01 AN-35
KM75C01 AN-50
KM75C01 AN-80
KM75C02A
KM75C02AP-15
KM75C02AP-20
KM75C02AP-25
KM75C02AP-35
KM75C02AP-50
KM75C02AP-80
KM75C02AJ-15
KM75C02AJ-20
KM75C02AJ-25
KM75C02AJ-35
KM75C02AJ-50
KM75C02AJ-80
KM75C02AN-15
KM75C02AN-20
KM75C02AN-25
KM75C02AN-35
KM75C02AN-50
KM75C02AN-80
KM75C03A
KM75C03AP-25
KM75C03AP-35
KM75C03AP-50
KM75C03AP-80
KM75C03AJ-25
KM75C03AJ-35
KM75C03AJ-50
KM75C03AJ-80
KM75C03AN-25
KM75C03AN-35
KM75C03AN-50
KM75C03AN-80
lOT
10T7201 SNLA
15P
20P
25P
35P
50P
80P
15J
20J
25J
35J
50J
80J
15TP
20TP
25TP
35TP
50TP
80TP
IOT7202SNLA
15P
20P
25P
35P
50P
80P
15J
20J
25J
35J
50J
80J
15TP
20TP
25TP
35TP
50TP
80TP
IOT7203SNLA
25P
35P
50P
80P
25J
35J
50J
80J
25TP
35TP
50TP
80TP
3
FIFO CROSS REFERENCE
SHARP
LH5495
LH54950-15
LH54950-25
LH54950-35
LH5495U-15
LH5495U-25
LH5495U-35
LH5496
LH5496-20
LH5496-25
LH5496-35
LH5496-50
LH54960-15
LH54960-20
LH54960-25
LH54960-35
LH54960-50
LH5496U-15
LH5496U-20
LH5496U-25
LH5496U-35
LH5497
LH5497-20
LH5497-25
LH5497-35
LH5497-50
LH54970-20
LH54970-25
LH54970-35
LH54970-50
LH5497U-20
LH5497U-25
LH5497U-35
LH5498
LH5498-20
LH5498-25
LH5498-35
LH5498-50
LH54980-20
LH54980-25
LH54980-35
LH54980-50
LH5498U-20
LH5498U-25
LH5498U-35
LH5499
LH5499-20
LH5499-25
LH5499-35
LH5499-50
LH5499U-20
LH5499U-25
LH5499-U35
lOT
10T7200L
15TP
25TP
35TP
15J
25J
35J
10T7201L
20P
25P
35P
50P
15TP
20TP
25TP
35TP
50TP
15J
20J
25J
35J
10T7202L
20P
25P
35P
50P
20TP
25TP
35TP
50TP
20J
25J
35J
IOT7203
20P
25P
35P
50P
20TP
25TP
35TP
50TP
20J
25J
35J
IOT7204
20P
25P
35P
50P
20J
25J
35J
Cypress
CY7C420
CY7C420-30PC
CY7C420-40PC
CY7C420-65PC
CY7C420-300C
CY7C420-400C
CY7C420-650C
CY7C420-300MB
CY7C420-400MB
CY7C420-650MB
CY7C421
CY7C421 -30PC
CY7C421-40PC
CY7C421-65PC
CY7C421-30JC
CY7C421-40JC
CY7C421-65JC
CY7C421-30VC
CY7C421-40VC
CY7C421-65VC
CY7C421-300C
CY7C421-400C
CY7C421-650C
CY7C421-300MB
CY7C421-400MB
CY7C421-650MB
CY7C421-30LMB
CY7C421-40LMB
CY7C421-65LMB
CY7C424
CY7C424-30PC
CY7C424-40PC
CY7C424-65PC
CY7C424-300C
CY7C424-400C
CY7C424-650C
CY7C424-300MB
CY7C424-400MB
CY7C424-650MB
CY7C425
CY7C425-30PC
CY7C425-40PC
CY7C425-65PC
CY7C425-30JC
CY7C425-40JC
CY7C425-65JC
CY7C425-30VC
CY7C425-40VC
CY7C425-65VC
CY7C425-300C
CY7C425-400C
CY7C425-650C
CY7C425-300MB
CY7C425-400MB
CY7C425-650MB
CY7C425-30LMB
CY7C425-40LMB
CY7C425-65LMB
1_9
lOT
IOT7201 SNLA
25P
35P
65P
250
350
650
300B
400B
650B
25TP
35TP
65TP
25J
35J
65J
25Y
35Y
65Y
25TC
35TC
65TC
30TCB
40TCB
65TCB
30LB
40LB
65LB
IOT7202SNLA
25P
35P
65P
250
350
650
300B
400B
650B
25TP
35TP
65TP
25J
35J
65J
25Y
35Y
65Y
25TC
35TC
65TC
30TCB
40TCB
65TCB
30LB
40LB
65LB
Cypress
CY7C428
CY7C428-20PC
CY7C428-25PC
CY7C428-30PC
CY7C428-40PC
CY7C428-65PC
CY7C428-200C
CY7C428-250C
CY7C428-300C
CY7C428-400C
CY7C428-650C
CY7C428-250MB
CY7C428-300MB
CY7C428-400MB
CY7C428-650MB
CY7C429
CY7C429-20PC
CY7C429-25PC
CY7C429-30PC
CY7C429-40PC
CY7C429-65PC
CY7C429-20JC
CY7C429-25JC
CY7C429-30JC
CY7C429-40JC
CY7C429-65JC
CY7C429-200C
CY7C429-250C
CY7C429-300C
CY7C429-400C
CY7C429-650C
CY7C429-20VC
CY7C429-25VC
CY7C429-30VC
CY7C429-40VC
CY7C429-65VC
CY7C429-250MB
CY7C429-300MB
CY7C429-400MB
CY7C429-650MB
CY7C4321433
CY7C432-25PC
CY7C432-30PC
CY7C432-40PC
CY7C432-65PC
CY7C432-250C
CY7C432-300C
CY7C432-400C
CY7C432-650C
CY7C432-250MB
CY7C432-300MB
CY7C432-400MB
CY7C432-650MB
CY7C433
CY7C433-25PC
CY7C433-30PC
CY7C433-40PC
CY7C433-65PC
lOT
IOT7203S/L
20P
25P
25P
35P
65P
200
250
250
350
650
200B
300B
400B
650B
20TP
25TP
25TP
35TP
65TP
20J
25J
25J
35J
65J
20TC
25TC
25TC
35TC
65TC
20Y
25Y
30Y
40Y
65Y
20TCB
30TCB
40TCB
65TCB
IOT7204S
25P
25P
35P
65P
250
250
350
650
250B
300B
400B
650B
25TP
25TP
35TP
65TP
4
FIFO CROSS REFERENCE
Cypress
CY7C433
CY7C433-25VC
CY7C433-30VC
CY7C433-40VC
CY7C4321433
CY7C433-65VC
CY7C433-25JC
CY7C433-30JC
CY7C433-40JC
CY7C433-65JC
CY7C433-300MB
CY7C433-400MB
CY7C433-650MB
CY7C433-30LMB
CY7C433-40LMB
CY7C433-65LMB
CY3341
CY3341-2PC
CY3341PC
CY3341-20C
CY3341DC
CY3341-20MB
CY33410MB
CY7C401
CY7C401-25PC
CY7C401-15PC
CY7C401-10PC
CY7C401-5PC
CY7C401-250C
CY7C401-150C
CY7C401-100C
CY7C401-50C
CY7C401-250MB
CY7C401-150MB
CY7C401-100MB
CY7C402
CY7C402-25PC
CY7C402-15PC
CY7C402-10PC
CY7C402-5PC
CY7C402-250C
CY7C402-150C
CY7C402-100C
CY7C402-50C
CY7C402-250MB
CY7C402-150MB
CY7C402-100MB
CY7C403
CY7C403-25PC
CY7C403-15PC
CY7C403-10PC
CY7C403-250C
CY7C403-150C
CY7C403-100C
CY7C403-250MB
CY7C403-150MB
CY7C403-100MB
lOT
10T7204S
25Y
35Y
40Y
IOT7204S
65Y
25J
25J
35J
65J
30TCB
40TCB
65TCB
30LB
40LB
65LB
IOT72401 L
10P
10P
100
100
100B
100B
Cypress
CY7C404
CY7C404-25PC
CY7C404-15PC
CY7C404-10PC
CY7C404-250C
CY7C404-150C
CY7C404-100C
CY7C404-250MB
CY7C404-150MB
CY7C404-100MB
lOT
10T72404L
25P
15P
10P
250
150
100
250B
150B
100B
25P
15P
10P
10P
250
150
100
100
250B
150B
100B
10T72402L
25P
15P
10P
10P
250
150
100
100
250B
150B
100B
10T72403L
25P
15P
10P
250
150
100
250B
150B
100B
1.9
5
t;)®
SMP
CROSS REFERENCE GUIDE
Integrated Device Technology, Inc.
CYPRESS
CY7C130-35PC
45PC
55PC
350C
450C
550C
35LC
45LC
55LC
450MB
550MB
45LMB
55LMB
CY7C131-25JC
35JC
45JC
55JC
35LC
45LC
55LC
45LMB
55LMB
CY7C132-35PC
45PC
55PC
350C
450C
550C
35LC
45LC
55LC
450MB
550MB
45LMB
55LMB
CY7C136-25JC
35JC
45JC
55JC
35LC
45LC
55LC
45LMB
55LMB
CYPRESS
lOT
10T7130SA35P
45P
55P
35C
45C
55C
35L48
45L48
55L48
45CB
55CB
45L48B
55L48B
IDT7130SA25J
35J
45J
55J
35L52
45L52
55L52
45L52B
55L52B
10T7132SA35P
45P
55P
35C
45C
55C
35L48
45L48
55L48
45CB
55CB
45L48B
55L48B
IOT71321 SA25J
35J
45J
55J
35L52
45L52
55L52
45L52B
55L52B
AMO
lOT
AM2130-55PC
70PC
10PC
550C
700C
100C
70/BXC
10/BXC
121BXC
IOT7130SA55P
70P
100P
55C
70C
100C
70CB
100CB
120CB
CY7C140-35PC
45PC
55PC
350C
450C
550C
35LC
45LC
55LC
450MB
550MB
45LMB
55LMB
CY lC141-25JC
35jC
45JC
55JC
35LC
45LC
55LC
45LMB
55LMB
CY7C142-35PC
45PC
55PC
350C
450C
550C
35LC
45LC
55LC
450MB
550MB
45LMB
55LMB
CY7C146-25JC
35JC
45JC
55JC
35LC
45LC
55LC
45LMB
55LMB
1.10
lOT
IOT7140SA35P
45P
55P
35C
45C
55C
35L48
45L48
55L48
45CB
55CB
45L48B
55L48B
IOT7140SA25J
35J
45J
55J
35L52
45L52
!35L52
45L52B
55L52B
IOT7142SA35P
45P
55P
35C
45C
55C
35L48
45L48
55L48
45CB
55CB
45L48B
55L48B
I0T71421 SA25J
35J
45J
55J
35L52
45L52
55L52
45L52B
55L52B
t;J~
SSD
CROSS REFERENCE GUIDE
Integrated Device Technology, Inc.
CYPRESS/MUL TICHIP
PIN
CYM1240HD-35MB
CYM1240HD-45MB
CYM1420HD-25C
CYM1420HD-30C
CYM1420PD-30C
CYM1420HD-35C
CYM1420PD-35C
CYM1420HD-45C
CYM1420PD-45C
CYM1420HD-55C
CYM1420HD-70C
CYM1420HD-35MB
CYM1420HD-45MB
CYM1420HD-55MB
CYM1421 HD-70MB
CYM1421 HD-85MB
CYM1421HD-100MB
CYM1422PS-30C
CYM1422PS-35C
CYM1422PS-45C
CYM1422PS-55C
CYM1441PZ-25C
CYM1441 PZ-35C
CYM1441 PZ-45C
CYM1460PS-35C
CYM1460PS-45C
CYM1460PS-55C
CYM1460PS-70C
CYM1461PS-70C
CYM1461PS-85C
CYM1461PS-100C
CYM1464PD-25C
CYM1464PD-30C
CYM1464PD-35C
CYM1464PD-45C
CYM1464PD-55C
CYM1464PD-70C
CYM1465PD-85C
CYM1465PD-100C
CYM1465PD-120C
CYM1465PD-150C
CYM1466HD-35C
CYM1466LHD-35C
CYM1466HD-35MB
CYM1466LHD-35MB
CYM1466HD-45C
CYM1466LH D-45C
CYM1466HD-45MB
CYM1466LHD-45MB
CYM1466HD-55C
CYM1466LHD-55C
CYM1466HD-55MB
CYM1466LHD-55MB
lOT PIN
DIRECT
EQUIVALENT
7M4042S35CB
7M4042S45CB
8M824S25C
8M824S30C
8M824S30N
8M824S35C
8M824S35N
8M824S45C
8M824S45N
8M824S50C
8M824S50N
8M824S70C
8M824S70N
8M824S40CB
8M824S45CB
8M824S55CB
8M824S70CB
8M824S85CB
8M824S100CS
8MP824S30S
8MP824S35S
8MP824S40S
8MP824S50S
lOT PIN
SIMILAR
PART
8MB824S25P
8MB824S30P
8MB824S30P
8MB824S35P
8MB824S35P
8MB824S45P
8MB824S45P
1 MEG
28 PIN
1 MEG
32 PIN
(256K X 4) JEDEC
DIP
(128K X 8) JEDEC
DIP
1 MEG (128K X 8) JEDEC
32 PIN DIP
I [Low power version]
1 MEG (128K X 8)
30 PIN SIP
7MP4034S25Z
7MP4034S35Z
7MP4034S45Z
7MP4008S35S
7MP4008S45S
7MP4008S55S
7MP4008S70S
7MP4058L70S
7MP4058L85S
7MP4058L 1OOS
7MB4048S25P
7MB4048S30P
7MB4048S35P
7MB4048S45P
7MB4048S55P
7M4048L70N
7M4048L85N
7M4048L 1OON
7M4048L 120N
7M4048L 120N
7M4048S35C
7M4048L35C
7M4048S35CB
7M4048L35CB
7M4048S45C
7M4048L45C
7M4048S45CB
7M4048L45CB
7M4048S55C
7M4048L55C
7M4048S55CB
7M4048L55CB
CYPRESS/MUL TICHIP
ORG/PACKAGE
2 MEG (256K X 8) JEDEC
60 PIN ZIP
4 MEG (512KX 8)
36 PIN SIP
7MP4008S70S
7MP4008L85S
7MP4008L 1OOS
4 MEG (512KX8)
36 PIN SIP
4 MEG (512KX 8) JEDEC
32 PIN DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
1.11
SSD CROSS REFERENCE
CYM1466HD-70C
CYM1466LHD-70C
CYM1466HD-70MB
CYM 1466LHD-70MB
CYM 1466H D-85C
CYM 1466LHD-85C
CYM1466HD-85MB
CYM1466LHD-85MB
CYM1466HD-100C
CYM 1466LHD-1 OOC
CYM1466HD-100MB
CYM 1466LHD-1 OOMB
CYM1466HD-120C
CYM1466LHD-120C
CYM1466HD-120MB
CYM1466LHD-120MB
CYM1540PS-30C
CYM 1540PS-35C
CYM1540PS-45C
CYM1541PD-25C
CYM 1541 PD-35C
CYM 1541 PD-45C
CYM1610HD-20C
CYM 161 OHD-25C
CYM1610HD-35C
CYM1610HD-45C
CYM1610HD-50C
CYM1610HD-25MB
CYM1610HD-35MB
CYM1610HD-45MB
CYM1610HD-50MB
CYM1611HV-20C
CYM1611HV-25C
CYM1611HV-30C
CYM1611HV-35C
CYM1611HV-45C
CYM1611 PV-20C
CYM1611PV-25C
CYM1611PV-30C
CYM1611PV-35C
CYM1611 PV-45C
CYM1620HD-30C
CYM1620HD-35C
CYM1620HD-45C
CYM1620HD-50C
CYM1620HD-45MB
CYM1620HD-50MB
CYM1621 HO-25C
CYM 1621 HD-30C
CYM1621 HD-35C
CYM1621HO-45C
CYM1621 HD-25MB
CYM1621 HD-30MB
CYM1621 HD-35MB
CYM1621 HO-45MB
CYM1622HV-20C
CYM1622HV-25C
CYM1622HV-35C
CYM1622HV-45C
7M4048S70C
7M4048L70C
7M4048S70CB
7M4048L70CB
7M4048S85C
7M4048L85C
7M4048S85CB
7M4048L85CB
7M4048S100C
7M4048L 1OOC
7M4048S100CB
7M4048L 1OOCB
7M4048S120C
7M4048L 120C
7M4048S120CB
7M4048L 120CB
4 MEG (512K X 8) JEDEC
32 PIN DIP
7MB4040S25P
7MB4040S35P
7MB4040S45P
7MB4040S25P
7MB4040S35P
7MB4040S45P
2 MEG (256K X 9)
44 PIN SIP
2 MEG (256K X 9)
44 PIN DIP
7MC4005S20CV
7MC4005S25CV
7MC4005S35CV
256K (16K X 16)
40 PIN DIP
8M656S40C
8M656S50C
7MC4005S25CVB
7MC4005S35CVB
8M656S40CB
8M656S50CB
7MC4005S20CV
7MC4005S25CV
7MC4005S30CV
7MC4005S35CV
7MC4005S45CV
7MC4005S20CV
7MC4005S25CV
7MC4005S30CV
7MC4005S35CV
7MC4005S45CV
8M624S30C
8M624S35C
8M624S45C
8M624S50C
8M624S45CB
8M624S50CB
7M624S25C
7M624S30C
7M624S35C
7M624S45C
7M624S25CB
7M624S30CB
7M624S35CB
7M624S45CB
7MP4027S20V
7MP4027S25V
7MP4027S35V
7MP4027S45V
256K (16K X 16)
36 PIN DSIP
1 MEG (64K X ,1,6) JEDEC
40 PIN DIP
1 MEG (64K X 16),
(128K X 8), (256K X 4) "
40 PIN DIP
1 MEG (64K X 16)
40 PIN DSIP
1.11
2
SSD CROSS REFERENCE
CYM1623HD-70MB
CYM1623HD-85MB
CYM1623HD-100MB
CYM1624PV-20C
CYM1624PV-25C
CYM1624PV-35C
CYM1624PV-45C
CYM1626PS-30C
CYM1626PS-35C
CYM1626PS-45C
CYM1641HD-25C
CYM1641HD-35C
CYM1641HD-45C
CYM1641HD-55C
CYM1641HD-35MB
CYM1641 HD-45MB
CYM1641 HD-55MB
CYM1821PZ-12C
CYM1821PZ-15C
CYM1821 PZ-20C
CYM1821 PZ-25C
CYM1821 PZ-35C
CYM1821 PZ-45C
CYM1822HV -20C
CYM1822HV-25C
CYM1822HV-30C
CYM1822HV-35C
CYM1822HV-45C
CYM1828HG-20C
CYM1828HG-25C
CYM1828HG-25MB
CYM1828HG-30C
CYM1828HG-30MB
CYM1828HG-35C
CYM1828HG-35MB
CYM1828HG-45C
CYM1828HG-45MB
CYM1828HG-55C
CYM1828HG-55MB
CYM1828HG-70C
CYM1828HG-70MB
CYM1830HD-25C
CYM1830HD-30C
CYM1830HD-35C
CYM1830HD-45C
CYM1830HD-55C
CYM1830HD-35MB
CYM1830HD-45MB
CYM1830HD-55MB
CYM1831PZ-15C
CYM1831 PZ-20C
CYM1831 PZ-25C
CYM1831 PZ-30C
CYM1831PZ-35C
CYM1831 PZ-45C
CYM1831PM-15C
CYM1831PM-20C
CYM1831PM-25C
CYM1831 PM-30C
CYM1831 PM-35C
CYM1831 PM-45C
8M624S70CB
8M624S85CB
8M624S100CB
7MP4028S20V
7MP4028S25V
7MP4028S35V
7MP4028S45V
8MP624S30S
8MP624S35S
8MP624S45S
7M4016S25C
7M4016S35C
7M4016S45C
7M4016S55C
7M4016S35CB
7M4016S45CB
7M4016S55CB
7MP4031 B12Z
7MP4031 S15Z
7MP4031 S20Z
7MP4031 S25Z
7MP4031 S35Z
7MP4031 S35Z
7MC4032S20CV
7MC4032S25CV
7MC4032S30CV
7MC4032S35CV
7MC4032S45CV
7M4003S20CH
7M4003S25CH
7M4003S25CHB
7M4003S30CH
7M4003S30CHB
7M4003S35CH
7M4003S35CHB
7M4003S45CH
7M4003S45CHB
7M4003S50CH
7M4003S50CHB
7M4003S50CH
7M4003S70CHB
7M4017S25C
7M4017S30C
7M4017S35C
7M4017S45C
7M4017S50C
7M4017S35CB
7M4017S45CB
7M4017S50CB
7MP4036B15Z
7MP4036S20Z
7MP4036S25Z
7MP4036S30Z
7MP4036S35Z
7MP4036S35Z
7MP4036B15M
7MP4036S20M
7MP4036S25M
7MP4036S30M
7MP4036S35M
7MP4036S35M
1 MEG (64K X 16) JEDEC
40 PIN DIP
I [low power version1
1 MEG (64KX 16)
40 PIN DSIP
1 MEG (64KX 16)
40 PIN SIP
4 MEG (256K X 16)
48 PIN DIP
512K (16K X 32) JEDEC
64 FR-4 ZIP
512K (16K X 32)
88 PIN DSIP
1 MEG (32K X 32)
66 PIN HIP
2 MEG (64K X 32)
60 PIN DIP
2 MEG (64K X 32) JEDEC
64 PIN ZIP
2 MEG (64K X 32) JEDEC
64 PIN SIMM
1.11
3
SSD CROSS REFERENCE
CYM1832PZ-2SC
CYM1832PZ-3SC
CYM1832PZ-4SC
CYM1832PZ-SSC
CYM1838HG-20C
CYM1838HG-2SC
CYM1838HG-2SMB
CYM1838HG-30C
CYM1838HG-30MB
CYM1838HG-3SC
CYM1838HG-3SMB
CYM1838HG-45C
CYM1838HG-4SMB
CYM1838HG-SSC
CYM1838HG-SSMB
CYM1838HG-70C
CYM1838HG-70MB
CYM1840PD-20C
CYM1840PD-2SC
CYM1840HD-2SC
CYM1840PD-30C
CYM1840HD-30C
CYM1840PD-3SC
CYM1840HD-3SC
CYM1840PD-4SC
CYM1840HD-4SC
CYM1840PD-SSC
CYM1840HD-SSC
CYM1841 PZ-20C
CYM1841 PZ-2SC
CYM1841 PZ-30C
CYM1841 PZ-3SC
CYM1841PZ-45C
CYM1841 PZ-SSC
CYM1841 PM-20C
CYM1841 PM-2SC
CYM1841 PM-30C
CYM1841 PM-3SC
CYM1841 PM-45C
CYM1841 PM-SSC
CYM4210HD-30C
CYM4210HD-40C
CYM4210HD-SOC
CYM4210HD-60C
CYM4210HD-8SC
CYM4210HD-40MB
CYM4210HD-SOMB
CYM4210HD-60MB
CYM4210HD-8SMB
CYM4220HD-30C
CYM4220HD-40C
CYM4220HD-SOC
CYM4220HD-60C
CYM4220HD-8SC
CYM4220HD-40MB
CYM4220HD-SOMB
CYM4220HD-60MB
CYM4220HD-8SMB
7MP4036S2SZ
7MP4036S3SZ
7MP4036S3SZ
7MP4036S3SZ
7M4013S20CH
7M4013S2SCH
7M4013S2SCHB
7M4013S30CH
7M4013S30CHB
7M4013S3SCH
7M4013S3SCHB
7M4013S4SCH
7M4013S4SCHB
7M4013SS0CH
7M4013SS0CHB
7M4013SS0CH
7M4013S70CHB
7MB4067S20P
7MB4067S2SP
2 MEG (64K X 32)
60 PIN ZIP
4 MEG (128K X 32)
66 PIN HIP
8 MEG (2S6K X 32)
60 PIN DIP
7MB4067S2SP
7MB4067S30P
7MB4067S30P
7MB4067S3SP
7MB4067S3SP
7MB4067S4SP
7MB4067S4SP
7MB4067S4SP
7MB4067S4SP
7MP404SS20Z
7MP404SS2SZ
7MP404SS30Z
7MP404SS3SZ
7MP404SS45Z
7MP404SSSSZ
7MP404SS20M
7MP4045S2SM
7MP404SS30M
7MP404SS3SM
7MP4045S4SM
7MP4045SSSM
720SSL2SP
720SSL2SP
720SSLSOP
720SSLSOP
720SSL80P
720SSL30DB
720SSLSODB
720SSLSODB
720SSL80DB
7206SL2SP
7206SL2SP
7206SLSOP
7206SLSOP
7206SL80P
7M206S40CB
7M206SS0CB
7M206S60CB
7M206S8SCB
8 MEG (2S6K X 32) JEDEC
64 PIN ZIP
8 MEG (2S6K X 32) JEDEC
64 PIN SIMM
8K X 9 FIFO
28 PIN DIP
16K X 9 FIFO
28 PIN DIP
1.11
4
SSD CROSS REFERENCE
DENSE-PAC PIN
DPS128M8N-70
DPS128M8N-85
DPS128M8N-100
DPS128M8N-120
DPS128M8N-150
DPS16X5-XXX
DPS16X17-25
DPS16X17-35
DPS16X17-45
DPS16X17-55
DPS257-XXX
DPS1024-25C
DPS1024-35C
DPS1024-45C
DPS1024-55C
DPS1026-25C
DPS1026-35C
DPS1026-45C
DPS1026-55C
DPS1 027 -25C
DPS1 027 -35C
DPS1027-45C
DPS1027-55C
DPS128X32V3-70
DPS128X32V3-85
DPS128X32V3-100
DPS128X32V3-120
DPS128X32V3-150
DPS2516-25C
DPS2516-35C
DPS2516-45C
DPS2516-55C
DPS4648-85C
DPS4648-100C
DPS4648-120C
DPS4648-150C
DPS5124-45C
DPS5124-55C
DPS6432-35C
DPS6432-45C
DPS6432-55C
DPS6432-70C
DPS6433-85C
DPS6433-100C
DPS6433-120C
DPS6433-150C
DPS6433-55C
DPS6433-70C
DPS6433-100C
DPS8645-XXX
IDTP/N
DIRECT
EQUIVALENT
71 M024-70
71 M024-85
71 M024-100
71 M024-120
71 M024-120
7MP564
7MP564
7MC4005S25CV
7MC4005S35CV
7MC4005S45CV
7MC4005S55CV
7M656
7M656
7M656
7M656
lOT PIN
SIMILAR
PART
DENSE-PAC
ORG/PACKAGE
1 M (128K X 8) Monolithic
32 PIN DIP
80K (16K X 5)
28 PIN SIP
256K (16K X 16)
36 PIN DSIP
256K (16K X 16)
(32K X8)
(64K X4)
40 PIN DIP
1 MEG (256K X 4),
(128K X 8), (64K X 16)
42 PIN DIP
7M624
7M624
7M624
7M624
7M624
7M624
7M624
7M624
1 MEG (256K X 4),
(128K X 8), (64K X 16)
40 PIN DIP
1 MEG (256K X 4);
(128K X 8), (64K X 16)
40 PIN DIP
7M624S25C
7M624S35C
7M624S45C
7M624S55C
7M4013S70CHB
7M4013S85CHB
7M4013S100CHB
7M4013S100CHB
7M4013S100CHB
4 MEG (128K X 32)
66 PIN HIP
4 MEG (256K X 16)
44 PIN DIP
7M4016
7M4016
7M4016
7M4016
7M812
7M812
7M812
7M812
7MP4034
7MP4034
512K (64K X 8)
32 PIN DIP
2 MEG (512K X 4),
(256K X8)
54 PIN DIP
2 MEG (64K X 32)
60 PIN DIP
7M4017S35C
7M4017S45C
7M4017S55C
7M4017S70C
7MP4034,
7MP4034,
7MP4034,
7MP4034,
7M4017
7M4017
7M4017
7M4017
7M4017S55C
7M4017S70C
7M4017S70C
7MP456
7MP456
1.11
2 MEG (64K X 32)
(128K X 16), (256K X 8)
60 PIN DIP
[low power version]
2 MEG (64K X 32)
60 PIN DIP
I [low power versionl
256K (64K X 4)
28 PIN SIP
5
SSDCROSSREFERENCE
DPS8808-XXX
DPS8M612-85C
DPS8M612-100C
DPS8M612-120C
DPS8M612-150C
DPS8M624-85C
DPS8M624-100C
DPS8M624-120C
DPS8M624-150C
DPS8M656-35C
DPS8M656-40C
DPS8M656-70C
DPS10241-25C
DPS10241-35C
DPS10241-45C
DPS10241-55C
DPS40256-XXX
DPS41257-XXX
DPS41288-70C
DPS41288-85C
DPS41288-100C
DPS45128-85C
DPS45128-100C
DPS45128-120C
DPS45128-150C
DPS45129-85C
DPS45129-100C
DPS45129-120C
DPS45129-150C
DPS512S8-85C
DPS512S8-100C
DPS512S8-120C
DPS512S8-150C
DPS3232V
7M864
7M864
8M612S85C
8M612S100C
8M612S100C
8M612S100C
8M624S85C
8M624S100C
8M624S100C
8M624S100C
1 MEG (64K X 16)
40 PIN DIP
8M656S40C
256K (16K X 16)
40 PIN DIP
7MC4001 S35C
1 MEG (1024K X 1)
30 PIN SIP
8M656S40C
8M656S70C
7MC4001 S35CS
7MC4001 S45CS
7MC4001 S55CS
8M856
8M856
8M856
8M856
8M824S70C
8M824L70N
8M824L85N
8M824L100N
7MP4008
7MP4008
7MP4008
7MP4008
7M4016S55C
7M4016S55C
7M4016S55C
7M4016S55C
7M4048L85N
7M4048L 1OON
7M4048L 120N
7M4048L 120N
7M4003SXXCH
DPE3232V
7M7004SXXCH
EDI PIN
lOT PIN
DIRECT
EQUIVALENT
71 M025-70
71 M025-85
71 M025-1 00
71 M024-70
71 M024-85
71 M024-1 00
8M824S35C
8M824S45C
8M824S50C
8M824S45CB
8M824S50CB
8M824S70CB
8M824S60N
8M824L70N
8M824L100N
8M824L100N
8M824L100N
ED188128-70
ED188128-85
ED188128-100
ED188130-70
ED188130-85
ED188130-100
EDI8M8128C35C6C
EDI8M8128C45C6C
EDI8M8128C55C6C
EDI8M8128C45C6B
EDI8M8128C55C6B
E DI8M8128C70C6B
EDI8M8128C60P6C
EDI8M8128C70P6C
EDI8M8128C100P6C
EDI8M8128C120P6C
EDI8M8128C150P6C
64K (8K X8)
28 PIN DIP
512K (32K X 16)
40 PIN DIP
256K (32K X 8)
28 PIN DIP
256K (32K X 8)
28 PIN DIP
1 MEG (128K X 8)
32 PIN DIP
4 MEG (512K X 8)
48 PIN DIP
4 MEG (256K X 16)
48 PIN DIP
4 MEG (512K X 8)
32 PIN DIP
lOT PIN
SIMILAR
PART
1 MEG (32K X 32)
66 PIN HIP
1 MEG (32K X 32) EEPROM
66 PIN HIP
EDI
ORG/PACKAGE
1 M (128K X 8) Monolithic
32 PIN DIP (1 CS)
1 M (128K X 8) Monolithic
32 PIN DIP (2 CS)
8M824S35N, 8MP824S35S
8M824S45N, 8MP824S45S
8M824S50N, 8MP824S50S
1 MEG (128K X 8) JEDEC
32 PIN DIP
8M824S60C, 8MP824S60S
8M824S70C, 8MP824L70S
8MP824L 1OOS
8MP824L 1OOS
8MP824L 1OOS
1 MEG (128K X 8) JEDEC
32 PIN DIP
1.11
6
SSD CROSS REFERENCE
EDIBMB12BCB5C6B
EDIBMB12BC1006CB
EDIBMB12BC1206CB
EDIBMB12BC1506CB
EDIBMB256C70P6C
EDIBMB256CB5P6C
EDIBMB256C100P6C
EDIBM8256C120P6C
EDIBMB256C150P6C
EDIBFB257C85B6C
EDIBFB257C100B6C
EDIBF8257C120B6C
EDIBFB257C150B6C
EDIBM8257C85P6C
EDIBMB257C100P6C
EDIBM8257C120P6C
EDIBMB257C150P6C
EDIBFB257C45MSC
EDIBFB257C55MSC
EDIBF8257C70MSC
EDIBFB258C45MSC
EDI8F825BC55MSC
EDIBFB25BC70MSC
EDIBMB512CB5P6C
EDIBMB512C100P6C
EDIBM8512C120P6C
EDIBM8512C150P6C
EDIBM8512CB5C6B
EDIBMB512C100C6B
EDIBM8512C120C6B
EDIBMB512C150C6B
EDIBFB512C25M6C
EDIBFB512C30M6C
EDI8F8512C35M6C
EDIBFB512C45M6C
EDIBF8512C55M6C
EDIBFB512C70M6C
EDIBM8512C30M6B
EDIBM8512C35M6B
EDIBM8512C45M6B
EDIBM8512C55M6B
. EDIBM8512C70M6B
EDIBF1664C100PC
EDIBF1664C120PC
EDIBF1664C150PC
EDHB16H16C-25CC-Z
EDH816H16C-35CC-Z
EDHB16H16C-45CC-Z
EDH816H16C-25CMHR-Z
EDHB16H16C-35CMHR-Z
EDH816H16C-45CMHR-Z
EDI8M1664C45C6C
EDIBM1664C55C6C
EDIBM1664C60C6C
EDIBM 1664C70C6C
EDIBM 1664C85C6C
, EDIBM1664C100C6C
EDIBM1664C55C6B
EDIBM1664C60C6B
EDI8M 1664C70C6B
EDIBM1664C85C68
EDI8M 1664C1 00C6B
BMB24SB5CB
BMB24S100CB
BMB24S100CB
BMB24S100CB
7M406BL70N
7M4068LB5N
7M406BL 1OON
7M4068L 120N
7M406BL 120N
7M4068LB5N
7M4068L 1 OON
7M4068L 120N
7M4068L 120N
7M406BLB5N
7M4068L 1OON
7M4068L 120N
7M4068L 120N
1 MEG (12BK X B) JEDEC
32 PIN DIP
[low power version]
2 MEG (256K X 8) JEDEC
32 PIN DIP
2 MEG (256K X 8) JEDEC
32 PIN DIP
2 MEG (256K X 8) JEDEC
32 PIN DIP
7MP4034S45Z
7MP4034S45Z
7MP4034S45Z
7MP4034S45Z
7MP4034S45Z
7MP4034S45Z
7M404BLB5N
7M4048L 1 OON
7M4048L 120N
7M4048L 120N
7M4048SB5CB
7M4048S100CB
7M4048S120CB
7M4048S120CB
7MB4048S25P
7MB4048S30P
7MB4048S35P
7MB4048S45P
7MB4048S55P
7M4048L70N
7M4048S30CB
7M404BS35CB
7M4048S45CB
7M4048S55CB
7M4048S70CB
8M624S70C
BM624S70C
8M624S70C
7MC4005S25CV
7MC4005S35CV
7MC4005S45CV
7MC4005S25CVB
7MC4005S35CVB
7MC4005S45CVB
8M624S40C
8M624S50C
8M624S60C
BM624S70C
BM624SB50C
8M624S100C
BM624S50CB
8M624S60CB
8M624S70CB
8M624SB5CB
8M624S100CB
2 MEG (256K X 8)
36 PIN SIP
2 MEG (256K X 8)
36 PIN SIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
8MP624L 1 OOS
8MP624L1 OOS
8MP624L 1 OOS
1 MEG (64K X 16)
40 PIN DIP
256K (16K X 16)
36 PIN DSIP
1 MEG (64K X 16) JEDEC
40 PIN DIP
1.11
7
SSDCROSSREFERENCE
EDI8M1664C25C9C
EDI8M1664C35C9C
EDI8M 1664C45C9C
EDI8M1664C55C9C
EDI8M1664C70C9C
EDI8M1664C25C9B
EDI8M1664C35C9B
EDI8M1664C45C9B
EDI8M 1664C55C9B
EDI8M1664C70C9B
EDI8M16256C25C9C
EDI8M16256C35C9C
EDI8M16256C45C9C
EDI8M16256C55C9C
EDI8M16256C70C9C
EDI8M 16256C35C9B
EDI8M16256C45C9B
EDI8M 16256C55C9B
EDI8M 16256C70C9B
EDI8M16257C35M6C
ED18M16257C45M6C
EDI8M16257C55M6C
EDI8M16257C70M6C
EDIBF3264C25M6C
EDIBF3264C35M6C
EDI8F3264C45M6C
EDIBF3264C55M6C
EDIBM3264C25C6B
EDI8M3264C35C6B
. EDIBM3264C45C6B
EDIBM3264C55C6B
EDIBF3264C15MZC
EDIBF3264C20MZC
EDIBF3264C25MZC
EDIBF3264C35MZC
EDIBF3264C45MZC
EDIBF3264C55MZC
EDIBF3212BC15BZC
EDIBF32128C20BZC
EDIBF32128C25BZC
EDIBF32128C35BZC
EDIBF32128C45BZC
EDIBF32128C15BMC
EDI8F32128C20BMC
EDI8F32128C25BMC
EDI8F32128C35BMC
EDI8F32128C45BMC
ED18F'32256C20B6C
EDI8F32256C25B6C
EDI8F32256C30B6C
EDI8F32256C35B6C
EDI8F32256C45B6C
EDI8F32256C55B6C
EDI8F32256C70B6C
EDIBF32256C20BZC
EDIBF32256C25BZC
EDI8F32256C35BZC
EDI8F32256C45BZC
EDIBF32256C55BZC
7M624S25C
7M624S35C
7M624S45C
7M624S55C
7M624S70C
7M624S25CB
7M624S35CB
7M624S45CB
7M624S55CB
7M624S70CB
7M4016S25C
7M4016S35C
7M4016S45C
7M4016S55C
7M4016S55C
7M4016S35CB
7M4016S45CB
7M4016S55CB
7M4016S55CB
1 MEG (64K X 16)
40 PIN DIP
4 MEG (256K X 16)
48 PIN DIP
7MB4066S35P
7MB4066S45P
7MB4066S55P
7MB4066S55P
7M4017S25C
7M4017S35C
7M4017S45C
7M4017S50C
7M4017S30CB
7M4017S35CB
7M4017S45CB
7M4017S50CB
7MP4036B15Z
7MP4036S20Z
7MP4036S25Z
7MP4036S30Z
7MP4036S35Z
7MP4036S35Z
7MP4095B15Z
7MP4095S20Z
7MP4095S25Z
7MP4095S35Z
7MP4095S45Z
7MP4095B15M
7MP4095S20M
7MP4095S25M
7MP4095S35M
7MP4095S45M
7MB4067S20P
7MB4067S25P
7MB4067S30P
7MB4067S35P
7MB4067S45P
7MB4067S55P
7MB4067S55P
7MP4045S20Z
7MP4045S25Z
7MP4045S35Z
7MP4045S45Z
7MP4045S55Z
4 MEG (256K X 16)
40 PIN DIP
2 MEG (64K X 32)
60 PIN DIP
2 MEG (64K X 32) JEDEC
64 PIN ZIP
4 MEG (128K X 32) JEDEC
64PIN ZIP
4 MEG (128K X 32) JEDEC
64PIN SIMM
8 MEG (256K X 32)
60 PIN DIP
8 MEG (256K X 32) JEDEC
64PIN ZIP
1.11
8
SSD CROSS REFERENCE
EDIBF32256C20BMC
EDIBF32256C25BMC
EDIBF32256C35BMC
EDIBF32256C45BMC
EDIBF32256C55BMC
EDIBMB130C50CC
EDI8MB130C60CC
EDIBMB130C70CC
EDIBMB130CBOCC
EDIBMB130C90CC
EDIBMB130Cl00CC
EDIBMB130C120CC
EDIBMB130C150CC
EDIBMB130C50CB
EDI8MB130C60CB
EDI8MB130C70CB
EDIBMB130C80CB
EDIBMB130C90CB
EDIBMB130C100CB
EDI8MB130C120CB
EDIBMB130C150CB
EDIBMB130P90CB
EDIBMB130P100CB
EDI8MB130P120CB
EDIBMB130P150CB
EDIBM864C50CC
EDIBMB64C60CC
EDIBMB64C70CC
EDI8M864C80CC
EDI8M864C90CC
EDI8M864C100CC
EDI8MB64C120CC
EDI8M864C150CC
EDIBM864C50CB
EDI8MB64C60CB
EDIBMB64C70CB
EDIBM864CBOCB
EDIBM864C90CB
EDIBM864C100CB
EDIBMB64C120CB
EDIBMB64C150CB
EDH81 H256C-55
EDHB1 H256C-70
EDHB4H64C-35CC-D3
EDHB4H64C-45CC-D3
EDHB4H64C-55CC-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CM HR-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CC-S
EDHB4H64C-45CC-S
EDHB4H64C-55CC-S
7MP4045S20M
7MP4045S25M
7MP4045S35M
7MP4045S45M
7MP4045S55M
7MC156S55CS
7MC156S70CS
B MEG (256K X 32) JEDEC
64PIN SIMM
BM824
8MB24
8MB24
8MB24
BMB24
BMB24
BM824
BM824
BMB24
8MB24
8MB24
8MB24
8MB24
BMB24
BM824
BMB24
8MB24
BMB24
8MB24
8MB24
7M812
7MB12
7MB12
7MB12
7M812
7M812
7M812
7M812
7M812
7MB12
7MB12
7MB12
7MB12
7M812
7M812
7MB12
7MP156
7MP456
1 MEG (128K X 8)
32 PIN DIP
[dual chip enable]
1 MEG (12BK X 8)
32 PIN DIP
[dual chip enable]
[low power version]
512K (64K X 8)
32 PIN DIP
256K (256K X 1)
2B PIN SIP
256K (64K X 4)
24 PIN DIP
256K (64K X 4)
2B PIN SIP
7MP456S35S
7MP456S45S
7MP456S55S
1.11
9
SSDCROSSREFERENCE
EDH8808HC-55CMHR
EDH8808HC-70CMHR
EDH8808C-10CMHR
EDH8808C-12CMHR
EDH8808C-15CMHR
EDH8808CL-20CMHR·
EDH8808CL-25CMHR
E DH8808A-1 OCMHR
EDH8808A-12CMHR
EDH8088A-15CMHR
EDH8808AL-20CMHR
EDH8808AL-25CMHR
EDH8832C-12C
E DH8832C-15C
EDH8832C-20C
EDH8832C-12CMHR
EDH8832C-15CMHR
EDH8832C-20CMHR
EDH8832HC-45CMHR
EDH8832HC-55CMHR
EDH8832HC-70CMHR
EDH8832HC-85CMHR
INOVA PIN
MT5C1008-70
8M864L85CB
8M864L 120CB
8M864L 150CB
8M864L 150CB
8M864L 150CB
7M864L85CB
7M864L 120CB
7M864L 150CB
7M864L 150CB
7M864L 150CB
8M856L85C
8M856L85C
8M856L85C
8M856L 1OOCB
8M856L 1OOCB
8M856L 1OOCB
7M856S45CB
7M856S55CB
7M856S65CB
7M856S75CB
IDTP/N
DIRECT
EQUIVALENT
71 M024-70
71 M024-85
71 M024-100
71 M025-70
71 M025-85
71 M025-100
IDTP/N
DIRECT
EQUIVALENT
71 M024-70
MT4S1288-30
MT4S1288-35
MT4S1288-45
MT2S321 6-30
MT2S3216-35
MT2S3216-45
MT4S6416-30
MT4S6416-35
MT4S6416-45
MTBS1632-12
MTBS1632-15
MTBS1632-20
MTBS1632-25
MTBS1632-30
MTBS1632-35
MTBS1632-45
MTBS6432-15
MTBS6432-20
MTBS6432-25
MTBS6432-30
MTBS6432-35
MTBS6432-45
8M824S30C
8M824S35C
8M824S45C
8M612S30C
8M612S35C
8M612S45C
8M624S30C
8M624S35C
8M624S45C
7MP4031 B12Z
7MP4031 S 15Z
7MP4031 S20Z
7MP4031 S25Z
7MP4031 S30Z
7MP4031 S35Z
7MP4031 S35Z
7MP4036B15Z
7MP4036S20Z
7MP4036S25Z
7MP4036S25Z
7MP4036S35Z
7MP4036S35Z
S128K8-70
S128K8-85
S128K8-100
S128K8T-70
S128K8T-85
S128K8T-100
MICRON
TECHNOLOGY PIN
8M864L55CB
8M864L75CB
64K (8K X8)
28 PIN DIP
7M856S
7M856S
7M856S
7M856S
7M856S
7M856S
8M856L
8M856L
8M856L
8M856L
IDTP/N
SIMILAR
PART
256K (32K X 8)
28 PIN DIP
256K (32K X 8)
28 PIN DIP
INOVA
ORG/PACKAGE
1 M (128K X 8) Monolithic
32 PIN DIP (2 CS)
1 M (128K X 8) Monolithic
32 PIN DIP (1 CS)
IDTP/N
SIMILAR
PART
MICRON TECHNOLOGY
ORG/PACKAGE
1 M (128K X 8) Monolithic
32 PIN DIP
1 MEG (128K X 8) JEDEC
32 PIN DIP
512K (32K X 16) JEDEC
40 PIN DIP
1 MEG (64K X 16) JEDEC
40 PIN DIP
512K (16K X 32) JEDEC
64 PIN ZIP
2 MEG (64K X 32) JEDEC
64 PIN ZIP
1.11
10
SSD CROSS REFERENCE
MT4S12832-20
MT4S 12832-25
MT4S 12832-35
MT4S 12832-45
MT8S25632-20
MT8S25632-25
MT8S25632-35
MT8S25632-45
MOSAIC PIN
MSM8128S-70
MSM8128S-85
MSM8128S-100
MSM8128S-120
MSM8128SX-70
MSM8128SX-85
MSM8128SX-100
MSM8128SX-120
MS1256CS-25
MS1256CS-35
MS8128SLU-55
MS8128SU-70
MS8128SL-10
MS8256RKL-10
MS8256RKL-12
MS8512FKX-85
MS8512FKX-10
MS8512FKX-12
MS8512SCMB-85
MS8512SCMB-10
MS8512SCMB-12
MS8512SC-25
MS8512SC-30
MS8512SC-35
MS8512SC-45
MS8512SC-55
MS8512SC-70
MS8512SCMB-30
MS8512SCMB-35
MS8512SCMB-45
MS8512SCMB-55
M S8512SCM B-70
MS8512RKX-10
MS8512RKX-12
MS8512RKX-15
MS1664FKX-30
MS1664FKX-35
MS1664FKX-45
MS1664BCX-25
MS1664BCX-35
MS1664BCXMB-25
MS1664BCXMB-35
MS3216RKX-12
MS3216RKX-15
MS3216RKX-20
MS3216RKX-25
MS3216RKX-35
MS3216RKX-45
7MP4095S20Z
7MP4095S25Z
7MP4095S35Z
7MP4095S45Z
7MP4045S20Z
7MP4045S25Z
7MP4045S35Z
7MP4045S45Z
IDTP/N
DIRECT
EQUIVALENT
71 M024-70
71 M024-85
71 M024-1 00
71M024-120
71 M025-70
71 M025-85
71M025-100
71M025-120
8M824S50C
8M824S70C
8M824S70C
7M4048L85N
7M4048L 1OON
7M4048L120N
7M4048S85CB
7M4048S100CB
7M4048S120CB
7MB4048S25P
7MB4048S30P
7MB4048S35P
7MB4048S45P
7MB4048S55P
7M4048L70N
7M4048S30CB
7M4048S35CB
7M4048S45CB
7M4048S50CB
7M4048S70CB
7MP4008L 1OOS
7MP4008L 1OOS
7MP4008L 1OOS
8M624S30C
8M624S35C
8M624S45C
7M624S25C
7M624S35C
7M624S25CB
7M624S35CB
7MP4031 B12Z
7MP4031 S15Z
7MP4031 S20Z
7MP4031 S25Z
7MP4031 S35Z
7MP4031 S35Z
4 MEG (128K X 32) JEDEC
64 PIN ZIP
8 MEG (256K X 32) JEDEC
64 PIN ZIP
IDTP/N
SIMILAR
PART
MOSAIC
ORG/PACKAGE
1M (128K X 8) Monolithic
32 PIN DIP (2 CS)
1M (128K X 8) Monolithic
32 PIN DIP (1 CS)
7MP156, 7MC156
7MP156, 7MC156
8M824SXXN, 8MP824
256K (256K X 1)
25 PIN SIP
1 MEG (128K X 8)
32 PIN DIP
7MP4034
7MP4034
2 MEG
32 PIN
4 MEG
32 PIN
(256K X 8)
SIP
(512K X 8) JEDEC
DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
4 MEG (512K X 8) JEDEC
32 PIN DIP
7MP4058L 1OOS
7MP4058L 120S
7MP4058L 120S
4 MEG (512K X 8)
36 PIN SIP
1 MEG (64K X 16) JEDEC
40 PIN DIP
1 MEG (64KX 16)
40 PIN DIP
512K (16K X32) JEDEC
64 PIN ZIP
1.11
11
SSD CROSS REFERENCE
PUMA 2S1000
7M4003SXXCH
PUMA 2S4000
7M4013SXXCH
PUMA 2E1000
7M7004SXXCH
MS3264FKX-25
MS3264FKX-35
MS3264FKX-45
MS3264FKX-55
MS3264RKX-15
MS3264RKX-20
MS3264RKX-25
MS3264RKX-35
MS3264RKX-20
MS32256FKX-25
MS32256FKX-30
MS32256FKX-35
MS32256FKX-45
MS32256FKX-55
MS32256RKX-20
MS32256RKX-25
MS32256RKX-30
MS32256RKX-35
MS32256RKX-45
MS32256RKX-55
MOTOROLA PIN
7MP4036S25Z
"
MCM32257-20
MCM32257-25
MCM3264-12
MCM3264-15
MCM3264-20
MCM8256-15
MCM8256-20
SMART MODULAR PIN
SM68512-85
SM68512-10
SM68512-12
SM232128-20
SM232128-25
SM232128-35
SM232256-20
SM232256-25
SM232256-35
SM332256-20
SM332256-25
SM332256-35
7M4017S35C
7M4017S40C
7M4017S50C
7MP4036815Z
7MP4036S20Z
7MP4036S25Z
7MP4036S35Z
7MP4036S45Z
7M84067S25P
7M84067S30P
7M84067S35P
7M84067S45P
7M84067S55P
7MP4045S20Z
7MP4045S25Z
7MP4045S30Z
7MP4045S35Z
7MP4045S45Z
7MP4045S55Z
IDT PIN
DIRECT
EQUIVALENT
7MP4045S20
7MP4045S25
7MP4036812
7MP4036B15
7MP4036S20
IDTP/N
DIRECT
EQUIVALENT
7M4048L85N
7M4048L 1OON
7M4048L 120N
7MP4095S20Z
7MP4095S25Z
7MP4095S35Z
7MP4045S20Z
7MP4045S25Z
7MP4045S35Z
7MP4045S20M
7MP4045S25M
7MP4045S35M
1 MEG
66 PIN
4 MEG
66 PIN
1 MEG
66 PIN
2 MEG
60 PIN
(32K X 32)
HIP
(128K X 32)
HIP'
(32K X 32) EEPROM
HIP
(64K X 32)
DIP .
2 MEG (64K X 32) JEDEC
64 PIN ZIP
8 MEG (256K X 32)
60 PIN DIP
8 MEG (256K X 32) JEDEC
64 PIN ZIP
IDTP/N
SIMILAR
PART
MOTOROLA
ORG/PACKAGE
8 MEG (256K X 32) JEDEC
64 PIN ZIP
2 MEG (64K X 32) JEDEC
64 PIN ZIP
7MP4034S15Z
7MP4034S20Z
IDTP/N
SIMILAR
PART
2 MEG (256K X 8) JEDEC
60 PIN ZIP
SMART MODULAR
ORG/PACKAGE
4 MEG (512K X 8) JEDEC
32 PIN DIP
4 MEG (128K X 32)JEDEC
64 PIN ZIP
8 MEG (256K X 32) JEDEC
64 PIN ZIP
8 MEG (256K X 32) JEDEC
64 PIN ZIP
1.11
12
TECHNOLOGY AND CAPABILITIES
IDT... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor
industry today. A new technology is rapidly displacing older
NMOS and bipolar technologies as the workhorse of the '80s
and beyond. That technology is high-speed CMOS. Integrated
Device Technology, a company totally predicated on and
dedicated to implementing high-performance CMOS products,
is on the leading edge of this dramatic change.
Beginning with the introduction of the industry's fastest
CMOS 2K x 8 static RAM, lOT has grown into a company with
multiple divisions producing a wide range of high-speed
CMOS circuits that are, in almost every case, the fastest
available. These advanced products are produced with lOT's
proprietary CEMOSTM technology, a twin-well, dry-etched,
stepper-aligned process utilizing progressively smaller
dimensions.
From inception, lOT's product strategy has been to apply
the advantages of its extremely fast CEMOS technology to
produce the integrated circuit elements required to implement
high-performance digital systems. lOT's goal is to provide the
circu its necessary to create systems which are far superior to
previous generations in performance, reliability, cost, weight,
and size. Many of the company's innovative product designs
offer higher levels of integration, advanced architectures,
higher density packaging and system enhancement features
that are establishing tomorrow's industry standards. The
company is/committed to providing its customers with an everexpanding ~eries of these high-speed, lower-power IC solutions
to system design needs.
lOT's commitment, however, extends beyond state-of-theart technology and advanced products to providing the highest
level of customer service and satisfaction in the industry.
Manufacturing products to exacting quality standards that
provide excellent, long-term reliability is given the same level
of importance and priority as device performance. lOT is also
dedicated to delivering these high-quality advanced products
on time. The company would like to be known not only for its
technological capabilities, but also for providing its customers
with quick, responsive, and courteous service. .
lOT's product families are available in both commercial and
military grades. As a bonus, commercial customers obtain the
benefits of military processing disciplines, established to meet
or exceed the stringent criteria of the applicable military
specifications.
lOT is the leading U.S. supplier of high-speed CMOS
circuits. The company's high-performance fast SRAM , FCT
logic, high-density modules, FIFOs, multi-port memories,
BiCEMOSTM ECl 1/0 memories, RISC SubSystems, and the
32- and 64-bit RISC microprocessor families complement
each other to provide high-speed CMOS solutions for a wide
range of applications and systems.
Dedicated to maintaining its leadership position as a stateof-the-art IC manufacturer, lOT will continue to focus on
maintaining its technology edge as well as developing a
broader range of innovative products. New products and
speed enhancements are continuously being added to each
of the existing product families, and additional product families
are being introduced. Contact your lOT field representative or
factory marketing engineer for information on the most current
product offerings. If you're building state-of-the-art equipment,
lOT wants to help you solve your design problems.
2.1
Ell
lOT MILITARY AND DESC-SMD PROGRAM
lOT is a leading supplier of military, high-speed CMOS
circuits. The company's high-performance Static RAMs, FCT
Logic Family, Complex Logic (CLP), FIFOs, Specialty
Memories (SMP), ECl I/O BiCMOS Memories, 32-bit RISC
Microprocessor, RISC Subsystems and high-density
Subsystems Modules product lines complement each other to
provide high-speed CMOS solutions to a wide range of
military applications and systems. Most of these product lines
offer Class B products which are fully compliant to the latest
revision of MIL-STD-883, Paragraph 1.2.1. In addition, lOT
offers Radiation Tolerant (RT), aswell as Radiation Enhanced
(RE), products.
lOT has an active program with the Defense Electronic
Supply Center (DESC) to list all of lOT's military compliant
SMD
devices on Standard Military Drawings (SMD). The SMD
program allows standardization of militarized products and
reduction of the proliferation of non-standard source control
drawings. This program will go far toward reducing the need
for each defense contractor to make separate specification
control drawings for purchased parts. lOT plans to have
SMDs for many of its product offerings. Presently, lOT has 88
devices which are listed or pending listing. The devices are
from lOT's SRAM, FCT Logic family, Complex Logic (CLP),
FIFOs and Specialty Memories (SMP) product families. lOT
expects to add another 20 devices to the SMD program in the
near future. Users should contact either lOT or DESC for
current status of products in the SMD program.
SMD
SMD
SRAM
lOT
LOGIC
lOT
CLP
lOT
84036/E
5962-88740
8413218
5962-86015/A
5962-86859
5962-86705/0
5962-85525/8
5962-8855218
5962-886621A
5962-88611/A
5962-88681/A
5962-88545
5962-89891
5962-89892
5962-89690
5962-38294/8
5962-89692
5962-89712
6116
6116LA
6167
7187
6198/719817188
6168
7164
71256L
712568
71682L
712588
71258L
7198
6198
6116
7164
7188
71982
39C108 & C
49C460A
39C60A
49C410
75C48S
49C402lA
7216L
7217L
7210
lOT
5962-86875/8
5962-87002lC
5962-88610/A
5962-88665/A
7130/7140
713217142
71338/71435
7133U7143L
FIFO
lOT
5962-87531
5962-86846/A
5962-88669
5962-89568
5962-89536
5962-89863
5962-89523
5962-89666
5962-89942
5962-89943
5962-89567
7201 LA
72404
72038
7204L
7202L
72018
72403L
7200L
72103L
72104L
7203L
54 FCT244/A
54 FCT245/A
54 FCT299/A
54 FCT373/A
54 FCT374/A
54 FCT377/A
54FCT138/A
54 FCT240/A
54 FCT273/A
54FCT861A18
54 FCT827A18
54FCT841A18
54FCT821A18
54FCT521/A
54FCT161/A
54 FCT573/A
54FCT823A18
54FCT163/A
54 FCT825A18
54 FCT863A18
29 FCT520Al8
54FCT646
54FCT139/A
54 FCT824A18
54 FCT533/A
54FCT1821A
54 FCT645A18
54 FCT640Al8
54 FCT534/A
54 FCT540/A
54FCT541/A
54FCT191/A
54 FCT241 IA
54 FCT399/A
54 FCT574/A
54 FCT833A18
54 FCT845A18
54 FCT543/A
5962-877081A
5962-88533/A
5962-886131A
5962-88643/A
5962-88743/A
5962-89517
5962-86893
5962-87686
5962-88733/A
SMP
5962-87630/8
5962-87629/C
5962-8686218
5962-87644/A
5962-87628/C
5962-87627/8
5962-87654/A
5962-87655/A
5962-87656/A
5962-89533
5962-89506
5962-88575
5962-88608
5962-88543/A
5962-88640/A
5962-886391A
5962-88656
5962-88657/A
5962-88674
5962-88661
5962-88736/A
5962-88775
5962-89508
5962-89665
5962-88651
5962-88652
5962-88653
5962-88654
5962-88655
5962-89767
5962-89766
5962-89733/A
5962-89732
5962-89652
5962-89513
5962-89731
5962-88675
5962-89730
2509tbl01
2.2
RADIATION HARDENED TECHNOLOGY
lOT manufactures and supplies radiation hardened products
for military/aerospace applications. Utilizing special processing
and starting materials, lOT's radiation hardened devices survive
in hostile radiation environments. In Total Oose, Oose Rate,
and environments where single event upset is of concern, lOT
products are designed to continue functioning without loss of
performance. lOT can supply all its products on these
processes. Total Oose radiation testing is performed in-house
2.3
on an ARACOR X-Ray system. External facilities are utilized
for device research on gamma cell, LlNAC and other radiation
equipment. lOT has an on-going research and development
program for improving radiation handling capabilities (See
"lOT Radiation Tolerant/Enhanced Products for Radiation
Environments" in Section 3) of lOT products/processes.
II
lOT LEADING EDGE CEMOS TECHNOLOGY
HIGH-PERFORMANCE CEMOS
and wide operating temperature range; it also achieves speed
and output drive equal or superior to bipolar Schottky TTL.
The last decade hasseen development and production offour
"generations" of lOT's CEMOS technology with process
improvements which have reduced lOT's electrical effective
(Left) gate lengths by more than 50 percent from 1.3 microns
(mi"ionths of a meter) in 1981 to 0.6 microns in 1989.
From lOT's beginnings in 1980, it has had a belief in and a
commitment to CMOS. The company developed a highperformance version of CMOS, ca"edenhanced CMOS
(CEMOS), that allows the design and manufacture of leadingedge components. It incorporates the best characteristics of
traditional CMOS, including low power, high noise immunity
CEMOSI
CEMOS II
Calendar Year
1981
A
1983
Drawn
Feature Size
2.5Jl
1.7Jl
Left
Basic
Proces
Enhancements
CEMOS III
CEMOS V
CEMOS VI
1985
1987
1989
1990
1.3Jl
1.2Jl
1.0Jl
O.8Jl
C
1.3Jl
1.1Jl
O.gJl
Dual-well,
Wet Etch,
Projection
Aligned
Dry Etch,
Stepper
Shrink,
Spacer
O.8Jl
Silicide,
BPSG,
BiCEMOS I
O.6Jl
O.45Jl
BiCEMOS II
BiCEMOS III
2514 drw 01
CEMOS IV .. CEMOS III - scaled process optimized for high-speed logic.
Figure 1.
Continual advancement of CEMOS technology allows lOT
to implement progressively higher levels of integration and
achieve increasingly faster speeds maintaining the company's
established position as the leader in high-speed CMOS
integrated circuits. In addition, the fundamental process
technology has been extended to add bipolar elements to the
CEMOS platform. lOT's BiCEMOS process combines the
ultra-high speeds of bipolar devices with the lower power and
cost of CMOS, allowing us to build even faster components
than straight CMOS at a slightly higher cost.
CEMOSI
1981
CEMOSII
1983
SEM photos (miniaturization)
CEMOSV
1989
2514 drw 02
Figure 2. Flfteen-Hundred-Power Magnification Scanning Electron
Microscope (SEM) Photos of the Four Generations of IDrs CEMOS
Technology
2.4
Potential
+nO
I
I
I
n-Substrate
-3V
NMOS
+5V
CEMOSTM
G~-
e
e
G
2514 drw 04
2514 drw 03
Figure 3. lOT CEMOS Device Cross Section
Figure 4. lOT CEMOS Built·ln High Alpha Particle Immunity
InpuVOutput Pad
ALPHA PARTICLES
1,000
t-
Random alpha particles can cause memory cells to
temporarily lose their contents or suffer a "soft error." Traveling
with high energy levels, alpha particles penetrate deep into an
integrated chip. As they burrow into the silicon, they leave a
trail of free electron-hole pairs in their wake.
The cause of alpha particles is well documented and
understood in the industry. lOT has considered various
techniques to protect the cells from this hazardous occurrence.
These techniques include dual-well structures (Figures 3 and
4) and a polymeric compound for die coating. Presently, a
polymeric compound is used in many of lOT's SRAMs; however,
the specific techniques used may vary and change from one
device generation to the next as the industry and lOT improve
the alpha particle protection technology.
I-
1\
'\
n-Substrate
Qi
il~
~
w.
(a)
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Typical
2514 drw 05
Figure 5. lOT CEMOS Latchup Suppression
LATCHUP IMMUNITY
A combination of careful design layout, selective use of
guard rings and proprietary techniques have resulted in virtual
elimination of latchup problems often associated with older
CMOS processes (Figure 5). The use of NPN and N-channel
I/O devices eliminates hole injection latchup. Double guard
ring structures are utilized on all input and output circuits to
absorb injected electrons. These effectively cut off the current
paths into the internal circuits to essentially isolate I/O circuits.
Compared to older CMOS processes which exhibit latchup
characteristics with trigger currents from 10-20mA, lOT
products inhibit latchup at trigger currents substantially greater
than this.
2.4
2
SURFACE MOUNT TECHNOLOGY
AND
lOT'S MODULE PRODUCTS
Requirements for circuit area reduction, utilizing the most
efficient and compact component placement possible and the
needs of production manufacturing for electronics assemblies
are the driving forces behind the advancement of circuit-board
assembly technologies. These needs are closely associated
with the advances being made in surface mount devices
(SMO) and surface mount technology (SMT) itself. Yet, there
are two major issues with SMT in production manufacturing of
electronic assemblies: high capital expenditures and complexity of testing.
The capital expenditure required to convert to efficient
production using SMT is still too high for the majority of
electronics companies, regardless of the 20-60% increase in
the board densities which SMT can bring. Because of this high
barrier to entry, we will continue to see a large market segment
[large even compared to the exploding SMT market] using
traditional through-hole packages (i.e. DIPs, PGAs, etc) and
assembly techniques. How can these types of companies
take advantage of SMO and SMT?Let someone else, such
as lOT, do it for them by investing time and money in SMT and
then in return offer through-hole products utilizing SMT processes. Products which· fit this description are mUlti-chip
modules, consisting of SMT assembled SMOs on a throughhole type substrate. Modules enable companies to enjoy SMT
density advantages and traditional package options without
the expensive startup costs required to do SMT in-house.
Although subcontracting this type of work to an assembly
house is an alternative, there still is the other issue of testing,
an area where many contract assembly operations fall short
of lOT's capability and experience. Prerequisites for adequate module testing sophisticated high performance parametric testers, customized test fixtures, and most importantly the experience to tests today's complex electronic
devices. Companies can therefore take advantage of lOT's
experience in testing and manufacturing high performance
CMOS mUlti-chip modules.
At lOT, SMO components are electrically tested, environmentally screened, and performance selected for each lOT
module. All modules are 100% tested as if they are a separate
functional component and are guaranteed to meet all specified parameters at the module output without the customer
having to understand the modules' internal workings.
Other added benefits companies get by using lOT's CMOS
module products are:
1) a wide variety of high performance, through-hole products utilizing SMO packaged components,
2) fast speeds compared with NMOS based products,
3) low power consumption compared with bipolar technologies, and
4) low cost manufacturability compared with GaAs based
products.
lOT has recognized the problems of SMT and began
offering CMOS modules as part of its standard product portfolio. lOT modules combine the advantages of:
1) the low power characteristics of lOT's CEMOS"" and
BiCEMOS"" products,
2) the density advantages of first class SMO components
including those from lOT's components divisions, and
3) experience in system level design, manufacturing, and
testing with its own in-house SMT operation.
lOT currently has two divisions (Subsystems and RISC
Subsystems) dedicated to the development of module products ranging from simple memory modules to complex VME
sized application specific modules to full system level CPU
boards. These modules have surface mount devices assembled on both sides of either a multi-layer glass filled epoxy
(FR-4) or a mUlti-layer co-fired ceramic substrate. Assembled
modules come available in industry standard through-hole
packages and other space-saving module packages. Industry proven vapor-phase or IR reflow techniques are used to
solder the SMOs to the substrate during the assembly process. Because of our affiliation with lOT's experienced semiconductor manufacturing divisions, we thoroughly understand and therefore test all modules to the applicable datasheet specifications and customer requirements.· .
Thus, lOT is able to offer today's electronic design engineers a unique solution for their "need-rTlOre-for-less"
problem.modules. These high speed, high performance
products offer the density advantages of SMO and'SMT, the
added benefit of low power CMOS technology, and throughhole packaged electronics without the high cost of doing it inhouse.
2.5
STATE-OF-THE-ART FACILITIES AND CAPABILITIES
• Integrated Device Technology.is headquartered in Santa
Clara, California -the heart of "Silicon Valley." The company's
operations are housed in six facilities totaling over 500,000
square feet. These facilities house all aspects of business
from research and development to design, wafer fabrication,
assembly, environmental screening, test, and administration.
In-house capabilities'include scanning electron microscope
(SEM) evaluation, particle impact noise detection (PIND),
plastic and hermetic packaging, military and commercial
testing, burn-in, life test, and a full complement of environmental
screening equipment.
.
The over-200,000-square-foot corporate headquarters
campus is composed of three buildings. The largest facility on
this site is a 100,000 square foot, two-building complex. The
first building, a 60,000-square-foot facility, is dedicated to the
Standard logic and RISC Microprocessor product lines, as
well as hermetic and plastic package assembly, logic products'
test, burn-in, mark, QA, and a reliability/failure analysis lab.
lOT's Packaging' and Assembly Process Development
teams are located here.' To keep pace with the development
of new products and to enhance the lOT philosophy of
"innovation," these teams have ultra-modern, integrated and
correspondingly sophisticated equipment and environments
at their disposal. All manufacturing is completed in dedicated
clean room areas (Class 10K minimum), with all preseal
operations accomplished under Class 100 laminarflow hoods.
Development of assembly materials, processes and
equipment is accomplished under a fully operational production
environment to ensure reliability and repeatable product. The
Hermetic Manufacturing and Process Development team is
currently producing custom products to the strict requirements
of M Il-STD-883. The fully automated plastic facility is currently
producing high volumes of USA-manufactured product, while
developing state-of-the-artsurfac- mount technology patterned
after Mll-STD-883.
Thesecond building of the complex houses sales, marketing,
finance, M IS, and Northwest Area Sales.
The RISC Subsystems Division is located across from the
two-building complex in a 50,000-square-foot facility. Also
located at this facility are Quality Assurance and wafer
fabrication services. Administrative services, , Human
Resources, International Planning, Shipping and Receiving
departments are also housed in this facility.
lOT's largest and newest facility, opened in 1990 in San
2.6
Jose, California, is a mUlti-purpose 150,OOO-square-foot, ultramodern technology development center. This facility houses
a 25,000 square foot, combined Class 1 (a maximum of one
particle-per-cubic-foot of 0.2 micron or larger), sub-half-micron
R&D fabrication facility and a wafer fabrication area. This fab
supports both production volumes of lOT products, including
some next-generation SRAMs, and the R&D efforts of the
technology developm ent staff . Technology developm ent efforts
targeted for the center include advanced silicon processing
and wafer fabrication techniques. A test area to support both
production and research is located on-site. The building is
also the home of the FIFO, ECl, and Subsystems product
lines.
lOT's second largest facility is located in Salinas, California,
about an hour south of Santa Clara. This 95,000-square-foot
facility, located on 14 acres, houses the Static RAM Division
and Specialty Memory product line. Constructed in 1985, this
facility contains an ultra-modern 25,OOO-square-foot highvolume wafer fabrication area measured at Class 2-to-3 (a
maximum of 2 to 3 particles-per-cubic-foot of 0.2 micron or
larger) clean room conditions. Carefu I design and construction
of this fabrication area created a clean room environment far
beyond the 1985 average for U.S. fab areas. This made
possible the production of large volumes of high-density
submicron geometry, fast static RAMs. Thisfacility also houses
shipping areas for lOT's leadership family of. CMOS static
RAMs. This site can expand to accommodate a 250,000square-foot complex.
To extend our capabilities while maintaining strict control of
our processes, lOT has an operational Assembly and Test
facility located in Penang, Malaysia. This facility assembles
product to U.S. standards, with all assemblies done under
laminar flow conditions (Class 100) until the silicon is encased
in its final packaging. All products in this facility are
manufactured to the quality control requirements of Mil-STD883.
All of lOT's facilities are aimed at increasing our
manufacturing productivity to supply ever-larger volumes of
high-performance, cost-effective, leadership CMOS products.
fI
SUPERIOR QUALITY AND RELIABILITY
Maintaining the highest standards of quality in the industry
on all products is the basis of Integrated Device Technology's
manufacturing systems and procedures. From inception,
quality and reliability are built into all of IDT's products. Quality
is "designed in" at every stage of manufacturing - as opposed
to being "tested-in" later - in order to ensure impeccable
performance.
Dedicated commitment to fine workmanship, along with
development of rigid controls throughout wafer fab, device
assembly and electrical test, create inherently reliable products.
Incoming materials are subjected to careful inspections. Quality
monitors, or inspections, are performed throughout the
manufacturing flow.
lOT military grade monolithic hermetic products are designed
to meet or exceed the demanding Class B reliability levels of
MIL-STD-883 and MIL-M-38510, as defined by Paragraph
1.2.1 of MIL-STD-883.
Product flow and test procedures for all monolithic hermetic
military grade products are in accordance with the latest
revision and notice of M IL-STD-883. State-of-the-art production
techniques and computer-based test procedures are coupled
with tight controls and inspections to ensure that products
meet the requirements for 100% screening. Routine quality
conformance lot testing is performed as defined in MIL-STD883, Methods 5004 and 5005.
For I DT module products, screening of the fully assembled
substrates is performed, in addition to the monolithic level
screening, to assure package integrity and mechanical
reliability. All modules receive 100% electrical tests (DC,
functional and dynamic switching) to ensure compliance with
the "subsystem" specifications.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, IDT
ensures that commercial, industrial and military grade products
consistently meet customer requirements for quality, reliability
and performance.
SPECIAL PROGRAMS
Class S. IDT also has all manufacturing, screening and
test capabilities in-house (except X-ray and some Group D
tests) to perform complete Class S processing per MIL-STD883 on alilDT products and has supplied Class S products on
several programs.
Radiation Hardened. IDT has developed and supplied
several levels of radiation hardened products for military/
aerospace applications to perform at various levels of dose
rate, total dose, single event upset (SEU), upset and latchup.
IDT products maintain nearly their same high-performance
levels built to these special process requirements. The
company has in-house radiation testing capability used both
in process development and testing of deliverable product.
IDT also has a separate group within the company dedicated
to supplying products for radiation hardened applications and
to continue research and development of process and products
to further improve radiation hardening capabilities.
2.7
QUALITY AND RELIABILITY
QSP-QUALlTY, SERVICE AND PERFORMANCE
Quality from the beginning, is the foundation for lOT's
commitment to supply consistently high-quality products to
our customers. lOT's quality commitment is embodied in its all
pervasive Continuous Quality Improvement (CQI) process.
Everyone who influences the quality of the product-from the
designer to the shipping clerk-is committed to constantly
improving the quality of their actions.
lOT QUALITY PHILOSOPHY
liTa make quantitative constant improvement in the quality
of our actions that result in the supply of leadership products
in conformance to (he requirements of our customers. "
lOT's ASSURANCE STRATEGY FOR CQI
Measurable standards are essential to the success of CQI.
All the processes contributing to the final quality of the product
need to be monitored, measured and improved upon through
the use of statistical tools.
DEVELOPMENT
I
I
ASSEMBLY
I
Productivity Improvement
Using constant improvement teams made up from •
employees at all levels of the organization.
Leadership
Focusing on quality as a key business parameter and
strategic strength.
Total Employee Participation
Incorporating the cal process into the lOT Corporate
Culture.
People Excellence
Committing to growing, motivating and retaining people
through training, goal setting, performance measurement
and review.
TEST
I
SHIP
Our customers receive the benefit of our optimized systems.
Installed to enhance quality and reliability, these systems
provide accurate and timely reporting on the effectiveness of
manufacturing controls and the reliability and quality
performance of lOT products and services.
ORDER ENTRY
I
PRODUCTION CONTROL
SERVICE FLOW
Documentation
Documenting and training in policies, procedures,
measurement techniques and updating through
characterization/ capability studies.
Customer Service
Supporting the customer, as a partner, through
performance review and pro-active problem solving.
FAB
PRODUCT FLOW
Standardization
Implementing policies, procedures and measurement
techniques that are common across different operational
areas.
.
I
SHIPPING
I
CUSTOMER SUPPORT
Thesesystems and controls concentrate on cal byfocusing
on the following key elements:
Statistical Techniques
Using statistical techniques, including Statistical Process
Control (SPC) to determine whether the product!
processes are under control.
3.1
PRODUCT FLOW
Product quality starts here. lOT has mechanisms and
procedures in place that monitor and control the quality of our
development activities. From the calibration of design capture
libraries through process technology and product
characterization that establish whether the performance,
ratings and reliability criteria have been met. This includes
failure analysis of parts that will improve the prototype product.
Atthe pre-production stage once again in-house qualification
tests assure the quality and reliability of the product. All
specifications and manufacturing flows are established and
personnel trained before the product is placed into production.
Manufacturing
To accomplish cal during the manufacturing stage, control
items are determined for major manufacturing conditions.
Data is gathered and statistical techniques are used to control
specific manufacturing processes that affect the quality of the
product.
In-process and final inspections are fed back to earlier
processes to improve product quality. All product is burnedin (where applicable) before 100% inspection of electrical
characteristics takes place.
Products which pass final inspection are then subject to
Quality Assurance and Reliability Tests. This data is used to
improve manufacturing processes and provide reliability
predictions of field applications.
Inventory and Shipping
Controls in shipping focus on ensuring parts are identified
and packaged correctly. Care is also taken to see that the
correct paperwork is present and the product being shipped
was processed correctly.
SERVICE FLOW
Quality not only applies to the product but to the quality -of
-service we give our customers. Services is also constantly
monitored for improvement.
Order Procedures
Checks are made at the order entry stage to ensure the
correct processing of the Customer'sproduct. Afterverification
and data entry the Acknowledgements (sent to Customers)
are again checked to ensure details are correct. As part of the
CQI process, the results of these verifications are analyzed
using statistical techniques and corrective actions are taken.
Customer Support
lOT has a worldwide network of sales offices and Technical
Development Centers. These provide local customer support
on business transactions, and in addition, support customers
on applications information, technical services, benchmarking
of hardware solutions, and. demonstration of 'various
Development Workstations.
The key to CQI is the timely resolution of defects and
implementation of the corrective actions. This is no more
important than when product failures are found by a
customer.When failures are found at the customer's incoming
inspection, in the production line, or the field application, the
Division Quality Assurance group is the focal point for the
investigation' of the cause of failure and implementation of the
corrective action. lOT constantly improves the level of support
we give our customers by monitoring the response time to
customers that have detected a product failure. Providing the
customer with an analysis of the failure, including corrective
actions and the statistical analysis of defects, brings CQI full
circle-full support of our customers and their designs with
high-quality products.
SUMMARY
Production Control
Production Control (P.C.) is responsible for the flow and
logistics of material as it moves through the manufacturing
processes. The quality of the actions taken by P.C. greatly
impinges on the quality of service the customer receives.
Because many of our customers have implemented Just-inTime (JIT) manufacturing practices, IOTas a supplier also has
to adopt tt,ese same disciplines. As a result, employees
receive extensive training and the performance level of key
actions are kept under constant review. These key actions
include:
Quotation response and accuracy.
Scheduling response and accuracy.
Response and accuracy of Expedites.
Inventory, management, and effectiveness.
On time delivery.
3.1
In 1990, lOT made the commitment to "Leadership through
Quality, Service, and Performance Products".
We believe by following that credo lOT and our cusotmers
will be successful in the coming decade.With the
implementation of the CQI strategy within the company, we
will satisfy our goal ...
"Leadership through Quality, Service and Performance
Products".
2
lOT QUALITY CONFORMANCE PROGRAM
A COMMITMENT TO QUALITY
Integrated Device Technology's monolithic assembly
products are designed, manufactured and tested in accordance
with the strict controls and procedures required by Military
Standards. The documentation, design and manufacturing
criteria of the Quality and Reliability Assurance Program were
developed and are being maintained to the most current
revisions of MIL-38S1 0 as defined by paragraph 1.2.1 of MILSTO-883 and MIL-STO-883 requirements.
Product flow and test procedures for all Class B monolithic
hermetic Military Grade microcircuits are in full compliance
with paragraph 1.2.1 of MIL-STO-883. State-of-the-art
production techniques and computer-based test procedures
are coupled with stringent controls and inspections to ensure
that products meet the requirements for 100% screening and
quality conformance tests as defined in MIL-STO-883, Methods
S004 and SOOS.
Product flow and test procedures for all plastic and
commercial hermetic products are in accordance with industry
practices for producing highly reliable microcircuits to ensure
that products meet the lOT requirements for 100% screening
and quality conformance tests.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, lOT
ensures that our products consistently meet customer
requirements for quality, reliability and performance.
4.
Wire Bond Monitor: Product samples are routinely
subjected to a strength test per Method 2011 , Condition
0, to ensure the integrity of the lead bond process.
5.
Pre-Cap Visual: Before the completed package is
sealed, 100% of the product is visually inspected to
Method 2010, Condition B criteria.
6.
Environmental Conditioning: 100% of the sealed
product is subjected to environmental stress tests.
These thermal and mechanical tests are designed to
eliminate units with marginal seal, die attach or lead
bond integrity.
7.
Hermetic Testing: 100% of the hermetic packages
are subjected to fine and gross leak seal tests to
eliminate marginally sealed units or units whose
seals may have become defective as a result of
environmental conditioning tests.
8.
Pre-Burn-In Electrical Test: Each product is 100%
electrically tested at an ambienttemperatu re of +2SoC
to lOT data sheet or the customer specification.
9.
Burn-In: 100% of the Military Grade product is
burned-in under dynamic electrical conditions to the
time and temperature requirements of Method 101S,
Condition o. Except for the time, Commercial Grade
product is burned-in as applicable to the same
conditions as Military Grade devices.
10.
Post-Burn-In Electrical: After burn-in, 100% of the
Class B Military Grade product is electrically tested to
lOT data sheet or customer specifications over the
-SsoC to + 12SoC temperature range. Commercial
Grade products are sample tested to the applicable
temperature extremes.
11.
Mark: All product is marked with product type and lot
code identifiers. MIL-STO-883 compliant Military
Grade products are identified with the required
compliant code letter.
12.
Quality Conformance Tests: Samples of the Military
Grade product which have been processed to the
100% screening tests of Method 5004 are routinely
subjected to the quality conformance requirements of
Method SOOS.
SUMMARY
Monolithic Hermetic Package Processing Flow(1)
Refer to the Monolithic Hermetic Package Processing Flow
diagram. All test methods refer to MIL-STO-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.
Die Visual Inspection : Wafers are cut and separated
and the individual die are 100% visually inspected to
strict lOT-defined internal criteria.
3.
Die Shear Monitor: To ensure die attach integrity,
product samples are routinely subjected to a shear
strength test per Method 2019.
NOTE:
1. For quality requirements beyond Class B levels such as SEM analysis, X-Ray inspection, Particle Impact Noise Reduction (PIND) test, Class S screening
or other customer specified screening flows, please contact your Integrated Device Technology sales representative.
3.2
II
SUMMARY
Monolithic Plastic Package Processing Flow
6.
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods' refer to MIL-STO-883 unless
otherwise stated.
1. Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.
Post Mold Cure: Plastic encapsulated devices are
baked to ensure an optimum polymerization of the
epoxy mold compound so as to enhance moisture
resistance characteristics.
7.
Pre-Burn-In Electrical: Each product is 100%
electrically tested at an ambienttemperature of +25°C
to lOT data sheet or the customer specification.
8.
Burn-In: Except for MS I Logic fam ily devices where
it may be obtained as an option, all Commercial
Grade plastic package products are burned-in for 16
hours at + 125°C minimum (or equivalent), utilizing
the same burn-in conditions as the Military Grade
product.
Topside silicon nitride passivation is all applied to all
wafers for better moisture barrier characteristics.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.
9.
Die Visual Inspection: Wafers are 100% visually
inspected to strict, lOT defined internal criteria.
3.
4.
5.
Post-Burn-In Electrical: After burn-in, 100% of the
plastic product is electrically tested to lOT data sheet
or customer specifications at the maximum
temperature extreme. The minimum temperature
extreme is tested periodically on an audit basis.
,Die Push Test:
To ensure die attach integrity,
product samples are routinely subjected to die push
tests, patterned after MIL-STO-883, Method 2019.
10. Mark: All product is marked with product type and lot
code identifiers. Products are identified with the
assembly and test locations.
Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull and ball shear tests to
ensure the integrity ofthewire bond process, patterned
after MIL-STOc883, Method 2011, Condition O.
11. Quality Conformance Inspection: Samples of the
plastic product which have been processed to the
100% screening requirements are subjected to the
Periodic Quality Conformance Inspection Program.
Where indicated, the test methods are patterned after
MIL-STO-883 criteria.
Pre-Cap Visual: Before encapsulation, all product
lots are visually inspected (using LTPO 5 sampling
plan) to criteria patterned after MIL-STO-883, Method
2010, Condition B.
3.2
2
TABLE 1
This table defines the device
clas~ screening procedures for lOT's high reliability products in conformance with MIL-STD-883C.
Monolithic Hermetic Package Final Processing Flow
OPERATION
CLASS-C(1)
CLASS-8
CLASS-S
TEST METHOD
RQMT
TEST METHOD
RQMT
TEST METHOD
RQMT
1015 Condo 0,
240 Hrs @ 125°C or
equivalent
100%
1015 Condo 0,
160 Hrs. @ 125°C min
or equivalent
100%
Per applicable
device specification
100%
POST BURN-IN
ELECTRICAL:
Static (~C), Functional
and Switching (AC)
Per applicable
device specification
+25, -55 and 125°C
100%
Per applicable
device specification
+25, -55 and 125°C
100%
Per applicable (2)
device specification
100%
Group A ELECTRICAL:
Static (~C), Functional
and Switching (AC)
Per applicable
device specification
and 5005
Sample
Per applicable
device specification
and 5005
Sample
MARK/LEAD
STRAIGHTENING
lOT Spec
100%
lOT Spec
100%
lOT Spec
100%
FINAL ELECTRICAL
TEST
Per applicable
device specification
+25°C
100%
Per applicable
device specification
+25°C
100%
Per applicable
device specification
+25°C
100%
lOT Spec
100%
lOT Spec
100%
lOT Spec
100%
Sample
lOT Spec
Sample
100%
lOT Spec
100%
BURN-IN
FINAL VISUAUPACK
QUALITY CONFORMANCE
INSPECTION
5005 Group B, C, O.
QUALITY SHIPPING
INSPECTION
(VisuaVPlant Clearance)
lOT Spec
Sample
100%
5005 Group B,C,O.
lOT Spec
Per applicable (2)
Sample
device specification
NOTES:
1. Class-C = lOT commercial spec. for hermetic and plastic packages
2. Typical O°C, 70°C, Extended -55°C +125°C
3.2
3
II
RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
INTRODUCTION
DEVICE ENHANCEMENTS
The need for high-performance CMOS integrated circuits
in military and space systems is more critical today than ever
before. The low power dissipation that is achieved using
CMOS technology, along with the high complexity and density
levels, makes CMOS the nearly ideal component for all types
of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may
be encountered. The implication of a device failure within a
military or space system clearly is critical. lOT has made a
significant contribution toward providing reliable radiationtolerant systems by offering integrated circuits with enhanced
radiation tolerance. Radiation environments, lOT process
enhancements and device tolerance levels achieved are
described below.
Of the four radiation environments above, lOT has taken
considerable data on the first two, Total Dose Accumulation
and Dose Rate. lOT has developed a process thatsignificantly
Radiation
Category
Source
Effect
Total Dose
Gamma
Space or
Nuclear
Event
Permanent
Dose Rate
Photons
Nuclear
Event
Temporary
Upset of Logic
State or
Latch-up
SEU
Cosmic
Rays
Space
Temporary
Upset of
Logic State
Neutron
Neutrons
Nuclear
Event
Device Leakage
Due to Silicon
Lattice Damage
THE RADIATION ENVIRONMENT
There are four different types of radiation environments
that are of concern to builders of military and space systems.
These environments and their effects on the device operation,
summarized in Figure 1, are as follows:
Total Dose Accumulation refers to the total amount of
. accumulated gamma rays experienced by the devices in the
system, and is measured in RAOS (SI) for radiation units
experienced at the silicon level. The physical effect of gamma
rays on semiconductor devices is to cause threshold shifts (Vt
shifts) of both the active transistors as well as the parasitic field
transistors. Threshold voltages decrease as total dose is
accumulated; at some point, the device will begin to exhibit
parametric failures as the input/output and supply currents
increase. At higher radiation accumulation levels, functional
failures occur. In memory circuits, however, functional failures
due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of
radiation, usually photons or electrons, experienced by the
devices in the system due to a pulse event, and is measured
in RAOS (Si) per second. The effect of a high dose rate or
burst of radiation on CMOS integrated circuits is to cause
temporary upset of logic states and/or CMOS latch-up. Latchup can cause permanent damage to the device.
Single Event Upset (SEU) is a transient logic state change
caused by high-energy ions, such as energetic cosmic rays,
striking the integrated circuits. As the ion passes through the
silicon, charge is either created through ionization or direct
nuclear collision. If collected by a circuit node, this excess
charge can cause a change in logic state of the circuit.
Dynamic nodes that are not actively held at a particular logic
state (dynamic RAM cells for example) are the most susceptible.
These upsets are transient, but can cause system failures
known as "soft errors."
Neutron Irradiation will cause structural damage to the
silicon lattice which may lead to device leakage and, ultimately,
functional failure.
Primary
Particle
2510 drw 01
Figure 1.
improves the radiation tolerance of its devices within these
environments. Prevention of SEU failures is usually
accomplished by system-level considerations, such as Error
Detection and Correction (EOC) circuitry, since the occurrence
of SEUs is not particularly dependent on process technology.
Through lOT's customer contracts, SEU has been gathered
on some devices. Little is yet known about the effects of
neutron-induced damage. For more information on SEU
testing, contact lOT's Radiation Hardened Product Group.
Enhancements to lOT's standard process are used to
create radiation enhanced and tolerant processes. Field and
gate oxides are "hardened" to make the device less susceptible
to radiation damage by modifying the process architecture to
allow lower temperature processing. Device implants and Vts
adjustments allow more Vt margin. In addition to process
changes, lOT's radiation enhanced process utilizes epitaxial
substrate material. The use of epi substrate material provides
a lower substrate resistance environment to create latch-Up
free CMOS structures.
RADIATION HARDNESS CATEGORIES
Radiation Enhanced (RE) or Radiation Tolerant ('RT)
versions of lOT products follow lOT's military product data·
sheets whenever possible (consult factory). lOT's Total Dose
Test plan exposes a sample of die on a wafer to a particular
Total Dose level via ARACOR X-Ray radiation. This Total
Dose Test plan qualifies each 'RE or'RTwafertoaTotal Dose
level. Only wafers with sampled die that pass Total Dose leyel
3.3
tests are assembled and used for orders (consult factory for
more details on Total Dose sample testing). With regard to
Total Dose testing, clarifications/exceptions to MIL-STD-883,
Methods 5005 and 1019 are required. Consult factory for
more details.
The 'RE and 'RT process enhancements enable IDT to
offer integrated circuits with varying grades of radiation
tolerance or radiation "hardness".
• Radiation Enhanced process uses Epi wafers and is able
to provide devices that can be Total Dose qualified to 10K
RADs (Si) or greater by IDT's ARACOR X-Ray Total Dose
sample die test plan (Total Dose levels require negotiation,
consult factory for more details).
• Radiation Tolerant product uses standard wafer/process
material that is qualified to 10K RADs (Si) Total Dose by
IDT's ARACOR X-Ray Total Dose sample die test plan.
Integrated Device Technology can provide Radiation
Tolerant/Enhanced versions of all product types (some speed
grades may not be available as 'RE).
Please contact your IDT sales representative or factory
marketing to determine availability and price of any IDT
product processed in accordance with one of these levels of
radiation hardness.
CONCLUSION
There has been widespread interest within the military and
space community in IDT's CMOS product line for its radiation
hardness levels, as well as its high-performance and low
power dissipation. To serve this growing need for CMOS
circuits that must operate in a radiation environment, IDT has
created a separate group within the company to concentrate
on supplying products for these applications.Continuing
research and development of process and products, including
the use of in-house radiation testing capability, will allow
Integrated Device Technology to offer continuously increasing
levels of radiation-tolerant solutions.
3.3
2
PACKAGE DIAGRAM OUTLINES
II
SECTION PAGE
MONOLITHIC PACKAGE DIAGRAM OUTLINES (Continued) ................................... 4.3
PKG.
J18-1
J20-1
J28-1
J32-1
J44-1
J52-1
J68-1
J84-1
DESCRIPTION
18-Pin Plastic Leaded
20-Pin Plastic Leaded
28-Pin Plastic Leaded
32-Pin Plastic Leaded
44-Pin Plastic Leaded
52-Pin Plastic Leaded
68-Pin Plastic Leaded
84-Pin Plastic Leaded
L20-1
L20-2
L22-1
L24-1
L28-1
L28-2
L32-1
L44-1
L48-1
L52-1
L52-2
L68-1
L68-2
20-Pin
20-Pin
22-Pin
24-Pin
28-Pin
28-Pin
32-Pin
44-Pin
48-Pin
52-Pin
52-Pin
68-Pin
68-Pin
E16-1
E20-1
E24-1
E28-1
E28-2
16-Lead
20-Lead
24-Lead
28-Lead
28-Lead
CERPACK ................................................................................................................
CERPACK ................................................................................................................
CERPACK ................................................................................................................
CERPACK ................................................................................................................
CERPACK ................................................................................................................
9
9
9
9
9
F20-1
F20-2
F24-1
F28-1
F28-2
F48-1
F64-1
F68-1
F84-2
20-Lead Flatpack .................................................................:..................................................
20-Lead Flatpack (.295 body) .................................................................................................
24-Lead Flatpack ....................................................................................................................
28-Lead Flatpack ....................................................................................................................
28-Lead Flatpack ....................................................................................................................
48-Lead Quad Flatpack ........................................................................................ ~ ................ .
64-Lead Quad Flatpack ..........................................................................................................
68-Lead Quad Flatpack ..........................................................................................................
84-Lead Quad Flatpack (cavity up) ....................................................................................... .
5
5
5
5
5
6
6
PQ80-2
PQ100-1
PQ100-2
PQ132-1
80-Lead Plastic Quad Flatpack (IEAJ) ...................................................................................
100-Lead Plastic Quad Flatpack (JEDEC) ............................................................................ .
100-Lead Plastic Quad Flatpack (EIAJ) .................................................................................
132-Lead Plastic Quad Flatpack (JEDEC) ............................................................................ .
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Leadless Chip
Chip Carrier (rectangular) ...................................................................
Chip Carrier (square) ..........................................................................
Chip Carrier (square) ......................................................................... .
Chip Carrier (rectangular) ...................................................................
Chip Carrier (square) ......................................................................... .
Chip Carrier (square) ..........................................................................
Chip Carrier (square) ..........................................................................
Chip Carrier (square) ......................................................................... .
25
24
24
25
24
24
24
24
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
12
10
12
12
10
12
12
10
10
11
11
11
11
(rectangular) ............................................................................
(square) .................................................................................. .
(rectangular) ............................................................................
(rectangular) ............................................................................
(square) ...................................................................................
(rectangular) ............................................................................
(rectangular) ............................................................................
(square) ...................................................................................
(square) .................................................................................. .
(square) .................................................................................. .
(square) ...................................................................................
(square) ....................................................: ............................. .
(square) .................................................................................. .
II
7
8
23
22
23
22
MODULE PACKAGE DIAGRAM OUTLINES
Module package diagrams are located at the back of each Subsystems data sheet.
4.2
2
C)
..
PACKAGE DIAGRAM OUTLINES
Integrated Device Technology, Inc.
DUAL IN-LINE PACKAGES
14
D
-\
Ie::::::]
~e~
-1
~
b1
LF=======A
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. THE MINIMUM LIMIT· FOR DIMENSION b1 MAYBE .023 FOR· CORNER LEADS.
16-28 LEAD CERDIP (300 MIL)
OWG
#
i# OF LOS (N)
SYMBOL
A
b
b1
C
D
E
E1
e
L
L1
Q
S
S1
ex
D16-1
16
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
.750 .830
.285 .310
.290 .320
.100 BSC
.125 .175
.150
.015 .055
.020 .080
.005
0"
15"
D18-1
18
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
.880 .930
.285 .310
.290 .320
.100 SSC
.125 .175
.150
.015 .055
.020 .080
.005
0"
15"
020-1
20
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
.935 1.060
.285 .310
.290 .320
.100 SSC
.125 .175
.150
.015 .060
.020 .080
.005
0"
15"
4.3
D22-1
22
MIN MAX
.140 .200
.015 .021
.045 .060
.009 .012
1..050 1.080
.285 .310
.300 .320
.. 100 SSC
.125 .175
.150
.015 .060
.020 .080
.005
0"
15"
D24-1
24
MIN MAX
.140 .200
.015 .021
.045 .065
.009 .014
1.240 1.280
.285 .310
.300 .320
.100 BSC
.125 .175
.150
.015 .060
.030 .080
.005
0"
15"
D28-3
28
MIN MAX
.140 .200
.015 .021
.045 .065
.009 .014
1.440 1.485
.285 .310
.300 .320
.100 SSC
.125 .175
.150
.015 .060
.030 .080
.005
0"
15"
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24-40 LEAD CERDIP (400 & 600 MIL)
1#
DWG #
OF LDS (N)
SYMBOL
A
b
b1
e
D
E
E1
e
L
L1
Q
S
S1
ex.
D24-3
24
MIN
MAX
.130 .175
.015
.021
.045 .065
.009 .014
1.180 1.250
.350 .410
.380 .420
.100 sse
.125
.175
.150
.015 .060
.030 .070
.005
O·
15·
D24-2
24
MIN
MAX
.090 .190
.014 .023
.045 .060
.008 .012
1.230 1.290
.500 .610
.590 .620
.100 sse
.125 .200
.150
.015 .060
.030 .080
.005
O·
15·
D28-1
28
MIN
MAX
.090
.200
.014
.023
.045
.065
.008
.014
1.440 1.490
.510
.600
.590
.620
.100 Bse
.125
.200
.150
.020
.060
.030
.080
.005
O·
15·
D40-1
40
MIN
MAX
.160 .220
.014 .023
.045 .065
.008 .014
2.020 2.070
.510 .600
.590 .620
.100 Bse
.125 .200
.150
.020 .060
.030 .080
.005
o·
15·
32 LEAD CERDIP (WIDE BODY)
1#
DWG #
OF LDS eN)
SYMBOL
A
b
b1
e
D
E
E1
e
L
L1
Q
S
S1
ex
D32-1
32
MIN
MAX
.120
.210
.014
.023
.045
.065
.008
.014
1.625 1.675
.570
.600
.590
.620
.100 sse
.125
.200
.150
.020
.060
.030
.080
.005
O·
15·
4.3
2
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
20-32 LEAD SIDE BRAZE (300 MIL)
S2
L
Q 1 -_ .----W=t==========::L..:~
rt=
,
-+---'"---r--SEATING PLANE
C
E1
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
1#
DWG #
OF LDS (N)
SYMBOL
A
b
b1
e
D
E
E1
e
L
L1
Q
S
S1
S2
C20-1
20
MIN
MAX
.090
.200
.014
.023
.045
.060
.008
.015
.970 1.060
.260
.310
.290
.320
.100 Bse
.125
.200
.150
.015
.060
.065
.030
.005
.005
C22-1
22
MIN
MAX
.100
.200
.023
.014
.045
.060
.008
.015
1.040 1.120
.310
.260
.290
.320
.100 BSC
.125
.200
.150
.015
.060
.030
.065
.005
.005
C24-1
24
MIN
MAX
.090
.200
.015
.023
.045
.060
.008
.015
1.180 1.230
.310
.220
.290
.320
.100 BSC
.125
.200
.150
.015
.060
.030
.065
.005
.005
-
4.3
e28-1
28
MAX
MIN
.090
.200
.023
.014
.045
.060
.015
.008
1.380 1.420
.310
.220
.290
.320
.100 BSC
.200
.125
.150
.060
.015
.065
.030
.005
.005
-
C32-3
32
MIN
MAX
.090
.200
.014
.023
.045
.060
.008
.014
1.580 1.640
.280
.310
.290
.320
.100 Bse
.100
.175
.150
.060
.030
.030
.065
.005
.005
3
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24-68 LEAD SIDE BRAZE (600 MIL)
D - - - - - - - i..~1
D
E
1
I
1 .._
68 LEAD OPTION
'---t--'..,-,--,-,-.-....,.,............--r--r-r-r-r---r-T--r-T--.-r--r-t---r-1r--r-r--r-,--r-'
~S~!2__:j~~~========~======~~
·rlt-Ull. I '
Q
T T~--l:ri
li.l
!:
L - . ___ .~
L1
1
I
I
e-l
~~OTES:
1.
2.
#
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
SSC - BASIC Lt::AD SPACING BETWEEN CENTERS.
OWG #
OF LOS eN)
SYMBOL
A
b
b1
C
0
E
El
e
L
L1
Q
S
Sl
S2
C24-2
24
MIN
MAX
.090
.190
.015
.023
.045
.060
.008
.012
1.180 1.220
.610
.575
.595
.620
.100 BSC
.125
.175
.:50 I .020
.060
.030
.065
.005
.005
-
C28-3
28
MIN
tv1AX
.085 I .190
.015
.022
.045
.060
.008
.012
1.380 1.430
.580
.610
.595
.620
.100 sse
.175
.125
.150
.060
.020
.030
.065
.005 i .005 I
C32-1
32
MIN 1 MAX
.100
.190
.015 ! ~023
.045 ! .060
.014
.008
1.580 1.640
.580
.610
.590
.620
.100 SSC
.100 I .175
.150
.020
.060
.030 I .065
.005 I .005
4.3
C40-1
40
MIN
MAX
.085
.190
.015
.023
.045
.060
.008
.012
1.980 2.030
.580
.610
.595
.620
.100 Bse
.125 i .175
.150
.020 I .060
.030 I .065
.005 II
.005
C48-2
48
MIN
MAX
.190
.100
.023
.015
.060
.045
.008
.012
2.370 2.430
.550
.610
.620
.595
.100 Bse
.125
.175
.1.50
.060
.020
.065
.030
.005 , .005 i -
C68-1
68
Ml~
MAX
;085
.190
.023
.015
J)60
.045
.008
.Oi2
2.380 2.440
.580
.610
.590
.620
.070 sse
.125 i .175
.150
.020
.070
.030 I .OoS
.005
.005 i -
4
PACKAGE DIAGRAM OUTLINES
FLATPACKS
20-28 LEAD FLATPACK
..--- D
b
1i
-------t
1
S1
-jA
II
Q
L
E3
N
S
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
1#
DWG #
OF LDS (N)
SYMBOL
A
b
C
D
E
E2
E3
e
K
L
Q
S
S1
F20-1
20
MIN
MAX
.092
.045
.019
.015
.004
.007
.540
.360
.340
.130
.030
.050 BSC
.006
.015
.250 i .370
.010 i .040
.045
.000
F20-2
20 (.295 BO;:)Y)
MIN
MAX
.045
.092
.015
.019
.007
.004·
.540
.245
.303
.130
.030
.050 BSC
.008
.015
.250
.370
.010
.040
.045
.005
F24-1
24
MiN
MAX
.090
.045
.015
.019
.004
.007
.640
.420
.360
.180
.030
.050 BSC
F28-1
28
MAX
MIN
.045
.090
.015
.019
.004
.007
.710
. 740
.520
.480
.180
.040
.050 ase
F28-2
28
MAX
MIN
.045
.115
.015
.019
.004
.007
.710 . .740
.480
.520
.180
.040
.050 Bse
-
-
-
-
-
-
.250
.010
.250
.010
.370
.045
.045
.250
.026
-
.370
.040
.045
.370
.045
.045
.005
-
.005
-
.005
4.3
-
-
5
PACKAGE DIAGRAM OUTLINES
FLATPACKS (Continued)
48-64 LEAD QUAD FLATPACK
.-.--- E
--~
E2
r--E1
f-- L - -
-- L--
D
I
I
,I
I
~
D1
L
re
J
~
t
D
D2
A2
~
II
b
t
I
PIN 1 I D J
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
it
DWG #
OF LDS (N)
SYMBOL
A
A1
A2
b
C
DIE
D1/E1
D2/E2
e
L
ND/NE
F48-1
48
MIN
MAX
.089
.108
.079
.096
.058
.073
.018
.022
.008
.010
.750
.100 REF
.550 BSC
.050 BSC
.350
.450
12
F64-1
64
MIN
MAX
.070
.090
.060
.078
.030
.045
.016
.020
.009
.012
.885
.915
.075 REF
.750 BSC
.050 BSC
.350
.450
16
6
PACKAGE DIAGRAM OUTLINES
FLATPACKS (Continued)
68 LEAD QUAD FLATPACK
D
D1
D2
I
I
~ hT 'IT
hT hT
hT hT 'IT
~PIN
PIN 1
F
~
hT hT ITT
1 INDEX
:::t
=I
1=
=I
1=
=l
_1=
=I
-
-
==t
E2
E1
E
=I
1=
=t
I
1=
~rU
~ ~
=I
~ ~ ~
~ ~
~V-
I
-
L
f
I---e
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED
2. sse - BASIC LEAD SPACING BETWEEN CENTERS.
#
DWG #
OF LDS (N)
SYMBOL
A
A1
b
e
DIE
D1/E1
D2/E2
e
L
ND/NE
F68-1
68
MIN
MAX
.080
.145
.070
.090
.014
.021
.008
.012
1.640
1.870
.926
.970
.800 SSC
.050 BSC
.350
.450
17
4.3
7
PACKAGE DIAGRAM OUTLINES
FLATPACKS (Continued)
84 LEAD QUAD FLATPACK (CAVITY UP)
1
D1
D2
I
I
~
~~I~~~~,.~~~~lr------r
j
t~
PIN 1
PIN 1 INDEX
E2
E1
E
f
E3
)
'"I
I
OWG#
# OF LDS (N)
SYMBOL
A
A1
b
C
O/E
D1/E1
02/E2
03/E3
e
L
ND/NE
F84-2
84
MIN
MAX
.140
.105
.014
.020
.007
.013
1.940 1.960
1.170
1.130
1.000 BSC
.500 BSC
.050 BSC
.350
.450
21
NOTES:
1. ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
4.3
8
PACKAGE DIAGRAM OUTLINES
CERPACKS
16-28 LEAD CERPACK
.----- 0
-----..,~
S1
Q
L
tt-
N
E1
E
-'---_-( J
K
II
I
I I
I
--I~ ---e~
L
--S
NOTES:
1. ALL DIMENSION ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
DWG #
'# OF LOS (N'
SYMBOL
A
b
C
D
E
E1
e
K
L
Q
S
S1
E16-:-1
16
MIN
MAX
.055
.085
.015
.019
.0045 .006
.370
.430
.245
.285
.305
.050 BSC
.008
.015
.250
.370
.040
.026
.045
.005
-
E20-1
20
MAX
MIN
.045
.092
.015
.019
.0045 .006
.540
.245
.300
.305
.050 BSC,
.008
.015
.250
.370
.026
.040
.045
.005
E24-1
24
MIN
MAX
.045
.090
.019
.015
.0045 .006
.640
- .300
.420
.440
.050 BSC'
.008
.015
.370
.250
.026
.040
.045
.005
4.3
E28-2
E28-1
28
28
MAX
MIN
MAX - MIN
.045
.115
.045
.090
.015
.019
.015
.019
.0045 -.006 .0045 .006
.740
.740
;340
.380.460
.520
-,
.550
.400
.050 BSC
.050 BSC
.008
.015
.008
.015
.370
.250
.370' i.250
.045
.026
.045
.026
.045.045
.000
.005
~
9
PACKAGE DIAGRAM OUTLINES
LEAD LESS CHIP CARRIERS
J
h X 45"
3 PL
X 45"
iA1i
-4--+--
+
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
E
--I--{---y-
~L3
B3~
0
20-48 LEAD Lce (SQUARE)
DWG
#
# OF LDS (N)
SYMBOL
A
A1
B1
B2
B3
D/E
D1/E1
D2/E2
D3/E3
e
e1
h
J
L
L1
L2
L3
ND/NE
L20-2
20
MAX
MIN
.100
.064
.054 .066
.022 .028
.072 REF
.006
.022
.342 .358
.200 BSC
.100 BSC
.358
.050 SSC
.015
.040 REF
.020 REF
.045
.055
.045
.055
.077 .093
.003
.015
5
L28-1
28
MIN
MAX
.064
.100
.050 .088
.022 .028
.072 REF
.006
.022
.442 .460
.300 BSC
.150 BSC
.460
.050 BSC
.015
.040 REF
.020 REF
.055
.045
.045 .055
.077 .093
.003
.015
7
L44-1
44
MIN
MAX
.064
.120
.054 .088
.022 .028
.072 REF
.006
.022
.640 .660
.500 BSC
.250 SSC
.560
.050 SSC
.015
.040 REF
.020 REF
.045
.055
.045 .055
.077
.093
.003
.015
11
4.3
L48-1
48
MIN
MAX
.120
.055
.090
.045
.023
.017
.072 REF
.006 .022
.554 .572
.440 Bse
.220 SSC
.500
.535
.040 sse
.015
.012 RADIUS
.020 REF
.033 .047
.047
.033
.093
.077
.015
.003
12
10
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS (Continued)
52-68 LEAD LCC (SQUARE)
DWG #
# OF LOS (N)
SYMBOL
A
A1
B1
B2
B3
O/E
01/E1
D2/E2
D3/E3
e
e1
h
J
L
L1
L2
L3
ND/NE
L52-1
52
MIN
MAX
.061
.087
.077
.051
.022
.028
.072 REF
.006
.022
.739
.761
.600 Bse
.300 Bse
.661
.050 Bse
.015
.040 REF
.020 REF
.045
.055
.045
.055
.077
.093
.015
.003
13
L52-2
52
MIN
MAX
.120
.082
.072 .088
.022
.028
.072 REF
.006
.022
.739
.761
.600 BSe
.300 BSe
.661
.050 Bse
.015
.040 REF
.020 REF
.055
.045
.045
.055
.075
.093
.003
.015
13
L68-2
68
MIN
MAX
.082
.120
.072 .088
;022
.028
.072 REF
.006
.022
.938
.962
.800 Bse
.400 Bse
.862
.050 Bse
.015
.040 REF
.020 REF
.055
.045
.045
.055
.095
.075
.003
.015
17
4.3
L68-1
68
MIN
MAX
.065
.120
.075
.055
.014
.008
.072 REF
.006
.022
.554
.566
.400 Bse
.200 Bse
.535
.025 BSe
.015
.040 REF
.020 REF
.055
.045
.055
.045
.093
.077
.015
.003
17 .
11
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS (Continued)
h X 45"
3 PL
J X 45", A 1 i
E
t
--l
-r--+---+-
A
D3
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
20-32 LEAD LeC (RECTANGULAR)
1#
DWG #
OF LDS (N~
SYMBOL
A
A1
B1
S2
S3
D
D1
D2
D3
E
E1
E2
E3
e
e1
h
J
L
L1
L2
L3
ND
NE
L20-1
20
MIN
MAX
.060 .075
.050
.065
.022 .028
.072 REF
.006
.022
.284 .296
.150 Bse
.075 sse
.280
.420 .435
.250 Bse
.125 sse
.410
.050 sse
.01.5
.040 REF
.020 REF
.045
.055
.045 .055
.080 .095
.015
.003
4
6
L22-1
22
MIN
MAX
.100
.064
.054 .063
.022
.028
.072 REF
.006
.022
.284 .296
.150 Bse
.075 sse
.280
0480
.496
.300 sse
.150 sse
.480
.050 sse
.015
.012 RADIUS
.012 RADIUS
.039
.051
.051
.039
.097
.083
.003
.015
4
7
L24-1
24
MIN
MAX
.064
.120
.054 .066
.022 .028
;072 REF
.006
.022
.292 .308
.200 Bse
.100 Bse
.308
.392 0408
.300 Bse
.150 sse
.408
.050 sse
.015
.025 REF
.015 REF
.040
.050
.040 .050
.077 .093
.003
.015
5
7
4.3
+
L28-2
28
MIN
MAX
.060
.120
.050 .088
.022 .028
.072 REF
.006
.022
.342 .358
.200 Bse
.100 SSC
.358
.560
.540
0400 sse
.200 sse
.558
.050 sse
.015
.040 REF
.020 REF
.045
.055
.045
.055
.077
.093
.015
.003
5
9
~L3
B3~
0
L32-1
32
MIN
MAX
.120
.060
.050 .088
.028
.022
.072 REF
.022
.006
.458
.442
.300 sse
.150 sse
.458
.560
.540
.400 sse
.200 sse
.558
.050 sse
.015
.040 REF
.020 REF
.055
.045
.045
.055
.077
.093
.015
.003
7
9
12
II
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS
68 PIN PGA (CAVITY UP)
¢B1
1
2
3
4
5
7
8
9 10 11
TOP VIEW
---r-
GGGG GoG EB
KGGGGG GGGGG
JGG
GG
HGG
GG
GGG
GG
F
+ GG
EGG
DGG
GG
CGG
GG
B<11GGGG GGGGEB
A
GG0 G G0 GEB
L
-----t---.-
E1
E
-,
-t---t-----L-
1~1-4--1..-
~1
.1.1
PIN 1 ID
SEATING PLANE
DWG
#
G68-1
# OF PINS (Nl
SYMBOL
A
¢B
¢B1
¢B2
DIE
D1/E1
e
L
M
Q
68
MIN
.070
.016
MAX
.145
.020
.080
.040
.060
1.140
1.180
1.000 BSC
.100 BSC
.120
.140
11
.040 .. 060
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC. LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "MOl REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDT'S OPTION.
4.3
13
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
84 PIN PGA ( CAVITY UP -
11 X 11 GRID)
TOP VIEW
1 2
3
4
5
L00000
K00000
J00
H00
0
+
G000
F+t-&-t+-e-H-&+-
E000
E1
-,
E
000
D00
00
c00
0
0
B00000
A
0000
00
00000
0000f-+tt----'-
~1
1.1.
.1.1
PIN 1 ID
SEATING PLANE
DWG
#
# OF PINS eN)
SYMBOL
A
'¢B
¢B1
¢B2·
DIE
D1/E1
e
L
M
Q
G84-3
84
MIN
MAX
.070
.145
.016
.020
.080
.040.· .060
1.080 1.120
. 1.000 BSC
.100 BSC
.120
.140
11
.040
.060
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDT'S OPTION.·
.
4.3
14
PACKAGE DIAGRAM OULTINES
PIN GRID ARRAYS (Continued)
108 PIN PGA ( CAVITY UP)
BOTTOM VIEW
1
2
3
4
5
6
7
8
/
TOP VIEW
¢B1
9 10 J11 12 _ - . - . . - - - - - - - t - - - - - - - - - - ,
8 G G G 8 G GG G G G (DI-+++-----rLG000G0GGGG00
KG00GG0000000
JGG0
GG8
HGG8
00G
GGG8
+
000 E1
FGG8
0GG
EGGG
G00
DG0G
000
c800000G0GG00
BGG00G0G0GG00
M
E
+
A E~G0G0GGGGG0H-++-CP---L..
1-4------
~1 =======:.I~~I
PIN 1
10-./
SEATING PLANE
DWG #
# OF PINS eN)
SYMBOL
A
¢B
¢B1
¢B2
DIE
D1/E1
e
L
M
Q
G108-1
108
MIN
MAX
.070
.145
.016
.020
.080
.040
.060
1.188
1.212
1.100 BSC
.100 BSC
.120
.140
12
.040
.060
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS
5. CHAMFERED CORNERS ARE IDT'S OPTION.
4.3
15
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES
16-32 LEAD PLASTIC DIP (300 MIL)
I~
~I
D
PLANE
I
I
eA
~
~
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. 0 & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
1#
DWG #
OF LOS (N)
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
a
S
Q1
MIN
.140
.015
.015
.050
.OOB
.745
.300
.247
.090
.310
.120
0'
.015
.050
P16-1
P22-1
P28-2
16
22
28
MAX
.165
.035
.022
.070
.012
.760
.325
.260
.110
.370
.150
15'
.035
.070
MIN
.145
.015
.015
.050
.008
1.050
.300
.240
.090
.310
.120
O·
.020
.055
MAX
.165
.035
.022
.065
.012
1.060
.320
.270
.110
.370
.150
15'
.040
.075
4.3
MIN
.145
.015
.015
.045
.008
1.345
.300
.270
.090
.310
.120
o·
.020
.055
P32-2
32
MAX
.180
.030
.022
.065
.015
1.375
.325
.295
.110
.400
.150
15·
.042
.065
MIN
.145
.015
.016
.045
.008
1.545
.300
.275
.090
.310
.120
0'
.020
.055
MAX
.180
.030
.022
;060
.015
1.585
.325
.295
.110
.400
.150
15'
.060
.065
16
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
18-24 LEAD PLASTIC DIP (300 MIL -
FULL LEAD)
~
E1
t
E
, t
Ur--+----f--+----,~
S
Q1
TI
PLANE
L
I
~
I
eA
~
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD' FLASH OR PROTRUSIONS.
DWG #
P1B-1
P20-1
# OF LDS eN)
18
20
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
IX
S
Q1
MIN
.. 140
.015
.015
.050
.. OOB '
.BB5.
.300
.247
.090
.310
.120
0'
.040
.050
MAX
.100
.035
.020
.070
.012
.910
.325
.260
.110
.370
.150
15'
.060
,070
MIN
.140
.015
.015
.050
.OOB
1.022
.300
.240
.090
.310
.120
0'
.025
055
P24-1
24
MAX
.100
.035
.020
.070
.012
1.040
.325
.2BO
.110
.370
.150
15'
.070
075
4.3
MIN
.140
.015
.015
.050
.OOB
1.240
.300
.250
.090
.310.
.120
0'
.055
055
MAX
.105
.035
.020
.065 '
.012
1.255
.320
.275
.110
.370
.150
15'
.075
.070
17
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
24-48 LEAD PLASTIC DIP (600 MIL)
f
E1
t
E
, t
US
~----------~~------------~
Q1
~
TI
L
--",~-c
eA
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2. D & E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
#
IJWG J/:
OF LEADS (N
SYMBOLS
A
A1
b
b1
C
D
E
E1
e
eA
L
ex
S
Q1
P?4-2
24
MIN
MAX
.160
.1~
.015
.035
.015
.020
.050
.065
.008
.012
1.240 1.260
.600
.620
.530
.550
.090
.110
.610
.670
.120
.150
o·
15·
.060
.080
.060
.080
P32-1
32
MIN
MAX
.170
.190
.015
.050
.016
.020
.045
.055
.012
.008
1.645 1.655
.600
.625
.530
.550
.090
.110
.610
.670
.125
.135
O·
15·
.070
.080
.065
.075
P28-1
28
MIN
MAX
.160
.185
.015
.035
.015
.020
.050
.065
.008
.012
1.420 1.460
.600
.620
.550
.530
.090
.110
.610
.670
.150
.120
o·
15·
.080
.055
.080
.060
4.3
P_40-1
40
MIN
MAX
.160
.185
.015
.035
.015
.020
.050
.065
.012
.008
2.050
2.070
.600
.620
.550
.530
.090
.110
.610
.670
.120
.150
O·
15·
.070
.085
.080
.060
P48-1
48
MIN
MAX
.170
.200
.015
.035
.015
.020
.050
.065
.008
.012
2.420 2.450
.600
.620
.530
.560
.090
.110
.610
.670
.120
.150
o·
15·
.060
.075
.060
.080
18
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE Ie
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. 0 & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE .
•
PIN 1
e
~T. hfttt~~
B
--lrA1---'"
.
. SEATING PLA~~J
16-24 LEAD SMALL OUTLINE (GULL WING DWG
#
#
OF LDS (N)
SYMBOL
--tL~
ex
JEDEC)
S016-1
S018-1
S020-2
S024-2
16 (.300)
18 (.300)
20 (.300")
24 (.300")
MIN
MIN
MAX
MIN
MAX
MAX
MIN
MAX
A
.095
.1043
.095 .1043
.095
.1043
.095
.1043
A1
.005
.0118
.005
.0118
.005
.0118
.005
.0118
B
.014
.020
.014
.020
.014
.020
.014,
.020
e
.0091
.0125
.0091 .0125
.0091
0125
.0091 .0125
D
.403
.413
.447
.497
.511
e
.050 Bse
.292
.2992
h
.010
H
.400
L
.018
.045
ex
O·
8"
0"
S
.023
.035
.023
E
.462
.050 Bse
.050 Bse
.292 .2992
.292
.2992
.020
.010
.020
.010
.419
. .400
.419
.018 . .045
.600
.614
.050 Bse
.292
.2992
.020
.010
.020
.400
.419
.400
.419
.018
.045
.018
.045
8"
0"
8"
0"
8"
.035
.023
.035
.023
.035
4.3
19
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE Ie (Continued)
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS
AND TO BE MEASURED FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE.
, PIN 1
e
~~hfr~~~
-II-B
t\
A11T
SEATING
PLA~E' J
28 LEAD SMALL DUTLING (GULL WING DWG
1#
#
OF LDS (N)
S028-2
S028-3
28 (.300")
28 (.330")
SYMBOL
MIN
MAX
A
.095
.1043
.110
.120
A1
.005
.0118
.005
.014
B
.014
.020
.014
.019
C
.0091
.0125
.006
.010
D
.700
.712
.718
.728
e
E
.050 BSe
.292
.2992
MIN
II
--JLfJEDEC)
MAX
.050 BSe
.340
.350
h
.010
.020
.012
.020
,H
.400
.419
.462
.478
L
.018
.045
.028
.045
ex
O·
8'
O·
8'
S
.023
.035
.023
.035
4.3
20
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE Ie (Continued)
NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. D1 & E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSION AND TO BE MEASURED
FROM THE BOTTOM OF THE PKG.
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004"
AT THE SEATING PLANE
1fT
N
E1
E
~.~lli
~-------D1------~~
~ X 45"
t~~c
I..
-I
~~B1
E2
20-32 LEAD SMALL OUTLINE (J-BEND, 300 MIL)
DWG
#
#
OF LDS (N)
SYMBOLS
A
A1
S
B1
e
D1
E
E1
E2
e
h
S
S020-1
20
MIN
MAX
.120
.140
.078
.095
-
-
.014
.020
.013
.008
.500
.512
.335
.347
.292
.300
.262
.272
.050 Bse
.010
.020
.023
.035
S024-4
24
MIN
MAX
.130
.148
.082
.095
.026
.032
.015
.020
.007
.011
.620
.630
.335
.345
.295
.305
.260
.280
.050 Bse
.010
.020
.032
.043
S024-8
24
MIN
MAX
.120
.140
.078
.091
-
-
.014
.019
.0091
.0125
.602
.612
.335
.347
.292
.299
.262
.272
.050 Bse
.010
.016
.032
.043
4.3
S028-5
28
MIN
MAX
.120
.140
.078
.095
.014
.020
.008
.013
.700
.712
.335
.347
.292
.300
.272
.2~2
.050 Bse
.012
.020
.023
.035
S032-2
32
MIN
MAX
.130
.148
.082
.095
.026
.032
.016
.020
.008
.013
.820
.830
.330
.340
.295
.305
.260
.275
.050 sse
.012
.020
.032
.043
21
PACKAGE DIAGRAM OUTLINES
PLASTIC QUAD FLATPACKS
100-132 LEAD PLASTIC QUAD FLATPACK (JEDEC)
NOTES:
1. ALL DIMENSIONS ARE IN INCHES, UNLESS
OTHERWISE SPECIFIED.
2. Bse - BASIC LEAD SPACING BETWEEN
CENTERS.
3. PIN 1 IDENTIFIER CAN BE POSITIONED AT
EITHER ONE OF THESE TWO LOCATIONS.
4. DIMENSIONS D1, D2, E1, AND E2 DO NOT
INCLUDE MOLD PROTRUSIONS. ALLOWABLE
MOLD PROTRUSIONS ARE AS FOLLOWS:
D1 & E1 = .010 MAX.
D2 & E2 = .007 MAX.
5. ND & NE REPRESENT NUMBERS OF LEADS
IN D & E DIRECTIONS RESPECTIVELY.
E1 E E2
~
-II- b~J ~
~SEATING
PLANE
.025 MIN
(OPTIONAL)
DWG IF
# OF LDS (N)
SYMBOLS
A
A1
B
b1
C
D
D1
D2
D3
e
E
E1
E2
E3
L
ex
ND/NE
PQ100-1
100
MIN
MAX
.160
.1BO
.020
.040
.OOB
.016
.OOB
.012
.0055
.OOB
.B75
.885
.747
.753
.B97
.903
.600 REF
.025 BSC
.B75
.885
.747
.753
.B97
.903
.600 REF
.020
.030
0"
B"
25/25
PQ132-1
132
MIN
MAX
.1BO
.160
.040
.020
.016
.OOB
.012
.OOB
.OOB
.0055
1.075 1.0B5
.953
.947
1.097 1.103
.BOO REF
.025 BSC
1.075 1.0B5
.947
.953
1.097 1.103
.BOO REF
.020
.030
0"
8"
33/33
4.3
22
III
~
PACKAGE DIAGRAM OUTLINES
PLASTIC QUAD FLATPACKS (Continued)
80 & 100 LEAD RECTANGULAR PLASTIC QUAD FLATPACK (EIAJ)
1#
DWG #
OF LOS (N)
SYMBOLS
A
A1
A2
C
0
01
03
E
E1
E3
L
ND/NE
P
W
ZD
ZE
PQBO-2
PQ100-2
100
MIN
MAX
MIN
MAX
2.BO
3.40
2.BO
3.40
.25
.25
2.54
3.05
2.54
3.05
.13
.20
.13
.20
23.65 24.15 23.65 24.15
19.90 20.10 19.90 20.10
1B.40 REF
18.85 REF
17.65 1B.15 17.65 1B.15
13.90 14.10 13.90 14.10
12.00 REF
12.35 REF
.65
.95
.65
.95
20/30
16/24
.BO BSC
.65 BSC
.25
.30
.45
.40
.BO
.575
1.00
.B25
BO
NOTES:
1. ALL DIMENSIONS ARE IN METRIC, UNLESS
OTHERWISE SPECIFIED.
2. BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. 01 & E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS .254 PER SIDE.
4. NO & NE REPRESENT NUMBERS OF LEADS IN
o & E DIRECTIONS RESPECTIVELY.
4.3
23
PACKAGE DIAGRAM OUTLINES
PLASTIC LEADED CHIP CARRIERS
20-84 LEAD PLce (SQUARE)
1-----
D
----I
A1
C
~---D1---~
45· x .045
B
SEATING PLANE
HEATSINK OPTIONAL ON J84-1
NOTES:
1.
2.
3.
4.
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
BSC - BASIC LEAD SPACING BETWEEN CENTERS
D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE
ANOTHER WITHIN .004" AT THE SEATING PLANE.
ND & NE REPRESENT NUMBER OF LEADS IN D & E DIRECTIONS
RESPECTIVELY.
D1 & E1 SHOULD BE MEASURED FROM THE BOTTOM OF THE PKG.
5.
6.
DWG #
OF LDS
SYMBOL
A
A1
B
b1
C
C1
D
D1
D2/E2
D3/E3
E
E1
#
e
ND/NE
J20-1
20
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.385 .395
.350 .356
.290 .330
.200 REF
.385 .395
.350 .356
.050 BSC
5
J28-1
28
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.485 .495
.450 .456
.390 .430
.300 REF
.485 .495
.450 .456
.050 BSC
7
J44-1
44
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.685 .695
.650 .656
.590 .630
.500 REF
.685 .695
.650 .656
.050 BSC
11
J52-1
52
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.785 .795
.750 .756
.690 .730
.600 REF
.785 .795
.750 .756
.050 BSC
13
4.3
J68-1
68
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
.985 .995
.950 .956
.890 .930
.800 REF
.985 .995
.950 .956
.050 SSC
17
J84-1
84
MIN MAX
.165 .180
.095 .115
.026 .032
.013 .021
.020 .040
.008 .012
1.185 1.195
1.150 1.156
1.090 1.130
1.000 REF
1.185 1.195
1.150 1.156
.050 BSC
21
24
PACKAGE DIAGRAM OUTLINES
PLASTIC LEADED CHIP CARRIERS (Continued.)
18-32 LEAD PLce (RECTANGULAR)
-8---
m
+
-----13-
E1
E
B
!. °D~ ~N_D)---t
I
SEATING
OPTIONAL FEATURE
ADHESIVE PEDESTAL
(32 LO ONLY)
PLANE~
I
I
r--D2~
\
OWG
#
#
J18-1
32
18
OF LOS
SYMBOL
J32-1
MIN
MAX
MIN
MAX
A
.120
.140
.120
.140
A1
.075
.095
. 075
.095
B
.026
.032
.026
,.032'
b1
.013
.021
.013
.021
C
.015
.040
.015
.040
C1
. 008
.012
.008
.012
C2
-
-
.005
.015
D
.320
.335
.485
.495
D1
.289
. 293
.449
.453
02
.225
.265
.390
.430
03
.150 REF
.300 REF
E
.520
.535
.585
.595
E1
.489
.493
.549
.553
E2
.422
.465
.490
.5,30
E3
.200 REF
.400 REF
e
.050 BSC
.050 BSC
ND/NE
4/5
-.,
NOTES:
1. ALL DIMENSIONS' ARE IN INCHES,:UNLESS
OTHERWISE SPECIFIED .
2 . BSC - BASIC LEAD SPACING BETWEEN
CENTERS.
3. o & E DO Nor INCLUDE MOLD FLASH OR
.'"
PROTRUSIONS. "
""
4. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN.004'"
AT THE' SEATING PLANE .
5 . ND & NE REPRESENT "NUMBERS OF LEADS IN
o & E DIRECTIONS RESPECTIVELY.
6 . 01 & E1 SHOULD BE MEASURED FROM THE i
BOTTOM OF THE PACKAGE .
7 /
9
4.3
25
FIFO PRODUCTS
FIFO MEMORIES
Integration of lOT high-speed static RAM technology with
internal support logic yields high-performance, high-density
FIFO memories. A FIFO is used as a memory buffer between
two asynchronous systems with simultaneous read/write
access. The data rate between the two systems can be
regulated by monitoring the status flags and throttling the read
and write accesses. Since these FIFOs are built with an
internal RAM pointer architecture, there is no fall-through time
between a write to a memory location and a read from that
memory location. System performance is significantly improved over the shift register-based arschitecture of previous
FIFO designs which are handicapped with long fall-through
times.
lOT offers the widest selection of monolithic FIFOs, ranging
from shallow 64x4 and 64x5 to the high-density 16Kx9.
Shallow FIFOs regulate data flow in tightly couped computational engines. High-density FIFOs store large blocks in
networking, telecommunication and data storage systems.
The IOT7200 FIFO family (256x9 through the 16Kx9 FIFOs)
are all pin and function compatible, making density upgrades
simple. Alii OT FIFOs can be cascaded to greaterword depths
and expanded to greater word widths with no external support
logic.
lOT's high-speed SyncFIFOTM is ideal for multiprocessor
systems, workstations and high-end graphics. The innovative
architecture of the SyncFIFO (internal I/O registers with separate clock and enable inputs), along with wider data bus,
simplifies design and reduces interface log icc.
The Parallel-Serial FIFOs incorporate a serial input or a
serial output shifter for serial-to-parallel or parallel-to-serial
bus interface. The Parallel-Serial FIFOs also offer six status
flags for flexible data throttling.
A variety of packages are available: standard plactic FIP
and CEROIP, surface mount ceramic LCe, PLCC and SOIC,
and high-reliability flatpack. Increasing board density is the
overwhelming goal of lOT's package development efforts, as
demonstrated by the introduction of the 300 mil ThinOIP.
FIFO modules, composed of four LCC devices mounted on
a multi-layer co-fired ceramic substrate, increase densities to
32Kx18 which are pin-compatible with current monolithic
versions.
lOT is committed to offering FIFOs of increasing density,
speed and enhanced architectural innovations, such as Flexishift™ and the BiFIFO, for easier system interface.
5.0
TABLE OF CONTENTS
PAGE
FIFO PRODUCTS
IOT7200
IOT7201
IOT7202
IOT7203
IOT7204
IOT7205
IOT7206
IOT72005
IOT72015
IOT72025
IOT72021
IOT72031
IOT72041
IOT72103
IOT72104
IOT72105
IOT72115
IOT72125
IOT72131
IOT72141
IOT72132
IOT72142
IOT72200
IOT72210
IOT72220
10T72230
IOT72240
IOT72420
IOT72201
10T72211
IOT72221
IOT72231
IOT72241
IOT72421
IOT72215
IOT72225
10T72205LB
IOT72215LB
IOT72225LB
IOT72235LB
IOT72245LB
IOT72401
IOT72402
10T72403
IOT72404
IOT72413
IOT7251
IOT72510
IOT7252
10T72520
IOT72511
IOT72521
256 x 9-Bit Parallel FIFO ...........................................................................................
512 x 9-Bit Parallel FIFO ...........................................................................................
1024 x 9-Bit Parallel FIFO ....................................................................~....................
2048 x 9-Bit Parallel FIFO .........................................................................................
4096 x 9-Bit Parallel FIFO ........................................................... ..............................
8192 x 9-Bit Parallel FIFO .........................................................................................
16384 x 9-Bit Parallel FIFO ..................................................... ..................................
256 x 18-Bit Parallel First-In/First-Out FIFO ......................... .....................................
512 x 18-Bit Parallel First-In/First-Out FIFO ................ ..............................................
1K x 18-Bit Parallel First-In/First-Out FIFO ................................................................
1K x 9-Bit Parallel Flagged FIFO with OE .................................................................
2K x 9-Bit Parallel Flagged FIFO with OE .................................................................
4K x 9-BitParaliel Flagged FIFO with OE .................................................................
2048 x 9-Bit ConfigurableParaliel/Serial FIFO ...........................................................
4096 x 9-Bit Configurable Parallel/Serial FIFO ..........................................................
256 x 16-Bit Parallel-to-Serial FIFO ...........................................................................
512 x 16-Bit Parallel-to-Serial FIFO ...........................................................................
1024 x 16-Bit Parallel-to-Serial FIFO .........................................................................
2048 x 9-Bit Parallel-to-Serial FIFO ...........................................................................
4096 x 9-Bit Parallel-to-Serial FIFO ...........................................................................
2048 x 9-Bit Parallel/Serial FIFO ...............................................................................
4096 x 9-Bit Parallel/Serial FIFO ...............................................................................
256 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................................................
512 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................................................
1024 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
2048 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
4096 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
64 x 8-Bit Parallel SyncFIFOTM (Clocked FIFO) ........................................................
256 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................................................
512 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ......................................................
1024 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
2048 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
4096 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
64 x 9-Bit Parallel SyncFIFOTM (Clocked FIFO) ........................................................
512 x 18-Bit Parallel Synchronous FIFO ...................................................................
1024 x 18-Bit Parallel Synchronous FIFO .................................................................
256 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
512 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ....................................................
1024 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..................................................
2048 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..................................................
4096 x 18-Bit Parallel SyncFIFOTM (Clocked FIFO) ..................................................
64 x 4-Bit Parallel FIFO .............................................................................................
64 x 5-Bit Parallel FIFO .............................................................................................
64 x 4-Bit Parallel FIFO (w/Output Enable) ...............................................................
64 x 5-Bit Parallel FIFO (w/Output Enable) ...............................................................
64 x 5-Bit Parallel FIFO with Flags ............................................................................
512 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO ......................................
512 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO ......................................
1024 x 18-Bit - 1K x 9-Bit Bus Matching Bidirectional FIFO ....................................
1024 x 18-Bit -1 K x 9-Bit Bus Matching Bidirectional FIFO ....................................
512 x 18-Bit Parallel Bidirectional FIFO .....................................................................
1024 x 18-Bit Parallel Bidirectional FIFO ...................................................................
5.0
5.1
5.1
5.1
5.2
5.2
5.2
5.2
5.3
5.3
5.3
5.4
5.4
5.4
5.5
5.5
5.6
5.6
5.6
5.7
5.7
5.8
5.8
5.9
5.9
5.9
5.9
5.9
5.9
5.10
5.10
5.10
5.10
5.10
5.10
5.11
5.11
5.12
5.12
5.12
5.12
5.12
5.13
5.13
5.13
5.13
5.14
5.15
5.15
5.15
5.15
5.16
5.16
2
1992 FIFO TABLE OF CONTENTS (CONTINUED)
IDT72605
IDT72615
IDT7271
IDT7272
IDT7273
256 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ...........................
512 x 18-Bit Parallel Sync BiFIFOTM (Clocked Bidirectional FIFO) ...........................
512 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ..........................
1024 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ........................
2048 x 9-Bit Parallel Asynchronous Single-Bank Bidirectional FIFO ....... ~................
PAGE
5.17
5.17
5.18
5.18
5.18
SUBSYSTEMS PRODUCTS (Please refer to pages indicated in Section 7 of this book.)
FIFO MODULES
IDT7MP2009
IDT7MP2010
IDT7M208
IDT7M207
32K x 18 CMOS Parallel In-Out FIFO Module...........................................................
16K x 18 CMOS Parallel In-Out FIFO Module...........................................................
64K x 9 Parallel In-Out FIFO Module ........................................................................
32K x 9 Parallel In-Out FIFO Module ........................................................................
7.12
7.12
7.13
7.13
II
5.0
3
t;)
Integrated Device Technology, Inc.
CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO
256 x 9-BIT, 512 x 9-BIT, 1 K
IDT7200S/L
IDT7201SAlLA
IDT7202SAlLA
x 9-BIT
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201A)
• 1 K x 9 organization (IDT7202A)
• Low power consumption
- Active: 770mW (max.)
-Power-down: 27.5mW (max.)
• Ultra high speed-15ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin and functionally compatible with 720X family
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOSTM technology
• Military product compliant to MIL-STD-883, Class 8
• Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function.
The IDT7200/7201A17202A are dual-port memories that
load and empty data on a first-in/first-out basis. The devices
use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins. The
devices have a read/write cycle time of 25ns (40MHz).
The devices utilizes a 9-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT720017201A17202A are fabricated using IDT's
high-speed CEMOS technology. They are designed forthose
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class 8.
FUNCTIONAL BLOCK DIAGRAM
THREESTATE
A
BUFFERS
~
DATA. OUTP)UTS
(uo-Qa
1 - - - - 4 - - EE
L~~--.J--I--
Xi ----~L-_ _ _~-----l~
FURT
FF
XO/HF
2679 drw Ot
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
05C·2000/4
©t 992 Integrated Device Technology. Inc.
5.1
IDT720017201A17202A CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
256 x 9-BIT, 512 x 9-BIT & 1K x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
iN
28
Vee
08
2
27
04
03
3
26
05
02
4
25
06
02
5
29
01
5
24
07
01
6
28
07
Do
6
23
FURT
Do
7
27
NC
Xi
7
FF
8
00
9
01
10
02
03
08
GNO
P28-1,
C28-1,
028-1,
P28-2,
S028-3
&
S028-5
06
22
RS
Xi
8
21
EF
FF
9
20
XO/HF
00
10
24
EF
19
07
01
11
23
XO/HF
11
18
06
NC
12
22
07
12
17
05
02
13
21
06
13
16
04
14
15
R
J32-1
&
L32-1
26
FURT
25
RS
14 15 16 17 18 19 20
2679 drw02a
DIP/SOIC/FLATPACK
TOP VIEW
LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Terminal Voltage
with Respect
toGNO
RECOMMENDED DC OPERATING
CONDITIONS
Com'l.
Mil.
Unit
-0.5 to +7.0 -0.5 to +7.0
V
Min.
Typ.
Max.
Unit
VeeM
Military Supply
Voltage
4.5
5.0
5.5
V
Veee
Commercial Supply
Voltage
4.5
5.0
5.5
V
GNO
Supply Voltage
0
0
V
°C
VIH(l)
Input High Voltage
Commercial
2.0
-
-
V
mA
VIH(l)
Input High Voltage
Mlitary
2.2
-
-
V
2679 tbl 01
VIL(2)
Input Low Voltage
Commercial and
Military
-
-
0.8
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
NOTE:
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
oto +70
-55 to +125
°C
-55 to +125 -65 to +135
°C
-55 to +125 -65 to +155
Symbol
Tem~erature
lOUT
50
DC Output
Current
50
NOTE:
CAPACITANCE
Symbol
CIN
COUT
Parameter
0
2679tbl03
1. VIH = 2.6V for Xi input (commercial).
VIH = 2.8V for Xi input (military).
2. 1.SV undershoots are allowed for 10ns once per cycle.
(TA = +25°C, f = 1.0 MHz)
Parameter(1)
Condition
Max.
Unit
Input Capacitance
VIN = OV
8
pF
Output Capacitance
VOUT= OV
8
NOTE:
pF
2679tbl02
1. This parameter is sampled and not 100% tested.
5.1
2
IDT720017201A17202A CMOS PARALLEL FIRST·INfFIRST·OUT FIFO
256 X 9·BIT, 512 X 9·BIT & lK X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee
=
5.0V+1
- 0%, TA = O°C to +70°C; Military: Vee
=
5.0V+1
- 0%, TA = -55°C to +125°C)
IDT7200
IDT7201A
IDT7202A
Commercial
tA 15,20n8
IDT7200
IDT7201A
IDT7202A
Military
tA 20n8
=
IDT7200
IDT7201A
IDT7202A
Commercial
tA 25,35n8
=
=
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
-1
-
1
-10
10
-1
Output Leakage Current
-10
-
10
-10
10
-10
VOH
Output Logic "1" Voltage IOH = -2rnA
2.4
2.4
Output Logic "0" Voltage IOH = 8rnA
-
-
-
VOL
0.4
ICC1(3)
Active Power Supply Current
ICC2(3)
Standby Current (R=W=RS=FURT=VIH)
Icc3(L)(3)
Power Down Current (All Input = Vcc· 0.2V)
-
-
-
-
Icc3(S)(3)
Power Down Current (All Input = Vee· 0.2V)
Symbol
IU(1)
Input Leakage Current (Any Input)
ILO(2)
Parameter
125(4)
15
0.5
-
-
5
-
2.4
0.4
-
140(4)
-
20
0.9
9
Typ. Max. Unit
-
f.lA
f.lA
1
10
-
V
-
0.4
125(4)
-
5
V
rnA
15
rnA
0.5
rnA
rnA
2679tbl04
DC ELECTRICAL CHARACTERISTICS (Continued)
(Commercial: Vee
=
5.0V±1 0%, TA = O°C to +70°C; Military: Vee
=
5.0V±1 0%, TA = -55°C to +125°C)
IDT7200
IDT7201A
IDT7202A
Military
tA 30,40n8
IDT7200
IDT7201A
IDT7202A
Commercial
tA 50,65,80,120n8 tA
=
=
Symbol
.
Parameter
Min.
IU lll
Input Leakage Current (Any Input)
-10
ILO(~I
Output Leakage Current
-10
VOH
Output Logic "1" Voltage IOH = -2rnA
2.4
VOL
Output Logic "0" Voltage IOH = 8rnA
lec1\;j)
Active Power Supply Current
lec2\;J)
Standby Current (R=W=RS=FURT=VIH)
ICC3(L)\3)
Power Down Current (All Input = Vec· 0.2V)
ICC3(S)\3)
Power Down Current (All Input = Vcc • 0.2V)
,-
NOTES:
1. Measurements with 0.4 :> VIN :> Vee.
2. R VOUT:> Vee.
3. Icc measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
'
5.1
Typ.
Max.
Min.
-
10
-1
10
-10
-
Typ.
IDT7200
IDT7201A
IDT7202A
Military
50,65,80,120n8
=
Max.
Min.
1
-10
Typ. Max. Unit
-
2.4
-
-
2.4
-
-
V
0.4
-
-
0.4
-
-
0.4
V
140(4)
-
50
80
-
5
8
-
70'
20
0.9
-
-
0.5
5
9
10
-10
-
f.lA
f.lA
10
10
100
rnA
8
15
rnA
-
-
0.9
rnA
-
-
9
rnA
2679tbl05
3
IDT720017201A17202A CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
256 x 9-BIT, 512 x 9-BIT & 1K x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Commercial: VCC = 5.0V±1 0%, TA = O°C to +70°C; Military: Vcc = 5.0V±1 0%, TA = -55°C to + 125°C)
Commercial
Com'I&MiI.
Commercial
Military
Commercial
7200S/l20
7200SlL15
7200S/L25
7200SlL30
7200SlL35
7201SAlLA15 7201 SAlLA20 7201 SAlLA25 7201 SAlLA30 7201 SAlLA35
7202SAlLA15 7202SAlLA20 7202SAlLA25 7202SAlLA30 7202SAlLA35
Symbol
ts
Parameter
Shift Frequency
Min.
Max.
Min.
-
40
30
10
20
5
5
5
30
20
10
12
0
30
20
20
10
30
20
20
10
-
tRC
Read Cycle Time
25
-
tA
Access Time
-
15
tRR
Read Recovery Time
tRPW
Read Pulse Width(2)
tRLZ
Read Pulse Low to Data Bus at Low Z(3)
twLZ
Write Pulse High to Data Bus at Low Z(3,4)
tDV
Data Valid from Read Pulse High
10
15
5
5
5
-
tRHZ
Read Pulse High to Data Bus at High Z(3)
-
twc
Write Cycle Time
twpw
Write Pulse Width(2)
twR
Write Recovery Time
tDS
Data Set·up Time
tDH
Data Hold Time
tRSC
Reset Cycle Time
tRS
Reset Pulse Width(2)
tRSS
Reset Set-up Time(3)
tRSR
Reset Recovery Time
tRTC
Retransmit Cycle Time
tRT
Retransmit Pulse Width(2)
tATS
Retransmit Set-up Time(3)
tRTR
Retransmit Recovery Time
25
15
10
11
0
25
15
15
10
25
15
15
10
15
-
tEFL
Reset to Empty Flag Low
-
tHFH,FFH Reset to Half-Full and Full Flag High
-
-
-
-
-
25
25
25
15
15
tRTF
Retransmit Low to Flags Valid
tREF
Read Low to Empty Flag Low
tRFF
Read High to Full Flag High
tRPE
Read Pulse Width after EF High
twEF
Write High to Empty Flag High
twFF
Write Low to Full Flag Low
tWHF
Write Low to Half-Full Flag Low
-
tRHF
Read High to Half-Full Flag High
-
twPF
Write Pulse Width after FF High
15
txOL
ReadiWrite to XO Low
-
txOH
ReadiWrite to XO High
-
15
15
25
25
15
15
txl
XI Pulse Width(2)
txlR
XI Recovery Time
txlS
XI Set-up Time
15
10
10
-
15
-
-
-
-
20
-
Max.
Min.
Max.
33.3
20
-
35
28.5
25
-
-
-
10
25
5
5
5
15
-
-
35
25
10
15
0
35
18
-
-
-
-
25
25
10
35
25
25
10
30
30
-
30
20
20
25
-
-
-
-
-
-
-
-
-
Max.
Unit
22.2
MHz
45
-
ns
-
35
-
ns
-
30
-
-
10
35
5
10
5
20
-
ns
ns
ns
ns
-
ns
-
20
ns
-
ns
-
45
35
10
18
0
45
35
35
10
-
45
35
35
-
-
ns
ns
-
ns
ns
ns
-
ns
ns
ns
ns
-
ns
-
ns
45
45
ns
40
30
30
-
30
-
-
30
30
40
40
-
30
30
45
45
30
-
-
35
-
ns
30
-
35
ns
-
30
-
ns
30
10
10
-
35
10
10
35
-
ns
20
-
-
25
20
-
-
20
-
20
10
10
-
25
10
10
-
-
40
30
30
10
Min.
25
-
-
-
40
10
30
5
5
5
40
30
10
18
0
40
30
30
10
Max.
-
25
25
35
35
25
25
-
-
40
40
35
35
35
25
25
20
20
30
30
-
Min.
-
-
NOTES:
10
35
-
ns
ns
45
30
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2679 tbl 06
1. limings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.1
4
ID1720017201A17202A CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
256 X 9-BIT, 512 X 9·BIT & 1K x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Continued)
(Commercial: Vcc = 5.0V±10%, TA = O°C to +70°C; Military: Vcc = 5.0V±10%, TA=-55°C to +125°C)
Military
Commmercial and Military
7200SlL50
7200SlL65
7200S/L80
7200S/L120
7201 SAlLA40 7201SAlLA50 7201 SAlLA65 17201 SAlLA80 7201SAlLA120
7202SAlLA40 7202SAlLA50 7202SAlLA65 17202SAlLA80 7202SAlLA 120
7200S/L40
Max.
Min.
Max.
Min.
Max.
ts
Shift Frequency
-
20
-
15
-
12.5
tRC
Read Cycle lime
50
-
65
-
80
tA
Access lime
40
-
50
tRR
Read Recovery Time
10
15
-
tRPW
Read Pulse Width(2}
-
15
50
-
10
15
Symbol
Parameter
Min.
40
5
tRLZ
Read Pulse Low to Data Bus at Low Z(3}
twLZ
Write Pulse High to Data Bus at Low Z(3.4}
tDV
Data Valid from Read Pulse High
10
5
tRHZ
Read Pulse High to Data Bus at High Z(3}
-
twe
Write Cycle lime
twpw
5
50
25
-
65
Write Pulse Width(2}
40
-
50
twR
Write Recovery lime
10
-
15
lOS
Data Set-up lime
20
-
tDH
Data Hold Time
0
tRSC
Reset Cycle lime
50
-
tRS
Reset Pulse Width(2}
40
-
50
tRSS
Reset Set-up Time(3}
-
tRSR
Reset Recovery Time
40
10
tRTC
Retransmit Cycle lime
50
-
50
15
tRT
Retransmit Pulse Width(2}
40
-
50
tRTS
Retransmit Set-up Time(3}
40
50
tRTA
Retransmit Recovery lime
10
-
tEFL
Reset to Empty Flag Low
-
50
tHFH,FFH Reset to Half-Full and Full Flag High
-
50
50
30
Min.
Max.
Min.
Max.
Unit
-
10
7
MHz
-
100
-
140
-
ns
65
80
-
120
ns
-
20
20
65
-
80
120
10
-
10
10
-
ns
-
-
-
15
5
-
20
-
20
-
ns
-
5
-
5
-
ns
30
80
30
-
30
35
ns
100
ns
120
-
ns
20
80
-
120
-
80
20
120
20
-
ns
100
-
-
65
-
140
140
-
ns
ns.
15
-
20
30
-
30
40
5
-
10
65
-
80
-
65
15
65
80
10
40
10
140
ns
ns
ns
ns.
ns
ns
-
80
-
100
-
65
80
-
120
80
20
-
15
-
-
120
20
-
65
80
80
-
140
ns
100
-
140
ns
65
-
80
100
ns
60
60
ns
45
-
60
60
-
140
45
-
100
65
-
60
ns
-
65
15
65
ns
ns
ns
ns
tRTF
Retransmit Low to Flags Valid
tREF
Read Low to Empty Flag Low
-
tRFF
Read High to Full Flag High
-
35
-
tRPE
Read Pulse Width after EF High
40
-
50
-
65
-
80
-
120
-
ns
twEF
Write High to Empty Flag High
35
-
45
-
60
ns
35
45
-
60
60
ns
tWHF
Write Low to Half-Full Flag Low
65
-
80
-
100
140
ns
tRHF
Read High to
50
-
65
80
-
100
140
ns
twPF
Write Pulse Width after FF High
40
-
50
-
65
-
60
Write Low to Full Flag Low
-
60
twFF
-
-
80
-
120
-
ns
txOL
ReadlWrite to XO Low
-
40
-
50
-
65
-
80
120
ns
txOH
ReadlWrite to XO High
40
-
50
-
80
120
ns
XI Pulse Width(2}
-
50
-
-
80
-
120
-
ns
txlR
XI Recovery lime
-
10
-
10
-
ns
XI Set-up Time
-
-
txlS
10
15
65
10
15
65
txl
40
10
10
-
-
15
-
15
-
Ha~-Full
Flag High
50
-
60
60
NOTES:
ns
2679 tbl 07
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
5.1
5
IDT7200n201A17202A CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
256 X 9-BIT, 512 X 9-BIT & 1K X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
sv
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
UK
Sns
1.SV
1.SV
See Figure 1
TO
OUTPUT
PIN
2679tbl08
--+-----...
sson
30pF*
2679 drw03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
SIGNAL DESCRIPTIONS
the Data Outputs (Qo - Qs) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (EF) will go low,
allowing the "final" read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high aftertwEF and a valid
Read can then begin. When the FIFO is empty, the internal
read painter is blocked from Rso external changes in Rwill not
affect the FIFO when it is empty.
INPUTS:
DATA IN (Do - Os)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after FIRST LOAD/RETRANSMIT (FURT)
power up before a write operation can take place. Both the
This is a dual-purpose input. In the Depth Expansion Mode,
Read Enable (R) and Write Enable (W) inputs must be in . this pin is grounded to indicate that it is the first loaded (see
the high state during the window shown in Figure 2, (i.e., Operating Modes). In the Single Device Mode, this pin acts as
tRSS before the rising edge of RS) and should not change the restransmit input. The Single Device Mode is initiated by
until tRSR after the rising edge of RS. Half-Full Flag (HF) grounding the Expansion In (Xi).
will be reset to high after Reset (RS).
The IDT7200/7201A/7202A can be made to retransmit
data when the Retransmit Enable control (RT) input is pulsed
WRITE ENABLE (W)
low. A retransmit operation will set the internal read pointer to
A write cycle is initiated on the falling edge of this input if the the first location and will not affect the write pointer. Read
Full Flag (FF) is not set. Data set-up and hold times must be Enable (R) and Write Enable (W) must be in the high state
adhered to with respect to the rising edge of the Write Enable during retransmit. This feature is useful when less than 256/
(IN). Data is stored in the RAM array sequentially and 512/1024 writes are performed between resets. The retransindependently of anyon-going read operation.
mit feature is not compatible with the Depth Expansion Mode
After half of the memory is filled and at the falling edge of and will affect the Half-Full Flag (HF), depending on the
the next write operation, the Half-Full Flag (HF) will be set to relative locations of the read and write pointers.
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the EXPANSION IN (Xi)
total memory of the device. The Half-Full Flag (HF) is then
This input is a dual-purpose pin. Expansion In (Xi) is
reset by the rising edge of the read operation.
grounded to indicate an operation in the single device mode.
To prevent data overflow, the Full Flag (FF) will go low, Expansion In (Xi) is connected to Expansion Out (XO) of the
inhibiting further write operations. Upon the completion of a previous device in the Depth Expansion or Daisy Chain Mode.
valid read operation, the Full Flag (FF) will go high after tRFF,
allowing a valid write to begin. When the FIFO is full, the
OUTPUTS:
internal write pointer is blocked from W, so external changes
FULL FLAG (FF)
in Wwill not affect the FIFO when it is full.
The Full Flag (FF) will go low, inhibiting further write
operation, when the write pointer is one location less than the
READ ENABLE (R)
read pointer, indicating that the device is full. If the read
A read cycle is initiated on the falling edge of the Read
pointer is not moved after Reset (RS), the Full-Flag (FF) will go
Enable (R) provided the Empty Flag (EF) is not set. The data
low after 256 writes for IDT7200, 512 writes forthe IDT7201A
is accessed on a First-lniFirst-Out basis, independent of any
and 1024 writes for the IDT7202A.
ongoing write operations. After Read Enable (R) goes high,
5.1
6
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 X 9·8IT, 512 X 9·81T & 1K X 9·81T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EMPTY FLAG (EF)
The Empty Flag (EF) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (xi) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous device reaches the last location of memory.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode,
when Expansion In (Xi) is grounded, this output acts as an
indication of a half-full memory.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (HF) will be set low
and will remain set until the difference between the write
DATA OUTPUTS (00 - 08)
Data outputs for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
~--------------tRSC--------------------~~
~--------------tRS------------~~
2679 drw 04
NOTES:
Figure 2. Reset
1. EF, FF, HF may change status during Reset, but flags will be valid at tRse.
2. Wand R = VIH around the rising edge of RS.
Qo-Ol
_ FI-OII----- twpw -----J~w~_
Do-~
___-oJ/
- - - - - - - - ( ""--_ _ _ _ _- ' 1 - - - - - (
DATA IN VALID
)>-----2679 drw 05
Figure 3. Asynchronous Write and Read Operation
5.1
7
IDT7200n201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 x 9-BIT, 512 x 9·BIT & lK x 9·BIT
LAST WRITE
IGNORED
WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
tRFF
2679 drw06
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
EF
DATA OUT
-+----(
2679 drw 07
Figure 5. Empty Flag From Last Read to First Write
...................................-tRTC""'''''''''''''''''''''''''''''''''''''''''''''''''''~
...................................-tRT""'''''''''''''''''''''''''''''''~
~
~
W,R
FLAG VALID
2679 drw
as
Figure 6. Retransmit
5.1
8
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 X 9·BIT, 512 X 9·BIT & 1K X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
EF
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
w
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
w
....
HALF-FULL OR LESS
f4- t
RHF -
l-tWHF..=-1
\-
MORE THAN HALF-FULL
..,'HALF-FULL OR LESS
2678 drw 11
Figure 9. Half·Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
IXDL
f _____
r\
t_X_O_H
READ FROM
LAST PHYSICAL
LOCATION
tXOL(
2679 drw 12
Figure 10. Expansion Out
5.1
9
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 x 9·8IT, 512 x 9·81T & lK x 9·81T
14----
w
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t XI
t XIR
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
2679 drw 13
Figure 11. expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (Le. FF is monitored on the device
where Wis used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8:
Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IOT720017201 Al7202A may be used when the application requirements are for 256/512/1024 words or less.
The IOT7200/720 1Al7202A is in a Single Oevice Configuration when the Expansion In (Xi) control input is grounded (see
Figure 12).
Depth Expansion
The IOT72001720 1A/7202A can easily be adapted to applications when the requirements are for greater than 256/5121
1024 words. Figure 14 demonstrates Oepth Expansion using
three IOT720017201A17202As. Any depth can be attained by
adding additional IOT720017201A17202As. The IOT7200/
7201A17202A operates in the Oepth Expansion mode when
the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Oepth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status
flags (EF, FF and HF) can be detected from anyone device.
Figure 13 demonstrates an 18-bit word width by using two
IOT720017201A17202As. Any word width can be attained by
adding additional IOT720017201A17202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IOT720017201 Al7202As as shown
in Figure 16. Both Oepth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the
bus until the Rline is raised from low-to·high, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the Wline being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.1
10
EI
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 x 9·BIT, 512 x 9·BIT & 1K X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(H1=)
(HALF-FULL FLAG)
. . - - - - READ (R)
WRITE iYJ) - - - - . .
DATA OUT (0)
EMPTY FLAG (EF)
. . - - - - RETRANSMIT (Rl)
DATA IN (0)_-+-----,/1
FULL FLAG (FF) - 4 - - - - - f
r---.
RESET (RS) - - - - . .
EXPANSION IN (Xi)
2679 drw 14
Figure 12. Block Diagram of Single 256/51211024 X g AFO
OATAIN (0)
WRITE
fJii)
FULL FLAG
ffl
RESET (RS)
-------+---.....
lOT
..---+- - - - - - 72001
lOT
7201 AI
7202A
----~
72001
- - - - - - -+---.,.
7201 AI
7202A
-K----
READ (R)
1-------
EMPTY FLAG (EF)
......,~---
RETRANSMIT (Rl)
'---_ _ _ _ _ _ _ _- - ! - _ , /
OATAour(Q)
2679 drw 15
Figure 13. Block Diagram of 256/51211024 X 18 FIFO Memory Used In Width Expansion Mode
TABLE I-RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
Mode
Reset
Retransmit
ReadlWrite
AS
AT
0
X
1
0
~
0
0
1
1
0
Internal
Read Pointer
Location Zero
Location Zero
IncrementllJ
Status
Write Pointer
Location Zero
Unchanged
Incrementl1J
Outputs
EF
FF
0
1
1
X
X
X
X
X
X
FfF
NOTE:
2679tbl09
1. Pointer will increment if flag is High.
TABLE II-RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Mode
Reset First Device
Reset All Other Devices
ReadlWrite
AS
Fe
0
0
0
1
~
(1 )
(1)
1
X
(1 )
Internal Status
Read Pointer
Write Pointer
Location Zero
Location Zero
Location Zero
Location Zero
X
X
NOTE:·.
1.
Xi is connected to XC o.!£.revious device. See Figure 14.
Xi = Expansion Input, HF = Half-Full Rag Output
Outputs
EF
FF
0
0
1
X
X
1
2679tbll0
RS = Reset Input, FDRT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
5.1
11
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 x 9·BIT, 512 x 9·BIT & 1K x 9·BIT
w--------<~---::~
D _ _ _""'-9+-_ _---.--.---.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT
72001
7201 AI
7202A
~~--~--~---------R
EF
I----_+_----,
Q
~-.~+-------vcc
RS
----------~-I~
Xi
-
2679 drw 16
Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)
Ell
00-08
09-017
00-08
R,W,RS
09-017
IDT72001
IDT7201A1
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT72001
IDT7201A1
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT72001
IDT7201A1
IDT7202A
DEPTH
EXPANSION
BLOCK
D9 -D17
Do·D8
Do-DN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
D9 -DN
D18 -DN
D(N·8)-DN
D(N-8)-DN
2679 drw 17
Figure 15. Compound FIFO Expansion
NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
5.1
12
IDT720017201A17202A CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
256 x 9·BIT, 512 x 9·BIT & 1K X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RB
EFB
HFB
FFA
SYSTEM A
SYSTEM B
WB
FFB
2679 drw 18
Figure 16. Bidirectional FIFO Mode
DATA IN
w
R
EF
tWLZ
DATA OUT
2679 drw 19
Figure 17. Read Data Flow·Through Mode
w
FF
t DH
DATA IN
tA
DATA OUT
;;:;JJ
--------------~~ ~ATAOUTVALID ~~--------------------------2679 drw 20
Figure 18. Write Data Flow·Through Mode
5.1
13
t;)®
Integrated Device Technology, Inc.
CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO
2048 X 9-8IT, 4096 x 9-8IT,
8192 X 9-81T & 16384 X 9-81T
IDT7203
IDT7204
IDT720S
IDT7206
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
The IOT7203/7204/7205/7206 are dual-port memories buffers with internal pointers that load and empty data on a firstin/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of
the Write (Vii) and Read (R) pins. All FIFOs have a readlwrite
cycle time of 30ns (33MHz).
The devices 9-bit width provides a bit for a control or parity
at the user's option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position
when RT is pulsed low. A Half-Full Flag is available in the
single device and width expansion modes.
The IOT7203/7204/720517206 are fabricated using lOT's
high-speed CEMOS technology. They are designed for applications requiring asynchronous and simultaneous readlwrites
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STO-883, Class 8.
•
•
•
•
•
•
•
•
First-ln/First-Out dual-port memory
2048 x 9 organization (IOT7203)
4096 x 9 organization (IOT7204)
8192 x 9 organization (IOT7205)
16384 x 9 organization (IOT7206)
High-speed: 20ns access time
Low power consumption
- Active: 770mW (max.)
- Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
Pin and functionally compatible with IOT720X family
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CEMOSTM technology
Military product compliant to MIL-STO-883, Class 8
Standard Military Drawing for #5962-88669 (IOT7203),
5962-89567 (IOT7203), and 5962-89568 (IOT7204) are
listed on this function.
-------FUNCTIONAL BLOCK DIAGRAM
_
THREESTATE
A
BUFFERS
"""v/
DATAOUTPUTS
(00-08)
f-----,-+--- EE
~~~.....J---I-·FF
Xi - - - - - - L . . . . . - I_ _ _J----'~
XO/HF
FURT
2661 drw 21
CEMOS is a trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
APRIL 1992
DSC-2004l5
5.2
ID17203n204n205n206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 x 9·BIT, 4096 x 9·BIT, 8192 X 9·BIT & 16384 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IN
L.....IL.....I~II~L.....IL.....I
]5
05
03
02
01
Do
02
01 ]6
Do ]7
06
07
Xi
FURT
RS
EF
XO/HF
Q7
Q6
Qs
Q4
Xi
FF
Qo
Q1
Q2
Q3
Q8
8op-=~~~o
INDEX
Vcc
04
08
FF
Qo
01
NC
02
Rating
Commercial
C!l
2661
drw 20b
RECOMMENDED
DC OPERATING CONDITIONS
Military
Unit
-0.5 to + 7.0
-0.5 to +7.0
Operating
Temperature
o to +70
-55 to +125
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +155
°C
lOUT
DC Output
Current
50
50
mA
Symbol
V
GNO
TA
07
NC
26[ FURT
&
2S[ RS
]10
L32-1
24[ EF
]11
23 [ XO/HF
]12
22( 07
]13~ ~ ~ ~ ~ ~ ~1[ 06
PLCC/LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Terminal
Voltage with
Respect to
06
28[
oo~~O:do
DIP
TOP VIEW
Consult Factory for CERPACK Pinout
Symbol
:J ~ c;; g29[
J32-1
2661 drw 20a
VTERM
en '"
27 [
]8
]9
R
GNO
~
°C
NOTE:
2661 tbl01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Min.
Typ.
Max.
Unit
VeeM
Military Supply
Voltage
4.5
5.0
5.5
V
Veee
Commercial Supply
Voltage
4.5
5.0
5.5
V
GNO
Supply Voltage
VIH(I)
Input High Voltage
Commercial
2.0
-
-
V
VIH(I)
Input High Voltage
Military
2.2
-
-
V
VIL(2)
Input Low Voltage
Commercial and
Military
-
-
O.S
V
0
0
0
V
NOTES:
1. VIH = 2.6V for Xi input (commercial).
VIH = 2.SV for Xi input (military).
2. 1.SV undershoots are allowed for 10ns once per cycle.
2661 tbl02
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5.0V±1 0%, TA = O°C to +70°C; Military: Vcc = 5.0V±1 0%, TA = -55°C to +125°C)
IDT7203172041
IDT7205
Commercial
tA = 20ns
Symbol
Parameter
Min.
IU(I)
Input Leakage Current (Any Input)
-1
ILO(2)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage IOH = -2mA
2.4
VOL
Output Logic "0" Voltage IOH = SmA
lecl(3)
Active Power Supply Current
-
lec2(3)
Standby Current (R=W=RS=FURT=VIH)
Icc3(L)(3)
Power Down Current (All Input = Vee - 0.2V)
lec3(S)(3)
Power Down Current (All Input = Vee - 0.2V)
NOTES:
1. Measurements with 0.4 ~ VIN
2. R ---2661 drw 03
Figure 3. Asynchronous Write and Read Operation
5.2
6
1017203172041720517206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 X 9·8IT, 4096 X 9·blt, 8192 X 9·81T & 16384 X 9·81T
LAST WRITE
IGNORED
WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ
R
FF
2661 drw 04
Figure 4. Full FlagTlmlng From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
W
R
II
EF
DATA OUT
2661 drwOS
Figure 5. Empty Flag Timing From Last Read to First Write
~---------------tRTC----------------------~
~----------------tRT--------------~
VI,R
HF, EF, FF
FLAG VALID
2661 drw 06
NOTE:
1. 8=, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
5.2
7
IDT7203172041720517206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 x 9·BIT, 4096 x 9·BIT, 8192 x 9·BIT & 16384 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
EF
R
2661 drw 07
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
FF
w
ss SSSSSSSSSS~tWPF1"2661 drw 08
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
w
R
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
2661 drw 09
Figure 9. Half·Fuli Flag Timing
Vi
R
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
tXOL~
txo~___________t_XO~H~
XO
2661 drw 10
Figure 10. Expansion Out
5.2
8
1017203172041720517206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 X 9·BIT, 4096 X 9·bit, 8192 X 9·BIT & 16384 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
XI
w
READ FROM
FIRST PHYSICAL
LOCATION
2661 drw 11
Figure 11. Expansion In
OPERATING MODES:
USAGE MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8:
Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status
flags (EF, FF and HF) can be detected from anyone device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7203172041720S17206s. Any word width can be attained
by adding additional IDT7203/72041720S17206s (Figure 13).
Single Device Mode
A single IDT7203172041720S17206 may be used when the
application requirements are for 2048/4096/8192116384 words
or less. The IDT720317204/720S/7206 is in a Single Device
Configuration when the Expansion In (Xi) control input is
grounded (see Figure 12).
Depth Expansion
The IDT7203/7204/720S/7206 can easily be adapted to
applications when the requirements are for greater than 20481
4096/8192/16384 words. Figure 14 demonstrates Depth Expansion using three IDT7203/72041720S17206s. Any depth
can be attained by adding additional IDT7203172041720S1
7206s. The IDT7203/7204/720S17206 operates in the Depth
Expansion mode when the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 14.
S. The Retransmit (RT) function and Half·Fuli Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7203/7204/7205/7206s as
shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the
bus until the R line is raised from low-to-high, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge ofW, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
FIFOs or FIFO Modules.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.2
9
EI
IDT7203172041720517206 CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
2048 x 9-BIT, 4096 x 9-BIT, 8192 x 9-BIT & 16384 x 9-BIT
(HALF-FULL FLAG)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HF)
WRITE { f i i ) - - -...
. . . - - - - READ (R)
DATA OUT (0)
EMPTY FLAG (EF)
. . . - - - - RETRANSMIT (Rl)
DATA IN (0)--1-_,/
FULL FLAG (FF) .----1
RESET (RS) - - -..
1-----..
EXPANSION IN (Xi)
2661 drw 12
Figure 12. Block Diagram of 2048
x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used In Single Device Mode
HF
DATAIN (D)
WRITE{fii)
------
FULL FLAG (FF)
RESET (RS)
------
lOT
7203/
7204/
7205/
7206
lOT
7203/
72041
7205/
7206
------
------
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (Rl)
'--_ _ _ _ _ _ _ _-f-_,/DATAOUT(O)
2661 drw 13
NOTE:
1. Flag detection is accomplished by monitoring the FF,
Do not connect any output signals together.
EF and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used In Width Expansion Mode
5.2
10
IDT7203172041720517206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 X 9·BIT, 4096 X 9·blt, 8192 X 9·BIT & 16384 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
Internal Status
Inputs
Outputs
AS
R'f
Xi
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment (1)
Increment(1)
X
X
X
Mode
Hf:
NOTE:
1. Pointer will Increment if flag is high.
2661 tbl07
TABLE 11- RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Outputs
Internal Status
Inputs
AS
]:[
~
Read Pointer
Write Pointer
"EF
"FF
Reset First Device
0
0
(1 )
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
ReadlWrite
1
X
(1 )
X
X
X
X
Mode
NOTES:
1. Xi is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FURT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
2661 tbI 08
Xi = Expansion Input, HF = Half-Full Flag Output
II
I-ot----~~__I-----R
w--------------.-----~~
Q
D -------=9'-f------r--r-.
1-+........+-1-----------
Vee
RS----------------~~~
2661 drw 14
Figure 14. Block Diagram of 6149 X 9/12298 X 9/24596 X 9/49152 X 9 FIFO Memory (Depth Expansion)
5.2
11
IDTI203172041720517206 CMOS PARALLEL FIRST·IN/FIRST·OUT FIFO
2048 X 9·BIT, 4096 X 9·BIT, 8192 X 9·BIT & 16384 X 9·BIT
R,W,RS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Oo-oa
09-017
Oo-oa
09-017
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
BLOCK
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
BLOCK
BLOCK
Do -Da
D(N-a)-DN
09 -017
DO-ON __________________________________________
09 -ON
D1a
-ON
D(N-B)-DN
2661 drw 15
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
Rs
EFs
HFs
SYSTEM A
SYSTEM S
Ws
FFs
2661 drw 16
Figure 16. Bidirectional FIFO Operation
DATAIN
~____________________________________________________
w
tRPE
R
EF
twLZ
DATAoUT--------------------------~
2661 drw 17
Figure 17. Read Data Flow·Through Mode
5.2
12
1017203172041720517206 CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO
2048 x 9-BIT, 4096 X 9-bit, 8192 X 9-BIT & 16384 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R
FF
DATAIN
------------~----------------------------,
tA=;j
OO\
DATAOUT-------.....
DATA OUT VALID
)00--------2661 drw 18
Figure 18. Write Data Flow-Through Mode
5.2
13
(;)
Integrated Device Technology, Inc.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins. The
devices have a read/write cycle time of 25ns (40MHz).
The device utili,zes an 18-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features two OE pins for bus matching
applications. In single device mode, these pins can be used to
read data at different time intervals.
These FIFOs have two end point flags, Empty (EF) and Full
(FF); and two partial flags with fixed offsets, Almost Full (AFF)
and Almost Empty (AEF) for higher memory utilization. All
flags are active Low outputs.
The IDT72005172015/72025 are fabricated using IDT's
high-speed CEMOS technology. They are designed forthose
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
ADVANCE
INFORMATION
IDT72005
IDT72015
IDT72025
CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO
256 x 18-BIT, 512 x 18-BIT &
1K X 18-BIT
First-In/First-Out dual-port memory
256 x 18 organization (IDT72005)
512 x 18 organization (IDT72015)
1K x 18 organization (IDT72025)
High speed-25ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Status Flags: Empty, Full, Almost Full, Almost Empty
Two OE pins for bus matching applications
High-performance CEMOSTM technology
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72005/72015/72025 are dual-port memories that
load and empty data on a first-in/first-out basis. The devices
use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
FUNCTIONAL BLOCK DIAGRAM
OATAINPUTS
(00-017)
w
THREESTATE
BUFFERS
•
{)-
OE1
OATA OUTPUTS
(00-O17)
R
FF
AFF
AEF
EF
~ --------~~
______-t------.
RS
FL/(OE2}
XO
2553 drw 01
CEMOS is a trademari< of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC ·2049/1
<01992 Integrated Device Technology, Inc.
5.3
1
t;)
IDT72021
IDT72031
IDT72041
CMOS PARALLEL
FLAGGED FIFO WITH OE
1K x 9, 2K x 9, 4K x 9
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory
• Bit organization
- IDT72021-1 K x 9
- IDT72031-2K x 9
- IDT72041-4K x 9
• Ultra high speed
- IDT72021-25ns access time, 35ns cycle time
- IDT72031-35ns access time, 45ns cycle time
- IDT72041-35ns access time, 45ns cycle time
• Easily expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Function~ equivalent to IDT7202/03/04 with Ou~
Enable (OE) and Almost Empty/Almost Full Flag (AEF)
• Four status flags: Full, Empty, Half-Full (single device
mode), and Almost Empty/Almost Full (7/8 empty or 7/8
full in single device mode)
• Output Enable controls the data output port
• Auto-retransmit capability
Available in 32-pin DIP and surface mount 32-pin LCC
and PLCC
• Military product compliant to MIL-STD-883, Class B
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs (First-In/FirstOut). Data can be written into and read from the memory at
independent rates. The order of information stored and
extracted does not change, but the rate of data entering the
FIFO might be different than the rate leaving the FIFO. Unlike
a static RAM, no address information is required because the
read and write pointers advance sequentially. The IDT72021 /
031/041 s can perform asynchronous and simultaneous read
and write operations. There are four status flags, (HF, FF, EF,
AEF) to monitor data overflow and underflow. Output Enable
(OE) is provided to control the flow of data thr~gh the outQ..Ut
port. Additional key features are Write (W), Read (R),
Retransmit (RTUirst Load (FL), Expansion In (XI) and
Expansion Out (XO). The IDT72021/031/041s are designed
for those~plications requiring data control flags and Output
Enable (OE) in multiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using IDT's
Military grade product is
CEMOSlM technology.
manufactured in compliance with the latest version of
MIL-STD-883, Class B, for high reliability systems.
FUNCTIONAL BLOCK DIAGRAM
DATA OUTPUTS
(Oo-Oa)
w
r--t-t-----OE
THREESTATE
BUFFERS
DATA OUTPUTS
(Oo-Oa)
.---------------~EF
~======~~------------~FF
~--------------~AEF
Xi - - - - - - - + iL -_ _ _....I----------------------------XO/HF
2677 drw 01
CEMOS is a trademark of Integrated Devioe Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·2003/4
©1992 Integrated Devioe Technology, Inc.
5.4
10172021,10172031,10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K
x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vee
Vee
W
INDEX
D4
D5
D6
D7
Da
D3
D2
D1
FURT
RS
OE
EF
XO/HF
50
Xi
AEF
FF
07
06
00
01
02
03
05
04
ao~~,a:
R
Oa
GND
2677 drw 03
LCC/PLCC
TOP VIEW
GND
DIP
TOP VIEW
aa
CJCJ
2677 drw02
PIN DESCRIPTIONS
Symbol
Name
I/O
Do-Da
Inputs
I
Data inputs for 9-bit wide data.
RS
Reset
I
When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM
array. HF and F~o hig~ and AEF and EF go low. A reset is required before an initial WRITE
after power-up. Rand W must be high during RS cycle.
W
Write
I
When WRITEis low, data can be written into the RAM array sequentially, independent of READ.
In order for WRITE to be active, FF must be high. When the FIFO is full (FF-Iow), the internal
WRITE operation is blocked.
R
Read
I
When READ is low, data can be read from the RAM array sequentially, ind~ndent of WRITE.
In orderfor READ to be active, EF must be high. When the FIFO is empty (EF-Iow), the internal
READ operation is blocked.:....Ibe three-state output buffer is controlled by the read signal and
the external output control (OE).
FURT
First Load/
Retransmit
I
This is a dual ~rpose input. In the single device configuration (XI grounded), activating
retransmit (FURT-Iow) w~ set t~ internal READ pointer to the first location. There is no effect
on the WRITE pointer. Rand W must be high before setting FURT low. Retransmit is not
compatible with depth expansion. In the depth expansion configuration, FURT-Iow indicates
the first activated device.
XI
Expansion In
I
!!!.the single device configuration, XI is grounded. In depth expansion or daisy chain expansion,
OE
Output Enable
I
When OE is set high, the data flow through the three-state output buffer is inhibited regardless
of an active READ operation. A read operation does increment the read pointer in this situation.
When OE is set low, Oo-Oa are still in a high impedance condition if no READ occurs. For a
complete READ operation with data ppearing on Oo-Oa, both Rand OE should be asserted low.
FF
Full Flag
0
When FF goes low, the device is full and further WRITE operations are inhibited. When FF is
high, the device is not full.
EF
Empty Flag
0
When EF goes low, the device is empty and further READ operations are inhibited. When EF
is high, the device is not empty.
AEF
Almost-Emptyl
Almost-Full Flag
0
When AEF is low, the device is empty to 1/8 full or 7/8 to completely full. When AEF is high,
the device is greater than 1/8 full, but less than 7/8 full.
XO/HF
Expansion Out!
Half-Full Flag
0
This is a dual purpose output. In the single device configuration (XI grounded), the device ~
more than half full when H F is low. In the dee!.h expansion configuration (XO connected to XI
ofthe next device), a pulse is sentfrom XO to XI when the last location in the RAM array is filled.
Oo--Oa
Outputs
0
Data outputs for 9-bit wide data.
Description
XI is connected to XO (expansion out) of the previous device.
2677tb101
5.4
2
10172021, 10172031, 10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARVAND COMMERCIAL TEMPERATURE RANGES
STATUS FLAG
CAPACITANCE
Number of Words in FIFO
Symbol
1K
2K
4K
FF
AEF
HF
EF
0
0
0
H
L
H
L
1-127
1-255
1-511
H
L
H
H
128-512
256-1024
512-2048
H
H
H
H
513-896
1025-1792
2049-3584
H
H
L
H
897-1023
1793·2047
3585-4095
H
L
L
H
1024
2048
4096
L
L
L
H
CIN
COUT
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
Storage
Temperature
TSTG
lOUT
DC Output
Current
Mil.
Unit
Com'l.
-0.5 to +7.0 -0.5 to +7.0 V
o to +70
-55 to +125
°C
-55 to +125 -65 to +135
°C
-55 to +125 -65 to +155
°C
50
50
Unit
pF
Output Capacitance
VOUT = OV
10
10
pF
2677tb103
Parameter
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vccc
Commercial
Supply Voltage
4.5
5.0
5.5
V
ABSOLUTE MAXIMUM RATINGS(1)
RatinJl
Terminal Voltage
with Respect
toGND
Max.
VIN = OV
RECOMMENDED DC
OPERATING. CONDITIONS
Symbol
VTERM
Condition
Input Capacitance
NOTE:
1. These parameters are sampled and not 100% tested.
2677tb1102
Symbol
(TA = +25°C, f = 1.0 MHz)
Parameter(1)
rnA
0
0
0
GND
Supply Voltage
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL(1)
Input Low Voltage
Commercial and
Military
-
-
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 1Dns once per cycle.
V
2677tb105
NOTE:
2677 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
5.4
3
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K X 9, 2K X 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS -10172021
(Commercial: Vcc = S.OV±1 0%, TA = O°C to +70°C; Military: Vee = SV±1 0%, TA = -5SoC to +125°C)
10T72021
Commercial
tA::25,35ns
10T72021
Military
tA::30,40ns
10T72021
Commercial
tA=50,65,80,12Ons
10T72021
Military
tA:50,65,80,120ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Input Leakage Current
(Any Input)
-1
-
1
-10
-
10
-1
-
1
-10
-
10
~
ILd 2)
Output Leakage Current
-10
-
10
-10
-10
-10
-
-
2.4
-
2.4
-
2.4
-
10
2.4
-
10
Output Logic "1" Voltage
IOH=-2mA
-
10
VOH
-
~
V
VOL
Output Logic "0" Voltage
IOL=8mA
-
-
0.4
-
-
0.4
-
-
0.4
-
-
0.4
V
ICC1(3,4)
Active Power Supply
Current
-
-
120
-
-
140
-
50
80
-
70
100
mA
ICC2(3)
~and..Ey Curre~_
(R = W = RS = FURT = VIH)
-
-
12
-
-
20
-
5
8
-
8
15
mA
ICC3(3)
Power Down Current
(All input = Vcc-0.2V)
-
-
500
-
-
900
-
-
500
-
Symbol
IU(1)
Parameter
Typ. Max. Unit
-
~
900
2677tb106
OC ELECTRICAL CHARACTERISTICS -IOT72031, IOT72041
(Commercial: Vee = S.OV±10%, TA = O°C to +70°C; Military: Vee= SV±10%, TA=-55°C to +125°G)
IOTI2031
10T72031
IOTI2041
IOTI2041
Commercial
Military
tA =35,50,65,80,120ns tA =40,50,65,80,120ns
Symbol
IU(1)
Min.
Typ.
Max.
Min.
input Leakage Current (Any Input)
-1
1
-10
ILO(2)
Output Leakage Current
-10
10
-10
VOH
Output Logic "1" Voltage lOUT = -2mA
2.4
-
2.4
VOL
ICC1(3,5)
Output Logic "0" Voltage lOUT = 8mA
0.4
Active Power Supply Current
75
120
ICC2(3)
Standby Current (R = W = RST = FURT = VI H)
8
12
ICC3(3)
Power Down Current (All Input = Vcc - 0.2V)
-
-
-
2
-
Parameter
NOTES:
1.
2.
3.
4.
5.
Typ. Max. Unit
-
0.4
V
100
150
mA
12
25
mA
-
4
10
~
10
~
V
-
mA
2677tb107
Measurements with 0.4::;; VIN ::;; Vee.
R2: VIH, 0.4::;; VOIJT::;; Vee.
Icc measurements are made with OE = HIGH.
Tested at f = 2OMHz.
Tested at f = 15.3 MHz.
5.4
4
10172021,10172031,10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K X 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS -IOT72021(1)
(Commercial: Vcc
=
S.OV±10%. TA = O°C to +70°C; Military: Vcc = SV±10%. TA = -SsoC to +12S°C)
Symbol
Mil.
Com'l
Mil.
72021 x 30
72021 x 35
72021 x40
Min.
Max.
Max.
Min.
Max.
Min.
Max.
Unit
Shift Frequency
-
28.5
-
25
-
22.2
-
20
MHz
tRC
R Cycle Time
35
-
40
-
45
-
50
-
ns
tA
Access Time
-
25
-
30
-
35
-
40
ns
tRR
R Recovery Time
R Pulse Width(2)
10:
-
10
35
5
5
5
-
10
40
5
5
5
ns
-
-
-
25
5
5
5
10
30
5
5
5
-
ns
-'
ns
-
ns
fs
tRPW
Parameter
Com'l
72021 x 25
tRLZ
R Pulse Low to Data Bus at Low Z(3)
tWLZ
W Pulse High to Data Bus at Low Z(3.4)
tDV
Data Valid from R Pulse High
-
Min.
-
-
-
ns
tRHZ
R Pulse High to Data Bus at High Z(3)
-
18
-
20
-
20
-
25
ns
twc
-
W Recovery Time
Data Set-up Time
Data Hold Time
RS Cycle Time
RS Pulse Width(2)
50
40
10
20
0
50
40
40
10
50
40
10
-
tRSC
45
35
10
18
0
45
35
35
10
45
35
10
ns
tDH
-
-
tDS
40
30
10
18
0
40·
30
30
10
40
30
10
ns
tWR
35
25
10
15
0
35
25
25
10
35
25
10
-
twpw
W Cycle Time
W Pulse Width(2)
-
35
35
25
25
-
-
-
40
40
30
30
-
-
tRS
tRSS
RS Set-up Time
tRSR
RS Recovery Time
tRTC
RT Cycle Time
tRT
RT Pulse Width(2)
tRTR
RT Recovery Time
tRSFl
RS to EF and AEF Low
tRSF2
RS to HF and FF High
tREF
R Low to EF Low
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
-
ns
ns
ns
ns
-.
ns
-
ns
-
ns
ns
-
-
45
45
30
30
-
50
50
35
35
35
-
40
-
ns
-
ns
tRFF
R High to FF High
-
tRPE
R Pulse Width After EF High
25
-
30
tWEF
W High to EF High
-
W Low to EF Low
-
tWHF
W Low to HF Low
-
-
30
30
40
40
-
30
30
45
45
-
35
35
50
50
ns
tWFF
ns
ns
tRHF
R High to HF High
-
25
25
35
35
tWPF
W Pulse Width after FF High
25
-
30
-
35
-
40
-
ns
tRF
R High to Transitioning AEF
-
tOEHZ
tOELZ
OE Low to Low-Z (Enable)(3)
0
0
tAOE
OE Low Data Valid (00-08)
-
45
45
17
17
20
50
50
20
20
25
ns
-
40
40
15
15
18
-
W Low to Transitioning AEF
OE High to High-Z (Disable)(3)
-
-
tWF
35
35
12
12
15
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
0
0
-
0
0
-
0
0
-
ns
ns
ns
ns
ns
ns
ns
2677lb108
5.4
5
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K
x 9, 4K X 9
AC ELECTRICAL CHARACTERISTICS -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT72021 (1) (Continued)
(Commercial: Vcc = S.OV±1 0%, TA = O°C to +70°C; Military: Vcc = SV+1
- 0%, TA = -SsoC to +12S°C)
Military and Commercial
72021 x 50
Symbol
fs
Parameter
Shift Frequency
Min.
Max.
-
15
72021 x65
Min.
-
Max.
12.5
72021 x 80
Min.
Max.
72021 x 120
Min.
-
'10
-
Max.
Unit
7
MHz
tRC
R Cycle Time
65
-
80
-
100
-
140
-
ns
tA
Access Time
-
50
-
65
-
80
-
120
ns
tRR
R Recovery Time
15
120
tRLZ
R Pulse Low to Data Bus at Low Z(3)
10
10
tWLZ
W Pulse High to Data Bus at Low Z(3,4)
5
5
-
5
5
-
ns
80
-
20
50
-
20
R Pulse Width(2)
tov
Data Valid from R Pulse High
5
-
15
tRPW
5
-
5
5
-
ns
tRHZ
R Pulse High to Data Bus at High Z(3)
-
30
-
30
twc
W Cycle Time
65
80
twpw
W Pulse Width(2)
50
tWR
W Recovery Time
15
tos
Data Set-up Time
30
tOH
Data Hold Time
5
tRSC
RS Cycle Time
65
65
10
-
30
-
35
ns
100
-
ns
120
ns
140
-
65
-
80
-
140
80
-
120
-
ns
65
-
80
-
120
-
ns
20
-
20
-
ns
tRT
RT Pulse Width(2)
50
-
tRTR
RT Recovery Time
15
-
15
tRSF1
RS to EF and AEF Low
65
RS to HF and FF High
tREF
R Low to EF Low
tRFF
R High to FF High
45
-
80
tRSF2
-
tRPE
R Pulse Width After EF High
50
-
tWEF
W High to EF High
tWFF
W Low to EF Low
-
tWHF
W Low to HF Low
tRS
RS Pulse Width(2)
50
tRSS
RS Set-up Time
50
tRSR
RS Recovery Time
15
tRTC
RT Cycle Time
65
ns
-
65
15
30
10
15
80
65
10
80
20
40
10
100
100
80
20
20
40
10
140
ns
ns
ns
ns
ns
ns
ns
-
ns
140
ns
140
ns
60
-
60
ns
120
20
ns
100
60
-
60
-
60
ns
65
-
80
-
120
-
ns
45
-
60
60
ns
-
60
60
ns
-
65
-
80
-
100
140
ns
tRHF
R High to HF High
-
65
-
80
-
100
-
60
45
-
140
ns
tWPF
W Pulse Width after FF High
50
-
65
-
80
-
120
-
ns
tRF
R High to Transitioning AEF
-
65
80
-
140
ns
W Low to Transitioning AEF
-
65
-
100
tWF
-
100
-
140
ns
tOEHZ
DE High to High-Z (Disable)(3)
0
25
0
30
0
30
0
30
ns
tOELZ
DE Low to Low~Z (Enable)(3)
0
25
0
30
0
30
0
30
ns
tAOE
DE Low Data Valid (00-08)
-
30
-
40
-
40
-
40
65
45
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
80
60
80
100
60
ns
2677tb109
5.4
6
10172021,10172031,10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K
X
9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS -IOT72031, IOT72041(1)
(Commercial: vcc = S.OV±1 0%, TA = O°C to +70°C; Military: vcc = SV±1 0%, TA = -SsoC to +12S°C)
72031 x 35
72041 x 35
Symbol
72031 x 50
72041 x 50
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Shift Frequency
-
22.2
-
20
-
15
MHz
tRC
R Cycle Time
45
-
50
-
tA
Access Time
-
35
-
tRR
R Recovery Time
R Pulse Width(2)
10
35
5
5
5
-
10
40
5
5
5
40
-
65
15
50
10
5
5
fs
tRPW
Parameter
72031 x 40
72041 x40
tRLZ
R Pulse Low to Data Bus at Low Z(3)
tWLZ
W Pulse High to Data Bus at Low Z(3.4)
tDV
Data Valid from R Pulse High
-
-
-
tRHZ
R Pulse High to Data Bus at High Z(3)
-
20
-
25
-
twc
W Cycle Time
twpw
W Pulse Width(2)
tWR
W Recovery Time
tDS
Data Set-up Time
Data Hold Time
-
tRSC
RS Cycle Time
65
50
15
30
5
65
tRS
RS Pulse Width(2)
-
50
40
10
20
0
50
40
40
10
50
40
10
-
tDH
45
35
10
18
0
45
35
35
10
45
35
10
45
45
30
30
-
50
50
35
35
-
40
-
-
tRSS
RS Set-up Time
tRSR
RS Recovery Time
tRTC
RT Cycle Time
tRT
RT Pulse Width(2)
tRTR
RT Recovery Time
tRSF1
RS to EF and AEF Low
tRSF2
RS to HF and FF High
tREF
R Low to EF Low
-
tRFF
R High to FF High
-
tRPE
R Pulse Width After EF High
35
-
tWEF
W High to EF High
-
tWFF
W Low to EF Low
-
tWHF
W Low to HF Low
-
-
-
-
50
50
15
65
50
15
-
ns
50
ns
-
ns
-
ns
ns
-
ns
30
ns
-
ns
-
ns
ns
-
ns
ns
ns
ns
ns
-
ns
-
ns
ns
-
65
65
45
45
50
-
ns
-
ns
-
45
45
65
65
ns
ns
ns
ns
ns
ns
tRHF
R High to HF High
-
30
30
45
45
-
35
35
50
50
tWPF
W Pulse Width after FF High
35
-
40
-
50
-
ns
tRF
R High to Transitioning AEF
-
45
45
17
17
20
-
50
50
20
20
25
-
ns
0
0
65
65
25
25
-
30
tWF
W Low to Transitioning AEF
tOEHZ
DE High to High-Z (Disable)(3)
tOELZ
DE Low to Low-Z (Enable)(3)
tAOE
DE Low Data Valid (00--08)
0
0
-
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
-
0
0
-
-
ns
ns
ns
ns
ns
ns
ns
2677tbll0
5.4
7
II
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K X 9, 2K X 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS -IOT72031, IOT72041 (1) (Continued)
(Commercial: Vcc = S.OV±1 0%, TA = O°C to +70°C; Military: Vcc = SV+10%,
TA = -SsoC to +12S°C)
72031 x65
72041 x 65
Symbol
Parameter
Min.
Max.
Shift Frequency
-
12.5
tRC
R Cycle Time
80
-
tA
Access Time
-
65
tRR
tRPW
R Recovery Time
R Pulse Width(2)
tRLZ
R Pulse Low to Data Bus at Low Z(3)
-
tWLZ
W Pulse High to Data Bus at Low Z(3,4)
tov
Data Valid from R Pulse High
15
65
10
5
5
tRHZ
R Pulse High to Data Bus at High Z(3)
twc
twpw
W Cycle Time
W Pulse Width(2)
tWR
W Recovery Time
tos
Data Set-up Time
tOH
Data Hold Time
tRSC
RS Cycle Time
tRS
RS Pulse Width(2)
tRSS
RS Set-up Time
tRSR
RS Recovery Time
tRTC
RT Cycle Time
tRT
RT Pulse Width(2)
tRTR
RT Recovery Time
tRSFI
RS to EF and AEF Low
tRSF2
RS to HF and FF High
tREF
R Low to EF Low
tRFF
72031 x 80
72041 x80
Max.
Min.
Max.
Unit
10
-
7
MHz
100
-
140
-
ns
-
80
-
120
ns
-
-
ns
-
20
120
10
-
20
80
10
5
5
5
5
,-
ns
-
ns
-
30
-
30
-
35
ns
80
65
15
30
10
80
-
100
80
20
40
10
100
-
140
120
20
40
10
140
-
ns
-
ns
-
ns
-
ns
-
120
120
20
140
120
20
-
ns
-
ns
-
80
80
20
100
80
20
ns
80
80
60
60
-
100
ns
100
60
60
-
140
140
60
60
ns
R High to FF High
-
tRPE
R Pulse Width After EF High
65
-
80
-
. 120
-
ns
tWEF
W High to EF High
W Low to EF Low
-
-
tWHF
W Low to HF Low
R High to HF High
-
60
60
100
100
-
tRHF
-
60
60
80
80
-
60
60
140
140
ns
tWFF
tWPF
W Pulse Width after FF High
65
-
80
-
120
-
ns
tRF
R High to Transitioning AEF
tWF
W Low to Transitioning AEF
-
-
OE High to High-Z (Disable)(3)
a
tOELZ
OE Low to Low-Z (Enable)(3)
0
0
100
100
30
30
-
tOEHZ
80
80
30
30
0
140
140
30
30
lAOE
OE Low Data Valid (00-08)
-
40
-
40
-
40
fs
65
65
15
80
65
15
NOTES:
-
-
-
Min.
72031 x 120
72041 x 120
-
a
-
-
-
a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2677tbl11
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.4
8
10172021,10172031,10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
GND to 3.0V
Sns
UK
1.SV
1.SV
See Figure 1
TO
OUTPUT -.------+
PIN
30pF*
680n
2677tbl 12
2677 drw 04
or equivalent circuit
Figure 1. Output Load
• Includes scope and jig capacitances.
~--------------------tRSC----------------------------~
~--------------------
t RS
II
HF, FF
2677drw 05
Figure 2. Reset
NOTES:
1. EF, FF, HF, and AEF may change status during Reset, but flags will be valid at tRSC.
2. Wand R c VIH around the rising edge of RS.
Qo-Qa
____ F~~------twpw --------~--W~_
Do -Da
___---II
--------------~~______________ ~----~(~___D_A_T_A_I_N_V_A_L_ID___J)r----------2677drw 06
Figure 3. Asynchronous Write and Read Operation
NOTE:
1. Assume DE is asserted low.
5.4
9
10172021,10172031,10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K X 9, 4K X 9
LAST WRITE
IGNORED
WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
W
tRFF
2677 drw 07
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
DATA OUT (1,;.,)~I------<
2677 drw 08
Figure 5. Empty Flag From Last Read to First Write
NOTE:
1. Assume OE is asserted low.
~-----------------tRTC------------------------~
~-----------------tRT ----------------~
W,R
AEF~F,EF,FF
FLAG VALID
2677 drw09
Figure 6. Retransmit
5.4
10
10T72021, 10T72031, 10T72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
2677 drw 10
Figure 7. Empty Flag Timing
\'-----1.RFF
w
f
\\\\\\\\\\\\\\\\\\\\\\\\\\\S\\\\stt
WPF
) 2677 drw 11
Figure 8. Full Flag Timing
~r-
w
1\
R
,,"::
~tWHF'"
HALF-FULL
tRHF
HALF-FULL (1/2)
(1/2)
~\I\.
I
4-tRF __
I+--- tWF ---.
7/8 FULL
,l
HALF-FULL + 1
7/8 FULL
ALMOST-FULL (7/8 FULL + 1)
AEF
ALMOST-EMPTY
(1/8 FULL-1)
(1/8 FULL)
ALMOST-EMPTY (1/8 FULL-1)
2677 drw 12
Figure 9. Almost-Empty/Almost-Full Flag and Half-Full Timings
1~"
__-----------------------tRC----------------------------------__~1
tOEHZ
00-8
HIGH IMPEDANCE
DATA
Figure 10. Output Enable and Read Operation Timings
5.4
11
10T72021, 10172031, 10172041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
,xa"
'XOL {
f
,xalf
u
,xa"
f
2677drw 14
Figure 11. Expansion Out
t XI
t XIS
t XIR
1____
~
FIRST
PHYSICAL
W_R_IT_E_TO
_ _ _. . ..I / , - - - - 4
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
Figure 12. Expansion In
2677 drw 15
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
The IDT72021/031/041 is in the Single Device
Configuration when the Expansion In (XI) control input is
grounded (see Figure 13).
(HALF-FULL FLAG)
WRITE
RF ill
(IN)
READ (R)
DATA IN (D)
lOT
FULL FLAG (FF) ~----f 72021/031/041
RESET (RS)
1-----
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
L_"""'T"""_--14----- OUTPUT ENABLE (OE)
EXPANSION IN (XI)
2677 drw 16
Figure 13. Block Diagram of Single 1K12K14K x 9 FIFO
5.4
12
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K X 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the
corresQQ.nding.i.QQut control signals of multiple devices. Status
flags (EF, FF, HF, and AEF) can be detected from anyone
device. Figure 14 demonstrates an 18-bitwordwidth by using
two IDT72021/031/041 devices. Any word width can be
attained by adding additional IDT72021/031 /041 s.
AEF
HF
DATA IN (D) -1-_+-'/1
------~---t~---- OUTPUT ENABLE (OE)
WRITE (W) - - - + f - - - - - - - -f--___t+_ - - - - - IDT
IDT
~--- READ (Fh
FULL FLAG (FF) ~---i 72021/031/041
72021/031/041
1----.. EMPTY FLAG (EF)
RESET (RS) - - - - . . - - - - - - - -+---~ - - - - - 1 4 - = - - - - RETRANSMIT (RT)
DATA OUT (Q)
2677drw 17
Figure 14. Block Diagram of 1K12K14K X 18 FIFO Memory Used In Width Expansion Configuration
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF, HF and AEF signals on either (any) device used in the width expansion configuration. Do
not connect any output signals together.
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT72021/031/041 can easily be adapted to applications when the requirements are for greater than 1K12K14K
words. Figure 15 demonstrates Depth Expansion using three
IDT72021/031/041s. Any depth can be attained by adding
additional devices. The IDT72021/031/041 operates in the
Depth Expansion configuration when the following conditions
are met:
1. The first device must be designed by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied
to the Expansion In (Xi) pin of the next device. See
Figure 15.
4. External logic is needed toJl§nerate a composite Full
Flag (Ef) and Empty Flag (Ef). This requires the ORing
of all EFs and ORing of all FFs ~. alL.!!!.ust be set to
generate the correct composite FF or EF). See Figure
15.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information refer to Tech Note 9: "Cascading FIFOs or FIFO Modules".
COMPOUND EXPANSION MODE
The two expansion techinques described above can be
applied together in a straight forward manner to achieve large
FIFO arrays (see Figure 16).
BIDIRECTIONAL MODE
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT72021/031/041s as shown in
Figure 17. Care must be taken to assure that the appropriate
flag is monitor~ by each~stem (i.e., FF is monitored on the
device where W is used; EF is monitored on the device where
Ris used). Both Depth Expansion and Width Expansion may
be used in this mode.
DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted: a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 18), the FIFO permits the reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (twEF + tA) ns after the rising
edge of W, called the first write edge. It remains on the bus
until the R line is raised from low-to-high, after which the bus
would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted. In the interval of time that Rwas low, more
words can be written to the FIFO (the subsequent writes after
the first write edge will be deassert the Empty Flag); however,
the same word (written on the first write edge), presented to
the oU!Eut bus as the read pointe..G would not be incremented
when R was low. On toggling R, the other words that are
written to the FIFO will appear on the output bus as in the read
cycle timings.
5.4
13
II
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K X 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The Rline causes
the FF to be deasserted but the IN line, being low causes it to
be asserted a~in in anticipation of a new data word. On t~
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
For additional information refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech
Note 6: "Designing with FIFOs".
TRUTH TABLES
TABLE I-RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
Mode
Internal Status
Reset
Retransmit
RS
0
1
RT
X
0
XI
0
0
ReadlWrite
1
1
0
Read Pointer
Location Zero
Location Zero
Increment(1)
Outputs
Write Pointer
Location Zero
Unchanged
Increment(1)
EF
FF
HF
AEF
0
X
X
1
1
X
X
X
X
0
X
X
NOTE:
1. Pointer will increment if flag is High.
2677tb113
TABLE II-RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Mode
Reset First Device
Reset All Other Devices
ReadlWrite
RS
0
0
1
FL
0
1
X
Internal Status
XI
(1 )
(1 )
Read Pointer
Location Zero
Location Zero
X
(1 )
Outputs
Write Pointer
Location Zero
Location Zero
EF
FF
0
0
X
1
1
X
X
NOTE:
2677tb114
1. 2Q is connected to XO o.!£!'evious device. See Figure 15. RS = Reset Input FORT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
XI = Expansion Input, HF = Half-Full Flag Output, AEF = Almost Empty/Almost Full Flag.
~=_~~~-----R
w-------.---~
Q
D _ _--=9'-+-_ _--.--.--.
f-+.......-+-If----------
Vee
RS---------~~~
2677 drw 18
Figure 15. Block Diagram of 3K16K112K X 9 FIFO Memory (Depth Expansion)
NOTE:
1. IDT only guarantees depth expansion with identicallDT part numbers and speed.
5.4
14
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
aO-aN
R.W.RS
IDT720211
IDT720211
031/041
031/041
IDT72021/
031/041
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DO-ON ___________________________________________
2677drw 19
Figure 16. Compound FIFO Expansion
NOTES:
1. For depth expansion block see section od Depth Expansion and Figure 15.
2. For Flag detection see section on Width Expansion and Figure 14.
RB
EFB
HFB
SYSTEM A
SYSTEM B
2677 drw 20
Figure 17. Bidirectional FIFO Mode
DATA IN
t WLZ
DATA OUT
(1) __________r-________________________-+~
DATA OUT VALID
2677drw 21
Figure 18. Read Data Flow-Through Mode
NOTE:
1. Assume OE is asserted low.
5.4
15
IDT72021, IDT72031, IDT72041
CMOS PARALLEL FLAGGED FIFO WITH OE 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
14---
tWPF
t RFF
t DH
DATA IN
tA
DATAoUT
(1)_ _ _ _ _ _ _ _:;.;:::"
~
.
DATAOUTVA~[D )@_______. ;. .",. ____
2677drw22
Figure 19. Write Data Flow-Through Mode
NOTE:
1. Assume DE is asserted low.
5.4
16
(;5
Integrated Device Technology, Inc.
IDT72103
IDT72104
CMOS PARALLEL-SERIAL FIFO
2048 X 9-BIT
& 4096 x 9-BIT
FEATURES:
APPLICATIONS:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial input/output frequency
• Serial-to-parallel, parallel-to-serial, serial-to-serial, and
parallel-to-parallel operations
• Expandable in both depth and width with no external
components
• Flexishift™ - Sets programmable serial word width
from 4 bits to any width with no external components
• Multiple flags: Full, Almost-Full (Full-1/8),Full-MinusOne, Empty, Almost-Empty (Empty + 1/8), Empty-Plus
One, and Half-Full
• Asynchronous and simultaneous read or write
operations
• Dual-port, zero fall-through time architecture
• Retransmit capability in single-device mode
• Packaged in 40-pin ceramic and plastic DIP, 44-pin LCC
and PLCC
• Military product compliant to MIL-STD-883, Class B
•
•
•
•
•
•
•
•
•
High-speed data acquisition systems
Local area network (LAN) buffer
High-speed modem data buffer
Remote telemetry data buffer
FAX raster video data buffer
Laser printer engine data buffer
High-speed parallel bus-to-bus communications
Magnetic media controllers
Serial link buffer
DESCRIPTION:
The IDT721 031721 04 are high-speed Parallel-Serial FIFOs
to be used with high-performance systems for functions such
as serial communications, laser printer engine control and
local area networks.
A serial input, a serial output and two 9-bit parallel ports
make four modes of data transfer possible: serial-to-parallel,
parallel-to-serial, serial-to-serial, and parallel-to-parallel. The
IDT721 03/ 721 04 are expandable in both depth and width for
all of these operational configurations.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS (Do-D8)
SI
SIX
SICP
SERIAL
OUTPUT
CIRCUITRY
FF
SERIAU
PARALLEL
CONTROL
WRITE
POINTER
FF-1
EF+1
EF
FLAG
LOGIC
AEF
HF
RAM ARRAY
2048 x 9
4096 x 9
READ
POINTER
••
DEPTH
EXPANSION
LOGIC
!
,-_R_E_S_E_T_--,L
AS
_
LOGIC
SERIAL
OUTPUT
CIRCUITRY
DATA OUTPUTS (Qo-08)
SERIAL
OUTPUT
SO
SOX
SOCP
2753 drw 01
CEMOS and F1exishift are trademarks 01 Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·200915
- + - - - - - - - - - - - '
GND
Vee
2753 drw38
SI-+~----------~
NOTE:
1. All Si/PI pins are tied to GND and SO/PO pins are tied to Vee. OE is tied LOW. For FF and EF connections see Figure 29.
Figure 35. An 8K X 8 Serial-In, Parallel-Out FIFO
5.5
28
10T72103,10T72104
CMOS PARALLEL-SERIAL FIFO 2048 X O-BIT & 4006 X O-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
l
\tci
SI
SIX
I
Os
IOT72104
-f---- SICP
OO-S
Xi
W 14-
R
• l
SI
SICP
10T72104
XO
SERIAL
INPUT
CLOCK
I
SIX SI Os XO
SICP
Vi 14R
SI
SICP
IOT72104
IOT72104
Xi
XO
SIX SI 05 XO
R
I
SIX SI Os XO
SICP
Xi
Xi
IDT72104
• l 'j
Vi
~+-
R
SICP
IDT72104
Oo-s
Oo-s
00-5
~
~
~
~
Po-s
~
~
____________________
w 14R~
l
•l
W ~+-
05
Xi
00-5
XO
r
SIX
l
1
\tci
Xi
Oo-s
l
• l
I
Os
SIX
P9-17
~y~
w +fR+ r---I-- READ
~
P1S-23
____________________- - J
2753 drw39
PARALLEL DATA OUT
NOTE:
1. All SI/PI pins are tied to GND. SO/PO pins are tied to Vee. For FF and EF connections see Figure 29.
Figure 36. An 8K X 24 Serial-In, Parallel-out FIFO Using Six 10T72194s
Serial Data Output
The Serial Output mode is selected by setting the SO/PO
line low. When in the Serial-Outmode, one of the Q1-slines
shou Id be used to control the Rsignal. In the Serial-Out mode,
the Qo-s are taps off a digital delay line. By selecting one of
these taps and connecting n to the input, the width of the serial
word to be read and shifted is programmed. For instance, if
the Qs line is connected to the R input, on every sixth clock
cycle a new word is read from the FIFO RAM array and begins
to be shifted out. The serial word is shifted out Least
Significant Bit First. If the input mode of the FIFO is parallel,
the information that was written into the Do bit will come out as
the first bit of the serial word. The second bit of the serial
stream will be the 01 bit and so on.
In the stand alone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SOCP clock, all of the
Q outputs except for Qo go LOW and a new serial word is
started. On the next clock cycle, Q1 will go HIGH, Q2 on the
next clock cycle and so on, as shown in Fig.!!l"e 37. This
continues until the Q line, which is connected to R, goes HGIH
at which point all of the Q lines go LOW on the next clock and
a new word is started.
In the cascaded case, word width of more than 9 bits can
be achieved by using more than one device. By tieing the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to Qs of the previous devices, a cascaded
serial word is achieved. On the first LOW-to-H IGH clock edge
of SOCP, all the lines go low exceptfor Qo. Just as in the stand
alone case, on each consecutive clock cycle, each Q line goes
HIGH in the order of least to most significant. When QS (which
is connected to the SOX input of the next device) goes HIGH,
the Do of that device goes HIGH, thus cascading from one
device to the next. The Q line of the most significant device,
which programs the serial word width, is connected to all R
inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is tri-stated, only
the device which is currently shifting out is enabled and driving
the 1-bit bus.
Figure 39 shows an example of the interconnections for a
16-bit serialized FIFO.
5.5
20
10T72103,10T72104
CMOS PARALLEL·SERIAL FIFO 2048 X 9·BIT & 4096 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE DEVICE SERIAL OUTPUT CONFIGURATION
Vee
GND PARALLEL DATA IN
SERIAL·OUT CLOCK
SERIAL·OUT DATA
GND
Vee
4
6
4
6
0
SOCP
Qo=1
Q1V
V
Q2~
'--I
Q3\
Q4\
\
/
\
/
/
Q6\
Q7\
R\
\
1\
1\
/
/
/
'-'-'-'-'-r--L
r--L
2753 drw40
NOTE:
1. Input data is loaded in 8-bit quantities and read out serially.
Figure 37. Serlal·Out Configuration
5.5
30
10172103,10172104
CMOS PARALLEL-SERIAL FIFO 2048 X 9-BIT & 4096 X 9-BIT
SOCP-SERIAL
OUTPUT CLOCK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUT FROM
RAM ARRAY
SO/PO
DELAYED
TIMING
GENERATOR
SERIAL-OUT
REGISTER
SO/PO
PARALLEL-OUT DATAl
TIMED OUTPUT Oo-s
2753 drw 41
Figure 38. Serial-Output Circuitry
PARALLEL DATA IN
16-BITS WIDE
7
Do-s
SO
SERIAL-OUTPUT
CLOCK
FIFO #1
SOX
R
a
\
06 O.E FIFO #2 \
AND R OF FIFO
#1 AND FIFO #2
\
SliP I
SO/PO
SOX
as
R
10
14
06
15
,rvv\
/
fC
FIFO #2
SOCP
A..r\
sOF FIFO #1 \
AND SOX OF
FIFO #2
GND
SO
SOCP
Vee
SOCP
00-6
Vee
55
.
'------\J;JIr----...I
'----------J!ir---------...I
2753 drw 42
NOTE:
1. The parallel Data In is tied to 00-8 of FIFO #1 and 00-6 of FIFO #2.
Figure 39. Serial-Output for 16-Bil Parallel Data In
5.5
31
IDTI2103,IDTI2104
CMOS PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL OUTPUT WITH DEPTH EXPANSION
00-7
00-7
W 14-...-+-+-----·W
10T72104
FLIRT
SOCP+rj---r==========~_~~~~~
Vee
SO
-+.........._ _ _ _ _--1
2753 drw 43
NOTE:
1. All SI/P) pins are tied to Vee and SO/PO pins are tied to GND. OE is tied LOW. For FF and EF connections see Figure 17.
Figure 40. An 8K x 8 Parallel-In Serial-Out FIFO
SERIAL IN AND SERIAL OUT WITH WIDTH AND DEPTH EXPANSION
SICP
I
SI
~
FULL
FLAG
~-
EMPTY
FLAG
Vee
~
1
SICP
t
l
SI
II
•
I
SICP XI XO 08
FURT
IOT72104
FF
EF
SOX so SOCP
r
Iii
l
SI
SIX
~
~
I
R+-
f
1
1
i
SICP XI XO Os
Iii *10T72104
SOX so
T
....
SOCP XOXI aS
FURT
R~
as
r
Os
Iii
IOT72104
+
SIX
l
SI
sox so
I
'l¥Q
I
1
SIX
FURT
~
Vee
so
•
I
08
SIX
SI SICP
:
FURT
W .-.
IOT72104
FF
R~
EF
sox so SOCP XO XI aS
I
~
sOCP
1
~.
II
+
SOCP
J
R~
as
1
2753 drw 44
NOTE:
.
1. All RS pins are connected together. All OE pins are connected LOW. All Si/p) and SO/PO pins are grounded.
Figure 41. 128K x 1 Serial-In Serial-Out FIFO
5.5
32
(;)®
IDT72105
IDT72115
IOT72125
CMOS PARALLEL-TO-SERIAL FIFO
256 X 16, 512 x 16, 1024 x 16
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
The IDT72105172115172125s are very high speed, low
power dedicated parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256,512 and 1 K word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller
applications.
Expansion in width and depth can be achieved using
multiple chips. lOT's unique serial expansion logic makes this
possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/AlmostFull. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The AlmostEmpty/Almost-Full Flag is available only in a single device
mode.
The IDT72105/15/25 are fabricated using lOT's leading
edge, submicron CEMOSTM technology. Military grade product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
•
•
•
•
25ns parallel port access time, 35ns cycle time
45MHz serial output shift rate
Wide x16 organization offering easy expansion
Low power consumption (50mA typical)
LeasVMost Significant Bit first read selected by asserting
the FUOIR pin
Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
Dual-port zero fall-through architecture
Available in 28-pin 300 mil plastic and ceramic DIP,
28-pin SOIC, 32-pin LCC and 32-pin PLCC
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
00-15
i
16
WRITE
POINTER
RAM
ARRAY ,++READ j4POINTER
256 x 16
512 x 16
1024 x 16
I-~
RSIX
RSOX
Lt
FLAG
LOGIC
EXPANSION
LOGIC
FUDIR
SERIAL OUTPUT
LOGIC
~
i
SOCP
SO
I
I- 1-+
I- 1-+
FF
EF
I- 1-+ HF
I- 1-+ AEF
I
2665 drwOl
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC-203813
00 cS
I-J L....J I-J
I I
I-J L..J I-J
-t
I I
N
C'>
'"
J5
J6
J7
Js
L-IC'>
C;;
2S [
27 [
26 [
25 [
24[
23 [
22 [
J32-1
L32-1
J9
JlO
J11
J12
J 13:!
~ ~ ~ ~ ~
r-1 r-1
o ><
rI
,..,
r-1
en en a:
g29[
012
011
010
09
Os
RS
NC
SO
~ 21 [ NC
, . , r-1
ILL c..
ZU)~~o~g
a:
I~ XCI)
aCI)
DIP/SOIC
TOP VIEW
a:
2665 drw 02a
, 2665 drw 02b
LCC/PLCC
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
1/0
Description
00-015
Inputs
I
Data inputs for 16-bit wide data.
RS
Reset
I
When 8§.is se!J.9.w, internal READ and WRITE pointers are set to the first location of the RAM
array. FF and HE.go HIGH. EF and AEF g2-h0W. A reset is required befo~an initial WRITE
after power-up .. W must be high during the RS cycle. Also the First Load pin (FL) is programmed
only during Reset.
W
Write
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Oata set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in
the RAM array sequentially and independently of any ongoing read operation.
SOCP
Serial Output
Clock
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
FUDIR
First Load!
Direction
I
This is~ dual purpose input used in the width and deE!t) expansion confi9!:!!ations. The First
Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
RSIX
Read Serial In
Expansion
I
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
SO
Serial Output
0
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
FF
Full Flag
0
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
EF
Empty Flag
0
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is
HIGH, the device is not empty.
HF
Half-Full Flag
0
When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to
half-full.
RSOXlAEF
Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag
0
This is a dual pur~ output. In the single device configuration (RSIX HIGH), this is an AEF
2.!:!.!Eutpin. WhenAEFis LOW, the device is empty-to-(1/8 full-1) or (7/8 full +1)-to-full. When
AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
Vee
Power Supply
Single power supply of 5V.
GND
Ground
Single ground of
av.
26651bl01
5.6
2
IOTI2105,IOTI2115, IOTI2125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL·TO·SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATUS FLAGS
Number of Words in FIFO
1OT721 05
10T72115
10T72125
FF
AEF
HF
0
0
0
H
L
H
L
1-31
1-63
1-127
H
L
H
H
EF
32-128
64-256
128-512
H
H
H
H
129-224
257-448
513-896
H
H
L
H
225-255
449-511
897-1023
H
L
L
H
256
512
1024
L
L
L
H
2665tbl02
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
TBIAS
TSTG
lOUT
Rating
Terminal
Voltage with
Respect to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
-0.5 to + 7.0
Military
-0.5 to + 7.0
Unit
V
o to +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to + 125
-65 to + 155
°C
50
50
rnA
Symbol
NOTE:
2665 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Min.
Typ.
Max.
Unit
Vccc
Commercial Supply
Voltage
4.5
5.0
5.5
V
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
V
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL(1)
Input Low Voltage
Commercial &
Military
-
-
0.8
V
0
0
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vcc = 5.0V ± 10%, TA = O°C to +70°C; Military Vcc = 5V ± 10%, TA = ·55°C to +125°C)
10T72105/10T721151
10T72125
10T72105/101721151
10T72125
Military
Commercial
Symbol
Min.
Parameter
I IL(1)
Input Leakage Current (Any Input)
IOL(2)
Output Leakage Current
VOH
Output Logic "1" Voltage lOUT
VOL
Output Logic "0" Voltage lOUT
-
-
-1
-10
= -2mA(5)
= 8mA(6)
Typ.
2.4
Max.
Min.
Typ.
Unit
Max.
1
-10
-
10
10
-10
-
10
-
2.4
-
-
V
0.4
-
0.4
V
75
125
rnA
4
12
rnA
1
8
rnA
ICC1 (3)
Power Supply Current
-
50
100
Icc2(3)
Average Standby Current
-
4
8
-
-
1
6
-
JlA
JlA
(Vii = RS = FUDIR = VIH)(SOCP = VIL)
ICC3 (3,4,7)
Power Down Current
NOTES:
1. Measurements with O.4V::; VIN::; Vcc.
2. SOCP = VIL, 0.4::; VOUT::; Vee.
3. icc measurements are made with outputs open .
. 4. RS = FuDIR = W= Vee - 0.2V; SOCP = 0.2V; ali other inputs ;:: Vcc - 0.2 or ::; 0.2V.
5. For SO, lOUT = -4mA.
6. For SO, lOUT = 16mA.
7. Measurements are made after reset.
5.6
2665tbl05
3
IDT72105,IDT72115, 10172125,
256 X 16, 512 x 16, 1024 x 16 PARALLEL·TO·SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vce = SV+10%,
TA = O°C to +70°C' Military' Vee = SV +
- 10% TA = ·SsoC to +12S°C)
Parameter
Symbol
ts
Parallel Shift Frequency
tsocp
Serial Shift Frequency
Figure
COM'L
72105L25
72115L25
72125L25
Min. Max.
-
-
28.5
50
MILITARY
72105L30
72115L30
72125L30
Min. Max.
-
25
40
1
-
45
COM'L AND
72105L50
72115L50
72125L50
Min. Max.
-
MILITARY
72105L80
72115L80
72125L80
Min. Max.
Unit
15
-
10
MHz
40
-
28
MHz
ns
PARALLEL INPUT TIMINGS
twc
Write Cycle Time
2
35
twpw
Write Pulse Width
2
25
tWR
Write Recovery Time
2
10
tos
Data Set-up Time
2
12
tOH
Data Hold Time
2
0
-
65
-
100
50
-
80
15
20
2
-
5
-
tWEF
Write High to EF High
5,6
-
35
-
40
-
45
-
50
ns
tWFF
Write Low to FF Low
4, 7
Write Low to Transitioning HF, AEF
8
-
35
tWF
35
-
40
-
45
ns
45
-
50
40
50
tWPF
Write Pulse Width After FF High
7
25
ns
-
30
-
50
-
80
-
ns
30
10
13
15
15
ns
ns
ns
ns
SERIAL OUTPUT TIMINGS
tsocp
Serial Clock Cycle Time
3
20
9
10
15
-
ns
8
-
35
3
-
25
Serial Clock Width High/Low
-
22
tsocw
tSOPD
SOCP Rising Edge to SO Valid Data
3
-
14
-
15
-
15
-
17
ns
tSOHZ
SOCP Rising Edge to SO at High Z(1)
3
3
14
3
14
3
15
3
17
ns
tsOLZ
SOCP Rising Edge to SO at Low Z(1)
3
3
14
3
14
3
15
3
17
ns
tsoCEF
SOCP Rising Edge to EF Low
5,6
-
35
40
ns
4, 7
-
35
50
ns
tSOCF
SOCP Rising Edge to Transitioning
HF, AEF
8
-
35
40
45
-
50
SOCP Rising Edge to FF High
-
45
tSOCFF
-
50
ns
tREFSO
SOCP Delay After EF High
6
35
-
40
-
65
-
100
-
ns
-
100
-
ns
10
ns
12
-
40
45
ns
RESET TIMINGS
tRSC
Reset Cycle Time
1
35
-
45
-
65
tRS
Reset Pulse Width
1
25
-
30
50
tRSS
Reset Set-up Time
1
25
30
tRSR
Reset Recovery Time
1
10
-
-
7
15
50
15
80
80
20
ns
ns
ns
EXPANSION MODE TIMINGS
tFLS
FL Set-up Time to RS Rising Edge
9
7
tFLH
FL Hold Time to RS Rising Edge
9
0
tOIRS
DIR Set-up Time to SOCP Rising
Edge
9
10
-
11
-
12
-
tOIRH
DIR Hold Time from SOCP Rising
Edge
9
5
-
5
-
5
-
5
-
ns
tSOXD1
SOCP Rising Edge to RSOX Rising
Edge
9
-
15
-
17
-
17
-
20
ns
tSOXD2
SOCP Rising Edge to RSOX Falling
Edge
9
-
15
-
17
-
17
-
20
ns
tSIXS
RSIX Set-up Time to SOCP Rising
Edge
9
5
-
5
-
8
-
15
-
ns
tSIXPW
RSIX Pulse Width
9
10
-
10
-
15
-
20
-
NOTE:
1. Values guaranteed by design.
1
8
2
5
ns
ns
ns
2665tbl06
5.6
4
10T72105,10T72115, 10T72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
SV
Input Pulse Levels
GND t03.0V
Input Rise/Fall Times
1.1Kn
Sns
Input Timing Reference Levels
1.SV
Output Reference Levels
1.SV
Output Load
TO
OUTPUT -----.>----e
PIN
See Figure A
680n
2665tbl07
2665 drw 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
COUT
Output
Capacitance
Conditions
Max.
Unit
or equivalent circuit
VIN = OV
10
pF
Figure A. Output Load
VOUT= OV
12
pF
·Includes jig and scope capacitances.
NOTE.
1. This parameter is sampled and not 100% tested.
2665tbiOa
FUNCTIONAL. DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (FL) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the
00-15 input data lines. A write cycle is initiated on the falling
edge of the Wri~JW) signal provided the Full Flag (FF) is not
asserted.J!!he W signal changes from HIGH-to-LOWand the
Full Flag (FF) is already set, thewrite line is internally inhibited
internally from incrementing the write pointer. and no write
operation occurs.
.
Data set-up and hold times must be me~ith respect to the
rising edge of Write. On the rising edge of W, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next
data word is inhibited from moving to the output register and
being clocked out by SOCP.
The serial word is shifted out Least S~ificant Bit or Most
Significant Bit first, depending on the FUDIR level during
operation. A LOW on OIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
~---------------tRSC---------------~
~-------------tRS ---------~
~--------tRSS------------.~--
w
FLAG
STABLE
SOCP
FUDIR
NOTE 2
\. t=:
____________
<_______________________________________________________________________________________________________________________________________________________________
\ '----------',r!.--
t WEF
EF __________________________________
n-1
NOTE 1
SOCP
/\--
NOTE 2
SO
NOTE:
1. soep should not be clocked until EF goes high.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
2665 drw09
Figure 6. Empty Boundary Condition Timing
o
SOCP
FF
II
w
--+jooII---tDH
DATA IN
---------+--------------------------[
DATA IN VALID
'-------------------'
SO
NOTE 1
DATA OUT VALID
2665 drw 10
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
Figure 7. Full Boundary Condition Timing
w
1------J/
HALF-FULL
HALF-FULL (1/2)
HALF-FULL + 1
soep
AEF
AEF
ALMOST-FULL (7/8 FULL + 1)
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
2665 drw 11
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
5.6
7
10T72105,10T72115, 10T72125,
256 x 16,512 x 16, 1024 x 16 PARALLEL·TO·SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
15
RSIX
o
---------------------1 \--____-'
2665 drw 12
Figure 9. Serial Read Expansion
OPERATING CONFIGURATIONS
Width Expansion Mode
In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the
RSOX and RSIX pins together, as shown in Figure 11, and
programming which is the Least Significant Device, a cascaded serial word is achieved .. The Least Significant Device
is programmed by a LOW on the FUDIR pin durin~set. ~II
other devices should be programmed HIGH onthe FUDIRpln
at reset.
.
Single Device Mode .
.
The device must be reset before beginning operation so
that all flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single devi~era·
tion to the device. The RSOXlAEF pin defaults to AEF and
outputs the Almost·Empty and Almost-Full Flag.
PARALLEL DATA IN
00-15
Vee
SERIAL OUTPUT CLOCK
RSIX
RSOXlAEF
SOCP
SO
ALMOST-EMPTY/FULL FLAG
SERIAL DATA OUT
2665 drw 13
Figure 10. Single Device Configuration
5.6
8
IDT72105,IDT72115, IDT72125,
256 x 16, 512 X 16, 1024 X 16 PARALLEL·TO·SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Inputs
Internal Status
Outputs
RS
FL
CIR
Read Pointer
Write Pointer
AEF, EF
FF
Reset
0
X
X
Location Zero
Location Zero
0
1
1
ReadiWrite
1
X
0,1
Increment(l)
Increment(l)
X
X
X
Mode
HF
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
2665tbl09
Table 1. Reset and First Load Truth Table-Single Device Configuration
The three flag outputs, Empty (EF), Half-Full (HF) and
Full (FF), should be taken from the MostSignificant Device (in
the example, FIFO #2). The Almost-Empty/Almost-Full flag is
not available. The RSOX pin is used for expansion.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1·bit bus. NOTE: After reset, the level on the
FUOIR pin decides if the Least Significant or Most Significant
Bit is read first out of each device.
SERIAL OUTPUT CLOCK
PARALLEL OATAIN
~
LOW AT RESET
~
l'
00-15
SOCP
FlIOIR
RSIX
HIGH AT RESET
~
EF
016-31
HF
W
FF
RSIX
SOCP
FlIOIR
-
-
W
Depth Expansion (Daisy Chain) Mode
FIFO #1
RSOX
SO
I
I
I
RSOX
EF ~ EMPTY FLAG
HF ~ HALF-FULL FLAG
FIFO #2
SO
FF ~ FULL FLAG
i
SERIAL OATAouT
2665 drw 14
Figure 11. Width Expansion for 32·bit Parallel Data In
The IDT721 05/15/25 can easily be adapted to applications
requiring greater than 1024 words. Figure 12 demonstrates
Depth Expansion using three IDT72105/15/25s and an
IDT74FCT138 Address Decoder. Any depth can be attained
by adding additional devices. The Address Decoder is necessary to determine which FIFO is being written. A word of data
must be written sequentially into each FIFO so that the data
will be read in the correct sequence. The IDT72105/15/25
operates in the Depth Expansion Mode when the following
conditions are met:
1. The first device must be programmed by holding FL LOW
at Reset. All other devices must be programmed by
holding FL high at reset.
2. The Read Serial Out Expansion pin (RSOX) of each device
must be tied to the Read Serial In Expansion pin (RSIX) of
the next device (see Figure 12).
3. External logic is needed to generate composite Empty,
5.6
Half-Full and Full Flags. This requires the OR-ing of all EF,
HF and FF Flags.
4. The Almost-Empty and Almost-Full Flag is not available
due to using the RSOX pin for expansion.
Compound Expansion (Daisy Chain) Mode
The IDT72105/15/25 can be expanded in both depth and
width as Figure 13 indicates:
1. The RSOX-to-RSIX expansion signals are wrapped
around se~entially.
2. The write (W) signal is expanded in width.
3. Flag signals are only taken from the Most Significant
Devices.
4. The Least Significant Device in the array must be
programmed with a LOW on FUDIR during reset.
9
II
IDT72105,ID172115, ID172125,
256 x 16,512 X 16, 1024 X 16 PARALLEL-TO-SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW AT RESET
..
--
PA RALLEL DATA IN
~
~
D0-15
FUDIR
RSIX
-
W
SOCP
,
EF
-
EMPTY
FLAG
I
HF f -
FIFO #1
RSOX
SO
FF
I-
I
ADDRESS 00
DECODER 01
74FCT138 10 f-- f--f--
HIGH AT RESET
....
~
DO-15
-f-t W
SERIAL OUTPUT CLOCK
FUDIR
RSIX
FIFO #2
SOCP
EF
I-r-r-
HF
RSOX
SO
FF
HALF-FULL
FLAG
--
J
I-t- r--
I
HIGH AT RESET
..
'---
~
D0-15
FUDIR
RSIX
-
f- W
EF
-
HF
FIFO #3
L...eo SOCP
-
I-r-
RSOX
SO
FULL
FLAG
I
-
I
FF
I
SERIAL DATA OUT
2665 drw 15
Figure 12. A 3K
X
16 Parallel-to-Serlal FIFO using the ID172125
Inputs
Internal Status
Write Pointer
HF, FF
Location Zero
0
1
Location Zero
Location Zero
0
1
X
X
X
X
F[
DIR
Read Pointer
Reset-First Device
0
0
X
Location Zero
Reset All Other Devices
0
1
X
ReadIWrite
1
X
0,1
Mode
NOTE:
1. RS
Outputs
EF
AS
2665tbll0
= Reset Input, FLtFIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.
Table 2. Reset and First Load Truth Table-Width/Depth Compound Expansion Mode
5.6
10
10172105,10172115, 10172125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESS
DECODER
74FCT138
PARALLEL DATA IN
00
I
01
10
SERIAL OUTPUT CLOCK
LOW ON RESET
I
,-- ~
...
I
-
sOCP
~
EF
-
FUDIR
DO-15
FIFO #1
-
-t W
HF
~
--.
....
t
RSOX
SO
I
I
SOCP
FUDIR
Dl6-31
4
FF
Vi
'-I-
'-r.
L-~
I
~
FUDIR
W
FIFO #3
RSIX
i
RSOX
t
I
SO
'--
r.
f-.
so
I
I
~
FF
-
!
p
RSOX
so
I
I
FF
RSOX
so
t
I
J
~
~
SOCP
FUDIR
Dl6-31
FIFO #6
L----
~
Vi
RSIX
f
RSOX
I
~
EMPTY
FLAG
FF l-
EF f-f-fHF
RSIX
HF
-
i
FIFO #4
EF
FIFO #5
RSIX
l
FUDIR
Dl6-31
-
FUDIR
DO-15
W
J
I
SOCP
-
,-+-.. Vi
p
r-
1
sOCP
HF
RSOX
1
... 1--
-
EF
DO-15
-
-
.
-
r--
-
RSIX
I
SOCP
EF
HF
FIFO #2
RSIX
HIGH ON RESET
HALF-FULL
FLAG
I
FF f-f- r-
EF t-t- r-tHF f-f-
so
FF
1
---I
FULL
FLAG
SERIAL DATA OUT
2665 drw 16
Figure 13. A 3K x 32 Parallel-to-Serlal FIFO using the 10172125
5.6
11
G
IDT72131
IDT72141
CMOS PARALLEL-TO-SERIAL FIFO
2048 X 9-81T & 4096 x 9-81T
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 7-9, 16-18,32-36
bit using FlexishifPM serial output without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low power CEMOSTM
technology
• Available in 28-pin ceramic, plastic DIP and 32-pin
plastic leaded chip corner (PLCC)
• Military product compliant to MIL-STO-883, Class B
The IOT72131/72141 are high-speed, low power parallelto-serial FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IOT72131/72141 can be
configured with the lOTs serial-to-parallel FIFOs (IOT72132/
72142) for bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output
port. Wider and deeper parallel-to-serial data buffers can be
built using multiple IOT72131/72141 ch~ lOTs unique
Flexishift serial expansion logic (SOX, NR) makes width
expansion possible with no additional components. These
FIFOswili expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IOT72131 /141 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The almost-full (7/8), half-full, and almost empty
(1/8) flags signal memory utilization within the FIFO.
The IOT72131/72141 is fabricated using lOTs high-speed
submicron CEMOS technology. Military grade product is
manufactured in compliance with the latest revision of
MIL-STO-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
Do-Da
EF
FLAG
LOGIC
AEF
IHF
FF
RAM ARRAY
2048 x 9
4096 x 9
WRITE
POINTER
NEXT READ
POINTER
·••
FU~~~
RESET LOGIC
I
SOX
SO
04 06 07 Oa
2751 drw 01
CEMOS and Flexishift are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology. Inc.
APRIL 1992
DSC·2029/3
5.7
1
IDTI2131,IDTI2141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9-91T & 4096 x 9·91T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
Name
Description
1/0
Do-D8
Inputs
I
Data inputs for 9-bit wide data.
RS
Reset
I
When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM
array. HFand FE.go high, and AEF and EF go low. A reset is r~ed before an initial WRITE
after power-up. W must be high and SOCP must be low during RS cycle.
W
Write
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data setup and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored
in the RAM array sequentially and independently of any ongoing read operation.
SOCP
Serial Output
Clock
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
NR
Next Read
I
To program the Serial Out data word width, connect NR with one of the Data Set pins (04, 06,
07 and 08). For example, NR - 07 programs for a 8-bit Serial Out word width.
FURT
First Load!
I
This is a dual~rpose input. In the single device configuration (XI grounded), activating
retransmit (FURT·low) w!!!..set the internal READ pointer to the first location. There ~no effect
on the WRITE pointer. W must be high and SOCP must be low before setting FURT low.
Retransmit is not compatible with depth expansion. In the depth expansion configuration, FURT
grounded indicates the first activated device.
Retransmit
XI
Expansion In
In the single device configuration, XI is grounded. In depth expansion ordaisy chain expansion,
I
Xi is connected to XO (expansion out) of the previous device.
SOX
Serial Output
Expansion
I
In the Serial Output Expansion mode, the SOX pin ofthe least significant device is tied high. The
SOX pin of all other devices is connected to the 08 pin of the previous device. Data is then
clocked out least significant bit first. For single device operation, SOX is tied high.
SO
Serial Output
0
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first.
In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristatod
at the end of the byte.
FF
Full Flag
0
When FF goes low, the device isfull and further WRITE operations are inhibited. When FF is high,
the device is not full.
EF
Empty Flag
0
When EF goes low, the device is empty and further READ operations are inhibited. When EF
is high, the device is not empty. See the description on page 6 for more details.
AEF
Almost-Emptyl
Almost-Full Flag
0
When AEF is low, the device is empty to 1/8 full or 7/8 to completely full. When AEF is high, the
device is greater than 1/8 full, but less than 7/8 full.
XO/HF
Expansion Out!
Half-Full Flag
0
This is a dual-purpose output. In the single device configuration (XI grounded), the devic~ more
than half full when HF is low. In the dep!!!.expansion configuration (XO connected to XI of the
next device), a pulse is sent from XO to XI when the last location in the RAM array is filled.
04,06,
07 and
08
DataSet
0
The appropriate Data Set pin (04,06,07 and 08) is connected to NR to program the Serial Out
data word width. Forexample: 06 - NR programs a 7-bitword width, 08 - NR programs a 9-bit
word width, etc.
Vee
Power Supply
Single Power Supply of 5V.
GND
Ground
Single ground at OV.
2751 tbl01
STATUS FLAGS
Number of Words in FIFO
IDT72131
IDT72141
FF
AEF
HF
0
0
H
L
H
L
1-255
1-511
H
L
H
H
EF
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2751 tbl02
5.7
2
10T72131, 10T72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
W
28
Vee
04
27
05
03
26
06
25
07
02
0 1
24
P28-1
&
C28-3
Do
Xi
23
FURT
22
RS
SOX
EF
SOCP
20
XO/HF
10
19
GND
AEF
11
18
08
FF
12
17
07
04
13
16
06
GND
14
15
NR
DIP
TOP VIEW
J5
08
21
SO
INDEX
LJLJLJIILJLJLJ
~ (') '" I I ~
C;; g
';:-l
29 [
Do
J6
28[
08
Xi
J7
27[
NC
SOX
J8
SOCP
]9
J32-1
26 [
FLiRT
25[
RS
EF
SO
J10
24[
AEF
]11
23 [
XO/HF
FF
J12
J 13
22 [
GND
21 [
08
NC
;!
2751 drw02b
2751 drw 02a
PLCC
TOP VIEW
5.7
3
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Min.
Typ.
Max.
Unit
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vcc
5.0
5.5
V
Operating
Temperature
Oto +70
-55 to +125
°C
Commercial Supply
Voltage
4.5
TA
GND
Supply Voltage
0
V
TSIAS
Temperature
Under Bias
-55 to +125
-65to+135
°C
VIH
Input High Voltage
Commercial
2.0
-
-
V
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
VIH
Input High Voltage
Military
2.2
-
-
V
lOUT
DC Output
Current
50
50
mA
VIL(l)
Input Low Voltage
-
-
0.8
Parameter
0
0
NOTE:
1. 1.SV undershoots are allowed for 10ns once per cycle.
2751 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V
2751 tbl04
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
CIN
Input Capacitance
VIN = OV
COUT
Output Capacitance
VOUT
= OV
Unit
Max.
10
pF
12
pF
NOTE:
1. This parameter is sampled and not 100% tested.
2751 tbl05
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc= 5.0V ± 10%, TA = O°C to +70°C; Military: Vcc = S.OV ± 10%, TA = -55°C to + 125°C)
10T72131/10T72141
10T72131/10T72141
Commercial
Symbol
IIL(l)
Parameter
Input Leakage Current
(Any Input)
Min.
Typ.
-1
-
Military
Max.
Min.
Max.
Unit
1
-10
Typ.
-
10
J.tA
10
J.tA
IOL(2)
Output Leakage Current
-10
-10
Output Logic "1" VOltage,
lOUT = -8mA
2.4
-
10
VOH
-
2.4
-
-
V
VOL
Output Logic "0" Voltage
lOUT = 16mA
-
-
0.4
-
-
0.4
V
Icc1(3)
Power Supply Current
140
-
100
160
mA
~erage Standby Current
-
90
ICC2(3)
8
12
-
12
25
mA
-
-
2
-
-
4
mA
12
0N = RS = FURT = VIH)
(SOCP = VIL)
Icc3(L)(3,4)
Power Down Current
Icc3(S)(3,4)
Power Down Current
NOTES:
1. Measurements with 0.4" VIN" Vcc.
2. SOCP"VIL,O.4"VouT"Vee.
3. lee measurements are made with outputs open.
4. RS = FIlRT = W= Vee -O.2V; SOCP::; 0.2V; all other inputs ~ Vee -0.2V or::; 0.2V.
5.7
8
mA
2751 tbl 06
4
I0T72131,IOTI2141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5.0V ± 10%, TA = O°C to +70°C; Military: "Vee = 5.0V ± 10%, TA= -55°C to +125°C)
Military "
Commercial
Symbol
ts
tsocp
Parameter
IDT72131x35
IDT72141x35
Min.
Max.
Parallel Shift Frequency
-
Serial-Out Shift Frequency
-
MIl. and Com'l.
IDT72131x40
IDT72141x40
Min.
Max.
IDT72131x50
IDT72141x50
Min.
Max.
-
20
50
-
50,
18
-
20
-
0
45
10
-
40
. 10
-
30
0
15
-
-
30
-
35
-
45
-
35
-
45
50
-
65
-
50
-
22.2 .
"-
Unit
15
MHz
40
MHz
PARALLEL INPUT TIMINGS
tDS
tDH
twc
twpw
Data Set-up Time
Data Hold Time
Write Cycle Time
Write Pulse Width
twR
tWEF
tWFF
tWF
twPF
Write
Write
Write
Write
35
Recovery Time
High to EF High
Low to FF Low
Low to Transitioning HF, AEF
Write Pulse Width After FF High
-
30
-
45
35
-
50
40
5
65
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
SERIAL OUTPUT TIMINGS
tSOHZ
tSOlZ
tSOPD
SOCP Rising Edge to SO at High Z(1)
SOCP Rising Edge to SO at Low Z(1)
tsox
tsocw
tSOCEF
tSOCFF
tSOCF
SOX Set-up Time to SOCP Rising Edge
Serial In Clock Width High/Low
SOCP Rising Edge (Bit 0 - Last Word) to EF Low
SOCP Rising Edge to FF High
SOCP Rising Edge to HF, AEF, High
-
20
-
30
tREFSO
Recovery Time SOCP After EF High
35
5
16
5
16
5
26
5
22
5
22
5
22
18
-
18
-
18
-
5
-
5
10
-
-
SOCP Rising Edge to Valid Data on SO
5
8
ns
ns
ns
25
-
25
35
35
-
40
30
-
40
ns
ns
ns
ns
ns
-
40
-
50
-
ns
-
8
RESET TIMINGS
tRSC
tRS
tRSS
tRSR
tRSF1
Reset Cycle Time
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
45
-
50
35
-
40
35
-
40
45
45
-
10
-
10
65
-
50
-
ns
ns
50
-
ns
ns
65
15
-
tRSF2
tRSQl
Reset to EF and AEF Low
Reset to HF and FF High
Reset to Q Low
20
-
20
-
35
-
ns
ns
ns
tRSQH
Reset to Q High
20
-
20
-
35
-
ns
Retransmit Cycle Time
45
-
65
40
50
35
-
40
-
10
-
10
-
15
-
ns
35
-
50
Retransmit Pulse Width"
Retransmit Set-up Time
Retransmit Recovery Time
35
40
-
50
40
50
ns
ns
-
ns
ns'
ns
50
50
65
RETRANSMIT TIMINGS
tRTC
tRT
tATS
tRTR
50
I
ns
ns
ns
DEPTH EXPANSION MODE TIMINGS
tXOl
tXOH
ReadlWrite to XO Low
ReadlWrite to XO High
-
35
-
tXI
tXIR
XI Pulse Width
XI Recovery Time
XI Set-up Time
35
-
40
-
50.
10
-
10
-
10
15
-
tXIS
15
NOTE:
1. Guaranteed by design minimum times, not tested.
"
15
2751 tbl 07
5.7
5
10T72131, 10T72141
CMOS PARALLEL·TO·SERIAL FIFO 2048 x 9·BIT & 4096
x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS {Continued}
(Commercial: Vce = 5.0V ± 10%, TA = O°C to +70°C; Military: Vee = 5.0V ± 10%, TA = -55°C to +125°C)
Military and Commercial
IDT72131x65
IDT72141x65
Symbol
Parameter
ts
Parallel Shift Frequency
tsocp
Serial-Out Shift Frequency
Min.
-
Max.
12.5
33
IDT72131x80
IDT72141x80
Min.
Max.
IDTI2131x120
IDTI2141x120
Max.
Unit
10
-
7
MHz
28
-
25
MHz
40
-
20
-
-
Min.
PARALLEL INPUT TIMINGS
-
40
100
15
-
tos
Data Set-up Time
30
tOH
Data Hold Time
10
twc
Write Cycle Time
80
twpw
Write Pulse Width
65
tWR
Write Recovery Time
10
80
10
20
-
140
120
ns
ns
ns
ns
ns
tWEF
Write High to EF High
-
60
-
60
-
60
ns
tWFF
Write Low to FF Low
-
60
60
-
60
ns
tWF
Write Low to Transitioning HF, AEF
-
80
-
100
-
140
ns
tWPF
Write Pulse Width After FF High
65
-
80
-
120
-
ns
SERIAL OUTPUT TIMINGS
tSOHZ
soep Rising
Edge to SO at High Z(1)
5
20
5
25
5
35
ns
tSOLZ
SOCP Rising Edge to SO at Low Z(1)
5
22
5
30
5
35
ns
tsoPO
soep Rising
35
ns
tsox
-
22
-
30
SOX Set-up Time to SOCP Rising Edge
5
5
-
ns
Serial In Clock Width High/Low
10
-
5
tsocw
-
15
-
ns
tSOCEF
soep Rising
-
30
ns
60
-
65
ns
tSOCF
SOCP Rising Edge to HF, AEF, High
50
-
30
SOCP Rising Edge to FF High
-
30
tSOCFF
60
-
65
ns
tREFSO
Recovery Time SOCP After EF High
65
-
80
-
120
-
ns
100
-
140
120
-
ns
80
ns
Edge to Valid Data on SO
Edge (Bit 0 - Last Word) to EF Low
50
15
-
RESET TIMINGS
tRSC
Reset Cycle Time
80
tRS
Reset Pulse Width
65
tRSS
Reset Set-up Time
65
tRSR
Reset Recovery Time
15
-
20
-
20
-
tRSF1
Reset to EF and AEF Low
-
80
-
100
-
140
ns
tRSF2
Reset to HF and FF High
-
80
-
100
-
140
ns
tRSQL
Reset to Q Low
50
-
ns
50
-
105
Reset to Q High
-
65
tRSQH
ns
120
-
ns
20
-
ns
80
65
120
105
ns
ns
ns
RETRANSMIT TIMINGS
tRTC
Retransmit Cycle Time
80
-
100
tRT
Retransmit Pulse Width
65
80
tRTS
Retransmit Set-up Time
65
tRTR
Retransmit Recovery Time
15
-
-
140
120
ns
20
-
-
80
-
120
ns
80
-
120
ns
-
120
-
ns
80
DEPTH EXPANSION MODE TIMINGS
tXOL
ReadlWrite to XO Low
-
65
tXOH
ReadlWrite to XO High
-
65
tXI
XI Pulse Width
65
tXIR
XI Recovery Time
10
tXIS
XI Set-up Time
15
-
NOTE:
1. Guaranteed by design minimum times, not tested.
80
10
15
10
15
ns
ns
2751 tbl08
5.7
6
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
1.1K.o.
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
OU1put Load
D.U.T.---.-....
680.0.
See Figure A
30pF*
2751 tbl 09
2751 dlW 03
or equivalent circuit
Figure A. Ouput Load
'Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
Parallel Data Input
The data is written into the FIFO in parallel through the
00-8 input data lines. A write cycle is initiated on the falling
edge of the Wri~(W) signal provided the Full Flag (FF) is not
asserted . .!!!.he W signal changes from HIGH-to-LOW and the
Full-Flag (FF) is already set, the write line is inhibited internally
from incrementing the write pointer and no write operation
occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. The data is written to the RAM at the write
pointer. On the rising edge of W, the write pointer is
incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of soep providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next
data word is inhibited from moving to the output register and
being clocked out by soep. NOTE: soep should not be
clocked once the last bit of the last word has been clocked out.
If it is, then two things will occur. One, the SO pin will go highZ and two, soep will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that
isthe first bit will be DO, then 01 and so on uptothe serial word
width. The serial word width must be programmed by connecting the appropriate Data Set line (04, 06, 07 or 08) to the
NR input. The Data Set lines are taps off a digital delay line.
Selecting one of these taps, programs the width of the serial
word to be read and shifted out.
~-------------------------tRSC------------------------~
~------------------tRS-----------------4~
w
SOCP
Q4, 06, 07, Os
2751 drw 04
Figure 1. Reset
5.7
7
10T72131, 10T72141
CMOS PARALLEL·TO·SERIAL FIFO 2048 x 9·BIT & 4096
x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
twc
w ~r-
,
-k-
jf'-
1\
1\
twpw
tWR
II
Do-a
"\J
~
tos
r
-r
tOH
2751 drw 05
Figure 2. Write Operation
n-1
\'----
SOCP
sox
SO (2)
27~1
drw OG
~----tsoPO
Figure 3. Read Operation
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (EF = low) and the Next Active Device in Width Expansion Mode.
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
JYV\
SOCP
w
FIRST WRITE
n-1
FF
Figure 4. Full Flag from Last Write to First Read
5.7
2751 drw 07
8
10T72131,10T72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
LAST READ
x 9-BIT & 4096 X 9-BIT
NO READ
SOCP
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST WRITE
FIRST READ
(1)
VALID
SO
2751 drw 08
NOTE:
1. SOCP should not be clocked until EF goes high.
Figure 5. Empty Flag from Last Read to First Write
DATA IN
----~*~-------------------------------------------\~------------------(
tWEF
EF
socp
(1)
SO
2751 drw 09
NOTE:
1. SOCP should not be clocked until EF goes high.
Figure 6. Empty Boundary Condition Timing
5.7
9
10T72131,10T72141
CMOS PARALLEL·TO·SERIAL FIFO 2048 X 9·BIT &. 4096 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOCP
IN
DATA IN
so
DATAoUT
VALID
2751 drw 10
Figure 7. Full Boundry Condition Timing
w
t___---II
HALF-FULL (1/2)
HALF-FULL +1
HF
HALF·FULL
tWF
SOCP
tWF
AEF
AEF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST FULL (7/8 FULL + 1)
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
2751 drw 11
Figure 8. Half Full, Almost Full and Almost Empty Timings
5.7
10
10172131,10172141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~-------------------------------------------------------tRTC--------------------------------------------------~
~--------------------------------tRT-------------------------------------~
NOTE:
1. EF, AEF,HF and FF may change status during Retransmit, but flags will be valid at tRTC.
2751 drw 12
Figure 9. Retransmit
WRITE TO LAST PHYSICAL LOCATION
w
READ FROM LAST
PHYSICAL LOCATION
I,------t'\
LAST
LAST -1
SOCP
tXOH
2751 drw 13
Figure 10. Expansion-Out
w
tXIS
Read from first
physical location
SOCP
2751 drw 14
Figure 11. Expansion-In
5.7
11
10172131,10172141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Data Set lines (04, 06, 07, 08) go low and a new serial word
is started. The Data Set lines then go high on the equivalent
soep clock pulse. This continues until the a line connected
to NR goes high completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of soep.
Single Device Configuration
In the standalone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the soep clock, all of the
PARALLEL DATA IN
~
DO-7
SOCP
SERIAL OUTPUT CLOCK
Vee
SO
SOX
NR
I
Q4
Q6 Q7 Qs
Xi
SERIAL DATA OUTPUT
GND
I I I I
SOCP
1
\\--_ _ _ _ I
''-
\ ' - - -_ _- - - 1
I
Q6 , " - - - -_ _ _- - - - - J
..--1
III
Q7'~________________~;---\~______________~~
NR~
r-\
\~.----------------~I
\~
________________~~
2751 drw 15
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
Inputs
Mode
Internal Status
Outputs
RS
FLIRT
XI
Read Pointer
Write Pointer
AEF, EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
ReadlWrite
1
1
0
Increment(1)
Increment(1)
X
X
NOTE:
HF
X
2751 tbl10
1. Pointer will increment if appropriate flag is HIGH.
5.7
12
10T72131,10T72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9·81T & 4096 X 9·81T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
connected tothe SOX input of the next device goes HIGH, the
Do of that device goes HIGH, the cascading from one device
to the next. The Data Set line of the most significant bit
programs the serial word width by being connected to all NR
inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit-bus.
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW·to·H IGH clock edge of soep, all lines go
LOW. Just as in the standalone case, on each corresponding
clock cycle, the equivalent Data Set line goes HIGH in order
of least to most significant. When the Data Set line which is
PARALLEL DATA IN
1S-BITS WIDE
f9,
I
SO
SERIAL OUTPUT CLOCK
G~D
I
SERIAL DATA
OUTPUT
XI
DO·8
SOCP
FIFO #1
NR
•I
r
o
08
I
I
10
1
GNi
XI
DO-6
SO
SOX
Vee
7
SOCP
FIFO #2
SOX
NR
!
14
06
~
15
~
SOCP~
as OF FIFO #1 AND"""""\.
SOX OF FIFO #2
/
\.I....-----i't(~ _ _ _- - - J
06 OF FIFO #2 AND"""""\.
NR OF FIFO #1 AND
FIFO #2
\.
/
I....-----i't(~------------i.'t(~-----J
2751 drw 16
Figure 13. Width Wxpanslon for 16·blt Parallel Data In. The Parallel Data In Is tied to 00-8 of FIFO #1 and 00-6 of FIFO #2.
5.7
13
10172131,10172141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72131/41 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 14 demonstrates Depth Expansion using three
IDT72131/41. Any depth can be attained by adding additional
IDT72131/41 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
~
~
soep
~
XI
SO
soep
NR
I
r
W
-
XO
1
Q7
00-7
W ;4--<
SO
soep
I
r
XO
1
Q7
NR
~~
00-7
FIFO #3
IDT72141
FURT
SO
I
~
~~
FIFO #2
IDT72141
XI
~
00-7
-
Vec
SOX
~~
00-7
FIFO #1
IDT72141
FURl'
~
-c..
5.
XI
SOX
so
4.
All other devices must have FL in the high state.
The Expansion Out (XO) Bin of each device must be
tied to the Expansion In (XI) pin of the next device.
External logic is needed to ~nerate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must
be set to generate the correct composite FF or Ell..
The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
1
-FURT
SOX
2.
3.
W
XO
soep
Q7
NR
~
-l
I
r
2751 drw 17
Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
outputs
Internal Status
Mode
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset-First
Device
a
a
(1 )
Location Zero
Location Zero
a
1
Reset-All
Other Devices
a
1
(1 )
Location Zero
Location Zero
a
1
ReadlWrite
1
X
(1 )
X
X
X
X
NOTES:
2751 tblll
1. Xi is connected to XO of previous device.
2. RS = Reset Input, FLIRT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output,
5.7
Xi = Expansion Input.
14
G
CMOS SERIAL-TO-PARALLEL FIFO
2048 X 9-BIT
4096 x 9-BIT
IDT72132
IDT72142·
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift™ serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CEMOSTM
technology
• Available in a 28-pin ceramic, plastic DIP and 32-pin
plastic leaded chip carrier (PLCC) packages
• Military product compliant to MIL-STO'-883, Class B
The IOT72132172142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial communications applications, tapeldiskcontrollers, and local area
networks (LANs). The IOT72132/72142 can be configured
with the lOTs parallel-to-serial FIFOs (IOT72131172141) for
bidirectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IOT72132172142 c~ lOTs unique
Flexshift serial expansion logic (SIX, NW) makes width
expansion possible with no additional components. These
FIFOswili expand to a variety of word widths including 8, 9,16,
and 32 bits. The IOT72132/142 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost
Empty (1/8) flags signal memory utilization within the FIFO.
The IOT72132/72142 is fabricated using lOTs high-speed
submicron CEMOS technology. Military grade product is
manufactured in compliance with the latest revision of
MIL-STO-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SI
~
FLAG
LOGIC
NEXT WRITE
POINTER
EF
AEF
IHF
FF
RAM ARRAY
2048 x 9
4096 x 9
2752 drw 01
CEMOS and Flexishift are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC-2030/3
©1992 Integrated Device Technology, Inc.
5.8
10172132, 10172142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
Name
1/0
Description
SI
Serial Input
I
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus 07, DB determine which device stores the data.
RS
Reset
I
When RS is set low, internal READ and WRITE pOinters are set to the first location of the RAM
array. HFand FFgo high, andAEF, and EFgo low. A reset is required before an initial WRITE
after power-up. R must be high during an RS cycle.
NW
Next Write
I
To program the Serial In word width, connect NW with one of the Data Set pins (07, DB).
SICP
Serial Input Clock
I
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
R
Read
I
When READ is low, data can be read from the RAM array sequentially, in~endent of SICP.
In orderfor READ to be active, EF must be high. When the FIFO is empty (EF-Iow). the internal
READ operation is blocked and QO-QB are in a high impedance condition.
FURT
First Loadl
Retransmit
I
This is a dual ~pose input. In the single device configuration (XI grounded), activating
retransmit (FURT-Iow) w!!!settheinternal READ pointertothefirstlocation. There~ no effect
on the WRITE pointer. R must be high and SICP must be low before setting FURT low.
Retransmit is not possible in depth expansion. In the depth expansion configuration,
FURT grounded indicates the first activated device.
XI
Expansion In
I
In the single device configuration, XI is grounded. In depth expansion or daisy chain
expansion, XI is connected to XO (expansion out) of the previous device.
SIX
Serial Input
Expansion
I
In the Expansion mode, the SIX pin of the least significant device is tied high. The SIX pin of
all other devices is connected to the 07 or DB pin of the previous device. For single device
operation, SIX is tied high.
OE
Output Enable
I
When OE is set low, the parallel output buffers receive data from the RAM array. When OE
is set high, parallel three state buffers inhibit data flow.
Qo-QB
Output Data
0
Data outputs for 9-bit wide data.
FF
Full Flag
0
When FF goes low, the device is full and data must not be clocked by SICP. When FF is high,
the device is not full. See the diagram on page 7 for more details.
EF
Empty Flag
Almost-Full Flag
0
When EF goes low, the device is empty and further READ operations are inhibited. When EF
is high, the device is not empty.
AEF
Almost-Emptyl
Half-Full Flag
0
When AEF is low, the device is empty to 1/8 full or 7/8 to completely full. When AEF is high,
the device is greater than 1/8 full, but less than 7/8 full.
XO/HF
Expansion OuV
0
This is a dual purpose output. In the single device configuration (XI ground~, the device is
more than half full when HF is low. In the depth expansion configuration (XO connected to
XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array
is filled.
07, DB
Data Set
0
The appropriate Data Set pin (07, DB) is connected to NWto program the Serial In data word
width. For example: 07 - NW programs a 8-bit word width, DB - NW programs a 9-bit word
width, etc.
Vee
Power Supply
Single Power Supply of 5V.
GND
Ground
Three grounds at OV.
2752tbiOl
STATUS FLAGS
Number of Words in FIFO
-
10172132
10172142
FF
AEF
0
0
H
L
HF
H
EF
L
1-255
1-511
H
L
H
H
H
256-1024
512-2048
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2752tbl02
5.8
2
III
10T72132, 10T72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9-81T & 4096 X 9-81T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
GNO
27
Vee
07
Xi
26
Os
NW
2S
LJLJLJIILJLJLJ
'a_~_~_~---":1oI:...-. .
I
3
8
7
0
(MSB)
C>OOa
0000
Full Offset (LSB)
Default Value 007H
1~_2_(_~0_S:_)-tI ~>a
0
8
3
0
(MSB)
0000
I
2655 drw 05
Figure 3. Offset Register Location and Default Values
5.10
I
0
7
Full Offset (LSB) Reg.
Default Value 007H
1_(M_:_oB_)--I1
0
7
IDT72421172201172211172221172231172241 CMOS PARALLEL SyncFIFON (Clocked FIFO)
64 x 9-8IT. 2!56 x 9-8IT. !512 x 9-8IT. 1024 x 9-8IT. 2048 x 9-81T & 4096 x 9-81T
OUTPUTS:
Full Flag (FF) - The Full Flag (FF) will go low. inhibiting
further write operation. when the device is full. If no reads are
performed after Reset (RS). the Full Flag (FF) will go low after
64 writes for the IDT72421. 256 writes for the IDT72201. 512
writes for the IDT72211. 1024 writes for the IDT72221. 2048
writes for the IDT72231. and 4096 writes for the IDT72241.
The Full Flag (FF) is synchronized with respect to the LOW~
'to-HIGH transition of the write clock (WCLK).
Empty Flag (EF) - The Empty Flag (EF) will go low.
inhibiting further read operations. when the read pointer is
equal to the write pointer. indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag (PAF) - The
Programmable Almost-Full Flag (PAF) will go low when the
FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS). the Programmable Almost-Full
Flag (PAF) will go low after (64-m) writes for the IDT72421.
(256-m) writes for the IDT72201. (512-m) writes for the
IDT72211. (1 024-m) writes for the IDT72221. (2048-m) writes
MILITARY AND COMMERCIAL TEMPERATURE RANGES
forthe IDT72231. and (4096-m) writes for the IDT72241. The
offset "m" is defined inthe Full offset registers.
-If there is no Full offset specified, the Programmable
Almost-Full Flag (PAF) will go low at Full-7 words.
The Programmable Almost-Full Flag (PAF) is synchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
Programmable Almost-Empty Flag (PAE) - The
Programmable Almost-Empty Flag (PAE) will go low when the
read pointer is "n+ 1" locations less than the write pointer. The
offset "n" is defined in the Empty offset registers. If no reads
are performed after Reset the Programmable Almost-Empty
Flag (PAE) will go high after "n+ 1" for the IDT72421172201!
72211172221172231172241.
If there is no Empty offset specified, the Programmable
Almost-Empty Flag (PAE) will go low at Empty+7 words.
The Programmable Almost-Empty Flag (PAE) is
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).
Data Outputs (00 - as) data.
Data outputs for a 9-bit wide
TABLE 1: STATUS FLAGS
NUMBER OF WORDS IN FIFO
72421
72201
72211
0
1 to n(l)
0
1 to n(l}
0
1 to n(1)
(64-m)(2) to 63
(n+1) to (256-(m+1))
(256-m) (2) to 255
(n+1) to (512-(m+1))
(512-m)(2) to 511
64
256
512'
(n+1) to (64-(m+1))
1=F
ro
m
EF
H
H
H
H
H
L
H
H
L
L
L
L
H
H
H
H
H
H
H
L
2655tbl10
NUMBER OF WORDS IN FIFO
72221
72231
72241
~
m
m
0
0
0
H
H
L
L
1 to n(l)
1 to n(l)
1 to n(l)
H
H
L
H
(n+1) to (1024-(m+1))
(n+1) to (2048-(m+1))
(n+1) to (4096-(m+1))
H
H
H
H
(1024-m)(2) to 1023
(2048-m)(2) to 2047
(4096-m)(2) to 4095
H
L
H
H
4096
L
L
H
1024
NOTES.
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
2048
EF
H
2655tbl11
5.10
8
IDT72421n2201n2211n2221n2231n2241 CMOS PARALLEL SyncFIFOThi (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9oBIT, 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tRS------------~~
--------~~-------tRSR------~*
--------~~-----tRSR------~*
--------~~-----tRSR------~*
WEN2ILD
(1)
~~~~~~~L+~-----------------------+-------------------'
Qo- Q8
2655 d/W 06
NOTES:
1. Holding WEN2ILD high during reset will make the pin act as a second write enable pin. Holding WEN2ILD low during reset will make the pin act as a load
enable tor the programmable flag offset registers.
2. After reset, the outputs will be low it OE = 0 and tri-state it OE = 1.
3. The clocks (RCLK, WCLK) can be free-running turing reset.
Figure 4. Reset Timing
5.10
9
IDT72421n2201n2211n2221n2231n2241 CMOS PARALLEL SyncFIFOTM (Clocked FIFO)
64 x 9·BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9oBIT, 2048 x 9-BIT & 4096 x 9-BIT
t--------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tcLK-----~~
WCLK
Do - 08
NO OPERATION
WEN2I
NO OPERATION
(If Applicable)
~-----tWFF---~~
~-----tWFF---~~
tSKEW1(1)
RCLK
2655 drw 07
NOTE:
1. ISKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
.
Figure 5. Write Cycle Timing
5.10
10
IDT72421n2201n2211n2221n2231n2241 CMOS PARALLEL SyncFIFO'" (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9-BIT, 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tCLK----------~~
RCLK
NO OPERATION
~------tREF----~~
EF
VALID DATA
00-08
tOHZ
OE
tSKEW1(1)
WCLK
WEN1
WEN2
,,~-----------------------------------------------------------'/
2655 drwoa
NOTE:
1. tSKEWl is the minimum time between a rising WCLK edge and a rising RCLK ed~ for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Tim ing
5.10
11
II
IDT72421n2201n2211n2221n2231n2241 CMOS PARALLEL SyncFIFO"" (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9-BIT, 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
00- 08
WEN1
WEN2
(If Applicable)
....-----tFRd 1) - - - - - . J
RCLK
EF
tA
00- 08
Do
01
tOLZ
____________________________~
~.----------tOE-----~
2655 drw 09
NOTE:
1. When tSKEW1 ~ minimum specification, tFRL = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
5.10
12
IDT72421f72201172211172221172231172241 CMOS PARALLEL SyncFIFOTN (Clocked FIFO)
64 x 9-BIT, 256 x 9oBIT, 512 x 9-BIT, 1024 x 9oBIT, 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do - 08
FF
WEN2
(If Applicable)
RCLK
LOW
00-08
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.10
13
IDT72421172201172211172221172231172241 CMOS PARALLEL SyncFIFOTN (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9oBIT, 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
00-08
WEN2
(If Applicable)
(1)
~-------------tFRL------~~
RCLK
EF
REN1,
REN2
LOW
_ _~1.....----_
Qo· 08
DATA IN OUTPUT REGISTER
=>[<
DATA READ
2655 drw 11
NOTE:
1. When tSKEW1 ;:: minimum specification, tFRL maximum = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEWl
The Latency Timings apply only at at the Empty Boundary (8= = LOW).
Figure 9. Empty Flag Timing
5.10
14
IDT72421f72201f72211f72221f72231f72241 CMOS PARALLEL SyncFIFOThl (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9oBIT, 2048 x 9-BIT & 4096 x 90BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tENS~
WEN2
(If Applicablel--_ _ _-4....L......L....J
(1)
PAF
Full - (m+1) words in FIFO
RCLK
REN1,
REN2
2655 drw 12
NOTES:
1. PAF offset = m.
2. 64 - m words in for 10T72421, 256 - m words in FI FO for 10T72201 , 512 - m words for 10T72211 , 1024 - m words for 1OT72221 , 2048 - m words for IOT72231 ,
4096 - m words for 10T72241.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes low.
5.10
15
IDT72421172201172211172221172231172241 CMOS PARALLEL SyncFIFO'l>l (Clocked FIFO)
64 X 9-8IT, 2!56 X 9-81T, !512 X 9-8IT, 1024 X 9-81T, 2048 X 9-81T & 4096 X 9-8IT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tENS7::.\
C
tENH
WEN2
(If Applicable~_ _ _....4.....4.-'-.J
(1)
PAE
n words in FIFO
n+ 1 words in FIFO
RCLK
2655 drw 13
NOTES:
1. PAE offset .. n.
2. tSKEw21s the minimum time bet'Neen a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time bet'Neen the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words In the FIFO when PAE goes low.
Figure 11. Programmable Empty Flag Timing
5.10
16
IDT72421172201172211172221172231172241 CMOS PARALLEL SyncFIFOThi (Clocked FIFO)
64 x 9·BIT, 256 x 9·BIT, 512 x 9·BIT, 1024 x 9oBIT, 2048 x 9·BIT & 4096 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
LD
WEN1
Do·D7
2655 drw 14
Figure 12. Write Offset Registers Timing
II
RCLK
Qo· Q7
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
2655 drw 15
Figure 13. Read Offset Registers Timing
5.10
17
10T72421(72201(72211(72221(72231(72241 CMOS PARALLEL SyncFIFO"" (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9-BIT, 2048 x 9-BIT & 4096 x 9-BIT
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION· A single IDT724211
72201/72211/72221/72231172241 may be used when the
application requirements are for 64/256/512/1024/2048/4096
words or less_ When the IDT72421/72201/722111722211
MILITARY AND COMMERCIAL TEMPERATURE RANGES
72231172241 are in a Single Device Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure
14)_lnthisconfiguration,theWriteEnable2/Load(WEN2ILD)
pin is set low at Reset so that the pin operates as a control to
load and read the programmable flag offsets_
l
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE 1 (WEN1)
lOT
724211
722011
722111
722211
722311
72241
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (Do - Os)
FULL FLAG (Ff)
PROGRAM M..ABLE ALMOST FULL (PAF)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (bE)
DATA OUT (OJ - Os)
EM PTY FLAG (Ef)
PROGRAMMABLE ALMOST EMPTY (PAE)
1
READ ENABLE 2 (REN2)
2655 drw 16
Figure 14. Block Diagram of Single 64 x 9/256 x 9/512 x 9/1024 x 9/2048 x 9/4096 x 9 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION· Word width may
be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should
be created for each of the end-point status flags (EF and FF).
The partial status flags (AE and AF) can be detected from any
one device. Figure 15 demonstrates a 18-bit word width by
using two IDT72421172201/72211172221/72231172241s. Any
word width can be attained by adding additional IDT724211
72201172211/72221172231172241 s.
When the IDT72421/72201/72211172221/72231172241
are in a Width Expansion Configuration, the Read Enable 2
(REN2) control input can be grounded (see Figure 15)_ In this
configuration, the Write Enable 2ILoad (WEN2/LD) pin is set
low at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
RESET (RS)
RESET (RS)
DATA IN (D)
/18
I
/9
J
,
,9
I
WRITE CLOCK (WCLK)
WRITE ENABLE1 (WENf)
WRITE ENABLE2ILOAD (WEN2ILD)
-
~
lOT
72421/
72201/
724211
FULL FLAG (FF) #1
I
FULL FLAG (FF) #2
72201/
72211/
722111
722211
72221/
PROGRAMMABLE (PAF)
72231/
72241
722311
1
READ ENABLE (REr-·j)
OUTPUT ENABLE (bE)
lOT
----.
-
READ CLOCK (RCLK)
I
19
72241
1
READ ENABLE 2 (REN2)
PROGRAMMABLE~AE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
1_ 9 DATA OUT (0) ,18
I
I
I
READ ENABLE 2 (REN2)
2655 drw 17
Figure 15. Block Diagram of 64 x 18/256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO
Used In a Width Expansion Configuration
5.10
18
IDT72421n2201n2211n2221n2231n2241 CMOS PARALLEL SyncFIFO'" (Clocked FIFO)
64 x 9-BIT, 256 x 9-BIT, 512 x 9-BIT, 1024 x 9-BIT, 2048 x 9-BIT & 4096 x 9-BIT
DEPTH EXPANSION· The IOT72421/7221/72211/722211
72231/72241 can be adapted to applications when the requirements are for greater than 64/256/512/1024/2048/4096
words. The existence of two enable pins on the read and write
port allow depth expansion. The Write Enable 21Load pin is
used as a second write enable in a depth expansion configuration thus the Programmable flags are set to the default
values. Depth expansion is possible by using one enable
input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical
application would have the expansion logic alternate data
MILITARY AND COMMERCIAL TEMPERATURE RANGES
access from one device to the next in a sequential manner.
The IOT7242117221172211172221172231172241 operates in
the Depth Expansion configuration when the following conditions are met:
1. The WEN2I LO pin is held high during Reset so that this pin
operates a second Write Enable.
2. External logic is used to control the flow of data.
Please see the Applicatioin Note" DEPTH EXPANSION OF
lOT'S SYNCHRONOUS FIFOs USING THE RING COUNTER
APPROACH" for details of this configuration.
II
5.10
19
f;)
CMOS PARALLEL
SyncFIFOTM (CLOCKED FIFO)
512 X 18-81T & 1024 X 18-81T
Integrated Device Technology, Inc.
FEATURES
•
•
•
•
•
•
•
•
•
512 X 18-bit and 1024 x 18-bit memory array structures
20ns read / write cycle time
Easily expandable in width
Read and write clocks can be independent or coincident
Dual-port zero fall-through time architecture
Programmable almost-empty and almost-full flags
Empty and Full flags signal FIFO status
Half-Full flag capability in a single device configuration
Output enable puts output data bus in high impedance
state
• Produced with advanced submicron CEMOSTM
technology
• Available in a 68-lead flatpack (FP), pin grid array (PGA),
and plastic leaded chip carrier (PLCC)
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION
The IDT72215L and IDT72225L are very high speed, lowpower first-in, first-out (FIFO) memories with read and write
co~trols. The IDT72215L has a 512 x 18-bit memory array,
while the IDT72225L has a 1024 x 18-bit memory array.
IDT72215L
IDT72225L
These FIFOs are applicable for a wide variety of data buffering
needs, such as optical disk controllers, local area networks
(LANs), and interprocessor communication.
Both FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK) and a data
Input enable pin (WEN). Data is written into the Synchronous
:-IFO on every clock when WEN is asserted. The output port
IS controlled by another clock pin (RCLK) and another enable
pin (REN). The read clock can be tied to the write clock for
single clock operation or the two clocks can run independent
of one another for dual clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the
output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
~ull (FF), and two programmable flags, Almost-Empty
(PAE) and Almost-Full (PAF). The loading of the programmable flag offsets can be controlled by a si mple state machine
and is initiated by asserting the load pin (LD). A Half-Full flag
(HF) is also available.
The IDT72215U72225L is fabricated using IDT's high
speed submicron CEMOSTM technology. Military grade product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
BE
CEMOS is
Qo.Q17
2761 drw 01
a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·2050/1
©1992 Integrated Device Technology. Inc.
5.11
IDT72215U72225L CMOS
SYNCHRONOUS FIFO 512
X
18·BIT and 1024 X 18·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vee
11
03
GND
00
HF
GND Vee
WEN GND
III1IIIII IIII
~"""""
10
09
GND
06
04
02
Vee
01
FF
PAF
GND well( PAE
05
D2
Dl
07
Vee
D4
D3
07
GND
oB
D6
D5
06
010
09
GND
D7
05
all
Vee
Vee
DB
04
GND 012
03
014
02
Vee 015
01
A
013
Pin 1 Designator
Dl0
.,/
016
Vee
GND
liS
GND
017
EF
Vee
OE
B
C
D
E
F
[])
RCLK D17
REN
GND
G
H
D16
PIN
015
GNO
'~
016
017
vee
~
GNO
vee
~
DE
05
1=
1=
1=
GNO
010
:]14
56[:
a12
all
Dll
D14
D13
:]15
55 [:
:]18
54
c:
Vee
08
:]17
53 [:
al0
52[:
Qg
J68-1
:]18
07
:] 19
51
06
:] 20
SOC as
D9
D12
09
Vee
C
GNO
05
:] 21
4g[:
D4
:J 22
48C
Vee
03
:] 23
47[:
ae
02
:] 24
46C
as
01
:J 25
45[:
a7
GNO
D15
~ ~
I~
~ ~ ~ ~It ~ ~ 8 5 ~
PLCC
TOP VIEW
66 65 6:63 62 61 60 59 58 57 56 55 54 53
52~
51
50
6
46
7
45
vee
44
R'F
43
42
~
10
11
41
40
39
15
16
17
GND
m
vee
GND
38
we;I
37
36
WCCR
GNO
34V
35
~ 181920 21 22 23 24 2~26 2728 293031 3233
2761 drw03
vee
GND
F68-1
a·a ~
03
02
01
00
13
14
017
016
015
a13
2
47
GNO
......
68 [:
3
48
12
I I I I1I1
57 [:
4
5
9
I
:]13
011
5
49
8
III
:]12
012
6
3
4
Rm
ReLK
6~
II
Vee
:]11
7
2761 drw 02
{l68
t:
3:
1
(080-OB7)
::~
>~
-I~
(')
l>
-r
tD-
O
c:
(1):::/
o~o
r:::/
0
0
Port B
9
(DAo-DA7,DAt6)
DBo-DBa
~
U'I
,,
'1
Write
Parity Error
,
t-
Reset
DMA
Control
j.--
-~
RS t
REO"
ACK"
ClK
::
i=
FlGA*
FlGB*
FlGc*
FlGD*
16
(DAo-DAtS)
----,
.-
Status
__________
Configuration 0
~
:c
<
~~4----------------------------------------~
~
o
g
Configuration 1
---------Configuration 2
---------Configuration 3
----------
::
::
m
:c
o
,
_~o~~g_u!a.!i~~ ~
Configuration 5
5>
r
-----------------------------------------~----i-----~
---------,,
,,
Configuration 6
____________________
____________________
---------Configuration 7
~
-I
m
::
"C
m
~---J
:c
~
NOTES:
"'"
:c
:c
>
z
c;)
m
(0) Can be programmed either active high or active low in intemal configuration registers.
(t) Available as a pin on the IDT7251 0/520. Accessible on all parts through internal registers.
(tt) Can be programmed through an internal configuration register to be either an input or an output.
2669 drw 04
m
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
lOT's BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the lOT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO's 9-bit
bypass path.
The BiFIFOs can be used in three different bus configurations: 18 bits to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits.
One BiFIFO can be used for the 18- to 9-bit configuration,
and two BiFIFOs are required for 36- to 9-bit or 36- to 18-bit
configurations. Bits 11 and 12 of Configuration Register 5
determine the BiFIFO configuration (see Table 11 for
Configuration Register 5 format).
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFOs. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed in processor interface mode, the Port B interface
pins are inputs driven by the second processor. If a peripheral device is connected to the BiFIFOs, Port B is programmed to peripheral interface mode and the interface pins
are outputs.
18- to 9-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 9-bit processor or a 9-bit peripheral.
Bits 11 and 12 of Configuration Register 5 should be set to
00 for a stand-alone configuration. Figures 1 and 2 show the
BiFIFO in 18- to 9-bit configurations for processor and
peripheral interface modes respectively.
36- to 9-bit Configurations
Two BiFIFOs can be hooked together to create a 36-bit to
9-bit configuration. This means that a 36-bit processor can
talk to a 9-bit processor or a 9-bit peripheral. Both BiFIFOs
are programmed simultaneously through Port A by placing
one command word on the most significant 16 data bits and
one command word on the least significant 16 data bits
(parity bits should be ignored).
One BiFIFO must be programmed as the master device
and the other BiFIFO is the slave device. Bits 11 and 12 of
Configuration Register 5 are set to 10 for the slave device
and 11 for the master device. The first two 9-bit words on
Port B are read from or written to the slave device and the
next two 9-bit words go to the master device.
When both BiFIFOs are in peripheral interface mode, the
Port B interface pins of the master device are outputs and
this BiFIFO controls the bus. The Port B interface pins of the
slave device are inputs driven by the master BiFIFO. Two
BiFIFOs are connected in Figure 4 to create a 36- to 9-bit
peripheral interface.
The two BiFIFOs shown in Figure 3 are configured to
connect a 36-bit processor to a 9-bit processor.
36-BIT PROCESSOR to 18-BIT PROCESSOR CONFIGURATION
Processor
A
Processor
B
2669 drw05
Figure 1. 36- to 18·BIt Processor Interface Configuration
NOTE:
1. !!pper B!BFO only is used in 18- to 9-bit configuration. Note that Cntl A refers to CSA, AI, Ao, RfiiA and DSA; Cntl B refers to RfiiB and DSB or
RB and WB.
5.15
5
II
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
36-81T PROCESSOR to 18-81T PERIPHERAL CONFIGURATION
lOT
BiFIFO
....H~_-t....._ _ DMAorSystem
Clock
Peripheral
Controller
Processor
Address
Cnt!
ACK
REO
Control
Data
en
:l
.c
Data
lOT
BiFIFO
1/0
Data
RAM
2669 drw 06
Figure 2. 36· to 18·Blt Peripheral Interface Configuration
NOTE:
1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that Cntf A refers to CSA, Al, Ao, RiWA and DSA; Cntf B refers to RiWs and DSs or
RS andWs.
36- to 18-bit Configurations
In a 36- to 18-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 16
data bits to each device with the 4 parity bits ignored.
80th 8iFIFOs must be programmed into stand-alone mode
for a 36-bit processor to communicate with an 18-bit processor or an 18-bit peripheral. This means that bits 11 and 12 of
Configuration Register 5 must be set to 00.
This configuration can be extended to wider bus widths
(54- to 27-bits, 72- to 36-bits, ... ) by adding more BiFIFOs to
the configuration. Figures 1 and 2 show multiple BiFIFOs
configured for processor and peripheral interface modes
respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B interface
controls are inputs. Both REO and ClK pins should be pulled
lOW to ensure that the set-up and hold time requirements for
these pins are met during reset. Figures 1 and 3 show
BiFIFOs in processor interface mode.
Peripheral Interface Mode
If Port B is connected to a peripheral controller, all BiFIFOs
in the configuration must be programmed in th~eriph~1
interface mode. To assure fixed high states for RB and WB
before they are programmed into an output, both pins should
be pulled-up to Vcc with 10K resistors.
If the BiFIFOs are in stand-alone configuration mode
(18-to 9-bit, 36-to 18-bit, ... ), then the Port B interface pins are
all outputs. Of course, only one set of Port 8 interface pins
should be used to control a single peripheral device, while the
other interface pins are all ignored. Figure 2 shows standalone configuration BiFIFOs connected to a peripheral.
In a 36- to 9-bit configuration, the master device controls
the bus. The Port B interface pins of the master device are
outputs and the interface pins of the slave device are inputs.
A 36- to 9-bit configuration of two BiFIFOs connected to a
peripheral is shown in Figure 4.
Port A Interface
The 8iFIFO is straightforward to use in microprocessorbased systems because each 8iFIFO port has a standard
microprocessor control set. Port A has access to six resources: the A--7B FIFO, the B--7A FIFO, the 9-bit direct data
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and ReadlWrite pins
determine the resource being accessed as shown in Table 1.
Data Strobe is used to move data in and out of the BiFIFO.
When either of the internal FIFOs are accessed 18 bits of
data are transferred across Port A. Since the bypass path is
only 9 bits wide, the least significant byte with parity
(DAO-DA7, DA16) is used on Port A. All of the registers are 16
bits wide which means only the data bits (DAO-DA1S) are
passed by Port A.
5.15
6
IDTI251, IDTI252, IDTI2510, IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
36-81T PROCESSOR to 9-81T PROCESSOR CONFIGURATION
lOT
BiFIFO
Processor
A
Processor
B
Address
Control
Control
Data
Data
RAM
RAM
2669 drw07
Figure 3. 36- to 9-Blt Processor Interface Configuration
NOTE:
1.
Cntf A refers to CSA, A1, Ao, RiWA and DSA; Cntl B refers to RJWB and DSB or RB and WB.
36-81T PROCESSOR to 9-81T PERIPHERAL CONFIGURATION
lOT
BiFIFO
DMAor
System
Clock
Peripheral
Controller
Processor
Address
Cntl
Control
ACK
REO
Data
Data
1/0
Data
RAM
2669 drw 08
Figure 4. 36- to 9-Blt Peripheral Interface Configuration
NOTE:
1. Cntl A refers to CSA, A1, Ao, RiWA and DSA; Cntf B refers to RiWB and DSB or RB and WB.
5.15
7
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PORT A RESOURCES
COMMAND OPERATIONS
CSA
A1
Ao
Read
Write
0
0
0
B~AFIFO
A~BFIFO
0
0
0
1
9·bit Bypass Path
9·bit Bypass Path
1
0
Configuration
Registers
Configuration
Registers
0
1
Command
Opcode
1
1
Status Register
Command Register
X
X
Disabled
Disabled
0000
0001
0010
0011
0100
0101
0110
0111
1000
2669 Tbl 02
Table 1. Accessing Port A Resources Using CSA, AO, and A1
Bypass Path
The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
. B interface pins are outputs. The bypass path is 9 bits wide in
an 18· to 9-bit configuration or in a 36- to 9·bit configuration.
Only in the 36- to 18-bit configuration is the bypass path 18 bits
wide.
During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register5(see Table 11) issetto 1 for peripheral interface
mode. In a 36- to 9·bit configuration, both Port B data buses
will be active. Data written into Port A will appear on both
master and slave Port B buses concurrently. To avoid Port B
bus contention, thedataon DAo-DA7and DA160fboth BiFIFOs
should be exactly the same. Data read from Port A will appear
on pins DAO-DA7 and DA16 of both BiFIFOs within the same 36bit word.
Command Register
Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration l3ggisters.
The Command Register is written by setting CSA ... 0,
A1 = 1, Ao = 1. Commands written into the BiFIFO have a
4-bit opcode (bit 8 - bit 11) and a 3-bit operand (bit 0 - bit 2)
as shown in Figure 5. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to set the Port B DMA direction, to set the
Status Register format, to modify the Port B Read and Write
Pointers, and to clear Port B parity errors. The command
opcodes are shown in Table 2.
The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.
The Configuration Register address is set directly by the
command operands shown in Table 4.
Intelligent reread/rewrite is performed by changing the Port
B Read Pointer with the Reread Pointer or by changing the
Function
Reset BiFIFO (see Table 3)
Select Configuration Register (see Table 4)
Load Reread Pointer with Read Pointer Value
Load Rewrite Pointer with Write Pointer Value
Load Read Pointer with Reread Pointer Value
Load Write Pointer with Rewrite Pointer Value
Set DMA Transfer Direction (see Table 5)
Set Status Register Format (see Table 6)
Increment in byte for A~B FIFO Read Pointer
(Port 8)
1001
Increment in byte for
(Port 8)
1010
1011
Clear Write Parity Error Flag
8~A
FIFO Write Pointer
Clear Read Parity Error Flag
2669tbl03
Table 2. Functions Performed by Port A Commands
Port B Write Pointer with the Rewrite Pointer. No command
operands are required to perform a reread/rewrite operation.
When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port Bread/write DMA direction operands.
The BiFIFO supports two Status Register formats. Status
Register format 1 gives all the internal flag status, while Status
Register format 0 providesthe data in the Odd Byte Register.
Table 6 gives the operands for selecting the appropriate
Status Register format. See Table 8 for the details of the two
Status Register formats.
Two commands are provided to increment the Port BRead
and Write Pointers in case reread/rewrite is performed.
Incrementing the pointers guarantees that pointers will be on
a word boundary when an odd number of bytes is transmitted
through Port B. No operands are required forthese commands.
When parity check errors occur on Port B, a clear parity
error command is needed to remove the parity error. There
are no operands for these commands.
Reset
...lhe IDT72510 and IDT72520 have a hardware reset pin
(RS) that resets all BiFIFO functions. A hardware reset
requires the following four conditions: Rs and Ws must be
HIGH, RER and REW must be HIGH, LDRER and LDREW
must be LOW, and DSA must be HIGH (Figure 9). After a
hardware reset, the BiFIFO is in the following state: Configuration Registers 0-3 are OOOOH, Configuration Register 4 is set
COMMAND FORMAT
I
15
X
12
X
X
X
11
7
8
X
Command Opcode
X
X
X
o
3
2
x
Command Operand
2669 tbl 04
Figure 5. Format for Commands Written Into Port A
5.15
8
1017251,1017252,10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RESET COMMAND FUNCTIONS
Reset
Operands
SELECT CONFIGURATION REGISTER
COMMAND FUNCTIONS
Function
Operands
000
No Operation
001
Reset B~A FIFO (Read, Write, and Rewrite
Pointers = 0)
010
011
000
Reset A~B FIFO (Read, Write, and Reread
Pointers = 0)
Reset B~A and A~B FIFO
100
Reset Internal DMA Request Circuitry
101
No Operation
110
No Operation
111
Reset All
Function
Select Configuration Register 0
001
Select Configuration Register 1
010
Select Configuration Register 2
011
Select Configuration Register 3
100
Select Configuration Register 4
101
Select Configuration Register 5
110
Select Configuration Register 6
111
Select Configuration Register 7
2669tbl06
Table 4. Select Configuration Register Command Functions.
2669tbl05
Table 3. Reset Command Functions
DMA DIRECTION COMMAND FUNCTIONS
to 6420H, and Configuration Registers 5 and 7 are OOOOH.
Additionally, Status Register format
is selected, all the
pointers including the Reread and Rewrite Pointers are set to
0, the odd byte register valid bit is cleared, the DMA direction
is set to B-7A write, the internal DMA request circuitry is
cleared (set to its initial state), and all parity errors are cleared.
A software reset command can reset A-7B pointers and
the B-7A pointers to 0 independently or together. The request
(REQ) DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is NOT the
same as a software Reset All command. Table 7 shows the
BiF IFO state after the different hardware and software resets.
Operands
a
Function
XXO
Write B~A FIFO
XX1
Read A~B FIFO
2669tbl07
Table 5. Set OMA Direction Command Functions. Command Only
Operates In Peripheral Interface Mode
STATUS REGISTER FORMAT COMMAND
FUNCTIONS
Operands
Function
XXO
Status Register Format 0
XX1
Status Register Formal 1
2669tbiOB
Table 6. Command Functions to Set the Status Register Format
STATE AFTER RESET
Hardware Reset
(RS asserted, IDT72510
& IDT72520 only)
B~A
Configuration Registers 0-3
OOOOH
-
Configuration Register 4
6420H
-
Configuration Register 5
OOOOH
Configuration Register 7
OOOOH
(001)
Status Register format
0
B~A
Read, Write, Rewrite
Pointers
0
0
A~B
0
-
Odd byte register valid bit
DMA direction
clear
B~Awrite
DMA internal request
clear
Parity errors
clear
(010)
Software Reset
B~A and
A~B (011)
-
-
Read, Write, Reread
Pointers
A~B
-
0
clear
-
-
-
Internal
Request
(100)
All (111)
OOOOH
0
-
0
-
0
-
clear
clear
-
-
clear
-
6420H
OOOOH
OOOOH
0
clear
2669tbl09
Table 7. The BiFIFO State After a Reset Command
5.15
9
II
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Status Register
The Status Register reports the state of the programmable
flags, the DMA read/write direction, the Odd Byte Register
valid bit, and parity errors. The Status Register is read by
setting CSA = 0, A1 = 1, Ao = 1 (see Table 1).
There are two Status Register formats that are set by a
Status Register format command. Format 0 stores the Odd
Byte Register data in the lower eight bits of the Status
Register, while format 1 reports the flag states and the DMA
read/write direction in the lower eight bits. The upper eight bits
are identical for both formats. The flag states, the parity errors,
the Odd Byte Register valid bit, and the Status Register format
are all in the upper eight bits of the Status Register. See Table
8 for both Status Register formats.
Configuration Registers
The eight Configuration Register formats are shown in
Table 9. Configuration Registers 0-3 contain the programmable flag offsets for the Almost Empty and Almost Full flags.
These offsets are set to 0 when a hardware reset or a software
reset all is applied. Note that Table 9 shows that Configuration
Registers 0-3 are 10 bits wide to· accommodate the 1024
locations in each FIFO memory of the IDT7252/520. Only 9
least significant bits are used for the 512 locations of the
IDT7251 /510; the most significant bit, bit 9, must be set to O.
Configu ration Register 4 is used to assign the internal flags
to the external flag pins (FlGA-FlGo). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 10. The default condition for Configuration Register
4 is 6420H as shown in Table 7. The default flag assignments
are: FlGo is assigned B~A FUIT, FlGc is assigned B~A
Empty, FlGs is assigned A~B Full, FlGA is assigned A~B
Empty.
Configuration Register 5 isa general control register. The
format of Configuration Register 5 is shown in Table 11. Bit 0
sets t~ntel-3t1e interface (RS, WS) or Motorola-style interface (DSS, R/Ws) for Port B. Bit 1 changes the byte order for
data coming through Port B. Bits 2 and 3 redefine Full and
Empty Flags for reread/rewrite data protection.
Bits 4-9 control the DMAinterface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don't care states. Bits 4 and 5 set the polarity
of the DMA control pins REO and ACK, respectively. An internal clock controls all DMA operations. This internal clock is
derived from the external clock (ClK). Bit 9 determines the
internal clock frequency: the internal clock = ClK or the internal clock = ClK divided by 2. Bit 8 sets whether Rs, Ws, and
DSs are asserted for either one or two internal clocks. Bits 6
and 7 set the number of internal clocks between REO assertion and ACK assertion. The timing can be from 2 to 5 cycles
as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (Rs, Ws,
DSs, RiVJs) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
Bits 11 and 12 set the width expansion mode. For 18- to
9-bit configurations or 36- to 18-bit configurations, the BiFI Fa
should be set in stand-alone mode. For a 36- to 9-bit configuration, one BiFIFO must be in slave mode and the other BiFIFO must be in master mode. The master BiFIFO allows the
first two bytes transferred across Port B to go to the slave
BiFIFO, then the next two bytes go to the master BiFIFO.
Configuration Register 7 controls the parity functions of
Port B as shown in Table 12. Either parity generation or parity
STATUS REGISTER FORMAT 1
STATUS REGISTER FORMAT 0
Signal
Bit
Signal
Bit
0
0
Reserved
1
1
Reserved
2
2
Reserved
3
DMA Direction
4
4
A~B Empty Flag
5
5
A~B Almost-Empty Flag
6
6
B~A
Full Flag
Almost-Full Flag
3
Odd Byte Register
7
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format
=0
7
B~A
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format
A~B Full Flag
=1
12
A~B Full Flag
12
13
A~B Almost-Full Flag
13
A~B
14
B~A Empty Flag
14
B~A Empty Flag
15
B~A
15
B~A Almost-Empty Flag
Almost-Empty Flag
2669tbll0
Almost-Full Flag
2669tblll
Table 8. The Two Status Register Formats
5.15
10
1017251,1017252,10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER FORMATS
15
Config. Reg. 0
X
10
X
X
X
X
15
Config. Reg. 1
X
A-?8 FIFO Almost-Empty Flag Offset
X
10
X
X
X
X
A-?8 FIFO Almost-Full Flag Offset
X
15
10
15
10
B~A
Config. Reg. 2
Config.Reg.3
X
Config. Reg. 4
Flag 0 Pin Assignment
15
X
X
X
X
12
11
FIFO Almost-Empty Flag Offset
B~
X
FIFO Almost-Full Flag Offset
4
Flag C Pin Assignment
Flag B Pin Assignment
Flag A Pin Assignment
15
Config.Reg.5
General Control
15
Config.Reg.6
Reserved
15
Config. Reg. 7
Parity Control
NOTE:
1.
2669tbl12
Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT7251 and IDT72510.
Table 9. The BiFIFO Configuration Register Formats
checking is enabled for data read and written through Port B.
Bit 8 controls parity checking and generation for B~A write
data. Bit 9 controls parity checking and generation for A~B
read data. Bit 10 controls whether the parity is odd or even.
Bit 11 is used to assign the internal parity checking error to the
FLGA pin. When the parity error is assigned to FLGA, the
Configuration Register 4 flag assignment for FLGA is ignored.
EXTERNAL FLAG ASSIGNMENT CODES
Assignment
Code
0000
Internal Flag Assigned to Flag Pin
A~B
Empty
Almost-Empty
0001
A~B
0010
A~B
Full
Programmable Flags
0011
A~B
Almost-Full
The lOT BiFIFO has eight internal flags; four of these flags
have programmable offsets, the other four are empty or full.
Associated with each FIFO memory array are four internal
flags, Empty, Almost-Empty, Almost-Full and Full, for the total
of eight internal flags. The Almost-Empty and Almost-Full
offsets can be set to any depth through· the Configuration
Registers 0-3 (see Table 9). The offset (or depth) of FIFO
RAM array is based on the unitof an 18-bitword. Theflags are
asserted at the depths shown in Table 13. After a hardware
reset or a software reset all, the almost flag offsets are set to
O. Even though the offsets are equivalent, the Empty and Almost-Empty flags have different timing which means that the
flags are not coincident. Similarly, the Full and Almost-Full
flags are not coincident because of timing.
These eight internal flags can be assigned to any of four
external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 10). For the specific flag timings, see Figures
20-23.
The current state of all eight flags is available in the Status
Register in Status Register format 1. In Status Register format
0, only four flags can be found in the Status Register (see
Table 8).
0100
B~AEmpty
0101
B~A
0110
B~AFull
0111
B~A
1000
A~B
Empty
1001
A~B
Almost-Empty
1010
A~B
Full
1011
A~B
Almost-Full
1100
B~A
Empty
1101
B~A
Almost-Empty
1110
B~AFull
1111
B~A
5.15
Almost-Empty
Almost-Full
Almost-Full
2669tbl13
Table 10. Configuration Register 4 Internal Flag Assignments to
External Flag Pins.
11
II
1017251,1017252,10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port B Interface
Port B also has parity, reread/rewrite and OMA functions.
Port B can be configured to interface to either Intel-style (RB,
WS) or Motorola-style (OSB, R/WS) devices in Configuration
Register 5 (see Table 11). Port Bcanalsobeconfiguredtotalk
to a processor or a peripheral device through Configuration
Register 5. In processor interface mode, the Port B interface
controls are inputs. In peripheral interface mode, the Port B
interface controls are outputs. After a hardware reset or a
software Reset All command, Port B defaults to an Intel-style
processor interface; the controls are inputs.
Two 9-bit words are put together to create each 18-bit word
stored in the internal FIFOs. The first 9-bit word written to Port
B goes into the Odd Byte Register shown in the detailed block
diagram. The Odd Byte Register valid bit (Bit 8) in the Status
Register is 1 when this first 9-bit word is written. The data bits
from Port B (OBO-OB7) are also stored in the lower 8 bits of the
Status Register when Status Register format 0 is selected
(see Table 8). The second write on Port B moves the 9-bits
from Port B and the 9-bits in the Odd Byte Register into the
B~A FIFO and advances the B~A Write Pointer. The Status
Register valid bit is set to 0 after the second write.
When Port B reads data from the A~B FIFO, two buffers
choose which 9 of the 18 memory bits are sent to Port B.
These buffers alternate between the upper 9 bits (OA8-0A15,
OA17) and the lower 9 bits (OAO-OA7, OA16). The A-~B Read
CONFIGURATION REGISTER 5 FORMAT
Bit
Function
a
Solect Port B Interface
a
Pins are RB and WB (Intel-style interface)
AB & WB or DSB & RIWB
1
Pins are DSB and RIWB (Motorola-style interface)
Byte Order of 18-bit Word
a
lower byte DA7-DAD and parity DA16 are read or written first on Port
B
1
Upper byte DA15-DAB and parity DA17 are read or written first on
PortB
1
2
3
Full Flag Definition
Empty Flag Definition
a
Full Flag is asserted when write pointer meets read pointer
1
Full Flag is asserted when write pointer meets reread pointer
a
Empty Flag is asserted when read pointer meets write pointer
1
Empty Flag is asserted when read pointer meets rewrite pointer
REO pin active HIGH
4
REO Pin Polarity
a
1
REO pin active lOW
5
ACK Pin Polarity
a
ACK pin active lOW
1
7-6
8
9
10
REO / ACK Timing
2 internal clocks between REO assertion and ACK assertion
01
3 internal clocks between REO assertion and ACK assertion
10
4 internal clocks between REO assertion and ACK assertion
11
5 internal clocks between REO assertion and ACK assertion
Port B Read and Write
a
Timing Control for Peripheral Mode
1
RB, WB, and DSB are asserted for 2 internal clocks
Internal Clock
a
internal clock
Frequency Control
1
internal clock
Port B Interface
a
Processor interface mode (Port B controls are inputs)
Mode Control
1
Peripheral interface mode (Port B controls are outputs)
00
12-11
13
ACK pin active HIGH
00
RB, WB, and DSB are asserted for 1 internal clock
= ClK
= ClK divided by 2
Stand-alone mode (18- to 9-bits, 36- to 18-bits)
Width Expansion
01
Reserved
Mode Control
10
Slave width expansion mode (36- to 9-bits)
11
Master width expansion mode (36- to 9-bits)
Unused
14
Unused
15
Unused
2669tbl14
Table 11. BiFIFO Configuration Register 5 Format
5.15
12
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER 7 FORMAT
BIT
FUNCTION
0-7
Unused
8
Parity Input Control
0
B~A
1
Enable Parity Generate, Disable Parity Check
9
Parity Output Control
0
Disable Parity Generate, Enable Parity Check
A~B
1
Enable Parity Generate, Disable Parity Check
10
Parity Odd/Even
0
Odd
Control
1
Even
11
Assign Parity Error to
0
No Parity Error Output
Flag A Pin
1
Parity Error on Flag A Pin
12-15
Disable Parity Generate, Enable Parity Check
Unused
2669 tbl15
Table 12. BIFIFO Configuration Register 7 Format
Pointer is advanced after every two Port Breads.
The BiFIFO can be set to order the 9-bit data so the first 9bits go to the lSB (DAO-DA7, DA16) or the MSB (DA8-DA15,
DA17) of Port A. This data ordering is controlled by bit 1 of
Configuration Register 5 (see Table 11).
DMA Control Interface
The BiFIFO has DMA control to simplify data transfers with
peripherals. For the BiFIFO DMA controls (REO, ACK and
ClK) to operate, the BiFIFO must be in peripheral interface
mode (Configuration Register 5, Table 11).
DMA timing is controlled by the external clock input, ClK.
An l.Q.ter~1 clock is deri~d from this ClK signal to generate
the Rs, Ws, DSs and R/Ws output signals. The internal clock
also determines the timing between REO assertion and ACK
assertion. Bit 9 of Configuration Register 5 determines
whether the internal clock is the same as ClK or whether the
internal clock is ClK divided by 2.
Bit 8 of Configuration Register 5 sets whether Rs, Ws and
DSs are asserted for 1 or 2 internal clocks. Bits 6 and 7 of
Configuration Register 5 set the number of clocks between
REO assertion and ACK assertion. The clocks between REO
assertion and ACK assertion can be 2, 3, 4 or 5.
Bits 4 and 5 of Configuration Register 5 set the polarity of
the REO and ACK pins, respectively.
A DMA transfer command sets the Port B read/write direction (see Table 5). The timing diagram for DMA transfers is
shown in Figure 17. The basic DMA transfer starts with REO
assertion. After 2 to 5 internal clocks, ACK is asserted by the
BiFIFO. ACKwili not be asserted if a read is attempted on an
Empty A~B FIFO or if a write is attempted on a Full B~A
FIFO. If the BiFIFO is in Motorola-style interface mode, R/Ws
is set at the same time that ACK is asserted. One internal
clock later, DSs is as~ertecL.. If the BiFIFO is in Intel-style
interface mode, either Rs or ws is asserted one internal clock
after ACK assertion. These read/write controls stay asserted
for 1 or 2 internal clocks, then ACK, DSs, Rs and Ws are made
inactive. This completes the transfer of one 9-bit word.
On the next rising edge of ClK, REO is sampled. If REO
is still asserted, another DMA transfer starts with the assertion
of ACK. Data transfers will continue as long as REO is
asserted.
Parity Checking and Generation
Parity generation or checking is performed by the BiFIFO
on data passing through Port B. Parity can either be odd or
even as determined by Bit 10 of Configuration Register 7.
When parity checking is enabled, DB8 is treated as a data
bit. DS8data will be passed to DA16 (bypass operation) or
stored in the RAM array (FIFO operation) for B->A operation;
INTERNAL FLAG TRUTH TABLE
Number of Words In FIFO
From
To
Empty Flag
Almost-Empty Flag
Almost·Full Flag
Full Flag
0
0
Asserted
Asserted
Not Asserted
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
Not Asserted
n+1
D- (m+ 1)
Not Asserted
Not Asserted
Not Asserted
Not Asserted
D-m
D -1
Not Asserted
Not Asserted
Asserted
Not Asserted
D
D
Not Asserted
Not Asserted
Asserted
Asserted
NOTE:
1.
2669tbl16
SiFIFO flags can be assigned to external flag pins to be observed. D = FIFO depth (IDT7251/510 = 512, IDT72521520 = 1024),
n = Almost-Empty flag offset, m= Almost-Full flag offset.
Table 13. Internal Flag Truth Table.
5.15
13
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
similarly, DA16 or parity bits from the RAM array will be passed
to DB8 for A->B operations. A->B read parity errors and B->A
write parity errors are shown in Bit 9 and 10 in the Status
Register. If an external parity error signal is required, a logical
OR of the two parity error bits is brought out to FLGA pin by
setting Bit 11 of Configuration Register 7.
Parity generation creates the ninth bit. This ninth bit is
placed on DB8 for A->B read operation, and on DA16 or RAM
array for B->A write operation.
It is recommended that if the parity pins (DB8, DA16, and
DA17) are not used, they should be pulled down with 10K
resistors for noise immunity.
Intelligent Reread/Rewrite
Intelligent reread/rewrite is a method the BiFIFO uses to
help assure data integrity. Port B of the BiFIFO has two extra
pointers, the Reread Pointer and the Rewrite Pointer. The
Reread Pointer is associated with the A->B FIFO Read
Pointer, while the Rewrite Pointer is associated with the B->A
FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read
Pointer is the current address of the same FIFO RAM array.
By loading the Read Pointer with the value held in the Reread
Pointer (RER asserted), reads will start over at the beginning
of the data block. In order to mark the beginning of a data
block, the Reread Pointer should be loaded with the Read
REREAD OPERATIONS
Pointer value (LDRER asserted) before the first read is
performed on this data block. Figure 6 shows a Reread
operation.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
the current address within the RAM array. The operation of the
REW and LDREW is identical to the RER and LDRER discussed above. Figure 7 shows a Rewrite operation.
For the reread data protection, Bit 2 of Configuration
Register 5 can be set to 1 to prevent the data block form being
overwritten. In this way, the assertion of A->B full flag will occur
when the write pointer meets the reread pointer instead of the
read pointer as in the normal definition. For the rewrite data
protection, Bit 3 of Configuration Register 5 can be set to 1 to
prevent the data block from being read. In this case, the assertion of B->A empty flag will occur when the read pointer meets
the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
REWRITE OPERATIONS
Write
Pointer - . . .
Rewrite
function
Read
Pointer
2669 drw09
2669 drw 10
Figure 6. BIFIFO Reread Operations
Figure 7. BiFIFO Rewrite Operations
5.15
14
1017251,1017252,10172510,10172520
BUS MATCHING BIOIRECTIONAL FIFO
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS{l)
Symbol
VTERM
Rating
Commercial
Military
Unit
Terminal Voltage
With Respect To
Ground
-0.5 to +7.0
-0.5 to +7.0
V
Symbol
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
lOUT
DC Output
Current
-55 to +125
-65 to +155
°C
50
50
mA
NOTE:
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Max.
Unit
Military Supply
Voltage
4.5
5.0
5.5
V
Veee
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
VIH
Input HIGH Voltage
Commercial
2.0
-
-
V
VIH
Input HIGH Voltage
Military
2.2
-
-
V
VIL(l)
Input LOW Voltage
Commercial and
Military
-
-
0.8
V
2669tbl17
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
VeeM
0
0
0
NOTE:
V
2669tbl18
1. 1.SV undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = O°C to +70°C; Military: Vcc = 5V ± 10%, TA = -55°C to +125°C)
IDT7251L
IDT7252L
IDT72510L
IDT72520L
Commercial
fA
Symbol
Parameter
= 35, 40, 50, 80ns
Min.
IIL(l)
Input Leakage Current (Any Input)
IOL(2)
Output Leakage Current
-10
IDT7251L
IDT7252L
IDT72510L
IDT72520L
Military
-1
Typ.
fA
Max.
Min.
1
-10
10
-10
= 40, 50, 80ns
Typ.
Max.
Unit
10
!lA
!lA
-
-
2.4
-
-
V
0.4
-
0.4
V
180
250
rnA
24
50
rnA
VOH
Output Logic "1" Voltage lOUT = -lmA
2.4
VOL
Output Logic "0" Voltage lOUT = 4mA
leeP)
Average Vee Power Supply Current
-
150
220
-
lec:P)
Average Standby Current (RB = Ws = D~ =
V IH)
-
16
30
-
-
10
NOTES:
2669tbl19
1. Measurements with O.4V ~ VIN ~ Vce, DSA = DSs ;:: VIH. 2. Measurements with 0.4 V ~ VOUT ~ Vcc ~ DSA = DSs ;:: VIH. 3. Masurements are made
with outputs open. Tested at f = 20 MHz.
AC TEST CONDITIONS
+5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
1.1 kn
D.U.T. ----'II/'----4p
See Figure 8
2669 tbl20
S80n
30 pF *
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
CIN(2)
Input Capacitance
COUT(1,2)
Output Capacitance
Conditions
Max.
Unit
VIN = OV
8
pF
VOUT= OV
12
pF
NOTES:
2669 drw 11
or Equivalent Circuit
Figure 8. Output Load
2669tb121
1. With output deselected.
2. Characterized values, not currently tested.
• Includes jig and scope capacitances
5.15
15
10T7251, 10T7252, 10T72510, 10T72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = SV+1D%,
TA = DOC to +7DoC; Military: Vcc = SV+1D%,
TA = -SsoC to +12S°C)
Commercial
IDT7251L35
IDT7252L35
IDT72510L35
IDT72520L35
Symbol
Parameter
Min.
Max.
Commercial and Military
IDT7251L40
IDT7252L40
IDT72510L40
IDT72520L40
Max.
Min.
IDT7251L50
IDT7252L50
IDT7251L80
IDT7252L80
IDT72510L50
IDT72520L50
IDT72510L80
IDT72520L80
Min.
Min.
Max.
Unit
Timing
Figure
-
ns
9
ns
9
Max.
RESET TIMING (Port A and Port B)
Reset recovery time
45
35
35
10
-
50
40
40
10
Flag reset pulse width
-
45
-
tRSC
Reset cycle time
tRS
Reset pulse width
tRSS
Reset set-up time
tRSR
tRSF
-
-
-
100
80
80
20
-
ns
9
-
65
50
50
15
-
ns
9
50
-
65
-
100
ns
9
-
PORT A TIMING
taA
Port A access time
-
35
-
40
-
50
-
80
ns
talz
Read or write pulse LOW
to data bus at low Z
5
-
5
-
5
-
10
-
ns
12,14, 15
12,15,16
taHz
Read or write pulse
HIGH to data bus at high
Z
-
20
-
25
-
30
-
30
ns
12,14,15,16
taDv
Data valid from read
pulse HIGH
5
-
5
-
5
-
5
-
ns
12,14,16
taRc
Read cycle time
Read pulse width
45
35
10
5
-
50
40
10
5
-
-
-
65
50
15
5
-
100
80
20
10
-
ns
taRPW
ns
12
12, 14, 15
12
10,12,16
-
ns
taRR
Read recovery time
tas
CS\, Ao, A1, PJNA set-up
time
taH
CS\, Ao, A1, PJNA hold
time
5
-
5
-
5
-
10
-
ns
10, 12
taos
tclDH(1)
Data set-up time
-
Write pulse width
tawR
Write recovery time
tawRCOM
Write recovery time after
a command
40
10
100
80
20
80
-
ns
Write cycle time
30
5
65
50
15
50
-
tawpw
20
5
50
40
10
40
-
tawc
18
0
45
35
10
35
11,12,14,15
11,12,14,15
12
11,12,14
12
11
Data hold time
-
-
-
-
-
-
ns
ns
ns
ns
ns·
ns
NOTE:
1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers.
5.15
16
IDTI251, IDTI252, IDTI2510, IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V±10%, TA = O°C to +70°C; Military: Vce = 5V±10%, TA = -55°C to +125°C)
Commercial
Symbol
Parameter
Commercial and Military
IDT7251L35
IDT7251L40
IDT7251L50
IDT7251L80
IDT7252L35
IDT7252L40
IDT7252L50
IDT7252L80
IDT72510L35
IDT72510L40
IDT72510L50
IDT72510L80
IDT72520L35
IDT72520L40
IDT72520L50
IDT72520L80
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Timing
Max.
Unit
Figure
PORT B PROCESSOR INTERFACE TIMING
tbA1
Port B access time with
no parity
-
35
-
40
-
50
-
80
ns
13,14,15
tbA2
Port B access time with
parity
-
42
-
48
-
60
-
90
ns
13,14,15
tbLZ
Read or write pulse LOW
to data bus at low Z
5
-
5
-
5
-
10
-
ns
13,14,15
tbHZ
Read or write pulse
HIGH to data bus at high
-
20
-
25
-
30
-
30
ns
13,14,15
5
-
5
-
5
-
10
-
ns
13, 14, 15, 16
50
-
13
Z
tbiJV
Data valid from read
pulse HIGH
tbRC
Read cycle time
45
tbRPW
Read pulse width
35
-
40
tbRR
Read recovery time
10
-
10
5
5
20
65
-
100
-
ns
50
-
80
-
ns
13
15
20
-
ns
13
10
-
13
-
-
30
-
40
--
ns
5
-
tbs
AlWB set-up time
5
tbH
AlWB hold time
5
tbOSl
Data set-up time with no
parity
18
-
tbOHl
Data hold time with no
parity
0
-
5
-
5
-
10
tbOS2
Data set-up time with
parity
22
-
25
-
35
-
tbOH2
Data hold time with
parity
0
-
5
-
5
tbwc
Write cycle time
45
-
65
Write pulse width
35
40
tbWR
Write recovery time
10
-
50
tbwpw
10
5
10
ns
13
ns
13,14,15
-
ns
13,14,15
45
-
ns
13,14,15
-
10
-
ns
13,14,15
13
ns
13,15
-
15
-
20
-
ns
-
-
100
50
ns
13
80
PORT B PERIPHERAL INTERFACE TIMING
tbA1
Port B access time with
no parity
-
40
-
45
-
55
-
85
ns
17
tbA2
Port B access time with
parity
-
42
-
48
-
60
-
90
ns
17
tbCKC
Clock cycle time
20
-
20
6
-
8
8
5
-
10
5
-
5
-
40
Clock pulse HIGH time
-
25
tbCKH
-
-
20
-
25
-
tbcKL
Clock pulse LOW time
6
tbREQS
Request set-up time
5
tbREQH
Request hold time
tbACKL
Delay from a rising clock
edge to ACK switching
5
-
18
5.15
10
10
16
16
10
5
35
ns
17
ns
17
ns
17
ns
17
ns
17
ns
17
17
iii
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V±1 0%, TA = O°C to +70°C; Military: Vee = 5V±1 0%, TA = -55°C to + 125°C)
Commercial
Symbol
Parameter
Commercial and Military
IDT7251L35
IDT7251L40
IDT7251L50
IDT7252L35
IDT7252L40
IDT7252L50
IDT7252L80
IDT72510L35
IDT72510L40
IDT72510L50
IDT72510L80
IDT72520L35
IDT72520L40
IDT72520L50
IDT72520L80
Min.
Min.
Min;
Min.
Max.
Max.
Max.
IDT7251L80
Max.
Timing
Unit
Figure
PORT B RETRANSMIT and PARITY TIMING
tbOSBH
RER, REW, LORER,
LOREW set-up and
recovery time
10
-
10
-
15
-
15
-
ns
9, 18
tbPER
Parity error time
25
-
25
-
30
-
30
-
ns
19
-
-
30
20
--
15
-
15
40
30
-
ns
-
15
25
20
-
ns
16
16
16
BYPASS TIMING
tSYA
Bypass access time
tSYO
Bypass delay
-
Bypa~data
15
20
15
-
3
-
3
-
3
-
3
-
ns
16
taSYDV
valid time
-
ns
from OS\
tbSYDV (3)
Bypass data valid time
from OS3
FLAG TIMING
tREF
Read clock edge to
Empty Flag asserted
-
35
-
40
-
45
-
60
ns
14,15,20,22
twEF
Write clock edge to
Empty Flag not asserted
-
35
-
40
-
45
-
60
ns
14,15,20,22
tRFF
Read clock edge to Full
Flag not asserted
-
35
-
40
-
45
-
60
ns
14,15,21,23
twFF
Write clock edge to Full
Flag asserted
-
35
-
40
-
45
-
60
ns
14,15,21,23
tRAEF
Read clock edge to
Almost-Empty Flag
asserted
-
50
-
55
-
60
-
75
ns
20,22
twAEF
Write clock edge to
Almost-Empty Flag not
asserted
-
50
-
55
-
60
-
75
ns
20,22
tRAFF
Read clock edge to
Almost-Full Flag not
asserted
-
50
-
55
-
60
-
75
ns
21,23
twAFF
Write clock edge to
Almost-Full Flag
asserted
-
50
-
55
-
60
-
75
ns
21,23
NOTES:
1. Read and Write are internal signals derived from DSA, RiWA, DSe, RiWe, Re, and We.
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
5.15
18
IDTI251, IDTI252, IDTI2510, IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1 - 0 0 I I 1 - - - - - - - tRSC -------~
..........
a-----
tRS ------1~
WS,Rs
(or RlWs, DSs)
LDRER
LDREW
REO
•
FLGA,
FLGc
FLGs,
FLGD
2669 drw 12
Figure 9. Hardware Reset Timing for IDTI2510/520
5.15
19
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AO,A1
tas
Figure 10. Basic Port A Control Signal TIming (Applies to All Port A TIming)
\'---_ _ _---J/
\'-------
twpw
tWRCOM
Opcode
DAB-DA12
or
Operand
2669 drw 14
DAO-DA2
taDs
taDH
Figure 11. Port A Command TIming (Write)
5.15
20
1017251,1017252,10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
~~-----tawc------~~
tawpw
tas .....I--I~
l""1li1-------.-1
taH
Input
DAD - DA17
taDs
taDH
READ
~~-------taRc---------p~
tas
II
Output
DAD - DA17
I
Figure 12. Read and Write Timing for Port A
5.15
2669 drw 15
21
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
(RJWB)
WB
(or DS3)
-
~r
-
~
~
tbs
}f-
tbwpw
~
1\
L
Input
DBo-DBa
tbOS1 or tbOS2
...
tbwc
r
.. lL~
~
tbWR~
..
IL~
/I
I
-
~
tbH
.I
- - '! tbOH1 ortbOH2
NOTES:
1. ttOS1 and tboH1 are with parity checking or if parity is ignored, tbOS2 and tOOH2 are with parity generation.
2. Fi:l = 1
READ
~.---------tbRC--------~~
RB
tbRPW ---1.".......- tbRR
(or DS3)
tbH
tbs
Output
DBo-DBa
tbLZ
tbA1 or tbA2
NOTES:
2669 drw 18
1. tM1 is with parity checking or if parity is ignored, tbA2 is with parity generation.
2. WB=1
Figure 13. Port B Read and Write Timing. Processor Interface Mode Only
5.15
22
ID17251, ID17252, ID172510, ID172520
BUS MATCHING BIDIRECTIONAL FIFO
A-7B FIFO WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW-THROUGH
DAo-DA17
A~B
Full Flag(l)
1 4 - - - tRFF - -.........I---I~ tWFF
AB (or DS3)
DBo-DB8
~tbHZ~
1 4 - - -__~1 tbA1 or tbA2(2)
NOTES:
1. Assume the flag pin is programmed active low.
2. tbA1 is with parity checking or if parity is ignored, tbA2 is with parity generation.
3. RliJA = O.
B-7A FIFO READ FLOW-THROUGH
talz
DAo-DA17
B~A
Empty Flag(ll.
WB (or DS3)
DBo-DB8
2669 drw 16
NOTES:
1. Assume the flag pin is programmed active low.
2. tbJS1 & tboH1 is with parity checking or if parity is ignored, tbDS2 & tbJH2 is with parity generation.
3. RliJA = 1.
Figure 14. Port A Read and Write Flow-Through Timing. Processor Interface Mode Only
5.15
23
1017251,1017252,10172510,10172520
BUS MATCHING BIOIRECTIONAL FIFO
B~A
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
FIFO WRITE FLOW-THROUGH
taA
B-tA
Full Flag(1)
~--__~I
~---
taHz ---'.~I
----------f-----J
tRFF ~---I~"--~
tbwpw
~---~
tWFF
Ws (or DSB)
Dso-Dss
tbOS1 or tbOS2 (2)
~-~~-~
tbOH1 ortboH12 (2)
NOlES:
1. Assume the flag pin Is programmed active low.
2. ttoS1 & tboH1 are with parity checking or if parity Is ignored, tbOS2 & tboH2 are with parity generation.
3. RWA .. 1.
A~B
FIFO READ FLOW-THROUGH
DAo-DA17
taos ~-~"'-"I taoH
A-tB
Empty Flag(1).
~_tW-E-F_.~._--~tbRPW
t4---~
tREF
Rs (or DSB)
tbLZ 14--~
Dso-DBS
tbA10rtbA2
NOTES:
1. Assume the flag pin Is programmed active low.
2. tM1 are with parity checking or if parity is ignored, tbA2 are with parity generation.
2669 drw 19
3. RWA= O.
Figure 15. Port B Read and Write Flow-Through Timing
5.15
24
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
B-tA READ BYPASS
DAo-DA7,
DA16
Rs (~(orDSS)
(RlWS)
___________71 _-Dso-Ds8
BYTE 0
tBYO
~----BYT--E-1--~)~------~(~---------B-YT--E-2-----------
NOTE:
1. Once the bypass starts, any data changes on Port B bus (Byte 0 -t Byte 1) will be passed to Port A bus.
2.
&I
WB = 1.
A-tB WRITE BYPASS
DAo-DA7,
DA16
Ws
(2) (orOSS)
(RlWS)
Dso-Ds8
2669 drw 17
NOTE:
1. Once the bypass starts, any data changes on Port A bus (Byte 0 -t Byte 1) will be passed to Port B bus.
2
~ =1
Figure 16. Bypass Path Timing. BIFIFO Must be in Peripheral Interface Mode
5.15
25
IOTI251, IOTI252, 10172510, IOTI2520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE WORD DMA TRANSFER
~
2to 5 CYcieSOi1 cycle
tCKC
tCKH
ClK
REQ
~ltCKL
I
J
REQS
1 to 2 cycles
~
I
L
...
\~
I
tREQH
~
WRITE
'\
(RJWs)
tACKL ~
Ws (or 0S3)
JL
"
"
/IL
f4~
/~
K
~
tACKL.~
KZ)
Output
080-0817
tbLZ
tbA1
READ
(RlWs)
~
tACKL
...
)®~
...
I~
..
or tbA2
•
tbov
~ tbHZ~
--------------------------------------------- - -- -------- ----------------------
~K.
Rs (orOS3)
tACKL ___
....
~
Input
} ~
~ tACKL
"'
V
/
I\..
080-0S17
tbOS1
NOTES:
or tbOS2
tbOH1
or tbOH2
1. tbAl, tbOSl & tbOHl are with parity checking or if parity is ignored, tbA2, tbOS2 & tboH2 are with parity.
BLOCK DMA TRANSFER
2
5
~cy~fes
-1
1 to 2
cycles
1 to 2
~2t05~
H
I
cycles
I
ClK~
cycles
H
..
···•
•
··•
ACK, RlWs
Rs, Ws (or 0S3)
•
·
"
'---+---!'.
V
~
"
l/
'---'----(,
•
2669 drw 20
Figure 17. Port B Read and Write OMA Timing. Peripheral Interface Mode Only
5.15
26
ID17251, ID17252, ID172510, ID172520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AB, WB
(or
RfiJB, DS3)
tbDSBH
tbWPWH
tbDSBH
Bffi.
REW
LDRER,
LDREW
2669 drw 21
Figure 18. Port B Reread and Rewrite Timing for Intelligent Retransmit
Set Parity Error:
FLGA is assigned as the parity error pin
~,
RlWB
/L
tbH
tbs
~
AB, WB (orDS3)
..
/L
'"
...
~
tPER
FLGA
Clear Parity Error:
Command written into Port A clears parity error on FLGA pin
,
~_
.....
~L
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
./
taH .....
__----~
tas
==t
______________________________________~._______t_P_ER
__
FLGA
~---------------
NOTE:
1. FLG\ is the only pin that can be assigned as a parity error output.
2669 drw 22
Figure 19. Port B Parity Error Timing
5.15
27
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Read
-------------------------;\r-----------------------~
Ws
(or RIWs=o,
DS3)
B-tA
Empty Flag
~ tRAEF
B-tA Almost·
Empty Flag
1'--------------\'\-,--------2669 drw23
NOTES:
1. B~A FIFO is initially empty.
2. Assume the flag pins are programmed active low.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled.
4. RlNA = 1
Figure 20. Empty and Almost·Empty Flag Timing for B~A FIFO. (n
= Programmed Offset)
Read
--------------------------;\r-------------------,
Write
_
Ws ----, 1
(or R1Ws=O, DS3)
B-tA Almost·
Full Flag
n
2m+1
211 3 r1 4
1{:tWAFF
L2J l2J l2J
r\
W
\r------+-----------------+------------4\-------+-J
~------.:t
B-tA --------------------------4\r------+~
Full Flag
'rl--------------2669 drw 24
NOTES:
1. ~A FIFO initially contains O-(M+1) data words. 0 = 512 for lOT 7251/510; 0 = 1024 for IOT7252/520.
2. Assume the flag pins are programmed active low.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled.
4. RNJA = 1
Figure 21. Full and Almost·Full Flag Timing for B~A FIFO. (m
5.15
=Programmed Offset)
·28
IDT7251, IDT7252, IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Write
------,
~\-,
. r---1
L2..J
i--------------------------------~\\
~
L2J
Read
"Rs
(or RlWB=1, DSs)
A~B
Empty Flag
A~B
------------\'\\-c---------------
Almost-Empty Flag
NOTES:
1. A-tB FIFO is initially empty.
2. Assume the flag pins are programmed active low.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled.
4. PmA=1
2669 drw2S
FIgure 22. Empty and Almost-Empty Flag TImIng for A-tB FIFO. (n
=Programmed OHset)
Write
-- ------,
Ds\
.
r---1
L2-J
~\-,
L2.J
.
i--------------------------------~\'\-,----------------
~
~
(or RlWs=1, DSs)
R~
---+--t-----~
\---t--+-----....,
B~A ------Ih.
Almost- Full Flag
B~AFull
Flag
2669 drw26
NOTES:
1.
2.
3.
4.
A-tB FIFO initially contains D-(M+1) data words. D = 512 for IDT7251/510; D = 1024 for 1DT72521520.
Assume the flag pins are programmed active low.
For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads must be doubled.
PmA =0
FIgure 23. Full and Almost-Full Flag TIming for A~B FIFO. (m
5.15
= Programmed Offset)
29
II
G
IDT72511
IDT72521
PARALLEL BIDIRECTIONAL FIFO
512 X 18-BIT & 1024 x 18-BIT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512x18-Bit-512x18-Bit(IOT72511)
• 1024 x 18 - Bit - 1024 x 18 - Bit (IOT72521)
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit communication
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight flags can be assigned to four external
flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard OMA control pins for data exchange with
peripherals
• 6a-pin PGA and PlCC packages
The IOT72511 and IOT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. lOT BiFIFOs integrate two side-by-side memory arrays for data transfers in
two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration
Registers.
The lOT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight
internal flags can be assigned to any of four external flag pins
(FlGA-FlGD) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and OMA
functions. Six programmable I/O pins are manipulated through
two Configuration Registers. The Reread and Rewrite controls
will read or write Port B data blocks multiple times. The
BiFIFO has three pins, REQ, ACK and ClK, to control OMA
transfers from Port B devices.
SIMPLIFIED BLOCK DIAGRAM
Data
Data
Port
A
110
14-~
Control
Flags
~
_ _ _~
Control
I .....I -.....~ DMA
2668 drwOl
MILITARY AND COMMERCIAL TEMPERATURE RANGES
"'1992 Integrated Device Technology. Inc.
APRIL 1992
DSC-2031/4
5.16
1
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
11
DS17 FlGs FlGD
DS13
DS14
DS15 FlGA FlGc
Ao
DA15 DA13
DAll
DA17
DA14 DA12
PI05 PI04
10
DS11
DS12
09
DS9
DS10
DA9
DA10
08
GND
DS8
PI03
DA8
07
Rs
GND
06
Ws
Vee
05
DS7
04
Al
GND LDRER
Vee
DSA
DS16
GND
RS
DS5
DS6
PI02 LDRE'II
03
DS3
DS4
DA7
DA16
02
DS2
DSl
ClK
DA6
01
•
Dso
ACK REW GND CSA
A
B
(
G68-1
C
REO RER RlWA PIOo
DAO
DA2
DA5
Pial
DAl
DA3
DA4
J
K
D
E
F
G
H
l
2668 drw 02
PGA
TOP VIEW
PIN 1
DESIGNATOR
~ ~ ~;( ~ B FIFO Read
Pointer, while the Rewrite Pointer is associated with the B->A
FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read
Pointer is the current address of the same FIFO RAM array.
By loading the Read Pointer with the value held in the Reread
Pointer (RER asserted), reads will start over at the beginning
of the data block. In order to mark the beginning of a data
block, the Reread Pointer should be loaded with the Read
Pointer value (lDRER asserted) before the first read is
performed on this data block. Figure 6 shows a Reread
operation.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
the current address within the RAM array. The operation of the
REW and lDREW is identical to the RER and lDRER discussed above. Figure 7 shows a Rewrite operation.
For the reread data protection, Bit 2 of Configuration
Register 5 can be set to 1 to prevent the data block from being
overwritten.lnthisway, the assertion ofA->Bfuliflagwili occur
when the write pointer meets the reread pointer instead of the
read pointer as in the normal definition. For the rewrite data
protection, Bit 3 of Configuration Register 5 can be set to 1 to
INTERNAL FLAG TRUTH TABLE
Number of Words In FIFO
From
To
Empty Flag
Almost·Empty Flag
Almost·Fuli Flag
Full Flag
0
0
Asserted
Asserted
Not Asserted
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
Not Asserted
n+1
D - (m + 1)
Not Asserted
Not Asserted
Not Asserted
Not Asserted
D-m
D -1
Not Asserted
Not Asserted
Asserted
Not Asserted
D
D
Not Asserted
Not Asserted
Asserted
Asserted
NOTE:
2668 tbl14
1. BiFIFO flags must be assigned to external flag pins to be observed. D = FIFO depth (IDT72511
offset, m = Almost-Full flag o f f s e t . ·
= 512, IDT72521 = 1024), n =Almost-Empty flag
.
Table 11. Internal Flag Truth Table
5.16
11
10172511/10172521
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
prevent the data block from being read. In this case the
assertion of B->A empty flag will occur when the read pointer
meets the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
Programmable InputlOutput
The BiFIFO has six programmable 1/0 pins (PlOD - PIOs)
which are controlled by Port A through Configuration Registers 6 and 7. Data from the programmable 1/0 pins is mapped
directly to the six least significant bits of Configuration Register 6. Figure 4 shows the format of Configuration Register 6.
REREAD OPERATIONS
This data is read or written by Port A on the data pins
(DAo- DAs). A programmed output PIOi pin (i = 0,1, ... , 5)
displays the data latched in Bit i of Configuration Register 6.
A programmed input PIOi pin allows Port A bus to sample its
data on DAi by reading Configuration Register 6. The read
and write timing for the programmable 1/0 pins is shown in
Figure 19. The direction of each programmable 1/0 pin can be
set independently by programming the mask in Configuration
Register 7. Each P10 pin has a corresponding input/output
direction mask bit in Configuration Register 7. Figure 5 shows
the format of Configuration Register 7. Setting a mask bit to a
logic 1 makes the corresponding 1/0 pin an output. Mask bits
set to logic 0 force the corresponding 1/0 pin to an input.
REWRITE OPERATIONS
Read
Write
Pointer --.....
II
Read
Pointer
Rewrite
Function
Pointer
2668 drw 07
2668 drw 08
Figure 7. BiFIFO Rewrite Operations
Figure 6. BiFIFO Reread Operations
5.16
12
10172511/10172521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Military
Unit
Terminal Voltage
With Respect To
Ground
-0.5 to +7.0
-0.5 to +7.0
V
Symbol
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
lOUT
DC Output
Current
. -55 to +125
-65 to +155
°C
50
rnA
50
NOTE:
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Max.
Unit
,4.5
5.0
5.5
V
4.5
5.0
5.5
V
0
0
V
-
-
V
-
-
V
-
0.8
V
Military Supply
Voltage
Vccc
Commercial Supply
Voltage
GND
Supply Voltage
VIH
Input HIGH Voltage
Commercial
2.0
VIH
Input HIGH Voltage
Military
2.2
VIL(l)
Input LOW Voltage
Commercial and
Military
-
2668 tbl15
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speCification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
...
Parameter
VCCM
0
NOTE:
2668 tbl16
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = O°C to +70°C; Military: Vcc = 5V ± 10%, TA = -55°C to +125°C)
IDT72511L
IDT72521L
Commercial
tA = 35, 40, 50, 80ns
Min.
Max.
Typ.
Parameter
Symbol
IIL(l)
Input Leakage Current (Any Input)
IOL(2)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage bUT= -1mA
2.4
VOL
Output Logic "0" Voltage bUT = 4mA
ICCl (3)(4)
Average VCC Power Supply Current
ICC2(3)
Average Standby Current (Rs = WS = Ds\ =
V IH)
-
-1
IDT72511L
IDT72521L
Military
tA = 40, 50, 80ns
Min.
Typ.
Max.
-10
-
10
10
-10
-
10
-
2.4
0.4
-
-
0.4
V
180
250
rnA
24
50
rnA
150
230
16
30
-
NOTES:
1.
2.
3.
4.
Unit
1
-
J.lA
J.lA
V
2668tbl17
Measurements with O.4V::; VIN::; Vcc, DSA = DSB <: VIH
Measurements with 0.4V::; VOUT::; Vcc, DSA = DSB <: VIH
Measurements are made with outputs open.
Tested at f = 20 MHz.
+5V
AC TEST CONDITIONS
1.1 kn
GNDto3.0V
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
D.U.T.
680n
30 pF*
See Figure 8
Output Load
2668tbl18
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
CIN(2)
COUT(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
Max.
Unit
VIN = OV
8
pF
VOUT = OV
NOTES:
12
OR EQUIVALENT CIRCUIT
2668 drw09
Figure 8. Output Load
"Includes jig and scope capacitances
pF
2668 tbl19
1. With output deselected.
2. Characterized values, not currently tested.
5.16
13
10172511/10172521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc
= 5V ± 10%, TA =
O°C to + 70°C; Military: Vcc
Commercial
Symbol
Parameter
5V +
- 10%, TA
= -55°C to + 125°C)
Commercial and Military
IDT72511L35
IDT72511L40
IDT72511L50
IDT72511L80
IDT72521L35
IDT72521 L40
IDT72521L50
IDT72521L80
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Unit
Timing
Figure
-
ns
9
100
Max.
RESET TIMING (Port A and Port B)
Reset recovery time
45
35
35
10
-
50
40
40
10
-
65
50
50
15
-
Reset to flag time
-
45
-
50
-
65
100
80
80
20
-
tRSC
Reset cycle time
tRS
Reset pulse width
tRSS
Reset set-up time
tRSR
tRSF
-
ns
9
ns
9
ns
9
ns
9
ns
PORT A TIMING
tM
Port A access time
-
35
-
40
-
50
-
talz
Read or write pulse LOW
to data bus at low Z
5
-
5
-
5
-
10
80
-
ns
12,14,15
12,15,16
taHz
Read or write pulse
HIGH to data bus at high
Z
-
20
-
25
-
30
-
30
ns
12,14,15,1.6
taDV
Data valid from read
pulse HIGH
5
-
5
-
5
-
5
-
ns
12,14,16
taRc
Read cycle time
-
50
40
65
50
100
80
ns
-
-
ns
12
12,14,15
-
10
5
15
5
-
20
10
-
ns
-
-
-
Read pulse width
45
35
10
5
-
taRPW
ns
12
10,12,16
taRR
Read recovery time
taS
CS\, Ao, A1, RNJA set-up
time
taH
CS\, Ao, A1, RNJA hold
time
5
-
5
-
5
-
10
-
ns
10,12
Data set-up time
18
2
45
35
10
35
-
20
5
50
40
10
-
30
5
65
50
15
50
-
40
10
100
80
20
80
-
ns
11,12,14,15
11,12,14,15
taDs
taDH(1)
Data hold time
tawc
Write cycle time
tawpw
Write pulse width
tawR
Write recovery time
tawRCOM
Write recovery time after
a command
-
-
40
ns
12
ns
ns
11,
~2,
ns
12
ns
11
14
2668tbl20
NOTE:
1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers.
5.16
14
II
IDT72511/IDT72521
BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, TA = O°C to + 70°C; Military: Vee
Commercial
Symbol
Parameter
5V ± 10%, TA = -55°C to + 125°C)
Commercial and Military
10T72511 L35
10T72511L40
10T72511L50
10T72511L80
10T72521 L35
10T72521 L40
10T72521L50
10T72521L80
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Timing
Unit
Figure
PORT B PROCESSOR INTERFACE TIMING
tbA
Port 8 access time
-
35
tbLZ
Read or write pulse LOW
to data bus at low Z
5
-
tbHZ
Read or write pulse
HIGH to data bus at high
-
20
5
-
40
5
-
40
-
50
-
80
ns
13,14,15
-
5
-
10
-
ns
13,14,15
25
-
30
-
30
ns
14,13,15
5
-
5
-
10
-
ns
13,14,15,16
50
-
65
-
100
-
ns
13
50
80
ns
13
15
-
20
ns
13
5
-
10
ns
13
5
-
10
-
10
100
Z
tbov
Data valid from read
pulse HIGH
tbRC
Read cycle time
45
tbRPW
Read pulse width
35
tbRR
Read recovery time
10
tbs
RlWs set-up time
5
tbH
RlWs hold time
5
tbos
Data set-up time
18
tbOH
Data hold time
2
tbwc
Write cycle time
45
tbwpw
Write pulse width
35
-
tbwR
Write recovery time
10
-
10
40
10
5
5
20
5
50
30
5
65
50
15
40
80
20
ns
13
ns
13, 14, 15
-
ns
13,14,15
-
ns
13
ns
13,15
ns
13
PORT B PERIPHERAL INTERFACE TIMING
tbA
Port 8 access time
-
40
-
45
-
55
-
85
ns
17
tbCKC
Clock cycle time
20
-
20
25
17
6
8
tbCKL
Clock pulse LOW time
6
5
5
-
ns
Clock pulse HIGH time
-
40
tbCKH
20
-
25
-
35
ns
17
tbREOS
Request set-up time
5
tbREOH
Request hold time
5
-
tbAcKL
Delay from a rising clock
edge to ACK switching
-
18
8
5
5
-
10
10
10
16
16
10
ns
17
ns
17
ns
17
ns
17
2668 tbl 21
5.16
15
10172511/10172521
BIDIRECTIONAL FIRST-IN FIRST·OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, TA = O°C to + 70°C; Military: Vee
Symbol
Parameter
PORT B RETRANSMIT TIMING
tbDSBH
RER, REW, LDRER,
LDREW set-up and
recovery time
Commercial
10172511 L35
10172521 L35
Max.
Min.
5V ± 10%, TA = -55°C to + 125°C)
Commercial and Military
10172511L40
10172511L50
10172511L80
10172521 L40
10172521L50
10172521 L80
Max.
Min.
Min.
Min.
Max.
Max. Unit
Timing
Figure
10
-
10
-
15
-
15
-
ns
9,18
PROGRAMMABLE 1/0 TIMING
tPIOA
Programmable 110
access time
-
25
-
25
-
30
-
30
ns
19
tPIOS
Programmable 110 setup time
10
-
10
-
15
-
15
-
ns
19
tPIOH
Programmable 110 hold
time
10
-
10
-
15
-
15
-
ns
19
BYPASS TIMING
tBYA
Bypass access time
20
15
-
25
20
-
30
20
-
40
30
ns
Bypass delay
-
-
tBYD
Bypa~data
15
-
15
-
15
-
15
-
ns
16
16
16
3
-
3
-
3
-
3
-
ns
16
taSYDV
valid time
from Ds\
tbBYDV (3)
Bypa~datavalid
time
from DS3
ns
FLAG TIMING (1) (2)
tREF
Read clock edge to
Empty Flag asserted
-
35
-
40
-
45
-
60
ns
14,15,20,22
twEF
Write clock edge to
Empty Flag not asserted
-
35
-
40
-
45
-
60
ns
14,15,20,22
tRFF
Read clock edge to Full
Flag not asserted
-
35
-
40
-
45
-
60
ns
14,15,21,23
twFF
Write clock edge to Full
Flag asserted
-
35
-
40
-
45
-
60
ns
14,15,21,23
tRAEF
Read clock edge to
Almost-Empty Flag
asserted
-
50
-
55
-
60
-
75
ns
20,22
twAEF
Write clock edge to
Almost-Empty Flag not
asserted
-
50
-
55
-
60
-
75
ns
20,22
tRAFF
Read clock edge to
Almost·Full Flag not
asserted
-
50
-
55
-
60
-
75
ns
21,23
twAFF
Write clock edge to
Almost-Full Flag
asserted
-
50
-
55
-
60
-
75
ns
21,23
NOTES:
2668 tbl22
1. Read and write are Internal signals derived from '[)SA, RlWA,We, RlWe, lie, and We.
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are Internal flags, the timing given Is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
5.16
16
IDT7251111DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
......1------- tRse -------~
......1----- tRs ------II~
WB,RB
(or RlWB, DSB)
RER,
REW
LDRER,
LDREW
REO
FLGA,
FLGe
FLGB,
FLGD
2668 drw 10
Figure 9. Hardware Reset TIming
AO,A1
tas
Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing)
5.16
17
10172511110172521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
\ _____----11
\\....----tWRCOM
Opcode
DAB - ~12
or
Operand
DAD - ~12
2668 drw 12
Figure 11. Port A Command Timing (write).
WRITE
DSA
tas
Input
DAD - DA17
taos
taoH
READ
RfiiA
taRe
DSA
tas
Output
DAD - DA17
Figure 12. Read and Write Timing for Port A
5.16
18
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
(RIWB)
Ws
(or DS3)
..
~~
tbwc
)
-
~
Input
Dso-DBs
v
,I
r-
I
. '1
tbos
tbOH
.
y-_
tbWPW....., ~ tbWR...-.)
-
'1
tbs
,,
tbH
,,
I
NOTE:
1.~=1_
READ
RS
(or DS3)
Output
Dso-DBs
NOTE:
1. Wa=1
Figure 13. Port BRead a'nd Write Timing, Processor Interface Mode Only
5.16
19
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
A-tB FIFO WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW-THROUGH
DAO - DA17
taDH
A-78
Full Flag 1)
~--tRFF
---I~""-~ tWFF
Rs (or oSs)
Dso -
DATA OUT
1)317
~--__~tbA
NOTES:
1. Assume the flag pin is programmed active low.
2. RiiiA = 0
B-tA FIFO READ FLOW-THROUGH
tall
DAD - DA17
8-7A
Empty Flag(l)
Ws (or oSs)
DATA INPUT
Dso - C817
~--- tbDS ---~
2547 drw 13
NOTES:
1. Assume the flag pin is programmed active low.
2. RiiiA = 1
Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only
5.16
20
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
B~A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIFO WRITE FLOW-THROUGH
OAo-OA17
B~A
Full Flag(l)
Rs= 1 (or RMis= 0)
Ws (or OS:!)
Oso-Oss
~----~~------~tbOH
NOTES:
1. Assume the flag pin is programmed active low.
2. RfiJA= 1
A~B
FIFO READ FLOW-THROUGH
OAo-OA17
taos
~-~~-...
taoH
A~B
Empty Flag(1)
tWEF
t REF
Ws= 1 (or RMis= 1)
----------~
As (or OS:!)
taLZ ~-~
Oso-Oss
tbA
2668 drw 18
NOTES:
1. Assume the flag pin is programmed active low.
2. RfiJA= 0
Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only
5.16
21
IDT72511/1OT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
B-tA READ BYPASS
DM-DA7,
DA16
(RtWs)
DBo-DB8
NOTES:
1. Once the bypass mode starts, any data change on Port B bus (Byte O-+Byte 1) will be passed to Port A bus.
2. WB= 1
A-tB WRITE BYPASS
DAo-DA7,
DA16
BYTE 2
tBYD
WB {or DSa)
(RtWB)
DBo-DB8
2668 drw 16
NOTES:
1. Once the bypass mode starts, any data change on Port A bus (Byte O-+Byte 1) will be passed to Port B bus.
2. RB= 1
Figure 16. Bypass Path Timing, BiFIFO Must Be in Peripheral Interface Mode
5.16
22
IDT72511I1DT72521
BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE WORD DMA TRANSFER
t05CYcieS
~
tCKC
tCKH
ClK
tCKL
REO
tREOS .......,.--'II~ tREOH
WRITE
(R/WS)
tACKL
WS(orDS3)
Output
Dsa-Ds17
READ
(RIWs)
Rs(orDS3)
Input
Dsa-Ds1?
tbos . .- -. . . . .- -. . . tboH
BLOCK DMA TRANSFER
r- cyc~es -1
2t 5
1 t02
cycles
H
~2t05~
cycles
I
I
1 to 2
cycles
H
CLKl5UliU
I
REO
~
I
I
I
I
I
I
I
I
I
I
RS, WS(orDS3)
"
,,~~V
o
V
'-..,....--(,
2668 drw 19
Figure 17. Port B Read and Write DMA timing. Peripheral Interface Mode Only
5.16
23
10172511110172521
BIDIRECTIONAL FIRST-IN FIRST·OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AB, WB
(or RlWB, DS3)· _ _ _ _--'
tbwpw
tbOSBH
tbOSBH
Be..B
REW
LDRER,
LDREW ________________--'
2668 drw20
Figure 18.. Port B Reread and Rewrite TIming for Intelligent Reread/Rewrite
Port A --+PIO WRITE
~~
_____ tawc ______~~
tas
II
Input
OAo-OAS
Output
PIOo-PIOs
PIO --+Port A READ
Output
DAo-DAS
Input
PIOo-PIOs
Figure 19. Programmable 110 Timing
5.16
24
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Read
--------------------~\~------------------------~
tREF
B-)A Empty
Flag
B-)A AlmostEmpty Flag _ _ _ _ _ _ _ _ __
-------\'\-,,----2668 drw22
NOTES:
1. ~A FIFO is initially empty.
2. Assume the flag pins are programmed active low.
3.
RliiiA = 1
Figure 20. Empty and Almost-Empty Flag Timing for B-tA FIFO, (n:: programmed offset)
Read
D~--------------------~\\-----------------------~
(2)
B-)A - - - - - - - - - - - \
Full Flag
~-__I__,
2668 dfW23
NOTES:
1. B--+A FIFO initially contains D - (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521.
2. Assume the flag pins are programmed active low.
3.
RmA= 1
Figure 21. Full and Almost-Full Flag Timing for B-tA FIFO, (m :: programmed offset)
5.16
25
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D8A~~~________________________________~\,~(__________.....
AS
(or RlWB=1, DEB) .....- - - - + - 1 - - - - - - \
\---+--t-------..,
Read
A-7B Empty (2)
Flag
-----t-"
A-7B Almost- (2)
----------\'t-e-----------
Empty Flag .....- - - - - - - - - - - - \ ~--.....,.
2668 drw 24
NOTES:
1. A-tB FIFO is initially empty.
2. Assume the flag pins are programmed active low.
3. WA= 1
Figure 22. Empty and Almost-Empty Flag Timing for A-7B FIFO, (n
=programmed offset)
Read
DS\----------------------\\~--------------------~
(2)
B-7A ----------------------\
Full Flag
r------+-_.
2668dIW 23
NOTES:
1. B-7A FIFO initially contains D - (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521.
2. Assume the flag pins are programmed active low.
3. RJiiJA= 1
Figure 23. Full and Almost-Full Flag Timing for A-7B FIFO, (m = programmed offset)
5.16
26
G®
PARALLEL SyncBiFIFOTM
(CLOCKED BIDIRECTIONAL FIFO)
256 X 18-BIT AND 512 x 18-BIT
PRELIMINARY
IOT72605
IOT72615
Integrated Device Technology, Inc.
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 organization (lOT 72605)
• 512 x 18 organization (lOT 72615)
• Synchronous interface for fast (25ns) read and write cycle
times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and the
B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 68-pin PGA and
PLCC
• Military product compliant to MIL-STO-883, Class B
DESCRIPTION:
The IOT72605 and IOT72615 are very high speed, low
power bidirectional FIFO memories with synchronous interface
for fast read and write cycle times. The SyncBiFIFOTM is a
data buffer that can store or retrieve information from two
sources simultaneously. Two dual-port FIFO memory arrays
are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal.
Individual output enable signals control whether the
SyncBiFIFO is driving the data lines of a port or whether those
data lines are in a high impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memories.
The offset depths of the almost-full and almost-empty flags
can be programmed to any location.
The SyncBiFIFO is fabricated using lOT's high speed
submicron CEMOSTM technology. Military grade product is
manufactured in compliance with the latest revision of MILSTO-883, Class B.
OAO·OAI7
FUNCTIONAL BLOCK DIAGRAM
- -.... ,1> INPUT REGISTER
EFAB
PAEAB
PAFAB
FFAB
GNO
elKs
-----~I
OEB
RiWa
~B ~~~~~+-----~----L-----+--~
OBO·0817
2704drw 01
SyncBiFIFO and CEMOS are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·204512
et 992 Integrated Device Technology, Inc.
5.17
1
IDT72605/IDT72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
11
DB3
DB4
Dss
DB7
DB9
Vee
DB11
DB13
GND
GND
DB6
DB8
GND
DB10
DB12
DB14
DB15
DB16
Ci"t A
DB17
10
DB1
DB2
09
RS
DBO
08
RlWB
ClKB
07
DEB
rnB
06
GND
SYP B
05
mAB mAB
G68-1
mBA mBA
~AB
~AB
A2
Vee
Ao
A1
rnA
GSA
ClKA
RiWA
DA17
Pin 1 Designator
/
04
~BA
~BA
03
DA1
DAO
•
02
DA2
DA3
GND
DA6
DA8
GND
DA10
DA12
DA14
DA16
DM
DAS
DA7
DA9
Vee
DA11
DA13
GND
DA15
S
C
D
01
A
E
G
H
K
PGA
Top View
2704drw02
LJLJLJLJLJLJLJLJIILJLJLJLJLJLJLJLJ
DA16
DA17
ClKA
RiwA
ENA
CSA
Ao
A1
A2
VCC
EFAS
FFAS
PAEAS
PAFAS
OEA
DS17
DS16
9 8 7 6 5 4 3 2 L J 686766656463 6261
::: 10
1
60::
::: 11
59::
::: 12
58::
57::
56::
55::
54::
53::
J68-1
52::
51::
50::
49::
48::
47::
46::
45::
::: 26
44::
2728293031323334353637383940414243
rlrlrlrlrlrlrlrlrlrlrlrlrlrlrlrlrl
DA2
DA1
DAO
EFsA
FFBA
PAEsA
PAFsA
GND
BYPs
OEs
ENs
RlWs
ClKs
RS
DBa
DS1
DS2
~~~~~~~~~aaaaa~aa
CJ
CJ
oCJooooo
PLCC
Top View
5.17
2704 dIW03
2
10T72605/10T72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
110
1/0
Description
DAO-DA17
Data A
CSA
Chip Select A
I
Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.
RlWA
ReadIWrite A
I
This pin controls the read or write direction of Port A. If RlWA is LOW, Data A input data is
written into Port A. If RfWA is HIGH, Data A output data is read from Port A. In bypass mode,
when RfWA is LOW, message is written into A~8 output register. If RfWA is HIGH, message
is read from 8~A output register.
CLKA
Clock A
I
CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of
CLKA.
ENA
Enable A
I
When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data
transfers occur.
OEA
Output Enable A
I
When RlWA is HIGH, Port A is an output bus and OEA controls the high impedance state of
DAD-DA17. If OEA is HIGH, Port A is in a high impedance state. If OEA is LOW while CSA is
LOW and RfWA is HIGH, Port A is in an active (low impedance) state.
I
When CSA is asserted, Ao, A1, A2 and RlWA are used to select one of six internal resources.
Ao, A1, A2 Addresses
1/0
Data inputs & outputs for the 18-bit Port A bus.
Data inputs & outputs for the 18-bit Port 8 bus.
DBO-DB17
Data 8
RlWB
ReadIWrite 8
I
This pin controls the read or write direction of Port 8. If RlWB is LOW, Data 8 input data is
written into Port 8. If RfWB is HIGH, Data 8 output data is read from Port 8. In bypass mode,
when RfWB is LOW, message is written into A~8 output register. If RfWB is HIGH, message
is read from 8~A output register.
ClKB
Clock 8
I
Clock 8 is typically a free running clock. Data is read or written into Port 8 on the rising edge
of ClKB.
ENB
Enable 8
I
When ENB is LOW, data can be read or written to Port 8. When ENB is HIGH, no data
transfers occur.
OEB
Output Enable 8
I
When RlWB is HIGH, Port 8 is an output bus and OEB controls the high impedance state of
DBO-DB17. If OEB is HIGH, Port 8 is in a high impedance state. If OEB is LOW while RfWB
is HIGH, Port 8 is in an active (low impedance) state.
EFAB
A~8
PAEAB
A~8
Empty Flag
0
When EFAB is lOW, the A~8 FIFO is empty and further data reads from Port 8 are inhibited.
When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to ClKB. In the bypass
mode, EFAB HIGH indicates that data DAD-DA17 is available for passing through. After the
data DBO-DB17 has been read, EFAB goes LOW.
0
When PAEAB is LOW, the A~8 FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, t~
A~8 FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB
Register is 8. PAEAB is synchronized to CLKB.
0
When PAFAB is LOW, the A~8 FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH,
the A~8 FIFO contains less than or equal to the depth minus the offset in PAFAB Register.
The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.
Programmable
Almost-Empty Flag
PAFAB
A~8
Programmable
Almost-Full Flag
FFAB
A~8
Full Flag
0
When FFAB is LOW, the A~8 FIFO is full and further data writes into Port A are inhibited.
When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLI VIN:,> Vee.
2. OE ~ VIH; 0.4 :'> VOUT:,> Vee.
3. Tested with outputs open. Testing frequency f=20MHz
5.17
4
10T72605/10T72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
+5V
In Pulse levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output load
GND t03.0V
3ns
1.5V
1.5V
See Figure 2
un
D.U.T. - - - . . . . - -....
680n
2704tbl07
30pF*
or equivalent circuit 2704 drw 05
Figure 2. Output Load
• Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = SV±10%, TA = O°C to +70°C; Military: Vce = SV±10%, TA = -SsoC to +12S°C)
Com'J.
Symbol
Parameter
Mil.
Com'l. and Mil.
IDT72615L25 IDT72615L30 IDT72615L35 IDT72615L50
IDT72605L25 IDT72605L30 IDT72605L35 IDT72605L50
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
Timing Figures
fCLK
Clock frequency
-
40
-
33
-
28
-
20
MHz
tCLK
Clock cycle time
25
-
50
-
ns
4,5,6,7
10
12
-
35
Clock high time
14
4,5,6,7,12,13,14,15
10
12
-
14
20
tRS
Reset pulse width
25
-
30
35
tRSS
Reset set-up time
15
18
21
-
30
tRSR
Reset recovery time
15
-
-
-
ns
Clock low time
-
20
tCLKL
-
30
tCLKH
18
-
21
-
30
tRSF
Reset to flags in intial state
-
25
-
30
-
35
-
50
-
ns
4,5,6,7,12,13,14,15
ns
3
-
ns
3
ns
3
50
ns
3
tA
Data access time
3
15
3
18
3
21
3
25
ns
5,7,8,9,10,11
tcs
Control signal set-up time(1)
6
-
7
-
8
-
10
-
ns
4,5,6,7,8,9,10,11,12,
13,14,15
tCH
Control signal hold time(1)
1
-
1
-
1
-
1
-
ns
4,5,6,7,10,11,12,13,
14,15
4,6,8,9,10,11
tDS
Data set-up time
6
-
7
-
10
1
-
1
1
-
1
-
ns
Data hold time
-
8
tDH
ns
4,6
tOE
Output Enable lOW to
output data valid(2)
3
13
3
16
3
20
3
28
ns
5,7,8,9,10,11
tOLZ
Output Enable lOW to data
bus at low Z(2)
0
-
0
-
0
-
0
-
ns
5,7,8,9,10,11
tOHZ
Output Enable HIGH to data
bus at high Z(2)
3
13
3
16
3
20
3
28
ns
5,7,10,11
tFF
Clock to Full Flag time
-
21
-
30
ns
4,6,10,11
18
-
21
-
30
ns
5,7,8,9,10,11
tPAE
Clock to Programmable
Almost Empty Flag time
15
-
18
Clock to Empty Flag time
-
15
tEF
18
-
21
-
30
ns
12,14
tPAF
Clock to Programmable
Almost Full Flag time
-
15
-
18
-
21
-
30
ns
13,15
tSKEWl
Skew between ClKA & ClKs
for Empty/Full Flags(2)
12
-
15
-
17
-
20
-
ns
4,5,6,7,8,9,10,11
tSKEW2
Skew between ClKA & ClKs
for Programmable Flags(2)
19
-
22
-
25
-
34
-
ns
4,7,12,13,14,15
15
2704tb108
NOTES
1. Control Signals refer to eSA, RiWA, ENA, A2, At, Ao, RiWB, ENB.
2. Minimum values are guaranteed by design.
5.17
5
10172605/10172615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
RESET
lOT's SyncBiFIFO is versatile for both multiprocessor and
peripheral applications. Data can be stored or retrieved·
from two sources simultaneously.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Two dual-port FIFO
memory arrays are contained in the SyncBiFIFO; one data
buffer for each direction. Each Port has its own independent
clock. Data transfers to the I/O registers are gated by the
enable signals. The transfer direction for each port is
controlled independently by a read/write signal. Individual
output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines,
, are in a high impedance state. The processor connected to
Port A of the BiFIFO can send or receive messages directly
to the Port B device using the 18-bit bypass path.
The SyncBiFIFO can be used in multiples of 18-bits. In a
36- to 36-bit configuration,' two SyncBiFIFOs operate in
parallel. Both devices are programmed simultaneously, 18
data bits to each device. This configuration can be extended
to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by
adding more SyncBiFIFOs to the configuration. Figure 1
show multiple SyncBiFIFOs configured for multiprocessor
communication.
The microprocessor or microcontroller connected to Port
A controls all operations of the SyncBiFIFO. Thus, all Port
A interface pins are inputs driven by the controlling
processor. Port B interfaces with a second processor. The
Port B control pins are inputs driven by the second
processor.
Reset is accomplished whenever the Reset (RS) input is
taken to a low state with GSA, ENA and ENB HIGH. During
reset, both internal read and write pointers are set to the
first location. A reset is required after power up before a
write operation can take place. The A~B and B~A FIFO
Empty Flags (EFAB, EFBA) and Programmable Almost Empty
Flags (PAEAB, PAEBA) will be set to low after tRSF. The
A~B and B~A FIFO Full Flags (FFAB, FFBA) arid
Programmable Almost Full Flags (PAFAB, PAFBA) will be
set to high after tRSF. After the reset, the offsets of the
Almost-Empty Flags and Almost- Full Flags for the A~B
and B~A FIFO offset default to 8.
PORT A INTERFACE
The SyncBiFIFOTM is straightforward to use in microprocessor-based systems because each port has a standard
microprocessor control set. Port A interfaces with
microprocessor through the three address pins (A2-Ao) and
a Ghip Select GSA pins. When GSA is asserted, A'i,A1,Ao
and RiwA are used to select one of six internal resources
(Table 1).
With A2=0 and A1=0, Ao determines whether data can
be read out of output register or be written into the FIFO
(Ao=O), or the data can pass through the FIFO through the
bypass path (Ao=1).
With A2=1, four programmable flags (two A~B FIFO
programmable flags and two B~A FIFO programmable
flags) can be selected: the A~B FIFO Almost-Empty Flag
Offset (A1 =0, Ao=O), A~B FIFO Almost-Full Flag Offset
(A1=0, Ao=1), B~A FIFO Almost-Empty Flag Offset (A1=1,
Ao=O), B~A FIFO Almost-Full Flag Offset (A1=1, Ao=1).
Port A is disabled when GSA is deasserted and data A is
in high impedance state.
IDT
SYNCBIFIFO
DATAB
~ DATA A
ClKs
ClKA
CONTROL A CONTROL B
ClK
MICROPROCESSOR
A
DATA
ADDR, I/O
RAM A
~CONTROllr-lOGIC
..
•
~
---
IDT
SYNCBIFIFO
DATA A
DATA B
ClKs
ClKA
CONTROL A CONTROL B
-.
-
ClK
MICROPROCESSOR
B
DATA
_1CONTROl~
lOGIC
---
....
11
-I
ADDR 1/0
'
I
RAMB
SYSTEM
CLOCK B
SYSTEM
CLOCK A
2704 drw 04
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2, Control A Consists of RiWA, ENA, OEA, CSA, A2, Al, Ao. Control B consists of RiWs, ENs, OEB.
Figure 1. 36· to 36·bit Processor Interface Configuration
5.17
6
EI
10T72605110T72615
PARALLEL SyncBiFIFO
CSA
0
RtWA
0
ENA
0
OEA
Data A
1/0
0
I
Data A is written on CLKA t. This write cycle immediately following
low impedance cycle is prohibited.
0
0
0
0
0
1
0
1
0
1
X
0
I
I
0
Data A is written on CLKA
Data A is ignored
0
1
0
1
0
0
0
1
1
1
1
0
1
1
1
X
X
0
1
X
X
0
0
I
0
Data is read (1) from RAM array to output register on CLKA t.
Data A is high impedance
Output register does not change (2), Data A is low impedance
Output register does not change(2), Data A is high impedance
Data A is ignored (3)
NOTES
1. When A2A1Ao
2.
3.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port A Operation
t.
Data is read II} from RAM array to output register on CLKA t,
Data A is low impedance
Data A is high impedance(3)
2704 tbl 09
= 000, the next B~A FIFO ~alue is r~ad ~ut of the output register and the read pointer advances. If A2A1Ao = 001, the bypass path is
sele~ted and ?ypass data from the Port B Input register IS read from the Port A output register. If A2A1AoO = 1XX, a flag offset register is selected
and Its offset IS read out through Port A output register.
.
Regar~less of the condition. of A2A1Ao, the data in the Port A output register does not change and the B~A read pointer does not advance.
If CSA IS HIGH, then BYPB IS HIGH. No bypass occur under this condition.
Table 1.
Port A Operation Control Signals
BYPASS PATH
The bypass paths provide direct communication between
Port A and Port B. There are two full 18-bit bypass paths,
one in each direction. During a bypass operation, data is
passed directly between the input and output registers, and
the FIFO memory is undisturbed.
Port A initiate~d terminates all bypass operations.
The bypass flag, BYPB, is asserted to inform Port B that a
bypass operation is beginning. The bypass flag state is
controlled by the Port A controls, although the BYPB signal
is synchronized to ClKB. So, BYPB is asserted on the next
rising edge of ClKB when A2A1Ao=001and CSA is low.
When Port A returns to normal FIFO mode (A2A1Ao=OOO or
CSA is High), BYPB is deasserted on the next ClKB rising
edge.
Once the SyncBiFIFO is in bypass mode, all data transfers
are controlled by the standard Port A (RlWA, ClKA, ENA,
OEA) and Port B (RlWB, ClKB, ENB, OEB) interface pins.
Each bypass path can be considered as a one word deep
FIFO. Data is held in each input register until it is read.
Since the controls of each port operate independently, Port
A can be reading bypass data at the same time Port B is
reading bypass data.
When R/WA and ENA is lOW, data on pins DAO-DA17 is
written into Port A input register. Following the rising edge
of ClKA for this write, the A-tB Full Flag (FFAB) goes lOW.
Subsequent writes into Port A are blocked by internal logic
until FFAB goes HIGH agai~ On the next ClKB rising
edge, the A-tB Empty Flag (EFAB) goes HIGH indicating to
Port B that data is available. Once R/WB is HIGH and ENB
is lOW, data is read into the Port B output register. OEs
still controls whether Port B is in a high-impedance state.
When OEB is lOW, the output register data appears at DBoDB17. EFA~oes lOW following the ClKs rising edge for
this read. FFAS goes HIGH on the next ClKA rising edge,
letting Port A know that another word can be written through
the bypass path.
.
Bypass data transfers from Port B to Port A work in a
similar manner with EFsA and FFBA indicating the Port A
output register state.
When the Port A address changes from bypass mode
(A2A1Ao=001) to FIFO mode (A2A1Ao=OOO) on the rising
edge of ClKA, the data held in the Port B output register
may be overwritten. Unless Port A monitors the BYPs pin
and waits for Port B to clock out the last bypass word, data
from the A-tB FIFO will overwrite data in the Port B output
register. BYPs will go HIGH on the rising edge of GlKB
signifying that Port B has finished its last bypass operation.
Port B must read any bypass data in the output register on
this last ClKs clock or it is lost and the SyncBiFIFO returns
~IFO operations. It is especially important to monitor
BYPs when GlKs is much slower than GlKA to avoid this
condition. BYPB will also go HIGH after GSA is brought
HIGH; in this manner the Port B bypass data may also be
lost.
Since the Port A processor controls CSA and the bypass
mode, this scenario can be handled for B-tA bypass data.
The Port A processor must be set up to read the last bypass
word before leaving bypass mode.
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various
operations shown in Table 2. Port A is accessed when
GSA is lOW, and is inactive if GSA is HIGH. RlWA and ENA
lines determine when Data A can be written or read. If RI
WA and ENA are lOW, data is written into input register on
the low-to-high transition of ClKA. If RlWA is HIGH and
OEA is lOW, data comes out of bus and is read from
output register into three-state buffer. Refer to pin
descriptions for more information.
5.17
7
10172605/10172615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I
CSA
A2
A1
Ao
Read
0
0
0
0
B-+A FIFO
0
0
0
1
18-bit Bypass Path
0
1
0
0
A-+B FIFO Almost-Empty
Flag Offset
0
1
0
1
A-+B FIFO Almost-Full
Flag Offset
0
1
1
0
B-+A FIFO Almost-Empty
Flag Offset
0
1
1
1
B-+A FIFO Almost-Full
Flag Offset
1
X
X
X
Port A Disabled
Write
I A-+B FIFO
2704tbl to
Table 2. Accessing Port A Resources Using CSA, A2, A1, and Ao
PROGRAMMABLE FLAGS
The lOT SyncBiFIFO has eight flags: four flags for A~B
FIFO (EFAS, PAEAs, PAFAS, FFAS) , and four flags for B~A
FIFO (EFsA, PAEsA, PAFsA, FFsA). The Empty and Full
flags are fixed, while the Almost Empty and Almost Full
offsets can be set to any depth through the Flag Offset
Registers (see Table 3). The flags are asserted at the
depths shown in the Flag Truth Table (Table 4). After
reset, the programmable flag offsets are set to 8. This
means the Almost Empty flags are asserted at Empty + 8
PAEAB Register
PAFAB Register
PAEBA Register
PAFBA Register
words deep, and the Almost Full flags are asserted at Full 8 words deep.
The PAEAs is synchronized to CLKs, while PAFAS is
synchronized to CLKA; and PAEsA is synchronized to CLKA,
while PAFsA is synchronized to CLKs. If the minimum time
(tsKEW2) between a rising CLKs and a rising CLKA is met,
the flag will change state on the current clock; otherwise,
the flag may not change state until the next clock rising
edge. For the specific flag timings, refer to Figures 12-15.
17
16
15
14
13
12
11
10
9
X
X
X
X
X
X
X
X
X
17
16
15
14
13
12
11
10
X
X
X
X
X
X
X
9
X
8
X
17
16
15
14
13
12
11
10
X
X
X
X
X
9
X
8
X
17
16
15
14
13
12
X
X
X
X
X
9
X
8
X
IX IX
11
10
IX IX
8
7
6
5
4
3
0
2
A-+B FIFO Almost-Empty Flag Offset
7
6
5
4
3
0
2
A-+B FIFO Almost-Full Flag Offset
7
6
5
4
3
0
2
B-+A FIFO Almost-Empty Flag Offset
7
6
5
4
3
2
0
B-+A FIFO Almost-Full Flag Offset
2704 tblll
NOTE:
1. Sit 8 must be set to 0 for the 10172605 (256 x 18) Synchronous SiFIFO.
Table 3. Flag Offset Register Format
Number of Words
In FIFO
To
From
0
EF
m
PAF
FF
0
Low
Low
High
High
1
n
High
Low
High
High
n+1
D-(m+1)
High
High
High
High
D-m
0-1
High
High
Low
High
0
0
High
High
Low
Low
n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
= FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
2704 tbl12
o
Table 4. Internal Flag Truth Table
5.17
8
EI
IDT72605/IDT72615
PARALLEL SyncBIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PORT B CONTROL SIGNALS
The Port B control signal pins dictate the various
operations shown in Table 5. Port B is independent of
GSA.
RiwB and ENB lines determine when Data can be
written or read in Port B. If R/WB and ENB are LOW, data
is written into input register, and on low-to-high transition of
GlKs data is written into input register and the FIFO memory.
RiWB
ENs
~
Data B
If 0
0
0
0
I
0
0
1
X
1
0
1
0
0
I
I
0
1
0
1
0
1
1
1
1
0
,1
0
0
If R/WB is HIGH and OEB is LOW, data comes out of bus
and is read from output register into three-state buffer.. In
bypass mode; if R/WB is lOW, bypass messages are
transferred into B-7A output register. If R/WA is HIGH,
bypass messages are transferred into A-7B output register.
Refer to pin descriptions for more information.
Port B Operation
Data B is written on elKB i. ,This write cycle immediately following output low
impedance cycle is prohibited
Data B is written on elKB i.
Data B is ignored
Data is read(1) from RAM array to output register on elKB
impedance
Data is read(1) from RAM array to output register on elKs
i,
Data B is lo~
i. Data B is high
impedance
Output register does not change(2) , Data B is low impedance
Output register does not change(2), Data B is high impedance .
2704tbl13
NOTES:
1. When A2A1Ao = 000 or 1XX, the next A7B FIFO value is read out of the output register and the read pointer advances. If A2A1Ao = 001, the bypass
path is selected and bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1Ao, the data in the Port B output register does not change and the A-tB read pointer does not advance.
Table 5. Port B Operation Control Signals
5.17
9
IDT72605I1DT72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tRS------------~
EFAS.
PAEAS.
EFsA.
PAEsA
EFAS.
PAEAS.
EFsA.
PAEsA
CSA.
~~~
.
/ZZZZZ
~
tRss------~.~!4~-------'tRSR--------~~~~_______________
2704 drw 06
Figure 3. Reset Timing
DAO-DA17
elKs
NO READ
OPERATION
2704 drw07
Figure 4. Port A (A-tB) Write Timing
5.17
10
IDT72605/IDT72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ClKA
AO,A1,A2,
~~~lI.L...~
CSA
ENA
EFBA
DAO-DA17
----------t-----"'tOLZ
OEA
ClKs
NO WRITE
2704drw 08
Figure 5. Port A (B-7A) Read Timing
~------------tCLK------------~
tCLKH ----~I-----
ClKs
RIWB
ENs
FFsA
Dso-Ds17
ClKA
NO READ
OPERATION
READ
2704 drw 09
Figure 6. Port B (B-7A) Write Timing
5.17
11
10172605/10172615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ClKB
RlVVB
ENB
EFAB
OBO-OB17
---------+--..,-----<
tOll
OEB
ClKA
NO WRITE
OPERATION
2704 drw 10
Figure 7. Port B (A-+B) Read Timing
II
5.17
12
IDT72605/IDT72615
PARALLEL SyncBIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLKA
tDS
DAO-DA17
C3
D1
~-------·tFRL------~
CLKe
RlWe
ENe
Deo-DB17
tA?
--------t~XXXXXtA~_ D _ o_~_C_1_
_ _ _{tOLZ--l'
tOE
~
2704 drw
11
NOTE:
1. When tSKEW1 ~ minimum specification, IFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, IFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (s: = Low).
Figure 8. A-tB First Data Word Latency after Reset for Simultaneous Read and Write
5.17
13
IDT72605/IDT72615
PARALLEL SyncBIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLKB
RlWB
ENB
lOS
02
01
OBO-OB17
14-----tFRL ---~
CLKA
CSA ,E~
_ _---...{IO~~ - tOE • 3
•
tA-:j.__
_____ _JK
tA~
~xXxxX
OAO-OA17
0_0
0_1_
2704 drw 12
NOTE:
1. When tSKEW1 ~ minimum specification, tFAL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFAL(Max.) = 2tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = Low).
Figure 9.
B~A
First Data Word Latency after Reset for Simultaneous Read and Write
5.17
14
IDTI2605/1DT72615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ClKA
A2,A1,Ao,= 001
RlWA
FFAs
FIFO FLAG
DAO-DA17
ClKs
RIWB
ENs
EFAS
BYPASS FLAG
FIFO FLAG
FIFO FLAG
BYPs
Dso-Ds17
OEs
>I
DATA OUTPUT
~-tO-H-Z-~---------
____________________________________________
2704 drw 13
NOTES:
1. When CSA is brought HIGH, A~B Bypass mode will switch to FIFO mode on the following CLKA low-to-high transition.
2. After the bypass operation is completed, the BVPe goes from low-to-high; this will reset all bypass flags. The bypass path becomes available for the
next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 10.
A~B
Bypass Timing
5.17
15
10172605110172615
PARALLEL SyncBiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ClKB
RlWB
ENB
BYPB
DBO-DB17
ClKA
AO,A1,A2,
A2 ,A1,Ao, = 001
ENA
EFBA
BYPASS FLAG
FIFO FLAG
DATA OUTPUT
DAO-DA17
OEA
>I-
~--------------------------------------~
2704 drw 14
NOTES:
1. When CSA is brought HIGH, A-tB Bypass mode will switch to FIFO mode on the following CLKA going low-to-high.
2. After the bypass operation is completed, the BVPs goes from low-to-high; this will reset all bypass flags. The bypass path becomes available for the
next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 11. B-tA Bypass Timing
5.17
16
10172605110172615
PARALLEL SyncBIFIFO
C:::,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
l
(RlWA'O)
PAEAS
l
<
WRITE
I
n words in FIFO
'
H
, '
n+1 words in FIFO
ClKs
READ
2704 drw 15
NOTES:
1. tSKEW2 the minimum time between a rising ClKA edge and a rising ClKs ~e for PAEAs to change during that clock cycle. If the time between the
rising edge of ClKA and the rising edge of ClKs is less than tSKEW, then PAEAs may not go HIGH until the next ClKS rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes low.
Figure 12.
A~B
Programmable Almost-Empty Flag Timing
ClKA
ENA
(AlWA= 0)
NOTES:
1. tSKEW2 is the minimum time between a rising ClKs edge and a rising ClKA edge for PAFAS to change during that clock cycle. If the time between the
rising edge of ClKs and the rising edge of ClKA is less than tSKEW2, then PAFAB may not go HIGH until the next ClKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes low.
Figure 13.
A~B
Programmable Almost-Full Flag Timing
5.17
17
10172605110172615
PARALLEL SyncBiFIFO
ClKs
ro~H
MILITARY AND COMMERCIAL TEMPERATURE RANGES
mLR
~si\
ENs
(RiWA= 0)
PAESA
(it
WRITE
n words in
~IFO
n+1 words in FIFO
ClKA
READ
2704 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising ClKB edge and a rising ClKA edge for PAEBA to change during that clock cycle. If the time between the
rising edge of ClKB and the rising edge of ClKA is less than tSKEW2, then PAEBA may not go HIGH until the next ClKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FI FO when PAE goes low.
Figure 14. B~A Programmable Almost-Empty Flag Timing
II
ClKs
ENs
(RiWA= 0)
WRITE
Full- m words in FIFO
Full- (m+1) words in FIFO
elK',.~
t~
tCSi\
ENA
(RiWA= 1)
(itcH
READ
2704 drw 18
NOTES:
1. tSKEW2 is the minimum time between a rising ClKB edge and a rising ClKA edge for PAFBA to change during that clock cycle. If the time between the
rising edge of ClKB and the rising edge of ClKA is less than tSKEW2, then PAFBA may not go HIGH until the next ClKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes low.
Figure 15. B~A Programmable Almost-Full Flag Timing
5.17
18
G®
PARALLEL ASYNCHRONOUS
SINGLE-BANK BIDIRECTIONAL FIFO
512 X 9-BIT, 1024 x 9-BIT, 2048 x 9-BIT
PRELIMINARY
IDT7271
IDT7272
IDT7273
Integrated Device Technology, Inc.
FEATURES:
• Bidirectional data transfer
• 512 x 9 organization (IDT7271)
• 1024 x 9 organization (IDT7272)
• 2048 x 9 organization (IDT7273)
• Fast 25ns access time
• Single bank FIFO memory with data flow in one direction
ata time
• Direction pin controls data flow from Port A-to-B, or Port
B-to-A
• Full and Empty flags
• Fixed Almost-Full and Almost-Empty partial flags
• Bypass and Diagnostic modes
• 32-pin DIP, PLCC, LCC and SOJ
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7271/727217273 are very high speed, low power
FIFO memories that enhance processor-to-processor and
processor-to-peripheral communications. The 727x family
use a single bank of memory; therefore, allowing one port to
be accessed at any time. A direction pin (DIR) is provided to
determine data flow direction. When the DIR pin is Low, data
flows from port A-to-B. Data flows in the opposite direction
when the DIR pin is High.
A device reset can be initiated at any time by bringing the
Reset (RS) pin LOW while holding the Read (RD) , Bypass
(BYP), Diagnostic (DIAG) and Write (WR) pins High.
There are four separate flags on these BiFIFOs. The two
end-point flags are Empty (EF) and Full (FF); and the two
partial flags with fixed offset size of 07H (eight bytes from the
boundaries) are Almost-Empty (AE) and Almost-Full (AF); All
flags are active low.
Bypass control allows data to be directly transferred from
port A to port B, or vice versa, without going through the
memory array. The bypass mode can be set by asserting the
BYP pin (active Low).
The diagnostic mode allows written data to be read through
the same port. This provides systems memory self-test upon
power up or after a system failure.
The IDT7271/2/3 are fabricated using IDT's high speed
submicron CEMOSTM technology. Military grade products are
manufactured in compliant with the latest revision of MILSTD-883, Class B.
FUNCTIONAL BLOCK DIAGRAMS
DATA PORTA
(DQAo-DQAs)
DUAL PORT RAM
ARRAY
2048 X 9
1024 X 9
512 X 9
AFF~----------~
AEF~----------~
FF
~----------
EF~
RS
RDA
WRA
DIR
BYP
FLAG
LOGIC
________~ I I I__~_~~
CONTROL
LOGIC
ROB
WRB
DIAG
2529 drw 01
CEMOS and SyncFIFO are trademarks of Integrated Device Techology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
©1992 Integrated Device Technology, Inc.
DSC·204711
5.18
IDT7271/IDT7272/1DT7273 PARALLEL ASYNCHRONOUS
SINGLE-BANK BIDIRECTIONAL FIFO 512 x 9-BIT, 1024 x 9-BIT & 2048 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
D0A4
2
31
DOAs
D0A2
3
30
D0A7
D0A1
4
29
DOAs
DOAo
5
28
Ei=
AE
6
27
DIR
WRA
7
GND
8
WRB
AF
INDEX
D0A5
D0A3
P32-1
26
RDA
25
Vee
9
24
RS
10
23
ROB
DIAG
11
22
BYP
DOBO
12
21
FF
4
13
20
DOss
DOB2
14
19
DOB7
DOB3
15
18
DOBS
DOB4
16
17
DOB5
3
2
LJ
32 31 30
1
29
J32-1
L32-1
DOAs
28
EF
27
DIR
26
RDA
25
Vee
11
23
ROB
12
22
BYP
21
FF
RS
._,
DOB1
DIP
TOP VIEW
l.J L.J L.J i i l.j L.J L.J
.J 13
J.1 !§.
.t~
.E
.qIII
III
J-~ L~
gg
I II II II II I I II I
co
N
C')
III
III
o
000 0
I.()
III
,.....
co
III
III
0
0
0000000
PLCC/LCC
TOP VIEW
2529 drw 02
2529 drw 03
PIN DESCRIPTION
Symbol
Name
110
Description
DQAo-DQAs
Data A
110
9-bit data pins for port A. The DIR pin controls direction of these pins (input or output)
DQBo-DQBs
Data B
I/O
9-bit data pins for port B. The DIR pin controls state of these pins (inputs or outputs)
RDA
Read A
I
This input pin controls port A read operation. In bypass mode this pin controls the A port
output enables. Active Low input.
ROB
Read B
I
This input pin controls port B read operation. Active Low input.
WRA
Write A
I
This input pin controls port A write operation. In bypass mode this pin controls the port B
output enables. Active Low input.
WRB
WriteB
I
This input pin controls port B write operation. Active Low input.
DIR
Direction
I
This input pin determines data flow direction. When it is Low, data flows from port A to
port B. When it is High, data flows in the opposite direction.
DIAG
Diagnostic
I
Once the data is loaded, the DIAG pin can be asserted followed by the DIR pin's state
change, the written data can then be read through the same port.
BYP
Bypass
I
This input pin sets the FIFO in the bypass mode, in which the FIFO acts as a transceiver.
Active Low input.
RS
Reset
I
This pin resets all functions. Active Low input.
AE
Partial Flag
0
This output pin is asserted when the FIFO is almost empty. Active Low output.
AF
Partial Flag
0
This output pin is asserted when the FIFO is almost full. Active Low output.
FF
Full Flag
0
This output is asserted when the FIFO is completely full. Active Low output.
EF
Empty Flag
0
This output is asserted when the FIFO is completely empty. Active Low output.
Vee
Power
One +5V power pins.
GND
Ground
One ground pin at OV.
2529 tbl 01
5.18
2
1017271/1017272/1017273 PARALLEL ASYNCHRONOUS
SINGLE·BANK BIDIRECTIONAL FIFO 512 x 9·BIT, 1024 x 9·BIT & 2048 x 9·BIT
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Com'l.
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
TSIAS
Mil.
o to +70
V
Symbol
-55 to +125
°C
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +155
°C
lOUT
DC Output
Current
50
50
RECOMMENDED DC
OPERATING CONDITIONS
Unit
-0.5 to +7.0 -0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
mA
NOTE:
2529 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
Parameter
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vccc
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
VIH
Input High Votage
Commercial
2.0
-
-
V
VIH
Input High Votage
Military
2.2
-
-
V
VIL(l)
Input Low Voltage
Com'l. and Mil.
-
-
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
V
2529 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5.0V
± 10%, TA =
O°C to +70°C; Military: Vcc = 5.0V
± 10%, TA = ·55°C + 125°C)
ID17271L
ID17272L
ID17273L
Commercial
tA 25, 35, SOns
Min.
Max.
Typ.
=
Symbol
Parameter
IIL(l)
Input Leakage Current (Any Input)
IOL(2)
Output Leakage Current
·10
VOH
Output Logic "1" Voltage IOUT= -2mA
2.4
VOL
Output Logic "0" Voltage lOUT = 8mA
ICC1(3)
Average VCC Power Supply Current
-
Icc2(3)
·1
Average Standby Current (RA = WA =
RS = VIH)
Rs = Ws =
Icd3)
-
Power Down Current (All Inputs = Vcc 0.2V)
=
Max.
Unit
1
·10
-
10
10
·10
-
10
J.IA
J.IA
-
2.4
-
-
0.4
-
-
0.4
V
100
150
mA
15
-
12
25
mA
8
-
-
12
mA
75
120
8
-
tA
Min.
ID17271L
ID17272L
ID17273L
Military
30, 35, SOns
Typ.
NOTES:
1. Measurements with 0.4 ::; VIN ::; Vcc.
2. OE ~ VIH, 0.4 ::; Your ::; Vcc.
3. Tested at f = 20 MHz.
V
2529tbl04
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figure 1
1.1Kn
D.U:r.--.--...
2529 tbl 05
CAPACITANCE(1)
Symbol
CIN(3)
COUT(2,3)
(TA = +25°C,
f=
680n
30pF*
1.0 MHz)
Parameter
Condition
Max.
Unit
Input Capacitance
VIN = OV
10
pF
Output Capacitance
VOUT= OV
10
pF
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
3. Characterized values, not currently tested.
or equivalent circuit
2529 drw04
Figure 1. Output Load
2529 tbl 06
"Includes jig and scope capacitances.
5.18
3
IDT7271/IDT72721IDT7273 PARALLEL ASYNCHRONOUS
SINGLE-BANK BIDIRECTIONAL FIFO 512 x 9-BIT, 1024 x 9-BIT & 2048
x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ACELECTRICAL CHARACTERISTICS
(Commercial: Vce = 5.0V ± 10%, TA = O°C to +70°C; Military: Vee = 5.0V ± 10%, TA = -55°C + 125°C)
Symbol Parameter
Reset Timing
tRSC
Reset Cycle Time
Reset Pulse Width
tRS
tRSS
Reset Set-up Time
Reset Recovery Time
tRSR
tRFV
Reset to Flag Valid
ReadlWrite Timing
Read Access Time
tA
tRC
Read Cycle Time
Read Pulse Width
tRPW
Read Recovery Time
tRR
Data valid from read pulse HIGH
tov
Read HIGH to data bus at High Z
tRHZ
Read LOW to data bus at Low Z
tRLl
Write Cycle Time
twc
twpw
Write Pulse Width
Write Recovery Time
tWR
Data Set-up Time
tos
Data Hold Time
tOH
Direction Change, Diagnostic and Bypass Timing
DIR Change to Write Low
tOFWL
DIR Change to Valid Flags
tOFV
DIR Change to Read Low
tORL
DIR Change to DIAG High
tDHOGL
DIR Setup
tORSU
tOGLOC
DIAG Low to DIR Change
DIAG High to Write Low
tOGHWL
DIAG Low to Write Low (either port)
tOGWR
tSYSU
BYP Set-up Time
Bypass Access Time
tSYA
Bypass Delay Time
tSYO
Flag Timing
tFEFV
Fu" or Empty Flag Valid
tAFAEV
Almost-Fu" or Empty Flag Valid
Commercial
IDT7271L25
IDT7272L25
IDT7273L25
Min.
Max.
35
25
25
10
35
25
10
3
-
Military
IDT7271L30
IDT7272L30
IDT7273L30
Max.
Min.
Commercial and Military
IDT7271L35
IDT7271L50
IDT7272L35
IDT7272L50
IDT7273L35
IDT7273L50
Min.
Max.
Min.
Max.
-
-
-
65
50
50
15
35
-
50
-
35
-
50
-
-
-
40
30
30
10
-
45
35
35
10
25
-
30
-
-
25
-
30
-
40
30
10
3
-
-
-
-
-
-
-
-
45
35
10
3
-
65
50
15
3
20
-
20
-
-
-
3
65
50
15
30
5
-
-
-
18
-
3
35
25
10
15
0
-
-
3
40
30
10
18
0
-
3
45
35
10
18
1
25
-
30
-
35
-
50
-
-
20
-
25
-
30
45
20
0
10
10
25
10
10
-
25
0
15
15
30
15
15
-
30
1
20
20
35
20
20
-
-
-
35
5
30
30
50
30
30
-
-
25
25
-
30
30
-
35
35
20
35
-
25
40
-
30
45
-
-
-
-
-
-
-
-
-
30
-
-
-
50
50
40
65
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2529 tbl 07
5.18
4
1017271/1017272/1017273 PARALLEL ASYNCHRONOUS
SINGLE-BANK BIDIRECTIONAL FIFO 512 x Q-BIT, 1024 x Q-BIT & 2048 x Q-BIT
FUNCTIONAL DESCRIPTION
lOT's Single-Bank BiFIFO family is versatile for both multiprocessor and peripheral applications. The 727x family is a
low-cost solution for bidirectional systems where data flow in
only one direction at a time is needed. The Single-Bank
BiFIFO implies that there is only one bank of memory shared
by two ports, with a direction pin provided for altering data flow
direction.
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the writing
side; EF is monitored on the reading side). In general a write
cycle cannot be allowed to begin if FF is asserted and a read
cycle cannot be allowed to begin if EF is asserted. For additional information, refer to Tech Note 8: Operating FIFOs on
Full and Empty Boundary Conditions and Tech Note 6: De-
signing with FIFOs.
Reset
A reset is initiated by bringing the Reset (RS) pin Low, while
holdin9.!b..e Read (RD), Bypass (BYP), Diagnostic (DIAG) and
Write (WR) pins High. After a device reset, all internal pointers
are cleared and flags are adjusted accordingly. For proper
device operation, all control inputs pins must be stable before
the reset signal is deasserted. A recovery time is required
before loading the device or altering operation mode (Bypass,
Diagnostic, etc).
Flags
There are four separate flags on the 7271/2/3 BiFIFO, two
partial flags, a full flag and an empty flag. All are active low.
The two~rtial flags are the Almost Full (AF) and the Almost
Empty (AE) flags, each with a fixed offset size of 07H (eight
bytes from the empty or full conditions). These can be used
as an early warnif!9..signal. The two other flags are fixed at
Empty EF and Full FF. These are asserted during the last read
or write operation respectively. These are used to prevent
device overflow or underflow.
Data Flow Direction
MILITARY AND COMMERCIAL TEMPERATURE RANGES
By asserting the WRA, data on the A port will be driven out the
B port. By assertin~ RDA, data on the B port will be driven
out theA port. The WRA signal is used to enable the B ~ort's
bus drivers. The RDA signal is used enable the A ports. WRA
and RDA must not be low at the same time.
Entering and exiting the bypass mode does not affect the
. internal pointers. The state of the DIR pin is ignored in the
bypass mode. If DIR changes state in Bypass mode, the
pointers will not reset until leaving the Bypass mode. If DIR
changes state momentarily in Bypass mode there is no effect.
Bypass mode does not alter flag states.
Diagnostic Mode
Many systems require memory testing upon power up or
after a system failure. The 727x family has a built-in diagnostic
mode for self test. When in the diagnostic mode, written data
can be read through the same port by altering the state of the
DIR pin. In this case, the pointers are not reset (with direction
change) allowing the retrieval of written data. The read and
write pointers are reset upon exiting the diagnostic mode. The
leading edge of the first write cycle experienced after leaving
diagnostic mode is used to terminate the reset cycle. Flag
operations are normal in diagnostic mode, reflecting only the
relative states of the read and wri~inters. Thus they
change on the rising edge of the DIAG signal when the
pointers are reset upon leaving diagnostic mode.
The state of the DIR pin is latched when DIAG is brought
low, determining which port of the FIFO is used for diagnostics. If DIR is Low at the High-to-Low transition of DIAG, A port
is used for diagnostics. If High, B port is used. Figure 12
shows diagnostics for B port, but the timing also applies to A
port diagnostics if DIR is inverted.
Data can be loaded into the memory array before or after
setting the part into diagnostic mode. The DIAG pin must be
asserted before by the DIR pin's first state change. Once in
the diagnostic mode, data that has been written can be
retrieved through the same port by reading from that port.
Reading and writing can continue indefinately until the diagnostic mode has been exited.
Data can only flow from one port to another at any given
time. The direction of data flow is determined by the state of
the DIRpin. When the DIRpin is Low, data can be written only
into port A. Data can be read only out of port B. Data flows in
the opposite direction when the DIR pin is High. Data flow
function can be changed at any time. By altering the DIR state,
the two read and write pointers are reset and data flows in the
opposite direction. The falling edge of the first write cycle is
used to determine the end of the reset cycle. Flags outputs
reflect the pointer states and thus change on the change of the
DIR signal.
Bypass Mode
Asserting the BYP pin (active Low) places the device in the
bypass mode. The FIFO functions as a simple transciever in
this mode. Data can be directly written into or read out of a
device which is connected to the B port by a device connected
to the A port.
While in this mode, both ROB and WRB must be held High.
5.18
5
IDT7271/IDT72721IDT7273 PARALLEL ASYNCHRONOUS
SINGLE·BANK BIDIRECTIONAL FIFO 512 x 9·BIT, 1024 x 9·BIT & 2048 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~---------------------tRSC---------------_ _~
RS
----------""14- t RSR
WRA,WRB
RDA,RDB
BYP,DlAG
~~~~~~~~~--------------------------------~~------~----
_tRsR
_ _ _ _ _ _ _---1.....
DIR
2529 drw 05
Figure 2. Reset Cycle Timing
2529 drw 06
Figure 3. Write Timing (A or B )
RDAor RDB
DQAO· DOAe
or
OUTPUT DATA
DQso· DQ3e
2529 drw 07
Figure 4. Read Timing (A or B)
5.18
6
1017271/101727211017273 PARALLEL ASYNCHRONOUS
SINGLE-BANK BIDIRECTIONAL FIFO 512 X 9-BIT,1024 X 9-BIT & 2048 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RO"x"
Last Write
,
WR"y"
Ignored Writes
,-
/
..../
,
- -
First Read
-- /
,_ J
IFE'}=-
FF
Figure 5.
Full Flag Assertlon/Deassertlon Timing, In either direction or In Diagnostic mode
2529 drw 08
WR"y"
Last Read
,
RO"x"
Ignored Reads
,-
/
..../
" ,-
..../
/
Figure 6. Empty Flag Assertlon/Deassertlon Timing, In either direction or In Diagnostic mode
2529 drw 09
RO"x"
a-bytes to
full FIFO
WR"y"
_t~'AEV
Figure 7. Almost Full Flag Assertlon/Deassertlon Timing, In either direction or In Diagnostic mode
WR"y"
2529 drw 10
a-bytes to
,empty FIFO
'Fil) "x"
Figure 8. Almost Empty Flag AssertlonlDeassertlon Timing, In either direction or In Diagnostic mode
5.18
2529 drw 11
7
101727111017272/1017273 PARALLEL ASYNCHRONOUS
SINGLE·BANK BIDIRECTIONAL FIFO 512 X 9·BIT, 1024 X 9·BIT & 2048 X 9·BIT
DOAO· DQ\a
WRA
Byte 0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Byte 1
----------+-,
DOBO· DQ3a
DIR
Figure 9. Bypass mode: Data flow from A to B
2529 drw 12
DOBO· DOBa
DOAO - DOAa
2529 drw 13
Figure 10. Bypass mode: Data Flow from B to A
Direction
Direction
Change
Change
Reset Cycle
Reset Cycle
WRB
WRA
tDFWL ----I~
DIR
EF,AEF
/
,-
/
,-
/
/
FF, AFF
2529 drw 14
Figure 11. Data Flow Direction Change and Reset cycle Timing
5.18
8
10T7271/10T7272110T7273 PARALLEL ASYNCHRONOUS
SINGLE·BANK BIDIRECTIONAL FIFO 512 x 9·BIT, 1024 x 9·BIT & 2048 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RDB .....------~--------------~ r------------~
tDRSU - -.....--14-
DIR
---------------@--I .------~
I----~~~-----------~
DBO·DB8 .....
2529 drw 15
Figure 12. Diagnostic Mode ReadlWrlte TIming and DIagnostic Reset Cycle.
TABLE 1-- OPERATING MODES
RS
BYP
DIAG
OIR
RDA
Lr
1
1
x
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
WRA
Operating Mode
WFB
1
1
--u-
1
1
1
1
1
1
1
1
Lr
0
1
1
--u-
1
1
X
1
0
1
1
0
1
X
0
1
1
1
1
1
1
0
1
1
1
1
1
--u-
-U-
1
ROO
--u- --u1
1
1
-U-
Device reset
Diagnostic mode: data is being loaded through
'.
A port
Diagnostic mode: data is being retrieved
through A port
Diagnostic mode: data is being loaded through
B port
Diagnostic mode: data is being retrieved
through B port
Bypass mode: Data flows from A port to B port
'
Bypass mode: Data flows from 8 port to A port
FIFO
flows
FIFO
flows
Mode: Asynchronous read/write. Data
from j)ort A to port 8.
Mode: As~nchronous read/write. Data
from port to Dart A
2529 tbl 07
Unspecified states are not allowed
5.18
9
SPECIALITY MEMORY PRODUCTS
MULTI-PORT RAMS
Integrated Device Technology has emerged as the leading
mUlti-port RAM supplier by combining CEMOS/BiCEMOS
technology with innovative circuit design. With system performance advantages as a goal, we have brought system
design expertise together with circuit and technology expertise in defining dual-port and four-port RAM products. Our
dual-port memories are now industry standards. The synergistic relationship between advanced process technology,
system expertise and unique design capability add value
beyond that normally achieved. As an example, our dual-port
memories provide arbitration along with a completely tested
solution to the metastability problem .. Various arbitration
techniques are available to the designer to prevent contention
and system wait states. On-chip hardware arbitration,
"semaphore" token passing or software arbitration allow the
most efficient memory to be selected for each application. At
lOT, innovation counts only when it provides system advantages to the user.
Both commercial and military versions of all lOT memories
are available. Our military devices are manufactured and
processed strictly in conformance with all the administrative
processing and performance requirements of MIL-STD-883.
Because we anticipated increased military radiation resistance requirements, all devices are also offered with special
radiation resistant processing and guarantees. As the leading
supplier of military specialty RAMs, lOT provides performance
and quality levels second to none.
Our commercial dual-port and four-port memories, in fact,
share most processing steps with military devices.
6.0
TABLE OF CONTENTS
PAGE
SPECIALTY MEMORY PRODUCTS
IDT7130SNLA
IDT7140SNLA
IDT7030SNLA
IDT7040SNLA
IDT7132SNLA
IDT7142SNLA
IDT7032SNLA
IDT7042SNLA
IDT71321SNLA
IDT71421 SNLA
IDT7012
IDT70121 S/L
IDT70125S/L
IDT7133SNLA
IDT7143SNLA
IDT7134SNLA
IDT71342SNLA
IDT7014S
IDT7099S
IDT7005S/L
IDT7024S/L
IDT7006S/L
IDT7025S/L
IDT7050S/L
IDT7052S/L
8K (1 K x 8) Dual-Port RAM (Master) .........................................................................
8K (1 K x 8) Dual-Port RAM (Slave) ...........................................................................
8K (1 K x 8) Dual-Port RAM (Master) .........................................................................
8K (1 K x 8) Dual-Port RAM (Slave) ................................................................ ...........
16K (2K x 8) Dual-Port RAM (Master) .......................................................................
16K (2K x 8) Dual-Port RAM (Slave) .........................................................................
16K (2K x 8) Dual-Port RAM (Master) .. ... ... ..... ... ... ...... ..... ...... ... ...... ..... ... ... ... ..... .......
16K (2K x 8) Dual-Port RAM (Slave) .........................................................................
16K (2K x 8) Dual-Port RAM (Master with Interrupts) ...............................................
16K (2K x 8) Dual-Port RAM (Slave with Interrupts) .................................................
18K (2K x 9) Dual-Port RAM .. ... ... ..... ... ...... ... ..... ... ... ... ........... ... ........... ...... ......... ......
18K (2K x 9) Dual-Port RAM (Master with Busy and Interrupt) .................................
18K (2K x 9) Dual-Port RAM (Slave with Busy and Interrupt) ...................................
32K (2K x 16) Dual-Port RAM (Master) .....................................................................
32K (2K x 16) Dual-Port RAM (Slave) .......................................................................
32K (4K x 8) Dual-Port RAM .....................................................................................
32K (4K x 8) Dual-Port RAM (with Semaphore) ........................................................
36K (4K x 9-Bit) Dual-Port RAM ................................................................................
36K (4K x 9) Synchronous Dual-Port RAM ...............................................................
64K (8K x 8) Dual-Port RAM .....................................................................................
64K (4K x 16) Dual-Port RAM ...................................................................................
128K (16K x 8) Dual-Port RAM .................................................................................
128K (8K x 16) Dual-Port RAM .................................................................................
8K (1 K x 8) FourPort™ Static RAM ...........................................................................
16K (2K x 8) FourPort™ Static RAM .........................................................................
6.1
6.1
6.2
6.2
6.3
6.3
6.4
6.4
6.5
6.5
6.6
6.7
6.7
6.8
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
SUBSYSTEMS PRODUCTS (Please refer to pages indicated in Section 7 of this book.)
MULTI·PORT MODULES
IDT70M74
IDT7M1002
IDT7M1014
IDT7M1024
IDT7M1012
IDT7MB6036
IDT7MB6046
IDT7MB1006
IDT7MB6056
IDT7MB1008
IDT7M1005
IDT7M1004
IDT7M1001
IDT7MP1021
IDT7M1003
IDT7MP1023
4K x 16 FourPort™ Static RAM Multichip Module .....................................................
16K x 32 Dual-Port Static RAM Module ....................................................................
4K x 36 SiCMOS Dual-Port Static RAM Module .......................................................
4K x 36 Synchronous Dual-Port Static RAM Module ................................................
2K x 36 Dual-Port Static RAM Module ......................................................................
128K x 16 Dual-Port RAM (Shared Memory Module) ...............................................
64K x 16 Dual-Port RAM (Shared Memory Module) .................................................
64K x 16 Dual-Port Static RAM Module ....................................................................
32K x 16 Dual-Port RAM (Shared Memory Module) .................................................
32K x 16 Dual-Port Static RAM Module ....................................................................
16K x 9 Dual-Port Static RAM Module ......................................................................
8K x 9 Dual-Port Static RAM Module ........................................................................
128K x 8 Dual-Port Static RAM Module ....................................................................
128K x 8 Dual-Port Static RAM Module ....................................................................
64K x 8 Dual-Port Static RAM Module ......................................................................
64K x 8 Dual-Port Static RAM Module ......................................................................
M
7.2
7.3
7.4
7.5
7.6
7.7
7.7
7.8
7.8
7.8
7.9
7.9
7.10
7.11
7.10
7.11
2
t;)~
IDT7130SA/LA
IDT7140SAlLA
CMOS DUAL-PORT RAM
8K (1 K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High-speed access
-Military: 25/30/35/45/55/70/90/1 00/120ns (max.)
-Commercial: 20/25/30/35/45/55/70/90/100ns (max.)
• Low-power operation
-I DT7130/1 DT7140SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT7130/IDT7140LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 Only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
• INT flag for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible, single 5V ±1 0% power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT7130/IDT7140 are high speed 1 K x 8 dual-port
static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit dual-port RAM or as a "MASTER" dualport RAM together with the IDT7140 "SLAVE" dual-port in
16-bit-or-more word width systems. Using the IDT MASTER/SLA VE dual-port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CEMOSTM high-performance
technology, these devices typically operate on only 325mW
of power at maximum access times as fast as 20ns. Lowpower (LA) versions offer battery backup data retention capability, with each dual-port typically consuming 200llW from
a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, 48- or 52-pin LCCs, 52-pin PLCCs,
and 48-Lead flatpacks. Military grade product is manufactured in compliance with the latest revision of MIL-STD883, Class B.
•
FUNCTIONAL BLOCK DIAGRAM
RlWl
CEl
RiwR
CER
OEl
OER
A9l
All
1I00l
A9R
A7R
I/OOR
I/OlL
I/07R
BUSYR(1)
ASR
BUSYl(1)
ASl
AOl
AOR
NOTES:
1. IOT7130 (MASTER): BUSY is open drain output and requires pullup
resistor.
IOT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
2689 drwOl
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology. Inc.
6.1
APRIL 1992
DSC·l000/3
1DT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
Y.Q.c
CI;.R
QEl
...B!Y:1..l
BU~l
8.M'..B.
Illil
OEl
6lLSYR
It:ilR
AOl
OER
All
AOR
A1R
A2R
A3R
A4R
ASR
ASR
A2l
A3l
A4l
ASl
ASl
A7l
A8l
A7R
A9l
I/Ool
I/Oll
I/02l
I/03l
I/04l
I/OSl
I/OSl
I/07L
L48-1
&
F48-1
::12
::13
::14
::1S
::16
:: 17
37::
36::
3S::
34::
33::
32::
A8R
A9R
I/07R
GND---...=:....:....._ _.....=.:::....J
I/OsR
I/OSR
I/04R
I/03R
I/02R
I/01R
I/OoR
2689 drw 03
. 48-PIN LCC/FLATPACK
TOP VIEW
~I~ ~I~I~I~I~ ~I~I~I~I~ ~
INDEX
LJ L. L, LJ L. LJ
2689 drw 02
7 6 5 4 3
DIP
TOP VIEW
II
LJ L. LJ LJ L, L.
2 •• 52 51 50 49 48 47
1
46::
AIL
:: 6
A2L
45::
44::
:: 10
43::
:: 11
42::
:: 12
J52-1
41 ::
:: 13
&
:: 14
40::
L52-2
39::
:: 15
36::
:: 16
37::
:: 17
36::
:: 16
35::
:: 19
34
:: 20 21 22232425262726293031 3233 :::
A3L
A4L
ASL
ASL
A7L
ASL
A9L
IIOOL
IIOIL
II02L
II03L
:: 9
r, r 1 r, r, r
1
r 1 r 1 r, r 1 r 1 r 1 r
1
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
TSTG
lOUT
Storage
Temperature
DC Output
Current
-55 to +125
50
-65 to +135
-65 to +150
50
AOA
AtA
A2A
A3A
A4A
ASA
AeA
A7A
ASA
A9A
N/C
II07A
r,
2689 drw 04
52-PIN LCC/PLCC
TOP VIEW
VTERM(2) Terminal Voltage
with Respect to
GND
O'EA
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
°C
°C
Parameter
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
-
6.0(2)
V
-
0.8
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + O.SV.
mA
2689 tbl 01
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + O.SV.
2689 tbl 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
GND
-55°C to + 125°C
OV
5.0V
O°C to +70°C
OV
5.0V
Vee
± 10%
± 10%
2689 tbl 03
6.1
2
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vce = S.OV ±10%)
Symbol
IDT7130SA
IDT7140SA
Min.
Max.
Test Conditions
Parameter
IDT7130LA
IDT7140LA
Max.
Max.
Unit
IILlI
Input Leakage
Current(9)
Vee = 5.5V, VIN = OV to Vee
-
10
-
5
flA
Illol
Output Leakage
Current
CE' = VIH, VOUT = OV to Vee
-
10
-
5
flA
Val
Output Low Voltage
IOL=4.0mA
-
0.4
-
0.4
V
V
(1/00-1107)
Val
Open Drain Output
Low Voltage (SUSY', Tf\IT)
IOL = 16mA
-
0.5
-
0.5
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-'
V
2689 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1,8) (Vec = S.OV ± 10%)
Symbol
lee
IS81
IS82
IS83
IS84
Parameter
Test Conditions
Dynamic Operating
Current (80th Ports
Active)
eE = Vil
Outputs Open
f = fMAX(4)
Standby Current
(80th Ports - TTL
Level Inputs)
CEl and CER ;::: VIH
f = fMAX(4)
Standby Current
(One Port - TTL
Level Inputs)
CEl or CER ;::: VIH
Active Port Outputs
Open, f = fMAX(4)
Full Standby Current
(80th Ports - All
CMOS Level Inputs)
80th Ports eEL and
CER ;::: Vee -0.2V
VIN ;::: Vee -0.2V or
VIN ~ 0.2V,f = 0(5)
Full Standby Current
(One Port - All
CMOS Level Inputs)
One Port GEL or
eER ;::: Vee -0.2V
VIN;::: Vee -0.2V or
VIN ~ 0.2V
Active Port Outputs
Open, f = fMAX(4)
7130 x 20(2,6)
7140 x 20(2,6)
Version
Typ. Max.
SA Mil.
LA 125 2~?
com'l.~ 125 2t5::::::
SA Mil.
)~~~:;J{:::::;:
LA 30 :(~~:::::.
com'l.~ 30
SA - .....;..;.......
Mil.
LA - :.::::::;:~2::
;::::;::J.$,O
com'l.~ 80
80 \:/145
......:.:.:SA - .::;:;:::::::'
,.
Mil.
--:;:;:::::
LA
SA t.O .. :115
C om'
'I
LA ~n~t :':/5
.-
::::::.~
Mil.
SA
LA
:2\: ) :::(:::?::::.::
-
::/'1.0 175
Com 'I. SA
::::::+0::::
140
LA
7130 x 25 (6)
7140 x 25 (6)
Typ. Max.
125 300
125 240
125 260
125 210
30
80
30
60
30
65
30
45
80 195
80 160
80 175
80 140
1.0
30
10
0.2
1.0
15
0.2
5
7130 x 30(6)
7140 x 30(6)
Typ. Max.
125 295
125 235
125 255
125 205
30
80
30
60
30
65
30
45
80
190
80
155
80 170
80
135
1.0 30
10
0.2
1.0
15.
0.2
5
7130 x 35(7) 7130 x 45
7140 x 35(7) 7140 x 45
Typ. Max. Typ. Max.
125 290
75 230
125 230
75 185
75 190
75 195
75 155
75 145
30
80
25
65
60
55
30
25
25
65
25
65
25
25
45
45
80 185
40 135
40 110
80 150
40 120
40 130
95
40
85
40
30
1.0 30
1.0
10
0.2 10
0.2
1.0 15
1.0
15
0.2
4
0.2
4
70
185
70
180
70
175
40
70
150
70
145
70
140
35
95
70
170
70
165
40
115
40
105
70
135
70
130
35
90
35
80
NOTES:
1. "x" in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. Atf = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1lIRe, and using
"AC TEST CONDITIONS" of input levels of GND to 3V.
5. f = 0 means no address or eontrollines change. Applies only to inputs at CMOS level standby.
6. Not available in DIP packages, see 7030/40 data sheet.
7. DIP packages for O°C to +70°C only, see 7030/40 data sheet.
8. Vcc=5V, TA=+25°C for Typ.
9. At Vcc$2.0V input leakages are undefined.
6.1
Unit
mA
mA
rnA
rnA
125
rnA
2689tbl05
3
ID17130SAlLA AND ID17140SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1,6) (Continued) (Vcc = 5.0V -+10%)
Symbol
Icc
IS81
IS82
IS83
IS84
Parameter
Test Conditions
Dynamic Operating
Current (Both Ports
Active)
eE= VIL
Outputs Open
f = fMAX(4)
Standby Current
(Both Ports - TIL
Level Inputs)
eEL and CEA ~ VIH
f = fMAX(4)
Standby Current
(One Port - TTL
Level Inputs)
eEL or eEA ~ VIH
Active Port Outputs
Open, f = fMAX(4)
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CEl and
eEA ~ Vee -0.2V
VIN ~ Vee -0.2V or
VIN S 0.2V, f = 0(5)
Full Standby Current
(One Port -All
CMOS Level Inputs)
One Port CEL or
eEA ~ Vee -0.2V
VIN ~ Vee -0.2V or
VIN S 0.2V
Active Port Outputs
Open, f = fMAX(4)
Version
SA
Mil.
LA
com'l.~
Mil.
SA
LA
com'l.~
Mil.
SA
LA
com'l.~
Mil.
SA
LA
SA
C om 'I .LA
Mil.
7130 x 55
7140 X 55
Typ. Max.
65 230
65 185
65 180
65 140
25
65
25
55
25
65
25
45
40 135
40 110
40 115
40
85
1.0
30
0.2
10
1.0
15
0.2
4
7130
7140
Typ.
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
1.0
0.2
70
70
Max.
225
180
180
135
65
55
60
40
135
110
110
85
30
10
15
4
7130
7140
Typ.
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
1.0
0.2
X
X
90
90
Max.
200
160
180
130
65
45
55
35
125
100
110
75
30
10
15
4
7130
7140
Typ.
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
1.0
0.2
X
X
100 7130 X
100 7140 X
Max. Typ.
190
65
155
65
180
130
65
25
45
25
55
35
125
40
100
40
110
75
30
1.0
10
0.2
15
4
-
X
X
120(3
120(3)
Max. Unit
190
155
rnA
-
65
45
rnA
125
100
rnA
-
-
30
10
SA
40
120
40
115
40
110
40
110
40
LA
35
90
35
85
35
80
35
80
35
80
40
100
40
100
40
95
40
95
35
75
35
75
35
70
35
70
-
-
Com'l.SA
LA
rnA
110
rnA
2689 tbl 06
NOTES:
1. "x" in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. At f= fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1IIRc, and using
"AC TEST CONDITIONS" of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc=5V, TA=+25°C for Typ.
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
VOA
Vee for Data Retention
ICCDA
Data Retention Current
tCOA(3)
Chip Deselect to Data
IDT7130LAlI DT7140LA
Typ.(1)
Min.
Max.
Test Conditions
Parameter
I Mil.
Vec = 2.0V, CE ~ Vee -0.2V
VIN ~ Vee -0.2V or VIN S 0.2V
I Com'i.
2.0
-
-
Unit
0
V
100
4000
~
-
100
1500
(lA
0
-
-
ns
-
-
ns
Retention Time
tA(3)
tRc( 2)
Operation Recovery
Time
2689tbl07
NOTES:
1. Vce = 2V, TA = +25°C
2. tRc = Read Cycle Time
3. This parameter is guaranteed but not tested.
6.1
4
1DT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (lK x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
CE
VOR ~ 2.0V
4.5V
d
tCOR
,~_____V_O_R____-J/
VIH
tRb
VIH
2689 drw 05
AC TEST CONDITIONS
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 , 2, and 3
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2689 tbl 08
5V
12500.
DATA OUT
_--~:.
DATA OUT
7750.
_-----1
7750.
Figure 1. Output Load
5pF*
Figure 2. Output Load
(for tHZ, tLZ, twz, and tow)
5V
~270n
BUSY or INT
---i
100pF*
(30pF for 20ns, 25ns,
30ns versions &
35ns military)
1
Figure 3. BUSY and INT
Output Load
* Including scope and jig
2689 drw 06
6.1
5
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7130 x 20(2,6) 7130 x 25(6)
7140 X20(2,6) 7140 x 25(6)
Symbol
Parameter
Read Cycle
Read Cycle Time
tAC
tAA
Address Access Time
Chip Enable Access Time
tACE
Output Enable Access Time
tADE
tOH
Output Hold From Address Change
Output Low Z Time (1,4)
tLZ
Output High Z Time(1,4)
tHZ
tpu
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time( 4 )
tPD
Min.
20
Max.
Min.
"\.:.:.-
- ();;20
- ::>{.:20
- /:r::·: 10
O::::;::{:-
o :.:.:.:.:.:.:"V::::: 8
°t}::· -:;':':"
;:::-::;::.:.
50
Max.
7130 x 30(6) 7130 x 35(7)
7140 X 30(6) 7140 x 35(7)
Min. Max.
Min.
Max.
7130 x 45
7140 x 45
Min. Max.
25
-
30
-
35
-
45
-
-
-
30
30
15
-
35
35
25
-
-
25
25
12
-
45
45
30
0
0
-
0
0
-
0
5
-
-
10
0
-
-
50
-
-
-
0
5
-
12
-
15
-
20
0
-
0
-
0
-
-
50
-
50
-
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 09
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5) (Continued)
7130 x 70
7140 x 70
7130 x 55
7140 x 55
Symbol
Parameter
Read Cycle
Read Cycle Time
tRC
Address Access Time
tAA
tACE
Chip Enable Access Time
Output Enable Access Time
tADE
Output Hold From Address Change
tOH
Output Low Z Time (1,4)
tLZ
Output High Z Time(1,4)
tHZ
tpu
Chip Enable to Power Up Time( 4)
Chip Disable to Power Down Time( 4 )
tPD
Min.
Max.
Min.
Max.
7130 x 90
7140 x 90
7130 x 100
7140 x 100
Min. Max.
Min.
Max.
7130 x 120(3)
7140 x 120(3)
Min. Max.
55
-
70
-
90
-
100
-
120
-
-
55
55
35
-
70
70
40
-
90
90
40
-
100
100
40
-
120
120
60
0
5
-
-
-
0
5
-
10
5
-
10
5
-
10
5
-
-
40
-
40
-
30
-
35
-
40
·0
-
0
-
0
-
0
-
-
50
-
50
-
50
-
50
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2, and 3).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. "x· in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages, see 7030/40 data sheet.
7. DIP packages for O°C to +70°C only, see 7030/40 data sheet.
0
-
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbltO
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE (1,2,4)
DATA OUT
PREVIOUS DATA VALID
DATA VALID
2689 drw 07
NOTES:
1. RiW is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. Ol: = VIL.
6.1
6
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE (1, 3)
tACE
~K
/1{
tAOE
tHZ
/It'
"'I\..
fc--tLZ-
.,
..
DATAoUT
--tHZ-
«<:
DATA VALID
-'i<..,F-
tLZ
i4-tpu
1..-
CURRENT :::=====~~~~~~~~~~-~-~~~5-0-%-------------------------------------5-0---%~________
tPD
2689 drw 08
NOTES:
1. RfN is high for Read Cycles.
2. Device is continuously enabled, CE" = VIL.
3. Addresses valid prior to or coincident with CE" transition low.
4. ~=VIL.
6.1
7
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (7)
7130 x 20(2,0)
7140 x 20(2,8)
Symbol
Parameter
Write Cycle
Write Cycle Time(5)
twc
Chip Enable to End of Write
tEW
tAW
Address Valid to End of Write
Address Set-up Time
tAS
twp
Write Pulse Width (6)
Write Recovery Time
tWR
Data Valid to End of Write
tDW
Output High Z Time (1, 4)
tHZ
Data Hold Time
tDH
Write Enabled to Output in High Z (1, 4)
twz
Output Active From End of Write (1,4)
tow
Min.
7130 x 25(8)
7140 x 25(8)
Min. Max.
Max.
25
20
20
0
20
0
12
20 '\,.. 15 :(-::):,--
.::;)i>o ':-:::):-
15
15:::::::::':
03}:::
10':,::,:,:,:, -
.{:::.:.
-
8
0:::\:::': -
-:::(:::.
0·:":··:····
8
-
-
7130 X 30(8)
7140 x 30(8)
Min. Max.
-
30
25
25
0
25
0
15
10
-
-
-
0
-
-
10
0
-
-
-
-
-
-
-
15
-
20
-
-
12
-
15
0
7130 X 45
7140 x 45
Min. Max.
45
35
35
0
35
0
20
-
a
-
0
35
30
30
0
30
0
20
-
12
0
7130 X 35(9)
7140 x 35(9)
Min. Max.
-
a
0
20
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689tblll
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)
Symbol
Parameter
Write Cycle
Write Cycle Time(5)
twc
Chip Enable to End of Write
tEW
Address Valid to End of Write
tAW
Address Set-up Time
tAS
twp
Write Pulse Width (b)
Write Recovery Time
tWR
Data Valid to End of Write
tow
Output High Z Time (1, 4)
tHZ
toH
Data Hold Time
Write Enabled to Output in High Z (1.4)
twz
Output Active From End of Write (1, 4)
tow
7130 x 55
7140 x 55
Min. Max.
55
40
40
a
40
0
20
7130 x 70
7140 x 70
Min. Max.
-
70
50
50
-
a
50
0
30
-
-
7130 x 90
7140 x 90
Min. Max.
90
85
85
a
-
-
7130 x 100
7140 x 100
Min. Max.
100
90
-
-
a
-
-
-
65
0
40
40
-
-
a
-
40
-
55
0
40
-
40
-
30
a
35
-
-
0
-
a
-
-
30
-
35
-
40
-
40
-
a
-
0
-
0
-
Max.
120
100
100
a
55
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2, and 3).
2. O°C to +70°C temperature range only.
3. -55'C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, twc = tBAA + twP.
6. Specified for C5i: at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. "x" in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages, see 7030/40 data sheet.
9. DIP packages for O°C to +70°C only, see 7030/40 data sheet.
Min.
90
a
0
7130 X 120(3)
7140 x 120(3)
a
0
-
-
40
50
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl12
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Parameter(1)
2689tbl13
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
.
6.1
S
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (RIW CONTROLLED TIMING)(1,2,3,7)
~---------------------------------------------------------twc--------------------------------------------------~
ADDRESS
-------I~t---------------------------twP (7) ---------------------------I~f-tWR
DATA OUT
14------------tDW ------------I~I--------tDH
------------t~
DATA IN
2689 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
twc
=>K
~tAS
)(
..
tAW
}
/V
tWR
tEW
t
DATA IN
I
tDW
tDH
J
/1
2689 drw 10
NOTES:
1. Rtifl must be high during all address transitions.
2. A write occurs during the overlap (lEW or twp) of a low ~ and a low RJVii.
3. twR is measured from the earlier of ~ or Rtifl going high to the end of the write cycle.
4. During this period, the 110 pins are in the output state and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the Rtifllow transition, the outputs remain in the high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
7. If at: is low during a RJW controlled write cycle, the write pulse width must be larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tow. If ot: is high during an RJVii controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.1
9
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL·PORT RAM SK (1K x S·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE{B)
7130 X 20(1,10) 7130 x 25 (10)
7140 X20(1,10) 7140 X 25 (10)
Symbol
Parameter
BUSY TIMING (FOR MASTER IDT7130 ONLY)
tBAA
tBDA
BUSY Access Time to Address
BUSY Disable Time to Address
tBAC
BUSY Access Time to Chip Enable
BUSY Disable Time to Chip Enable
Write Pulse to Data Delay(3)
Write Data Valid to Read Data Delay(3)
tBDC
tWDO
tDDO
Min.
Max.
Min.
20
- ",:,:::-:.;W
- :{::;:-:::20
- ::::::-:,},:20
- :·:·:·:>/50
- :::::::::::::::35
Arbitration Priority Set-up Time (4)
5 ...::::::::;.BUSY Disable to Valid Data(5)
tBDO
- ····t~ote
BUSY INPUT TIMING (FOR SLAVE IDT7140 ONLY) :: :~..::
Write to BUSY Input(6)
tWB
0:(":: ;.; Write Hold After BUSY(7)
tWH
14::':':·" Write Pulse to Data Delay(9)
50
tWDO
-
-
5
tAPS
tDDO
Write Data Valid to Read Data Delay(9)
-
-
5
35
Max.
Min.
-
25
20
20
20
50
35
-
-
Note
7130 X 30 (10) 7130 X 35 (11)
7140 X 30(10) 7140 X 35(11)
5
5
Max.
-
30
25
25
25
50
35
-
-
-
-
Note
Min.
5
5
-
0
15
-
0
20
-
0
20
-
50
35
-
50
35
-
Max.
-
35
30
30
25
60
35
'-
-
Note
7130 X 45
7140 x 45
Min. Max.
5
5
60
35
-
35
35
30
25
70
45
Note
0
20
-
-
70
45
Unit
ns
ns
ns
ns
5
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 14
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE{B)
Symbol
Parameter
BUSY TIMING (FOR MASTER IDT7130 ONLY)
BUSY Access Time to Address
tBAA
tBDA
tBAC
BUSY Disable Time to Address
BUSY Access Time to Chip Enable
tBDC
tWDO
tDDO
BUSY Disable Time to Chip Enable
Write Pulse to Data Delay(3)
Write Data Valid to Read Data Delay(3)
tAPS
Arbitration Priority Set·up Time(4)
7130 x 55
7140 x 55
Min. Max.
-
45
40
35
30
80
55
5
-
-
BUSY Disable to Valid Datal!»
tBDO
BUSY INPUT TIMING (FOR SLAVE IDT7140 ONLY)
Write to BUSY Inputlb)
0
tWB
tWH
tWDO
Write Hold After BUSYlf)
Write Pulse to Data Delay(9)
toDO
Write Data Valid to Read Data Delay (9)
20
-
Note
7130 x 70
7140 x 70
Min.
Max.
-
7130 x 100
7140 x 100
Min. Max.
-
45
40
35
30
90
70
-
45
45
45
45
100
90
-
5
-
5
-
5
-
-
5
7130 x 90
7140 x 90
Min. Max.
-
Note
5
-
-
0
20
-
0
20
80
55
-
90
70
-
Note
100
90
5
0
20
-
5
-
Min.
-
50
50
50
50
120
100
Note
7130 x 120(2)
7140 x 120(2)
5
-
-
0
20
120
100
-
Max.
Unit
60
60
60
60
140
120
ns
ns
ns
ns
ns
ns
Note
140
120
5
ns
ns
ns
ns
ns
ns
NOTES:
2689tbl IS
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3.
Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
(For Master IDT7130 only)".
4. To ensure that the earlier of the two ports wins.
5. tBDD is a calculated parameter and is the greater of 0, twDD-twP (actual) or tDDD-tDW (actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
S. "x' in part numbers indicates power rating (SA or LA).
9.
Port-to-port delay through RAM cells from writing port to reading port, refer.to "Timing Waveform of Read With Port-to-Port Delay (For Slave IDT7140
Only)".
10. Not available in DIP packages, see 7030/40 data sheet.
11. DIP packages for oDe to +70°C only, see 7030/40 data sheet.
eusv
6.1
10
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF REAO WITH BUSY (1,2,3) (FOR MASTER IOT7130 ONLy)
twc
ADDRR
)~
'\V
/,
MATCH
twp
~K.
RiWR
/v
)~t
tow
)(
DATAINR
VALID
i+-tAPS(1)
MATCH
ADDRL
)
tBDO---'"
tBOA-'-
\ LA
BUSYL
twoo
DATAauTL
) ( VALID
toOO(4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE" at La for the reading port.
2689 drw 11
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY (1,2,3)(FOR SLAVE IOT7140 ONLy)
ADDRR
RlWR
l
twc
>K
MATCH
'V
/~
twp
~,
/
V
)~t
tDW
)K
DATAINR
VALID
MATCH
ADDRL
tWDD
)K
DATAauTL
VALID
tODD
NOTES:
1. Assume BUS? input at HI for the writing port, and 01: at LO for the reading port.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
2689 drw 12
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (FOR SLAVE IOT7140 ONLY)
e:-f_tWBi_twPytWH1
2689 drw 13
6.1
11
1DT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO_1, CE ARBITRATION (FOR MASTER IOT7130
ONLY)
eEL VALID FIRST:
ADDR ~
ADDRESSES MATCH
~
LANDR~~--------------------------------------______________~
GEL
CER
r
"k
==~tAPShtBAc~_---i-L_· ~~-=-=
__
tBDC--j-·,
J
l\
BUSYR
eER VALID FIRST:
2689 drw 14
ADDR ~
ADDRESSES MATCH
~
LANDR~~--------------------------------------------------~~
CER_~tAPS~_---4r
~tBAC~
GEL
_ _ __
-k.
.
l\
BUSYL
tBDC--j,.......------_
J
2689 drw 15
TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, AOORESSVALIO ARBITRATION(1)
(FOR MASTER IOT7130 ONLY)
LEFT ADDRESS VALID FIRST:
i4-----tRC OR
ADDRL
twc------~~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDRR
I----tBDA----}~.
_______________t_BAA_9
i " '.
I I.
l
BUSYR
~--------------------~
2689 drw 16
RIGHT ADDRESS VALID FIRST:
~----tRC
ADDRR
OR
twc------~~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR L
tBAA
BUSYL
9~________:1..~_-_-_-_-_t_B_DA_-_-_-_-~}~
2689 drw 17
NOTE:
1. UL = UR
= VIL
6.1
12
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (3)
7130 x 20(1,4)
7140 x 20(1,4)
Symbol
Interrupt
tAS
tWR
tiNS
tlNR
Parameter
Tim ing
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
Min.
Max.
7130 x 25(4)
7140 x 25(4)
7130 x 30(4)
7140 x 30(4)
7130 X 35(5)
7140 x 35(5)
Min.
Min.
Max.
Min.
Max.
Max.
7130 x 45
7140 x 45
Min. Max.
Unit
>:::::
a
a
-
-
~.):~
:::::::i-
{::=i 20
).:;::....
a
a
-
a
a
-
a
a
-
a
a
-
-
25
25
-
30
30
-
35
35
-
40
40
-
20
ns
ns
ns
ns
2689tbl16
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
7130 x 55
7140 x 55
Symbol
Parameter
Interrupt Timing
tAS
Address Set-up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
7130 x 70
7140 x 70
Max.
7130 x 90
7140 x 90
7130 x 100
7140 x 100
Min.
Max.
Min.
Max.
7130 x 120(2)
7140 x 120(2)
Min.
Max.
Min.
Min. Max.
a
a
-
a
a
-
a
a
-
a
a
-
a
a
-
-
45
45
-
50
50
-
55
55
-
60
60
-
70
70
Unit
ns
ns
ns
ns
2689 tbl17
NOTES:
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. "x" in part numbers indicates power rating (SA or LA).
4. Not available in DIP packages, see 7030/40 data sheet.
5. DIP packages for O°C to +70°C only, see 7030/40 data sheet.
TIMING WAVEFORM OF INTERRUPT MODE (1,2)
LEFT SIDE SETS INTR:
~----------twc----------~
ADDRL
tI
WRITE 3FF
RlWL
IiNS=\k
INTR
2689 drw 18
RIGHT~SIDE
CLEAR TNfR:
1+--------tRc------------F~
f
ADDRR
READ3FF
.
'-~~~~-¥~K_~~'_~~~~_ _~~------------------------------
RlWR
OER
7ZZZZZZZZZ
\SSSSSSSSSSSSSSS'L
tWA
__
INTR
/
l===tINRJe.....--_ _ _ _ _ _ __
----------------------------------------------------2689 drw 19
NOTES:
1. CEl = CER = Vil
2. INTl and INTR are reset (high) during power up.
6.1
13
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATuRE RANGES
TIMING WAVEFORM OF INTERRUPT MQDE(1, 2)
RIGHT SIDE SETS INTL:
~----------twc----------~
ADDRR
WRITE3FE
N5
INTL
"
1""--____________________________
2689 drw 20
LEFT SIDE CLEAR INTL:
~-----------tRc-----------~~
ADDRL
READ 3FE
RiWL
GEL
__
INTL
/
\SSSSSSSSS~
~tINRJt.-----------------------------------------2689 drw 21
NOTES:
1. CEL
=CER = VIL
2. INTR and fl\JTL are reset (high) during power up.
16-81T MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RIGHT
RN.J
IDT7130
MASTER
BUSY
'AAA
,,'1'
we
BUSY
+5V
RN.J
RN.J
+5V
IDT7140
SLAVE (1)
BUSY
AAA
'1''1'",
RN.J
BUSY
2689 drw22
NOTE:
1. No arbitration in IDT7140 (SLAVE). SUSV-IN inhibits write in IDT7140 (SLAVE).
6.1
14
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IOT7130/IOT7140 provides two ports with separate
control, address, and I/O pins that permit independent access
for reads or writes to any locations in memory. The IOT7130/
IOT7140 has an automatic power down feature controlled
by CEo The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE high). When a port is enabled, access to
the entire memory array is permitted. Each port has its
own Output Enable control (DE). In the read mode, the
port's DE turns on the output drivers when set LOW. Noncontention READ/WRITE conditions are illustrated in Table
1.
The interrupt flag (INT) permits communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INTL)
is set when the right port writes to memory location 3FE
(HEX). The left port clears the interrupt by reading address
location 3FE. Likewise, the right port interrupt flag (INTR) is
set when the left port writes to memory location 3FF (HEX)
and to clear the interrupt flag (INTR), the right port must
read the memory location 3FF. The message (a-bits) at
3FE or 3FF is user defined. If the interrupt function is not
used, address locations 3FE or 3FF are not used as
mailboxes, but as part of the random access memory. Refer
to' Table II for the interrupt operation.
'
port that has BUSY set LOW. The delayed port will have
access when BUSY goes inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the
on-chip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before cr, on-chip control logic arbitrates between
CEl and CER for access; or (2) if the crs are low before
an address match, on-chip control logic arbitrates between
the left and right addresses for access (refer to Table II). In
either mode of arbitration, the delayed port's BUSY flag is
set and will reset when the port granted access completes
its operation.
.,
DATA BUS WIDTH EXPANSION
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in
a dual-port RAM system implies that several chips will be
active at the same time. If each chip includes a hardware
arbitrator, and the addresses for each chip arrive at the
same time, it is possible that one will activate its BUSYL
while another activates its BUSYR signal. Both sides are
now busy and the CPUs will wait indefinitely for their port to
become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTER/SLAVE approach where only one arbitrator, in
the MASTER; is used. The SLAVE has BUSY inputs which
allow an interface to the MASTER with no external
ARBITRATION LOGIC
components and with a speed advantage over other
systems.
FUNCTIONAL DESCRIPTION:
When expanding dual-port RAMs in width, the writing
The arbitration logic will resolve an address match or a
chip enable match down to 5ns minimum and determine the SLAVE RAMs must be delayed, until after the BUSY
which port has access. In all cases, an active BUSY flag input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a contention situation. Conversely, the
will be set for the delayed port.
The BUSY flags are provided for the situation when both write pulse must extend a hold time past BUSY to ensure
ports simultaneously access the same memory location .. that a write cycle takes place after the contention is resolved.
When this situation occurs, on-chip arbitration logic will This timing is inherent in all dual-port memory systems where
determine which port has access and sets the delayed port's more than one chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
BUSY flag. BUSY is set at speeds that permit the processor
to hold the operation and its, respective address data. It is maximum arbitration time of the MASTER. If, then, a
importantto 'note that the write operation is invalidfor the contention occurs, the write to the SLAVE will be inhibited
due to BUSY from the MASTER.
of
6.1
15
1D17130SAlLA AND 1D17140SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READIWRITE CONTROL(4)
Left Or Right Port (1)
RIW eE
X
H
OE
X
X
H
X
L
H
H
L
L
L
X
L
H
Function
Port Disabled and in Power
Down Mode 1882 or 1884
Z
CER = GEL = H, Power Down
Mode, 1881 or 1883
DATAIN Data on Port Written into Memory(2)
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
00-7
Z
2689 tbl 18
NOTES:
1. AOL-A9L#AoR-A9R
2. If BUSY = L, data is not written
3. If BUSY = L, data may not be valid, see twoo and to~D timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
TABLE II-INTERRUPT FLAG(1, 4)
RIWL
L
X
X
X
eEL
L
X
X
L
Left Port
OEL
AOL-A9L
X
3FF
X
X
X
X
3FE
L
TNiL
X
X
U3)
H(2)
RIWR
X
X
L
X
CER
X
L
L
X
Right Port
'()E'R
AOL-A9R
X
X
3FF
L
3FE
X
X
X
Tm'R
U2)
H(3)
X
X
Function
Set Right TfiITR Flag
Reset Right TfiITR Flag
Set Left mTL Flag
Reset Left TfiITL Flag
2689 tbl19
NOTES:
1. Assumes BUSY'L = IiDSYR = H.
2. If BOSY'L = L, then NC.
3. If BOSYR = L, then NC.
4. H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE
TABLE 111- ARBITRATION (2)
Flags(1)
Right Port
Left Port
AOR-A9R
eEL
AOL-A9L
eER
H
H
X
X
X
H
L
Any
L
Any
H
X
L
*- AOL-A9L
L
*-AOR-A9R
Address Arbitration With CE Low Before Address Match
LV5R
L
LV5R
L
RV5L
RV5L
L
L
Same
Same
L
L
Same
L
Same
L
CE Arbitration With Address Match Before CE
LL5R
LL5R
= AOR-A9R
RL5L
RL5L
= AOR-A9R
LW5R
= AOR-A9R
LW5R
LW5R
LW5R
= AOR-A9R
= AOL-A9L
= AOL-A9L
= AOL-A9L
= AOL-A9L
Function
No Contention
No Contention
No Contention
No Contention
ImSVL
H
H
H
H
ImSVR
H
H
H
H
H
L
H
L
L
H
L
H
L-PortWins
R-PortWins
Arbitration Resolved
Arbitration Resolved
H
L
H
L
L
H
L
H
L-PortWins
R-Port Wins
Arbitration Resolved
Arbitration Resolved
2689tbl20
NOTES:
1. INi Flags Don't Care.
2. X = DON'T CARE, L = LOW, H = HIGH
LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW ~ 5ns before Right
RL5L = Right CE = LOW ~ 5ns before Left
LW5R = Left and Right
= LOW within 5ns of each other.
cr
6.1
cr.
cr.
16
t;J®
CMOS DUAL-PORT RAM
8K (1 K x 8-BIT)
PRELIMINARY
I DT7030SAlLA
I DT7040SAlLA
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 25/35/45ns (max.)
-Commercial: 20/25/35ns (max.)
• Low-power operation
-I DT7030/40SA
Active: 400mW (typ.)
Standby: 7mW (typ.)
-IDT7030/40LA
Active: 400mW (typ.)
Standby: 2mW (typ.)
• MASTER IDT7030 easily expands data bus width to 16or-mare-bits using SLAVE IDT7040
• On-chip port arbitration logic (IDT7030 only)
• BUSY output flag on IDT7030; BUSY input on IDT7040
• INT flag for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TIL-compatible, single 5V ±1 0% power supply
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT7030/IDT7040 are high speed 1 K x 8 dual-port
static RAMs. The IDT7030 is designed to be used as a
stand-alone 8-bit dual-port RAM or as a "MASTER" dualport RAM together with the IDT7040 "SLAVE" dual-port in
16-bit-or-more word width systems. Using the IDT MASTER!
SLAVE dual-port RAM approach in 16-or-more-bit memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CEMOSTM high-performance
technology, these devices typically operate on only 400mW
of power at maximum access times as fast as 20ns. Lowpower (LA) versions offer battery backup data retention
capability, with each dual-port typically consuming 200/lW
from a 2V battery.
The IDT7030/IDT7040 devices are packaged in 48-pin
sidebraze or plastic DIPs. Military grade product is
manufactured in compliance with the latest revision of MILSTD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
RlWR
CER
A8l -++---,
A7l
r---+i~
A9R
A7R
I/OOl
I/OOR
I/07l
I/07R
BUSYl(1) ~r-;====::::;-~
'----;:::====~~ BUSYR(1)
ASl
...--_---X_ _-,.
ASR
AOl
AOR
-~--------._
ARBITRATION
AND INTERRUPT LOGIC
-
RlW l
:
--.0.-....--....,......-....---.-'-
NOTES:
1. IOT7030 (MASTER): BUSY is open drain output and requires pullup resistor.
IOT7040 (SLAVE): BlJSY is input.
2. Open drain output: requires pullup resistor.
A9R
AOR
CER
RlWR
2690 drwot
CEMOS is a trademark 01 Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc
6.2
APRIL 1992
DSC·l07812
1
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CEl = 1
RiWl = 2
~l = 3
INTl
4
OEl 5
AOl F= 6
All
7
A2l
8
---
~!~ = ~O
ASl
GND
ASl
48
47
46
45
44
43
42
41
CER
F= R/WR
l3lJSYR
F= INTR
OER
F= AOR
F= A1R
A2R
~g F= ~!=
= 11
12
= 13
A7L 14
ASl
15
A9l
16
IIOOl = 17
IIOll 18
II02l ~ 19
II03l 20
I/04l = 21
I/OSl 22
IIOSl 23
I/07L 24
P48-1 38
&
37
C48-2 36
35
34
33
32
31
30
29
28
27
26
25
ASR
Vee
ASR
F= A7R
ASR
A9R
F= II07R
IIOSR
F= I/OSR
1/04R
F= 1I03R
F= 1I02R
1/01 R
I/OOR
2690 drw 02
DIP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1}
Symbol
Rating
VTERM(2} Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
°C
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
Vil
Input Low Voltaqe
-0.5(1)
-
6.0(2)
V
0.8
V
2690 Ibl 02
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
2690lbl01
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vee + O.SV.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
2690 Ibl 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
Conditions
=OV
VIN = OV
VIN
Max. Unit
11
pF
Output Capacitance
11
pF
COUT
NOTE:
2690 Ibl 04
1. This parameter is determined by device characterization but is not
production tested.
6.2
2
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM BK (1K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = S.OV ±10%)
Symbol
Parameter
IDT7030SA
IDT7040SA
Min.
Max.
Test Conditions
IDT7030LA
IDT7040LA
Max.
Max.
Unit
IILlI
Input Leakage
Current(7)
Vee = 5.5V, VIN = OV to Vee
-
10
-
5
!lA
IILol
Output Leakage
Current
CE = VIH, VOUT = OV to Vee
-
10
-
5
!lA
VOL
Output Low Voltage
(VOO-V07)
IOL= 4.0mA
-
0.4
-
0.4
V
VOL
Open Drain Output
IOL = 16mA
-
0.5
-
0.5
V
IOH = -4mA
2.4
-
2.4
-
LowVolt~ejBDS?
VOH
Output High Voltage
Wi)
V
2690 tbl 05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc = S.OV ± 10%)
Symbol
lee
1881
1882
1883
1584
Parameter
Test Condition
Version
Mil.
7030 x 20(2)
7030 x 25
7030 x 35
7030 x 45(3)
7040 x 20(2)
7040 x 25
7040 x 35
7040 x 45(3)
Typ.
Max. Typ. Max. Typ.
Max.
Typ.
125
125
300
240
125
125
290
230
125
125
285
225
rnA
260
210
125
125
250
200
.:?::::Jh::::::
125
125
30
80
60
65
45
30
30
30
30
30
30
30
30
rnA
30
80
60
65
45
80
<}t;C"
80
80
80
80
195
160
175
140
80
80
80
80
185
150
165
130
80
80
180
145
rnA
1.0
0.2
1.0
0.2
30
10
15
30
10
15
1.0
0.2
30
10
rnA
5
1.0
0.2
1.0
0.2
70
70
70
70
185
150
170
135
70
70
70
70
175
140
160
125
70
70
170
135
rnA
SA
LA
Dynamic Operating
CUrrent (Both Ports
Active)
"CE= VIL
Outputs Open
f = fMAX(4)
Standby Current
(Both Ports - TTL
Level Inputs)
"GEL and"GER ~ VIH
f = fMAX(4)
Standby Current
(One Port - TTL
Level Inputs)
"GEL or ct:R ~ VIH
Active Port Outputs
Open, f = fMAX(4)
SA
LA
Com'l. SA
LA
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports GEL and
CER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN :s; 0.2V, f = 0(5)
Mil.
SA
LA
Com'l. SA
LA
Full Standby Current
(One Port-All
CMOS Level Inputs)
One Port "GEL or
"GER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN:S; 0.2V Active Port
Outputs Open, f=fMAX(4)
Mil.
Com'l. SA
LA
SA
LA
Com'l. SA
LA
':';;;"'"
,:2t5!l'
./215=:;:;'
125
125
Mil.
Mil.
:::;::::;:;:;;;;;;;
·~ttt::+i+-
lAlL. . }
15
:p~i;;;;;:::~;:· 5
SA ..,.,,::;,. ':':::
LA ,,;..;i:;:.
Com'l. SA :':::"1t):::;:,
LA
70
175
140
Max. Unit
60
5
2690 tbl 06
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. Atf = fMAX, address and control lines (except Output Enable) are cycling atthe maximum frequency read cycle of 1/tRc, and using "AC TEST CONDITIONS"
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc=5V, TA=+25°C for Typ.
7. At Vcc$2.0V input leakages are undefined.
6.2
3
IDT7030SAlLA AND 1DT7040SAlLA
CMOS DUAL-PORT RAM aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (LA Version Only)
Svmbol
Parameter
Test Conditions
VDR
Vee for Data Retention
Vee = 2.0V, CE~ Vee - 0.2V
leeDR
Data Retention Current
VIN ~ Vee - 0.2V or VIN $ 0.2V
IDT7030LAlIDDT7040LA
Tvp.(1)
Min.
Max.
Unit
2.0
-
0
V
-
100
4000
~
100
1S00
I Mil.
l Com 'I.
teDR(3)
Chip Deselect to Data
Retention Time
tR(3)
Operation Recovery
Time
0
-
-
ns
tRcl 2)
-
-
ns
NOTES:
1. Vee = 2V, TA = +25°C
2. tRe = Read Cycle Time
3. This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
AC TEST CONDITIONS
Vee
CE
VDR~
4.SV
d
2.0V
4.SV
Input Rise/Fall Times
Sns
Input Timing Reference Levels
1.SV
Output Reference Levels
teDR
,~______
VD_R____~/
GNDto 3.0V
Input Pulse Levels
DATA RETENTION MODE
1.SV
Output Load
tRb
See Figures 1, 2 & 3
2690 tbl 08
~H
~H
2690 drw03
SV
SV
12S0f!
12S0f!
DATA OUT __--~
DATA OUT - - . . - -....
77Sf!
77Sf!
30pF*
SpF*
Figure 2. Output Load
(for tHZ, tLZ, twz, and tow)
Figure 1. Output Load
SV
~270n
BUSY or INT
---i
1
30PF
'
2690 drw 04
Figure 3. BUSY and INT
Output Load
* Including scope and jig
6.2
4
IDTI030SAlLA AND IDTI040SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
Parameter
Symbol
7030 x 20(2)
7040 x 20(2)
Min. Max.
7030 x 25
7040 x 25
Min. Max.
7030 x 35
7040 x 35
Min. Max.
7030 x 45(3)
7040 x 45(3)
Min. Max.
Unit
Read Cycle
tRC
Read Cycle Time
35
-
45
-
tAA
Address Access Time
25
-
35
45
ns
Chip Enable Access Time
25
-
35
45
ns
25
-
0
-
0
0
-
-
tACE
tAOE
25
20
12
Output Enable Access Time
tOl-+
Output Hold From Address Change
tLZ
Output Low Z Time(1,4)
tHZ
Output High Z Time(1,4)
tpu
Chip Enable to Power Up Time(4)
tPD
Chip Disable to Power Down Time(4)
o·t}\ -
o
o
10
o
~::::.:.:.:
50
50
ns
30
ns
0
-
ns
15
-
20
ns
0
-
0
-
ns
-
50
-
50
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to +70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. "x· in part numbers indicates power rating (SA or LA).
ns
ns
2690 Ibl 09
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
-----:J(~~----------------------tRC----------------------~~
ADDRESS
DATAoUT
-----'l:~:~~=~~=~~-t-O~H----~t-AA---.==I=~~~~~~-.~I------------------------f~-tO-H----------VALID DATA
PREVIOUS DATA VALID
--------------------~~~~'-~
2690 drw05
NOTES:
1. RtW is high for Read Cycles.
2. Device is continuously enabled,
= VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = VIL.
cr
6.2
5
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM aK (1K X a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE{1,3)
tACE
~'\.
//
tAOE
tHZ
~K.
//
~tLZ--"
DATAoUT
-+-tHZ
.. < < <:
,f-"
~
-"
..
DATA VALID
tLZ
',.
+-tpu . .
tpo
~URRENT :::===========~~~-_-~-~~~5-0-%-O-----------------------------------~~
______
2690 drw 06
NOTES:
1. RIW is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = VIL.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)
Parameter
Symbol
7030 x 20(2}
7040 x 20(2}
Min. Max.
7030 x 25
7040 x 25
Min. Max.
7030 x 35
7040 x 35
Min. Max.
7030 x 45(3}
7040 x 45(3}
Min. Max.
Unit
Write Cycle
twc
Write Cycle Time(5)
25
35
45
tEW
Chip Enable to End of Write
20
30
35
ns
tAW
Address Valid to End of Write
20
30
35
ns
ns
tAS
Address Set-up Time
o
o
o
ns
twp
Write Pulse Width(6)
20
30
35
ns
tWR
Write Recovery Time
0.:.5\:-
o
o
o
ns
tow
Data Valid to End of Write
10:····:·:::::-
12
20
20
ns
tHZ
Output High Z Time(1,4)
tOH
Data Hold Time
twz
Write Enabled to Output in High Z(l,4)
tow
Output Active From End of Write(1,4)
10
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to +70°C temperature range only.
3. -55'C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTERISLAVE combination, !we = tBAA + twP.
6. Specified for OE at high (refer to "Timing Waveform of Write Cycle", Note 7).
7. "x" in part numbers indicates power rating (SA or LA).
6.2
o
15
10
o
20
15
o
o
o
ns
20
o
ns
ns
ns
2690tbll0
6
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM SK (1 K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (RIW CONTROLLED TIMING)(1,2,3,7)
twc
ADDRESS
DE
CE
twp(7)
RlW
DATA OUT
tDH
tDW
DATA IN
2690 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,2,3,5)
twc
ADDRESS
~K
)~
II
tAW
\4--tAS
1
..IV
tWR
tEW
j.-
RlW
I
I
DATA IN
I'
tDW
tDH
J
/1
2690 drw08
NOTES:
1.
2.
3.
4.
5.
6.
7.
RiViI must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE' and a low RiViI.
twR is measured from the earlier of CE' or RiViI going high to the end of the write cycle.
DUfing this period, the 110 pins are in the output state and input signals must not be applied.
If the CE' low transition occurs simultaneously with or after the RiViIlow transition, the outputs remain in the high impedance state.
Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig).
If l51: is low during a R/W controlled write cycle, the write pulse width must be larger of twp or (twz + tow) to allow the 110 drivers to turn off and data to
be placed on the bus for the required tow. If l51: is high during a RJW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.2
7
IDT7030SAlLA AND ID17040SAlLA
CMOS DUAL-PORT RAM aK (1K X a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
7030 x 20(1)
7030 x 25
7040 X 20(1)
7040 x 25
Parameter
Symbol
Min.
Max.
Min.
Max.
7030 x 35
7030 x 45(2)
7040 x 35
7040 x 45(2)
Min.
Max.
Min. Max.
Unit
Busy Timing (For Master 1017030 Only)
35
25
20
35
35
ns
30
20
30
30
ns
BUSY Disable Time to Chip Enable
20
25
25
ns
Write Pulse to Data Delay(3)
50
60
70
ns
tODD
Write Data Valid to Read Data Delay(3)
35
55
ns
tAPS
Arbitration Priority Set-up Time(4)
tBDO
BUSY Disable to Valid Data(5)
tBAA
BUSY Access Time to Address
tBDA
tBAC
BUSY Disable Time to Address
BUSY Access Time to Chip Enable
tBDC
tWDD
20
-
:::. 20
45
5
5
5
Note 5
Note 5
-
ns
ns
Note 5
ns
Busy Input Timing (For Slave 1017040 Only)
o
o
BUSY Input(6)
o
tWB
Write to
tWH
Write Hold After BOSy(7)
tWDD
Write Pulse to Data Delay(9)
50
50
60
70
ns
tODD
Write Data Valid to Read Data Delay(9)
35
35
45
55
ns
20
15
ns
20
ns
NOTES:
2690 tbl t 1
1. DOC to +70°C temperature range only.
2. -55°C to +12SoC temperature range only.
3. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUS? (For Master IOT7030 only)".
4. To ensure that the earlier of the two ports wins.
5. tBDD is a calculated parameter and is the greater of 0, twDD-twP (actual) or tODD-tow (actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
8. "x" in part numbers indicates power rating (SA or LA).
9. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wawform of Read With Port-to-Port Delay (for Slave IOT7040
Only)".
6.2
a
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL·PORT RAM SK (1K X S·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF REAO WITH BUSy(1,2,3) (FOR MASTER IOT7030 ONLY)
twc
ADDRR
~V
/~
)K
MATCH
twp
'\K
RiW'R
/
tow
)(
DATAINR
VALID
--tAPS(1)
ADDRL
V
>k
0H
MATCH
)
c..tBOA
\ LA
BUSYL
tBOO-
twoo
DATAOUTL
) ( VALID
toOO(4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OC at LO for the reading port.
2690 drw09
TIMING WAVEFORM OF REAO WITH PORT-TO-PORT OELAy(1,2,3) (FOR SLAVE IOT7040 ONLy)
L
ADDRR
twc
>k
)(
MATCH
twp
~,
RlWR
//
)K0H
tow
)(
DATAINR
ADDRL
VALID
MATCH
twoo
)(
DATAOUTL
VALID
tODD
NOTES:
1. Assume 80SY input at HI for the writing port, and DE" at LO for the reading port.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
2690 drw 10
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (FOR SLAVE IOT7040 ONLY)
twp
pm
-{'WB}
J'WH{
BUSY
2690 drw 11
6.2
9
IDT7030SAllA AND ID17040SAllA
CMOS DUAl·PORT RAM 8K (1K x 8·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
(FOR MASTER IDT7030 ONLY)
__________ ______-x=
eEL VALID FIRST:
~
ADDR==>(
LAND R
,
ADDRESSES MATCH
r
lAPS~
CEl
CER
..tBAc=t
~tBDC=:}
BUSYR
CER VALID FIRST:
___________________x=
2690 drw 12
ADDR==>(
LAND R ,
ADDRESSES MATCH
~IAPS~
CER
CEl
.
1BAC=t
BUSYl
k
tBDC =:}
2690 drw 13
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION(1) (FOR
MASTER IDT7030 ONLY)
LEFT ADDRESS VALID FIRST:
~----tRC
ADDR l
--~~
OR
twc---~
ADDRESSES MATCH
-----------------------ADDRESSES DO NOT MATCH
ADDRR
BUSYR
2690 drw 14 '
RIGHT ADDRESS VALID FIRST:
~----tRC
ADDR R
----~
OR
twc--~~
------------------~--~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR l
BUSYl
NOTE:
1. crL
tBAA ,
_________:=~~~=_tB_D_A===~}~
2690 drw 15
= erR = VIL
6.2
10
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM SK (1K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7030
Symbol
20(1)
7030 x 25
7030 x 35
7030 x 45(2)
7040 X 20(1)
7040 x 25
7040 x35
7040 x 45(2)
X
Mln·.M:~.
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Interrupt Timing
tAs
Address Set-up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
o
o
o
o
o
o
o
35
35
25
25
NOTES:
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. "x· in part numbers indicates power rating (SA or LA).
ns
ns
40
40
ns
ns
2690tbl12
TIMING WAVEFORM OF INTERRUPT MODE(1,2)
LEFT SIDE SETS INfR:
~----------twc----------~
ADDRL
WRITE3FF
RiWL
________________t_IN_St
INTR
-------------------------------------------------------------------------------------------------------------------------------2690 drw 16
RIGHT SIDE CLEARS INTR:
~---------------------------tRc------------~~
ADORR
OER
READ 3FF
SSSL
\ss
-':=tINR
INTR
.
/
J-----------------------------
---j "
2690 drw 17
NOTES:
1. eEL =CE:R = VIL
2. rnTL and rnTR are reset (high) during power up.
6.2
11
IDTI030SAlLA AND ID17040SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT MODE(1,2)
RIGHT SIDE SETS INTL:
~----------lWC----------~
ADDRR
WRITE3FE
RiWR
_____________ll_NS_"t
INTL
~----------------------------~--------------------2690 drw 18
LEFT SIDE CLEARS INTL:
~-------------tRC------------~~
ADDRL
READ 3FE
OEL\SSSSSSS~
~IiNA
INTL
/
=:}___------------2690 drw 19
NOTES:
1. CtL = crR = VIL
2.
INfR and TNiL are reset (high) during power up.
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
pjW
RIGHT
RiW
pjW
IDT7030
MASTER
BUSY
-w.r
BUSY
+5V
+5V
pjW
AAA
yvV
pjW
IDT7040
SLAVE (1)
BUSY
BUSY
2690 drw20
NOTE:
1. No arbitration in IOT7040 (SLAVE). BUSY-IN inhibits write in IOT7040 (SLAVE).
6.2
12
IDTI030SAlLA AND IDTI040SAlLA
CMOS DUAL-PORT RAM 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IOT7030/IOT7040 provides two ports with separate
control, address, and I/O pins that permit independent access
for reads or writes to any locations in memory. The IOT7030/
IOT7040 has an automatic power down feature controlled
by CEo The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE high). When a port is enabled, access to
the entire memory array is permitted. Each port has its own
Output Enable control (OE). In the read mode, the port's
OE turns on the output drivers when set LOW. Noncontention REAO/WRITE conditions are illustrated in Table
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the
on-chip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before CE, on-chip control logic arbitrates between CEl
and CER for access; or (2) if the CEs are low before an
address match, on-chip control logic arbitrates between the
left and right addresses for access (refer to Table II). In
either mode of arbitration, the delayed port's BUSY flag is set
and will reset when the port granted access completes its
operation.
DATA BUS WIDTH EXPANSION
MASTER/SLAVE DESCRIPTION
1.
The interrupt flag (INT) permits communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INTl) is
set when the right port writes to memory location 3FE (HEX).
The left port clears the interrupt by reading address location
3FE (HEX). Likewise, the right port interrupt flag (INTR) is set
when the left port writes to memory location 3FF (HEX) and
to clear the interrupt flag (INTR) the right port must read the
memory location 3FF. The message (8-bits) at 3FE or 3FF
is user defined. If the interrupt function is not used, address
locations 3FE or 3FF are not used as mailboxes, but as
part of the random access memory. Refer to Table II for
the interrupt operation.
ARBITRATION LOGIC
FUNCTIONAL DESCRIPTION
The arbitration logic will resolve an address match or a
chip enable match down to 5ns minimum and determine
which port has access. In all cases, an active BUSY flag will
be set for the delayed port.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location.
When this situation occurs, on-chip arbitration logic will
determine which port has access and sets the delayed port's
BUSY flag. BUSY is set at speeds that permit the processor
to hold the operation and its respective address data. It is
important to note that the write operation is invalid for the
port that has BUSY set LOW. The delayed port will have
access when BUSY goes inactive.
6.2
Expanding the data bus width to sixteen-or-more-bits in
a dual-port RAM system implies that several chips will be
active at the same time. If each chip includes a hardware
arbitrator, and the addresses for each chip arrive at the
same time, it is possible that one will activate its BUSYL
while another acitivates its BUSYR signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTER/SLAVE approach where only one arbitrator, in
the MASTER, is used. The SLAVE has BUSY inputs which
allow an interface to the MASTER with no external
components and with a speed advantage over other
systems.
When expanding dual-port RAMS in width, the writing of
the SLAVE RAMS must be delayed, until after the BUSY
input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a contention situation. Conversely, the
write pulse must extend a hold time past BUSY to ensure that •
a write cycle takes place after the contention is resolved.
'
This timing is inherent in all dual-port memory systems where
more than on chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a
contention occurs, the write to the SLAVE will be inhibited
due to BUSY from the MASTER.
13
IDT7030SAlLA AND IDT7040SAlLA
CMOS DUAL-PORT RAM SK (1K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READIWRITE CONTROL(4)
Left or Right Port(1)
RtW
CE
OE
00-7
X
H
X
Z
Port Disabled and in Power
Down Mode 1882 or 1884
X
H
X
Z
CER = GEL = H, Power Down
Mode, 1881 or 1883
L
L
X
DATAIN
Function
H
L
L
DATAoUT
H
l
H
Z
Data on Port Written into Memory (2
Data in Memorv Output on Port (3)
OIJtnIJt~
Hiah
NOTES:
2690 tbl13
1. AOL - A9L"#- AOR - A9R
2. If BUSY = L, data is not written.
3. If BiJSY = L, data may not be valid, see twDD and tODD timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
TABLE II-INTERRUPT FLAG(1,4)
Left Port
Right Port
RIWL
CEL
OEL
AOL-A9L
lNTL
RIWR
CE"R
C>"E"R
AOR-A9R
TNfR
L
L
X
3FF
X
X
X
X
X
U2)
X
X
X
X
X
X
L
L
3FF
H(3)
X
X
X
X
L(3)
L
L
X
3FE
X
Set Left INTL Flag
X
L
L
3FE
H(2)
X
X
X
X
X
Reset Left INTL Flag
NOTES:
1. Assume BOSYL = BUSYR
2. If BiJSYL = L, then NC.
Function
Set Right INTR Flag
Reset Right INTR Flag
3. If BDSYR = L, then NC.
2690 tbl14
4. H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE.
= H.
TABLE 11- ARBITRATION(1,2)
Left Port
Flags(1)
Right Port
CEL
AOL-A9L
CER
AOR-A9R
BU"SVL
BUSYR
H
X
H
X
H
H
No Contention
Function
L
Any
H
X
H
H
No Contention
H
X
L
Any
H
H
No Contention
L
;{:AOR-A9R
L
;{:AOL-A9L
H
H
No Contention
L-PortWins
Address Arbitration With CE Low Before Address Match
L
LV5R
L
LV5R
H
L
L
RV5L
L
RV5L
L
H
R-PortWins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
L-PortWins
CE Arbitration With Address Match Before CE
LL5R
=AOR-A9R
LL5R
=AOL-A9L
H
L
RL5L
=AOR-A9R
RL5L
=AOL-A9L
L
H
R-PortWins
LW5R
=AOR-A9R
LW5R
=AOL-A9L
H
L
Arbitration Resolved
H
Arbitration Resolved
LW5R
=AOR-A9R
LW5R
=AOL-A9L
L
NOTES:
2690tbl15
1. INT Flags Don't Care.
2. X = DON'T CARE, L = LOW, H = HIGH. LV5R = Left Address Valid;:: 5ns before right address. RV5L = Right Address Valid;:: 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other. LL5R = Left CE = LOW;:: 5ns before Right CE.
RL5L = Right CE = LOW;:: 5ns before Left CEo LW5R = Left and Right CE = LOW within 5ns of each other.
6.2
14
G®
I DT7132SAlLA
IDT7142SAlLA
CMOS DUAL-PORT RAM
16K (2K x a-BIT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 25/30/35/45/55/70/90/1 00/120ns (max.)
- Commercial: 20/25/30/35/45/55/70/90/1 OOns (max.)
• Low-power operation
- IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-ormore bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)
• BUSY output flag on IDT7132; BUSY input on IDT7142
• Battery backup operation -2V data retention
• TTL-compatible, single 5V ±1 0% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
• Industrial temperature range (-40°C to +85°C) is available,
tested to miliary electrical specifications
The IDT7132/IDT7142 are high-speed 2K x 8 dual-port
static RAMs. The IDT7132 is designed to be used as a standalone 8-bit dual-port RAM or as a "MASTER" dual-port RAM
together with the IDT7142 "SLAVE" dual-port in 16-bit-ormore word width systems. Using the IDT MASTER/SLAVE
dual-port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT's CEMOSTM high-performance technology, these devices typically operate on only 325mW of
power at maximum access times as fast as 20ns. Low-power
(LA) versions offer battery backup data retention capability,
with each dual-port typically consuming 200JlW from a 2V
battery.
The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48- or 52-pin LCCs, 52-pin PLCCs,
and a 48-lead flatpacks. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883,
Class B.
FUNCTIONAL BLOCK DIAGRAM
A10L
.---+-f-- A10R
A7L
I/OOL
A7R
I/OOR
I/07L
BUSYL(l)
I/07R
O4I~;::::===;---:-_.~~_...,'-----;:====::::;-::~-.o
ASL
BUSYR(l)
ASR
AOL
AOR
-~-------'4---;-
Al0R
LOGIC
~ AOR
(IDT7132 ONLy) CER
RNVL--~~-----~- ~R
2692 drw 01
NOTE:
1. IDT7132 (MASTER): BUS'? is open drain output and requires pullup resistor.
IDT7142 (SLAVE): BUS'? is input.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL Tf:MPERATURE RANGES
©1992 Integrated Device Technology, Inc.
6.3
APRIL 1992
DSC·l001l3
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
CEL
R/Vh
BOSVL
Vee
LJ LJ LJ L. L,
CER
6 5 4 3
AIL :7
A2L :8
A3L :9
A4L
ASL
A6L :12
AlL :13
ASL : 14
A9L :15
I/OOL : 16
I/OIL
I/02L : 18
RIWR
BUSYR
AlaR
A10L
GEL
GER
AOL
AlL
A2L
A3L
A4L
:10
:11
AOR
Am
A2R
A3R
AsL
A4R
A6L
A5R
A6R
A7L
ASL
A9L
A7R
!/OOL
A9R
II01L
!/07R
!/06R
!/05R
AOR
AIR
A2R
A3R
A4R
ASR
A6R
AlR
ASR
A9R
I/07R
I/OSR
rl rl rl rl rl rl rl rl rl rl rl rl
2692 drw 03
48-PIN LCClFLATPACK
TOP VIEW
!/02R
!/Om
!/OOR
DIP
TOP VIEW
34:
33:
32:
31:
19 20 21 22 23 24 25 26 27 28 2930
II04R
II03R
GND
ILl L' LJ LI LI LJ
:17
ASR
!/02L
!/03L
!/04L
!/05L
!/06L
!/07L
I
2" 48 47 46 45 44 43
1
42:
41:
40:
39:
3S:
L48-1
37:::
&
36:
F4S-1
35:
2692 drw 02
INDEX
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
AIL
A2L
A3L
A4L
ASL
A6L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
-55 to +125
-65 to +150
°C
50
50
rnA
TSTG
A7L
ASL
A9L
1I00L
1I0lL
1I02L
DC Output
Current
NOTE:
:::9
::: 10
::: 11
::: 12
::: 13
:::
:::
:::
:::
:::
:::
L5~-2
OER
AOR
AIR
A2R
A3R
A4R
ASR
A6R
A7R
ABR
A9R
N/C
1I07R
2692 drw 04
2692 tbl 01
1. Stresses greater than those iisted under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + O.SV.
52-PIN LCC/PLCC
TOP VIEW
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
14
15
16
17
18
19
7 6 5 4 3 2 • J 52 51 50 49 48 47
1
46:
45::
44::
43::
42::
J52-1
41::
40:::
39::
38::
37::
36::
35::
34
1I03L ::: 20 21 22232425262728293031 3233 ::
Temperature
lOUT
:::8
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
V
VIH
Input High Voltage
-
VIL
Input Low Voltaqe
2.2
-0.5(1)
0
6.0(2)
-
0.8
V
NOTE:
Grade
Military
Commercial
V
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
2692tbl03
2692 tbl 02
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + O.SV.
6.3
2
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLV VOLTAGE RANGE (Vcc = 5.0V +10%)
Symbol
Parameter
IDT7132LA
IDT7142LA
Max.
Max.
IDT7132SA
IDT7142SA
Min.
Max.
Test Conditions
Unit
Ilul
Input Leakage
Current(9)
Vee = 5.5V, VIN = OV to Vee
-
10
-
5
JlA
lilol
Output Leakage
Current
CE = VIH, Your = OV to Vee
-
10
-
5
JlA
Val
Output Low Voltage
(1/00-1/07)
IOl=4mA
-
0.4
-
0.4
V
VOL
Open Drain Output
Low Voltage (BUsY)
IOl = 16mA
-
0.5
-
0.5
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
V
2692 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLE VOLTAGE RANGE(1,8) (Vcc
Test Conditions
Symbol
Parameter
Icc
Dynamic Operating
Current (Both Ports
Active)
GE= Vil
Standby Current
(Both Ports - TIL
Level Inputs)
GEL and GER ~ VIH
1582
Standby Current
(One Port-TIL
Level Inputs)
GEL or GER ~ VIH
1583
Full Standby Current
(Both Ports - All
GER ~ Vee -0.2V
CMOS Level Inputs
VIN ~ Vee -0.2V or
VIN::; 0.2V,f = 0(5)
1581
1584
Full Standby Current
(One Port - All
CMOS Level Inputs)
Outputs Open
f = fMAX(4)
7132 x 20(2,6) 7132 x 25(6) 7132
Version 7142 x 20(2,6) 7142 x 25(6) 7142
Mil.
SA
LA
=
5.0V ± 10%)
x 30 (6)
x 30 (6)
7132 x 35(7)
7142 x 35(7)
7132 x 45
7142 x 45
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
125 300 125 295 125 290 75 230
.. 125 240 125 235 125 230 75 185
~--~S~A~~1~2S~::~}2~6~5~~12~5~2~6~0~~12~5~2~5~5~:75~~1~9~5~7~5~~19~0~mA
ComlLA
125:.. 215
125
210
125
205
75
155
75
145
f = fMAX(4)
M'I
SA - ' :::"80 195
80 190 80 185 40 135
I. LA --'::::::::::::::::~
80 160 80 155 80 150 40 110
Active Port Outputs ~--~S~A~~8~O+.~:+':.~~8~0~~8~0--~17~5~~8~0--~17~0~~4~0~1~3~0+-4~0~~1720~mA
Open, f = fMAX(4)
Com1LA 80 {\:}45
80 140
80 135 40
95
40
85
Both Ports CEl and
One Port GEL or
GER ~ Vee -0.2V
VIN ~ Vee -0.2V or
VIN::; 0.2V
Active Port Outputs
Open, f = fMAX(4)
Mil. t t - ::::::::L
1.0 30
1.0 30
1.0 30
1.0 30
I----=-~--:-::::::.-.:::~::"__1--0...;.;.2.;....-....;1....;;.0-+...;;0..;.;;.2~....;1....;;.0-+-_0;.;;;.2~...;.,10~_0:...;..2~_1.:....:0~ mA
comltt
Mil.
SA
LA
6:~":' ::.~~
6:~
\5
6:~
155
6:~
~5
6:~
1]
::::··::::L
::/\::':-
70
70
185
150
70
70
180
145
70
70
175
140
40
35
125
95
70
70
170
135
70
70
165
130
40
35
115
90
40
35
105
80
~----~--~~-4--------~------~----~~----~mA
comlSLAA
70<::::.175
7ri ::':':140
2692 tbl 05
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. Atf= fMax, address and control lines (except Output Enable) are cycling althe maximum frequenc.;y read cycle of 1/tRc, and using "AC TEST CONDITIONS·
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Not available in DIP packages - see 7032/7042 data sheet.
7. DIP packages for O°C to +70°C temperature range only - see 703217042 data sheet.
8. Vcc=5V, TA=+25°C for Typ.
9. At Vcc~2.0V input leakages are undefined.
6.3
3
•
•
1DT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K ~ a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1,8) (Continued) (Vcc = 5.0V +
- 10%)
Symbol
lee
IS81
IS82
IS83
IS84
Parameter
Test Conditions
Mil.
Dynamic Operating
Current (Both Ports
Active
GE = VIL
Outputs Open
f= fMAX(4)
Standby Current
(Both Ports - TTL
Level Inputs)
CEl and CER ~ VIH
f = fMAX(4)
Standby Current
(One Port - TTL
Level Inputs)
GEL or GER ~ VIH
Active Port Outputs
Open, f = fMAX(4)
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports GEL and
CER ~ Vee -0.2V
VIN ~ Vee -0.2V or
VIN ~ 0.2V,f = 0(5)
Full Standby Current
(One Port - All CMOS
Level Inputs)
One Port GEL or
CER ~ Vee -0.2V
VIN ~ Vee -0.2V or
VIN ~ 0.2V
Active Port Outputs
Open, f = fMAX (4)
7132 x 55 7132 x 70
7142 x55 7142 x 70
Typ. Max. Typ. Max.
Version
~
~§ 230
~~ ~~g
~~ ~~~
Com'I.Et
65
65
65
25
25
25
25
40
40
40
40
SA
LA
SA
Com 'I. LA
1.0 30
0.2 10
1.0 15
0.2 4
1.0 30
0.2 10
1.0 15
0.2 4
1.0
0.2
1.0
0.2
30
10
15
4
1.0 30
0.2 10
1.0 15
0.2 4
1.0 30
0.2 10
SA
LA
40120
35 90
40 115
35 85
40 110
35 80
40 110
35 80
40 110
35 80
Com'l.E:'
40100
35 75
40 100
35 75
40 95
35 70
40
35
- --
Com'l.E:'
Mil.
SA
LA
Com'l.E:'
Mil.
SA
LA
Mil.
Mil.
185
180
140
65
55
65
45
135
110
115
85
~~ 225
7132 x90 7132 x 100 7132 x 120(3)
7142 x 90 7142 x 100 7142 x 120
Typ. Max. Typ. Max. Typ. Max.
65 190
65155
65 180
65 180
- 65 130
65 130
- 25 65
25 65
25 65
25 45
25 45
25 45
25 55
25 55
25 35
25 35
40 125
40 125
40 125
40 100
40 100
40 100
40 110
40 110
- 40 75
75
40
- -
65
65
65
25
25
25
25
40
40
40
40
180
180
135
65
55
60
40
135
110
110
85
-
-
-- --
95
70
Unit
mA
mA
mA
mA
mA
2692tbl06
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. Atf= fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
"AC TEST CONDITIONS· of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Not available in DIP packages - see 7032/7042 data sheet.
7. DIP packages for O°C to +70°C temperature range only - see 703217042 data sheet.
8. Vcc=5V, TA=+25°C for Typ.
DATA RETENTION CHARACTERISTICS (LA Version Only)
IDT7132LAlIDT7142LA
Symbol
Parameter
VOR
Vee for Data Retention
leeDR
Data Retention Current
teoR(3)
tR(3)
Test Conditions
Vee = 2.0V, CE ~ Vee -0.2V
VIN c Vee -0.2V or VIN ~ 0.2V
Chip Deselect to Data
Retention Time
Min.
I Mil.
I Com'l.
-
0
Operation Recovery
Typ.
2.0
tRe(2)
Max.
Unit
0
V
100
4000
jlA
100
f500
JlA
-
-
ns
-
-
ns
Time
NOTES:
1. Vcc = 2V, TA = +25°C
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not tested.
2692tbl07
6.3
4
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
Vee
CE
VOR~
4.5V
2.0V
GND TO 3.0V
5ns
1.5V
1.5V
See Figures 1, 2, & 3
2692 tbl 08
7zk,'CDR,
VOR
VIH
2692 drw 05
5V
5V
1250n
DATAOUT~---i
DATAoUT .......- - - i
775n
775n
Figure 1. Output Load
5pF*
Figure 2. Output Load
(for tHY, tLZ, twz, and tow)
5V
--t1
270n
BUSY
100pF*
(30pF for 20ns, 25ns &
30ns versions and 35ns
military)
Figure 3. Busy Output Load
(IDT7132 only)
• Including scope and jig
6.3
2692 drw06
5
IDT7132SAlLA AND 1DT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
Symbol
Parameter
Read C cle
Read Cycle Time
tRG
tAA
Address Access Time
Chip Enable Access Time
tAGE
tAOE
Output Enable Access Time
tOH
Output Hold From Address Chanqe
Output Low Z Time(1,4)
tLZ
Output High Z Time(l,4)
tHZ
tpu
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
tPD
7132 x 20(2,6)
7142 x 20(2,6)
Min,
Max.
-
30
-
35
-
45
-
-
30
30
15
-
35
35
25
-
45
45
30
-
0
-
a
-
a
a
-
5
-
5
-
10
-
12
-
a
-
a
50
-
50
-
-
'''::20
::':\::10
.,;::::::' -
a
a .::<> -
cf'
·4
Max.
7132 x 45
7142 x 45
Min. Max.
25
25
12
,::20
-~~(/
Min.
7132 X 35(7)
7142 x 35(7)
Min. Max.
-
-
7132 x 30(6)
7142 x 30(6)
25
+
20
7132 x 25(6)
7142 x 25(6)
Max.
Min.
8
a
a
-
15
-
a
-
50
-
50
a
-
20
50
. Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 tbl 09
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5) (Continued)
Symbol
Parameter
Read C cle
Read Cycle Time
tRG
Address Access Time
tAA
Chip Enable Access Time
tACE
Output Enable Access Time
tAOE
tOH
Outout Hold From Address Chanae
Output Low Z Time(l,4)
tLZ
Output High Z Time(1,4)
tHZ
tpu
Chip Enable to Power Up_ Time(4)
Chip Disable to Power Down Time(4)
tPD
7132 x 55
7142 x 55
Min.
Max.
7132 x 70
7142 x 70
Min.
Max.
7132 x90
7142 x 90
Min. Max.
55
-
70
-
90
-
55
55
35
-
70
70
40
-
-
0
5
0
5
a
-
30
50
a
-
7132 x 100
7142 x 100
Min. Max.
7132 x 120(3)
7142 x 120(3)
Min.
-
100
-
120
-
-
-
90
90
40
-
100
100
40
-
120
120
60
10
5
-
-
-
10
5
-
10
5
-
35
-
40
-
40
-
-
50
a
-
-
50
-
a
-
50
0
-
40
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 tbll0
NOTES:
1.
2.
3.
4.
5.
6.
7.
Max.
Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
O°C to +70°C temperature range only.
-55'C to +125°C temperature range only.
This parameter guaranteed but not tested.
"x" in part numbers indicates power rating (SA or LA).
Not available in DIP packages - see 7032n042 data sheet.
DIP packages for O°C to +70°C temperature range only - see 7032n042 data sheet.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
------J;~~----------------------tRC----------------------~~~
ADDRESS
DATAoUT
-----'~~~~~=~~=~~-t-O--H----~t-AA-----.=,=======:.~I----------------------~~~-tO-H----------PREVIOUS DATA VALID
DATA VALID
NOTES:
2692 drw 07
1. RJW is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addressps valid prior to or coincident with CE transition low.
4. DE' = VIL.
6.3
6
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE (1,3)
tACE
~~.
/~
tAOE
~
.
tHZ
/V
"-tLZ-
7r
DATA OUT
~I.:-
I--tHZ-
< < ~:
-'",-
DATA VALID
~<...
tLZ
=~~~~~~~~~-_-_-_~-_-.-}+'7'5-0-O/c-O-------------------5-O~%~
.
-tpu
I
CURRENT : :
I
tPD
I.-
_ _ __
2692 drw 08
NOTES:
1. RIW is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = VIL.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)
Symbol
Parameter
Write Cycle
Write Cycle Time(5)
twc
tEW
Chip Enable to End of Write
tAW
Address Valid to End of Write
tAS
Address Set·up Time
Write Pulse Width(6)
twp
Write Recovery Time
tWR
tDW
Data Valid to End of Write
Output High Z Time(l,4)
tHZ
tDH
Data Hold Time
Write Enabled to Output in High Z(l,4)
twz
Output Active From End of Write(1,4)
tow
7132 x 20(2,8)
7142 x 20(2,8)
7132 x 25(8)
7142 x 25(8)
7132 x 30(8)
7142 x 30(8)
7132 x 35(9)
7142 x 35(9)
7132 x 45
7142 x 45
Min.
Min.
Min. Max.
Min.
Min.
20
15
15
0
15
a
1a
Max.
-
+::
"$.
.::~;:...
: ::.:-
c,?:=::-
<,/ -./:::/ 8
a::,;,::::'·
4"
a
25
20
20
a
2a
a
12
-
8
-
0
a
Max.
-
30
25
25
a
25
a
15
-
-
-
35
30
30
a
3a
a
2a
-
-
1a
-
12
-
0
-
1a
-
-
a
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2, and 3).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, twc = tBAA + twP.
6. Specified for OE at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. "x" in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages - see 703217042 data sheet.
9. DIP packages for O°C to +70°C temperature range only - see 703217042 data sheet.
6.3
-
Max.
a
Max.
-
-
45
35
35
a
35
a
2a
-
15
-
2a
-
a
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
-
12
-
15
-
20
-
a
-
a
-
ns
ns
ns
ns
2692 tblll
7
IDT7132SAlLA AND ID17142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPL V VOLTAGE RANGE(7) (Continued)
Symbol
Parameter
Write Cycle
Write Cycle Time (5)
twc
Chip Enable to End of Write
tEW
tAW
Address Valid to End of Write
tAS
Address Set-up Time
twp
Write Pulse Width (6)
tWA
Write Recovery Time
Data Valid to End of Write
tDW
Output High Z Time (1,4)
tHZ
tDH
Data Hold Time
Write Enabled to Output in High Z(1,4)
twz
Output Active From End of Write(1,4)
tow
7132 x 55
7142 x 55
7132 x 70
7142 x 70
7132 x 90
7142 x 90
7132 x 100
7142 x 100
7132 x 120(3)
7142 x 120(3)
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min.
55
40
40
0
40
0
20
-
-
-
70
50
50
0
50
0
30
-
90
85
85
0
55
0
40
-
30
-
35
-
0
-
0
-
0
-
30
-
35
0
-
0
-
-
-
-
100
90
90
0
55
0
40
-
120
100
100
0
65
0
40
40
-
40
-
-
0
-
-
40
-
40
-
50
0
-
0
-
0
-
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1,2 and 3).
2. QOG to +70oG temperature range only.
3. -55°G to +125°G temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, twe = tBAA + twP.
6. Specified for DE' at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. "x' in part numbers indicates power rating (SA or LA).
-
Max.
-
0
-
-
40
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26921bl12
CAPACITANCE (TA = +25°C,f = 1.0MHz)
Parameter (1)
Input Capacitance
Output Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
26921bl13
6.3
8
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (RIW CONTROLLED TIMING)(1,2,3,7)
twc
ADDRESS
DE
CE
twp(7)
RiW
DATA OUT
tow
tOH
DATA IN
2692 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
twc
=>K
i4--tAS
)(
..
tAW
1
/v
tEW
L
l1"-
DATA IN
tWR
tow
tOH
.1
1
/1
2692 drw 10
NOTES:
1. RNI must be high during all address transitions.
2. A write occurs during the overlap (lEW or twp) of a low CE: and a low RfN.
3. twR is measured from the earlier of CE: or RIW going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
S. If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig).
7. If OE is low during a RlW controlled write cycle, the write pulse width must be larger of twp or (twz + tDW) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tDW. If C51: is high during an RfN controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.3
9
IDT7132SAlLA AND ID17142SAlLA
CMOS DUAL-PORT RAM 16K (2K X S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
Symbol
Parameter
7132 x 20 (1,1~
7142 x 20 (1,1~
Min.
Max.
7132 X 25(10) 7132 x 30(10) 7132 x 35 (11)
7132 X 25 (10) 7142 X 30 (10) 7132 X 35 (11)
Min.
Max.
Min. Max.
Min. Max.
7132 X 45
7142 X 45
Min. Max.
Unit
Busy Timing (For Master 1017132 Only)
tBAA
BUSY Access Time to Address
tBOA
tBOC
BUSY Disable Time to Address
BUSY Access Time to Chip Enable
BUSY Disable Time to Chip Enable
tWOD
Write Pulse to Data Delay (3)
tODD
Write Data Valid to Read Data Delay (3)
tAPS
Arbitration Priority Set-up Time (4)
tBOD
BUSY Disable to Valid Data (5)
tBAC
-
20
-
25
-
30
-
20
25
-
go
-
20
25
-
30
-
::40
-
20
25
-
25
\:50
::=:35
-
50
-
-
35
29
50
-
60
35
-
35
-
5
-
5
-
:
::2~ :;::Note 5
5
-
35
Note 5
5
-
Note 5
-
30
Note 5
-
35
35
ns
-
30
ns
25
ns
-
70
ns
5
-
ns
45
ns
-
ns
Note 5
ns
Busy Input Timing (For Slave 1017142 Only)
tWB
Write to BUSY Input (6)
0:<:::=
tWH
Write Hold After BUSY (7)
1Jt:
-
tWOD
Write Pulse to Data Delay (9)
4-
50
toDD
Write Data Valid to Read Data Delay(9)
-
35
0
15
-
-
20
-
50
-
50
35
-
35
0
0
20
-
60
35
0
20
-
-
ns
ns
70
ns
45
ns
26921bl14
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
Symbol
Parameter
7132 x 55
7142 x 55
Max.
Min.
7132 x 70
7142 x 70
Min.
Max.
7132 x 90
7142 x 90
Min. Max.
7132 x 100
7142 x 100
Min. Max.
7132 x 120(2)
7142 x 120(2)
Min. Max.
Unit
Busy Timing (For Master 1017132 Only)
45
-
50
45
-
50
45
90
-
100
70
-
90
-
50
30
-
tBAA
BUSY Access Time to Address
-
45
-
45
tBOA
-
40
-
40
-
35
30
tWOD
Write Pulse to Data Delay (3)
80
-
tODD
Write Data Valid to Read Data Delay(3)
-
35
tBoc
BUSY Disable Time to Address
BUSY Access Time to Chip Enable
BUSY Disable Time to Chip Enable
55
-
tAPS
Arbitration Priority Set-up Time(4)
5
tBOD
BUSY Disable to Valid Data (5)
-
tBAC
Note 5
5
-
Note 5
5
-
45
Note 5
5
-
60
ns
120
-
140
ns
100
-
120
ns
-
ns
50
Note 5
5
-
60
ns
60
ns
60
ns
Note 5
ns
Busy Input Timing (For Slave IOT7142 Only)
BUSY InpuH6)
tWB
Write to
tWH
Write Hold After BUSY(7)
20
0
tWOD
Write Pulse to Data Delay(9)
tOOD
Write Data Valid to Read Data Delay(9)
-
80
55
0
-
0
20
-
20
-
90
-
70
100
90
0
20
-
120
100
0
-
ns
20
-
ns
-
140
ns
120
ns
NOTES:
2692 Ibl15
1. O'C to +70°C temperature range only.
2.
-55°C to +125°C temperature range only.
.
3.
Port-to-port delay through RAM cells from writing port to reading port, refer to "TIming Waveform of Read With BDSV (For Master IDT7132 only)".
To ensure that the earlier of the two ports wins.
4.
5.
tBDD is a calculated parameter and is the greater of 0, twDD-twP (actual) or tDDD - tDW (actual)
6.
To ensure that the write cycle is inhibited during contention.
7.
To ensure that a write cycle is completed after contention.
8.
"x· in part numbers indicates power rating (SA or LA).
9.
Port-to-port delay through RAM cells from writing port to reading port, refer to "TIming Waveform of Read With Port-to-Port Delay (For Slave 1D17142
Only)".
10. Not available in DIP packages - see 703217042 data sheet.
11. DIP packages for O°C to +70°C temperature range only - see 703217042 data sheet.
6.3
10
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K X S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF REAO WITH BUSY (1,2,3) (FOR MASTER IOT7132 ONLY)
ADDRR
)K
,\/
MATCH
/,
twp
~K.
RlWR
/1'
>KH
tDW
)K
DATAINR
VALID
-tAPS(1)
ADDRL
MATCH
tBDA~
}-
\
BUSYL
l---"
tBDD---"
tWDD
)K
DATAOUTL
VALID
toDD (4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continously enabled for both ports.
4. 0"1: at LO for the reading port.
2692 drw 11
TIMING WAVEFORM OF REAO WITH PORT-TO-PORT OELAy(1,2,3) (FOR SLAVE IOT7142 ONLy)
t
ADDRR
twc
>k
)(
MATCH
twp
~,
RiWR
/1'
)~t
tow
)(
DATAINR
VALID
MATCH
ADDRL
tWDD
)K
DATAOUTL
VALID
tDDD
NOTES:
1. Assume BOSV input at HI for the writing port, and OE at LO for the reading port.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
2692 drw 12
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (FOR SLAVE IOT7142 ONLY)
twp
WW
-{tw,}
}tWHi
BUSY
2692 drw 13
6.3
11
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K X a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE.ARBITRATION
(FOR MASTER IOT7132 ONLY)
CEL VALID FIRST:
ADDR===>(
LAND R
___________________x=
ADDRESSES MATCH
~tAPsh
"ACq
CEl
CER
BUSYR
CER VALID FIRST:
ADDR===>(
LAND R
'
GEL
~"DC=:}
2692 drw 14
___________________x=
ADDRESSES MATCH
~tAPSh
CER
1
tBAcq
BUSYl
h
teDC =:}
2692 drw 15
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, AOORESSVALIO ARBITRATION(1)
(FOR MASTER IOT7132 ONLY)
i4-----'tRC OR
ADDR l
)(
---~
twc-----I~
ADDRESSES MATCH
)(
ADDRR
ADDRESSES DO NOT MATCH
~---------------------
tAPS~
+-__________________________
~--------------------+---------------------------~
~
) (~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _- J
~tBAA9
BUSYR
______\'"II!_·~~~~~t_BD_A~~~~~}~
2692 drw 16
RIGHT ADDRESS VALID FIRST:
14-----'tRC OR
twc-----~
ADDRESSES MATCH
ADDRR
ADDRESSES DO NOT MATCH
ADDR l
\'"II!4f----tBDA--.....1~,
_ _ _ _ _ _ _t_BM_-----j
BUSYl
NOTE:
______________
;f
~
-------------
2692 drw 17
1. ct:L =crR = VIL
6.3
12
IDT7132SAllA AND IDT7142SAllA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RIGHT
-
RlW
RlW
-
IDT7132
RlW
RlW
MASTER
BUSY
AAA
",'1'",
BUSY
+5V
+5V
-
RlW
AAA
YYV
-
IDT7142
RlW
SLAVE (1)
BUSY
BUSY
2692 drw 18
NOTE:
1. No arbitration in IDT7142 (SLAVE). BUSY-IN inhibits write in IDT7142 (SLAVE).
FUNCTIONAL DESCRIPTION:
and CER for access; or (2) if the CEs are low before an address
match, on-chip control logic arbitrates between the left and
right addresses for access (refer to Table II). In either mode of
arbitration, the delayed port's BUSY flag is set and will reset
when the port granted access completes its operation.
The IDT7132142 provides two ports with separate control,
address, and liD pins that permit independent access for
reads or writes to any locations in memory. These devices
have an automatic power-down feature controlled by CEo The
CE controls on-chip power-down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output
Enable control (DE). In the read mode, the port's DE turns on
the output drivers when set LOW. Non-contention READI
WRITE conditions are illustrated in Table 1.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in a
dual-port RAM system implies that several chips will be active
at the same time. If each chip includes a hardware arbitrator, •
and the addresses for each chip arrive at the same time, it is
possible that one will activate its BUSYlwhile another acitivates •
its BUSYR signal. Both sides are now busy and the CPUs will
wait indefinitely for their port to become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTERISLAVE approach where only one arbitrator, in the
MASTER, is used. The SLAVE has BUSY inputs which allow
an interface to the MASTER with no external components and
with a speed advantage over other systems.
When expanding dual-port RAMs inwidth, the writing of the
SLAVE RAMs must be delayed, until after the BUSY input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, thewrite pulse must
extend a hold time past BUSY to ensure that a write cycle
takes place after the contention is resolved. This timing is
inherent in all dual-port memory systems where more than on
chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then,acontention
occurs, the write to the SLAVE will be inhibited due to BUSY
from the MASTER.
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip
enable match down to 5ns minimum and determine which port
has access. In all cases, an active BUSY flag will be set for the
delayed port.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location.
When this situation occurs, on-chip arbitration logic will
determine which port has access and sets the delayed port's
BUSY flag. BUSY is set at speeds that permit the processor
to hold the operation and its respective address data. It is
important to note that the write operation is invalid for the port
that has BUSY set LOW. The delayed port will have access
when BUSY goes inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the
on-chip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before CE, on-chip control logic arbitrates between CEl
6.3
13
1D17132SAlLA AND ID17142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READIWRITE CONTROL(4)
Left Or RiQht Port (1)
RtW CE
X
H
OE
00-7
X
Z
X
H
X
L
H
H
L
L
L
X
L
H
Function
Port Disabled and in Power
Down Mode IS82 or IS84
CER = GEL = H, Power Down
Mode, IS81 or ISB3
DATAIN Data on Port Written into Memory(2)
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance
Z
~692tb116
NOTES:
1. AOl- Al0l;t AOR- Al0R
2. If BUSY = L, data is not written
3. If BOSY = L, data may not be valid, see twoo and tBOO timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
TABLE 11- ARBITRATION(1,2)
eEL
Left Port
AOl - Al0l
Right Port
Flags
AOR - Al0R
I30SYl
BUSYR
X
X
H
H
No Contention
H
H
No Contention
Any
H
H
H
H
No Contention
No Contention
H
X
H
L
Any
H
X
H
L
*-AOR -Al0R
L
*-AOL -A1OL
L
Address Arbitration With CE Low Before Address Match
LV5R
L
LV5R
L
RV5L
RV5L
L
L
Same
L
Same
L
L
Same
L
CE Arbitration With Address Match Before CE
= AOR -Al0R
LL5R
LL5R
= AOR -Al0R
RL5L
RL5L
=AOR -Al0R
LW5R
LW5R
LW5R
= AOR -Al0R
Function
CER
LW5R
H
L
H
L
L-PortWins
H
L
H
R-PortWins
Arbitration Resolved
Same
L
= AOL -Al0L
= AOL -Al0L
= AOL -Al0L
=AOL -Al0L
H
L
L-PortWins
L
H
H
L
R-PortWins
Arbitration Resolved
L
H
Arbitration Resolved
Arbitration Resolved
2692tbl17
NOTES:
1. X = DON'T CARE, L = LOW, H = HIGH
2. LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid;:: 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW;:: 5ns before Right IT.
RL5L = Right IT = LOW;:: 5ns before Left CEo
. LW5R = Left and Right CE = LOW within 5ns of each other.
6.3
14
(;)®
.'
CMOS DUAL-PORT RAM
16K (2K x a-BIT)
PRELIMINARY
I DT7032SAlLA
I DT7042SAlLA
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION:
• High-speed access
-Military: 25/35/45ns (max.)
-Commercial: 20/25/35ns (max.)
• Low-power operation
-IDT7032/42SA
Active: 400mW (typ.)
Standby: 7mW (typ.)
-IDT7032/42LA
Active: 400mW (typ.)
Standby: 2mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7032 easily expands data bus width to 16or-more-bits using SLAVE IDT7042
• On-chip port arbitration logic (IDT7032 only)
• BUSY output flag on IDT7032; BUSY input on IDT7042
• Battery backup operation -2V data retention
• TTL-compatible, single 5V ±1 0% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT7032/1DT7042 are high speed 2K x 8 dual-port
static RAMs. The IDT7032 is designed to be used as a
stand-alone 8-bit dual-port RAM or as a "MASTER" dualport RAM together with the IDT7042 "SLAVE" dual-port in
16-bit-or-more word width systems. Using the IDT MASTER!
SLAVE dual-port RAM approach in 16-or-more-bit memory
system applications results fn full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independant ports with separate
control, address, and 1/0 pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CEMOSTM high-performance
technology, these devices typically operate on only 400mW
of power at maximum access times as fast as 20ns. Lowpower (LA) versions offer battery backup data retention
capability, with each dual-port typically consuming 200llW
from a 2V battery.
The IDT7032/7042 devices are packaged in 48-pin
sidebraze or plastic DIPs. Military grade product is
manufactured in compliance with the latest revision of MILSTD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
Riiih
CEL
RlWR
CER
OEL
OER
A10L
AlL
IIOOL
Al0R
A7R
I/OOR
I/07L
BUSVL(l)
I/07R
BUSVR(l)
ASL
ASR
AOL
AOR
RNVL--~~------~'--
RNVR
2693 drw 01
NOTE:
1. IDT7032 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7042 (SLAVE): BUSY is input.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
6.4
APRIL 1992
DSC·l077/1
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K X a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CEL
R/WL
CER
R/WR
8USYL
BlJSVR
AWL
A10R
OEL
OER
AOL
AOR
A1L
A1R
A2L
A2R
A3L
A3R
A4L
A4R
ASL
ASR
GND
Vee
A6L
A6R
A7L
A7R
ABL
ABR
A9L
A9R
I/OOL
1/07R
1/01L
1/06R
1/02L
I/OSR
1/03L
1I04R
1/04L
1/03R
I/OSL
1/02R
1/06L
1/01R
1/07L ---='-'-_ _-=:...r- I/OOR
2693 drw02
DIP
Top View
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
with Respect to
GND
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65to +135
°C
Storage
-55 to +125
-65 to +150
°C
50
50
mA
TSTG
Commercial
DC Output
Current
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V
± 10%
26931bl02
RECOMMENDED
DC OPERATING CONDITIONS
Temperature
lOUT
Ambient
Temperature
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
6.0(2)
V
VIL
In~ut Low VoltCille
Symbol
NOTE:
26931blOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI NGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposureto absolute maximum rating conditions for extended
periods may affect reliability.
2. VTEAM must not exceed Vee + O.SV.
2.2
-0.5(1)
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTEAM must not exceed Vee + O.SV.
6.4
-
0.8
V
2693 Ibl 03
2
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = s.OV +10%)
Symbol
Parameter
IDT7032SA
IDT7042SA
Min.
Max.
Test Conditions
IDT7032LA
IDT7042LA
Max.
Max.
Unit
IILlI
Input Leakage
Current(7)
Vee = 5.5V, VIN = OV to Vee
-
10
-
5
jlA
Illol
Output Leakage
Current
CE = VIH, VOUT = OV to
-
10
-
5
J.LA
Val
Output Low Voltage
(IIOo-IIO?)
IOL= 4rnA
-
0.4
-
0.4
V
Val
Open Drain Output
Low VoltageJBUSY)
IOl = 16mA
-
0.5
-
0.5
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
Vee
V
2693tbl04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc = s.OV ± 10%)
Symbol
lee
1581
Parameter
Test Conditions
Dynamic Operating
Current (Both Ports
Active)
CE = Vil
Outputs Open
f = fMAX(4)
Standby Current
(Both Ports - TIL
Level Inputs)
CEl and CER ~ VIH
f = fMAX(4)
Version
1583
1584
Standby Current
(One Port - TIL
Level Inputs)
Full Standby Current Both Ports GEL and
(Both Ports - All
CER ~ Vcc -0.2V
CMOS Level Inputs) VIN ~ Vee -0.2V or
VIN::; 0.2V, f = 0(5)
7032 x 35
7042 x35
7032 x 45(3)
7042 x 45(3)
Typ. Max.
Typ. Max.
Typ. Max.
Typ. Max.
Unit
mA
125
125
125
125
30
30
30
30
80
80
300
240
260
210
80
60
65
45
195
160
125
125
125
125
30
30
30
30
290
230
250
200
80
60
65
45
125 285
125 225
80
80
185
150
80
80
180
145
rnA
COM'L.~
80
80
175
140
80
80
165
130
SA
1.0
0.2
1.0
0.2
70
70
70
70
30
10
15
1.0
0.2
1.0
0.2
70
70
70
70
30
10
15
1.0
0.2
30
10
rnA
MIL.
LA
COM'L.~
MIL.
-::....
125 ::::265
125:~Hj
SA
LA
COM'L SA
CEl or GER ~ VIH
Active Port Outputs
Open, f = fMAX(4)
7032 x 25
7042 x 25
SA
'LA
1582
7032 x 20(2)
7042 x 20(2)
3ci
::,:::q~9
30
:::))~5
SA
MIL.
MIL.
LA
LA
COM'L.~
SA
Full Standby Current One Port CEl or
MIL.
LA
(One Port - All
GER ~ Vcc -0.2V
CMOS Level Inputs) VIN ~ Vcc -0.2V or
COM'L SA
. LA
VIN ::; 0.2V Active Port
Outputs Open, f =fMAX(4)
1'.0. :':15
tfz)i 5
:,~::::;:
....;;.:
:\2 ... _
\10
175
::::::ic)" ::: 140
5
185
150
170
135
rnA
30
30
80
60
rnA
mA
mA
5
175
140
160
125
rnA
70
70
170
135
rnA
rnA
2693tbl05
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. Atf; fMAX, address and control lines (except Output Enable) are cycling atthe maximum frequency read cycle of 1/tRc, and using "AC TEST CONDITIONS"
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc=5V, TA=+25°C for Typ.
7. At Vcc$2.0V input leakages are undefined.
6.4
3
ID17032SAlLA AND ID17042SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
IDT7032LAlIDT7042LA
Typ.(1)
Min.
Max.
Test Conditions
Parameter
VOR
Vee for Data Retention
ICCDR
Data Retention Current
tCOR(3)
Chip Deselect to Data
Vee = 2.0V,
I MIL.
I COM'L.
CE ~ Vee -0.2V
VIN ~ Vee -0.2V or VIN S 0.2V
2.0
-
0
Unit
0
V
100
4000
Jl}\
100
1500
J.lA
-
-
ns
-
-
ns
Retention Time
tR(3)
tRC(2)
Operation Recovery
Time
2693 tbl06
NOTES:
1. Vec = 2V, TA = +25°C
2. tAc = Read Cycle Time
3. This parameter is guaranteed but not tested.
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fail Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
VCC
4.5V
d
VOR~ 2V
GNDT03.0V
5ns
1.5V
1.5V
See Figures 1 , 2 & 3
tCDR
2693 tbl 07
,~_____V_D_R____~/
tRb
v~
~H
2693 drw03
5V
5V
1250n
1250n
DATA OUT ~----....
DATA OUT ~----....
775n
775n
30pF*
5pF*
Figure 2. Output Load
(for tHZ, tLl, twz, and tow)
Figure 1. Output Load
5V
~130
270n
BUSY
PF.
2693 drw 04
Figure 3. trnSY Output Load
(1017032 only)
* Including scope and jig
6.4
4
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K X a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7032 x 20(2)
7042 x 20(2)
Symbol
Read Cycle
tRc
Parameter
Min.
7032 x 35
7042 x 35
Min. Max.
7032 X 45(3)
7042 x 45(3)
Min.
Max.
Unit
45
45
45
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-;:::?:::.:.:
r),.,
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low Z Time (1,4)
Output High Z Timell,4)
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
tAA
tACE
tAOE
tOH
tLZ
tHZ
tpu
tpo
Max.
7032 x 25
7042 x 25
Min. Max.
25
-
35
-
25
25
12
-
--
-
0
0
-
0
0
8
-
10
-
-
0
-
-
50
0
-
20
-:':;;;:)::'20
- :::::::·;:::::'20
- :::::::::::::: 10
o :,::::'\ 0
0
:-:.:::
.\:::,:.::
~:J2 50
-
35
35
25
-
15
50
0
0
0
20
50 '
-
2693 tbl 08
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1,2 and 3).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. ·x" in part numbers indicates power rating (SA or LA).
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE (1,2,4)
~~~---------------------tRC----------------------~~~
ADDRESS
-----'l::~~-~=--==--=t=O=H=~-tA-A~~.--,-------------~-.:1------------------------~~-tO-H----------
DATAoUT
DATA VALID
PREVIOUS DATA VALID
2693 drw05
TIMING WAVEFORM OF READ CYCLE NO_ 2, EITHER SIDE (1,3)
tACE
"~
.IV
tAOE
tHZ
~"
OE
.It'
~tHZ-
4--tLZ---"
~'......
DATA OUT
< < <:
DATA VALID
~
f-
tLZ
~tPu .....
Icc
~ 50%
lr
I",.
CURRENT Iss ________________.....
NOTES:
1. Rfilil is high for Read Cycles.
2. Device is continuously enabled, CE: = VIL.
3. Addresses valid prior to or coincident with CE: transition low.
4. OE: = VIL.
tpo
50%~",-----_
2693 drw 06
6.4
5
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K X S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE{7)
7032 x 20(2)
7032 x 25
7042 X 20(2)
Min. Max.
Symbol
Parameter
Write Cycle
Write Cycle Time(5)
twc
tEW
Chip Enable to End of Write
Address Valid to End of Write
tAW
Address Set-up Time
tAS
twp
Write Pulse Width(6)
Write Recovery Time
tWR
Data Valid to End of Write
tDW
Output High Z Time(1,4)
tHZ
Data Hold Time
tDH
Write Enabled to Output in High Z(1,4)
twz
Output Active From End of Write (1,4)
tow
20 ::::::"
15::::::::;.;
15::: ..: ....•..
-
0:.;:;:::;:'\15/:::::::: 0::::;::::\: 10 .:.::.:.:-i::;-:........:
8
::'.:.':::
0:::::::','
25
20
20
0
20
0
12
-
-
7032 x 35
7042 x 35
Min. Max.
7032 x 45(3)
7042 x 45(3)
Min. Max.
-
35
30
30
0
30
0
20
-
45
35
35
0
35
0
20
-
-
20
-
10
-
15
0
-
0
-
8
-
10
-
15
-
20
-
0
-
0
-
0
-
q(:::) ..
7042 x 25
Min. Max.
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTERISLA VE combination, twc = tBAA + twP.
6. Specified for OE' at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. "x" in part numbers indicates power rating (SA or LA).
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2693tbl09
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
NOTE:
1. This parameter is sampled and not 100% tested.
2693 tbl10
6.4
6
IDTI032SAlLA AND IDTI042SAlLA
CMOS DUAL-PORT RAM 16K (2K X S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (RIW CONTROLLED TIMING) (1,2,3,7)
~---------------------------------------------------------twc--------------------------------------------------~
ADDRESS
----l~.----------------------------twP (7) ---------------------------I~-tWR . .
RiW
DATA OUT
~-----------tDW----------~~I--------tDH ----------~~
DATA IN
2693 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING) (1,2,3,5)
twc
ADDRESS ~/
~,
",\/
4----tAS
/,
.
tAW
}
/V
tEW
tWR
..-
RiW
L
I.
r
DATA IN
tow
tOH
_I
J
~I
2693 drw 08
NOTES:
1.
2.
3.
4.
5.
6.
7.
RIW must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low RfJil.
twA is measured from the earlier of CE" or RIW going high to the end of the write cycle.
During this period, the I/O pins are in the output state and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
If OJ: is low during a RlW controlled write cycle, the write pulse width must be larger of twp or (twz + tDW) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tow. If OE is high during an RJW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.4
7
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
Symbol
Parameter
Busy Timing (For Master IDTI032 Only)
7032 x 20(1)
7042 x 20(1)
Min. Max.
tBM
BUSY Access Time to Address
-
tBDA
BUSY' Disable Time to Address
BUSY' Access Time to Chip Enable
- ::.:):.: :20'
- :L:{)w
- :(:)('20'
- .....:::':-:':':::{50
tBAC
tBDC
BUSY Disable Time to Chip Enable
tWDD
Write Pulse to Data Delay (3)
tDDD
Write Data Valid to Read Data Delay (3)
tAPS
Arbitration Priority Set-up Time (4)
tBDD
BUSY Disable to Valid Data (5)
Busy Input Timing (For Slave IDT7042 Only)
Write to BUSY Input (6)
tWB
Write Hold After BUSY (7)
tWH
tWDD
Write Pulse to Data Delay (9)
toDD
Write Data Valid to Read Data Delay(9)
20'
_.:.:.;.
:::\35
•...;.;:\~:;;:
5 .......
......;..::
-
-
5
-
5
-
-
-
0'
15
50'
35
-
:.:.;.;.
-f.}.
-
7032 x 35
7042 x 35
Min. Max.
25
20'
20'
20'
50
35
':::::::Note 5
0'::::::::....:'::
1~:
-
7032 x 25
7042 x 25
Min. Max.
Note 5
50
35
-
-
0'
20
-
7032 x 45(2)
7042 x 45(2)
Min. Max.
-
35
3D
3D
25
60'
45
-
-
Note 5
-
-
60'
45
-
5
0
20
-
-
Unit
35
35
3D
25
70
55
-
ns
Note 5
ns
-
70'
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2693 tbl11
NOTES:
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUS'Y (For Master IDT7032 only)".
4. To ensure that the earlier of the two ports wins.
5. tSOD is a calculated parameter and is the greater of 0, twoo-twp (actual) or tODD - tow (actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention ..
8. "x" in part numbers indicates power rating (SA or LA).
9. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With Port-to-Port Delay (For Slave IDT7042
Only)".
6.4
a
IDT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF REAO WITH BUSY (1,2,3)(FOR MASTER IOT7032 ONLY)
ADDRR
)(
)K
MATCH
twp
'\K
/
V
J tDH
f4-tDW
)K
DATAINR
)k
VALID
-+-tAPS(1)
ADDRL
MATCH
)
tBDA ......
\ LA
BUSYL
tBDD---""
tWDD
)K
DATAOUTL
VALID
tDDD (4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE at LO for the reading port.
2693 drw 09
TIMING WAVEFORM OF REAO WITH PORT-TO-PORT OELAy(1,2,3) (FOR SLAVE IOT7042 ONLY)
I
ADDRR
twc
>k
)K
MATCH
twp
'\K.
/V
tDW
DATAINR
)(
sK"
VALID
MATCH
ADDRL
tWDD
)K
DATAOUTL
VALID
tDDD
NOTES:
1. Assume BUSY input at HI for the writing port, and DE' at LO for the reading port.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
2693 drw 10
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (FOR SLAVE IOT7042 ONLY)
~fooiIf----twP---....t~
B::~_tWBJ_}tWH~
2693 drw 11
6.4
9
IDT7032SAllA AND IDT7042SAllA
CMOS DUAL-PORT RAM 16K (2K x 8-BIn
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
(FOR MASTER IDT7032 ONLY)
eEL VALID FIRST:
ADDR ~
ADDRESSES MATCH
~
LANDR~----------------------------------------------------~
:::-'i!APS~_It______________
~
___t_BA_C=1
I--tBDC-------j •...--__________
J
~
BUSYR
__
2693 drw 12
CER VALID FIRST:
ADDR ~
ADDRESSES MATCH
~
LANDR~--------------------------------------------~
::_'itAPs~_It--__________
~
__tB_A_C=1
I--tBDC-------j ....--__________
J
1\
BUSYL
__
2693 drw 13
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION (1)
(FOR MASTER IDT7032 ONLY)
LEFT ADDRESS VALID FIRST:
14-----tRC OR
twc------~
ADDRESSES MATCH
ADDRL
ADDRESSES DO NOT MATCH
ADDRR
tBAA9______:~~~~~t_BD_A~~~~~1~...--________
BUSYR
2693 drw 14
RIGHT ADDRESS VALID FIRST:
14-----tRC OR
AD DR R
--~
twc-------~
~---------------~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR L
BUSYL
NOTE:
1. CE:L
tBAA9______:~~~~~t_BD_A~~~~~1~,--_______
2693 drw 15
= CE:R = VIL
6.4
10
ID17032SAlLA AND ID17042SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RIGHT
RIW
IDT7032
MASTER
BUSY
AAA
Y'I'Y
RiW
BUSY
+5V
+5V
-
RIW
AAA
YYY
-
RIW
IDT7042
SLAVE(1)
BUSY
BUSY
2693 drw 16
NOTE:
1. No arbitration in IOT7042 (SLAVE). BUSY-IN inhibits write in IOT7042 (SLAVE).
FUNCTIONAL DESCRIPTION
The IDT7032142 provides two ports with separate control,
address, and 1/0 pins that permit independent access for
reads or writes to any locations in memory. These devices
have an automatic power down feature controlled by CEo The
CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output
Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. Non-contention READI
WRITE conditions are illustrated in Table 1.
ARBITRATION LOGIC
FUNCTIONAL DESCRIPTION
The arbitration logic will resolve an address match or a chip
enable match down to 5ns minimum and determine which port
has access. In all cases, an active BUSY flag will be set for the
delayed port.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location.
When this situation occurs, on-chip arbitration logic will determine which port has access and sets the delayed port's BUSY
flag. BUSY is set at speeds that permit the processor to hold
the operation and its respective address data. It is important
to note that the operation is invalid for the port that has BUSY
set LOW. The delayed port will have access when 130SY goes
inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the
on-chip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before CE, on-chip control logic arbitrates between GEL
6.4
and CERfor access; or (2) if the CEs are low before an address
match, on-chip control logic arbitrates between the left and
right addresses for access (refer to Table II). In either mode of
arbitration, the delayed port's BUSY flag is set and will reset
when the port granted access completes its operation.
DATA BUS WIDTH EXPANSION
MASTER/SLAVE DESCRIPTION
Expanding the data bus width to sixteen-or-more-bits in a
dual-port RAM system implies that several chips will be active
at the same time. If each chip includes a hardware arbitrator, •
and the addresses for each chip arrive at the same time, it is
•
possible that one will activate its BUSYL while another acitivates its BUSYR signal. Both sides are now busy and the
CPUs will wait indefinitely for their port to become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTERISLAVE approach where only one arbitrator, in the
MASTER, is used. The SLAVE has BUSY inputs which allow
an interface to the MASTER with no external components and
with a speed advantage over other systems.
When expanding dual-port RAMS inwidth, the writing ofthe
SLAVE RAMS must be delayed, until after the BUSY input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse must
extend a hold time past BUSY to ensure that a write cycle
takes place after the contention is resolved. This timing is
inherent in all dual-port memory systems where more than on
chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to
BUSY from the MASTER.
11
1DT7032SAlLA AND IDT7042SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
REAOIWRITE CONTROL (4)
Left Or Right Port (1)
RIW Ci:
X
H
o"E"
X
X
H
X
L
H
H
L
L
L
X
L
H
Function
00-7
Port Disabled and in Power
Down Mode 1582 or 1584
Z
GER = GEL = H, Power Down
Mode, 1581 or 1583
DATAIN Data on Port Written into Memory(2)
DATAoUT Data in Memory Output on Port(3)
High Impedance Outputs
Z
Z
2693tbl12
NOTES:
1. AOl- Al0l;t AOR - Al0R
2. If BOSV = L, data is not written
3. If BOSV = L, data may not be valid, see twoo and tODD timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
TABLE 11- ARBITRATION (1,2)
Flags (2)
Left Port
Right Port
eEL
eER
AOR-A10R
AOL - A10L
H
H
X
X
L
Any
X
H
H
X
L
Any
':f.AOL - A10L
L
':f.AOR - A10R
L
Address Arbitration With CE Low Before Address Match
LV5R
l.
LV5R
L
L
RV5L
L
RV5L
L
Same
L
Same
Same
L
Same
L
CE Arbitration With Address Match Before Ci:
LL5R
LL5R
= AOR - A10R
RL5L
RL5L
=AOR - A10R
LW5R
=AOR - A10R
, , LW5R
LW5R
LW5R
= AOA - A10R
= AOL - A10L
= AOL - A10L
= AOL - A10L
= AOL - A10L
Function
BUSVL
H
H
H
H
BUSYR
H
H
H
H
H
L
H
L
L
H
L
H
L-PortWins
R-PortWins
Arbitration Resolved
Arbitration Resolved
H
L
H
L
L
H
L
H
L-PortWins
R-PortWins
Arbitration Resolved
Arbitration Resolved
No Contention
No Contention
No Contention
No Contention
2693tbl13
NOTES:
1. X = DON'T CARE, L = LOW, H = HIGH
2. LV5R = Left Address Valid,;:: 5ns before right address.
RV5L = Right Address Valid;:: 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW;:: 5ns before Right CE.
RL5L = Right CE = LOW;:: 5ns before Left CE.
LW5R = Left and Right CE = LOW within 5ns of each other.
6.4
12
(~J
IDT71321 SA/LA
IDT71421 SA/LA
CMOS DUAL-PORT RAM
16K (2K x 8-BIT)
WITH INTERRUPTS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 25/30/35/45/55170ns (max.)
-Commercial: 20/25/30/35/45/55ns (max.)
• Low-power operation
-IDT71321 /IDT71421 SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT71321/421 LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• Two INT flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to 16or-mare-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
• BUSY output flag on IDT71321; BUSY input on
IDT71421
• Fully asynchronous operation from either port
• Battery backup operation -2V data retention
• TTL-compatible, single 5V ±1 0% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT71321/IDT71421 are high-speed 2K x 8 dualport static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit dual-port RAM or as a "MASTER"
dual-port RAM together with the IDT71421 "SLAVE" dualport in 16-bit-or-more word width systems. Using the IDT
MASTERISLA VE dual-port RAM approach in 16-or-morebit memory system applications results in full speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CEMOSTM high-performance technology, these devices typically operate on only 325mW of
power at maximum access times as fast as 20ns. Lowpower (LA) versions offer battery backup data retention capability, with each dual-port typically consuming 200JlW from
a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin
LCCs and PLCCs. Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class
B.
FUNCTIONAL BLOCK DIAGRAM
RlWl
RiWR
CEl
CER
OEl
A10l
All
VOOl
I---;=~+- AlaR
I/07l
I/07R
A7R
I/OOR
BUSYl(ll o.,-~====:;--:.
L----;====~~o() BUSYR(ll
ASl
,..-----'0.--...,.
ASR
AOl
__.z------._
AlaR
ARBITRATION
:
AOR
AND INTERRUPT AOR
LOGIC
CER
RNVl--~~~-~~- RlWR
L-=========:::::'_INTR(2l
INTl(2l_==========-..J
NOTES:
1. 10171321 (MASTER): BUSY is open output and requires pullup resistor. 10171421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
2691 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1:)1992 Integrated Device Technology. Inc.
6.5
APRIL 1992
DSC·1031/3
IDTI1321SAlLA AND IDTI1421SAlLA
CMOS DUAL-PORT RAM 16K (2K X a-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
A1L
:87
A2L
:9
6 5 4
3
2
5251 50 49 481~::
L J
1
OER
45::
AOR
A3L
:10
Am
A4L
:11
A2R
A5L
:12
ASL
:13
A7L
:14
40::
A5R
ASL
:15
39::
ASR
A9L
:16
38::
A7R
37::
36::
ASR
1I00L
1/01L
A3R
J52-1
&
L52-2
:17
LCC/PLCC
:18
TOP VIEW
1/02L
:19
1/03L
:22~
A4R
A9R
NC
35::
4
222324252627282930 31 32 ?3 ::
1/07R
rl rl r l rl rl rl rl rl rl rl rl rl rl
2691 drw 02
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
TA
Operating
Temperature
a to +70
-55to+125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65to+135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
Military
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V±10%
O°C to +70°C
OV
5.0V
± 10%
2691 tbl 02
RECOMMENDED
DC OPERATING CONDITIONS
Parameter
Min_
Typ_
Max_
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
a
a
V
VIH
Input High Voltage
2.2
6.0(2)
V
VIL
Input Low Voltaqe
-0.5(1)
Symbol
2691 tblOl
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.SV.
-
Unit
0.8
V
2691 tbl 03
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + O.SV.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = S.OV± 10%)
Symbol
Parameter
IDT71321SA
IDT71421SA
Max.
Min.
Test Conditions
IDT71321LA
IDT71421LA
Min.
Max.
Unit
IILlI
Input Leakage
Current(1)
Vee = 5.5V, VIN
= OV to Vee
-
10
-
5
JlA
IILol
Output Leakage
Current
CE = VIH, VOUT
= OV to Vee
-
10
-
5
JlA
VOL
Output Low Voltage
(1100-1107)
IOL
= 4mA
-
0.4
-
0.4
V
VOL
Open Drain Output Low
Voltaqe (BUSY/INn
IOL
= 16mA
-
0.5
-
0.5
V
VOH
Output High Voltaqe
IOH
= -4mA
2.4
-
2.4
-
1. At Vcc$2.0V Input leakages are undefined.
V
2691 tbl04
6.5
2
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K X 8-BI1) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 6) (VCC = 5 OV +
- 10%)
71321x20(2)
71421 x20 (2)
Symbol
Icc
1581
1582
1583
1584
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current
(Both Ports - TIL
Level Inputs)
Standby Current
(One Port -TIL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port -All
CMOS Level Inputs)
Test Conditions
CE = Vil
Outputs Open
f = fMAX(4)
CEl and CER ;::: VIH
f = fMAX(4)
SA
Mil.
LA
Com'l.
Both Ports CEl and
CER ;::: Vee -O.2V
VIN ;::: Vee -0.2V or
VIN:;; 0.2V,f = 0(5)
One Port CEl or
CER ;::: Vee -0.2V
VIN;::: Vee -0.2V or
VIN:;; 0.2V
Active Port Outputs
Open, f =fMAX(4)
SA
LA
SA
Mil.
Com'!.
CEl or CER ;::: VIH
Active Port Outputs
Open, f =fMAX(4)
Typ.
Version
SA
30·:
30:: ;::@m?
:~
-
-
LA
SA
LA
SA
Mil.
LA
Com'!.
SA
LA
SA
Mil.
LA
Com'!.
::;::-
::::!!!::.::.::~~~
125
125
=(
)K
i--tHZ(6) -
/~
+-- tHZ (6) ___
tAW
W~
//
tWp(7)
i4----tAS
RiW
tWR --.
/V
"t\..
f4---twz (6)
DATA OUT
(4)
tow
lr
'I
tow
1/
DATA IN
tOH
(4)
)-
~
I
1
2691 drw07
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING (1,2,3,5)
ADDRESS
twc
=>(
)K
tAW
4-tAS
'}
/V
tEW
tWR
~
RiW
L
DATA IN
II
tow
tDH
.J
J
1
2691 drw OS
NOTES:
1. RiW must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a low CE and a low RiW.
3. twR is measured from the earlier of CE or RiW going high to the end of the write cycle.
4. Durin9..!bis period, the VO pins are in the output state and input s!9..nals must not be applied.
5. If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. If OE is low during a RiW controlled write cycle, the write pulse width must be larger of twp or (twz + tow) to allow the lID drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified twP.
6.5
7
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K X 8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
71321x20 (1)
71421x20 (1)
Min. Max.
Symbol
Parameter
Busy Timing (For Master IDT71321 Only)
tBAA
BUSY Access Time to Address
tBDA
BUSY Disable Time to Address
tBAC
tBDC
BUSY Access Time to Chip Enable
tWDD
tDDD
tAPS
Write Data Valid to Read Data Delay (3)
Arbitration Priority Set-up Time(4)
tBDD
BUSY Disable to Valid Data(5)
tWDD
Write Hold After BUSY (7)
Write Pulse to Data Delay (9)
tDDD
Write Data Valid to Read Data Delay (9)
-
25/30
20
-\/\:: 20
_::()};: 20
-
20/25
-=::;::....
..:.:....:.: ..
-::::::/?
50
-:::;:;:::;:;:;: 35
5:;::::-::·····
-
.........
~::::::::Note 5
Busy Timing (For Slave IDT71421 Only)
Write to BUSY Input (6)
tWB
tWH
20
-::'"
BUSY Disable Time to Chip Enable
Write Pulse to Data Delay (3)
71321x25/30
71421x25/30
Min. Max.
5/5
-
20/25
20/25
50/50
35/35
Note 5
71321x35
71421x35
Min. Max.
5
-
Unit
35
ns
30
ns
30
ns
ns
ns
25
60
35
ns
-
ns
ns
Note 5
::::::::::/:
o\i:·? -
010
-
12{::t::: -
15/20
-
-/\::
_:.:.:.:.:.;.;.;
50
35
-
50/50
35/35
0
20
-
-
60
35
ns
ns
ns
ns
2691 tbl12
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGERANGE(8) (CONTINUED)
71321x45
71421x45
Min. Max.
Parameter
Symbol
Busy Timing (For Master IDT71321 Only)
BUSY Access Time to Address
tBAA
tBDA
BUSY Disable Time to Address
tBAC
tBDC
BUSY Access Time to Chip Enable
BUSY Disable Time to Chip Enable
Write Pulse to Data Delay (3)
-
Write Data Valid to Read Data Delay (3)
-
tWDD
tDDD
tAPS
Arbitration Priority Set-up Time(4)
tBDD
BUSY Disable to Valid Data(5)
5
-
Busy Timing (For Slave IDT71421 Only)
Write to BUSY Input(6)
0
tWB
tWH
tWDD
Write Hold After BUSy(7)
Write Pulse to Data Delay(9)
tDDD
Write Data Valid to Read Data Delay(9)
20
-
71321x55
71421x55
Min. Max.
30
-
35
25
-
30
70
45
-
80
55
35
35
Note 5
70
45
5
0
20
-
45
40
NoteS
80
55
71321x70(2)
71421x70(2)
Min. Max.
5
0
20
-
Unit
45
ns
40
ns
35
ns
30
ns
90
70
ns
ns
-
ns
Note 5
ns
-
ns
90
ns
ns
70
ns
NOTES:
2691 tbl13
1. O°C 10 +70°C temperalure range only.
2. -55°C 10 +125°C temperature range only.
3. Port-Io-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (For Master 10T71321 only)".
4. To ensure that the earlier of the two ports wins.
.
5. tBOO is a calculated parameter and is the greater of 0, twoo-twp (actual) or to~D - tow (actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
S. "x· in part numbers indicates power rating (SA or LA).
9. Port-Io-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With Port-to-Port Delay (For Slave 10T71421
Only)".
6.5
8
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-811) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (1,2,3) (FOR MASTER IOT71321)
twc
ADDRR
)(
)K
MATCH
twp
RNJR
'\,
/V
tDW
)K
DATAINR
0H
>K
VALID
-tAPS
MATCH
ADDRL
)
'"
tBDD-
tBDA-
-J"
tWDD
)K.
DATAOUTL
VALID
tDDD(4)
2691 drw 09
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
4. DE at LO for the reading port.
TIMING WAVEFORM OF READ WITH PORT-TO-PORT OELAy(1,2,3) (FOR SLAVE IOT71421 ONLY)
I
ADDRR
twc
>K
)(
MATCH
twp
~'\.
/
/
tDW
)K
DATAINR
VALID
)KH
MATCH
ADDRL
tWDD
) ( VALID
DATAOUTL
tDDD
2691 drw 10
NOTES:
1. Assume BUSY input at HI for the writing port, and DE at LO for the reading port.
2. Write Cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
TIMING WAVEFORM OF WRITE WITH BUSY (FOR SLAVE IOT71421)
twp
-=-{ i
IWB
}IWH{
BUSY
2691 drw 11
6.5
9
IDT71321SAllA AND IDT71421SAllA
CMOS DUAL-PORT RAM 16K (2K X S-BI1) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
(FOR MASTER IOT71321 ONLY)
CEl VALID FIRST:
~
ADDR==><
LAND R
.
________________~X=
ADDRESSES MATCH
~IAPS~
CEl
CER
tBAcq h J
tBOO
BUSYR
CER VALID FIRST:
ADDR==><~
LAND R
.
_________________X=
ADDRESSES MATCH
~IAPS~
CER
CEl
2691 drw 12
BUSYl
tBAcq htBDCJ
2691 drw 13
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION
(FOR MASTER IDT71321 ONLY)(1)
LEFT ADDRESS VALID FIRST:
1+------tRC OR
ADDRl
twc----~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDRR
tBM9"--____~~~~~~t_BD_A~~~~~}~________
BUSYR
2691 drw 14
RIGHT ADDRESS VALID FIRST:
14------tRC OR
twc----~
)K' - - -ADDRESSES
MATCH
)K ADDRESSES DO NOT MATCH
----------' '-------------'
ADDRR
---'
tAPs~
ADDRl
r-----------+--------------~
)(
'------------+--------------~
-------'
BUSYl
-tBAA9"--____!,..·_-_-_-_-_~_t_BD_A~~~~~}~
2691 drw 15
NOTE:
1. eEL
= eER = Vil
6.5
10
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-Bll) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
71321 SAlLA20(1) 71321 S/IJLA25/30
71421 SAlLA20(1) 71421 SAlLA25/30
Max.
Min.
Max.
Min.
Symbol
Parameter
Interrupt Timing
Address Set-up Time
tAS
Write Recovery Time
tWR
tiNS
tlNR
interrupt Set Time
interrupt Reset Time
a
a
-
a
a
-
20
20
-
-
71321SAlLA35
71421SAlLA35
Min.
Max.
a
a
-
ns
ns
-
35
35
ns
ns
25/30
25/30
Unit
2691 tbl14
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (CONTINUED)
71321SAlLA45
71421SAlLA45
Max.
Min.
Symbol
Parameter
Interrupt Timing
Address Set-up Time
tAS
tWR
Write Recovery Time
interrupt Set Time
tiNS
tlNR
interrupt Reset Time
71321SAlLA70(2)
71421SAlLA70(2)
Min.
Max.
71321 SAlLA55
71421SAlLA55
Min.
Max.
a
a
-
a
a
-
0
0
-
40
40
-
45
45
-
Unit
-
ns
ns
50 '
50
ns
ns
2691 tbl15
NOTES:
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
TIMING WAVEFORM OF INTERRUPT MODE (1,2)
LEFT SIDE SETS INTR:
twc
ADDRL
RiWL
iNTR
III
WRiTE 7FF
IINst
2691 drw 16
RIGHT SIDE CLEARS INTR:
~-------------tRC--------------~
ADDRR
READ 7FF
RiWR
OER
,SSSSSSSSSSSSSSSL
~
/
l==tINR-1 _ _ _ _ _ _ __
INTR
~
'
2691 drw 17
NOTES:
1. CEl = CER = Vil
2. INTl and INTR are reset (HIGH) during power up.
6.5
11
1DT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K X S-BI1) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT MODE (1, 2)
RIGHT SIDE SETS INTL:
~----------twc----------~
ADDRR
WRITE 7FE
RIWR
INTL
t_IN_S~~
_____________
___________________________________________________
2691 drw 18
LEFT SIDE CLEARS INTL:
14---------------tRC ---------------.t
ADDRL
GEL
_
READ 7FE
/
"SSSSSSSSSSSSSSS'L ----1 ._____________
_
--'::::::IINR
J
INTL
----------------------------------------------
2691 drw 19
NOTES:
1. CEl = CER = VIL
2. INTR and INTL are reset (HIGH) during power up.
16-81T MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RIGHT
RlW
RlW
IDT71321
MASTER
BUSY
-JWv.
BUSY
+5V
RiW
RlW
+5V
IDT714f~
SLAVE
AAA
YYV
RiW
1
BUSY
BUSY
2691 drw20
NOTE:
1. No arbitration in IDT71421 (SLAVE). BUSY-IN inhibits write in IDT71421 (SLAVE).
6.5
12
1DT71321SAllA AND IDT71421SAllA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Contention occurs when both left and right ports are active and both addresses match. When this situation occurs,
the on-chip arbitration logic determines access. Two modes
of arbitration ar~ovided: (1) if the addresses match and
are valid before CE, on-chip controlloJ!i.2 arbitrates between
CEl and CER for access; or (2) if the CEs are low before an
address match, on-chip control logic arbitrates between the
left and right addresses for access (refer to Table III). In either mode of arbitration, the delayed port's BUSY flag is set
and will reset when the port granted access completes its
operation.
FUNCTIONAL DESCRIPTION
The IOT71321/IDT71421 provides two ports with separate control, address, and 110 pins that permit independent
access for reads or writes to any locations in memory. These
devices have an automatic power-down feature controlled
by CEo The CE controls on-chip power-down circuitry that
permits the re~ctive port to go into a standby mode when
not selected (CE high). When a port is enabled, access to
the entire memory array ~ermitted. Each port has its own
Output Enable control (DE). In the read mode, the port's
DE turns on the output drivers when set LOW. Non-contention READ/WRITE conditions are illustrated in Table 1.
The interrupt flag (INT) permits communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INTl)is
set when the right port writes to memory location 7FE (HEX).
The left port clears the interrupt by reading address location
7FE. Likewise, the right port interrupt flag (INTR) is set
when the left port writes to memory location 7FF (HEX) and
to clear the interrupt flag (INTR), the right port must read
the memory location 7FF. The message (8 bits) at 7FE or
7FF is user-defined. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes
but as part of the random access memory. Refer to Table II
for the interrupt operation.
DATA BUS WIDTH EXPANSION
MASTER/SLAVE DESCRIPTION
Expanding the data bus width to sixteen-or-more-bits in
a dual-port RAM system implies that several chips will be
active at the same time. If each chip includes a hardware
arbitrator, and the addresses for each chip arrive at the
same time, it is possible that one will activate its BUSYl
while another acitivates its BUSYR signal. Both sides are
now busy and the CPUs will wait indefinitely for their port to
become free.
To avoid the "Busy Lock-Out" problem, lOT has developed a MASTER/SLAVE approach where only one arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs
which allow an interface to the MASTER with no external
components and with a speed advantage over other systems.
When expanding dual-port RAMS in width, the writing of
the SLAVE RAMs must be delayed, until after the BUSY
input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a contention situation. Conversely, the
write pulse must extend a hold time past BUSY to ensure
that a write cycle takes place after the contention is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due
to BUSY from the MASTER.
ARBITRATION LOGIC
FUNCTIONAL DESCRIPTION
The arbitration logic will resolve an address match or a
chip enable match down to 5ns minimum and determine
which port has access. In all cases, an active BUSY flag
will be set for the delayed port.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location.
When this situation occurs, on-chip arbitration logic will determine which port has access and sets the delayed port's
BUSY flag. BUSY is set at speeds that permit the processor to hold the operation and its respective address and
data. It is important to note that the operation is invalid for
the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.
6.5
13
all
•
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READIWRITE CONTROL (4)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Left Or Right Port(1)
RfW
CE
OE
00-7
X
H
X
Z
X·
H
X
Function
Port Disabled and in Power
Down Mode IS82 or IS84
Z
CER = CEL = H, Power Down
Mode, IS81 or IS83
DATAIN Data on Port Written into Memory(2)
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
L
L
X
H
L
L
H
L
H
2691
NOTES:
1. AOL-Al0L -:t AOR-Al0R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see twoo and tBOO timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
2691 Ibl 17
NOTE:
1. This parameter is determined by device characterization but is not 100%
tested.
tbl16
TABLE II-INTERRUPT FLAG(1,4)
Left Port
Right Port
OEl
AOl-A10l
INTl
RfWR
CER
OER
AOl-A10R
7FF
X
X
X
X
INTR
L(2)
X
X
X
X
X
X
X
X
X
X
7FF
H(3)
L
L
L
L
L(3)
7FE
L
L
7FE
H(2)
X
X
X
X
X
X
RlWl
L
CEl
L
X
X
X
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
NOTES:
1. Assumes BUSYL = BUSYR = H.
2. If BUSYL = L, then NC.
3. If BUSYR = L, then NC.
4. H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE.
2691 tbllS
TABLE III - ARBITRATION (1, 2)
Left Port
Right Port
Flags
eEL
AOL-A10L
CER
AOR-Al0R
BUSYL
BUSYR
H
L
X
H
No Contention
H
H
H
H
Any
X
X
H
No Contention
H
X
L
Any
H
H
No Contention
H
H
No Contention
H
L
* AOR-Al0R
L
* AOL-A10L
Address Arbitration With CE Low Before Address Match
LV5R
L
L
LV5R
Function
RV5L
L
RV5L
L
L
H
L-PortWins
L
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
L-PortWins
R-PortWins
CE Arbitration With Address Match Before CE
LL5R
= AOR-Al0R
LL5R
R-PortWins
= AOl-Al0l
H
L
RL5L
= AOL-Al0L
L
H
= AOR-Al0R
LW5R
= AOL-Al0L
H
L
Arbitration Resolved
= AOR-Al0R
LW5R
= AOL-Al0L
L
H
Arbitration Resolved
RL5L
LW5R
= AOR-Al0R
LW5R
NOTES:
1. INT Flags Don't Care.
2. X = DON'T CARE, L = LOW, H = HIGH
LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW ~ 5ns before Right CE.
RL5L = Right CE = LOW ~ 5ns before Left CEo
LW5R = Left and Right CE = LOW within 5ns of each other.
2691 tbl19
6.5
14
t;)
HIGH-SPEED
2K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT7012
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
- IDT7012S
Active: 400mW (typ.)
Standby: 7mW (typ.)
- IDT7012L
Active: 400mW (typ.)
Standby: 2mW (typ.)
• Fully asychronous operation from either port
• Each port has a 9-bit wide data path. The 9th bit could be
used as the parity bit
• Battery backup operation - 2V data retention
• TTL compatible, single 5V (±10%) power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is
avalable, tested to military electrical specifications
The IDT7012 is a high-speed 2K x 9 dual-port static RAM
designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to
be able to externally arbitrate or withstand contention when
both sides simultaneously access the same dual-port
location.
The IDT7012 provides two independent ports with
separate control, address, and I/O pins that permit
independent, asychronous access for reads or writes to any
location in memory. It is the user's responsibility to ensure
data integrity when simultaneously accessing the same
memory location from both ports. An automatic power-down
feature, controlled by CE, permits the on-chip circuitry of each
port to enter a very low standby power mode.
The IDT7012 utilizes a 9-bit wide data path to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking.
Fabricated using IDT's CEMOSTM high-performance
technology, these devices typically operate on only 400mWof
power at maximum access times as fast as 25ns. Low-power
(L) versions offer battery backup data retention capability, with
each port typically consuming 200llW from a 2V battery.
The IDT7012 is packaged in 48-pin sidebrazed or plastic
DIPs, 48-pin LCCs and 48-pin flatpacks. The military devices •
are processed 100% in compliance to the test methods of
MIL-STD-883, Method 5004.
FUNCTIONAL BLOCK DIAGRAM
pjijih
J
CEl
I
I
]
A7L
1I0al
I/00l
(~
,~
-
:=
--
1
DEL
A10l
,
1
w
··
COL
SEl
·
r--
f4COLUMN ~
liD
r--
ROW
SELECT
~
}
-
AOl -'--~
RlWR
I
CER
\..
··
ASl -.--~
I
J
-----"
fY-l r--V
~
A
I\..
"'j
"
v
COLUMN
liD
U
r--
0
0
.
A10R
A7R
I/0aR
110 OR
r--
-
7-
MEMORY
ARRAY
COL
SEl
OER
A
"'j
"
v
1 + - - - .ROW
0
SELECT 1 + - - _
-
ASR
AOR
2653 drw 01
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
6.6
APRIL 1992
05C·l04912
1DT7012 HIGH SPEED 2K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CEl
A9l
OEl
INDEX
CER
RNVR
A10R
A9R
OER
AOR
A1R
A2R
A3R
A4R
ASR
S
A2l
A3l
A4l
ASl
GND
A6l
A7l
Aal
1I00l
I/01l
I/02l
I/03l
I/04l
1I0Sl
I/06l
I/07l
I/Oal
AOR
A1R
A2R
A3R
A4R
ASR
ASR
A7R
Vee
ABR
I/OBR
I/OlR
I/OSR
A6R
A7R
AaR
1I0aR
I/07R
I/06R
1I0SR
I/04R
I/03R
I/02R
I/01R
I/OOR
2653 drw 02
DIP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
TA
TSIAS
TSTG
lOUT
Rating
Commercial
Military
Unit
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
-0.5 to +7.0
-0.5 to +7.0
V
Storage
Temperature
DC Output
Current
Oto +70
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
50
50
mA
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
Grade
Military
Commercial
Symbol
CIN
COUT
(TA
Ambient Temperature
GND
Vee
-55°C to + 125°C
O°C to +70°C
OV
OV
5.0V± 10%
5.0V ± 10%
2653tbl02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Vee
GND
NOTE:
2653 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions
for extended periods may affect reliabilty.
2. VTERM must not exceed Vee + o.sv.
CAPACITANCE
2653 drw 03
LCC/FLATPACK
TOP VIEW
Parameter
Supply Voltage
Supply Voltage
Min.
Typ.
Max.
Unit
4.5
0
5
0
5.5
0.0
V
V
V
VIH
Input HiQh VotaQ9
2.2
-
6.0(2)
VIL
Input Low Voltage
-0.5(1)
-
0.8
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
V
2653tbl03
= +25°C, f = 1.0MHz)
Parameterll }
Condition
VIN = OV
Max.
Unit
Input Capacitance
11
pF
Output Capacitance
VOUT= OV
11
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2653 tbl13
6.6
2
1017012 HIGH SPEED 2K
x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc
Symbol
Parameter
= 5.0V± 10%)
70125
Min. Max.
Test Condition
7012L
Min. Max. Unit
Ilul
Input Leakage Current(7)
Vee =5.5V. VIN = OV to Vee
-
10
~
Output Leakage Current
CE = VIH.
-
5
~
OutQut Low Voltage
Output High Voltage
IOl=4mA
IOH =-4mA
-
10
0.4
-
5
lilol
VOL
VOH
0.4
2.4
-
2.4
-
V
V
VOUT = OV to Vee
2653 Ibl 04
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE{1,6) (Vcc = 5.0V ± 10%)
Symbol
Parameter
Dynamic
lee
Operating
Current (Both
Ports Activel
1881
Standby
Current (Both
Ports-TTL
Level Inputs)
1882
Standby
Current (One
Port-TTL
Level Inputs)
1883
1884
Test
Condition
CE:::;Vll
Outputs Open
f = fMAX(4)
GEL and
CER ~VIH
f = fMAX(4)
CElor
GER~VIH
Active Port
Outputs Open.
f = fMAx(4)
Full Standby
Current
(Both Ports-All
CMOS Level Inputs)
Both Ports GEL and
CER;:::: Vee- 0.2V
VIN ;:::: Vee - 0.2V
or VIN:::; 0.2V. f = 0(5)
Full Standby
Current
(One Port-All
CMOS Level Inputs)
One PortCEL
or CER ;:::: Vee - 0.2V.
VIN ;:::: Vee - 0.2V or
VIN:::; 0.2V
Active Port Outputs
Open. f = fMAX(4)
7012
x 25(2)
Version Typ. Max.
S
Mil.
L
Coml S 125 260
L 125 220
Mil.
S
L
65
Coml S 30
30
45
L
S
Mil.
L
80 175
Coml S
L
80 145
-
-
Mil.
S
L
Coml S
L
S
Mil.
L
Coml S
L
NOTES:
-
-
1.0
0.2
15
5
-
-
70
70
170
140
7012
Max.
290
230
250
210
80
60
65
45
185
150
165
135
Typ.
125
125
125
125
30
30
30
30
80
80
80
80
Max.
285
225
245
205
80
60
65
45
180
145
160
130
Typ.
125
125
125
125
30
30
30
30
80
80
80
80
Max.
280
220
240
200
80
60
65
45
175
140
155
125
Typ. Max. Unit
125 275 rnA
125 215
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
1.0
0.2
1.0
0.2
1.0
0.2
70
70
70
70
175
140
160
130
70
70
70
70
30
10
15
5
170
135
155
125
70
70
70
70
7012
x 35
7012
x 45
x 70(3)
x 55
Typ.
125
125
125
125
30
30
30
30
80
80
80
80
7012
-
-
30
30
80
60
-
-
80
80
170
135
-
-
30
10
15
5
1.0
0.2
30
10
-
-
165
130
150
120
70
70
160
125
-
-
rnA
rnA
rnA
rnA
2653 Ibl 05
1. ·x· in part numbers indicates power rating (S or L).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. Atf = fMAX. address and control lines (exceptOutput Enable) are cycling at the maximum frequency read cycle of 1lIRe. and using "AC TEST CONDITIONS"
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc=5V. TA=+25°C for Typ.
7. At Vccs;,2.0V input leakages are undefined.
6.6
3
ID17012 HIGH SPEED 2K
x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version Only)
Symbol
Test Condition
Parameter
VOR
leeOR
Vee for Data Retention
Data Retention Current
teoR(3)
tR(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
I Mil.
Vee = 2.0V, C"E;:: Vee - 0.2V
I Com'l.
VIN;:: Vee - 0.2V or VIN $; 0.2V
Min.
7012L
Typ.(1)
Max.
2
-
-
-
100
100
0
tRe (2)
-
-
NOTES:
1. Vce = 2V, TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
Unit
V
4000
1500
~
~
-
ns
ns
2653tbl06
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VOR ;:: 2V
Vee
\
VOR
I
~----------------------~.
tR~
V»0\\\\\\\\\\\\
2653 drw 04
AC TEST CONDITIONS
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2653 tbl 07
5V
12500
1670
DATAoUT - - + - -....
DATAOUT~ 1.73V
1
7750
30
5pF*
pF'
2653 drw 06
2653 drw 05
• Including
~cope
and jig.
Figure 2. Output Load
(for tHZ, tLZ, twz and tow)
Figure 1. Equivalent Output Load
6.6
4
ID17012 HIGH SPEED 2K
x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7012
Symbol
Read Cycle
Parameter
x 25(2)
7012
x 35
7012
x 45
7012
x 55
7012
x 70(3)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC
Read Cycle Time
25
-
35
-
45
-
55
-
70
-
ns
tM
Address Access Time
25
-
45
-
55
ns
35
-
45
55
tAOE
Output Enable Access Time
25
30
tOH
Output Hold From Address Change
a
-
-
ns
tLZ
Output Low Z Time(1,4j
-
a
-
ns
tHZ
Output High Z Time«(1,4)
-
10
15
-
20
30
-
35
ns
tpu
Chip Enable to Power-Up Time(4)
a
-
a
-
a
-
-
a
-
ns
tPD
Chip Disable to Power-Down Time(4)
-
50
-
50
-
50
a
a
a
-
a
70
Chip Enable Access Time
a
a
-
35
tACE
a
a
50
-
50
25
12
-
-
-
a
NOTES:
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1 and 2).
2. O°C to +70°C temperature range only.
3. -55°C to +12SoC temperature range only.
4. This parameter guaranteed but not tested.
5. "x· in part numbers indicates power rating (S or L).
35
70
ns
40
ns
ns
2653 tbl 08
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1, 2,4)
==t= tOH~_
~
ADDRESS
DATA OUT
tRC----------------~~
PREVIOUS DATA
LtOHi
V~
~Ir"K"":lIl""'1l'"""K'""'lIr""'Jl[-X-K""'J!~-x-Jr""'J'
DATA VALID
2653 drw 09
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1, 3)
tACE
~["
]'tAOE
-
tHZ___..
~["
tHZ
tLZ
+'
,,'+\\-'[""
.
DATAoUT
~
tLZ
:4-
VALID DATA~:
-tPD
CURRE~~-_================~=~-50-o/c-O---------------------------5~
~----------------+- tpu
ISS...t
2653 drw 10
NOTES:
1. Rflil is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to coincident with CE transition low.
4. DE' = VIL.
6.6
5
IDT7012 HIGH SPEED 2K
x 9 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
7012
Symbol
Write Cycle
Write Cycle Time
twc
Parameter
x 25(2)
-
25
20
20
tEW
Chip Enable to End of Write
tAW
Address Valid to End of Write
tAS
twp
Address Set-up Time
Write Pulse Width (5)
a
-
20
tWR
Write Recovery Time
a
tow
Data Valid to End of Write
Output High Z Timel1 ,4)
12
tHZ
tOH
7012
x 35
7012
x 45
7012
x 55
7012
x 70(3)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
a
-
35
30
30
45
35
35
a
-
-
30
-
35
-
a
-
a
10
10
20
-
a
-
20
-
-
55
40
40
a
40
a
70
50
50
a
50
a
-
ns
ns
ns
ns
ns
ns
15
20
-
20
-
30
30
-
a
-
a
-
a
-
a
-
-
15
60
45
-
20
-
30
-
35
a
-
a
-
a
-
-
70
55
-
80
65
-
95
80
twz
tow
Data Hold Time
Write Enabled to Output in High ZI1,4)
Output Active From End of Write(1,4)
a
-
a
twoo
Write Pulse to Data Delay
-
-
tODD
Write Data Valid to Read Data Delay
-
50
35
-
-
35
NOTES:
1.Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. O°C to +70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. Specified for OE at high (refer to "Timing Waveform of Write Cycle", Note 7).
6. "x" in part numbers indicates power rating (S or L).
ns
ns
ns
ns
ns
ns
ns
2653 tbl 09
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(1)
ADDRR
RlWR
twc
i
~~
J~
MATCH
twp
-X·
~[--
1
,
I4-tow~
DATAINR
j~
ADDRL
VALID
MATCH
tWDD
~~
DATAOUTL
J~
tODD
VALID
2653 drw 14
NOTE:
1. Write cycle parameters should be adhered to in order to ensure proper writing.
6.6
6
IDTI012 HIGH SPEED 2K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (RIW CONTROLLED TIMING)(1, 2, 3, 7)
twc
ADDRESS
~~
~~
l~
I
tHZ(6)
i
I
tAw
\\\\~~
ltWp(7)
~tAs
tWR
~[-
RiW
}'-
~
~tWZ(6)
DATAoUT
~tow~
(4)
1\
.'..
--------ooccn_«
INDEX
..J
..J
..J
..J..J
OER
AOR
A1R
A2R
A3R
A4R
ASR
A6R
A7R
ABR
A9R
IIOBR
II07R
J52-1
&
L52-2
2654 drw 02
LCC/PLCC
TOP VIEW
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
-0.5 to +7.0
-0.5 to +7.0
V
TA
TSIAS
TSTG
lOUT
Grade
Military
Commercial
Ambient Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V ± 10%
2654 tbl 02
o to +70
-55 to +125
°C
-55 to +125
-£5 to +135
°C
-55 to +125 '-£5 to +150
°C
Symbol
rnA
Vcc
GND
Supply Voltage
Supply Voltage
VIH
Input HiQh VotaQe
VIL
Input Low Voltaoe
50
50
RECOMMENDED DC
OPERATING CONDITIONS
NOTE:
2654 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. VTERM must not exceed Vcc + O.SV.
Parameter
Min.
Typ.
Max.
Unit
4.5
0
5
0
5.5
0.0
V
V
-
6.0(2)
V
-
0.8
V
2.2
-0.5(1)
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
6.7
2654tbl03
2
IDT 70121/1DT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V± 10%)
Parameter
Symbol
70121S
70125S
Min. Max.
Test Condition
Ilul
Input Leakage Current{?)
Vee = 5.5V, VIN
Illol
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
GE = VIH VOUT = OV to Vee
IOl= 4mA
IOH =-4mA
= OV to Vee
70121L
70125L
Min. Max. Unit
-
10
-
5
10
0.4
-
5
0.4
2.4
-
2.4
-
!lA
!lA
V
V
2654 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc = 5V ± 10%)
70121 X 25(2 70121 X 35
70125 x 25(2 70125 x 35
Test
Parameter
Symbol
lee
Dynamic
Operating
Current (80th
Ports Active)
IS81
Standby
Current (80th
Ports-TTL
Level Inputs)
Standby
IS82
Current (One
Port-TTL
Level Inputs)
IS83
Full Standby
Current (80th
Ports-CMOS
Level Inputs)
Full Standby
IS84
Current (One
Port-CMOS
Level Inputs)
Condition
CE~
Vil
Outputs Open
f = fMAX(4)
CEl and
GER~VIH
f = fMAX(4)
CEl or GER ~ VIH
Active Port
Outputs Open,
f = fMAX(4)
80th Ports GER
and GEL ~ Vee - 0.2V
VIN ~ Vee - 0.2V
or VIN ~ 0.2V, f = 0(5)
One Port GEL or CER ~ Vee
- 0.2V, VIN ~ Vee - 0.2V or
VIN ~ 0.2V, Active Port
Outputs Open, f = fMAX(4)
Version
Mil.
S
L
Com'i. S
L
Mil.
S
L
Com'i. S
L
Mil.
S
L
Com'l. S
L
Mil.
S
L
Com'i. S
L
Mil.
S
L
Com'i. S
L
Typ. Max. Typ.
- 125
- 125
125 260 125
125 220 125
- 30
30
30
65 30
30
45 30
-
-
-
80
80
175
145
-
-
1.0
0.2
15
5
-
-
70
70
170
140
80
80
80
80
1.0
0.2
1.0
0.2
70
70
70
70
70121
70125
Max. Typ.
290 125
230 125
250 125
210 125
80
30
60
30
65
30
30
45
185 80
150 80
165 80
135 80
30
1.0
10 0.2
15 1.0
5
0.2
175 70
140 70
160 70
130 70
x 45
x 45
70121 x 55 70121
70125 x 55 70125
Max. Typ.
285 125
225 125
245 125
205 125
30
80
60
30
30
65
45
30
180 80
145 80
160 40
130 40
30
1.0
10 0.2
1.0
15
5
0.2
170 70
135 70
155 70
125 70
Max.
280
220
240
200
80
60
65
45
175
140
155
125
30
10
15
5
165
130
150
120
x 70(3
x 70(3
Typ. Max. Unit
125 275 mA
125 215
-
-
30
30
80
60
-
-
80
80
170
135
-
-
1.0
0.2
30
10
-
-
70
70
160
125
-
-
-
-
mA
mA
mA
mA
2654tbl05
NOTES:
1. "x· in part numbers indicates power rating (S or L).
2. O°C to +70°C temperature range only.
3. -55°C to +125°C temperature range only.
4. At f = fMAx, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRc, and using "AC TEST
CONDITIONS· of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc=5V, TA=+25°C for Typ.
7. At Vcc~2.0V input leakages are undefined.
6.7
3
lOT 70121/1DT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version Only)
70121 L170125L
Symbol
Test Condition
Parameter
VOR
leeOR
Vee for Data Retention
Data Retention Current
Vee
teDRl~)
Chip Deselect to Data Retention Time
Operation Recovery Time
VIN 2! Vee - 0.2V or VIN $ 0.2V
tR\O}
=2.0V, CE 2! Vee -
0.2V
l Mil.
I Com'!.
Min.
Typ.(1)
2
-
-
0
tRe\':}
NOTES:
Max.
Unit
-
V
100
100
4000
lS00
-
-
f.lA
f.lA
-
ns
ns
2654 tbl06
1. Vee = 2V, TA = +25°C.
2. tRO = Read Cycle Time.
3. This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
VOR 2! 2V
\
'~
______________________
-J.I
VOR
~\\\\\\\\\\\
2654 drw 03
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
GND to 3.0V
Input Timing Reference Levels
Output Reference Levels
1.SV
1.SV
See Figures 1, 2 & 3
Sns
Output Load
2654tbl07
SV
12S00
167n
DATAoUT -
DATAOUT~ 1.73V
.......- - i
77S0
30PF*
1
SpF*
2654 drw 04
2654 drw 05
Figure 1. Equivalent Output Load
Figure 2. Output Load
(for tHZ, tLZ, twz, and tow)
1670
"B"OSYormT ~ 1.73V
30PF*
1
Figure 3. Equivalent BUSY and
2654 drw06
rnT Output Load
* Including scope and jig.
6.7
4
IDT 70121/1DT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLVVOLTAGE RANGE(5)
~0121
x 25(2)
70121
x 35
~0125 X 25(2) 70125 X 35
Symbol
Parameter
Read Cycle
Read Cycle Time
tRC
Address Access Time
tM
tACE
Chip Enable Access Time
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
Output Low Z Time(1,4)
tLZ
Output High Z Time(1,4)
tHZ
tpu
Chip Enable to Power-Up Time\")
Chip Disable to Power-Down Time(4)
tPD
70121 x 45
70125 X 45
70121 x 55 70121 x 70(3
70125 X 55 70125 X 70(3
Min. Max Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
25
12
35
-
45
-
55
-
-
-
35
35
25
-
45
45
30
-
55
55
35
-
a
a
-
a
a
-
a
a
-
-
a
a
-
10
-
15
-
20
30
50
-
35
a
-
-
50
25
-
a
-
a
-
a
-
a
a
a
-
50
-
50
-
50
-
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1,2 and 3).
2. O°C to +70°C temperature range only.
3. -55°C to + 125°C range orlly.
4. This parameter guaranteed but not tested.
5. ·x" in part numbers indicates power rating (S or L).
70
-
70
70
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
2654tbl08
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
~
tRC----------------~~
ADDRESS~toH~l
DATAoUT
lGtOH"j
PREVIOUS DATA VAL1DlXXX*
~1r........,r-x-'"Jl"""lII~W"'"lII~Ir'"X"""Jr""7,.
DATA VALID
2654drw08
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1,3)
tACE
~.
~
tAOE
tHZ
I
~[-
LtHZ~ .-
1\
tLZ
,'-' ,..,'-
DATAoUT
Icc
CURRENT
Iss
VALID DATA
-'.\ \-'r
-tpu
::t
--------J--
tLZ
III
50%
NOTES:
1. RIWis high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to, or coincident with, CE transition low.
4. ~=VIL.
tPD
..,'-
50%~
_ _ _ __
2654 drw 09
6.7
5
_
lOT 70121/10T 70125 HIGH-SPEED 2K x 9
DUAL·PORT STATIC RAM WITH BUSY & INTERRUPT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
~0121 x 25(2) 70121 X 35
~0125 X 25(2) 70125 X 35
Symbol
Write Cycle
Parameter
-
a
20
-
Write Recovery Time
a
tHZ
Data Valid to End of Write
Output High Z Time ll •4 )
tDH
Data Hold Time
twz
Write Enabled to Output in High Z(1,4)
tow
Output Active from End of Write(1,4)
Write Cycle Timel:J)
tEW
Chip Enable to End of Write
tAW
Address Valid to End of Write
tAS
twp
Address Set-up Time
Write Pulse Width U)
tWR
tDW
70121
70125
X
X
55 70121 X 70(3
55 70125 X 70(3
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
20
20
twc
70121 X 45
70125 X 45
45
35
35
30
-
-
a
-
a
12
-
20
-
-
10
-
15
0
-
a
-
10
a
-
-
NOTES:
1.Transition is measured ±500mV from low or high voltage with load (Figures 1. 2 and 3).
2. O°C to +70°C temperature range only.
3. -55'C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTERISLA VE combination. twc = tBM + twP.
6. "x" in part numbers indicates power rating (S or L).
7. Specified for OE at high (Refer to "Timing Waveform of Write Cycle". Note 7).
6.7
55
40
40
20
-
-
20
-
-
a
-
a
-
15
-
20
-
a
-
a
-
a
35
30
30
a
a
35
-
a
-
40
-
a
20
30
30
-
70
50
50
a
50
a
-
ns
ns
ns
ns
ns
ns
..30
-
35
a
-
ns
-
35
ns
-
ns
a
ns
ns
2654 tbl 09
6
lOT 70121/10T 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,2,3,7)
twc
~~
7~
I~r
ADDRESS
tHZ(6)
I
~
tWR ~
tAW
\\\\~
\.\.
,~
I
!4-tWZ(6)
DATAoUT
I+---tow
V
(4)
I]
1\
(4)
1
,
I
---------cE____J------..,-..t-t---RtWRLB
~_ _ _ _~~-+--OER
A10L - - - t - t - - - - - ,
AeL ---t=+----,
...---++--A10R
.-t=+-- ABR
I/OeL -I/015L ->'-----+4-t
1--~--.''--I/OeR-I/015R
I/OOL-I/07L --.<-........-/
1---+---.''--I/OoR-I/07R
BUSYL(1) _~----------I
BUSYR(1)
L._ _ _ _ _ _ _........_
...--_-->L..-._-,
A7L-t--~
i4-:----t- A7R
AOL-t--~
14-"---+-AOR
14------ A10R
A10L ----:---~
NOTES:
1. IOT7133 (MASTER): BUSY is open drain
output and requires pull-up resistor.
IOT7143 (SLAVE): BUSY is input.
2. LB = LOWER BYTE
3. US = UPPER BYTE
AOL ----=:....--~
~L - - - - -...
OEL -----~
R/WLUB - - - - -...
RIWLLB - - - - -...
ARBITRATION
LOGIC
(IOT7133 ONLY)
/4-----=---
AOR
14------ ~R
14------ OER
14------ RlWRUB
14------ RlWRLB
2746 drw 01
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology. Inc.
6.6
APRIL 1992
DSC·103313
1
ID17133SAlLA,ID17143SAlLA
CMOS DUAL-PORT RAMS 32K (2K
x 16-811)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
L......I1..-IL.....IL......JL.....IL.....JL.....I1..-I11L......JL......IL......J .......
9 8 7 6 5 4 3 2
I/09l
I/OlOl
IIOllL
I/012l
I/013l
I/014l
I/015L
Vee(1)
GND(2)
I/OOR
I/01R
I/02R
I/03R
II04R
I/05R
I/06R
I/07R
]
]
]
]
10
11
12
13
]14
]
]
]
]
]
]
15
16
17
18
19
20
L.....I ....... L......JL......J
68 67 66 65 64 63 62 61
60[
1
59 [
58 [
I I
LJ
J68-1
&
F68-1
57 [
56[
55[
54[
53[
52[
51 [
50 [
49 [
48[
J21
] 22
47[
46[
45[
44[
J26
27 2829 3031 3233 3435 36 37 3839 4041 42 43
J23
J24
] 25
A6l
A5l
A4l
A3l
A2l
All
AOl
BUSYl
CEl
CER
BUSYR
AOR
A1R
A2R
A3R
A4R
A5R
~~~~~~~~~~~~~~~~~
2746 drw 02
PLCC/FLATPACK
TOP VIEW
NOTES:
1. Both Vce pins must be connected to the supply to assure reliable operation.
2. Both GND pins must be connected to the supply to assure reliable operation.
3. UB = Upper Byte, LB = Lower Byte
6.8
2
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K
51
x 16-81T)
50
Pol
11
52
53
10
A8l
55
Al0l
OB
RtWllB
57
Vee (1)
61
39
35
37
Am
A4R
A3R
34
A5R
32
33
30
31
28
RIWRlB
G6B-1
1/02l
1/04l
1/06l
27
RtWRUB
24
25
1/014R
1/015R
22
23
1/012R
1/013R
20
21
1/0 lOR
I/0llR
18
19
5
7
9
1/013l
1I015l
GND(2)
2
4
6
8
10
•
1I010l
1/012l
1/0 14l
Vee(l)
I/OOR
1/02R
1/04R
1/06R
1/07R
A
B
C
D
E
F
G
H
J
K
Pin 1
11
15
26
I/0lll
1/09l
13
110m
12
1/03R
1/05R
16
14
OER
GND(2)
3
1
A9R
29
-
1I00l
1/08l
A7R
Al0R
66
68
A6R
A8R
58
1/07l
Designator
BUSYR
64
67
/
--
36
A2R
RtWLUB
1/05l
01
CEl
AOR
62
65
02
41
43
AOl
38
40
CER
BUSYl
OEl
1/03l
03
45
A2l
60
63
04
47
A4l
42
44
All
A9l
I/0ll
05
49
A7l
46
A3l
56
59
06
48
A5l
54
09
07
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1/08R
1/09R
17
L
2746 drw 03
PGA
TOP VIEW
NOTES:
1. Both Vcc pins must be connected to the supply to assure reliable operation.
2. Both GND pins must be connected to the supply to assure reliable operation.
3. UB = Upper Byte, LB = Lower Byte
6.8
3
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL·PORT RAMS 32K (2K x 16.BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
TA
Rating
Terminal Voltage
with Respect
to GND
Operating
CAPACITANCE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
o to +70
-55 to +125
°C
Symbol
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power
Dissipation
2.0
2.0
W
DC Output
Current
50
lOUT
Unit
VIN = OV
11
pF
COUT
InpuVOutput
Capacitance
VI/O= OV
11
pF
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
rnA
NOTE:
2746 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vee + 0.5V.
Max.
Input Capacitance
Grade
50
Conditions
CIN
NOTE:
2746 tbl 02
1. This parameter is determined by device characterization but is not
production tested.
Tem~erature
TSIAS
(TA = +25°C,f = 1.0MHz)
Parameter(1)
Military
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V ± 10%
2746tbl03
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
Symbol
Parameter
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + 0.5V.
6.8
-
0.8
V
2746 tbl04
4
1DT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K X 16-81T)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Either port, Vcc = 5.0V ± 10%)
IDT7133SA
IDT7143SA
Symbol
Parameter
Test Conditions
IDT7133LA
IDT7143LA
Max.
Min.
Min.
IILlI
Input Leakage Current(6)
Vee = 5.5V, VIN = OV to Vee
-
10
Illol
Output Leakage Current
CE = VIH, Your = OV to Vee
-
10
Val
Output Low Voltage (1/00-1/015)
IOl= 4mA
0.4
Val
Open Drain Output Low Voltage
(BUSY)
IOL = 16mA
-
0.5
-
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
Max.
Unit
5
~
5
~
0.4
V
0.5
V
-
V
2746tbl05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) (Vcc= 5.0V± 10%)
7133x25(1
7143x25(1)
Test
Symbol
Icc
1881
Condition
Parameter
Dynamic Operating
Current
CE::;Vll
Outputs Open
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
= fMAX(4)
1884
-
COM'L. S
L
-
300
270
S
L
-
-
-
325
295
-
75
65
25
25
75
65
25
25
70
60
25
25
70
60
-
210
190
210
190
-
200 mA
180
190
170
-
-
-
220
200
Active Port
Outputs Open
COM'L. S
L
-
Full Standby Current
(Both Ports-
Both Ports CEl &
CER ~ Vee - 0.2V
MIL.
CMOS Level Inputs)
VIN ~ Vee - 0.2V or COM'L. S
VIN::; 0.2V, f = 0(5)
L
Full Standby Current
(One Port-All
CMOS Level Inputs)
One Port CEl or
MIL.
CER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
-
190
170
-
-
1
0.2
30
10
1
0.2
30
10
1
0.2
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
1
0.2
S
-
-
-
210
-
200
-
L
-
-
-
190
-
180
-
180
190
180
-
170
-
160
-
160
-
NOTES:
1. DOC to +7DoC temperature range only.
280
250
25
25
-
VIN::; 0.2V
COM'L. S
Active Port out~uts
Open, f = fMAX 4)
L
-
80
70
-
S
L
285
255
Unit
310 mA
280
25
25
MIL.
-
-
80
70
CEl or CER~ VIH
= fMAX(4)
-
Typ.(2 Max.
25
25
75
65
L -
315
285
85
75
25
25
S
290
260
-
320
290
7133x70r90
7143x70r90
25
25
80
70
f
7133x55
7143x55
-
25
25
Standby Current
(One Port - TTL
-
295
265
COM'L. S
L
Level Inputs)
1883
-
CEl and CER~ VIH MIL.
= fMAX(4)
Level Inputs)
1882
S
L
f
7133x45
7143x45
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max.
Version
MIL.
7133x35
7143x35
200
180
-
180
160
mA
-
180
160
30
10
1
0.2
30
10
15
4
1
0.2
15
4
200
-
190 mA
-
180
-
170
-
170
150
-
150
mA
170
2746 tbl 06
2. Vcc = SV, TA = +2SoC.
3. "x" in part number indicates power rating (SA or LA).
4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. At Vcc5.2.DV input leakages are undefined.
6.8
5
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(LA Version Only) VLC = O.2V, VHC = VCC - O.2V
IDT7133LAlIDT7143LA
Symbol
Test Condition
Parameter
VDR
Vcc for Data Retention
Vcc = 2V
iCCDR
Data Retention Current
CE~ VHC
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
Max.
I
I
MiL.
-
4000
COM'L.
-
1500
V
~
-
0
tRc'2)
NOTES:
1. Vee
Unit
-
2.0
VIN ~ VHC or ~ VLC
tCDR(3)
Min.
ns
ns
27461bl07
= 2V, TA = +25°C
2. tAc = Read Cycle lime
3. This parameter is guaranteed but not tested.
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTiON MODE
VDR~2V
VDR
2746 drw 05
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 , 2 & 3
Output Load
27461bl 08
5V
5V
12500
12500
DATAoUT
DATAoUT
-....---i
7750
30pF*
Figure 1. Output Load
5V
-_---11
7750
_
~270n
BUSy-i
5pF*
Figure 2. Output Load
(for tLl, tHZ, twz, tow)
30pF*
1
2746 drw 06
Figure 3. BUSY Output Load
(IDT7133 only)
*Including scope and jig
6.8
6
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K
x 16~BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
IDT7133x25(1---2746drw 10
NOTES:
1. RNi or CE must be high during all address transitions~
_
2. A write occurs during the overlap (tEW or twp~f a low CE and a low RIW.
3. twA is measured from the earlier of CE or RIW going high to the end of write cycle.
4. Durin9..!bis period, the 1/0 pins are in the output state, and input ~nals must not be applied.
5. If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig). This parameter is sampled and not 100% tested.
7. If OE is low during a RiW controlled write cycle~e write pulse width m~st be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
'
8. RNi for either upper or lower byte.
6.8
9
1DT7133SAlLA, IDT7143SAlLA
CMOS DUAL·PORT RAMS 32K (2K
x 16·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSy(1, 2, 3) (For MASTER IDT7133)
twc
ADDRR
~(
)
MATCH
-----'
twp
~
RiWR
<
//
K.
~tDW
)
DATAIN R
tAPS (1)
ADDRL
BUSYL
K
)(~
~("
VALID
MATCH
""l---",
~tBDA
tWDD
;r
DATAOUTL
tODD (4)
_L
tBDD
) ~
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE at LO for the reading port.
2746 drw 11
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(1, 2, 3) (For SLAVE IDT7143)
twc
)
MATCH
ADDRR
twp
RiWR(2)
~K
/
<
/
>it
..--tDW
DATAIN
)(
R
VALID
MATCH
ADDRL
tWDD
)
DATAOUTL
tODD
NOTES:
1. Assume BUSY input at HI for the writing port, and OE at LO for the reading port.
2. Write cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for both ports.
E
2746 drw 12
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (For SLAVE IDT7143)
~~---------twP----~----~
p-
BU: --{:~_B
2746 drw 13
6.8
10
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K
x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION (For MASTER
IDT7133)
CEL VALID FIRST:
ADDRLANDR
~_________________A_D_D_R_ES_S_E_S_M_A_T_C_H____________________~
2746 drw 14
CER VALID FIRST:
ADDRLANDR
><=
~",---_______________A_D_D_R_ES_S_E_S_M_A_T_C_H_________________
2746 drw 15
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION(1)
(For MASTER IDT7133)
LEFT ADDRESS VALID FIRST:
~----tRC
ADDRL
OR twc
---~
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
ADDRR
t MA
BUSYR
=1_____::~~~~_t_B_DA -_-_~~~~~
__
2746 drw 16
RIGHT ADDRESS VALID FIRST:
~---tRc
OR twc
---~
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
ADDRR
ADDRL
t BAA
~"'---
____
~_.~:~~~~_t_BD_A_____~
2746 drw 17
NOTE:
1. CEl = CER
= VIL
6.8
11
IDT7133SAllA, IDT7143SAllA
CMOS DUAL-PORT RAMS 32K (2K x 16-811)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT7133/43 provides two ports with separate control,
address, and I/O pins that permit independent access for
reads or writes to any location in memory. The devices have
an automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
r~ective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array ~emitted. Each port has its own Output
Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. Non-contention READ/
WRITE conditions are illustrated in Table 1.
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip
enable match down to 5ns minimum and determine which port
has access. In all cases, an active BUSY flag will be set for
thedel~ort.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location.
When this situation occurs, on-chip arbitration logic will
determine which port has access and sets the delayed port's
BUSY flag. BUSY is set at speeds that permit the processor
to hold the operation and its respective address and data. It
is important to note that a write operation is invalid for the port
that has BUSY set LOW. The delayed port will have access
when BUSY goes inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this occurs, the on-chip
arbitration logic determines access. Two modes of arbitration
are provided: (1) if the addresses match and are valid before
CE, on-chip control logic arbitrates between CEl and CER for
access; or (2) if the CEs are low before an address match, onchip control logic arbitrates between the left and right
addresses for access (refer to Table II). In either mode of
arbitration, the delayed port's BUSY flag is set and will reset
when the port granted access completes its operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to 32 bits or more in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and
the addresses for each chip arrive at the same time, it is
possible that one will activate its BUSYl while another
activates its BUSYR signal. Both sides are now busy and the
CPUs will await indefinately for their port to become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTER/SLAVE approach where only one hardware
arbitrator, in the MASTER, is used. The SLAVE has BUSY
inputs which allow an interface to the MASTER with no
external components and with a speed advantage over other
systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse
must extend a hold time past BUSY to ensure that a write cycle
takes place after the contention is resolved. This timing is
inherent in all dual-port memory systems where more than
one chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to
BUSY from the MASTE R.
TABLE 1- NON-CONTENTION READ/WRITE CONTROL(4)
LEFT OR RIGHT PORrVll
Outputs Open
MIL.
S
L
-
(Both Ports Active)
1= IMAX(3)
COM'L. S
L
-
ISBt
Standby Current
(Both Ports-TIL
CEl and CER <: VIH MIL.
1= IMAX(3)
ISB2
ISB3
ISB4
S
L
COM'L. S
L
Level Inputs)
Standby Current
(One Port-TIL
CEl or CER <: VIH
MIL.
Active Port Outputs
Level Inputs)
Open, I = IMAX(3)
7134X35
Typ.(2) Max. Typ.(2)
Version
Symbol
S
L
COM'L. S
L
-
-
Max.
7134X45
7134XS5
-
240
200
-
75
55
25
25
70
50
25
25
25
25
75
45
25
25
70
40
-
200
170
-
190
160
-
300
260
-
280
240
-
260
220
-
-
-
-
25
25
25
25
80
50
-
-
-
-
-
280
240
-
-
70
50
25
25
70
50
25
25
70
40
25
25
70
40
-
180
150
-
180
150
-
160
130
180
150
-
170
140
-
-
-
160
130
-
-
240
200
160
130
-
-
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
CMOS Level Inputs) VIN <: Vee - 0.2V or COM'L. S
VIN:,> 0.2V, 1=0(3)
L
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
Full Standby Current One Port CEl or
CER <: Vee - 0.2V
(One Port-All
-
-
-
190
160
-
180
150
170
140
-
170
140
-
170
140
-
160
130
-
150
120
-
-
-
Full Standby Current Both Ports CEl and MIL.
CER <: Vee - 0.2V
(Both Ports-All
MIL.
S
L
S
L
CMOS Level Inputs) VIN <: Vee - 0.2V or COM'L. S
VIN :'>0.2V
L
Active Port Outputs
Open, I = IMAX(3)
-
-
-
150
120
-
-
Unit
270
220
240
200
-
-
270
220
-
-
-
7134X70
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max.
mA
mA
mA
mA
mA
150
120
NOTES:
2720 tbJ 06
1. "X" in part number indicates power rating (SA or LA).
2. Vee = 5V, TA = +25°C.
3. IMAX = 1/tRe = All inputs cycling at 1= 1/tRe (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby ISB3.
4. O°C to +70°C temperature range.
5. At Vcc:'>2.0V input leakages are undelined.
6.9
3
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC = O.2V, VHC = VCC - O.2V
Symbol
Parameter
VCC for Data Retention
Vcc = 2V
ICCOR
Data Retention Current
CE
~
VHC
VIN ~ VHC or VLC
tCOR(3)
tR(3)
Min.
Typ.(l)
Max.
Unit
2.0
-
-
V
MIL.
-
100
4000
~
COM'L.
-
100
1500
Test Condition
VOR
I
I
Chip Deselect to Data Retention Time
-
0
tRct 2)
Operation Recovery Time
-
NOTES:
1. Vce = 2V, TA = +25°C.
2. tRc = Read Cycle Time.
3. This parameter is guaranteed but not tested.
ns
ns
2720 tbl 07
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
2720 drw05
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2720 tbl 08
+5V
+5V
1250n
DATAoUT
1250n
~.--....
775n
DATAoUT
30pF *
~.--....
775n
5pF *
2720 drw 06a
2720 drw 06b
Figure 2. Output Load
(for tLZ, tHZ, twz, tow)
Figure 1. Output Load
"Including scope and jig
6.9
4
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7134X25(3)
Parameter
Symbol
Min.
Max.
7134X35
Min.
Max.
7134X45
Min.
Max.
7134X55
Min.
7134X70
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
45
-
55
-
70
-
ns
tAA
Address Access Time
-
25
25
15
-
-
45
45
25
-
55
55
30
-
70
70
40
ns
-
35
35
20
0
tACE
Chip Enable Access Time
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
0
-
5
-
5
-
5
-
ns
a
a
a
a
Output Low Z Time(1, 2)
-
0
tLz
tHZ
Output High Z Time(1, 2)
-
15
-
20
-
20
-
25
-
30
ns
-
ns
ns
ns
tpu
Chip Enable to Power Up Time(2)
0
-
a
-
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
50
-
50
-
50
-
50
-
50
ns
NOTES:
1. Transition is measured ±!)OOmV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. O°C to +70"C temperature range only.
4. "X· in part number indicates power rating (SA or LA).
2720 tbl 09
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1, 2, 4)
ADDRESS
DATAoUT
PREVIOUS DATA VALID
DATA VALID
2720 drw 07
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1, 3)
tACE
/~
~'\.
tAOE
1HZ
CtHZ~
"\K
tLZ
<..
DATAoUT
CURRENT
Isa
LJr
" " ~""
VALID DATA
~
I.
.. tpu
tPD
===========-~+?5-0-o/.-0-------------------------------------------50~%~
tLZ
Icc
~~
/
I
2720 drw 08
NOTES:
1. Rm is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = VIL.
6.9
5
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x 8-Bm
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLYVOLTAGE(6)
7134X25(5)
Symbol
Parameter
Min.
Max.
7134X35
Min.
Max.
7134X45
7134X55
7134X70
Min.
Max.
Min.
Max.
Min.
45
55
-
60
Max.
Unit
WRITE CYCLE
tDW
Data Valid to End of Write
15
-
20
-
20
-
25
-
30
-
tHZ
Output High Z Time(1, 2)
-
15
-
20
-
20
-
25
-
30
ns
toH
Data Hold Time(3)
-
3
-
3
-
3
-
3
-
ns
twz
Write Enabled to Output in High Z(l, 2)
-
15
-
20
-
20
-
25
-
30
ns
tow
Output Active from End of Write(l, 2, 3)
3
-
3
-
3
-
3
-
3
-
ns
tWDD
Write Pulse to Data Delay(4)
-
70
ns
-
55
-
90
35
-
80
Write Data Valid to Read Data Delay(4)
-
80
toDD
-
50
70
ns
twc
Write Cycle Time
25
tEW
Chip Enable to End of Write
20
tAW
Address Valid to End of Write
20
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write RecoveryTime
0
20
0
0
35
30
30
0
30
0
40
40
0
40
0
50
50
0
50
0
55
65
ns
60
-
0
-
ns
60
ns
70
0
ns
ns
ns
ns
NOTES:
2720tbll0
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. The specification for IDH must be met by the device supplying write data to the RAM under all operating conditions. Although IDH and tow values will vary
over voltage and temperature, the actual IDH will always be smaller than the actual tow.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read with Port-to-Port Delay".
5. Qoe to +70°C temperature range only.
6. "X" in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(1)
ADDRR
twc
>k
)K
MATCH
twp
"' "-
/V
tDW~
)K
DATA IN R
VALID
MATCH
ADDRL
tWDD
)K. VALID
DATAoUTL
tDDD
2720 drw09
NOTE:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
6.9
6
ID17134SAlLA
CMOS DUAL-PORT RAM 32K (4K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING(1, 2, 3,4, 6, 7)
twc
ADDRESS ~
--./
K
K
)
f4-tAs-
.7~
OE
tAW
CE
tWR-
~s...
,{
tWp(7)
~K
RMI
tLZ
DATA OUT
H
.7
(6)_
~twz
tHZ(6)--...
~
tHZ(6)
tow
"
(4)
(4)
/'
f'
tDW-
DATA IN
)
r-
tDH
"
r
./
2720 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.1, CE CONTROLLED TIMING(1, 2, 3,5)
twc
ADDRESS
)K
)(
tAW
+-tAS
1
"I
/v
tEW
________________________________
tWR-'
~~-tD-W-----.-14-----t-DH-~~_________________
DATA IN
2720 drw 11
NOTES:
1. RNi must be high during all address transitions.
2. A write occurs during the overlap (tEw or twp~f a low CE and a RNi.
3. twR is measured from the earlier of CE or RIW going high to the end of write cycle.
4. Durin~is period, the 110 pins are in the output state, and input ~nals must not be applied.
5. If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig). This parameter is sampled and not 100% tested.
7. If DE is low during a RNi controlled write 9'£le, the write pulse w~th must be the larger of twP or (twz + tDW) to allow the 110 drivers to turn off data to be
placed on the bus for the required tow. If DE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twP.
6.9
7
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT)
FUNCTIONAL DESCRIPTION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I - READ/WRITE CONTROL
The IOT7134 provides two ports with separate control,
address, and liD pins that permit independent access for
reads or writes to any location in memory. These devices
have an automatic power down feature controlled by CE. The
CE controls on-chip power down circuitry that permits the
r~ective port to go into standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array i~ermitted. Each port has its own Output
Enable control (DE). In the read mode, the port's DE turns on
the output drivers when set LOW. Non-contention READI
WRITE conditions are illustrated in the table below.
Left or Right Port(1)
RIW
CE
OE
00-7
X
H
X
Z
Port Disabled and in Power
Down Mode, 1862 or 1864
X
H
X
Z
CER = CEl = H, Power Down
Mode, 1861 or 1863
L
L
X
DATAIN
H
L
L
DATAoUT
X
X
H
Z
Function
Data on port written into
memory
Data in memory output on port
High impedance outputs
2720 tbl11
NOTE:
1.
6.9
AOL-A11L;t:AOR-A11R
H = HIGH, L = LOW, X =
Don't Care, Z = High Impedance
a
~®
Integrated Device Technology, Inc.
PRELIMINARY
IDT71342SA
IDT71342LA
CMOS DUAL-PORT RAM
32K (4K X a-BIT)
WITH SEMAPHORE
FEATURES:
DESCRIPTION:
• High-speed access
Military: 35/45/55170ns (max.)
Commercial: 25/35/45/55170ns (max.)
• Low-power operation
IDT71342SA
Active: 500mW (typ.)
Standby: 5mW (typ.)
IDT71342LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation-2V data retention
• TIL-compatible; single 5V (±10%) power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature raange (-40°C to +85°C) is available, tested to military electrical specifications
The IDT71342 is an extremely high-speed 4K x 8 dual-port
static RAM with full on-chip hardware support of semaphore
signalling between the two ports.
The IDT71342 provides two independ ent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. To assist in arbitrating between ports, a fully
independent semaphore logic block is provided. This block
contains unassigned flags which can be accessed by either
side; however, only one side can control the fla9....§.t any time.
An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry...Q!. each port to enter a very low
standby power mode (both CE and SEM high).
Fabricated using IDT's CEMOSTM high-performance
technology, this device typically operates on only 500mW of
power at maximum access times as fast as 25ns. Low -power
(LA) versions offer battery backup data retention capability,
with each port typically consuming 200JlW from a 2V battery.
The device is packaged in either a hermetic 52-pin leadless
chip carrier or a 52-pin PLCC.
The IDT71342 military devices are manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
RlWR
RlWl
CEl
CER
OEl
1++-+-.-----
IJOol-I/07L ---------t-+-I
1/0 OR - 1/07R
SEMl---------j~~--------~_j------------SEMR
AOl-A11l
-------~
RIGHTSIDE
ADDRESS 14----------- AOR - A11R
DECODE
LOGIC
LEFT SIDE
ADDRESS
DECODE
LOGIC
2721 drw 01
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CC1992 Integrated Device Technology, Inc.
6.10
APRIL 1992
OSC-1080/1
1
IDT71342SA/LA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
7 6 5
A1L
::: 8
A2L
::: 9
A3L
:::
A4L
A5L
4
3
2
52 51 50494847
46:
45:
OER
10
44:
A1R
:::
11
43:
A2R
:::
12
42:
A3R
A6L
:::
13
J52-1
41 :
A4R
A7L
::: 14
L52-2
40:
A5R
ASL
::: 15
39:
A6R
A9L
:::
16
38:
A7R
I/OOL
::: 17
37:
ASR
1/01L
::: 18
36:
A9R
1/02L
35:
::: 19
... 20
34'...
21 2223 2425262728 293031 3233 L.
N/C
1/03L
&
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to Ground
Com'l.
-0.5 to +7.0
CAPACITANCE(1)
Mil.
-0.5 to +7.0
Unit
Symbol
V
110m
2721 drw 02
LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
AOR
(TA
= +25°C, f = 1.0MHz)
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = OV
11
pF
VOUT = OV
11
pF
2721 tbl 02
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.5
1.5
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
2721 tbl01
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATI NGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specif icationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V.
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V±10%
O°C to +70°C
OV
5.0V±10%
2721 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
-
6.0(2)
V
-
0.8
Vee
Supply Voltage
GND
Ground
VIH
Input High Voltage
2.2
VIL
Inout Low Voltaae
_0.5(1)
V
2721 tbl04
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.5V.
6.10
2
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (Vcc = 5V ± 10%)
IDT71342SA
Symbol
Parameter
Test Conditions
Min.
Ilul
Input Leakage Current(S)
Vee = 5.5V, VIN = OV to Vee
IILol
Output L8akage Current
CE = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
IOL
IOL
VOH
Output High Voltage
-
= 6mA
= 8mA
IOH =-4mA
IDT71342LA
Max.
2.4
Min.
Max.
Unit
10
-
5
~
10
-
5
J.l.A
0.4
-
0.4
V
0.5
0.5
V
-
2.4
-
V
2721 tbl 05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = s.OV ± 10%)
71342X25(4)
Parameter
lee
Dynamic Operating
Current
CE::;Vll
Outputs Open
MIL.
(Both Ports Active)
SEM = Don't Care
1= IMAX(3)
COM'L. S
L
Dynamic Operating
Current
CE~ VH
Outputs Open
MIL.
(Semaphores
Both Sides)
SEM ::; VL
1- IMAX(3)
COM'L. S
L
Standby Current
(Both Ports-TTL
CEl and CER ~ VIH
SEMl = SEMR ~ VIH
MIL.
Level Inputs)
1= IMAX(3)
Standby Current
(One Port-TTL
Level Inputs)
lec1
IS81
IS82
IS83
Test Conditions
Typ.(2)
Symbol
Version
S
L
71342X35
-
-
-
-
-
-
280
240
-
200
170
-
-
-
COM'L. S
L
25
25
CEl or CER ~ VIH
Active Port Outputs
MIL.
-
Open, I = IMAX(3)
SEMl =SEMR > VIH
COM'L. S
L
S
L
S
L
S
L
Full Standby Current Both Ports CEl and
(Both Ports-All
CER ~ Vee - 0.2V
MIL.
CMOS Level Inputs) VIN ~ Vce - 0.2V or
VIN::; 0.2V
COM'L. S
L
S
L
-
-
-
190
170
280
240
240
200
-
270
220
240
200
170
150
-
170
150
170
140
-
170
140
25
25
75
55
25
25
70
50
25
25
80
50
25
25
75
45
25
25
70
40
-
-
200
170
190
160
170
140
-
-
-
260
220
-
-
185
155
180
150
-
300
260
71342X55
71342X70
Typ.(2) Max. Typ.(2) Max. Unit
-
-
-
71342X45
Max. Typ.(2) Max. Typ.(2) Max.
-
-
270
220
rnA
240
200
170
150
-
170
140
70
50
25
25
70
50
25
25
70
40
25
25
70
40
180
150
-
160
130
-
180
150
160
130
-
rnA
rnA
rnA
160
130
-
-
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
-
190
160
-
180
150
-
170
140
-
-
-
170
140
150
120
-
150
120
-
150
120
rnA
SEMl=SEMR~
IS84
Vcc - 0.2V 1=0(3)
Full Standby Current One Port CEl or
CER ~ Vcc - 0.2V
(One Port-All
CMOS Level Inputs) VIN ~ Vcc - 0.2V or
VIN::; 0.2V
SEMl = SEMR ~
Vcc -0.2V
Active Port Outputs
Open I = IMAX(3)
S
L
-
-
-
-
COM'L. S
L
-
MIL.
170
140
-
150
130
-
rnA
2721 tbl06
NOTES:
1. "X" in part number indicates power rating (SA or LA).
2. Vee = 5V, TA = +25°C.
3. IMAX = 1/tRC = All inputs cycling atl = 1/tRC (except Output Enable). 1=0 means no address or control lines change. Appliesonly to inputs at CMOS level
standby IS83.
4. O°C to +70°C temperature range.
5. At Vcc::;2.0V input leakages are undelined.
6.10
3
ID171342SAlLA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC = O.2V, VHC = VCC - O.2V
Symbol
Parameter
VOR
VCC for Data Retention
ICCOR
Data Retention CUrrent
Test Condition
Min.
Typ.(1)
Max.
Unit
-
2.0
-
-
V
-
100
4000
JlA
100
1500
0
-
tRC(2)
-
Vcc = 2V
CE~VHC
tCOR(3)
tR(3)
Chip Deselect to Data Retention Time
VIN
~
I
I
MIL.
COM'L.
VHC or:::; VLC
Operation Recovery Time
-
ns
ns
2721 tbl07
NOTES:
1. Vee = 2V, TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW
Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vec
2721 drw 03
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2721 tbl 08
+5V
12500
DATAoUT
DATAoUT
---<~-....
7750
---<.---....
775Q
30pF'
5pF •
2721 drw04b
2721 drw04a
Figure 2. Output Load
(for tLZ, tHZ, twz, tow)
Figure 1. Output Load
"Including scope and jig
6.10
4
IDTI1342SAlLA
CMOS DUAL·PORT RAM 32K (4K x S.BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
71342X25(5)
Symbol
Parameter
Min.
71342X35
Max.
Min.
71342X45
Max.
Min.
71342X55
Max.
Min.
71342X70
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
45
-
55
-
70
-
tAA
Address Access Time
-
25
35
ns
Output Enable Access Time
-
-
35
20
70
40
ns
tAOE
25
15
-
70
-
-
55
Chip Enable Access Time(3)
-
45
tACE
-
tOH
Output Hold from Address Change
0
-
0
-
0
ns
tLZ
Output Low Z Time(1, 2)
0
-
0
-
tHZ
Output High Z Time(1, 2)
-
15
-
tpu
Chip Enable to Power Up Time(2)
0
-
tPD
Chip Disable to Power Down Time(2)
-
tsop
SEM Flag Update Pulse (OE or SEM)
tWDD
tDDD
45
25
0
5
-
20
-
0
-
50
-
10
-
Write Pulse to Data Delay(4)
-
50
Write Data Valid to Read Data
Delay(4)
-
35
55
30
ns
ns
5
-
5
-
20
-
25
-
30
ns
0
-
0
-
0
-
ns
50
-
50
-
50
-
50
ns
15
-
15
-
20
-
20
-
ns
-
70
-
80
-
80
-
90
ns
70
ns
55
55
0
65
ns
2721 tbl09
NOTES:
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is~aranteed but not tested.
__
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
4. Port to Port delay through RAM cells from writing port to a reading port.
5. O°C to +70°C temperature range only.
6. ·X· in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1, 2, 4)
ADDRESS
~~~~~~~~~UA~t~~~~~~~~~~~~~
~14~-----tOH ----~
~~
---~
----'
tOH
DATA VALID
PREVIOUS DATA VALID
DATAoUT
2721 drwOS
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1, 3)
!4-tsop
CEor SEM(5)
tACE
/~K
/~
tsop
tHZ
tAOE
)~
CtHZ~
~K
tLZ
.,,,-/ /"7"-
DATAoUT
-'.,.
tLZ
I+tpu
Icc
CURRENT
" " -'.,.
~500/.
VALID DATA
II"
~
tPD
___________
IS8
NOTES:
1. Rm is high for Read Cycles.
2. Device is continuously enabled, CE = VIL. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = VIL.
5. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
6.10
2721 drw 06
5
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(1,2)
twc
ADDRR
>K
)(
MATCH'
twp
"':\..
/
/
tow
)/
,:\..
DATAINR
tDH
>k
VALID
ADDRL
J
MATCH
tWDD
DATAoUTL
) ( VALID
tODD
2721 drw 07
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. Device is continuously enabled for both ports.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
7134X25(5)
Parameter
Symbol
7134X35
Min.
Max.
Min.
-
35
Max.
7134X45
7134X55
Min.
Max.
Min.
Max.
45
55
20
-
25
-
7134X70
Min.
Max.
Unit
WRITE CYCLE
ns
0
-
60
-
ns
0
-
ns
30
-
ns
20
-
15
-
20
-
20
-
25
-
30
ns
-
3
-
3
-
3
-
3
-
ns
15
-
20
-
20
-
25
-
30
ns
-
3
-
3
10
10
-
10
10
-
10
-
10
-
10
-
ns
10
-
3
10
-
3
twc
Write Cycle Time
25
tEW
Chip Enable to End of Write(3)
20
tAW
Address Valid to End of Write
20
tAS
Address Set-up Time
0
twp
Write Pulse Width
20
tWR
Write RecoveryTime
0
tow
Data Valid to End of Write
15
tHZ
Output High Z Time(1, 2)
-
tDH
Data Hold Time(4)
0
twz
Write Enabled to Output in High Z(1, 2)
-
tow
Output Active from End of Write(1, 2, 4)
3
tSWR
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
30
30
0
30
0
40
40
0
40
0
10
50
50
0
50
0
70
60
60
ns
ns
ns
ns
ns
2721 tbll0
NOTES:
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is~aranteed but not tested.
__
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL This condition must be valid for the entire lEw time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although IDH and tow values will vary
over voltage and temperature, the actual IDH will always be smaller than the actual tow.
5. OOG to +70°C temperature range only.
6. "X· in part number indicates power rating (SA or LA).
6.10
6
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K
x B-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING(1, 2,3, 7)
ADDRESS
twc
==>K
V
)
r--...
f4-tAs--to
./k'
OE
tAW
CE or SEM
(8)
tWR-
~~
~
tWp(7)
~K..
tLZ
V
tHZ(6)
tow
H
DATA OUT
./
I4--twz (6)_
l/
"/
(4)
f
tHZ(6)_
to~
tow-
)
l-
"/
1/
DATA IN
(4)
r
2720 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.1, CE CONTROLLED TIMING(1, 2, 3, 5)
twc
ADDRESS
)K
)K
tAW
CE(B)
i-4-tAS
DATA IN
'}
-I
/V
tWR___.
tEW
______---1EtDW
..'..
tDH3)f-___
2721 drw 09
NOTES:
1. Rm must be high during all address transitions.
2. A write occurs during the overlap (tEW or twplPf a low CE or ~M and a low Rm.
3. twR is measured from the earlier of CE or RIW (or SEM or RIW) going high to the end of write cycle.
4. Durin9..!!!s period, the 1/0 pins are in the output state, and input signals ~st not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig) .. This parameter is sampled and not 100% tested.
7. If OE is low during a RNi controlled write ~Ie, the write pulse w~th must be the larger of twp or (twz + tDW) to allow the 1/0 drivers to turn off data to be
placed on the bus for the required tow. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twP.
8. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Either condition must be valid for the entire tEW time.
6.10
7
IDT71342SAlLA
CMOS DUAL·PORT RAM 32K (4K x a·BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
t+----tAA ---~
Ao - A2
VALID ADDRESS
DATAoUT
VALID
DATAo
R/Vi
------~~~tAOE
2721 drw 10
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4)
NOTES:
1. DaR = DOL = Vll, CER = CEl = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. Either side "A" = left and side "S" = right, or side "A" = right and side "S" = left.
3. This parameter is measured from the point where RiWA or SEMA goes high until RiWB or SEMB goes high.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.10
a
IDT71342SAlLA
CMOS DUAL·PORT RAM 32K (4K
x S·BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IOT71342 is an extremely fast dual·port 4K x 8 CMOS
static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the dual-port RAM to claim a privilege
over the other processor for functions defined by the system
designer's software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a
portion of the dual-port RAM or any other shared resource.
The dual-port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS static RAMs and can be read from or written to at the
same time, with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the dual-port RAM. These devices have an automatic
power-down feature controlled by CE, the du~ort RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Table 1 where CE and
SEM are both high.
Systems which can best use the IOT71342 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IOT71342's hardware semaphores, which
provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IOT71342 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the dual-port RAM. These latches can be used
to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphores provide a
hardware assist for a use assignment method called "Token
Passing Allocation." In this method, the state of a semaphore
latch is used as a token indicating that a shared resource is in
use. If the left processor wants to use this resource, it requests
the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful,
it proceeds to assume control over the shared resource. If it
was not successful in setting the latch, it determines that the
right side processor had set the latch first, has the token and
is using the shared resource. The left processor can then
either repeatedly request that semaphore's status or remove
its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the
set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IOT71342 in a
separate memory space from the dual-port RAM. This address
space is accessed by placing a low input on the SEM pin
(which acts as a chip select forthe semaphore flags) and using
the other control pins (Address, OE, and R/W) as they would
be used in accessing a standard static RAM. Each of the flags
has a unique address which can be accessed by either side
through the address pins Ao-A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other (see
Table II). That semaphore can now only be modified by the
side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other .side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location
from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or
OE) to go inactive or the output will never change.
A sequence of WRITE/READ must be used by the
semaphore in order to guarantee that no system level
contention will occur. A processor requests access to shared
resources by attempting to write a zero into a semaphore
location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will
appear as a one, a fact which the processor will verify by the
subsequent read (see Table II). As an example, assume a
processor writes a zero in the left port at a free semaphore
location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume
6.10
9
II
•
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
control overthe resource in question. Meanwhile, if a processor
on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be
read from that semaphore on the rightside during asubsequent
read. Had a sequence of READ/WRITE been used instead,
system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 3. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
TABLE I -
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will now stay low
until its semaphore request latch is written to a one. From this
it is easy to understand that, if a semaphore is requested and
the processor which requested it no longer needs the resource,
the entire can hang up until a one is written into that semaphore
request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at the
same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
NON-CONTENTION READ/WRITE CONTROL
Left or Right Port(1)
RNI
CE
SEM
OE
X
H
H
X
H
H
L
X
X
X
H
L
X
DATAIN
Port Data Bit DO Written Into Semaphore Flag
L
H
L
DATAoUT
Data in Memory Output on Port
L
L
H
X
DATAIN
X
L
L
X
-
J
H
00-7
Function
Z
Port Disabled and in Power Down Mode
L
DATAoUT
Data in Semaphore Flag Output on Port
H
Z
Output Disabled
Data on Port Written Into Memory
Not Allowed
27211blll
NOTE:
1. AOL=Al0L:tAoR-Al0R
H = HIGH, L = LOW, X = Don't Care, Z
J= Low-to-High transition.
= High Impedance
TABLE 11- EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1)
Function
No Action
00- 07 Left
Do - 07 Right
1
1
Status
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left side has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
27211bl12
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
6.10
10
1D171342SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen. Code integrity is of the
utmost importance when semaphores are used instead of
slower, more restrictive hardware intensive schemes.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-Some examples
Perhaps the simplest application of semaphores is their
application as resource markers for the IOT71342's dual-port
RAM. Say the 4K x 8 RAM was to be divided into two 2K x 8
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of the memory.
To take a resource, in this example the lower 2K of dual-port
RAM, the processor on the left port could write and then read
a zero into Semaphore O. If this task were successfully
completed (a zero was read back rather than a one), the left
processor would assume control of the lower 2K. Meanwhile,
the right processorwou Id attempt to perform the same function.
Since this processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control of the second 2K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Seniaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of dual-port RAM with each
other.
The blocks do not have to by any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the dual-port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices had determined which memory area was "off limits"to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT" state is available on one or both sides. Once
a semaphore handshake has been performed, both processors
can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures.
In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads and
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
Do
WRITE
~D
SEMAPHORE
READ
SEMAPHORE
REQUEST FLIP FLOP
D~
Q~3Jw{T
•
•
Do
WRITE
SEMAPHORE
READ
2721 drw 12
Figure 3. 10171342 Semaphore Logic
6.10
11
t;)®
PRELIMINARY
IDT7014S
HIGH-SPEED 36K
(4K X 9-8IT)
DUAL-PORT RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• True dual-ported memory cells which allow simultaneous
reads of the same memory location
• High-speed access
Military: 20/25/35ns (max.)
Commercial: 15/20/25ns (max.)
• Low-power operation
IOT7014S
Active: 900mW (typ.)
• lOT'S BiCEMOSTM process
• Fully asynchronous operation from either port
• TTL-compatible; single 5V (±10%) power supply
• Available in 52-pin plastic leaded chip carrier
• Military product compliant to MIL-STO-883, Class B
The IOT7014 is an extremely high-speed 4K x 9 dual-port
static RAM designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself
to those systems which cannot tolerate wait states or are
designed to be able to externally arbitrate or withstand
contention when both sides simultaneously access the same
dual-port RAM location.
The IOT7014 provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. It is the user's responsibility to ensure data integrity
when simultaneously accessing the same memory location
from both ports.
The IOT7014 utilitizes a 9-bit wide data path to allow for
parity at the user's option. This feature is especially useful in
data communication applications where it is necessary to use
a parity bit for transmission/reception error checking.
Fabricated using lOT's BiCEMOSTM high-performance
technology, these dual-ports typically operate on only 900mW
of power at maximum access times as fast as 15ns.
The IOT7014 is packaged in a 52-pin PLCC. Military grade
product is manufactured in compliance with the latest revision
of MIL-STO-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
RlWR
RlWl
OER
IIOOl-I/Oal --''----~
AOl- A 11l
LEFT SIDE
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
1'4----L--_
I/OOR- I/OaR
RIGHT SIDE
ADDRESS
DECODE
LOGIC
AOR-A11R
2528 drw 01
BiCEMOS"'" is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
6.11
APRIL 1992
DSC·l07612
1
IDT7014S HIGH-SPEED 36K (4K x 9-81T)
DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
~ ~ ~ ~ ~
IN DEX "
E
~ ~ ~ ~ ~
ffi ffi
,.....,«""I""'i«I""'r"'I"«,..,.«.,..,.«..,..,«..,....I""«'I""I""«,..,.«"'I"T«..,..,«I""'t""'I"«,..,.«~
44:::
43:::
OEl
42:::
41:::
, 40::
Vee
39:::
RlWl
38:::
A10l
J52-1
A11l
37:::
GND
IIOal
36:::
I/07L
I/06l
2528 drw 02
52-Pin PLCC
Top View
NOTES:
1. All Vee pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Commercial
Military
Unit
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3)
Terminal Voltage
-0.5 to Vee
-0.5 to Vee
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
0(.;
Storage
Temperature
-55 to +125
VTERM
TSTG
lOUT
(2)
Rating
DC Output Current
Grade
Military
Commercial
50
50
GND
O°C to +70°C
OV
OV
Vee
5.0V±10%
5.0V ± 10%
25281bl02
RECOMMENDED DC OPERATING CONDITIONS
Symbol
-65 to +150
Ambient
Temperature
-55°C to + 125°C
°C
rnA
NOTES:
2528 Ibl 01
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATI NGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Inputs and Vee terminals only.
3. 1/0 terminals only.
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
Vil
Input Low Voltage
-0.5(1)
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
6.11
-
0.8
V
2528 Ibl 03
2
IDT7D14S HIGH-SPEED 36K (4K x 9-Bm
DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vce = S.OV± 10%)
1017014S
Symbol
Parameter
Test Condition
Min.
Max.
10
0.4
V
-
V
IILlI
Input Leakage Current
Vcc = 5.5V, VIN = OV to Vcc
IILol
Output Leakage Current
VOUT = OV to Vcc
VOL
Output Low Voltage
IOL=4mA
-
VOH
Output High Voltage
IOH =-4mA
2.4
Unit
flA
flA
10
2528tbl04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vee = SV± 10%)
1017014S15(1)
Test
Symbol
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Icc
Version Typ.
Condition
Outputs Open
f = fMAX(3)
Max.
1017014S20
1017014S25
Typ.
Typ.
Max.
Max.
1017014S35(2)
Max.
Unit
Mil.
-
-
-
260
-
255
Typ.
-
250
rnA
Com'l.
-
250
-
245
-
240
-
-
2528tbl05
NOTES:
1. Qoe to +70 o e temperature range only.
2. -55°C to +125°e temperature range only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRe, and using "Ae TEST
CONDITIONS' of input levels of GND to 3V.
AC TEST CONDITIONS
GND to3.0V
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
DATAOUT~
....L
;[
Zo=50n
~
See Figures 1,2 and 3
Output Load
} son
1.5V
2528 drw 03
2528tbl06
Figure 1. Output load.
CAPACITANCE (TA = +2S0C, f = 1.0MHz)
Symbol
Parameter(1)
Condition
Max. Unit
CIN
Input Capacitance
VIN = OV
11
COUT
Output Capacitance
VOUT= OV
11
pF
pF
2528 tbl 07
5V
!J.TAA
(Typical, ns)
1250n
4
DATAoUT -....--...
775n
5pF*
20 40 60 80 100120140160180 200
2582 drw 04
Capacitance (pF)
2528 drw 05
• Including scope and jig.
Figure 3. Lumped Capacitive Load, Typical Derating.
Figure 2. Output Load (for tHZ, twz, and tow)
6.11
3
ID17014S HIGH-SPEED 36K (4K
DUAL-PORT RAM
x 9-81T)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7014X1S(3)
Svmbol
Parameter
Min.
Max.
7014X20
Min.
Max.
7014X3S(4)
7014X25
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
-
20
-
25
-
35
-
ns
tAA
Address Access Time
15
-
20
10
-
25
12
-
35
ns
20
ns
3
3
-
3
0
-
0
-
3
-
ns
-
9
-
11
-
15
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tLl
Output Low Z Time(1, 2)
0
-
tHZ
Output High
-
7
Z Time(1, 2)
8
NOTES:
1.
2.
3.
4.
ns
ns
2528tbl08
Transition is measured ±500m V from low or high impedance voltage with load (Figure 1).
This parameter is guaranteed but not tested.
O°C to +70°C temperature range only.
-55°C to +125°C temperature range only.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1 ,2)
ADDRESS
DATAoUT
-----..l'""". ~. ~ ~ ~ ~ t-O~H~ ~ ~ ~ -t~A ~ ~=:-tR~-C=~- =~- =~_-=-~_-=-~_-~ " '- - - - - - - -t~ ""'----to-H-_-_-_-_-_----t-~--PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1, 3)
'{;'"""~-----tAOE---~Jl~
DATAoUT
----t-----
~1<-+--k
)K
MATCH
twp
",
/V .
tDW_
)(
DATAIN R
VALID
MATCH
ADDRL
tWDD
)K VALID
DATAoUTL
tDDD
2528 drw08
6.11
5
IDTI014S HIGH-SPEED 36K (4K X 9-Bln
DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE(1, 2, 3, 4, 5)
~---------------------twc--------------------~
ADDRESS
~----------------tAW---------------~
tAs -"f4----------twP (5) __________~-tWR
RiW
DATAoUT
tDH~~_ _ __
DATAIN
2528 drw 09
NOTES:
1. RiW must be high during all address transitions.
2. twR is measured from RiW going high to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig). This parameter is sampled and not 100% tested.
5. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off data to be
placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twP.
FUNCTIONAL DESCRIPTION
TABLE 1- READ/WRITE CONTROL
The IDT7014 provides two ports with separate control,
address, and 1/0 pins that permit independent access for
reads or writes to any location in memory. It lacks the chip
enable feature of CEMOSTM Dual Ports, thus it operates in
active mode as soon as power is applied. Each port has its
own Output Enable control (OE). In the read mode, the port's
OE turns on the output drivers when set LOW. Non-contention
READ/WRITE conditions are illustrated in the table below.
Left or Right Port(1)
RIW
OE
00-8
Function
L
X
DATAIN
Data on port written into
memory
H
L
DATAoUT
Data in memory output on port
X
H
Z
High impedance outputs
2528 tbl10
NOTE:
1. AOL-A11L:tAoR-A11R
H = HIGH, L = LOW, X = Don't Care, Z
6.11
=
High Impedance
6
t;)®
HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS
DUAL-PORT RAM
PRELIMINARY
IDT7099S
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed clock-to-data output times
- Military: 20/25/30ns (max.)
- Commercial: 15/20/25ns (max.)
• Low-power operation
- IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• 4K X 9 bits
• Architecture based on dual-port RAM cells
- Allows full simultaneous access from both ports
- Independent bit/byte read and write inputs for control
functions
• lOT's BiCEMOSTM process technology
• Synchronous operation
- 4ns setup to clock, 1 ns hold on all control, data, and
address inputs
- Data input, address, and control registers
- Fast 15ns clock to data out
- Self-timed write allows fast write cycle
- 20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA and PLCC
• Military product compliant to MIL-STO-883, Class B
The IDT7099 is a high-speed 4K x 9 bit synchronous dualport RAM. The memory array is based on dual-port memory
cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up
and hold times. The timing latitude provided by this
approach allow systems to be designed with very short
realized cycle times. With an input data register, this device
has been optimized for applications having unidirectional data
flow or bi-directional data flow in bursts. Changing data
direction from reading to writing normally requires one dead
cycle.
Fabricated using lOT's BiCEMOSTM high-performance
technology, these dual-ports typically operate on only
900mW of power at maximum high-speed clock-to-data output times as fast as 15ns. An automatic power down
feature, controlled by CE, permits the on-chip circuitry of each
port to enter a very low standby power mode.
The IDT7099 is packaged in a 68-pin PGA or 68-pin
PLCC. Military grade product is manufactured in compliance
with the latest revision of MIL-STO-883, Method 5004.
FUNCTIONAL BLOCK DIAGRAM
I/08 ............,r-_~
WRITE
LOGIC
I/OO-7L
14-+-+--+-+-++-1
MEMORY
ARRAY
...-_ _..... I/OSR
I/Oo-7R
WRITE
LOGIC
SENSE
SENSE
AMPS DECODER DECODER AMPS t-++-+-+--H~~
BIT OER
BIT OE !.:
BYTE OEl:--+-'
BYTE OER
CLKR
CLKl:----~~~4-+_--~+#--~--~
CLKEN !.:-------+--H--+_---+-6.ft--~-----'
CLKEN R
ST
ST
WT
GEN(1)
J-o'-I--+-~WT
GEN(1)
REG 1--1--4-.....
BIT RlWR
REG
BYTE RlW R
CE R
NOTE:
1. Self-timed write generator.
3007 drw at
BiCEMOS is a trademark of Integrated Device Technology, Inc.
APRIL 1992
MILITARY AND COMMERCIAL TEMPERATURE RANGE
©1992 Integrated Device Technology, Inc.
6.12
DSC-l09712
IDT7099S HIGH-SPEED 36K (4K x 9-81T)
SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
51
50
A5l
53
52
A7L
55
48
A4l
49
44
42
40
CLKl ~LKENR
AOl
All
CLKENl
47
A3l
A6l
46
A2l
45
43
41
CLKR
38
A1R
39
AOR
36
37
A2R
35
A4R
54
57
59
BIT
OEl
A7R
33
A9R
56
Alll
34
A6R
32
A8l
A9l
ASR
A3R
30
A10l
A8R
31
AllR
58
BYTE
OEl
28
BIT
OER
Al0R
29
BYTE
OER
61
BYTE
RIWl
60
Vee
GND
GND
63
62
BIT
RIWl
24
BIT
RIWR
25
BYTE
RIWR
64
22
23
NC
65
-CER
-
GND
67
26
GU68-1
CEl
66
I/07L
68
20
1
I/06l
3
Pin1/
Designator A
5
Vee
NC
2
•
I/08R
I/08l
4
7
I/03l
6
11
9
I/Oll
8
GND
10
I/05l
I/04l
I/02l
I/OOl
B
C
o
E
13
I/OOR
12
GND
F
15
I/02R
14
18
Vee
16
I/06R
27
NC
21
GND
19
I/07R
•
17
I/01R
I/03R
I/04R
I/05R
G
H
J
.K
L
3007 drw 02
68-Pin PGA
Top View
NOTES:
1. All vee pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
6.12
2
I
IDTI099S HIGH-SPEED 36K (4K x 9-81T)
SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONTINUED)
INDEX
L--J L.....J
L-I
L.....J
L......J
L......J
L....I
L.....J
9 8 7 6 5 4 3 2
A6l
A7L
A8l
A9l
A10l
A11l
BYTE DEL
BIT DEL
Vee
BYTE RlWl
BIT RNiL
NC
I I
L......J
L......J
L.....J
L......J
L.....J
L-J L......J L-J
C&]~
GND
I/08l
"
68 67 66 65 64 63 62 61
60[
59[
58 [
57 [
56[
55[
54[
J68-1
53[
52[
51 [
50[
49[
I I
~
] 10
] 11
] 12
] 13
] 14
]15
] 16
] 17
] 18
] 19
] 20
] 21
~[~
] 23
47[
] 24
46 [
] 25
45 [
] 26
44 [
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/07L
I/06l
"
A7R
A8R
A9R
A10R
A11R
BYTEOER
BIT OER
GND
GND
BYTE RlWR
BIT RiWR
NC
r-1 r-1 f 1 r-1 r I r - l r I r-1 . , . , . . , 1'1 . , ,...., . ,
r-l.,
GND
I/08R
I/07R
I/06R
~
3007 drw 03
68-Pin PLCC
Top View
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
ABSOLUTE MAXIMUM RATINGS (1)
Commercial
Military
Symbol
Rating
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +7.0 -0.5 to +7.0
Terminal Voltage
-0.5 to VCC -0.5 to VCC
VTERM(3)
o to +70
V
V
-55 to +125
°C
Temperature
Under Bias
-55to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
lOUT
DC Output Current
TA
Operating
Temperature
TSIAS
50
50
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Unit
Grade
Ambient
Temperature
GND
VCC
Military
-55°C to +125°C
OV
5.0V ± 10%
Commercial
O°C to +70°C
OV
5.0V ± 10%
3007tb102
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Min.
Typ.
Max.
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
-
6.0
V
VIL
Input Low Voltage
-
0.8
Symbol
rnA
NOTES:
3007tb10l
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Inputs and Vee terminals only.
3. 110 terminals only.
2.2
-0.5(1)
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
6.12
Unit
V
3007tbl03
3
IDTI099S HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc
= 5.0V
± 10%)
IDT7099S
Symbol
Parameter
IILlI
Input Leakage Current
Test Condition
VCC = 5.5V, VIN = OV to VCC
Illal
VOL
Output Leakage Current
CE = VIH, VOUT = OV to VCC
Output Low Voltage
IOL=4mA
-
VaH
Output High Voltage
IOH =-4mA
2.4
Min.
Max.
10
10
/lA
/lA
0.4
V
-
-
Unit
V
3007tbl04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5V ± 10%)
IDT7099S 15(1)
Test
Symbol
lee
1581
1582
1583
1584
Condition
Parameter
Version Typ.
GE:S;Vll
Dynamic
Operating
Outputs Open
Current (Both f = fMAX(3)
Ports Active)
Standby
GEL and
Current (Both CER ~VIH
f = fMAX(3)
Ports-TTL
Level Inputs)
Standby
Current (One
Port-TTL
Level Inputs)
GEL or CER ~ VIH
Active Port
Outputs Open, .
f = fMAx(3)
Full Standby
Current (Both
Ports-CMOS
Level Inputs)
Both Ports GER
and GEL;::: Vee - 0.2V
VIN ~ Vee - 0.2V
or VIN :s; 0.2V, f = 0(4)
Full Standby
Current (One
Port-CMOS
Level Inputs)
One Port CEl or CER ~ Vee
- 0.2V, VIN ~ Vee - 0.2V or
VIN :s; 0.2V, Active Port
OutputsOpen, f = fMAX(3)
Max.
IDT7099S20
IDT7099S25
IDT7099S30(2)
Typ. Max.
Typ.
Max.
Typ.
Max.
Unit
Mil.
-
-
-
390
-
370
-
360
rnA
Com'!.
-
390
-
360
-
340
-
-
Mil.
-
-
-
190
-
170
-
140
Com'!.
-
220
-
180
-
160
-
-
Mil.
-
-
-
290
-
270
-
250
Com'!.
-
300
-
270
-
250
-
-
Mil.
-
-
-
20
-
20
-
20
Com'!.
-
10
-
10
-
10
-
-
Mil.
-
-
-
280
-
260
-
240
Com'!.
-
290
-
260
-
240
-
-
rnA
rnA
rnA
rnA
NOTES:
3007tbiOS
1. aoc to +7aoC temperature range only.
2. -55°C to +125°C temperature range only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1ItCLK, and using "AC TEST
CONDITIONS" of input levels of GND to 3V.
.
4. f = a means no address, clock: or control lines change. Applies only to inputs at CMOS level standby.
AC TEST CONDITIONS
Input Pulse Levels
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
DATA aUT
GND to 3.0V
Input Rise/Fall Times
D-f.~)
--.r::=
.
Zo = 50n
I
~
} 50n
1.5V
3007 drw 04
See Figures 1, 2 and 3
Figure 1. Output load.
6.12
4
ID17099S HIGH-SPEED 36K (4K X g-Bln
SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5V
8
7
6
12500
!lTM
(Typical, ns)
5
4
DATAoUT _~.-.._......
3
7750
5pF·
2
3007 drw 05
20 40 60 80 100120140160180200
Capacitance (pF)
, Figure 2. Output Load (for tClZ, tCHZ, tOlZ, and tOHZ).
3007 drw 06
·Including scope and jig.
Figure 3. Lumped Capacitive Load, Typical Derating.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE{READ AND WRITE CYCLE TIMING}
(Commercial: VCC = 5V ± 10%, TA = O°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
Commercial
7099515
5ymbol
Parameter
7099520
Min. Max. Min.
Max.
Military
7099525
7099520
Min. Max. Min. Max.
-
20
8
8
-
25
10
10
-
20
Clock Low Time
20
6
6
tCQV
Clock High to Output Valid
-
15
-
20
-
tRSU
Registered Signal Set-up Time
tRHD
Registered Signal Hold Time
tCOH
Data Output Hold After Clock High
4
1
3
tClZ
Clock High to Output Low Z
2
-
-
tClK
Clock Cycle Time
tClKH
Clock High Time
tClKL
7099525
Unit
25
10
10
-
30
12
12
-
ns
8
8
-
25
-
20
-
-
5
2
3
2
2
-
6
30
-
ns
-
25
-
2
-
-
ns
-
9
3
2
2
2
3
2
2
-
10
-
-
0
tCHZ
Clock High to Output High Z
2
7
5
1
3
2
2
9
6
1
3
2
2
tOE
Output Enable to Output Valid
-
8
-
10
-
12
12
tOll
Output Enable to Output Low Z
0
-
0
-
0
-
0
tOHZ
Output Disable to Output High Z
-
7
-
-
11
-
-
12
12
11
tcsu
Clock Enable, Disable Set-up Time
4
tCHD
Clock Enable, Disable Hold Time
2
-
5
2
-
6
2
-
5
3
-
6
3
-
-
30
-
35
-
45
-
35
-
45
9
7099530
Min. Max. Min. Max.
9
-
7
ns
ns
ns
-
15
15
0
-
ns
-
14
ns
7
3
-
ns
-
55
ns
ns
ns
ns
ns
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read
Data Delay
3007tbl06
6.12
5
ID17099S HIGH·SPEED 36K (4K x 9·811)
SYNCHRONOUS DUAL·PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE(1,2)
CLOCK
BYTE~W ~~~~--~~~~~~~---+~~~~~~~--~~~~~~~--~~~~~~
orBIT~
ADDRESS
DATAoUT
------+------<.
BYTE OE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--/
orBITot
3007 drw07
TIMING WAVEFORM OF READ CYCLE WITH PORT-TO-PORT DELAY
CLOCKR
RJWR
ADDRR
DATAINR
CLOCKL
ADDRL
MATCH
?
--JXXXXXZZ)l<
tCWDO
DATA OUTL __________
NOTES:
XX?----ZZ)I<
X~
VALID
3007 drw 08
1. GEL = CER = L, ~L = CIl « « « « « « «
I ~
o 0 0 wi
::::,::::, z 0
I/D2L
I/03L
I/04L
I/00L
GND
I/05L
I/00L
Vee
GND
I/OOR
I/01R
I/02R
Vee
I/03R
I/04R
I/05R
I/06R
IDT7005
J68-1
L68·1
A5L
A4L
A3L
A2L
AlL
AOL
INTL
BUSYL
GND
Mis
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
2738 dfW02
LCC/PLCC/FLATPACK
TOP VIEW
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
6.13
2
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
51
11
All
55
09
BUSYR
GND
37
AOR
28
CEl
GND
24
OER
I/04l
I/02l
7
GND
6
4
9
I/OlL
8
13
11
110m
GND
10
15
Vee
14
12
16
I/03l
I/05l
I/06l
Vee
I/OOR
I/02R
I/03R
B
C
D
E
F
G
H
Pin 1
Designator
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
I/04R
I/05R
CER
21
20
5
NC
23
SEMR
NC
2
•
25
22
3
A12R
NC
RiWl
1
Al0R
27
26
ID17005
8Kx 8 DPR
IN 68-PIN PGA
G68-1
A8R
29
AllR
NC
A6R
31
A9R
A12l
A5R
33
30
66
I/Oll
34
A4R
Al0l
I/OOl
68
35
AlA
64
OEl
A3R
32
62
SEMl
36
A2R
60
67
02
39
41
43
INTl
Am
INTR
A8l
NC
65
03
45
All
38
40
Mis
BUSYl
58
Vee
63
04
AOl
56
A11L
61
05
47
A3l
42
44
46
A2l
54
59
06
A6l
A9l
57
07
48
A4l
49
52
53
10
08
50
A5l
RiWR
19
18
I/07R
NC
17
I/06R
K
L
2738 d:w 03
6a-PIN PGA
TOP VIEW
PIN NAMES
Left Port
Right Port
CEl
CER
Names
Chip Enable
R1Wl
RfWR
ReadIWrite Enable
DEL
OER
Output Enable
AOl-A12l
AOR - A12R
Address
I/OOl - I/OlL
I/OOR -II07R
Data Input/Output
SEMl
SBVlR
Semaphore Enable
TI'ITl
TI'ITR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
27381bl18
6.13
3
IDTI005S/L
HIGH-SPEED BK
x B DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
RIW
DE"
SEM
1100-7
H
X
H
Hi-Z
Mode
L
L
X
X
H
DATAIN
'L
H
L
H
DATAoUT
X
X
H
X
Hi-Z
NOTE:
1. AOL -
Deselected: Power Down
Write to Memory
Read Memory
Outputs Disabled
2738 tbl 01
A12L ~ AOA -
A12A
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RIW
OE
SEM
1100-7
H
H
L
L
DATAoUT
Read Data in Semaphore Flag
X
X
L
DATAIN
Write DINO into Semaphore Flag
X
H
L
J
Mode
-
L
Not Allowed
2738 tbl 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage
with Respect
toGND
-0,5 to +7.0
Military
-0.5 to +7.0
Unit
V
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65to+150
°C
DC Output
Current
Military
Commercial
TA
lOUT
Grade
50
GND
Vee
·55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
2738tbl05
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
0
0
V
VIH
Input High Voltage
2.2
6.0(2)
V
VIL
Input Low Voltage
-0.5(1)
0.8
V
Symbol
50
Ambient
Temperature
mA
NOTES:
2738 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTEAM must not exceed Vee + O.SV.
Parameter
NOTES:
1. VIl2: -3.0V for pulse width less than 20ns.
2. VTEAM must not exceed Vee + O.SV.
-
Unit
2738 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
COUT
Output
Capacitance
Conditions
= OV
VOUT = OV
VIN
Max.
Unit
11
pF
11
pF
NOTE:
2738 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
6.13
4
IDT7005S/L
HIGH-SPEED BK x B DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc= 5.0V± 10%)
10T7005S
Parameter
Symbol
Test Conditions
Min.
IOL = 4mA
-
IOH = -4mA
2.4
IILlI
Input Leakage Current(5)
Vee = 5.5V, VIN = OV to Vee
IILol
Output Leakage Current
Cl:: = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
Max.
10T7005L
Min.
Max.
Unit
10
-
5
10
5
flA
flA
0.4
-
0.4
V
-
2.4
-
V
2738 tbl 07
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = 5.0V ± 10%)
Symbol
lee
1581
1582
Test
Condition
Parameter
Dynamic Operating
Current
GE ::; VIL, Outputs Open
SE;ii~ VIH
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CER = CEL~ VIH
SE;iiR = S'E"fVfL~ VIH
Level Inputs)
f
= fMAX(3)
= fMAX(3)
Standby Current
CEL or CER~ VIH
(One Port - TTL
Active Port Outputs Open
Level Inputs)
f
= fMAX(3)
Version
MIL.
1584
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port-All
CMOS Level Inputs)
NOTES:
-
-
COM'L.
S
L
160
160
MIL.
S
L
-
-
COM'L.
S
L
20
20
70
50
-
mA
340
290
mA
S
-
L
-
S
95
240
L
95
210
S
L
S
L
1.0
0.2
10
15
5
MIL.
S
L
-
-
COM'L.
S
L
90
90
220
180
MIL.
COM'L.
Both Ports Cl::L and
CER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN::; 0.2V, f = 0(4)
S'E"fVfR = S'E"fVf~ Vee - 0.2V
One Port GEL or
Cl::R ~ Vee - 0.2V
S'E"fVfR = "SEML~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN ::; 0.2V
Active Port Outputs Open, f = fMAX(3)
-
S
L
S'E"fVfR - S'E"fVfL> VIH
1583
7005X35
COM'L ONLY
Typ.(2) Max. Uni
MIL.
COM'L.
mA
-
mA
rnA
2738 tbl 08
1. X in part numbers indicates power rating (S or L)
2. Vee = SV, TA = +2SoC.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRe, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. At Vcc$.2.0V input leakages are undefined.
6.13
5
IDT7005S/L
HIGH-SPEED 8K
x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vec = 5.0V ± 10%)
7005X45
Symbol
lee
1881
1882
Test
Condition
Parameter
Dynamic Operating
Current
CE ::; Vll, Outputs Open
SEf'J~ VIH
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CEl = CER~ VIH
SEf'JR = SEMl~ VIH
Level Inputs)
f
=fMAX(3)
=fMAX(3)
Standby Current
CER or CEl~ VIH
(One Port -
Active Port Outputs Open
TTL
Level Inputs)
f
=fMAX(3)
= SEMl> VIH
1884
7005X70
MIL ONLY
Max. TypP) Max. Unit
Typ.(2)
Max.
Typ.(2)
MIL.
S
L
155
155
400
340
150
150
395
335
140
140
390
330
COM'L.
S
L
155
155
340
290
150
150
335
285
-
-
MIL.
S
L
16
16
85
65
13
13
85
65
10
10
85
65
COM'L.
S
L
16
16
70
50
13
13
70
50
-
-
MIL.
S
90
290
85
290
80
290
L
90
250
85
250
80
250
S
90
240
85
240
L
90
210
85
210
-
-
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
-
-
-
-
Version
COM'L.
SEMR
1883
7005X55
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
COM'L.
VIN::; 0.2V, f = 0(4)
SEf'JR = SElJl~ Vee - 0.2V
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
One Port GEL or
CER ~ Vee - 0.2V
S
85
260
80
260
75
260
CMOS Level Inputs)
SElJR = SElJl~ Vee - 0.2V
COM'L.
VIN ~ Vee - 0.2V or
VIN::; 0.2V
L
85
85
215
220
80
80
215
220
75
215
S
-
-
Active Port Outputs Open,
f = fMAX(3)
L
85
180
80
180
-
-
MIL.
MIL.
rnA
rnA
rnA
rnA
rnA
NOTES:
2738 tbl 08
1. X in part numbers indicates power rating (S or L)
2. Vee = 5V, TA = +25°C.
3. At f = fMAX, address and control lines {except Output Enable} are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.13
6
IDTI005S/L
HIGH-SPEED BK x B DUAL-PORT STATIC RAM
MILITARVAND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVERALL TEMPERATURE RANGES (L Version Only)
(VLC =
a 2V.VHe = Vee - a 2V)
Symbol
Parameter
Test Condition
VDR
Vee for Data Retention
Vee = 2V
lecDR
Data Retention Current
CE~VHe
teDR(3)
tR(3)
Chip Deselect to Data Retention Time
VIN ~ VHC or $ VLC
I MIL.
I COM'L.
Min.
Typ.(1)
2.0
-
0
tRe(2)
Operation Recovery Time
Max.
Unit
-
V
100
4000
~
100
1500
-
-
ns
-
NOTES:
1. TA = +25°e, Vcc = 2V
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not tested.
ns
2738 tbl 09.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
VDR
CE
71777IIfV1H
~
2V
\~__________
V_D_R__________~I
tR~
~\\\\
2738 drw04
AC TEST CONDITIONS
Input Pulse Levels
GND to3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
OU1pU1 Reference Levels
1.5V
OutpU1 Load
See Figures 1 & 2
2738 tbl10
5V
1250n
DATAoUT
167n
BUSV~1.73V
Il'IT
DATAoUT-_-....
j30P
775n
P
5pF*
2738 drw 06
2738 drw 05
* Including scope and jig.
Figure 2. Output Load
(for tLl, tHZ, twz, tow)
Figure 1. Equivalent Output Load
6.13
7
IDT7005S/L
HIGH·SPEED 8K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDTIOO5X35
COM'L ONLY
Symbol
Parameter
Min.
Max.
Unit
35
-
35
ns
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time(3}
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
35
20
-
tLZ
Output Low Z Time(1, 2)
3
-
ns
tHZ
Output High Z Time(1, 2)
-
ns
tpu
Chip Enable to Power Up Time(2}
tPD
Chip Disable to Power Down Time(2}
-
15
50
tsoP
Semaphore Flag Update Pulse (OE or SEM)
15
-
ns
0
IDTIOO5X45
Parameter
Symbol
Min.
Max.
IDTIOO5X55
Min.
Max.
55
ns
ns
ns
ns
ns
IDTIOO5X70
MIL ONLY
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
-
55
tAA
Address Access Time
-
tACE
Chip Enable Access Time(3}
-
45
45
tAOE
Output Enable Access Time
-
25
-
-
3
5
70
ns
ns
-
70
35
-
ns
-
3
5
55
30
-
70
-
ns
ns
tOH
Output Hold from Address Change
tLZ
Output Low Z Time(1, 2)
3
5
tHZ
Output High Z Time(1, 2)
-
20
-
25
-
30
ns
tpu
Chip Enable to Power Up Time(2}
0
-
0
-
-
ns
tPD
Chip Disable to Power Down Time(2}
-
50
-
Semaphore Flag Update Pulse
15
-
15
50
-
ns
tsoP
50
-
0
15
(DE or SEM)
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = L, SEM = H.
4. X in part numbers indicates power rating (5 or L).
6.13
ns
ns
2738tbl t 1
8
IDT7005S/L
HIGH·SPEED 8K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
~---------------------tRC
·ADDR
: . - - - tAOE (4) ______. - j
-----r'-r'""T""" I
RiW
I
I
I
I
DATA OUT
:'-tLZ(1)
I
VALID DATA
(4)
BUSYOUT
tsoo (3,4)
2738 drw 07
NOTES:
1. Timing depends on which signal is asserted last, DE" or ct:.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BOSV has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tM or tBDD.
5. S1:M = H.
TIMING OF POWER-UP POWER-DOWN
2738 drw 08
6.13
9
IDTI005S/L
HIGH·SPEED 8K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
IDT7005X35
COM'L ONLY
Parameter
Symbol
Max.
Min.
Unit
WRITE CYCLE
twc
Write Cycle Time
35
-
ns
tEW
Chip Enable to End of Write(3)
30
ns
30
-
ns
0
-
ns
tAW
Address Valid to End of Write
tAS
Address Set·up Time(3)
0
ns
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End of Write
25
-
15
ns
0
-
ns
15
ns
30
ns
ns
tHZ
Output High Z Timel1,
tDH
Data Hold Time(4)
twz
Write Enable to Output in High Zp, 2)
tow
Output Active from End of Write(1, 2, 4)
0
-
ns
tSWRD
SEM Flag Write to Read Time
10
ns
tsps
SEM Flag Contention Window
10
-
2)
-
Parameter
Symbol
IDT7005X45
IDT7005X55
Min.
Min.
Max.
Max.
ns
IDT7005X70
MIL. ONLY
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tEW
Chip Enable to End of Write(3)
tAW
Address Valid to End of Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
45
40
..
40
0
35
-
tDW
Data Valid to End of Write
25
-
tHZ
Output High Z Time(1, 2)
-
20
tDH
Data Hold Time(4)
twz
Write Enable to Output in High Z(1, 2)
tow
0
55
45
45
0
30
25
-
0
-
-
20
-
25
Output Active from End of Write(1, 2, 4)
0
-
0
-
tSWRD
SEM Flag Write to Read Time
10
-
10
tsps
SEM Flag Contention Window
10
-
10
0
ns
40
-
-
30
ns
-
ns
50
-
0
ns
70
-
40
-
-
50
50
0
0
0
-
ns
ns
ns
ns
ns
30
ns
0
-
ns
-
10
-
ns
-
10
-
ns
NOTES:
27381bl12
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = L, SEM = H. To access semaphore, CE = Hand SEM = L. Either condition must be valid for the entire tEw time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although IDH and tow values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. X in part numbers indicates power rating (S or L).
6.13
10
IDT7005S/L
HIGH-SPEED 8K X 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,3,5,8)
twc
~J
~
ADDRESS
I
tHZ
i
tAW
J
•
tWp(2)
04-tAS(6)
~l-
RlW
]'r
1\
14--
DATAoUT
~tow
twz
V
(4)
lJ
~
.'"
(4)
,
J
--------------------------~~
_______________~~~----------------tDW
DATAIN
tWR(7)
tDH
2738 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,3,5,8)
,
twc
ADDRESS
~
]~
tAW
~
I4-tAs!6)
1
J
"'4
-----------------------------i~~--------------~---~----------------tDW
DATAIN
"WR(7)_
tEW(2)
tDH
2738 drw 10
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
RfN must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low RfIJ for memory array writing cycle.
twR is measured from the earlier of CE or RiW (or SEM or RIW) going high to the end of write cycle.
During this period, the 110 pins are in the output state and input signals must not be applied.
If the CE or SEM low transition occurs simultaneously with or after the Rffllow transition, the outputs remain in the high impedance state.
Timing depends on which enable signal is asserted last, CE", RIW, or byte control.
Timing depends on which enable signal is de-asserted first, CE", RffI, or byte control.
If DE is low during RIW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tow. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.13
11
IDT7005S/L
HIGH-SPEED aK x a DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao -A2
VALID ADDRESS
SEM
DATA 0 ------+--------+--<
~ ------~----,
- - - " " _ - - ' t AOE
OE
Write Cycle
NOTE:
1. CE: = H for the duration of the above timing (both write and read cycle).
Read Cycle
2738 drw 11
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
AOA-A2A
SIDE(2) "A"
MATCH
X
RlWA
SEMA
AOB-A2B
SIDE(2)"B"
RlWB
SEMB
NOTES:
1. DOR = DOL = L, CE:R = CE:L = H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "B" is the opposite port from "A".
3. This parameter is measured from RiWA or ~ going high to R/We or smB going high.
.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is not guarantee which side will obtain the flag.
6.13
12
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7005X35
COM'L ONLY
Parameter
Symbol
BUSY TIMING (MIS
IBAA
IBOA
IBAC
Min.
BOSV Access Time from Address Match
l3OSY' Disable Time from Address Not Matched
l3OSY' Access Time from Chip Enable Low
tBOC
BUSY Disable Time from Chip Enable High
tAPS
Arbitration Priority Set-up Time(2)
tBOO
BUSY Disable to Valid Data(;:!)
Unit
-
35
30
30
25
ns
5
-
-
BUSY TIMING (MIS = L)
l3OSY' Input to Write(4)
tWB
tWH
Max.
= H)
Write Hold After 13OS'Y'5)
ns
ns
ns
ns
Note 3
ns
0
25
-
ns
-
60
45
ns
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
tDOO
Write Data Valid to Read Data Delay(1)
Parameter
Svmbol
BUSY TIMING (MIS
IDT7005X45
IDT7005X55
Min.
Min.
-
35
30
30
25
-
tBOC
tAPS
Arbitration Priority Set-up Time(2)
5
tBOO
l3OSY' Disable to Valid Data(3)
-
tBOA
tBAC
Max.
IDT7005X70
MIL ONLY
Min.
Max.
Unit
=H)
l3OSY' Access Time from Address Match
BOSV Disable Time from Address Not Matched
l3OSY' Access Time from Chip Enable
l3OSY' Disable Time from Chip Enable
tBAA
Max.
ns
-
45
40
40
35
-
-
5
45
40
40
35
-
ns
ns
ns
5
-
Note 3
-
Note 3
ns
0
25
-
0
25
-
ns
70
55
-
80
-
95
80
ns
Note 3
ns
ns
=
BUSY TIMING (MIS L)
ffiJSY Input to Write(4)
tWB
tWH
0
25
Write Hold After BUSY(5)
-
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
-
tDOO
Write Data Valid to Read Data Delay(1)
-
65
ns
NOTES:
2738 tbl13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (MIS = H) or "Timing Waveform of
Write With Port-To-Port Delay (MlS=L)"".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tODD - tOW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'x" is part numbers indicates power rating (5 or L).
6.13
13
IDTI005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSy(2) (MiS
=H)
twc
ADDRR
-~K
)(
MATCH
twp
~
RiWR
./
""
)
tAPS (1)
) K~
BUSYL
>kH
I---tDW
DATAIN R
ADDRL
I"
K
VALID
MATCH
\
~tBDA
"r-"
tSDD
)-
tWDD
)
DATAOUTL
tODD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CE"l = CE:R = L
3. DE = L for the reading port.
E
2738 drw 13
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1,2)(M/S = L)
ADDRR
twc
-
)
MATCH
K
twp
~
RiWR
"-
./
Y
~<"
~tDW
)
DATAIN R
K
VALID
MATCH
ADDRL
tWDD
)
DATAoUTL
tDDD
NOTES:
1. BUSY input equals H for the writing port.
2. eEL =
= L
E
2738 drw 14
erR
TIMING WAVEFORM OF SLAVE WRITE (MIS = L)
~~--------twP----~----~
8U:~ --{:W_BF273B drw 15
6.13
14
IDT7005S/L
HIGH·SPEED 8K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MIS
ADDR 'A'
and 'B'
=H)
~~________________A_D_D_R_ES_S_E_S_M_A_T_C_H____________________~
CE'A'
tAPS
(2)
"---t~
2738 drw 16
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDRESS "N"
MATCHING ADDRESS "N"
ADDR'B'
BUSY'B'
2738 drw 17
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7005X35
COM'L ONLY
Parameter
Symbol
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
-
ns
tiNS
Interrupt Set Time
-
30
ns
tlNR
Interrupt Reset Time
-,
30
ns
IDT7005X45
Parameter
Symbol
Min.
Max.
IDT7005X55
Min.
Max.
0
-
ns
IDT7005X70 '
MIL. ONLY
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
NOTE:
1. "x" in part numbers indicates power rating (8 or L).
35
35
0
-
40
40
0
0
-
-
ns
50
ns
50
ns
ns
2738 tbl14
6.13
15
1DT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~---------------------twc--------------------~
ADDR'A"
I INS (3)
=t------------------------------------------------2738 drw 18
~---------------------tRc --------------------~
INTERRUPT CLEAR ADDRESS
ADDR's'
(2)
CE's'
OE's'
IINR(3)}
INT's'
2738drw 19
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Left Port
Right Port
OEl AOl-A12l INTl
OER AOR-A12R INTR
L(2)
X
X
Function
RIWR
CER
X
X
X
X
Lt:lJ
X
L
L
1FFF
H(3)
X
L
L
X
1FFE
X
Set Left INTL Flag
1FFE
Ht"J
X
X
X
X
X
Reset Left INTL Flag
RlWl
eEL
L
L
X
1FFF
X
X
X
X
X
X
X
X
L
L
NOTES:
Set Right INTR Flag
Reset Right INTR Flag
2738tbl15
1. Assumes BUSYL = BUSYR = H.
2. If BUSYL = L, then no change.
3. If BUSYR = L, then no change.
6.13
16
ID17005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE 11- ADDRESS BUSY
ARBITRATION
Inputs
eEL
eER
X
X
H
X
X
H
L
L
AOL-A12L
AOR-A12R
NO MATCH
MATCH
MATCH
MATCH
Outputs
"EffiSYL(1) BOSVR(1)
Function
H
H
Normal
H
H
Normal
H
H
Normal
(2)
(2)
Write Inhibit(3j
NOTES:
2738tblt6
1. Pins BOSYL and "EiUS'?R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT7005 are push pull, not open drain outputs. On slaves the "EiUS'?x input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs ofthis port. IftAPs is not met, either "EiUS'?L or "EiUS'?R = Low will result. "EiUS'?Land BOS'Y'Routputs cannot be lowsimultaneouly.
3. Writes to the left port are internally ignored when "EiUS'?L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when "EiUS'?R outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
00- 07 Left
Status
00- 07 Right
Semaphore free
1
No Action
1
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphorE
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Right port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
2738tbl17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.
FUNCTIONAL DESCRIPTION
The message (8 bits) at 1 FFE or 1FFF is user-defined. If the
interrupt function is not used, address locations 1FFE and
1 FFF are not used as mail boxes, but as part of the random
access memory. Refer to Table I forthe interrupt operation.
The IOT7005 provides two ports with separate control,
address and 110 pins that permit independent access for reads
or writes to any location in memory. The IOT7005 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is set when the right port
writes to memory location 1 FFE (HEX). The leftportclearsthe
interrupt by reading address location 1 FFE. Likewise, the
right port interrupt flag (INTR) is set when the left port writes to
memory location 1FFF (HEX) and to clear the interrupt flag
(INTR), the right port must read the memory location 1 FFF.
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
6.13
17
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
a:
w
CE
CE
MASTER
Dual Port
RAM
Busy (L) Busy (R)
SLAVE
Dual Port
RAM
Busy (L)
MASTER
CE
Dual Port
RAM
Busy (L) Busy (R)
SLAVE
CE
Dual Port
RAM
Busy (R)
Busy (L)
0
a()
w
Busy (R)
0
Busy (R)
2738 drw 20
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
SEMAPHORES
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the lOT 7005 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IOT7005 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IOT7005 RAM the busy pin is
an output if the part is used as a master (MIS pin = H), and the
busy pin is an input if the part used as a slave (MiS pin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
can be initiated with the RlW signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
The IOT7005 is an extremely fast dual-port 8K x 8 CMOS
static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the dual-port RAM to claim a privilege
over the other processor for functions defined by the system
designer's software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a
portion of the dual-port RAM or any other shared resource.
The dual-port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the dual-port RAM. These devices have an automatic
power-down feature controlled by CE, the dual-port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IOT7005 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IOT7005's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IOT7005 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
6.13
18
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the dual-port RAM. These latches can be used
to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphores provide a
hardware assist for a use assignment method called "Token
Passi.ng Allocation." In this method, the state of a semaphore
latch IS used as a token indicating that shared resource is in
use. If the left processor wants to use this resource, it requests
the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful
it proceeds to assume control over the shared resource. If it
was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and
is using the shared resource. The left processor can then
either repeatedly request that semaphore's status or remove
its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the
set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7005 in a
separate memory space from the dual-port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard static RAM. Each of
t~e fla~s has a unique address which can be accessed by
either Side through address pins AD -A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
activ~. This ~erves to disallow the semaphore from changing
state In the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
sema~hor~ in a test loop must cause either signal (SEM orOE)
to go inactive or the output will never change.
A ~equence WRITE/READ must be used by the semaphore In order to guarantee that no system level contention will
occur. A processor requests access to shared resources by
attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain. a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the rightside during subsequent read. Had
a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the ~ame location. The reason for this is easily understood by
I~oklng at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag
low and the other side high. This condition will continue until
a one is written to the same semaphore request latch. Should
the other side's semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made the
logic guarantees that only one side receives the token. If'one
s~de is earlier than the other in making the request, the first
Side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains. a zero must be
6.13
19
1DT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7005's dual-port
RAM. Say the BK x B RAM was to be divided into two 4K'x B
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
dual-port RAM, the processor on the left port could write and
then read a zero in to Semaphore o. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 4K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back
one in response to the zero it had attempted to write into
Semaphore o. At this point, the software could choose to try
and gain control of the second 4K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of dual-port RAM with each
other.
a
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the dual-port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CP U must be locked out of a section
of memory during a transfer and the lID device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits"to
the CPU, both the CPU and the lID devices could access their
assigned portions of memory continuously without any wait
.
states.
Semaphores are also useful in applications where no
memory "WAIT" state is available on one or both.sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads and
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
R PORT
b..EQBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE
_--.1....--1
'---'--_ _+ SEMAPHORE
READ
READ
2738 drw 21
Figure 4. IDT7005 Semaphore Logic
6.13
20
e;J
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
IDT7024S/L
Integrated Device Technology, Inc.
FEATURES:
more than one device
• Mis = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• True dual-ported memory cells which allow simultaneous
reads of the same memory location
• High-speed access
- Military: 35/45/55/70ns (max.)
- Commercial: 25/30/35/45/55ns (max.)
• Low-power operation
- IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TIL compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, quad flatpack and PLCC
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7024 is a high-speed 4K x 16 dual-port static RAM.
The IDT7024 is designed to be used as a stand-alone 64K-bit
FUNCTIONAL BLOCK DIAGRAM
R!WL
UBL
- "'
I
'"-,
r
j
~
'"--,
-.-./
1
A11L
A10L
-
··
~
~
7j~
0
I--
I/0Bl -1/015L
COL
SEL
I/00l -1/07L
I--
"----
BUSYL
A9L
AOL
-'-
"-
.I
··
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY'
S
is input.
2. BUSY outpu ts
andfNl'outputs
are non-tri-stated
push-pull.
RIWL
SEML
INTL
ROW
SELECT
A11L
AoL
CEL
OEL
UBL
LBL
t/
"-~
COLUMN
I/O
~
I:-...
...
I
~r
"v
MEMORY
ARRAY
.
1
I
COLUMN
tllfl
MIS
..
I--
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEMOS is a trademari< of Integrated Device Technology, Inc.
1/0
I--
A10R
I/OBR-I/015R
COL
SEL
I/OOR -I/OlA
"----
I
BUSYR
..
..
~
v
K
A11R
.
ROW
SELECT
··
A9R
AOR
A11R
AOfl
CER
OER
UBR
LBR
RIWR
SEMR
INTR
2740drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<\)1992 Integrated Device Technology, Inc.
r-L
~~ Lt
6.14
APRIL 1992
DSC·l04512
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
dual-port RAM or as a combination MASTER/SLAVE dualport RAM for 32-bit-or-more word systems. Using the lOT
MASTER/SLAVE dual-port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and liD pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CEMOSTM high-performance technology, these devices typically operate on only 750mW of
power at maximum access times as fast as 25ns. Low-power
(L) versions offer battery backup data retention capability with
typical power consumption of 500llW from a 2V battery.
The IOT7024 is packaged in a ceramic 84-pin PGA, an 84pin quad flatpack, and a PLCC. The military devices are
processed 100% in compliance to the test methods of MILSTO-883, Method 5004.
PIN CONFIGURATIONS
1I00L
I/0.:lL
I/010L
I/OllL
I/012L
I/013L
GND
I/014L
I/015L
Vee
GND
I/OOR
I/01R
I/02R
Vee
I/03R
I/04R
I/05R
I/OSR
I/07R
I/OaR
An
IDT7024
J84-1
F84-2
ASL
A5L
A4L
A3L
A2L
AlL
AOL
INTL
BUSYL
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
A5R
ASR
2740 drw02
PLCC/FLATPACK
TOP VIEW
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
6.14
2
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
63
61
1/07L
66
64
1/010L
67
58
1/04L
65
1/08l
55
1/02L
59
1/06l
69
54
I/OOL
56
1/03l
65
I/0lll
50
UBl
46
45
AllL
LBL
47
CEl
53
GND
48
SEML
49
I/0ll
57
1/09l
51
OEL
44
NC
43
52
Vee
72
75
41
76
79
33
Vee
81
32
IDT7024
GS4-3
GND
82
31
84
Mis
28
29
AOR
INTL
07
7
11
GND
12
10
8
2
5
1/01 OR
1/013R
1/015R
6
9
23
SEM R
GND
14
17
15
13
20
AllR
22
A8R
16
18
05
04
Am
25
A5R
UBR
RlWR
BUSYR
27
A2R
1/07R
06
All
30
INTR
26
1/09R
os
36
1/04R
1
1/06R
A2l
34
AOl
GND
Vee
1/02R
83
1/05R
09
37
35
,BUSYl
80
1/03R
A4l
A3l
78
77
1/01R
10
A6l
74
GND
A5l
39
RlWl
73
70
11
40
38
1/014l
I/OOR
A7L
A8L
1/012L
71
1/015l
42
AlOL
A9l
68
1/013l
,
60
1/05L
03
A3R
24
A6R
19
02
A4R
3
4
1/08R
I/0llR
1/012R
1/014R
OER
LBR
CER
N/C
Al0R
A9R
21
A7R
A
B
C
D
E
F
G
H
J
K
L
01
2740 drw03
Pin 1
Designator
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
84·PIN PGA
TOP VIEW
PIN NAMES
Left Port
Right Port
GEL
CER
Names
Chip Enable
RlWl
RlWR
ReadlWrite Enable
DEL
DER
Output Enable
AOl- Alll
AOR-AllR
Address
1/00l - I/015l
I/OOR -1/015R
Data InpuVOutput
SEMl
SE'fVfR
Semaphore Enable
UE3l
UE3R
Upper Byte Select
rnl
rnR
Lower Byte Select
TfJTl
TfJTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2740 tblt8
6.14
3
IDT7024S/L
HIGH-SPEED 4K
x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON·CONTENTION READ/WRITE CONTROL
Inputs(l)
outputs
CE
RIW
OE
UB
LB
SEM
1/08-15
1/00-7
H
X
X
X
X
H
Hi-Z
Hi-Z
X
X
X
H
H
H
Hi-Z
Hi-Z
Both Bytes Deselected: Power Down
L
L
X
L
H
H
DATAIN
Hi-Z
Write to Upper Byte Only
L
L
X
H
L
H
Hi-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
Hi-Z
L
H
L
H
L
H
Hi-Z
L
H
L
L
L
H
X
X
H
X
X
X
Mode
Deselected: Power Down
Read Upper Byte Only
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
Hi-Z
Hi-Z
Outputs Disabled
NOTE:
2740 tbl 01
1. AOL-AllL ;tAoR-AllR
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RIW
OE
UB
LB
SEM
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
DATAoUT DATAoUT Read Data in Semaphore Flag
X
1/08-15
Mode
1/00-7
L
H
H
L
H
J
X
X
X
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
X
-.I
X
H
H
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
L
X
X
L
X
L
L
X
X
X
L
L
H
-
-
NotA"owed
-
NotA"owed
2740tbl02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM(2)
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V±10%
O°C to +70°C
OV
5.0V± 10%
2740 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTE:
2740 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vee + O.SV.
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
a
a
V
VIH
Input High Voltage
2.2
-
6.0(2)
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VII2 -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
2740 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(l)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = OV
11
pF
COUT
Output
Capacitance
VOUT= OV
11
pF
NOTE:
2740 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
6.14
4
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc= S.OV± 10%)
1017024S
Symbol
Parameter
Test Conditions
IILlI
Input Leakage Current(5)
Illol
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
Min.
= 5.5V, VI~ = OV to Vee
CE = VIH, VOUT = OV to Vee
IOl = 4rnA
IOH = ·4rnA
Vee
2.4
1017024L
Max.
Max.
Unit
-
5
5
flA
flA
0.4
-
0.4
V
-
2.4
-
10
10
Min.
V
2740 tbl 07
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = S.OV ± 10%)
7024X25
COM'L ONLY
Test
Symbol
Icc
IS81
IS82
Condition
Parameter
Dynamic Operating
Current
CE ::; Vll, Outputs Open
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CER = CEL~ VIH
SEMR = SEML~ VIH
Level Inputs)
f
= fMAX(3)
Standby Current
CEl or CER~ VIH
(One Port -
Active Port Outputs Open
TTL
Level Inputs)
MIL.
S
L
COM'L.
S
L
SEfVf~ VIH
= fMAX(3)
f
= fMAX(3)
IS84
170
170
360
$19.
COM'L.
S
L
25
25
MIL.
S
L
-,:" ; ;i: :i: ~:
COM'L.
Both Ports GEL and
CER ~ Vee· 0.2V
CMOS Level Inputs)
COM'L.
VIN ~ Vee· 0.2V or
VIN::; 0.2V, f = 0(4)
SEMR = SEML~ Vee· 0.2V
Full Standby Current
(One Port-All
One Port CEl or
CER ~ Vee· 0.2V
CMOS Level Inputs)
SEMR
MIL.
350
300
':~:?2::::::;::
:::::. ::;:'
70::::
<:)::§p: .
22
22
70
50
-
S
105:{: :::::::250
L
105·::::·:
S
L
:::i:;::
S
L
165
165
:::;:::::::,..
S
L
Full Standby Current
(Both Ports - All
·:::::::~O
160
160
340
290
20
20
85
65
20
20
70
50
95
290
95
250
250
95
240
100
215
95
210
1.0
0.2
30
10
1.0
0.2
15
5
90
90
260
215
)(1;0·::::::::' 15
5
400
340
100
;;;;;~;~;~;~
Oi2/( )i
160
160
1.0
0.2
15
5
rnA
rnA
rnA
rnA
t:':::::;;:;:·:::·
MIL.
S
L
COM'L.
S
100
230
95
230
90
220
L
100
190
95
190
90
180
=SEML~ Vee· 0.2V
VIN ~ Vee· 0.2V or
Max.
MIL.
SEMR = SEML> VIH
IS83
TypP)
Version
7024X30
7024X35
COM'L ONLY
Typ.(2) Max. Typ.(2) Max. Unit
;0:::
rnA
VIN::; 0.2V
Active Port Outputs Open,
f - fMAX(3)
2740 tbl 08
NOTES:
1. X in part numbers indicates power rating (5 or L)
2. Vec = SV, TA = +2SoC.
3. At f = fMAx, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions·
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. At Vee ~ 2.0V input leakages are undefined.
6.14
5
ID17024SfL
HIGH·SPEED 4K
x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc = 5.0V ± 10%)
7024X45
Symbol
lee
1581
1582
Test
Condition
Parameter
Dynamic Operating
Current
CE::; Vll, Outputs Open
SEM~ VIH
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CEl = CER~ VIH
SEMR = SEMl~ VIH
Level Inputs)
f
= fMAX(3)
=fMAX(3)
Standby Current
CER or CEl~ VIH
(One Port-TIL
Active Port Outputs Open
f = fMAX(3)
Level Inputs)
SEMR
IS83
IS84
7024X55
7024X70
MIL ONLY
Typ.(2) Max. Unit
Typ,(2)
Max.
Typ.(2)
Max.
MIL.
S
L
155
155
400
340
150
150
395
335
140
140
COM'L.
S
L
155
155
340
290
150
150
335
285
-
-
MIL.
S
L
16
16
85
65
13
13
85
65
10
10
85
65
COM'L.
S
L
16
16
70
50
13
13
70
50
-
-
MIL.
S
90
290
85
290
80
290
L
90
250
85
250
80
250
S
90
240
85
240
-
-
L
90
210
85
210
-
-
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
-
-
Version
COM'L.
= SEMl~ VIH
MIL.
390
330
Full Standby Current
(80th Ports - All
80th Ports GEL and
GER ~ Vee· 0.2V
CMOS Level Inputs)
VIN ~ Vee· 0.2V or
COM'L.
VIN::; 0.2V, f = 0(4)
SEMR = SEMl~ Vee· 0.2V
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
One Port CElor
GER ~ Vee· O.2V
S
85
260
80
260
75
260
CMOS Level Inputs)
SEMR = SEMl~ Vee· 0.2V
COM'L.
VIN ~ Vee· 0.2V or
VIN::; 0.2V
L
S
85
85
215
220
80
80
215
220
75
215
-
-
Active Port Outputs Open,
f - fMAX(3)
L
85
180
80
180
-
-
MIL.
mA
mA
mA
mA
mA
2740 tbl 08
NOTES:
1. X in part numbers indicates power rating (8 or L)
2. Vcc = 5V, TA = +25°C.
3. At f = fMAx, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1ftRc, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.14
6
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = O.2V, VHC = VCC - O.2V)
Symbol
Parameter
Test Condition
VOR
Vcc for Data Retention
Vcc = 2V
IceoR
Data Retention Current
CE~ VHC
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
VIN
~
VHC or::; VLC
Min.
I MIL.
I COM'L.
Typ.(1)
Max.
2.0
-
-
100
4000
-
100
1500
-
0
tRC<2)
Unit
-
V
!lA
-
ns
-
ns
NOTES:
1. TA = +25°C, Vcc = 2V
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not tested.
2740 Ibl 09
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VOR ~ 2V
VCC
CE
~._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
711/7II/:V1H
VOR
\.
I
~\\\\\\\\\\\\\
2740 drw 04
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
5ns Max.
Input Rise/Fall Times
1.5V
Input Timing Reference Levels
1.5V
Output Reference Levels
See Figures 1 & 2
Output Load
2740tbl10
SV
1250n
DATAoUT
1
167n
'8USV~ 1.73V
rm
3OpF
DATAoUT-....--...
77sn
•
5pF*
2740 drw 06
2740 drw05
* Including scope and jig.
Figure 1. Equivalent Output Load
Figure 2. Output Load
(for tLZ, tHz, twz, tow)
6.14
7
IDT7024S/L
HIGH-SPEED 4K
x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
Symbol
IDT7024X25
COM'L ONLY
Min.
Max.
Parameter
IDT7024X30
COM'L ONLY
Min.
Max.
IDT7024X35
Min.
Max.
Unit
READ CYCLE
tAC
Read Cycle Time
25
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
-
- 30
-
35
-
-
-
-
30
30
30
15
-
35
35
35
20
ns
-
3
3
-
3
-
ns
tASE
Byte Enable Access Time(3)
-
tAOE
Output Enable Access Time
-:::::i: :;: :.: 13
:::::::::?5
::-:-:(:.::25
"'::'::\:.25
ns
ns
ns
ns
tOH
Output Hold from Address Change
3 : : : : ; ::::::.-
tLZ
Output Low Z Time(1, 2)
3:·:::::)::
tHZ
Output High Z Time\l, £)
"'i::}::
15
-
15
-
15
ns
tpu
Chip Enable to Power Up Time(2)
9::::'::::::::
-
0
-
0
-
ns
3
ns
tPD
Chip Disable to Power Down Time(2)
:.;(:::.:
50
-
50
-
50
ns
tsoP
Semaphore Flag Update Pulse (~or 8m)
':1:2::·::::
-
15
-
15
-
ns
Parameter
Symbol
IDT7024X45
IDT7024X55
Min.
Min.
Max.
Max.
IDT7024X70
MIL ONLY
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
-
55
-
70
-
ns
tAA
Address Access Ti me
-
-
55
30
-
70
70
70
ns
-
55
.55
35
ns
-
ns
30
ns
tACE
Chip Enable Access Time(3)
-
tASE
Byte Enable Access Time(3)
-
45
45
45
25
-
3
5
-
-
3
5
20
-
25
-
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low Z Time(1, 2)
3
5
tHZ
Output High Z Time(1, 2)
-
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
-
ns
tPD
Chip Disable to Power Down Time(2)
-
50
-
50
-
50
ns
tsoP
Semaphore Flag Update Pulse (DE or seJ)
15
-
15
-
15
-
NOTES:
1.
2.
3.
4.
ns
ns
0
ns
2740lblll
Transition is measured ±500mV from low or high impedance voltage with load (figures 1 and 2).
This parameter is guaranteed but not tested.
To access RAM, CE' = L, DB or rn = L, ~ = H.
X in part numbers indicates power rating (5 or L).
6.14
8
ID17024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
~-------------------- tRC
ADDR
~tABE (4)
- - - " " " " r - r - r -.... I
_ _-I~
UB, LB
I
I
I
j..-tLZ(1)
VALID DATA(4)
DATAoUT
BUSYOUT
tBDD(3,4)
2740 drw 07
NOTES:
1. Timing depends on which signal is asserted last, rn=, ct:, rn, or DB.
2. Timing depends on which signal is de-asserted firs ct:, OE", rn, or DB.
3. tSDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
l3(JS'( has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last lASE, lAOE, lACE, tM or tSDD.
5.
~=H.
TIMING OF POWER-UP POWER-DOWN
2740 drw 08
6.14
9
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
Symbol
IDT7024X25
COM'L ONLY
Max.
Min.
Parameter
IDT7024X30
COM'L ONLY
Min.
Max.
IDT7024X35
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tEW
Chip Enable to End of Write(3)
tAW
Address Valid to End of Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End of Write
25
20
20
0
20
::):m
1:(:'::Si.
I<:;{~.
[:::::/:;::.....
o ,: : i:::::;:::
15:::::: 1:::::::I:.:.::,.
15
I
Timel!,~}
tHZ
Output High Z
tDH
Data Hold Time (4)
twz
Write Enable to Output in High
tow
Output Active from End of Write(1, 2, 4)
tSWRD
~ Flag Write to Read Time
p:'::;;. . :
H:r·:·:·:··
tsps
SEM Flag Contention Window
10
O:tt t -
zt 1 , ~J
.7'1/':
15
-
-
IDT7024X45
Symbol
Parameter
Min.
Max.
30
25
25
0
25
0
20
0
0
10
10
-
35
30
30
0
30
0
25
15
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
15
ns
0
-
ns
15
-
15
ns
-
0
-
ns
IDT7024X55
Min.
-
Max.
10
10
IDT7024X70
MIL. ONLY
Min.
Max.
ns
ns
ns
Unit
WRITE CYCLE
-
55
45
45
0
40
0
30
-
70
50
50
0
50
0
40
-
ns
30
ns
tAW
Address Valid to End of Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End of Write
45
40
40
0
35
0
25
tHZ
Output High Z Time(1, 2)
-
20
-
25
-
tDH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High Z(1, 2)
-
20
-
25
-
30
ns
0
-
0
10
-
ns
twc
Write Cycle Time
tEW
Chip Enable to End of Write(3)
tow
Output Active from End of Write(1, 2, 4)
tSWRD
~ Flag Write to Read Time
0
10
-
tsps
SEM Flag Contention Window
10
-
NOTES:
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
2740tbl12
1.
2.
3.
4.
Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
This parameter is guaranteed but not tested.
To access RAM, IT = L, US or [B = L, ~ = H. To access semaphore, CE = H and ~ = L. Either condition must be valid for the entire tEW time.
The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. X in part numbers indicates power rating (S or L).
6.14
10
IDTI024S/L
HIGH-SPEED 4K X 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,3,5,8)
twc
ADDRESS
~
~
, ]r-
I
tHZ
f
tAW
""'-
'I
I
US or LS
I
twp(2)
4-tAS(6)
")
r.-- t wZ..:=:::I
(4)
4-,-tow
\I
V
1\
,1\
~I"
(4)
\
J
--------------------------~k~---------------·~~~----------------tow
DATAIN
tWR(7)
~
\.
DATAoUT
'f
tOH
2740 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE, UB, LB CONTROLLED TIMING(1,3,5,8)
,
twc
ADDRESS
\
j~
Jt
,
tAW
~r~tAS6)
US or LS
,
j'_... WR(7)
tEW(2)
J
-
. Rm
------------------cF
tow
DATAIN
1114
tOH
J~2740 drw 10
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
Rflil must be high during all address transitions.
,'
'
A write occurs during the overlap (tEw or twp) of a low UB' or
and a low CE and a low RIW for memory array writing cycle.
twR is measured from the earlier of CE or RIW (or SE'fJ or RIW) going high to the end of write cycle.
During this period, the 1/0 pins are in the output state and input signals must not be applied.
If the CE or SE'fJ low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
Timing depends on which enable signal is asserted last, CE, RIW or byte control.
Timing depends on which enable signal Is de-asserted first, CE, RIW or byte control.
If DE' is low during RIW controlled write cycle, the write pulse width must be the larger of twP or (twz + tow) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tow. If OE' is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
m
6.14
11
IDT7024S/L
HIGH-SPEED 4K X 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao - A2.
VALID ADDRESS
DATA 0
------~.-~tAOE
2740 drw 11
NOTE:
1. CE = H for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
AOA-A2A
SIDE(2) "A"
MATCH
X
Rfih
SEMA
Aos-A2s
SIDE (2) "8"
RJWs
SEMs
NOTES:
1. DaR = DOL = L, CE"R = CEl = H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "S" is the opposite port from "A".
3. This parameter is measured from RiWA or SEMA going high to RiWB or SEMB going high.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is not guarantee which side will obtain the flag.
6.14
12
1DT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7024X25
COM'L ONLY
Max.
Min.
Parameter
BUSY TIMING (MiS
IDT7024X30
_COM'L ONLY
Min.
Max.
BUSY Access Time from Address Match
-
30
BUSY Disable Time from Address Not Matched
-
25
·/:20
-
tBDA
-
tBAC
BUSY Access Time from Chip Low
BUSY Disable Time from Chip High
:):.:20
:,)('17
-
tBDC
-
25
25
20
-
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY' Disable to Valid
5 ."", 1/:·- ,::::Note 3
':::::':;'!:::
Data(3)
=L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSy(5)
tWDD
Write Pulse to Data Delay(1)
tODD
Write Data Valid to Read Data Delay(1)
0:,,:·····
-
17/,1
-
.42:"':.
-
Svmbol
Parameter
Min.
-
tBDC
tAPS
Arbitration Priority Set-up Time(2)
5
tBDD
BUSY Disable to Valid Data(3)
-
tBAC
BUSY TIMING (MiS
Unit
5
0
20
Note 3
-
-
-
35
ns
30
30
25
ns
5
-
ns
ns
-
ns
Note 3
ns
0
25
-
ns
-
60
ns
45
ns
ns
50
-
55
-
40
Max.
IDT7024X55
Min.
Max.
IDT7024X70
MIL ONLY
Min.
Max.
Unit
=H)
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
tBDA
-
35
IDT7024X45
tBAA
Max.
(:c·
PORT-TO-PORT DELAY TIMING
BUSY TIMING (MiS
Min.
=H)
tBAA
BUSY TIMING (MiS
IDT7024X35
-
35
30
30
25
-
5
Note 3
-
-
45
40
40
35
-
45
40
40
35
-
5
-
-
Note 3
Note 3
ns
ns
ns
ns
ns
ns
=L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSy(5)
0
25
-
-
0
25
0
25
-
ns
-
-
-
80
65
-
95
80
ns
ns
PORT-TO-PORT DELAY TIMING
two 0
Write Pulse to Data Delay(1)
toDD
Write Data Valid to Read Data Delay(1)
-
70
55
ns
NOTES:
2740tbl13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (MIS = H)" or "Timing Waveform
of Write With Port-To-Port Delay (MlS=L)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tODD - tOW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "x" is part numbers indicates power rating (S or L).
6.14
13
IDTI024S/L
HIGH-SPEED 4K
x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSy(2) (MIS
ADDRR
=H)
twc
==>K
)
MATCH
K
twp
~
RiWR
K
/
V
-.-tow
) (
DATAIN R
*H
VALID
tAPS (1)
) K~
ADDR L
MATCH
~tBDA ~
"'---"
BUSYL
DATAOUTL
tsoo
twoo
)
toOO(3)
2740 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEl = CER = L
3. DE = L for the reading port.
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1,2) (MIS
ADDRR
E
=L)
twe
=>k
)~
MATCH
~
RJWR
twp
,
/
V
~tow
)
DATAIN R
K
>r<"
VALID
MATCH
ADDRL
twoo
)
DATAOUTL
tODD
NOTES:
1. BUSY input equals H for the writing port.
2. CEl = CER = L
E
2740 drw 14
TIMING WAVEFORM OF SLAVE WRITE (MIS = L)
~~--------twP----~----~
8~~~W_B~
2740 drw 15
6.14
14
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MIS
ADDR "A"
and "B"
~
= H)
~
ADDRESSES MATCH
~---------~
tAPS(~-~-t
CE"A"
CE"B"
~BAC ---j
i--tBDC
~
BUSY"B'
~
, _ _
A
2740drw 16
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
tMA
1-
~~_tBDA
BUSY"B"
2740 drw 17
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
IDT7024X25
COM'LONLY
Min.
Max.
Parameter
IDT7024X30
COM'L ONLY
Min.
Max.
IDT7024X35
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
a
tiNS
Interrupt Set Time
7::::~::::
tlNR
Interrupt Reset Time
Symbol
.;;:/F
Parameter
,,7:('
I::::/':~
20
20
a
a
-
-
25
25
IDT7024X45
IDT7024X55
Min.
Min.
Max.
Max.
a
a
-
-
ns
-
ns
30
ns
30
ns
IDT7024X70
MIL. ONLY
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
Write Recovery Time
a
-
a
a
-
a
a
-
ns
tWR
tiNS
Interrupt Set Time
-
35
40
ns
interrupt Reset Time
-
35
-
50
tlNR
-
NOTE:
1. "x" in part numbers indicates power rating (S or L).
40
50
ns
ns
27401bl14
6.14
15
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~---------------------twc------------------~
ADDR'A'
CE'A'
INT'B'
tlNS(')
"1-----------------------2740 drw 18
~-----------------t RC -----------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR'B'
CE'B'
DE'B'
"NR(') : }_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..--_ __
INT'B'
2740 drw 19
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port US" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Left Port
Right Port
RtWL
CE'L
O£L AOL·A11L lNiL
L
L
X
FFF
X
X
X
X
X
X
X
X
X
L
L
FFE
RtWR
CE'R
X
X
X
O'ER AOR·A11R lNTR
L(2)
X
X
X
Ll « « « « « « «
I ~
!/02L
!/03L
IJ04L
!/05L
GND
!/OSL
!/OlL
Vee
GND
!/OOR
!/01R
!/02R
Vee
!/03R
!/04R
!/05R
!/OSR
!DT7006
J68-1
L68-1
A5L
A4L
A3L
A2L
A1L
AOL
!NTL
BUSYL
GND
MIS
BUSYR
!NTR
AOR
A1R
A2R
A3R
A4R
2739 drw 02
LCC/PLCC/FLATPACK
TOP VIEW
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
6.15
2
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
51
50
11
A5l
53
10
55
09
41
GND
38
39
BUSYR
36
A1R
INTR
37
AOR
35
32
30
28
67
CEl
IIOll
23
SEMR
CER
20
21
--
OER
3
II02l
5
II04l
4
6
II07l
II05l
II06l
B
C
D
11
GND
Vee
,E
15
13
Vee
II01R
10
8
II03l
Pin 1
Designator
9
7
GND
12
18
II04R
16
14
A13R
22
NC
1
A12R
25
NC
66
2
•
24
RiWl
Al0R
27
GND
64
IIOOl
68
26
62
A8R
29
AllR
IDT7006
16K x 8 DPR
IN 68-PIN PGA
G68-1
A6R
31
A9R
A13L
A5R
33
AlA
A12l
SEMl
34
A4R
A2R
60
GEL
A3R
AlOl
NC
65
02
43
INTl
40
MIS
58
Vee
63
03
45
All
42
BUSYl
56
61
04
AOl
A8l
Alll
06
05
47
A3l
44
46
A2l
54
59
07
A6l
A9l
57
08
49
52
All
48
A4l
RiWR
19
II07R
NC
17
IIOOR
II02R
II03R
II05R
II06R
F
G
H
J
K
L
2739 drw 03
sa-PIN PGA
TOP VIEW
PIN NAMES
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
Left Port
Right Port
GEL
CER
Names
RlWl
RlWR
Chip Enable
ReadlWrite Enable
DEL
AOl-A13l
DER
AOR-A13R
Address
Output Enable
IIOOl-II07L
1I00R-II07R
SEMl
SEMR
Data InpuVOutput
Semaphore Enable
INTl
INTR
BUSYR
Busy Flag
BOSYl
Interrupt Flag
MIS
Master or Slave Select
Vee
Power
Ground
GND
2739 tbl18
6.15
3
IDT7006S/L
HIGH-SPEED 16K X 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
RIW
O""E"
sal
1/00-7
H
X
X
H
Hi-Z
L
L
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
Hi-Z
Mode
Deselected: Power Down
Write to Memory
Read Memory
Outputs Disabled
NOTE:
1. AOL-A13L;tAoR-A13R
2739 tbl 01
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Outputs
Inputs
CE
RIW
O""E"
SEM
1/00-7
H
H
L
L
DATAoUT
Read Data in Semaphore Flag
X
L
DATAIN
Write DINO into Semaphore Clag
X
X
L
H
L
.-r .
Mode
-
Not Allowed
2739tbl02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
with Respect
toGND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
Commercial
+25°C, f;"
Parameter(1)
Vee
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V±10%
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0(2)
V
VIL
Input Low Voltage
-0.5(1)
0.8
V
Symbol
NOTE:
1. VIL2 -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
-
2739 tbl 06
1.0MHz)
Max.
Unit
CIN
Input Capacitance
VIN = OV
11
pF
COUT
Output
Capacitance
VOUT = OV
11
pF
Symbol
GND
-55°C to + 125°C
2739 tbl 05
NOTE:
2739 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vee + O.SV.
CAPACITANCE (TA =
Ambient
Temperature
Conditions
NOTE:
2739 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
6.15
4
ID17006S/L
HIGH·SPEED 16K x 8 DUAL·PORTSTATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V ± 10%)
10170065
Parameter
Symbol
Test Conditions
Min.
I017006L
Max.
Min.
Max.
Unit
IILlI
Input Leakage Current(5)
Vee = 5.5V, VIN = OV to Vee
-
10
-
5
j.tA
Illal
Output Leakage Current
CE = VIH, VOUT = OV to Vee
-
10
5
j.tA
VOL
Output Low Voltage
IOL= 4rnA
-
0.4
-
0.4
V
VOH
Output High Voltage
IOH = ·4rnA
2.4
-
2.4
-
V
2739 tbl 07
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vee = 5.0V ± 10%)
Symbol
lee
Parameter
Dynamic Operating
Current
(Both Ports Active)
1861
CE $ Vll, Outputs Open
S"EM<=: VIH
f = fMAX(3)
Version
MIL.
S
L
-
COM'L.
S
L
160
160
-
-
COM'L.
S
L
20
20
70
50
Standby Current
CEl or CER<=: VIH
MIL.
S
(One Port - TTL
Active Port Outputs Open
f '" fMAX(3)
L
-
-
S
95
240
L
95
210
S
L
S
L
-
-
1.0
0.2
15
5
-
COM'L.
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Full Standby Current
(One Port-All
CMOS Level Inputs)
Both Ports CE:l and
CER <=: Vee· 0.2V
VIN <=: Vee· 0.2V or
VIN $ 0.2V, f '" 0(4)
SEMR = SBv1'L<=: Vee· O.2V
One Port CEl or
CER <=: Vee· 0.2V
SEMR = SEMl<=: Vee· 0.2V
VIN <=: Vee· 0.2V or
VIN $ 0.2V
Active Port Outputs Open,
f = fMAX(3)
MIL.
COM'L.
MIL.
COM'L.
rnA
340
290
S
L
SEYfR = SEKifl> VIH
1864
-
MIL.
Level Inputs)
1863
7006X35
COM'LONLY
Typ.!2) Max. Unl
CER = CEl<=: VIH
S"EMR = SEYfl<=: VIH
f = fMAX(3)
Standby Current
(Both Ports - TTL
Level Inputs)
1862
Test
Condition
S
L
-
-
S
90
220
L
90
180
rnA
rnA
rnA
rnA
NOTES:
2739 tbl 08
1. X in part numbers indicates power rating (S or L)
2. Vec = 5V, TA = +25°e.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRc, and using "Ae Test Conditions·
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. At Vcc75,2.0V input leakages are undefined.
6.15
5
IDT7006S/L
HIGH·SPEED 16K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc = 5.0V ± 10%)
7006X45
Symbol
Icc
1881
1882
Parameter
Test
Condition
GE::; Vll, Outputs Open
Dynamic Operating
Current
~~VIH
(Both Ports Active)
f = fMAX(3)
Typ.(2)
Max.
Typ.(2)
MIL.
S
L
155
155
400
340
150
150
395
335
140
140
COM'L.
S
L
155
155
340
290
150
150
335
285
-
Version
390
330
-
-
CEl = CER~ VIH
SEMR = SEMl~ VIH
MIL.
S
L
16
16
85
65
13
13
85
65
10
10
85
65
Level Inputs)
f = fMAX(3)
COM'L.
S
L
-
-
70
50
13
13
70
50
-
-
S
90
290
85
290
80
290
L
90
250
85
250
80
250
S
90
240
85
240
-
-
L
90
210
85
210
-
-
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
S
L
1.0
0.2
15
5
1.0
0.2
15
5
-
-
S
85
260
80
260
75
260
Standby Current
CER or CEl~ VIH
(One Port-TIL
Active Port Outputs Open
f = fMAX(3)
MIL.
COM'L.
SEMR = ~l> VIH
1884
7006X70
MIL ONLY
Max. Typ.(2) Max. Unit
Standby Current
(Both Ports - TIL
Level Inputs)
1883
7006X55
Full Standby Current
(Both Ports - All
Both Ports GEL and
CER ~ Vee· 0.2V
CMOS Level Inputs)
VIN ~ Vee· 0.2V or
COM'L.
VIN::; 0.2V, f = 0(4)
~R = SEMl~ Vee· 0.2V
One Port CEl or
MIL.
CER ~ Vee· 0.2V
SEMR = ~l~ Vee· 0.2V
Full Standby Current
(One Port-All
CMOS Level Inputs)
VIN ~ Vee· 0.2V or
VIN::; 0.2V
Active Port Outputs Open,
f = fMAX(3)
MIL.
COM'L.
rnA
rnA
rnA
rnA
-
L
85
215
80
215
75
215
S
85
220
80
220
-
-
L
85
180
80
180
-
-
rnA
NOTES:
2739tbl08
1. X in part numbers indicates power rating (S or L)
2. Vcc = 5V, TA = +25°C.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.15
6
IDT7006S/L
HIGH·SPEED 16K x 8 DUAL·PORTSTATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLe - 0 2V , VHC - Vee - 0 2V)
Symbol
Parameter
Test Condition
VOR
Vcc for Data Retention
Vcc = 2V
ICCOR
Data Retention Current
CE'~ VHC
tCDR(3)
tR(3)
Chip Deselect to Data Retention Time
VIN
~
VHC or ~ VLC
I MIL.
I COM'L.
Min.
Typ.(1)
2.0
-
-
Unit
-
V
100
4000
~
100
1500
-
0
tRC(2)
Operation Recovery Time
Max.
-
NOTES:
ns
ns
2739tbl09
1. TA = +25°e, Vee
c
2V
2. tAc = Read Cycle Time
3. This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vce
VOR
~
2V
\~__________
V_O_R__________-JI
CE 7IZlllZZVIH
2739 drw 04
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
5ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 & 2
2739tbl10
DATAoUT
1670
5V
BUSV~1.73V
1
1250n
30PP
Jf\JT
DATAoUT-...--....
2739awOS
775f!
5pF*
Figure 1. Equivalent Output Load
2739 drw 06
Figure 2. Output Load
(for tLZ, tHZ, twz, tow)
• Including scope and jig.
6.15
7
1DT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7006X35
COM'L ONLY
Symbol
Parameter
Min.
Max.
Unit
35
3
3
0
15
35
35
20
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low Z Time(1, 2)
tHZ
Output High Z Time(1, 2)
tpu
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
tsoP
Semaphore Flag Update Pulse (OE or SEM)
Symbol
Parameter
IDT7006X45
IDT7006X55
Min.
Max.
Min.
Max.
55
3
55
55
30
-
ns
ns
ns
-
ns
15
ns
-
ns
50
-
ns
ns
ns
IDT7006X70
MIL ONLY
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
-
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
3
45
45
25
-
tLZ
Output Low Z Time(1,~)
5
-
5
-
tHZ
Output High Z Time(1, 2)
-
20
-
tpu
Chip Enable to Power Up Time l ")
-
tPD
Chip Disable to Power Down Time(2)
tsoP
Semaphore Flag Update Pulse (OE or SEM)
0
15
25
70
3
5
-
70
70
35
30
0
-
0
-
ns
50
-
50
-
15
-
15
50
-
ns
-
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = L, SEM = H.
4. X in part numbers indicates power rating (5 or L).
6.15
-
ns
ns
ns
ns
ns
ns
ns
ns
2739 tblll
8
1DT7006S/L
HIGH·SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
...................................--- tRC - -.............................................~
~
ADDR
DATAoUT
VALID DAT.A!4)
tBOO(3,4)
2739 drw07
NOTES:
1. Timing depends on which signal is asserted last, OE' or CE.
2. Timing depends on which signal is de-asserted first CE or OE'.
3. tSDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tASE, tAOE, tACE, tM or tSDD.
5. SDVl = H.
TIMING OF POWER-UP POWER-DOWN
:
ISB
~tpU1,
..J1'
2739 drw08
6.15
9
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
IOTIOO6X35
Symbol
Parameter
Min.
Max.
Unit
WRITE CYCLE
ns
0
-
Data Valid to End of Write
25
-
ns
tHZ
Output High Z Timell, 1:')
-
15
ns
tDH
Data Hold Time(4)
0
-
ns
twz
Write Enable to Output in High Zp,
tow
twc
Write Cycle Time
35
tEW
Chip Enable to End of Write(3)
30
tAW
30
tAS
Address Valid to End of Write
Address Set-up Time (3)
twp
Write Pulse Width
30
tWR
Write Recovery Time
tDW
0
ns
ns
ns
ns
ns
-
15
ns
Output Active from End of Writel1, 2, 4)
0
--
ns
tSWRD
SEM Flag Write to Read Time
10
-
ns
tsps
SEM Flag Contention Window
10
-
ns
Symbol
2)
Parameter
IOTIOO6X45
IOTIOO6X55
Min.
Min.
Max.
Max.
IOTIOO6X70
MIL. ONLY
Min.
Max.
I Unit
WRITE CYCLE
twc
Write Cycle Time
45
-
55
-
70
-
ns
tEW
Chip Enable to End of Write(3)
40
-
45
-
50
-
ns
tAW
Address Valid to End of Write
40
-
45
-
50
-
ns
tAS
Address Set-up Time(3)
0
-
0
-
0
-
ns
twp
Write Pulse Width
35
-
40
-
50
-
ns
tWR
Write Recovery Time
0
-
0
0
Data Valid to End of Write
25
-
30
40
-
ns
tow
-
tHZ
-
20
-
25
-
30
ns
tDH
Output High Z Time(1, 2)
Data Hold Time (4)
0
-
0
-
twz
Write Enable to Output in High Zl1, 2)
-
20
-
25
tow
Output Active from End of Writel1, 2, 4)
0
-
0
-
tSWRD
SEM Flag Write to Read Time
10
10
-
tsps
SEM Flag Contention Window
10
-
10
-
10
ns
-
ns
30
ns
0
-
ns
10
-
ns
-
ns
0
-
NOTES:
2739 tbl12
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = L, SEM = H. To access semaphore, CE = Hand SEM = L. Either condition must be valid for the entire lEw time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. X in part numbers indicates power rating (S or L).
6.15
10
IDTI006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,3,5,8)
,
twc
---.
ADDRESS
~r
]~
_1\
i
I
tHZ
tAW
CE
J
tWp(2)
i'--tAS(6)
tWR(7)
~r
RlW
]r
~twz
DATAoUT
~tow
V
(4)
'I
1\
~I~
,
J
-------------------------------------------------~K~---------------~~~----------------tow
DATAIN
(4)
tOH
2739 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,3,5,8)
twc
ADDRESS ~r
~~
JI\
----1
tAW
_tAst 6)
\1
]
WR(7)
tEW(2)
-----------------------------{~~-------------~--~~----------------tow
DATAIN
.. '..
f4-
tOH
2739 drw 10
NOTES:
1. RfiN must be high during all address transitions.
2. A write occurs during the overlap (tEw or twp) of a low CE and a low Rm for memory array writing cycle.
3. twR is measured from the earlier of CE or Rm (or SEM or Rm) going high to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RtVllow transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE, Rm, or byte control.
7. Timing depends on which enable signal is de-asserted first, CE, Rm, or byte control.
8. It Of is low during RtVl controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data to
be placed on the bus tor the required tow. It OE is high during an RtVl controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
6.15
11
IDT7006S/L
HIGH-SPEED 16K
x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
SEM
DATAo---+---+-~
PJw ---+-----.
2739 drw 11
NOTE:
1. C'E" = H for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
AOA-A2A
SIDE (2) "A"
MATCH
X
pjifh
Ell
SEMA
Aos-A2S
SIDE (2)"8"
RlWs
SEMs
NOTES:
1. DOR = DOL = L, crR = C'E"L = H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "8" is the opposite port from "A".
3. This parameter is measured from R1WA or st:fJA going high to R1WB or ~B going high.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is not guarantee which side will obtain the flag.
6.15
12
IDTI006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7006X35
COM'L ONLY
Symbol
Parameter
BUSY TIMING (MIS
Min.
Max.
Unit
-
35
ns
30
ns
-
30
ns
=H)
tBOC
m:JSV Access Time from Address Match
BUSY' Disable Time from Address Not Matched
BUSY' Access Time from Chip Enable Low
BUSV Disable Time from Chip Enable High
-
25
ns
tAPS
Arbitration Priority Set-up Time(2)
5
-
ns
tBOD
~ Disable to Valid Data(3)
-
tBM
tBOA
tBAC
BUSY TIMING (MIS
Note 3
ns
=L)
tWB
BUSY' Input to Write(4)
tWH
Write Hold After ~5)
0
-
ns
25
-
ns
-
60
ns
45
ns
PORT·TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
toDD
Write Data Valid to Read Data Delay(1)
Symbol
Parameter
BUSY TIMING (MiS
IDT7006X45
IDT7006X55
Min.
Min.
Max.
30
tBAC
-
tBOC
~ Disable Time from Chip Enable High
-
tAPS
Arbitration Priority Set-up Time(2)
5
tBDD
m:JSV Disable to Valid Data(3)
-
tBOA
BUSY TIMING (MIS
Unit
=H)
m:JSV Access Time from Address Match
BUSY' Disable Time from Address Not Matched
m:JSV Access Time from Chip Enable Low
tBM
Max.
IDT7006X70
MIL. ONLY
Min.
Max.
25
-
-
5
35
30
Note 3
-
45
ns
40
ns
40
-
40
ns
35
-
35
ns
-
5
-
ns
45
40
Note 3
-
Note 3
ns
=L)
tWB
~ Input to Write(4)
tWH
Write Hold After IDJSV{5)
25
-
25
-
-
70
-
80
55
-
65
0
0
-
ns
25
-
95
ns
80
ns
0
ns
PORT·TO-PORT DELAY TIMING
MOD
Write Pulse to Data Delay(1)
toDD
Write Data Valid to Read Data Delay(1)
NOTES:
2739tbl13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BOSV (MIS = H)" or "Timing Waveform
of Write With Port-To· Port Delay (MlS=L}".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tODD - tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "x' is part numbers indicates power rating (S or L).
6.15
13
IDT7006S/L
HIGH·SPEED 16K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSy(2) (MIS
=H)
twc
ADDRR
~(
MATCH
)"
twp
)~
~I\.
RiWR
+---tow
)(
DATAIN R
VALID
>KH
tAPS(1)
)(~
ADDRL
MATCH
\
BUSY L
'-'BDAF'BDD
'~
twoo
DATAOUTL
t 000(3)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CE:L = CE:R = L
3. 01: = L for the reading port.
)E
2739 drw 13
=
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1,2){MiS L)
~---------------twc--------------~
MATCH
ADDRR
~--------twP--------~
RlWR
tow'--+l+~
VALID
DATAIN R
MATCH
ADDRL
~--------+----twoo------------~
DATAoUTL
1 4 - - - - - t ooo------~
NOTES:
1. BUSY input equals H for the writing port.
2.
2739 drw 14
crL = CER = L
TIMING WAVEFORM OF SLAVE WRITE (MIS
= L)
~~-------twP----~----"~
Bu:~~_B~2739 drw 15
6.15
14
IDT7006S/L
HIGH·SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MIS
= H)
V--
ADDR
"A" ~
and "8"
~_ _ _ _ _ _ _A_D_D_R_E_S_S_E_S_M_A_T_C_H_ _ _ _ _ _ _---,/,----
CE"A"
_tAPS(~2)
~
I
-------r-------------tBAt:--j
~tBD~ • _ _
~
--A'
CE"8"
BUSY "8"
2739 drw 16
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDRESS "N"
MATCHING ADDRESS "N"
ADDR"8"
t BAA
BUSY '8"
={_______
t_8_DA_l
2739 drw 17
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7006X35
COM'L ONLY
Parameter
Symbol
Min.
Max.
Unit
-
ns
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
a
a
tiNS
Interrupt Set Time
-
30
ns
tlNR
Interrupt Reset Time
-
30
ns
Parameter
Symbol
IDT7006X45
IDT7006X55
Min.
Max.
Min.
a
a
-
a
a
-
-
35
-
40
Max.
ns
IDT7006X70
MIL. ONLY
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
NOTE:
1. "x" in part numbers indicates power rating (S or L).
35
40
a
a
-
ns
-
ns
-
50
ns
50
ns
2739 tbl14
6.15
15
IDTI006S/L
HIGH·SPEED 16K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~---------------twc--------------~
ADDR'A'
tIN5(3)"1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
INT'B'
2739 drw 18
~---------------tRc--------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR'B'
tINR(3)}..--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
INT'B'
2739 drw 19
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "S" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. TIming depends on which enable signal is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Right Port
Left Port
RIWl
CEl
L
L
X
3FFF
X
X
X
X
X
X
X
X
X
L
L
3FFE
OER AOR-A13R TNfR
L(2)
X
X
Function
RIWR
CER
X
X
X
X
Ll;j)
X
L
L
3FFF
H(3)
L
L
X
3FFE
X
Set Left INTL Flag
Hl~)
X
X
X
X
X
Reset Left TNTL Flag
OEl AOl-A13L INTL
NOTES:
1. Assumes SUSYL = BUSYR = H.
2. If BOSYL = L, then no change.
3. If BUSYR = L, then no change.
Set Right TNTR Flag
Reset Right TNTR Flag
2739 tbl15
6.15
16
1DT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
ADDRESS BUSY
Outputs
Inputs
AOl-A13l
AOR-A13R
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSVl(1) BUSVR(1)
CEl
CER
X
NO MATCH
H
H
Normal
H
X
X
Function
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(~)
NOTES:
2739 tblt6
1. Pins BOSYL and BOSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BOSYx outputs on the
IDT7006 are push pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAps is not met, either BOSY"L or BOSY"R = Low will result. BOSY"L and BOSY"R outputs cannot be low
simultaneouly.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE III -
EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
00 - 07 Left
Status
00 - 07 Right
Semaphore free
No Action
1
1
Left Port Writes "0" to Semaphore
a
a
1
Left port has semaphore token
1
No change. Right side has no write access to semaphore
a
a
No change. Left port has no write access to semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
1
Right port obtains semaphore token
Right Port Writes "1" to Semaphore
a
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
a
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
a
1
Right port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2739tbl17
FUNCTIONAL DESCRIPTION
The IOT7006 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IOT7006 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is set when the right port
writes to memory location 3FFE (HEX). The left port clears the
interrupt by reading address location 3FFE. Likewise, the
right port interrupt flag (INTR) is set when the left port writes to
memory location 3FFF (HEX) and to clear the interrupt flag
(INTR), the right port must read the memory location 3FFF.
The message (8 bits) at 3FFE or 3FFF is user-defined. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Table 1 for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
6.15
17
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
r--
I
T
MASTER
CE
Dual Port
RAM
Busy (L) Busy (R)
SLAVE
CE
Dual Port
RAM
Busy (L) Busy (R)
a:
,-w
0
0
()
w
0
~
I
MASTER
Dual Port
RAM
Busy (L)
Busy (L)
SLAVE
CE
Dual Port
RAM
Busy (R)
Busy (L)
1
CE
Busy (R)
Busy (R)
I
2739 drw 20
Figure 3. Busy and chip enable routing for both width and depth expansion with 1DT7006 RAMs.
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the lOT 7006 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IOT7006 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IOT7006 RAM the busy pin is
an output if the part is used as a master (MIS pin = H), and the
busy pin is an input if the part used as a slave (MIS pin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a masterlslave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
can be initiated with the R/W signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
SEMAPHORES
The IOT7006 is an extremely fast dual-port 16K x 8 CMOS
static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the dual-port RAM to claim a privilege
over the other processor for functions defined by the system
designer's software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a
portion of the dual-port RAM or any other shared resource.
The dual-port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in fu nction to standard
CMOS static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous REAOIWRITE of,
a non-semaphore location. Semaphoresareprotected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the dual-port RAM. These devices have an automatic
power-down feature controlled by CE, the dual-port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IOT7006 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IOT7006s hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IOT7006 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
6.15
18
r.II
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the dual-port RAM. These latches can be used
to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphores provide a
hardware assist for a use assignment method called "Token
Passing Allocation." In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in
use. If the left processorwants to use this resource, it requests
the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful
it proceeds to assume control over the shared resource. If it
was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and
is using the shared resource. The left processor can then
either repeatedly request that semaphore's status or remove
its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the
set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7006 in a
separate memory space from the dual-port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AD -A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
6.15
activ~. This ~erves to disallow the semaphore from changing
state In the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or
OE) to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in orderto guarantee that no system level contention will
occur. A processor requests access to shared resources by
attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the rightside during subsequent read. Had
a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the ~ame location. The reason for this is easily understood by
I~oklng at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latchis written to a one. From this it is
easy to understand that, if a semaphore is requested and the
proces~or which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
res.olve this problem ..If simultaneous requests are made, the
logiC guarantees that only one side receives the token. If one
s~de is earlier than the other in making the request, the first
Side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resou~ce i~ secure. As with any powerful programming
technique, If semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
19
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7006's dual-port
RAM. Say the 16K x 8 RAM was to be divided into two 8K x
8 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
dual-port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 8K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 8K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of dual-port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the dual-port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the liD device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the liD devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT" state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structu reo The other processor then reads and
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processorto come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
R PORT
b..EQBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE4-____~~
L--....L...._ _ _ _. . .
READ
SEMAPHORE
READ
2739 drw 21
Figure 4. IDT7006 Semaphore Logic
6.15
20
(;)
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
• True dual-ported memory cells which allow simultaneous
reads of the same memory location
• High-speed access
- Military: 35/45/55/70ns (max.)
- Commercial: 25/30/35/45/55ns (max.)
• Low-power operation
- IOT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IOT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IOT7025 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
IDT7025S/L
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, quad flatpack and PLCC
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IOT7025 is a high-speed 8K x 16 dual-port static RAM.
The IOT7025 is designed to be used as a stand-alone 128K-
FUNCTIONAL BLOCK DIAGRAM
.
RIWl
UBl
A12l
Al0l
1
··
-
-
I
LBl
CEl
OEl
r
\.
~
1
-..J
'--.r
-J
--
"--
I/0Sl -1/01Sl
I--
COL
SEL
COLUMN
1/0
I--
I/00l -1/01L
'---
A9l
AOl
·
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSYoutputs
and INT outputs
are non-tri-stated
push-pull.
r-<-
~
W 7j~
I
A
ROW
V
SELECT
"-
"
A12l
AOl
CEl
OEl
UBl
LBl
~
~
A
"-
~r
··
I
CEMOS is a trademark of Integrated Device Technology, Inc.
BUSYR
"-
v
··
I
I/OOR-I/07R
L...-
I
'"
Al0R
I/OSR-I/01SR
COL
SEL
f--
A
A12R
ROW
SELECT
.
A9R
AOR
A12R
AOR
CER
OER
UBR
LBR
RlWR
SEMR
INTR
2683 drw01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology. Inc.
COLUMN
1/0
tW
MIS
··
f--
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
I
RlWl
SEMl
INTl
~~ L
MEMORY
ARRAY
v
RlWR
UBR
~
6.16
APRIL 1992
OSC104612
1
ID17025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
bit dual-port RAM or as a combination MASTERISLAVE dualport RAM for 32-bit-or-more word systems. Using the lOT
MASTERISLAVE dual-port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and liD pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CEMOSTM high-performance technology, these devices typically operate on only 750mW of
power at maximum access times as fast as 25ns. Low-power
(L) versions offer battery backup data retention capability with
typical power consumption of 500llW from a 2V battery.
The IDT7025 is packaged in a ceramic 84-pin PGA, an 84pin quad flatpack, and a PLCC. The military devices are processed 100% in compliance to the test methods of MIL-STD883, Method 5004.
PIN CONFIGURATIONS
1I00l
IfOsl
If010l
If011l
II012l
If013l
GNO
If014l
If015l
Vee
GNO
If OaR
I/01R
If02R
A7l
ASl
A5l
A4l
A3l
A2l
All
AOl
IOT7025
J84-1
F84-2
INTl
BUSYl
GNO
MIS
BUSYR
INTR
Vee
AOR
If03R
I/04R
I/05R
I/OSR
I/07R
IfOeR
A1R
A2R
A3R
A4R
A5R
ASR
2683 drw 02
PLCC/FLATPACK
TOP VIEW
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
6.16
2
IDTI025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
63
61
I/07L
66
64
I/010l
67
58
60
I/05l
59
62
I/08l
55
I/02l
I/04l
I/06l
56
I/03l
65
110m
69
54
IIOOl
50
UBl
45
46
A11l
LBl
47
CEl
53
GND
48
SEMl
49
I/01l
57
I/09l
51
OEl
44
A12l
72
41
75
76
79
81
32
IDT7025
G84-3
GND
82
84
Mis
28
INTA
07
A2A
7
I/07A
11
GND
23
12
GND
2
5
8
10
I/010A
I/013A
I/015A
RlWA
9
15
SEMA
14
17
20
A11A
22
A8A
BUSYA
24
A6A
4
6
I/012A
I/014A
OEA
LBA
CEA
A12A
A10A
A9A
A7A
A
B
C
D
E
F
G
H
J
K
L
18
19
02
A4A
I/011A
16
03
A3A
3
13
04
A1A
I/08A
-
05
25
A5A
UBA
06
A1L
27
26
I/09A
INTL
30
29
AOA
I/04A
1
I/06A
08
36
31
GND
Vee
I/02A
83
I/05A
A2L
34
AOL
80
I/03A
09
37
35
BUSYL
78
77
I/01R
33
Vee
74
GND
A4L
A3L
73
70
10
39
38
I/014L
I/OOA
A5l
A6L
110m
71
II015L
11
A8l
R/NL
68
I/013L
A7L
40
43
A9l
52
Vee
42
A10l
21
01
~
2683d rw03
Pin 1
Designator
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
84-PIN PGA
TOP VIEW
PIN NAMES
Left Port
Right Port
CEA
CEL
Names
Chip Enable
RlWL
RlWA
ReadIWrite Enable
OEL
OEA
Output Enable
AOL-A12L
AOA-A12A
Address
I/OOl - I/015L
I/OOA -I/015A
Data InpuVOutput
SEML
SEMA
Semaphore Enable
UBL
UBA
Upper Byte Select
LBL
LBA
Lower Byte Select
INTL
INTA
Interrupt Flag
BUSYL
BUSYA
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2683tbl18
6.16
3
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
outputs
CE
RIW
OE
UB
LB
SEM
1/08-15
1/00-7
H
X
X
X
X
H
Hi-Z
Hi-Z
X
X
X
H
H
H
Hi-Z
Hi-Z
Both Bytes Deselected: Power Down
L
L
X
L
H
H
DATAIN
Hi-Z
Write to Upper Byte Only
L
L
X
H
L
H
Hi-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
Hi-Z
L
H
L
H
L
H
Hi-Z
L
H
L
L
L
H
X
X
H
X
X
X
Mode
Deselected: Power Down
Read Upper Byte Only
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
Hi-Z
Hi-Z
Outputs Disabled
NOTE:
1. AOL-AI2L ;eAOR-AI2R
2683tbiOl
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RIW
OE
UB
LB
SEM
1/08-15
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
1/00-7
Mode
DATAoUT DATAoUT Read Data in Semaphore Flag
X
H
L
H
H
L
H
X
X
X
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
X
J-"
J-"
X
H
H
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
L
X
X
L
X
L
L
X
X
X
L
L
-
-
Not Allowed
Not Allowed
2683tbl02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
toGND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V ± 10%
2683 tbl 05
50
50
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
rnA
NOTE:
2683 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vee + O.SV.
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0(2)
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VIL2 -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vee + O.SV.
CAPACITANCE (TA =
Symbol
+25°C,
Parameter(1)
2683 tbl 06
f = 1.0MHz)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = OV
11
pF
COUT
Output
Capacitance
VOUT = OV
11
pF
NOTE:
2682 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
6.16
4
IDn025S/L
HIGH-SPEED 8K X 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V ± 10%)
IDT7025S
Param~ter
Symbol
Test Conditions
IILlI
Input Leakage Current(5)
IILol
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
Min.
= 5.5V, VIN = OV to Vee
CE = VIH, Your = OV to Vee
10:'" = 4mA
10H = -4mA
IDT7025L
Max.
Min.
Max.
Unit
-
10
-
5
~
-
10
-
5
~
-
0.4
-
0.4
V
2.4
-
2.4
-
Vee
V
2683 tbl 07
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vec = 5.0V ± 10%)
7025X25
COM'L ONLY
Typ.(2) Max.
Test
Symbol
Ice
1881
1882
1883
1884
Parameter
Condition
Dynamic Operating
Current
CE::; Vll, Outputs Open
SEM ~ VIH
(Both Ports Active)
f
= fMAX(3)
Standby Current
(Both Ports - TTL
CER = CEl~ VIH
SEMR = SEMl~ VIH
Level Inputs)
f
= fMAX(3)
Version
MIL.
COM'L.
MIL.
COM'L.
S
L
S
L
2\::::
.
:::::,:
170/:'::
~I}\
-
S
L
2!?,:;:::i ::::::::,50
25:':::::':
:):70
22
22
70
50
---:,,::.::t::::::
S
L
Level Inputs)
f = fMAX(3)
SEMR = SEMl~ VIH
COM'L.
S
L
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
MIL.
S
L
~~~~~~~:~~;
CMOS Level Inputs)
COM'L.
VIN ~ Vee - 0.2V or
VIN::; 0.2V, f = 0(4)
SEMR = SEMl~ Vee - 0.2V
S
L
1.0
Full Standby Current
(One Port-All
One Port CEl or
CER ~ Vee - 0.2V
S
L
CMOS Level Inputs)
SEMR = SEMl~Vee - 0.2V
COM'L.
VIN ~ Vee - 0.2V or
L
350
300
....... ':{}-
MIL.
S
165
165
:~r)-
S
L
CEl or CER~ VIH
Active Port Outputs Open
VIN::; 0.2V
Active Port Outputs Open,
f = fMAX(3)
360
9 :::::310
17
Standby Current
(One Port - TTL
MIL.
7025X30
7025X35
COM'L ONLY
Typ.(2) Max. Typ.(2) Max. Unit
:::::::::::> -:':','
105. ::::~50
105 :::::?20
100
100
250
215
::::::::::-
:::::::::::::::::::-
l.gyy ::lllf5
,,? : ,}
1.0
0.2
15
5
:::::::./: .:':::::::.
,:,:,:,:,:,:,:
::::,:,:,:,
f>::\ )::::::
10&: :::::~30
10~
:;:!:::;:;;90
160
160
400
340
160
160
340
290
20
20
85
65
20
20
70
50
95
95
290
250
95
95
240
210
1.0
0.2
30
10
1.0
0.2
15
5
90
90
260
215
rnA
rnA
rnA
rnA
rnA
95
230
90
220
95
190
90
180
NOTES:
2653 tbl 08
1. X in part numbers indicates power rating (S or L)
Vcc
=
SV,
TA
=
+2SoC.
2.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. At Vcck"
VALID
MATCH
ADDRp2. P3 or P4
twoo
)
DATAp2. P3. or P4
tODO
E
2817 drw 10
NOTES:
1. Assume BUSY input at HIGH and CE at LOW for the writing port.
2. Write cycle parameters should be adhered to in order to ensure proper writing.
3. Device is continuously enabled for any of the reading ports which has its OE at LOW.
TIMING WAVEFORM OF WRITE WITH BUSY INPUT
twp
RNi
t4---~ tWH
2817 drw 11
7.2
8
IDT70M74 (4K x 16) FourPort™
STATIC RAM MULTICHIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
1.60"
M~~---TYP·----~~~I
~ r---------t<2
T
•••••••••••••••
••••••••••••••••
•••• •••••• • ••
•••
••
••••
•• ••••
••••
•••
••••
•••
•••••
• •••
• •••
•••
•
••••
•••
•
••
••
•• •••••• •• ••
••
••••••••••••••••
••••••••••••••••
••••••••••••••••
1.60"
TYP.
1llI~~1
••••••••••••••••
TOP VIEW
BOTTOM VIEW
0.250"
-----'=TYP.
p.J:il'I=II=II::i::i:ii=III=II~I~
T
SIDE VIEW
2817drw12
fI
7.2
9
~®
16Kx32 CMOS
DUAL-PORT STATIC RAM
MODULE
IDT7M1002
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High density 512K CMOS dual-port RAM module
• Fast access times
Commercial: 25, 30, 35, 40, 45, 55, 65ns
Military: 30, 40, 45, 55, 65ns
• Fully asynchronous read/write operation from either port
• Easy to expand data bus width to 64 bits or more using
the Master/Slave function
• Separate byte read/write signals for byte control
• On-chip port arbitration logic
• INT flag for port-to-port communication
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted fine pitch (25 mil) LCC packages allow
through-hole module to fit into 121 pin PGA footprint
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
The IDT7M1 002 is a 16K x 32 high speed CMOS Dual-Port
static RAM Module constructed on a co-fired ceramic substrate using four 16K x 8 (IDT7006) Dual-Port static RAMs in
surface-mounted LCC packages. The IDT7M1 002 module is
designed to be used as stand-alone 512K dual-port RAM or as
a combination Master/Slave dual-port RAM for 64-bit or more
word width systems. Using the lOT Master/Slave approach in
such system applications results in full-speed, error-free operation without the need for additional discrete logic.
The module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via additional control signals SEM
& INT.
The IDT7M1 002 module is packaged in a ceramic 121 pin
PGA (Pin Grid Array) 1.35 inches on a side. Maximum access
times as fast as 25ns are available over the commercial
temperature range and 30ns over the military temperature
range.
All lOT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
PIN CONFIGURATION
10
11
12
13
R_1/0(24)
U/0(24)
U/0(26)
U/0(2S)
U/0(30)
U::s
U5~
UWJ(3)
Rj)~
Rj::S
R_1I0(30)
R_1/0(2S)
R_1/0(26)
U/0(23)
L_1/0(2S)
U/0(27)
L_1I0(29)
U/0(31)
L_A(O)
L_RIW(4)
R_A(O)
R_1I0(31)
R_1I0(2S)
R_1/0(27)
R_1/0(2S)
R_1/0(23)
e
U/0(21)
U/0(22)
vee
L_A(3)
L_A(2)
L_A(1)
GND
R_A(1)
R_A(2)
R_A(3)
GND
R_1I0(22)
R_1I0(21)
D
U/0(19)
L_1/0(20)
L_A(4)
GND
R_A(4)
R_1I0(20)
RJ/0(19)
E
U/0(17)
U/0(1S)
L_A(S)
R_A(S)
R_1I0(1S)
RJ/0(17)
L_SEM
U/0(16)
L_A(6)
R_A(6)
R_1/0(16)
R_.SEM
L_BUSY
UNT
GND
GND
R INT
R BUSY
R R!W(1)
A
G
H
K
M
PGA
TOP VIEW
L R1W(1)
uW:l(2)
L_A(7)
R_A(7)
R R1W(2)
U/0(1S)
U/0(14)
L_A(S)
R_A(S)
R_1/0(14)
R_1I0(1S)
L 1/0(13)
L 1/0(12)
L A(S)
R A(S)
R 1/0(12)
R 110(13)
GND
R_A(12)
R_A(11)
R_A(10)
vee
GND
R_1I0(11)
RiW (4)
R_A(13)
R_1/0(2)
R_1/0(4)
R_I/O(6)
R_I/O(S)
R_1I0(10)
R_R!W(3)
R_1I0(0)
R_I/O(1)
R_1/0(3)
R_I/O(S)
R_I/O(7)
L_1/0(11)
MIS
GND
L_A(10)
L_A(11)
L_A(12)
L_1/0(10)
U/O(S)
L_1/0(6)
U/0(4)
U/0(2)
L_A(13)
R
U/0(9)
U/0(7)
U/O(S)
U/O(3)
U/0(1)
U/O(O)
R_1I0(S)
2795 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·706412
©1992 Integrated Device Technology, Inc.
7.3
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
MIS
I
-
-
L_I/O(O-7)
R_1I0(0-7)
L_CS
L_OE
L_SEM
L_INT
L_BUSY
R_CS
R_OE
R_SEM
R_INT
R_BUSY
RJWV(O)
1DT7006
16Kx B
(ARBITRATION
LOGIC)
I
LJWV (0)
I
)
10T7006
16KxB
~
f-
(ARBITRATION
LOGIC)
......
~
~~
I
)
-
I
)
10T7006
16KxB
.- -
.....
(ARBITRATION
LOGIC)
r--.
I-~
I
)
I-
I
)
IOT7006
16KxB
--
(ARBITRATION
LOGIC)
l - fl-
I
LJWV (3)
II
2795 drw 02
PIN NAMES
Left Port
Right Port
L A (0-13)
R_A (0-13)
Address Inputs
L 1/0 (0-31)
L RlW (1-4)
Data Inputs/Outputs
L CS
R 1/0 (0-31)
R R/W(1-4)
R CS
L OE
ROE
Output Enable
L BUSY
L_INT
R BUSY
R_INT
Interrupt Flag
R SEM
L SEM
MIS
Description
Read/Write Enables
Chip Select
Busy Flag
Semaphore Control
MasterlSlave Control
Vee
Power
GND
Ground
27951bl 01
7.3
2
IDTIM1002
16K x 32 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commerlcal
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
RECOMMENDED OPERATING
. TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
Military
-55°C to + 125°C
Commercial
VCC
OV
5.0V ± 10%
OV
5.0V ± 10%
O°Cto +70°C
2795tbl03
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
2795tbl 02
NOTE:
GND
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation ofthe device atthese or any other conditions above those
indicated in the operational sections of this specification Is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Parameter
Min.
Typ.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
,0
0
V
VIH
Input High Voltage
2.2
-
6.0
V
Vil
Input Low Voltage
-0.5(1)
-
0.8
V
Max. Unit
2795tbl04
NOTE:
1. VIL;:: :-3.0V for pulse width less than 20ns
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
Symbol
Test Conditions
Max.
Units
IILlI
Input Leakage
(Address & Control)
Parameter
Vee= Max.
VIN = GND to Vee
Min.
-
40
f.1A
IILlI
Input Leakage
(Data)
Vee = Max.
VIN = GND
-
10
f.1A
IILol
Output Leakage
(Data)
Vee = Max.
CS ~ VIH, VOUT = GND to Vee
-
10
f.1A
VOL
Output Low
Vee = Min. IOl = 4mA
Voltage
-
0.4
V
VOH
Output High
Voltage
Vee
2.4
-
V
to Vee
=Min, IOH = -4mA
2795 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
Commercial
Symbol
Parameter
Test Conditions
Min.
lec2
Dynamic Operating Current
(Both Ports Active)
Vee = Max., CSs Vll, SEM = Don't Care
Outputs Open, f = fMAX
-
ISB
Standby Supply Current
(Both Ports Inactive)
Vee = Max., L_CSand R_CS~VIH
Outputs Open, f = fMAX
ISB1
Standby Suppy Current
(One Port Inactive)
ISB2
Full Standby Supply Current
(Both Ports Inactive)
Max.
Military
Min.
Max.
Units
1360
-
1600
rnA
-
.280
-
340
rnA
Vee = Max., L_CSor R_CS~ VIH
Outputs Open, f = fMAX
-
1000
-
1160
rnA
L CS and R CS ~ Vee - 0.2V
VIN > Vee - O.2V or < b.2V
L_SEM and R_SEM ~ Vee;.. 0.2V
-
60
-
120
rnA
2795tbl 06
7.3
3
IDTIM1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+5V
CAPACITANCE (1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
CIN(1)
Input Capacitance
(CS, OE, SEM, Address)
VIN = OV
40
pF
CIN(2)
Inp~ Capacitance
(RIW, I/O, INl)
VIN = OV
12
pF
CIN(3)
Input CaPa.9itance
(BUSY, MIS)
VIN
= OV
45
pF
COUT
Output Capacitance
(I/O)
12
pF
VOUT
= OV
480n
30pF*
255n
"Including scope and jig.
NOTE.
2795 tbl 07
1. This parameter is guaranteed by design but not tested.
2795 drw 03
Figure 1. Output Load
+5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
DATAoUT
255n
1.5V
See Figures 1 & 2
2795tbl08
"Including scope and jig.
2795 drw 04
Figure 2. Output Load
(For tCHz,
AC ELECTRICAL CHARACTERISTICS
tCLz, tOHZ, tOLZ, tWHZ, toW)
(Vcc = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
_25(10)
Symbol
Parameter
Min.
Max.
7M1002SxxG,7M1002SxxGB
_30(10)
_35(10)
-40
Min.
Max.
Min.
Max. Min. Max.
-45
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
25
-
30
-'
35
-
40
-
45
-
tAA
Address Access Time
25
-
30
-
35
-
40
-
45
ns
tACS(2)
Chip Select Access Time
25
-
35
-
45
ns
15
11
-
20
-
40
Output Enable Access Time
-
30
tOE
-
tOH
tLZ(1)
Output Hold from Address Change
3
-
3
3
-
3
tHZ(1)
Output to High
15
tPU(1)
Chip Select to Power Up Time
tPO(1)
Chip Deselect to Power Up Time
-
tsop
Sem. Flag Update Pulse (OE or SEM)
Output to Low
Z
Z
ns
22
-
25
ns
3
-
ns
3
-
-
17
-
20
ns
0
-
0
3
-
3
-
-
15
-
15
0
-
0
-
-
ns
50
-
50
-
50
-
50
-
50
ns
15
-
15
-
15
-
15
-
15
-
ns
-
30
-
35
-
40
-
45
-
ns
ns
0
-
ns
35
-
ns
3
0
-
5
ns
Write Cilcle
twc
tcW(2)
Write Cycle Time
25
Chip Select to End of Write
20
tAW
Address Valid to End of Write
20
tAS
Address Set-Up Time
twp
Write Pulse Width
tWR
Write Recovery Time
0
20
0
25
25
0
25
0
30
30
0
30
0
35
35
0
35
0
40
40
0
ns
ns
(Continued on next page)
2795tbl 09
7.3
4
•
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%, TA = 55°C to +125°C or O°C to +70°C)
7M1002SxxG,7M1002SxxGB
_30(10)
_35(10)
-40
_25(10)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
-45
Max.
Min.
Max.
Unit
Write Cy_cle (continued)
-
25
15
-
tow
Data Valid to End of Write
18
-
22
tOH
Data Hold Time
a
-
a
tHZ(1)
Output to High
-
15
tow(1)
Output Active from End of Write
a
-
a
-
a
tSWRD
SEM Flag Write to Read Time
10
-
10
-
10
tsps
SEM Flag Contention Window
10
-
10
-
10
25
30
50
-
-
40
-
Z
-
a
-
25
15
-
-
10
a
a
10
-
25
17
-
-
ns
20
ns
a
-
ns
. 10
-
ns
a
-
10
ns
ns
Busy Cycle-Master Mode(3)
tBAA
BUSY Access Time to Address
tBDA
BUSY Disable Time to Address
tBAC
BUSY Access Time to Chip Select
tBDC
BUSY Disable Time to Chip Deselec
tWDD(5)
Write Pulse to Data Delay
-
tODD
Write Data Valid to Read Data Delay
-
35
tAPS(6)
Arbitration Priority Set-Up Time
5
-
tBDD
BUSY Disable to Valid Time
-
20
20
20
5
-
NOTE 9
25
25
25
55
NOTE 9
60
-
65
-
45
-
50
-
30
30
-
5
-
25
-
35
NOTE 9
5
-
35
30
30
25
NOTE
5
9
-
35
ns
30
ns
30
ns
25
ns
70
ns
55
ns
-
ns
NOTE 9
ns
Busy Cycle-Slave Mode (4)
tWS(7)
Write to BUSY Input
a
-
a
-
a
Write Hold after BUSY
20
-
25
-
25
-
25
-
25
-
ns
tWH(8)
a
a
tWDD(5)
Write Pulse to Data Delay
-
50
-
55
-
60
-
65
-
70
ns
ns
Interrupt Timing
tAS
Address Set-Up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
a
a
-
a
a
-
a
a
-
20
-
25
-
30
25
-
30
20
-
a
a
-
-
a
a
-
ns
32
-
35
ns
32
-
35
ns
ns
2795tbl 10
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM, Cs:s; VIL and SEM <= VIH. To access semaphore, CS <= VIH and SEM :s; VIL.
3. When the module is being used in the Master Mode (MIS <= VIH).
4. When the module is being used in the Slave Mode (MlS:s; VIL).
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
6. To ensure that the earlier of the two ports wins.
7. To ensure that the write cycle is inhibited during contention.
8. To ensure that a write cycle is completed after contention.
.
9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tODD - tWP (actual).
10. Preliminary specifications.
7.3
5
IDTIM1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%, TA = -55°C to +125°C or ooe to +70°C)
-55
Symbol
Parameter
Min.
-65
Max.
Min.
Max.
Unit
65
65
ns
35
ns
-
ns
-
ns
ns
ns
Read Cycle
tRC
Read Cycle Time
55
-
tAA
tACS(2)
Address Access Time
-
Chip Select Access Time
-
tOE
Output Enable Access Time
tOH
tLZ(1)
Output Hold from Address Change
3
5
55
55
30
-
65
-
-
-
3
5
-
25
-
0
-
30
50
tHZ(1)
Z
Output to High Z
tPU(1)
Chip Select to Power Up Time
tPD(1)
Chip Deselect to Power Up Time
-
50
0
-
tsop
Sem. Flag Update Pulse (OE or SEM)
15
-
15
-
55
45
-
65
50
45
0
40
0
30
-
-
Output to Low
ns
ns
ns
ns
Write Cycle
twc
tcW(2)
Write Cycle Time
tAW
Address Valid to End of Write
tAS
Address Set-Up Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
Chip Select to End of Write
tDH
Data Hold Time
tHZ(1)
Output to High
tWHZ(1)
Write Disable to Output in High
tOw(1)
Output Active from End of Write
tSWRD
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
Z
Z
-
ns
ns
0
-
50
0
50
0
40
0
-
ns
-
25
-
30
ns
25
-
30
ns
0
10
10
-
0
10
10
-
ns
45
40
40
35
80
-
-
45
40
40
35
90
65
-
75
ns
-
5
-
ns
-
ns
ns
ns
ns
-
ns
ns
ns
Busy Cycle-Master Mode(3)
tBAA
BUSY Access Time to Address
tBDA
BUSY Disable Time to Address
tBAC
BUSY Access Time to Chip Select
-
tBDC
tWDD(5)
BUSY Disable Time to Chip Deselect
-
Write Pulse to Data Delay
-
toDD
tAPS(6)
Write Data Valid to Read Data Delay
tBDD
BUSY Disable to Valid Time
Arbitration Priority Set-Up Time
5
-
NOTE 9
(Continued on next page)
7.3
-
-
-
NOTE 9
ns
II
ns
ns
ns
ns
ns
2795tbl
6
11
IDT7M1002
16K x 32 CMOS DUAL·PORTSTATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee
= 5V
± 10%, TA = 55°C to +125°C or O°C to +70°C)
·55
Symbol
Parameter
Min.
·65
Max.
Min.
Max.
Unit
Busy Cycle·Slave Mode(4)
tWB(7)
Write to BUSY Input
0
-
Write Hold after BUSY
25
-
0
tWH(8)
25
-
ns
tWDD(5)
Write Pulse to Data Delay
-
80
-
90
ns
-
0
-
ns
0
40
-
45
ns
40
-
45
ns
Interrupt Timing
tAS
Address Set-Up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM, CS:$ VIL and SEM ;:: VIH. To access semaphore, CS;:: VIH and SEM :$ VIL.
3. When the module is being used in the Master Mode (MIS;:: VIH).
4. When the module is being used in the Slave Mode (MIS :$ VIL).
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
6. To ensure that the earlier of the two ports wins.
7. To ensure that the write cycle is inhibited during contention.
S. To ensure that a write cycle is completed after contention.
9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tODD - tWP (actual).
7.3
ns
ns
2795tbl 12
7
IDT7M1002
16K x 32 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
~---------tRC
ADDRESS
DATAoUT
2795 dew 05
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE (1',3, 5)
tACE
cs
tCHl (6)
tsoP
OE
tOLl (6)
tOHl (6)
DATA VALID
DATAoUT
tPD (6)
tCLl (6)
Icc
50%
50%
CURRENT
ISB
~tPU(6)
2795 dew 06
NOTES:
1. RiW is high for Read Cycles
2. Device is continuously enabled CS S VIL. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OES VIL
5. To access RAM, CS S VIL and SEM ~ VIH. To access semaphore, CS ~ VIH and SEM S VIL.
6. This parameter is guaranteed by design but not tested.
7.3
II
8
IDTIM1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIW CONTROLLED TIMING) (1,2,4)
..
~E
ADDRESS
><
..
~
'"
~
-toW(9)_~
tWHZ (9)
.I
(4)
~I
----------------------------~~
--tow
DATAIN
tWR (7)
7' ~
~
J
DATAoUT
L
7
.
twp (2)
---tCHZ~
7 ~
.
tAW
__ tAS (6) __ ..
RlW
~
twc
---
~
-tOH
____
DA_T_A_V_AL_ID__
~:>~I----------2795 dlW 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,2,4)
..
..
twc
~E
ADDRESS
"
tAS (6)
~~
tAW
~
'".
7'
L
..
twp (2)
tWR (7)
RlW
----------------------------~~
----tow
DATAIN
~
-tOH
->~I-----------
____
DA_T_A_V_AL_ID____
2795 dlW 08
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
RiW must be high during all address transitions.
A write occurs during the overlap (twp) of a low CS and a low RiW.
twR is measured from the earlier of CS or RiW (or SEM or RiW) going high to the end of write cycle.
During this period, the I/O pins are in the output state and input signals must be applied.
If the CS or SEM low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
Timing depends on which enable signal is asserted last.
Timing depends on which enable signal is de-asserted first.
If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twP or (twz + tow) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified twP.
7.3
9
IDTIM1002
16K x 32 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE (1)
1......11----- tAW
.......- - - t A A
Ao-A2
DATAo
RlW
- - - . - i - - tAOE
1----- WRITE CYCLE ----'~ ...- - - -
~
READ CYCLE
2795 drw 09
NOTE:
1. CS:<: VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION (1,3,4)
MATCH
:><:~
_____________________________
SIDE(2) "A"
II
MATCH
(2)
SIDE
"8"
2795 drw 10
NOTES:
1. DOR = DOL::; VIL, (L_ CS = R_ CS) :<: VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "S" is the opposite port from "A".
3. This parameter is measured from RiWA or SEMA going high to RiWs or SEMs going high.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.3
10
IDT7M1002
16K x 32 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (MIS;::: VIH)(2)
twc·
~~
ADDRR
~~
MATCH
twp
~
RlWR
7 ?-
""
-tDW-
~E
DATAINR
VALID
j.-
tAPS (1)
7 ~~
ADDRL
tDH
~E
tBDA
--
MATCH
/)
tBDD
"7 ~
(-tDDD (3)
~
~~
DATAoUTL
tWDD
I
~
2795 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins.
2. ~ CS = R_ CS) !> VIL
3. OE!> VIL for the reading port.
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (MIS:::; VIH)
(1,2)
~---------------twc
ADDRR
MATCH
twp
tDW -
tDH
·VALID
DATAINR
MATCH
ADDRL
~----------
tDDD
DATAoUTL
tWDD
2795 drw 12
NOTES:
1. BUSY input e~als High for the writing port.
2. (L_ CS = R_ CS)·!> VIL
.
7.3
11
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (MIS ~ VIL)
twp
DATAINR
2795 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION (CS CONTROLLED TIMING)
(1)
X
ADDR"A"~
AND "8" ~_ _ _ _ _ _ _ _ _
A_D_D_R_ES_S_M_A_T_C_H_ _ _ _ _ _ _ _ _ _ _..;'"
~tAPS
.....
, _ __
tBDC
(21
CS "8"
~--t~
tBAC
8USY"8"
2795 drw 14
TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING) (1)
II
ADDRESS "N"
ADDR "A"
ADDR"8"
MATCHING ADDRESS "N"
__________
~:::~_-_t_M_A_ _ _~_________t_BD_A_~---------
8USY"8"
2795 drw 15
NOTES:
1. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
7.3
12
JDT7M1002
16K x 32 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT CYCLE
(1)
~----------------------twc
INTERRUPT SET ADDRESS (2)
ADDR "A"
CE"A"
RlW1"A"
tiNS (3)
=-1
---!...--.-~---
ADDR"~~~-~~~~~~~~~~~IN~T-E~R~R-U~P-T-C-~-~~R-AD-D-R-E-S~-2-)~~~~~~
~~tAS(3)
OE "8"
IINR (3)
~_______________________________________
INT "8"
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "S" is the port opposite from UA".
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLE I: Non-Contention Read/Write Control
(1)
Mode
Outputs
Inputs
2795 drw 17
CS
RIW
OE
SEM
H
X
X
H
High-Z
Deselected or Power Down
L
L
X
H
Data In
Write
L
H
L
H
Data_OUT
X
X
H
X
High-Z
1/0
Description
Read
Outputs Disabled
NOTE:
1. The conditions for non-contention are L_A (0-13) 'f. R_A (0-13).
2.
denotes a LOW to HIGH waveform transition.
2795tbl 13
-.r
TRUTH TABLE II: Semaphore ReadlWrite Control
Inputs(2)
CS
RIW
Outputs
OE
SEM
1/0
H
H
L
L
Data_OUT
H
-1
X
L
Data_IN
L
X
X
L
-
Mode
Description
Read Data in Semaphore Flag
Write Data-,N (0, 8, 16, 24)
Not Allowed
INTERRUPT/BUSY FLAGS, DEPTH & WIDTH EXPANSION, MASTER/SLAVE CONTROL,
SEMAPHORES
2795 tbl 14
For more details regarding Interrupt/Busy flags, depth and/or width expansion, master/slave control, or semaphore
operations, please consult the IDT7006 data sheet.
7.3
13
IDTIM1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
--J r- 0.125
r- 10~55 --.J1
PACKAGE DIMENSIONS
0.025 ~I+, 0.200
1.325
B8 1
!Dl
IDl
R
1::1
1.325
1.355
J
0.235
MAX.
TOP VIEW
r-~~~I
0000000000000
0000000000000
0000000000000
000
000
ggg
ggg
ggg
r
llO.016
0.020
0.040
C"'l 0.060
+I II-- ~
-+I
~0.175
MAX.
T
1.200
J:
ggg sse
000
000
0000
000
0000000000000
~g
~~~O
00060
ggggg ggggg g
SOnOMVIEW
Pin A1
2795 drw 18
II
7.3
14
(~J
4Kx36
BiCMOS DUAL-PORT
STATIC RAM MODULE
PRELIMINARY
IDT7M1014
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High density 4K x 36 SiCMOS Dual-Port Static RAM
module
• Fast access times
Commercial: 15,20,25, 30ns
Military: 20, 25, 30ns
• Fully asynchronous read/write operation from either port
• Surface mounted LCC packages allow through-hole
module to fit on a ceramic PGA footprint
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
The IDT7M1014 is a 4K x 36 asynchronous high speed
SiCMOS Dual-Port static RAM module constructed on a cofired ceramic substrate using 4 IDT7014 (4K x 9) asynchronous Dual-Port RAMs. The IDT7M1014 module is designed
to be used as stand alone 36-bit dual-port RAM.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory.
The IDT7M1 014 module is packaged in a ceramic PGA
(Pin Grid Array). Maximum access times as fast as 15ns and
20ns are available over the commercial and military temperature range respectively.
AIIIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class S making them ideally suited
to applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
L_A(0-11)
-
r - - - R_A(0-11)
LJ/O(O-8)
R_I/O(O-8)
IOT7014
4Kx 9
L_OE
L_R!W(O)
R_OE
R_RlW(O)
L_I/O(9-17)
R_I/O(9-17)
10T7014
4Kx9
L_RlW(1)
R_RIW(1)
L_I/O(18-26)
R_I/O(18-26)
IOT7014
4Kx 9
L_RJW(2)
R_RlW(2)
L_I/O(27-35)
R_I/O(27-35)
-
10T7014 I - - 4Kx 9
2819 d/W 01
BiCEMOS'" is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·70961·
©1992 Integrated Device Technology, Inc.
7.4
IDT7M1014 (4K x 36)
BICMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TBD
Commercial
Military
Unit
VTERM(2) Terminal Voltage
with Respect to
GND
Rating
-0.5 to +7.0
-0.5 to +7.0
V
VTERM(3) Terminal Voltage
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAs
Temperature
Under Bias
-10 to +85
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
(Please Consult Factory)
NOTE:
2819tbl02
1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied, Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2, Inputs and Vcc terminals only.
3. 1/0 terminals only,
RECOMMENDED DC
OPERATING CONDITIONS
PIN NAMES
Right Port
Left Port
"
L_RlW(0-3)
R_RJW(0-3)
Symbol
Names
ReadlWrite Enables
L_OE
R_OE
Output Enables
L_A (0-11)
R_A (0-11)
Address Inputs
L_I/O (0-35)
R_IIO (0-35)
Data InpuVOutputs
Vee
Power
GND
Ground
2819tbiOl
Min.
Typ.
Max.
Vee
Supply Voltage
Parameter
4,5
5,0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6,0
V
VIL
Input Low Voltage
-0,5(1)
-
Unit
0.8
NOTE:
1. VIL;:: -3,OV for pulse width less than 20ns.
V
2819 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Vce
Military
-55°C to +125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
Commercial
2819 tbl 04
CAPACITANCE TABLE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
C_IN(1)
Input Capacitance (Address, CS, OE)
C_IN(2)
Input Capacitance (Data,
COUT
RIW)
Conditions
Max.
Unit
V_IN = OV
50
pF
= OV
V_OUT =OV
15
pF
15
pF
V_IN
Output Capacitance (Data)
NOTE:
1. This parameter is guaranteed by design but not tested,
2819 tbl 05
7.4
2
•
IDT7M1014 (4K x 36)
BiCMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to+70°C)
Test Conditions
Min.
Max.
Unit
liLiI
Input Leakage
VIN = GND to Vee
Parameter
Vee = Max.
-
40
j.tA
IILol
Output Leakage
OE ~ VIH, VOUT = GND to Vee
Vee = Max.
-
40
j.tA
VOL
Output Low Voltage
Vee = Min. IOL = 4mA
-
0.4
V
VOH
Output High Voltage
Vee = Min. IOH = -4mA
2.4
-
Symbol
V
2819nbl06
DC ELECTRICAL CHARACTERISTICS
= 5V ± 10%, TA =-55°C to + 125°C or O°C to +70°C)
(Vee
Icc
Test Conditions
Parameter
Symbol
Min.
-
Vee = Max.,
Operating Current
Max.
Unit
1040
rnA
Outputs Open. f = fMAX(1)
NOTES:
1. At f=fMAX, address and data inputs (except OE) are cycling at the maximum frequency of read cycle of 1/tRC, and using "AC TEST
2819 Ibl 07
CONDITIONS· of input levels of GND to 3V.
AC TEST CONDITIONS
GNDto 3.0V
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1-3
Output Load
2819 Ibl 08
+5V
480n
DATAoUT--------~------_1
6
!l.TAA
255n
5 pF*
(Typical, ns)
4
2819 drw 02
"Including scope and jig.
Figure 1. Output Load
(For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
20
40
60
80
100 120 140 160 180
200
CAPACITANCE (pF)
2819 drw 04
DATA OUT
-.Y:_¥-------rD
ZO
= 50n
-=-
Figure 3. Alternate Lumped Capacitive Load,
Typical Derating
150n
1.5V
2819 drw 03
Figure 2. Alternate Output Load
7.4
3
IDTIM1014 (4K x 36)
BiCMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
7M1014SxxG,7M1014SxxGB
-15(3)
Symbol
Parameter
Min.
-20
Max.
-25
Min.
Max.
Min.
-35
Max.
Min.
Max.
Unit
Read Cycle
tHc
Read Cycle Time
15
-
20
-
25
-
35
-
ns
tAA
Address Access Time
-
15
-
20
-
25
-
35
ns
tOE
Output Enable Access Time
-
8
-
10
-
12
-
20
ns
tOH
Output Hold from Address Change
3
3
-
3
-
ns
Output Enable to Output in Low Z
0
-
3
tOLZ(l)
-
0
-
0
-
ns
tOHZ(l)
Output Disable to Output in High Z
-
7
-
9
-
11
-
15
ns
-
20
25
-
35
-
30
15
30
2
-
12
15
'-
25
-
ns
20
0
-
0
-
0
-
11
-
15
ns
-
ns
0
Write Cycle
twc
Write Cycle Time
15
lAw
Address Valid to End of Write
14
lAs
Address Set-Up Time
0
twp
Write Pulse Width
twR
Write Recovery Time
1
-
tow
Data Valid to End of Write
10
-
toH
Data Hold Time
0
-
0
-
twHZ(l)
Write Enable to Output in High Z
-
7
-
9
toW(l)
Output Active from End of Write
0
-
0
-
twDD
Write Pulse to Data Delay
tooo(1)
Write Data Valid to Read Data Delay
'12
-
15
2
30
-
40
25
-
30
0
20
0
-
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Port-to-Port delay through the RAM cells from the writing port to the reading port.
3. Commercial specification only.
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE)
-
0
2
0
ns
ns
ns
ns
ns
ns
45
-
55
ns
35
-
45
ns
2819 tbl 09
II
(1,2)
ADDRESS
DATAoUT
2819 drw 05
NOTES:
1. RIW is hig h for Read Cycles.
2.
OE~
VIL
7.4
4
IDT7M1014 (4K x 36)
BICMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE)
(1,2)
DATAoUT
2819 drw 06
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY
twc
L
ADDRR
RlWR (1)
*
)~
MATCH
twp
"',
/V
tow
)(
DATAINR
VALID
MATCH
ADDRL
twoo
)~ VALID
DATAoUTL
toDD
NOTES:
1. Rm is high for Read-2Ycles.
2. Adress valid prior to OE transition low.
3. This parameter is guaranteed by design but not tested.
2819 drw07
7.4
5
IDT7M1014 (4K x 36)
BiCMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE (EITHER SIDE) (1,2)
twc
ADDRESS
~----------------- tAW
tWR
RlW
DATAoUT
DATAIN
NOTES:
1. RfiiJ is high during all address transitions.
2. If OE is low during the write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is high, this requirement does not apply, and the write pulse
can be as short as the specified twP.
3. This parameter is guaranteed by design but not tested.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
2819 drw 08
PACKAGE DIMENSIONS
~ ~ -l
I
c ':;[
~
0.025
~ I]~J rowm~~~
0.235
MAX.
TOP VIEW
r
I
0000000000000
0000000000000
0000000000000
00000
00000
gggo
ggg
oggg
ggg
0000
0000
000000
00000
0000000000000
--I
0
11+ ~
--.J I---
1.200~
BSe
~ ~.~~
•
0.020
0.040
o:oso
0.175
MAX.
T
1.200
J:
BSe
~oooooooooooo
r
.... 000000000000
BOTTOM VIEW
2819 drw 09
PinA1
7.4
6
(;)®
4K x 36 SYNCHRONOUS
DUAL-PORT STATIC RAM
MODULE
ADVANCE
INFORMATION
IDT7M1024
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 4K x 36 Synchronous Dual-Port SRAM
module
• 50MHi: operation
• lOT's BiCEMOSTM process technology
• Architecture based on dual-port RAM cells
- Allows full simultaneous access from both ports
• Synchronous operation
4ns setup to clock, 1ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 15ns clock to data out
Self-timed write allows fast write cycle
20ns cycle time, 50MHz operation
• Clock enable feature
• Single 5V (±1 0%) power supply
• Multiple GND pins and decoupling capacitors for
maximum noise immunity
• Inputs/outputs directly TIL compatible
The IDT7M1 024 is a 4K x 36 bit high speed synchronous
Dual-Port static RAM module constructed on a co-fired ceramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs.
The IDT7M1024 module is designed to be used as a stand
alone 36-bit Dual-Port static RAM.
The IDT7099 (4K x 9) Dual-Port RAMs have registers on
address inputs, control and data lines, providing for low setup and hold times for the IDT7M1024 module.
The IDT7M1 024 module is packaged in a 144-pin ceramic
PGA (Pin Grid Array), with a cycle time as fast as 20ns
providing 50MHz operation.
All lOT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
L_CLK
L_CLKEN
L_CS
-
-
L_5E" L_A(0-11)
L_IIO(O-8)
R_DE
R_A(0-11)
R_IIO(O-8)
IDT7099
4Kx 9
L_ RJW(O)
-
R_R!W(O)
II
IDT7099
4Kx 9
II
)
IDT7099
4Kx 9
JI
)
)
----
IDT7099
4Kx 9
BiCEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©t 992 Integrated Device Technology, Inc.
I
2809 drw at
APRIL 1992
DSC-70971t
(;)®
2Kx36
CMOS DUAL-PORT
STATIC RAM MODULE
IDT7M1012
Integrated Device Technology, Inc.
IDT7M1 012 modules are designed to be used as stand alone
36-bit dual-port RAM where on-chip hardware port arbitration
is not needed. It is the users responsibility to ensure data
integrity when simultaneously accessing the same memory
location from both ports.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory.
The IDT7M1 012 module is packaged in a 121-pin ceramic
PGA (Pin Grid Array), resulting in package dimensions of only
1.36" x 1.36" x 0.28". Maximum access times as fast as 25ns/
30ns are available over the commercial/military temperature
range.
All lOT military modules are constructed with semiconductor components manufacturedin compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
FEATURES
• High density 2K x 36 CMOS Dual-Port Static RAM
module
• Fast access times
Commercial: 25, 30, 40, 50, 60ns
Military: 30, 40, 50, 60, 70ns
• Fully asynchronous read/write operation from either port
• Surface mounted LCC packages allow through-hole
module to fit on a 121-pin PGA footprint
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
DESCRIPTION
The IDT7M1 012 is a 2K x 36 high speed CMOS Dual-Port
static RAM module constructed on a co-fired ceramic substrate using four IDT7012 (2K x 9) Dual-Port RAMs. The
PIN CONFIGURATION(1)
B
C
D
E
F
G
H
K
L
M
11
12
13
7
S
9
U/O(27)
L_I/O(2S)
L_I/O(30)
U/O(32)
L_R!W(4)
LJ/O(lS) R_I/O(lS) R_I/O(19) R_I/O(21) R_1I0(23) R_I/O(24)
R_I/O(26)
L_I/O(29)
L_I/O(31)
L_I/O(33)
vcc
L.:.YO(34)
R_I/O(34)
GND
R_A(10)
R_A(9)
R_A(O)
GND
L_I/O(3S)
R_I/O(33)
R_A(l)
R_I/O(27)
R_I/O(32)
R_A(2)
R_I/O(2S)
R_I/O(31)
R_A(3)
R_I/O(29)
R_I/O(30)
GND
R_CS
GND
2
A
6
L_FWll(3) R_RIW{3) R_I/O(20) R_I/O(22) R_I/O(2S)
GND
3
4
vcc
L_A(O)
LJ/O(20) L_I/O(24)
L_A(l)
GND
LJ/O(21)
L_I/O(2S)
L_A(2)
L_I/O(22)
L_I/O(26)
L_A(3)
L_I/O(19)
L_I/O(23)
S
L_A(9)
L~(10)
10
PGA
Top View
R_RJW(4) R_I/O(3S)
GND
L_CS
GND
L_RJW(l)
L_OE
R_RJW(l)
L_RJW(2)
R_OE
R_RlW(2)
L_I/O(O)
R_I/O(3)
L_A(4)
R_A(4)
U/O(lS)
R_I/O(17)
L_I/O(l)
R_I/O(2)
L_A(S)
R_A(S)
U/O(16)
R_I/O(16)
L_I/O(2)
R_I/O(l)
GND.
L_A(6)
L__A(7)
L_A(S)
GND
R_A(S)
R_A(7)
R_A(6)
VCC
GND
R_I/O(lS)
U/O(3)
R_I/O(O)
VCC
R_I/O(4)
R_I/O(S)
R_I/O(7)
R_I/O(S)
L_I/O(ll)
L_I/O(12)
LJ/O(13)
L_I/O(14)
U/O(17)
R_I/O(14)
L_I/O(4)
U/O(S)
L_I/O(6)
L_I/O(7)
L_I/O(S)
R_I/O(6)
L_I/O(9)
L_1I0(10)
R_1I0(9)
R_I/O(10) R_I/O(ll) R_I/O(12)
R_I/O(13)
N
2
3
4
S
6
7
9
10
11
12
A
B
C
D
-
H
K
L
M
N
13
2821 drw 01
NOTES:
1. For the IDT7M1011 (1 K x 36 version). Pins C6 and C8 (L_A(10) and R_A(10) respectively) must be connected to VCC for proper operation of the
module.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC-7073/1
©1992 Integrated Device Technology, Inc.
7.6
IDT7M1012 (2K x 36)
CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAMS
L_A(D-10)
-
~
L_IIO(O~
L CS
L=:OE
R_A(D-10)
R_I/O(O-8)
R CS
R=OE
IDT7012
2K x 9
L_RlW(O)
R_RIW(o)
L_"O(9-17)
R_I/O(9-17)
r - IDT7012
2Kx 9
L_RIW(1)
R_R!W(1)
L_IIO(18-26)
R_I/O(18-26)
IDT7012
2K X 9
L_RIW(2)
R_RlW(2)
L_I/O(27-35)
R_I/O(27-35)
IDT7012 I - 2Kx 9
'-----
2821 drw 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
PIN NAMES
Left Port
Right Port
Names
L_CS
R_CS
Chip Selects
L_RlW(1-4)
R_RlW(1-4)
ReadlWrite Enables
L_OE
R_OE
Output Enables
L_A (D-10)
R_A (0-10)
Address Inputs
L_I/O (0-35)
R_"O (0-35)
Data Input/Outputs
Vee
Power
GND
Ground
Grade
Ambient
Temperature
GND
Military
-55°C to + 125°C
OV
5.0V
O°Cto +70°C
OV
5.0V ± 10%
Commercial
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC
OPERATING CONDITIONS
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-D.5(1)
-
0.8
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
± 10%
2821 Ibl 03
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-D.5 to +7.0
-D.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
2821 Ibl 01
Symbol
Vee
2821 Ibl 04
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
V
2821 Ibl 02
7.6
2
IDT7M1012 (2K x 36)
CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE TABLE (TA = +25°C, f = 1.0MHz)
Symbol
Conditions
Parameter
C IN(1)
Input Capacitance JAddress, CS,
C IN(2)
Input Ca~acitance JData,~
COUT
Output Capacitance (Data)
0])
Max.
=OV
V IN =OV
V OUT = OV
V IN
Unit
50
pF
15
pf
15
pF
2821 tbl 05
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(Vee
=5V ± 10%, TA =-55°C to +125°C or O°C to +70°C)
Symbol
Min.
Test Conditions
Parameter
Max.
Unit
IILlI
Input Leakage
Vee =Max.
VIN =GND to Vee
-
40
JlA
IILol
Output Leakage
Vee =Max.
CS~ VIH, VOUT =GND to Vee
-
40
JlA
VOL
Output Low Voltage
Vee = Min. IOL = 4mA
-
0.4
V
VOH
Output High Voltage
Vee
2.4
-
V
=Min. IOH = ·4mA
2821 tbl 06
DC ELECTRICAL CHARACTERISTICS
(Vee
=5V ± 10%, TA =-55°C to +125°C or O°C to +70°C)
Min.
Max.(t)
Max,!2)
Unit
lee
Dynamic Operating
Current (Both Ports Active)
Vee =Max., CS S VIL,
Outputs Open f =fMAX
-
1040
1240
rnA
ISB
Standby Supply
Current (Both Ports Inactive)
Vee = Max., CS_L and CS_R ~VIH
Outputs Open, f =fMAX
-
260
320
rnA
ISBt
Standby Supply
Current (One Port Inactive)
Vee =Max., CS_L 0 CS ~ VtH
Outputs Open, f =fMAX
-
700
800
rnA
1582
Full Standby Supply
Current (Both Ports Inactive)
CS Land CS R ~ Vee -O.2V
VIN> Vee 0.2V or < 0.2V
-
60
120
rnA
Symbol
Test Conditions
Parameter
2821 tbl 07
NOTES:
1. For commercial grade (O°C to +70°C) versions only.
2. For military grade (·55°C to +125°C) versions only.
7.6
3
•
IDT7M1012 (2K x 36)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
2821 lbl 08
+5V
480,Q
480,Q
DATAoUT
DATAoUT
255,Q
30pF*
255,Q
5pF*
*Including scope and jig.
Figure 1. Output load
Figure 2. Output load
2821 drw 03
2821 drw 04
(For tCHZ, tClZ, tOHZ, tOlZ, tWHZ, tOW)
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
Symbol Parameter
7M1012SxxG,7M1012SxxGB
-25(3)
-30
-40
-50
-60
-70
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
25
-
30
-
40
-
50
-
60
-
70
-
ns
tAA
Address Access Time
25
-
40
-
50
-
60
ns
25
30
40
70
ns
12
-
15
30
-
60
Output Enable Access Time
-
50
tOE
-
-
70
Chip Select Access Time
-
30
tAcs
-
35
-
40
ns
tOH
Output Hold from Address Change
0
0
-
0
-
0
-
0
Chip Select to Output in low Z
0
0
-
0
-
0
tCLZll)
-
0
-
0
-
0
-
ns
tCHZll)
Chip Deselect to Output in High Z
-
ns
tOLZll) Output Enable to Output in low Z
tOHZ(1) Output Disable to Output in High Z
tpu(1)
Chip Select to Power Up Time
tPDll)
Chip Deselect to Power Down Time
25
ns
10
-
12
-
15
-
20
-
30
-
35
-
0
-
0
-
0
-
0
-
0
-
ns
10
-
12
-
15
-
20
-
30
-
35
ns
-
0
-
0
-
0
-
0
-
0
-
ns
-
50
-
50
-
50
-
50
-
50
-
50
ns
-
40
-
50
-
60
-
70
-
35
-
40
-
50
30
35
-
50
0
-
40
0
-
0
-
ns
30
50
-
ns
0
ns
30
0
-
0
0
Write Cycle
twc
Write Cycle Time
25
-
30
tcw
Chip Select to End of Write
20
25
tAw
Address Valid to End of Write
20
-
tAs
Address Set-Up Time
0
-
0
-
twp
Write Pulse Width
20
-
25
-
30
-
35
-
40
twR
Write Recovery Time
0
-
0
0
12
-
15
20
20
-
0
Data Valid to End of Write
-
0
tDW
-
20
-
tDH
Data Hold Time
0
-
0
-
0
-
0
-
0
-
tOHZll)
Output Disable to Output in High Z
25
0
ns
ns
ns
ns
ns
-
10
-
20
-
35
ns
12
15
-
20
-
30
10
-
15
-
-
12
twHzll) Write Enable to Output in High Z
30
-
35
ns
tow(1)
0
-
0
-
0
-
0
-
0
-
0
-
Output Active from End of Write
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Port-to-Port delay through the RAM cells from the writing port to the reading port.
3. Preliminary specification only.
7.6
ns
2821 tbl09
4
IDTIM1012 (2K x 36)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE) (1,2,4)
ADDRESS
DATAoUT
2821 drw 05
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE) (1, 3, 5)
tACS
CS
tCHZ (6)
OE
DATAoUT
ICC
CURRENT
IS8
50%
2821 drw 06
NOTES:
1. RiW is high for Read Cycles
2. Device is continuously enabled, CS:::; VIL.
3. Addresses valid prior to or coincident with CS transition low
4. OE:::; VIL
5. To access RAM, CS = L.
6. This parameter is guaranteed by design but not tested.
7.6
5
IDT7M1012 (2K x 36)
CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIW CONTROLLED TIMING) (1, 3,5,8)
..
twc
ADDRESS
OE
.....----~----------------------------------------------------~
R/W
DATAoUT
DATAIN
2821 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 3, 5, 8)
twc
~
ADDRESS
tAw
CS
twp (2)
R/W
tow
DATAIN
tOH
DATA VALID
2821 drw 08
NOTES:
1. RiW must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low RiW for memory array writing cycle.
3. twR is measured from the earlier of CS or RiW going high to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is low during a RiW controlled write cycle, the write~Ise width must be th~arger of twp or (twz + tDW) to allow the 1/0 drivers to turn
off and data to be placed on the bus for the required tDW. If OE is high during an RIW controlled write cycle, this requirement does not apply.
and the write pulse can be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
7.6
6
IDTIM1012 (2K x 36)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
J+-
0.260
1.325
MAX.
liMAX
1.355=--+j
0.280
I
0.125
D.175
IT'
,~
';!iW~II~~
0.040
0.060
I--;;~go~
0000000000000
0000000000000
0000000000000
000
000
ggg
ggg
0.016
0.020
0.040
YO.060
I
0.100
sse
T
1.200
000
000
sse
000
000
000
0
0
0
1
0000
000
0000000000000
0000000000000
.. poooooooooooo
r
PIN A1
2821 drw 09
7.6
7
(;)®
128K x 16
64K X 16
32K X 16
CMOS DUAL-PORT RAM
(SHARED MEMORY MODULE)
Integrated Device Technology, Inc.
IDT7MB6036
IDT7MB6046
IDT7MB6056
FEATURES:
DESCRIPTION:
• High density 2 megabit/1 megabitl512K-bit CMOS DualPort static RAM (shared memory modules)
• Fully asynchronous read/write operation from either port
• Port arbitration/multiplexing logic by custom FCT chip set
• Memory array comprised of industry standard static RAM
component
• Fast access time
- 40ns (max.)
• Versatile controls: BUSY output flag and separate controls for lower and upper byte writes on each port
• Master/Slave control on-board for expanding word width
• Multiple GND and Vcc pins for maximum noise immunity
• Inputs and outputs directly TIL-compatible
• Single 5V (±10%) power supply
The Shared Memory Module provides two ports with separate control, address and Data I/O pins that permit independent access for read or writes to any location in the memory
array. Using the on-board Master/Slave input allows these
modules to be used as building blocks in 32-bit or more-bit
systems requiring full speed operation without additional
discrete logic.
In the Master Mode, the Shared Memory Module arbitrates
asynchronously between the left and right portsCS inputs. The
first to arrive is granted exclusive access to the entire RAM
array for as long as its CS is asserted. If both ports attempt
simultaneous access, the losing port will have its BUSY
asserted until the winning port completes it access, at which
time the second port will be granted its own exclusive access
to the entire RAM array. See application note AN-? 4 for more
details regarding proper module operating modes.
FUNCTIONAL BLOCK DIAGRAM(1)
UROUT
SELouT
MIS
I
CSL
[5S[L
CSR
DSLR
DSUR
[)SOL
RiWL
..
BSYLor URIN
I ADDR
I MUX
Ao-14L
6i:LL
~L
•
..
•
A15R
A16R
BSYR or SELIN
AO·14R
DO-7R
OELR
Do-14L
Da·15L
RlWR
ARBITRATION AND CONTROL
A15L
A16L
DATA
MUX
•
Da-15R
OEHR
RAM ARRAY
2688 drw 01
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC·7039/3
©1992 Integrated Device Technology, Inc.
7.7
IDT7MB6036/6046/6056 (128K!64K!32K x 16)
CMOS DUAL·PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (1, 2)
Vee
CSL
RlWL
DSLL
DSUL
A1SL
A1SL
A14L
GND
A13L
A12L
A11L
A10L
A9L
ASL
A7L
ASL
ASL
Vee
A4L
A3L
A2L
A1L
AOL
GND
•
2 •
3 •
4 •
5 •
6 •
7 •
8 •
9 •
10.
11 •
12.
13.
14.
15 •
16.
17.
18.
19 •
20.
21 •
22.
23.
24.
25.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
GND
CSR
RiWR
DSL R
DSUR
A1SR
A1SR
A14R
GND
A13R
A12R
A11R
A10R
A9R
ASR
A7R
ASR
ASR
GND
A4R
A3R
A2R
A1R
AOR
GND
GND
BSY L or URIN
UFh
GND
D 1SL
D14L
D 13 L
D12L
GND
D11L
D10L
D9L
DSL
OEOL
D7L
DSL
o SL
D4L
GND
D3L
o 2L
o 1L
DOL
OELL
GND
100.
99 •
98 •
97 •
96 •
95 •
94 •
93 •
92 •
91 •
90 •
89 •
88 •
87 •
86 •
85 •
84 •
83 •
82 •
81 •
80 •
79 •
78 •
77 •
76 •
.50
.49
.48
.47
.46
.45
.44
.43
.42
• 41
.40
.39
.38
.37
• 36
.35
.34
.33
.32
• 31
.30
.29
.28
.27
.26
GND
BSY R or SEL IN
SELoUT
M/S
D1SR
D14R
D13R
D12R
Vee
D11R
D10R
D9R
DSR
OEUR
D7R
DSR
DSR
D4R
GND
D3R
D2R
D1R
DaR
OELR
Vee
2688 drw02
NOTES:
1. Pins 7 and 57 must be grounded for proper operation of the 7MB6046 module.
2. Pins 6, 7, 56 and 57 must be grounded for proper operation of the 7MB6056 module.
PIN DESCRIPTION
Description
Symbol
Vee
Power
GND
Ground
AO·1SL
DO·1SL
AO·1SR
Left Port Address
DO·1SR
Right Port Data
RiW
CS
Active Low Chip Select
DSL
Data Strobe for Lower Byte
•
Left Port Data
Right Port Address
ReadlWrite Control
DSU
Data Strobe for Upper Byte
OEL
Output Enable for Lower Byte
OEU
BSYLor URIN
Output Enable for Upper Byte
Left Busy Output for Stand Alone or Master Mode. Left or Right Port Select Input for Slave Mode.
BSYR or SELIN
Right Busy Output for Stand Alone or Master Mode. RAM Array Select Input for Slave Mode.
UROUT
Left or Right Port Select Output on Master to be Connected to URJN Input on One or More Slaves
when Width Expansion is Required.
RAM Array Select Output on Master to be Connected to SEL_IN Input on One or More Slaves when
Width Expansion is Required.
Master/Slave signal for cascading master wlone or more slaves.
SELoUT
MIS
2688 tbl 01
7.7
2
IDT7MB6036/6046/6056 (128K164K132K x 16)
CMOS DUAL-PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Unit
-0.5 to +7.0
V
Terminal Voltage with
Respect to GND
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
0
0
0
V
-
6.0
V
-
O.B
V
TA
Operating Temperature
o to +70
°C
GND
Supply Voltage
TBIAS
Temperature Under Bias
-10 to +85
°C
VIH
Input High Voltage
TSTG
Storage Temperature
-55 to +125
°C
VIL
Input Low Voltage
lOUT
DC Output Current
50
rnA
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
2688 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
Symbol
Parameter
Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = OV
20
pF
COUT
Output Capacitance
VOUT= OV
20
2.0
-0.5(11
2688 tbl 04
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
pF
Grade
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
5.0V ± 10%
2688 tbl 03
2688 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ± 10%, TA =
Symbol
ooe to +70°C)
Parameter
Test Conditions
Min.
Max.
Unit
1IL11
Input Leakage Current
Vee= Max.
VIN = GND to Vee
-
15
I-lA
IILol
Output Leakage Current
Vee= Max.
CS = VIH, VOUT = GND to Vee
-
15
I-lA
lee
Dynamic Operating Current
Vee = Max., CS :::; VIL,
f = fMAX, Output Open
-
520
rnA
ISB
Standby Power Supply Current
CS;::: VIH, Vee= MAX.
Outputs Open, f = fMAX.
-
200
rnA
VOH
Output High Voltage
Vee = Min.
IOH =-8mA
2.4
-
V
VOL
Output Low Voltage
Vee= Min.
IOL = 16mA
0.4
V
2688tbl06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
2688tbl07
7.7
3
IDTIMB6036/6046/6056 (128K!64K!32K x 16)
CMOS DUAL-PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
+5V
+5V
~
480n
DATAoUT--------,-------~
DATAoUT--------,-------~
255n
255n
30pF*
5 pF*
2688 drw 03
2688 drw 04
*Including scope and jig.
Figure 1. Output Load
Figure 1. Output Load
(for to HZ and tOLZ)
AC ELECTRICAL CHARACTERISTICS (Vee = 5.0V + 10%, TA =
-50
~o
Symbol
Parameter
480n
Min.
Max.
Min.
ooe to +70°C)
-60
Max.1 Min.
-70
Max.
Min.
-85
Max.
I Min. Max.
-100
Min.
Max. Unit
No Contention Read
tRC
Read Cycle Time
40
-
50
-
60
-
70
-
85
-
100
-
ns
tM
Address Access Time
-
-
Chip Select Access Time
-
70
70
37
-
85
85
42
100
100
47
tOH
tOLZ(I)
OIP Hold from Address Chanqe
22
5
-
ns
Output Enable to Data Valid
60
60
32
-
tOE
-
-
tACS
40
40
5
OE to Output in Low-Z
-
tOHZ(I)
OE to Output in Hiqh-Z
5
8
-
5
8
-
5
-
8
-
50
50
27
8
-
5
8
-
7.5
-
7.5
-
7.5
-
7.5
-
40
35
35
0
15
20
3
22
5
-
-
-
70
60
60
0
15
35
5
30
5
-
-
60
50
50
0
15
30
5
25
5
-
-
50
45
45
0
15
25
3
22
5
-
85
75
75
0
15
50
5
45
10
12
40
-
12
50
-
-
12
60
-
15
70
-
-
-
ns
ns
ns
8
-
7.5
-
7.5
ns
-
-
ns
ns
-
100
90
90
0
15
60
5
50
10
-
20
85
-
ns
No Contention Write
twc
Write Cycle Time
tAW
Address Valid to End of Write
tcw
CS to End of Write
tAS
Address Set-Up Time
tCDS
CS to Data Strobe
tDS
Data Strobe Width
tWR
Write Recovery Time
tDW
Data Valid to End of Write
tDH
Data Hold from End of Write
-
-
-
-
-
-
-
ns
-
ns
-
ns
-
ns
ns
ns
ns
Contention Read
tCB
CSto BUSY
tBD
Busy Ne!:1ate to Data Valid
Contention Write
--
-
20
100
ns
ns
tCB
CSto BUSY
-
12
-
12
-
12
-
15
-
20
-
20
ns
tBDS
Busy Negate to Data Strobe
7
--
7
-
7
-
10
-
15
-
15
-
ns
11
11
Slave Timing
tLR
CS to UR Output
-
11
14
14
15
-
20
-
ns
14
-
20
--
-
20
CS to Select Output
-
15
tSEL
20
ns
tAPs
Arbitration Priority Set-up Time
5
-
5
-
5
-
5
-
5
-
5
-
NOTE:
1. This parameter guaranteed by design but not tested.
ns
2688tbl08
7;7
4
II
IDT7MB6036/6046/6056 (128K164K132K x 16)
CMOS DUAL·PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~----------------tRC
ADDRESS
~
____________________~~~~~~~~~~~~~----------•
~--r--------------tAA
OE
1+-------
tOE
tOLZ (2.:..)_ _ _~
1-4------- tACS
DATAoUT
--------------------------------~~
2688 drwOS
TIMING WAVEFORM OF WRITE CYCLE (CS CONTROLLED)
1+------------------------ twc
ADDRESS
1-4------------------~W
CS
------+---------~~~-------------tcw
Rm
DATAIN
. , . . - - - - - - - - - - - - tDS -----------~~of
2688 drw 06
TIMING WAVEFORM OF WRITE CYCLE (OS CONTROLLED)
~-----------------------twc--------------------------~.~I
ADDRESS
1-4------------------
tAW
Riw
tow -
.....~-tDH
--+-~
DATAIN
tCDS - - - i " " i 4 - - - - - - tDS
tWR
2688 drw07
NOTES:
1. RNi= VIH.
2. Transition is measured +200mV from steady state with 5pF load (including scope and jig. This parameter guaranteed by design, but not tested.
7.7
5
IDTIMB6036/6046/6056 (128K164K132K x 16)
CMOS DUAL-PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF CONTENTION READ, (CS ARBITRATION)
CSL
VALID FIRST:
L1~~~~
______________________________________~~~________________
1
s::: -----------~-tA-PS--(l~_t-CB--~--~-----------~~----tC-B--~-~--Lr---_-_~
eSL
___
-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-__
--
7f:DO-15R
tBD
-:1 :. . ._. . . .,. ., . . ,. ,. .~-=-:
:*: RI't~II~ATA
__
X
2688 drw 08
TIMING WAVEFORM OF CONTENTION WRITE, (CS ARBITRATION)
CSR
VALID FIRST:
=><~------------------------------------------------------------~><--------------------------
LAND R
ADDR
CSR
_1:'AP51:"_ _
- - + -_ _ _
CSL
~ B~
_____________________
tC__
BSYL
___________________________________________________tB_D_S___ ~.....-----DSL
2688 drw 09
TIMING WAVEFORM OF SLAVE(2)
CS
(TO MASTER)
---------------f
/
:-1 .
URauT
!LR
(FROM MASTER) -------------4--~
SELoUT
tSEL ~~---~--I-------------------------------------~
(FROM MASTER)
2688 drw 10
NOTES:
1. tAps is only necessary to guarantee left side access. Within this set-up time, one side or the other will gain access, but neither will have priority.
2. CS inputs are ignored when configured as a Slave, allowing the Master to control port selection with uR_OUT and SEL_OUT signals.
7.7
6
IDT7MB6036/6046/6056 (128K!64K!32K
x 16)
CMOS DUAL-PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MB6036
I
.............T
:D:D:~
:blkJwl
t
2.590
""2]"1'0
I"
~
.........................
~
2.490
---""2.5iCi""---./
.~~
...QML
11
0.400
2.190
2.210
2.310
1.990
2.010
1
TOP VIEW
PIN 1
0.100
TYP .
+
.........................
.........................
DDDD
DDDD
III]
III]
III]
III]
I::::::::::::::::::::::::
BOTTOM VI EW
-.J j.
0.100
TYP.
2688 drw 11
7MB6046
I
t=:
.............T
2.590
2.610
~
2.490
I"
---2']"1'0---.!
.........................
:D:D:~
2.310
:W:kJwl
t
TOP VIEW
PIN 1
· . · . 0·. ·. . 0·
+
.........................
• ~-&m-
11
2.190
2.210
...1..22Q....
2.010
1
0.015
0.025
DD
lID
.........................
.........................
BOTTOM VI EW -.J j.
III]
0.345
"'OAo'O
III]
III]
0.100
TYP.
7.7
2688 drw 12
7
IDT7MB6036/6046/6056 (128K164K132K x 16)
CMOS DUAL-PORT RAM SHARED MEMORY MODULE
COMMERCIAL TEMPERATURE RANGE
7MB6056
I
I"
~
..........................
............T
2.590
~
2.610
2.490
---~
0.345
""1i:4oO
:D:D:~
.0.0
.
D1
t
1.990
2.010
1
.........................
TOP VIEW
0.100
TYP .
t.........................
.........................
1
2.190
2.210
2.310
PIN 1
.. r--mt-
0.015
0.025
DD
!Ill
!Ill
!Ill
!Ill
:::::::::::::::::::::::::
BonOM VIEW
+\\4
0.100
TYP.
7.7
2688 drw 13
8
64K x 16
32K X 16
CMOS DUAL-PORT
STATIC RAM MODULE
t;)
Integrated Device Technology, Inc.
PRELIMINARY
IDT7MB1006
IDT7MB1008
FEATURES
DESCRIPTION:
• High density 1M/512K CMOS dual-port static RAM
module
• Fast access times: 25ns (max.)
• Fully asynchronous read/write operation from either port
• Easy to expand data bus width to 32 bits or more using
the master/slave function
• Separate upper and lower byte control
• On-chip port arbitration logic
• INT flag for port-to-port communication and BUSY flag for
maintaining data coherency
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted PQFP (plastic quad flatpack) components on a 132-pin FR-4 QIP (Quad In-line Package)
• Single 5V (±10%) power supply
• Input/outputs directly TTL compatible
The IDT7MB1 006/1 008 is a 64K x 16/32Kx 16 high-speed
CMOS dual-port static RAM module constructed on a multilayer epoxy laminate (FR-4) substrate using eight IDT7025
(8K x 16) dual-port RAMs or depopulated using only four
IDT7025 dual-port RAMs. The IDT7MB1 006/1 008 module is
designed to be used as stand-alone dual-port RAM or as a
combination master/slave dual-port RAM for 32-bit or wide
word systems. Using the IDT master/slave approach in such
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via additional control signals SEM
and INT. BUSY flags are provided to maintain data coherency
between ports.
The IDT7MB1 006/1 OOB module is packaged on a FR-4
132-pin QIP (Quad In-line Package) with dimensions of only
3.51" x 1.61" x 0.31 ". Maximum access times as fast as 25ns
are available over the commercial temperature range.
All inputs and outputs of the IDT7MB1006/1008 are TTL
compatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refreshing for operation of the module.
PIN CONFIGURATION
GND
M/"S"
Vee
L_BUSY(O)
L_A(O)
L_A(2)
L_A(4)
GND
L_A(6)
L_A(8)
UUSY(4)
L_A(10)
L_A(12)
L_A(14)
L_LB
L_BUSY(2)
GND
Vee
Lj5s
L Rfii
U/O(O)
U/O(2)
L_BUSY(6)
U/O(4)
U/O(6)
GND
U/O(8)
LJ/O(10)
LJ/O(12)
LJ/O(14)
Vee
L_BUSY(7)
GND
(1)
GND
GND
Vee
R_BUSY(O)
R_A(O)
R_A(2)
R_A(4)
GND
R_A(6)
R_A(8)
R_BUSY(4)
R_A(10)
R_A(12)
R_A(14)
R_iB
R_BUSY(2)
GND
Vee
Rj:S
R_RlW
RJ/O(O)
RJ/O(2)
R_BUSY(6)
R_I/O(4)
RJ/O(6)
GND
R_I/O(8)
RJ/O(10)
R_I/O(12)
R_I/o(14)
Vee
R_BUSY(7)
GND
1 • • 67 GND
2 • • 68 GND
3 • • 69Vee
4 • .70 UNT
5 • • 71 L_A(1)
6 • • 72 L_A(3)
7 • • 73 L_A(5)
8 • • 74 GND
9 • • 75 L_A(7)
10. • 76 L_A(9)
11 • • 77 L_BUSY(1)
12 • • 78 L_A(11)
13 • • 79 L_A(13)
14 • • 80 L_A(15)
15 • • 81 L_UB
16 • • 82 L_BUSY(5)
17 • • 83 GND
18 • • 84 Vee
19 • • 85 L_SEM
20 • • 86 LjjE"
21 • • 87 LJ/O(1)
22. • 88 U/O(3)
23 • • 89 L_BUSY(3)
24 • • 90 U/O(5)
25 • • 91 U/O(7)
26 • • 92 GND
27. • 93 LJ/O(9)
28 • • 94 U/O(11)
29 • • 95 U/O(13)
30. • 96 LJ/O(15)
31 • • 97 Vee
32 • • 98 GND
33 • • 99 GND
132 • • 66
131 • • 65
130 • • 64
129 • • 63
128 • • 62
127 • • 61
126 • • 60
125 • • 59
124 • • 58
123 • • 57
122 • • 56
121 • • 55
120 • • 54
119 • • 53
118 • • 52
117 • • 51
116 • • 50
115 • • 49
114 • • 48
113 • • 47
112. • 46
111. • 45
110. .44
109 • • 43
108. • 42
107 • • 41
106. • 40
105 • • 39
104 • • 38
103 • • 37
102 • • 36
101 • • 35
100 • • 34
GND
GND
Vee
RJN"T
R_A(1)
R_A(3)
R_A(5)
GND
R_A(7)
R_A(9)
R_BUSY(1)
R_A(11)
R_A(13)
R_A(15)
R_DB
R_BUSY(5)
GND
Vee
R SEM
R=5t
RJ/O(1)
R_I/O(3)
R_BUSY(3)
RJ/O(5)
RJ/O(7)
GND
R_I/O(9)
RJ/O(11)
RJ/O(13)
RJ/O(15)
Vcc
GND
GND
PIN NAMES
Right Port
Left Port
L
L
L
L
L
L
A (0-15)
I/O (0-15)
RlW
CS
OE
BUSY(0-7)
Description
R A (0-15)
R I/O (0-15)
R RIW
Address Inputs
Data Inputs/Outputs
ReadIWrite Enables
R CS
R OE
R BUSY(0-7)
Chip Select
Output Enable
Busy Flags
Interrupt Flag
Semaphore Control
Master/Slave Control
Power
Ground
R_INT
R__SEM
L_INT
L SEM
M/S
Vee
GND
2803 tbl 01
2803 drw 01
alP
TOP VIEW
NOTES:
1. For the I DT7MB 1008 (32K x 16) version, Pins 53 & 80 must be connected
to GND for proper operation of the module.
CEMOS is a trademark of Integrated Device Technology, Inc.
APRIL 1992
COMMERaALTEMPERATURERANGE
DSC-7049/3
(-
L_BUSYO-7
L_A15
L_A14
L_A13
I
I
I
I
74FCT138
j
I
L_Ao-12
L_OE
L_R/W
...
I
~,-.
L
I
74FCT138
2803 drw 02
7MB1008
-
•
R_l/Oo-15
RLB
R::JJB
R RlW
"'"-
i 74FCT138
L_l/Oo-15
L_LB
L UB
R::::Ao-12
I
I
I I
L_Ao-12
L_OE
L_RlW
1
11
III
~~LIGSRij
7025
I
R-BE
L
74FCT138
I
CSLGSRij
7025
~CSLGSR~~ GSL GSR
7025
7025
I
f
--.-
I I I
I
I
2803 drw 03
7.S
2
IDT7MB100S/100S (S4K!32K X 1S)
CMOS DUAL·PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
VTERM
Grade
Ambient
Temperature
GND
Vee
Commercial
O°C to + 70°C
OV
5.0V± 10%
28031bl 02
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Vee
Supply Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
GND
Supply Voltage
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
0.8
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
Rating
Terminal Voltage with
Respect to GND
Value
Unit
-0.5 to +7.0
V
°C
TA
Operating Temperature
o to +70
T81AS
Temperature. Under Bias
-10 to +85
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
NOTE:
28031bl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V
2803 Ibl 03
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)
7MB10061B
Symbol
Parameter
Test Conditions
Max.
Unit
CINl
Input Capacitance
(CS, BUSY, SEM, INl)
VIN = OV
15/15
pF
CIN2
Input Capacitance
(Data, Address,
All Other Controls)
VIN = OV
100/60
pF
COUT
Output Capacitance
(Data)
VOUT= OV
100/60
pF
2803 Ibl 05
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = O°C to + 70°C)
Symbol
Parameter
Test Conditions
IDT7MB1006
Min.
Max.
IDT7MB1008
Min.
Max.
Unit
Ice2
Dynamic Operating
Current
(Both Ports Active)
Vee = Max., CS::; VIL, SEM ~ VIH
Outputs Open, f = fMAX
-
960
-
680
mA
ICCl
Dynamic Operating
Current
(One Port Active)
Vee = Max., L_CSor R_CS~ VIH,
Outputs Open, f = fMAX
-
760
-
480
mA
1581
Standby Supply
Current
(TTL Levels)
Vee= Max., L_CSand R_CS~VIH
Outputs Open, f = fMAX
L SEM and R SEM ~ Vee - 0.2V
-
565
-
285
mA
IS82
Full Standby
Supply Current
(CMOS Levels)
L_CSand R_CS~ Vee· 0.2V
VIN > Vee - 0.2V or < 0.2V
L_SEM and R_SEM ~ Vee - 0.2V
-
125
-
65
mA
2803 tbl 06
7.S
3
IDT7MB1006/100S (64K132K X 16)
CMOS DUAL·PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = ooe to + 70°C)
Symbol
IDT7MB1006
Min.
Max.
Test Conditions
Parameter
IDT7MB1008
Min.
Max.
Unit
IILlI
Input Leakage
(Address & Other Controls)
Vee = Max.
VIN = GND to Vee
-
80
-
40
j.tA
IILlI
Input Leakage
(Data,CS,BUSY,SEM,IN1)
Vee = Max.
VIN = GND to Vee
-
10
-
10
j.tA
IILol
Output Leakage
(Data)
Vee = Max.
CS 1:11--------
NOTES:
2803 dlW 09
1. R/W is High for Read Cycles
2. Device is continuously enabled. CS = Low. UB or [8 = Low. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE= Low.
5. To access RAM, CS = Low, UB or [8 = Low, SEM = H. To access semaphore, CS = Hand SEM = Low.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is Low during a RtW controlled write cycle, the write pulse width must be larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tOW. If OE is High during a R!W controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS, UB, LB CONTROLLED TIMING)(1,3,5,8)
twc
ADDRESS
CS
~(
~
_tAS(6)_
UB or LB
'"
)(
..
tAW
)1'
.. tWR(7)
twp (2)
II
~
)1'
~~
ANI
r.:-_t_DW
_____
..
DATAIN
---------------------------KC
~I._____tD_H~
DATA VALID
==>1)1--------
2803 dlW 10
NOTES:
1. RtW must be high during all address transitions.
2. A write occurs during the overlap (twp) of a Low UB or [8 and a Low CS and a Low RtW for memory array writing cycle.
3. twR is measured from the earlier of CS or RtW (or SEM or RtW) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the RtW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during an RfiJ controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
7.8
10
IDDMB1006/1008 (64K!32K X 16)
CMOS DUAL-PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
tOH
14----
VALID ADDRESS
Ao-A2.
tAA
----I~
VALID ADDRESS
SEM
DATAo
RIW
DE
2803 drw 11
NOTE:
1. CS = High for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
AOA-A2A
SIDE(2) "A"
MATCH
X. . . ______
RiWA
AOB-A2B
SIDE(2) "8"
RiWB
2803 drw 12
NOTES:
1. DOR = DOL = Low, L_CS = R_ CS = High. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "Bn is the opposite port from "A".
3. This parameter is measured from RfiiJA or SEMA going High to RtWB or SEMB going High.
4. Iftsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.8
11
IDT7MB1006/1008 (64K/32K X 16)
CMOS DUAL·PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ WITH BUSY (MIS;?: VIH)(2)
twc
ADDRR
)(
)(
MATCH
RIWR
twp
~:\..
/~
tDH
tow
)(
DATAIN R
)k
VALID
i*tAPS (1)
ADDRL
MATCH
~
/
I-tBDA
( /"
BUSYL
tBDD-
two 0
)~
DATAoUT L
tODD (3)
WRITE CYCLE LEFT PORT
(RIGHT PORT READ = BUSY)
READ CYCLE
RIGHT PO RT
NOTES:
1. To ensure that the earlier of the two ports wins.
2. L CS = R CS = Low
3.
= Lowtor the reading port.
2803 drw 13
OE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (MIS:::;; VIL)(1,2)
twc
ADDRR
)K
RlWR
)(
MATCH
twp
~I'\.
•
/'1'
tDH
DATAIN R
)K
tow
>k
VALID
MATCH
ADDRL
tWDD
)~
DATAoUTL
toDD
WRITE CYCLE LEFT PORT
NOTES:
..
1. BUSY input equals High for the writing port .
2. L_CS = R_CS = Low
READ CYCLE
RIGHT PORT
2803 drw 14
7.8
12
IDT7M81006/100B (64K132K X 16)
CMOS DUAL·PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH BUSY (MIS:::; VIL)
~-------------------twP
RIW
~tWH
tWB
_-{
8USY
----------------/
2803 drw 15
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CSTIMING(1)
X
ADDR"A"
and"8" _ _ _--'
CS"A"
" '-----------'/~
CS"8"
_
BUSY"8"
x___
ADDRESS MATCH
tAPS (2) _
,
~---
tBDC -----~
, ' -_ _ _ _-+-_ _ _ _ _ _ _ _ _-+-_ _ _ _ _ _ __
-------------+-_
.. tBAC
/1'
'--------------------'
2803 drw 16
WAVEFORM OF BUSyARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDR "A"
MATCHINGADDRESS "N"
ADDR "8"
8USY"8"
_
_ _
tBAA=1
tBDA)
-
•.....--------------
NOTES:
~----------------2803 drw 17
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
WAVEFORM OF INTERRUPT TIMING(1)
twc--------~
~~~~~~~~~~~------
ADDR "A"
INTERRUPT SET ADDRESS
.....- . . . - \ tWR (4)
CS"A"
R/W"A"
INT"S"
"NS(3)~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
NOTES:
1. All timing is the same for left and right ports. Port "An may be either the left or right port. Port "8" is the port opposite from "An.
2. See InterruptTruth Table.
3. Timing depends on which enable signal is asserted IClSt.
4. Timing depends on which enable is de-asserted first.
7.B
2803drw 18
13
ID17MB1006f100B (64Kf32K X 16)
CMOS DUAL-PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF INTERRUPT TIMING(1)
~----------------tRC
)
ADDR "B"
INTERRUPT CLEAR ADDRESS
lAS (3)
CS"B"
OE"B"
t_IN_R_(3_)~
---1'
_____________________________________
INT _"B"
2803drw 19
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A'.
2. See InterruptTruth Table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable is de-asserted first.
TRUTH TABLE I: NON-CONTENTION READIWRITE CONTROL(1, 2, 3)
Inputs(l)
Outputs
RIW
OE
UB
LB
SEM
II0s -1/015
1100-1/07
H
X
X
X
X
H
Hi-Z
Hi-Z
X
X
X
H
H
H
Hi-Z
Hi-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
Hi-Z
Write to Upper Byte Only
L
L
X
H
L
H
Hi-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
Hi-Z
Read Upper Byte Only
L
H
L
H
L
H
Hi-Z
DATAoUT
Read Lower Byte Only
L
H
L
L
L
H
DATAoUT
DATAoUT
Read Both Bytes
X
X
H
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
CS
Mode
Deselected: Power Down
NOTES:
1.
2803 tbl 13
AOL-A12;eAoR-A12R
TRUTH TABLE II: SEMAPHORE READIWRITE CONTROL
Inputs
cs
OE
UB
LB
SEM
II0s -1/015
1100-1/07
H
H
L
X
X
L
DATAoUT
DATAoUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATAoUT
DATAoUT
Read Data in Semaphore Flag
X
X
X
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
X
H
H
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
---
---
H
X
S
S
L
X
X
L
X
L
L
X
X
X
L
L
Mode
Not Allowed
Not Allowed
NOTES:
1.
II
Outputs
RfilJ
2803 tbl 14
AOL-A12;eAoR-A12R
INTERRUPT/BUSY FLAGS, DEPTHIWIDTH EXPANSION, MASTER/SLAVE CONTROL,
SEMPAHORES
For more details regarding InterrupUBusy flags, depth/width expansion, master/slave control, or semaphore operations,
please consult the IDT7025 datasheet.
7.B
14
I
IDT7MB1006/100S (64K!32K X 16)
CMOS DUAL-PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MB1006
................. J
3.490
3.5fO
1
•••••••••••••••••••••••••••••••••
1.590
T.6fO
DDBDD~
[II]
lID
lID
[II]
T
1.490
T:'STO
[II]
•••••••••••••••••••••••••••••••••
.................................
----------~~
TOP VIEW
PIN1/
'Wi lin II i_iiillfF
SIDE VIEW
~ \'-0.100
0.015~1
0.025
~
TYP.
SIDE VIEW
•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••
DODD
•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••
BOTTOM VIEW
2803 drw 20
7.S
15
IDTIMB1006/100S (64K132K X 16)
CMOS DUAL-PORT STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MB1008
3.490
3.5TO
11
.................................
.................................
}~a
DDBDD
:mT .................................
=
= = =
=
1. 490
1.
1.310 5f5
.................................
0.195
MAX.
TOP VIEW
PIN1/
----lI
SIDE VIEW
i
TITITIlffiTITIlffilTfITffiffffITf
0.015
0.025
_I
t--
i
II 0.100
-II- TYP.
SIDE VIEW
.................................
.................................
.................................
.................................
2803 drw 21
BOTTOM VIEW
II
7.S
16
t;)@
8K116K x 9
CMOS DUAL-PORT
STATIC RAM MODULES
Integrated Device Technology, Inc.
PRELIMINARY
IDT7M1004
IDT7M1005
IDT7M1 004/1005 modules are designed to be used for stand
alone 9-bit word width systems where on-chip arbitration is
not needed. It is the users 'responsibility to ensure data
integrity when simultaneously accessing the same memory
location from both ports.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory.
The IDT7M1 004/1 005 modules are packaged in a 60-pin
ceramic sidebrazed DIP (Dual In-line Package). Maximum
access times as fast as 30ns are available over the commercial temperature range and 40ns overthe military temperature
range.
AIiIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
FEATURES:
• High density 8Ki16K x 9 CMOS Dual-Port Static RAM
modules
Fast access times
-commercial: 30,35,45,55, 65ns
-military: 40, 45, 55, 65, 80, 100ns
Fully asynchronous read/write operation from either port
Expand data bus width to 18 bits or more using external
arbitration
Surface mounted LCC packages allow through-hole
module to fit on a 60-pin sidebrazed DIP
Single 5V (±10%) power supply
Inputs/outputs directly TTL compatible
DESCRIPTION:
The IDT7M1 004/1 005 are 8Ki16K x 9 high speed CMOS
Dual-Port static RAM modules constructed on a co-fired
ceramic substrate using 8 IDT7012 (2K x 9) Dual-Port RAMs
or depopulated using only 4 IDT7012 Dual-Port RAMs., The
FUNCTIONAL BLOCK DIAGRAMS
x 9)
IDT7M100S (16K
~ 70121~
I
70121
r----!CEl CER
~
A13l
A12l
A11l
~~
70121
CElCER
CEl CER
I I
IrI
I
~4£C~31!... [
04 Os 06 07
74FCT138
04 Os 06 07
I
-
II
1
L--j"CEl CER
I
t
~
~CElCER~
f{C~CERt
70121
70121
70121
I/0o-al
> - 1I00-8R
BUSYR
l - f---
100010203 I
1000102031
l.:
70121 I
CEl CERr--------:-:
l-
I
RiWR
OER
Ao lOR
CS1R
-rE
A11R
A12R
A13R
CEl CER
70121 I
1
1
2797 drw 01
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
APRIL 1992
DSC·707211
7.9
IDT7M1004/IDT7M1005 (8K116K x 9)
CMOS DUAL-PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOTIM1004 {SK X 9}
L_CS
E-A12
A13
:A11
L pJjJ
LOE
L_A-O-1O
L_I/OO-8
2797 drw 02
PIN CONFIGURATION
PIN NAMES(1)
GND
Left Port
Right Port
Names
L_RIW
2
R_RIW
L_CS
R_CS
Chip Selects
L_A(O)
3
R_A(O)
L_A(1)
4
R_A(1)
Vee
L
RlW
R
R!W
ReadlWrite Enables
L_OE
R_OE
Output Enables
L_A(2)
5
R_A(2)
L_A(3)
6
R_A(3)
L_A (0-13)
R_A (0-13)
Address Inputs
L_A(4)
7
R_A(4)
L_I/O (0-8)
R_I/O (0-8)
Data InpuVOutputs
GND
8
R_A(5)
L_A(5)
9
R_A(6)
L_A(6)
10
R_A(7)
L_A(7)
11
R_A(8)
L_A(8)
12
R_A(9)
L_A(9)
13
R_A(10)
L_A(10)
14
R_A(11)
L_A(11)
15
R_A(12)
16
GND
L_A(12)
17
R_A(13)
L_A(13)
18
R_OE
L_OE
L_CS
L_I/O(O)
19
20
Rj5s
R_I/O(O)
21
22
Vee
Power
GND
Ground
2797 Ibl 01
NOTE:
1. OntheIDT7M1 004 option (8Kx9) L_AI3 and R_AI3 need to be connected
to GND for proper operation of the module.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
R_I/O(1)
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
L_I/O(1)
L_I/O(2)
23
R_I/O(2)
GND
L_IIO(3)
24
RJ/O(3)
L_IIO(4)
25
RJ/O(4)
L_I/O(5)
26
R_I/O(5)
L_I/O(6)
L_I/O(7)
L_I/O(8)
27
R_IIO(6)
28
GND
30
R_I/O(7)
R_I/O(8)
Vee
29
Vee
.2797 Ibl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DIP
TOP VIEW
2797 drw 03
7.9
2
II
IDT7Ml004/IDT7Ml005 (8K116K x 9)
CMOS DUAL-PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Vee
Parameter
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
Grade
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
Supply Voltage
GND
Supply Voltage
VIH
Input High Voltage
2.2
0
VIL
Input Low Voltage
-0.5(1)
0
-
0
V
Military
6.0
V
Commercial
0.8
V
NOTE:
2797 tbl 04
2797 tbl 03
1. VIL ~ -3.0V for pulse width less than 20ns.
CAPACITANCE TABLE (TA =
+25°e, f = 1.0MHz)
Conditions
IDT7M1004
Max.
IDT7M1005
Max.
Unit
Input Capacitance
(AD-l0, OE, RIW)
V_IN = OV
100
55
pF
C_IN(2)
Input Capacitance (Data)
V_IN = OV
100
55
pF
C_IN(3)
Input Capacitance
(A11-13, CS)
V_IN = OV
15
15
pF
COUT
Output Capacitance (Data)
V_OUT = OV
100
55
pF
Symbol
Parameter
C_IN(l)
NOTE:
1. This parameter is guaranteed by design but not tested.
2797 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to + 125°C or ooe to + 70°C)
IDT7M1004
Symbol
Parameter
Test Conditions
Min.
IDT7M1005
Max.
Max.
Unit
Ilul
Input Leakage
Vee = Max.
VIN = GND to Vee
-
40
-
80
flA
IILol
Output Leakage
Vee = Max.
CS ~ VIH, VOUT = GND to Vee
-
40
-
80
flA
VOL
Output Low Voltage
Vee = Min. IOL = 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
Vee = Min. IOH = -4mA
2.4
-
2.4
-
Min.
V
2797 tbl 06
Commercial
Test Conditions
Military
Min. Max. 11 Max. (2) Min. Max. 11 Max. (2) Unit
Symbol
Parameter
lee2
Dynamic Operating
Current (Both Ports Active)
Vee = Max., CS~ VIL,
Outputs Open, f = fMAX
-
500
870
-
560
860
rnA
leel
Standby Supply
Current (One Port Inactive)
Vee = Max., CS_L or CS_R ~ VIH
Outputs Open, f = fMAX
-
370
650
-'
430
750
rnA
IS81
Standby Supply
Current (Both Ports Inactive)
Vee = Max., CS_L and CS~ VIH
Outputs Open, f = fMAX
-
280
560
-
280
560
rnA
IS82
Full Standby Supply
Current (Both Ports Inactive)
CS_L and CS_R ~ Vee -o.2V
VIN > Vee 0.2V or < 0.2V f=O
-
60
120
-
120
240
rnA
2797 tbl 07
NOTES:
1. I DT7Ml 004 (SK x 9) version only.
2. IDT7M100S (16K x 9) version only.
7.9
3
IDT7M1004/IDT7M1005 (8K116K x 9)
CMOS DUAL·PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figures 1 & 2
2797 tbl 08
+5V
+5V
4800
4800
DATAoUT - -...- - -.....
DATAoUT
2550
~
2550
30pF*
5pF*
2797 drw 05
2797 drw 04
"Including scope and jig.
Figure 2. Output Load (For tCHZ, leLz, tOHz,
tOLZ, tWHZ, tow)
Figure 1. Output Load
7.9
4
IDT7M1004/1DT7M1005 (8K116K x 9)
CMOS DUAL·PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V -+ 10%, TA = -55°C to + 125°C or DoC to +70°C)
Symbol
Parameter
·30(9)
·80(10)
·100(lQ)
·35(9)
·40
·45
·65
·55
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
30
-
35
-
40
-
45
-
55
-
65
---
80
-
100
-
ns
1M
Address Access Time
-
30
35
-
40
-
45
-
80
-
100
ns
-
30
35
-
40
-
45
55
-
65
Chip Select Access
Time
-
55
tACS(2)
-
65
-
80
-
100
ns
tOE
Output Enable Access
Time
-
15
-
20
-
20
-
25
-
30
-
35
-
40
-
45
ns
tOH
Output Hold from
Address Change
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tCl2(l)
Chip Select to Output
in Low Z
3
-
3
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tCHZ(l)
Chip Deselect to Output
in High Z
-
15
-
15
-
15
-
20
-
25
-
30
-
35
-
40
ns
tOLZ(l)
Output Enable to
Output in Low Z
3
-
3
-
3
-
5
-
5
-
5
-
5
-
5
-
ns
tOHZ(l)
Output Disable to
Output in High Z
-
15
-
15
-
15
-
20
-
25
-
30
-
35
-
40
ns
tPU(1)
Chip Select to Power
UpTime
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tPO(1)
Chip Deselect to Power
UpTime
-
50
-
50
-
50
-
50
-
50
-
50
-
50
-
50
ns
WrileCycle
twe
Write Cycle Time
30
-
35
-
55
-
80
-
100
30
35
40
-
45
50
-
55
-
60
-
ns
-
-
65
25
-
45
Chip Select to End of
Write
-
40
tcW(2)
tAw
Address Valid to End
of Write
25
-
30
-
35
-
40
-
45
-
50
-
55
-
60
-
ns
0
-
0
-
0
55
-
60
0
-
0
0
40
-
45
-
50
-
ns
50
tAs
Address Set-Up Time
0
-
0
-
0
twp
Write Pulse Width
25
-
30
-
35
twR
Write Recovery Time
0
-
0
-
0
tow
Data Valid to End of
Write
20
-
25
-
25
-
0
-
0
35
-
40
0
-
0
25
-
30
-
ns
ns
ns
ns
tOH
Data Hold Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tOHZ(l)
Output Disable to
Output in High Z
-
15
-
15
-
15
-
20
-
25
-
30
-
35
-
40
ns
twHZ(l)
Write Enable to Output
in Hiah Z
-
15
-
15
-
15
-
20
-
25
-
30
-
35
-
40
ns
toW(1)
Output Active from End
of Write
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
NOTES:
1. ihis parameter is guaranteed by design but not tested.
2. To access RAM array, CS::; VIL.
3. Master mode is not available on this module.
4. The module is always in the Slave Mode.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
6. To ensure that the earlier of the two ports wins.
7. To ensure that the write cycle is inhibited during contention.
8. To ensure that a write cycle is completed after contention.
9. This speed is currently available in commercial versions only.
10. This speed is currently available in military versions only.
7.9
2797 tbl 09
5
IDT7M1004/IDT7M1005 (8K116K x 9)
CMOS DUAL·PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE) (1, 2,4)
ADDRESS
DATAoUT
2797 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE) (1, 3, 5)
tAcs
tCHZ (6) ------<~
DATAoUT
Icc
CURRENT
IS8
2797 drw 07
NOTES:
1. RiW is high for Read Cycles
2. Device is continuously enabled, CS = L. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with cs transition low
4. DE= L
5. To access RAM, CS = L. To access semaphore, CS = H.
6. This parameter is guaranteed by design but not tested.
7.9
6
IDT7M1004/IDT7M1005 (8K/16K x 9)
CMOS DUAL-PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIW CONTROLLED TIMING) (1, 3, 5, 8)
~
ADDRESS
OE
Cs
Rm
DATAoUT
DATAIN
2797 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,3,5,8)
twc
ADDRESS
tAW
twp (2)
RlW
DATAIN
2797 drw 09
NOTES:
1. RiW must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low RiW for memory array writing cycle.
3. twR is measured from the earlier of CS or RiW going high to the end of write cycle.
4. During this period, the 110 pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 110 drivers to turn off and data
to be placed on the bus for the required tow. If DE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
7.9
7
ID17M1004/ID17M1005 (8K116K x 9)
CMOS DUAL-PORT STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
7M1004
I
3.085
I
~4~---------3.150----------~~~
riIt.590
620
UU·
~
0.220
0.270
0.320
* +
flTIfrrfffflfl
fffl
rfffITffffflfF---.
~I+,
~
~ 14-, ~ -
0.010
0.050
0.035
0.060
0.015
0.022
0.100
TYP.
t
0.007
0.013
SIDE VIEW
~
0.175
SIDE VIEW
............ ··········-1
~D
~
IJ
!;J
BOTTOM VIEW
2797 drw 10
7M100S
~I~.-----------;:~:;
~I
[/Jf~;g
-t~
0.007
0.220
0.270
0.230
0.320
+ +
T: ,,,,14-,.,....,
,ft" ,,,'1m f' ,,,"ff ,14--,,, r,~
-.---. -
0.01 0
0.050
~
D.OT3
SIDE VIEW
.j
0.035
0.060
0.015
0.022
0.100
TYP.
0.125
0.175
SIDE VIEW
~
TI
11 _____ _____
lio----r
~~ ~
llJ ____
____ _____
BOTTOM VIEW
7.9
11
2797 drw 11
8
__
G
Integrated Device Technology, Inc.
128K x 8
64Kx8
CMOS DUAL-PORT
STATIC RAM MODULE
PRELIMINARY
IDT7M1001
IDT7M1003
FEATURES
DESCRIPTION:
• High density 1M/512K CMOS dual-port static RAM
module
• Fast access times:
commercial - 25, 30, 35, 40, 50, 65ns
military - 35, 40, 50, 65, 80ns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (Ieadless chip carriers) components on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL compatible
The IDT7M1001/1DT7M1003 is a 128K x 8 /64K x 8 highspeed CMOS dual-port static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
dual-port RAMs and two lOT FCT138 decoders or depopulated using only four IDT7006s and two decoders.
This module provides two independent ports with separate
control, address, and 110 pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (SEM) "handshake" signaling. The IDT7M1 001/1 003 module is designed
to be used as stand-alone dual-port RAM where on-chip
hardware port arbitration is not needed. It is the users
responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1001/1003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with dimensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 25ns over the commercial temperature range and
35ns over the military temperature range are available.
All inputs and outputs of the IDT7M1 001/1 003 are TTL
compatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refreshing for operation of the module.
All lOT military module semiconductor components are
manufacured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN CONFIGURATION(1)
Vee
GND
RiWR
OER
CSR
SEMR
AOR
Am
A2R
A3R
A4R
ASR
ASR
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A1SR
A1SR
GND
I/OOR
110m
1I02R
1I03R
1I04R
1I0SR
I/OSR
RlWL
OEL
CSL
'S'EfJL
AOL
A1L
GND
A2L
A3L
A4L
ASL
ASL
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A1SL
A1SL
1I00L
1I01L
1I02L
1I03L
1I04L
1I0SL
I/OSL
1/07L
GND
PIN NAMES
Left Port
Right Port
A (O-16)L
1/0 (0-7)L
A (O-16)R
RlWL
RlWR
Address Inputs
Data Inputs/Outputs
ReadIWrite Enables
CSL
OEL
CSR
Chip Select
OER
SEMR
Output Enable
Semaphore Control
1/0 (0-7)R
SEML
Description
Vee
Power
GND
Ground
2804 tbl 01
1/07R
Vee
DIP
TOP VIEW
2804 drw 01
NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 & 43 must be connected
to GND for proper operation of the module.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC·7006/3
"'1992 Integrated Device Technology, Inc.
7.10
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
7M1001
I
l
r----4
7006
r----
-
.----
.-------
l
CsRi-
CSL
I
7006
-
,.--
J l
7006
,.--
CsL CSl-
r-
1
J l
r-
-
I-- ,----
CsL CSl t-
r- -CSL
CsR
L
-4
RJ/OO-7
--
I
-4
R_R/W
R_OE
R_AO-13
L
I
74FCT138
74FCT138
L_AO-13
USE
L_RiW
I
I
'I
LJ/OO-7
J
7006
'---
'----
'----
-
-
CSL
CSR l -
CsL CSl
I-.
r----
'--
7006
r-
r--
'--
7006
-
CSL CSl
r-
I--
I-.
-
1
I
r-----
7006
1I
[
I
t.-
r--
CsR r---
CSL
'--
7006
1 r
r
-
'--
\4\4-
1
2804 drw 02
7M1003
4
RJ/OO-7
R_RlW
R_OE
U:s
I
I
R_AO-13
74FCT138
I
Lj5E"
I
II
I
I
I
'-,
U/OO-7
CSl
Cs,~
7006
I
CSl
e&~
7006
1
CSl
e&~
7006
74FCT138
1
I
II
~,
7006
es'r
1
2804 drw 03
7.10
2
•
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
T81AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Military
-55°C to + 125°C
OV
5.0V
O°C to +70°C
OV
5.0V
Commercial
Vee
± 10%
± 10%
2804 tbl 04
2804 tbl 02
NOTE:
RECOMMENDED DC OPERATING
CONDITIONS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE(1)
Symbol
(TA = +25°C,
Parameter
f = 1.0MHz)
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
0.8
Max.
1. VIL (min.) = -3.0V for pulse width less than 20ns.
Unit
CINl
Input Capacitance
(CSorSEM)
VIN
= OV
15
pF
CIN2
Input Capacitance
(Data, Address,
All Other Controls)
VIN
= OV
100
pF
COUT
Output Capacitance
(Data)
VOUT
= OV
100
V
2804 tbl 05
NOTE:
pF
2804 tbl 03
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(Vee
= 5V ± 10%
TA
=-55°C to +125°C or O°C to +70°C)
Commercial
Test Conditions
Military
Min. Max. 11 Max. (2) Min. Max. 11 Max. (2) Unit
Symbol
Parameter
lee2
Dynamic Operating
Current (Both Ports Active)
Vee = Max., CS ~ VIL, SEM ;::: VIH
Outputs Open f - fMAX
-
940
660
-
1130
790
rnA
leel
Standby Supply
Current (One Port Active)
Vee = Max., L_CS or R_CS;::: VIH
Outouts Op_en f - fMAX
-
750
470
-
905
565
rnA
1581
Standby Supply
Current (TTL Levels)
Vee = Max., L_CS and R_CS;::: VIH
Outputs Open, f = fMAX
-
565
285
-
685
345
rnA
1582
Full Standby Supply
Current (CMOS Levels)
L_CS and R_CS;::: Vee -O.2V
VIN > Vee 0.2V or < 0.2V
L SEM and R SEM;::: Vee -O.2V
-
125
65
-
245
125
rnA
L SEM and R SEM > Vee -O.2V
2804 tbl 06
NOTES:
1. IDT7M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.
7.10
3
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = -55°C to +125°C and O°C to +70°C)
Symbol
Parameter
IDT7M1001
Min.
Max.
Test Conditions
IDT7M1003
Min.
Max.
Unit
IILlI
Input Leakage
(Address, Data & Other Controls)
Vee = Max.
VIN = GND to Vee
-
80
-
40
~
IILlI
Input Leakage
(CSand SEM)
Vee = Max.
VIN = GND to Vee
-
10
-
10
~
Illol
Output Leakage
(Data)
Vee = Max.
CS ~ VIH, VOUT = GND to Vee
-
80
-
40
~
Val
Output Low Voltage
Vee = Min.
IOL = 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
Vee = Min.
IOH = -4mA
2.4
-
2.4
-
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fail Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
+5V
+5V
4800
DATAoUT
------.-----1
2550
•
4800
DATAoUT - - - - - - r - - - - - i
30 pF*
2550
5 pF*
2804 drw 04
2804 drw 05
Figure 1. Output Load
Figure 2. Output Load
(for tClZ, tCHZ, tOlZ. tOHZ, tWHZ, tow)
"Including scope and jig.
7.10
4
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V
± 10%, TA = -55°C to + 125°C and ooe to +70°C)
_25(5)
Symbol
Parameter
Min.
_30(5)
Max.
Min.
_35(5)
Max.
Min.
-40
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
25
-
30
-
35
-
40
-
ns
1M
Address Access Time
-
25
-
30
-
35
-
40
ns
tACS(2)
Chip Select Access Time
-
25
-
30
-
35
-
40
ns
tOE
Output Enable Access TIme
-
13
-
15
-
20
-
25
ns
tOH
Output Hold From Address Change
3
-
3
-
3
-
3
Chip Select to Output in Low Z
3
-
3
-
3
-
3
-
ns
tCLZ(I)
tCHZ(I)
Chip Deselect to Output in High
-
18
-
20
-
20
20
ns
tOLZ(I)
Output Enable to Output in Low Z
3
-
3
-
3
-
-
ns
tOHZ(I)
Output Disable to Output in High
-
18
-
20
-
20
-
20
ns
tPU(I)
Chip Select to Power Up TIme
0
-
0
-
0
-
0
-
ns
tPO(I)
Chip Disable to Power Down Time
-
50
-
50
-
50
-
50
ns
tsop
SEM Flag Update Pulse (OE or SEM)
12
-
12
-
15
-
15
-
ns
Z
Z
3
ns
Write Cycle
twc
Write Cycle TIme
25
-
30
-
35
-
40
-
ns
tcW(2)
Chip Select to End of Write
20
-
25
-
30
-
35
-
ns
tAw
Address Valid to End of Write
20
-
25
-
30
-
35
-
ns
tAS1(3)
Address Set-up to Write Pulse TIme
5
-
5
-
5
-
5
-
ns
tAS2
Address Set-up to
0
-
0
-
0
-
0
-
ns
twp
Write Pulse Width
20
-
25
-
30
-
35
-
ns
twR(4)
Write Recovery TIme
0
-
0
-
0
-
0
-
ns
tow
Data Valid to End of Write
15
-
20
-
25
-
30
-
ns
tOH(4)
Data Hold TIme
0
-
0
-
0
-
0
-
ns
es TIme
-
18
-
20
-
20
-
20
ns
-
18
-
20
-
20
-
20
ns
Output Active from End of Write
0
-
0
-
0
-
0
-
ns
SEM Flag Write to Read Time
10
-
13
-
15
-
15
-
ns
10
-
13
-
15
-
15
-
ns
-
50
-
55
-
60
-
65
ns
35
-
40
-
45
-
50
tOHZ(1)
Output Disable to Output in High
twHZ(1)
Write Enable to Output in High
toW(I.4)
tSWRO
tsps
Z
Z
SEM Flag Contention Window
Port-to-Port Delay Timing
twoO(6)
Write Pulse to Data Delay
toOO(6)
Write Data Valid to Read Data Valid
NOTES:
1. This parameter is quaranteed by design but not tested.
2. To access RAM CS ~ VIL and SEM <: VIH. To access semaphore, CS <: VIH and SEM ~ VIL.
3. tAS1= 0 if RNi is asserted low simultaneously with or after the CS low transition.
4. For CS controlled write cycles, twR= 5ns, tOH= 5ns, tow= 5ns.
5. Preliminary specifications only.
6. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.10
ns
2804 tbl 09
5
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ± 10%, TA = -55°C to +125°C and O°C to +70°C)
-50
Symbol
Parameter
Min.
-65
Max.
Min.
-80
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle TIme
50
-
65
-
80
-
ns
tAA
Address Access TIme
-
50
65
-
80
ns
tACS(2)
Chip Select Access Time
-
50
65
-
80
ns
tOE
Output Enable Access TIme
-
30
-
35
-
40
ns
tOH
Output Hold From Address Change
3
-
3
-
3
-
ns
tCLZ(1)
Chip Select to Output in Low Z
3
-
3
-
3
-
ns
30
-
35
ns
-
3
-
ns
tCHZ{l)
Chip Deselect to Output in High Z
-
25
tOLZ{l)
Output Enable to Output in Low Z
3
-
tOHZ{l)
Output Disable to Output in High Z
t?u(1)
Chip Select to Power Up TIme
tPO{l)
Chip Disable to Power Down TIme
tsop
SEM Flag Update Pulse (OE or SEM)
-
3
25
-
30
-
35
ns
-
0
-
0
-
ns
-
50
-
50
-
50
ns
15
-
20
-
20
-
ns
0
Write 0 cle
twc
Write Cycle Time
50
-
65
-
80
-
ns
tcW(2)
Chip Select to End of Write
40
-
50
-
55
-
ns
tAw
Address Valid to End of Write
40
-
50
-
55
-
ns
tAS1(3)
Address Set-up to Write Pulse TIme
5
-
5
-
5
-
ns
tAS2
Address Set-up to
0
-
0
-
0
-
ns
twp
Write Pulse Width
40
-
45
-
50
-
ns
twR(4)
Write Recovery TIme
0
-
0
-
0
-
ns
tow
Data Valid to End of Write
35
-
40
-
45
-
ns
0
-
0
-
ns
ns
CS TIme
tOH(4)
Data Hold TIme
0
-
tOHZ{l)
Output Disable to Output in High Z
-
25
-
30
-
35
twHZ{l)
Write Enable to Output in High Z
-
25
-
30
-
35
ns
tow{l.4)
Output Active from End of Write
0
-
0
-
0
-
ns
tSWRO
SEM Flag Write to Read Time
15
-
15
-
15
-
ns
tsps
SEM Flag Contention Window
15
-
15
-
15
-
ns
ns
Port-to-Port Delay TIming
twoO(5)
Write Pulse to Data Delay
-
70
-
85
-
95
toOO(5)
Write Data Valid to Read Data Valid
-
55
-
70
-
80
NOTES:
1. This parameter is quaranteed by design but not tested.
2. To access RAM CS::; VIL and SEM ~ VIH. To access semaphore, CS ~ VIH and SEM ::; VIL.
3. tAS1= 0 if Rm is asserted low simultaneously with or after the CS low transition.
4. For CS controlled write cycles, twR= 5ns, tOH= 5ns, tow= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.10
ns
2804 tbl 10
6
•
I
ID17M1001/1003 (128K164K X 8)
CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE)(1,2,4)
I~--------------------- tRc--------------------~
tAA
DATA OUT
2804 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE)(1,3,5)
1 _ - - - - - lACS
----------+1
1 4 - - - - I CHZ(6) --------+I
IOHZ(6) _
DATA VALID
DATA OUT
,eo,"}
1 4 - - - - IClZ (6) ------~f_3~41i:.--------t_--------:------1
Icc
CURRENT
1 4 " - - - - I PO (6)
50%
-----5-0-%-t+l~__
ISB
2804 drw 07
NOTES:
1. RNi is High for Read Cycles
2. Device is continuously enabled. CS = Low. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE = Low.
5. To access RAM, CS = Low, SEM = H. To access semaphore, CS = Hand SEM = Low.
6. This parameter is guaranteed by design but not tested.
7.10
7
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (R/W CONTROLLED TIMING)(1,3,5,8)
twe
ADDRESS
==:)~
)~
r-
tOHZ ( 9 ) - -
tAW
~\..
~,
_tAS(6)
tWR(7)
twp(2)
'~
/'
_toW(9) _ _
I - tWHZ(9)
DATA OUT
DATA
IN
,
"-
(4)
'1
-K~~-D-A-T-A
tow
.....................................................................................
VA-~-'ID~
.1I•
"-
(4)
)-
tOH
..............................
..............................----
NOTES:
2804 drw 08
1. RtW is High for Read Cycles
2. Device is continuously enabled. CS = Low. US or LS = Low. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE= Low.
5. To access RAM, CS = Low, US or
= Low, SEM = H. To access semaphore, CS = Hand SEM = Low.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is Low during a RtW controlled write cycle, the write pulse width must be larger of twp or {twz + tow} to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tOW. If OE is High during a RtW controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
rn
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,3,5,8)
twc
ADDRESS
~K
..
f4--- t AS(6)
RIW
)(
,
tAW
/~
~,
.
tWR(7) + - -
tWP(2)
/r
'\.
J_
.. _ t.....
OH---1
r-_tDW
__
DATA
IN
-----------------!(C
..DATA VALID
=>I~------
NOTES:
1. RtW must be high during all address transitions.
2804 drw 09
2. A write occurs during the overlap (twp) of a Low US or
and a Low CS and a Low RtW for memory array writing cycle.
3. twR is measured from the earlier of CS or RtW (or SEM or RtW) going high to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the RtW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is low during a RtW controlled write cycle, the write pulse width must be the larger of twP or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
rn
7.10
8
IDTIM1001/1003 (128K/64K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
tOH
~---
t AA
---~
VALID ADDRESS
Ao -A2
DATA 0
2804 drw 10
NOTE:
1. CS = High for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
AOA-A2A
SIDE(2) "A"
MATCH
X~
_____
::----~1;-tsp-s-------AOB-A2B
SIDE(2) "8"
RIWB - - - - - - - - - - - '
SEMB
2804 drw 11
NOTES:
1. DOR = DOL = Low, L_CS = R_CS = High. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "S" is the opposite port from "A".
3. This parameter is measured from RfiJA or SEMA going High to RIWB or SEMB going High.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.10
9
IDT7M1001/1003 (128K/64K X 8)
CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1)
twc
)(
ADDR R
)(
MATCH
twp
RIW R
'!!~
/V
tDH
tDW
)K:
DATA IN R
>k
VALID
ADDRL
MATCH
tWDD
)~
DATA OUT L
tDDD
WRITE CYCLE LEFT PORT
NOTE:
1. L_CS
YCLE
"""'RIGHT
REA5CPORT
2804 drw 12
= R_CS = Low
TRUTH TABLES
TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
cs
Outputs
RIW
OE
SEM
1/00-1/07
Mode
X
X
H
Hi-Z
Deselected: Power Down
L
L
X
H
DATAIN
Write to Both Bytes
L
H
L
H
DATAoUT
Read Both Bytes
X
X
H
X
Hi-Z
Outputs Disabled
H
NOTE:
1. AOL - A12
2804 tbl 11
*' AOR -
A12R
TABLE II: SEMAPHORE READIWRITE CONTROL(1)
Outputs
Inputs
cs
H
X
L
RIW
OE
SEM
1/00-1/07
Mode
H
L
L
DATAoUT
Read Data in Semaphore Flag
X
L
DATAIN
Write DINa into Semaphore Flag
X
L
S
X
-
NotAl/owed
2804 tbl 12
NOTE:
1. AOL-AI2*,AoR-AI2R
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
7.10
10
IDT7M1001/1003 (128K164K X 8)
CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
7M1001
I
3.190
~
4
~
I
~:~~~D:DD~DDI
TOP VIEW
PIN)'
.
0.330
MAX.
0.010
0.050
t
0.380
MAX.
t.
+"tm~~l
0.035
O.OSO
0.015
0.022
~
,
0.100
TYP.
0.S15
0.S35
0.007
0.013
SIDE VIEW
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 13
7M1003
I
I
3.190
~
4
~
.g:~~ID:DD:DDI
TOP VIEW
PIN1'"
0.010
0.070
0.310
MAX.
0.380
MAX.
t
t
!
~\4
'Q.06O
~
0.015
0.022
~~
.
0.100
TYP.
0.S15
0.S35
0.007
0.013
~
=¥~TIW~I'nmm~tm~nm:Ril'iffmffffff:m:pT=~'~l
0.035
~
,
SIDE VIEW
T
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 14
7.10
11
t;j
128K/64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE
PRELIMINARY
IDT7MP1021
IDT7MP1023
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION:
• High density 1M/512K CMOS dual-port static RAM
modules
• Fast access times: 25, 30, 35, 40, 50ns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted plastic components on a 64-lead SIMM
(Single In-line Memory Module)
• Multiple Vcc and GNO pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TIL compatible
The IOT7MP1021/1023 is a 128K164K x 8 high-speed
CMOS dual-port static RAM module constructed on a multilayer FR-4 substrate using decode logic and either eight
IOT7006 (16K x 8) dual-port RAMs for the 7MP1021 or four
IOT7006s for the 7MP1 023.
The IOT7MP1 021 /1 023 provide two independent ports
with separate control, address, and I/O pins that permit
independent and asynchronous access for reads or writes to
any location in memory. System performance is enhanced by
facilitating port-to-port communication via semaphore (SEM)
"handshake" signaling. The IOT7MP1 021/1023 modules are
designed to be used as stand-alone dual-port RAMs where
on-chip hardware port arbitration is not needed. It is the users
responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IOT7MP1021/1023 modules are packaged on a 64lead multilayer FR-4 SIMM (Single In-line Memory Module).
Maximum access times as fast as 25ns over the commercial
temperature range are available.
All inputs and outputs of the 10T7MP1 021/1 023 are TTL
compatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refreshing for operation of the module.
PIN CONFIGURATION
R_A(O)
2
1
3
VCC
L_A(O)
R_A(1)
4
5
L_A(1)
R_A(2)
6
R~(3)
7
L_A(2)
8
R_A(4)
10
GND 12
9
11
L_A(3)
L_A(4)
13
L_A(5)
15
L_A(6)
16
17
L_A(7)
18
19
L_A(8)
21
L_A(9)
22
23
L_A(10)
24
26
25
GND
L_OE
Left Port
Right Port
L_RtW
L A (0-15)
R A (O-15)
Address Inputs
L 1/0 (O-7)
R 1/0 (0-7)
Data Inputs/Outputs
L RIW
R RIW
ReadlWrite Enables
L CS
R CS
Chip Select
R_A(5)
14
R_A(6)
R_A(7)
R_A(8)
20
R_A(9)
R_A(10)
R_A(11)
R_OE 28
27
PIN NAMES
Description
R_RIW
30
29
31
R_SEM
32
33
L_CS
R_CS
34
35
L_A(11)
GND
36
37
L_A(12)
R_A(12)
38
39
L_A(13)
R_A(13)
40
41
L_A(14)
R_A(14)
42
43
L_A(15)
R_A(15)
44
45
N.C.
N.C.
45
47
L_I/O(O)
NOTE:
R_I/O(O)
48
49
L_I/O(1)
R_I/O(1)
50
51
GND
R_I/O(2)
52
1. For the IDT7MP1 023 (64K x 8) version, Pins 45 & 46 must be connected
to GND for proper operation of the module. These pins become L_A(16)
and R_A(16) respectively for the IDT7MP1021 (128K x 8) version.
53
L_I/O(2)
L_SEM
R_I/O(3)
54
55
L_I/O(3)
R_I/O(4)
56
57
L_I/O(4)
R_I/O(5)
58
59
R_I/O(6)
L_I/O(5)
60
61
R_I/O(7)
L_I/O(6)
62
64
63
L_I/O(7)
VCC
SIMM
TOP VIEW
L OE
R OE
Output Enable
L SEM
R SEM
Semaphore Control
Vce
Power
GND
Ground
II
2839 tbl 01
2839 drw 01
CEMOS is a trademark 01 Integrated Device Technology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
fI:l1992 Integrated Device Technology, Inc.
DSC·70SS/3
7.11
IDT7MP1021/1023 (128K!64K x 8)
CMOS DUAL·PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
7MP1021
L_A(16)
L_A(15)
L_A(14)
L_CS
J
~~
I
7006
GSL GSR
I
k~
7006
GSLGSR
I
7006
CSL GSR
l-
I
I
I
R_R/W
R OE
R=:A(o-13)
I
I DECODER I
I
.I
I
L_A(o-13)
L_OE
L_R/W
k
~~
7006
CSL GSR
I
DECODER
r
J
I
'-,
Cs~ ~CsLCs~
~CsLCSR~
~CSL7006CSR~
7006
7006
R_A(14)
R_A(15)
R_A(16)
i C s L7006
I
I
I
2839 drw 02
7MP1023
L_A(15)
L_A(14)
R_RlW
R35'E
R_A(O-13)
R_CS
L_A(O-13)
L_OE
L_RtW
R_A(14)
R_A(15)
L_I/O(O-7)
R_I/O(O-7)
L_SEM
..
R_SEM
2839 drw 03
7.11
2
IDT7MP1021/1023 (128K164K x 8)
CMOS DUAL-PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial Unit
Terminal Voltage with Respect to
-0.5 to +7.0
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
TA
Operating Temperature
o to +70
°C
T81AS
Temperature Under Bias
-10 to +85
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
V
GND
Vee
5.0V
± 10%
2839 tbl 04
mA
2839 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE(1)
(TA
Symbol
= +25°C, f = 1.0MHz)
Parameter
Test Conditions
Max.
Unit
CINl
Input Capacitance
(CSor SEM)
VIN = OV
15
pF
CIN2
Input Capacitance
(Data, Address,
All Other Controls)
VIN = OV
100
pF
COUT
Output Capacitance
(Data)
VOUT= OV
100
pF
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
NOTE:
1. This parameter is guaranteed by design but not tested.
Parameter
Min.
Typ.
Max.
Vee
SUPRly Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
0.8
V
NOTE:
1. VIL (min.)
Unit
2839 tbl 05
= -3.0V for pulse width less than 20ns.
2839 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V
± 10%, TA =O°C to +70°C)
IDT7MP1021/1023
Max.(2)
Min.
Max.!l)
Vee = Max., CS:s; VIL, SEM ~ VIH
Outputs Open, f = fMAX
-
940
660
mA
Standby Supply
Current (One Port Active)
Vee = Max., L_CSor R_CS~ VIH
Outputs Open, f = fMAX
-
750
470
mA
1581
Standby Supply
Current (TTL Levels)
Vee = Max., L_CS and R_CS ~ VIH
Outputs Open, f = fMAX
-
565
285
mA
IS82
Full Standby Supply
Current (CMOS Levels)
L_CSand R_CS~ Vee -O.2V
VIN > Vee 0.2V or < 0.2V
L_SEM and R_SEM ~ Vee -O.2V
-
125
65
mA
Symbol
Parameter
lee2
Dynamic Operating
Current (Both Ports Active)
leel
Test Conditions
Unit
L_SEM and R_SEM ~ Vee -O.2V
NOTES:
1. For IDT7MP1 021 (128K x 8) version only.
2. For IDT7MP1023 (64K x 8) version only.
2839 tbl 06
7.11
3
II
IDT7MP1021/1023 (128K164K x 8)
CMOS DUAL·PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = O°C to + 70°C)
Symbol
Test Conditions
Parameter
IDT7MP1021
Max.
Min.
IDT7MP1023
Max.
Min.
Unit
IILlI
Input Leakage
(Address, Data & Other Controls)
Vee = Max.
VIN = GND to Vee
-
80
-
40
~
1IL11
Input Leakage
(CSand SEM)
Vee = Max.
VIN = GND to Vee
-
10
-
10
~
IILol
Output Leakage
(Data)
Vee = Max.
CS ~ VIH, VOUT
-
80
-
40
~
-
0.4
-
0.4
V
2.4
-
VOL
Output Low Voltage
Vee = Min.
VOH
Output High Voltage
Vee
= Min.
= GND to Vee
IOL = 4mA
IOH = -4mA
2.4
V
2839 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2839 tbl 08
+5 V
4800
480n
DATAoUT--------,-------~
2550
DATAoUT--------,-------~
2550
30 pF*
2839 drw 04
5 pF*
2839 drw 05
Figure 2. Output Load
(for tClZ, tcHZ, tOlZ. tOHZ, tWHz, tow)
Figure 1. Output Load
·Including scope and jig.
7.11
4
IDTIMP1021/1023 (128K164K x 8)
CMOS DUAL-PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ± 10%, TA = DoC to +70°C)
7MP1023SxxM, 7MP1 021 SxxM
_25(5)
Symbol
Parameter
_30(5)
Min.
Max.
_35(5)
Min.
Max.
Min.
-40
Max.
Min.
-50
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
25
-
30
-
35
-
40
-
50
-
1M
Address Access Time
-
25
-
30
-
35
-
40
50
ns
tACS(2)
Chip Select Access Time
-
-
30
35
-
40
50
ns
tOE
Output Enable Access Time
-
13
-
15
-
-
20
-
25
tOH
Output Hold From Address Change
3
-
3
-
3
-
25
3
-
tCl.Z(l)
Chip Select to Output in Low Z
3
-
3
-
3
-
3
-
tCHZ(l)
Chip Deselect to Output in High Z
-
18
-
20
-
20
-
20
-
ns
30
ns
3
-
ns
3
-
ns
-
25
ns
tOLZ(l)
Output Enable to Output in Low Z
3
-
3
-
3
-
3
-
3
-
ns
tOHZ(l)
Output Disable to Output in High Z
-
18
-
20
-
20
-
20
-
25
ns
ns
!pu(1)
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
0
-
!p0(1)
Chip Disable to Power Down Time
-
50
-
50
-
50
-
50
-
50
ns
tsop
SEM Flag Update Pulse (OE or SEM)
12
-
12
-
15
-
15
-
15
-
ns
Write Cycle
twc
Write Cycle Time
25
-
30
-
35
-
40
-
50
-
ns
tcW(2)
Chip Select to End of Write
20
-
25
-
30
-
35
-
40
-
ns
tAw
Address Valid to End of Write
20
-
25
-
30
-
35
-
40
-
ns
tAS1(3)
Address Set-up to Write Pulse Time
5
-
5
-
5
-
5
-
5
-
ns
tAS2
Address Set-up to
0
-
0
-
0
-
0
-
0
-
ns
twP
Write Pulse Width
20
-
25
-
30
-
35
-
40
-
ns
twR(4)
Write Recovery Time
0
-
0
-
0
-
0
-
0
-
ns
tow
Data Valid to End of Write
15
-
20
-
25
-
30
-
35
-
ns
tOH(4)
Data Hold Time
0
-
0
-
0
-
0
-
0
-
ns
CS Time
tOHZ(l)
Output Disable to Output in High Z
-
18
-
20
-
20
-
20
-
25
ns
twHZ(l)
Write Enable to Output in High Z
-
18
-
20
-
20
-
20
-
25
ns
toW(1.4)
Output Active from End of Write
0
-
0
-
0
-
0
-
0
-
ns
tSWRO
SEM Flag Write to Read Time
10
-
13
-
15
15
-
15
-
ns
tsps
SEM Flag Contention Window
10
-
13
-
15
-
15
-
15
-
ns
Port-to-Port Delay Timing
twoO(6)
toOO(6)
Write Pulse to Data Delay
-
50
-
55
-
60
-
65
-
70
ns
Write Data Valid to Read Data Valid
-
35
-
40
-
45
-
50
-
55
ns
NOTES:
1. This parameter is quaranteed by design but not tested.
2. To access RAM CS:5: VIL and SEM ~ VIH. To access semaphore, CS ~ VIH and SEM :5: VIL.
3. tAS1= 0 if Rm is asserted low simultaneously with or after the CS low transition.
4. For CS controlled write cycles, twR= 5ns, tOH= 5ns, tow= 5ns.
5. Preliminary specifications only.
6. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.11
2839 tbl 09
5
•
IDTIMP1021/1023 (128K164K x 8)
CMOS DUAL-PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE)(1,2,4)
~------------------- tRC------------------~·~1
tM
DATAoUT
2839 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE)(1,3,5)
~---------tACS
- - - - - I..~I
!4----tcHZ (6) _ _ _~
tOHZ
DATAoUT
CURRENT
(6)_
DATA VALID
~---tcU(6)'------~~~~---------r--------------------1
ICC----------tP-U-(6-)J-+~-----------------------11--------t-PD-(-6)~~~_-_-_-~}W%
W%
ISB - - - - - - - - - - '
2839 drw 07
NOTES:
1. RiW is High for Read Cycles
2. Device is continuously enabled. CS = Low. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE= Low.
5. To access RAM, CS = Low, SEM = H. To access semaphore, CS = Hand SEM = Low.
6. This parameter is guaranteed by design but not tested.
7.11
6
IDTIMP1021/1023 (128K164K x 8)
CMOS DUAL-PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (R/W CONTROLLED TIMING)(1,3,5,8)
twc
ADDRESS
)K
~(
rOHZ(9)~
OE
CS
RIW
tAW
~,
~V
f4--- tAS (6)
tWR(7)
tWp(2)
"~
~toW(9)
~tWHZ(9)
oATAoUT
DATAIN
04-
/V
(4)
__
,
/j
--~k=
.. I.
tow
tOH
"
(4)
)-
DATA VALID
NOTES:
2839 drw 08
1. RIW is High for Read Cycles
2. Device is continuously enabled. CS = Low. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE= Low.
5. To access RAM, CS = Low, SEM = H. To access semaphore, CS = Hand SEM = Low.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is Low during a RIW controlled write cycle, the write pulse width must be larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tOW. If OE is High during a R!W controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,3,5,B)
twc
ADDRESS
~(
CS
"
)(
..
tAW
jl'
-tAS(6)_'
tWR(7)
tWp(2)
RIW
I-DATAIN
------------------lCI;~
tow
..
I..
DATA VALID
fI
--toH
--1
==>1111--------
NOTES:
2839 drw 09
1. RIW must be high during all address transitions.
2. A write occurs during the overlap (twp) of a Low CS and a Low RIW for memory array writing cycle.
3. twR is measured from the earlier of CS or RIW (or SEM or RIW) going high to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
7.11
7
IDT7MP1021/1023 (128K164K x 8)
CMOS DUAL-PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OFSEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
tOH
~----- ~ ----~~
VALID ADDRESS
Ao-A2
VALID ADDRESS
---I~·tWR
DATAo
RiW
2839 drw 10
NOTE:
1. CS = High for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(l,3,4)
MATCH
AOA-A2A
SIDe
2
)
"A"
X . . .________
RlWA
AOB-A2B
RlWB
SEMB
2839 drw 11
NOTES:
1. DOR = DOL = Low, L_CS'; R_CS = High: Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "An may be either left or right port. "B" is the opposite port from "An.
3. This parameter is measured from pjifjA or SEMA going High to RtWs or SEMs going High.
4. If tsps is violated, the semaphore will fall positively to one side orthe other, but there is no guarantee which side will obtain the flag.
7.11
8
IDTIMP1021/1023 (128K164K x 8)
CMOS DUAL·PORT STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1)
twc
)(
ADDRR
)(
MATCH
twp
RIWR
~K.
/'
tDH
tow
)~
DATAIN R
)k
VALID
MATCH
ADDRL
tWDD
)@
DATAOUTL
tODD
NOTE:
1. L_CS = R_CS = Low
WRITE CYCLE LEFT PORT
READC YCLE
RIGHT PORT
2839 drw 12
TRUTH TABLES
TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
Outputs
CS
RIW
OE
SEM
1/00-1/07
Mode
H
X
X
H
Hi-Z
Deselected: Power Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAoUT
Read from Memory
X
X
H
X
Hi-Z
Outputs Disabled
NOTE:
1. AOL-AI2;t:AoR-AI2R
",,., , II
TABLE II: SEMAPHORE READIWRITE CONTROL(1)
Outputs
Inputs
CS
RIW
H
H
OE
L'
SEM
1/00-1/07
Mode
L
DATAoUT
Read Data in Semaphore Flag
DATAIN
Write DINO into Semaphore Flag
X
S
X
L
L
X
X
L
-
Not Allowed
NOTE:
2839 tbl 11
1. AOL-AI2 ;t:AOR-AI2R
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
PACKAGE DIMENSIONS -
PLEASE CONSULT FACTORY
7.11
9
32K x 18
16K x 18
CEMOSTM PARALLEL
IN-OUT FIFO MODULE
t;)
Integrated Device Technology, Inc.
IDT7MP2009
IDT7MP2010
IOT7MP2009/7MP2010 are FIFO memory modules constructed on multi-layered epoxy laminate (FR-4) substrate by
mounting eight IOT7205 (8K x 9) or IOT7204 (4K x 9) FIFOs
in plastic leaded chip carriers. Extremely high speeds are
achieved in this fashion due to the use of IOT7205s and
IOT7204s fabricated in lOT's high performance CEMOS technology. These devices utilize a algorithm that loads and
empties data on a first-In/first-out basis. The device uses Full
and Empty flags to prevent data overflow and underflow and
expansion logic to allow for unlimited expansion capability in
both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Oata is toggled in and out of the device
through the use of the WRITE (W) and REAO (R) pins. The
devices have a read/write cycle time of 25ns (min.) for
commercial temperature ranges.
The devices utilize a 18-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
First-In/First-Out memory module
32K x 18 organization (IOT7MP2009)
16K x 18 organization (IOT7MP2010)
High speed: 15ns (max.) access time
Separate upper and lower 9-bit XI and XO
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
MASTER/SLAVE multiprocessing applications
Bidirectional and rate buffer applications
Empty and Full warning-flags
High-performance CEMOSTM technology
Single 5V (±1 0%) power supply
DESCRIPTION:
XIL--------,
RS --~H BS
R
R
-w
-w
00-17
Fe
tt-
XOL
XIH
B.
W
FFI-I--
I
XI
2x
EF
10T7204/5
_~~~==~X~o__F_F
t- ='WR
II-
~r-H
p-EF
b
J
Qo-a l -
00-17
~ RS
0(0)
0(1)
0(2)
0(3)
0(4)
0(5)
0(6)
0(7)
0(8)
Qo-a r . . - - f - - - Qo-a
X5
~ _RS
I-
XIL
EFI------,
1017204/5
00-17
Fe
GNO
~
XI
EFI--
I017~4/5 Qo-al-
00-17
_
X5
FL
W
Vcc
FF
FF
XIH
0(9)
0(10)
0(11)
0(12)
0(13)
0(14)
0(15)
0(16)
0(17)
FFI-
I
'- RS
XI
EFH-
'--- B.. 10T7~4/5Qo-a .....- - f - - - Q9-17
'---- W
' - - 00-17
FFt------'
XOH-------~l
2799 drw 01
Vcc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
33
35
37
39
41
43
45
47
49
51
ZIP
Vcc
XOL
Q(O)
Q(1)
Q(2)
Q(3)
Q(4)
Q(5)
Q(6)
Q(7)
Q(8)
RS
GNO
R
EF
XOH
Q(9)
Q(10)
Q(11)
Q(12)
Q(13)
Q(14)
Q(15)
Q(16)
Q(17)
GNO
2799 drw 02
TOP VIEW
CEMOS is a trademark of Integrated Device Technology. Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC·705312
©1992 Integrated Device Technology, Inc.
7.12
IDT7MP2009/2010 (32K 116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
PIN NAMES
RECOMMENDED DC
OPERATING CONDITIONS
W
R
RS
Write
Read
Reset
Vce
FL
00-17
First Load
DATAIN
GND
Supply Voltage
0
V
00-17
DATAoUT
VIH(1)
2.0
-
-
V
XIH. XIL
Expansion In (HiQh Bit. Low Bit)
Input High Voltage
Commercial
XOH XOL
Expansion Out (HiQh Bit Low Bit)
Full FlaQ
VIL(1)
Input Low Voltage
Commercial
-
-
O.B
V
FF
EF
Empty FlaQ
Symbol
Vcc
Power
GND
Ground
Parameter
Commercial
Supply Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
NOTE:
2799 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
2799 tbl 04
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = OV
VOUT", OV
ABSOLUTE MAXIMUM RATINGS(1)
Max.
80
120
NOTE:
Symbol
Unit
pF
pF
VTERM
2799 tbl 02
1. This parameter is guaranteed by design but not tested.
Rating
Terminal Voltage with Respect
to GND
Com'l.
Unit
-0.5 to +7.0
V
TA
Operating Temperature
Oto +70
°C
TBIAS
Temperature Under Bias
-10 to +B5
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
rnA
NOTE:
2799 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speCification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Vcc= 5 OV +1
- 0% TA=0°Cto+70°C)
Symbol
ID17MP2010
Min. Max.
Parameter
ID17MP2009
Min. Max.
Unit
-
20
-
20
j.IA
BO
BO
j.IA
2.4
-
2.4
-
V
0.4
0.4
V
12BO
-
1200
rnA
Average Standby Current (R = W = RS = FURT = VIH)
-
115
rnA
Power Down Current (All Input = Vee - 0.2V)
-
65
Ilul(1)
Input Leakage Current (Any Input)
lIoLl(2)
Output Leakage Current
VOH
Output Logic "1"
VOL
Output Logic "0" Vo~age lOUT = BmA
lec1(3)
Operating Current
lec2(3)
lee3(3)
Vo~age
lOUT = -2mA
NOTES:
125
-
65
rnA
2799 tbl 05
1. Measurements with 0.4 s VIN s VOUT.
2. R:::: VIH. 0.4 S VOUT S Vce.
3. Icc measurements are made with outputs open.
7.12
2
II
IDTIMP2009/2010 (32K116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1 & 2
. Output Reference Levels
Output Load
2799 tbl 06
+5V
+5V
~
480n
DATAoUT-...--...
DATAOUTn
30pF*
255n
4800
25511
2799 drw 03
y
.
5pF
2799 drw 04
* Includes scope and jig capacitances.
Figure 1. Output Load
Figure 2. Output Load
(for tRLZ, twLZ, and tRHZ)
* Includes scope and Jig capacitances.
AC ELECTRICAL CHARACTERISTICS
, (Vee = S.OV ± 10%, TA
=
O°C to + 70°C)
7MP2009SxxZ. 7MP20 OSxxZ
_20(3)
-25
-30
_15(3)
Min. Max. Min. Max.
Parameter
tRG
Read Cycle Time
25
-
30
-
35
-
40
-
45
-
ns
tA
Access Time
-
15
-
20
-
25
-
30
-
35
ns
tRR
tRPW(1)
Read Recovery Time
10
10
5
tWLZ(2)
Write Pulse High to Data Bus at Low Z
5
10
-
ns
Read Pulse Low to Data Bus at Low Z
tDV
Data Valid from Read Pulse High
5
-
-
10
tRLZ(2l
-
10
15
-
10
Read Pulse Width
-
5
-
ns
tRHZ(2)
Read Pulse High to Data Bus at High Z
-
15
-
13
-
20
-
20
-
20
ns
twc
Write Cycle Time
25
-
30
35
-
40
15
20
25
-
30
tWR
Write Recovery Time
10
-
10
10
tDS
Data Set-up Time
11
-
15
tDH
Data Hold Time
0
0
tRSC
Reset Cycle Time
25
-
tRs(1)
Reset Pulse Width
15
25
-
30
tRSR
Reset Recovery Time
10
10
-
10
-
10
-
ns
Write Pulse Width
-
45
twPW(1)
-
tEFL
Reset to Empty Flag Low
30
-
35
-
40
45
ns
tREF
Read Low to Empty Flag Low
20
-
25
-
30
35
ns
tRFF
25
30
35
ns
25
-
35
ns
25
-
30
-
20
5
5
5
10
30
-
20
25
Read High to Full Flag High
-
tWEF
Write High to Empty Flag High
-
20
tWFF
Write Low to Full Flag Low
-
17
-
17
20
NOTES:
10
23
23
20
Min.
25
5
5
5
18
0
35
Max.
Min.
-35
Symbol
30
5
10
5
18
0
40
Max.
30
Min.
35
5
35
10
20
0
45
35
Max.
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2799tbl07
1. Pulse widths less than minimum value are not allowed.
2. This parameter is guaranteed by design but not tested.
3. Preliminary specifications only.
7.12
3
IDT7MP2009/2010 (32K 116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5.0V
± 10%, TA =
O°C to +70°C)
7MP2009SxxZ,7MP2010SxxZ
-50
-60
-40
Symbol
Parameter
tRC
-70
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
50
-
65
-
75
tA
Access Time
-
40
-
50
-
60
70
ns
tRR
tRPW(1)
Read Recovery Time
Read Pulse Low to Data Bus at Low Z
tWLZ(2)
Write Pulse High to Data Bus at Low Z
-
tDV
tR HZ(2)
Data Valid from Read Pulse High
15
50
10
15
5
-
tRLZ(2)
10
40
5
10
5
-
15
60
10
15
5
-
85
15
70
10
15
5
Read Pulse High to Data Bus at High Z
-
-
30
-
30
-
Write Cycle Time
50
40
10
20
0
50
40
10
-
75
60
15
30
5
75
60
15
-
65
50
50
50
50
-
85
70
15
30
10
85
70
15
-
Read Pulse Width
twc
twPW(1)
Write Pulse Width
tWR
Write Recovery Time
tDS
Data Set-up Time
tDH
Data Hold Time
tRSC
tRS(1)
Reset Cycle Time
tRSR
Reset Recovery Time
Reset Pulse Width
tEFL
Reset to Empty Flag Low
tREF
Read Low to Empty Flag Low
tRFF
Read High to Full Flag High
tWEF
Write High to Empty Flag High
tWFF
Write Low to Full Flag Low
-
25
-
65
50
15
30
5
65
50
15
-
-
50
40
40
40
40
-
-
-
-
NOTES:
'-
-
75
60
60
60
60
-
ns
-
ns
-
ns
-
ns
30
-
ns
-
ns
-
ns
-
ns
85
70
70
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2799 tbl 08
1. Pulse widths less than minimum value are not allowed.
2. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF RESET CYCLE{1,2)
II
..
tRS
tRSR
tEFL
2799 drw 05
NOTES:
1. tRsc = tRs + tRSR
2. Vi and R = VIH during RESET.
7.12
4
IDT7MP2009/2010 (32K116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF ASYNCHRONOUS WRITE AND READ OPERATION
tRPW
DATAoUT VALID
00-8
twPW------lI~--
tDS
tDH
DATAoUT VALID
00-8
DATAoUT VALID
2799 drw 06
TIMING WAVEFORM FOR THE FULL FLAG FROM LAST WRITE TO FIRST READ
LAST WRITE
FIRST READ
ADDITIONAL
READS
FIRSTWRITE
2799 drw 07
TIMING WAVEFORM FOR THE EMPTY FLAG FROM LAST READ TO FIRST WRITE(1)
LAST WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
DATAoUT
2799 drw 08
NOTE:
1. This parameter is guaranteed by design but not tested.
7.12
5
IDTIMP200912010 (32K 116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OFTHE EMPTY FLAG CYCLE(1)
2799 drw 09
NOTE:
1. (tRPE
= tRPW)
TIMING WAVEFORM OF THE FULL FLAG CYCLE
w
2799 drw 10
NOTE:
1. (twPF = twpw)
fI
I
7.12
6
IDT7MP2009/2010 (32K116K x 18)
CMOS PARALLEL IN-OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ DATA FLOW-THROUGH MODE
DATAIN
tRPE --~
DATAoUT
DATAoUT VALID
2799 drw 11
tWLZ
TIMING WAVEFORM OF WRITE DATA FLOW-THROUGH MODE
tWPF-
tDH
DATAIN
DATAoUT----i---<
DATAoUT VALID
2799 drw 12
DEPTH/WIDTH EXPANSION & DATA FLOWTHROUGH MODES:
For more details on expanding FIFO modules in depth and/
or width, please refer to the IDT7204 or IDT7205 data sheets.
For more details on data flow-through modes (read data fallthrough and write data fall-through), please refer to the IDT7204
or IDT7205 data sheets.
7.12
7
IDT7MP2009/2010 (32K/16K x 18)
CMOS PARALLEL IN·OUT FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
g:~:gI
,.....,..~II+- -+II+-
Pin 1
0.100
. Typ.
0.050
Typ.
·
.
1-. Y
0.345
Max.
0.100
Typ.
0.015
0.025
0.125
0.190
FRONT VIEW
2799 drw 13
BACK VIEW
7.12
8
32KJ64K x 9
CMOS PARALLEL IN-OUT
FIFO MODULE
G
IDT7M207
IDT7M208
Integrated Device Technology, Inc.
rithm that loads and empties data on a first-in/first-out basis.
The device uses Full and Empty flags as warnings for data
overflow and underflow conditions and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the device
through the use of the WRITE (W) and READ (R) pins. The
devices have a read/write cycle time of 20ns (min.) for
commercial and 30ns (min.) for military temperature ranges.
The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking.
IDT's Military FIFO modules have semiconductor
components manufactued in compliance with the latest revision
of MIL-STD-883, Class 8, making them ideally suited to
applications demanding the highest level of performance and
reliability.
FEATURES:
•
•
•
•
•
•
•
•
•
•
First-In/First-Out memory module
64K x 9 (IDT7M208) or 32K x 9 (IDT7M207)
High speed: 20ns (max.) access time
Asynchronous and simultaneous read and write
Fully expandable: depth and/or width
MASTERISLA VE multiprocessing applications
Bidirectional and rate buffer applications
Empty and Full warning-flags
High-performance CEMOSTM technology
Single 5V (±10%) power supply
DESCRIPTION:
IDT7M207 and IDT7M208 are FIFO memory modules
constructed on a multi-layered ceramic substrate using four
IDT7205 (8K x 9) or IDT7206 (16K x 9) FIFOs in leadless chip
carriers. Extremely high speeds are achieved in this fashion
due to the use of IDT7205/6s fabricated in IDT's high performance CEMOS technology. These devices utilize an algo-
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Do-D8
00-Q8
W
XO
1
R
RS
1
Xi-
L
1
1
I T
11
11
XOI-
1OT7205/6
1OT7205/6
Xi
FF
EF
-I-<
FL
FF EF
D4
D5
D6
D7
Xi
RS
FL
xo
FF
EF
IDT7205/6
IDT7205/6
00
01
02
03
08
GND
XO
FL
FF -~
Xi
IT
IT
Vee
xo
'-Xi
IT
Vcc
xoU
I
Iii
D8
D3
D2
D1
Do
~~
EF
'-Xi
FF
~l
EF
J
-
07
06
05
04
R
""---
DUAL 4-INPUT OR GATE
2718 drw 01
DIP
TOP VIEW
2718 drw 02
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
OSC·7098/·
©1992 Integrated Device Technology. Inc.
7.13
IDTIM207 (32K x 9), IDTIM208 (64K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
CAPACITANCE (TA = +25°e, f = 1.0 MHz)
W=
WRITE
FL =
FIRST LOAD
XI =
EXPANSION IN
EF=
EMPTY FLAG
R=
READ
D=
DATAIN
XO=
EXPANSION OUT
Vee =
5V
RS=
RESET
Q=
DATAoUT
FF=
FULL FLAG
GND=
GROUND
Symbol
CIN
COUT
Parameter(l)
Input Capacitance
Output Capacitance
Condition
VIN = OV
VOUT = OV
Max.
50
50
NOTE:
1. This parameter is guaranteed by design but not tested.
Unit
pF
pF
2718 tbl 03
27181bl01
RECOMMENDED DC
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Rating
Symbol
Terminal Voltage
VTERM
with Respect
toGND
Operating
TA
Temperature
Temperature
TSIAS
Under Bias
TSTG
Storage
Temperature
DC Output
lOUT
Current
Symbol
Com'l.
Mil.
Unit
-0.5 to +7.0 -0.5 to +7.0 V
o to +70
-55 to +125
°C
-55 to +125 -65 to +135
°C
-55 to +125 -65 to +150
°C
50
50
Parameter
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
VIH\l)
Supply Voltage
0
0
V
Input High Voltage
Commercial
2.0
-
-
V
VIH(l)
Input High Voltage
Military
2.2
-
-
V
VIL(2)
Input Low Voltage
Commercial and
Military
-
-
O.B
V
rnA
NOTE:
2718 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
0
NOTES:
1. VIH = 2.6V forXi' input (commercial)
VIH = 2.SV forXi' input (military)
2. 1.5V undershoots are allowed for 10ns once per cycle.
2718 tbl 04
DC ELECTRICAL CHARACTERISTICS
( Vee = 5.0V±1 0%, TA = ooe to +70°C; and -55°C to +125°C)
Commercial
Max.
Min.
Military
Min.
Max.
Svrnbol
IU(l)
Parameter
Input Leakage Current (Any Input)
-5
5
-40
40
IOL(2)
Output Leakage Current
-40
40
-40
40
Unit
IlA
IlA
VOH
Output Logic "1" Vo~age lOUT = -2mA
2.4
-
2.4
-
VOL
ICC1(3)
Output Logic "0" Vo~age lOUT = BmA
-
0.4
-
0.4
V
Average Vce Power Supply Current
560
rnA
Average Standby Current (R = W = AS = FURT = VIH)
ICC3(3)
Power Down Current (All Input = VCC - 0.2V)
-
32
-
720
ICC2(3)
-
NOTES:
1. Measurements with 0.4 ~ VIN ~ Vee.
2. R <: VIH, 0.4 ~ VOUT ~ Vee.
3. lee measurements are made with outputs open.
60
V
BO
mA
48
rnA
2718 tbl 05
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figure 1 & 2
2718tbl06
7.13
2
IDT7M207 (32K x 9), IDT7M208 (64K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+5V
+5V
DATAoUT - - . - - - - - - - .
DATAoUT -
___. - - - - -.......
30pF*
255n
30pF*
255n
2718 drw 03
2718 drw 04
Figure 2. Output Load
(for tRLZ, tWLZ, and tRHZ)
Figure 1. Output Load
• Includes scope and Jig capacitances.
* Includes scope and jig capacitances.
AC ELECTRICAL CHARACTERISTICS
(Vec = 5.0V±10%, TA = O°C to +70°C and -55°C to +125°C)
Symbol
Parameter
_20(3}
_25(3}
(Com'l Only)
(Com'l Only)
Min.
Max.
Min.
_30(3}
Max.
Min.
-35
Max.
Min.
Max.
Unit
-
25
-
22.5
MHz
-
40
-
45
-
ns
-
25
-
30
-
35
ns
10
10
-
10
30
-
35
-
5
-
5
5
5
10
5
-
5
5
-
-
-
ns
25
-
5
-
ns
Read Pulse High to Data Bus at High Z
-
16
-
20
-
20
-
20
ns
twc
Write Cycle Time
30
35
25
30
35
tWR
Write Recovery Time
10
-
10
-
10
-
10
tos
Data Set-up Time
15
-
18
-
18
-
20
tOH
Data Hold Time
0
-
0
-
0
0
-
35
-
40
45
25
-
30
-
-
ns
20
-
45
Write Pulse Width
-
40
twPW(I)
-
35
-
ns
10
-
10
-
10
-
ns
30
-
35
-
40
45
ns
35
ns
23
-
25
35
ns
23
-
25
23
-
25
-
33.3
-
30
-
35
Access Time
-
20
tRR
Read Recovery Time
10
tRPW(I)
Read Pulse Width
20
-
tRLZ(2)
Read Pulse Low to Data Bus at Low Z
5
tWLZ(2)
Write Pulse High to Data Bus at Low Z
5
tov
Data Valid from Read Pulse High
tRHZ(2)
fs
Shift Frequency
-
tRC
Read Cycle Time
tA
tRSC
Reset Cycle Time
30
tRS(I)
Reset Pulse Width
20
tRSR
Reset Recovery Time
10
tEFL
Reset to Emtpy Flag Low
tREF
Read Low to Emtpy Flag Low
-
tRFF
Read High to Full Flag High
tWEF
Write High to Empty Flag High
tWFF
Write Low to Full Flag Low
NOTES:
1. Pulse widths less than minimum value are not allowed.
2. Values guaranteed by design, not currently tested.
3. Preliminary specifications only.
23
28.6
25
5
-
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
35
ns
27181bl07
7.13
3
IDT7M207 (32K x 9), IDT7M208 (64K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V±1 0%, TA = ooe to + 70 0 e and -55°e to + 125°C)
-40
Symbol
Parameter
fs
Shift Frequency
-
tRC
Read Cycle Time
tA
Access Time
tRR
-50
-60
-70
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
20
-
15.4
-
13.3
-
11.6
MHz
50
40
65
-
50
75
-
60
85
-
70
ns
-
Read Recovery Time
10
-
15
15
15
-
ns
60
70
-
ns
10
-
ns
ns
tRPW(1)
Read Pulse Width
40
-
50
-
tRLZ(2)
Read Pulse Low to Data Bus at Low Z
5
10
-
10
tWLZ(2)
Write Pulse High to Data Bus at Low Z
10
-
-
15
-
15
-
15
-
ns
tDV
Data Valid from Read Pulse High
5
-
5
-
5
-
5
-
ns
tRHZ(2)
Read Pulse High to Data Bus at High Z
-
25
-
30
-
30
-
30
ns
twc
Write Cycle Time
50
65
-
75
-
85
-
ns
twpw(1)
Write Pulse Width
40
-
50
-
60
70
-
ns
tWR
Write Recovery Time
10
-
15
-
15
-
15
-
ns
30
-
30
-
ns
5
-
10
-
ns
85
-
ns
70
-
ns
tDS
Data Set-up Time
20
-
30
tDH
Data Hold Time
0
5
-
tRSC
Reset Cycle Time
50
65
-
75
tRS(1)
Reset Pulse Width
40
50
-
60
tRSR
Reset Recovery Time
110
-
15
-
15
-
15
-
ns
tEFL
Reset to Emtpy Flag Low
-
55
-
65
-
75
-
85
ns
tREF
Read Low to Emtpy Flag Low
-
40
-
50
-
60
-
70
ns
tRFF
Read High to Full Flag High
-
50
-
70
ns
Write High to Empty Flag High
40
60
ns
-
40
-
70
Write Low to Full Flag Low
-
50
tWFF
-
60
tWEF
-
40
50
NOTES:
60
70
ns
2718tbl08
1. Pulse widths less than minimum value are not allowed
2. Values guaranteed by design, not currently tested.
TIMING WAVEFORM OF RESET CYCLE(1,2)
tRS
RS
~~
7i(..
w
~~
~
IEFL
~
....
EF
tRSR
f4-
2718 drw 05
NOTES:
1. tRsc = tRS + tRSR
2. Wand R = VIH during RESET.
7.13
4
IDnM207 (32K x 9), IDnM208 (64K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF ASYNCHRONOUS WRITE AND READ OPERATION
Oo-Qa
_ FI-oII-----
twpw
-----ro--
___----J/
W~_
Do-Da
--------( . . ._____----' J------t:(
DATAIN
VALID
)>-----2718 drw 06
TIMING WAVEFORM FOR THE FULL FLAG FROM LAST WRITE TO FIRST READ
LAST WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
tRFF
2718 drw 07
TIMING WAVEFORM FOR THE EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
DATAoUT
2718 drw 08
NOTE:
1. This parameter is guaranteed by design but not tested.
7.13
5
IDT7M207 (32K x 9), IDT7M208 (64K X 9)
CMOS PARALLEL IN·OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM FOR THE EMPTY FLAG CYCLE
w
2718 drw 09
NOTE:
1. tRPE must be
~
tRPW (min). Refer to Technical Note TN-OS for details on this boundary condition.
TIMING WAVEFORM FOR THE FULL FLAG CYCLE
Vi
2718 drw 10
NOTE:
1. twPF must be
~
twpw (min). Refer to Technical Note TN-OS for details on this boundary condition.
7.13
6
IDT7M207 (32K x 9), IDT7M208 (64K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ DATA FLOW-THROUGH MODE
DATA IN
3V
OV
OV
tWL
DATAoUT---------r-------------------------+_+<
VALID
2718 drw 11
TIMING WAVEFORM OF WRITE DATA FLOW-THROUGH MODE
3V
R
tWPF
W
OV
FF
ov
tRFF
tOH
DATAIN
DATAoUT
-------------@ Vee - 0.2V or < 0.2V
80
rnA
2769 tbl 08
7.14
2
IDT7MP4104
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figures 1·4
2769 tbl 09
+5V
+5V
480n
480n
DATAoUT
DATAoUT-----------,r-------~
2550
2 5 5 0 Y 3 0 PF'
2769 drw 03
~
_
~
5pF*
2769 drw 04
'Includes scope and jig.
Figure 2. Output Load
Figure 1. Output Load
(for tOLZ,tOHZ, tcHZ, tcLZ, twHZ, tow)
DATAoUT
l'i---Z-O-=-5-o-n--~""'11500
t.TAA
(Typical, ns)
5
4
1.5V
2769 drw 05
Figure 3. Alternate Output Load
20
40
60
60
100 120 140 160 160
200
CAPACITANCE (pF)
2769drw 06
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
7.14
3
IDT7MP4104
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +1
- 0%, TA = O°C to +70°C)
7MP4104SxxZ,7MP4104SxxM
-20
Symbol
Parameter
Min.
. -25
Max.
-35
Min.
Max.
Min.
Max.
Unit
25
25
35
ns
-
3
0
-
35
35
18
Read Cycle
tRC
Read Cycle Time
20
-
tAA
Address Access Time
tACS
tCLZ(1)
Chip Select Access Time
-
20
20
Chip Select to Output in Low Z
3
-
25
3
tOE
tOLZ(1)
Output Enable to Output Valid
-
12
-
15 .
Output Enable to Output in Low Z
-
0
-
tCHZ(1)
Chip Deselect to Output in High Z
0
-
tOHZ(1)
Output Disable to Output in High Z
-
10
10
-
12
12
tOH
tpu(1)
Output Hold from Address Change
Chip Select to Power-Up Time
3
0
-
3
0
-
tpo(1)
Chip Deselect to Power-Down Time
-
20
-
25
-
-
25
20
20
0
20
3
-
-
-
ns
ns
ns
ns
-
ns
18
18
-
ns
ns
3
0
-
-
ns
35
ns
-
ns
-
35
30
30
0
30
3
-
15
-
20
ns
15
0
0
-
20
0
0
-
ns
ns
Write Cycle
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
tWHZ(1)
Write Recovery Time
20
15
15
0
15
·3
Write Enable to Output in High Z
-
tow
Data to Write Time Overlap
tOH
Data Hold from Write Time
tow(1)
Output Active from End of Write
12
0
0
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
NOTE:
10
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
2769 tbltO
1. This parameter is guaranteed by design, but not tested.
7.14
4
IDT7MP4104
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
DATA OUT
2769 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
~: ~_-~ _-~ _-~ _-~ _-~ t~O~H~ -_~ -_~ -_t~A_A~ -_-_-tR~C:______________.__--~~-t-O-H---------1
PREVIOUS DATA VALID
DATA VALID
2769 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
~~~~~~~~~~.I~~~~.~
DATAoUT
II<--------------------------------~
2769 drw 09
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.14
5
IDTIMP4104
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED) (1,2,3,7)
twe
ADDRESS
~
~
K
)K
/
V
tAW
-
""-
f.-
/
/
twp
tAS
(7)
tWR_
"",
/
~ tWHZ(6)_
tOHZ(6)
tOHZ (6)
DATA OUT
(4)
/
~
tOW(6)1
"-
(4)
r
/
_tow
/
DATA IN
""
) r-
tOH
DATA VALID
"/
2769 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED) (1,2,3,5)
twe
ADDRESS
)
K
) (
tAW
f4- tAS
'}
/'
tew
tWR
tow
DATAIN
~
-------------------cE
-.1.-
tOH
DATA VALID
II
3)1---2769 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
PACKAGE DIMENSIONS - PLEASE CONSULT FACTORY FOR DETAILS
7.14
6
~
256K x 32
BiCMOS/CMOS STATIC RAM
MODULE
PRELIMINARY
IDT7M4077
Integrated Device Technolo&Y,lnc. '
FEATURES:
DESCRIPTION:
• High density 8 megabit static RAM module
The IDT7M4077 is a 256K x 32 static RAM module constructed on a multilayer ceramic substrate using eight 256Kx4
static RAMs in leadless chip carrier (LCC) packages. Availability of four write enable lines (one for each group of two
RAMs) provides byte write capability. The IDT7M4077 is
available with access time as fast as 15ns with minimal power
consumption.
The IDT7M4077 is packaged in a 64 pin sidebraze DIP
(Dual In-line Package). The DIP configuration allows 64 pins
to be placed on a package 3.5 inches long, 0.6 inches wide
and 0.31 inches thick.
All inputs and outputs of the IDT7M4077 are TIL compatible and operate from a single 5V supply. Full asynchronous
circuitrY requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
AIIIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class S, making them ideally suited
to applications demanding the highest level of performance
and reliability.
• Low profile 64 pin sidebraze DIP (Dual In-line Package)
• Very fast access time: 15ns (max.)
• Surface mounted leadless chip carrier (LCC) components
on an multilayer ceramic substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
• Multiple GND pins and decoupling capacitors for maximum noise immunity
PIN CONFIGURATION
Vee
GND
1100
1/08
1/09
1/01
1/02
1/03
1/010
1/011
~o
GND
~1
1/04
1/05
1/06
1/012
1/013
1/014
1/015
1107
A9
Ao
:FUNCTIONAL BLOCK DIAGRAM
A10
A11
A1
A2
A3
OE
GND
A4
A5
A6
A7
A12
A13
GND
CS
A14
A15
A16
A17
A8
1/016
1/017
1/018
1/019
1/00-7 1/08-15 1/016-23 1/024-31
2814drw02
1/024
1/025
1/026
1/027
GND
WE3
WE2
1/020
1/021
1/022
1/023
PIN NAMES
1/028
1/029
1/030
1/031
Vee
GND
2814 drwOl
DIP
TOP VIEW
1/00-31
Data Inputs/Outputs,
Ao-17
Addresses
CS
Chip Select
WEo-3
Write Enables
OE '.
Output Enable
Vce
Power
GND
Ground
2814 tblOl
BiCEMOS and CEMOS are trademarks of Integrated Device Technology, Inc,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
eSC-707711
©1992 Integrated Device Technology, Inc,
7.15
IDT7M4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Terminal Voltage
with Respect
TRUTH TABLE
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
o to +70
-55 to +125
°C
T81AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
Temperature
-55 to +125
TSTG
lOUT
Output
Power
X
High Z
Standby
Read
L
L
H
DATAoUT
Active
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
(TA =
+25°C, F = 1.0MHz)
2814 tbl 04
-65 to +150
50
°C
50
Parameter(l)
Symbol
Conditions
Max.
Unit
CliO
I/O Capacitance
(Data)
V(IN) =OV
15
pF
CINl
Input Capacitance
(Address & Control)
V(IN) =OV
90
pF
Input Capacitance
V(IN) ",OV
35
pF
rnA
NOTE:
2814 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
Unit
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
O.S
V
NOTE:
1. VIL(min)
WE
X
CAPACITANCE
DC Output
Current
Symbol
OE
H
Mode
toGND
TA
CS
Standby
CIN2
(WE)
NOTE:
1. This parameter is guaranteed by design but not tested.
2814 tbl 05
RECOMMENDEC OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
Vee
2814 tbl 06
2814 tbl 03
= -1.5V for pulse width less than 10ns.
DC ELECTRICAL CHARACTERISTICS
= 5 OV +10%
TA = -55°C to +125°C and O°C to +70°C)
-
(VCC
Symbol
Parameter
Test Conditions
Min
Max.
Unit
IILlI
Input Leakage
(Address and Control)
Vee = Max.; VIN
= GND to Vee
-
IILlI
Input Leakage (Data)
Vee", Max.; VIN
IILlI
Input Leakage (WE)
Vee", Max.; VIN
= GND to Vee
= GND to Vee
-
V
IILol
Output Leakage
Vee = Max.; CS = VIH, VOUT = GND to Vee
VOL
Output Low
Vee", Min., IOL", SmA
-
VOH
Output High
Vee", Min., IOH '" -4mA
2.4
so
flA
10
10
flA
flA
flA
0.4
V
20
II
2814 tbl 07
7M4077(1.2)
Symbol
Icc
Parameter
Test Conditions
7M4077(3)
Military
Max.
Comm.
Max.
Military
Max.
Comm.
Max.
1760
1600
1500
1200
rnA
rnA
Dynamic Operating
Current
f '" fMAX; CS'" VIL
Vee Max.; Output Open
IS8
Standby Supply
Current
CS;::: VIH. Vee Max.
Outputs Open. f = fMAX
720
600
600
4S0
IS81
Full Standby
Supply Current
CS;::: Vee - 0.2V; f '" 0
VIN > Vee - 0.2V or < 0.2V
400
320
320
SO
=
=
Unit
rnA
2814 tOI 08
NOTES:
1. Preliminary speCifications only.
2. 15-20ns versions only.
3. 25-55ns versions only.
7.15
2
IDT7M4077 256K x 32
BlCMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1-4
2814 tbl 09
+5V
+5V
480n
480n
DATAoUT
255n
DATAoUT
Lr30PF'
255nY5
PF'
2814 drw 04
2814 drw 03
"Includes scope and jig.
Figure 1. Output Load
(for toLZ, tCHZ, tCLZ, tWHZ, tow)
Figure 1. Output Load
ATAA
(Typical, ns) 5
4
DATAoUT
Zo = 50n
n- 1
50n
1.5V
20
2814 drw 05
40
60
80
100 120 140 160 180
CAPACITANCE (pF)
200
2814 drw 06
Figure 4. Alternate Lumped capacitive Load,
Typical Derating
Figure 3. Alternate Output Load
7.15
3
IDnM4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V +10%,
TA = -55°e to + 125°e and ooe to +70°C)
7M4077SxxC 7M4077SxxCB
-15(2)
Symbol
Parameter
Min.
-17(2)
Max.
Min.
-20(2)
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
-
17
-
20
-
ns
tAA
Address Access Time
-
-
Chip Select Access Time
-
-
ns
tOE
Output Enable to Output Valid
-
8
-
3
-
ns
Chip Select to Output in Low Z
3
20
20
tCLZ(1)
3
17
17
10
-
tACS
15
15
12
ns
tOLZ(1)
Output Enable to Output in Low Z
0
-
-
0
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
8
8
-
Output Disable to Output in High Z
8
-
8
tOH
Output Hold from Address Change
3
-
3
-
3
10
10
ns
tOHZ(1)
-
0
-
-
ns
-
-
-
ns
ns
-
17
15
15
0
15
0
ns
ns
Write Cycle
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
15
12
12
0
12
0
tWHZ(1)
Write Enable to Output in High Z
-
8
tDW
Data to Write Time Overlap
tDH
Data Hold from Write Time
toW(1)
Output Active from End of Write
10
0
0
-
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
-
-
-
-
20
17
17
0
17
0
-
10
-
13
10
0
0
-
15
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
2814tbll0
fI
7.15
4
IDT7M4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee = 5 OV +10%
TA = -55°C to + 125°C and O°C to +70°C)
-
Symbol Parameter
Read Cycle
-25
Min. Max.
7M4077SxxC 7M4077SxxCB
-30
-35
-45
Min. Max. Min. Max. Min. Max.
tRC
Read Cycle Time
25
-
30
-
35
-
tAA
Address Access Time
-
tACS
tCLZ(1)
Chip Select Access Time
-
25
25
-
30
30
-
35
35
Chip Select to Output in Low Z
3
-
3
-
tOE
tOLZ(1)
Output Enable to Output Valid
-
15
-
18
Output Enable to Output in Low Z
0
-
0
-
3
0
tCHZ(1)
Chip Deselect to Output in High Z
-
tOHZ(1)
Output Disable to Output in High Z
~
17
12
-
20
15
-
25
20
tOH
tPU(1)
Output Hold from Address Change
Chip Select to Power-Up Time
3
0
-
3
0
-
3
0
tPO(1)
Chip Deselect to Power-Down Time
-
25
-
30
-
30
25
25
0
25
0
-
-55
Min.
Max.
Unit
-
55
-
ns
-
55
55
ns
-
45
45
-
3
-
3
-
ns
23
-
25
-
25
ns
-
-
0
-
-
ns
ns
-
0
3
0
-
. 35
-
35
30
30
0
30
0
45
-
ns
30
25
-
30
25
-
3
0
-
ns
-
45
-
55
ns
-
45
40
40
0
40
0
-
55
50
50
0
40
0
-
ns
-
ns
ns
ns
Write Cycle
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
tWHZ(1)
Write Recovery Time
25
20
20
0
20
0
Write Enable to Output in High Z
-
18
-
20
-
23
-
25
-
25
tDW
Data to Write Time Overlap
-
20
0
0
-
25
0
0
-
30
0
0
-
30
0
0
ns
Data Hold from Write Time
20
0
0
-
tDH
toW(1)
-
ns
Output Active from End of Write
-
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
-
-
ns
ns
ns
ns
ns
ns
2814tblll
7.15
5
IDT7M4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1,3,4)
~---------------------
tRC
ADDRESS
~----------~-----------
DATAoUT
tACS -------------+------1~
tClZ (5) __________
~
----------------------------------------C
2814 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
~ ~ ~ =~=~=~=~=- =- =- =- ~t~O-H~- =- =- =- ~t-A ~ - ~ -t~R~C- - - - - - -~-I-~ -tO-H- - - - DATA VALID
PREVIOUS DATA VALID
2814 drw 08
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with cs transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.15
6
•
IDnM4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1,2,3,7)
ADDRESS
twc
,
~/
~
/
)
"
/'rt'
tAW
~
"
-.- tAS
tWR(~
(7)
~,
-
tOHZ
DATAoUT
~
/
twp
(4)
tWHZ
/
~
tOHZ
(6) __
(6)
tow (6)
(6)
"
(4)
/
"
tDH
tDW_
DATA)N
r
DATA VALID
"
)-
/
2814 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2(1,2,3,5)
twc
ADDRESS
-
)(
)
K
tAW
-"'~
~
~
(3)
tew
DATAIN
tWR
DATA VALID
to"
3)1----2814 drw 10
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7.15
7
IDT7M4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
r
I
~:;~:I~~lul:=JDI
3.485
3.555
•
0.590
O 610
(lt
.
TOP VIEW
o 310~
PIN 1
0.335 MAX
.-L
MAX - ' - -
*~nm'm'mnnmflnmm0
-lr- -~ ~ r- ~
0.007
0.013
SIDE VIEW
O.045MAX
0.035
0.060
0.015
0.022
.0100 TYP
.g.~~;
.
IL~]j~~~~~~~[~~~~~ ~~~I~~~:~~JI
BOTTEMVIEW
2814 drw 11
II
I
7.15
8
256K x 32
CMOS STATIC RAM MODULE
~
IDT7MB4067
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 8 'megabit static RAM module
The IDT7MB4067 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability
of four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MB4067 is available with
access time as fast as 20ns with minimal power consumption.
The IDT7MB4067 is packaged in a 60 pin DIP (Dual In-line
Package). The DIP configuration allows 60 pins to be placed
on a package 3.0 inches long and 0.6 inches wide and 0.365
inches tall.
All inputs and outputs of the IDT7MB4067 are TTL compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
• Low profile 60 pin DIP (Dual In-line Package)
• Very fast access time: 20ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
• Multiple GND pins and decouplingcapacitors for
maximum noise immunity
PIN CONFIGURATION
GND
Vee
Ao
1/031
1/030
1/029
1/028
1/00
1/01
1/02
1/03
FUNCTIONAL BLOCK DIAGRAM
Au
A16
CS3
CSo
A1
1/027
1/04
1/05
1/06
1/07
11026
1/025
1/024
A2
A3
WEo
A4
A5
A15
A14
WE1
A13
A12
1/08
1/09
1/010
1/011
1/023
1/022
1/021
1/020
A6
A7
CS1
Aw
Ao-u
x 32
8
1100-7
1/08-15 1/016-23 1/024-31
2830 drw 02
PIN NAMES
Addresses
CS2
Ao-Au
1/019
1/00-31
Data InputslOutputs
CSa
Chip Select for 1/00-7
CS1
Chip Select for 1/08-15
CS2
Chip Select for 1/016-23
CSs
Chip Select for 1/024-31
WEo
Write Enable for 1/00-15
11018
I/0u
1/016
A9
Vee
A8
GND
256K
RAM
An
1/012
1/013
1/014
1/015
18
DIP
TOP VIEW
2830 drwOl
WE1
Write Enable for 1/016-31
GND
Ground
Vcc
Power
2830 tbl 01
APRIL 1992
COMMER~ALTEMPERATURERANGE
OSC-708312
e1992 Integrated Device Technology, Inc.
7.16
ID17MB4067
256K x 32 CMOS STATIC RAM MODULE
CAPACITANCE (TA =
+25°e,
Parameter(1)
Symbol
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
F = 1.0MHz)
Conditions
Max.
Unit
Mode
CS
WE
Output
CliO
Data 1/0 Capacitance
V(IN) = OV
15
pF
Standby
H
Hi·Z
Standby
CIN(W)
Input Capacitance
(WE)
V(IN)
= OV
X
40
pF
Read
L
H
Dout
Active
CIN(C)
Input Capacitance
(CS)
V(IN)
= OV
20
pF
Write
L
L
Din
Active
CIN(A)
Input Capacitance
(Address)
V(IN) = OV
75
pF
2830 tbl 05
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Value
Unit
-0.5 to +7.0
V
2830 tbl 02
NOTE:
VTERM
1. This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
0.8
V
-
NOTE:
1. VIL (min)
Power
TA
Operating Temperature
o to +70
°C
TBIAS
Temperature Under Bias
-10 to +85
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
rnA
NOTE:
2830 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
2830 tbl 03
=
Terminal Voltage with
Respect to GND
-2.0V for pulse width less than 10ns.
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V ± 10%
2830 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ±1 0%, TA =
ooe to +70°C)
7MB4067
Symbol
Test· Conditions
Parameter
Min.
Max.
Unit
80
JlA
-
10
-
10
JlA
JlA
0.4
V
2.4
-
Input Leakage
(Address and Control)
Vee = Max.; VIN = GND to Vee
-
Ilul
Input Leakage (Data)
Vee = Max.; VIN
= GND to Vee
IILol
Output Leakage
Vee = Max.; CS = VIH, VOUT = GND to Vee
VOL
Output Low
Vee
VOH
Output High
Vee
Ilul
= Min., IOL = 8mA
= Min., IOH =-4mA
V
2830tbl07
Symbol
Parameter
Test Conditions
Min.
7MB4067
Max.
Unit
lee
Dynamic Operating
Current
f =fMAX; CS =VIL
Vee = Max.; Output Open
-
1200
rnA
ISB
Standby Supply
Current
CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX
-
480
rnA
ISB1
Full Standby
Supply Current
CS ~ Vee - 0.2V; f = 0
VIN> Vee - 0.2V or < 0.2V
-
80
rnA
2830 tbl 08
7.16
2
IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figure 1 & 2
2830 tbl 09
+5 V
480n
480n
DATAoUT--------~------~
255n
DATAoUT--------,-------~
255n
30 pF*
2830 drw 03 "Includes
5 pF*
scope and jig
2830 drw 04
Figure 1. Output Load
Figure 1. Output Load
(for tCHZ, tClZ, tWHZ, tow)
AC ELECTRICAL CHARACTERISTICS (Vcc = 5V ±10%, TA = O°C to +70°C)
7MB4067SxxP
-20(2)
Symbol Parameter
Read Cycle
Min.
-30
-25
Max.
Min.
Max.
Min.
-35
Max.
Min.
-45
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
20
-
25
-
30
-
35
-
45
-
ns
tAA
Address Access Time
20
-
30
ns
25
-
30
35
-
45
20
-
35
Chip Select Access Time
-
25
tACS
-
45
ns
tCLZ(l)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHZ(l)
Chip Deselect to Output in High Z
-
10
-
12
-
15
18
-
tOH
Output Hold from Address Change
3
-
3
3
Chip Select to Power-Up Time
0
-
0
0
-
5
tpu(1)
-
tPO(l)
Chip Deselect to Power-Down Time
-
20
-
25
-
-
25
30
20
-
20
ns
5
-
ns
0
-
0
-
ns
30
-
35
-
45
ns
-
35
-
45
30
-
40
0
-
0
ns
30
35
0
-
-
0
-
-
ns
30
0
-
ns
Write Cycle
twc
Write Cycle Time
20
tcw
Chip Select to End of Write
15
tAW
Address Valid to End of Write
15
tAS
Address Set-up Time
0
-
twp
Write Pulse Width
15
-
20
tWR
Write Recovery Time
0
-
0
-
tWHZ(l)
Write Enable to Output in High Z
-
13
-
15
-
18
-
20
-
23
ns
tDW
Data to Write Time Overlap
12
15
-
25
-
ns
0
0
-
0
-
ns
Output Active from End of Write
0
-
20
Data Hold from Write Time
-
17
tDH
toW(1)
-
0
-
0
-
20
0
0
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
25
25
0
25
0
0
40
ns
ns
ns
ns
2830 tbltO
7.16
3
IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS
~
tRC--------------------~
~_____________________________________
-
CS
(1)
tAA - - - - - - - - - -..
-...t'
~--~--~--~--~---,--
tACS-----~
tClZ (5) _ _-I~
DATAoUT------------------------------~
2830 drw 05
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
DATAoUT
PREVIOUS DATA VALID
DATA VALID
2830 drw 06
TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)
CS~~_
.I~ (5)_--KIDK
~~.
_{
______!
________
. - tC_LZ__
DATAoUT
ICHt"
j)l-______
2830 drw 07
NOTES:
1. WE is high for read cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.16
4
IDT7MB4067
256K
x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
1~4~-------------------twc
ADDRESS
~--------------tAW
tAS
__ I~"~---------- twp (7)----------..... 1
tow (6)-t_---.l~
tWHZ (6)
DATAoUT
(4)
(4)
DATA VALID
DATAIN
2830 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,2,3,5)
4
ADDRESS
.
twc
~ fE
~ fE
4
tAW
~
-- _tAs
7 ~
~
4
..
tcw
----------------------------------~~
~tDW~
DATAIN
tWR
~:>~I-------------
-tDH-
___D_A_TA_V_A_Ll_D__
2830 drw 09
NOTES:
1.
2.
3.
4.
S.
6.
WE or CS must be high during all address transitions.
A write occurs during the overlap (~ of a low CS and a low WE.
twR is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state, and input signals must not be applied.
If the CS low transition transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
Transition is measured ±200mV from steady state with a SpF load (including scope and jig). This parameter is guaranteed by
design but not tested.
7. During a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tow) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tow.
7.16
5
IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
/..
~
3.010
~I
IP::::::[:::::jC::::K:::::Ji [
TOP VIEW
PIN 1
.
0.365
MAX.
r----,r-----,..---------.,r---------,
--:--..L.-.
+
T
J'~tmmfmmf'mm:"mnt~
.ICIC,X::K::JI
0.035
0.065
0.015
0.025
--.j
j..--0.100
TYP
SIDE VIEW
BOTTOM VIEW
7.16
~
,-
0.007
"0:"0"13
SIDE VIEW
0.120
0:175
2830drw 10
6
e;J
256K x 32
IDT7MP4045
BiCMOS/CMOS STATIC RAM
MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 8 megabit static RAM module
The IDT7MP4045 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability
of four chip select lines (one for each group of two RAMs)
provides byte access. Extremely fast speeds can be achieved
due to the use of 1 megabit static RAMs fabricated in IDT's
high performance, high reliability BiCEMOSTM technology.
The IDT7MP4045 is available with access time as fast as 10ns
with minimal power consumption.
The IDT7MP4045 is packaged in 64 pin FR-4 ZIP (Zigzag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 64 pins to be
placed on a package 3.65 inches long and 0.35 inches wide.
At only 0.60 inches high, this low profile package is ideal for
systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the IDT7MP4045 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of
use.
Two identification pins (PDO and PD1) are provided for
applications in which different density versions of the module
are used. In this way, the target system can read the
respective levels of PDO and PDl to determine a 256K depth.
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module)
• Ultra fast access time: 1Ons (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
a
• Inputs/outputs directly TTL compatible
PIN CONFIGURATION(1)
PDo
2
1/00
1/01
1/02
1/03
4
Vee
A7
12
14
A8
A9
16
18
1/04
1/05
1/06
1/07
20
22
WE
28
30
A14
CSl
GND
POl
10
11
13
15
17
19
21
23
25
24
26
27
32 ZIP,SIMM
TOP VIEW
CS3
A16
GND
1/016
1/017
1/018
1/019
AlO
All
A12
A13
1/020
1/021
1/022
1/023
GND
34
36
38
40
4:>
44
46
48
50
52
54
56
58
60
62
64
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1/08
1/09
1/010
1/011
PDo-GND
PD1-GND
Ao
Al
A2
1/012
1/013
1/014
1/015
GND
A15
CS2
FUNCTIONAL BLOCK DIAGRAM
CSl
CS3
CS4
1/025
1/026
1/027
A3
A4
A5
PIN NAMES
1/00-31
2703 drw 02
Vee
1/00-31
Data Inputs/Outputs
A6
Ao-17
Addresses
1/028
1/029
1/030
1/031
CSl-4
Chip Selects
WE
Write Enable
OE
Output Enable
PDO-l
Depth Identification
2703 drw 01
NOTE:
1. Pins 2 and 3 (PDo and PD1) are read by the user to determine the density
of the module. If PDo reads GND and PD1 reads GND, then the module
had a 256K depth.
Vee
Power
GND
Ground
NC
No Connect
2703 tbl 01
BiCEMOS and CEMOS are trademarks of Integrated Device Technology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
©1992 Integrated
CS2
CS4
A17
OE
1/024
DSC-706113
Device Technology, Inc.
7.17
IDTIMP4045 256K x 32
BiCMOS/CMOS STATIC RAM MODULE
CAPACITANCE
(TA
TRUTH TABLE
= +25°C, F = 1.0MHz)
Parameter(1)
Symbol
COMMERCIAL TEMPERATURE RANGE
Conditions
Max.
Unit
CS
OE
WE
Output
Power
CIN(D)
Input Capacitance
(Data)
V(IN) = OV
12
pF
Standby
H
X
X
High Z
Standby
Read
L
L
H
DATAoUT
Active
CIN(A)
Input Capacitance
(Address & Control)
V(IN) = OV
70
pF
Write
L
X
L
DATAIN
Active
COUT
Output Capacitance
V(OUT) = OV
12
pF
Read
L
H
H
High-Z
Active
NOTE:
1. This parameter is guaranteed by design but not tested.
Mode
2703 tbl 05
2703tbl 02
ABSOLUTE MAXIMUM RATINGS(l}
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
VTERM
Rating
Terminal Voltage with
Respect to GND
Value
Unit
-0.5 to +7.0
V
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Temperature
oto +70
°C
Vee
Supply Voltage
4.5
5.0
5.5
V
T81AS
Temperature Under Bias
-10 to +85
°C
GND
Supply Voltage
a
0
a
V
TSTG
Storage Temperature
VIH
Input High Voltage
2.2
-
6.0
V
lOUT
DC Output Current
VIL
Input Low Voltage
-{l.5(1)
-
0.8
Symbol
NOTE:
1. VIL (min)
V
2703 tbl 03
= -1.5V for pulse width less than 10ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
-55 to +125
°C
50
mA
NOTE:
2703 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Vee
5.0V±10%
2703 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Vce = 5.0V +1
- 0%, TA = O°C to +70°C)
Max.
Unit
Input Leakage
(Address and Control)
Vee = Max.; VIN = GND to Vee
-
80
J.lA
Ilul
Input Leakage (Data)
Vee = Max.; VIN =GND to Vee
Output Leakage
Vee = Max.; CS = VIH, VOUT = GND to Vee
-
10
IILOI
10
J.lA
J.lA
VOL
Output Low
Vee = Min., IOL = 8mA
-
0.4
V
VOH
Output High
Vee = Min., IOH = -4mA
2.4
-
Symbol
Ilul
Parameter
Test Conditions
Min.
V
2703 tbl 07
10ns - 17n5(1)
Symbol
Parameter
Test Conditions
Max.
20n5 - 45ns
Max.
Unit
Icc
Dynamic Operating
Current
f = fMAX; CS = VIL
Vee = Max.; Output Open
1600
1200
rnA
158
Standby Supply
Current
CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX
480
480
mA
1581
Full Standby
Supply Current
CS~ Vee- 0.2V; f = 0
VIN > Vee - 0.2V or < 0.2V
320
80
mA
NOTE:
1. Preliminary specifications only.
2703 tbl 08
7.17
2
IDT7MP4045 256K x 32
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GNDto 3.0V
Input Rise/Fall Times
Sns
Input Timing Reference Levels
1.SV
Output Reference Levels
1.SV
Output Load
See Figures 1-4
2703 tbl 09
. +SV
+SV
480n
DATAoUT
2550
480n
DATAoUT------------r-------~
Lr30PP
2550
2703 drw 03
~
_
SpF.
~
2703 drw 04
·Includes scope and jig.
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ,tOHZ, tCHZ, tCLl, twHZ, tow)
DATA OUT .l:_¥------:L~~
Zo=SOO
=
tsao
ATM
(Typical, ns)
5
1.SV
2703 drw 05
Figure 3. Alternate Output Load
20
40
60
80
100 120 140 160 180
200
CAPACITANCE (pF)
2703 drw 06
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
7.17
3
IDT7MP4045 256K x 32
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
VCC = 5V ±1 0%, TA = O°C to +70°C)
7MP4045SxxZ, 7MP4045SxxM
-12(2)
-15(2)
-10(2)
Symbol Parameter
Read Cycle
Min.
Max.
Min.
Max.
Min.
Max.
_17(2)
Min.
Max.
Unit
tRC
Read Cycle Time
10
-
12
-
15
-
17
-
ns
tM
Address Access Time
-
-
12
Chip Select Access Time
-
-
8
-
15
10
-
tACS
tCLZ(1)
10
7
ns
Chip Select to Output in Low Z
2
-
2
2
-
2
tOE
tOLZ(1)
Output Enable to Output Valid
-
5
-
5
17
12
-
-
6
-
8
ns
Output Enable to Output in Low Z
2
-
2
-
2
-
2
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
6
-
7
-
8
-
10
ns
tOHZ(1)
Output Disable to Output in High Z
-
3
-
4
-
5
-
6
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
ns
15
-
-
10
0
10
0
-
17
10
12
ns
9
-
ns
-
ns
ns
Write Cycle
twc
Write Cycle Time
10
-
12
tcw
Chip Select to End of Write
8
8
tAW
Address Valid to End of Write
8
-
tAS
Address Set-up Time
0
twp
Write Pulse Width
8
-
9
tWR
tWHZ(1)
Write Recovery Time
0
-
0
-
Write Enable to Output in High Z
-
5
-
5
tow
Data to Write Time Overlap
5
Data Hold from Write Time
0
2
5
0
2
-
tOH
toW(1)
-
-
0
2
Output Active from End of Write
-
9
0
-
0
12
-
0
-
6
-
6
-
0
-
2
8
ns
ns
ns
ns
7
ns
-
ns
ns
ns
2703 tbll0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
7.17
4
IDT7MP4045 256K x 32
BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V +10%,
TA = O°C to +70°C)
7MP4045SxxZ 7MP4045SxxM
-25
-20
Symbol
Parameter
Read Cycle
Min.
Max.
Min.
-30
Max.
Min.
-35
Max.
Min.
-45
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
20
-
25
-
30
-
35
-
45
-
ns
tAA
Address Access Time
-
20
-
25
-
30
35
-
45
ns
tACS
Chip Select Access Time
-
20
-
25
-
30
-
35
-
45
ns
tCLZ(1)
Chip Select to Output in Low Z
5
-
5
-
-
5
-
ns
tOE
Output Enable to Output Valid
-
10
tOLZ(1)
Output Enable to Output in Low Z
0
-
0
-
0
-
tCHZ(1)
Chip Deselect to Output in High Z
-
12
-
15
Output Disable to Output in High Z
-
10
tOHZ(1)
10
tOH
Output Hold from Address Change
3
3
-
5
Chip Select to Power·Up Time
0
-
3
tpu(1)
-
0
-
tPO(1)
Chip Deselect to Power-Down Time
-
20
-
25
-
-
25
-
-
25
10
-
0
12
10
5
-
15
5
-
18
-
23
ns
-
0
-
ns
-
18
ns
10
-
20
-
10
ns
0
5
-
ns
0
-
0
-
ns
30
-
35
-
45
ns
30
-
35
-
45
-
ns
25
-
30
-
40
-
ns
25
-
30
40
35
-
ns
30
-
0
-
0
-
ns
Write Cycle
twc
Write Cycle Time
20
tew
Chip Select to End of Write
15
tAW
Address Valid to End of Write
15
tAS
Address Set-up Time
0
twp
Write Pulse Width
15
tWA
tWHZ(1)
Write Recovery Time
0
Write Enable to Output in High Z
-
13
-
15
-
18
-
20
-
23
ns
tow
Data to Write Time Overlap
12
-
25
0
-
ns
0
Output Active from End of Write
0
-
20
0
-
17
Data Hold from Write Time
-
15
tOH
toW(1)
0
-
0
-
20
20
0
20
0
0
0
NOTES:
0
0
0
0
0
0
ns
ns
ns
ns
2703tblll
1. This parameter is guaranteed by design, but not tested.
7.17
5
IDTIMP4045 256K x 32
BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
----------~
ADDRESS
CS
~CS----------r_--~
tCLl (5) _____
~
DATA OUT
2703 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
~::~_-~~_-~~_-~~_-~~_-~~t~O~H~~-_~~-_~~~t~A_A~~-_-_-t~R_C~--------------.-I----~~-t-OH----------PREVIOUS DATA VALID
DATA VALID
2703 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
~ ~~
tm(5)
t tCHZ~
1
DATAOUT-------I--+«XX>K-----------~
2703 drw 06
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.17
6
IDT7MP4045 256K x 32
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED) (1,2,3,7)
twc
ADDRESS
~V
) V~
-----./ ~
DE
/
V
tAW
CS ~
~
V
/
twp (7)
~tAS
'~
f4-
tWR_
/
tWHZ
(6) _
tOHZ(6)
tOHZ (6)
DATA OUT
(4)
V
tOW(6)_
f--
V
"-
~
/
14--
V
DATA IN
"
tDW
(4)
) I-
tDH
DATA VALID
"
/
2703 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED) (1,2,3,5)
twc
ADDRESS
)
K
)
K
tAW
1-4-
tAS
l'
/
tWR
tDW
DATAIN
~
tcw
-----------------«E
~I
...
tDH
DATA VALID
2703 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (~ of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, 110 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7.17
7
IDT7MP4045 256K x 32
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
ZIP VERSION
"I
3.640
3.660
1..
•
:"~~---.t
PIN1
g:g~;
....1. . .
0.250
~"~
~r-...,~ ~
TYP.
0.100
TYP.
0.050
TYP.
0.125
SIDE VIEW
0":'19l)
FRONT VIEW
BACK VIEW
SIMM VERSION
2703 drw 12
3.840
~------------~------------------~~
SIDE VIEW
PIN 1
I
0
0.350
MAX.
.!:. . . . ~.l.". . ,. . ~L"",. . .!.~!.............l'\~
,I,
BACK VIEW
2703 drw 13
PIN 1
•
7.17
8
(;)~
Integrated Device Technology, Inc.
SUBSYSTEMS FLEXI-PAKTM FAMILY
32Kx32
128Kx32
CMOS STATIC RAM MODULES
IDT7M4003
IDT7M4013
FEATURES:
DESCRIPTION:
•
The IDT7M4003/4013 are high-speed, high-density
1megabitl4 megabit CMOS static RAM modules constructed
on a mUlti-layer co-fired ceramic substrate using either 32K x
8 or 128K x 8 SRAM components.
These modules are part of the IDT Subsytems "Flexi-Pak"
Family. This family of SRAM/EEPROM/EPROM memory
modules support applications requiring stand alone static or
programmable memory or those applications needing a combination of both. All three module configurations have equivalent pin-outs, making these "plug-in compatible" with each
other (Le. inter-changeable) suitable for a wide range of
applications.
The IDT7M4003/4013 is available with access times as
fast as 15ns over the commercial temperature range and
20ns over the military temperature range.
This family of IDT modules are offered in a 66-pin, ceramic
HIP (Hex In-line Package). This HIP package is similar to a
PGA and allows the designer to fit 1 megabitl4 megabit of
memory into 1 sq. inch of board space.
AIiIDT military modules are assembled with semiconductor components compliant with the latest revision of M IL-STD883, Class S, making them ideally suited to applications
demanding the highest level of performance and reliability.
•
•
•
•
•
•
•
•
•
High-density 1 megabitl4 megabit CEMOSTM static RAM
modules
Member of the Subsystems "Flexi-Pak" Family of interchangeable modules, with equivalent pin-outs, supporting a wide range of applications
Footprint compatible module upgrades to the next higher
density with relative ease
Fast access times:
7M4003 - 15ns (max.) commercial
7M4003 - 20ns (max.) military
7M4013 - 15ns (max.) commercial
7M4013 - 20ns (max.) military
Low power CMOS operation
Surface mounted LCC or SO components on a multilayered co-fired ceramic substrate
Offered in a 66-pin "PGA-type" HIP (Hex In-line Package), occupying only 1 sq. inch of board space
Single 5V (±10%) power supply
Multiple ground pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
FUNCTIONAL BLOCK DIAGRAM
1/08-11015
1/016-1/023
or
128K x 8
or
128K x 8
32K x8
or
128K x 8
32K x 8
or
128K x 8
CEo WEo
CE1 WE 1
CE2 WE 2
CE3 WE3
Ao-A16
OE
1/024 -1/031
1/00-1/07
2711 drw 01
CMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC-7069/2
©1992 Integrated Device Technology, Inc.
7.18
ID17M4003/4013 (32K1128K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION(1)
1/08
1109
1/010
A13
A14
A15
A16
GND
1/00
1/01
1/02
WE1
CS1
GND
1/011
A10
A11
A12
Vee
CSo
GND
1/03
1/015
1/014
1/013
1/012
OE
GND
WEo
1/07
1/06
1/05
1/04
.1 .12
.2 • 13
03 .14
• 4 .15
• 5 .16
• 6 .17
• 7 .18
• 8 .19
• 9 .20
• 10.21
• 11 .22
.23
.24
025
.26
.27
.28
.29
.30
.31
.32
.33
34.45.560
35.46.57 •
36047058.
37.48.59 •
38.49.60 •
39.50.61 •
40.51.62 •
41.52.63 •
42.53.64 •
43.54.65 •
44.55.66 •
1/024
1/025
1/026
A6
A7
GND
A8
A9
1/016
1/017
1/018
1/031
1/030
1/029
1/028
Ao
A1
A2
1/023
1/022
1/021
1/020
Vee
CS3
WE3
1/027
A3
A4
A5
WE2
CS2
GND
1/019
HIP
TOP VIEW
2711 drw 02
NOTE:
1. For the IDT7M4003 (32K x 32) version, pins 6 and 7 are no connects.
ABSOLUTE MAXIMUM RATINGS(1)
PIN NAMES
Name
Symbol
Description
1/00-31
Data InputslOutputs
AO-16
Address Inputs
WEn-3
Write Enables
CSO-3
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
2711 tbl01
Parameter
Conditions
Max.
Unit
CIN(1)
Input Capacitance
(DATA, CS, WE)
VIN = OV
50
pF
CIN(2)
Input Capacitance
(ADDRESS, OE)
VIN = OV
12
pF
COUT
Output Capacitance
VOUT= OV
12
NOTE:
1. This parameter is guaranteed by design, bu't not tested.
pF
2711 tbl02
Output
Military
Unit
-0.5 to +7.0
V
o to +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125
-65to+135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
TA
Operating
Temperature
TBIAS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
TRUTH TABLE
Mode
Power
CS
DE
WE
Standby
H
X
X
High-Z
Read
L
L
H
DATAoUT
Active
Read
L
H
H
High Z
Active
Write
L
X
L
DATAIN
Active
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
NOTE:
2711 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
Rating
VTERM
Parameter
Min.
Typ.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
Max. Unit
0.8
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
Standby
2711 tbl03
V
2711 tbl 05
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V± 10%
DOC to +70°C
OV
5.0V±10%
2711 tbl06
7.18
2
•
IDTIM4003/4013 (32K1128K x 32)
CMOS STAllC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ± 10%, TA = -55°C to + 125°C and O°C to +70°C)
Min.
Max.!l)
Max.<2)
Unit
IILlI
Input Leakage Current
(Address,OE)
Vee = Max., VIN = GND to Vee
-
5
10
J.lA
IILlI
Input Leakage Current
(Data, CS, WE)
Vee = Max., VIN = GND to Vee
-
20
40
J.lA
IILol
Output Leakage Current
Vee = Max.
CS = VIH, VOUT = GND to Vee
-
5
10
J.lA
lee
Dynamic Operating Current
Vee = Max., CS 5; VIL
f = fMAX, Output Open
-
800
880
mA
IS8
Standby Supply Curent
Vee = Max., CS ~ VIH
f = fMAX, Output Open
-
80
280
mA
IS81
Full Standby Supply Current
CS ~ Vee -0.2V
VIN > Vee -0.2V or < 0.2V
-
80
80
mA
VOL
Output Low Voltage
Vee = Min., IOL = 8mA(3)
-
0.4
0.4
V
VOH
Output High Voltage
Vee = Min., IOH = -4mA(4)
2.4
-
-
Symbol
Parameter
Test Conditions
V
2711 tbl 07
NOTES:
1. For TA = ooe to +70 oe versions only.
2. For TA = -55°C to + 125°C versions only.
3. 10l = 2mA for 70ns -100ns versions of the IDT7M4013.
4. IOH = -1mA for 70ns -100ns versions of the IDT7M4013.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
10ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1 and 2
Output Load
2711 tbl07
+5V
4800
4800
DATAoUT--------~------~
2550
DATAoUT--------~------~
2550
30 pF*
2711 drw 03
5 pF*
2711 drw 04
Figure 2. Output Load
(for tClZ, tOll, tCHz, tOHZ, tow, tWHZ)
Figure 1. Output Load
"Including scope and jig
7.18
3
IDT7M4003/4013 (32K!128K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ± 10%, TA = -55°C to + 125°C and O°C to +70°C)
_17(2)
_15(2)
Parameters
Symbol
Min.
Max.
Min.
_20(2)
Max.
Min.
-25
Max.
Min.
-30
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
-
17
-
20
-
25
-
30
-
ns
tM
Address Access Ti me
-
-
~
-
20
20
-
30
30
Chip Select to Output in Low Z
5
-
5
-
5
25
25
ns
Chip Select Access Time
17
17
-
tACS
tCLZ(1)
15
15
-
5
-
ns
tOE
tOLZ(1)
Output Enable to Output Valid
Output Enable to Output in Low Z
tCHZ(1)
-
5
-
10
-
11
-
12
-
13
-
15
ns
0
-
0
-
0
-
2
-
2
-
ns
Chip Deselect to Output in High Z
-
6
tOHZ(1)
Output Disable to Output in High Z
-
6
-
7
7
-
7
-
12
12
-
15
13
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
3
-
ns
-
17
13
13
0
13
0
-
20
15
15
0
15
0
-
25
20
20
0
20
0
-
30
25
25
0
23
0
-
8
-
-
12
-
13
ns
-
9
13
3
5
-
15
3
5
-
ns
8
ns
ns
WRITE CYCLE
tAW
Address Valid to End of Write
lAS
Address Set-up Time
twp
Write Pulse Width
tWR
tWHZ(1)
Write Recovery Time
15
12
12
0
12
0
Write Enable to Ouput in High Z
-
6
tow
Data to Write Time Overlap
8
tOH
toW(1)
Data Hold from Write Time
0
0
-
twc
Write Cycle Time
tcw
Chip Select to End of Write
Output Active from End of Write
-
,...-
8
0
0
NOTES:
-
0
0
-
9
-
ns
ns
ns
ns
ns
ns
ns
ns
2711 tbl 09
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specification only.
II
7.18
4
IDT7M4003/4013 (32K1128K x 32)
CMOS STAl1C RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vce = 5.0V ± 10%, TA = -55°C to +125°C and O°C to +70°C)
·35
Symbol
Parameters
Min.
·50
·40
Max.
Min.
Max.
Min. Max.
·60
·70
·85
(Mil. Only)
(Mil. Only) (Mil. Only)
Min. Max. Min. Max. Min. Max. Unl
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
35
-
tACS
Chip Select Access Time
-
tCLZ(l)
Chip Select to Output in Low
tOE
Output Enable to Output Valid
tOLZ(1)
Output Enable to Output in Low Z
tCHZ(l)
Chip Deselect to Output in High
Z
5
2
-
-
40
-
50
-
60
-
35
35
-
40
40
-
50
50
-
60
60
-
-
5
-
5
-
25
20
20
-
-
5
5
-
30
20
20
20
5
-
-
85
-
70
70
-
-
5
-
-
30
-
35
5
-
5
-
-
25
25
-
30
30
-
5
5
-
70
-
tOHZ(l)
Z
Output Disable to Output in High Z
-
17
15
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
35
30
30
40
35
35
50
45
45
-
2
-
40
-
60
55
55
5
45
-
70
65
65
5
45
20
a
25
a
85
85
ns
-
ns
ns
-
40
35
35
5
-
ns
-
85
80
80
5
50
-
ns
-
ns
-
ns
30
-
ns
-
35
5
5
35
-
-
ns
ns
ns
ns
ns
ns
WRITE CYCLE
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
a
-
twp
Write Pulse Width
25
-
30
-
tWR
Write Recovery Time
a
-
a
-
a
tWHZ(l)
Write Enable to Ouput in High
-
17
-
20
-
tDW
Data to Write Time Overlap
-
16
-
tDH
Data Hold from Write Time
-
3
tow(1)
Output Active from End of Write
16
3
5
-
5
-
25
5
5
Z
2
NOTE:
-
-
30
5
5
-
-
30
5
5
-
a
ns
ns
ns
ns
ns
2711 tbl 10
1. This parameter is guaranteed by design, but not tested.
7.18
5
IDT7M4003/4013 (32K1128K x 32)
CMOS STAllC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~----------------- tRC
ADDRESS
tall (5) 1'4------+-1
tACS --~f----~
tCll (5) _ _~~
DATAoUT
2711 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
={~.------~H
tRC
_ _ _ _ _ _ _ _ __
W
~----------D-AT-A-V-A-Ll-D-~~~2711 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
~~
DATAoUT
tCll (5)
i
l
•• ••
•• ••
••
••
•.~
••
•
•
rut
• 1
0.200
MAX .
--;J
i
!1Q.1.§..
O.~50 0.025
MAX .
0.250
MAX.
•
~
~
0.610
0.990
1.010
7.18
2711 drw11
8
IDT7M4003/4013 (32K1128K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7M4013SxxNH
PIN1
L
'" 1
1.355------'
1 385
.
~
,TOIDlID~O
l
~
1.385
1"---~I'
0.100
--.t... 0.015
+
TYP.--.j ~
PIN1
~
••
•••
•• ••
• ••
••
•••
.~
••
0.250
MAX .
mt
.,1
--;J
0.025
O'050
MAX .
0.305
MAX.
I~I
~
0.990
1.010
2711 drw 12
7.18
9
(;5
64K x 32
BiCMOS/CMOS STATIC RAM
MODULE
IDT7MP4036
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 2 megabit static RAM module
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package) or
64 pin SIMM (Single In-line Memory Module)
• Ultra fast access time: 1Ons (max.)
• Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum
noise immunity
• Inputs/outputs directly TIL compatible
The IDT7MP4036 is a 64K x 32 static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 64K
x 4 static RAMs in plastic SOJ packages. Availability of four
chip select lines (one for each group of two RAMs) provides
byte access. Extremely fast speeds can be achieved due to
the use of 256K static RAMs fabricated in IDT's high performance, high reliability CEMOSTM and BiCEMOSTM technology.
The IDT7MP4036 is available with access time as fast as 10ns
with minimal power consumption,
The IDT7MP4036 is packaged in a 64 pin FR-4 ZIP {Zigzag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 64 pins to be
placed on a package 3.65 inches long and 0.35 inches wide.
At only 0.50 inches high, this low profile package is ideal for
systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the IDT7MP4036 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh foroperation and provides equal access and cycle times for ease of
use.
Two identification pins (PDO and PD1) are provided for
applications in which different density versions of the module
are used. In this way, the target system can read the
respective levels of PDO and PD1 to determine a 64K depth.
PIN CONFIGURATION(1)
POD
1/00
1/01
1/02
1/03
Vee
A7
A8
A9
1/04
1/05
1/06
1/07
WE
A14
CSl
CS3
NC
GND
1/016
1/017
1/018
1/019
Al0
All
A12
A13
1/020
1/021
1/022
11023
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
POl
1/08
1/09
1/010
1/011
AD
Al
A2
1/012
1/013
1/014
1/015
GND
A15
CS2
POD-OPEN
PD1-GND
FUNCTIONAL BLOCK DIAGRAM
CSl
CS4
NC
OE
1/024
1/025
1/026
1/027
A3
A4
A5
CS3
CS4
1/00-31
Vee
PIN NAMES
A6
1/028
1/029
1/030
1/031
2682 drw 02
ZIP,SIMM
TOP VIEW
NOTE:
1. Pins 2 and 3 (PDo and PDt) are read by the user to determine the density
of the module. If PDo reads Open and PDt reads GND, then the module
had a 64K depth.
2682 drw at
1/00-31
Data Inputs/Outputs
Ao-15
Addresses
CSl-4
Chip Selects
WE
Write Enable
OE
Output Enable
PDO-1
Depth Identification
Vcc
Power
GND
Ground
NC
No Connect
2682tbiOt
BiCEMOS and CEMOS are trademarks of Integrated Device Technology, Inc.
COMMER~ALTEMPERATURERANGE
Vee - 0.2V or < 0.2V
2682 tbl 08
7.19
2
x 32
BICMOS/CMOS STATIC RAM MODULE
IDT7MP4036 64K
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1-4
Output Load
2682tbl09
+5V
+5V
480.0
480.0
DATA OUT--.----.
255.0
DATAoUT-....--....
30pF*
255.0
2682 drw 04
2682 drw 03
*incluces scope and jig.
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tOHZ, tcHZ, tCLl, tWHZ, tow)
8
6
•
ATAA
(Typical, ns)
5
4
DATAoUT
!Y---Z-O-=-5-0-.o--~-r150n
1.5V
20
2682 drw 05
40
60
80
100
120 140
160 180
200
CAPACITANCE (pF)
2682 drw06
Figure 4. Alternate Lumped capacitive Load,
Typical Derating
Figure 3. Alternate Output Load
7.19
3
IDT7MP4036 64K x 32
BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ±1 0%, TA = DOC to +70°C)
7MP4036BxxZ, 7MP4036BxxM
-12(2)
-15
-10(2)
Symbol Parameter
Read Cycle
Min.
Max.
Min.
Max.
Min.
Max.
-17
Min.
Max.
Unit
17
2
-
ns
17
ns
9
ns
-
ns
6
-
8
ns
-
2
ns
tRC
Read Cycle Time
10
-
12
-
15
-
tM
Address Access Time
Chip Select Access Time
10
7
-
12
7
-
15
tACS
-
tClZ(1)
Chip Select to Output in Low Z
2
-
2
-
2
-
tOE
Output Enable to Output Valid
-
4
-
5
-
tOlZ(1)
Output Enable to Output in Low Z
2
-
2
-
2
tCHZ(1)
Chip Deselect to Output in High Z
-
6
-
-
Output Disable to Output in High Z
-
4
-
-
8
tOHZ(1)
7
5
10
5
-
6
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
ns
15
-
-
ns
9
-
-
ns
7
ns
8
ns
Write Cycle
twc
Write Cycle Time
12
Chip Select to End of Write
10
7
-
tcw
-
8
tAW
Address Valid to End of Write
8
9
tAS
Address Set·up Time
0
0
-
twp
Write Pulse Width
8
9
tWR
tWHZ(1)
Write Recovery Time
0
-
-
0
-
10
0
10
0
-
17
10
12
0
12
0
Write Enable to Output in High Z
-
4
-
5
-
6
-
tDW
Data to Write Time Overlap
6
6
Data Hold from Write Time
tow(1)
Output Active from End of Write
0
2
-
7
0
2
-
9
tDH
-
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
0
2
-
0
2
-
ns
ns
ns
ns
ns
ns
ns
2682 tbl10
7.19
4
ID17MP4036 64K x 32
BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V +1
- 0%, TA = O°C to +70°C)
7MP4036SxxZ, 7MP4036SxxM
-20
Symbol
Parameter
Read Cycle
Min.
-25
Max.
-35
Min.
Max.
Min.
Max.
Unit
35
-
35
35
25
ns
tRC
Read Cycle Time
20
-
25
tAA
Address Access Time
-
tACS
tCLZ(1)
Chip Select Access Time
-
-
3
tOE
Output Enable to Output Valid
10
-
25
25
12
tOLZ(1)
Output Enable to Output in Low Z
3
0
20
20
-
0
-
tCHZ(1)
Chip Deselect to Output in High Z
tOHZ(1)
Output Disable to Output in High Z
-
10
10
-
tOH
Output Hold from Address Change
Chip Select to Power-Up Time
-
3
tpu(1)
3
0
15
15
-
0
-
3
0
3
0
tPD(1)
Chip Deselect to Power-Down Time
-
20
-
25
-
-
25
20
20
0
20
0
-
35
30
30
0
30
0
Chip Select to Output in Low Z
-
ns
ns
ns
ns
-
ns
22
22
35
ns
-
ns
-
ns
ns
ns
ns
ns
Write Cycle
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
tWHZ(1)
Write Recovery Time
20
15
15
0
15
0
Write Enable to Output in High Z
-
12
-
15
-
18
ns
tow
Data to Write Time Overlap
15
0
0
-
20
0
0
ns
Data Hold from Write Time
-
-
tDH
toW(1)
12
0
0
-
ns
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
Output Active from End of Write
NOTE:
1. This parameter is guaranteed by design, but not tested.
ns
ns
ns
ns
ns
2682 tblll
II
I
7.19
5
IDl7MP4036 64K x 32
BlCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ----------~
ADDRESS
CS
~--~-+~--------------------------~------~~~~~--~~'-~~~~~
~CS -------+---4~
tCLZ (5)
-----~
DATAoUT-----------------------------------~
•
2682 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
DATAoUT
PREVIOUS DATA VALID
DATA VALID
2682 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
DATAoUT
~-tCLZ(5)-~CS-~-.1===_L_'CHZ(5)==j
---j<::><:~
~
2682 drw 09
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.19
6
IDTIMP4036 64K x 32
BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLED TIMING){1, 2, 3, 7)
twc
)(
ADDRESS
)(
./ ~
tAW
~
K
f4-
./
twp
tAS
(7)
~
tWR-
~~
./
~
f - - - tWHZ(6) -
(4)
DATAoUT
-tOHZ~
tow (6)
tOHZ (6)
"
./
lr
tDH
(4)
)-
tDW-
V
DATAIN
I'
DATA VALID
"'"
./
2682 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING){1, 2, 3, 5)
twc
ADDRESS
-
)
K
K
tAW
~
DATAIN
)
tAS
'1
/
/
tWR
tcw
-------t::[
tDW
.. I.
DATA VALID
tDH
3;lt---- II
2682 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going High to the end of write cycle.
4. During this period, I/O pins are in the output state, input signals must not be applied.
5. If the CS Low transition occurs simultaneously with or after the WE Low transition, the outputs remain in a high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but, not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tow) to allow the I/O drivers to turn off data and
to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7,19
7
IDT7MP4036 64K x 32
BiCMOS/CMOS STATIC RAM MODULE
PACKAGE DIMENSIONS
ZIP VERSION
0.500
MAX.
PIN 1
COMMERCIAL TEMPERATURE RANGE
I~
~I
3.640
3.660
D~D~D~D~ -.l
~.~£T- °T~5~." t--
:tr- j~ :t
TYP.
TYP.
SIDE VIEW
0l9ci""
FRONT VIEW
BACK VIEW
2682 drw 12
SIMM VERSION
l.tl+-
_~_O~5
.
0.055
PIN 1
SIDE VIEW
FROtfTVlEW
2682 drw 13
7.19
8
(;)
16K x 32
BiCMOS/CMOS STATIC
RAM MODULE
IDT7MP4031
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
High density 512K static RAM module
Low profile 64 pin ZIP (Zig-zag In-line Package)
Ultra-fast access time: 8ns (max.)
Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
• Multiple GND pins for maximum noise immunity
PIN CONFIGURATION(1)
PDo
1/00
1/01
1/02
1/03
Vee
A7
A8
A9
1/04
1/05
1/06
1/07
WE
NC
CS1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
CS3
NC
GND
1/016
1/017
1/018
1/019
AlO
Al1
A12
A13
1/020
1/021
1/022
1/023
GND
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1 GND
3 PD1
5 1/08
1/09
1/010
11 1/011
13 Ao
15 A1
17 A2
19 1/012
21 1/013
23 1/014
25 1/015
27 GND
29 NC
31 CS2
PDo-GND
PD1-0PEN
The IDT7MP4031 is a 16K x 32 static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 16K
x 4 static RAMs in plastic SOJ packages. Availability of four
chip select lines (one for each group of two RAMs) provides
byte access. Extremely fast speeds can be achieved due to
the use of 64K static RAMs fabricated in lOT's high performance, high reliability BiCEMOSTM or CEMOSTM technology.
The IDT7MP4031 is available with access time as fast as 8ns
with minimal power consumption.
The IDT7MP4031 is packaged in a 64 pin FR-4 ZIP (Zigzag In-line Package). The dual row configuration allows 64
pins to be placed on a package 3.65 inches long and 0.35
inches wide. At only 0.50 inches high, this low profile package
is ideal for systems with minimum board spacing.
All inputs and outputs of the IDT7MP4031 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for
operation and provides equal access and cycle times for ease
of use.
Two identification pins (PDO and PD1) are provided for
applications in which different density versions of the module
are used. In this way, the target system can read the
respective levels of PDO and PD1 to determine a 16K depth.
FUNCTIONAL BLOCK DIAGRAM
33 CS4
35 NC
37 OE
39 1/024
41 1/025
43 1/026
45 1/027
47 A3
49 A4
51 A5
53 Vee
55 A6
57 1/028
59 1/029
61 1/030
63 1/031
1/00-31
2681 drw 01
PIN NAMES
1100-31
Data Input/Output
Ao-13
Addresses
2681 drw 02
ZIP
TOP VIEW
NOTE:
1. Pins 2 and 3 (PDO and PD1) are read by the user to determine the depth
of the module. If PDO reads GND and PD1 reads Open, then the module
has 16K depth.
CS1-4
Chip Select
WE
Write Enable
OE
Output Enable
PDO-1
Depth Identification
Vcc
Power
GND
Ground
2681 tbl01
BiCEMOS and CEMOS are trademarks of Integrated Device Technology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-705413
©1992 Integrated Device Technology, Inc.
7.20
II
IDTIMP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
TRUTH TABLE
Conditions
Max.
Unit
Mode
CS
OE
WE
Output
Power
CIN(D)
Input Capacitance
(Data)
V(IN) = OV
15
pF
Standby
H
X
X
HighZ
Standby
Read
L
L
H
DATAoUT
Active
CIN(A)
Input Capacitance
(Address & Control)
V(IN)", OV
70
pF
Write
L
X
L
DATAIN
Active
COUT
Output Capacitance
V(OUT) '" OV
15
pF
Read
L
H
H
High-Z
Active
NOTE:
2681 tbl05
2681 tbl 02
1. This parameter is guaranteed by design, but not tested.
ABSOLUTE MAXIMUM RATINGS(l)
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Vee
GND
VIH(2)
VIL
VTERM(2)
Parameter
Min.
Typ.
Max.
Unit
Supply Voltage
4.5
5.0
5.5
V
Supply Voltage
0
0
0
Input High Voltage
2.2
-
6.0
Input Low Voltage
-0.5(1)
-
0.8
NOTES:
V
V
V
1. VIL (min) = -:-1.SV for pulse width less than 10ns.
2. I/O pins must not exceed Vcc +O.SV.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Value
Unit
-0.5 to +7.0
V
TA
Operating Temperature
o to +70
°C
TBIAS
Temperature Under Bias
-10 to +85
°C
TSTG
Storage Temperature
lOUT
DC Output Current
-55 to +125
°C
50
rnA
NOTES:
2681 tbl03
Grade
Rating
Terminal Voltage with
Respect to GND
2681 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. 1/0 pins must not exceed vee +O.SV.
Vee
5.0V ± 10%
2681 tbl04
DC ELECTRICAL CHARACTERISTICS
= 5 OV +10%
TA = O°C to +70°C)
-
(Vce
7MP4031S 7MP40318
Symbol
Max.
Max.
Unit
Input Leakage
(Address and Control)
Vee", Max.; VIN '" GND to Vee
-
40
80
J.LA
IILlI
Input Leakage (Data)
Vee", Max.; VIN '" GND to Vee
10
J.LA
Output Leakage
Vee", Max.; CS '" VIH, VOUT '" GND to Vee
-
5
ILO
5
10
.f.lA
VOL
Output Low
Vee", Min., IOL '" 8mA
-
0.4
0.4
V
VOH
Output High
Vee", Min., IOH '" -4mA
2.4
-
-
V
IILlI
Parameter
Test Conditions
Min.
2681 tbl07
Symbol
Parameter
Test Conditions
7MP40318
7MP4031S
8 -15ns
20 - 35ns
Max.
Unit
1200
rnA
Max.
lec
Dynamic Operating
Current
Vee", Max.; CS", VIL; f '" fMAX
Output Open
1600
IS8
Standby Supply
Current
CS ~ VIH, Vee", Max.
f '" fMAX, Outputs Open
-
480
rnA
IS81
Full Standby
Supply Current
CS~ Vee- 0.2V; f '" 0,
VIN> Vee - 0.2V or < 0.2V
-
160
rnA
2681 tbl 08
7.20
2
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1-4
Output Load
26811bl09
+5V
+5V
480n
DATAoUT-__255Q
480Q
....
DATAoUT-__30pF*
....
255n
2681 drw 04
2681 drw 03
"Including scope and jig.
Figure 2. Output load
(for tCHZ, tClZ, tOHZ, tOlZ, tWHZ and tOW)
Figure 1. Output load
aTAA
(Typical, n5)
5
~¥-=--Z-0-=-50-n----,~ 500
•
DATA OUT
1.5V
2681 drw 05
20
40
60
60
100 120 140 160 160
200
CAPACITANCE (pF)
2681 drw 06
Figure 4. Alternate Lumped Capacitive load,
Typical Derating
Figure 3. Alternate Output Load
7.20
3
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = O°C to +70°C)
7MP4031BxxZ
_10(2)
_8(2)
Symbol Parameter
Read Cvcle
Min.
Max.
Min.
Max.
-12
Min.
Max.
Unit
tRC
Read Cycle Time
8
-
10
-
12
-
ns
tAA
Address Access Time
8
-
Chip Select Access Time
8
-
10
10
-
12
12
ns
tACS
tCLZ(1)
1
-
1
-
1
-
ns
tOE
tOLZ(1)
Output Enable to Output Valid
-
4
-
5
-
6
ns
1
-
-
1
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
-
6
1
-
tOHZ(1)
Output Disable to Output in High Z
-
3
-
tOH
Output Hold from Address Change
3
-
3
10
Chip Select to Output in Low Z
Output Enable to Output in Low Z
ns
8
ns
3
-
3
ns
-
3
-
ns
12
-
ns
9
-
ns
10
0
-
8
-
7
Write Cycle
twc
Write Cycle Time
8
tcw
Chip Select to End of Write
8
tAW
Address Valid to End of Write
8
tAS
Address Set·up Time
0
twp
Write Pulse Width
8
tWR
tWHZ(1)
Write Recovery Time
0
-
0
Write Enable to Output in High Z
-
3
-
tDW
Data to Write Time Overlap
5
5
tDH
toW(1)
Data Hold from Write Time
0
Output Active from End of Write
3
-
NOTES:
1. This parameter is guaranteed, but not tested.
2. Preliminary specifications only.
8
0
3
12
0
ns
-
ns
9
-
ns
-
0
-
ns
3
-
3
ns
-
6
-
ns
0
-
ns
3
ns
2681 tbll0
7.20
4
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±1 0%, TA = O°C to + 70°C)
7MP4031 BxxZ
7MP4031SxxZ
-20
-15
Parameter
Symbol
Read Cycle
Min.
Max.
Min.
-25
Max.
Min.
-35
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
15
-
20
-
25
-
35
-
ns
tAA
Address Access Time
15
-
25
ns
20
-
25
-
35
Chip Select Access Time
-
20
tACS
tCLZ(1)
-
35
ns
-
5
-
5
-
ns
tOE
tOLZ(1)
Output Enable to Output Valid
-
9
15
-
20
ns
Output Enable to Output in Low Z
5
-
-
5
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
10
ns
Output Disable to Output in High Z
-
15
tOHZ(1)
-
15
ns
tOH
Output Hold from Address Change
3
3
ns
tpu(1)
Chip Select to Power-Up Time
0
-
tPO(1)
Chip Deselect to Power-Down Time
-
15
-
Chip Select to Output in Low Z
5
15
-
7
7
5
5
-
12
-
5
8
-
3
-
3
0
-
0
-
0
-
20
-
25
-
35
ns
-
30
-
ns
25
ns
0
25
-
0
-
ns
8
10
ns
Write Cycle
twc
Write Cycle Time
14
-
17
-
20
tcw
Chip Select to End of Write
14
-
17
-
20
tAW
Address Valid to End of Write
14
-
17
-
20
tAS
Address Set-up Time
0
0
Write Pulse Width
14
17
-
0
twp
-
20
-
tWR
tWHZ(1)
Write Recovery Time
0
-
0
-
0
-
Write Enable to Output in High Z
-
6
-
tow
Data to Write Time Overlap
10
-
10
tOH
Data Hold from Write Time
0
-
0
tow(1)
Output Active from End of Write
5
-
5
NOTE:
1. This parameter is guaranteed, but not tested.
7
-
25
ns
ns
ns
-
7
-
10
ns
13
-
15
ns
0
-
0
5
-
5
-
ns
ns
2681 tbl11
•
7.20
5
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
---
....- - - - - - - - - - tRC ----------~
~CS------~--~
tCLZ (5) -'-------I~
DATAoUT---------------------------------------c
2681 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~~~----------ADDRESS ------
DATAoUT
tRC
------------I~~
t:-----------tO-H------t-AA-------------------.-I----~: ~-t-O-H----~-------------~~~--
DATA VALID
PREVIOUS DATA VALID
2681 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
DATAoUT
~"""'--tCLZ(5)-r-1_-_-_-_t_tCHZ(5)~
___
---j<::><::><:~
~
2681 drw 09
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. DE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.20
6
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
twc
)(
ADDRESS
)(
/
~
tAW
~
"'-
/
twp
tAS
(7)
tWR-
~,
WE
./ ~
-tWHZ(6)tOHZ (6)
(4)
DATAoUT
~
-tOHZ~
tow (6)
l
"'
./
r
tDH
(4)
) -
tDWDATAIN
I'"
DATA VALID
'"
/
2681 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING}(1, 2, 3, 5)
twc
ADDRESS
-
)
K
tAW
I-- tAS
DATAIN
)(
}
/
V
tcw
-----t::E
tWR
tow
"'1DATA VALID
tDH
3~2681 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going High to the end of write cycle.
4. During this period, 1/0 pins are in the output state, input signals must not be applied.
5. If the CS Low transition occurs simultaneously with or after the WE Low transition, the outputs remain in a high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but, not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tow) to allow the 1/0 drivers to turn off data and
to be placed on the bus for the required tow. If OE is high during an WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twp .
7.20
7
II
IDT7MP4031 (16K x 32)
BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
3.640
3.660
I
..
~
I
~~Irl=I~C=I~I=I~C=I~I-.l
p'N1~f
0.015
0.025
TYP.
0.100
TYP.
0.050
TYP.
0.125
0.190
SIDE VIEW
FRONT VIEW
BACK VIEW
2681 drw 12
7.20
8
~®
PRELIMINARY
IDT7MB4065
IDT7MB4066
256K x 20/256K x 16
BiCMOS/CMOS STATIC RAM
MODULES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 256K x 20/256K x 16 SiCMOS/CMOS static
RAM modules
• Low profile 48-pin FR-4 DIP (Dual In-line Package)
• Fast access time: 10ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
• Multiple GND pins for maximum noise immunity
The IDT7MS4065/4066 are high-speed, high density 256K
x 20/256K x 16 SiCMOS/CMOS static RAM modules constructed on an epoxy laminate (FR-4) substrate using either 5
256K x 4 or 4 256K x 4 static RAMs in plastic SOJ packages.
The IDT7MS4065/4066 are available with access time as fast
as 10ns with minimal power consumption.
The IDT7MS4065/4066 are packaged in a 48 pin FR-4 DIP
(Dual In-line Package). The dual row configuration allows 48
pins to be placed on a package 2.4 inches long, 600 mils wide
and 0.35 inches tall.
All inputs and outputs of the IDT7MB4065/4066 are TTL
compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
PIN CONFIGURATIONS(1)
FUNCTIONAL BLOCK DIAGRAM(1)
GND
1/019
1/01 a
1/017
1/016
1/015
1/014
1/013
1/012
1/011
1/010
GND
OE
1/09
I/0a
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
Vee
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vee
A17
A16
A15
A14
A13
ADDRESS
256K X 20
A12
RAM
All
Ala
A9
CSU
CSL
12
GND
1/00-7
WE
Aa
A7
A6
1108-19
2808 drw 02
NOTE:
1. On the 7MB4066, there are 16 1/05 with byte access to I/Os(O-7)and
I/Os(8-15).
A5
A4
A3
A2
PIN NAMES
Al
1100-19
Data Inputs/Outputs
Ao
AO-17
Address
GND
CSL
Chip Select - Lower Byte
2808 drwOl
DIP
TOP VIEW
NOTE:
1. On the 7MB4066, pins 10,11,14, 15 are N.C. (No Connects).
CSU
Chip Select - Upper Byte
WE
Write Enable
OE
Output Enable
NC
No Connect
Vee
Power
GND
Ground
2808 tbl 01
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-708112
101992 Integrated Device Technology. Inc.
7.21
II
IDT7MB4065/4066 (256K x 20/256K x 16)
BiCMOS/CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Comm.
Unit
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
o to +70
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Vee
Supply Voltage·
4.5
5
5.5
V
°C
GND
Supply Voltage
0
0
0
V
V
TA
Operating Temperature
TBIAS
Temperature Under Bias
-10to +B5
°C
VIH
Input High Voltage
2.2
-
6
TSTG
Storage Temperature
-55 to +125
°C
VIL
Input Low Voltage
-0.5 (1)
-
O.B
lOUT
DC Output Current
50
rnA
NOTE:
NOTE:
2808 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V
2808tbl04
1. VIL = -2.0V for pulse width less than 10ns.
RECOMMENDED OPERATING TEMPERA·
TURE AND SUPPLY VOLTAGE
TRUTH TABLE
Mode
Unit
Grade
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
5.0V± 10%
2808tbl05
Output
Power
CS
OE
Standby
H
X
X
Hi-Z
Standby
Read
L
L
H
Dout
Active
Write
L
X
L
Din
Active
Symbol
Parameter(1)
Conditions
Max.
Unit
Read
L
H
H
Hi-Z
Active
CIN(D)
CIN(A)
Input Capacitance
Input Capacitance
(Address and Control)
VIN = OV
VIN = OV
12
42
pF
pF
COUT
Output Capacitance
VOUT = OV
12
WE
CAPACITANCE
(TA = +25°C, F = 1.0MHz)
2808 tbl 03
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V +10%,
TA = O°C to +70°C)
Symbol
IILlI
Test Conditions
Parameter
Input Leakage
(Address and Control)
2808tbl06
= Max.; VIN
IILlI
Input Leakage (Data)
Vee
IILol
Output Leakage
Vee", Max.; CS '" VIH, VOUT '" GND to Vee
= GND to Vee
VOL
Output Low
Vee", Min., IOL", BmA
VOH
Output High
Vee", Min., IOH
Max.
Unit
-
50
~
-
10
~
10
~
0.4
V
2.4
-
V
Min.
Vee", Max.; VIN '" GND to Vee
= -4mA
2808tbl07
7MB4065
10 - 17ns(1)
Symbol
Parameter
Test Conditions
Max.
7MB4066
20 - 45ns
Max.
10 - 17ns(1)
Max.
20 - 45ns
Max.
Unit
lec
Dymanic Operating
Current
f = fMAX(2); CS '" VIL
Vee = Max.; Output Open
1000
750
BOO
600
mA
IS8
Standby Supply
Current
CS ~ VIH, Vee = Max.
Outputs Open, f '" fMAX(2)
300
300
240
240
mA
IS81
Full Standby
Supply Current
CS ~ Vee - 0.2V; F = 0
VIN > Vee - 0.2V or < 0.2V,
f '"
200
50
160
40
mA
a
NOTES:
2808 tbl 08
1. Preliminary specifications only.
2. fMAX = 1/tRC
7.21
2
IDT7MB4065/4066 (256K x 20/256K x 16)
BICMOS/CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figures 1-4
2808 tbl09
+5V
~
+5V
480n
480n
DATAoUT--------,-------~
255n
DATAoUT--------~------~
255n
5 pF*
30 pF*
* includes scope and jig.
2808 drw 04
2808 drw 03
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCL.Z, tWHZ, tow)
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V -+10% , TA = O°C to +70°C)
7MB4065/4066SxxP
-10(2)
Symbol
Parameter
Read Cycle
Min.
Max.
Min.
_17(2)
-15(2)
-12(2)
Max.
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
10
-
12
-
15
-
17
-
ns
tAA
Address Access Time
Chip Select Access Time
10
10
-
12
12
-
15
15
-
17
17
ns
tACS
tCLZ(1)
2
-
2
-
2
-
2
-
ns
tOE
tOLZ(1)
Output Enable to Output Valid
-
4
-
5
-
6
-
8
ns
Output Enable to Output in Low Z
2
-
2
-
2
-
2
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
-
6
7
-
4
4
8
5
-
ns
Output Disable to Output in High
-
10
tOHZ(1)
-
6
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
ns
10
8
8
0
8
0
-
-
-
17
15
15
0
15
0
-
ns
-
15
12
12
0
12
0
-
ns
-
ns
6
-
7
ns
10
0
2
-
ns
Chip Select to Output in Low
Z
Z
ns
Write Cycle
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
tWHZ(1)
Write Enable to Output in High
tDW
Data to Write Time Overlap
tDH
tow(1)
Data Hold from Write Time
Z
Output Active from End of Write
-
12
10
10
0
10
0
-
4
-
5
-
5
0
2
-
6
-
0
2
-
8
0
2
-
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
-
-
-
ns
ns
ns
ns
ns
2808tbl10
7.21
3
IDT7MB4065/4066 (256K x 20/256K x 16)
BICMOS/CMOS STATIC RAM MODULES
DATAoUT
COMMERCIAL TEMPERATURE RANGE
.1:'f------::L-r'l
Zo= 500.
ilTAA
(Typical, ns) 5
4
500.
1.5V
280e drw 05
20
40
60
Figure 3. Alternate Output Load
80
100 120 140
160 180
200
CAPACITANCE (pF)
2808 drw06
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ± 10%, TA
Symbol
= O°C to +70°C)
-20
Min. Max.
Parameters
Read Cycle
tRC
Read Cycle Time
-25
Min.
Max.
7MB4065/4066SxxP
-30
-35
Min. Max. Min. Max.
-45
Min. Max.
Unit
20
-
25
-
30
-
35
-
45
-
ns
20
ns
35
-
45
30
-
35
25
-
30
20
-
25
Chip Select Access Time
-
45
ns
tCLZ(1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
-
18
-
23
ns
-
ns
-
20
ns
10
ns
ns
tAA
Address Access Time
tACS
tOE
Output Enable to Output Valid
-
10
-
12
-
15
tOLZ(1)
Output Enable to Output in Low Z
0
-
0
-
0
-
tCHZ(1)
Chip Deselect to Output in High Z
-
10
12
Output Disable to Output in High Z
-
10
-
15
tOHZ(1)
-
tOH
Output Hold from Address Change
3
3
Chip Select to Power Up Time
0
0
-
3
tPU(1)
-
tpo(1)
Chip Deselect to Power Down Time
-
20
-
25
25
10
0
-
0
-
18
5
0
-
5
0
-
0
-
-
30
-
35
-
45
ns
30
35
-
45
-
ns
40
-
40
-
ns
0
35
-
ns
10
10
ns
Write Cycle
tAS
Address Set-up Time
0
twp
Write Pulse Width
15
tWR
Write Recovery Time
0
-
0
-
0
-
0
-
0
-
ns
tWHZ(1)
Write Enable to Output in High Z
-
13
-
15
-
18
-
20
-
23
ns
tDW
Data to Write Time Overlap
12
-
15
17
-
ns
0
-
0
0
-
ns
Output Active from End of Write
0
-
0
-
25
Data Hold from Write Time
-
20
tDH
tow (1)
-
0
-
twc
Write Cycle Time
20
tcw
Chip Selection to End of Write
15
tAW
Address Valid to End of Write
15
20
20
0
20
NOTE:
25
25
0
25
0
0
30
30
0
30
0
0
ns
ns
ns
2808 tblll
1. This parameter is guaranteed by design but not tested.
7.21
4
IDT7MS4065/4066 (256K x 20/256K x 16)
SiCMOS/CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.1
(1)
ADDRESS
DATAoUT
2808 drw 07
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
ADDRESS
DATAoUT
---~~
2-tOH
tRC
f-tOH
1M
PREVIOUS DATA VALID
DATA VALID
2808 drw 08
TIMING WAVEFORM OF READ CYCLE NO.2 (1,3,4)
DATAoUT
2808 drw 09
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to CS transition low.
4.0E = VIL.
5. Transition is measured ±200 mV from steady state. This parameter is guaranteed by design, but not tested.
7.21
5
\
ID17MB4065/4066 (256K x 20/256K x 16)
BICMOS/CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2,3,7)
twc
~
) "-
K
)
ADDRESS
/
t'
tAW
~
K
7
twp
~tAS
tWR _
(7)
~~
~
tOHZ
DATAoUT
(4)
tWHZ
~
~
/
(6) ___
tOHZ
tow
(6)
"
(6)
(6)
./
Lrr
tDH
(4)
) -
tDW_
".
DATAIN
"
DATA VALID
./
2808 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2, 3, 5)
twc
ADDRESS
-
)
K
CS
~tAs
DATAIN
)K
tAW
'}
/
~
tcw
--------t::(
tWR
tDW
"I-
tDH
DATA VALID
2808 drw 11
NOTES:
1. WE or CS must High during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twp is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, so input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, outputs remain in a high impedance state.
6. Transition is measured ±200 mV from steady state. This parameter is guaranteed by design, but not tested.
7.lf OE is low during a WE controlled write cycle, the wirte pulse width must be the larger of twp or (twHZ + tow) to allow the I/O
drivers to turn off and data to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle, this
requirement does not apply and the write pulse can be as short as the specified twP.
7.21
6
IDT7MB4065/4066 (256K x 20/256K x 16)
BiCMOS/CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MB4065
I
2.390
....
"""2:41"0
..
I
II:::::n::::::lr:::::rl} [];f1t
TOP VIEW
1
!
PiN1
I
,n" ~,~""=;----' ~~O
h",","
~ ~ I~
0.025 ~
- I I -
~ ~
0100
TYP.
~
0.013
END VIEW
0.035,.
0.065
0.125
0.175
SiDE ViEW
Ir::::::[:::::]::::::rl
BOTTOM ViEW
2080 drw 12
7MB4066
I
2.390
"""2:410
~
.-
I
Ir::::r:::::::]=rl}~
[-;r
t
tinn n,n 'fln, hn n"~ ~~O
TOP VIEW
1
1
PIN 1
I,
~~I~
0.025
~
- II
-0100
~ ~
TYP.
IIIIII~
~ ~ 0.065
0.007
0.013
END VIEW
.0.125
0.175
SIDE VIEW
II:::::]::::::]::::::rl
BOTTOM ViEW
7.21
2080 drw 13
7
(;)®
512K1256K x 16
CMOS STATIC RAM MODULE
IDT7MP4047
IDT7MP4046
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed 8/4 megabit (pin compatible) CMOS static
RAM modules
• Fast access time: 70ns (max.)
• Low power consumption
- Active: 220mA max.
- CMOS Standby: 850llA max.
- Data retention: 450llA max. (Vcc= 2V)
• Surface mounted small outline plastic packages on a 45
pin FR-4 SIP (Single In-line Package)
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
The IDT7MP4047/4046 is a 512K!256K x 16 CMOS static
RAM module constructed on a multilayer epoxy laminate (FR4) substrate using eight or four 128K x 8 static RAMs in small
outline plastic packages and a one-of-fou r decoder. Availability of two Write Enables and two Output Enables provides byte
access and output control flexibility. The IDT7MP4047/4046
is available with access times as fast as 70l1s with a maximum
operating current of 220mA. For battery backup applications,
a very low data retention current is available.
The IDT7MP4047/4046 is packaged in a 45 pin FR-4 SIP
(Single In-line Package). This results is a package 4.6 inches
in length and less than 0.2 inches in thickness.
All inputs and outputs of the IDT7MP4047/4046 are TTL
compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
FUNCTIONAL BLOCK DIAGRAM
19
512K!256K x 16
RAM
1/00-7
1/08-15
2754 drw 01
CEMOS is a trademarK of Integrated Device Technology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC·705711
©1992 Integrated Device Technology, Inc.
7.22
IDT7MP4047/4046 (512K!256K x 16)
CMOS STATIC RAM MODULE
PIN CONFIGURATION GND
Vce
WEl
OEl
1/015
1/014
1/013
1/012
1/011
1/010
1/09
I/0a
Ala
A17
A1S
A15
A14
A13
A12
All
Ala
CS
GND
A9
Aa
A7
As
A5
A4
A3
A2
Al
Ao
1/07
I/0s
1/05
1/04
1/03
1/02
1/01
1/00
OEo
WEo
Vee
GND
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION(1) -
7MP4047
GND
Vee
WE1
OE1
1/015
1/014
1/013
1/012
1/011
1/010
1/09
I/0a
Ao
Al
A2
A3
A4
A5
As
A7
A17
10
11
12
13
14
10
11
12
13
14
15
lS
17
18
19
OS
SIP
FRONT VIEW
2754 drw 02
GND
A17
A1S
A15
Al1
A13
A12
A11
AlO
A9
Aa
1/07
I/0s
1/05
1/04
1/03
1/02
1101
1/00
OED
WED
Vee
GND
2754 drw 03
NOTE:
1. For proper operation of the 7MP4046 module, pins 21 and 24 must be tied
together.
PIN NAMES - 7MP4046
PIN NAMES - 7MP4047
1/00-1/015
Ao-Ala
CS
WEn-l
OEn-l
Vee
GND
7MP4046
1/00-1/015
Ao-A17
CS
WEn-l
OEn-l
Vee
GND
Data InputslOutputs
Addresses
Chip Select
Write Enables
Output Enables
Power
Ground
2754 tbl 03
7.22
Data Inputs/Outputs
Addresses
Chip Select
Write Enables
Output Enables
Power
Ground
2754 tbl 04
2
IDT7MP4047/4046 (512K1256K x 16)
CMOS STATlC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Terminal Voltage with
Respect to GND
RECOMMENDED DC OPERATING
CONDITIONS
Unit
-0.5 to +7.0
Symbol
V
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
0
0
0
V
-
6
V
TA
Operating Temperature
o to +70
°C
GND
Supply Voltage
TBIAS
Temperature Under Bias
-10to+85
°C
VIH
Input High Voltage
2.2
TSTG
Storage Temperature
-55to +125
°C
VIL
Input Low Voltage
-0.5(1)
lOUT
DC Output Current
50
rnA
NOTE:
2754 Ibl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
27541bl07
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
TRUTH TABLE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V
± 10%
27541bl08
CS
WE
Standby
H
X
High Z
Standby
Read
L
H
DATAoUT
Active
Write
L
L
High Z
Active
Mode
0.8
Output
Power
2754 Ibl 06
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ± 10%, TA = O°C to +70°C)
7MP4046 7MP4047
Parameter
Max.
Max.
Unit
-
4
8
M
4
8
~
Vee = Min., IOL = 2mA
-
0.4
0.4
V
Vee = Min., IOH = -1 rnA
2.4
-
-
V
Dynamic Operating Current
Vee = Max., CS = VIL,
f = fMAX, Output Open
-
220
220
rnA
ISB
Standby Supply Current
(TTL Levels)
CS;::: VIH, Vee = Max.,
f = fMAX, Ouput Open
-
12
24
rnA
ISB1
Full Standby Supply Current
(CMOS Levels)
CS;::: VHe, VIN ;::: VHe or::; VLe
Vee = Max., Output Open
-
450
850
llA
Symbol
Test Conditions
IILlI
Input Leakage
Vee = Max., VIN = GND to Vee
IILol
Output Leakage
Vee = Max.
CS = VIH, VOUT = GND to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Min.
27541bl 09
DATA RETENTION CHARACTERISTICS
(TA = O°C to +70°C)
Symbol
Parameter
VOR
Vee for Data Retention
leeOR
Data Retention Current
Test Condition
Min.
7MP4046/4047
Max.@2.0V
-
2.0
-
CS;::: Vee - 0.2V
0
tRe(1)
teoR(2)
Chip Deselect to Data Retention Time
VIN ::; Vee - 0.2V
tR(2)
Operation Recovery Time
VIN;::: - 0.2V
NOTES:
1. tRe = Read Cycle Time.
2. This parameter is guaranteed by design, but not tested.
250/450
-
Unit
V
~
ns
ns
27541bll0
7.22
3
IDTIMP4047/4046 (512K!256K x 16)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 and 2
Output Load
2754 tbl 11
+5V
+5V
480n
480n
DATAoUT-...--...
255n
DATAoUT-...--...
30pF"
255n
2754 drw 05
2754 drw 04
Figure 1. Output Load
Figure 2•. Output Load
(for tClZ, tOlZ, tCHZ, tOHZ, .tow, and tWHZ)
"Including scope and jig
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = O°C to +70°C)
7MP4046/4047LxxS
-85
-70
Symbol
Parameters
Min.
Max.
Min.
-100
Max.
Min.
-120
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
70
-
85
-
100
-
120
-
ns
tAA
Address Access Time
-
70
85
ns
-
70
tOE
Output Enable to Output Valid
-
45
48
33
-
35
-
120
Chip Select Access Time
-
100
tACS
-
0
-
0
5
tOHZ(1)
Output Disable to Output in High Z
tOLZ(1)
Output Enable to Output in Low Z
0
tCLZ(1)
Chip Select to Output in Low Z
5
tCHZ(1)
Chip Deselect to Output in High Z
tOH
Output Hold from Address Change
30
85
100
50
120
ns
60
ns
40
ns
-
ns
-
5
-
-
5
-
40
-
43
-
45
-
50
ns
10
-
10
-
10
-
10
-
ns
85
-
100
120
-:
82
-
5
90
-
100
-
ns
65
-,
-
100
-
ns
45
-
ns
0
-
ns
0
-
ns
0
ns
WRITE CYCLE
twc
Write Cycle Time
70
twp
Write Pulse Width
55
tAS
Address Set-up Time
0
tAW
Address Valid to End of Write
65
-
tcw
Chip Selection to End of Write
65
-
80
-
85
tDS
Data Set-up Time
35
-
38
-
40
tDH
Data Hold Time
0
0
Write Recoverv Time
0
0
-
0
tWR
-
tWHZ(1)
Write Enable to Ouput in High Z
-
30
-
33
-
35
-
40
ns
toW(1)
Output Active from End of Write
0
-
0
-
0
-
0
-
ns
NOTE:
1. This parameter is guaranteed by design, but not tested.
2
75
0
90
5
ns
ns
ns
2754 tbl12
7.22
4
II
IDnMP4047/4046 (512K!256K x 16)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE(1) - 7MP4047
CAPACITANCE(1) - 7MP4046
(TA= +25°C f = 1 OMHz)
Symbol
TA = +25°C, f = 1.0MHz)
Parameter
Conditions
Typ.
Unit
Symbol
Parameter
Conditions
Typ.
Unit
GiN
Input Capacitance
VIN = OV
35
pF
CIN
Input Capacitance
VIN = OV
30
pF
GiN(C)
Input Capacitance(CS)
VIN = OV
8
pF
CIN(C)
Input Capacitance(CS)
VIN = OV
8
pF
COUT
Output Capacitance
VOUT = OV
35
pF
COUT
Output Capacitance
VOUT= OV
20
NOTE:
1. This parameter is guaranteed by design, but not tested.
NOTE:
1. This parameter is guaranteed by design, but not tested.
2754 tbl 01
pF
2754 tbl 02
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
------------t
ADDRESS
tOE
tOlZ
(5)
t------t
tACS
~----
tClZ
(5)
---~
DATAoUT
2754 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
~~~~~mc~~~~~~~~
t~____
__
DATAoUT _-----J
~x~'_x~>k======='==LDA=T=A=VA=:=:=~===:==
t_OH_ _t_AA""'""""_>k-l-.
2754 drw08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
~'"'-- _
L
DATAoUT
tw"'-L:
r
_
1~
~x~
L
teHz'"
~"--------_
~
2754 drw 09
NOTES:
1. WE is high for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. DE = Vil.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed, but not tested.
7.22
5
IDT7MP4047/4046 (512K1256K x 16)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VOR~
2V
VOR
2754 drw 06
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3,7)
twe------------------~~
twp(7) __________~__
tOHZ(6)
tow (6)
(4)
tow __--"_.!.!:tD:.!.!H~
DATA VALID
DATAIN
2754 dew 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3,5)
twe------------------~~
II
ADDRESS
tAW - - - - - - - - - - - - - - - - -
tew
DATAIN
------------.l---~~
---------«f
tow
'1
DATA VALID
toH
tWR
3)1----------2754 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CSand a low WE.
3. twR is measured from the earlier of CS or WE going High to the end of write cycle.
4. During this period, 1/0 pins are in the output state and inputs signals must not be applied.
5. If the CS Low transition occurs simultaneously with or after the WE Low transitions, the outputs remain in a high impedance state.
6. Transition is measured ±200m V fi om steady state with a 5pF load (including scope and jig).. This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required two. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specilied twP.
7.22
6
IDT7MP4047/4046 (512K1256K x 16)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MP4046
t4-r-----
4490
4.510--------..
0.0"
"7i:065
PIN 1
'---
-1dl1
1_
0.140
MAX
__
J ---1\-- om,
FRONT VIEW
BACK VIEW
7MP4047
14-1"- - - -
2754 drw 12
4.490
4.510--------..
1
-1
r-t~
~
4-0:0r3
0007
T
0.040
M60
PIN 1
-.J
FRONT VIEW
I~ I
V
~ HH \
II
~~ .
,"", ", f,,,, ""1"" "", "" """ n
BACK VIEW
7.22
2754 drw 13
7
t;)
64K x 16
BiCMOS/CMOS STATIC RAM
MODULE
IDT7MP4027
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 1 megabit static RAM module
• Low profile 40 pin DSIP (Dual Single In-line vertical Package)
• Ultra fast access time: 10ns (max.)
• Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
• Single SV (±10%) power supply
• Inputs/outputs directly TIL compatible
• Multiple GND pins for maximum noise immunity
The IDT7MP4027 is a 64K x 16 static RAM module constructed on an epoxy laminate (FR-4) substrate using 464K
x 4 static RAMs in plastic SOJ packages. The IDT7MP4027
is available with access time as fast as 10ns with minimal
power consumption.
The IDT7MP4027 is packaged in a 40 pin DSIP (Dual
Single In-line vertical Package). This configuration allows 40
pins to be placed on a package 2 inches long, 0.3S inches thick
and O.S inches tall.
All inputs and outputs of the IDT7MP4027 are TIL compatible and operate from a single SV supply. Full asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Vcc
1/00
1/01
1/02
1/03
A2
1/015
1/014
1/013
1/012
GND
A13
Ao
A1
A3
A12
A4
A11
As
As
A10
AO-15
CS
WE
OE
64K X 16
RAM
16
1/00-15
2843 drw 02
A9
Aa
A7
1/04
1/05
II0s
1/07
CS
GND
1/011
1/010
1/09
I/0a
WE
OE
A15
NC
A14
NC
II
PIN NAMES
2843 drw 01
DSIP
TOP VIEW
AO-15
Addresses
1/00-15
Data InputslOutputs
CS
Chip Select
WE
OE
Write Enable
Output Enable
NC
No Connect
Vee
Power
GND
Ground
2843 tbl 01
BiCEMOS and CEMOS are trademarks of Integrated Device Technology, Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-lOll!l
©1992 Integrated Device Technology, Inc.
7.23
IDT7MP4027
64Kx 16 BlCMOS/CMOS STATIC RAM MODULE
CAPACITANCE
(TA
TRUTH TABLE
= +25°C, F = 1.0MHZ)
Parameter(1)
Symbol
COMMERCIAL TEMPERATURE RANGE
Conditions
Max.
Unit
CliO
Data 1/0 Capacitance
V(IN) = OV
15
pF
CIN
Input Capacitance
(Address and Control)
V(IN) = OV
40
pF
NOTE:
Mode
2843 tbl 02
1. This parameter is guaranteed by design but not tested.
CS
Standby
H
OE WE
Output
Power
X
X
High Z
Standby
Read
L
L
H
DATAoUT
Active
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
2843 tbl 05
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
6.0
V
O.S
V
Symbol
Parameter
VIH
Input HiQh Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
-
NOT~
1.
VIL
VTERM
~3~ro
(min)
=
GND
Commercial
O°C to +70°C
OV
Unit
V
TA
Operating Temperature
o to +70
°C
T81AS
Temperature Under Bias
-10 to +S5
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
rnA
2843 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Value
-0.5 to +7.0
NOTE:
-1.SV for pulse width less than 10ns.
Grade
Rating
Terminal Voltage with
Respect to GND
Vee
5.0V
± 10%
2843 tbl04
DC ELECTRICAL CHARACTERISTICS
(Vec = 5.0V +10%,
TA = O°C to +70°C)
Symbol
Max.
Unit
Input Leakage
Vee = Max.; VIN = GND to Vee
(Address and Control)
-
40
flA
IILlI
Input Leakage (Data)
Vee
10
Output Leakage
Vee
-
10
flA
flA
VOL
Output Low
-
0.4
V
VOH
Output High
= Max.; VIN = GND to Vee
= Max.; CS = VIH, VOUT = GND to Vee
Vee = Min., IOL = SmA
Vee = Min., IOH = -4rnA
-
IILOI
2.4
-
V
IILlI
Parameter
Test Conditions
Min.
2843 tbl 07
Symbol
Parameter
Test Conditions
7MP40278
Max.
7MP4027S
Max.
Unit
720
640
rnA
lee
Dyrnanic Operating
Current
f = fMAX; CS = VIL
Vee = Max.; Output Open
IS8
Standby Supply
Current
CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX
-
160
rnA
IS81
Full Standby
Supply Current
CS ~ Vee - 0.2V; f = 0
VIN > Vee - 0.2V or < 0.2V
-
120
rnA
2843 tbl 08
7.23
2
IDT7MP4027
64K x 16 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
Output Load
See Figures 1-4
2843 tbl09
+5V
480n
480n
DATAoUT
DATAoUT------------.---------~
255n
5 pF*
2843 drw03
2843 drw 04
Figure 2. Output Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Figure 1. Output Load.
DATA OUT-l'f---Z-O-=-5-0-n----r'~ 50n
t.TAA
(Typical. ns)
5
1.5V
2843 drw 05
20
40
60
80
100 120 140
160 180
200
CAPACITANCE (pF)
2843 drw 06
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating.
Figure 3. Alternate Output Load.
7.23
3
IDTIMP4027
64K x 16 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ±1 0%, TA = O°C to + 70°C)
7MP4027BxxV
-12(2)
-15
-10(2)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
-17
Max.
Min.
Max.
Unit
Read Cycle
tAC
Read Cycle Time
10
-
12
-
15
-
17
-
ns
tM
Address Access Time
-
10
-
12
15
ns
Chip Select Access Time
-
4
-
5
-
17
tACS
-
8
ns
tCLZ(1)
Chip Select to Output in Low Z
2
-
2
-
2
-
ns
tOE
Output Enable to Output Valid
-
4
-
8
ns
tOLZ(1)
Output Enable to Output in Low Z
2
-
2
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
6
8
-
10
ns
tOHZ(1j
Output Disable to Output in High Z
-
5
-
6
ns
tOH
Output Hold from Address Change
2
5
-
2
2
6
-
7
3
-
5
-
5
-
5
-
12
-
15
9
-
10
4
-
6
5
-
ns
-
17
10
12
10
-
12
-
ns
-
0
-
Write Cycle
twe
Write Cycle Time
10
tcw
Chip Select to End of Write
7
tAW
Address Valid to End of Write
8
-
tAS
Address Set-up Time
0
-
0
twp
Write Pulse Width
8
9
tWR
Write Recovery Time
0
-
tWHZ(1)
Write Enable to Output in High Z
-
4
-
tDW
Data to Write Time Overlap
4
-
6
Data Hold from Write Time
0
0
Output Active from End of Write
2
-
0
tDW(1)
-
5
tDH
NOTES:
1. This parameter is guaranteed by deSign, but not tested.
2. Preliminary specifications only.
8
9
0
2
5
0
-
2
6
-
0
ns
ns
ns
ns
0
-
ns
-
7
ns
8
-
0
2
ns
ns
ns
2843tbl10
7.23
4
IDTIMP4027
64K x 16 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V +1
- 0% TA = O°C to +70°C)
7MP4027SxxV
·20
Symbol
Parameter
Read Cycle
Min.
·25
Max.
Min.
·30
Max.
Min.
·35
Max.
Min.
Max.
Unit
tAC
Read Cycle Time
20
-
'25
-
30
-
35
-
ns
tAA
Address Access Time
Chip Select Access Time
20
20
-
25
25
-
30
30
-
35
35
ns
tACS
tCLZ(1)
-
Chip Select to Output in Low Z
4
-
4
-
4
-
4
-
ns
tOE
Output Enable to Output Valid
12
-
12
-
15
-
tOLZ(1)
Output Enable to Output in Low Z
0
-
0
-
0
-
0
tCHZ(1)
Chip Deselect to Output in High Z
Output Disable to Output in High
-
10
10
-
tOHZ(1)
tOH
tPU(1)
Output Hold from Address Change
-
Chip Select to Power-Up Time
3
0
tpo(1)
Chip Deselect to Power-Down Time
-
Z
20
ns
3
0
15
15
-
20
20
-
20
20
20
-
3
0
-
3
0
-
ns
-
25
-
30
-
35
ns
25
20
20
0
20
0
-
30
25
25
0
25
0
-
35
30
30
0
30
0
-
ns
-
ns
-
ns
-
ns
-
20
ns
20
0
0
-
ns
ns
ns
ns
ns
ns
Write Cycle
-
twp
Write Pulse Width
20
15
15
0
15
tWR
tWHZ(1)
Write Recovery Time
a
-
-
10
-
15
-
20
tow
Data to Write Time Overlap
12
0
0
-
15
0
0
-
17
0
0
-
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
Write Enable to Output in High
Z
tOH
Data Hold from Write Time
tow(1)
Output Active from End of Write
-
NOTE:
1. This parameter is guaranteed by design, but not tested.
ns
ns
-
ns
-
ns
2843 tbltt
,.
7.23
5
IDT7MP4027
64K x 16 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~-------------------tRC
ADDRESS
DATAoUT
-------------------------------------<
2843 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~--------------------tRC
ADDRESS
tAA
.....- - - - - - - tOH -----~
DATAoUT
PREVIOUS DATA VALID
2843 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
cs-{
~
DATAoUT
tCLZ (5'
~
lOOOK
lACS
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE = ViL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.23
t
tCHZ (5,
==j
~
2843 drw 09
6
IDT7MP4027
64K x 16 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3,7)
twc------------------~~
ADDRESS
tWR(3)
~----------tcw ----------~
tAW
14------ twp(2) -------~~
DATAoUT
DATAIN
2843 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3,5)
twc-----------------~~
ADDRESS
~-----------tcw ------~
twp(2) ----------~
tWHZ(4,9)
---+----------
14----
•
tow (9)
DATAoUT
tDHj(~
DATAIN
2843 drw 11
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period,110 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200m V from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, write pulse ((twp) > twHZ + tow) to allow the 1/0 drivers to turn off and data to be placed on the bus for the required
tow. If DE" is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.
7.23
7
IDT7MP4027
64K x 16 BICMOSfCMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
L.-2.000
I--=------ 2.0 15
~I
0.350
_I
L
~~oo1f
TYP.~
_ I _ 0.007
~0.013
SIDE VIEW
2843 drw 12
7.23
8
t;)®
IDT7MB4040
256K x 9
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High density separate 110, 2 megabit (256K x 9) static
RAM module
• Low profile 44 pin, 600 mil DIP
• Fast access time: 10ns (max.)
• Surface mounted plastic SOJ packages on a multilayer
epoxy laminate (FR-4) substrate
• Multiple ground pins for maximum noise immunity
• Inputs/outputs directly TTL compatible
The IDT7MB4040 is a separate 110, 9 bit wide 2 megabit
static RAM module constructed on a multilayer epoxy
laminate (FR-4) substrate using 9 256K x 1 static RAMs in
plastic SOJ packages. The IDT7MB4040 is available with
access times as fast as 1Ons with minimal power consumption.
The IDT7MB4040 is packaged in a 44 pin FR-4 DIP. The
memory configuration results in a package 3.4 inches long,
600 mils wide, and only 350 mils in height. Provision of a ninth
bit results in a optimal package for high reliability applications
where parity is a must.
All inputs and outputs of the IDT7MB4040 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refreshing for
operation and provides equal access and cycle times for ease
of use.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
9
18
CS
Vee
AD
Au
A16
A15
A14
A13
Al
A2
A3
A4
A5
A6
A7
01
ADDRESS
GNO
256K x 9
RAM
GNO
A12
All
AlO
000
001
002
003
GNO
004
005
006
007
As
WE
A9
010
011
012
013
014
015
016
017
9
DO
2700 drw 01
Dis
~Os
WE
GNO
CS
Vee
2700 drw 02
DIP
TOP VIEW
COMMERCIAL TEMPERATURE RANGE
APRIL 1992
"'1992 Integrated Device Technology, Inc.
DSC·7048/3
7.24
IDTIMB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PIN NAMES
CAPACITANCE
(TA = +25°C,
Parameter(1)
f = 1.0MHz)
Olo-OIB
Data Inputs
Symbol
Typ.
Unit
DOD-DOs
Data Outputs
CIN(D)
VIN
= OV
15
pF
Ao-A17
Addresses
Input Capacitance
(Data)
CS
Chip Select
CIN(A)
VIN
= OV
75
pF
WE
Write Enable
Input Capacitance
(Address and Control)
Vee
Power
COUT
Output Capacitance
VOUT';' OV
15
pF
NOTE:
1. This parameter is guaranteed by design, but not tested.
Ground
GNO
Conditions
2700 tbl 04
2700 tbl 01
RECOMMENDED DC OPERATING
CONDITIONS
TRUTH TABLE
Parameter
Mode
CS
WE
Output
Power
Symbol
Min.
Typ.
Max.
Unit
Standby
H
X
High-Z
Standby
Vee
Supply Voltage
4.5
5.0
5.5
V
Read
L
H
DATAoUT
Active
GND
Supply Voltage
0
0
0
V
Write
L
L
High-Z
Active
VIH
Input High Voltage
2.2
-
5.8
V
VIL
Input Low Voltage
-0.5{1)
-
0.8
2700tbl02
ABSOLUTE MAXIMUM RATINGS(1)
Rating
Commercial
Unit
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
°C
TBIAS
Temperature
Under Bias
-10 to +85
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output
Current
50
rnA
Symbol
V
NOTE:
1. VIL = -2.0V for pulse width less than 15ns.
2700 tbl 05
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V
± 10%
2700 tbl 06
NOTE:
2700 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those. indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7.24
2
ID17MB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
Vee = S.OV ± 10%, TA = O°C to +70°C)
Symbol
Parameter
Test Conditions
Input Leakage
(Address and Control)'
Ilul
Max.
Unit
Vee = Max., VIN = GND to Vee
Min.
-
45
J.lA
-
10
10
J.lA
J.lA
-
0.4
V
2.4
-
V
Ilul
Input Leakage (Data)
Vee = Max., VIN
IILol
Output Leakage
Vee = Max.
CS = VIH, VOUT = GND to Vee
= GND to Vee
= 8mA
VOL
Output Low Voltage
Vee = Min.,loL
VOH
Output High Voltage
Vee = Min., IOH = -4mA
2700 tbl 07
Parameter
Test Conditions
10ns,12ns
15-35ns
Max.
Max.
Unit
Icc
Dynamic Operating Current
Vee = Max., CS S; VIL
Outputs Open, f = fMAX.
1710
1350
rnA
ISB
Standby Supply CUrrent
CS ~ VIH, Vee = Max.,
Outputs Open, f = fMAX.
630
360
rnA
ISB1
Full Standby Supply Current
CS ~ Vee - 0.2V, f=O
VIN c Vee - 0.2V or S; 0.2V
270
270
rnA
Symbol
NOTE:
1. 10ns, 12ns are preliminary specifications.
2700 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1 & 2
Output Load
2700tbl09
II
+5V
480n
480n
DATAoUT--------,-------~
DATAoUT--------,-------~
255n
255n
30pF*
5 pF*
2700 drw 04
2700 drw 03
Figure 1. Output Load
Figure 2. Output Load
(for tClZ, tCHZ, tWHZ, tow)
"Including scope and jig
7.24
3
IDT7MB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(2) (Vee = S.OV +
- 10%, TA = oo'C to +70°C)
Symbol
Parameters
-10
Min. Max.
I
7MB4040SxxP
-12
-15
Min. Max. Min.
Max.
-17
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
10
-
12
-
15
tAA
Address Access Time
-
tACS
Chip Select Access Time
-
10
10
-
-
tCLZ(1)
Chip Select to Output in Low Z
3
-
3
tCHZ(1)
Chip Deselect to Output in High Z
-
10
-
12
12
10
tOH
tpu(1)
Output Hold from Address Change
3
-
3
0
0
tPO(1)
Chip Deselect to Power Down Time
-
10
-
3
0
-
3
Chip Select to Power Up Time
-
12
-
-
15
12
12
0
12
0
7
-
3
-
-
ns
17
17
10
ns
-
ns
0
15
-
17
ns
-
-
17
15
15
0
15
0
8
-
15
15
10
17
-
3
-
ns
ns
ns
ns
Write Cycle
twp
Write Pulse Width
8
-
tWR
Write Recovery Time
0
-
12
10
10
0
10
0
tWHZ(1)
Write Enable to Ouput in High Z
-
6
-
tow
Data to Write Time Overlap
8
tOH
Data Hold from Write Time
tow(1)
Output Active from End of Write
0
0
twc
Write Cycle Time
10
tcw
Chip Selection to End of Write
8
tAW
Address Valid to End of Write
8
tAS
Address Set-up Time
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. 10ns, 12ns are preliminary specifications.
-
9
0
0
-
10
0
0
-
-
-
11
0
0
-
ns
-
ns
-
ns
-
ns
9
-
ns
ns
ns
ns
ns
ns
2700 tbll0
7.24
4
IDT7MB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee
= 5.0V ± 10%, TA = O°C to + 70°C)
-20
Symbol
Parameters
Min.
Max.
7MB4040SxxP
-25
Min.
Max.
-35
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
20
-
25
-
35
-
ns
tAA
Address Access Time
Chip Select Access Time
20
20
-
25
25
-
35
35
ns
tACS
tCLZ(1}
-
Chip Select to Output in Low Z
3
-
5
-
5
-
ns
tCHZ(1}
Chip Deselect to Output in High Z
-
10
-
13
-
20
ns
tOH
tpu(1}
Output Hold from Address Change
-
3
0
-
3
0
-
ns
Chip Select to Power Up Time
3
0
tPO(1}
Chip Deselect to Power Down Time
-
20
-
25
-
35
ns
twc
Write Cycle Time
Chip Selection to End of Write
20
17
tAW
Address Valid to End of Write
17
-
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
0
17
0
-
25
22
22
0
22
3
-
35
30
30
0
30
3
-
ns
tcw
tWHZ(1}
Write Enable to Ouput in High Z
-
10
-
13
-
20
ns
tow
Data to Write Time Overlap
Data Hold from Write Time
13
0
0
-
15
0
5
-
20
0
5
-
ns
tOH
toW(1}
ns
ns
Write Cycle
Output Active from End of Write
-
ns
ns
ns
ns
ns
ns
ns
2700 tbl11
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2)
ADDRESS
~~~~~~~~
---, t
DATAoUT
PREVIOUS DATA VALID
tR_C_(5_}~~~_-~~~~_-~~~_-~~~~~~
_____________________________
1
roH - - - ;
J(XX>I<===========D=A=T=A=V=A=LI=D=========
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
~
_______
2700 drw 05
_ _ _ _ _ _ _ _ tRC (5) _ _ _ _ _ _ _...-1
DATAoUT
VccSUPPLY
CURRENT
Icc - - - - - - IS8------+--'
2700 drw 06
NOTES:
1. WE is high for Read Cycle.
2. es is low for Read Cycle.
3. Address valid prior to or coincident with es transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading on Figure 2. This parameter is guaranteed by design, but not tested.
5. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
7.24
5
•
ID17MB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1, 2, 3,7)
~----------------------- twe --------------------~~
ADDRESS
twp (7) __________. - j...._
WE
DATAoUT
(4)
tow
- - . - j....-----1~
tDH
DATAIN
2700 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1, 2, 3, 5)
twe
ADDRESS
-
)(
)(
tAW
CS
__ tAS
~
/ ~
tWR.
tew
DATAIN----------------------------------~~
tDW
.,1..DATA VALID
tDH
3~2700 drw 08
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going High to the end of write cycle.
4. During this period, 1/0 pins are in the output state, input signals must not be applied.
5. If the CS Low transition occurs simultaneously with or after the WE Low transition, the outputs remain in a high impedance state.
6. Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig). This parameter is guaranteed by design, but, not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the 1/0 drivers to turn off data and
to be placed on the bus for the required tow. If OE is high during an WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twp .
7.24
6
IDT7MB4040
(256K x 9) CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
"I
~ -----------~
r-
3.410
{ f~
~ 0.610
L~
0.013
TOP VIEW
0.370
SIDE VIEW
MAX
0.035
'0:'070'
0.015
Q.025
0.100
TYP.
BOTTOM VIEW
0.120
'Q.1Ts'"
2700 drw 09
,.
7.24
7
(;)®
PRELIMINARY
IDT7MB4084
2Mx8
CMOS STATIC RAM
MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
High density 16 megabit (2M x 8) static RAM module
Equivalent to the JEDEC standard for future monolithic
Fast access time: 55ns (max.)
Low power consumption
- Active: 110mA (max.)
- CMOS Standby: 450~A (max.)
- Data Retention: 250~A (max.) Vee = 2V
• Surface mounted plastic packages on a 36-pin, 600 mil
FR-4 DIP (Dual-In-Line Package) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
The IDT7MB4084 is a 16megabit (2M x 8) static RAM
module constructed on a co-fired ceramic or multilayer epoxy
laminate (FR-4) substrate using four 512K x 8 static RAMs
and a decoder. The IDT7MB4084 is available with access
times as fast as 55ns, and a data retention current of 250JlA
and a standby current of 450~A.
The IDT7MB4084 is packaged in a 36-pin FR-4 DIP
resulting in the same JEDEC footprint in a package 1.8
inches long and 0.6 inches wide.
All inputs and outputs of the7MB4084 are TTL compatible
and operate from a single 5V supply. Fully asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Ao
Al
A2
A3
A4
CS
1/00
1/01
Vee
GND
1/02
1/03
WE
As
A6
A7
As
A9
ADDRESS
CS
2Mx8
RAM
WE
OE
1/0
2794drwOl
A20
A19
AlB
Au
A16
OE
1/07
1/06
Vec
GND
1/05
1/04
Als
A14
A13
A12
An
AlO
DIP
TOP VIEW
2794 drw 02
PIN NAMES
1/00-7
Data Inputs/Outputs
AO-20
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vee
Power
GND
Ground
2794 tbl 01
CEMOS is a trademark 01 Integrated Device Technology Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-7095/-
<01992 Integrated Device Technology, Inc.
7.25
ID17MB4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
CS
OE
WE
Output
Power
Symbol
Standby
H
X
X
High-Z
Standby
VTERM
Read
L
L
H
DOUT
Active
Terminal Voltage
with Respect
toGND
Read
L
H
H
High-Z
Active
TA
Write
L
X
L
DIN
Active
Mode
2794 tbl 02
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Typ.
Unit
CIN
Input Capacitance
VIN = OV
35
pF
CIN(e)
Input Capacitance (CS)
VIN = OV
8
pF
COUT
Output Capacitance
VOUT= OV
35
NOTE:
1. This parameter is guaranteed by design, but not tested.
pF
2794 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min.
Parameter
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
-
6
V
-
0.8
V
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
Commercial
Unit
-0.5 to +7.0
V
Operating
Temperature
o to +70
°C
T81AS
Temperature
Under Bias
-10 to +85
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
rnA
Rating
NOTE:
2794 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
GND
Vee
O°C to +70°C
Ov
5V± 10%
2794 tbl 06
2794 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V -+ 10%, TA = O°C to +70°C)
7MB4084LxxP
Max.
Unit
20
20
JlA
JlA
-
0.4
V
Vee = Min., IOH = -1 rnA
2.4
-
V
Dynamic Operating Current
Vee = Max., CS:=; VIL; f = fMAX,
Outputs Open
-
110
rnA
IS8
Standby Supply Current
(TTL Levels)
CS ~ VIH, Vee = Max., f = fMAX,
Outputs Open
-
12
rnA
IS81
Full Standby Supply Current
(CMOS Levels)
CS~ Vee - 0.2V, VIN
or:=; 0.2V
-
450
JlA
Symbol
Parameter
Test Conditions
Min.
-
Vee = Min., IOL = 2mA
Output High Voltage
Icc
IILlI
Input Leakage
Vee = Max., VIN = GND to Vee
IILol
Output Leakage
Vee = Max., CS = VIH,
VOUT = GND to Vee
VOL
Output Low Voltage
VOH
~
Vee - 0.2V
II
2794tbl07
7.25
2
IDT7MB4084
2M x 8 CMOS STATIC RAM MODULE'
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS
(TA = O°C to + 70°C)
Symbol
Parameter
Test Condition
Min.
-
VOR
Vee for Data Retention
lecDR
Data Retention Current
CS ~ Vce • 0.2V
tCDR(2)
Chip Deselect to Data Retention Time
VIN :S Vee· 0.2V or
tR(2)
Operation Recovery Time
VIN ~ 0.2V
2.0
Max.
Vcc@2.0V
Unit
-
V
-
250
j.tA
0
-
ns
tRe llJ
ns
NOTES:
2794 tbl 08
1. tRC = Read Cycle Time.
2. This parameter is guaranteed by design, but not tested.
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VDR~2V
VDR
2794 drw 03
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figures 1 and 2
2794 tbl 09
+5V,
+5V
480n
480n
DATAoUT--------,-------~
DATAoUT--------,-------~
255n
255n
30 pF*
5 pF*
2794 drw 05
2794 drw 04
Figure 1. Output Load
Figure 2. Output Load
(for tOlZ, tCHZ, tOHZ, tWHZ, tow and telz)
7.25
3
IDTIMB4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(2)
(Vee = 5V ± 10%, TA = O°C to +70°C)
7MB4084LxxP
-55
Symbol
Parameter
Min.
-70
Max.
Min.
-85
Max.
Min.
-100
Max.
Min.
-120
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
55
-
70
-
85
-
100
-
120
-
ns
tAA
Address Access Time
-
55
-
70
85
-
100
ns
55
-
85
120
ns
60
ns
20
-
30
-
100
45
35
-
120
30
-
40
ns
5
-
0
ns
5
-
0
5
-
-
20
-
40
tACS
Chip Select Access Time
tOE
Output Enable to Output Valid
tOHZ(1)
tCHZ(1)
Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
tOH
Output Hold from Address Change
5
-
5
tpu(1)
Chip Select to Power-Up Time
0
-
tPO(1)
Chip Deselect to Power-Down Time
-
55
tOLZ(1)
tCLZ(1)
Output Disable to Output in High
5
70
48
33
50
5
-
5
-
5
-
-
43
-
45
-
50
ns
-
5
5
0
-
0
-
0
-
-
ns
-
70
-
85
-
100
-
120
ns
120
-
ns
90
5
-
5
-
ns
-
ns
ns
0
5
0
ns
ns
Write Cycle
twc
Write Cycle Time
55
-
70
-
85
-
100
twp
Write Pulse Width
55
55
65
Address Set-up Time
tAW
Address Valid to End of Write
50
82
-
75
tAS
90
-
100
tcw
Chip Select to End of Write
50
80
-
85
Data to Write Time Overlap
20
38
40
0
0
-
0
0
-
-
100
tow
-
0
-
tOH
Data Hold Time
0
tWR
Write Recovery Time
0
-
tWHZ(1)
Write Enable to Output in High
-
20
-
30
-
33
-
35
-
40
ns
toW(1)
Output Active from End of Write
5
-
0
-
0
-
0
-
0
-
ns
5
Z
0
65
65
35
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
2
0
0
45
ns
ns
ns
ns
27941bll0
II
7.25
4
IDT7MB4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
14-----------
tRG - - - - - - - - - . . - j
ADDRESS
DATAoUT
------------------~
2794 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRG
----------~
ADDRESS
tAA - - - - - - - - - - . . /
14------
tOH -----~
DATAoUT
2794 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
tAGS _ _ _ _~----~~
~~~~~~~~~~~_t_G_LZ_(_5)_-_ -_-_-_-_-_-_~:.~~------t-G-HZ-(-5)-l_
DATAoUT ____
.
-_-_
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.25
2794drw 08
5
IDT7MB4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
twc
ADDRESS
=>K
~-'
) '/
',
,
/ ~
tAW
/
twp (7)
-tAS
~
tWR-
~~
/ ~
~ tWHZ(6)...,
tOHZ (6)
tow (6)
tOHZ (6)
DATAoUT
(4)
l
"-
/
r
tDH
(4)
) f-
tDW-
DATAIN
DATA VALID
"
/
2794 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
~ '/
~
)K
"
_tAS
tAW
'}
/
'/
tcw
DATAIN ________________________________
--(~
tWR
tDW
"I •
DATA VALID
tDH
3~-
2794 drw 10
NOTES:
1.
2.
3.
4.
5.
6.
7.
WE or CS must be high during all address transitions.
A write occurs during the overlap (~ of a low CS and a low WE.
twA is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, 110 pins are in the output state, and input si~s must not be applied.
"the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
Transition is measured ±200mV from steady state with a SpF load (including scope and jig). This parameter is guaranteed by design, but not tested.
"DE is low during a WE controlled write cycle, the write pulse width must be the greater of twp or twHZ + tow to allow the liD drivers to turn olf and data
to be placed on the bus for the required tDW. "DE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
PACKAGE DIMENSIONS -- PLEASE CONSULT FACTORY
7.25
6
G~
2Mx8
CMOS STATIC RAM
MODULE
PRELIMINARY
IDT7MP4059
Integrated Device Technology, Inc.
FEATURES:
• High-density 16 megabit CMOS static RAM module
• Pin-compatible upgrade from IDT7MP4058 (512K x 8)
SRAM module
• Fast access time: 55ns (max.)
• Low power consumption
- Active: 11 OmA (max.)
- CMOS Standby: 450flA (max.)
- Data Retention: 250flA (max.)Vcc = 2V
• Surface-mounted RAM packages on an epoxy laminate
(FR-4) substrate
• Offered in a 36-pin SIP (Single In-line Package) for
maximum space-saving
• Single 5V (±10%) power supply
• Inputs and outputs TTL-compatible
PIN CONFIGURATION
DESCRIPTION:
The IDT7MP4059 is a 2M x 8 high-speed CMOS static
RAM module constructed on an epoxy laminate substrate
(FR-4) using four 512K x 8 static RAMs and a one-of-four
decoder in plastic surface mount packages.
The IDT7MP4059 is available with maximum access times
as fast as 55ns, with maximum operating power consumption
of605mW.
The IDT7MP4059 is offered in a 36-pin SIP (Single In-line
Package). This vertically mounted SIP module is a costeffective solution allowing for very high packing density.
All inputs and outputs of the IDT7MP4059 are TTL-compatible and operate from a single 5V supply. Fully asynchronous
circuitry is used, requiring no clocks or refreshing for operation.
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
A20
ADDRESS
\l::c
WE:
6
7
8
9
10
2;/
WE -----0
11/02
1/0 3
2M x 8
OE-o
1/00
Al
RAM
CS -----0
A2
A3
A4
11
12
13
14
15
16
17
18
19
20
21
22
23
GND
1/05
24
25
26
As
27
28
29
30
31
32
33
34
35
36
Ao
Al0
DATA 110
Al1
As
A13
2840 drw 02
A14
Alg
55
A1s
A16
A12
AIS
PIN NAMES
1/01
AO-20
Address Inputs
1/00-7
Data Inputs/Outputs
OE
Output Enable
1/07
WE
Write Enable
1104
1106
CS
Chip Select
GND
A7
As
Ag
A17
\l::c
DE:
Vcc
Power
GND
Ground
--
2840 lbl 01
SIP
BACK VIEW
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
©1992 Integrated Device Technology, Inc.
DSC·709411
7.26
IDTIMP4059
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating(1)
Commercial
Unit
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
V
TA
o to +70
Operating
Temperature
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
°C
T81AS
Temperature
Under Bias
-10 to +85
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
Parameter
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
V
VIH
Input High Voltage
2.2
a
-
6
V
VIL
Input Low Voltage
-0.5
-
0.8
V
Unit
NOTE:
1. VIL = -3.0V for pulse width less than 20ns
2840 tbl 04
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
2840 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device atthese or any other conditions
above those indicated in the operational sections ofthisspecification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Grade
Commercial
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
5V± 10%
2840 tbl 05
CAPACITANCE
Symbol
CIN
TRUTH TABLE
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions Typ.
Input Capacitance
CIN(e)
Input Capacitance (CS)
COUT
Output Capacitance
Unit
Mode
CS
OE
WE
Output
Power
H
X
X
High-Z
Standby
= OV
VIN = OV
35
8
pF
Read
L
L
H
DOUT
Active
VOUT= OV
35
pF
Read
L
H
H
High-Z
Active
2840tbl03
Write
L
X
L
DIN
Active
VIN
NOTE:
1. This parameter is guaranteed by design, but not tested.
pF
Standby
2840tbl06
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10% TA = O°C to +70°C)
Symbol
Parameter
Test Conditions
= Max., VIN = GND to Vee
III
Input Leakage
Vee
ILO
Output Leakage
Vee = Max., CS = VIH, VOUT = GND
to Vee
Min.
Max.
Unit
-
20
j.iA
20
j.iA
-
0.4
V
2.4
-
V
Vee = Max., CS ~ VIL; f = fMAX,
Outputs Open
-
110
mA
Standby Supply Current
(TTL Levels)
CS ~ VIH, Vee = Max., f = fMAX,
Outputs Open
-
12
mA
Full Standby Supply Current
(CMOS Levels)
CS~ Vee 0.2V, VIN
or ~ 0.2V
-
450
j.iA
VOL
Output Low Voltage
Vee = Min., IOL = 2mA
VOH
Output High Voltage
Vee = Min., IOH
Icc
Dynamic Operating Current
IS8
IS81
=-1 mA
~
Vee-0.2V
2840 tbl 07
7.26
2
IDT7MP4059
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS
(TA = O°C TO +70°C)
Vcc@2.0V
Symbol
Test Condition
Parameter
Min.
-
VOR
VCC for Data Retention
leeoR
Data Retention Current
teoR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
Max.
-
250
VIN::;; Vee - 0.2V or
0
VIN ~ O.2V
tRd 1)
-
CS ~ Vee - 0.2V
Unit
-
:2.0
V
.!lA
ns
ns
NOTES:
1. tRC = Read Cycle Time
2. This parameter is guaranteed by design, but not tested.
2840 tbl 08
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VOR ~2V
2840 drw 03
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 and 2
Output Load
2840tbl09
+5V
+5V
4800
4800
DATAoUT-...---i
2550
DATAoUT-....--.....
30pF"
2550
2840 drw05
2840 drw 04
"Including scope and jig.
FIgure 2. Output Load
(For tOLz, tCHZ, tOHZ, tWHZ, tow and tCLl)
FIgure 1. Output Load
7.26
3
IDnMP4059
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vec = 5V ± 10%, TA = O°C to +70°C)
7MP4059LxxS
-55
Parameter
Symbol
Min.
-70
Max.
Min.
-85
Max.
Min.
-100
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read
55
-
70
-
85
-
100
-
ns
tAA
Address Access Ti me
-
55
-
70
85
ns
Chip Select Access Time
-
55
-
70
85
-
100
tACS
-
100
ns
tOE
Output Enable to Output Valid
30
-
45
-
48
-
50
ns
20
-
30
-
33
-
35
ns
0
-
0
-
ns
C~cle
Time
tOHZ(1)
Output Disable to Output in High Z
-
tOLZ(1)
Output Enable to Output in Low Z
0
tCLZ(1)
Chip Select to Output in Low Z
5
-
5
-
5
-
tCHZ(1)
Chip Deselect to Output in High Z
-
20
-
40
-
43
tOH
Output Hold from Address Change
5
-
5
-
5
-
tPU(1)
Chip Select to Power-Up Time
tPD(1)
Chip Deselect to Power-Down Time
5
5
-
0
-
-
55
-
70
-
85
-
70
-
0
-
0
0
0
ns
45
ns
-
ns
-
ns
100
ns
Write Cycle
twc
Write Cycle Time
55
twp
Write Pulse Width
40
tAS
Address Set-up Time
0
tAW
Address Valid to End of Write
45
tcw
Chip Select to End of Write
45
tow
Data to Write Time Overlap
30
tDH
Data Hold Time
0
-
tWR
Write Recovery Time
0
tWHZ(1)
Write Enable to Output in High Z
toW(1)
Output Active from End of Write
55
0
65
85
-
100
-
ns
65
-
75
-
ns
2
-
5
-
ns
90
-
ns
82
38
0
-
0
-
-
0
-
0
-
20
-
-
30
-
33
5
-
0
-
0
-
NOTE:
1. This parameter is guaranteed by design, but not tested.
65
35
80
85
-
ns
40
-
ns
0
-
ns
0
-
ns
0
35
ns
-
ns
2840tbll0
II
7.26
4
IDT7MP4059
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
~
_________________t_AA_____t_RG_______________________
tOLZ (5) -.f4.---~
~---------
tGLl !5)
-----~
DATAoUT --------~----------------------------~
tAGS - - - - - - - - - - - '
2840 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2 (1, 2, 4)
tRG
ADDRESS
tOH
tOH
DATA VALID
DATAoUT
2840 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
tGLZ(5) - - - - . . . . ,
tGHZ(5) -
DATA VALID
DATAoUT
tAGS
-------~
2840 drw 08
NOTES:
1. WE is High for Read Cycle
2. Device is continuously selected CS = VIL
3. Address valid prior to or coincident with CS transition low
4. DE = VIL
5. Transition is measured = 200mV from steady state. This parameter is guaranateed by design but not tested.
7.26
5
IDT7MP4059
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3,7)
.
ADDRESS
twe
II
~E
) ~
7 fL-
..
~
""--
II'
tAW
tAS
~
~
..
twp(7}
..
~
7
DATAIN
r-
(4)
tOHZ(6}
"
/'
tWR
~
I
tow (6)
tWHZ(6}
DATAoUT
L
7
l-r
-
l
tOHZ(6}(4)
1
tDW~
DATA VALID
I
tDH
>-
J
'I
2840 dlW 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3,5)
I~"~------------------- twe
ADDRESS
tAW
-- _
DATAIN
tAS -1Ioi~------------- tew
l~ lOW -~IOH
-------------------------------(K
DATA VALID
-I>)1----:..------- •
2840 dlW 10
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlay (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write
pulse can be as short as the specified twP.
PACKAGE DIMENSIONS -
PLEASE CONSULT FACTORY
7.26
6
t;)®
IDT7M4048
IDT7MB4048
512K x 8
BiCMOS/CMOS STATIC
RAM MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 4 megabit (S12K x 8) static RAM module
• Equivalent to the JEDEC standard for future monolithic
512K x 8 static RAMs
• Fast access time: 1Sns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: 400llA (max.)
- Data Retention: 250llA (max.) Vee = 2V
• Surface mounted plastic packages on a 32-pin, 600 mil
ceramic or FR-4 DIP substrate
• Single SV (±10%) power supply
• Inputs/outputs directly TTL compatible
The IDT7M4048/7MB4048 is a 4 megabit (S12K x 8)
static RAM module constructed on a co-fired ceramic or
multilayer epoxy laminate (FR-4) substrate using four 1
megabit static RAMs and a decoder. The IDT7MB4048 is
available with access times as fast as 15ns. For low power
applications, the IDT7M4048 version offers a data retention
current of 200ilA and a standby current of 400J.1A
The IDT7M4048 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 4 megabits into the JEDEC DIP footprint. The
IDT7MB4048 likewise is packaged in a 32-pin FR-4 DIP
resulting in the same JEDEC footprint in a package 1.6
inches long and 0.6 inches wide.
All inputs and outputs of the IDT7M4048 and 7MB4048
are TTL compatible and operate from a single SV supply.
Fully asynchronous circuitry requires no clocks or refresh for
operation and provides equal access and cycle times for
ease of use.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Vee
A15
A17
WE
A13
Aa
Ag
All
OE
Al0
CS
Ala
A16
A14
A12
A7
A6
A5
A4
A3
A2
Al
Ao
I/O?
110s
1/05
1/04
1/03
1/00
1/01
1/02
GND
DIP
TOP VIEW
ADDRESS
19
512K x 8
CS
RAM
WE
OE
1/0
2675 drw 01
2675 drw 02
PIN NAMES
1/00-7
Data Inputs/Outputs
AO-1B
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vee
Power
GND
Ground
2675tbl01
CEMOS is a trademark of Integrated Device Technology Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-4047/3
©1992 Integrated Device Technology, Inc.
7.27
IDTIM4048,IDTIMB4048
512K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
CS
~
WE
Output
Power
Symbol
Standby
H
X
X
High-Z
Standby
VTERM
Read
L
L
H
DOUT
Active
Terminal Voltage
with Respect
toGND
Read
L
H
H
High-Z
Active
TA
Write
L
X
L
DIN
Active
Mode
2675 tbl 02
CAPACITANCE(1)
Symbol
CIN
f = 1.0MHz)
(TA = +25°e,
Parameter
Conditions
Typ.
Unit
= OV
VIN = OV
VOUT = OV
35
pF
Input Capacitance
VIN
CIN(e)
Input Capacitance (CS)
COUT
Output Capacitance
S
pF
35
pF
NOTE:
1. This parameter is guaranteed by design, but not tested.
2675 tbl3
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
-
6
V
O.S
V
Rating
Commercial
Unit
-0.5 to +7.0
V
Operating
Temperature
Oto+70
°C
TBIAS
Temperature
Under Bias
-10 to +S5
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
NOTE:
2675 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXI MU M RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLVVOLTAGE
Grade
Commercial
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
5V± 10%
2675tbl06
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
2675tbl04
DC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = ooe to +70°C)
7MB4048SxxP
Symbol
Parameter
Ilul
Input Leakage
IILol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Dynamic Operating Current
\.-
7M4048LxxN
Test Conditions .
= Max., VIN = GND to Vee
Vee = Max., CS = VIH,
VOUT = GND to Vee
Vee = Min., IOL = 2mA(1),
IOL = SmA(2)
Vee = Min., IOH = -1 mA(1),
IOH = -4mA(2)
Vee = Max., CS::;; VIL; f = fMAX,
Vee
Min.
Max.
25 - 55ns
Min.
Max.
15 - 20ns(3)
Max.
Unit
S
8
JlA
JlA
-
0.4
V
-
2.4
-
V
-
4S0
-
520
mA
12
-
250
-
250
mA
0.4
-
50
-
170
mA
-
4
-
S
4
-
-
0.4
2.4
Min.
S
-
-
0.4
-
2.4
-
110
-
Outputs Open
= Max., f =fMAX,
ISB
Standby Supply Current
(TTL Levels)
CS ~ VIH, Vee
Outputs Open
ISB1
Full Standby Supply Current
(CMOS Levels)
CS ~ Vee - 0.2V, VIN ~ Vee - 0.2V
or::;; 0.2
NOTES:
1. For 7M4048LxxN version only.
2. For 7MB4048SxxP version only.
3. Preliminary specifications only.
2675 tbl 07
7.27
2
II
IDT7M4048, IDT7MB4048
512K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS(3)
(TA = O°C to +70°C)
Symbol
Parameter
Test Condition
Max.
VCC@2.0V
Min.
-
2.0
-
CS ~ Vee· 0.2V
-
250
Chip Deselect to Data Retention Time
VIN $ Vcc • O.2V or
0
Operation Recovery Time
VIN
-
VOR
Vee for Data Retention
leCDR
Data Retention Current
teoR(2)
tR(2)
~
tRc llJ
O.2V
Unit
V
~
ns
ns
NOTES:
1. lAc = Read Cycle Time.
2. This parameter is guaranteed by design, but not tested.
3. For 7M4048LxxN version only.
2675tbl08
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VOR
~
2V
VOR
2675 drw03
AC TEST CONDITIONS
Input Pulse Levels
GNDto 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 • 4
Output Load
2675 tbl 09
+5V
+5V
480n
480n
DATAoUT--------,-------,
255n
DATAoUT---------r------~
255n
30 pF*
2675 drw04
5 pF*
2675 drw 05
Figure 2. Output Load
(for tOll, tcHZ, tOHZ, tWHZ, tow and tCLl)
Figure 1. Output Load
7.27
3
IDT7M4048, IDT7MB4048
512K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
IITM
(Typical. ns)
5
DATA OUT ~'r'---------r=n
ZO =500
1
=
500
1.SV
20
40
60
80
100 120 140 160 180 200
2675 drw 04a
CAPACITANCE (PF)
267Sd!w 05.
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
Figure 3. Alternate Output Load
AC ELECTRICAL CHARACTEF .ISTICS
(VCC = SV ± 10%, TA = O°C to +70°C)
7MB4048SxxP
I
.1Sl;jj
Symbol
Parameter
Min.
Max.
.17l;jj
Min.
Max.
I
I
.20l;jj
Min.
Max.
I
.?5
Min. Max.
.::10
·35
Min~ Max. Unit
Min.
Max.
30
-
-
35
-
30
30
15
12
-
35
35
15
15
-
a
-
ns
5
20
ns
ns
Read Cycle
tRC
Read Cycle Time
15
-
17
-
20
-
25
-
tAA
Address Access Time
-
Chip Select Access Time
tOE
Output Enable to Output Valid
tOHZ(l)
Output Disable to Output in High Z
17
17
8
7
-
tACS
-
20
20
10
8
-
25
25
12
12
tOLZ(l)
Output Enable to Output in Low Z
a
a
Chip Select to Output in Low Z
5
-
a
tClZ(l)
-
5
-
tCHZ(l)
Chip Deselect to Output in High Z
tOH
Output Hold from Address Change
1
15
15
8
7
12
-
tpu(1)
Chip Select to Power-Up Time
a
-
tpo(1)
Chip Deselect to Power-Down Time
-
15
-
-
-
a
5
-
12
1
a
-
-
17
-
5
3
13
-
14
3
a
-
a
-
-
20
-
20
15
3
18
18
12
-
25
17
3
20
20
15
-
-
a
a
-
a
5
3
-
ns
ns
ns
ns
ns
16
3
a
-
a
-
25
-
30
-
35
ns
-
30
20
35
25
-
ns
a
25
25
-
ns
-
-
-
ns
-
ns
-
ns
15
-
ns
ns
Write Cycle
15
15
3
15(5)
-
twc
Write Cycle Time
twp
Write Pulse Width
tAS(2)
Address Set-up Time
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
tow
Data to Write Time Overlap
tOH(2)
Data Hold Time
15
10
0
tWR(2)
Write Recovery Time
a
-
tWHZ(l)
Write Enable to Output in High Z
-
toW(l)
Output Active from End of Write
2
-
17 14 3
17(4) 17 10 0
-
-
-
a
-
a
a
8
-
10
-
13
-
-
2
-
2
-
2
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. tAS=Ons for CS controlled write cycles. tDH, twR= 3ns for CS controlled write cycles.
3. Preliminary specifications only.
4. tAW=14ns for CS controlled write cycles.
5. tAW=12ns for CS controlled write cycles.
7.27
a
-
30
30
20
ns
ns
17
-
0
-
a
-
a
a
5
15
-
15
ns
-
5
-
ns
ns
2675tbll0
4
fI
IDT7M4048, IDT7MB4048
512Kx 8 BICMOS/CMOSSTATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = DoC to +70°C)
7MB4048SxxP
-45
Symbol
Read Cycle
Parameter
Min.
7M4048LxxN
Min.
_65(3)
-60(3)
-55
Max.
Max.
Min.
Max.
Min.
-70
Max.
Min.
Max. Unit
tRC
Read Cycle Time
45
-
55
-
65
-
65
-
70
-
ns
tAA
Address Access Time
Output Enable to Output Valid
-
60
60
30
25
-
65
65
35
25
70
70
45
30
ns
Chip Select Access Time
55
55
30
20
-
tOE
tOHZ(1)
45
45
25
20
-
tACS
-
tOLZ(1)
Output Enable to Output in Low Z
-
-
tCLZ(1)
Chip Select to Output in Low Z
5
5
-
5
5
-
0
5
tCHZ(1)
Chip Deselect to Output in High Z
-
tOH
tPU(1)
Output Hold from Address Change
tPO(1)
Output Disable to Output in High Z
-
-
ns
ns
ns
-
ns
-
ns
ns
-
40
10
0
-
ns
65
-
70
ns
65
55
0
65
65
30
0
0
-
70
55
0
65
65
35
0
0
-
ns
-
ns
ns
-
5
5
-
3
5
20
-
20
-
25
-
25
-
Chip Select to Power·Up Time
5
0
-
5
0
-
10
0
-
10
0
-
Chip Deselect to Power· Down Time
-
45
-
55
-
65
-
-
55
45
5
50
50
20
0(2)
0(2)
-
-
65
50
0
60
60
30
0
0
-
ns
Write Cycle
twc
Write Cycle Time
twp
Write Pulse Width
tAS
Address Set·up Time
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
tDW
Data to Write Time Overlap
tDH
Data Hold Time
tWR
tWHZ(1)
Write Recovery Time
45
35
5
40
40
20
0(2)
0(2)
Write Enable to Output in High Z
-
15
-
20
-
25
-
25
-
30
tOW(1)
Output Active from End of Write
5
-
5
-
0
-
0
-
0
-
-
NOTES:
-
ns
ns
ns
ns
ns
ns
ns
2675tblll
1. This parameter is guaranteed by design, but not tested.
2. tAs=Ons for CS controlled write cycles. tDH, twR= 5ns for CS controlled write cycles.
3. Preliminary specifications only.
7.27
5
IDT7M4048, IDT7MB4048
512K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10%, TA = O°C to +70°C)
7M4048LxxN
-85
Symbol
Read Cycle
Parameter
Min.
-120
-100
Max.
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
85
-
100
-
120
-
ns
tAA
Address Access Time
-
-
120
ns
Chip Select Access Time
Output Enable to Output Valid
-
tOLZ(1)
Output Enable to Output in Low Z
Chip Select to Output in Low Z
tCHZ(1)
Chip Deselect to Output in High Z
-
tOH
tPU(1)
Output Hold from Address Change
10
43
-
50
ns
tCLZ(1)
-
ns
Chip Select to Power-Up Time
0
-
Chip Deselect to Power-Down Time
-
85
120
ns
tPO(1)
0
5
10
0
-
120
60
40
ns
tOE
tOHZ(1)
0
5
100
100
-
tACS
85
85
48
-
100
-
75
Output Disable to Output in High Z
33
-
-
50
35
-
-
0
-
5
45
-
-
100
10
0
-
ns
ns
ns
ns
ns
Write Cycle
twc
Write Cycle Time
twP
Write Pulse Width
85
65
tAS
Address Set-up Time
2
82
80
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
tow
Data to Write Time Overlap
tOH
Data Hold Time
tWR
tWHZ(1)
Write Recovery Time
tow(1)
-
5
90
-
120
-
ns
90
-
5
-
ns
100
100
-
85
40
0
0
-
0
-
Write Enable to Output in High Z
-
33
-
35
0
-
Output Active from End of Write
0
-
0
-
0
38
0
NOTE:
-
45
0
40
-
ns
ns
ns
ns
ns
ns
ns
ns
2675tbl12
1. This parameter is guaranteed by design, but not tested.
7.27
6
,.
IDTIM4048, IDTIMB4048
512K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~---------- tRC---------~
ADDRESS
DATAoUT
2675 drw 06 .
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~----------- tRC
ADDRESS
tAA
~-----
tOH _ _ _ _---1--1
DATAoUT
2675 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
tACS
~_ _ _ _ _ tCLl (5) -------t~
DATAoUT----------------------------------~
2675 drw 08
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.27
7
IDTIM4048, IDTIMB4048
512K x 8 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3,7)
twc
ADDRESS
-
K
)
)
K
OE
CS
/
k'"
tAW
~
'"
/
__ tAS
WE
twp
tOHZ
DATAoUT
tWR _
(7)
~~
f4--- tWHZ
(4)
~
/ ~
tOHZ
(6) __
(6)
tow (6)
(6)
"
./
l
tOH
tow-
DATAIN
r
"
DATA VALID
(4)
'"
)-
/
2675 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2,3,5)
ADDRESS
-
twc
)
K
)
K
tAw
_00
1-
/
V
tcw
\
tWR
fI
WE
DATAIN
----------(E
tow
.. '.
DATA VALID
tOH3)1-__
2675 drw 10
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the 110 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7.27
8
I
IDTIM4048, IDTIMB4048
512K x 8 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7M4048LxxN
0.385
MAX.
5
~
•
0.015
Pin 1
t
t)t~:1'1111' ,ii" "!!!~
~ r'
I
..Q.Q.1§..
""Q."06"5
0.025
0.100
TYP.
SIDE VIEW
~
0.590
. "Q.62"O
"L- ~
j4-"14, ..\\..-,
I
I
0.035
0.405
MAX.
0.175
~
0.013
I-I
\..
~I
... j.-
[:::][:::JI
BonOM VIEW
2675 drw 11
7MB4048SxxP
r-
1.590~
1.610
I
TOP VIEW
SIDE VIEW
0.590
0.620
BOTTOM VIEW
2675 drw 12
7.27
9
(;)®
512K x 8
CMOS STATIC RAM MODULE
PRELIMINARY
IDT7M4048
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 4 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
S12K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
-Active: 110mA (max.)
- CMOS Standby: 1.4mA (max.)
- Data Retention: 800llA (max.) Vce = 2V
• Surface mounted LCCs (Ieadless chip carriers) on a 32pin, 600 mil ceramic DIP substrate
• Single SV (±10%) power supply
• Inputs/outputs directly TTL compatible
The IDT7M4048 is a 4 megabit (S12K x 8) CMOS static
RAM module constructed on a co-fired ceramic substrate
using four 1 Megabit static RAMs and a decoder. The
IDT7M4048 is available with access times as fast as 17ns.
For low power applications, the IDT7M4048 version offers a
data retention current of 800llA and a standby current of
1.4mA.
The IDT7M4048 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 4 megabits into the JEDEC DIP footprint.
All inputs and outputs of the IDT7M4048 are TIL compatible and operate from a single SV supply. Fully asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
All lOT military module semiconductor components are
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
CS
512K x 8
RAM
II
WE
OE
I/O
2822 dlW 02
CEMOS is a trademark of Integrated Device Technology Inc.
MILITARY TEMPERATURE RANGE
APRIL 1992
©1992 Integrated Device Technology. Inc.
DSC·707411
7.28
IDnM4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PIN CONFIGURATION
PIN NAMES
A1S
A1S
Al
Vcc
A1S
A17
WE
A13
As
A9
All
OE
Ala
CS
Ao
IIOJ
1/06
A14
A12
A7
As
As
A4
A3
A2
1/00-7
Data Inputs/Outputs
AO-1S
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vee
Power
GND
Ground
2822 tbl 01
1107
1/05
1104
1/03
1/01
1102
GND
2822 drw 01
DIP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(l)
TRUTH TABLE
CS
OE
WE
Output
Power
Symbol
Military
Unit
Standby
H
X
X
High-Z
Standby
VTERM
-0.5 to +7.0
V
Read
L
L
H
DOUT
Active
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
-55 to +125
°C
TSIAS
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to +160
°C
lOUT
DC Output Current
50
mA
Mode
Read
L
H
H
High-Z
Active
Write
L
X
L
DIN
Active
2822tbl09
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter
Conditions
Typ.
Unit
VIN = OV
50
pF
VIN = OV
10
pF
VOUT= OV
40
pF
Input Capacitance
CIN(C)
Input Capacitance (CS)
COUT
Output Capacitance
NOTE:
1. This parameter is guaranteed by design, but not tested.
2822tbll0
RECOMMENDED DCOPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
-
6
V
0.8
V
Rating
NOTE:
2822 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATI NGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
GND
-55°C to + 125°C
OV
Vee
5V
± 10%
2822tbl04
2822tbl03
7.28
2
IDTIM4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%. TA = -55°C to +125°C)
7M4048SxxCB 7M4048LxxCB
Symbol
Parameter
17ns-55ns
Test Conditions
Min.
Vee = Max., VIN
IILlI
Input Leakage
IiLol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
Icc
Dynamic Operating Current
= GND to Vee
Vee = Max., CS = VIH,
VOUT = GND to Vee
Vee = Min., IOL = 2mA(1),
IOL = 8mA(2)
Vee = Min., IOH = -1 mA(1),
IOH = -4mA(2)
Vee = Max., CS::; VIL; f = fMAX,
60ns-120ns
Max.
Max.
Unit
20
20
-
20
J.lA
J.lA
-
0.4
-
0.4
V
2.4
-
2.4
-
V
-
240
-
110
rnA
-
120
-
12
rnA
rnA
-
20
Min.
Outputs Open
158
Standby Supply Current
(TTL Levels)
CS 2: VIH, Vee = Max., f
Outputs Open
=fMAX,
1581
Full Standby Supply Current
(CMOS Levels)
CS 2: Vee - 0.2V, VIN 2: Vee - O.2V
or::; 0.2V
-
60
-
4
Very Low Power Version(3)
-
60
-
1.4
NOTES:
1. For 17ns-55ns versions only.
2. For 60ns-120ns versions only.
3. L version only.
rnA
2822 tbl 05
DATA RETENTION CHARACTERISTICS(5)
(TA = -55°C to + 125°C)
Symbol
VOR
Parameter
Test Condition
-
Vee for Data Retention
Min.
Max.
Vcc@2.0V
Unit
2.0
-
V
rnA
ns
leeoR
Data Retention Current
CS 2: Vee - 0.2V
-
2(4)
teoR(3)
m(3)
ChiD Deselect to Data Retention Time
VIN::; Vee - 0.2V or
a
Operation Recovery Time
VIN> 0.2V
-
tRe(2)
ns
NOTES:
1. Vee = 2V, TA = +25°C.
2. me = Read Cycle Time.
3. This parameter is guaranteed by design, but not tested.
4. For 60ns-120ns versions, ICCDR=800f.\A.
5. L version only.
2822tbl09
fI
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VOR2:2V
VOR
2822 drw 03
7.28
3
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
2822tbl07
+5V
+5V
480n
480n
DATAoUT--+--....
DATAoUT - - + - -....
255n
255n
2822 drw 10
Figure 2. Output Load
(for tOlZ, tCHZ, tOHZ, tWHZ, tow and tClZ)
Figure 1. Output Load
• Including scope and jig
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V +
- 10%, TA = O°C to +70°C)
7M4048SxxCB, 7M4048LxxCB
_17(::1)
Symbol
Read Cycle
Parameter
_20(::1)
Min.
Max.
Min.
-25
Max.
-30
Min.
Max.
Min.
-35
Max.
Min.
Max. Unit
tRC
Read Cycle Time
17
-
20
-
25
-
30
-
35
-
ns
tAA
Address Access Time
-
17
-
20
-
25
30
-
35
ns
tACS
Chip Select Access Time
17
30
35
ns
15
-
15
ns
Output Disable to Output in High Z
-
7
-
25
Output Enable to Output Valid
-
20
tOE
tOHZ(1)
-
-
12
-
15
ns
tOLZ(1)
Output Enable to Output in Low Z
0
0
5
5
-
ns
5
-
0
5
-
0
Chip Select to Output in Low Z
-
0
tCLZ(1)
-
tCHZ(1)
Chip Deselect to Output in High Z
-
12
-
13
-
14
-
16
-
20
ns
tOH
tPU(1)
Output Hold from Address Change
1
3
-
3
0
-
0
-
ns
0
-
3
0
-
3
Chip Select to Power-Up Time
-
tPD(1)
Chip Deselect to Power-Down Time
-
17
-
20
-
25
-
30
-
35
ns
20
-
25
-
30
-
17
20
-
ns
3
0
-
ns
30
ns
0
-
0
-
0
-
0
-
35
15
0
-
ns
-
15
ns
8
10
8
12
12
5
0
ns
ns
Write Cycle
twe
Write Cycle Time
17
twp
tAS(2)
Write Pulse Width
14
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
17
tow
tOH(2)
Data to Write Time Overlap
10
Data Hold Time
0
tWR(2)
Write Recovery Time
0
-
tWHZ(1)
Write Enable to Output in High Z
-
10
-
13
-
15
-
15
tow(1)
Output Active from End of Write
2
-
2
-
2
-
5
-
Address Set-up Time
3
17(4)
18
18
12
0
NOTES:
1.
2.
3.
4.
3
20
20
15
0
0
25
25
17
0
25
30
20
5
-
ns
ns
ns
ns
ns
2822tbl06
This parameter is guaranteed by design, but not tested.
tAS=Ons for CS controlled write cycles. tDH, tWR= 3ns for WE controlled write cycles.
Preliminary specifications only.
tAW=14ns for CS controlled write cycles.
7.28
4
ID17M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = -55°C to +125°C)
7M4048SxxCB, 7M4048LxxCB
I
-45
Symbol
Parameter
Min.
Max.
-65 1")
-60 1")
-55
Min.
Max.
Min.
Max.
Min.
-70
Max.
Min.
Max. Unit
Read Cycle
-
70
-
ns
65
65
35
25
-
ns
-
0
5
70
70
45
30
-
ns
-
ns
40
10
ns
tRC
Read Cycle Time
45
-
55
-
65
-
tAA
Address Access TIme
-
45
45
-
55
55
-
60
60
30
20
-
30
25
25
-
-
25
10
0
-
-
0
-
-
65
50
tACS
Chip Select Access Time
tOE
tOHZ(1)
Output Enable to Output Valid
tOLZ(1)
Output Enable to Output in Low Z
tCLZ(1)
Chip Select to Output in Low Z
tCHZ(1)
Chip Deselect to Output in High Z
tOH
Output Hold from Address Change
tPU(1)
Chip Select to Power-Up Time
tPO(1)
Chip Deselect to Power-Down Time
Output Disable to Output in High Z
5
5
5
0
-
-
3
5
20
-
20
-
-
5
-
10
25
20
-
45
5
5
0
-
55
55
-
45
5
20
-
65
65
5
5
-
65
0
-
ns
ns
ns
ns
70
ns
-
ns
ns
Write Cycle
twc
Write Cycle Time
45
twp
Write Pulse Width
tAS
Address Set-up TIme
35
5
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
tow
Data to Write Time Overlap
tDH
Data Hold TIme
20
0(2)
tWR
Write Recovery TIme
0(2)
tWHZ(1)
Write Enable to Output in High Z
-
toW(1)
Output Active from End of Write
40
40
5
-
-
15
-
50
50
20
0(2)
0(2)
5
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. tAS=Ons for CS controlled write cycles. tDH, twR= 5ns for WE controlled write cyeles.
3. Preliminary specifications only.
0
-
-
25
0
-
0
60
60
30
0
65
55
0
65
65
30
0
0
0
25
-
70
55
0
-
ns
-
ns
65
-
ns
65
35
0
-
ns
0
0
-
ns
-
ns
30
ns
-
ns
ns
2822tbl06
II
7.28
5
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10% TA = -55°C to + 125°C)
7M4048SxxCB, 7M4048LxxCB
-85
Symbol
Read Cycle
Parameter
Min.
-100
Max.
Min.
-120
Max.
Min.
Max.
Unit
tAC
Read Cycle Time
85
-
100
-
120
-
ns
tAA
Address Access Time
-
85
-
100
-
120
ns
tACS
Chip Select Access Time
85
ns
50
-
120
Output Enable to Output Valid
60
ns
tOHZ(1~
Output Disable to Output in High Z
-
100
tOE
-
35
-
40
ns
tOLZ(1)
Output Enable to Output in Low Z
0
-
0
ns
tCLZ(1)
Chip Select to Output in Low Z
5
-
5
-
tCHZ(1)
Chip Deselect to Output in High Z
-
43
-
45
-
50
ns
tOH
Output Hold from Address Change
10
10
0
0
-
ns
Chip Select to Power-Up Time
-
10
tpu(1)
-
tPD(1)
Chip Deselect to Power-Down Time
-
85
-
100
-
120
ns
48
33
-
0
5
0
ns
ns
Write Cycle
twc
Write Cycle Time
85
-
100
-
ns
Write Pulse Width
65
75
90
Address Set-up Time
2
5
-
5
tAW
Address Valid to End of Write
82
-
90
100
tcw
Chip Select to End of Write
80
-
85
-
-
ns
tAS
-
-
120
twp
tDW
Data to Write Time Overlap
38
-
40
45
Data Hold Time
0
-
0
0
-
ns
tDH
tWR
Write Recovery Time
0
-
0
-
0
-
ns
tWHZ(1)
Write Enable to Output in High Z
35
-
40
ns
tow(1)
Output Active from End of Write
-
ns
0
NOTE:
1. This parameter is guaranteed by design, but not tested.
33
-
0
-
100
0
ns
ns
ns
ns
2822tbl08
7.28
6
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OFREAD CYCLE NO. 1(1)
~--------------tRC--------------~
ADDRESS
DATA OUT
---------------------------<
2822 drw 04
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~----------------tRC----------------~
ADDRESS
~-------------tAA --------------~
~-------tOH--------~
DATA OUT
~_
_ _ _ _ _ _~110.-
2822drw05
II
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS1==-:~--=--~__=_---t-CL-Z(-5)-=-t-A-CS-=-_=.-.p-, -ttCHZ{5 P
-,.-,
II<
DATA OUT
l
~
'2822drw06
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guranateed by design, but not tested.
7.28
7
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING}(1, 2, 3, 7)
ADDRESS
twe
=>K
)(
)f
tAW
~~
/~
twp(7)
I--tAS
tWR_
~i\..
/'r
~tWHZ(6) ....
t OHZ(6)
tOW(6)
tOHZ(6)
DATA OUT
(4)
"-
/
~
~
tow-
DATA IN
"
DATA VALID )
"
(4)
)r2B22 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING}(1, 2, 3,5)
ADDRESS
=>K
.-'AS "}
twe
)(
tAW
/V
tew
tWR
DATAIN--------------------------~K:=
tow
.. I.
tOH
DATA VALID
2B22 drw OB
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, write pulse ((twp) > twHZ + tow) to allow the 1/0 drivers to turn off and data to be placed on the bus for the required
tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.
7.28
8
IDTIM4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PACKAGE DIMENSIONS
1.680
~I
\+--U20
::: III
PIN 1
I'
aD
aD
~
aD
I
aD
TOP VIEW
0.005
0.040
~
~10.590
0.035
M65
0.015
M25
0.100
TYP.
0.007
_1_
0.013
~
0.620
END VIEW
SIDE VIEW
BonOMVIEW
•
7.28
9
(;)®
512K x 8
CMOS STATIC RAM MODULE
IDT7MP4058
Integrated DevIce Technology, Inc.
FEATURES:
DESCRIPTION:
• High-density 4 megabit CMOS static RAM module
• Pin compatible with future 16 megabit upgrade
(IDT7MP4059)
• Fast access time: 70ns (max.)
• Low power consumption
- Active: 11 OmA (max.)
- CMOS Standby: 450llA (max.)
- Data Retention: 250jlA (max.)Vee = 2V
• Surface-mounted RAM packages on an epoxy laminate
(FR-4) substrate
• Offered in a 36-pin SIP (Single In-line Package)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
The IDT7MP4058L isa 512K x 8 high-speed CMOS static
RAM module constructed on an epoxy laminate substrate
(FR-4) using four 128K x 8 static RAMs and a one-of-four
decoder in plastic surface mount packages.
The IDT7MP4058L is available with maximum access
times as fast as 70ns, with maximum operating power consumption of 605mW.
The IDT7MP4058L is offered in a 36-pin SIP (Single In-line
Package). This vertically mounted SIP module is a costeffective solution allowing for very high packing density.
All inputs and outputs of the IDT7MP4058L are TILcompatible and operate from a single 5V supply. Fully asynchronous circuitry is used, requiring no clocks or refreshing for
operation.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ADDRESS
WE ----..0
OE--.a
Vee
WE
1/02
1/03
1/00
512K x a
RAM
CS~
fa
Al
A2
A3
A4
DATA I/O
GND
2798 drw 02
1/05
Al0
All
As
A13
A14
NC
CS
PIN NAMES
AO-1B
A15
A16
A12
A18
As
1/01
GND
Ao
A7
As
As
1/07
1/04
1/06
Address Inputs
1/00-7
Data Inputs/Outputs
DE
WE
Output Enable
Write Enable
CS
Chip Select
Vce
Power
GND
Ground
NC
No Connect
2798tbiOl
A17
Vee
OE
2798 drw 01
SIP
BACK VIEW
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
eSC·705M
©1992 Integrated Device Technology. Inc.
7.29
IDTIMP4058
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating(1)
Commercial
Unit
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Operating
Temperature
o to +70
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
TA
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
°C
Parameter
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5
5.5
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6
V
VIL
Input Low Voltage
-0.5
-
0.8
V
V
NOTE:
1. VIL = -3.0V for pulse width less than 20ns
NOTE:
2798 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Unit
2798 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
GND
O°C to +70°C
OV
Vee
5V
± 10%
2798 tbl 04
CAPACITANCE
Symbol
TRUTH TABLE
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions Typ.
Unit
Mode
CS
OE
WE
Output
Power
Standby
H
X
X
High-Z
Standby
H
DOUT
Active
H
High-Z
Active
DIN
Active
CIN
Input Capacitance
VIN = OV
35
CIN(C)
Input Capacitance (CS)
VIN = OV
8
pF
Read
L
L
COUT
Output Capacitance
VOUT = OV
35
pF
Read
L
H
2798 tbl 06
Write
L
X
L
NOTE:
1. This parameter is guaranteed by design, but not tested.
pF
2798 tbl 07
DC ELECTRICAL CHARACTERISTICS
(Vce = 5V +
- 10% TA = O°C to +70°C)
Symbol
Parameter
Test Conditions
Max.
Unit
-
4
4
JlA
JlA
Vee = Min., IOL = 2mA
-
0.4
V
Vec = Min., IOH = -1 mA
2.4
-
Vee = Max., CS:S VIL; f = fMAX,
Outputs Open
-
110
mA
Standby Supply Current
(TTL Levels)
CS ~ VIH, Vec = Max., f = fMAX,
Outputs Open
-
12
mA
Full Standby Supply Current
(CMOS Levels)
CS~ Vee 0.2V, VIN
or:s 0.2V
-
450
JlA
IILlI
Input Leakage
Vee = Max., VIN = GND to Vee
IILol
Output Leakage
Vec = Max., CS = VIH, VOUT = GND
to Vce
VOL
Output Low Voltage
VOH
Output High Voltage
Icc
Dynamic Operating Current
ISB
ISB1
~
Min.
Vec-0.2V
V
2798 tbl 05
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
VDR
Vee for Data Retention
leCDR
tCDR(2)
Data Retention Current
Chip Deselect to Data Retention Time
tR(2)
Operation Recovery Time
(TA= O°CTO +70°C)
Test Condition
CS~Vee 0.2V
VIN :S Vee 0.2Vor
VIN
NOTES:
1. tAe = Read Cycle Time
2. This parameter is guaranteed by design, but not tested.
~
0.2V
Min.
Max.
Unit
2.0
-
-
250
JlA
-
ns
0
tRe(1)
V
ns
2798 tbll 0
7.29
2
II
I
IDT7MP4058
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
GNDt03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
Input Timing Reference Levels
Output Reference Levels
Output Load
2798 tbl 08
+5V
+5V
48011
48011
DATAoUT--+---i
25511
DATAoUT--+---'
30pF'
25511
"Including scope and jig.
2798 drw03
2798 drw 04
Figure 1. Output Load
Figure 2. Output Load
(For tOll, tCHZ, tOHZ, tWHZ, tow and tCLl)
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = O°C to +70°C)
7MP4058LxxS
-70
Symbol
Parameter
Min.
-85
Max.
-100
Min.
Max.
Min.
-120
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
70
-
85
-
100
-
120
-
ns
tM
Address Access Time
70
-
85
-
100
-
120
ns
tACS
Chip Select Access Time
-
70
85
-
100
-
120
ns
tOE
tOHZ(1)
Output Enable to Output Valid
-
45
48
-
60
ns
-
30
-
50
Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
-
35
-
40
ns
0
-
0
-
ns
5
-
ns
-
40
-
43
-
45
-
50
ns
tOH
tPU(1)
Output Hold from Address Change
10
10
0
-
ns
0
-
10
0
-
10
Chip Select to Power-Up Time
-
tPO(1)
Chip Deselect to Power-Down Time
-
70
-
85
-
100
-
120
ns
85
-
100
-
120
-
90
5
5
-
90
38
40
0
-
-
ns
75
40
ns
tOLZ(1)
tCLZ(1)
tCHZ(1)
Output Disable to Output in High
5
0
5
33
-
0
5
0
-
ns
Write Cycle
tAW
Address Valid to End of Write
65
tcw
Chip Select to End of Write
65
tDW
Data to Write Time Overlap
35
-
tDH
Data Hold Time
0
-
0
-
tWR
tWHZ(1)
Write Recovery Time
0
-
0
30
-
33
tOW(1)
Output Active from End of Write
-
0
-
twc
Write Cycle Time
70
twp
Write Pulse Width
55
tAS
Address Set-up Time
Write Enable to Output in High
0
Z
0
NOTE:
65
2
82
80
85
0
0
35
-
100
100
45
0
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
2798tbl09
1. This parameter is guaranteed by design, but not tested.
7.29
3
IDT7MP4058
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VOR
~2V
2798 dew 05
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRG
tAA
--------~
tOLZ(5) - t - - - - - . . - j
1-4-----DATAoUT
tGLZ(5) - - - - - . . - j
----;--------------~
tAGS -------~
2798 dew 06
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
tRC
ADDRESS
tOH
tOH
fI
DATAoUT
2798 dew 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
1 4 - - - - - tCLZ(5) - - - - - - t
DATAoUT
-----l-------------<
tCHZ(5) - -
DATA VALID
tACS -------~
2798 dew 08
NOTES:
1. WE is High for Read Cycle
2. Device is continuously selected CS = VIL
3. Address valid prior to or coincident with CS transition low
4. OE= VIL
5. Transition is measured = 200mV from steady state. This parameter is guaranateed by design but not tested.
7.29
4
IDT7MP4058
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
twe
ADDRESS
OE
..
tAW
CS
~
..
twp(7)
lAs -- ..
WE
toW(6)
tWHZ(6)
(4)
DATAoUT
tOHZ(6)
DATA VALID
DATAIN
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
.
ADDRESS ~
"7
-
~
.
tAW
~
-
.
7~
twe
-
tAS
7 ~
~
..
..
tew
----------------------------~~~
tWR
:>~I------------
- - tDW~ 4 - tDH---
DATAIN
____
D_AT_A_V_A_L_ID____
2798 drw 10
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlay (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and Jig). This parameter is guaranteed by design but not tested.
7. If OE is low during a WE controlled write cycle, write pulse width must be the larger of twp or (tWHZ + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
7.29
5
IDT7MP4058
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
3.590
14
~
~I
0.185
~:~~TI I
l!l D !l l
II
;-*-- TTTTTTTTTTTTTTTTTTTTTTTT TTTTnTTTnr
---.II+- TYP.
!
-+l I+-
MAX.
0.007
0.013
0.100
FRONT VIEW
I
~
l!l~
Or• ~!llTiTTTTiiTTTiiTTTiiTTnTTTiiTTTiTT
D.OsO
BACK VIEW
SIDE VIEW
*
0.120
0.175
2798 drw 11
II
7.29
6
t;)®
IDT7M4068
IDT7MB4068
256K x8
BiCMOS/CMOS STATIC
RAM MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 2 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
256K x 8 static RAMs
• Fast access time: 10ns (max.)
• Low power consumption (L version)
- Active: 11 OmA (max.)
- CMOS Standby: 250)..lA (max.)
- Data Retention: 150)..lA (max.) Vee = 2V
• Surface mounted plastic packages on a 32-pin, 600 mil
ceramic or FR-4 DIP (Dual In-line Package) substrate
• Single 5V (±1 0%) power supply
• Inputs!outputs directly TTL compatible
The IDT7M4068!7MB4068 is a 2 megabit (256K x 8)
static RAM module constructed on a co-fired ceramic or
multilayer epoxy laminate (FR-4) substrate using two 1
Megabit static RAMs and a decoder. The IDT7MB4068 is
available with access times as fast as 10ns. For low power
applications, the IDT7M4068 version offers a data retention
current of 150)..lA and a standby current of 2501lA.
The IDT7M4068 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 2 megabits into the JEDEC DIP footprint. The
IDT7MB4068 likewise is packaged in a 32-pin FR-4 DIP
resulting in the same JEDEC footprint in a package 1.6
inches long and 0.6 inches wide.
All inputs and outputs of the IDT7M4068 and 7MB4068
are TIL compatible and operate from a single 5V supply.
Fully asynchronous circuitry requires no clocks or refresh for
operation and provides equal access and cycle times for
ease of use.
PIN CONFIGURATION(1)
FUNCTIONAL BLOCK DIAGRAM
NOTE 2
A16
A14
A12
Vcc
A1S
A17
WE
A13
As
Ag
All
OE
Ala
CS
1107
1/06
1/05
1/04
1/03
A7
A6
As
A4
A3
A2
Al
Ao
1/00
1/01
1/02
GND
ADDRESS
CS
256K
x8
RAM
WE
OE
1/0
2823 drw 02
PIN NAMES
2823 drw 01
DIP
1/00-7
Data Inputs/Outputs
TOP VIEW
AO-17
Addresses
NOTES:
1. For proper operation of the 7M4068LxxN module, Pin 1 must be connected to GND. For the 7MB4068xxP module, Pin 1 in a no connect.
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vee
Power
GND
Ground
2823 tbl 01
CEMOS is a trademark of Integrated Device Technology Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-7075/2
©t 992 Integrated Device Technology, Inc.
7.30
IDT7M4068, IDT7MB4068
256K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
CS
OE
WE
Output
Power
Symbol
Standby
H
X
X
High-Z
Standby
VTERM
Read
L
L
H
DOUT
Active
Read
L
H
H
High-Z
Terminal Voltage
with Respect
toGND
Active
TA
Write
L
X
L
DIN
Active
T81AS
Mode
2823 tbl 02
Rating
Commercial
Unit
-0.5 to +7.0
V
Operating
"Wmperature
o to +70
°C
fel~:,erature
-10 to +B5
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output CUrrent
50
rnA
Un er Bias
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
CIN
Input Capacitance
CIN{C)
Input Capacitance (CS)
COUT
Output Capacitance
Conditions
Typ.
Unit
= OV
VIN = OV
VOUT = OV
25
pF
B
pF
25
pF
VIN
2823 tbl 03
NOTE:
1. This parameter is guaranteed by design, but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5{l)
-
6
V
-
O.B
V
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
NOTE:
2823 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
GND
Vce
O°C to +70°C
Ov
5V± 10%
2823 tbl 06
2823tbl04
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V
± 10%, TA = O°C to +70°C)
7MB4068SxxP
7M4068LxxN
Symbol
Parameter
IILlI
Input Leakage
IILol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Dynamic Operating Current
Test Conditions
= Max., VIN = GND to Vee
Vee = Max., CS = VIH,
VOUT = GND to Vee
Vee = Min., IOL = 2mA{l),
IOL = BmA(2)
Vee = Min., IOH = -1 mA{l), ,.IOH =-4mA(2)
Vee = Max., CS::; VIL; f = fMAX,
Vee
25 - 55ns
Min.
Max.
Min.
Max.
-
2
10
2
-
-
0.4
2.4
10 - 20ns(3)
Min.
Max. Unit
10
-
10
JlA
JlA
-
0.4
-
0.4
V
-
2.4
-
2.4
-
V
-
110
-
300
-
400
rnA
-
6
-
120
-
120
rnA
-
0.25
-
20
-
BO
rnA
10
Outputs Open
= Max., f =fMAX,
IS8
Standby Supply Current
(TTL Levels)
CS~ VIH, Vee
Outputs Open
IS81
Full Standby Supply Current
(CMOS Levels)
CS~ Vee - 0.2V, VIN
or::; 0.2V
~
Vce· 0.2V
NOTES:
1. For 7M4068LxxN version only.
2. For 7MB4068SxxP, 7MB4068BxxP versions only.
3. Preliminary specifications only.
2823 tbl 07
7.30
2
IDT7M4068, IDT7MB4068
256K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS(3)
(TA = O°C to +70°C)
Max.
Symbol
Parameter
Test Condition
-
VOR
Vee for Data Retention
ICCDR
Data Retention Current
CS~
tCDR(2)
Chip Deselect to Data Retention Time
VIN::; Vee - 0.2V or
tR(2)
Operation Recovery Time
VIN ~ 0.2V
Vcc@2.0V
Min.
Vee - 0.2V
Unit
2.0
-
-
150
J.lA
0
-
ns
tRct')
V
ns
NOTES:
1. tRC = Read Cycle Time.
2. This parameter is guaranteed by design, but not tested.
3. For 7M4068LxxN version only.
2823tbl08
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VDR
~2V
VOR
2823 drw 03
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1-4
Output Load
2823 tbl 09
+5V
+5V
~
480n
DATAoUT--------~------~
255n
480n
. DATAoUT---------r------~
255n
30 pF*
5 pF*
2823 drw 04
2823 drw 05
Figure 1. Output Load
Figure 2. Output Load
(for tOlZ, tcHZ, tOHZ, tWHZ, tow and tClZ)
* Including scope and jig
7.30
3
IDT7M4068, IDT7MS4068
256K x 8 SICMOS/CMOS STATIC RAM MODULE
DATAoUT
Zo = 50n
COMMERCIAL TEMPERATURE RANGE
~50Q
!l.TAA
(Typical, ns)
4
1.5V
2823 drw 06
20 40 60 80100120140160180200
CAPACITANCE (pF)
Figure 3. Alternate Output Load
2823 drw 07
. Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
AC ELECTRICAL CHARACTERISTICS
(Vec = 5V +
- 10% , TA = O°C to +70°C)
7MB4068SxxP
_10(2)
Symbol
Read Cycle
Parameter
Min.
tAC
Read Cycle Time
10
tM
Address Access Time
tACS
Chip Select Access Time
tOE
tOHZ(1)
Output Enable to Output Valid
Output Disable to Output in High Z
-
tOLZ(1)
Output Enable to Output in Low Z
0
tCLZ(1)
Chip Select to Output in Low Z
tCHZ(1)
tOH
_17(2)
_15(2)
_12(2)
Max.
Min ..
10
10
12
-
15
-
17
12
. 12
-
6
-
8
ns
0
15
15
7
7
-
-
6
-
17
17
ns
-
-
3
-
7
-
ns
10
-
-
12
0
5
-
ns
3
-
3
10
-
-
15
12
-
3
-
17
14
0
14
14
10
0
0
6
0
3
3
Chip Deselect to Output in High Z
-
10
-
Output Hold from Address Change
3
-
3
10
10
-
12
10
-
6
-
Max.
Unit
Min.
-
Min.
Max.
Max.
ns
ns
ns
ns
ns
Write Cycle
twc
Write Cycle Time
twp
Write Pulse Width
tAS
Address Set·up Time
3
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
10
10
tDW
Data to Write Time Overlap
6
tDH
Data Hold Time
tWR
tWHZ(1)
Write Recovery Time
0
0
-
Write Enable to Output in High Z
-
8
-
toW(1)
Output Active from End of Write
2
-
2
3
12
12
8
0
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
-
8
-
15
15
10
0
0
2
-
10
-
0
-
ns
-
ns
-
ns
ns
-
ns
10
-
ns
ns
ns
ns
ns
2823tbll0
7.30
4
IDT7M4068, IDT7MB4068
256K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10%, TA = O°C to +70°C)
7MB4068SxxP
·20
Symbol
Read Cycle
Parameter
Min.
·30
·25
Max.
Min.
Max.
Min.
·35
Max.
Min.
Max. Unit
tRC
Read Cycle Time
20
-
25
-
30
-
35
-
ns
tAA
Address Access Time
20
ns
30
-
35
Chip Select Access Time
35
ns
Output Enable to Output Valid
-
30
tOE
tOHZ(1)
-
25
tACS
-
15
-
15
ns
12
-
15
ns
0
-
0
ns
5
-
5
20
ns
-
ns
tOLZ(1)
tCLZ(1)
tCHZ(1)
Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High
20
10
10
0
-
0
5
-
5
-
10
-
25
12
12
14
tOH
tPU(1)
Output Hold from Address Change
5
-
5
-
Chip Select to Power·Up Time
0
-
0
tPO(1)
Chip Deselect to Power· Down Time
-
12
-
25
-
25
-
16
-
ns
5
-
5
0
-
0
-
30
-
35
ns
-
30
35
-
ns
0
25
-
30
-
ns
20
-
-
20
-
25
30
-
17
0
-
0
0
-
ns
15
-
-
15
18
-
20
ns
0
-
ns
Write Cycle
twc
Write Cycle Time
20
twp
Write Pulse Width
15
tAS
Address Set-up Time
0
tAW
Address Valid to End of Write
16
tcw
Chip Select to End of Write
15
tow
Data to Write Time Overlap
12
tOH
Data Hold Time
0
tWR
tWHZ(1)
Write Recovery Time
0
-
Write Enable to Output in High Z
-
13
toW(1)
Output Active from End of Write
0
17
0
0
-
NOTE:
1. This parameter is guaranteed by design, but not tested.
20
0
0
-
25
0
20
0
0
-
ns
ns
ns
ns
ns
ns
2823 tbl11
7.30
5
ID17M4068, ID17MB4068
256K x 8 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = O°C to +70°C )
7MB4068SxxP
·45
Symbol
Parameter
Min.
7M4068LxxN
·60(2)
·55
Max.
Min.
Max.
Min.
Max.
·65(2)
Min.
·70
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
45
-
55
-
65
-
65
-
70
-
tAA
Address Access Time
-
45
55
ns
45
55
65
-
70
70
ns
tOE
tOHZ(1)
Output Enable to Output Valid
25
-
30
Output Disable to Output in High Z
-
-
65
Chip Select Access Time
-
60
tACS
-
20
-
20
tOLZ(1)
Output Enable to Output in Low Z
a
a
tCLZ(1)
Chip Select to Output in Low Z
5
-
tCHZ(1)
Chip Deselect to Output in High Z
-
20
tOH
tPU(1)
Output Hold from Address Change
5
-
5
Chip Select to Power-Up Time
a
-
tPO(1)
Chip Deselect to Power-Down Time
-
60
ns
-
30
-
35
-
45
ns
25
25
-
30
ns
3
-
5
-
ns
5
-
5
-
a
5
-
5
-
ns
-
25
-
25
-
25
40
ns
10
-
10
ns
a
-
10
a
-
a
-
45
-
55
-
65
-
65
-
55
-
65
-
65
45
50
-
55
a
-
a
-
-
ns
-
70
ns
-
70
ns
65
-
65
65
-
65
-
30
-
35
-
ns
a
a
-
-
ns
30
ns
0
Write Cycle
twc
Write Cycle Time
45
twp
Write Pulse Width
35
tAS
Address Set-up Time
a
tAW
Address Valid to End of Write
40
Chip Select to End of Write
40
-
50
tcw
tow
Data to Write Time Overlap
25
-
25
tOH
Data Hold Time
Write Recovery Time
-
0
tWR
a
a
a
-
a
a
-
a
a
tWHZ(1)
Write Enable to Output in High Z
-
25
-
25
-
25
-
25
-
toW(1)
Output Active from End of Write
a
-
a
-
a
-
a
-
a
50
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
-
60
-
30
60
55
a
a
-
ns
ns
ns
ns
ns
ns
28231bl12
•
7.30
6
IDTIM4068, IDTIMB4068
256K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = O°C to +70°C)
7M4068LxxN
·100
·85
Symbol"
Read Cycle
Parameter
Min.
Max.
Min.
·120
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
85
-
100
-
120
-
ns
tM
Address Access Time
85
-
100
-
120
ns
tACS
Chip Select Access Time
85
120
ns
Output Enable to Output Valid
48
60
ns
tOHZ(1)
Output Disable to Output in High Z
-
33
-
100
tOE
-
tOLZ(1)
Output Enable to Output in Low Z
0
-
tCLZ(1)
Chip Select to Output in Low Z
5
-
-
tCHZ(1)
Chip Deselect to Output in High Z
-
43
-
45
tOH
tpu(1)
Output Hold from Address Change
10
10
Chip Select to Power-Up Time
0
-
tPO(1)
Chip Deselect to Power-Down Time
-
85
50
-
40
ns
ns
5
-
-
50
ns
-
10
-
ns
-
100
-
120
ns
120
-
ns
90
-
ns
5
ns
45
-
0
-
ns
0
5
0
35
-
-
0
0
ns
ns
Write Cycle
twc
Write Cycle Time
85
Write Pulse Width
65
-
100
twp
tAS
Address Set-up Time
2
-
5
tAW
Address Valid to End of Write
82
90
tcw
Chip Select to End of Write
80
-
tow
Data to Write Time Overlap
38
-
40
tDH
Data Hold Time
tWR
Write Recovery Time
0
-
0
-
0
-
ns
tWHZ(1)
Write Enable to Output in High Z
-
33
-
35
-
40
ns
toW(1)
Output Active from End of Write
-
0
-
0
-
ns
0
0
NOTE:
1. This parameter is guaranteed by design, but not tested.
-'-
75
85
0
100
100
ns
ns
ns
2823 tbl13
7.30
7
IDTIM4068, IDTIMB4068
256K x 8 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~-------------------tRC
ADDRESS
DATAoUT
----------------------------------<
2823 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
f4---------------------- tRC
f4-----------------f4----------tOH tAA
--------~~
DATAoUT
2823 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
t
cs~_ _ _ _
~fooIC===~~~~~_t_C_LZ_(5_)==_t-A_C-S~~~~~:"kxx*"
DATAoUT _ _ _ _
teHz (5)
1r2823 drw 10
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. DE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.30
8
IDT7M4068, IDT7MB4068
256K x 8 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
ADDRESS
twe
K
)
)
K
./ ~
OE
tAW
CS
~
"
/~
twp (7)
~tAS
~'"
k-tWHZ
tOHZ (6)
DATAoUT
(4)
tWR_
It'
/
(6) .....
to HZ (6)
tow (6)
~
"
.~
./
I'
tDH
(4)
)
I-
tDW_
1/
DATAIN
r
DATA VALID
"
/
2823 dlW 11
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
twe
ADDRESS
/
) "-
)K
tAW
CS
~tAS
~
/
V
tew
tWR
WE
DATAIN
---..:(
tow
II I •
DATA VALID
tDH
3>1--2823 dlW 12
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, 110 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW) to allow the 110 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7.30
9
IDT7M4068, IDT7MB4068
256K x 8 BICMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7M4068LxxN
...1..§gQ..
1.710
I ,- - ,-,
14
0.580
D.6OO
,~,
_I
--~
~~: ;~ __ _~: ~~:
TOP VIEW
,0.405
,
Pin1
MAX.
;I~"Imill jiIIIIIII~
~r' 1-"'1+, "'11.,
I
0.035
0.065
I
I
0.015
0.025
0.100
TYP.
0.590
0.620
~
I
I
I'" -~I
0.007 . . . j.-
L-0.125
0.175
I
0.013
SIDE VIEW
BOTTOM VIEW
2823 drw 13
7MB4068SxxP
II
TOP VIEW
A~.;n~'nmnfm,,,ian'~II~: f~~O
/ ~I,"I~ "'1 ~
Pin 1
0.035
0.065
0.015
0.025
0.100
TYP.
l-0.120
0.175
0.007
0.013
n
14
1__
~I
0.590
0.620
. . .~
SIDE VIEW
2823 drw 14
BOTTOM VIEW
7.30
10
G®
256Kx8
CMOS STATIC RAM MODULE
PRELIMINARY
IDT7M4068
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 2 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
256K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: 700llA (max.)
- Data Retention: 400llA (max.) Vee = 2V
• Surface mounted LCCs (Ieadless chip carriers) on a 32pin, 600 mil ceramic DIP substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
The IDT7M4068 is a 2 megabit (256K x 8) CMOS static
RAM module constructed on a co-fired ceramic substrate
using two 1 Megabit static RAMs and a decoder. The
IDT7M4068 is available with access times as fast as 17ns.
For low power applications, the IDT7M4068 version offers a
data retention current of 400llA and a standby current of
7001lA.
The IDT7M4068 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 2 megabits into the JEDEC DIP footprint.
All inputs and outputs of the IDT7M4068 are TTL compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
All IDT military module semiconductor components are
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
CS
256K x 8
RAM
WE
DE
2824 drw 01
I/O
CEMOS is a trademark of Integrated Device Technology Inc.
APRIL 1992
MILITARY TEMPERATURE RANGE
DSC·707611
©1992 Integrated Device Technology, Inc.
7.31
ID17M4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PIN NAMES
PIN CONFIGURATION(1)
Vee
A1S
A17
WE
A13
As
A9
All
OE
Ala
CS
1/07
1/06
1/05
1/04
1/03
NOTE 2
A16
A14
A12
A7
A6
As
A4
A3
A2
Al
Ao
1/00
1/01
1/02
GND
1/00-7
Data Inputs/Outputs
AO-17
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vcc
Power
GND
Ground
2824 tbl 01
2824 drw 02
DIP
TOP VIEW
NOTE:
1. For proper operation of the module, Pin 1 must be connected to GND.
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
Mode
CS
OE
WE
Output
Power
Symbol
Military
Unit
Standby
H
X
X
High-Z
Standby
VTERM
-0.5 to +7.0
V
Read
L
L
H
DOUT
Active
Terminal Voltage
with Respect
to GND
TA
Operating
Temperature
-55 to +125
°C
TSIAS
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to +160
°C
lOUT
DC Output Current
50
rnA
Read
L
H
H
High-Z
Active
Write
L
X
L
DIN
Active
2824tbl02
CAPACITANCE(1) (TA =
Symbol
+25°C, f = 1.0MHz)
Parameter
CIN
Input Capacitance
CIN(C)
Input Capacitance (CS)
COUT
Output Capacitance
Conditions
Typ.
VIN
= OV
= OV
VOUT = OV
25
pF
VIN
10
pF
25
pF
NOTE:
1. This parameter is guaranteed by design, but not tested.
Unit
2824 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
-
6
V
0.8
V
Rating
NOTE:
2824 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5V± 10%
2824 tbl 06
2824 tbl 05
7.31
2
II
IDT7M4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Vce = 5V ± 10%, TA = -55°C to + 125°C)
7M4068SxxCB 7M4068LxxCB
Symbol
17ns-55ns
Test Conditions
Parameter
Min.
IILlI
Input Leakage
IILol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Dynamic Operating Current
= Max., VIN = GND to Vee
Vee = Max., CS = VIH,
VOUT = GND to Vee
Vee = Min., IOL = 2mA(1),
IOL = 8mA(2)
Vee = Min., IOH = -1 mA(l),
IOH = -4mA(2)
Vee = Max., CS~ VIL; f = fMAX,
Vee
Outputs Open
= Max., f = fMAX,
60ns-120ns
Max.
Min.
Max.
Unit
-
10
10
~
10
-
10
~
-
0.4
-
0.4
V
2.4
-
2.4
-
V
-
240
-
110
mA
-
60
-
6
mA
mA
158
Standby Supply Current
(TTL Levels)
CS;:: VIH, Vee
Outputs Open
1581
Full Standby Supply Current
(CMOS Levels)
CS;:: Vee - 0.2V, VIN;:: Vee - 0.2V
or ~ 0.2V
-
30
-
2
VerY Low Power Version(3)
-
30
-
0.7
NOTES:
1. For 60ns-120ns versions only.
2. For 17ns-55ns versions only.
3. L version only.
mA
2824tbl07
DATA RETENTION CHARACTERISTICS(5)
(TA = -55°C to +125°C)
Symbol
Parameter
Test Condition
-
VDA
Vee for Data Retention
IceDA
Data Retention Current
CS;:: Vee - 0.2V
tCDA(3)
Chip Deselect to Data Retention Time
VIN
tA(3)
Operation Recovery Time
VIN;:: 0.2V
~
Vee - 0.2V or
Min.
Max.
Vcc@2.0V
Unit
2.0
-
-
1(4)
mA
-
ns
0
tRe(2)
V
ns
NOTES:
1. Vee = 2V, TA = +25°C.
2. tRe = Read Cycle Time.
3. This parameter is guaranteed by design, but not tested.
4. For 60ns-120ns versions, ICCDR=400j,tA.
5. L version only.
2824 tbl 08
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VDA;:: 2V
VDA
2824 drw 03
7.31
3
IDTIM406a
256K x a CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
2824 tbl 09
+5V
+5V
480n
480n
DATAoUT - . . . - -....
DATAoUT---.-----.
255n
255n
2824drw 05
Figure 1. Output Load
2824 drw 04
Figure 2. Output Load
(for tOlZ, tCHZ, tOHZ, tWHZ, tow and tClZ)
• Including scope and jig
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = O°C to +70°C)
7M4068SxxCB,7M4068LxxCB
_17(3)
Symbol
Parameter
Min.
_20(3)
Max.
Min.
Max.
Min.
-25
Max.
-30
Min.
Max.
-35
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
17
-
20
-
25
-
30
-
35
-
ns
tAA
Address Access Time
-
17
20
-
25
30
ns
-
25
35
ns
10
12
15
-
35
20
-
15
ns
8
-
12
-
12
-
15
ns
0
-
0
-
-
ns
5
-
5
-
tACS
Chip Select Access Time
Output Enable to Output Valid
-
17
tOE
8
-
tOHZ(1)
Output Disable to Output in High Z
-
7
-
tOLZ(1)
Output Enable to Output in Low Z
0
-
tCLZ(1)
Chip Select to Output in Low Z
5
-
tCHZ(1)
Chip Deselect to Output in High Z
-
0
-
5
-
12
-
13
-
30
14
-
16
0
5
-
-
ns
20
ns
-
ns
tOH
Output Hold from Address Change
1
-
3
-
3
-
3
tPU(1)
Chip Select to Power-Up Time
0
-
0
-
0
-
0
-
tpo(1)
Chip Deselect to Power-Down Time
-
17
-
20
-
25
-
30
-
35
ns
-
25
-
30
35
20
-
3
-
-
ns
17
-
0
-
0
25
-
30
25
-
30
17
-
20
15
-
3
0
ns
Write Cycle
twe
Write Cycle Time
17
-
20
twp
Write Pulse Width
14
Address Set-up Time
-
15
tAS(2)
tAW
Address Valid to End of Write
-
18
tew
Chip Select to End of Write
17
18
tow
tDH(2)
Data to Write Time Overlap
10
Data Hold Time
0
tWR(2)
Write Recovery Time
0
-
tWHZ(1)
Write Enable to Output in High Z
-
10
toW(1)
Output Active from End of Write
2
-
2
3
17(4)
3
0
-
0
-
12
20
0
-
--
0
-
13
-
15
-
2
-
NOTES:
1.
2.
3.
4.
20
15
0
0
5
-
25
0
0
5
ns
-
ns
-
ns
ns
ns
ns
ns
15
ns
-
ns
2824 tbll0
This parameter is guaranteed by design, but not tested.
tAS=Ons for es controlled write cycles. toH, tWR= 3ns for WE controlled write cycles.
Preliminary specifications only.
tAW=14ns for es controlled write cycles.
7.31
4
FI
IDT7M4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C)
7M4068SxxCB, 7M4068LxxCB
-45
Parameter
Symbol
Min.
I
-55
Max.
Min.
Max.
-60\")
Min.
Max.
I
-65'''}
Min.
-70
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
45
-
55
-
65
-
65
-
70
-
ns
tAA
Address Access Time
toE
Output Enable to Output Valid
55
55
30
-
60
60
30
25
-
65
65
35
25
70
70
45
30
ns
5
5
-
5
5
3
5
-
5
5
-
0
5
-
ns
-
20
-
20
-
25
-
Output Hold from Address Change
5
10
Chip Select to Power-Up Time
0
0
-
10
tPU(1)
-
25
-
-
tOH
5
0
-
0
tPO(1)
Chip Deselect to Power-Down Time
-
45
-
55
-
65
0
-
65
-
40
10
70
ns
tCHZ(1)
Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
-
-
tOHZ(1)
-
ns
Chip Select Access Time
45
45
25
20
-
tACS
-
45
35
-
55
45
5
-
65
-
-
70
55
0
65
65
35
0
0
0
-
ns
-
ns
tOLZ(1)
tCLZ(1)
Output Disable to Output in High
20
-
-
-
-
ns
ns
ns
ns
ns
ns
Write Cycle
twc
Write Cycle Time
twp
Write Pulse Width
tAS
Address Set-up Time
tAW
Address Valid to End of Write
tcw
Chip Select to End of Write
5
40
40
tDW
Data to Write Time Overlap
tDH
Data Hold Time
20
0(2)
tWA
Write Recovery Time
0(2)
tWHZ(1)
Write Enable to Output in High
tow(1)
Output Active from End of Write
Z
5
0
-
65
55
0
65
65
30
0
0
50
0
0(2)
-
15
-
20
-
25
-
25
-
5
-
0
-
0
-
50
50
20
0(2)
NOTES:
60
60
30
0
-
-
-
30
-
ns
ns
ns
ns
ns
ns
ns
ns
2824 tblll
1. This parameter is guaranteed by design. but not tested.
2. IAS=Ons for CS controlled write cycles. tDH. twA= 5ns for WE controlled write cycles.
3. Preliminary specifications only.
7.31
5
IDTIM4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10% TA = -55°C to + 125°C)
7M4068SxxCB, 7M4068LxxCB
-100
-85
Symbol
Parameter
Min.
Max.
Min.
-120
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
85
-
100
-
120
-
ns
tAA
Address Access Time
-
-
-
-
120
120
ns
Chip Select Access Time
100
100
-
tACS
85
85
tOE
Output Enable to Output Valid
-
48
-
50
60
ns
tOHZ(1)
Output Disable to Output in High Z
-
33
-
Output Enable to Output in Low Z
tCLZ(1)
Chip Select to Output in Low Z
0
5
-
0
5
40
-
ns
tOLZ(1)
35
-
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
43
-
ns
10
Chip Select to Power-Up Time
0
-
0
-
ns
tPU(1)
10
0
50
Output Hold from Address Change
10
-
tOH
tPO(1)
Chip Deselect to Power-Down Time
-
85
-
-
120
ns
120
90
5
-
ns
ns
35
0
-
40
ns
-
0
-
ns
45
-
100
-
0
5
ns
ns
ns
Write Cycle
twc
Write Cycle Time
85
-
100
twp
Write Pulse Width
-
tAS
Address Set-up Time
75
5
tAW
Address Valid to End of Write
65
2
82
tcw
Chip Select to End of Write
tow
Data to Write Time Overlap
tOH
Data Hold Time
80
38
0
tWR
Write Recovery Time
0
-
tWHZ(1)
Write Enable to Output in High Z
-
33
0
-
toW(1)
Output Active from End of Write
0
-
0
NOTE:
1. This parameter is guaranteed by design, but not tested.
-
90
85
40
0
-
100
100
45
0
n:;
n:;
ns
ns
ns
ns
2824 tbl12
II
7.31
6
IDT7M4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~--------------tRC--------------~
ADDRESS
DATAoUT - - - - - - - - - - - - - - - ( .
2824 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~----------------tRC----------------~
ADDRESS
14------------- tAA
------------~
~-------tOH--------~
DATA OUT
2824 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
cs1:=c~---=-=-~t--CLZ-(--5)=-t-A-CS-=-~-.~--.-'----('CHZ(5 11
DATAoUT--------------~-
2824 drw 08
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. DE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guranateed by design, but not tested.
7.31
7
IDT7M4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
ADDRESS
twe
=>(
)K
/'
tAW
~,
/'f'
twp(7)
4----tAS
tWA-
~,
/'
tOHZ(6)
+--tWHZ(6)-+
tOHZ(6)
DATA OUT
(4)
tOW(6)
V
"
/
tOH
tow-~
DATA IN
I'
DATA VALID
~
(4)
)~
"
2824 drw 09
/
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3,5)
twe
ADDRESS
=> (
)(
tAW
)1'
__ lAS " }
tew
DATAIN __________________________
tWA
~~
tow
.. hi
II
tOH
DATA VALID
2824 drw 10
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled wri~cle, write pulse ((twp) > twHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required
tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.
7.31
8
IDTIM4068
256K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PACKAGE DIMENSIONS
1.680
1I0Il41--_1.720 --~~I
PIN 1
F1
j4
I
0.035
0.065
0.015
0.025
0.100
TYP.
0.007
0.013
-4-
~ 0.590
0.620
END VIEW
SIDE VIEW
I::::~::::~::::~::I
2824 drw 11
BOTTOM VIEW
7.31
9
~®
256K x 8
CMOS STATIC RAM MODULE
IDT7MP4034
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density separate 1/0, 2 megabit CMOS static RAM
module
• Fast access time: 1Ons (max.)
• Low profile 42-pin ZIP (Zig-zag In-line vertical Package)
• Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum
noise immunity
• Inputsloutputs directly TTL compatible
The IDT7MP4034 is a separate 1/0, 256K x 8 CMOS static
RAM module constructed on an epoxy laminate (FR-4)
substrate using 8 256K x 1 static RAMs in plastic SOJ
packages. Availability of two chip select lines (one for each
group of four RAMs) provides nibble access and allows the
user to configure the memory into a 256K x 8 or a 512K x 4
organization. The IDT7MP4034 is available with access times
as fast as 1Ons with minimal power consumption.
The IDT7MP4034 is packaged in a 42-pin FR-4 ZIP (Zigzag In-line vertical Package). The memory configuration
results in a package 2.65 inches long and 0.35 inches wide.
At only 0.5 inches high, this low profile package is ideal for high
performance systems with minimum board spacing.
All inputs and outputs of the IDT7MP4034 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for
operation.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
CSo
GNO 1
010 3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
Oil 5
012 7
013 9
Ao 11
A2 13
A4 15
As 17
CSJ 19
WE 21
As 23
AlO 25
A12 27
A14 29
A1S 31
014 33
015 35
Dis 37
, 017 39
Vee 41
ZIP
TOP VIEW
01(0-3)
Vee
000
001
002
003
Al
A3
As
A7
GNO
CSl
CSl
01(4,7)
256Kx 8
RAM
II
A9
All
A13
00(0-3)
00(4-7)
A1S
2745 drw 02
A17
004
005
PIN NAMES
DOs
007
GNO
010-7
2745 drw 01
Oata Inputs
000-7
Oata Outputs
AO-17
Address Inputs
CSo-l
Chip Selects
WE
Write Enable
Vee
Power
GNO
Ground
2745 tbl 01
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC·7055/3
lOt 992 Integrated Device Technology. Inc.
7.32
IDTIMP4034 (256K x 8)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VTERM
Rating
Terminal Voltage with
Respect to GND
RECOMMENDED DCOPERATING CONDITIONS
Value
Unit
-0.5 to +7.0
V
o to +70
°C
Temperature Under Bias
-10 to +S5
°C
Storage Temperature
-55 to +125
°C
TA
Operating Temperature
TSIAS
TSTG
lOUT
DC Output Current
50
Symbol
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
6.0
V
Supply Voltage
GND
Ground
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
-
O.S
V
NOTE:
2745 tbl 04
1. VIL = -3.0V for pulse width less than 20ns.
mA
NOTE:
Parameter
Vee
2745 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI NGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient Temperature
2745 tbl 05
TRUTH TABLE
CAPACITANCE (TA = +25°C. f = 1.0MHz)
Mode
CS
WE
Standby
H
X
Read
L
Write
L
Output
Parameter(1)
Power
Symbol
Conditions
Typ.
Unit
High-Z
Standby
CIN(D)
VIN = OV
15
pF
H
DATAoUT
Active
Input Capacitance
(Data)
L
DATAIN
Active
CIN(A)
Input Capacitance
(Address and Control)
VIN
= OV
92
pF
COUT
Output Capacitance
2745 tbl 03
VOUT
= OV
NOTE:
15
pF
2745 tbl 06
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS(1)
(Vee = 5V ± 10%. TA = O°C TO +70°C)
Max.
Unit
IILlI
Input Leakage
(Address and Control)
Vee = Max.
VIN = GND to Vee
-
40
j.tA
Ilul
Input Leakage
(Data)
Vee = Max.
VIN = GND to Vee
-
10
j.tA
IILol
Output Leakage
Vee = Max.
CS = VIH. VOUT = GND to Vee
-
10
j.tA
VOL
Output Low Voltage
Vee = Min., IOL = SmA
-
0.4
V
VOH
Output High Voltage
Vee = Min., IOH = -4mA
2.4
-
Symbol
Parameter
Test Conditions
Min.
V
2745 tbl 07
Test Conditions
10-12ns
15-45ns
Max.
Max.
Unit
lee
Dynamic Operating Current
CS = VIL, Output Open
Vee =Max., f = fMAX
1520
1200
mA
Iss
Standby Supply Current
CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX
560
320
mA
ISS1
Full Standby Supply Current
CS~ Vee - 0.2V,
VIN > Vee - 0.2V or < 0.2V, f
240
240
mA
Symbol
Parameter
NOTE:
=0
2745tbl08
1. 10, 12, 15, and 17ns are preliminary specifications only.
7.32
2
IDT7MP4034 (256K x 6)
CMOS STAT1C RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2745 tbl 09
+5V
+5V
480n
480n
---e-----_
DOUT
255n
DOUT - -....- - - - _
30pF *
255n
5pF *
2745 drw 03
Figure 1. Output Load
2745 drw 04
Figure 2. Output Load
(for tcHZ, tClZ, tow and tWHZ)
• Including scope and jig.
AC ELECTRICAL CHARACTERISTICS(2)
Vce = 5.0V + 10% TA = O°C to +70°C)
7MP4034SxxZ
-10
Symbol
-12
I
Parameter
-15
I
-17
I
I
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
READ CYCLE
tRC
Read Cycle Time
10
-
12
-
15
-
17
-
tAA
Address Access Time
10
-
12
ns
10
-
12
15
-
17
Chip Select Access Time
-
15
tACS
-
17
ns
-
3
-
3
-
3
-
ns
10
-
10
-
10
-
10
ns
-
3
-
3
-
3
-
0
-
ns
0
-
10
-
12
-
15
-
17
ns
-
12
15
-
17
12
15
13
15
0
-
-
0
-
ns
9
ns
tCLZ(1)
Chip Select to Output in Low Z
tCHZ (1)
Chip Deselect to Output in High Z
tOH
Output Hold from Address Change
3
tpu (1)
Chip Select to Power Up Time
0
tPD
Chip Deselect to Power Down Time
(1)
3
-
0
ns
•
ns
WRITE CYCLE
tAW
Address Valid to End of Write
10
-
10
tAS
Address Set-up Time
0
0
twp
Write Pulse Width
10
10
tWR
Write Recovery Time
0
-
-
0
-
tWHZ(1)
Write Enable to Output in High Z
5
-
5
twc
Write Cycle Time
10
tcw
Chip Select to End of Write
10
-
13
13
0
-
8
15
0
-
ns
ns
ns
ns
ns
tDW
Data to Write Time Overlap
8
-
11
0
0
-
0
-
ns
0
-
10
Data Hold from Write Time
-
10
tDH
tow (1)
Output Active from End of Write
0
-
0
-
0
-
0
-
ns
NOTES:
1. This parameter is guaranteed by design but not tested.
2. 10,12,15, and 17ns are preliminary specifications only.
ns
2745tbll0
7.32
3
IDTIMP4034 (256K x 8)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vee = 5.0V + 10%, TA = O°C to +70°C)
·20
Symbol
Parameter
·25
Min.
I Max.
20
20
25
-
-
25
25
I
Min. Max.
I ·35
I Min. IMax.
·45
Min.
IMax.
Unit
READ CYCLE
45
-
ns
-
45
45
ns
-
35
35
-
5
-
5
-
ns
-
13
-
-
25
ns
-
3
-
3
20
-
3
-
ns
0
-
0
-
0
-
0
-
ns
-
20
-
25
-
35
-
45
ns
-
-
35
30
30
0
30
0
-
45
40
40
0
40
0
-
ns
-
ns
-
ns
-
ns
-
25
22
22
0
22
0
25
-
ns
0
ns,
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
20
-
tClZ (1)
Chip Select to Output in Low Z
3
-
5
tCHZ (1)
Chip Deselect to Output in High Z
-
10
toH
Output Hold from Address Change
3
tpu (1)
Chip Select to Power Up Time
tpo (1)
Chip Deselect to Power Down Time
35
-
ns
WRITE CYCLE
twc
Write Cycle Time
tcw
Chip Select to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
20
17
17
0
17
0
tWHZ (1)
Write Enable to Output in High Z
-
10
-
13
tow
Data to Write Time Overlap
tOH
Data Hold from Write Time
13
0
-
15
0
tow (1)
Output Active from End of Write
-
0
-
-
-
-
-
-
20
-
20
0
-
25
0
0
-
C
-
ns
ns
ns
ns
2745 tblll
NOTE:
1. This parameter is guaranteed by design but not tested.
7.32
4
IDTIMP4034 (256K x 8)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~----------------tRC----------------~~
ADD,RESS
~
.
____________________________________
~--~--------~tAA----------~.~1
CS
~----tOH
1-4--------tACS
~----tCLZ (4)
-----------------------------<
------~
DATAoUT
2745 drw05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2)
~----------------tRc------------------1~
~:t~~-=-~==tO=H~tA--A-=-~-=--=-bk--,-------~·-,=====,....-~__-_-
ADDRESS·
=1---====
_--t__
O--"
DATAoUT
2745 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3)
"I: tA=bk
_____________'_~,-_______tC_L_Z_(4_J
C
-'
DATAoUT
-
.
2745 drw 07
NOTES:
1, WE is high for read cycle,
2. Device is continuously selected, CS = V,L.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state with 5pF load (including scope and jig). This parameter is guaranteed by design but not tested.
7.32
5
II
IDT7MP4034 (256K x 8)
CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1,2, 3) (WE CONTROLLED TIMING)
twe
ADDRESS
)K
)(
tAW
"- I'\..
//
twp
tAS
tWR~
'~
/
/
~tWHZ(5)~
4-tOW(5)~
'I
I'\.
DATAoUT
DATAIN------------------------------------~~-tD-W----·D-':-T-A--VA--LI-~-DH---------~~)~~I-------2745 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1,2,3, 4) (CS CONTROLLED TIMING)
twc
ADDRESS
)(
)(
tAW
1
tAS
//
tew
I
tWR~
/
/
DATAIN ____________________________________-k~-tD-W----·D-':-T-A--VA--LI-:_H_-_-___
-~~)~I-------NOTES:
2745 drw 09
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (tcw or twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. If the CS low transition occurs simultaneous with or after the WE low transition, the outputs remain in the high impedance state.
5. Transition is measured ±200mV from steady state with SpF load (including scope and jig). This parameter is guaranteed by design but not tested.
PACKAGE DIMENSIONS
I"
~~
Pin 1
2.630
2.650
~I
~ ~100~15~ ~~o
Typ.
0.025
~lr-~~~~
L
I
0.100
TYP.
SIDE VIEW
0.190
FRONT VIEW
2745 drw 10
7.32
6
G®
IDT71 M024
IDT71 M025
128K x 8
CMOS STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 1 megabit (128K x 8) static RAM
• Dual Chip Select Version (IOT71 M024)
Single Chip Select Version (IOT71 M025)
• Fast access time:
- commercial: 55ns (max.)
- military: 60ns (max.)
• Low power consumption
- active: 1 OOmA (max.)
- CMOS standby: 2mA (max.)
• Very low power version
- data retention: 50llA (max.) Vcc = 3V
- CMOS standby: 100ilA (max.)
• 32-pin ceramic sidebrazed DIP or ceramic leadless chip
carrier (LCC)
• Single 5V (±1 0%) power supply
• Inputs/outputs directly TTL compatible
The IOT71 M024/71 M025 is a 1 megabit (128K x 8) static
RAM packaged in a sidebrazed ceramic dual in-line package
(DIP) and a ceramic lead less chip carrier (LCC). The
IOT71 M024/71 M025 is available with access times as fast
as 55ns. For battery backup applications, a very low power
version is available, offering a commercial temperature data
retention current of 50llA with Vcc = 3V.
The IOT71 M024/71 M025 are packaged in JEOEC standard 600 mil 32-pin ceramic DIPs. The IOT71 M024 as comes
in a hermetic 400 mil by 820 mil LCC. For surface mount
applications, the proposed JEOEC standard 400 mil by 820
mil LCC is ideal.
All inputs and outputs of the IDT71 M024/71 M025 are TTL
compatible and operate from a single 5V supply. Fully
asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease
of use. All lOT military semiconductor components are
manufactured in compliance to the latest revision of MILSTD-883 Class 8, making them ideally suited for applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION(1)
128K x 8
RAM
1/0
2820 drw 01
NOTE:
1. For the IDT71 M024 version only.
PIN NAMES
1/00-7
Data Inputs/Outputs
AO-1B
Addresses
CS1, CS2
Chip Selects
WE
Write Enable
OE
Output Enable
N.C.
No Connect
Vcc
Power
GND
Ground
Vcc
NC
A16
A14
A12
A7
A6
As
A4
A3
A2
Al
Ao
1100
1101
1102
GND
A1S
CS2
WE
A13
AB
A9
All
DE
Ala
CSl
1/07
II0s
1105
1104
1/03
2820 drw02
DIP, LCC
TOP VIEW
NOTE:
1. For the IDT71 M024 version Pin 30=C52. ForthelDT71 M025 version Pin
30=N.C.
2820 tbl 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
DSC-7091/3
Vee - 0.2V or < 0.2V
Very Low Power Version(1)
-
2
-
2
rnA
-
100
-
350
NOTE:
1. For data retention version, please specify L power when ordering.
J.tA
2820 tbl07
7.33
2
IDT71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 and 2
Output Load
2820tbl08
+5 V
4800.
4800.
DATAoUT--------~------~
2550.
DATAoUT--------~------~
2550.
30 pF*
5 pF*
2820 drw 03
2820 drw 04
Figure 1. Output Load
Figure 2. Output Load
(for tOlZ, tCHZ, to HZ, tWHZ, tow and tClZ)
* Including scope and jig
DATA RETENTION CHARACTERISTICS(1)
to +70°C and -55°C to +125°C)
(TA = O°C
Comm. Military
Symbol
Parameter
Test Condition
-
V
2.2
-
V
~4.5V
-
0.8
0.8
V
VOR < 4.5V
-
0.2
0.2
V
50
300
IlA
-
50
200
IlA
-
-
ns
Vcc for Data Retention
VCSt
CS1 Input Voltage
VOI1~2.2V
VCS2
CS2 Input Voltage
VOR
Data Retention Current
CS2~
Vcc
~
0.2V,
VIN $ Vee - O.2V or VIN
Data Retention CLirrent
2.0
Vee = 3.0V, CS2 $ 0.2V or
CS1,
ICCOR2
Unit
-
-
VOR
ICCORl
Max.
Min.
Vec
= 2.0V, CS2 $
~
0.2V
0.2V or
CS1, CS2 ~ Vee - 0.2V,
VIN $ Vee - 0.2V or VIN
tPOS(2)
Power Down Set Up Time
tPOR(2)
Power Down Recovery Time
~
0.2V
0
tRC(3)
NOTES:
1. This option is only offered when ordering L power version.
2.. This parameter is guaranteed by design, but not tested.
3. tRC = Read Cycle Time.
ns
2820 tbl 09
7.33
3
IDT71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VCC
VOR ~2V
CS2
2820 drw05
AC ELECTRICAL CHARACTERISTICS
Vec = 5V + 10% TA = O°C to +70°C and -55°C to +125°C
71M024 or 71 M025
_60(2)
_65(2)
_55(2,3)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
-70
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
60
-
65
-
70
-
70
-
ns
tAA
Address Access Time
55
-
65
ns
60
-
65
70
ns
tACS2
Chip Select (CS2) Access Time
65
70
tOE
Output Enable to Output Valid
25
tOHZ(1)
Output Disable to Output in High
-
20
tOLZ(1)
Output Enable to Output in Low
Z
Z
-
-
70
Chip Select (CS1) Access Time
-
60
tACS1
3
-
3
5
-
Z
-
20
-
25
-
25
-
25
ns
10
10
10
-
10
ns
0
-
70
-
70
ns
55
60
30
25
5
tCLZ1,2(1)
Chip Select to Output in Low
tCHZ1,2(1)
Chip Deselect to Output in High
tOH
tPU(1)
Output Hold from Address Change
Chip Select to Power-Up Time
0
-
0
-
tPO(1)
Chip Deselect to Power-Down Time
-
60
-
65
-
Z
5
5
0
35
25
-
5
5
70
ns
35
ns
25
ns
-
ns
-
ns
ns
Write Cycle
twc
Write Cycle Time
60
-
65
-
70
-
70
-
ns
twp
Write Pulse Width
45
50
Address Valid to End of Write
55
60
tCW1
Chip Select (CS1) to End of Write
55
65
tCW2
Chip Select (CS2) to End of Write
55
-
-
ns
tAW
65
-
ns
tDW
Data to Write Time Overlap
25
30
Data Hold Time
0
tWR
Write Recovery Time
0
-
ns
tDH
-
55
Address Set-up Time
-
55
tAS
-
tWHZ(1)
Write Enable to Output in High
toW(1)
Output Active from End of Write
0
Z
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary ~pecification only.
3 Commercial temperature only.
0
60
60
30
-
0
20
-
-
0
0
25
-
0
65
65
65
30
0
0
0
25
-
0
65
a
0
0
ns
ns
ns
ns
ns
25
ns
-
ns
2820tbl10
7.33
4
ID171 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Vee = 5V + 10% T A = O°C to + 70°C and -55°C to + 125°C)
71M024
Parameter
Symbol
Read Cycle
·120
I
Min.
Max.
Min.
Max.
85
85
85
40
30
100
-
100
100
100
45
120
-
ns
-
ns
35
-
-
35
-
5
5
10
120
120
120
45
35
35
tRC
Read Cycle Time
85
tAA
Address Access Time
tACS1
Chip Select (CS1) Access Time
tACS2
Chip Select (CS2) Access Time
tOE
tOHZ(1)
Output Enable to Output Valid
-
tOLZ(1)
Output Enable to Output in Low Z
tCLZ1,2(1)
Chip Select to Output in Low Z
tCHZ1,2(1)
Chip Deselect to Output in High Z
tOH
tPU(1)
Output Hold from Address Change
tPO(1)
Output Disable to Output in High Z
or 71M025
·100
·85
-
-
5
5
-
30
Chip Select to Power-Up Time
10
0
-
5
5
10
0
Chip Deselect to Power-Down Time
-
85
-
-
Min.
-
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
a
-
100
-
120
ns
-
120
65
-
35
-
ns
Write Cycle
Write Recovery Time
85
60
0
70
70
70
35
0
0
-
100
65
0
75
75
75
40
0
0
Write Enable to Output in High Z
-
30
-
0
-
a
twc
Write Cycle Time
twp
Write Pulse Width
tAS
Address Set-up Time
tAW
Address Valid to End of Write
tCW1
Chip Select (CS1) to End of Write
tCW2
Chip Select (CS2) to End of Write
tow
Data to Write Time Overlap
tOH
Data Hold Time
tWR
tWHZ(1)
toW(1)
Output Active from End of Write
NOTE:
1. This parameter is guaranteed by design, but not tested.
-
-
-
-
-
a
75
75
75
40
a
a
a
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
35
-
ns
ns
2820tblll
•
7.33
5
I
10T71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~------------------tRC
ADDRESS
CS2
DATAoUT
----------------------------------~
2820 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
~---------
tOH
tAA
DATAoUT
2820 drw07
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS2 _____
DATAoUT
___"t-I_:=_-==-_-=-=-_-=~t-C_LZ~-(5_)-=-~tA_C=S====:.kx~
____ ltC_Hz_(_5)
2820 drw 08
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS1 = VIL, CS2 = VIH .
3. Address valid prior to or coincident with CS1 transition low, CS2 transition high.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.33
6
IDT71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
twc
ADDRESS
~(
~
)
K
./
~
tAw
~
CS2
-
./ ~
"
~
/'
twp
--tAS
(7)
~~
I-tWHZ
(6)
tOHZ
(4)
DATAoUT
~
tWR -
/ ~
(6)
.....
tow
_tOHZ
(6)
Lr
"
./
r
tDH
tDW
DATAIN
I"
(6)
--
)-
(4)
-
"
DATA VALID
./
2820 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS1, CS2 CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
~
"
tAW
~~
7
~
"/ ~
CS2
--tAS
DATAIN
)(
~
~
,
------------------c:[
•
3)1---tWR
tcw
tDW
-.1..DATA VALID
tDH
2820 drw 10
NOTES:
1. WE or CS1 must be high, or CS2 must be low during all address transitions.
2. A write occurs during the overlap (twp) of a low CS1, high CS2, and a low WE.
3. twR is measured from the earlier of CS1 or WE going high or CS2 going low to the end of the write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS1 low transition, CS2 high transition occur simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, twp must be greater than twHZ + tow to allow the I/O drivers to turn off and data to be placed on the bus for the required
tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.
7.33
7
10171 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
400 MIL BY 820 MIL LCC PACKAGE
0.392
0.060
0.090
:jJ:
0:458
~
0.100
SIDE VIEW
BOTTOM VIEW
BOTTOM VIEW
2820 drw 11
600 MIL DUAL IN-LINE PACKAGE
I....
0.580
"'D.616"
II
1.580
1.640
TOP VIEW
0.100
0.190
0.020
0.060
Pin 1
"I
i
~lllilllllllllll~
~~~~~~
I
0.040
0.060
I
. , '
0.015
D.023
I
0.100
SIDE VIEW
..MlliL.~
0.620
I
,....
0.125
0.175
0.008
o:D1"2
~I
....
I
~I
TYP.
2820 drw 12
7.33
8
G®
256KB/1MB/4MB
IDT79R4000 SECONDARY CACHE
MODULE BLOCK FAMILY
PRELIMINARY
IDT7MP6074
IDT7MP6084
IDT7MP6094
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed BiCEMOSTM/CEMOSTM secondary cache
module block constructed to support the IDT79R4000 CPU
• Available as a pin compatible family to build 256 kilobyte
(unified), 1 megabyte (unified) and 4 megabyte (unified or
split) secondary caches
• Zero wait-state operation
• Four word line size
• Operating frequencies to support 50MHz and 75MHz
IDT79R4000
• Available as a set of fou r identical high density 80 lead (goldplated fingers) SIMMs (Single In-Line Memory Modules)
• Surface mounted plastic components on a multilayer epoxy
laminate (FR-4) substrate
• Multiple ground pins and decoupling capacitors for maximum noise immunity
• TTL compatible II0s
• Single 5V (±10%) power supply
The IDT7MP6074 is a256 kilobyte IDT79R4000 secondary
cache module block constructed on a multilayer epoxy laminate substrate (FR-4), using 11 16K x 4 static RAMs and 2
IDT74FBT2827 drivers. The IDT7MP6084 is a 1 megabyte
IDT79R4000 secondary cache module block using 11 64K x
4 static RAMs, and the IDT7MP6094 is a 4 megabyte
IDT79R4000 secondary cache module block using 11 256K x
4 static RAMs. The IDT74FBT2827 has internal25W series
resistors and BiCEMOSTM II0s resulting in the fastest propagation times with minimal overshoot and ringing. Four identical cache module blocks comprise a full secondary cache.
The IDT7MP6074/84/94 support use in an IDT79R4000based system at speeds of 50MHz and 75MHz with zero waitstate operation. These Module support a four word line size.
For other line sizes, please consult factory.
All inputs and outputs of the IDT7MP6074/84/94 are TTLcompatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
FUNCTIONAL BLOCK DIAGRAM
A1-17
17 /
/
OE
74FBT2827
x2
TCS
DCS
f-
~
AH7
OE
CS
Ao
Ao
WE
WE
256K x 36
DATA
-
36
/
V
1/00-35
AH7
OE
CS
256K x 8
TAG
Ao
WE
8 ./
,;
TO-7
2833 drw 01
BiCEMOS and CEMOS are trademar1to
"I)
HIGH·Z
2835 drw07
NOTES:
1. DE Must be taken inactive at least as long as tOHZ + ts before the second rising clock edge of write cycle.
2. A·Data to be written to original input address.
B·Data to be written to original input address except Ao is now Ao.
C·Data to be written to original input address except A1 is now A1.
D·Data to be written to original input address except Ao and A1 are now Ao and A1.
3. If ADS goes low during a burst cycle, a new address will be loaded, and another burst cycle will be started.
4. If CS is taken inactive during a burst write cycle the burst counter will discontinue counting until the CS input again goes active. The timing of the CS input
for this control of the burst counter must satisfy setup and hold parameters ts and tHo CS timing is the same as any synchronous signal when used to block
writes or to stop the burst count sequence.
PACKAGE DIMENSIONS
I
4.240
~4'----------------------4.260-------------------~~
I
g!l
0.2:5
0.255
14----4- - 3 . 9 7 4
0.250
---..~
MAX
3.994
c=J~CJ CJ~CJ
J ,
PIN 1
0.390
0.410
-
0.250 TYP.
0.050
TYP.
FRONT VIEW
"."' .. ,,'"'''''''''''''''''''''' "
'"'
I
0.045
0.055
SIDE VIEW
,
.... ''''''.. ''''''''''' .... '''
BACK VIEW
PIN 1
7.38
2835 drw 08
6
t;)®
PRELIMINARY
IDT7MP6048
IDT7MP6068
IDT79R4000 FLEXI-CACHETM
DEVELOPMENT TOOL
Integrated Device Technology, Inc.
FEATURES:
• Hardware Development Tool for implementing various configurations of the secondary cache requirement for the
IDT79R4000 CPU
• Configurable in various cache sizes, number of words per
line size, and split vs. unified cache operation
• Move from prototype/development to production with no redesign by using pin compatible "production grade"
IDT79R4000 secondary cache modules
• Development module operating frequencies to support zero
wait-state 50MHz IDT79R4000 operation
• Four identical 80 lead gold-plated SIMMs (Single In-Line
Memory Modules) support each IDT79R4000 CPU
• Surface mounted plastic components on a multilayer epoxy
laminate (FR-4) substrate
• Multiple ground pins and decoupling capacitors for maximum noise immunity
• TTL compatible I/Os
• Single 5V (±10%) power supply
DESCRIPTION:
The IDT7MP6048/7MP6068 is a Hardware Development
Tool used for implementing various configurations of the
secondary cache requirement for the IDT79R4000 CPU. By
changing jumpers on the modules, the designer can easily
change certain characteristics (cache size, number of words
per line, and split vs. unified operation) of the secondary cache
in the lab. By running benchmarks on the actual system using
these various cache configurations, the secondary cache
which best optimizes system performance can be determined. This development tool gives you cache performance
benchmarks which are superior to benchmarks derived via
simulation.
Move from development to production without changing
the secondary cache footprint by choosing pin compatible
"production grade" IDT79R4000 secondary cache modules.
T~ese high performance, high density IDT modules are optimized to meet the customers' exact cache requirements
required for volume production of the system (please consult
the factory for more details).
The IDT7MP6048 is a 1 megabyte secondary cache module block (four identical modules builds a complete cache to
support each IDT79R4000 CPU) constructed on a mUltilayer,
epoxy laminate substrate (FR-4) using 11 64K x 4static RAMs
and FBT logic drivers while the IDT7MP6068 is a 4 megabyte
secondary cache module block using 11 256Kx 4 static RAMs
and FBT logic drivers. Extremely high speeds can be achieved
using high performance BiCEMOSTM IDT61 B298 or
(continued on page 2)
FUNCTIONAL BLOCK DIAGRAM(1)
P1-P6
A1-17
OE
TCS
DCS
-----
17/ ..
7
74FBT2827
x2
~-
I-
P8, P9
4:-
-..
a
~
Ao
WE
A1-17
A1-17
64K x36
OE
or
CS
256K x 36
DATA
Ao
.
WE
1
36y
.J1
1/00-35
~
OE
64K x 8
CS
256K x 8
TAG
Ao
or
WE
~~
8
""~
v
TO-7
2841 drw 01
NOTE:
1. ~he Da~a and Tag sizes shown on t~e block diagram are only for the case when the jumpers are in the default positions for the respective modules. These
sizes Will change according to the Jumper connections (see Jumper Connections on page 2).
BiCEMOS, CEMOS and FLEXI-CACHE are trademarks of Integrated Device Technology Inc.
APRIL 1992
COMMERCIAL TEMPERATURE RANGE
DSC-7093/-
©1992 Integrated Device Technology, Inc.
7.39
IDTIMP6048, 7MP6068 (DEVELOPMENT KIT)
IDTI9R4000 SECONDARY CACHE MODULES
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (continued from page 1)
IOT71 B028 static RAMs and IDT74FBT2827 drivers. The
FBT drivers have BiCEMOSTM II0s and internal 25Q series
output resistors resulting in the fastest propagation times with
minimal overshoots and ringing. Multiple GND pins and on-
board decoupling capacitors provide maximum noise immunity for this performance critical part of the system. All inputs
and outputs of the modules are TTL-compatible and operate
from a single 5V supply. Fully asynchronous circuitry is used,
requiring no clocks or refresh for operation of the module.
CACHE CONFIGURATIONS(1)
Memory
Size
Words per
line
Cache
Operation
4MB (7MP6068 default)
4 (default)
unified cache (default)
2MB
8
split cache
1MB (7MP6048 default)
16
512KB
32
256KB
128KB
NOTE:
2841 tbl01
1. Please refer to the Jumper Connections for instructions on how to implementthe Cache
Configurations shown above.
JUMPER CONNECTIONS:
Cache depth and Split vs. Unified Operation are controlled by Jumpers P1-P6 as follows:
~
P3 0
0
P2
J
J
0
P1
0
~
0
P6
0
iiii-fil
P5 0
0
iiii-fil
P4 0
0
0
P3
0
P2
1
0
P1
~
1 MEG UNIFIED
(7MP6048 DEFAULT)
0
P3
0
P2
0
P1
I
~
I
0
0
0
!ii-IIil 0
P6
D
P3
J
!ii-IIil 0
P5 0
D
P2
1
!ii-IIil 0
P4 0
D
P1
J
0
0
P3
Uii-IIiii)
0
P5 0
0
P4
0
P2
0
0
P1
I
1
~
0
0
!ii-IIil 0
P6
D
P3
~
0
P5 0
0
0
P4
D
P2
I
D
P1
0
~
0
D
P3
P6
IiiI-fit
P5 0
0
~
0
D
P2
D
P1
P4 0
J
~
0
l
1
0
~
0
P6
0
c1
~
0
P5 0
0 (iIIooooIIi)
P4 0
512K SPLIT
~
0
P6
0
I
~1
0
D
P4
0
J
128K SPLIT
NOT SUPPORTED
BY R4000
128K UNIFIED
256K SPLIT
256K UNIFIED
0
512K UNIFIED
1 MEG SPLIT
!ii-IIil
P6
I
~
0
Cache line size is controlled by Jumpers P7-P9 as follows:
~
[-....ri)
[ioooIIIi)
pg 0
P9 0
~
[ii.oooIO
P8 0
P8 0
~I
P9 0
D
P8
D
P7
8 WORDS/LINE
16 WORDS/LINE
~
P7 0
4 WORDS/LINE
(DEFAULT)
J
~
D
P9
D
P8
D
P7
t
t
t
32 WORDS/LINE
2841 drw 02
7.39
2
IDT7MP6048, 7MP6068 (DEVELOPMENT KIT)
IDT79R4000 SECONDARY CACHE MODULES
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION(1)
Vee
1/01
1/03
1105
GND
1/08
1/010
1/012
1/014
1/015
1/017
1/019
1/021
GND
1/023
1/025
1/027
1/029
1/030
1/032
1/034
GND
Ao
A2
A4
A6
Vee
OE
A8
Ala
GND
A13
A15
A17
To
Tl
T3
T5
T7
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
PIN NAMES
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
GND
1/00-35
Data Inputs/Outputs
1/00
TO-7
Tag Inputs/Outputs
1102
1104
AO-17
Address Inputs
1/06
1/07
1/09
1/011
1/013
GND
1/016
1/018
1/020
1/022
1/024
1/026
1/028
WE
Write Enable
OE
Output Enable
Vee
Power Supply
GND
Ground
CAPACITANCE
Symbol
Parameter(l)
Conditions
GND
CIN(D)
Input Capacitance (Data)
1/031
CIN(A)
1/033
1/035
Input C~acitanc_e_
(A1-15, OE, TCS, DCS)
CIN(S)
Input Capacitance
(Ao, WE)
COUT
Output Capacitance
WE
Al
A3
Max. Unit
= OV
VIN = OV
10
pF
10
pF
= OV
100
pF
VIN
VIN
VOUT= OV
10
NOTE:
1. This parameter is guaranteed by design, but not tested.
A5
GND
DCS
A7
pF
2841 tbl04
RECOMMENDED DC OPERATING
CONDITIONS
A9
An
A12
A14
A16
Symbol
TCS
GND
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
NOTE:
1. VIL = -l.SV for pulse width less than 10ns.
Vee
2841 drw 03
",,., , II
V
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. For proper operation of the module, please refer to the Jumper Connections for proper connections of the module pins. .
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Commercial
Tag Chip Select
Vee
SIMM
TOP VIEW
Grade
Data Chip Select
TCS
2841 tbl03
T2
T4
77 T6
79
DCS
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
5V± 10%
Symbol
VTERM
Ratlng(1)
Value
Unit
Terminal Voltage with Respect
toGND
-0.5 to +7.0
V
TA
Operating Temperature
o to +70
°C
TSIAS
Temperature Under Bias
-10 to +85
°C
TSTG
Storage Temperature
lOUT
DC Output Current
-55 to +125
°C
50
rnA
NOTE:
2841 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMU M RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2841 tbl 02
7.39
3
IDT7MP6048, 7MP6068 (DEVELOPMENT KIT)
IDT79R4000 SECONDARY CACHE MODULES
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Vee = SV +
- 10%, TA.,. O°C to +70°C)
Parameter
Symbol
Test Conditions
IIlI11
Input Leakage (except Ao. WE)
IIlI21
Input Leakage (Ao, WE)
IiLol
Output Leakage
Icc
Operating Current
VOH
Output High Voltage
VOL
Output Low Voltage
= Max., VIN = GND to Vcc
Vcc = Max., VIN = GND to Vcc
Vcc = Max., CS = VIH, VOUT = GND to Vcc
CS = VIL; Vcc = Max., Outputs Open
Vcc = Min., IOH = -4mA
Vcc = Min., IOL = 8mA
Vcc
Min.
Max.
Unit
-
10
10
J.lA
J.lA
J.lA
2200
mA
2.4
-
V
-
0.4
110
V
2841 tbl07
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 - 4
Output Load
2841 tbl 08
+5V
+5V
4800
4800
DATAoUT--+--....
2550
DATAoUT-........30pF*
..
2550
2841 drw 05
2841 drw04
Figure 2. Output Load
(for tOLZ and tOHZ)
Figure 1. Output Load
* Including scope and jig.
ATAA
(Typical, ns)
5
4
DATAOUTJt~___________~~
Zo = son
=!- lson
1.SV
2841 drw 06
20
40
60
80
100 120 140 160 180
200
CAPACITANCE (pF)
2841 drw 07
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
Figure 3. Alternate Output Load
7.39
4
IDT7MP6048, 7MP6068 (DEVELOPMENT KIT)
1DT79R4000 SECONDARY CACHE MODULES
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vee = 5V ± 10%, TA = O°C to +70°C)
7MPS048/S0S8SxxM
-12
Parameter
Symbol
Min.
-15
Max. Min.
-17
-20
M&x. Min. Max. Min.
-25
Max.
Min.
-30
Max. Min.
Max Unit
READ CYCLE
tAA
Address Access Time
Ao Access Time
-
12
10
-
tAOA
tOE
tOHZ(1)
Output Disable to Output in High Z -
12
10
-
tOLZ(1)
Output Enable to Output in Low
2
-
2
15
12
15
12
-
12
10
7
7
0
-
15
-
-
12
10
10
0
-
Output Enable to Output Valid
Z
-
-
20
16
-
25
21
-
-
17
14
17
13
-
-
25
17
2
-
2
20
15
-
2
17
14
12
12
0
-
20
-
16
15
15
0
-
25
21
20
20
0
-
ns
-
30
26
30
20
-
2
-
ns
-
30
26
25
25
0
-
ns
-
ns
ns
ns
ns
WRITr: CYCLE
tAW
Address Valid to End of Write
tAOW
Ao Valid to End of Write
twp
Write Pulse Width
tow
Data Valid to End of Write
tOH
Data Hold Time
-
-
-
-
-
-
-
ns
ns
-
NOTE:
1. This parameter is guaranteed by design but not tested.
ns
2841 tbl 08
TIMING WAVEFORM OF READ CYCLE(1)
ADDR VALID
ADDR
tAA --------I~
DATAoUT
2841 drw 08
NOTE:
1. This parameter is guaranteed by design, but not tested.
II
TIMING WAVEFORM OF WRITE CYCLE
ADDR
) '\./
..
ADDR VALID
tAW
t
twp
/
tOH
tow
V
DATAIN
V
['-.
DATA VALID
)
I--
2841 drw 09
7.39
5
IDT7MP6048, 7MP6068 (DEVELOPMENT KIT)
IDT79R4000 SECONDARY CACHE MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
EXPLODED VIEW OF
JUMPER AREA
P3
'""!
P2
a-O 0
P6 .....
0
P5
o
P1 ~
0
P9 "-:
-:0 . P8 "-:
P4 "-:
0
P7
a-:
0.350
MAX.
4.640
'4.660
~
--I '----
0.045
~r- 0.055
j4-0.250
0.240
TYP.
PIN 1
Q.2s"O
o
FRONT VIEW
D
0.050
SIDE VIEW
TYP.
gcoocogcD~
IDlD~D~D§D
oc ooe ooe
~eo~e ~e
0
000
BACK VIEW
PIN 1
7.39
2841 drw 10
6
~®
Integrated Device Technology, Inc.
THE SUBSYSTEMS "FLEXI-PAKTM"
CMOS MODULE FAMILY
GENERAL
INFORMATION
SRAM, EPROM, & EEPROM MODULES
FEATURES:
DESCRIPTION:
• High-density modules using high-speed CMOS SRAM,
EPROM, and EEPROM components.
• Inter-changeable modules with equivalent footprints
• Fast access times:
SRAM: 20ns (max.) - military
15ns (max.) - commercial
EEPROM: 95ns (max.) - military
75ns (max.) - commercial
EPROM: 95ns (max.) - military
40ns (max.) - commercial
The Flexi-Pak family of modules are high-speed, highdensity CMOS memory modules constructed on a multilayer
co-fired ceramic substrate using either SRAM, EPROM, or
EEPROM components in lead less chip carriers.
This family of IDT modules supports applications requiring
stand alone static or programmable memory or those applications needing a combination of both. All module configurations
in this family have equivalent footprints, allowing "plug-in
compatibility" with each other (Le. interchangeable), ideal for
a wide range of prototype and debugging applications.
The Flexi-Pak family utilizes the fastest commercial grade
and MIL-STD-883 Class S military grade components, giving
you the highest performance available anywhere. CMOS
technology offers a low-cost, low-power alternative to bipolar
and fast NMOS memories.
All versions of the Flexi-Pak Module Family are offered in
a 66-pin, ceramic HIP (Hex In-line Package). This HIP package is similar to a PGA and allows the designer to fit into 1 sq.
inch of board space.
AIiIDT military modules are assembled with semiconductor
components compliant with the latest revision of MIL-STD883 Class S, making them ideally suited to applications
demanding the highest level of performance and reliability.
• Low power CMOS operation
• Surface mounted LCC components on a co-fired ceramic
substrate
• Offered in a 66-pin, ceramic HIP (Hex In-line Package)
occupying as small as1 sq. inch of board space
• Single 5V (± 10%) power supply
• Multiple ground pins for maximum noise immunity
• Inputs and outputs directly TIL-compatible
ORGANIZATIONS
SRAM:
EEPROM: IDT7M7004 - 128K x 8, 64K x 16, 32K x 32
IDT7M7014*- 512K x 8, 256K x 16, 128K x 32
IDT7M4003 -128K x 8, 64K x 16, 32K x 32
IDT7M4013 - 512K x 8, 256K x 16, 128K x 32
SRAM / EEPROM:
IDT7M7005 - 64K x 8/ 64K x 8
64K x 8 / 32K x 16
32K x 16 / 64K x 8
32K x 16 / 32K x 16
IDT7M7025* -64K x 8/ 256K x 8
64K x 8 / 128K x ~16
32K x 16/ 256K x 8
32K x 16 / 128K x 16
IDT7M7035* -256K x 8/ 256K x 8
256K x 8/ 128K x 16
128K x 16 / 256K x 8
128K x 16/ 128K x 16
IDT7M7045* -256K x 8 / 64K x 8
256K x 8 / 32K x 16
128K x 16/ 64K x 8
128K x 16/ 32K x 16
SRAM / EPROM:
IDT7M7012 - 64K x 8/ 64K x 8
64Kx8/32Kx 16
32K x 16/ 64K x 8
32K x 16/ 32K x 16
IDT7M7002 - 64K x 8/ 256K x 8
64K x 8 / 128K x 16
32K x 16/ 256K x 8
32K x 16/ 128K x 16
IDT7M7022* -256K x 8 / 256K x 8
256K x 8 / 128K x 16
128K x 16 / 256K x 8
128K x 16/ 128K x 16
IDT7M7032* -256K x 8/ 64K x 8
256K x 8 / 32K x 16
128K x 16 / 64K x 8
128K x 16 / 32K x 16
·Please consult the factory for availability of these versions.
Flexi-Pak is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1992
eSC-7092J2
Vee -0.2V or < 0.2V
-
46
46
rnA
VOL
Output Low Voltage
Vee = Min., IOL = BmA
-
0.4
0.4
V
VOH
Output High Voltage
Vee = Min., IOH = -4mA (3)
2.4
VOL
Output Low Voltage
Vee = Min., IOL = 6mA
-
VOH
Output High Voltage
Symbol
Parameter
Test Conditions
(3)
(4)
Vee = Min., IOH = -4mA (4)
NOTES:
1. For TA = O°C to +70°C versions only.
2. For TA = -55°C to +125°C versions only.
3. For liDs (0-15).
4. For liDs (16-31).
2.4
0.45
-
-
II
V
0.45
V
-
V
2826tbl07
7.42
3
IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS (EEPROM)
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 & 2
2826 tbl 08
AC ELECTRICAL CHARACTERISTICS (EEPROM)
(Vec = 5V ± 10%, TA = -55°C to + 125°C or O°C to +70°C)
-75
Symbol
Parameters
-95
Min.
Mex.
Min.
-125
Max.
Min.
-150
Max.
Min.
-200
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
75
-
95
-
125
-
150
-
200
-
ns
tAA
Address Access Ti me
75
-
95
-
150
ns
75
125
200
ns
Output Enable to Output Valid
50
-
150
tOE
-
95
-
200
Chip Select Access Time
-
125
tACS
-
70
-
80
ns
tCHZ (1)
Chip Select to Output in Hiqh
tOH
Output Hold from Address Change
Z
40
55
0
40
0
50
0
55
0
55
0
60
ns
0
-
0
-
0
-
0
-
0
-
ns
WRITE CYCLE
twc
Write Cycle Time
0.4
10
0.4
10
0.4
10
0.4
10
0.4
10
ms
tAH
Address Hold Time
50
50
-
50
-
50
2
2
2
-
2
twp
Write Pulse Width
105
CS Set-up Time
0
0
tCH
CSHold Time
0
-
0
-
0
-
105
tcs
-
-
ns
Address Setup Time
-
50
tAS
-
tDS
Data Set-up Time
55
-
55
-
Data Hold Time
-
55
tDH
0
-
0
-
105
0
105
0
0
55
-
0
-
0
2
105
ns
ns
0
-
ns
0
-
ns
55
-
ns
0
-
ns
PAGE MODE WRITE CYCLE
twc
Write Cycle Time
0.4
10
0.4
10
0.4
10
0.4
10
0.4
10
ms
tAH
Address Hold Time
50
50
-
50
2
2
-
2
-
ns
2
-
50
Address Setup Time
-
50
tAS
lOS
Data Set-up Time
55
-
55
-
55
-
ns
Data Hold Time
0
-
55
tDH
0
-
0
-
ns
Write Pulse Width
105
105
-
105
-
0
twp
-
-
105
tBLC
Byte Load Cycle Time
0.2
200
0.2
200
0.2
200
0.2
200
0.2
200
J.ls
Write Pulse Width High
55
-
55
-
55
-
55
-
55
-
ns
-
0
-
0
-
0
-
0
-
ms
0
-
0
-
0
-
0
-
ns
100
ns
tWPH
2
55
0
105
-
ns
ns
DATA POLLING CYCLE
tDH (1)
Data Hold Time
0
tOEH (1)
Output Enable Hold Time
0
tOE (1)
Output Enable to Output Delay
tWR(1)
Write Recovery Time
2
100
-
2
100
-
2
100
-
2
100
-
2
-
ns
2826 tbl 09
NOTE:
1. This parameter is guaranteed by design but not tested.
7.42
4
IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS (SRAM)
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 & 2
2826 Ibl 10
+5 V
+5 V
480n
480n
DATAoUT---------.--------;
255n
Figure 1. Output Load
DATAoUT--------,-------~
255n
30 pF*
2826 drw 03
5 pF*
2826 drw 04
Figure 2. Output Load
(for tClZ, tOlZ, tCHZ, tOHZ, tow, tWHZ)
AC ELECTRICAL CHARACTERISTICS
(Vcc:= 5.0V
± 10%, TA = -55°C to + 125°C and O°C to +70°C)
_15(2)
Parameters
Symbol
Min.
·17(2)
Max.
Min.
·20(2)
Max.
Min.
·25
Max.
Min.
·30
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
-
17
-
20
-
25
-
30
-
ns
tAA
Address Access Ti me
-
15
-
17
-
20
-
25
-
30
ns
tACS
Chip Select Access Time
-
15
-
17
-
20
-
25
-
30
ns
tCLZ(l)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
-
ns
tOE
Output Enable to Output Valid
-
10
-
11
-
12
-
13
15
ns
tOLZ(l)
Output Enable to Output in Low Z
0
-
0
-
0
-
2
-
tCHZ(l)
Chip Deselect to Output in High Z
-
6
-
7
8
-
12
tOHZ(l)
OutQUt Disable to Output in HiQh Z
-
6
-
7
-
7
-
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
17
-
20
-
25
15
15
-
0
-
-
15
5
-
-
ns
15
ns
12
-
13
ns
-
3
-
ns
-
30
20
25
ns
20
-
25
-
0
-
0
-
ns
20
-
ns
0
-
23
0
-
-
9
-
12
-
13
ns
9
-
13
3
0
-
5
-
ns
-
-
15
0
2
WRITE CYCLE
twc
Write Cycle Time
15
tew
Chip Select to End of Write
12
tAW
Address Valid to End of Write
12
tAS
Address Set·up Time
0
twp
Write Pulse Width
12
tWR
Write Recovery Time
0
tWHZ(l)
Write Enable to Ouput in High Z
-
tow
Data to Write Time Overlap
tOH
toW(l)
Data Hold from Write Time
Output Active from End of Write
13
13
0
13
0
6
-
8
-
8
0
-
0
0
-
0
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specification only.
8
-
0
3
5
ns
ns
ns
ns
ns
27111bl 09
7.42
5
II
IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V
± 10%, TA = -55°C to + 125°C and O°C to +70°C)
-35
Symbol
Parameters
Min.
-40
Max. Min.
-50
Max.
Min.
Max.
-60
(Mil. Only)
Min. Max.
-70
-85
(Mil. Only) (Mil. Only)
Min. Max. Min. Max. Unl
READ CYCLE
tRC
Read Cycle Time
35
-
40
-
50
-
60
-
70
-
85
-
ns
tAA
Address Access Ti me
35
-
70
ns
60
-
70
-
85
40
-
60
35
-
50
Chip Select Access Time
-
40
tACS
-
85
ns
tCLZ(1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
20
-
25
-
30
-
30
-
35
-
40
ns
tOLZ(1)
Output Enable to Output in Low Z
2
-
5
-
5
-
5
-
5
-
5
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
17
20
20
25
30
35
ns
30
-
35
ns
-
5
-
ns
ns
80
-
5
-
ns
50
ns
50
15
-
20
-
20
-
25
-
5
-
5
-
5
-
5
-
5
40
-
50
-
60
-
85
55
65
80
45
-
55
-
70
45
2
-
5
-
5
45
45
tOHZ(1)
Output Disable to Output in High Z -
tOH
Output Hold from Address Change
WRITE CYCLE
twc
Write Cycle Time
35
tcw
Chip Select to End of Write
30
tAW
Address Valid to End of Write
30
-
tAS
Address Set-up Time
0
-
2
twp
Write Pulse Width
25
30
tWR
Write Recovery Time
0
-
0
-
0
-
0
-
0
-
0
-
tWHZ(1)
Write Enable to Ouput in High Z
-
17
-
20
-
20
-
25
-
30
-
35
ns
tow
Data to Write Time Overlap
16
16
Output Active from End of Write
5
5
-
5
-
ns
tow(1)
-
35
5
-
30
3
-
30
Data Hold from Write Time
-
25
toH
-
35
35
3
5
40
5
5
65
5
5
5
ns
ns
ns
ns
ns
2711 tbl 10
NOTE:
1. This parameter is guaranteed by design, but not tested.
EEPROM TIMING WAVEFORMS
TIMING WAVEFORM OF READ CVc"LE(1}
~~:==============tAA========~-t-R-C~~~~~~~~.~I~~~~~~~~~~~~~~~-tO-H-----------
ADDRESS. ______
~----------tcs--~~~
OE
tOE ----------..-.1
DATAoUT
2826drw 05
NOTES:
1. This parameter is guaranteed by design but not tested.
7.42
6
IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)
twc
ADDRESS
~~
~
tAH
"""",-"""""",'
'/~LhF-
I
"*-/////////////////////
""""'- '-",""
r-
~""" ~
7f-
I
DATAoUT
H
tCH
tAs _
twp
(
DATAIN
t
..
tos
1XXXX
tOH
OATAVALIO
2826 drw 06
TIMING WAVEFORM OF PAGE MODE WRITE CYCLE (1)
______-J~r------------------------------------II------------------II---II~II--
tBLC
II~II---AO-5
----,I~~~~~~~------r-~,------~~--------II------~)(~--------II---
_ _ _ _J
DATAIN
1~----------1 "------if---' ' - - - - - - - - ' " - - - - - - - - -
- - - - " - - - - - - - - - - 1 ' - - - - - - - ' 1 '--____J
BYTE 0
BYTE 1
BYTE 2
'----
II
' .
II - - - -
II - - - - - - - -...... ~ I 1 - II
)"--/'- I1 - - -
BYTE3
BYTE 62
BYTE 63
2826 drw 07
NOTE:
1. A6 throughA14 must specify the page address during each High to Low transitions ofWE(or CS). OE must be High only when WE and CSare both Low.
TIMING WAVEFORM OF DATA POLLING CYCLE
II
I,-------------------------------------------II--------------~---II----
II
II
II
1/07
AO-14
An
X
An
II
~II
An
:5
2826 drw 08
NOTES:
1. This parameter is guaranteed by design but not tested.
2. A6 through A 14 must specify the page address during each High to Low transitions of WE (or CS). OE must be High only when WE and CS are both Low.
7.42
7
IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SRAM TIMING WAVEFORMS
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
+---------
tRC ----------~
ADDRESS
..
tOE_
(5)
tOLZ
14----I~1
CS
tACS
tCLl (5) _ _ _ _--1
DATAoUT
2826 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
1 - - - - - - - - - tRC
ADDRESS
DATAoUT
=1
---------
' - - -_ _ _ _ _ _-----'
~~
-
tOH
VA
>kxX*----...:-+-r--
DATA
VALID
2826 drw 10
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
DATAoUT
E-
(5)
teLZ
*
=l - - - - + - - - - OV
--""""'rt-
OUTPUT
NORMALLY
HIGH _ _-'"L
OPPOSITE PHASE
INPUT TRANSITION
3.SV
VOL
VOH
OV
---""----OV
2836 drw 07
NOTES
2836 drw 09
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate:s 1.0 MHz; Zo :s son; tF :S 2.5ns;
tR:S 2.5ns.
7.43
6
IDTIMP9244T/AT/CT, IDTIMP9245T/AT/CT
FAST CMOS 32-BIT BUFFER/LINE DRIVER/BIDIRECTIONAL TRANSCEIVER MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
2.640
~
\-
.\
~
~ D ~ D ~ I 1.I~D
T
O.010TYP
~:;~~
PIN1
.J~.070
TYP
+-0.015
0.023
FRONT VIEW
T
+0.035
TYP
~
BACK VIEW
7.43
0.090
0.120
SIDE VIEW
PIN1
2836 drw 10
7
DOMESTIC SALES REPRESENTATIVES
ALABAMA
lOT
555 Sparkman Dr.,
Ste.1200-D
Huntsville, AL 35816
(205) 721-0211
ALASKA
Westerberg & Associates
Bellevue, WA
(206) 453-8881
CANADA
(WESTERN)
IDAHO
(NORTHERN)
Westerberg & Associates
Bellevue, WA
Anderson Associates
Bountiful, UT
(206) 453-8881
(801) 292-8991
COLORADO
IDAHO
(SOUTHERN)
lOT
(NW Regional Office)
1616 17th St., Ste. 370
Denver, CO 80202
(303) 628-5494
ARIZONA
Western High Tech Mktg.
Scottsdale, AZ
(602) 860-2702
Thorson Rocky Mountain
Englewood, CO
(303) 799-3435
ARKANSAS
CONNECTICUT
lOT
Undco Associates
Woodbury, CT
(5. Central Regional
Office)
14285 Midway Rd., Ste.
100
Dallas, TX 75244
(214) 490-6167
CALIFORNIA
lOT
(Corporate Headquarters)
2975 Stender Way
P.O. Box 58015
Santa Clara, CA 95052
(408) 727-6116
lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
lOT
(SW Regional Office)
6 Jenner Dr., Ste. 100
Irvine, CA 92718
(714) 727-4438
lOT
(SW Regional Office)
16130 Ventura Blvd.,
Ste.370
Encino, CA 91436
(818) 981-4438
Quest-Rep
San Diego, CA
(619) 565-8797
Thorson Rocky Mountain
Salt Lake City, UT
(801) 942-1683
ILLINOIS
lOT
(Central Headquarters)
1375 E. Woodfield Rd.,
Ste.380
Schaumburg, IL 60173
(708) 517-1262
lOT
MARYLAND
NEVADA
(NORTHERN)
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste. 201
Annapolis, MO 21403
(301) 858-5423
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
MASSACHUSETIS
lOT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898-9266
Tritech Sales
Farmington Hills, MI
Synmark Sales
Park Ridge, IL
DELAWARE
(708) 390-9696
lOT
INDIANA
lOT
Arete Sales
Ft. Wayne, IN
(N. Central Regional Office)
1650 W. 82nd Street
Ste.1040
Minneapolis, MN 55431
(313) 442-1200
MINNESOTA
(219) 423-1478
Arete Sales
Greenwood, IN
(612) 885-5777
FLORIDA
(317) 882-4407
OHMS Technology Inc.
Edina, MN
lOT
IOWA
(612) 932-2920
10
Rep Associates
Cedar Rapids, IA
MISSISSIPPI
Indian Harbor Beach, FL
(319) 373-0152
lOT
(407) 773-3412
KANSAS
lOT
Rush & West Associates
Olathe, KS
(SE Regional Office)
1413 S. Patrick Dr.,
Ste.10
Indian Harbor Beach, FL
(SE Regional Office)
1413 S. Patrick Dr., Ste.
32937
(SE Regional Office)
18167 U.S. 19 North
Ste.455
Clearwater, FL 34624
(813) 532-9988
lOT
(SE Regional Office)
1500 N. W. 49th St.,
Ste.500
Ft. Lauderdale, FL 33309
(305) 776-5431
GEORGIA
lOT
(407) 773-3412
KENTUCKY
MISSOURI
Arete Sales
Ft. Wayne, IN
Rush & West Associates
St. Louis, MO
(219) 423-1478
(314) 965-3322
LOUISIANA
MONTANA
lOT
Thorson Rocky Mountain
Englewood, CO
CANADA
(EASTERN)
(SE Regional Office)
1413 S. Patrick Dr., Ste.
CMT Renmark, Inc.
Kanata,ONT
Indian Harbor Beach, FL
MAINE
32937
lOT
(613) 591-9555
(407) 773-3412
CMT Renmark, Inc.
Mississauga,ONT
HAWAII
(416) 612-0900
lOT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Wes'tboro, MA 01581
(508) 898-9266
10
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
32937
(913) 764-2700
(5. Central Regional
Office)
14285 Midway Rd., Ste.
100
Dallas, TX 75244
(214) 490-6167
NEVADA
(SOUTHERN)
Western High Tech Mktg.
(Clark County, NV)
Scottsdale, AZ
(602) 860-2702
NEW HAMPSHIRE
lOT
MICHIGAN
(203) 266-0728
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste.
201
Annapolis, MD 21403
(301) 858-5423
lOT
(303) 799-3435
NEBRASKA
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898-9266
NEW JERSEY
lOT
(NE Regional Office)
One Greentree Centre,
Ste.202
Marlton, NJ 08053
(609) 596-8668
SJ Mid-Atlantic, Inc.
Mt. Laurel, NJ
(609) 866-1234
NEW MEXICO
Western High Tech Mktg.
Scottsdale, Az
(602) 360-2702
NEW YORK
lOT
(NE Regional Office)
250 Mill St., Ste.107
Rochester, NY 14614
(716) 777-4040
Quality Components
Buffalo, NY
(716) 837-5430
Quality Components
Manlius, NY
(315) 682-8885
lOT
(Central Headquarters)
1375 E. Woodfield Rd.,
Ste.380
Schaumburg, IL 60173
(708) 517-1262
SJ Associates
Rockville Centre, NY
(516) 536-4242
NORTH CAROLINA
Tingen Technical Sales
Raleigh, NC
(919) 870-6670
NORTH DAKOTA
OHMS Technology Inc.
Edina, MN
(612) 932-2920
PENNSYLVANIA
(EASTERN)
SJ Associates
Rockville Centre, NY
(516) 536-4242
OHIO
Norm Case Associates
Rocky River, OH
RHODE ISLAND
IDT
(216) 333-0400
(Eastern Headquarters)
#2 Westboro Business
Park
OKLAHOMA
200 Friberg Pkwy.,
IDT
Ste.4002
(S. Central Regional Office) Westboro, MA 01581
14285 Midway Rd., Ste.
(508) 898-9266
100
Dallas, TX 75244
SOUTH CAROLINA
(214) 490-6167
lOT
(SE Regional Office)
OREGON
1413 S. Patrick Dr., Ste. 10
Westerberg & Associates
Indian Harbor Beach, FL
Portland, OR
32937
(503) 620-1931
Norm Case Associates
Rocky River, OH
VERMONT
IDT
555 Sparkman Dr.,
Ste.1200-D
Huntsville, AL 35816
(205) 721-0211
IDT
(Eastern Headquarters)
#2 Westboro Business
Park
200 Friberg Pkwy.,
Ste.4002
Westboro, MA 01581
(508) 898-9266
TEXAS
IDT
(S. Central Regional Office)
14285 Midway Rd., Ste.
100
Dallas, TX 75244
(214) 490-6167
IDT
(S. Central Regional Office)
17314 State Hwy. 19
Ste.242
Houston, TX 77064
(713) 890-0014
UTAH
(407) 773-3412
PENNSYLVANIA
(WESTERN)
TENNESSEE
SOUTH DAKOTA
IDT
(NW Regional Office)
7981 168th Ave. N.E.,
Ste.32
Redmond, WA 98052
(206) 881-5966
WEST VIRGINIA
VIRGINIA
Norm Case Associates
Rocky River, OH
IDT
(NE Regional Office)
Horn Point Harbor
105 Eastern Ave., Ste. 201
Annapolis, MD 21403
(301) 858-5423
(216) 333-0400
WISCONSIN
Synmark Sales
Park Ridge, IL
(708) 390-9696
WASHINGTON
Westerberg & Associates
Bellevue, WA
(206) 453-8881
WYOMING
Thorson Rocky Mountain
Englewood, CO
(303) 799-3435
Anderson Associates
Bountiful, UT
(801) 292-8991
OHMS Technology Inc.
Edina, MN
(612) 932-2920
(216) 333-0400
lOT TECHNICAL CENTERS
Integrated Device Technology, Inc.
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
(408) 492-8350
Integrated Device Technology, Inc.
(Southwestern Regional Office)
6 Jenner Drive, Suite 100
Irvine, CA 92718
(714) 727-4438
Integrated Device Technology, Inc.
(South Central Regional Office)
14285 Midway Road, Suite 100
Dallas, TX 75244
(214) 490-6167
Integrated Device Technology, Ltd.
(European Headquarters/Northern Europe
Regional Office)
21 The Crescent
Leatherhead
Surrey, UK KT228DY
Tel.: 44-0372-363-339/734
Integrated Device Technology, Inc.
(Eastern Headquarters)
#2 Westboro Business Park
200 Friberg Parkway, Suite 4002
Westboro, MA 01581
(508) 898-9266
AUTHORIZED DISTRIBUTORS (U.S. and Canada)
Alliance
Future
Electronics
Contact your local office.
Hall·Mark
Hamiiton/Avnet
Insight
Electronics
Vantage
Components
Zentronics
,.
INTERNATIONAL SALES REPRESENTATIVES
AFRICA
Monte Vista International
5673 W. Los Positas Blvd.,
Ste.205
Pleasanton, CA 94588
Tel: 510-463-8693
Scientec, REA
Saint-Etienne, France
Tel.: 33-77-79-7970
Jermyn GmbH
Nurnberg, Germany
Tel.: 49-9111425095
Microelit SPA & SRL
Milan,ltaly
Tel.: 39-2-4817900
A2M
Brignolles, France
Tel.: 33-1-94-59-2293
Scantec GmbH
Planegg, Germany
Tel.: 49-859-8021
Microelit SPA & SRL
Rome,ltaly
Tel.: 39-6-8894323
A2M
Bron, France
Tel.: 33-1-72-37-0414
Scantec GmbH
Kirchheim, Germany
Tel.: 49-70-215-4027
A2M
BUC, France
Tel.: 33-1-39-56-8181
Scantec GmbH
Ruckersdorf, Germany
Tel.: 49-91-157-9529
A2M
Cesson-Sevigne, France
Tel.: 33-1-99-63-3232
Topas Electronic GmbH
Hannover. Germany
Tel.: 49-51-113-1217
AUSTRIA
A2M
Le Chesnay Cedex, France
Tel.: 33-1-39-54-9113
Topas Electronic GmbH
Quickborn, Germany
Tel.: 49-4106-73097
Ing. Ernst Steiner
Vienna, Austria
Tel.: 43-222-827-4740
A2M
Merignac, France
Tel.: 33-1-56-34-1097
HONG KONG
BELGIUM
Aquitech
Merignac, France
Tel.: 33-56-55-1830
AUSTRALIA
George Brown Group
Rydalmere, Australia
Tel.: 612·638-1999
George Brown Group
Hilton, Australia
Tel.: 618-352-2222
George Brown Group
Blackburn, Australia
Tel.: 613-878-8111
Betea S.A.
St.-Stevens-Woluwe,
Belgium
Tel.: 322-725-1080
DENMARK
ExatecAJS
Copenhagen, Denmark
Tel.: 45-31-191022
FINLAND
ComodoOy
Helsinki, Finland
Tel.: 358-0757-2266
FRANCE
IDT
(So. Europe Reg. Office)
15 Rue du Buisson aux
Fraises
91300 Massy, France
Tel.: 33-1-69-30-89-00
Scientec REA
Bordeaux, France
Tel.: 33-56-39-3271
Scientec REA
Chatillon, France
Tel.: 33-149-652750
Scientec REA
Cesson-Sevigne, France
Tel.: 33-99-83-9898
Scientec REA
Rognes, France
Tel.: 33-42-50-1805
Scientec REA
Schwerwiller, France
Tel.: 33-88-82-5514
Aquitech
Cedex, France
Tel.: 33-1-4-96-9494
Aquitech
Rennes, France
Tel.: 33-99-78-3132
Aquitech
Lyon, France
Tel.: 33-72-73-2412
IDT
(Hong Kong Reg. Office)
Rm.1505,
151F The Centre Mark,
287-299 Queen's Road
Central
Hong Kong
Tel.: 852-542-0067
Lestina International Ltd.
Kowloon, Hong Kong
Tel.: 852-735-1736
INDIA
Malhar Corp.
Bryn Mawr, PA
Tel.: 215-527-5020
GERMANY
ISRAEL
IDT
(Central Europe Reg.
Office)
Gottfried- Von-Cramm-Str. 1
8056 Neufahrn, Germany
Tel.: 49-8165-5024
Vectronics, Ltd.
Herzlia, Israel
Tel.: 972-52-556070
Jermyn GmbH
Umburg, Germany
Tel.: 49-6431/508-0
Lasi Electronica
Bologna, Italy
Tel.: (3951) 353815
Jermyn GmbH
Berlin, Germany
Tel.: 49-30/2142056
Lasi Electronica
Firenze, Italy
Tel.: (3955) 582627
Jermyn GmbH
Dusseldorf, Germany
Tel.: 49-211/25001-0
Lasi Electronica
Milano, Italy
Tel.: (39) 266-101370
Jermyn GmbH
Heimstetten, Germany
49-89/909903-0
Lasi Electronica
Roma,ltaly
Tel.: (19396) 5405301
Jermyn GmbH
Herrenberg, Germany
Tel.: 49-7032/203-01
Lasi Electronica
Torino, Italy
Tel.: (3911) 328588
Jermyn GmbH
Norderstedt, Germany
Tel.: 49-40/5282041
ITALY
JAPAN
IDT
(Japan Headquarters)
U.S. Bldg. 201
1-6-15 Hirakarasho,
Chiyoda-Ku
Tokyo 102, Japan
Tel.: 813-3221-9821
Dia Semi con Systems
Tokyo, Japan
Tel.: 813-3439-2700
Kanematsu Semiconductor
Corp.
Tokyo, Japan
Tel.: 813-3551-7791
Marubun
Tokyo, Japan
Tel.: 813-3639-9805
Tachibana Tectron Co., Ltd.
Tokyo, Japan
Tel.: 813-3793-1171
KOREA
Eastern Electronics
Seoul, Korea
Tel.: 822-553-2997
NETHERLANDS
Auriema
Eindhoven, Netherlands
Tel.: 31-40-816565
NORWAY
Eltron NS
Oslo, Norway
Tel.: 47-2-500650
SINGAPORE
Data Source Pte. Ltd.
Lorong, Singapore
Tel.: 65-291-8311
SOUTH AMERICA
Intectra Inc.
Mountain View, CA
Tel.: 415-967-8818
SPAIN
Anatronic, SA
Madrid, Spain
Tel.: 34-1-542-5566
Anatronic, S.A.
Barcelona, Spain
Tel.: 34-3-258-1906
SWEDEN
Svensk Teleindustri AB
Spanga, Sweden
Tel.: 46-8-761-7300
SWITZERLAND
W. StolzAG
Baden-Daettwil,
Switzerland
Tel.: 41-56-849000
TAIWAN
Johnson Trading Company
Taipei, Taiwan
Tel.: 886-273-31211
World Peace Industrial Co.,
Ltd.
Taipei, Taiwan
Tel: 886-2788-5200
UTC
Taipei, Taiwan
Tel.: 886-2-7753666
UNITED KINGDOM
IDT
(European Headquartersl
No. Europe Reg. Office)
21 The Crescent
Leatherhead
Surrey, UK KT228DY
Tel.: 44-0372-363-339/734
Micro Call, Ltd.
Thame Oxon, UK
Tel.: 44-844-261-939
The Access Group Ltd.
Hertfordshire, UK
Tel.: 0462-480888
Integrated
Device Technology, Inc.
2975 Stender Way
Santa Clara, CA 95054-3090
(800) 345-7015 FAX: (408) 492-8674
(j
Recycled Paper
C Copyright 1992 Integrated Device Technology. Inc.
Printed in U.S.A.
DBK·SMp·00042
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:11 05:13:31-08:00 Modify Date : 2017:08:11 05:54:53-07:00 Metadata Date : 2017:08:11 05:54:53-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:96d26be6-9cb2-8c4f-a3f3-9b99dcae2a78 Instance ID : uuid:372919e6-42ba-e441-87cb-001ba7928ac9 Page Layout : SinglePage Page Mode : UseNone Page Count : 956EXIF Metadata provided by EXIF.tools