1992_Micro_Networks_Data_Conversion_Products 1992 Micro Networks Data Conversion Products
User Manual: 1992_Micro_Networks_Data_Conversion_Products
Open the PDF directly: View PDF 
.
Page Count: 587
| Download | |
| Open PDF In Browser | View PDF |
Index by Part Number
ADC80 .......... 6-5
ADC84 .......... 6-11
ADC85 .......... 6-11
ADC87 .......... 6-17
ADS574 ......... 5-9
ADS774 ......... 5-21
ADS7800 ........ 5-33
DACHK .......... 7-5
DACHK·2 ........ 7-5
DAC71-COB-I ...... 7-9
DAC71-COB-V ..... 7-9
DAC71-CSB-1 ...... 7-9
DAC71-CSB-V ..... 7-9
DAC80-CBI-1 ...... 7-13
DAC80-CBI-V ..... 7-13
DAC85-CB1-1 ...... 7-17
DAC85-CBI-V ..... 7-17
DAC87 .......... 7-21
DAC88 .......... 7-25
MD2840 ......... 10-5
MD2841 ......... 10-5
MD2842 ......... 10-5
MD3802 ......... 10-11
MD3805 ......... 10-11
MD3810 ......... 10-11
MD3902 ......... 10-15
MD3905 ......... 10-15
MD3910 ......... 10-15
MD5024 ......... 10-19
MN0300A ........ 8-5
MN343 .......... 8-9
MN344 .......... 8-9
MN346 .......... 8-13
MN347 .......... 8-13
MN370 .......... 7-29
MN371 .......... 7-29
MN373 .......... 8-17
MN374 .......... 8-25
MN376 .......... 8-31
MN379 .......... 8-35
MN574A ......... 6-23
MN674A ......... 6-31
MN774 .......... 6-39
MN2020 ......... 8-41
MN2200 ......... 8-47
MN3000 ......... 7-31
MN3001 ......... 7-31
MN3002 ......... 7-31
MN3003 ......... 7-35
MN3004 ......... 7-35
MN3005 ......... 7-35
MN3006 ......... 7-31
MN3007 ......... 7-35
MN3008 ......... 7-39
MN3009 .
. 7-39
MN3014 ......... 7-41
MN3020 ......... 7-43
MN3040 .
. ... 7-47
MN3290 ......... 7-51
MN3291 ......... 7-51
MN3292 ......... 7-51
MN3348 ......... 7-57
MN3349 ......... 7-59
MN3850 ......... 7-61
MN3860 ......... 7-65
MN4000 ......... 8-53
MN5065 .
. . 6-47
MN5066 . . .
. .. 6-47
MN5100. . .
. ... 6-51
MN5101 .......... 6-51
MN5120 ......... 6-57
MN5121 .......... 6-57
MN5122 ......... 6-57
MN5123 ......... 6-57
MN5130 ......... 6-57
MN5131 .......... 6-57
MN5132 ......... 6-57
MN5133 ......... 6-57
MN5140 ......... 6-57
MN5141 .......... 6-57
MN5142 ......... 6-57
MN5143 . . . .
6-57
MN5150 ......... 6-65
MN5160 ......... 6-71
MN5200 ......... 6-77
MN5201 ......... 6-77
MN5202 ......... 6-77
MN5203 ......... 6-77
MN5204 ......... 6-77
MN5205 ......... 6-77
MN5206 ......... 6-77
MN5210 ......... 6-85
MN5211 ......... 6-85
MN5212 ......... 6-85
MN5213 ......... 6-85
MN5214 ......... 6-85
MN5215 ......... 6-85
MN5216 ......... 6-85
MN5240.
.6-93
MN5245 ......... 6-99
MN5245A ........ 6-99
MN5246 ......... 6-99
MN5246A ........ 6-99
MN5249 . . .
. .. 6-109
MN5250 ......... 6-115
MN5251 ......... 6-115
MN5252 ......... 6-115
MN5253 ......... 6-115
MN5284 .
. .. 6-119
MN5285 ......... 6-119
MN5286 . . . .. . .. 6-119
MN5287 ......... 6-119
MN5290 ......... 6-127
MN5291 . . . .
. . 6-127
MN5295 ......... 6-135
MN5296 ......... 6-135
MN5825 . . .. . ... 6-143
MN5902 ......... 6-149
MN5903 ......... 6-157
MN5903A ........ 6-157
MN5904 ......... 6-163
MN5905 ......... 6-163
MN5906 ......... 6-169
MN5908 ......... 6-177
MN5909 ......... 6-185
MN6227 . . ..
'" 5-41
MN6228. .
. . 5-41
MN6249 ......... 5-53
MN6290. .
. ... 5-59
M N6291 .
. . 5-59
MN6295 . .
. . 5-71
MN6296 ......... 5-71
MN6400 ......... 5-79
MN6405 ......... 5-87
MN6450 ......... 5-95
MN6500 ......... 5-103
MN6774 ......... 5-109
MN6900 ......... 5-117
MN6901 ......... 5-129
MN7120 ......... 9-5
MN7130 ......... 9-9
MN7140 ......... 9-15
MN7143 ......... 9-15
MN7145 ......... 9-23
MN7146 ......... 9-23
MN7147 ......... 9-23
MN7150-8 ........ 9-31
MN7150-16 ....... 9-31
MN7208 ......... 9-39
MN7216 ......... 9-39
MN7450 ......... 9-45
MN7451 ......... 9-45
Bold Copy = New Products
The information provided herein is believed to be reliable; however, Micro Networks assumes no responsibility for
inaccuracies or omissions. Micro Networks also assumes no responsibility for the use of this information, and
all such usage will be at the user's risk. Specifications are subject to change as Micro Networks reserves the
right to make improvements and changes in its products.
©1992 Micro Networks Division of Unitrode Corporation
Printed in U.S.A.
July 1992
[1JJ MICRO NETWORKS
Data Conversion
Products
Catalog
Mission Statement
Our mission is to be an acknowledged leader in supplying innovative analog signal
processing microcircuits whose high performance and quality uniquely meet the needs of
our customers.
We will achieve this by serving customers in a superior manner with:
•
•
•
•
leading-edge products
strong technical support
advanced manufacturing techniques
on-time delivery
By matching our capabilities and customers' needs, we will best achieve our profit-growth
objectives.
We recognize that loyal, productive employees are our most important resource.
Therefore, we will provide a safe, clean working environment and foster open communications, mutual respect and trust at all levels. We will encourage participation of all
employees and recognize and reward their efforts in meeting our goals and our
customers' expectations. We will provide equal opportunity in employment and promote
employee development and advancement.
Successful innovation and the willingness to take risks are key to achieving individual and
company growth.
Our relationships with customers, suppliers, community and government will be
characterized by mutual understanding and trust. We are committed to conducting our
business in an ethical and responsible manner.
1-1
History
Shortly after its creation in 1969, Micro Networks earned the
reputation as the innovative leader in the design and manufacturing of high reliabiity, dual-in-line packaged, data-acquisition
and conversion products for military/aerospace, industrial and
commercial applications. As recent product introductions and
1969-Micro Networks is created to design, develop, manufacture and market highly reliable, hybrid, DIP, dataacquisition and conversion products for
military/aerospace, industrial and commercial
applications.
1970-Micro Networks introduces the world's first thin-film
hybrid data converter (MN302, 8-bit D/A) pioneering the
active laser trimming of thin-film resistor networks.
1971-The first complete, voltage-output, 8-bit (MN307), 10-bit
(MN310) and 12-bit (MN312) D/A converters are introduced. These are the first such devices to incorporate internal references and current-to-voltage output
amplifiers.
1973-The first successive approximation NO converter in a
DIP, the 8-bit MN502, is introduced, and MN3850 and
MN3860 become the first 12-bit Ollis to guarantee true
12-bit performance over the full -55°C to + 125°C
temperature range.
1974-Micro Networks introduced the first 12-bit succcessive
approximation NO converters in DIP's. Designated
MN5200 and MN5210, they become the only 12-bit NO's
for the next 5 years to guarantee ± 1i2LSB linearity and
no missing codes from-55°C to +125°C. These units
become the most popular 12-bit AID's for
military/aerospace applications and eventually become
the first hybrid NO's to have a slash sheet (38510/120).
1976-The first, complete, single package data acquisition
system (DAS), MN7100 (8 bits, 8 channels), is introduced.
1977-The first, ultra low-power, 8-bit (MN5065, 53mW), 12-bit
(MN5250, 56mW) and 14-bit (MN5260, 215mW) DIPpackaged NO's are introduced.
1978-MN5500 is the first 12-bit NO to incorporate a complete
microprocessor interface (chip enable, chip select, address decode, RIW, 3-state, etc.); while MN5280 is the
first 16-bit, successive approximation NO in a DIP. In the
same year, MN7140 is the first complete, 12-bit DAS to
operate from -55°C to +125°C, and MN5410 is the first
12-bit, autoranging (16-bit dynamic range) NO.
1979-Micro Networks refines thin-film processing and
assembly techniques and wins the race to introduce the
first 12-bit NO capable of operating at 200°C in downhole, oil-exploration applications.
1980-Micro Networks wins another race introducing the first
12-bit AID in a DIP to convert in 1 microsecond. For
years, MN5245 is the only DIP NO to use low-resolution,
monolithic flash converters in a two-step (subranging)
conversion approach.
1982-MN5290 and MN5291 16-bit NO's are the first NO's to
guarantee better than 12-bit performance from -55°C
to +125°C and the first 16-bit DIP NO's that can be successfully screened to MIL-STD-883.
1-2
technical innovations indicate, we still merit that reputation earned 23 years ago. What follows is a historical summary of the
unique technical and practical achievements in Micro Networks
continued advancement of data conversion technology.
1983-MN574A is introduced as the first commercially available
hybrid AID converter to employ gate-array technology.
MN379 is the first track-hold (T/H) amplifier to directly
drive ultra high-speed 8 and 9-bit flash converters.
1985-Micro Networks introduces the MN5420 Hardware
Autoranging AID. This industry-first 12-bit AID
automatically senses the amplitude of its input signal
and selects one of nine input gain ranges to optimize
the accuracy of its 12-bit 1,.,sec NO. The 16-bit floatingpoint output (mantissa and exponent) covers a 20-bit
dynamic range.
1986-Micro Networks revamps its process and quality-control
documentation; adds 17,000 sq. ft. of new clean-room
facility; undergoes a D.E.S.C. audit; and receives MILSTD-1772 Certification. After having used FFT testing
as an in-house development tool since 1979, we introduce the first products in the MN6oo0 Series of highspeed, wide-bandwidth, FFT-tested, sampling NO
converters.
1987-MN5295 becomes the industry's first high-speed
(17,.,sec) 16-bit NO to meet full military requirements
(-55°C to +125°C operation, MIL-STD-883 screening).
1988-Micro Networks submits its qualification samples;
receives MIL-STD-1772 qualification; and is added to the
Hybrid Microcircuits Qualified Manufacturers List.
1989-Micro Networks established a modem link with the
Defense Electronic System Center (DESC) to support
the development of Standardized Military Drawings
(DESC SMD). Micro Networks obtained listings for many
standard device types (including MN5200/5210 Series,
MN5290/5295, etc.)
1990-Micro Networks introduces its first Flash NO Converter
the MN5903 (6-bit, 75MHz). Additionally, the MN6400
is the first in a series of true 16-bit self-calibrating Sampling NO converters to be announced. Custom hybrids
become a key product line for Micro Networks.
1991-MN5902 (8-bit, 20MHz) and MN5906 (6-bit, 50MHz) are
Micro Networks first CMOS monolithic Flash NO converters to be announced. These devices provide highspeed performance in combination with the low-power
characteristics of their CMOS design. The MN6400
Series of self-calibrating devices are expanded with the
MN6405 and MN6450. The MN6900 (8-bit, 500MHz)
and MN6901 (8-bit, 250M Hz) Sampling NO converters
are also released for application in ultra-high-speed
digitizing systems.
1992-Micro Networks introduces the MN4000, a performance
upgrade to industry-standard "0010" and "0025" type
T/H amplifiers. The MN4000 offers an excellent combination of high-resolution and high-speed. Additionally,
the MN7450 is Micro Networks first 8-channel, 16-bit,
50kHz, single-package DAS. More to come!
Table of Contents
Index by Part Number . .............................. Cover
Mission Statement . ................................... 1-1
History . ............................................ 1-2
Still Available/Discontinued ............................ 1-4
Quality Control and High Reliability Screening
Introduction ....................................... 2-3
Compliant MIL-H-38534 Hybrids ....................... 2-4
DESC SMD Listing .................................. 2-5
Custom Capabilities .................................. 3-3
Tutorial
Understanding Data Converters ........................ 4-3
Track-Hold Amplifiers ............................... 4-31
Sampling A/D Converters
Introduction ....................................... 5-2
Selection Guide .................................... 5-7
Product Data Sheets ................................. 5-9
Analog-to-Digital Converters
New Product Highlights .............................. 6-2
Selection Guide .................................... 6-3
Product Data Sheets ................................. 6-5
Digital-to-Analog Converters
New Product Highlights .............................. 7-2
Selection Guide .................................... 7-3
Product Data Sheets ................................. 7-5
Track-Hold and Gain Amplifiers
New Product Highlights .............................. 8-2
Selection Guide .................................... 8-3
Product Data Sheets ................................. 8-5
Data Acquisition Systems
New Product Highlights .............................. 9-2
Selection Guide .................................... 9-3
Product Data Sheets ................................. 9-5
V-F/F-V and Clock Circuits
New Product Highlights .............................. 10-2
Selection Guide ................................... 10-3
Product Data Sheets ................................ 10-5
Ordering Information . ................................ 11-3
1-3
Still Available
The following is a list of older Micro Networks converter products. Although our newer
converters provide higher performance at lower cost, we realize that is is often not
economical for you, the customer, to redesign existing systems or products. Consequently,
we reiterte our commitment to continue to supply these devices for as long as possible;
however, we are compelled to point out that component unavailability and/or manufacturing practicalities may, on occasion, make it impossible for us to keep that commitment. Please contact our Sales/Marketing Department for information on price and
delivery, lead times, minimum order quantities, and recommended alternatives for new
designs.
MN050
MN301
MN302
MN303
MN306
MN308
MN309
MN311
MN312
MN315
MN316
MN319
MN321
MN328
MN329
MN333
MN335
MN360
MN362
MN364
MN366
MN368
MN380
MN410
MN411
MN412
MN413
MN415
MN416
MN502
MN503
MN504
MN507
MN508
MN509
MN510
MN511
MN515
MN516
MN2000
MN2001
MN2002
MN2003
MN2004
MN2005
MN2006
MN2120
MN3010
MN3013
MN3015
MN3100
MN3300
MN3310
MN3311
MN3660
MN5110
MN5111
MN5610
MN5611
MN5612
MN5613
MN5614
MN5615
MN5616
MN5700
MN7100
MN1900
MN375
MN5280
MN5282
MN6231
MN6232
Discontinued
Unfortunately, there are some devices that, because of obsolete or unavailable materials
or discontinued manufacturing processes, we are unable to supply. Please contact our
Marketing/Applications Department for advice regarding alternate device types.
MN0405
MN0605
MN0805
MN350
MN351
MN352
MN5260
14
MN5815
DACBO-CCO-J
DACBO-CCO-V
DAC85-CCO-J
DACB5-CCO-V
MN5820
MN5420
MN565A
MN542
DACB12
MNHT-0010
MNHT-0025
MNHT-378
MNSA-1020
MNSA-1040
MNSA-1205
MNSA-1210
MN5900
MN5901
[1JJ MICRO NETWORKS
~
2-2
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
Quality Control and
High Reliability Screening
Micro Networks is MIL-STD-1772 Certified and Qualified
Micro Networks has long been recognized as a leading supplier of thin
and thick-film, hybrid, data-acquisition and conversion products for
demanding military and aerospace applications. In addition to utilizing proven hybrid assembly techniques, many new products from Micro Networks
are designed and implemented using state-of-the-art monolithic design
and fabrication technologies.
Our products are presently employed in a wide variety of applications ranging from missile-guidance and satellite systems to critical ground support
and test equipment. Our modern facility in Worcester, Massachusetts was
designed and built for the production of thin and thick-film hybrid and
monolithic microcircuits and is capable of producing in excess of one-half
million devices annually.
Micro Networks imposes tight quality control on all aspects of design and
manufacturing. Our Quality Control Department oversees all aspects of
high reliability product processing and screening. The Quality Assurance
Department sets the material standards, specifies manufacturing flow,
controls processing screening standards, maintains lot traceability, and
continuously monitors all parameters critical to product quality.
In order to enhance Micro Networks position as an industry leader in the
design and manufacture of high-reliability hybrid and monolithic microcircuits, Micro Networks has implemented a Total Quality Management Program. This program has been successful in fostering a company-wide
culture of quality consciousness that ensures continuous improvement
in the quality of products and services delivered to our customers. We
believe that by following the precepts of 10M, we can fully satisfy the quality and customer-service expectations of today's marketplace.
An effective Statistical Process Control (SPC) program plays an important role in any 10M process. Selecting the correct processes to monitor,
determining the capabilities of those critical processes, monitoring them,
and implementing corrective actions quickly and effectively are vital to
resolving problems, improving quality, and reducing costs.
Our Total Quality Management program here at Micro Networks provides
our operators and inspectors with contemporary SPC training programs
allowing us to reduce process variability thereby improving overall quality and delivery performance.
MIL-STD-1772 QUALIFIED MANUFACTURERS LISTED - Micro
Networks is fully certified and qualified to MIL-STD-1772, and is listed
in the Qualified Manufacturers List (QML) maintained by the Defense
Electronics Supply Center (DESC). Only those products that are
manufactured, assembled, and tested in acordance with MIL-H-38534
(Hybrid Microcircuits, General Specification for) in a QML-listed facility
may bear the "CH" certification mark for non-SMD-controlled hybrid
microCircuits or the "QML:' certification mark for SMD-controlled
(Standard Military Drawing) devices.
STANDARDIZED MILITARY DRAWINGS (SMD) - Our MIL-STD-1772
qualification enables us to participate in DESC's Standardized Military
Drawing program. This program was conceived to eliminate redundant
documentation for commonly used standard devices in military applications. This program significantly reduces the need for unique OEMproduced Source/Specification Control Drawings (commonly referred to
as SCD's) and has become a preferred method of procurement for buyers
of military hybrid and monolithic integrated circuits. SMD's are described in the DOD-STD-100 document. This program also supports the
Department of Defense's parts-control program in acordance with
MIL-STD-965.
Micro Networks has taken an active roll in supporting the DESC SMD program by establishing in-house word-processing capability for SMD creation, and maintaining a dedicated PC-Modem connection with DESC for
the transmitting and receiving of DESC SMD documentation. Micro Networks welcomes our customers to join us in sponsoring the creation of
new SMD's for our standard catalog items.
Many of Micro Networks standard products families are available as either
compliant MIL-H-38534 or as DESC SMD devices. See Table 1 for listing
of devices currently (at the time of this printing) available as compliant MILH-38534 devices. See Table 2 for those devices currently (at the time of
this printing) available in accordance with a DESC SMD.
Please contact your local Sales Representative or the factory for current
information regarding availability of either compliant or SMD devices or
for assistance in creating new SMDs for Micro Networks products.
NON.JAN MULTICHIP AND OTHER NON.JAN MICROCIRCUITS Custom monolithics, non.JAN multi chip and all other non.JAN microcircuits except hybrids described or implied to be compliant with Method
5004 and Method 5005 of MIL-STD-883 must meet the requirements of
paragraph 1.2.1.b of MIL-STD-883. MIL-STD-1772 QML listed manufacturers such as Micro Networks already meet most of these requirements:
as they are very similar. By exercising proper control over the source of
chip suppliers, Micro Networks is able to offer compliant monolithic and
multichip microcircuits. These compliant devices have a quality factor
(utilized for reliability calculations per MIL-HDBK-217) two and a half times
better than non-compliant devices.
PREDICTING DEVICE RELIABILITY - For the purpose of predicting the
reliability of electronic equipment and systems, the military has developed
quality factors for component parts. While many factors are involved in
determining these theoretical failure rates, only the quality factor no and
the application-environment factor n E appear in all models. All system
failure rates are directly dependant on these factors.
MIL-HDBK-217 governs the procedures for determining theoretical failure
rates and quality factors for hybrid integrated microcircuits used in military
electronic systems. Table 5.1.2.9-6 of the handbook specifies that hybrid
2-3
circuits supplied to the Class-B requirements of MIL-STD-883 by fully
qualified, QML-listed manufacturers must have a designated IIa of 0.5,
as compared to a nO of 1.0 for devices tested in accordance with Method
5008 of MIL-STD-8B3, but from a non-OML-listed supplier. In other words,
a compliant device supplied by Micro Networks has twice the theoretical
reliability of a similar device from a non-OML-listed supplier. Furthennore,
compliant Class-B devices are rated forty times more reliable than products from non-compliant suppliers, subjected to unscreened devices.
ENVIRONMENTAL STRESS SCREENING - Micro Networks produces
products that represent the end result of all the very best disciplines:
innovative designs, strict adherence to established design rules, superior
materials and components, tightly monnored and controlled processes,
stringent test procedures, and effective corrective measures that permanently fix problems. All of these desciplines are essential to the
manufacture of a superior-quality, highly-reliable product.
Our customers are producing complex, high-perfonnance equipment that
must operate in unusually demanding environments and under uncommonly stressful conditions. These programs require a high degree of
assurance that the products designed into these systems will meet the
expected level of reliability and performance. For these programs that do
not require MIL-H-38534 compliant deviCes or for non-milnary applications
where enhanced reliability is required, Micro Networks offers devices
which are Environmentally Stressed Screened.
These Environmentally Stressed Screened devices are screened to the
test methods of MIL-8TD-883, Method 500a However, these devices
should not be confused with compliant MIL-H-38534 devices. Differences
between Environmentally Stressed Screened and Compliant devices lie
in the additonal requirements for full compliance with MIL-H-38534
requirements: Element Evaluation, In Process Controls and Screening
and Quality Conformance Inspection.
Environmentally Stressed Screened devices offer designers a costeffective solution to their particular system requirements.
CAPABILITIES - Micro Networks, in support of our military business,
maintains in-house test capability for performing the following tests:
Hermetic Seal
Stabilization Bake
Burn-in/Life Test
Temperature Cycle
Constant Acceleration
Marking Permanence
PIND
Thermal Shock
Solderability
Bond Strength
Internal Visual
X-Ray
XRF
Die Shear
When required, additional testing is perfonned at
laboratories.
Compliant MIL-H-38534 Device Families
ADC87
DACHK
DAC88
MN0300A
MN3431344
MN3461347
MN370/371
MN373
MN376
MN379
MN2020
MN3000 Series
MN3008/3009
MN3014
MN3020
MN3040
MN3290-V Series
MN3348
MN3349
MN3860
MN5100/5101
MN5120/30/40 Series
MN5150
MN5200 Series
MN5210 Series
MN524515246
MN5250 Series
MN5290
MN5825
MN6400
MN7120
MN7130
MN7145146/47 Series
MN7150-8
MN7150-16
DES~proved
test
Future Compliant (1)
MN374
MN3003 Series
MN5160
MN5295196
MN5249
MN6249
MN6290/6291
MN629516296
MN6405
MN6450
MN6500
MN6774
MN7140/43
MN7208
MN7216
MN7450
MN7451
Table 1. Compliant MIL-H-38534 Device Families
NOTES: 1. Contact factory for availability of future compliant products.
2-4
DIA Converters
Sampling AID Converters
Part No.
MN6227T/B
MN6228T/B
MN6295T1B
MN6296T/B
MN6400T/B
DESC 59628998401 HXX'
8998402HXX'
8998301 HXX'
8998302HXX'
9177001 HXX'
Page Number
5-41
5-41
5-71
5-71
5-79
AID Converters
MN5200H/B
MN5201H/B
MN5202H/B
MN5203H/B
MN5204H/B
MN5205H/B
MN5206H/B
MN5210H/B
MN5211H/B
MN5212H/B
MN5213H/B
MN5214H/B
MN5215H/B
MN5216H/B
MN5245H/B
MN5245FH/B
MN5245AH/B
MN5245AFH/B
MN5246H/B
MN5246FH/B
MN5246AH/B
MN5246AFH/B
MN5290H/B
MN5291H/B
MN5295H/B
MN574AT/B
ADC87H/B
8958301YX
8958303YX
8958305YX
8958302YX
8958304YX
8958306YX
8958307YX
8958401YX
8958403YX
8958405YX
8958402YX
8958404YX
8958406YX
8958407YX
8959501XX
8959501YX
8959502XX
8959502YX
8959503XX
8959503YX
8959504XX
8959504YX
8956301HXX
8956302HXX
8956901HXX
8512702XX"
8850802XX
6-77
6-77
6-77
6-77
6-77
6-77
6-77
6-85
6-85
6-85
6-85
6-85
6-85
6-85
6-99
6-99
6-99
6-99
6-99
6-99
6-99
6-99
6-127
6-127
6-135
6-23
6-17
Part No.
MN3008H/B
MN3009H/B
MN3020H/B
MN370H/B
MN371H/B
MN3860H/B
DAC87H/B
MN329OT/B-V
MN3291T1B-V
MN3292T/B-V
DESC59628768801 XX
8768802XX
8971801 XX
8981401XX'
8981402XX'
9057001HXX
8300301JC"
8953103HYX
8953104HYX
8953102HYX
Page Number
7-39
7-39
7-43
7-29
7-29
7-65
7-21
7-51
7-51
7-51
T/H Amplifiers
MN346H/B
MN376H/B
MN4000H/B
8994001HXX
9073001 HXX'
9085601 HXX'
8-13
8-31
8-53
Data Acquisition
MN7130H/B
MN7140H/B
9057101 HXX'
9079701HXX
9-9
9-15
'Release Pending
"Pursuing listing on Existing SMD
If the device type you're interested in is not listed,
please consult factory.
Table 2. DESC Standardized Military Drawings (SMD) Cross Reference.
2-5
OJ
MICRO NETVVORKS
~
2-6
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
Custom Hybrid Microcircuits
Capabilities
EXPERTISE THROUGH
EXPERIENCE
CUSTOMS DEVELOPED
AT MICRO NETWORKS
LIBRARY OF BUILDING
BLOCK CHIPS
• Years of military/high
reliability experience
• Highpass, Lowpass and
Bandpass Filters
• Flash A/D Converters
• Micro Networks fastestgrowing line
• High-Speed Line Driver
• Autocalibrating
AID Converters
• Specialty: analog and
analog/digital interface
• Thick-film, thin-film,
chip-and-wire expertise
• Proven programmanagement
techniques
• Geometric ADC
with Autoranging
• Precision Voltage
Regulators
• Precision SignalConditioning Circuits
• D/A Converters
• Error-Correction ASICs
• T/H Amplifier Front Ends
• High-Precision
NiCr Resistors
• Custom
ADCs and DACs
• Data-Acquisition
Circuits
• Programmable-Gain
Amplifiers
• Motor-Drive Hybrids
Partial Program List
3-2
AIRCRAFT
SHIPBOARD
MISSILE
A-6F
MK46
AMRAAM
B-1
MK50
PATRIOT
F-1
BSYI
ROLAND
F-14
BSYII
CROTALE
F-15
RAPLOC
PENGUIN
F-16
SQS56
MAVERICK
F-18
SQQ89
HARM
Custom Hybrid Capabilities
Custom hybrid circuits represent Micro Networks' fastestgrowing product line. These circuits are a natural outgrowth
of the company's many years of experience in designing,
manufacturing, and testing precision, hybrid-based signalprocessing circuits. The rich diversity of technologies and
materials available for both passive and active circuit
elements makes custom hybrid circuits the solution of
choice in the most demanding applications.
Black box. Given a circuit's input/output specifications, MN's engineers can design an appropriate circuit and translate it to optimal hybrid form.
Hybrid circuits have long been the preferred circuit solution in military/aerospace environments, whose stateoOf-the
art performance requirements preclude the use of
monolithic integrated circuits, and whose limited space
mandates the smallest possible physical volume. Custom
hybrid circuits from Micro Networks are designed into aircraft (F-14, F-16, F-18, A-6F); shipboard systems (BSY1,
BSY2, MK46, MK50, RAPLOC, SQ56, SQQ89); and
missiles (AMRAAM, Patriot), to name just a few applications.
"Grey box" design demands a great deal of engineering
expertise. Given the constraints on hybrid-circuit designs-component availability, value limits and tolerances, and
other factors--it is often possible to modify an existing circuit design to enhance the resulting hybrid circuit's
manufacturability, cost- effectiveness, and performance.
Micro Networks' success in custom hybrid circuits is inextricably linked to the company's commitment to quality
(see the section entitled, Quality Control and HighReliability Screening). Quality consciousness pervades all
departments at Micro Networks. From order entry to the
shipping dock, quality is a philosophy of life, not something
that's tested-in. Micro Networks was one of the firl;t
manufacturers certified and qualified to DESC's MILSTD-1772 standard for hybrid facilities. From the beginning, Micro Networks has specialized in the production of
microcircuits that satiSfy the rigorous requirements of MILSTD-883 and MIL-H-38534.
Micro Networks' philosophy in developing and producing
custom hybrid circuits is to successfully serve our
customers' needs through a combination of:
•
Commitment
•
Integrity
•
Competence
•
Qualified facilities
•
Qualified and dedicated personnel
ENGINEERING RESOURCES - Micro Networks' staff of
design engineers possesses a wealth of multi-disciplinary
skills. Their many years of experience in deSigning
analog/digital interface circuits provides broad-based proficiency in analog, digital, and mixed-signal electronics. In
the development of a custom hybrid, MN's engineering staff
works closely with the customer, in one of several ways:
Build-to-print. This is the one-foroOne translation of
an existing circuit design to hybrid form, retaining
all component types, values, and tolerances appearing in the original schematic diagram.
"Grey box". Based on an existing schematic
diagram and input/output specifications, MN's
engineers can often effect major or minor modifications that make the circuit more suitable for hybrid
fabrication.
In black box and "grey box" design endeavors, Micro Networks' engineers have an extensive library of building-block
circuit functions to draw upon. Available circuit blocks
previously developed for both standard and custom products include flash AID converters, D/A converters, errorcorrection ASICs, and track/hold amplifier stages.
Micro Networks' engineering department has a full range
of deSign, engineering, and simulation tools to facilitate
rapid and accurate custom-hybrid design. These tools include a computer-based hybrid layout system, SPICE software for circuit simulation, and thermal-modeling software.
For quick sample turnaround, the engineering department
has a dedicated prototype assembly area. For those cases
where it is advantageous to design an ASIC chip for use
in a custom hybrid, Sun workstations and Cadence CAD
software provide the capability to design both CMOS and
bipolar IC chips.
Custom hybrid circuits successfully developed and produced by Micro Networks include: data-acquisition systems;
AID and D/A converters; track/hold amplifiers; precision
switched-gain amplifiers; lowpass, bandpass, and
highpass filters; low-noise amplifiers; low-dropout
regulators; multichannel amplifiers; transceivers; line
drivers; smart Darlington drivers; actuator drivers; phaselocked-loop circuits; a 20-bit dynamic-range AID converter,
and a host of others.
This extraordinary diversity of circuit functions, precision
and speed requirements, analog/digital interface environments, and packaging solutions has endowed Micro
Networks' engineering staff with an unparalleled wealth of
experience, and more-than-ample expertise to undertake
any conceivable custom- hybrid project.
TECHNOLOGY AND FACILITIES - One of the major advantages of hybrid circuits is the ability to combine diverse
materials, components, and technologies that would be impractical or impossible to incorporate in monolithic ICs. As
an example, Micro Networks employs both thick-film and
thin-film processes in the design of its resistor networks and
single-layer and multilayer substrates. Thick-film resistors
provide maximum economy in most circuit applications; in
applications demanding extremely tight tolerances,
resistor-to-resistor matching, or precise temperature tracking, nickel-chromium thin-film resistors provide the ultimate
in electrical characteristics. Both sputtering and evaporation systems are available for depositing thin-film conductors and resistors.
Manual or automatic laser-trim stations provide either
passive (trim to resistor value) or active (trim for circuit performance) adjustments for resistor networks and assembled hybrids. In mounting components on substrates, Micro
Networks uses conductive or non- conductive epoxy, eutectic, or solder bonding techniques. For making circuit connections, manual and fully automatic wire-bonding stations
accommodate gold and aluminum wires of a wide range
of diameters. Packaging options presently available from
Micro Networks include: DIPs, SiPs, LCes, metal bathtubs,
TO-5, and TO-.3.
Micro Networks' test department and test equipment are
ideally geared to the production testing of custom hybrid
circuits. Several LTX and Eagle automatic test systems provide rapid, economical, and repeatable tests of analog,
digital, and mixed-signal functions. A team of experienced test programmers ensures rapid turnaround for new
designs. In addition to these automatic production test
systems, Micro Networks' test- engineering department is
adept at designing specialized test systems for low-volume
projects or for Circuits that require special testing
techniques.
34
PROGRAM MANAGEMENT -It is Micro Networks' standard procedure to appoint an experienced program
manager to direct the development efforts for new custom
hybrid projects. The duties of the program manager include:
•
Provide a single communications interface between
the customer and Micro Networks;
•
Participate in design reviews;
•
Coordinate schedule reviews and manage
program meetings;
•
Develop status reports and action plans;
•
Develop and maintain computer-based PERT and
Gantt charts for use as management and
communication tools;
•
Serve as the customer's advocate to Micro Networks'
management.
The unique combination of engineering expertise, hybridtechnology mastery, and proven program-management excellence makes Micro Networks eminently qualified to meet
the most demanding custom-hybrid challenges.
[1J] MICRO NETWORKS
~
4·2
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852·5400
Understanding Data Converters
INTRODUCTION
Analog to Digital and Digital to Analog Converters are collectively referred to as Data Converters, and their usage has
paralleled the availability of digital computing power increasing enormously since the early fifties. Analog to digital (A/D)
and digital to analog (D/A) converters are the interface between the physical parameters of the real world, which are
analog, and the digital world of computation and control
systems. Data converters find applications in widely diverse
fields ranging from the digital multimeter on your bench to
sophisticated inertial guidance systems capable of targeting
a misSile to within thousands of feet after thousands of miles
of flight. Other typical applications include high efficiency,
emission reducing electronic fuel systems, computer-based
energy management systems, and the industrial and process control systems that refine our fuel, prepare and
package our food, and process the plethora of chemicals
required by our complex society.
The present situation involving data converters is very complex. He (she) is a rare engineer who has not had at least a
casual acquaintance with data converters and an equally
rare one who can claim to clearly understand them. This is
partly due to the fact that converters are such rapidlyevolving (and sometimes confusing) components. They are
made in high resolutions and accuracies by only a few
manufacturers. Data sheets range from excellent to
abominable. Specification parameters are sometimes confusing and not well standardized. Packaging ranges from
modules and printed circuit boards to standard Dual·in·Line
packages, and contents range from complete functions to
various "bits and pieces" that require the addition of other
components entailing perhaps more importantly, the con·
sideration of additional error sources.
In this tutorial section we hope to share with you our hundred
odd years of cumulative data converter experience and give
you the tools that will enable you to compare different design
approaches and manufacturers so you will be able to select
the most cost effective components and approaches for your
specific data converter application.
At Micro Networks, our philosophy is that all converter
specifications should be defined from a "black box"
(equivalent circuit) point of view. An input/output transfer
function should be defined, clearly described, and bounded
by maximum error specifications, both at room temperature
and over the full operating temperature range. Individual er·
rors should be combined to give overall error specifications
whenever the individual specifications are not of any per·
tinence, and specification parameters should be clearly
defined.
As you use this catalog, you will seethis philosophy reflected
in our data sheets. You will find more accuracy specifica·
tions, clear definitions, and generously populated maximum
columns. But now onto the meat-how to understand and
work with data converters and their specification sheets.
DATA CONVERTER TRANSFER FUNCTIONS
Let's begin at the beginning, with the data converter in·
put/output transfer functions. Figure 1 shows the ideal digital
inputlanalog output transfer function of a 3 bit, 0 to + 10Vout·
put range, binary coded digital to analog converter (D/A).
Figure 2 shows the ideal digital input/analog output transfer
function of a 3 bit. ± 10V output range. offset binary coded
D/A converter.
Analog Output
(DC Volts)
10.00
875
I
1 LSB
7.50
~ 1.25 Vol1s
6.25
5.00
3.75
2.50
1.25
o·~oo
001
010
011
100 101
110
111
9~~~~'
Figure 1. Digital input/analog output transfer function of an
ideal, 3·bit, 0 to + 10V output range, binary coded D/A con·
verter.
Analog Output
(DC Volts)
I
+ 7.5
1 LSB = 2.5 Volts
+ 5.0
+ 2.5
Digital
0000--"'1--'-0"'10-0"'11-10"0-10+1-1+10-111 Input
00
- 2.5
- 5.0
- 7.5
-10.0
Figure 2. Digital input/analog output transfer function of an
ideal, 3 bit, ± 10Voutput range, offset binary coded D/A con·
verter.
The transfer functions are discontinuous with a unique one·
to·one correspondence between digital input codes and
analog output voltages. For each input code there is one and
only one output level. The number of different input codes is
equal to 2 n where n is equal to the number of digital input
bits. A 3 bit D/A has 2' = 8 different input codes; an 8 bit D/A
4·3
has 2' = 256 different input codes; a 12 bit DIA has 2" = 4096
input codes; etc ... The 3 bit DIA of Figure 2 operates as
follows:
For a Digital Input of
MSB
Bit 2
LSB
000
001
o
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
o
The Analog Output
Voltage Is
-10.0V
-7.5V
-5.0V
-2.5V
O.OV
+2.5V
+5.0V
+7.5V
The analog output of a DIA converter changes in discrete
analog steps with changes in digital input. The smallest
change in output level that can be generated by a DIA converter,i.e., the change from one analog output level to an adjacent level, is the value assigned to the converter's Least
Significant Bit (LSB). The smallest change in output level a
DIA can produce is a measure of its resolving power; it is its
resolution. Resolution is also expressed in bits. In this example we have a 3 bit converter; its resolution is 3 bits. Resolution can also be expressed in terms of the number of output
levels the device has; for a 3 bit device the number is eight.
The value of the LSB (also called a quantum) is equal to the
converter's Full Scale Range (FSR) divided by the number of
different input codes, i.e., the number of different output
levels (2 n). A DIA converter's Full Scale Range is equivalent to
the nominal peak to peak voltage (or current for current-output devices) of the converter's output range. For the 3 bit 0 to
+ 10V output range DIA of Figure 1, FSR = 10 volfs, and 1
LSB = 10VI2n = 10VI8 1.25 volts. For the 3 bit ± 10V output
range DIA of Figure 2, FSR = 20 volts, and 1
LSB 20VI2 n 20VI8 2.5 volts. Table I shows the weights
and amplitudes of LSB's for higher resolution converters.
=
=
=
=
Notice in Figures 1 and 2 that when all the digital inputs are
turned "on", i.e., when the digital input is 111, the output of
the converter doesn't quite make it to its nominal full scale
value. It always falls 1 LSB short. This is due to the fact that
"dB"
BIT 2-n (Fraction)
MSB 2-' 112
-6
2-2 114
2
-12
2- 3 118
-18.1
3
2-' 1116
4
- 24.1
2-' 1132
5
- 30.1
2- 6 1164
6
- 36.1
2- 7 11128
7
-42.1
2-' 11256
8
-48.2
2-' 11512
-54.2
9
2-" 111,024
10
-60.2
2-" 112,048
11
-66.2
2-" 114,096
12
-72.2
2- 13 118,192
13
-78.3
14
2-" 1116,384
-84.3
15
2-" 1132,768
-90.3
2- 16 1165,536
16
-96.3
17
2-" 11131,072
- 102.3
18
2-" 11262,144
- 108.4
19
2- 19 11524,288
- 114.4
2-" 111 ,048,576 - 120.4
20
1I2n
(Decimal)
0.5
0.25
0.125
0.0625
0.03125
0.015625
0.007812
0.003906
0.001953
0.0009766
0.00048828
0.00024414
0.00012207
0.000061035
0.0000305176
0.0000152588
0.00000762939
0.000003814697
0.000001907349
0.0000009536743
Table 1. Binary bit weights and amplitudes.
4-4
the value of bit 1 (the Most Significant Bit or MSB) is FSRI2,
the value of bit 2 is FSRI4, and the value of bit 3 (LSB) is FSRI8.
When all the bits are "1", the output level will be the value of
bit 1 (MSB) plus thatof bit 2 plus thatofbit3(LSB), i.e., its level
will be ('12 + '/., + Yo) = 'Is FSR. Therefore, the actual positive full
scale output of the DIA in Figure 1 is + 8.75V, not 10V, and the
actual positive full scale output of the DIA in Figure 2 is
+ 7.5V, not 10V. For simplicity and convenience, however,
data converters will usually have their analog input or output
defined according to its nominal full scale (FS) value or its
nominal FSR rather than to its actual FS or FSR.
Invariably, you'll see DIA transfer functions depicted as staircases. If one displays the DIA transfer function on a scope
while stepping the input and sweeping the output at the right
speed, one can make the transfer function look like the staircase one often sees, but the theoretical transfer function is a
series of points as shown in Figures 1 and 2. A given digital input produces one and only one analog output level (voltage or
current), and there are only 2n (n = numberof input bits) possible inputs (outputs).
When a manufacturer measures the accuracy of a DIA converter, he attaches his voltmeter or scope to the output, applies digital data to the inputs, and measures the output to
see how close the levels are to what they're supposed to be.
The ideal analog inputldigital output transfer function of a 3
bit, 0 to + 10V input range, straight binary coded analog to
digital converter (AID) is shown in Figure 3. The ideal analog
input/digital output transfer function of a 3 bit, ± 10V input
range, offset binary coded AID converter is shown in Figure 4.
The transfer functions are discontinuous and there is not a
unique one-to-one relationship between analog input 7.5 +10.0
Analog
Input
(DC Volls)
011
010
001
000
_
Figure 4. Analog input/digital output transfer function of en
ideal, 3 bit, ± 10V input range, offset binary coded AID converter.
exist in any but the 2 n states indicated. The "rise" portions of
the staircase do not exist. Return to Figure 4. This 3 bit AID
operates as follows:
For an Input
Voltage Between
< -7.5V
- 7.5V and - 5.0V
- 5.0V and - 2.5V
- 2.5V and O.OV
O.OV and + 2.5V
+ 2.5V and + 5.0V
+ 5.0V and + 7.5V
> + 7.5V
The AID Output Will Be
MSB
Bit 2
LSB
o
o
o
o
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
The arrows at the ends of the transfer function indicate that
analog inputs greater than + 7.5V (up to the device's maximum allowed positive input voltage) all give a 111 output and
that analog inputs less than - 7.5V (down to the maximum
allowed negative input voltage) all give a 000 output. Also
note that digital output words correspond not to single
analog input voltages, but to "bands" or "ranges" of input
voltage. The width of each band is the quantization size or the
quantum; it is the value assigned to the converter's Least
Significant Bit (LSB), and it is again equivalent to the converter's Full Scale Range (FSR) divided by 2 n (n number of
bits). An AID's FSR is equivalent to the nominal peak-to-peak
value of its input range. For the 0 to + 10V input range 3 bit
AID of Figure 3, FSR = 10 volts, and 1 LSB = 10V/2n = 10V/8
= 1.25 volts. For the ± 10V input range 3 bit AID of Figure 4,
FSR = 20 volts and 1 LSB = 20V/2 n = 2.5 volts. The value of an
LSB is the smallest analog change or difference which can be
distinguished or resolved by the AID. It is an indicator of can·
verter resolution. As with DIA's, AID resolution is usually expressed as the number of output bits or as the numberof output states. See Table I.
=
Return again to Figures 3 and 4. Note again the quantization
effect. Many different analog inputs may yield the same
digital output. This is what quantization is all about. In Figure
3, any analog input between + 1.25V and + 2.50V gives a
digital output of 001.001 is the digital output for a "band" of
analog input voltages that is 1 LSB wide. If we assign the
code 001 tothe nominal midrange of the input band for which
it is valid, we can say that 001 corresponds to input voltages
of + 1.875V ± 0.625 volts, which can be written as
+ 1.875V ± 1/2 LSB. The ± '12 LSB is the quantization uncertainty or the quantization noise. You'll often see it referred to
on AID data sheets as Inherent Quantization Error. It's
unavoidable, and its magnitude is always an irreducible ± '12
LSB. If you want to reduce its effect, you'll have to go to a can·
velter that has higher resolution, i.e., one that has more output codes and therefore, a smaller LSB. If you went to a 12 bit
AID with a ± 10V input range, each digital output word would
represent a band of input voltages only 0.00488 volts wide.
This band is still 1 LSB wide, but now an LSB is a lot smaller.
Digital output codes are always going to stand for "bands" or
"ranges" of input voltage. You've got to round off somewhere.
For the purposes of specifying and testing AID converters, it
is difficult and time consuming to measure the center of a
quantization level (the + 1.875V in this example). The only
points along AID's analog input/digital output transfer function that can quickly and accurately be detected and
measured are the transition voltages, the voltages at which
the digital outputs change from one code to the next.
Note in Figure 4 that the digital output changes from 000 to
001 as the input is increased from some more negative
voltage to - 7.5V. It changes from 001 back to 000 as the input
is decreased from some more positive voltage to - 7.5V. This
voltage, - 7.5V, is the Minus Full Scale LSB Transition
Voltage. It is the voltage at which the LSB changes from a "1"
to a "0" or vice versa while all other bits remain "0". If the LSB
output were tied to an LED and the converter were continuously converting, the LED would flicker on and off when
the input voltage was at - 7.5V. For this reason, transition
voltages are often called "flicker" voltages. Notice that the
011 to 100 transition (called the "major transition" because
all the output bits change) ideally occurs at the zero volt
analog input. At this point, under the conditions described
above, all the output bits would be flickering. Lastly, the
Positive Full Scale LSB Transition Voltage, the voltage at
which the LSB flickers while the other bits remain "1", is
ideally + 7.5V.
Analog Input
(DC Volts)
+ 10.0
+ 7.5
+2.5
0.0
Digital
MSB
Output
LSB
111
11~
10~
~~~
-2.5
01~
-7.5
-10.0
000
OO~
Figure 5. Example of how digital output coding tables appear
on Micro Networks' AID converter data sheets. This table
describes the AID of Figure 4. With the converter continuously converting, the output bits indicated as~ will change from a
"1" to a "0" or vice versa as the input passes through the
voltage level indicated. The digital output changes from 000
to OOt1or vice versa) at an input level of - 7.5V. Input signals
below this level will give an output of all "O's". The digital output changes from 011 to 100 (all bits change) at an input of
zero volts. The digital output changes from 110 to 111 (or vice
versa) at an input of + 7.5V. Any voltage greater than + 7.5V
will give an output of all "1 's".
4-5
Many converter users don't realize that transition voltages
are what manufacturers look for when testing AID converter
Linearity and Accuracy. When a manufacturer tests the ac·
curacy or linearity of an AID converter, he attaches his
voltmeter to the input to see if the transition voltages are
where they are supposed to be. Micro Networks has begun to
include transition voltages in the Output Coding Tables ap·
pearing in our AID converter data sheets. Figure 5 shows the
coding table that Micro Networks would use to describe the
AID of Figure 4. If one wanted to depict the AID transfer function as a set of points (similar to a DIA transfer function) one
can simply plot the transition voltages and suffer no loss of
information. This is done in Figure 6. Notice that an AID
always has one less transition (2 n - 1) than the number of out·
put codes (2 n).
Output
Transitions
110tot11
101 t0110
The rationale behind the transfer function of Figure 7 is to
have the output codes centered in the input bands corresponding to LSB increments. The first transition occurs at % LSB
above zero; the last '/2 LSB below 10V. The code 001 corresponds to inputs of 1 LSB ± % LSB. Throughout this
discussion we will use AID transfer functions similar to those
of Figures 3 and 4 because we feel the symmetrical nature of
the plot will simplify specification parameter demonstra·
tions.
GROUPING CONVERTER SPECIFICATIONS
For the purpose of clarifying and simplifying the explanation
of converter specifications, we have divided the specs into
two major categories: the Performance Specifications and
the Design Specifications. The Performance Specifications
have been further subdivided into the Relative Performance
Specifications, the Absolute Performance Specifications,
and the Dynamic Specifications. The pertinent specs falling
into each category are summarized in the diagrams below.
We feel that classifying the definitions in this manner will
clarify and reinforce their meanings and help us makea point.
100 to 101
011 to 100
PERFORMANCE SPECIFICATIONS
010 to 011
001 to 010
000 to 001
Analog
0.00 1.25 2.50 3.75 5.006.25 7.50 8.75 10.00
Input
(DC Volts)
Figure 6. The digital output transitions of Figure 3 are plotted
as a function of input voltage. This plot conveys all the infor·
mation of Figure 3.
Relative
Absolute
Performance Specifications
Performance Specifications
Integral linearity
Full Scale Absolute Accuracy Error
Unipolar Offset Error
Differential Linearity
Relative Accuracy
Bipolar Offset Error
Monotonicity (D/A's)
Unipolar Zero Error
Bipolar Zero Error
No Missing Codes (AID's)
Gain Error
Drift Specifications
Drift Sper.ifications
Dynamic Specifications
Settling Time (D/A's)
Output Slew Rate (D/A's)
Conversion Time (AID's)
Throughput Rate (AID's)
Clock Frequency (AID's)
Digital
Output
111
110
101
100
011
DESIGN CHARACTERISTICS
AND REQUIREMENTS
010
001
000
0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.7510.00
0.625
8.125
Analog
Input
(DC Volts)
Figure 7. Analog inputldigital output transfer function of an
ideal, 3 bit, 0 to + 10V input range, binary code AID converter
trimmed so its first transition (000 to 001) occurs at + % LSB
(+ 0.625V) and its last transition (110 to 111) at FS-3/2 LSB
(+8.125V).
Lastly, note in Figure 3 that the LSB does not become a "1"
until the analog input reaches a full LSB. Some manufacturers will design their AID's so that the transfer function is
pushed down % LSB, i.e., the LSB becomes a "1" when the in·
put reaches + '/' LSB. This is shown in Figure 7. The rationale
behind the transfer function of Figure 3 is to have the transfer
function symmetrical within the entire input range. The first
transition occurs 1 LSB above zero; the last 1 LSB below 10V.
The code 001 corresponds to inputs between 1 and 2 LSB's.
4-6
Power Supply Range
Power Supply Rejection
Current Drains
Power Consumption
Reference Voltage
Reference Current
DIA CONVERTERS
Digital Input Coding
Input Logic Levels
I nput Loading
Glitch Energy
Compliance Voltage
Output Load Current
For D/A's with Input Registers:
1) Latch Enable Pulse Width
2) Data Setup Time
3) Data Hold Time
Others
AID CONVERTERS
Digital Output Coding
Output Logic Levels
Drive Capability (Fanout)
Input Logie Levels
Input Loading
Pulse Widths:
1) Start Command
2) Clock Low
3) Clock High
Start Signal Setup Time
Others
The RELATIVE PERFORMANCE SPECIFICATIONS describe
how the points that form a D/A's actual transfer function or
the quantization bands that form an AID's actual transfer
function relate to each other as a group. Are they all there?
How close to each other are they? Do they form a straight
line? etc .. The Relative Performance Specs look at the shape,
conformity, and orientation of the transfer function, not at its
location on its axes. The single most important Relative Per·
formance spec is Integral Linearity. The other important
Relative Performance Specifications are Differential Lineari·
ty, Monotonicity (for D/A's), No Missing Codes (for AID's), and
Gain Error. Gain Error is adjustable on most converters
avai lable today. For all but the most sophisticated converters
however, none of the other Relative Performance Specifica·
tions are adjustable.
The ABSOLUTE PERFORMANCE SPECIFICATIONS
describe what the Relative Performance Specs do not, the
location of the transfer function on its axes. They do not con·
cern themselves with the fine details of the transfer function.
For all practical purposes, they assume the transfer function
is a straight line and question how this line relates to the axes
it is plotted on. Does it pass exactly through zero? How close
is its positive full scale endpoint to where it is supposed to
be? How close is its negative full scale endpoint to where it is
supposed to be? All of the Absolute Performance Specifica·
tions are types of Absolute Accuracy Errors, and they must be
specified without adjustment, i.e., they must apply before any
optional gain and offset adjusting has been performed. The
specs we will discuss are Absolute Accuracy Error, Unipolar
Offset Error, Bipolar Offset Error, Unipolar Zero Error, and
Bipolar Zero Error.
The DYNAMIC SPECIFICATIONS are really only two specs.
They basically tell a user how fast an AID or a D/A gets its job
done. For many users, they are the most important specs.
We will discuss Settling Time for D/A's and Conversion
Time for AD's.
The DESIGN SPECIFICATIONS describe the properties and
requirements of converters that are fixed by design. For the
most part, they are selfexplanatory, and we will not spend
much time discussing them. Normally, designers do not
choose converters based on their Design Specifications. Oc·
casionally, someone will need an ultra·low power device or
maybe an AID that definitely has to be able to drive CMOS, but
usually people will select a converter based on its Perfor·
mance Specifications and tailor their system to meet the con·
verter's Design SpeCifications.
DRIFT SPECIFICATIONS-Almost all of the important con·
verter performance specifications are temperature sensitive,
i.e., they drift with temperature. These temperature in·
stabilities are important and are usually specified in terms of
the resultant change in a particular parameter (a delta) for a
given change in temperature, i.e., their units are usually VI ·C,
%FSR/·C, ppm/·C, ppm of FSR/·C, (fractions of an LSB)/·C,
or total change over a specific temperature range. Drift
specifications are called Temperature CoeffiCients, Temp·
cos, or T.C.'s. The T.C.'s we will concern ourselves with are
those for Integral Linearity, Differential Linearity, Gain, Offset
(Unipolar and Bipolar), and Absolute Accuracy. The effects of
each on converter performance will be discussed within the
section devoted to the appropriate room temperature
specification.
Most converter drifts are fairly linear, and manufacturers will
invariably assume they are linear when testing and measur·
ing them. To measure or test a tempco, a manufacturer will
measure a given parameter at two different operating
temperatures and calculate the tempco as the total change in
the parameter divided by the change in temperature. Normal·
Iy, if a manufacturer is guaranteeing performance over a O·C
to + 10·C temperature range, he will make test
measurements at O·C, at + 25·C, and at + 10·C. The range
chosen for calculating the T.C. can be O·C to + 25 ·C, + 25·C
to + 10·C, or O·C to + 10·C. Each may give a different
number for the T.C., and the largest number should be the one
that appears on the device data sheet.
Let's clarify ppm's before we get too far along since most
tempcos will appear as some number of ppm's/·C. PPM
stands for parts per million and can be thought of the same a
one thinks about percentages.
1ppm = lila' = 10" = 0.000001 = 0.0001 %
lppm of FSR = 1/10'FSR = 0.0001 %FSR
1% = 10'ppm
1 % FSR = 10'ppm of FSR
If a certain parameter is specified at + 25·C and carries with
it a T.C. of ± 20ppm/·C and the converter is presently
operating in an environment whose ambient temperature is
+ 125·C, we can expect the parameter to have changed (in
the worst case) by an amount a = change in temperature
times the tempco.
a =aT x (T.C.)
a = [ (+ 125·C) - (+ 25·C) 1x (± 20ppm/·C)
a = (100·C) x (± 20ppm/·C)
a = ± 2000ppm = ± 0.2%
The total value of the parameter at + 125·C will be equal to its
room temperature value plus its drift component (± 0.2%).
DIGITAL TO ANALOG CONVERTERS-RELATIVE
PERFORMANCE SPECIFICATIONS.
INTEGRAL LINEARITY-Integral Linearity, Integral Linearity
Error, Linearity Error, Linearity, and Non·Linearity are all the
same specification. They are not the same as Differential
Linearity which is discussed in the next section. Integral
Linearity is a measure of the "straightness" of a D/A con·
verter's transfer function. Refer to Figures 1 and 2. All the
points that constitute a D/A's transfer function should
theoretically form a perfectly straight line when connected
together. Figure 8 shows what an actual D/A transfer function
may look like. Integral Linearity is a measure of how far the
points deviate from a reference straight line drawn through
them as a group. Integral Linearity Error is usually expressed
in portions of an LSB (± V, LSB, ± V2 LSB, ± % LSB, etc.).
Oftentimes, if linearity error is greater than ± 1 LSB, it will be
expressed in %FSR or ppm of FSR.
Analog Output
(DC Volts)
8.75
750
6.25
5.00
3.75
2.50
1.25
....._ _ _ _-+---+-+----< Digital
0.00000 001 010 011 laO 101 110 111 Input
Figure 8. Transfer function of a nonideal, 3 bit, 0 to + 10V D/A
converter. Output points not forming a straight line is an In·
tegral Linearity Error. c.f. Figure 1.
4-1
There are presently two accepted definitions of Integral
Linearity; the two differ according to how they dictate the
reference straight line should be drawn.
1) END·POINT LINEARITY of a D/A converter is a measure of
the greatest deviation of the analog output values from a
straight line drawn between the end'points of the converter's
actual transfer function.
Analog Output
(DC Volts)
8.75
7.50
6.25
+1h LSS-------·
5.00
Analog Output
3.75
(DC Volts)
2.50
8.75
1.25
7.50
6.25
+% LSB
0.00
-------.
1-,........--+:---:_+___-:-,-+:--:"
001 010 011 100 101
5.00
Digital
110 111 Input
Figure 10. According to the best·fit definition of Integral
Linearity, the transfer function of Figure 8 has a ± V. LSB Integral Linearity Error. The most deviate points are + V. LSB
and - V. LSB away from the best-fit straight line.
3.75
2.50
1.25
------- -'h LSB
.-------
-% LSB
Dig;taJ
0.00000 001 010 011 100 101
110 111 Input
Figure 9. According to the end-point definition of Integral
Linearity, the transfer function of Figure 8 has a ± % LSB In·
tegral Linearity Error. The most deviate points are + % LSB
and - % LSB away from a straight line drawn through the
endpoints.
Figure 9 shows the actual D/A transfer function of Figure 8
with a straight line drawn between its end·points. The "ac·
tual" end-points of the transfer function are the measured
output voltages that appeared when the digital inputs were
000 and 111. Notice in Figures 8 and 9 that the actual end·
points are not the same as the ideal end· points of Figure 1
and that the reference straight line passes through the actual
and not the ideal end-points. The fact that the end·points and
the rest of the points that comprise the transfer function are
not located on the axes exactly where they are supposed to
be does not matter right now-that's an accuracy error.
Linearity views the points as an independent set and concerns itself only with how the points relate to each other, not
to the axes. Note that the most deviate transfer function
points are ± % LSB above and below the line and that
therefore, this converter has ± % LSB Integral Linearity ac·
cording to the end'point definition.
2) BEST·FIT STRAIGHT LINE LINEARITY of a D/A converter is
a measure of the deviation of the analog output values from a
best-fit straight line drawn through the group of points that
comprise the converter's actual transfer function. "Best-fit"
does not have a mathematical definition; the line is determined empirically by manipulation and can be defined simply as
the line that yields the best linearity spec.
± '12 LSB linear according to the best·fit definition may have
its endpoints anywhere within the band. Along that same line
of thought, best-fit linearity specifications will always be
symmetrical (± % LSB, ± 'I, LSB, etc.) while end-point
linearity specifications may be asymmetrical (such as + V.
LSB- % LSB).
Micro Networks feels that Integral Linearity is one of the most
important converter specifications, and we contend that an n
bit converter is not a true n bit converter unless it guarantees
± V. LSB Integral Linearity (by either definition) over
whatever temperature range it is to be used.
The traditional definition of linearity is the best-fit definition.
End-point linearity is growing in popularity as a result of the
microprocessor revolution. Many people are using
distributed processors located near AID converters and software to correct for converter inaccuracies. This is usually accomplished by locating the actual transfer function endpoints and relating the rest of the points to a hypothetical
straight line connecting the end-points. If linearity is
specified according to the end-point definition, a user already
knows how far away from the hypothetical line the rest of the
transfer function points are and the corrected accuracy will
be as good as the converter's linearity. If linearity is specified
according to the best-fit definition, the user will not know how
his hypothetical straight line compares to the best-fit straight
line used to measure the linearity. For the person not using
either hardware or software to correct the accuracy of their
converter, it makes no difference which definition of linearity
has been used by the manufacturer.
Figure 10 repeats the non·ideal D/A transfer function of
Figure 8 with a "best·fit" straight line drawn through the
transfer function. Notice that the line does not pass through
the transfer function end-points and that the furthest points
away from the line are only ± V. LSB away. This converter has
± V. LSB Integral Linearity according to the best-fit straight
line definition. If you find it difficult to think in terms of a best·
fit straight line, you can simply say that all the points of the
transfer function fall in a band 1 LSB wide.
In a strict mathematical sense, the end-point definition is a
more conservative measure of Integral Linearity than the
best-fit definition. A converter tested to some linearity (say
± V. LSB) according to the best-fit definition may be half as
linear (twice as nonlinear or± 1 LSB) according to the endpoint definition. In reality, the reference line used for either
definition almost always turns out to be the same line, and in
all but the most sophisticated applications, a user would be
hard pressed to tell the difference between a converter that
was ± V. LSB linear according to the best-fit definition and
one that was ± V. LSB linear according to the end-point
definition.
In actuality, if a D/A converter has ± V. LSB Linearity accor·
ding to either definition, all of its transfer function pOints will
fall in a band 1 LSB wide. The converter that is ± V. LSB linear
according to the end-point definition will, by definition, have
its endpoints in the center of the band. The converter that's
People often speak of converter linearity in terms of bits. They
will say a converter has 12 bit linearity if its linearity spec is
equivalent to ± V. LSB for 12 bits (± 0_012% FSR), regardless
of the number of input or output bits the converter actually
4-8
has. They'll say it has 11 bit linearity if its linearity spec is
equivalent to ± '/2 LSB for 11 bits (±0.024%FSR); or 8 bit
linearity if its linearity spec is equal to ± 1;' LSB for 8 bits
(± 0.195%FSR). You'll come across 14 bit converters with 12
bit linearity and 12 bit converters with 11 bit linearity. You'll
see 12 bit converters that have 12 bit linearity at room
temperature, but their linearity drifts to 10 bits at + 125"C
(see Linearity Drift). You will also see devices whose linearity
exceeds their resolution. Some 12 bit converters have 13 bit
linearity, i.e., their linearity spec is ± 0.006% FSR (';' LSB for
13 bits, '14 LSB for 12 bits). Many 8 bit converters will have bet·
ter than 8 bit linearity.
For D/A converters, ± 1;' LSB Integral Linearity (by either
definition) guarantees Monotonicity and ± 1 LSB Differential
Linearity. For most converters, Integral Linearity is not adjustable.
DIFFERENTIAL LINEARITY-Differential Linearity is also
called Differential Linearity Error or Differential Nonlinearity.
If the digital input code to a D/A is changed from its present
code to either the next higher or next lower code, the analog
output level should increase or decrease an amount
equivalent to one LSB. In other words, adjacent digital codes
should result in measured output values that are exactly one
LSB apart. Any deviation of the actual "step" size from the
ideal one LSB is called a Differential Linearity Error or a Differential Nonlinearity, and the error is usually expressed in
(sub)multiples of an LSB.
A maximum Differential Linearity Error of ± Vz LSB means
that output step sizes can have a height of 1 LSB ± '/2 LSB,
i.e., the output voltage can change anywhere from '/2 to 1%
LSB's when the input changes from one code to the next.
Figures 11 through 14 show sketches of a 3 bit, 0 to + 10V,
binary coded, D/A transfer function. The first (Figure 11) is
ideal; it is a repeat of Figure 1. Each output step is 1 LSB
high,and the Differential Linearity Error is zero LSB's. The second (Figure 12) has ± '12 LSB Differential Linearity Error.
Note that some steps are ,/, LSB high (1 LSB- 'I, LSB) others
are 1 Vz LSB's high (1 LSB + % LSB). Figure 13 shows the
transfer function of a D/A with ± 1 LSB Differential Linearity.
Some steps are 0 LSB's high and others are 2 LSB's high. This
converter is still monotonic. Figure 14 shows the transfer
function of a nonmonotonic converter. Its Differential Linearity is ± 1% LSB's. Note that some steps are negative 1;' LSB
(1 LSB-l% LSB) while others are 2';' LSB's (1 LSB + 1'1, LSB).
Converters with Differential Linearity Errors greater that ± 1
LSB may be Nonmonotonic (see section discussing
Monotonicity).
Analog Output
(DC VoltSI
875
7.50
625
5 00
375
250
+ ',. LSB
1.25
a 00
000 001 010 all
100 101
110
111
9~~~~'
Figure 12_ Nonideal, 3 bit, D/A transfer function having a ± Vz
LSB Differential Linearity Error. Some of the output steps are
+ 'Iz LSB high; others are + 1 '12 LSB's high.
Analog Output
(DC Volts)
I
875
7.50
6.25
5.00
t2 LSB's
3.75
2.50
1.25
.------- +0 LSS's
Digital
0.00 000 001 010 0'"
100 101
110
111 Input
Figure 13. Nonideal, 3 bit, D/A transfer function having a ± 1
LSB Differential Linearity Error. Some of the output steps are
oLSB's high (no change in output voltage following a change
in input code); others are + 2 LSB's high.
Analog Output
(DC Volts)
8.75
7.50
6.25
5.00
3.75
Analog Output
(DC Volts)
+21f2 LSB's
2.50
1.25
0.00+-__>-_--<_ _ _ __....___ Digital
Input
000 001 010 all 100 101 110 111
8.75
7.50
6.25
+1 LSB
5.00
3.75
Figure 14_ Nonideal, 3 bit, D/A transfer function having ± 1 'Iz
LSB Differential Linearity Error. Some of the output steps are
- 'Iz LSB high (output goes down when input goes up); others
are + 2% LSB's high. This converter is nonmonotonic.
2.50
+1 LSB
1.25
.------------_
~
000 001 010 011 100 101
~~
110 111 Input
Figure 11_ A repeat of the ideal, 3 bit, D/A transfer function of
Figure 1_ Each output step or discontinuity is 1 LSB high.
Return to Figures 12 and 13. Both of these converters still
have better than ± Vz LSB Integral Linearity according to the
best-fit straight line definition but not according to the endpoint definition. ± Vz LSB Integral Linearity by either definition, however, guarantees that Differential Linearity Error will
be better than ± 1 LSB, i.e., maximum Differential Linearity
Error has an upper bound equal to two times the Integral
4-9
Linearity Error. It can be less than 2X Linearity, however, and
some manufacturer may choose to test and specify it as be·
ing such. For example, a converter may specify ± V. LSB In·
tegral Linearity and ± % LSB Differential Linearity. If it
specifies ± V2 LSB Integral Linearity and says nothing about
Differential Linearity, one can only assume that maximum
Differential Linearity will be ± 1 LSB.
Two last comments-maximum Differential Linearity Error
does not allow one to infer anything about Integral Linearity
Error. One popular manufacturer, for example, advertises
their 12 bit D/A as having ± V. LSB Differential Linearity from
·55·C to + 125 ·C. Integral Linearity, however, over the same
temperature range is specified at ± 2 LSB's (10 bit Integral
Linearity).
Differential linearity errors do not have to be symmetrical. If a
converter had no output steps smaller than + V. LSB and
none larger than + 2 LSB's, its Differential Linearity Error
would be - V., + 1 LSB.
MONOTONICITY-Monotonicity is more a property of a DIA
converter than it is a specification. Either a converter is
monotonic or it is not. The relevant specification is the
temperature range over which Monotonicity is guaranteed.
Monotonicity means that the analog output of a D/A does not
decrease as the digital input is increased nor increase as the
digital input is decreased. This definition allows the output to
remain the same as the digital input is increased or decreas·
ed. It is the same as saying that the derivative of the transfer
function is always greater than or equal to zero.
Micro Networks prefers a slightly more strict definition which
demands that the analog output always increase (decrease)
as the digital input is increased (decreased).
Another way of defining Monotonicity is to say that Differen·
tial Linearity Error must be less than - 1 LSB. In other words,
steps can be any size as long as they are greater than zero,
i.e., as long as they are positive. Monotonicity is a very impor·
tant parameter for D/A's used in servo applications. One
always wants to be sure that a system drive signal is going up
or down when it is supposed to. Nonmonotonicity can result
in positive feedback and loop instabilities.
Monotonicity does not guarantee Differential Linearity (other
than to the degree just stated), nor does it guarantee Integral
Linearity. Monotonic converters can have very large positive
steps or series of smaller positive steps that result in highly
nonlinear transfer functions. The transfer functions of Figure
15 are monotonic but nonlinear.
Analog Output
(DC Volts)
Analog Output
(DC Volts)
:::~,/"/,,,"''''
.:
,':
0.00 :
000
:::LL. /
... , ..
".
••••..
8.75l£. . . .
100
111
5.00
000
••
Digital
111 Input
>i
000 ...•...•...
. 000
100
Digital
100
111 Input
Figure 15. Three examples of D/A transfer functions that are
monotonic but highly nonlinear. Monotonicity guarantees
that Differential Linearity will be > - 1 LSB, but it gives no
guarantees about Integral Linearity.
4·10
Beware of converters that guarantee Monotonicity and even
Differential Nonlinearity over some temperature range but do
not mention what happens to Integral Linearity over the same
range. They could exhibit severe "bowing" of the transfer
function as shown in Figures 15a and 15b.
REMEMBER: ± V. LSB Integral Linearity Error will guarantee
Monotonicity and Differential Linearity Error better than ± 1
LSB. Monotonicity and Differential Linearity, however, give
no guarantees about Integral Linearity. A Monotonic transfer
function is not necessarily a straight one.
INTEGRAL AND DIFFERENTIAL LINEARITY DRIFTSRecall that Integral Linearity is usually specified as a % of
FSR or in fractions of an LSB. Integral Linearity Tempcos are
usually given in ppm's of FSRI·C.lf a 12 bit D/A converter has
± V. LSB (± 0.Q12% FSR) Integral Linearity at + 25·C and a
± lppm of FSRI·C Linearity Tempco, its Linearity at + 125·C .
will be equal to its room temperature value plus its drift from
+ 25·C to + 125·C. The drift will equal:
a = aT x (T.C.)
a=(100·C)x(±lppm of FSR/°C)
a = ± 100ppm of FSR
a= ±O.OI%FSR
Therefore, at + 125·C, the converter Linearity becomes
(room temp value) + (drift) = (± 0.012% FSR) + (± 0.Q1 % FSR)
= ± 0.22% FSR. ± 0.22% FSR is almost equivalent to 1 LSB
for 12 bits (0.024% FSR) or V. LSB for 11 bits. Therefore, at
+ 125·C this converter would only have 11 bit Integral Linear·
ity which would mean that its effective resolution has been
reduced to 11 bits. In other words, the converter manufacturer
is saying that at + 125 ·C, he no longer guarantees
Monotonicity.
Most Micro Networks converters are guaranteed to be
± V. LSB Linear at room temperature and ± V2 LSB Linear
over their entire operating temperature range. For can·
verters that don't hold ± V.LSB Linearity over temperature,
we will give a linearity spec at + 25·C and another spec
that applies over the entire operating temperature range.
Our MN565AJ 12·bit D/A, for example, guarantees ± V2 LSB
linearity at room temperature and ± 3/4 LSB from O°C to
+70 oC.
Recall that Differential linearity Error is usually specified as
a % of FSR or in fractions of an LSB. Differential Linearity
Tempcos are usually given in ppm's of FSR/oC.lf a 12 bit D/A
converter has a maximum Differential linearity of ± '12 LSB
at + 25·C and a Differential linearity Tempco of ± 2ppm of
FSR/oC, its Differential linearity at + 125·C will be:
± '12 LSB + [ (100·C) x (± 2ppm of FSR/·C) 1
± V. LSB + (± 200ppm of FSR)
± 0.012%FSR + (± 0.02%FSR)
±0.32%FSR.
This is greater than ± 1 LSB. At + 125°C, this 12 bit converter
may have become nonmonotonic. We say "may have become
non monotonic" because it is possible that the converter
transfer function bowed upwards such that the step sizes
got larger but the device stayed monotonic. Normally,
however, when this type of drift phenomenon occurs, the
manufacturers will be proud of the fact that they have main·
tained Monotonicity and will say something to the effect of
"Monotonicity guaranteed over temperature". If such a
statement does not appear, a user can only assume that the
converter became nonmonotonic when Differential lineari·
tyexceeded ± 1LSB. At what temperature did that occur for
the device mentioned above? At what temperature did its
Differential Linearity Drift exceed ± V. LSB?
± 'Iz LSB = ± 0.012% of FSR = 120ppm of FSR. If Differen·
tiallinearity Drift is ± 2ppm of FSR/·C, it will take 60°C for
the drift to equal ± '12 LSB. Therefore, the converter became
non monotonic at + 25·C + (+ 60·C) = + 85 ·C.
What Differential Linearity Drift would a 12 bit D/A that
guaranteed ± ';' LSB Differential Linearity at room
temperature (+ 25 ·C) have to maintain in order to maintain
Monotonicity up to + 125·C? ± V. LSB= 120ppm of FSR.
120ppm of FSR/.H = 120ppm of FSR/100·C = 1.2ppm of
FSR/·C
Lastly, recall that ± '12 LSB Integral Linearity guarantees
Monotonicity and Differential Linearity less than ± 1 LSB for
D/A converters. A D/A that guarantees ± V. LSB Linearity and
Monotonicity at room temperature and then gives an Integral
Linearity Drift specification without specifically stating what
happens to Monotonicity or Differential Linearity over
temperature is not guaranteeing monotonicity at any
temperature other than + 25 ·C.
RELATIVE ACCURACY-Relative Accuracy is a confusing
specification, and you will not see it used on a Micro
Networks data sheet. It is the data converter specification
that has the greatest variety of definitions from different
manufacturers. Micro Networks defines the Relative Accuracy of a D/A converter to be the measure of how accurate
any of the D/A's output states are relative to a straight line
drawn between the endpoints of the D/A's actual transfer
function. Relative Accuracy is usually expressed in
(sub)multiples of LSB's or in %FSR, and according to our
definition, is exactly the same as Integral Linearity Error according to the end-point definition. Relative Accuracy does
not include Gain and Offset Errors (to be discussed).
Some manufacturers have defined D/A Relative Accuracy to
be the accuracy of any output state relative to the converter
reference. This may be a fine definition for fixed external
reference or for multiplying D/A converters, but it makes little
sense when applied to the large majority of internal reference
Dual-in-Line packaged D/A's. Most of these devices are functionally laser trimmed as assembled devices, and neither the
manufacturer not the user ever know what the actual voltage
of the internal reference is.
As a data converter specification, Relative Accuracy has two
uses. Firstly, many manufacturers will use it for the purpose
of informing a user how accurate, relative to the ideal, he/she
can expect his/her D/A to be after its initial Gain and Offset
Errors have been adjusted to zero through the use of trimming
potentiometers. As an example, take the 3 bit, 0 to + 10V D/A
we've been discussing. If the manufacturer guarantees
Relative Accuracy = ± 1j, LSB, and the user adjusts the output so it is exactly OV when the input is 000 and exactly
+ 8.75V when the input is 111, every other analog output will
be within ± ';' LSB (0.625 volts) of where it is ideally supposed
to be. In this respect, we agree with the manufacturer who
defines Relative Accuracy to be" ... the deviation of the analog
value at any code (relative to the full analog range of the
device transfer characteristics) from its theoretical value
(relative to the same range), after the full-scale range (FSR)
has been calibrated". The second use of Relative Accuracy is
that some manufacturers will use it in lieu of an Integral
Linearity Error spec. This is fine if the intent is not to deceive.
We stated earlier that in order for an n bit converter to be a true
n bit converter, its Integral Linearity Error should be no worse
than ± 1j, LSB for n bits. Many times, when Relative Accuracy
appears in lieu of Integral Linearity Error, we have noticed the
error to be greater than ± 1j, LSB.
Beware of high resolution converters (12 bits and up) that
spec "accuracies" better than ± 2 LSB's. As a practical matter, such levels are difficult to achieve in state·of·the·art D/A's
without external gain and offset adjustments. The manufac·
turer probably means Relative Accuracy.
GAIN ERROR-Gain Error is also called Range Error, Scale
Error, or Scale Factor Error, and it has a number of differently
stated definitions that all basically mean the same thing.
Gain Error is a measure of the deviation from the ideal of the
slope of a converter's transfer function. The slope of a con·
verter's transfer function is defined as the slope of a straight
line connecting its endpoints. The slope of the ideal transfer
function as plotted in Figures 1 and 2 is 45· or 1. A device with
negative Gain Error would have a less steep transfer function.
A device with positive Gain Error would have a more steep
transfer function. See Figure 16. Gain Error is normally
Analog Output
(DC Volts)
10.00
B.75
/
7.50
/
/
/
/
/
6.25
/
/
/
/
5.00
/
/
/
3.75
/
(a)
/
/
I
/
2.50
/
/
/
1.25
/
/
0.00 ~_-___000 001 010 011
......._ -.......~ ~~g~~~1
100 101 110 111
Analog Output
(DC Volts)
+7.5
+5.0
OO~O-OD+-'-D'+-O-O+-"-/-,/''-+:''.4'''''''''111
/
Digital
I n put
/
/
/
/
/.
/
/
/
- 5.0
- 7.5
(b)
-10.0
Figure 16. Sketches show the effect of positive Gain Error on
the transfer function of a unipolar D/A converter (a) and theef·
fect of negative Gain Error on the transfer function of a
bipolar D/A converter (b). The ideal transfer functions are
shown as broken lines; the transfer functions with Gain Error
as solid lines.
measured using one of two methods. In method 1, a unipolar
converter is first offset adjusted, either through hardware or
software, until the zero end of its transfer function is pulled
exactly into zero. A bipolar converter is first offset adjusted
until the negative full scale end of its transfer function is pull·
ed into its ideal value. Then the positive full scale output
values are measured and compared to the ideal values. For
the unipolar converter, Gain Error will be the difference bet·
ween the measured and the ideal full scale output expressed
as a % of the ideal output level. For the bipolar converter,
Gain Error will be the difference between the measured and
the ideal values of the total change from the negative full
scale output to the positive full scale output expressed as a
percentage of the ideal value. Method 2 consists of
measuring the unipolar converter's actual, unadjusted
positive full scale output and subtracting its actual zero out·
put. For bipolar converters, the actual, unadjusted positive
full scale output is measured and the actual minus full scale
output is subtracted from it. The difference between the
4·11
resulting number and the ideal value forthis number (FSR -1
LSB) expressed as a % of the ideal is the Gain Error. Gain Er·
ror can be defined as the difference between the measured
and the ideal values of the converter's full output range
(which is equivalent to the converter's FSR -1 LSB). Because
the final number that results from measuring Gain Error by
either method is a voltage, Gain Error specifications may
sometimes appear in units of % FSR.
a
EXAMPLE: Recall the 3 bit, to + 10V D/A of Figure 1. Its output for a 000 input is supposed to be OV. Its output for a 111 in·
put is supposed to be + 8.75V. Its ideal full output range is
equal to + 8.75V -OV = + 8.75 volts (FSR -1 LSB). If its· actual 000 output was + 0.05V and its actual 111 output was
+ 8.85V, its actual full output range would be + 8.80 volts. Its
Gain Error would be (8.80 - 8.75)/8.75 = 0.57%. See Figure 17.
If the converter's actual 000 output was -0.05V and its actual
111 output was + 8.70V, its actual full output range would be
+ 8.75V and its Gain Error would be zero. It would have an Off·
set Error and hence an Absolute Accuracy Error, but it would
not have Gain Error. See Figure 17 and please read the sec·
tions describing Absolute Accuracy and Offset Error.
Analog Output
(DC Volts)
"~I
tellS you how accurate your converter is going to be if you
simply plug it in, power it up, and start converting. Relative
Accuracy tells you how accurate it will be after you go
through the gain and offset error adjusting procedure.
"Given" refers to the fact that any Absolute Accur,acy
specification has to be accompanied by some indication of
where along the converter's input/output transfer function
the spec applies, i.e., at what input code the Absolute Ac·
curacy of the output is to be measured.
Because Absolute Accuracy Error is measured and specified
without adjustment, it includes all factors that may be affecting a converter's accuracy at the point of measurement-Of·
fset Error, Gain Error, Linearity Error, and Noise Error. Refer
back to Figure 1. Assuming the transfer function is linear, the
two key points necessary to fully describe this converter's
Absolute Accuracy are at positive full scale (digital input 111)
and at zero (digital input 000). To avoid ambiguity, the specs
would be called Unipolar Positive Full Scale Absolute Ac·
curacy Error and Unipolar Zero Absolute Accuracy Error(also
called Unipolar Zero Error). Refer back to Figure 2. The three
key pOints necessary to adequately describe the Absolute
Accuracy of this device are at positive full scale (digital input
111), negative full scale (digital input 000), and zero (digital in·
put 100). The three relevant specifications are Bipolar Positive
Full Scale Absolute Accuracy Error, Bipolar Negative Full
Scale Absolute Accuracy Error, and Bipolar Zero Absolute Accuracy Error (also called Bipolar Zero Error).
(a)
FULL SCALE ABSOLUTE ACCURACY - This is the Absolute
Accuracy Error measured when the output of a D/A is suppos·
ed to be at its full scale value. Some manufacturers will draw
a distinction between Unipolar and Bipolar Positive and
Negative Full Scale Absolute Accuracy Errors. Micro Net·
works normally does not. For a converter's unipolar positive,
unipolar negative, or bipolar output ranges, our Full Scale Ab·
solute Accuracy Error specification refers to either the
positive or negative full scale point or both, whichever is appropriate. Take our MN3013 and MN3014 8 bit D/A's for exampie. These devices have user-selectable output ranges of a to
+ 10V,Oto - 10V, ± 5V, and ± 10V, and ourdatasheetgivesa
single Full Scale Absolute Accuracy Error specification. The
spec applies to all the full scale output points, i.e., it means
Unipolar Positive Full Scale Absolute Accuracy when using
the a to + 10V range; Unipolar Negative Full Scale Absolute
Accuracy when using the to - 10V range; and both Bipolar
Positive and Bipolar Negative Full Scale Absolute Ac·
curacies when using the bipolar ranges. We will call out the
different Full Scale Absolute Accuracy Errors separately only
if they have different values.
a
Figure 17. The ideal D/A transfer function is sketched as the
broken line. The solid line above it has a positive 0.57% Gain
Error (a). The solid line below it has zero Gain Error (b).
Gain Error is not an accuracy measurement, although as you
will see, it can be used to calculate a converter's Absolute Ac·
curacy Error when this spec is not given.
D/A CONVERTERS-ABSOLUTE PERFORMANCE
SPECIFICATIONS
ABSOLUTE ACCURACY ERROR-The Absolute Accuracy
Error of a voltage output D/A converter is the difference bet·
ween the actual, unadjusted output voltage that appears
following the application of a given digital input code and the
ideal or expected output voltage for that code. This difference
is usually expressed in LSB's or % FSR.
The two key words in this definition are "unadjusted" and
"given". "Unadjusted" means just that; a D/A converter's Ab·
solute Accuracy has to be measured before any optional gain
and offset adjusting is performed. This is how Absolute Ac·
curacy differs from Relative Accuracy. Absolute Accuracy
4·12
ZERO ERROR-This is the Absolute Accuracy Error
measured when the output of the D/A is supposed to be zero
volts. Micro Networks will draw a distinction between
Unipolar and Bipolar Zero Errors for converters that have dif·
ferent values for these two specifications. Otherwise, we will
simply give a single Zero Errorspecification. Our MN3850 and
MN3860 12 bit D/A's have user·selectable output ranges of a
to + 5V, a to + 10V, ± 2.5V, ± 5V, and ± 10V, and the data
sheet lists a single Zero Error of ± 0.05% FSR at + 25·C and
± 0.1 % FSR over the entire operating temperature range. This
spec applies to both Unipolar and Bipolar Zero Error depen·
ding upon which output range is being used.
Unipolar and Bipolar Full Scale Absolute Accuracy and Zero
Errors are summarized in Figure 18. The transfer function
shown in Figure 19 has a Negative Full Scale Absolute Accuracy Error of + 2.5 volts (+ 1 LSB), a Bipolar Zero Error of
- 0.625 volts (- % LSB), and a Positive Full Scale Absolute
Accuracy Error of - 3.125 volts (- 1 % LSB's). As will be explained in the following sections, Full Scale Absolute Ac·
curacy and Zero Errors are the way in which Micro Networks
prefers to specify converter accuracy.
Analog Output
IDC Volts)
Analog Output
IDC Volts)
+7.5000
Unipolar
Positive
Full Scale
Absolute
Accuracy
8.75
t
/
1
1', LSB
/
4.3750
i
/
/
Error
000 001
T
010 011
.,
/
1
la)
,
/
,
i
.
Digital
111 Input
110
'f. LSB
7.5000
-10.0000
u~~~~ar
0.00
+---,,L-=---:-t---+,--__.......- ....
Digital
111 Input
Error
T
Figure 19. Example of a 3 bit, ± 10V output range D/A con·
verter with a Bipolar Negative Full Scale Absolute Error of
+ 2.5 volts (1 LSB), a Bipolar Zero Error of - 0.625 volts ( - '/.
LSB), and a Bipolar Positive Full Scale Absolute Accuracy Er·
ror of - 3.125 volts ( - 1 % LSB's).
Analog Output
IDC Volts)
1
Digital 0t-00_+-......._-+-_ _ _ _~4-_+ 0.00
Input
u~~~~ar
Error
T
Unipolar
Negative
Full Scale
Absolute
Accuracy
Error
-8.75
(b)
1
Analog Output
IDC Volts)
1
Bipolar
Positive
Full Scale
Absolute
Accuracy
Error
+7.5
T
Digital
111
Input
Bipolar
Negative
Full Scale
Absolute
Accuracy
-10.0
(e)
Error
i
Figure 18. Summary of Full Scale Absolute Accuracy and
Zero Errors for unipolar positive D/A converters (a), for
unipolar negative D/A converters (b), and for bipolar D/A
converters (c).
OFFSET ERROR-D/A Offset Error is an Absolute Accuracy
Error that by definition has to be measured at a particular
place along the converter's transfer function. It is the only
widely used converter spec that is not a "black box" type of
specification. The user has to have some understanding of
how the converter works because the point of error measure·
ment (the point where the spec applies) is determined by con·
verter design. Linearity Error, Absolute Accuracy Error, Gain
Error, and the other performance specifications relate only to
a converter's transfer function and allow the user to think of
the converter as a "black box". For this reason, Micro Net·
works does not like to specify Offset Errors. A converter's Off·
set Error will always be the same as either our Zero Error or
Full Scale Absolute Accuracy Error,and we much prefer these
specs, for we believe that most converter users prefer to think
of converters as building blocks with certain input/output
characteristics and that they really don't care what goes on
inside of them. Many of our data sheets do list Offset Errors,
however; the specs are there solely to facilitate comparing
our converters to those of other manufacturers who prefer to
spec Offset Errors.
For a quick understanding of how most D/A converters
operate, see Figure 20. The figure is a simplified schematic
for the 3 bit, 0 to + 10V, straight binary coded D/A whose
transfer function is shown in Figure 1. The converter consists
of 3 binary weighted current sources, 3 digitally·controlled
electronic switches, and an output operational amplifier that
converts the switch currents to an output voltage. The current
sources are constant; they always push the current indicated
('12 mA for the MSB current source, V. mA for the Bit 2 current
source, and y. mA for the Bit 3 current source) in the direction
indicated. The digitally·controlled electronic switches are
simple; they are connected directly to the D/A's digital inputs.
When a logic "1" is applied toa given digital input, the respec·
tive switch moves to the right connecting its current source to
the summing junction of the output amplifier. When a logic
"0" is applied, the given switch moves to the left disconnecting the current source from the summing junction and connecting it to ground. The current labeled IDAC is the total current being pulled from the amplifier summing junction by the
current sources. The output op amp is an an inverting
amplifier configuration with a 10n feedback resistor such
that the D/A output voltage (Vout) is always equal to
IDAC x 10Kn.
4-13
I
Analog Output
(DC Volts)
10.00
/
/
I
8.75
I
I
I
7.50
/
/
/
6.25
/
/
5.00
/
/
IIDACPlRF~10K!l
L-~---+-~~~_-'--~
I
3.75
/
/
/
2.50
-
Analog
...
Output
I
When the code 000 is applied, all the switches are to the left,
and all the current sources are connected to ground.
IOAC = 0, and Vout = O. When the code 100 is applied (the
state indicated in the sketch), the MSB current source is
connected :\0 the output op amp, and the other current
sources are connected to ground. IOAC = ';' mA, and
Vout = + 5V. When the code 110 is applied,
IOAC = 'h + '/. = % mA; Vout = + 7.5V. When the code 111
is applied, IOAC = 'h + '/. + Y, = 'kmA; Vout = + B.75V. That's
simpleeno~gh. If this converter were constructed with elec·
tronic switches that went to the left with "1 's"applied and to
the right with "O's"applied, we'd have a 3 bit, 0 to + 10V O/A
with complementary binary coding. 000 applied would move
all the switches to the right. IOAC would equal 'is mA, and
Vout would be + B.75V. 111 applied would move all the swit·
ches to the left.IOAC would equal 0 mA, and Vout would be
OV.
O/A converter Offset Error (actually, in this example,
because we are discussing a unipolar converter we should
specify Unipolar Offset Error, but the definition is the same)
is the Absolute Accuracy Error measured when the digital
inputs are such that IOAC is supposed to equal zero. Offset
Error is usually measured in volts and specified in LSB's or
%FSR. It is IOAC not equalling zero when it is supposed to
coupled with the offset error of the output op amp that result
in O/A Offset Error. IOAC not equalling zero is primarily due
to switch leakage in the "off" state.
I
1.25
/
/
0.00
Figure 20. A simplified schematic for the 3 bit 0 to + 10V O/A
of Figure 1. A logic "1" applied moves the switches to the
right. A logic "0" applied moves the switches to th'3 left.
/
DIgital
001 010 011
100 101
110 111 Input
Figure 21. Unipolar Offset Error has the effect of displacing
the transfer function along the voltage (output) axis parallel
to itself. The broken line shows the ideal O/A transfer func·
tion. The solid line shows the transfer function of a O/A that
has a Negative Unipolar Offset Error.
Virtually all converter users think that Offset Error is the
same as Zero Error. It is not.
Many manufacturers will define O/A Offset Error to be the
analog output error that occurs when the digitally·
controlled switches are in the "off" position. This definition
is the same as the IOAC = 0 definition, but it is confusing
because it is often not clear what "off" means for complementary coded converters.
What is Bipolar Offset Error? First we have to understand
how bipolar converters work. First we must realize that the
bipolar transfer function looks just like a unipolar one that
hild been offset (moved down) ';' FSR (the value of an MSB).
This offsetting effect is accomplished in actual converters
by adding a constant current (equivalent to the MSB current)
to the summing junction of the output amplifier. See Figure
22. It is the same as Figure 20 except that an additional 'h
mA current source has been permanently attached to the
summing junction of the output 00 amp. The result is that
Vout now equals (IOAC - 'h mA),. 10K. Therefore, when the
input code is 100, IOAC = 'h mA, and Vout = OV. When the
code is 111, IOAC='/, mA, and Vout= +3.75V. The 0 to
+ 10V O/A converter of Figure 20 has become a ± 5V O/A
converter.
Offset Error adds a constant error voltage, the offset
voltage, to all the output levels of a voltage output O/A.1t has
the effect of sliding the transfer function up or down along
the output (voltage) axis parallel to itself. Figure 21 shows
the transfer function of a unipolar O/A that has only
Unipolar Offset Error, i.e., it has no Gain Error.
"Why," you may be asking, "do I have to understand how the
converter works to understand Offset Error? Why don't you
simply say it's the error measured when the output is sup·
posed to be zero volts? How is it different from Zero Error?"
For 90% of unipolar converters it isn't. For these devices
there is no difference between Unipolar Offset and Unipolar
Zero Error. There is a distinct subset of Unipolar O/A con·
verters, however, for which Unipolar Offset Error has to be
measured at one of the full scale outputs. These will be
discussed shortly. For bipolar O/A's, Bipolar Offset Error is
hardly ever measured at the zero volt output. This will also
be discussed shortly.
4·14
Analog
Output
Figure 22. The 0 to + 10V 3 bit O/A of Figure 20 has been con·
verted into a ± 5V 3 bit O/A by attaching a V2 mA constant cur·
rent source to the summing junction of the output op amp.
Bipolar Offset Error is still the Absolute Accuracy Error
measured when the digital inputs are such that IDAC is sup·
posed to = O. It is IDAC not equalling zero and the per·
manently attached '12 mA current source not equalling ex·
actly V2 mA coupled with the offset error of the output op
amp that result in Bipolar Offset Error. For this converter, as
well as for 90% of all other bipolar D/A's, Bipolar Offset Er·
ror occurs at the minus full scale output. It is not equivalent
to Bipolar Zero Error. For these converters, it is the same as
Negative Full Scale Absolute Accuracy Error. As you might
suspect, there is a subset of bipolar D/A converters for
which the IDAC = 0 condition occurs at positive full scale.
These will also be discussed shortly.
Bipolar Offset Error affects a converter's transfer function
the same way Unipolar Offset Error does. It Slides the func·
tion up or down along the voltage axis parallel to itself adding
a constant offset voltage to each output level. The transfer
function of a bipolar converter having only Bipolar Offset Er·
ror (no Gain Erro~ is sketched in Figure 23. Let's now explore
the subsets of converters mentioned above, those unipolar
DIA's whose Unipolar Offset Error does not occur at zero and
those bipolar DIA's whose Bipolar Offset Errordoes not occur
at their minus full scale point. Figure 24 shows a popular
digital to analog conversion technique that employs PNP
transistors acting as equally weighted current sources and
an R·2R resistor ladder acting as a current dividing network.
For years, the only 12 bit DIA's capable of holding ± '12 LSB
linearity over the - 55·C to + 125·C temperature range were
designed this way. The circuit shown is for a 3 bit voltage out·
put DIA. The output range is 0 to -10 volts such that a 000
digital input (TTL levels) will give a zero volt output and a 111
input will give a - 8.75V output (minus full scale plus 1 LSB).
One least significant bit (LSB) will be equal to 10
voltsl2' = 1.25 volts. The transfer function is sketched in
Figure 25.
Digital signals applied to the appropriate input pins turn the
current sources (transistors 0"0,, and 0,) on or off. The R·2R
ladder network divides each transistor'S collector current
between ground and the converter's output op amp in a man·
ner such that the portion of each collector current that
reaches the output op amp is binarily weighted according to
the transistor's position.
Analog Output
(OC Volts)
,. ,.
+7.5
+5.0
+2.5
000 001 010
;
;
,.,.
,.
/
,. ,.
/
,. ,.
,.
,.
,.
/
/
Digital
Input
101
110 111
- 2.5
- 5.0
- 7.5
-10.0
Figure 23. Bipolar Offset Error has the same effect as
Unipolar Offset Error. The solid line shows the transfer func·
tion of a DIA that has a positive Bipolar Offset Error.
The reference voltage (- VREF) is equal to - 10V, and RREF
is equal to 20K. Node A is a virtual ground. IC1, the collector
current of transistor 0" equals VREF/RREF + 0.5mA, and
IE1 = IC1· The transistor bases are strapped together, and the
RE'S are chosen such that the bases are biased at + 1.4V. Op
amp A, is used to maintain Node B at a constant voltage as
the transistors are switched on and off and the IE'S change.
Assuming the transistors are in their forward active regions
of operation and all the RE'S are equal to each other (and not
worrying about the switching diodes right now) makes
IE1 = IE2 = IE3 = IE4 and IC1 =IC2 = IC3 = IC4. The transistor
emitters(the switching diode anodes) are all at approximately
+ 2.0V (transistor VBE = - 0.6V). The cathodes of the swit·
ching diodes (D" D" D,) are the digital inputs to the converter.
Digital signals applied to the converter's digital inputs turn
the switching diodes and hence the transistors on and off. A
TTL logic "0"( + O.BV maximum) applied to the converter's
digital inputs (the diode cathodes) will forward bias the
diodes. This results in the emitter voltages being pulled down
to 1.4 volts (+ O.BV for the digital input plus + 0.6V for the
diode drop) removing forward bias from the base emitter junco
tion and turning off the transistors. Collector currents go to
zero. The currents that flow through the RE'S are sunk in the
digital signal sources. The application of a TTL logic "1"
(+ 2.0V minimum) to the converter's digital inputs reverse
biases the switching diodes bringing the transistor emitters
back up to + 2.0V. This turns the transistors on driving collec·
tor current into the R·2R resistor network.
=
The output amplifier summing junction node has been
broken apart to show IDAC as the current coming out of tran·
sistors 0" 0" and 0, and the R·2R ladder network into the
summing junction. If all the digital inputs are "O's", tran·
sistors 0" 0" and 0, will be turned off, and IDAC should
equal zero. If the bit 1 (MSB) input has a "1" applied, and bits 2
and 3 have "O's" applied, IC2and IC3 will equal zero and IOAC'
will equal IC4 = IC1 = + 0.5 mAo With the two bipolar offset
connections (C t and C,) open, all of IDAC becomes IF. With
the feedback resistor RF = 10K, the output voltage will equal
- RFIF = - (10K) x (+ 0.5 mAl = - 5V. With a "1" applied to
the bit 2 digital input and "O's" applied to the bit 1 and bit 3 in·
puts, IC2 and IC4 will be zero and IC3 will equal + 0.5 mAo The
ladder network will divide IC3 so that IDAC will equal + 0.25
mA. Vout will now equal - 2.5V. With a "1" appliedtothe bit3
(LSB) input and "O's" applied to bits 1 and 2, IC3 and IC4 will
be zero, and IC2 will equal + 0.5 mAo This will be divided such
that IDAC will equal + 0.125mA and Vout will equal - 1.25
volts.
When all the digital inputs have "1's" applied, IOAcwi11 be
equal to the sum of the currents that resulted when the "1 's"
were applied separately, I.e., IDAC=0.5 mA + 0.25 mA +
0.125 mA = 0.875 mAo Vout will now equal -8.75 volts. The
rest of the output voltages for the remainder of the input
codes can be calculated by simply adding the appropriate
combination of voltage for each bit individually. The entire
digital input/analog output transfer function is shown in
Figure 25. This 3 bit D/A converter has a 0 to - 10V output
range, and its Unipolar Offset Error (the Absolute Accuracy
Error measured when IDAC is supposed to equal zero) must
be measured with a 000 digital input, i.e., at its zero volt out·
put. No problems! Let's now convert our 0 to -10V unipolar
DIA into a ± 5V bipolar D/A. This is accomplished by making
bipolar offset connection Ct. The Ct connection results in a
constant current IB01 = VREF/RB01 = 10V/26.67
KO = + 3.75mA being pulled out of the output op amp summ·
ing junction in the direction indicated. IF is now equal to IDAC
-IB01.Therefore, when the digital inputs of the converter are
all "O's" and IDAC =0, IF will equal -IB01 (which is constant
at - 0.375mA), and Vout will equal + 3.75 volts. With a "0" ap·
plied to the bit 1 digital input and "1 's" applied to the bit 2 and
bit 3 inputs,lDAC will equal + 0.375mA.IF = IDAC - IB01 will
now equal zero, and Vout will equal zero. With all "1's" applied
to the digital inputs, IDAC will equal +0.875mA and IFWill
4-15
Digital Inputs
LSB
A BOl
ABO>
8il2
= 26.67KO
~
11.429Kll
-VRef
now equal + 0.5mA. Vout will equal - 5.0 volts. The transfer
function for the ± 5V output range converter will be that
shown in Figure 26b. Comparing Figure 26b to Figure 26a
shows graphically that to convert a unipolar negative (0 to
- 10V) 3 bit D/A to a bipolar ± 5V 3 bit D/A, the transfer func·
tion is offset (pushed up) an amount equal to the weight of
bits 2 and 3 (3.75 volts). Again, this is effected electronically
by pulling a constant current equivalent to the bit 2 plus 3 current (0.375mA) out of the output amplifier summing junction,
i.e., through the feedback resistor.
Where doe's Bipolar Offset Error have to be measured? Accor·
ding to its definition, it has to be measured when IDAC is supposed to equal zero. This occurs with a digital input of 000 and
an analog output of + 3.75V. Bipolar Offset Error, at least for
this converter, has to be measured at its positive full scale
output, not at its negative full scale output. It is IDAC not
110 101 100 all 010 001 000
0.00
-1.25
-2.50
-3.75
-5.00
-6.25
-7.50
-8.75
Analog Output
(DC Vol Is)
Figure 25. Digital input/analog output transfer function of the
- 10V 3 bit D/A of Figure 24.
o to
4-16
ISOl
~
~
1802
~C~·
'C~·
Figure 24. Actual schematic for a 3 bit 0 to - 10V D/A. The
PN P transistors act as current sources and the R·2R ladder
network acts as a binary weighted current divider. Digital in·
put data turns the transistors on or off.
-10.0V
Digilal111
Input
MS8
equalling zero and IB01 not equalling + 0.375mA coupled
with op amp offset error that cause Bipolar Offset Error.
Finally, to make our original 0 to -10V converter into a 0 to
+ 10V converter, the transfer function must be offset full
scale. The 0 to + 10V transfer function is shown in Figure 26c.
Comparing this to Figure 26a shows that the original transfer
function must be offset (pushed up) an amount equal to the
weight of all the digital inputs (8.75 volts). To accomplish this
electronically, the C, offset connection has to be made (C, is
now open). The C, connection results in a constant current of
IB02 = VREF/RB02 = 10V/11.429K= + 0.875mA being pulled out of the output op amp summing junction in the direction
indicated. IF now equals IDAC - IB02. Therefore, when the
converter's digital inputs are all "O's" (lDAC = 0), IF equals
-IB02(constant at - 0.875mA), and Vout will equal + 8.75V.
Witha "1" applied tothe bit 1 digital input and "O's" applied to
the bit 2 and bit 3 digital inputs, IDAC will equal + 0.5mA.
IF = IDAC -IB02 will now equal - 0.375mA and Vout will
equal + 3.75V. With all "1 's" applied to the digital inputs,
IDAC will equal + 0.875mA and IF wilifloW equal OmA. Vout
now equals zero volts. Again, the vnipolar positive (0 to
+ 10V) transfer function is shown in Figure 26c. Where does
Unipolar Offset Error now have to be measured? IDAC is sup'
posed to equal zero when the converter output is at KS
positive full scale output ( + 8.75V). Therefore, Unipolar Offset
Error has to be measured there, not at the zero volt output.
Notice how the digital coding differs for the unipolar positive
and unipolar negative ranges. Forthe unipolar negative range
(Figure 26a), a 000 digital input gave zero volts output. For the
unipolar positive range (Figure 26c), a 000 digital input gives a
+ 8.75V (full scale minus 1 LSB) output. In order to get zero
volts out of the unipolar positive converter, one has to apply a
111 digital code. Applying this code to the unipolar negative
converter gives a - 8.75V (minus full scale plus 1 LSB) output.
The reason we have gone through all ofthis in such detail is to
show precisely why we don't like Offset Error as a data con·
verter specification. Some manufacturers will include in their
data sheets an eXplanation of Offset Error so the user can
know where the spec applies. Others simply use the term Off-
., "I
Analog Output
Analog Output
(DC Volts)
IDC Volts)
'''~
,875
, 5 00
t
500
·500
•
•
ttt
000
•
ttt
000
Digital
Input
111
Digital
Input
8.75
750
625
POSitive
Offset Drift
5 00
000
3.75
la)
5 00
5.00
875
875
Ib)
j
5.00
2.50
1 25
875
Ie)
Figure 26. The 0 to - 10V 3 bit D/A transfer function (a) of
Figure 25 is turned into that for a ± 5V 3 bit D/A (b) by making
the C, offset connection. It is turned into that for a 0 to + 10V 3
bit D/A (c) by making the C, offset connection. Notice how
subtracting a constant offsetting current from the summing
junction of the output op amp affects the transfer function.
OOO~
______
000 001
~--
010 all
__
~--
100 101
__
~
110
111
Digital
Input
Figure 27. Offset Drift slides the transfer function parallel to
itself along the voltage axis. The transfer function motion in·
dicated would occur for a positive offset drift.
Analog Output
IDC Volts)
set to mean Zero Error. Again, Micro Networks takes the posi·
tion that a user should not have to understand the inner work·
ings of any converter he/she is considering using, and that Of·
fset Error, because it is defined according to these inner
workings, is an ambiguous spec that should be avoided when
speCifying converters. We prefer to specify the accuracy of a
converter's input/output characteristic using Full Scale Ab·
solute Accuracy and Zero Errors.
OFFSET AND GAIN DRIFT-Offset Error is usually express·
ed in LSB's or %FSR and Offset Drift is usually expressed in
ppm's of FSR/oC. If a D/A converter has a room temperature
(+ 25°C) Offset Error of ± 0.1 % FSR and an Offset Drift of
± 5ppm of FSR/oC. Its Offset Error at + 85°C will equal its
room temperature value plus a drift component. The drift
component will equal (.1T) x (Offset T.C.) = (60°C) x (± 5ppm
of FSR/ 0c) = ± 300ppm of FSR = ± 0.03% FSR. The total Off·
set Error at +85°Cwillequal(±0.1% FSR)+(±O.03% FSR)
= ± 0.13% FSR. At + 125°C, the total Offset Error will equal
±0.15% FSR. As Offset drifts, the transfer function moves
parallel to itself along the voltage (output) axis. See Figure 27.
Gain Error is usually expressed as a %, and Gain Drift is
usually expressed in ppm's/ °C. If a D/A converter has a room
temperature (+ 25°C) Gain error of ± 0.2% and a Gain Drift of
± 20ppm/ °C, its total Gain Error at + 85°C would be
± 0.32%, and its total Gain Error at + 125°C would be
± 0.4%. Gain Drift has the effect of rotating the D/A transfer
function around the point at which Offset Error occurs. See
Figure 28.
Forthe unipolar D/A, Gain and Offset Drift are the result of in·
depedent error sources, and their combined net effect on the
transfer function as temperature changes is unpredictable.
Figure 29a shows a unipolar unit exhibiting positive Offset
Drift and positive Gain Drift. Its Absolute Accuracy Drift is
equal to the sum of Gain and Offset Drift. Figure 29b shows a
unipolar unit exhibiting negative Offset Drift and positive
Gain Drift in a manner such that Full Scale Absolute Ac·
curacy does not drift at all. If the directions of Offset and Gain
Drift are not known, a user can only assume that worst case
Unipolar Absolute Accuracy Drift will be equal to the sum of
the two drift specs.
For the bipolar D/A, Bipolar Offset and Gain Drifts interact in
a complicated manner that results in Absolute Accuracy Drift
being less than the sum of the two specs. This will bediscuss·
ed shortly.
8.75
7.50
/
6.25
./
./
/./
5 00
/
375
/ / ,/
/'
/'
Negative
Gain Drift
~"./
250
,/;,,"
1.25
~
"
0.00000 001
Digital
010 all
100 101
tl0
111 Input
Figure 28. Gain Drift rotates the transfer function around the
point at which Offset Error occurs. The transfer function mo·
tion indicated would occur for a ne9ative gain drift.
ABSOLUTE ACCURACY
VS.
GAIN AND OFFSET
Presently, Micro Networks manufactures D/A and A/D con·
verters for two main types of users, and we specify these con·
verters accordingly. The first type of user is in the commer·
cial/industrial marketplace. We understand this user to be
very cost conscious and willing to go through a gain and off·
set adjusting procedure to achieve the greatest accuracies
from his/her converters. Our experience tells us that these
users expect to be able to purchase lower cost converters by
not demanding maximum limits on room temperature Ab·
solute Accuracies. They do however, demand good
Linearities and hence good Relative Accuracies. They also
demand accurate Linearity, Gain, and Offset Drift specifica·
tions because they usually deSign equipment to operate over
known limited temperature ranges. The second type of user is
in the military/aerospace marketplace. This user has to
design equipment to operate within specification over the en·
tire - 55°C to + 125°C temperature range, and he/she wants
to avoid the use of adjusting potentiometers because of their
inherent unreliability and their need for periodic recalibra·
tion. This user cannot concern himself/herself with drift
specifications, but demands Absolute Accuracy and Lineari·
ty specs guaranteed from - 55°C to + 125°C.
4-17
I
I
I
Analog Output
(DC Volts)
10.00
/
8.75
/
7.50
/
6.25
I
II
5.00
3.75
/ I
/
function points other than that at which Offset Error
occurs and at temperatures other than + 25 ·C.
3) The Gain·Offset Method may reject units whose Gain
and Offset Errors have oppOSite polarities resulting in
acceptable accuracy.
4) The Absolute Accuracy method allows us to specify
much tighter Bipolar Zero Errors than the competition
without affecting our overall yields.
I
i
I
/
/
/
/
/
/
/
Positive
Gain Drift
Positive
Offset Drift
/
(a)
2.50
1.25/
Digital
0.00 -I'--+-_--<--+-~>__~__< Input
000 001 010 011 100 101 110 111
Analog Output
(DC Volts)
10.00
8.75
7.50
/'
,- ,-/?'
6.25
,-/',/-
5.00
3.75
2.50
"
,-'- /
,...
. . . . . . . . . .i/
/
Negative
Gain Drift
(b)
Positive
Offset Drift
1.25
Digital
0.00000 001 010 011
100 101
110 111 Input
Figure 29. Positive Unipolar Offset and Gain Drifts add
together to give a positive Absolute Accuracy Drift (a). It is
possible for Offset and Gain Drifts to be in opposite direc·
tions such that Full Scale Absolute Accuracy Drift is zero (b).
Let's discuss these pOints one at a time. The ambiguity of Off·
set we have already addressed in the section labeled "Offset
Error".
To address point 2, we have to answer the question "How
does one go about determining the Absolute Accuracy of a
D/A converter that lists only Offset and Gain Errors on its data
sheet?" At room temperature, one can simply add the two er·
rors. Take an industry·standard 12 bit D/A like the DAC80.
Most manufacturers of this device will list the following
speCifications at room temperature.
Unipolar Offset Error
± 0.15%FSR (Maximum)
Bipolar Offset Error
± 0.15%FSR (Maximum)
±0.3%
Gain Error
The DAC80's Unipolar Offset Error occurs at its zero volt out·
put, and its Bipolar Offset Error occurs at its minus full scale
output. Therefore, at room temperature, its Unipolar Zero Er·
ror will equal its Unipolar Offset Error ( ± 0.15%FSR), and its
Unipolar Positive Full Scale Absolute Accuracy Error will
equal the sum of its Unipolar Offset and Gain Errors
(± 0.45% FSR). This means that when operating at + 25·C on
the 0 to + 10V output range, the unadjusted DAC80's actual
full scale output voltage may be as much as ±0.45%FSR
(which equals 45mV or almost 19 LSB's) away form its ideal
value (+ 9.9976V) and still be within spec. The limits are sum·
marized in Figure 30.
Analog Output
(DC Volts)
+10.0426
It is this second type of application that we would like to
discuss in detail. We would like to explain why we feel that the
converter to be used in an application in which its initial Gain
and Offset Errors are not going to be adjusted out with exter·
nal potentiometers is much better specified with Zero and
Full Scale Absolute Accuracy Errors than it is with Gain and
Offset Errors, both at room temperature and over any
specified operating temperature range.
+ 9.9976
+ 9.9526
1
• +9.9976V ±0.45% FSR
f
For all practical purposes, the transfer function of a data con·
verterwith halfway decent linearity can be considered to be a
straight line, and the converter's accuracy specifications
should describe the position of the straight line relative to its
axes, i.e., they should describe how close the straight line
+ 0.0150
comes to the ideal. There are two simple ways to describe the
Digital
plot of astraight line on a set of rectangular axes. The line can o.oooov ±0.15% FSR
I
I
Input
111111111111
0000 0000 0000
be described by two points or by a point and slope (angle).
- 0.0150
Micro Networks prefers the two·point technique (our two
pOints being our Zero Error and Full Scale Absolute Accuracy
Error) to the point·slope technique (the point being Offset Er·
ror and the slope being Gain Error). We prefer our method for
Figure 30. At + 25 ·C, the DACBO's Unipolar Positive Full
no fewer than four good reasons:
Scale Absolute Accuracy Error (± 0.45% FSR) is equal to the
1) Offset Error is confusing.
sum of its Unipolar Offset Error (± 0.15% FSR) and its Gain
Error (± 0.3%). The dots show the ideal transfer function for
2) The Gain·Offset Method calls for extra, often com·
plicated, mathematical manipulation on the part of
the 0 to + 10V output range. The solid lines are the Absolute
Accuracy limits.
the user to determine converter accuracy at transfer
1
T
4·18
For bipolar ranges, the Negative Full Scale Absolute Accuracy Errorwill equal the BipolarOffset Error( ± 0.15%FSR).
The Positive Full Scale Absolute Accuracy Errorwill equal the
sum of the Bipolar Offset and Gain Errors (± 0.45% FSR). The
Bipolar Zero Error will equal the sum of the Bipolar Offset Error and '/2 the Gain Error (± 0.3% FSR). These limits are summarized in Figure 31.
Analog Output
(DC Volts)
1
-1-100576
199976V • 06% FSR
+ 9.9976
Analog Output
(DC Volts)
1
+5.0426)
t
99376
////f
t 4 9976V :t-O 45% FSR
,4.9976
+ 00164
1111
~\--"_----r+---<~~+-+--fr--l~\-+--<
a oooov
!9'tal
1
'0 164% FSR
00164
T
./
t--<--y4-~~II'r-~~~~~-~
111111111111
Digital
Input
0000 0000 0000
0000 0000 0000 Input
T
1
-5 OOGOV
~O
15% FSR •
I
00300
49850
Figure 32. Unipolar Absolute Accuracy of the DAC80 at
+ 70°C is equal to the sum of Unipolar Offset Error at + 70 °C
and Gain Error at + 70°C.
-5 0000
-5 0150
To calculate the Absolute Accuracy of a DAC80 at
temperatures other than + 25°C, users can make use of the
converter's Gain, Offset. and Reference Drift specifications.
The data sheet lists the following:
Gain Drift
± 30ppml °C (Maximum)
Gain Drift Exclusive of
± 10ppm/oC (Maximum)
Reference Drift
Reference Drift
± 20ppml °C (Maximum)
± 3ppml °C (Maximum)
Unipolar Offset Drift
± 15ppm/oC (Maximum)
Bipolar Offset Drift
Calculating Bipolar Absolute Accuracies at temperatures
other than +25°C is not so simple. Negative Full Absolute
Accuracy Error at + 70°C is equal to Bipolar Offset Error at
+70°C (±0.2175%FSR) but Positive Full Scale Absolute Ac·
curacy Error at +70°C is not equal to the sum of Bipolar Offset Error at + 70°C and Gain Error at + 70 °C. This is due to
the fact that the largest portions of Gain Drift and Bipolar Off·
set Drift are the result of reference drift, and in the bipolar
mode, these components partially cancel each other making
Positive Full Scale' Absolute Accuracy Drift much less than
the sum of Gain and Bipolar Offset Drift. As a rule of thumb,
Positive Full Scale Absolute Accuracy Drift will be equal to 11z
the Reference Drift plus the Gain Drift Exclusive of Reference
Drift plus the Bipolar Offset Drift Exclusive of Reference Drift.
If these drift specifications are not listed on the manufac·
turer's data sheet, the following rules can usually be applied:
Reference Drift = 2/, of Gain Drift
Gain Drift Exclusive of
Reference Drift = 1/, of Gain Drift
Bipolar Offset Drift Exclusive of
Reference Drift = '13 of Bipolar Offset Drift
Let's find the Unipolar and Bipolar Absolute Accuracies of
the DAC80 at + 70°C. For unipolar ranges, the calculations
are simple. Zero Error at + 70°C will be the same as Unipolar
Offset Error at + 70 °C; it will be equal to the room
temperature value plus the drift component. The change in
temperature (.H) from + 25°C to + 70°C is 45°C. Therefore,
the drift component is (45°C) x (± 3ppm of
FSRI 0c) = ± 135ppm of FSR = ± 0.0135% FSR, and the total
Unipolar Offset Error at + 70°C will equal
±0.15%FSR±0.0135%FSR= ±0.1635%FSR (maximum).
The Positive Full Scale Absolute Accuracy Error at + 70°C
can be calculated in two ways. The first method simply adds
the Unipolar Offset Error at + 70°C to the Gain Error at
+ 70°C. The Gain Error at + 70°C will equal the room
temperature value plus the drift component:
± 0.3% + (45°C) x (± 30ppm/ °C) = ± 0.3% + 1350ppm
= ± .435%. The Positive Full Scale Absolute Accuracy Error
at + 70°C will equal ±0.1635% FSR ±0.435% FSR=
± 0.5985% FSR. These limits are summarized in Figure 32.
Applying these rules to the DAC80 gives the result that the
total Positive Full Scale Absolute Accuracy Drift will equal
± 10 ± 10 ± 5ppm of FSR/oC. Bipolar Positive Full Scale Absolute Accuracy Error at + 70°C will equal the room
temperature spec (± 0.45% FSR) plus the drift component.
The drift component will be (45°C) x (± 25ppm of
FSR/ 0c) = ± 1125ppm of FSR = ± 0.1125 of FSR and the
Positive Full Scale Absolute Accuracy Error at + 70°C will
equal ± 0.45 ± 0_1125 = ± 0.5625%FSR which is better than
the Unipolar Positive Full Scale Absolute Accuracy Error at
+ 70°C. The results are summarized in Figure 33. I think we
have made our point. It takesa lot more work than it should for
a user to figure out how accurate a converter is going to be
when he/she intends to use it without initial gain and offset
adjustments, and the device is specified with initial Gain and
Offset Errors and the appropriate drift specifications. The
situation is complicated by the fact that many manufacturers
who choose to give room temperature Gain and Offset Errors
only give typical values for these specs.
T
Figure 31. At + 25°C, the DAC80's Bipolar AbsoluteAccuracy
is equal to the sum of its Bipolar Offset Error and its Gain
Error. The dots show the ideal transfer function for the ± 5V
output range. The solid lines are the Absolute Accuracy
limits.
4-19
I
1
+4.9976V·±0.5625% FSR
1111 1111 1111
~,~~~~~----~
l
1
'-5.0000V ±0.2175% FSR
T
-I97~:0390
The ideal transfer function is the short-dashed line. The longdashed lines show the Offset Error, and the solid lines show
the Absolute Accuracy Limits fixed by the sum of Gain and
Offset Errors. We are assuming that the device's Offset Error
occurs at its zero volt output. Fig. 35 plot (a) is the transfer
function of a D/A converter that has the maximum allowable
Gain and Offset Errors, i.e., the transfer function tracks the
upper limit of Absolute Accuracy. It has a Zero Error of + 1
LSB and a Positive Full Scale Absolute Accuracy Error of + 2
LSB's. Fig. 35 plot (b) is the transfer function of aD/A
that has - Y, LSB Offset Error and + 21.45% Gain Error (1 'h
times the allowable limit). This unit would be rejected for exceeding the Gain Error specification yet its Zero Error is twice
as good as that of the previous unit (- V2 LSB compared to
+ 1 LSB) and its Positive Full Scale Absolute Accuracy Error
is also twice as good as the "good" unit (+ 1 LSB compared
to + 2 LSB's). The user who is not performing initial gain and
offset adjusting would actually prefer the "bad" unit.
-5.0000
-5.0218
Analog Output
(DC Volts)
+ 70·C
is better than the sum of Bipolar Offset Error at + 70·C and
Gain Error at + 70 ·C.
Figure 33. Bipolar Absolute Accuracy of the DAC80 at
11
11.25
10.00
+8.75V +1 LSB
8.75
/
(a)
.
7.50
Point 3 was that we felt the Gain-Offset technique could
result in the rejection of units that had perfectly good accuracy. This point needs clarification, and we think this is
best accomplished graphically. We will give one example
here and further examples in the discussion of point 4. Figure
34 shows the Absolute Accuracy limits of a 3 bit, 0 to + 10V
output range D/A that has a maximum Unipolar Offset Error
of ± 12.5% FSR (± 1 LSB) and a maximum Gain Error of
± 14.3% (this Gain Error spec results in a maximum Gain Error of ± 1 LSB when the converter is at its full scale output).
6.25
(b)/
/
/
r
/
/
T
5.00
3.75
DigItal
-1'--...."--+----+---.......---. Input
111
-1.25
Analog Output
(DC Volts)
1
+11.25
+10.00
/
+ 8.75
/
+ 7.50
/ / ~ +8.75V ±2 LS8's
/ ///
+ 6.25
////
+ 5.00
T
~//
/
+ 3.75
f/'//,
/
+ 2.50
///
+ 1.25
/
//
~
,;::
//'
Digital
0.00 ¥--""'-0"'1-0-0"'1-1-1~0-0-10-1-11~0---'111 Input
- 1.25
Figure 34. The solid lines show the Absolute Accuracy limits
of a 3 bit 0 to + 10V D/A that has a Unipolar Offset Error of
± 12.5% FSR(± 1 LSB) and a Gain Error of ± 14.3%.
4·20
Figure 35. Transfer function (a) is that of a 3 bit 0 to + 10V D/A
that has the maximum Gain and Offset Error allowed in
Figure 34. Unipolar Zero Error = + 1 LSB. Full Scale Absolute
Accuracy Error = + 2 LSB's. Transfer function (b) is that of a 3
bit 0 to + 10V D/A that has a Unipolar Offset Error (Zero
Error) = - Y, LSB and Gain Error = + 21.45%. The result is a
Full Scale Absolute Accuracy Error of + 1 LSB.
Point 4 refers only to bipolar converters, but we want to
preface our discussion by saying that for unipolar converters
there real!y is not a whole lot of difference between specifying
Gain and Offset Errors and Full Scale Absolute Accuracy and
Zero Errors. We saw in the discussion of point 2 that as long
as a user knows where the Offset Error specification applies,
all he/she has to do is add the Gain and Offset Errors at any
temperature to find the Full Scale Absolute Accuracy and
Zero Errors at that temperature.
As we also saw in the discussion of point 2, the situation is
not the same for the bipolar converters. Let's review what the
Gain-Offset technique says about the Absolute Accuracy of
bipolar converters. Figure 36 shows the Absolute Accuracy
limits of 3 bit, ± 5V output range D/A that has a maximum
Bipolar Offset Error of ± 1 LSB and a maximum Gain Error of
± 14.3%, The sketch is the same as that of Figure 32 offset
half scale. We are assuming that this device's Bipolar Offset
Error occurs at its minus full scale output. As you can see, the
Absolute Accuracy limits are in the shape of a "fan" and
henceforth, we shall call the Gain·Offset technique of specifying accuracy the fan Method. As temperature changes,
gain and offset drift in an interacting manner resulting in a
new Fan at each temperature. The result is still a fan-shaped
limit, however, and its bipolar offset end (the minus full scale
end in this example) is always tighter than its other end (the
positive full scale end in this example).
Analog Output
(DC Volts)
Bipolar
POSitive
Full Scale
/ Absolute
/
Acr.urB.cy
//
Error
/
Analog Output
(DC Volls)
1
+625
+500
/
-t 3 75
T
000 001
Digital
111 Input
- 2 50
1
-375
-5 00
(a)
625
T
Analog Output
(DC Volts)
1
+6.25
Bipolar
Positive
Full Scale
Absolute
Accuracy
+5.00
-t-3.75
Error
T
Digital
111 Input
1
Bipolar
Offset
Error
T
-3.75
-5.00
-6.25
I
t3 75V -2 LSB's
(b)
Figure 36. Absolute Accuracy limits of a 3 bit ± 5V D/A with a
± 1 LSB Bipolar Offset Error and a ± 14.3% Gain Error(a). Absolute Accuracy limits are in the shape of a "Fan" (b).
Figure 37. Micro Networks prefers to loosen the Negative Full
Scale Absolute Accuracy Error and tighten the Bipolar Zero
Error gving Absolute Accuracy limits that resemble a
"Butterfly".
Micro Networks specifies the accuracy of bipolar converters
using a Negative Full Scale Absolute Accuracy Error, a
Positive Full Scale Absolute Accuracy Error, and a Bipolar
Zero Error. We usually make our Positive and Negative Full
Scale Error specifications equal to each other and much
greater than our Bipolar Zero Error resulting in Absolute Accuracy limits that resemble a "butterfly" (see Figure 37).
Henceforth, we will refer to our technique as the Butterfly
Method.
As stated earlier, we feel the Butterfly Method allows us to
specify much tighter Bipolar Zero Errors than the Fan Method
does. Let's see why. The tight end of the Fan limits is always
the Bipolar Offset Error specification, and Bipolar Offset Error is an error source that most manufacturers have a pretty
good handle on. Therefore, either because of tradition or
through an effort to make their converters look as good as
possible on paper, these manufacturers will specify tight
Bipolar Offset Errors. Because Gain Error is much more difficult and more expensive to control, these manufacturers
have to open up the other end of the Fan in order to get decent
product yields. The result is that the Bipolar Zero Error
specification has to be opened up to accommodate the Gain
Error.
In reality, thanks to laser trimming, Bipolar Zero Error is about
as easy to control as Bipolar Offset Error is, and Micro Networks has chosen to relax our Negative Full Scale Absolute
Accuracy Error and tighten up our Bipolar Zero Error. In other
words, for every unit that has a good Negative Full Scale Absolute Accuracy Error and poor Bipolar Zero Error there is a
unit that has a poor Negative Full Scale Absolute Accuracy
Error and a good Bipolar Zero Error. Micro Networks has
chosen to call the latter "good" units and former "bad" units.
Manufacturers who test to the Fan Method are calling the latter "bad" units and the former "good" units. See Figure 38.
Why do we feel our "good" units are better than their "good"
units? Firstly, for most D/A and ND converters used in closed
loop control applications, Bipolar Zero Accuracy is much
more important than Negative Full Scale Accuracy. Take a
look at our MN3850H and MN3860H 12 bit D/A converters.
These devices guarantee ±O.1%FSR maximum Bipolar Zero
Error over the entire -55°C to +125°C operating
temperature range. You cannot buy a 12 bit D/A with a better
4-21
Analog Output
(DC Volts)
0;:.00"----,,,-1'---,,4_ _ Dig ital
111 Input
(a)
within the band defined as "final value ± Yo LSB" (+ 7.25 ±
1.25 volts).
Analog Output
(DC Volts)
00,-,0_--,.'H7"_....,-, Digital
111 Input
(b)
+F.S.-
Figures 38a and 38b. The unit whose transfer function is
shown as the dashed line has a large Bipolar Offset Error and
a small Bipolar Zero Error. It fails the Fan limits and passes
the Butterfly limits.
Analog Output
(DC Volts)
If a Settling Time spec is given for a 1 LSB change, the change
should be that occurring when the MSB just turns on or off,
i.e., when the digital input goes from a "0" and all "l's" to a
"1" and all "O's" or vice versa. This is the situation in which
the greatest output glitch and therefore the longest settling
for a 1 LSB change occurs. In most D/A applications, Output
Slew Rate will not be an important parameter if Settling Time
is properly specified.
Analog Output
(DC Volts)
.............. Final
f Value ±'/2 LSB
,,-,-~"""--
Zero - - - c - - - t L . . . . - - - + - - - - - -
-F.S.---CJ
Digital~
AII'Ts"
Input~\...._ _ _ _ _ _ _ _ _ __
00;:,0"--........,.f'-1!---,.4-_ _ Dig ital
111 Input
(e)
0;e:OO"------::.MI-7-"-__
Digital
111 Input
(d)
Figures 38c and 38d. The unit whose transfer function is
shown as thedashed line has a small Bipolar Offset Error and
a large Bipolar Zero Error. It passes the Fan limits and fails
the Butterfly limits. Which is the more accurate device?
Bipolar Zero Error. Secondly, we see very few bipolar applica·
tions in which it is necessary to have a Negative Full Scaleab·
solute Accuracy Error that is better than the Positive Full
Scale Absolute Accuracy Error, especially at the expense of
Bipolar Zero Error.
We have made our case. A good percentage of Micro Net·
works converters are designed without the option for external
gain and offset adjusting. These devices were designed for
simplicity of use, and all of them are specified with maximum
Full Scale Absolute Accuracy and Zero Errors at room
temperature and over the specified operating temperature
range. Please feel free to contact our Applications Staff if you
have any questions concerning how and why we specify our
converters the way we do.
D/A CONVERTERS-DYNAMIC SPECIFICATIONS
SETILING TIME-Settling Time is defined as the total
elapsed time between the application of a new input code and
the point at which the analog output has entered and reo
mained within some specified percentage of its final value.
Normally, the input code change should be such that the D/A
output is forced over its full.range, i.e., the code change
should be from all "l's" to all "O's" or vice versa. Thespecified
limits of the final error band are placed around the output's
final value, not its ideal value. See Figure 2. Suppose this 3 bit,
± 10V D/A gave an actual output of + 7.25V (instead of the
ideal + 7.5V) when its input was all "l's". To measure settling
time, one would start at a 000 input, apply a 111 input, and
measure how long it took for the output to reach and remain
4·22
Figure 39. Settling Time is the elapsed time between the ap·
plication of a new input code and the point at which the
analog output enters and remains within the band described
as final value ± V, LSB.
SUCCESSIVE APPROXIMATION AID CONVERSION
The technique of AID conversion most widely used in data ac·
quisition applications is that of "successive
approximations". This is primarily due to the fact that suc·
cessive approximation AID conversion offers excellent
tradeoffs in resolution, speed, accuracy, and cost. The
highest resolution devices can convert 16 bits in tens of
microseconds with some models selling for under $200.12 bit
units can convert in under 2!,sec and sell for under $40. 8 bit
units can convert in hundreds of nanoseconds and sell for a
few bucks.
Virtually all successive approximation (SA) analog to digital
converters are voltage input devices, and the conversion pro·
cess is remarkably similar to finding the weight of an
unknown object using a chemist's balance and a set of bin·
arilyweighted known weights(e.g., V, lb., V. lb., Y,lb., y',lb( = 1
oz.), V. oz., % oz., etc.). All of the AID converters presently
manufactured by Micro Networks are successive approxima·
tion types. Figure 40 shows a simplified block diagram for a 3
bit, 0 to + 10V successive approximation AID. Figure 41 is its
timing diagram. The circuit consists of a block of controlling
logic and flip flops known as a successive approximation
register (SAR), a current output D/A converter with reference,
a clock, and a comparator. The outputs of the SAR's four flip
flops act as both the direct (parallel) data outputs of the con·
verter and the digital drive for the internal D/A converter.
When the appropriate signal is applied to the converter's
Start Convert input, the Status output rises toa "1" indicating
that the converter is in the process of performing a conver·
sion and that digital output data is not valid. At the same
instant, the digital outputs of the SAR all go to "0" except for
the MSB which is set to a "1". In this state (called the reset
state), the digital output of the AID is 100, and the current
(IDAC) coming out of the internal D/A is the MSB current.
The analog input signal dropped across Rin produces a cur·
rent lin. The D/A continuously converts the digital output
of the AID into an equivalent analog current that the com·
parator continuously compares to lin. The comparator output
Status Output
Serial Output
Start Convert
+--t-+--t~
MSB
+-t--+-~ Bit 2 g~f~~atls
+--+-~LSB
Ana log I nput ~--'V'V'v---+---I"
Figure 40. Block diagram of a 3 bit successive approximation
AID converter. This technique is very similar to weighing an
unknown on a chemist's balance.
The analog input to an S/A type AID should not change during
the conversion time. The conversion time is defined as the
width of the Status output pulse and it is strictly a function of
clock frequency. If the input were to change during a conver·
sion, the output code would no longer accurately represent
the analog input unless the new value were larger than the
sum of the weights already present by an amount less than
the sum of the untried weights. Since this is a not-of tenfulfilled requirement, it is common to employ a sample-hold
device ahead of the converter to retain the input value that
was present at the instant the conversion starts and maintain
it constant throughout the conversion. The Status output of
the converter could be used to release the sample-hold from
its hold mode at the end of conversion. A sample-hold may
not be needed if the signal (by itself, or with filtering) varies
slowly enough and is sufficiently noise-free that significant
changes will not occur during the conversion interval.
Accuracy, linearity, and speed are primarily affected by the
properties of the D/A converter, the reference, and the comparator. In general, the settling time of the D/A converter and
the response time of the comparator are considerably slower
than the switching time of the digital elements and will limit
co'nversion speed. The differential nonlinearity of the D/A
converter will be reflected in the differential nonlinearity of
the resulting AID converter. If the D/A converter is nonmonotonic, one or more codes may be missing from the AID
converter's output range. Bipolar AID's are created by using
bipolar D/A's with appropriate input scaling.
Clock
Start
Convert
MSB~
Bit2~
Bit3~
clock edges, and these edges can be used to clock serial data
into receiving registers.
Ilf--:----
------:1----
Status~r-:
o~~~~: ZZ/77Zz//11
IlL'__
Figure 41. Timing diagram for the 3 bit AID of Figure 40. After
a conversion has been initiated, each output bit is set to its
final value on successive rising clock edges.
("1" or "0") informs the SAR whether the present digital out·
put (100 in the reset state) is "greater than" or "less than" the
analog input. Depending upon which is greater, on the first
rising clock edge after the start signal has been applied, the
SAR's logic will make a decision and set the MSB to its final
state ("1" or "0") and bring bit2 up to a "1". Thedigital output
is now X10. The D/A converts this to an analog value, and the
comparator determines whether this value is greater or less
than the analog input. On the next rising clock edge, the SAR
reads the comparator feedback, sets bit 2 to its final state,
and brings bit 3 up to a logic "1". The digital output is now
XX1. On the next rising clock edge, the SAR reads the com·
parator feedback and sets the LSB to its final state. If this
were more than a 3 bit AID, this successive approximation
procedure would continue in order of descending bit weights
until all the output bits had been set. The rising clock edge
that sets the LSB to its final state also drops the Status out·
put to a "0" indicating that the conversion has been com·
pleted and that the digital output data is now valid. Data will
remain valid as long as the status is a "0".
There is also a Serial Data output. The data is in nonreturn·to·
zero format (NRZ) with each bit being present on the output
line for one clock period following the rising clock edge that
set that bit to its final value. Serial data is valid on falling
The SAR's employed by Micro Networks in most of our SA
type AID converters are complementary coded. This means
that in the reset state the MSB is a "0" and the other bits are
"1's", and as each bit is set to its final value, the succeeding
bit is dropped to a "0" rather than being raised to a "1". At the
end of a conversion, the Status rises to a "1" ratherthan dropping to a zero. The fact that we use complementary coded
SAR's makes very little difference since we normally also use
complementary coded D/A's internal to the AID's. The final
result is that most of our AID's are complementary rather
than straight binary coded.
Figure 42 is a repeat of Figure 3. It is the transfer function of a
3 bit, 0 to + 10V input range, binary coded AID converter.
Figure 43 is a repeat of Figure 4. It is the transfer function of a
3 bit, ± 10V input range, offset binary coded AID converter.
Recall our brief discussion of the AID transfer function at the
beginning of this tutorial. The only points along an AID's
analog input/digital output transfer function that can quickly
Digital
Output
t11
110
101
100
011
010
1 LSB
001
=1.25V
000
0.00 1.25 2.50 3.755.00 6.25 7.50 8.7510.00
Analog
Input
(DC Volts)
Figure 42. Analog input/digital output transfer function of an
ideal, 3 bit, 0 to + 10V input range, binary coded AID converter.
4-23
and accurately be detected and measured are the transition
voltages, the analog input voltages at which the digital outputs change from one code to the next.
Digital
Digital
Output
Output
111
1 LSB = 2.5V
110
I----t
Output
Transitions
110 to 111
101 to 110
--
100 to 101
011 to 100
010 to 011
101
-10.0 -7.5 -5.0 -2.5
100
+2.5 +5.0 +7.5 +10.0
Analog
Input
(DC Volts)
001 to 010
000 to 001
011
010
001
000
0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.00
(a)
-
Output
Transitions
110 to 111
Figure 43_ Analog inputldigital output transfer function of an
ideal, 3 bit ± 10V input range, offset binary coded AID
converter.
101 to 110
100 to 101
-+2.5 +5.0 +7.5 +10.0
-10.0 -7.5 -5.0 -2.5
Notice in Figure 43 that the digital output changes from 000 to
001 as the input is increased from some more negative
voltage to - 7.5V.lt changes from 001 back to 000 as the input
is decreased from some more positive voltage to - 7.5V. This
voltage, - 7.5V, is the Minus Full Scale LSB Transition
Voltage. It is the voltage at which the LSB changes from "1"
to a "0" or vice versa while all other bits remain "0". Note that
the011 to 100 transition (called the major transition because
all the output bits change) ideally occurs at the zero volt
analog input, and that the Positive Full Scale LSB Transition
Voltage, the voltage at which the LSB changes whi Ie the other
bits remain "1", is ideally + 7.5V.
Most converter users don't real ize that transition voltages are
what manufacturers look for when testing AID converter
Linearity and Accuracy. When a manufacturer tests the accuracy of an AID converter, he attaches his voltmeter to the input to see if the transition voltages are where they're supposed to be. If one wanted to depict the AID transfer function as a
set of points (similar to a DIA transfer function) one simply
has to plot the transition voltages with no loss of information.
This is done in Figure 44.
This section now continues with a discussion of Relative and
Absolute Performance Specifications for AID converters. The
discussions of individual parameters will not be as detailed
as they were for DIA converters sinc.e most of the observations made earlier pertain to both DIA's and AID's. In particular, the arguments against the use of Offset Errors and
the reasons why Micro Networks prefers to specify bipolar
accuracies according to the Butterfly Method rather than to
the Fan Method pertain equally to both AID's and D/A's.
ANALOG TO DIGITAL CONVERTERS - RELATIVE
PERFORMANCE SPECIFICATATIONS
INTEGRAL LINEARITY - As was the case with DIA's, the integral Linearity of AID converters is a measure of the
"straightness" of the converter's input/output transfer function. For DIP;s, Integral Linearity described how close the
points that were the analog output voltages were to a straight
line drawn through them. For AID's, it describes how close
the pOints that are the transition voltages are to a straight line
drawn through them. Figure 45 is a blow-up of the first four
levels of the transfer function of Figure 42. The transition
voltages, the analog input voltages at which the digital output change from one code to the next, are circled at the left
end of each level (one could have just as easily chosen the
4-24
Analog
Input
(DC Volts)
011 to 100
Analog
Input
(DC Volts)
010 to 011
001 toOl0
000 to 001
(b)
Figure 44_ The digital output transitions of Figures 42 and 43
are plotted as a function of input voltage. These plots convey
all the information of Figures 42 and 43.
Digital
Output
010
G~
G---l: :
I
001
000
I
I
I
I
I
I
I
0.00
1.25
2.50
3.75
Analog
Input
(DC Volts)
Figure 45. The first 4 transitions of Figure 42 are expanded to
clarify what points along the AID transfer function we are
calling the transition voltages.
right ends) and also indicated on the horizontal (anaI0g) axis.
These are the points for which linearity has to be tested, and
the reference straight line can be drawn according to either
an end-point definition or a best-fit definition (see DIA Integral Linearity). AID Integral Linearity Error is usually expressed in fractions of an LSB (± % LSB, ± 1j, LSB, etc.) or in
%FSR or ppm's of FSR.
Figure 46 shows a nonlinear, 3 bit AID transfer function.
Some of its bands are wider than 1 LSB; some are narrower
than 1 LSB. Figure 47 plots the transition voltages of Figure
46, and Figure 48 shows that the transfer function of Figure
46 has ± LSB Linearity Error according to the best-fit definition.
r.
that the AID has perfect linearity, obviously it does not. Figure
49c shows that plotting and drawing a straight line through
the transition voltages gives this AID ± % LSB Integral
Linearity Error (according to the best-fit definition).
Digital
Output
111
110
101
100
Analog Output
(DC Volts)
011
010
875
001
000
0.00 1.25 250 3.75 5.00 625 750 8.75 10 00
Analog
Input
(DC Volts)
750
6.25
Figure 46. Nonideal, 3 bit, 0 to + 10V input range AID con·
verter. Output levels greater or less than 1 LSB wide result in
an Integral Linearity error.
500
3.75
2.50
Output
Transitions
110 to 111
1 25
a 00
000 001
(a)
101 to 110
010 011
100 101
110
Digital
111 Input
100 to 101
all to 100
Digital
Output
111
010 to all
001 to 010
110
000 to 001
000 1 25 250 375 5.00 625 750 875 1000
101
Analog
Input
(DC Volts)
100
011
Figure 47. The transition voltages of figure 46 are plotted
against analog input.
010
001
000
Digital
Output
LSB
,, ,,
(b)
,
111
0.00 1 25 250 375 5.00 625 750 8.75 10.00
Analog
Input
(DC Volts)
110
100
Digital
Output
111
011
110
010
101
101
001
+-I~
LSB
000
000 1 25 250 3 75 500 625 750 875 10.00
,,
::
100
Analog
Input
(DC Volts)
011
010
Figure 48. The AID transfer function fo Figure 46 is shown to
have ± % LSB Integral Linearity according to the best·fit
straight line definition.
001
(e)
A few manufacturers have defined Integral Linearity for AID
converters to be the deviation of the "midpoints" of the levels
from a straight line drawn through them. Micro Networks
does not accept this definition, and Figure 49 demonstrates
why. If the 3 bit D/A of Figure49a were used to construct a 3 bit
successive approximation AID, the AID's transfer function
would look like that shown in Figure 49b. Drawing a straight
line through the centers of the levels leads one to conclude
,
+h LSB
Analog
000
Input
000 1.25 2.50 3.75 5.00 625 750 875 10.00 (DC Volts)
Figure 49. If the 3 bit D/A whose transfer function is shown in
(a) is used to make a 3 bit successive approximation AID, the
AID's transfer function will be that shown in (b). If one uses
the midpoints of the levels and not the transition points to
test Integral Linearity, this obviously nonlinear AID would
have perfect linearity. (c) shows that when the transition
points are used, the device has ± %LSB linearity according to
the best·fit definition.
4·25
Micro Networks feels that Integral Linearity is one of the most
important AID converter specifications, and we contend that
an n bit converter is not a true n bit converter unless it
guarantees at least ± V2 LSB Linearity over whatever
temperature range it is to be used. For AID converters, ± Y,
LSB Integral Linearity by either definition will guarantee No
Missing Codes and Differential Linearity Error better than ± 1
LSB.
DIFFERENTIAL LINEARITY ERROR-All the steps of the DIA
transfer function were supposed to be 1 LSB high. All the
levels or bands of the AID transfer function are supposed to
be 1 LSB wide. AID Differential Linearity Error is a measure of
the distance between transition voltages (i.e., a measure of
the widths of input voltage bands), with any deviation of the
actual "distance" from the ideal 1 LSB appearing as the error.
The amount of error is usually expressed in fractions of an
LSB.
A maximum Differential Linearity Error of ± '12 LSB means
that the "distance" between transition voltages can be as
large as 1 LSB ± '12 LSB, i.e., the input voltage may have to increase or decrease as little as Y, LSB or as much as 1 '12
LSB's before an output transition occurs. See Figure 50. The
transfer function of Figure 50 has some levels that are % LSB
wide and one that is 1 % LSB's wide. Its Differential Linearity
Error is ± % LSB. Integral Linearity Error better than ± '12
LSB byeilherdefinition guarantees that Differential Linearity
Error will be better than ± 1 LSB, i.e., maximum Differential
Linearity Error has an upper bound equal to two times Integral
Linearity Error. It can be less than 2X Linearity, however, and
some manufacturers may choose to test and specify it as being such. For example, a converter may specify ± '12 LSB Integral Linearity and ± % LSB Differential Linearity. If it
specifies ± '12 LSB Integral Linearity and says nothing about
Differential Linearity, one can only assume that maximum
Differential Linearity will be ± 1 LSB.
..,
II
II
--' I
101
II
II
100
011
010
.-------,
I
I
--'
I
I
110
,
+11h LS8's
100
,, ,,
011
- ', ,'
010
,
I
_+'h
001
000
(a)
'
---'
tOl
LSB
Analog
Input
(DC Volts)
0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.00
Digital
Output
111
/
:/:
110
/
101
,
:/
100
;.
011
/
./
010
001
/
,'
:
}:
, ,
,
:
~11/4 LSErs
/
/
000-1---+_ _- + -_ _-
(b)
'
+% LSB
_ _ _ _ _-+
0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.00
Analog
Input
(DC Volts)
Figure 51. Differential Linearity does not guarantee Integral
Linearity. The AID transfer function shown in (a) has ± V2 LSB
Differential Linearity but ± ~8 LSB Integral Linearity according to the best-fit definition and + 1 % LSB Integral Linearity
according to the end-point definition.
NO MISSING CODES-No Missing Codes is to AID converters what monotonicity is to DIA converter's (see
Monotonicity). There is really no need to specify Monotonicity for successive approximation AID converters. These
devices are monotonic by design; if the input voltage goes up,
the output code goes up. The question is how high up does
the output go? Does it jump up so high as to miss the next output level? Look at Figure 52. When the input voltage to this
Digital
Output
111
110
Digital
Output
111
+'/4 LSB
,
I
I
I
I
+W. LSB
001
000
0.00 1.252.503.755.006.257.508.75 10.00
Analog
Input
(OC Volts)
Digital
Output
111
110
Figure 50. Demonstration of an AID transfer function with
± % LSB Differential Linearity Error. Some levels are + '/.
LSB wide; others are + 1 % LSB wide.
101
100
011
010
Maximum Differential Linearity Error does notallowoneto infer anything about Integral Linearity Error. The transfer function of Figure 51 has ± V2 LSB Differential Linearity Error but
± 'Yo LSB Integral Linearity Error. Lastly, what happens if Differential Linearity Error is ± 1 LSB? Some of the levels will be
2 LSB's, wide; others will be a LSB's wide. Zero LSB's wide
means that tlie level does not exist and that the converter
misses a code.
4-26
001
000
0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.00
Analog
Input
(DC Volts)
Figure 52. This AID transfer function shows the digital output
going from all to 101 as the analog input increases. The code
100 is missing.
converter gets to + 2.5V, the output code becomes 011. The
output stays on this code while the input voltage increases to
+ 3.75V. Now the output changes to the code 101. The code
100 was missed. A successive approximation AID misses
codes when its internal D/A is nonmonotonic. The AID whose
transfer function is shown in Figure 52 was constructed using the D/A of Figure 53. Notice how the non monotonic D/A input (100) is the missing AID code.
Analog Output
(DC Voltsl
8.75
7.50
625
5.00
3.75
2.50
1.25
Digital
0.000·00-0+0-1-0+10-0+1-1-1~00-1-0-1-1-10-1-11 Input
Figure 53. The AID converter whose transfer function is
shown in Figure 52 was built with the non monotonic D/A
whose transfer function is shown here. The AID misses a
code (100) at the point at which the D/A is non monotonic.
Like Monotonicity, No Missing Codes is more a property of a
converter than it is a specification. The relevant specification
is "the temperature range over which no missing codes is
guaranteed". No Missing Codes is an important parameter.
One always wants to make sure that all 2n output codes are
achievable for an n bit converter. If an n bit converter misses a
code at its major transition (the most likely place for this to
occur) it might as well be an (n·1) bit converter.
Remember: ± Y, LSB Integral Linearity will guarantee No
Missing Codes and Differential Linearity Error better than ± 1
LSB. However, No Missing Codes and Differential Linearity
Error better than ± 1 LSB do not guarantee ± V2 LSB Integral
Linearity. Many converters will guarantee No Missing Codes
over some temperature range, but they won't guarantee ± V2
LSB Integral Linearity.
INTEGRAL AND DIFFERENTIAL LINEARITY DRIFT-See
this section under D/A converters for an explanation of how
to calculate the magnitude of Integral and Differential
Linearity Drifts over a given temperature range.
A 12 bit AID converter that guarantees ± Y, LSB (± 0.012%
FSR) Integral Linearity Error at + 25·C and gives an Integral
Linearity Drift of ± 1 ppm of FSR/·C will have an Integral
Linearity of ± 0.022% FSR at + 125 ·C. ± 0.022% FSR is
almost equivalent to 1 LSB for 12 bits (O.024% FSR) or Y, LSB
for 11 bits. Therefore, at + 125·C this converter would only
have 11 bit Integral Linearitywhich would mean that its effec·
tive resolution has been reduced to 11 bits. In other words, the
manufacturer of this converter is saying that at + 125 ·C, Dif·
ferential Linearity Error can be as bad as ± 2 LSB's (for 12
bits) and that he no longer guarantees No Missing Codes.
Most Micro Networks AID converters are guaranteed to be
± y, LSB Linear at room temperature and ± Y, LSB Linear
with No Missing Codes over their entire operating
temperature range. For converters that don't hold ± Y, LSB
Linearity over temperature, we will give a Linearity spec at
+25°C and another Linearity spec that applies over the entire operating temperature range. Our MN574AT 12-bit ND, for
example guarantees ±'/2 LSB Integral Linearity at room
temperature and ±1 LSB from -55°C to +125°C. A 12-bit AID
converter that guarantees ±'/2 LSB Differential Linearity Error at + 25·C and gives a Differential Linearity Drift of
± 2ppm of FSR/·C will have a Differential Linearity Error of
±0.032% FSR at + 125·C, and ±0.032% is equivalent to
approximately 1 V2 LSB's. At 125·C this AID may have missing codes. We say "may have missing codes" because it is
possible that the converter transfer function bowed upwards such that the levels got wider and then smaller such
that no codes were missed. Normally, however, when this
type of drift phenomenon occurs, the manufacturers will be
proud of the fact that they have maintained No Missing
Codes and will say something to the effect of "No Missing
Codes guaranteed over temperature". If such a statement
does not appear, a user can only assume that the converter
began to miss codes when Differential Linearity exceeded
± 1LSB. At what temperature did that occur for the device
mentioned above? At what temperature did its Differential
Linearity Drift exceed ± 'hLSB? ± V2LSB= ±O.012% of
FSR = ± 120ppm of FSR. If Differential Linearity Drift is
± 2ppm of FSR/·C, it will take 60·C for the drift to equal
± 'h LSB. Therefore, the converter began to miss codes at
+ 25·C + (60·C) = + 85·C.
What Differential Linllarity Drift would a 12 bit AID that
guaranteed ± Y, LSB Differential Linearity at room
temperature (+ 25·C) have to maintain in order to guarantee
No Missing Codes up to + 125·C? ± 'h LSB = 120ppm of
FSR. 120ppm of FSR/AT = 120ppmof FSR/100·C = 1.2ppm of
FSR/·C.
Lastly, recall that ± Y, LSB Integral Linearity guarantees No
Missing Codes and Differential Linearity Error less than ± 1
LSB for AID converters. An AID that guarantees ± Y, LSB
Linearity and No Missing Codes at room temperature and
then gives an Integral Linearity Drift specification without
specifically stating what happens to Differential Linearity or
Missing Codes over temperature is not guaranteeing No
Missing Codes at any temperature other than + 25 ·C.
GAIN ERROR-As was the case with DIA's, AID Gain Error is
a measure of the deviation from the ideal of the slope of a converter's transfer function. The slope of an AID converter
transfer function can be defined as the slope of a straight line
from its first transition to its last transition. Tha slope of the
ideal transfer function, as plotted in Figures 42 and 43 is 45·
or 1. A device with positive Gain Error would have a more
steep transfer function. A device with negative Gain Error
would have a less steep transfer function. See Figure 54. AID
Gain Error is usually measured by first locating the "first" and
"last" transitions of a converter's transfer function. The first
Digital
Output
111
---+-
----- ---+
110
101
100
011
010
001
000
0.001.252.503.755.006.257.508.7510.00
~
Analog
Input
(DC Votts)
Figure 54_ Example of a unipolar AID transfer function exhibiting positive Gain Error. The ideal transfer function is
shown as the broken line.
4-27
transition for a unipolar AID is the one closest to zero for
unipolar positive devices and the one closest to the negative
full scale point for unipolar negative devices. The first transition for a bipolar device is the one closest to the negative full
scale point. The last transition is the last one at the other end
of the transfer function. Gain Error is the difference between
the real and the ideal values of the full analog interval between these two voltages.
Return to Figure 43. For this AID, the ideal first transition
voltage is - 7.5V, and the ideal last transition voltage is
+ 7.5V. The ideal difference between these two points is 15
volts (FSR-2 LSB's). If the transfer function of Figure 43 had
an actual first transition at - 8.0V and an actual last transition at + 7.75V the difference would be 15.75 volts. The difference between the ideal and actual values for this number
would be 15.75 - 15.00 = 0.75 volts. Expressed as a percentage, this gives a Gain Error of 0.75/15 5%. Note that this is
a negative Gain Error, the transfer function would be less
steep than ideal. For those who like to express Gain Error in
% FSR, the error would be 0.75 volts/FSR = 0.75 volts/20
volts = 3.75% FSR.
=
Gain Error is not an accuracy measurement, although as you
will see, it can be used to calculate an AID converter's Absolute Accuracy Error when this spec is not given.
RELATIVE ACCURACY-As we stated in the D/A section,
Relative Accuracy is a confusing specification, and you will
not see it used on a Micro Networks data sheet. It is the data
converter specification that has the greatest variety of definitions from different manufacturers. Micro Networks defines
the Relative Accuracy of an AID converter to be the measure
of how accurate any of the AID's transition voltages are
relative to a straight line drawn between the first and last transitions of the AID's actual transfer function. Relative Accuracy is usually expressed in (sub)multiples of LSB's or in
% FSR, and according to our definition, is exactly the same as
Integral Linearity Error according to the end-point definition.
Relative Accuracy does not include Gain and Offset Errors (to
be discussed).
As a data converter specification, Relative Accuracy has two
uses. Firstly, many manufacturers will use it for the purpose
of informing a user how accurate, relative to the ideal, he/she
can expect his/her AID to be after its initial Gain and Offset Errors have been adjusted to zero through the use of trimming
potentiometers. As an example, take the 3 bit, 0 to + 10V A/D
of Figure 42. If the manufacturer guarantees Relative Accuracy = ± ';' LSB, and the user adjusts the converter so that
its 000 to 001 transition occurs at an input voltage of exactly
+ 1.25 volts and its 110 to 111 transition occurs at an input
voltage of exactly + 8.75 volts, every other transition voltage
will be within ± V, LSB (± 0.625 volts) of what it is supposed
to be. The second use of Relative Accuracy is that some
manufacturers will use it in lieu of an Integral Linearity Error
spec. This is fine if the intent is not to deceive. We stated
earlier that in order for an n bit converter to be a true n bit converter, its Integral Linearity Error should be no worse than
± 'I, LSB for n bits. Many times, when Relative Accuracy appears in lieu of Integral Linearity Error, we have noticed theerror to be greater than ± % LSB. Beware of high resolution (12
bits and up) AID converters or Data Acquisition Systems that
spec "accuracies" better than ± 2 LSB's. As a practical matter, such levels are difficult to achieve in state-of-the-art AID's
without external gain and offset adjustments. The manufacturer probably means Relative Accuracy.
AID CONVERTERS-ABSOLUTE PERFORMANCE
SPECIFICATIONS
ABSOLUTE ACCURACY ERROR-The Absolute Accuracy
Error of a voltage input AID converter is the difference between the actual, unadjusted, analog input voltage at which a
4-28
given digital transition occurs and the analog input voltage at
which that transition is ideally supposed to occur. This difference is usally expressed in LSB's or % FSR.
The two key words in this definition are "unadjusted" and
"given". "Unadjusted" means just that; an AID converter's
Absolute Accuracy has to be measured before any optional
gain and offset adjusting is performed. This is where Absolute Accuracy differs from Relative Accuracy. Absolute Accuracy tells you how accurate your converter is going to be if
you simply plug it in, power it up, and start converting.
Relative Accuracy tells you how accurate it will be after you
go through the gain and offset error adjusting procedure.
"Given" refers to the fact that any Absolute Accuracy
specification has to be accompanied by some indication of
where along the converter's input/output transfer function
the spec applies, Le., for which digital output transition is the
Absolute Accuracy of the input voltage to be measured. If no
such indication is given, a user can only assume that a given
Absolute Accuracy Error spec applies over the converter's entire input/output range, i.e., it applies to every transition.
Because Absolute Accuracy Error is measured and specified
without adjustment, it includes all factors that may be affecting the converter's accuracy at the point of
measurement-Offset Error, Gain Error, Linearity Error, and
Noise Error.
Refer back to Figure 42. Assuming the transfer function is
linear, the two key points necessary to fully describe this AID
converter's Absolute Accuracy would be at positive full scale
(110 to 111 transition) and at zero (000 to 001 transition). To
avoid ambiguity, the specs would be called Unipolar Positive
Full Scale Absolute Accuracy Error and Unipolar Zero Absolute Accuracy Error (also called Unipolar Zero Error). Refer
back to Figure 43. The three key points necessary to adequately describe the Absolute Accuracy of this device are at
positive full scale (110 to 111 transition), negative full scale
(000 to 001 transition), and zero (011 to 100 transition). The
three relevant specifications are Bipolar Positive Full Scale
Absolute Accuracy Error, Bipolar Negative Full Scale Absolute Accuracy Error, and Bipolar Zero Absolute Accuracy
Error (also called Bipolar Zero Error).
FULL SCALE ABSOLUTE ACCURACY ERROR- This is the
Absolute Accuracy Error measured for the output transition
that brings the digital output to the code representing a full
scale input. If it is the positive full scale code, some people
may refer to the transition as the "last" transition. If it is the
negative full scale code (for unipolar negative or bipolar converters) some people may refer to the transition as the "first"
transition. We avoid this terminology because in complementary coded converters, it is not clear what first and last transitions mean.
Some manufacturers will draw a distinction between
Unipolar and Bipolar Positive and Negative Full Scale Absolute Accuracy Errors. Micro Networks normally does not.
For unipolar positive, unipolar negative, or bipolar input
ranges, our Full Scale Absolute Accuracy Error specification
refers to either the positive or negative full scale point or both,
whichever is appropriate. Take our MN5200 and MN5210
Series 12 bit AID's. These devices offer input ranges of 0 to
- 10V, 0 to + 10V, ± 5V, and ± 10V, and our data sheet lists a
Single Full Scale Absolute Accuracy Error. The spec applies
for all the full scale output points, Le., it means Unipolar
Positive Full Scale Absolute Accuracy when using the 0 to
+ 10V range, Unipolar Negative Full Scale Absolute Accuracy when using the 0 to - 10V range, and both Bipolar
Positive and Bipolar Negative Full Scale Absolute Accuracies when using the bipolar ranges. We will list the errors
separately if they have different values.
ZERO ERROR-This is the Absolute Accuracy Error
measured for the output transition that brings the digital output to the code corresponding to an input of zero volts. Micro
Networks will draw a distinction between Unipolar and
Digital
Output
111
110
101
100
011
010
001
Analog
Input
(DC Volts)
000
1 25
875
--+1
~Un'rolar~
Unipolar
Positive
Full Scale
Absolute
Accuracy
Error
Zero
Error
(a)
I<-
Bipolar Zero Error for converters that have different values for
these two specifications. Otherwise, we simply give a single
Zero Error specification.
Full Scale Absolute Accuracy and Zero Error are summar·
ized in Fig. 55. If an AID converter is linear, i.e., if its Integral
linearity Error is less than ± 1j, LSB, the Absolute Accuracy
of any transition can be found through interpolation of the
Full Scale and Zero Errors as the sketches show. The 3 bit AID
whose transfer function is shown in Figure 56 has a Negative
Full Scale Absolute Accuracy Error of -1.25 volts (-1 LSB),
a Bipolar Zero Error of - 0.625 volts ( - V, LSB), and a Positive
Full Scale Absolute Accuracy Error of zero volts. As was ex·
plained in the DIA section, Full Scale Absolute Accuracy and
Zero Errors are the way in which Micro Networks prefers to
specify converter accuracy.
Digital
Output
111
110
---
I
1 LSB
->I
- 5 00
----->I
Accuracy
Error
875
--->I
I<-
Unipolar
Zero
Error
1 25
-375
101
0625 100
+3.75
Analog
Input
(DC Volts)
011
I<---111
--
I<-
Analog
Input
(DC Volts)
010
001
110
000
101
//-
/-/
,hI
->I I<-'" LSB
100
Figure 56. Example of a 3 bit, ± 5V input range AID converter
with a Negative Full Scale Absolute Accuracy of - 1.25 volts
(- 1 LSB), a Bipolar Zero Error of - 0.625 volts ( - ,/, LSB), and
a Positive Full Scale Absolute Accuracy Error of zero.
011
010
001
000
+----'
Digital
Output
OFFSET ERROR-Micro Networks does not emphasize AID
Offset Error as being an important specification for the same
reason we don't emphasize DIA Offset Error. You have to
understand the inner workings of an AID in order to understand exactly where its Offset Error specification applies.
Let us simply say that an AID's Offset Error has to be
measured when the DIA internal to the AID would have its
Offset Error measured. The AID's Offset Error should be
measured when the current coming out of the internal DIA is
zero. This may occur at the first transition (000 to 001) or it
may occur at the last transition (110 to 111); you have to
know how the AID works to know where its Offset Error
specification applies.
Digital
Output
,---+
111
+375
001
Bipolar
Positive
Full Scale
Absolute
Accuracy
Error
I<----
Analog
Input
(DC Volts)
000
(el
->I
I<-
Bipolar
Zero
Error
An AID's Offset Error is often but not alwavs eauivalent to its
Zero Error.
An AID's Offset Error will always be the same as either its
Zero Error or its Full Scale Absolute Accuracy Error, and we
much prefer these specs, for as we stated previously, we
believe that most converter users prefer to think of converters
as building blocks with certain input/output characteristics,
and they really don't care what goes on inside of them. Many
of our data sheets do list Offset Errors, however; the specs
are there solely to facilitate comparing our converters to
those of other manufacturers who prefer to spec Offset Error.
AID CONVERTERS -DYNAMIC SPECIFICATIONS
Figure 55. Summary of Full Scale Absolute Accuracy and
Zero Errors for unipolar positive AID converters (a), for
unipolar negative AID converters (b), and for bipolar AID
converters (c).
CONVERSION TIME-Conversion Time is exactly that-the
time required for an AID converter to perform a single conversion. For successive approximation AID's, Conversion Time
can be defined as the width of the converter's status output
4-29
pulse. See Figure 41. Conversion Time is not equivalent to the
time it takes an AID in a system to produce new valid output
data. There are two pitfalls users shou Id be aware of. The first
is that for a high percentage of SA type AID converters, output
data is not valid when the converter's status line indicates
that the converter is done converting. Normally, due to different propagation delays for high and low signals, the LSB
will not achieve its final value until some time after the status
changes. This delay is normally only tens of nanoseconds,
but if you're not aware of it, you'll get erroneous LSB data
when using the status to strobe a register to latch your output
data. You may have to add a delay. The other problem occurs
at the other end of a conversion, at the start. Most SA type AID
converters don't start the instant a start signal comes along.
They reset on a rising clock edge after the start signal has
changed levels. There is usually a setup time requirement
that says you have to change the start some time before the
clock edge, usually tens of nanoseconds. See Figure 41.
4-30
Oftentimes, the conversion won't continue until the start
signal returns to its original level, so you'll want to have it
return before the next clock edge or suffer additional delay.
The net result of setup time and LSB delay is that it will normally take at least one additional clock period beyond the
status period to update valid digital output data.
Another thing users should be aware of is that SA type AID
converters calling for external clocks will require the generation of a precise frequency to achieve the fastest conversion
times.
Text and sketches by Chuck Saba/is
Track and Hold Amplifiers
Track and Hold (T/H) and Sample and Hold (S/H) amplifiers
are widely used in data acquisition, data distribution, and
analog signal processing systems. They are devices that
accurately store analog voltages. They could be called
"voltage memories". Their single most popular application is
to "freeze" the input voltage to an AID converter at the
instant a conversion begins and to hold this voltage constant
during the conversion process. In this application as in most,
the characteristics of the T/H or S/H are crucial to overall
system accuracy, especially in high speed or high resolution
systems. Micro Networks manufactures a number of T/H
amplifiers. In this section, we will discuss some of the
problems encountered in T/H design and operation and
explain how Micro Networks has minimized their effects.
We will define key T/H specifications and explain what to
look for on manufacturers' data sheets. Lastly, we will demonstrate three popular T/H applications: an AID aperture
reducer, a D/A deglitcher, and a peak detector.
WHEN IS A T/H A S/H?
In general, people will use the terms Sample and Hold.and
Track and Hold interchangeably. There is a distinct difference between the two, however. Both are linear circuits that
have three operational terminals and two modes of operation. The terminals are the analog input terminal, the analog
output terminal, and the digital control terminal. The operating modes are obviously the track mode and the hold mode
for the T/H and the sample mode. and the hold mode for the
S/H. When a T/H is in the track mode, its output follows or
tracks and is equal to its input. When commanded into the
hold mode, the T/H's output becomes constant and equal to
~
,,
THE CIRCUITS AND THEIR PROBLEMS
Figure 2 shows a T/H circuit in its simplest form. The circuit
consists of an electronically controlled switch and a hold
capacitor. When the switch is closed. the voltage at the input
terminal appears across the capacitor, and the output voltage
will equal the input voltage. If the input voltage now changes,
the capacitor will charge or discharge and the output voltage
will follow. When the switch is opened, the capacitor retains
its charge and the output voltage remains equal to the input
voltage at the instant the switch was opened.
Track/Hold
Command
Analog
Output
,
its input value at the instant the device was commanded into
the hold mode. A T/H can remain in either operational state
indefinitely. A S/H cannot operate indefinitely in either
mode. When commanded to the sample mode, it will take a
very fast sample and immediately go back into the hold
mode. It normally spends most of its time in the hold mode
with its output at some fixed voltage; it cannot track an input
signal. A T/H amplifier can be used as a S/H. A true S/H
amplifier cannot be used as a T/H. In practice, most samplel
hold amplifiers manufactured today are actually track and
hold amplifiers. The few true S/H amplifiers made today will
clearly be labeled as being such. Figure 1 summarizes the
difference between T/H and S/H amplifiers.
Hold
Hold
\
Figure 2. In a simple track and hold circuit, when the switch
is closed the output voltage equals the input voltage. When
the switch is opened, the capacitor retains its charge and the
output voltage remains constant.
The electronic switch is digitally driven. For Micro Networks
T/H's, a logic "0" applied to the unit's control input commands the device into the hold mode. A logic "1" commands
it to the track mode.
Hold
Analog
Output
~
Analog
Input
_L-
,,
,,
Track
\
\
t
Hold
Time
CB---L----------~+_--------~~
Hold
Figure 1. A sample and hold amplifier (1a.) takes a quick
sample of the input signal and immediately returns to the
hold mode. A track and hold amplifier (1b.) can track the
input for part of the time and hold it for the rest of the time.
A T/H can remain indefinitely in either operational mode.
If the electronic switch is a FET, its gate can be driven directly
or through an appropriate driving circuit. In either case, the
"speed" with which this circuit's analog output can follow its
analog input will be determined by the time constant of the
switch "on" resistance and the hold capacitor, providing the
input is driven from a low impedance source. Adding a fast,
high impedance buffer amplifier (voltage follower) in front of
the switch not only charges the hold capacitor from a low
impedance source, it gives the overall T/H circuit a high input
impedance. This is important since in some applications, the
T/H will be operating at the output of a high impedance
signal source, and the source should not be overloaded. The
speed, accuracy, and drive capability of the input buffer will
obviously affect the overall response of the T/H circuit, and
the buffer should be carefully chosen. The ability of the
circuit to hold a voltage will depend on how quickly the
capacitor loses its charge after the switch has opened. Si nce
in this example, the capacitor is connected directly to the T/H
output, the output loading is important. This condition is
eliminated by placing a second buffer (voltage follower)
between the hold capacitor and the T/H output. This buffer
should be a fast, FET·input device with a very high input
4-31
impedance and a low input bias current to prevent hold
capacitor charge from leaking off too rapidly. It should also
have a low ,output impedance enabling the T/H to drive
relatively low input impedance devices such as most AID
converters (typically 2KD to 20KD input impedance).
Similiarly, to prevent capacitor leakage, the FET switch
should have a low "off" leakage, and the hold capacitor
should be a low leakage device with a high insulation
resistance. Most hybrid T IH's with internal hold capacitors
will employ NPO ceramic capacitors. Other acceptable
capacitor types are polystrene, polypropylene, polycarbonate, and Teflon. Figure 3 shows the simple circuit of Figure 2
with input and output buffers added.
ArJalog
Input
Analog
Output
Figure 4. FET source to drain capacitance causes leedthrough. Gate to drain capacitance results in charge injection when the FET gate voltage changes causing Pedestal.
RIN
Analog
Output
Analog
Input
~ 6Vq
Control
RF
~~~I~? o--"vvv/-:r--'V'v'V--r-------,
Summing
Point
Figure 3. Adding a buffer in front of the switch quickens
capacitor charging and gives the T/H high input impedance.
Adding a buffer behind the hold capacitor reduces capacitor
charge bleeding and output droop.
The track and hold circuit as described so far (Figure 3) can
be extremely fast if a fast switch and fast followers are
employed. It will be reasonably accurate; however, accuracy
will be limited by offset, gain, and linearity errors in the
followers as well as by imperfections in the switch. The main
problem with the switch is capacitance-both across it from
input to output and between its output and its control (gate)
input (see Figure 4). Capacitance across the switch (sourcedrain capacitance in the case of a FET switch) will cause
some of the input signal to be coupled through to the holding
capacitor even when the switch is off. This is called "feedthrough". Capacitance between the switch output and its
gate input (gate-drain capacitance in the case of a FET
switch) will cause a step or "pedestal" in the hold voltage as
the switch is turned off. This pedestal error results from a
phenomenon called charge injection or charge dumping.
Refer to Figure 4. The gate to drain capacitance of the FET
switch couples the switch-control voltage (Vg) on the gate to
the hold capacitor. When the switch is turned from on to off,
an amount of charge equal in magnitude to Cgd times the
change in FET gate voltage (Q = Cgd /':,V g) transfers from the
hold capacitor to the gate drive circuit. This produces an
error in hold voltage equivalent to the product of the step in
gate voltage and the gate to drain capacitance divided by the
hold capacitance.
/':,VH=..9..= Cgd/':,V g
CH
CH
Since increased speed is often obtained by reducing the size
of the hold capacitor, pedestal error may become unacceptably high. Compounding this problem in a floatingswitch type track and hold such as the one we have been
describing, is the fact that the apparent gate signal amplitude
will change as the analog signal changes. Return again to
Figure 4. The switching voltage applied to the gate of the FET
will usually step between two fixed levels, but the instantaneous voltage appearing at the drain of the FET will be
equal to VH and changing all the time. Therefore, the amount
of charge injected and hence the magnitude of pedestal error
will be a function of the instantaneous analog voltage
present on CH when Vg changes. In other words, pedestal
4·32
Control
Figure 5. Pedestal amplitude dependence upon input voltage
level is eliminated by having the FET drain operate at virtual
ground. The drain voltage of the FET in Figure 4 is equal to
VH and changes with input voltage. The circuit above does
not eliminate pedestal but keeps it constant.
Control
Figure 6. Pedestal error resulting from charge injection is
compensated for by adding to the amplifier's non-inverting
terminal a switch (S2) and capacitor (CPed) circuit the same
as the main switch (S1) and hold capacitor circuit. Equal
and opposite charge injections result in pedestal cancellation. c.f. Figure 5.
error, already a problem by its mere presence, will vary in
magnitude with analog signal level, possibly in a non-linear
manner.
One solution to this problem is to place the switch in the
circuit in such a way that it never sees a voltage change while
in the track mode. Such a circuit is the "summing-point
switch" type track and hold of Figure 5. In its most basic
form, the circuit consists of an op-amp wired for inverting
gain with a switch between the summing point and the
inverting input of the amplifier. The hold capacitor is placed
between the amplifier output and its inverting input, where it
will acquire the inverse of the analog input signal as long as
the switch is closed and RIN equals RF, i.e., the circuit has
unity gain. When the switch is opened, the amplifier becomes, in effect, a unity gain follower with an output offset
with respect to the grounded non-inverting input equal to the
voltage present on the holding capacitor at the moment the
switch opens. A pedestal will be generated by charge
injection as before, but its amplitude will not be a function of
the analog input voltage.
Although constant in amplitude, the pedestal generated by a
summing-poi nt-switch track and hold may still be unacceptable. It is possible to remove most or all of it by inducing a
step of equal amplitude on the non-inverting input of the
amplifier. One way to accomplish this is to place a switch of
the same type as the summing point switch (Sl) in parallel
with a capacitor the same value as the hold capacitor
between the non-inverting input and ground (see Figure 6).
This auxiliary switch (S2) is driven by the same gate signal
that drives the main switch so that when a hold command is
given, equal amounts of charge are transferred into both the
holding and pedestal compensation capacitors (CPed). Any
pedestal which still remains due to a slight switch or
capacitor mismatch can be eliminated by adjusting the value
of the pedestal compensation capacitor.
Control
Figure 7. Capacitance coupled feedthrough is reduced with
the addition of a back-to-back diode pair to the summing
point. The diodes restrict the voltage swing at the summing
point while in the hold mode. Capacitively coupling the
amplifier non-inverting input to the summing point with a
capacitor (CFdtu) equal in magnitude to Csd(see Figure 4)
effectively eliminates this component of feedthrough.
WHAT ABOUT FEEDTHROUGH?
As previously mentioned, another pr'oblem caused by switch
capacitance is feedthrough. Switch capacitance induced
feedthrough will have an amplitude equal to the summing
point signal amplitude times the switch source-drain capacitance (Csd) divided by the hold capacitance (CH). One means
of reducing this effect is to employ a summing point clamp.
This may be a FET switch to ground or simply a back-to-back
diode pair (see Figure 7) used to restrict the voltage swing at
the summing point during the hold mode. If a FET switch to
ground is used, it must be turned off while in track to allow
the summing point to move slightly. The back-to-back
diodes, however, may be left in place at all times since in
normal operation the summing point is a virtual ground and
need only move small amounts in response to high speed
signals. An added benefit of the summing point clamp is that
by restricting the voltage swing on the switch input, the gate
signal need not move as far to insure complete turn-off under
all input/output conditions.
another switch of the same type as the main switch permanently wired in the off state.
The switch is not the only path for feedthrough; some input
signal can travel directly to the output through the feedback
resistor. I n this case it is the ratio of the feedback resistor to
the output impedance of the amplifier that determines
feedthrough amplitude. Also, feedback path induced feedthrough will be in phase with the input while summing point
switch feedthrough will be out of phase. It is the feedback
path feedthrough that will tend to dominate at higher
frequencies as the output impedance of the amplifier increases. This type of feedthrough is very difficult to cancel,
and may therefore be a limiting factor in high speed track and
holds. The only way to combat it, besides using a faster
amplifier, is to use larger feedback resistors. This procedure,
while reducing feedthrough, may also affect speed by
increasing the time constant with any capacitance associated with the summing point.
As with pedestal, the only effective means of completely
eliminating feedthrough (at least at low frequencies) is to
cancel it by injecting a signal of equal amplitude and
opposite polarity. This can be done by capacitively coupling
the summing point to the non-inverting input of the amplifier,
either with a small capacitor (CFdtu in Figure 7) or by using
So far in the discussion, it has been assumed that when the
main switch (Sl) is closed, the summing point drives the hold
s,
Figure 8. Adding a low output impedance, current boosting
buffer (A2) in front of the main switch (Sl) quickens acquisition time. FET input buffers before the main amplifier (Al)
reduce charge leakage and droop rate. If the main amplifier
(Al) is a high speed device, RComp provides compensation in
the track mode. CComp provides compensation in the hold
mode. This is the basic circuit employed in MN343, MN344,
MN346 and MN347 T/H amplifiers.
-=Control
4-33
capacitor directly. This condition may limit the speed of the
device since the time constant generated by the holding
capacitor and the feedback resistor (together with the onresistance of the switch) will determine the time required by
the track and hold to aquire the input to any given accuracy.
Return to Figure 5. With RF = 2KO and CH = 2000pF (assume
Ron for the FET is negligible compared lothe 2Kfl) T = RFCH =
4l'Sec. Therefore, to charge CH to within 0.01% (% LSB for a
12 bit converter) of its final value will take about 9 time
constants or 36 I'sec.
Reducing the feedback resistors and/or reducing the value
of the hold capacitor may improve speed but only by
sacrificing performance in the areas of feedthrough and
pedestal. One solution is' to insert a voltage follower (A2) into
the feedback loop, i.e., between the summing point and the
switch (see Figure8). It is now this amplifier and not the main
amplifier that provides the current to charge the hold
capacitor, The hold capacitor can now acquire a voltage at a
rate determined by the output current capability of the
follower, providing the slew rate of the main amplifier and its
output drive capacity are sufficient. Output settling time can
still be limited by capacitance at the summing point, but its
value is now greatly reduced and consists mainly of the
summing point clamp and follower input capacitance.
Adding the buffer allows us to increase the values of RIN and
RF which in turn reduces feedback path induced feedthrough and increases T/H input impedance.
WHAT ABOUT THE HOLD MODE?
Once the track and hold has aquired a desired voltage, it
must be able to hold it for a reasonable length of time to
within given limits of drift. The main cause of any change in
output voltage will be a loss of charge from the hold
capacitor to the virtual ground at the inverting input of the
amplifier. Leakage from the pedestal compensation capacitor, if used, to the non-inverting input node of the amplifier
will have a similar effect but in the opposite direction.
Assuming the off-resistance of the switches used is very
high, most of the leakage will be into the amplifier inputs.
This can be reduced considerably by placing suitable FET
input followers in front of the amplifier (see Figure 8). The
followers, however, will lose their effectiveness somewhat at
higher temperatures due to the doubling of gate leakage
experienced by FET's every 10' C. Capacitor characteristics
such as leakage and dielectric absorbtion or "soakage" will
add to the problem, so choose carefully. The net effect versus
time of hold capacitor charge loss is termed "droop rate."
TIMING, WHEN IS THE T/H REALLY HOLDING?
We said earlier that the T/H's FET switches are driven from an
"appropriate driving circuit." Switching the track and hold
from one mode to the other involves converting the logic "1"
or "0" at the unit's control input (usually TTL or ECL) to a
driving signal capable of opening or closing the appropriate
switches. The output of the driving circuit (gate circuit) will
depend on what types of switches are to be driven and may
even involve two or more outputs delayed so as to activate
switches in a predetermined sequence. Sequential switching
may be required when, for example, the main summing point
switch must be opened prior to applying an active summing
point clamp so as to avoid the large step that would result
from grounding a "live" summing point. The gate circuit
must act quickly, with whatever delay that does exist being as
consistant as possible. The length of the gate circuit delay
can be compensated for to some extent by adding analog
input delay or possibly by advancing the control input
slightly. However, variations in gate circuit delay will result in
errors since the analog signal may change significantly over
the period of time during which the T/H is actually moving
into the hold mode. The slope of the output of the gate circuit
is also important, as it may determine how quickly the switch
itself takes to turn off. Speed is critical here for the same
4-34
reason that consistency in gate delay is important: it is
needed to pinpoint the exact time at which the analog input is
held. In spite of all these considerations, the chain of events
set in motion by activating the gate circuit is not ended even
when all the switching has been done. When switching into
"track", the analog input must still be aquired; and when
switching into "hold", the output must settle in response to
being hit with any residual pedestal and/or spikes generated
by the switching process.
A discussion of the factors governing the selection of the
main amplifier (A1 in Figures 4-8) might prove useful at this
point. The main amplifier is undoubtedly the most important
element in determining the overall speed and accuracy
characteristics of the track and hold, and it will usually
consume most of the power. Its slew rate may limit the slew
rate ofthe track and hOld, and in any case, will determine the
upper limit of the current output requirements placed on the
follower driving the hold capacitor (see Figure 8). As mentioned previously, the output impedance of the main amplifier will have a marked effect on feedthrough, especially at
the higher frequencies. The amplifier's settling time will be
the limiting factor in determining the settling time of the
whole circuit; however, delays in the feedback loop will also
have an effect here. It is quite often the case that the faster
amplifiers will not be unity gain compensated and must be
run at higher gains to achieve their specified settling times.
In order for the track and hold to maintain stability and an
overall gain of one (or at least minus one), some form of
frequency compensation must be applied. While in the
"track" mode, compensation can be applied to the summing
point in the form of a resistor to ground (Rcomp in Figure 8).
The value is selected so that its ratio to the value of the
feedback resistor gives the closed loop gain required to
maintain stability and best settling time. Since this internal
loop gain will increase any offset by the same amount, a
capacitor is sometimes inserted in series with the compensation resistor to eliminate it from the loop at low frequencies
and D.C. where compensation is not needed. When in the
"hold" mode, compensation can be applied by means of a
capacitor between the inverting and non-inverting inputs of
the amplifier (CComp in Figure 8). Once again its value is
chosen to give the required gain when compared in value
with the holding capacitor. This capacitor will, of course,
have no effect on offset but may affect speed slightly.
SPECIFICATION DEFINITIONS
Specific definitions of terms have not been stressed so far in
this discussion. This was done in the belief that definitions
would have more meaning after the operation of the track
and hold circuit as a whole had been presented. Although the
definitions of the terms used to describe various effects are
quite important, there appears to be some ambiguity and
even some difference of opinion when it comes to interpreting actual manufacturers' data sheets. Terms containing the
word "aperture" appear to be particularly confusing and are
rarely clearly defined. The following list contains what are
believed to be the most logical and often used definitions for
the terms given, at least when they are applied to sample and
hold and track and hold circuits. Refer to Figure 9 for
clarification.
ACQUISITION TIME The elapsed time between the application of a "track" command and the point at which the analog
output has arrived at within a specified percentage of its final
value. Acquisition time will include gate delay, amplifier
settling time, and any time spent slewing between voltages.
Because of slew rate limitations, actual acquisition time will
depend upon the amplitude of the voltage change to be
acquired. When specifying acquisition time, both the analog
output step size and the permitted error band must be given.
~
MICRD NETWDRKS
QJ] MICRO NETWORKS
324 Clark 51., Worcester, MA 01606 (508) 852-5400
4-38
Analog
Output
Figure 11. A T/H can be used to make a peak detector. The
comparator compares the T/H's input and output. When the
T/H input exceeds its output, the comparator selects the
track mode. If the input falls below the output, the comparator selects the hold mode and the peak is stored.
Unfortunately, the circuit just described doesn't always
work. One problem is that if the comparator does not select
the hold mode whenever the input equals the output, the
circuit will remain in track forever. To overcome this, the
comparator input offset must be set to insure hold is selected
when its inputs are equal. Too much offset will, however,
produce an offset error in the held peak value. A more
serious problem can result from hold pedestal. If pedestal
polarity is such that it forces the comparator to go back into
track immediately following the switch into hold, the output
will oscillate around the input value and it will be impossible
to hold a peak. For this reason, the pedestal polarity must
always be in the same direction as the peak being held. This
makes reversing the polarity of the peak detector difficult,
since it is usually not practical to reverse the pedestlit.of the
track and hold. Transients following a track command may
result in errors if the track and hold is told to hold before it
has settled. For this reason, a "pulse stretcher" should be
used between the comparator and the logic input of the track
and hold which will delay the hold command during the
track-mode settling time. Speed will of course be limited by
the pulse stretcher delay. A delay of five microseconds, for
example, will result in a maximum speed of about 1 KHz for
0.05% accuracy.
This discussion about peak detectors is given to illustrate
some of the problems actually encountered when using
track and hold circuits. (There are, in fact, better ways to
construct peak detectors than by using a comparator with a
track and hold, but they will not be dealt with here.) Track
and hold circuits can be very useful in many designs, but an
understanding of their problems and limitations is crucial in
avoiding misapplication.
Text and sketches by
Marshall Shepard and
Chuck Sabalis
4-37
percentage of the TIH's full-scale voltage swing. A TIH used
in an n bit system should be linear to within ±'/, LSB for n bits.
OFFSET (TRACK MODE) The D.C. voltage appearing at the
analog output while in the track mode with the analog input
grounded. It will usually be temperature dependant, and this
dependance should be specified. To avoid confusion, Micro
Networks calls this parameter Track Offset or Sample Offset.
Offset (Hold Mode) or Hold Offset refers to the voltage with
respect to ground appearing at the output immediately after
the circuit is commanded into the hold mode with the input
grounded. Hold Offset can be as large as Track Offset plus
Pedestal Error.
PEDESTAL An unwanted D.C. step in the output voltage
occurring as the circuit is driven into the hold mode. It is the
result of unequal charge transfer to the input nodes of the
main amplifier during the switching operation. It may also be
called Sample to Hold or Track to Hold Offset.
Analog Input
-----------
Analog O u t p u t - - - - -
Offset Error
(Track mode)
Pedestal Error
Offset Error
(Hold mode)
-
Track
~
Hold
Figure 10. Summary of Offset (Track Mode). Offset (Hold
Mode) and Pedestal Errors. Broken line is T/H analog input.
Solid line is analog output. Analog input level equals zero
volts.
SAMPLE AND HOLD A linear circuit capable of holding the
instantaneous value of its analog input signal present at the
moment a "sample" command is given. The circuit is normally
in the "hold" mode and cannot "track" an input. Output
droop prevents the circuit from holding a signal idefinitely.
SAMPLE RATE The maximum frequency at which a complete sample and hold operation can be performed while
remaining within specified accuracy limits. It will be the
inverse of the period determined by adding Acquisition Time
and Track to Hold Settling Time.
SETTLING TIME (TRACK MODE) The time required for the
track and hold output to stabilize in the track mode to within
specified limits of its final value following a step change
applied at the analog input.
SETTLING TIME (TRACK TO HOLD) The time required for
the track and hold output to stabilize in the hold mode to
within specified limits of its final value following the transition
from the track mode.
SLEW RATE The maximum rate of change in voltage with
respect to time that the analog output is capable of developing while attempting to track the input. The slope will
usually be determined either by the main amplifier or by the
current available for charging the holding capacitor. Slew
rate will limit the full power bandwidth of the track and hold.
SMALL SIGNAL BANDWIDTH The maximum analog signal
frequency that can be tracked before the gain is reduced by
more than 3db. This presumes the signal amplitude is small
enough so as not to be slew rate limited.
4-36
SUMMING POINT The pOint in the feedback loop of a
summing-poi nt-switch type track and hold circuit (see Figure
5) which is connected to the inverting input of the main
amplifier to produce the inverting gain configuration required for tracking. It can also be used as a current-tovoltage input to the circuit, which can be convenient in some
applications.
TRACK AND HOLD A linear circuit capable of holding the
instantaneous value of the analog input signal present at the
moment a "hold" command is given. The circuit can remain
indefinitely in either mode, however, output droop will cause
the accuracy of a held voltage to decrease with time.
APPLICATIONS
There are two basic types of applications for which track and
hold circuits are normally used. One is the situation in which
the instantaneous value of a rapidly changing analog signal
must be stored temporarily so it can be measured or
operated on by equipment with limited bandwidth. The other
arises when it is desirable to eliminate some portion of an
analog signal by holding a previous value during the interval
in question.
An example of the first type is the use of a track and hold
circuit at the input of an analog to digital converter. If the
analog input of a Successive Approximation AID Converter
changes by more than ±'/, LSB during the conversion
interval, significant errors may result. To enable an AID
converter to accurately convert the instantaneous value of a
high speed input signal, a track and hold is used in front of
the AID. It is timed to acquire the signal, track it, and hold it
when necessary for as long as it takes to complete a
conversion. With this arrangement, the AID converter "sees"
only the droop rate of the track and hold circuit, which
usually is not a problem with relatively high speed AID's.
An example of the second type is a D/A Deglitcher. When
converting a digital signal into analog form, a 01 A converter
may produce spurious spikes or "glitches" in the analog
output. These spikes are normally due to non-synchronous
switching of current sources. In some applications these
glitches may detract from overall circuit performance and
must therefore be removed. One way to accomplish this is to
follow the OIA converter with a track and hold circuit which
is placed in the hold mode just before the digital inputs of the
01 A are permitted to change state. It is then returned to the
track mode when sufficient time has elapsed to insure the
01 A analog output has settled to its new value. If the 01 A
converter is a current-output type, this output can often be
fed directly into the summing point of the track and hold
circuit. With this arrangement, the track and hold can be
made to double as a current-to-voltage amplifier.
A third often mentioned application of track and hold circuits
is in a peak detector. This is a circuit capable of storing the
highest (or lowest) values an analog signal reaches during a
given period of time. At first glance it seems quite simple to
build, but real-world operating characteristics make the
track and hold based peak detector a fairly difficult design
problem.
The basic circuit consists of comparing the input and output
of the track and hold with a voltage comparator and using the
comparator output to control the gate (see Figure 11). When
the input of the track and hold exceeds the output, the
comparator selects the track mode. If the input falls below
the output, the hold mode is selected and the previous peak
is stored. Reversing the inputs of the comparator will reverse
the polarity of the stored peak. A possible variation on this
design involves comparing the summing point of the track
and hold (if available) with ground.
For the MN343 and MN346, for example, Micro Networks
specifies Acquisition Time for a 20 vol! step settling to within
±0.01% FSR of its final value.
APERTURE The time required by the main signal-path
switch to change from a low-impedance state to a highimpedance state, thereby placing the circuit in the "hold"
mode. I! is determined by the gate circuit output slew rate
and/or by the characteristics of the switch itself and does not
include other gate circuit char3cteristics such as gate delay
(see Aperture Delay). While normally short enough to be
neglected, it will affect the precision with which the exact
point at which the hold mode begins can be known. Aperture
is rarely specified on manufactures' data sheets. When it
does appear, the manufacture invariably means Aperture
Delay.
APERTURE DELAY, APERTURE TIME, APERTURE TIME
DELAY The time lag between the application of the "hold"
command and the instant the output stops tracking the input.
"Stops tracking" can be defined as being able to meet the
feedthrough attenuation specification. Aperture Delay is
determined primarily by the switch drive circuit and includes
aperture.
APERTURE JITTER A rapid and random fluctuation in
Aperture Delay brought about by noise in the gate circuit. I!
will appear as a variation in Aperture Delay from sample to
sample. Errors resulting from aperture jitter will increase in
direct proportion to the slope of the analog input signal.
APERTURE TIME Equivalent term for Aperture Delay.
APERTURE UNCERTAINTY Sometimes used synonymously with Aperture Jitter, Aperture Uncertainty should also
include middle and long-term fluctuations in Aperture Delay
brought about by the combined effects of temperature,
aging, and digital input speed and amplitude on the gate
circuit.
CHARGE INJECTION, CHARGE TRANSFER, CHARGE
DUMPING In a T/H orS/H, Charge Injection is the phenomenon of moving a small amount of charge from the main
signal path switch to or from the hold CapaCitor during
switch turn-off. It is caused by the change in switch controlling voltage being coupled through switch capacitance tothe
hold capacitor. It is the cause of Pedestal.
DROOP RATE The rate of change in output voltage with
time while in the hold mode. Droop results from charge lost
by the hold capacitor and pedestal compensation capacitor
(if used) to the input nodes of the main amplifier. Droop rate
will normally change with temperature, and therefore should
always be specified at a given temperature. Micro Networks
specifies maximum droop rates over fixed temperature
ranges.
FEEDTHROUGH The amount of analog input signal coupled
through to the analog output while the circuit is in the hold
mode. It may have any phase relationship with the input and
will normally increase at higher frequencies.
FEEDTHROUGH ATTENUATION The ratio of feedthrough
amplitude to the analog input signal amplitude while in the
hold mode. It is usually expressed in dB's with the most
negative values being, of course, the most desirable. It
should be specified at a given frequency or as a function of
frequency. A graph is preferable.
FULL POWER BANDWIDTH, LARGE SIGNAL BANDWIDTH
The frequency at which a full scale input /output sine wave
becomes slew rate limited.
GAIN, GAIN ACCURACY The ratio of the change in analog
output voltage to the change in analog input voltage while in
the track mode. Gain Accuracy refers to how close the slope
of the T/H's input/output transfer function approximates the
slope of the ideal transfer function. Positive or negative unity
gain is most common for track and hold circuits, but any
value is possible.
GATE DELAY Equivalent term for Aperture Delay.
LINEARITY The maximum deviation from the best-fit straight
line approximation to the input/output transfer function of
the track and hold. Linearity is usually expressed as a
Analog Input
,,
·tl0V-
- - - - - - - - --
Analog O u t p u t - - - - -
,,
,,
~qUiS!tion
Time
(20V step to
Pedestal,"''''', Feedthrough
\'\
\
'00'%
"1 ,/ \ 1
,
:'::0.01% FSR)
OV--
~Aperture
O"elay
Droop
1
i r---------r-----
,, ,,,
\ ....'
Slew Rate
LogiC "1"_
Logic "0"-
l
Track Mode
~
Hold Mode
_ _- - - . . J
Figure 9. Summary of TJH specifications. The broken line is
the T/H's analog input. The solid line shows its analog
output. The T/H has a ±10V analog input range. The lower
trace is the digital T /H command signal. A logic "0" puts the
T/H into the track mode. A logiC "I" puts it into the hold mode.
Refer to the text for the specification definitions.
4-35
MN6000 Series Sampling AID Converters
MN6000 Series Sampling AID Converters are complete, singlepackage, high-resolution (12-16 bits), analog-to-digital (AID) converters with internal, user-transparent, high-speed track-hold (T/H)
amplifiers. This mating of Micro Networks proven AID and T/H expertise is complimented by new testing and specification techniques
that make MN6000 Series AID's ideally suited for the repetitive
sampling and digitizing of rapidly changing analog signals in
"signal-processing" types of applications.
The AID-converter sections of the products in this Series all use the
successive-approximation (SA) AID conversion technique. This approach has been proven to be the most practical for performing highspeed, high-resolution AID conversions because of the excellent
tradeoffs it offers in terms of speed, resolution, power consumption
and size. The SA conversion technique, however, is notoriously poor
in its ability to accurately convert dynamically changing (slewing)
analog input signals. In fact, SA type AID converters, by themselves,
are effectively incapable of accurately converting any1hing other
than d.c. signals. This inherent shortcoming is normally overcome
by employing external T/H amplifiers in front of the AID converters
to track the changing input signal and instantaneously "freeze" it
whenever an AID conversion is to be performed. MN6000 Series
AID's now move the T/H internal to the AID and eliminate it as a
design concern.
For each AID in the Series, the internal high-speed T/H amplifier
is completely user transparent. The T/H's input is isolated from the
outside world by either a high-impedance input buffer or a series
resistor to a virtual ground. The output of the T/H is electrically compatible with and internally connected directly to the input of the AID
converter, and the operational state of the T/H is internally controlled by the AID's status line. The need for potentially confusing T/H
timing specifications like acquisition time, aperture delay, aperture
jitter, etc. has been completely eliminated. MN6000 Series AID's
need only be clocked at the appropriate sampling rate, and all T/H
timing parameters are accommodated.
Concerning test and specification techniques, traditional, essentially static, techniques for testing and specifying the relativeaccuracy characteristics of AID converters (integral linearity, differentiallinearity, no missing codes, etc.) have proven to be inappropriate
and frequently inadequate for understanding the true dynamic
"Signal processing" capabilities of sampling AID converters. That
problem has now been overcome thanks to recently developed
digital-signal-processing (DSP) technologies that enable us to easily
evaluate the true, frequency-domain, signal-processing capabilities
of sampling AID's while operating them under dynamic-input
conditions.
Each AID in the MN6000 Series is fully tested both statically, in the
traditional manner, and dynamically with a series of 512-point Fast
Fourier Transforms (FFT's). In the resulting spectra, signal level
(rms), noise level (both peak and rms), signal-to-noise ratio (SNR,
rms-to-rms) and harmonic distortion measurements are calculated,
and each parameter is fully specified and guaranteed for each
device over each operating temperature range. And all dynamic performance specifications are guaranteed while operating the AID's
at their maximum sampling rates with analog input signal frequencies up to the Nyquist limit (input frequency equal to '/2 the
sampling rate).
All AID's in the MN6000 Series are packaged in 28 or 32-pin ceramic
dual-in-lines. Resolutions range from 12 to 16 bits, with SNR performance ranging from 68dS to 84dS. Guaranteed harmonic distortion levels run as low as -88dS. All devices operate from ± 15V and
+5V supplies. Each device type within the Series offers assorted
grades of temperature and electrical performance and optional highreliability screening to MIL-STD-883 as described in the selection
guide and individual device data sheets.
OdB
Sample Spectrum
A
-2OdB
Signal
Amplitude
Relative
to Full Scale
512-point FFT; Hanning windowing; 10 spectra averaged
D
-4OdB
Vertical axis normalized for OdS equal to full scale (r.m.s.).
For an AID with a ±10V input range, OdS equals 7.07V r.m.s.
-SOdB
Horizontal axis equals 256 frequency bins. Each bin equals
(sampling rate) +512Hz.
-SOdB
c
-100dB
= OHz
Applied
Signal
Frequency
Second
Harmonic
Frequency (Hz)
5-2
S = Peak (spurious) noise level
C
D
E
F
-12OdB
f
A = Signal amplitude (r.m.s.) relative to full scale (OdS)
Third
Harmonic
f = % Sampling Rate
= Average noise level (noise floor)
= R.m.s. noise level
= Signal to harmonics
= Signal to noise ratio (r.m.s.-to-r.m.s.)
INTERNAL T/H AMPLIFIER-The proliferating use of AID converters in DSP applications has resulted in significantly greater
demands on AID's to be able to convert dynamic signals, particularly
sinusoids. More and more frequently, T/H amplifiers are used with
AID's to enable them to accomplish this task.
MN6000 Series AID's are extremely user friendly. They have been
configured in a manner that virtually eliminates all of the problems
encountered when mating T/H's and successive approximation
AID's and driving the pair from real-world signal sources. The T/H
is truly transparent. Either a high-impedance input buffer or a series
resistor isolates it from the external signal source, and its output is
internally connected directly to the input of the AID converter. The
output-current, impedance and transient-response characteristics
of each T/H have been optimized for driving its respective SA AID.
More importantly, the critical dynamic characteristics of the T/H
(aperture delay, aperture jitter, small and large signal bandwidths,
droop rate, etc.) have been similarly optimized. However, most importantly, the critical inter-device timing relationships (T/H mode control, transient decay time, etc.) are all internally controlled by the
AID's timing and control circuitry. All that users need to provide
externally is a start convert pulse.
The value of the hold capacitor used in each internal T/H has been
selected so that T/H output droop, even over temperature, is not
significant (greater than ± 'I2LSB) during the AID's conversion time.
Similarly, the offset and pedestal voltages, as well as the gain error,
of the T/H do not contribute to the overall accuracy of the sampling
AID because each is effectively nulled out during our active laser
trimming of the AID converter.
FREQUENCY-DOMAIN TESTING-As stated earlier, all MN6000
Series AID's are specified and tested statically, in the traditional
manner (linearity, accuracy, offset error, current drains, etc.), and
dynamically in the frequency domain. In the dynamic tests, the sampling AID is operated in a manner that resembles an application as
a digital spectrum analyzer. A very low distortion signal generator
(harmonics -100dB) is used to generate a pure, full-scale, fullfrequency sine wave that the AID samples and digitizes at its
specified maximum rate. The conditions are set to approach the Nyquist sampling limit (at least 2 samples per signal cycle; sampling
frequency greater than 2 times signal frequency). A total of 512
sample-and-convert operations are performed, and the digital output data is stored in a high-speed, FIFO, buffer-memory box. The
512 data points are then accessed by a microcomputer which executes a 512-point Fast Fourier Transform (FFT) after applying a
Hanning (raised COSine) window function to the data. The resulting
spectrum shows the amplitude and frequency content of the converted signal along with any errors (noise, harmonic distortion,
spurious signals, etc.) introduced by the AID converter. Subsequently, signal-to-noise ratio (SNR) and harmonic distortion
measurements are read from the spectrum. A functional block
diagram of the test setup and a sample spectrum appear below.
MN6000
Senes
Sampling
AID
Fast
Buffer
Memory
Crystal
Clock
Frequency·Domain Testing
of AID Converters
Mini
Computer
OdB1
j
I
-2OdB
i
j
-4OdB -6OdB"
Input Frequency: 4kHz
Sampling Rate: 2O.5kHz
RMS Signal:
RMS Noise:
SIN:
2nd Ha""onic:
- O.28dB
- 85.63dB
85.35K:
ACOUISITION
-----,"I-~,
----I
IAQ
--.1
SfH gg~::~~~~DE )(
'---~P='"~11~+~5V~---/
AcaUISITION
'-------
,-------,,-------,
lAP
EMULATION MODE
ACQUISITION
ACQUISITION
CONVERSION
-....1
Pin 11
IAQ
=::
OVto -15V
-
nsec
400
1000
nsec
Figure 3. Signal Acquisition and Conversion Timing
Table 4. Read Timing Parameters
effectively initiate the conversion. Similarly, ~ must be valid for at
least 50 nsec (t HAC = 50 nsec min) while CE is high to effectively
initiate the conversion. The Status line rises to a logic"1"no later
than 200 nsec after the rising edge of CE (tosc = 200 nsec max).
Once Status is at logic "1 ", additional convert commands will be
ignored until the ongoing conversion is complete. Table 3 gives the
limits for the convert timing parameters.
TIMING - RETRIEVING DATA - When a conversion is in progress
(Status output = "1"), the ADS574's 3-state output buffer is in its
high-impedance state. After the falling edge of Status indicates the
conversion is complete, the combination of CE = "1 ", CS = "0",
and RIC = "1" is used to activate the buffer and read the digital
output data.
If the cited combination of control signals is satisfied and the 12/8
line has logic "1" imposed, all 12 output bits will become valid
5-14
SYMBOL
PARAMETER
tAQ+tc
Throughput Times:
12-Bil Conversion
8-Bit Conversion
Conversion Time:
12-Bit Conversion
8-Bit Conversion
Acquisition Time
Aperture Delay
Aperture Jitter
tc
tAO
tA
tJ
S/H CONTROL EMULATION
TYP. MAX. TYP. MAX. UNITS
22
16
18
12
25
18
22
16
18
12
4
4
20
0.3
4000
30
Table 5. Conversion Timing Over T MIN to TMAX
25
18
I'sec
I'sec
I'sec
I'sec
I'sec
nsec
nsec
In the Emulation mode, the ADS574 introduces a delay time between the Convert command and the start 01 conversion, in order
to allow the converter enough time to acquire the signal belore the
conversion. The delay causes an effective increase in aperture time
Irom 0.02!,sec to 4 } and returns low no longer than 1000 nsec after data
is valid (tHS)' In this mode, output data is available most of the time, and
becomes invalid only during a conversion.
RIC
&~us-----r------JI
~I
Figure 5. Stand Alone Mode With Negative Start Pulse.
Figure 6 details operation with ~positive start pulse. Output da!.a lines
are enabled during the time RIC is high. The falling edge 01 RIC starts
the next conversion, and the data lines return to the high-impedance
state and remain in that state until the next rising edge of RIC. In this
mode, output data is inaccessible most of the time, and becomes valid
only when RIC goes high. Table 6 gives the timing parameters for the
two modes.
DO
RIC
MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3 DB2 DBl DBO
o
0
o
I~I---
--------..
Hlgh-Z State
I~
DBl1 to DBO
Data Valid )>-------------~\
Data Valid
o
Status --i------+-----,---'
High·Z
~I ~I
High·Z State
__......:._~V Data Valid '\1>-__________________
_
-f"
?1?18
MSB27
0,
081026
0,
0,
0,
0,
0,
0,
08925
DBa 24
DB? 23
DB622
OBS 21
DB420
OB319
08218
-
DB11 to DBO
\
I
Figure 6. Stand-Alone Mode with Positive Start Pulse.
Do
OBI 17
Data
LSB 16
B"
SYMBOL
PARAMETER
MIN.
tHRL
tos
tHOR
tHRH
tOOR
Low RIC Pulse Width
25
SlS Delay after RIC
Data Valid after RIC Low
High RIC Pulse Width
Data Access Time
TYP.
MAX.
200
25
100
150
UNITS
nsec
nsec
nsec
nsec
nsec
Figure 4. Connection to 8-Bit Bus
Table 6. Stand-Alone Mode Timing over TMtN to TMAX
STAND-ALONE OPERATION - The ADS574 can be used in a
stand-alone mode in systems having dedicated input ports and not
requiring full bus-interface capability. In this mode, CE and 1218 are
tied to logic "1" (they may be hard-wired to +5V), CS and Ao are
tied to logic "0" (they may be grounded), and the conversion is controlled by RIC. A conversion is initiated whenever RIC is brought low
(assuming a conversion is not already in progress), and all 12 bits
of the 3-state output buffers are enabled whenever RIC is brought
high (assuming Status has already gone low, indicating completion
of conversion).
UNIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits lor the unipolar operating mode are
shown in Figure 7.lltheOto +10Vinput range isto be used, apply
the analog input to Pin 13. II the 0 to +20V input range is to be used, apply the analog input to Pin 14. If the gain adjustment is not
needed, replace trim potentiometer R2 with a lixed, 500 ±1%
metal-film resistor to meet all published specifications. II the offset
adjustment is not needed, connect Pin 12 (Bipolar Offset) directly to
Pin 9 (Analog Ground).
5-15
.5V o--?"-1ri 1 Voo
2
1218
3
CS
Status 28
High
Bits
4 "Start Convert
L.Jo----t--l 5
I:
25
24
RIC
ADS574
WllhoulTrlm
Middle
Bits
5011
Analog Inputso-_---i---l
.5V
lO!,F
8
RefOul
9
AnaGnd
11
Mod,
BlpOffset
13
IOVlnput
14
2OVlnpu!
1
V"
2
12i8
3
CS
4
Ao
5
RIC
Start Convert
--ulOOk!l
H
low
Bits
High
Bits
Ref Out
9
AnaGnd
10
Rei In
11
Mod,
Bits
13 lOVlnpul
Analog Inputs
"
2OVlnpu!
r
BipolaroffseterrcirreferstotheaccuracyoftheOlllllllllll to 1000
00000000 digital output transition (see section entitled "DIGITAL
OUTPUT CODING"). Ideally, this transition should occur 'I2LSB
below OV, and if the bipolar offset adjustment is not used, the transition will occur within the specified limit of its ideal value. Offset adjustment in the bipolar configuration is performed not at the zerocrossing point but at the minus full-scale point. The procedure is
to apply an analog input equal to - FS + 'l2LSB (-4.9988V for the
±SV range; -9.9976V for the ±OV range), and adjust the bipolar
offset trimpot "down" until the digital output is all zeros. Then adjust "up" until the LSB "flickers" between "0" and "I".
Bipolar gain error can be defined as the accuracy of the 1111 1111
1110to 111111111111 digital outpultransition after the bipolar offset
adjustment has been effected. Ideally, this transition should occur
1'12 LSBs below the nominal positive full-scale value of the selected
input range. This corresponds to +4.9963Vand +9.9927V for the
±SVand ± 10V ranges, respectively. Gain trimming is accomplished
by applying either of these voltages and adjusting the gain trimpot
"up" until the digital outputs are all ones, then adjusting "down"
until the LSB "flickers" between "I" and "0".
22
21
.sv
Status
1 Vorl
20
low
Bits
12 BlpOl!set
j=
24
lOO!!
R,
28
25
Middle
8
17
Status
+15Vo---J\IVtII--O -15V
Ol!set
I'
18
1.
AOSS74
WllhTnm
l"
21
20
to Ret In
12
22
BIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the bipolar operating mode are·
shown in Figure 8. If the ±SV input range is to be used, apply the
analog input to Pin 13. If the ± 10V range is to be used, apply the
analog input to Pin 14. If either bipolar offset or bipolar gain adjustments are not to be used, the trim pots should be replaced by
fixed, son ±1% metal-film resistors to meet all published
specifications.
f
10!,F
2
1218
3
OS
4
"-
5
RIC
8
Ref Out
9
AnaGnd
High
Bits
18
17
16
Start Convert
--u-
A08574
Middle
Bits
10
Refln
11
Mod,
low
50!!
Bits
12 BlpOlfset
Unipolar offset error refers to the accuracy of the 0000 0000 0000
to 0000 0000 0001 digital output transition (see section entitled
"DIGITAL OUTPUT CODING"). If the offset adjustment is not used, the actual transition will occur within specified limits of its ideal
value (+ '12 LSB). For the 10V range, 1 LSB = 2.44mV. For the 20V
range, 1 LSB = 4.88mV. To adjust the offset, apply an analog input
equal to + 'I2LSB and, with the ADSS74 continuously converting,
adjust the offset potentiometer "down" until the digital output is all
ones, and then adjust "up" until the LSB "flickers" between "0"
and "I".
Unipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 1111 1111 1111 digital output transition after the unipolar offset adjustment has been effected. Ideally, this transition should occur 1'12LSBs below the nominal full-scale voltage for the selected
input range. This corresponds to +9.9963V and + 19.9927V, respectively, for the 10V and 20V unipolar input ranges. Gain trimming is
accomplished by applying either of these voltages and adjusting
the gain potentiometer "up" until the digital outputs are all ones,
and then adjusting "down" until the LSB "flickers" between "0"
and "I":'
In some applications, it is desirable to have the LSB equal exactly
2.SmV (10.24V input range) or SmV (20.48V input range). To implement these ranges, replace the 100 gain trimpot by a son fixed
resistor. Then insert a 2.7kn trimpot in series with Pin 13 for a 10.24V
range; Pin 14 for a 20.48V range. Offset trimming then proceeds as
described earlier, and the gain trim is effected with the new trimpot.
S-16
Analog Inputs
,
.5V
10l'F
20V Input
OS
4
A,
AOS574
High
Blls
Start Convert
--u-
WlthTnm
Middle
Bits
RefOu!
9
AnaGnd
10
Ref In
11
Mod'
"
BlpOtfset
13
IOV Input
14
20V Input
Analog Inputs
Figure 8. Bipolar Connections
r
18
17
28
r
26
25
24
5 RIC
,
21
Sialus
VOD
2 12/8
3
22
16
13 lOV Input
"
25
20
50U
Figure 7. Unipolar Connections
I:
r
24
WllhoutTnm
10011
28
f
22
21
20
Low
Blls
r
18
17
16
DIGITAL OUTPUT CODING
ANALOG INPUT VOLTAGE (Volts)
Oto +2OV
+5V
Oto +10V
±10V
DIGITAL OUTPUT
MSB
LSB
+10.0000
+9.9963
+20.0000
+19.9927
+5.0000
+4.9963
+10.0000
+9.9927
1111 1111 1111
1111 1111 1110'
+5.0012
+4.9988
+4.9963
+10.0024
+9.9976
+9.9927
+0.0012
-0.0012
-0.0037
+0.0024
-0.0024
-0.0073
tJl/J0rJ~I/JI/JI/JI/J'
0111 1111 1110'
+0.0012
0.0000
+0.0024
0.0000
-4.9988
-5.0000
-9.9976
-10.0000
0000 0000 OOO~ •
000000000000
1000 0000 OOO~'
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is straight binary.
2. For bipolar input ranges, output coding is offset binary.
3. For 0 to + IOV or ±5V input ranges, lLSB for 12 bits =2.44m\l. lLSB
for 11 bits =4.BBm\l.
4. For 0 to +20Vor ± IOV input ranges, lLSB for 12 bits =4.8Bm\l.
lLSB for 11 bits =9.77mV.
'Voltages given are the theoretical values for the transition indicated. Ideally,
with the converter continuously converting, the output bits indicated as III will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
EXAMPLE: For an ADS574 operating on its ± IOV input range, the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage of -9.9976 volts. Subsequently, any input voltage
more negative than -9.9976 volts will give a digital output of all "D's". The transition from digital output 1000 0000 0000 to 0111 1111 1111 will ideally occur
at an input of -0.0024 volts, and the 1111 11111111 to 11111111 1110 transition
should occur at +9.9927 volts. An input more positive than +9.9927 volts will
give all "l's".
I
ADS574 BLOCK DIAGRAM
+5V Supply (1)
Data Mode Select 12/8 (2)
Chip Select CS (3)
Byte Address Ao (4)
ReadlConvert RIC (5)
~
~
0---
oJ-,:
Chip Enable CE (6)
TIMING
AND
CONTROL
LOGIC
rr=t
I-
SUCCESSIVEAPPROXIMATION REGISTER
J-
{) (28) Status Output
r3
I--
Y
CLOCK
S
T
A
T
E
I
B
+2.5V Ref Out (8)
o----f
Analog Ground (9)
0----.
0
VEE(Mode Control) (11) 0---.
Bipolar Offset (12) ,....
2.5V
REF
I
20V Input (14)
~
I
I
CAPACITOR-ARRAY
12-BIT DIA CONVERTER
J
-
(26) DBIO (Bit 2)
~ (25) DB9 (Bit 3)
..Q (24) DBB (Bit 4)
r-~ (23) DB7 (Bit 5)
----;:<
~
~
F r-~
F
E
R
+-0
(22) DB6 (Bit 6)
(21) DB5 (Bit 7)
(20) DB4 (Bit 8)
(19)
(18)
(17)
(16)
DB3 (Bit 9)
DB2 (Bit 10)
OBI (Bit 11)
DBO (LSB)
(15) Digital Ground
.....
'-"
wV",
0
,....
.. A
'-"
r-. (27) DBll (MSB)
U
+2.5V Ref In (10)
10V Input (13)
r=
....
COMPARATOR
5-17
TYPICAL PERFORMANCE
(TA =25"C, Supplies = +5V, ±10V Bipolar Input, fiN =40kHz, unless otherwise indie!lted)
SIGNAl.J(NOISE + DISTORTION) vs
INPUT FREQUENCY AND AMBIENT TEMPERATURE
FREQUENCY SPECTRUM (±10V. 2kHz Inpul)
0
S/(N + D) _73.1dB
-20 I - t - - - - - r - - - - - i - THO _ -94.5dB
SNR = 73.1dB
c
.9
--40
iD
E
40516·p'OI~n
"'c'"
''""
~
FFT
-60
~
--80
5l
z
C>
::;
70
'0
~
.9'
-100
en
-120
0
5
10
15
10
0.1
20
FREQUENCY SPECTRUM (±10V. 19kHz Input)
FREQUENCY SPECTRUM (±IV. 19kHz Input)
0
-20
0
+ D) - 68.4dB
/-___-+___--1_ SI(N
THO =-75.9dB
-20
1-----+-----+-
SNR = 69.3dB
--40
iD
E
40916·POI~IT
'"
.".Ec:
-60
'"
--80
S/(N + D) - 53.3dB
THO = -74.5dB
SNR = 53.3dB
-40
iD
E
FFT
40516·P'OI~JT
"'c'"
''""
::;
C>
FFT
--80
C>
::;
--80
-100
-100
-120
-120
0
5
10
15
5
0
20
10
Frequency (kHz)
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
".5
~
:r:
I-
z
en
"
90
.,;
C>
c:
0
.,
.
~
~
0-
en
r--r--.
;;;
::>
"§
r-..
'ii)
u.
0
............
40
'"
a:
~
0::> 20
en
t--..
70
i"
c:
~~
'E
,..'"
60
~
a:
~
a:
'"0 BO
c:
0
20
iD 80
0
0::
15
Frequency (kHz)
SPURIOUS FREE DYNAMIC RANGE. SNR AND THO
vs INPUT FREQUENCY
iD
E 100
~
c..
60
0.1
10
Input Frequency (kHz)
5·18
100
Inpul Frequency (kHz)
Frequency (kHz)
100
10
10
100
lk
10k
lOOk
Supply Ripple Frequency (Hz)
1M
10M
PACKAGE OUTLINES
DIM
A
B
D
E
F
G
H
14
J
K
M
N
PACKAGE E. PLASTIC SINGLE DIP
P
1------- 0 -------
INCHES
MIN MAX
.169
.200
AI"I .015
.070
.015
.020
B
B,
.015
.055
.012
C
.006
0 11) 1.380 1.455
E
.600
.625
ElI'1 .485
.550
e,
.100 BASIC
.600 BASIC
eA
DIM
All,
-,
o
E,
o
INCHES
MIN
MAX
1255 1.355
270
.290
.170
.1SO
.010
.080
.100 BASIC
.045
.055
.016
.020
NlA
.125
.300 BASIC
O· I 15·
.006
.015
.020
.040
MILLIMETERS
MIN MAX
429
5.06
0.38
1.78
0.38
0.51
0.38
1.40
0.20
0.30
35.05
DIM
L
L2
a
S"
MILLIMETERS
MIN
MAX
31.88 34.42
7.37
6.86
3.81
4.32
0.25
2.03
2.54 BASIC
1.14
1.40
0.41
0.51
3.18
NlA
7.62 BASIC
O· I 15·
0.20
0.38
0.51
1.02
INCHES
MIN
MAX
.100
.200
.000
.030
O·
15·
.040
.080
MILLIMETERS
MIN
MAX
5.06
2.54
0.00
0.76
O·
15'
1.02
2.03
36.96
15.24 15.88
12.32 13.97
2.54 BASIC
15.24 BASIC
PACKAGE P. PLASTIC DOUBLE DIP
_II_B
1-:-8-------
A
--------,~~I
DIM
A
B
C
D
"'Index Mark
F
G
J
K
14
PACKAGE F. CERAMIC HERMETIC SINGLE DIP
L
~~
1
I
I
!
__
N
INCHES
MIN
MAX
1.388 1.412
.300
.320
.160
.016
.020
.OSC BASIC
.095 .105
.009
.012
.125
.180
.310
290
.040
.060
MILLIMETERS
MIN
MAX
35.26 35.86
7.62
8.13
4.06
0.41
0.51
1.27 BASIC
2.41
2.67
0.23
0.30
3.18
4.57
7.37
7.87
1.02
1.52
-
ute
11K
5-19
PACKAGE H. CERAMIC HERMETIC DOUBLE DIP
1--1'- - - - -
A
0,
"I
15
28
D
14
DIM
A
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
1.386 1.414
.115
.175
.015
.021
.035
.060
.100 BASIC
.064
.036
.012
.008
.120
.240
.600 BASIC
-
.025
10'
.060
MILLIMETERS
MIN
MAX
35.20 35.92
4.45
2.92
0.53
0.38
0.89
1.52
2.54 BASIC
1.63
0.91
020 j 0.30
3.05
6.10
15.24 BASIC
_ I 10'
1.52
0.64
PACKAGE U. PLASTIC SOIC
DIM
A
B
C
D
G
H
J
L
M
N
~
5-20
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
INCHES
MIN
MAX
.700
.716
286
.302
.093
.109
.016 BASIC
.OSOBASIC
.022 .038
.012
.008
.398
.414
5'lYP
.000 .012
MILLlMffiRS
MIN
MAX
17.78 18.19
7.26
7.67
2.36
2.77
0.41 BASIC
127 BASIC
0.56
0.97
0.20
0.30
10.11 10.52
5'lYP
0.00
0.30
l1JJ
_
ADS774
8.5",sec, 12-Bit
SAMPLING AJD CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Low Cost
• Pin-Compatible
with MN574/674/774
• Eliminates External S/H
in Most Applications
• Complete, 8.5",sec,
12-Bit A/D Converter
with Internal
Clock
Reference
Control Logic
• Full 8- or 16-Bit ",p Interface:
3-State Output Buffer
Chip Select, Address Decode
Read/Write Control
• No-Missing-Codes Guaranteed
Over Temperature
• Single +5V Supply Operation
• Low Power: 120mW Max
• Package Options
0.3" Plastic DIP
0.3" Hermetic DIP
0.6" Plastic DIP
0.6" Hermetic DIP
SOIC
The ADS774 is a complete, low-cost, 12-bit successive-approximation
A/D converter with an internal sample/hold function. In most existing
applications, it is drop-in compatible with non-sampling 774 types, and
eliminates the need for an external S/H amplifier. The ADS774 uses an
innovative, capacitor-array internal D/A converter, based on CMOS
technology. The use of a CMOS architecture results in much lower
power consumption and the ability to operate from a single +5V supply
(the formerly required -12V or -15V supply is optional, depending on the
application).
The ADS774 is complete with internal clock, reference, control logic,
and 3-state output buffer. The interface logic provides for easy handshaking with most popular 8- and 16-bit microprocessors. The
ADS774's 3-state output buffer connects directly to the ",P's data bus,
and is readable as either one 12-bit word or two 8-bit bytes. Chip
select, chip enable, address decode (for short cycling), and read/write
(read/convert) control inputs enable the ADS774 to connect directly to a
system address bus and control lines, and to operate totally under processor control.
Internal scaling resistors allow a pin-selectable choice of four
input ranges: OV to +10V, OV to +20V, ±5V, and ±10V. The maximum
throughput time (including both acquisition and conversion) for 12-bit
conversions is 8.5",sec over the full operating-temperature range. The
ADS774 is available for operation over the commercial (ODC to +70DC)
and military (-55 DC to + 125 DC) temperature ranges. Package options
include 28-pin single (0.300) or double (0.600) plastic or hermetic
ceramic DIPs, and 28-pin plastic SOIC. For availability of devices
screened to MIL-STD-883, consult factory.
Linearity
Model
Number
ADS774JE
ADS774KE
ADS774JP
ADS774KP
ADS774JU
ADS774KU
ADS774JH
ADS774KH
ADS774SF
ADS774TF
ADS774SH
ADS774TH
OJ]
_
Package
0.3"
0.3"
0.6"
0.6"
0.6"
0.6"
0.3"
0.3"
0.6"
0.6"
Plaslic DIP
Plaslic DIP
Plaslic DIP
Plaslic DIP
SOIC
SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Temperature
Range
O°C 10 +70°C
O°Clo +70 oC
O°C 10 +70°C
O°Clo +70 oC
O°Clo +70°C
OOClo +70°C
O°C 10 +70°C
O°Clo +70°C
-55°C 10 + 125°C
-55°C 10 +125°C
-55°C 10 + 125°C
-55°C 10 + 125°C
Error Max
(Tmin to T max)
±1LSB
±V2LSB
±1LSB
± 'I2LSB
±1LSB
±'I2LSB
±1LSB
± 'I2LSB
±1LSB
±3/4 LSB
±1LSB
±3!4LSB
May 1992
MICRO NETWORKS
Copyright©'992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (SOB) B52-5400
5-21
ADS774 12-Bit SAMPLING AID CONVERTER
ORDERING INFORMATION
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range:
J, KGrades
S, TGrades
Specified Temperature Range:
J, KGrades
S, T Grades
Storage Temperature Range
VEE to Digital Ground
Voo to Digital Ground
Analog Ground to Digital Ground
Control Inputs (CE, CS, ~, 12/8, RIC)
to Digital Ground
Analog Inputs
(Ref In, Bipolar Offset, lOVIN)
to Analog Ground
20VIN to Analog Ground
Ref Out
Junction Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance 8JA: Ceramic
Plastic
II
PART NUMBER - - - - - - - - - - - ADSn4 T H
-40°C to +85°C
-55°Cto +125°C
O°C to +70°C
-55°C to +125°C
-65°Cto +150OC
to -l6.5V
Oto +7V
Select suffix J, K, S or T for
desired performance and
specific temperature range.
.
Select suffix E, F, H, P or U
for desired package o p t i o n . - - - - - - - - - - - - '
o
±1V
-0.5V to Voo to +O.5V
±l6.5V
±24V
Indefinite Short to
Ground, Momentary
Short to Voo
+165°C
+300°C
5O"CfW
100°C!W
DESIGN SPECIFICATIONS ALL UNITS (TA=TMIN to T MAx , Voo= +5V, VEE = -15V to +5V, fs=117kHz, fIN=lDkHz)
(unless otherwise indicated)
ANALOG INPUTS
MIN.
Input Voltage Ranges: Unipolar
Bipolar
Input Impedance: 0 to +1011, ±5V
to +2OV, +10V
o
8.5
35
TYP.
MAX.
UNITS
Oto +10,0 to +20
+5, +10
Volts
Volts
12
50
kll
kll
DIGITAL INPUTS CE, CS, RIC, ~, 12/8
Logic Levels: Logic "1"
Logic "0"
Loading: Logic Current
Input CapaCitance
+2.0
-0.5
-5
0.1
5
+5.5
+0.8
+5
Volts
Volts
"A
pF
DIGITAL OUTPUTS DBD to DBll, Status
Output Coding: Unipolar Ranges
(Note 1)
Bipolar Ranges
Logic Levels: Logic "1" (ISOURCE = 500"A)
Logic "0" (ISINK = 1.6mA)
Leakage (DBO to DBll) in High-Z State
Output Capacitance
Straight Binary
Offset Binary
+2.4
-5
0.1
5
+0.4
+5
Volts
Volts
"A
pF
INTERNAL REFERENCE
Reference Output Voltage (Pin 8)
Available Output Source Current
+2.4
0.5
+2.5
+2.6
Volts
mA
VDD
+5.5
POWER SUPPLY REQUIREMENTS
Power Supply Range: VEE Supply (Note 2)
Power Supply Range: VDD Supply
Current Drains: lEE (VEE = -15V)
-16.5
+4.5
100
Power Dissipation
VEE=OVto +5V
-1
+15
+24
Volts
Volts
mA
mA
75
120
mW
DYNAMIC CHARACTERISTICS
Sampling Rate (Max) TMIN to T MAX
25°C
Aperture Delay tAP
With VEE =+5V
With VEE =OV to -15V
Aperture Uncertainty (Jitter)
With VEE =+5V
WithVEE=OVto -15V
Settling Time to 0.01% for
Full·Scale Input Step
117
125
kHz
kHz
20
nsec
1.6
~sec
300
10
1.4
psec rms
nsec rms
~sec
CONVERSION TIME (Including Acquisition Time)
tAO + tc at 25°C:
B-Bit Cycle
12-Bit Cycle
12-Bit Cycle, T MIN to T MAX
5-22
5.5
7.5
8
5.9
8
8.5
~sec
~sec
~sec
PERFORMANCE SPECIFICATIONS (TA =T MIN to TMAX' VOO = +5V, Vee = -15V to +5V, fs =117kHz, fiN =10kHz unless otherwise indicated)
ADS774J, S
GRADE
MIN.
TYP.
RESOWTION
ADS774K, T
MAX.
._UNITS
12
12
Bits
±1
±2
±10
±0.25
±1J2
±2
±4
±0.25
LSB
LSB
LSB
%FSR
LSB
±1
±1
±1f2
±314
LSB
LSB
±0,47
±0.75
±0.22
±0.5
±0.37
±0.5
±0.12
±0.25
%FSR
%FSR
%FSR
%FSR
Bits
MAX.
MIN.
TYP.
TRANSFER CHARACTERISTICS
DC ACCURACY
At 25°C:
Linearity Error
Unipolar Offset Error (Notes 3. 4)
Bipolar Offset Error (Notes 3, 5)
Full-Scale Calibration Error (Notes 3, 6, 7)
Inherent Quantization Uncertainty
TMIN to TMAX:
Linearity Error: J, K, Grades
S. T Grades
Full-Scale Calibration Error:
Untrimmed: J, K Grades
S, TGrades
Trimmed to Zero at 25°C: J, K Grades
S, T Grades
Resolution for No Missing Codes
+112
+'12
12
12
TEMPERATURE COEFFICIENTS (Note 8)
Unipolar Offset
Max. Change Over Temperature:
Bipolar Offset
Max. Change Over Temperature:
J, K Grades
S, T Grades
Full-Scale Calibration
Max Change Over Temperature:
J, K Grades
S, T Grades
±5
+2
±2.5
+1
±1O
±2
+4
±5
±1
+2
±45
±9
+20
±25
±5
+10
-ppm/oC
LSB
ppm/oC
LSB
LSB
ppm/oC
LSB
LSB
AC ACCURACY (Note 9)
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-ta-Noise Ratio
Signal-ta-(Noise+Distortion) Ratio (SINAD)
Intermodulation Distortion
(f1N1 =20kHz; flN2 =23kHz)
73
69
68
78
-77
72
71
-75
76
78
-77
71
70
72
-72
-75
71
-75
dB
dB
dB
dB
dB
POWER SUPPLY SENSITIVITY
Change in Full-Scale Calibration (Note 10)
+4.75V < Voo < +5.25V
Max. Change: J, K Grades
S, TGrades
SPECIFICATION NOTES:
1. See table of transition voltages in section labeled Digital Output Coding.
2. The use of VEE is optional. This input sets the mode for the internal sample/hold circuit. When VEE =-15V, IEE =-1mA typ; when VEE=OV.
IEE=±5~ typ; when VEE=+5V, IEE=+167,A typo
3. Adjustable to zero with external potentiometer.
4. Unipolar offset error is defined as the difference between the ideal and
the actual input voltage at which the digital output just changes from 0000
0000 0000 to 0000 0000 0001 when the ADS774 is operating with a unipolar
range. The ideal value for this transition is + 'I2LSB. See section labeled
Digital Output Coding.
5. Bipolar offset error is defined as the difference between the ideal and the
actual input voltage at which the digital output just changes from 01111111
1111 to 1000 0000 0000 when the ADS774 is operating with a bipolar range.
The ideal value for this transition is -'I2LSB. See section labeled Digital
Output Coding.
6. Listed specs assume a fixed 500 resistor between Ref Out (Pin 8) and Ref
In (Pin 10) and a fixed 50n resistor between Ref Out (Pin 8) and Bipolar
Offset (Pin 12) in bipolar configurations; or Bipolar Offset grounded in
unipolar configurations. Full-scale calibration error is defined as the
±'12
±'12
±1
±1
LSB
LSB
difference between the ideal and the actual input voltage at which the digital
output just changes from 1111 1111 1110 to 1111 1111 1111. The ideal value
for this transition is 1'12 LSBs below the nominal full-scale voltage. See section labeled Digital Output Coding.
7. FSR is a full-scale range. For the ± 10V input range, FSR is 20\1, For the
o to + 10V input range, FSR is 10V
8. Temperature coefficient specifications assume the use of the internal
reference.
9. Specifications assume VEE = +5V, which starts a conversion immediately upon a Convert command. If VEE =OV to -15V, the ADS774 emulates
standard ADC774 operation. In this mode, the internal sample/hold circuit
acquires the input signal after receiving the Convert command, and does
not assume that the input level had been stable before the arrival of the
Convert command.
10. Worst-case change in accuracy, compared with accuracy with a +5V
supply.
Specifications are subject to change without notice as Micro Networks
reserves the right to make improvements and changes in its products.
5-23
PIN DESIGNATIONS
Pin 1
28
1 +5V Supply (+V DD)
2
Data Mode Select 12/8
3 Chip Select
14
. 15
CS
28 Status Output
Z7 DBll (MSB)
26 DB10 (Bit 2)
4 Byte Address Ao
25 DB9 (Bit 3)
4 Read/Convert R/C
24 DB8 (Bit 4)
6 Chip Enable CE
23 DB7 (Bit 5)
7 No Connect'
22 DB6 (Bit 6)
8 +2.5V Ref Out
21 DB5 (Bit 7)
9 Analog Ground
20 DB4 (Bit 8)
10 +2.5V Ref In
19 DB3 (Bit 9)
11 Mode Control VEE
18 DB2 (Bit 10)
12 Bipolar Offset
17 DBI (Bit 11)
13 10V Input
16 DBa (LSB)
14 20V Input
15 Digital Ground
'No Internal Connection
DESCRIPTION OF OPERATION
APPLICATIONS INFORMATION
The ADS774 is a complete 12-bit AID converter. It uses the
successive-approximation conversion technique and incorporates
all required function blocks - capacitor-array D/A converter, comparator, clock, reference, and control logic. The CMOS-based
capacitor-array architecture provides an inherent samplelhold function; the ADS774 is thus a sampling equivalent of the industrystandard 774 AID converter. The device mates directly to most
popular 8-, 16-, and 32-bit microprocessors and contains all the
necessary address-decoding logic, control logic, and 3-state output buffering to operate completely under processor control. In most
cases, the ADS774 will require only a power supply, a bypass
capacitor, and two resistors to provide the complete AID conversion
function. The completeness of the device makes it most convenient
to think of the ADS774 as a function block with specific input/output transfer characteristics; it is thus quite unnecessary to be concerned with its inner workings.
LAYOUT CONSIDERATIONS AND GROUNDING - Proper attention to layout and decoupling is necessary to obtain specified performance from the ADS774. It is very important that the ADS774's
power supply be filtered, well-regulated, and free from highfrequency noise. The use of a noisy supply may cause the generation of unstable output codes. It is advisable to bypass the +5V
supply with a IOI'F tantalum capacitor, located as close as possible to the converter. It is recommended to pay special attention to
the avoidance of noise and spikes if a switching power supply is
employed.
Operating the ADS774 under microprocessor control (note that it
also functions as a stand-alone AID) entails, in most applications,
a series of read and write instructions. Initiating a conversion requires sending a command from the processor to the AID, and also
involves a write operation. Once the proper signals have been
received and a conversion has begun, the ADS774 cannot be stopped or restarted, and digital output data is not available until the conversion has been completed. Immediately following the initiation of
a conversion cycle, the ADS774's Status Output (also called Busy
Line or End-of-Conversion (EOC) Line) rises to logic "1 ", indicating
that a conversion is in progress. At the end of a conversion, the internal control logic will cause the Status Output to drop to "0", and
will enable internal circuitry to allow reading output data by external command. By monitoring the state of the Status Output or by
waiting an appropriate period of time, the microprocessor will know
when the conversion is complete and that output data is valid and
ready to be read.
If the ADS774 interfaces with 12-bit or wider microprocessors, it is
possible to 3-state-enable all 12 output bits simultaneously, allowing data collection with a single read operation. If the ADS774
operates with an 8-bit processor, output data can be formatted to
read in two 8-bit bytes. The first byte will contain the 8 mostsignificant bits (MSBs). The second byte will contain the remaining 4 least-significant bits (LSBs), in a left-justified format, with 4 trailing zeroes.
5-24
To avoid noise pickup, it is important to minimize coupling between
analog inputs and digital signals. Pins 10 (Reference In), 12 (Bipolar
Offset), and 13 and 14 (Analog Inputs) are particularly susceptible
to noise. The circuit layout should be configured to locate the
ADS774 and associated analog-input circuitry as far as possible
from high-speed digital circuitry. The use of wire-wrap circuit construction is not recommended; careful printed-circuit construction
is preferable. If external offset and gain-adjust potentiometers are
used, the trimmers should be located as close to the ADS774 as
possible. If no trims are required and fixed resistors are used, they
should be situated as close to the converter as possible.
Analog (Pin 9) and Digital (Pin 15) Ground pins are not internally
connected. It is advisable to tie them together as close to the converter as possible, preferably via a large analog ground plane
beneath the package. If it is necessary to run these commons
separately, it is recommended to connect a 10nF ceramic bypass
capacitor between Pins 9 and 15, as close to the converter as possible. Pin 9 (Analog Ground) is the common reference point for the
ADS774's internal reference. It should be connected as close as
possible to the analog-input signal reference point.
CONTROL FUNCTIONS - Operating the ADS774 under
microprocessor control is most easily understood by examining the
various control-line functions in a truth table. Table 1 is a summary
of the ADS774's control-line functions. Table 2 is the truth table that
applies to these functions.
Unless Chip Enable (CE, Pin 6, logic "1" = active) and Chip Select
(CS, Pin 3, logic "0" = active) are both asserted, various combinations of logic signals applied to other control lines (RIC, 1218, and
&l will have no effect on the ADS774's oper~tion. When CE and
CS are both asserted, the signal applied to RIC (Read/Convert, Pin
5) deter!!lines whether a data Read (RIC = "1") or a Convert operation (RIC = "0") is initiated.
-,--_._-----
Pin
If the 12/8 line is at logic "0", output data will be accessible as two
8-bit bytes as detailed in the section entitled "TIMING - READING
OUTPUT DATA". In this situation, Ao = "0" will result in accessing
the 8 MSBs. In this mode, only the 8 upper bits or the 4 lower bits
can be accessed at one time, as addressed by Ao. In these applications, the 4 LSBs (Pins 16 to 19) should be hard- wired to the 4 MSBs
(Pins 24 to 27). Thus, during a read operation, when Ao is low, the
upper 8 bits are enabled and they present data on Pins 20 through
27. See the section entitled "HARD-WIRING TO 8-BIT DATA
BUSES".
I
Designati.~O_n+D=-e:,-fc.:in-,::it,,-io,--n,-,---_+-:-F,--U,,-nc,--t,-io,-~ _ _._______.
CE (Pin 6)
Chip Enable
(active high)
Must be high ("1") to either initiate
a conversion or read output data.
0-1 edge may be used to initiate a
conversion.
cs (Pin 3)
Must be low ("0") to either initiate a
conversion or read output data.
1-0 edge may be used to initiate a
Chip Select
(active low)
conversion.
RIC (Pin 5)
ReadlConvert
("1" =read)
("0" = convert)
Must be low ("0") to initiate
either 8 or 12-bit conversions.
1-0 edge may be used to initiate a
conversion. Must be high ("1") to
read output data. 0-1 edge may be
used to initiate a read operation.
Ao (Pin 4)
Byte Address
Short Cycle
In the start-convert mode.
Ao selects 8-bit (Ao="I") or 12-bit
(Ao= "0") conversion mode. When
reading output data in 2 8-bit bytes.
Ao="O" accesses 8 MSBs (high
byte) and Ao="I" accesses
4 LSBs and trailing "O's" (low byte).
12/8 (Pin 2)
Data Mode
Select
("1"=12 bits)
("0" =8 bits)
When reading output data,
12/8="1" enables all 12 output bits
simultaneously. 12/8="0" will
enable the MSbs or LSBs as
determined by the Ao line.
TIMING - INITIATING CONVERSIONS - It is the combination
of CE = "1",
= "0", RIC = "0", Ao = "I" (initiate 8-bit conversion) or Ao = "0" (initiate 12-bit conversion) that initiates a convert
operation. As stated earlier, the actual conversion can be initiated
by the rising edge of CE, the falling edge of CS, or the falling edge
of RIC. Whichever occurs last will control the conversion; however,
all three may occur simultaneously. The nominal delay time from
either input transition to the beginning of the conversion (rising edge
of Status) is the same for all three inputs (60 nsec typ). If it is desirable
that a particular one of these three inputs be responsible for initiating
the conversion, the other two should be unchanging for a minimum
of 50 nsec prior to the transition of the chosen input.
cs
Because the ADS774's control logic latches the Ao signal upon the
initiation of a conversion, the Ao line should be stable immediately
prior to whichever of the cited transitions is used to initiate the conversion. The RIC transition is normally used to initiate conversions
in stand-alone operation; however, it is not recommended to use this
line to initiate conversions in I'P applications. If RIC is high just prior
to a conversion, there will be a momentary enabling of output data
as if a Read operation were occurring, and the result could be
system_bus contention. In most iY?plications, Ao should be stable
and RIC low before either CE or CS is used to initiate a conversion.
'----- -'--------'------"---_._--
Table 1_ ADS774 Control Line Functions
-
CONTROL INPUTS
.
..:--,--
ADs774 OPERATION
CE
CS
RIC
12/8
Ao
0
X
1
1
0-1
0-1
1
1
1
X
1
0
0
0
0
1-0
1-0
0
X
X
1-0
1-0
0
0
0
0
1
X
X
X
X
X
X
X
X
1
X
X
0
1
0
1
0
1
X
1
1
0
0
1
1
0
0
0
1
--
I
--
No Operation
No Operation
Initiates 12-Bit Conversion
Initiates 8-Bit Conversion
Initiates 12-Bit Conversion
Initiates 8-Bit Conversion
Initiates 12-Bit Conversion
Initiates 8-Bit conversion
Enables 12-Bit Parallel
Output
Enables 8 MSBs
Enables 4 LSBs and
4 Trailing Zeros
CE
RIC
Ao
STATUS----j:;::::::::;~I
i
Table 2. Control Line Truth Table
In the initiation of a conversion, the signal applied to Ao (Byte Address/Short Cycle, Pin 4) determines whether a 12-bit conversion
(Ao = "0") or an 8-bit conversion (Ao = "I") is initiated. It is the combination of CE = "I", CS = "0", RIC = "0", and Ao = "I" or "0"
that initiates a convert operation. The actual conversion can be initiated by t~ rising edge of CE, the falling edge of CS, or the falling
edge of RIC, as shown in Table 2 and the section entitled "TIMING
-INITIATING CONVERSIONS". In the initiation of a conversion,
the 12/8 line has "don't care" status.
When reading digital output data from the ADS?,74, it is necessary
to assert CE and CS. The signals applied to 12/8 and Ao will determine the format olthe output data. Logic "I" applied to the RIC line
will initiate actual output data access. If the 12/8 line is at logic "I",
all 12 output data bits will be accessed simultaneously when the RIC
line's state changes from "0" to "I".
..- - - -
~
tX-"I-
High-Z State
DBll to DBO
• tx comprises tAO + tc in Emulation Mode;
tc only in S/H Control Mode.
Figure 1_ Convert Timing
~ure 1 shows timin9.!or a typical application. In this application,
CS is brought low, RIC is brought low, And Ao is set to its chosen
value prior to CE's "O"-to-"I" transition. The sequence can be accomplished in a number of ways, incl!:!.ding connecting CS and Ao
to address bus lines, connecting RIC to a readlwrite line (or its
equivalent), and generating "O"-to-"I" transition on CE using the
system clock. In this example, CS should be at log!,£ "0" 50 nsec
prior to the CE transition (tssc = 50 nsec min), RIC should be at
logic "0" 50 nsec prior to the CE transition (tSRC = 50 nsec min),
and Ao should be stable nsec prior to the CE transition (tSAC =
nsec min). The minimum pulse width for CE = "I" is 50 nsec
(t HEC = 50 nsec min) and both CS and RIC must be valid for at least
a
a
5-25
SYMBOL
PARAMETER
MIN.
tose
tHEC
tsss
tHse
tSRC
tHRC
tSAC
tHAC
STS Delay from CE
CE Pulse Width
iSS to CE Setup
CS Low During CE High
RIC to CE Setup
RIC Low During CE High
Ao to CE Setup
Ao Valid During CE High
50
50
50
50
50
0
50
TYP.
60
30
20
20
0
20
MAX. UNITS
200
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
20
Table 3. Convert Timing Parameters
If the cited combination of control signals is satisfied and the 12/8
line has logic "1" imposed, all 12 output bits will become valid
simultaneously. lithe 121aline has logic "0" imposed, output data
will be formatted for an 8-bit data bus.
Bgure 2 shows timing for a typical application. Il!..this application,
CS is brought low, Ao is set to its final state, and RIC is brought high,
all before the rising edge of CEo CS and Ao shollid be valid 50 nsec
prior to CE (tSSR and tSAR = 50 nsec min). RIC can become valid
at the same time as CE (tSRR = 0 nsec min).
Ao may be toggled at any time without damage to the converter.
Break-before-make action is guaranteed between the two data bytes,
which ensures that the outputs strapped together in 8-bit bus applications will never be enabled at the same time.
Access time is measured from the point at which CE and RIC are
both high (assuming CS is already low). Data actually becomes valid
typically 150 nsec before the falling edge of Status, as indicated by
tHS ' In most applications, the 12/8 input will be hard-wired high or
low; although it is fullyTTLlCMOS compatible and may be actively
driven. Table 4 gives the limits for the read timing parameters.
CE
SIH CONTROL MODE AND NON-SAMPLING 574 EMULATION
MODE - Figure 3 and Table 5 show the basic differences between
the two operating modes. In both modes, the acquisition time is 4
I-'sec typo In the Control mode, during the 41-'sec acquisition time,
the input signal may not slew faster than the inherent slew rate of
the ADS774. After the Convert command arrives, any changes in
the input signal level have no effect on the conversion, as the input
signal is already sampled and the conversion process begins
immediately.
RIC
Ao
STATUS~~+-----------------"
In the Control mode, a Convert command can provide some useful
peripheral functions - for example, control an input MUX or a
programmable-gain amplifier. In these applications, the input signal
has time to settle before the subsequent acquisition occurs after
the conversion. The internalsamplelhold function keeps aperture
jitter to a minimum; therefore, it is possible to digitize high input frequencies without the need for an external samplelhold amplifier.
DBII to.~D~B~O~___~H~i9~h-:Z~S~ta~te~_.t::o;;.-v.;kj::::r~
Figure 2. Read Timing
AIC
SYMBOL
PARAMETER
too
tHO
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
Access Time from CE
Data Valid after CE Low
Output Float Delay
CS to CE Setup
RIC to CE Setup
Ao to CE Setup
iSS Valid after CE Low
RIC High after CE Low
Ao Valid after CE Low
STS Delay after Delay Valid
MIN.
25
50
0
50
0
0
50
75
TYP.
75
35
100
0
MAX. UNITS
150
150
nsec
375
nsec
nsec
nsec
nsec
nsec
nsec
nsec
25
150
nsec
nsec
I
---------~~---------------------,
----+,
I
~I
------~
ACQUISITION
Ic
+-t AP
r---------~
SlH CONTROL MODE
ACQUISITION
CONVERSION
EMULATION MODE
ACQUISITION
ACQUISITION
CONVERSION
Pin 11 = OV to -15V
Figure 3. Signal Acquisition and Conversion Timing
Table 4. Read Timing Parameters
50 nsec while CE = "1" (t HSC and t HRC = 50 nsec min) to effectively initiate the conversion. Similarly, ~ must be valid for at least
50 nsec (t HAC = 50 nsec min) while CE is high to effectively initiate
the conversion. The Status line rises to a logic "1" no later than 200
nsec after the rising edge of CE (tosc = 200 nsec max). Once
Status is at logic' '1", additional convert commands will be ignored
until the ongoing conversion is complete. Table 3 gives the limits
for the convert timing parameters.
TIMING - RETRIEVING DATA - When a conversion is in progress
(Status output ="1"), the ADS774's 3-state output buffer is in its highimpedance state. After the falling edge of Status indicates the conversion is complete, the combination of CE = "1 ", CS = "0", and
RIC = "1" is used to activate the buffer and read the digital output
data.
5-26
SYMBOL
PARAMETER
tAO+tC
Throughput Times:
12-Bit Conversion
8-Bit Conversion
Conversion Time:
12-Bit Conversion
8-Bit Conversion
Acquisition Time
Aperture Delay
Aperture Jitter
tc
tAO
tA
tJ
SlH CONTROL EMULATION
TYP. MAX. TYP. MAX. UNITS
8
6
6.4
4.4
1.4
20
0.3
8.5
6.3
8
6
6.4
4.4
1.4
1600
10
Table 5. Conversion Timing Over T MIN to TMAX
8.5
6.3
I'sec
I'sec
I'sec
I'sec
I'sec
nsec
nsec
In the Emulation mode, the ADSn4 introduces a delay time between
the Convert command and the start of conversion, in order to allow
the converter enough time to acquire the signal before the conversion. The delay causes an effective increase in aperture time from
0.02 I'sec to 1.6 I'sec, and allows the ADSn4 to replace industrystandard, non-sampling n4 types in existing sockets. Slewing of
the analog input prior to the Convert command has no effect on the
accuracy of the ADSn4. In both the Control and Emulation modes,
the internal samplelhold circuit begins slewing to track the input
signal immediately after the conversion is complete.
In the Emulation mode, the ADS774 can replace existing, nonsampling 774 types in almost all applications, without any changes
in system hardware or software. It is not necessary that the input
signal be stable before a Convert command arrives, but it must remain stable during the acquisition period after the Convert command is received (as it must with other n4 types) for accurate performance. Unlike other, non-sampling n4 types, theADS774 allows
the input to begin slewing before the end of conversion (after the
1.61'sec acquisition period), so it is possible to increase system
throughput in many cases.
HARD-WIRING TO 8-BIT DATA BUSES - For applications with
a-bit data buses, output lines DB4 to DBll (Pins 20 to 27) should
connect directly to lines Do to 0 7 in the system data bus. In addition,
output lines DBO to DB3 (Pins 16 to 19) "hould connect to lines D.
to 0 7 on the system data bus, and to ADSn4 output lines DBa to
DBll (Pins 24 to 27). Figure 4 shows the proper connections. Thus
connected, if Ao is low during a read operation, the upper a bits are
enabled and become valid on output pins 20 to 27. When Ao is high
during an operation, the 4 lSBs are enabled on output pins 16 to
19 and the 4 middle bits (Pins 20 to 23) are overridden with zeros.
07
High Byte
(AD = 0)
low Byte
(AD = 1)
06
05
04
03
02
01
This configuration gives rise to two possible modes of operatlon. Conversions can be initiated with either positive or negative RIC pulses.
Figure S details operation with a negative start pulse. In this case, the
outputs are forced into the high-impedance state in response to the failing edge of RIC, and they return to valid logic levels after the conversion cycle is completed. The Status output goes high 200 nsec after
RIC goes low (t DS) and returns low no longer than 1000 nsec after data
is valid (tHsl. In this mode, output data is available most of the time, and
becomes invalid only during a conversion.
AIC
. - los
--...1,---------,.,
+ ___JI
Status _ _
~I
I~I
/>--------4\
---___.
0811 to DBa
Data Valid
High·Z State
Figure 5. Stand-Alone Mode With Negative Start Pulse.
Figure 6 details operation with a positive start pulse. Output data lines
are enabled during the time RIC is high. The falling edge of RIC starts
the next conversion, and the data lines return to the high-impedance
state and remain in that state until the next rising edge of RIC. In this
mode, output data is inaccessible most of the time, and becomes valid
only when RIC goes high. Table 6 gives the timing parameters for the
two modes.
DO
MSB DB10 DB9 DBa DB7 DB6 DBS DB4
RIC
DB3 DB2 OBI
DBO
0
o
o
o
Status--4---+_ _..,.......J
I
~
-r-
,...-"---Data Valid
21218
MSB 27
D,
081026
D,
08925
D,
08824
D,
08723
D,
08622
D,
08521
D,
DB420
D,
08319
High-Z
_--,-_--_________
_
/
Figure 6. Stand-Alone Mode with Positive Start Pulse.
08218
08117
~
Data
Bus
~
SYMBOL
PARAMETER
MIN.
tHRL
Low RIC Pulse Width
25
tos
STS Delay after RIC
tHDR
Data Valid after RIC Low
tHAH
High RIC Pulse Width
tOOA
Data Access Time
TYP.
MAX.
UNITS
nsec
200
25
100
nsec
nsec
nsec
150
nsec
Figure 4. Connection to 8-Bit Bus
Table 6. Stand-Alone Mode Timing over T MIN to TMAX
STAND-ALONE OPERATION - The ADSn4 can be used in a
stand-alone mode in systems having dedicated input ports and not
requiring full bus-interface capability. In this mode, CE and 12/8 are
tied to logic "1" (they may be hard-wired to +SV), CS and AD are
tied to logic "0" (they may be grounded), and the conversion is controlled by RIC. A conversion is initiated whenever RIC is brought low
(assuming a conversion is not already in progress), and all 12 bits
of the 3-state output buffers are enabled whenever RIC is brought
high (assuming Status has already gone low, indicating completion
of conversion).
UNIPOLAR OPERATION AND CALIBRATION -Analog input connections and calibration circuits for the unipolar operating mode are
shown in Figure 7. If the 0 to + 10V input range is to be used, apply
the analog input to Pin 13. If the 0 to +20V input range is to be used, apply the analog input to Pin 14. If the gain adjustment is not
needed, replace trim potentiometer R2 with a fixed, SOOI% metalfilm resistor to meet all published specifications. If the offset adjustment is not needed, connect Pin 12 (Bipolar Offset) directly to
Pin 9 (Analog Ground).
5-27
+5V
IO/,F
1
Voo
2
1218
3
CS
4
'"
Stan Convert
--u-
5
Status 28
High
Bits
AIC
I:
25
24
ADS774
WlthoutTnm
8
Ref Out
9
AnaGnd
Middle
Bits
Aelln
11
Mode
12
BlpO/fsel
13
lOV Input
14
2CNInpui
Low
Bits
1O"F
1
Voo
2
12/8
3
CS
--u-
5
High
'"
Middle
8
RelDul
Sits
9 AnaGnd
10
Aefln
11
Mode
12
BipOffsel
13
10\1 Input
14
2rNinput
Analog Inputs
f
f
Bipolar offset error refers to the accuracy olthe 0111 11111111 to 1000
00000000 digital output transition (see section entitled "DIGITAL
OUTPUT CODING"). Ideally, this transition should occur 1hLSB
below OV, and if the bipolar offset adjustment is not used, the transition will occur within the specified limit of its ideal value. Offset adjustment in the bipolar configuration is performed neit at the zerocrossing point but at the minus full-scale point. The procedure is
to apply an analog input equal to -FS + 1hLSB (-4.9988V forthe
±SV range; -9.9976V for the ± 10V range), and adjust the bipolar
offset trimpot "down" until the digital output is all zeros. Then adjust "up" until the LSB "flickers" between "0" and "1".
Bipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 111111111111 digital output transition after the bipolar offset
adjustment has been effected. Ideally, this transition should occur
11i2LSBs below the nominal positive full-scale value of the selected
input range. This corresponds to +4.9963Vand +9.9927V for the
±SVand ± 10V ranges, respectively. Gain trimming is accomplished
by applying either of these voltages and adjusting the gain It u.,pot
"up" until the digital outputs are all ones, then adjusting "down"
until the LSB "flickers" between "1" and "0".
22
21
+5V
1
VDl)
2
1218
3
CS
Low
Bits
IO/.F
17
4
5
'"
8
RelDul
SIan Convert
-U-
RIC
f
26
High
Bits
18
25
24
AD5774
16
WlthoulTnm
tOm!
Middle
BllS
In some applications, it is desirable to have the LSB equal exactly
2.SmV (10.24V input range) or SmV (20.48V input range). To implement these ranges, replace the 1000 gain trimpot by a SO 0 fixed
resistor. Then insert a 2.7kO trimpot in series with Pin 13 for a 10.24V
range; Pin 14 for a 20.48V range. Offset trimming then proceeds as
described earlier, and the gain trim is effected with the new trimpot.
12
BlpOilsel
13
1(Nlnpul
14
20V Input
Low
Bits
.5V
tOI'F
1
Vrl(l
2
12t8
3
CS
4
A"
5
RIC
Start Convert
-UWlthTnm
ADS774
High
911s
AnaGnd
Rei In
"
Mode
91pOfisel
13
IOVlnput
14
20VInput
Analogtnputs
Figure 8. Bipolar Connections
28
r
26
25
r
22
21
20
Low
BIIS
12
17
24
Middle
91ts
10
r
18
Status
8 RelOu1
9
"
16
Analog Inputs
"1".
Unipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 11111111 1111 digital output transition afterthe unipolar offset adjustment has been effected. Ideally, this transition should occur 11hLSBs below the nominal full-scale voltage for the selected
input range. This corresponds to +9.9963V and + 19.9927V, respectively, for the 10V and 20V unipolar input ranges. Gain trimming is
accomplished by applying either of these voltages and adjusting
the gain potentiometer up until the digital outputs are all ones, and
then adjusting down until the LSB "flickers" between "0" and "1 ".
Ref In
Mode
50!!
Figure 7. Unipolar Connections
Unipolar offset error refers to the accuracy of the 0000 0000 0000
to 0000 0000 0001 digital output transition (see section entitled
"DIGITAL OUTPUT CODING"). If the offset adjustment is not used, the actual transition will occur within specified limits of its ideal
value (+ 1hLSB). For the 10V range, 1 LSB = 2.44mV. For the 20V
range, 1 LSB = 4.88mV. To adjust the offset, apply an analog input
equal to + 1hLSB and, with the ADS774 continuously converting,
adjust the offset potentiometer down until the digital output is all
ones, and then adjust up until the LSB "flickers" between "0" and
10
11
r
22
2
~o
:::;;
-aD
Cl
IV
-40
.".ec:
~O
::e
-aD
~
-100
-100
-120
-120
0
10
:!? 100
10
20
z
I
90
.~-
40
30
ffi
InT
~il!rot'o~ (T~J;'
I
S\9~WJ!Nolsel Ra(iOI(S~R)
50
55
80
10
'D
.5
~
.
,g
a:
~
70
0
li'iii'
r-.r....
40
r....
r....r-.
a:
r-.r....
2!0
8:
"
20
Ul
I
60
D-
10
60
c
-'" ~~
Input Frequency (kHz)
5·30
20
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
Ti'lfITi' Tfr
0.1
10
SPURIOUS FREE DYNAMIC RANGE, SNR AND THO
vs INPUT FREQUENCY
TotallHalmW
80
0
Input Frequency (kHz)
IL
c%
55
Input Frequency (kHz)
II
1
~
50
Spurious Free Dynamic Range
o
Ul
40
30
I
f-
a!
100
Input Frequency (kHz)
Input Frequency (kHz)
":Ec:
~
10
0.1
55
+25°C
~
65
0
ro
~
~
c:
.2'
-120
-20
Hi
ro
100
10
10
100
lk
10k
lOOk
Supply Ripple Frequency (Hz)
1M
10M
PACKAGE OUTLINES
DIM
A
B
D
E
F
G
H
14
J
K
PACKAGE E. PLASTIC SINGLE DIP
M
N
P
-------- 0
-------~
DIM
AC"
-,
o
o
E,
A,")
B
BI
INCHES
MIN MAX
.169
200
.015
.070
.015
.020
.015
.055
.006
.012
1.360 1.455
E
.600
.625
E,I'I .485
.550
.100 BASIC
el
.600 BASIC
eA
C
0(1)
INCHES
MIN
MAX
1.255 1.355
270
.290
.150
.170
.010
.060
.100 BASIC
.055
.045
.016
.020
.125
NlA
.300 BASIC
15'
0'
.006
.020
.015
I
.040
MILLlMffiRS
MIN
MAX
4.29
5.06
0.36
1.78
0.36
0.51
0.36
1.40
020
0.30
35.05 36.96
15.24 15.66
12.32 13.97
2.54 BASIC
1524 BASIC
MILLIMETERS
MIN
MAX
31.88 34.42
6.86
7.37
3.61
4.32
0.25
2.03
2.54 BASIC
1.14
1.40
0.41
0.51
3.18
NlA
7.62 BASIC
0'
15"
0.20
0.36
0.51
1.02
INCHES
MIN
MAX
.100
.200
.000
.030
0'
15'
.040
.080
DIM
L
1.2
a
sm
MILLIMETERS
MIN
MAX
2.54
5.06
0.76
0.00
0'
15'
1.02
2.03
PACKAGE P. PLASTIC DOUBLE DIP
-II-e
A
I"
28
~ [
1
'<: Index Mark
1~1_
DIM
A
] 14 IJ
B
C
PACKAGE F. CERAMIC HERMETIC SINGLE DIP
,,
!
~~
I I
,i
,
0
F
G
J
K
L
N
INCHES
MIN
MAX
1.368 1.412
.300
.320
.160
.016
.020
.050 BASIC
.095
.009
.125
.290
.040
.105
.012
.180
.310
.060
MILLIMETERS
MIN
MAX
35.26 35.66
7.62
8.13
-
4.06
0.41
0.51
127 BASIC
2.41
2.67
0.23
0.30
3.18
4.57
7.37
7.87
1.02
1.52
u Ie
---Tl
N
K
5-31
PACKAGE H. CERAMIC HERMETIC DOUBLE DIP
r---------A
15
28
D
°1
F
DIM
A
C
D
F
14
G
H
J
K
L
M
N
INCHES
MIN
MAX
1.386 1.414
.115
.175
.015
.021
.060
.035
.100 BASIC
.064
.036
.012
.008
.120
.240
.600 BASIC
10"
.025
.060
MILLIMETERS
MAX
MIN
35.20 35.92
4.45
2.92
0.38
0.53
1.52
0.89
2.54 BASIC
0.91
1.63
0.20
0.30
3.05 1 6.10
15.24 BASIC
0.64
10"
I
1.52
~
PACKAGE U. PLASTIC SOIC
DIM
A
8
C
D
G
H
J
L
M
N
[1JJ
_
MICRO NETWORKS
324 Clark St .. Worcester. MA 01606 (508) 852-5400
5-32
INCHES
MIN
MAX
.716
.700
.266
.302
.109
.093
.016 BASIC
.050 BASIC
.022
.038
.0081.012
.414
.398
5°TYP
.012
.000
MILLIMETERS
MIN
MAX
17.76 16.19
7.26
7.67
2.36
2.77
0.41 BASIC
1.27 BASIC
0.56
0.97
0.20
0.30
10.11 10.52
5°TYP
0.00
0.30
LlJ
_
ADS7800
3/lsec, 12-Bit
SAMPLING AID CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• 333kHz Over Temperature
• ±5Vand ±10V Input Ranges
• AC and DC Performance
Completely Specified
• Internal Sample/Hold, Clock,
Reference, 3-State Buffer
• 215mW Power Dissipation
• No-Missing-Codes
Over Temperature
• 8-Bit or 12-Bit Output Format
• Package Options
Plastic DIP
Hermetic DIP
SOIC
The ADS7800 is a complete, low-cost, 12-bit successive-approximation
AID converter with an internal sample/hold function. The ADS7800
uses an innovative, capacitor-array internal D/A converter, based on
CMOS technology. The use of a CMOS architecture results in
extremely low power consumption. Total acquisition and conversion
time of 31"sec results in a 333kHz sampling rate, over the entire
operating temperature range. AC and DC performance are completely
specified.
The ADS7800 is complete with internal clock, reference, control logic,
and 3-state output buffer. The interface logic provides for easy handshaking with most popular 8- and 16-bit microprocessors. The
ADS7800's 3-state output buffer connects directly to the I"P'S data bus,
and is readable as either one 12-bit word or two 8-bit bytes. Chip
select, high-byte enable, and read/write (read/convert) control inputs
enable the ADS7800 to connect directly to a system address bus and
control lines, and to operate totally under processor control.
Internal scaling resistors allow a pin-selectable choice of two input
ranges: ±5Vand ± 10V. The ADS7800 is available for operation over
the commercial (O°C to + 70°C) and industrial (-40°C to +85°C)
temperature ranges. Package options include 24-pin single (0.300")
plastic or hermetic ceramic DIPs, and 24-pin plastic SOIC. The
ADS7800 operates from a +5V supply and either a -12V or -15V
supply.
Model
Number
ADS7800JP
ADS7800KP
ADS7800JU
ADS7800KU
ADS7800AH
ADS7800BH
Package
Temperature
Range
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Ceramic DIP
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
-40°C to +85°C
Ceramic DIP
-40°C to +85°C
Linearity
Error Max
(T m;n to T m,,)
±1
±'h
±1
±'h
±1
±'h
SINAO'
(dB Min.)
67
69
67
69
67
69
'Signal-to-(Noise+Oistortion) Ratio.
l1JJ
_
May 1992
Copyright 1992
MICRO NETWORKS
Micro Networks
All rights reserved
324 Clark SI, Worcester, MA 01606 (508) 852-5400
5-33
I
ADS7800 12-Bit SAMPLING AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range:
J, KGrades
A, B Grades
Storage Temperature Range:
+Vs to Digital Ground
-Vs to Analog Ground
+VSA to +VSD
Analog Ground to Digital Ground
Control Inputs to Digital Ground
Analog Input to Voltage
Junction Temperature
Lead Temperature (Soldering, 10 sec)
Power Dissipation
Thermal Resistance JA :
Plastic DIP
SOIC
Ceramic DIP
e
DESIGN SPECIFICATIONS
ORDERING INFORMATION
PART NUMBER -----ADS7800 J P
O°C to +70 oC
_40°C to +85°C
-65°C to + 150°C
+7V
-16.5V
±0.3V
Select suffix J, K, Aor B for ~
desired performance and
specific temperature range.
Select suffix P, U or H
for desired package option.
±1V
-03V to Vs +0.3V
±2rN
+160°C
+300°C
750mW
l00°C/W
100°C/W
50 0 C/W
(TA =TMIN to T MAX' VS = +5V, Vs = -15V, Is =333kHz, unless otherwise indicated)
ANALOG INPUTS
MIN.
TYP.
Input Voltage Range
Input Impedance: ± 10V
+5V
MAX.
4.4
2.9
UNITS
Volts
+10 and +5
6.3
4.2
B.l
5.4
kO
kO
+5.3
+0.8
+5
-5
Volts
Volts
+5.0
+0.4
±5
Volts
Volts
,..A
DIGITAL INPUTS CS, RIC, HBE
Logic Levels: Logic "1"
Logic "0"
Loading: Logic "1"
Logic "0"
+2.4
-0.3
"A
"A
DIGITAL OUTPUTS DBO to DB11, BUSY
Output Format
Output Coding
Logic Levels: Logic "1" (ISOURCE = 500,..A)
Logic "0" (ISINK = 1.6mA)
Leakage (High-Impedance State)
12-Bit Parallel or 8-Bit/4-Bit
Offset Binary
+2.4
0
±0.1
INTERNAL REFERENCE
Reference Output Voltage (Pin 3)
Available Output Source Current
1.9
2.0
10
2.1
Volts
,..A
-11.4
+4.75
-15
+5.0
3.5
18
135
-16.5
+5.25
6
25
215
-
Volts
Volts
rnA
rnA
mW
POWER SUPPLY REQUIREMENTS
Power Supply Range: -Vs Supply
Power Supply Range: +Vs Supply
Current Drains: -Is
+Is (Total)
Power Dissipation
DYNAMIC CHARACTERISTICS
Aperture Delay
Aperture Uncertainty (Jitter)
Transient Response, Full-Scale Step (Note 1)
Overvoltage Recovery, 2 X FS (Note 2)
13
150
130
150
nsec
psec, rms
nsec
nsec
CONVERSION TIME
Conversion Only
Conversion + Acquisition
Throughput Rate
SPECIFICATION NOTES:
1.
2.
3.
4.
For 12-bit accuracy in specified time.
To specified performance in specified time.
Adjustable to zero with external trimpot.
Least Significant Bit. lLSB=2.44mV for the
±5V range; 4.88mV for the ±10V range.
5. Characterized over T MIN to T MAX at + FS, OV, and - FS. 0.1 LSB
is typical rms noise with worst-case conditions:
+ FS at + 125°C.
6. All dB figures refer to ±10V or ±5V full-scale input.
CAUTION: These Devices are sensitive to electrostatic discharge.
Proper anit-ESD IC handling procedures should be followed.
5-34
333
2.5
2.6
380
2.7
3.0
pSec
~sec
kHz
PERFORMANCE SPECIFICATIONS (TA =TMIN to TMAX, +VS =+5V, -VS =-15V, fS =333kHz, unless otherwise indicated)
ADS7800KP/KUlBH
ADS780OJP/JUIAH
MODEL
TRANSFER CHARACTERISTICS
MIN.
TYP.
RESOWTION
MAX.
TYP.
MIN.
12
MAX.
UNITS
12
Bits
±O.35
%
ppm/oC
LSB(Note4)
LSB
Bits
LSB
ppm/oC
LSB
TRANSFER CHARACTERISTICS
Full·Scale Error
Full-Scale Error Drift
Integral Nonlinearity
Differential Nonlinearity
Resolution for No Missing Codes
Bipolar Zero Error (Note 3)
Bipolar Zero Error Drift
Transition Noise (Note 5)
±O.50
6
6
±1
±1
12
±1!2
±3/4
12
±2
±4
1
0.1
1
0.1
AC ACCURACY (Note 6)
Spu rious-Free Dynamic Range
Total Harmonic Distortion
Signal-te-Noise Ratio
Signal-to-(Noise+Distortion) Ratio (SINAD)
Intermodulation Distortion (-6dB Signals)
(flNl =24.4kHz; flN2 =28.5kHz)
74
68
67
80
-80
73
72
-74
71
70
-77
POWER SUPPLY SENSITIVITY
-Vs=-13.5V to -16.5V
-Vs=-l1.4V to -12.6V
+Vs = +4.75V to +5.25V
TEMPERATURE RANGE
70
69
-77
-74
± 1;'
± 1;'
+1
Specified: JP/JU/KP/KU Models
AH/BH/ Models
Storage
CS (20)
77
77
-77
0
-40
-65
+70
+85
+150
0
-40
-65
0-------.
R/e(19)
-74
dB
dB
dB
dB
dB
±';'
± 1;'
±';'
LSB
LSB
LSB
+70
+85
+150
°C
°C
°C
-77
.---0
(24) +Vs ANA
.---0
(23) +Vs DIG
(21) BUSY
CONTROL
LOGIC
SUCCESSIVEAPPROXIMATION REGISTER
(5) OBll (MSB)
(S) OB10
(7) DB9
(8) DB8
(9) DB7
3
S
T
A
T
E
±10V IN (1)
±5V IN (2) D--JlJ'I/V'-+----------I
CAPACITOR-ARRAY
12-BIT
DIA CONVERTER
REF OUT (3)
o--------~--------'
ANA GNO (4)
0--
DIG GNO (13)
0--
(10) DBS
(11) OB5
(12) OB4
(14) DB3
B
U
F
F
E
R
(15) DB2
(IS) DBI
(17) DBO (LSB)
(18) HBE
COMPARATOR
.---0
(22) -Vs
ADS7800 BLOCK DIAGRAM
5-35
PIN DESIGNATIONS
24
12
13
± 10V Analog Input. Ground for ±5 range.
2 ±5V Analog Input. Ground for ± IOV range.
3 +2V Reference Output
4 Analog Ground. Connect to Pin 13.
5 Data Bit 11 (MSB)
6 Data Bit 10
24
23
22
21
20
7 Data Bit 9
8 Data Bit 8
9 Data Bit 7
10 Data Bit 6
11 Data Bit 5
12 Data Bit 4
18
17
if
if
if
if
HBE
HBE
HBE
HBE
Low;
Low;
Low;
Low;
19
"0" if HBE High.
16
"0" if HBE High.
15
14
13
"0" if HBE High.
"0" if HBE High.
+5V Analog Power Supply. Connect to Pin 23.
+5V Digital Power Supply. Connect to Pin 24
-12V or -15V Negative Power Supply
BUSY
Cs Chip Select
RIC ReadlConvert
HBE High Byte Enable
Data Bit 0 (LSB) if HBE Low, Data Bit 8 if HBE High.
Data Bit 1 if HBE Low; Data Bit 9 if HBE High.
Data Bit 2 if HBE Low; Data Bit 10 if HBE High.
Data Bit 3 if HBE Low; Data Bit 11 if HBE High.
Digital Ground. Connect to Pin 4.
DESCRIPTION OF OPERATION
The ADS7800 is a complete 12-bit AiD converter. It uses the successiveapproximation conversion technique and incorporates all required function blocks - capacitor-array D/A converter, corr,parator, clock,
reference, and control logic. The CMOS-based capacitor-array architecture provides an inherent samplelhold function. The device mates
directly to most popular 8-, 16-, and 32-bit microprocessors and contains all the necessary address-decoding logic, control logic, and 3-state
output buffering to operate completely under processor control. In most
cases, the ADS7800 will require only power supplies and bypass
capacitors to provide the complete AiD conversion function. The completeness of the device makes it most convenient to think of the
ADS7800 as a function block with specific input/output transfer
characteristics; it is thus quite unnecessary to be concerned with its
inner workings.
During the conversion, the BUSY signal imposes the high-impedance
state on the output data lines and also inhibits input lines. The inhibition causes Pin 19 to ignore any pulses, so new conversions cannot
be initiated while a conversion is taking place, whether the pulses result
from spurious sources or an attempt to short-cycle the conversion.
BASIC OPERATION - Figure 1 gives the basic connections for
operating the ADS7800 with the ± 10V input range in Convert mode.
The Convert command RIC, applied to Pin 19, puts the ADS7800 in
Hold mode and initiates the conversion. RIC must hold Pin 19 low for
at least 40nsec. The BUSY signal on Pin 21 is held low during the conversion, and goes high after the conversion is completed and the data
is transferred to the output latches. The rising edge of the signal on
Pin 21 can thus serve to read the converted data.
The signal HBE on Pin 18 allows the ADS7800 to be used with an 8bit bus. At. the end of a conversion, a low input on Pin 18 loads the eight
LSBs of data into the latches of Pins 9 through 12 and 14 through 17.
A high signal on Pin 18 then loads the four MSBs into the latches of
Pins 14 through 17, and Pins 9 through 12 are forced low. Figure 2 and
Table 1 give the timing parameters for the basic acquisition and conversion operations.
In Read mode, Pin 19 is held low, and a high-going pulse serves to
read data and initiate a conversion. In Read mode, the rising edge of
the RICsignal on Pin 19 enables the output data pins, thus val!£ating
the data from the previous conversion. The falling edge of RIC then
puts the ADS7800 in Hold mode and initiates a new conversion. The
ADS7800 will begin acquiring a new signal upon the completion of the
conversion, even before the BUSY signal rises on Pin 21, and will track
the input signal until the start of the next conversion, whether the
ADS7800 is in Convert or Read mode.
RIC
r-
BUSY--+--~
21N2
BUSY 21 1--+------....
Ric 191--+-------C
HBEIS
t--
+
, - - - - - - - t - - 1 a DBB
,----~---l9
Hold Time
OB7
Figure 2. Conversion and Acquisition Timing
OB215-~
D8314
r--
DGN013
f----.
+
Figure 1. Basic ±10V Connection Diagram
Symbol
Typ
Max
Units
nsec
BUSY Delay from RIC
80
150
ts
BUSY Low
2.5
2.7
lAP
Aperture Delay
13
"'tAP
Aperture Jitter
150
Conversion Time
2.47
t DSC
,"0
ILSBI
Parameter
Ic
Table 1. Acquisition and Conversion Timing
5-36
pSec
nsec
psec, rms
2.70
~sec
CONTROL FUNCTIONS - The ADS7800 offers easy interface to
most digital systems, whether microprocessor-based or other. The
ADS7800 can operate under complete microprocessor control, or in
a stand- alone mode, in which it is controlled only by the RIC input on
Pin 19. Microprocessor control entails initiating the conversion and
reading the output data, either in one 12-bit parallel word or in two B-bit
bytes. All control inputs (CS, RIC, and HBE) are TIL- and CMOScompatible. Tables 2 and 3 detail the functions of the control inputs.
Pin No.
Symbol
Function
High Byte Enable. When held Low, data
output has 12-bit parallellormat. When held
High, 4 MSBs appear on Pins 14 to 17;
zeros appear on Pins 9 to 12. Must be Low
to initiate conversion.
18
HBE
19
RIC
Read/~nvert. Falling edge initiates conversion
when CS is Low, HBE is Low, and BUSY is High.
20
Cs
Chip Select. Outputs in High-Z state when
CS is High. Must be Low to initiate conversion
or read data.
21
BUSY
Busy, Output Low during conversion.
Data valid on rising edge in Convert mode.
In stand-alone mode, a single control line connected to RIC controls
the ADS7BOO. CS and HBE are grounded in this mode. The output
data is in 12-bit parallel format. Stand-alone mode is useful in systems
using dedicated input ports that do not require full bus-interface
capability.
A high-to-Iow transition on R/Cinitiates a conversion. The 3-state outpul latches are enabled when RIC and BUSY are high. Thus, two
modes of operation are possible: Either positive or negative pulses can
initiate a conversion. Either way, the RIC pulse must remain low for
at least 40nsec.
Figure 3 and Table 4 give timing details for a conversion initiated by
a negative RIC pulse. In this case (referred to as Convert mode), the
3-state outputs revert to the high-impedance state in response to the
falling edge of RIC, and become enabled for data access after the completion of the conversion.
BUSY
--+----.1
Table 2. Role of Control Functions
Convert
CS
RIC
1
X
X
1
0
1-0
0
1
Holds Signal and Starts Conversion.
0
1
0
1
3-State Output Buffers Enabled
Upon End of Conversion.
Data
HBE BUSY
Operation
None -
---+-_.1,--=-'-'----....1
Sec _ _---r--'l'-_-"----'-_ _ _JI\......;.;:;,,;.,:..:....,'-_H,g"-h_'m...:p"'ed;.;.a_c''''e_
.-_
Outputs in High-Z State.
0
1
1
1
Enable High Byte in 8-Bit Bus Mode.
0
1-0
1
1
Inhibits Start of Conversion.
X
X
X
0
Conversion in Progress. Outputs in
High-Z State. New Conversion Inhibited
Until End of Present Conversion.
I
Figure 3. Timing with Negative RIC Pulse
X="Don't Care'.
Table 3. Control Functions
Symbol
tw
Parameter
RIC Pulse Width
Min.
Typ.
40
10
Max.
Units
nsec
BUSY Delay from Ric
80
150
nsec
ts
BUSY Low
2.5
2.7
iiSec
tAP
Aperture Delay
13
nsec
"tAP
Aperture Jitter
150
psec, rms
tosc
Conversion Time
2.47
tOSE
BUSY from End of Conversion
100
tos
BUSY Delay after Data Valid
tA
Acquisition Time
tc
tA + tc
tHOR
25
Total Throughput Time
Valid Data Held after Ric Low
20
nsec
nsec
130
300
nsec
2.6
3.0
"sec
50
nsec
nsec
CS or HBE Low before RIC 1 -0 Transition
25
5
CS or HBE Low after RIC 1-0 Transition
25
0
too
Data Valid from CS Low, RIC High, and HBE as Selected (100-pF Load)
tHOR
Valid Data Held after R/CLow
65
20
iiSec
200
ts
Delay to High-Z State after RIC Falls or CS Rises (3kQ Pullup or Pulldown)
2.7
75
tH
tHL
i,'
_
nsec
150
50
50
nsec
nsec
150
nsec
Table 4. Timing Specifications Over T MIN to TMAX'
5-37
Figure 4 and Table 4 detail the timing considerations for a conversion
initiated by a pos~ive RICpulse. In this case (referred to as Read mode),
output d~ from a previous con~rsion .is enabled during the high portion of RIG. The falling edge of RIC initiates a new conversion, and the
3-state outputs revert to the high-impedance state until RIC again attains a high state.
cs
RIC
HBE
BUSY ---;---------i
DB11
to
DBD
Figure 4. Timing with Positive R/CPulse
TIMING -INITIATING CONVERSIONS - As seen in Table 1, only
a negative-going transition on RlC--no other combination of states or
transitions-can initiate a conversion in the ADS78oo. CS or HBE high,
or BUSY low, will inhibit conversion. CS and HBE should be stable
for at least 25 nsec prior to the RIC transition. Figure 5 shows the timing details for initiation of a conversion.
cs
or
HBE
Figure 6. Read Cycle Timing
INTERNAL CLOCK - A factory-trimmed internal clock in the
ADS7800 yields a typical conversion time of 2.47pSec at 25°C, and a
maximum conversion time of 2.7pSec over the entire operating
temperature range. This conversion time, coupled with a guaranteed
maximum acquisition time of 300nsec, ensures a 333kHz minimum
throughput rate under all conditions.
BIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the ADS7800 are shown in Figure
7. If the ±5V input range is to be used, apply the analog input to Pin
2 and ground Pin 1. If the ± 10V range is to be used, apply the analog
input to Pin 1 and ground Pin 2. If either offset or gain adjustments
are not to be used, the ADS7800 will perform to the limits in the
specification table.
Bipolar offset (zero) error can be defined as the accuracy of the 0111
1111 1111 to 1000 0000 0000 transition voltage (-2.44mV for the ± 10V
range; -1.22mV for the ±5V range). With the ADS7800 converting continuously, adjust the 10kfl trimpot "up" until the output code is 1000
00000000, then adjust "down" until all bits are "flickering" between
"0" and "1".
R/C---_...
BUSY---------~------~I
+1OV~
lDBe
INPUT
1.
No
Tnm
Data
Bus
Data Valid
2
High Impedance
----+'
Gain
Figure 5. Conversion Initiation Timing
Gain
+5V
The BUSY line, in a low state only during a conversion, shCJINS the status
of the converter. During the conversion, the 3-state output latches remain in a high-impedance state; therefore, data is inaccessible during a conversion. During the conversion, the digital inputs CS, RIC,
and HBE are immune to additional transitions, so conversions cannot be prematurely terminated or restarted.
TIMING - READING DATA - After the start of a conversion, the
3-state output buffers remain in a high-impedance state until the following logic combination exists: RIC is high, BUSY is high, and cS is low.
When this combination occurs, the 3-state data lines are enabled in
accordance with the state of HBE. Figure 6 and Table 4 give details
of the timing relationships and specifications for reading data.
5-38
10kO
10kO ~"',"",,-N-"
BipZero
49.9Il
J01n
6.65KO
-15V
-15V
Figure 7. Connections and Calibration
justments should be mounted as close to the converter as possible.
Bipolar gain error can be defined as the accuracy of the 1111 1111 1110
to 1111 1111 1111 digital output transition after the bipolar offset adjustment has been effected. Ideally, this transition should occur 1'12 LSBs
below the nominal positive full-scale value of the selected input range.
This corresponds to +4.9963Vand +9.9927Vforthe ±5Vand ±10V
ranges, respectively. Gain trimming is accomplished by applying either
of these voltages and adjusting the gain trimpot "up" until the digital
outputs are all ones, then adjusting "down" until the LSB "flickers"
between "1" and "0".
It is necessary to bypass the reference output (Pin 3) with a 221'F to
471'F, 2V tantalum capacitor. The drive capability of this pin is lirnited
(10~ typ), so it is necessary to provide buffering if this reference voltage
is to be used in other parts of the system.
POWER-SUPPLY SEQUENCING PRECAUTIONS -If the two +5V
supply inputs of the ADS7800 are powered-up sequentially instead of
simultaneously, the converter may experience latch-up and draw excessive current. Connecting the two supply pins together on the printedcircuit board will normally prevent this problem. However, the
phenomenon can occur if the ADS7800 is plugged into a live socketfor example, during incoming inspection or lab evaluation. In these
cases, it is necessary to ensure that power is applied only after the
ADS7800 has been plugged in.
LAYOUT CONSIDERATIONS AND GROUNDING - The ADS7800
has two +5V supply pins: VSA (Pin 24) and VSD (Pin 23). To achieve
maximum accuracy in the ADS7800, these supplies are not connected
internally. They should be connected together on the printed- circuit
board, at a point as close as possible to the ADS7800. Both supply
lines should be well isolated from digital supplies that are subject to
large load variations. As a general rule, it is good practice to isolate
the analog portions of a system from the effects of digital switching by
running a separate +5V supply line from a supply regulator to the
analog components.
AVOIDING TRANSIENT PHENOMENA - various transients coupled
into the ADS7800 can cause errors that may difficult to diagnose. If
errors persist despite careful grounding and bypassing measures, they
might find their origins in one or more not-so-obvious transient
phenomena. A checklist of several transient-avoidance steps can be
useful in designing a new system.
To minimize noise, the tied-together Vs Pins 23 and 24 should be
bypassed to ground with a 6.81'F tantalum capacitor in parallel with a
0.1i 2.7J'Sec) will avoid affecting the LSB decision.
These bypassing measures are extremely important, as noise on the
power-supply lines can degrade converter performance. It is necessary
to pay special attention to filtering out noise and spikes when a switching power supply is used.
The analog (Pin 4) and digital (Pin 13) ground pins are also not connected internally, and should be connected together as close as possible to the ADS7800. The use of a ground plane on the printed- circuit
board is highly recommended, as it optimizes high- frequency ground
characteristics and reduces noise coupling into sensitive converter circuitry. It is especially important to reference the analog input to the
analog ground on Pin 4, to eliminate from the input circuitry any voltage
drops that might occur in the power-supply ground returns.
High-speed bus transients can also couple into the ADS7800 via the
data outputs, even when the output buffers are in the high- impedance
state. If such transients exist, it is good practice to isolate them from
the converter by providing additional buffering to the data outputs. The
BUSY line can serve to enable these added buffers.
It is necessary to take the input impedance of the ADS7800 into account when designing the analog drive circuitry. The output impedance
of the driver should be negligible with respect to the 6.3kfl (± 10V range)
or 4.2kfl (±5V range) input impedance of the ADS7800, or at least invariant with respect to signal level. Further, it is crucial to prevent any
coupling between the analog input lines and digital signal lines. If these
lines must cross, it is recommended that they do so at right angles,
and with a minimum of crossover area. If they must run parallel for any
distance, it is good design practice to insert a ground pattern between
them as a shield. Any external trimpots used for full-scale or offset ad-
It goes without saying that transients on the analog inputs are to be
avoided scrupulously, especially in the interval within ± 20nsec of the
"1 "-to-"O" transition of RIC, when they may affect the charge transferred
to the capacitor array. Careful layout and design of the analog drive
circuitry are necessary to avoid these transients. Finally, in multiplexed systems, it is most prudent to switch channels in the multiplexer
only after the conversion is complete. Otherwise, glitches or ringing
in the switched signal may be coupled into the ADS7800 during the
conversion process.
DIGITAL OUTPUT CODING
._- - - - - - - - - , - . _ - - - - - - - - - ,
.. __ A~~LO~~NI)y~0'()It~ __________ ~r_DIGITAL OUTPUT
± 5V
± 10V
+5.0000
+4.9963
+10.0000
+9.9927
1111
1111
+0.0012
-0.0012
-0.0037
+0.0024
-0.0024
-0.0073
1000 0000 000$1'
0/IJ1iJ/IJ lIJ~/IJ 00/6/6'
0111 1111 111/6'
-4.9988
-5.0000
-9.9976
-10.0000
0000 0000 000/6'
0000 0000 0000
MSB
LSB
1111
1111
1111
111$1'
DIGITAL OUTPUT CODING NOTES:
1. Output coding is offset binary.
2. For ±5V input range. 1LSB for 12 bits = 2.44mV 1LSB for 11
bits = 4.88mV
3. For ±10V input range. 1LSB for 12 bits = 4.88mV 1LSB for
11 bits = 9.77mV
, Voltages given are the theoretical values for Ihe transitions indicaled. Ideally. with Ihe converter continuously converting. the
outpul bils indicated as¢will change from a logic "1"10 a logic
"0" or visa versa as the input voltage passes through Ihe level
indicated.
EXAMPLE: For an ADS7800 operating on its ± lOV input range,
the transition from digital output 0000 0000 0001 (or vice versa)
will ideally occur at an input voltage of -9.9976 volts. Subsequently. any input voltage more negative than -9.9976 volts will give
a digital output of all "O·s". The transition from digital output 1000
0000 0000 to 0111 1111 1111 will ideally occur at an input of -0.0024
volts. and the 1111 1111 1111 to 1111 11111110 transition should occur at +9.9927 volts. An input more positive than +9.9927 volts
will give all "1 's".
5-39
PACKAGE OUTLINES
PACKAGE H. CERAMIC HERMETIC DIP
DIM
A
B
C
D
F
G
J
K
L
N
INCHES
MILLIMETERS
MIN MAX MIN MAX
1.188 1.212 30.18 30.78
.300 .320 7.62 8.13
.160
4.06
.016
.020 0.41 0.51
.osa TYP
127TYP
.105 2.41 2.67
.095
.009
.012 0.23 0.31
.170 BASIC
4.32 BASIC
.290 I .310 7.37 7.87
.040 .060 1.02 1.52
-
-
PACKAGE P. PLASTIC DIP
I'
'I
cg::::::::2:IIJ
A
'Pinl
DIM
A
B
D
E
F
G
H
J
K
M
N
P
INCHES
MIN MAX
1.125 1.255
.250
.290
.150
.170
.060
.010
.100 BASIC
.070
.050
.016
.020
.125
.300 BASIC
O·
15'
.015
.008
.010
.030
MILLIMETERS
MIN MAX
28.58 31.88
6.35 7.37
3.81 4.32
.25
2.03
2.54 BASIC
1.27 1.78
0.41 0.51
3.18
7.63 BASIC
O·
15'
0.20 0.38
.25 I .76
INCHES
MIN MAX
.602
.618
.618
.595
.286
.302
.270
.285
.108
.093
.015
.019
.osa BASIC
.026
.034
.012
.008
.390
.422
O·
10'
.QOO
.012
MILLIMETERS
MIN MAX
15.29 15.70
15.11 15.70
7.26 7.67
6.86 7.24
2.36 2.74
0.38 0.48
1.27 BASIC
0.66 0.86
0.20 0.30
9.91
10.72
O·
10'
0.00 0.30
PACKAGE U. PLASTIC SOIC
f f
81
LTITI=t=rn=rrrr;:;::;::;:::n=rr=;:r~~
Pi
1
5-40
8
DIM
A
Al
B
61
C
D
G
H
J
L
M
N
l1JJ
_
MN6227
MN6228
WIDEBAND, SAMPLING
12-Bit AID
CONVERTERS
MICRO NETWORKS
FEATURES
• 33kHz Sampling Rate
With Internal TIH Amplifier
• 16.5kHz Full·Power
Input Bandwidth
• 70dB Signal·to·Noise Ratio
Over Full Bandwidth
• - 80dB Harmonics Over
Full Bandwidth
• Full 8 or 16·Bit "p Interface:
CS, CE, RIC, Ao, 12/8
150nsec Bus Access Time
• Industry· Standard MN574A
Package and Pinout
• 1100mW Max Power
• Fully Specified O°C to + 70°C
(J and K Models) or - 55°C
to + 125°C (S and T Models)
28 PIN DIP
DESCRIPTION
MN6227 and MN6228 are the first, general-purpose, high·
speed, 12·bit, sampling AID converters designed and
specified for contemporary DSP applications in the fields
of spectrum analysis, voice recognition, vibration anal·
ysis, signature recognition, and others. These devices
consist of high·speed (25jLsec), jLP interfaced (CS, CE,
read/convert, 3·state buffer, etc.), successive-approx·
imation type, 12·bit AID converters with internal, high·
speed, track·hold (T/H) amplifiers. They have the ability to
accurately sample and digitize transient or periodic input
signals with slew-rate and frequency content orders of
magnitude higher than can be converted by an A/D
without a companion T/H.
1:'-'
MN6227 (10V input span) and MN6228 (20V input span)
are configured in a manner that makes the T/H transparent to the user. There are no confusing acquisition
time, aperture delay, or aperture jitter specifications.
These are true sampling, broadband AID converters that
are specified accordingly. Sampling rate, analog-input
full-power bandwidth, harmonic distortion, and signal-tonoise ratio (SNR, rms-to-rms) are all fully specified. Each
device is fully tested both statically, in the traditional
manner, and dynamically with a series of 512-point FFT's
(see sample spectrum below).
-
These devices are packaged in small, low-profile, 28-pin,
side-brazed, ceramic DIP's and have the industrystandard MN574A pinout. Devices are fully specified for
O°C to + 70°C (J and K models) or - 55°C to + 125°C (S
and T models) operation.
OdB -
-2OdB
o 190J..48?6)
-40dB
0220 (55B8)
j
i
Input Frequency: 16kHz
Sampling Rate: 33kHz
RMSSignal: -0.26<18
RMS Noise" -73.64<16
SIN: 73.3&18
Signal
Amplitude
Relative 10
Full Scale
-100dS
14-°6001 15241 _
Dimensions in Inches
(millimeters)
Input Frequency
~
May 1988
MICRO NETWORKS
324 Clark Sl., Worcester, MA 01606 (508) 852-5400
5-41
,,
MN6227 MN6228 WIDEBAND SAMPLING 12-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN6227J, K; MN6228J, K
MN6227S, SIB, T, TIB
MN6228S, SIB, T, TIB
Storage Temperature Range
Positive Supply (+ Vcc, Pin 7)
Negative Supply (- Vcc, Pin 11)
Logic Supply (+ Vdd, Pin 1)
Digital Inputs (Pins 2·6)
Analog Inputs: Pins 10 and 12
Pin 13 (MN6227)
Pin 14 (MN6228)
Analog Ground (Pin 9) to Digital
Ground (Pin 15)
Ref Out (Pin 8) Short Circuit Duration
ORDERING INFORMATION
-55'Cto + 125'C
PART NUMBER
O'C to + 70'C
- 55'C to + 125'C
- 55'C to + 125'C
-65'Cto + 150'C
o to + 16.5 Volts
to - 16.5 Volts
o to + 7 Volts
- 0.5 to ( + Vdd + 0.5) Volts
± 15 Volts
± 15 Volts
± 15 Volts
Select MN6227 or MN6228
Select suffix J. K. S. or T for
desired performance and
specified temperature range.
Add "IB" to "S" or "T" models for
Environmental Stress Screening.
o
MN6227TIB
~I
±1 Volt
Continuous to Ground
DESIGN SPECIFICATIONS ALL UNITS (fA = + 25°C, ± Vee = ± 15V, + Vdd = + 5V unless otherwise Indicated) (Note 1)
ANALOG INPUTS
Input Impedance (Note 16): Resistance
Capacitance
TYP.
MIN.
o to
Input Voltage Ranges: MN6227
MN6228
1
Input Bias Current Over Full
Temperature Range (Note 16):
MAX.
+ 10, ± 5
±10
Volts
Volts
5
50
± 100
UNITS
Mohm
pF
±600
nA
+0.8
Volts
Volts
DIGITAL INPUTS CE, CS, RIC, A o ' 1218
Logic Levels: Logic "1"
Logic "0"
+2.4
Loading: Logic Currents
Input Capacitance (Note 16)
±1
5
±10
p.A
pF
DIGITAL OUTPUTS DBO - DB11, STS
Output Coding (Note 2): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (l.ource,,;320p.A)
Logic "0" (I.ink"; 1.6mA)
Straight Binary
Offset Binary
+2.4
+0.4
Leakage (DBO-DB11) in High·Z State
±1
Output Capacitance (Note 16)
5
±10
Volts
Volts
p.A
pF
INTERNAL REFERENCE
Reference Output (Pin 8): Voltage
Drift (Note 16)
Output Current (Notes 3, 16)
+9.9
+10
±15
+10.1
1
Volts
ppml'C
mA
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc Supplies
+ Vdd Supply
Power Supply Rejection (Note 14): + Vcc Supply
- Vcc Supply
+ Vdd Supply
5-42
± 14.5
+4.5
±15
+5
± 15.5
+5.5
-50
-50
-50
Volts
Volts
dB
dB
dB
Current Drains: + Vcc Supply
- Vcc Supply
+ Vdd Supply
+22
-34
+9
+28
-40
+15
mA
mA
rnA
Power Consumption
885
1095
mW
PERFORMANCE SPECIFICATIONS (Typical at TA = + 25°C, :!: Vcc = :!: 15V, + Vdd = + 5V unlass otherwise indicated)
MN6227J
MN6228J
MN6227K
MN6228K
MN6227S
MN6228S
MN6227T
MN6228T
UNITS
Minimum Guaranteed Sampling Rate (Note 4)
Maximum AID Conversion Time (Note 5)
33
25
33
25
33
25
33
25
kHz
"sec
Signal-to-Noise Ratio (SNR, Note 6):
Initial (+ 25"C) (Minimum)
T min to T max (Minimum, Note 7)
68
66
70
68
68
66
70
68
dB
dB
Harmonics and Spurious Noise (Note 8):
Initial (+ 25 "C) (Minimum)
T min to T max (Minimum, Note 7)
-77
-80
-77
-77
-74
-74
-80
-77
dB
dB
Input Signal Full-Scale Bandwidth (Minimum, Note 9)
16.5
16.5
16.5
16.5
kHz
Integral Linearity Error: Initial (+ 25 "C) (Maximum)
Tmin to Tmax (Maximum, Note 7)
±1
±1
±1f2
±1h
±1
±1
±1fz
± 1
LSB
LSB
Resolution for Which No Missing
Codes is Guaranteed: Initial (+ 25"C)
Tmin to Tmax (Note 7)
11
11
12
12
11
11
12
12
Bits
Bits
DYNAMIC CHARACTERISTICS
STATIC CHARACTERISTICS
Unipolar Offset Error (Notes 10, 11):
Initial (+ 25"C) (Maximum)
Drift (Maximum)
Maximum Change to Tm;n or Tma , (Notes 7, 15)
Bipolar Zero Error (Notes 10, 12):
Initial (+ 25"C) (Maximum)
Drift (Maximum)
Maximum Change to Tmin or Tma , (Notes 7,15)
±2
±10
±2
±2
±5
±1
±2
±10
±4
±2
±5
±2
LSB
ppm of FSR/"C
LSB
±4
±15
±3
±4
±10
±2
:!:4
±15
±6
±4
± 10
±4
LSB
ppm of FSR/"C
LSB
Full Scale Accuracy Error (Notes 10, 13):
Initial (+ 25"C) (Maximum)
Tm;n to Tmax Without Initial Adjustment
Tmln to Tmax With Initial Adjustment
Drift (Maximum)
Maximum Change to Tm;n or Tma , (Notes 7,15)
±0.2
±0.4
±0.2
±50
±10
±0.1
±0.2
±0.1
±25
±5
±0.2
±0.7
±0.5
±50
±20
±0.1
±0.4
±0.3
±25
±10
%FSR
%FSR
%FSR
ppm of FSR/"C
LSB
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data
12. Bipolar zero error is defined as the difference between the ideal and the
sheet.
2. See table of transition voltages in section labeled Digital Output Coding.
actual input voltage at which the digital output just changes from 0111
1111 1111 to 1000 0000 0000 when operating the MN6227/6228 on a
3. If the internal reference is used to drive an external load, the load should
not change during a conversion.
4. Minimum guaranteed sampling rate refers to the fact that these devices
guarantee all other performance specs while sampling and digitizing at a
bipolar range. The ideal value at which this transition should occur is
- 'h LSB. See Digital Output Coding. Listed specs assume fixed 500
resistors between Ref Out (pin 8) and Ref In (pin 10) and between Ref Out
(pin 8) and Bipolar Offset (pin 12).
33kHz rate. Obviously, devices may be operated at lower sampling frequencies If desired and typically will meet all performance specs while
sampling at rates of 40kHz or higher.
5. Whenever the Status Output (pin 28) is low (logic "0"), the internal T/H is
in the track mode and the AID converter is not converting. When Status is
high (the definition of AID conversion time), the TIH is In the hold mode,
and the AID is performing a conversion.
13. Full scale accuracy specifications apply at positive full scale for unipolar
input ranges and at both positive and negative full scale for bipolar input
ranges. Full scale accuracy error Is defined as the difference between the
6. This parameter represents the rms-signaHo-rms-noise ratio in the output
spectrum (excluding harmonics) with a full-scale input sine wave (Odb) at
ideally occurs at an input voltage 1% LS8's below the nominal positive full
scale voltage. The latter ideally occurs 1/2 LSB above the nominal negative
any frequency up to 16.5kHz.
7. MN6227J, K and MN6228J, K are fully specified for O"C to + 70"C operation. MN6227S, SIB, T, TIB and MN6228S, SIB, T, TlB are fully specified for
- 55°C to + 125"C operation.
full scale voltage. See Digital Output Coding. Listed specs assume fixed
500 resistors between Ref Out (pin 8) and Ref In (pin 10) and between Ref
Out (pin 8) and Bipolar Offset (pin 12).
8. This parameter represents the peak signal to peak non·fundamental component (harmonic or spurious, inband or out of band) in the output
spectrum.
9. This is the highest-frequency, full-scale, input signal for which the SNR
and harmonic figures are guaranteed when sampling at a 33kHz rate.
10. Adjustable to zero with external potentiometer.
11. Unipolar offset error is defined as the difference between the ideal and the
actual input voltage at which the digital output just changes from 0000
00000000 to 0000 0000 0001 when operating the MN6227 on its unipolar
range. The ideal value at which this transition should occur is
ideal and the actual input voltage at which the digital output just changes
from 1111 1111 1110 to 1111 1111 1111 for unipolar and bipolar input
ranges. Additionally, it describes the accuracy of the 0000 0000 0000 to
0000 0000 0001 transition for bipolar input ranges. The former transition
14. Power supply rejection is defined as the change in the analog input
voitageatwhichthe111111111110tolll111t11111 or 0000 0000 0000 to
0000 0000 0001 output transitions occur versus a change in power-supply
voltage.
15. Listed maximum change specifications for unipolar offset, bipolar zero
and full-scale accuracy correspond to the maximum change from the in·
itial value (+ 25 DC) to the value at Tmin or T max.
16. These parameters are listed for reference only and are not tested.
+ % LS8.
See Digital Output Coding.
Specifications subject to change without notice as Micro Networks reserves
the right to make improvements and changes in its products.
CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.
Unipolar
Bipolar
Specified
Temperature
Range
No Missing
Codas
Integral
Linearity
Minimum
Sampling
Rate
Minimum
Input
Bandwidth
SNR
Harmonics
MN6227J
Oto +10V
±5V
O'Cto +70'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6227K
Oto +10V
±5V
O'Cto +70'C
12 Bits
± V. LSB
33kHz
16.5kHz
70dB
-80dB
MN6227S
Oto +10V
±5V
-55'C to + 125'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6227S/B
Oto +10V
±5V
-55'Cto + 125'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6227T
Oto +10V
±5V
-55'C 10 + 125'C
12Blls
± V2 LSB
33kHz
16.5kHz
70dB
-BOdB
MN6227T/B
010 +10V
±5V
-55'Cto +125'C
12 Bils
± V. LSB
33kHz
16.5kHz
70dB
-80dB
MN6228J
N.A.
±10V
O'C to + 70'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6228K
N.A.
±10V
O'C to + 70'C
12 Bits
± V. LSB
33kHz
16.5kHz
70dB
-80dB
MN6228S
N.A.
±10V -55'C to + 125'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6228S/B
N.A.
±10V -55'Cto +125'C
11 Bits
±1 LSB
33kHz
16.5kHz
68dB
-77dB
MN6228T
N.A.
±10V -55'C to + 125'C
12 Bits
± V2 LSB
33kHz
16.5kHz
70dB
-BOdB
MN6228T/B
N.A.
±10V - 55'C to + 125'C
12 Bits
± V2 LSB
33kHz
16.5kHz
70dB
-BOdB
Part
Number
Input Voltage Range
BLOCK DIAGRAM
+ 5'11 Supply \1} ( } - - -
Chip Select
Byte Address
[==r==5~U~CC;E;55~'V;E==:==L---o
0---
Data Mode Select 1218 (2)
CS (3\
(28) Status Output
APPROXIMATION REGISTER
----0 (27)
1.0 (4)
DB11 (MSB)
(26) 0810 (Bil 2)
(25) 089(8113)
(24)088(8114)
Read/Convert RIC (5)
Chip Enable CE (6)
+ 15V Supply (7) 0 - -
+ tOV
Ret Oul (8)
Analog GrQund (9)
+ la'll Rei
0--8
---0
0-----
(23) DB7 (Bit 5)
(22) DBe (Bit 6)
(21) 085(8117)
(20) DB4 (Bit 8)
(19) DB3(8it9)
(18) DB2 (Bit 10)
(17) OBI (Bit 11)
(16) DBO (LSB)
19.95kO
In (IO)
---0
0---------1
12 BIT
OIA CONVERTER
---0
(15) Digital Ground
a---.
'-----,-----'
Bipolar Olfsel (12) o-_ _ _ _-""'.,,;;;'O'--_ _ _ _+----1
-15V Supply (11)
la'll Input (MN6227) (13)
20V Input (MN6228) (14)
" -_ _-<1_-<
Status
Nole: Pin 14 is a "No Connect" on the MN6227
Pin 131s a "No Connect" on the MN6228
PIN DESIGNATIONS
•
28
14
15
PIN 1
544
(1) + 5V Supply ( + Vdd)
(2) ·Data Mode Select 12iii
(3) Chip Select CS
(4) Byte Address Ao
(5) Read/Convert RIC
(6) Chip Enable CE
(7) + 15V Supply (+ Vcd
(B) +10V Ref Out
(9) Analog Ground
(10) + 10V Ref In
(11) - 15V Supply ( - Vcd
(12) Bipolar Offset
(13) Analog Input MN6227 (N.C. MN6228)
(14) Analog Input MN6228 (N.C. MN6227)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
Status Output
DB11 (MSB)
DB10 (Bit 2)
DB9(Bit 3)
DBB (Bit 4)
DB7 (Bit 5)
DB6 (Bit 6)
DB5 (Bit 7)
DB4 (Bit 8)
DB3 (Bit 9)
DB2 (Bit 10)
DB1 (Bit 11)
DBO (LSB)
Digital Ground
DESCRIPTION OF OPERATION
MN6227 and MN6228 are complete, 12-bit AID converters
with internal microprocessor-interface logic and internal
track-hold (T/H) amplifiers_ They have been designed to
repetitively sample and digitize dynamically changing input
signals in DSP-type applications. The AID-converter sections of these devices employ the successiveapproximation (SA) conversion technique, and AID's of this
type, while offering excellent tradeoffs in terms of speed,
resolution, and power consumption, are nortoriously poor in
their ability to accurately convert dynamically changing
(slewing) analog-input signals. In fact, the AID converter
section of the MN6227/6228 has a 25!,sec conversion time,
and if it did not have a T/H, it would be effectively incapable
of accurately digitizing a Signal slewing more than ± V. LSB
during that period. This corresponds to an input slew-rate
limit of ± 0.098mV/!,sec (for adevice with a ± 10V input range)
or a full-scale, sinusoidal, input bandwidth of 1.56Hz. The input bandwidth of MN6227/6228 is increased more than 4
orders of magnitude by its internal T/H amp. When these
converters are commanded to perform a conversion, the TlH
instantaneously "freezes" the input signal and holds it constant while the AID converter performs a conversion.
The T/H is configured in such a manner as to be transparent
to the user. A high-impedance input buffer isolates it from
the external signal source, and its output is internally connected directly to the AID. Its operational state is controlled
by the AID in the sense that whenever the AID is performing
a conversion (Status Line = "1 "), the T/H is driven into its
hold mode, and when the AID is between conversions
(Status Line = "0"), the T/H is in its track (signal acquistion)
mode.
In most applications, MN6227/6228 will require only power
supplies, bypass capacitors, and two fixed resistors to provide the complete sampling/conversion function. The completeness of the device makes it most convenient to think of
MN6227/6228 as a function block with specific input/output
and transfer characteristics, and it is quite unnecessary to
concern oneself with its inner workings.
Operating MN6227/6228 under microprocessor control (it
also functions as a stand-alone AID) will consist, in most applications, of a series of read and write operations. Initiating
a conversion involves sending a command from the processor to the AID and is essentially a write operation.
Retrieving digital output data is accomplished with read
operations. Once the proper signals have been received and
a conversion has begun, it cannot be stopped or restarted,
and digital output data is not available until the conversion
has been completed. Immediately following the initiation of
a conversion cycle, the MN6227/6228's Status Line (also
called Busy Line or End of Conversion (E.O.C.)) will rise to a
logic "1" indicating that a conversion is in progress. At the
end of a conversion, the internal control logic will drop the
Status Line to a "0" and enable internal circuitry to permit
output data to be read by external command. By sensing the
state of the Status Line or by waiting an appropriate amount
of time, the microprocessor will know when the conversion
is complete and that output data is valid and can be read.
If MN6227/6228 is to be operated with 12-bit or greater
microprocessors, all 12 output bits can be 3-state enabled
simultaneously permitting data collection with a single read
operation. If MN6227/6228 is operated with an 8-bit !,P, output data can be formatted to be read in two 8-bit bytes. The
first will contain the 8 most significant bits (MSB's). The
second will contain the remaining 4 least significant bits
(LSB's) in a left justified format with 4 trailing "O's".
MN6227/6228 TIMING
-1nL.____..JnL.___
c~~~~rt ~L-_ _ _
T/H _ _ _..J
AID _ _ _..J
Output
Data
When the AID is not converting and the T/H is acquiring a
new signal, digital output data from the previous conversion
is valid and ready to be read.
MN6227/6228 are designed such that when conversions are
initiated at any rate up to 33kHz, enough time remains between the falling edge of Status and the next Start Convert
command for the T/H to fully acquire its next sample. When
the device is clocked at a 33kHz sampling rate, the T/H has
the ability to accurately acquire, track, and hold full-scale
input signals with frequency components up to 16.5kHz. In
most DSP-type applications, MN6227/6228 will be required
to repetitively sample and digitize input signals with frequencies below 16.5kHz. This will ensure that the Nyquist
criterion of sampling 2 times per period is achieved. Similarly, it ensures that the sampling (and digitizing) frequency
(33kHz) is at least 2 times the signal frequency.
THE INTERNAL T/H AMPLIFIER
As stated earlier, MN6227/6228's internal T/H amplifier is
configured in such a way as to be transparent to the user.
The T/H's output is connected directly to the input of the
AID converter, and its operational mode is controlled directly by the Status output of the AID converter. Consequently,
users of MN6227/6228 need not burden themselves with
oftentimes confusing T/H specifications like acquisition
time, aperture-delay time, aperture jitter, droop rate, etc ..
These parameters are not specified for MN6227/6228 and
are, in fact, impossible to directly test considering that the
T/H output and control lines are not accessible at the device
pins. The manner in which MN6227/6228 is specified (input
bandwidth, sampling rate, signal-to-noise ratio, harmonic
distortion, etc.) obviates the need for knowing the specific
T/H time-domain performance specifications, however, we
do supply typical values for critical T/H parameters on the
following page.
Note that the static errors (gain error, track-mode offset
error, and pedestal) of the T/H function add directly to the
corresponding errors of the AID converter but that both are
effectively nulled with the functional laser trimming of the
AID. T/H offset error and pedestal, for example, add directly
to AID-converter offset error. However, when the AID offset
is functionally laser trimmed, it is done with the whole
device sampling at a 33kHz rate and the T/H is in the hold
mode whenever trimming is actually performed. Consequently, all error sources are compensated for. All static errors on MN6227/6228 (accuracy error, unipolar offset error,
bipolar zero error, etc.) are tested and specified as full inputoutput transfer specifications and include both the T/H and
AID.
5-45
,I '
.-
Typical T/H Performance Specifications
Gain Error
Gain linearity Error
Track-Mode Output Offset Error
Pedestal
Acquisition Time: 10V step to ± 0.01 %
20V step to ± 0.01 %
Track-Hold Transient Settling (to ± 1mY)
Slew Rate
Full Power Bandwidth
Effective Aperture Delay Time
Aperture Jitter
Droop Rate
Hold-Mode Feedthrough Attenuation
~B'···································T.·············· .........•....••.................
±0.01%
±0.005%FSR
±0.5mV
±lmV
11'sec
21'sec
250nsec
± 40V/I'sec
500kHz
- 25nsec
0.5nsec
± O.ll'V/l'sec
-BOdB
FREQUENCY-DOMAIN TESTING - MN6227/6228 is
specified and tested statically in the traditional manner
(linearity, accuracy, offset error, current drains, etc.) and
dynamically in the frequency-domain. In the dynamic tests,
MN6227/6228 is operated in a manner that resembles an application as a digital spectrum analyzer. A very low distortion
signal generator (harmonics -90dB) is used to generate a
pure, full-scale, 16kHz sine wave that MN6227/6228 samples
and digitizes at a 33kHz rate. These conditions (signal period
= 62.5I'sec, sampling interval = 30l'sec) approach the Nyquist sampling limit (at least 2 samples per signal cycle;
sampling frequency greater than 2times signal frequency). A
total of 512 sample-and-convert operations are performed,
and the digital-output data is stored in a high-speed, FIFO,
buffer-memory box. The 512 data pOints are then accessed by
a microcomputer which executes a 512-point Fast Fourier
Transform (FFT) after applying a Hanning (raised cosine) window function to the data. The resulting spectrum shows the
amplitude and frequency content of the converted signal
along with any errors (noise, harmonic distortion, spurious
Signals, etc.) introduced by the AID converter. Subsequently,
signal-to-noise ratio (SNR) and harmonic distortion
measurements are read from the spectrum. A functional
block diagram of the test setup appears below, and a sample
spectrum appears above.
Mini
Computer
The spectrum above is the real portion (imaginary portions of
spectrums are discarded) of a 512-point FFT. The horizontal
axis is the frequency axis, and its rightmost end is equal to '12
the sampling rate (16.5kHz in this case). The horizontal axis is
divided into 256 frequency bins, each with a width of 64.45Hz.
Recall that the highest frequency on the frequency axis of the
spectrum of a sampled signal is equal to one-half the sampling rate and that input signals with frequencies higher than
'12 the sampling rate are effectively "undersampled" and
aliased back into the spectrum.
The vertical axis of the spectrum corresponds to signal
amplitude in rms volts relative to a full-scale sinusoidal input
signal (OdB). The sample spectrum above is the result of
averaging 10 512-point FTT's run on data taken from an
MN6227 operating on its bipolar input range (± 5V) with a fullscale input sine wave (v(t) = 5sinwt) at a frequency of 8kHz. In
the spectrum, the full-scale input signal appears at 8kHz at a
5-46
. . . . . . .•. . . . •. . . . •. . ,f.···.In~Sampl.,
F:,u:.:~ =~z
-2OdB
....
t·······································
-4OdB
Signal
RMS SIgnal: - D.38dB
t·····
RMS Noise: -72.8D
SIN: 72.21dB
- &OdS
:;::::~:
Full Scale
+ . . . . . . . . . . . . . . . . ..
t······································ •..................................................
-8OdB t·····································
.1·······················
-l00dB
-120118
-14OdB
OH,
16.SKHz
Input Frequency
level of - 0.39dB. Full-scale rms signals do not appear at
- 3dB levels because the FFT program has been normalized
to bring them to zero. The d.c. component in the spectrum is
effectively the offset error of the MN6227 combined with that
of the signal generator and test fixture. A second harmoniC, if
it were either present in the input signal or created by the
MN6227, would appear at 16kHz. If a third harmonic were present, it would be aliased back into the spectrum and appear at
9kHz. Harmonic distortion and spurious noise levels are
calculated as the ratio (in dB) of the Signal level to the
strongest harmonic or spurious (nonharmonic) signal in the
spectrum. In the sample spectrum above, the strongest harmonic is the second. It appears at a level of - 80_29dB, and
the signal to harmonics ratio is equal to 79.9dB. Rms noise is
calculated as the rms summation of all non fundamental and
nonharmonic components in the output spectrum, and SNR
is calculated as the ratio of the rms signal to the rms noise.
For the above spectrum, the normalized rms signal level is
- 0.39dB; the rms noise level is - 72.60dB and the SNR
is 72.21dB.
The term "noise" is generally used to describe what remains
in the output spectrum after all fundamental, harmonic, d.c.,
and outstanding spurious components have been removed. It
generally appears across all frequency bins at some relatively flat level sometimes referred to as the "noise floor". The
rms noise, as described above, represents the broadband
noise that would appear superimposed on the sinusoidal input signal if that signal were perfectly recreated from the
stored digital-output data. Virtually all the noise in the output
spectrum is created either by the act of digitizing or by the AID
converter itself.
In a simple, first-order analysis, the noise in the output spectrum of an AID converter can be traced to three sources. All
three of these noise sources have the potential to manifest
themselves as quasi-random relative-accuracy errors in any
single AID conversion of a static signal and subsequently, the
potential to manifest themselves as broadband noise in a
series of conversions of a dynamically changing signal. Two
of these noise sources (quantization noise and converter
noise) are effectively constant and do not change with inputsignal frequency. The third (aperture noise) usually varies
linearly as a function of input-signal frequency, basically
doubling whenever input frequency doubles.
Digitizing an analog Signal quantizes it or "rounds it off".
Digitizing or quantizing an analog signal with a 12-bit AID effectively "rounds off" the signal to one of 4096 possible
discrete levels. This rounding off produces an inherent accuracy error in that the digital output may no longer exactly
represent the analog input. If one has an ideal AID converter
with all other accuracy-error sources driven to zero, the
actual value of rounding-off error or quantization error can be
as small as zero or as large as ± '12 LSB from conversion to
conversion. In a Single conversion of a static input Signal,
Effective Resolution vs. Input Frequency
MN574A, 25p.sec, 12·Bit AID
Input Frequency:
Sampling Rate:
RMS SIgnal:
RMS Nolar.
SIN:
-2Od.
-4Od.
SIgnal
AmpiHude
Relative to
Full Seakl
Od.
Od.
Od.
2Hz
102.4Hz
-o.ISdB
-74.07dB
73.92dB
Input Frequency:
Sampling Rate:
RMS Signal:
RMS Noise:
SIN:
-2Od.
-""'.
200Hz
10.24kHz
-o.l3dB
- 5UedB
S1.13dB
-6Od.
-6Od.
-IOOe1B
-IOOe1B
-12OdB
-12OdB
- IOdB
-14OdB
-14011B
51.2HZ
OH.
-""'.
2kHz
4O.98kHz
-O.14dB
- 32.89dB
32.5SdB
-6Od.
-6Od.
- &OdB
Input Frequency:
Sampling Rate:
RUS SIgnal:
RMS Noise:
SIN:
-2Od.
OH.
2O.AlkHz
OH.
5.12kHz
Input FNquency
Input FNqu.ncy
Input FNquency
SNO
'DOd.
r--r-'--"--~-r--rr-'r-'--''--.--r--rr-.--'--,,
The three spectra above are each the result of
averaging 10 512-pt FFT's run on an MN574A type
12-bi! AID converter without a companion T/H
amplifier. The input signal frequencies are respec·
tively 2Hz, ,200Hz, and 2'kHz,. ThelA/D's conversion
time is approximately 25"sec;the sampling rates are
respectively 102.4Hz, 10.24kHz, and 40.98kHz. The
accompanying plot shows the rapid (6dB/octave)
degradation of SNR (effective resolution) with in·
creasing input frequency when SA type AID con·
verters are used to digitize dynamically changing
input signals without the aid of a T/H amplifier.
00d. ~~~--++--t--r~H--1--1--++--+--t--H~~-+--+1
BOd. r-~-+--++--r--r~H--+--f--tt--+--r--Hr-~-+--+1
roo.
r--r~~~--t--+--rr--r-~-+f--+--+--+r--r-+--~
00d. r-~-+--++--r--r~r.r-+--f--tt--+--r--H--~-+--+1
6Od. r-~-+--++--r--r~H-~~+--t+--+--r--H--+--+--+1
ODd. ~~~--++--t--r~H--1--1--++--+--t--H~~-+--+1
2Od. ~~~--++--t--r~H--1--1--++--+--t-~~1--+--+1
'Od.
~~~--++--t--r~H-~--1--++--+--t--H~~-+--+1
B 10
20
40
80 100 200
400 800 lk
2k
4k
8k 10k 20k
40k 80k lOOk
Input Frequency (Hz)
Effective Resolution vs. Input Frequency
MN6227, 33kHz, 12·Bit, Sampling AID
Od.
Od.
Input Frequency:
Sampling Rate:
RMS mgnal:
AMS Noise:
SIN:
-2Od.
-""'.
Signal
Amplitude
Relative to
Full Scale
2Hz
102.4Hz
- G.23dB
- 73.02dB
72.79dB
-2OdB
OdS
Input Frequency:
Sampling Rate:
RMS Signal:
RMS Noise:
SIN:
10kHz
33kHz
- O.2tdB
73.37dB
-6Od.
-4Od.
-6Od.
-BOd.
-BOd.
-BOd.
-100dB
-tOOdB
-tOOelB
-12Oc1B
-12OdB
-12OdB
-14Od8
-14OdB
.,.....
-14OdB
OH.
Input Frequency:
Sampling Rate:
AMS Signal:
RMS Noise:
SIN:
-2Od.
-4OdB
18kHz
33kHz
- O.2&lB
- 73.84dB
73.38dB
-6Od.
OH.
16.87kHz
Input Frequency
Input Frequency
OH.
16.87kHz
Input frequency
.NO
'DOd.
00d.
..
BOd.
roo.
BOd.
SOd.
4Od.
3Od.
2Od.
,Od.
Od.
810
20
40
80100 200
400 BOO lk
2k
4k
Bk 10k 20k
The three spectra above are each the result of
averaging 10 512-pt FFT's run on an MN622712-bit
sampling AID. The input signal frequencies are
respectively 2Hz, 10kHz, and 16kHz, and the
sample/convert rates are respectively 102.4Hz,
33.33kHz, and 33.33kHz. The accompanying plot
shows that MN6227's internal T/H amplifier enables
the device to maintain near ideal SNR independent
of increasing input frequencies. The aperture jitterof
the T/H is small enough to maintain SNR for under·
sampled input frequencies, i.e., for frequencies
greater than 16.5kHz.
40k 10k 100k
Input Frequency (Hz)
5-47
quantization error is simply an accuracy error. It is Impossible
for a given conversion of an unknown signal to be more accurate than ± V. LSB. In a series of conversions of a
dynamically changing signal, actual instantaneous quantization error varies from sample to sample and manifests itself
as broadband noise. In the output spectrum, this noise limits
the theoretically achievable signal-to-noise ratio to the
following:
Ideal SNR
= (6.02n +
1.76)dB
n = number of bits
For an ideal 12-bit AID, the theoretical noise floor in a
512-point FFT occurs around - 98dB, and the theoretical
SNR is 74dB. For an ideal 11-bit AID and a 512-point FFT, the
numbers are - 92dB and 68dB respectively.
The second type of single-conversion accuracy error that
manifests itself as broadband noise in the output spectrum
results from the actual noise of the AID converter. This "converter noise" is frequently referred to as "transition noise"
and manifests itself, among other ways, by allowing certain
fixed, static, input Signals to produce either of two adjacent
output codes from one conversion to the next. In most AID
converters, the transition from one given digital output code
to the next (or vice versa) does not always occur at exactly the
same analog input voltage. The "transition voltage" varies
from conversion to conversion, and this "transition noise"
(the band of adjacent-code uncertainty) is normally on the
order of ± 1/10 to ± 1/3 LSB.lt is caused by broadband noise
and timing jitter in the AID's constituent components
(especially its comparator and reference circuit). In a single
given AID conversion, transition noise adds (or subtracts) to
the device's static differential linearity error. Again, this
phenomenon will manifest itself as an accuracy error in any
single conversion and as noise in any series of conversions of
a changing input signal.
This second noise component should be thought of simply as
the "converter noise". Recall that quantization noise is a
result of the digitizing process, and it limits SNR to some
theoretical value. Its effect is independent of the type or kind
of AID converter used. Converter noise is a function of how
"noisy" a selected AID converter may be, and it reduces actual measured SNR's to a level something below ideal. Hence
MN6227/6228 guarantees 70dB and not 74dB initial roomtemperature SNR.
The third component of AID converter noise derives from the
fact that SA type AID converters (without companion T/H
amplifiers) cannot accurately convert dynamically changing
input signals. Because of the nature of the technique of successive approximations, it is imperative that AID's using this
technique maintain a stable input signal during their conversion (aperture) time. Slew rates in excess of (± V. LSB) I (conversion time) can cause accuracy errors in any individual conversion. In a series of conversions of a sinusoidal Signal, the
slew rate varies from sample to sample, and the consequent
aperture (slew-rate) errors manifest themselves as broadband noise.
This third component of AID noise is effectively eliminated by
MN6227/6228's internal T/H. The T/H's ability to instantaneously freeze the slewing input Signal (limited only by the
T/H's aperture jitter) and hold it constant results in the AID
seeing a series of d.c. signals and not the sinusoid itself.
MN6227/6228's ability to maintain SNR over its full input
bandwidth (up to the "Nyquist frequency" or V. the sampling
rate) is the result of the T/H's ability to limit the overall noise
to the quantization noise plus the noise inherent in the AID.
5-48
The plots on the previous page demonstrate that an AID
without a'companion T/H is effectively incapable of accurately converting analog input signals above some critical frequency (slew rate) and that the AID's SNR or "effective resolution" deteriorates at approximately 6dB/octave above that
frequency. Basically, the AID's quantization and converter
noise remain constant while its aperture noise doubles each
time the input frequency doubles.
MN6227/6228's internal T/H effectively eliminates aperture
noise allowing the AID to maintain "low-frequency SNR" as
the actual input frequency increases.
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS AND GROUNDING-Proper attention to layout and decoupling is necessary to obtain
specified accuracy from the MN6227/6228. It is critically important that the device's power supplies be filtered, wellregulated, and free from high-frequency noise. Use of noisy
supplies may cause unstable output codes to be generated.
Switching power supplies are not recommended for circuits
attempting to achieve 12-bit accuracy unless great care is
used in filtering any switching spikes present in the output.
Decoupling capacitors should be used on all power-supply
pins; the + 5V supply decoupling capacitor should be connected directly from pin 1 to pin 15 (Digital Ground) and the
+ Vee and - Vee pins should be decoupled directly to pin 9
(Analog Ground). Suitable decoupling capacitors are 1/LF
tantalum type in parallel with a 0.1/LF ceramic discs.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pickup. Pins 10 (Reference In),
12 (Bipolar Offset), and 13 and 14 (Analog Inputs) are particularly noise susceptible. Circuit layout should attempt to
locate the MN6227/6228 and associated analog-input circuitry as far as possible from logic circuitry. The use of wirewrap circuit construction is not recommended. Careful
printed-circuit construction is preferred. If external offset
and gain adjust potentiometers are used, the pots and
associated series resistors should be located as close to
MN6227/6228 as possible. If no trim adjusting IS required
and fixed resistors are used, they likewise should be as
close as possible.
Analog (pin 9) and Digital (pin 15) Ground pins are not connected to each other internal to MN6227/6228. They must be
tied together as close to the unit as possible and both connected to system analog ground, preferably through a large
analog ground plane beneath the package. If these commons must be run separately, a non polarized 0.01/LF
ceramic bypass capacitor should be connected between
pins 9 and 15 as close to the unit as possible and wide conductor runs employed. Pin 9 (Analog Ground) is the ground
reference point for MN6227/6228's internal reference. It
should be connected as close as possible to the analog input signal reference point.
POWER SUPPLY DECOUPLING
Pin 1 ~'--T+5V
I_F
Pin 15
0
T
I
O.o1_F
-
Digital
Ground
CONTROL FUNCTIONS-Operating MN6227/6228 under
microprocessor control is most easily understood by examining the assorted control·line functions in a truth table.
Table 1 below is a summary of MN6227/6228 control-line
functions. Table 2 is the control· line Truth Table.
Table 1: MN6227/6228 Control Line Functions
Table 2: MN6227/6228 Truth Table
CONTROL INPUTS
CS
RIC
12/8
A,
a
x
x
x
X
X
1
X
X
X
No Operation
1
1-0
X
a
Initiates 12-Bit Conversion
1-0
X
1
Initiates 8-Bit Conversion
a
Initiates 12-Bit Conversion
X
1
Initiates 8-Bit Conversion
1
1-0
a
a
a
X
0-1
a
a
a
a
X
a
Initiates 12-Bit Conversion
1
1-0
0
X
1
Initiates 8-Bit Conversion
1
a
1
1
X
Enables 12-Bit Parallel
Output
1
a
a
1
a
a
a
Enables 8 MSB's
1
Enables 4 LS8's and
4 Trailing Zeros
1
Pin
Designation
CE (Pin 6)
CS (Pin
3)
R/C (Pin 5)
AD (Pin 4)
12/8 (Pin 2)
0-1
Definition
Chip Enable
(active high)
Function
Must be high ("1") to
either initiate a conver·
sion or read output data.
0- 1 edge may be used
to initiate a conversion.
Chip Select
(active low)
Must be low ("0") to
either initiate a conver·
sion or read output data.
1 - 0 edge may be used
to initiate a conversion.
Read/Convert
("1"= read)
("0" = convert)
Must be low ("0") to
initiate either 8 or 12·bit
conversions. 1-0 edge
may be used to initiate a
conversion. Must be high
("I") to read output data.
0-1 edge may be used
to initiate a read
operation.
MN6227/6228 OPERATION
CE
1
1
No Operation
TABLE 1, TABLE 2 NOTES:
1. "1" indicates TIL logic high (2.4V minimum).
2. "0" indicates TIL logic zero (0.8V maximum).
3. X indicates "don't care",
4.0-1,1-0 indicate logic transitions (edges).
5. Output data format is as follows:
MSB
xxxx
xxxx
xxxx
High
Bits
Middle
Bits
Low
Bits
8 MSB's
LSB
4LSB's
Byte Address
Short Cycle
In the start·convert
mode, AD selects 8-bit
(AD = "1 ") or 12·bit
(AD = "0") conversion
mode. When reading out·
put data in 2 8·bit bytes,
AD = "0" accesses 8
MSB's (high byte) and
Ao= "I" accesses 4
LSB's and trailing "0'5"
(low byte).
When initiating a conversion, the signal applied to AD (Byte
Address/Short Cycle, Pin 4) determines whether a 12·bit con·
version is initiated (Ao = "0") or an 8-bit conversion is initiated (Ao = "1"). It is the combination of CE = "1", CS = "0",
R/C = "0" and Ao = "1" or "0" that initiates a convert operation, and the actual conversion can be initiated by the rising
edge of CE, the falling edge of CS or the falling edge of R/C
as shown in the Truth Table and as described below in the
section labeled Timing·lnitiating Conversions. When initiating conversions, the 12~ line is a "don't care".
Data Mode
Select
("1"= 12 bits)
("0" = 8 bits)
When re~ding output
data, 12/8 = "1" enables
all 12 output bits simulta·
neously. 12/8= "0" will
enable the MSB's or
LSB's as determined by
the AD line.
When reading digital output data from MN6227/6228, CE and CS
must be asserted, and the signals applied to 12/8 and Ao will ELeter·
mine the format of output data. Logic "1" applied to the RIC line
will initiate actual output data access. lithe 1218 line is a "1", all 12
output data bits will be accessed simultaneously when the RIC line
goes from a "0" to a "1".
Unless Chip Enable (CE, Pin 6, logic "1" = active) and Chip
Select (CS, Pin 3, logic "0" = active) are both asserted,
various combinations of logic signals applied to other con·
trol lines (R/~, 12/8, and AD) will have no effect on
MN6227/6228 operation. When CE and C'S are both
asserted; the signal applied to RiC (Read/Convert, Pin 5)
determines whether a data read (R/~ = "1") or a convert
operation (R/C; = "0") is initiated.
If the 12/8 line is a "0", output data will be accessible as two 8-bit
bytes as described below in the section labeled Timing-Reading
Output Data. In this situation, Ao="O" will result in the 8 MSB's being accessed and An="1" will result in the 4 LSB's and 4 trailing
zeros being accessed. In this mode, only the 8 upper bits or the 4
lower bits can be enabled at one time, as addressed by An. For these
applications, the 4 LSB's (pins 16-19) should be hardwired to the
4 MSB's (pins 24-27). Thus, during a read, when An is low, the upper 8 bits are enabled and present data on pins 20 though 27. When
An goes high, the upper 8 data bits are disabled, the 4 LSB's then
present data to pins 24 to 27, and the 4 middle bits are overridden
so that zeros are presented to pins 20 through 23.
5-49
TIMING-INITIATING CONVERSIONS-It is the combination of CE="1", ~="O", R/C="O" and A,="1" (initiate
a-bit conversion) or A, = "0" (initiate 12-bit conversion) that
initiates a convert operation. As stated earlier, the actual
conversion can be initiated by the risinILedge of CE, the faIling edge of ~ or the falling edge of RIC. The A, line should
be stable immediately prior to whichever of the above transitions is used to initiate a conversion. The RIC transition is
normally used to initiate conversions in stand-alone operation, and it is not recommended to use this line to initiate
conversion in p.P applications. If RIC is high just prior to a
conversion, there will be a momentary enabling of output
data as if a read operation were occuring, and the result
could be system bus contention. In most applications, A,
should be stable and RIC low before either CE or CS is used
to initiate a conversion.
Timing for a typical application is shown below. In this application ~ is brought low, RIC is brought low, and A, is set
to its chosen value prior to CE becoming a "1". This sequence can be accomplished in a number of ways including
connecting ~ and A, to address bus lines, connecting RIC
to a readlwrite line (or its equivalent) and generating a CE
0-1 transition using the system clock. In this example CS
should be a "0" 50nsec prior to the CE transition
(tssc = 50nsec min), RIC should be a "0" 50nsec prior to the
CE transition (tsRc = 50nsec min), and A, should be stable
Onsec prior to the CE transition (tSAC = Onsec min). The
minimum pulse width for CE = "1" is 50nsec (tHEC = 50nsec
min) and both ~ and RIC must be valid for at least 50nsec
while CE = "1" (tHSC and tHRC = 50nsec min) to effectively initiate the conversion. A, must be valid for at least 50nsec
(t HAC = 50nsec min) while CE is high to effectively initiate
the conversion. The Status Line rises to a "1" no more than
200nsec after the rising edge of CEo (tDSC = 200nsec max).
Once the Status = "1", additional convert commands will be
ignored until the conversion is complete.
TIMING-RETRIEVING DATA-The combination of
CE = "1 ", CS = "0", and RIC = "1" is required to access
digital output data. If the above combination of control
signals is met and the 12/8 line has a "1" applied, all twelve
output bits will become valid simultaneously. If the 12i81ine
has a "0" applied, output data is formatted for an a-bit data
bus, and the a MSB's will become valid when the above condition is met with A, = "0" while the a LSB's (4 data bits and
4 trailing "D's") will become valid whenever A,="1". Data
access can be initiated by either the rising edge of CE or the
falling edge of CS.
Timing for a typical application is shown below. In this application,
CS is brought low, An is set to its final state, and RIC is brought high
all before the rising edge of CEo CS and Ao should be valid 50nsec
prior to CE (tSSR =50nsec min, tSAR =50nsec min). RIC can
become valid the same time as CE (tSRR =Onsec min). In the a-bit
bus interface mode (12/8="0"), An must be stable at least 50nsec
prior to CE going high. An may be toggled at anytime without
damage to the converter. Break-belore-make action is guaranteed
between the two data bytes, which assures that the outputs strapped together in a-bit bus applications will never be enabled at the
same time.
Access time is measured from the pOint where CE and RIC
are both high (assuming CS is already low).
CE
RIC
RIC
tSAR
A.
OB..
~s----------~------+------------
::~,-Hi9h--+--k~L"J
-,-. !:H! lig! !h____+-__-{I-~~__I
OBt-DB" __
Impedance
Impedance
tDo
Read Cycle Timing
Convert Start Timing
MN6227/6228 TIMING SPECIFICATIONS:
CONVERT MODE
Symbol Parameter
Min
STS Delay lrom CE
tosc
CE Pulse Width
50
tHEC
CS 10 CE Selup
50
IssC
Max
200
50
Typ
100
30
20
20
0
20
0
20
15
10
13
20
17
25
tHsc
~ Low During CE High
50
ISAC
IHAC
tSAc
IHAC
Ic
RIC 10 CE Setup
RIC Low During CE High
50
50
0
5-50
A. 10 CE Selup
A. Valid During CE High
Conversion Time
8·Bil Cycle
12·Bit Cycle
Units
ns
ns
ns
ns
ns
ns
ns
ns
_s
_s
MN6227/6228 TIMING SPECIFICATIONS:
READ MODE
Symbol Parameter
Access Time (from CE)
too
Dala Valid after CE Low
IHD
Oulput Float Delay
tHl
CS to CE Setup
tSSA
RIC to CE Setup
tSAA
A. to CE Setup
tSAA
CS Valid After CE Low
tHSR
RIC High After CE Low
tHRR
A. Valid After CE Low
tHAR
Min
25
50
0
50
0
0
50
Typ
75
35
100
0
0
25
0
0
25
Max
150
150
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
HARDWIRING TO 8-BIT DATA BUSES-For applications
with 8-bit data buses, output lines OB4-0B11 (pins 20-27)
should be connected directly to data bus lines 0 0-0,. In addition, output lines OBO-OB3 (pins 16-19) should be connected
to data bus lines 0,-0, or to MN6227/6228 output lines OB8OB11. Thus, if Ao is low during a read operation, the upper 8
bits are enabled and become valid on output pins 20-27.
When Ao is high during a read operation, the 4 LSB's are
enabled on output pirfS 16-19 and the 4 middle bits (pins
20-23) are overridden with "a's".
High Byte (Ao = 0)
Low Byte (Ao= 1)
0,
0,
0,
D.
0,
0,
0,
Do
MSB DB10 DB9 DBB DB7 DB6 DB5 DB4
a
a
a
DB3 DB2 DB1 DBa a
2 1218
Status 28
3Cs
4 A,
MN6227/6226 bipolar oparation
with trim adjustment.
5 RIC
Bits
Analog
Inputs
MN6227/6228
0,
0,
0,
0,
0,
0,
0,
0,
27(MSB)
26(DB10)
25 (DB9)
24(DB8)
23 (DB7)
22 (DB6)
21 (DB5)
20 (DB4)
19 (DB3)
18 (OB2)
MN6227/6226 bipolar operation
without trim adjustment. 500
resistors should be ~ 1 ufo
metal 111m.
-
16 (LSB)
Hardwiring for 8·Bil Dala Buses
Status 28
3CS
High
4 A,
5 RIC
6 CE
-
17 (DB1)
2 12/8
CJl
::J
R,
m
~0
10 Relln
50!!
50!!
Analog
Inputs
_
Unipolar offset error refers to the accuracy of the 0000 0000
0000 to 0000 0000 0001 digital output transition (see Digital
Output Coding). If offset adjustment is not used, this transition will occur within ± 2 LSB's of its actual ideal value
(+ v. LSB). For the 10V range, 1 LSB = 2.44mV. To offset adjust, apply an analog input equal to + V, LSB and with the
MN6227 continuously converting, adjust the offset potentiometer "down" until the digital output is all "a's" and then
adjust "up" until the LSB just changes from a "0" to a "1".
The offset adjust circuit has a range of approximately
± 15mV, and different offsets can be set for different
system requirements.
Unipolar gain error can be defined as the accuracy of the
1111 1111 1110 to 1111 1111 1111 digital output transition
after unipolar offset adjustment has been accomplished.
Ideally, this transition should occur 1V, LSB's below the
nominal full scale of the selected input range. This voltage
is + 9.9963V for the 10V unipolar input range. Gain trimming
is accomplished by applying this voltage and adjusting the
gain potentiometer "up" until the digital outputs are all
"1's" and then adjusting down until the LSB just changes
from a "1" to a "0".
MN6227 unipolar operation
with trim adjustment.
.5V
1
+ 15V
7
14 ± tOV Range
-15V 11
2 12ia
R,
100'
-- Vee
lS
19
13 ± 5V Range
9 AnaGnd
UNIPOLAR OPERATION AND CALIBRATION-Analog input
connections and calibration circuits for the unipolar
operating mode is shown below. When the a to + 10V input
range is used, apply the analog input to pin 13 of the
MN6227. If gain adjustment is not used, replace trim pot R,
with a fixed 500 ± 1 % metal-film resistor to meet all
published specifications. If unipolar offset adjustment is
not used, connect pin 12 (Bipolar Offset) directly to pin 9
(Analog Ground).
Low
Bits
12 SIP Otf
0----
0--
24
27
Middle 20
Bits
23
8 RetOul
R,
:,.
Bits
o----.Vf"'--< + Vee
Status 28
High
24
4 A,
Bits
27
5 RIC
Middle 20
Bits
23
6 CE
10 Ref In
100k
DlgGnd 15
._.. 11'
~~t~ ~: ~_)
8 RefOul
tOO!!
~~''\.'\."-'-
Analog
Input
_ _--1
12 SiP Ofl
13 + lOV Range
~
+5V
1
+ 15V
7
-15V 11
I
L _'_A_"_G_'d_ _O_'9_G_'d_15---,
MN6227 unipolar operation
without trim adjustment.
2 12/8
Status 28
3CS
High
Bits
, A,
5 RIC
6 CE
A,
10 Refln
50!!
~
1
24
27
Middle 20
Bits
23
Low
Bits
lS
19
8 Ref Out
12 BlpOIl
If a 10.24V ( 2.5mV/bit) input range is required, the gain trim
pot (R,) should be replaced with a fixed 500 resistor, and a
2000 trim pot inserted in series with the analog input to pin
13. Offset trimming proceeds the same. Gain trimming is
now accomplished with the new pots.
Analog
Input
13 + 10V Range
+5V
1
+ 15V
7
-15V 11
9 Ana Gnd
DigGnd 15
5-51
BIPOLAR OPERATION AND CALIBRATION-Analog input
connections and calibration circuits for the bipolar
operating modes are shown on the previous page. If the
± 5V input range is to be used on MN6227, apply the analog
input to pin 13. If the ± 10V range is to be used on MN6228,
apply the analog input to pin 14. If either bipolar offset or
bipolar gain adjustment are not to be used, the trim pots R,
and R2 can be replaced with fixed 500 ± 1 % metal-film
resistors to meet all published specifications.
Bipolar zero error refers to the accuracy of the 0111 1111
1111 to 10000000 0000 digital output transition (see Digital
Output Coding). Ideally, this transition is supposed to occur
'12 LSB below zero volts, and if bipolar offset adjustment is
not used, the actual transition will occur within the
specified limit of its ideal value. Offset adjusting on the
bipolar device is performed not at the zero crossing point
but at the minus full scale point. The procedure is to apply
STAND·ALONE OPERATION
The MN6227/6228 can be used in a "stand-alone"'mode in
systems having dedicated input ports and not requiring full
bus interface capability. In this mode, CE and 12/8 are tied
to logic "1", CS and A. are tied to logic "0", and the conversion is controlled by RfC_ A conversion is initiated when RIC
is brought low, and all 12 bits of the three-state output buffers are enabled when RIC is brought high. This gives rise to
two possible modes of operation; conversions can be initiated with either positive or negative RIC pulses. The timing diagram below details operation with a negative start
pulse. In this case, the outputs are forced into the highimpedance state in response to the falling edge of RIC and
return to valid logic levels after the conversion cycle is com-:
an analog input equal to - FS + '12 LSB (- 4.9988V for the
± 5V range, - 9.9976V for the ± 10V range) and adjust the
bipolar offset trim pot "down" until the digital output is all
"O's". Then adjust "up" until the LSB just changes from "0"
to a "1",
Bipolar gain error can be defined as the accuracy of the
1111 1111 1110 to 1111 1111 1111 digital output transition
after bipolar offset adjustment has been accomplished.
Ideally, this transition should occur 1'/2 LSB's below the
nominal positive full scale value of the selected input range.
This voltage is + 4.9963V and + 9.9927V respectively for the
± 5V and ± 10V bipolar input ranges. Gain trimming is accomplished by applying either of these voltages and adjusting the gain trim pot "up" until the digital outputs are all
"1's" and then adjusting "down" until the LSB just changes
from a "1" to a "0".
pleted. The Status line goes high 200ns after RIC goes low
and returns low 300ns after data is valid.
The timing diagram below details operation with a positive
start pulse, Output data lines are enabled during the time
RIC is high. The falling edge of RIC starts the next conversion and the data lines return to three-state (and remain
three-state) until the next rising edge of RIG.
R/C~ _ _
tDDR
tHRL~
,>-,_ _ _ _ _ _
R/C~
~-
DB,· DB"
1 Ar---------L
I-I
nl::l
~.
I.---
te
---1
-1
DB~'
~ tHOR
te
---I
-----{~>-----"'f-----~
STAND·ALONE MODE TIMING
Symbol Parameter
t
tHRl
~-HS
tDS
/, Data
tHOR
"~~valld
,
l-1
High Pulse for RIC-Oulputs Enabled While RIC High, Otherwise High·Z
tos1
STS - - - - - " - - - - - J
tHDR-I
tr"tL-
STS
t HS
,L-_ __
tHRH
tDDR
low Pulse for RIC-Outputs Enabled After Conversion
Low RIC Pulse Width
STS Delay from RIC
Data Vand After RIC Low
STS Delay Alter Data Valid
High RIC Pulse Width
Data Access Time
Min
Typ
Max
50
200
25
300
150
500
1000
150
Units
ns
ns
ns
ns
ns
ns
DIGITAL OUTPUT CODING
ANALOG INPUT VOLTAGE (Volts)
o to
+ 10V
±5V
± 10V
5.0012
4.9988
4.9963
+ 5.0000
+ 4.9963
+ 0.0012
+ 10.0000
+ 9.9927
+ 0.0024
- 0.0012
- 0.0037
-
0.0012
0.0000
- 4.9988
- 5.0000
- 9.9976
-10.0000
+ 10.0000
+ 9.9963
+
+
+
+
0.0024
0.0073
DIGITAL OUTPUT
MSB
LSB
111111111111
11111111111~'
1000 0000 OOO~·
~~f1f1~f1_'
01111111111~'
0000 0000 000fi/'
0000 0000 0000
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input range, output coding is straight binary.
2. For bipolar input ranges, output coding is offset binary.
3. For 0 to + 10V or ± 5V input ranges, 1 LSB for 12 bits = 2.44mV. 1LSB for
11 bits = 4.88mV.
4. For ± 10V input range, 1 LSB lor 12 bits = 4.88mV. 1 LSB for 11
bits = 9.77mV.
*Voltages given are the theoretical values for the transitions indicated. Ideally, with the converter continuously converting, the output bits indicated as ~
will change from "1" to "0" or vice versa as the Input voltage passes through
the level indicated.
5-52
EXAMPLE: For an MN6228 operating on its ± 10V input range, the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage of - 9.9976 volts. Subsequently, any input voltage
more negative than - 9.9976 volts will give a digital output of all "O's". The
transition from digital output 10000000 0000 to 0111 11111111 will ideally occur at an input of -0.0024 volts, and the 111111111111 to 111111111110
transition should occur at + 9.9927 volts. An input more positive than
+ 9.9927 volts will give all "1's".
MN6249
[1JJ
_
MICRO NETWORKS
2MHz, 12-Bit
SAMPLING AID CONVERTER
DESCRIPTION
MN6249 is a 2MHz, 12-bit sampling AID converter which
offers outstanding dynamic as well as static performance.
This sampling AID contains an internal T/H amplifier and a
12-bit, subranging AID converter in a single, 40-pin, triplewide DIP package. The internal T/H amplifier allows the AID
converter to digitize 1MHz full-scale input signals at rates up
to 2MHz. Each device is fully FFT (Fast Fourier Transform)
tested using contemporary DSP technology and guarantees
up to 68dS minimum signal-to-noise ratio (SNR, rms-to-rms)
and up to -78dS harmonics and spurious noise.
FEATURES
• 2MHz Sampling Rate
With Internal T/H Amplifier
• 12MHz
Input Bandwidth
• FFT Testing
• Minimum 68dB Signal-to-Noise
Ratio to N.yquist
• Typical -78dB Harmonics
Over Full Bandwidth
MN6249 is configured such that the internal T/H amplifier is
completely transparent. The T/H's operational mode is internally controlled by the AID timing logic. Users need only
supply start convert commands at the desired sampling rate.
Each device is fully tested both statically, in the traditional
manner, and dynamically with a series of 512-point FFT's.
This type of configuration and specification/testing eliminates the need for potentially confusing and often
misleading T/H specifications like aperture delay, aperture
jitter, charge injection, etc., and also eliminates frustrating
attempts to translate data-converter time-domain specifications into frequency-domain performance.
• Small 40-Pin DIP
• No Missing Codes
Guaranteed Over Temperature
• TTL Compatible Digital
Inputs and Outputs
• 3-State Output Buffer
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
40 PIN DIP
PIN 1
Off
I
I
MN6249 is an excellent choice for digitizing analog signals
in systems that require both high-resolution and high-speed
in as small a package as possible. Typical applications
include spectrum, vibration, waveform and transient analysizers; radar, sonar and video digitizers; medical imaging
equipment; digital filters; and multiplexed or simultaneoussampling data-acquisition systems.
MN6249 is manufactured in Micro Networks MIL-STD-1772
qualified facility, and for military/aerospace and harsh
environment industrial applications, the MN6249 H/S is
available with Environmental Stress Screening while the
MN6249 H/S CH is 100% screened to MIL-H-38534.
Contact factory for availability of CH devices.
Dimensions in Inches
(millimeters)
l1lJ
_
February 1990
MICRO NETWORKS
324 Clark St., Worcester, MA 01606
(508) 852-5400
5-53
MN6249 2MHz 12-Bit SAMPLING AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN6249J, K
MN6249S, T
Storage Temperature Range
Positive Supply (+Vcc, Pin 19)
Negative Supply (-Vcc, Pin 25)
Logic Supply \+Vdd, Pin 5, 29, 40)
-5.2V Supply (-Vee, Pin 14)
Digital Inputs (Pins 7, 12)
Analog Inputs:
10V Range (Pin 16)
5V Range (Pin 17)
Reference Output Current
ORDERING INFORMATION
-55°C to + 125°C (case)
PART NUMBER
O°C to + 70°C (case)
-55°C to + 125°C (case)
-65°C to +150°C
-0.5 to + 18 Volts
+0.5 to -18 Volts
-0.5 to +7 Volts
to -7 Volts
-0.5 to +5.5 Volts
Select suffix J, K, S, or T for desired
performance and specified temperature range.
Add "/B" suffix to "s" or "T" models for
Environment Stress Screening. - - - - Add "CH" suffix to "SIB" or "T/B" models
for 100% screening according to MIL-H-38534.
Contact factory for availability of "CH" device types.
o
MN6249X1B CH
~
-7 to +7 Volts
-3.5 to +3.5 Volts
10mA
DESIGN SPECIFICATIONS (TA =+2SOC, ±Vcc= ±ISV, +Vdd=+SV, -Vee=-S.2V unless otherwise indicated)
ANALOG INPUTS
MIN.
Input Voltage Ranges: 5V Range
10V Range
Input Impedance (Note 1): Resistance:
5V Range
10V Range
MAX.
5V Range
10V Range
UNITS
±2.5
±5.0
Volts
Volts
500
0
0
1000
Capacitance
Offset Adjustment Range:
TYP.
10
pF
±50
±100
mV
mV
DIGITAL INPUTS (Start Convert, OE)
Logic Levels: Logic "1'·
Logic "0"
+0.8
Volts
Volts
+20
-0.4
pA
mA
+0.5
Volts
Volts
+10
-10
pA
pA
+2.0
Logic Currents: Logic "1" (VIH = +2.7V)
Logic "0" (Vll = +O.4V)
DIGITAL OUTPUTS (Parallel, Status, T/H Control, MSB)
Output Coding
COB
erc
Logic Levels: Logic "1" (lsource:s;100pA)
Logic "0" (lsink:S; 2mA)
+2.7
Leakage Current (Bl - B12 in High-Z State): Logic "1" (VOH = +2.7V)
Logic "0" (VOL = +0.4V)
INTERNAL REFERENCE
Reference Output (Pin 24): Voltage
Drift (Note 1)
Output Current (Notes 1, 2)
Volts
+10
±10
2
ppm/oC
mA
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc Supply
+Vdd Supply
-Vee Supply
Power Supply Rejection (Note 3): +Vcc Supply
-Vcc Supply
+Vdd Supply
-Vee Supply
Current Drains: +Vcc Supply
-Vcc Supply
+Vdd Supply
-Vee Supply
Power Consumption
5-54
±14.5
+4.75
-5.0
±15.0
+5.0
-5.2
-50
-50
-35
-65
-60
±15.5
+5.25
-5.4
dB
dB
dB
dB
-70
-50
-80
65
80
210
50
3485
Volts
Volts
Volts
75
95
240
60
mA
mA
mA
mA
mW
-,
J
K
S
T
UNITS
2
400
2
400
2
400
2
400
MHz
nsec
Signal-te-Noise Ratio (SNR, Note 6): Initial (+25°C)
T min to T max (Note 11)
66
64
68
66
66
64
68
66
dB
dB
Harmonics and Spurious Noise (Note 7): Initial (+25°C)
T min to T max (Note 11)
-70
-70
-72
-67
-72
-70
-67
-70
Small Signal Bandwidth
12
12
12
12
dB
dB
-------MHz
Integral Linearity Error: Initial (+25°C)
T min to T max (Note 11)
1
1.5
1
1
1
1.5
1
1
LSB
LSB
Resolution for No Missing Codes: Initial @+25°C
T min to T max (Note 11)
12
12
12
12
12
12
12
12
Bits
Bits
Bipolar Zero Error (Notes 8, 9): Initial (+25°C)
0.3
0.5
0.2
0.4
0.3
0.5
0.2
0.4
%FSR
%FSR
0.25
0.40
0.20
0.30
0.25
0.40
0.20
0.30
%FSR
%FSR
DYNAMIC CHARACTERISTICS
Minimum Guaranteed Sampling Rato (Note 4)
Maximum AID Conversion Time (Note 5)
I
~
J
-~
STATIC CHARACTERISTICS
Tmin
to T max
Full-Scale Accuracy Error (Notes 8, 10): Initial (+25OC)
T min to T max (Note 11)
I
I
SPECIFICATION NOTES:
1. This parameter is listed for reference only and is not tested.
2. lithe internal relerence is used to drive an external load, the load must not change
during a conversion.
3. Power supply rejection is defined as the change in the aAalog input voltage at which
the 1111 1111 1110 to 1111 1111 1111 or the 0000 0000 0000 to 0000 0000 0001 output transition occurs versus a change in power supply voltage.
4. Minimum guaranteed sampling rate refers to the fact that these devices guarantee
all other performance specs while sampling and digrtizing at a 2MHz rate. Obviously,
the devices may be operated at lower sampling frequencies if desired.
5. When Status is high, the NO is performing a conversion.
6. This parameter represents the rms-signal-to-rms-noise ratio in the output spectrum
(excluding harmonics) with a full-scale input (OdB) sine wave at any frequency up
to 941.41 KHz and is specified as a minimum.
7. This parameter represents the highest signal-to-non-fundamental component ratio
(harmonic or spurious, in-band or out-of-band) in the output spectrum and is
specified as a minimum.
e.
Adjustable to zero with an external potentiometer.
9. Bipolar zero error is defined as the difference between the ideal and the actual in-
put voltage at which the digital output just changes fromOlll11111111 to 10000000
0000. The ideal value at which this transition should occur is - '12 LSB.
10. Full-scale accuracy specifications apply at both positive and negative full-scale and
are defined as the differences between the ideal and the actual input vollage at
which the digital output just changes from 0000 0000 0001 to 0000 0000 0000 for
positive full-scale and from 1111 1111 1110101111 1111 1111 for negative fUII_scale'l
The former transition ideally occurs at an input voltage 1'hLSB 's below the nominal
"
positive full-scale voltage. The latter ideally occurs 'I,LSB above the nominal
negative full-scale voltage.
11. MN6249J and MN6249K are specified for ooe to +700 e operation. MN6249S, SIB
and MN624!IT, TIB are fully specified for -55°e to + 125°e operation.
"
BLOCK DIAGRAM
La""
t--t--t--t--t--t---
DIgital
E~
CorreClIOl!
logIC
TIHOutput
RefaranceOutput(+5V)
(21) 0 ' - - - - - - - - - - 1
(27)0----------+----t-----,
'----
LSO
II
-
r--
f-o
3-Slale
Output
Latch
(11) a
T/HCommand
(10) 0 - - - -
:
+15VSupplI'(."V(:C)
(19) 0 1 - 1 - - - -
_lSV Supply (-Vcc)
(25) °0
tt'~'"
AnillogGround (18.22.23,28)
-S.2V Supply (-""1
--~-
lOgIC
r~O_~_"_
(14) o _ _. .
-
Gall'
~
T'
p,
I:llll(M$8)
&,12
R.t3
,,,,
""
""
8
(7)
~~~~!
,-".nlro!
(2)
(35)
3-5181e
Slalus{EOC)
rn-T:~9
r--c,
'--<
9ili(MS6)
--"
-
Latch
(12) 0
",
i---c.
ReferenceOutput(+10V} ( 2 4 ) 0 - - - - - - - - - - j - - - - - + - - - - - '
StartCorlll81'1
(4)
c,-"
--
'--
~ I.,''''
~
f-<>
o...lpUIEnable(OE)
(33)
\31)
B,112(LSB)
7-B'1
o.
Converter
I
(8.9131
TeSIF-o,nI.
+5VSupply(+Wd) (5,29,40) O - - : t . . - - O.Q1~F
Dog,laiGround t6.20.28. 39)
o-_T>--_
Test Points are connected to internal
circuitry and should not be connected
to externally.
5-55
TIMING DIAGRAM
0.0
Time (nsec)
Start Convert
I
500
250
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
750
I
I
I
I
I
I
I
I
I
I
I
I
I
I
--1I______________--IrlL.____________
"'1__- - - - 4OOn8ec----......
--I1
AID Status
L--.J:..;::====::-a;355i5;;;ns;.e~c-===::::;.:jIL_ _..J
T/H Control
----.J
Output Data
J ______..:.v.:::al~id:.-_ _ ____'~'___ _ _ _ __'v;.:;a::.;li;;.d_ _ _ _ ___'C
Hold
Track
Hold
TIMING DIAGRAM NarES:
1. Minimum start convert pulse width is 50nsec. The rising edge of start convert resets
internal timing circuits ensuring that T/H Control (pin 10) is set to a logic "0" and
that the first conversion made upon "powerup" is valid. The falling edge of Start
Convert initiates the conversion, and Start Convert must remain low for 350nsec
minimum.
2. Status rises to a "I" typically 45nsec after the falling edge of Start Convert.
3. Conversion time is defined as the time from the falling edge of Start Convert to the
falling edge of Status and is specified as 400nsec maximum.
4. Digital output data from the previous conversion remains valid typically 280nsec
after the falling edge of Start and 235nsec after the rising edge of Status.
5. Digital output data is valid on the falling edge of Status.
6. Output data is enabled and becomes valid a maximum of 50nsee after Output
Enable (OE, pin 7) is broughllow.
7. The falling edge of T/H Control occurs 300nsee maximum after the falling edge of
Start Convert.
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - The MN6249 is a 12-bit, sampling, AID converter consisting of a high-speed AID converter and
its companion T/H amplifier. The AID section is a multistage (twostep) AID converter. It employs the Micro Networks Serial-Parallel
conversion technique (sometimes referred to as the subranging
technique) with digital error correction. The technique uses two 7-bit
flash AID converters (actually a single 7-bit flash converter is used
twice) in a configuration that yields a resolution (12 bits) that is
beyond the practical limits of what can be achieved in a single highresolution flash converter. For a detailed discussion of the SerialParallel conversion technique and digital error correction, please
refer to the MN5245/5246 data sheet.
The Start Convert signal must be a positive pulse with a minimum
pulse width of 50nsec (100nsec maximum if continuously converting at maximum conversion rate) and must remain low during the
conversion for a minimum of 350nsec. The rising edge of Start COnvert resets the timing logic ensuring that all timing pulses are set
to the proper state and that the first conversion following "power on"
produces valid digital output data. The falling edge of Start Convert
initiates the conversion setting T/H Control Output and Status
(E.O.C.) to logic "1 's", The T/H Control Output signal remains a logic
"1" for 300nsec maximum after the falling edge of Start Convert
and returns to a logic "0" when the "analog-processing" portion
of the conversion is complete. Status remains a logic "1" for 400nsec
maximum after the falling edge of Start Convert. Status returning
low signifies that the conversion process is complete and that
parallel output data is valid.
The internal T/H amplifier enables the MN6249 to sample and
digitize analog input signals while maintaining SNR (rms-signal-torms-noise) and harmonic distortion performance specifications. The
T/H amplifier's mode of operation is controlled by the internal controllogic circuitry. When a conversion is initiated by the falling edge
of Start Convert, the T/H amplifier is switched from the track mode
to the hold mode, indicated by the T/H Control Output changing from
a logic "0" to a logic "1". The internal T/H amplifier remains in the
hold mode during the "analog processing" portion of the conversion cycle. Once the analog processing is complete, and the analog
input signal no longer needs to be held at a constant value, the T/H
is switched to track mode to acquire and track the next analog input signal to be converted (T/H Control Output changes from a logic
"1" to a logic "0"). This allows the T/H amplifier's acquisition time
to overlay the' 'digital processing" portion of the conversion cycle.
5-56
Valid parallel output data is available on the falling edge of Status
and remains valid during the next conversion for 280nsec (typ) after
the next falling edge of Start Convert. See Timing Diagram. This
allows the use of riSing and falling edges of either Start Convert or
Status for latching output data.
LAYOUT CONSIDERATIONS - Proper attention to layout and
decoupling is necessary to obtain specified accuracy and performance from the MN6249. Analog Ground (pins 18, 22, 23, 28) is not
connected internally to Digital Ground (pins 6, 20, 26, 39). All ground
pins should be tied together as close to the unit as possible and connected to system analog ground, preferably through a large analog
ground plane underneath the package. If p.c. card ground lines must
be run separately, wide conductor runs should be used with 0.01 fl F
ceramic capacitors interconnecting them as close to the package
as possible.
Coupling between analog inputs and digital signals should be
minimized to avoid noise piCk-Up. Care should be taken to avoid long
runs or analog runs close to digital lines.
Power supply connections should be short and direct, and all power
supplies should be decoupled with high-frequency bypass
capacitors to ground. 1fl F tantalum capacitors in parallel with 0.01 fl F
ceramic capacitors are the most effective combination. Single 1fl F
ceramic capacitors can be used if necessary to save board space.
A 0.1 fl F capacitor should be connected from Gain Adjust (pin 27)
to system analog ground.
Pins 5, 29,
40 0
Pins 6, 20,
26,39 c
Pin 14 u
0
Pins 18, 22,
23, 28
I
l
I
I
I
l
I
I
+5V
Pin 19
Digital
Ground
0
Pins 18, 22,
23,28 c
-5.2V
Pin 25 c
1
I
II IT
Analog
Ground
POWER SUPPLY DECOUPLING
+15V
Analog
Ground
-15V
PIN DESIGNATIONS
•
40
Pin I
20
21
cr.
Notes: "Test Points" P.) are connected to internal circuitry and should not be
connected to externally.
INTERNAL T/H AMPLIFIER - As stated earlier, MN6249's internal T/H amplifier is configured in such a way as to be transparent
to the user. The T/H's output is connected directly to the input of the
AID converter, and its operational mode is controlled directly by the
internal control logic circuitry. Consequently, users olthe MN6249
need not burden themselves with oftentimes confusing T/H
specifications like acquisition time, aperture-delay time, aperture
jitter, droop rate, etc. . These parameters are not specified for
MN6249 and are, in fact, impossible to directly test considering that
the T/H output and control lines are not accessible at the device pins.
The manner in which MN6249 is specified (input bandwidth, sampling rate, signal-to-noise ratio, harmonic distortion, etc.) obviates the
need for knowing the specific T/H time-domain performance
specifications.
Note that the static errors (gain error, track-mode offset error, and
pedestal) of the T/H function will add directly to the corresponding
errors of the AID converter but that both are effectively nulled with
the functional laser trimming of the AID. T/H offset error and
pedestal, for example, add directly to AID-converter offset error.
However, when the AID offset is functionally laser trimmed, it is done
at the 2MHz sampling rate with the T/H is in the hold mode. Consequently, all error sources are compensated for. All static errors on
MN6249 (accuracy error, unipolar offset error, bipolar zero error, etc.)
are tested and specified as full input-output transfer specifications
and include both the T/H and AID.
STATUS OUTPUT/DATA VALID-The Status or End of Conversion
(E.o.C., pin 11) is set to a logic "I" by the falling edge of Start Convert; remains high during the conversion; and is set to a logic "0"
when the conversion is complete. Digital output data is valid on the
falling edge of Status and remains valid 280nsec after Start Convert goes low initiating the next conversion. When making successive conversions, any of the edges occurring during the beginning of the data-valid period (fall of Status, falling edge of the next
Start Convert, rising edge of Status, etc.) are best suited forthis purpose. Also, output data can be enabled during this data-valid period
by bringing Output Enable (DE, pin 7) low. The delay from the failing edge of OE to o'Jtput data enabled is 50nsec maximum.
GAl'" ADJUST - Pin Z1 on MN6249 serves a unique function. The
device's internal +SV :2% reference is brought out at this point
and can be used to drive external loads. If used for this purpose,
pin 27 should be buffered with a FET-input device as drawing more
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
Bii3
Bit 2
Bit I (MSB)
Bit I (MSB)
+5V Supply (+Vdd)
Digital Ground
Output Enable (DE)
T.P.
T. P.
T/H Control Output
Status (EOC)
Start Convert
T.P.
-5.2V Supply (-Vee)
Offset Adjust
IOV Range
5V Range
Analog Ground
+15V Supply (+Vcc)
Digital Ground
40 +5V Supply (+Vdd)
39 Digital Ground
38 Bit 4
'51 Bit 5
36 Bit 6
35 Bit 7
34 Bit 8
33 Bit 9
32 Bit 10
31 Bit II
30 Bit 12 (LSB)
29 +5V Supply (+Vdd)
28 Analog Ground
27 Gain Adjust
26 Digital Ground
25 -15V Supply (-Vcc)
24 Reference Output (+IOV)
23 Analog Ground
22 Analog Ground
21 T/H Output
than 5pA from the internal reference will affect MN6249 accuracy
and linearity. Pin 27 can also be used as a Reference In pOint if it
is necessary to operate MN6249 from an external reference. An application requiring an external reference might be one in which it
is necessary to have a number of devices operate from the same
reference in order to track each other in changing temperatures. The
applied reference should be +5V ±2S0mV.
Pin Z1 also functions as the gain-adjust point for MN6249. Gain adjustment is accomplished using a 10k!l to 100k!l trimming potentiometer and a 500k!l series resistor as shown below. The series
resistor can be ± 20% carbon composition or better. The multiturn
potentiometer should have a TCR of l00ppm/oC or less to minimize
drift with temperature. Gain adjusting is normally accomplished by
applying the analog input voltage at which the 1111 11111110 to 1111
1111 1111 digital-output transition is ideally supposed to take place
and adjusting the pot until the transition is observed.
+15V
10kll
Pin 'Z1 O--....~IM,.-~~
to
100kll
Gain Adjust Range= ±O.2% FSR
OFFSET ADJUST -Initial offset error of the MN6249 can be adjusted to zero by applying a voltage to Offset Adjust (pin 15). A SO!,!l
resistor is connected from Offset Adjust (pin 15) to the internal T/H
amplifier's summing junction. This allows the output of a voltageoutput DAC or the wiper of a potentiometer to be connected directly to Offset Adjust (pin 15).
+15V
Offset Adjust (15)
4
to
lOOK
10k
Offset Adjust (15)
0----1
± 5V DAC
I
-15V
5-57
ORDERING INFORMATION
Part
Number
I
Specified
Temperature
Range
No Missing
Integral
Codes
Linearity
Over Temp. Over Temp.
MN6249J
OOClo +70°C
MN6249K
O°C to +70OC
-SsoC to + 12SOC
MN6249S
MN6249SIB'"
-55°C to +125°C
MN6249S1B CHI2l -S5°C to +125OC
-S5°C to +125OC
MN6249T
MN6249T/B''I
-SsoC to +125°C
MN6249T/B CH'" -SsoC to + 12SoC
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bils
12 Bits
±l.SLSB
±1LSB
±l.5LSB
±1.5LSB
±l.5LSB
±1LSB
±1LSB
±1LSB
Minimum
Sampling
Rate
Minimum
Input
Bandwidth
SNR
Harmonics
2M Hz
2MHz
2MHz
2MHz
2MHz
2MHz
2M Hz
2M Hz
lMHz
1MHz
lMHz
1MHz
lMHz
1MHz
1MHz
1MHz
66dB
66dB
66dB
66dB
68dB
68dB
68dB
68dB
-70dB
-72dB
-7OdB
-7OdB
-7OdB
-72dB
-72dB
-72dB
1. Includes Environmental Stress Screening.
2. Fully compliant to MIL-H-38534.
DIGITAL OUTPUT CODING
Analog Input
Digital Output
±5V
±2.5V
-S.OGOO
-4.9988
-2.S0OO
-2.4994
1111 1111 1111
11111111111,-
-0.0036
-0.0012
+0.0012
+4.9964
-0.0018
-0.0006
+0.0006
1000 0000 0000"'
fl0"fJ"rt 0"~~f1 fJ"fJ"rtf1'
011111111110'"
+2.4982
+2.SOOO
0000 0000 000,0000 0000 0000
+5.0000
MSB
[11J
_
LSB
NOTES:
1. For a 12-bit converter with a 5 Volt FSR. 1LSB=1.22mV. For a 12·bit converter with
a 10 Volt FSR. 1LSB=2.44m11.
2. Coding is complementary offset binary.
"Analog voltages listed are the theoretical values for the transitions indicated. Ideally.
with the converter continuously converting. the output bits indicated as _ will change
from a "1" to a "0" or vice versa as the input voltage passes through the level Indicated.
MICRO NETWORKS
324 Clark St.. Worcester, MA 01606
S-S8
(508) 852-5400
l1JJ
_
MN6290
MN6291
DESCRIPTION
The MN6290 Series of Low-Distortion, 16-Bit, Sampling, AID
Converters offers an outstanding combination of resolving
power, conversion speed, low noise, and low harmonic
distortion. These SA type AID's are packaged in small,
32-pin, double-wide DIP's and have internal track-hold (T/H)
amplifiers that enable them to accurately sample and
digitize 10kHz full-scale input signals at rates up to 20kHz.
Each device is fully FFT (Fast Fourier Transform) tested
using contemporary DSP technology and guarantees up to
84dB signal-to-noise ratio (SNR, rms-to-rms) and up to
- 88dB harmonics and spurious noise.
FEATURES
• 20kHz Sampling Rate
With Internal T/H Amplifier
• 10kHz Full-Power
Input Bandwidth
• 84dB Signal-to-Noise Ratio
Over Full Bandwidth
• -88dB Harmonics Over
Full Bandwidth
• FFT Testing
• Serial and Parallel Outputs
• 1.5 Watts Max Power
• Standard 32-Pin DIP
• Fully Specified O°C to +70°C
(J and K Models) or -55°C
to +125°C (S and T Models)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
32 PIN DIP
---1t
0D15fO. 3811
~Nl
0035(0.889)
1.---\- - - ,
~-r
MN6290 (10V input span) and MN6291 (20V input span)
are configured in a manner that makes their internal T/H
completely user transparent. A high-impedance (5Mfl) input
buffer isolates the T/H from its signal source, and the T/H's
operational mode is internally controlled by the AID's status
line. Users need only supply start-convert pulses at the
desired sampling rate. Each device is fully tested both
statically, in the traditional manner, and dynamically with a
series of 512-point FFT's. This type of configuration and
testing eliminates the need for potentially confusing and
misleading T/H specifications like aperture delay, aperture
jitter, charge injection, etc., and also eliminates historically
frustrating attempts to translate data-converter time-domain
specifications into frequency-domain performance.
O.087@11Q!
O.115(2.92~
--~-1
-,
I
I
I
I
I
1,~~~
O.110(19.56l __ ..
0.810 (20.5n
OdB ,"
I
1500(3810)
~IJJ
L __
I
LOW-DISTORTION
SAMPLING, 16-Bit
AID CONVERTERS
MICRO NETWORKS
J
L
-I _-.L~~~ !!'=l g.~~ ~:ii1~
0.020(0.508)
T
1
- 20dB
1...
i
-4OdB '
I
Signal
Amplitude
Input Frequency:
Sampling Rate:
RMS Signal:
RMS Noise:
SIN:
2nd Harmonic:
3rd Harmonic:
10kHz
2O.5kHz
- 0_28dB
- 85_71dB
85_43dB
- 9O.47dB
- 94.89dB
- BOdB
Relative to
Full Scale
-80dB
-100dB
-120dB
Dimensions in Inches
(millimeters)
-140dB
OHz
10_25kHz
Input Frequency
~
MICRO NETWORKS
December 1991
Copyright c 1991
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
5-59
MN6290, MN6291 SAMPLING 16-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN6290J, K; MN6291J, I<
MNC,?"OS, SIB, T, TIB
MN6291S, SIB, T, TIB
Storage Temperature Range
Positive Supply ( + Vcc, Pin 27)
Negative Supply (- Vcc, Pin 23)
Logic Supply; + Vdd, Pin 29)
Digital Inputs (Pins 30, 32)
Analog Inputs (Pins 7, 8)
Analog Ground (Pins 9, 26) to Digital
Ground (Pin 31)
Ref Out (Pin 8) Short Circuit Duration
ORDERING INFORMATION
-55·Cto +125·C
PART NUMBER
O·C to + 70·C
- 55·C to + 125·C
- 55·C to + 125·C
-65·Cto +150·C
a to + 16.5 Volts
a to - 16.5 Volts
a to + 7 Volts
a to + 5.5 Volts
± 15 Volts
""ct "''''''J, " """"
±1 Volt
Continuous to Ground
II
MN6290T/B CH
Select suffix K, S, or T for
I
desired performance and
specified temperature range.
Add "/B" to "S" or "T" models for
Environmental Stress Screening.
Add "CH" to "SIB" or "T/B"
models for 100% screeni ng
according to MIL-H-38534.-------'
Contact factory for availability of "CH"
device types.
DESIGN SPECIFICATIONS ALL UNITS (TA= +25°C, ±Vcc= ±15V, + Vdd= +5V unless otherwise indicated)(Note 1)
ANALOG INPUTS
MIN.
TYP.
a to
Input Voltage Ranges: MN6290
MN6291
Input Impedance (Note 17): Resistance
Capacitance
MAX.
+ 10, ± 5
±10
Volts
Volts
5
50
Input Bias Current Over Full
Temperature Range
UNITS
Mohm
pF
±600
nA
+0.8
Volts
Volts
+40
-0.8
p.A
rnA
+0.4
Volts
Volts
DIGITAL INPUTS (Start, Short Cycle)
Logic Levels: Logic "1"
Logic "0"
+2.0
Logic Currents: Logic "1" (V'H = + 2.4V)
Logic "0" (V'L = + O.4V)
DIGITAL OUTPUTS (Serial, Parallel, Status, Clock)
Output Coding (Note 2): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (lsource,,320p.A)
Logic "0" (lsink" 3.2mA)
Straight Binary
Offset Binary
+2.4
INTERNAL REFERENCE
Reference Output (Pin 24): Voltage
Drift (Note 17)
Output Current (Notes 3,17)
+9.9
1
Volts
ppml·C
rnA
±15
+5
±15.5
+5.5
Volts
Volts
±0.003
±0.003
±0.001
±0.02
±0.02
±0.01
%FSR/% Supply
%FSRI% Supply
%FSRI% Supply
+33
-34
+28
+48
-40
+35
mA
mA
mA
1150
1500
mW
+10
±15
+10.1
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc Supply
+ Vdd Supply
Power Supply Rejection (Note 14): + Vcc
-Vcc
+Vdd
Current Drains: + Vcc Supply
- Vcc Supply
+ Vdd Supply
Power Consumption
5-60
±14.5
+4.5
PERFORMANCE SPECIFICATIONS (Typical at TA= + 25°C, ± Vcc = ± 15V, + Vdd = + 5V unless otherwise indicated)
MN6290J
MN6291J
MN6290K
MN6291K
MN6290S
MN6291S
MN6290T
MN6291T
UNITS
Minimum Guaranteed Sampling Rate (Note 4)
Maximum AID Conversion Time (Note 5)
20
40
20
40
20
40
20
40
~sec
Signal-to-Noise Ratio (SNR, Note 6):
Initial (+ 25°C) (Minimum)
T mio to T max (Minimum, Note 7)
80
78
84
82
80
78
84
82
dB
dB
-85
-82
-88
-85
-85
-82
-88
-85
dB
dB
10
10
10
10
kHz
± 0.006
±0.012
±0.003
±0.006
± 0.006
±0.012
±0.003
±0.006
%FSR
%FSR
13
13
14
14
13
13
14
14
Bits
Bits
±0.05
±15
±0.12
±0.05
±7.5
±0.084
±0.05
±15
±0.2
±0.05
±7.5
±0.125
%FSR
ppm of FSR/oC
%FSR
Bipolar Zero Error (Notes 10, 12):
Initial (+25°C) (Maximum)
Drift (Maximum)
Max Error Tmio to Tmax (Note 15)
± 0.075
±15
±0.15
±0.05
±10
±0.1
± 0.075
±15
± 0.225
±0.05
±10
±0.15
%FSR
ppm of FSR/oC
%FSR
Full Scale Accuracy Error (Notes 10, 13):
Initial (+ 25°C) (Maximum)
Max Error Tmio to Tmax (Note 15)
Drift (Maximum)
±0.2
±0.35
±30
±0.1
±0.2
±20
±0.2
±0.5
±30
±0.1
±0.3
±20
%FSR
%FSR
ppm of FSR/oC
DYNAMIC CHARACTERISTICS
Harmonics and Spurious Noise (Note 8):
Initial (+ 25°C) (Minimum)
T mio to T max (Minimum, Note 7)
Input Signal Full-Scale Bandwidth (Minimum, Note 9)
kHz
STATIC CHARACTERISTICS
Integral Linearity Error: Initial (+ 25°C) (Max. Note 16)
Tmio to Tmax (Maximum, Note 7)
Resolution for Which No Missing
Codes is Guaranteed: Initial ( + 25°C)
Tmio to Tmax (Note 7)
Unipolar Offset Error (Notes 10, 11):
Initial (+ 25°C) (Maximum)
Drift (Maximum)
Max Error Tmio to Tmax (Note 15)
I
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data
sheet.
2. See table of transition voltages in section labeled Digital Output Coding.
3. In addition to supplying 1mAof current for bipolar offsetting purposes(pin 7
connected to pin 24), the internal reference is capable of driving up to 1mA
into an external load. If the internal reference is used to drive an external
load, the load should not change during a conversion.
4. Minimum guaranteed sampling rate refers to the fact that these devices
guarantee all other performance specs while sampling and digitizing at a
20kHz rate. Obviously, devices may be operated at lower sampling frequencies if desired and typically will meet all performance specs whilesampling
at rates of 25kHz or higher.
5. Whenever the Status Output (pin 1) is low ("logic "0"), the internal T/H is in
the track mode, and the AID converter is not converting. When Status is high
(the definition of AID conversion time), the T/H is in the hold mode, and the
AID is performing a conversion.
6. This parameter represents the rms-signal-to-rms-noise ratio in the output
spectrum (excluding harmonics) with a full-scale input sine wave (Odb) at
any frequency up to 10kHz.
7. MN6290J, Kand MN6291J, K are fufly specified forO°Cl0 + 70°Coperalion.
MN6290S, SIB, T, TIB and MN6291 S, SIB, T, TlB are fUlly speCified for - 55°C
to + 125°C operation.
S. This parameter represents the peak signal to peak non-fundamental component (harmonic or spurious, in band or out of band) in the output
spectrum.
9. This is the highest-frequency, full-scale, input signal for which the SNR and
harmonic figures are guaranteed when sampling at a 20kHz rate.
10. Adjustable to zero with external potentiometer.
11. Unipolar offset error is defined as the difference between the ideal and the
actual input voltage at which the digital output just changes from 0000 0000
00000000 10 0000 00000000 0001 when operaling the MN62900n its unipolar
range. The ideal value at which this transition should occur is + % LSB. See
Digilal Oulpul Coding.
12. Bipolar zero error is defined as the difference between the ideal and the
actual input voltage at which the digital output just changes from 01111111
11111111101000 0000 0000 0000 when operaling the MN629016291 on a
bipolar range. The ideal value at which this transition should occur is
- % LSB. See Digital Output Coding.
13. Full scale accuracy specifications apply at positive full scale for unipolar input ranges and at both positive and negative full scale for bipolar input
ranges. Full scale accuracy error is defined as the difference between the
ideal and the actual input voltage at which the digital output just changes
fromll11111111111110tol111111111111111 for unipolar and bipolar Inpul ranges. Addilionally, il describes the accuracy of the 0000 0000 0000
0000 to 0000 0000 0000 0001 transition for bipolar input ranges. The former
transition ideally occurs at an input voltage 1 % LSB's below the nominal
positive full scale voltage. The latter ideally occurs % LSB above the
nominal negative full scale voltage. See Digital Output Coding.
14. Power supply rejection is defined as the change in the analog input vOitage
atwhichlhelllll11111111110tollll111111111111 or 0000 0000 0000
0000 to 0000 0000 0000 0001 output transitions occur versus a change in
power-supply voltage.
15. Listed maximum error-over- temperature specifications for unipolar offset,
bipolar zero and full-scale accuracy correspond to the combination of maximum room-temperature errors and worst-case drift conditions to describe
the worst-case error that might be encountered over the entire specified
temperature range.
16. ± 0.006% FSR is equivalent to ± V2LSB for 13bits and is equal to ±0.6mV
for a device with a 10V full scale range (0 to + 10V or ± 5V input range).
± 0.003%FSR is equivalent to ± Vz LSB for 14 bits and is equal to ± 0.3mV
for a device with a 10V full scale range.
1? These parameters are listed for reference only and are not tested.
Specifications subject to change without notice as Micro Networks reserves
the right to make improvements and changes in its products.
5-61
BLOCK DIAGRAM
Start Convert (30)
TIMING AND
CONTROL
LOGIC
-
I
Status Output (E.O.C.) (I)
+ 15V Supply (27) 0
- 15V Supply (23) 0
+ 5V Supply (29) 0
Ground (31) 0
Ground (9. 26) 0
~(22)MS B
(21)
(20)
(19)
(18)
,.
""
Bit
Bit
Bit
Bit
(17) Bit
(16) Bit
~
:>
,
I
~(15)Bit
,
I
I
It-
G-
I
+-- _+---------<:l
(14) Bit
_~~(13)Bit
I
i
~
I
I
i
i
I
i
~-t---
~
10kll
~
1
CH
NOTE: For unipolar operation (MN6290 0 nly)
pin 7 should be connected to grou nd.
For bipolar operation (MN6290/MN 6291;
connect pin 7 to pin 24.
~
~Status
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS - Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN6290/6291. The units' three ground pins (pins 9,
26, and 31) are not connected to each other internally. They
must be tied together as close to the unit as possible and all
connected to system analog ground, preferably through a
large analog ground plane beneath the package. If these
commons must be run separately, a non-polarized O.OII'F
ceramic bypass capacitor should be connected between
analog ground pins (pins 9 and 26) and digital ground (pin 31)
as close to the unit as possible. Wide conductor runs should
be employed.
Coupling between analog inputs and digital signals should
be minimized to avoid nosie pick·up. Bipolar Offset (pin 7),
Analog Input (pin 8), Offset Adjust (pin 28) and Gain Adjust
(pin 25) are particularly noise sLlsceptable. Care should be
taken to avoid long runs or runs close to digital lines when
utiiizing these inputs. Input signal lines should be a short as
possible. In bipolar operation, where Bipolar Offset (pin 7) is
connected to Reference Output (pin 24), a short jumper
should be used. For external offset adjustment, the series
resistor(s) should be located as close to Offset Adjust (pin 28)
as possibfe. A O.OIJLF capacitor should be connected between
5-62
Gain Adjust (pin 25) and Analog Ground as close to the
package as possible. An O.OlJLF capacitor should be connected
from Reference Output (pin 24) to Analog Ground.
Power supplies should be decoupled with tantalum and
ceramic capacitors located close to the MN6290/6291. For
optimum performance and noise rejection, II'F tantalum
capacitors paralleled with O.OIJLF ceramic capacitors should
be used as shown in the diagrams below.
If short-cycling is not used the Short-Cycling pin (pin 32) must
be connected to +5V (pin 29).
POWER SUPPLY DECOUPLING
Pin 27 0
+ ~F
I ~F
Pin 29 0 - ' 1 - - - . - - + 5V
I
Pin 31 0
~F I
-
0.01
Pin. 9, 26 a
Ground
1 ~F
Pln230
I
1
IT I
T
-
I
+15V
0.01 ~F
Ground
0.Q1 .F
-15V
PIN DESIGNATIONS
•
32
16
17
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Status IE.O.C.)
Clock Output
Bit 13
Bit 14
Bit 15
Bit 16 ILSB)
Bipolar Offset
Analog Input
Analog Ground
Serial Output
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Short Cycle
Digital Ground
Start Convert
+ 5V Supply I + V dd)
Offset Adjust
+ 15V Supply 1+ Vce!
Analog Ground
Gain Adjust
Reference Output 1+ 10V)
- 15V Supply 1- V cc )
Bit 1 IMSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-MN6290 and MN6291 are
16·bit, sampling, AID converters. Each contains a 16·bit
successive·approximation type AID and a companion track·
hold (T/H) amplifier. The T/H's enable MN6290 and MN6291 to
accurately and repetitively sample and digitize dynamically
changing input signals in both traditional data·acquisition
and contemporary DSP·type applications.
Successive approximation (SA) type AID converters, when
operated without the aid of T/H amplifiers, are severely
limited in their ability to accurately convert changing analog
input signals. The traditional rule of thumb for guaging such
performance is that the AID's are incapable of accurately
converting signals that are slewing faster than (± VzLSB)1
(conversion time). For a 14·bit AID with an input range of ± 10V
and a conversion time of 40l'sec, this corresponds to an input
slew·rate limit of ± 7.61'.v/l'sec. If one wishes to express the
slew·rate limit as a bandwidth for a full·scale illPut sinusoid,
it corresponds to 0.24Hz.
The proliferating use of AID converters in DSP applications
has resulted in significantly greater demands on AID's to be
able to convert dynamic signals, particularly sinusoids. More
and more frequently, T/H amplifiers are used with AID's to
enable them to accomplish this task.
MN6290/6291 are extremely user friendly. They have been
configured in a manner that virtually eliminates all of the pro·
blems encountered when mating T/H's and successive approximation AID's and driving the pair from real-world signal
sources. The T/H is truly transparent. A high-impedance
(5Mohm) input buffer isolates it from the external signal
source, and its output is internally connected directly to the
input of the AID converter. Theoutput current, impedance and
transient-response characteristics of the T/H have been optimized for driving the 16·bit SA AID. More importantly, the
critical dynamic characteristics of the T/H (aperture delay,
aperture jitter, small and large signal bandwidths, droop rate,
etc.) have been similarly optimized. Most importantly, the
critical inter-device timing relationships (T/H mode control,
transient decay time, etc.) are internally controlled by
MN6290/6291 's timing and control circuitry. All that users
need to provide externally is the start convert pulse.
The falling edge of the start convert pulse activates
MN6290/6291's internal timing circuitry. Immediately, the T/H
(which has been in the track or signal·acquisition mode up
until this time) is driven into the hold mode instantaneously
"freezing" the value of the analog input signal.
Simultaneously, MN6290/6291's status output (also called
"End of Conversion" or E.O.C.) is set to a logic "1" indicating
that the T/H is now in hold; that an AID conversion is now in
progress; and that the parallel output data (from the previous
conversion) is no longer valid. M N6290/6291 's internal timing
logic now provides approximately 1 I'sec of delay to permit
the track-to-hold switching transient at the output of the T/H
to decay. Subsequently, the internal clock is started, and the
16·bit AID conversion of the held signal proceeds.
The value of the hold capacitor used in MN6290/6291 's inter·
nal T/H has been selected so thai T/H output droop, even over
temperature, is not significant (~Ireater than ± '/2 LSB) during
the AID's conversion time. Similarly, the offset and pedestal
voltages, as well as the gain error, of the T/H do not contribute
to the overall accuracy of the sampling AID because they are
effectively nulled out during our active laser trimming of the
AID converter.
At the completion of the AID conversion, MN6290/6291's internal control logic turns off the internal clock; drops the
status output back to a logic "0"; and commands the T/H
back into the track mode to acquire a new input signal. Status
gOing low signifies that the conversion is complete and that
the parallel output data is valid. A 20nsec delay has been
added between the finalization of the LSB and the falling
edge of status. This ensures that all output bits are valid when
status falls and permits the use of this trailing edge to clock
data into output latches. Output data remains valid until the
falling edge of the next start convert pulse.
5-63
I
TIMING DIAGRAM
START CONVERT ~~_________________________________________________________________
STATUS
--.-J
L
T1H in Hold Mode
INTERNAL CLOCK
MSB
UlIIl1!II
BIT 2
IT!lJI.lJlJ
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT '1
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16
Ul
ll"LWl..llJ
lllllllllJ
ZllllllllJ
o.
llllllm
llllllll.lJ
7Zlll.ZlllJ
llllmlJJ
lllTll.lllJ
llll1JTtlJ
lllllillJJ
llZllil.llJ
tl.1llflZlJ
llll1.LlllJ
7Zlll.!l.llJ
10
SERIAL OUTPUT
SPECIFICATIONS (TA
= + 25°C, supply voltages
:!:
1SV and
+ SV
15
16
unless otherwise specified)
DYNAMIC CHARACTERISTICS
MIN.
Conversion Time (16 Bits) (Note 6)
Internal Clock Frequency (Notes 4, 8)
404
Start Convert Pulse Width (Notes 2, 7)
40
Delay Falling Edge of Start to (Note 8): Status = "1"
Clock Output = '"1"
TYP.
MAX.
UNITS
35
40
~sec
462
kHz
nsec
30
400
nsec
nsec
Delay Rising Clock Edge to Output Data
Valid (Parallel, Serial, Status) (Note 8)
20
100
nsec
Delay LSB Valid to Falling Edge of Status (Notes 3, 8)
20
40
nsec
TIMING DJAGRAM NOTES:
,. Operation shown is for the digital word 0,0, 011000,0,011.
2. The Start Convert command can be either a positive or negative pulse at
least 40nsec wide. Conversions are initiated on the falling edge of the
Start Convert command.
3. Data will be valid 20nsec prior to the falling edge of Status (E.O.C.).
4. The internal clock is enabled and the conversion commences following
an internal delay which allows for T/H switching and settling.
5-64
5. When the converter is initially "powered up" it maycomeon at any point in
the conversion cycle.
6. Conversion time is defined as the width of the Status (E.O.C.) pulse.
7. The minimum time between falling edges of the Start Convert command
is 50l1sec.
8 These parameters are listed for reference only and are not tested.
APPLICATIONS INFORMATION
START CONVERT
STATUS
.JiL..-___________----'
---.J
TIH in Hold Mode
INTEANAL CLOCK
MSB
7ll1l1ll11J
BIT 2
lllllfLl.l}.
BIT 3
lUlllllJliJ
BIT 4
llllllllf},
BIT 15
lUlUllllJ
LJ 1
Ul
L..-~
________________________________________
~,___,~~
___
LJ 1
BIT 16ll1LZllllJ
SERIAL OUTPUT
PARALLEL OUTPUT
7I!1.mi1Jll!ll1L2.J
15
16
~,--_ _ _ _ _ _ _ _ _I_NV_A_Ll_D_ _ _ _ _ _ _ _ _ _ _~_ _ _ _IN_V_AL_'D_ __ _
TIMING DIAGRAM - The above timing diagram illustrates
the relationships of the external and internal timing pulses
discussed in the following sections. Additionally, the above
diagram shows the beginning of a second conversion and of
particular interest, the relationship of Start Convert, Status
(E.O.C.), Serial Output and Parallel Output from one conver·
sion to another.
START CONVERT - The falling edge of the start convert
signal initiates the sampling/digitizing cycle. Either positive,
negative or symetrical pulses can be used to initiate conver·
sions provided that the start convert signal has a minimum
positive pulse width of 40nsec. To achieve guaranteed perfor·
mance, the maximum repetition rate of the start convert
signal is 20kHz. Obviously, MN6290/6291 may be operated at
lower sampling rates if desired. If necessary, the start convert
signal may be set to a logic "1" after the conversion has
begun, however, the next falling edge should not occur until
the ongoing conversion is complete and a minimum of
1O!,sec has been allowed for the internal T/H amplifier to ac·
quire and track the next analog input voltage to be sampled
and digitized. See diagram above.
STATUS OUTPUT - The Status Output (End of Conversion
(E.O.C.), pin 1) will be set to a logic "1" 30nsec (typical) after
the falling edge of Start Convert; will remain a logic "1" during
the conversion; and will be set to a logic "a" when the conver·
sion is complete. The falling edge of status occurs a
minimum of 20nsec after the LSB output bit is set to its final
value (delay from LSB bit valid to falling edge of Status is
20nsec min). Therefore, the Status Output may be used to
latch valid digital output data. If the latches selected require
more than 20nsec of set·up time, simple gate delays can be
used to delay the falling edge of Status. See diagram above.
I
(pin 32). For example, to truncate at 14 bits, connect Bit 15 (pin
5)to the Short Cycle input (pin 32); converting will stop and the
Status Output (End of Conversion (E.O.C.), pin 1) will be set to
a logic "a" a minimum of 20nsec after bit 14 has been set.
PARALLEL OUTPUTS - During the succesive approxima·
tion process the weight of each bit is compared to the value of
the analog input voltage. The converter is reset to MSB·0111
11111111 1111·LSB by the riSing edge of the first clock pulse.
Subsequent rising clock edges set the bit previously tested to
its final state and brings the next bit to be tested to a logic
"a". This process continues until all bits have been tested
and the Status Output returns to a logic "a". Valid parallel
output data can only be latched at the end of the
sample/conversion cycle.
The LSB bit is valid 20nsec prior to the falling edge of Status
Output (E.O.C.), therefore, this edge may be used to latch
parallel output data. While the converter is idling (Status Out·
put is "a"), the parallel output data from the most recent con·
version remains valid until the start of the next conversion
cycle.
SERIAL OUTPUT - Serial output data is provided only during
the conversion process and is in a NRZ (non·return to zero)
format. The data is coded the same as parallel c~tput data
and is synchronous with the internal clock. Each serial output
bit is valid 20nsec after the rising clock edge (serial output
data lags parallel output by one clock cycle, see timing
diagram) and can be strobed into a shift register by rising
edges of the internal clock.
SHORT CYCLE - For applications requiring fewer than 16
bits of resolution, MN6290/6291 can be truncated or short
cycled to the desired number of bits with a proportionate
decrease in the AID conversion time. To truncate at n bits,
simply connect the n + 1 bit output to the Short Cycle input
5-65
DIGITAL OUTPUT CODING
DIGITAL OUTPUT
ANALOG INPUT
Oto +10V
±5V
+F.S.
+ F.S. - 'I, LSB
+ 1f2F.S. + Y2 LSB
+ 'lzF.S. - % LSB
+1f2 F.S. -3/2LSB
+ V2 LSB
I
± 10V
MSB
a
LSB
1111 1111 1111 1111
1111 1111 1111 11111"
1000 0000 0000 ooort"
+F.S.
+ F.S. - 'I' LSB
+ % LSB
-% LSB
_3/2 LSB
- F.S. + '/, LSB
-F.S.
j/i/i/il flflfll flfIj/fi flflflfI"
0111 1111 1111 111ll'"
0000 0000 0000 000i/"
0000 0000 0000 0000
CODING NOTES:
1.
2.
3.
4.
For
For
For
For
10 Volts FSR, 1LSB for 16 Bits = 152.6"V. 1LSB for 14 Bits = 610.4"V.
20 Volts FSR, lLSB for 16 Bits = 305.2"V.1LSB for 14 Bits·= 1.22mV.
unipolar ranges, the coding is straight binary.
bipolar ranges, the coding is offset binary.
* Analog voltages listed are the theoretical values for the transitions indicated. Ideally, with the MN6290/MN6291 continuously converting, the
output bits indicated as ~will change from a "1" to a "0" or vice versa as
the input voltage passes through the level indicated.
EXAMPLE: For the ± 10V range, the transition from output code 1111
111111111111 to output code 1111111111111110 (or vice versa) will
+ 9.999542V (+ F.S. - 3/ 2 LSB). Subsequently,
any voltage greater than + 9.999542V will give a digital output of all
"1 's.'· The transition from digital output 0111111111111111 to 1000 0000
ideally occur at an input of
0000 0000 (or vice versa) wi II ideally occur at an input of - 0.000153 volts.
The 0000 0000 0000 0000 to 0000 0000 0000 0001 transition will occur at
- 9.999847V. An input more negative than this level will give all "a's."
INPUT RANGE SELECTION
Part
Number
o to
+ 10V
±5V
6290
6290
6291
GAIN ADJUSTMENT - Connect the gain potentiometer as
shown below and apply the input voltage at which the 1111
1111 1111 1110 to 1111111111111111 transition is ideally
supposed to occur. While continuously converting, adjust the
gain potentiometer until all the output bits are "1" and the
LSB "flickers" on and off. A 0.011'f capacitor should be con·
nected from Gain Adjust(pin 25) to Analog Ground (pins 9, 26).
Connect Pin 7
to Pin
Range
Ground
24
24
± 10V
OPTIONAL EXTERNAL ZERO AND GAIN ADJUSTMENTS Initial zero and gain errors may be trimmed to zero using
external potentiometers as shown in the following diagrams.
Adjustments should be made following warmup, and to
avoid interaction, zero should be adjusted before gain. Fixed
resistors can be ±20% carbon composition or better.
Multiturn potentiometers with TCR's of 100ppm/oC or less
are recommended to minimize drift with temperature. If these
adjustments are not used, pin 28 should be left open. A O.Q1l'f
capacitor should be tied from Gain Adjust (pin 25) to Analog Ground
(pins 9,26).
ZERO ADJUSTMENT - Connect the zero adjust poten·
tiometer as shown below. For unipolar ranges (MN62900nly),
apply the input voltage at which the 0000 0000 0000 0000 to
0000 0000 0000 0001 transition is ideally supposed to occur.
While continuously converting, adjust the zero potentiometer
until all bits are "0" and the LSB "flickers" on and off.
For bipolar ranges (MN6290 and MN6291), apply the input
voltage at which the 0111111111111111 to 1000 0000 0000
0000 transition is ideally supposed to occur. While con·
tinuously converting, adjust the zero potentiometer until all
bits are "flickering."
.
1.6M!!
flak!!
to
• 100k!1
~'~ o--w--'>
-15V
5-66
i
+15V
+ 15V
or
.
160k!1
160k!1
1Okll
~~~tolOOkll
22kO
_
-15V
I
+15V
Pin
10MI!
25~
Pins
9,26
J
10k!!
to
+15V
1M!l
270kll
or
0~~1 _15:00kll
100kll
lOkI!
to
100kO
-15V
THE INTERNAL T/H AMPLIFIER
As stated in the Description of Operation, MN6290/6291 's in·
ternal T/H amplifier is transparent to the user. The T/H's out·
put is connected directly to the AID's input and its operational
mode is controlled by the Timing and Control Logic (see
Block Diagram). The user is not required to supply additional
support timing circuits sometimes necessary when mating
an AID with its companion T/H. Additionally, MN6290/6291
users need not concern themselves with oftentimes confus·
ing TlH specifications like acquisition time, aperture· delay
time, aperture jitter, droop rate, etc .. These parameters are
not specified for MN6290/6291 and are, in fact, impossible to
directly test because the T/H's output and control line are not·
accessable at the device pins. Frequency·domain specifica·
tions like input bandwidth, sampling rate, signal·to·noise
ratio, harmonic distortion, etc. obviates the need for knowing
the specific T/H time·domain specifications, however, the
table on the following page does supply typical values for
those critical T/H performance specifications.
Note that the static errors (gain error, track-mode offset error,
and pedestal) of the T/H function add directly to the corresponding errors of the AID converter but that both are effectively nulled with the functional laser trimming of the AiD. T/H
offset error and pedestal, for example, add directly to AiDconverter offset error. However, when the AiD offset is functionally laser trimmed, it is done with the whole device sampling at a 20kHz rate and the T/H is in the hold mode whenever
trimming is actually performed. Consequently, all error
sources are compensated for. All static errors on
MN6290/6291 (accuracy error, unipolar offset error, bipolar
zero error, etc.) are tested and specified as full input-output
transfer specifications and include both the T/H and AiD.
OdB
Input Frequency: 4k"iz
Sampling Rate: 2O.5kHz
- 20dB
RMS Signal: - O.28dB
RMS Noise: - 85.63dB
-40dB -SOdB -
SIN: 85.35dB
2nd Harmonic: - 99.27dB
3rd Harmonic: - 91.98dB
-BOdB
-10OdB
-120dB
Typical T/H Performance Specifications
-l40dB
Gain Error
± 0.01 %
Gain Linearity Error
± 0.001 %FSR
.----------- --- ---- -----------------c-c--c----1
Track Mode Output Offset Error
± 0.5mV
Pedestal
± 0.5mV
-"-. -----Acquisition Time: 10V step to ± 0.003%
5psec
20V step to ± 0.003%
6psec
.,---------
Track·Hold Transient Settling (to ± lmV)
Slew Rate
Full Power Bandwidth
250nsec
±4V/pse~50kHz
---------------Effective Aperture Delay Time
- 25nsec
Aperture Jitter
0.5nsec
~~pR~;e
Hold·Mode Feedthrough Attenuation
± 0.05pV/psec
- B6dB
FREQUENCY-DOMAIN TESTING MN6290/6291 is
specified and tested statically in the traditional manner
(linearity, accuracy, offset error, current drains, etc.) and
dynamically in the frequency domain. In the dynamic tests,
MN6290/6291 is operated in a manner that resembles an application as a digital spectrum analyzer. A very low distortion
signal generator (harmonics -100dB) is used to generate a
pure, full-scale, 10kHz sine wave that MN6290/6291 samples
and digitizes at a 20.5kHz rate. These conditions (signal
period = 100l'sec, sampling interval = 48.8I'sec) approach
the Nyquist sampling limit (at least 2 samples per signal cycle; sampling frequency greater than 2 times signal frequency). A total of 512 sample-and-convert operations are
performed, and the digital output data is stored in a highspeed, FIFO, buffer-memory box. The 512 data points are then
accessed by a microcomputer which executes a 512-point
Fast Fourier Transform (FFT) after applying a Hanning
(raised cosine) window function to the data. The resulting
spectrum shows the amplitude and frequency content of the
converted signal along with any errors (noise, harmonic
distortion, spurious signals, etc.) introduced by the AiD converter. Subsequently, signal-to-noise ratio (SNR) and harmonic distortion measurements are read from the spectrum.
A functional block diagram of the test setup appears below,
and a sample spectrum appears above.
MN6290
MN6291
16·Bit
Sampling
AID
~.-~----
~
Frequency-Domain Testing
of AID Converters
Mini
Computer
10.25kHz
OHz
Input Frequency
The spectrum above is the real portion (imaginary portions of
spectra are discarded) of a 512-point FFT. The horizontal axis
is the frequency axis, and its rightmost end is equal to 1j, the
sampling rate (10.25kHz in this case). The horizontal axis is
divided into 256 frequency bins, each with a width of 40.04Hz.
Recall that the highest frequency on the frequency axis of the
spectrum of a sampled signal is equal to one-half the sampling rate and that input signals with frequencies higher than
1j, the sampling rate are effectively "undersampled" and
aliased back into the spectrum.
The vertical axis of the spectrum corresponds to signal
amplitude in rms volts relative to a full-scale sinusoidal input
signal (OdB). The sample spectrum above is the result of
averaging 10 512-point FFT's run on data taken from an
MN62900perating on its bipolar input range( ± 5V)with a fullscale input sine wave (v(t) = 5sinwt) at a frequency of 4kHz. In
the spectrum, the full-scale input signal appears at 4kHz at a
level of - 0.28dB. Full-scale rms signals do not appear at
- 3dB levels because our FFT program has been normalized
to bring them to zero. The d.c. component in the spectrum is
effectively the offset error of the MN6290 combined with that
of the signal generator and test fixture. A second harmonic, if
it were either present in the input signal or created by the
MN6290, would appear at 8kHz. If a third harmonic were present, it would be aliased back into the spectrum and appear
at 8.5kHz. Harmonic distortion and spurious noise levels are
calculated as the ratio (in dB) of the signal level to the
strongest harmonic or spurious (nonharmonic) signal in the
spectrum. In the sample spectrum above, the strongest harmonic is the third. It appears at a 'evel of - 92.26dB, and the
signal to harmonics ratio is equal to 91.98dB. Rms noise is
calculated as the rms summation of all nonfundamental and
nonharmonic components in the output spectrum, and SNR
is calculated as the ratio of the rms signal to the rms noise.
For the above spectrum, the normalized rms signal level is
- 0.28dB; the rms noise level is - 85.63dB; and the SNR is
85.35dB.
The term "noise" is generally used to describe what remains
in the output spectrum after all fundamental, harmonic, d.c.,
and outstanding spurious components have been removed. It
generally appears across all frequency bins at some relatively flat level sometimes referred to as the "noise floor". The
rms noise, as described above, represents the broadband
noise that would appear superimposed on the sinusoidal input signal if that signal were perfectly recreated from the
stored digital output data. Virtually all the noise in the output
spectrum is created either by the act of digitizing or by the AiD
converter itself.
5-67
Effective Resolution v.s. Input Frequency
MN5290, 40tl-sec, 16·Bit AID
OdB
OdB ;'"
Input Frequency:
Sampling Rate:
RMS Signal:
RMS Nolae:
SIN:
2nd Harmonic:
3rd Harmonic:
-20dB
-4OdB
Signal
Amplitude
Re1ativeto
Full Scale
I
-&OdB
4Hz
171 Hz
- O.59dB
- 81.81dB
81.21dB
-99.11dB
- 93.52dB
-2OdB
-4OdB
-OOdB + . . . . . . . . . . . . . . . . . . . . . -1.
-OOdB
-OOdB
-l00dB
-l00dB
-12Od8
-l2OdB
-14OdB
OH,
85.5Hz
85.5Hz
Input Frequency
Input Frequency
Input Frequency
SN.
100dB
.... B
....B
70dB
&OdB
SOdB
40dB
30dB
20dB
10dB
OdB
The three spectra above are each the result of
averaging 10 512-pt FFT's run on an MN5290 type
16-bit A/D converter without a companion T/H
amplifier. The input signal frequencies are respectively 4Hz, 40Hz, and 400Hz. The AID's conversion
time is approximately 40J.tsec, and the sampling
rates are respectively 171 Hz, 171 Hz, and 1.18kHz.
The accompanying plot shows the rapid (6dB/octave) degradation of SNR (effective resolution) with
increasing input frequency when SA type AID converters are used to digitize dynamically changing
input signals without the aid of a T/H amplifier.
810
20
40
80100 200
400
8001k
2k
4k
ak10k 20k
40k
80k 100k
Input Frequency (Hz)
Effective Resolution v.s. Input Frequency
MN6290, 20kHz, 16·Bit, Sampling AID
OdB
OdB T· .
.. .. ....... .... Input Frequency: 100Hz
-2OdB
-4OdB
-OOdB1--I··············································
Sampling Rate:
RMS Signal:
RMS NoJse:
SIN:
2nd Hannonlc:
3rd Hannonic:
5.21kHz
-O.27dB
-8S.99dB
85.71dB
- 89.1OdB
- 95.04dB
- 20dB
OdB T
j
i" ...................................+.....
t·
-4OdB~'
Input Frequency: 4kHz
Sampling Rate: 2005kHz
~~~ ~:~sa~~ :~=B
SJN: 85.35dB
I
-2OdB ~
i
-40dB .
I
2nd Hannonlc: - 99.27dB
3rd Harmonic: - 91.9BdB
-&OdB
Input Frequency:
Sampling Rate:
RMS Signal:
RMS Noise:
SIN:
2nd Harmonic:
3rd Harmonic:
10kHz
20.5kHz
- O.28c1B
- 85.71dB
85.43dB
- 90.47dS
- 94.89dS
-BOdS
2.61kHz
.N.
Input Frequancy
Input Frequency
100dBr--r--.--n,-.--,--"--.-~--TT--.--r--rr-,,-,---n
.... B ~~--~-H~1--1--4+--+--+--~--~~~H-~--4-~
.... B ~~--~-H~4r-1--~--+--+--~--~~~H-~~4-~
7OdB~~--~-H~4-~--~--+--+--~--~~~H-~-L4-~
00
&OdB ~~--~-H~4r-1--~--+--+--~--~~~H--1--1-~
SOdB ~~--~-H~4r-1--~--+--+--~--~~~H-~--4-~
40dB ~~--~~~4-~--~--+--+--~--~~~H-~--4-~
30dB ~~--~~~H--1--4+--+--+--~--~~~H--1--4-~
20dB ~~--~~~4r-1--~--+--+--~--~~-1H--1--1-~
10dB ~-+--~~~H--1--~--+--+--~--~~~H-~--4-~
OdB L--L__
__ __
__LL__
__
L--LL--L~
810
20
40
~
~-L
80100 200
400 8001k
Input Frequency (Hz)
5-68
L--L~LL~
2k
4k
8k1Ok 20k
J-~
40k &Ok 100k
The three spectra above are each the result of
averaging 10 512-pt FFT's run on an MN6290 16-bit
sampling AID. The input signal frequencies are
respectively 100Hz, 4kHz, and 10kHz, and the
sample/convert rates are respectively 5.21kHz,
20.5kHz, and 20.5kHz. The accompanying plot
shows that MN6290's internal T/H amplifier enables
the device to maintain near ideal SNR independent
of increasing input frequencies. Theaperturejitterof
the T/H is small enough to maintain SNR for undersampled input frequencies, i.e., for frequencies
greater than 10kHz.
In a simple, first- order analysis, the noise in the output spectrum of an AID converter can be traced to three sources, All
three of these noise sources have the potential to manifest
themselves as quaSi-random relative-accuracy errors in any
single AID conversion of a static signal and subsequently, the
potential to manifest themselves as broadband noise in a
series of conversions of a dynamically changing signal. Two
of these noise sources (quantization noise and converter
noise) are effectively constant and do not change with inputsignal frequency. The third (aperture noise) usually varies
linearly as a function of input-signal frequency, basically
doubling whenever input frequency doubles.
The third component of AID converter noise derives from the
fact that SA type AID converters (without companion T/H
amplifiers) cannot accurately convert dynamically changing
input signals. Because of the nature of the technique of successive approximations, it is imperative that AID's using this
technique maintain a stable input signal during their conversion (aperture) time. Slew rates in excess of (± ';' LSB) I (conversion time) can cause accuracy errors in any individual conversion. In a series of conversions of a sinusoidal signal, the
slew rate varies from sample to sample, and the consequent
aperture (slew-rate) errors manifest themselves as broadband noise.
Digitizing an analog signal quantizes it or "rounds it off".
Digitizing or quantizing an analog signal with a 16-bit AID
effectively "rounds off" the signal to one of 65,536 possible
discrete levels. This rounding off produces an inherent
accuracy error in that the digital output no longer exactly
represents the analog input. If one has an ideal AID converter
with all other accuracy-error sources driven to zero, the
actual value of rounding-off error or quantization error can be
as small as zero or as large as ± '12 LSB from conversion to
conversion. In a single conversion of a static input signal,
quantization error is simply an accuracy error. It is impossible
for a given conversion of an unknown signal to be more accurate than ± '12 LSB. In a series of conversions of a
dynamically changing signal, actual instantaneous quantization error vdries from sample to sample and manifests itself
as broadband noise. In the output spectrum, this noise limits
tile theoretically achievable signal-to-noise ratio to the
following:
This third component of AID noise is effectively eliminated by
MN6290/6291's internal T/H. The T/H's ability to instantaneously freeze the slewing input signal (limited only by the
T/H's aperture jitter) and hold it constant results in the AID
seeing a series of d.c. signals and not the sinusoid itself.
MN6290/6291's ability to maintain SNR over its full input
bandwidth (up to the "Nyquist frequency" or '12 the sampling
rate) is the result of the T/H's ability to limit the overall noise
to the quantization noise plus the noise inherent in the AID.
Ideal SNR = (6.02n
+ 1.76)dB
n = number of bits
For an ideal 16-bit AID. the theoretical noise floor in a
512-point FFT occurs around -122dB, and the theoretical
SNR is 98dB. For an ideal 14-bit AID and a 512-point FFT, the
numbers are - 110dB and 86dB respectively.
The second type of single-conversion accuracy error that
manifests itself as broadband noise in the output spectrum
results from the actual noise of the AID converter. This "converter noise" is frequently referred to as "transition noise"
and manifests itself, among other ways, by allowing certain
fixed, static, input signals to produce either of two adjacent
output codes from one conversion to the next. In most AID
converters, the transition from one given digital output code
to the next (or vice versa) does not always occur at exactly the
same analog input voltage. The "transition voltage" varies
from conversion to conversion, and this "transition noise"
(the band of adjacent-code uncertainty) is normally on the
order of ± 1/10 to ± 1/3 LSB. It is caused by broadband noise
and timing jitter in the AID's constituent components
(especially its comparator and reference circuit). In a single
given AID conversion, transition noise adds (or subtracts) to
the device's static differential linearity error. Again, this
phenomenon will manifest itself as an accuracy error in any
single conversion and as noise in any series of conversions of
a changing input signal.
This second noise component should be thought of simply as
the "converter noise". Recall that quantization noise is a
result of the digitizing process, and it limits SNR to some
theoretical value. Its effect is independent of the type or kind
of AID converter used. Converter noise is a function of how
"noisy" a selected AID converter may be, and it reduces actual measured SNR's toa level something below ideal. Hence
MN6290/6291 K and T models guarantee 84dB and not 86dB
initial room-temperature SNR.
The plots on the previous page demonstrate that an AID
without a companion T/H is effectively incapable of accurately converting analog input signals above some critical frequency (slew rate) and that the AID's SNR or "effective resolution" deteriorates at approximately 6dB/octave above that
frequency. Basically, the AID's quantization and converter
noise remain constant while its aperture noise doubles each
time the input frequency doubles.
;,;,N0290ii:J2:'J1 's i.ltemal 1/H efleci!veiy eliminates aperture
noise allowing the AID to maintain "low-frequency SNR" as
the actual input frequency increases.
The plot below graphically Illl:stl',,'es the princi,J'es we ilave
been discussing and focuses on AID converter noise, not on
SNR. Earlier, we discussed quantization noise (~Q)' converter
noise (~cl and slew rate or aperture noise (~A) and how each
individually contributes to broadband noise in an AID's output spectrum. The plot below illustrates the relationship of
the three noise components to each other as input signal frequency increases. If each of the three noise components is
expressed in r.m.S. terms, the total r.m.s. noise (~T) of the AID
converter will be the square root of the sum of the squares of
its respective noise components. The vertical axis of the plot
is the r.m.s. value of the AID converter's total noise expressed
in dB. The horizontal axis is the frequency of the AID's analog
input signal plotted on a logarithmic scale.
R.M.S.
Noise (dB)
1)
a
1+ 3dB
+ Conv. Noise
~l)a2+\lc21-----~~
Ie
Log Frequency (Hz)
5-69
At very low (approaching d.c.) input frequencies, aperture
noise effectively makes no contribution, and the total noise is
equal to the r.m.S. summation of quantization nOise and con·
verter noise. As explained earlier, this initial noise level is
greater than that solely attributable to theoretical quantization noise and is a constant term in the total r.m.S. noiseequa·
tion shown below.
~ Q = Quantization Noise
~ C = Converter Noise
~ A = Aperture Noise (slew·rate noise)
~ Total (r.m.s.)
As the input frequency increases, aperture noise begins to
come into play. At some critical frequency (fd, the contribu·
tion made by aperture noise will be equal to that of quantiza·
tion plus converter noise, and the total noise will have risen
3dB above its initial value (SNR drops 3dB). Aperture noise
increases 6dB for every octave increase in input frequency
and eventually overwhelms the other noise components
which have essentially remained constant. If one maintains a
constant input level while increasing the input signal fre·
quency through many decades, the plot of the AID's SNR vs.
input frequency should look like the inverse of the noise plot
shown on the previous page. This is demonstrated in the ac·
tual plots of SNR vs. frequency for the MN5290 shown
previously.
J~ Q (r.m.s.) 2 + "C (r.m.s.) 2 + "A (r.m.s.)'
=
~T= ~("Q2+"C2)+"A2
I
\
Constanl
Tenn
Frequency
Dependent
Tenn
ORDERING INFORMATION
Minimum
Sampling
Rate
Minimum
Input
Bandwidth
SNR
Bipolar
Specified
Temperature
Range
MN6290J
o to
+ 10V
±5V
O°C to + 70°C
13 Bits
±0.006%FSR
20kHz
10kHz
BOdB
-85dB
MN6290K
Oto +10V
±5V
O°C to + 70°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
- 88dB
MN6290S
o to
+ 10V
±5V
- 55°C to + 125°C
13 Bits
±0.006%FSR
20kHz
10kHz
80dB
- 85dB
MN6290S/B
Oto +10V
±5V
- 55°C to + 125°C
13 Bits
±0.006%FSR
20kHz
10kHz
80dB
- 85dB
MN6290T
o to
oto
+ 10V
±5V
- 55°C to + 125°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
-88dB
+ 10V
±5V
- 55°C to + 125°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
-B8dB
Input Voltage Range
Part
Number
MN6290T/B
Unipolar
No Missing
Codes
Integral
Linearity
MN6291J
N.A.
± 10V
O°C to + 70°C
13 Bits
±0.006%FSR
20kHz
10kHz
80dB
-85dB
MN6291K
N.A.
± 10V
O°C to + 70°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
- 88dB
MN6291S
N.A.
±10V
- 55°C to + 125°C
13 Bits
±0.006%FSR
20kHz
10kHz
80dB
- 85dB
MN6291S/B
N.A.
±10V
- 55°C to + 125°C
13 Bits
±0.006%FSR
20kHz
10kHz
80dB
-85dB
MN6291T
N.A.
± 10V
- 55°C to + 125°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
- 88dB
MN6291T/B
N.A.
± 10V
- 55°C to + 125°C
14 Bits
±0.003%FSR
20kHz
10kHz
84dB
88dB
Contact factory for availability of CH device types.
[1JJ
_
MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852·5400
5·70
Harmonics
U~Jj
_
MN6295
MN6296
LOW-DISTORTION,50kHz
16-Bit, SAMPLING
AID CONVERTERS
MICRO NETWORKS
DESCRIPTION
FEATURES
• 50kHz Sampling Rate
With Internal T/H Amplifier
• 25kHz Full-Power
Input Bandwidth
• 84dB Signal-to-Noise Ratio
Over Full Bandwidth
• -88dB Harmonics Over
Full Bandwidth
• FFT Testing
• Serial and Parallel Outputs
• 1.3 Watts Power Consumption
• 32-Pin Side-Brazed DIP
• Fully Specified DoC to +70°C
(J and K Models) or -55°C
to +125°G (S and T Models)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
32 PIN SIDE-BRAZED DIP
00010(0.251
0.030(0.76)
PIN 1
\
11
The MN6295/6296 Family of 50kHz, 16-bit, sampling AID
converters offers an outstanding combination of resolving
power, sampling rate, low noise and low harmonic distortion.
These SA type AID's are packaged in small, side-brazed,
32-pin, triple-wide DIP's and have internal track-hold (T/H)
amplifiers that enable them to accurately sample and digitize
25kHz full-scale input signals at rates up to 50kHz. The
package, including the internal T/H, is smaller than that of most
stand-alone 16-bit AID's. Each device is fully FFT (Fast Fourier
Transform) tested using contemporary DSP technology and
guarantees up to B4dB signal-to-noise ratio (SNR, rms-to-rms)
and up to -BBd8 harmonics and spurious noise.
I
MN6295 (10V input span) and MN6296 (20V input span) are
configured in a manner that makes their internal T/H completely
user transparent. A 2.5k!l input resistor isolates the T/H from its
signal source, and the T/H's operational mode is internally
controlled by the AID's status line. Users need only supply
start-convert pulses at the desired sampling rate. Each device
is fully tested both statically, in the traditional manner, and
dynamically with a series of 512-point FFT's. This type of
configuration and testing eliminates the need for potentially
confusing and misleading T/H specifications like aperture
delay, aperture jitter, charge injection, etc., and also eliminates
frustrating attempts to translate data-converter time-domain
specifications into frequency-domain performance.
0.10012.54)
T1
1564(4023)
The MN6295/6296 Family offers 4 electrical performance
grades (J,K,S and T part-number suffixes) and 2 operating
temperature ranges (ODe to +70 De and -55 De to +125 DC.
1500(3810)
1616(4105)
t
-j ~ ;H'11
~
~::~h~
~'~!J~)
:1(462)
IF=~~=~=fg;=~l=====J1 t
I---
0.900122661
--.J
I"f,;1O!.')
0020(051)
~~~::~
Dimensions in Inches
(millimeters)
~
April 1990
MICRO NETWORKS
324 Clark Sl., Worcester, MA 01606
(508) 852-5400
5-71
MN6295 MN6296 50kHz SAMPLING 16-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN6295J, K; MN6296J, K
MN6295S, SIB, T, TIB
MN6296S, SIB, T, TIB
Storage Temperature Range
Positive Supply (+Vcc, Pin 28)
Negative Supply (-Vcc, Pin 21)
Logic Supply (+Vdd, Pin 30)
Digital Inputs (Pins 31,32)
Analog Inputs (Pins 24, 25)
Analog Ground (Pin 22)
to Digital Ground (Pin 19)
Ref. Out (Pin 23) Short Circuit Duration
-55°C to + 125°C
O°C to +70°C
-55°C to +125°C
-55°C to +125°C
-65°C to +150°C
a to + 16.5 Volts
a to -16.5 Volts
Oto +7 Volts
to +5.5 Volts
±15 Volts
a
±1 Volt
Continuous to Ground
ORDERING INFORMATION
PART NUMBER
MN6295T/B CH
~
Select MN6295 or MN6296.
Select suffix J, K, SorT for
desired performance and specified
temperature range. - - - - Add "/B" to "S" or "T" models for
Environmental Stress Screening.
Add "CH" to "SIB" or "T/B" models
for 100% screening according to
MIL-H-38534.---------------'
Contact factory for availability of "CH"
device types.
DESIGN SPECIFICATIONS ALL UNITS (TA=+25OC, ±Vcc= ±15V, +Vdd=+5V unless otherwise indicated) (Note 1)
ANALOG INPUTS
TYP.
MIN.
a to
Input Voltage Ranges: MN6295
MN6296
MAX.
2.5
50
Input Impedance (Note 17): Resistance
Capacitance
UNITS
Volts
Volts
+10, ±5
±10
k[J
pF
DIGITAL INPUTS (Start, Short Cycle)
Logic Levels: Logic "1"
Logic "0"
+0.8
Volts
Volts
+40
-1.6
p.A
rnA
+0.4
Volts
Volts
+2.0
Logic Currents: Logic "1" (VIH =+2.4V)
Logic "0" (VIL = +0.4V)
DIGITAL OUTPUTS (Serial, Parallel, Status, Clock)
Output Coding (Note 2): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (lsource:s320p.A)
Logic "0" (l"nk:S 3.2mA)
CSB
COB
+2.4
INTERNAL REFERENCE
1
Volts
ppmloC
rnA
±15
+5
±15.5
+5.5
Volts
Volts
±0.003
±O.o03
±0.001
±0.02
±0.02
±0.01
%FSR/%Supply
%FSR/%Supply
%FSR/%Supply
Current Drains: +Vcc Supply
-Vcc Supply
+Vdd Supply
+42
-30
+48
+55
-40
+60
rnA
rnA
rnA
Power Consumption
1320
1725
mW
Reference Output (Pin 23): Voltage
Drift
Output Current (Notes 3. 17)
+9.9
+10
±15
+10.1
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc Supply
+Vdd Supply
Power Supply Rejection (Note 14): +Vcc Supply
-Vcc Supply
+Vdd Supply
5-72
±14.5
+4.5
PERFORMANCE SPECIFICATIONS (Typical TA =+25"C, ±Vcc = ± 15V, +Vdd= +5V unless otherwise indicated)
MN6295J
MN6296J
MN6295K
MN6296K
MN6295S
MN6296S
MN6295T
MN6296T
UNITS
Minimum Guaranteed Sampling Rate (Note 4)
Maximum AID Conversion Time (Note 5)
50
16
50
16
50
16
50
16
kHz
I'sec
Signal-to-Noise Ratio (SNR, Note 6):
Initial (+25°C) (Minimum)
Tmin to T max (Minimum, Note 7)
80
78
84
82
80
78
84
82
dB
dB
Harmonics and Spurious Noise (Note 8):
Initial (+25°C) (Minimum)
T min to Tmax (Minimum, Note 7)
-85
-82
-88
-85
-85
-82
-88
-85
dB
dB
Input Signal Full-Scale Bandwidth (Minimum, Note 9)
25
25
25
25
kHz
±0.006
±0.012
±0.003
±0.006
±0.006
±0.012
±0.003
±0.006
%FSR
%FSR
13
13
14
14
13
13
14
14
Bits
Bits
Unipolar Offset Error (Notes 10, 11):
Initial (+25°C) (Maximum)
Drift (Maximum)
Max Error Tmin to Tmax (Note 7, 15)
±0.05
±15
±0.12
±0.05
± 7.5
±0.084
±0.05
±15
±0.2
±0.05
±7.5
±0.125
%FSR
ppm of FSR/oC
%FSR
Bipolar Zero Error (Notes 10, 12):
Initial (+25°C) (Maximum)
Drift (Maximum)
Max Error Tmin to T max (Note 7, 15)
±0.075
±15
±0.15
±0.05
±10
±0.1
±0.075
±15
±0.225
±0.05
±10
±0.15
%FSR
ppm of FSR/oC
%FSR
Full Scale Accuracy Error (Notes 10, 13):
Initial (+25°C) (Maximum)
Drift (Maximum)
Max Error T min to Tmax (Note 7, 15)
±0.2
±30
±0.35
±0.1
±20
±0.2
±0.2
±30
±0.5
±0.1
±20
±0.3
%FSR
ppm of FSR/oC
%FSR
DYNAMIC CHARACTERISTICS
STATIC CHARACTERISTICS
Integral Linearity Error: Initial (+25°C) (Max. Note 16)
T min to T max (Maximum, Note 7)
Resolution for Which No Missing
Codes is Guaranteed: Initial (+25°C)
Tmin to Tmax (Note 7)
I
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data sheet.
2. CSB=complementary straight binary.
COB=complementary offset binary.
See table of transition voltages in section labeled Digital Output Coding.
3. In addition to supplying 1mA of current for bipolar offsetting purposes (pin 23
connected to pin 26), the internal reference is capable of driving up to 1mA into an external load. If the internal reference is used to drive an external load,
the load should not change during a conversion.
4. Minimum guaranteed sampling rate refers to the fact that these devices
guarantee all other performance specs while sampling and digitizing at a 50kHz
rate. Obviously, devices may be operated at lower sampling frequencies if
desired and typically will meet all performance specs while sampling at rates
of 55kHz or higher.
5. Whenever Status (pin 18) is low (logic "0"), the internal TIH is in the track mode,
and the ND converter is not converting. When Status is high (the definition of
ND conversion time), the TIH is in the hold mode, and the ND is performing
a conversion.
6. This parameter represents the rms-signal-to-rms-noise ratio in the output spectrum (excluding harmonics) with a full-scale input sine wave (OdB) at any frequency up to 25kHz.
7. MN6295J, K and MN6296J, K are fully specified for DOC to +70°C operation.
MN6295S, SIB, T, T/B and MN6296S, SIB, T, T/B are fully specified for -55°C
to +125°C operation.
8. This parameter represents the peak signal to peak non-fundamental component (harmonic or spurious, inband or out of band) in the output spectrum.
9. This is the highest-frequency, full-scale, input signal for which the SNR and harmonic figures are guaranteed when sampling at a 50kHz rate.
10. Adjustable to zero with external potentiometer.
11. Unipolar offset error is defined as the difference between the ideal and the actual input voltage at which the digital output just changes from 0000 0000 0000
0000 to 0000 0000 0000 0001 when operating the MN6295 on its unipolar range.
The ideal value at which this transition should occur is - 'hLSB. See Digital
Output Coding.
12. Bipolar zero error is defined as the difference between the ideal and the actual input voltage at which the digital output just changes from 1000 0000 0000
0000to0111111111111111 when operating the MN629516296 on abipolarrange.
The ideal value at which this transition should occur is +'hLSB. See Digital
Output Coding.
13. Full scale accuracy specifications apply at negative full scale for unipolar input ranges and at both positive and negative full scale for bipolar input ranges.
Full scale accuracy error is defined as the difference between the ideal and
the actual input voltage at which the digital output just changes from 1111 1111
11111110 to 1111111111111111 for unipolar and bipolar input ranges. Additionally,
it describes the accuracy of the 0000 0000 0000 0000 to 0000 0000 0000 0001
transition for bipolar input ranges.
14. Power supply rejection is defined as the change in the analog input voltage at
which the 1111 1111 1111 1110 to 1111 1111 1111 1111 or 0000 0000 0000 0000
to 0000 0000 0000 0001 output transitions occur versus a change in powersupply voltage.
15. Listed maximum
error~er-temperature
specifications for unipolar offset,
bipolar zero and full scale accuracy correspond to the combination of maximum
room-temperature errors and worst case drift conditions to describe the worst
case error that might be encountered over the entire specified temperature
range.
16. ±0.006%FSR is equivalentto ± V,LSB for 13 bits and is equal to ±0.6mV for
a device with a 10V full scale range (0 to -1OV or ± 5V input range).
±0.003%FSR is equivalentto ± V. LSB for 14 bits and is equal to ± O.3mV for
a device with a 10V full scale range.
17. These parameters are listed for reference only and are not tested.
Specifications subject to change without notice as Micro Networks reserves the
right to make improvements and changes in its products.
5-73
BLOCK DIAGRAM
Timing and
Control
Logic
Start Convert (31)
0
- 15V Supply (21) 0
+ 5V Supply (30) ()
Ground (22) 0
Ground (19) 0
Ref. Output (23)
t--
I
Status (E.O.C.) (18)
+ 15V Supply (28)
(20) CI ock Output
(32) Sh ort Cycle
(17) Se rial Output
Successive Approximation Register
(1)
(2)
(3)
(4)
Bit
Bit
Bit
Bit
1 (MSB)
2
3
4
(5) Bit 5
(6) Bit 6
~
"
"
~
(7) Bit
(8) Bit
(9) Bit 9
(10) Bit 10
~
(11) Bit 11
(12) Bit 12
(13) Bit 13
(14) Bit 14
(15) Bit 15
(16) Bit 16 (LSB)
B~
Gain Adjust (29)
16-Bit DIA Converter
Comparator
~[>-
Offset Adjust (27)
~
Bipolar Offset (26)
10V Input (MN6295) (25)
20V Input (MN6296) (24)
10kl)
I
-
r
1. For unipolar operation (MN6295 only) pin 26 shou Id be grounded.
2. For bipolar operation (MN629516296) connect pin 26 to pin 23.
3. For MN6295, connect input to pin 25. Pin 24 is a " no connect.
For MN6296, connect input to pin 24. Pin 25 is a " no connect".
+
.,..
NOTES:
~
--
lOkI!
to
.
or
180kl!
10k \!
180kl!
to
100kl!
±30V/"sec
100kll
22kl!
_
-15V
-15V
500kHz
-25nsec
0.4nsec
± 0.05"VI"sec
-B6dB
PARALLEL OUTPUTS-During the successive approximation process the weight of each bit is compared to the value of the analog
input voltage. The converter is reset to MSB-01111111 1111 1111-LSB
by the rising edge of the first clock pulse. Subsequent rising clock
edges set the bit previously tested to its final state and brings the
next bit to be tested to a logic "0". This process continues until all
bits have been tested and Status returns to a logic "0". Valid parallel
output data can only be latched at the end of the sample/conversion
cycle.
The LSB bit is valid 20nsec prior to the falling edge of Status (E.O.G.),
therefore, this edge may be used to latch parallel output data. While
5-76
the converter is idling (Status is "0"), the parallel output data from
the most recent conversion remains valid until the start of the next
conversion cycle.
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
below and apply the input voltage at which the 1111 1111 1111 1110
to 11111111 11111111 transition is ideally supposed to occur. While
continuously converting, adjust the gain potentiometer until all the
output bits are "1" and the LSB "flickers" on and off. A 0.01p.f
capacitor should be connected from Gain Adjust (pin 29) to Ground.
l
.
Pin
10MI!
29~
Pins
19.22
J
om
10k'!
to
100kl!
"F -15V
!
+ 15V
+ 15V
1 Mil
270kll
or
100kl!
lOkI!
to
100kll
-15V
PIN DESIGNATIONS
•
32
16
17
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
PIN 1
Bit 1 (MSB)
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
BitB
Bit9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16 (lSB)
DIGITAL OUTPUT CODING
-10V
Digital Output
±5V
0
-'hlSB
- Y2F.S.+3i2lSB
- Y2 F.S. + Y2 lSB
-lhF.S._1hLSB
-F.S.+3/2lSB
-F.S.
Short Cycle
Start Convert
+5V Supply (+Vdd)
Gain Adjust
+15VSupply(+Vcc)
Offset Adjust
Bipolar Offset
10V Input (MN6295; N.C. MN6296)
20V Input (MN6296; N.C. MN6295)
Reference Output (+ 10V)
Ground
-15V Supply (-Vee)
Clock Output
Ground
Status
Serial Output
INPUT RANGE SELECTION
Analog Input
oto
32
31
30
29
2B
Z7
26
25
24
23
22
21
20
19
1B
17
I
±10V
MSB
+F.S.
+F.S._lhlSB
+3i2lSB
+Y2lSB
-'hlSB
-F.S. +3i2lSB
-F.S.
LSB
0000 0000 0000 0000
0000 0000 0000 OOO~
0111 1111 1111 111~"
JlJIIIJI JlJI~J6 JI~JI~ ~J6J1J1"
1000 0000 0000 0001"
111111111111111!1"
1111 1111 1111 1111
Part
Number
6295
6295
6296
Range
Connect Pin 26
to Pin
Oto -10V
±5V
±10V
Ground
23
23
CODING NOTES:
1.
2.
3.
4.
For
For
For
For
10 Volts FSR, 1LSB for 16 Bits=152.6~V. 1LSB for 14 Bits=610.4~V.
20 Volts FSR, 1LSB for 16 Bits=305.2~V. 1LSB for 14 Bits=1.22mV.
unipolar ranges, the coding is straight binary.
bipolar ranges, the coding if offset binary.
EXAMPLE: For the ± 10V range, the transition from output code 0000 0000 0000
0000 to output code 0000 0000 0000 0001 (or vice versa) will ideally occur at an
input of +9.999847V (+F.S. -lhLSB). Subsequently, any voltage greater than
+9.999847V will give a digital output of all "D's." The transition from digital out·
put 0111 1111 11111111 to 1000000000000000 (or vice versa) will ideally occur
at an input of +0.000153 volts. The 1111111111111110to 1111111111111111 tran·
sition will occur at -9.999542V. An input more negative than this level will give
all "1's."
"Analog voltages listed are the theoretical values for the transitions indicated.
Ideally, with the MN6295JMN6296 continuously converting, the output bits
indicated as (J will change from a "1" to a "0" or vice versa as the input voltage
passes through the level indicated.
ORDERING INFORMATION
Part
Number
MN6295J
MN6295K
MN6295S
MN6295S1B (1)
MN6295S1B CH(2)
MN6295T
MN6295T/B (1)
MN6295T/B CH(2)
MN6296J
MN6296K
MN6296S
MN6296S/B (1)
MN6296S/B CH(2)
MN6296T
MN6296T/B (1)
MN6296T/B CH(2)
Specified
Temperature
Range
Input Voltage Range
Unipolar
Bipolar
Oto -10V
oto -10V
Oto -10V
Oto -10V
Oto -10V
oto -10V
oto -10V
Oto-10V
NA
NA
NA
NA
NA
NA
NA
N.A.
±5V
±5V
±5V
±5V
±5V
±5V
±5V
±5V
±10V
±10V
±10V
±10V
±10V
±10V
±10V
±10V
OOCto
OOC to
-55°C to
-55°Cto
-55°C to
-55°C to
-55°Cto
-55°C to
OOCto
OOCto
-55°C to
-55°C to
-55°Cto
-55°C to
-55°C to
-55°C to
+70 oC
+70oC
+ 125°C
+125°C
+ 125°C
+125°C
+125°C
+ 125°C
+70 oC
+70 oC
+ 125°C
+ 125°C
+125°C
+ 125°C
+ 125°C
+ 125°C
No Missing
Codes
Integral
Linearity (3)
Minimum
Sampling
Rate
Minimum
Input
Bandwidth
SNR
Harmonics
13 Bits
14 Bits
13 Bits
13 Bits
13 Bits
14 Bits
14 Bits
14 Bits
13 Bits
14 Bits
13 Bits
13 Bits
13 Bits
14 Bits
14 Bits
14 Bits
±0.006%FSR
±0.003%FSR
±0.OO6%FSR
±0.006%FSR
±0.006%FSR
±0.003%FSR
±0.003%FSR
±0.003%FSR
±0.006%FSR
±0.003%FSR
±0.006%FSR
±0.006%FSR
±0.006%FSR
±0.003%FSR
±0.003%FSR
±0.003%FSR
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
50kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
25kHz
BOdB
B4dB
BOdB
BOdB
BOdB
B4dB
B4dB
B4dB
BOdB
B4dB
BOdB
BOdB
BOdB
B4dB
B4dB
B4dB
-B5dB
-BBdB
-B5dB
-B5dB
-B5dB
-BadB
-BBdB
-BadB
-B5dB
-BBdB
-B5dB
-BSdB
-B5dB
-BBdB
-BBdB
-BadB
Notes:
1. Includes Environmental Stress Screening.
2. Contact factory for availability of CH device types.
3. ±O.006%FSR is equivalent to ± '12LSB for 13 bits.
±O.003%FSR is equivalent to ± 'hLSB for 14 bits.
5·77
I
~ MICRO NETVVORKS
[1JJ
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
5-78
MN6400
O::JJ
_
MICRO NETWDRKS
50kHz, 16-Bit
SELF-CALI BRATI NG
SAMPLING ND CONVERTER
DESCRIPTION
The MN6400 is a complete self-calibrating, 16-bit, 50kHz
Sampling AID converter. Each Sampling AID contains an
inherent TIH function, analog input buffer amplifier, reference,
timing and control logic circuitry, microprocessor interface and
parallel data bus driver making it the most complete device of its
kind: These Sampling AID converters are packaged in small,
28-pm, side-brazed, double-wide DIPs. The inherent T/H function allows these devices to accurately sample and digitize
dynamically changing analog input signals at rates up to 50kHz.
The package, including all of the functions, is smaller than that
of most stand-alone 16-bit AIDs. Each device is fully tested using
contemporary FFT (Fast Fourier Transform) technology and
guarantees frequency-domain performance - no more guesswork in converting time-domain specifications (linearity,
accuracy, etc.) into frequency-domain performance.
FEATURES
• Self-Calibrating AID Provides
True 16-bit Performance
• 50kHz Sampling Rate with
Inherent T/H Function
• 16-Bit No-Missing-Codes
Guaranteed Over Full Operating
Temperature Range
• Complete Contains:
T/H Function
Analog Input Buffer
Reference
Timing and Control Logic
f.tP Interface
Parallel Data Bus Driver
• ±1LSB Integral Linearity
• 88dB SNR, -98dB Harmonics
• 740mW Maximum Power
Consumption
• Fully specified O°C to +70OC
(J and K Models) or -55°C to
+125°C (S and T Models)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
28 PIN SIDE-BRAZED DIP
The MN6400 offers four analog input voltage ranges (0 to +5V,
~ to .+ 1~V~ ±5V and ± 10V) whose Bipolar and Unipolar operation IS digitally controlled. These devices may be operated from
the .internal clock, or for critical sampling applications, these
deVices may be operated from a low-jitter crystal clock circuit.
Serial output data is provided synchronized to the serial clock
output. The internal parallel data bus driver with its 3-state outputs enables the MN6400 to connect directly to system data
buses without loading concerns.
The MN6400 offers users four electrical performance grades
(J,K,S and T models) and two operating temperature ranges
(O°C to +70°C and -55°C to +125°C) In addition, Sand T
models are available with environmental stress screening.
Contact factory for availability of fully compliant MIL-H-38534
devices.
,
PIN I
! \' Dimensions in Inches
.
(millimeters)
[1lJ
_
January 1992
Copyright(c)1992
Micro Networks
MICRO NETWORKS
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
5·79
1:-_
-
MN6400 50kHz 16·Bit SELF·CALIBRATING SAMPLING AID CONVERTER
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN6400J,K
MN6400 S,T
Storage Temperature Range
~ 15V Supply (+Vce, Pin 15)
-15V Supply (-Vee, Pin 14)
+5V Supply (+Voo, Pin 21)
Digital Inputs:
(Pins 10, 11, 12, 13,22,23,24)
Analog Inputs: (Pins 17, 18)
DESIGN SPECIFICATIONS (T A
ORDERING INFORMATION
-55°C to + 125°C
OOC to +70 oC
-55°C to + 125°C
-65°C to + 150°C
to +16.5 Volts
to -16.5 Volts
-0.3 to +6.0 Volts
o
o
PART NUMSER
S,""
~ S On and
for desiredJperformance
,off"
specified temperature range.
Add "IS" suffix to "S" or "T" models
for Environmental Stress Screening.
Add "CH" to "SIS" and "TIS" models
for MIL-H-38534 compliant devices.
-0.3 to +Voo +0.3V
±Vee
=+25"C, ±Vcc =± 15V, +VDD =+5V unless otherwise specified) (Note 10)
ANALOG INPUTS
MIN,
Input Voltage Ranges:
5V Input
TYP,
Oto
-510
Oto
-10 to
10V Input
Input Impedance:
III
MN6400T/S CH
5V Input
MAX,
+5
+5
+10
+10
Volts
Volts
Volts
Volts
kO
kO
5
10
lOV Input
UNITS
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "0"
+0.8
Volts
Volts
±10
±10
pA
pA
+0.26
Volts
Volts
±10
pA
+4.55
±10
Volts
ppm/DC
+2.0
Logic Currents: Logic "1" (VIH = +2.4V)
Logic "0" (VIL = +0.4V)
DIGITAL OUTPUTS
Logic Levels: Logic "1" (IOH = +6.0mA)
Logic "0" (IOL=-6.0mA)
+3.9
+4.3
+0.16
30State Leakage Current
INTERNAL REFERENCE
Reference Output: Voltage (Note 11)
Drift
+4.45
+4.5
±3
POWER SUPPLY REQUIREMENTS
Power Supply Range: ±Vcc Supply
+Voo Supply
±11.4
+4.5
±15
+5
±16.5
+5.5
Volts
Volts
±.0001
±.OO01
±.OO01
±.001
±.001
±.001
%Fs/%VS
%Fs/%VS
%Fs/%VS
Current Drains: +Vee Supply
-VccSupply
+VooSupply
+5
-20
+14
+10
-31
+25
mA
mA
mA
Power Consumption
445
740
mW
Power Supply Rejection: +Vcc Supply
-Vee Supply
+Voo Supply
SPECIFICATION NOTES:
1. External Master Clock frequency set to 4MHz, synchronous sampling mode and
background calibration disabled.
2. Specification listed applies after calibration at any temperature within the specified
temperature range.
3. Specification listed applies over the specified temperature range after inijial calibration at 25°c'
4. Specification listed applies after calibration at 25°C,
5. Unipolar offset error is defined as the difference between the ideal and the actual
input voltage at which the digital output changes from 0000 0000 0000 0000 to 0000
0000 0000 0001 when operating the MN6400 on a unipolar range.
6. Bipolar zero error is defined as the difference between the ideal and actual input
voltage at which the digital output changes from 0111 1111 1111 1111 to 10000000
0000 0000 when operating the MN6400 on a bipolar range.
7. Full scale absolute accuracy ennr includes offset, gain, linearity, noise, and all other
errors. Full scale absolute accuracy specifications apply at positive full scale for
unipolar input ranges and at both poSitive and negative full scales for bipolar input
ranges. Full scale absolute accuracy error is defined as the difference between the
ideal and the actual input voltage at which the digital output changes from 1111 1111
1111 1110 to 1111 1111 1111 1111 for unipolar and bipolar input ranges. Additionally,
it describss the accuracy of the 0000 0000 0000 0001 to 0000 0000 0000 0000 transition for bipolar input ranges.
5-80
8. This parameter represents the rms-signal-~rms-noise ratio in the output spectrum
(excluding harmonics) wijh a full scale analog input sine wave (OdB) at the specified
frequencies.
9. This parameter represents the peak-ta-peak non-fundamental component (harmonic or spurious, inband or out of band) in the output spectrum.
10. External Master Clock frequency set to 4MHz and operated in the synchronous
sampling mode.
11. Reference output is to bs bypassed to Analog Ground with a 1O~F capaCitor in
parallel with an 0.1,.F capacitor. Reference must not be used for applications circuits without buffering.
PERFORMANCE SPECIFICAiiONS (lYpical at +25"C, ±Vcc
=± 15V, +VDD =+5V unless otherwise indicated) (Note 1)
STATIC CHARACTERISTICS
Integral Linearity Error (Max) (Note 2)
Integral Linearity Error (Max) (Note 3)
Minimum Resolution for Which No Missing
Codes is Guaranteed (Note 3)
MN6400J
MN6400K
MN6400S
MN6400T
UNITS
±O.OOt5
±0.0022
±0.0015
±0.0015
±0.0015
±0.0022
±0.0015
±0.0015
%FSR
%FSR
16
16
16
16
Bits
Unipolar Offset Error (Notes 4, 5)
Initial (Maximum)
Drift (Maximum)
±0.03
±4
±0.02
±2.5
±0.03
±4
±0.02
±2.5
%FSR
ppm of FSRloC
Bipolar Zero Error (Notes 4, 6)
Initial (Maximum)
Drift (Maximum)
±0.03
±4
±0.02
±2.5
±0.03
±4
±0.02
±2.5
oloFSR
ppm of FSRloC
Full Scale Accuracy Error (Notes 4, 7)
Initial (Maximum)
Drift (Maximum)
±0.1
±15
±.05
±10
±0.1
±15
±.05
±10
%FSR
ppm of FSRloC
50
16.25
50
16.25
50
16.25
50
16.25
kHz
I'sec
85
81
83
85
81
83
88
84
79
88
84
85
82
79
85
82
dB
dB
dB
dB
-96
-90
-94
-88
-98
-92
-96
-90
-96
-90
-94
-88
-98
-92
-96
-90
dB
dB
dB
dB
DYNAMI.C CHARACTERISTICS
Minimum Guaranteed Sampling Rate
Maximum AID Conversion Time
Signal-to-Noise Ratio (Notes 3, 8):
Initial (+25°C): 1kHz Full Scale Input (Minimum)
12kHz Full Scale Input (Minimum)
T min to T max: 1kHz Full Scale Input (Minimum)
12kHz Full Scale Input (Minimum)
Harmonics and Spurious Noise (Notes 3, 9):
Initial (+25°C): 1kHz Full Scale Input (Maximum)
12kHz Full Scale Input (Maximum)
T min to T max: 1kHz Full Scale Input (Maximum)
12kHz Full Scale Input (Maximum)
I
BLOCK DIAGRAM
+1SV Supply (15) 0>-----0-
0----
-1SV Supply (14)
+SV Supply (21) 0 > - - - - Analog Ground
(19. 20) 0 > - - - - -
Digital Ground
(9) 0>-----0-
SV Analog Input (18) 0 - - - - - - ,
lOV Analog Inpul (17) o---"VVV\'-"'-"V'VVv--9--i Input
Buffer
Bus
Driver
l6-Bit
Self-Calibrating
NO
Converter
Reference Output
(16)
Clock Input
(10)
Data/Statu$
(11)
(12)
BipolarltJnipolar (13)
3-StateIRead
Reset (22)
Background Calibration
Start Convert
(1) Bil BlLSBlS1
(2) Bi17115182
(3) Bit6l141S3
(4) Bit 5113154
(5) Bi14112/8S
(6) Bil3l11186
(7) Bit 2110187
(8) M8B1Bit 9/S8
(25) Serial Data Output
(26) Serial Clock Output
(27)
Conversion Status
(28) Acquisition Status
Timing
and
Control
Logic
(23)
(24)
5-81
PIN DESIGNATIONS
Pin 1
14
28
15
Bit 8/Bit 16 (LSB) or S1
28
Acquisition Status
2
Bit 7/Bit 15 or S2
27
Conversion Status
3
Bit 6 IBit 14 or S3
26
Serial Clock Output
4
Bit 5 IBit 13 or S4
25
Serial Data Output
5
Bit 4/Bit 12 or S5
24
Start Convert
6
Bit 3/Bit 11 or S6
23
Background Calibration
7
Bit 2/Bit 10 or S7
22
Reset
8
Bit 1 (MS8)/Bit 9 or S8
21
+5V Supply (+VDD)
Digital Ground
20
Analog Ground
10
Clock Input
19
Analog Ground
9
11
Data/Status
18
5V Analog Input
12
3-State/Read
17
10V Analog Input
13
Bipolar/Unipolar
16
Reference Output ( +4.5V)
14
-15v/-12V Supply (-Vce)
15
+15V/+12V Supply (+Vcc)
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - The MN6400 is a 16-bit
Sampling AJD converter containing an inherent, user-transparent
T/H function and features self-calibration, JLP-interface logic and an
8-bit parallel data bus driver. Self-calibration and the inherent T/H
function enable the MN6400 to accurately sample and digitize
dynamically changing analog input signals at a 50kHz throughput
rate.
The MN6400 is designed to operate from ± 12 or ± 15V and +5V
power supplies and an external or internally generated Master
Clock. After power-up, the MN6400 must be reset by bringing Reset
(pin 22) high for a minimum of 100nsec. Bringing Reset high clears
the internal logic circuitry while returning Reset low initiates a full
calibration cycle. Full calibration cycles require 1,441,020 Master
Clock cycles (360.255msec with external4MHz Master Clock applied). Conversion Status (pin 27) is high during calibration and
returns low when complete.
After calibration, conversions can be initiated by the falling edge of
Start Convert. The signal applied to Start Convert (pin 24) must remain low for a minimum of one Master Clock cycle plus 50nsec. This
translates into 300nsec with the use of an external4MHz clock. Start
Convert must return high prior to the end of the conversion cycle
(65 clock cycles, 16.251'sec with 4M Hz clock) to allow sufficient time
for the next sample to be acquired.
With the conversion complete, output data and converter status
information may be read using various combinations of input controllines. Both serial and parallel data are available. Serial data is
available at Serial Data Output (pin 25) and is syncronous and valid
with the rising edges of Serial Data Clock Output (pin 26). Serial
data is presented MSB first, and is only available during the conversion cycle. Parallel data is available in two 8-bit bytes. Once a
conversion is complete and Data/Status (pin 11) is set high, parallel
output data is read by bringing 3-State/Read low. MSB-byte data
(MSB-bit 8) is lirst to be presented to data output lines (pins 1-8).
Toggling 3-State/Read (that is, to bring it high and then low again)
presents LSB-byte data. Output data lines are in the high-impedance
state when 3-State/Read is high.
In addition to conversion data, device status information can also
be accessed via the 8-bit data lines (pins 1-8). Status information
is presented when Data/Status is set low. A detailed description of
the types of status information which is provided and the pin locations of this information appear in the section labeled Parallel Output Pin Description - Status Information.
5-82
POWER SUPPLIES AND LAYOUT - The MN6400 is powered from
standard supply voltages of + 12/15V (pin 15), -12/15V (pin 14) and
+5V (pin 21). The analog ground (pins 19,20) and digital ground (pin
9) are separated to minimize analog and digital circuit interaction.
The analog ground is internally used as a reference point, therefore
it should be used as the system analog ground reference point. Care
must be taken to reduce the system noise to a level below the
MN6400's high-resolution conversion capability.
It is recommended that the power supplies be decoupled in the
following manner. The +12/15Vand -12/15V supplies should be
bypassed with a 0.01 JLf capacitor in parallel with a 0.47 JLF capacitor
to analog ground. The +5V supply, which powers both analog and
digital internal circuitry, should be bypassed with a 0.1 JLf capacitor
in parallel with a 0.01 JLf capacitor to analog ground. The optimum
value decoupling capacitors to use may vary depending on the users
system noise characteristics.
Pm" C
047"F
P,,,919 20 C
Pm 14
0~7"F
I I'
Power Supply Oecoupling
v
rO O1 ,,,
Ir
I
I
I
Gmocd
Pm"c
ol 1F
I
1
I
'V ee
IoollF
PinS. 9 19.20 C>--4-~-~-""'- Ground
001'''V''
DEVICE CALIBRATION - The MN6400 features two usercontrolled self-calibration modes of operation. Self-calibration
insures optimum performance at any temperature and at any time
throughout the lifetime of the device. Self-calibration also eliminates
the need for additional external circuitry to maintain operation of the
device within specification.
The first mode of calibration is called reset, and its initiation is controlled with Reset (pin 22). A reset calibration must be performed
after the device is powered-up, and can be repeated optionally after
the device reaches its operating temperature. The required initial
reset is initiated by strobing the Reset pin high for a minimum of 100
nsec. When Reset is brought high, internal logic clears. When Reset
returns low, a Single full calibration lasting 1,441,020 master clock
cycles begins (360.255 msec w/4 MHz clock). During reset the Conversion Status (pin 27) output will be in a high state, and will fall low
upon completion of calibration.
The reset mode of calibration can be initiated by either hardware
using a power-up reset circuit or by software in microprocessor control applications. Care must be taken to avoid an inadvertent reset
brought about by bringing 3-State/Read (12), Data/Status (pin 11)
and Start Convert (pin 24) low simultaneously.
The second mode of calibration is called background calibration,
which is activated by either tying Background Calibration (pin 23)
to digit~ound or bringing Background Calibration and
3-State/Read (pin 12) both low. This mode differs from reset calibra·
tion in that a fractional portion of the total calibration time is added
to the end of each conversion. After 72,051 conversions, the calibration cycle is complete. The conversion time of the device when
background calibration is active is extended by 20 master clock
cycles (5l'sec w/4 MHz clock). Except for the decrease in throughput
rate, the background calibration mode is transparent to the user.
MASTER CLOCK - The MN6400 operates from a master clock that
can be supplied externally or generated internally depending upon
the signal applied to Clock Input (pin 10). A logic low on this pin will
activate the 2 MHz minimum internal clock. Optionally, the user can
supply a TTL or CMOS system clock with a maximum frequency
of 4MHz (100kHz minimum) to the Clock Input. All device timing
characteristics scale to the master clock frequency. The internal
oscillator exhibits relatively high jitter compared to crystal OSCillators,
which may affect performance in some sampling applications.
INITIATING CONVERSIONS - A falling edge on the Start Convert
(pin 24) digital input will set the device into the hold mode and initiate a conversion cycle. The Start Convert input must remain low
for a minimum of one master clock cycle plus 50 nsec (300 nsec
w/4 MHz clock). It must return high before the minimum conversion
time of 65 clock cycles (16. 25!'5ec w/4 MHz clock) to allow sufficient
time for acquisition of the next sample.
T/H ACQUISITION - The MN6400 is a sampling AID converter,
therefore it requires a finite amount of time to accurately acquire an
analog input signal before performing a conversion. At the completion of a conversion, signalled by the falling of Conversion Status
(pin 27), the device automatically enters the acquisition mode and
begins to track the analog input. A minimum acquisition time of six
master clock cycles plus 2.251'sec (3.75I'sec w/4 MHz clock) is required to acquire the input signal. When sufficient time has elapsed after a conversion for the acquisition of the input signal, the
Acquisition Status (pin 28) output will fall low. It returns high on initiation of a new conversion cycle. When driving the MN6400 from
a high source impedance, the necessary acquisition time should
be extended to allow for the resultant increase in the input settling
time constant.
The MN6400's acquisition circuitry operates from a delayed and
divided down internal clock frequency of V. times the master clock.
If sampling is not synchronized to this internal clock, a sample will
be synchronously taken but may not be converted until up to four
master clock cycles later (1!'5ec w/4 MHz clock). In ather words,
when Start Convert goes low and is not synchronous with the internal clock, a maximum of four master clock cycles may occur
before Conversion Status goes high. This asynchronous uncertainty
adds these four master clock cycles plus 235 nsec of internal clock
delay (1.235I'sec w/4 MHz clock) to the conversion time.
When performing an asynchronous sampling operation, the device
can operate at 69 master clock cycles plus 235 nsec for conversion
and six master clock cycles plus 2.251'sec for acquisition for a total
of 75 master clock cycles plus 2.4851'sec (21.235I'sec w/4 MHz
clock). This corresponds to a 47.1 kHz maximum throughput rate.
Although the sample is asynchronously converted, the sample itself
is taken synchronously upon the falling edge of Start Convert. This
is particularly important to users in DSP applications.
To synchronize the sampling operation to the internal clock, the Acquisition Status (pin 28) output can be connected to the Start Convert (pin 24) input. The Acquisition Status output is synchronized
to the internal clock, thereby eliminating the sampling uncertainty
and enabling device operation at 65 master clock cycles for conversion and 15 master clock cycles for acquisition for a total of 80
master clock cycles (20l'sec w/4 MHz clock). This corresponds to
a 50kHz maximum throughput rate.
ANALOG INPUTS - The MN6400 can be operated in four userselectable input voltage range configurations. They are 0 to +5V,
±5V, 0 to +10Vand ± 10V. The 5V Analog Input(pin 18) is used for
5V full scale analog inputs, and the 10V Analog Input (pin 17) is used
for 10V full scale analog inputs. Selection of a unipolar or bipolar
input transfer function is made with the Bipolar/Unipolar digital input
(pin 13). A logic high on this pin selects a bipolar transfer function'
of analog input voltage between -Full Scale and +Full Scale. A
logic low on this pin selects a unipolar transfer function of analog
input voltages between OV and +Full Scale.
The unipolar voltage ranges are digitally represented at the output
in Straight Binary format. An all zero's output corresponds to OV at
the input, and an all ones output corresponds to + FS range voltage
at the input. The bipolar voltage ranges produce digital outputs in
Offset Binary format. An all zeros output corresponds to an analog
input voltage of -Full Scale Range.
The MN6400 contains an input buffer configured to condition the
analog input signal for optimum acquisition and conversion performance. Additional signal-conditioning circuitry meeting 16 bit
performance levels can be used to drive the analog inputs.
REFERENCE OUTPUT - The MN6400 contains an internal +4.5V
low drift precision reference. This reference voltage appears at
Reference Output (pin 16) to allow for the attachment of a O.I/F
capacitor in parallel with a 1OI'Ftantaium capaCitor. These capaCitors
are required to allow the reference to exhibit a low output impedance
throughoutthe frequency range of device operation. The optimum
value for these capacitors will vary depending on the master clock
frequency being used.
It is recommended not to use the Reference Output pin for any
additional circuitry requirements. If absolutely necessary, the
Reference Output can be buffered and used to fulfill additional
circuitry requirements.
DIGITAL OUTPUTS - The MN6400 supplies converted data and
device status information on outputs capable of driving system bus
connections directly. The device presents both parallel data in an
8-bit MSB/LSB byte format and serial data with serial clock output.
In addition to digital output data, device status information can be
read via the parallel data bit outputs.
The information present on the 8-bit bus is controlled by the state
of Data/Status (pin 11). When high, converted data can be read on
the bus.
When low, the status register can be read on the bus. Converted
data appears on the bus in parallel MSB/LSB ~ format. A read
operation is executed by bringing the 3-State/Read'(pin 12) input
low. The first read operation following a conversion will bring the bus
out of the 3-state condition and present the eight MSBs (MSB on
pin 8 through bit 8 on pin 1). On the second read operation following a conversion, executed by bringing 3-State/Read back high and
then low again, the eight LSBs will be presented (Bit 9 on pin 8
through LSB on pin 1). On subsequent reads before the next conversion is complete, the MSB/LSB byte will toggle. Data is valid after
a delay of 100 nsec from the falling edge of Conversion Status, and
remains valid until the next Conversion Status falling edge.
5-83
I
PARALLEL OUTPUT PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
8
MSB
BYTE
Bit8
Bit 7
Bit6
Bit 5
Bit4
Bit3
Bit2
MSB
LSB
BYTE
LSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit9
STATUS
BIT
Sl
S2
S3
S4
S5
S6
S7
S8
STATUS INFORMATION
Same as Conversion Status (pin 27).
'Reserved for factory use.
LSBlMSB byte indicates which data byte will appear on next read operation.
Same as Acquisition Status (pin 28)
Reserved for factory use.
Tracking - high when device is tracking the input.
Converting - high when the device is converting the input.
Calibrating - high when the device is calibrating.
Device status information can be read on the bus whenever
Data/Status is low. Status bit pin locations and definitions appear
under the section labeled Parallel Output Pin Description.
Converted data is available in Serial format (MSB first) at the Serial
Data Output (pin 25). Serial data is present at the output when it is
determined during conversioF). Serial data is valid and can be
latched with the rising edge of Serial Clock Output (pin 26).
The Conversion Status (pin Z7) and Acquisition Status (pin 28) outputs provide the user with device status information detailed in the
Pin Description Section. Conversion Status will remain low for four
master clock cycles if 3-State/Read is held low. These status outputs along with the serial data and clock output are not 3-stateable.
but have direct bus--_---_4-_Ground
DEVICE CALIBRATION - The MN6405 features two user-controlled
self-calibration modes of operation. Self-calibration insures optirnum
performance at any temperature and at any time throughout the
lifetime of the device. Self-calibration also eliminates the need for additional external circuitry to maintain operation of the device within
specification.
The first mode of calibration is called reset, and its initiation is controlled with Reset (pin 21). A reset calibration must be performed after
the device is powered-up, and can be repeated optionally after the
device reaches its operating temperature. The required initial reset
is initiated by strobing the Reset pin high for a minimum of 100 nsec.
When Reset is brought high, internal logic clears. When Reset retums
low, a single full calibration lasting 1,441,020 master clock cycles
begins (360.255 msec w/4 MHz clock). During reset the Conversion
Status (pin 24) output will be in a high state, and will fall low upon completion of calibration.
The reset mode of calibration can be initiated by either hardware using
a power-up reset circuit or by software in microprocessor control
applications.
The second mode of calibration is called background calibration,
which is activated by either tying Background Calibration (pin 19) to
digital ground or bringing Background Calibration and 3-State/Read
(pin 9) both low. This mode differs from reset calibration in that a fractional portion of the total calibration time is added to the end of each
conversion. After 72,051 conversions, the calibration cycle is complete. The conversion time of the device when background calibration is active is extended by 20 master clock cycles (5l'sec w/4 MHz
clock). Except for the decrease in throughput rate, the background
calibration mode is transparent to the user.
MASTER CLOCK - The M N6405 operates from a master clock that
can be supplied externally or generated internally depending upon
the signal applied to Clock Input (pin 10). A logic low on this pin will
activate the 2 MHz minimum internal clock. Optionally, the user can
supply a TTL or CMOS system clock with a maximum frequency of
4MHz (100kHz minimum) to the Clock Input. All device timing
characteristics scale to the master clock frequency. The internal
oscillator exhibits relatively high jitter compared to crystal oscillators,
which may affect performance in some sampling applications.
INITIATING CONVERSIONS - A falling edge on the Start Convert
(pin 22) digital input will set the device into the hold mode and initiate
a conversion cycle. The Start Convert input must remain low for a
minimum of one master clock cycle plus 50 nsec (300 nsec w/4 MHz
clock). It must return high before the minimum conversion time of 65
clock cycles (16.25!'5ec w/4 MHz clock) to allow sufficient time for acquisition of the next sample.
T/H ACQUISITION - The MN6405 is a sampling AID converter,
therefore it requires a finite amount of time to accurately acquire an
analog input signal before performing a conversion. At the completion of a conversion, signalled by the falling of Conversion Status (pin
24), the device automatically enters the acquisition mode and begins
to track the analog input. A minimum acquisition time of six master
clock cycles plus 2.25!'5ec (3.75I'sec w/4 MHz clock) is reauired to
acquire the input signal. When sufficient time has elapsed after a conversion for the acquisition of the input signal, the Acquisition Status
(pin 23) output will fall low. It returns high on initiation of a new conversion cycle. When driving the MN6405 from a high source impedance, the necessary acquisition time should be extended to allow
for the resultant increase in the input settling time constant.
The MN6405's acquisition circuitry operates from a delayed and divided down internal clock frequency of 1f4 times the master clock. If
sampling is not synchronized to this internal clock, a sample will be
synchronously taken but may not be converted until up to four master
clock cycles later (1i
16 (lSB)
-
5-113
TIMING DIAGRAM -- FULL MICROPROCESSOR CONTROL
READ------------------------------------~
\,-------,1
WR\
/
RIC
CE
tSAC -
+
tOSC+.ir-----------------------------------.
Status --~f--.J
--------------tc--------------~----i_------------t_~-----
+-___________H-=i9_h_lm.:,.p_ed_8_nC_9________________-+_-<1
DB,. DB" ______
Data Valid
tHO-
_too
Read Data Cycle
Initiating Conversion
TIMING - INITIATING CONVERSIONS - It is the combination
of CE="1", CS="O", R/C="1-0" andAo="1" (initiate an 8-bit conversion) or Ao="O" (initiate a 12-bit conversion) that initiates a convert operation. As stated earlier, the actual conversion is initiated
by the falling edge of RIC. CE and CS ml!,st be asserted and stable
concurrently with the falling edge of RiC. Because the MN6774's
control logic latches the Ao signal upon conversion initiation, the ~
line should be stable immediately prior to the falling edge of RIC.
The diagram below illustrates the initiation of a conversion and
subsequent read cycle. When connected to and under micro processor control, conversions are initiated when the MN6774's CE
input il!.high while RIC is brou9!:!!.low by WR. In this application,
CE, RIC are brought high while CS is low and Ao is set to its chosen
state prior to the falling edge of RIC. Once a conversion has begun,
additional convert commands will be ignored until the ongoing
conversion is complete.
TIMING - RETRIEVING DATA - In the example below, data is
enabled when READ is brought low, which in turn, brings CE high.
This in combination with CE low and 12/8= "1" enables all twelve
output bits to be read simultaneously. If the 12/8 line is "0", output
data will be formatted for an 8-bit bus. The 8 MSB's will become valid
when the above conditions are met with Ao="O"; while the 8 LSB's
(4 data bits plus 4 trailing "O's") will become valid whenever Ao= "1".
If 12/8="1", Ao is a "don't care." If an 8-bitconversion is performed
and all 12 output data bits are read, bit 9 (OB3) will be a "1", and
bits 10-12 (OB2-0BO) will be "O's".
Ao may be toggled !}t any time without damage to the converter.
Break-before-make action is guaranteed between the two data bytes,
which assures that the outputs strapped together in 8-bit bus
applications will never be enabled at the same time.
Access time is measured from the point at which CE and RIC are
both high (assuming CS is already low). Data actually becomes valid
300nsec (typ) before the falling edge of Status. In most applications,
the 12/8 input will be hard-wired high or low; although it is fully
TLUCMOS compatible and may be actively driven.
CONVERT MODE
Symbol
Parameter
tosc
tHEC
tssc
tHSC
tSAC
tHAC
tc
Status Delay from RIC
RIC Pulse Width
CE and CS Setup
CE and CS Hold Time
Ao to RIC Setup
Ao Valid During RIC Low
COnversion Time (+25°C)
a-Bit Cycle
12-Bit Cycle
5-114
Min
50
0
50
0
50
lYP
Ma»
Units
60
30
250
nsec
nsec
nsec
nsec
nsec
nsec
20
20
5
7.5
5.3
a
!,sec
!,sec
READ MODE
Min
Symbol
Parameter
too
tHO
tHL
tSSR
tSAR
tHSR
tHAR
Access Time from CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
Ao to CE Setup
CS Valid After CE Low
50
50
0
Ao Valid After CE Low
50
25
Typ
Max
Units
75
35
100
0
25
150
nsec
nsec
nsec
nsec
nsec
nsec
150
nsec
TIMING DIAGRAM -
STAND ALONE OPERATION
R!C---~
-----,1
1"~
'""
DB.! DB·
-------Clm~pe:cd;-ca-cnc:cec---------~
---F~
~-
DB" DB.,
Ie
Ins . . . . . .
/
Strttus
I~h--
-
Data
High
Valid
Impedance
-
Viliid
0<11;1
V;llid
I~-
-L.-:::m
STAND-ALONE OPERATION
The MN6774 can be used in a "stand-alone" mode in systems
having dedicated input ports and not requiring full bus interface
capability. In this mode, CE and 12/8 are tied to logic "1" (they
may be hard-wired to +5V), CS and Ao are tied to logic "0" (they
may be grounded), and the conversion is controlled by RIC. A
conversion is initiated whenever RIC is brought low (assuming a
conversion is not already in progress), and all 12 bits of the threestate output buffers are enabled when Status returns low indicating
conversion complete).
This gives rise to two possible modes of operation; conversions can
be initiated with either positive or negative RIC pulses. The timing
diagram details operation with a negative or positive start pulse. In
either case, the outputs are forced into the high-impedance state
in response to the falling edge of RIC and return to valid logic levels
after the conversion cycle is completed.
o to
I~,se~-
Low RIC Pulse Width
50
STS Delay from RIC
200
nsec
25
nsec
Data Valid After RIC Low
STS Delay After Data Valid
150
375
nsec
High RIC Pulse Width __ ~~ ____ ~_ ns--,,~
tHOR
tHS
tHAH
Max
I
Parameter
tos
Min
Typ
Symbol
tHRL
Units
DIGITAL OUTPUT CODING NOTES:
DIGITAL OUTPUT CODING
ANALOG INPUT VOLTAGE (Volts)
STAND-ALONE MODE TIMING
DIGITAL 0 UTPUT
1.
2.
3.
For unipolar input ranges, output coding is complementary straight binary.
For bipolar input ranges, output coding is complementary offset binary.
For a to -10Vor ±5V input ranges. 1 LSB for 12 bits=2.44mV 1 LSB for 11
bits=4.88mV
For ±10V input range. 1 LSB for 12 bits=4.88mV 1 LSB for 11 b,ts=9.77mV
±SV
±10V
-5.0000
-4.9963
-10.0000
- 9.9927
1111
1111
1111
1111
1111
4.
111~'
- 5.0012
- 4.9988
4.9963
-0.0012
+0.0012
+0.0037
- 0.0024
+ 0.0024
+ 0.0073
1000
0000
0111
0000
0000
1111
OOO~'
OOO~'
*Voltages given are the theoretical values for the transitions indicated. Ideally, with the
converter continuously converting, the output bits indicated as¢ WIll change from "1"
to "0" or vice versa as the input voltage passes through the level indIcated.
- 0.0012
0.0000
+4.9988
+5.0000
+ 9.9976
+10.0000
0000
0000
0000
0000
-10V
-10.0000
- 9.9963
MSB
LSB
111,0"
ooo~·
0000
EXAMPLE: For an MN6774 operating on its ± 10V input range, the transition from digital
output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will Ideally occur at an input
voltage of +9.9976 volts. Subsequently, any input voltage more positive than +9.9976
volts will give a digital output of all "D's." The transition from digital output 1000 0000
0000 to 0111 1111 1111 will ideally occur at an input of +0.0024 volts, and the 1111 1111
1111 to 1111 1111 1110 transition should occur at -9.9927 volts. An input more negative
than -9.9927 volts will give all "1's".
5-115
UNIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the unipolar operating modes
are shown below. If the 0 to -1OV input range is to be used, apply
the analog input to pin 13. If gain adjustment is not used, replace
trim pot R2 with a fixed, 50n±1%, metal-film resistor to meet all
published specifications. If unipolar offset adjustment is not used,
connect pin 12 (Bipolar Offset) directly to pin 9 (Analog Ground).
Unipolar offset error refers to the accuracy of the 0000 0000 0000
to 0000 0000 0001 digital output transition (see Digital Output
Coding). If offset adjustment is not used, the actual transition will
occur within ±2 LSB's of its ideal value (-1hLSB). For the 10Vrange,
1 LSB=2.44mV. To offset adjust, apply an analog input equal to
- 1hLSB and, with the MN6774 continuously converting, adjust the
offset potentiometer "up" until the digital output is all "D's" and then
adjust "down" until the LSB "flickers" between "0" and "1".
MN6774 unipolar operation
with trim adjustment.
R.
HXlk
21218
$tatus28
3CS
High
MN6774 unipolar operation
without trim adjustment.
2121S
3CS
"
"
H.
B'ts
5 RiC
Middle 20
H.
5 RIC
R,
to Refln
5""
8 RelOu!
,;NV-L----1
10 Re!ln
Analog
Inputs
14 +20V Range
BIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the bipolar operating modes are
shown below. If the ± 5V input range is to be used, apply the analog
input to pin 13. If the ± 10V range is used, apply the analog input
to pin 14. If either bipolar offset or bipolar gain adjustments are not
to be used, the trim pots R1 and R2 should be replaced with fixed,
50n ± 1%, metal-film resistors to meet all published specifications.
.5V
,
13+10VRange
+15V
7
14+20VRange
-tSVt'
5-116
D'gGnd 15
MN6774 bipolar operation
212,a:
'A,
5 RIC
6 CE
10 Relln
8 RelOut
12 BlpOff
13 ±5VRange
Status 28
"
Middle 20
SRIi':
Bits
"
H.
23
"
"
.5V ,
Low
Bits
+15V
7
Status 28
High
Bits
"
"
Middle 20
Bits
23
Low
Bits
8 RelOut
"
79
12 BlpOff
13 ±5VAange
+ 15V
7
14 ±10VAange
14 ±10VRange
9 AnaGnd
2121ii
3CS
High
Blls
DlgGnd 15
MICRO NETWORKS
324 Clark St., Worcester. MA 01606
"
"
without trim adjustment.
Bipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 1111 1111 1111 digital output transition after bipolar offset
adjustment has been accomplished. Ideally, this transition should
occur 1112 LSB's above the nominal negative full scale value of the
selected input range. This corresponds to -4.9963Vand -9.9927V
respectively for the ± 5V and ± 10V bipolar input ranges. Gain trimming is accomplished by applying either of these voltages and
adjusting the gain trim pot "down" until the digital outputs are all
"1's" and then adjusting "up" until the LSB "flickers" between "1"
and "0".
_
Bl1s
MN6774 bipolar operation
Bipolar offset error refers to the accuracy ofthe 0111 1111 1111 to 1000
0000 0000 digital output transition (see Digital Output Coding). Ideally, this transition should occur 1hLSB above zero volts, and if bipolar
offset adjustment is not used, the actual transition will occur within
the specified limit of its ideal value. Offset adjusting on the bipolar
device is performed not at the zero crossing point but at the positive
full scale Point. The procedure is to apply an analog input equal to
+FS-1f2LSB(+4.9988Vforthe ±5Vrange, +9.9976Vforthe ±10V
range) and adjustthe bipolar offsettrim pot "up" until the digital output is all "D's". Then adjust "down" until the LSB "flickers" between
"0" and "1".
llJJ
"
"
with trim adjustment.
3CS
Analog
Inputs
Low
8 Ref Out
9 AnaGnd
If a 10.24V (1 LSB=2.5mV) input range is required, the gain trim pot
(R2) should be replaced with a fixed 50n resistor and a 200n trim
pot inserted in series with the analog input to pin 13. Offset trimming proceeds as described above. Gain trimming is now accomplished with the new pots. If one is not gain trimming and wishes
to use fixed-value resistors, the value is 120n. MN6774's input impedance is laser trimmed to a typical accuracy of ± 2%.
High
Bits
M.ddle 20
1231pO!1
12 SIP Of!
13 + IOV Range
Unipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 1111 1111 1111 digital output transition after unipolar offset
adjustment has been accomplished. Ideally, this transition should
occur 1112 LSB's above the nominal minus full scale of the selected
input range. This corresponds to -9.9963V for the -10V unipolar
input range. Gain trimming is accomplished by applying this voltage
and adjusting the gain potentiometer "down" until the digital outputs are all "1 's" and then adjusting "up" until the LSB "flickers"
between "1" and "0".
Status 28
(508) 852-5400
9 AnaGnd
DlgGnd 15
MN6900
l1JJ
_
DESCRIPTION
FEATURES
• SOOMHz Effective Conversion
Rate
• 7.0 Effective Bits at 250M Hz
Input
• son input
•
•
•
•
•
•
•
•
•
a-Bit, 500MHz
SAMPLING AID CONVERTER
MICRO NETWORKS
±1/2 lSB Integral Linearity Error
<10.15 Metastable States
±270mV Input Signal Range
Dual Interleaved Output Data
Paths
Reference Sense Inputs for
Precision Reference Voltage
Setting
+SV, -S.2V Power Supplies
latched ECl Compatible
Outputs
84 Pin Strip-Line Ceramic
Package
7.SW Power Dissipation
The MN6900 is a high speed, 8-bit, fully parallel Analog to
Digital converter with strobed comparators, latched outputs
and internal Track-Hold amplifier. Dual monolithic
converters, driven by the track-hold, operate on opposite
clock edges (time interleaved). Sampling rates of 500MHz
allow accurate digitizing of analog signals from DC to
250MHz .
Innovative design of the internal T/H gives exceptionally
wide input bandwidths of 1.2GHz and aperture jitter of
<2pS. These two features combine to give effective bits
performance of 7.0 at an input signal frequency of 250M Hz.
Special comparator output design and decoding minimizes
metastable states and out-of-sequence codes.
APPLICATIONS
High Energy Physics
Radar/Sonar
Communications
Medical Electronics
ORDERING INFORMATION
Model Number Speed
Resolution Package
MN6900
500MHz 8-bit, T/H
MN6900EVB
500MHz 8-bit. T/H
Ceramic
84-pinQuad
Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
Junction-to-Case (RaJc)
Thermal Resistance
Junction-to-Ambient (RaJA. 200 Lineal FVmin)
with heat sink (RaJA. 400 Lineal FVmin)
~
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
February 1991
Copyright © 1991
Micro Networks
All Rights Reserved
5-117
MN6900 8 Bit 500MHz SAMPLING AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Negative (VEE)
Supply Voltage, Positive (Vce)
Supply Voltage, Difference (VCC-VEE)
Analog Input Voltage (VAIN)
Reference Voltage (VART, VBRT)
Reference Voltage (VARB, VBRB)
-7 to OV
o to +7V
12V
±2V
-0.3 to tl.5V
-1.5 to to.3V
-2.3toOV
VEE to OV
14mA
12mA
-55 to + 150°C
-15 to +125°C
+250°C
Clock Input Voltage (VIH, V,L)
DIV10 Input Voltage (VIH, V,L)
Output Current, lomax (TJ <100°C)
(100 1OO°C). See Figures 1-3 for timing information.
17
19
20
22
23
25
26
28
BO
B1
B2
B3
B4
B5
B6
B7
See AO through A7 above. See Figures 1-3 for timing information.
29
SUB
Circuit Substrate contact. This pin MUST be connected to VEE.
33
31
+DClK
-DClK
Differential clock output (+DClK, -DClK). Used to time and phase
following circuitry. Outputs AO through A7 are valid after the riSing edge
of +DClK. BO through B7 output data are valid after the falling edge of
+DClK (see Figure 1 for output timing information).
35
DIV10
Divide by 10 mode pin. leave open for normal operation. Selects divide
by 10 mode when grounded.
16,48,63
NC
No internal connections to these pins.
52
TP1
Internal connection, leave pin open
53
TP2
Internal connection, leave pin open
12
TP3
Internal connection, leave pin open
11
TP4
Internal connection, leave pin open
65
TP5
Internal connection, leave pin open
66
TP6
Internal connection, leave pin open
I
5-119
Pin #
Symbol
Comments
PHADJ
Phase adjustment for T/H. Normally connected to ground. A phase
adjustment of approx. ±18pS can be made by varying this pin's bias point
to optimize interleaving between sides A and B (see Note 1).
83
81
VCCT
Positive supply connection for internal node. Connect this pin to VCC.
50
VART
"A" side positive reference voltage top input (see Note 2).
51
VARTS
"A" side positive reference voltage top sense (see Note 2).
55
VARB
"A" side negative reference voltage bottom input (see Note 2).
54
VARBS
"A" side negative reference voltage bottom sense (see Note 2).
14
VBRT
"B" side positive reference voltage top input (see Note 2).
13
VBRTS
"B" side positive reference voltage top sense (see Note 2).
9
VBRB
"B" side negative reference voltage bottom input (see Note 2).
10
VBRBS
"B" side negative reference voltage bottom sense (see Note 2).
4,7,15,49
GND
Power Supply Ground. Connect all pins.
57,60,64,67
70,71,74,77
78,79,82,84
18,24,27,30
34,37,40,46
8,21,43,56 VCC
Positive power supply, +5V nominal.
32,69,80
Negative power supply, -5.2V nominal.
VEE
Note 1: Good results are obtained by connecting the PHADJ input to ground. Improved performance
can be achieved by applying a voltage between ±1.25V to this input. The point in time that the "A"
T/H bridge samples relative to the time that the "B" T/H bridge samples can be varied through a
±18pS typo range.
Note 2: VART, VARB, VBRT, and VBRB should be adjusted separately from a well bypassed reference circuit to ensure proper amplitude and offset matching. The sense connection to each of these
terminals allows precision setting of the reference voltage. The reference ladder is similar for both
networks (check electrical section for values). Any noise on these terminals will severely reduce
overall performance.
5-120
TYPICAL CONNECTION DIAGRAM
~'
~1I.1
MN6900
-)
-)
PMlldJI'-"-_ _ _..:
Q.? l'!L le. 24. 27. 3 •• 34
31. 4B. 45. 1:19. '57.&8. &4. &7
1 •• 11. HI. 11.
1~L
79. &2·154
5-121
DEFINITION OF TERMS
EFFECTIVE BITS
Dynamic accuracy of the MN6900 is expressed in
effective bits. Effective bits is a measure of the signal to
error ratio of an analog to digital conversion. Effective
bits is expressed as the number of bits of an ideal, but
lower resolution, AID conversion with the same signal to
error ratio. That is, the quantization error of the ideal
converter equals the total error of the device. In addition
to the ideal quantization error, other sources of error
include all DC and AC non-linearities, clock and aperture
jitter, missing output codes, and noise. Noise on
references and supplies also degrades effective bits
performance.
Effective bits is calculated from a digital record taken
from the AID under test. The input to the AID is a sine
wave filtered with an anti-aliasing filter to remove any
harmonic content. The digital record taken from this
signal is compared against a mathematically generated
sine wave. DC offsets, phase and amplitudes of the
mathematical model are adjusted until a best fit sine
wave is found. After subtracting this sine wave from the
digital record the residual error remains. The rms value
of the error is applied in the following equation to yield
the AID converter's effective bits.
METASTABLE STATES
In a typical AID converter, metastable states may occur
when the analog input voltage, at the time the sample
is taken, falls close to the decision pOint for any of the
255 input comparators. The output code resulting from
this input voltage can have a large error and could
result in a false full or zero scale output. Through
innovative circuit design, Micro Networks has reduced
the magnitude of this type of error in the MN6900 to
less than one LSB, and reduced the probability of this
occurring to less than one error every 1015 clock
cycles. If the MN6900 were operated at 500 MHz, 24
hours per day, this would translate to one metastable
state error every 50 days.
INTEGRAL LINEARITY ERROR
Integral Linearity Error (ILE) is the difference between
the measured input voltage and the calculated input
voltage for that output code. The calculated input
voltage is determined from a straight line least squares
fit for all transitions. ILE is expressed in terms of an
LSB size.
LSB=-------slope of least squares fit line
EB = N _ Log (measured rms error)
2 \
ideal rms error
ILE(LSB) =
'N' is the resolution of the converter. In this case N = B.
It is important to note at which frequency the
measurement was made. The worst case error for any
device will be at the converter's maximum clock rate
with the analog input near the Nyquist rate (1/2 the input
clock rate).
APERTURE WIDTH AND JITTER
Aperture width and aperture jitter are performance
indicators of the AID converter. Each of these
parameters will greatly affect the AID's high frequency
accuracy (see Figure 4). Aperture width is defined as
the time that the track-and-hold circuit takes to
disconnect the hold capacitor from the input circuit (i.e.,
to turn off the sampling bridge and put the TIH in its hold
mode). Aperture jitter is defined as the uncertainty of
the actual start point of the aperture width.
5-122
LSB
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the difference
between the measured LSB step and an ideal LSB
step size between adjacent code transitions. DLE is
expressed in LSBs and is calculated using the
following equation:
(V MEAS- (V MEAS.,)) - LSB
DLE(LSB) = - - - - - - - LSB
VMEAS.' is the measured value of the previous code.
A DLE error specification of <1 LSB guarantees that
there are no missing codes and the transfer function is
monotonic.
APPLICATION NOTES
POWER SUPPLIES/GROUNDS
A +5V supply as well as a -5.2 V supply is needed for
proper operation. Bypassing of the VEE and VCC
supply pins to GND should be done with a good quality
0.1 >IF and 0.001 >IF ceramic capacitor located as close
to the package as possible.
ClK AND DClK.
All clock signals, input and output, are differential.
The input clocks, +ClK and -ClK, are the primary
timing signals for the MN6900, and are fed to the
internal circuitry from one of two input groups, pins
(2,3) or pins (62,61), through a 50 n transmission line.
One set of +ClK, -ClK inputs should be driven and the
other pair terminated by 50 U to -2 V. Either set of
inputs can be used as the driven inputs (input lines are
balanced) for ease of circuit connection. A minimum
pulse width tpwi is required for the input clocks, +ClK,
-ClK, to ensure proper operation (see timing Figures 1
through 3).
To ensure optimum performance and repeatable
results, a low phase noise clock source should be used
for +ClK and -ClK. Phase noise from the input clock
source will reduce the converter's effective bits
performance and cause inconsistent results. The clock
supplied to the MN6900 is internally divided by two,
reshaped, and buffered. This divided clock becomes
the internal signal used as strobes for the converters.
+DClK, -DClK are output clock signals derived from
the input clocks and are used for external timing of the
data outputs AData and BData (AData is valid on the
rising edge of +DClK, and BData is valid on the falling
edge). They are fixed at one half the rate of the input
clocks in divide by '1' mode. The MN6900 is specified
to work at a maximum input clock frequency of 500
MHz (see Table 1).
DATAFLOW
The MN6900 contains an internal Track and Hold (T/H)
amplifier that samples the analog input voltage for the
AID to convert. The T/H is split into two sections which
operate on opposite clock edges. The input clock,
+ClK, is conditioned by the T/H and fed to the AID
section. The output clock +DClK, used for output data
timing, will be divided by 2 or 10 from the input clock
+ClK (see Table 1). The differential inputs, +AIN and
-AIN, are tracked continuously between data samples.
When a negative internal strobe edge is sensed, the
T/H goes into the hold mode (see Figure 4). When the
internal strobe is in the low state, the just acquired
sample is presented to the AID converter's input
comparators. Internal processing of the sampled data
takes an additional 15 clock cycles before it is available
at the outputs AData and BData. For timing see
Figures 1 through 3.
INPUT CLOCK PHASING
The clock edge that AData and BData operate from is
undetermined at power up. If the converter is desired
to work off a specific input clock edge, the following
procedure using TRKI and -TRKI must be
implemented.
+
+TRKI and -TRKI are differential ECl inputs that are
used in addition to the normal input clock (+ClK) to set
phasing of the data. A signal!!t one half of the input
clock rate with the proper set up and hold time (setup
and hold typically 300 ps) is applied to these inputs. By
applying a logic "1" to +TRKI ("0" to -TRK1) before the
negative transition of +ClK, side AData is chosen. If
BData is desired at the negative edge of +ClK, then a
logic "0" must be applied ("1" to -TRK1) instead.
In this manner, several MN6900 converters can be
interleaved to obtain faster effective sampling rates.
TRACK-AND-HOlD
As with all AID converters, if the input waveform is
changing rapidly at the time of conversion the
Effective Bits (EB) and Signal to Error Ratio (SER) will
decrease. To avoid this problem a Track-and-Hold
(T/H) circuit was added internally to the MN6900.
The T/H increases attainable effective bits performance, and allows capture of analog data more
accurately at high conversion rates.
The T/H provides two additional circuit functions for
the MN6900. First, its nominal voltage gain of four (4)
reduces the input driving signal to 270 mV (±135 mV
differentially, normal conversion range assuming a
±1.02 V reference). Secondly, the T/H provides a
differential 50 n low VSWR input allowing easy
interfacing to this converter. Although the normal
operating range is 270 mY, it can be operated with up
to ±500 mV on each input with respect to ground.
This extended input level would include the analog
Signal and any DC common mode voltage.
To obtain full scale digital output with differential input
drive, a nominal 270 mV must be applied between
+AIN and -AIN. That is, +AIN = +135 mV and -AIN=
-135 mV (when no DC offset is applied). Mid-scale
digital output code occurs when there is no voltage
difference across the analog inputs. Zero scale digital
output code, with differential drive, occurs when +AIN
= -135 mV and -AIN = +135 mY. The output of the
converter stays at all ones (full scale) or all zeros
(zero scale) when over or under ranged, respectively.
Table 2 shows these relationships in a tabular form.
Single ended operation can be handled simply by
applying a DC offset to, or by leaving open, one of the
analog inputs (both +AIN and -AIN are terminated
internally with 50 U to analog ground). Then drive
one input with a ±270 mV + offset to obtain either full
or zero scale digital output. If a DC common mode
offset is to be applied, the total voltage swing allowed
is ±500 mV (analog signal plus offset with respect
to ground).
INPUT REFERENCE lADDER
The AID converter's reference ladder is a Kelvin
sensed resistor string used to set the lSB size and
dynamic operating range of the converter. Normally,
the top and bottom of this string are driven with an
op-amp circuit.
The buffer amplifier circuit used to drive the top and
bottom inputs will need to supply approximately
21 mA due to a resistor string impedance of 100 n
minimum. A reference voltage of ±1.02 V is normally
applied to inputs VAAl' VB AT and VA AB , VB Ae . These
references control the comparators' input windows
and can be adjusted up to ±1.2 V to accommodate
extended input requirements (accuracy specifications
are guaranteed with references of ±1.02 V). The
reference inputs VA ATS ' VAA~S' VB ATs ' and VBA~s allow
Kelvin sensing of the appliea voltages for precision
setting of the resistor chain.
Any noise on the reference pins will directly affect the
code uncertainty and degrade the effective bits
performance of the AID.
5-123
TABLE 1 - OUTPUT MODE CONTROL
DCLK*
DIV10
Description
(Divide by 1 mode)
OPEN
250 MHz
GND
50 MHz
AData and BData valid on opposite DClK edges
(AData on rise, BData on fall).
(Divide by 10 mode)
Input clocks (+ClK, -ClK)
AData and BData valid on opposite DClK edges
(AData on rise, BData on fall).
Data sampled at input ClK rate but 4 out of
every 5 samples discarded.
=500 MHz for all above combinations.
In all modes the output clock +OClK will be a 50% duty cycle signal.
TABLE 2 -INPUT VOLTAGE RANGE
Input
Differential
Single Ended
**
+AIN**
-AIN**
Output Code
MSBtoLSB
+135mV
0
-135mV
+270 mV
0
-270 mV
-135mV
0
+135 mV
0
0
0
11111111
10000000
00000000
11111111
10000000
00000000
full scale
mid scale
zero scale
full scale
mid scale
zero scale
An offset V10' as specified in the DC electrical parameters, will be present at the input. Compensate for this offset by adjusting the reference voltage.
Offsets may be different between side A and side B.
APPLICATION NOTES
DIV10
When DIV10 is grounded it enables the divide by 10 circuitry. The output data and clock rates are reduced by a
factor of 10 with respect to the input clock. The output clock duty cycle remains at 50% and the clock to output data
phasing remains the same. In this mode four out of every five sampled input values are discarded. When left open
this input will be pulled low by internal circuitry and the converter will function in its fastest mode. This pin is left
open for normal operation.
PHASE ADJUST
PH ADJ is normally connected to ground, but can be adjusted from a variable supply of ±1.25 V. This control affects
the point in time that one half of the converter samples the input signal relative to the other half. An adjustment
range of ±18 ps typically, is made available for optimization of converter performance.
If PH ADJ is not grounded, care should be taken to bypass it properly since any noise on this pin will reduce system
performance.
INTERLEAVING
PH ADJ is used only to adjust timing between the clock and data as stated above. Reference inputs must be adjusted
to compensate for amplitude and offset differences.
.
Figure 1. Output Timing: DIV10 = OPEN
+CLK
-CLK
+DCLK
-DCLI(
~----
----,~ -t~:h--~~- t-P~l- jL_ -------J-- --- ---1_ -- --- __ J~
~r------------------'L
!eo
__________________ J\--------- --------tpdl
AData
BOnta
5-124
x
x
Figure 2. Output Timing: Clock to Data, Fast Mode DIV10
=OPEN
+CLK
+DCLK
AData
BData
Data arbitrary on start up for side A or B unless TRK1 is used.
Figure 3. Output Timing: Divide by 10 Mode (DIV10 = GND)
+CLK
+DCLK
--------------~;~~:----~\/
;
AData
BData
N
------------------------~I
~;------------·----------------------------r-------
----------------------------11
I
X
N +5
Data arbitrary on start up for side A or B unless TRK1 is used.
Figure 4. T/H Aperture Timing
ClK
-ClK
=x'---___x=
low
Analog
Inpul
Sampled
Dolo
,, ,
(T /H)
Rperlur~
Dela~
Rperture WIdth
Rperture Jitter
lad
law
lOJ
5-125
Figure 5.
Figure 6.
Integral Linearity Error (LSB's) vs Output Code
Differential Linearity Error (LSB's) vs Output Code
D !r~f RENT JAt
L1N[ARITY
ERROR
[NTECiR~c
(LSS",)
L INE~RITY
rRRDR
(LS8~
-0.25
)
tJ.7S
'cR
OUTPUT (UDE
'" CODE
OU~PtJT
Figure 7. FFT.
Figure 8. FFT.
=
=
=
FelK 500 MHz, FAIN 251.4462 MHz, SER -44.5 dB,
Noise Floor = -67.3 dB, Spurious = -58.2 dB
=
=
=
FelK 250 MHz, FAIN 10.4462 MHz, SER -47.2 dB,
Noise Floor = -70.5 dB, Spurious = -61.8 dB
-
0
0
c-
0
(dB)
(dB)
--
I
r .r'I IAlil lA
la,
I, 'I I 'V ''if 1"11'
JI.
'J!
,n.h
,
, .,'
"I,
11"111
,I
AI
o
,I
"UI' If
~
. HI fAA.
IIIIIW 'ft" IN'
Figure 9. Effective Bits vs Frequency (FA"')
FelK = 500 MHz, V,N = 95% FS
7,7
7.15
.A~
d~
1I'IK IN 1"\" rw~
Figure 10. Effective Bits vs Frequency (FeLK )
FAIN = 10.4462 MHz, V'N = 95% FS
7.83
~5
1.11.,
V "
(MH»
(MH»
.,...
-- - I-- f---
7.14
7.14
7.7
7.7
7.19
7.6
7,'
7.6
TI.o\lMlIEIIIT)=25"C
EFFECTIVE:. 5
T(AMIIIENTI,,2S*C
EFFECTIVE 4
4
Bl7S
(LSB's)
50
100
lSO
'00
ANALOG INPUT FREQUENCY (MHz)
5-126
25.
30.
3
..
,I
I
,SO
I
I
300
3SO
...
I ,----,-..,....-,
400
CLOCK FREQUENCY (MHz)
450
50. '50
GNO
"3
TPS
P'
GNO
TPG
GNO
PS
HFGNO
"G
GNO
VEE
GNO
P7
GNO
Dlv1B
MN6900
+AIN
·I=IIN
(TOP
GNO
UIEW)
-AIN
GNO
+DCLK
VEE
-OCLK
-!=lIN
GND
GND
SUB
GNO
GND
B7
,
GND
VEE
BG
veeT
BS
GND
GND
PHADJ
B'
B3
GND
I
PIN
INDICATOR f"UlG
OR NOTCH
COPUI NRR
RCROS 5 ALL LERO 5
5-127
~ MICRO NETVVORKS
~
5-128
MICRO NETWORKS
324 Clark 51., Worcester, MA 01606 (508) 852-5400
MN6901
l1JJ
_
a-Bit, 250M Hz
SAMPLING AID CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• 250M Hz Effective Conversion
Rate
• 6.8 Effective Bits at 125MHz
Input
• 50n input
• <±1/2 lSB Integral Linearity
Error
• <10-15 Metastable States
• Dual Output Data Paths
• On Chip 8 to 16 Demux,
Selectable
• ±270mV Input Signal Range
• Reference Sense Inputs for
Precision Reference Voltage
Setting
• +5V, -5.2V Power Supplies
• latched ECl Compatible
Outputs
• 84 Pin Strip-Line Ceramic
Package
• 5W Power Dissipation
The MN6901 is a high speed, 8-bit, fully parallel Analog to
Digital converter with strobed comparators, latched outputs
and internal Track-Hold amplifier. A sampling rate of
250MHz allows accurate digitizing of analog signals from
DC to 125MHz.
Innovative design of the internal T/H achieves input signal
bandwidths of 1.2GHz and aperture jitter of <2pS. These
two features combine to give effective bits performance of
6.8 at 125MHz. In addition, special comparator output
decoding minimizes false codes.
I
Dual output data paths provide several data output modes
for easy interfacing. These modes include two identical fast
outputs, or an 8:16 demultiplexer to reduce output data
rates to one-half the clock rate.
APPLICATIONS
High Energy PhYSics
Radar/Sonar
High Speed Image Processing
Communications
Medical Electronics
Instrumentation
ORDERING INFORMATION
Model No.
Speed
Resolution
MN6901
250M Hz 8-bit. T/H
MN6901 EVB
250MHz 8-bit. T/H
Package
Ceramic
84-pinQuad
Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
Junction-to-Case (RaJc)
Thermal Resistance
Junction-to-Ambient (RaJA. 200 Lineal It/min)
~
MICRO NETWORKS
February 1991
Copyright © 1991
Micro Networks
All Rights Reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
5-129
MN6901 8 Bit 250MHz SAMPLING AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
-7toOV
Supply Voltage, Negative (VEE)
Supply Voltage, Positive (VCCl
Supply Voltage, Difference (Vec-VEE)
Analog Input Voltage (VAIN)
Reference Voltage (V ART)
Reference Voltage (V ARB)
o to +7V
12V
±2V
-0.3 to + 1.5V
-1.5 to +0.3V
-2.3 to OV
-33m A
-43mA
-55 to + 150°C
-15 to +125°C
+250°C
Digital Input Voltage (VIH, V,L)
Data Output Current (lOMAX)
DCLK Output Current (lOMAX)
Storage Temperature (TsTG)
Operating Temperature, Junction (ToPR)
Lead Temperature (solder <1 Osec) (Ts)
VEE~-5.2V, Vcc~+5V, RL~50n to -2V, VRTo 1.02V. VRB~-1.02V, TA~25°C unless otherwise noted.
t
ANALQ§lNPUTS_ _ _ _ _ _ _ _ _ _ _ _ _-~~~~~~~IN
MAX
UNITS
mV
mV
-17
mV
+32
51
n
49
1.2
GHz
__
=-_+~ _ _ _ .j... __d_B
Common Mo
,ui
I"V'
12.5
•• IA~.
.1.
'rr 14 "
18.1&
n
J, ,& nMrY .nft
11 'I' 'f! 'I' ~.
31.2531.5
43.75
50
Figure 11. Effective Bits vs Frequency (FeLK)
= 250 MHz, V,N = 95% FS
FAIN = 10.4 MHz, V ,N = 95% FS
T, ...... ,,";:5C
T".. ,,",,-2SC
[fF£(lluf
BITS
>S,
RNI'lLOG INPUT
'"
'"
FREQUENCY (M1z)
CLOCK fREQUENCY (MHz)
Figure 12. Effective Bits vs Frequency (FAIN)
Te
Figure 13. Effective Bits vs Frequency (FAIN)
=80°C, FeLK =250 MHz, V,N =95% FS
Te
=-1Soc, FeLK =250 MHz, V'N =95% FS
"
~. , i v.
•Ii",
: !
T,,"U"
AI'H'ILOG INPUT
5-138
UFECTlU(
BITS
sec.
,REaUENC'!' (MHz)
'"
T".S(,"
ANALOG
6.'
1St .
INPUl
H!((lU[NCV (MHzl
'"
'"
Figure 14. ClK, DClK, DClK, FelK = 250 MHz
Divide by one mode.,
Vertical
=5OOmVldiv, Horizontal =1ns/div
Figure 15. DClK, t, = 710 ps
Vertical
=2oomVldlv, Horizontal =500 ps/div
Figure 16. ClK, DClK, AData, F elK =250 MHz
Divide by one mode
Vertical = 500 mVidiv, Horizontal = 2ns/div
5-139
[1:!J MICRO NETWORKS
~
5-140
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
Analog-to-Digital Converters
Since its inception, Micro Networks has continually contributed to advancing the leading edge of DIP-packaged, high-speed, high-resolution
ND conversion technology. As detailed in the History section at the
beginning of this catalog, we lay claim to a long list of industry firsts. Recent years have seen the introduction of a 16-bit, 17pSec extendedtemperature range ND (MN5295/5296), a 12-bit, 400nsec ND converter
(MN5249), and many 12 and 16-bit sampling ND converters (MN6249,
MN6400, MN6405).
The four products listed below are the first in a series of high-speed 6
and 8-bit CMOS monolithic Flash ND converters. The MN5902 and
MN5908 are 8-bit, 20M Hz and 15MHz devices. Two 6-bit devices, the
MN5906 and MN5909, convert at an impressive 50MHz and 100M Hz
and consume less than 200mW of power.
MN5902
MN5908
MN5906
MN5909
8-Bit
6-Bit,50MHz
6-Bit, 100MHz
CMOS Flash AID
Converters
CMOS Flash AID
Converter
CMOS Flash AID
Converter
FEATURES
FEATURES
• 20MHz (MNS902)
1SMHz (MNS908)
• 6-Bit Resolution
Plus Overflow Bit
• 6-Bit Resolution
Plus Overflow Bit
•
•
•
•
• SOMHz Typical
Conversion Rate
• 100MHz Typical
Conversion Rate
• Single +SV Operation
• Low Input Capacitance
• Low Power (190mW, typ.)
•
•
•
•
FEATURES
Single +SV Supply Operation
Low Harmonic Distortion
3-State Outputs
Easy Cascading to 9 Bits
• Low 350mW Power
Consumption
• Small 24-Pin DIP
• -SsoC to +12SoC
Operating Temperature Range
• Optional Environmental
Stress Screening
6-2
Micro Networks is a recognized leading supplier of high-speed, highresolution ND converters for military/aerospace applications, and we
currently supply products to more than 50 missile, aircraft and satellite
programs. Most of our ND converters are available specified for extended temperature range operation, in hermetically sealed packages. Additionally, these devices are available with optional Environmental Stress
Screening (H/S models) or compliant with MIL-H-38534 requirements.
Our complete line of high-performance ND converters is complimented
by a complete line of compatible, high-performance track-hold (T/H)
amplifiers (see Section 8), and we also offer a growing line of sampling
ND converters (see Section 5).
• Small l8-Pin Ceramic
or Plastic DIP
• 3-State Outputs
• Optional Environmental
Stress Screening
Single +5V Operation
Low Input Capacitance
Low Power (200mW, Typical)
Externally-Strobed,
Auto-Zeroed Comparators
• Small 20-Pin Ceramic
or Plastic DIP
• 3-State Outputs
• Optional Environmental
Stress Screening
Analog-to-Digital Converters
Resolution
16-Bits
12·Bits
8-Bits
Model
Number
Maximum
Conversion
Time
(J--..l-----'----Ground Pin 25 0
1
I
OPERATION WITH EXTERNAL CLOCK-The external clock
is connected and gated as shown. The Convert Command
input must be synchronized with the external clock signal
and the Clock Inhibit input tied low, for proper operation.
ADC 80
+15V
IT IT
JlL-.._ _ _ __
O.D1~F
Ground
O.D1~F
-
-
15V
I
.JlJl.Jl
DIGITAL
COMMON
END OF CONVERSION-During conversion, the decision as
to the proper state of any bit (bit "n") is made on the rising
edge of the clock pulse "h + 1". Therefore, a complete conversion requires 13 clock pulses with the Status (E.O.C.) Olltput dropping from logic "1" to logic "0" shortly after the failing edge of the 13th clock pulse. Parallel data is valid and
ready to be read when Status falls. This allows direct use of
Status for latching parallel data.
CLOCK OUTPUT-The internal 556kHz clock is brought out
(pin 23) and will drive up to two standard TIL loads. The internal clock is stopped at the end of each conversion and
remains low until a new conversion is initiated.
SERIAL DATA OUTPUT-Serial data is available (pin 26) in
non-return-to-zero formal. Timing for the serial output is
shown on the Timing Diagram.
REFERENCE OUTPUT-The internal 6.3V reference (pin 24)
will drive loads up to 30k ohms, however it is recommended
that this output be buffered before use.
6-8
CONTINUOUS CONVERSION WITH EXTERNAL CLOCKFor continuous conversion of the input signal, the Convert
Command and Clock Inhibit inputs are tied low and an ex·
ternal clock applied to the Clock Inpul. The converter will then
continuously convert, reset and initiate new conversions. The
converter will be reset on the 13th clock pulse, and the subsequent conversion will be initiated by the 14th clock pulse. The
output data will be valid when E.O.C. goes low and will remain
valid until E.O.C. returns high.
ADC 80
CONVERT
COMMAND
E.O.C.
DIGITAL
CDMMON
CONTINUOUS CONVERSION WITH INTERNAL CLOCKFor continuous conversion of the input signal, the Clock Inhibit and External Clock pins are tied high. The conversion is
initiated by the 14th clock pulse and the internal clock runs
continuously. The oscillator formed by gates 1 and 2 insures
that the conversion will start when logic power is turned on.
ADCBO
470pF
~..:-"~
20
O.OO47#lF
OPTIONAL EXTERNAL OFFSET AND GAIN ADJUSTMENTS
-Initial offset and gain errors may be trimmed to zero using
external potentiometers as shown in the following diagrams.
Adjustments should be made following warm-up, and to
avoid interaction, offset should be adjusted before gain.
Fixed resistors can be ±20% carbon composition or better.
Multiturn potentiometers with TCR's of 100 ppm/oC or less
are recommended to minimizedrift with temperature. If these
adjustments are not used, pin 11 should be connected as described in the Input Voltage Connections section, and pin 16
should be left open.
OFFSET ADJUSTMENT-Connect the offset potentiometer
as shown, and apply the input voltage at which the 1111 1111
1111 to 111111111110 transition is idealy supposed to occur
(see Output Coding Table). While continuously converting,
adjust the offset potentiometer until all the output bits are
"1" and the LSB "flickers" on and off.
+ 15V
SHORT CYCLE FEATURE-The ADC80 may be operated at
faster speeds if resolution of less than 12 bits is required.
Connections for Short Cycle (pin 21) are shown in the following table:
Pin 11
'8M!!
~
+ 15V
10k!!
to
100kH
22kU
-15V
RESOLUTION (BITS)
Connect Pin 21 to
Maximum Conversion Time
Internal Clock v,sec) (Note 1)
Maximum nonlinearity
at +25°C (% of F8R)
12
10
8
Pin 9
Pin 28
Pin 30
25
22
18
±0.012
(Note 2)
±0.048
±0.20
GAIN ADJUSTMENT-Connect the gain potentiometer as
shown, and apply the input voltage at which the 0000 0000
0000 to 0000 0000 0001 transition is ideally supposed to occur.
While continuously converting, adjust the gain potentiometer until all the output bits are "0" and the LSB "flickers" on
and off.
NOTES: (1) Max. conversion time to maintain ± V2LSB linearity error.
(2) ADCBO·12 model only.
+ 15V
10MU
CONNECT
INPUT SIGNAL
TO PIN
CONNECT
PIN 12
TO PIN
CONNECT
PIN 14
TO PIN
±10V
14
11
Input 8ig.
±5V
13
11
Open
±2.5V
11
Pin 11
Oto +5V
13
13
15
Pin 11
Oto +10V
13
15
Open
INPUT
SIGNAL
+ 15V
10kll
Pin 16
INPUT VOLTAGE CONNECTIONS-The analog input voltage
ranges of the ADC80 are user selectable by external pin connections as shown in the adjacent table.
- 15V
to
100k11
Jom"F
Pin
16o-r'yyo,-r--'\"""'-~
10k!2
to
100k!!
- 15V
6-9
I
DIGITAL OUTPUT CODING
Analog Input Voltage Range
Digital Outputs
010 +5V
010 + 10V
±2.5V
±5V
±10V
MSB
+5.0000
+4.9982
+ 10.0000
+9.9963
+2.5000
+2.4982
+5.0000
+4.9963
+ 10.0000
+9.9927
000000000000
00000000 OOog-
LSB
+2.5006
+2.4994
+2.4982
+ 5.0012
+4.9988
+ 4.9963
+0.0006
-0.0006
- 0.0018
+0.0012
-0.0012
-0.0037
+0.0024
-0.0024
-0.0073
0111111111111~~ftft~
1000 0000 OOog-
+0.0006
0.0000
+ 0.0012
0.0000
- 2.4994
-2.5000
-4.9988
-5.0000
-9.9976
-10.0000
111111111111
11111111111~-
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is complementary straight binary.
2. For bipolar input ranges, output codi~ complementary offset binary or
complementary two's complement if MSB output is used.
3. ForOto +5Vor ±2.5V input ranges, lLSBforI2bits~I.22mV.1LSBforl0
bits ~ 4.BBmV.
4. ForO to + 10V or ±5V input ranges, lLSB for 12 bits ~ 2.44mV. lLSB for 10
bits ~ 9.77mV.
5. ForO to +20Vor ±10V input ranges, lLSBforI2bits~4.88mV.1LSBforl0
bits ~ 19.53mV.
EXAMPLE: For an ADCBO-12 operating on its ± 10V input range, the transition
from digital output 111111111111 tolllllllllll0(orvlceversa) will ideally
occur at an input voltage of -9.9976 Volts. Subsequently, any input voltage
more negative than -9.9976 Volts will give a digital output of all "1 's". The tran·
sition from digital outputOll111111111 to 10000000 0000 will ideallyoccurat
an input of -0.024 Volts, and the 0000 0000 0000 to 0000 0000 0001 transition
should occur at + 9.9927 Volts. An input more positive than + 9.9927 Volts will
give all "a's".
·Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as 0' will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
TIMING DIAGRAM
CONVERT
COMMAN~~_____________________________________________________
INTERNAL
CLOCK
WllA
MSB
BIT 2
~
BIT 3
W/iJ
BIT 4
W/iJ
BIT 5
l!!iL1
BIT 6
1f!.ljj
BIT 7
Jl!ZLl
BIT 8
WZI
BIT 9
BIT 10
Jl!ZLl
Wll
BIT 11
WfZ,j
lSB
WIIlJ
E.O.C.
_.J
LJ
LJ
LJ
LJ
~__~__--"8~~1~1__~1~2________________
~~~:~T WZZ/ZZZZJMSB~6
DYNAMIC CHARACTERISTICS
Conversion Time: 12·Bits
1(J..Bils
Clock Delay from Convert Command
Clock Period
Clock Pulse Width (High)
Status Delay from Convert Command
All Bits Reset Delay from Convert Command
Data Valid Time from Clock Pulse High
6-10
MIN.
TYP.
MAX.
UNITS
22
19
153
1.81
0.87
186
141
-15
25
22
"sec
"sec
nsec
"sec
"sec
nsec
nsec
nsec
UJJ
_
ADC84
ADC85
HIGH-SPEED,12-Bit
A/D CONVERTERS
MICRO NETWORKS
FEATURES
• Fast Conversion Times:
8Jtsec max. for 12 Bits
SJtsec max. for 10 Bits
• ± V2 LSB Linearity and No
Missing Codes Guaranteed
Over Temperature
• Complete:
Internal Reference
Internal Clock
User·Optionallnput Buffer
• Versatile:
5 Input Voltage Ranges
Serial and Parallel Outputs
4 Output Coding Formats
Short· Cycle Capability
Variable Clock
• Small 32·Pin DIP
32 PIN SIDE·BRAZED DIP
QJ!!P.J.9~111
DESCRIPTION
ADC84 and ADC85 are high-speed, 12-bit, successive approximation analog-to-digital converters. Each is complete with
internal reference, clock and input buffer amplifier and is
extremely versatile offering 5 user·selectable input ranges,
short cycling capability, parallel and serial outputs, a status
output for easy interfacing in microprocessor-based
applications, and an internal clock with the option of using
an external clock.
Models are available in both 10 and 12 bit linearities for either
O°C to + 70°C or -25°C to +85°C operation. No clock
adjusting is necessary to achieve the guaranteed 8Jtsec maximum conversion time (for 12 bits), and "no missing codes" is
guaranteed over temperature.
The Micro Networks ADC84 and ADC85 series of 12-bit A/D
converters are direct pin·for-pin replacements for industrystandard ADC84 and ADC85 converters and offer faster conversion times, lower power consumption and guaranteed "no
missing codes".
ADC84 and ADC85 series devices are excellent choices for
high-speed applications in commercial/industrial OEM
designs. They are particularly well suited for high-speed,
multichannel, simultaneous sampling or sequential, data
acquisition systems.
For example, ADC84 or ADC85 can be combined with an
MN376 high-speed T/H amplifier and an industry-standard 508
type CMOS multiplexer to create a multichannel DAS with a
scan rate greater than 100,000 channels/sec. In DSP-type applications, ADC84 or ADC85 can be configured with MN376 to
create a 100kHz-pius digitizer with a 50kHz input bandwidth
that will typically produce signal-to-noise ratios greater than
70dB with harmonics more than 80dB down.
, 1-1
'- -_- -'" T.tT
~,
o~m~
\
0.100 (2.54)
O.900(22.86)j
o
[
920 (2337)
.
0.151 (3.84)
O.lB2(4.62}
~
;I---lI ~~~::~:
O.190(4.83}
O.2tQ{S.33}
IF==~=O'20====j~ f
I
0.012(0.31)
1---
0.900 (.22.86)
----..J
Dimensions in Inches
(millimeters)
Model
Number
Linearity
Error (%FSR)
Specification
Temp. Range
Gain
Drift (ppm/GC)
ADC84·10
ADC84·12
±0.048
±0.012
O'Cto +70'C
O'C to + 70'C
±30
±30
ADC85C·10
ADC85C·12
±0.048
±0.012
O'Cto + 70'C
O'Cto +70'C
±40
±25
ADC85·10
ADC85·12
±0.048
±0.012
-25'C to +85'C
-25'C to +85'C
±20
±15
~
_
MICRO NETWORKS
April 1988
324 Clark St .. Worcester. MA 01606 (508) 852-5400
6-11
ADC84 ADC85 HIGH·SPEED 12·Bit AID CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
ADC84-10, ADC84-12
ADC85C-10, ADC85C-12
ADC85-10, ADC85-12
Storage Temperature Range
Positive Supply (+ Vee, Pin 28)
Negative Supply (- Vee, Pin 31)
Logic Supply (+ Vdd, Pin 16)
Digital Inputs (Pins 14, 21)
Analog Inputs (Pins 24, 25)
Buffer Input (Pin 30)
PART NUMBER - - - - - - - - - - A D C 8 X X XX
Select ADC84, ADC85C or ADC85
-I
for desired performance and
specified temperature range.
Select -10 or -12 for desired
resolution and linearity error. - - - - - - - - - - - '
I
- 55·C to +125·C
O·Cto +70·C
O·Cto +70·C
-25·C to +85·C
- 65·C to + 150·C
- 0.5 to + 18 Volts
+ 0.5 to -18 Volts
- 0.5 to + 7 Volts
- 0.5 to + 5.5 Volts
±25 Volts
± 15 Volts
SPECIFICATIONS ALL UNITS (Typical atTA = + 2SoC, ± Vcc = ± 1SV, + Vdd = + SV unless otherwise indicated)(Note 13)
ADC84
MODEL
-10
ADC8SC
-12
-10
ADC8S
-12
-10
-12
UNITS
ANALOG INPUTS
Input Voltage Ranges: Unipolar
Bipolar
··
···
Oto +5,Oto +10
±2.5, ±5, ±10
Input Impedance (Direct Input) (Note 1):
oto + 5V, ± 2.5V
Oto +10V, ±5V
±10V
2.5
5
10
Buffer Amplifier: Impedance (min)
Bias Current (Note 1)
Settling Time to ±0.01 % for 20V Step (Notes 1,2)
100
±50
2
·
··
·
···
··
·
··
DIGITAL INPUTS (Start, Short Cycle)
Logic Levels: Logic "1" (min)
Logic "0" (max)
+2.0
+0.8
Logic Currents: Logic "1" (VIH = +2.4V)
Logic "0" (VIL = + 0.4V)
+40
-1.6
··
·
Volts
Volts
kfl
kfl
kfl
Mfl
nA
j----------1 (24)
(13)
MN346
ADC84/85Cf85
~-----
Throughput - - - - - I
Start Convert
USING A TRACK/HOLD AMPLIFIER WITH AN ADC84I85C185
-When using a track·hold (T/H) amplifier with an
ADC84/85C/85, the 17H can be driven directly(or inverted) from
the AID's Start Convert signal. When the Start is high prior to
the beginning of a conversion, the T/H can be in the tracking
or signal acquisition mode. The falling edgeofthe start signal
initiates the conversion and simultaneously commands the
Status (E.O.C.)
Conversion Time
Throughput Rate
T/H Acquisition Time
AID Conversion Time
100kHz
2"sec
8"sec
6·15
I:
..
OPTIONAL EXTERNAL OFFSET AND GAIN ADJUSTMENTS
-Initial offset and gain errors may be trimmed to zero using
external potentiometers as shown in the following diagrams.
Adjustments should be made following warm-up, and to
avoid interaction, offset should be adjusted before gain.
Fixed resistors can be ±20% carbon composition or better.
Multiturn potentiometers with TCR's of 100ppm/oC or less
are recommended to minimize drift with temperature.lfthese
adjustments are not used, pin 22 should be connected as described in the Input Range Selection section and a 0.011'F
capacitor should be connected from pin 27 to pin 26.
0000 0001 to 0000 0000 0000 transition is ideally supposed to
occur (see Digital Output Coding). While continuously converting, adjust the gain potentiometer until all the output bits
are "0" and the LSB "flickers" on and off. A 0.011'F capacitor
should be connected from Gain Adjust (pin 27) to Analog
Ground (pin 26).
+15V
Pin
f
lOk !!
1.8MII
22~10
lOOkll
-15V
or
OFFSET ADJUSTMENTS-Connect the offset potentiometer as shown and apply the input voltage at which the 1111
1111 1110 to 1111 1111 1111 transition is ideally supposed to
occur (see Digital Output Coding). While continuously converting, adjust the offset potentiometer until all the output
bits are "1" and the LSB "flickers" on and off.
Pin
180kll
i
or
+15V
180kO
10kO
~~'v-1""""'/\'-~
~10
22
1
22kl!
-=-
GAIN ADJUSTMENT-Connect the gain potentiometer as
shown below and apply the input voltage at which the 0000
+15V
100kO
lOkI!
10
100kll
-15V
Offset Adjust
Gain Adjust
INPUT RANGE SELECTION
Analog Input Voltage Range
Pin Connections
oto
o to
+5V
+10V
±2.5V
±5V
±10V
FOR NORMAL INPUT
Input Impedance (kll)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 30 to Pin
Connect Input to Pin
2.5
26
22
26
24
5
26
Open
26
24
2.5
22
22
26
24
5
22
Open
26
24
10
22
Input Signal
26
25
FOR BUFFERED INPUT
Input Impedance (Mil)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 29 to Pin
Connect Input to Pin
100
26
22
24
30
100
26
Open
24
30
100
22
22
24
30
100
22
Open
24
30
100
22
29
25
30
DIGITAL OUTPUT CODING
Analog Input Voltage Range
Digital Outputs
Oto +5V
Oto +10V
±2.5V
±5V
±10V
+5.0000
+4.9982
+ 10.0000
+9.9963
+2.5000
+ 2.4982
+5.0000
+4.9963
+ 10.0000
+9.9927
+2.5006
+2.4994
+2.4982
+ 5.0012
+4.9988
+4.9963
+0.0006
-0.0006
-0.0018
+ 0.0012
- 0.0012
- 0.0037
+0.0024
-0.0024
-0.0073
+0.0006
0.0000
+0.0012
0.0000
-2.4994
-2.5000
-4.9988
-5.0000
-9.9976
-10.0000
MSB
LSB
0000
0000
0000
0000
0000
000f1"
0111
1111
111(1"
1000
0000
OCXW"
1111
1111
1111
1111
111(1"
1111
r/rI(lf/ (l(lr/rj f68rJ(l"
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is complementary straight binary
(CSB).
2. For bipolar input ranges, output coding is complementary offset binary
(COB).
3. For bipolar input ranges, complementary two's complement coding (CTC)
can be obtained by using the complement of the most significant bit MSB.
"'Mm§ is available on pin 13. See Pin Designations.
4. For 0 to + 5V or :t 2.5V input ranges, 1 LSB for 12 bits: 1.22mV. 1LSB for
10 bits: 4.88mV.
5. For 0 to + 10V or :t 5V input ranges, 1 LSB for 12 bits: 2.44mV. 1LSB for
10 bits:9.77mV.
6. For :t 10V input range, 1 LSB for 12 bits: 4.88mV. 1LSB for 10 bits: 19.5mV.
·Voltages given are the theoretical values for the transitions Indicated. Ideally,
with the converter continuously converting, the output bits indicated as 16 will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
6-16
EXAMPLE: For an ADC85-12 operating on its ± 10V input range, the transition
from digital output 111111111111 to 111111111110 (or vice versa) will ideally
occur at an input voltage of -9.9976 volts( - Full Scale + V, LSB). Subsequently, any Input voltage more negative than -9.9976 volts will give a digital output
of all "1's". The transition from digital output loooooooooootoOlll11111111
will ideally occur at an input voltage of -0.0024 volts ( - V,LSB) and the 0000
0000 0001 to 0000 0000 0000 transition should occur at + 9.9927 volts (+ Full
Scale -l\LSB). An input more positive than + 9.9927 volts will give all "O's".
ADC87
I;
J
_
12-Bit, 8J.1.sec
MICRO NETWORKS
MILITARY
AID CONVERTER
FEATURES
• Fully Guaranteed
-55°C to +125°C Operation
• 8Jlsec Max Conversion Time
• CompletelVersatile
AID Function:
Internal or External Clock
Internal Reference
User-Optional Input Buffer
Serial and Parallel Outputs
Short-Cycle Pin
• No Missing Codes
Guaranteed Over Temperature
• Low Drift:
Gain ±20ppm/oC Max
Offset ±5ppm/oC Max
• Pin-Compatible ADC84/85
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
DESCRIPTION
The Micro Networks ADC87 is a high-performance, 12-bit,
successive approximation, AID converter in a hermetically
sealed, ceramic, 32-pin dual-in-line package. It is pin-compatible
with industry-standard ADC85 type 12-bit AID converters and is
the first device of this type to offer fully guaranteed performance
specifications over the full -55°C to +125°C operating
temperature range. It also guarantees an 8/Lsec max conversion
time compared to the 10/Lsec of other devices in its class.
ADC87 linearity is guaranteed better than ± V2LSB, and no
misSing codes is guaranteed over temperature. Max gain drift is
a low ±20ppm/oC; max offset drift a low ±5ppm of FSR/oC.
ADC87 is extremely versatile. It has its own reference and
internal clock; yet it can run from an external clock. There are 5
user-selectable input ranges, serial and parallel outputs, a shortcycle pin, a user-optional high-impedance input buffer and pins
for optional offset and gain adjustments.
For military aerospace or harsh-environment commercial/industrial applications, ADC87H/B CH is fully screened to
MIL-H-38534 in Micro Networks' MIL-STD-1772 qualified facility.
ADC87 is ideally suited for fast data digitizing in militaryl
aerospace applications. Its rugged, hermetically sealed, ceramic
package has outstanding thermal characteristics and can withstand the harshest environments.
Dimensions in Inches
(millimeters)
~
MICRO NETWORKS
December 1991
Copyright 1991
Micro Networks
All rights reserved
324 Clark St.. Worcester. MA 01606 (508) 852·5400
6-17
ADCS712-Bit S/lsec AID CONVERTERS
ABSOWTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
ADC87
ADC87H, ADC87H/B
Storage Temperature Range
Positive Supply (+Vcc, Pin 28)
Negative Supply (-Vcc, Pin 31)
Logic Supply (+Vdd, Pin 16)
Digital Inputs (Pins 14, 21)
Analog Inputs: Direct (Pins 24, 25)
Buffer (Pin 30)
-55°C to + 125°C
-25°C to +85°C
-55°C to + 125°C
-65°C to + 150°C
-0,5 to +18 Volts
+0.5 to -18 Volts
-0.5 to +7 Volts
-0.5 to +5.5 Volts
±25 Volts
±15 Volts
PART N U M B E R - - - - - - - - - - ADC87H/B CH
Standard part is specified for -25°C to +850~
operation.
Add "H" for specified -55°C to + 125°C
operation. _ _ _ _ _ _ _ _ __
Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.
SPECIFICATIONS (T A = +2SOC, ±Vcc= ± 1SV, +Vdd = +5V unless otherwise indicated)
MIN,
ANALOG INPUTS
TYP.
MAX.
o to
Input Voltage Ranges: Unipolar
Bipolar
2.5
5
Direct Input Impedance (Note 1): 0 to +5V, ± 2.5V
to +10V. ±5V
±10V
o
Buffer Amplifier (Note 2): Gain Accuracy
Input Impedance (Note 1)
Input Bias Current (Note 1)
Offset Voltage
Settling Time (20V Step to ± 0.01%FSR)
kG
kG
kG
10
10'0
±0.01
10'2
±2
±4
3
UNITS
Volts
Volts
+5,0 to +10
± 2.5, ±5, ± 10
±7
±1Q
%
G
nA
mV
~sec
DIGITAL INPUTS (Start Convert, Short Cycle)
Logic Levels: Logic "1"
Logic "0"
+0.8
Volts
Volts
+80
-3.2
~
mA
±V2
±1
LSB
LSB
+2.0
Logic Currents: Logic "1" (VIH =+2.4V)
Logic "0" (VIL = +0.4V)
TRANSFER CHARACTERISTICS (Note 3)
Linearity Error: Initial (+25°C)
Over Temperature (Note 4)
±V4
± '/2
Differential Linearity Error
Differential Linearity Drift (Notes 1, 4)
±1/2
±2
Guaranteed Temperature Range for No Missing Codes:
ADC87
ADC87H, ADC87H/B
-25
-55
LSB
ppm of FSR/oC
+85
+125
°C
°C
Unipolar Offset Error (Notes 5, 6): Initial (+25°C)
Drift (Note 4)
±0.1
±3
±0.2
±5
%FSR
ppm of FSR/oC
Bipolar Zero Error (Notes 5. 7): Initial (+25°C)
Drift (Note 4)
±0.1
±5
±0.25
±10
%FSR
ppm of FSR/oC
Gain Error (Notes 5, 8): Initial (+25°C)
Drift (Note 4)
±0.1
±10
±0.25
±20
%
ppm/oC
+0.4
Volts
Volts
DIGITAL OUTPUTS (Parallel, Serial, Clock, Status)
Output Coding (Note 9): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (lsoUReE:5320~)
Logic "0" (ISINK :53.2mA)
CSB
COB, erc
+2.4
REFERENCE OUTPUT
Internal Reference: Voltage
Accuracy (Note 1)
Tempeo
External Current
6-18
+6.3
±5
±5
±10
200
Volts
%
ppm/oC
~
DYNAMIC CHARACTERISTICS
MIN.
Conversion Time (Note 10)
~ternal Clock Frequency (Note 1)
1.5
Start Convert Pulse Width (Note 1)
TYP.
MAX.
UNITS
7
8
"sec
MHz
1.7
nsec
50
Delay Falling Edge of Start Convert to Status="1" (Note 1)
50
100
nsec
Delay Falling Edge of Status to LSB Valid (Note 1)
25
120
nsec
Delay Rising Clock Edge to Output Data Valid
(Parallel, Serial, Status)
75
140
nsec
+15
-15
+5
+15.5
-15.5
+5.25
Volts
Volts
Volts
±0.01
±0.01
±0.OO5
±0.02
±0.02
±0.01
%FSR/%Supply
%FSR/%Supply
%FSR/%Supply
Current Drain: +15V Supply
-15V Supply
+5V Supply
+27
-27
+60
+35
-35
+75
mA
mA
mA
Power Consumption
1110
1425
mW
POWER SUPPLIES
i-Power Supply Range: +15V Supply
-15V Supply
+5V Supply
._--
+14.5
-14.5
+4.75
Power Supply Rejection (Note 11): +15V Supply
-15V Supply
+5V Supply
SPECIFICATION NOTES:
8. Gain error is defined as the error In the slope of the converter transfer function.
It is expressed as a percentage and is equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value for the full input voltage span
from the input voltage at which the output changes from 1111 1111 1111 to 1111
,. These parameters are listed for reference only ana are not tested.
2. When using the internal buffer amplifier, buffer settling time must be added to
converSion time when calculating system throughput. See section tabled Internal Buffer Amplifier.
3. FSR=full scale range. A unit connected for a Ota +5Vor ± 2.5V input range has
a 5V FSR. A unit connected for a to +lOVor ±5V input range has a 10V FSR,
etc .. 1 LSB for 12 bits is equivalent to O.024%FSR.
4. Listed specIfication applies over the _25°C to +85°C temperature range for
ADC87. Listed specification appliesoverthe -55°C to +125°Ctemperature range
1111 1110 to the input voltage at which the output changes from 0000 0000 0001
to 0000 0000 0000.
a
9. CSB=complementary straight binary. COB=complementary offset binary.
CTC=complementary two's complement. See table of transition voltages in section labeled Digital Output Coding.
10. Conversion is initiated on the falling edge of the start convert command. and conversion time is defined as the width of status (E.O.C.). Conversion time may be
shortened, with lower resolution, by short cycling. Connect pin 2 (Bit 11) to pin
14 (Short Cycle) for 10-bit conversions. See Timing Diagram.
11. Power supply rejection is defined as the change in the analog input voltage at
for ADC87H and ADC87H/B.
5. Initial error is adjustable to zero.
6. Unipolar offset error is defined as the difference between the ideal and the actual input voltage at which the digital output just changes from 1111 11111110 to
1111 11111111 when operating the ADC87 on a unipolar range. The ideal value
at which this transition should occur is + 'hLSB. See Digital Output Coding.
7. Bipolar zero error is defined as the difference between the ideal and the actual
which the 1111 11111110 to 11111111 1111 or 0000 0000 0000 to 0000 0000 0001
output transitions occur versus a change in power-supply voltage.
input voltage atwhich the digital output just changes from 0111 11111111 to 1000
Specifications subject to change without notice as Micro Networks reserves the
right to make improvements and changes in its products.
0000 0000 when operating the ADC87 on a bipolar range. The ideal value atwhich
this transition should occur is -'hLSB. See Digital Output Coding.
BLOCK DIAGRAM
Clock Adjust (17)
Start Convert (21)
Clock Output (19)
~
(20) Status (E.D.C.)
(14) Short Cycle
(32) Serra I Output
Successive
Approximation
Register
-~
(12) Bif 1 (MSB)
(11) Bit2
(10) Bit 3
(9) Bit4
(8) Bit 5
(7) Bil6
(6) Bit 7
(5) BitB
(4) Bit 9
(3) Bit 10
(2) Bit 11
(1) elt 12 (LSB)
+ 15V Supply (28) 0----+
-15YSupply(31) 0----+
+ 5V Supply (16) 0----+
Digital Ground (15) 0----+
Analog Ground (26) 0 - - - - +
Buffer Qut (29)
Buffer In (30)
Ref. Out (IB)
~
Ref
12·8i1
D/A Converter
Summing Junction (22)
SkU
10V Range (24)
(27) Gain Adjust
I
Bipolar Offset (23)
20V Range (25)
(13) MSB
-vv
-v :~"I.
J
Comparator
6·19
PIN DESIGNATIONS
•
32
16
17
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit 12 (LSB)
Bit 11
Bit 10
Bit9
Bit 8
Bit 7
Bit6
Bit5
Bit 4
Bit3
Bit 2
Bit 1 (MSB)
MSB
Short Cycle
Digital Ground
+5VSupply(+Vdd)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Serial Output
-15VSupply (-Vecl
Buffer Input
Buffer Output
+15V Supply (+Vecl
Gain Adjust
Analog Ground
20V Range
10V Range
Bipolar Offset
Summing Junction
Start Convert
Status (E.O.C.)
Clock Output
Reference Output (+6.3V)
Clock Adjust
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracies.
Analog and digital grounds(pins 15 and 26) are not connected
to each other internally and must be tied together as close to
the package as possible, preferably through a large analog
ground plane underneath the package. If these commons
must be run separately, a nonpolarized, 0.01 to O.lI'F bypass
capacitor should be connected between pins 15 and 26 as
close to the package as possible and wide conductor runs
should be used.
Coupling between the analog inputs and digital signals
should be minimized to reduce noise pickup. The Summing
Junction (pin 22) is the direct input to the internal comparator
and is particularly noise susceptible. In bipolar operation,
where pin 22 is connected to pin 23, a short jumper should be
used, and when external offset adjustment is employed, the
1.8 megohm resistor should be located as close to the
package as possible.
Power supplies should be decoupled with tantalum or elec·
trolytic capacitors located close to the device package. For
optimum results, 11'F capacitors paralleled by O.OlI'F ceramic
capacitors should be connected as shown in the diagrams
below. An additional O.OlI'F ceramic bypass capacitor should
be located close to the package connecting the gain adjust
point (pin 27) to analog ground.
Pinl6'
I"F
Pin 15
0
I
I
T T
STATUS OUTPUT-The Status or End of Conversion (E.O.C.)
output will be set to a logic "1" by the falling edge of the Start
Convert; will remain high during conversion; and will drop to a
logic "0" whIm conversion is complete. Due to propagation
delays, the least significant bit of any conversion will not be
valid unli( a maximum of 120nsec after the Status output has
gone low.
SHORT CYCLING-For applications requiring less than 12
bits resolution, these converters can be truncated or short
cycled at the desired number of bits with a proportionate decrease in conversion time. The connections shown below
both increase the clock rate and truncate theconverterto pro·
vide the minimum conversion time for a given resolution.
Resolution (Bits)
12
10
8
Connect Pin 17 to Pin
Connect Pin 14 to Pin
Conversion Speed v------------,
(21)
Analog Input
(13)
(8)
.>--------.., (24)
MN346
ADC87
!-------Throughput - - - - - \
Start Convert
USING A TRACK/HOLD AMPLIFIER WITH AN ADC87When using a track-hold (T/H) amplifier with an ADC87, the T/H
can be driven directly (or inverted) from the AID's Start Convert signal. When the Start is high prior to the beginning of a
conversion, the T/H can be in the tracking or signal acquisi·
tion mode. The falling edge of the start signal initiates the
conversion and simultaneously commands the T/H into the
Status (E.O.C.)
Conversion Time
Throughput Rate
T/H Acquisition Time
AID Conversion Time
100kHz
21'sec
81'sec
6·21
OPTIONAL EXTERNAL OFFSET AND' GAIN ADJUSTMENTS
-Initial offset and gain errors may be trimmed to zero using
external potentiometers as shown in the following diagrams.
Adjustments should be made following warm-up, and to
avoid interaction, offset should be adjusted before gain.
Fixed resistors can be ±20% carbon composition or better.
Multiturn potentiometers with TCR's of 100ppm/ C or less
are recommended to minimize drift with temperature. If these
adjustments are not used, pin 22 should be connected as described in the Input Range Selection section and a 0.011'F
capacitor should be connected from pin 27 to pin 26.
00000001 to 0000 0000 0000 transition is ideally supposed to
occur (see Digital Output Coding). While continuously converting, adjust the gain potentiometer until all the output bits
are "0" and the LSB "flickers" on and off. A O.OII'F capacitor
should be connected from Gain Adjust (pin 27) to Analog
Ground (pin 26).
D
+ISV
+15V
1
22~V~Ok!!
Pin
10k\!
I.BMD
Pin
27
~
Pin
-ISV
or
OFFSET ADJUSTMENTS-Connect the offset potentiometer as shown and apply the input voltage at which the 1111
11111110to 111111111111 transition is ideally supposed to
occur (see Digital Output Coding). While continuously converting, adjust the offset potentiometer until all the output
bits are "1" and the LSB "flickers" on and off.
Pin
lBOkO
10M!!
26
J
_F -15V
or
+ 15V
llOk!!
to
lOOk!!
+ISV
lBOk!! I10kD
22~r~OkU
-;:
GAIN ADJUSTMENT-Connect the gain potentiometer as
shown below and apply the input voltage at which the 0000
-15V
Offset Adjust
Gain Adjust
INPUT RANGE SELECTION
Analog Input Voltage Range
Pin Connections
a to
+5V
Oto +10V
±2.5V
±5V
±10V
FOR NORMAL INPUT
Input Impedance (kll)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 30 to Pin
Connect Input to Pin
2.5
26
22
26
24
5
26
Open
26
24
2.5
22
22
26
24
5
22
Open
26
24
10
22
Input Signal
26
25
FOR BUFFERED INPUT
Input Impedance (Mil)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 29 to Pin
Connect Input to Pin
100
26
22
24
30
100
26
Open
24
30
100
22
22
24
30
100
22
Open
24
30
100
22
29
25
30
DIGITAL OUTPUT CODING
Digital Outputs
Analog Input Voltage Range
Oto +5V
o to
+10V
±2.5V
±5V
±10V
LSB
MSB
+ 5.0000
+ 4.9982
+ 10.0000
+9.9963
+ 2.5000
+ 2.4982
+ 5.0000
+ 4.9963
+ 10.0000
+9.9927
0000
0000
0000
0000
0000
000i1'
+2.5006
+ 2.4994
+ 2.4982
+ 5.0012
+4.9988
+ 4.9963
+ 0.0006
- 0.0006
-0.0018
+0.0012
-0.0012
-0.0037
+0.0024
-0.0024
-0.0073
0111
1111
1000
0000
1110'"
r6~0'"
0000'"
+ 0.0006
0.0000
+0.0012
0.0000
- 2.4994
- 2.5000
-4.9988
- 5.0000
-9.9976
-10.0000
1111
1111
1111
1111
1110'"
1111
ri0'~ 00rifD
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is complementary straight binary
(GSB).
2. For bipolar input ranges, output coding is complementary offset binary
(GOB).
3. For bipolar input ranges, complementary two's complement coding (GTC)
can be obtained by using the complement of the most significant bit MSB,
MSB is available on pin 13. See Pin Designations.
4. For a te +5Vor ±2.SV input ranges, lLSB for 12 bits= 1.22mV. lLSB for
10 bits = 4.BBmV.
5. For a to + 10V or ± SV input ranges, 1LSB for 12 bits = 2.44mV. 1LSB for
10 bits = 9.77mV.
6. For ± 10V input range, 1LSB for 12 bits = 4.B8mV. 1LSB for 10 bits = 19.5mV.
• Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as" will
change from" 1" to "0" or vice versa as the input voltage passes through the
level indicated.
6-22
EXAMPLE: For an ADG87 operating on its ± IOV input range, the transition from digital
output 1111 1111 1111 to 1111 1111 1110 (or vice versa) will ideally occur at an input
voltage of -9.9976 volts (-Full Scale + V2LSB). Subsequently, any input voltage more
negative than -9.9976 volts will give a digital output of all "1 's". The transition from
digital output 1000 0000 0000 to 0111 11111111 will ideally occur at an input voltage
of -0.0024 volts (- V2LSB) and the 0000 0000 0001 to 0000 0000 0000 transition
should occur at +9.9927 volts (+Full Scale -3',LSB). An input more positive than
+9.9927 volts will give all "O's".
l1JJ
_
MN574A
/lP-COMPATIBLE
MICRO NETWORKS
25/lsec, 12-Bit
AID CONVERTER
DESCRIPTION
FEATURES
• LowCost
• Complete, 25JLSec, 12-Bit
AID Converter with Internal:
Clock
Reference
Control Logic
• HI-574A and AD574A Pin
and Function Compatible
• Full 8 or 16-Bit p.P Interface:
Three-State Output Buffer
Chip Select, Address Decode
ReadlWrite Control
• No Missing Codes Guaranteed
Over Temperature
• Operation with ± 12V or
± 15V Supplies
• 28-Pin DIP, 450mW Max Power
• Full Mil Operation
-55"C to +125"C
MN574A's combination of bipolar and CMOS technologies
represents the latest advances in 574N674A evolution, and
all problems associated with earlier models from other
manufacturers have been solved. These devices are truly
TIL compatible over all temperature ranges, and they are
not prone to CMOS latch-up at power-on. Their internal clock
has minimal drift, and conversion time is guaranteed over all
temperature ranges. Bus access time is guaranteed not to
exceed 150nsec, and the Ao line may be toggled freely with
no fear of output-data overlap thanks to break-before-make
action on the output buffer. At 450mW max, power consumption is almost half that of competing devices.
MN574A is ideal for most military/aerospace and industrial,
general-purpose, data-acquisition applications. The device is
multi-sourced and available in 5 different electrical grades
fully specified for either O°C to +70°C or -55°C to + 125°C
operation. Each device guarantees integral linearity and no
missing codes as summarized below. Add "/B" to either the
SorT grade units for environmental stress screening.
28-PIN CERAMIC DIP
0.108(2.74)
0166 (4.22)
MN574A is a complete, low-cost, 12-bit, successiveapproximation AID with internal buried-zener reference
(+ 10V), clock, and control logic. MN574A is packaged in a
28-pin DIP and contains all the interface logic necessary to
directly mate to most popular 8 and 16-bit microprocessors.
MN574A's 3-state output buffer connects directly to the p.P's
data bus and can be read either as one 12-bit word or as two
8-bit bytes. Chip select, chip enable, address decode (short
cycle), and read/write (read/convert) control inputs enable
MN574A to connect directly to system address bus and controllines and operate totally under processor control.
(1120(3D5)
0.240 (610)
Dimensions in Inches
(millimeters)
Model
MN574AJ
MN574AK
MN574AL
MN574AS
MN574AS/B'
MN574AT
MN574AT/B'
Temperature Range
O°C to +70°C
O°C to +70°C
O°Cto +70°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
Linearity
Error Max
(T min to T max)
±1LSB
±'hLSB
±'hLSB
±1LSB
±1LSB
±1LSB
±1LSB
No Missing
Codes
(T min to T max)
11 Bits
12 Bits
12 Bits
11 Bits
11 Bits
12 Bits
12 Bits
*Includes environmental stress screening
~
December 1991
Copyright, 1991
MIcro Networks
All rights reserved
MICRO NETWORKS
324 Clark St., Worcester, MA 01606
(508) 852-5400
6-23
MN574A I1P-COMPATIBLE, 25l1sec, 12-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN574AJ, K, L
MN574AS, SIB, T, TIB
Storage Temperature Range
Positive Supply (+Vee, Pin 7)
Negative Supply (-Vee, Pin 11)
Logic Supply (+Vdd, Pin 1)
Digital Inputs (Pins 2-6)
Analog Inputs: Pins 10, 12 and 13
Pin 14
Analog Ground (Pin 9)
to Digital Ground (Pin 15)
Ref. Out (Pin 8) Short Circuit Duration
PART NUMBER - - - - - - - - - - - MN574AX/B
O°C to +70°C
-55°C to +125°C
-65°C to + 150°C
o to + 16.5 Volts
o to -16.5 Volts
o to +7 Volts
-0.5 to ( + Vdd + 0.5) Volts
±16.5 Volts
±24 Volts
II
Select suffix J, K, L, S or T for
desired performance and specified
temperature range. - - - - - - - - - - - - - - - - ' .
Add "/B" suffix to S or T models
for environmental stress screening. - - - - - - - - - - - '
±1 Volt
Continuous to Ground
Momentary to ± Vee
DESIGN SPECIFICATIONS ALL UNITS (TA=+25"C, ±Vcc= ±12V or ±15V, +Vdd=+5V unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Input Impedance: 0 to + 10V, ±5V
o to +20V, ±10V
TYP.
oto
Input Voltage Ranges: Unipolar
Bipolar
4.7
9.4
MAX_
+10,0 to +20
±5, ±10
5
10
UNITS
Volts
Volts
5.3
10.6
k!l
k!l
+5.5
+0.8
Volts
Volts
DIGITAL INPUTS CE, CS, RIC, AD, 12/8 (Note 2)
Logic Levels: Logic "1"
Logic "0"
Loading: Logic Currents
Input Capacitance
+2.0
-0.5
-5
±0.1
5
+5
pA
pF
DIGITAL OUTPUTS DBO-DBll, STS (Note 2)
Output Coding (Note 3): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "I" (lsource:5 500pA)
Logic "0" (lslnk :51.SmA)
Leakage (DBO-DB11) in High-Z State
Straight Binary
Offset Bi nary
+0.4
Volts
Volts
+5
pA
+2.4
-5
Output Capacitance
±0.1
pF
5
INTERNAL REFERENCE
Reference Output (Pin 8): Voltage
Drift
Output Source Current (Note 4)
+10.1
Volts
ppm/oC
mA
+5
±lS.5
+5.5
Volts
Volts
Current Drains: +Vcc Supply
-Vcc Supply
+Vdd Supply
+3.5
-15
+9
+5
-20
+15
mA
mA
mA
Power Consumption (± Vcc= ± 15V)
325
450
mW
13
20
17
25
~sec
+9.9
+10.0
±10
2.0
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc
+Vdd
±11.4
+4.5
Power Supply Rejection (See Performance Specifications)
DYNAMIC CHARACTERISTICS
Conversion Time (Notes I, 2, 5): 8-Bit Cycle:
12-Bit Cycle:
10
15
"sec
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data sheet.
2. Listed specifications guarahteed over each device's full specified temperature range
as determined by part number suffix.
3. See table of transition voltages in section labeled Output Coding.
4. The internal reference can be used to drive an external load, and it is capable of
supplying up to 2mA over and above the requirements of the reference-in and
bipolar-offset resistors. The external load should not vary during a conversion. The
reference output does not require a buffer when operating with either ± 15V or ± 121/
supplies.
5. If a conversion is started with Ao (pin 4) low, a full 12-bit conversion cycle is initiated.
If Ao is high, a shorter 8-bit conversion is initiated. Conversion time is defined as
the width of the Status Output pulse. See the Timing sections for more details.
6-24
6. MN574AJ, K, L are futly specified for O'C to +70'Coperation. MN574AS, T, are
fully specified for -55°C to +125°C operation.
7. Adjustable to zero with external potentiometer.
S. Unipolar offset error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0000 0000 0000 to 0000
00000001 when operating the MN574A on a unipolar range. The ideal value at
which this transition should occur is +1hLSB. See Digital Output Coding.
9. Listed maximum change specifications (temperature coefficients) for unipolar offset, bipolar offset and full scale calibration error correspond to the maximum change
from the initial value (+25°C) to the value at Tmin or T max.
PERFORMANCE SPECIFICATIONS (Typical at TA = +25°C, ± Vcc = ± 12V or ± 15V, + Vdd = + 5V unless otherwise indicated)
MODEL
574AJ
574AK
574AL
574AS
574AT
UNITS
±1
±1
± 112
±'/2
±'/2
±'/2
±1
±1
±'/2
±1
LSB
LSB
11
11
12
12
12
12
11
11
12
12
Bits
Bits
Unipolar Offset Error (Notes 7, 8):
Initial ( + 25°C) (Max)
Drift (Max)
Max Change to T min or T max (Note 9)
±2
±10
±2
±1
±5
±1
±1
±5
±1
±2
±S
±2
±1
±2.5
±1
LSB
ppm of FSR/oC
LSB
Bipolar Offset Error (Notes 7, 10):
Initial ( + 25°C) (Max)
Drift (Max)
Max Change to T min or T max (Note 9)
±4
±10
±2
±4
±5
±1
±2
±5
±1
±4
±10
±4
±4
±5
±2
LSB
ppm of FSR/oC
LSB
±0.25
±0.47
±0.22
±50
±9
±0.25
±0.37
±0.12
±27
±5
±0.25
±0.3
±0.05
±10
±2
±0.2S
±0.7S
±0.5
±50
±20
±0.2S
±O.S
±0.25
±2S
±10
%FSR
%FSR
%FSR
ppm of FSR/oC
LSB
±2
±2
±'/2
±1
±1
±'12
±1
±1
± '12
±2
±2
±'/2
±1
±1
±'12
LSB
LSB
LSB
Integral Linearity Error: Initial ( + 25°C) (Max)
T min to T max (Max, Note 6)
Resolution for Which No Missing
Codes is Guaranteed: Initial (+ 25°C)
T min to T max (Note 6)
Full Scale Calibration Error (Notes 7, 11):
Initial (+ 25°C) (Max)
T min to T max Without Initial Adjustment
T min to T max With Initial Adjustment
Drift (Max)
Max Change to T min or T max (Note 9)
Power Supply Rejection (Note 12)
+13.5V,; +Vcc,; +16.5Vor +11.4V,; +Vcc,; +12.6V
-16.5V,; - Vcc,; -13.5V or -12.6V,; -Vcc,; -11.4V
+ 4.5V,; + Vdd,; + 5.5V
10. Bipolar offset error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0111 1111 1111 to 1000
0000 0000 when operating the MN574A on a bipolar range. The ideal value at which
this transition should occur is - V2LSB. See Digital Output Coding.
11. Listed specs assume a fixed 500 resistor between Ref Out (pin 8) and Ref In (pin
10) and a fixed 500 resistor between Ref Out (pin 8) and Bipolar Offset (pin 12,
bipolar configurations) or Bipolar Offset grounded (unipolar configurations). Full
scale calibration error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 1111 1111 1110 to 1111
1111 1111. Ideally, this digital output transition should occur at an analog voltage
1V2LSB's below the nominal full scale voltage. See Digital Output Coding.
12. Listed spec is the max change in full scale calibration accuracy as supplies are
varied over the range indicated.
Specifications subject to change without notice as Micro Networks reserves the right
to make improvements and changes in its products.
I
ORDERING INFORMATION
Part
Number
MN574AJ
MN574AK
MN574AL
MN574AS
MN574AS/B (3)
MN574AT
MN574AT/B (3)
Specified
Temperature
Range
DoC to +70°C
DoC to +70°C
DoC to +70°C
-55°C to + 125°C
-55°C to +125°C
-55°C to + 125°C
-55°C to + 125°C
1. Maximum error expressed in LSB's for 12 bits.
BLOCK DIAGRAM
+25°C
Temp.
No Missing
Codes
Over Temp.
±1
±'/2
±';'
±1
±1
±';'
±';'
±1
±';'
±';'
±1
±1
±1
±1
11 Bits
12 Bits
12 Bits
11 Bits
11 Bits
12 Bits
12 Bits
Integral Linearity (1)
2. Expressed in ppm of FSR/oC.
Max.
Offset
Drift (2)
Max.
Full Scale
Drift (2)
Max.
Power
(mW)
±10
±5
±5
±5
±5
±2.5
±2.5
±50
±27
±10
±50
±50
±25
±25
450
450
450
450
450
450
450
3. Includes environmental stress screening.
.;. 5V Supply (1) I - - .
Data Mode Select 12/8 (2) ,~
Chip Select
es (3)
1,=::[==~S~UC;C~ES~S~'V~E==l:===l---.(J (28) Status Output
APPROXIMATION REGISTER
(27) DB11 (MSB)
(26) 0810 (Bit 2)
(25) DB9 (Bit 3)
Byte Address Ao (4) \..
Read/Convert RIC (5) '-
(24) 088 (Bit 4)
Chip Enable CE (6)l
+ 12VJ + 15V Supply (7l
+10VRetOutI8)
(23) OB7(BII5)
(22) DBS (Bit 6)
, (21) OB5(BIt 7)
(20) DB4 (BiI8)
C"----+-
-:'1
:~
:J
Analog Ground 19) ~
--1
.. 10\1 Ret In 1101 ->--_ _ _'.;,;99;;,'''''''_ _ _
- 12\11 _. 15'10 Supply 111)
~
(19) OB3 (Bit 9)
(18) DB2 (Bit 10)
(17) DBI (Bit 11)
(16) DBD (LSB)
(15) Dlgllal Ground
J------+.
0-------------+-----1
Bipolar Ollsell12) ......
10V Input (13) 0 - - - - - - - - ,
20\1 Input r14) 10-_~~5k~"_ _~_ _~_ __ _ '
CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.
6-25
PIN DESIGNATIONS
•
PIN 1
28
14
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
+ 5V Supply (+ vdd)
Data Mode Select 12i8
Chip Select CS
Byte Address Ao
Read/Convert R/C
Chip Enable CE
+ 12V/ + 15V Supply (+ Vcd
+ 10V Ref Out
Analog Ground
+ 10V Ref In
- 12V/- 15V Supply (- Vcd
Bipolar Offset
10V Input
20V Input
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
Status Output
DB11 (MSB)
DB10 (Bit 2)
DB9 (Bit 3)
DB8 (Bit 4)
DB7 (Bit 5)
DB6 (Bit 6)
DB5 (Bit 7)
DB4 (Bit 8)
DB3 (Bit 9)
DB2 (Bit 10)
DB1 (Bit 11)
DBO (LSB)
Digital Ground
DESCRIPTION OF OPERATION
The MN574A is a complete 12-bit ND converter. It utilizes the successive approximation conversion technique and contains all
required function blocks - successive approximation register
(SAR), D/A converter, comparator, clock and reference - internal
to its package. The MN574A mates directly to most popular 8, 16
and 32-bit microprocessors and contains all the necessary address
decoding logic, control logic, and ~te output buffering to operate
completely under processor control. In most applications, the
MN574A will require only power supplies, bypass capacitors, and
two fixed resistors to provide the complete ND conversion function.
The completeness ofthis device makes it most convenient to think
of the MN574A as a function block with specific inputloutput and
transfer characteristics, and it is quite unnecessary to concern
oneself with its inner workings.
Operating the MN574A under microprocessor control (it also functions as a stand-alone ND) consists, in most applications, of a series
of read and write instructions. Initiating a conversion requires
sending a command from the processor to the ND and involves a
write operation. Retrieving digital output data is accomplished with
read operations. Once the proper signals have been received and
a conversion has begun, it cannot be stopped or restarted, and
digital output data is not available until the conversion has been completed. Immediately following the initiation of a conversion cycle, the
MN574A's Status Output (also called Busy Line or End of Conversion (E.O.C.) Line) rises to a logic "1" indicating that a conversion
is in progress. At the end of a conversion, the internal control logic
will drop the Status Output to a "0" and enable internal circuitry to
permit output data to be read by external command. By senSing the
state of the Status Output or by waiting an appropriate amount of
time, the microprocessor will know when the conversion is complete
and that output data is valid and can be read.
If the MN574A is operated with 12-bit or wider microprocessors, all
12 output bits can be 3-state enabled simultaneously, permitting data
collection with a single read operation. If the MN574A is operated
with an 8-bit "p. output data can be formatted to be read in two 8~bit
bytes. The first will contain the 8 most significant bits (MSB's). The
second will contain the remaining 4 least significant bits (LSB's),
in a left justified format, with 4 trailing "O's".
Decoupling capacitors should be used on all power supply pins; the
+5V supply decoupling capacitors should be connected directly
from pin 1 to pin 15 (Digital Ground), and the +Vccand -Vee supplies should be decoupled directly to pin 9 (Analog Ground). A
suitable decoupling capacitor pair is usually a relatively large tantalum (1 -10"F) in parallel with a smaller (0.01 -to" F) ceramic disc.
Coupling between analog inputs and digital signals should be
minimized to avoid noise pickup. Pins 10 (Reference In), 12 (Bipolar
Offset), and 13 and 14 (Analog Inputs) are particular.ly noise susceptible. Circuit layout should attempt to locate the MN574A and
associated analog input circuitry as far as possible from high-speed
digital circuitry. The use of wire-wrap circuit construction is not
recommended. Careful printed-circuit construction is preferred. If
external offset and gain adjust potentiometers are used, the pots
and associated series resistors should be located as close to the
MN574A as possible. If no trim adjusting is required and fixed
resistors are used, they likewise should be as close as possible.
Analog (pin 9) and Digital (pin 15) Ground pins are not connected
to each other internal to the MN574A. They must be tied together
as close to the unit as possible and both connected to system analog
ground, preferably through a large analog ground plane beneath
the package. If these commons must be run separately, a nonpolarized 0.01"F ceramic bypass capaCitor should be connected
between pins 9 and 15 as close to the unit as possible and wide
conductor runs employed. Pin 9 (Analog Ground) is the ground
reference point for the MN574A's internal reference. It should be connected as close as possible to the analog input signal reference
point.
POWER SUPPLY DECOUPLING
Pin 1 °1:'F
r
I
T
I
5V
001+F
T"
Pin 15 o_.J._ _----'
___ ' Digital
Ground
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS AND GROUNDING - Proper attention to layout and decoupling is necessary to obtain specified accuracy from the MN574A. It is critically important that the MN574A's
power supplies be filtered, well regulated, and free from highfrequency noise. Use of noisy supplies may cause unstable output
codes to be generated. Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless
great care is used in filtering any switching spikes present in the
output.
6·26
CONTROL FUNCTIONS - Operating the MN574A under
microprocessor control is most easily understood by examining the
assorted control-line functions in a truth table. Table 1 below is a
summary of MN574A control-line functions. Table 2 is the MN574A
Truth Table.
Unless Chip Enable (CE, pin 6, logic "1"= active) and Chip Select
(CS, pin 3, logic "0" = active) are both asserted, various combinations of logic signals applied to other control lines (RIC, 1218 and
Ao) will have no effect on MN574A operation. When CE and CS are
Table 1: MN574A Control Line Functions
Pin
Designation
Definition
Function
CE (Pin 6)
Chip Enable
(active high)
Must be high ("1 ") to
either initiate a conversion or read output data.
0-1 edge may be used
to initiate a conversion.
CS
Chip Select
(active low)
Must be low ("0") to
either initiate a conversion or read output data.
1-0 edge may be used
to initiate a conversion
(Pin 3)
R/C (Pin 5)
Ao (Pin 4)
12/8 (Pin 2)
Read/Convert
("1"= read)
("0" = convert)
Byte Address
Short Cycle
Data Mode
Select
("1" = 12 bits)
("0" = 8 bits)
(Note 5)
Must be low ("0") to
initiate either 8 or 12-bit
conversions. 1-0 edge
may be used to initiate a
conversion. Must be high
("1 ") to read output data.
0-1 edge may be used
to initiate a read
operation
In the start-convert
mode, Ao selects 8-bit
(Ao = "1") or 12-bit
(Ao = "0") conversion
mode. When reading output data in 2 8-bit bytes,
Ao = "0" accesses 8
MSB's (high byte) and
Ao = "1" accesses 4
LSB's and trailing "O's"
(low byte).
When reading output
data, 12/8 ="1" enables
all 12 output bits simultaneously. 12/8 = "0" will
enable the MSB's or
LSB's as determined by
the Ao line.
both asserted, the signal applied to RIC (Read/Convert, pin 5) determines whether a data read (R/C="1") or a convert operation
(R/C="O") is initiated.
When initiating a conversion, the signal applied to Ao (Byte Address/Short Cycle, pin 4) determines whether a 12-bit conversion
is initiated (Ao="O") or an 8-bit conversion is initiated (Ao="1")_lt
is the combination of CE="1", CS="O", RIC = "0" and Ao="1" or
"0" that initiates a convert operation. The actual conversion can
be initiated by the rising edge of CE, the falling edge of CS, or the
falling edge of RIC as shown in the Truth Table and as described
in the section labeled Timing - Initiating Conversions. When
initiating conversions, the 121Bline is a "don't care".
When reading digital output data from the MN574A, CE and CS must
be asserted, and the Signals applied to 1218 and Ao will determine
the format of output data. Logic "1" applied to the RIC line will initiate
actual output data access. lithe 1218 line is a "1 ", all 12 output data
bits will be accessed simultaneously when the RIC line goes from
a "0" to a "1"_
If the 1218 line is a "0", output data will be accessible as two B-bit
bytes as detailed in the section labeled Timing - Reading Output
Data. In this situation, Ao="O" will result in the B MSB's being accessed, and Ao="1" will result in the 4 LSB's and 4 trailing zeros
being accessed. In this mode, only the 8 upper bits or the 4 lower
bits can be enabled at one time, as addressed by Ao. For these ap-
plications, the 4 LSB's (pins 16-19) should be hardwired to the 4
MSB's (pins 24-27). Thus, during a read, when Ao is low, the upper
B bits are enabled and present data on pins 20 through 27. When
Ao goes high, the upper 8 data bits are disabled. The 4 LSB's then
effectively present data to pins 24 to 27, and the 4 middle bits are
overridden so that zeros are presented to pins 20 through 23. See
the section labeled Hardwiring to 8-Bit Data Buses.
Table 2: MN574A Truth Table
CE
CONTROL INPUTS
1218
RIC
CS
MN574A OPERATION
A,
0
X
X
X
X
X
1
0
0
0
0
1-0
1-0
X
X
X
1-0
1-0
0
0
X
X
0
1
0
1
a
X
a
X
1
a
0
1
1
X
0
0
1
1
0
0
0
1
1
1
0-1
0-1
I
1
1
1
1
X
X
No Operation
No Operation
Initiates 12-Bit Conversion
Initiates 8-Bit Conversion
Initiates 12-Bit Conversion
Initiates 8·Bit Conversion
Initiates 12-Bit Conversion
Initiates 8-Bit Conversion
Enables 12-Bit Parallel
Output
Enables 8 MSB's
Enables 4 LSB's and
4 Trailing Zeros
TABLE " TABLE 2 NOTES:
1. "I" indicates TTL logic high (+2.OV minimum).
2. "a" indicates TTL logic zero (+0.8V maximum).
3. X indicates "don't care",
4. 0-1, 1-0 indicate logic transitions (edges).
5. Some vendors 574A's required the 1218 line to be hard wired to either +5V
(pin 1) or OV (pin 15). The MN574A may be hard wired as such or driven with
normal TTL signals.
6. Output data format is as follows:
MSB
XXXX
XXXX
xxxx
High
Bits
Middle
Bits
Low
Bits
8 MSB's
LSB
4 LSB's
TIMING - INITIATING CONVERSIONS - It is the combination
of CE="1", CS="O", R/C="O" and Ao="1" (initiate B-bit
conversion) or Ao="O" (initiate 12-bit conversion) that initiates a
convert operation_ As stated earlier, the actual conversion can be
initiated by the rising edge of CE, the falling edge of CS or the failing edge of RIC. Whichever occurs last will control the conversion;
however, all three may change simultaneously. The nominal delay
time from either input transition to the beginning of the conversion
(rising edge of Status) is the same for all three inputs (60nsec). If
it is desired that a particular one of these three inputs be responsible for starting the conversion, the other two should be stable a
minimum of 50nsec prior to the transition of that input.
Because the MN574A's control logic latches the Ao Signal upon conversion initiation, the Ao line should be stable immediately prior to
whichever of the above transitions is used to initiate the conversion_
The RIC transition is normally used to initiate conversions in standalone operation; however, it is not recommended to use this line to
initiate conversions in liP applications. If RIC is high just prior to a
conversion, there will be a momentary enabling of output data as
if a read operation were occurring, and the result could be system
6-27
I
:
bus contention. In most applications, Ao should be stable and RIC
low before either CE or CS is used to initiate a conversion.
Timing for a typical application is shown below. In this application,
CS is brought low, RIC is brought low, and Ao is set to its chosen
value prior to CE becoming a "1". This sequence can be accomplished in a number of ways including connecting CS and Ao
to address bus lines, connecting RIC to a readlwrite line (or its
equivalent) and generating a CE 0-1 transition using the system
clock. In this example, CS should be a "0" 50nsec prior to the CE
transition (tssc =50nsec min), RIC should be a "0" 50nsec prior
to the CE transition (tSRC =50nsec min), and Ao should be stable
Onsec prior to the CE transition (tSAC =Onsec min). The minimum
pulse width for CE="1" is 50nsec (tHEC =50nsec min) and both CS
and RIC must be valid for at least 50nsec while CE="1" (tHSC and
tHRC =50nsec min) to effectively initiate the conversion. Similarly,
Ao must be valid for at least 50nsec (tHAC =50nsec min) while CE
is high to effectively initiate the conversion. The Status Line rises
to a "1" no later than 200nsec after the rising edge of CE
(tosc =200nsec max). Once Status = "1 ", additional convert commands will be ignored until ongoing conversion is complete.
TIMING - RETRIEVING DATA - When a conversion is in progress
(Status Output="1"), the MN574A's 3-state output buffer is in its
high-impedance state. After the falling edge of Status indicates that
the conversion is done, the combination of CE = "1 ", CS= "0", and
R/C="1" is used to activate the buffer and read the digital output
data. If the above combination of control signals is met and the 1218
line has a "1" applied, all twelve output bits will become valid
simultaneously. If the 12/8 line has a "0" applied, output data will
be formatted for an 8-bit data bus. The 8 MSB's will become valid
when the above conditions are met with Ao= "0"; while the 8 LSB's
(4 data bits and 4 trailing "0'5") will become valid whenever Ao= "1 ".
If 12/8="1", Ao is a "don't care". If an 8-bitconversion is performed
and all 12 output data bits are read, bit 9 (OB3) will be a "1", and
bits 10-12 (OB2-OBO) will be "0'5". Data access can be initiated by
either the rising edge of CE or the falling edge of CS.
Timing for a typical application is shown below. In this application, CS is brought low, Ao is set to its final state, and RIC
is brought high all before the riSing edge of CEo CS and Ao
should be valid 50nsec prior to CE (tSSR =50nsec min,
tSAR =50nsec min). RIC can become valid the same time as CE
(tSRR =Onsec min).
Ao may be toggled at any time without damage to the converter.
Break-before-make action is guaranteed between the two data bytes,
which assures that the outputs strapped together in 8-bit bus
applications will never be enabled at the same time.
Access time is measured from the point at which CE and RIC are
both high (assuming CS is already low). Data actually becomes valid
typically 400nsec before the falling edge of Status as indicated by
tHS. In most applications, the 12/8 input will be hard-wired high or
low; although it is fully TLUCMOS compatible and may be actively
driven.
CE
tH~L
CE
~ ~_-- ~tH_S_C~~~
__
cs ~\~--
___________
t H S R -1
t SSR - -
~-+---+----"
_________.
RIC
RIC
A,
A,
STS
STS
+-__-
\
6 RefOul
12 alp 011
~
.4.nalog---Inputs ('
.. 5V
1
13 .. 10V Range
.. 15V
7
14 + 201,1 Range
.. 15V '1
9 Ana Gnd
2 12 18
unipolar operation
without trim adjustment.
D"G"d~
Status 28
3CS
MN574A
• A,
5 ~IC
R,
• CE
10 Ref In
50\1
8 ReI 01.11
12 Blp
If a 10.24V (1 LSB=2.5mV) or a 20.48V (1 LSB=5mV) input range
is required, the gain trim pot (R:z) should be replaced with a fixed
500 resistor and a 2000 trim pot (5000 for 20.48V) inserted in series
with the analog input to pin 13 (pin 14 for 20.48V). Offset trimming
proceeds as described above. Gain trimming is now accomplished
with the new pots. If one is not gain trimming and wishes to use
fixed-value resistors, the values are 1200 and 2400, respectively.
MN574A's input impedance is laser trimmed to a typical accuracy
of ±2%.
BIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the bipolar operating modes are
shown below. If the ± 5V input range is to be used, apply the analog
input to pin 13. If the ± 10V range is used, apply the analog input
to pin 14, If either bipolar offset or bipolar gain adjustments are not
to be used, the trim pots R1 and R2 should be replaced with fixed,
500 ± 1%, metal-film resistors to meet all published specifications.
·"
3CS
R.
Unipolar offset error refers to the accuracy of the 0000 0000 0000
to 0000 0000 0001 digital output transition (see Digital Output
Coding). If offset adjustment is not used, the actual transition will
occur within specified limits of its ideal value (+ 112 LSB). For the
10V range, 1 LSB=2.44mV. For the 20V range, 1 LSB=4.88mV. To
offset adjust, apply an analog input equal to + 112LSB and, with the
MN574A continuously converting, adjust the offset potentiometer
"down" until the digital output is all "O's" and then adjust "up"
until the LSB "flickers" between "0" and "1".
Unipolar gain error can be defined as the accuracy of the 1111 1111
1110 to 1111 1111 1111 digital output transition after unipolar offset
adjustment has been accomplished. Ideally, this transition should
occur W2LSB's below the nominal full scale of the selected input
range. This corresponds to +9.9963Vand + 19.9927V respectively
for the 10V and 20V unipolar input ranges. Gain trimming is accomplished by applying either of these voltages and adjusting the
gain potentiometer "up" until the digital outputs are all "1's" and
then adjusting down until the LSB "flickers" between' '1" and' '0' '.
21218
unipolar operation
with trim adjustment.
MN574A
at!
Analog
Inputs
9 AnaGnd
I
MN574A bipolar operation
with trim adjustment.
Offset
Analog
Inputs
2 12IA
bipolar operation
without trim adjustment.
3~
MN574A
4 "-
5 Ril:
R,
500
500
R,
Analog 0 - - - Inpulso---_ _ ~
Status 28
High
81ts
2'
27
• CE
Middle 20
Bils
23
10 Relln
Low
811s
8 ReIOut
,.,.
12 Blp Oft
13 :t 5\1 Range
'4 :t lOY Range
9 AnaGnd
+SV
1
+ 15V
7
-15\1 11
Dig Gnd 15
6-29
HARDWIRING TO 8-BIT DATA BUSES - For applications with 8-bit
data buses, output lines 0B4-0B11 (pins 20-27) should be connected
directly to data bus lines 0 0 -0 7 • In addition, output lines OBo-OB3
(pins 16-19) should be connected to data bus lines 0 4 -0 7 or to
MN574A output lines OB8-0B11. Thus, if Ao is low during a read
operation, the upper 8 bits are enabled and become valid on output pins 20-2Z When Ao is high during a read operation, the 4 LSB's
are enabled on output pins 16-19 and the 4 middle bits (pins 20-23)
are overridden with "O's".
0,
High Byte (Ao: 0)
Low Byte (Ao: 1)
0,
0,
D.
0,
0,
0,
200ns after RIC goes low (tos) and returns low no longer than
1000nsec after data is valid (tHS). In this mode, output data is
available "most of the time" and becomes invalid only during a
conversion.
Do
MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3 DB2 OBI DBO 0
0
0
0
MN574A
27(MS8)
0,
26(08'0)
25(089)
24 (08B)
o.
23(087)
0,
22(086)
0,
2, (085)
O.
Do
o.
20 (DB4)
'91083)
Low Pulse lor RIC-Outputs Enabled Aller Conversion
0,
-
'8(082)
(Jl
17 (DB1)
CD
The timing diagram below details operation with a positive start
pulse. Output data lines are enabled during the time RIC is high.
The falling edge of RIC starts the next conversion, and the data lines
return to three-state (and remain three-state) until the next rising
edge of RIC. In this mode, output data is inaccessible' 'most of the
time" and becomes valid only when RIC is brought high.
:::l
R/C~_
~0
'6ILS8)
'" _l'" " r'~7L ,~
Hardwiring for 8·Bit Data Buses
STAND-ALONE OPERATION
The MN574A can be used in a "stand-alone" mode in systems
having dedicated input ports and not requiring full bus interface
capability. In this mode, CE and 1218 are tied to logic "1" (they may
be hard-wired to +5V), CS and Ao are tied to logic "0" (they may
be grounded), and the conversion is controlled by RIC. A conversion is initiated whenever RIC IS brought low (assuming a conversion is not already in progress), and all 12 bits of the three-state
output buffers are enabled whenever RiC is brought high (assuming Status has already gone low indicating conversion complete).
~ f - - 1 I HDR
08 .08., ----j~vOaalt,dat)-------;:I::H:::id9",h=--_
~
mpeance
tODR
0
I
I
High Pulse lor RIC-Outputs Enabled While RIC High, Otherwise High·Z
STAND·ALONE MODE TIMING
This gives rise to two possible modes of operation; conversions can
be initiated with either positive or negative RIC pulses. The first timing diagram to the right details operation with a negative start pulse.
In this case, the outputs are forced into the high-impedance state
in response to the falling edge of RIC and return to valid logic levels
after the conversion cycle is completed. The Status Output goes high
Symbol Parameter
tHRL
tos
tHOR
tHs
tHAH
tooR
Min
Low RIC Pulse Width
STS Delay from RIC
Data Valid After RIC Low
STS Delay After Data Valid
High RIC Pulse Width
Data Access Tjme
Typ
Ma.
50
200
25
300
150
400
1000
150
Units
ns
ns
ns
ns
ns
ns
DIGITAL OUTPUT CODING
ANALOG INPUT VOLTAGE (Volts)
o to
+ 10V
+ 10.0000
+ 9.9963
+
+
+
+
5.0012
4.9988
4.9963
0.0012
0.0000
o to
+ 20V
+ 20.0000
+ 19.9927
+ 10.0024
+ 9.9976
+ 9.9927
+ 0.0024
0.0000
DIGITAL OUTPUT
±5V
± 10V
+ 5.0000
+ 4.9963
+ 0.0012
+ 10.0000
+ 9.9927
+ 0.0024
- 0.0012
- 0.0037
-
0.0024
0.0073
1000 0000 000.0'
.0~rt.0.0.0.0 rtllW'
01111111111.0'
-4.9988
- 5.0000
- 9.9976
-10.0000
0000 0000 000.0'
0000 0000 0000
MSB
LSB
111111111111
11111111111.0'
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output codirl"g is straight binary.
2. For bipolar input ranges, output coding is ollset binary.
3. For 0 to + 10V or ± 5V input ranges, lLSB for 12 bits = 2.44mV. lLSB for
11 bits:4.BBmV.
4. For 0 to + 20V or ± 10V input ranges, lLSB for 12 bits = 4.BBmV. 1LSB for 11
bits: 9.77mV.
'Voltages given are the theoretical values lor the transitions indicated. Ideal·
Iy, with the converter continuously converting, the output bits indicated as ~
will change from "1" to "0" or vice versa as the input voltage passes through
the level indicated.
6·30
EXAMPLE:IFor an MN574A operating on its ± 10V input range, the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage of - 9.9976 volts. Subsequently. any input voltage
more negative than - 9.9976 volts will give a digital output of all "O's". The
transition from digital output 1000 0000 0000 to 0111 1111 1111 will ideally oc·
cur at an input 01 -0.0024 volts, and the 111111111111 to 111111111110
transition should occur at + 9.9927 volts. An input more positive than
+ 9.9927 volts will give all ''1's''.
lWJ
_
MN674A
MICRO NETWORKS
/lP-COMPATIBLE
15/lsec, 12-Bit
AID CONVERTER
DESCRIPTION
FEATURES
• Complete, 15/Lsec, 12-Bit
AlD Converter with Internal:
Clock
Reference
Control Logic
• HI-674A and AD674A Pin
and Function Compatible
• Full 8 or 16-Bit /LP Interface:
Three-State Output Buffer
Chip Select, Address Decode
Read/Write Control
• ± V2LSB Linearity Guaranteed
-55"C to +125°C (U Model)
• No Missing Codes Guaranteed
Over Temperature
• Operation with ±12Vor
± 15V Supplies
• 28-Pin DIP, 450mW Max Power
• Full Mil Operation
-55"C to + 125"C
28-PIN CERAMIC DIP
..
PIN 1
\
0.025(064)
0.oeO(1.52)
--1 fII
-T~
MN674A is a faster version (15/Lsec max conversion time) of the
industry-standard MN574A microprocessor-interfaced, 12-bit A/D
converter. It is a complete, successive-approximation A/D with
internal buried-zener reference (+ 10V), clock, and control logic.
MN674A is packaged in a 28-pin DIP and contains all the interface logic necessary to directly mate to most popular 8 and
16-bit microprocessors. The 3-state output buffer connects
directly to the /LP'S data bus and can be read either as one 12-bit
word or as two 8-bit bytes. Chip select, chip enable, address
decode (short cycle), and read/write (read/convert) control inputs
enable MN674A to connect directly to system address bus and
control lines and operate totally under processor control.
MN674A's combination of bipolar and CMOS technologies
represents the latest advances in 574A1674A evolution, and all
problems associated with previous models from other manufacturers have been solved. These devices are truly TTL compatible over all temperature ranges, and they are not prone to
CMOS latch-up at power-on. Their internal clock has minimal
drift, and conversion time is guaranteed over all temperature
ranges. Bus access time is guaranteed not to exceed 150nsec,
and the Ao line may be toggled freely with no fear of output-data
overlap thanks to break-before-make action on the output buffer.
At 450mW max, power consumption is almost half that of competing devices.
MN674A is ideal for most military/aerospace and industrial,
general-purpose, data-acquisition applications. The device is
available in 5 different electrical grades fully specified for either
O°C to +70°C or -55°C to +125°C operation. Each device
guarantees integral linearity and no missing codes as summarized below. Add "/B" to either the S or T grade units for environmental stress screening.
1.386(35.20)
1414{3!i.92)
0.120(3.05)
0.240 (S.10)
Dimensions in Inches
(millimeters)
I
Model
MN674AJ
MN674AK
MN674AL
MN674AS
MN674AS/B'
MN674AT
MN674AT/B'
Temperature Range
O°Cto +70°C
O°C to +70°C
O°C to +70 oC
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
Linearity
Error Max
(T min to T max)
±1LSB
± '12LSB
±'hLSB
±1LSB
±1LSB
±1LSB
±1LSB
No Missing
Codes
(T min to T max)
11 Bits
12 Bits
12 Bits
11 Bits
11 Bits
12 Bits
12 Bits
'Includes environmental stress screening.
~
December 1991
Copyright., 1991
MICRO NETWORKS
324 Clark SI., Worcester. MA 01606
Micro Networks
All rights reserved
(508) 852-5400
6-31
MN674A p.P-COMPATIBLE 15p.sec 12-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN674AJ, K, L
MN674AS, SIB, T, TIB
Storage Temperature Range
Positive Supply (+Vcc, Pin 7)
Negative Supply (-Vcc, Pin 11)
Logic Supply (+Vdd, Pin 1)
Digital Inputs (Pins 2-6)
Analog Inputs: Pins 10, 12 and 13
Pin 14
Analog Ground (Pin 9)
to Digital Ground (Pin 15)
Ref. Out (Pin 8) Short Circuit Duration
ORDERING INFORMATION
II
PART NUMBER - - - - - - - - - - - MN674AXIB
DOC to +70°C
-55°C to +125°C
-65°C to +150°C
o to +16.5 Volts
oto -16.5 Volts
oto +7 Volts
-0.5 to (+Vdd + 0.5) Volts
±16.5 Volts
±24 Volts
Select suffix J, K, L, S or T for
desired performance and specified
temperature range. ______________.J.
Add "/B" suffix to SorT models
for environmental stress screening.---------..J
±1 Volt
Continuous to Ground
Momentary to ± Vcc
DESIGN SPECIFICATIONS ALL UNITS (TA=+2SOC, ±Vcc= ±12Vor ±ISV, +Vdd=+SV unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Input Impedance: 0 to +IOV, ±5V
o to +2OV, ±IOV
TYP.
o to
Input Voltage Ranges: Unipolar
Bipolar
4.7
9.4
MAX.
+10,0 to +20
±5, ±10
5
10
UNITS
Volts
Volts
5.3
10.6
kll
kll
+5.5
+0.8
Volts
Volts
+5
pA
pF
DIGITAL INPUTS CE, CS, RIC, AD, 12/8 (Note 2)
Logic Levels: Logic "1"
Logic "0"
Loading: Logic Currents
Input Capacitance
+2.0
-0.5
-5
±0.1
5
DIGITAL OUTPUTS DBO-DBll, STS (Note 2)
Output Coding (Note 3): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (lsource:5500pA)
Logic "0" (I.;nk :51.6mA)
Leakage (DBO-DBll) in High-Z State
Straight Binary
Offset Binary
+2.4
+0.4
-5
Output Capacitance
±0.1
+5
Volts
Volts
pA
pF
5
INTERNAL REFERENCE
+10.1
Volts
ppm/OC
mA
+5
±16.5
+5.5
Volts
Volts
Current Drains: +Vcc Supply
-Vcc Supply
+Vdd Supply
+3.5
-15
+9
+5
-20
+15
mA
mA
mA
Power Consumption (± Vcc= ± 15V)
325
450
mW
8
12
10
15
"sec
"sec
Reference Output (Pin 8): Voltage
Drift
Output Source Current (Note 4)
+9.9
+10.0
±10
2.0
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vec
+Vdd
±11.4
+4.5
Power Supply Rejection (See Performance Specifications)
DYNAMIC CHARACTERISTICS
Conversion Time (Notes 1, 2, 5): 8-Bit Cycle
12-Bit Cycle
6
9
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data sheet.
2. Listed specifications guaranteed over each device's full operating temperature
r~nge as determined by part number suffix.
3. See table of transition voltages in section labeled Output Coding.
4. The internal reference can be used to drive an external load, and it is capable of
supplying up to 2mA over and above the requirements of the reference·in and
bipolar-offset resistors. The external load should not vary during a conversion. The
reference output does not require a buffer when operating with ± 12V supplies.
5. If a conversion is started with Ao (pin 4) low, a full 12-bit conversion cycle is initiated.
If Ao is high, a shorter 8-bit conversion is initiated. Conversion time is defined as
the width of the Status Output pulse. See the Timing sections for more details.
6. MN674AJ, AK, AL are fully specified for OOC to +70°C operation. MN674AS, AT are
fully specified for -55°C to +125°C operation.
7. Adjustable to zero with external potentiometer.
S. Unipolar offset error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0000 0000 0000 to 0000
0000 0001 when operating the MN674A on a unipolar range. The ideal value at
which this transition should occur is + hLSB. See Digital Output Coding.
6-32
9. Listed maximum change specifications (temperature coefficients) for unipolar offset, bipolar offset and full scale calibration error correspond to the maximum change
from the initial valUe (+25OC) to the value at T min or T max.
10. Bipolar offset error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0111 1111 1111 to 1000
0000 0000 when operating the MN674A on a bipolar range. The ideal value at which
this transition should occur is -'hLSB. See Digital Output Coding.
11. Listed specs assume a fixed SOD resistor between Ref Out (pin 8) and Ref In (pin
10). Full scale calibration error is defined as the difference between the ideal and
the actual input voltage at which the digital output just changes from 111111111110
to 1111 1111 1111. Ideally, this digital output transition should occur at an analog
voltage 1'hLSB's below the nominal full scale voltage. See Digital Output Coding.
12. Listed spec is the max change in full scale calibration accuracy as supplies are
varied over the range indicated.
Specifications subject to change without notice as Micro Networks reserves the right
to make improvements and changes in its products.
=+25°C,
PERFORMANCE SPECIFICATIONS (Typical at TA
=
±Vcc" ± 12V or ± 15V, + Vdd +5V unless otherwise indicated)
674AJ
674AK
674AL
674AS
674AT
UNITS
±1
±1
± ';'
± ';'
±';'
±'h
±1
±1
±V2
±1
LSB
LSB
11
11
12
12
12
12
11
11
12
12
Bits
Bits
Unipolar Offset Error (Notes 7, 8):
Initial (+25°C) (Max)
Drift (Max)
Max Change to T min Or T max (Note 9)
±2
±10
±2
±2
±5
±1
±2
±5
±1
±2
±5
±2
±2
±2.5
±1
LSB
ppm of FSR/oC
LSB
Bipolar Offset Error (Notes 7, 10):
Initial (+25°C) (Max)
Drift (Max)
Max Change to Tmin Or T max (Note 9)
±10
±10
±2
±4
±5
±1
±4
±5
±1
±10
±10
±4
±4
±5
±2
LSB
ppm of FSR/oC
LSB
Full Scale Calibration Error (Notes 7, 11):
Initial (+25°C) (Max)
Tmin to T max Without Initial Adjustment
Tmin to T max With Initial Adjustment
Drift (Max)
Max Change to Tmin or T max (Note 9)
±0.25
±0.47
±0.22
±50
±9
±0.25
±0.37
±0.12
±27
±5
±0.25
±0.3
±0.05
±10
±2
±0.25
±0.75
±0.5
±50
±20
±0.25
±0.5
±0.25
±25
±10
%FSR
%FSR
%FSR
ppm of FSR/oC
LSB
±2
±2
±';'
±1
±1
±'h
±1
±1
±';'
±2
±2
±V2
±1
±1
±';'
LSB
LSB
LSB
MODEL
Integral Linearity Error: Initial (+25°C) (Max)
T min to T max (Max, Note 6)
Resolution for Which No Missing
Codes is Guaranteed: Initial (+25°C)
T min to T max (Note 6)
Power Supply Rejection (Note 12)
+13.5V:,;+Vcc:,; +16.5V or +11.4V:,;+Vcc:,; +12.6V
-16.5V:,;-Vcc:,; -13.5Vor -12.6V:,;-Vcc:,; -11.4V
+4.5V:,; +Vdd:,; +5.5V
ORDERING INFORMATION
Specified
Temperature
Range
Part
Number
MN674AJ
MN674AK
MN674AL
MN674AS
MN674AS/B (3)
MN674AT
MN674AT/B (3)
+25°C
Temp.
No Missing
Codes
Over Temp.
±1
±';'
±';'
±1
±1
±';'
±';'
±1
±';'
±';'
±1
±1
±1
±1
11 Bits
12 Bits
12 Bits
11 Bits
11 Bits
12 Bits
12 Bits
Integral Linearity (1)
O°C to +70°C
O°C to +70°C
OOC to +70°C
-55°C to + 125°C
-55°C to +125°C
-55°C to + 125°C
-55°C to + 125°C
Max.
Offset
Drift (2)
Max.
Full Scale
Drift (2)
Max.
Power
(mW)
±10
±5
±5
±5
±5
±2.5
±2.5
150
j 27
±10
±50
±50
±25
±25
~bO
~50
!
!
450
450
450
450
450
1. Maximum error expressed in LSB's for 12 bits.
2. Expressed in ppm of FSR/oC.
3. Includes environmental stress screening.
BLOCK DIAGRAM
+ 5V
Supply (1)
Data MOde Select 1218 (2)
(>- -- __
~------;SU~C~C:;'ES;;S~IV;E--l----~--O (28) Status Output
0--
IM
APPROXIMATION REGISTER
(27)
(26)
(25)
(24)
Byle Address Ao (4)
Read/Convert RIC (5)
OBll (MSB)
0810 (Bit 2)
DB9 (Bit 3)
eBB (BII 4)
Chtp Enable CE (6)
+ 12VI + 15V Supply (7)
+ tOV Rei Out (8)
0--0
[tOY REF
i
-------0
Analog Ground (9)
... tOV Aef In (10)
-12VI-15V Supply (11)
Bipolar Ollsel (12)
tOV Input (13)
20V Input (14)
0-----
(19) 083(811 9)
(18) OB2 (SII 10)
(17) DBt (8it 11)
(16) DBO (LSB)
0-_ _--.:;'9;;;.95;;;';::"_ _ _-1
---0
(15) Digital Ground
0--
__
o------_~--+_-_I
0-------,
O. _ _ ~5~k"_ _----<>-_~_-_ _'
CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.
6-33
I
PIN DESIGNATIONS
(1)
•
28
PIN 1
14
15
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
+ 5V Supply (+ Vddl
Data Mode Select 12/8
Chip Select CS
Byte Address Ao
Read/Convert R/C
Chip Enable CE
+ 12V/ + 15V Supply (+ Veel
+ 10V Ref Out
Analog Ground
+ 10V Ref In
- 12V /- 15V Supply ( - Veel
Bipolar Offset
10V Input
20V Input
Status Output
DB11 (MSB)
DB10 (Bit 2)
DB9 (Bit 3)
DB8 (Bit 4)
DB7 (Bit 5)
DB6 (Bit 6)
DB5 (Bit 7)
DB4 (Bit 8)
DB3 (Bit 9)
DB2 (Bit 10)
DB1 (Bit 11)
DBO (LSB)
Digital Ground
DESCRIPTION OF OPERATION
The MN674A is a complete 12-bit ND converter. It utilizes the successive approximation conversion technique and contains all
required function blocks - successive approximation register
(SAR), D/A converter, comparator, clock and reference - internal
to its package. The MN674A mates directly to most popular 8, 16 and
32-bit microprocessors and contains all the necessary address
decoding logic, control logic and 3-state output buffering to operate
completely under processor control. In most applications, the
MN674A will require only power supplies, bypass capacitors, and
two fixed resistors to provide the complete ND conversion function.
The completeness of this device makes it most convenient to think
of the MN674A as a function block with specific input/output and
transfer characteristics, and it is quite unnecessary to concern
oneself with its inner workings.
Operating the MN674A under microprocessor control (it also functions as a stand-alone ND) consists, in most applications, of a series
of read and write instructions. Initiating a conversion requires
sending a command from the processor to the ND and involves a
write operation. Retrieving digital output data is accomplished with
read operations. Once the proper signals have been received and
a conversion has begun, it cannot be stopped or restarted, and
digital output data is not available until the conversion has been completed. Immediately following the initiation of a conversion cycle, the
MN674A's Status Output (also called Busy Line or End of Conversion (E.O.G.) Line) rises to a logic "1" indicating that a conversion
is in progress. At the end of a conversion, the internal control logic
will drop the Status Output to a "0" and enable internal circuitry to
permit output data to be read by external c<;Jmmand. By sensing the
state of the Status Output or by waiting an appropriate amount of
time, the microprocessor will know when the conversion is complete
and that output data is valid and can be read.
If the MN674A is operated with 12-bit or wider microprocessors, all
12 output bits can be 3-state enabled simultaneously, permitting data
collection with a single read operation. If the MN674A is operated
with an 8-bit JtP, output data can be formatted to be read in two 8-bit
bytes. The first will contain the 8 most significant bits (MSB's). The
second will contain the remaining 4 least significant bits (LSB's),
in a left justified format, with 4 trailing "O's".
Decoupling capacitors should be used on all power supply pins; the
+5V supply decoupling capacitors should be connected directly
from pin 1 to pin 15 (Digital Ground), and the +Vec and -Vee supplies should be decoupled directly to pin 9 (Analog Ground). A
suitable decoupling capacitor pair is usually a relatively large tantalum (1-1OJtF) in parallel with asmaller(0.01-1.0JtF)ceramicdisc.
Coupling between analog inputs and digital signals should be
minimized to avoid noise pickup. Pins 10 (Reference In), 12 (Bipolar
Offset), and 13 and 14 (Analog Inputs) are particularly noise susceptible. Circuit layout should attempt to locate the MN674A and
associated analog input circuitry as far as possible from high-speed
digital circuitry. The use of wire-wrap circuit construction is not
recommended. Careful printed-circuit construction is preferred. If
external offset and gain adjust potentiometers are used, the pots
and associated series resistors should be located as close to the
MN674A as possible. If no trim adjusting is required and fixed
resistors are used, they likewise should be as close as possible.
Analog (pin 9) and Digital (pin 15) Ground pins are not connected
to each other internal to the MN674A. They must be tied together
as close to the unit as possible and both connected to system analog
ground, preferably through a large analog ground plane beneath
the package. If these commons must be run separately, a nonpolarized 0.01JtF ceramic bypass capacitor should be connected
between pins 9 and 15 as close to the unit as possible and wide
conductor runs employed. Pin 9 (Analog Ground) is the ground
reference point for the MN674A's internal reference. It should be connected as close as possible to the analog input signal reference
point.
POWER SUPPLY DECOUPLING
Pin7
Pin 1 °1:'F
r
I
T
I
T'"
Ground
I
+Vee
1"F
5V
001+F
Pin 15 0_...J._ _----'
_ _ _ Digital
r
I r
o-r-+----r+-- ~~~~~~
°
Pin 9
1"F
Pin 110
O.D1"F
T T
O.D1"F
-
-Vee
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS AND GROUNDING - Proper attention to layout and decoupling is necessary to obtain specified accuracy from the MN674A. It is critically important that the MN674A's
power supplies be filtered, well regulated, and free from highfrequency noise. Use of noisy supplies may cause unstable output
codes to be generated. Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless
great care is used in filtering any switching spikes present in the
output.
6-34
CONTROL FUNCTIONS - Operating the MN674A under
microprocessor control is most easily understood by examining the
assorted control-line functions in a truth table. Table 1 below is a
summary of MN674A control-line functions. Table 2 is the MN674A
Truth Table.
Unless Chip Enable (CE, pin 6, logic "1" = active) and Chip Select
(CS, pin 3, logic "0" =active) are both asserted, various combinations of logic signals applied to other control lines (RIC, 12/8 and
Ao) will have no effect on MN674A operation. When CE and CS are
Table 1: MN674A Control Line Functions
Pin
Designation
Definition
Function
CE (Pin 6)
Chip Enable
(active high)
Must be high ("I ") to
either initiate a conversion or read output data.
0-1 edge may be used
to initiate a conversion.
CS (Pin 3)
Chip Select
(active low)
Must be low ("0") to
either initiate a conversion or read output data.
1 - 0 edge may be used
to initiate a conversion
R/C (Pin 5)
Ao (Pin 4)
12/8 (Pin 2)
Read/Convert
("1"= read)
("0" = convert)
Byte Address
Short Cycle
Data Mode
Select
("1" = 12 bits)
("0" = 8 bits)
(Note 5)
Must be low ("0") to
initiate either 8 or 12-bit
conversions. 1- 0 edge
may be used to initiate a
conversion. Must be high
("1 ") to read output data.
0-1 edge may be used
to initiate a read
operation
In the start-convert
mode, Ao selects 8-bit
(Ao = "1") or 12-bit
(Ao = "0") conversion
mode. When reading output data in 2 8-bit bytes,
Ao = "0" accesses 8
MSB's (high byte) and
Ao = "1" accesses 4
LSB's and trailing "O's"
(low byte).
When re~ding output
data, 12/8 = "1" enables
all 12 output bits simultaneously. 12/8 = "0" will
enable the MSB's or
LSB's as determined by
the Ao line.
plications, the 4 LSB's (pins 16-19) should be hardwired to the 4
MSB's (pins 24-27). Thus, during a read, when Ao is low, the upper
8 bits are enabled and present data on pins 20 through 27. When
Ao goes high, the upper 8 data bits are disabled. The 4 LSB's then
effectively present data to pins 24 to 27, and the 4 middle bits are
overridden so that zeros are presented to pins 20 through 23. See
the section labeled Hardwirlng to 8-Bit Data Buses.
Table 2: MN674A Truth Table
CONTROL INPUTS
CE
CS
RIC
12/8
MN674A OPERATION
A.
a
x
x
x
X
X
1
X
X
X
No Operation
1
1-0
X
a
Initiates 12-Bit Conversion
Initiates 8-Bit Conversion
0-1
a
a
a
a
1
1-0
1
No Operation
1-0
X
1
X
a
Initiates 12-Bit Conversion
X
1
Initiates 8-Bit Conversion
X
a
Initiates 12-Bit Conversion
1-0
a
a
a
a
X
1
Initiates 8-Bit Conversion
1
a
1
1
X
Enables 12-Bil Parallel
Output
1
a
a
1
a
a
a
Enables 8 MSB's
1
Enables 4 LSB's and
4 Trailing Zeros
1
0-1
1
1
TABLE 1, TABLE 2 NOTES:
1. "I" indicates TTL logic high (+2.OV minimum).
2. "0" indicates TTL logic zero (+O.BV maximum).
3. X indicates "don't care".
4.0-1,1-0 indicate logic transitions (edges).
5. Some vendors 674's required the 12t8line to be hard wired to either +5V
(pin 1) or OV (pin 15). The MN674A may be hard wired as such or driven with
normal TTL signals.
6. Output data format is as follows:
MSB
xxxx
xxxx
xxxx
High
Bits
Middle
Bits
Low
Bits
a MSB's
LSB
4 LSB's
both asserted, the signal applied to RIC (Read/Convert, pin 5) determines whether a data read (RiC="I") or a convert operation
(R/C="O") is initiated.
When initiating a conversion, the signal applied to Ao (Byte Address/Short Cycle, pin 4) determines whether a 12-bit conversion
is initiated (Ao="O") or an S-bit conversion is initiated (Ao="I"). It
is the combination of CE="I", CS="O", R/C="O" and Ao="I" or
"0" that initiates a convert operation. The actual conversion can
be initiated by the rising edge of CE, the falling edge of CS or the
falling edge of RIC as shown in the Truth Table and as described
in the section labeled Timing ~ Initiating Conversions_ When
initiating conversions, the 1218 line is a "don't care".
When reading digital output data from the MN674A, CE and CS must
be asserted, and the signals applied to 12/8 and Ao will determine
the format of output data. Logic "I" applied to the RlCline will initiate
actual output data access. lithe 12/81ine is a "1", all 12 output data
bits will be accessed simultaneously when the RiC line goes from
a "0" toa "1".
If the 12/8 line is a "0", output data will be accessible as two S-bit
bytes as detailed in the section labeled Timing - Reading Output
Data. In this situation, Ao= "0" will result in the S MSB's being accessed, and Ao= "1" will result in the 4 LSB's and 4 trailing zeros
being accessed. In this mode, only the S upper bits or the 4 lower
bits can be enabled at one time, as addressed by Ao. For these ap-
TIMING - INITIATING CONVERSIONS - It is the combination
of CE="1", CS="O", R/C="O" and Ao="1" (initiate S-bit
conversion) or Ao= "0" (initiate 12-bit conversion) that initiates a
convert operation. As stated earlier, the actual conversion can be
initiated by the rising edge of CE, the falling edge of CS or the failing edge of RIC. Whichever occurs last will control the conversion;
however, all three may change simultaneously. The nominal delay
time from either input transition to the beginning of the conversion
(rising edge of Status) is the same for all three inputs (60nsec). If
it is desired that a particular one of these three inputs be responsible for starting the conversion, the other two should be stable a
minimum of 50nsec prior to the transition of that input.
Because the MN674A's control logic latches the Ao signal upon conversion initiation, the Ao line should be stable immediately prior to
whichever olthe above transitions is used to initiate the conversion.
The RIC transition is normally used to initiate conversions in standalone operation; however, it is not recommended to use this line to
initiate conversions in f.lP applications. If RIC is high just prior to a
conversion, there will be a momentary enabling of output data as
if a read operation were occurring, and the result could be system
6-35
I
,_
bus contention. In most applications, Ao should be stable and RIC
low before either CE or CS is used to initiate a conversion.
Timing for a typical application is shown below. In this application,
CS is brought low, RIC'is brought low, and Ao is set to its chosen
value prior to CE becoming a "1". This sequence can be accomplished in a number of ways including connecting CS and Ao
to address bus lines, connecting RIC to a readlwrite line (or its
equivalent) and generating a CE 0-1 transition using the system
clock. In this example, CS should be a "0" 50nsec prior to the CE
transition (tssc=50nsec min), RIC should be a "0" 50nsec prior
to the CE transition (tSRC =50nsec min), and Ao should be stable
Onsec prior to the CE transition (tSAC =Onsec min). The minimum
pulse width for CE = "1" is 50nsec (tHEC =50nsec min) and both CS
and RIC must be valid for at least 50nsec while CE="1" (tHSC and
tHRC =50nsec min) to effectively initiate the conversion. Similarly,
Ao must be valid for at least 50nsec (tHAC =50nsec min) while CE
is high to effectively initiate the conversion. The Status Line rises
to a "1" no later than 200nsec after the rising edge of CE
(tDSC =200nsec max). Once Status = "1", additional convert commands will be ignored until ongoing conversion is complete.
TIMING - RETRIEVING DATA - When a conversion is in progress
(Status Output="1"), the MN674A's 3-state output buffer is in its
high-impedance state. After the falling edge of Status indicates that
the conversion is done, the combination of CE= "1", CS= "0", and
R/C="1" is used to activate the buffer and read the digital output
data.lfthe above combination of control signals is met and the 12/8
line has a "1" applied, all twelve output bits will become valid
simultaneously. If the 12/8 line has a "0" applied, output data will
be formatted for an 8-bit data bus. The 8 MS8 's will become valid
when the above conditions are met with Ao= "0"; while the 8 LSB's
(4 data bits and 4 trailing "O's") will become valid whenever Ao = "1".
If 1218="1", Ao is a "don't care". If an 8-bit conversion is performed
and all 12 output data bits are read, bit 9 (083) will be a "1", and
bits 10-12 (082-080) will be "O's". Data access can be initiated by
either the rising edge of CE or the falling edge of CS.
Timing for a typical application is shown below. In this application, CS is brought low, Ao is set to its final state, and RIC
is brought high all before the rising edge of CE. CS and Ao
should be valid 50nsec prior to CE (tSSR =50nsec min,
tSAR =50nsec min). RIC can become valid the same time as CE
(tSRR =Onsec min).
Ao may be toggled at any time without damage to the converter.
Break-before-make action is guaranteed between the two data bytes,
which assures that the outputs strapped together in 8-bit bus
applications will never be enabled at the same time.
Access time is measured from the point at which CE and RIC are
both high (assuming CS is already low). Data actually becomes valid
typically 300nsec before the falling edge of Status as indicated by
tHS. In most applications, the 12/8 input will be hard-wired high or
low; although it is fully TLUCMOS compatible and may be actively
driven.
CE
;---
CE
tSSR
RIC
IHRR
tSAR
' - -_ __
RIC
A,
A,
STS
STS
DBo- DBI1 _--:-::.:.H:.:Jigc-:h_ _+-_-{I-~D~al~a---l
Impedance
Valid
+ __________
DBa-DB" _--:-..:.H::"ig!:.:h_ _
Impedance
100
Rood
Convert Start Timing
MN674A TIMING SPECIFICATIONS:
CONVERT MODE
Symbol Parameter
STS Delay from CE
tosc
CE Pulse Width
tHEC
CS to CE Setup
tssc
~ Low During CE High
tHSC
RIC to CE Setup
tSRC
RIC Low During CE High
tHRC
A. to CE Setup
tSAC
A. Valid During CE High
tHAC
Conversion Time (Over Temp.)
tc
8·Bit Cycle
12·Bit Cycle
6-36
Min
50
50
50
50
50
0
50
6
9
Typ
60
30
20
20
0
20
Max
200
20
8
12
10
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
"s
"s
Cycle Timing
MN674A TIMING SPECIFICATIONS:
READ MODE
Symbol Parameter
Access Time (from CEl
too
Data Valid after CE Low
tHO
Output Float Delay
tHL
CS to CE Setup
tSSR
RIC to CE Setup
tSAR
A. to CE Setup
tSAR
CS Valid After CE Low
tHSR
RIC High After CE Low
tHRR
A. Valid After CE Low
tHAR
STS Delay After Data Valid
tHS
Min
25
50
0
50
0
0
50
100
Typ
75
35
100
0
Max
150
150
25
300
600
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the unipolar operating modes
are shown below. If the 0 to +10V input range is to be used, apply
the analog inputto pin 13.lftheOto +20Vrange is used, apply the
analog input to pin 14. If gain adjustment is not used, replace trim
pot R2 with a fixed, 500 ± 1%, metal-film resistor to meet all published
specifications. If unipolar offset adjustment is not used, connect pin
12 (Bipolar Offset) directly to pin 9 (Analog Ground).
3CS
If a 10.24V (1 LSB=2.5mV) or a 20.48V (1 LSB=5mV) input range
is required, the gain trim pot (R 2) should be replaced with a fixed
son resistor and a 200n trim pot (5000 for 20.48V) inserted in series
with the analog input to pin 13 (pin 14 for 20.48V). Offset trimming
proceeds as described above. Gain trimming is now accomplished
with the new pots. If one is not gain trimming and wishes to use fixedvalue resistors, the values are 1200 and 2400, respectively.
MN674A's input impedance is laser trimmed to a typical accuracy
of ±2%.
High
Bits
• A,
R,
lDOk
5 RIC
24
27
Middle 20
Bits
23
6 CE
Low
10 Ret In
B.ls
S RelOut
Unipolar offset error refers to the accuracy of the 0000 0000 0000
to 0000 0000 0001 digital output transition (see Digital Output
Coding). If offset adjustment is not used, the actual transition will
occur within ± 2 LSB's of its ideal value (+ 112 LSB). For the 10V
range, 1 LSB=2.44mV. For the 20V range, 1 LSB=4.88mV. To offset adjust, apply an analog input equal to + '/2 LSB and, with the
MN674A continuously converting, adjust the offset potentiometer
"down" until the digital output is all "O's" and then adjust "up" until the LSB "flickers" between "0" and "1".
Unipolar gain error can be defined as the accuracy of the 11111111
1110 to 1111 1111 1111 digital output transition after unipolar offset
adjustment has been accomplished. Ideally, this transition should
occur 1112 LSB's below the nominal full scale of the selected input
range. This corresponds to +9.9963Vand + 19.9927V respectively
for the 10V and 20V unipolar input ranges. Gain trimming is accomplished by applying either of these voltages and adjusting the
gain potentiometer "up" until the digital outputs are all "1's" and
then adjusting down until the LSB "flickers" between "1" and "0".
Status 28
2 1218
MN674A unipolar operation
with trim adjustment.
I.
16
12 Blp Of!
13 + tOV Range
'4 ... lOY Range
9 AnaGnd
2 1218
MN674A unipolar operation
JCS
without trim adjustment.
• A,
+ 5V
1
+ 15V
7
~
15V 11
O,gGnd 15
Status 28
High
Blls
2'
27
5 RIC
Middle 20
6 CE
B.ts
R,
Low
B.ls
10 Relln
e Ref Out
23
16
I.
12 Sip Off
13
Analog
Inputs
+ tOV
Range
14 + 20V Range
9 Ana Gnd
+5V
1
-+- 15V
7
- 1SV 11
Q'gGnd 15
I
21.11
...
3CS
BIPOLAR OPERATION AND CALIBRATION - Analog input connections and calibration circuits for the bipolar operating modes are
shown below. If the ± 5V input range is to be used, apply the analog
input to pin 13. If the ± 10V range is used, apply the analog input
to pin 14. If either bipolar offset or bipolar gain adjustments are not
to be used, the trim pots R, and R2 should be replaced with fixed,
50n ± 1%, metal-film resistors to meet all published specifications.
Bipolar offset error refers totheaccuracyofthe011111111111 to 1000
00000000 digital output transition (see Digital Output Coding). Ideally, this transition should occur '/2 LSB below zero volts, and if bipolar
offset adjustment is not used, the actual transition will occur within
the specified limit of its ideal value. Offset adjusting on the bipolar
device is performed not at the zero crossing pOint but at the minus
full scale point. The procedure is to apply an analog input equal to
-FS+1I2 LSB (-4.9988V lor the ±5V range, -9.9976Vforthe ±1OV
range) and adjustthe bipolar offset trim pot "down" until the digital
output is all "O's". Then adjust "up" until the LSB "flickers" between
"0" and "1".
Bipolar gain error can be defined as the accuracy of the 1111 1111
1110to 111111111111 digital output transition after bipolar offset adjustment has been accomplished. Ideally, this transition should occur 1112 LSB's below the nominal positive full scale value of the
selected input range. This corresponds to +4.9963V and +9.9927V
respectively for the ± 5V and ± 10V bipolar input ranges. Gain trimming is accomplished by applying either of these voltages and adjusting the gain trim pot "up" until the digital outputs are all "1's"
and then adjusting "down" until the LSB "flickers" between "1" and
"0".
MN674A bipolar operation
with trim adjustment.
S RIC
Low
Bits
Offset
Adjust
R
t
Analog
Inpuls
2 124
Stalul 28
3~
High
2'
Bits
27
...
MN674A bipolar operation
without trim adjustment. 500
resistors should be ± 1%
metal film.
5 R,e
6 CE
R,
10 Ref In
50!!
50!!
e
0-------
Low
Bits
RefOul
I.
16
12 Sip Off
R,
Analog
Inputs
Middle 20
Bils
23
+5V
1
13 :t 5V Range
-+- lSV
7
14
- 1SV 11
:t
10V Range
9 AnaGnd
OigGnd 15
6-37
HARDWIRING TO 8-BIT DATA BUSES - For applications with 8-bit
data buses, output lines 0B4-0B11 (pins 20-27) should be connected
directly to data bus lines 0 0 -0 7 . In addition, output lines OBO-OB3
(pins 16-19) should be connected to data bus lines 0 4 -0 7 or to
MN674A output lines OB8-0B11. Thus, if Ao is low during a read
operation, the upper 8 bits are enabled and become valid on output pins 20-27. When Ao is high during a read operation, the 4 LSB's
are enabled on output pins 16-19 and the 4 middle bits (pins 20-23)
are overridden with "O's".
High Byte (Ao = 0)
Low Byte (Ao= 1)
200ns after RIC goes low (tDS) and returns low no longer than
1000nsec after data is valid (tHS). In this mode, output data is
available "most of the time" and becomes invalid only during a
conversion.
0,
D.
0,
D.
0,
0,
0,
Do
MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3 DB2 DBl DBa 0
a
a
0
MN674A
27 (M8B)
26 (DB10)
25(DB9)
24 (DBB)
23 (OB7)
22 (OB6)
21 (OB5)
20 (OB4)
19 (DB3) r--1B (OB2)
17 (OB1)
16 (LSB)
0,
0,
0,
Low Pulse lor RIC-Outputs Enabled Alter Conversion
D.
0,
The timing diagram below details operation with a positive start
pulse. Output data lines are enabled during the time RIC is high.
The falling edge of RIC starts the next conversion, and the data lines
return to three-state (and remain three-state) until the next rising
edge of RIC. In this mode, output data is inaccessible "most of the
time" and becomes valid only when RiC is brought high.
0,
0,
0,
(/)
::::J
al
RIC~.~
«~
0
Hardwiring lor 8·Bit Data Buses
STAND·ALONE OPERATION
STS
The MN674A can be used in a "stand-alone" mode in systems
having dedicated input ports and not requiring full bus interface
capability. In this mode, CE and 12/8 are tied to logic "1" (they may
be hard-wired to +5V), CS and Ao are tied to logic "0" (they may
be grounded), and the conversion is controlled by RiC. A conversion is initiated whenever RIC is brought low (assuming a conversion is not already in progress), and all 12 bits of the three-state
output buffers are enabled whenever RiC is brought high (assuming Status has already gone low indicating conversion complete).
This gives rise to two possible modes of operation; conversions can
be initiated with either positive or negative RIC pulses. The timing
diagram below details operation with a negative start pulse. In this
case, the outputs are forced into the high-impedance state in
response to the falling edge of RIC and return to valid logic levels
after the conversion cycle is completed. The Status Output goes high
l"""I'""b~tHDR
--<~>----""
...-.,......:H"'i9"'h'--~
Impedance
tDDRH
DB,· DB" _ _ _
I
I
High Pulse lor RIC-Outputs Enabled While RIC High, Otherwise High·Z
STAND·ALONE MODE TIMING
Symbol Parameter
Low RIC Pulse Width
tHRL
tDS
STS Delay from RIC
Data Valid After RIC Low
tHOR
tHS
STS Delay After Data Valid
High RIC Pulse Width
tHRH
Data Access Time
tDDR
Min
Typ
Max
50
200
25
300
150
400
1000
150
Units
ns
ns
ns
ns
ns
ns
DIGITAL OUTPUT CODING
010 +10V
+ 10.0000
+ 9.9963
+ 5.0012
+ 4.9988
+ 4.9963
+ 0.0012
0.0000
ANALOG INPUT VOLTAGE (Volts)
±5V
010 + 20V
± 10V
+ 20.0000
+ 19.9927
+ 10.0024
+ 9.9976
+ 9.9927
+ 5.0000
+4.9963
+ 0.0012
- 0.0012
- 0.0037
+
+
+
-
10.0000
9.9927
0.0024
0.0024
0.0073
+ 0.0024
0.0000
- 4.9988
- 5.0000
- 9.9976
- 10.0000
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges. output codin'g is straight binary.
2. For bipolar input ranges, output coding is offset binary.
3. For 0 to + 10V or :t 5V input ranges, 1LSa for 12 bits; 2.44mV. 1LSB for
11 bits; 4.BBmV.
4. For 0 to + 20Vor :t 10V input ranges, 1LSB for 12 bits; 4.BBmV. 1LSB for 11
bits; 9.77mV.
'Voltages given are the theoretical values for the transitions indicated. Ideal·
Iy, with the converter continuously converting, the output bits indicated as ~
will change from "1" to "0" or vice versa as the input voltage passes through
the level indicated.
6-38
DIGITAL OUTPUT
MSB
LSB
111111111111
11111111111.0'
1000 0000 000.0'
.0rtrtrt.0rtrtfH/rtrt.0'
0111 1111 111.0'
0000 0000 000.0'
0000 0000 0000
EXAMPLE: For an MN674A operating on its :t tOV input range, the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage 01 - 9.9976 volts. Subsequently, any input voltage
more negative than - 9.9976 volts will give a digital output 01 all "O's". The
transition from digital output 10000000 0000 to 01111111 1111 will ideally oc·
cur at an input 01 -0.0024 volts, and the 111111111111 to 111111111110
transition should occur at + 9.9927 volts. An input more positive than
+ 9.9927 volts will give all ''1's''.
MN774
~ MICRO NETWORKS
p.P-COMPATIBLE
8J.tsec, 12-Bit
AID CONVERTER
DESCRIPTION
FEATURES
• Complete, 8JLSec, 12-Bit
AID Converter with Internal:
Clock
Reference
Control Logic
• HI-774A Pin and
Function Compatible:
Faster (9JLSec over Temp.)
Lower Power (450mW max)
• Full 8 or 16-Bit liP Interface:
Three-State Output Buffer
Chip Select, Address Decode
Read/Write Control
• ± 1fzLSB Linearity Guaranteed
-55"C to +125"C (U Model)
• 100kHz Sampling Rate
with MN376 T/H Amplifier
• Operation with ± 12V or
± 15V Supplies
• 28-Pin DIP
• Full Mil Operation
-55"C to +125"C
28-PIN CERAMIC DIP
The MN774 is the fastest device (8p.sec) in Micro Networks
MN574A1674A1774 Family of p.P-interfaced, 12-bit ADC's. Like
other devices in the Family, MN774 is a complete AID with
internal buried-zener reference (+ 10V), clock, and control logic.
It is packaged in a 28-pin DIP that contains all the interface logic
necessary to directly mate to most 8 and 16-bit IlP's. Chip select,
chip enable, address decode and read/write control inputs
enable MN774 to connect directly to system address bus and
control lines. The 3-state output buffer connects directly to the
JLP'S data bus and can be read either as one 12-bit word or as
two 8-bit bytes.
MN774 combines monolithic bipolar technology for its precision
analog functions with CMOS technology for its high-speed logic
functions. Its clock-oscillator circuit benefits from a currentcontrolled architecture that not only enables us to make a faster
device but one whose conversion time is guaranteed over
temperature (8.5JLsec max O°C to +70°C; 9JLsec max -55°C to
+ 125°C). Not only is the MN774 faster than competing devices,
it consumes significantly less power (450mW max).
MN774 may be combined with a fast T/H such as MN376
(200nsec max acquisition time) to configure an impreSSive, fully
JLP controlled, sampling AID capable of accurately digitizing
full-scale signals at rates up to 100kHz. Such a configuration
typically achieves signal-to-noise ratios (SNR's) of 72dB with
harmonics down more than -80dB while digitizing signals with
full-power bandwidths up to 500kHz.
MN774 is idea! for most military/aerospace and industrial, highspeed, data-acquisition applications. The device is available in 5
different electrical grades that guarantee integral linearity and
no miSSing codes as summarized below.
0.108(2.14)
0.166(4.22)
Model
MN774J
MN774K
MN774L
MN774S
MN774S/B'
MN774T
MN774T/B'
0.120(3.05)
0.240(6.10)
Dimensions in Inches
(millimeters)
Temperature Range
O°C to +70°C
OOCto +70°C
O°C to +70°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
Linearity
Error Max
(Tmin to Tmax)
±ILSB
±'hLSB
±'hLSB
±ILSB
±ILSB
±ILSB
±ILSB
No Missing
Codes
(T min to Tmax)
11 Bits
12 Bits
12 Bits
11 Bits
11 Bits
12 Bits
12 Bits
'Includes environmental stress screening.
~ MICRO NETWORKS
324 Clark St.. Worcester. MA 01606
December 1991
Copyright, 1991
Micro Networks
All rights reserved
(508) 852·5400
6-39
I
MN774 p.P-COMPATIBLE, ap'sec, 12-Bit AID CONVERTERS
ORDERING INFORMATION
AB$OWTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN774J, K, L
MN774S, SIB, T, TIB
Storage Temperature Range
Positive Supply (+Vcc, Pin 7)
Negative Supply (-Vcc, Pin 11)
Logic Supply (+Vdd, Pin 1)
Digital Inputs (Pins 2-6)
Analog Inputs: Pins 10, 12 and 13
Pin 14
Analog Ground (Pin 9)
to Digital Ground (Pin 15)
Ref. Out (Pin 8) Short Circuit Duration
-55°C to + 125°C
O°Cto +70°C
-55°C to + 125°C
-65°C to +150°C
o to + 16.5 Volts
o to -16.5 Volts
to +7 Volts
-0.5 to (+Vdd + 0.5) Volts
±16.5 Volts
±24 Volts
II
PART NUMBER - - - - - - - - - - - MN774X/B
Select suffix J, K, L, S or T for
desired performance and specified
temperature r a n g e . - - - - - - - - - - - - - - ' Add "/B" suffix to S or T models
for environmental stress screening. - - - - - - - - - - - '
o
±1 Volt
Continuous to Ground
Momentary to ± Vcc
DESIGN SPECIFICATIONS ALL UNITS (TA = +25OC, ±Vcc= ± 12V or ± 15V, +Vdd= +5V unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Input Impedance: 0 to +10V, ±5V
to +20V, ± 10V
o
TYP.
oto
Input Voltage Ranges: Unipolar
Bipolar
4.7
9.4
MAX.
+10,0 to +20
±5, ±10
5
10
UNITS
Volts
Volts
5.3
10.6
kll
kll
+5.5
+0.8
Volts
Volts
+5
"A
pF
DIGITAL INPUTS CE, CS, RIC, Ao, 12/8 (Note 2)
Logic Levels: Logic "1"
Logic "0"
Loading: Logic Currents
Input Capacitance
+2.0
-0.5
-5
±0.1
5
DIGITAL OUTPUTS DBO·DBll, STS (Note 2)
Output Coding (Note 3): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1" (lsources500"A)
Logic "0" (Isink S 1.6mA)
Leakage (080-0Bl1) in High-Z State
Straight Binary
Offset Binary
+2.4
+0.4
-5
±0.1
Volts
Volts
+5
"A
pF
+10.1
Volts
ppm/oC
mA
+5
±16.5
+5.5
Volts
Volts
Current Drains: +Vcc Supply
-Vcc Supply
+Vdd Supply
+3.5
-15
+9
+5
-20
+15
mA
mA
mA
Power Consumption (± Vec= ± 15V)
325
450
mW
5
5.3
pSec
,.sec
pSec
7.5
5.7
6
8
8.5
9
Output Capacitance
5
INTERNAL REFERENCE
Reference Output (Pin 8): Voltage
Drift
Output Source Current (Note 4)
+9.9
+10.0
±10
2.0
POWER SUPPLY REQUIREMENTS
Power Supply Range: ±Vcc
+Vdd
±11.4
+4.5
Power Supply Rejection (See Performance Specifications)
PYNAMIC CHARACTERISTICS
Conversion Time (Notes 1, 5): 8-Bit Cycle: +25°C
O°Cto +70OC
-55OC to + 125°C
12·Bit Cycle: +25°C
O°Cto +70°C
-55OC to + 125°C
"sec
,.sec
"sec
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data sheet.
2. Listed specifications guaranteed over each device's full operating 'temperature
range as determined by part number suffix.
3. See table of transition voltages in section labeled Output Coding.
4. The internal reference can be used to drive an external load, and it is capable of
supplying up to 2mA over and above the requirements of the reference-in and
bipolar-offset resistors. The external load should not vary during a conversion. The
reference output does not require a buffer when operating with ± 12V supplies.
5. If a conversion is started with Ao (pin 4) low, a full 12-bit conversion cycle is initiated.
If Ao is high, a shorter S-bit conversion is initiated. Conversion time is defined as
the width of the S~atus Output pulse. See the Timing sections for more details.
6-40
6. MN774J, K, L are fully specified for OOC to + 70°C operation. MN774S, T are fully
specified for -55OC to + 1250C operation.
7. Adjustable to zero with external potentiometer.
S. Unipolar offset error is defined as the difference between the ideal and the actual
input vollage at which the digital output just changes from 0000 0000 0000 to 0000
0000 0001 when operating the MN774 on a unipolar range. The ideal value at which
this transition should occur is + 'hLSB. See Digital Output Coding.
9. Listed maximum change specifications (temperature coefficients) for unipolar offset, bipolar offset and full scale calibration error correspond to the maximum change
from the initial value (+25OC) to the value at Tm;, or T ma>
In
RIC~,~
~
Cl
Hardwiring for 8·Bit Data Buses
l'"""1'' /L ,J-
STAND-ALONE OPERATION
The MN774 can be used in a "stand-alone" mode in systems having
dedicated input ports and not requiring full bus interface capability. In this mode, CE and 1218 are tied to logic "1" (they may be hardwired to +5V), CS and Ao are tied to logic "0" (they may be grounded), and the conversion is controlled by RIC. A conversion is initiated
whenever RlCis brought low (assuming a conversion is not already
in progress), and all 12 bits of the three-state output buffers are enabled whenever RIC is brought high (assuming Status has already
gone low indicating conversion complete).
m _
tDDRH
~tHDR
OB,.OB" _ _ _,""",~f-_ _~~=,H=j9",h=__
~
I
Impedance
I
High Pulse lor RiC-Outputs Enabled While RIC High, Otherwise Hlgh·Z
STAND·ALONE MODE TIMING
This gives rise to two possible modes of operation; conversions can
be initiated with either positive or negative RIC pulses. The timing
diagram below details operation with a negative start pulse. In this
case, the outputs are forced into the high-impedance state in
response to the falling edge of RIC and return to valid logic levels
after the conversion cycle is completed. The Status Output goes high
Symbol Parameter
tHRL
tos
tHOR
tHS
tHRH
tOOR
Min
Low RIC Pulse Width
STS Delay lrom RIC
Data Valid After RIC Low
STS Delay After Data Valid
High RIC Pulse Width
Data Access Time
Typ
Max
50
200
25
150
375
150
150
Units
ns
ns
ns
ns
ns
ns
DIGITAL OUTPUT CODING
ANALOG INPUT VOLTAGE (Volts)
o to
+ 10V
o to
+ 20V
DIGITAL OUTPUT
±5V
±10V
MSB
LSB
+ 10.0000
+ 9.9963
+ 20.0000
+ 19.9927
+ 5.0000
+ 4.9963
+ 10.0000
+ 9.9927
+
+
+
5.0012
4.9988
4.9963
+ 10.0024
+ 9.9976
+ 9.9927
+ 0.0012
- 0.0012
-0.0037
+ 0.0024
- 0.0024
- 0.0073
RJRJ[Ig RJRJr;Jr;J fiJfiJrtRJ"
0111 1111111RJ"
+
0.0012
0.0000
+
-4.9988
-5.0000
- 9.9976
- 10.0000
0000 0000 000lJ"
0000 0000 0000
0.0024
0.0000
111111111111
11111111111R)"
10000000 OOOR)"
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is straight binary.
2. For bipolar input ranges, output coding is ollset binary.
3. For a to + 10V or ± 5V input ranges, 1LSB lor 12 bits = 2.44mV. 1LSB lor
11 bits=4.88mV.
4. Fora to + 20V or ±10Vinputranges,1LSBlor12bits=4.88mV.1LSBfor11
bits = 9.77mV.
·Voltages given are the theoretical values lor the transitions indicated. Ideal·
ly. with the converter continuously converting, the output bits indicated as fI
will change from "1" to "0" or vice versa as the Input voltage passes through
the level indicated.
6·46
EXAMPLE: For an MN774 operating on its ± 10V Input range, the transition
Irom digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage 01 - 9.9976 volts. Subsequently, any input voltage
more negative than - 9.9976 volts will give a digital output 01 all "a's". The
transition Irom digital output 1000 0000 0000 to 011111111111 will ideally oc·
cur at an input 01 -0.0024 volts, and the 1111 11111111 to 1111 1111 1110
transition should occur at + 9.9927 volts. An input more positive than
+9.9927 volts will give all "1's".
,
_
MN5065
MN5066
I'
LOW-POWER, 8-Bit
AJD CONVERTERS
MICRO NETWORKS
DESCRIPTION
FEATURES
MN5065 and MN5066 are extremely low-power, 8-bit, successive approximation analog-to-digital converters that
may be operated from a single + 12 Volt power supply.
These converters are designed with CMOS logic and have
power consumptions less than 84mW maximum. The
MN5065 has a ±5V input range; the MN5066 has a 0 to
+ 10V input range. Both devices are housed in small,
convenient, 18-pin dual-in-line packages.
These AID's are complete with internal reference and are
actively laser trimmed as complete units eliminating the
need for external adjusting potentiometers. Performance
features include the following: ± % LSB linearity and "no
missing codes" guaranteed over the entire operating
temperature range, 100J.tsec conversion time, and ±2 LSB
maximum absolute accuracy error over the entire operating
temperature range.
MN5065 and MN5066 may be procured for operation over
either the O°C to +70°C or the -55°C to + 125°C ("H" models)
temperature range. For military/aerospace or harsh-environment
commercial/industrial applications, MN5065H/B and
MN5066H/B are available with optional Environmental Stress
Screening.
• Low Power
84mW Maximum
• Single +12V Supply
• Small 18-Pin DIP
• CMOS/TIL Compatible
• Adjustment-Free
No Gain and Offset
Adjustment Necessary
• Full Mil Operation
- 55°C to + 125°C
18 PIN DIP
.Q.Q.~-'tO.087!2.220)
P~NC' ,TI':~i~L
I
MN5065 and MN5066 are excellent choices for remote
battery-operated instrumentation, for. portable test equipment, and for oceanographic and seismologic monitoring
equipment. In these applications, adjustment-free operation and maximum specifications guaranteed over
temperature assure field interchangeability without
recalibration.
1.012(2570)
~
j
0.770(19.56)
0610(20.57)
_1.
I
--1 . ----- U =rgg~lg.~~l
1
lr-------.j----I-
0200 (5.080!
0.230(5842)
r
+·g:g~lg:~: I tg·~1Z!~·~l
1.--0600 (1524)
j
Dimensions in Inches
(millimeters)
[1:JJ
_
May 1988
MICRO NETWORKS
324 Clark Sl., Worcester, MA 01606 (508) 852-5400
647
MN5065 MN5066 LOW·POWER 8·Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Storage Temperature
Power Supplies (Pins 15, 18)
Analog Inputs (Pin 9)
Digital Inputs (Pins 12, 17)
O'C to +70°C
-55'C to +125'C ("H" Models)
-65' C to +150° C
-0.5 to +16 Volts
±15 Volts
-0.5 to + Logic Supply
ORDERING INFORMATION
PART NUMBER - - - - - - - - - M N 5 0 6 5 H / B
Seillct MN5065 or MN5066 Model.
I
Standard part is specified for O°C to + 70°C
operation.
Add "H" suffix for specified -55°C to + 125'C
operation.-------------_...J
Add "/B" to "H" devices for
Environmental Stress Screening. _ _ _ _ _ _ _-.1
SPECIFICATIONS (TA = +25'C Vdd = Vcc = 12V unless olherwlse specified)
ANALOG INPUTS
+Vdd
MIN.
TYP.
MAX.
-5 to +5
Oto+l0
Input Voltage Range: MN5065
MN5066
Input Impedance
UNITS
Volts
Volts
50
Kn
DIGITAL INPUTS
Logic Levels (Note 1): Logic "1"
Logic "0"
+ 5V
+12V
+ 5V
+12V
3.5
8.4
1.5
3.5
Start Convert Input: Pulse Width
Setup Time Start High to Clock
Clock Input: Frequency (Note 2)
Positive Pulse Width (Note 3)
Rise and Fall Times (Note 3)
pA
pF
10
5
Loading: Input Current
Input Capacitance (Vin=OV)
+ 5V
+12V
+ 5V
+12V
750
250
300
150
+ 5V
+12V
+ 5V
+12V
600
300
Volts
Volts
Volts
Volts
nSec
nSec
nSec
nSec
85
15
4
KHz
nSec
nSec
,"Sec
,"Sec
±%
±%
±%
LSB
LSB
LSB
TRANSFER CHARACTERISTICS
Linearity Error (Nole 4): +25°C
O°C to +70°C
-55°C 10 +125°C ("H" Models)
±1,4
±1f4
LSB
±V2
Differential Linearity Error
Guaranteed Over Temperature
No Missing Codes
Full Scale Absolute Accuracy Error (Notes 5, 6):
+25°C
O°C to +70°C
-55°C to +125°C ("H" Models)
Zero Error (Noles 5, 6): +25'C
O°C to +70°C
-55°C to +125°C ("H" Models)
.±%
±1
±1
±2
±2
LSB
LSB
LSB
±Y4
±%
±%
LSB
LSB
LSB
±1
±1
± 0.1
±20
Gain Error (Note 5)
Gain Drift
%
ppml'C
DYNAMIC CHARACTERISTICS
100
Conversion Time (Note 2)
Analog Input Settling Time (Note 8)
1.5
,"Sec
,"Sec
DIGITAL OUTPUTS
Complementary Offset Binary
Complementary Straight Binary
Logic Coding (Nole 9): MN5065
MN5066
Logic Levels (Note 1): Logic "1"
Logi·c "0"
Output Drive Capability:
Parallel Outputs: Logic "1" (VoH=2.5V)
(VoH=llV)
Logic "0" (VOL=O.4V)
(VoL=O.5V)
Serial and Status Outputs: Logic "1" (VoH=2.5V)
(VoH=llV)
Logic "0" (VOL=O.4V)
(VoL=O.5V)
648
+ 5V
+12V
+ 5V
+12V
4.95
11.95
+ 5V
+12V
+ 5V
+12V
-0.2
-0.2
+0.4
+1.0
-1.7
-2.0
+1.6
+4.0
mA
mA
mA
mA
+ 5V
+12V
+ 5V
+12V
-0.2
-0.2
+0.2
+0.5
-1.7
-2.0
+0.8
+2.0
mA
mA
mA
mA
0.05
0.05
Volts
Volts
Volts
Volts
+Vdd
REFERENCE OUTPUT
MIN.
MAX.
UNITS
10
Volts
%
ppm/oC
p.A
+12.00
+12.36
+12.36
Volts
Volts
± 0.01
± 0.04
%FSR/%Vs
TYP.
Internal Reference: Voltage
Accuracy
Tempco of Drift
Ext. Current Without Buffering
+ 6.3
± 5.
±15.
POWER SUPPLY REQUIRMENTS
Power Supply Range: +Vcc (Pin 18)
+Vdd (Pin 15)
+11.64
+ 4.75
Power Supply Rejection (Note 10):
Current Drain: +Vcc (Pin 18)
+Vdd (Pin 15)
Power Consumption
(Vcc~ 12V)
+ 5V
+12V
4.3
0.05
0.1
5.5
0.2
1.5
mA
mA
rnA
+ 5V
+12V
52
53
67
84
mW
mW
SPECIFICATION NOTES:
1. The +Vdd LogiC Supply (Pin 15) can be at any voltage between +5V (low
power TTL compatibility) and +12V (CMOS compatibility).
2. Conversion Time is defined as the width of the Converter's STATUS
(E.O.C.) pulse. See Timing Diagram. For the MN5065 and the MN5066, a
Applications Manual for an explanation of how Micro Networks. defines
Full Scali Absolute Accuracy, Zero, and Gain Errors. For the MNs06s and
MN5066 we 100% test Full Scale Absolute Accuracy and Zero Error at
room temperature and at the high and low extreme of the specified
operating temperature range.
100 ,LISee conversion time corresponds to an external clock frequency of
6. 1 LS8 for an B bit converter corresponds to 0.39% FSR. See Note 7.
85KHz. Micro Networks guarantees linearity and absolute accuracy at and
below this clock frequency.
7. FSR stands for Full Scale Range and is equal to the peak to peak input
voltage 01 the converter. For both the MNs065 and MN5066, FSR = 10V,
and 1 LSB ~ 39mV.
3. The clock may be asymmetrical. and it may ramp up and down as long as it
meets minimum pulse width and maximum rise and fall time requirements.
4. Micro Networks tests and guarantees maximum linearity error at room
temperature and at the high and low extremes of the specified operating
temperature range.
5. See the tutorial section of the Micro Networks. Product Guide and
8. Analog Input Settling Time is the time required for the input circuitry to
settle to within ±'/, LSB for a 10V step in input signal.
9. Serial and parallel output data have the same coding. Serial data is in
Non-Return to Zero (NRZ) format. See Output Coding and Timing Diagram.
10. PSRR is tested over a range of ±3% with Vcc
BLOCK DIAGRAM
Start
Convert \17)
I
Clock
Input (12)
PIN DESIGNATIONS
SUCCESSIVE
APPROXIMATION
REGISTER
f--
NC (14) ~
REF
I
I
I
(11) Status
(10) Serial
Output
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
+Vcc (18) ~
+Vdd (15) ~
Ground (16) ~
Ref. Out (13)
(9)
8 BIT D/A
I
(MN5065 only)
"
IA.
R"
-
•
COMPARATOR
APPLICATIONS INFORMATION
The digital circuitry used in the MN5065 and MN5066 is
CMOS. The standard precautionary measures for handling
CMOS should be followed.
Proper attention to layout and decoupling is necessary to
obtain specified accuracies from the MN5065 and MN5066.
The units' GROUND (Pin 16) should be connected to system
analog ground, preferably through a large ground plane
beneath the package. Power supplies should be decoupled
with tantalum or electolytic capaCitors located as close to the
units as possibi"e. For optimum performance and noise
I
18
PIN 1
MSB
Bit 2
Bit3
8it4
BitS
Bit 6
Bit 7
LSB
'-- -wv--Analog
Input
= Vdd = + 12V.
10
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Bit 5
Bit6
Bit 7
Bit 8 (LSB)
Analog Input
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
18
17
16
15
14
13
12
11
10
+Vcc Power Supply
Start Convert
Ground
+Vdd Logic Supply
N/C
Ref. Output (+6.3V)
Clock Input
Status (E.O.C.)
Serial Output
rejection, 1p.F capacitors paralleled with 0.01 p.F ceramic
capacitors should be used as shown in the diagram below.
Pin 180o--r'---1,-+12V
t
Pin 16c
1
Pin 150
~FI
I
~FT
-
I "F
I
r°.o1"F
001
Ground
-
+Vdd
649
TIMING DIAGRAM
Clock
Start Convert
MSB
Bit2
Bit3
Bit4
BitS
Bit6
Bit7
BitS
ZZ?1Z I/II ll.iJ,
ll1ZtIIIIzl4
ZZZZZZ?1?1~
UL~~~~________~r----l~O
~
I
ZZZIIIZZZZ~
ZZZZZZZZZZZ~
ZZZZZZZZIII~
ll1ZZZZIIII~
~~~~7-----------------------------~~~~------~
I
VllzzmZ0
L-____________________________________~r
Status
Serial Output
____________________________
zozzmomzzzzm
MSB
~
Bit 4
Bit6~
BitS
TIMING DIAGRAM NOTES:
1. Operation shown is for the digital word 0101 1101 which corresponds to
5. The delay between the resetting clock edge and the STATUS actually
+6.328V on the 0 to +10V (MN5066) input range. See Output Coding.
2. Conversion Time is defined as the width of the STATUS (E.O.C.) pulse.
3. The converter is reset (MSB = "1", all other bits = "0", STATUS = "0") by
6. The STATUS (E.O.C.) output will rise to a "1" 750 nSec (maximum) after
the first falling clock edge after the determination of LSB. STATUS will
holding the START CONVERT high during a low to high clock transition;
the START CONVERT must be high for a minimum of 300 nSec priorto the
clock transition. Output bits. starting with the MSB, will beset totheirfinal
values on succeeding clock edges. The START CONVERT input does not
have to return low for the conversion to continue.
4. The START CONVERT may be brought high al any time during a
dropping to a "0" is 750 nSec maximum.
remain high until the converter is reset. Parallel output data is valid as long
as STATUS is a "1".
7. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequent falling clock edges, and these
edges can be used to clock serial data into receiving registers.
8. Forcontinuous conversion, connect the STATUS output pin (Pin 11) tothe
START CONVERT input (Pin 17). When the converter is initially "powered
up", it may come on at any pOint in the conversion cyc,le.
conversion to reset and begin converting again.
OUTPUT CODING
ANALOG INPUT (DC VOLTS)
The key pOints along an AID converter's analog input/digital
output transfer function are the transition voltages, the input
voltages at which the digital outputs change from one state
to the next. These are the points manufacturers look for
when testing AID accuracy and linearity. To test the Full
Scale Absolute Accuracy of the MN5066, for example, we
find the input voltage at which the digital outputs just change
from 00000000 to 00000001. To test the Zero Error, we find
the input voltage at which the digital outputs just change
from 11111111 to 11111110. These and other transition voltages are listed below.
[1JJ
_
MN5066
+ 5.000
+ 4.961
+1.0.000
+ 9.961
00000000
00000000'
+ 0.039
0.000
- 0.039
+ 5.039
+ 5.000
+ 4.961
01111110
00000000'
10000000'
- 4.961
- 5.000
+ 0.039
0.000
11111110'
11111111
MSB
LSB
• Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as 0 will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
EXAMPLE: For an MN5065 (±5V analog input range) the transition from
digital output 11111111 to 11111110 (or vice versa) will ideally occurat an input
voltage of -4.961 volts. Subsequently, any input voltage more negative than
-4.961 volts will give a digital output of all "l's". The transition from digital
output 1000 0000 to 01111111 (or vice versa) will ideally occur at an input of
zero volts, and the 0000 0000 to 0000 0001 (or vice versa) transition should
occur at +4.961 volts. An input greater than +4.£61 volts will give all "O's"
MICRO NETWORKS
324 Clark S1., Worcester, MA 01606 (508) 852-5400
6-50
DIGITAL OUTPUT
MN5065
lLD
_
MN5100
MN5101
HIGH-SPEED
8-Bit AID CONVERTERS
MICRO NETWORKS
DESCRIPTION
FEATURES
MN5100 and MN5101 are very high-speed, 8-bit, successive
approximation AID converters. MN5100 guarantees a 1.5JLsec
conversion time, and MN5101 guarantees a 900nsec conversion time. Containing an internal reference and requiring only an external clock, these devices are much easier to use
than other 8-bit AID's in their speed class. Both devices are
functionally laser trimmed and complement their speed performance with excellent linearity (±Y2 LSB max) and accuracy (± Y2 LSB max) specifications. These specifications
are achieved without the need for external adjusting potentiometers and are guaranteed over the full specified
temperature range. MN5100 and MN5101 are a simple
solution to high-speed, low-resolution, digitizing requirements in single or multi-channel systems .
MN5100 and MN5101 are packaged in standard, 24-pin,
double-wide, hermetically sealed, ceramic DIP's. Both
devices are TTL compatible; have a low-drift, - 6.3V internal
reference; and offer 7 user-selectable input voltage ranges.
Supply requirements are ± 15V and + 5V, and power
consumption is 1550mW maximum.
Units are available and fully specified for OOC to +70°C
(MN5100 and MN5101) or -55°C to +125°C (MN5100H, H/B
and MN5101H, HIS) operation. For militarylaerospace or
harsh-environment commercial/industrial applications,
MN5100H/B CH and MN5101H/B CH are fully screened to
MIL-H-38534 in Micro Networks MIL-STD-1772 qualified facility.
• High Conversion Speed
900nsec MN5101
1.5,.sec MN5100
• Small 24-Pin DIP
• ±1/2LSB Linearity and
No Missing Codes
Over Temperature
• Parallel and Serial
Outputs
• Adjustment-free
No Gain or Offset
Adjustments Necessary
• Fully Specified O°C to +70°C
(MN5100/5101) or -55°C to
+125°C (MN5100/5101H or H/B)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
24 PIN DIP
0.015 (0.381)
0.035 (0.889)
P~N 1
IIr-_ O.08~ ~.W 1
....j
0.11
r.-\-~T
. 1)
~~~I
Part
Number
1315(33.40)
0.B10(20.57)
; - - - - - i -L
-r
O.120
Specified
Temperature Range
1.51'sec
1.5l'sec
1.51'sec
1.51'sec
900nsec
900nsec
900nsec
900nsec
O°C to +70°C
-55°C to +125°C
- 55°e to + 125°C
-55°C to +125°C
O°Cto +70°C
-55°e to +125°C
-55°e to +125°C
-55°e to +125°C
1.100(27.94)
--I1LJ~
L_
I
-I
Conversion
Time
I
gm~w,1
MN5100
MN5100H
MN5100H
MN5100H/B CH
MN5101
MN5101H
MN5101H/B
MN5101H/B CH
@.j""
0.170(4.18)
!.-O.600(1S.24JJ
Dimensions in Inches
(millimeters)
l1:JJ
_
MICRO NETWORKS
March 1988
324 Clark St., Worcester, MA 01606 (50B) B52·5400
6-51
MN5100 MN5101 HIGH·SPEED, 8·Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN5100, MN5101
MN5100H, MN5100H/B
MN5101H, MN5101H/B
Storage Temperature Range
Positive Supply (+ Vee, Pin 16)
Negative Supply (- Vee, Pin 13)
Logic Supply (+ Vdd, Pin 6)
Analog Inputs (Pins 11, 12)
Digital Inputs (Pins 23, 24)
- 55·C to + 125·C (case)
O·C to +70·C
-55·C to +125·C (case)
- 55·C to + 125·C (case)
- 65·C to + 150·C
- 0.5 to + 18 Volts
+0.5 to -18 Volts
- 0.5 to +7 Volts
±25 Volts
- 0.5 to + 5.5 Volts
PART NUMBER - - - - - - - - - - MN5100H/B CH
Select MNS100 or MNS10l Model.
I
Standard part is specified for O·C to +70·C
operation.
Add "H" suffix for specified -SS·C to +12S·C
(case) operation. _ _ _ _ _ _ _ _ _ _ _--'
Add "/B" to "H" devices for
Environmental Stress Screening. _ _ _ _ _ _ _--'
Add "CH" to "HIB" devices for
100% screening according to MIL-H-38S34.-------'
SPECIFICATIONS (TA= +25°C, ±Vcc= ±15V, +Vdd= +5V unless otherwise Indicated)(Note 1)
ANALOG INPUTS
MIN.
Input Voltage Ranges: Unipolar Posilive
Unipolar Negative
Bipolar
Input Impedance (Notes 2, 3): SV FSR
10VFSR
20VFSR
TYP.
MAX.
UNITS
Oto +5,Oto +10
Oto -5,010 -10
±2.5, ±5, ±10
Volts
Volts
Volts
1.5
3
k!l
k!l
k!l
6
DIGITAL INPUTS (Start, Clock)
Logic Levels All Inputs: Logic "1"
Logic "0"
Logic Currents: Start: Logic
Logic
Clock: Logic
Logic
"1" (VIH
"0" (VIL
"1" (VIH
"0" (VIL
+0.8
Volts
Volts
+80
-1.6
+40
-1.6
pA
rnA
pA
rnA
+2.0
;
;
;
;
+2.4V)
+ O.4V)
+ 2.4V)
+ O.4V)
TRANSFER CHARACTERISTICS
Resolution
a
Linearity Error (Note 4): Initial (+25° C)
Over Temperature (Note 5)
±'1.
±v.
±'12
± '/2
Bits
LSB
LSB
Full Scale Absolute Accuracy Error (Notes 4, 6):
Initial (+2So C)
O°C to +70 0 C
-SsoC to +12SoC
±'1.
±'12
±1
± '/2
±1
±2
LSB
LSB
LSB
Unipolar Offset Error (Notes 4, 7):
Initial (+2S°C)
DoC to +70 0 C
-S5°C to + 125°C
±'1.
±'12
±1
± '12
±1
±2
LSB
LSB
LSB
Bipolar Zero Error (Notes 4, a):
Initial (+2S0C)
DoC to +70°C
-SSOC to +12SoC
±'1.
±'12
±1
±'h
±1
±2
LSB
LSB
LSB
+0.4
Volts
Volts
200
ppm/DC
pA
Conversion Time (Note 10): MNS100
MNS101
1.S
900
,.sec
nsec
External Clock Frequency (Note 2): MNS100
MN5101
S.33
MHz
MHz
DIGITAL OUTPUTS
Output Coding (Note 9): Unipolar Ranges
Bipolar Ranges
Logic Levels All Outputs: Logic "1" (lsource s aOpA)
Logic "0" (Isink s 3.2mA)
CSB
COB
+2.4
REFERENCE OUTPUT
-6.3
Internal Reference (Note 2): Voltage
Accuracy
Tempeo
External Current
Volts
±10
±10
%
DYNAMIC CHARACTERISTICS
a88
Clock Pulse Width (Note 2): High
Low
20
50
nsec
nsec
Setup Time Start Low to Clock (Note 2)
20
nsec
6-S2
POWER SUPPLIES
Power Supply Range: + 15V Supply
-15V Supply
+5V Supply
MIN.
TYP.
MAX.
UNITS
+14.55
-14.55
+4.75
+15.00
-15.00
+5.00
+15.45
-15.45
+5.25
Volts
Volts
Volts
±0.01
±0.03
± 0.01
Power Supply Rejection (Notes 3, 11): + 15V Supply
-15V Supply
+5V Supply
%FSR/o/nSupply
%FSR/%Supply
%FSR/%Supply
Current Drain: +15V Supply
-15V Supply
+5V Supply
+25
-25
+75
+35
-35
+100
mA
mA
mA
Power Consumption
1125
1550
mW
SPECIFICATION NOTES:
1. Listed specifications apply lor all part numbers unless specilically indicated.
2. These parameters are listed for reference and are not tested.
3. FSR =full scale range. and itis equal to the nominal peak-to-peak voltage olthe
selected input voltage range. A unit connected for ± 1OV operation has a 20V
FSR. A unitconnectedforOto + 10V, Oto -10Vor ±SVoperation has a 10V
FSR. A unit connected forO to +SV,Oto -SV,or ±2.SVoperationhasaSVFSR.
4. 1 LSB for B bits in 20V FSR is 7BmV.
1 LSB for B bits in 10V FSR is 39mV.
1 LSB for B bits in SV FSR is 19.5mV.
S. Listed specifications apply over the O·C to + 70·C temperature range for standard products, and over the -SS·Cto + 12S·C (case) range for "H" products.
6. Full scale absolute accuracy error includes offset, gain, linearity, noise and all
other errors. Full scale accuracy specifications apply at positive full scale for
unipolar positive input ranges, at negative full scale for unipolar negative input
ranges and at both positive and negative full scale for bipolar input ranges. Full
scale accuracy error is defined as the difference between the ideal and the actual input voltage at which the digital output just changes from 0000 0000 to 0000
0001 for unipolar positive and bipolar input ranges. Additionally, it describes the
accuracy olthe 1111 1111 to 1111 1110 transition for unipolar negative and
bipolar input ranges. The former transition ideally occurs at an input voltage 1
LSB below the nominal positive full scale voltage. The latter ideally occurs 1 LSB
above the nominal negative full scale voltage. See Digital Output Coding.
7. Unipolar offset error is defined as the difference between the ideal and the ac-
B.
9.
10.
11.
tual input voltage at which the digital output just changes from 1111 1111 to 1111
1110 when operating MN5100/5101 on a unipolar positive range (0 to + 5V, 0
to + 1OV) or from 0000 0000 to 0000 0001 when operating on a unipolar negative
range (0 to - 5V or 0 to -10V). The ideal value at which this transition should
occur is + 1 LSB for unipolar positive ranges and -1 LSB for unipolar negative
ranges. See Digital Output Coding.
Bipolar zero error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0111 1111 to 1000
0000 when operating the MNSl OO/Sl 01 on a bipolar range. The ideal value at
which this transition should occur is 0 volts. See Digital Output Coding.
CSB complementary straight binary. COB complementary offset binary.
Conversion time is defined as the width of Status (E.O.C.).
Power supply rejection is defined as the change in the analog input voltage at
which the 11111110to 11111111 or 0000 0000 to 0000 0001 outputtransitions
occur versus a change in power-supply voltage.
=
=
Specifications subject to change without notice as Micro Networks reserves the
right to make improvements and changes in its products.
I
BLOCK DIAGRAM
Start Convert (24)
(21) Status (E.O.C.)
Successive
Approximation
Register
Clock Input (23)
(1) Serial Output
-
+ ISV Supply (16) 0
~
(5) Bit 1 (MSB)
-15V Supply (13) 0
~
(4)Bit2
+ 5V Supply (6) 0
~
(3) Bit 3
Ground (10) 0
~
(2) Bit4
Ground (22) 0
~
No Connect (15) 0
~
Bipolar Offset (7) no
(20) BitS
.l'N-
I I
IA"I'-
-
(19)8it6
(18) Bit 7
Ref.
(17) Bit 8 (LSB)
Reference Output ( - 6.3V) (14)
B-Bit D/A
Bipolar Offset (9) n.
10V Input (11)
20V Input (12)
Summing Junction (8)
V"
--#l'-
,..
~
~ator
6-53
PIN DESIGNATIONS
•
24
12
13
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Serial Output
Bit4
Bit 3
Bit 2
Bit 1 (MSB)
+ 5V Supply (+ Vdd)
Bipolar Offset
Summing Junction
Bipolar Offset
Ground
10V Input
20V Input
Start Convert
Clock Input
Ground
Status (E.O.C.)
Bit 5
Bit 6
Bit 7
Bit 8 (LSB)
+ 15V Supply (+ Vee)
N.C.
Reference Output (-6.3V)
-15V Supply (- Vee)
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-The Successive Approximation Register (SAR) is a set of flip flops (and control logic)'
whose outputs act as both the direct (parallel) data outputs of
the Analog to Digital Converter (AID) and the digital drive for
the AID's internal Digital to Analog Converter (D/A). See Block
Diagram. Holding the AID's Start Convert (pin 24) low during a
clock low to high transition resets the SAR. In this state, the
output of the MSB flip flop is set to logic "0", the outputs of the
other bit flip flops are set to logic "1", and the Status output
(pin 21) is set to logic "1" (See Timing Diagram). The Start Convert must now be brought high again for the conversion to continue. If the Start is not brought high, the converter will remain
in the reset state.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator continuously compares to the analog input signal.
The comparator output ("1" or "0") informs the SAR whether
the present digital output (0111 1111 in the reset state) is
"greater than" or "less than" the analog input. Depending
upon which is greater, on the first rising clock edge after the
Start has returned high, the SAR will set the MSB to its final
state ("1" or "0") and bring bit 2 down to a "0". The digital
output is now X011 1111. The DIA converts this to an analog
value, and the comparator determines whether this value is
greater or less than the analog input. On the next rising
clock edge, the SAR reads the comparator feedback, sets
bit 2 to its final value, and brings bit 3 down to a logic "0".
The digital output is now XX01 1111. This successive approximation procedure continues until all the output bits
are set. The rising clock edge that sets the LSB (bit 8) also
drops the Status output to a "0" signaling that the conversion is complete. Output data is now valid and will remain
so until another conversion is started. The clock does not
have to be turned off.
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracies from
the MN5100Series converters. The units' two ground pins (pins
10 and 22) are not connected internally. They should be tied
together as close to the package as possible and connected to
system analog ground, preferably through a large ground
plane underneath the package. If the grounds cannot be tied
together and must be run separately, a non-polarized 0.0~:.,f'
bypass capacitor should be connected between pins 10 and 22
as close to the unit as possible and wide conductor nms
employed.
6-54
Power supplies should be decoupled with tantalum or electrolytic type capacitors located close to the converter. For optimum performance and noise rejection, 11'F capacitors
paralleled with O.OlI'F ceramic capacitors should be used as
shown in the diagrams below.
Pin16c
1,F
Pins 10, 22
I
I
I
I
+15V
O.D1,F
-I+---If-Ground
<>-0
1,F
Pin 13 ,
Pin6
0
1,F
I
T
I
T
+sv
O.OlpF
Pins 10,22 0-0-.l.----L-Ground
T T
O.01pF
-
-15V
POWER SUPPLY DECOUPLING
CONTINUOUS CONVERTING-The MN5100 Series AID converters can be made to continuously convert by tying the
Status output (pin 21) to the Start Convert input (pin 24). In
this configuration, Status (Start Convert) will go low at the
end of a conversion (see Timing Diagram) and the next rising
clock edge will reset the converter bringing Status (Start Convert) high again. The MSB will be set on the next rising clock
edge. The result is that the Status will go low for approximately one clock period following each conversion. Please
read the section describing the Status output.
SHORT CYCLING-For applications requiring less than
8-bits resolution, the MN5100 Series AID's can be truncated
or short cycled to the desired number of bits with a proportionate decrease in conversion time. The following circuit
may be used to truncate at n bits.
SHORT CYCLING SINGLE CONVERSION
Clock
o-----f~,
Status o -_ _ _......_ _ _...q
Slart
f------4>---o Convert
TIMING DIAGRAM
Clock
Start Convert
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit6
Bit 7
LSB
IT!IlIll!7111
ZZZtllZZllllJ
o
llll.ZZt7.ilZlJ
ZZIIlZlllll.?J
/ IllllZlllZlJ
ll221.ZZlllllJ
Zl!1ll.Zlll.ZlJ
ZZZlll2ItJ.1Z1
o
o
o
STATUS
Serial Output
MSB
Bit 2
TIMING DIAGRAM NOTES:
1. Operation shown is for the digital word 1101 0001 which corresponds to
- B.164V on the 0 to -10V input range. See Output Coding.
2. Conversion Time is defined as the width of the Status (E.O.C.) pulse.
3. The converter is reset (MSB = "0", all other bits="1", Status ="1") by
holding the Start Convert low during a low to high clock transition. The
Start Convert must be low for a minimum of 20 nsec prior to the clock tran·
sition. Holding the Start low will hold the converter in the reset state. Actual conversion will begin on the next rising clock edge after the Start has
returned high.
4. The delay between the resetting clock edge and Status actually rising to a
"1" is 50nsec maximum.
5. The Start Convert may be brought low at any time during a conversion to
reset and begin converting again.
Assuming a conversion is already in progress, bit (n + 1) will
go low as bit n is being set (see Timing Diagram). Since the
Start Convert signal is high at this time, Status (the output of
IC2) will go low gating off the clock at IC3 ending the conversion. To begin a new conversion, Start Convert is brought low
driving Status high and gating on the clock. The first rising
clock edge the converter sees with Start Convert low will
reset the converter bringing bit (n + 1) high again. Now Status
will remain high as Start Convert is brought back high allowing the conversion to continue. Therefore, in this configuration, Status and Start Convert function normally, i.e., the
same as Status and Start Convert for a converter not being
short cycled.
SHORT CYCLING AND CONTINUOUS CONVERTING-A
previous section described how continuous converting for
8-bits could be accomplished by simply tying the Status output back to the Start Convert input To continuously convert
at n bits, one simply has to tie the bit (n + 1) output back to
the Start Convert input The bit (n + 1) output acts like a
Status when one short cycles at n bits_It goes high when the
converter is reset, remains a "1" during the conversion, and
drops to a "0" as bit n is being set Since it is possible for the
converter to come on in any state at power-on, a lock-up condition may occur if bit (n + 1) comes on as a "1" and the conversion process comes on at bit (n + 2). This situation can be
avoided by making the Start Convert input the AND function
of bit (n + 1) and the Status output.
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit B
6. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequent falling clock edges, and these
edges can be used to clock serial data into receiving registers.
7. Output data will be valid 50nsec (maximum) after the Status (E.O.C.) output has returned low. Parallel output data will remain valid and the Status
output low until another conversion is initiated.
B. For continuous conversion, connect the Status output (pin 21) to the Start
Convert input (pin 24). See section on Continuous Conversion.
9. When the converter is initially "powered up", it may come on at any point
in the conversion cycle.
If one is already using the circuit described in the section
labeled Short Cycling, one can short cycle and continuously
convert by making the Start Convert input the AND function
of Status (iC2) and Status (pin 21) outputs.
SHORT CYCLING CONtiNUOUS CONVERTING
MN5tOOl5101
(24)1----,
IC = 7400
STATUS OUTPUT -The Status or End Of Conversion (E.O.C.)
output will be set to a logic "1" when the converter is reset;
will remain high during conversion; and will drop to a logic
"0" when conversion is complete. Due to propagation delays,
the least significant bit (LSS) of a given conversion may not
be valid until a maximum of 50nsec after Status has returned
low_ Therefore, an adequate delay must be provided if Status
is to be used to strobe latches to hold output data. Simple
6-55
gate delays can be employed or the Status can be made the
input of a 0 flip flop whose clock input is the same as the converter clock (see sketch)_ In this situation, the Q output will
change one clock period after Status changes.
LATCHING DATA CONTINUOUS CONVERSIONS
Clock
<>--r----i (23)
LATCHING OUTPUT DATA
Status _ _ _~ 0
,...
Q
Strobe
Strobe
7474
Q
Strobe
i
Clock
Clock
I
I
I
I
I
I
I
I
I
I
I
I ~
Strobe-,
Clock
Start
I
Status .-J'r-----------;I~
I
I
I
~r-+-------------+-...L-I
I
1,..--+-_ _ _ _ _ _ _ _ _--;I
I
If continuously converting, the Status (E.O.C.) output can be
NORed with the converter clock, as shown above, to produce a positive strobe pulse V. period wide, V. period after
the Status output has gone low. The rising edge of this
pulse can be used to latch data after each conversion.
LLI
I
I
L
status--f
Q---;.I--i'
0--+1I - ...
.I
I
I
I
I
I
INPUT RANGE SELECTION
Analog Input Voltage Range
Pin Connections
oto
Oto -5V
Connect Input to Pin
Connect Pin 8 to Pin
Connect Pin 7 to Pin
Connect Pin 9 to Pin
Input Impedance (kill
11
12
Ground
Ground
1.5
-10V
11
Open
Ground
Ground
3
Oto +5V
Oto +10V
±2.5V
±5V
±10V
11
7,9,12
8,9,12
7,8,12
1.5
11
7,9
8,9
7,8
3
11
9,12
Ground
8,12
1.5
11
9
Ground
8
3
12
9
Ground
8
6
DIGITAL OUTPUT CODING
Analog Input Voltage Range
Oto -5V
o to
-10V
Digital Outputs
Oto +5V
Oto +10V
±2.5V
±5V
±10V
MSB
LSB
0.000
-0.019
0.000
-0.039
+5.000
+4.981
+10.000
+9.961
+2.500
+2.481
+5.000
+4.961
+10.000
+9.922
0000
0000
0000
0000
-2.481
-2.500
-2.519
- 4.961
-5.000
-5.039
+2.519
+2.500
+2.481
+5.039
+4.961
+0.019
0.000
-0.019
+0.039
0.000
-0.039
+0.078
0.000
-0.078
0111
~rJ0'
1000
1110'
~~
0000'
-4.981
-5.000
-9.961
-10.000
+0.019
0.000
+0.039
0.000
- 2.481
-2.500
-4.961
-5.000
-9.922
-10.000
1111
1111
1110'
1111
+5~000
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is straight binary.
2. For bipolar input ranges, output coding is offset binary.
3. For a to + SV, a to - SV or ±2.SV input ranges, 1 LSB for 8 bits = 19.5mV.
4. For a to + 10V, 0 to -10Vor ± SV input ranges, 1 LSB for 8 bits = 39mV.
5. For ±10V input range, 1 LSB for8 bits = 78mV.
·Voltages given are the theoretical values forthe transitions indicated.ldeal·
Iy, with the converter continuously converting, the output bits indicated as~
will change from "1" to "0" or vice versa as the input voltage passes through
the level indicated.
6-56
EXAMPLE: For an MNS100 operating on its ± 10V Input range, the transition
from digital output 0000 0000 to 0000 0001 (or vice versa) will ideally occur at
an input voltage of +9.922 volts. Subsequently, any input voltage more
positive than + 9.922 volts will give a digital output of all "D's". The tranSition
from digital output 10000000 to 01111111 will ideally occur at an input of
0.000 volts, and the 11111111 to 11111110 transition should occur at - 9.922
volts. An input more negative than - 9.922 volts will give all "1's".
l1JJ
_
MN5120 Series
MN5130 Series
MN5140 Series
MICRO NETWORKS
8-Bit AID CONVERTERS
DESCRIPTION
FEATURES
The MN5120, MN5130 and MN5140 Series are a family of
8-bit, high-speed, successive approximation analog-to-digital
converters in small, 18-pin, hermetically sealed dual-in-line
packages. All devices incorporate our own thin-film resistor
networks and are functionally laser trimmed as complete
devices to meet all published specifications without external
adjustments.
Each Series offers analog input ranges of 0 to + 10V, 0 to
-10V, ±5V and ±10V. MN5120 Series devices complete a
conversion in 6ftsec. MN5130 and MN5140 Series devices
complete a conversion in 2.5ftsec. The MN5120 and MN5130
Series devices operate from ± 15V supplies. MN5140 devices
operate from ± 12V supplies. All units require a + 5V logic
supply.
• 2.5?,sec Maximum Conversion
Time (MN5130, MN5140)
• Small 18-pin DIP
• ±1/2 LSB Linearity and
No Missing Codes
Guaranteed Over Temperature
• Full Mil Operation
-55°C to + 125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
18 PIN DIP
II!
q
q
.".to
"l
u:::;::=
1:=0.310(7.67) .....
0.170(4.32) max
0.170(4.32) max
T
These A/D's are fully specified and tested for linearity and
accuracy at room temperature and at both the high and low
extremes of the specified operating temperature range.
Devices may be ordered for either O°C to +70°C or -55°C
to +125°C ("H" models) operation, and all guarantee
± 1/2 LSB linearity over their entire operating temperature
range. Full scale absolute accuracy is guaranteed to be better
than ±1 LSB at +25°C and better than ±2LSBs over
temperature. For military/aerospace or harsh-environment
commercial/industrial application, "H/B CH" are fully screened
to MIL-H-38534 in Micro Networks' MIL-STD-1772 qualified
facility.
I
Low cost, 8-bit resolution and high conversion speeds make
MN5120, MN5130 and MN5140 Series A/D's excellent
choices for digitizing data in microprocessor-based systems
for industrial-control and monitoring applications.
Adjustment-free operation, accuracy and linearity specs
guaranteed from -55°C to +125°C, and optional MIL-H-38534
screening make them excellent choices for military/aerospace
and avionics applications.
I+- 0.300 (7.62)_
Dimensions in Inches
(millimeters)
[1JJ
_
January 1992
Copyright 1992
MICRO NETWORKS
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-57
MN5120 MN5130 MN5140 SERIES 8-Bit AID CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
O"C to + 70"C
- 55"C to + 125"C ("H" Models)
- 65"C to + 150"C
+18 Volts
-18 Volts
- 0.5 to + 7 Volts
±15 Volts
- 0.5 to + 5.5 Volts
Storage Temperature
Positive Supply (+ Vcc, Pin 1)
Negative Supply (- Vcc, Pin 18)
Logic Supply (+ Vdd, Pin 12)
Analog Input (Pin 2)
Digital Inputs (Pins 8, 10)
PART NUMBER
MN51XX H/B CH
- operation.
... ~.~,,~~~ . .~
II
Add "H" for specified -55°C to +125°C
operation. _ _ _ _ _ __
Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.
SPECIFICATIONS (TA = + 2SoC, Supply Voltagas ± 1SV and + SV unlass otherwise Indicated)
MIN.
ANALOG INPUTS
Input Voltage Range: MN5120,
MN5121,
MN5122,
MN5123,
MN5130,
MN5131,
MN5132,
MN5133,
MN5140
MN5141
MN5142
MN5143
Input Impedance:
MN5130,
MN5131,
MN5132,
MN5133,
MN5140
MN5141
MN5142
MN5143
MN5120,
MN5121,
MN5122,
MN5123,
TYP_
MAX_
o to
UNITS
-10
- 5 to + 5
-10 to + 10
to +10
Volts
Volts
Volts
Volts
5
KIJ
KIJ
KIJ
KIJ
o
5
10
5
DIGITAL INPUTS (ALL UNITS)
Logic Levels: Logic "1"
Logic "0"
Clock Input (Note 1): Pulse Width High
Pulse Width Low
Loading (Note 2)
Frequency (Note 3): MN5120 Series
MN5130 Series
MN5140 Series
Start Convert Input: Loading High (Note 2)
Loading Low (Note 2)
Setup Time Start LoW to Clock (Note 4)
DIGITAL OUTPUTS (ALL UNITS)
Logic Levels: Logic "1"
Logic "0"
2.0
Volts
Volts
1
1.33
3.2
3.2
nSec
nSec
TTL Load
MHz
MHz
MHz
25
50
2
1
20
3.6
0.2
2.4
Output Coding (Note 5): Unipolar Ranges
Bipolar Ranges
Output Drive Capability, All Outputs (Note 2): Logic "1"
Logic "0"
0.8
0.4
TTL Loads
TTL Load
nSec
Volts
Volts
Straight Binary
Offset Binary
11
5
TTL Loads
TTL Loads
TRANSFER CHARACTERISTICS (ALL UNITS)
Linearity Error (Note 6): O"C to + 70"C
- 55"C to + 125"C ("H" Models)
Differential Linearity Error
No Missing Codes
±Y2
±1fz
±Y2
LSB
LSB
LSB
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Notes 7, 8):
+ 25"C
- 55"C to + 125"C (Note 10)
±%
± 1
± 2
LSB
LSB
±Y2
± 1
± 1
LSB
LSB
Unipolar Offset Error, 0 to + 10V Range (Notes 7, 8):
+ 25"C
- 55"C to + 125"C (Note 10)
±1f4
±%
± 1
± 1
LSB
LSB
Unipolar Offset Error, 0 to -10V Range (Notes 7, 8):
+ 25"C
- 55"C to + 125"C (Note 10)
±
±Y2
± 1
± 2
LSB
LSB
Bipolar Offset Error, ± 5V and ± 10V Ranges (Notes 7, 8):
+ 25"C
- 55"C to + 125"C (Note 10)
± 1
± 1
± 2
LSB
LSB
Offset Drift (Note 9): 0 to + 1QV Range
to - 10V Range
± 5V and ± 10V Ranges
± 1
±10
±10
ppm of FSR/"C
ppm of FSR/"C
ppm of FSR/"C
Gain Error (Note 7)
Gain Drift
± 0.1
±20
%
ppm/"C
Zero Error (Notes 7, 8): + 25"C
- 55"C to + 125"C (Note 10)
o
6-58
± 1/4
± 1
±
V4
1
±Y2
MIN.
DYNAMIC CHARACTERISTICS
MAX.
TYP.
6
2.5
2.5
Conversion Time (Note 3): MN5120 Series
MN5130 Series
MN5140 Series
UNITS
I'Sec
I'Sec
I'Sec
POWER SUPPLY REQUIREMENTS (ALL UNITS)
±11
+ 4.75
Power Supply Range (Note 11): ± Vee
+Vdd
±17
+ 5.25
+5.00
±O.02
±0.01
Power Supply Rejection (Note 11): + Vee
-Vee
Volts
Volts
%FSR/%Vs
%FSR/%Vs
Current Drain (Note 11): + Vee
-Vee
+Vdd
12
-10
70
16
-18
100
mA
mA
mA
Power Consumption (All Units)
680
1010
mW
SPECIFICATION NOTES:
1.
The clock may be asymmetrical with minimum positive or negative
pulse width. See Note 3.
2.
One TIL load is defined as sinking 40"A with a logic "1" applied and
sourcing 1.S mA with a logic "0" applied.
3.
Conversion Time is defined as the width of the converter's STATUS
(E.O.C.) output pulse. See Timing Diagram. For the MN5120 series,
the maximum conversion time of 6 ",Sec corresponds to an external
clock frequency of 1.33 MHz. For the MN5130 and MN5140 series, the
maximum conversion time of\ 2.5 Ip,Sec corresponds to an external
clock frequency of 3.2 MHz. Micro Networks guarantees Absolute
Accuracy and Linearity at and below these clock frequencies.
7.
See Absolute Accuracy section below for explanation of how Micro
Networks tests and specilies Absolute Accuracy, Offset, Gain and
Zero Errors.
8.
1 LSB for an 8 bit converter corresponds to ± 0.39%FSR .. See Note 9.
9.
FSR stands for Full Scale Range and is equal to the peak to peak
voltage of the selected input range. For the ± 10V input range, FSR is
20 volts, and 1 LSB Is equal to 78 mY. For the 0 to ± 10V and ± 5V
ranges, FSR is 10 volts, and 1 LSB is equal to 39 mV.
4.
In order to reset the converter, START CONVERT must be brought
low at least 20 nSec prior to a low to high clock transition. See
Timing Diagram.
10. For Commercial Models, this specification applies over the ODe to
+ 70 D e range. See Ordering Information.
5.
Serial and parallel output data have the same coding. Serial data is
in Non·Return to Zero (NRZ) format. See Output Coding (page 8)and
Timing Diagram.
6.
Micro Networks tests and guarantees maximum linearity error at
room temperature and at both extremes of the specified operating
temperature range.
11. For 1he MN5120 and MN5130 Series the positive and negative power
supply ( + Vcc and - Vcc) requirements are + 15V and -15V. For the
MN5140 series the + Vcc and - Vec requirements are + 12V and
-12V. All units will operate over a ± Vcc range of ±11V to ±17Vwith
reduced accuracy, and all units require a + 5V logic supply ( + Vdd).
PIN DESIGNATIONS
BLOCK DIAGRAM
~~~:ert (8)
CIOCk(10)
Input
+Vcc
- Vce
+ Vdd
Ground
Ground
(1)
(18)
(12)
(9)
(17)
SUCCESSIVE
APPROXIMATION
REGISTER
•
+--1-++-1--+-1-+--4-_ 1(16) Bit 1 (MSB)
(15)
(14)
(13)
(S)
(5)
(4)
Bit 2
Bit 3
Bit4
Bit5
BitS
Bit 7
(3) Bit 8 (LSB)
9
1
2
Analog
Input (2) I
18
Pin 1
(7) Status (E.O.C.)
(11) Serial Output
3
4
5
6
7
8
9
Positive Supply (+ Vee)
Analog Input
Bit 8 (LSB)
Bit 7
Bit 6
Bit 5
Status (E.O.C.)
Start Convert
Ground
10
18
17
16
15
14
13
12
11
10
Negative Supply ( - Vee)
Ground
Bit 1 (MSB)
Bit2
Bit 3
Bit 4
+ 5V Supply ( + Vdd)
Serial Output
Clock Input
6-59
ABSOLUTE ACCURACY ERROR
DIGITAL
OUTPUT
DIGITAL
OUTPUT
--+
11111111
A given digital output code is valid for a band of analog input voltages that is ideally 1 LSB wide. This is demonstrated
in the next column where portions of the theoretical analog
input/digital output transfer function of the MN5122,
MN5132, and MN5142 AID converters (± 10V input range) are
sketched.
Notice that, ideally, any analog input between zero and
+ 0.078V (1 LSB.= 0.078 volts) will give a digital output of
10000000. If we assign this code to the nominal midrange of
the analog input band for which it is valid, we can say that
the 1000 0000 digital code corresponds to analog inputs of
+ 0.039V ± 0.039V ( + 0.039V ± Yo LSB). The ± Yo LSB is a
quantization uncertainty unavoidable in AID conversion. It is
referred to as Inherent Quantization Error and its magnitude
can be reduced only by going to higher resolution
converters.
It is difficult and time consuming to measure the center of a
quantization level (the + 0.039 volts in this example). The
only pOints along an A/D converter's analog input/digital
output transfer function that can quickly and accurately be
detected and measured are the transition voltages, the voltages at which the digital outputs change from one code to
the next. The Abso/ute Accuracy Error of a voltage input AID
converter is the difference between the actual, unadjusted,
analog input voltage at which a given digital transition occurs and the analog input voltage at which that transition is
ideally supposed to occur. This difference is usually expressed in LSB's or %FSR (see Note 9 above). Absolute Accuracy Error includes gain, offset, linearity, and noise errors,
and when specified over temperature, encompasses the individual drifts of these errors.
11111110
11111101
8
1000 0001
N
N
......
I
I
~ ~ ~
I
,,
CD
CD
'"
en
I
CD
---,----1
(10)
I
MN5120/30/40
SHORT CYCLING CONTINUOUS CONVERTING
Strobe
MN5120/30/40
(8)1---....,
Clock
Status
I
I
1.-----------.2,1
I
I
I
I
.-JI
Strobel]
I
If one is already using the circuit described in the section
labeled SHORT CYCLING, one can short cycle and continuously convert by making the START CONVERT input the
AND function of STATUS (IC2) and STATUS (pin 7) outputs.
STATUS OUTPUT-The STATUS or END OF CONVERSION
(E.O.C.) output will be set to a logic "1" when the converter
is reset; will remain high during conversion; and will drop to
a logic "0" when conversion is complete. Due to propagation delays, the least significant bit (LSB) of a given conversion may not be valid until a maximum of 50 nSec after
STATUS has returned low. Therefore, an adequate delay
must be provided if STATUS is to be used to strobe latches
to hold output data. Simple gate delays can be employed or
the STATUS can be made the input of a D flip flop whose
clock input is the same as the converter clock (see sketch).
In this situation, the Q output will change one clock period
after STATUS changes.
I~
I
I ~
I
USING A TRACK AND HOLD AMP WITH MN5120/30/40 AID's
- The error that results when trying to convert moving
analog signals with a successive approximation AID can be
as great as the amount the analog Signal changes during a
single AID conversion time. If this error is unacceptable, a
Track and Hold (T/H) or Sample and Hold (S/H) amplifier can
be placed between the analog signal source and the AID
converter. A careful error analysis will be necessary to determine if the T/H is actually reducing and not increasing overall error. T/H parameters such as aperture uncertainty, gain
accuracy, pedestal error and droop rate will have to be contended with (see the tutorial section of the Micro Networks'
Applications Manual and Product Guide for a complete discussion of T/H parameters).
Normally, the T/H can be controlled directly by the AID's
STATUS output. Typical connections are shown on the next
page. The STATUS output changes from a "0" to a "1" when
the converter is reset. This drives the T/H from the track to the
hold mode. At the end of conversion, STATUS returns to a "0"
restoring the T/H to the track mode.
6-63
track-te-hold settling time do not contribute errors. If necessary, the width of the START CONVERT pulse can be increased to allow more time between the T/H being commanded into the hold mode (STATUS = "1") and the MSB
being set. Recall that output bits do not begin to get set until after the START CONVERT has returned high. The example below shows a 2.25 "Sec delay to allow for track to hold
settling. Clock frequency = 1.33 MHz; 1 period = 0.75 "Sec.
DRIVING A TRACK AND HOLD
STATUS~
MN343 T/H
6 "S Acq. Time
4 mV Pedestal
.3 mV/mSec Droop
"l"=TRACK
"0"= HOLD
Clock
>------1 (2)
Start Convert
MN5120/30/40
Status
START
CONVERT
I--
(8)
MSB
Recall that if the START CONVERT pulse is brought high immediately after the converter has been reset, the MSB will
be finalized one clock period later (see Timing Diagram).
Care should be taken to ensure that aperture delay time and
Bit2
Bit 3
INPUT VOLTAGE AND OUTPUT CODING
ANALOG INPUT
MN5120,30,40
o to -10V
DIGITAL OUTPUT
MN5121,31,41
:!:5V
MN5122,32,42
:!:10V
MN5123,33,43
to +10V
0.000
-0.039
+5.000
+4.961
+ 10.000
+9.922
+ 10.000
+9.961
-4.961
- 5.000
-5.039
+0.039
0.000
-0.039
+0.078
0.000
- 0.078
+ 5.039
+5.000
+4.961
*, *,.
-9.961
-10.000
-4.961
- 5.000
- 9.922
-10.000
+ 0.039
0000 OOO~'
0000 0000
o
0.000
MSB
1111
1111
LSB
1111
111~'
1000 OOO~·
0111
111~'
---l
l17T11t
l//O/I
llll.llJ
LJ-
• Voltages given are the theoretical values for the transitions indicated. Ideally, with the converter continuously converting, the output bits indicated as $ will
change from "1" to a "0" or vice versa as the input
voltage passes through the level indicated. See the
section on Absolute Accuracy Error for an explanation of Output Transition Voltages.
EXAMPLE: For an MN5122 (± 10V analog input range)
the transition from digital output 0000 0000 to 0000
0001 (or vice versa) will ideally occur at an input
voltage of - 9.922 volts. Subsequently, any input volt·
age more negative than - 9.922 volts will give a
digital output of all "0'5". The transition from digital
output01111111 to 1000 0000 will ideally occur at an
input of zero volts, and the 1111 1110 to 1111 1111
transition should occur at
+ 9.922 volts. An input
greater than +9.922 volts will give all "1'5".
0::1J
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-64
2.5 "Sec
MN5150
~
_
MICRO NETWORKS
HIGH-SPEED
a-Bit AID CONVERTER
with 3-STATE OUTPUTS
DESCRIPTION
FEATURES
MN5150 is a high-speed, 8-bit, successive approximation
analog-to-digital converter with a three-state output buffer for
easy interfacing to microprocessor and microcomputer data
buses. Other performance features include a 2.5/Lsec maximum conversion time, ± 1f2 LSB linearity and "no missing
codes" guaranteed over the entire operating temperature
range, and ± 1 LSB unadjusted absolute accuracy. Convenience features include hermetic dual-in-line packaging, 7
user-selectable input ranges, and thanks to the stability of
our own laser-trimmed thin-film resistor networks, the absence of external gain and offset adjusting potentiometers.
• Fast 2.5~sec
Conversion Time
• 3-State Output Buffer
• ±1/2LSB Linearity and
No Missing Codes Over
Temperature
• Adjustment-Free
No Gain or Offset
Adjustments Necessary
• Fully Specified O°C to +70°C
(MN5150) or -55°C to +125°C
(MN5150H and MN5150H/B)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
Units are available for either O°C to + 70°C or - 55°C to
+ 125°C operation with performance fully specified and
guaranteed over the entire operating temperature range.
High reliability processing, screening and qualification
according to Method 5008 of MIL-STD-883 are available for
military/aerospace applications.
24 PIN DIP
~Nl
O"'5 •. 381)1~
~
\r.\-----,f~I
a~~ !§::
j
1.100 ('.a.94)
u-t~L
!~
0.170 (4.3i-8)
I--
0.600 (15.24)
I
Units are available for either O°C to +70°C or -55°C to + 125°C
operation with performance fully specified and guaranteed over
the entire operating temperature range. High-reliability processing, screening and qualification according to MIL-H-38534 are
available for military/aerospace applications.
-.I
MN5150's 3-state output buffer simplifies interfacing to
microprocessor and microcomputer data buses. In memorymapped applications, MN5150 looks like a RAM location with a
2.5/Lsec access time. It should be considered for high-speed industrial monitoring and automatic test equipment. Optjonal MILH-38534 screening, hermetic packaging, and fully guaranteed
performance from -55°C to + 125°C make MN5150H/B CH an
excellent choice for fast military data digitizing applications.
Part
Number
MN5150
MN5150H
MN5150H/B
MN5150H/B CH
Temperature Range
for Guaranteed No Missing Codes
8 Bits
O°C to +70°C
8 Bits
-55°C to + 125°C
8 Bits
-55°C to +125°C
8 Bits
-55°C to +125°C
Dimensions in Inches
(millimeters)
[1JJ
_
M.. rch 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-65
MN5150 HIGH·SPEED 8·Bit AID with 3·STATE BUFFER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN5150
MN5150H, MN5150H/B
Storage Temperature
+ 15V Supply (+ Vcc, Pin 16)
-15V Supply (- Vcc, Pin 13)
+ 5V Supply (+ Vdd, Pin 6)
Analog Input (Pins 11, 12)
Digital Inputs (Pins 15, 23, 24)
ORDERING INFORMATION
- 55·C to + 125·C
PART N U M B E R - - - - - - - - - MN5150H/B CH
O·Cto +70·C
-55·Cto +125·C
- 65·C to + 150·C
- 0.5 to + 18 Volts
+ 0.5 to - 18 Volts
- 0.5 to + 7 Volts
±20Volts
- 0.5 to + 5.5 Volts
Standard part is specified for O°C to +70°C
operation.
~
Add "H" for specified -55°C to +125°C
operation. _ _ _ _ _ _ _ __
Add "/B" to .. H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL·H·38534.
SPECIFICATIONS (TA = + 25°C, ± Vee = ::!: 15V, + Vdd = + 5V unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Input Voltage Ranges: Unipolar Negative
Unipolar Positive
Bipolar
Input Impedance (Note 2): 0 to - 5V, 0 to + 5V, ± 2.5V
Oto -10V,Oto +10V, ±5V
+10V
DIGITAL INPUTS (Start, Clock,
TYP.
MAX.
UNITS
Oto -5,Oto -10
oto + 5, 0 to + 10
± 2.5, ± 5, ± 10
Volts
Volts
Volts
2.5
5
10
kll
kO'
kO
0El
Logic Levels: Start, Clock: Logic
Logic
OE: Logic
Logic
"1"
"0"
"1"
"0"
+2.0
+1.5
Volts
Volts
Volts
Volts
+80
-1.6
+40
-1.6
± 10
±10
p.A
mA
p.A
mA
p.A
p.A
±V2
±Y2
LSB
LSB
+70
+125
·C
·C
+0.8
+3.5
Logic Currents: Start: Logic "1" (VIH = + 2.4V)
Logic "0" (VIL = + O.4V)
Clock: Logic "1" (VIH = + 2.4V)
Logic "0" (VIL = + O.4V)
OE: Logic "1" (VIH = + 5.0V)
Logic "0" (VIL =O.OV)
TRANSFER CHARACTERISTICS
Resolution
Temperature Range for Guaranteed No Missing Codes:
MN5150
MN5150H, MN5150H/B
Bits
8
Linearity Error: Initial (+ 25·C)
Over Temperature
±1f4
±1f4
0
-55
Full Scale Absolute Accuracy Error (Notes 4, 6):
Initial( + 25·C)
Over Temperature (Note 5)
±1h
±1
±1
±2
LSB
LSB
Unipolar Offset Error (Notes 4, 7): Initial (+ 25°C)
Over Temperature (Note 5)
±1A
±v.
± 1/2
±1
LSB
LSB
Bipolar Zero Error (Notes 4, 8): Initial (+25°C)
Over Temperature (Note 5)
± 1/",
±1fz
±1
LSB
LSB
±Yz
DIGITAL OUTPUTS (Parallel, Serial, Status)
Output Coding (Note 9): Unipolar Ranges
Bipolar Ranges
Logic Levels:
Parallel Outputs: Logic "1" Usources 1.6mAl
Logic "0" UsinkS 1.6mA)
Status, Serial Outputs: Logic "1" Usources400p.A
Logic "0" Oslnks8mAl
Leakage (Parallel Outputs) in High-Z State (Note 2)
SB
OB
+2.4
+0.4
+2.4
+0.4
±20
Volts
Volts
Volts
Volts
p.A
REFERENCE OUTPUT
Internal Reference (Note 2): Voltage
Accuracy
Tempco
External Current
6-66
+6.3
±10
±10
200
Volts
%
ppm/·C
p.A
DYNAMIC CHARACTERISTICS
MIN.
Conversion Time (Note 10)
External Clock Frequency
Clock Pulse Width (Note 2): High
Low
Setup Time Start Low to Clock (Note 2)
TYP.
MAX.
UNITS
2.5
3.2
"sec
MHz
nsec
nsec
nsec
+15.45
-15.45
+5.25
Volts
Volts
Volts
25
50
20
POWER SUPPLIES
Power Supply Range: + 15V Supply
-15V Supply
+5V Supply
+14.55
-14.55
+4.75
+15
-15
+5
Power Supply Rejection (Notes 2,3,11): + 15V Supply
-15V Supply
±0.03
±0.01
-
% FSR/%Supply
%FSR/%Supply
Current Drain: + 15V Supply
-15V Supply
+5V Supply
+12
-10
+70
+16
-18
+101
rnA
rnA
rnA
Power Consumption
680
1015
mW
SPECIFICATION NOTES:
1. Listed specifications apply for all part numbers unless specifically indicated.
2. These parameters afe listed for reference and afe not tested.
3. FSR = full scale range, and it is equal to the nominal peak·to·peak voltage of
the selected input voltage range. A unit connected for ± 10Voperation has a
20V FSR. A unit connected forOto + 10V,Oto -10Vor ±SVoperation hasa
10V FSR. A unit connected for 0 to + SV, 0 to - SV or ± 2.SV operation has a
SV FSR.
4. 1LSB for B bits in 20V FSR is 7BmV.
1LSB for B bits jn 10V FSR is 39mV.
1LSB for B bits in SV FSR is 19.5mV.
5. Listed specifications apply over the O"C to + 70"C temperature range for
standard products and over the - SS"C to + 12S"C range for "H" products.
6. Full scale absolute accuracy error Includes offset, gain, linearity. noise and
all other errors. Full scale accuracy specifications apply at positive full
scale for unipolar positive input ranges, at negative full scale for unipolar
negative input ranges and at both positive and negative full scale for bipolar
input ranges. Full scale accuracy error is defined as the difference between
the ideal and the actual input voltage at which the digital output just
changes from 11111111 to 11111110 for unipolar positive and bipolar input
ranges. Additionally it describes the accuracy of the 0000 0000 to 0000 0001
transition for unipolar negative and bipolar input ranges. The formertransition ideally occurs at an input voltage 1 LSB below the nominal positive full
scale voltage. The latter ideally occurs 1 LSB above the nominal negative
full scale voltage. See Digital Output Coding.
7. Unipolar offset error is defined as the difference between the ideal and the
actual Input voltage at which the digital output just changes from 00000000
to 00000001 when operating MNS1S0 on a unipolar postive range. The ideal
value at which this transition should occur Is + 1 LSB. When operating
MNS1S0 on a unipolar negative range, unipolar offset error is defined as the
difference between the Ideal and the actual input voltage at which the
digital output just changes from 1111 1110 to 11111111. The ideal value at
which this transition should occur is -1 LSB. See Digital Output Coding.
8. Bipolar zero error is defined as the difference between the ideal and the ac·
tual input voltage at which the digital output just changes from 01111111 to
1000 0000 when operating the MNSI50 on a bipolar range. The ideal value at
which this transition should occur is 0 Volts. See Digital Output Coding.
9. SB straight binary. OB offset binary.
10. Conversion time is defined as the width of Status (E.O.C.).
11. Power supply rejection is defined as the change in the analog input voltage
at which the 11111110to 11111111 or 0000 0000 to 0000 0001 outputtransi·
tions occur versus a change in power·supply voltage.
=
=
Specifications subject to change without notice as Micro Networks reserves
the right to make Improvements and changes in its products.
BLOCK DIAGRAM
Start Convert (24)
(21) Status (E.O.C.)
Successive
(1) Serial Output
Approximation
Register
Clock Input (23)
15V Supply (16) 0
)(MSB)
f----o (5)(41 Bit1
Bit 2
)
----0
-15V Supply (13) --
r--
High.lmpedance
State
INPUT RANGE SELECTION
Analog Input Voltage Range
Pin Connections
Oto +5V
Connect Input to Pin
Connect Pin 7 to Pin
Connect Pin 8 to Pin
Connect Pin 9 to Pin
Input Impedance (kll)
11
Ground
12
Ground
2.5
oto
+10V
11
Ground
Open
Ground
5
±2.5V
±5V
±10V
11
Ground
9,12
8,12
2.5
11
Ground
9
8
5
12
Ground
9
8
10
oto
oto
-5V
11
8,9,12
7,9,12
7,8,12
2.5
-10V
11
9
7,9
7,8
5
DIGITAL OUTPUT CODING
Analog Input Voltage Range
o to
+5V
+ 5.000
+ 4.981
+ 2.519
+ 2.500
+ 2.481
+0.019
0.000
Digital Output
Oto +10V
±2.5V
±5V
±10V
Oto -5V
Oto -10V
+ 10.000
+9.961
+5.039
+5.000
+4.961
+2.500
+2.481
+0.019
0.000
-0.019
-2.481
-2.500
+5.000
+4.961
+0.039
0.000
-0.039
-4.961
-5.000
+ 10.000
+9.922
+0.078
0.000
-0.Q78
-9.922
-10.000
0.000
-0.019
-2.481
-2.500
-2.519
-4.981
-5.000
0.000
-0.039
-4.961
-5.000
-5.039
-9.961
-10.000
+0.039
0.000
MSB
1111
1111
1000
fl(6r61t
0111
0000
0000
LSB
1111
111fl"
OOQfl"
-"
111(6"
00016"
()()()()
DIGITAL OUTPUT CODING NOTES:
1.
2.
3.
4.
S.
For unipolar input ranges, output coding is straight binary.
For bipolar input ranges, output coding is offset binary.
For 0 to + SV, 0 to - SV or ± 2.SV ranges, I LSB for 8 bits = 19.5mV.
For 0 to + 10V, 0 to -tOY or + SV input ranges, 1LSB for 8 bits = 39mV.
For ± 10V input range, 1LSB for 8 bits = 78mV.
• Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as II will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
~
6·70
EXAMPLE: For an MNS150 operating on its ±1OV Input range, the transition
from digital output 0000 0000 to 0000 0001 (or vice versa) will ideally occur at an
input voltage 01 - 9.961 volts. Subsequently, any input voltage more negative
than - 9.961 volts will give a digital outputol all "O's". The transition Irom digital
output 1000 0000 to 01111111 will ideally occur at an input 010.000 volts, and the
11111111 to 11111110 transition should occur at +9.961 volts. An input more
positive than +9.961 volts will all give all "1's".
MICRO NETWORKS
324 Clark 5t., Worcester, MA 01606 (508) 852·5400
MN5160
l1:JJ
_
MICRO NETWORKS
HIGH-SPEED
8-Bit AID CONVERTER
with LATCHED, 3-STATE OUTPUTS
DESCRIPTION
FEATURES
• Fast 2.0/Lsec
Conversion Time
• Latched, 3-State Output Buffer
• ~1/2LSB Linearity and
No Missing Codes
Over Temperature
• Adjustment-Free
No Gain or Offset
Adjustments Necessary
• Fully Specified O°C to + 700C
(MN5160) or -55OC to +125OC
(MN5160H and MN5160H/B)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
MN5160 is a high-speed, 8-bit, successive approximation AID
converter with an onboard, latched, 3-state output buffer for
easy data bus interfacing. Fast (2l'sec maximum) conversion
time, ± V2 LSB linearity, ± 1 LSB absolute accuracy and "no
missing codes" guaranteed over the entire operating
temperature range make the MN5160 an excellent choice for
industrial or military, high-speed, single or multi-channel
data acquisition systems in monitoring or automatic test
equipment. In very high-speed applications, the latched,
3-state output buffer provides a significant advantage over
unlatched AID's in that it allows valid parallel output data
from the previous conversion to be held and read during an
ongoing conversion.
MN5160 is packaged in a 24-pin, double-wide, hermetically
sealed DIP and features 5 user-selectable input ranges. The
stability of our Micro Networks laser-trimmed thin-film
resistor networks allows MN5160 to operate without external gain and offset adjustments and maintain full accuracy
and linearity over temperature.
I
Units are available and fully specified for O°C to +70°C
(MN5160) or -55°C to +125°C (MN5160H and MN5160H/B)
operation. For military/aerospace or harsh-environment
commercial/industrial applications, MN5160H/B is available with
Environmental Stress Screening, while MN5160H/B CH is
screened in accordance with MIL-H-38534. Contact factory for
availability of "CH" device types.
24 PIN DIP
Part
Number
MN5160
MN5160H
MN5160H/B
MN5160H/B CH
Temperature Range for
Guaranteed No Missing Codes
8 Bits
8 Bits
8 Bits
8 Bits
O°C to +70°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
~ 0.600 (15.24) -J
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
January 1992
Copyright 1992
Micro Networks
All rights reserved
324 Clark SI., Worcester, MA 01606 (508) 852-5400
6-71
MN5160 HIGH·SPEED 8·Bit AID CONVERTER with LATCHED 3-STATE OUTPUTS
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN5160
MN5160H, MN5160H/B
Storage Temperature Range
Positive Supply (+ Vcc, Pin 16)
Negative Supply ( - Vcc, Pin 13)
Logic Supply (+ Vdd, Pin 6)
Analog Inputs (pins 11, 12)
Digital Inputs (Pins 7,15,23,24)
-55·Cto +125·C
PART NUMBER
MN5160 HIS CH
O·C to + 70·C
-55·Cto +125·C
-65·Cto +150·C
- 0.5 to + 18 Volts
+0.5 to -18 Volts
- 0.5 to + 7 Volts
±20 Volts
- 0.5 to + 5.5 Volts
O°C to +70°C operation.
Add "H" for specified -55°C to +125°C
operation. _ _ _ _ _ __
-~.,,~~~
II
Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.
Contact factory for availability of "CH" device types.
SPECIFICATIONS (2) Bit 4
Output
:----<' (20) Bit 5
Buffer
~ (19) Bit 6
)
~-~
Ground (10)
Ground (22) 0
+6.3V Reference Output (14)
Bipolar Offset (9)
)
~
T
'---0 (18) Bit 7
r----" (17) Bit 8 (LSB)
D/A Converter
20V Input (12)
I
(7) Output Enable (OE)
(15) Latch Enable
I
Summing Junction (8)
10V Input (11)
(5) Bit 1 (MSB)
f----<:> (4) Bit 2
~Wlv'AA5~~
5kO
~
~rator
6-73
PIN DESIGNATIONS
•
24
12
13
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
Serial Output
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
+ 5V Supply ( + Vdd)
Output Enable (010)
Summing Junction
Bipolar Offset
Ground
10V Input
20V Input
24
23
22
21
20
19
18
17
16
15
14
13
Start Convert
Clock Input
Ground
Status (E.O.C.)
Bit5
Bit 6
Bit 7
Bit 8 (LSB)
+ 15V Supply (+ Vee)
Latch Enable
Reference Output (+ 6.3V)
-15V Supply (- Vee)
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-The Successive Approximation Register (SAR) is a set of flip flops (and control logic)
whose outputs act as both the direct (parallel) data outputs of
the Analog to Digital Converter (AID) and the digital drive for
the AID's internal Digital to Analog Converter (D/A). See Block
Diagram. Holding the AID's Start Convert (pin 24) low during a
clock low to high transition resets the SAR. In this state, the
output of the MSB flip flop is set to logic "0", the outputs of
the other bit flip flops are set to logic "1", and the Status output (pin 21) is set to logic "1" (See Timing Diagram). The Start
Convert must now be brought high again for the conversion
to continue. If the Start is not brought high, the converter will
remain in the reset state.
The DIA Internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The comparator output ("1" or "0") informs the SAR whether the present digital output (0111 1111 in the reset state) is "greater
than" or "less than" the analog input. Depending upon which
is greater, on the first riSing clock edge after the Start has
returned high, the SAR will set the MSB to its final state ("1"
or "0") and bring bit 2 down to a "0". The digital output is now
X0111111. The DIA converts this to an analog value, and the
comparator determines whether this value is greater or less
than the analog input. On the next rising clock edge, the SAR
reads the comparator feedback, sets bit 2 to its final value,
ahd brings bit 3 down to a logic "0". The digital output is now
XX01 1111. This successive approximation procedure continues until all the output bits are set. The rising clock edge
that sets the LSB (bit 8) also drops the Status output to a "0"
signaling that the conversion is complete. Output data is now
valid and will remain so until another conversion is started.
The clock does not have to be turned off.
As you recall, digital output bits are reset to 01111111 at the
beginning of the successive approximation conversion process and that valid parallel output data can only be read betweeh conversions. MN5160's Latch Enable (pin 15) and Output Enable (pin?) allow data from a prior conversion to be
latched and read while the next conversion is in progress. If
desired, valid output data may be latched by applying a "0" to
"1" edge to Latch Enable (pin 15). If this is done, output data
from the just completed conversion will be latched in
MN5160's 3-state output latch. Once latched, output data
may be read by bringing Output Enable (OE, pin?) low. Output
data will be valid 50nsec maximum after Output Enable is
low. Output data bits are returned to the high-impedance
state by bringing Output Enable high.
6-74
LAYOUT CONSIDERATIONS- Proper attention to layout and
decoupling is necessary to obtain specified accuracies from
the MN5160. The unit's two ground pins (pins 10 and 22) are
not connected internally. They should be tied together as
close to the package as possible and connected to system
analog ground, preferably through a large ground plane
underneath the package. If the grounds cannot be tied
together and must be run separately, a non-polarized 0.01JLF
bypass capacitor should be connected between pins 10 and
22 as close to the unit as possible and wide conductor runs
employed.
Power supplies should be decoupled with tantalum or electrolytic type capacitors located close to the converters. For
optimum performance and noise rejection, 1JLF capacitors
paralleled with 0.01JLF ceramic capacitors should be used as
shown in the diagrams below.
Pin 16
C
1,F
Pins 10. 22
I
T
I
+ 15V
TO.Q1,F
c----4I--I~Ground
1,F
Pin 13 c
T
Pin 6
I
0
1,F
Pins 10, 22
I
+5V
T O.Q1,F
-I.I----L..Ground
0>-0
T°.Q1,F
-
15V
POWER SUPPLY DECOUPLING
CONTINUOUS CONVERTING-The MN5160 AID converters
can be made to continuously convert by tying the Status output (pin 21) to the Start Convert input (pin 24). In this configuration, Status (Start Convert) will go low at the end of a
conversion (see Timing Diagram) and the next riSing clock
edge will reset the converter bringing Status (Start Convert)
high again. The MSB will be set on the next rising clock edge.
The result is that the Status will go low for approximately one
clock period following each conversion. Please read the section describing the Status output.
STATUS OUTPUT - The Status or End Of Conversion (E.O.C.,
pin 21) output will be set to a logic "1" when the converter is
reset; will remain high during conversion; and will drop to a
logiC "0" when conversion is complete. Due to propagation
delays, the least significant bit (LSB) of a given conversion
may not be valid until a maximum of 1OOnsec after Status has
returned low. Therefore, an adequate delay must be provided
if Status is to be used to strobe latches to hold output data.
Simple gate delays can be employed or the Status can be
made the input of a 0 flip flop whose clock input is the same
as the converter clock. In this situation, the Q output will
change one clock period after Status changes.
TIMING DIAGRAM
Clock
Start Convert
MSB
Bit 2
Bit 3
Bil4
Bit 5
Bit 6
Bit 7
LSB
/TIIII/IIT/i1
ZZZLllZZllllJ
TIlll.lil.LI!lJ
ZZZLZllllZllJ
o
o
llilllllllll:J
ZZZZZZZllZllJ
llllllllllllJ
77llZZ11.tlZZI
o
o
STATUS
MSB
Serial Output
Bit 2
TIMING DIAGRAM NOTES:
1. Operation shown is for the digital word 1101 0001 which corresponds to
8.164V on the 0 to + tOV input range. See Output Coding.
2. Conversion Time is defined as the width of the Status (E.O.CJ pulse.
3. The converter is reset (MSB ="0", all other bits ="1", Status ="1") by
holding the Start Convert low during a low to high clock transition. The Start
Convert must be low for a minimum of 20nsec prior to the clock transition.
Holding the Start low will hold the converter in the reset state. Actual can·
version will begin on the next rising clock edge after Start has returned high.
4. The delay between the resetting clock edge and Status actually rising to a
"1" is SOnsec maximum.
5. The Start Convert may be brought low at any time during a conversion to
reset and begin converting again.
6. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequent failing clock edges, and these
edges can be used to clock serial data Into receiving registers.
OUTPUT ENABLE-Output Enable (OE, pin 7l controls the
state of the parallel outputs. When a conversion is complete,
valid parallel output data may be enabled by bringing Output
Enable low. Data will be available 50nsec maximum after
Output Enable is low. Output data is returned to the highimpedance state by bringing Output Enable high. See
diagram below.
Status
~
-----.l
__....Jr
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
7. Output data will be valid 100nsec(maxlmum)aftertheStatus (E.O.CJoutput
has returned low. Parallel output data will remain valid and the Status out·
put low until another conversion is initiated.
8. Parallel output data can be latched at the end of a conversion by a "0" to "1"
edge applied to LatctJ Enable (pin 15).
_
9. Parallel output data can be enabled by bringing Output Enable (OE., pin 7)
low. Parallel output bits can be returned to the high impedance state by set·
ting Output Enable high.
10. For continuous conversion, connect the Status output (pin 21) to the Start
Convert Input (pin 24). See section on Continuous Conversion.
11. When the converter Is initially "powered up", It may come on at any point in
the conversion cycle.
LATCH ENABLE-Valid parallel output data can be latched
in MN5160's output buffer by the rising edge ("0" to "1" tran·
sition) of Latch Enable input (pin 15). When continuously con·
verting, data from the previous conversion can be latched
and read during a subsequent conversion. The Status (E.O.C.)
output can be NORed with the converter clock, as shown
below, to produce a positive strobe pulse V. period wide, V.
period after the Status output has gone low. The rising edge
of this pulse can be used to latch data after each conversion.
Once latched, output data can be enabled and read by bringing Output Enable (O'!:, pin 7llow.
Output Enable ----------------,~
Parallel
Output
Data
High.lmpedance
-----=-,,-:-------c==>---State
6-75
II
.
-:,
LATCHING DATA CONTINUOUS CONVERSIONS
Clock O-.-----i (23)
MNS160
'LSUlSL
LJ
---,nL____
Clock (pin 23)
Status (pin 21)
~
Conversion N
Latch Enable (pin lS)
~1--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Latched Parallel Data
~_ _ _ _ _ _ _ _c.:.o.:.n.:.v..:e.:.rs.:.io.:.n.:..:.N_.l_ _ _ _ _ _ _
--lX
Conversion N
INPUT RANGE SELECTION
Connecl
Analog Input Voltage Range
010 +10V
±2.5V
010 +5V
Input to Pin
Pin 8 to Pin
Pin 9 to Pin
Input Impedance
11
12
Ground
2.5kfl
11
Open
Ground
5kfl
11
12,9
8
2.5kfl
±5V
±10V
11
9
8
5kfl
12
9
8
10k!)
DIGITAL OUTPUT CODING
Analog Input Voltage Range
o to +5V
Oto +10V
±2.5V
±5V
±10V
+ 5.000
+ 4.981
+ 2.519
+ 2.500
+ 2.481
.·0.019
0.000
+ 10.000
+2.500
+2.481
+0.019
0.000
-0.019
-2.481
-2.500
+ 5.000
+ 10.000
+9.922
+0.078
0.000
- 0.078
-9.922
-10.000
+9.961
+ 5.039
+ 5.000
+4.961
+0.039
0.000
+4.961
+ 0.039
0.000
-0.039
-4.961
-5.000
Digital Output
MSB
LSB
1111
1111
1000
1111
1118'
0008'
~
NrM!'
0111
0000
0000
111~'
00011'
0000
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is straight binary.
2.
3.
4.
S.
For bipolar input ranges, output coding is offset binary.
Fora to +SVor ±2.SV Input ranges, lLSB for 8 bits= 19.5mV.
For a to + 10V or ± SV input ranges, lLSB for 8 bits = 39mV.
For ±10V input range, lLSBfor8bits=78mV.
'Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as ~ will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
6-76
EXAMPLE: For an MNS160 operating on its ± 10V input range, the transition
from digital output 0000 0000 to 0000 0001 (or vice versa) will ideally occur at an
input voltage of - 9.961 volts. Subsequently, any input voltage more negative
than -9.961 volts will give a digital output of all "a's". The transition from
digital output 1000 0000 to 0111 1111 will ideally occur at an input of - 0.039
volts, and the 11111111 to 11111110transltion should occurat + 9.883 volts. An
input more positive than +9.883 volts will give all "1's."
l1JJ
_
MN5200 Series
50p.sec, 12-Bit
MILITARY
AID CONVERTERS
MICRO NETWDRKS
DESCRIPTION
-FEATURES
MN5200 Series devices are 12-bit, successive approximation
• 50/Lsec Maximum
Conversion Time
• ±1/2LSB Linearity and
No Missing Codes
Guaranteed Over Temperature
• Small 24-Pin DIP
• ±1LSB Zero Error
• ±2LSB Absolute Accuracy
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
AID converters in industry-standard, 24-pin, dual-in-line
packages. Functional laser trimming of our own nichrome
thin-film resistor networks results in adjustment-free devices
that are extremely accurate and highly stable.
Zero error, for example, is guaranteed to be better than
± 0.025% FSR ( ± 1 LSB) at + 25°C and better than ± 0.05%
FSR (± 2 LSB) over the entire operating temperature range.
All uni~s are fully specified and 100% tested for linearity and
accuracy at their operating temperature extremes as well as
at room temperature.
These AID converters are available in a number of input
voltage ranges. For each range, the user has the option of
specifying a model complete with internal reference or, for
improved overall accuracy, a model which uses an external
reference. In all cases, ± 112LSB linearity and 12-bit "no
missing codes" are guaranteed over the entire operating
temperature range.
I
All models of the MN5200 Series may be procured for operation over the full -55°C to + 125°C military temperature
range ("H" models) or the O°C to +70°C commercial
temperature range. For military/aerospace or harshenvironment commercial/industrial applications "HIS CH"
models are fully screened to MIL-H-38534 in Micro Networks
MIL-STD-1772 qualified facility.
The MN5200 Series (50/Lsec conversion time) and MN5210
Series (13/Lsec conversion time) are the industry's most
widely accepted 12-bit AID's for military/aerospace applications. These devices are presently designed into more than
50 military/aerospace programs. Their small size, low power
consumption and adjustment-free operation make them excellent selections for compact, highly reliable systems. New
applications will be found wherever size, speed, power and
temperature considerations are paramount.
O::JJ
_
MICRO NETWORKS
January 1992
Copyright 1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-77
MNS200 SERIES SOp'sec 12-Blt MILITARY AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Storage Temperature
Positive Supply (Pin 15)
Negative Supply (Pin 13)
Logic Supply (Pin 2)
Analog Input (Pin 14)
Digital Inputs (Pins 1, 24)
Digital Outputs
Rei. Input (MN5203, 04, 05)
O·C to +70·C
-55·C to +125·C ("H" Models)
-65·C to +150·C
+18 Volts
-18 Volts
-0.5 to +7 Volts
125 Volts
-0.5 to +5.5 Volts
Logic Supply
oto -15 Volts
ORDERING INFORMATION
PART NUMBER
MN520X HIB CH
Select Model Number (MN5200, MN5201 etc.)------.J
Standard part is specified for O·C to +70·C
operation.
Add "H" for specified -55·C to + 125·C
operation. _ _ _ _ _ _ _ _ _ _ _ _ _-1
Add "/B" to "H" mOdels for
Environmental Stress Screening. _ _ _ _ _ _ _- J
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.------J
SPECIFICATIONS (T A = +25°C, Supply Voltages ± 15V and ±5V, lor Ext. Ref. Models VRef = -10.000V, unless otherwise specified).
ANALOG INPUTS
Input Range (Input Impedance) (Note 1):
oto -10V (5KIl)
-5V to +5V (5KIl)
-10V to + 10V (10KIl)
oto + 10V (5KIl)
TRANSFER CHARACTERISTICS
Linearity Error (Notes 2,3): +25°C
OOCto +70°C
-55°C to + 125°C ("H" Models)
Differential Linearity Error
No Missing Codes
Full Scale Absolute Accuracy Error (Notes 4, 5)
+25°C
O°C to +70°C
-55°C to + 125°C ("H" Models)
Zero Error (Notes 4, 5): +25°C
OOCto +70°C
-55°C to + 125°C ("H" Models)
Gain Error (Note 5)
Gain Drift
Conversion Time (Note 6)
POWER SUPPLIES
Power Supply Range: ± 15V Supplies
+5V Supply
Power Supply Rejection (Note 7): + 15V Supply
-15V Supply
Current Drain: +15V Supply
-15V Supply
+5V Supply
-10V Reference (MN5203, 04, 05)
DIGITAL INPUTS (ALL UNITS)
Logic Levels: Logic "I"
Logic "0"
Clock Input (Note 8): Pulse Width High
Pulse Width Low
Loading High (V," =2.4V)
Loading Low (V," =0.3V)
Frequency (Note 6)
Start Convert Input: Loading High (V," =2.4V)
Loading Low (V," =0.3V)
Setup Time Start Low to Clock (Note 9)
DIGITAL OUTPUTS (ALL UNITS)
Logic Coding (Note 10): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "I"
Logic "0"
Output Drive Capability, All Outputs (Note 11): Logic "I"
Logic "0"
REFERENCE INPUT/OUTPUT (Note 12)
Internal Reference: Voltage
Accuracy
Tempeo 01 Drift
Max. External Current (Without Bulfering)
External Reference: Voltage
Loading
6-78
MODEL NUMBER
(External Ref.)
MN5203
MN5204
MN5205
MODEL NUMBER
(Internal Ref.)
MN5200
MN5201
MN5202
MN5206
TYP.
MAX.
+V,
+ ';'
tV,
+'12
± 0.25
± 0.2
±O.o1
± 0.025
TYP.
+v.
tV,
tV,
+ ';'
MAX.
± ';'
+';'
UNITS
LSB
LSB
LSB
LSB
± 0.05
± 0.1
± 0.1
+ 0.025
-± 0.05
± 0.05
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%
ppm/oC
,"Sec
tV,
+';'
Guaranteed Over Temperature
± 0.05
± 0.025
± 0.05
± 0.4
± 0.4
± 0.025
± 0.05
+ 0.05
±O.o1
± 0.025
± 0.025
+ 10
± 0.025
± 3
50
± 0.005
± 0.01
23
-25
25
MIN.
2.0
50
±3
+ 5
± 0.02
± 0.05
28
-35
42
± 0.005
± 0.005
23
-25
25
-1.5
TYP.
± 3
+ 5
± 0.02
± 0.02
28
-35
42
-2
MAX.
0.7
125
175
2
-0.25
4
-0.25
20
-0.4
240
40
-0.4
25
Complementary Straight Binary
Complementary Offset Binary
2.4
3.6
0.15
0.3
8
2
-6.3
±2
±5
100
-10.000
-2
%
%
%FSR/%Vs
%FSR/%Vs
mA
mA
mA
mA
UNITS
Volts
Volts
nSec
nSec
~
mA
KHz
~
mA
nSec
Volts
Volts
TTL Loads
TTL Loads
Volts
%
ppm/DC
~
Volts
mA
Micro Networks guarantees linearity and Absolute Accuracy at and
below this clock frequency.
7. Micro Networks tests and guarantees Power Supply AeJection over the
:t.15V :t.3% range.
SPECIFICATION NOTES:
1. Consult lactory for other available Input voltage ranges.
2. Micro Networks tests and guarantees maximum linearity error at room
temperature and at both the high and low extremes of the specified
operating temperature range.
8. The clock may be asymmetrical with minimum positive or negative pulse
width. See Note 6.
9. In order to reset the converter, STAAT CONVEAT must be brought low
at least 25 nSec prior to a lowto high clock transition. See Timing Diagram.
10. CSB =Complementary Straight Binary
COB = Complementary Offset Binary
3. 1 LSB for a 12 bit converter corresponds to 0.024%FSR. See Note 4.
4. FSA stands for Full Scale Aange and is equal to the peak to peak voltage
of the selected input range. For the ±10V Input range. FSR is 20 volts, and
1 LSB'is equal to 4.88 mV. For the 0 to +10V, 0 to -10V, and ±5V ranges,
FSA is 10 volts, and 1 LSB is equal to 2.44 mV.
Serial and parallel output data have the sarne coding. Serial data is in Non-
5. See Absolute Accuracy section below for an explanation of how Micro
Networks tests and specifies Full Scale Absolute Accuracy, Gain, and
Zero Errors.
Aeturn to Zero (NAZ) format. See Output Coding and Timing Diagram.
11. One TTL load is defined as sinking 40 ~A with a logic "" applied and
sourcing 1.6 rnA with a logic "0" applied.
12. MN5200, MN5201, MN5202, and MN5206 have an internal-6.3V reference.
MN5203, MN5204, and MN5205 require an external-l0.000V reference.
6. ConverSion Time is defined as the width of the converter's STATUS
(E.O.C.) pulse. See Timing Diagram. For the MN5200 Series, a 50
~Sec
conversion time corresponds to an external clock frequency of 240 kHz.
BLOCK DIAGRAM
Start Convert (1)
PIN DESIGNATIONS
SUCCESSIVE
APPROXIMATION
REGISTER
Clock Input (24)
I
(22) Status Out
Serial Out
h~ (3)
(9)
- (8)
+15V Supply(15) ~
-15V Supply (13) ~
+5V Supply
(2) ~
Ground
(11) ~
Ground
(23) ~
(7)
(6)
(5)
(4)
(21)
(20)
(19)
(18)
(17)
(16)
Ref. In/Out (12)
(See Note 12 Abov e)
D/A CONVERTER
I
Analog
Input (14)
R'N
(MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
(LSB)
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
'---
{>
COMPARATOR
ABSOLUTE ACCURACY ERROR
•
24
12
13
PIN 1
Start Convert
+5V Supply
Serial Output
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
N/C
Ground
Ref. Out (-6.3V)
Ref. In (-10.0V)
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
24 Clock Input
23 Ground
22 Status (E.O.C.)
21 Bit 7
20 Bit 8
19 Bit 9
18 Bit 10
17 Bit 11
16 Bit 12 (LSB)
15 +15V Supply
14 Analog Input
13 -15V Supply
DIGITAL
OUTPUT
0000 0000 0000
A given digital output code is valid for a band of analog input
voltages that is ideally 1 lSB wide. This is demonstrated in
the next column and on the following page where portions of
the theoretical analog input/digital outputtransfer functions
of the MN5206 (0 to +10V input range) and the MN5202 (±10V
input range) are sketched.
Notice that, for the MN5206, any analog input between
+0.00244 volts (1lSB = 2.44 mY) and +0.00488 volts will give a
digital output of 11111111 1110. If we assign this code to the
nominal midrange of the analog input band for which it is
valid, we can say that the 1111 1111 1110 digital code
corresponds to analog inputs of +3,66 mV ±1.22 mV which
can be written as +3.66 mV ±1/2 lSB. The ±1/2 lSB is a
quantization uncertainty unavoidable in AID conversion. It is
referred to as I nherent Quantization Error and its magnitude
can be reduced onJy by gOing to higher resolution converters,
1
0000 0000 000 1
0000 0000 0010
OIIIIII'I"'j
1000 0000 0000
/
111111111101~/
111111111110
1111 1111 1111
-
~
o
§
d
~
~
~
~
~
M
g. g. §d
);......'----<'~_+_ll>-I+---+-----<--+-~. ANALOG
~ 6 ;: § ~ ~ 6
INPUT
~
80 v _ ~ ~, 0
m
~
0
~
8
~
mmm§
~
~
~
d
+
MN5206 TRANSFER FUNCTION
6-79
I
0000 0000 0000
0000 0000 0001
0000 0000 0010
DIGITAL
OUTPUT
> > > > ...
> >
8 ~'" '" '"'"'" § ~
"! '"
"1
~ o
IX>
0
011111111110
011111111111
~
I
*
'" '" '"
1000 0000 0000
0
,
111111111101
111111111110
<----
,,
,,
......
> > > > > >
18
...
1000 0000 0001
111111111111
1
0
----+
,
,,
'"U;
'" ~ '"~ '""1 "!~
~
'"+ + '"+ +"
0
IX>
"! "! "1
0
I
0
0
These Absolute Accuracy Error specifications are summarized in the two plots below. The ideal transfer function is now
sketched as a broken line. We guarantee, for the MN5206H,
that the actual transfer function will be ±1/2 LSB linear and
that all the transition voltages will fall within the boundaries
indicated by the solid lines at +25°C and at -55°C and
+125°C.
DIGITAL
OUTPUT
0000 0000 0000 TO
0000 0000 0001
TRANSITION
/
/
/
/
MN5202 TRANSFER FUNCTION
It is difficult and time consuming to measure the center of a
quantization level (the +0.00366 volts in this example). The
only points along an AID converter's analog input/digital
output transfer function that can quickly and accurately be
detected and measured are the transition voltages, the
voltages at which the digital outputs change from one code
to the next. The Absolute Accuracy Error of a voltage input
AID converter is the difference between the actual, unadjusted, analog input voltage at which a given digital
transition occurs and the analog input voltage at which that
transition is ideally supposed to occur. This difference is
usually expressed in LSB's or %FSR (see Note 4 above).
Absolute Accuracy Error includes gain, offset, linearity, and
noise errors, and when specified over temperature, encompasses the individual drifts of these errors.
For the MN5200 Series AID converters, Micro Networks tests
Absolute Accuracy Error at both endpoints of unipolar input
ranges and at both endpoints and the midpoint of bipolar
input ranges. These tests are performed at room temperature
and at both the high and low extremes of the specified
operating temperature range. The specifications appear in
the table as the Full Scale Absolute Accuracy and Zero
Errors.
EXAMPLE MN5206: Return to the ideal analog input/digital
output transfer function of the MN5206 sketched on page 3.
Notice that the digital output data changes from 1111 1111
1111 to 1111 1111 1110 when the input voltage increases
from OV to +2.44 mV. It changes from 1111 1111 1110 back to
1111 1111 1111 as the input voltage is decreased from some
more positive voltage to +2.44 mV. This voltage, +2.44 mV is
the zero transition voltage. It is the voltage at which the LSB
changes from a "1" to a "0" or vice versa while all other bits
remain "1'. The positive full scale LSB transition voltage, the
voltage at which the LSB changes while the other bits remain
"0", is ideally +9.9976V.
For the MN5206H (0 to +10V input range, -55°C to +125°C
operation), Micro Networks tests linearity and the accuracy
of the two transition voltages just discussed at -55° C, +25° C,
and +125°C. We guarantee that the transfer function will be
±1/2 LSB linear at all temperatures and that the zero
transition will be within ±0.025%FSR (±2.5 mV) of its ideal
value (+2.44 mV) at +25° C and within ±0.05%FSR (±5 mV) of its
ideal value at -55°C and at +125°C. This is our Zero Error
specification. We guarantee that the positive full scale LSB
transition voltage will be within ±0.05%FSR (±5 mV) of its
ideal value (+9.9976V) at +25°C and within ±0.4%FSR (±40
mV) of its ideal value at -55°C and +125°C. This is our Full
Scale Absolute Acuracy Error specificatiol).
6-80
111111111111TO
111111111110
TRANSITION ~~------------~~----~ANALOG
~ G;
~
INPUT
ov
C\lr--N
ro ro
8l8l~
88
~:~
06
MN5206 ABSOLUTE ACCURACY +25°C
DIGITAL
OUTPUT
0000 0000 0000 TO
0000 0000 0001
TRANSITION
/
/
/
/
/
/
/
111111111111TO
111111111110
TRANSITION -fI:~'-----------,~---:!c----~ANALOG
~~~
~
~ INPUT
ggg
cicici
~
a)
ro
m
tri
~
+"
0
MN5206H ABSOLUTE ACCURACY -55°C AND +125°C
EXAMPLE MN5202: Return to the ideal analog input/digital
output transfer function of the MN5202 sketched above.
Notice that the digital output data changes from 1111 1111
1111 to 1111 1111 1110 when the input voltage increases
from -10.000V to -9.9951V.1t changes from 111111111110
back to 1111 1111 1111 as the input voltage is dlJcreased
from some more positive voltage to -9.9951V. This voltage,
-9.9951V, is the negative full scale LSB transition voltage. It is
the voltage at which the LSB changes from a ''1'' to a "0" or
vice versa while all other bits remain ''1''. The 100000000000
to 0111 1111 1111 transition (called the "major transition"
because all the bits change) ideally occurs at the zero volt
analog input. The positive full scale LSB transition voltage,
the voltage at which the LSB changes while the other bits
remain "0", is ideally +9.9951V.
For the MN5202H (±10V input range, -55°C to +125°C
operation), Micro Networks tests linearity and the accuracy
of the three transition voltages just discussed at -55°C,
+25° C, and +125° C. We guarantee that the transfer function
will be ±112 LSB linear at all temperatures and that the
positive and negative full scale LSB transition voltages will
be within ±0.05%FSR (±10 mV) of their ideal values (+9.9951V
and -9.9951V) at +25°C and within ±0.4%FSR (±SO mV) of
their ideal values at -55°C and +125°C. This is our Full Scale
DIGITAL
OUTPUT
Absolute Accuracy Error specification. We also guarantee
that the major transition voltage will be within ±O.025%FSR
(±5 mY) of its ideal value (zero volts) at +25°C and within
±0.05%FSR (±10 mY) of its ideal value over the entire -55°C
to +125°C operating temperature range. This is our Zero
Error specification.
0000 0000 0000 TO
0000 0000 0001
TRANSITION
>
0)
>
>
>
Ci
en
"0
<0
<0
en
0)
/
ANALOG
INPUT
<0
¥
/
111111111111 TO
111111111110
TRANSITION
MNS202H ABSOLUTE ACCURACY -55°C AND +12SoC
/
/
/
/
c:iaiai
....--.;.'..;'>-.+-'----~~~72"'"'~=....,>----+ANALOG
INPUT
/
aja.ici
+ + +
/
/
/
111111111111 TO
111111111110
TRANSITION
/
<0
a;
0)
/
/
»>
~~~
>
<0
en
en
~
These Absolute Accuracy Error specifications are summarized in the two plots below. The ideal transfer function is now
sketched as a broken line. We guarantee, for the MN5202H,
that the actual transfer function will be ±1/2 LSB linear and
that all the transition voltages will fall within the boundaries
indicated by the solid lines at +25°C and at -55°C and
+125°C.
DIGITAL
OUTPUT
0000 0000 0000 TO
0000 0000 0001
TRANSITION
>
<0
"0
/
/
/
Because Micro Networks tests and guarantees ±1/2 LSB
linearity at all temperatures, the Absolute Accuracy of any
transition voltage can be interpolated from the Full Scale
Absolute Accuracy and Zero Error specifications. Example:
at +25° C, the 100000000000 to 0111 1111 1111 transition of
the MN5206 will occur within ±0.0375%FSR (±3.75 mY) of its
ideal value (+5.000V). For temperatures intermediate to
+25°C and -55°C or +125°C, maximum Full Scale Absolute
Accuracy and Zero Errors can also be interpolated. At
+75° C, for example, Full Scale Absolute Accuracy Error will
be ±0.225%FSR.
We have not specified Unipolar and Bipolar Offset Errors for
the MN5200 Series. We feel that Offset is a confusing
MN5202 ABSOLUTE ACCURACY +2SoC
TIMING DIAGRAM
MSB mmzzzzZ/l
h
Bit2wmmm
~"1---------------------------------------------------
Bit 3 WI/l/I/IIA
o
Bit 41/zmzzllZ/l
L-.Jl
Bit 51/o/IIllIO,
a
BltSmZmZma
o
Bit 71/l/lllll7l/l
L-.Jl
Bit 8 '1l1l1!!111/l
Bit 9 ZWIIIlIZIA
~r.l--------------------------
o
Bit 10 zmm?WJJ
Bit 11
wvwm
0
LSB~71~/:V~z:~~/:a~A~__~========~~_~====~____~========~__~====~~====~~1=======::
Status _
Serial Out -----------11~=-_::-:-:_~L...,__-=_-1---1~
MSB
Bit 2
Bit 3
Bit 4 Bit 5
Bit S Bit 7
Bit 8 Bit 9 Bit 10 Bit 11
LSB
TIMING DIAGRAM NOTES:
1. Operation shown is for the digital word 1101 0011 0101 which corresponds to 1.7432V on the 0 to +10V input range (MN5206). See Output
Coding.
2. Conversion time is defined as the width of the STATUS (E.O.C.) pulse.
3. The converter is reset (MSs • "0", all other bits· "1", STATUS· "1") by
holding the START CONVERT low during a low to high clock transition.
The START CONVERT must be low for a minimum of 25 nSec prior to the
clock transition. Holding the START low will hold the converter In the
reset state. Actual conversion will begin on the next rising clock edge
after the START has returned high.
4. The delay between the resetting clock edge and STATUS actually rising
to a "1" is 120 nSec maximum.
5. The START CONVERT may be brought low at any time during a conver·
sion to reset and begin converting again.
6. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequent falling clock edges, and these
edges can be used to clock serial data into receiving registers.
7. Output data will be valid 30 nSec (maximum) after the STATUS (E.O.C.)
output has returned low. Parallel output data will remain valid and the
STATUS output low until another conversion is initiated.
8. For continuous conversion, connect the STATUS output (Pin 22) to the
START CONVERT input (Pin 1). See section on Continuous Conversion.
9. When the converter Is initially "powered up", it may come on at any point
in the conversion cycle.
6·81
I
DESCRIPTION OF OPERATION-The Successive Approximation Register (SAR) is a set of flip flops (and control logic)
whose outputs act as both the direct (parallel) data outputs
of the Analog to Digital Converter (AID) and the digital drive
for the AID's internal Digital to Analog Converter (D/A). See
Block Diagram. Holding the AID's START CONVERT (Pin 1)
low during a clock low to high transition resets the SAR. In
this state, the output of the MSB flip flop is set to logic "0", the
outputs of the other bit flip flops are set to logic "1", and the
STATUS output (Pin 22) is set to logic "1" (see Timing
Diagram). The START CONVERT must now be brought high
again for the conversion to continue. If the START is not
brought high, the converter will remain in the reset state.
specification and choose not to use it. Offset Errors for the
MN5200 Series will always be equivalent to either our Full
Scale Absolute Accuracy or Zero Errors and we prefer these
specifications because of their simplicity. Be sure you clearly
understand each manufacturer's converter specification definitions before you compare converters solely on a data sheet
basis.
GAIN ERROR-Gain Error is the difference between the
ideal and the measured values of a converter's Full Scale
Range (minus 2 LSB); it is a measure of the slope of the
. converter's transfer function. Gain Error is not a type of
Absolute Accuracy Error, but it can be calculated using two
Absolute Accuracy Error measurements. It is equivalent to
the Absolute Accuracy Error measured for the 0000 0000
0000 to 0000 0000 0001 transition minus that measured for
the 1111 1111 1111 to 1111 1111 1110 transition.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The
comparator output ("1" or "0") informs the SAR whether the
present digital output (0111'1111 1111 in the reset state) is
"greater than" or "Iess than" the analog input. Depending
upon which is greater, on the first rising clock edge after the
START has returned high, the SAR will set the MSB to its final
state ("1" or "0") and bring bit 2 down to a "0". The digital
output is now X011 1111 1111. The DIA converts this to an
analog value, and the comparator determines whether this
value is greater or less than the analog input. On the next
rising clock edge, the SAR reads the comparator feedback,
sets bit 2 to its final value, and brings bit 3 down to a logic "0".
The digital output is now XX01 1111 1111. This successive
approximation procedure continues until all the output bits
are set. The rising clock edge that sets the LSB (bit 12) also
drops the STATUS OUTPUT to a "0" signaling that the
conversion is complete. Output data is now valid and will
remain so until another conversion is started. The clock does
not have to be turned off.
See the Converter Tutorial Section of the Micro Networks'
Applications Manual and Product Guide for a complete
discussion of converter specifications.
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN5200 Series converters. The units' two GROUND
pins (Pins 11 and 23) are not connected internally. They
should be tied together as close to the package as possible
and connected to system analog ground, preferably through
a large ground plane underneath the package. If the grounds
cannot be tied together and must be run separately, a nonpolarized 0.011'F bypass capaCitor should be connected
between Pins 11 and 23 as close to the unit as possible and
wide conductor runs employed.
Power supplies should be decoupled with tantalum or
electrolytic capaCitors located close to the converters. For
optimum performance and noise rejection, 11'F capacitors
paralleled with 0.011'F ceramic capaCitors should be used as
shown in the diagrams below.
CONTINUOUS CONVERTING - The MN5200 Series AID
converters can be made to continuously convert by tying the
STATUS output (Pin 22) to the START CONVERT input (Pin
1).In this configuration, STATUS (START CONVERT) will go
low at the end of a conversion (see Timing Diagram) and the
next rising clock edge will reset the converter bringing
STATUS (START CONVERT) high again. The MSB will be set
on the next rising clock edge. The result is that the STATUS
will go low for approximately one clock period following
each conversion. Please read the section describing the
STATUS output. See below for continuous conversions while
short cycling.
Pin 15 0 r
r
+15V
Pin 20 r
r
+5V
11'Fr
T O.01 ,..F
1~
TO.01I'F
Pin 11,230-'--tr--rt-GrOUnd
Pin 11, 23 ....
0 -T.1..--'--GrOUnd
11'F T
T0.D1I'F
Pin 130 -15V
POWER SUPPLY DECOUPLING
DIGITAL OUTPUT CODING
DIGITAL OUTPUT
ANALOG INPUT
MN52oo, 5203
O.OOOOV
- 0.0024V
- 4.9976V
- 5.0000V
- 5.0024V
- 9.9976V
-10.0000V
MN5201, 5204
+5.ooooV
+4.9976V
+O.OO204V
O.OOOOV
-0.OO24V
-4.9976V
- 5.0000V
MN5202, 5205
+10.0OO0V
+ 9.9951V
+ 0.0049V
O.OOODV
- 0.0049V
- 9.9951V
-10.0000V
MN5206
+10.0000V
+ 9.9976V
+ 5.0024V
+ 5.0000V
+ 4.9976V
+ 0.0024V
O.OOOOV
" Vollages given are Ihelheorellcal values forlhe Iransilionslndicaled. Ideally,
wllh Ihe converter conllnuously converting, Ihe output bits Indicated as. will
change from "1" 10 ''0'' or vlea versa as the Inpul voltage p&888IIlhrough Ihe
levellndlcaled. See Ihe &ecllon on Absolute Accuracy Errorfor an explanallon
of Oulpul Transilion Voltage•.
EXAMPLE: For an MN5202I05 (±10Vanalog Inpul range) Ihelranailion from
6-82
LSB
MSB
0000 0000 0000
0000 0000 0000"
011111111110"
0000 0000 0000"
100000000000"
1111 1111 1110"
111111111111
dlgllal oulpul 0000 0000 0000 10 0000 0000 0001 (or vice versa) will ideally
occur al an Inpul vollage of +9.9951 volls. Subsequenlly, any Inpul vollage
more posilive Ihan +9.9951 volls will give a dlgllal oulpul of all "O's". The
lransilion from digital oulpul 1000 0000 0000 10 0111 1111 1111 will ideally occur
alan Inpul of zero volls, and Ihe 11111111111110111111111110 Irensilion should
occural-9.9951 volts. An Inpulmore negativelhan-9.9951 vollswlllglveall"1·s".
SHORT CYCLING-For applications requiring less than 12
bits resolution, the MN5200 Series AID's can be truncated or
short cycled to the desired number of bits with a proportionate
decrease in conversion time. The following circuit may be
used to truncate at n bits.
ClOCKO------r------
STATUS
STATUS OUTPUT-The STATUS or END OF CONVERSION
(E.O.C.) output will be set to a logic "1" when the converter is
reset; will remain high during conversion; and will drop to a
logic "0" when conversion is complete. Due to propagation
delays, the least significant bit (LSB) of a given conversion
may not be valid until a maximum of 30 nSec after STATUS
has returned low. Therefore, an adequate delay must be
provided if STATUS is to be used to strobe latches to hold
output data. Simple gate delays can be employed or the
STATUS can be made the input of a D flip flop whose clock
input is the same as the converter clock (see sketch). In this
situation, the Q output will change one clock period after
STATUS changes.
STATUS
START
CONVERT
STROBE
7474
SHORT CYCLING SINGLE CONVERSIONS
ClK
Assuming a conversion is already in progress, bit (n+1) will
go low as bit n is being set (see Timing Diagram). Since the
START CONVERT signal is high at this time, STATUS (the
output of IC2) will go low gating off the clock at IC3 ending
the conversion. To begin a new conversion, START CONVERT is brought low driving STATUS high and gating on the
clock. The first rising clock edge the converter sees with
START CONVERT low will reset the converter bringing bit
(n+1) high again. Now STATUS will remain high as START
CONVERT is brought back high allowing the conversion to
continue. Therefore, in this configuration, STATUS and
START CONVERT function normally, i.e., the same as
STATUS and START CONVERT for a converter not being
short cycled.
SHORT CYCLING AND CONTINUOUS CONVERTING-A
previous section described how continuous converting for
12 bits could be accomplished by simply tying the STATUS
output back to the START CONVERT input. To continuously
convert at n bits, one simply has to tie the bit (n+1) output
back to the START CONVERT input. The bit (n+1) output
acts like a STATUS when one short cycles at n bits. It goes
high when the converter is resElt, remains a "1" during the
conversion, and drops to a "0" as bit n is being set. Since it is
possible for the converter to come on in any state at poweron, a lock-up condition may occur if bit (n+1) comes on as a
"1" and the conversion process comes on at bit (n+2). This
situation can be avoided by making the START CONVERT
input the AND function of bit (n+1) and the STATUS output.
a
STROBE
CLOCK
CLOCK
I
I
I
I
I
,
I
I
I
I
SLJ1.JUl.JlJ"U~
START~'
JJ
I
I
"r---------lls------;
~
STATUS ----.J
I~
Q---7-~
Il
I
Q ---'--',
I
:L'i
L -_ _ _ _~I,~'---~~
If continuously converting the STATUS (E.O.C.) output can
be NORed with the converter clock, as shown below, to
produce a positive strobe pulse 1/2 period wide, 1/2 period
after the STATUS output has gone low. The rising edge of this
pulse can be used to latch data after each conversion.
CLOCK
<>-.-----1
STROBE
~LJ"
CLOCK-J
I
STATUS
"
LJ U
~LJ~LJ"
I
I
I
I
I
I
L
-.Jr-----------lJl-----LJ,
STROBE
,., ,., ,., ,., ciS,
LJ LJ LJ LJ U
~
H----r--1l--I
USING A TRACK AND HOLD AMP WITH MN5200 SERIES
A/D'I-The error that results when trying to convert moving
SHORT CYCLING CONTINUOUS CONVERTING
If one is already using the circuit described in the section
labeled SHORT CYCLING, one can short cycle and continuously convert by making the START CONVERT input the
AND function of STATUS (lC2) and STATUS (pin 7) outputs.
analog signals with a successive approximation A/D can be
as great as the amount the analog signal changes during a
single AID conversion time. If this error is unacceptable, a
Track and Hold (T/H) or Sample and Hold (S/H) amplifier
can be placed between the analog signal source and the A/D
converter. A careful error analysis will be necessary to
determine if the T/H is actually reducing and not increasing
overall error. T/H parameters such as aperture uncertainty,
gain accuracy, pedestal error and· droop rate will have to be
contended with (see the tutorial section of the Micro Networks'
6-83
CLOCK~
Applications Manual and Product Guide for a complete
discussion of T/H parameters).
START~
Normally, the T/H can be controlled directly by the AID's
STATUS output. Typical connections are shown below for
Micro Networks' MN343 (10 I'Sec acquisition timeto ±.0.01%)
and MN346 (1.6I'Sec acquisiton time to ±0.01%) Track and
Hold Amplifiers. The STATUS output changes form a "0" to a
"1" when the converter is reset. This drives the T/H from the
track to the hold mode. At the end of conversion, STATUS
returns to a "0" restoring the T IH to the track mode.
~
ANALOG
INPUT
>---1(14)
MN5200
MN343
10l'Sec
60 nSec
3mV
0.1 mVimSec
1.51'Sec
AcquiSition Time
Aperature Delay
Pedestal Error
Droop Rate
Track to Hold Settling
MN346
1.61'Sec
30 nSec
2 mV
0.1 mVimSec
150 nSec
Recall that if the START CONVERT pulse is brought high
immediately after the converter has been reset, the MSB will
be finalized one clock period later (see Timing Diagram).
Care should be taken to ensure aperture delay time and
track-to-hold settling time do not contribute errors. If necessary, the width of the START CONVERT pulse can be
increased to allow more time between the T/H being commanded into the hold mode (STATUS = "1") and the MSB
being set. Recall that output bits do not begin to get set until
after the START CONVERT has returned high. The example
below shows a 8.4 I'Sec delay to allow for track to hold
settling. Clock frequency = 240 kHz; 1 period = 4.2 I'Sec.
STATUS~
f-8.4~Sec-1
MSB~
~------
LJ
BIT 2ll1lllJ
BIT all1lllJ
TRIGGERING WITH A POSITIVE EDGE-If it is inconvenient to generate a negative going START CONVERT
PULSE of the proper width, MN5200 Series AID's can be
made to start converting on a positive going edge by
employing the circuit shown below. Assuming the previous
conversion is done and the Start Signal is low, the STATUS
output will be low, the output of IC1 will be high, and the
output of IC2 will be high. A rising edge as a Start Signal will
drive the output of IC2 low. The converter will reset on the
next rising clock edge. Resetting brings the STATUS high;
IC1 goes low; the start Signal is still high sothe output of IC2
goes high allowing the conversion to continue immediately.
The Start Signal has only to be brought back down before the
conversion is completed.
START
SIGNAL~IC2 ~(1)
~
MN5200
Cl
(22)
'-------'
CLOCK
-.lLfLJULJ1J1.fLJLJLIUL
~~~R}L
~~_ _ _ _ __
STATUS _ _ _ _ _--'
IC1 _ _ _ _ _--,
(ST~~i - - - - , U r - - - - - \ \ ; . l - - - - - - CONVERT)
24 PIN DIP
T
0.015(0.38) -.I~
PIN 1
0.035 (O.89)
\~\
I
.!!:~..!l.'
9
1.100(27.94)
,!.~--,J_
-1-.L
L---Q1lQJ.!-no
I-- ''''(20Sn
,------,
~
0.115(2.921]
J.
U
'.'oolS,,!,!
0020(''',
0230(584)
-1-0.120 {3.051
0170(4.32)
. '000(254'1
24-PIN DIP
Dimensions in Inches
(millimeters)
Note: MN5200 and MN5203
utilize package A.
MN5201, MN5202, MN5204,
MN5205, and MN5206 utilize
package B.
1 2~Q{31 2"1
1270(3226)
r -rL
0600l1524)
-0620(1575)
I
6:~~;;:~~
I~
100'060'''''41...1
"'"' I f
1100(2794)
l
Jtd:
O',..,;.l.b,
O.-{h",,'I,
OOl:'IO:JO,
/.- 0.600 flS.241-J
6-84
PACKAGE A
14-
PACKAGE B
MN5210 Series
l1::U
_
MICRO NETWORKS
13/Lsec, 12-Bit
MILITARY AID CONVERTERS
DESCRIPTION
FEATURES
• 13JLsec Maximum
Conversion Time
• ±1/2LSB Linearity and
No Missing Codes
Guaranteed Over Temperature
• Small 24-Pin DIP
• ±1LSB Zero Error
• ±2LSB Absolute Accuracy
• Low Power
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
MN5210 Series devices are high-speed, 12-bit, successive approximation NO converters in industry-standard, 24-pin dual-inline packages. Conversion time is 13JLsec max, and all specifications are met with a 1MHz clock. Functional laser trimming of
our own nichrome thin-film resistor networks results in
adjustment-free devices that are extremely accurate and highly
stable. Zero error, for example, is guaranteed to be better than
± 0.025% FSR (± 1 LSB) at +25°C and better than ± 0.05%
FSR (± 2 LSB) over the entire operating temperature range. All
units are fully specified and 100% tested for linearity and accuracy at their operating temperature extremes as well as at
room temperature.
These NO converters are available in a number of input voltage
ranges. For each range, the user has the option of specifying a
model complete with internal reference or, for improved overall
accuracy, a model which uses an external reference. In all
cases, ± 112LSB linearity and 12-bit "no missing codes" are
guaranteed over the entire operating temperature range.
All models of the MN5210 Series may be procured for operation
over the full -55°C to + 125°C military temperature range ("H"
models) or the O°C to +70°C commercial temperature range.
For military/aerospace or harsh-environment commercial/industrial applications, "H/B CH" models are fully screened to
MIL-H-38534 in Micro Networks MIL-STO-1772 qualified facility.
The MN5210 Series (13JLsec conversion time) and MN5200
Series (50JLsec conversion time) are the industry's most widely
accepted 12-bit NO's for military/aerospace applications. These
devices are presently designed into more than 50 military/
aerospace programs. Their small size, low power consumption
and adjustment-free operation make them excellent selections
for compact, highly reliable systems. New applications will be
found wherever size, speed, power and temperature considerations are paramount.
G::!J MICRO NETWORKS
January 1992
Copyright©1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
6·85
MN5210 SERIES 13p.Sec 12-Bit MILITARY AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Storage Temperature
Positive Supply (Pin 15)
Negative Supply (Pin 13)
Logic Supply (Pin 2)
Analog Input (Pin 14)
Digital Inputs (Pins 1, 24)
Digital Outputs
Ref. Input (MN5213, 14, 15)
ORDERING INFORMATION
PART N U M B E R - - - - - - - - - MN521X H/B CH
O·C to +70·C
-55·C to+125·C ("H" Models)
-65·C to +150·C
+18 Volts
-18 Volts
-0.5 to +7 Volts
±25 Volts
-0.5 to +5.5 Volts
Logic Supply
o to -15 Volts
I
Select Model Number (MN5210, 521" etc.)
Standard part is specified for O·C to + 7O·C
operation.
Add "H" for specified -55·C to + 125·C
operation. - - - - - - - - - - - - -.......
Add "'B" to "H" models for
Environmental Stress Screening. - - - - - - -.......
Add "CH" to "/B" models for 100%
screening according to MIL·H·38534.--------I
SPECIFICATIONS (TA =2S·C. Supply Voltages±1SV and +SV. for Ext. Ref. Model. VRo,=-10.000V. unle•• otherwl.e 8pacllled).
ANALOG INPUTS
Input Range (Input Impedance) (Note I):
o to -IOV (5KIl)
-5V to +5V (5KIl)
-IOV to + 10V (IOKIl)
o to +10V (5KIl)
TRANSFER CHARACTERISTICS
Linearity Error (Notes 2. 3): +25·C
O·C to +70·C
-55·C to +125·C ("H'" Models)
Differential Linearity Error
No Missing Codes
Full Scale Absolute Accuracy Error (Notes 4, 5)
+25·C
O·C to +70·C
-55°C to +125·C ("H" Models)
Zero Error (Notes 4, 5): +25·C
DoC to +70°C
-55°C to +125°C ("H" Models)
Gain Error (Note 5)
Gain Drift
Conve,'- 1n Time (Note 6)
POWER SUPPLIES
Power Supply Range: ± 15V Supplies
+5V Supply
Power Supply Rejection (Note 7): + 15V Supply
-15V Supply
Current Drain: + 15V Supply
-15V Supply
+5V Supply
-10V Reference (MN5203, 04, 05)
DIGITAL INPUTS (ALL UNITS)
Logic Levels: Logic "I"
Logic "0"
Clock Input (Note 8): Pulse Width High
Pulse Width Low
Loading High (V" =2.4V)
Loading Low (V" =0.3V)
Frequency (Note 6)
Start Convert Input: Loading High (V" =2.4V)
Loading Low (V" =0.3V)
Setup Time Start Low to Clock (Note 9)
DIGITAL OUTPUTS (ALL UNITS)
Logic Coding (Note 10): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1"
Logic "0"
Output Drive Capability, All Outputs (Note 11): Logic "1"
Logic "0"
REFERENCE INPUT/OUTPUT (Note 12)
Internal Reference: Voltage
Accuracy
Tempco of Drift
Max. External Current (Without Buffering)
External Reference: Voltage
Loading
6-86
MODEL NUMBER
(External Ref.)
MN5213
MN5214
MN5215
MODEL NUMBER
(Internal Ref.)
MN5210
MN5211
MN5212
MN5216
TYP.
MAX.
+1f4
+112
±114
±112
TYP.
MAX.
±1f4
± 114
+1/2
±1J2
+112
± 0.025
± 0.2
± 0.01
± 0.025
+ 1f2
Guaranteed Over Temperature
± 0.025
± 0.05
± 0.05
± 0.4
± 0.4
± 0.025
± 0.05
± 0.05
+0.Q1
±- 0.025
±
OfoFSR
%FSR
%FSR
%FSR
%FSR
%FSR
%
ppm/DC
13
13
I,Sec
+ 3
±5
+ 3
%
%
%FSR/% Vs
%FSR/% Vs
mA
mA
mA
mA
UNITS
±5
MIN,
± 0.05
± 0.1
± 0.1
+ 0.025
0.05
± 0.05
± 0.025
± 3
± 0.025
± 10
± 0.005
+ 0.01
23
-25
25
+112
±1f2
UNITS
LSB
LSB
LSB
LSB
± 0.02
+ 0.05
28
-35
42
± 0.005
+ 0.005
23
-25
25
-1.5
TYP.
± 0.02
+ 0.02
28
-35
42
-2
MAX.
2.0
0.7
125
175
2
-0.25
4
-0.25
20
-0.4
1
40
-0.4
25
Complementary Straight Binary
Complementary Offset Binary
2.4
3.6
0.15
0.3
8
2
-6.3
±2
±5
100
-10.000
-2
Volts
Volts
nSec
nSec
ItA
mA
MHz
ItA
mA
nSec
Volts
Volts
TTL Loads
TTL Loads
Volts
%
ppm/DC
ItA
Volts
mA
A 1 MHz clock gives a STATUS pulse that is 12 ,uSec wide. The 13 .uSec
spec reflects the fact that unless careful timing precautions are taken, it
will usually take 13 clock periods to update digital output data.
SPECIFICATION NOTES:
1. Consult factory for other available input voltage ranges.
7. Micro Networks tests and guarantees Power Supply Rejection over the
±15V ±3% range.
2. Micro Networks tests and guarantees maximum linearity error at room
temperature and at both the high and low extremes of the specified
operating temperature range.
8. The clock may be asymmetrical with minimum positive or negative pulse
width. See Note 6.
3. 1 LSB for a 12 bit converter corresponds to O.024%FSR. See Note 4.
9. In order to reset the converter, START CONVERT must be brought low
at least 25 nSec prior to a lowto high clock transition. See Timing Diagram
4. FSR stands for Full Scale Range and is equal to the peak to peak voltage
of the selected input range. For the ±10V input range, FSR is 20 volts, and
1 LSB is equal to 4.88 mV. For the 0 to +10V. a to -10V, and ±5V ranges,
FSR is 10 volts, and 1 LSB is equal to 2.44 mV.
10. CSB = Complementary Straight Binary
COB = Complementary Offset Binary
Serial and parallel output data have the same coding. Serial data is in NonReturn to Zero (NRZ) format. See Output Coding and Timing Diagram.
5. See Absolute Accuracy section below for an explanation of how Micro
Networks tests and specifies Full Scale Absolute Accuracy, Gain, and
Zero Errors.
11. One TTL load is defined as sinking 40 ,LLA with a logic "1" applied and
sourcing 1.6 rnA with a logic "0" applied.
6. Conversion Time is defined as the width of the converter's STATUS
(E.O.C.) pulse (see Timing Diagram). Micro Networks guarantees MN5210
Series converters will meet all specs with clock frequencies up to 1 MHz.
12. MN5210, MN5211, MN5212, and MN5216 have an internal-6.3V reference
MN5213, MN5214, and MN5215 require an external -10.000V reference.
BLOCK DIAGRAM
Start Convert (1 )
PIN DESIGNATIONS
SUCCESSIVE
APPROXIMATION
REGISTER
Clock Input (24 )
~
(22) Status Out
(3) Serial Out
(9)
-(8)
+15V Supply (15) ~
-15V Supply (13) ~
+5V Supply
(2) ~
Ground
(11) ~
Ground
(23) ~
(7)
(6)
(5)
(4)
(21 )
(20)
(19)
(18)
(17)
(16)
(MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bil7
Bil8
Bit 9
Bit 10
Bit 11
(LSB)
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Ref. InlOut (12)
(See Note 12 Abov e)
Analog Input (14)
D/A CONVERTER
..A,
I
R'N
COMPARATOR
ABSOLUTE ACCURACY ERROR
DIGITAL
OUTPUT
0000 0000 0000
A given digital output code is valid for a band of analog input
voltages that is ideally 1 LSB wide. This is demonstrated in
the next column and on the following page where portions of
the theoretical analog input/digital output transfer functions
of the MN5216 (Oto +10V input range) and the MN5212 (±10V
input range) are sketched.
0000 0000 0001
Notice that, for the MN5216, any analog input between
+0.00244 volts (1 LSB = 2.44 mY) and +0.00488 volts will give a
digital output of 1111 11111110. If we assign this code to the
nominal midrange of the analog input band for which it is
valid, we can say that the 1111 1111 1110 digital code
corresponds to analog inputs of +3.66 mV ±1.22 mV which
can be written as +3.66 mV ±1/2 LSB. The ±1/2 LSB is a
quantization uncertainty unavoidable in AID conversion. It is
referred to as Inherent Quantization Error and its magnitude
can be reduced only by going to higher resolution converters.
•
24
12
13
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
Starl Converl
+5V Supply
Serial Output
Bit 6
BI15
Bit 4
BI13
Bit 2
Bil1 (MSB)
2.2 I'F to +15V
Ground
Ref. Out (-6.3V)
Ref In (-10.0V)
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
24 Clock Input
23 Ground
22 Sial us (E.O.C.)
21 Bit 7
20 Bil8
19 Bit 9
18 Bit 10
17 Bit 11
16 Bit 12 (LSB)
15 +15V Supply
14 Analog Input
13 -15V Supply
1
0000 0000 00 10
0111111111111
-
1000 0000 0000
/
~/
111111111101t
111111111110~
1111 1111 1111>
o
o
o
o
a
>
o:t
"<:t
("\J
0
0
c:i
>
0:)
00
"<:t
a
a
> '>-'1>,--:>~-:>"";;II--:>>-~->-~-', ANALOG
("\J
(Q
C')
If)
0
en
en
r--.
0
r--.
O"<:t
0
0
0
a
a
"<:t
"<:t
("\J
0
0
co
i::
en
en
co
u)
(\J
'"'"co
>
~co
co
>
0
INPUT
0
0
0
0
0
MN5216 TRANSFER FUNCTION
6-87
I
0000 0000 0000
0000 0000 00a1
1
0000 0000 DO 10
0111111111101
0111 1111 1111
1000 DODD 0000
1000 0000 0001
111111111101[
11111111 1110
111111111111
DIGITAL
OUTPUT
,..,..> >.,.,
'"~ ...~
0
1
0
.,>., i':,..
> > > >
... '" .,"'"' '"'" ;;;'" 88
'"en '"'"en '"'"en ~
+
+
+ +
0
0
0
0
0
0
<'l
0
0
These Absolute Accuracy Error specifications are summarized in the two plots below. The ideal transfer function is now
sketched as a broken line. We guarantee, for the MN5216H,
that the actual transfer function will be ±1/2 LSB linear and
that all the transition voltages will fall within the boundaries
indicated by the solid lines at +25°C and at -55°C and
+125°C.
DIGITAL
OUTPUT
000000000000 TO
0000 0000 0001
TRANSITION
/
/
/
1
MNS212 TRANSFER FUNCTION
It is difficult and time consuming to measure the center of a
quantization level (the +0.00366 volts in this example). The
only points along an AID converter's analog input/digital
output transfer function that can quickly and accurately be
detected and measured are the transition voltages, the
voltages at which the digital outputs change from one code
to the next. The Absolute Accuracy Error of a voltage input
AID converter is the difference between the actual, unadjusted, analog input voltage at which a given digital
transition occurs and the analog input voltage at which that
transition is ideally supposed to occur. This difference is
usually expressed in LSB's or %FSR (see Note 4 above).
Absolute Accuracy Error includes gain, offset, linearity, and
noise errors, and when specified over temperature, encompasses the individual drifts of these errors.
For the MN521 0 Series AID converters, Micro Networks tests
Absolute Accuracy Error at both endpoints of unipolar input
ranges and at both endpoints and the midpoint of bipolar
input ranges. These tests are performed at room temperature
and at both the high and low extremes of the specified
operating temperature range. The specifications appear in
the table as the Full Scale Absolute Accuracy and Zero
Errors.
EXAMPLE MN5216: Return to the ideal analog input/digital
output transfer function of the MN5216 sketched on page 3.
Notice that the digital output data changes from 1111 1111
1111 to 1111 1111 1110 when the input voltage increases
from OV to +2.44 mY. It changes from 1111 1111 1110 back to
1i 11 1111 1111 as the input voltage is decreased from some
more positive voltage to +2.44 mY. This voltage, +2.44 mV is
the zero transition voltage. It is the voltage at which the LSB
changes from a "1" to a "0" or vice versa while all other bits
remain "1'. The positive full scale LSB transition voltage, the
voltage at which the LSB changes while the other bits remain
"0", is ideally +9.9976V.
For the MN5216H (0 to +10V input range, -55°C to +125°C
operation), Micro Networks tests linearity and the accuracy
of the two transition voltages just discussed at -55° C, +25° C,
and +125° C. We guarantee that the transfer function will be
±112 LSB linear at all temperatures and that the zero
transition will be within ±0.025%FSR (±2.5 mY) of its ideal
value (+2.44 mY) at +25° Cand within ±0.05%FSR (±5 mY) of its
ideal value at -55°C and at +125°C. This is our Zero Error
specification. We guarantee that the positive full scale LSB
transition voltage will be within ±0.05%FSR (±5 mY) of its
ideal value (+9.9976V) at +25°C and within ±0.4%FSR (±40
mY) of its ideal value at -55°C and +125°C. This is our Full
Scale Absolute Acuracy Error specification.
6-88
111111111111TO
111111111110
TRANSITION ~~------------~~----~ANALOG
6&;
~~
INPUT
NI'-
o..:;t
g;~
88
00
0)0)
MNS216 ABSOLUTE ACCURACY +2SoC
DIGITAL
OUTPUT
00000000 0000 TO
0000 0000 0001
TRANSITION
/
/
/
/
111111111111TO
1111 1111 1110
TRANSITION -4'-+-----------<---------_...ANALOG
~~~
~
~
INPUT
000
000
000
C:;
'"....o
o
These Absolute Accuracy Error specifications are summarized in the two plots below. The ideal transfer function is now
sketched as a pro ken line. We guarantee, for the MN5212H,
that the actual transfer function will be ±1/2 LSB linear and
that all the transition voltages will fall within the boundaries
indicated by the solid lines at +25° C and at -55° C and
+125°C.
DIGITAL
OUTPUT
0000 0000 0000 TO
0000 0000 000 1
TRANSITION
>
'"mm
~~~
ANALOG
INPUT
111111111111 TO
111111111110
TRANSITION
/
Because Micro Networks tests and guarantees ±1/2 LSB
linearity at all temperatures, the Absolute Accuracy of any
transition voltage can be interpolated from the Full Scale
Absolute Accuracy and Zero Error specifications. Example:
at +25° C, the 100000000000 to 0111 1111 1111 transition of
the MN5216 will occur within ±0.0375%FSR (±3.75 mV) of its
ideal value (+5.000V). For temperatures intermediate to
+25°C and -55°C or +125°C, maximum Full Scale Absolute
AcciJracy and Zero Errors can also be interpolated. At
+75° C, for example, Full Scale Absolute Accuracy Error will
be ±0.225%FSR.
/
/
E-__~~__________~~/~~M7A~J~O~R~~~____~ANALOG
/
5TRANSITION;::~~
INPUT
LO
LO
o
I/)
LO
000>0
...
~
~O:O
mmo
/
111111111111 TO
1111 1111 1110
/
~
0
~
/
omen
>
MN5212H ABSOLUTE ACCURACY -55°C AND +125°C
»>
om",
omm
/
TRANSITION
We have not specified Unipolar and Bipolar Offset Errors for
the MN5210 Series. We feel that Offset is a confusing
MN5212 ABSOLUTE ACCURACY +25° C
TIMING DIAGRAM
Clock
Bit
21f1111/V0IJ
o
L--J1
Bit 3 ZzzmOOZIl
Bit 41/ZZlWZIZ/J
Bit 5
'lll77Ilvm
Bit 6
/V1Il7J777A
a
o
Bit 7 iOZ/Oll!//J
L--.J1
~r.1--------------------------
Bit 8 'l7ZOZZZTfI1
a
L--.J1
71IIII1lZZZIl
Bit 10 ZZZIIIIVIIII
Bit 9
o
Bit 11 WROZI/J
LSB
mmmm
L--J1
Status _ _ _---'
L-J!
SeriaIOut _ _ _ _ _ _-'1
MSB
Bit 2
Bit 3
Bit 4
~
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
LSB
TIMING DIAGRAM NOTES:
1. Operation shown is for the digital word 1101 0011 0101 which corresponds to 1.7432V on the a to +10V input range (MN5216). See Output
Coding.
2. Conversion time is defined as the width of the STATUS (E.O.C.) pulse.
3. The converter is reset (MSB = "0", all other bits = "1", STATUS = "1") by
holding the START CONVERT low during a low to high clock transition.
The START CONVERT must be low for a minimum of 25 nSec prior to the
clock transition. Holding the START low will hold the converter in the
reset state. Actual conversion will begin on the next rising clock edge
after the START has returned high.
4. The delay between the resetting clock edge and STATUS actually rising
to a "1" is 120 nSec maximum.
5. The START CONVERT may be brought low at any lime during a conversion to reset and begin converting again.
6. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequent falling clock edges, and these
edges can be used to clock serial data into receiving registers.
7. Output data will be valid 30 nSec (maximum) after the STATUS (E.O.C.)
output has returned low. Parallel output data will remain valid and the
STATUS output low until another conversion is initiated.
8. For continuous conversion, connect the STATUS output (Pin 22) to the
START CONVERT input (Pin 1). See section on Continuous Conversion.
9. When the converter is initially "powered up", it may come on at any point
in the conversion cycle.
6-89
specification and choose not to use it. Offset Errors for the
MN5210 Series will always be equivalent to either our Full
Scale Absolute Accuracy or Zero Errors and we prefer these
specifications because of their simplicity. Be sure you clearly
understand each manufacturer's converter specification definitions before you compare converters solely on a data sheet
basis.
GAIN ERROR-Gain Error is the difference between the
ideal and the measured values of a converter's Full Scale
Range (minus 2 LSB); it is a measure of the slope of the
converter's transfer function. Gain Error is not a type of
Absolute Accuracy Error, but it can be calculated using two
Absolute Accuracy Error measurements. It is equivalent to
the Absolute Accuracy Error measured for the 0000 0000
0000 to oood 0000 0001 transition minus that measured for
the 1111 1111 1111 to 1111 1111 1110 transition.
See the Converter Tutorial Section of the Micro Networks'
Applications Manual and Product Guide for a complete
discussion of converter specifications.
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN5210 Series converters. A 2.2!,F (25V) nonpolarized capacitor must be connected between- Pin 10 and
+15V. The units' two GROUND pins (Pins 11 and 23) are not
connected internally. They should be tied together as close
to the package as possible and connected to system analog
ground, preferably through a large ground plane underneath
the package. If the grounQs cannot be tied together and must
be run separately, a non-polarized 0.01!,F bypass capacitor
should be connected between Pins 11 and 23 as close to the
unit as possible and wide conductor runs employed.
Power supplies should be decoupled with tantalum or
electrolytic capacitors located close to the converters. For
optimum performance and noise rejection, 1!,F capacitors
paralleled with 0.01!,F ceramic capacitors should be used as
shown in the diagrams below.
Pin 15 0 1
1
DESCRIPTION OF OPERATION-The Successive Approximation Register (SAR) is a set of flip flops (and control logic)
whose outputs act as both the direct (parallel) data outputs
of the Analog to Digital Converter (AID) and the digital drive
for the AID's internal Digital to Analog Converter (D/A). See
Block Diagram. Holding the AID's START CONVERT (Pin 1)
low during a clock low to high transition resets the SAR. In
this state, the output of the MSB flip flop is set to logic "0", the
outputs of the other bit flip flops are set to logic "1", and the
STATUS output (Pin 22) is set to logic "1" (see Timing
Diagram). The START CONVERT must now be brought high
again for the conversion to continue. If the START is not
brought high, the converter will remain in the reset state.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The
comparator output ("1" or "0") informs the SAR whether the
present digital output (0111 1111 1111 in the reset state) is
"greater than" or "less than" the analog input. Depending
upon which is greater, on the first rising clock edge after the
START has returned high, the SAR will set the MSB to its final
state ("1" or "0") and bring bit 2 down to a "0". The digital
output is now X011 1111 1111. The DIA converts this to an
analog value, and the comparator determines whether this
value is greater or less than the analog input. On the next
rising clock edge, the SAR reads the comparator feedback,
sets bit 2 to its final value, and brings bit 3 down to a logic "0".
The digital output is now XX01 1111 1111. This successive
apprOXimation procedure continues until all the output bits
are set. The rising clock edge that sets the LSB (bit 12) als('
drops the STATUS OUTPUT to a "0" Signaling that the
conversion is complete. Output data is now valid and will
remain so until another conversion is started. The clock does
not have to be turned off.
CONTINUOUS CONVERTING - The MN5210 Series AID
converters can be made to continuously convert by tying the
STATUS output (Pin 22) to the START CONVERT input (Pin
1). In this configuration, STATUS (START CONVERT) will go
low at the end of a conversion (see Timing Diagram) and the
next rising clock edge will reset the converter bringing
STATUS (START CONVERT) high again. The MSB will be set
on the next rising clock edge. The result is that the STATUS
will go low for approximately one clock period following
each conversion. Please read the section describing the
STATUS output. See below for continuous conversions while
short cycling.
+15V
l 10.01 "F
1 "F T
r O.01 "F
Pin 11, 23""'----:
Buffer In (30)
Ref. Out (18)
Bipolar Offset (23)
:$J
:j?
12·8it
D/A Converter
Summing Junction (22)
5kll
20V Range (25)
lOV Range (24)
v
(13) MSB
(12) Bit 1 (MS8)
(11) Bit2
(10) Bit 3
(9) Bit4
(8) Bit5
(7)Bit6
(6) Bit7
(5) Bit8
(4) 81t9
(3) Bit 10
(2) Bit 11
(1) Bit 12 (LSB)
+ 15V Supply (28) ~
-15VSupply(31) ~
+5V Supply (16) ~
Digital Ground (15) 0
~
Analog Ground (26) a
~
Buffer Out (29)
(20) Status (E.O.C.)
(14) Short Cycle
(32) Serial Output
5kll
V\I"-
(27) Gain Adjust
Ie?::,
6·95
PIN DESIGNATIONS
•
32
16
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
Bit 12 (LSB)
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1 (MSB)
MSB
Short Cycle
Digital Ground
+ 5V Supply (+ Vdd)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Serial Output
-15V Supply (- Vecl
Buffer Input
Buffer Output
+ 15V Supply (+ Vecl
Gain Adjust
Analog Ground
20V Range
10V Range
Bipolar Offset
Summing Junction
Start Convert
Status (E.O.C.)
Clock Output
Reference Output (+6.3V)
Clock Adjust
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Propsr attention to layout and
decoupling is necessary to obtain specified accuracies. Analog and
digital grounds (pins 15 and 26) are not connected to each other
internally and must be tied together as close to the package as possible, preferably through a large analog ground plane underneath
the package. If these commons must be run separately, a nonpolarized, 0.D1 to 0.1".F bypass capacitor should be connected between pins 15 and 26 as close to the package as possible and wide
conductor runs should be used.
Coupling between the analog inputs and digital signals should be
minimized to reduce noise pickup. The Summing Junction (pin 22)
is the direct input to the internal comparator, and is particularly noise
susceptible. In bipolar operation, where pin 22 is connected to pin
23, a short jumper should be used, and when external offset adjustinent is employed, the 1.8 megohm resistor should be located as
close to the package as possible.
Power supplies should be decoupled with tantalum or electrolytic
capacitors located close to the device package. For optimum results,
1". F capacitors paralleled by 0.D1". F ceramic capacitors should be
connected as shown in the diagrams below. An additional 0.01". F
ceramic bypass capacitor should be located close to the package
connecting the gain adjust pOint (pin 27) to analog ground.
Pin 28
Pin 16
I
0
1~F
I
1~F
+5V
O.01~F
_1-,-__1.1-- Digital
Pin260
Pin 15 0-0
Ground
0
I
I I
1~F
Pin31
0
I
T
SHORT CYCLING-For applications requiring less than 12 bits
resolution, these converters can be truncated or short cycled at the
desired number of bits with a proportionate decrease in conversion
time. The connections shown below truncate the converter to provide the minimum conversion time for a given resolution.
Resolution (Bits)
12
10
8
Connect Pin 17 to Pin
Connect Pin 14 to Pin
Conversion Speed (J.------1 (24)
MN376
MN5240
1-0---- Throughput - - - - 0 1
Start Convert
Status (E.O.C.)
Conversion Time
Throughput Rate
T/H Acquisition Time
AID Conversion Time
192kHz
200nsec
5"sec
6-97
I
OPTIONAL EXTERNAL OFFSET AND GAIN ADJUSTMENTSInitial offset and gain errors may be trimmed to zero using external
potentiometers as shown in the following diagrams. Adjustments
should be made following warmup, and to avoid interaction, offset
should be adjusted before gain. Fixed resistors can be ± 20% carbon composition or better. Multiturn potentiometers with TCR's of
100ppm/oC or less are recommended to minimize drift with
temperature. If these adjustments are not used, pin 22 should be
connected as described in the Input Range Selection section and
a 0.Q1 pF capacitor should be connected from pin 27 to pin 26.
Output Coding). While continuously converting, adjust the gain
potentiometer until all the output bits are "a" and the LSB "flickers"
on and off. A 0.Q1 pF capacitor should be connected from Gain Adjust (pin 27) to Analog Ground (pin 26).
+15V
Pin
22
OFFSET ADJUSTMENTS-Connect the offset potentiometer as
shown and apply the input voltage at which the 1111 1111 1110 to 1111
11111111 transition is ideally supposed to occur (see Digital Output
Coding). While continuously converting, adjust the offset potentiometer until all the output bits are "1" and the LSB "flickers" on
and off.
f
1.8MI!
o--vv---
10k!l
to
100kn
-15V
or
Pin
180kn
180k!l
or
+15V
1
Pi n
10k!l
22~to100kn
27
Pin
22kn
'"
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
below and apply the input voltage at which the 0000 0000 0001 to
0000 0000 0000 transition is ideally supposed to occur (see Digital
270k!l
10kn
~Jo.016V8';1~~Ok!l
J
26
-15V
r
+15V
27?kn
Offset Adjust
~~F'l
v
-15V
'"
Gain Adjust
INPUT RANGE SELECTION
Analog Input Voltage Range
Pin Connections
o to
o to
+ 5V
FOR NORMAL INPUT
Input Impedance (kO)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 30 to Pin
Connect Input to Pin
2.5
26
22
26
24
FOR BUFFERED INPUT
Input Impedance (MO)
Connect Pin 23 to Pin
Connect Pin 25 to Pin
Connect Pin 29 to Pin
Connect Input to Pin
100
26
22
24
30
±2.5V
±5V
±10V
5
26
Open
26
24
2.5
22
22
26
24
5
22
Open
26
24
10
22
Input Signal
26
25
100
26
Open
24
30
100
22
22
24
30
100
22
Open
24
30
100
22
29
25
30
+ 10V
DIGITAL OUTPUT CODING
Analog Input Voltage Range
o to
+5V
o to
+10V
Digital Outputs
±2.5V
±5V
±10V
MSB
LSB
+5.0000
+4.9988
+10.0000
+9.9976
+2.5000
+2.4988
+5.0000
+4.9976
+10.0000
+9.9951
0000 0000 0000
0000 0000 0000"
+2.5012
+2.5000
+2.4988
+5.0024
+5.0000
+4.9976
+0.0012
0.0000
-0.0012
+0.0024
0.0000
-0.0024
+0.0049
0.0000
-0.0049
0111 1111 1110"
0'0fb0fbfbfb0'0fb00"
1000 0000 0000"
+0.0012
0.0000
+0.0024
0.0000
-2.4988
-2.5000
-4.9976
-5.0000
-9.9951
-10.0000
111111111110'
111111111111
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input ranges, output coding is complementary straight binary (CS8).
2. For bipolar input ranges, output coding is complementary offset binary (COB).
3. For bipolar input ranges, complementary two's complement coding (GTC) can
be obtained by using the complement of the most significant bit. MSB is available
on pin 13. See Pin Designations.
4. For 0 to +5V or ±2.5V input ranges. 1LSB for 12 bits=1.22mV 1LSB for 10
blts=4.88mV
5. For 0 to +10V or ±5V input ranges, 1LSB for 12 bits=2.44mV. 1LSB for 10 bits
=9.77mV.
6. For ±lOV input range, 1LSB for 12 bits=4.88mV. 1LSB for 10 bits=19.5mV
·Voltages given are the theoretical valt.;es for the transitions indicated. Ideally, with
the converter continuously converting, the output bits indicated as ~ will change from
"1" to "0" or vice versa as the input voltage passes through the level indicated.
6-98
EXAMPLE: For a MN5240 operating on its ± 10V range, the transition from digital
output 1111 1111 1111 to 1111 1111 1110 (or vice versa) will ideally occur at an input
voltage of -9.9951V (-Full Scale +1LSB). Subsequently, any input voltage more
negative than -9.9951V will give a digital output of all "1'5' '. The transition from digital
output 100000000000 to 0111 1111 1111 will ideally occur at an input voltage of OV
and the 0000 0000 0001 to 0000 0000 0000 transition should occur at +9.99S1V (+Full
Scale -1LSB). An input more positive than +9.9951V will give all "O's".
U1J
_
MN5245
MN5246
1.1 MHz, 12-Bit
MICRO NETWORKS
AID CONVERTERS
DESCRIPTION
MN5245, MN5245A, MN5246 and MN5246A are 850nsec,
12-bit, AID converters that guarantee 1.1 M Hz conversion
rates. When used with MN376 High-Speed TIH Amplifiers,
these AID's can be configured to form bonafide, 1MHz,
sample-and-convert systems that can digitize full-scale
(5V) input signals with bandwidths up to 500kHz. These
systems typically achieve signal-to-noise ratios of 70dB
with harmonics down more than - 80dB while digitizing
500kHz signals at the Nyquist rate.
Packaged in standard, 40-pin, hermetically sealed,
ceramic dual-in-lines, MN5245 and MN5246 AID converters
offer an outstanding combination of resolution, speed,
size and cost. These TTL compatible devices achieve their
sub-1 usec conversion speed using the digitally corrected
subranging (serial-parallel) AID conversion technique.
Recent advances in monolithic flash AID converters and
improvements in digital error correcting techniques have
enabled us to reduce chip count over previous designs
while improving performance.
FEATURES
• 850nsec Maximum
Conversion Time
• Guaranteed 1.1MHz
Conversion Rate
• 1MHz Sampling Rate
When used with MN376
T/H Amplifier
• Multisourced
• Small 40-Pin DIP
• No Missing Codes
Guaranteed Over
Temperature
• TTL Compatible
• 3-State Output Buffer
(MN5245A, MN5246A)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
MN5245 has a 0 to + 5V analog input range; while
MN5246 has a ± 2.5V analog input range. "A" versions
of each device contain internal 3-state output buffers to
facilitate microprocessor interfaCing. All models guarantee
± 0.024% FSR integral linearity and "no missing codes"
for 12 bits over their entire specified temperature ranges.
40 PIN DIP
PIN 1
\
MN5245 and MN5246 are ideal design solutions for highspeed digitizing applications in which speed, accuracy,
size and reliability are paramount considerations. Typical
applications include spectrum, vibration, waveform and
transient analyzers; radar, sonar and video digitizers;
medical imaging equipment; digital filters; and multiplexed
or simultaneous-sampling data-acquisition systems.
MN5245 and MN5246 are manufactured in Micro Networks
MIL-STD-1772 qualified hybrid facility, and for
military/aerospace and harsh-environment industrial
applications, they are available 100% screened to MIL.H-38534.
!
1-0.6001".241--1
Dimensions in inches
(millimeters)
OJ]
_
MICRO NETWDRKS
January 1992
Copyright " 1992
Micro Networks
All rights reserved
324 Clark St.. Worcester, MA 01606 (508) 852-5400
6-99
MN5245 MN52461MHz 12·Bit AID CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN5245, 45A, 46, 46A
MN5245E, 45AE, 46E, 46AE
MN5245H, 45AH, 46H, 46AH
MN5245H/B, 45AH/B, 46H/B, 46AH/B
Storage Temperature Range
+ 15V Supply (+ Vcc , Pin 9)
-15V Supply (- Vcc , Pin 3)
+ 5V Supply (+ Vdd, Pins 15, 22, 39)
Digital Inputs (Pins 36 and 37)
Analog Input (Pin 1): MN5245, MN5245A
MN5246, MN5246A
SPECIFICATIONS (TA
j
I
- 55"C to + 125" C (case)
: : ::UN~::5Ro-r-M-N-5-2-46-.- - - - - - MN524 A HIS CH
O"C to + 70"C (case)
- 25"C to + 85"C (case)
-55"C to + 125"C (case)
-55"C to + 125"C (case)
-65"C to + 150"C
- 0.5 to + 18 Volts
+ 0.5 to - 18 Volts
- 0.5 to + 7 Volts
- 0.5 to + 5.5 Volts
- 1 to + 6 Volts
- 3.5 to + 3.5 Volts
Add "A" suffix for optional
3·state output buffer. _ _ _ __
Standard Part is specified for DOC to +70°C
operation.
-------1
Add "E" suffix for specified -25°C to +85°C
(case) operation.
-------1
Add "H" suffix for specified -55°C to +125°C
(case) operation.
--------'
Add "IB" to "H" devices for
Environmental Stress Screening. _ _ _ _ _ _ _---'
Add "CH" to "HIS" devices for 100%
screening according to MIL-H-38534 _ _ _ _ _ _ _--J
= + 25°C, Supply Voltages ± 1SV and + SV unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Input Voltage Range: MN5245, MN5245A
MN5246, MN5246A
Input Impedance (Note 11)
TYP.
MAX.
UNITS
Oto +5
-2.5 to +2.5
Volts
Volts
2/10
k!llpF
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "a"
+2.0
a
+5.0
+0.8
Volts
Volts
1
1
LSTIL Load
LSTIL Load
±1
±1
LSB
LSB
Loading (Note 2): Start Convert Input
Data Enable Input (MN5245A, MN5246A)
TRANSFER CHARACTERISTICS (Note 3)
±Y2
±Y2
Integral Linearity Error: Initial (+ 25"C)
Over Temperature
12-Bit No Missing Codes
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Note 4): Initial (+ 25"C)
Over Temperature
±0.05
±0.1
±0.15
±0.3
%FSR
%FSR
Unipolar Offset Error (MN5245, MN5245A; Note 5): Initial (+ 25°C)
Over Temperature
Drift
±0.05
±0.1
±10
±0.1
±0.15
±20
%FSR
%FSR
ppm of FSR/oC
Bipolar Zero Error (MN5246, MN5246A;Note 6): Initial (+ 25"C)
Over Temperature
Drift
±0.05
±0.1
±10
±0.1
±0.2
±25
%FSR
%FSR
ppm of FSR/"C
Gain Error (Note 7): Initial (+ 25"C)
Over Temperature
Drift
±0.05
±0.1
±15
±0.1
±0.3
±40
%
%
ppm/"C
+0.5
Volts
Volts
DIGITAL OUTPUTS
Output Coding (Note 8): MN5245, MN5245A
MN5246, MN5246A
Output Logic Levels (Note 12): Logic "1" (lsouRceS 100~A)
Logic "0"(I S1NK s2mA)
Straight Binary
Offset Binary
+2.7
Leakage (Bit l-Bit 12) in High-Z State (MN5245A, MN5246A):
Logic "1" (VOH = +2.7V)
Logic "a" (VOL = + 0.4V)
+10
-10
~A
850
nsec
/LA
DYNAMIC CHARACTERISTICS
Conversion Time (Note 9)
Conversion Rate (Note 9)
1.1
MHz
Start Convert Pulse Width (Notes 10, 11)
50
nsec
825
Delay Falling Edge of Start to Status = "1" (Note 11)
Delay Falling Edge of Start to Previous Output Data Invalid (Note 11)
45
750
Delay Falling Edge of Start to Falling Edge of T/H Control
750
Delay Falling Edge of Status to Output Data Valid (Note 11)
Delay Falling Edge of Enable to Output Data Valid (Note 11)
nsec
nsec
780
nsec
a
nsec
nsec
50
REFERENCE OUTPUT
Internal Reference (Note 11): Voltage
Accuracy
Drift
External Current
6-100
+5.000
±2
±10
5
Volts
%
ppm/"C
~A
POWER SUPPLY REQUIREMENTS
MIN.
TYP.
MAX.
UNITS
Power Supply Range: +15V Supply
-15V Supply
+5V Supply
+14.55
-14.55
+4.75
+15
-15
+15.43
-15.45
+5.25
Volts
Volts
Volts
Power Supply Rejection (Note 13): +15V Supply
-15V Supply
+5V Supply
+5
-50
-50
-50
dB
dB
dB
Current Drain: +15V Supply
-15V Supply
+5V Supply
+41
-83
+150
+50
-90
+165
mA
mA
mA
Power Consumption
2635
2925
mW
SPECIFICATION NOTES:
7. Gain error is defined as the error in the slope of the converter transfer func·
tion. It is exprBssed as a percentage and is equivalent to the deviation
(divided by the ideal value) between the actual and the ideal value for the
full input voltage span from the input voltage at which the output changes
from 11 t 1 1111 111 t to 1 t11 11111110 to the input voltage at which the
output changes from 0000 00000001 to 0000 0000 0000. Initial gain error is
adjustable to zero with an external potentiometer.
B. See Output Coding table for details.
9. Conversion time is defined as the width of the converter's Status output
pulse. The combination of 50nsec Start Convert pulses and 850nsec
Status pulses permits minimum 1.1MHz conversion rates. See Timing
Diagram.
10. Actual conversion process is initiated on the falling edge of the Start Convert signal. See Timing diagram,
11. These parameters are listed for reference only and are not tested.
12. Digital outputs inClude Data Bits (pins 23·34), Status (pin 17), and T/H can·
trol (pin 20). Specified drive capability is the equivalent of 5 LS TTL loads
minimum.
13. Power supply rejection is defined as the change in the analog input
voltage at which the 111111111110to 111111111111 or 0000 0000 0000 to
0000 00000001 output transitions occur versus a change in power-supply
voltage.
1. Unless otherwise indicated, listed specifications apply for all MN5245.
MN5245A. MN5246 and MN5246A models. Drift specifications apply over
each device's specified temperature range as selected by part number
suffix.
2. One LS TIL load is defined as sinking 20"A with a logic "1" applied and
sourcing 0.4mA with a logic "0" applied.
3. FSR FuliScale Range. ForboththeMN5245and MN5246, FSR 5volts.
For a 12·bit converter, 1LSB = 0.024% FSR.
4. Full scale accuracy specifications apply at positive full scale for unipolar
input ranges and at both positive and negative full scale for bipolar input
ranges. Full scale accuracy error is defined as the difference between the
ideal and the actual input voltage at which the digital output just changes
from 1111 1111 1110 to 1111 1111 1111 for unipolar and bipolar input
ranges. Additionally, it describes the accuracy of the 0000 0000 0000 to
0000 0000 0001 transition for bipolar input ranges. The former transition
ideally occurs at an input voltage 1 % LSB's below the nominal positive
full scale voltage. The latter ideally occurs % LSB above the nominal
negative full scale voltage. See Digital Output Coding.
5. Unipolar offset error Is defined for the MN5245 and MN5245A as the dif·
ference between the actual and ideal input voltage at which the 0000 0000
0000 to 0000 0000 0001 transition occurs. The ideal value at which this
transition should occur is + % LSB. See Digital Output Coding.
6. Bipolar zero error is defined as the difference between the actual and the
ideal input voltage at which the 0111 1111 1111 to 100000000000 transi·
tion occurs for the MN5246 and MN5246A. The ideal value at which this
transition should occur is - % LSB. See Digital Output Coding.
=
=
Specifications subject to change without notice as Micro Networks
reserves the right to make improvements and changes in its products.
BLOCK DIAGRAM
.---Analog (I)
Inpul
,---
MSB
1 - - ' - - - - - - 0 134) MSB
S,/'
7·Bil
Flash
s,"]-
Dlg,la l
Eno'
COHeClion
Latch
AID
Convertef
l"Qlf
LSB
'----
-
R.I
Slart (36)
Convert
TlH Conlfol (20I
SlatuS (17)
y
rl
-
I
Timing
Acd
Conlrol
LogiC
Gain
r>
.
~
IF
r--
- - - 0 (33) BII 2
(32) BII 3
~ 3~~~~;~ ~
r----
~
(Nole 31
t-
(31) Bit.
- - - - 0 (30) B,15
~
~~
(29) BI\6
128) B.17
13710u-tpulEnable
10E. Note 31
12n BI18
BI19
3Stale~ (261
12518,\ 10
Latch
I~~::e;l~ 1241 e,t
-
7·BII
0"
Cconverter
'----
-~
1
0191
rOl'~OOl,,:i3'
II
(231 LSB
.'5V Supply
- 15V Supply
Analog
12. 7.121 Grou-nd
----~I.---.-
~
~
'----0
l
Log<
L:8
135)B117
(7) Ou!pll!Enable(OE)
~
~
I------<'
o
-----h=
(34) Bit 8
(33) Bit 9
(32) 81110
(31) Bll11
(30) B" 12
(lSB)
(1 7) +15V Supply (+Vcc)
O.D1/iF
(2 5} -"VSopplv(-Vccl
O.D1"F
~
NC
r
--
I
.-------
00 (4) MSB
--",-
18 13 IS 16 19 241 0 - - - - -
~
I
I
20,". 23.2B} '""ogGm"d
0 (14) -S2V Supply (-Vdd)
--IT"----O
"No Connects" (N.C.) are not connected to internal Circuitry.
(>8.
001,F
(5,29.40) +5VSuppty(+Vdd)
°.Dl"F
- - - + - - - - - 0 (6.26,39) DIgital Ground
6·111
PIN DESIGNATIONS
•
40
20
21
Pin 1
NOTES:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
Bit 3
Bit 2
Bit 1 (MSB)
MSB
+5V Supply (+Vdd)
Digital Ground _
Output Enable (OE)
N.C.
Over/Underrange (OR/UR)
T/H Control
Status (E.O.C.)
Start Convert
N.C.
-5.2V Supply (-Vdd)
N.C.
N.C.
+ 15V Supply (+Vcc)
Analog Ground
N.C.
Analog Ground
'31
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
+5V Supply (+Vdd)
Digital Ground
Bit4
Bit 5
Bit 6
Bit 7
Bit8
Bit9
Bit 10
Bit 11
Bit 12 (LSB)
+5V Supply (+Vdd)
Analog Ground
Reference Output ( + 5V)
Digital Ground
-15V Supply (-Vcc)
N.C.
Analog Ground
Analog Input
Analog Ground
1. "No Connects" (N.C.) are not connected to internal circuitry.
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-MN5249 is a multistage (twostep) AID converter. It employs the Micro Networks Serial-Parallel
conversion technique (sometimes referred to as the subranging
technique) with digital error correction. The technique uses two 7-bit
flash AID converters (actually a single 7-bit flash converter is used
twice) in a configuration that yields a resolution (12 bits) that is
beyond the practical limits of what can be achieved in a single highresolution flash converter. The technique trades off speed against
resolution, and in the case of MN5249 against size, as putting the
device in a single DIP package necessitates additional considerations. For a detailed discussion of the Serial-Parallel conversion
technique and digital error correction, please refer to the
MN5245/5246 data sheet.
Start Convert must be a positive pulse with a minimum pulse width
of 50nsec (100nsec maximum if continuously converting at maximum conversion rate) and must remain low during the conversion.
The rising edge of Start Convert resets the timing logic ensuring
that all timing pulses are set to the proper state and that the first conversion following "power on" produces valid digital output data. The
falling edge of Start Convert initiates the conversion setting T/H Control and Status (E.o.C.) to logic "1 's". The T/H Control remains a logic
"1" for 300nsec maximum after the falling edge of Start Convert
and returns to a logic "0" signaling that the "analog-processing"
portion of the conversion is complete and that a constant-value
analog input signal is no longer required. Status remains a logic "1"
for 400nsec maximum after the falling edge of Start Convert. Status
returning low, signifies that the conversion process is complete and
that parallel output data is valid.
The T/H Control signal enables designers to achieve maximum
sampling rates from T/H-A/D pairs (MN376-MN5249 for example)
by allowing the T/H to acquire the next analog voltage to be converted during the digital error correction process rather than waiting
until the fall of Status.
Valid parallel output data is available on the falling edge of Status
and remains valid during the next conversion for 280nsec (typ) after
the next falling edge of Start Convert. See Timing Diagram. This
allows the use of rising and falling edges of either Start Convert or
Status for latching output data.
6-112
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy and performance from the MN5249. Analog Ground (pins 18, 20, 21, 23, 28)
is not connected internally to Digital Ground (pins 6, 26, 39). All
ground pins should be tied together as close to the unit as possible and connected to system analog ground, preferably through a
large analog ground plane underneath the package. If p.c. card
ground lines must be run separately, wide conductor runs should
be used with O.D1!,F ceramic capacitors interconnecting them as
close to the package as possible.
Coupling between analog inputs and digital signals should be
minimized to avoid noise pick-up. Care should be taken to avoid long
runs or analog runs close to digital lines.
Power supply connections should be short and direct, and all power
supplies should be decoupled with high-frequency bypass
capacitors to ground_ 11' F tantalum capacitors in parallel with 0.011' F
ceramic capacitors are the most effective combination. Single 1!,F
ceramic capacitors can be used if necessary to save board space.
A 0.11' F capacitor should be connected from Reference Output (pin
27) to system analog ground.
Pms 5,
29~ 40
0
Pins 6, 26, 39
Pm 14
I
I
I
I
I
I
I
I
+5V
,++
Pin 17 c
Digital
Ground
-S.'N
P,ns 18, 20,
21,23,28
Pm 25 c
I
I
Analog
Ground
Pms 18. 20,
21,23,28
POWER SUPPLY DECOUPLING
I
I
+15V
Analog
Ground
-15V
TIMING DIAGRAM
0.0
I
Time (nsec)
Start Convert
250
I
I
I
I
I
I
I
I
I
I
500
I
I
I
I
I
I
I
I
I
750
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~t-1L..·:~~~~~~~~~-4-00-n-se-c-=--=--_-_-_-_-_-_-"'-_~I---'II~--------------
--.J
AID Status
L---.Jr:,,;;:::=====-3!35~5inn;'se;;:c~===..
;:J.I___
T/H Control
~
Output Data
:J______~V::;al::..:id'___ _ _ _~...._ _ _ _ _ _...:Vc:a"'lid~_ _ _ _ _~C
TIMING DIAGRAM NOTES:
1. Minimum start convert pulse width is 50nsec. The rising edge of start convert resets
internal liming circuits ensuring that T/H Control (pin 10) is set to a logic "0" and
that the first conversion made upon "powerup" is valid. The falling edge of Start
Convert initiates the conversion, and Start Convert must remain low for 350nsec
minimum. See section labeled Start Convert.
2. Status rises to a "1" Iypically 45nsec after the falling edge of Start Convert.
3. Conversion time is defined as the time from the falling edge of Start Convert to the
falling edge of Status and is specified as 400nsec maximum.
4. Digital output data from the previous conversion remains valid typically 280nsec
after the falling edge of Start and 235nsec after the rising edge of Status.
REFERENCE IN/OUT, GAIN ADJUST-Pin Z7 on MNS249 serves
a unique function. The device's internal +SV ±2% reference is
brought out at this point and can be used to drive external loads.
If used forthis purpose, pin Z7 should be buffered with a FET-input
device as drawing more than SpA from the internal reference will
affect MNS249 accuracy and linearity. Pin Z7 can also be used as
a Reference In point if it is necessary to operate MNS249 from an
external reference. An application requiring an external reference
might be one in which it is necessary to have a number of devices
operate from the same reference in order to track each other in
changing temperatures. The applied reference should be +SV
±2S0mV.
Pin Z7 also functions as the gain-adjust point for MNS249. Gain adjustment is accomplished using a 10kO to 100kO trimming potentiometer and a SOOkO series resistor as shown below. The series
resistor can be ± 20% carbon composition or better. The multiturn
potentiometer should have a TCR of 100ppm/oC or less to minimize
drift with temperature. Gain adjusting is normally accomplished by
applying the analog input voltage at which the 111111111110 to 1111
1111 1111 digital-output transition is ideally supposed to take place
and adjusting the pot until the transition is observed.
5. Digital output dala is valid on the falling edge of Status.
o. Output data is enabled and becomes valid a maximum of 50nsec after Output
Enable (OE, pin 7) is brought low. See section labeled Output Enable.
7. The falling edge of T/H Control occurs 300nsec maximum after the falling edge of
Start Convert. See section labeled Slart Convert.
OVERRANGE/UNDERRANGE-An overrangetunderrange o u t - I -','
put (ORtUR, pin 9) is provided and will be set to a logic "1" if an
over or underrange condition exists. An input voltage 1 LSB more
positive than the voltage at which the 1111 1111 1110 to 1111 1111
1111 transition occurs will set the ORtUR outputto a logic "1" and
parallel output bits will remain at all "1 's". Similarly, an input voltage
1 LSB more negative than the voltage at which the 0000 0000 0001
to 0000 0000 0000 transition occurs will set the ORtUR output to
a logic "1" and parallel output bits will remain at all "D's."
STATUS OUTPUT/DATA VALID-The Status or End of Conversion
(E.O.C., pin 11) is setto a logic "1" by the falling edge of Start Convert; remains high during the conversion; and is set to a logic "0"
when the conversion is complete. Digital output data is valid on
the falling edge of Status and remains valid 280nsec after Start
Convert goes low initiating the next conversion. When making successive conversions, any olthe edges occurring during the beginning olthe data-valid period (fall of Status, falling edge olthe next
Start Convert, rising edge of Status, etc.) are best suited for this
purpose. Also, output data can be ~bled during this data-valid
period by bringin~tput Enable (OE, pin 7) low. The delay from
the falling edge ofOE to output data enabled is SOnsec maximum.
+ 15V
Pin 27 o--~~---'lIJ\ftr-~~~
Gain Adjust Range
= ± 0.2%
10kll
to
100kll
FSR
6-113
TRACK/HOLD CONTROL-The Track/Hold Control (T/H Control,
pin 10) output is provided so that designers can achieve maximum
throughput without additional glue chips when using a track-hold
amplifier with MN5249. This output signal is set to a logiC "1" by
the falling edge of Start Convert and remains high during the
"analog-processing" portion of the NO's conversion cycle. It drops
back low when the "digital-processing" portion of the conversion
cycle commences, signaling that it is no longer necessary to maintain a stable analog input. Use of this signal allows a companion
T/H amplifier to acquire and track the next analog input signal to
be converted during the "digital-processing" portion of the present
conversion. T/H Control remains low until the falling edge of the next
Start Convert signal.
The diagram below shows the MN376, high-speed T/H amplifier and
the MN5249 configured as a 2M Hz, 12-bit sampling system. Maximum throughput is achieved because the MN376's T/H Command
input is driven directly by the MN5249's T/H Control output.
MN376-MN5249 2MHz Sampling System
Start Convert
0------------,
+5V + 15V -15V -5.':N
+5V + 15V -15V
Status
OR/UR
MSB
Analog Input
(22)
MN5249
LSB
(30)
DE
(7)
'-----i(10)
0.1 p F
Start Convert
Status
DL..________________.....JIL
L..-------.JI
-----II
Track
'---_
_--III
Hold
T/H Control _ _ _.......1
Parallel Output - - - - - - - - - - - - - - , , - - - , , - - - - -
Data
Data valid N-1 Conversion
Data valid N Conversion
I
Time (nsec)
100
200
300
I
400
I
I
I
500
DIGITAL OUTPUT CODING
Analog Input
MN5249
+2.5000
+2.4982
+0.0006
-0.0006
-0.0018
-2.4994
-2.5000
Digital Output
LSB
MSB
1111 1111 1111
11111111111~"
1000 0000 ooolt"
NOTES:
1. For a 12-bit converter with a 5 Volt FSR. lLSB=I.22mV.
2. Coding is offset binary.
·Analog voltages listed are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as (6 will change
from a "1" to a "0" or vice versa as the input voltage passes through the level indicated.
~(6(6f6 (6~r;1(6 (6(6m,-
011111111110'"
ooooooooooor;1"
0000 0000 0000
[LJJ
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606
6-114
(508) 852-5400
MN5250 Series
_
LOW-POWER
CMOS, 12-Bit
NO CONVERTERS
MICRO NETWORKS
DESCRIPTION
FEATURES
MN5250 Series devices are extremely low-power, 12-bit, successive approximation AID converters in industry-standard,
24-pin, ceramic, dual-in-line packages. Power consumption is
80mW maximum.
• Low Power
80mW Maximum
• Small 24-Pin DIP
• Linearity and
No Missing Codes
Guaranteed Over
Temperature
• ±O.1% FSR Absolute Accuracy
• Totally Adjustment Free
No Full-Scale or Zero
Adjustments Necessary
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
Combining the advantages of highly stable thin-film resistors,
functional laser trimming and hermetic packaging, the MN5250
Series offers designers the ultimate in convenience for highresolution, low-power analog-to-digital conversion. All devices
are supplied complete with internal reference, and no external
trimming components or adjustments are necessary to meet
published specifications.
Four input voltage rages are offered, and all units are fully
specified and 100% tested for linearity and accuracy at their
operating temperature extremes as well as at room temperature.
All models of the MN5250 Series may be procured for operation
over the full -55°C to + 125°C military temperature range ("H"
models) or the O°C to +70°C commercial temperature range.
For military/aerospace or harsh-environment commercial/industrial applications, "H/S CH" models are fully screened to
MIL-H-38534 in Micro Networks MIL-STD-1772 qualified facility.
The MN5250 Series is the ideal choice for designs requiring
high resolution and low power consumption. Their small size,
low power consumption and adjustment-free operation make
them excellent selections for compact, highly reliable systems.
Typical applications include remote-site seismological monitoring, precision portable instruments and high-accuracy industrial
instrumentation.
24 PIN DIP
0;B
OOB7~
PIN 1
\
°""'' '1
1.100(2794)
1 ui,j. ,
r- "'"'" -1 ~
0B10(2OSn
~."'ll
0020(0'"
0230(5.84)
~0120(3.05)
0.170(4.32)
~0600(1524)-.l
Dimensions in Inches
(millimeters)
May 1988
O:::JJ
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-115
MN5250 SERIES LOW-POWER CMOS 12-Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
O·C to +70·C
-SS·C to +12S·C ("H" Models)
-6S·C to +IS0·C
+18 Volts
-18 Volts
-O.S to+16 Volts
±2S Volts
-O.Sto +Vdd
Storage Temperature
+12V Supply (Pin .IS)
-12V Supply (Pin 13)
Logic Supply (+Vdd, Pin 2)
Analog Input (Pin 14)
Digital Inputs (Pins " 24)
ORDERING INFORMATION
PART NUMBER
MN525X H IB CH
Select MNS2S0, MNS2S1, MNS2S2, or MNS253. .--.J
Standard Part is specified for O·C to +70·C
operation.
Add "H" suffix for specified -SS·C to +12S·C
operation. -------------~
Add "/B" to "H" devices for
Environmental Stress Screening. _ _ _ _ _ _ _..J
Add "CH" to "H/B" devices for 100%
screening according to MIL-H-38S34. - - - - - - - - '
SPECIFICATIONS (T.. = +2S· C, Supply Voltages ±12V and +SV, unle.. otherwise specified).
+Vdd
ANALOG INPUTS
Input Voltage Range (Input Impedance): MNS2S0
MNS2S1
MNS2S2
MNS2S3
MIN.
(SOKO)
(SOKO)
(100KO)
(SOKO)
TYP.
MAX.
UNITS
Volts
Volts
Volts
Volts
Oto-l0
- Sto+ S
-10 to +10
o to +10
DIGITAL INPUTS
Logic Levels (Note 1): Logic "1"
+ SV
+12V
+ SV
+12V
Logic "0"
3.S
8.4
1.S
3.S
Loading: Input Current
Input CapaCitance (Vin=OV)
Start Convert Input: Pulse Width
Setup Time Start High to Clock
Clock Input: Frequency (Note 2)
Positive Pulse Width (Note 3)
Rise and Fall Times (Note 3)
10
S
+ 5V
+12V
+ 5V
+12V
750
250
300
ISO
+ SV
+12V
+ SV
+12V
600
300
Volts
Volts
Volts
Volts
pA
pF
nSec
nSec
nSec
nSec
71
15
4
KHz
nSec
nSec
"Sec
"Sec
TRANSFER CHARACTERISTICS
±1f.4
Linearity Error (Note 4): +2S· C
O·C to +lO·C
-SS· C to +125· C ("H" Models)
±Y..
±v,
±1f2
Differential Linearity Error
No MIssing Codes (O·C to +lO·C)
±v,
±1f2
±1
LSB
LSB
LSB
LSB
Guaranteed
Full Scale Absolute Accuracy Error (Notes S, 6):
+2S·C
O·C to +lO·C
-SS·C to +12S·C ("H" Models)
± 0.05
± 0.2
± 0.3
± 0.1
± 0.5
± 0.6
%FSR
%FSR
%FSR
Zero Error (Notes 5, 6): +25· C
O·C to +70·C
-SS·C to +12S·C ("H" Models)
± 0.01
± 0.04
± 0.05
± 0.1
± 0.1
%FSR
%FSR
%FSR
Gain Error (Note 5)
Gain Drift
± 0.05
±20
%
ppm/·C
DYNAMIC CHARACTERISTICS
Conversion Time (Note 2)
Analog Input Settling Time (Note 8)
17S
2
"Sec
"Sec
DIGITAL OUTPUTS
Logic Coding (Note 9): Unipolar Ranges
Bipolar Ranges
Logic Levels (Note 1): Logic "1"
Logic "0"
Output Drive Current, All Outputs:
Logic "1" (VOH=2.SV)
(Vo~IIV)
Logic "0" (VoL=O.4V)
(VoL=I.SV)
6-116
Complementary Straight Binary
Complementary Offset Binary
+ SV
+12V
+ SV
+12V
4.95
11.95
+ SV
+12V
+ SV
+12V
0.2
0.3
0.1
1.0
0.01
0.05
1.7
1.0
0.6
4.0
Volts
Volts
Volts
Volts
mA
mA
mA
mA
+Vdd
REFERENCE OUTPUT
MIN.
TYP.
MAX.
UNITS
10
Volts
%
ppm/oC
p.A
+12.36
-12.36
+12.36
Volts
Volts
Volts
- 6.3
± 5.
±15.
Internal Reference: Voltage
Accuracy
Tempco of Drift
Ext. Current Without Buffering
POWER SUPPLY REQUIREMENTS
+11.64
-11.64
+ 4.75
Power Supply Range (Note 10): +12V Supply
-12V Supply
+ 5V Supply
+12.00
-12.00
+ 5.00
%FSR/%Vs
%FSR/%Vs
%FSR/%Vs
Power Supply Rejection: +12V Supply
-12V Supply
+ 5V Supply
± 0.003
± 0.03
± 0.0003
Current Drain: +12V Supply
-12V Supply
+ 5V Supply
2.4
- 2.0
0.5
3.5
- 2.7
1.0
mA
mA
mA
56
80
mW
Power Consumption
SPECIFICATION NOTES:
1. The +Vdd Logic Suppy (Pin 2) can be at any voltage between +5V (low
power TTL compatibility) and +12V (CMOS compatibility).
2. Conversion Time is defined as the width of the converter's STATUS
(E.O.C.) pulse. See Timing Diagram. For MN5250 Series AID's, a 175 p.Sec
conversion time corresponds to an external clock frequency of 71 KHz.
Micro Networks guarantees linearity and absolute accuracy at and below
this clock frequency.
3. The clock may be asymmetrical, and it may ramp up and down as long as it
meets minimum pulse width and maximum rise and fall time requirements.
4. Micro Networks tests and guarantees maximum linearity error at room
temperature and at the high and low extremes of the specified operating
temperature range.
5. See the tutorial section of the Micro Networks' Product Guide and
Applications Manual for an explanation of how Micro Networks defines Full
Scale Absolute Accuracy, Zero, and Gain Errors. For MN5250 Series AID's
we 100% test Full Scale Absolute Accuracy Error and Zero Error at room
temperature and at the high and low extremes of the specified operating
temperature range.
6. 1 LSB for a 12 bit converter corresponds to 0.024%FSR. See Note 7.
7. FSR stands for Full Scale Range and is equal to the peak to peak input
voltage of the selected converter. Forthe MN5250, MN5251, and MN5253,
FSR = 10V, and 1 LSB = 2.44mV. For the MN5252, FSR = 20V, and 1LSB =
4.SSmV.
8. Analog Input Settling Time is the time required for the input circuitry to
settle to within ±1h LSB for a 10V step in input signal.
9. Serial and parallel output data have the same coding. Serial data is in
Non-Return to Zero (NRZ) format. See Output Coding and Timing
Diagram.
10. The recommended range for the ±12V supplies is ±3%. Units will operate
over a range of ±10V to ±14V with reduced accuracy.
PIN DESIGNATIONS
BLOCK DIAGRAM
Start Convert (1) 0 - - Clock Input
SUCCESSIVE
APPROXIMATION
REGISTER
(24) 0 - - -
(3)
(MSB)
(S)
Bit 2
+12V Supply (15) ~
(7)
Bit 3
-12V Supply (13) ~
(S)
+Vdd Supply
Bit 4
Bit 5
(2) ~
Ground
(11) ~
(5)
(4)
Ground
(23) ~
(21) Bit 7
Bit 6
(20) Bit S
(19) Bit 9
(1S) Bit 10
(17) Bit 11
(1S) (LSB)
Analog Input (14)
DIA CONVERTER
AU
~,~
I
I
24
PIN 1
Serial Out
(9)
Ref. Out
(12) 0 - - (-S.3V)
•
(22) Status Out
12
13
Pin 1.
Pin 2.
Pin 3.
Pin 4.
Pin 5.
Pin 6.
Pin 7.
Pin 8.
Pin 9.
Pin 10.
Pin 11.
Pin 12.
Start Convert
Logic Supply (+Vdd)
Serial Output
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
N/C
Ground
Ref. Out (-6.3V)
Pin 13.
Pin 14.
Pin 15.
Pin 16.
Pin 17.
Pin 18.
Pin 19.
Pin 20.
Pin 21.
Pin 22.
Pin 23.
Pin 24.
-12V Supply
Analog Input
+12V Supply
Bit 12 (LSB)
Bitll
Bit 10
Bit 9
Bit 8
Bit 7
Status (E.O.C.)
Ground
Clock Input
'--
~"
ARATOR
6·117
TIMING DIAGRAM
Clock
MSB
ZLL!lllll1l..4
Bit 2
W/WOO/l
10
OZ/WZZZ/4
Bit4WOOOO/l
r---,~o
Bil 3
__________________________________________
~-----
Bit 5 W/ZZZOZ/4
~r---.--------------------------~-----
BitSOZOWWJ
Bit 7
r---l~0________________________+ _ - - - -
WOZWZZ4
Bit 8 ZllllllllU'-!iI _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- '
Bit 9
OZZlOOl/~
r---l~0________________~----
Bil 10
zzz//ooo4
r---l~0__________~-----
Bit 11
/00177014
LSB
ZlWZlOZ!A
Status
Serial Output
/7777wwmOZZIll
~
MSB
Bit 4
Bit 5
TIMING DIAGRAM NOTES:
Bil S
Llill.l..JEiTt8
Bit 9
Bit 10
I
Bit 11
Bit 12
5. The delay between the resetting clock edge and the Status actually dropping to a "0" is 750nsec maximum.
S. The Status (E.O.C.) output will rise to a "1" 750nsec (maximum) after
the firslfalling clock edge after the determination of LSB. Status will remain high until the converter is reset. Parallel output data is valid as long
as Status is a "1".
7. Both serial and parallel data bits become valid on the same rising clock
edges. Serial data is valid on subsequenlfalling clock edges, and these
edges can be used to clock serial data into receiving registers.
8. For continuous conversion, connecllhe Status output pin (pin 22) to the
Start Convert input (Pin 1).
9. When the converter is initially "powered up", it may come on at any point
in the conversion cycle.
1. Operation shown is for the digital word 0101 11010011 which corresponds to S.357V on the 0 to + 1OV (MN5253) input range. See Output Coding.
2. Conversion Time is defined as the width of the Status (E.O.C.) pulse.
3. The converter is reset (MSB = "1 ", all other bits = "0", Status = "0") by
holding the Start Convert high during a low to high clock transition; the
Start Convert must be high for a minimum of 300nsec prior to the clock
transition. Output bits, starting with the MSB, will be set totheir final values
on succeeding clock edges. The Start Convert must return low prior to
the falling edge of the fourth clock cycle after conversion commences.
4. The Start Convert may be brought high at any time during a conversion
to reset and begin converting again.
DIGITAL OUTPUT CODING
DIGITAL OUTPUT
ANALOG INPUT
MN5250
MN5251
MN5252
MN5253
O.OOOOV
- 0.0024V
+ 5.0000V
+ 4.9976V
+10.0000V
+ 9.9951V
+10.0000V
+ 9.9976V
0000 0000 0000
0000 0000 0000"
- 4.9976V
- 5.0000V
- 5.0024V
+ 0.0024V
O.OOOOV
- 0.0024V
+ 0.0049V
O.OOOOV
- 0.0049V
+ 5.0024V
+ 5.0000V
+ 4.9976V
011111111110"
0000 0000 0000"
100000000000"
- 9.9976V
-10.0000V
- 4.9976V
- 5.0000V
- 9.9951V
-10.0000V
+ 0.0024V
O.OOOOV
111111111110"
111111111111
• Voltages given are the theoretical values forthe transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as 0 will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.,
EXAMPLE: For an MN5252 (±10V analog input range) the transition from
digital outpull11111111111 to 111111111110 (or vice versa) will ideally occur
APPLICATIONS INFORMATION
The digital circuitry used in the MN5250 Series AID's is
CMOS. The standard precautionary measures for handling
CMOS should be followed.
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN5250 Series converters. The units' two GROUND
pins (Pins 11 and 23) are not connected internally. They
should be tied together as close to the package as possible
and connected to system analog ground, preferably through
a large ground plane underneath the package. If the grounds
cannot be tied together and must be run separately, a nonpolarized 0.01 /-IF bypass capacitor should be connected
6-118
MSB
LSB
at an input voltage of -9.9951 volts. Subsequently, any input voltage more
negative than -9.9951 volts will give a digital output of all "l's': The transition
from digital output 1000 0000 0000 to 01111111 1111 (or vice versa) will ideally
occur at an input of zero volts, and the 0000 0000 0000 to 0000 0000 0001
(or vice versa) transition should occur at +9.9951 volts. An input greater
than +9.9951 volts will give all "D's".
between Pins 11 and 23 as close to the unit as possible ano
wide conductor runs employed.
Power supplies should be decoupled with tantalum or
electrolytic capacitors located close to the converters. For
optimum performance and noise rejection, 1/-1F capacitors
paralleled with O.Q1/-1F ceramic capacitors should be used
as shown in the diagram below.
Pin 15<>c-'I---'1r-- +12V
Pin20
1 ~F
Pin 11,
I
23c~_IL-
I
I~FI
+5V
10.01 ~F
I001~F
Pin 11, 230
_ _.J_--Ground
Ground
1 "F I
Pin 130
-
10.Q1 "F
-
-12V
MN5284 Series
__ MICRO NETWORKS
LOW-POWER
16-Sit
AID CONVERTERS
DESCRIPTION
FEATURES
An outstanding combination of resolution, speed, packaging,
power consumption and price may make the MN5284 Series
the best high-resolution AID converters ever put in dual-in-line
packages. Featuring 16-bit resolution and a maximum 50!-,sec
conversion time, MN5284 Series AID's are packaged in 32-pin,
side-brazed, ceramic DIP's and have an impressively low
300mW maximum power consumption when operating from
± 15V and +5V supplies. ± 12V supplies may also be used.
• 16-Bit Resolution
• 15-Bit No Missing Codes
• 300mW Max Power
Consumption
• 50!,sec Max Conversion Time
• Serial and Parallel Outputs
• True-TTL and 5V-CMOS
Compatible
These are successive approximation type AID's fabricated in
thin-film hybrid technology. Each employs a recently developed
HCf CMOS successive approximation register and a proprietary, low-power, partially segmented, bipolar DAC that is inherently monotonic. "No missing codes" to the 15-bit level and
true integral linearity to the 14-bit level are guaranteed over the
device's entire O°C to +70°C specified temperature range.
• Small 32·Pin Side·
Brazed DIP
• ±12V to ±15V Power
Supply Range
• 8 User-Selectable
Input Voltage Ranges
Each AID is complete with internal reference and clock and is
truely compatible with either TTL or 5V-CMOS logic families.
Digital input currents are specified at ± 10~ max, and fanout is
2 standard TTL loads.
32 PIN SIDE·BRAZED DIP
\
1r
, T1
D.Ol0(O.251
0.030 (0.78)
PIN1
0.100(2.54)
: : 'J
t
0.900(22.86)
j
0.920(23.371
_1 J ~: :
~:~~:!:~:
~
0.190(4.83)
O.210(5.3~!
If==~=O'20====j~I t
0.012(0.31)
I---
0.900 (22.86)
Originally designed for remote, lightweight, battery-operated
data acquisition applications, MN5284 Series devices are extremely versatile. Their 50/Lsec max conversion time permits
167kHz data throughputs when used with Micro Networks MN373,
High-Resolution Track-Hold Amplifier (10!-,sec max acquisition
time to ±O.003%, 300mW power consumption). Serial and
parallel data outputs and optional CSB, COB and CTC output
coding permit various data transmission and processing
schemes, and devices may be short cycled to any resolution
with a proportionately faster conversion time. Four part numbers
in the Series offer the input voltage ranges shown below.
Number
Unipolar
Input Range
Bipolar
Input Range
LSB@
14·Bits
LSB@
16-Bits
MN5284
MN5285
MN5286
MN5287
Oto -20V
o to -16.384V
Oto -1OV
Oto -8.192V
±10V
±a192V
±5V
±4.096V
1.22mV
1mV
0.61mV
0.5mV
305.21'V
25Ol'V
152.61'V
1251'V
Part
--....1
Dimensions in Inches
(millimeters)
~
December 1991
Copyright 1991
MICRO NETWORKS
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
6·119
MN5284 SERIES LOW·POWER 16·Bit AID CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN5284, 85, 86, 87
Storage Temperature Range
Positive Supply ( + Vee, Pin 30)
Negative Supply ( - Vee, Pin 31)
Logic Supply ( + Vdd, Pin 17)
Analog Input (Pin 25)
Digital Inputs (Pins 22,24)
SPECIFICATIONS (TA
ORDERING INFORMATION
PART NUMBER - - - - - - - - - - M N 5 2 8 X
Select desired input voltage range.
I
- 55°C to + 125°C
O°C to + 70°C
- 65°C to + 150°C
- 0.5 to + 18 Volts
+ 0.5 to -18 Volts
- 0.5 to + 7 Volts
Nominal ± 5Volts
oto + 5.5 Volts
= + 25°C, ± Vee = ± 15V, + Vdd =+ 5V unless otherwise indicated)
ANALOG INPUTS
MIN.
Input Voltage Ranges (Note 1): Unipolar (MN5284, 85, 86, 87)
Bipolar (MN5284, 85, 86, 87)
Input Impedance: 0 to
Oto
o to
Oto
TYP.
UNITS
MAX.
Oto -20, -16.384, -10, -8.192
±10, ±8.192, ±5, ±4.096
Volts
Volts
20
16.384
10
8.192
kll
kll
kll
kll
- 20V,.± 10V (MN5284)
-16.384V, ±8.192V(MN5285)
-10V, ± 5V (MN5286)
-8.192V, ±4.096V(MN5287)
DIGITAL INPUTS
Logic Levels (Note 2): Logic "1"
Logic "0"
Logic Currents (V IH = +5V, VIL = OV, Note 2)
Start Convert Command Positive Pulse Width (Note 3)
..,,Volts
Volts
+2.0
+0.8
~A
±10
1
-'.
TRANSFER CHARACTERISTICS (Note 4)
Resolution
~sec
Bits
16
Integral Linearity Error (Note 5): Initial (+ 25°C)
Over Temperature (Note 6)
± 0.0015
±0.003
±0.003
%FSR
%FSR
Differential Linearity Error: Initial (+ 25°C)
Over Temperature (Note 6)
±0.0015
± 0.003
± 0.006
%FSR
%FSR
+ 70
°C
Temperature Range for Guaranteed 15·Bit No Missing Codes
M N5284, 85, 86, 87
0
Full Scale Absolute Accuracy Error (Note 7):
Unipolar: Initial (+ 25°C)
Over Temperature (Note 6)
Bipolar: Initial (+ 25°C)
Over Temperature (Note 6)
±0.05
±0.1
±0.05
±0.1
±0.1
±0.2
±0.15
±0.25
%FSR
%FSR
%FSR
%FSR
Unipolar Offset Error (Notes 8, 9): Initial (+ 25°C)
Over Temperature (Note 6)
Drift
±0.025
±0.05
±2
±0.1
±0.15
%FSR
%FSR
ppm of FSR/oC
Bipolar Zero Error (Notes 8,10): Initial (+25°C)
Over Temperature (Note 6)
Drift
±0.05
±0.1
±5
±0.12
±0.2
%FSR
%FSR
ppm of FSR/OC
Gain Error (Notes 8,11): Initial (+25°C)
Over Temperature (Note 6)
Drift
±0.05
±0.1
±5
±0.1
±0.2
±15
%
%
ppm/oC
+0.4
Volts
Volts
DIGITAL OUTPUTS
Logic Levels (Note 2): Logic "I" (lsOURCE :s400I'A)
Logic "0" (lSINK :s 3.2mA)
Output Coding (Note 12): Unipolar Ranges
Bipolar Ranges
+3.5
CSB
COB,CTC
REFERENCE OUTPUT
Internal Reference: Voltage
Accuracy
Tempco
External Current
6-120
- 9.000
±0.025
±5
±0.05
1
Volts
%
ppm/oC
mA
DYNAMIC CHARACTERISTICS (Note 13)
MIN.
Conversion Time (16 Bits)_.(Note 14)
Internal Clock Frequency
TYP.
MAX.
UNITS
45
50
"sec
kHz
75
40
150
80
nsec
nsec
35
70
320
=
Delay Falling Edge of Start to: Status "1"
Clock Output
="1"
Delay Rising Clock Edge to Output Data
Valid (Parallel, Serial, Status)
Delay LSB valid to Falling Edge of Status
40
POWER SUPPLIES
Power Supply Range (Note 15): ±V~ Supply
+Vdd Supply
±11.4
+4.75
Power Supply Rejection: + Vee Supply
-Vee Supply
+Vdd Supply
Current Drains: + Vee Supply
-Vec Supply
+ Vdd Supply
Power Consumption (± Vcc
= ± 15Vl
±16
+5.25
±15
+5
Volts
Volts
±0.001
±0.001
±0.001
%FSR/% Supply
%FSR/% Supply
%FSR/% Supply
9
-5
9
mA
mA
mA
255
SPECIFICATION NOTES:
1. Oto -16.384Vand ±8.192V input ranges correspond to 1 LSB = 1mVfor14
bits or 1 LSB = 'l.mV for 16 bits. 0 to -8.192V and ±4.096V input ranges
correspond to 1 LSB = 'j, mV for 14 bits and 1 LSB = Y,mV for 16 bits.
2. Digital portions of MN5284 Series AID's are implemented with HCT CMOS
logic and devices are true TTL and 5V CMOS compatible with specified logic
levels and currents guaranteed over each devices entire specified temperature range.
3. Conversion is initiated on falling edge of Start Convert command; see timing diagram.
4. FSR = full scale range. A unit connected forO to + 10Vor ±5Voperation has
a 10V FSR.A ± 10V unit hasa20V FSR. A ±8.192V unit hasa 16.38V FSRetc.
1 LSB for 16 bits is equivalent to 0.00153%FSR, 1 LSB for 15 bits is equiva·
lent to 0.00305%FSR.
5. ±O.003%FSR is equivalent to ± Vz LSB for 14 bits. ::to.0015%FSR is
equivalent to ± % LSB for 15 bits.
6. Listed specifications apply over the DoC to + 70°C temperature range for
standard products.
7. Full scale absolute accuracy error includes offset, gain, linearity, noise, and
all other errors and is specified without adjustment. It refers to negative full
scale accuracy for unipolar ranges and to both positive and negative full
scale accuracies for bipolar ranges.
8. Initial offset and gain errors are adjustable to zero with optional external
potentiometers or voltage output D/A converters.
9. Unipolar offset error is defined as the difference between the actual and the
ideal input voltage at which the 000000000000 0000 to 0000 0000 0000 0001
digital output code transition occurs when operating on a unipolar input
range.
nsee
nsec
300
mW
10. Bipolar zero error is defined as the difference between the actual and the
ideal input voltage at which the 1000 00000000 0000 to0111111111111111
digital output code transition occurs when operating on a bipolar input
range.
11. Gain error is defined as the error in the slope of the converter transfer function. It is expressed as a percentage and is equivalent to the deviation (divided by the ideal value) between the actual and the ideal value forthe full in·
put voltage span from the input voltage at which the output changes from all
1111111111111111 to 1111111111111110totheinputvoltageatwhich the
output changes from 0000 0000 0000 0001 to 0000 0000 0000 0000.
12. CSB = complementary straight binary. COB = complementary offset
binary. For bipolar ranges, complementary two's complement(CTC) coding
is available if the MSB output is used.
13. Listed dynamic specifications are guaranteed over each device's entire
specified temperature range.
14. Conversion time is defined as the width of the Status (End of conversion)
pulse. Conversion time may be shortened, with lower resolution, by short
cycling. Connect pin 15 (Bit 15), for example, to pin 24 (Short Cycle) for 14·bit
conversions.
15. For operation with ±Vee supplies below ±12V, only 0 to ·8.192V, ±8.192V,
±5Vand ±4.096V input ranges should be used.
Specifications subject to change without notice as Micro Networks reserves the
right to make improvements and changes in its products.
PIN DESIGNATIONS
•
32
16
11
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1 (MSB)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (LSB)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BTf1
(MSB)
- Vcc Supply (-12V/-15V)
+ Vee Supply (+ 12VI + 15V)
Ground
Gain Adjust
Reference Output ( - 9.0V)
Bipolar Offset
Analog Input
Short Cycle
Offset Adjust
Start Convert
Ground
Clock Output
Status Output (E.O.C.)
Serial Output
+ Vdd Supply (+5Vl
6·121
BLOCK DIAGRAM
Slarl Converl (22)
Clock
Successive Approximation Register
f--
(32) SB
M
1
Clock Oulpul (20)
+ Vee Supply (30) 0
(19) Sl alus Oulpul (E.O.C.)
(18) Se rialOulpul
~(24)Sh orl Cycle
(1)
(2)
(3)
(4)
(5)
(6)
(7)
)
~ O.OI.F
- Vee Supply (31)
:~ O.OI.F
+ Vdd Supply (17)
(8)
{: O.OI.F
Ground (29)
Ground (21)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
I
Ref. Oulpul (27)
Ref.
M SB
Bi 12
Bi 13
Bi 14
Bi 15
Bi 16
Bi 17
Bi 18
Bi 19
Bi 110
Bi 111
Bi 112
Bi 113
Bi 114
Bi 115
BI 116
67.6kll
Gain Adjusl (28)
16·Bil D/A Converler
1>Comparator
8.3kll
Offsel Adjusl (23)
Analog Inpul (25)
Rin
1
I
Bipolar Offsel (26 )
I
17.6kll
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS AND GROUNDING - Proper at·
tention to layout and decoupling is necessary to obtain
specified linearity and accuracy from MN5284 Series
devices. It is critically important that power supplies be
filtered, well·regulated, and free from high frequency noise.
Use of noisy supplies can easily cause unstable output codes
t< be generated. Switching power supplies are not recom·
mended for circuits attempting to achieve 12·bit or better
accuracy unless great care is used in filtering any switching
spikes present in the output.
MN5284's two ground pins (pins 21 and 29) are not connected
to each other internal to the device. It is recommended,
however, that the two pins be tied together as close to the unit
as possible and both connected to system analog ground,
preferably through a large, low-impedance, analog ground
plane beneath the package. If p.c. card ground lines must be
run separately, wide conductor runs should be used with
O.01I'F ceramic capacitors interconnecting them as close to
the package as possible.
Power supply connections should be short and direct, and
even though MN5284 has internal O.01I'F ceramic bypass
capacitors, it is recommended that all power supplies be
decoupled with additional high· frequency bypass capacitors
to ground. Foroptimum performance and noise rejection, 11'F
tantalum capacitors in parallel with O.01I'F ceramic
capacitors are the most effective combination. Single 11'F
ceramic capacitors can be used if necessary to save board
space. If the recommended ground·plane approach can not
be used and .separate p.c. card ground runs are used, the
± Vcc supplies should be decoupled to pin 29 and the + Vdd
supply to pin 21.
6·122
POWER SUPPLY OECOUPLING
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick·up. Pins 23 (Offset Adjust),
25 (Analog Input), 26 (Bipolar Offset), 27 (Reference Output),
and 28 (Gain Adjust) are particularly noise susceptible. Care
should be taken to avoid long runs or runs close to digital
lines when utilizing these pins. Input signal lines should be as
short as possible. In bipolar operation, where pin 26 is connected to pin 27, a short jumper should be used. When using
external offset and gain adjustments, the adjusting pots or
voltage·output DAC's should be located as close to MN5284
as possible. If using optional gain adjust, an O.01I'F ceramic
capacitor should be connected between pin 28 and analog
ground as close to the package as possible. Similarly, if using
the Reference Output (pin 27) to drive an external load or to
operate MN5284 in a bipolar mode, an O.01I'F ceramic
capacitor should be connected between pin 27 and analog
ground.
If short·cycling is not used, the Short·Cycle pin (pin 24) must
be connected to + 5V (pin 17).
TIMING DIAGRAM
START CONVERT
INTERNAL CLOCK
"'SB
ITITIlI
BIT 2
/1/1/;1
BIT 3
/IIIflI
BIT 4
/IJ/IA
BIT 5
/UI/II
BIT6
/l1//li
BIT 7
/1/1/11
BIT B
lllll.!J
lllll.!J
lllll.!J
lllll.!J
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16
STATUS
U'
U'
U'
U'
ZZZLZL1
ZZZllL1
Zll.lllJ
Zllil1J
ZZlllLI
-----.J
EXTERNAL CLOCK
SERIAL OUTPUT
11/1//1711)1,1 ,
~6
'5
SPECIFICATIONS (TA = + 25°C, Supply Voltages ± 1SV and + SV unless otherwise specified)
DYNAMIC CHARACTERISTICS
MIN.
Conversion Time (16 Bits)
Internal Clock Frequency
Start Convert Positive Pulse Width
MAX.
UNITS
45
50
"sec
kHz
75
40
150
80
"sec
nsec
nsec
35
70
nsec
320
1
Delay Falling Edge of Start to: Status = "1"
Clock Output = "1"
Delay Rising Clock Edge to Output Data
Valid (Parallel, Serial, Status)
Delay LSB valid to Falling Edge of Status
TYP.
40
nsec
TIMING DIAGRAM NOTES:
1. Operation shown Is for the digital word 0101011000101011.
2. The Start Convert command must be at least 1,,"ec wide and must remain
low during conversion.
3. The internal clock is enabled and the conversion cycle commences on the
falling edge of the Start Convert signal.
4. Output data will be valid 40nsec (minimum) prior to the failing edge of
Status (E.O.C.) and will remain valid until another conversion is initiated.
5. When using an external clock, the converter will continuously convert.
Each conversion will be initiated by the failing edge of the first external
clock pulse following Status going low at the end of the previous conver·
slon. See External Clock.
6. Once a conversion has begun, a second start pulse will not reset the
converter. See Start Convert.
7. When the converter is initially "powered up", it may come on at any
point in the conversion cycle.
8. Conversion time is defined as the width of the Status (End of Conver·
sian) pulse. Conversion time may be shortened, with lower resolution,
by short cycling. Connect pin 15 (Bit 15) to pin 24 (Short Cycle) for 14 bit
conversions.
6-123
START CONVERT-The Start Convert signal must be a positive pulse with a minimum pulse width of 1l'sec. The falling
edge of the Start Convert signal resets the converter and
turns on the internal clock. Status going low at the end of a
conversion turns off the internal clock. If the Start Convert
input is brought high after a conversion has been initiated,
the internal clock will be disabled halting the conversion. If
the Start Convert input is then brought low, the original conversion will continue with a possible error in the output bit
that was about to be set when the internal clock was stopped.
DESCRIPTION OF OPERATION - See Block Diagram. The
Successive Approximation Register(SAR) is a set of flip flops
(and control logic) whose outputs act as both the direct
(parallel) data outputs of the analog-to-digital converter (AID)
and the digital drive for the AID's Internal digital-to-analog
converter (D/A). The falling edge of a start convert pulse applied to pin 22 turns on the AID's internal clock and resets the
SAR.ln this state, the output of the MSB flip flop is set to logic
"0", the outputs of the other bit flip flops are set to logic "1 ",
and the Status Output (pin 19) is set to logic "1" (see Timing
Diagram). The Start Convert must now remain low for the conversion to continue.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The comparator output ("1" or "0") informs the SAR whether the present digital output (0111 1111 1111 1111 in the reset state) is
"greater than" or "less than" the analog input. Depending
upon which is greater, on the first rising clock edge after the
Start has gone low, the SAR will set the MSB to its final state
("1" or "0") and bring bit 2 down to a "0". The digital output is
now X011 1111 1111 1111. The DIA converts this to an analog
value, and the comparator determines whether this value is
greater or less than the analog input. On the next rising clock
edge, the SAR reads the comparator feedback, sets bit 2 to its
final value, and brings bit 3 down to a logic "0". The digital
output is now XX01 1111 1111 1111. This successive approximation procedure continues until all the output bits are set.
The rising clock edge that sets the LSB (bit 16) also drops the
Status Output to a "0" signaling that the conversion is complete and turning off the internal clock. Outp:.!t data is now
valid and will remain so until another conversion is started.
SHORT CYCLING - For applications requiring less than 16
bits resolution, MN5284 Series AID's can be truncated or
short cycled at the desired number of bits with a proportionate decrease in conversion time. To truncate at n bits,
simply connect the n + 1 bit output tothe Short Cycle pin (pin
24). For example, to truncate at 14 bits, connect pin 15(Bit 15)
to pin 24; converting will stop and the Status output will go
low after bit 14 has been set. Bit 14 (the LSB for a 14-bit conversion) will be valid approximately 40nsec prior to the falling
edge of status.
EXTERNAL CLOCK - An external clock may be connected to
the Start Convert input. This external clock must consist of
negative-going pulses 100 to 200nsec wide and must be at a
lower frequency than the internal clock. The result is that
each falling edge of the external clock turns on the internal
clock for a single cycle, completing a conversion in 17 clock
cycles. The internal clock will be disabled whenever the Start
Convert input is held high. When using an external clock, a
Start Convert command is unnecessary. The converter will
begin to convert when the external clock is started and will
provide a continuous string of conversions with each conversion starting on the first falling edge of the external clock
after the Status output has gone low signaling the end of the
previous conversion. When continuously converting in this
manner, the Status output will go low for one external clock
period following the completion of each conversion.
SERIAL OUTPUT - Serial data is available only during the
conversion process. Format is NRZ with the MSB occuring
6-124
first. Serial data is coded the same as parallel output data,
and it is synchronous with the internal clock as shown in the
timing diagram. Each data bit becomes valid no longer than
70nsec after each rising clock edge and remains valid for the
full clock period. Therefore, falling clock edges can be used to
strobe serial data into output registers.
STATUS OUTPUT - The Status or End of Conversion (E.O.C.)
output will be set to a logic "1" by the falling edge of the Start
Convert signal; will remain high during conversion; and will
drop to a logic "0" when conversion is complete. There is a
minimum 40nsec delay between the point at which the LSB
becomes valid (is set to its final value) and the status output
falls to a "0". If an external latch is used to clock output data
away from the MN5284, this 40nsec mayor may not be long
enough to satisfy the set-up time requirement of the latch. If it
is not, additional delay will have to be generated. Simple gate
delays can be employed or the latch can be controlled by the
leading edge of the next start convert pulse. Recall that existing outpu·t data does not become invalid until the falling
edge of the start pulse. See diagram below.
Status
Output Data
---1
,
......
'--_
==><___
In_v_al_id_ _~~
Start Convert
If continuously converting with an external clock, the Status
output can be NORed with the internal clock output, as
shown below, to produce a positive strobe pulse approximately V. period wide, approximately V. period after the
Status output has gone low. The rising edge of this pulse can
be used to latch data after each conversion. Recall that the
falling edges of the external clock pulses generate rising
edges of the internal clock and that these two clocks appear
180 degrees out of phase. The delay from the rising edge of
the internal clock to the rising edge of Status is typically
35nsec. See Timing Diagram and the section labeled External
Clock.
External
Clock
0------1
22
MN5284
Series
20
19
L------L../
)0----.
Strobe
,
4h r i r i
r--u-u-lJIJ
u u ,u u
r-1
Ext Clock
Int Clock
Status
,
jJr------41----:....,Wl
,
Strobe
--n
!~
Iil'-----
INTERNAL REFERENCE - MN5284 Series devices contain
an internal, low-drift -9V reference that is laser trimmed to
an in itial accuracy of ± 0.05%. The reference is pinned out on
pin 27 and can supply up to 1mA beyond the current required
for bipolar operation (pin 27 connected to pin 26). If the external load is expected to vary during converter operation or if
the internal reference is to be used to drive external circuitry
at elevated temperatures, the reference output should be buffered externally.
DIGITAL OUTPUT CODING
ANALOG INPUT
Unipolar Ranges
0
,-1 LSB
Bipolar Ranges
+F.S.
+ F.S.-l LSB
- 'h F.S. + 1 LSB
-'12 F.S.
- '12 F.S. - 1 LSB
+ 1 LSB
0
-1 LSB
- F.S. + 1 LSB
-F.S.
- F.S. + 1 LSB
-F.S.
Part Number
MN5284
MN5285
MN5286
MN5287
Unipolar
Input Range
o to - 20V
o to -16.384V
Oto -10V
Oto -8.192V
Bipolar
Input Range
±10V
± B.192V
±5V
± 4.096V
OUTPUT
DIGITAL
MSB
LSB
0000 0000 0000 OOW
0000 0000 0000 OOOfll'
011111111111111~'
%%%~ %%~~ rt~rt~ ~~%~'
1000 0000 0000 OOO~'
111111111111111%'
1111111111111111
LSB VALUE
16·Bits
14·Bits
1.22mV
305.2~V
1mV
250~V
0.61mV
152.6~V
0.5mV
125~V
CODING NOTES:
1. For unipolar ranges, the coding is complementary straight binary.
2. For bipolar ranges, the coding is complementary offset binary.
3. For bipolar ranges, if MS"'e is used instead of MSB, the coding will
be complementary two's complement.
.. Analog voltages listed are the theoretical values for the transitions indicated.ldeally, with the MN5284 continuously converting, the output bits
indicated asJJ will change from a "1" to a "0" or vice versa as the input
voltage passes through the level indicated.
EXAMPLE: For the ± 10V range, the transition from output code 0000 0000
00000000 to output code 0000 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage of + 9.999695V (+ F.S. - 1 LSB). Subsequently,
any voltage greater than + 9.999695V will give a digital output of all "O's".
The transition from digital output 1000000000000000 to 0111 1111 1111
1111 (or vice versa) will ideally occur at an input of zero volts. The 1111
1111 1111 1111 to 1111 1111 1111 1110 transition will occur at
- 9.999695V. An input more negative than this level will give all ''1'5'',
and if one were performing optional bipolar·offset adjustment, it would be done at this point.
INPUT RANGE SELECTION - MN5284 Series AID's have an
internal, current-output, 16·bit DIA converter that is complementary coded and sources current at its output. Conse·
quently, MN5284 Series AID's are complementary coded
and have unipolar input ranges that are negative (0 to - 20V,
o to -16.384V, etc,). Each device in the Series has one
unipolar and one bipolar input voltage range. Unipolar
ranges are selected by leaving pin 26 (Bipolar offset) open;
bipolar ranges are selected by connecting pin 26 (Bipolar
offset) to pin 7 (Reference Output).
To avoid potential confusion, Micro Networks does not
specify bipolar offset error for MN5284 Series AID's. We
specify unipolar offset error and unipolar negative full scale
accuracy (Full Scale Absolute Accuracy Error) for unipolar
input ranges, and for bipolar input ranges, we specify
positive and negative full scale accuracy as well as a
bipolar zero error (around the zero-volt input point).
Making the bipolar·offset connection pulls a constant cur·
rent from the comparator summing junction and has the ef·
fect of offsetting the device transfer function "upward" an
amount equal to V2 of its full scale range (FSR). Recall that
the traditional definition of unipolar offset error for a SllCcessive approximation AID is the input·output accuracy error that occurs when the internal DIA is turned "off" or sourcing zero current (see the tutorial section of the Micro Net·
works catalog for details) and that for MN5284 type AID's
operating on their unipolar input range, this error occurs
around zero volts (the all "O's" digital output). If one were
performing optional unipolar offset adjustment, it would
be done at this point. Note that making the bipolar-offset
connection effectively moves this point "upward" to
+ '12 FSR (equivalent to the positive full scale pOint on the
bipolar input range). Now, at least according to traditional
definitions, the point at which bipolar offset error occurs is
the positive full scale point (still the all "O's" digital output),
OPTIONAL EXTERNAL OFFSET AND GAIN ADJUSTMENTS
- Initial offset and gain errors may be trimmed to zero using external potentiometers or voltage output DAC's as
shown in the following diagrams. Adjustments should be
made following warmup, and to avoid interaction, offset
should be adjusted before gain. The gain and offset adjust
pOints (pins 28 and 23) are purely resistive and are
specifically designed to be driven with applied voltages
ranging from + 5V to - 5V. Adjusting voltages can be
generated by tying potentiometers to the supplies or, in
microprocessor based applications, by using voltagf; .)utput
DAC's. If potentiometers are used, they should be r-.ultiturn
devices with TCR's of 100ppm/oC or less. Fixed resistors
can be ± 20% carbon composition or better. If these adjustments are not used, pin 23 should be left open and pin
28 should be decoupled to ground with a O.D1/LF ceramic
capacitor.
6-125
I
OFFSET ADJUSTMENT-Connect the offset potentiometer
to pin 23 as shown. For unipolar ranges, apply the input volt·
age at which the 0000 0000 0000 0000 to 0000 0000 0000 0001
transition is ideally supposed to occur (see Digital Output
Coding). While continuously converting, adjust the offset potentiometer until all the output bits are "0" and the LSB "flick·
ers" on and off. For bipolar rangEls, apply the input voltage at
which the 0111 11111111 1111 to 1000000000000000 transi·
tion is ideally supposed to occur(see Digital Output Coding).
While continuously converting, adjust the offset potentiom·
eter until all the output bits are "flickering". The offset adjust
sensitivity is approximately ±0.04%FSRlVolt, and the total
range of offset adjust, using the applied voltages of ± 5V, is
±0.2%FSR.
GAIN ADJUSTMENT - Connect the gain potentiometer to
pin 28 as shown, and apply the input voltage at which the
1111 1111 1111 1111 to 1111 1111 1111 1110 transition is
ideally supposed to occur. While continuously converting,
adjust the gain potentiometer until all the output bits are
"1" and the LSB "flickers" on and off. The gain·adjust sen·
sitivity is approximately ± 0.08%1V0It, and the total range
of gain adjust, using applied voltages of ± 5V, is ± 0.4%.
+15V
+15V
10klJ
10klJ
Pin 23
o---_~ 10kO
or
Pin 23
00----11
+ 5V
V -OUl DAC
1
Pin 28
o---_~ 10k"
Pin 28
10k"
1QkD
-lSV
-15V
GAIN ADJUST
OFFSET ADJUST
[lJ]
_
MICRO NETWORKS
324 Clark SI.. Worcester, MA 01606 (508) 852·5400
6-126
or
0_--"'1
±5V
V - Oul DAC
1
I.
MN5290
MN5291
!
HIGH-RESOLUTION
EXTENDED-TEMPERATURE
AID CONVERTERS
~ MICRO NETWORKS
FEATURES
• 16-Bit Resolution
• 14-Bit Performance
Guaranteed Over Temperature
• 40jlsec Max Conversion Time
• ±O.003% FSR Maximum
Linearity Error
• Serial and Parallel Outputs
• 6 User-Selectable Input Ranges
• 1080mW Max Power
Consumption
• Standard 32-Pin DIP
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
32 PIN DIP
DESCRIPTION
MN5290 and MN5291 are high-performance, dual-in-line
packaged, 40!-,sec, 16-bit AID converters specifically designed
for use in military/aerospace and industrial applications that
demand fully guaranteed high-resolution performance over
extended operating temperature ranges. These successive
approximation AID converters exploit the stability and tracking advantages of both SiCr and NiCr thin-film resistor technologies. Fully assembled devices are functionally laser
trimmed before and after a proprietary resistor stabilization
process that made MN5290 and MN5291 the industry's first
16-bit AID's to fully guarantee performance from -55°C to
+ 125°C. Recently, the Micro Networks MN5295/5296 (17!-'sec
conversion time) have joined MN5290/5291 as the only true
military 16-bit AID's.
MN5290 and MN5291 are packaged in industry-standard,
hermetically sealed, 32-pin, ceramic, dual-in-line packages.
Each is complete with internal clock and reference and has 6
user-selectable input ranges. Output data is straight binary
coded for unipolar input ranges and offset binary coded for
bipolar input ranges and is available in both serial and
parallel formats.
MN5290 and MN5291 are ideal for applications requiring true
14- and 13-bit performance over extended temperature ranges.
Applications will be found in military instrumentation, ATE and
servo systems and in industrial robotic position sensing
systems. MN5290H/B and MN5291H/B are available with Environmental Stress Screening while MN5290H/B CH and
MN5291H/B CH are screened in accordance with MIL-H-38534.
r
PIN 1
Model
Number
~O.600115.241-..l
Dimensions in Inches
(millimeters)
[1JJ
_
MN5290
MN5290E
MN5290H
MN5290H/B
MN5290H/B CH
MN5291
MN5291E
MN5291H
MN5291H/B
MN5291H/B CH
Temperature Range
for Guaranteed No MiSSing Codes
14
14
14
14
14
13
13
13
13
13
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
MICRO NETWORKS
O°C to +70°C
-25°C to +85°C
-55°C to +125°C
-55°C to + 125°C
-55°C to +125°C
O°C to +70°C
-25°C to +85°C
-55°C to +125°C
-55°C to + 125°C
-55°C to +125°C
January 1992
Copyright' 1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-127
MN5290 MN5291 HIGH·RESOLUTION AID CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN5290, MN5291
MN5290E, MN5291E
MN5290H, H/B; MN5291H, HIB
Storage Temperature Range
+ 15V Supply ( + Vee, Pin 27)
-15V Supply (- Vee, Pin 23)
+ 5V Supply (+ Vdd, Pin 29)
Analog Inputs (Pins 8 and 9)
Digital Inputs (Pins 30 and 32)
-55·Cto +125·C
PART NUMBER---------MN5290 H/B CH
O·C to + 70·C
-25·C to +85·C
-55·C to + 125·C
- 65·C to + 150·C
- 0.5 to + 18 Volts
+0.5 to -18 Volts
Oto +7 Volts
±22 Volts
oto + 5.5 Volts
Select MN5290 or MN5291 model. _ _ _ _ _.....
Standard Part is specified for O·C to +70·C
operation.
Add "E" suffix for specified -25°C to +85°C
operation.
------f
Add "H" suffix for specified -55°C to +125°C
operation.
_ _ _ _ _.....
Add "/B" to "H"devices for
Environmental Stress Screening. _ _ _ _ _ _ _.J
Add "CH" to "H/B" devices for 100%
screening according to MIL-H-38534. - - - - - - - - '
1
SPECIFICATIONS (TA = +2S oC, ± Vee = ± ISV, + Vdd = + SV unless otherwise Indicated )(Note 1)
ANALOG INPUT
MIN_
TYP_
MAX_
oto
Input Voltage Ranges: Unipolar
Bipolar
Input Impedance (Note 2): 0 to +5V, ±2.5V
Oto +10V, ±5V
±10V
UNITS
Volts
Volts
+5, 10,20
±2.5, 5,10
2.5
5
10
kll
kll
kll
DIGITAL INPUTS (Start, Short Cycle)
Logic Levels: Logic "1"
Logic "0"
+0.8
Volts
Volts
+40
-1.6
poA
rnA
+2.0
I Logic Currents: Logic "1" (VIH = + 2.4V)
Logic "0" (VIL = + 0.4Y)
TRANSFER CHARACTERISTICS (Note 3)
16
Resolution
Bits
Integral Linearity Error (Note 4): Initial (+25·C): MN5290
MN5291
Over Temperature (Note 5): MN5290
MN5291
±0.0015
±0.003
±0.003
±0.006
±0.003
±0.006
±0.006
±0.012
%FSR
%FSR
%FSR
%FSR
Differential Linearity Error (Note 4): MN5290
MN5291
±0.003
±0.006
±0.006
±0.012
%FSR
%FSR
+70
+85
+125
·C
·C
·C
Temperature Range for Guaranteed No Missing Codes
MN5290 (14 bits), MN5291 (13 bits)
MN5290E (14 bits), MN5291 E (13 bits)
MN5290H (14 bits), MN5291 H (13 bits)
0
-25
-55
Full Scale Absolute Accuracy Error (Note 6):
Unipolar: Initial (+25·C)
Over Temperature (Note 5)
Bipolar: Initial (+25·C)
Over Temperature (Note 5)
±0.075
±0.15
±0.1
±0.2
±0.15
±0.3
±0.2
±0.4
%FSR
%FSR
%FSR
%FSR
Unipolar Offset Error (Notes 7, 8): Initial (+25·C)
Over Temperature (Note 5)
Drift
±0.05
±0.1
±5
±0.1
±0.2
±15
%FSR
%FSR
ppm of FSR/·C
Bipolar Zero Error (Notes 7, 9): Initial (+25·C)
Over Temperature (Note 5)
Drift
±0.05
±0.1
±5
±0.12
±0.2
±15
%FSR
%FSR
ppm of FSR/·C
Gain Error (Notes 7, 10): Initial (+25·C)
Over Temperature (Note 5)
Drift
±0.05
±0.1
±5
±0.1
±0.2
±20
%
%
ppm/·C
+0.4
Volts
Volts
DIGITAL OUTPUTS (Serial, Parallel, Status, Clock)
Output Coding (Note 11): Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "I" OSOURCES320poA)
Logic "0" OSINKs3.2mA)
SB
OB
+2.4
REFERENCE OUTPUT
Internal Reference: Voltage
Accuracy
Tempco (Note 2)
External Current (Notes 2,12)
+10.000
±0.025
±5
1
Volts
%
ppm/·C
mA
36/40
posec
±0.1
DYNAMIC CHARACTERISTICS
Conversion Time (14 Bits/16 Bits) (Note 13)
6-128
34/38
MIN.
TYP.
MAX.
UNITS
±14.55
+4.75
±15
+5
±15.45
+5.25
Volts
Volts
±0.005
±0.005
±0.001
±0.02
±0.02
±0.01
%FSR/%Supply
%FSR/% Supply
% FSR/% Supply
Current Drains: + 15V Supply
-15V Supply
+5V Logic Supply
+30
-20
+12
+37
-29
+18
rnA
rnA
rnA
Power Consumption
810
1080
mW
POWER SUPPLIES
Power Supply Range: ± 15V Supplies
+5V Logic Supply
Power Supply Rejection (Note 14): + 15V Supply
-15V Supply
+ 5V Logic Supply
SPECIFICATION NOTES:
1. Listed specifications apply for all part numbers unless specifically in·
dicaled. Detailed liming specificalions appear in the Timing sections of
this dala sheet.
2. These parameters are listed for reference only and are not tested.
3. FSR = full scale range. and it is equal to the nominal peak·to·peak voltage of
the selected input voltage range. A unit connected for 0 to + 20V or ± 10V
operation has a 20V FSR. A unit connected for 0 to + 10V or ± 5V operation
has a 10V FSR etc. 1 LSB for 16 bits Is equivalent to 0.00153%FSR. 1 LSB for
14 bits is equivalent to 0.0061 % FSR.
4. ±0.003%FSR is equivalent to ± Y, LSB for 14 bits. ±0.006%FSR is
equivalent to ± Y, LSB for 13 bits.
5. Listed specifications apply over the O'C to + 70'C temperature range for
standard products, over the -25'C to +85'C range for "E" products and
over the -55'C to + 125'C range for"H" products.
6. Full scale absolute accuracy error includes offset, gain, linearity, noise, and
all other errors and is specified without adjustment. Full scale accuracy
specifications apply at positive full scale for unipolar input ranges and at
both positive and negative full scale for bipolar input ranges. Full scale ac-
curacy error is defined as the difference between the ideal and the actual in·
put voltage at which the digital output just changes from 111111111111
1110 to 1111 1111 1111 1111 for unipolar and bipolar input ranges. Addi·
tionally, it describes the accuracy of the 0000 0000 0000 0000 to 0000 0000
00000001 transition for bipolar input ranges. The former transition ideally
occurs at an input voltage I'hLSB's below the nominal positive full scale
voltage. The latter ideally occurs 'hLSB above the nominal negative full
scale voltage. See Digital Output Coding.
9. Bipolar zero error is defined as the difference between the ideal and the ac·
tual input voltage at which the digital output just changes from 01111111
1111 1111 to 1000 0000 0000 0000 when operating the MN5290/5291 on a
bipolar range. The ideal value at which this transition should occur is
- y, LSB. See Digital Output Coding.
10. Gain error is defined as the error in the slope of the converter transfer function.lt is expressed as a percentage and is equivalent to the deviation (divided by the ideal value) between the actual and the ideal value for the full input
voltage span from the input voltage at which the output changes from 1111
111111111111 to 1111111111111110to the input voltage at which the out·
put changes from 0000 0000 0000 0001 to 0000 0000 0000 0000.
11. SB = straight binary. OB = offset binary. See table of transition voltages in
section labeled Digital Output Coding.
12. In addition to supplying lmA of current for bipolar offsetting purposes(pin 7
connected to pin 24), the internal reference is capable of driving up to lmA
into an external load. If the internal reference is used to drive an external
load, the load should not change during a conversion.
13. Conversion is initiated on the falling edge of the start convert command,
and conversion lime is defined as the width of the status (end of conversion)
pulse. Conversion time may be shortened, with lower resolution, by short
cycling. Connect pin 5 (Bit 15) to pin 32 (Short Cycle) for 14·bit conversions.
See Timing Diagram.
14. Power supply rejection is defined as the change in the analog input voltage
at which the 111111111111111Oto 1111111111111111 or 0000 0000 0000
0000 to 0000 0000 0000 0001 output transitions occur versus a change in
power·supply voltage.
7. Initial unipolar offset (bipolar zero) and gain errors are adjustable to zero
with the use of external potentiometers.
B. Unipolar offset error is defined as the difference between the ideal and the
actual input voltage at which the digital output just changes from 0000 0000
0000 0000 to 0000 0000 0000 0001 when operating the MN5290/5291 on a
unipolar range. The ideal value at which this transition should occur is
+ 'hLSB. See Digital Output Coding.
Specifications subject to change without notice as Micro Networks
reserves the right to make improvements and changes in its products.
PIN DESIGNATIONS
•
32
16
17
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Status (E.O.C.)
Clock Output
Bit 13
Bit 14
Bit 15
Bit 16 (LSB)
Bipolar Offset
10V Input Range
20V Input Range
Serial Output
Bit 12
Bit 11
Bit 10
Bit9
Bit8
Bit 7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Short Cycle
Ground
Start Convert
+ 5V Supply ( + Vdd)
Summing Junction
+ 15V Supply (+ Vee!
Ground
Gain Adjust
Reference Output (+10V)
-15V Supply (- Vec)
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit5
Bit 6
6·129
BLOCK DIAGRAM
I CLOCK I
Start Convert (30)
I
I
+ 15V Supply (27)
-
J
Clock Oulput (2)
(1) SIal us (E.O.C.)
(32)ShOr! Cycle
(10) Sari alOutput
SUCCESSIVE APPROXIMATION REGISTER
(22) MS B
(21) BII 2
(20) Bit 3
(19)BII 4
(18) BII 5
(17) Bit 6
(16) Bit 7
(15) Bit 8
(14) Bit 9
(13) Bit 10
(12) Bit 11
(11) Bit 12
(3) Bit 13
(4) Bit 14
(5) Bit 15
(6) Bit 16
,.
,.
"
"
0
- 15V Supply (23) 0
+ 5V Supply (29) 0
Ground (31) 0
Ground (26) 0
;.
B-
Ref. Oulpul (24)
L-
Gain Adjusl (25)
OlA CONVERTER
Summing Junction (28)
COMPARATOR
10V Range (8)
20V Range (9)
5kll
I
5kll
1
1[>-
Bipolar Offsel (7)
10kll
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-See Block Diagram. The
successive approximation register (SAR) is a set of flip flops
(and control logic) whose outputs act as both the direct
(parallel) data outputs of the analog-to-digital converter (AID)
and the digital drive for the AID's internal digital-to-analog
converter (D/A). The falling edge of a start convert pulse applied to pin 30 turns on the AID's internal clock and resets the
SAR. In this state, the output of the MSB flip flop is set to
logic "0"; the outputs of the other bit flip flops are set to a
logic "1"; and the Status (pin 1) is set to logic "1" (see Timing
Diagram). The Start Convert must now remain low for the conversion to continue.
The D/A internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The comparator output ("1" or "0") informs the SAR whether the present digital output (0111 1111 1111 1111 in the reset state) is
"greater than" or "less than" the analog input. Depending
upon which is greater, on the first rising clock edge after Start
Convert has gone low, the SAR will set the MSB to its final
state("1" or "0") and bring bit 2down to a "0". The digital output is now X011111111111111. The DIA converts this to an
analog value, and the comparator determines whether this
value is greater or less than the analog input. On the next rising clock edge, the SAR reads the comparator feedback, sets
bit 2 to its final value, and brings bit 3 down to a logic "0". The
digital output is now XX01111111111111_ This successive
approximation procedure continues until all the output bits
are set. The riSing clock edge that sets the LSB (bit 16) also
6-130
drops the Status Output to a "0" signaling that the conversion is complete and turning off the internal clock. Output
data is now valid and will remain so until another conversion
is started.
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracies from
the MN5290 and MN5291. The units' two ground pins (pins26
and 31) are not connected to each other internally. They must
be tied together as close to the unit as possible and both connected to system analog ground, preferably through a large
analog ground plane beneath the package_If these commons
must be run separately, a nonpolarized 0.01,..F ceramic bypass capaCitor should be connected between pins 26 and 31
as close to the unit as possible and wide conductor runs
employed.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick-up. Pins 7 (Bipolar Offset), 8
and 9 (Analog Inputs), 28 (Summing Junction) and 25 (Gain
Adjust) are particularly noise susceptible. Care should be
taken to avoid long runs or runs close to digital lines when
using these inputs. Input signal lines should be as short as
possible. In bipolar operation, where pin 7 is connected to pin
24, a short jumper should be used. If bipolar offsetting is not
used, pin 7 should be grounded to pin 26. For external offset
adjustment, the 1.8 megohm resistor should be located as
close to pin 28 as possible. A 0.01,..F ceramic capacitor should be
connected between pin 25 and analog ground as close to the
package as possible.
TIMING DIAGRAM
START CONVERT
II
INTERNAL CLOCK
71117l!
ZZlLlLl
BIT 3 ZZlLlL1
BIT 4
ZllllA
BIT 5 ZZlLlL1
BIT 6
ZZlLlLl
BIT 7
ZZLZlLl
BIT 8
ZZlLlL1
ZZLZlLl
ZZlLlL1
ZZLZlLl
BIT 12 ZZlLlL1
MSB
BIT 2
~r.,----------------------------------
I
BIT 9
BIT 10
81T 11
SIT 13
BIT 14
BIT 1S
BIT 16
STATUS
~------------
LJl
ZZZZlL1
ZlZZZL1
Z1llllJ
ZZLllL1
---.J
EXTERNA:'" CLOCK
SERIAL OUTPUT
SPECIFICATIONS (TA
12?z~~7JL~
15
= + 2S"C, Supply Voltages:!: lSV and + SV unless otherwise specified)
DYNAMIC CHARACTERISTICS
TYP.
MAX.
UNITS
Conversion Time (14 Bitsf16 Bits)
MIN.
34/38
36/40
"sec
Internal Clock Frequency (Note 8)
420
Start Convert Positive Pulse Width (Note 8)
Delay Falling Edge of Start to (Note 8): Status
kHz
50
=
"1"
Clock Output
=
"1"
nsec
50
20
80
50
nsec
nsec
200
nsec
Delay Rising Clock Edge to Output Data
Valid (Parallel, Serial, Status) (Note 8)
20
120
Delay LSB Valid to Falling Edge of Status (Note 8)
20
60
nsec
TIMING DIAGRAM NOTES
1. Operation shown is for the digital word 0101 011000101011.
2. The Start Convert command must be at least 50nsec wide and must remain
low during conversion.
3. The internal clock is enabled and the conversion cycle commences on the
falling edge of the Start Convert Signal.
4. Data will be valid 60nsec before the Status (E.O.C.) output goes low and will
6. When the converter is initially "powered up", it may come on at any point in
the conversion cycle.
7. Conversion time is defined as the width of the Status (End of Conversion)
pulse. Conversion time may be shortened, with lower resolution, by short
cycling. Connect pin 5 (Bit 15) to pin 32 (Short Cycle) for 14 bit conversions.
8. These parameters are listed for reference only and are not tested.
remain valid until another conversion is initiated.
5. When using an external clock, the converter will continuously convert. Each
conversion will be initiated by the falling edge of the first external clock
pulse following E.O.C.'s gOing low at the end of the previous conversion.
See External Clock.
6-131
Power supplies should be decoupled with tantalum and
ceramic capacitors located close to the MN5290 and
MN5291. For optimum performance and noise rejection, 1/LF
tantalum capacitors paralleled with 0.01/LF ceramic capacitors should be used as shown in the diagram below.
If short cycling is not used, the Short Cycle pin (pin 32) must
be connected to +5V (pin 29).
POWER SUPPLY DECOUPLING
Pin 29 0
1 pF
Pin 31 0
I
I
Pin 27 0
I
+5V
10.01 pF
.
Pin 26
Ground
1 pF
0
1 pF
Pin 23
0
1
I
-
-
I I
+ 15V
STATUS OUTPUT-The Status or End of Conversion (E.O.C.)
output will be set to a logic "1" by the falling edge of the Start
Convert signal; will remain high during conversion; and will
drop to a logic "0" when conversion is complete. The falling
edge of Status is internally delayed a minimum of 20nsec to
ensure that all parallel output data, including the LSB, is valid
by the time the edge occurs. If parallel data is to be latched
into external registers, this delay should be long enough to
accomodate the set-up time requirements of the latch such
that Status can be used to strobe the latch. If the delay is not
long enough, the Status can be delayed with gate delays or
the latch can be strobed with the leading edge of the next
start convert pulse: See diagram below.
0.01 pF
Ground
Start Convert
T T
IL.___________~
0.01 pF
-
-
-
15V
Output Data-=:=><~
START CONVERT - The Start Convert signal must be a
positive pulse with a minimum pulse width of 50nsec. The
falling edge of the Start Convert signal resets the converter
and turns on the internal clock. Status going low at the end
of a conversion turns off the internal clock. If the Start Convert input is brought high after a conversion has been
initiated, the internal clock will be disabled halting the conversion. If the Start Convert input is then brought low, the
original conversion will continue with a possible error in the
output bit that was about to be set when the internal clock
was stopped.
SHORT CYCLING-For applications requiring fewer than 16
bits of resolution, the MN5290 and MN5291 can be truncated
or short cycled at the desired number of bits with a proportionate decrease in conversion time. To truncate at n bits,
Simply connect the n + 1 bit output to the Short Cycle pin (pin
32). For example, to truncate at 14 bits, connect pin 5 (Bit 15)
to pin 32; converting will stop and Status will go low after bit
14 has been set. For any length conversion, the falling edge of
Status is internally delayed a minimum of 20nsec to ensure
that all parallel output data, including the LSB, is valid by the
time the edge occurs.
EXTERNAL CLOCK-An external clock may be connected to
the Start Convert input. This external clock must consist of
negative-going pulses 100 to 200nsec wide and must be at a
lower frequency than the internal clock. The result is that
each falling edge of the external clock turns on the internal
clock for a Single cycle, completing a conversion in 17 clock
cycles. The internal clock will be disabled whenever Start
Convert is held high. When using an external clock, a Start
Convert command is unnecessary. The converter will begin
to convert when the external clock is started and will provide
a continuous string of conversions with each conversion
starting on the first falling edge of the external clock after
Status has gone low signaling the end of the previous conversion. When continuously converting in this manner, Status
will go low for one external clock period following the completion of each conversion.
SERIAL OUTPUT-Serial data is available only during the
conversion process. Format is NRZ with the MSB occurring
first. Serial data is coded the same as parallel output data,
and it is synchronous with the internal clock as shown in the
Timing Diagram. Each data bit becomes valid typically
120nsec after each riSing clock edge and remains valid for
the full clock period. Therefore, falling clock edges can be
used to strobe serial data into output registers.
6-132
'---_S__v_a_lid_ _>C
status _ _1
___
'n_va_li_d_ _ _X~
If continuously converting with an external clock, Status can
be NORed with the internal clock, as shown below, to produce a positive strobe pulse approximately Yo period wide,
approximately Yo period after Status has gone low. The rising
edge of this pulse can be used to latch data after each conversion. Recall that the falling edges of the external clock
pulses generate rising edges of the internal clock and that
these two clocks appear 180 degrees out of phase. The delay
from the rising edge of the internal clock to the riSing edge of
Status is typically 120nsec. See Timing Diagram and the section labeled External Clock.
External
0 - - - - - 1 30
MN5290
MN5291
Clock
2
'-----------L--'
Int Clock
)1>---. Strobe
,
Status
-iJr--------illl---~~UJ
s tra be
:J
,
:
II
n1
. ,'-.____
INTERNAL REFERENCE- The MN5290 and MN5291 contain
an internal, low-drift 10V reference that is laser trimmed to an
initial accuracy of ± 0.1 %. The reference is pinned out on pin
24 and can supply up to 1mA beyond the current required for
bipolar operation (pin 24 connected to pin 7). If the external
load is expected to vary during converter operation or if the
internal reference is to be used to drive external circuitry at
elevated temperatures, the reference output should be buffered externally.
OPTIONAL EXTERNAL ZERO AND GAIN ADJUSTMENTS Initial zero and gain errors may be trimmed to zero using external potentiometers as shown in the following diagrams.
Adjustments should be made following warmup, and to avoid
interaction, zero should be adjusted before gain. Fixed
resistors can be ±20% carbon composition or better. Multiturn potentiometers with TCR's of 100ppm/oC or less are recommended to minimize drift with temperature. If these adjustments are not used, pin 28 should be connected as
described in the Range Selection section.
ZERO ADJUSTMENT-Connect the zero adjust potentiometer as shown. For unipolar ranges, apply the input voltage at
which the 0000 0000 0000 0000 to 0000 0000 0000 0001 transition is ideally supposed to occur. While continuously converting, adjust the zero potentiometer until all bits are "0" and the
LSB "flickers" on and off. For bipolar ranges, apply the input
voltage at which the 0111 1111 1111 1111 to 100000000000
0000 transition is ideally supposed to occur. While continuously converting, adjust the zero potentiometer until all bits
"flicker" on and off.
DIGITAL OUTPUT CODING
• FS
+F.S .
+ F.S. - )/2 LSB
+ ':2 LSB
"2
MSB
1111111111111111
11111111111111'~·
1000 0000 0000 OOO~'
,l!j!'i$'j!'j!'~ _
_J/ 2 LSB
011111111111111"·
+ ' 2 lSB
- F.s. + '12 LSB
0
-F.S.
0000 0000 0000 000/1'
0000 0000 0000 0000
-)/1
LSB
lOkll
to
100kll
or
~~~IBOk!l i;~k!l
lBOkll
l00kll
22k!l
_
-15V
-15V
GAIN ADJUSTMENT-Connect the gain potentiometer as
shown, and apply the input voltage at which the 1111 1111
1111 1110 to 1111 1111 1111 1111 transition is ideally supposed to occur. While continuously converting, adjust the
gain potentiometer until all the output bits are "1" and the
LSB "flickers" on and off.
+ 15V
Pin
lOMIl
+15V
Il0kll
25~ to
Pin
26
J
D--<~f\,...-_JV\r-'!K
or
10kll
to
l00kll
0~~1 _15:00kll
ANALOG INPUT VOLTAGE RANGE
LSB
- '/2 LSB
'zF S.
f
I.BMIl
DIGITAL OUTPUT
BIPOLAR RANGES
+ F.S - J/ 1 LSB
+ ' 2 F S. + ! 2 LSB
+ ' 2F.S. LS8
-4-
.
~'~ o--w--">
+15V
INPUT RANGE SELECTION
ANALOG INPUT
UNIPOLAR RANGES
+ 15V
0'n~"
PIN CONNECTIONS
±5V
±10V
Oto +5V
Oto +10V
Oto +20V
±2.5V
Connect Pin 7 to Pin
26
26
26
24
24
24
Connect Pin 9 to Pin
28
Open
Input
28
Open
Inpul
Connect Pin 28 to Pin
9
Open
Open
9
Open
Open
Connect Input to Pin
8
8
9
8
8
9
Input Impedance (KIl)
2.5
5
10
2.5
5
10
CODING NOTES:
1.
2.
3.
4.
For 10 Volts FSR. 1LSB for 16 Bits = 152.6.V. 1LSB for 14 Bits = 61O.4.V.
For 20 Volts FSR, lLSB for 16 Bits = 305.2.V. lLSB for 14 Bits = 1.22mV.
For unipolar ranges, the coding is straight binary.
For bipolar ranges, the coding is offset binary.
* Analog voltages listed are the theoretical values for the transitions indicated.ldeally, with the MN5290/MN5291 continuously converting, the out·
put bits indicated as~ will change from a "1" to a "0" or vice versa as the input voltage passes through the level indicated.
USING TRACK·HOLD AMPLIFIERS WITH
MN5290 AND MN5291 CONVERTERS
Successive approximation type AID converters cannot accurately digitize analog signals whose slew rates produce
amplitude changes (Ll.V) greater than ± VzLSB during the
AID conversion time (Ll.t). If such signals are to be accurately
digitized, a sample/hold (S/H) or track/hold (T/H) amplifier
will be required in front of the AID to hold input signals constant during the conversion period, For an MN5290
operating on its ± 10V input range and short cycled for
14-bit conversions, VzLSB (Ll.V) is equivalent to 0.61mV, and
the maximum conversion time (Ll.t) is 36l'sec. Therefore, the
analog-signal slew-rate limit beyond which an MN5290 requires a T/H is equal to Ll.V/Ll.t=0.61mV/36I'sec=16.94
V/sec. If one prefers to think in terms of sinusoidal bandwidths, one concludes that a 36l'sec, 14-bit AID cannot accurately digitize a sinewave whose instantaneous slew rate
exceeds 16.94V/sec. For a given sine wave v(t)=
Asinwt, the maximum slew rate will equal Ll.V/Ll.t
(max) = Aw = 2.. Af. If A = 10V and Ll.V/Ll.t (max) = 16.94V1sec,
then f(max) = 0.27Hz. In summary, the MN5290 or any similar
successive approximation type AID operated without a T/H
(S/H) cannot be expected to accurately and linearly digitize
EXAMPLE: For the ± 10V range, the transition from output code 1111
111111111111 to output code 1111111111111110(orviceversa)will ideally
occur at an input of + 9.999542V (+ F.S. - 'I,LSB). Subsequently, any
voltage greater than + 9.999542V will give a digital output of all
"1 's." The transition from digital output 0111 1111 1111 1111 to 1000 0000
00000000 (or vice versa) will ideally occur at an input of - 0.000153volts. The
0000 0000 0000 0000 to 0000 0000 0000 0001 transition will occur at
- 9.999847V. An input more negative than this level will give all "a's."
a ± 10V sine wave with a frequency above 0.27Hz. The AID
will exhibit accuracy and linearity errors around the max
slew rate pOint (zero crossing) of the sine wave. A properly
selected T/H (S/H) in front of a given AID converter will increase the permitted slew rate (bandWidth) by a factor equal
to the ratio of the AID conversion time divided by the T/H
aperture jitter. The T/H may reduce system throughput,
however, since T/H acquisition and transient settling times
will have to be added to AID conversion time to determine
how often digital output data can be updated.
There are four major considerations when choosing a T/H to
operate with the MN5290 or MN5291. The T/H must have an
input/output linearity commensurate with that of the
chosen AID. The T1H must be capable of and clearly specify
acquisition and track-to-hold transient settling times to
± 0.003% FSR (± Vz LSB for MN5290 short-cycled to 14 bits)
or to ± 0.006%FSR (± Vz LSB for MN5291 short-cycled to 13
bits). The T/H's output droop in the hold mode must be low
enough so the held signal does not change more than
± VzLSB during the AID conversion time. For an MN5290
operating on its ± 10V range and short cycled to 14 bits, this
droop limit is 0.61mV/361'sec = 16.94I'VlJ.lSec. For an MN5291
operating on its ± 10V range and short cycled to 13 bits, this
droop limit is 1.22mV/341'sec = 361'V/J.lSec. Lastly, the T1H
6-133
feedthrough attenuation must be such that no more than
± 'hLSB of changing input signal feeds through during the
conversion period. For use with a 14·bit MN5290, the TlH
should have at least 84dB of feedthrough attenuation at ap·
propriate frequencies. For use with a 13·bit MN5291, the T/H
should have at least 78dB of feedthrough attenuation.
When actually implementing the T/H·A/D connection, there
are two important timing considerations. When commanded
to the signal acquisition mode (track mode) the T/H must be
given enough time to acquire a new signal to within
± V. LSB of final value, and when commanded back to the
hold mode, the T/H must be given enough time to permit its
output transient to settle to within ± V.LSB of final value
before initiating a conversion. This second consideration is
often overlooked. When a T/H or S/H is commanded from
the signal acquisition mode to the hold mode, a transient
(glitch) invariably occurs, and the transient should be allow·
ed to decay sufficiently before an AID conversion is in·
itiated. The relevant TlH specification may be called Track
to Hold Transient Settling Time, Transient Settling Time or
simply Settling Time. It is important to recall that for most
successive approximation type AID converters, the MSB is
not set to its final value until 1 full clock period after a con·
version has been initiated, and the transient must have
decayed before that time. In the MN5290 for example (see
Timing Diagram), the MSB is not set to its final value until 1
full clock period (2.4,.,sec typical) after the falling edge of
the start convert command. If the transient of the selected
T/H decays to within ± V. LSB of the appropriate resolution
in less than 2.4,.,sec, the falling edge of the convert com·
mand can be used to drive the T/H into the hold mode.
Figure 1 (below) shows just such a configuration. When the start
command is high, the T/H is in the tracking (signal acquisition)
mode. The falling edge of the start command puts the T/H into the
hold mode and simultaneously initiates the conversion operation.
The MSB is set to its final value 1 clock period later, and the switch·
ing transient of the selected T/H must decay sufficiently during that
time. The duration of the start convert command must be long
enough to accommodate the acquisition time of the chosen T/H.
hold mode. As before, the T/H transient will have to decay
before the AID makes its MSB deCision. The falling edge of
status at the end of a conversion drives the T/H back into
the track mode. The time between the falling edge of status
and the falling edge of the next start convert pulse (the ris·
ing edge of the next status pulse) must be long enough to
accomodate the acquisition time of the selected TIH.
~MSB
I
Analog
Input
MN5290
MN5291
LSB
",";Track
"0"; Hold
startCommand~
Status Output
T/H Mode
T/H Output
Acquire
I
I
Hold
Acquire
I
~
MSB Set
to Final
Value
Figure 2. If controlling the T/H with the converter status output, the time be·
tween conversions must be long enough to accomodate the acquisition time
of the chosen T/H.
If the MN5290 or MN5291 is to be operated in a continuously
converting mode, there will not be enough time between
conversions for most T/H's to acquire a new signal to the ap·
propriate accuracy. In this situation, the falling edge of
status at the end of each conversion can be used to fire a
one·shot whose output can be both the start convert and
T/H command signals. The duration of the one·shot must be
long enough to accomodate the acquisition time of the
chosen T/H.
MSB
+ '5V - t 5V + 5V
Analog
Input
, LSB
","; Track
"0"; Hold
MSB
Analog
Input
Start
Convert
LSB
Start Command ---1~L
TIH Mode
TIH Output
I
Acquire
I
_______
Hold
~
to Final
Value
Figure 1. If controlling the T/H with the converter start pulse, the pulse must
be wide enough to accomodate the acquisition time of the chosen TfH.
Another popular technique is to control the T/H's operation
with the AID converter's status line. This is demonstrated in
Figure 2 below. For the MN5290 and MN5291, the status out·
put is high during a conversion and drops low when a con·
version is complete. The riSing edge of status at the begin·
ning of a conversion is used to command the T/H into the
6·134
"1" = Track
"0"; Hold
Status
One·Shot
T/H Mode
T/H Output
HOld
I
Acquire
I
Hold
~
to Final
Value
Figure 3. If continuously converting, a one-shot may be required to generate
the start and T/H command pulses.
l1lJ
_
MN5295
MN5296
17p,sec, 16-Bit
MICRD NETWDRKS
EXTENDED TEMPERATURE
AID CONVERTERS
DESCRIPTION
FEATURES
High resolution, high speed, small package and the ability to
operate over extended temperatures (including -55°C to
+125°C) are brought together in the MN5295 and MN5296.
These TIL-compatible, 16-bit, DIP-packaged AID converters
guarantee 17p.sec maximum conversion time (for 16 bits); 1.2
Watts maximum power consumption; and ±O.003%FSR
maximum integral linearity error. Over temperature, MN5295
guarantees 14-bit "no missing codes", and MN5296 guarantees the same for 13-bits. Each device is packaged in a
standard, 32-pin, double-wide, hermetic, ceramic DIPnot the triple-wide DIP's of most other 16-bit AID's.
• 16-Bit Resolution
• 17{--------7
-15V Supply (23)
+ 5V Supply (29)
Ground (31)
Ground (26)
,."
0
0
0
""
0
a-
Ref. Output (24)
"---
Gain Adjust (25)
D/A CONVERTER
Summing Junction (28)
COMPARATOR
10V Range (8)
20V Range (9)
Bipolar Offset (7)
5kll
1
5kll
10kll
I
I
>-
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-See Block Diagram. The
successive approximation register (SAR) is a set of flip flops
(and control logic) whose outputs act as both the direct
(parallel) data outputs of the analog-to-digital converter (AID)
and the digital drive for the AID's internal digital-to-analog
converter (D/A). The falling edge of a start convert pulse applied to pin 30 turns on the AID's internal clock and resets the
SAR. In this state, the output of the MSB flip flop is set to
logic "0"; the outputs of the other bit flip flops are set to a
logic "1"; and the Status (pin 1) is set to logic "1" (see Timing
Diagram). The Start Convert must now remain low forthe conversion to continue.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The comparator output ("1" or "0") informs the SAR whether the present digital output (0111 1111 1111 1111 in the reset state) is
"greater than" or "less than" the analog input. Depending
upon which is greater, on the first rising clock edge after Start
Convert has gone low, the SAR will set the MSB to its final
state ("1" or "0") and bring bit 2 down to a "0". The digital output Is now X011 1111 1111 1111. The DIA converts this to an
analog value, and the comparator determines whether this
value is greater or less than the analog input. On the next rising clock edge, the SAR reads the comparator feedback, sets
bit 2 to its final value, and brings bit 3 down to a logic "0". The
digital output is now XX01 1111 1111 1111. This successive
approximation procedure continues until all the output bits
are set. The rising clock edge that sets the LSB (bit 16) also
6-138
drops the Status Output to a "0" signaling that the conversion is complete and turning off the internal clock. Output
data is now valid and will remain so until another conversion
is started.
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracies from
the MN5295 and MN5296. The units' two ground pins (pins 26
and 31) are not connected to each other internally. They must
be tied together as close to the unit as possible and both connected to system analog ground, preferably through a large
analog ground plane beneath the package. If these commons
must be run separately, a non polarized 0.01!'F ceramic
bypass capacitor should be connected between pins 26 and·
31 as close to the unit as possible and wide conductor runs
employed.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick-up. Pins 7 (Bipolar Offset), 8
and 9 (Analog Inputs), 28 (Summing Junction) and 25 (Gain
Adjust) are particularly noise susceptible. Care should be
taken to avoid long runs or runs close to digital lines when
using these inputs. Input signal lines should be as short as
possible. In bipolar operation, where pin 7 is connected to pin
24, a short jumper should be used. If bipolar offsetting is not
used, pin 7 should be grounded to pin 26. For external offset
adjustment, the 1.8 megohm resistor should be located as
close to pin 28 as possible. A 0.Q1 ~ ceramic capacitor should be
connected between pin 25 and analog ground as close to the
package as possible.
Power supplies should be decoupled with tantalum and
ceramic capacitors located close to the MN5295 and
MN5296. For optimum performance and noise rejection, 11'F
tantalum capacitors paralleled with 0.011'F ceramic
capacitors should be used as shown in the diagrams below.
If short cycling is not used, the Short Cycle pin (pin 32) must
be connected to +5V (pin 29).
POWER SUPPLY DECOUPLING
Pin 27
Pin 29
C
1 "F
Pin 31
I I
T T
+ 5V
0.01 "F
o~...J--....-J-L......-Ground
1 "F
Pin 26
.
I I
O~--'rr---lr-- + 15V
0
1 "F
Pm230
001 "F
-
~
r
T
-
STATUS OUTPUT-The Status or End of Conversion (E.O.C.)
output will be set to a logic "1" by the falling edge of the Start
Convert signal; will remain high during conversion; and will
drop to a logic "0" when conversion is complete. The falling
edge of Status is internally delayed a minimum of 20nsec to
ensure that all parallel output data, including the LSB, is valid
by the time the edge occurs. If parallel data is to be latched
into external registers, this delay should be long enough to
accomodate the set-up time requirements of the latch such
that Status can be used to strobe the latch. If the delay is not
long enough, the Status can be delayed with gate delays or
the latch can be strobed with the leading edge of the next
start convert pulse. See diagram below.
Ground
Start Convert
I L___________....-JI"L-
0.01"F
-
-15V
status _ _1
-=x__
......::ln;c.v.:::al.:::id_ _~X
Output Data
START CONVERT - The Start Convert signal must be a
positive pulse with a minimum pulse width of 50nsec. The
falling edge of the Start Convert signal resets the converter
and turns on the internal clock. Status going low at the end
of a conversion turns off the internal clock. If the Start Convert input is brought high after a conversion has been
initiated, the internal clock will be disabled halting the con·
version. If the Start Convert input is then brought low, the
original conversion will continue with a possible error in the
output bit that was about to be set when the internal clock
was stopped.
SHORT CYCLING-For applications requiring fewer than 16
bits of resolution, the MN5295 and MN5296 can be trurlcated
or short cycled at the desired number of bits with a proportionate decrease in conversion time. To truncate at n bits,
simply connect the n + 1 bit output to the Short Cycle pin (pin
32). For example, to truncate at 14 bits, connect pin 5 (Bit 15)
to pin 32; converting will stop and Status will go low after bit
14 has been set. For any length conversion, the falling edge of
Status is internally delayed a minimum of 20nsec to ensure
that all parallel output data, including the LSB, is valid by the
time the edge occurs.
EXTERNAL CLOCK-An external clock may be connected to
the Start Convert input. This external clock must consist of
negative-going pulses 100 to 200nsec wide and must be at a
lower frequency than the internal clock. The result is that
each falling edge of the external clock turns on the internal
clock for a single cycle, completing a conversion in 17 clock
cycles. The internal clock will be disabled whenever Start
Convert is held high. When using an external clock, a Start
Convert command is unnecessary. The converter will begin
to convert when the external clock is started and will provide
a continuous string of conversions with each conversion
starting on the first falling edge of the external clock after
Status has gone low signaling the end of the previous conversion. When continuously converting in this manner, Status
will go low for one external clock period following the completion of each conversion.
SERIAL OUTPUT-Serial data is available only during the
conversion process. Format is NRZ with the MSB occurring
first. Serial data is coded the same as parallel output data,
and it is synchronous with the internal clock as shown in the
Timing Diagram. Each data bit becomes valid typically
120nsec after each rising clock edge and remains valid for
the full clock period. Therefore, falling clock edges can be
used to strobe serial data into output registers.
, - I_ _
Valid
S>C
If continuously converting with an external clock, Status can
be NORed with the internal clock, as shown below, to produce a positive strobe pulse approximately V2 period wide,
approximately 'I> period after Status has gone low. The rising
edge of this pulse can be used to latch data after each conversion. Recall that the falling edges of the external clock
pulses generate rising edges of the internal clock and that
these two clocks appear 180 degrees out of phase. The delay
from the rising edge of the internal clock to the rising edge of
Status is typically 120nsec. See Timing Diagram and the section labeled External Clock.
External
Clock
0------;
30
MN5295
MN5296
~)o----.
Ext Clock
Strobe
--U---U-U~~
Int Clock
,
Status
---'-"";-'GJ
jJr-------llri
,
Strobe
~
Ii
fl!L.----
INTERNAL REFERENCE-The MN5295 and MN5296 contain
an internal, low-drift 10V reference that is laser trimmed to an
initial accuracy of ±0.1 %. The reference is pinned out on pin
24 and can supply up to 1mA beyond the current required for
bipolar operation (pin 24 connected to pin 7). If the external
load is expected to vary eluring converter operation or if the
internal reference is to be used to drive external circuitry at
elevated temperatures, the reference output should be buffered externally.
6-139
I
TIMING DIAGRAM
START CONVERT
INTERNAL CLOCK
MSB
II/T/JI
BIT 2
I/IIJII
:l
1/111/1
BIT 4
I/IIJA
BIT
U'
U'
lLll.l1J
lLll.l1J
BIT 7 ZLl.ll1J
BIT 8
ZLl.ll1J
BIT 9
ZLl.ll1J
BIT 10 ZLl.ll1J
BrT 11 ZLl.ll1J
BIT 12 ZLl.ll1J
BIT 13 ZlZZZLl
BIT 5
BIT 6
SIT 14
ZLlZZL1
BrT 15
Zlll.llJ
BIT 16
ZZLZZL1
STATUS
~
EXTERNAL CLOCK
SERIAL OUTPUT
SPECIFICATIONS (TA
~
L
~
ll.~~:72?Zl~---1
15
16
= + 25°C, Supply Voltages ± 1SV and + SV unless otherwise specified)
TYP.
MAX.
UNITS
Conversion Time (14 Bits/16 Bits)
14/16
15/17
"sec
Internal Clock Frequency (Note 8)
1
DYNAMIC CHARACTERISTICS
MIN.
Start Convert Positive Pulse Width (Note 8)
Delay Falling Edge of Start to (Note 8): Status = "1"
Clock Output
MHz
nsec
50
= "1"
50
20
80
50
nsec
nsec
200
nsec
Delay Rising Clock Edge to Output Data
Valid (Parallel, Serial, Status) (Note 8)
20
120
Delay LSB Valid to Falling Edge of Status (Note 8)
20
60
nsec
TIMING DIAGRAM NOTES
1. Operation shown is for the digital word 0101011000101011.
2. The Start Convert command must be at least SOnsee wide and must remain
low during conversion.
3. The internal clock is enabled and the conversion cycle commences on the
falling edge of the Start Convert signal.
4. Data will be valid 60nsec before the Status (E.O.C.) output goes low and will
remain valid until another conversion is initiated.
5. When using an external clock, the converter will continuously convert. Each
conversion will be initiated by the falling edge of the first external clock
pulse following E.O.C.'s going low at the end of the previous conversion.
See External Clock.
6-140
6. When the converter is initially "powered up", it may come on at any point in
the conversion cycle.
7. Conversion time is defined as the width of the Status (End of Conversion)
pulse. Conversion time may be shortened, with lower resolution, by short
cycling. Connect pin 5 (Bit 15) to pin 32 (Short Cycle) for 14 bit conyersions.
8. These parameters are listed for reference only and are not tested.
OPTIONAL EXTERNAL ZERO AND GAIN ADJUSTMENTS Initial zero and gain errors may be trimmed to zero using
external potentiometers as shown in the following diagrams.
Adjustments should be made following warmup, and to avoid
interaction, zero should be adjusted before gain. Fixed
resistors can be ±20% carbon composition or beller. Multiturn potentiometers with TCR's of 100ppm/oC or less are recommended to minimize drift with temperature. If these adjustments are not used, pin 28 should be connected as
described in the Range Selection section.
ZERO ADJUSTMENT-Connect the zero adjust potentiometer as shown. For unipolar ranges, apply the input voltage at
which the 0000 0000 0000 0000 to 0000 0000 0000 0001 transition is ideally supposed to occur. While continuously converting, adjust the zero potentiometer until all bits are "0" and the
LSB "flickers" on and off. For bipolar ranges, apply the input
voltage at which the 0111111111111111 to 100000000000
0000 transition is ideally supposed to occur. While continuously converting, adjust the zero potentiometer until all bits
"flicker" on and off.
DIGITAL OUTPUT CODING
+F.S.
+F.S.
+ F.S. - 3/2 LSB
+ % LSB
- '/2 LSB
+ VtF.S.
- 3/2 LSB
+% LSB
0
lOkU
- Vz LSB
_3/ZLSB
- F.S.
+ '/2
-F.S.
LSB
.
180kll
180kll
P,"~
28
or
100kO
f
'Okll
10
l00kll
22kll
-15V
-:
-15V
GAIN ADJUSTMENT-Connect the gain potentiometer as
shown, and apply the input voltage at which the 1111 1111
1111 1110 to 1111 1111 11111111 transition is ideally supposed to occur. While continuously converting, adjust the
gain potentiometer until all the output bits are "1" and the
LSB "flickers" on and off.
i
+ 15V
Pin
1OMO
25~
Pin
26
J
°S'
+15V
10kO
10
1MU
270kO
10k!)
10
100kll
or
lOOk!)
00kO
_15:
DIGITAL OUTPUT
BIPOLAR RANGES
+ F.S. - 3!2 LSB
+ 'hF.S. + % LSB
+ % F.S.
f
.
1.8MO
~;~IO
-15V
INPUT RANGE SELECTION
ANALOG INPUT
UNIPOLAR RANGES
+15V
+15V
MSB
ANALOG INPUT VOLTAGE RANGE
LSB
1111111111111111
l1111111111111Hf*
1000 0000 0000 ooog-
Il'trtrtrtrtrtrti1lrl1!'~'011111111111111,0000 0000 0000 000l!-
PIN CONNECTIONS
±SV
::t:l0V
Oto +5V
Oto +10V
Oto +20V
±2.SV
Connect Pin 7 to Pm
26
26
26
24
24
24
Connect Pin 9 to Pm
28
Open
Input
28
Open
Input
Connect Pin 28 to Pin
9
Open
Open
9
Open
Open
Connect Input to Pin
8
8
9
8
8
9
Input Impedance (KU)
2.5
5
10
2.5
5
10
0000 0000 0000 0000
CODING NOTES:
1.
2.
3.
4.
For 10 Volts FSR, 1LSB lor 16 Bits = 152.6.V. lLSB for 14 Bits = 610.4.V.
For 20 Volts FSR, lLSB for 16 Bits = 305.2.V. lLSB for 14 Bits = 1.22mV.
For unipolar ranges, the coding is slraighl binary.
For bipolar ranges, the coding is offset binary.
* Analog voltages listed are the theoretical values for the transitions in·
dicated.ldeally, with the MN5295/MN5296 continuously converting, the Oul·
put bits indicated as,ilwill change from a "I" to a "0" or vice versa as the in·
pul vollage passes Ihrough Ihe level indicaled.
USING TRACK·HOLD AMPLIFIERS WITH
MN5295 AND MN5296 AJD CONVERTERS
High-speed, high-resolution, successive approximation type
AID converters, such as MN5295/5296, are severely limited in
their ability to accurately convert dynamic input signals.
Stated differently, these high-resolution, high-throughput
digitizers have limited analog input bandwidth capabilities.
In high-speed data-acquisition or digital-signal-processing
(DSP) applications in which high resolution, high throughput
and high input bandwidth are required, a track-hold (T/H)
amplifier must be used to overcome the AID's inherent bandwidth limitations. The T/H has the ability to follow (track) the
high-speed input signal until it is time to convert it. When
commanded into the hold mode, the T/H instantaneously
"freezes" the input signal and holds it constant while the AID
performs its conversion.
The MN374 High-Speed, High-Resolution T/H Amplifier has
been designed specifically as a companion T/H for MN52951
5296 AID's. A typical application is described below. Please
see the MN5290/5291 data sheet for a general discussion of
important factors to consider when selecting a T/H for use
with higher resolution AID's.
EXAMPLE: For Ihe ± 10V range, the Iransition from output code 1111
111111111111 to outpul code 1111111111111110(orviceversa)will ideally
occur at an inpul cf T 9.999542V (+ F.S. - 'I,LSB). Subsequently, any
voltage grealer Ihan + 9.999542V will give a digital oulput of all
"l's." The Iransilion fr"m digital oulput 01111111 1111 11111010000000
0000 0000 (or vice versa) will ideally occur al an input of - 0.000153 volls. The
0000 0000 0000 0000 10 0000 0000 0000 0001 Iransition will occur al
- 9.9GGS47V. An inpul more negalive Ihan Ihis level will give all "O·s."
For slower speed AID converters, the most popular technique
used to control the T/H's operation is to drive the T/H directly
with the AID's status line. For virtually all high-resolution
AID's in use today, including MN5295/5296, this technique
does not work because the T/H's track-to-hold transients will
not reliably settle fast enough. The application described
below is a much more cautious way to control the T/H-A/D
timing because it uses a timed one-shot to delay the start of
the AID conversion. The circuit allocates a predetermined
amount of time for the track-to-hold transient to fully settle
before initiating the AID conversion. After the conversion has
been completed, the circuit immediately drives the T/H back
into the track mode.
The principles discussed below are general and can be used
for virtually any T/H-A/D combination. The system is run by an
externally applied clock whose frequency determines the
overall sampling/digitizing rate. Please refer to the timing
and schematic diagrams below as well as the MN374 T/H
data sheet.
The system consists of the AID, the T/H, a single one-shot and
a dual flip-flop. The falling edge of the system clock triggers
the 74LS123 one-shot, and the system clock can have any
duty cycle as long as it has a minimum positive pulse width of
6-141
50nsec to accommodate the setup-time requirement of the
one-shot.
The one-shot produces a 500nsec pulse, and both the 0 and Q
outputs are utilized. The 0 output becomes the start pulse for
the MN5295/5296, and the Q output drives the set pin of the
first half of the 74LS74 flip-flop. The 01 output of the flip-flop
controls the operational mode of the MN374 T/H. The falling
edge of the Q output of the 74LS123 asynchronously sets the
flip-flop driving its 01 output high and its 01 output low. The
MN374, which has an active-low control line, is immediately
driven into its hold mode by the falling edge of 01.
The pulse width of the 74LS123 has been selected so that
there is now ample time for the MN374 track-to-hold transient
to fully decay before the AID conversion begins. After
500nsec, the 0 output of the one-shot drops to "0" initiating
the AID conversion, and driving the Status output (pin 1)of the
AID to a "1 ". The T/H remains in hold because the rising edge
of the Q output of the one-shot does not affect the first flipflop. The rising edge of Status asynchronously resets the second flip-flop driving the 02 output low.
The TIH remains in the hold mode for the next 17!,sec as the
AID completes its conversion. At the end of t'Je conversion,
the AID's Status line drops to a "0", and this sets the second
flip-flop. The 02 output goes high clocking the first flip-flop
which has a "0" on its D line. This forces the 01 output low
and the 01 output high driving the TIH back into the signalacquisition (track) mode.
The status of this system can be monitored at a number of
different pOints. Whenever pin 1 (Status) of MN529515296 is a
logic "1", the AID is performing a converSion, and output data
is not valid. The falling edge of this line signals that the conversion is complete and that output data is now valid. The 01
output of the first flip-flop can be used to monitor the T/H.
Whenever this line is a "1 ", the TIH is in the hold mode. When
it is a "0", the TIH is in the track mode. The falling edge here
also indicates that a conversion has just been completed and
that output data is now valid. If an external latch is to be used
to clock data away from MN529515296, either of the falling
edges described above may be used to strobe the latch.
Remember that the above application does not automatically
take care of the TIH acquisition time and that this time must
be allowed for in determining the external clock period. If the
MN529515296 requires 17!,sec to make a conversion, and the
T/H requires 4!,sec for acquisition time, adding 2!,sec of overhead time yields a period of 23!,sec. That means the system
can be clocked at 43kHz and still be guaranteed to meet full
accuracy and linearity performance.
It is unnecessary to have the 74LS123 one-shot in the application if the externally applied clock can be made to be a
series of 50nsec-wide positive pulses occurring at a 43kHz
rate. In other words, if the clock can be made to look like the
output of the one-shot in our timing diagram, it is unnecessary to have the one-shot. The clock can drive the MN52951
5296 directly, and it can be inverted to drive the 74LS74.
MN374
+15V-15V +5V
+15V-15V
(11)
Analog
Input
Olgllal
Output
(13)
(4.61
f--------o
AJDStatus
~------<
l1HStalus
System
Clock
IC2",7~L~74
1-----------
25••o c - - - - - - - 1
74LS123 Q
74LS123 l:i
AID Status _ _ _ _ _---'
a; -----,
Data Valid
Converting
Hold
~----------------~
T/H Statu.
----1r -----:-:H:::ol7"d- - - - - - ,
Track
Track
ORDERING INFORMATION
Integral Linearity
(%FSR, Max.)
Specified
Temperature
Range
Conversion
Time
(!,sec, Max.)
+2S"C
Temp.
MN5295
MN5295H
MN5295H/B
O'Cto + 70'C
- 55'C to + 125'C
- 55'C to + 125'C
17
17
17
±0.003
±0.003
±0.003
±0.006
±0.006
±0.006
14 Bits
14 Bits
14 Bits
1200
1200
1200
32-pin DIP
32-pin DIP
32-pin DIP
MN5296
MN5296H
MN5296H/B
O'Cto +70'C
- 55'C to + 125'C
- 55'C to + 125'C
17
17
17
±0.006
±0.006
±0.006
±0.012
±0.012
±0.012
13 Bits
13 Bits
13 Bits
1200
1200
1200
32-pin DIP
32-pln DIP
32-pin DIP
Part
Number
Contact factory for availability of CH device types.
6-142
No Missing
Power
Codes Over Consumption
Temperature (mW,Max.)
Package
r-
L-
r--
MN5825
_
COMPLETE
1pSec, a-Bit
ND CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Complete AID with
Internal Clock
and Reference
• 1"sec Maximum
Conversion Time
• Logic-Controlled Unipolar
or Bipolar Operation
• ±1/2LSB Max Integral
Linearity Error
• No Missing Codes
Guaranteed Over Temperature
• Small 24-Pin DIP
• Pin Compatible ADC815/825
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
24 PIN DIP
-1 t
"'\------, T
P~N 1
~.~~ l~:::
~
',;::1
1.275132.38)
1.315(33.40)
1.100(27.94)
~
w 10
:
1
,01610.411
0020(0.51)
0.200(5.08)
0.230(5.84)
MN5825 is a complete, high-speed, 8-bit AID converter. It
contains its own internal reference and clock and guarantees a
maximum 1"sec conversion time. This is a successive approximation type AID, and unlike other AID's in its speed class, it
does not require heavy external support circuitry (references,
input buffers, trimmers, etc.). It is functionally laser trimmed for
gain, offset and linearity completely eliminating the need for
external trimming potentiometers. MN5825 is pin and function
compatible with other ADC825 8-bit AID's and offers greater
reliability resulting from an improved, lower-chip-count design.
MN5825 guarantees ± lhLSB maximum integral linearity error,
and "no missing codes" is guaranteed over either the O°C to
+70 oC or -55°C to +125°C operating temperature range. Initial
offset error is guaranteed not to exceed ± lhLSB. Output data is
available in either parallel or serial format. Digital output coding
is straight binary for unipolar input ranges and either offset
binary or two's complement for bipolar input ranges.
MN5825 is hermetically sealed in an industry-standard, 24-pin,
ceramic DIP and offers 3 unipolar (0 to +5V, 0 to + 10V and 0 to
+20V) and 3 bipolar (±2.5V, ±5Vand ±10V) input ranges.
Each unit has the unique ability to be switched from unipolar to
bipolar operation with a TTL-compatible control signal applied to
one of the device pins.
I
The MN5825 family includes 5 models as summarized below.
For military/aerospace or harsh-environment commercial!
industrial applications, MN5825H/B CH is fully screened to
MIL-H-38534 in Micro Networks' MIL-STD-1772 qualified facility.
Model
Number
MN5825
MN5825E
MN5825H
MN5825H/B
MN5825H/B CH
Conversion
Time
1"sec
1"sec
1"sec
1"sec
1"sec
Specified
Temperature Range
O°Cto +70°C
-25°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
f.O.120C3.0S1
0.170(4.32)
I.-0600(1524)..J
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
February 1992
Copyright©1992
Micro Networks
All rights reserved
324 Clark St .. Worcester. MA 01606 (508) 852·5400
6-143
MN5825 HIGH-SPEED 8-Bit AID CONVERTER
ORDERING INFORMATION
PART NUMBER - - - - - - - - MN5825H/B CH
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN5825
MN5825E
MN5825H, 5825H/B
Storage Temperature Range
+15V Supply (+Vee, Pin 3)
-15V Supply (-Vee, Pin 4)
+5V Supply (+Vdd, Pin 15)
Analog Inputs (Pins 9, 10 and 11)
Digital Inputs (Pins 8 and 12)
SPECIFICATIONS (TA
-55°Cto +125°C
O°Cto +70°C
-25°C to +85°C
-55°C to +125°C
-65°Cto +150 oC
-0.5 to +18 Volts
+0.5 to -18 Volts
-0.5 to +7 Volts
±25 Volts
to +5.5 Volts
o
Standard Part is specified for O°C to +70°C
operation.
Add "E" suffix for specified -25°C
to +85°C o p e r a t i o n . - - - - - - - - - - - I
Add "H" suffix for specified -55°C
to +125°C operation.
Add "/B" to "H" devices for
Environmental Stress Screening.------......
Add "CH" to "H/B" devices for
100% screening according to MIL-H-38534.----..I
----------01
=+25°C, ±Vce= ±15V, +Vdd=+5V unless otherwise indicated)
ANALOG INPUTS
Input Impedance:
a to
a to
a to
TYP.
MIN.
MAX.
o to
Input Voltage Ranges: Unipolar
Bipolar
+5V. ±2.5V
+IOV, ±5V
+20V, ± 10V
UNITS
+5, 10.20
± 2.5. ±5. ± 10
Volts
Volts
1.34
2.29
4.27
kll
kll
kll
DIGITAL INPUTS (Start Convert, Bipolar Offset)
Logic Levels All Inputs: Logic "I"
Logic "0"
+0.8
Volts
Volts
+80
-3.2
+40
-1.6
I.A
mA
I.A
mA
±V4
± '/2
±1f2
LSB
LSB
±'h
±I
LSB
+2.0
Logic Currents: Start Convert: Logic "I" (VIH = +2.4V)
Logic "0" (Vll = +O.4V)
Bipolar Offset Control (Note 4): Logic "I" (V'H = +2.4V)
Logic "0" (V'l = +0.4V)
TRANSFER CHARACTERISTICS (Note 5)
Integral Linearity Error: Initial (+25°C)
Over Temperature (Note I)
Differential Linearity Error
No Missing Codes
Guaranteed Over Temperature
Unipolar Zero Error (Note 6): Initial (+25°C)
Drift (Note I)
± V4
±IOO
±'h
±150
~V/oC
LSB
Bipolar Zero Error (Note 7): Initial (+25°C)
Drift (Note I)
..
±1f4
±25
±I
±50
LSB
ppm of FSR/oC
Gain Error (Note 8): Initial (+25°C)
Drift (Note I)
±I
±50
±3
±IOO
LSB
ppm/DC
DlGITA!. OUTPUTS (Serial, Parallel, Status, Clock)
Output Coding (Note 9): Unipolar Ranges
Bipolar Ranges
SB
OB, TC
----
Logic Levels: Serial. Parallel, Status: Logic "I" (I SOURCE ,,;16OI.A)
Logic "0" (ISINK ,,;4mA)
Clock: Logic "1" (tSOURCE ,,;24OI.A)
Logic "0" (ISINK ,,;4mA)
+0.4
Volts
Volts
Volts
Volts
1
~sec
100
40
nsec
nsee
Delay Falling Edge of Clock to Output Data
Valid (Parallel, Serial, Status)
35
nsee
Delay Falling Edge of Status to LSB Valid
35
nsec
+2.4
+0.4
+2.4
DYNAMIC CHARACTERISTICS
Conversion Time (Note 10)
Start Convert Pulse Width (Note 2)
Delay Rising Edge of Start Convert to Status=1
50
POWER SUPPLIES
Power Supply Range: ± 15V Supply
+5V Supply
Power Supply Rejection (Note 3): +15V Supply
-15V Supply
+5V Supply
±14.5
+4.75
±15
+5
±15.5
+5.25
±0.004
±0.004
±0.001
Volts
Volts
%FSR/%Vs
%FSR/%Vs
%FSR/%Vs
Current Drain: +15V Supply
-15V Supply
+5V Supply
+25
-10
+80
+35
-15
+100
mA
mA
mA
Power Consumption
925
1250
mW
6-144
SPECIFICATION NOTES:
8. Gain error is defined as the error in the slope of the converter transfer function.
It is expressed as a percentage and is equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value for the full input voltage span
from the input voltage at which the output changes from 0000 0000 to 0000 0001
to the voltage at which it changes from 1111 1110 to 1111 1111.
9. Coding applies for both serial and parallel outputs. Serial output is in standard
NRZ format with MSB appearing first. SB=straight binary. OB=offset binary.
TC=two's complement.
10. Conversion time is defined as the width of Status. Listed specifications assume
start convert pulse is 50nsec wide.
1. Listed specificalions apply over the O·C to + 70·C temperature range for MN5825,
overthe -25·Cto +85·Ctemperature range for MN5825E and overthe -55·C
to + 125·C temperature range for MN5825H and H/B.
2. Rising edge of start convert pulse resets converter. Falling edge starts clock and
initiates conversion. See Timing Diagram.
3. Power supply rejection is defined as the change in the analog input voltage at
which the 1111 1110 to 1111 1111 or 0000 0001 to 0000 0000 output transitions occur verses a change in power-supply voltage.
4. Apply logic "1" for bipolar operation, logic "0" for unipolar operation.
5. FSR stands for full scale range and is equivalent to the nominal peak-ta-peak
voltage of the selected input range, i.e., FSR=5 Volts for 0 to +5Vand ±2.5V
ranges. FSR=10 Volts for Oto + lOY and ± 5V ranges. FSR=20 Volts for Oto +2OY
and ± lOY ranges. For an 8-bit converter, lLSB=0.39%FSR.
6. Unipolar zero error is £Iefined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 0000 0000 to 0000 0001
when operating on a unipolar range. See Digital Output Coding.
7. Bipolar zero error is defined as the difference between the ideal and the actual
input voltage at which the digital output just changes from 01111111 to 10000000
when oPerating on a bipolar range. See Digital Output Coding.
Specifications subject to change without notice as Micro Networks reserves the right
to make improvements and changes in its products.
PIN DESIGNATIONS
BLOCK DIAGRAM
Start Convert (12)
~}-1i
~
Successive
Approximation
Register
-I
0 (1) Senal Output
f-
Clock Output (13) ,,)
+ 15V Supply
- 15V Supply
J----
(17) MSB
(4)
0---
(18) 811 2
+ 5V Supply (15) J -
(19) Bit 3
--
(20) Bit 4
Analog (5. 6. 7)
Ground
~
a
(21) Btt 5
._-
5V Range (9) 'J
-
10V Range (101 J- --~
20V Range (111 2'
12
13
I
(22) Bit 6
(23) Bit 7
~Bipolar Offset Control (8) 0
24
rl>~ (16) MSB
(3)
Power Ground (14)
•
PIN 1
D (2) Status (E.O.C.)
~
Switch
DIA Converter
I
11<1/
2kll
4kn
(24) LSB
I
1
I
I
1
1
4500
'---
I
Comparator
l>
1
2
3
4
5
6
7
8
9
10
Serial Output
Status (E.O.C.)
+ 15V Supply
- 15V Supply
Analcg Ground
Analog Ground
Anal':>g Ground
Bipc lar Offset Control
Analog Input, 5V Range
An;;,log Input, 10V Range
11 Analog Input, 20V Range
12 Start Convert
24 Bit 8 (LSB)
23 Bit 7
22 Bit 6
21 Bit 5
20 Bit 4
19 Bit 3
18 Bit 2
17
16
15
14
13
~(MSB)
Bit 1 (MSB)
+ 5V Supply
Power Ground
Clock Output
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-See Block Diagram. The
Successive Approximation Register (SAR) is a set of flip flops
(and control logic) whose outputs act as both the direct (parallel)
data outputs of the Analog to Digital Converter (AID) and the
digital drive for the AID's internal Digital to Analog Converter
(D/A). The riSing edge of the start convert pulse applied to pin
12 resets the converter (MSB =·0, all other bits = 1 and
Status = 1). The internal clock is enabled and the conversion
commences on the falling edge of the start convert pulse. Start
convert must remain low during the conversion.
The DIA internal to the AID continuously converts the AID's
digital output back to an analog signal which the comparator
continuously compares to the analog input signal. The comparator output (" 1" or "0") informs the SAR whether the present digital output (0111 1111 in the reset state) is "greater than"
or "less than" the analog input. Depending upon which is
greater, on the first falling clock edge after the Start has gone
low, the SAR will set the MSB to its final state ("1" or "0") and
bring bit 2 down to a "0". The digital output is now XOll 1111.
The DIA converts this to an analog value, and the comparator
6-145
TIMING DIAGRAM
Start Convert
---11. . . ._____________________
Clock Output
Status (E.O.C.) _ _- - '
Bit 2
\\\\\'1
'\\\\\\J
Bit 3
\\\\\'\j
Bit 4
\\\\\'\J
MSB
o
\\\\\'J
6 \\\\\\1
\\\\\\1
Bit 5
Bit
Bit 7
LSB
Serial Output
\\\\\~
sssssss..\S\SS~
MSB
~_____~~
LSB
TIMING DIAGRAM NOTES:
1. Operation is shown for the digital output 1100 1011.
2. The Start Convert command must be at least SOnsec wide and must remain
low during conversion.
3. The rising edge of Start Convert resets the converter (MSB = 0, other bits = 1,
Status = 1). The internal clock is enabled and the conversion cycle commences
on the falling edge of the Start Convert signal.
determines whether this value is greater or less than the analog
input. On the next falling clock edge, the SAR reads the comparator feedback, sets bit 2 to its final value, and brings bit 3
down to a logic "0". The digital output is now XX01 1111. The
successive approximation procedure continues until all the output bits are set. The falling clock edge that sets the lSB (bit
8) also drops the Status Output to a "0" Signaling that the conversion is complete and turning off the internal clock. Output
data is now valid and will remain so until another conversion
\s started.
LAYOUT CONSIDERATIONS AND GROUNDING-Proper attention to layout and decoupling is necessary to obtain specified
accuracy and speed performance from the MN5825. The unit's
four ground pins (pins 5, 6, 7, 14) are not connected to each
other internally, They must be tied together as close to the unit
as possible and all connected to system analog ground,
preferably through a large analog ground plane beneath the
package.
Power supplies should be decoupled with electrolytic or tantalum
and ceramic capacitors located close to the MN5825. For optimum performance and noise rejection, 1/LF tantalum capaCitors
paralleled with 0.01/LF ceramic capaCitors should be used as
shown in the diagrams below.
6-146
4. Conversion time is defined as the width of the status pulse.
5. The delay from the rising edge of Start Convert to the rising edge of Status
is typically 40nsec.
6. Both serial and parallel data bits become valid on the same falling clock edges.
Serial data is valid on subsequent rising clock edges, and the edges can be
used to clock serial data into receiving registers.
Pin3
Pin 15
'I
1~F
+5V
O.D1~F
1. . . ------'--
Pins 5, 0 _
6,7,14
I
1~F
I
1
C
Ground
Pins 5, 6,
7,14
I
!
+15V
O.D1~F
o_T+-----_+-_
I
1~F T
Pin40
Ground
1°.D1~F
-
-15V
POWER SUPPLY DECOUPUNG
Analog inut leads should be a short as possible and unused analog
inputs must be connected to ground. See Input Range Selection
table,
STATUS (E.O.C.)-Status (End of Conversion, E.O.C., pin 2)
will be set to a logic "1" 40nsec (typical) after the rising edge
of Start Convert; will remain a logic" 1" during the conversion;
and will be set to a logic "0" when the conversion is complete.
Due to propagation delays, the least significant bit (lSB) of a
given conversion may not be valid until 35nsec after Status has
returned low.
START CONVERT -The rising edge of the start convert signal
resets the converter; the MSB is set to a logic "0", the remaining bits are set to a logic "1" and Status (E.O.C.) is set to a
logic" 1". The converter will remain in the reset state until the
start convert signal is brought low. The internal clock is enabled and the conversion commences on the falling edge of the
start convert signal. The start convert positive pulse width is
50nsec minimum and must not exceed 100nsec maximum in
order to meet the 1!,sec conversion time specification. See Timing Diagram.
SERIAL OUTPUT -Serial output data is provided in addition to
parallel data and is in standard non-return-to-zero (NRZ) format
with the MSB appearing first. Serial output data is coded straight
binary (SB) for unipolar ranges and offset binary (OB) for bipolar
ranges. Serial data bits become valid on rising clock edges and
are delayed one clock pulse from valid parallel data bits.
Therefore, rising clock edges may be used to clock serial data
into receiving registers.
BIPOLAR OFFSET CONTROL-Bipolar Offset Control (pin 8)
is a digital input and must be connected to a logic "0" for
unipolar operation or to a logic "1" for bipolar operation. Logic
levels are TTL-compatible and loading is 1 TTL load maximum.
ANALOG INPUTS-MN5825 has three analog inputs and input ranges are configured by selecting the desired full scale
range and grounding the unused inputs. For example, if a 10V
full scale range is desired (± 5V or 0 to + 10V), the input signal
is connected to pin 10, I and pins 9 and 11 are hardwired to
ground. See Input Range Selection table. Bipolar operation is
selected by applying a logic" 1" to Bipolar Offset Control (pin
8) and unipolar operation is selected by applying a logic "0".
See section labeled Bipolar Offset Control.
INPUT RANGE SELECTION
Analog Input Voltage Ranges
Pin Connections
o to
Input Impedance (kll)
Con nect Pi n 9 to
Connect Pin 10 to
Connect Pin 11 to
Connect Pin 8 to
1.34
Input
Ground
Ground
Logic "0"
+5V
o to
+10V
Oto +20V
±2.5V
±5V
±10V
2.29
Ground
Input
Ground
Logic "0"
4.27
Ground
Ground
Input
Logic "0"
1.34
Input
Ground
Ground
Logic "1"
2.29
Ground
Input
Ground
Logic "1"
4.27
Ground
Ground
Input
Logic "1"
tNPUT RANGE SELECTION NOTES:
1. Bipolar Offset Control (pin 8) is a digital input and must be connected to a logic "0"
for unipolar operation or to a logic "1" for bipolar operation.
2. Unused analog inputs must be connected to ground.
DIGITAL OUTPUT CODING
Analog Input Voltage
o to
+5V, +10V, +20V
+F.S.
+F.S.-'i2LSB
+'hF.S.+'hLSB
+ 'hF.S.-'hLSB
+'hF.S.-'i2LSB
+'hLSB
0
±2.5V, ±5V, ±10V
+F.S.
+F.S.-"2LSB
+'hLSB
-'hLSB
-'/2LSB
-F.S.+V2LSB
-F.S.
DIGITAL OUTPUT CODING NOTES:
1.
2.
3.
4.
5.
For 5 Volts FSR, 1 LSB = 19.5mV.
For 10 Volts FSR, 1 LSB=39mV.
For 20 Volts FSR, 1 LSB = 78.1 mY.
For unipolar ranges, the coding is straight binary.
For bipolar ranges, the coding is offset binary or
two's complement if MSB output is used.
Digital Output
LSB
MSB
1111
1111
1000
l!J0"0"l!J
0111
0000
0000
1111
111l!J
0000"
l!Jl!Jl!Jl!J
111.0"
000.0"
0000
• Analog voltages listed are the theoretical values for the transitions indicated. Ideal·
Iy, with the MN5825 continuously converting, the output bits indicated as l!J will
change from "1" to "0" or vice versa as the input voltage passes through the
level indicated.
EXAMPLE: For the ",10V range, the transition from output code lIlt 1111 to
output code 1111 1110 (or vice versa) will ideally occur at an input of + 9.883V
(+ FS - 'I,LSB). Subsequently, any voltage greater than + 9.883V will give a digital
output of all "I s". The transition from digital output 0111 1111 to 1000 0000 (or
vice versa) will ideally occur at an input of - 0.039V. The 0000 0000 to 0000 0001
transition will occur at -9.961V. An input more negative than this level will give
all "O's."
6-147
QJ] MICRO NETWORKS
~
6-148
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
MN5902
l_1:D MICRO NETWORKS
8-Bit, 20MHz CMOS FLASH AID
CONVERTER
DESCRIPTION
FEATURES
The MN5902 is a high-speed, 8-bit monolithic CMOS Flash AID
converter that provides a 20MHz sampling rate over its full
operating temperature range. Operating from a single +5V
supply, the MN5902 provides high-speed performance while
consuming less power than other available 8-bit, 20MHz
devices. Its 3-state latched data outputs include an overflow
signal that allows easy cascading of two devices to obtain 9-bit
resolution.
• 20MHz Sampling Rate
• Single +5V Supply Operation
• Low Harmonic Distortion
• Latched 3-State Outputs
The MN5902 utilizes 255 CMOS sampling comparators to convert the analog input signal into a digital output word; one additional comparator provides an overflow signal when an input
overrange condition occurs. Proprietary circuitry auto-zeros the
comparators during each conversion to eliminate any dc offset
errors that might arise from comparator mismatches.
• Easy Cascading to 9 Bits
• Low 350mW Power
Consumption
• Small 24-Pin DIP
The MN5902 operates in a pipelined mode, which allows high
sampling rates and helps to eliminate spurious codes. A companion device, the MN5908, operates in a transparent mode, which
allows one-shot operation for subranging and sampling applications (see the MN5908 data sheet).
• -55~to +125~
Operating Temperature Range
• Optional Environmental
Stress Screening
Outstanding performance features of the MN5902 include
guaranteed maximum differential and integral linearity specifications as well as no-missing-codes performance over the full
operating temperature range. The MN5902 is specified for O°C
to +70°C operation; the MN5902E is specified for -25°C to
+85°C operation while the MN5902H is specified for -55°C
to + 125°C operation. For military/aerospace applications, the
MN5902H/B is available with Environmental Stress Screening.
24 PIN SIDE-BRAZED DIP
0.030(0.78)
1-'
PIN 1
1.185 (30.19)
1.100(27.94)
' -:=Jl~') s.~
!--r:
0580 (14.73)
A-
0.240 (6.10)
=::.:;:
8 00 (1524)
~
~
~~~~:!.:g
APPLICATIONS
Video Digitizers
Medical Imaging
RADAR Systems
Thermal Imaging
Pulse Measurement Systems
Waveform Analyzers
Subranging AID Converters
ECM Equipment
Synchronous Demodulation
Infrared Imaging
0.008(0.201
0.012(0.30)
Communications
0.600(15.24)-J
This data sheet contains preliminary information regarding the MN5902. Please contact
the factory for up-to-date performance and product information.
Dimensions in Inches
(millimeters)
[1JJ
_
MICRO NETWORKS
May 1992
Copyright©1992
Micro Networks
All rights reserved
324 Clark Sl., Worcester, MA 01606 (508) 852-5400
6-149
I
MN5902 a-Bit, 20MHz CMOS FLASH AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature. Range:
Specified Temperature Range:
MN5902
MN5902H or MN5902H/B
Storage Temperature Range
+5V Supply (Pin I, 10, 19)
Digital Inputs (Pins 2, II, 12)
Digital Outputs: (Pins 13-17, 21-24)
(Short-circuit protected to Ground)
Analog Input
ORDERING INFORMATION
-55°C to +125°C
OOCto +70°C
-55°Cto +125°C
-65°C to +150°C
-0.5 to +7.0 Volts
-0.5 to +5.5 Volts
-0.5 to +5.5 Volts
PART NUMBER - - - - - - - - - - MN5902 HIB
Standard device is specified for O°C to
+70 oC operation.
Add "E" suffix for "725°C to +85°C operation. Add "H" suffix for -55°C to + 125°C
operation.-------------------'
Add "/B" suffix to "H" model for
Environmental Stress Screening. - - - - - - - - - - - '
-0.5 to Voo +0.5 Volts
SPECIFICATIONS (TA = + 25°C, Voo = +5.0V, VREF + = +3.0V, VREF _ =OV, and sampling rate =15MHz unless otherwise indicated)
ANALOG INPUT
Input Voltage Range
Input Capacitance: Static
Dynamic
REFERENCE INPUTS
Reference Ladder Resistance
Reference Input Range
MIN.
TYP.
0
MAX.
UNITS
3.5
Volts
pF
pF
10
32
+0.5
300
+3.0
+3.5
Ohms
Volts
+0.01
-0.01
+1.5
+5
-5
4.9
0.1
0.4
Volts
Volts
8
±0.35
±0.4
±0.85
±1.5
±0.6
±0.6
±1.0
±1.8
Bits
LSB
LSB
LSB
LSB
DIGITAL INPUTS
Logic Levels: Logic "I"
Logic "0"
Logic Currents: Logic "I" (VIH=+4.0V)
Logic "0" (VIL=+0.4V)
Minimum Clock Pulse Width
+3.5
20
Volts
Volts
pA
pA
nsee
DIGITAL OUTPUTS
Logic "I" Voltage at 4mA Load
Logic "0" Voltage at 4mA Load
4.5
TRANSFER CHARACTERISTICS
Resolution
Differential Linearity: Initial
Over Temperature
Integral Linearity: Initial (Note 1)
Over Temperature
No Missing Codes
Guaranteed Over Temperature
Zero-Scale Offset (Note 2)
Gain Error: Initial
Over Temperature
40
70
1.0
1.5
mV
LSB
LSB
20
TBD
-48
-44
MHz
dB
dB
40
10
50
20
25
MHz
nsec
-5
0
50
+5
nsec
psec
+4.5
+5.0
±0.01
+70
+93
+5.5
+0.02
+80
+100
Volts
%FSR/%V oo
rnA
mA
DYNAMIC PERFORMANCE
Sampling Rate
Signal-to-Noise Ratio
Total Harmonic Distortion
(4MHz Analog Input)
Full-Power Bandwidth
Output Data-Valid Delay
(From Rising Clock Edge)
Aperture Delay
Aperture Uncertainty
POWER SUPPLY REQUIREMENTS
Power Supply Range
Power Supply Rejection
Power Supply Current: Initial
Over Temperature
SPECIFICATION NOTES
1. Integral linearity specifications are based on end-point measurements, and
assume an unadjusted reference mid-point.
2. Zero-scale offset is the difference between the measured input voltage required
to produce the transition of code 00000000 to code 00000001, and the voltage
theoretically corresponding to 0.5LSB.
6-150
BLOCK DIAGRAM
Analog Input (5, 7)
(13) Overflow
(14) Bit 1 (MSB)
R"4(t8) e>--.
(15) Bit 2
(16) Bit 3
256:8
Data
Binary
Output
Encoder
Latch
(17) Bit 4
(21) Bit 5
(22) Bit6
R'14 (20) cr-.
(23) Bit 7
(24) Bit 8 (LSB)
(11)CS1
(12)CS2
V REF _ (3)
Clock Input (2)
o-_ _ _ _.J
00-------------'
+VDD Supply (1, 10, 19) 0 0 - - - -..
Ground (4, 8) O~---+
6-151
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - The block diagram illustrates
the architecture of the MN5902, a fully parallelS-bit AID converter.
A total of 256 sampling comparators are used to convert the signal
on the VIN line to a digital word. The pulses at ti'1e ClK input are converted intemally into the three phases that control the operation of
the comparators. The first cycle, Phase 1, is initiated when the ClK
switches to the high state. An analog switch at the input to each comparator then samples a reference voltage that is established by a
256-element resistor ladder between the VREF+ and VREF- pins.
Each unique reference-voltage tap represents one of the quantization levels to which the signal at VIN will be compared.
Overlapping with Phase 1, the Phase 2 cycle serves to auto-zero the
comparators. This operation has the purpose of cancelling dc-offset
errors that arise from device mismatch between comparators. M. the
end of the Phase 2 interval, the capacitor at the input to each comparator stores the difference between the reference tap voltage and
the auto-zeroed bias point. The capacitor will hold the comparator
at a high-gain trigger point in preparation for sampling the input signal.
The low-going transition of the clock terminates the auto-zeroing interval and initiates the input-sampling interval. The Phase 3 period
is norH>Vel1apping with Phase 2 to minimize coupling of the reference
to the input. A sampling glitch will be observed on the VIN line at the
beginning of Phase 3, as the ioput buffer amplifier must charge or
discharge the coupling capacitors from their reference levels to the
new level of the input signal. The comparators serve as track-andhold amplifiers over the duration of the sampling interval. When the
clock returns high, the sampling switches are turned off and the comparator levels are latched into fiip-flops.
To determine the quantized level of the input signal, it is necessary
to find the transition points between comparators that produce logic
"1" results and those that produce logic "0" results. This transition
point, corresponding to the signal residing at the end of the sampling interval, will lie within a 1lSB (least-significant-bit) voltage range.
This function of thermometer decoding is fulfilled by the 3-input NAND
gates at the output of each comparator latch.
The thermometer decoder will cause just one of the 256 NAND gates
to assume a low-level output. This signal will represent an address
to the 256-t0-8 encoder, which can then produce a properly encoded binary output. Latches on the digital outputs can be used to store
the digitized result. The MN5902 utilizes latches in a signalprocessing pipeline fashion. Digital inputs, CS1 and CS2, are used
to set the latches' outputs to the high-impedance state.
For the MN5902, the total conversion period upon start-up is two clock
periods (see the timing diagram in Figure 2); the -conversions proceed thereafter at the clock rate.
DIGITAL OUTPUT CODING
ANALOG INPUT
VOLTAGE (Voe)
+VREF
+VREF -1/2lSB
+VREF-lSB
+VREF "':3/2lSB
+1/2VREF + 1/2lSB
+1/2VREF -1/2lSB
OVERFLOW
1
~
0
0
DIGITAL OUTPUT
MSB
LSB
1111
1111
1111
1111
1111
1111
1111
11111
1000 00016
gggg ggg16
+ 1/2VREF -3/2lSB
0
0
0
+1/2lSB
0
0
0
0000 00011
0000 0000
0111
11111
Analog inputs indicated are the theoretical values for the transitions of the
codes indicated above. With the converter continously converting, the output bits indicated as,il'will change from logic "0" to logic "1" or vise versa
as the input voltage passes through the indicated level.
6-152
LAYOUT AND GROUNDING CONSIDERATIONS - The MN5902
and other high-speed devices require that careful consideration be
given to high-speed and low-noise design techniques. Care must be
taken to assure that seperation of analog signals and digital signals
is maintained. The use of ground and power planes as well as signal
shielding are highly recommended. Bypass capacitors should be
used and located as close to the device as possible. It is also recommended that circuitry interfacing to the MN5902 be located as close
to the device as possible to minimize transmission line effects.
3-STATE OUTPUT CONTROL - Both CS1 and CS2 can be used
to enable the 8-bit output lines or to set them to the high-impedance
state. CS1 controls the 8-bit output lines, while CS2 controls both the
output lines and the Overflow output. This arrangement makes it
possible to stack two devices in a 9-bit configuration, in which
Overflow becomes the MSB (most-significant bit), and to select the
lower eight bits from either the upper or lower AID converter.
TRUTH TABLE
CS1
CS2
B1-B8
OVERFLOW
0
1
X
1
1
0
Valid
High-Z
High-Z
Valid
Valid
Hlgh-Z
INTERMEDIATE RESISTOR TAPS - Intermediate taps at each
quarter point of the reference resistor ladder are brought out to
package pins. In high-speed operation, it is necessary to provide
capacitive decoupling of these points to ground in order to prevent
clock noise from interfering with the conversion.lt is possible to adjust
the dc potentials at these points to trim integral linearity, or to obtain
a non-linear transfer characteristic.
CASCADING FOR 9-BIT OPERATION - It is possible to stack or
cascade two MN5902 Flash AID converters to configure a 9-bit
digitizer. Cascading entails connecting the reference-resistor ladders
in two devices in series. The bottom of the upper converter's ladder
(VREF -) connects to the top of the lower converter's ladder (VREF +).
The reference voltage source is connected to VREF + of the upper
converter while the VREF - connection of the lower converter is tied
to ground. Mid-scale of the cascaded AID system is established at
the point where the lower AID converter overflows.
The Overflow output from the lower AID converter detects the overflow
condition and becomes the MSB ofthe 9-bit system, and in addition,
serves to multiplex the lower eight bits between the two AID converters.
Two output controls are provided by the MN5902. CS2 controls the
3-state output function of the eight data output bits plus the overflow
output. A logic "1" applied to the CS2 input enables these out~
while a logic "0" forces the output into the high-impedance state. CS1
onli'has an effect on the eight data output bits. A logic "0" applied
to CS1 enables these data lines while a logic "1" forces them into
the high-impedance state.
In the cascaded configuration, the MSB is set high (upon the overflow
condition of the lower 8-bit AID converter), it disables the lower data
output bits while enabling the output bits and overflow bits of the upper
AID converter. Because the upper AID converter is experiencing an
underflow condition at the crossover point, a proper mid-scale code
is produced. A 9-bit system overflow signal is available from the upper
AID converter.
The use of signal input buffer amplifiers are recommended in
cascading applications. Separate signal paths for each AID converter
provide several benefits. First, input bandwidth and settling time performance in the switched-capacitor input of each MN5902 will benefit
from being driven from a unique source. Secondly, offset and gain
errors in each AID will manifest themselves as large differential
and integral linearity errors in the output transfer function of the
9-bit system.
sion for the gain is 1+ RF/Req, where Req is the parallel combination of the resistors at the amplifiers input with the feedback path
disconnected. Because gain and offset are interrelated, the offset
potentiometer should be large relative to the other resistor (10K Ohms
for example).
To minimize these errors, it is possible to effect separate adjustments
on the CLC400 current-feedback amplifiers. The offset potentiometer
of the upper amplifier provides an adjustment for system differential
linearity at the mid-scale point. The gain of the amplifiers provide a
means for achieving gain matching between the two eight-bit devices
thereby allowing trim of the system integral linearity error. The expres-
Figure 3. MN5902 9-Bit Cascade Connection
ClK VREF+
Clock
~C400
Analog Input
C'd V
V1N
J-
-5V
f--
CS1
r- CS2
V REF _ OF
Overflow
v
~-
I
'-- ,......
VREF _ OF
V
-5V
-v
(>
.1
B9(LSB)
B8
B7
B6
~C400
r'V D
I--
V 1N
t
, B5
B4
B3
B2
>- CS1
CS2
"
-b-
B1(MSB)
6-153
PIN DESCRIPITONS
PIN
SYMBOL
FUNCTIONAL DESCRIPTION
1
Voo
Supplies power to analog and digital sections
of chip. Nominal level +5v.
2
ClK
Externally supplied clock signal; used internally to generate three distinct phases for the
comparator sampling sequence, comparator
latches, and bit-output latches.
3
VREF-
4
GND
5
V'N
6
RM,o
7
V'N
8
GNO
9
VREF+
10
Voo
11
CSI
6-154
PIN
SYMBOL
FUNCTIONAL DESCRIPTION
12
CS2
Voltage potential at the bottom of the resistor
ladder that sets the lower limit of the NO converter's range. Also sets the offset code for 0
to 1 transition.
13
OF
Ground potential for the analog and digital
circuitry. Also the Silicon substrate potential.
The analog signal input to the lower half of
the NO converter.
14
Bl
15
B2
16
B3
17
B4
18
R3/4
19
Voo
Supplies power to analog and digital sections
of chip. Nominal level +5V.
20
R114
1st quarter point of the NO converter's
resistor ladder, at the boundary between
codes 64 and 65. Normally decoupled through
a capacitor to ground, but can be
used to adjust integral linearity or to impart
a non-linear transfer function.
21
B5
5th most-significant bit of the digitized 8-bit
output. Has a weight of FSR/32.
22
B6
23
B7
24
B8
6th most-significant bit of the digitized 8-bit
output. Has a weight of FSRI64.
7th most-significant bit of the digitized 8-bit
output. Has a weight of FSRI128.
(lSB) least-significant bit of the digitized 8-bit
output. Has a weight of FSR1256.
Midpoint of the resistor ladder, at the boundary between codes 128 and 129. Normally
decoupled through a capacitor to ground,
but may be used to adjust linearity or to
impart a non-linear transfer function.
The analog signal input to the upper half of
the NO converter.
Ground potential for the analog and digital
circuitry. Also the silicon substrate potential.
Voltage potential to the top of the resistor
ladder that sets the upper limit of the NO
converter's range. Can be used to make gain
adjustments. Nominally +3.OV.
Supplies power to analog and digital sections
of chip. Nominal level +5V.
3-state control for output bits Bl to B8.
When CS2 is high, Q!!!put bits are enabled
(When CSI is low). CSI is a don't care (X)
when CS2 is low.
3-state control for output bits Bl to B8 and the
Overflow output. When CS2..!.§l1igh, output
bits Bl to B8 are enabled if CSI is low. CS2
has independent control of the OverflOW output. If CS2 is low, Bl to B8 and Overflow are
in the high-impedance state.
When high, Overflow indicates that the input
voltage exceeds the top reference tap point,
nominally VREF+ -'hlSB. Outputs Bl to B8
assume all "l's" when Overflow is high.
(MSB) Most-significant bit of the digitized 8-bit
output. Has a weight of FSRI2 where FSR
(full-scale range) is VREF+ -VREF-.
2nd most-significant bit of the digitized 8-bit
output. Has a weight of FSRI4.
"3rd most-significant bit of the digitized 8-bit
output. Has a weight of FSRI8.
4th most-significant bit of the digitized 8-bit
output. Has a weight of FSRI16.
3rd quarter point of the NO converter's
resisitor ladder, at the boundary between
codes 64 and 65. Normally decoupled through
a capacitor to ground, but can be
used to adjust integral linearity or to impart
a non-linear transfer function.
TIMING DIAGRAM
Analog
Input
Clock
g~~ut ____-J)(~_____D_a_ta_N_-_1____
_J
~____D_a_ta__N__-J)(~_____
PIN DESIGNATIONS
24
12
13
1 +Voo Supply
2 Clock
3 VREF _
4 Ground
5 Analog Input
6RM1O
7 Analog Input
8 Ground
9 VREF+
10 +Voo
11 CS1
12 CS2
24 Bit 8 (LSB)
23 Bit 7
22 BitS
21 Bit 5
20R 1/4
19 +Voo
18 R3/4
17 Bit 4
16 Bit 3
15 Bit 2
14 Bit 1 (MSB)
13 Overflow
6-155
MICRO NETVVORKS
~
6-156
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
~
MN5903
6-Bit, 75MHz
FLASH AID CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• 6-Bit Resolution
• 75MHz Conversion Rate
• 140MHz Input Bandwidth
• 36dB SNR at 35MHz
• Low Harmonic Distortion
-44dB at 10MHz
-36dB at 35MHz
• Overflow Output (7th bit)
• Low Input CapaCitance, 25pF
• ECL 10K Compatible Output Data
• Operating Temperature Range -55°C
to +125°C, case (S and T Grades)
• Improved Pin-for-Pin Compatibility
with AD9000 (MN5903 Model)
Ii-,
r---'~_.J
The MN5903 is an ultra-high speed 6-bit monolithic Analog to
Digital converter with a guaranteed conversion speed (strobe
frequency) of up to 75MHz. The MN5903 utilizes the "Flash" or
parallel principle whereby a field of 64 comparators simultaneously determine the precise analog input. The comparators'
outputs are converted to ECl compatible outputs through two
encoding stages which are activated by the Encode signal.
The MN5903 is offered in two logic configurations. The MN5903A
is designed to be used as a stand-alone 6-bit AID converter or as
a terminating device for a 7 or a-bit AID. The MN5903 is designed
to be used as a cascading device with the MN5903A for 7 or a-bit
applications. The MN5903 also offers improved performance and
pin-for-pin compatibility to the AD9000.
The MN5903 has a low input capacitance of 25pF and a 13kOhm
input impedance which allows the input to be easily driven by
interfacing circuitry.
The MN5903's broad input bandwidth of 140MHz and low
aperture uncertainty of 25psec eliminate the user's need for an
additional track and hold amplifier. The MN5903 also provides an
overflow signal which indicates when the analog input signal
exceeds the +VREF voltage. A hysteresis control function is provided that allows the user to modify the comparator's sensitivity.
Packaged in a small, 16-pin, hermetically sealed package, the
MN5903 offers an outstanding Signal-to-Noise-Ratio (SNR) of
36dB at 35MHz and low Total Harmonic Distortion (THO) of
-44dB at 10MHz.
Micro Networks offers premium "K" and 'T' grades of the MN5903
and MN5903A devices. Their superior performance includes the
following specifications which are guaranteed over their fl.!.!!
operating temperature range: ±1/2lSB max. differential linearity,
±O.75lSB max. full scale error, 33dB min. SNR at 10MHz analog
input and -35dB max. THO at 1OM Hz analog input.
MN5903 Devices are specified for O°C to +70 oC (case, J and K
models) operation, and 55°C to + 125°C (case, Sand T models)
operation. For applications in harsh-environment industrial or
military/aerospace systems, SIB and T/B models are available
with Environmental Stress Screening.
PlNl
APPLICATIONS
Radar Systems
Digital Oscilloscopes
Automatic Test Equipment
Dimensions in Inches
(millimeters)
[1J]
_
ECM Equipment
Analytical Systems
July1990
MICRO NETWORKS
324 Clark St. Worcester. MA 01606
(508) 852·5400
6·157
MN5903 6 Bit 75MHz FLASH AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range (case)
Specified Temperature Range (case)
MN5903J,MN5903K
MN5903S, MN5903T
Storage Temperature Range
Positive Supply Voltage (+Vs )
Negative Supply Voltage (-Vs)
Analog Input Voltages (V,N • +VREF. -VRE,)
Encode Input Voltage
Hysteresis Control Voltage (VH)
Digital Input Voltages
Digital Output Current
Analog Ground to
Digital Ground Voltage Differential
ORDERING INFORMATION
-55°C to + 125°C
PART NUMBER - - - - - - - - MN5903XXlB
O°Cto +70°C
-55°C to +125°C
-65°C to +150a C
-0.3 to +6 Volts
+0.3 to -6 Volts
-3.5 to +2.5 Volts
-Vs to 0 Volts
Oto 3.0 Volts
-3.5 to +0.0 Volts
20mA
to.5 Volts
I
Select MN5903 or MN5903A Mode\.
Select suffix J, K, S, or T for
desired performance and specified
temperature range. _ _ _ _ _ _ _ _ _ _ _..J
Add "/B" to "S" or "T" models for
Environmental Stress Screening. _ _ _ _ _ _..,.......
ELECTRICAL SPECIFICATIONS (T.=+25°C, +V RE'=+ 1.0V, -V REF=-1.0V, +Vs=+5.0V, -Vs=-5.2V unless otherwise indicated.
Specifications apply to all grades unless specific grades are referenced).
PARAMETER
Min
Typ
Max
6
RESOLUTION
Units
Bits
ANALOG INPUTS
Input Voltage Range over Temperature
Input Bias Current (Sampling)
over Temperature (Note I)
Input Bias Current (Latched)
over Temperature (Note I)
Input Resistance
Input Capacitance (Note 2)
t2
Full Power Bandwidth (Note 3)
140
13
25
700
Volts
j.lA
700
j.lA
50
kOhms
pF
MHz
REFERENCE INPUTS (Note 4)
Reference Ladder Resistance
Reference Ladder Tempco
Reference Input Bandwidth
80
200
Ohms
Ohms/DC
MHz
0.5
1.0
0.35
0.5
LSB
LSB
LSB
LSB
0.5
1.0
0.35
0.5
LSB
LSB
LSB
LSB
0.275
20
TRANSFER CHARACTERISTICS
Differential Linearity: Initial (+25°C): J, S Grades
over Temperature: J, S Grades
Differential Linearity: Initial (+25°C): K, T Grades
over Temperature: K, T Grades
0.25
Integral Linearity: Initial (+25°C): J, S Grades
over Temperature: J, S Grades
Integral Linearity: Initial (+25°C): K, T Grades
over Temperature: K, T Grades
0.25
0.25
0.25
Guaranteed Over Temperature
No Missing Codes
+Full Scale Input Error: Initial (+25°C): J, S Grades
over Temperature: J, S Grades
+Full Scale Input Error: Initial (+25°C): K, T Grades
over Temperature: K, T Grades
-Full Scale Input Error: Initial (+25°C): J, S Grades
over Temperature: J, S Grades
-Full Scale Input Error: Initial (+25°C): K, T Grades
over Temperature: K, T Grades
0.3
0.15
0.25
0.15
7/8
1.5
0.5
0.75
7/8
1.5
0.5
0.75
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
20
13.3
MHz
MHz
nsec
nsec
DYNAMIC PERFORMANCE
Conversion Rate: J Grade
Conversion Rate: K, S, and T Grades
Conversion Time: J Grade
Conversion Time: K, S, and T Grades
50
75
2
25
Aperture Delay (t D )
Aperture Uncertainty (Jitter)
Output Propagation Delay (tpD ) (Note 2, 5)
Output Hold Time (tOH ) (Note 2, 6)
6-158
70
80
7
8
nsec
psec
12
14
nsec
nsec
ELECTRICAL SPECIFICATIONS (Continued)
PARAMETER
Min
Typ
Max
Units
DYNAMIC PERFORMANCE (Continued)
Transient Response Time (Note 7)
13
Overvoltage Recovery Time (Note 8)
Output Rise or Fall Time: J Grade (Note 9)
Output Rise or Fall Time: K, S, and T Grades (Note 9)
11
nsec
5
4.5
nsec
nsec
nsec
ENCODE INPUT
Logic "1"
Logic "0"
Logic "1"
Logic "1"
Voltage over Temperature
Voltage over Temperature
Current over Temperature
Current over Temperature
Encode Pulse Width High (tpw")
Encode Pulse Width Low (tpwL)
-1.1
-1.5
100
100
6.6
6.6
Volts
Volts
~A
~A
\lsec
nsec
AC LINEARITY (Note 10)
Dynamic Linearity (Note 11)
0.5
LSB
In-Band Harmonics
(DC to lMHz)
(1 MHz to 5MHz)
(5MHz to 8MHz)
48
48
46
dBc
dBc
dBc
38
38
37
37
dB
dB
dB
dB
dB
37
36
36
dB
dB
dB
-47
-44
-44
-30
dB
dB
dB
dB
dB
dB
dB
-1.5
Volts
Volts
Signal to Noise Ratio (Note 12)
(540kHz Analog Input): J and S Grades
(540kHz Analog Input): K and T Grades
(10MHz Analog Input): J and S Grades
(10MHz Analog Input): K and T Grades
(10MHz Analog Input): K and T Grades
over Temperature
(20MHz Analog Input)
(35MHz Analog Input): J and S Grades
(35MHz Analog Input): K and T Grades
31
35
35
33
31
Total Harmonic Distortion (THD)
(2MHz Analog Input)
(I OMHz Analog Input): J and S Grades
(1 OM Hz Analog Input): K and T Grades
over Temperature
(20M Hz Analog Input)
(35MHz Analog Input): J and S Grades
(35MHz Analog Input): K and T Grades
-43
-34
-34
-38
-35
I
DIGITAL OUTPUTS (Note 13)
Logic "1" Voltage over Temperature
Logic "0" Voltage over Temperature
-1.1
POWER SUPPLIES
Positive Supply Current (+5.0V)
over Temperature
71
85
90
mA
mA
Negative Supply Current (-5.2V)
over Temperature
~5
75
80
mA
mA
Nominal Power Dissipation
693
mW
Reference Ladder Dissipation
20
mW
SPECIFICATION NOTES
1. Measured with A'N=+V REF ,
2. Listed specification is for reference only and is not tested.
3. Full Power Bandwidth is the input frequency at a 75MHz
sampling rate at which the reconstructed output amplitude
drops 3dB with respect to the output.
4. The differential reference voltages may be varied under
normal operating conditions from ±0.5 Volts to ±2.0 Volts.
+VREF must always be greater than -V R,·,.
5. Measured from leading edge of ENCODE to data out on Bit 1
(MSB).
6. Measured from trailing edge of ENCODE to data out on Bit 1
(MSB).
7. For a full-scale step input, 6 bit accuracy is obtained in the
specified time.
8. Time to recover to 6 bit accuracy after an overvoltage whose
input is equal to 150% of the full-scale input voltage.
9. Measured on the MSB (Bit I) only.
10. Measured at 50MSPS encode rate.
11. Analog Inputfrequency =15MHz.
12. RMS signal to RMS noise.
13. Measured with outputs terminated with 100 Ohm resistors to
-2.0 volts.
6-159
ENCODE
(4)
VH
(3)
AIN
(6)
+REF
+ Vs
- Vs
- REF
A.GND
(15)
OF
(14)
MSB
(13)
BIT 2
(12)
BIT 3
(11)
81T 4
(10)
81T 5
(9)
LS8
(8)
(7)
(1)
Q-----7
LATCH
STAGE
Q-----7
1ST
ENCDR
(AND)
(5) o--vv\!4-~~-H
(2)~
2ND
ENCDR
(OR)
OUTPUT
STAGE
COMPARATORS
D.GND(16)~
Tie pins 2 and 16
together externally
Figure 1.
Block Diagram
APPLICATION INFORMATION
The MNS903A has a nonreturn-to-zero output
logic coding when AIN ~ +VREF • This coding is
desirable for applications that require stand-alone
6-bit NO converters. The MNS903 has a returnto-zero logic coding when AIN ~ +VREF . (See Digital
Output Coding.) This facilitates the cascading of
the MNS903 with the MNS903A for applications
requiring 7 or 8-bits. The MNS903's coding is
usually not desired for stand-alone 6-bit
applications as additional external circuitry is
required to convert the output logic to non returnto-zero coding. The MNS903 is recommended for
those applications that can benefit from superior
performance and pin-for-pin compatibility with the
AD9000.
The MNS903 and MNS903A have open emitter
outputs which allow the output of several devices
to be WIRE-OR'D when cascaded for increased
resolution. Figure 3 shows how the MNS903 and
MNS903A may be stacked together for usage as
a 7-bit NO converter.
HYSTERESIS CONTROL FUNCTION
The MNS903 has a Hysteresis Control Voltage
Input, VH• which allows the user to affect the
comparators' sensitivity. An input voltage of OV to
+3V applied to VH (Pin 3) causes the comparator
hysteresis to vary from approximately 1SmV to
SOmV. IncreaSing the comparator hysteresis
reduces the error rate (number of false full-scale
output codes in a given period). The MNS903 is
tested with the VH input open and produces a very
6-160
low error rate. Use of the hysteresis control
function may be considered for error sensitive
applications, especially those employing a high
(greater than SOMHz) encode rate. The VH input,
when used, should be decoupled to ground
through a 0.1 J.LF ceramic capacitor.
LAYOUT SUGGESTIONS
It is strongly recommended that a substantial
ground plane be placed under and around the
MNS903. It is recommended that the MNS903's
Analog Ground and Digital Ground be
connected together at the MNS903 and also
connected to the ground plane.
The power supplies and reference inputs should
be decoupled to ground directly at the MNS903
with 0.1 J.LF ceramic capacitors in order to reduce
the effects of system noise on converter
accuracy. Chip capacitors will produce the best
results because they do not have the lead
inductance inherent to discrete devices. The
reference inputs should be driven from a loW
source impedance. This will help to minimize
errors caused by noise on the reference source
and also minimize errors otherwise caused by
the reference's source impedance. Test Figure 4
includes circuitry that has been proven to be a
simple and effective means of driving the
reference inputs.
PIN DESIGNATIONS
Pin
Symbol
Function
Pin
Symbol
Function
1
-Vs
Ana Gnd
Negative Supply Voltage.
16
Dig Gnd
Digital Ground
Analog Ground
15
OF
Overflow Signal
Hysteresis Control Voltage
Signal
14
Bit 1
13
Bit2
Bit 1 (MSB)
Bit2
Negative Reference Voltage
Analog Input
12
11
Bit3
Bit 4
Bit3
Bit 4
Positive Supply Voltage
10
Bit5
Bit 5
9
Bit 6
Bit 6 (LSB)
2
3
4
VH
5
6
~VRF.F
7
8
Encode
A'N
+Vs
Positive Reference Voltage
+VREF
•
16
Pin 1
(Top)
8
9
DIGITAL OUTPUT CODING
MN5903
Analog Input
OF MSB
(Bit I)
I
0 0
+VREF
+VREF -1/2LSB
+VREF -3/2LSB
+1/2LSB
0
-1/2LSB
-V REF +1/2LSB
-VREF
MN5903A
Analog Input
Digital Output
.
0
0
a
a
0
0
LSB
(Bit 6)
0
0
0
. . . ·
·
a a a ·
. a. a. a. . a·
a a a a a ·
a a a a a a
I
I
I
I
0
0
I
I
Digital Output
OF MSB
(Bit I)
I
1 1
1
I
I
I
I
0
I
.
+VREF
+VREF -1/2LSB
+V REF -3/2LSB
+1/2LSB
I
·
. . . . ·
·
a
a
a
a a.
a
a
0
a a a
a a a a
a
0
I
I
I
-1/2LSB
-VREF + 1/2LSB
~VREF
LSB
(Bit 6)
I
I
1
I
I
I
I
I
a a ·
a a a
a a
a a a
Note: • indicates a bit transition whereby the output bit(s) is(are) changing from "I" to "0" or vice versa.
The analog input voltages shown above are the theoretical voltages for the corresponding digital output.
Example: With an analog input of -V REF + 1/2LSB, the output code will be at the transition of the codes
to
ANALOG
INPUT
Output Propagation
Delay
ENCODE
OUTPUT
tOH
Minimum Output
Hold Time
t PWH -
Minimum Encode
Pulse Width High
t PWL -
Minimum Encode
Pulse Width Low
X
-
Output data not valid
N
-
Data from sample N
I
~tpD~
~toH~
~x[N\x
I
Aperture Delay
N+2
I
a 000000 and a 000001 .
AxA
Figure 2.
Timing Diagram
is)
,--lli- MN
5903A
~
i')
is)
ANALOG
INPUT 0 - -
~
MN
5903
ENCODE o--~
(15)
OVERRANGE
ff*-----(12)
~
~
~
(15)
(14)
(13)
(12)
(IT)
(ID)
iO)
--0 BIT 7(M58)
86
85
84
-0 B3
-0 82
81T I (L58)
-----::0
")
I')
Figure 3.
Cascading 7-Bit Operation
6-161
':!:
Rl
+5
10k
~
,.
2.5k
9
f/0 (-2V
\!Y
Supply)
30UF
2N2907
+5
-5.2
-5.2
0.1~
,
I~
17
Q-
fD
Iz
8m
P5
I r ; - - - - t - ' -5i PO
~m
0.1
ANALOG
2k
INPUT
100
+5
®
CLOCK
INPUT
100
®
Figure 4.
Test Circuit
100141
100 24 VEE
11~
3 P4
1---'--.-_ _+-,-2--1
~_ _-+...c.'-=.j6 Pl
¥III
!~
18
f--'-=~_ _t--="2=j2 P3
L .... .1
1 P2
2 --1
1---.-_ _+-
;'0
-D
jIl
~0.1
~146X
MSB
L
8, +VR
~s:
~-I
§~
11
~.
®
2
MSB
Q5
I
Q4 3
I
I
I
Q3 4
Q2 5
Ql 8
QO
I
lSB
9
G elK
:r--r:-:
6,/
17
100
®
~
MN5904/5905
100MHz Conversion Rate
140MHz Input Bandwidth
High Input Impedance
ECl 10K Compatible Outputs
Overflow Output (7th Bit)
low 25pF Input Capacitance
Operating Temperature Range -55°C
to +125°C Case (H Grade)
Pin-for-Pln Compatibility With SOA
5200N and SOA 5200S
~)
--j
n
lJ~
The MN5904/5905's 25pF input capacitance and 150pA input
current make the devices extremely easy to drive in highfrequency applications. In addition, the devices' 140 MHz
input bandwidth and 25psec aperture uncertainty eliminate
the need for a track-and-hold amplifier at the input.
Packaged in a small, hermetically sealed 16-pin DIP, the
MN5904/5905 offers outstanding specifications: ± 'l2lSB
maximum differential nonlinearity and ±0.75lSB maximum
full-scale error at 25°C, and no-missing-codes performance
over the full operating-temperature range. MN5904/5905
Series devices are specified for operation over OOC to +70°C
(case) and -55°C to +125°C (case). The MN5904 and
MN5905 are pin-compatible equivalents to Siemens' SDA
5200N and SDA 5200S, respectively.
0.280 (7.11)
if
The MN590415905 is an ultra-high-speed 6-bit monolithic AID
converter capable of operating at sampling rates as high as
100M Hz. The device uses a parallel-comparator, or "flash",
architecture to convert ±2 V analog input signals to ECl-level
outputs through two encoding stages. The converter is
offered in two logic configurations. The MN5905 is designed
for use either as a stand-alone 6-bit AID converter or as a
terminating device or configuring a cascaded 7- or 8-bit AID
converter. The MN5904 is designed for use as a cascading
device in these enhanced-resolution applications.
The MN5904 provides an overflow signal that indicates
analog input voltages in excess of the +VREF voltage. A
hysteresis control function allows the user to optimize input
characteristics by modifying the input comparators' sensitivity.
16-PIN SIDE-BRAZED DIP
r
FLASH AID CONVERTER
DESCRIPTION
FEATURES
r-
6-Bit, 100MHz
MICRO NETWORKS
J_1.-_
J1:~~;~~~
IC
0.14 (3.5)
0.02 (0.5)
0.300 (7.62)",
Dimensions in Inches
(millimeters)
APPLICATIONS
Radar Syslems
Digital Oscilloscopes
Medical Imaging
Analytical Systems
Video Digitizing
Subranging AJD Systems
Video Test Systems
Automalic Test Equipmenl
[1JJ
_
MICRO NETWORKS
324 Clark Street..Worcester. MA 01606
December 1991
Copyright,( 1991
Micro Ne1works
All rights reserved
(508) 852-5400
6-163
MN590415905 6-Bit, 100MHz FLASH AID CONVERTER
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Rance (case)
Specified Temperature Range (case)
MN5904, 5905
MN5904E,5905E
MN5904H, 5905H
Storage Temperature Range
Positive Supply Voltage (+Vs)
Negative Supply Voltage (-Vs)
Analog and Reference Inputs
Encode Input
Hysteresis Control
Digital Inputs
Analog -Digital Ground Voltage Differential
-55°C to + 125°C
O°C to +70'C
-40'C to +85'C
-55°C to + 125°C
-65°C to +150°C
-0.3 to +6.0 Volts
-6.0 to +0.3 Volts
-3.5 to +2.5 Volts
-Vs to +0.0 Volts
to +3.0 Volts
-3.5 to +0.0 Volts
±0.5 Volts
o
PART NUMBER
MN590XH
I
Select PIN MN5904 or MN5905 for
desired output logic coding.
Add no suffix for O'C to +70'C (case)
operating temperature.
Add "E" suffix for -40'C to +85'C (case)
operating temperature.
Add "H" suffix for -55'C to +125'C (case)
operating temperature.
ELECTRICAL SPECIFICATIONS (T.=+25°C; +Vs=+5.0V; -Vs=-5.2V; ±VREF=±1V; fENOOOE -75MHz unless otherwise indicated.)
PARAMETER
MIN.
Resolution
TYP.
MAX.
UNITS
B~s
6
ANALOG INPUTS
Input Range
Input Span for '/2LSB DNL (Note 1)
Inpul Span for 'I.LSB DNL
Inpul Current at VAlN=+ VREF
Input Current at V AlN=-VREF
Input Capacitance
+VREF
-VREF
1.2
2.4
0.6
1.2
150
-500
500
500
25
Volts
Volts
Volts
flA
nA
pF
REFERENCE INPUTS
Positive Reference Voltage (Note 2)
Negative Reference Voltage (Note 2)
Reference Ladder Resistance
Total Reference Span (Note 2)
-2.5
-3.0
96
128
+2.0
+1.5
195
5.0
Volts
Volts
Ohms
Volts
±D.5
±1.0
± 0.5
± 1.0
LSB
LSB
LSB
LSB
TRANSFER CHARACTERISTICS
Differential Linearity at +25°C
over Temperature
Integral Linearity at +25°C
over Temperature
±0.25
±0.25
No MiSSing Codes
Guaranteed Over Temperature
+Full Scale Input Error at +25°C
Over Temperature
-Full Scale Input Error at +25°C
Over Temperature
±0.3
±0.25
±7/8
±1.5
±7/8
±1.5
LSB
LSB
LSB
LSB
ENCODE INPUT
"I"
"0"
"I"
"0"
Level
Level
Input Current
Input Current
Encode Pulse Width High (tPWH )
Encode Pulse Width Low (l pwL )
-1.1
-2.0
-0.9
-1.7
6
6
-0.6
-1.6
50
50
6.6
6.6
Volts
Volts
flA
flA
nsec
nsec
DATA OUTPUTS (Note 3)
"1" Output Level
"0" Oulput Level
6-164
-I.t
-2.0
-0.9
-1.7
-0.7
-1.5
Volts
Volts
ELECTRICAL SPECIFICATIONS (CONTINUED)
DYNAMIC PERFORMANCE
MIN.
TYP.
MAX.
UNITS
Aperture Delay (t D)
Aperture Uncertainty (Jitter)
2
25
nsec
psec
Output Propagation Delay (tpD ; Note 4)
Output Hold Time (tOH ; Note 5)
9
t1
nsec
nsec
Maximum Encode Rate
75
Input Slew Rate
Input ·3dB Bandwidth (Note 6)
100
MHz
500
140
V/l'sec
MHz
'12
LSB
AC LINEARITY (Note 7)
Dynamic Linearity at f. ,N =15MHz
In· Band Harmonics
DC to 1MHz
1 to 5MHz
5 to 8MHz
48
48
46
dBc
dBc
dBc
Signal·to·Noise Ratio (Note 8)
1OMHz Analog Input
35M Hz Analog Input
37
36
dB
dB
Total Harmonic Distortion (THD)
1OMHz Analog Input
35MHz Analog Input
·44
·34
dB
dB
POWER SUPPLIES
Positive Supply
Negative Supply
Positive Supply Current
Negative Supply Current
+4.5
-5.7
+5.0
-5.2
50
55
+5.5
-4.7
80
80
Volts
Volts
mA
mA
Notes:
1. Span, also called full-scale range (FSR), is the maximum negativeto-positive excursion of the input voltage. DNL is differential
nonlinearity, the deviation from the theoretical step size for any
code.
2. Total.Reference Span is +V AEF -(-V AEF)' +V AEF must always be more
positive than -V AEF
3. Measured with outputs terminated with 100n resistors to -2.0V.
5. Measured from trailing edge of ENCODE to data out on Bit6
(MSB).
6. Input frequency at a 75MHz sampling rate at which the reconstructed output amplitude drops 3dB with respect to the input
signal.
7. Measured with 50MHz sampling rate.
8. RMS signal to RMS noise.
4. Measured from leading edge of ENCODE to data out on Bit6
(MSB).
6·165
ENCODE (6)
HYSTERESIS
VH(S)
V"IN(3)
+VR• F (2)
0-------.
o---""""'Ir---H
o--.....--1'---H
(15) OVERFLOW
(14) D6 (MSB)
(13) 05
>-.f---I
-V.(S) 0 -
LATCH
STAGE
1ST
ENCDR
(AND)
2ND
ENCDR
(OR)
OUTPU
STAGE
(12) D4
(11) 03
(10) 02
-VR• F (4)
(9) 01
o---'---H
GND(1,16)~
COMPARATORS
Figure 1. Block Diagram
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - In accordance with
industry convention, both the MN5904 and MN5905
are deSigned to produce their first logic transition
(000000 to 000001) when the analog input voltage
surpasses -V REF+lI2LSB. This convention centers the
codes such that an ideal D/A converter with an outputvoltage range matching the input-voltage range of the
MN5904/5905, connected to the input of the MN59041
5905, will produce unambiguous, identical codes in the
MN5904/5905 (see Digital Output Coding). With this
coding scheme, the last transition (111110 to 111111)
occurs when the analog-input voltage surpasses
+V REF-11I2LSB.
The MN5904 and MN5905 differ in their output coding
when the analog-input voltage surpasses +VREF _1112 LSB.
For both models, the overflow output changes from "0"
to "1" at this point. In the MN5905, the output code
remains 111111; in the MN5904, however, the code
changes from 111111 to 000000. Because of its
nonreturn-to-zero coding, the MN5905 is the AID
converter of choice for stand-alone 6-bit applications.
The return-to-zero coding, of the MN5904 makes the
device suitable for cascading with the MN5905 to
obtain 7 or 8 bits of resolution. The open-emitter output
architecture of both devices facilitates the cascade
connection (Figure 3).
HYSTERESIS CONTROL FUNCTION - A HystereSiS
Control Voltage (VH) pin in the MN5904/5905 provides
an adjustment of the input comparators' sensitivity. An
input voltage of OV to +3V applied to VH causes the
6-166
comparator hysteresis to vary from approximately 15mV
to 50mV. Increasing the comparator hystereSis reduces
the error rate (number of false full-scale output codes in
a given period). It may be desirable to consider the use
of the hysteresis control function for error-sensitive
applications, especially those employing a high (greater
than 50MHz) sampling rate. The VH input, when used,
should be decoupled to ground through a 0.111F
capacitor.
LAYOUT SUGGESTIONS - It is strongly recommended
that a substantial ground plane be placed under and
around the MN5904/5905. It is further recommended
that the two ground pins be connected together as
closely as possible to the MN5904/5905, and also
connected to the ground plane. The power supplies and
reference inputs should be decoupled to ground directly
at the MN5904/5905 with 0.111F capacitors in order to
reduce the effects of system noise on converter
accuracy.
Chip capacitors produce the best results because they
do not exhibit the lead inductance inherent in discrete
components. The reference inputs should be driven
from a source having low output impedance. The low
impedance will help to minimize errors caused by noise
on the reference line and will also reduce errors that
could otherwise arise from the reference's source
impedance. Figure 4 shows circuitry that has proven to
be a simple and effective means of driving the reference
inputs.
PIN DESIGNATIONS
1
Digital Ground 1
16
Digital Ground 2
2
+VREF
15
Overflow Output
3
VAIN
14
06 (MSB)
4
-VREF
13
05
5
Hysteresis Control
12
04
6
Encode
11
03
7
8
+Vs
-Vs
10
02
9
•
16
8
9
Pin 1
01 (LSB)
DIGITAL OUTPUT CODING
Analog Input
Overflow
MSB
LSB
Analog Input
Overflow
MSB
LSB
0
0
0 0 0
0
0
+V RE ,ILSB
0
1
1
VRE,+'/,LSB
-'/,LSB
0
0
0
0
+V RE ,'I2LSB (MN5905) 0
1
1 1
1 1
1
0
0
0 0 0 0
0
0
+ VRE,'I2LSB (MN5904) 0
1
+ VRE,(MN5905)
1
+ VRE ,(MN5904)
0
0 0 0 0
0
-VREF
OV
0
0
1
1
0
+'/,LSB
+VRE,-I'/,LSB
0
1
1
NOTE: The symbol
0 0
0 0 0
0
0
0
0
0
1 1 1
1
1
0
0 0
1
1 1 1
0
0
1
1
0
oIndicates a bit transition, in which the indicated bit is alternating between "0" and "I".
->-1
ANALOG
INPUT
0 0
1 1
:.-t.
N
t" - Aperture Delay
tpD - Output Propagation Delay
tOH - Minimum Output Hold Time
I
tPWH - Minimum Encode Pulse Width High
tPWL - Minimum Encode Pulse Width Low
ENCODE
x
N
-.11.,.1 ......
I
I
I
- Output data not valid
- Data from sample N
F\x E\
OUTPUT
Figure 2. Timing Diagram
~
2
VAIN
ENCODE
IS
3
DOV
14
13 t - - MN590512 t - 11 r-10 f 9
6 4
",FSRo--f
2
15
14
13
MN5904 12
11
10
'--- 6
4 9
'--- 3
Figure 3.
07
06
05
04
03
02
01
Cascaded 7-Bit Operation
6-1b7
'"m
·2V
+SV
2.Sk!
~~
!n
~D
~D
Iz
~m
-g
~-4
01
:~
~
o
i{!.
~D
~D
*~
°Ul
Figure 4. Reference Drive
MN5906
_
MICRO NETWORKS
6-Bit, 50MHz CMOS
FLASH AID CONVERTER
DESCRIPTION
FEATURES
• 6-Bit Resolution
Plus Overflow Bit
• 50MHz Typical Conversion Rate
• Single +5V Operation
• Low Input Capacitance
• Low Power (190mW, typ.)
The MN5906 is a high-speed, low-power, monolithic CMOS
Flash AID converter. The MN5906 converts analog input signals
into six-bit digital words at an impressive 50MHz (typ) rate. The
device's.pipelined flash architecture contains 64 auto-zeroed
comparators, reference resistor ladder, decode logic and output
3-state latches. An intermediate tap is provided for user
adjustments of integral linearity.
The converter provides six TIL-compatible output bits plus an
overflow flag signal. Overflow can be used in conjunction with
3-state output controls to stack multiple MN5906's for higher
resolution applications.
The MN5906 is available for commercial/industrial applications
in both ceramic side-brazed and plastic DIP packages. The
MN5906 H/B is also available with Environmental Stress
Screening for application in military/aerospace systems.
• Small 18-Pin Ceramic
or Plastic DIP
• 3-State Outputs
• Optional Environmental Stress
Screening
Model
Number
MN5906PD
MN5906CD
MN5906PDE
MN5906CDE
MN5906CDH
MN5906CDH/B
Package
Temperature
Range
Mil
Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
O°C to +70°C
O°C to +70°C
-25°C to +85°C
-25°C to +85°C
-55°C to + 125°C
-5SoC to + 12SoC
No
No
No
No
No
Yes
I
APPLICATIONS
Video
RADAR Systems
Pulse Measurement Systems
Subranging AID Converters
Synchronous Demodulation
Infrared Imaging
Communications
This data sheet contains preliminary information regarding the MNS906. Please contact
the factory for up-to-date performance and product information.
L
April 1992
Copyright 1992
[1JJ
-
MICRO NETWORKS
Micro Networks
All rights reserved
324 Clark St .. Worcester, MA 01606 (508) 852-5400
----------------------------~
6-169
MN5906 6-Bit, 50MHz CMOS FLASH AID CONVERTER
ORDERING INFORMATION
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range:
Specified Temperature Range:
MN5906PD, CD
MN5906PDE, CDE
MN5906CDH, CDH/B
Storage Temperature Range
MN5906PD, POE
MN5906CDE, CDH, CDH/B
Power Supply Voltages (+Voo, Pins 5, 6)
Digital Inputs (Pins 3, 4, 18)
Analog Input (Pin 8)
-55°C to + 125°C
O°C to +70°C
-25°C to +85°C
-55°C to + 125°C
-65°C to + 100°C
-65°C to + 150°C
-0.5 to +7.0 Volts
-0.5 to +Voo +0.5 Volts
-0.5 to +Voo +0.5 Volts
PART NUMBER - - - - - - - - - MN5906 CD H/B
Select suffix "PO" for PlastiC. DIP
~
or "CD" for ceramic D I P . - - - - .
Standard "PD" and "CD" are
specified for O°C to +70 o C operation.
Add "E" suffix to models for
specified -25°C to +85°C operation.
Add "H" suffix to "CD" models for
specified -55°C to + 125°C operation.
Add "/B" suffix to "CDH" models for
Environmental Stress Screening.
-----------1
SPECIFICATIONS (TA = +25°C, Supply Voltage +Voo = +5V, VAEF = +2.75V, fClK =35 MHz unless otherwise indicated)
ANALOG INPUT
MIN.
TYP.
MAX.
o to VREF
Input Voltage Range
Input Capacitance
Full Power Bandwidth
UNITS
12
100
Volts
pF
MHz
+2.75
90
0.3
Volts
Il
Il/oC
REFERENCE INPUTS
Reference Voltage (+VREF. )
Reference Ladder Resistance
Reference Ladder Tempco
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "0"
+1.5
Volts
Volts
+5
-5
pA
pA
+0.4
Volts
Volts
±1
± 3/4
LSB
LSB
20
MHz
nsec
nsec
+3.5
Logic Loading: Logic "1" (VIH =+4.5V)
Logic "0" (Vll = +0.5V)
+1
-1
DIGITAL OUTPUTS
Logic Levels: Logic "1" (loH = 4mA)
Logic "0" (Iol = 4mA)
+4.5
TRANSFER CHARACTERISTICS
±3f4
±v.
Integral Linearity Error (Notes 1, 2)
Differential Linearity Error (Notes 1, 3)
~IC PERFORMANCE
Conversion Rate
Aperture Delay
Output Propagation Delay
35
10
50
5
14
Signal-to·(Noise and Distortion) Ratio (SINAD)
fAIN=1MHz
fAIN=10MHz
34
33
dB
dB
Spurious Free Dynamic Range (SFDR)
fAIN=1MHz
fAIN =10MHz
43
37
dB
dB
POWER SUPPLY
Power Supply Voltage (+Voo Supply)
Power Supply Current (+Voo Supply)
+4.75
SPECIFICATION NOTES,
1.
2.
3.
Measured while operating at specified conversion rate
Integral linearity Error is speclfred usmg transfer function endpoints often limes referred to as endpoint IIneanty.
Differential Linearity Error measurements are based on code transitions.
6-170
+5
+38
+5.25
Volts
mA
--
BLOCK DIAGRAM
0-----,
+VREF(Pm 2)
(F",'6)Overfiow
Analog Input (Pm 8)
(Pin 15)MSB
(Pm 14)8112
(Pin 13)8113
(Pm 12)8114
(Pin 1\)8115
(PIO 10) LSB
(Pm 3) CS2
(Pm 4) CSI
L _ _ _ _ _ _ _ _ _ _......_ _--
!:.
I
89 (LSB)
88
87
86
-1-
81 (MSB)
6-181
PIN DESCRIPITONS
PIN
SYMBOL
FUNCTIONAL DESCRIPTION
PIN
SYMBOL
FUNCTIONAL DESCRIPTION
12
CS2
3-state control for output bits B1 to B8 and
the Overflow output. When CS2 is ~'
output bits B1 to B8 are enabled if
1 is low.
CS2 has independent control of the Overflow
output. If CS2 is low, B1 to B8 and Overflow
are in the high-impedance state.
Voltage potential at the bottom of the resistor
ladder that sets the lower limit of the AID converter's range. Also sets the offset code for 0
to 1 transition.'
13
OF
When high, Overflow indicates that the input
voltage exceeds the top reference tap point,
nominally VREF+ - '12 LSB. Outputs B1 to B8
assume all "1's" when Overflow is high.
GND
Ground potential for the analog and digital
circuitry. Also the Silicon substrate potential.
14
B1
5
VIN
The analog signal input to the lower half of
the AID converter.
(MSB) Most-significant bit of the digitized 8-bit
output. Has a weight of FSR/2 where FSR
(full-scale range) is VREF+ - VREF _.
15
B2
6
Midpoint of the resistor ladder, at the boundary between codes 128 and 129. Normally
decoupled through a capacitor to ground,
but may be used to adjust linearity or to
impart a non-linear transfer function.
2nd most-significant bit of the digitized 8-bit
output. Has a weight of FSR/4.
RMID
16
B3
3rd most-significant bit of the digitized 8-bit
output. Has a weight of FSR/8.
17
B4
4th most-significant bit of the digitized 8-bit
output. Has a weight of FSR/16.
18
R3/4
3rd quarter point of the AID converter's
resisitor ladder, at the boundary between
codes 64 and 65. Normally decoupled
through a capacitor to ground, but can be
used to adjust integral linearity or to impart
a non-linear transfer function.
19
Voo
Supplies power to analog and digital sections
of chip. Nominal level +5V.
20
R1/4
1st quarter point of the AID converter's
resistor ladder, at the boundary between
codes 64 and 65. Normally decoupled through
a capacitor to ground, but can be
used to adjust integrallinearily or to impart
a non-linear transfer function.
21
B5
5th most-significant bit of the digitized 8-bit
output. Has a weight of FSR/32.
22
B6
6th most-significant bit of the digitized 8-bit
output. Has a weight of FSR/64.
23
B7
7th most-significant bit of the digitized 8-bit
output. Has a weight of FSRI128.
24
B8
(LSB) Least-significant bit of the digitized 8-bit
output. Has a weight of FSR/256.
1
V DD
Supplies power to analog and digital sections
of chip. Nominal level +5V.
2
ClK
Externally supplied clock signal; used internally to generate three distinct phases for the
comparator sampling sequence and comparator latches.
3
VREF-
4
7
VIN
The analog signal input to the upper half of
the AID converter.
8
GND
Ground potential for the analog and digital
circuitry. Also the silicon substrate potential.
9
VREF+
Voltage potential to the top of the resistor
ladder that sets the upper limit of the AID
converter's range. Can be used to make gain
adjustments. Nominally +3.0V.
10
VDD
Supplies power to analog and digital sections
of chip. Nominal level +5V.
11
CS1
3-state control for output bits B1 to B8.
When CS2 is high, Q!!!put bits are enabled
(When CS1 is low). CS1 is a don't care (X)
when CS2 is low.
6-182
TIMING DIAGRAM
Analog Input
Clock
Output _ _ _ _ _ _ _--J
Data
PIN DESIGNATIONS
24
1 +Voo Supply
2 Clock
3 VREF 4 Ground
5 Analog Input
6 R M10
7 Analog Input
8 Ground
I"
13
9
10
11
12
VREF+
+Voo
CS1
CS2
24
23
22
21
Bit 8 (LSB)
Bit7
Bit6
Bit5
20
19
18
17
16
15
14
13
R'I4
I
+Voo
R3J4
Bit4
Bit 3
Bit2
Bit 1 (MSB)
Overflow
6-183
QJ] MICRD NETWDRKS
~
6-184
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
OJl
_
MN5909
6-Bit, 100MHz CMOS
FLASH AID CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• 6-Bit Resolution
Plus Overflow Bit
• 100MHz Typical Conversion Rate
• Single +5V Operation
The converter provides six TIL-compatible output bits plus an
overflow flag signal. Overflow can be used in conjunction with
3-state output controls to stack multiple MN5909's for higher
resolution applications.
• Low Input Capacitance
• Low Power (200mW, Typical)
• Externally-Strobed, Auto-Zeroed
Comparators
• Small 20-Pin Ceramic
or Plastic DIP
• 3-State Outputs
• Optional Environmental Stress
Screening
The MN5909 is a high-speed, low-power, monolithic CMOS
Flash AID converter. The MN5909 converts analog input signals
into six-bit digital words at an impressive 100M Hz (typ) rate. The
device's transparent flash architecture contains 64 externallystrobed, auto-zeroed comparators, reference resistor ladder,
decode logic and output 3-state buffers. An intermediate tap is
provided for user adjustments of integral linearity.
The MN5909 is available for commercial/industrial applications
in both ceramic side-brazed and plastic DIP packages. The
MN5909H/B is also available with Environmental Stress Screening for application in military/aerospace systems.
Model
MN5909PD
MN5909CD
MN5909PDE
MN5909CDE
MN5909CDH
MN5909CDH/B
Package
Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Temp. Range
O°Cto +70°C
O°Cto +70°C
-25°C to +85°C
-25°C to +85°C
-55°C to +125°C
-55°C to +125°C
Mil
No
No
No
No
No
Yes
APPLICATIONS
Video
RADAR Systems
Pulse Measurement Systems
Infrared Imaging
Communications
High-Speed Digitizers
EW and ECM Systems
This data sheet contains preliminary information regarding the MN5909. Please contact
the factory for up-to-date performance and product information.
[1JJ
_
MICRO NETWORKS
May 1992
CopyrightrcJ1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (506) 652-5400
6-185
MN5909 6-Bit, 100MHz CMOS FLASH AID CONVERTER
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range:
Specified Temperature Range:
MN5909PD, CD
MN5909PDE, CDE
MN5909CDH, CDH/B
Storage Temperature Range
MN5909PD, PDE
MN5906CD, CDE, CDH, CDH/B
+VDD Supply (Pins 5, 6, 7)
Digital Inputs (Pins 3, 4, 19, 20)
Analog Input (Pin 9)
ORDERING INFORMATION
-55°C to + 125°C
O°C to +70°C
-25°C to +85°C
-55°C to + 125°C
-65°C to + 100°C
-65°C to + 150°C
-0.5 to +70 Volts
-0.5 to +VDD +0.5 Volts
-0.5 to +VDD +0.5 Volts
PART NUMBER - - - - - - - - - MN5909 CD H/B
Select suffix "PD" for plastic DIP
or "CD" for ceramic D I P . - - - - - - - - - - - - - - ' ·
Standard "PD" and "CD" are
specified for O°C to +70°C operation.
Add "E" suffix to either "PD" or "CD" models for
specified -25°C to +85°C operation.---------i
Add "H" suffix to "CD" models for
specified -55°C to + 125°C operation. _ _ _ _ _ _ _ _.J
Add "/B" suffix to "CDH" models for
Environmental Stress Screening. - - - - - - - - - - - - '
I
SPECIFICATIONS (TA =+25OC, +VOD = +5V, VREF+ =+2.7SV, VREF _ =O.OV, ICLK =100 MHz unless otherwise indicated)
ANALOG INPUT
MIN.
TYP.
o to
Input Voltage Range
Input Capacitance
Full Power Bandwidth
MAX.
UNITS
Volts
pF
MHz
+VREF
12
100
REFERENCE INPUTS
Volts
Il
WOC
+2.75
90
0.3
Reference Voltage (VREF+. )
Reference ladder Resistance
Reference ladder Tempeo
DIGITAL INPUTS
logic levels: Logic "1"
Logic "0"
+1.5
Volts
Volts
+5
-5
"A
"A
+0.4
Volts
Volts
+3.5
Logic Currents: Logic "1"
logic "0"
DIGITAL OUTPUTS
Logic Levels: Logic "1"
logic "0"
+4.5
TRANSFER CHARACTERISTICS
± 3/4
±V4
Integral Linearity Error
Differential Linearity Error
No Missing Codes
±3A
±1
LSB
LSB
20
MHz
nsec
nsec
Guaranteed
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Output Propagation Delay
10
100
5
14
ACLINERITY
Signal-to-(Noise and Distortion)
fAIN=IMHz
fAIN=10MHz
Spurious Free Dynamic Range:
fAIN=IMHz
fAIN=10MHz
34
33
dB
dB
43
dB
dB
37
POWER SUPPLY
Power Supply (+VDD Supply)
Power Supply Drain (+ VDD Supply)
SPECIFICATION NOTES:
1.
Measured while operating at specified conversion rate with an auto-zero pulse repitition rate of 40kHz.
2.
Integral Lineanty Error is specified using transfer function endpoints.
3.
Differential Linearity Error measurements are based on code transitions.
6-186
+4.75
+5
+40
+5.25
Volts
mA
PIN DESIGNATIONS
20
~o
11
20 Conversion Clock
19 Auto-zero Strobe
18 Ground
17 Overflow
16 Bit 1 (MSB)
15 Bit 2
14 Bit 3
13 Bit 4
12 Bit 5
11 Bit 6 (LSB)
V REF-
2
3
4
5
6
7
8
9
10
VREF+
3-State Control (CS2)
3-State Control (CS1)
+VDD Supply
+VDD Supply
+VDD Supply
Ground
Analog Input
RMID
PACKAGE OUTLINE
~
.1
ts
n'-_____
StrobeS
Clock
Strobe
J
tpw
~
-=1'-________________
Clock
TIMING NOTES:
1. tpw must be high for one full clock cycle.
Strobe may be asynchronous with Clock.
2. ts = Strobe repetition rate=40kHz.
3. Output data is indeterminate when strobe = "1 ".
Output data returns valid upon falling
edge of clock after strobe returns to "0".
g~~ut~~_ln_v_a_lid__J)(~________~_a_lid_ _ _ _ ___
PIN DESCRIPTIONS
INCHES
H
,,...-'----.. ...L
I
Ir8>==~r-
MILLIMETERS
DIM.
MIN.
MAX.
MIN.
MAX.
A
1.010
0.990
25.65
25.15
B
0.300
0.320
162
8.13
C
0.285
0.305
7.24
U5
D
0.295
0.305
7:49
U5
E
0.125
0.200
3.18
5.08
F
-
0.123
G
0.048
0.052
H
0.900 BASIC
I
0.100 BASIC
2.54 BASIC
J
0.D16
0.020
0.41
0.51
K
0.005
0.D15
0.13
0.38
1.22
3.12
1.32
22.86 BASIC
Package shown is for
MN5909CO, COE, COH and
COH/B. Please contact factory
for information regarding
dimensions and availability of
"PO" and "POE" models.
6-187
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - The MN5909 6-Bit, 100MHz
CMOS Flash AID converter, operates in a transparent fashion with
an externally supplied asynchronous, auto-zero pluse. Typical
CMOS Flash AID converters auto-zero the sampling comparators
during each clock cycle. The MN5909's unique architecture utilizes
an externally-applied asynchronous pulse to auto-zero the sampling comparators every 40,000 conversions (typically).
The auto-zero pulse must be high during a low-Io-high transition of
the applied conversion clock and must remain high for a minimum
of one clock cycle. It is recommended that a 40kHz repetition rate
of the auto-zero pulse be utilized.
LAYOUT AND GROUNDING CONSIDERATIONS - The MN5909
and other high-speed devices require that careful consideration be
given to high-speed and low-noise design techniques. The pinout
of the MN5909 has been carefully chosen to maintain as much
separation of digital and analog signals as possible. The use of
ground and power planes and signal shielding is highly recommended. It is recommended that bypass capacitors of 0.01 and 0.001pF
should used and located as close to the device as possible.
Output data present during the auto-zero phase should be considered invalid.
It is also recommended that Circuits interfacing with the MN5909
(such as data latches, etc.) be located within 2 inches of the device
to avoid transmission line effects (rise and fall times of the MN5909
output drivers are 2nsec or less implying frequency components
in the hundreds of MHz).
PIN DESCRIPTIONS
DIGITAL OUTPUT CODING
NAME
SYMBOL
1,2
Reference Inputs
-VREF,
+VREF
3
3-State Control
(Overflow Bit)
CS2
PIN
4
3-State Control
(Data Bits)
CSl
5,6,7
Power Supply
+Voo
8
Ground
GND
9
Analog Input
AiN
10
Reference
Resistor Midpoint
Data Output Bits
RMIO
B6-Bl
Overflow Bit
OF
18
Ground
GND
19
Strobe
STB
20
Clock
CLK
11,12,13
14,15,16
17
DESCRIPTION
Bottom and top of the
reference resistor string.
-VREF normally tied to GND,
+VREF normally tied to +2.75
Volts.
Overflow bit valid when
CS2 = Logic "1". Output bits
and overflow bit in
high-impedance state when
CS2= Logic "0".
See Truth Table.
Data bits valid when
= Logic "0". Data bits
in hig~edanCe state
when 1 = Logic "1".
CSi is a "don't care" (X)
when CS2 is a Logic "0".
See Truth Table.
Connected to +5V Supply for
normal operation.
Connected to System Analog
Grou nd plane.
Connect analog input signal
to be digitized. Nominally CN
to +VREF.
Midpoint tap to resistor
ladder.
Digital Output Bits.
esr
ANALOG INPUT
_
0
0
0
1 000
¢ ¢ ¢ ¢
0 1 1 1
o ~
¢ f{J
1 ~
0
0
0 0 0 0
0 0 0 0
o f{J
o 0
+'I2VREF + 'I2LSB
+'I2VREF-'I2LSB
+'/2VREF _3/2 LSB
+ 'I2LSB
0
MSB
1 1
1 1
1 1
1 1
1
1
1
1
Analog inputs indicated are the theoretical values for the transitions of codes
indicated above. With the converter continuously converting, the output bit
indicated as _ will change from Logic' '0" to Logic' '1" or vise versa as the
input voltage passes through the indicated level.
TRUTH TABLE
CS1
0
1
X
CS2
1
1
0
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
6-188
LSB
1 1
1 1
1 1
1 ~
OF
1
~
0
0
Set to a Logic "1" when
anal09 input exceeds +VREF
-'I2LSB.
Connected to System Analog
Ground plane.
Externally-applied auto-zero
strobe pulse.
Clock Input.
l1JJ
1
1
1
1
+VREF
+VREF -'I2LSB
+VREF-1LSB
+VREF _3/2 LSB
81
-
Valid
High-Z
High-Z
86
OF
Valid
Valid
High-Z
Digital-to-Analog Converters
Micro Networks offers a complete line of D/A converters ranging in
resolution from 8 to 16-bits. Included are many 8-bit (MN3000 Series,
MN3020), 12-Bit (MN3850, MN3860, DACHK, DAC85, DAC87, DAC88)
and 16-bit (MN3290-1 Series, MN3290-V Series, DAC71) devices that
have become multisourced industry standards. We also have a complete line of high-speed D/f!\s with internal data input latches (MN3020,
MN3040, MN3860, DAC88) to facilitate microprocessor interfacing.
MN3290-1 Series
Cu rrent -Output
Extended-Temperature
Range
16-Bit D/A Converters
MN3290-V Series
Voltage-Output
Extended-Temperature
Range
16-Bit D/A Converters
FEATURES
FEATURES
• 16-Bit Resolution
• 16-Bit Resolution
• Fully Specified
-55°C to +125°C Operation
• Fully Specified
-55°C to + 125°C Operation
• ± 0.006% FSR Integral
linearity
•
± 0.006% FSR Integral
linearity
• 14-Bit Monotonic
Guaranteed Over Temperature
• 14-Bit Monotonic
Guaranteed Over Temperature
• Internal Reference
• Internal Reference
and Output Op Amp
• Three Models:
MN3290-V, 0 to +10V
MN3291-V, ± 5V
MN3292-V, ± 10V
• Three Models:
MN3290-1, 0 to -2mA, RF =5k
MN3291-1, ± 1mA, RF =5k
MN3292-1, ± 1mA, RF=10k
• Fast Output Settling:
1J1Sec Max to ±0.003%FSR
Function Compatible
• Fast Output Settling:
Full Scale Step to
± 0.003%FSR, 8~sec Max
• DESC SMD 5962-89531
• DAC71/72 Pin-for-Pin and
• DAC71/72 Pin-for-Pin and
• MIL-STD-883 Screening
Optional. MIL-STD-1772 Qualified
Facility
7-2
The MN3290-1 and MN3290-V Series of extended temperature range,
16-Bit D/A converters are targeted for application in the most demanding military/aerospace and industrial systems. The MN3290 devices
are exactly pin-for-pin and function compatable with older, industrystandard DAC71/72 devices. A total of 36 different models
(I-Out, V-Out, OOC to +70°C, and -55°C to +125°C) makes the MN3290
Series suitable for almost any high-resolution, extended-temperature
range application.
Function Compatible
• DESC SMD 5962-89531
• MIL-STD-883 Screening
Optional. MIL-STD-1772 Qualified
Facility
Digital-to-Analog Converters
Resolution
16-Bits
12-8ils
Model
Number
Maximum Internal Ref. Specified
Maximum Monotonic
Selling Time and Output Temperature linearity ErOver
Range
(DC)
Op Amp
ror (%FSR) Temperature
",sec) (1)
DAC71-V
DAC71-1
10
1
Yes (2)
MN3290-V
MN3290-1
Series
8
1
Yes (2)
OAC80-V
DAC80-1
4
0.3 (Typ)
Yes (2)
DAC8S-V
DAC8S-1
4
0.3 (Typ)
Yes (2)
DAC87
4
Yes
oto
oto
+70
+70
- 55 to +125
oto
oto
+70
+70
-25 to +85
-25 to +85
- 55 to +125
Power
(mW)
DIP
Package
Hi-Rei
Oplion
OESC SMO
(5962-)
Page No.
±OO03
(Note 3)
525
24 Pin
No
NA
7-9
±0003
(Note 3)
525
435
24 Pill
Yes
8953103
8953104
8953102
7-51
±0012
Yes
345
24 Pill
No
NA
7-13
±0012
Yes
345
24 Pill
No
NA
717
±0012
Yes
345
24 Pin
Yes
8300301
7-21
--
----
oto
DACHK
4
Yes
+70
- 55 to +125
±0012
Yes
975
24 Pin
Yes
(Note 4)
7-5
±0012
Yes
345
24 Pin
Yes
(Note 4)
7-61
±0012
Yes
495
24 Pin
Yes
(Note 4)
7-25
±0.012
Yes
495
24 Pin
Yes
9057001
7-65
±0012
Yes
195
24 Pin
Yes
(Note 4)
7-57
±0.012
Yes
195
24 Pin
Yes
(Note 4)
7-59
7-29
oto
MN3850
4
Yes
+70
- 55 to +125
oto
DAC88
7
Yes
+70
- 55 to +125
oto
MN3860
7
Yes
+70
- 55 to +125
oto
MN3348
8
Yes
+70
- 55 to + 125
oto
MN3349
10
MN370
MN371
60
35
Yes
oto
Yes
+70
- 55 to +125
±0012
Yes
90
18 Pin
Yes
8981401
8981402
oto
10-Bits
MN3040
8-Bits
+70
- 55 to +125
10
Yes
+70
- 55 to +125
±0.05
Yes
450
18 Pin
Yes
(Note 4)
7-47
±005
Yes
450
16 Pin
Yes
(Note 4)
7-35
±02
Yes
495
16 Pin
Yes
8768801
8768802
7-39
±0.2
Yes
505
18 Pin
Yes
8971801
7-43
±02
Yes
420
16 Pin
Yes
(Note 4)
7-41
±0.2
Yes
510
14 Pin
Yes
(Note 4)
7-31
oto
MN3003
Series
30
Yes
+70
- 55 to +125
MN3008
MN3009
1
Yes
oto +70
- 55 to +125
oto
MN3020
3
Yes
+70
- 55 to +125
oto
MN3014
MN3000
Series
NOTES:
2.5
Yes
+70
- 55 to +125
oto
30
Ves
+70
- 55 to +125
1. Specified for a full scale output step settling to ± '12 LSB.
2. Current-output models do not have internal output op amps.
3. Monotonicity for 14 bits guaranteed over temperature.
4. Contact the factory for information regarding DESC SMD's for these device types.
",. Indicates New Product.
7-3
[1=:!J MICRO NETWORKS
~
74
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
DACHK
~
12-Bit
D/A CONVERTER
MICRO NETWORKS
with INPUT REGISTER
DESCRIPTION
FEATURES
DACHK is a complete, VOltage-output, 12-bit D/A converter that
contains a low-drift reference and a high-speed input register to
facilitate microprocessor interfacing. The register has a
minimum setup time of 50nsec; a hold time of Onsec; and
pulses as narrow as 60nsec can be used to latch new data. Output settling time for a 20V step settling to ± 112LSB is 4JLsec.
• Complete With Internal:
Input Register
Output Op Amp
Low-Drift Reference
• ±1/2 LSB Max
Linearity Error
• Monotonicity Guaranteed
Over Temperature
• 50nsec Data Setup Time
• 41tsec Settling Time
• 5 Output Ranges
2 Coding Options
• Multisourced
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
DACHK is packaged in a standard, hermetically-sealed, 24-pin,
ceramic dual-in-line and offers 5 user-selectable output ranges
(0 to +5V, 0 to +10V, ±2.5V, ±5Vand ±10V) and 2 input
coding options (straight binary or two's complement). Units
require ± 15V and +5V supplies and consume 975mW of power.
DACHK is functionally laser trimmed for linearity, gain and offset, eliminating the need for external trimming potentiometers.
Units are available for three operating temperature ranges (O°C
to +70°C, -25°C to +85°C and -55°C to + 125°C), and each
unit guarantees 12-bit monotonicity over its entire range. For
military/aerospace or harsh environment commercial/industrial
applications, "H/B CH" models are fully screened to MILH-38534 in Micro Networks' MIL-STD-1772 qualified facility.
Model
Number
24 PIN DIP
~Nl
T
1230(31.2~
, 270(32.26)
Ll
DACHK
DACHKE
DACHKH
DACHKH/B
DACHKH/B CH
DACHK·2
DACHK·2E
DACHK·2H
DACHK·2H/B
DACHK·2H/BCH
Coding
Specified
Temp. Range
Straight Binary
Straight Binary
Straight Binary
Straight Binary
Straight Binary
Two's Complement
Two's Complement
Two's Complement
Two's Complement
Two's Complement
DOC to +7DoC
-25°C to +85°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
DOC to +7DoC
-25°C to +85°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
; I fQ&~~~
I--J
0019(048)
0175(4451
020;'(521)
Dimensions in Inches
(millimeters)
~
MICRO NETWORKS
January 1992
Copyright" 1992
Micro Networks
All rights reserved
324 Clark Sl., Worcester, MA 01606 (508) 852·5400
7·5
DACHK 12·Bit D/A CONVERTER with INPUT REGISTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
DACHK, DACHK-2
DACHKE, DACHK-2E
DACHKH, H/B; DACHK-2H, H/B
Storage Temperature Range
Positive Supply (+Vcc, Pin 22)
Negative Supply(-Vcc, Pin 14)
Logic Supply (+Vdd, Pin 13)
Register Enable (Pin 16)
Digital Inputs (Pins 1-12)
ORDERING INFORMATION
-55°C to +125°C
PART NUMSER --------DACHK-2H/BCH
O°C to +70°C
-25°Cto +85°C
- 55°C to + 125°C
-65°C to +150°C
o to + 18 Volts
oto -18 Volts
- 0.5 to + 7 Volts
- 0.5 to + 5.5 Volts
- 0.5 to + 5.5 Volts
Standard Part is specified for O°C to +70°C
operation.
Add "E" suffix for specified -25°C to +85°C
operation.
Add "H" suffix for specified -55°C to +125°C
operation . - - - - - - - - - - - - - - - '
Add "IS" to "H" devices for Environmental
Stress Screening.
Add "CH" to "HIS" devices for 100% screening
according to MIL-H-38534.----_ _ _ _ _-I-I
---------------1
SPECIFICATIONS (TA = + 25°C, ± Vee = ± 15V, + Vdd = + 5V unless otherwise indicated )(Note 1)
DIGITAL INPUTS
MIN_
Logic Levels: Logic "1"
Logic "0"
+2.0
Input Currents: Data Inputs: Logic "1" (V1H = +2.4V)
Logic "0" (V1L = +0.4V)
Register Enable: Logic "1" (V1H = +2.4V)
Logic "0" (V1L = +0.4V)
TYP_
MAX_
UNITS
+0.8
Volts
Volts
p.A
mA
p.A
mA
+20
-0.4
+60
-1.2
Logic Coding (Note 2): DACHK: Unipolar Ranges
Bipolar Ranges
DACHK-2: Bipolar Ranges
Straight Binary
Offset Binary
Two's Complement
ANALOG OUTPUT
Output Voltage Ranges: Unipolar
Bipolar
Output Current
Oto +5,Oto +10
±2.5, ±5, ±10
Volts
Volts
±5
Output Impedance
mA
0.05
11
TRANSFER CHARACTERISTICS (Note 3)
Integral Linearity Error
±%
Differential Linearity Error
±Y2
Temperature Range for Guaranteed Monotonicity:
DACHK, DACHK-2
DACHKE, DACHK-2E
DACHKH, H/B; DACHK-2H, H/B
0
-25
-55
± V2
LSB
LSB
+70
+85
+125
°C
°C
°C
Unipolar Offset Error (Notes 4, 5)
±0.1
%FSR
Bipolar Offset Error (Notes 4, 6)
±0.1
%FSR
Gain Error (Notes 4, 7)
±0.1
%
DRIFT SPECIFICATIONS (Note 8)
Integral Linearity Drift
Unipolar Offset Drift
Bipolar Offset Drift
Gain Drift
±2
±3
±7
±15
±5
±10
±20
ppm of FSR/oC
ppm of FSR/oC
ppm of FSR/oC
ppm/oC
DYNAMIC CHARACTERISTICS
Settling Time to ± V2 LSB: 20V Step
10V Step
1 LSB
Slew Rate
4
3
0.8
p'sec
p'sec
p'sec
±20
V/p.sec
POWER SUPPLIES
Power Supply Range: + 15V Supply
-15V Supply
+5V Supply
Power Supply Rejection: + 15V Supply
-15V Supply
+14.55
-14.55
+4.75
+15
-15
+5
+15.45
-15.45
+5.25
Volts
Volts
Volts
±0.002
±0.002
%FSRI%Supply
%FSR/%Supply
Current Drain: + 15V Supply
-15V Supply
+5V Supply
+20
-35
+30
mA
mA
mA
Power Consumption
975
mW
7-6
SPECIFICATION NOTES:
6. Bipolar offset error is defined as the difference between the actual and
the ideal output voltage when configured in a bipolar output range with a
digital Input of 0000 0000 0000 (1000 0000 0000 for DACH K·2 models).
7. Gain error is defined as the error in the slope of the converter transfer
function. It is expressed as a percentage and is equivalent to the devia·
tion (divided by the ideal value) between the actual and the ideal value for
the full output voltage span from the 111111111111 (011111111111 for
DACHK-2 models) output to the 0000 0000 0000 (1000 0000 0000 for
DACHK-2 models) output.
8. Drift specifications apply over the O"C to + 70"C temperature range for
DACHK and DACHK-2; over the -2S"C to +8S"C temperature range
for DACHKE and DACHK-2E; and over the -SS"C to + 12S"C tempera·
ture range for DACHKH, DACHKH/B and DACHK-2H, DACHK-2H/B.
1. Unless otherwise indicated, listed specifications apply for all DACHK
and DACHK-2 models.
2. DACHK Is available with either binary input coding (DACHK, DACHKE,
DACHKH and DACHKH/B) ortwo'scomplement input coding (DACHK-2,
DACHK-2E, DACHK-2H and DACHK-2H/B). See Ordering Information.
3. FSR stands for full scale range and is equal to the peak·to-peak voltage of
the selected output range. For the ± 10V output range, FSR is 2OV, and 1
LSB Is Ideally equal to 4.BBmV. For the a to + 10Vand ± 5V ranges, FSR is
10V, and 1 LSB is ideally equal to 2.44mV. For the a to + 5V and ± 2.5
r/lnges, FSR is 5V, and 1 LSB is ideally equal to 1.22mV.
4. Initial offset and gain errors are adjustable to zero with user·optional,
external trimming potentiometers.
5. Unipolar offset error is defined as the difference between the actual and
the Ideal output voltage when configured in a unipolar output range with
a digital input of 0000 0000 0000.
BLOCK DIAGRAM
Register
(16)
Enable
(MSB)
Bit1
Bit2
Bit3
Bit4
BitS
Bit6
Bit?
Bit8
Bit9
Bit10
Bit11
Bit12
Ground
+1SVSupply
-1SVSupply
+5VSupply
I
I
Ref.
(1)
(2)
(3)
.0,
t:"
0'"
;;:.t::
cr:
z ;;:
*''""
(4)
(S)
(6)
(7)
(8)
0>
~
~'"
"'-
"oc:
i ~
Co
"'"0
(9)
ii5
'5
oS
..J "
"'U
~
•
(22) 0
(14)
~
-T
SkU ~
0 _ _ _...,
...
.
(24) Ref. Output
(17) Bipolar Offset
(23) Gain Adjust
(18) 10V Range
,y
(19) 20'1 Range
5kU
(20) Summing Junction
~
(12)
0
r
~ ~
(11)
(211
d
Ci5~
0
(10)
1
1
(1S) Analog Output
I
(13)0_--...
.
PIN DESIGNATIONS
•
Pin
24
1
12
13
1
2
3
4
5
6
7
B
9
10
11
12
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Bit5
Bit6
Bit?
BitB
Bit9
Bit 10
Bit 11
Bit 12 (LSB)
24
23
22
21
20
19
18
17
16
15
14
13
Ref. Out ( + 6.2V)
Gain Adjust
+ 15V Supply (+Vee)
Ground
Summing Junction
20V Range
10V Range
Bipolar Offset
Register Enable
Analog Output
-15V Supply (-Vee)
+5V Supply (+Vdd)
7-7
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy from
the DACHK. The unit's Ground (pin 21) must be tied to circuit
analog ground as close to the package as possible, preferably through a large ground plane underneath the package.
GAIN ADJUSTMENT-Connect the gain potentiometers as
shown and apply all "1's" to the digital inputs'" Adjust the
potentiometer until the analog output is equal to the maximum positive voltage for the chosen output range as shown
in the Input Logic Coding table.
Power supplies should be decoupled with tantalum or electrolytic type capacitors located close to the unit. For optimum performance, 1"F capacitors paralleled with 0.01"F
ceramic capacitors should be used.
+15V
2.2MIl
Pln20~
Coupling between analog and digital signals should be minimized to avoid noise pickup. Short jumpers should be used
and when tying the Bipolar Offset (pin 17) to the Summing
Junction (pin 20) for bipolar operation. If external gain and
offset adjustments are to be used, the series resistors should
be located as close to the unit as possible.
REFERENCE OUTPUT-The DACHK contains an internal
+6.2V referenbe, and the units are actively laser trimmed to
operate from this reference. If the internal reference is used
to drive an external load, it should be buffered if the load current will exceed 20"A.
OPTIONAL GAIN AND OFFSET ADJUSTMENTS - The
DACHK will operate as specified without external adjustments. If desired, however, absolute accuracy error can be reduced by following the trimming procedure described below.
Adjustments should be made following warmup, and to avoid
interaction, the offset adjustment must be made before the
gain adjustment. Multiturn potentiometers with TCR's of
100ppml a C or less are recommended to minimize drift with
temperature. Series resistors can be ± 20% carbon composition or better. If these adjustments are not used, pins 20 and
23 should not be grounded.
+15V
f Pin23~1'00kll
l00kll
OFFSET ADJUST
GAIN ADJUST
-15V
i
-15V
• "1" and all "D's" for 2'5 complement
* ·"0" and all "1 'sIt for2's complement
REGISTER ENABLE - When the Register Enable (pin 16) is
high (hold mode) the digital data in the input register will be
latched, and when the Register Enable is low (track mode),
the converter's output will follOW its input. In order to latch
new digital data into the register, the Register Enable must
go low for a minimum of 60nsec and digital input data must
be valid for a minimum of 50nsec prior to Register Enable
going high again. See Timing Diagram.
INPUT REGISTER TIMING DIAGRAM
Register
Enable
Digital
Input
Data
OFFSET ADJUSTMENT-Connect the offset potentiometer
as shown and apply all "O's" to the digital inputs.' Adjust the
potentiometer until the analog output is equal to zero volts
for the unipolar output ranges or negative full scale for bipolar output ranges.
=i
TIMING NOTES:
TMEPW
TSDE
TH
TSDE
THl
,-----------' -_ _ _ _ _ _ _ _ __
I
Minimum Enable Pulse Width IS 6Onsee.
Minimum Setup Time Digital Data to Enable is SOnsee.
Digital Data Hold Time from Register Enable is Onsee.
INPUT LOGIC CODING
STRAIGHT BINARY
MSB
LSB
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000
OUTPUT RANGES
+5V Oto +10V
+4.9988
+9.9976
+3.7500
+7.5000
+5.0000
+2.5000
+ 1.2500
+2.5000
+0.0012
+0.0024
0.0000
0.0000
oto
OFFSET BINARY
MSB
LSB
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000
TWO'S COMPLEMENT
OUTPUT RANGES
+2_5V
MSB
LSB
±5V
±10V
+2.4988 +4.9976 +9.9951
0111 1111 1111
0100 0000 0000
+1.2500 +2.5000 +5.0000
0.0000
0000 0000 0000
0.0000
0.0000
-1.2500 -2.5000 -5.0000
1100 0000 0000
-2.4988 -4.9976 -9.9951
1000 0000 0001
1000 0000 0000
-2.5000 -5.0000 -10.0000
CODING NOTES:
1. For unipolar operation, the coding is straight binary.
2. For bipolar operation, the coding is either offset binary or two's complement.
3. For FSR = 20V, 1 LSB = 4.BBmV
4. For FSR 10V, 1 LSB 2.44mV
5. For FSR = SV, 1 LSB = 1.22mV
=
=
OUTPUT RANGE SELECTION
Pin Connections
Connect Pin 15 to
Connect Pin 17 to
Connect Pin 19 to
7-8
oto
+5V
18
21
20
Oto +10V
18
21
-
±2.5V
18
20
20
±5V
18
20
±10V
19
-
15
20
l1JJ
_
DAC71
INDUSTRY-STANDARD
16-Bit
D/A CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• 16-Bit Resolution
• Complete With Internal
Reference and Output
Op Amp (V Models)
• Current or Voltage Output
• ±O.003%FSR Linearity
Guaranteed
• 14-Bit Monotonicity Guaranteed
Over Temperature
• Fast Settling:
10l'sec (V Models)
1J'Sec (I Models)
• 24·Pin Side-Brazed DIP
• Multisourced
DAC71 is a 16-bit hybrid digital-to-analog converter in a small,
24-pin, dual-in-line package. This high-resolution D/A includes
an internal reference and is available in both voltage and current
output models. The DAC71 offers a guaranteed maximum
linearity error of ±O.003%FSR at +25°C and guarantees 14-bit
monotonicity over temperature.
Utilizing the most advanced functional laser trimming techniques, DAC71 eliminates the need for external trimpots, and all
parameters are specified without adjustment. Optional gain and
offset adjustment points are available for applications requiring
greater accuracy.
All models of DAC71 have complementary binary coded inputs.
Units are available with output voltage ranges of 0 to +10Vor
± 10V or output current ranges of ± 1mA or 0 to --2mA Devices
operate from ± 15V power supplies; consume 525mW; and are
direct pin-for-pin replacements for DAC71 devices from other
manufacturers.
DAC71 is the ideal choice for applications requiring high resolution, small size and low cost. Typical applications include
robotics, high-resolution servo and control systems, highaccuracy function generation and precision instrumentation.
24-PIN SIDE-BRAZED DIP
-r
Pl" 1
Model
Number
Input Code
Output Mode
DAC71-COB·V
DAC71-CSB-V
Complementary Offset Binary
Complementary Straight Binary
-10V to + 10V
0 to + 10V
DAC71-COB-1
DAC71·CSB-1
Complementary Offset Binary
Complementary Straight Binary
-lmA to + lmA
0 to -2mA
g30(31.24)
1.270(32.26)
.L---------'.
~
~~~f,Wslj O.153(3.~
Ir::::
0.183(4.65)
IF=~=023I~~
0.200 IS.OB)
0.230 (5.84)
0,012 (O.30)
l..-o.sOO(lS.24)--l
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
February 1992
Copyright©I992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
7·9
DAC71 INDUSTRY-STANDARD 16-Bit D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
Positive Supply (+Vcc, Pin 23)
Negative Supply (-Vcc, Pin 19)
Digital Inputs (Pins 1-16)
ORDERING INFORMATION
O°C to +70°C
-65°C to + 150°C
a to +18 Volts
a to -18 Volts
-0.5 to +18 Volts
III
PART NUMBER - - - - - - - - - - DAC71-CSB-V
Select "COB" suffix for Complementary
Offset Binary coding or "CSB" suffix for
Complementary Straight Binary coding. - - - - - - - ' .
Select "V" suffix for voltage output
or "I" suffix for current o u t p u t . - - - - - - - - - - '
SPECIFICATIONS (TA= +25"C, ±Vcc= ±15V, unless otherwise indicated) (Note 1)
DIGITAL INPUTS
MIN.
Logic Levels: Logic "1"
Logic "0"
+2.4
Input Currents: Logic "1" (VIH = +2.7V)
Logic "0" (VIL = +0.4V)
TYP.
MAX.
UNITS
+0.8
Volts
Volts
"A
+40
-1.0
mA
Oto +10
±10
Volts
Volts
ANALOG OUTPUTS (VOLTAGE MODELS)
Voltage Models (Note 2): DAC71-CSB-V
DAC71-COB-V
Output Current
mA
±5
0.15
Output Impedance
Short Circuit Duration
Il
Indefinite to Ground
ANALOG OUTPUTS (CURRENT MODELS)
Current Models (Note 2): DAC71-CSB-1
DAC71-COB-1
Oto -2
±1
mA
mA
Compliance Voltage
±2.5
Volts
Output Impedance: Unipolar
Bipolar
4
2.45
kll
kll
TRANSFER CHARACTERISTICS (Note 3)
Linearity Error
Temperature Range For 14-Bit Monotonicity
±0.003
a
%FSR
+70
°C
Unipolar Offset Error (Notes 4, 5): DAC71-CSB-V
DAC71-CSB-1
±0.1
±0.1
%FSR
%FSR
Bipolar Offset Error (Notes 4, 6): DAC71-COB-V
DAC71-COB-1
±0.1
±0.1
±0.1
±0.1
%FSR
%FSR
0/0
%
Unipolar Offset Drift: DAC71-CSB-V
DAC71-CSB-1
±10
±10
ppm of FSR/oC
ppm of FSR/oC
Bipolar Offset Drift: DAC71-COB-V
DAC71-COB-1
±15
±40
ppm of FSR/oC
ppm of FSR/oC
Gain Drift: Voltage Models
Current Models
±20
±45
ppm/oC
ppm/oC
10
!,sec
!,sec
Gain Error (Notes 4, 7): Voltage Output
Current Output
±0.05
±0.05
DRIFT SPECIFICATIONS (Notes 3, 8)
DYNAMIC CHARACTERISTICS
Settling Time (Voltage Models): 20V Step to ±0.003%FSR
1 LSB Step (Note 10)
Slew Rate (Voltage Models)
Settling Time (Current Models) lmA Step to ±OOO3%FSR: 100 to l001l Load
lkll Load
7-10
5
3
±10
Vi!'5ec
1
3
!'5ec
!,sec
I REFERENCE OUTPUT
Internal Reference: Voltage
Tempco
External Current
MIN.
TYP.
±1.5
+6.3
±10
±2.5
MAX.
+14.55
-14.55
+15.00
-15.00
UNITS
Volts
ppmloC
mA
POWER SUPPLIES
Power Supply Range: + 15V Supply
-15V Supply
Power Supply Rejection: + 15V Supply
-15V Supply
+15.45
-15.45
±0.001
±0.001
Volts
Volts
%FSRI%Vs
%FSRI%Vs
Current Drain: + 15V Supply
-15V Supply
+18
-17
+35
-30
mA
mA
Power Consumption
525
975
mW
SPECIFICATION NOTES:
,. Unless otherwise indicated, listed specifications apply for all DAC71 models.
2. DAC71 is available in both voltage output (DAC71-CSB-V, DAC71-COB-V) and current output (DAC71-CSB-I, DAC71-COB-I) models.
3. FSR stands for full scale range and is equal to the peak-to-peak voltage of the
selected output range. For the ±10V output range, FSR is 20 Volts, and lLSB
is ideally equal to 300pV. For the 0 to +10V range, FSR is 10 Volts, and lLSB is
ideally equal to 150pV.
4. Initial offset and gain errors are adjustable to zero with user·optional, external
trimming potentiometers.
5. Unipolar offset error is defined as the difference between the actual and the ideal
output voltage with a digital input of 1111 1111 11111111.
6. Bipolar offset error is defined as the difference between the actual and the ideal
output voltage with a digital input of 1111 1111 1111 1111.
7. Gain error is defined as the error in the slope of the converter transfer function.
It is expressed as a percentage and is equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value for the full output voltage or
current span from the 1111 1111 1111 1111 output to the 0000 0000 0000 0000
output.
8. Drift specifications apply over the aoc to +70 0 e temperature range for all models.
9. Specified with gain and offset errors adjusted to zero at +25°C.
10. LSB step is for 14-bit resolution.
BLOCK DIAGRAM
PIN DESIGNATIONS
(24) ReI. Output
MSB
(I)
Bit2
8it3
(2)
(3)
(4)
(5)
Sit4
BitS
Bit6
Bit?
Bit8
Bit9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
lSB
168lT
CURRENT
SWITCH
'NO
(10)
(It)
(12)
(t3)
(t4)
(t5)
(tS)
13
II Out)
(Rt)
~
Not.:
Current Output models do not
include output op amp
~
12
(21) Summing JunctIon
(17) Analog Output
Ground (20)
Rt
24
(22) Gain Adjust
(5)
(7)
(S)
(9)
+15V Supply (23)
-15V Supply (19)
•
PIN 1
5K{CSB), 10K{COB)
1
2
3
4
5
6
7
8
9
10
11
12
Bit 1 (MSB)
Blt2
Bit3
Bit4
Bit 5
Bit 6
Bit 7
Bit8
Bit9
Bit 10
Bit 11
Bit 12
24 VrefOut
23 +15V Supply
22 Gain Adjust
2t Summing Junction (lOut for Current Out)
20 Ground
19 -15V Supply
18 N.C.
17 Vout RF for Current Out)
16 Bit 16 (LSB)
15 Bit 15
14 Bit 14
13 Bit 13
7-11
INPUT LOGIC CODING
Voltage Output (Volts)
Digital Input
MSB
LSB
0000 0000 0000 0000
0000 0000 0000 0001
0111 1111 1111 1111
1000 0000 0000 0000
1111 11111111 1110
1111111111111111
Current Output (rnA)
CSB
COB
CSB
COB
+9.99985
+9.99970
+5.00000
+4.99985
+0.00015
0.00000
+9.99969
+9.99939
0.00000
-0.00031
+9.99969
-10.00000
-1.99997
-1.99994
-1.00000
-0.99997
-0.00003
0.00000
-0.99997
-0.99994
0.00000
+0.00003
+0.99997
+1.00000
CODING NOTES
1. CSB=Complementary straight binary for unipolar output ranges.
2. COB = Complementary offset binary for bipolar output ranges.
3. For FSR=2OV. 1 LSB=300~V
4. For FSR=IOV. 1 LSB=150~V
5. For FSR=2mA. 1 LSB=30nA
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy from DAC71.
The unit's ground connection (pin 20) must be tied to circuit analog
ground as close to the package as possible, preferably through a
large ground plane underneath the package.
should be ± 20% carbon composition or better and must be located
as close as possible to the package to prevent noise pickup. A O.D1I'F
ceramic capaCitor should be connected from gain adjust (pin 22)
to ground.
Power supplies should be decoupled with tantalum or electrolytic
type capacitors located close to the unit. For optimum performance,
11'F capacitors paralleled with O.D1I'F ceramic capacitors should
be used as shown in the following diagrams.
OFFSET ADJUSTMENT-Connect the offset potentiometer as
shown and apply all "1's" to the digital inputs. Adjust the potentiometer until the analog output is equal to zero volts for unipolar
output ranges or minus full scale voltage for bipolar output ranges.
POWER SUPPL Y DECOUPLING
Pin230
1 .F
I
I
o.ot .F
Pin 21
3.9Mn
o------'W/"'------;;>~
1.F
T lo.
01 • F
-15V
15V
Coupling between analog and digital signals should be minimized
to avoid noise pickup. If external gain and offset adjustments are
to be used, the series resistors should be located as close to the
unit as possible.
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
and apply all "a's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the maximum positive voltage for the
chosen output range as shown in the Coding table.
DAC7l has a guaranteed linearity specification of 14 bits.lfthe 16-bit
resolution of the device is not required, bit 15 (pin 15) and bit 16 (pin
16) should be connected to +5V through a single 1kO resistor.
High resolution devices such as DAC71 present unique layout problems. Grounding and contact resistance become a matter of critical
importance. A l6-bit converter with a 10V FSR has an LSB value
of 150"V. Assuming a 5mA load, series wiring and contact resistance
of only 3OmO will throw the output off 1LSB. In terms of system layout,
the impedance of #18 wire is approximately 0.064!l1ft. Assuming 0
contact resistance, less than 6 inches of wire could produce a 1LSB
error in the analog output. Careful layout and the use of external
trim potentiometers for gain and offset can eliminate many potential sources of error.
OPTIONAL GAIN AND OFFSET ADJUSTMENTS-DAC71 will
operate as specified without external adjustment. If desired.
however, gain and offset errors can be trimmed with potentiometers.
Adjustments should be made following warmup, and to avoid interaction, the offset adjustment must be made before the gain adjustment. Multitu rn potentiometers with TCR 's of 100ppm/o C or less are
recommended to minimize drift with temperature. Series resistors
7·12
1~:n
l00Kn
Pin 20 + - f G r o u n d
Pin 19 0
!
+15V
+15V
!
+15V
P,n 22
270Kn
0---1r---W/"I...------3:>O~
r
l~:n
l00Kn
.D1j.1F
-15V
REFERENCE OUTPUT-All DAC71 models contain an internal
+6.3V voltage reference. The reference output (pin 24) may be used to drive an external load. A buffer amplifier is recommended if
external load current exceeds 1.5mA.
OUTPUT COMPLIANCE VOLTAGE-Compliance voltage is the
maximum voltage swing allowed on the output of the current models
while maintaining specified accuracy. DAC7l is specified for a compliance voltage swing of ± 2.5V, and an absolute maximum range
of 5V is permitted without damage to the device.
DAC80
~
LOW-COST
MONOLITHIC, 12-Bit
D/A CONVERTERS
MICRO NETWORKS
DESCRIPTION
The Micro Networks DAC80 is a complete, single-chip, low-cost,
12-bit D/A converter. It represents the most recent monolithic implementation of the venerable hybrid DAC80 that has long been
an industry standard. The popularity of this proven product is
due to its low cost; its multisource availability; its guaranteed
performance over temperature; its optional current or voltage
output; its fast settling time; and its ability to operate from either
± 12V or ± 15V supplies. This latest design employs an on-chip
buried-zener reference for low noise; the newest thin-film
fabrication and laser-trimming techniques for tight accuracy and
linearity guaranteed over temperature; a proprietary referencebuffer circuit that permits fully specified operation over a wide
supply range; and an on-chip output op amp for current-tovoltage conversion and fast settling.
FEATURES
• Low-Cost Single-Chip Design
• Current or Voltage Output
• Complete With Internal
Reference and Output
Op Amp (V Models)
• ± V2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Fast Settling:
3p.Sec (V Models)
300nsec (I Models)
• .±12V to ±15V Supplies
• 345mW Power Consumption
• 24-Pin Side-Brazed
Ceramic DIP
These DINs are TIL voltage compatible; however, they draw low
enough logic currents to be driven from CMOS logic. ± 112LSB
linearity and monotonicity for 12-bits are guaranteed over the full
O°C to +70°C operating temperature range. Output settling time
for a 20V step to ± 112LSB is 4J-!sec maximum. A 2mA step
typically settles in 300nsec.
• Multisourced
24 PIN SIDE-BRAZED DIP
0.030(0.761
,-------LL----.
=:i
T L,
omo (U8)
PIN 1
1.185(30.10)
"00(27.94)
'·215(30'~'1
1
LC-~-·-:080-0(~-::~-1j-
t·
i
I.-
0.600 (15.24)
-J
0.021(0.53)
t~"2~:~~~\
-
::~:~:
'-0.170(4.32)
0.008(0.20)
0.012(0.30)
DAC80 is packaged in a 24-pin, side-brazed, ceramic DIP and
requires supplies that can range from ± 12V to ± 15V. On-chip,
laser trimmed, thin-film, range resistors allow users to select output voltage ranges of ± 2.5V, ±5V, ± 10V, 0 to +5V or 0 to + 10V
and output current ranges of ±1mA or 0 to -2mA. The Micro
Networks monolithic DAC80 is a pin-for-pin, functionally
equivalent replacement for earlier hybrid versions of this device
except that it no longer requires a +5V supply. Some other
monolithic DAC80's are not exact replacements. The DACBO
"Z" model is no longer a necessary ordering option as all
models now operate from ± 12V to ± 15V supplies. For -25°C to
+85°C or -55°C to +125°C operation, please see the Micro
Networks DAC85 or DAC87.
Model
Input Code
Output Mode
Power Supplies
DAC80-CBI-V
DAC80-CBI-1
Complementary Binary
Complementary Binary
Voltage
Current
±12V1±15V
±12V/±15V
Dimensions in Inches
(millimeters)
~
April 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-13
DAC80 LOW-COST MONOLITHIC 12-Bit D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range
Storage Temperature Range
+Vcc Supply (Pin 22)
-Vcc Supply (Pin 14)
Digital Inputs (Pins 1-12)
Analog Output
-25°C to +85°C
O°C to +70°C
-65°C to + 150°C
a to +18 Volts
a to -18 Volts
-1 to +18 Volts
(Note 1)
PART NUMBER - - - - - - - - - - D A C 8 0 - C B I - X
Select "V" suffix for voltage output
I
or "I" suffix for current output. - - - - - - - - - - - ' .
SPECIFICATIONS (TA =+25°C, ±Vcc= ± 15V unless otherwise indicated)
DIGITAL INPUTS
MIN.
TYP.
Resolution
MAX.
Logic Coding (Note 2): Voltage Output
Current Output
Bits
CSB,COB
CSB,COB
Logic Levels: Logic "I"
Logic "a"
+2.0
Logic Currents: Logic "I" (VIH =+2.4V)
Logic "a" (Vll =+OAV)
+20
-ISO
Output Voltage Ranges
±2.5, ±5, ±1O,Oto +5,Oto +10
Output Current
±5
Output Impedance
,.A
,.A
- - r--------.
Output Current Ranges
Volts
!l
r---
±1,Oto-2
Output Impedance: Unipolar Range
Bipolar Range
-_.
_<:;ompliance Voltage
4.6
2.6
6.6
3.2
rnA
8.6
3.7
- - r--
Linearity Error (O°C to +70°C)
Linearity Error (O°C to +70°C)
Temperature Range For Guaranteed Monotonicity
--
Unipolar Offset Error (Notes 4, 5)
Bipolar Offset Error (Notes 4, 6)
~ain !,~!(Notes 4, 7)
--
kll
kl2
±2.5
...
:!!I~NSFER C~RACTERISTICS (Note 3)
--
rnA
0.05
ANALOG OUTPUTS (CURRENT MODEL)
~~fferential
-Volts
Volts
+16.5
+O.S
a
f----ANALOG OUTPUTS (VOLTAGE MODEL)
f--~ntegral
UNITS
12
Volts
±lh
LSB
- - - - 1 - - - - - - -1 - - - - - - - - _ . - - f - - -±V4
±1/2
±J.4
LSB
-r--'--"- - '
a
+70
°C
- -1--..- -..- - - - ±0.05
±0.05
±0.1
_._---
o..f!!.FT S~~IFICATIONS (Note S)
±0.15
±0.15
±0.3
%FSR
%FSR
%
..
±10
±25
-±O.OS
±0.15
Total Error (O°C to + 70°Cj (Note 10): Unipolar
±0.06
±0.12
Bipolar .._.
- - - - - - - - - - _.. .. .._---_.
....
...
... _ - - - - - - - - - - - _._--... ----- ._-"--±3
±1
Unipolar Offset Drift
±15
±5
.Bip~Iar..()~fse~..[)r~f!.. _ _ ..___.. _ _ ._. - - _ - - - - - - - - _ .
±15
±30
Gain Drift: Including Internal Reference
±10
±5.
.. _~c~u~i~tern~l'l.efererJC:~ ______________._..
_.
...Total Bipolar Drift (Note 9)
ppm of FSR/oC
.. _ - - - -
__
__ __ __
_
.~--
r--'
%FSR
%FSR
ppm of FSR/oC
ppm of FSR/oC
..
...
__
DYNAMIC
CHARACTERISTICS
_._--"".
._-- ------_._------_._--_._._. __ ._----- ------Settling Time (Note 11) Voltage Output:
With 10k!! Feedback
With 5kU Feedback
F~rlL.SB ..Ch
Control
Bit 3 (3)
' - - - - - - 0 (16) Ref. Input
Bill0 (10)
LSB (12)
Bit 2 (2)
R
":'
f-.....---+-......-~
----0
(14) - Vee
-------0 (15) Vout
Bit 10 (10)
Bit 11 (11) 0------'
LSB(12) 0 - - -_ _-'
1
2
3
4
5
6
7
8
9
10
11
12
Bit 1 (MSB)
Bil2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bil9
Bill0
Bit 11
Bit 12 (LSB)
24
23
22
21
20
19
18
17
16
15
14
13
---0
(14) -Vee
---0
(13) N.C.
Ref. Oul ( + 6.3V)
Gain Adjust
+Vee Supply
Ground
Summing Junction
20V Range
10V Range
Bipolar Onset
Ref. Input
Output Voltage
-Vee Supply
N.C.
7·15
A~PLlCATIONS
INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy and speed
from the DACSO. The unit's ground (pin 21) must be tied to circuit
analog ground as close to the package as possible, preferably
through a large analog ground plane underneath the package.
Power supplies should be decoupled with tantalum or electrolytic
and ceramic capacitors located close to the unit. Foroptimum performance, 1iF tantalums paralleled with 0.Q1 iF ceramic capacitors
should be used. Coupling between analog and digital signals should
be minimized to avoid noise pickup. Short jumpers should be used when tying the Reference Output (pin 24) to the Reference Input (pin 1b) and when tying the Bipolar Offset (pin 17) to the Summing Junction (pin 20, V models) or Output (pin 15, I models) for
bipolar operation. If external gain and offset adjustments are to be
used, the series resistors and trim pots should be located as close
to the unit as possible.
REFERENCE OUTPUT-The DAC80 contains an internal +6.3V
± 1% voltage reference, and the units are actively laser trimmed to
operate from this reference. Therefore, though the user has the option of using an external reference, for specified operation, the
Reference Output (pin 24) must be connected to ,he Fieference Input (pin 16).lfthe internal reference is used to drive an ext\Jrnalload,
it should be buffered if the load current will exceed 2.5mA.
± 12V OPERATION-All DACSO models can operate over the entire power supply range of ± 11.4V to ± 16.5V. Even with supply levels
dropping to ± 11.4V, the DAC80 can swing a full ± 10V range, provided the load current is limited to ±2.5mA. With power supplies
greater than ± 12V, the DAC80 output can be loaded up to ± 5mA
over the entire ±Vcc range.
should be made following warmup, and to avoid interaction, the offset adjustment must be made before the gain adjustment. Multiturn
potentiometers with TCR's of 100ppm/oC or less are recommended to minimize drift with temperature. Series resistors can be ± 20%
carbon composition or better.lfthese adjustments are not used, pins
20 and 23 should be connected as described elsewhere (do not
ground).
OFFSET ADJUSTMENT-Connect the offset potontiometer to pin
20 for voltage output models or pin 15 for current output models and
apply all "1's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the appropriate value for unipolar or
bipolar output ranges as listed in the Digital Input Coding table.
+15V
(V)~.9MU
Pin 20
Pin 15 (I)
+15V
10kU
to
1QOkU
Pin 20 (V)
1aOk!1
180k!1
10kU
Pin 15 (I) o--¥l'r-~.J.t\,.,-,~ 10
100kU
-15V
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
and apply all "O's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the appropriate value listed in the Digital
Input Coding table.
+ 15V
Pin 23O-~...JVII'r---O;:
OPTIONAL GAIN AND OFFSET ADJUSTMENTS-The DACSOwili
operate as specified without external adjustments. If desired,
however, absolute accuracy error can be reduced to ± 'i2LSB by
following the trimming procedure described below. Adjustments
+ 15V
10kU
10
100kU
-1SV
DRIVING EXTERNAL OP AMPS
(lOut Models)
OUTPUT RANGE SELECTION
Output
Range
Connect
Pin 15 to
Connect
Pin 17 to
±10V
±5V
±2.5V
o to +10V
o to +5V
±lmA
Oto -2mA
19
18
18
18
18
17
20
20
. 20
21
21
15
21
N.C.
SkU
(19)
I
,, 20V Range
I
Connect
Pin 19to
Connect
Pin 16 to
15
24
24
24
24
24
24
24
N.C.
20
N.G.
20
N.C.
N.C.
,'...-------4--0
10V Range
(18) I
I
(15)
6.6kO
I
I
I
I
voul
I
(21)
I
DIGITAL INPUT CODING
Digital Input
MSB
0000 0000 0000
000000000001
011111111111
1000 0000 0000
111111111110
111111111111
7·16
Current Output
Voltage Output
LSB
Oto +5V
+4.9988
+4.9976
+2.5000
+2.4988
+0.0012
0.0000
o to
+10V
+9.9976
+9.9951
+5.0000
+4.9976
+0.0024
0.0000
±2.5V
±5V
±10V
Oto -2mA
±1mA
+2.4988
+2.4976
0.0000
-0.0012
-2.4988
-2.5000
+4.9976
+4.9951
0.0000
-0.0024
-4.9976
-5.0000
+9.9951
+9.9902
0.0000
-0.0049
-9.9951
-10.0000
-1.9995
-1.9990
-1.0000
-0.9995
-0.0005
0.0000
-0.9995
-0.9990
0.0000
+0.0005
+0.9995
+1.0000
DAC85
l1JJ
_
HIGH-SPEED
INDUSTRIAL, 12-Bit
D/A CONVERTERS
MICRO NETWORKS
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
The Micro Networks DAC85 is a complete, single-chip, low-cost,
12-bit D/A converter. It represents the most recent monolithic
implementation of the hybrid DAC85 - a proven device whose
small package, high reliability and guaranteed performance over
the -25°C to +85°C temperature range have made it a standard for demanding industrial applications. This newest version
of the DAC85 now guarantees its settling time (4p.sec for a 20V
step settling to ± 112 LSB) and has the ability to operate from
either ± 12V or ± 15V supplies. It employs an on-chip, buriedzener reference for low noise; the newest thin-film fabrication
and laser-trimming techniques for tight accuracy and linearity
guaranteed over temperature; a proprietary reference buffer
circuit that permits fully specified operation over a wide supply
range; and an on-Chip output op amp for current-to-voltage conversion and fast settling.
Low-Cost Single-Chip Design
-25"C to +85°C Operation
Current or Voltage Output
Complete With Internal
Reference and Output
Op Amp (V Models)
± V2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
Fast Settling:
3",sec (V Models)
300nsec (I Models)
± 12V to ± 15V Supplies
345mW Power Consumption
24-Pin Side-Brazed
Ceramic DIP
Multisourced
These DINs are TTL voltage compatible; however, they draw low
enough logic currents to be driven from CMOS logic. ± 112LSB
linearity and monotonicity for 12-bits are guaranteed over the full
-25°C to +85°C operating temperature range.
DAC85 is packaged in a 24-pin, side-brazed, ceramic DIP and
requires supplies that can range from ± 12V to ± 15V. On-chip,
laser trimmed, thin-film, range resistors allow users to select output voltage ranges of ± 2.5V, ±5V, ± 10V, 0 to +5V or 0 to + 10V
and output current ranges of ± 1mA or 0 to -2mA.
24 PIN SIDE-BRAZED DIP
T -,
ll~--'Q261
,.------ll-----
L
1.185/30.10)
1100(27.94)
J
1.2"(30'''~)
='Bl
~I
~J
t
~
f9
0.600 (15.24)
I.-
0-021 (0.53)
~~
0.240(6.10)
-
0.025 (0.64)
0.060(1.52)
.--~
0.170(4.32)
. . . . . . ~OO8 (0.20)
0.012(0.30)
The Micro Networks monolithic DAC85 is a pin-for-pin, functionally equivalent replacement for earlier hybrid versions of this
device except that it no longer requires a +5V supply. Some
other monolithics are not exact replacements. The DAC85 "Z"
model is no longer a necessary ordering option as all models
now operate from ±12V to ±15V supplies. For -55 D C to
+ 125°C operation with or without MIL-STD-883 screening,
please see Micro Networks DAC87.
Model
Number
DAC85-CBI-1
DAC85-CBI-V
Temperature
Range
-25°C to +85°C
-25°C to +85°C
Input
Code
Complementary Binary
Complementary Binary
Output
Mode
Current
Voltage
0.600(15.24)--..l
Dimensions In Inches
(millimeters)
~
April 19BB
MICRO NETWORKS
324 Clark St.. Worcester, MA 01606 (508) 852-5400
7-17
DAC85 HIGH-SPEED INDUSTRIAL 12-Bit D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range
Storage Temperature Range
+ Vcc Supply (Pin 22)
-Vcc Supply (Pin 14)
Digital Inputs (Pins 1-12)
Analog Output
ORDERING INFORMATION
-55°C to +125°C
-25°C to +85°C
-65°Cto +150°C
Oto +18 Volts
to -18 Volts
-1 to +18 Volts
(Note 1)
PART NUMBER - - - - - - - - - - DAC8S-CBI-X
I
Select "V" suffix for voltage output
or "I" suffix for current output. - - - - - - - - - - ' .
o
SPECIFICATIONS (TA = +2SoC, ±Vcc= ± 12V or ± 15V unless otherwise indicated)
DIGITAL INPUTS
MIN.
Resolution
MAX.
12
Logic Coding (Note 2): Voltage Output
Current Output
Logic Levels: Logic "1"
Logic "0"
TYP.
UNITS
Bits
CSB,COB
CSB,COB
+2.0
0
Logic Currents: Logic "I" (VIH = +2.4V)
Logic "0" (Vll = +OAV)
+16.5
+0.8
Volts
Volts
+20
-180
pA
pA
ANALOG OUTPUTS (VOLTAGE MODEL)
Output Voltage Ranges
±2.5, ±5, ±10,Oto +5,Oto +10
Output Current
±5
Output Impedance·
Volts
rnA
0.05
Il
ANALOG OUTPUTS (CURRENT MODEL)
Output Current Ranges
Output Impedance: Unipolar Range
Bipolar Range
Compliance Voltage
±1,Oto-2
4.6
2.6
6.6
3.2
rnA
8.6
3.7
±2.5
kll
kll
Volts
TRANSFER CHARACTERISTICS (Note 3)
Integral Linearity Error (-25°C to +85°C)
±'I4
± 'I,
LSB
Differential Linearity Error (-25°C to +85°C)
±'/2
±3J4
LSB
Temperature Range For Guaranteed Monotonicity
-25
Unipolar Offset Error (Notes 4, 5)
Bipolar Offset Error (Notes 4, 6)
Gain Error (Notes 4, 7)
±0.05
±0.05
±0.1
+85
°C
±0.1
±0.15
±0.2
%FSR
%FSR
%
DRIFT SPECIFICATIONS (Note 8)
±10
±25
ppm of FSR/oC
±O.OB
±0.06
±0.2
±O.12
%FSR
%FSR
Unipolar Offset Drift
Bipolar Offset Drift
±1
±5
±3
±10
ppm of FSR/oC
ppm of FSR/oC
Gain Drift: Including Internal Reference
Excluding Internal Reference
±15
±5
±20
±10
ppm/DC
ppm/DC
Settling Time (Note 11) Voltage Output:
With 10kll Feedback
With 5kll Feedback
For 1 LSB Change
3
2
1
4
3
I'sec
I'sec
J'Sec
Settling Time (Note 11) Current Output:
For lOll to 1001l Loads
For lkll Load
300
1
nsec
J'Sec
±15
V/J'Sec
Total Bipolar Drift (Note 9)
Total Error (-25°C to +B5°C) (Note 10): Unipolar
Bipolar
DYNAMIC CHARACTERISTICS
~ate (Voltage Models)
7-18
±10
INTERNAL REFERENCE
TYP.
MIN.
Internal Reference: Voltage
Accuracy
Drift
External Current
+6.3
±1
±10
MAX.
UNITS
±20
2.5
Volts
%
ppm/oC
rnA
+16.5
-16.5
Volts
Volts
POWER SUPPLIES
Power Supply Range: +Vcc Supply
-Vcc Supply
+11.4
-11.4
+15
-15
Power Supply Rejection: +Vcc Supply
-Vcc Supply
%FSR/%Supply
%FSR/%Supply
±0.002
±0.002
Current Drains: +Vcc Supply
-Vcc Supply
+8
-15
+12
-20
rnA
rnA
Power Consumption
345
480
rnW
SPECIFICATION NOTES:
1. The DAC85's output is short-circuit protected and units can withstand a sustained
short to ground or either power supply.
CSB~complementarystraight binary. COB~complementaryoffset binary. See
Digital Input Coding table for details.
3. FSR stands for full scale range and is equivalent to the nominal peak-to-peak
voltage (current) of the selected output range. FSR~5 volts for a to +5V and
±2.5Voutput ranges. FSR~10volts forOto + IQV and ±5Voutput ranges etc..
For a 12-bit cunverter, IlSB~0.024%FSR.
4. Initial offset and gain errors are adjustable to zero with user-optional, external,
trimming potentiometers.
5. Unipolar offset error is the difference between the actual and the ideal output
when operating on a unipolar output range with a digital input of 1111 1111 1111.
2.
6. Bipolar offset error is the difference between the actual and the ideal output when
operating on a bipolar output range with a digital input of 1111 1111 1111.
7. Gain error is defined as the error in the slope of the converter transfer function.
It is expressed as a percentage and is equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value for the full voltage or current
output span from the 1111 1111 1111 output to the 0000 0000 0000 output.
8. To maintain published drift specifications, current output models must use in~
ternal feedback resistors.
9. Includes gain, offset and linearity drifts.
10. With initial gain and offset errors adjusted to zero at +25°C.
11. Settling time specified for an FSR step settling to ±O.Ol%FSR (± 'hlSB).
BLOCK DIAGRAMS and PIN DESIGNATIONS
(Current Models)
MSB(l)
(Voltage Models)
o------,~
Bit 2 (2)
":"
Control
(24) Ref. Out
MSB (1)
(23) Gain Adjust
Bit 2 (2)
<>------,~f
'J: rRef.I L.o
":"
Control
Bit 4 (4)
---0
12·Bil
Resistor
Ladder
Network
and
Current
Switches
Bit 5 (5)
Bit 6 (6)
Bit 7 (7)
Bit 8 (8)
3kO
I-~-t-'M-""'---o
(21) Ground
Bit 4 (4)
(20) Scaling Network
Bit 5 (5)
(19) Scaling Network
Bi' 6 (6)
(18) Scaling Network
Bi' 7 (7)
12·8it
ReSistor
Ladder
Network
and
Current
Switches
5kO
t---'Ni,.--<>
(17) Bipolar
Offset
Bit 8 (8)
f--~---+-~--<> (20) Summing Junction
ti:
I
6.3kO
'--------0
Bit 10 (10)
(15)
lout
0----==11---'
~
0-------'
---<> (13) N.C.
1
2
3
4
5
6
7
8
9
10
11
12
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1 (MSB)
2
3
4
5
6
7
8
9
10
11
12 (lSB)
24
23
22
21
20
19
18
17
16
15
14
13
(19) 20V Range
SkO
(18) 10V Range
(17) Bipolar Offset
63kO
'-------<> (16) Ref. Input
Bit 9 (9)
LSB (12)
(23) Gain Adjust
Bit 3 (3)
Bit 3 (3)
Bit 11 (11)
(24) Ref. Out
(14) -Vee
Ref. Out (+ 6.3V)
Gain Adjust
+Vce Supply
Ground
Bi' 9 (9)
(16) Ref. Input
>-----<>
Bit 10 (10)
0------'
LSB (12) 0---__-"
1
2
3
4
Scaling Network
Scaling Network
Scaling Network
Bipolar Offset
Ref. Input
Output Current
-Vee Supply
N.C.
~
Bit 11 (11)
7
8
9
10
11
12
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1 (MSB)
2
3
4
5
6
7
8
9
10
11
12 (lSB)
(15)
------0 (13)
24
23
22
21
20
19
18
17
16
15
14
13
Vou!
(14) -Vcc
N.C
Ref. Out ( + 6.3V)
Gain Adjust
+Vec Supply
Ground
Summing Junction
20V Range
10V Range
Bipolar Offset
Ref. Input
Output Voltage
- Vce Supply
N.C.
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy and speed
from the DAC8S. The unit's Ground (pin 21) must be tied to circuit
analog ground as close to the package as possible, preferably
through a large analog ground plane underneath the package.
Power supplies should be decoupled with electrolytic and ceramic
capacitors located close to the unit. For optimum performance, 1pF
tantalums paralleled with 0.01 pF ceramic capacitors should be used.
7-19
Coupling between analog and digital signals should be minimized
to avoid noise pickup. Short jumpers should be used when tying
the Reference Output (pin 24) to the Reference Input (pin 1S) and
when tying the Bipolar Offset (pin 17) to the Summing Junction (pin
20, V models) or Output (pin 15, I models) for bipolar operation. If
external gain and offset adjustments are to be used the series
resistors and trim pots should be located as close to the unit as
possible.
REFERENCE OUTPUT-The DAC85 contains an internal +S.3V
± 1% voltage reference, and the units are actively laser trimmed to
operate from this reference. Therefore, though the user has the option of using an external reference, for specified operation, the
Reference Output (pin 24) must be connected to the Reference Input (pin IS). If the internal reference is used to drive an external load,
it should be buffered if the load current will exceed 2.5mA.
OUTPUT RANGE SELECTION
I
f-
Output
Range
±10V
±5V
±2.5V
to +10V
o to +5V
i ±lmA
LOto -2mA
o
Connect
Pin 15 to
Connect
Pin 17 to
Connect
Pin 19 to
Connect
Pin 16 to
19
18
18
18
18
17
20
20
20
21
21
15
N.C.
15
N.C.
GND
N.C.
N.C.
24
24
24
24
24
24
24
20
N.C.
20
GAIN ADJUSTMENT-Connect the Gain potentiometer as shown
and apply all "O's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the appropriate value listed in the Digital
Input Coding table,
+ 15V
10MU
270kn
10kn
to
l00kO
Pin 23
lO,Ol
+ 15V
270kO
lQkn
to
lookl1
Pin 23
J1 F
7.8kt!
-15V
-15V
CURRENT OUTPUT MODELS-Current output models of the
DAC85 may be used to drive the summing junction of an output op
amp to produce an output voltage. Using the internal feedback
resistors of the DAC85-CBI-1 provides the same output voltage
ranges as the voltage model. To obtain the desired output voltage
range when connecting an external op amp, refer to the figure and
table below,
5"0
(t9)
,, 20V Range
,
,,
I
I
10V Range
(t8) I
(15)
6.6""
I
I
I
I
I
A
Vout
I
(21) I
OPTIONAL GAIN AND OFFSET ADJUSTMENTS-The DAC85 will
operate as specified without external adjustments. If desired,
however, absolute accuracy error can be reduced to ± 'hLSB by
following the trimming procedure described below. Adjustments
should be made following warmup, and to avoid interaction, the offset adjustment must be made before the gain adjustment. Multiturn
potentiometers with TCR's of 100ppm/oC or less are recommended to minimize drift with temperature. Series resistors can be ± 20%
carbon composition or better. Ifthese adjustments are not used, pins
20 and 23 should be connected as described elsewhere (do not
ground).
OFFSET ADJUSTMENT-Connect the offset potentiometer to pin
20 for voltage output models or pin 15 for current output models and
apply all "1's" to the digital inputs, Adjust the potentiometer until
the analog output is equal to the appropriate value for unipolar or
bipolar output ranges as listed in the Digital Input Coding table,
Pm 15 (I)
Connect
Ato
Connect
Pin 17 to
Connect
Pin 19 to
Connect
Pin 16 to
±10V
±5V
±2,5V
o to +10V
Oto +5V
19
18
18
18
18
15
15
15
21
21
A
N,C,
15
N,C.
15
24
24
24
24
24
DAC85-CBI-1 has an output current of 0 to -2mA (shunted by S,SkO
or ± lmA (shunted by 3,2kO), If desired, the current-output model
can be terminated directly with a resistive load (RL) to provide a
voltage output over a range of ± 2,5V, The full scale outputs will be
as follows:
(S.SkO x RL)
(3,2k{l X RL)
Vo = -2mA (S.SkO + RL) or ± lmA (3.2k{l + RLl
+ 1SV
+ 15V
Pln20(V)~.9M!!
Output
Range
lOkI!
to
100kll
Pm 20 (V)
laOk!!
lOkI!
Pin 15 (I) C)-Wr~--'lMr---=3; to
100k!l
-15V
In order to obtain the best temperature tracking characteristics, it
is suggested that the bulk of the load resistor be made up by paralleling the internal feedback resistors. For example, paralleling the 5k,
3k and 2k resistors gives an equivalent impedance of 9S80, This
impedance in series with an external 210{l resistor yields a voltage
range of ato -2V. External resistors should be good quality metalfilm types with a maximum of 100 ppm/oC temperature coefficient.
DIGITAL INPUT CODING
Digital Input
MSB
Voltage Output
LSB
0000 0000 0000
000000000001
011111111111
100000000000
111111111110
111111111111
7-20
o to
+5V
+4,9988
+4,9976
+2.5000
+2.4988
+0,0012
0,0000
o to
+10V
+9,9976
+9,9951
+5.0000
+4.9976
+0.0024
0,0000
Current Output
±2.5V
±5V
±10V
Oto -2mA
±lmA
+2,4988
+2,4976
0.0000
-0,0012
-2,4988
-2,5000
+4,9976
+4,9951
0.0000
-0.0024
-4.9976
-5,0000
+9.9951
+9.9902
0.0000
-0,0049
-9,9951
-10,0000
-1.9995
-1,9990
-1.0000
-0.9995
-0.0005
0,0000
-0,9995
-0.9990
0,0000
+0.0005
+0,9995
+1.0000
lIJJ
_
DAC87
MICRO NETWORKS
INDUSTRY-STANDARD
MILITARY, 12-Bit
D/A CONVERTERS
DESCRIPTION
FEATURES
• Fully Guaranteed
-55"C to +125°C Operation
• Linearity and Monotonicity
Guaranteed Over Temperature
• 4Jlsec Settling Time
• Low Drift:
Gain ±20ppm/oC Max
Offset ±3ppm of FSR/oC Max
• Small 24-Pin Hermetic DIP
• No +5V Supply Required
• 480mW Maximum
Power Consumption
• Pin-Compatible
DAC85-CBI-V, AD DAC87
• MIL-STD-1772
Qualified Facility
24 PIN SIDE-BRAZED DIP
The DAC87 is a high-performance, TIL-compatible, 12-bit
digital-to-analog converter in a 24-pin, hermetically sealed
ceramic dual-in-line package. The DAC87 is a monolithic
voltage-output D/A complete with an internal reference and fast
output amplifier. It is pin-for-pin compatible with industry standard DAC87 and DAC85/80 D/A converters and guarantees a
4J.tsec output settling time (20V step settling to ±O.5LSB). Other
critical accuracy performance parameters are fully specified and
guaranteed over the entire operating temperature range.
Linearity and monotonicity are guaranteed over temperature,
and total unadjusted error is specified as ±O.3% FSR maximum
over temperature.
The Micro Networks DAC87 has 5 user-selectable output
ranges, a fully short-circuit protected output, and a maximum
power consumption of 480mW. The DAC8l's rugged ceramic
package is hermetically sealed, and for military/aerospace applications, DAC87H/B is available with Environmental Stress
Screening.
DAC87 type 12-bit D/A converters have become the industry
standard for military/aerospace and demanding industrial applications. The DAC87's monolithic design results in improved
reliability. Guaranteed monotonicity over temperature makes the
DAC87 an excellent choice for closed-loop servo systems.
-ri
I
i
1~~5.@!Ql
1215(3086)
.L
i·
.-
i!
_L! ___
:
I
0015(041J I
O.021~
I I
Ir: OE!!Qn~~J i i i .~ 0240 (S-'O)
J
_~
Qq~~i9_~
,
I I
~
~ . --- .--·g~~~f~:~~
_I
L -_ _ _---',
t ·
0120f!051
0600(1524)
0060(152)
....
OQ.q8JQ)lQi
I
I
/..- 0.600 (15 24)
0012 (030)
--.I
Dimensions in Inches
(millimeters)
[LJJ
_
February 1992
MICRO NETWORKS
Copyright©1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-21
DAC87 INDUSTRY-STANDARD MILITARY 12-Bit D/A CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
DAC87
DAC87H, H/B
Storage Temperature Range
+ 15V Supply (+Vcc, Pin 22)
-15V Supply (-Vcc, Pin 14)
Digital Inputs (Pins 1-12)
Output Current
-55°C to + 125°C
PART NUMBER
-25°C to +85°C
-55°C to + 125°C
-65°C to + 150°C
-0,5 to +18 Volts
+0.5 to -18 Volts
-0.5 to +18 Volts
(Note 1)
Standard device is specified for -25°C to +85°C
operation.
Add "H" suffix for specified -55°C to +125°C
operation. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...l
DAC87H/B
Add "/B" suffix to "H" models for Environmental
Stress Screening.------_ _ _ _ _ _ _--I
SPECIFICATIONS (TA = +25°C, ±Vcc= ±15V unless otherwise indicated) (Note 2)
DIGITAL INPUTS
MIN.
Logic Levels: Logic "1"
Logic "0"
+2.0
TYP.
Input Currents: Logic "1" (VIH =+2.4V)
Logic "0" (VIL = +O.4V)
Logic Coding: Unipolar Output Ranges
Bipolar Output Ranges
MAX.
UNITS
+0.8
Volts
Volts
+20
-180
p.A
p.A
Complementary Straight Binary
Complementary Offset Binary
ANALOG OUTPUT
Output Voltage Ranges: Unipolar
Bipolar
Output Impedance (Note 11)
Output Current (Notes 1, 11)
Volts
Volts
Oto +5,Oto +10
±2.5,±5,±10
0.05
0.20
fl
rnA
±V4
± '/2
± 3/.
LSB
LSB
±5
TRANSFER CHARACTERISTICS (Note 3)
Linearity Error: Initial (+25°C)
Over Temperature (Note 4)
Differential Linearity Error
Monotonicity
±V2
LSB
Guaranteed Over Temperature
Total Error, Without Adjustment (Note 5): Initial (+2S°C)
Over Temperature (Note 4)
±0.05
±0.15
±0.1
±0.3
%FSR
%FSR
Unipolar Offset Error (Notes 6, 7): Initial (+25°C)
Over Temperature (Note 4)
Drift (Note 10)
±0.02
±0.04
±1
±0.05
±0.08
±3
%FSR
%FSR
ppm of FSR/OC
Bipolar Offset Error (Notes 6, 8): Initial (+25°C)
Over Temperature (Note 4)
Drift (Note 10)
±0.02
±0.05
±5
±0.05
±0.1
±10
%FSR
%FSR
ppm of FSR/oC
Gain Error (Notes 6, 9): Initial (+25°C)
Over Temperature (Note 4)
Drift (Note 10)
±0.05
±O.IS
±10
±0.1
±0.25
±20
%
%
ppm/oC
3
2
1
4
3
"sec
"sec
"sec
DYNAMIC CHARACTERISTICS
Settling Time to ±O.OI%FSR: 20V Step
10VStep
1 LSB Step (Note 11)
Slew Rate (Note 11)
±10
±12
V/"sec
+6.3
±5
±10
Volts
%
ppm/oC
rnA
INTERNAL REFERENCE
Internal Reference (Note 11): Voltage
Accuracy
Drift
External Current
7-22
2.5
POWER SUPPLIES
MIN.
TYP.
MAX.
UNITS
+14.25
-14.25
+15
-15
+15.75
-15.75
Volts
Volts
±0.02
±0.002
±0.04
±0.004
%FSR/%Supply
%FSR/%Supply
Current Drains: + 15V Supply
-15V Supply
+8
-15
+12
-20
mA
mA
Power Consumption
345
480
mW
Power Supply Range: + 15V Supply
-15V Supply
Power Supply Rejection: + 15V Supply
-15V Supply
SPECIFICATION NOTES:
1. The DACa? is short-circuit protected to ground or either supply.
2. Unless otherwise indicated, listed specifications apply for all DAC87 models.
3. FSR stands for full scale range and is equal to the peak-to-peak voltage of the
selected output range. For the ± 10V output range, FSA is 20 Volts, and 1 LSB
is ideally equal to 4.88mV. For the 0 to + 10V and ± 5V ranges, FSR is 10 Volts,
and 1 LSB is ideally equal to 2.44mV. For the 0 to +5Vand ± 2.5V ranges, FSR
is 5 Volts, and 1 LSB is ideally equal to 1.22mV.
4. DAC87 is specified for -25'C to +85'C operation. DAC87H and DAC87H/B are
specified for -55°C to +125°C operation.
5. This specification applies to both unipolar and bipolar output ranges and is
specified without adjustment. With optional gain and offset adjustment, initial accuracy error can be reduced to ± O.012%FSR( ± 1hLSB).
6. Initial offset and gain errors are adjustable to zero with user-optional, external
trimming potentiometers.
7. Unipolar offset error is defined as the difference between the actual and the ideal
output voltage when configured in a unipolar output range with a digital input of
1111 1111 1111.
8. Bipolar offset error is defined as the difference between the actual and the
ideal output when configured in a bipolar output range with a digital input of 1111
11111111.
9. Gain error is defined as the error in the slope of the converter transfer function.
It is expressed as a percentag. and is equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value forthe full output voltage span
from the 1111 1111 1111 output to the 0000 0000 0000 output.
10. For -25'C to +85'C operation (DAC87), the maximum drift tempcos are the
following: Unipolar offset drift ± 5ppm of FSA/'C
Bipolar offset drift ± 15ppm of FSA/'C
Gain drift ± 30ppm/'C
11. These parameters are listed for reference only and are not tested.
BLOCK DIAGRAM
PIN DESIGNATIONS
~ (24)
MSB
(1)
Bit 2
(2)
Bit 3
(3)
Bit 4
(4)
Bit 5
(5)
Bit 6
(6)
Bit 7
(7)
Bit 8
(8)
Bit 9
(9)
-i
Reference
Control
Circuit
L
(23) Gain Adjust
I
)-
.A
1'0
~
(16) Ref. Input
N.C. (13) 0
Ground (21) 0
~
15V Suppty (14) 0
~
13
(19) 20V Range
(18) 10V Range
(17) Bipolar Offset
,.,.
12
>
Bit 11 (11)
+15V Supply (22) 0
24
Summing
Junction
Bit 10 (10)
LSB (12)
•
PIN 1
(20)
12-Bit
Resistor
Network
and
Current
Switches
Ref. Output
~~
[v
(15) Output
1
2
3
4
5
6
7
8
9
10
11
12
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1 (MSB)
2
3
4
5
6
7
8
9
10
11
12 (LSB)
24
23
22
21
20
19
18
17
16
15
14
13
Reference Out ( + 6.3V)
Gain Adjust
+ 15V Supply ( + Vee)
Ground
Summing Junction
20V Aange
10V Aange
Bipolar Offset
Aeference Input
Analog Output
- 15V Supply ( - Vee)
N.C.
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
bypassing is necessary to obtajn specified accuracies from the
DAC8Z The unit's ground pin (pin 21) should be tied to system analog
ground as close to the package as possible, preferably to a large
analog ground plane beneath the package. Coupling between analog
and digital signals should be minimized to avoid noise pickup. A short
jumper should be used when tying the Reference Output (pin 24) to
the Reference Input (pin 16). Pin 20, the line to the Summing Junc7-23
tion of the output amplifier, is particularly noise susceptible. Care
should be taken to avoid long runs or runs parallel to digital lines when
tying to this pin for output range selection. If optional external offset
and gain adjusting is used, the series resistors should be located as
close to the package as possible, and short conductor runs should
be used.
should be made following warmup, and to avoid interaction, offset
must be adjusted before gain. Multiturn potentiometers with TCR's
of 100ppm/o C or less are recommended to minimize drift with
temperature. Series resistors can be ± 20% carbon composition or
better. If these adjustments are not used, pins 20 and 23 should not
be connected to ground.
For optimum performance and noise rejection, power supplies should
be bypassed with capacitors located as close to the unit as possible. We have found 11" F tantalum capacitors paralleled with 0.011" F
ceramic capacitors to be a cost-effective combination. Single 11"F
ceramic capacitors can be used to save space.
OFFSET ADJUSTMENT-Connect the offset potentiometer as
shown below and apply the digital input 1111 1111 1111. Adjust the offset potentiometer until the output is exactly zero volts for unipolar
ranges and minus full scale for bipolar ranges. See Input Logic
Coding.
+15V
POWER SUPPLY BYPASSING
Pin 220
1
~F
Pin 21 0
I
I
I
1°°1 ~F
Pin 20
-'3W;_ _ _ _
0-0_ _ _ _
r0.Q1
-'----'-0_1
~F
Range of Adjustment= ±0.15%FSR
10M[J
--I---'WV'~---?>~
0-0
J
O.Q1~F
Range of Adjustment= ±0.25%
OUTPUT RANGE SELECTION
Output Range
+5V
o to
±2.5V
±5V
Connect Pin 24 to
16
16
16
16
16
Connect Pin 17 to
21
21
20
20
20
+10V
±10V
Connect Pin 15 to
18
18
18
18
19
Connect Pin 19 to
20
N.C.
20
N.C.
15
Connect Pin 20 to
19
N.C.
19,17
17
17
INPUT LOGIC CODING
Digital Input
Analog Output
LSB
Oto +5V
o to
±2.5V
±5V
±10V
0000 0000 0000
0000 0000 000 1
+4.9988V
+4.9976V
+9.9976V
+9.99S1V
+2.4988V
+2.4976V
+4.9976V
+4.99S1V
+9.99S1V
+9.9902V
011111111111
1000 0000 0000
+2.S000V
+2.4988V
+S.OOOOV
+4.9976V
O.OOOOV
-0.0012V
O.OOOOV
-0.0024V
O.OOOOV
-0.0049V
1111 11111110
111111111111
+0.0012V
O.OOOOV
+0.0024V
O.OOOOV
-2.4988V
-2.S000V
-4.9976V
-S.OOOOV
-9.9951V
-10.0000V
+10V
CODING NOTES
1. For unipolar operation. the coding is complementary straight binary (CSB).
2. For bipolar operation, the coding is complementary offset binary (COB).
3. For FSR=2OV, 1 LSB=4.88mV.
t .. For FSR=10V, 1 LSB=2.44mV.
, For FSR=5V, 1 LSB=I.22mV.
7-24
-15V
+15V
Pin 23
o to
1OOkO
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
below and apply a 0000 0000 0000 digital input. Adjust the gain potentiometer until the output voltage is at its ideal positive full scale value
(+F.S.-1 LSB, see Input Logic Coding).
OPTIONAL OFFSET AND GAIN ADJUSTMENTS-The DAC87 will
operate as specified without additional adjustments. If desired, inputloutput accuracy error can be reduced to ± lhLSB (± 0.012%FSR)
by following the trimming procedures described below. Adjustments
MSB
l
15V
REFERENCE OUTPUT-The DAC87 contains an internal +6.3V
±5% voltage reference, and units are actively laser trimmed to
operate from this reference. Therefore, though the user has the option of using an external reference, for specified operation, the
Reference Output (pin 24) must be connected to the Reference Input (pin 16). If the internal reference is used to drive an external load,
the load current should not exceed 2.5mA.
Pin Connections
-3>~ 1~kO
Ground
1 ~F
Pin 14
+15V
f
-15V
~kO
l00kO
~
DAC88
12-Bit
D/A CONVERTER
with INPUT REGISTER
MICRO NETWORKS
DESCRIPTION
The DAC88 is a 12-bit digital-to-analog converter with a fast,
internal, TTL input register. It is packaged in a hermetically
sealed, ceramic, 24-pin duaf-in-line package ilnd is complete
with internal reference and output amplifier. Three user selectable output ranges are available (0 to +10V, ±5Vand ±10V),
and performance features include the following: fast output settling (7pSec for a 20V change), ±0.1%FSR maximum absolute
accuracy, and ± lhLSB linearity and monotonicity guaranteed
over the full operating temperature range. Maximum power consumption is 730mW.
FEATURES
• Complete With Internal:
Input Register
Output Op Amp
Low-Drift Reference
• ± V2LSB Linearity
and Monotonicity
Guaranteed Over
Temperature
• 40nsec Data Setup Time
• ±O.1% FSR Unadjusted
Absolute Accuracy
• 7pSec Max Settling Time
(20V step to ± V2LSB)
• Small 24-Pin DIP
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
The DAC88 is functionally laser trimmed for linearity, gain and offset, eliminating the need for external potentiometers. Units are
available for three operating temperature ranges (O°C to
+70°C, -25°C to +85°C and -55°C to + 125°C). Linearity and
accuracy are tested 100% and guaranteed both at room and
temperature extremes. For militarylaerospace or harshenvironment commercial/industrial applications, "H/B" models are
available with Environmental Stress Screening while "H/B CH"
models are screened in accordance with MIL-H-38534.
24 PIN DIP
1.230!31.24J
1.100(27.94)
1.270/3U6}
'--------'~
~:;g;:~:lj
t===i~
looo"o~1
I
0012(030)
0.153(3.89)
0183(4.65)
I
;I~
1---1
·;I
The DAC88 is TTL compatible, and its internal input register
facilitates interfacing to microprocessor and minicomputer data
buses. Applications include microprocessor-based data distribution systems, programmable power supplies and servo drivers.
Optional MIL-H-38534 processing and guaranteed linearity and
accuracy specifications over the -55°C to + 125°C temperature
range make the DAC88H/B an excellent choice for military
avionics and fire control systems.
0.019/0.48)
Model
Number
DAC88
DAC88E
DAC88H
DAC88H/B
DAC88H/BCH
Temperature
Range
Input
Coding
Max. Power
Consumption
O°C to +70°C
-25°C to +85°C
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
CSB/COB
CSB/COB
CSB/COB
CSB/COB
CSB/COB
730mW
730mW
730mW
730mW
730mW
.-
0175(445)
0205(5.21)
if
f--O.600(15.24)--..l
Dimensions in Inches
(millimeters)
~
MICRO NETWORKS
February 1992
CopyrighHC)1992
Micro Networks
All rights reserved
324 Clark St.. Worcester, MA 01606 (508) 852·5400
7·25
DAC88 12·Bit D/A CONVERTER with INPUT REGISTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
DAC88
DAC88E
DAC88H, H/B
Storage Temperature Range
Positive Supply (+Vcc, Pin 22)
Negative Supply (-Vcc, Pin 14)
Logic Supply (+Vdd, Pin 13)
Register Enable (Pin 19)
Digital Inputs (Pins 1-12)
ORDERING INFORMATION
PART NUMBER
OOCto +70°C
-25°C to +85°C
-55°C to +125°C
-65 0 Cto +150°C
a to +18 Volts
Oto -18 Volts
-0.5 to +7 Volts
-0.5 to +5.5 Volts
-0.5 to +5.5 Volts
DAC88H/B CH
Standard Part is specified for O°C to +70°C
operation.
----------i
Add "E" suffix for specified -25°C to +85°C
operation.---------------i
Add "H" suffix for specified -55°C to + 125°C
operation. _ _ _ _ _ _ _ _ _ _ _ _ _ _-I
Add "/B" to "H" devices for Environmental Stress
Screening.-----------------'
Add "CH" to "H/B" devices for 100% screening
according to MIL-H-38534.-------------i
SPECIFICATIONS (TA= + 25OC, ±Vcc= ±15V +Vdd=+5V unless otherwise indicated) (Note 1)
DIGITAL INPUTS
MIN.
Logic Levels: Logic "1"
Logic "0"
+2.0
TYP.
Input Currents: Data Inputs: Logic "1" (VIH =+2.4V)
Logic "0" (Vll = +0.4V)
Register Enable: Logic "1" (VIH =+2.4V)
Logic "0" (Vll =+0.4V)
Register Enable (Note 2): Pulse Width
Setup Time Digital Data to Enable
Logic Coding: Unipolar Range
Bipolar Ranges
MAX.
UNITS
+0.7
Volts
Volts
+30
-0.6
+60
-1.2
pA
mA
pA
mA
nsec
nsec
60
40
Complementary Straight Binary
Complementary Offset Binary
ANALOG OUTPUT
Output Voltage Ranges: Unipolar
Bipolar
Output Impedance
Output Current
±4
Oto +10
±5,±10
Volts
Volts
0.5
±5
!l
mA
TRANSFER CHARACTERISTICS (Note 3)
Linearity Error: Initial (+25°C)
Over Temperature (Note 8)
Monotonicity
±v.
± '/2
±V2
LSB
LSB
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Notes 4, 5): Initial (+25°C)
Over Temperature (Note 8)
Zero Error (Notes 4. 6): Initial (+25°C)
Over Temperature (Note 8)
Gain Error (Notes 4, 7)
Gain Drift
±0.05
±0.15
±0.1
±0.3
%FSR
%FSR
±0.025
±0.05
±0.05
±0.1
%FSR
%FSR
±0.1
±10
%
ppm/oC
DYNAMIC CHARACTERISTICS
Settling Time to ± 0.01% for 20V Step
5
Output Slew Rate
7
pSec
±20
V/pSec
+6.3
±2
±10
2.5
Volts
%
ppm/oC
mA
+15.00
-15.00
+5.00
+15.45
-15.45
+5.25
Volts
Volts
Volts
±0.01
±0.001
±0.04
±0.004
%FSR/%Supply
%FSR/%Supply
Current Drain: + 15V Supply
-15V Supply
+5V Supply
+8
-15
+30
+12
-20
+50
mA
mA
mA
Power Consumption
495
730
mW
REFERENCE OUTPUT
Internal Reference: Voltage
Accuracy
Tempco
External Current
POWER SUPPLIES
Power Supply Range: +15V Supply
-15V Supply
+5V Supply
Power Supply Rejection: +15V Supply
-15V Supply
7-26
+14.55
-14.55
+4.75
SPECIFICATIONS
1. Unless otherwise Indicated. listed specifications apply for all DAC88 models.
2 The analog output Will follow its digltailnput when Register Enable IS a logic "0"
Digital Input data will be latched and analog output voltage constant when
Register Enable IS logic "1" The minimum Register Enable pulse Width 10 latch
new digital input data IS 60nsec. See Timing Diagram.
3. FSR stands for full scale range and IS equal to the peak-la-peak voltage of the
selected output range, For the i 10V output range. FSR IS 20 Volts, and lLSB
is Ideally equal to 4.88mV For the a to + lOV and ± 5V ranges. FSR is 10 Volts,
and 1LSB IS ideally equal to 244mV
4 Initial zero and gam errors are adjustable 10 zero with user-optional. external trimming potentiometers.
5. Full Scale Absolute Accuracy Error includes offset. gain. linearity. noise. and all
other errors and (s specified without adjustment. For unipolar output ranges. Full
Scale Absolute Accuracy Error refers to the deviation between the actual and the
Ideal output with an all"O's" digital Input applied For bipolar output ranges. the
spec. refers to the deviation between the actual and the Ideal output with either
all "O's" (positIVe full scale) or all "1's" (negative full scale) applied.
6. Zero error is defined as the difference between the actual and the ideal output
voltage for the Input code which ideally produces 0 Volts out. For the 0 to + 10V
range. zero error is measured with a digital Input of 111111111 1111. For ±5V and
"i" 10V ranges. zero error is measured with a digital Input of 0111 1111 1111.
7. Gain error IS defined as the error in the slope of the converter transfer function.
It IS expressed as a percentage and IS equivalent to the deviation (divided by the
ideal value) between the actual and the ideal value for the full output span from
the 1111 1111 1111 output to the 0000 0000 0000 output.
Listed specifications apply over the O°C fa + 70°C temperature range for standard products. over the ~25°C to +85°C range for "E·' products. and over the
-55°C to +125°C range for ··H" products
BLOCK DIAGRAM
PIN DESIGNATIONS
Register
Enable (191
~-
1
2
3
4
5
6
7
8
9
10
11
12
(24) Ref Output
) (16) Ref Input
tMSB)
(LS5)
Bit
Bit
8.t
Bit
81t
Bit
81t
Bit
Bit
Bit
BIt
Bit
1
2
3
4
5
6
7
8
9
10
11
12
(1)
(21
(3)
(4)
)(17) BIpolar Offset
.j
Ii'
15)
a:
(6)
(7)
(8)
~
(9)
(10)
t11)
112)
£
i
I!
z'
"en
~c
(23) Gain Adjust
'(18) 10V Range
~§
.:u
~~
(20) Summing Junction
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12 (LSB)
24 Ref. Out (+6.3V)
23 Gain Adjust
22 +15V Supply
21 Ground
20 Summing Junction
19 Register Enable
18 10V Range
17 Bipolar Offset
16 Ref. In
15 Analog Output
14 -15V Supply
13 +5V Supply
(15) Analog Output
Ground
.'5V Supply
-15V Supply
.5V Supply
(21 J 0--------+
(22) o--------It>
(14)o--------It>
(13)<>------+
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy from the
DAC88. The units' Ground (pin 21) must be tied to circuit analog
ground as close to the package as possible, preferably through a
large ground plane underneath the package.
Power supplies should be decoupled with tantalum or electrolytic
type capacitors located close to the unit. For optimum performance,
1",F capaCitors paralleled with O.Q1",F ceramic capacitors should
be used.
Coupling between analog and digital signals should be minimized
to avoid noise pickup. Short jumpers should be used when tying
the Reference Output (pin 24) to the Reference Input (pin 16) and
when tying the Bipolar Offset (pin 17) to the Summing Junction (pin
20) for bipolar operation. If external gain and offset adjustments are
to be used, the series resistors should be located as close to the
unit as possible.
potentiometers with TCR's of 100 ppm/oC or less are recommended to minimize drift with temperature. Series resistors can be ± 20%
carbon composition or better. Ifthese adjustments are not used, pins
20 and 23 should not be grounded.
OFFSET ADJUSTMENT- Connect the offset potentiometer as
shown and apply all "1's" to the digital inputs. Adjust the potentiometer until the analog output is equal to zero volts for the unipolar
output ranges or minus full scale for bipolar output ranges.
GAIN ADJUSTMENT- Connect the gain potentiometer as shown
and apply all "O's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the maximum positive voltage for the
chosen output range as shown in the Coding table.
+15V
3.9MlI
REFERENCE OUTPUT-The DAC88 contains an internal
+6.3V ±2% voltage reference, and the units are actively lasertrimmed to operate from this reference. Therefore, though the user has
the option of using an external reference, for specified operation,
the Reference Output (pin 24) must be connected to the Reference
Input (pin 16). If the internal reference is used to drive an external
load, it should be buffered if the load current will exceed 2.SmA.
OPTIONAL GAIN AND OFFSET ADJUSTMENTS-The DAC88 will
operate as specified without external adjustments. If desired,
however, absolute accuracy error can be reduced to ±1LSB by
following the trimming procedure described below. Adjustments
should be made following warmup and, to avoid interaction, the offset adjustment must be made before the gain adjustment. Multiturn
P,n20
1
~l'Ok!!
-15V
OFFSET ADJUST
+15V
10M!!
1
p'n23~1'Ok!l
-15V
GAIN ADJUST
REGISTER ENABLE-When the Register Enable (pin 19) is high
(hold mode) the digital data in the input register will be latched, and
when the Register Enable is low (track mode), the converter's output will follow its input. In order to latch new digital data into' the
register, the Register Enable must go low for a minimum of 60nsec
and digital input data must be valid for a minimum of 40nsec prior
to Register Enable going high again. See Timing Di?gram.
7-27
INPUT REGISTER TIMING DIAGRAM
OUTPUT RANGE SELECTION
Pin Connections
Analog Output
Output Range
Register
Enable
=i_
TSDE
Digital
Input
Data_
TH*
~
Oto +10V
±5V
±10V
Connect Pin 24 to
.16
16
16
Connect Pin 17 to
Connect Pin 15 to
21
18
20
18
20
N.C.
Connect Pin 20 to
N.C.
17
17
INPUT LOGIC CODING
Digital Input
_ _ _ _ _ _ _ _ _ __
MSB
TIMING NOTES:
TMEPW Minimum Enable Pulse Width is 60nsec.
TSDE Minimum Setup Time Digital Data to Enable is 40nsec.
TH
Digital Data Hold Time from Register Enable is Onsec.
Analog Output
a to
LSB
+10V
±5V
±10V
0000 0000 0000
000000000001
+9.9976V
+9.9951V
+4.9976V
+4.9951V
+9.9951V
+9.9902V
011111111111
100000000000
+5.0000V
+4.9976V
O.OOOOV
-0.0024V
O.OOOOV
-0.0049V
111111111110
111111111111
+0.0024V
O.OOOOV
-4.9976V
-5.0000V
-9.9951V
-10.0000V
CODING NOTES:
1. For unipolar operation, the coding is complementary straight binary (CSB).
2. For bipolar operation, the coding is complementary offset binary (COB).
3. For FSR=20V, lLSB=4.88mV.
4. For FSR=10V, lLSB=2.44mV.
MICROPROCESSOR INTERFACING
Interfacing the DAC88 to 8, 12 and 16-bit microprocessors is
simplified by the DAC88's internal 12-bit register. External address
and control decoding will be required, however.
Interfacing to 12 and 10-bit processors is fairly direct and can usually
be accomplished by NAN Ding the desired address lines with the
processor's MEMORY WRITE or I/O WRITE line and using the output to drive the DAC88's Register Enable input. For most processors,
valid data remains on the data bus for a period of time after the
removal of either valid address or control signals. This results in data
being latched into the DAC88 immediately after one of the address
or control signals changes but before valid data goes away.
Interfacing to 8-bit processors is slightly more complicated and an
8-bit external register is needed as shown in the sketch below.
Address decoding must be organized such that the 8-bit intermediate register and the DAC88's internal 12-bit register appear
at two different addresses. The 12 bits of digital data are sent to the
DAC88 via two data transfers. First, the 8 least significant bits of
digital data are written to the intermediate latch. Then, the 4 most
significant bits of digital data are written to the DAC88's 12-bit latch.
The result is that the 4 MSB's on the data bus and the 8 LSB's held
in the intermediate latch are all latched into the DAC88's latch
simultaneously. This technique is called double buffering and it
avoids the analog output slewing to an undesirable state determined
by the LSB's of the new digital data and the MSB's of the previous
digital data.
~
7-28
I
Address and
Control
Decoding
I
I
I
~
DAC88
--
---
Ul
"
III
~
r-
0
r-'---
07
.,
$
iii.1
r-
~l IIIr-
~
iiii~
cbE5l'
r-
~a:
l-
r-
Da
Co-
MICRO NETWORKS
324 Clark St., Worcester. MA 01606 (508) 852-5400
~-~
~
A nalog
0 utput
_
MN370
MN371
MICRO NETWORKS
LOW-POWER, 12-Bit
D/A CONVERTERS
DESCRIPTION
MN370 and MN371 are precision, ultra-low-power, voltageoutput, 12-bit O/A converters. Each is complete with internal
voltage reference and output amplifier; consumes only
120mWof power (maximum); and is packaged in an 18-pin,
hermetically sealed, ceramic dual-in-line.
FEATURES
• Complete D/A Converters:
Internal Reference
Internal Output Amplifier
• Low Power
135mW Maximum
Adjustment Free
• ±1/2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Small 18-Pin DIP
• 0 to +10V (MN371) and
± 10V (MN370) Output
Ranges
MN370 has a bipolar ±10 output range; MN371 has a
unipolar 0 to + 10V output range. Both use functional laser
trimming of thin-film nichrome resistor networks to
guarantee ±O.05% FSR unadjusted absolute accuracy
eliminating the need for gain and offset adjusting potentiometers and periodic recalibration.
MN370 and MN371 are excellent choices for satellite, airborne and remote-site applications that require high
reliability and the precision of a 12-bit O/A converter but are
unable to tolerate the size and power consumption of
conventional designs. Adjustment-free operation and
guaranteed accuracies assure field interchangeability
without the need for recalibration. Units are fully specified for
to +70°C
either -55°C to +125°C ("H" models) or
operation. For military/aerospace or harsh-environment
commercial/industrial applications, "H/B CH" models are fully
screened to MIL-H-38534 in Micro Networks MIL-STO-1772
qualified facility.
• Full Mil Operation
-55°C to +125OC
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
aoc
18 PIN DIP
BLOCK DIAGRAM
0.015(0.38)-,,/r--
0.075(1911
PlN\D~ ~"I'
11:
:
(MN370 Only)
26n
0100(254)
O105'
T
QE!~!
1 027 {26 09)
s:=r
o 480 l1? 191
:*"'0 520 i1:f211-
o 00910_2~1
- -1\.fI/\t- - -,
l
1
0.800(20.32)
--~ lJi 1
001
I
0020(051)
iL~?9J1..9~
~17014J2)
0200(5081
0230(564)
--.-
0012(030)
~
0300(7621
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
LSB
(1)
(2)
(3)
(4)
(5)
(6)
(13)
(14)
(15)
(16)
(17)
(18)
>--CI)
Zw
wI
cr:U
cr:>:::
::J;;:
UCI)
cr:
w",
Ocr:
00
~~
cr:w
~z
cr:
(12) Analog
Output
«-----0(11) Ground
-15VGround
« - - - - - 0 (9) +15V Supply
N/C
~(8)
N/C
~(7)
~(10)
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
May 1988
Copyright©1991
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-29
MN370 MN371 LOW-POWER 12-Bit D/A CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
PART NUMBER - - - - - - - - - - - MN370H/B CH
Select MN370 or MN371 model.
I
Standard part is specified for OOC to +70"C
operation.
Add "H" suffix for specified -55"C to + 125·C
operation.-----_ _ _ _ _ _ _ _ _ _ _..J
- 55·C to + 125·C
Operating Temperature Range
Specified Temperature Range:
MN370, MN371
MN370H, H/B, MN371H, H/B
Storage Temperature Range
+ 15V Supply (+ Vcc , Pin 9)
-15V Supply (- Vcc , Pin 10)
Digital Inputs (Pins 1·6, 13·18)
O·C to + 70·C
-55·Cto +125·C
- 65·C to + 150·C
to +17 Volts
o to -17 Volts
o to + 15 Volts
o
Add "/B" to "H" devices for Environmental
Stress Screening.--------_ _ _ _ _ _....J
Add "CH" to "HIB" devices for 100% screening
according to MIL·H-38534. - _ _ _ _ _ _ _ _ _ _ _--.J
SPECIFICATIONS (TA =+25"<:, ±Vcc= ± 15V unless otherwise indicated)
DIGITAL INPUTS
MIN.
Logic Levels: Logic "1"
Logic "0"
+2.4
TYP.
Input Currents: Logic "1"
Logie "0"
MAX.
UNITS
+0.8
Volts
Volts
+10
-10
p.A
p.A
ANALOG OUTPUTS
-10 to +10
o to +10
Output Range: MN370
MN371
Volts
Volts
5
Output Impedance
Output Load Current
Ohms
rnA
+ 1
TRANSFER CHARACTERISTICS
to +70·C
, Linearity Error (Note 1): O·C
-55· C to +125· C
±
Monotonocity
V-
±
±
LSB
LSB
0;,
0;,
Guaranteed Over Temperature
Absolute Accuracy Error (Notes 2, 3):
+25·C
O·C to +70·C
-55· C to +125· C
± 0.025
±0.05
±0.2
±0.3
%FSR
% FSR
% FSR
35
60
f.l,sec
J,lsec
DYNAMIC CHARACTERISTICS
Settling Time: 10V Step to ±1/2 LSB
20V Step to ±1/2 LSB
25
50
Output Slew Rate
±0.5
V/p.Sec
POWER SUPPLY REQUIREMENTS
+14.55
-14.55
Power Supply Range: +15V Supply
-15V Supply
+15.45
-15.45
Volts
Volts
±0.01
% FSR/% Vs
% FSR/% Vs
Power Supply Rejection: +15V Supply
-15V Supply
± 0.015
t' 0.02
± 0.03
Current Drain Output Unloaded: +15V Supply
-15V Supply
+3
-3
+4
-5
rnA
rnA
Power Consumption
90
135
mW
SPECIFICATtON NOTES:
MN370. we measure ilfor 111111111111, 00000000 0000 andOlllllllllll.
1. Micro Networks tests and guarantees maximum linearity error at room
temperature and both extremes of the specified operating temperature
range.
We perform these measurements at +25°C and at both the high and low
extremes of the specified operating temperature range. These measurements. coupled with our linearity tests, allow us to guarantee that, at
+25°C, the analog output, for any given digital input. will be within
± 0.05% FSR of its ideal value, and that over the entIre operating temperature
range. the analog output will be within ± 0.3 % FSR of Its Ideal value
2. The Absolute Accuracy Error of a voltage output D/A is the difference
between the actual output voltage that appears following the application
of a given digital input code and the ideal or expected output voltage for
that code. Absolute Accuracy Error includes gain, offset, linearity, and
noise errors and encompasses the drifts of these errors when specified
over temperature. For the MN370. we measure the Absolute Accuracy Error
when the digital inputs are 1111 1111 1111 and 000000000000. For the
DIGITAL INPUT
MSB
LSB
0000 0000 0000
000000000001
0111 1111 1111
1000 0000 0000
11111111 1110
111111111111
ANALOG OUTPUT (DC VOLTS)
MN370
MN371
+ 9.9951
+ 9.9902
0.0000
- 0.0049
- 9.9951
-10.0000
+9.9976
+9.9951
+5.0000
+4.9976
+0.0024
0.0000
For the MN370, the coding is Complementary Offset Binary.
For the MN371, the coding is Complementary Straight Binary.
7·30
+15.00
-15.00
3. For a 12 bit converter, 1 LSB corresponds toO.024% FSR. FSR stands for
Full Scale Range and is equivalent to the peak to peak voltage of the
converter's output range. For the ±10V output range, FSR is 20V and
1 LSB = 4.BBmV. For the 0 to +10V output range, FSR is 10V and
1 LSB = 2.44mV.
LAYOUT CONSIDERATIONS - Proper attention to layout
and decoupJing is necessry to obtain specified accuracies.
The unit's ground pin (Pin 11)
+15V
should be connected to sys- Pin90
tem analog ground, preferably
01
0
.
1 ~F
~F
through a large ground plane
beneath the package. Power Pin 11 O>-I+---I+--Ground
supplies should be decoupled
1 ~F
~F
with 1 /IF capacitors paralleled
15V
with 0.01 /IF ceramic capacitors Pin 100
as shown in the diagram.
I
I
I
1
T r°.Q1
MN3000
Series
~
_
MICRO NETWORKS
HIGH-ACCURACY
8-Bit D/A CONVERTERS
DESCRIPTION
FEATURES
• Complete D/A Converters:
Internal Reference
Internal Output Op Amp
• Small 14-Pin DIP
• ±1/2 LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• ± 1/4LSB Zero Error
Over Temperature
• ±1LSB Absolute Accuracy
Over Temperature
• Adjustment-Free
• Full Mil Operation
-55"C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
'O I'
I
14 PIN DIP
0015(0.38)..,j1-
PIN
f89
0,062(2.08)
11-
°o~:~:
:
I
The MN3000 Series are 8-bit, voltage-output, digital-to-analog
converters that offer high accuracies, particularly around
zero, and adjustment-free operation. Each unit contains an
internal reference and output amplifier and is packaged in a
14-pin, ceramic, hermetically sealed dual-in-line package.
Units are available for either ooe to + 70 0 e or - 55 °e to
+ 125 °e ("H" models) operation. Functional laser trimming
of our own ultra-stable thin-film resistor networks eliminates
the need for gain and offset adjustments and allows us to
guarantee the following over the entire operating temperature range: ± Vz LSB linearity error, ± % LSB zero error and
± 1 LSB unadjusted full scale absolute accuracy error.
Four output voltage ranges are available (MN3000, 0 to -10V;
MN3001, ±5V; MN3002, 0 to +10V; MN3006, ±10V), and all
devices operate from ± 15V supplies consuming a maximum of
660mW. For military/aerospace or harsh-environment commercial/industrial applications, "H/B eH" models are fully screened
to MIL-H-38534 in Micro Networks MIL-STD-1772 qualified
facility.
MN3000 Series D/A's are excellent choices for servo and
other applications requiring high accuracy and repeatability
around zero. In many cases, their excellent accuracies allow
them to be used as cost-saving replacements for higherresolution converters. Their completeness, small size,
low weight, guaranteed accuracy and thin-film reliability
make them excellent choices for military and aerospace
applications.
0.770(1956)
~ O.48o.t!b!ID1
n
0.520(13.21)
0.009(0.23)
0012(030)
0126(320)
{;I~
H
0.020(0.51)
~172(4.37)~200(5.08)
0.230(5.84)
T
~ ..j
0.300(7.62)
Dimensions in Inches
(millimeters)
[1JJ
_
May 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-31
MN3000 SERIES HIGH-ACCURACY 8-Bit D/A CONVERTERS
ORDERING INFORMATION
PART N U M B E R - - - - - - - - - - - - MN300XH/B CH
ABSOLUTE MAXIMUM RATINGS:
Operating Temperature
O°C to +70°C
-55°C to +125°C ("H" Models)
-65°C to +150°C
Storage Temperature
+18 Volts
+15V Supply (Pin 9)
-18 Volts
-15V Supply (Pin 7)
Digital Inputs (Pins 1-4, 11-14)
-0.5 to +15 Volts
operation.
Add "H" suffix for specified -55°C to +125°C
operation.
------------'
Add "/B" to "H" devices for Environmental
Stress Screening. - - - - - - - - - - - - - - - - '
Add "CH" to "H/B" devices for 100% screening
according to MIL-H-38534. _ _ _ _ _ _ _ _ _ _ _ _ _...J
"""r'I"t:'.6T'ON!l IT" = 25°C, SUDDtv Vntt,,'l". +1~V_ unless otherwise specified).
.- _.
- - _ ..
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "0"
I
Select model (MN3000, MN3001, etc,)
Standard Part is specified for OOC to + 70°C
MIN.
TYP_
MAX.
2.0
0.8
40
- 1
Input Currents: Logic "1"
Logic "0"
UNITS
Volts
Volts
p.A
rnA
ANALOG OUTPUTS
o to
-5 to
o to
-10 to
Output Voltage Range: MN3000
MN3001
MN3002
MN3006
Output Impedance
Output Current
-10
+5
+10
+10
Volts
Volts
Volts
Volts
Ohms
rnA
0.5
± 4
TRANSFER CHARACTERISTICS
Linearity Error (Note 1): O°C to +70°C
-55°C to +125°C
Monotonicity
±
''\
± \I,
± \I,
LSB
LSB
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Notes 2, 3):
+25°C
-55°C to +125°C (Note 4)
±
'I,
±
'h
± 1
Zero Error (Notes 2, 3): +25°C
-55°C to +125°C (Note 4)
±
Unipolar Offset Error (Notes 2, 3)
MN3000: +25°C
-55°C to +125°C (Note 4)
MN3002: +25°C
-55°C to +125°C (Note 4)
±
'I,
'I,
±
'I,
v..
LSB
LSB
±
v~
'I,
'I,
LSB
LSB
LSB
LSB
± 'I,
± 1
LSB
LSB
±
± 1
±
'I,
±
±
Bipolar Offset Error (Notes 2, 3) MN3001, MN3006:
+25°C
-55°C to +125°C (Note 4)
± \I,
Offset Drift: MN3002
MN3000. MN3001, MN3006
1:
Gain Error (Note 2)
Gain Drift
± 0.1
±20
LSB
LSB
2
±10
ppmofFSRfOC
ppmofFSRfOC
%
ppm/oC
DYNAMIC CHARACTERISTICS
Settling Time: 10V Step to ±1/2 LSB
20V Step to ±1/2 LSB
Output Slew Rate
23
46
0.5
30
60
p.Sec
p.Sec
Volts/MSec
POWER SUPPLY REQUIREMENTS
Power Supply Range: +15V Supply
-15V Supply
+15.00
-15.00
+15.45
-15.45
Volts
Volts
Power Supply Rejection (Note 5): +15V Supply
-15V Supply
±0.01
±0.015
Current Drain:, Output Unloaded (Note 6): +15V Supply
-15V Supply
17
-17
22
-22
rnA
rnA
510
660
mW
Power Consumption
SPECIFICATION NOTES:
1. Micro Networks tests and guarantees maximum Linearity Error at room
temperature and at both extremes of the specified operating temperature
range.
2. See the Absolute Accuracy Error section on Page 3 for an explanation of
how Micro Networks Corporation tests and specifies Full Scale Absolute
Accuracy. Zero, Offset, and Gain Errors.
3. One LSB for an 8 bit converter corresponds to 0.39% FSR. FSR stands for
Full Scale Range and is equal to the peak to peaK vOltas;c vf the converter's
7-32
+14.55
-14.55
% FSR I % Vs
% FSR I % Vs
output range. For the MN3006, FSR is equal to 20V and 1 LSB is equal to
18mV. For the MN3000, MN3001, and MN3002, FSR is equal to 10V and
1 LSB is equal to 39mV.
4. For Commercial Models, this specification applies over the O°C to +70°C
temperature range. See Ordering Information.
5. The MN3000 Series will operate over a power supply range of ±14V to
±18V with reduced accuracy.
PIN DESIGNATIONS
BLOCK DIAGRAM
(MN3000!1,6)
•
PIN 1
- - ---'VWv- - --,
14
I
I
MSB
(1)
Btl2
(2)
Bit3
(3)
Bil4
(4)
Bit 5
(11)
Bit 6
(12)
Bit 7
(13)
LSB
(14)
"
f-
z
UJ
a:
a:
If)
UJ
I
U
f-
:::J ~
U If)
a:
0
a: ;;:
N
f-
f-
Z
--6---0 (5)
-al a:
UJ
:s
Analog
Output
1
2
3
4
5
6
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Analog Output
Ground
7 -15V Supply
-=
+15V Supply (9)0
~
--IIi---r+-T
LAYOUT CONSIDERATIONS - Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN3000 Series. The units' two Ground pins (Pins
6 and 8) should be tied together as close to the unit as
possible and both connected to system analog ground,
preferably through a large analog ground plane beneath the
-
-15V
DIGITAL INPUT CODING
MSB
LSB
ANALOG OUTPUT (DC VOLTS)
11111111
1111 1110
1000 0000
01111111
0000 0001
0000 0000
MN3000
MN3001
MN3002
MN3006
0.000
-0.039
-4.961
-5.000
-9.922
-9.961
+5.000
+4.961
+0.039
0.000
-4.922
-4.961
+9.961
+9.922
+5.000
+4.961
+0.039
0.000
+10.000
+9.922
+0.078
0.000
-9.844
-9.922
~
_
MICRO NETWORKS
324 Clark S\., Worcester, MA 01606 (508) 852-5400
7-34
Ground
rO.0 1"F
l"F
Pin 7 c
DIGITAL INPUT
APPLICATIONS INFORMATION
+15V
rO.0 1"F
l"F
Pins 6,
I
MN3003
lJJ
_
Series
DESCRIPTION
The MN3003 Series are 10-bit, voltage-output, digital-toanalog converters. Each unit is complete with internal
reference and output amplifier and is packaged in a 16-pin,
ceramiC, hermetically sealed dual-in-line package.
Units are available for either 0 °C to + 70°C or - 55 °C to
+ 125°C ("H" models) operation, and all devices are
adjustment-free. Functional laser trimming of our own thinfilm, nichrome resistor networks eliminates the need for external gain and offset adjustments and user calibration. The
excellent stability and tracking of these resistors allows us
to guarantee ± Y2 LSB linearity and 10-bit monotonicity over
the entire operating temperature range. Zero error is
guaranteed to be less than ± 1 LSB over the entire operating
temperature range.
Four output voltage ranges are available (MN3003, 0 to -10V;
MN3004, ±5V; MN3005, 0 to +10V; MN3007, ±10V), and all
devices operate from ±15V supplies consuming a maximum of
585mW. For military/aerospace or harsh-environment commercial/industrial applications, "H/B CH" models are fully screened
to MIL-H-38534 Micro Networks MIL-STD-1772 qualified facility.
FEATURES
• Complete DIA Converters:
Internal Reference
Internal Output Amplifier
• Small 16-Pin DIP
• ± 1/2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Adjustment-Free
• Full Scale Absolute
Accuracy Error ±1LSB
• ±1LSB Zero Error
Over Temperature
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
'Of"I)\-
MN3003 Series D/A converters are widely used in such applications as medical electronics, industrial control systems
and automatic test equipment. They are excellent choices
for servo and control applications that require tight zero
error. Their small size, low weight, inherent reliability and
adjustment-free operation make them excellent choices for
a wide variety of military and aerospace applications.
16 PIN DIP
0.015(0.38)11-
PIN
O.082(2.08~
O'91':~21::':
9.,870(22.10)
0.925(2350)
~
n
0,46(1(12.19)
i-0.520 (13.21)
0.009 (0.23i
0012(030)
HIGH-ACCURACY
10-Bit D/A CONVERTERS
MICRO NETWORKS
0700"",)
~ -td~
0.020 (0.51)
0.230(5.84)
!
~ ~
0300(7.62)
Dimensions in Inches
(millimeters)
[1D
_
,
"
f
J-1~172(437)O.200(5.08)
.0'18(3.00)
I~.·;
-
May 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852·5400
7-35
MN3003 SERIES HIGH-ACCURACY 10-Bit D/A CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS:
O°C to +70°C
Operating Temperature
-55°C to +125°C ("H" Models)
-65°C to +150°C
Storage Temperature
+18 Volts
+15V Supply (Pin 10)
-18 Volts
-15V Supply (Pin 8)
-0.5 to +15 Volts
Digital Inputs (Pins 1-5, 12-16)
SPECIFICATIONS (TA
~
PART NUMBER - - - - - - - - - - - - MN300XH/B CH
Select model part number (MN3003, MN3004, etc.) - _ _.....1
Standard Part is specified for DoC to +70°C
operation.
Add
"H" suffix
-55°C
to_
+125°C
operation.
_for
_ specified
____
__
_ _ _ _ _ _ _--'
Add "/B" to "H" devices for
Environmental Stress Screening.------_ _ _ _-'
Add "CH" to "H/B" devices for 100% screening
according to MIL-H-38534.--------------'
Contact factory for availability of CH device types.
25°C, Supply Voltages 1:15V, unless otherwise specified).
DIGITAL '''''PUTS
Logic Levels: Logic "1"
Logic "0"
MIN.
TYP.
MAX.
2.0
0.8
Input Currents: Logic "1"
Logic "0"
40
- 1
UNITS
Volts
Volts
"A
mA
ANALOG OUTPUTS
Output Voltage Range: MN3003
MN3004
MN3005
MN3007
Output Impedance
Output Current
a to -10
-5 to +5
a to +10
-10 to +10
Volts
Volts
Volts
Volts
0.5
Ohms
mA
1: 4
TRANSFER CHARACTERISTICS
Linearity Error (Note 1): O°C to +70°C
-55°C to +125°C
Monotonicity
1:
~
±. 1h
1: 'h
LSB
LSB
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Notes 2,3):
+25°C
-55°C to +125'C (Note 4)
1: 0.025
1: 0.2
±0.1
1: 0.4
%FSR
%FSR
Zero Error (Notes 2. 3): +25°C
-55°C to +125'C (Note 4)
1: 0.025
:t 0.05
±0.1
1: 0.1
%FSR
%FSR
Unipolar Offset Error (Notes 2, 3)
MN3003: +25°C
-55°C to +125°C (Note 4)
MN3005: +25'C
-55°C to +125'C (Note 4)
:t
1:
1:
1:
0.025
0.2
0.025
0.05
±0.1
:t 0.4
±O.l
:t 0.1
%FSR
%FSR
%FSR
%FSR
Bipolar Offset Error (Notes 2, 3) MN3004, MN3007
+25°C
-55°C to +125°C (Note 4)
:t 0.025
1: 0.2
±0.1
1: 0.4
%FSR
%FSR
Offset Drifl: MN3005
MN3003, MN3004, MN3007
:t 2
:tl0
Gain Error (Note 2)
Gain Drift
1: 0.1
1:20
ppm of FSR/'C
ppm of FSR/o C
%
ppm/'C
DYNAMIC CHARACTERISTICS
23
46
0.5
Settling Time: 10V Step to :t1/2 LSB
20V Step to :t1/2 LSB
Output Slew Rate
30
60
"Sec
"Sec
Volts/"Sec
POWER SUPPLY REQUIREMENTS
+15.00
-15.00
+15.45
-15.45
Power Supply Rejection (Note 5): +15V Supply
-15V Supply
1: 0.005
1: 0.01
1: 0.015
1: 0.03
Current Drain, Output Unloaded: +15V Supply
-15V Supply
13
-17
17
-22
rnA
rnA
Power Consumption
450
585
mW
Power Supply Range: +15V Supply
-15V Supply
SPECIFICATION NOTES:
1. Micro Networks tests and guarantees maximum Linearity Error at room
temperature and at both extremes of the specified operating temperature
range.
2. See the Absolute Accuracy Error section on Page 3 for an explanation of
how Micro Networks Corporation tests and specifies Full Scale Absolute
Accuracy, Zero, Offset, and Gain Errors.
One LSB for a 10 bit converter corresponds to 0,1% FSR. FSD ,t:mds for
7-36
+14.55
-14.55
Volts
Volts
% FSR I%Vs
% FSR 1 % Vs
Full Scale Range and is equal to the peak to peak voltage of the converter'S
output range. For the MN3007, FSR is equal to 20V and 1 LSB is equal to
20mV. For the MN3003, MN3004, and MN300S, FSR is equal to 10V and
1 LSB is equal to 10mV.
4. For Commercial Models, this specification applies over the DOC to +70°C
temperature range. See Ordering Information.
5. The MN3003 Series will operate over a power supply range of ±14V to
±18V with reduced accuracy.
PIN DESIGNATIONS
BLOCK DIAGRAM
(MN3003/4/7)
•
16
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Bit 5
Analog Output
7 Ground
8 -15V Supply
16
15
14
13
12
11
10
- - JI/tN'- - --,
PIN 1
I
MSB (1)
(2)
Bit 2
(3)
Bit3
(4)
Bit4
Bit 5 (5)
Bit 6 (12)
Bit 7 (13)
Bit8 (14)
Bit 9 (15)
LSB (16)
"a:
f- rJl
Z W
~, ~f-
a:
a:
f- Z
wI
U
f-
:::J~
U
rJl
a:
w
>-~-O(6)
Analog
Output
iii a:
oW
~
0
o
«..J
..;;(_____0(10) +15V Supply
E(---0(8)
-15V Supply
..;;(,----0 (9) Ground
";;(---0(7) Ground
EE-----"O(ll) N/C
1
2
3
4
5
6
Bit 10 (LSBI
Bit 9
Bit 8
Bit 7
Bit6
N/C
+15V Supply
9 Ground
ANALOG
ABSOLUTE ACCURACY ERROR
The Absolute Accuracy Error of a voltage output D/A converter is the difference between the actual, unadjusted, output voltage that appears following the application of a given
digital input code and the ideal or expected output voltage
for that code. This difference is usually expressed in LSB's
or %FSR (see Note 3 above). Absolute Accuracy Error
includes gain, offset, linearity, and noise errors and encompasses the drifts of these errors when specified over
temperature.
For the MN3003 Series converters with unipolar output
ranges (MN3003, MN3005), Micro Networks tests Absolute
Accuracy Error at the zero and full scale outputs. For the
units with bipolar output ranges (MN3004, MN3007)), we
test both the positive and negative full scale outputs as well
as the zero volt output. We perform these tests at +25°C
and at the high and low extremes of the specified operating
temperature range. The errors appear in the specification
table as the Full Scale Absolute Accuracy and Zero Errors.
EXAMPLE: For the MN3007H (±10V output range, -55°C to
+125° C), the expected output for a 00000 00000 digital input is -9.980V, the expected output for a 01111 11111 digital
input is zero volts, and the expected output for a 11111 11111
digital input is +10.000V. Micro Networks measures all three
actual, unadjusted, output voltages at +25°C, -55°C, and
+125°C. We guarantee that when the digital input is all "1's"
or all "O"s, the output will be at its ideal positive or negative
full scale value ±20mV (±0.1%FSR) at +25°C and ±80mV
(±O.4%FSR) at -55° C and +125° C. We guarantee that when
the digital input is 01111 11111, the output will be zero volts
±20mV (±0.1%FSR) at +25°C and zero volts ±20mV
(±0.1 %FSR) at -55° C and +125° C. These limits are summarized in the two sketches below where the MN 3007 digital
input/analog output transfer function is shown as a dotted
line, and the Absolute Accuracy limits are indicated with
closed lines.
Unipolar and Bipolar Offset Error are both Absolute Accuracy Errors. Their definitions differ with respect to where
along the converter's digital-inputlanalog-output transfer
function the errors are to be measured, i.e., different analog
output errors are measured at different digital input codes.
OFFSET ERROR - For the MN3003 Series, Offset Error is
the Absolute Accuracy Error measured when the digital
input is 00000 00000. For the MN3005, Offset Error tells how
+loo:~~IPUT
+10.000V
+
9.990V
DIGITAL
000001-10-00-0-0-_<~-7'''l-7_LO-.O--:C00:::0C:-00=---""\I--7.L-f-_70L.0-i2·~v-111'-1 i~i,~T
01111 1111 1
- 9.900V
1
+- 9.980V
I
!-10060V
I
ABSOLUTE ACCURACY -55°C.' 125"C
7-37
accurate the converter will be when its output is supposed
to be zero volts. For this converter, Offset Error is the same
as Zero Error discussed above. For the MN3003, MN3004,
and MN3007, Offset Error tells how accurate the converters
will be when their outputs are supposed to be at their minus
full scale values. For these converters, Offset Error is
equivalent to Full Scale Absolute Accuracy Error.
It is redundant to specify Bipolar and Unipolar Offset Errors
after giving Full Scale Absolute Accuracy and Zero Errors
as described above. We have provided the offset specifications to simplify comparing the MN3003 Series to other
10 bit D/A:s. Be sure you clearly understand each manufacturer's specification definitions before you compare converters solely on a data sheet basis.
If the grounds cannot be tied together and must be run
separately, a non-polarized 0.01 f.1.F bypass capacitor should
be connected between pins 7 and 9 as close to the package as
possible and wide conductor runs employed.
Power supplies should be decoupled with ta"talum or
electrolytic type capacitors located as close to the MN3003
as possible. For optimum performance and noise rejection,
1f.1.F capacitors paralleled with 0.01f.1.F ceramic capacitors
should be used as shown in ihe diagram below.
GAIN ERROR - Gain Error is the difference between the
ideal and the measured values of a converter's full scale
range (minus 1 LSB). See Note 3 above. It is a measure of
the slope of the converter's transfer function. Gain Error is
not a type of Absolute Accuracy Error, but it can be calculated using two Absolute Accuracy Error measurements.
It is equivalent to the Absolute Accuracy Error measured for
the 11111 11111 digital input minus that measured for the
00000 00000 digital input, and it is usually expressed as a
percentage.
See the Converter Tutorial Section of the Micro Networks'
Product Catalogue for a complete discussion of converter
specifications.
DIGITAL INPUT CODING
ANALOG OUTPUT (DC VOLTS)
DIGITAL INPUT
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS - Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN3003 Series. The units' two Ground pins (Pins
7 and 9) should be tied together as close to the unit as possible
and both connected to system analog ground, preferably
through a large analog ground plane beneath the package.
[1JJ
_
MSB
LSB
MN3004
MN3005
MN3007
0.000
-0.010
-4.990
-5.000
-9.980
-9.990
+5.000
+4.990
+0.010
0.000
-4.980
-4.990
+9.990
+9.980
+5.000
+4.990
+0.010
0.000
+10.000
+9.980
+0.020
0.000
-9.960
-9.980
11111 11111
11111 11110
1000000000
0111111111
0000000001
0000000000
MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852-5400
7-38
MN3003
l1JJ
_
MN3008
MN3009
HIGH-SPEED,8-Bit
D/A CONVERTERS
MICRO NETWORKS
DESCRIPTION
MN3008 and MN3009 are very fast, complete, voltageoutput, 8-bit digital-to-analog converters in dual-in-line
packages. Both devices include an internal voltage
reference and output amplifier, and both are packaged in
hermetically sealed, 16-pin, ceramic DIP's,
Output settling time to ± % LSB is guaranteed to be less
than 11lsec for a full scale (4V) change.
Models are available for either O°C to +70°C or -55°C to
+125°C ("H" models) operation, For military/aerospace or
harsh-environment commercial/industrial applications, "H/B
CH" models are fully screened to MIL-H-38534 in Micro
Networks MIL-STD-1772 Qualified Facility.
FEATURES
• 1!'5ec Maximum Settling Time
(Full Scale Step to ± 1/2LSB)
• Complete D/A Converters:
Internal Reference
Internal Output Amplifier
• ±1/2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Small 16-Pin DIP
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
Offering the inherent stability of thin-film hybrid construction and guaranteed performance over temperature,
MN3008 and MN3009 are ideal choices for applications
where space, weight and size are at a premium. Typical applications include avionics and fire control systems, highspeed function generators and graphic displays.
BLOCK DIAGRAM
9
REF.
(MN3009 ONLY)
-
-
-..A/\J\!'- - - - -,
I
}
I
I
16 PIN DIP
Q,015 (0 36) ~
PlNO'
n
~t@}.
0.012 (O,3D)
0 o~~
fBI'}~~:,:
'1-
r _l
Q.480 (12.19)1
0520(13.21)
f-
~,QQl
~,172
(4.37)
,-t;L~
I
I
MSB
(11
Bi12
(2)
Bil3
(3)
Bit 4
(4)
Bil5
(5)
Bit 6
(6)
BiI?
(7)
LSB
(10)
+ 15V
Supply (16) O--~
-E<--~O
:>
.....
""~--O
(9) NIC
?
""""0.----0
(13) NIC
r
l)
f-'::
iiii:
",'"
«
is
')-+----D
(14)
Analog
Output
0020(0.51)
H
Q_.?QQJ§..OBl
0.230(5.84)
.- 15V Supply (11)
0
Ground (12) 0
T
(8) N}C
..
E:'----~O (15) NIC
0.300 (762)
Dimensions in Inches
(millimeters)
[1JJ
_
May 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
7·39
MN3008 AND MN3009 HIGH·SPEED 8·Bit D/A CONVERTERS
ORDERING INFORMATION
PART NUMBER - - - - - - - - - - - MN3008H/B CH
ABSOLUTE MAXIMUM RATINGS
O'C to + 70'C
- 55'C to + 125'C ("H" Models)
- 65'C to + 150'C
+18 Volts
-18 Volts
- 0_5 to + 15 Volts
Operating Temperature
Storage Temperature
+ 15V Supply (Pin 16)
-15V Supply (Pin 11)
Digital Inputs (Pins 1-7, 10)
SPECIFICATIONS ITA
=25°C, Supply Voltages
------------J
Select MN3008 or MN3009.
Standard Part is specified for O°C to +70°C
operation.
Add "H" suffix for specified -55°C to + 125°C
operation.
_ _ _ _ _ _ _ _..J
Add "/B" to "H" devices for Environmental
Stress Screening.
Add "CH" to "H/B" devices for 100%
screening according to MIL-H-38534.-----------I
----------1
:!:15V, unless otherwise specified)_
MIN_
DIGITAL INPUTS
TYP_
MAX_
UNITS
Volts
Volts
2.0
Logic Levels: Logic "1"
Logic "0"
0.8
p.A
rnA
40
-1.0
Input Currents: Logic "1"
Logic "0"
ANALOG OUTPUTS
o
Output Voltage Range: MN3008
MN3009
Volts
Volts
to +4
-2 to +2
Ohms
rnA
0.5
Output Impedance
Output Load Current
±3
TRANSFER CHARACTERISTICS
Linearity Error (Note 1): O'C to + 70'C
- 55'C to + 125'C "H" Models
±V4
±V2
±1f2
LSB
LSB
Absolute Accuracy Error (Notes 2,3): + 25'C
O'C to + 70'C
- 55'C to + 125'C "H" Models
±0.1
±0.2
±0.5
±0.4
±0.4
± 1.0
% FSR
% FSR
% FSR
0.5
30
1.0
p.Sec
V/p.Sec
DYNAMIC CHARACTERISTICS
Settling Time (Full Scale Change to ± V. LSB)
Output Slew Rate
POWER SUPPLY REQUIREMENTS
Power Supply Range: + 15V Supply
-15V Supply
+ 14.55
-14.55
Power Supply Rejection: + 15V Supply
-15V S'Jpply
Current Drain, Output Unloaded: + 15V Supply
-15V Supply
Power Consumption
+ 15.00
-15.00
+ 15.45
- 15.45
Volts
Volts
±0.01
±0.02
±0.02
±0.04
% FSR 1% Vs
% FSR 1% Vs
15
-18
25
- 25
rnA
rnA
495
750
mW
SPECIFICATION NOTES:
1. Micro Networks tests and guarantees maximum linearity error at room
temperature and at both extremes of the specified operating temperature range.
2. The Absolute Accuracy Error of a voltage output DIA is the difference
belween Ihe actual outpul voltage that appears following the applicalion of a given digital inpul code and the ideal or expected outpul voltage for that code. Absolute Accuracy Error includes gain, offset, linearity, and noise errors and encompasses the drifts of these errors when
specified over lemperature. For the MN3008 and MN3009, Ihe Absolute
Accuracy Error specification applies over the converters' entire output
range. We tesl Absolule Accuracy Error al both endpoints of the
MSB
LSB
11111111
11111110
10000000
01111111
00000001
00000000
Full Scale Range and is equal to Ihe peak to peak voltage of the converters output range. For Ihe MN3008 and MN3009, FSR equals 4V. and 1
LSB
15.6mV.
=
LAYOUT CONSIDERATIONS
DIGITAL INPUT CODING
DIGITAL INPUT
MN3008's output range and at both endpoints and the midpoint of the
MN3009's output range. This lesling, coupled with our linearity testing.
allows us to guarantee that, from aoe to + 70°C, any analog output will
be within ± O.4%FSR (± 1 LSB) of ils ideal level and that. from - 55'C to
+125°e, any analog output will be within ±1.0%FSR of its ideal level.
See Note 3.
3. For an 8 bit converter, 1 LSB corresponds to 0.39% FSR. FSR stands for
ANALOG OUTPUT (DC VOLTS)
MN3008
MN3009
+3.984
+3.969
+2.000
+1.984
+0.016
0.000
-1.984
-1.969
0.000
+0.016
+1.984
+2.000
Proper attention to layout and decoupling is necessary to obtain specified accuracies from the MN3008 and MN3009. The
units' Ground (Pin 12) should be tied to system analog ground
as close to the package as pOSSible, preferably through a
large ground plane beneath the package. Power supplies
should be decoupled with tan+ 15V
talum or electrolytic type ca- Pin 16 0
pacitors located close to the
1/IF
001 IIF
unit. For optimum noise rejection, 1 I'F capacitors parallel
Pin 12 0
Ground
with 0.Q1 I'F ceramic capacitors should be used as shown
1 ,F
"F
in the adjacent diagram.
I
IT ITom
Pin11
7-40
1
0
-
-
-15V
MN3014
UJJ
_
HIGH-SPEED
8-Bit
D/A CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
MN3014 is a complete, high-speed (2.5{tsec), adjustment-free,
8-bit digital-to-analog converter. It contains an internal reference
and output amplifier and is housed in a 16-pin, hermetically
sealed, ceramic dual-in-line package. MN3014 is available for
either O°C to +70°C or -55°C to +125°C operation and
features the following: 570mW maximum power consumption,
4 user-selectable output ranges, ±1/2 LSB linearity guaranteed
over temperature, ± 1/2LSB absolute accuracy guaranteed at
+25°C and ±2LSB's guaranteed over temperature. MN3014
settles to within ±1/2LSB for a 20 Volt step in 2.5{tsec maximum. For military/aerospace or harsh-environment commercial/industrial applications, MN3014H/B CH is fully screened to
MIL-H-38534 in Micro Networks MIL-STD-1772 qualified facility.
• Complete D/A Converter:
Internal Reference
Internal Output Op Amp
• Small 16-Pin DIP
• 2.5 ",sec Max Settling Time
(20V Step to ±1/2lSB)
• ±1/2lSB linearity and
Monotonicity Guaranteed
Over Temperature
• ±1/2lSB Absolute Accuracy
• Full Mil Operation
-55°C to +125°C
• Mll-H-38534 Screening
Optional. Mll-STD-1772
Qualified Facility
MN3014 was deSigned for applications in which adjustment-free
operation and fast settling time are required and where space,
weight and size are at a premium. Use of these units minimizes
design and purchasing time and assures field interchangeability
without the need for adjustment or recalibration.
BLOCK DIAGRAM
16 PIN DIP
I'I"
o~
l
---*-----0(14) Analog Output
Bit 3 (3)
Bit 4 (4)
Bit 5 (5)
8 BIT
D/A
a,t 6 (6)
-=-
6.3 Kll
.--'V'./v---G (10)
Bit 7 (7)
1----------1>---'vv\r--Q (9)
LSB (8)
Offset
Offset
6.3 Kll
0200 ,SOB)
0230(584)
t
1-I
o
'15V Supply (16)~
-15V Supply
(11)~
Ground
(12)~
300 (762)
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
May 1988
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-41
MN3014 HIGH·SPEED a·Bit D/A CONVERTER
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
O'C to +70'C
-55'C to +125'C ("H" Models)
Storage Temperature
-65'C to +150'C
+15V Supply (Pin 16)
+18 Volts
-15V Supply (Pin 11)
-18 Volts
Digital Inputs (Pins 1-8)
-10 to +18 Volts
PART NUMBER - - - - - - - - - - - - MN3014H/B CH
Standard part is specified for O'C to +70°C
operation.
Add "H" for specified -55°C to +125'C
operation. - - - - - - - - - - - - - - - - - . . . . . . /
Add "/B" to "H" models for Environmental
Stress S c r e e n i n 9 . - - - - - - - - - - - - - - - -......
Add "CH" to "/B" models for 100%
screening according to MIL-H-38534.----------......
SPECIFICATIONS (TA = 25' C, Supply Voltages ±15V, unless otherwise specified)_
MIN_
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "0"
TYP_
MAX_
UNITS
0.8
Volts
Volts
2.0
10
10
Input Currents: Logic "1" (Vin = 2.0 to +18 Volts)
Logic "0" (Vin = -10 to +0.8 Volts)
p.A
p.A
ANALOG OUTPUTS
o to +10, 0 to -10
Unipolar Output Ranges
Bipolar Output Ranges
Volts
Volts
±5, ±10
n
0.5
Output Impedance
Output Load Current
rnA
± 4
TRANSFER CHARACTERISTICS
Linearity Error (Note 1): O°C to +70°C
-55'C to +125°C
± %
Monotonicity
±
±
Y,
Y,
LSB
LSB
Guaranteed Over Temperature
Full Scale Absolute Accuracy Error (Notes 2, 3):
+25'C
-55°C to +125'C (Note 4)
± %
Zero Error (Note 5): +25' C
-55'C to +125°C (Note 4)
± %
± 'f,
±2
± y,
± 1
LSB
LSB
LSB
LSB
DYNAMIC CHARACTERISTICS
Settling Time (20 volt change to ±1/2 LSB): MN3014
2.5
Output Slew Rate: MN3014
20
p.Sec
V/p.Sec
POWER SUPPLIES
Power Supply Range: +15V Supply
-15V Supply
+14.55
-14.55
+15.45
-15.45
Volts
Volts
Power Supply Rejection (Note 6): +15V Supply
-15V Supply
± 0.03
Current Drain, Output Unloaded: +15V Supply
-15V Supply
18
-10
24
-14
rnA
rnA
Power Consumption
420
570
mW
and 0000 0000 for the bipolar ranges (See Note 5).
1. Micro Networks tests and guarantees maximum linearity error at room
temperature and both extremes of the specified operating temperature
range.
2. The Absolute Accuracy Error of a voltage output D/A is the difference
between the actual output voltage that appears following the application of
a given digital input code and the ideal or expected output voltage for that
code. Absolute Accuracy Error includes gain, offset, linearity, and noise
errors and encompasses the drifts of these errors when specified over
temperature. For the M N3014, the Full Scale Absolute Accuracy Error is the
Absolute Accuracy Error measured when the digital input is 1111 1111 for
the 0 to + 10V range, 00000000 fortheO to -10V range. and both 11111111
ANALOG OUTPUT (DC VOLT)
DIGITAL INPUT
o to +10V
o to -10V
.±SV
±10V
00000000
0000 0001
01111111
10000000
11111110
11111111
0.000
+0.039
+4.961
+5.000
+9.922
+9.961
-9.961
-9.922
-5.000
-4.961
-0.039
0.000
-5.000
-4.961
-0039
0.000
+4.922
+4.961
-10.000
- 9.922
- 0078
0.000
+ 9.844
+ 9.922
CONNECT
PIN to PIN
9 to 12
10 to 12
13 to 15
9 to 15
10 to 15
13 to 15
9 to 12
10 to 15
13 to 15
9 to 12
10to 15
MSB
LSB
% FSR I % Vs
% FSR I % Vs
± 0.01
SPECIFICATION NOTES:
7-42
+ 15.00
-15.00
3. For an 8 bit converter, 1 LSB corresponds to 0.39% FSR. FSR stands for Full
Scale Range and is equivalent to the peak to peak voltage of the selected
output rang~. For the ±10V output range. FSR is 20V and 1 LSB:: 78 mV. For
the other output ranges, FSR is 10V and 1 LSB :: 39 mV.
4. For Commercial Models, this specification applies over the O°C to +70°C
temperature range. See Ordering Information.
5. Zero Error is the Absolute Accuracy Error measured when the output of
the converter is supposed to be zero volts (see Note 2).
6. The MN3014 will operate over a power supply range of ± 14V to ± laV with
reduced accuracy.
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies.
The unit's ground pin (Pin 12)
should be connected to system analog ground, preferably
through a large ground plane
beneath the package. Power
supplies should be decoupled
with 1 p.F capacitors paralleled
with 0.01 /IF ceramic capacitors
as shown in the diagram.
MN3020
~
_
MICRO NETWORKS
a-Bit D/A CONVERTER
with INPUT REGISTER
DESCRIPTION
FEATURES
• Complete D/A Converters:
High-Speed Input Register
Internal Reference
Internal Output Amplifier
• ±1/2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Small 18-Pin DIP
• Adjustment-Free
• ±1LSB Unadjusted
Absolute Accuracy
Over Temperature
• 31'sec Maximum Settling Time
(10V Step to ± 1/2LSB)
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
MN3020 is an 8-bit digital-to-analog converter complete
with internal reference, output amplifier and input register.
It is packaged in a hermetically sealed, ceramic, 18-pin
dual-in-line and features the following: 4 user-selectable
output ranges (2 unipolar, 2 bipolar), fast output settling
(3p.sec max for a 10 Volt change) and linearity and accuracy
specifications guaranteed over temperature.
The MN3020's hybrid construction combines a low-drift
voltage reference, Micro Networks ultrastable thin-film
resistor networks, and the newest monolithic chips
available. Active laser trimming results in a device with
± V2 LSB linearity and ± 1LSB unadjusted absolute
accuracy error guaranteed over the entire operating
temperature range.
Units are available for either O°C to +70°C or -55°C to
+125°C (H models) operation, and Micro Networks 100%
tests and guarantees both linearity and accuracy at room
temperature and at both operating temperature extremes. For
military/aerospace or harsh-environment commercial/industrial
applications, MN3020H/B CH is fully screened to MIL-H-38534
in Micro Networks' qualified facility.
MN3020's digital inputs are TTL compatible, and its internal input register facilitates interfacing to microprocessor and
minicomputer data buses. Applications include microprocessorbased data distribution systems, programmable power supplies,
low-resolution displays, and servo drivers. Optional MILH-38534 processing and accuracy specs guaranteed over the
-55°C to +125°C temperature range make the MN3020 an excellent choice for military avionics and fire control systems.
18 PIN DIP
I
Dimensions in Inches
(millimeters)
~
May 1988
MICRO NETWORKS
324 Clark Sl., Worcesler, MA 01606 (508) 852-5400
7-43
MN3020 8·Bit D/A CONVERTER with INPUT REGISTER
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
O°C to +70°C
Operating Temperature
-55°C to +125° C ("H" Models)
-65°C to +150°C
Storage Temperature
+18 Volts
+15V Supply (Pin 1)
-18 Volts
-15V Supply (Pin 13)
-0.5 to +7 Volts
+5V Supply (Pin 11)
-0.5 to +5.5 Volts
Digital Inputs (Pins 2-9)
-0.5 to +5.5 Volts
Register Enable (Pin 10)
PART NUMBER
MN3020H/B CH
Standard part is specified for O°C to +70 oC
operation.
Add "H" for specified -55°C to +125°C
operation.,----------------'
Add "/B" to "H" models for Environmental
Stress Screening. - - - - - - - - - - - - - - - '
Add "CH" to "/B" models for 100% screening
according to Mll-H-38534.----------......I
SPECIFICATIONS (TA ~ 25°C, Supply Voltages ±15V and +5V, unless otherwise specified).
DIGITAL INPUTS
MIN.
TYP.
Bits
2.0
0.7
Input Currents
Data Inputs: Logic "1" (Vin ~ 2.4 Volts)
Logic "0" (Vin ~ 0.3 Volts)
Register Enable: Logic "1" (Vin ~ 2.4 Volts)
Logic "0" (Vin ~ 0.3 Volts)
Register Enable (Note 1):
Pulse Width
Setup Time Digital Data to Enable
UNITS
Straight Binary
Offset Binary
Logic Coding: Unipolar Ranges
Bipolar Ranges
Logic Levels: Logic "1"
Logic "0"
MAX.
8
Resolution
30
- 0.6
40
- 0.8
Volts
Volts
/loA
mA
/loA
mA
nSec
nSec
60
40.
ANALOG OUTPUTS
o to +10. 0 to -10
Output Voltage Ranges: Unipolar
Bipolar
Output Impedance
Output Current
Volts
Volts
±5, ±10
0.5
II
mA
±4
TRANSFER CHARACTERISTICS
Linearity Error (Notes 2, 4): DoC to +70°C
-55°C to +125°C
Monotonicity
±
'~1
± I;;'
± '/?
LSB
LSB
Guaranteed Over Temperature
Absolute Accuracy Error (Notes 3,4): O°C to +70°C
-55°C to +125°C
±
'I,
± 1
± 1
LSB
LSB
± 1
Unipolar Offset Error (Notes 3, 4): O°C to +70°C
-55°C to +125°C
± 1
LSB
LSB
Bipolar Offset Error (Notes 3, 4): O°C to +70°C
-55°C to +125°C
± 1
± 1
LSB
LSB
± 2
t10
±10
Offset Drift (Note 6): Unipolar Positive Range
Unipolar Negative Range
Bipolar Ranges
Bipolar Zero Error: DoC to +70°C
-55°C to +125°C
ppm of FSRfO C
ppm of FSR/oC
ppm of FSR/oC
± 1
± 1
Gain Error
Gain Drift (Note 6)
± 0.1
±15
LSB
LSB
%
ppm/oC
DYNAMIC CHARACTERISTICS
Settling Time (10 Volt Change to ±1/2 LSB)
Output Slew Rate
3.0
20
I'Sec
Volts/l'Sec
POWER SUPPLIES
Power Supply Range: +15V Supply
-15V Supply
+5V Supply
+14.0
-14.0
+ 4.75
+15.0
-15.0
+ 5.0
+18.0
. -18.0
+ 5.25
Volts
Volts
Volts
Power Supply Rejection: +15V Supply
-15V Supply
± 0.03
± 0.01
Current Drain, Output Unloaded: +15V Supply
-15V Supply
+5V Supply
15
-11
23
20
-13
37
mA
mA
mA
Power Consumption
505
680
mW
7-44
%FSR/%Vs
%FSR/%Vs
SPECIFICATION NOTES:
entire output range. See Absolute Acuracy Error section below for an
explanation of how Micro Networks Corporation tests and specifies
Absolute Accuracy Error, Offset Error, and Bipolar Zero Error.
1. Converter analog output will follow digital input when Register Enable is a
logic "0", Digital input data will be latched and analog output vol~age
constant when Register Enable is a logic "1", The minimum RegIster
Enable pulse width to latch new digital input data is 60 nSec. See Timing
Diagram.
4. 1 LSB for an B bit converter corresponds to O.39%FSR. See Note .).
5. FSR stands for Full Scale Range and is equal to the peak to peak voltage of
the selected output range. For the ±.10V output range, FSR is 20 volts, and
1 LSB is equal to 78mV. For the 0 to +10V range, ~SR is 10 volts, and 1 LSB
is equal to 39mV.
2. Micro Networks tests and guarantees maximum linearity Error at room
temperature and at both extremes of the specified operating temperature
range.
3. The Absolute Accuracy Error specification applies over the converter's
6. Over specified operating temperature range.
PIN DESIGNATIONS
BLOCK DIAGRAM
. - - - - - - - (16) Summing Junction
•
..----- .....
--0
Register
(lO)o---~
Enable
Bit 5
Bit 6
Bit 7
LSB
18
PIN 1
(14) Analog Output
8 BIT
D/A
10
3.15 Kll
(6)
(7)
(8)
(9)
.--'lIIr--
a:
UJ
t-
en
(18) Unipolar Offset
1-----<1__--'.111<--0 (17)
(9
6.3 Kll
UJ
a:
+15V Supply (1)0------7
-15V Supply (13)0------7
+ 5V Supply (11)0------7
Ground (12)0------7
ABSOLUTE ACCURACY ERROR
The Absolute Accuracy Error of a voltage output DIA
converter is the difference between the actual, unadjusted,
output voltage that appears following the application of a
given digital input code and the ideal or expected output
voltage for that code. This difference is usually expressed in
LSB's or %FSR (see Note 5 above). Absolute Accuracy Error
includes gain, offset, linearity, noise and all other errors,
and includes the drifts of these errors when specified over
temperature.
For the MN3020, Micro Networks tests Absolute Acuracy
Error at both endpoints of all unipolar output ranges and at
both endpoints and the midpoint of all bipolar output ranges.
These tests are performed at both room temperature and at
the high and low extremes of the specified extended temperature range.
Example: For the MN3020H's ±10V output range (see Input
Coding and Output Range Selection), the expected output
for a 0000 0000 digital input is -10 volts; the expected output
for a 1000 0000 digital input is 0 volts; and the expected
output for a 1111 1111 digital input is +9.922 volts. Micro
Networks measures all three actual, unadjusted output
voltages at -55°C, +25°C and +125°C and guarantees them
to be within ±1 LSB of their ideal values.
Unipolar Offset Error, Bipolar Offset Error, and Bipolar Zero
Error are all Absolute Accuracy Errors. Their definitions
differ with respect to where along the converter's digital
input/analog output transfer function the errors are to be
measured, i.e., different analog output errors are measured
at different digital input codes.
OFFSET ERROR-For the MN3020; Offset Error is the
Bipolar Offset
1.
2.
3.
4.
5.
6.
7.
B.
9.
+15V Supply
Bit 1 (MSB)
Bit 2
Bit3
Bit4
Bit5
Bit6
Bit7
BitB (LSB)
lB. Unipolar Offset
17. Bipolar Offset
16. Summing Junction
15. Range Select
14. Analog Output
13. -15V Supply
12. Ground
11. +5V Supply
10. Register Enable
Absolute Accuracy Error measured when the digital input is
00000000. For the unipolar positive range, this speCification
tells how accurate the unadjusted converter will be when its
output is supposed to be zero volts. For the unipolar negative
and the bipolar ranges, it tells how accurate the unadjusted
converter will be when its output is supposed to be at its
munus full scale value.
BIPOLAR ZERO ERROR-Bipolar Zero Error is the Absolute
Accuracy Error measured when the digital input is 1000
0000 and the converter is operating in a bipolar mode. It is the
error measured when the output is supposed to be zero volts
on the ±5V and ±10V output ranges.
It is redundant to specify Offset and Bipolar Zero Errors after
giving an Absolute Accuracy Error spec that applies overthe
converter's entire output range. We have provided the Offset
and Bipolar Zero Error specs to simplify comparing the
MN3020 to other 8 bit D/A's. Be sure you clearly understand
each manufacturer's specification definitions before you
compare converters solely on a data she&~ basis.
GAIN ERROR-Gain Error is the difference between the
ideal and the measured values of ~ converter's full scale
range (minus 1 LSB). See Note 5 above. It is a measure of
the slope of the converter's transfer function. Gain Error is
not a type of Absolute Accuracy Error, but it can be calculated using two Absolute Accuracy Error measurements.
It is equivalent to the Absolute Accuracy Error measured
for the 1111 1111 digital input minus that measured for the
0000 0000 digital input, and it is usually expressed as a
percentage.
See the Converter Tutorial Section of the Micro Networks'
Product Catalogue for a complete discussion of converter
specifications.
7-45
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracy
from the MN3020. The unit's Ground pin (pin 12) should be
tied to system analog ground as close to the package as
possible, preferably through a large ground plane underneath the package.
Power supplies should be decoupled with tantalum or electrolytic type capacitors located close to the MN3020. For
optimum performance, l"F capacitors paralleled with
O.Ol"F ceramic capacitors should be used as shown in the
diagrams below.
POWER SUPPLY DECOUPLING
I I
Pin 1: :-F-I+---~It--oO:::und
Pin10
1 uF
Pin 130
+15V
J
Pin110
1 ~F
I
I
I
I
+5V
0.01 ~F
Pin 12 co--'------'--Ground
1°.01 ~F
-
For most processors, valid data remains on the data bus for a
period of time after the removal of either valid address or
control signals. This results in data being latched into the
MN3020 immediately after one of the address or control
signals changes but before valid data goes away.
For connecting mUltiple MN3020's to a processor data bus
in data distribution system applications, 3 line to 8 line and
4 line to 16 line decoders can be used to selecti~ely active
the MN3020s' input registers.
The MN3020's digital data inputs can usually be tied directly
to the processor's data bus with each input presenting
approximately one low power TTL load to the bus.
INPUT CODING AND OUTPUT RANGE
SELECTION
ANALOG OUTPUT (DC VOLTS)
DIGITAL INPUT
-15V
Coupling between analog and digital signals should be
minimized to avoid noise pickup. Short jumpers should be
used when tying pins together for output range selection,
especially when connecting either of the offset pins (pins 17
and 18) to the summing junction (pin 16). If external offset
adjustment is employed, the 1.8 megom resistor should be
located as close to the package as possible.
OPTIONAL OFFSET ADJUSTMENT-A constant offset
voltage can be added to or subtracted from the output of
the MN3020 for the purpose of increasing accuracy at and
around a particular output leve!.
This is accomplished by using an external potentiometer
to add or subtract current at the summing junction of the
MN3020's internal output amplifier. Because the MN3020 is
not equipped for gain adjustment, offsetting the output to
increase the accuracy of any particular output level may
degrade the accuracy of other levels. Adjustment should
be made following warm-up and a multiturn potentiometer
with a TCR of 100 ppm/oC or less should be used to minimize drift with temperature.
Connect the offset potentiometer as shown; apply the desired input code (see Coding
Table); adjust the offset potentiometer until the desired output
level is achieved. If offset adj ustment is not used, pin 16should
be connected as described in
the Range Selection section.
required, however. These functions can usually be accomplished by NAN Ding the appropriate address and control
lines and using the output to drive the MN3020's Register
Enable input.
,,"~I:.
1
MSB LSB
UNIPOLAR UNIPOLAR BIPOLAR
+5
POSITIVE NEGATIVE
00000000
00000001
01111111
10000000
11111110
11111111
0.000
+0.039
+4.961
+5.000
+9.922
+9.961
CONNECT
PIN TO PIN
14 to 15
17 to GND
18 to GND
Range of adjustment
= 11 LSB
-15V
MICROPROCESSOR INTERFACING - Interfacing the
MN3020 to a microprocessor is simplified by the MN3020's
internal register. External address and control decoding is
-10.000
- 9.922
- 0.078
0000
+ 9.844
+ 9.922
14 to 15
161017
16 to 17
17 to GND 18 to GND 18 to GND
INPUT REGISTER TIMING DIAGRAM
Register
Enable
Digital
Input
Data
TIMING NOTES:
T MEPW
Minimum enable pulse width is 60 nSec.
T SeE
Minimum setup time digital input data to enable is 40
TH
Hold time is defined as the required delay between the leading edge
of register enable and the end of valid input data. For the MN3020,
the hold time is zero.
T OS
Output settling time for a 10 volt change to ±1I2 LSB is 3
[1:=JJ
MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852-5400
7-46
-5.000
-4.961
-0.039
0.000
+4.922
+4.961
100k
16
_
-9.961
-9.922
-5.000
-4.961
-0.039
0.000
14 to 15
16 to 18
BIPOLAR
±10
~Sec.
~Sec max.
MN3040
_
10-Bit D/A CONVERTER
with INPUT REGISTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Complete With Internal:
Input Register
Output Op Amp
Reference
• ±1/2LSB Linearity and
Monotonicity Guaranteed
Over Temperature
• Small l8-Pin DIP
• 40nsec Setup Time
• Adjustment-Free
• ±O.l% FSR Unadjusted
Absolute Accuracy
Over Temperature
• 1OI'sec Max Settling Time
(20V step to ± l/2LSB)
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
18 PIN DIP
The MN3040 is a fast, 10-bit digital-to-analog converter with a
fast TIL input register for easy interfaCing and rapid throughputs
in microprocessor-based systems. !t is packaged in a
hermetically sealed, ceramic, 18-pin dual-in-line and is complete
with internal reference and output amplifier. Two output ranges
are available (0 to -10V and ± 10V), and performance features
include the following: fast output settling (typically 5{tsec for a
20V change), ±O.l%FSR overall accuracy, and ± V2LSB linearity and monotonicity guaranteed over the entire operating
temperature range. Maximum power consumption is 715 mW.
The MN3040 is actively laser trimmed as a complete device for
linearity, gain and offset, eliminating the need for external adjusting potentiometers. Units are available for either O°C to
+70°C or -55°C to +125°C ("H" models) operation, and Micro
Networks 100% tests and guarantees both linearity and accuracy at room temperature and at both operating temperature
extremes. For military/aerospace or harsh-environment commercial/industrial applications, "H/B CH" models are fully
screened to MIL-H-38534 in Micro Networks' MIL-STD-1772
qualified facility.
The MN3040's digital inputs are TTL compatible, and its internal input register facilitates interfacing to microprocessor and
minicomputer data buses. Applications include microprocessorbased data distribution systems, programmable power supplies,
low-resolution displays and servo drivers. Optional MIL-H-38534
processing and linearity and accuracy specs guaranteed over
the -55°C to +125°C temperature range make MN3040 and
excellent choice for military avionics and fire control systems.
~
0300 (762)
Dimensions in Inches
(millimeters)
O::D
_
MICRO NETWORKS
May 1988
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-47
MN3040 10·Bit D/A CONVERTER with INPUT REGISTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Specified Temperature
Storage Temperature
+15V Supply (Pin 8)
-15V Supply (Pin 9)
+5V Supply (Pin 7)
Digital Inputs (Pins 1-5, 14-18)
Register Enable (Pin 6)
Output Current
SPECIFICATIONS (fA
ORDERING INFORMATION
-55°C to +125°C
O°C to +70°C (Standard)
-55°C to +125°C ("H" Models)
-65°C to +150°C
+18 Volts
-18 Volts
-0.5 to +7 Volts
-0.5 to +5.5 Volts
-0.5 to +5.5 Volts
(Note 1)
= + 25°C, Supply Voltages
Logic Levels:
Standard part is specified for DoC to +70°C
operation.
Add "H" for specified -55°C to + 125°C
operation.-------------------'
Add "/B" to "H" models for
Environmental Stress Screening. - - - - - - - - - -....
Add "CH" to "/B" models for 100% screening
according to MIL-H-38534 .
--------------I
± 15V and + 5V, unless otherwise specified)
DIGITAL INPUTS
Logic Coding:
PART N U M B E R - - - - - - - - - - - MN3040H/B CH
MIN.
Unipolar (0 to -10V) Range
Bipolar (-10 to +10V) Range
Logic "1"
Logic "0"
TYP,
MAX,
2.0
0.7
Input Currents
Data Inputs: Logic "I" (Vin = 2.4 Volts)
Logic "0" (Vin = 0.3 Volts)
Register Enable: Logic "I" (Vin = 2.4 Volts)
Logic "0" (Vin = 0.3 Volts)
Register Enable (Note 2):
Pulse Width
Setup Time Digital Daia to Enable
UNITS
Complementary Binary
Complementary Offset Binary
30
- 0.6
60
- 1.2
60
40
Volts
Volts
p.A
mA
p.A
mA
nSec
nSec
ANALOG OUTPUTS
OlJtput Impedance
Output Load Current
n
0.5
±4
mA
TRANSFER CHARACTERISTICS
linearity Error (Notes 3, 5):
±Y4
O°C to +70°C
-55° C to +125° C ("H" Models)
Monotonicity
±Y2
±1h
LSB
LSB
Guaranteed Over Temperature
Absolute Accuracy Error (Notes 4, 5):
+25°C
O°C to +70°C
-55°C to +125°C ("H" Models)
± 0.05
± 0.1
± 0.2
Gain Error
Gain Drift
± 0.1
±15
±0.1
±0.4
±0.4
%FSR
%FSR
%FSR
%
ppmfOC
DYNAMIC CHARACTERISTICS
Settling Time (20V Change to ±1/2 LSB)
Output Slew Rate
5
15
10
p.Sec
V/p.Sec
+15.00
-15.00
+ 5.00
+17.00
-17.00
+ 5.25
Volts
Volts
Volts
POWER SUPPLY REQUIREMENTS
Power Supply Range:
+15V Supply
-15V Supply
+5V Supply
Power Supply Rejection:
+14.00
-14.00
+ 4.75
Current Drain, Output Unloaded:
+15V Supply
-15V Supply
+5V Supply
Power Consumption
SPECIFICATIONS NOTES
1. The output is short circuit protected to ground or either supply.
2. Converter analog output will follow digital input when Register Enable is
a logic "0", Digital input data will be latched and analog output voltage
constant when Register Er.able is a logic "1 ". The minimum Register Enable
pulse width to latch new di':lital input data is 60 nSec. See Timing Diagram.
3. Micro Networks tests ana guarantees maximum Linearity Error at room
temperature and at both extremes of the specified operating temperature
range.
7-48
%FSR/%Vs
%FSR/%Vs
± 0.005
± 0.005
+15V Supply
-15V Supply
13
- 7
30
20
-11
50
mA
mA
mA
450
715
mW
4. The Absolute Accuracy Error specification applies over the converter's
entire output range. See Absolute Accuracy Error section below for an
explanation of how Micro NetworkS Corporation tests and specifies
Absolute Accuracy Error and Gain Error.
S. 1 LSB for a 10 bit converter corresponds to 0.098% FSR. See Note 6.
6. FSR stands for Full Scale Range and is equal to the peak to peak voltage of
the selected output range. For the ±10V output range, FSR is 20 volts,and 1
LSB is equal to 19.5 mV. FortheOto-l0V range, FSR is 10 volts,and 1 LSB
is equal to 9.BmV.
PIN DESIGNATIONS
BLOCK DIAGRAM
, - - - - - - - - - < l ( 1 2 ) Summing
Enable
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
LSB
•
Junction
Register
(6)0-----,
(14)
(15)
(16)
(17)
(18)
(1)
(2)
(3)
REF
18
PIN 1
10
>--4---0(13) Analog
Output
>-«
00,
0
10
0
(4)
(5)
-I~
>.-__O_JVVlIIr--<> ( 11) Bipolar
Offset
+15V Supply (8)0-0--_
-15V Supply (9)0
)
+5V Supply (7)0---------+
Ground (10)0---------+
ABSOLUTE ACCURACY ERROR
The Absolute Accuracy Error of a voltage output D/A
converter is the difference between the actual, unadjusted
output voltage that appears following the application of a
given digital input code and the ideal or expected output
voltage for that code. This difference is usually expressed in
LSB's or %FSR (see Note 6 in the Specification Notes).
Absolute Accuracy Error includes gain, offset, linearity, and
noise errors and encompasses the drifts of these errors when
specified over temperature.
For the MN3040, Micro Networks tests Absolute Accuracy
Error at both endpoints of the unipolar output range (0 to
-10V) and at both endpoints and the midpoint of the bipolar
output range ±10V). These tests are performed at room
temperature and at the high and low extremes of the
specified operating temperature range.
Example: For the MN3040H (-55°C to +125°C temperature
range) operating on its ±10V output range, the expected
analog output for all 1111 1111 digital input is 9.9805V (see
Input Coding and Range Selection). The expected output for
a 1000000000 digital input is 0 volts, and the expected output
for a 00 0000 0000 digital input is +10.0000V. Micro Networks
measures all three actual, unadjusted output voltages at
-55°C, +25°C, and +125°C. We guarantee that at +25°C, all
three will be within ±O.l%FSR (±20mV) of their ideal values
and that over the entire -55°C to +125°C operating
temperature range, all three will be within ±O.4%FSR (±80
my) of their ideal values. By also testing and guaranteeing
±'h LSB Linearity overtemperature, we guarantee the transfer
function will be monotonic and that every output level will be
within our Absolute Accuracy specification of where it is
ideally supposed to be. Please see the Input Coding Table.
1
2
3
4
5
6
7
8
9
Bit6
Bit 7
Bit 8
Bit 9
Bit 10 (LSB)
Register Enable
+5V Supply
+15V Supply
-15V Supply
18 Bit 5
17 Bit 4
16 Bit 3
15 Bit 2
14 Bit 1 (MSB)
13 Analog Output
12 Summing Junction
11 Bipolar Offset
10 Ground
OFFSET ERROR - Bipolar and Unipolar Offset Error are
Absolute Accuracy Errors. It would be redundant to specify
them after giving an Absolute Accuracy Error that applies
over the converter's entire output range.
GAIN ERROR - Gain Error is the difference between the
ideal and the measured values of a converter's full scale
range (minus 1 LSB). It is a measure of the slope of the
converter's transfer function. Gain Error is not a type of
Absolute Accuracy Error, but it can be calculated using two
Absolute Accuracy Error measurements. It is equivalent to
the Absolute Accuracy Error measured for the 00 0000 0000
digital input minus that measured for the 11 1111 1111 digital
input, and it is usually expressed as a percentage.
See the Converter Tutorial Section of the Micro Networks'
Product Guide and Applications Manual for a complete
discussion of converter specifications, and be sure you
clearly understand each manufacturer's specification
definition before you compare converters solely on a data
sheet basis.
INPUT CODING AND OUTPUT RANGE
SELECTION
DIGITAL INPUT
ANALOG OUTPUT (DC VOLTS)
a to -lOY
10 to -10Y
00 0000 0000
00 0000 0001
0.0000
- 0.0098
' 10.0000
- 9.9805
011111 1111
10 0000 0000
10 0000 0001
- 4.9902
- 50000
- 50098
0.0195
0.0000
- 0.0195
11 1111 1110
1111111111
- 9.9805
- 9.9902
- 9.9609
- 9.9805
Pin Connections
Pin 11 Open
Pin 12 Open
Pin 11 to Pin 12
MSB
LSB
T
I!
7-49
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT CONSIDERATIONS - Proper attention to layout
and decoupling is necessary to obtain specified accuracy
from the MN3040. The unit's Ground pin (pin 10) should be
tied to system analog ground as close to the package as
possible, preferably through a large ground plane
underneath the package.
Interfacing the MN3040 to 8, 12, and 16 bit microprocessors
is simplified by the MN3040's internal 10 bit register. External
address and control decoding will be required, however.
POWER SUPPLY DECOUPLING
Pin 7c
Pin
I
10: ~F r
I
+sv
rO.01 ~F
-
Ground
Interfacing to 12 and 16 bit processors is fairly direct and can
usually be accomplished by NANDing the desired address
lines with processor's MEMORY WRITE or I/O WRITE line
and using the output to drive the MN3040's Register Enable
input. For most processors, valid data remains on the data
bus for a period of time after the removal of either valid
address or control signals. This results in data being latched
into the MN3040 immediately after one of the address or
control signals changes but before valid data goes away.
Interfacing to 8 bit processors is slightly more complicated
and an 8 bit external register is needed as shown in the
sketch below.
Power supplies should be decoupled with tantalum or
electrolytic capacitors located close to the MN3040. For
optimum performance, 11-'F capacitors paralleled with O.OlI-'F
ceramic capacitors should be used as shown in the diagrams
below.
REGISTER ENABLE - When the Register Enable (Pin 6) is
high (hold mode) the digital data in the input register will be
latched, and when the Register Enable is low (track mode).
the converter's output will follow its input. In order to latch
new digital data into the register, the Register Enable must
go low for a minimum of 60 nSec and digital input data must
be valid for a minimum of 40 nSec prior to Register Enable
going high again.
INPUT REGISTER TIMING DIAGRAM
Address decoding must be organized such that the 8 bit
intermediate register and the MN3040's internal 10 bit register appear at two different addresses. The 10 bits of digital
data are sent to the MN3040 via two data transfers. First, the 8
least significant bits of digital data are written to the
intermediate latch. Then the 2 most significant bits of digital
data are written tothe MN3040's 10 bit latch. The result is that
the 2 MSB's on the data bus and the 8 LSB's held in the
intermediate latch are all latched into the MN3040's latch
simultaneously. If one wants to change only the MSB and/or
bit 2, only a single write operation is necessary.
If the intermediate latch is tied to the MN3040's 8 most
significant bits, it would take only a single write operation to
change only the LSB and/or bit 9. Tochangeanyoftheother
bits would involve two write operations. This latter
configuration would reduce software if one were using the
MN3040 to generate smooth waveforms.
kf.Register
!
Enable'\
Digital
lnput
DRta
MN3040
ANALOG
OUTPUT
TIMING NOTES:
TME.PW
Minimum enable pulse width is 60 nSec.
TSDE
TH
Minimum setup time digital input data to enable is 40 nSec.
Hold time is defined as the required delay between the leading edge
of register enable and the end of valid input data. Forthe MN3040 the
hold time is zero.
Output settling time for a 20 volt change to ±V2LSB is 1011Sec max.
Tos
[hI]
_
MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852-5400
7-50
MN3290 Series
[1J] MICRO NETWORKS
Extended-Temperature
16-Bit D/A Converters
DESCRIPTION
FEATURES
• 16-Bit Resolution
• Fully Specified
-55°C to +125°C Operation
• ±O.006% FSR Linearity
and 14-Bit Monotonicity
Guaranteed Over Temperature
• Complete with Internal
Reference and Output
Op Amp (V Models)
• Current or Voltage Output:
3 Voltage Ranges
2 Current Ranges
• Fast Settling to ±O.003%FSR:
81"sec Max (V Models)
1!"5ec Max (I Models)
• DAC71/DAC72 Pin and
Function Compatible
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
24-PIN SIDE-BRAZED DIP
PIN 1
T
To accommodate any application, each of MN3290's six
models offers four different electrical grades ("J" and "K"
devices for O°C to +70°C operation; "S" and "T" devices
for -55°C to + 125°C operation) as summarized below.
"SIB" and "T/B" models are available with Environmental
Stress Screening. "SIB CH" and "T/B CH" models are
screened in accordance with MIL-H-38534.
Output
Base (1)
Part Number Range
'------'~
t
For demanding military/aerospace or extended-temperature
commercial/industrial applications, the MN3290 Series of
16-bit D/A converters has overcome virtually every problem
associated with the multi-sourced, industry-standard,
DAC11/DAC12 Family. Integral linearity, monotonicity (to the
14-bit level), gain and offset drift, and TIL compatibility are
all guaranteed over each device's full specified temperature
range (including -55°C to + 125°C); while full DAC11/DAC12
pin and function compatibility are retained.
Monotonicity Over Temperature
1.230(31.24)
1.270(32.26)
~~~j
MN3290 Series consists of six different devices including
three voltage-output models (0 to + 10V, ±5V, ± 10V) and
three current-output models (0 to -2mA, ± 1mA with 5kU
feedback, ± 1mA with 10kU feedback). Each device is complete with its own precision, buried-zener reference (+6.3V)
and low-noise, fast-settling, output op amp (voltage-output
models). Packaging is standard, 24-pin, side-brazed,
ceramic DIP. Power consumption is 975mW max, and no
+5V supply is required. Settling time to ±0.003%FSR is a
quick 8/lsec max for "V-out" devices and 1!l5eC max for
"I-out" devices.
0.153(3.89)
0.183(465)
'==='~
l ~~f
I
OOCto +70OC
-55OC to + 1250C
J
K
S(2)
T(2)
MN3290X-1
MN3290X-V
Oto -2mA
Oto +10V
13 Bits
13 Bits
14 Bits
14 Bits
13 Bits
13 Bits
14 Bits
14 Bits
MN3291X-1
MN3291X-V
±lmA
±5V
13 Bits
13 Bits
14 Bits
14 Bits
13 Bits
13 Bits
14 Bits
14 Bits
MN3292X-1
MN3292X-V
±lmA
±lOV
13 Bits
13 Bits
14 Bits
14 Bits
13 Bits
13 Bits
14 Bits
14 Bits
1. Select the suffix J, K, S or T in the "X" position for full part number.
2. Sand T models are available with 100% screenin9 to Mll-STD-883. Add "IB"
to part number.
0012(0.30)
1.-0.600(15.24)---1
Dimensions in Inches
(millimeters)
~
September 1989
MICRO NETWORKS
324 Clark St.. Worcester, MA 01606
(508) 852-5400
7-51
MN3290 Series Extended-Temperature 16-Bit D/A Converters
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN329XJ, MN329XK
MN329XS, SIB; MN329XT, TIB
Storage Temperature Range
+15V Supply (+Vcc, Pin 23)
-15V Supply (-Vcc, Pin 19)
Digital Input Voltage (Pins 1-16)
External Voltage Applied
to RF (Pin 17, I Models)
External Voltage Applied
to VOUT (Pin 17, V Models)
Short Circuit Duration:
Ref. Out (Pin 24) to Ground
VOUT (Pin 17) to Ground
ORDERING INFORMATION
-55°C to + 1250C
O°Cto +70°C
-55OC to + 125°C
-65°C to + 150°C
to +18 Volts
to -18 Volts
-1 to +18 Volts
o
o
±18Volts
±5 Volts
PART NUMBER---------MN329XX/B-X CH
I I
Select MN3290, MN3291, or MN3292
with either "-I" or "-V" suffix for
selected output range.
Select J, K, S or T suffix for
specified temperature range and
electrical performance.----------.....
Add "/B" to "S" or "T" models for
Environmental Stress Screening
Add "CH" to "SIB" or "T/B" models for
100% screening to MIL-H-38534.-----------'
----------1
Indefinite
Indefinite
DESIGN SPECIFICATIONS ALL UNITS (T A = +25OC, ±Vcc= ± 15V unless otherwise indicated)
DIGITAL INPUTS
MIN.
Resolution
TYP.
MAX.
UNITS
+Vcc
+0.8
Volts
Volts
+40
-0.5
mA
16
Logic Levels (Note 1): Logic "1"
Logic "0"
+2.4
-1.0
Input Currents (Note 1): Logic "1" (VIH = +2.7V)
Logic "0" (VIL = +0.4V)
+20
-0.35
Logic Coding (Note 2):
Voltage Output: Unipolar Range
Bipolar Ranges
Current Output: Unipolar Range
Bipolar Range
CSB
COB
SB
OB
Bits
pA
VOLTAGE OUTPUTS
Oto +10
±5
±10
Volts
Volts
Volts
0.15
Ohms
mA
Oto -2
±1
±1
mA
mA
mA
Output Source Impedance: MN3290X-1
MN3291X-1
MN3292X-1
4
2.45
2.45
kll
kll
kll
Output Compliance Voltage (Note 4)
±2.5
Volts
Output Voltage Ranges: MN3290X-V
MN3291X-V
MN3292X-V
Output Impedance
Output Current
±5
CURRENT OUTPUTS (Note 15)
Output Current Ranges: MN3290X-1
MN3291X-1 (Note 3)
MN3292X-1 (Note 3)
DYNAMIC CHARACTERISTICS
Settling Time (to ±0.003%FSR):
Voltage Output: Full-Scale Step
1LSB Step (Note 5)
Current Output (Note 7): 10 to 1001l Load
1kll Load
4
2.5
0.35
1
Output Slew Rate (Voltage Output Only)
±10
8
"sec
~sec
1
3
"sec
"sec
VI"sec
REFERENCE OUTPUT
Internal Reference: Voltage
Drift:
External Source Current
+6.0
1.5
+6.3
±10
2.5
+6.6
Volts
ppm/oC
mA
SPECIFICATION NOTES
1. Specified logic levels and input currents are guaranteed over each device's entire
specified temperature range as selected by part number suffix.
2. CSB=Complementary straight binary; COB=Complementary offset binary;
SB=Straight binary; OB=Offset binary. See Digital Input Coding.
3. The MN3291X-1 has an internal5kO feedback resistor which can be used with an
external output op amp to generate a ± 5V output voltage. The MN3292X-1 has an
internal 10k{} feedback resistor which can be used to generate a ± 10V output
voltage.
4. For current--output devices, compliance voltage is the maximum vottage swing
allowed at the output pin while still being able to maintain specified accuracy and
linearity.
7-52
5. The "lLSB" settling time applies to the theoretical worst-case step which is the
major carry (1000 0000 0000 0000 to 0111 1111 1111 1111).
6. Specified with no load.
7. Current-out settling time is strongly influenced by the output RC time constant and
is therefore a function of load.
a FSR=Full Scale Range and is equal to the nominal peak-to-peak voltage or current of the selected output range. A unit with a ± lOV output range (MN3292X·V)
has a 20V FSR. A unit with a 0 to +1OV output (MN329OX-V) or ±5V output
(MN3291X-V) has a 10V FSR.
POWER SUPPLIES
Power Supply Range:
MIN.
TYP.
MAX.
UNITS
±13.5
±15
±16.5
Volts
+35
+30
-25
rnA
rnA
rnA
rnA
Current Drains (Note 6):
Voltage Models: +15V Supply
-15V Supply
Current Models: + 15V Supply
-15V Supply
+18
-17
+15
-14
Power Supply Rejection Ratio:
J and S Models: + 15V Supply
-15V Supply
K and T Models: +15V Supply
-15V Supply
±0.0015
±OOO15
±0.0015
±0.0015
±0.006
±0.006
0,0.003
±0.003
%FSR/%Vs
oAlFSR/%Vs
%FSR/%Vs
%FSR/%Vs
525
435
975
825
mW
mW
Power Consumption: V Models
I Models
-30
PERFORMANCE SPECIFICATIONS (Typical @ TA = +25"C, o,Vcc= ± 15V unless otherwise indicated) (Notes 8, 15)
MODEL
MN329XJ-X
MN329XK-X
MN329XS-X
MN329XT-X
Units
±0.006
0,0.012
±0.003
0,0.006
0,0.006
±0.012
±0.OO3
±0.006
%FSR
%FSR
14
13
14
14
14
13
14
14
Bits
Bits
Unipolar Offset Error (Notes 11, 12)
Initial (+25°C, Max)
Drift (Max, Note 10)
0,0.1
0,10
±0.1
0,5
±0.1
±10
±0.1
0,5
%FSR
ppm of FSR/oC
Bipolar Zero Error (Notes 11, 13)
Initial (+25°C, Max)
Drift (Max, Note 10)
±0.1
0,15
0,0.1
±10
±0.1
0,15
±0.1
±10
%FSR
ppm of FSR/oC
Gain Error (Notes 11, 14)
Initial (+25°C, Max)
Drift (Max, Note 10)
±0.1
±20
±0.1
±15
±0.1
±20
±0.1
±15
%
ppm/DC
Integral Linearity Error (Note g)
Initial (+25°C, Max)
Over Temperature (Max, Note 10)
Resolution for which Monotonicity is Guaranteed:
Initial (+25°C)
Over Temperature (Note 10)
SPECIFICATION NOTES
9. ±0.003% FSR is equivalent to ± 112LSB for 14 bits. ±O.OOO% FSR is equivalent
14. Gain error is defined as the error in the slope of the converter transfer function. It
to ± 1/,LSB for 13 bits.
10. J and K models are fully specified for O°C to +70°C operation. Sand T models are
fully specified for -55°C to +125°C operation.
is expressed as a peroentage and is equivalent to the deviation (divided by the ideal
value) between the actual and the ideal value for the full output voltage or current
span from the 1111 1111 1111 1111 output to the 0000 0000 0000 0000 output.
11. Initial gain and offset errors are trimmable to zero with user-optional external
potentiometers.
15. For current-output devices, the tolerance on output current and output impedance
12. Unipolar offset error applies to the MN3290X-X only. It is defined as the difference
between the actual and the ideal output (zero Volts) with a digital input of all "t's".
13. Bipolar zero error applies to the MN3291X-X and MN3292X-X only. It is defined as
the difference between the actual and the ideal output (zero Volts) with the digital
code 0111 1111 tIll 1111 applied.
is ± 30%. Current-out models are specified and tested (for all parameters except
settling time) with an external op amp connected using the internal feedback resistor.
PIN DESIGNATIONS
24
Pin 1
12
13
NOTES:
1. Pin 21 is also the zero-adjust point.
2. No connects (N.G.) are not connected internally.
1
2
3
4
5
6
7
B
g
10
11
12
Bit 1 (MSB)
Bit2
Bit 3
Bit4
BitS
Bit6
Bit7
Bit8
Bit9
Bit 10
Bit 11
Bit 12
24 Reference Out (+6.3V)
23 +15V Supply (+Vcc)
22 Gain Adjust
21 Summing Junction (V Models)
lOUT (I Models)
20 Ground
19 -15V Supply (-Vcc)
18 N.C.
17 VOUT (V Models)
RFEEDBACK (I Models)
16 Bit 16 (LSB)
15 Bit 15
14 Bit 14
13 Bil13
7-53
BLOCK DIAGRAM
(24)
~
0 (23)
(MSB) Bit 1 (1)
Bit 2 (2)
RF (Note 2)
Bit 3 (3)
Bit 4 (4)
16-Bit
Ladder
Network
and
Current
Switches
Bit 5 (5)
Bit 6 (6)
Bit 7 (7)
Bit 8 (8)
Bit 9 (9)
r
+15V Supply (+Vcc)
(22)
Gain Adjust
(21)
Summing Junction (lOUT)
~
0 (20) Ground
~
~
0 (19)
-15V Supply (-Vee)
0(18)
N,C,
I
I
I
Reference Output (+6,3V)
(17) VOUT (RFDBK)
I
1- :.. _(N~te~1
Bit 10 (10)
(16)
Bit 11
(11)
(15)
Bit 16 (LSB)
Bit 15
Bit 12 (12)
(14)
(13)
Bit 14
Bit 13
Notes:
I, Current-output models do not have an internal output amplifier,
2, RF =5kll for MN3290 and MN3291.
RF =10kll for MN3292,
3, Pin 21 is also the zero-adjust point
4, No connects (N,C,) are not connected internally,
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS AND GROUNDING - Proper attention to layout and decoupling is necessary to obtain specified
linearity and accuracy from MN3290 Series devices, It is critically
important that power supplies be filtered, well-regulated, and free
from high-frequency noise, Use of noisy supplies can easily cause
unstable output levels to be generated, Switching power supplies
are not recommended for circuits attempting to achieve 12-bit or
better accuracy unless great care is used in filtering any switching
spikes present in the output
MN3290191192's Ground pin (pin 20) should be connected to system
analog ground, preferably through a large, low-impedance, analog
ground plane beneath the package,
Power supply connections should be short and direct, and all supply
lines should be decoupled (bypassed) with tantalum or electrolytic
capacitors located close to the unit For optimum performance, a
relatively large tantalum (1-101' F) paralleled with a smaller
(0,01-1,01' F) ceramic disc should be used as shown in the diagram
below,
I
I
f !
Pin 23
0
Pin 20
o--1t----I---
I.F
Pin 19
~'F T
+Vcc
MN3290191192 has an integral linearity specification (± O,OO3%FSR)
equivalent to that of a "true" 14-bit converter, If one wishes to use
only 14 of MN3290/91/92's 16 digital input lines, bit 15 (pin 15) and
bit 16 (pin 16) may be connected to any fixed voltage from +5V to
+15V (pin 23) through a Single lkO resistor,
High resolution devices such as MN3290191/92 present unique
layout problems, Grounding and contact resistances become a
matter of critical importance, A 16-bit converter with a 10V FSR has
an LSB value of 150l'V, Assuming a 5mA load, series wiring and contact resistance of only 30mO will throw the output off 1LSB, In terms
of system layout, the impedance of #18 wire is approximately
O,064Wft, Assuming contact resistance, less than 6 inches of wire
could produce a 1LSB error in the analog output Careful layout and
the use of external trim potentiometers for gain and offset adjusting
can eliminate many potential sources of error,
°
O.D1.F
I
Analog
Ground
O.D1,:vcc
Coupling between digital inputs and analog output should be
minimized to avoid noise pick-up, Pins 21 (Summing Junction), 24
(Reference Output), and 22 (Gain Adjust) are particularly noise
susceptible, Care should be taken to avoid long runs or runs close
to digital lines when utilizing these pins, If using external offset and
gain adjustments, the series resistors and adjusting pots should be
7-54
located as close to MN3290191192 as possible, If using optional gain
adjust, an 0.Q11' F ceramic capacitor should be connected between
pin 22 and analog ground as close to the package as possible,
Similarly, if using the Reference Output (pin 24) to drive an externalload, an 0.Q11' F ceramic capacitor should be connected between
pin 24 and analog ground,
OPTIONAL GAIN AND ZERO ADJUSTMENTS - MN3290 Series
devices will operate as specified without external adjustment If
desired, however, gain and zero errors (either initial or at temperature) can be trimmed with external potentiometers, Adjustments
should be made following warmup, and to avoid interaction, the zero
adjustment must be made before the gain adjustment Multiturn
potentiometers with TCR's of 100ppmloC or less are recommended to minimize drift with temperature, Series resistors should be
± 20% carbon composition or better and must be located as close
as possible to the package to prevent noise pickup, A 0.Q11' F ceramic
capacitor should be connected from gain adjust (pin 22) to ground,
Figure 1.
ZERO ADJUSTMENT - Connect the zero potentiometer as shown
for either current or voltage-output devices. For both unipolar and
bipolar devices, zero adjusting is performed at the theoretical zero
output. For example, for the MN3290-V (0 to +10V output), apply
the input code of all "1's" and adjust the output for 0 volts. For the
MN3292-1 (± 1mA output) apply a "0" and all "1's" and adjust for
OmA output. If it is not convenient to use a 3.9MO series resistor, the
"T" network may be substituted.
4'·"
to
100k!]
180kll
(1)
Digital
Inputs
LSB
(16)
Figure 1. Driving an external resistive load In parallel with RF.
+15V
+lSV
Pin 21
MN329XX·1
MSB
Figure 2.
180kU
10kH
Pin 21
MN329XX·1
to
100kll
MSB
(1)
10kl1
-15V
-15V
Digital
Inputs
GAIN ADJUSTMENT - Connect the gain potentiometer as shown
for either current or voltage-output devices. Apply the digital input
code that theoretically produces the maximum positive voltage, or
maximum negative current, as appropriate (see Digital Input
Coding). Adjust the potentiometer to achieve the desired output.
Gain adjusting effectively rotates the device transfer function around
zero.
LSB
270kH
10kn
to
100kU
-15V
Number
MN3290X·1
MN3291X·/
MN3292X·1
For MN3292X-I, paralleling RF and Ro produces an effective output impedance of 1.97kO. If one wishes to produce an output voltage
of ± 2V, an external 8900 resistor must be put in series with RF as
shown in Figure 2.
lOUT
ROUT
RF
VOUT
010 -2mA
4kO
2.45kO
2.4SkO
SkO
SkO
10kO
010 +10V
±lmA
±1mA
±SV
±10V
DRIVING AN EXTERNAL OP AMP WITH CURRENT-OUTPUT
DEVICES - Current-output models of MN3290191192 may be used to drive the summing junction of an output op amp in the traditional current-to-voltage configuration shown in Figure 3. Using the
internal feedback resistors produces the same voltage ranges as
the voltage-output devices and also maintains specified accuracy
and drift.
Figure 3.
MN329XX·1
MSB
(1)
RF
Digital
Inputs
OUTPUT COMPLIANCE VOLTAGE - Compliance voltage is the
maximum voltage swing allowed on the output of the current models
while maintaining specified linearity and accuracy. MN3290191192-1
is specified for a compliance voltage swing of ±2.5V, and an absolute maximum range of ±5Vis permitted without damage to the
device.
When designing the resistive load, one should use MN3290191192's
internal feedback resistor as often as possible. The feedback and
output resistances of the DAC are implemented on the same thinfilm network and will track each other, as well as the rest of the DAC,
very closely. The bulk of the load resistance should be made with
Ro and RF whenever possible. See Figures 1 and 2. Paralleling RF
and Ro for the MN3290X-1 produces an effective output resistance
of 2.22k. Adding an external RL of 1.82kO in parallel with RF will
yield an effective load of 1kO, producing an output voltage range
of 0 to -2V.
(16)
Part
REFERENCE OUTPUT - All MN3290191192 models contain an internal +6.3V ± 5% voltage reference. The reference output (pin 24)
may be used to drive an external load. The use of an external buffer is recommended if the anticipated source current will exceed
1.5mA or if the load is expected to vary while the D/A converter is
in use. The reference output is short-circuit protected to ground.
DRIVING A RESISTIVE LOAD WITH CURRENT-OUTPUT
DEVICES - When using current-output devices to drive resistive
loads, care should be taken not to exceed the compliance voltage
limitation. This means that for MN3290X-1 (0 to -2mA output), the
effective load resistance must not exceed 1.25kO. For MN3291X-1
and MN3292X-1 (± 1mA output), the effective load must not exceed
2.5kO.
VOUT
Figure 2. Driving an external resistive load in series with RF.
+lSV
Pin 22 o-_.JW\r-......:~
"--+---'.--<>
LSB
(17)
>-......
_ - - < l VOUT
(16)
Figure 3. Driving an external op amp using the internal feedback resistor.
With the use of an external feedback resistor, the output may be
scaled to any voltage; however it will be at the expense of increased
gain drift. The thin-film resistors internal to MN3290/91/92 typically
track each other to within ± 1ppm/o C, but their absolute TCR may
be as high as ± 50ppm/ oC. An alternative method of scaling the output voltage and preserving the low gain drift is shown in Figure 4.
For output voltages larger than ± 10V, a high-voltage op amp may
be employed with an external feedback resistor. Back-to-back protection diodes should be used at the summing junction to protect
the DAC's output stage.
F/gure4.
MN329XX·1
MSB (1)
Digital
Inputs
LSB
(16)
Figure 4. Using external op amps with internal and external feedback resistors
to maintain low gain drift.
7-55
DIGITAL INPUT CODING
MN3292
MN3291
MN3290
Digital Input
LSB
oto +lOV
Oto -2mA
±5V
±lmA
±lOV
±lmA
0000 0000 0000 0000
0000 0000 0000 0001
0011111111111111
0111111111111111
1000 0000 0000 0000
10111111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1111
+9.99985
+9.99969
+7.50000
+5.00000
+4.9998S
+2.50000
+O.oooIS
0.00000
-1.99997
-1.99994
-1.50000
-1.00000
-0.99997
-0.50000
-0.00003
0.00000
+4.99985
+4.99969
+2.50000
0.00000
-O.OOOIS
-2.50000
-4.9998S
-5.00000
-0.99997
-0.99994
-0.50000
-0.00000
0.00003
+0.50000
+0.99997
+1.00000
+9.99969
+9.99939
+5.00000
0.00000
-0.00031
-S.ooooo
-9.99969
-10.00000
-0.99997
-0.99994
-0.50000
0.00000
+0.00003
+0.50000
+0.99997
+1.00000
MSB
CODING NaTES
1. For 10 Volts FSR, lLSB for 16 bits=I52.6~V. lLSB for 14 bits=610.4~v.
2. For 20 Volts FSR, lLSB lor 16 bits=305.~V. lLSB lor 14 bits=1.22m11.
3. For 2mA FSR, lLSB for 16 bitsz305~. 'ILSB lor 14 bits=122.1~.
4. For the unipolar voltage range, the coding is complementary straight binary. For
bipolar voltage ranges, it is complementary offset binary.
5. For the unipolar current range, the coding is straight binary. Forthe bipolar current
range, ~ is offset binary.
ORDERING INFORMATION
Part
Number
Output
Voltage
Range
MN329OJ-1
MN3290K-1
MN3290S-1
MN3290SlB-I(3)
MN329C1T-1
MN329C1T/B-I(3)
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
MN329OJ-V
MN3290K-V
MN3290S-V
MN3290SlB-V(3)
MN32911T-V
MN329OT/B-V(3)
oto +IOV
oto +IOV
Output
Current
Range
Oto
Oto
010
010
Oto
Oto
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
Feedback
Resistor
SkI)
SkI)
Ski)
SkI)
SkI)
SkI)
Specified
Temperature
Range
Integral linearity (1)
Guaranteed
Monotonlcity (2)
+25"C
Temp.
+25"C
Temp.
±0006
±0.003
±0.006
±0006
±0003
±O.oo3
±O.o12
±0.006
±0.012
±0.012
±0.006
±0.006
14
14
14
14
14
14
13
14
13
13
14
14
±0.006
±O.oo3
±0.006
±0.006
±0.003
±0.003
±0.012
±0.006
±0.012
±0.012
±0.006
±0006
14
14
14
14
14
14
13
14
13
13
14
14
oto +IOV
oto +IOV
oto +IOV
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
SkI)
SkI)
SkI)
SkI)
SkI)
SkI)
O°Cto +70°C
OOCto +70°C
-55°Cto +12S·C
-55OClo +12SOC
-SSOC to + 12SoC
-55OCto +12SoC
OOCIO +70oC
OOCto +70°C
-55°Cto +12SoC
-SsoC to + 12SOC
-55°C to +12SoC
-55·Cto +12SOC
MN3291J-1
MN3291K-1
MN3291S-1
MN3291S1B-I(3)
MN3291T-1
MN3291T1B-1(3)
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
±lmA
±lmA
±lmA
±lmA
±lmA
±lmA
Ski)
SkI)
Ski)
SkI)
SkI)
SkI)
O°Cto +70OC
OOCto +70OC
-SSOCto +12SOC
-SSOCto +12SOC
-55OCto +12SOC
-SSOCto +12SOC
±0006
±0.003
±0.006
±0006
±0003
±O.oo3
±0.012
±0.006
±0.012
±0.012
±0.006
±0006
14
14
14
14
14
14
13
14
13
13
14
14
MN3291J-V
MN3291K-V
MN3291S-V
MN3291S1B-V(3)
MN3291T-V
MN3291T/B-V(3)
±S
±S
±S
±S
±5
±5
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
SkI)
SkI)
Ski)
SkI)
SkI)
5k1)
OOCto +70OC
OOC to +70OC
-SSOCto +12SOC
-SSOCto +12SOC
-5SOC to +12SoC
-55OCto +12SOC
±0006
±0003
±0006
±0.006
±0003
±0.003
±O.o12
±0.006
±0.012
±0.012
±0.006
±0.006
14
14
14
14
14
14
13
14
13
13
14
14
MN3292J-1
MN3292K-1
MN3292S-1
MN3292S1B-I(3)
MN3292T-1
MN3292T/B-I(3)
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
±lmA
±lmA
±lmA
±lmA
±lmA
±lmA
lOkI)
lOkI)
lOkI)
lOki)
lOkI)
lOki)
OOCto +70OC
OOClo +70OC
-55°C to +12SOC
-SSOCto +12SOC
-SSOCto +12SOC
-55OC to +12SoC
±0.006
±0003
±0.006
±0006
±0003
±0.003
±0.012
±0.006
±O.o12
±0.012
±0006
±0.006
14
14
14
14
14
14
13
14
13
13
14
14
MN3292J-V
MN3292K-V
MN3292S-V
MN3292S1B·V(3)
MN3292T-V
MN3292T/B-V(3)
±IOV
±IOV
±IOV
±IOV
±IOV
±IOV
N.A.
N.A.
N.A.
NA
N.A.
N.A.
lOki)
lOkI)
lOki)
lOkI)
lOki)
lOkI)
OOCto +70OC
O°Cto +70OC
-55OCto +12SOC
-SSOCto +12SOC
-SSOC to + 12SOC
-SSOCto +12SOC
±0.006
±0003
±0.006
±0006
±0003
±0.003
±0.012
±0.006
±O.o12
±0.012
±0.006
±0.006
14
14
14
14
14
14
13
14
13
13
14
14
Oto +IOV
1. Maximum error expressed in %FSR. ±O.003%FSR is equivalent to ± '12LSB
for 14 bits. ±O.006oIoFSR is equivalent to ± 1/,LSB for 13 bits.
2. Minimum number of bits for which monolonicity is guaranteed over
temperature.
3. Add "GH" to "SIB" or "T/B" models for 100% screening to MIL·H·38534.
7-56
MN3348
~
HIGH-ACCURACY
LOW-POWER
12-Bit D/A CONVERTER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Complete D/A Converter:
Internal Reference
Internal Output Amplifier
• Outstanding Accuracy:
±O.05%FSR @ +25°C
±O.1%FSR -55°C +125°C
• Low Power 375mW Max
• Small 24-Pin DIP
• Adjustment-free
No Gain and Offset
Adjustment Necessary
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
..
PIN'
\
MN3348 is a low-power 12-bit D/A that offers outstanding accuracies. The device is housed in an industry-standard,
hermetically sealed, 24-pin dual-in-line package and features
performance specifications guaranteed over either the O°C to
+70°C or -55°C to + 125°C ("H" Model) operating
temperature range. Overall unadjusted absolute accuracy is
guaranteed to be better than ±O.05%FSR at room temperature
and better than ±O.1%FSR from -55°C to +125°C. Power consumption is a low 375mW maximum. Other features include 5
user-selectable output ranges, 8jtsec maximum settling time
and guaranteed monotonicity. For military/aerospace or harshenvironment commercial/industrial applications, MN3348H/B
CH is fully screened to MIL-H-38534 in Micro Networks' MILSTD-1772 qualified facility.
MN3348 was designed for high-accuracy applications in which
power and space are at a premium. Hermetic packaging, MILH-38534 processing and performance specs guaranteed from
-55°C to +125°C make it an excellent choice for
military/aerospace and avionics applications.
BLOCK DIAGRAM
Bipolar Offset
+ 15V
r--JoNVIr----o (5)
Summing June.
Optional
1 - - - - - - o..--'IIMr-~ 20KO
Offset
(2)
20MO
Adjustment
MSB (24)
Bit
2 (23)
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
(3) 10V Range
f--'YM---"--WlIr---o (4) 20V Range - 15V
(22)
(21)
(20)
(19)
(18)
~-~
--r
Bit 9
Bit 10
Bit 11
LSB
(1)
~~~~~~
+ 15V
Gain Adjust
Bit B (17)
6)
~
(16)
(15)
(14)
(13)
20MO
(8)
L -_ _ _ _ _ _..... (7)
0.120 (3.05)
Optional
20KO
REF.
~~ '1~~)t
~~f;~~)
Gain
Adjustment
-ISV
0.170 (4.32)
+ 15V Supply (10)
0------+
- 15V Supply (9)
~
(11) Ground
+-------0 (12') Ground
4----()
Dimensions in Inches
(millimeters)
[1JJ
_
May 1988
MICRO NETWORKS
324 Clark Sl., Worcester, MA 01606 (508) 852-5400
7·57
MN3348 HIGH·ACCURACY LOW·POWER 12·Bit D/A CONVERTER
ORDERING INFORMATION
PART NUM8ER - - - - - - - - - - MN3348H/B CH
Standard part is specified for ooe to +70 0 e
ABSOLUTE MAXIMUM RATINGS
operation.
- 55"C to + 125°C
- 65"C to + 150°C
+18 Volts
-18 Volts
- 0.5 to + 5.5 Volts
Operating Temperature
Storage Temperature
Positive Supply (Pin 10)
Negative Supply (Pin 9)
Digital Inputs (Pins 13·24)
Add "H" for specified -55°e to +125°e
operation. _ _ _ _ _ _ _ _ _ _ _ _ _--1
Add "/8" to "H" models for Environmental
Stress Screening. _ _ _ _ _ _ _ _ _ _ _ _.J
Add "CH" to "/8" models for 100% screening
according to MIL-H-38534.----------...J
SPECIFICATIONS (TA = + 25"C, Supply Voltages ± 15V unless otherwise specified).
MIN.
DIGITAL INPUTS
TYP.
MAX.
I
SPECIFICATION NOTES:
1.
FSR stands for Full Scale Range
and is equal to the peak to peak
voltage of the selected output
range. For the 0 to - 5V and ± 2.5V
ranges, FSR = 5V. For the 0 to - lOV.
and ± 5V ranges, FSR = 10V. For
the ± 10 range, FSR = 20V. 1 LS8 for
UNITS
3.5
Logic Levels: Logic "I"
Logic "0"
Volts
Volts
1.5
Complementary 8inary
Complementary Offset Binary
Logic Coding: Unipolar Ranges
Bipolar Ranges
±10
Input Current
pA
ANALOG OUTPUT
a 12 bit converter = 0.024 % FSR.
o to
Unipolar Out~ut Ranges
Bipolar Output Ranges
Output Impedance
Output Load Current
Absolute Accuracy Error includes
gain, offset, linearity, and all other
errors and is specified without ad·
{}
0.1
±10
±5
2.
Volts
Volts
- 5,0 to -10
± 2.5, ± 5, ± 10
rnA
justment. The specification applies
over the converter's entire output
range. Absolute Accuracy can be
improved with optional gain and offset adjustments. (See below).
TRANSFER CHARACTERISTICS
Linearity Error (Note 1):
+25"C
O°C to + 70°C
- 55"C to + 125"C ("H" Models)
±0.005
±0.012
±0.024
Differential Linearity
%FSR
%FSR
%FSR
±0.012
± 0,024
± 0,048
±1
Monotonicity
3.
For the specified performance Pin 8
(Ref. Out) must be connected to Pin
LSB
7 (Ref. In). Any additional loading of
the reference must not exceed 1
mAo If an external reference is used.
its voltage must be -10.000V and it
Guaranteed
Absolute Accuracy Error (Notes 1, 2):
+25"C
O'C to + 70"C
- 55"C to + 125°C ("H" Models)
± 0,025
±0.04
±0.05
±0.05
± 0.075
±0.1
must be able to supply 1 rnA.
%FSR
%FSR
%FSR
DYNAMIC CHARACTERISTICS
Settling time (20V Step to ± 'h LSB)
Output Slew Rate
6
10
8
"Sec
V/"Sec
REFERENCE (Note 3)
Internal
External
-10
-10
Volts
Volts
POWER SUPPLY REQUIREMENTS
Power Supply Range: + 15V Supply
-15V Supply
+ 15.00
-15.00
+9.00
-13,00
Current Drain, Output
Unloaded: + 15V Supply
-15V Supply
5
-8
Volts
Volts
10
-15
rnA
rnA
Power Supply Rejection
±0.001
± 0.005
Power Consumption
195
375
POWER SUPPLY DECOUPLING
Power supplies should be decoupled with 1 ~F
capacitors paralleled with 0.01 /LF ceramic
capacitors as shown below.
Pin 10
0
1 .F
Pins 11, 12
I
I
I
I
Pin
+ 15V
0.01 .F
0-1+---"'11T I
1 .F
7·58
+ 18.00
-18,00
910
Ground
0,01 .F
-
-15V
%FSR/%Vs
mW
OPTIONAL GAIN AND
OFFSET ADJUSTMENTS
Connect the Offset and Gain
Adjust potentiometers as
shown in the block diagram.
UNIPOLAR RANGES-Apply a
digital input of all "O's" and ad·
just the OFFSET potentiometer
for OV out. Apply all "1 's" and
adjust the GAIN potentiometer
for the output value shown in
the table.
BIPOLAR RANGES-Apply a
digital input of all "O's" and ad·
just the OFFSET potentiometer
for the minus full scale output.
Apply all "1 's" and adjust the
GAIN potentiometer for the out·
put value shown in the table.
DIGITAL INPUT CODING
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT
±2.5V
±5V
o to-5V
o to-l0V
1111 1111
1111 1110
-4.9988
-4.9976
-9.9976
-9,9951
- 2.4988
- 2.4976
- 4.9976
-4,9951
-
1000 0000 0001
1000 0000 0000
0111 1111 1111
-2.5012
-2.5000
- 2.4988
- 5,0024
- 5,0000
- 4.9976
-0.0012
0.0000
+ 0.0012
- 0.0024
0.0000
"'0,0024
-
0000 0000 0001
0000 0000 0000
-0,0012
0.0000
-0,0024
0.0000
+ 2.4988
+ 2.5000
+ 4,9976
+ 5.0000
+ 9.9951
+ 10.0000
8 to
5 to
1 to
2 to
8 to 7
5 to 11
1 to 3
8 to 7
5 to 7
1 to 3
8 to 7
5 to 7
1 to 4
1111
1111
Connect Pin to Pin
7
11
3
4
8 to
5 to
1 to
2 to
7
7
3
4
±10V
-
9.9951
9.9902
0.0049
0.0000
+ 0.0049
MN3349
I
_
r!
LOW-POWER,12-Bit
D/A CONVERTER
MICRO NETWORKS
DESCRIPTION
MN3349 is a low-power 12-bit D/A converter. It is an exact
pin-for-pin replacement for the DAC349, offering superior performance and fully guaranteed specifications. Each unit is
complete with internal reference and output amplifier and is
housed in an industry-standard, 24-pin dual-in-line package.
Operating temperature range is -55°C to +125°C, and all key
performance specifications are given as maximums and
guaranteed. Features include 5 user-selectable output ranges,
10ltsec maximum settling time and '3l5mW rTJ?Ximum power
consumption. For military/aerospace or harsh-environment
commercial/industrial applications, MN3349H/B CH fully
screened to MIL-H-38534 in Micro Networks MIL-STD-1772
qualified facility.
FEATURES
• DAC349 Pin Compatible
• Complete D/A Converter:
Internal Reference
Internal Output Amplifier
• Low Power 375mW Max
• Small 24-Pin DIP
• 5 User-Selectable
Output Ranges
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
~N3349 was designed for requirements in which power, speed,
size and temperature considerations are paramount. Maximum
specifications minimize design and purchasing time and ensure
field interchangeability without the need for recalibration.
BLOCK DIAGRAM
24 PIN DIP
BIpOlar Offset
r--"VWIr---<>
~N
Summing Junc.
~2J.l"
,
t-------<>i---'V'{I/Ir-o:!
O.115(292}]
\
20KO
(2)
\
~~?}?'.Qg,~
1315{3340)
1.100 (27.94)
~-_I-'J - . t~!.:
'-I_-_-o-n-Ol-".•
I
+ 15V
(5)
0810(2057)
-I
r-------.;
---.L
U
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
LSB
20MO
~ (3) 10V Range
(24)
(23)
(22)
(21)
(20)
(19)
(18)
-1.....vvvv---o (4) 20V Range
>----0
~~~~~~
20MO
6)
~
(16)
(15)
(14)
(13)
20KO
AEF
'---------0
(8)
~e~ ·1~~)t
(7)
~~f,~~)
+ 15V Supply (10)
~
+ - - - 0 (11) Ground
- 15V Supply
~
+-----0 (12) Ground
(9)
- 15V
Gain Adjust
(17)
I
~~~~
(1)
Optional
Offset
Adjustment
Optional
Gain
Adjustment
- 15V
t.Qo..@J(~Q.2l.
170 (4.32)
Dimensions in Inches
(millimeters)
[11J
_
MICRO NETWORKS
May 1988
Copyright©1991
Micro Networks
All rights reserved
324 Clark St.. Worcester, MA 01606 (508) 852-5400
7-59
MN3349 LOW·POWER 12·Bit D/A CONVERTER
ORDERING INFORMATION
PART NUMBER
Operating Temperature
Storage Temperature
Positive Supply (Pin 10)
Negative Supply (Pin 9)
Digital Inputs (Pins 13-24)
SPECIFICATIONS (TA
- 55°C to + 125°C
- 65°C to + 150°C
+18 Volts
-18 Volts
- 0.5 to + 5.5 Volts
= + 25°C
MN3349H/B CH
~
Standard part is specified for OOC to +70°C
operation.
Add "H" tor specified -55OC to +125°C
operation.---------Add "/B" to "H" models for Environmental
Stress Streening. - - -_ _ __
Add "CH" to "HIS" models for
100% screening according to MIL-H-38534.
ABSOLUTE MAXIMUM RATINGS
Supply Voltages +
- 15V unless otherwise specified).
TYP_
MIN_
DIGITAL INPUTS
Logic Levels: Logic "1"
Logic "0"
UNITS
MAX.
Volts
Volts
3.5
1.5
Logic Coding: Unipolar Ranges
Bipolar Ranges
Complementary Binary
Complementary Offset Binary
Input Current
2.
FSR stands for Full Scale Range
I
+10
pA
ANALOG OUTPUT
o to
Unipolar Output Ranges
Bipolar Output Ranges
Volts
Volts
- 5, 0 to - 10
±2.5, ±5, ±10
Output Impedance
Output Load Current
0
0.1
±10
±5
mA
TRANSFER CHARACTERISTICS
LSB
LSB
±Y2
Linearity Error
Differential Linearity
±1
Guaranteed
Monotonicity
±0.05
±0.05
±0.05
Scale Factor, Gain Error (Note 1)
Unipolar Offset Error (Notes 1, 2)
Bipolar Offset Error (Notes 1, 2)
±0.1
±0.2
±0.1
%
%FSR
%FSR
DYNAMIC CHARACTERISTICS
Settling time (20V Step to ± V2 LSB)
Output Slew Rate
V/~Sec
DRIFT CHARACTERISTICS
Accuracy Drift (Note 3)
Linearity Drift
Differential Linearity Drift
ppm of FSR/oC
ppm of FSR/oC
ppm of FSR/oC
±30
±5
±2
REFERENCE (Note 4)
Internal
External
Volts
Volts
-10
-10
POWER SUPPLY REQUIREMENTS
Power Supply Range: + 15V Supply
-15V Supply
+ 15.00
-15.00
+9.00
-13.00
Current Drain, Output
Unloaded: + 15V Supply
-15V Supply
mA
mA
Power Supply Rejection
±0.001
±0.005
Power Consumption
195
375
POWER SUPPLY DECOUPLING
Power supplies should be decoupled with 1 ~F
capaCitors paralleled with 0.01 ~F ceramic
capaCitors as shown below.
Pin 10
C
1 ~F
I
I
I
I
+ 15V
0.01 "F
Pins 11, 12 c-I+----II~ Ground
1 "F
Pin 9
7-60
Volts
Volts
+ 18.00
-18.00
10
-15
5
-8
C
T T
0.01 "F
-
-15V
and is equal to the peak to peak
voltage of the selected output
range. For the 0 to - 5V and ± 2.5V
ranges, FSR=5V. FortheOto -10V
and ± 5V ranges, FSR = 10V. For
the ± 10 range, FSR = 20V. 1 LSB for
a 12 bit converter = 0.024% FSR.
3.
Total effect of linearity, offset, and
gain drift on overall converter aecuracy.
4.
For the specified performance Pin 8
(Ref. Out) must be connected to Pin
7 (Ref. In). Any additional loading of
the reference must not exceed 1
rnA. If an external reference is used,
its voltage must be -10.000V and it
must be able to supply 1 rnA.
~Sec
10
8
10
SPECIFICATION NOTES:
1.
Initial Offset and Gain Errors are extemally adjustable (see below).
%FSR/%Vs
mW
OPTIONAL GAIN AND
OFFSET ADJUSTMENTS
Connect the Offset and Gain
Adjust potentiometers as
shown in the block diagram.
UNIPOLAR RANGES-Apply a
digital input of all "O's" and adjust the OFFSET potentiometer
for OV out. Apply all "1 's" and
adjust the GAIN potentiometer
for the output value shown in
the table.
BIPOLAR RANGES-Apply a
digital input of all "O's" and adjust the OFFSET potentiometer
for the minus full scale output.
Apply all "1 's" and adjust the
GAIN potentiometer for the
output value shown in the
table.
DIGITAL INPUT CODING
DIGITAL INPUT
MSB
LSB
a to-5V
1111
1111
1111
1110
-4.9988
-4.9976
-9.9976
- 9.9951
- 2.4988
- 2.4976
- 4.9976
- 4.9951
-
1000 0000 0001
1000 0000 0000
0111 1111 1111
- 2.5012
- 2.5000
- 2.4988
- 5.0024
- 5.0000
- 4.9976
- 0.0012
0.0000
+0.0012
- 0.0024
0.0000
+ 0.0024
-
0.0049
0.0000
+ 0.0049
0000 0000 0001
0000 0000 0000
- 0.0012
0.0000
- 0.0024
0.0000
+ 2.4Q88
+ 2.5000
+ 4.9976
+ 5.0000
+ 9.9951
+ 10.0000
8 to
5 to
1 to
2 to
8 to 7
5 to 11
1 to 3
8 to 7
5 to 7
1 to 3
8 to 7
5 to 7
1 to 4
1111
1111
Connect Pin to Pin
7
11
3
4
ANALOG OUTPUT
Oto-10V
±2.5V
±5V
8
5
1
2
to
to
to
to
7
7
3
4
±10V
9.9951
9.9902
MN3850
[1JJ
_
MICRO NETWDRKS
INDUSTRY-STANDARD
MILITARY, 12-Bit
D/A CONVERTERS
DESCRIPTION
The MN3850 is a high-performance, TIL-compatible, 12-bit
digital-to-analog converter in a 24-pin, hermetically sealed
ceramic dual-in-line package. The MN3850 is a monolithic
voltage-output D/A complete with an internal reference and fastsettling output amplifier. It is pin-for-pin compatible with industry
standard "3850" devices as well as many DAC87 and DAC85/80
D/A converters. The MN3850 guarantees a 4!Lsec output settling
time (20V step settling to ±0.5LSB). Other critical accuracy performance parameters are fully specified and guaranteed over
the entire operating temperature range. Linearity and
monotonicity are guaranteed over temperature, and full scale
absolute accuracy error is specified as ±0.3% FSR maximum
over temperature.
FEATURES
• Fully Guaranteed -55°C to
+125°C operation
• Linearity and Monotonicity
Guaranteed Over Temperature
• 4/.!sec Settling Time
• Small 24-Pin Hermetic DIP
• No +5V Supply Required
• 480mW Maximum
Power Consumption
• Pin-Compatible
DAC85-CBI-V, AD DAC87
• MIL-STD-1772
Qualified Facility
The Micro Networks MN3850 has 5 user-selectable output
ranges, a fully short-circuit protected output, and a maximum
power consumption of 480mW. The MN3850's rugged ceramic
package is hermetically sealed, and for military/aerospace
applications, MN3850H/B is available with Environmental Stress
Screening.
24 PIN SIDE-BRAZED DIP
PIN 1
0030(076)
~T '~i
L
1
1.185(30.10\
12'5(30'~')
1100(27.94)
The MN3850 was designed for military/aerospace, industrial
and OEM applications in which high-speed D/A conversion in
severe, wide-temperature-range environment is required.
The MN3850 12-bit D/A converter has become the industry
standard for military/aerospace and demanding industrial
applications. The MN3850's monolithic design results in
improved reliability. Guaranteed monotonicity over temperature
makes the MN3850 an excellent choice for military and
aerospace control systems.
I '.
.-
s.=
0021(0.53)
----':1
r-~I
0.580 (14.73)
I
A
!.-
0240 (6.10)
0.600 '" 24)
I::
---~
:::
0170(4.32)
_
O.ooe(O.201
0.012 (O.30)
0600 {15.24} - . /
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
February 1992
Copyright©1992
Micro Networks
All rights reserved
324 Clark St.. Worcester. MA 01606 (508) 852-5400
7·61
MN3850 INDUSTRY-STANDARD MILITARY 12-Bit D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN3850
MN3850H, H/B
Storage Temperature Range
+ 15V Supply (+Vcc, Pin 22)
-15V Supply (-Vcc, Pin 14)
Digital Inputs (Pins 1-12)
Output Current
Standard device is specified for DoC to 70°C
operation.
Add "H" suffix for specified -55°C to + 125°C
operation.-----------------'
Add "/B" suffix to "H" models for
Environmental Stress Screening.---------.....
PART NUMBER----------MN3850H/8
O°Cto +70·C
-55°C to + 125°C
-65°C to +150·C
-0.5 to +18 Volts
+0.5 to -18 Volts
-0.5 to + 18 Volts
(Note 1)
SPECIFICATIONS (T A = +25°C, ±Vcc= ± 15V unless otherwise indicated) (Note 2)
DIGITAL INPUTS
MIN.
Logic Levels: Logic "1"
Logic "0"
+2.0
TYP.
Input Currents: Logic "1" (VIH =+2.4V)
Logic "0" (VIL = +0.4V)
Logic Coding: Unipolar Output Ranges
Bipolar Output Ranges
MAX.
UNITS
+0.8
Volts
Volts
+20
-180
i~
REFERENCE OUTPUT-The MN38S0 contains an internal +6.3V
±S% voltage reference, and units are actively laser trimmed to
operate from this reference. Therefore, though the user has the option of using an external reference, for specified operation, the
Reference Output (pin 24) must be connected to the Reference Input (pin 16). If the internal reference is used to drive an external load,
the load current should not exceed 2.SmA.
OPTIONAL OFFSET AND GAIN ADJUSTMENTS-The MN38S0
will operate as specified without additional adjustments. If desired,
input/output accuracy error can be reduced to ± 1f2LSB
( ± 0.012%FSR) by follOWing the trimming procedures described
below. Adjustments should be made following warmup, and to avoid
interaction, offset must be adjusted before gain. Multiturn potentiometers with TCR's of 100ppm/oC or less are recommended to
minimize drift with temperature. Series resistors can be ± 20% carbon composition or better. If these adjustments are not used, pins
20 and 23 should not be connected to ground.
Range of Adjustment = ±0.150f0FSR
o to
+10V
Pin 23
10M\!
--I---vw-----?>~
O....
J
Range of Adjustment = ±0.2S%
±2.5V
±5V
16
16
16
16
16
Connect Pin 17 to
21
21
20
20
20
±10V
Connect Pin 15 to
18
18
18
18
19
Connect Pin 19 to
20
N.C.
20
N.C.
15
Connect Pin 20 to
19
N.C.
19,17
17
17
INPUT LOGIC CODING
Digital Input
Analog Output
LSB
o to
±2.5V
±5V
±10V
0000 0000 0000
000000000001
+4.9988V
+4.9976V
+9.9976V
+9.9951V
+2.4988V
+2.4976V
+4.9976V
+4.9951V
+9.9951V
+9.9902V
011111111111
100000000000
+2.5000V
+2.4988V
+5.0000V
+4.9976V
O.OOOOV
-0.0012V
O.OOOOV
-0.0024V
O.OOOOV
-0.0049V
111111111110
111111111111
+0.0012V
O.OOOOV
+0.0024V
O.OOOOV
-2.4988V
-2.5000V
-4.9976V
-5.0000V
-9.9951V
-10.0000V
Oto +5V
+10V
CODtNG NOTES
1. For unipolar operation, the coding is complementary straight binary (CSB).
2. For bipolar operation, the coding is complementary offset binary (COB).
3. For FSR=2OV, 1 LSB=4.88mv.
4. For FSR=10V, 1 LSB=2.44mV.
5. For FSR=5V, 1 LSB=1.22mv.
[1JJ
_
MICRO NETWORKS
324 Clark St .. Worcester. MA 01606 (508) 852-5400
7-64
f
t~kn
100kD
0.01"F
Connect Pin 24 to
MSB
-15V
+15V
Output Range
Oto +5V
10kD
to
100kD
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
below and apply a 0000 0000 0000 digital input. Adjust the gain potentiometer until the output voltage is at its ideal positive full scale value
(+F.S.-l LSB, see Input Logic Coding).
OUTPUT RANGE SELECTION
Pin Connections
f
-1SV
MN3860
Q=:D MICRO NETWORKS
12-Bit
D/A CONVERTER
with INPUT REGISTER
DESCRIPTION
FEATURES
• Complete With Internal:
Input Register
Output Op Amp
Low-Drift Reference
• ±1/2LS8 Linearity
and Monotonicity
Guaranteed Over
Temperature
• 40nsec Data Setup Time
• ±O.1% FSR Unadjusted
Absolute Accuracy
• 7pSec Max Settling Time
(20V step to ±1/2LS8)
• Small 24-Pin Side-Brazed DIP
• Full MIL Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
24 PIN DIP
PIN 1
\
The MN3860 is a 12-bit digital-to-analog converter with a fast,
internal, TIL input register. It is packaged in a hermetically
sealed, ceramic, 24-pin dual-in-line package and is complete
with internal reference and output amplifier. Three user selectable output ranges are available (0 to + 10V, ±5V and ± 10V),
and performance features include the following: fast output settling (7pSec for a 20V change), ±0.1%FSR maximum absolute
accuracy, and ± 112LSS linearity and monotonicity guaranteed
over the full operating temperature range. Maximum power consumption is 730mW.
The MN3860 is functionally laser trimmed for linearity, gain and
offset, eliminating the need for external potentiometers. Units
are available for two operating temperature ranges (O°C to
+70°C and -55°C to + 125°C). Linearity and accuracy are
tested 100% and guaranteed both at room and temperature extremes. For military/aerospace or harsh-environment commercial/industrial application, "H/S CH" models are fully screened
to MIL-H-38534 in Micro Networks MIL-STD-1772 qualified
facility.
The MN3860 is TIL compatible, and its internal input register
facilitates interfacing to microprocessor and minicomputer data
buses. Applications include microprocessor-based datadistribution systems, programmable power supplies and servo
drivers. Optional MIL-H-38534 processing and guaranteed
linearity and accuracy specifications over the -55°C to +125°C
temperature range make the MN3860 an excellent choice for
military avionics and fire control systems.
Model
Number
MN3860
MN3860H
MN3860H/B
MN3860H/BCH
Temperature
Range
Input
Coding
Max.Power
Consumption
Doe to +70 oe
-55°C to + 125°C
-55°C to + 125°C
-55°C to + 125°C
eSB/COB
CSB/COB
CSB/COB
CSB/COB
730mW
730mW
730mW
730mW
0200(508)
0230(584)
f~~
0170(432)
Dimensions in Inches
(millimeters)
~
February 1992
Copyright©1992
MicroNetwor1-----,
r-......--~(16)
(MSB)
(LS6)
B;t 1
B,t 2
Bit 3
Bit 4
B"5
B,t 6
(1)
(2)
(3)
(4)
Bit 7
Bit 8
Bit 9
(7)
(8)
(9)
elt 10
(10)
Bit 11
(11)
(12)
Ref. Input
(17) Bipolar Offset
f-----~(23)
(5)
(6)
6,,12
1
2
3
4
5
6
7
8
9
10
11
12
Ref. Output
Gain Adjust
r - -......---~(18) lOV Range
f---1-----+_~ (20) Summing Junellon
>--......
Bit 1 (MSB)
Bit 2
Bit3
Bit 4
Bit5
Bit 6
Bit 7
Bit8
Bit9
Bit 10
Bit 11
Bit 12 (LSB)
24
23
22
21
20
19
18
17
16
15
14
13
Ref. Out (+6.3V)
Gain Adjust
+15V Supply
Ground
Summing Junction
Register Enable
10V Range
Bipolar Offset
Ref. In
Analog Output
-15V Supply
+5V Supply
~ (15) Analog Output
Ground
+15V Supply
-15V Supply
+SV Supply
(21) o-------to
(22) 0-----------+
(14)0-----------+
(13)0-----------+
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy from the
MN3860. The units' Ground (pin 21) must be tied to circuit analog
ground as close to the package as pOSSible, preferably through a
large ground plane underneath the package.
Power supplies should be decoupled with tantalum or electrolytic
type capacitors located close to the unit. For optimum performance,
1/LF capacitors paralleled with 0.01/LF ceramic capacitors should
be used.
Coupling between analog and digital signals should be minimized
to avoid noise pickup. Short jumpers should be used when tying
the Reference Output (pin 24) to the Reference Input (pin 16) and
when tying the Bipolar Offset (pin 17) to the Summing Junction (pin
20) for bipolar operation. If external gain and offset adjustments are
to be used, the series resistors should be located as close to the
unit as possible.
REFERENCE OUTPUT-The MN3860 contains an internal
+6.3V ±2% voltage reference, and the units are actively laser trimmed to operate from this reference. Therefore, though the user has the
option of using an external reference, for specified operation, the
Reference Output (pin 24) must be connected to the Reference Input
(pin 16). If the internal reference is used to drive an external load, it
should be buffered if the load current will exceed 2.5mA_
OPTIONAL GAIN AND OFFSET ADJUSTMENTS-The MN3860
will operate as specified without external adjustments. If desired,
however, absolute accuracy error can be reduced to ± 1LSB by
following the trimming procedure described below. Adjustments
should be made following warmup and, to avoid interaction, the offset adjustment must be made before the gain adjustment. Multiturn
potentiometers with TCR's of 100 ppm/DC or less are recommended to minimize drift with temperature. Series resistors can be ± 20%
carbon composition or better. If these adjustments are not used, pins
20 and 23 should not be grounded.
OFFSET ADJUSTMENT- Connect the offset potentiometer as
shown and apply all "1's" to the digital inputs. Adjust the potentiometer until the analog output is equal to zero volts for the unipolar
output ranges or minus full scale for bipolar output ranges.
GAIN ADJUSTMENT- Connect the gain potentiometer as shown
and apply all "O's" to the digital inputs. Adjust the potentiometer until
the analog output is equal to the maximum positive voltage for the
chosen output range as shown in the Coding table.
+15V
+15V
3.9Mn
Pin 20
1
~110k!J
-15V
OFFSET ADJUST
10Ma
1
Pin23~110kn
-15V
GAIN ADJUST
REGISTER ENABLE-When the Register Enable (pin 19) is high
(hold mode) the digital data in the input register will be latched, and
when the Register Enable is low (track mode), the converter's output will follow its input. In order to latch new digital data into the
register, the Register Enable must go low for a minimum of 60nsec
and digital input data must be valid for a minimum of 40nsec prior
to Register Enable going high again. See Timing Diagram.
7-OT
I
INPUT REGISTER TIMING DIAGRAM
r'1~~\
MEPW
T
1-
Pin Connections
l/~r '"'~
~~ __
.=i t
TSDE
Digital
Input
Data__
OUTPUT RANGE SELECTION
THl
----------~
+10V
±5V
±10V
Connect Pin 24 to
16
16
16
Connect Pin 17 to
Connect Pin 15 to
21
18
20
18
20
N.C.
Connect Pin 20 to
N.C.
17
17
INPUT LOGIC CODING
Digital Input
_ _ _ _ _ _ _ _ _ __
MSB
TIMING NOTES:
TMEPW Minimum Enable Pulse Width is sOnsec.
TSDE Minimum Setup Time Digital Data to Enable is 40nsec.
TH
Digital Data Hold Time from Register Enable is Onsec.
Analog Output
oto
Output Range
Analog Output
LSB
a to
+10V
±5V
±10V
0000 0000 0000
0000 0000 0001
+9.9976V
+9.9951V
+4.9976V
+4.9951V
+9.9951V
+9.9902V
011111111111
1000 0000 0000
+5.0000V
+4.9976V
O.OOOOV
-0.0024V
O.OOOOV
-0.0049V
111111111110
1111 1111 1111
+0.0024V
O.OOOOV
-4.9976V
-5.0000V
-9.9951V
-10.0000V
CODING NOTES:
1. For unipolar operation, the coding is complementary straight binary (CSB).
2. For bipolar operation, the coding is complementary offset binary (COB).
3. For FSR=20V, 1LSB=4.BBmV.
4. For FSR=10V, 1LSB=2.44mV.
MICROPROCESSOR INTERFACING
Interfacing the MN3860 to 8, 12 and 16-bit microprocessors is
simplified by the MN3860's internal 12-bit register. External address
and control decoding will be required, however.
I
Interfacing to 12 and 10-bit processors is fairly direct and can usually
be accomplished by NANDing the desired address lines with the
processor's MEMORY WRITE or 110 WRITE line and using the output to drive the MN3860's Register Enable input. For most processors, valid data remains on the data bus for a period of time after
the removal of either valid address or control signals. This results
in data being latched into the MN3860 immediately after one of the
address or control signals changes but before valid data goes away.
I
I
MN3860
'--
:>
r-
~
r-
r-
III
Address decoding must be organized such that the 8-bit intermediate register and the MN3860's internal 12-bit register appear
at two different addresses. The 12 bits of digital data are sent to the
MN3860 via two data transfers. First, the 8 least significant bits of
digital data are written to the intermediate latch. Then, the 4 most
significant bits of digital data are written to the MN3860's 12-bit latch.
The result is thatthe 4 MSB 's on the data bus and the 8 LSB's held
in the intermediate latch are all latched into the MN3860's latch
simultaneously. This technique is called double buffering and it
avoids the analog output slewing to an undesirable state determined
by the LSB's of the new digital data and the MSB's of the previous
digital data.
D7
,..---;'--
tl~
·.. 1
~.iIi' r~a:
-
-
"'HI
III E'-
cbS~
.5
-
DO
'---
"
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
7-68
I
.,
0
_
Decoding
~
InterfaCing to 8-bit processors is slightly more complicated and an
8-bit external register is needed as shown in the sketch below.
[bJJ
Address and
Control
'---
-
---'>
Analog
0 utput
Track-Hold and Gain Amplifiers
Micro Networks offers a complete line ofTrack-Hold (TlH) amplifiers for
application in low-resolution (7-9 Bit applications), medium-resolution
(12-Bit applications) and high-resolution (14-16 Bit applications) systems.
For example, the MN379 is a low-resolution, ultra-high speed device
suitable for use with flash AID converters; the MN376 is well suited for
moderately high-speed 12-bit systems; and the MN373 and MN374 are
designed for application in 14 to 16-bit systems.
Track-hold (sample-hold) amplifiers are most frequently used in conjunction with AID converters to track (capture) rapidly changing analog
signals and hold them constant while the converter is performing a conversion. If the analog input of a successive approximation or subranging AID converter changes more than ± 'hLSB during the conversion
interval, significant errors may result. This means, for example, that a
high-speed 12-bit AID such as MN5245 (850nsec conversion time) can
only accurately digitize signals slowerthan 40Hz (5V peak-to-peak) while
maintaining acceptable error. The same converter used in conjunction
with an MN376 T/H amplifier (200nsec acquisition time, 40psec aperture
jitter) can accurately digitize a lMHz signal.
MN4000
High-Speed
12-Bit Linear
T/H Amplifier
In addition to T/H amplifiers, Micro Networks offers designers two gain
amplifiers. The MN2020 is a digitally programmable gain amplifier with
gains of I, 2, 4, 8, 16,32, 64 and 128. The MN2200 is an instrumentation amplifier featuring internal gain ranges of I, 10, 100 and 1000.
MN379
Flash-Converter
Compatible
T/H Amplifier
MN374
High-Speed
High-Resolution
Track-Hold Amplifier
FEATURES
FEATURES
FEATURES
• 40nsec Signal Acquisition
(1V Step to ± 0.1%)
• Designed to Directly
Drive Flash Converters
• ± 0.02% FSR Maximum
• 2psec Maximum
Aperture Jitter
• 4flsec Max Acquisition Time
(20V Step to ± 0.003%)
• Compatible with All DIP
Packaged 14-16 Bit AID's
• 400psec Aperture Jitter
• ± lflV/flSec Max Droop Rate
• 90dB Min Feedthrough
Attenuation
• Small 14-Pin DIP
• Pin and Function
Compatible with SHC76
• Full Mil Operation
-55°C to + 125°C
Gain Nonlinearity Error
• 50MHz Small
Signal Bandwidth
• Capative loads to 500pF
• 30nsec Max Acquisition Time
(1V Step to ± 0.1%)
• Functionally Compatible with
"-001010025" Devices
• ± 300V/flSec Min Slew Rate
• DESC SMD 5962-90856
Listed
• 100MHz Bandwidth
• TIL or ECl Compatible
• Full Mil Operation
-55°C to +125°C
• 24-Pin DIP
• Full Mil Operation
-55°C to + 125°C
• low 30mVp-p T/H Transient
8-2
While speed (acquisition time) is oftentimes the first criterion used in
selecting a T/H amplifier, it is important to remember that T/H inpuUoutput linearity must be consistent with AID converter and system linearity requirements. A very high-speed T/H amplifier that specifies ± 0.05%
linearity (the equivalent of 100bit linearity) should not be selected for use
in a 12-bit system (± 0.01%). Similarly, speed parameters like acquisition and track-to-hold settling times should be specified to ± 0.05% accuracy for 10-bit applications or to ± 0.01 % accuracy for 12-bit applications. The selection guides on the following page have been organized
in a fashion that first groups products by linearity or "resolution" and
then lists individual products in order of decreasing speed.
• 15nsec Max Settling Time
Track-Hold Amplifiers
Application
Maximum
Unearily
Enur (lifo)
7-9 Bits
±Q.l
12-Bits
Model
Specified
Temp
Range ("C)
35nsec
+1,
5V Step ±25V
to ±Q.l%
MN319
oto
+70
-55 to +125
1
±500
1575
24 Pin
Yes
(Note 2)
8-35
±0.01
40nsec
2V Step
to ±0.1%
+1,
±lV
MN4000
oto +70
-55 to +125
50
±200
750
24 Pin
Yes
9085601
8-53
±Q.Ol
l60nsec
lW Step
to±Q.01%
250nsec
lW Step
to±Q.01%
-1,
±lW
MN:fIIi
oto +70
-55 to +125
40
±Q.5
730
24 Pin
Yes
9073001
8-31
-1, MN03IIOA
oto +70
-55 to +125
±lW
400
±5
730
24 Pin
Yes
(Note 2)
8-5
lpSec
lW Step
to ±Q.01%
lpSec
lW Step
~ ±Q.05%
65¢>ec
2rJJ Step
to±Q.01%
Z5pSec
lrJJ Step
to±O.01%
-1,
±lW
MN34&
oto +70
-55 to +125
400
±Q.l
640
14 Pin
Yes
8994001
8-13
-1,
±lW
MN347
oto +70
-55 to +125
400
±05
640
14 Pin
Yes
(Note 2)
8-13
-1,
±lW
MN7130
oto +70
-55 to +125
60(1)
±4
900
32 Pin
Yes
9057101
9-9
-1,
±lW
MN343
Oto +70
-55 to +125
2000
±Q.l
345
14 Pin
Yes
(Note 2)
8-9
75pSec
-1,
lrJJ Step ±lW
to±Q.05%
3pSec
-1,
lrJJ Step ± lrJJ
to
±Q.003%
MN344
oto +70
-55 to +125
2000
±Q.4
345
14 Pin
Yes
(Note 2)
8-9
MN374
oto +70
-55 to +125
400
±Q.l
390
14 Pin
Yes
(Note 2)
8-25
MN3Td
oto +70
-55 to +125
1000
±Q.5
300
14 Pin
Yes
(Note 2)
8-17
±0.01
±0.01
±Q.01
±0.01
±Q.01
±0.01
14-16 Bits
±0.003
±0.003
Acquisi- Gain and
lion
IIollage
Time
Range
85ltsec
lrJJ Step
to
±Q.003%
Aperture
Jitter
(psec)
Droop
Hale
!/.tV/pS)
Power
(mW)
DIP
Package
Hi-Rei
Option
DESC
SMD
(5962-)
Page
•
±1,
±lrJJ
No.
Instrumentation MN2200
Gain
Ranges
Max Gain
Error (OlD)
1,10,100, ±0.01 to ±0.1
1000 Internal, Depending
on Range
1 to 1000
with External
Resistor
Ollset
Voltage
(RTI, ltV)
Ollset Drift
!!tV/oC)
Small Signal
BW
(kHz)
±100
(G=100)
±0.6
(G=100)
750
(G=l)
Power
(mW)
240
~pecified Temp
Range (OC)
DIP Pkg.
-25 to +85
-55 to +125
18 Pin
Mil-Std-883
Hi-Rei Option
DESCSMD
(5962-)
Yes
(Note 2)
Mil-Std-883
Hi-Rei Option
DESSMD
(5962-)
Yes
(Note 2)
Page
No.
8-47
Programmable-Gain MN2020
Gain
.Ranges
1,2,4,8,16,
32,64,128
Digitally
Programmed
Max Gain
Error (%)
±0.OO5 to
±0.2
Depending
on Range
Ollset
Voltage
(RTI, flV)
Offset Drift
!!tV/oC)
±100
±5
Small Signal
BW
(kHz)
5000
(G=l)
Power
(mW)
275
pecifled Temp
Range (OC)
DIP Pkg.
18 Pin
ato +70
-55 to +125
Page
No.
8-41
NOTES: 1. Listed specification is for typical Aperture Delay Time in nsec.
2. Contact the factory for information regarding DESC SMD's for these device types.
,; Indicates New Product.
8-3
[1JJ MICRO NETWORKS
~
8·4
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852·5400
MN0300A
HIGH-SPEED
12-Bit LINEAR
T/H AMPLIFIER
U:JJ
_
MICRO NETWDRKS
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
300nsec Max Acquisition Time
10V Step to ±O.01%
±O.01%FS Linearity
100psec Maximum Aperture Jitter
± 10V Input/Output Range
G=-1, ±O.05% Gain Accuracy
HTC-0300A Pin Compatible
Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
\
0.087(221)
..
MN0300A has been optimized for use in high-speed, widebandwidth, data-acquisition and rapid-update, data-distribution
applications. Acquisition time for a 10V step acquired to ±O.01%
(±1mV) is guaranteed not to exceed 300nsec; small-signal
bandwidth is 8MHz; and output slew rate is typicallv
±250V/pSec. MN0300A's maximum output droop rate of
± 7p.V/pSec and minimum 70dB feedthrough attenuation make it
suitable for both multiplexed and simultaneous sampling dataacquisition applications.
MN0300A has a gain of -1 and is TTL compatible. Devices
require ± 15V and +5V supplies and have a maximum power
consumption of 875mW. Input/output voltage range is ±10V, and
packaging is standard, 24-pin, ceramic dual-in-line. Standard
product is specified for O°C to +70°C (ambient) operation. For
military/aerospace or harsh-environment commercial/industrial
applications, MN0300AH/B CH is fully screened to MIL-H-38534
in Micro Networks MIL-STD-1772 qualified facility.
24 PIN DIP
o~
PIN 1
MN0300A is a high-speed, dual-in-line packaged track-hold
(sample-hold) amplifier deSigned for use in general.purpose
data-acquisiton applications requiring performance up to the
12-bit level. Input/output linearity error is guaranteed not to
exceed ±O.01%FS (equivalent to ± lhLSB for 12 bits), and
active laser trimming is used to minimize initial offset, pedestal
and gain-accuracy errors.
The MN0300A is second sourced by the Analog Devices/
Computer Labs HTC-0300A.
0100""'1
'100(2794)
~J w,.+).,
0020(0.51)
0200(508)
0230 (584)
-r0120{3.05)
0170(432)
1..-0.600(1524)-.1
Dimensions in Inches
(millimeters)
~
May 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
8-5
MN0300A HIGH-SPEED 12-Bit LINEAR T/H AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range (Ambient)
Specified Temperature Range (Ambient)
MN0300A
MN0300AH, MN0300AH/B (Note 3)
Storage Temperature Range
± 15V Supply Voltage (± Vcc , Pins 24, 22)
+ 5V Supply Voltage (+ Vdd, Pin 9)
Analog Input (Pin 13) (Note 1)
Digital Input (Pins 11, 12)
Output Current (Note 2)
SPECIFICATIONS (fA
ORDERING INFORMATION
- 55·C to + 125·C
O·C to + 70·C
- 55·C to + 125·C
-65·C to + 150·C
± 18 Volts
- 0.5 to + 7 Volts
± 18 Volts
- 0.5 to + 5.5 Volts
±50 mA
= +25°C, Supply Voltages =
-------------1
± 15V and +5V unless otherwise indicated).
I ANALOG INPUT/OUTPUT
I
PART NUMBER - - - - - - - - - MN0300AH/B CH
Standard part is specified for
O°C to +70°C operation.
Add "H" for specified -55°C to +125°C
operation. - - - - - - - - - - - - - - - '
Add "/B" to "H" models for Environmental
Stress Screening.
Add "CH" to "/B" models for 100% screening
according to MIL-H-38534.------------'
Input/Output Voltage Range
MIN.
TYP
± 10.25
± 11.5
Input Impedance
Input Bias Current
I
Output Current (Note 2)
Output Impedance
MAX.
Volts
1
+ 15
±20
Maximum Capacitive Load
UNITS
kll
p.A
0.1
mA
Il
250
pF
DIGITAL INPUT
Logic Levels (TTL, Note 4): Logic "1"
Logic "0"
+2
+5
+0.8
a
! Loading (Note 5)
1
Volts
Volts
TTL Load
TRANSFER CHARACTERISTICS
I. Gain
Gain
Accuracy
-1
±0.05
±0.005
±0.1
±0.01
VIV
%
%FS
Offset Voltage (Track Mode)
Pedestal (Note 7)
±2
±5
±20
±50
mV
mV
Stability: Gain Drift
Offset Drift (Track Mode)
± 10
±40
±50
±75
ppm/·C
ppm of FSR/·C
Acquisitiion Time (Note 6):
10V Step to ± 0.01 % FS (± 1mV)
10V Step to ± 0.1 %FS (± 10mV)
250
170
300
200
nsec
Settling Time (Track-to-Hold, Note 8) to ±0.1 %FS (± 10mV)
100
120
nsec
Aperture Delay Time
10
20
100
nsec
psec(rms)
I Gain Linearity Error (Note 6)
DYNAMIC CHARACTERISTICS
~reJitter
Output Slew Rate
Small Signal Bandwidth (- 3dB)
120
8
Output Droop Rate
Feedthrough (2.5MHz, 20Vp-p input)
V/p.sec
MHz
250
±5
nsec
±7
70
p.V/p.sec
dB
POWER SUPPLIES
Voltage Range: ± 15V Supplies
+ 5V Supply
± 12
+4.75
±15
+5
±18
±5.25
Volts
Volts
Power Supply Rejection Ratio
± 10
Quiescent Current Drain: + 15V Supply
- 15V Supply
+ 5V Supply
+21
-22
+ 17
+25
-25
+25
mA
mA
mA
Power Consumption
730
875
mW
8-6
mV/v
SPECIFICATION NOTES:
1. Analog input signal should not exceed supply voltage.
2. The MN0300A's output is current limited at approximately ± 50mA and
can ;Nithstand a sustained short to ground. Shorts to either supply wi II
result in destruction. In normal operation, load current should not exceed
±20mA.
3. The MN0300AHIB is specified for - 55 'c to + t25'C operation and is processed and screened to the requirements of MIL·STD·883, Method 5008.
4. See Applications Information for use of Hold and Hold inputs.
5. One TIL load is defined as sinking 40,IA with a logic "1" applied and
sourcing 1.6mA with a logic "0" applied.
6. FS stands for Full Scale and is equivalent to 10 volts. FSR stands for Full
Scale Range and is equivalent to 20 volts. For a 12·bit system, 1
LSB = 0.024% FSR.
7. Pedestal reters to the unwanted step in output voltage that occurs as a
T/H is switched from the track to hold mode. For many T/H's, pedestal
amplitude is a function of input/output voltage level. For the MN0300A,
pedestal is constant regardless of input/output level.
8. Track-to-hold settling time refers to the time interval between the point at
which a device is commanded from the track to the hold mode and the
paint at which the analog output (fallowing a transient) settles to within a
specified error band around its final value.
BLOCK DIAGRAM
Analog Input (13)
(1) Analog Output
Input Ground (15) 0
-=
1kl!
co~c;:,~nd (11)
•
o (21) Ground
(9) + 5V Supply
o
(24) + 15V Supply
Hold
(12)
Command
Ground (10) 0
...
PIN DESIGNATIONS
•
1
2
3
4
5
6
7
8
9
10
11
12
Analog Output
N/C
N/C
N/C
N/C
N/C
N/C
N/C
+ 5V Supply
Ground
Hold Command
Hold Command
I I
o (23) Ground
DESCRIPTION OF OPERATION-In the track mode,
MN0300A functions as an op amp in an inverting unity-gain
configuration, and its output "follows" its input. When a
logic "1" is applied to the Hold pin (pin 11), the MN0300A's
output is frozen, and the output level is held until the track
mode is reestablished by applying a logic "0" to the Hold
pin. The held output level is the voltage applied at the input
of the MN0300A at the instant (plus the aperture time) the
hold command is applied.
24
MN0300A provides a Hold input for use if the Hold command
is inverted; that is if the user wishes to use a "0" for the hold
condition and a "1" for the track mode. Performance of the
unit is identical with either type of input.
13
24
23
22
21
20
19
18
17
16
15
14
13
• I
APPLICATIONS INFORMATION
PIN 1
12
(22) - 15V Supply
O.D1"F
+ 15V Supply
Ground
-15V Supply
Ground
N/C
N/C
N/C
N/C
N/C
Input Ground
N/C
Analog Input
Variations in the instants of sampling are called aperture
uncertainty Oitter). It appears as jitter in the sampling point
and can cause significant errors when very high dv/dt inputs
are sampled. During the hold period, feedthrough and droop
rate can introduce errors at the output. It is important that a
track·hold have high feedthrough rejection to prevent input·
to·output leakage during the hold period. The droop rate is
the amount the output changes during the hold period as a
result of loading on the internal hold capacitor.
When the Hold command input returns to the track condi·
tion, the amount of time required for the track·and·hold
output to reestablish accurate tracking of the input signal is
called the acquisition time.
8·7
GROUNDING AND BYPASSING-With proper grounding
and bypassing, MN0300A will meet all published performance specifications without any additional external
components. The device has four Ground pins (pins 10, 15,
21 and 23). All four must be tied together and connected to
system analog ground as close to the package as possible.
It is preferable to have a large analog ground plane beneath
the MN0300A and have all four ground pins soldered directly
to it.
MN0300A's ± 15V and + 5V supply pins are bypassed to
ground with 0.011'F ceramic capacitors inside the package.
In critical applications, additional external 0.11'F to 11'F
tantalum bypass capacitors may be required.
I
1.0
........
0.9 -Gain
O.B
:>
0.7
~ 0.6
.~ 0.5
""
~
"-'~
"" 0.4
~
I-- Phase
0.1
.J'
0'
I
0.01
0.03
0.1
0.3
1.0
3.0
10
Frequency (MHz)
Track Mode Gain Amplitude and Phase Response
I
15.0
:>
I
12.5
.s 10.0
/
e 7.5
ill
45'
./
0.3
0.2
90'
/
./
5.0
2.5
""""'"
10
100
Input Signal Slew Rate (VI,see)
Aperture Jitter Window = 100psec
For v(l)
10sin",t, dvldt(max)
20,f
=
=
Accuracy Error Due to Aperture Uncertainty
TRACK-HOLD COMMAND-A TTL logic "0" applied to pin
11 (or a logic "1" applied to pin 12) will put the MN0300A into
the track (sample) mode. In this mode, the device acts as an
inverting unity-gain amplifier, and its output will follow
(track) its input. A logic "1" applied to pin 11 (or a logic "0"
applied to pin 12) will put the MN0300A into the hold mode,
and the output will be held constant at the level present
when the hold command was given. If pin 11 is used to control the MN0300A, pin 12 must be connected to digital
ground. If pin 12 is used to control the MN0300A, pin 11 must
be tied to + 5V. Pins 11 and 12 each present 1 TTL load to
the digital drive circuit.
USING THE MN0300A WITH AID CONVERTERS-There are
two important considerations when using T/H's to drive
successive approximation AID's. The first is a dual requirement-the T/H's output stage should exhibit a very low
impedance compared to the AID's input impedance (usually
1 to 10kO) at frequencies up to five times the AID's clock frequency, and the T/H should be able to recover from current
transients in a time interval smaller than the AID's clock
period. These requirements are based on the fact that as a
successive approximation AID's internal D/A converter
changes its output current just prior to the determination of
each output bit, the T/H will be required to sink or source
large high frequency current transients and recover within
one clock period. In the hold mode, the MN0300A's output
impedance is typically 0.10. Its output typically recovers (to
± 0.01 %) from a 2mA step in less than 150nsec. The second
consideration involves the T/H's track-to-hold transient
settling time. If the same timing pulse that puts the T/H into
the hold mode initiates the AID conversion, the transient
settling time has to be short enough to ensure that the AID
has a stable accurate input when it makes the final decision
on whether its MSB ouput should be a "1" or "0". This decision normally takes place one clock period after a conversion has begun.
In most applications using the MN0300A in front of a
successive approximation AID converter, the MN0300A's
T/H command pin can be driven directly (or inverted if
necessary) from the converter's status output. The status
output changes state when the converter receives a convert
command, and this change can drive the T/H from the track
to the hold mode. The change in state of the AID's status
output at the end of the conversion can put the T/H back
into the track mode .. The diagram below illustrates an
MN0300A mated with an ADC85 AID in this manner. Since
the ADC85's MSB output is not set to its final value until one
clock period (approximately 600nsec) after a conversion
begins, the MN0300A's track-to-hold transient will be completely settled, and no extra precautions are necessary.
+15V-15V+5V
"
>100 (1.0)
~""'":'
~~ 30 (0.3)
"u..
;}~ 10 (0.1)
->
~E
Ii:
10V Output Change
.........
12
..........
3 (0.03)
1 (0.01)
50
100
150
...........
200
Time (nsee)
-
250
25
ADCB4/85/87
MN5240
I
MSB
I
I
LSB
300
Acquisition Accuracy vs. Acquisition Time for a 10V Step
Start
0------------'
Convert
8-8
+15V -15V +5V
II
MN343
MN344
'1
L::JJ
_
MICRO NETWORKS
GENERAL-PURPOSE
TRACK-HOLD AM PLI FI ERS
DESCRIPTION
FEATURES
• Small 14-Pin DIP
• Internal Hold Capacitor
• 10"sec Max Acquisition
Time (10V Step to ±O.01%,
MN343)
• ±O.3"V/!"5ec Max Droop
Rate (MN343)
• ±10V Range, G=-1
• Low Glitch 100mV
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
14 PIN DIP
~
MN343 and MN344 are complete, adjustment-free track-hold
amplifiers in small, 14-pin, hermetically sealed dual-in-line
packages. Employing an operational "track and hold" design
with neutralization of track-to-hold charge offset, they offer
low offsets and fast acquisition times. MN343 acquires a
signal to ± 0.01 % in 10llsec. MN344 acquires a signal to
± 0.05% in 10llsec. Both devices guarantee hold offset
including pedestal error to be less than B.5mV.
Both models are complete with hold capacitor and are laser
trimmed as complete units, eliminating the need for user
adjustment. Feedthrough in the hold mode and track-hold·
track transients are minimized by the unique compensation
scheme employed. Maximum droop rate is ±0.3pV/p,sec for
MN343 and ± 1p,V/p,sec for MN344.
MN343 and MN344 are available for operation over the full
-55°C to +125°C temperature range ("H" models). For
military/aerospace or harsh-environment commercial/industrial
applications, MN343H/B CH and MN344H/B CH are fully
screened to MIL-H-38534 in Micro Networks' MIL-STD-1772
qualified facility.
M N343 and MN344 track-hold amplifiers offer circuit designers a convenient, reliable, one-component track-hold function. They are ideal for data acquisition systems, for holding
time-varying analog signals during AID conversion, and for
deglitching DIA converter outputs. Small size and weight
combined with reliable thin-film hybrid construction and
specs guaranteed from -55°C to +125°C make these trackholds particularly well suited for military, avionics and
aerospace applications.
-I
0.300(7.62)
Dimensions in Inches
(millimeters)
~ MICRO NETWORKS
April 1988
324 Clark St., Worcester, MA 01606 (508) 852-5400
8-9
MN343 MN344 GENERAL·PURPO$E T/H AMPLIFIERS
AIISOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN343, MN344
MN343H, H/B; MN344H, H/B
Storage Temperature Range
+ 15V Supply (+ Vcc, Pin 11)
-15V Supply (- Vcc, Pin 14)
Analog Input (Pin 13)
Digital Input (Pin 1)
Output Current (Note 1)
ORDERING
- 55·C to + 125·C
I~E"ORMATION
PART NUMBER
MN343H/B CH
Select MN343 or MN344.
I
Standard Part is specified for O°C to + 70°C
operation.
Add "H" suffix for specified -55°C to +125°C
operation.--------------'
Add "/B" to "H" devices for Environmental
Stress Screening.------------'
Add "CH" to "H/B" devices for 100% screening
according to MIL-H-38534.----------'
O·C to + 70·C
-55·Cto +125·C
- 65·C to + 150·C
- 0.5 to + 18 Volts
+ 0.5 to -18 Volts
±15Volts
- 0.5 to + 7 Volts
±20mA
SPECIFICATIONS (TA = +25°C, ± Vee = ±15V unless otherwise indicated) (Note 2)
ANALOGINPUUOUTPUT
InputlOutput Voltage Range (Note 4)
Input Resistance (Note 3)
Output Current (Note 1)
DIGITAL INPUT
Logic Levels: Logic "1" (Track Mode)
Logic "0" (Hold Mode)
Logic Currents: Logic "1" (VIH = + 2AV)
Logic "0" (VIL = + OAV)
MIN.
±10
-1
±0.005
±0.01
±0.03
±0.03
±1
±4
±3
±5
7.5
10
7.5
10
±100
1.5
60
2
±3
80
±0.1
±0.4
±3.5
±20
0.01
±12
±15
±100
+13
-10
345
UNITS
Volts
kn
mA
+0.8
+40
-1.6
Volts
Volts
p.A
mA
±0.01
±0.02
±0.05
±0.05
±2.5
±10
±6
±10
V/V
%FSR
%
%
%
mV
mV
mV
mV
+2.0
DYNAMIC CHARACTERISTICS
Acquisition Time: MN343: 10V Step to ±0.01% (±1mV)
20V Step to ± 0.01 % ( ± 2mV)
MN344: 10V Step to ±0.05% (±5mV)
20V Step to +0.05% ( ± 10mV)
Track·to·Hold Transient (Note 9): Amplitude (Note 3)
Settling Time to + 1mV
Aperture Delay Time (Note 3)
Aperture Jitter (Note 3)
Output Slew Rate (Note 3)
Full Power Bandwidth (10Vp·p, - 3dB, Note 3)
Output Droop Rate: Initial (+25·C): MN343
MN344
O·C to + 70·C (Note 3)
-55·Cto + 125·C("H" models, Note 3)
Feedthrough Attenuation (@1kHz)
8-10
MAX.
±3
TRANSFER CHARACTERISTICS
Gain
Gain Linearity Error (Note 5)
Gain Accuracy: Initial (+25·C): MN343
MN344
Over Temperature (Note 6)
Offse! Voltage (Track Mode, Note 7): Initial (+25·C)
Over Temperature (Note 6)
Pedestal (Note 8): Initial (+25·C)
Over Temperature (Note 6)
POWER SUPPLIES
Voltag.e Range (Note 4)
Power Supply Rejection Ratio (Note 3)
Current Drains: + 15V Supply
-15V Supply
Power Consumption
TYP.
±11
3
10
15
10
15
2.5
±0.3
±1
0.04
±16
+17
-12
435
p'sec
p'sec
p'sec
p'sec
mV
p'sec
nsec
nsec
V/p.sec
kHz
p.Vlp.sec
p.V/p.sec
p.Vlp.sec
p.Vlp.sec
%
Volts
p.V/v
mA
mA
mW
SPECIFICATION NOTES:
1. MN343/344's output is short-circuit protected, and units can withstand sus·
2.
3.
4.
5.
tained shorts toground oreither supply with current limiting at approximately
± 2OmA. In normal operation, output current should not exceed ± 3mA.
Listed specifications apply for both MN343 and MN344 unless otherwise
indicated.
These parameters are listed for reference only and are not tested.
Maximum output voltage swing is typically ± Vcc ± 4V.
FS stands for full scale and is equivalent tol0Volts. FSR stands for full scale
range and is equivalent to 20 Volts. For a 12·bit system, 1 LSB
= 0.024% FSR.
7. Adjustable to zero with user-optional external potentiometer.
S. Pedestal refers to the unwanted step in output voltage that occurs as a TIH is
switched from the track to the hold mode. For many T/H's, pedestal
amplitude is a function of input/output voltage level. For the MN343 and
MN344, pedestal is constant regardless of input/output level.
9. Track·to·hold settling time refers to the time interval between the point at
which a device is commanded from the track to the hold mode and the
point at which the analog output (following a tranSient) settles to within a
specified error band around its final value.
6. Unless otherwise indicated, listed specifications apply over the O'C to
+ 70'C temperature range for MN343 and MN344 and over the - 55'C to
+ 125'C temperature range for MN343H, MN343HIB, MN344H and
MN~44H/B.
BLOCK DIAGRAM
3k!l
Analog Input
3k!l
(13) 0 - - - - - - ' \
+ 15V Supply (11)
~
-15V Supply
~
> ......---<0 (S)
(14)
Analog Output
(9)
No Connect (2,3,5,10,12) ~
~--p'5K -15V
(7)
Offset
Adjust
~--.
TIH Command
(1)
0----------------1
.....-------00
PIN DESIGNATIONS
T/H Command
No Connect
No Connect
Ground
No Connect
Ground
Offset Adjust
Ground
APPLICATIONS INFORMATION
14
1
2
3
4
5
6
7
(4,6)
14
13
12
11
10
9
8
-15V Supply (- Vee)
Analog Input
No Connect
+ 15V Supply (+ Vee)
No Connect
Offset Adjust
Analog Output
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracy
and speed performance from MN343 and MN344. The un~s'
two Ground pins (pins 4 and 6) are not connected to each
other internally. They should be tied together as close to the
unit as possible and both connected to system analog
ground, preferably through a large analog ground plane
underneath the package. If p.c. card ground lines must be
run separately, wide conductor runs should be used with
O.01I'F ceramic capacitors interconnecting them as close to
the package as possible.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick-up. Care should be taken
to avoid long runs or analog runs close to digital lines. Input
and output signal lines should be kept as short as possible,
and if external offset adjustment is used, the potentiometer
should be located as close to the unit as possible. If offset
adjust is not used, pins 7 and 9 should be left open.
8-11
Power supply connections should be short and direct, and
all power supplies should be decoupled with highfrequency bypass capacitors to ground. 11'Ftantalum capacitors in parallel with 0.011'F ceramic capacitors are the
most effective combination. Single 11'F ceramic capacitors
can be used if necessary to save board space.
OFFSET ADJUSTMENT-MN343/344's track-mode offset
error can be reduced to zero with a 5kll potentiometer connected between pins 7 and 9 with its wiper connected to
-15V. With the analog signal path grounded, the pot should
be adjusted until the output equals zero volts. The pot can
also be used to compensate forthe effects of pedestal by per-
forming the adjustment in the hold mode. This adjustment is
normally made while continually switching from track to hold
and observing the T/H output on a scope. This procedure will
eliminate adjustment ambiguities resulting from output
droop.
TRACK·HOLD COMMAND-A TTL logic "1" applied to pin 1
will put the MN343/344 into the track (sample) mode. In this
mode, the device acts as an inverting unity gain amplifier,
and its output will follow (track) its input. A logic "0" applied
to pin 1 will put the MN343/344 into the hold mode, and the
output will be held constant at the level present when the
hold command was given.
10
9
10
MN343
9
8
8
U
'"'"
.5
U
'"
E
.;;;
5
'0;
4
cr
.5
'),.° 10
'E"
1:).
E 6
;::
c:
'"'"
7
;::
6
c:
~
.;;;
'0;
cr
0
..:
7
4
0
..:
3
2
3
2
5
15
10
Output Swing (Volts)
20
10
15
Output Swing (Volts)
20
ORDERING INFORMATION
Part
Number
MN343
MN343H
MN343H/B (1)
MN344
MN344H
MN344H/B (1)
Specified
Temperature
Range
O·Cta
-55·Cta
-55·Cto
O·Cto
-55·Cto
-55·Cto
+ 70·C
+125·C
+125·C
+ 70·C
+125·C
+125·C
Gain
Accuracy
( + 25°C, MaX>
Offset
Voltage
( + 25°C, MaX>
Acquisition
Time (2)
(10V Step, MaX>
Output Droop
Rate
(+25°C, MaX>
Power
Consumption
(Maximum)
Ceramic
DIP
Package
±0.02%
±0.02%
±O.02%
±0.O5%
±O.05%
±O.05%
±2.5mV
±2.5mV
±2.5mV
±2.5mV
±2.5mV
±2.5mV
10"sec
1O"sec
1O"sec
10"sec
10"sec
10"sec
± O.3"VI"sec
± O.3"VI"sec
± 0.3"VI"sec
±1"VI"sec
±1"V/"sec
±1"VI"sec
435mW
435mW
435mW
435mW
435mW
435mW
14-pin
14-pin
14-pin
14-pin
14-pin
14-pin
Notes:
1. Add "CH" to "H/B" models for 100% screening to MIL-H-3B534.
2. For the MN343, acquisition time is specified for a final error
band of ±O.Ol%. For the MN344. acquisition time is specified for
a final error band of ±O.o5%.
~
8-12
MICRO NETWORKS
324 Clark St.. Worcester, MA 01606 (508) 852-5400
UJJ
_
MN346
MN347
HIGH-SPEED
TRACK-HOLD AMPLIFIERS
MICRO NETWORKS
DESCRIPTION
FEATURES
MN346 and MN347 are high-speed, adjustment-free track-hold
amplifiers in small, 14-pin, hermetically sealed dual-in-line
packages. Both units are complete with internal hold capacitor
and incorporate a neutralization of track-to-hold charge offset
that results in fast acquisition times and low pedestal errors.
MN346 acquires a lOV step to ±O.01% in 2/-t5t3C. MN347
acquires a 10V step to ±O.OS% in 2.S/-tsec. MN346 guarantees
offset and pedestal errors to be less than ± 3mV and ± 4mV
respectively. MN347 guarantees these errors to be less than
± SmV and ± 8mV respectively.
• Small 14-Pin DIP
• Internal Hold Capacitor
• 21'sec Max Acquisition Time
(10V Step to ±O.01%, MN346)
• ±10V Range, G=-1
• ±3mV Max Offset
±4mV Max Pedestal
• ±O.51'V/!'5ec Max Droop
Rate (MN346)
Both MN346 and MN347 are functionally laser trimmed as complete units eliminating the need for user adjustment while saving
the cost and space normally required for external components.
A unique compensation scheme minimizes feedthrough and
track-hold-track glitches. Maximum droop rate is ±O.S/-tV/pSec
for the MN346 and ± 1.S/-tViftSec for the MN347.
MN346 and MN347 are available for operation over the full
-SsoC to +125°C temperature range, and high reliability processing, screening and qualification according to MIL-H-38534
are available for military/aerospace applications.
• Low Glitch 40mV
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
'D l)
14 PIN DIP
9·015 (0.38\
P'N
f89
n
11-
0.082 (2.08)
1- o~
o.n0(1956l
--l I
0.825(20'"
~:J")
~ wt~
rLO.520(13.21)~-:1~172(4.37)O.200{5.08)
0.480112.19\
0.009(0.23)
0.012 (0.30)
MN346 and MN347 offer the circuit designer very fast acquisition times and the convenience of a one-component track-hold
function at low cost. These track-holds find application in D/A
deglitching, in high-speed data distribution systems and in highspeed, simultaneously-sampling or sequential data acquisition
systems requiring high scan rates. Small size and weight
combined with reliable thin-film hybrid construction and specs
guaranteed from -55°C to + 125°C make these track-holds
particularly well suited for military, avionics and aerospace
appl ications.
0020(0.51)
O.126@1Ql
0.230 (S.B4)
T
~ ~
0.300 (1.62)
Dimensions in Inches
(millimeters)
~ MICRO NETWORKS
May 1988
324 Clark st.. Worcester, MA 01606 (508) 852-5400
8-13
MN346 MN347 HIGH-SPEED T/H AMPLIFIERS
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN346, MN347
MN346H, H/B; MN347H, H/B
Storage Temperature Range
+ ISV Supply (+Vcc, Pin 11)
-ISV Supply (-Vcc, Pin 14)
Analog Input (Pin 13)
Digital Input (Pin 1)
Output Current (Note 1)
ORDERING INFORMATION
PART NUMBER
DoC to +70°C
-SsoC to +12SoC
-6SoC to + 150°C
-O.S to + 18 Volts
+O.S to -18 Volts
±15 Volts
-O.S to +7 Volts
±20mA
MN346H/B CH
Select MN346 or MN347.
I
Standard Part is specified for DoC to + 70°C
operation.
Add "H" suffix for specified -SsoC to + 12SoC
operation. _ _ _ _ _ _ _ _ _ _ _ _ _ _....1
Add "/B" to "H" devices for Environmental
Stress Screening. - _ _ _ _ _ _ _ _ _ _ _--'
Add "CH" to "H/B" devices for 100%
screening according to MIL-H-38S34.---------'
SPECIFICATIONS (TA= +25"C, ±Vcc= ±15V unless otherwise Indicated) (Note 2)
ANALOG INPUTIOUTPUT
MIN.
TYP.
Input/Output Voltage Range (Note 4)
±10
±11
Input Resistance (Note 3)
Output Current (Note 1)
MAX.
UNITS
Volts
3
kO
±3
mA
DIGITAL INPUT
Logic Levels: Logic "1" (Track Mode)
Logic "O"(Hold Mode)
+2.0
Logic Currents: Logic "1" (VIH = +2.4V)
Logic "0" (Vll = +0.4V)
+0.8
Volts
Volts
+1
-1S0
pA
pA
TRANSFER CHARACTERISTICS
Gain
-1
VN
Gain Linearity Error (Note S)
±0.005
±0.01
%FSR
Gain Accuracy: Initial (+2S°C): MN346
MN347
Over Temperature (Note 6): MN346
MN347
±0.01
±0.03
±0.03
±0.06
±0.02
±0.05
±0.05
±0.1
%
%
%
%
Offset Voltage (Track Mode, Note 7): Initial (+2S0C): MN346
MN347
Over Temperature (Note 6)
±1
±2
±6
±3
±S
±20
mV
mV
mV
Pedestal (Note 8): Initial (+25°C): MN346
MN347
Over Temperature (Note 6)
±2
±4
±10
±4
±8
±20
mV
mV
mV
1
1.6
1
1.6
2
2.5
2.5
3.S
J'Sec
I'sec
"sec
J'Sec
±40
150
500
mV
nsec
DYNAMIC CHARACTERISTICS
Acquisition Time: MN346: 10V Step to ±0.01% (±1mV)
20V Step to ±0.01% (±2mV)
MN347: 10V Step to ± O.OS% (± SmV)
20V Step to ± O.OS% (± 10mV)
Track-to-Hold Transient (Note 9): Amplitude (Note 3)
Settling Time to ± 1mV
30
Aperture Delay Time (Note 3)
nsec
Apertu re Jitter (Note 3)
400
psec
Output Slew Rate (Note 3)
±50
Vi!'5ec
Full Power Bandwidth (10Vp-p, -3dB, Note 3)
1.4
MHz
Output Droop Rate: MN346: Initial (+25°C)
O°Cto +70 oC
-55°C to +125°C
MN347: Initial (+25°C)
O°C to +70°C
-55°C to + 125°C
±0.1
±20
±200
±0.5
±60
±700
±0.5
±60
±700
±1.5
±150
±1500
"V/!'5ec
"V/!'5ec
"Vi!'5ec
"V/!'5ec
"V/!'5ec
I'V/!'5ec
Feedthrough Attenuation (@1kHz)
0.005
0.02
%
±15
±16
Volts
+20
-17
+28
-25
"VN
mA
mA
640
795
mW
POWER SUPPLIES
Voltage Range (Note 4)
Power Supply Rejection Ratio (Note 3)
Current Drains: + 15V Supply
-15V Supply
L-f'?wer Consumption
8-14
±12
±100
SPECIFICATION NOTES:
1. MN346/347's output is shmt,clfcuit protected and units can withstand sustained
shorts to ground or either supply with current limiting at approximately ± 20mA.
In normal operation. output current should not exceed ± 3mA.
2. listed specifications apply for both MN346 and MN347 unless otherwise
indicated.
3. These parameters are listed for reference only and are not tested.
4. MaXimum output voltage swing IS typically ± Vee ± 4V.
5. FS stands for full scale and is equivalent to 10 Volts. FSR stands for full scale range
and is equivalent to 20 Volts. For a 12-bit system, 1 LSB=0.024%FSR.
6. Unless otherwise indicated, listed specifications apply over the DOG to +70°C
temperature range for MN346 and MN347 and over the -55°C to + 125 D C
temperature range for MN346H, MN346H/B, MN347H and MN347H/B.
BLOCK DIAGRAM
7. Adjustable to zero with user·optional external potentiometer.
S. Pedestal refers to the unwanted step in output voltage that occurs as a T/H is
swilched from the lrack to the hold mode. For many T/H's, pedestal amplitude
is a func1ion of inpuUoutput voltage level. For the MN346 and MN347, pedestal
is constant regardless of input/output level.
9. Track-to-hold settling time refers to the time interval belween the pOint at which
a device is commanded from the track to the hold mode and the point at which
the analog output (following a transient) settles to within a specified error band
around its final value.
(12) Summing Junction
3kll
3kll
O------.J\
Analog Input
1131
+15VSupply
itl1 ~
- 15V Supply
1141 ~
>-+--<0
No Connect 12,3,5,101
~--p'5K
~
+15V Offset
Adjust
.. ~
III O - - - - - - - - - - - - - - - - i
t---------.()
PIN DESIGNATIONS
T/H Command
No Connect
No Connect
Ground
No Connect
6 Ground
7 Offset Adlust
(4,6) Ground
APPLICATIONS INFORMATION
14
1
2
3
4
5
Analog Output
(91
0---
171
TIH Command
(81
14
13
12
11
10
9
8
-15V Supply (-Vee)
Analog Input
Summing Junction
+15V Supply (+Vcc)
No Connect
Offset Adjust
Analog Output
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy and speed
performance from MN346 and MN347. The units' two Ground pins
(pins 4 and 6) are not connected to each other internally, They should
be tied together as close to the unit as possible and both connected
to system analog ground, preferably through a large analog ground
plane underneath the package, If p,c, card ground lines must be run
separately, wide conductor runs should be used with 0,01 p- F ceramic
capacitors interconnecting them as close to the package as
possible.
Coupling between analog inputs and digital signals should be
minimized to avoid noise pick-up, Care should be taken to avoid long
runs or analog runs close to digital lines, Input and output signal
lines should be kept as short as possible, and if external offset adjustment is used, the potentiometer should be located as close to
the unit as possible. If offset adjust is not used, pins 7 and 9 should
be left open,
8-15
Power supply connections should be short and direct, and all power
supplies should be decoupled with high-frequency bypass capacitors to ground. 11'F tantalum capacitors in parallel with 0.011'F
ceramic capacitors are the most effective combination. Single 11' F
ceramic capacitors can be used if necessary to save board space.
OFFSET ADJUSTMENT-MN3461347's track-mode offset error
can be reduced to zero with a 51<0 potentiometer connected between
pins 7 and 9 with its wiper connected to +15V. With the analog signal
path grounded, the pot should be adjusted until the output equals
zero volts. The pot can also be used td compensate for the effects
of pedestal by performing the adjl,lstment in the hold mode. This adjustment is normally made while continually switching from track
to hold and observing the T/H output on a scope. This procedure
will eliminate adjustment ambiguities resulting from output droop.
TRACK-HOLD COMMANO-A TTL logic "1" applied to pin 1 will
put the MN346/347 into the track (sample) mode. In this mode, the
device acts as an inverting unity gain amplifier, and its output will
follow (track) its input. A logic "0" applied to pin 1 will put the
MN3461347 into the hold mode, and the output will be held constant at the level present when the hold command was given.
2.0
2.0
MN347
MN346
1.8
1.8
0\0
"~
-=
w
:;;
1.6
~
],
1.4
w
:;;
1.4
;::
z
1.2
;::
1.0
0
E
(/)
1.0
0.8
:5
0.8
0
;::
z
Ui
:5
0
tl
«
1.2
0
tl
«
0.6
0.6
0.4
0.4
0.2
0.2
5
10
~
5
20
15
","
",.
1.6
OUTPUT SWING (Volts)
10
15
20
OUTPUT SWING (Volts)
ORDERING INFORMATION
Part
Number
MN346
MN346H
MN346H/B (1)
MN347
MN347H
MN347H/B (1)
Specified
Temperature
Range
Gain
Error (Max)
Offset
Error (Max)
+2S"C
Temp.
+2S"C
Temp.
+2SoC
O°C to +70 oC
-55°C to + 125°C
-55°C to + 125°C
O°C to +70°C
-55°C to + 125°C
-55°C to + 125°C
±O.02%
±0.02%
±0.02%
±O.o5%
±0.05%
±0.O5%
±O.o5%
±0.05%
±O.o5%
±0.1%
±0.1%
±O.1%
±3mV
±3mV
±3mV
±5mV
±5mV
±5mV
±20mV
±20mV
±20mV
±20mV
±20mV
±20mV
±4mV
±4mV
±4mV
±8mV
±8mV
±8mV
Temp.
Acquisition
Time (2)
(10V Step, Max)
+2S"C
Temp.
±20mV
±20mV
±20mV
±20mV
±20mV
±20mV
21'sec
21'sec
21'sec
2.5!'5ec
2.5!'5ec
2.5l'sec
±O.5
±O.5
±0.5
±1.5
±1.5
±1.5
±60
±700
±700
±150
±1500
±1500
Pedestal (Max)
Notes:
1. Add '"CH'" to "H/B" models for 100% screening to MIL-H-38534.
2. For the MN346, acquisition time is specified for a final error band of ±O.01%.
For the MN347, acquisition time is specified for a final error band of ±O.05%.
3. The units for droop are ,Ni,.sec.
~
8-16
MICRO NETWORKS
324 Clark St, Worcester, MA 01606 (508) 852-5400
Output Droop
Rate (3) (Max)
MN373
UJJ
_
LOW-COST
HIGH-RESOLUTION
TRACK-HOLD AMPLIFIER
MICRO NETWORKS
DESCRIPTION
FEATURES
MN373 is a high-resolution, moderately high-speed, track-hold
(T/H) amplifier designed to be compatible with all DIP packaged
14-16 bit NO converters available today. Some of the performance specifications that make MN373 ideal for high-resolution
applications are summarized below:
• Low Cost
• Compatible with All
DIP Packaged 14-16 Bit AID's
• 10!-,sec Max Acquisition
Time (10V Step to ±O.003%)
• 1nsec Aperture Jitter
• ±O.25!-'V/!-'5ec Max Droop
• ± 1mV Max Offset Error
• 84dB Feedthrough Attenuation
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
Specification
Gain Linearity Error
Gain Accuracy
Gain Drift
Offset Voltage
Offset Drift
Output Droop Rate
Feedthrough Attenuation
0015(0.38)
1r-
t
n
OQQ~102~J
0012-(030)
I
~-=.J241
0·825[20_96'
~
Jt~0.'-'J!l.4"
(L1..?~l~?Ol I
0.020 (0 51)
IL'0520(13i1jJ~I ~172(4.37)
fJ-Vloe
fJ-VlfJ-Sec
dB
0.082(2.08)
1- o~
Q770{l!.W
o.~60 i 1219j
Units
%FSR
%
ppm/oe
mV
MN373 is packaged in a standard, 14-pin, ceramic dual-in-line
and is TIL compatible. The device contains an uncommitted,
high-impedance (5MO), input buffer amplifier that enables it to
be used in numerous inverting and noninverting configurations
with and without gain. The input stage has a CMV of ± 10V; a
CMRR of 72dB minimum; and an input bias current guaranteed
not to exceed ±300nA. Required power supplies are ±15V, and
maximum power consumption is 390mW.
'D j'
f89
Max.
±0.003
±0.01
±1
±1
±20
±0.25
Dynamic specifications include 1O/lsec maximum acquisition
time (for a 10V step acquired to ±0.003%), 1nsec aperture jitter
and 400kHz small signal bandwidth. MN373's outstanding
±0.25/lVil-tSec maximum output droop rate enables the device to
hold signals to the 14-bit level for up to 2.4msec and to the 16-bit
level for up to 600/lsec. This makes MN373 ideal for highresolution simultaneous-sampling applications.
14 PIN DIP
PlN
Typ.
± 0.001
±0.003
±0.25
±0.25
±3
±0.05
84
Q-'~.Q~
--0230(5.84)
T
~ ~
0300(762)
The standard MN373 is fully specified for O°C to +70°C
(ambient) operation; with MN373H fully specified for -55°C to
+ 125°C (ambient) operation. MN373H/B CH includes 100%
screening to MIL-H-38534.
MN373 mates directly with Micro Networks MN5280/82,
MN5290/91 and MN5295/96 16-bit AID converters. For
military/aerospace applications, MN373H/B can be mated with
MN5290H/B to configure a full 16-bit digitizer with a 20kHz
sampling rate, a 10kHz analog bandwidth, and guaranteed
14-bit no missing codes from -55°C to + 125°C. With MN5295,
it forms a 33kHz digitizer.
Dimensions in Inches
(millimeters)
[1D
_
MICRO NETWORKS
May 1988
324 Clark St.. Worcester, MA 01606 (508) 852-5400
8-17
MN373 LOW-COST HIGH-RESOWTION T/H AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN373
MN373H, MN373H/B
Storage Temperature Range
+ 15V Supply (+ Vcc , Pin 9)
- 15V Supply (- Vcc , Pin 5)
Analog Input Voltage (Pins 1 and 2)
Differential Input Voltage (Pin 1 to Pin 2)
Digital Input (Pin 14)
Output Current (Note 1)
SPECIFICATIONS (TA
-55·Cto +125·C
O·C to + 70·C
-55·C to + 125·C
- 65·C to + 150·C
- 0,5 to + 18 Volts
+ 0.5 to - 18 Volts
± 15 Volts
±20 Volts
- 0.5 to + 7 Volts
±20mA
PART NUMBER
MN373H/B CH
Standard part is specified for O°C to + 70°C
operation.
Add "H" for specified -55°C to + 125°C
operation.---------------'
Add "/B" to "H" models for Environmental
Stress S c r e e n i n g . - - - - - - - - - - - - '
Add "CH" to "/B" models for 100% screening
according to MIL-H-38534. - - - - - - - - - - '
= + 2SoC, Supply Voltages = ± 15V, CH = Internal, Load = lkllllSOpF unless otherwise indicated)
ANALOG INPUT/OUTPUT
MIN.
TYP.
Input/Output Voltage Range
Input Resistance
Input CapaCitance
±10
±11
5
3
Input Bias Current: Initial (+ 25·C)
Over Temperature
Input Offset Current: Initial (+ 25·C)
Over Temperature
± 100
±200
±30
±60
Common Mode Voltage Range
CMRR
±10
72
Output Current (Note 1)
Output Resistance (Hold Mode)
±10
MAX.
UNITS
Volts
Mil
pF
±300
±500
±300
±500
nA
nA
nA
nA
Volts
dB
90
mA
1
Il
Maximum Capacitive Load
250
pF
Output Noise (d.c. to 10M Hz): Track Mode
Hold Mode
150
150
~V(rms)
~V(rms)
DIGITAL INPUTS
Logic Levels: Logic "1" (Hold Mode)
Logic "0" (Track Mode)
+0.8
Volts
Volts
+10
-10
~A
~A
2x 10'
±0.003
±0.001
±0.01
±0.003
V/V
%
%FSR
Offset Voltage (Track Mode)
Pedestal (Note 3)
±0.25
±0.5
±1
±2
mV
mV
Stability: Gain Drift
Offset Drift (Track Mode)
Pedestal Drift
±0.25
±3
± 10
±1
± 20
ppm/·C
8.5
8
7.5
10
9.5
~sec
9
~sec
+2
Loading: Logic "1"
Logic "0"
TRANSFER CHARACTERISTICS (Note 4)
Open Loop Gain (d.c.)
Ga;n Accuracy (G = + 1)
Gain Linearity Error (Note 2)
10'
~V/·C
~V/·C
DYNAMIC CHARACTERISTICS
Acquisition
10V Step
10V Step
10V Step
Time:
10 ± 0.003% (± 0.3mV)
to ± 0.006% (± 0.6mV)
to ± 0.01 % (± lmV)
Track·to·Hold Transient Settling Time:
to ± 0.003%FS (± 0.3mV)
to ± 0.006% FS (± 0.6mV)
to ±O.Ol%FS(±lmV)
~sec
250
225
200
nsec
nsec
nsec
Track·to·Hold Transient
25
mVp·p
Aperture Delay Time
Aperture Jitter
30
1
nsec
nsec
±10
400
V/~sec
Output Slew Rate
Small Signal Bandwidth (- 3dB, G
= + 1)
Output Droop Rate: + 25·C
O·C to +70·C
- 55·C to + 125·C ("H" Models)
Feedthrough Attenuation (10kHz, 10Vp-p input)
8-18
±0.05
±3
± 10
84
kHz
±0.25
±7.5
±20
~V/~sec
~V/~sec
~V/~sec
dB
MIN.
TYP.
MAX.
± 14.5
±15
± 16
POWER SUPPLIES
Voltage Range (Note 5)
UNITS
Volts
Power Supply Rejection: + 15V Supply
-15V Supply
± 0.1
±0.4
Current Drain: + 15V Supply
-15V Supply
10
-10
13
-13
mA
mA
Power Consumption
300
390
mW
mVIV
mVIV
SPECIFICATION NOTES
1. The MN373's output is not short-circuit protected, and shorts to ground
or either supply will result in destruction. In normal operation, continuous output current should not exceed ± 10mA.
2. FSR stands for Full Scale Range and is equal to 20 volts for the MN373.
± O.003%FSR is equivalent to ± 1f2 LSB for a 14-bit system.
3. Pedestal refers to the unwanted step in output voltage that occurs as a
TIH is switched from the track to the hold mode. For many T/H's
pedestal amplitude is a function of input/output voltage level. For the
MN373, pedestal is constant regardless of input/output level. It will vary
as a function of the user-optional external hold capacitor, however.
4. Gain Accuracy, Gain Linearity, Offset Voltage, Pedestal and their
respective drifts are specified for the MN373 in the follower (G = + 1)
configuration.
5. MN373 wifl operate with ± Vee supplies down to ± 10.5V if input/output
voltage is kept below ± 7.5V.
PIN DESIGNATIONS
BLOCK DIAGRAM
Offset Adjust (3) 0 - - - - - ,
Offset Adjust (4)
,-----------......~ (7) Analog Output
(+) tnput (2)
TlH Command (14)
'-----------.J
(8) Compensation
' - - - - - - - - - 0 (6) Anatog Ground
+ 15V Supply
(9)
~
-15V Suppty (5)
~
---.<> (10, 12) NfC
Analog Ground (13) 0 - - - -
1
2
3
4
5
6
7
(-) Input
(+) Input
Offset Adjust
Offset Adjust
-15V Supply
Ground
Analog Output
14
13
12
11
10
9
8
TIH Command
Ground
NIC
External Hold Cap
NIC
+ 15V Supply
Compensation
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracy
and speed performance from the MN373. The unit's two
Ground pins (pins 6 and 13) are not connected to each other
internally. They should be tied together as close to the unit
as possible and both connected to system analog ground,
preferably through a large analog ground plane underneath
the package. If p.c. card ground lines must be run separately, wide conductor runs should be used with 0.01/LF ceramic
capacitors interconnecting them as close to the package as
possible. If your system distinguishes between analog
signal and analog power gounds, pin 6 may be connected to
system signal ground and pin 13 to system power ground.
Coupling between analog inputs and digital signals should
be minimized to avoid nOise pick-up. Care should be taken
to avoid long runs or analog runs close to digital lines.
Power supply connections should be short and direct, and
all power supplies should be decoupled with high-frequency
bypass capacitors to ground. 1/LF tantalum capacitors in
parallel with 0.01/LF ceramic capacitors are the most effec·
tive combination. Single 1/LF ceramic capacitors can be
used if necessary to save board space.
If external hold and compensation capacitors are used, they
should be located as close to the MN373 as possible. If
these capacitors are not used, pins 8 and 11 should be left
open.
DESCRIPTION OF OPERATION-MN373 consists of a high·
speed transconductance amplifier, an analog switch, a hold
capacitor and a high·speed output integrating amplifier.
With uncommitted inverting input, noninverting input and
analog output terminals, MN373 operates as an uncom·
mitted op amp whose output level can be held constant with
the application of a digital control signal. The use of exter·
nal resistors enables one to configure the MN373 in any
number of inverting and noninverting configurations with
and without gain.
The most popular use of the MN373 is as a noninverting,
unity-gain track·hold amplifier. This is achieved by con·
necting pin 1 (Inverting Analog Input) to pin 7 (Analog
Output) and applying the analog input signal to pin 2 (Non·
inverting Analog Input). In this configuration, with a logic
"0" applied to pin 14 (T/H Command), the MN373's output
will track its input. When a logic "1" is applied to pin 14, the
8-19
MN373 is driven into the hold mode holding its output constant at the value that appeared when the hold command
was given.
1.0
0.5
0.2
0.1
~
0.05
ot...
*~
"">.......:...:...1-,~--o ~~~~~~
Analog o--~-l
Input
Command
L_~~:. "'0_ .,
'"
0.01
0
0.005
,
0.002
(~
___ J
'-
"
~
0
I
I
I
TIH
I\~
0.02
"
~
0.001
,
0.0005
"
0.0002
O,QOOl
f
+ 15V
10000
660J1000
100,000
TOlal Hold CdpaCltance (pF)
(Clotal = Clnternal ... CExternal. C Int. = 660pF)
00l.F
Figure 2. Output Droop Rate v.s. HOld CapaCitance
-15V
10
Figure 1. MN373 configured as a follower
(G = + 1) with additional hold capacitance.
MN373 was specifically designed for use with Micro
Networks MN5290, MN5291 and MN5282 16·bit, DIP pack·
aged, AID converters, and its output droop rate is slow
enough to hold a given analog sample to required accuracy
while those devices perform a conversion. If slower droop
rates are required, the MN373 can accept additional hold
capacitance applied to pin 11. A later section describes this
operation in detail.
MN373 can have its track mode offset error or the effect of
its pedestal reduced to zero with the use of an external
potentiometer. This is also described in detail in a later
section.
.
:>
S
-g
~
i"
£
0.5
II\~
0.2
'-
0.1
0,05
"
0.02
"~
~
0.01
....
0.005
....
0.002
0.00 1
ADDITIONAL HOLD CAPACITANCE-MN373 has an inter·
nal 660pF hold capaCitor and published performance speci·
fications are based on this capacitor. If one wishes to
reduce droop rate or pedestal amplitude while trading off
acquisition time, additional hold capacitance may be added
between pins 11 (External Hold Cap) and 7 (Analog Output).
The hold capacitor should have high insulation resistance
and low dielectric absorption, to minimize droop errors.
Polystyrene dielectric is a good choice for operating
temperatures up to + 85 ·C. Teflon and glass dielectrics of·
fer good performance to + 125·C and above. Whenever
additional hold capaCitance is used, additional compensation capacitance equal to one-tenth the additional hold
capacitance must be connected between pin 8 (Compensation) and ground. Exact value and type for this capaCitor are
not critical.
8-20
100.000
Total Hold CapaCitance (pF)
(Clotal
'=
Clnternal + CExternal. Cln!. = 660pF)
Figure 3. Pedestal Amplitude v.s. Hold CapaCitance
100
50
20
10
2
1000 ~
I....
"
~~
1
5
OFFSET ADJUSTMENT -MN373's track-mode offset error
can be reduced to zero using a 20kO potentiometer connected between pins 3 and 4 with its wiper connected to
- 15V. With the analog signal path grounded, the pot should
be adjusted until the output equals zero volts. The pot can
also be used to compensate for the effects of pedestal by
performing the adjustment in the hold mode. This adjust·
ment is normally made while continually switching from
track to hold and observing the TIH output on a scope. This
procedure will eliminate adjustment ambiguities resulting
from output droop.
10.000
660J'000
~
"
I~r
:..\.\o~
2
~c?
O. 1
,
V
L
g
200
~
100
50
"
0.05
500
20
"
10
....
'"~
~
ro
u
0
1+
0
§
£
0.0 2
0.0 1
660J.1OO0
10.000
100.000
Total Hold CapaCitance (pF)
(CTotal = Clnternal + CExternal. C In!. = 66OpF)
Figure 4. Slew Rate and Acquisition Time v.s. Hold CapaCitance
USING MN373 WITH SUCCESSIVE APPROXIMATION AID
CONVERTERS- Successive approximation (SA) type
AID converters are oftentimes severely analog-input-signal
slew-rate and bandwidth limited and can easily produce
errors when used to digitize dynamically changing signals.
The input-signal bandwidth limitations arise from the fact
that successive approximation type AID's sequentially
determine output-bit values (from MSB to LSB) by comparing the analog equivalent of output bits already determined to the instantaneous analog input signal. The conversion process assumes the analog input signal remains
"constant", and analog·input slew-rate and bandwidth
limitations derive from the requirement that input signals
not change more than ± '12 LSB (for the appropriate resolution) during the conversion period.
± '/,LSB
Input Slew Rate Limit =
Conversion Time
Input Bandwidth' =
± 'lzLSB
(Conv. Time)
Input Bandwidth' =
(2~)
(FSR/2)
(FSR/2 n + 1)
(Conv. Time)
(2~)
(FSR/2)
'For full scale sine waves
FSR = AID converter full scale range
n = resolution in bits
These AID converter input-bandwidth limitations can be
greatly overcome by using track·hold (T/H) amplifiers to
track and subsequently "freeze" (hold) analog input signals
that are changing too rapidly for the AID alone to accurately
digitize. If other parameters are appropriate, the slew-rate
and bandwidth limiting factor of the T/H-AID combination
will be the T/H's aperture jitter (aperture uncertainty)
specification, and the T/H-AID combination will now be able
to accurately sample and digitize signals slewing as much
as ± '/2 LSB during the T/H's aperture jitter time. The formulas for determining how fast a signal a given T/H can accurately capture when used in conjunction with a given AID
converter are the same as those stated above with ± '12 LSB
defined for the AID converter and with the variable (conversion time) replaced by (aperture jitter). Needless to say,
aperture jitter is a significantly smaller number than conversion time, and the bandwidth improvement when using the
T/H v.s. not using the T/H will equal the ratio of AID conversion time to T/H aperture jitter.
As an example, consider Micro Networks MN5290 16-bit
AID converter. This device guarantees "no missing codes"
to the 14-bit level, and it performs a 14-bit conversion in
40!,sec (maximum). For this device operating on its full
± 10V input voltage range, ± 'l2LSB (for 14 bits) is
equivalent to ± 0.61 mY, and the analog input slew-rate
limitation is equal to ± '12 LSB/conversion time
±0.61mV/40!,sec = ±0.015mV/!,sec. This is equivalent to
the highest slew rate encountered in a full-scale (± 10V)
sine wave with a frequency of 0.24Hz. When used in conjunction with MN5290, MN373, with its 1nsec aperture jitter,
is capable of capturing signals (to 14-bit accuracy) with
slew rates up to ± V2 LSB/aperture jitter = ± 0.61 mV/nsec
= 610mV/!'sec. This is the highest slew rate one would encounter in a full-scale sine wave with a frequency of 9.7kHz.
As expected, the improvement ratio of 9.7kHz to 0.24Hz is
equal to the ratio of 40!,sec to 1nsec.
Using T/H's in conjunction with AID's to increase analog
bandwidth will reduce throughout (conversion rate) in that
new digital output data cannot be realized until after the T/H
has acquired a new signal (acquisition time) and the AID
has converted it (conversion time). Another consideration
when calculating T/H-AID throughput is the T/H's Track-ToHold Transient Settling Time. If the same timing pulse is
used to put the T/H into the hold mode and initiate the AID
conversion, the transient settling time has to be short
enough to ensure that the AID has a stable, accurate input
when it makes the final decision on whether its MSB output
should be a "I" or "0". This decision normally takes place
one clock period after a conversion has begun.
In the case of using MN373 with MN5290, the AID's MSB is
not set to its final value until approximately 2.5!,sec after a
conversion has begun, and MN373's track-to-hold transient
has long since died away. When using faster AID's, a delay
may have to be added between the time the T/H goes into
hold and the AID begins converting with the consequence
that throughput suffers.
Returning to the MN373-MN5290 combination, the
throughput time will be 50!,sec (10!,sec acquistion time plus
40!,sec conversion time), and the conversion rate will be
20kHz. Comparing this to the 9.7kHz analog bandwidth
leads one to conclude that the MN373-MN5290 pair is
capable of "Nyquist digitizing" 9.7kHz sine waves at a
19.4kHz rate while guaranteeing true 14-bit resolution.
Other considerations when using T/H's with successive
approximation AID's involve the T/H's output stage. In the
hold mode, it should exhibit a very low output impedance
compared to the AID's input impedance (usually 1 to 10kO)
at frequencies up to five times the AID's clock frequency.
Also, the T/H should be able to fully recover (to ± '12 LSB)
from current transients in a time interval smaller than the
AID's clock period. These requirements are based on the
fact that as a successive approximation AID's internal D/A
converter changes its output current just prior to the determination of each output bit, the T/H will be required to sink
or source high frequency current transients and recover
within one clock period. The MN373's output is not current
limited, and in the hold mode, output impedance is typically
below 10. It recovers from output current transients (to
±0.003%FS) in less than 1!,sec.
In most applications using MN373 in front of a successive
approximation AID converter, MN373's T/H Command pin
can be driven directly (or inverted if necessary) from the converter's status output. The status output changes state
when the converter receives a convert command, and this
change can drive the T/H from the track to the hold mode.
The change in state of the AID's status output at the end of
the conversion can put the T/H back into the track mode.
The diagram below illustrates an MN373 mated with an
MN5290 in this manner. Since MN5290's MSB output is not
set to its final value until one clock period (approximately
2.8!,sec) after a conversion begins, MN373's track-to-hold
transient will be completely settled, and no extra timing
precautions are necessary.
8-21
+ 15V
R,
Offset
Adjust
r---------141
-15V
~
15V
+ 5V
~~-------l
MN373
R,
1221'~----,,.....o MSB
MN5290
>--4-
1::.;71+-'>-_--1191
I
I
161'~---',.....o LSB
I
I
Analog
Input
I
_____ JI
(8)
Start
Convert
Status
CorlVerllng
"1"
"0"
+ 15V
L
= Hold
= Track
- 15V
Figure 5. Combine MN373 with MN5290 to make a 14·bit digitizer with
a 20kHz update rate, a 10kHz analog-signal bandwidth, and 14-bit no
missing codes guaranteed over temperature.
USING MN373 TO DEGLITCH HIGH· RESOLUTION
CURRENT·OUTPUT D/A CONVERTERS-Virtually all
digital·to·analog (DIA) converters exhibit output transients,
affectionately know as glitches, when changing output
levels in response to digital-input code changes. The
primary causes of glitches are unequal digital-data arrival
and delay times, know as data skew, and asymmetrical
switch turn-on and turn-off times. The largest glitches occur
when major-carry code changes are made. In particular, the
worst-case glitch occurs at half scale when the input-code
change is from 0111 ... 1 to 1000... 0 or vice versa. Asymmetrical switch turn-on and turn-off delays may result in
momentary slewing to the 0000 ...0 or 1111 ... 1 output level
until all switches achieve their final state. The binarilyweighted nature of the current switches internal to most
D/A converters makes glitch slew rate and amplitude vary
from transition to transition, and consequently makes glitches extremely difficult to remove with filtering. DIA con·
verter output glitches mayor may not be a problem depending upon application. In long time-constant servo applications, they will not be a problem. In high-speed, highresolution waveform generators, they can cause severe harmonic distortions.
A deglitcher is a specially designed TIH amplifier capable of
considerably reducing D/A glitch amplitude and, perhaps
more importantly, making all glitches the same regardless
of digital·code change. MN373 works well as a deglitcher
because it has a small 25mV switching transient, and if it
used to deglitch a current-output D/A, it can also act as an
output amplifier supplying current-to-voltage conversion.
8-22
A TIH amplifier used as a deglitcher is connected to the output of the DIA and is kept in the track mode whenever the
DIA output is stable. Just prior to the arrival of new digital
data, the T/H is commanded to the hold mode to hold its
output constant while the D/A's output (the TIH's input) is
changing levels and experiencing its glitches. The TIH is
then put back into the track mode to acquire and track the
new DIA output.
The diagram on the next page illustrates MN373 performing
both deglitching and current-to-voltage conversion for a
current-output, 16-bit D/A converter (MNDAC71-COB·I).
MN373's high-impedance input buffer allows the currentoutput DIA to work into a virtual ground, and the DIA's internal feedback resistor is put into MN373's feedback loop.
The 16-bit D/A guarantees ± 0.003%FSR maximum linearity
error, and MN373's linearity error is commensurate.
MN373's ± 10mA minimum output current is enough to
drive the feedback resistor and the load. MN373's acquisition time is equal to the DIA's settling time when used
without a deglitcher so update rate is not compromised.
MN373's outstanding feedthrough attenuation ensures that
very little of the actual DIA glitch feeds through to the T/H
output, and the unit's low output droop rate ensures that
output change will be less than ± 2.5p.V during the approximately 10p.sec that MN373 is in the hold mode.
MNDAC71·COB·1
MSB
(1)
-15V Offset
Adjust
(20) Cap
(18)
(19) \-----4-+--1
(23)~---_...,
Bit 8
(8)
(17)
Bit 9
(9)
I
:>~~(7~)~I_~--o ~~~~~~
1
±1mA
I
LSB
Strobe
Clk
(16)
~_t(9)-
(5)
(13)
l"F
0------------------1
o 011-:"F::t----1
O.Ol"F
+15V -15V
X'-_________
DIA Input _______
DIA Output
DIA Settling Time
TIH Command
Track
Hold
Track
TIH
Acquisition
Time
TIH Output
-----J\r------J
Figure 6. Use MN373 with high·resolution current·output DIA
converters to perform both current-ta-voltage conversion and
output deglitching.
8·23
SUMMARY OF TRACK·HOLD PERFORMANCE PARAMETERS
Analog Input
~:::;::-~,
+10V-
,,
~qUjsjtjon
Time
- - - - - - - - --
Analog O u t p u t - - - - -
,,
,,
,,
,
.oo,::,~ral/.'. FeedrOU9h
(20V step to
±O.01% FSR)
DIP
i r---------r----I
OV--
•
I
•
j.- Aperture Delay
\
.. _'
I
Slew Rate
-10VLqgic"1"-
Logic "0"-
l
HOld Mode
Track Mode
L--.-_ _ _
into the track mode. A logic "1" puts it into the hold mode.
See the tutorial section of the Micro Networks catalog for
a detailed discussion of T/H performance specifications.
Summary of T/H specifications. The broken line is the
T/H's analog input. The solid line shows its analog output.
The T/H has a ± 10V analog input range. The lower trace is
the digital T/H command signal. A logic "0" puts the T/H
Analog Input
----- - - - ---
Analog Output - - - -
Offset Error
(Hold mode)
-
Track ~
Hold
Summary of Offset (Track Mode), Offset (Hold Mode) and
Pedestal Errors. Broken line is T/H analog input. Solid line
is analog output. Analog input level equals zero volts.
[1J]
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852·5400
8-24
MN374
HIGH-SPEED
HIGH-RESOLUTION
TRACK-HOLD AMPLIFIER
l_1JJ MICRO NETWCRKS
DESCRIPTION
MN374 is a high-speed (4J.1sec max acquisition time for a 20V
step acquired to ± 0.003%), high-resolution (± 0.003%FSR max
linearity error), unity-gain, inverting track-hold (T/H) amplifier
designed to be compatible with virtually all DIP-packaged,
14-16 bit AID converters available today. In particular, MN374
mates well with Micro Networks MN5290/5291 (40J.lsec, 16-bit
AID's) and MN5295/5296 (17J.!Sec, 16-bit AID's) as well as
with other industry-standard 16-bit AID's (ADC71/72, ADC76,
AD376, etc.).
The TIL-compatible MN374 makes the speed/precision trade-off
very well. Its impressive d.c. specifications include a maximum
± 0.02% gain error, a maximum ± 3mV offset error and a maximum ± 4mV pedestal. Dynamic specifications include 4p.sec
max acquisition time (20V step acquired to ± 0.003%); 3J.1sec
max track-to-hold transient settling time (to ± 0.003%FSR);
400psec aperture jitter; and ± 30V/J.!Sec slew rate. MN374's
outstanding ± 1J.lV/J.!Sec maximum output droop rate enables
the device to hold signals to the 14-bit level for up to 600J.lsec
and to the 16-bit level for up to 150p.sec. These performance
levels make MN374 ideal for high-resolution data acquisition in
either single-channel, multichannel sequenced, or multichannel
simultaneous-sampling applications.
An application note in this data sheet describes how to mate
MN374 with MN5295 (16-bit, 17J.!Sec AID) to create a 40kHz
sampling AID that guarantees 14-bit "no missing codes"
over its full temperature range.
FEATURES
• 4/lsec Max Acquisition Time
(20V Step to ±O.003%)
• Compatible with All DIP
Packaged 14-16 Bit AID's
• 400psec Aperture Jitter
• ±1/lV/J.LSec Max Droop Rate
• 90dB Min Feedthrough
Attenuation
• Small 14-Pin DIP
• Pin and Function
Compatible with SHC76
• Full Mil Operation
-55"C to +125"C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
'O j'
14 PIN DIP
PIN
f89
0.01510.3811t-
0.770(19.56)
D.625 120 961
n
0.020(0.51)
l
LO.520(13.21jJ
O.OO9~l
o.Ot2(O.30)
~
t
I
--.1::1'
"
~ utQ!!~ll
0.480(12.19)
,
0.082(2.08)
1- D~
~.172(4.37}
!!:,.126 (3.20)
0.200(5.08)
D.23O,S"1
T
MN374 is packaged in a small, 14-pin, single-wide, ceramic
DIP, and it carries the pinout that has become the de facto
standard for high-resolution T/H's. MN374 is fully specified
for either O°Cto +70°Cor -55°C to +125°C("H" model)
operation. For military/aerospace or harsh-environment
commercial/industrial applications, MN374H/B CH is fully
screened to MIL-H-38534 in Micro Networks' MIL-STD-1772
qualified facility.
Contact factory for availability of CH devices.
-l
0.300(7.62)
Dimensions in Inches
(millimeters)
O::JJ
_
MICRO NETWORKS
January 1992
CopyrightCcJ1992
Micro Networks
All rights reserved
324 Clark St, Worcester, MA 01606 (508) 852·5400
8·25
MN374 HIGH-SPEED HIGH-RESOWTION T/H AMPLIFIER
ORDERING INFORMATION
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN374
MN374H, MN374H/B
Storage Temperature Range
+ 15V Supply (+Vcc, Pin 11)
-15V Supply (-Vcc, Pin 14)
Analog Input (Pin 13)
Digital Input (Pin 1)
Output Current (Note 1)
-55°C to +125°C
OOCto +70°C
-55°C to +125°C
-65°Cto +150°C
-0.5 to +18 Volts
+0.5 to -18 Volts
± 15 Volts
-0.5 to +7 Volts
±20mA
PART NUMBER - - - - - - - - - - - 374H/B CH
Standard part is specified for
O°C to + 70°C operation.
Add "H" for specified -55°C to + 125°C
operation. _ _ _ _ _ _ _ _ _ _ _ _ _ _-1
Add "/B" to "H" models for Environmental
Stress S c r e e n i n g . - - - - - - - - - - - _ - - - '
Add "CH" to "B" models for 100%
screening according to MIL-H-38534.----------'
Contact factory for availability of "CH" devices.
SPECIFICATIONS (TA = +25OC, ± Vee = ± 15V unless otherwise indicated)
ANALOG INPUTS
MIN.
TYP.
Input/Output Voltage Range
Input Impedance (Note 2)
±10
±11
3
Volts
kG
Output Current (Note 1)
Output Impedance (Note 2)
±5
1
mA
G
250
pF
Maximum Capacitive Load (Note 2)
MAX.
UNITS
DIGITAL INPUT
Logic Levels: Logic "1" (Track Mode)
Logic "a" (Hold Mode)
+0.8
Volts
Volts
+20
-0.4
pA
mA
+2.0
Logic Currents: Logic "I" (VIH = +2.7V)
Logic "a" (VIL +0.4V)
=
TRANSFER CHARACTERISTICS (Note 3)
Gain
-1
VN
Gain Linearity Error
±0.001
±0.003
%FSR
Gain Accuracy: Initial (+25°C)
Drift (Note 6)
Error @ Tmln or Tmax (MN374H, H/B)
±om
±1
±0.02
±0.02
±5
±0.07
%
ppmloC
%
Offset Voltage (Track Mode, Note 4): Initial (+25°C)
Drift (Note 6)
Error @ Tmin or Tmax (MN374H, H/B)
±0.5
±5
±1
±3
±20
±5
poVloC
Pedestal (Note 5): Initial (+25°C)
Drift (Note 6)
Error @ Tmin or Tmax (MN374H, H/B)
±2
±10
±3
±4
±40
±8
poV/oC
Acquisition Time:
20V Step to ± 0.003% (± O.6mV)
20V Step to ± 0.01% (± 2mV, Note 2)
IOV Step to ± 0.003% (± O.3mV, Note 2)
10V Step to ± 0.01% (± lmV, Note 2)
2.5
1.5
3
1.2
4·
3
Track-to-Hold Transient (Note 2):
Amplitude
Settling Time to ± 0.003% FSR (± 0.6mV)
Settling Time to ± 0.01% FSR (± 2mV)
200
0.5
0.3
Aperture Delay Time (Note 2)
Aperture Jitter (Note 2)
30
400
nsec
psee
Output Slew Rate (Note 2)
Small Signal Bandwidth (-3dB, Note 2)
Full Power Bandwidth (Note 2)
±30
1.5
500
V/poSee
Output Droop Rate: +25°C
O°C to +7O°C
-55OCto +125°C ("H" Models)
±0.1
±10
±50
mV
mV
mV
mV
DYNAMIC CHARACTERISTICS
Feedthrough Attenuation (20kHz, 2OVp-p input)
90
Output NOise (d.e. to lMHz, Note 2) Track Mode
Hold Mode
3
2
poSec
poSec
poSec
posec
mV
posec
poSec
MHz
kHz
±1
±100
±500
poV/p.Sec
poV/poSec
poV/poSee
100
dB
200
200
poV(rms)
poV(rms)
POWER SUPPLIES
Voltage Range (Note 7)
±14.5
±15
Power Supply Rejection: +15V Supply
-15V Supply
±75
±75
Quiescent Current Drain: +15V Supply
-15V Supply
+15
-11
Power Consumption
390
8-26
±15.5
Volts
poVN
poVN
+24
-13
495
mA
mA
mW
SPECIFICATION NOTES:
1.
2.
3.
4.
MN374'S output is not short-circuit protected. Continuous shorts to ground or
instantaneous shorts to either supply will result in destruction. In normal operation,
continuous output current should not exceed ± 10mA.
These parameters are listed for reference only and are not tested.
FSR slands lor full scale range and is equal 10 20 VoIIS lor the MN374. ± 0.003%FSR
is equivalent to ± 'hLSB for a 14·bit system.
Initial track-mode offset error is adjustable to zero with a user-optional external
potentiometer. The offset adjust may also be used to compensate for pedestal. See
5.
6.
7.
Pedeslal refers to the unwanted step in output \'ollage that occurs as a T/H is
switched from the track to the hold mode. For many T/H's, pedeslal amplitude is
a function of inputloutput vollage level. For the MN374, pedestal is conslant
regardless of inputloutput level.
MN374 is fully specified for DoC to +70°C operation. MN374H and MN374H/B are
fully specified for -55°C to + 125°C operation.
MN374 will operate with ± Vcc supplies down to ± 11.4 Volts if inputloutput vollage
is kept below ± 7.5V.
Offset Adjustment.
BLOCK DIAGRAM
3kl)
Offset Adjust (7)
0-------+-----,
Offset Adjust (9)
0----------11-----,
Summing Junction (12)
0-----""'-
Analog Input (13) o---'VV\r--~~--i
>--4>----0. (8) Analog Output
~---------------------+--~>---------------------_o(6)Gmund
"'<=--------<0
T/H Command (1)
(11) +15V Supply
0----1
"'<~--------o (14) -15V Supply
"1" = Track
Ground (4)
0-----------'
"0"
=
Hold
No Connects 2, 3, 5, 10
PIN DESIGNATIONS
•
PIN 1
14
1
2
3
4
5
6
7
7
T/H Command
No Connect
No Connect
Ground
NoConnect
Ground
Offset Adjust
14
13
12
11
10
9
8
-15VSupply(-Vcc)
Analog Input
Summing Junction
+15V Supply (+Vcc)
No Connect
Offset Adjust
Analog Output
8
8-27
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified accuracy and speed
performance from the MN374. The unit's two Ground pins (pins 4
and 6) are not connected to each other internally. They should be
tied together as close to the unit as possible and both connected
to system analog ground, preferably through a large analog ground
plane underneath the package. If p.C. card ground lines must be run
separately, wide conductor runs should be used with 0.01 p.F ceramic
capaCitors interconnecting them as close to the package as
possible. If your system distinguishes between analog and digital
ground, pin 6 may be connected to system analog ground and pin
4 to system digital ground.
Coupling between analog inputs and digital signals should be
minimized to avoid noise pick-up. Care should be taken to avoid long
runs or analog runs close to digital lines. Input and output signal
lines should be kept as short as possible, and if external offset
adjustment is used, the potentiometer should be located as close
to the unit as possible. If offset adjust is not used, pins 7 and 9 should
be left open.
Power supply connections should be short and direct, and all power
supplies should be decoupled with high-frequency bypass
capacitors to ground. 1p.F tantalum capacitors in parallel with 0.01 p.F
ceramic capacitors are the most effective combination. Single 1p.F
ceramic capacitors can be used if necessary to save board space.
OFFSET ADJUSTMENT-MN374's track-mode offset error can be
reduced to zero using a 10kO to 20kO potentiometer connected
between pins 7 and 9 with its wiper connected to -15V. With the
analog signal path grounded, the pot should be adjusted until the
output equals zero volts. The pot can also be used to compensate
for the effects of pedestal by performing the adjustment in the hold
mode. This adjustment is normally made while continually switching
from track to hold and observing the T/H output on a scope. This
procedure will eliminate adjustment ambiguities resulting from
output droop.
TRACK-HOLD COMMAND-A TIL logic "1" applied to pin 1 will
put the MN374 into the track (sample) mode. In this mode, the device
acts as an inverting unity-gain amplifier, and its output will follow
(track) its input. A logic "0" applied to pin 1 will put the MN374 into
the hold mode, and after the switching transient settles, the output
will be held constant at the level present when the hold command
was given.
USING MN374 WITH SUCCESSIVE APPROXIMATION AID
CONVERTERS-Successive approximation (SA) type AID
converters are oftentimes severely analog input slew-rate and
bandwidth limited and can easily produce errors when used to
digitize dynamically changing signals. These input-signal bandwidth
limitations arise from the fact that successive approximation type
AID's sequentially determine output-bit values (from MSB to LSB)
by comparing the analog equivalent of output bits already
determined to the instantaneous analog input signal. The
conversion process demands that the analog input signal remain
"constant", and the analog input slew-rate and bandwidth limitations
derive from the requirement that input signals not change more than
± '12 LSB (for the appropriate resolution) during the conversion
period.
These AID converter input-bandwidth limitations can be overcome
by using track-hold (T/H) amplifiers to track and subsequently
"freeze" (hold) analog input signals that are changing too rapidly
for the AID alone to accurately digitize. If other parameters are
appropriate, the slew-rate and bandwidth limiting factor of the T/HAID combination will become the T/H's aperture jitter (aperture
uncertainty), and the T/H-AID combination will now be able to
accurately sample and digitize signals slewing as much as ± 'hLSB
during the T/H 's aperture jitter time. The formulas for determing how
fast a signal a given T/H can accurately capture when used in
8-28
Input Slew Rate Limit
±'hLSB
Conversion Time
Input Bandwidth" =
+ 'hLSB
(Conv. Time) (2'11') (FSR/2)
Input Bandwidth" =
(FSR/2" + ')
(Conv_ Time)(2'11')(FSR/2)
"For full scale sine waves
FSR = AID converter full scale range
n = resolution in bits
conjunction with a given AID converter are the same as those stated
above with ± 'hLSB defined for the AID converter and with the
variable (conversion time) replaced by aperture jitter. Needless to
say, aperture jitter is a significantly smaller number than conversion
time, and the bandwidth improvement when using the T/H vs. not
using the T/H will equal the ratio of AID conversion time to T/H
aperture jitter.
As an example, consider Micro Networks MN5295 16-bit AID
converter. This device guarantees "no miSSing codes" to the 14-bit
level, and it performs a full 16-bit conversion in 17p.Sec (maximum).
For this device operating on its full ± 10V input voltage range,
± 'hLSB/conversion time = ±0.61mVl17p.Sec = ±0.036mVlp.Sec
(calculated for a 14-bit LSB). This is equivalent to the highest slew
rate encountered in a full-scale ( ± 10V) sine wave with a frequency
of 0.57Hz. When used in conjunction with MN5295, MN374 with its
400psec aperture jitter, is capable of capturing signals (to 14-bit
accuracy) with slew rates up to ± 'hLSB/aperture jitter =
±0.61mVl400psec = ±1.525V1p.Sec. This is the highest slew rate
one would encounter in a full-scale sine wave with a frequency of
24.3kHz. As expected, the improvement' ratio of 24.3kHz to O.57Hz
is equal to the ratio of 17p.Sec to 400psec.
USing T/H's in conjunction with AID's to increase analog bandwidth
will reduce throughput (conversion rate) in that new digital output
data cannot be realized until after the T/H has acquired a new signal
(acquisition time) and the AID has converted it (cunversion time).
Another consideration when calculating T/H-AID throughput is the
T/H's Track-to-Hold Transient Setting Time. If the same timing pulse
is used to put the T/H into the hold mode and initiate the AID
conversion, the transient settling time has to be short enough to
ensure that the AID has a stable and accurate input when it makes
the final decision on whether its MSB output should be "1" or "0".
This decision normally takes place one clock period after a
conversion has begun.
Other considerations when using T/H's with successive
approximation AID's involve the T/H's output stage. In the hold
mode, it should exhibit a very low output impedance compared to
the AID's input impedance (usually 1 to 10kO) at frequencies up to
five times the AID's clock frequency. Also, the T/H should be able
to fully recover (to ± '12 LSB) from current transients in a time interval
smaller than the AID's clock period. These requirements are based
on the fact that as a successive approximation AID's internal D/A
converter changes its output current just prior to the determination
of each output bit, the T/H will be required to sink or source high
frequency current transients and recover within one clock period.
The MN374 output is not current limited, and in the hold mode,
output impedance is typically below 10. It recovers from output
current transients (to ± 0.003%FSR) in well under 1p.Sec.
For slower speed AID converters, the most popular technique
used to control the T/H's operation is to drive the T/H directly
with the AID's status line. For virtually all high-resolution
AID's in use loday, including MN5295/5296, this technique
does not work because the T/H's track-Io-hold transients will
not reliably settle fast enough. The application described
below is a much more cautious way to control the T/H-AID
timing because it uses a timed one-shot to delay the start of
the AID conversion. The circuit allocates a predetermined
amount of time for the track-to-hold transient to fully settle
before initiating the AID conversion. After the conversion has
been completed, the circuit immediately drives the T/H back
into the track mode.
The principles discussed below are general and can be used
for virtually any T/H-AID combination. The system is run by an
externally applied clock whose frequency determines the
overall sampling/digitizing rate. Please refer to the timing
and schematic diagrams below as well as the MN5295/96
data sheet.
The system consists of the AlD, the T/H, a single one-shot and
a dual flip-flop. The falling edge of the system clock triggers
the 74LS123 one-shot, and the system clock can have any
duty cycle as long as it has a minimum positive pulse width of
50nsec to accommodate the setup-time requirement of the
one-shot.
The one-shot produces a 500nsec pulse, and both the Q and Q
outputs are utilized. The Q o..!ltput becomes the start pulse for
the MN5295/5296, and the Q output drives the set pin of the
first half cif the 74LS74 flip-flop. The Q1 output of the flip-flop
controls the_operational mode of the MN374 T/H. The falling
edge of the Q output of the 74LS123 asynchronously sets the
flip-flop driving its Q1 output high and its Q1 output low. The
MN374, which has an active-low control line, is immediately
driven into its hold mode by the falling edge of Q1.
The pulse width of the 74LS123 has been selected so that
there is now ample time for the M N37 4 track-to-hold transient
to fully decay before the AID conversion begins. After
500nsec, the Q output of the one-shot drops to "0" initiating
the AID conversion, and driving the Status output (pin 1)ofthe
AlD to ~ "1". The T/H remains in hold because the riSing edge
of the Q output of the one-shot does not affect the first flipflop. The riSing edge of Status asynchronously resets the second flip-flop driving the Q2 output low.
The T/H remains in the hold mode for the next 17!,sec as the
AID completes its ·conversion. At the end of the conversion,
the AID's Status line drops to a "0", and this sets the second
flip-flop. The Q2 output goes high clocking the first flip-flop
which h~a "0" on its D line. This forces the Q1 output low
and the Q1 output high driving the T/H back into the signalacquisition (track) mode.
The status of this system can be monitored at a number of
different points. Whenever pin 1 (Status) of MN5295/5296 is a
logic "1 ", the AID is performing a conversion, and output data
is not valid. The falling edge of this line signals that the conversion is complete and that output data is now valid. The Q1
output of the first flip-flop can be used to monitor the T/H.
Whenever this line is a "1 ", the T/H is in the hold mode. When
it is a "0", the T/H is in the track mode. The falling edge here
also indicates that a conversion has just been completed and
that output data is now valid. If an external latch is to be used
to clock data away from MN5295/5296, either of the falling
edges described above may be used to strobe the latch.
Remember that the above application does not automatically
take care of the T/H acquisition time and that this time must
be allowed for in determining the external clock period. If the
MN5295/5296 requires 17!,sec to make a conversion, and the
T/H requires 4!,sec for acquisition time, adding 2!,sec of overhead time yields a period of 23!,sec. That means the system
can be clocked at 43kHz and still be guaranteed to meet full
accuracy and linearity performance.
It is unnecessary to have the 74LS123 one-shot in the application if the externally applied clock can be made to be a
series of 50nsec-wide positive pulses occurring at a 43kHz
rate. In other words, if the clock can be made to look like the
output of the one-shot in our timing diagram, it is unnecessary to have the one-shot. The clock can drive the MN52951
5296 directly, and it can be inverted to drive the 74LS74.
MN374
+15V-15V +5V
+15V -15V
(11)
Analog
Input
1141
1131
14.6)
(8)
"
I - - - - - - - c AJD SlaWs
System
Clock
L..._ _ _ _ _ -o TIHSlatus
+5V
IC2=74LS74
I
23Jlsec
Clock
n
-.fl
74LS1230
74LS123 Q
AJDStatus
01
T/H Status
Converting
Data Valid
~
Hold
Track
----.J
Hold
Track
I
8-29
l1:O MICRO NETVVORKS
[!cJJ MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852-5400
8-30
MN376
UJJ
_
200nsec
12-Bit LINEAR
TRACK-HOLD AMPLIFIER
MICRO NETWORKS
DESCRIPTION
FEATURES
MN376 is an extremely high-speed track-hold (sample-hold)
amplifier. Its 200nsec maximum acquisition time (to ±O.01%)
and 100nsec maximum track-to-hold transient settling time
enable it to deliver accurate, 12-bit linear, analog samples at a
3.3MHz rate. Its ±5p.V/pSec maximum droop rate enables it to
hold acquired signals to 12-bit accuracy for periods longer than
200p.sec. Its ±20psec aperture jitter (40psec total aperture window) enables it to accurately sample full scale analog signals
with frequencies up to 1MHz, while its 16MHz small-signal bandwidth and 300V/pSec slew rate obviously enable it to accurately
track much faster smaller-scale signals. In the hold mode, inputoutput feedthrough attenuation is specified at 78dB (better than
'hLSB in 12 bits) at 2.5MHz.
• 200nsec Max Acquisition Time
10V Step to ±O.01%
• 100nsec Max Track-to-Hold
Settling Time
• ±20psec Aperture Jitter
• Use with MN5245/46 for 1MHz
12-Sit AID Conversions;
with MN5249 for 2MHz
• 78dS Feedthrough Attenuation
• TTL Compatible
• Pin-Compatible MN0300A,
HTC-0300A, TP4860
MN376 is designed to be used with Micro Networks high-speed
12-bit AID's to configure high-throughput, broadband,
sampling/digitizing systems. It can be used with MN5245 or
MN5246 (850nsec 12-bit AID's) to configur~ a bonafide 1MHz
sampling AID with a 500kHz input bandwidth or with MN5249
(400nsec 12-bit AID) to form a 2MHz digitizer with a 1MHz
bandwidth.
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
24 PIN DIP
~\I.-N~_ _ _--,
0.015 (0.38)
0.035 (0.891
T
--I 1_
~
0.087 (2.211
0.115 (2.92)]
~254)
1100(27,94)
L'- - - ~-7 o".- '~l : l-d
!-
0.810(20.57)
-I
i-----i~
U
~::!~~:::
f.O.12013.0S)
0.170 (4.32)
\..- 0.600(15.24)-./
Dimensions in Inches
(millimeters)
~
Unlike many high-speed T/H's available today, MN376 fully
guarantees acquisition time and track-to-hold settling time (a
T/H's two throughput limiting specifications) to ±O.01%FS
(equivalent to ±O.005% FSR or ±1mV) and not to only ±O.1%
or ± 1%. A 24-pin dual-in-line package, a gain of -1, an
input/output range of ± 10V, and TTL compatibility make the
MN376 pin compatible with Micro Networks MN0300A, Analog
Devices/Computer Labs HTC-0300A, and industry-standard
4860 type high-speed T/H's.
MN376 is designed to be used without external adjustments. Its
thin-film nichrome resistors are actively laser trimmed to
minimize gain (±O.05%), offset (±O.5mV) and pedestal
(±2.5mV) errors. The stability of those resistors minimizes gain
(±O.5ppm/°C), offset (±3ppm of FSR/°C) and pedestal (±4ppm
of FSR/°C) drifts with temperature. Low power consumption
(875mW maximum) enables full DoC to +70°C (MN376) or
-55°C to +125°C (376 H, H/B) ambient operation. Optional
MIL-H-38534 screening makes the MN376H/B CH ideal for most
military/aerospace high-speed sampling applications.
May 1988
MICRO NETWORKS
324 Clark Sl.. Worcester. MA 01606 (508) 852·5400
8·31
MN376 200nsec 12·Bit LINEAR T/H AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Operating Temperature Range
Specified Temperature Range:
MN376
MN376H, MN376H/B (Note 3)
Storage Temperature Range
± 15V Supply Voltage (± Vee, Pins 24, 22)
+ 5V Supply Voltage (+ Vdd, Pin 9)
Analog Input (Pin 13) (Note 1)
Digltallnputs,(Pins 11,12)
Output Currerit (Note 2)
SPECIFICATIONS (TA
= + 25°C,
-55"Cto +125"C
PART NUMBER
Supply Voltages ± 15V and + 5V unless otherwise indicated)
ANALOG INPUTIOUTPUT
MIN.
TYP.
Input/Output Voltage Range
Input Impedance (Note 10)
±10.25
±11.5
1
Volts
kll
Output Current (Note 2)
Output Impedance (Note 10)
±20
0.1
mA
Il
100
pF
Maximum Capacitive Load (Note 10)
MAX.
UNITS
DIGITAL INPUTS
Logic Levels (Note 4): Logic "1"
LogiC "0"
+0.8
Volts
Volts
1
TTL Load
+2.0
Loading (Note 5)
TRANSFER CHARACTERISTICS
Gain
Gain Accuracy
Gain Linearity Error(Note 6)
-1
±0.05
±0.005
±0.1
±0.01
V/V
%
%FS
Offset Voltage (Track Mode)
Pedestal (Note 7)
±0.5
±2.5
±5
±20
mV
mV
Stability: Gain Drift
Offset Drift (Track Mode)
Pedestal Drift
±0.5
±3
±5
±5
±15
ppm/"C
ppm of FSR/"C
ppm of FSR/"C
Acquisition Time (Notes 6, 8):10V Step to ±0.01%FS (± 1mV)
10V Step to ±0.1%FS (± 10mV)
10VStepto ±1%FS(±1OOmV)
5V Step to ±0.01%FS (±0.5mV)
1V Step to ±1%FS(±100mV)
160
80
60
120
60
200
170
nsec
nsec
nsec
nsec
nsec
Settling Time, Track·to-Hold (Note 9): to ± 0.005% FS (±0.5mV)
to ±0.01%FS(±1mV)
to ±0.1%FS(±10mV)
60
50
30
130
100
Track-to·Hold Transient (Note 10)
180
mVp·p
6
DYNAMIC CHARACTERISTICS
160
nsec
nsec
nsec
Aperture Delay Time (Note 10)
Aperture Jitter (Note 10)
±20
nsec
psec
Output Slew Rate (Note 10)
Small Signal Bandwidth (- 3dB, Note 10)
±300
16
V/p.sec
MHz
Large Signal Bandwidth (Notes 10, 11): 100kHz
500kHz
1MHz
2MHz
-90
dB
dB
dB
dB
Droop: +25"C
+70"C
+125"C
±0.5
±15
±1.2
Feedthrough Attenuation (20Vp·p input): 100kHz
500kHz
1MHz
2.5MHz
8-32
-90
-84
-75
84
84
80
70
78
I
MN376H/B CH
Standard Part is specified for
~
O°C to +70°C Operation.
Add "H" for specified -55°C to + 125°C
operation.-------Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.
O"Cto +70"C
-55"Cto +125"C
- 65"C to + 150"C
± 18 Volts
-0.5 to + 7 Volts
±18Volts
- 0.5 to + 5.5 Volts
±50mA
±5
p.V/p.sec
p.V/p.sec
mV/p.sec
dB
dB
dB
dB
POWER SUPPLIES
Voltage Range: ± 15V Supplies
+5V Supply
MIN.
TYP.
±3
±5
Power Supply Rejection Ratio
±0.5
Quiescent Current Drain: + 15V Supply
-15V Supply
+5V Supply
Power Consumption
+21
-22
+17
730
MAX.
UNITS
%
%
mVN
mA
mA
mA
+25
-25
+25
875
rrWV
SPECIFICATION NOTES:
1. Analog input signal should not exceed supply voltage.
2. The MN376's output is current limited at approximately ± 50mA and can
amplitude is a function of input/output voltage level. For the MN376,
pedestal is constant regardless of input/output level.
8. Acquisition time is tested with no load and is relatively unaffected by
capacitive loads to 50pF and reSistive loads to 5000.
9. Track·to-hold settling time refers to the time interval between the point at
which a device is commanded from the track to the hold mode and the
point at which the analog output (following a tranSient) settles to within a
specified error band around its final value.
withstand a sustained short to ground. Shorts to either supply will result
in destruction. In normal operation. load current should not exceed
±20mA.
3. The MN376H/B is specified for -55'C to + 125'C operation and is processed and screened to the requirements of MIL·STD·883, Method 5008.
4. See Applications Information for use of Hold and ROId inputs.
5. One TIL load is defined as sinking 40"A with a logic "1" applied and
sourcing 1.6mA with a logic "0" applied.
6. FS stands for Full Scale and is equivalent to 10 volts. FSR stands for Full
Scale Range and is equivalent to 20 volts. For a 12·bit system, 1
10. These parameters are listed for reference only and are not tested.
11. Listed specification is the peak of the highest observed harmonic (usually the
second) in the output spectrum. Measured in the track mode with a full scale in~
put signal at the frequencies indicated.
LSB~0.024%FSR.
7. Pedestal refers to the unwanted step in output voltage that occurs as a
T/H is switched from the track to the hold mode. For many TlH's, pedestal
BLOCK DIAGRAM
PIN DESIGNATIONS
•
1kU
24
PIN 1
1kll
Analog Input (131
O---"""M---+---,
>-~--o (1) Analog Output
Ground (15)
12
~
13
---------0 (21) Ground
Hold
(11)
Command
~
Co~~~nd (12)
Ground (10) ~
..
1 Analog Output
"'"""
(24) -+- 15V Supply
1221 - 15V Supply
O.Ol/IF
II
I
I
I
0 (23) Ground
2
3
4
5
6
7
8
9
N/C
N/C
N/C
N/C
N/C
N/C
N/C
+ 5V Supply
10 Ground
11 HOld Command
12 ROia Command
24
23
22
21
20
19
18
+ 15V Supply
Ground
-15V Supply
Ground
N/C
N/C
N/C
17 N/C
16 N/C
15 Ground
14 N/C
13 Analog Input
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING-With proper grounding
and bypassing, the MN376 will meet all its published performance specifications without any additional external
components. The device has four Ground pins (pins 10, '15,
21 and 23). All must be tied together and connected to
system analog ground as close to the package as possible.
It is preferable to have a large analog ground plane beneath
the MN376 and have all four ground pins soldered directly to
it. Pin 10 is particularly groundnoise sensitive because in
the actual construction of the MN376, most of the digital
elements that constitute the switch drive circuit are
grounded to pin 10. Noise in the switch drive circuit couples
directly through to the main op-amp summing junction-the
most noise sensitive point in any T/H circuit. Therefore,
most digital ground currents will enter or leave the MN376
through pin 10, and in order to keep the output clean, care
must be taken to ensure that no ground potentials can exist
between pin 10 and the other ground pins. This is why pin 10
must be tied to the analog and not the digital ground
system. For the same reason, the + 5V digital logic supply
(pin 9) should be kept as clean as possible. This supply, as
well as the ± 15V sUpplies (pins 24 and 22), is bypassed to
ground with 0.011'F ceramic capaCitors inside the MN376's
package. In critical applications, additional external 0.11'F
to 11'F tantalum bypass capaCitors may be required.
8-33
TRACK·HOLD COMMAND-A TTL logic "0" applied to pin
11 (or a logic "1" applied to pin 12) will put the MN376 into
the track (sample) mode. In this mode, the device acts as an
inverting unity gain amplifier, and its output will follow
(track) its input. A logic "1" applied to pin 11 (or a logic "0"
applied to pin 12) will put the MN376 into the hold mode, and
the output will be held constant at the level present when
the hold command was given. If pin 11 is used to control the
MN376, pin 12 must be connected to digital ground. If pin 12
is used to control the MN376, pin 11 must be tied to + SV.
Pins 11 and 12 each present 1 TTL load to the digital drive
circuit.
CAPACITIVE AND RESISTIVE LOADING- To avoid possible
oscillations, current limiting, and performance variations
over temperature, the MN376's output loading has certain
restrictions. The maximum capacitive load to avoid oscilla·
tion is typically 2S0pF. Recommended resistive loading is
5000 (minimum), although values as low as 2Soo may be
used'. Acquisition and track-to-hold settling times are relatively unaffected by resistive loads down to soon and
capacitive loads up to SOpF. Higher capacitances will affect
both acquisition and settling time.
I
1.0
0.9 _Gain
0.8
1"00..
90'
.......
'"
;;; 0.7
In most applications using the MN376 in front of a
successive approximation AID converter, the MN376's T/H
command pin can be driven directly (or inverted if
necessary) from the converter's status output. The status
output changes state when the converter receives a convert
command, and this change can drive the T/H from the track
to the hold mode. The change in state of the AID's status
output at the end of the conversion can put the T/H back
into the track mode. The diagram below illustrates an
MN376 mated with an ADC8S-type AID in this manner. Since
the ADC8S's MSB output is not set to its final value until one
clock period (approximately 1S0nsec for the fastest devices
in this family) after a conversion begins, the MN376's trackto-hold transient will be completely settled, and no extra
timing precautions are necessary.
11
~ 0.6
.~ 0.5
"
successive approximation AID's internal DIA converter
changes its output current just prior to the determination of
each output bit, the TlH will be required to sink or source
large high frequency current transients and recover within
one clock period. In the hold mode, the MN376's output impedance is typically 0.10. Its output typically recovers (to
± 0.01 %) from a 2mA step in less than 100nsec. The second
consideration involves the T/H's track-to-hold transient settling time. If the same timing pulse that puts the T/H into the
hold mode intitiates the AID conversion, the transient settling time has to be short enough to ensure that the AID has
a stable accurate input when it makes the final decision on
whether its MSB output should be a "1" or "0". This decision normally takes place one clock period after a conversion has begun.
I
0.4
0.3
./
0.2 _Phase
i"""
0.1
0.Q1
I
V
0.03
0.1
0.3
1.0
3.0
45'
+15V -15V+5V
+15V -15V +5V
O'
12
10
Frequency (MHz)
25
Track Mode Gain Amplitude and Phase Response
21
14
+5V
Start 0 - - - - - - - - - - - - - '
Convert
See the MNS24S 12-bit AID data sheet for information on how to use
MN376 to configure a 1MHz, 12-bit sampling AID with a 500kHz input bandwidth. See the MN5249 data sheet to configure a 2MHz
sampling AID with a 1MHz input bandwidth.
[1:1J
_
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
8-34
MSB
LSB
20
USING THE MN376 WITH AID CONVERTERS-There are
two important considerations when using T/H's to drive
successive approximation AID's. The first is a dual reo
quirement-the T/H's output stage should exhibit a very low
impedance compared to the AID's input impedance (usually
1 to 10kO) at frequencies up to five times the AID's clock
frequency, and the T/H should be able to recover from current transients in a time interval smaller than the AID's clock
period. These requirements are based on the fact that as a
I
I
I
ADC84f85f87
MN5240
MN379
UJJ
_
FLASH-CONVERTER
COMPATIBLE
T/H AMPLIFIER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Designed to Directly
Drive Flash Converters
• 2psec Maximum Aperture Jitter
• Capacitive loads to 500pF
• 30nsec Max Acquisition Time
(1V Step to ±O.1%)
• 15nsec Max Settling Time
• ±300Vl,..sec Min Slew Rate
• 100MHz Bandwidth
• TTL or ECl Compatible
• 24-Pin DIP
• Full Mil Operation
-55°C to +125°C
• Mll-H-38534 Screening
Optional. Mil-STD 1772
Qualified Facility
An additional problem associated with higher-resolution flash
converters is the high capacitive input impedance that often
characterizes these d$wices. MN379 is designed to be unconditionally stable with capacitive loads up to 500pF, and its ability to
supply instantaneous output currents up to ± 100mA makes its
acquisition, settling and bandwidth characteristics relatively
unaffected by load.
MN379 has an inpuUoutput voltage range of ±2.5V. Its compensated open-loop design architecture gives it a minimum gain
of +0.92 and a pedestal guaranteed not to exceed ± 20mV. The
outstanding 2psec aperture jitter is achieved using a high-speed
diode-bridge switching scheme. The track-hold digital input controlling the bridge can be referenced to an external voltage for
CMOS or ECl compatibility. An internal reference is supplied for
TIL compatibility.
24 PIN DIP
~N
MN379 is an extremely high-speed track-hold (T/H) amplifier
designed to overcome the bandwidth and loading pr9blems
associated with many 6-9 bit, high-throughput, flash.type A/D
converters. The relatively high aperture uncertainty Gitter) of
many higher-resolution flash converters results in correspondingly large accuracy and linearity errors when digitizing highslew-rate (wide-bandwidth) signals. The result is a reduction in
effective-bit resolution. MN379 overcomes this problem with its
outstanding 2psec maximum aperture jitter. In such aperturereducing applications, MN379 can result in a 10 times improvement in the ability to digitize rapidly slewing signals while its
25MHz throughput causes no reduction in overall sampling rate.
1
\
\
MN379 is packaged in a standard, 24-pin ceramic dual-in-line.
Power supply requirements are ± 15V and maximum power consumption is 2 Watts. Standard product is fully specified for O°C
to +70°C (case) operation and for military/aerospace
applications, is available fully screened to Mll-H-38534
(MN379H/B CH).
~O.12(}(3.05)
0.170(4.32)
\.- 0 600(15.24)--1
Dimensions in Inches
(millimeters)
[1JJ
_
January 1992
Copyright c 1992
Micro Networks
MICRO NETWORKS
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
8·35
MN379 FLASH-CONVERTER COMPATIBLE T/H AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
- 55·C to + 125·C (case)
Operating Temperature Range
Specified Temperature Range:
MN379
MN379H, MN379H/B (Note 1)
Storage Temperature Range
+ 15V Supply( + Vcc, Pin 23)
- 15V Supply (- Vcc, Pin 12)
Analog Input Voltage (Pin 5)
Digital Input Voltage
(Pins 2 or 3 to ground)
Differential Digital
Input Voltage (Pin 2 to Pin 3)
Output Current (Note 2)
PART NUMBER
MN379H/B CH
Standard part is specified for O°C tO~700C
.
operation.
Add "H" for specified -55°C to +125°C
operation.
.
Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for 100%
screening according to MIL·H-38534.-------.....I
O·C to + 70·C (casel
- 55·C to + 125·C (case)
-65·Cto +150·C
- 0.5 to + 18 Volts
+ 0.5 to - 18 Volts
±5 Volts
± 15 Volts
±5 Volts
±35mA
SPECIFICATIONS (TA= + 25°C, Supply Voltages ±15V, ZLoad = 5000
II
15pF unless otherwise indicated)
ANALOG INPUT/OUTPUT
MIN.
Input/Output Voltage Range
±2.5
Input Impedance
TYP.
II
kO
5
10
Maximum Capacitive Load
II
pF
rnA
±25
Output Impedance
UNITS
Volts
10
Output Current (Note 2)
MAX.
0
pF
500
DIGITAL INPUTS (Note 3)
Digital Input Threshold (Pin 2 to Pin 3)
-100
+ 100
mV
Digital Input Operating Range (Pins 2 and 3 to Ground)
-5.5
+5.5
Volts
+2
+ 5.5
+0.8
Volts
Volts
+10
-0.25
rnA
+ 1.4
Volts
Logic Levels (Pin 2 or 3 tied to Pin 4): Logic "1"
Logic "0"
Logic Currents: Logic "1"
Logic "0"
TTL Reference (Pin 4) Output Voltage
+1.1
TTL Reference (Pin 4) Output Impedance
+ 1.25
~A
0
560
TRANSFER CHARACTERISTICS
Gain Error: Initial (+ 25·q
Drift (Note 4)
+0.92
+0.96
±20
±50
VIV
ppm/·C
Linearity Error (Full Temperature Range) (Notes 4, 5)
±0.05
±0.1
%FSR
Offset Voltage (Track Mode): Initial (+ 25·q
Drift (Note 4)
±5
± 100
±10
±200
mV
p.V/·C
Pedestal (Note 6): Initial (+ 25·C, Vin = OV)
Drift (Note 4)
Variation with Vin
±10
± 100
-8
±20
±200
mV
p.V/·C
mVIV
25
35
15
25
30
40
20
30
nsec
nsec
nsec
nsec
Track·to·Hold Transient: Height (Peak-to- Peak)
Settling Time (to ± 5mV)
60
10
15
mV
nsec
Aperture Delay Time
5
8
nsec
Aperture Jitter
1
2
psec (rms)
DYNAMIC CHARACTERISTICS
Acquisition Time: 5V
5V
1V
1V
Step
Step
Step
Step
to
to
to
to
± 1 % (± 50mV)
± 0.1 % (± 5mV)
± 1 % (± 10mV)
± 0.1 % (± 1mV)
Slew Rate
±400
V/p.sec
Small Signal Bandwidth (1Vp-p)
100
MHz
Large Signal Bandwidth (5Vp-p)
25
MHz
Feedthrough Attenuation (@10MHz)
±300
dB
60
Droop Rate: + 25·C
Over Temperature (Note 4)
±0.5
Doubles Every 10·C
±5
mV/pSec
POWER SUPPLIES REQUIREMENTS
Power Supply Range
8-36
± 15
± 15.75
Volts
Power Supply Rejection
±12
±25
p.VIV
Current Drain: + 15V Supply
-15V Supply
+55
-50
+ 70
-65
rnA
rnA
Power Consumption
1575
2025
mW
± 14.25
SPECIFICATION NOTES:
1. The MN379 has an approximate 50 0
ambient air temperature.
e rise of case temperature over stili,
2. Under normal operating conditions, continuous output current should not
exceed ± 35mA. The MN379 can withstand a continuous short to ground
for approximately 10 seconds. Shorts to either supply will result in
destruction.
3. The MN379's Hold and HOld inputs are essentially the direct inputs of a
comparator, and the Dlgilallnput Threshold Voltage Is effectively the com·
parator offset. Tying either Pin 2 or Pin 3 to Pin 4 (TTL Reference) will make
the other pin TTL compatible. For Pin 2: "0" = Track, "I" = Hold. For Pin 3:
"1" = Track, "O"=Hold. Tying either Pin 2 or Pin 3 to other reference
voltages can make the MN379 compatible with any logic family.
Q"e to + 70 e (case) temperature
range for the MN379 and over the - 55·C to + 125·C (case) temperature
range for the MN379H and MN379H/B.
5. Linearity Error is expressed as a percentage of the Full Scale Range (peak·
to-peak) of the input/output signal. In an 8-bit system, V. LSB is equivalent
to 0.19% FSR. In a 9-bit system, V. LSB is equivalent to ± 0.1 % FSR.
4. Listed specifications apply over the
G
6. Pedestal refers to the unwanted step in output voltage that occurs as a
T/H is switched from the track to the hold mode. For the MN379, pedestal
amplitude varies linearly with input signal amplitude. The pedestal
becomes more negative as the input signal becomes more positive.
BLOCK DIAGRAM
(13) Analog
Output
Analog (5)
Input
~(4)TTL
HOld(2)~
Comp
Hciid (3)
+ 15V Supply (23)
~
-15V Supply (12)
~
PIN DESIGNATIONS
•
24
PIN 1
12
~
-
--.0
1
2
3
4
5
6
7
8
9
10
11
12
13
Ground
Hold Command (Note)
l10Ta Command (Note)
TTL Reference
Analog Input
Ground
Ground
Ground
Ground
Ground
Ground
-15V Supply (- Vcc)
Note: Pin 2: "0"
=
24
23
22
21
20
19
18
17
16
15
14
13
Reference
(1,6·11,14·18,20·22)
Ground
Ground
+ 15V Supply (+ Vcd
Ground
Ground
Ground
NIC
Ground
Ground
Ground
Ground
Ground
Analog Output
=
Track, "I" Hold
Pin 3: "I" = Track, "0" = Hold
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS-The large switching currents
produced by MN379's diode·bridge switching circuitry make
it mandatory to provide a good ground and clean supplies to
the device in order to achieve specified speed and accuracy
performance. The unit has 16 ground pins (pins 1,6-11, 14-18,
20-22 and 24). They should all be tied together as close to
the unit as possible and all connected. to system analog
ground, preferably through a large low·impedance, analog
ground plane beneath the package.
If p.c. card ground liries must be run separately, wide con·
ductor runs should be used with O.Q1I'F ceramic capacitors
interconnecting them as close to the package as possible.
Power supply connections should be short and direct, and
all power supplies should be decoupled with high·frequency
bypass capaCitors to ground. 11'F tantalum capacitors in
parallel with 0.011'F ceramic capaCitors are the most effec·
tive combination.
Coupling between analog inputs and digital control signals
should be minimized to avoid noise pickup. Care should be
taken to avoid long analog runs or analog runs in parallel
with digital lines.
8-37
TRACK·HOLD COMMAND-A logic "0" applied to pin 2 (or a
logiC "1" applied to pin 3) drives MN379 into the track
(sample) mode. In this mode, the device performs as a unity·
gain amplifier (follower), and its output follows (tracks) its
input. A logic "1" applied to pin 2 (or a logic "0" applied to
pin 3) drives MN379 into the hold mode, holding the output
constant at the level present when the hold command was
given.
MN379's Hold !lnd Hofcl inputs are essentially the direct
inputs of a comparator, and the specification for Digital
Input Threshold Voltage is effectively the comparator offset.
Tying either pin 2 or pin 3 to pin 4 (TTL Reference) will make
the other pin TTL compatible. If, for example, pin 3 (Hold) is
tied to pin 4 (TTL Reference), a TTL logic "1" (+ 2.0V mini·
mum) applied to pin 2 will drive MN379 into the hold mode.
Tying either pin 2 or pin 3 to other reference voltages
can make MN379 compatible with any logic family. Tying
either to -1.3 volts, for example, will make the other ECL
compatible.
MN379 ACQUISITION TIME-MN379 acquisition time for
any step size settling to ± 1 % FSR (± 50mV) or ± 0.1 %FSR
(± 5mV) can be read from the plot below or calculated using
the following guidelines. Acquisition time basically consists
of the following 4 components:
1)
2)
3)
4)
5nsec gate delay
3nsec output amplifier delay
2.5nsec/volt slew rate
4nsec for settling to ± 1 % FSR or
14nsec for settling to ±0.1%FSR
The 8nsec total delay for the gate and output amplifier
circuits is constant. The total time required for slewing
obviously varies as a function of step size, and the settling
times are constant independent of step size. Therefore, as
demonstrated below, the acquisition time is easily calcu·
lated for any step size.
Typ
5V
5V
1V
1V
step
step
step
step
to
to
to
to
(8 + 12.5 + 4)nsec = 25nsec
(8 + 12.5 + 14)nsec = 35nsec
(8 + 2.5 + 4)nsec = 15nsec
(8 + 2.5 + 14)nsec = 25nsec
1%
0.1%
1%
0.1%
±l%IFSR/
/
Step 3
Size
(Votts)
/
o
o
/
/
/
15
20
'/
tA
-
Scale: Vertical 20mV/div
Horizontal 10nsecfdiv
Glitch Amplitude: 40mV
Glitch Area: 240mV·nsec
MN379 Typical Track·to·Hold Transient
DRIVING CAPACITIVE LOADS-As stated earlier, MN379 is
designed to directly drive most 6·9 bit flash converters. Such
converters often have highly capacitive input impedances,
and certain precautions must be taken to optimize MN379
performance with capacitive loads at the megahertz fre·
quencies the device is designed to handle. In particular, the
series inductance of the wire or pc card run connecting the
output of MN379 to its capacitive load is no longer insignificant. In order to obtain the quickest settling at the load in
response to a driving function at the T/H output, it will be
necessary to add a series resistor such that the resulting
RLC circuit is critically damped. Actually, a slightly underdamped response will settle somewhat faster, but the
improvement is not significant. The value of the damping
resistor will depend upon the length of wire and the load
capacitance.
Critical damping occurs in a series RLC circuit when the
resonant radian frequency (wo) equals the exponential damping coefficient (,,):
Since
Wo = 1/.j[C
and
" = R/2L
it follows that R = 2.jUC
where R is the required value of series resistance, L is the
wire inductance and C is the load capacitance. The 10n out·
put resistance of the T/H should be subtracted from the
calculated value of R since it is effectively in series with the
load. In making calculations, an inductance of 23nHylin. can
be assumed for straight, solid wire of AWG 20 to 28, or P.C.
runs of 100 to 600 mil' cross·sectional area. This value
should also serve as a good starting pOint for experimentation if other shapes or wire sizes are used. Bear in mind
that critical damping only guarantees best settling for a
given combination of Land C. There will still be practical
limits on the values these can assume if settling is to be
accomplished in a reasonable time.
±Oto FSR
/
/
10
30nsec
40nsec
20nsec
30nsec
/
V
The voltage at the load capacitor will be of the form
25
30
Acquisition Time (nsec)
MN379 Acquisition Time vs. Step Size
8-38
Max
!N
35
40
v(t) = A{ 1 - ("t + 1)e'''' I
in response to a step of amplitude A at the T/H output. For
settling to ±0.1%, v(t) = 0.999A and, from the equation
above, "t = 9.23. Since 0' = Wo = 1/.j[C, it follows that settling
to ± 0.1 % of the step size occurs at t = 9.23.j[C.
=
As an example, assume C LOAD 200pF and that it is 2,2
Inches from the T/H outpuL This corresponds to a wire
inductance of L = 23nHy/in. x 2.2in. = 51nHy. For critical
damping, R =2J[JC = 32!l. Subtracting 101) for the T/H output yields a final value of 22!l. This resistor should be a carbon or other non-inductive type, and its length will count as
part of the inductance to be damped. With C and L as above,
the settling time to ± 0.1 % will be t = 9.23J[C = 30nsec.
The actual settling t;me in any given situation will be
somewhat longer than predicted above due to the effects of
the settling time of the T/H itself. A very good approximation
of the overall settling time can be obtained by assuming the
two components add as the square root of the sum of their
squares. In the above example, assuming 30nsec settling
time for the T/H to ±0.1%, this would mean J30' + 30', or
about 42nsec total settling from the time a step is applied to
the input of the T/H to the time the voltage seen by the AID
settles to ± 0.1 % of its final value.
HEAT SINKING _. "H" versions of MN379 are fully
specified for - 55"C to + 125"C (case temperature) operation. Because of the device's high internal power dissipation, heatsinking precautions may be necessary to maintain junction temperatures below + 150"C.
MN379 typically dissipates 1575mW (2025mW maximum).
The device has a junction-to-ambient thermal resistance
(IIJA) of 34 "C/watt. Therefore, with no heatsinking, MN379's
junction-to-ambient temperature differential is typically
53.5"C. Following the + 150"C maximum junctiontemperature restriction, the calculated temperature differential dictates that one not operate MN379 in still, ambient air above + 96.5 "C. Note, however, that the unit has a
relatively low 7.5"C/watl junction-to-case thermal
resistance (/lJd that makes the device relatively easy to
heatsink.
TESTING APERTURE JITIER- The following method is
designed to measure the aperture jitter of the MN379 but,
with appropriate modification of the D.U.T. socket pinout,
may be used to measure any high-speed track-hold
amplifier.
Please refer to the diagram labeled 'Aperture Jitter Test Setup' for the following procedure. A pulse generator capable
of generating pulses with rising and falling edges with
slopes on the order of 1 Volt/ns is needed as is a sampling
scope and FET probe_ The pulse train is used initially to
drive the Hold or Hold input of the MN379 (depending upon
whether rising edge or falling edge jitter is to be measured).
Since the control inputs to the MN379 are fully differential,
the unused input is simply connected to ground for a reference and a symmetrical-around-ground input signal is used.
The indicated signal levels were chosen so as not to overload the FET probe when used in the X1 mode. Probe noise
is too high to get meaningful readings ifaX10 attenuator is
used. The drive signal is sent to both the sampling scope, to
set levels and for triggering, and to a "calibrated delay line".
The delay line compensates for aperture delay time and consists of a length of coax selected so that the aperture time
(switch opening) of the track and hold occurs at the fastest
rising (zero crossing) point of the input waveform. Use of
this form of delay ensures no added jitter. The length of the
delay line may vary from a few inches to several feel,
Once the delay line has been adjusted properly (this may be
confirmed by noting that the "held' voltage is near zero
volts), the FET probe is used to measure the input-signal
slew rate directly at the D.U.T. input pin (pin 5). This slew
rate will most likely be different for the riSing vs falling edge
so both should be measured. The FET probe is then returned
to the Analog Output (pin 13), and the sampling scope is set
to view a portion of the held waveform well past the track-tohold settling transienL A tangential noise measurement is
made by observing the width of the noise band on the scope
(mVp-p). This reading is then divided by six to get the approximate rms value of the noise. This number, when divided
by the slope of the input signal, will give the aperture jitter.
If the units used are mV and volts/ns the calculated jitter
will be in picoseconds (rms). A slightly more accurate
measurement may be obtained by subtracting the contribution of system noise to overall outj:'ut noise. ThiS may be
measured by observing the output on the oscilloscope while
the D.U.T. is in the track mode.
8-39
Chl
+15V
r
6.8~F
(13)
(24)
D.U.T.
MN379
I
100nsee
6.81~F
I
-15V
+O.5V~
Slope
~
W/nsee
-O.5V
Calibrated Delay Line
Aperture Jitter Test Setup
~
8-40
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
"'"
0
MN2020
DIGITALLY CONTROLLED
PROGRAMMABLE-GAIN
AMPLIFIER
l11J MICRD NETWDRKS
_
DESCRIPTION
FEATURES
MN2020 is a precision hybrid amplifier whose gain can be set to
anyone of 8 levels (1 to 128) with the application of a single 3-bit
digital word (TTL logic levels) to its gain control inputs. This
programmable-gain amplifier may be operated under direct
computer or microprocessor control to provide fully automated,
gain-range data acquisition.
• Programmable Gain
1 to 128 in 8 Steps
• Gain Selected with
a 3-Bit TTL Word
• Excellent Gain Accuracy:
±O.002% @ G=1
±O.1% @ G=128
• Low Offset Voltage
Drift ±5p.V/"C
• High Input Impedance
1000MO
• Small 18-Pin DIP
• Full Mil Operation
-55"C to +125"C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
The use of internal, laser-trimmed thin-film resistors result in
excellent gain accuracy, linearity and drift characteristics. In
addition, MN2020 has 100kHz of full power bandwidth and 5MHz
of small signal bandwidth resulting in a rapid settling time of
5p.sec for a 20 volt step (@G=1).
The MN2020 Programmable-Gain Amplifier is packaged in a
hermetically sealed, 18-pin dual-in-line package. The standard
device is fully specified for either O°C to +70°C or -55°C to
+ 125°C ("H" model) operation. For military/aerospace or harshenvironment commerciallindustrial applications, MN2020H/B CH is
fully screened to MIL-H-38534 in Micro Networks MIL-STD-1772
qualified facility.
18 PIN DIP
PI"'D~
n
1_ ~-'---~911
rO.520(13.21)
0.009(0.23)
0.012(0.30)
f"I':~
0,015 (0.381
--.I}--
0.075 (1.911
'I
1.027(26.09)
~ulI
MN2020 is an excellent choice for requirements where stable
accurate gains are necessary. Typical applications include
microprocessor-based data acquisition systems that have to
handle a wide dynamic range of analog inputs. MN2020 may be
combined with Micro Networks MN7130 Multiplexed Track-Hold
Amplifier and MN574A Microprocessor Interfaced AID Converter
to create a 16-channel, 12-bit, microprocessor-interfaced data
acquisition system capable of accepting analog inputs from
±7BmV to ± 1CN full scale (19-bit dynamic range). Additional
applications can be found in autoranging analog-to-digital conversion systems requiring wide dynamic ranges and in systems
that autorange under program control.
0.020 (0.51)
0.120(3.05)
~11Q(4.32)
0.200£5,081
0.230(5.84)
T
~
0.300 (7.62)
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
April 1992
Copyright 1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
8-41
MN2020 DIGITALLY CONTROLLED PROGRAMMABLE-GAIN AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Specified Temperature
Storage Temperature
+15V Supply (Pin 16)
-15V Supply (Pin 6)
+5V Supply (Pin 5)
Analog Input (Pin 10)
Digital Inputs (Pins 2-4)
===JJ
ORDERING INFORMATION
-5S0C to +12SoC
O°C to +70°C
-5SoC to +12SoC ("H" Model)
-6SoC to +IS0°C
-O.S to +18 Volts
+O.S to -18 Volts
-O.S to +18 Volts
±IS Volts
o to +Logic Supply (Note 1)
PART NUMBER
MN2020/H/B CH
Standard part is specified for
DoC to +70°C operation.
Add "H" for specified -55°C to +125°C
operation.-------Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for 100%
screening according to MIL-H-38534.---------.I
SPECIFICATIONS (TA=+2SoC, Supply Voltages ±1SV, unless otherwise speclfled)_
GAIN
MIN.
Fixed Gain Settings
TYP.
UNITS
1,2,4,8,16,32,64,128
Gain Nonlinearity (Note 2): G=1
G = 128
±0.OO2
±0.04
±O.OOS
±O.08
% FSR (Note 3)
%FSR
Gain Accuracy (Note 4) G = 1: +2SoC
O'C to HO'C
-S5' C to +125° C
±O.OO2
±0.OO3
±O'004
±O.OOS
±0.008
±0.01
%
%
%
±0.1
±0.1
±0.2
±O.2
±0.2
±0.4
%
%
%
G = 128: +25°C
O°C to +70°C
-SsoC to +12SoC
INPUT CHARACTERISTICS
Input Impedance
Input Voltage Range (@G=11
Offset Voltage IRlIllNotes 5 and 61
Initial 25°C
Drift vs. Temperature -S5' C to +12S' C
Input Bias Current: +2S'C
O'C to HO'C
-SS'C to +125'C ("H" Model)
Voltage Noise (RTI)
G=128 (0.1 to 10 Hz)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
GAIN SWITCHING
Gain Control LogiC Inputs
Logical 1
Logical 0
Loading
Gaif] Switching Time (Note 8)
POWER SUPPLY REQUIREMENTS (Vour=OI
Power Supply Range
Current Drain (Analog Supply)
Pow~r
Note
Note
Note
Note
Note
Consumption
1000
±12
MO
V
100
5
± 20
± 3
±IS0
p.V
p.V/oC
pA
nA
nA
±200
± 10
±500
p.Vp-p
5
±10
±12
5
DYNAMIC CHARACTERISTICS
Small Signal 8andwidth
G=1
G=128
Full Power Bandwidth (@G-l)
Slew Rate
Output Settling Time to ±0.1% 20V Step (Note 71
G=1
G=128
V
mA
5
MHz
40
KHz
KHz
100
12
5
65
V/p.Sec
75
+4.0
+0.8
1
0.6
±15
±9.2
275
1: Dlgllal mputs should not exceed logiC supply level. LogiC supply (pin 5) must be at least +5V to maintain logic levels
2: See dehnilion of gam nonlinearity on Page 3
J: FSA Full Scale Range If output sWing ~ :!:12V, FSA ~ 24V
4; Me'asured between endpOints of Input (output) range in order to negate the effects of the offset volt~ge.
$: 11T! Referred to Input
Nole 6· txlernally adjustable 10 zero
Note 7: For each gain value, the magnitude of the mput step was chosen to make the output step 20V.
Note 8: Between any Iwo gain values
8-42
MAX.
±18
±18
540
p.Sec
p.Sec
V
V
p.A
p.Sec
V
mA
mW
BLOCK DIAGRAM
PINNING
GAIN
CODE
AD AI
A2
(2)
(4)
(3)
1
2
3
4
5
6
7
8
9
(TOP)
18
17
16
15
14
13
12
11
10
ANALOG
OUTPUT
ANALOG
INPUT
(10)0---4
>---....,ji----o(7)
--<>(16) + 15V
-O(6)-15V
-o(12-15)A. GND.
OFFSET
ADJUSTMENT
•
+
+15V
- 0 ( 5 ) +15V
- 0 (1) D. GND.
1.
2.
3.
4.
5.
6.
7.
8.
9.
DIGITAL GND.
AD
A,
A2
+15 VOLTS (DIGITAL)
-15 VOLTS
ANALOG OUTPUT
OFFSET ADJ.
OFFSET ADJ.
10.
11.
12.
13.
14.
15.
16.
17.
18.
ANALOG INPUT
NO CONNECTION
ANALOG GND.
ANALOG GND.
ANALOG GND.
ANALOG GND.
+15 VOLTS (ANALOG)
NO CONNECTION
NO CONNECTION
PROGRAMMABLE GAIN AMPLIFIER
SPECIFICATION DEFINITIONS
GAIN-The ratio of the amplitude of output signal voltage
to the amplitude of input signal voltage.
GAIN ACCURACY-Either the percentage that actual
gain differs from ideal gain (%) or the amount that the
output, at a certain gain and input level, differs from the
ideal value (volts, % FSR).
GAIN NONLINEARITY-Maximum deviation of the inputoutput voltage transfer function from the ideal, expressed
as a percentage of the full output voltage range (FSR).
GAIN SWITCHING TIME-The time necessary for the
amplifier gain to settle to within 0.1% of its new value
following the appearance of a new digital code at its gain
coding terminals.
INITIAL OFFSET VOLTAGE (Referred to Input)-The
collection of internal voltage offsets summed and treated
as a single offset voltage source appearing in series with
the input. This offset, multiplied by the programmed gain,
will appear at the amplifier output, even when the input
signal is zero. This offset voltage can normally be zeroed
out with an external trim pot.
INITIAL OFFSET VOLTAGE (RTI) DRIFT vs TEMPERATURE-Drift in initial offset voltage resulting from temperature variations. Usually expressed as vrc or ppm
of FSR JOC.
INPUT BIAS CURRENT-The current drawn into (or out
of) the input terminals of the amplifier when the amplifier
is turned on and the input signal is zero (input grounded).
INPUT IMPEDANCE-Total impedance seen looking into
the amplifier input terminal (with the load connected)
with respect to analog ground.
LOADING-The apparent load that the digital gain coding
inputs of the amplifier present to their driving circuits.
Usually expressed as standard logic loads (e.g. 3 TTL
Loads) or in terms of the current sourced or sank when
the input is a logic "0" or "1".
OUTPUT DRIVE CURRENT-Current that the amplifier
will source or sink to the load while remaining within
specification.
OUTPUT VOLTAGE SWING-Maximum allowable output
excursion for faithful reproduction of the input signal.
This is limited to several volts less than the associated
power supply voltage range.
SETTLING TIME-The interval from the application of
either an input step at a fixed gain or a new gain code at a
fixed input level to the output's settling within a specified
error band (usually 0.1%) of its final value.
SMALL SIGNAL BANDWIDTH-Frequency at which the
amplifiers gain drops 3 dB from its D.C. value.
SLEW RATE-Maximum rate of change (V/Sec) in the
output in response to a step change at the input or a gain
change.
VOLTAGE NOISE (RTI) - Sum of the internal noise
sources treated as a single source appearing in series
with the input signal. The noise, multipled by the programmed gain, will appear at the amplifier output. Voltage
noise is dependent upon bandwidth and may be reduced
by using the minimum bandwidth necessary for a given
application.
8-43
TYPICAL CHARACTERISTICS
(TA=25°C, Supplies ±15V)
GAIN CODES AND SETTLING TIMES
GAIN ACCURACIES
GAIN
ACCURACY(%)
25°C
DIGITAL CODE OUTPUT SETTUNG TIME"
(±O.1 % 20V Step)
A2 A, Ao
GAIN
1
2
4
8
16
0
0
0
0
1
0
0
1
1
0
0
1
32
64
128
1
1
1
0
1
1
1
0
1
2.5
3
4
6
8
0
1
0
17
33
65
O°CI070°C
-55°C 10 +125°C
TYPICAL
MAX.
TYPICAL
MAX.
TYPICAL
MAX.
I'Sec
I'Sec
I'Sec
I'Sec
I'Sec
1
2
0.002
0.005
0.005
0.015
0.003
0.005
0.008
0.020
0.004
0.008
0.010
0.020
4
8
16
0.005
0.010
0.020
0.015
0.020
0.030
0.005
0.015
0.020
0.020
0.040
0.040
0.015
0.020
0.025
0.040
0.080
0.080
I'Sec
I'Sec
I'Sec
32
64
128
0.020
0.040
0.100
0.040
0.100
0.200
0.020
0.040
0.100
0.040
0.100
0.200
0.040
0.100
0.200
0.100
0.300
0.400
• For each gain value the magnitude of the input step was chosen to
make the output step 20V.
GAIN ACCURACY VS.
GAIN (TYPICAL, TA=O°C 10
70°C)
SMALL SIGNAL BANDWIDTH
VS. GAIN (TYPICAL, TA=25°C)
iX
GAIN NONLINEARITY VS.
GAIN (TYPICAL, TA=25°C)
til
5,000
.. 2,500
LI.
~
~ 1,250
J:
b
iQ
625
312
a:
Ul
'"1"'-
Z
:i
156
78
39
1
!. 0.07
_0.14
4
IL
~ 0.06
0.12
a:cC 0.05
;'0.10
o
l'\,
~ 0.08
::l
~ 0.06
"-["-
8
16
GAIN
32
/
<
Z 0.04
:c
Cl 0.02
"
64 128
2
4
-
/
V
16
32
/
Z
00.03
Z
Z 0.02
/
./
;(
" 0.01
0.005
~
8
w
~ 0.04
64 128
1--"1"'"
2
GAIN
4
8 16
GAIN
32
64 128
APPLICATIONS INFORMATION:
OFFSET ADJUSTMENT:
The MN2020 meets all specifications without adjustment. However, the
initial offset voltage may be adjusted to zero with the addition of a trimpot
between pins 8 and 9 as shown in the block diagram. A 20K, 10 turn,
<100 ppm/DC TC trimpot should be used to minimize drift with temperature.
LAYOUT CONSIDERATIONS:
Proper attention to layout and decoupling is necessary to obtain specified
accuracies. Analog and digital grounds are not connected internally. The
four (4) analog commons (pins 12-15) and the digital common (pin 1)
should be tied together as close to the package as possible. preferably
to a large ground plane underneath the package. If these commons must
be run separately. wide conductor runs should be used.
Power supplies should be decoupled with tantalum or electrolytic capacitors located close to the device package. For optimum results. l!J.F capacitors paralleled by 0.01 !J.F ceramic capacitors should be connected as
shown in the adjacent diagram.
8-44
Pins 5, 16 0
Pins 12-150
,
1 "F
Pin 60
1
"] I
1
l
0.01
10.01
0
+'5V
"F
oANAlOG
GND.
"F
0-lSV
INTERFACING THE MN2020 TO POPULAR MICROPROCESSORS
The MN2020 can be easily interfaced to microprocessors
for fully automated data acquisition or other applications
where it is desirable to change gain under program control.
Memory mapped I/O is recommended to take advantage
of the powerful memory reference instructions available
in most microprocessor instruction sets. Detailed information is provided below for the 6800 Series and 8080
Series processors. Interfacing to other processors would
be similar.
INTERFACING TO 6800 SERIES MICROPROCESSORS
Wiring and Timing Diagrams for interfacing the MN2020
with the 6800 family of microprocessors are shown in
Figure 1. In this example, the MN2020's gain control inputs are addressed and written to as a memory location
with the gain code in the three lowest order bits (Do, 01,02)
of the accumulator. The address bus connections shown
(A14, A13, and AO) correspond to memory address 6001
hexadecimal. Redundant addressing of the MN2020 would
occur at any address containing the bit combination A14,
A13, AO. The MN2020 may only be written to; attempts to
read the memory address assigned to the MN2020 will
result in indeterminate (floating CMOS inputs) data.
The connections to the VMA, ~2 clock and R/Vii lines are
used to insure correct timing and to prevent spurious data
that may be present on the address bus during non-memory
transfer operations from addressing the MN2020. When
connected as shown, the MN2020 will be reset to a gain of 1
by a reset pulse from the hardware reset control line of the
6800 System.
TIMING DIAGRAM
CIRCUIT DIAGRAM
CLOCK ¢2
DATA
BUS
le.2 OUTPUT
L------_"""~DA~TA~VA~L~'D~>--
I
1 - - - - - - ,' - _ _ _-oJ
t
~
DATA STROBED
INTO MN2020
DATA NOT VALID
INTERFACING TO 8080 SERIES MICROPROCESSORS
Wiring and Timing Diagrams for interfacing the MN2020
with the 8080 family of microprocessors are shown in
Figure 2. In this example, an 8228 system controller is
used, and the MN2020 is treated as a standard I/O device.
The gain code is written, as an output instruction, to the
MN2020 which is located at I/O address 80 hexadecimal.
CIRCUIT DIAGRAM
When the values of A7, AO, and I/O Ware "1", "0" and "0"
respectively, the output of IC 1A will go to logic zero. When
either of the address or I/O W outputs leaves the above
state, the output of IC2 is forced to a logic one, with the
rising edge triggering the latch IC2 which strobes the gain
code information into the MN2020.
TIMING DIAGRAM
ADDRESS
'US
l
A
A, FLLU~------
SYSTEM
DATA BUS
10 ,
0
t--~.
'------
Ie lA OUTPUT
t
~
DATA STROBED
INTO THE MN2020
DATA NOT VALID
8-45
'"In
12 Bit-1S Channel Data Acquisition System
WITH 19 BITS OF DYNAMIC RANGE AND AUTORANGING CAPABILITY
l-
TT
1 24
Channel 0
'~ ~
~
~
~ 3:
-5 ~ ~
~ 9~ :;!t¥:::t
~ 10 ~'5=:: ~
11
a::
~ 12
13
~ 14
4
5
6
ANALOG
INPUTS
±78 mV Full Scale
To
!
Q.
±10V Full Scale
Channel 15
;;= 1516
cI
IC5C
23 31
21
26
32
19
20
10K
'-J
27
28
29
30
~'Jv
1O±
S
b
9
x
8001
(Read)
8000
(Read)
Bit
5
I
X
I
X
~ .. ,"
I Bit
6
Bit
7
1
I
18
0, I 0, I 0,
I I I
X
X
~
lupJ'"
MN20:0 5
Programmable
Gain Amplifier
1 12
IC6B
I
8_lt
IC6A
,-l-
13 14
15 9 13
i
I Do I
81t
3
Bit Digitized Data
4
MSB Byte
I ~~t IJUitLSB Digitized Data
8~~
~~ ~
l
gtDaro~35
<:o:n C"l 039
~ =0
0
~
'/
IC51Y1
'-J
40
33
11
LSB Byte
............
A
~
__ _
Multiplexed S/HChannel Address
I
20815
jr---o< (
//
V/'
V/
//
~
~
~
o /
v~
IC5B
V ~/
V>/
V~/
V 55,~
2
X f f i X Converter
2
Bit
37
l - f----.
IC4
7
Starts AID
"'" MSB Bit
oN~.g ~
!~
'15V 15V·15V
,
8003
(Write)
0.01
"F
25
MEMORY MAP
I 0, I 0'1
;:
C :; Q"
22
6800 CPU
34p
36
7
(Write)
l>
18
22
19 23 32
16
12M
-15V
10
8000
21
L
17
"2~,,"'
I D.
3M
24
+15V
8 Programmable
Gams
(1 2 4 8
Hex.
I 0,
Address
Tf~
.;.15V
7
5
2
4
----i-~9~
10
0
12
7
'" 5
~
IC3
IC4
IC5
IC6
Q12
74LSOO
74LS02
74LS04
74LS20
~
~
D3...-::
D2~
D:::::
DO/
~
~
~
~
~
V/
\
\~
~
[\1\
~~\
:IJ
=<1
...
<
;::
l>
'"
~I
()
r
0
()
"
~
~
~
1\ \ \
I
I'
MN2200
I
L' I
_
HIGH-PERFORMANCE
INSTRUMENTATION AMPLIFIER
MICRO NETWORKS
DESCRIPTION
FEATURES
• Internal Gain Setting
Resistors for G=1, 10, 100, 1000
• Excellent Gain Accuracy:
±0.1% G=100 +25°C
±0.16% G=100 +85°C
±0.3% G=100 +125°C
• Low Offset Voltage
Drift ±0.6/LVIOC @ G=100
• Small 18-Pin DIP
• Full Mil Operation
-55°C to +125°C
MN2200 is a high-performance hybrid instrumentation amplifier
in a small, 18-pin, ceramic dual-in-line package. Internal, lasertrimmed, thin-film resistors provide user-selectable gains of 1,
10, 100 and 1000. The internal gain setting resistors provide
much better accuracy over temperature than conventional
designs requiring an external gain setting resistor. A single
external resistor may also be used for gain adjustment in
applications calling for gains between the fixed ranges.
An additional unique feature of MN2200 is its user-optional, twopole Butterworth filter. Two external capacitors can be used to
set the breakpoint of this lowpass filter from full bandwidth to
well below 1Hz.
MN2200 has a typical input offset voltage of ± 100/tV at +25°C,
and this can be adjusted to zero with an external trimpot. Input
offset voltage drift with temperature is an extremely low
±1.5/tV/oC at G=10 and drops to ±0.5/tV/oC at G=1000. In
addition, MN2200 offers 7kHz of full power bandwidth, 1000MO
input impedance, and has only ±5nA of input bias current.
The standard device is fully specified for either -25°C to +85°C
or -55°C to +125°C ("H" model) operation. For militaryl
aerospace or harsh-environment commercial/industrial applications, MN2200H/B is available with Environmental Stress
Screening.
18 PIN DIP
Typical applications for MN2200 include: amplifying strain
guages, thermocouples and other low-output transducers; highaccuracy data acquisition systems and biomedical instrumentation.
1-----1
0300(762)
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
January 1992
Copyright· 1992
Micro Networks
All rights reserved
324 Clark St .. Worcester. MA 01606 (508) 852-5400
8-47
MN2200 HIGH-PERFORMANCE INSTRUMENTATION AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Specified Temperature
Storage Temperature
+Vcc Supply (Pin 12)
-Vcc Supply (Pin 6)
Differential Input (Pin 2 to Pin 16)
Analog Inputs (Pins 2,16)
Output Short Circuit
ORDERING INFORMATION
-55'C to +125'C
-25' C to +85' C (Standard)
-55' C to +125' C ("H" Model)
-65'C to +150'C
+18 Volts
-18 Volts
±30 Volts
±Vcc
Protected
PART NUMBER
MN2200H/B
Standard part is specified for
~
O°C to +70°C operation.
Add "H" for specified -55OC to + 125°C operation.
Add "/B" to "H" models for Environmental
Stress S c r e e n i n g . - - - - - - - - - - - - - - I
SPECIFICATIONS (T. = +25OC, ±Vcc= ± 15V unless otherwise indicated)
FIXED GAIN LEVELS (Nole 4)
G=1
G=10
MAX
G=100
TYP
MAX
G=1000
TYP
MAX
TYP
MAX
TYP
Gain Accuracy': +25'C
-25' C to +85' C
-55'C to +125'C ("H" Model)
±0.005
±0.01
±0.02
±0.01
±0.02
±0.04
±0.03
±0.06
±0.1
±0.1
±0.16
±0.25
±0.03
±0.06
±0.15
±0.1
±0.16
±0.3
±0.05
±0.14
±0.25
±0.1
±0.45
±0.6
%
%
%
Gain Nonlinearity: +25'C
-25' C to +85' C
-55'C to +125'C ("H" Model)
±0.001
±0.002
±0.004
±0.002
±0.005
±0.01
±0.002
±0.005
±0.01
±0.005
±0.01
±0.02
±0.002
±0.005
±0.01
±0.005
±0.01
±0.02
±0.02
±0.05
±0.1
±0.05
±0.1
±0.2
%
%
%
INPUT CHARACTERISTICS
Input Impedance
Differential
Common mode
Input Voltage Range
Differential
Common mode
Common Mode Rejection Ratio
G=100 DC-10 Hz
Offset Voltage (referred to input)'
Initial @ G=100 (Note 1)
Drift vs. Temperature (Note 2)'
G=1
G=1000
1-~------O171 OUTPUT 1
<>-----+-;
""
GUARD (4\
.15V
0
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
OFFSET ADJ.
+ INPUT
GAIN 2
GUARD
OUTPUT REF.
-Vee
OUTPUT 1
OUTPUT 2
9 REMOTE SENSE
~1121'Vr.r
0-------t-t--1
;...(2)0--------1
1
<5,
OUTPUT
'"
10
11
12
13
14
15
16
17
18
C2 (FILTER)
C1 (FILTER)
+Vee
X1000
X100
X10
- INPUT
GAIN 1
OFFSET ADJ.
TYPICAL CHARACTERISTICS
(TA=25°C, Supplies ±15V)
50
10
\
V
-5
/
-10
/
20
/
.5
10
\
100
TIME
150
200
100
..
.
40
lK
10K
lOOK
(,.s)
SOURCE RESISTANCE (n)
COMMON MODE REJECTION
vs. FREQUENCY
FILTER BREAKPOINT
G"000
1.'"
~
G=10
'\
~
~
~
100
I""
I"'"
10K
32K
I
1001<
SOURCE IMPEDANCE
INPUT RANGE FOR
LINEAR RESPONSE
10.0
~
I
1.0
20
0.044
0.44
15
I~
0.1
1.0
10.0
O.lK
l.OK
10K
lOOK
COMMON-MODE INPUT FREQUENCY (Hz)
32K
1 MEG
10,000
1
Source
Imbalance
r-= ~'00
G=l
100
'-......
60
J
10
~
--- r---....
---
01
60
V
L Ko,1
120
100
/
\
I
~
/
I--
50
...
~
120 ~O()
V
0'1 '0100 \
Rl~lK I
C~=l00 pi
/
CMR VS. SOURCE
IMPEDANCE IMBALANCE
RMS INPUT NOISE VOLTAGE
VS SOURCE RESISTANCE
STEP RESPONSE
4.4
Cy.F1
//
kft7
PoSItIve
Inp~!
voltage
10
""
~
44.0
~
~ega"ve
t7
10
C1 (Pin (l1)=C
C2 (Pin (10)"C/2
Inp~!
voltage
15
20
SUPPLY VOLTAGE (V)
8-49
i
INSTRUMENTATION AMPLIFIERS
ADVANTAGES:
Instrumentation Amplifiers are committed, closed loop, gain
blocks that offer significant performance advantages over simple
operational amplifiers.
The principle advantages provided by Instrumentation Amplifiers
are:
•
•
•
•
•
Very high input impedance that is independent of gain.
Very high common mode rejection ratios.
High accuracies.
Low Drifts.
Addition of guard and reference terminals to compensate
for noise and external wiring resistance.
• Immunity to temperature variations.
APPLICATIONS:
Instrumentation Amplifiers are used to accurately amplify high
impedance low level signals, in the presence of noise and common mode voltages.
Typical applications include:
Amplifying thermocouples, strain gauges and other low level
transducers, high accuracy data acquisition systems and biomedical monitoring.
OFFSET ADJUSTMENT:
The MN2200 meets all specifications without adjustment. However, the initial offset voltage (200p.V max. referred to input) may
be adjusted to zero with the addition of a trim pot between pins 1
and 18 as shown in the block diagram. A 10 turn <100 ppm/oC
TC trim pot should be used for best performance.
GUARD TERMINAL:
The MN2200 incorporates a guard (Pin 4) to drive the input cable
shield when long input runs are necessary. The use of the guard
and shielded input cable greatly reduces the effects of common
mode voltages and induced noise and is recommended for noisy
environments and input lead runs of more than a few inches.
REMOTE SENSE:
Another feature of the MN2200 is the Remote Sense Terminal.
The Remote Sense is used to eliminate the effects of external
lead resistance and insure that an accurate output voltage is
present at locations remote from the actual instrumentation
amplifier.
OUTPUT REFERENCE:
The MN2200's Output Reference Terminal can be used in conjunction with the Sense Terminal to provide accurate output
voltages at locations remote from the instrumentation amplifier.
The Output Reference can also be used to offset the instrumentation Amplifier's output by a fixed amount. Any voltage applied
between analog ground and the Output Reference will appear as
a fixed offset in the output. When used as an offsetting input, the
Output Reference is a 20 k Ohm Resistive load. If not used to
offset the output, the Output Reference Terminal should be
connected to analog ground.
APPLICATIONS INFORMATION:
GAIN SETTING:
The MN2200 includes internal laser trimmed thin film resistors
for gains of 1, 10, 100, and 1000. These internal resistors track
very closely with the other resistors in the amplifier providing
superior performance over temperature, and should be used
whenever possible.
OPTIONAL 2 POLE BUTIERWORTH FILTER:
A unique feature of the MN2200 is the internal two pole Butterworth filter. Two external capacitors applied to pins 10 and 11 set
the breakpoint of this filer from full bandwidth to well below 1 Hz.
The breakpoint of the filters is defined by:
..
-(~)
f (Hz) - C(l'f)
C1 (Pin 11) = C
C2 (Pin 10) = C/2
Connections for internal gain selection are as follows:
Gain
1
10
100
1000
Connect
Pin to Pin
No connection
15 to 3
14 to 3
13 to 3
In addition, the gain can be set to any value>1 with the addition
of a single resistor connected between pins 3 and 17. Specifications will be gradually degraded for gains in excess of 1000.
This gain setting resistor should be low TC «10 ppm/OC) metal
film for best performance.
The value of the external gain setting resistor is defined by,
Gain = 1 + (4x H)')
R
The gain error of the above equation is typically 0.1% and a
maximum of 0.5% for gains>I.0. Gain drift with temperature will
be less than 0.006%IO C if resistors with TC's of 10 ppm/oC or
less are used.
8-50
OUTPUTS:
The MN2200 has two analog outputs: pins 7 and 8. Normally the
Pin 8 output, which includes the optional filter stage, is used. A
slight improvement in offset drifts may be achieved at gains < 10
by using the pin 7 output.
The pin 8 output must be used if remote senSing is employed.
GENERAL CONSIDERATIONS:
While Instrumentation Amplifiers have inherently high common
mode and power supply rejections, good bypassing, shielding,
and grounding techniques should be employed.
Input leads should be shielded and the power supplies bypassed
with IOl'f capacitors close to the amplifier.
In addition, when an external gain setting resistor is used it is
preferable to locate it close to the amplifier. If it is necessary to
locate this resistor more than a few inches from the amplifier
shielded leads should be used. Remotely locating the gain setting
resistor may degrade CMRR at high frequencies.
TYPICAL APPLICATION
I-~~,,~";,;"",,c
MN2200
'L
OUTPUT
"ff
GLJARD
ANALOG
GND
INSTRUMENTATION AMPLIFIER
SPECIFICATION DEFINITIONS
Gain-The ratio of the change in output voltage to the change in
input voltage.
Gain Nonlinearity-Maximum deviation from the ideal gain
transfer function over the full output range.
Small Signal Bandwidth-Frequency at which the amplifiers
gain drops 3 dB from its D.C. gain.
Settling Time-Time required for the output to reach specified
accuracy for a given change in the input.
Gain Accuracy-The percentage that actual gain differs from
ideal gain.
Common Mode Rejection Ratio-The ability of the amplifier to
reject signals common to both the plus and minus inputs and
extract the desired signal appearing between the plus and minus
inputs. Usually given as the ratio of differential gain to common
mode gain.
Differential Input Impedance-Impedance seen looking into the
plus and minus input terminals with respect to each other.
Common Mode Input Impedance-Impedance seen looking into
either the plus or minus input with respect to analog ground.
Initial Offset Voltage (referred to input)-Collection of internal
voltage offsets summed and treated as a single offset appearing
in series with the input. This offset, multiplied by the programmed
gain, will appear at the amplifier output. This can normally be
zeroed out with an external trimpot.
Offset Voltage Drift (referred to the input)-Drift in initial offset
voltage due to temperature variation.
Offset Voltage vs. Supplies-Change in initial offset voltage due
to variations in power supply voltages.
Voltage Noise (referred to input)-Sum of the internal noise
sources treated as a single source appearing in series with the
input signal. This noise, multiplied by the programmed gain, will
appear at the amplifier output. Voltage noise is dependent on
bandwidth and may be reduced by using the minimum bandwidth
necessary for a given application.
Filter Breakpoint-Frequency where the output is attenuated
3 dB by the internal filter.
Output Voltage Swing-Maximum allowable output excursion
for faithful reproduction of the input signal. This is limited to
several volts less than the associated power supply.
Output Drive Current-Current thai the amplifier will source or
sink to the load while remaining within specification.
Output Impedance-Source impedance of the amplifier output.
Output Load Capacitance-Maximum capacitive load that the
amplifier can drive while remaining stable and within specification.
Slew Rate-Rate of change of the output in response to a step
change at the input.
8-51
APPLICATIONS INFORMATION:
BIOELECTRIC AMPLIFIER
+15V
CATHODE
RAY
OSCILLOSCOPE
ELECTRODES
-15V
The circuit shown may be used to measure any of a number of bioelectric phenomena.
The MN2200 high performance instrumentation amplifier is used to amplify and buffer low level signals from
the bioelectric probe. The amplified signals are then displayed on a cathode ray oscilloscope or recorded by a strip
chart recorder.
In general both AC and DC characteristics of a waveform with peak amplitude on the order of 10MV are
measured. Since the electrodes used exhibit an output impedance of 20-100K it is necessary to use the MN2200's
guard terminal to drive the input cable shield. This minimizes common mode error caused by the wire to shield
capacitance of the input cable interacting with the unbalanced electrode impedances.
Next, there must be a path for instrumentation amplifier input bias current return.
In this circuit, the bias current return is provided by the ground plate on the skin surface. The internal fixed
gain of 1000 is used because an accurate, absolute measurement of the magnitude of the input voltage is desired.
Also, wiring of the output circuit should be done so as to minimize errors caused by current flowing in ground
lines or current drawn by the load. This is done by 1) connecting the instrumentation amplifier reference terminal to
the ground reference of the load and 2) connecting the output sense terminal directly to the output side of the load.
A cutoff frequency (50HZ) is used in the active filter section of the MN2200 to reduce noise while maintaining
sufficient bandwidth to display the AC component of the measured signal.
CURRENT OUTPUT TO
... GROUNDED LOAD USING
CURRENT SENSING
USING AN OUTPUT CURRENT BOOSTER
-15V '15V
SENSE
OFFSEnlNG THE OUTPUT WITH
REMOTE GAIN SWITCHING
THE OUTPUT REFERENCE
15V·15V
-15V ',5V
8-52
UJJ
_
MN4000
40nsec 12-Bit LINEAR
T/H AMPLIFIER
MICRO NETWORKS
DESCRIPTION
The MN4000 is a very high-speed (40nsec signal acquisition to
± 0.01%FSR), high-resolution (± O.024%FSR maximum gain
linearity error). unity-gain, non-inverting track-hold (T/H)
amplifier. The MN4000 is suitable for applications where
high-speed performance is required in conjuction with
high-resolution.
FEATURES
• ± 0.024% FSR Maximum
Gain Linearity Error
• 40nsec Full Scale
Acquisition Time (to 0.01%FSR)
• Low 30mVp-p
T/H Transient
• Fast 25nsec T/H
Transient Settling Time
• 50MHz Small Signal
Bandwidth
• Functionally Compatible
with Industry Standard
-001010025
• DESC SMD 5962-90856
Listed
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
The MN4000 is packaged in a small, 24-pin, hermetically
sealed, side-brazed DIP and maintains an established
industry-standard pinout making it a functionally compatible,
performance upgrade in applications utilizing -001010025
type devices.
The MN4000 is available fully specified for either O°C to +70°C
or -55° to +125°C (H, H/S and H/S CH models) operation.
For military/aerospace or harsh-environment commercial/industrial applications, the MN4000 HIS is available
environmentally stress screened. Consult factory for availability
of MN4000 H/S CH. Additionally, the MN4000 is listed on DESC
SMD 5962-90856.
24-PIN SIDE BRAZED DIP
PIN 1
T~
1~~U:~1
1'00(27.94)
1.270(32.26)
'----~
&::g~:~:lj
t!===~
9153(3891
0.183 (4.65)
; IJdU
0019(0.48)
~200(5.081
0230 (5.84)
lo~~ I~~
APPLICATIONS
I
High-Speed Signal Processing
RADAR and IF Processors
Instrumentation Systems
EW and ECM Systems
Video Digitizers
Communications Systems
0012 (O.30)
~O.600(1524}-J
Subranging AID Converters
Dimensions in Inches
(millimeters)
[1JJ
_
MICRO NETWORKS
324 Clark
April 1992
Copyright' 1992
Micro Networks
All rights reserved
81. Worcester, MA 01606 (508) 852·5400
8-53
MN4000 40nsec 12·Bit LINEAR T/H AMPLIFIER
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range:
Specified Temperature Range:
MN4000
MN4000H, H/B
Storage Temperature Range
± 15V Supply (± Vee, Pins 22, 3)
+5V Supply (± Voo, Pin 9)
-5.2V Supply (± Vee, Pin 4)
Analog Input (Pin 13)
Digital Input (Pin 5)
SPECIFICATIONS (TA
-55°C to + 125°C
OOC to +70°C
-55°C to + 125°C
-65°C to + 150°C
± 18 Volts
-0.5 to +6.5 Volts
+0.5 to -6.5 Volts
±2 Volts
o to to -3 Volts
JI
PART NUMBER
MN4000H/BCH
Standard device is specified for
O°C to +70° operation.
Add "H" suffix for specified -55°C to + 125°C operation.
Add "/B" suffix to "H" model for environmental stress screening.
Add "CH" to H/B models for 100% screening
according to MIL-H-38534. Consult factory
for availability of "CH" d e v i c e s . - - - - - - - - - - - - '
=+2SoC, Supply Voltages ± lSV, +SV and -S.2V unless otherwise indicated) (Note 1)
ANALOG INPUT/OUTPUT
Input/Output Voltage Range (Note 2)
Input Impedance (Note 2)
Output Cu rrent (Note 2)
Output Impedance (Note 2)
MIN.
TYP.
MAX.
UNITS
±1
10
Volts
±25
0.5
mA
!l
-1.8
Volts
Volts
±500
±500
pA
pA
k!l
0.25
DIGITAL INPUT
Logic Levels: Logic "1"
Logic "0"
-0.8
Logic Currents: Logic "1" (VIH = -0.8V)
Logic "0" (VIL=-1.8V)
TRANSFER CHARACTERISTICS
VN
Gain
Gain Error: Initial (+25°C)
Over Temperature
+1
±0.25
±1
±0.5
±2
%FSR
%FSR
Gain Linearity Error
±0.012
±0.024
%FSR
Input Offset Voltage: Intial (+25°C)
Over Temperature
±1
+10
±5
± 15
Pedestal: Initial (+25°C)
Over Temperature
±2
±10
±7
±15
mV
mV
mV
mV
DYNAMIC CHARACTERISTICS
Acquisition Time: 2V Step to ± 0.1% (± 2mV)
2V Step to ± 0.01% (± 0.2mV, Note 2)
30
40
Track-to-Hold Transient: Height (Peak to Peak)
Settling Time (to ± 2mV)
20
25
Aperture Delay Time
Aperture Jitter (Note 2)
Slew Rate (VIN = -1V to + 1V Step) (Note 2)
Small Signal Bandwidth (VIN =1V AC p-p) (Note 2)
30
nsec
nsec
mVp-p
nsec
5
nsec
±20
ps(rms)
200
250
VlpSec
50
60
MHz
40
MHz
Large Signal Bandwidth (VIN =2V p-p) (Note 2)
Feedthrough Attenuation (VIN =2V p-p @5 MHz)
50
60
30
60
72
Droop Rate: Initial (+25°C)
Over Temperature
50
Harmonic Distortion (Track Mode, VIN = ± 1\1, 5MHz)
-72
dB
200
20
~VlpSec
mVipSec
dB
POWER SUPPLY REQUIREMENTS
Power Supply Range: +Vee Supply
-Vee Supply
+Voo Supply
-VEE Supply
+15
-15
+5
-5.2
+15.45
-15.45
+5.25
-5.7
Volts
Volts
Volts
Volts
Current Drain: +Vee Supply
-Vee Supply
+Voo Supply
-VEE Supply
+8
-8
+50
-50
+10
-10
+70
-70
mA
mA
mA
mA
Power Supply Rejection Ratio: +Vee Supply
-Vee Supply
+VDD Supply
-VEE Supply
±8
±8
±8
±8
±15
± 15
± 15
±15
mVN
mVN
mVN
mVN
Power Consumption
750
1014
mW
SPECIFICATION NOTES:
1.
2.
8-54
RL = 100!l, CL = 50pF.
These parameters are listed for reference only and are not tested.
+14.55
-14.55
+4.75
-5.0
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS - The M N4000 is a high-resolution
high-speed device and requires that careful attention be paid to
layout, grounding and bypassing in order to achieve specified accuracy and speed performance. Coupling between analog input
and digital signals should be minimized to avoid noise pickup. Care
should be taken to avoid long analog runs in parallel with the digital
lines. In addition, particular attention must be paid to the device's
external hold capacitor connection. Pin 20 should be isolated from
digital signals and it is recommended that the pin be shielded by
ground.
The units five ground pins (pins 7,11,18,19, and 21) should be tied
together at the device and connected to system analog ground
preferably through a large, low-impedance analog ground plane
beneath the device.
If p.c. card ground runs must be run separately, wide conductor
runs should be employed with O.OluF ceramic capacitors interconnecting them as close to the device as possible.
Power supply connections should be as short and direct as possible, and all power supplies should be decoupled with highfrequency bypass capacitors to ground. It is recommended that
II'F tantalum capacitors in parallel with O.OII'F ceramic, surfacemount chip capacitors be located as close to the device pins as
possible.
TRACK-HOLD COMMAND - A Logic "0" applied to the TrackHold (T/H) Command input (pin 5) drives the device into the track
(sample) mode. In this mode, the MN4000 operates as a unity gain
amplifier (follower) and its output tracks (follows) the applied analog
input signal. A Logic "I" applied to the T/H Command (pin 5) drives
the MN4000 into the hold mode holding the output of the device
constant at the level present when the hold command was given.
The MN4000's T/H Command input is illustrated below. This input is compatible with ECL logic devices. However, precautions
should be taken in certain test circuits where the T/H Command
input is not driven with standard ECL logic devices (burn-in and
life test circuits for example). Care should be taken to avoid exceeding the absolute maximum ratings when hardwiring this input to negative supply voltages. In these cases when the T/H Command input is connected to a voltage supply, we recommend the
use of a series 10kO or greater resistor as shown below.
TIH Command
VT = -1.3V
Pin 5
applied T/H Command to the point where the T/H output has setlied
to within the specified band. The acquisition time of the MN4000
includes the gate delay of the switch, output amplifier delay,
effects of slew rate and the actual settling of the output signal. For
further discussion of acquisition time and other T/H amplifier
related specifications, refer to the data book tutorial section labeled
Track and Hold Amplifiers.
DRIVING CAPACITIVE LOADS - Care must be taken to optimize
the performance of the MN4000 in circuit applications with high
capacitive loading at the megahertz frequencies these devices are
designed to handle. In particular, the series inductance of the wire
or p.c. card run connecting the MN4000 to its capacitive load is
no longer insignificant. In order to obtain the quickest settling at
the load in response to a driving function at the T/H output, it will
be necessary to add a series resisitor such that the resulting RLC
circuit is critically damped. The value of the damping resisitor will
depend upon the length of the wire (or run) and the load
capacitance.
Critical damping occurs in a series RLC circuit when the resonant
radian frequency two) equals the exponential damping coefficient
(,,).
Since
w" = 1/,'LC
and
" = R/2L
it follows that
R = 2.jLlC
Where R is required value of series resistance, L is the wire (or run)
inductance and C is the load capacitance. in making calculations,
an inductance of 23nHylin. can be assumed for straight, solid wire
of AWG 20 to 28, or p.c. ru ns of 100 to 600mil 2 cross-sectional area.
This value should also serve as a good starting point for experimentation if other shapes or wire sizes are used. Bear in mind that
critical damping only guaranteed best settling for a given combination of Land C. There will still be practical limits on the values these
can assume if settling is to be accomplished in a reasonable time.
The voltage at the load capacitor will be the form
V(t) =All-{at + l)e
-""I
in response to a step of am pi itude A althe T/H output. For settl ing
to 0.1%, v{t) = 0.999A and, from the equation above, at = 9.23.
Sincea = wo = l/y'LC, it follows that the settling to ± 0.01% of the
step size occurs at the t = 9.23y'LC.
As an example, assume CLOAD = 200pF and that it is 2.2 inches
from the T/H ouput. This corresponds to a wire inductance of
L=23nHy/in. x 2.2in.=51nHy. For critical damping, R=2y'LiC
=320. This resistor should be a carbon or other non-inductive type,
and its length will count as part of the inductance to be damped.
With C and L as above the settling time to ± 0.1% will be
t=9.23y'LC =30nsec.
10k
or
Greater
-5.2V
-v
MN4000 ACQUISITION TIME - The MN4000's signal acquisition time is specified for full scale steps settling to a specified limit
(± O.I%FSR for 10-bit applications and ± O.OI%FSR for 12-bit applications). It is important to note, for the purpose of comparision,
that Micro Networks specifies this parameter from the edge of the
The actual settling time in any given situation will be somewhat
longer than predicted above due to the effects of the settling time
of the T/H itself. A very good approximation of the overall settling
time can be obtained by assuming the two components add as the
square root of the sum of their squares. In the above example,
assumi'l9. 30nsec settling time for the T/H to ± 0.1%, this would
mean y'30 2 +30 2, or about 42nsec total settling from the time a step
is applied to the input of the T/H to the time voltage seen be the
AID settles to ± 0.1% of its final value.
For 12-bit applications the calculations are as shown above where
settling is specified to ± 0.01% and settling occurs at 11.75y'LC.
8-55
PIN DESIGNATIONS
Pin 1
24
12
13
2
3
4
5
6
7
8
9
10
11
12
N.C.
N.C.
-15V Supply
-5.2V Supply
Hold Command
N.C.
Ground
N.C.
+5V Supply
N.C.
Ground
N.C.
24
23
22
21
20
19
18
17
16
15
14
13
Analog Output
N.C.
+15V Supply
Ground
Aux Hold Capacitor
Ground
Ground
N.C.
N.C.
N.C.
N.C.
Analog Input
Notes:
"No Connects" (N.C.) are not connected to internal circuitry.
BLOCK DIAGRAM
,----------<> (Pin 20) Aux. Hold Capacitor
Analog Input (Pin t3)
0----\
>--<> (Pin 24) Analog Output
X1
ICHOLD
T/H Command (Pin 5)
0-------1
+15V Supply (Pin 22) 0 - - -••
-15V Supply (Pin 3) 0 0 - - -••
+5V Supply (Pin 9) 0
•
-5.2V Supply (Pin 4) 0
•
Ground (Pins 7, 11, 18, 19, 21) 0
•
~
8-56
Pins 1, 6, 8, 10, 12, 14, 15, 16, 17 and 23
are not connected to internal circuitry (N.C.).
MICRO NETWORKS
324 Clark SI., Worcester, MA 01606 (508) 852-5400
Data Acquisition Systems
I
Data Acquisition Systems
A single-package data acquisition system (DAS) is a device that clearly
utilizes hybrid techhology's ability to combine IC's from different fabrication technologies to take advantage of the best aspects of each in a
single functional design.
The MN7150-8 and MN7t50-16 are excellent examples of this "hybrid
advantage". The MN7150 Series devices consist of an overvoltage protected CMOS multiplexer; a BiFeI instrumentation amplifier; a lowleakage dielectrically isolated T/H amplifier; and a high-speed bipolar
AID converter. All these IC's are combined and functionally lasertrimmed in a single design to give true 12-bit performance (± 'hLSB linearity) and 50kHz throughputs. MN7145 Series DAS's contain similar fuctions and also add a complete p.P interface (3-state buffer, address line,
read/write line, etc.) faCilitating direct microcomputer control.
Micro Networks pioneered the complete, single-package, data
acquisition system in 1975 with the MN7120 (8-bit, 8-channel, 90kHz
DAS). Three years later, our MN7130 (DAS front end) gave users the
MN7208
MN7216
Data Acquisition
Front End
FEATURES
• Complete DAS Front End:
Analog Input Multiplexer
Instrumentation Amplifier
LoadlSequence Control Logic
• Small 40-Pin DIP
• 1S-Single Ended or
8-Differential
Input Channels
• 10",sec Channel Switching
and In-Amp Settling Time
• Full Mil Operation
-55°C to + 125°C
• Use with MNSOOO Series
Sampling AID Converters
for Multi-Channel Digitizing
• Fully Specified O°C to +70°C
(J and K Models) or
-55°C to +125°C
(S and T Models)
9-2
flexibility of selecting their oWn AID converter. The MN7130 may be combined with the MN574A (or ADC80) to easily configure a low-cost, p.Pcompatible, 12-bit DAS. For military/aerospace applications, our MN7140
(12-bit, 20kHz DAS) was the first, single-package, 12-bit DAS to operate
over the -55°C to +125°C temperature range and withstand the rigors
of MIL-STD-883 screening. The MN7140 is joined by the MN7150 and
MN7145/46/47 which also offer extended temperature operation and
MIL-STD-883 screening performed in Micro Networks MIL-STD-1772
qualified facility.
Today, these products are joined by another Micro Networks first, the
MN7450, a small, single package, 8-channel, 16-bit Data Acquisition
System. This device is a complete dataacquisition function in a small
40-pin DIP and contains an analog input multiplexer, software programmable gain amplifier, inherent T/H function, internal clock, reference, and
a self-calibrating 16-bit AID converter cornplete with microprocessor interface control lines.
MN7450
MN7451
a-Channel, 16-Bit
Data Acquisition System
FEATURES
• Complete DAS:
Latched Input MUX
Software Programmable
Gain Amplifier
Buffer Amplifier
Inherent TIH Function
Internal Reference
Internal Clock Option
1S-Bit Self-Calibrating
AID Converter
• Small Double-Wide 40-Pin DIP
• 8 X 2 Byte Output Format
• 8 Single-Ended
Input Channels
• Input Over-Voltage Protection
• Low Initial Gain and
Offset Error
• Fully Specified OOC to +70°
(J and K Models) or
-55°C to + 125°C
(S and T Models)
Data Acquisition Systems
Acquisi·
Conyer· Through·
tion
Time
sian
pul
Inpul a ±V2LSB Time (Channels!
sec)
Channels ("sec) II'sec)
90,000
5
6
8
Maximum
Linearity
Error
(DfoFSR)
Power
(mW)
DIP
Package
±0.2
680
32 Pin
Hi·Rel
Option
DESC
SMD
(5962·)
Page
No.
oto +70
-55 to +125
Yes
(Note 1)
9-5
62 Pin
oto +70
-25 to +85
-55 to +125
Yes
(Note 1)
9-31
710
28 Pin
oto +70
-55 to +125
Yes
(Note 1)
9-23
±0.012
1250
40 Pin
oto +70
-25 to +85
-55 to +125
Yes
9079701
9-15
N.A.
±0.002
(Typ)
900
32 Pin
oto +70
-55 to +125
Yes
9057101
9-9
47,700
(Note 3)
±0.0015
658
40 Pin
oto +70
-55 to +125
Yes
(Note 1)
9-45
N.A.
±0.003
245
40 Pin
oto +70
-55 to +125
Yes
(Note 1)
9-39
Resolu·
lion
Model
8·Bils
MN712D
12·Bils
MN7150·8
MN7150-16
8
16
9
9
55,000
±0012
1785
MN7145
MN7146
MN7147
8
8
20
35,000
±0.012
±0.024
MN714D
8
(Expandable)
8
40
20,000
MN7130
16
(Expandable)
6.5
N.A.
MN745D
MN7451
MN72D8
MN7216
8
15
16
(Note 3) (Note 3)
8
16
10
(Note 2)
16·Bils
N.A.
Specified
Temp
Range
(OC)
NOTES: 1. Contact the factory for information regarding DESC SMD's for these device types.
2. Specification is for settling time including MUX switching and instrumentation amplifier settling time.
3. Due to the design of the MN7450 Series DAS, the channel switching and PGA settling time can be pipelined with AID
conversion allowing for total throughput in the pipelined mode of 47.7kHz.
r/ Indicates New Product.
9-3
MICRO NETVVORKS
~
9-4
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
December 1991
Copyrighl lO ·I991
Micro Networks
All rights reserved
MN7120
lh!J
_
8-Bit, 8-CHANNEL
DATA ACQUISITION SYSTEM
with 3-STATE OUTPUTS
MICRO NETWORKS
DESCRIPTION
FEATURES
• Complete System:
Input Multiplexer
Track-Hold Amplifier
8·Bit AID Converter
3·State Output Buffer
Control Logic
• Small 32·Pin DIP
• ±1/2 LSB Linearity and
No Missing Codes Guaranteed
Over Temperature
• Random or Sequential
Addressing
• 75,000 Channels/sec
Guaranteed Throughput
• Full Mil Operation
-55"C to +125"C
• MIL·H·38534
Screening Optional.
MIL·STD·1772
Qualified Facility
32 PIN DIP
PIN 1
\
MN7120 is a complete, 8-bit, 8-channel data acquisition system
with 3-state outputs in a single, 32-pin, hermetically sealed dualin-line package. Contained in the single package are input
multiplexer with address register, track-hold (T/H) amplifier, AID
converter, 3-state output buffer, clock and all the necessary controlling logic. The basic system's 8 input channels can be either
randomly or sequentially addressed, and input impedance is
greater than 10 megohms. The number of input channels is
easily expanded with external multiplexers.
MN7120 is actively laser trimmed as a complete device
eliminating the normally annoying DAS errors such as T/H
pedestal error. The system is adjustment-free. No external gain
or offset adjusting potentiometers are required to guarantee an
overall system error of better than ± 1 LSB at +25°C and better
than ±2 LSB's over the entire operating temperature range.
The MN7120's T/H has an acquisition time of 6JLsec, and the AID's
conversion time of 7JLSec allows an overall throughput rate of over
75,000 channelslsec. The standard device is fully specified for
either O°C to +70°C or -55°C to +125°C ("H" model) operation.
The MN7120H/B is available with Environmental Stress Screening
while the MN7120H/B CH is fully screened in accordance with
MIL-H-38534.
MN7120's output buffer facilitate interfacing to microprocessor
and microcomputer buses. Normally, simple address decoding
is all that has to be added to give data acquisition capability to
your microprocessor-based system. MN7120 is ideally suited for industrial control and monitoring systems. Highly reliable thin-film
hybrid construction, optional MIL-H-38534 screening, and performance specifications guaranteed from -55°C to + 125°C make it
the right choice for low-resolution military/aerospace data acquisition requirements.
I
Dimensions in Inches
(millimeters)
~
May 1988
MICRO NETWORKS
324 Clark St.. Worcester. MA 01606 (508) 852-5400
9-5
MN7120 8-Bit 8-CHANNEL DAS with 3-STATE OUTPUTS
ABSOWTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN7120
MN7120H, MN7120H/B
Storage Temperature Range
+15V Supply (Pin 19)
-15V Supply (Pin 20)
Logic Supply (Pin 21)
Analog Inputs (Pins 8-15)
Digital Inputs (Pins 1-4, 32)
ORDERING INFORMATION
PART NUMBER
-55°C to + 125°C
MN7120H/B CH
Standard Part is specified for O°C tO~700C
operation.
Add "H" for specified -55°C to +125°C
operation. - - - - - - - Add "/B" to "H" models for
Environmental Stress Screening.
Add "CH" to "/B" models for
100% screening according to MIL-H-38534.------I
OOC to +70 oC
-55°C to + 125°C
-65°C to + 150°C
-0.5 to +18 Volts
+0.5 to -18 Volts
-0.5 to +7 Volts
±15 Volts
-0.5 to +5.5 Volts
SPECIFICATIONS (TA=+25OC, ±Vcc= ±lSV, +Vdd=+SV unless otherwise indicated)
ANALOG INPUTS
MIN.
TYP.
MAX.
UNITS
Number of Input Channels (Note 1)
Input Voltage Range
8
±10
Volts
Input Impedance
Direct T/H Input Impedance (Pin 16)
10
10
Mohm
Mohm
Resolution
Quantization Error
8
± '/2
Bits
LSB
Integral Linearity Error: Initial (+25°C)
Over Temperature (Note 3)
±1/e
±1!4
± '/2
±'/2
LSB
LSB
Zero Error (Note 4): Initial (+25°C)
Over Temperature (Note 3)
±1f4
±V2
±1
±1
LSB
LSB
Full Scale Absolute Accuracy (Note 5): Initial (+25°C)
Over Temperature (Note 3)
±V2
±1
±1
±2
LSB
LSB
5
50
6
6
90
7
TRANSFER CHARACTERISTICS (Note 2)
DYNAMIC CHARACTERISTICS
T/H Acquisition Time (Note 6)
T/H Aperture Delay Time
AID Conversion Time
Throughput Rate (Channels/sec)
75
Crosstalk Attenuation
65
~sec
nsec
~ec
kHz
dB
POWER SUPPLIES
Power Supply Range: ±15V Supply
+5V Supply
Power Supply Rejection: +15V Supply
-15V Supply
+5V Supply
±5
±5
%
%
±0.04
±0.001
±0.001
%FSR/%Vs
%FSR/%Vs
%FSR/%Vs
Current Drains: +15V Supply
-15V Supply
+5V Supply
+10
-12
+70
+16
-25
+110
mA
mA
mA
Power Consumption
680
1165
mW
SPECIFICATION NOTES:
1. Eight single-ended input channels can be increased with external multiplexers.
applies at both positive and negative full scale. It is defiried as the difference bet-
2. For an 8-bit system with a 20V FSR (full scale range), 1 LSB is equal to 78.1mV.
3. MN7120 is fully specified for OOC to +70°C operation. MN7120H and MN7120H/B
are fully specified for -55°C to +125°C operation.
4. Zero error is defined as the difference between the ideal and the actual input voltage
at which the digital output just changes from 0111 1111 to 10000000. The ideal value
ween the ideal and the actual input voltage at which the digital output just changes
from 11111110 to 1111 1111 or from 00000000 to 0000 0001. The former 1ransition
ideally occurs at an input voltage 1 LSB below the nominal positive full scale voltage.
The latter ideally occurs 1 LSB above the nominal negative full scale voltage. See
Digital Output Coding.
6. Specified for a 20V step acquired to ± 'hLSB.
at which this transition should occur is 0 Volts.
5. Full scale absolute accuracy BFror includes offset, gain, linearity, noise and all other
errors and is specified without adjustment. The full scale accuracy specification
Analog Input
(DC Volts)
9-6
Digital Output
MSB
LSB
+10.000
+9.922
1111
1111
1111
llH)'
+0.078
0.000
-0.078
1000
OOOll'
0111
1110"'
-9.922
-10.000
0000
0000
0000'
0000
filfill'll'l filfilfilg!'
"Voltages given are the theoretical values for the transitions indicated.
Ideally, with the system continuously sampling and converting, the output bits indicated as ~ will change from a "1" to a "0" or vice versa
as the input vol18ge passes through the level indicated. The transition
from digital output 0000 0000 to digital output 0000 0001 (or vice versa) will ideally occur at -9.922V Subsequently, an input voltage more
negative than -9.922V will give an output of all "O's". The Iransition
from digital outpul 0111 1111 to digital outpul1000 0000 (or vice versa)
will ideally occur at an input of zerovolls. The 11111110 to 11111111 tran·
sition should occur a1 +9.922V. An inpul grea1erthan +9.922V should
give all "1's".
INPUTS
BLOCK DIAGRAM
It is recommended that unused analog inputs be
grounded.
ADDRESSING
Both sequential and random addressing are available
in the MN7120. For sequential addressing connect
LOAD to logic "1". Channels will sequence from 0 thru
7, advancing one channel on the leading edge of each
TRIGGER pulse. For random channel addressing the
channel address (421 binary code) is applied to the
CHANNEL ADDRESS INPUTS with LOAD at logiC
"0". The rising edge of the next TRIGGER pulse will
update the channel address. The CHANNELADDRESS
OUTPUTS, when enabled, indicate the last channel
selected.
DIGITAL INPUTS AND OUTPUTS
8.e used for exp,msion.
Logic"O"<04V
Logic'T':>4.OV
O!sableslnternaIMu~
-----1---
--f----- - - - - - + - - - - - - - j
Channel Aridress 3l,nes 421
Inputs
ls,nary
-----t -,Ota 1
L
I
F
'll::--- - [ - --
A~feSSE~b~
Data
~~able'-
Outputs
1
I ..
I
~-..
-
.
PIN
1
2
3
4
5
6
7
8
9
10
"
12
13
14
15
16
-
CLOCK
t20Pf
I;;-n~-~
• Parallel
30k
4OOnSl!cMax can bev8ned oran external
clock used
t
",--:;;:--- Lel/;'--
1 uA --
t~el
-
1SMl1z Max
Clock.ate
Tie 10 togic "T"if
Address Output is not
needed.
Tie to logic "0" jf
~~:~::d~utPuts
are not
Description
,....
Noial
Parallel digital data outputs
1 TTL
Output data is valid after E.O.C. goes low.
BI~~~MSBtht~~ _ _ -i- __--j-_ _ _ _ _ _ _ _------I
c~annel.addres.& outputs
I 1 TTL
IndicatllS channel being converted.
3hnes
··0"
ConverSion process complete 6 TTL
oulputdalavahd
NRZ
Se,;aIDataOutput
I
FUNCTION
Address Input - 1
Address Input - 2
Address Input - 4
load
Serial Data Output
Data Enable Input
Address Enable Input
Channel 0
Channell
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Sample/Hold Input
'TTL
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
The rising edge of a positive TRIGGER pulse updates
the channel address, the falling edge commands the
sample/hold to the sample mode.
~_ flrstrlsmgedgeollngger
l00.n5ec
.. -..-- ----------.- ---r-------"------1
1
Serial Data
Must be set up 100 nSec
before docking tTigger and
Mall.
Channel Add,essl42' Bmary
Outputs'
-----~
1
S~tem~IO~k-
__
rrL
Th,ee State Buffers
!True Bmary
E.O.C
_---I
Enables Data Output
_
L-
Aa~omAddressMOde
Starls Data AC(jUISI"on
Process
Three State Buffers
L-- . -- _____ .1.
~
125 nSec
~:Add"$M"";-t;T-..·-- ":~--- -D,"w;""~o'~'d;.:;;:-
~nableSAddressOutPut
1"0- -
~
~i-~'''~
L~lgnal
I Data Outputs
TTL
bellalidthraughriSlngedge
of trigger.
-;:;----- .--;~\.Ier
L~
Selects desired channel
m random address mode
TRIGGERING
E.O C. goes to logic ."" 5 uSec after trigger
returns I.OW.and returns to logic "0" When
conversion IS complete.
Oulpul ocCurs dunng the AID con'fflrsion
period.
FUNCTION
Mux Enable
Ground
+ 15 Volts
-15 Volts
+5 Volts
MSBOut
Bit 2
Bit 3
Bit 4
Bit 5
Bit 61 Address Output - 4
Bit 71 Address Output - 2
l S B I Address Output - 1
End of Conversion
Clock Inl Adj
Trigger Input
The MN7120 can be operated from it's internal clock or
an external clock applied to the CLOCK INPUT. The
internal clock is disabled during analog signal acquisition to reduce noise. A resistor (20k ohms or higher)
connected from the CLOCK INPUT to +5V will increase the clock rate inversly with resistance. If the
resistor is connected to ground the clock frequency
will decrease inversly with resistance. The clock rate
can be observed as an RC charging waveform of 0.5Vp
at the CLOCK INPUT. Loading at this point should be
greater than 10M ohms to avoid shifting the clock rate.
THREE STATE OUTPUTS
Three state buffers are employed on the data and
channel address outputs. Channel address or data
outputs are selected by a logic "0" on the corresponding ENABLE INPUT. If neither ENABLE is selected the
8 output lines will assume a high impedance state.
The CHANNEL ADDRESS and DATA outputs should
not be enabled simultaneously. Parallel data will be
valid in 95 nsec after the Enable pulse goes Low.
SERIAL DATA OUTPUT
The MN7120 provides serial as well as parallel data
output. The first falling edge of the Bit 2 output can be
used to indicate the start of the serial output data.
9-7
TIMINd DIAGRAM
RANOOM ADDRESS MODE
SEQUENTIAL ADDRESS MODE
TRIGGER INPUT
~L_ _ _ _ _ _ _ _ _ _ _ _ __
____~rl~__________
~
LOAD INPUT
I
CHANNEL ADDRESS INPUT
MUST BE VALID
I
~PARALlElOUTPUTS VALID=--=-!
E.O.C. OUTPUT
II
MSB OUTPUT
----------~I ~I____
BIT 2 OUTPUT
u
BIT 3 OUTPUT
u
BIT 4 OUTPUT
LSB OUTPUT
SERIAL DATA OUTPUT
CHANNEL ADDRESS OUTPUT
===x______________
________----'1 LfTTl
____~x~____________
ARB!TRARY CODE SHOWN 1011 1011
7 PACKAGE DATA AcaUISITION/DISTRIBUTION SYSTEM
DATA BUS
..
o~_--{) (18) Amplifier
r-~--t:'/
Output
MUX 2 Enable (27)
Analog Inputs
[
(1(~
(11)
(12)
(13)
(14)
(15)
(16)
Address
Channel
Inputs
~(24)
~CON=100PF
(A2(2B)g=====~~
-t15VSUpply(+Ved
J.r----~O (25) Ground
+---------<> (23)
~
15V Supply (- Ved
A1 (29)
AO(30)
T/H C o m m a n d ( 1 7 ) Q - - - - - - - - - - - - - - - - - - - - i
9-11
PIN DESIGNATIONS
•
32
16
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
ChannelO
Channell
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channell0
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Mux 1 Output
Mux 1 Enable
Ao Mux Address
Al Mux Address
A2 Mux Address
Mux 2 Enable
Mux 2 Output
Ground
+ 15V Supply (+ VcC!
-15V Supply (- VcC!
-In (Instrumentation Amplifier)
+ In (Instrumentation Amplifier)
Instrumentation Amplifier Output
T/H Amplifier Input
T/H Amplifier Output
17 T/H Command
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION-MN7130 is a complete data
acquisition system front end containing user-configurable
components (multiplexers, instrumentation amplifier and
track-hold amplifier).
In order to preserve maximum flexibility, all inputs and outputs of the subsections are available at the device pins. The
internal 8-channel multiplexers can be connected for 16
single-ended or 8 fully differential input operation and may be
directly addressed via three address lines and two mux
enable lines. The internal instrumentation amplifier offers
high input impedance (250M0I100pF) and 70dS common
mode rejection ratio. The internal track-hold amplifier completes this analog front-end function allowing dynamic input
Signals to be acquired and then held for analog-to-digital
conversion.
MN7130 can be used in conjunction with MN574A /LP-compatible 12-bit AID converters to configure a complete and inexpensive, 16-channel, 12-bit /LP-compatible DAS capable of
28,000 channels/secthroughput rates in a minimum of board
space. Substituting MN5240 for MN574A increases throughput to 60,000 channels/sec.
LAYOUT CONSIDERATIONS-Proper attention to layout and
decoupling is necessary to obtain specified performance
from the MN7130. The unit's ground pin (pin 25) should be tied
to system analog ground as close to the unit as possible,
preferably through a large analog ground plane underneath
the package.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick-up. Care should be taken to
avoid long runs or analog runs close to digital lines.
Power supply connections should be short and direct, and all
power supplies should be decoupled with high-frequency bypass capaCitors to ground. l/LF tantalum capaCitors in parallel with O.Ol/LF ceramic capacitors are the most effective
combination. Single l/LF ceramic capaCitors can be used if
necessary to save board space.
Pin 24 a
l~F
I
I
I
I
+15V
O.Q1~F
Pin 25 O~-+I---I+-- Ground
l~F
Pin 23 a
9-12
T T
O.Q1~F
-
15V
MULTIPLEXER-INSTRUMENTATION AMPLIFIER-The multiplexer section of the MN7130 is addressed with a three or
four bit binary word and can be configured for 8 full differential inputs or 16 single-ended inputs. The use of differential inputs provides high rejection of common mode noise and
elimination of ground return offsets. Differential inputs must
be used when both sides of the input signal are off ground.
Connections and truth tables for both modes of operation are
shown on the following pages.
Approximately l/Lsec access time should be allowed after addressing before the analog outputs of the multiplexer are
used. A particular point to note is the minimum logic "1" for
the multiplexer inputs is + 4.0V. If the multiplexer inputs are
to be driven from standard TIL logic, 1kO pullup resistors to
+ 5V should be used.
The following diagrams show typical connections for both full
differential and single-ended applications along with truth
tables which demonstrate multiplexer address (Ao, A 1, A-;)
and enable (MUXl Enable, MUX2 Enable) line functions.
MN7130 is specified and tested as a system (all elements
serially connected). Typical specifications for the multiplexer
and instrumentation amplifier appear below.
Typical Mux Performance Specifications
Numbers of Channels
Input Voltage Range
Input Impedance
16 Single-Ended
8 Full Differential
±10V
250M0I100pF
Logic Levels: Logic "1" (min.)
Logic "0" (max.)
+4.0V
+0.8V
Logic Currents: Logic "1"
Logic "0"
±lOjtA
Access Time
On Resistance
Cross Talk (1 kll Source, 1kHz, 20vp-p)
±lO~A
500nsec
2kll
-68dB
Typical Instrumentation Amplifier
Performance Specifications
Voltage Range
±10V
Input Impedance
250M!lI100pF
Input Current (max.)
±30nA
As stated earlier, the MN7130 is specified and tested as a system (all elements serially connected). Typical T/H amplifier
specifications are listed below.
T/H Amplifier
Performance Specifications
I Typical
Common Mode Rejection Ratio (min.)
70dB
Voltage Range
Gain
+1VIV
Input Impedance
Gain Error: Initial (+25'C)
Over Temperature
±0.02%
±0.05%
Input Bias Current
±15nA
Logic Levels: Logic "1" (min.)
Logic "0" (max.)
+2.4V
+0.8V
Logic Currents: Logic "1"
Logic "0"
±10p.A
±10p.A
Gain Nonlinearity
±0.002%
Large Signal Bandwidth
250kHz
±20V/p.sec
Output Slew Rate
4p.sec
Settling Time (20V Step to ±0.01%)
Output Voltage Swing (min.)
±10V
Output Current (min.)
±2mA
Output Load Capacitance (max.)
50pF
TRACK-HOLD AMPLIFIER-The track-hold amplifier is in the
hold mode when the T/H command is a logic "1" and in the
sample mode when the T/H command is a logic "0". A total of
10l'sec should be allowed after addressing the multiplexer
before the T/H is commanded to the hold mode to allow for
full scale (20V) changes. Maximum acquisition times for changes
less than full scale are shown on the following page.
In data acquisition applications, the T/H command input can
usually be driven directly from the AID converter Status
(E. D.C.) output.
±10V
10"1l
Gain
+1VIV
Gain Nonlinearity: Initial (+25'C)
Over Temperature
±0.002%
±0.005%
Offset Voltage (Track Mode): Initial (+ 25 'C)
Over Temperature
±2mV
±4mV
Offset Change (Pedestal, Hold Mode)
Over Temperature
±15mV
Droop Rate: Initial (25 'C) (max.)
O'C to + 70'C (max.)
- 55 'C to + 125 'C (max.)
±7p.V/p.sec
± 10p.V/p.sec
±40p.V/"sec
Acquisition Time (20V Step to ± 0.01 %) (max.)
10!,sec
Aperture Time (max.)
400nsec
Feedthrough (Hold Mode) @ 1kHz
±0.01%
Transients Peak Amplitude: Track·ta-Hold
Hold·to·Track
90mV
100mV
MULTIPLEXER CONNECTIONS and ADDRESSING
16 Single Ended Input Channels
Address Inputs
MUX 1
Output
MUX2
Output
(32)
(261
-"
(22)
Analog
Inputs
(27)
Channel
Address
Inputs
W"OI
A, (29)
A2(2B)
A3
(31)
MUX2
MUX 1
Enable
Enable
7404
+'"
(21)
Enable Inputs
On Channel
A2
A1
Ao
MUX1
MUX2
X
X
X
X
X
X
1
0
1
0
ILLEGAL
NONE
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
2
3
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
4
5
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
8
9
10
11
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
12
13
14
15
1
6
7
Logic "1" > +4.0V
Logic "0" < + O.8V
9-13
8 Differenliallnpul Channels
MUX2
~
Output
-Jo
+Jo
(26(
(22)
(21)
Address Inputs
C',"",IO
(1)
(21
(3(
Analog (4)
Inputs (5)
(6(
+4.0V
Logic "0" < +O.8V
Channel 7
Address [AO
Al (29)
Channel
Enable Inputs
MUX2
A2
+ , , 0 - - - - - - - -.....- - - - '
MN7130
Acquisition Time
vs. Output Swing
MN7130
Common Mode Rejection
vs. Frequency
1 11k"
Source
Imbalance
100
Acquisition
Time (Ilsec)
80
---..
~
-------
~
--------
40
20
15
10.0
_
MICRO NETWORKS
324 Clark St., Worcester. MA 01606 (508) 852·5400
9·14
O.1k
1.0k
10k
100k
Common Mode Input Frequency (Hz)
Output Swing (Volts)
OJ]
--
20
1.0
10
""
MN7140
~JJ
_
MICRO NETWORKS
12-Bit, a-CHANNEL
DATA ACQUISITION SYSTEM
DESCRIPTION
FEATURES
MN7140 is a complete 12-bit data acquisition system in an
industry-standard. 40-pin, double-wide dual-in-line package.
This unit contains an 8-channel input multiplexer (with latch and
counter for either random or sequential addressing), a true instrumentation amplifier (G=1, lin =100Mn), a track-hold
amplifier (with internal hold capacitor), a 12-bit successive approximation AID converter (with internal clock and reference).
and all the timing and control logic necessary to operate the
system with a single trigger pulse. The standard MN7140 has 8
single-ended inputs and can easily be expanded to 16 singleended or 8 differential inputs with the addition of a single external multiplexer.
• Complete DAS:
Input Multiplexer
Address Register
Instrumentation AI1}P
Track-Hold Amp
12-Bit AID Converter
Clock, Control Logic
• Industry Standard
40-Pin Double-Wide DIP
• Random or Sequential
Addressing
• ±O.1%FSR Maximum
Overall System Accuracy
• Adjustment-Free: No Gain or
Offset Adjustments Necessary
• Full Mil Operation
-55°C to +125°C
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
Active laser trimming of fully assembled units enables us to produce adjustment-free devices that guarantee performance
equal to or exceeding all other modular and hybrid systems.
Overall system linearity (± 1/2LSB) and absolute accuracy
(±O.1%FSR) are fully specified and guaranteed at all
temperatures. The standard device is fully specified for either
O°C to +70°C or -55 C to +125°C ("H" model) operation. The
MN7140H/B and MN7143H/B are available with Environmental
Stress Screening while MN7140H/B CH and MN7143H/B CH
are screened in accordance with MIL-H-38534.
Contact factory for availability of "CH" devices.
40 PIN DIP
For years, MN7140 was the only DIP-packaged 12-bit DAS to
fully specify and guarantee linearity and overall system accuracy, without adjustment, over its entire operating temperature
range. This feature, coupled with hermetic packaging and
optional MIL-H-38534 screening make it the established choice
for high-resolution military/aerospace and severe-environment
industrial data acquisition applications. Its thin-film hybrid construction and low chip count ensure the highest reliability.
r
I
I
o ",--
Dimensions in inches
(millimeters)
[1lJ
_
MICRO NETWORKS
January 1992
CopyrighlCol1992
Micro Networks
All righls reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
9·15
MN7140 12-Bit a-CHANNEL DATA ACQUISITION SYSTEM
ORDERING INFORMATION
PART NUMBER - - - - - - - - I M N 7 1 4 X H/B CH
I
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Specified Temperature
Storage Temperature
+ 15V Supply (Pin 20)
- 15V Supply (Pin 21)
Logic Supply (Pin 23)
Analog Inputs (Pins 1·4,37·40)
Digital Inputs (Pins 31·36, 11)
- 55'C to + 125'C
O'C to + 70'C (Standard)
- 25'C to + 85'C (" E" Model)
- 55'C to + 125'C ("H" Model)
-65'C to + 150'C
- 0.5 to + 18 Volts
+ 0.5 to - 18 Volts
- 0.5 to + 16 Volts
± 15 Volts
- 0.5 to + Logic Supply
Select MN7140 (± IOV) or MN7143
(0 to + 1 0 V ) . - - - - - - - - - - - I .
Standard Part is specified for O°C to + ?OoC
operation. Add "E" suffix for specified
-25°C to +85°C operation. Add "H" suffix for
specified -55°C to+ 125°C operation. - - - - - '
Add "/B" to "H" devices for
Environmental Stress Screening. - - - - - - - '
Add "CH" to "H/B" devices for 100%
screening according to MIL·H-38534.-------'
Contact factory for availability of "CH" device types.
SPECIFICATIONS (TA = + 25°C, Supply Voltages :t 15V and + 5V, unless otherwise specified)
ANALOG INPUTS
MIN.
Number of Input Channels (Note 1)
Input Voltage Range (Note 2)
Input Impedance
Input Capacitance
TYP.
MAX
Mohm
pF
100
10
Input Bias Current (Note 3): + 25'C
- 55'C to + 125'C
10
CMRR (Note 4)
80
UNITS
Channels
Volts
8
o to + 10V, ± 10V
25
250
nA
nA
dB
DIGITAL INPUTS
Logic Levels: Logic "1"
Mux Enable
Other Inputs (Note 5)
Volts
Volts
4
3.5
Logic "0"
Mux Enable
Other Inputs (Note 5)
0.8
1.5
Volts
Volts
Loading: Logic "1"
Mux Enable
Other Inputs (Note 5)
0.005
0.005
10
1.3
".A
".A
Logic "0"
Mux Enable
Other Inputs (Note 5)
-0.005
-0.005
-10
-1.3
".A
".A
Trigger Pulse Width
Setup Time, Address Mode and
Address Inputs to Trigger (Note 6)
240
nSec
300
nSec
TRANSFER CHARACTERISTICS
Linearity Error (Notes 7, 8):
+25'C
O'C to + 70'C
- 25'C to + 85'C ("E" Model)
- 55'C to + 125'C ("H" Model)
Differential Linearity Error
No Missing Codes
± 1/4
±Y2
±Y2
±Y2
±Y2
±Y2
±1
±1
±1
LSB
LSB
LSB
LSB
LSB
Guaranteed
Absolute Accuracy Error (Notes 9, 10):
+25'C
O'C to + 70'C
- 25'C to + 85'C ("E" Model)
- 55'C to + 125'C ("H" Model)
±0.05
±0.15
±0.15
±0.2
Gain Error (Note 10)
Gain Drift
±0.1
±0.4
±0.4
±0.4
±0.025
±20
%FSR
%FSR
%FSR
%FSR
%
ppm/'C
DYNAMIC CHARACTERISTICS
Acquisition Time (20V Step to ± 0.01 %) (Note 11)
AID Conversion Time
Throughput Rate (Channels/Sec.)
28.5
Full Power Bandwidth (Note 12)
Crosstalk (1KHz, lKO Source Impedance)
Feedthrough (1 KHz, 20Vp·p) (Note 13)
8
20
35
10
25
250
".Sec
".Sec
KHz
KHz
dB
%
-80
:to.Ol
DIGITAL OUTPUTS
Digital Output Coding
Logic Levels (All Outputs): Logic "1" I, = - 10 p.A
1,= -360 p.A
Logic "0" 1,= 10 I"A
1,=360I"A
9-16
Complementary Offset Binary
4
2.4
0.5
0.4
Volts
Volts
Volts
Volts
POWER SUPPLY REQUIREMENTS
Power Supply Range: + 15V Supply
-15V Supply
+ 5V Supply
+ 14.55
-14.55
+ 4.75
+ 15.00
-15.00
+5.00
Volts
Volts
Volts
+ 15.45
-15.45
+ 5.25
%FSR/%Vs
%FSR/%Vs
%FSR/%Vs
± 0.003
± 0.003
±0.001
Power Supply Rejection: + 15V Supply
-15V Supply
+ 5V Supply
Current Drains: + 15V Supply
- 15V Supply
+ 5V Supply
30
- 50
10
50
-75
16
mA
mA
mA
Power Consumption
1250
1955
mW
SPECIFICATION NOTES:
1. The standard MN7140 has 8 single'ended input channels. See
page 6 for· expanded single-ended and differential operation
using additional external multiplexers.
2. Contact factory for other available input voltage ranges.
3. Input bias current specification is for the "on" multiplexer
channel. "Off" channel leakage current is ± 50 nA maximum
at all temperatures.
4. CMRR specification is for full differential operation using an
external multiplexer. See page 6.
5. Other Digital Inputs include: ADDRESS INPUTS A" A" A" and
As, and the ADDRESS MODE INPUT.
6. If using random addressing or if changing from one addressing mode to the other, ADDRESS INPUT or ADDRESS MODE in·
formation must be present a minimum of 300 nSec prior to the
rising edge of TRIGGER.
7. Micro Networks tests and guarantees maximum linearity error
at room temperature and at the high and low extremes of
the specified operating temperature range. See Ordering
Information.
9. FSR stands for Full Scale Range and is equivalent to the peak
to peak voltage of the system's input range. For the MN7140,
FSR = 20 volts, and 1 LSB = 4.88 mV.
10. See sections on Absolute Accuracy and Gain Errors for an explanation of
how Micro Networks tests and specifies these parameters.
the tutorial section of the Micro Networks Product Guide and
Applications Manual for a complete discussion of DAS
specifications.
11. The MN7140's internal timing control logic allows 10 ~Sec for
channel switching, amplifier settling, and signal acquisition.
See Summary of Operation.
12. This spec applies from analog input to the output of the internal S/H amplifier and it applies when the S/H is acquiring and
tracking an analog input signal. It is the frequency at which a
20V-pp input/output sine wave becomes slew rate limited.
13. This spec also applies from the analog input to the output of
the internal S/H amplifier and it applies when the S/H
is holding an analog signal i.e., when the AID converter is
converting.
8. One LSB for a 12 bit system corresponds to 0.024%FSR. See
note 9.
BLOCK DIAGRAM
Trigger (11)
Address
Outputs
Address
Inputs
C
(
A,
A,
A.
A.
15)
(6)
(7)
(8)
A, (35)
A, (34)
A. (33)
A. (32)
(22) Gain Adj.
(17) MS8
(16) 8il2
Address
Latch
and
Counter
(15) Bit 3
(14) 8il 4
(13)
(12)
(29)
(28)
(27)
(26)
(25)
(24)
Address Mode (31)
Analog
Inputs
[
~~ ~ liit
Bit
Bit
Bit
Bit
Bit
I
5
6
7
8
9
8il 10
Bit 11
LS8
Ch 4 (1)
Ch 5 (2)
Ch 6 (3)
Ch 7 (4)
Mux Enable (36)
(30) Status
'------0
<>------'
(9)
o-------~-i
Inslr. Amp - (10)
o---------i
Inslr. Amp+
(19) Offset Adj.
(20) + 15V Supply
(21) - 15V Supply
(23) + 5V Supply
~ (18) Ground
~
+-----<>
~
9-17
ABSOLUTE ACCURACY ERROR
The MN7140 is a complete Data Acquisition System (DAS)
including input multiplexer, instrumentation amplifier,
track/hold amplifier (T/H), A/D converter, and control logic.
Accuracy and linearity are specified for the complete
system from analog input to digital output,eliminating the
need· for ordinarily important DAS component specifications such as instrumentation amp linearity, instrumentation amp gain accuracy, and T/H pedestal error.
Specifying the accuracy of the MN7140 as a system is
similar to specifying the accuracy of an A/D converter. Portions of the MN7140's analog input/digital output transfer
function are sketched below. Notice the quantization effect.
A given digital output code is valid for a "band" or "range"
of analog input voltages that theoretically, is 1 LSB wide.
For the MN7140 (± 10V input range, 12 bit resolution), 1 LSB
equals 4.88 mV. Ideally, any analog input between 4.88 mV
and 9.76 mV should give a digital output of 0111 1111 1110.
If we assign this code to the nominal midpoint of the band
of input voltage for which it is valid, we can say that
the 0111 1111 1110 digital output corresponds to analog inputs of + 7.32 mV ± 2.44 mV which can be written as
+ 7.32 mV ± Y, LSB. The ± Y, LSB is an irreducible quantization uncertainty unavoidable in AID conversion. It is
referred to as Inherent Quantization Error, and its magnitude
can be reduced only by going to higher resolution converters, i.e., ones that have smaller LSB's.
DIGITAL
OUTPUT
0000 0000 0000
0000 0000 0001
0000 0000 0010
0111 1111 1110
Return to the ideal analog input/digital output transfer function at the beginning of this discussion. Notice that the
digital output data is supposed to change from 1111 1111
1111 to 1111 1111 1110 when the input voltage increases
from -10.000V to - 9.9951V. It should change from 1111
1111 1110 back to 111111111111 as the input voltage is
decreased from some more positive voltage to - 9.9951V.
This voltage, - 9.9951V, is the negative full scale LSB transition voltage. It·is the voltage at which the LSB changes from
a "1" to a "0" or vice versa while all other bits remain "1".
The 1000 0000 0000 to 0111 1111 1111 transition (called the
major transition because all the output bits change) ideally
occurs at the zero volt analog input. The positive full scale
LSB transition voltage, the voltage at which the LSB
changes while the other bits remain "0", is ideally
+9.9951V.
For the MN7140, Micro Networks measures the three transition voltages just discussed. We perform these tests at
+ 25°C and at O°C and + 70°C for commercial models and
at - 55 °C and + 125°C for "H" models (see Ordering Information). This testing, coupled with our linearity testing,
allows us to guarantee that at + 25°C, the analog input
voltage at which any given digital output transition occurs
will be within ±0.1%FSR (±20 mV) of its ideal value and
that over the specified operating temperature range (- 55°C
to + 125°C for "H" models), the analog input voltage at
which any given digital output transition occurs will be
within ± 0.4% FSR (± 80 mV) of its ideal value.
These Absolute Accuracy Error specifications are summarized in the two plots below. The ideal transfer function is
represented by the broken line and the absolute accuracy
limits by the solid lines. We guarantee that at + 25°C, the
MN7140's actual transfer function will be better than ± V2
LSB linear and that all the trClnsition voltages will fall within
the boundaries indicated. We also guarantee that at O°C
and + 70°C for commercial models and at - 55 °C and
+ 125°C for "H" models, the actual transfer function will be
better than ± 1 LSB linear, and the transition voltages will
fall within the boundaries indicated.
011111111111
1000 0000 0000
1000 0000 0001
1111 1111 1101
111111111110
DIGITAL
OUTPUT
111111111111
MN7140 INPUT/OUTPUT TRANSFER FUNCTION
0000 0000 0000 to
0000 0000 0001TRANSITION
It is difficult and time consuming to measure the center of a
quantization band (the + 7.32 mV in this example). The only
points along an AID converter's analog input/digital output
transfer function that can quickly and accurately be
detected and measured are the tranSition voltages, the
analog input voltages at which the digital outputs change
from one code to the next. The Abso/ute Accuracy Error of a
voltage input AID converter is the difference between the
actual, unadjusted, analog input voltage at which a given
digital transition occurs and the analog input voltage at
which that transition is ideally supposed to occur. This difference is usually expressed in LSB's or %FSR. Absolute
Accuracy Error includes gain, offset, linearity, and noise errors, and when specified over temperature, encompasses
the individual drifts of these errors. For the MN7140, Micro
Networks tests Absolute Accuracy Error at both endpoints
and the midpoint of the system transfer function.
9-18
g
~
o
T
I
l
I
/
/
/
/
1
111111111111 to
111111111110
TRANSITION
MN7140 ABSOLUTE ACCURACY +2SoC
DIGITAL
OUTPUT
0000 0000 0000 to
000000000001
TRANSITION
"'
""
;;;
;;;
,,;
C;;
,,;
'"'"
~
~
The transition from output code 0000 0000 0000 to code 0000 0000
0001 will ideally occur at an input voltage of + 9.9951V. Subse·
quently, any input voltage greater than + 9.9951 volts will give a
digital output of all "a's". The transition from digital output 1000
0000 0000 to 0111 1111 1111 will ideally occur at an input of zero
volts, and the 111111111110 to 111111111111 transition should
occur at - 9.9951 volts. An input more negative than 9.9951 volts
will give all "l's".
/
/
/
1
/
/
/
ANALOG
INPUT
(DC VOLTS)
I
<--+- -
PIN DESIGNATIONS
+- ...----+--\\--;.r'--+-_'----j,~+----+-----4~
I )
/
//
/
;;;
;;;
C;;
,,;
~
I
/
;;;
""~
'"
~
'"+
+
•
Pin 1
40
20
21
/
// ..
/
/
I"" "" "" '0
111111111110
TRANSITION
MN7140H ABSOLUTE ACCURACY - 55·C, + 125·C
For temperatures intermediate to + 25·C and the extremes
of the specified operating temperature range, maximum Absolute Accuracy Errors can be found through interpolation.
At + 75°C, for example, the maximum Absolute Accuracy
Error of the MN7140H will be ±0.25%FSR.
OFFSET ERROR-We have not specified an Offset Error for
the MN7140. Offset Error is an Absolute Accuracy Error, and
it would be redundant and potentially confusing to specify
Offset Error after giving an Absolute Accuracy Error that ap·
plies over the converter's full input range.
GAIN ERROR-Gain Error is the difference between the
ideal and the measured values of the DAS's Full Scale
Range (minus 2 LSB's); it is a measure of the slope of the
DAS's transfer function. Gain Error is not a type of Absolute
Accuracy Error, but it can be calculated using two Absolute
Accuracy Error measurements. It is equivalent to the Ab·
solute Accuracy Error measured for the 0000 0000 0000 to
000000000001 transition minus that measured for the 1111
11111111 to 111111111110 transition.
DIGITAL OUTPUT CODING
ANALOG INPUT (DC VOLTS)
MN7143
MN7140
0.0000
+ 0.0024
+ 0.0049
+ 10.0000
+ 9.9951
+ 0.0098
+ 0.0049
+ 4.9976
+ 5.0000
+ 5.0024
+ 9.9951
+ 9.9976
+ 10.0000
Channel 4 Input
Channel 5 Input
Channel 6 Input
Channel 7 Input
Address Output (A,)
Address Output (A,)
Address Output (A,)
Address Output (A,)
Mux Output, Amp In (+)
Instr. Amp Input (-)
Trigger Input
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
Ground
Offset Adjust
+ 15V Supply (+ Vcc)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Channel 3 Input
Channel 2 Input
Channell Input
Channel a Input
Mux Enable
Address Input (A,)
Address Input (A,)
Address Input (A,)
Address Input (A,)
Address Mode
Status Output (E.O.C.)
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12 (LSB) _
Logic Supply (+Vdd)
Gain Adjust
-15V Supply (- Vcc)
APPLICATIONS INFORMATION
The digital circuitry used in the MN7140 is CMOS. The stan·
dard precautionary measures for handling CMOS should be
followed. For standard single·ended operation, Pin 10 (the
minus input to the internal instrumentation amplifier)
should be grounded, and Pin 36 (multiplexer enable) should
be tied to a logic "1".
DIGITAL OUTPUT
MSB
LSB
0000 0000 0000
0000 0000 OOO~'
0111 1111 11~~'
0111 1111 1111!!'
0.0000
0.0049
~I!ll!ll!l ~~I!lI!lI!lI!l~I!l'
- 0.0098
- 9.9951
-10.0000
1000 0000 00~1!l'
1111 1111 111~'
111111111111
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1000 0000 000q)'
'Voltages given are the theoretical values for the transitions
indicated. Ideally, with the DAS continuously acquiring and con·
verting data, the output bits indicated as ~ will change from a "1"
to a "0" or vice versa as the input voltage passes through the level
indicated. See the section on Absolute Accuracy Error for an ex·
planation of Output Transition Voltages and a sketch of the
MN7140's transfer function.
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN7140. The unit's GROUND (Pin 18) should be
connected to system analog ground, preferably through a
large ground plane underneath the package. Coupling bet·
ween analog inputs and digital signals should be minimized
to avoid noise pickup. Analog input runs should be well
separated from digital clock lines and other noise sources.
The OFFSET ADJUST pOint (Pin 19) is particularly noise
susceptible. Care should be taken to avoid long analog runs
or runs close to digital lines when utilizing this input.
When external offset adjustment is employed (see page 7),
the 3.3 megohm resistor and trim pot should be located as
close to the package as possible. Whether or not external
gain adjustment is used (see page 7), a 0.01 I'F ceramic
bypass capacitor should be located close to the package
connecting the GAIN ADJUST pOint (Pin 22) to analog
ground.
9-19
I_'
Power supplies should be decoupled with tantalum or electrolytic capacitors located close to the MN7140. For optimum performance and noise rejection, 1 p.F capacitors
paralleled with 0.01 p.F ceramic capacitors should be used
as shown in the diagram below.
Pin 20
C
I
1.F
Pin 23
cO
1 .F
I
I
T I
+5V
0.01 .F
Pin 18 ._..1-_ _ _
-'-_ Ground
Pin 18
+ 15V
0.01.F
o-±t---II--
1 .F
Pin 21
I
T
Ground
T T
0
0.01 .F
-
-
15V
SEQUENTIAL ADDRESSING CONTINUOUS CONVERSIONS-The MN7140 can be made to continuously sequence through channels acquiring and converting data by
applying a logic "1" to the ADDRESS MODE input (Pin 31)
and inverting the STATUS output (Pin 30) and tying it back
to the TRIGGER INPUT (Pin 11). In this mode, the STATUS
OUTPUT going low at the end of a conversion becomes the
rising TRIGGER edge that addresses the next channel and
initiates the next data acquisition and conversion cycle.
After each channel has been converted· and ·the STATUS
has dropped to a "0", the output data will be valid for approximately the next 10 p.Sec while the multiplexer is
switching channels and the TlH is acquiring the new signal.
The falling edge of STATUS may be used to latch output data
into an external receiving register (please read the section
describing the STATUS output). When continuously converting,
an external TRIGGER signal should be provided at power-on
to avoid possible latch-up.
POWER SUPPLY DECOUPLING
SUMMARY OF OPERATION-The rising edge of a TRIGGER
pulse loads the multiplexer (Mux) channel address and initiates a data acquisition and conversion cycle. If sequential
addressing is being used (see below), the next channel will
be accessed. If random addressing is being used, the channel whose address has been applied to the CHANNEL ADDRESS INPUTS will be accessed. The rising edge of the
TRIGGER pulse simultaneously fires an internal one-shot
(10 p.Sec pulse duration) whose output disables the internal
clock. 10 p.Sec later, the falling edge of the one-shot drives
the trackfhold amp (TfH) into the hold mode, gates on the
clock, generates a start convert signal for the 12 bit AID converter, and drives the STATUS OUTPUT to a logic "1". Gating
off the clock during the time the Mux is settling into its new
channel and the T/H is acquiring a new signal reduces noise
errors. When the conversion is complete (approximately 20
p.Sec later), the STATUS output returns to a logic "0" indicating that the conversion is complete, that the digital
output is valid, and that the TfH amplifier has returned to the
tracking mode. The unit is now ready to be triggered for the
acquisition and conversion of the next channel.
CHANNEL ADDRESS OUTPUTS-The MN7140's CHANNEL
ADDRESS OUTPUTS (Pins 5-8) are tied directly to the unit's
internal address counterllatch. They indicate, in 8421 binary,
the multiplexer channel presently being accessed. When using external multiplexers for differential or expanded singleended operation (see below), these outputs can be used to
address the external multiplexers, eliminating the need for
any additional address decoding circuitry. When using sequential addressing, the appropriate CHANNEL ADDRESS
OUTPUTS can be NORed together to generate a frame sync
pulse each time channel 7 (8 channel systems) or channel 15
(16 channel systems) is being addressed. In microprocessorbased systems, the ADDRESS OUTPUTS can be 3-state buffered to add channel read-back capability.
CHANNEL EXPANSION-The MN7140's input capabilities
can be expanded beyond the 8 basic channels with the addition of external analog multiplexers. The diagram below
shows a 16 channel single-ended system using an external
508A type multiplexer. Note that no additional address
ADDRESSING- The MN7140's input channels may be randomly or sequentially addressed. For random addressing,
the ADDRESS MODE input (Pin 31) must be tied to a logiC
"0" and the desired channel address (in 8421 binary) applied
to the CHANNEL ADDRESS INPUTS (Pins 32-35). In this addressing mode, the MN7140's internal address latchfcounter
acts as a 4 bit parallel register. The riSing edge of the TRIGGER pulse latches the new channel address and initiates
the data acquisition and conversion cycle. If the MN7140 is
not being expanded (see below) and only its 8 internal channels are being used, the A. address bit (Pin 32) is unnecessary, and this input can be tied either high or low but
should not be left open.
For sequential addressing, the ADDRESS MODE input (Pin
31) must be tied to a logic "1". In this mode, the internal address latchfcounter acts as a 4 bit binary counter. Each rising edge of the TRIGGER input will increment the channel
address and initiate the data acquisition and conversion cycle. Channel 0000 will be accessed after channel 1111. As
one changes from random to sequential addressing, the
next channel accessed will be one higher than the channel
last randomly addressed. Changing digital data appearing
at the ADDRESS INPUTS will not affect the MN7140 when it
is in the sequential addressing mode.
9-20
A8 A.A:Al
Address
Outputs
A8 A. A2 AI Address
Address
Mode
Inputs
16 SINGLE-ENDED INPUT CHANNELS
decoding circuitry is necessary. The MN7140's internal address latch/counter (see above) is a 4 bit unit that can be
used to either randomly or sequentially address up to 16
channels. For further expansion, additional mux's can be
tied to Pin 9 (the noninverting input to the internal instrumentation amplifier) or cascaded in front of the
MN7140's internal mux. Remember that for single·ended
operation, Pin 10 (the minus input to the internal instrumen·
tation amplifier) has to be grounded.
DIFFERENTIAL INPUT OPERATION-The MN7140 can be
configured for 8 differential input channels with the addition
of a single external multiplexer. A system using a 508A type
multiplexer is shown below. No additional address
decoding circuitry is necessary. Further expansion is possi·
ble with additional mux's tied to Pins 9 and 10 (the inputs to
the·internal instrumentation amplifier).
Ch1
[
OFFSET ADJUSTMENT -Connect the offset paten·
tiometer as shown, and apply an analog input voltage of
- 9.9951V. With the MN7140 performing repeated conver·
sions, adjust the offset potentiometer down until all the
output bits are "1". Then adjust up until the LSB just turns
to a "0".
37
38
39
40
1
2
3
4
Q!12
+ Inputs
OPTIONAL OFFSET AND GAIN ADJUSTMENTS-The
MN7140 will operate as specified without additional ad·
justments. If desired, however, Absolute Accuracy Error can
be reduced to ± 1 LSB by following the trimming procedure
described below. Adjustments should be made following
warmup, and to avoid interaction, the Offset Adjustment
must be made before the Gain Adjustment. Multiturn poten·
tiometers with TCR'S of 100 ppml 'c or less are recom·
mended to minimize drift with temperature. Series resistors
can be ± 20% carbon composition or better. If these ad·
justments are not used, Pins 19 and 22 should be left open.
Do not ground.
Ch 3
Ch 4
Ch5
Ch 6
Ctll
Ch 8
Pin 19
:::==
:::==
:::==
Ch6
:::==
thO
Ch 1
-Inputs
[
Ch 2
Ch
__3
Ch 4
Ch 5
h
Ch 7
4
5
6
7
2
T
508A 8
3.3MO
o>-----....JVN-----::>~
15
10
16
9
36
10
-15V
7
6
5
,
1~~!)
100KO
MN7140
12 MUX
11
!
+ 15V
OFFSET ADJUSTMENT
333435
31
1 111 1
A.A---;A-;
Address
Outputs
Address
Inputs
Address
Mode
8 DIFFERENTIAL INPUT CHANNELS
PIN 36 MULTIPLEXER ENABLE-When Pin 36 has a logic
"0" applied, the MN7140's internal mux is disabled. When
Pin 36 has a logic "1" applied, the internal mux is enabled
and can be accessed through ADDRESS INPUTS A" A" and
A4 (Pins 33-35).
GAIN ADJUSTMENT -Connect the gain potentiometer as
shown, and apply an analog input voltage of + 9.9951V. With
the MN7140 performing repeated conversions, adjust the
gain potentiometer up until all the output bits are "0". Then
adjust down until the LSB just turns to a "1".
!
+ 15V
Pin 22
3.3MO
C>---I--~VN-------:>~
1~~O
100K!)
rO.01 pF
STATUS OUTPUT (E.O.C.)-The STATUS or END OF
CONVERSION (E.O.C.) output (Pin 30) indicates whether the
MN7140 is tracking or converting an input signal. When
STATUS is a logic "0", the MN7140's internal TlH amplifier is
in the tracking mode and digital output data from the
previous conversion is still valid. When the STATUS is a
logic "1", the T/H is in the hold mode, and the internal A/D is
converting. The output data is not valid. The falling edge of
STATUS indicates that the conversion is complete, that the
output data is valid, and that the TlH has returned to the
tracking mode. Output data will be valid and enabled a minimum
of 300 nsec before STATUS returns low.
-15V
GAIN ADJUSTMENT
9·21
TIMING DIAGRAM
AddressMode---------------------------i5.~;rr~!\crctres.~~----------------L---------~R~a~n~d~o~m~A~d~d~r~es~s~in~g~
_______
Sequential Addressing
n~gm~~~~~~~~~~~~~~
Address Input Ao ~"¥~'-%~W
Address Input A1 &1¥""L4&..~'~~
Address Input A2
m'"
~~",*@u~Q 4#*"
Mux Channel :='ChanneI3=>C:
"*
$1
""m%
Channel
4-
$1
X
Channel
7=====
Address Output Ao
Address
Output A,
A,
Address Output
_-_~~_-----,
_____~=============================================~----------------------------
Status
Internal Clock
AID Start
Command
;~;;~~~~;;;~=====~~~~~=====~~~~~~~~;;;~~=~§~~~==
U------U
r ---------------
Note 6
MSB
Bit 3
§&XS§,,§§§~
Bit 8
~,"%\~~'\,%\\i"'i&"§{
Bit 9
~~~1&%'»~~~
TIMING DIAGRAM NOTES:
1. For sequential addressing, set ADDRESS MODE=:"1". For
random addressing, set ADDRESS MODE = "0".
6. All output bits are 3·stated during the AID conversion. They become
valid and enabled a minimum of 300nsec before STATUS returns low.
2. The minimum TRIGGER pulse width is 240 nSec, but the
TRIGGER does not have to be brought back down for the ac·
quisition and conversion cycle to continue.
7. Operation shown is for the digital word 1101 0011 0101 which
corresponds to an analog input of - 6.5137V.
3. In the random addressing mode, ADDRESS INPUT data must
be valid at least 300 nSec prior to TRIGGER.
4. The rising edge of TRIGGER disables the internal clock for
10 ~Sec during signal acquisition.
5. When STATUS = "1" the internal T/H is in the hold mode, and
the AID converter is performing a conversion. When
STATUS = "0", the conversion is complete; output data is
valid; and the T/H has returned to the track mode.
[hJJ
_
B. Conversion time is defined as the time the STATUS output is
high.
9. Once an acquisition and conversion cycle has begun, it can·
not be stopped by applying another TRIGGER pulse.
10. When the system is initially "powered up", it may come on at
any point in the cycle.
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852·5400
9·22
MN7145 Series
I! II
~
_
8-CHANNEL,12-Bit
DATA ACQUISITION SYSTEM
with /LP INTERFACE
MICRO NETWORKS
DESCRIPTION
FEATURES
• Complete, 8-Channel, 12-Bit
DAS with MUX, T/H, ADC, Ref.
and 3-State Output
• 25,000 Channels/sec
Guaranteed Throughput
• Microprocessor Interface
(3-State Output, Address Line,
Read/Convert, etc.)
• Small 28-Pin Side-Brazed DIP
• 18 Models (3 Input Voltage
Ranges)
• Fully Specified O°C to +70°C
(J and K Models) or -55°C to
+125°C (S and T Models)
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
28 PIN DIP
PIN t
\
t g~g;'~;\j --10125!~17~
o 155 (
.93
QJ90 (4.826)
O.22{) (5.588!
l::1-T
I--
The MN7145, MN7146 and MN7147 are complete, singlepackage, 8-channel, 12-bit, data acquisition systems with
internal decoding logic and 3-state output buffers which
greatly facilitate microprocessor control. Packing a lot of
function into a 28-pin, side-brazed, ceramic DIP, MN7145
Series DAS's each contain an 8-channel, overvoltage
protected (±35V) multiplexer; a high-speed (10p.sec), highimpedance (10 10 0), T/H amplifier; a high-speed (25/-tsec), 12-bit
AID with reference and clock; and all the timing and control
logic (3-state buffer, address line, read/convert line)
necessary for p.P control. System throughput rate is
guaranteed at 25,000 channels/sec for full rated accuracy.
These devices are manufactured using contemporary hybrid
assembly techniques, and they illustrate the technology's
ability to combine I.C.'s made with different processing
technologies into a single functional design that takes
advantage of the best aspects of each semiconductor
technology. The overvoltage protected mux is CMOS. The
T/H is high-speed bipolar with an npo hold cap. The A/D
combines high-speed bipolar technology with state-of-the-art
thin-film technology and TTL compatible CMOS. Active laser
trimming of fully assembled devices compensates for
summed accuracy and linearity errors to produce overall
system linearity (±%LSB) and accuracy (±0.05%FSR offset
error) that may not be achievable when assembling a similar
system with individual components. Small size, low power
(1 Watt max), high sampling rate and low cost may make
the MN7145 Series the most economical way possible to
achieve multichannel, 12-bit, data acquisition today.
MN7145 (0 to + 10V input range), MN7146 (±5V) and MN7147
(±10V) are fully specified over both O°C to + 70°C (J and K
models) and -55~C to +125°C (S and T models) temperature
ranges. Assorted linearity grades (± % LSB, ± 1LSB) at room
temperature and over temperature are available as outlined
in the specification table. All devices guarantee "no missing
codes" over temperature (to either the 12-bit or 11-bit level).
0.600 (t5.24)-..J
Dimensions In Inches
(millimeters)
~
February 1988
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
9-23
MN7145 SERIES a·CHANNEL, 12·Bit, DATA ACQUISITION SYSTEMS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
J and K Models
S, SIB, T, TIB Models
Storage Temperature Range
Positive Supply (+ Vcc, Pin 19)
Negative Supply (- Vcc, Pin 7)
Logic Supply (+ Vdd, Pin 6)
Digital Inputs (Pins 3, 4, 8-10)
Analog Inputs: (Pins 11-18)
(Pins 20, 21)
-55·C to + 125·C
O·Cto +70·C
-55·C to + 125·C
-65·Cto + 150·C
oto + 16.5 Volts
o to - 16.5 Volts
oto + 7 Volts
- 0.5 to (+ Vdd + 0.5) Volts
±Vcc ±20V
±Vcc
DESIGN SPECIFICATIONS ALL UNITS (TA
= + 25°C,
± Vee
PART NUMBER - - - - - - - - MN714XX/B CH
I
Select MN7145 (0 to +10V), MN714~6±5V)
or MN7147(±10V) - - - - .
Select suffix J,K,S or T for
desired performance and specified
temperature range. - - - - Add "/B" to "S" or "T" models for
Environmental Stress Screening
Add "CH" to "SIB" or "T/B" models for
100% screening according to
MIL-H-38534. _ _ _ _ _ _ _ _ _ _ _ _....J
=± 15V, + Vdd = + 5V unless otherwise indicated) (Note 1)
ANALOG INPUTS
MIN.
Number of Input Channels
Input 'Impedance (Note 2): On Channel
Off Channels
Input Bias Current (On Channel): + 25·C (Note 2)
Tmin to Tmax (Note 3)
Input Leakage Current (Off Channels, Note 2): + 25·C
Tmin to Tmax (Note 3)
Volts
Volts
Volts
10" 1100
10" 110
Il/pF
Il/pF
±1
±50
+2.4
-0.5
+4.0
0
nA
nA
nA
nA
+5.5
+0.8
+5.5
+0.8
Volts
Volts
Volts
Volts
±10
± 10
p.A
p.A
+0.4
Volts
Volts
±10
!,A
Straight Binary
Offset Binary
+2.4
Leakage (DBO·DBll) in High·Z State
±1
Output Capacitance (Note 2)
POWER SUPPLY REQUIREMENTS
Power Supply Range: ± Vcc Supplies
+ Vdd Supply
±250
±1
±50
DIGITAL OUTPUTS (Status, DBO·DB11)
Output Coding (Note 5): Unipolar Ranges
Bipolar Ranges
UNITS
+ 10
±5
±10
Logic Currents (All Inputs): Logic "1"
Logic "0"
Logic Levels: Logic "1" (I source ,;; 500!'A)
Logic "0" (lsink,;;1.6mA)
MAX.
o to
Input Voltage Ranges: MN7145
MN7146
MN7147
DIGITAL INPUTS
Logic Levels: Ao, RIC: Logic "1"
Logic "0"
MA o·MA 2 (Note 4): Logic "1"
Logic "0"
TYP.
8 Single-Ended
pF
5
±13.5
+4.5
±15
+5
±16.5
+ 5.5
Volts
Volts
Power Supply Rejection (Note 6): + Vcc Supply
- Vcc Supply
+ Vdd Supply
0.002
0.002
0.002
0.005
0.005
0.005
Current Drains: + Vcc Supply
- Vcc Supply
+ Vdd Supply
+18
-26
+10
+25
-35
+20
mA
rnA
mA
Power Consumption
710
1000
mW
DYNAMIC CHARACTERISTICS
Conversion Time (Note 7): 12-Bit Conversion
8-Bit Conversion
20
13
25
17
I'sec
I'sec
Throughput Rate
9-24
25
35
% FSRI% Supply
% FSRI% Supply
%FSRI% Supply
kHz
PERFORMANCE SPECIFICATIONS (Typical at TA
= + 25°C, :!: Vec =:!: 15V, + Vdd =+ 5V unless otherwise indlcated)(Note 8)
MN7145J
MN7146J
MN7147J
MN7145K
MN7146K
MN7147K
MN7145S
MN7146S
MN7147S
MN7145T
MN7146T
MN7147T
Integral Linearity Error:
Initial (+ 25'C) (Maximum)
T min to Tmax (Maximum, Note 3)
±1
±1
±Y2
±Y2
±1
±1
±1f2
±1
LSB
LSB
Resolution for Which No Missing
Codes is Guaranteed:
Initial (+ 25'C)
T mon to T max (Note 3)
11
11
12
12
11
11
12
12
Bits
Bits
Unipolar Offset Error (Notes 9,10):
Initial (+ 25'C) (Maximum)
Drift (Maximum)
±0.05
± 15
±0.05
±10
±0.05
±25
±0.05
±20
% FSR
ppm of FSR/'C
Bipolar Offset Error (Notes 9,11):
Initial (+ 25'C) (Maximum)
Drift (Maximum)
±0.25
±25
±0.1
±20
±0.25
±25
±0.1
±20
% FSR
ppm of FSR/oC
Gain Error (Notes 9,12):
initial (+ 25°C) (Maximum)
Drift (Maximum)
±0.3
±50
±0.3
±25
±0.3
±50
±0.3
±25
ppm/'C
MODEL
UNITS
%
SPECIFICATION NOTES:
1. Detailed timing specifications appear in the Timing sections of this data
sheet. FSR = Full Scale Range. MN7145 (0 to +10V input volt·age range)
and MN71461± 511 input ,oltage range) have a 10V FSR. MN7147(±10V in·
put voltage range) has a 20V FSR.
2. These parameters are listed for reference only and are not tested.
3. J and K models are fully specified for O'C to + 70'C operation. 5, SIB, T
and T/B models are fully specified for - 55°C to -+ 125°C operation. See
ordering information.
4. If the multiplexer inputs are driven from standard TIL logic, lkfl pullup
resistors to + 5V should be used.
5. See table of transition voltages in section labeled Digital Output Coding.
6. Power supply rejection is defined as the change in the analog input
voltage at which the 111111111110 to 111111111111 or 0000 00000000 to
0000 0000 0001 output transitions occur versus a change in power·supply
voltage.
7. Whenever the Status Output (pin 22) is low (logic "0"), the internal TIH is in
the track mode and the AID converter is not converting. When Status is
high (the definition of AID conversion time), the TlH is in the hold mode,
and the AID is performing a conversion.
8. All performance specifications are specified and tested while sampling
and converting at a 25kHz throughput rate.
9. Adjustable to zero with external potentiometer.
10. Unipolar offset error is defined asthedifference between the ideal and the
actual input voltage at which the digital output just changes from 0000
0000 0000 to 0000 0000 0001 when operating the MN7145 on its unipolar
range. The ideal value at which this transition should occur is + Yo LSB.
See Digital Output Coding.
11. Bipolar offset error Is defined as the difference between the ideal and the
actual Input voltage at which the digital output just changes from 0000
00000000 to 0000 00000001 when operating the MN7146 or MN7147 on a
bipolar range. The ideal value at which this transition should occur is
- F.S. + Yo LSB. See Digital Output Coding.
12. Gain error is defined as the error in the slope of the converter transfer function. It is expressed as a percentage and is equivalent to the deviation
(divided by the ideal value) between the actual and the ideal value for the
full input voltage span from the input voltage at which the output changes
from 111111111111 to 111111111110tothe input voltage at which the output changes from 0000 0000 0001 to 0000 0000 0000.
Specifications subject to change without notice as Micro Networks reserves
the right to make improvements and changes in its prod11cts.
CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.
BLOCK DIAGRAM
Control
Lines
Ao (3)
(
RIC (4)
I
1
TIMING and
CONTROL LOGIC
Ch 1 (11)
-
I
3
12) MSBIBit 9 (OBt1l0B3)
S
Ch 2 (12)
Ch 3 (13)
Analog
Inputs
Ch 4 (14)
8 CHANNEL
Ch 5 (18)
MULTIPLEXER
ChS (17)
~
AMPLIFIER
[.....---1
12·BIT
AID
CONVERTER
Ch 8(15)
Mux
( MAo (10)
Address
MAl (9)
Inputs
MA2 (8)
II
-
II
(28) Bit 3/Bit
I
11 (OB9/0Bl)
I
(27) Bit 4/LSB (OB8;OBO)
(26) Bit 5 (OB7)
B
T/H
COMMAND
Ch 7 (IS)
(1) Bit 2/Bit 10 (OB10/0B2)
T
A
T
E
U
F
F
E
R
(25) Bit 6 (OB6)
(24) Bit 7 (OB5)
(23) Bit 8 (OB4)
(20) Offset Adjust
(21) Gain Adjust
:Ii"i :.-~::'"::::'::::
(221 Status (E.O.C.)
O.Olp.F
(5)
Ground
TO.01 p.F
0 (S) + 5V Supply (+ Vdd)
( +
9-25
ORDERING INFORMATION
Part Number
Input
Voltage Range
o to
o to
MN7145J
MN7145K
MN7145S
MN7145S/B (2)
MN7145T
MN7145T1B (2)
Oto
Oto
Oto
o to
+10V
+10V
+10V
+10V
+10V
+10V
Integral linearity (1)
Temp.
+ 25°C
Specified
Temp. Range
No Missing
Codes
Over Temp.
Guaranteed
Throughput Rate
(ChannelS/sec)
Package
O·C to + 70·C
O·C to + 70·C
-55·Cto + 125·C
- 55·C to + 125·C
- 55·C to + 125·C
- 55·C to + 125·C
±1
±V2
±1
±1
±Y2
±Y2
±1
±V2
±1
±1
±1
±1
11
12
11
11
12
12
Bits
Bits
Bits
Bits
Bits
Bits
25,000
25,000
25,000
25,000
25,000
25,000
28-Pin
28-Pin
28-Pin
28-Pin
28-Pin
28-Pin
DIP
DIP
DIP
DIP
DIP
DIP
MN7146J
MN7146K
MN7146S
MN7146S/B (2)
MN7146T
MN7146T/B (2)
±5V
±5V
±5V
±5V
±5V
±5V
O·C to + 70·C
O·C to + 70·C
- 55·C to +·125·C
- 55·C to + 125·C
-55·Cto + 125·C
- 55·C to + 125·C
±1
±Y2
±1
±1
±1f2
±1f2
±1
±Y2
±1
±1
±1
±1
11
12
11
11
12
12
Bits
Bits
Bits
Bits
Bits
Bits
25,000
25,000
25,000
25,000
25,000
25,000
28-Pin
28-Pin
28·Pin
28·Pin
28-Pin
28·Pin
DIP
DIP
DIP
DIP
DIP
DIP
MN7147J
MN7147K
MN7147S
MN7147S/B (2)
MN7147T
MN7147T/B (2)
±10V
±10V
±10V
±10V
±10V
±10V
O·C to +70·C
O·C to +70·C
- 55·C to + 125·C
-55·C to + 125·C
- 55·C to + 125·C
- 55·C to + 125·C
±1
±1
±V2
±1
±1
±1
±1
11
12
11
11
12
12
Bits
Bits
Bits
Bits
Bits
Bits
25,000
25,000
25,000
25,000
25,000
25,000
28-Pin
28·Pin
28·Pin
28-Pin
28-Pin
28·Pin
DIP
DIP
DIP
DIP
DIP
DIP
±Y2
±1
±1
±%
±V2
1. Maximum error expressed in LS8's for 12 bits.
2. Includes 100% screening to MIL·STD-883.
PIN DESIGNATIONS
•
28
14
15
Pin 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bit 21Bit 10 (DB10IOB2)
MSB/Bit 9 (DBll/DB3)
Address Line (AoL
Read/Convert (RIC)
Ground
+ 5V Supply (+ Vdd)
- 15V Supply (- Vecl
Mux Address A2 (MAv
Mux Address Al (MAl)
Mux Address Ao(MAol
Channell Input
Channel 2 Input
Channel 3 Input
Channel 4 Input
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Bit 3/Bit 11 (DB9/DB1)
Bit 4/LSB (DB8/DBO)
Bit 5 (DB7)
Bit 6 (DB6)
Bit 7 (DB5)
Bit 8 (DB4)
Status (E.O.C.)
Gain Adjust
Offset Adjust
+ 15V Supply (+ Vecl
Channel 5 Input
Channel 6 Input
Channel 7 Input
Channel 8 Input
APPLICATIONS INFORMATION
DESCRIPTION OF OPERATION - MN7145 Series devices
are a·channel, 12·bit, data acquisition systems with inter·
nal a·channel multiplexer, track·hold (T/H) amplifier, 12-bit
analog·to·digital (AID) converter, and microprocessor inter·
face logic (3·state buffer, address line, readlconvert line). A
minimal amount of Signals need to be supplied externally to
these devices in order to achieve true multichannel data ac·
quisition. High input impedance and low input bias currents
allow analog signal sources to be connected directly to the
multiplexer inputs. Multiplexer channels are randomly
selected via three mux address lines (MAo, MAl, MA2l. The T/H
is controlled directly by the AID and requires no external commands. The address (Ao) and readlconvert (RIC) lines are used
in assorted combinations to: initiate (write) 12-bit conver·
sions, initiate a·bit conversions, read back MSB data and read
back LSB data. In normal operation, a mux address is
selected (000 = channel 1, 111 = channel a), and time must be
allowed for the mux to switch and settle and for the T/H to ac·
quire and track the new analog input signal. Then the AID con·
version is initiated by dropping the RIC line. Once a conver·
sion has been initiated, the device's Status output (pin 22)
9-26
rises to a logic "1" signaling that a conversion is in progress.
This action drives the T/H into the hold mode instantaneously
"freezing" the appropriate analog input and holding it constant while the AID conversion proceeds. When the conversion is complete, Status drops back to a logic "0"; the T/H is
driven back into the track mode; and output data is held in a
3-state buffer ready to be read. At this pOint, output data Is
available in two a·bit bytes (multiplexed on a single set of output lines) and can be enabled by bringing RIC high and toggl·
ing Ao(Ao= "0" enables MSBdata byte; Ao = "1" enables LSB
data byte). If RIC is brought high during a conversion, output
data is automatically enabled when the conversion is complete. The output data lines return to the high·impedance
state when RIC is brought low initiating a new conversion.
The multiplexer address can be changed during or after a con·
version. In order to achieve maximum device performance,
the multiplexer address may be changed 1JLsec after in·
itiating a conversion. If the multiplexer is updated in this
fashion, and a new channel is selected while a conversion is
in process, the T/H will immediately start to acquire and track
the new analog input signal when the conversion is complete.
This allows the microprocessor to read output data while the
T/H is acquiring the next analog input signal. The diagram
below illustrates the relationships of the timing signals
previously discussed. For more detailed timing information,
see the timing section of this data sheet.
TIMING DIAGRAM
MUX Address
=x
X
1\
Ao
/
Status
\
Converting
(
)
MSB Byte
)
LSB Byte
T/H Mode
<
Track
~
\
Hold
LAYOUT CONSIDERATIONS AND GROUNDING-Proper at·
tention to layout and decoupling is necessary to obtain
specified accuracy from MN7145 Series devices. It is criti·
cally important that the devices' power supplies be filtered,
well-regulated and free from high-frequency noise. Use of
noisy supplies may cause unstable output codes to be
generated. SWitching power supplies are not recommended
for circuits attempting to achieve 12-bit accuracy unless
great care is used in filtering any switching spikes present in
the output.
Decoupling capaCitors should be used on all power-supply
pins; the supply decoupling capacitors should be connected
directly from Vdd (pin 6), + Vcc (pin 19) and - Vcc (pin 7) to
Ground (pin 5). Suitable decoupling capacitors are 1JtF tantalum types in parallel with 0.01JtF ceramic discs. See
diagram below.
POWER SUPPLY DECOUPLING
Pin 6 0
U
/
U
RIC
I
'"F T
Track
/
Hold
ferred. If external offset and gain adjust potentiometers are
used, the pots and associated series resistors should be
located as close to the device as possible. If external adjustment potentiometers are not used, Offset Adjust (pin 20) and
Gain Adjust (pin 21) should be left open. Do not ground.
Ground (pin 5) should be connected to system analog ground
as close to the unit as possible, preferably through a large
analog ground plane beneath the package.
CONTROL FUNCTIONS-Operating MN7145 Series devices
under microprocessor control is most easily understood by
examining the control-line funtions in a truth table. Table 1
below is a summary of the control-line functions. Table 2 is
the control-line truth table.
Table 1: MN7145 Series Control Line Functions
Pin
Designations
Definition
Function
MA o-MA 2
(Pins 8-10)
MUXAddress
In
Selects MUX channel to be held
and converted.
RIC
(Pin 4)
ReadlConvert
("1"= Read)
("0" = Convert)
RIC 1-0 edge is used to initiate
8 or 12-bit conversions.
RIC = "1" enables output data
during a read cycle.
AD
(Pin 3)
Byte Address
Short Cycle
Pin 5 0
Coupling between analog inputs and digital signals should
be minimized to avoid noise pickup. Analog input runs should
be well separated from digital clock lines and other noise
sources. The use of wire-wrap circuit construction is not
recommended. Careful printed-circuit construction is pre-
)
In the start-convert mode, AD
selects 8-bit (Ao= "1") or 12-bit
(Ao= "0") conversion mode.
When reading output data, AD
selects the output data format.
Ao = "0" enables high and middle
bits. AD = "1" enables low bits
and trailing "O's".
9-27
Multiplexer input channels on MN7145 Series devices are
randomly accessed via Address lines (MAo, MA" MA~. The
multiplexer address may be changed after a conversion cycle
is complete. However, if desired, the multiplexer address may
be changed during a conversion cycle. If doing so, caution
must be used to ensure that the address is not updated within
1/Lsec of having initiated the conversion.
The ReadlConvert input (RIC, pin 4) is used in combination
with the Byte AddresslShort Cycle input (A o, pin 3) to initiate
either 8 or 12-bit conversion cycles and to read back output
data stored in the AID's 3-state output buffer. Conversion
cycles are initiated by bringinjj RIC low. Read cycles are initio
ated by bringing RIC high. RIC may remain low during a conversion or it may be brought back high. If it is returned high, it
must be done so within 1.5 /Lsec after the conversion begins. If
RIC is left low during a conversion, it should not be brought
high until after the status line has fallen indicating that the
conversion is complete.
Output data is only enabled when Status = "0" and RIC = "1 ".
However, if RIC has been brought high during the conversion,
output data will automatically be enabled 300nsec (mini·
mum) prior to the fall of Status. If RIC is left low during a con·
version, the output lines will remain in the high-impedance
state when Status returns low. RIC must then be brought high
to read output data.
The Byte AddresslShort Cycle input (A o, pin 3) is used in combination with RIC when initiating conversions and reading
output data. When initiating a conversion, the signal applied
to Ao determines whether a 12-bit (Ao = "0") or an 8-bit conversion is initiated (Ao= "1"). As discussed earlier, conversion
cycles are initiated by the falling edge of RIC. When reading
digital output data from MN7145 Series devices, the signal
applied to Ao determines which 8-bit data byte is multiplexed
to the eight digital output lines. When Ao ="0", the MSB byte
(MSB through bit 8) is enabled. When Ao = "1 ", the LSB byte
(bit 9 through LSB) is enabled.
Table 2: MN7145 Series Truth Table
RIC
Control Lines
Ao MA2 MA, MAo
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
1
0
1-0
0
X
1-0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
0
X
X
X
X
1
1
1
0
0
1
0
1
0
1
X
X
1
Device Operation
Select MUX Channell
Seiect MUX Channel 2
Select MUX Channel 3
Select MUX Channel 4
Select MUX Channel 5
Select MUX Channel 6
Select MUX Channel 7
Select MUX Channel 8
Initiate 12-8it Conversion on
Selected Channel
Initiate 8-8it Conversion on
Selected Channel
Enable 8 MS8's (high and middle
bits)
Enable 4 LS8's (low bits) and
4 trailing "O's"
Output Data Disabled (highimpedance state)
TABLE " TABLE 2 NOTES:
1. "I" indicates TTL logic high (2.4V minimum).
2. "0" indicates TTL logic low (0.8V maximum).
3. X indicates "don't care".
4.
indicates logic transition (falling edge).
5. Output data format is as follows:
'-0
MSB
XXXX
XXXX
XXXX
High
Bits
Middle
Bits
Low
Bits
8 MSB's
9-28
4 LSB's
LSB
TIMING - MUX ADDRESSING-MN7145 Series devices' input multiplexer is randomly addressed by applying the
desired channel address (000 = channel 1, 111 = channel 8)
to the address lines (MAo, MA" MA~. Once the desired channel is selected, 10/Lsec must be allowed for TIH acquisition
time (tACel prior to initiating a conversion. The multiplexer
address may be updated as early as 1/Lsec (t MUXH) after the
conversion cycle has begun if this is necessary to meet
system timing requirements. This address hold time (tMuXH)
ensures that the T/H amplifier has fully switched into the
hold mode prior to being presented with the signal on the
next channel.
TIMING - INITIATING CONVERSIONS-As stated earlier,
the falling edge of RIC in combination with Ao initiates
either 8-bit conversion cycles (Ao= "1") or 12-bit conversion
cycles (Ao = "0"). If the multiplexer address has been changed prior to initiating a conversion, a minimum of 10/Lsec
must be allowed for T/H acquisition time. As stated earlier,
the multiplexer address may be changed during an ongoing
conversion. In this case, the T/H will be commanded back into the track mode and will start acquiring the new channel's
signal as soon as the ongoing conversion is complete.
Timing for a typical 12-bit conversion cycle is shown below.
In this example, the multiplexer is addressed; 10/Lsec T/H acquisition time is allowed; and Ao is set to a logic "0" all prior
to initiating the 12-bit conversion cycle. Ao must remain
valid for 50nsec while RIC is low to ensure that a 12-bit conversion cycle is properly initiated (tHAA = 50nsec min.).
Status output rises to a logic "1" 200nsec after RIC is
brought low (tos = 200nsec max.) commanding the T/H
amplifier into the hold mode and signaling that a conversion
cycle is in progress. While Status is high, the output buffers
return to the high-impedance state and output data cannot
be read. The multiplexer address is updated after a
minimum address hold time of 1/Lsec (tMuXH = 1/Lsec min.). In
this example, RIC is returned high during the conversion cycle so that output data will be automatically enabled upon
completion of the cycle. Once a conversion has started, additional RIC falling edges will be ignored. However, if Ao
changes state after a conversion begins, additional RIC failing edges will latch the new state of A o, possibly causing a
wrong cycle length (8 vS. 12 bits) for that conversion. Not
shown in the example below, RIC may remain low during the
conversion in which case the output data will remain in the
high-impedance state when Status returns low at the end of
the conversion. Output data can then be enabled by bringing RIC high and asserting Ao as desired.
TIMING - RETRIEVING DATA-When the conversion cycle is
complete and Status output is low, the combination of signals applied to RIC and Aoallows output data bytes to be read
(A = "0" MSB byte, Ao = "1" LSB byte). In the example below,
R/~ is returned high during the conversion, and AD is set so
that the MSB byte is automatically enabled 300nsec before
the end of the conversion cycle. After the MSB byte has been
accessed by the system, the LSB byte is multiplexed to the
data output lines by bringing AD high. Break-before-make action ensures that MSB and LSB data bytes will not be enabled
at the same time. Data access time is 150nSec from the
change of Ao (tA2 = 150nsec max.). If one deSires, RIC may remain low during the conversion, in which case, output data
will not be enabled until Status is low and RIC is brought high.
In this case, data access from RIC = "1" is similarly 150nsec.
TIMING DIAGRAM
MUX
Address
RIC
Status
-----_ _.J
2YOb----...J
ADOR SEL "" Cs (CHIP SELECT)
~
I/O("M"'E'Mj
___________________________
~
~-------------------------------------~
AD
'A,
we
DIGITAL OUTPUT CODING
Analog Input Voltage (Volts)
MN7145
MN7146
MN7147
Oto +10V
+ 10.0000
+9.9963
+5.0012
+4.9988
+4.9963
+0.0012
0.0000
±5V
+5.0000
+4.9963
+0.0012
-0.0012
-0.0037
-4.9988
-5.0000
+ 10.0000
+9.9927
+0.0024
-0.0024
-0.0073
-9.9976
-10.0000
±10V
Digital Output
MSB
LSB
1111 11111111
1111 1111 11111'
1000 0000 OOO~'
IIIIII~ ~~II f1~III1'
01111111111~'
0000 0000 00011'
0000 0000 0000
DIGITAL OUTPUT CODING NOTES:
1. For unipolar input range. output coding is straight binary.
2. For bipolar input ranges, output coding is offset binary.
3. For 0 to +10V or ±5V input ranges,lLSB for 12 bits=2.44mV.1LSB for
11 bits = 4.88mV.
4. For ± 10V input range, lLSBfor12 bits=4.88mV.1LSB for 11 bits = 9.77mV.
'Voltages given are the theoretical values for the transitions indicated. Ideally,
with the converter continuously converting, the output bits indicated as_Will
change from "I" to "0" or vice versa as the input voltage passes through the
level indicated.
9-30
EXAMPLE: For an MN7147 operating on its ± 10V input range, the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will ideally
occur at an input voltage of - 9.9976 volts. Subsequently, any input voltage
more negative than - 9.9976 volts will give a digital output of all "0'5". The
transition from digital output 10000000 0000 to 011111111111 will ideally occur
at an input of ·-0.0024volts,andthell1111111111 toll1111111110transition
will occur at + 9.9927 volts. An input more positive than + 9.9927 volts will give
all "1'5".
MN71S0-8
MN71S0-16
8 and 16-CHANNEL
DIP-PACKAGED,12-Bit
DATA ACQUISITION SYSTEMS
...; MICRO NETWORKS
DESCRIPTION
FEATURES
MN7150-8 and MN7150-16 are complete, single-package, 12-bit
data acquisition systems. Built with contemporary hybrid construction techniques, each system contains: an overvoltage protected (±35V) input multiplexer; a multiplexer channel-address
latch/counter; a high-impedance (10 8 0) instrumentation amplifier
that can have its gain set from 1 to 1000; a high-speed (10ltsec
max acquisition time) track-hold amplifier with hold capacitor; a
high-speed (10ltsec max conversion time) 12-bit ND converter
with 3-state output buffer; a 10 Volt buffered reference; and all
timing and control logiC necessary to operate the system with a
single strobe command. The MN7150-8 offers 8 differential input
channels; while the MN7150-16 offers 16 single-ended input
channels. Both devices guarantee minimum throughput rates of
50,000 channels/sec.
• Complete DAS:
Multiplexer
Address Counter
Instrumentation Amp
Track-Hold Amp
12-Bit AID Converter
3-State Output Buffer
Timing and Control Logic
• 8 Differential or 16
Single-ended Input Channels
• Instrumentation Amplifier
Gains from 1 to 1000
• Random or Sequential
Addressing
• 50,000 Channels/sec
Guaranteed Throughput
• Small 62-Pin Package
• Full Mil Operation
-55°C to +125°C
MIL-H-38534 Optional
The gain of MN7150's internal instrumentation amplifier is set
anywhere from 1 to 1000 with a single external resistor making
the full scale input range of the system variable from ± 10V to
±10mV. This resistor, ±15Vand +5V supplies with bypass
caps, and user-optional gain and offset adjust potentiometers
are all that is required to configure a fully functional, 12-bit,
50kHz data acquisition system.
62 PIN PACKAGE
,--------':-,\ T -;1
PN
-irO.02010i11
i
i
I
2275(5779)
~I
0.040110211
2000150.801
2325"15906)
MN7150 offers outstanding flexibility. The 12 bits of digital output
data can be accessed in any combination of 3 four-bit bytes and
a 4-bit mux-address register permits input-channel addresses to
be read back if desired. Track-hold acquisition time and droop
rate can be varied by adding an external resistor or capacitor.
Expansion to 32 single-ended or 16 differential input channels is
accomplished with 2 additional IC's.
MN7150 is packaged in a unique, 62-pin, hermetically sealed,
ceramic package that occupies approximately 3.2 sq. in ..
Devices are fully specified for O°C to +70°C, -25°C to +85°C
(MN7150E), or -55°C to + 125°C (MN7150H) operation, and for
military/aerospace applications, 100% screening to MILH-38534 is optional.
0.018(0.46)
,-.,00-,,-."",
38O(305li-----1
_ _ 1_5.
1420(36.0n
.u;
""
I;nn~~n~~i~::i
: --I
1-0.10012.54)
--l
1__ 0.10012.54)
r-------l100(27~)---l
Dimensions in Inches
(millimeters)
~
_
MICRO NETWORKS
January 1992
Copyrigh1 ' 1992
Micro Networks
All rights reserved
324 Clark St.. Worcester. MA 01606 (508) 852-5400
9-31
MN7150 8 and 16·CHANNEL DIP·PACKAGED, 12·Bit DATA ACQUISITION SYSTEMS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Specified Temperature Range:
MN7150
MN7150E
MN7150H. MN7150H/B
Storage Temperature Range
+ 15V Supply (+ Vcc. Pin 43)
- 15V Supply (- Vcc. Pin 44)
+ 5V Supply (+ Vdd. Pin 18)
Analog Inputs (Pins 1-4.51-62. Note 1)
Digital Inputs
- 55·C to + 125·C
PART NUMBER - - - - - - - - MN7150-16H/B CH
O·C to + 70·C
-25·C to +85·C
-55·C to + 125·C
- 65·C to + 150·C
- 0.5 to + 18 Volts
+ 0.5 to - 18 Volts
- 0.5 to + 7 Volts
:1:35 Volts
o to + 7 Volts
Select MN7150-8 or MN7150-16 model------II
Standard Part is specified for OOC to + 70°C
operation.
Add "E" suffix for specified -25°C to +85°C
operation.
Add "H" suffix for specified -55°C to + 125°C
operation.----------------I
Add "/B" to "H" devices for
Environmental Stress Screening. - - - - - - - - '
Add "CH" to "H/B" devices for
100% screening according to MIL-H-38534.-----.J
SPECIFICATIONS (TA = + 25°C, Supply Voltages
=
:I: 15V and + 5V unless otherwise specified)
ANALOG INPUTS
MIN_
Input Voltage Ranges (Note 2): Unipolar
Bipolar
Common Mode Voltage Range
CMRR: G = 1 (10kHz)
G = 1000 (60Hz)
TYP_
MAX_
UNITS
8 Differential
16 Single-Ended
Number of Input Channels: MN7150-8
MN7150-16
o to +10
-10 to + 10
Volts
Volts
72
100
Volts
dB
dB
100
10
50
100
Mil
pF
pF
pF
±10
Input Resistance
Input Capacitance: Off Channels
On Channel: MN7150-8
MN7150-16
Input Bias Current: Initial (+ 25·q
Drift (Note 3)
± 100
Doubles Every 10·C
±2oo
pA
Input Offset Current: Initial (+ 25°q
Drift (Note 3)
± 25
Doubles Every 10·C
±5O
pA
±7
20.+ 10G
±12
Input Offset Voltage (Note 4): Initial (+ 25°q
Drift (Note 3)
Voltage Noise (RTI. Note 5): G = 1
G = 100.0
mV
~V/oC
~V(RMS)
~V(RMS)
150
1.6
DIGITAL INPUTS
Logic Levels: Mux Enable (Pin 5): Logic "1"
Logic "0"
Other Inputs (Note 6): Logic "1"
Logic "0."
+4
+0.8
+2
+0.8
Loading: Mux Enable (Pin 5. Note 19)
Load Input (Pin 19, Note 14)
Other Inputs (Pins 8,13-16,20.,21,26, 31; Note 14)
lkll Pullup to + 5V
2
1
Volts
Volts
Volts
Volts
LS TTL Loads
LS TTL Load
TRANSFER CHARACTERISTICS (Notes 7. 8)
Integral Linearity Error: Initial (+ 25°C)
Max Over Temperature (Note 3)
± 1/4
±%
+%
+1
Differential Linearity Error: Initial (+ 25°q
Drift (Note 3)
±112
±2
12-Bit No Missing Codes
LSB
LSB
LSB
ppm of FSR'oC
Guaranteed Over Temperature
Unipolar Offset Error (Notes 9, 10.): Initial (+ 25°q
Drift (Note 3)
±0.1
+20
±01
±35
%FSR
ppm of FSR/oC
Bipolar Zero Error (Notes 9, 11): Initial (+ 25 ·C)
Drift (Note 3)
+15
±oos
±2S
Gain Error (Notes 9, 12): Initial (+ 25°q
Drift (Note 3)
±0.1
+10.
±D.2
+30
%
ppm/oC
+0.4
Volts
Volts
±D.D5
%FSR
ppm of FSR/oC
DIGITAL OUTPUTS (Note 13)
Logic Levels: Logic "1"
Logic "0."
Fanout (Note 14)
Logic Coding (Note 15): Unipolar Ranges
Bipolar Ranges
9-32
+2.4
5
SB
OB
TTL Loads
DYNAMIC CHARACTERISTICS
TYP.
MAX.
UNITS
T/H Acquisition Time (Note 16)
9
10
~sec
AID Conversion Time
9
10
~sec
MIN.
Throughput Rate (Continuous Convert Mode)
50
Strobe Command Pulse Width
40
55
kHz
nsec
T/H Aperture Jitter
nsec
1
1
T/H Output Droop Rate
Feedthrough (@lkHz, Note 17)
:!:0.005
Mux Crosstalk Attenuation (@lkHz)
~V/!,sec
:!:0.01
%
74
Setup Time Digital Inputs (Note 18) to Strobe
Hold Time Digital Inputs (Note 18) from Strobe
dB
nsec
50
50
nsec
:!: 15.5
+5.25
Volts
Volts
POWER SUPPLIES
Power Supply Range: :!: 15V Supplies
+5V Supply
:!: 14.5
+4.75
Power Supply Rejection: + 15V Supply
-15V Supply
+ 5V Supply
:!: 15
+5
%FSR/%Supply
%FSR/% Supply
%FSR/% Supply
:!:0.003
:!:0.003
:!:0.001
Current Drains: + 15V Supply
-15V Supply
+ 5V Supply
42
-42
125
60
-55
135
mA
mA
mA
Power Consumption
1885
2400
mW
SPECIFICATION NOTES
1. The MN7150's input multiplexer can withstand continuous voltages up
to 20 volts greater than either supply and instantaneous transients up to
several hundred volts. In a power-off condition, analog input Yoltage
should not exceed ± 20 volts.
2. The gain of the MN7150's internal instrumentation amplifier;s set from
1 to 1000 with a single external resistor between pins 47 and 48. listed
input ranges (0 to + 10V, ± 10V) are for the MN7150's AID converter. If
amplifier gain is greater than 1, the system input range will equal a to
+ 10V or ± 10V divided by G.
3. listed specification applies over specified temperature range as
selected by part number suffix.
4. This specification applies only to Ihe front end of the MN7150 and is de·
fined as the voltage seen al the output of the TfH amplifier with the TfH
in the track mode, with the mux inputs grounded and with the instrumentation amplifier G = 1.
5. Measured at the output of the TfH amplifier.
6. Includes Strobe (pin 8), Mux Address inputs (pins 13·16), Load (pin 19),
Clear (pin 20), and Enables (pins 21, 26, 31).
7. Transfer specifications refer to the entire system from mux input to AID
converter output with instrumentation amplifier G = 1.
8. FSR = Full Scale Range. In Ihe unipolar mode, FSR = 10 volts. In the
bipolar mode, FSR=20 volts. For a 12·bit system, 1 LSB=0.024%FSR.
9. Initial offset and gain errors are adjustable to zero with optional external potentiometers.
10. Unipolar Offset error is defined as the difference between the actual and
11. Bipolar zero error is defined as the difference between the actual and
the ideal input voltage at which the 0111 1111 1111 to 1000 0000 0000
transition occurs when operating on a bipolar input range.
12. Gain error is defined as the error in the slope of the converter transfer
function. It is expressed as a percentage and is equivalent to the deviation (divided by the ideal value) between the actual and the ideal value
for the full input voltage span from the input vo:ltage at which the Qut·
put changes from 111! 1111 1111 to 1111 1111 1110 to the input voltage
at which the output changes from 0000 0000 0001 to 0000 0000 0000.
13. Includes Parallel Data, Mux Address and Status (E.O.C.) outputs.
14. One LS TTL load is defined as sinking 20.A with a logic "1" applied and
sourcing 0.4mA with a logic "a .. applied. One TTL load is defined as
sinking 40.A with a logic "1" applied and sourcing 1.6mA with a logic
"0" applied.
15. SB=Straighl Binary. OB=Offset Binary. See Outpul Coding lable for
delails.
16. Includes mux switching and settling time, instrumentation amp settling
time and T/H amp acquisition time. Specified for a 20V step settling to
± 0.01 % FSR.
17. Measured at the output of the T/H with the T/H in the hold mode.
18. Includes Mux Address. Mux Enable, Clear and Load inputs.
19. The MN7150's Mux Enable input (pin 5) goes directly to the enable input
of a 506A type CMOS multiplexer and has a lkll pullup resistor to + SV.
The enable input of the multiplexer itself draws ± 10JLA max.
the ideal input vollage at which the 0000 0000 0000 to 0000 0000 0001
transition occurs when operating on a unipolar input range.
PIN DESIGNATIONS
53 52
Bottom
View
21 22 - - - - - 1__ 31 32
Dot on top of package references pin 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Ch3( +)/Ch3
Ch2(+)/Ch':>
Chl(+)/Chl
ChO(+)/ChO
Mux Enable
R Delay
Status (E.O.C.)
Strobe
A,
A,
A,
~
~
Mux Address
Outputs
A.
Mux Address
A,
A,
Inputs
A,
Digital Ground
+5V Supply
Load
Clear
Enable (Bits 9·12)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Bit 12 (LSB)
Bit 11
Bit 10
Bit 9
Enable (Bits 5·8)
Bit 8
Bit 7
Bit 6
Bit 5
Enable (Bits 1·4)
Bit 4
Bit 3
Bit 2
Bit 1 (MSB)
Gain Adjust
Offset Adjust
Bipolar Input
Track·Hold Output
+ 10V Reference Out
Analog Signal Ground
Analog Power Ground
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
56
59
60
61
62
+ 15V Supply
-15V Supply
External Hold Cap
External Hold Cap
Gain Setting Resistor
Gain Setting Resistor
Instru. Amp (+) Input
Instru. Amp (-) Input
Ch7 (- )/Ch15
Ch6 (- )/Ch14
Ch5 (- )/Ch13
Ch4 (- )/Ch12
Ch3 (- )/Chll
Ch2 (- )/Chl0
Chl (-)/Ch9
ChO (- )/Ch8
Ch7 (+)fCh7
Ch6 (+)/Ch6
Ch5 (+)/Ch5
Ch4 (+)/Ch4
Pins 14 and 51-62 are defined for MN7150-8fMN71S0·16.
9·33
BLOCK DIAGRAM
Amp
Gain
Input
Setting
Resistor
+
(491
(501
(4BI
(471
External
Hold
Capacitor
(.51
(481
TlH
Out
Bipolar
Input
(391
(381
(37) Offset Adjust
(36) Gain Adjust
Mux Enable (5)
cr-3 State
Buffer
ChO( + I/ChO (41
Ch1( + I/Ch1 (31
Ch2( + I/Ch2 (21
Ch3( + I/Ch3(11
Ch4( + I/Ch4 (621
Ch5( + I/Ch5(611
Ch6( + lICh6 (601
16 Channel
Single
Ch7( + I/Ch7(591
ChO(- I/ChB (5BI
Ch1(-IICh9(571
8 Channel
Dlfferential
Mlix
12-8il
AID
or
(351
(341
(331
(321
MSB
Bil2
Bil 3
BII'
(31)
Eii'ibie (Bits 1-4)
(301
(291
(281
(271
Converter
Ch2(-I/Ch10 (561
Ch3(-I/Ch11 (551
Ch4(-IICh12 (541
Bil 5
BitS
Bit 7
Bit B
(26) En'ibie (Bits 5-8)
(251 Bil9
(241 Bit 10
Ch5(-I/Ch13 (53)
Ch6( - I/Ch 14 (521
Ch7(-IIChI5 (511
(23) Bit 11
(221lSB
MN7150-B/MN7150·16
M
Add~:SS
Oulputs
~
(21)
A, (121
A~ (11) <>-------+~
"A.(:~: ~::::::::::::::::::::::::::::::::::::::::::t~~H
(7)
(40)
(191
(161
(151
(141
(131
(201
(BI
LOad
A,
AI
A.
AI
Ciear
Str'O"be
(61
R Delay
E'ii'8bie (Bits 9-12)
Sta't"US
+ l0V ReI. Out
---0
---0
---0
(43) + lSV Supply
(441 - 15V Supply
(18) + 5V Supply
---<>
(41) Analog Signal Gnd.
(42) Analog Power Gnd.
(17) Digital Ground
---0
---0
Mux Address
Inputs
APPLICATIONS INFORMATION
SUMMARY OF OPERATION-The falling edge of a Strobe
pulse loads the multiplexer (mux) channel address and initiates a signal-acquisition and data-conversion cycle. If
sequential addressing is being used, the next channel will
be accessed. If random addressing is being used, the channel whose address has been applied to the Mux Address
Inputs will be accessed. The falling edge of Strobe simultaneously fires an internal one-shot (10!,sec pulse duration)
whose output controls the operational mode of the trackhold amplifier (T/H). The T/H is driven into the signal-acquisition (tracking) mode for 10!,sec during which the mux and
instrumentation amplifier settle and the T/H acquires the
new signal. After 10!,sec, the falling edge of the one-shot
drives the track-hold amp into the hold mode, gates on the
internal clock, generates a start-convert signal for the 12-bit
AID converter, and drives the Status Output to a logic "1".
Gating off the clock during the time the mux is settling into
its new channel and the T/H is acquiring a new signal reduces noise errors. When the conversion is complete (a
maximum 10!,sec later), the Status output returns to a logic
"0" indicating that the conversion is complete, that the
digital output is valid, and that the T/H amplifier has returned to the tracking mode. The unit is now ready to be
triggered for the acquisition. and conversion of the next
channel.
9-34
LAYOUT CONSIDERATIONS-Proper attention to layout
and decoupling is necessary to obtain specified accuracies
from the MN7150-8 and MN7150-16. Units are designed with
separate pins for Analog Power Ground (pin 42), Digital
Ground (pin 17) and Analog Signal Ground (pin 41), and if
your system distinguishes these grounds, the MN7150's
pins should be connected respectively. If not, the MN7150's
three ground pins should be tied together as close to the
unit as possible and all connected to sy",em analog ground,
preferably through a large analog ground plane beneath the
package.
For the MN7150-16, the inverting input to the internal instrumentation amplifier (pin 50) is not connected to the internal
multiplexer and this pin should be connected along with
pin 41 (Analog Signal Ground) to the signal-source reference
point.
Coupling between analog inputs and digital signals should
be minimized to avoid noise pick-up. Pins 36 (Gain Adjust),
37 (Offset Adjust) and 38 (Bipolar Input) are particularly
noise susceptible. Care should be taken to avoid long runs
or runs close to digital lines when utilizing these inputs. If
optional gain and offset adjusting is used, care should be
taken to locate potentiometers and series resistors as close
to the MN7150 as possible.
The output of the MN7150's T/H amp is internally connected
directly to the input of the AID converter. When operating in
a unipolar (0 to + 10V) mode, however, pin 39 (T/H Output)
must be connected to pin 38 (Bipolar Input) for proper operation. For bipolar (± 10V) operation, pin 40 (+ 10V Ref. Out)
must be connected to pin 38 (Bipolar Input) and pin 39
left open.
Pin 43
Pin 18
'I
1; ,"~F_I-'-
I
__
+ 5V
Pin 42
...II_OO~r::nd
,
I
Pin
DIGITAL PIN FUNCTIONS
ANALOG PIN FUNCTIONS
Pin 44
I
+ 15V
'+-f
T I
Ground
0
-
1 "F
MN7150 has internal 0.011'F bypass capacitors on each
supply line. It is recommended that power supplies be additionally decoupled with tantalum and ceramic capacitors
located as close to the device as possible. For optimum performance and noise rejection, 11'F tantalum capacitors
paralleled with 0.011'F ceramic capacitors should be used
as shown in the diagrams.
Pin
C
1'IF
O.01/IF
0.01 "F
15V
POWER SUPPLY DECOUPLING
Pin
Designation
Function
Designation
Mux Enable (Pin 5)
"0" disables internal mux. "1"
enables internal mux. Use to
disable internal mux when
addressing additional external
multiplexers.
R Delay (Pin 6)
Status (E.O.C.)
(Pin 7)
End of conversion. "0" =
signal acquisition cycle in
progress. "1" = AID conversion
cycle in progress. 1 -0 indicates conversion complete.
See Timing Diagrams.
Connect external resistor to
lengthen T/H acquisition time
when instrumentation amp is
set for high gain. R = (Acq.
Time) 10· - 9kO. For normal
operation pin 6 must be connected to + 5V.
Gain Adjust (Pin 36)
Connect user-optional, external, 20kO, gain-adjust potentiometer here.
Offset Adjust (Pin 37)
Connect user-optional, external, 20kO, offset-adjust potentiometer here.
Function
Strobe (Pin 8)
"1" - "0" falling edge updates
(increments) mux channel and
initiates signal acquisition
and AID conversion cycles.
Bipolar Input (Pin 38)
Mux Address Out
(pins 9-12)
Output of mux address
register. Shows channel
currently on. Straight binary
coding. See section describing
Channel Address Modes.
Connect to T/H Output (pin 39)
for unipolar (0 to + 10V) operation. Connect to + 10V Ref.
Out (pin 40) for bipolar (± 10V)
operation.
T/H Output (Pin 39)
Mux Address In
(Pins 13-16)
Selects mux channel in
random address mode.
Straight binary coding. See
section describing Channel
Address Modes.
Connect TlH Output to Bipolar
Input (pin 38) for unipolar
operation. Leave open for
bipolar operation.
+ 10V Ref. Out
(Pin 40)
Connect to Bipolar Input (pin
38) for bipolar (± 10V) operation. Open for unipolar (0 to
+ 10V) operation. Accuracy
= ± 0.05% typical. Drift =
± 10ppm/oC typical. Buffer
if used to drive external
load.
Add external polypropylene or
teflon hold capacitor to improve T/H droop rate_
=
Load (Pin 19)
"0" random address mode.
"1" = sequential address
mode.
Clear (Pin 20)
A logic "0" applied to this pin
forces mux address to ChO on
next falling edge of strobe
regardless of Load and Mux
Address Inputs. Tie to logic
"1" when not in use.
Enable (Bits 9-12)
(Pin 21)
"0" enables three-state buffer
for AID converter bits 9-12
(LSB). "1" disables buffer.
Enable (Bits 5-8)
(Pin 26)
"0" enables three-state buffer
for AID converter bits 5-8. "1"
disables buffer.
Enable (Bits 1-4)
(Pin 31)
"0" enables three-state buffer
for AID converter bits
1(MSB)-4. "1" disables buffer.
External Hold
Capacitor (pins 45-46)
Gain Setting
Resistor (Pins 47-48)
Inputs (Pins 49-50)
1'""ro~",.,;O"
Amp
Select gain resistor with
formula R = 20k/(G - 1). Leave
open for G = 1.
Use when adding additional
external multiplexers for expanded single-ended or differential operation. Connect
pin 50 to Analog Signal Common for MN7150-16.
9-35
STATUS OUTPUT (E.O.C.)-The status or End of Conversion
(E.O.C.) output (pin 7) indicates whether the MN7150 is
tracking or converting an input signal. When Status is a
logic "0", the MN7150's internal TlH amplifier is in the track·
ing mode and digital output data from the previous conver·
sion is still valid. When the Status is a logic "1 ", the T/H is in
the hold mode, the internal AID is converting, and the output
data is not valid. The falling edge of Status indicates that
the conversion is complete, that the output data is valid,
and that the T/H has returned to the tracking mode.
CHANNEL ADDRESS MODES
The MN7150·8 and MN7150·16 may have their input
multiplexer channels either randomly or sequentially ad·
dressed. For random addressing, pin 19 (Load) must have a
logic "0" applied. For sequential addressing, pin 19 must
have a logic "1" applied.
Address
Mode
Mux
Enable
Load
Clear
Address Address
Inputs Outputs
Random
1
0
1
Sequenlial
1
1
1
Don't
Care
On
Channel
1-0
Free Running
Sequential
(Note 2)
1
1
1
Don'l
Care
On
Channel
(Note 1)
1-0
Next
On
Channel Channel
SEQUENTIAL ADDRESSING CONTINUOUS CONVER·
SIONS-The MN7150 can be made to continuously sequence through channels acquiring and converting data by
applying logic "1's" to the Load and Clear pins (pins 19 and
20) and tying the Status (E.O.C,) output (pin 7) back to the
Strobe input (pin 8). In this mode, Status going low at the
end of a conversion becomes the falling edge of Strobe that
addresses the next channel and initiates the next data ac·
quisition and conversion cycle. After each channel has been
converted and the Status has dropped to a "0", the output
data will be valid for approximately the next 10l'sec while
the multiplexer is switching channels and the T/H is acquir·
ing the new signal. When continuously converting in this
manner, an external Strobe signal should be provided at
power-on to avoid possible latch·up.
Strobe
1-0
NOTES
1. In the free running sequential address mode, the channel address output
lines indicate the channel currently being sampled (Ch n) while digital output data is valid for the previously sampled channel. (Ch n - 1).
2. The free running sequential mode is implemented by tying the Status out·
put (pin 7) to the Strobe input (pin 8). At the end of each conversion, the fail·
ing edge of Statu5 increments the address counter and initiates the next
acquisition/conversion cycle.
RANDOM ADDRESSING-For random channel addressing,
the Load pin (pin 19) must be tied to logic "0"; the Clear pin
(pin 20) tied to logic "1" (or left open); and the desired channel address (in 8421 binary) applied to the Mux Channel Address Inputs (pins 13·16, pin 16 = A" pin 15= A" pin 14 = A.,
pin 13 = A,). In this address mode, the MN7150's internal
address latch/counter acts as a 4·bit parallel register. The
falling edge of the Strobe pulse latches the new channel ad·
dress and initiates the data acquisition and conversion cy·
cle. For the MN7150·8 (8·channel differential input), address
line A, is not required and pin 13 is a "don't care",
When Clear (pin 20) has a "0" applied, the next falling edge
of the Strobe command will drive the mux to channel 0 (ad·
dress 0000) regardless of the data on the address input lines
and regardless of the signal applied to the Load line.
Because the Strobe line activates the control logic and does
not drive the address latch directly, channel·address input
data must be va.lid 50nsec both before and after the falling
edge of the Strobe pulse.
SEQUENTIAL ADDRESSING-For sequential channel ad·
dressing, the Load pin (pin 19) and the Clear pin (pin 20)
must both be tied to logic "1". In this mode, the internal address latch/counter acts as a 4·bit counter, and the falling
edge of the Strobe pulse increments the channel address
and initiates tl:1e data acquisition and conversion cycle.
Channel 0 will be accessed after channel 7 (MN7150·8) or
channel 15 (MN7150·16). If one changes from random to
sequential addressing, the next channel accessed will be
9·36
one higher than the channel last randomly addressed,
Changing digital data appearing at the address Inputs will
not affect the MN7150 when it is in the sequential address
mode.
Address Inputs
A.
A.
A,
A,
Mux
Enable
Channel
Selected
X
X
X
X
0
None
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
3
4
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
2
5
6
7
1
1
8
9
1
1
1
10
11
1
1
1
12
13
14
15
MN7150·8
MNT150-16
NOTES
1. For the MN7150-8, Mux Address Input Line A, (pin 13) is a "don't care". Pin
13 is connectea to the MN7150·8's address Io.tchfcounter. however. the AI
output of the latch/counter is not connected to the MN7150·S's internal
mux.
CHANNEL ADDRESS OUTPUTS-The MN7150's Channel
Address Outputs (pins 9·12) are tied directly to the unit's in·
ternal address counterllatch. They indicate, in 8421 binary,
the multiplexer channel presently being accessed. When us·
ing external multiplexers for expanded differential or singleended operation, these outputs can be used to address the
external multiplexers, eliminating the need for any addi·
tional address decoding circuitry. When using sequential
addressing, the appropriate Channel Address Outputs can
be NORed together to generate a frame sync pulse each
time channel 7 (8 channel systems) or channel 15 (16 channel systems) is being addressed. In microprocessor·based
systems, the Address Outputs can be 3·state buffered to
add channel read·back capability.
TIMING DIAGRAM
Random Addressing
Sequential Addressing
10
10
11
11
><== Channel 3 = = = = = = = = =
Tracking (10"sec maximum)
Status
AID Start Command
Internal Clock
MSB
SSSSS\SSSSSS\S\SSS\S\\SS~
Bit 2
\SSSS\SSSSSSSSSSSSSSSSSSSJ
Tracking
Converting (10Jlsec maximum)
Converting
LJ1
,----,
Bit 3 SSSSSSSSSSSSSSSSSSSSSSSSSJ
~
Bit5 SSSSSSSSSSSSSSSSSSSSSSSSS!
Bit 6 S\\\sssssssssssssssSssssS!
Bit 7 ~_~\SSSSSSSssssssssssr
L
LJ 1
Bit 8 SSS\\SS\\\SS\ \\\S\SSSSSSSJ
Bit 9 SSS'SSSSSSSS\S\SSSSSSSSSSI
Bit 10 S:SS::S::S:,\'\\\SS" "'SSSSSSS'\!
Bit 11
~~~\\\\\\\\
0
LJ 1
,\\\\\\\SJ
Ur:1; - - - - · - - - - - - - - - - - - - - -
=
::::S='_" ,-=s='3\ \\\\\\\\\\SJ
LSB
Output Data
= ..
Channel II
0
~
Bit 4 SSSSSSSSSSSSSS\\\S\SS\\\S!
LJ 1
><= Channel 12
Data Val id - - X C = = = = = Not Valid
=
Data Valid
x= Not Valid
=
TIMING DIAGRAM NOTES
2.
3.
4.
5.
MN7150's internal clock and AID start-convert command signals are not
pinned out externally. They are included here to help the user understand
MN7150 operation.
The data acquisition/conversion cycle is initiated by the falling edge of
strobe. The strobe has a minimum positive or negative pulse width of
40nsec. In other words, strobe must be positive a minimum of 40nsec
prior to its falling edge and negative a minimum of 40nsec after its
falling edge.
Strobe may be brought high after an acquisition/conversion cycle has
begun with a new cycle not beginning until the next falling edge.
Mux Address, Load and Clear inputs must be valid 50nsec before and
after the falling edge of strobe.
Mux Address Outputs become valid typically 40nsec after the falling
edge of strobe.
6. The internal clock is gated off during the 10/lsec signal acquisition
period to reduce noise.
7. When Status = "1 ", the internal T/H is in the hold mode, and the AID con·
verter is performing a conversion. When Status = "0", the conversion is
complete; output data is valid; and the TlH has returned to the track
mode. Data will remain valid until Status goes high again.
8. When the Status goes high indicating that an AID conversion has begun,
the MSB goes to a "0" and all other output bits go to a "1". Output bits
are set to their final state on succeeding rising clock edges.
9. When enabling 3-state output buffers to access digital data, data
becomes valid no longer than SOnsec after an enable line is brought low.
DIGITAL OUTPUT CODING
Analog Input Voltage (Volts)
Unipolar Ranges
General
o to
+10V
Bipolar Ranges
General
:!:10V
Digital Output
MSB
LSB
FS
FS-1 V, LSB
+ 10.0000
+9.9963
+FS
+ FS-1%LSB
+ 10.0000
+ 9.9927
1111 1111 1111
11111111111.11"
'h FS + V, LSB
'hFS- 'l2LSB
'hFS-1%LSB
+ 5.0012
+4.9988
+4.9963
0+ %LSB
0- %LSB
0-1'hLSB
+0.0024
-0.0024
-0.0073
~_fIWI"
0+ V,LSB
0
+ 0.0012
0.0000
- FS+ V2LSB
-FS
-9.9976
-10.0000
0000 0000 O~"
0000 0000 0000
1000 0000 000(1"
01111111111(1"
NOTES
1. FSR stands for full scale range and is equivalent to the nominal peak-topeak voltage of the selected input voltage range.
2. 1LSB for a 12·bit system is equivalent to FSR/4096. Therefore, for a 20V
FSR, 1LSB = 4.88mV; for a 10V FSR, 1LSB = 2.44mV, etc.
3. For unipolar input ranges, output coding is straight binary. For bipolar input
ranges, output coding is offset binary.
·Voltages given are the theoretical values for the transitions indicated.
Ideally, with the converter continuously converting, the output bits in·
dlcated as _ will change from "1" to "0" or vice versa as the input voltage
passes through the level indicated.
EXAMPLE: For an MN7150 operating on its ± 10V input range. the transition
from digital output 0000 0000 0000 to 0000 0000 0001 (or vice versa) will
ideally occur at an input voltage of - 9.9976 volts. Subsequently. any input
voltage more negative than - 9.9976 volts will give a digital output of all
"O's". The transition from digital output 1000 0000 0000 to 0111 1111 1111
will ideally occur at an input of - 0.0024 volts, and the 1111 1111 1111 to
1111 1111 1110 transition should occur at +9.9927 volts. An input more
positive than + 9.9927 volts will give all "t's".
9·37
OPTIONAL OFFSET AND GAIN ADJUSTMENTS-The
MN7150 will operate as specified without additional
adjustments. If desired, however, system absolute accuracy
error can be reduced to ± 1LSB by following the trimming
procedure described below. Adjustments should be made
following warmup, and to avoid interaction, the offset ad·
justment must be made before the gain adjustment.
Multiturn potentiometers with TCR's of 100 ppm/·C or less
are recommended to minimize drift with temperature. Series
resistors can be ± 20% carbon composition or better. If
these adjustments are not used, Pins 36 and 37 should be
left open. Do not ground. If gain and offset adjusting is be·
ing performed on the MN7150-16, reference voltages may be
applied to any channel. If gain and offset adjusting is being
performed on the MN7150-8, reference voltages should be
applied to the (+) input of a given channel with the (-) input
tied to analog ground.
OFFSET ADJUSTMENT-Connect the offset potentiometer as
shown and apply an analog input voltage equivalent to + 'I2LSB if
operating in a unipolar mode or - '/2 LSB if operating in a bipolar
mode. Have the MN7150 performing repeated conversions, either
by being in the continuous converting mode or by being under external control. For the unipolar mode, adjust the offset potentiometer
"down" until all the output bits are "0". Then adjust "up" until the
LSB justturns to a "1 ". For bipolar mode, adjustthe potentiometer
"down" until the bits are MSB 011111111111 LSB. Then adjust it "up"
until the bits just turn to MSB 100000000000 LSB.
GAIN ADJUSTMENT-Connect the gain potentiometer as shown
and apply an analog input voltage equivalentto +FS-1'/2 LSB. With
MN7150 performing repeated conversions, adjust the gain potentiometer "up" until all the output bits are "1". Then adjust "down"
until the LSB just turns to a "0".
MN7150
It is recommended that gain and offset adjusting be ac·
complished while the system is performing continuous or at
least repeated conversions. If random addressing is used,
the mux will have to be held on one channel during the pro·
cess. If the continuous·converting sequential·address mode
is used (Status output tied to Strobe input), the Clear line
will have to be held low to keep the input multiplexer on
channel O. Alternatively, the voltages may be applied to all
channels simultaneously.
MULTIPLEXER EXPANSION-The MN7150-16's input capa·
bilities are easily expanded beyond 16 channels with the
addition of external analog multiplexers. The diagrams
below show the implementation of 32·channel single-ended
and 16-channel differential systems. For further singleended expansion, additional mux"s can be tied to pin 49
(the noninverting input to the internal instrumentation
+ 15V
(4)
(35)
MSB
(9)-(12) (22)
LSB
MN7150·16
.,
Offset (37)
Adjust
20kll
-15V
amplifier) or cascaded in front of the MN7150's internal mux.
Remember that for single·ended operation, pin 50 (the
inverting input to the internal instrumentation amplifier)
has to be grounded. For further differential expansion,
additional multiplexers will have to be tied to both the
inverting (pin 50) and noninverting (pin 49) inputs of the
internal instrumentation amplifier.
ChO
ChO (+)
.."!~ 20kll
Gain (36)
Adjust
(35)
(4)
Ch15
ChI5(+)
Address
Mux
Inputs
(51) (16)-(13)(8)
(50)
~'
~A'~~~
LSB
j~: ~~~~~U--f
Address A,
Mux
Inputs
A8
A,sO----
A:
SirObeo------......t>o--I
Strobe
HI-506A
ChO (-) o - r - - - I Mux Out
Mux
Address
Outputs
Enable
-----
Ch15 (-) <>---'----1
A·E~~~§A.
A4
A2
A,
A4
A2
ChI6o-r---i Mux Out
Ch31o-L----i
AI
Expansion to 16 Differential Channels
[1JJ
_
A,
Enable
A4
A2
A,
Expansion to 32 Single-ended Channels
MICRO NETWORKS
Mux
Address
Outputs
~
E==~9:E===~ AeA4A"
HI-506A
324 Clark SI., Worcester, MA 01606 (508) 852-5400
9-38
MSB
MN7150-16
A2
A,
MN7208
MN7216
[1D
_
MICRO NETWORKS
DATA ACQUISITION SYSTEM
FRONT-END
DESCRIPTION
FEATURES
• Complete DAS Front End:
Analog Input Multiplexer
Instrumentation Amplifier
Load/Sequence Control Logic
• Small 40-Pin DIP
• 16-Single-Ended or
8-Differential
Input Channels
• 10",sec Channel Switching and
In-Amp Settling Time
• Full Mil Operation
-55"<: to +125"<:
• Use with MN6000 Series
Sampling AID Converters
for Multi-Channel Digitizing
• MIL-H-38534 Screening
Optional. MIL-STD-1772
Qualified Facility
The MN7208 and MN7216 are thin-film hybrid circuits containing
two 8-channel multiplexers, random and sequential address
control logic and a precision instrumentation amplifier. This DAS
front-end function is packaged in a 40-pin side-brazed DIP and
can be used with Micro Networks MN6000 Series of sampling
AID converters to configure a complete, 16-channel singleended or an 8-channel full differential data acquisition system in
as few as 2 dual in-line packages. Extremely versatile, the
MN720817216 can be used in a wide variety of multi-channel
data acquisition applications.
The multiplexer section of the MN7208 and MN7216 features
over voltage protected analog inputs and break-before-make
channel switching. The internal control logic allows both random
and sequential channel addressing. The precision instrumentation amplifier's fast settling time and internal gain setting
resistors combine to offer high-speed and precision gain accuracy and low drift.
Channel access and settling time for both the MN7208 and
MN7216 to ±O.01% for a 20V step is 10jlSec maximum. These
devices, when used with the MN6774 12-Bit, 100kHz sampling
AID converter, can be configured into a fLP-interfaced 12-Bit,
50kHz data acquisition system (multi-channel AID) complete
with multiplexer, instrumentation amplifier, T/H amplifier, AID
converter and all interface and address decode logic.
The MN7208 and MN7216 have been designed to offer the user
maximum flexibility when designing for multi-channel data conversion applications where small size and physicaVeleetrical
compatibility are paramount considerations. Standard devices
are specified fully for ODe to +70D
e (J and K models) or -55De
to +125 De (S and T models) operation. For militarylaerospace or
harsh-environment industrial applications, "S" and "T" models
are available with environmental stress screening. Contact
factory for availability of fully compliant MIL-H-38534 devices.
[LJJ
_
October 1990
Copyright © 1990
Micro NIIIworId Mooe A (Read periormE..>d dUring cOllVerslon. MUX address and PGA
Timing Diagram Mode A
Gctln Address latched With Sl 10,000,000:1
>142 dB
V/F,
FN
±0.05%FS
± 0.05% of Input
1000
24 Pin
10·11
-10\1
> 2,000,000:1
>126 dB
VlF
±O.Ol%FS
± 0.01% of Input
650
24 Pin
10·15
oto
-10\1
> 5,000,000:1
>134 dB
V/F
±0.02%FS
± 0.02% of Input
800
24 Pin
10·15
oto
-10\1
> 10,000,000:1
>140 dB
V/F
±0.05%FS
± 0.05% of Input
850
24 Pin
10·15
Dynamic
Range
Type
Linearity
-10\1
> 2,000,000:1
>126 dB
V/F,
FN
oto
-10\1
> 5,000,000:1
>134 dB
MD3810
oto
-10\1
2MHz
MD3902
oto
5MHz
MD3905
10MHz
MD3910
V/F - Based 20-Bit AID Converters MD2840/2841/2842
ConvetSion
Time (msect
Model #
FulI·Scale
Differential
Linearity (ppmt
Integral
Linearity
Power
(mWt
DIP
Package
Page
No.
100
MD2840
10MHz
0.1
±O.05%FS
± 0.05% of Input
1195
32 Pin
10·5
200
MD2841
5MHz
0.2
±0.02%FS
± 0.02% of Input
1195
32 Pin
10·5
500
MD2842
2MHz
0.5
±O.OI%FS
± 0.01% of Input
1195
32 Pin
10-5
Power
(mWI
DIP
Package
Page
No.
700
40 Pin
10·19
VIF
24-Bit, 50MHz Counter/Timer MD5024
v'
Counter
Range
Programmable
Time Base
Operating
Mode
/LP
Interface
24 Bits
1 to 16 X 107
Clock Periods
Continuous
or Triggered
8 or 16
Bits
Application
Mode
Frequency
Counting or
Period
Measurement
Indicates New Product.
10-3
MICRO NET\NORKS
~
10-4
December 1991
Copyrigh1 , 1991
MICRO NETWORKS
324 Clark St., Worcester, MA 01606 (508) 852-5400
Micro Networks
All rights reserved
MD2840/2841/2842
llU
_
MICRO NETWORKS
100/200/500msec
INTEGRATING AID CONVERTERS
DESCRIPTION
FEATURES
• 20-Bit Integrating AID
• Programmable Conversion Time
• Continuous Sampling
• < 10j.lV Sensitivity
• Repeatability to 0.3ppm
• Microprocessor Compatible
• 1,000,000:1 Dynamic Range
• No Dead Time
Models MD2840/2841/2842 are complete, integrating AID
converters performing 20-bit conversions in 100
milliseconds, 200 milliseconds and 500 milliseconds respectively. This series uses a charged-balanced asynchronous
V/F converter architecture with internal counterltimer for
ultra-precise repeatability of wide-dynamic-range, slowly
varying signals.
With an input range of -1Ot-tV to -10V, this series provides
'A/D conversion with a dynamiC range of 1,000,000:1 (120db)
without the complications and errors associated with gainranging or logarithmic schemes.
Their unique architecture allows for continuous integration of
the input signal, improving noise rejection and avoiding the
annoying dead time associated with most integrating converters. The MD2840/2841/2842 Series achieves remarkable
repeatability of 0.3 ppm at up to 100 samples per second
depending on mode, speed, and resolution chosen (see
respective applications criteria).
32 PIN DIP
Commands to the converter and data from the converter are
communicated over an 8-bit microprocessor-compatible bus.
The unit can be used in continuous-sample or triggered
mode, where a data-ready flag alerts the t-tP that the conversion is complete.
i
r r-;t~D"
10.46)
1
--1
R1:'··
r _I
1.760
I-~~~
0900
-(22.9)
Analytical Instrumentation
i I~~
144.7)
~------'
APPLICATIONS
I
Automatic Test Equipment
Clinical Chemistry
Data-Acquisition Systems
~..J..
Elemental Analysis
~I
---J
""I
L
r
Magnetometers
Medical Instrumentation
Seismology
Thickness & Weighing Systems
Industrial Data Collection
o.iso
(63)
Dimensions In Inches
I
(millimeters)
~
_
MICRO NETWORKS
April 1992
Copyright ' 1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
10·5
MD2840/2841/2842 VlF, FIV CONVERTERS
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperatu re Range
+ 15V Supply (Pin 31)
-15V Supply (Pin 32)
+5V Analog Supply (Pin 29)
+5V Digital Supply (Pin 15)
Digital Inputs (Pins 4, 5, 6,
20, 21, 22, 23, 25, 26)
Analog Input
O°C to +70°C
-25°C to +100°C
+15.45 V
-15.45 V
+5.25 V
+5.25 V
~:~:~u::::e _________________M_D_=r-~840/~/2T842
5MHz Full-scale
2M Hz Full-scale
-
-0.3V to +5.3V
-15 V to +15V
SPECIFICATIONS (TA=+25OC, Supplies = ±15Vand +5V unless otherwise specified)
MIN.
ANALOG INPUTS
UNITS
MAX.
TYP.
Oto -10
Input Voltage Range
Volts
%
5
Overrange
Single-Ended
Configuration
Input Impedance
MD2840, MD2841
MD2842
kG
kn
6
14
1--'
- - ------
Offset Voltage
(trimmable to zero)
TRANSFER CHARACTERISTICS
Full-Scale Output
mV
±10
._._-MHz
MHz
MHz
,--._---%
±1
10
5
2
MD2840
MD2841
MD2842
Gain Error
(trimmable to zero)
--Differential Nonlinearity
Integral Nonlinearity
(maximum)
MD2840
MD2841
MD2842
Full-Scale Step Response
(maximum)
-Overload Recovery
(maximum)
0.1
0.2
0.5
MD2840
MD2841
MD2842
±0.05% FS ± 0.05% V,,,
±0.02% FS ± 0.02% V"
+0.01% FS + 0.01% V"'
MD2840
MD2841
MD2842
51'sec + 2 cycles of new fouT
10l'sec + 2 cycles of new fouT
20l'sec + 2 cycles of new fouT
MD2840
MD2841
MD2842
Noise (30)
(V'N = -10V, 1 sample/sec,
~_minutes)
ppm of FSR
ppm of FSR
ppm of FSR
12 cycles of new fouT
10 cycles of new fouT
8 cycles of new fouT
MD2840
MD2841
MD2842
5
4
3
"V
"V
- - 1 - - . _ - - - ----_., IN
STABI,LlTY
Gain Temperature Coefficient
60
Offset Temperature Coefficient
10
Power Supply Rejection
-
Gain
Offset
Warm-up Time
(to specified accuracy)
DIGITAL INPUTS
Logic Levels Logic "1"
Logic "0"
Pulse Width
RIW
All Others
Current Drains
10-6
ppm of FSR/oC
200
10
ppm of FSR/%Vs
I'v/%Vs
2
Minutes
nsec
50
10._.
--I--'
..
±14.55
+4.75
+15V
-15V
+5V
30
._----1----_._Volts
Volts
+0.4
+2.4
POWER SUPPLY REQUIREMENTS
± 15V Supplies
+5V Supplies
ppm of FSR/oC
100
±15.45
+5.2~
3
10
200
nsec
__._--_.- 1----------Volts
Volts
---------mA
mA
___
m~ ___
JI
THEORY OF OPERATION
The MD2840/2841/2842 Series uses a charge-balanced asynchronous V/F converter with internal counter-timer architecture as
shown in Figure 1. The full-scale range of the V/F is 10MHz for the
2840, 5MHz for the 2841 and 2M Hz for the 2842. The input signal
is tracked by the VlF, producing a pulse frequency linearly proportional to its full scale, ie:
This frequency is accumulated by the counter/timer for the full conversion time of the AiD and presented at the output as a binary word
up to 24 bits wide. The continuous tracking and accumulation of
pulses performs an inherently monotonic integrating function.
Once the pulse accumulation is complete, the count is instantaneously transferred to the output stage, ready to be accessed by the "P.
In the continuous sample mode, the counteritimer instantaneously
begins to accumulate counts for the next measurement. In the external trigger mode, the counteritimer awaits a trigger command
before beginning the next accumulation of pulses.
In both cases the V/F continues to generate a pulse frequency proportionately tracking the input signal. There is no dead time on these
converters, so the integration period and the conversion time is the
same and the terms are used interchangeably.
SENSITIVITY VS SPEED The sensitivity of the
MD2840/2841/2842 Series is directly proportional to the amount of
time the converter is allowed to integrate the input signal.
Sensitivity
=
VFS
VFS
FFS
Te
A. For Sensitivity - Often sensitivity, that is, the minimum change
in input voltage detectable by the converter, will be the overriding
criterion.
In that case, calculate the percent of full-scale represented by the
sensitivity. The inverse of that number represents the full scale
count needed.
S = VFs/(FFS • Te)
For Example
10"Von 10VFs =lppm
l/1ppm = 10· counts
or
lmV on 10V = 0.01%
1/0.Q1% = 104 counts
Next, determine the amount of time required for the V/F to generate
that count full scale. That will be your conversion time:
Model
MD2840 (10M Hz)
MD2841 (5MHz)
MD2842 (2M Hz)
10. Counts
0.1 sec
0.2 sec
0.5 sec
10' Counts
0.001 sec
0.002 sec
0.005 sec
or
B. For Integration Period Integration Period = Te = VFsI(FFS' Sensitivity)
Example: At 100 msec integrating (conversion) time
Model
MD2840 (10M Hz)
MD2841 (5MHz)
MD2842 (2M Hz)
FFs'Te
Where
CHOOSING A CONVERSION TIME - The architecture of the
MD2840/2841/2842 Series allows the designer to choose the conversion time of the AiD converter, for the sensitivity, for integration period,
or for a combination of both criteria.
Full-scale Voltage
Full-scale Frequency of the VlF
Conversion Time
EXAMPLE -If the MD2840, (with its 10MHz VlF) integrates the input signal for 1110th of a second, it will accumulate 1,000,000 pulses.
If the full-scale input voltage is 10V, each pulse counted will represent 10"V. Thus, the sensitivity of the MD2840 at 10 samples per
second is 10"V.
v,,,
Count
10. counts FS
5 x 105 counts FS
2 x 105 counts FS
Resolution
- 20 Bits
-19 Bits
-18 Bits
Sensitivity
10"V
20"V
50"V
C. Combination - In multiplexed systems different sensitivity/speed
combinations may be required for each channel. This is easily accomplished with the MD2840/2841/2842 Series by a simple program command setting the conversion time.
With the very wide dynamic range of the MD2840/2841/2842
Series the entire input range can be sampled at high speed and
low resolution until the desired level is detected. Then the integration time can be extended for higher-sensitivity measurements.
Where several instruments share one analog front-end designa combination of speed and sensitivity can be programmed into
the MD2840/2841/2842 Series "on the fly."
I",
Sometimes the conversion time dominates the design decision.
This is true when trying to reject periodic normal-mode noise such as 50/60 Hz line pickup. Then the conversion time should
be set at an integer multiple of the period of the noise (ie. 20 msec
or 40 msec or 60 msec for 50Hz rejection). 100 msec integration
is common as it rejects both 50 and 60 Hz pickup. Once the conversion time is chosen, the resolution and sensitivity can be
calculated.
Figure 1. Md2840/2841/2842 Block Diagram
Modell
Conversion Time
MD2840
10M Hz
100 SPS
100"V
10SPS
10"V
1 SPS
l"V
(16 Bits)
(20 Bits)
(23 Bits)
MD2841
5MHz
200"V
20"V
2"V
MD2842
2MHz
(15 Bits)
(19 Bits)
(22 Bits)
500"V
50"V
5"V
I
(14 Bits)
(18 Bits)
(21 Bits)
Table 1 - Sensitivity and Resolution With 0-10V F.S.
10-7
PROGRAMMING CONVERSION TIME
Conversion time is programmed by writing an 8-bit word to the AID
converter. RIW should be placed in a logic O. Program data are loaded on lines 00-07 and the Enable command is strobed low per
Figure 2.
MSB
07
MSB
0
Note setup and hold time of 10 nsec minimum before and after Enable
and the 50 nsec minimum Enable pulse width.
0
0
The programmed conversion time (Tc) is related to an external clock
(Fak) by the following formula. Clock frequencies up to 50MHz are
acceptable.
Tc = 1 X 6 X 10N
Fa,
STEP 4:
A/W
~I
l~E~~~~I~~
I
I
VALID PROGRAM DATA
I
I
~
I
I
~
I I
I
I
I
I
~
----t /"+t-
f.-
V
I
I
I I Ir10-nSEC MIN
5O-nSEC MIN
ENABLE
PULSE
11
HOLD TtME
-+j
WIDTH
><=
DON'T CARE
AD. A1. A 2 X
PIN DESIGNATIONS
32
1 VIN
2
10-8
0
1
0
1
0
1
0
1
17
B=
B3 B2 B1 BO
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
2
3
4
5
6
7
8
10
11
12
13
14
15
16
32 -15V
31 +15V
liN
3 Offset Tri m
30 Analog Ground
4 A2
29 +5V (ANA)
4 A1
28 FOUT -V/F Output Frequency
6 AO
Z1 FIN -Input to Counter
7 DO
26 RIW - ReadIWrite Select
8 D1
25 Enable
9 D2
24 DR-Data Ready
10 D3
23 R-Reset
11 D4
22 S-Start
12 D5
21 CS/SS
13 D6
20 CLK In
14 D7
19 CLK Out
15 +5V(DIG)
18 Xtal
16 Digital Ground
17 Xtal
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 2 - Compiling the Conversion Time Byte.
Example 1
2)
1)
For Tc = 100 msec and Fa, = 10MHz
Tc X Fak = 6 X 10N
100 msec X 10 X 106 = 10 X 105
3)
Choose N=5
4)
Code
6=10
MS6 N
0
101
B
0110
Example 2
1) For Tc = 1 msec and FCIk = 10MHz
2)
Tc xFclk=6x.l0N
1 msec X 10 X 106 = 10 X 103
3)
Choose N=3
4)
Figure 2. WRITE Command Timing
16
0
0
1
1
0
0
1
1
LSB
03 02 01 00
B3 B2 B1 BO
9
I I
I
I
~
ENABLE
Pin 1
0
0
0
0
1
1
1
1
Select desired conversion (integration) time.
Multiply time base by Fm. The answer is 6 X 10N.
Choose 6 as large as possible within 1-16 range. Determine appropriate N.
Assemble program byte (with MS6 = 1) selecting N & 6
from Table 2.
I I
DO·D7
0
1
2
3
4
5
6
7
X 10N
For a 10MHz Crystal Tc = 1_ X 6
107
STEP 1:
STEP 2:
STEP 3:
06 05 04
N2 N1 NO
N= N2 N1 NO
Code
6=10
MS6 N
011
0
B
0110
READING THE DATA
The MD2840/2841/2842 Series is capable of up to 24-bit
measurements. These are read out on the 8-bit bus in three bytes.
There are also overflow and programming bytes. The bytes are addressed at pin AO, A1, A2 per Table 3 via the timing commands in
Figure 3.
To read data, set the RIW line to the logical "1" (high) state, and the
AO, A1, A2 control lines to the appropriate states for the data byte
desired. The order in whic~ these signals are applied isn't important,
as long as they are present and static for at least 10 nsec before the
Enable (E) line is activated, and for a minimum of 10 nsec after Enable
(E) is removed. The Enable line performs the actual read operation;
it is a negative pulse, at least 50 nsec wide. Valid data is present on
the output bus 30 nsec maximum after the leading edge of Enable;
the data bus returns to a high impedance state 25 nsec maximum
after the trailing edge of the Enable pulse.
~~--------------I
~
RIW
ENABLE
K=
I
I
I
I
~-r-I
r-I
___
I f-
50 nSEC MIN
FpN~L~~E
WIDTH
I
I
I
I
AO
I
A1
A2
COMMAND
BYTE
a
a
a
READ
lOWER
1
a
a
READ
MIDDLE
a
1
a
READ
UPPER
1
1
a
READ
1
a
1
READ
----j~
l.-1()
liS! C MIN
HOlO 1iM[
--..l I I
I
I
I
I
I
----~'--~K~·___D~~~L_'D~~
I
~ ~!~~~~70
DATA HOLD
I
-.f
TIME
OVERFLOW
PROG
BYTE
Table 3 - Addressing the data bytes.
OVERFLOW AND PROGRAMMING
READBACK BYTES
If the 24-Bit counter overflows, the overflow bit (Do) on the Overflow
Byte (A = 110) will be in a high state. The data bits will roll over to
zero and continue to count. Thus, using the overflow bit, it is possible to use the MD2840/2841/2842 Series as a 25-bit converter. See
Table 3 and Figure 3 for commands and timing.
At any time the AID can be interrogated as to its programmed status
by reading the Program Readback Byte (A = 101). This will read back
the conversion time program byte.
OPTIONS
1. Offset voltage may be trimmed to zero using a 20KO potentiometer
with drift less than 100ppm/°C.
2. Full Scale output can be trimmed to zero error using a 2000 potentiometer with drift less than 100ppm/°C.
3. +5V (ANA) may be regulated for optimal performance using a National78l05 (typical) +5V regulator.
4. An optical isolator or isolation transformer may be inserted between Foci and F" to isolate the analog and digital sections of the
AID, if dictated by system requirements.
5. Clock frequency may come from a system clock, up to 50MHz
maximum, applied to ClK'N (pin 20). Alternately an oscillator
clock can be generated using a crystal (10MHz typical). Crom may
then be added to trim the crystal to the exact frequency desired.
Crcom values between 2 and 25pF are typical.
Figure 3. READ Command Timing
NOTES:
DR - Data Ready - Generates a logical "1" that indicates that
data has been latched and is ready to read. On Reset (pin 23) Data
Ready becomes active high and remains high until a READ operation is performed.
R - Reset - When logical' '0" is applied to pin 23 all operations
are stopped and all counters and latches are reset to zero. A
minimum pulse width of 100 nsec at logical a is requred.
S - Start and CS/SS - Continuous Sample ISynchronous Start
- When CS/SS is low, the converter, after receiving a single start
command, will continuously convert the input. When CS/SS is
High, the converter will wait for a START command before beginning the next conversion. The START command is positive edge
- triggered.
+5V (DIG) and +5V (VFC) may be supplied from the same +5V
supply. See Option #3.
Fo", and Fin should be tied together for normal operation. Fe", can
be used as a test pOint to check the output of the VlF. An optical
isolator or isolation transformer may be inserted between Fout and
F" to totally isolate the analog and digital sections of the converter. See Option #4.
ClK IN Receives a system clock up to 50MHz. ClK" should be
tied to ClKoo• if Crystal Oscillator Clock Circuit is used. See Option #5.
Xtal No connection if clock is supplied by System to pin 20
(ClK/o). For self-generated Crystal Clock See Option #5.
ORDERING INFORMATION
MD284a20 Bits • 100 msec
MD284120 Bits. 200 msec
MD284220 Bits • 500 msec
10-9
+15V
+5V (ANA)
+5V (DIG)
OPTION 3
+5V REGULATOR
OPTION 5
10MHz
;h
CTR1M
0
-
10M!!
OPTION 2
31
29
28
27
15
17
18
19
20
200!!
GAIN TRIM
OPTION 1
ClKOUT
ClKIN
7-14
DO-D7
26
AO-A2
+15V
~
-15V
4.5.6
'""'
30
OFFSET TRIM
32
-15V
16
23
21
25
R
CS/SS
E
ANALOG GROUND
Connection Diagram With Options
[1dJ
_
MICRO NETWORKS
324 Clark St.. Worcester. MA 01606 (508) 852-5400
10-10
R/W
24
DR
22
START
M 03802/3805/381 0
I
l- :)
__ MICRO NETWORKS
2/5/10MHz
V/F, FIV CONVERTERS
DESCRIPTION
FEATURES
• Guaranteed Minimuml
Maximum Specifications
• Wide Dynamic Range
> 2,000,00015,000,000/10,000,000:1
>126/1341142 dB
• Excellent Linearity
±0.01/0.02/0.05% FSR
±0.01/0.02/0.05% of Input
• Excellent Stability
10 /lV/OC Offset
75 ppm/oC Gain
• Voltage or Current Inputs
• Offset and Gain Error
Trimmable to Zero
• Complementary Frequency
Outputs-TTL/CMOS Compatible
• Small 24-Pin DIP
• Low Power
< 0.75/0.8511.0W
24-PIN CERAMIC DIP
PIN 1
\
\
--L--.
O~25"1
131
(332)
1 :00(2794)
I
I
'-------_ _--.J J _
L 0.80.0. ma' --l
1- (20.31 -I
'[-----11 __ L
1
t
I-
r
0..600
I
(15.21
...
:.J -+;:1
0205
(5.21
0155
(391
Models MD3802/3805/3810 are high-performance, precision
2/5/10MHz full-scale voltage-to-frequency converters, intended for those applications that require maximum performance
at the most economical cost. These converters feature
> 125/134/142-dB dynamic range, ±0.01/0.02/0.05% linearity,
and ±5% overrange capability.
All models accept a -100/lV to -10V full-scale analog input
signal that is converted to an output signal whose frequency
is proportional to the full-scale frequency within
±0.01l0.02/0.05% linearity, using the long-proven chargebalance technique. The devices offer buffered complementary TTL-compatible frequency outputs that will drive
capacitive loads as high as 50 pF.
Models MD3802/3805/3810, in addition to functioning as V/F
converters, can also be used as FIV converters. In this configuration, the converters will accept frequencies from dc to
2/5/10MHz and will produce proportional single-ended output voltages from OV to -10V.
In applications where overall system throughput must be
maintained at a specific rate, or where fixed offset or
different scale voltages would be more convenient, custom
frequencies and/or custom trimming can be easily accommodated. By increasing the full-scale output frequency by 10
to 20% for example, additional time would be available for
the system microprocessor to access the results of each
conversion. Please contact the factory to discuss your
specific timing requirements.
All models are packaged in a 1.31" x 0.80" x 0.15" 24-pin
ceramic DIL package. Power dissipation is lower than
0.75/0.85/1.0 watts, and operation to specified accuracy is
guaranteed over the ooe to + 70°C temperature range.
APPLICATIONS
Precision Integration
Data Recording
Digital Data Transmission
Frequency Synthesis
Weighing Systems
Analytical Instrumentation
Dimensions In Inches
(millimeters)
[LJJ
_
Tachometers
Accelerometers
Medical Instrumentation
Flow Meters
Telemetry
Robotics
MICRO NETWORKS
April 1992
Copyright
1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852-5400
10-11
I
ABSOWTE MAXIMUM RATINGS
Operaling Temperature Range
Storage Temperature Range
+ 15V Supply (Pin 1)
-15V Supply (Pin 5)
+5V Supply (Pin 20)
Analog Input (Pins 11)
O°C to +70·C
-65°C to + 150·C
+15.45 V
-15.45 V
+5.25 V
-15 V to +15V
ORDERING INFORMATION
PART NUMBER
MD3802 I 3805 I 3810
2MHz Full-scale _ _ _ _ _~_----l-:r
5MHz Full-scale
10MHz Full-scale
T
T
SPECIFICATIONS (TA= +25OC, Supplies = ±15Vand +5V unless otherwise specified)
MIN_
ANALOG INPUTS
TYP.
o to
Input Voltage Range
Nonsaturating Overrange
MAX.
-10
UNITS
Volts
5
%
Configuration
Single-Ended
Input Impedance
15
10
5
MD3802
MD3805
MD3810
Offset VoltaPce
(trimmable 0 zero)
±7
k!l
k!l
k!l
±10
mV
TRANSFER CHARACTERISTICS
Full-Scale Output
MD3802
MD3805
MD3810
Transfer Function
MD3802
MD3805
MD3810
MHz
MHz
MHz
2
5
10
2MHz·(V,N /10V)
5MHz'(V,N /10V)
10MHz'(V,N/10V)
Gain Error
(trimmable to zero)
MD3802
MD3805
MD3810
Nonlinearity (max.)
(not specified under
overrange conditions)
Full-Scale Step Response
(maximum; to 0.01%)
Overload Recovery
MD3802
MD3805
MD3810
±1
%
75
100
ppm of FSR/·C
ppm of FSR/·C
±0.01%FS±D.01%V'N
±0.02%FS±D.02%V'N
±0.05%FS±D.05%V'N
2 cycles of new fOUT +20~sec
2 cyctes of new fOUT + 10~sec
2 cycles of new fOUT +5~sec
MD3802
MD3805
MD3810
8 cycles of new fOUT
10 cycles of new fOUT
12 cycles of new fOUT
STABILITY
Gain Temperature Coefficient MD3802
MD3805, MD3810
50
75
Offset Temperature Coefficient
10
Power Supply Rejection
Gain
Offset
Warm-up' Time
(to speCified accuracy)
30
ppm of FSR/·C
200
10
ppm of FSR/%V s
2
Minutes
300
120
60
nsec
nsec
nsec
+4.5
0.4
Volts
Volts
±15.45
+5.25
Volts
Volts
20
25
35
rnA
rnA
rnA
~VI%Vs
OUTPUT
Pulse Width
MD3802
MD3805
MD3810
Logic Levels: Logic "1"
Logic "0" (3 rnA sink)
200
80
40
250
100
+3.5
+4.0
50
POWER SUPPLY REQUIREMENTS
± 15V Supplies
+5V Supply
+ 15V Current Drain
~ . ' " Co,,'" D~"
+5V Current Drain
Power DISSipation
I
10-12
±14.55
+4.75
MD3802
MD3805
MD3810
MD3802
MD3805
MD3810
MD3802
MD3805
MD3810
10
rnA
45
50
60
rnA
rnA
rnA
750
850
1000
mW
mW
mW
.- ::!::
.- ::t
4
4
OFFSET
ADJUST
+15V
AGND
O(23.4}
::J::
::!:
D(5)
-15V
Q(20)
.'v
(8)
GROUNDING - The A'1alog and Digital grounds are internally
separate in the MD38XX models. The use of ground plane is not
necessary for proper operation of the MD38XX. However, a ground
plane is recommended with any analog Signal conditioning circuitry
that my be used in a VlF application, especially if this circuitry involves
high gains. Any amplifiers used ahead of the MD38XX should have
decoupling capacitors on their power supply pins to help eliminate
potential problems with the high-frequency output of the V/F.
DGNO
I,. )10)0----+----1
v",
0(1)
OFFSET AND GAIN CALIBRATION
f---+------{) (9)
OFFSET CALIBRATION - Offset calibration should be performed
prior to gain calibration. With a -lmV analog input signal at pin 11
of the MD38XX, adjust the OFFSET potentiometer until a frequency
of 200/S00/1000Hz is observed on output pins 21, 23 or 24.
(11)n-J"\/'''_O-'--'
(19)
F,,, '
(18)
F..,
(23.24)
(21)
OUTPUT
OUTPUT
N/C PINS - Pins marked as N/C (no connection) have no electrical
connection to the internal circuitry of the MD38XX.
Figure 1. MD3802/3805/3810 Block Diagram.
USING THE MD38XX
GENERAL CONSIDERATIONS - A typical circuit configuration tor
the MD38XX models used as V/F converters is depicted in Figure 2.
The layout should be clean, with output pulses routed as far away
from the input analog signals as possible. To obtain maximum performance, bypass capacitors, as shown in both figures, should be
mounted right at the appropriate pins of the converters.
20011.
l().lUAN
v.
GAlN
ADJUST
} OUTPUT
"
10
I.
20.1<11
lo..TURN
OUTPUT PINS - Pins 23 and 24 are tied together internally. Either
or both may be used as the source of the frequency output of the
MD38XX, as long as the load specifications are not exceeded. Pin
21 provides a complementary signal relative to pins 23 and 24 with
similar loading limits.
VlF MODE
ANALOG INPUTS - Single-ended analog inputs from 0 to -lOV are
applied to pin 11 of the V/F converter through the GAIN adjustment
potentiometer.
FNMODE
sl00ppm
.-~
GAIN CALIBRATION - With a full scale analog input voltage of
-10.00V on pin 11 (MD38XX), adjust the GAIN potentiometer until
a full scale frequency of 2.000/S.000/10.000MHz is observed on output pin 21, 23, or 24.
21
0u"TPlrT
"
OFFSET
ADJUST
"
Figure 3 depicts the typical circuit configuration for the MD38XX used in the FN mode. In this mode, the MD38XX will accept a 0 to
2/S/10MHz input pulse train, with negative-going pulses, (2S0±SO)
(100±20) (SO± 10)nsec in width, and will produce a voltage output proportional to the input frequency. Riding on the ouput voltage will be
a ripple Voltage. Additional filtering of the output voltage by the use
of a 2-pole active filter will reduce the output ripple as shown in Table
1. A representive 2-pole active filter circuit is shown in Figure 4.
Suitable component values are listed in Table 1. It is recommended
that a high input impedance, low noise op amp be used, and that offset nulling be done in order to obtain accurate dc performance.
_15V
20KII
10-TURN
OFFSET
ADJUST
Figure 2. V/F Converter Configuration.
OFFSET AND GAIN TRIMMING - The OFFSET adjustment potentiometer should be a 20 kn, la-turn unit. With this pot in the circuit,
initial offsets of up to ±10mV may be trimmed to zero.
The GAIN adjustment potentiometer should be a 200n, 10-turn unit.
To ensure that the temperature coefficient of the potentiometer does
not become significant relative to the overall gain tempco specification, a 100 ppm or better potentiometer is recommended, With this
pot in the circuit, initial gain errors of up to ±2% may be trimmed
to zero.
.oNO'>--+....,2. 3. 4
GAIN
ADJUST
t--,-.....--~v"
>-_+!20
20011.
10-TURN
",'00ppm
OGNO·'---i.....LJ"
Figure 3. FN Converter Configuration.
10-13
FCUTOFF
Oulput Ripple (mV)
M03802 M03805 M03810
20 kHz
180
470
16.2
46.2
70
35
5
25 kHz
150
330
21.0
39.2
60
20
5
30 kHz
150
330
17.4
27.4
60
40
5
50 kHz
68
180
16.9
48.7
50
20
5
100 kHz
33
100
143
53.6
80
20
5
Figure 4. Typical 2-Pole Active Filter
VlFN ANALOG DATA INK - Figure 5 depicts the MD38XX used as
both the V/F and FN in an analog data link. Low-level analog data
may be transmitted over considerable distances with no degradation due to noise using this system, and with total system linearity of
0.02/0.04/0.10%.
Cl(pF) C2(PF) R1(kn) R2(kn)
Table 1. Ripple Reduction by Active Filter
200H.
1O·TURN
5:iOOppm
V"
11
11111 )
§""
24
GAIN
ADJUST
23
18
20KU
10·TURN
21
10
-15V
OFFSET
19
+15V
ADJUST
2OK9oFFSET
,0-TURN
ADJUST
8
18
-15V
+15V
+15V
2.3.4
AGND
AGND
2.3,4
GAIN
ADJUST
20
-15V
-15V
+5V
+5V
YOU!
200!!.
20
1Q-TURN
11
DGND
22
Figure 5. Analog Data Link.
PIN DESIGNATIONS
Pin 1
12
24
13
1 +15V Supply
24 Output
2 Analog Ground
23 Output
3 Analog Ground
22 Digital Ground
4 Analog Ground
21 Output
4 -15V Supply
20 +5V Supply
6 No Connect
19
7 No Connect
8 Offset Trim
18 F'N
17 No Connect
9 VOUT
16 No Connect
10
I'N
11 V'N
12 No Connect
10-14
FOUT
15 No Connect
14 No Connect
13 No Connect
22
::il00ppm
MD3902/390S/3910
~
_
MICRO NETWORKS
2/5/10MHz
V/F CONVERTERS
DESCRIPTION
FEATURES
• Outstanding Pricel
Performance Ratio
• Guaranteed Minimuml
Maximum Specifications
• Wide Dynamic Range
> 2,000,000/5,000,000/10,000,000:1
>126/1341142 dB
• Excellent Linearity
±0.01/0.02/0.05% FSR
±0.01/0.02/0.05% of Input
• Excellent Stability
10 INloC Offset
60 ppm/oC Gain
• Voltage or Current Inputs
• Offset and Gain Error
Trimmable to Zero
• Complementary Frequency
Outputs-TTL/CMOS Compatible
• Small 24-Pin DIP
• Low Power
< 0.65/0.S0/0.S5W
24-PIN CERAMIC DIP
..
.io"p
(2.5)
H-'
_0018
O<6I
o170 m,n
Models M03902/3905/3910 are high-performance, precision
2/5/10MHz full-scale voltage-to-frequency converters, intended for those applications that require maximum performance
at the most economical cost. These converters feature
> 125/134/142-dB dynamic range, ±0.Q11O.02/0.05% linearity,
and ±5% overrange capability. The M03902/3905/3910
devices feature overall performance and stability virtually
identical to that of similar units costing 40% or more.
All models accept a -1001lV to -10V full-scale single-ended
analog input signal that is converted to an output signal
whose frequency is proportional to the full-scale frequency,
within 0,01/0.02/0.05% linearity, using the long-proven
charge-balance technique. The devices offer 5% overrange
capability, and buffered complementary TTL-compatible
frequency outputs that will drive capacitive loads as high as
50 pF.
Stability of the M03902/3905/3910 Series is excellent for V/F
converters in the respective price ranges, with 10IlV/oC
typical, 30llV/oC maximum offset and 60 ppm/oC typical, 100
ppm/oC maximum gain temperature coefficients. Warm-up
time to specified accuracy is less than two minutes.
In applications where overall system throughput must be
maintained at a specific rate, or where fixed offset or
different scale voltages would be more convenient, custom
frequencies and/or custom trimming can be easily accommodated. By increasing the full scale output frequency by 10
to 20%, for example, additional time would be available for
the system microprocessor to access the results of each
conversion. Please contact the factory to discuss your
specific timing requirements.
All models are packaged in a 1.31" x 0.69" x 0.22" 24-pin
plastic OIL package. Power dissipation is lower than
0.65/0.8010.85 watts, and operation to specified accuracy is
guaranteed over the O°C to +70°C temperature range.
(43)
APPLICATIONS
Dimensions In Inches
(millimeters)
~
Precision Integration
Data Recording
Digital Data Transmission
Weighing Systems
Frequency Synthesis
Tachometers
Analytical Instrumentation
Accelerometers
Medical Instrumentation
Flow Meters
Telemetry
Robotics
MICRO NETWORKS
April 1992
Copyrighl © 1992
Micro Networks
All rights reserved
324 Clark St., Worcester, MA 01606 (508) 852·5400
10-15
MD3902/3905/3910 VlF CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
+ ISV Supply (Pin I)
-ISV Supply (Pin S)
+SV Supply (Pin 20)
Analog Input (Pins II)
ORDERING INFORMATION
O°C to +70 oC
-6SoC to + ISO°C
+IS.45 V
-15.45 V
+5.25 V
-15V to +15V
T
T
PART NUMBER
MD3902 I 390S I 3910
2M Hz Full-scale-_ _ _ _ _ _ _ _ _=r-l
SMHz Full-scale
10MHz Full-scale
SPECIFICATIONS (TA = +25OC, Supplies = ±15Vand +5V unless otherwise specified)
ANALOG INPUTS
MIN.
Input Voltage Range
TYP.
MAX.
Oto -10
Nonsaturating Overrange
UNITS
Volts
S
%
Configuration
Single-Ended
Input Impedance
MD3902
MD390S
MD3910
kQ
kQ
kQ
15
6
6
I
Offset Voltage
(Irimmable to zero)
±7
±10
mV
TRANSFER CHARACTERISTICS
Full-Scale Output
MD3902
MD390S
MD3910
Transfer Function
MD3902
MD3905
MD3910
MHz
MHz
MHz
2
5
10
2MHz·(V,Jl0V)
5MHz·(V,Jl0V)
10MHz·(V"/IOV)
Gain Error
(trimmable 10 zero)
Nonlinearity (max.)
(not specified under
overrange conditions)
MD3902
MD390S
MD3910
Full-Scale Step Response
(maximum; to 0.01%)
Overload Recovery
±1
%
60
100
ppm 01 FSR/oC
10
30
ppm 01 FSR/oC
200
10
ppm 01 FSR/%V,
2
Minutes
±O.OI%FS±O.D1%V"
±0.02%FS±0.02%V'N
±0.05%FS±0.05%V"
2 cycles of new '0<" +20~sec
2 cycles 01 new lou, + 10~sec
2 cycles 01 new fo", +5~sec
MD3902
MD390S
MD3910
MD3902
MD390S
MD3910
8 cycles 01 new lau,
10 cycles 01 new lou;
12 cycles of new fo",
STABILITY
Gain Temperature Coeflicient
Offset Temperature Coefficient
Power Supply Rejection
-
Gain
Olfset
Warm-up' Time
(to specllied accuracy)
~VI%V,
OUTPUT
Pulse Width
MD3902
MD390S
MD3910
Logic Levels: Logic "I"
Logic "0" (3 mA sink)
200
80
35
250
100
50
300
120
6S
nsec
nsec
nsec
+3.S
+4.0
+4.S
0.4
Volts
Volts
±IS.45
+5.25
Volts
Volts
20
30
30
mA
mA
mA
POWER SUPPLY REQUIREMENTS
±14.5S
+4.75
± ISV Supplies
+SV Supply
+ISV Current Drain
MD3902
MD3905
MD3910
-ISV Current Drain
+SV Current Drain
Power DisSipation
10-16
MD3902
MD3905
MD3910
MD3902
MD3905
MD3910
10
mA
40
40
SO
mA
mA
mA
6S0
800
8S0
mW
mW
mW
OFFSET AND GAIN TRIMMING - The OFFSET adjustment potentiometer should be a 20 kO, 10-tum unit. To insure that the temperature
coefficient of the potentiometer does not become significant relative
to the overall offset tempco specification, a 100 ppm or better potentiometer is recommended. With this pot in the circuit, initial offsets
of up to ± 10mV may be trimmed to zero.
----1~-0 (I) +15V
INTEGRA10R
',,.(10) 0----+--1
-"4:tr-l+-~O (2, 3. 4) AGNO
__--4T~O (5) -15V
--~1-0(20) +5V
rJ7T
The GAIN adjustment potentiometer should be a 2000, 10-turn unit
with a recommended temperature coefficient of 100 ppm or better,
With this pot in the circuit, initial gain errors of up to ±2% may be
trimmed to zero.
0(22) DGNO
GROUNDING - The Analog and Digital grounds are internally
separate in the MD39XX. The use of ground plane is not necessary
for proper operation of the MD39XX, However, a ground plane is
recommended with any analog signal conditioning circuitry that may
be used in front of the V/F, especially if this circuitry involves high
gains. Any amplifiers used ahead of the MD39XX should be decoupled to eliminate potential problems with the high-frequency output of
the V/F.
(23, 24) OUTPUT
L--------L=---:=---=-J----<> (21) OUTPUT
Figure 1. MD390213905/3910 Block Diagram
USING THE MD39XX
GENERAL CONSIDERATIONS - Figure 2 depicts a typical circuit
configuration for the MD39XX. The layout should be clean, with output pulses routed as far away from the input analog signals as possible. To obtain maximum performance, bypass capacitors, as shown
in Figure 2, should be mounted right at the appropriate pins of the
MD39XX.
+15V
ANALOG
GROUNG
,
::t
Me!-
I-
2
>--
4
2.
-15V
GAIN CALIBRATION - With a full-scale analog input voltage of
-10.0OV on pin 11, adjust the GAIN potentiometer until a full-scale
frequency of 2.000/S.000/10.000MHz is observed on output pin 21,
23, or 24.
FOUl
roW
3
,F
2'
N/C PINS - Pins marked as No Connect have no electrical connection to the internal circuitry of the MD39XX.
5
20
-;'
*6B
,F
22
2OO
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2017:07:25 13:02:45-08:00
Modify Date : 2017:07:25 13:46:30-07:00
Metadata Date : 2017:07:25 13:46:30-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:4de2d42e-e5f0-5d4b-99b0-1322534e7b63
Instance ID : uuid:227f488f-80a2-ad4e-8a20-010ea914ada7
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 587
EXIF Metadata provided by EXIF.tools