1992_Microchip_Data_Book 1992 Microchip Data Book
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[
OCHIP
BOOK
®
Microchip
Microchip
Microchip Data Book
1992 Second Edition
SERVING A COMPLEX AND COMPETITIVE
WORLD WITH USER - PROGRAMMABLE
EMBEDDED CONTROL
SYSTEM SOLUTIONS
© 1992 Microchip Technology Inc.
October 1992/ DS00018E
Microchip
TI and TMS320 are trademarks of Texas Instruments Inc.
DEC, VAX, VMS, and ULTRIX are trademarks of Digital Equipment Corp.
MACINTOSH is a trademark of Apple Computer, Inc.
IBM and IBM PC are trademarks of IBM Corp.
I'CTM is a tradmark of Philips.
Microwire™ is trademark of National Semiconductor.
SMC is a trademark of Standard Microsystems Corp.
Windows™ is a trademark of Microsoft.
PICPAK, PIC-ICE, PICPRO, PICALC, PICSIM, PROMASTER and
PICMASTER are trademarks of Microchip Technology Inc.
PIC is a registered trademark of Microchip Technology Inc.
The Microchip logo and name is a registered trademark of Microchip
Technology Incorporated.
All rights reserved. Copyright © 1992, Microchip Technology Inc.
"Information contained in this publication regarding device applications
and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Inc. with respect to the
accuracy or use of such information, or infringement of patents arising
from such use or otherwise. Use of Microchip's products as critical
components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any intellectual property rights."
© 1992 Microchip Technology
DS00018E
ii
Table of Contents
Microchip
SECTION 1
MICROCONTROLLER PRODUCT SPECIFICATIONS
PIC®16C5X
PIC®16CR54
PIC®16C71
PIC®17C42
SECTION 2
DEVELOPMENT SYSTEMS
PICMASTER-16™
PICMASTER-17™
PICPAK-IiTM
PICPAK-17™
PICPRO-lpM
PRO MASTERTM
SECTION 3
EPROM-Based 8-Bit CMOS Microcontroller Series ................................... 1ROM-Based 8-Bit CMOS Microcontroller ................................................... 1- 61
8-Bit CMOS EPROM Microcontroller with AID Converter ........................... 1-105
High Performance 8-Bit CMOS EPROM Microcontroller ............................ 1-169
PICMASTER Universal In-Circuit Emulator System ................................... 2- 1
PICMASTER PIC®17CXX In-Circuit Emulator System ............................... 2- 5
PIC®16C5x Low-Cost Microcontroller Development System ...................... 2- 9
PIC®17C42 Evaluation/Development/Programmer Kit ............................... 2- 13
PIC®16C5x Microcontroller EPROM Programmer Unit... ............................ 2- 17
CMOS PIC® Microcontroller Programmer Unit ........................................... 2- 21
SERIAL EEPROM PRODUCT SPECIFICATIONS
24C01A
24C02A
24C04A
24C16
24LC01
24LC02
24LC04
24LC16
59C11
B5C72
85C82
85C92
93C06
93C46
93C56
93C66
93LC46/56/66
93LCS56
93LCS66
1K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 1
2K (256 X 8) CMOS Serial Electrically Erasable PROM ............................ 3- 9
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 17
16K (8x256x8) CMOS Serial Electrically Erasable PROM ......................... 3- 25
1 K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 33
2K (256 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 41
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 49
16K (8 x 256 x 8) CMOS Serial Electrically Erasable PROM ..................... 3- 57
1K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM ............ 3- 65
1K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 73
2K (256 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 81
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 89
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM .................... 3- 97
1K (64 x 16) CMOS Serial Electrically Erasable PROM ............................. 3-105
2K (256 x 8 or 128 x 16) CMOS Serial Electrically Erasable PROM .......... 3-113
4K (512 x 8 or 256 x 16) CMOS Serial Electrically Erasable PROM .......... 3-121
CMOS Serial Electrically Erasable PROM .................................................. 3-129
2K CMOS Serial Electrically Erasable PROM ........................................... 3-137
4K CMOS Serial Electrically Erasable PROM ............................................ 3-139
© 1992 Microchip Technology Inc.
DS00018E
iii
Microchip
© 1992 Microchip Technology
DS00018E
iv
Table of Contents
Microchip
SECTION 4
EEPROM PRODUCT SPECIFICATIONS
28C04A
28C16A
28C17A
28C64A
SECTION 5
EPROM PRODUCT SPECIFICATIONS
27C64
27C128
27C256
27C512
27HC1616
27HC256
27LV256
27LV512
27CXXX
SECTION 6
64K (8K x 8) CMOS UV Erasable PROM ................................................... 5128K (16K x 8) CMOS UV Erasable PROM ............................................... 5256K (32K x 8) CMOS UV Erasable PROM ............................................... 5512K (64K x 8) CMOS UV Erasable PROM ............................................... 5256K (16K x 16) High Speed CMOS UV Erasable PROM ......................... 5256K (32K x 8) High Speed CMOS UV Erasable PROM ........................... 5256K (32K x 8) Low Voltage CMOS Erasable PROM ................................ 5512K (64K x 8) Low Voltage CMOS Erasable PROM ................................ 527CXXX EPROM Family Programming Algorithm ..................................... 5-
9
17
25
33
41
49
57
65
32-Segment CMOS LCD Driver .................................................................. 6Product Portfolio ......................................................................................... 6CMOS Digital Signal Processor .................................................................. 6-
1
5
9
LOGIC PRODUCTS
AY0438
DSP
DSP320C10
SECTION 7
4K (512 x 8) CMOS Electrically Erasable PROM ...................................... .4- 1
16K (2K x 8) CMOS Electrically Erasable PROM ...................................... .4- 9
16K (2K x 8) CMOS Electrically Erasable PROM ...................................... .4- 17
64K (8K x 8) CMOS Electrically Erasable PROM ...................................... .4- 25
QUALITY AND RELIABILITY
Quality Without Compromise ................................................................................................................. 7Plastic Package Reliability .................................................................................................................... 7-
SECTION 8
1
9
PACKAGING
Packaging Outlines and Dimensions ..................................................................................................... 8-
APPENDIX
OFFICE LOCATIONS
Factory Representatives
Distributors
Factory Sales
.................................................................................................................... A- 1
.................................................................................................................... A- 5
.................................................................................................................... A- 13
© 1992 Microchip Technology Inc.
DS00018E
v
Microchip
DS00018E
© 1992 Microchip Technology
vi
Microchip Technology Incorporated
SERVING A COMPLEX AND COMPETITIVE
WORLD WITH USER-PROGRAMMABLE
EMBEDDED CONTROL
SYSTEM SOLUTIONS
Motivated by customer
requirements ....
"Microchip Technology draws its impetus from the technology expectations of a large base of longstanding customers.
Microchip is small enough to respond quickly with technology to
serve our customers' needs. Moreover, as a fully integrated IC
Manufacturer, Microchip deploys its panoply of resources to act
timely and efficiently, and on a worldwide scale: Technology
LJevelopment, Design, Wafer Fabrication, Assembly and Test,
Quality, Reliability and Customer Support.
... and powered by continuous
improvement...
"Worldwide competition leaves no room for divergence or mediocrity. Microchip Technology, committed to focus on and continuously improve all the aspects of its business, has a unique
corporate culture. To improve performance, our employees are
encouraged to analyze their methods continually.
Personal
empowerment expands the capability ofpersonal responsibility to
continually serve our customers better.
... riding and leading the wave
of technological change.
"Our industry's life-line is innovation. The fast pace of technological change is inherent in our industry. Microchip Technology has
accelerated the rate of change of its technology and products to
leadership in providing user-programmable space-sensitive embedded control solutions.
"Change is our ally. Driving and managing customer-focused
change is our winning strategy. "
Steve Sanghi
President & Chief Executive Officer
DS00027F-1
© 1992 Microchip Technology Inc.
vii
MICROCHIP
TECHNOLOGY
INCORPORATED
Microchip
Company Profile
HIGHLIGHTS
BUSINESS SCOPE
• Focused on user-programmable embedded
control solutions
Microchip Technology Inc. manufactures and markets
a variety of VLSI CMOS semiconductor components to
support the user-programmable embedded control
market. In particular, the company specializes in
highly integrated, user-programmable RISC microcontrollers and related non-volatile memory products
to meet growing market requirements for high performance, yet economical embedded control capability in
an increasing number of price-sensitive products.
Microchip's products feature the industry's most economical OTP (one-time programmable) capability,
along with the compact size, integrated functionality,
ease of development and technical support so essential to timely and cost-effective product development
by our customers.
• Providing RISC 8-bit user-programmable
microcontrollers and supporting logic products
Providing Serial and Parallel EEPROMs and
EPROMs
• A unique corporate culture dedicated to continuous improvement
Research and development of high performance
user-programmable products
A history of innovation
An experienced executive team focussed on
innovation
Quality without compromise
MARKET FOCUS
Fully integrated manufacturing
Microchip targets selected markets where our advanced designs, progressive process technology and
industry leading operating speeds enable us to deliver
decidedly superior performance. The firm has positioned itself to maintain a dominant role as a supplier of
high performance user-programmable microcontrollers
and associated memory and logic products for embedded control applications.
• A global network of manufacturing and customer
support facilities
Company headquarters in Chandler,
Arizona: Executive Offices, R&D,
and Wafer Fabrication occupy this
campus.
DS00027F-2
viii
© 1992 Microchip Technology Inc.
Microchip Technology Incorporated
GUIDING VALUES
Cystomers Are Qyrfocu$
lqtal Cycle Times Are CompetHive
We establish successful customer partnerships by exceeding customer expectations for products,services
and attitude. We earn our credibility through meeting
commitments and producing quality products and ser,i
vices In a timely fashion. We believe each employee
must effectively ,serve their internal customers In order
forMicrochip's externalcustomerstobe properly served.
We focus' resources to optimize cycle times to' our
customers by empowering emploYeGstoachieveefficien! cycle times in their area 01 responsii)ility.•• We
believe that cycle time reduction is achieved by streamlining processes lhrough the systematic removal of
barriers to productivity.
Sifety Jl Neyer Compromised
Qy@llll! Comes Firat
We place our concern for safety Of our er1"iployees and
community at the forefront of our decisions, policies and
actions. Each employee is responsible for safety.
We will perlorm correctly the first time, maintain customer satisfaction and measure our quality against
requirements, We practice effective and standardized
Improvement methods, such as statistical process contral to anticipate problems and implement root cause
solutions. We believe that When quality comes firs!,
reduced costs follow.
We 'strive to, maintain competitive profits as they allow
continued Investments and future growth, and indicate
the overall success of Microchip.
Continuous Improyement Is Essentigl
Communication Is Vital
We utilize the concept,of 'Vital Few" to ,estaQjish our
priorities. We concentrate our resources on contihUOu$ly
improving the Vital Few while empowering each' em'ployee to make continuous improvements Intheir areaof
responsibility. We strive for Constructive andhortestselfcriticism to Identify improvement opportunities,
We encourage open, honest, constructive, and ongoing
communication In all company and community relationships to resolve issues, exchange information and share
knowledge.
Profit, Provide for Everything We Do
syppliers, Bepresenlati)".' Andgi.tribytors
Are Our Partners
Employee, Are QueGreate" StillOgtb
We maintain mutually beneficial partnerships with suppliers, representatives, and distribi1tors who are an
integral link 'in the achievement of our mission and
guiding values.
We design jobs and provide opportunities ,in a fashion
which clearly promotes pride in work, integritY,trust,
teamwork, creativity, employee involvement and development, fairness, and productivity. We base recogni;.
tion, advancement and compensation on an employee:s
achievement of excellence in team and Individual performanCe. We provide for employee health and welfare by
offering a competitive, comprehensive employee benefits program.
Professional Ethics Are Practiced
We manage our business and treat customers, employeeS, shareholders, investors, ,suppliers, distributors, representatives, community and government in a manner
that exemplifies our honesty; ethics and ,integrity. We
repognlze our responsibility to the community and are
proucHo serve as an equal opportunity employer.
Prodyct, And Technology Are Our
foundation
We commit to ongoing Investments and advancements
in the design and development of our manufacturing
process, device circuit and system technologies, which
provide innovative, reliable and cost-effective products
to support current and future market opportunities,
DS00027F-3
© 1992 Microchip Technology Inc.
ix
Microchip Technology Incorporated
PRODUCT FOCUS
Microchip's productfocus is user-programmable microcontrollers,
nonvolatile memories and supporting logic. These product lines
include PIC® microcontrollers, EEPROMs, and High Speed
EPROMs in a broad range oftechnologies, speeds and packages.
Microchip is quick to capijalize on advances in one product line by
incorporating those breakthroughs into other product families.
Microchip targets selected markets where our advanced designs,
progressive process technology and industry leading operating
speeds enable us to deliver decidedly superior performance. The
firm has recently positioned itself to playa dominant role as a
supplier of high performance user-programmable microcontrollers
and associated memory and logic products for embedded control
applications.
PIC® Microcontrollers from Microchip combine high performance,
low cost, and small package size. They offer the best price/
performance ratio in the industry. Large numbers of these
devices are used in automotive and cost-sensitive consumer
products, such as remote controls and appliances, computer
peripherals, data entry, office automation, automotive control
systems, security, and telecom applications.
MICROCONTROLLERS
EPROM
EEPROM
HIGH
END
MID-RANGE
PIC 16CXX
MID
RANGE
LOW
END
CMOS PIC
Microcontroller Families
DEVELOPMENT SYSTEMS
The widely accepted NMOS PIC16XX (over 75 million units
shipped) and CMOS PIC16CXX and PIC17CXX series are the
industry's only a-bit microcontrollers using a high speed RISC
architecture. Microchip pioneered the use of RISC architecture to
obtain high speed and instruction efficiency. The CMOS PIC16CXX
is in high volume production, with more than 25 million units
shipped, and has achieved nearly five thousand design wins
worldwide.
The PIC17CXX family is the world's highest performance a-bit
microcontroller. It continues PIC's high performance RISC architecture with an a-bit data word and 16-bit instruction word,
allowing expanded internal/external memory. The PIC17C42
incorporates advanced motor control peripherals allowing control
of two single-phase motors with a single PIC17C42. High
performance inter-controller communications can be implemented
with the PIC17C42's 4-megabits-per-second serial I/O.
Future CMOS PIC product families will include advanced features, such as higher speed, additional I/O, sophisticated timers,
embedded AID, extended instruction/data memory, inter-processorcommunication, and ROM, EPROM and E2PROM memories.
Both PIC16CXX and PIC17CXX families are supported by a
range of user-friendly development systems including programmers, emulators and demonstration boards.
PICMASTERTM is an advanced real-time emulator system using
the user friendly Windows® software environment. PICMASTERTM is a Microchip-designed universal emulator for both
PIC16CXX and PIC17CXX families. PIC PRO II and PRO
MASTER are advanced low cost programmers.
DS00027F-4
© 1992 Microchip Technology Inc.
x
Microchip Technology Incorporated
SOFTWARE SUPPORT
Both PIC families are supported by a selection of support software
including assemblers, linkerlloaders and libraries. The PIC16C5X
family is also supported by a software simulator.
.
A full-featured compiler is under development to support both
families.
Customers can obtain on-line updates on Microchip Development
Systems and Support Software via the Electronic Bulletin Board
System, "EBBS."
SERIAL EEPROMs
Microchip offers one of the broadest selections of CMOS Serial
EEPROMs on the market for embedded control systems. Serial
EEPROMs are available in variety of densities, operating voltages,
bus interface protocols, operating temperature ranges and space
saving packages. Device densities range from 1K bits up to 16K
bits. In addition to 5V only operation, Microchip offers serials that
read and write either at 2.5 or 2 volts. I'CTM, Microwire™ and 4
wire bus interface protocols are standard. Devices come in
three standard operating temperature ranges; commercial,
industrial and automotive. Small footprint packages include: 8
pin DIP, 8 pin SOIC in JEDEC and EIAJ body widths and 14 pin
SOIC. Other key features of the Serial EEPROM product line
include: ESD protection greater than 4K volts and endurance
of lOOK cycles worst case and 1M typical.
Microchip is a high volume supplier of Serial EEPROMs to all the
major markets worldwide, i.e. consumer, automotive, industrial,
computer and communications. Microchip is developing leading
edge unique serial EEPROMs.
PARALLEL EEPROMs
The CMOS EEPROM devices from Microchip are available in 4K,
16K, and 64K densities. The manufacturing process used for
these EEPROMs ensures 10,000 to 100,000 write and erase
cycles. Data retention is over 1ayears. Short write times are less
than 200 I!sec. These EEPROMs work reliably under demanding
conditions and operate efficiently at temperatures from -55°C to
+125 °C. Microchip's expertise in surface mount packaging
supports our customers' needs in space-sensitive applications.
Typical applications include computer peripherals, engine control, pattern recognition and telecommunications.
EPROMs
Microchip's CMOS EPROM devices are produced in densities
from 64K to 512K. High Speed EPROMs have access times
as low as 55 nanoseconds. Typical applications include computer
peripheral, military, instrumentation, and automotive devices.
Microchip's expertise in Surface Mount Packaging led to the
development of the Surface Mount OTP EPROM market where
Microchip is the #1 supplier today. Microchipis also a leading
supplier of low voltage EPROMs for battery powered applications.
MILITARY PRODUCTS
Microchip delivers military devices that conscientious engineers
can use with confidence. Our 883C compliant parts cover all
quality fronts: DESC standard military drawing approval, high
speed performance and quick turn availability.
Microchip's military products include CMOS memories, CMOS/
NMOS digital signal processors and microcontrollers - all highly
reliable with fast access times and proven retention. Endurance
is guaranteed in both dual in-line cerdip packages and lead less
chip carriers.
© 1992 Microchip Technology Inc.
DS00027F-5
xi
Microchip Technology Incorporated
OTHER MICROCHIP
PRODUCTS
Other Microchip products, such as DSP products and Liquid
Crystal Display Drivers, are mature products with proven track
record and a large, repeat customer base. Microchip provides a
wide package selection of single-chip DSPs that can be programmed for a wide variety of applications. Several variants ofthe
industry standard 3201 0 and 320C1 0 are offered at speeds up to
25 MHz. The 320 DSP family is often found in commercial and
military applications where medium and high performance parts
are required.
RESEARCH AND
DEVELOPMENT OF
Microchip's research and development activities, include exploring new process technologies and products that have industry
leadership potential. Particular emphasis is placed on products
that can be put to work in high performance embedded control
markets.
PERFORMANCE PRODUCTS
Equipment is continually updated to bring the most sophisticated
process, CAD and testing on line. Cycle times for new technology
development are continuously reduced to bring innovative new
products to our customers.
FUTURE PRODUCTS
AND TECHNOLOGY
New process technology is constantly being developed for
EEPROM, High Speed EPROM, and microcontroller products.
Advanced process technology modules are being developed that
will be integrated into our present product lines to achieve a range
of compatible processes. Current production technology utilizes
dimensions down to 0.9 microns.
More advanced technologies are under development, as well as
advanced CMOS RISC-based microcontroller and CMOS
EEPROM products. Objective specifications for new products
are developed by close cooperation with our many customerpartners worldwide.
FULLY INTEGRATED
MANUFACTURING
Microchip delivers fast turnaround through total control over all
phases of production. Design, product development, mask making, wafer fabrication, assembly and quality assurance testing are
conducted at facilities owned and operated by Microchip. Our
integrated approach to manufacturing along with rigorous use of
advanced statistical process control, continuous improvement
and implementation of root cause solutions to problems, has
brought forth tight product consistency levels and high yields
which enable Microchipto compete successfully in world markets.
Microchip's unique approach to SPC provides customers with
excellent costs, quality, reliability and on-time delivery.
A GLOBAL NETWORK OF
PLANTS AND FACILITIES
Microchip is a global competitor providing local service to the
world's technology centers. The Company's focal point is the
design and technology advancement facility in Chandler; Arizona.
Most military and high performance parts emanate from here,
along with front end wafer fabrication and electrical probing.
Microchip's assembly and test facility in Kaohsiung, Taiwan
houses the technology and modern assembly methods necessary for plastic and ceramic packaging.
Sales and application offices are located in key cities throughout
the Americas, Pacific Rim and Europe. Offices are staffed to meet
the high quality expectations of our customers, and can be
accessed for technical support, purchasing information and failure analysis.
4,
'. i
© 1992 Mk:rochip Technology Inc.
DS00027F-6
xii
Microchip Technology Incorporated
CHANDLER, AZ FACILITY
Chandler Wafer Fabrication: Diffusion Area
Chandler Wafer Fab: Sub-micron Alignment Area
TAIWAN FACILITY
Microchip Technology Taiwan, established in 1966, was the first
semiconductor manufacturing company in the Kaohsiung export
processing zone in south Taiwan.
Microchip's Kaohsiung plant has progressively
developed into an assembly and test facility of
the highest standards.
The plants' excellent track record and continuing efforts to achieve higher levels of quality and
technological advancement has resulted in
superior yields and fast turnaround.
DS00027F-7
© 1992 Microchip Technology Inc.
xIII
~----------------------
"_.. _ - -
---
Microchip Technology Incorporated
QUALITY WITHOUT
COMPROMISE
Product reliability is designed into Microchip products at the
outset. Design margins are established to guarantee that every
product can be easily produced, error-free and operates well
beyond the tolerances of the manufacturing process.
All our quality assurance tests are run to tighter than customer
specifications. Products are tested at least two machine tolerances higher than those specified by the customer.
Every new product is measured under accelerated stress testing.
Qualification samples encompass the full range of processed
tolerances at each step. Data sheets detailing these processes
enable customers to reach accurate decisions based on known
quantitative values.
To determine whether a process is within normal manufacturing
variation, statistical techniques are put to work at each process
step. In-process controls are performed by operators in the wafer
fabrication division and immediate corrective action is taken if
they deem a process is out of our very tight SPC control limits.
Products are also sampled weekly through a variety of carefully
monitored stress and accelerated life tests.
Microchip's positive documentation control program assures the
correct document is always available at the point of use.
CONTINUOUS IMPROVEMENT
Individuals in all departments analyze the methods employed in
their positions and formulate plans to improve performance. This
continuous improvement process is never completed. Screening
efforts alone are never considered enough. In all areas of our
business, everyone is expected to make continuous improvements to support their part of Microchip's unique culture.
FORMING A QUALITY
ALLIANCE WITH
CUSTOMERS
Microchip works in tandem with customers to establish mutual
programs to improve the performance of our products in their
systems. Microchip's quality and reliability support is extended
through final shipment of our customer's products. Microchip's
quality programs ensure that our products can be used with such
confidence that acustomercan implement improvement programs
centered on us as a supplier.
DS00027F-8
© 1992 Microchip Technology Inc.
ivx
Microchip
SECTION 1
MICROCONTROLLER
PRODUCT SPECIFICATIONS
PIC®16C5X
PIC®16CR54
PIC®16C71
PIC®17C42
EPROM-Based 8-Bit CMOS Microcontroller Series ................................... 1- 1
ROM-Based 8-Bit CMOS Microcontroller ................................................... 1- 61
8-Bit CMOS EPROM Microcontroller with AID Converter ........................... 1-105
High Performance 8-Bit CMOS EPROM Microcontroller ............................ 1-169
© 1992 Microchip Technology Inc.
DS00018E
H
Microchip
DS00018E
© 1992 Microchip Technology
1-ii
Microchip
EPROM-Based 8-Bit CMOS Microcontroller Series
FEATURES
Oscillator start-up timer
• Watchdog timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Security EPROM fuse for code-protection
Power saving SLEEP mode
• EPROM fuse selectable oscillator options:
Low cost RC oscillator: RC
Standard crystal/resonator: XT
High speed crystal/resonator: HS
Power saving low frequency crystal: LP
High Performance RISC-like CPU
Only 33 single word instructions to learn
All single cycle instructions (200 ns) except for
program branches which are two-cycle
Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
12-bit wide instructions
a-bit wide data path
512 - 2K x 12 on-chip EPROM program memory
25 - 72 x a general purpose registers (SRAM)
7 special function hardware registers
2 level deep hardware stack
Direct, indirect and relative addressing modes for data
and instructions
CMOS Technology
Low power, high speed CMOS EPROM technology
Fully static design
• Wide operating voltage range:
Commercial: 2.5V to 6.25V
- Industrial: 2.5V to 6.25V
- Automotive: 2.5V to 6.0V
Low power consumption
< 2 mA typical @ 5V, 4 MHz
151lA typical @ 3V, 32 KHz
< 3 IlA typical standby current @ 3V, O·C to 70T
Peripheral Features
12 - 20 I/O pins with individual direction control
a bit real time clock/counter (RTCC) with a-bit
programmable prescaler
Power on reset
FIGURE A - PIN CONFIGURATIONS
PDIP,SOIC,
CERDIP Window
PDIP,SOIC,
CERDIP Window
--- RTCC
---.. VDD
_RA2
_
RA3
RA1RAO _
--- RlCC
--MCLR
----"Vss
---RSO
---RS1
---RS2
___ RB3
OSC1-OSC2/CLKOUl ---
N/C
--.- Vss
N/C
·1
2
3
"tJ"tJ
......
en en
00
---RAO
---RA1
---RA2
___ RA3
VDD-4-
RS7--RS6--RSS ___
RB4 ___
___ RBO
---RB1
___ RB2
---RB3
---RB4
00
10
11
12
13
14
SSOP
RA1RAO ___
-RlCC
-MCLR
OSC1-OSC2/CLKOUl -
-.. Vss
-RBO
_RB1
_RB2
_RB3
MCLROSC1OSC2/CLKOUT
--RC7 ___
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLROSC1OSC2/CLKOUT - RC7 ___
RC6--RCS--RC4--RC3 ___
RC2 ___
RC1 ___
RCO ___
RB7 ___
RBS ___
RBS ___
SSOP
_RA2
_
RA3
- - vss
UI UI
""-lUI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-'-Vss
--- RTCC
~VDD
VDO .....
VDO .....
RB7RBS--RSS_
RS4-
~VDD
4
---RAO
---RA1
---RA2
___ RA3
5
---RBO
___RB1
---RB2
---RB3
---RB4
- . . Vss
© 1992 Microchip Technology Inc.
"tJ"tJ
~~
en en
00
UI UI
""-lUI
RC6--RC5--RC4--RC3 ___
RC2 ___
RC1 ___
RCO ___
RB7 ___
RBS ___
RB5 ___
DS300151 - page 1
1-1
PIC®16C5X Series
20.1.1 Host System Requirements ...............................
...54
20.1.2 Emulator System Components ......
.. ............. 54
PIC-PAK'M Development Kit ............................................. 56
20.2
PI CALC Cross-Assembler ............................................... 56
20.3
20.4
PICSIM~ Software Simulator
............. 56
20.5
PICPRO'" II Programmer. .... ............................
.. ....... 56
PRO MASTER'M
.................................. 56
20.6
21.0
EPROM Programming.
...........................
.57
Prototype Programmers.
.. .... 57
21.1
Production Quality Programmers ................................ .. 57
21.2
Gang Programmers
...... 57
21.3
21.4
Factory Programming
....................... 57
... 59
Index
Sales and Support ...
.............. 60
Table of Contents
1.0
1.1
2.0
2.1
2.2
2.3
2.4
2.5
3.0
3.1
3.2
3.3
4.0
4.1
4.2
4.2.1
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
5.0
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
6.0
7.0
7.1
7.2
7.3
7.4
7.5
8.0
9.0
9.1
10.0
10.1
11.0
11.1
11.2
12.0
12.1
12.2
12.3
13.0
13.1
14.0
14.1
15.0
15.1
15.2
15.2.1
16.0
16.1
16.3
16.4
16.5
16.6
16.7
16.8
16.9
17.0
18.0
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
20.0
20.1
General Description ...
.......... 3
Applications
....... 3
Architectural Description.,
........ 3
Harvard Architecture
......................
...... 3
Clocking Schemellnstruction Cycle .....
........ 3
........................ 4
Data Register File .....................
Arithmetic/Logic Unit (ALU) ..... ..............................
... 4
Program Memory ..................
...................... 4
PIC 16C5X Series Overview ... ...
............ 5
UV Erasable Devices ...
........................
. ...... 5
One-Time-Programmable (OTP) Devices
................ 5
Quick-Turnaround-Production (QTP) Devices
.......... 5
Operatiocal Register Files .............................
............. 6
fO Indirect Data Addressing ..........
.6
f1 Real Time ClockiCounter Register (RTCC)
... 6
Using RTCC with External Clock ............
..... 6
f2 Program Counter ..
. ................ 8
Stack.........
........................................
......... 9
f3 Status Word Register
........................
........... 11
Carry/Borrow and Digit Carry/Borrow Bits ....
......... 12
Time Out and Power Down Status Bits (TO. PD) .............. 12
Program Page Preselect (PIC16C56, PIC16C57 Only) .... 12
f4 File Select Register (FSR) ..
.. .... 12
1/0 Registers (Ports) ..........................
...13
f5 (PortA).
.. .................... 13
f6 (Port B) ..... .................................
...13
f7 (Port C)
.. 13
1/0 Interfacing... ............................
.. .... 13
1/0 Programming Considerations ......... ... ..........
.. 14
Bidirectional 1/0 Ports..
.. ......... 14
Successive Operations on 1/0 Ports ..
...................... 14
Operation in Noisy Environment ....... .. .........
... 14
General Purpose Registers ...............
.. .................... 15
Special Purpose Registers ..
.,,15
W Working Register ........................
.. 15
TRISA 1/0 Control Register for Port A (f5) ....................... 15
TRISB 1/0 Control Register for Port B (f6) .......
.. ....... 15
TRISC 110 Control Register for Port C (f7)
............ 15
OPTION Prescaler/RTCC Option Register..
.. ...... 15
Reset Condition ... .............. ..................
.. ... 16
Prescaler ....... .......................................
.... 16
........... 16
Switching Prescaler Assignment
Basic Instruction Set Summary.
........... 17
Instruction Description
.............. 19
.. .................. 23
Watchdog Timer (WDT) . ....................
WDT Period .... .....................................
.. ..... 23
WDT Programming Considerations ........
.. ....... 23
Oscillator Circuits... ......................
.. ................. 23
Oscillator Types ...........................
.. ........ 23
Crystal Oscillator.
............. ...............
.. ...... 23
RC Oscillator .................................................................. 23
Oscillator Start-up Timer (OST)...
...25
Power On Reset (POR) ................................................... 25
Power Down Mode (SLEEP) ........................................... 27
Wake-Up...
...... ............
.. ..... 27
Configuration Fuses .......................
.. ............. 27
Customer ID Code
..... 27
Code Protection. .............................
.. ............ 28
Verifying a Code-protected PIC ......................................... 28
Electrical Characteristics
.................... 29
Absolute Maximum Ratings .............................................. 29
DC Characteristics: PIC16C5X-RC, XT, HS, LP (Com) ... 30
DC Characteristics: PIC16C5XI-RC, XT, HS, LP (Ind) ..... 31
DC Characteristics: PIC16C5XI-RC, XT, HS, LP (Auto) .. 32
DC Characteristics: PIC16C5X-RC, XT, HS, LP (Com)
and PIC16C5XI-RC, XT, HS, LP (Ind) ............................... 33
DC Characteristics: PICI6C5XI-RC. XT, HS, LP (Auto) .. 34
AC Characteristics: PIC16C5X-RC. XT. HS, LP (Com)
...... 35
and PIC16C5XI-RC, XT, HS, LP (Ind) and (Auto)
Electrical Structure of Pins
................. 36
Timing Diagrams ..............................
.. ................ 36
DC & AC Charcteristics GraphslTables..
.. .. 37
Packaging Diagrams and Dimensions.
.. 45
18-Lead Plastic Dual In-Line (.300 mil)
....... .45
28-Lead Plastic Dual In-Line (.600 mil)
............ 46
28-Lead Dual In-Line Plastic (300 mil) ............................ .47
18-Lead Plastic Surface Mount
.......... .48
28-Lead Plastic Surface Mount ..................
..49
20-Lead Plastic Surface Mount ....... . ............
.. ... 50
28-Lead Plastic Surface Mount (.209 mil) .
.. ... 51
Package Marking Information .........
.. ... 52
Development Support ...... ........
.. ... 54
PICMASTER: High Performance Universal In-Circuit .
Emulator System ............................................................. 54
Table of Figures
2.1.1
2.2.1
4.1.1
4.2.1
4.2.2A
4.2.2B
4.2.3
4.3.1
4.5.1
5.4.1
5.5.2.1
7.5.1(
9.0.1
12.2.1
12.2.2
12.3.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
16.9.1
16.9.2
17.0.1
17.0.2
17.0.3
18.0.1
18.0.2
18.0.3
18.0.4
18.0.5
18.0.6
18.0.7
18.0.8
18.0.9
18.0.10
18.0.11
18.0.12
18.0.13
18.0.14
18.0.15
18.0.16
18.0.17
18.0.18
18.0.19
18.0.20
18.0.21
18.0.22
20.1.1
20.1.2
20.1.3
PIC16C5X Series Block Diagram
...... 4
Clockllnstruction Cycle ....
.. .................................. 5
RTCC Block Diagram (Simplified) ..
.. ............. 6
PIC16C5X Data Memory Map .......
.. ...................... 7
.. .................. 8
RTCC Timing: INT ClockiNo Prescale ....
RTCC Timing: INT ClockiPrescale 1:2..
.. ...... 8
.. ............ 9
RTCC Timing with External Clock.
Prograrn Memory Organization
... 10
Status Word Register f3
.................... 11
Equivalent Circuit for a Single 1/0 Pin
.......... 13
1/0 PorI Read/Write Timing.
.. ..................... 14
OPTION Register ..........................
.. ........ 15
Block Diagram RTCC/WDT Prescaler ............................. 17
Crystal Operation (or Ceramic Resonator).
.. ............. 24
External Clock Input Operation ........................................ 24
RC Oscillator (RC type only) ........................................... 24
External Power on Reset Circuit ....
.. ...... 24
Brown Out Protection Circuit ............................................ 25
Brown Out Protection Circuit ...............
.. ... 25
Simplified Power on Reset Block Diagram ...........
..26
. .. 26
Using External Reset Input.. .........................
.. ....... 26
Using On-Chip POR (Fast VDD Rise Time) .
Using On-Chip POR (Slow VDD Rise Time) ...................... 27
Electrical Slructure of 1/0 Pins (RA, RB, RC)
.............. 36
Electrical Structure of MCrn and RTCC Pins
....... 36
RTCC Timing
............................................................. 36
Oscillator Start-up Timing (PIC16CXRC) ....
.36
Input/Output Timing for 1/0 Ports (PIC16C5CRC) ............. 36
Typical RC Oscillator Frequency vs. Temperature
... 37
Typical RC Oscillator Frequency vs VDD ...................................... 37
Typical RC Oscillator Frequency vs VDD .............................. 37
Typical RC Oscillator Frequency vs VDD .............................. 38
TypicallpD vs VDD (Watchdog Disabled 25'C)
..... 38
TypicallpD vs VDD (Watchdog Enabled 25'C)
..... 38
Maximum IpD vs VDD (Watchdog Disabled) ...................... 39
Maximum IpD vs VDD (Watchdog Enabled) ...................... 39
VTH (Input Threshold Voltage) of 1/0 Pins vs VDD ............. 39
VIH, ViLlar MCLR, RTCC and OSC1
(in RC Mode) vs VDD...
.. .......................................... ..40
VTH (Input Threshold Voltage) of OSC1 Input in XT,
HS, and LP Modes vs VDD.. .. .................................................... 40
TypicallDD vs Freq Ext Clock, 25'C ......................
.. .. 41
Maximum IDD vs Freq Ext Clock, -40' to +85·C ............... .41
Maximum IDD vs Freq Ext Clock, -55' to +125·C .............. 42
WDT Timer Time-out Period vs VDD ........................................ 42
Transconductance (gm) of HS Oscillator vs VDO ................... 42
Transconductance (gm) of LP Oscillator vs Voo ................... 43
Transconductance (gm) of XT Oscillator vs Voo .................. ..43
10H VS VOH, VDO = 3V .
.......................
.. .. 43
10L VS VOL, VOD = 5V .....
.. ..43
10L vs VOL, Voo = 3V .. .............. ...... ...................... .. .... 44
10H VS VOH, Voo = 5V .....
.. .................... 44
PICMASTER ......................
.. .. 55
PICMASTER System Configuration.
.. .............. 55
PICMASTER Typical Screen .........
.. ..... 56
Table of Tables
1.0.1
2.1.1
4.3.1
4.5.2.1
4.5.2.2
10.0.1
12.2.1
12.2.2
16.2
18.0.1
18.0.2
18.0.3
21.2.1
Overview of PIC16C5X Devices ..............
.. ................. 3
Pin Functions.
.............. .4
Program Counter Stack Width ...
.. ........................ 8
Events Aftecting PDITO Status Bits
..... 12
PDITO Status After Reset .............
.. ............ 12
Instruction Set Summary.
.18
Capacitor Selection for Ceramic Resonators ...
... 24
Capacitor Selection for Crystal Oscillator .........
...24
Pin Descriptions ..........................
.. 29
RC Oscillator Frequencies ..........
.. 38
Input Capacitance for PIC16C54/56 .........
.. 44
Input CapaCitance for PIC16C55/57..
..44
List of Third Party Programmers ...................................... 57
© 1992 Microchip Technology Inc.
DS30D15! - page 2
1-2
PIC®16C5XSeries
1.0 GENERAL DESCRIPTION
Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP
microcontroller while benefiting from the OTP flexibility.
The PIC16C5X from Microchip Technology is a family
low cost, high performance, 8-bit, fully static, EPROM
based CMOS microcontrollers. It employs a RISC-like
architecture with only 33 single word/single cycle instructions to learn. All instructions are single cycle
(200ns) except for program branches which take two
cycles. The PIC16C5X delivers performance an order of
magnitude higher than its competitors in similar price
category. The 12-bit wide instructions are highly sym·
metrical resulting in 2:1 code compression over other 8bit microcontrollers in its class. The easy to use and
easy to remember instruction set reduces development
time significantly.
The PIC16C5X products are supported by an assembler, a software simulator, an in-circuit emulator and a
production quality programmer. All the tools are supported by IBM PC and compatible machines.
1.1 APPLICATIONS
The PIC16C5X series fits perfectly in applications ranging
from high speed automotive and appliance motor control
to low-power remote transmitters/receivers, pointing
devices, and telecom processors. The EPROM technology makes customization of application programs
(transmitter codes, motor speeds, receiver frequencies,
etc.) extremely fast and convenient. The small footprint
packages for through hole or surface mounting make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high performance, ease of use, and I/O flexibility make the PIC16C5X
series very versatile even in areas where no
microcontroller use has been considered before (e.g.
timer functions, replacement of "glue" logic in larger
systems, co-processor applications).
The PIC16C5X products are equipped with special
microcontroller like features that reduce system cost
and power requirements. The power on reset and oscillator start up timer eliminate the need for external reset
circuitry. There are four oscillator configurations to choose
from, including power saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, watchdog timer and code protection features
improves system cost, power and reliablity.
The UV-erasable cerdip-packaged versions are ideal for
code development while the cost-effective One Time
TABLE 1.0.1 - OVERVIEW OF PIC16C5X DEVICES
Part #
EPROM
RAM"
I/Ot
Package Options
PIC16C54 512 x 12
32 x 8
13
18L windowed CERDIP, 18L PDIP, 18L SOIC (300 mil), 20L SSOP
PIC16C55 512 x 12
32 x 8
21
28L windowed CERDIP, 28L PDIP (600 mil), 28L PDIP (300 mil),
28L SOIC (300 mil), 28L SSOP
1K x 12
32 x 8
13
18L windowed CERDIP, 18L PDIP, 18L SOIC (300 mil), 20L SSOP
PIC16C57 2K x 12
80 x 8
21
28L windowed CERDIP, 28L PDIP (600 mil), 28L PDIP (300 mil),
28L SOIC (300 mil), 28L SSOP
PIC16C56
...
t
Including special function registers .
The industrial versions and the HS version operates for VDD range of 4.5 V to 5.5 V (see DC specs) .
Includes RTCC pin.
2.0 ARCHITECTURAL DESCRIPTION
speed with overlapping instruction fetch and execution
cycles. That means that, while one instruction is executed, the following instruction is already being read
from the program memory. A block diagram of the
PIC16C5X series is given in Figure 2.1.1.
2.1 Harvard Architecture
The PIC16C5X single-chip microcomputers are lowpower, high-speed, full static CMOS devices containing
EPROM, RAM, I/O, and a central processing unit on a
single chip.
2.2 Clocking Scheme/Instruction Cycle
The clock input (from pin OSC1) is internally divided by
four to generate four non overlapping quadrature clocks
namely 01, 02, 03 and 04. Internally, PC is incremented every 01, instruction is fetched from program
memory and latched into instruction register in 04. It is
decoded and executed during the following 01 through
04. The clocks and instruction execution flow is shown
in Figure 2.2.1.
The architecture is based on a register file concept with
separate bus and memories for data and instructions
(Harvard architecture). The data bus and memory (RAM)
are 8-bits wide while the program bus and program
memory (EPROM) have a width of 12-bits. This concept
allows a simple yet powerful instruction set designed to
emphasize bit, byte and register operations under high
© 1992 Microchip Technology Inc.
D8300151- page 3
1·3
PIC®16C5X Series
FIGURE 2.1.1 -PIC16C5X SERIES BLOCK DIAGRAM
esc,
9.
OSC2 MCLR
WDTTIME
OUT
"SLEEP"
DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE
FROMW
RAO-RA3
The register file is divided into two functional groups:
operational registers and general purpose registers.
The operational registers include the Real Time Clock
Counter (RTCC) register, the Program Counter (PC),
t~e Status Register, the 1/0 registers (PORTs), and the
File Select Register_ The general purpose registers are
used for data and control information under command of
the instructions.
In addition, special purpose registers are used to control
the 1/0 port configuration, and the prescaler options.
TABLE 2.1.1 - PIN FUNCTIONS
Name
Functl.on
RAO- RA3
RBO- RB?
RCO-RC?
RTCC
MCLR
OSC1
OSC2/CLKOUT
1/0 PORT A
1/0 PORT B
1/0 PORT C (C55/5? only)
Real Time Clock/Counter
Master Clear
Oscillator (input)
Oscillator (output)
Power supply
Ground
No (internal) Connection,
voo
Vss
N/C
RCO-RC7
(PIC'SC551C57
ONLy)
RBO-RB7
2.4 Arithmetic/Logic Unit (ALU)
The 8-bit wide ALU contains one temporary working
register (W Register). It performs arithmetic and Boolean functions between data held in the W Register and
any file register. It also does single operand operations
on either the W register or any file register.
2.3 Data Register File
The 8-bit data bus connects two basic functional elements t"gether: the Register File composed of up to 80
addressable 8-bit registers including the 1/0 Ports, and
an 8-bit wide Arithmetic Logic Unit. The 32 bytes of RAM
are directly addressable while a "banking" scheme, with
banks of 16 bytes each, is employed to address larger
data memories (Figllre 4.2:1). Data can be addressed
direct, or indirect using the file select register (f4).
Immediate data addressing is supported by special
"literal" instructions which load data from program
memory into the W register.
2.5 Program Memory
Up to.512 words of 12-bit wide on-chip program memory
(EPROM) can be directly addressed. Larger program
memories can be addressed by selecting one of up to
four available pages with 512 words each (Figure 4_3.1)_
Sequencing of microinstructions is controlled via the
© 1992 Microchip Technology Inc.
OS300151 - page 4
1-4
PIC®16C5X Series
FIGURE 2.2.1 - CLOCKS/INSTRUCTION CYCLE
01
02
03
I
04
01
02
03
I
04
01
02
03
I
04
I,
OSC1
~,
01
L-_ _ _ _ _ _~V~L_ _ _ _ _ _~y____\L_ _ _ _ _ _ _ _ ,
02
: } Internal
I
03,'_ _ _ _ _1
04
PC
(Program Counter)
Phase
Clocks
~~~~~~~~~;~~~~~~r----====~!~~~~~~~~;~~~~~;~==~~~~~~;I~~==~
L
PC
PC+1
PC+2
OSC2ICLKOUT
(RCMode)
Fetch INST PC
~==:;~~~~c;====~--~~~~~--~
Execute INST (PC-i)
Fetch INST (PC+1)
~
Execute INST (PC)
Program Counter (PC) which automatically increments
to execute in-line programs. Program control operations, supporting direct, indirect, relative addressing
modes, can be performed by Bit Test and Skip instructions, Call instructions, Jump instructions or by loading
computed addresses into the PC. In addition, an on-chip
two-level stack is employed to provide easy to use
subroutine nesting.
Fetch INST (PC+2)
Execute INST (PC+ 1)
3.2 One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and updates. OTP devices have the oscillator type pre-configured by the factory, and they are tested only for this
special configuration (including voltage and frequency
ranges, current consumption). Table 3.2.1 gives an
overview about devices available now and planned for
future release.
3.0 PIC16C5X SERIES OVERVIEW
A wide variety of EPROM and RAM sizes, number of
I/O pins, oscillator types, frequency ranges, and packaging options is available. Depending on application and
production requirements the proper device option can
be selected using the information and tables in this
section. When placing orders, please use the "PIC 16C5X
Product Identification System" on the back page of this
data sheet to specify the correct part number.
The program EPROM is erased, allowing the user to
write the application code into it. In addition, the watchdog timer can be disabled, and/or the code protection
logic can be activated by programming special EPROM
fuses. The sixteen special EPROM bits for ID code
storage are also user programmable.
3.1 UV Erasable Devices
Microchip offers a QTP Programming Service for factory
production orders. This service is made available for
users who chose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices (see
Table 3.2.1) but with all EPROM locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your Microchip Technology sales office for more
details.
3.3 Quick-Turnaround-Production (QTP)
Devices
Four different device versions, as listed in Table 3.1.1,
are available to accommodate the different EPROM,
RAM, and I/O configurations. These devices are optimal
for prototype development and pilot series. The desired
oscillator configuration is EPROM programmable as
"RC", "XT", "HS" or "LP". An erased device is configured
as "RC" type by default. Depending on the selected
oscillator type and frequency, the operating supply voltage must be within the same range as a OTP/QTP part
would be specified for.
The available PIC development tools "PICPROTM and
PICPROTM II can program all PIC16C5X devices for
prototyping and pilot series up to low-volume production.
© 1992 Microchip Technology Inc.
D8300151 - page 5
1-5
PIC®16C5X Series
4.0 OPERATIONAL REGISTER FILES
RTS=1: The clock source for the RTCC or the prescaler, if assigned to it, is the signal on the RTCC
pin. Bit 4 of the OPTION register (RTE) determines, if an increment occurs on the falling
(RTE=1) or rising (RTE=O) edge of the signal
presented to the RTCC pin.
4.1 fO Indirect Data Addressing
This is not a physically implemented register. Addressing
fO calls for the contents of the File Select Register to be
used to select a file register. fO is useful as an indirect
address pointer. For example, in the instruction ADDWF
to, W will add the contents of the register pointed to by
the FSR (f4) to the content of the W Register and place
the result in W.
RTS=O: The RTCC register or its prescaler, respectively, will be incremented with the internal
instruction clock (= Fosc/4). The "RTE" bit in the
OPTION register and the RTCC pin are "don't
care" in this case. However, the RTCC pin
must be tied to VDD or Vss, whatever is convenient, to prevent unintended entering of test
modes and to reduce the current consumption
in low power applications.
If fO itself is read through indirect addressing (i.e. FSR =
Oh), then OOh is read. If fO is written to via indirect
addressing, the result will be a Nap.
As long as clocks are applied to the RTCC (from internal
or external source, with or without prescaler), f1 keeps
incrementing and just rolls over when the value "FFh" is
reached. All increment pulses for f1 are delayed by two
instruction cycles. After writing to f1, for example, no
increment takes place for the following two instruction
cycles. This is independent if internal or external clock
source is selected. If a prescaler is assigned to the
RTCC, the output of the prescaler will be delayed by two
cycles before f1 is incremented. This is true for instructions that either write to or read-modify-write RTCC
(e.g. MOVF f1, CLRF f1). For applications where RTCC
needs to be tested for zero without affecting its count,
use of MOVF f1, W instruction is recommended. Timing
diagrams in Figure 4.2.2 show RTCC read, write and
increment timing.
4.2 f1 Real Time Clock/Counter Register
(RTCC)
This register can be loaded and read by the program as
any other register. In addition, its contents can be
incremented by an external signal edge applied to the
RTCC pin, or by the internal instruction cycle clock
(CLKOUT=foscl4). Figure 4.1.1 is a simplified block
diagram of RTCC.
An 8-bit prescaler can be assigned to the RTCC by
writing the proper values to the PSA bit and the PS bits
in the OPTION register. OPTION register is a special
register (not mapped in data memory) addressable
using the 'OPTION' instruction. See section 7.5 for
details. If the prescaler is assigned to the RTCC,
instructions writing to f1 (e.g. CLRF 1, or BSF1 ,5, ... etc.)
clear the prescaler.
4.2.1 USING RTCC WITH EXTERNAL CLOCK
When external clock input is used for RTCC, it is synchronized with the internal phase clocks. Therefore, the
external clock input must meet certain requirements.
The bit "RTS" (RTCC signal Source) in the OPTION
register determines, if f1 is incremented internally or
externally.
FIGURE 4.1.1· RTCC BLOCK DIAGRAM (SIMPLIFIED)
RTCC
f05C/4
0
0
PIN
SYNC WITH
~
RTE
INTERNAL
CLOCKS
(2 CYCLE DELAY)
RTS
PSA
PS2. PS1, PSO
Notes:
1. Bits, RTE, RTS, PS2, PS1, PSO are located in option register.
2. The prescaler is shared with Watchdog Timer (see Figure 9.0.1).
OS300151 - page 6
© 1992 Microchip Technology Inc.
1-6
PIC®16C5X Series
FIGURE 4.2.1 - PIC16C5X DATA MEMORY MAP
FILE
ADDRESS
7654321
0
00
INDIRECT ADDR. (.)
01
RTCC
02
I AtO IA9
lAS
CALL
RETLW
PC
03
109 8 7 6 5 4 3 2 1 0
I
10 9 8 7 6 543 2 1 0
I-I
STACK 1
STACK 2
STATUS
04
FSR
05
PORTA
06
PORTB
07
-
7 6 5 4 321 0
I TRISA
I
I
PORTCn
08
'"-
09
'-
OA
'"-
OB
fOC
f-
00
f-
OE
GENERAL
PURPOSE
REGISTER
FILE
OPTION
TOANO FROM
REGISTER FILE
VIAALU
W
L
BIT 6, 5 OF FSR: BANK SELECT
(PICI6C57 ONLY)
30
r
o
1°1
00
1
10
I
TRISC
-
r-
OF
-
5 4 3 2 1 0
TRISB
50
70
FROMPROGRAM MEMORY
r
11
12
13
14
15
16
17
18
GENERAL
PURPOSE
REGISTER
FILE
(ALL TYPES)
GENERAL PURPOSE
REGISTER FILE
(PICI6C57 ONLY)
19
lA
lB
lC
10
(BANKO) ("".)
(BANK 1) (""")
(BANK 2) (".")
(BANK 3) (""")
IE
1F
3F
5F
7F
NOT A PHYSICALLY IMPLEMENTED REGISTER. SEE SECTION 4.0 OR DETAILS
(.)
(•• ) FILE 17 IS A GENERAL PURPOSE REG.ISTER ON THE PIC16C54/C56
(""") BANK 0 IS AVAILABLE ON ALL MICROCONTROLLERS WHILE BANK 1 TO BANK 3 ARE ONLY AVAILABLE ON THE
PICI6C57. (SEE SECTION 4.6 FOR DETAILS)
D5300151 - page 7
© 1992 Microchip Technology Inc.
1-7
PIC®16C5X Series
Also there is some delay from the occurance of the
external clock edge to the actual incrementing of RTCC.
Referring to Figure 4.1.1, the synchronization is done
after the prescaler. The output of the prescaler is
sampled twice in every instruction cycle to detect rising
or falling edges. Therefore, it is necessary for PSOUT to
be high foratleast2tosc and low for at least 2tosc where
tosc = oscillator time period.
Delay from external clock edge: Since the prescaler output
is synchronized with the internal clocks, there is a small
delay from the time the external clock edge occurs to the
time the RTCC is actually incremented. Referring to
Figure 4.2.3, the reader can see that this delay is
between 3 tosc and 7 tosc. Thus, for example, measuring the interval between two edges (e.g. period) will be
accurate within ±4 tosc (±200 ns @ 20 MHz).
When no prescaler is used, PSOUT (Prescaleroutput, see
Figure 5) is the same as RTCC clock input and therefore
the requirements are:
TRTH = RTCC high time;:: 2tosc + 20 ns
TRTL = RTCC low time;:: 2tosc + 20 ns
4.3 f2 Program Counter
The program counter generates the addresses for up to
2048 x 12 on-chip EPROM cells containing the program
instruction words (Figure 4.3.1).
When prescaler is used, the RTCC input is divided by the
asynchronous ripple counter-type prescaler and so the
prescaler output is symmetrical.
N.nn
Then: PSOUT high time = PSOUT low time = 2
where TRT = RTCC input period and N = prescale value
(2,4, .... , 256). The requirement is, therefore N.TRT
>
or TRT
> 4 lose N+ 40 ns
2
- 2 tosc + 20 ns,
-
Depending on the device type, the program counter and
its associated two-level hardware stack is 9 - 11-bits
wide.
TABLE 4.3.1 - PROGRAM COUNTER STACK
WIDTH
Part #
The user will notice that no requirement on RTCC high
time or low time is specified. However, if the high time
or low time on RTCC is too small then the pulse may not
be detected, hence a minimum high or low time of 10 ns
is required. In summary, the RTCC input requirements
are:
TRT
RTCC period;:: (4 tosc + 40 ns)/N
TRTH
RTCC high time;:: 10 ns
TRTL
RTCC low time;:: 10 ns
PC width
Stack width
9 bit
10 bit
11 bit
9 bit
10 bit
11 bit
PIC16C54/PIC16C55
PIC16C56
PIC16C57
The program counter is set to all "1"s upon a RESET
condition. During program execution it is auto
incremented with each instruction unless the result of
that instruction changes the PC itself:
FIGURE 4.2.2A - RTCC TIMING: INT CLOCK/NO PRESCALE
'ml~lool~'ml~lool~'ml~lool~'ml~lool~'ml~lool~'ml~lool~lml~loo1~lml~lool~'
I
PC
(PROGRAM
COUNTER)
,
,
I
PC-1
!=iT
RTCC
I
I
I
I
I
I
PC
pc+ 1
PC + 2
PC + 3
PC + 4
PC + 5
INSr.
MOVWFF1
MOVF F1, W
MOVFF1, W
MOVFF1, W
MOVFF1, W
MOVFF1, W
,
,
RT + 1 X
,
,
RT + 2
,
t
,
,
WriteF1
executed
NRT
X
t
Read F1
reads NAT
,
,
NRT
t
X
Read F1
reads NRT
,
,
,
!\IRI + 1 X
t
Read F1 reads
NRT + 1
,
,
,
,
1\1111
+
1
PC + 6
2 X
t
Read F1 reads
NRT +2
1\1111 + 3
,
,
Q
Read F1 reads
,
NRT + 3
FIGURE 4.2.2B - RTCC TIMING: INT CLOCK/PRESCALE 1:2
PC
(PROGRAM
COUNTER)
RTCC
PC-1
I
,
RT
X
Pc
PC+ 1
PC+2
PC+3
PC + 4
PC+5
MOVWFF1
MOVFF1, W
MOVFF1, W
MOVFF1, W
MOVFF1, W
MOVF F1, W
RT + 1
I
X
I
,
NRT
t
WriteF1
Read F1
executed
reads NRT
DS300151 . page 8
t
Read F1
reads NRT
,
PC+6
X
t
I
Read F1
reads NRT
t
Read F1
reads NAT
I
NRT + 1
t
Read F1
reads NRT
© 1992 Microchip Technology Inc,
1-8
PIC®16C5X Series
a)
b)
c)
d)
"GOTO" instructions allow the direct loading of the
lower 9 program counter bits (PC <8:0». In case of
PIC16C56/PIC16C57, the upper two bits of PC
(PC<10:9» are loaded with page select bits PA1,
PAO (bits 6,5 status register). Thus GOTO allows
jump to any location on any page.
"CALL" instructions load the lower 8-bit of the PC
directly while the ninth bit is cleared to "0". The PC
value, incremented by one, will be pushed into the
stack. In case of PIC16C56, PIC16C57, the upper
two bits of PC (PC<10:9» are loaded with Page
Select bits PA1, PAO (bits 6,5 status register).
"RETLW" instructions load the program counter
with the top of stack contents.
If PC is the destination in any instruction (e.g.
MOVWF 2, ADDWF 2, or BSF 2,5) then the computed 8-bit result will be loaded into the low 8-bits of
program counter. The ninth bit of PC will be cleared.
In case of PIC16C56/PIC16C57, PC<1 0:9> will be
loaded with Page Select bits PA 1, PAO (bits 6,5 in
status register).
"200" (page 1). A "GOTO xxx" at "200" will return the
program to address "xxx" on page "0" (assuming thatthe
page preselect bits in file register f3 are "0").
Upon a RESET condition, page 0 is pre-selected while
the program counter addresses the last location in the
last page. Thus, a "GOTO" instruction atthis location will
automatically cause the program to continue in page O.
4.4
S1i.Id
Status bits:
C,DC,Z
Description:
Add the contents 01 the W register to
register "I". II "d" is 0 the result is stored
in the W register. II "d" is 1 the result is
stored back in register "I".
ANDLW
AND Literal and W
Syntax:
ANDLW
k
kkkk
Encoding:
I 1110 I
Words:
1
Cycles:
1
I
kkkk
Operation:
(W .AND. k) ---> W
Status bits:
Z
Description:
The contents 01 W register are AND'ed
with the eight bit literal "k". The result is
placed in the W register.
ANDWF
ANDWwith f
Syntax:
ANDWF
Encoding:
I
Words:
1
Cycles:
1
0001
I
I
Operation:
(W .AND. I) ---> d
Status bits:
Z
Description:
BCF
Syntax:
BSF
Encoding:
I
Words:
1
Cycles:
1
Operation:
1 ---> I(b)
I
AND the W register with register "I". II "d"
is 0 the result is stored in the W register.
II "d" is 1 the result is stored back in
register "I".
BCF
Encoding:
I 0100 I
None
Bit "b" in register "I" is set to 1.
BTFSC
Bit Test, skip if Clear
Syntax:
BTFSC
Encoding:
I 0110 I bbbf I
Words:
1
Words:
1
Cycles:
1
Operation:
0 ---> I(b)
Status bits:
None
Description:
Bit "b" in register "I" is reset to O.
ffff
I,b
ffff
I
Cycles:
1(2)
Operation:
skip iff(b); 0
Status bits:
None
Description:
II bit "b" in register "I" is "0" then the next
instruction is skipped.
Bit Test, skip if Set
Syntax:
BTFSS
Encoding:
I 0111 I bbbf I
Words:
1
I,b
Cycles:
1 (2)
Operation:
skip if I(b) ; 1
ffff
I
Status bits:
None
Description:
If bit "b" in register "I" is "1" then the next
instruction is skipped.
CALL
I
I
Ilbit"b" is "1 ", the next instruction, letched
during the current instruction execution,
is discarded and a NOP is executed instead making this a 2 cycle instruction.
I,b
bbbf
ffff
Description:
Bit Clear f
Syntax:
I,b
I bbbf I
Status bits:
BTFSS
ffff
0101
Ilbit"b"is "0", the next instruction, letched
during the current instruction execution,
is discarded and a NOP is executed instead making this a 2 cycle instruction.
I,d
01df
Bit Set f
I
© 1992 Microchip Technology Inc.
Subroutine Call
Syntax:
,=.C'-'A.::cLL"'-r-_k'---r-_---,
Encoding:
11001
Words:
1
Cycles:
2
Operation:
PC + 1 ---> TOS; k ---> PC<7:0>,
'0' ---> PC<8>, PA2, PAl, PAO --->
PC<11 :9>;
Status bits:
None
I
kkkk
I
kkkk
I
DS30015I· page 19
1-19
PIC®16C5X Series
Description:
CLRF
Clear f and Clear d
Syntax:
Encoding:
DECF
Subroutine call. First, return address (PC
+ 1) is pushed into the stack. The eight bit
value is loaded into PC bits <7:0>. PC bit
9 is cleared. PC <2:0> bits are loaded into
PC <11 :9>. CALL is a two cycle instruction.
CLRF
I,d
I 0000 I OUf I ffff
I
Decrement f
Syntax:
DECF
Encoding:
I 0000 I 11df I ffff
I,d
Words:
1
Cycles:
1
Operation:
(1-1)~d
Status bits:
C,DC,Z
Description:
Decrement register "I". If "d" is 0 the result
is stored in the W register. II "d" is 1 the
result is stored back in register "I".
Decrement f, skip if 0
Words:
Cycles:
Operation:
OOh ~ I, OOh ~ d
DECFSZ
Status bits:
None
Syntax:
DECFSZ
Description:
The contents 01 register "I" are set to O. II
"d" is 0 the contents 01 both data memory
location "I" and W register are set to O. II
"d" is 1 the only contents 01 register "I" are
set to O.
Encoding:
I 0010 Illdf I Uff
Words:
1
Cycles:
1 (2)
Operation:
(I - 1)
~
I,d
I
d; skip il result; 0
CLRW
Clear W Register
Status bits:
None
Syntax:
rC_L_R_W-,_ _-,-_ _-.
Description:
Encoding:
I 0000 I 0100 I 0000
The contents 01 register "I" are decremented. II "d" is 0 the result is placed in
the W register. II "d" is 1 the result is
placed back in register "I". II the result is
o the next instruction is skipped.
I
Words:
Cycles:
Operation:
OOh ~W
Status bits:
Z
If the result is 0, the next instruction,
which is already letched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Description:
W registered is cleared. Zero bit (Z) is set.
CLRWDT
Clear Watchdog Timer
GOTO
Syntax:
CLRWDT
Syntax:
GOTO
Encoding:
I 0000 I 0000 I 0100 I
Encoding:
1
Words:
1
Cycles:
Operation:
OOh ~WDT, 0 ~ WDT prescaler,
1 ~ TO, 1 ~ PD
Description:
CLRWDT instruction resets the watchdog timer.lt also resets the prescaler 01
the WDT. Status bits TO and PD are set.
Syntax:
1
2
Operation:
k
COMF
Words:
1
ffff
I
Cycles:
I
~
d
PC<8:0>, PA2, PA1, PAO
PC<11:9>;
None
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded into
PC bits <1 0:0>. The upper bits 01 PC are
loaded lrom PCLATH <4:3>. GOTO is a
two cycle instruction.
INCF
Increment f
I,d
I 0010 I 01df
~
Status bits:
Complement f
Encoding:
Operation:
Words:
Cycles:
k
101k I kkkk I kkkk I
~
Status bits:
COMF
Unconditional Branch
Syntax:
INCF
Encoding:
I 0010
Words:
1
I,d
1
Status bits:
Z
Cycles:
Description:
The contents 01 register "I" are complemented. II "d" is 0 the result is stored in W.
" "d" is 1 the result is stored back in
register "I".
Operation:
(I + 1)
Status bits:
C,DC,Z
~
10df
ffff
I
d
© 1992 Microchip Technology Inc.
OS300151 - page 20
1·20
PIC®16C5X Series
Description:
The contents of register "f" are incremented. If "d" is 0 the result is placed in
the W register. If "d" is 1 the result is
placed back in register "f".
MOVF
Syntax:
MOVF
f,d
Encoding:
I 0010
OOdf
1
1
INCFSZ
Increment f, skip if 0
Words:
Syntax:
INCFSZ
f,d
Cycles:
Encoding:
I 0011 l
11df
I
nff
I
Movef
Operation:
(f)~d
Z
I ffff
Words:
1
Status bits:
Cycles:
1 (2)
Description:
The contents of register "f" are moved. If
"d" is 0 the result is placed in the W
register. If "d" is 1 the result is placed
back in register "f".
MOVLW
Move Literal to W
~
Operation:
(f + 1)
Status bits:
None
d, skip if result = 0
Description:
The contents of register "f" are incremented. If "d" is 0 the result is placed in
the W register. If "d" is 1 the result is
placed back in register "f". If the result is
othe next instruction is skipped.
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
IORLW
Inclusive OR Literal with W
Syntax:
IORLW
Encoding:
11101
Syntax:
MOVLW
Encoding:
11100
Words:
1
I
k
kkkk
I kkkk
Cycles:
k
Status bits:
None
Description:
The eight bit literal "k" is loaded into W
register.
MOVWF
Move Wto f
k
I kkkk I kkkk
~
Operation:
W
Words:
1
Syntax:
MOVWF
Cycles:
1
Encoding:
I 0000 I
Operation:
(W .OR. k) ~ W
Words:
1
OOlf
I ffff
Status bits:
Z
Cycles:
1
Description:
The contents of the W register are OR'ed
with the eight bit literal "k". The result is
placed in the W register.
Operation:
W~f
Status bits:
None
Description:
Move data from W register to register "f".
IORWF
Inclusive OR W with f
NOP
No Operation
Syntax:
IORWF
I 0001 I OOdf
Syntax:
NOP
Encoding:
Encoding:
I 0000 I 0000 I 0000 I
Words:
1
Cycles:
1
Cycles:
(W
Operation:
No operation
Status bits:
None
Description:
No operation
OPTION
Load Option Register
Operation:
Status bits:
Description:
f,d
ffff
Words:
.OR.f)~d
Z
Inclusive OR the W register with register
"f". If "d" is 0 the result is stored in the W
register. If "d" is 1 the result is stored back
in register "f".
Syntax:
OPTION
Encoding:
I
0000
I 0000 I 0010 I
Words:
Cycles:
© 1992 Microchip Technology Inc.
~
Operation:
W
Status bits:
None
OPTION;
Description:
The contents of the W register is loaded in
the OPTION register.
08300151- page 21
1-21
PIC®16C.5X Series
RETLW
Return Literal to W
Syntax:
RETLW
Encoding:
11000 1 kkkk
Words:
1
Cycles:
2
kkkk
Operation:
k ---+ W; TOS ---+ PC;
Status bits:
None
Description:
The processor is put into SLEEP mode
with the oscillator stopped. See section
on SLEEP mode lor more details.
k
SUBWF
The W register is loaded with the eight bit
literal uk". The program counter is loaded
Irom the top 01 the stack (the return
address). This is a two cycle instruction.
RLF
Rotate Left f through Carry
Syntax:
RLF
Subtract W from f
Syntax:
SUBWF
Encoding:
1 0000 1 10df 1 ffff 1
Words:
1
Cycles:
1
Operation:
(I-W) ---+d
Status bits:
C,DC,Z
;SUBWF Example #1
clrf
movlw
subwf
I,d
Ox20
1
Ox20
;f(20h)~0
;wreg~l
;f(20h)~f(20h)-wreg~0-1~FFh
;Carry=O; Result is negative
Encoding:
1 0011
Words:
1
;SUBWF Example #2
I ---+ d, 1<7> ---+ C, C ---+ d;
movlw
movwf
clrw
subwf
Oldf 1 ffff 1
Cycles:
Operation:
Status bits:
C
Description:
The contents of register "f" are rotated
one bit to the left through the Carry Flag.
If "d" is 0 the result is placed in the W
register. II "d" is 1 the result is stored back
in register "f".
Rotate Right f through Carry
Syntax:
RRF
Words:
1 0011
f,d
OOdf 1 ffff 1
1
Cycles:
Operation:
I ---+ d ---+ C, C ---+ d<7>;
Status bits:
C
Description:
OxFF
Ox20
;f(20h)~FFh
;wreg~O
Ox20
;f(20h)~f(20h)-wreg~FFh-0~FFh
;Carry=l:Result is positive
RRF
Encoding:
f,d
Description:
Subtract (2's complement method) the W
register Irom register "f". If "d" is 0 the
result is stored in the W register. If "d" is
1 the result is stored back in register "f".
SWAPF
Swapf
Syntax:
SWAPF
Encoding:
1 0011 1 10df 1 ffff
Words:
1
I,d
Cycles:
Operation:
The contents of register "I" are rotated
one bit to the right through the Carry Flag.
If "d" is 0 the result is placed in the W
register. If"d" is 1 the result is placed back
in register "f".
SLEEP
1<0:3> ---+ d<4:7>, 1<4:7> ---+ d<0:3>;
Status bits:
None
Description:
The upper and lower nibbles 01 register "I"
are exchanged. If "d" is 0 the result is
placed in W register. If "d" is 1 the result
is placed in register "I".
TRIS
Load TRIS Register
Syntax:
SLEEP
Syntax:
TRIS
Encoding:
1 0000 1 0000 1 0011 1
Encoding:
1 0000
Words:
1
Words:
Cycles:
Operation:
0000 1 Offf 1
Cycles:
0 ---+ PD, 1 ---+ TO;
OOh ---+ WDT, 0 ---+ WDT prescaler;
Status bits:
TO, PD
Description:
The power down status bit (PD) is cleared.
Time-out status bit (TO) is set. Watchdog
Timer and its prescaler are cleared.
Operation:
W ---+ TRIS register I;
Status bits:
None
Description:
TRIS register f (f ~ 5,6 or 7) is loaded with
the contents of the W register.
© 1992 Microchip Technology Inc.
DS300151 - page 22
1-22
PIC®16C5X Series
XORLW
Exclusive OR literal with W
Syntax:
XORLW
Encoding:
11111
Words:
1
I
The status bit "TO" in file register f3 will be cleared upon
a watchdog timer timeout.
The WDT period is a function of the supply voltage,
operating temperature, and will also vary from unitto unit
due to variations in the manufacturing process. Please
refertothe graphs in section 18.0 and DC specs for more
details.
k
kkkk
I
Cycles:
1
Operation:
(W .XOR. k) -> W
kkkk
I
Status bits:
Z
Description:
The contents olthe W register are XOR'ed
with the eight bit literal "k". The result is
placed in the W register.
XORWF
Exclusive OR W with f
11.2 WDT Proaramming Considerations
Syntax:
XORWF
Encoding:
I
0001
In a noisy application environment the OPTION register
can get corrupted. The OPTION register should be
updated at regular intervals.
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max. WDT
prescaler) it may take several seconds before a WDT
timeout occurs.
f,d
1 10df I
ffff
I
Words:
Cycles:
12.0 OSCILLATOR CIRCUITS
1
Operation:
(W .XOR. f) -> d
Status bits:
Z
Description:
Exclusive OR the contents of the W register with register "f". If "d" is 0 the result
is stored in the W register. If "d" is 1 the
result is stored back in register "f".
12.1 Oscillator Types
The PIC16C5X series is available with 4 different oscillator options. On windowed devices, a particular oscillator circuit can be selected by programming the configuration EPROM accordingly. The PIC development tools
(e.g. PICMASTER, PIC-PAK, PICPRO) provide special
commands to select the desired oscillator configuration.
On OTP and QTP devices, the oscillator configuration is
programmed by the factory and the parts are tested only
to the according specifications.
11.0 WATCHDOG TIMER (WDT)
The watchdog timer is realized as a free running on-chip
RC oscillator which does not require any external components. That means that the WDT will run, even if the
clock on the OSC1/0SC2 pins of the device has been
stopped, for example, by execution of a SLEEP instruction. A WDT timeout generates a device RESET condition. The WDT can be permanently disabled by programming a "zero" into a special EPROM fuse which is
not part of the normal program memory EPROM. The
PIC development tools "PICMASTERTM, PIC-PAKTM ",
and "PICPROTM" provide special commands to program
this fuse.
12.2 Crystal Oscillator
The PICI6C5X-XT, -HS, or LP needs a crystal or ceramic resonator connected to the OSCI and OSC2 pins
to establish oscillation (Figure 12.2.1). XT = Standard
crystal oscillator, HS = High speed crystal oscillator. The
series resistor Rs may be required forthe "HS" oscillator,
especially at lower than 20 MHz oscillation frequency. It
may also be required in XT mode with AT strip-cut type
crystals to avoid overdriving.
11.1 WDT Period
12.3 RC Oscillator
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to 2.5
seconds can be realized.
The "CLRWDT" and "SLEEP" instructions clear the
WDT and the prescaler, if assigned to the WDT, and
prevent it from timing out and generating a device
RESET condition.
For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operation
temperature. In addition to this, the oscillator frequency
will vary from unitto unit due to normal process parameter
variation. Furthermore, the difference in lead frame
capacitance between package types will also affect the
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation to due
tolerance of external Rand C components used. Figure
12.3.1 shows how the RIC combination is connected to
the PICI6C5X. For Rext values below 2.2 kOhm, the
© 1992 Microchip Technology Inc.
DS300151- page 23
1-23
PIC®16C5X Series
oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 MOhm), the
oscillator becomes sensitive to noise, humidity and
leakage. Thus, we recommend to keep Rextbetween 5
kOhm and 100 kOhm.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package
lead frame capacitance.
See table in section 18.0 for RC frequency variation from
part to part due to normal process variation. The
variation is larger for larger R (since leakage current
variation will affect RC frequency more for large R) and
for smaller C (since variation of input capacitance will
affect RC frequency more).
See characteristics in section 18.0 for variation of oscillator frequency due to VDD for given RextlCext values
as well as frequency variation due to operating temperature for given R, C, and VDD values.
Higher capacitance increases the stability of oscillator
but also increases the start-up time. These values are
for design guidance only. Since each resonator has its
own characteristics, the user should consult the resonator
manufacturer for appropriate values of external components.
FIGURE 12.2.2· EXTERNAL CLOCK INPUT
OPERATION (HS, XT, or LP TYPES ONLY)
CLOCK FROM
EXT. SYSTEM
~eI
- IJRsJ=
_
c=J
XTAL
C2
I
r
,
:
I
I
\
't/
PIC16C5X
/L-
L r J
I
I
I
Freq
C1
C2
LP
XT
32 KHz
100 KHz
200 KHz
455 KHz
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
20 MHz
15 pF
15 - 30 pF
15 - 30 pF
15 -30 pF
15 - 30 pF
15 pF
15 of
15 pF
15 pF
15 pF
15 pF
200 - 300 pF
100 - 200 pF
15 - 100 pF
15-30pF
15 pF
15 of
15 pF
15 pF
15 pF
Higher capacitance increases the stability of oscillator
but also increases the start-up time. These values are
for design guidance only. Rs may be required in HS
mode as well as XT mode to avoid overdriving crystals
with low drive level speCification. Since each crystal has
its own characteristics, the user should consult the
crystal manufacturer for appropriate values of external
components.
L 1
I
I , __ 1- ...
:
Osc
Type
HS
OSC1
I
OSC2
TABLE 12.2.2· CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
FIGURE 12.2.1· CRYSTAL OPERATION
(OR CERAMIC RESONATOR) (HS, XT OR
LP TYPES ONLY)
-.- - -,
PIC16C5X
OPEN~
The oscillator frequency, divided by 4, is available on the
OSC2/CLKOUT pin, and can be used for test purposes
or to synchronize other logic (see Figure 2.2.1 for
timing).
..
OSC1
SLEEP
FIGURE 12.3.1· RC OSCILLATOR (RC
TYPE ONLY)
- - .. - - - ..... TO INTERNAL
LOGIC
Rs may be required in HS and XT modes for AT strip-cut
crystals to avoid overdriving. See Tables 12.2.1 and 12.2.2
for recommended values of C1, C2 per oscillator type and
frequency.
VDD
Rex!
Cex!
TABLE 12.2.1· CAPACITOR SELECTION
FOR CERAMIC RESONATORS
Vss
0
±
=
OSC1
PIC16C5XRC
~ OSC2/CLKOUT
Fosc/4
Oscillator
Type
Resonator
Frequency
XT
455 KHz
2.0 MHz
4.0 MHz
8.0 MHz
HS
Capacitor Range
C1 = C2
150 - 330 pF
20 - 330 pF
20 - 330 pF
20 - 200 pF
DS300151 - page 24
© 1992 Microchip Technology Inc.
1-24
PIC®16C5X Series
13.0 OSCILLATOR START-UP TIMER
(OST)
FIGURE 13.1.1 - EXTERNAL POWER
ON RESET CIRCUIT
Voo
Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a
stable oscillation. An on-chip oscillator start-up timer is
provided which keeps the device in a RESET condition
for approximately 18 ms after the voltage on the MCLR
pin has reached a logic high (VIHMC) level. Thus, external RC networks connected to the MCLR input are not
required in most cases, allowing for savings in costsensitive and/or space restricted applications.
The OST will also be triggered upon a watchdog timer
timeout. This is particularly important for applications
using the WDT to awake the PIC16C5X from SLEEP
mode automatically.
The OST is not adequate for low frequency crystals
which require much longer than 18 ms to start up and
stabilize.
0lt- MG'"
::r
=-
C
PIC16C5X
Notes:
1. External power on reset circuit is required only if Voo
power-up slope is too slow or if a low frequency
crystal oscillator is being used that need a long
start-up time. The diode D helps discharge the
capacitor quickly when VDD powers down.
2. R < 40 KQ must be observed to make sure that
voltage drop across R does not exceed 0.2 V (max
leakage current spec on MCLR pin is 5 ~A). A
larger voltage drop will degrade VIH level on MCLR
pin.
3. R1 = 100Q to 1KQ will limit any current flowing
into MCLR from external capacitor C in the
event of MCLR pin breakdown due to ESD or
13.1 Power On Reset (POR)
EOS.
The PIC16C5X incorporates an on chip Power On Reset
(POR) circuitry which provides internal chip reset for
most power-up situations. To use this feature the user
merely needs to tie MCLR pin to VDD. A simplified block
diagram of the on-Chip power on reset circuit is shown in
Figure 13.1.4. The power on reset circuit and the
oscillator start-up timer circuit are closely related. On
power-up the reset latch is set and the start-up timer (see
Figure 13.1.4) is reset. The start-up timer begins counting once it detects MCLR to be high. After the time-out
period, which is typically 18 ms, it will reset the resetlatch and thus end the on-chip reset signal.
FIGURE 13.1.2 - BROWN OUT PROTECTION
CIRCUIT
Voo --_._--_._---jVoo
33 K
MCLR
PIC16C5X
Figures 13.1.5 and 13.1.6 are two power-up situations
with relatively fast rise time on VDD. In Figure 13.1.5,
VDD is allowed to rise and stabilize before bringing
MCLR high. The chip will actually come out of reset tOST
ms after MCLR goes high. In Figure 13.1.6, the on chip
power-on reset feature is being utilized (MCLR and VDD
are tied together). The VDD is stable before the startup
timer times out and there is no problem in getting a
proper reset. Figure 13.1.7 depicts a potentially problematic situation where VDD rises too slowly. In this
situation, when the start-up timer times out, VDD has not
reached the VDD (min) value and the chip is therefore not
guaranteed to function correctly.
Notes:
1. This circuit will activate reset when VDD goes
below (VZ + 0.7 V) where VZ = Zener voltage.
FIGURE 13.1.3 - BROWN OUT PROTECTION
CIRCUIT
Voo
Voo
R1
41
0--
R2
MCLR
R3
~
-=--
To summarize, the on chip power-on reset is guaranteed
to work if the rate of rise of VDD is no slower than 0.05 V/
ms. It is also necessary thatthe VDD starts from OV. The
on chip power on reset is also not adequate for low
frequency crystals which require much longer than 18
ms to start up and stabilize. For such situations, we
recommend that external RC circuits are used for longer
power on reset.
PIC16C5X
Notes:
1. This brown circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is
below a certain level such that:
VDD. _R_1_ = 0.7 V.
R1 + R2
DS300151 - page 25
© 1992 Microchip Technology Inc.
1-25
PIC®16C5X Series
FIGURE 13;1.4· SIMPLIFIED POWER ON RESET BLOCK DIAGRAM
paR (POWER-ON RESET)
POWER·UP
DETECT
voo
WOT TIME-OUT
- - - - ; L . . . -__
MCLR
PIN
r-----~--,----,f_'R-=E=S-=ET-'-*__I S
ON-CHIP
RCOSC
8-BIT ASYNCH
RIPPLE COUNTER
(START-UP TIMER)
1-------1 R
Q
QI-----~
CHIP RESET
FIGURE 13.1.5· USING EXTERNAL RESET INPUT
INT''::-=-= _-= _-~=_-~=_~ -/~l= = = = = - _/f_+I_______
---'_+-1_no_te_l_ _ __
\f-:
~ tOST ---.j
OST TIME-OUT
INTERNAL RESET
L- tOST - !
_______________' ____~I~~I
r
____________~II
I
Note 1: The tost time-out is invoked every time the chip comes out of reset.
FIGURE 13.1.6· USING ON·CHIP POR (FAST VDD RISE TIME)
Voo
MCLR
-----"y
----~~~-------------------------'h!--:- - - - - - - - - - - - - - - - - - - ~tOST----+f_'1_ _ _ _ _ _ _ _ _ _ _ _ _ __
INTERNAL paR _ _ _ _
OSTTIME-OUT - - - - - - - - - - - - - - '
INTERNAL RESET - - - ' - - - - - - - ' - - - - - - - '
© 1992 Microchip Technology Inc.
OS300151- page 26
1-26
PIC®16C5X Series
FIGURE 13.1.7 - USING ON-CHIP POR (SLOW Voo RISE TIME)
5V
VDD
INTERNAL POR
OV
~
------~---------------
----------'nf-i- - - - - - + - - - - - - - - - - - - - - -
itOST-r-;- - - - - - - - - - - - - - - OST TIME-OUT - - - - - - - - - - - - - - - '
INTERNAL RESET - - - - - - - - - - - - - - - '
When VIlD rises slowly, the internal time-out period expires long before VIlD has reached its final
value. In this example, the chip will reset properly if, and only if, V1;;, VDDMIN.
NOTE: Some applications may require external R/C
networks on the MCLR pin in order to allow for oscillator
startup times longer than one OST period. In this case,
a WOT wake up from power down mode is not recommended, because a RESET generated by a WOT time
out does not discharge the external capacitor, and the
PIC will be in RESET only for the oscillator start-up timer
period.
14.0 POWER DOWN MODE (SLEEP)
The power down mode is entered by executing a SLEEP
instruction.
If enabled, the watchdog timer will be cleared but keeps
running, the bit "PO" in the status register (f3) is cleared,
the "TO" bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP command was executed (driving high, low, or hiimpedance).
For lowest current consumption in this mode, all I/O pins
should be either at Voo, or Vss, with no external circuitry
drawing current from the I/O pin. I/O pins that are in the
High-Z mode should be pulled high or low externally to
avoid switching currents caused by floating inputs. The
RTCC input should also be at Voo or Vss for lowestcurrent
consumption.
The MCLR pin must be at VIHMC.
15.0 CONFIGURATION FUSES
The configuration EPROM consists of four EPROM
fuses which are not part of the normal EPROM for
program storage.
Two are for the selection of the oscillator type, one is the
watchdog timer enable fuse, and one is the code protection fuse.
The PIC development tools (PICMASTERTM,
PICPAK-IITM, PICPROTM, PICPRO II and PRO MASTER)
allow the setting of these with special commands.
OTP or aTP devices have the oscillator configuration
programmed by the factory and the parts are tested
accordingly. The packages are marked with the suffixes
"XT", "RCM, "HS" or "LP" following the part number to
identify the oscillator type and operating range.
14.1 Wake-Up
The device can be awakened by a watchdog timer
timeout (if it is enabled) or an externally applied "low"
pulse at the MCLR pin. In both cases the PIC will stay in
RESET mode for one oscillator start-up timer period
(triggered from rising edge on MCLR or WOT timeout)
before normal program execution resumes.
15.1 Customer ID Code
The PIC16C5X series has 16special EPROM bits which
are not part of the normal program memory. These bits
are available to the user to store an Identifier (10) code,
checksum, or other informative data. They cannot be
accessed during normal program execution. The
PIC16C5X programmers (e.g. PICPRO or PICPRO II)
provide special commands to read or write these 10 bits.
The "PO" bit in the STATUS register, which is set to one
during power on , but cleared by the "SLEEP" command,
can be used to determine ifthe processor was powered
up or awakened from the power down mode (Table
4.5.1.2). The TO bit in the Status register can be used
to determine, ifthe "wake up" was caused by an external
MCLR signal or a watchdog timer time out.
DS300151 - page 27
© 1992 Microchip Technology Inc.
1-27
PIC®16C5X, Series
15.2 Code Protection
152 1 VERIFYING A COPE-PROTECTED PIC
The program code written into the EPROM can be
protected by programming the code protection fuse with
When code protected verifying any program memory
location will read a scrambled output which looks like
"OOOOOOOOXXXX" (binary) where X is 1 or O. To verify a
device after code protection, fOllow this procedure:
a. First, program and verify a good device without code
protecting it.
b. Next, blow its code protection fuse and then load its
contents in a file.
c. Verify any code-protected PIC against this file.
When code protected, the contents of the program
EPROM cannot be read out in a way that the program
code can be reconstructed. In addition, all memory
locations starting at 040h and above are protected
against programming.
It is still possible to program locations OOOh - 03Fh, the
ID locations and the configuration fuses.
Note that the configuration fuses and the ID bits can still
be read, even if the code protection logic is active.
© 1992 Microchip Technology Inc.
D5300151 - page 28
1-28
PIC®16C5X Series
16.0 ELECTRICAL CHARACTERISTICS
'Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation ofthe device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
16.1 Absolute Maximum Ratings'
Ambient temperature under bias ........ -SS·C to + 12S·C
Storage Temperature ....................... - 6S·C to + 1S0·C
Voltage on any pin with respect to Vss
(except Voo and MCLR) ................ -0.6V to Voo +0.6V
Voltage on Voo with respect to Vss ............... 0 to +9.S V
Voltage on MCLR with respect to Vss
(Note 2) ........................................................ 0 to +14 V
Total power Dissipation (Note 1) .................... 800 mW
Max. Current out of Vss pin ............................. 1S0 mA
Max. Current into Voo pin .................................. SO mA
Max. Current into an input pin ........................ ±SOO IlA
Max. Output Current sinked by any 1/0 pin ........ 2S mA
Max. Output Current sourced by any 1/0 pin ..... 20 mA
Max. Output Current sourced by a single
1/0 port (Port A, B, or C) ................................... .40 mA
Max. Output Current sinked by a single
1/0 port (Port A, B, or C) ..................................... SOmA
Notes: 1. Total power dissipation should not exceed 800
mW for the package. Power dissipation is
calculated as follows:
Pdis = Voo x {Ioo - L loh} + L {(Voo-Voh) x loh}
+ L(Vol x 101)
2. Voltage spikes below Vss at the MCLR pin,
inducing currents greater than aOmA, may
cause latCh-Up. Thus, a series resistor of SO100n should be used when applying a "low'
level to the MCLR pin rather than pulling this
pin directly to Vss.
TABLE 16.2 - PIN DESCRIPTIONS
Name
Function
Observation
RAO - RA3
RBO - RB7
RCO - RC7
RTCC
1/0 PORT A
1/0 PORT B
1/0 PORT C
4 inputloutput lines.
a input/output lines.
a input/output lines, (PIC16CSS/CS7 only).
Schmitt Trigger Input.
Clock input to RTCC register. Must be tied to Vss or voo if
not in use to avoid unintended entering of test modes and
to reduce current consumption.
Schmitt Trigger Input.
A "Low" voltage on this input generates a RESET condition
for the PIC16CSX microcontroller.
A riSing voltage triggers the on-chip oscillator start-up timer
which keeps the chip in RESET mode for about 1ams. This
input must be tied directly, or via a pull-up resistor, to Voo.
"XT", "HS" and "LP" devices: Input terminal for crystal,
ceramic resonator, or external clock generator.
"RC" devices : Driver terminal for external RC combination
to establish oscillation.
For "XT", "HS" and "LP" devices: Output terminal for crystal
and ceramic resonator. Do not connect any other load to
this output. Leave open if external clock generator is used.
For "RC" devices: A "CLKOUT" signal with a frequency of
114 Fosc1 is put out on this pin.
--
Real Time Clock/Counter
MCLR
Master Clear
OSC1
Oscillator (input)
OSC2/CLKOUT
Oscillator (output)
Voo
vss
Power supply
Ground
No (internal) Connection
N/C
DS300151 - page 29
© 1992 Microchip Technology Inc.
1-29
PIC®16C5X Series
16.3 DC CHARACTERISTICS: PIC16C5X-RC, XT, HS, LP (COMMERCIAL)
DC CHARACTERISTICS,
POWER SUPPLY PINS
Standard Operating Conditions
o ~ TA ~ +70"C, unless otherwise stated
Operating temperature
Operating voltage Voo = 3.0V to 5.5V unless otherwise stated
Typ
Characteristic
Supply Voltage
PIC16C5X-XT
PIC16C5X-RC
PIC16C5X-HS
PIC16C5X-LP
RAM Data Retention
Voltage (Note 3)
voo start voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 2)
PIC16C5X-XT
PIC16C5X-RC (Note 5)
PIC16C5X-HS
PIC16C5X-LP
Power Down Current
(Note 4)
PIC16C5X
Sym
Min
Vooxt
Voorc
Voohs
Voolp
VOR
3.0
3.0
4.5
2.5
VPOR
Svoo
Max
Units
6.25
6.25
5.5
6.25
1.5
V
V
V
V
V
Fasc = DC to 4 MHz
Fasc = DC to 4 MHz
Fasc = DC to 20 MHz
Fasc = DC to 40 KHz
Device in SLEEP mode
Vss
V
Vlms
See section 13.1 for details on power on
reset
See section 13.1 for details on power on
(Note 1)
0.05-
Conditions
looxt
loorc
loohs1
loohs2
loolp
1.8
1.8
4.8
9.0
15
3.3
3.3
10
20
32
mA
mA
mA
mA
!lA
Fasc = 4 MHz, Voo = 5.5V
Fasc = 4 MHz, Voo = 5.5V
Fasc =10 MHz, Voo = 5.5V
Fasc = 20 MHz, Voo = 5.5V
Fasc = 32 KHz, Voo=3.0V, WDT disabled
Ipo1
Ipo2
4
0.6
12
9
!lA
!lA
Voo = 3.0V, WDT enabled
Voo = 3.0V, WDT disabled
- These parameters are based on characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Data in the column labeled "Typical" is based on characterization results at 25"C. This data is for deSign
guidance only and is not tested for, or guaranteed by Microchip Technology.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the
current consumption.
a) The test conditions for all 100 measurements in active operation mode are:
OSC1 =external square wave, from rail to rail; all 1/0 pins tristated, pulled to Voo, RT = Voo, MCLR = Voo; WDT
enabledldisabled as specified.
b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode.
This is the limit to which Voo can be lowered in SLEEP mode without losing RAM data.
The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all 1/0 pins in hi-impedence state and tied to Voo and Vss.
Does not include current through Rex!. The current through the resistor can be estimated by the formula
Ir = Voo/2Rext (mA) with Rext in kOhm.
© 1992 Microchip Technology Inc.
DS300151· page 30
1-30
PIC®16C5X Series
16.4 DC CHARACTERISTICS: PIC16C5XI-RC, XT, HS, LP (INDUSTRIAL)
Standard Operating Conditions
DC CHARACTERISTICS,
POWER SUPPLY PINS
Operating temperature -40"; TA"; +85"C, unless otherwise stated
Operating voltage Voo = 3.5V to 5.5V unless otherwise stated
Characteristic
Supply Voltage
PIC16C5X-XT
PIC16C5X-RC
PIC16C5X-HS
PIC16C5X-LP
RAM Data Retention
Voltage (Note 3)
voo start voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 2)
PIC16C5X-XT
PIC16C5X-RC (Note 5)
PIC16C5X-HS
PIC16C5X-LP
Power Down Current
(Note 4)
PIC16C5X
Sym
Min
Vooxt
Voorc
Voohs
Voolp
VOR
3.0
3.0
4.5
2.5
VPOR
Svoo
Typ
(Note 1)
Max
6.25
6.25
5.5
6.25
Units
Conditions
1.5
V
V
V
V
V
Fasc = DC to 4 MHz
Fasc = DC to 4 MHz
Fasc = DC to 20 MHz
Fasc = DC to 40 KHz
Device in SLEEP mode
Vss
V
See section 13.1 for details on power on
reset
See section 13.1 for details on power on
reset
V/ms
0.05'
looxt
loorc
loohs1
loohs2
IODlp
1.8
1.8
4.8
9.0
19
3.3
3.3
10.0
20.0
40
mA
mA
mA
mA
Ipo1
IPD2
5
0.8
14
12
~A
~A
~A
Fasc =
Fasc =
Fasc =
Fasc =
Fasc =
4 MHz, Voo = 5.5V
4 MHz, Voo = 5.5V
10 MHz, Voo = 5.5V
20 MHz, VOD = 5.5V
32 KHz, VDD = 3.0V, WDT disabled
VDO = 3.0V, WDT enabled
VDO = 3.0V, WDT disabled
, These parameters are based on characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Data in the column labeled "Typical" is based on characterization results at 25"C. This data is for design
guidance only and is not tested for, or guaranteed by Microchip Technology.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the
current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSCl = external square wave, from rail to rail; all 1/0 pins tristated, pulled to Voo, RT = VDD, MCLR = VOD; WDT
enabledldisabled as specified.
b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode.
This is the limit to which VOD can be lowered in SLEEP mode without losing RAM data.
The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all 1/0 pins in hi-impedence state and tied to VOO and Vss.
Does not include current through Rext. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (mA) with Rext in kOhm.
DS300151 - page 31
© 1992 Microchip Technology Inc.
1-31
PIC®16C5X Series
16.5 DC CHARACTERISTICS: PIC16C5XI-RC, XT, HS, LP (AUTOMOTIVE)
Standard Operating Conditions
DC CHARACTERISTICS,
POWER SUPPLY PINS
Operating temperature -40 ~ TA ~ + 125'C, unless otherwise stated
Operating voltage Voo = 3.5V to 5.5V unless otherwise stated
Characteristic
Supply Voltage
PIC16C5X-XT
PIC16C5X-RC
PIC16C5X-HS
PIC16C5X-LP
RAM Data Retention
Voltage (Note 3)
Voo start voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 2)
PIC16C5X-XT
PIC16C5X-RC (Note 5)
PIC16C5X-HS
PIC16C5X-LP
Power Down Current
(Note 4)
PIC16C5X
Sym
Min
Vooxt
Voorc
VODhs
VDDlp
VDR
3.25
3.25
4.5
2.5
VPOR
Svoo
Typ
(Note 1)
Max
6.0
6.0
5.5
6.0
Units
Conditions
1.5
V
V
V
V
V
Fosc = DC to 4 MHz
Fosc = DC to 4 MHz
Fosc = DC to 16 MHz
Fosc = DC to 40 KHz
Device in SLEEP mode
Vss
V
See section 13.1 for details on power on
reset
See section 13.1 for details on power on
reset
0.05*
V/ms
looxt
loorc
IDDhs1
IDDhs2
IDDlp
1.8
1.8
4.8
9.0
25
3.3
3.3
10.0
20.0
55
mA
mA
mA
mA
/-LA
Fosc
Fosc
Fosc
Fosc
Fosc
= 4 MHz, Voo = 5.5V
= 4 MHz, VOD = 5.5V
= 10 MHz, Voo = 5.5V
= 16 MHz, VDD = 5.5V
= 32 KHz, VOD = 3.25V, WDT disabled
IpD1
IPD2
5
0.8
22
18
/-LA
/-LA
VDO = 3.25V, WDT enabled
Voo = 3.25V, WDT disabled
* These parameters are based on characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Data in the column labeled "Typical" is based on characterization results at 25'C. This data is for design
guidance only and is not tested for, or guaranteed by Microchip Technology.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the
current consumption.
a) The test conditions for all 100 measurements in active operation mode are:
OSC1= external square wave, from rail to rail; all I/O pins tristated, pulled to VOD, RT = Voo, MCLR = VOD; WDT
enabled/disabled as specified.
b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode.
This is the limit to which Voo can be lowered in SLEEP mode without losing RAM data.
The power down current in .SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to Voo and Vss.
Does not include current through Rext. The current through the resistor can be estimated by the formula
Ir = Voo/2Rext (mA) with Rext in kOhm.
DS30015! - page 32
© 1992 Microchip Technology Inc.
1-32
PIC®16C5X Series
16.6 DC CHARACTERISTICS:
PIC16C5X-RC, XT, HS, LP (COMMERCIAL)
PIC16C5XI-RC, XT, HS, LP (INDUSTRIAL)
DC CHARACTERISTICS,
ALL PINS EXCEPT POWER SUPPLY
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40 < TA < +85'C for industrial
and O'C ~ TA ~ +70'C for commercial
Operating voltage Voo range as described in DC spec tables
16.3 and 16.4
Characteristic
Input Low Voltage
I/O ports
MCLR (Schmitt trigger)
RTCC (Schmitt trigger)
OSCl (Schmitt trigger)
OSCl
Input High Voltage
I/O ports
--
MCLR (Schmitt trigger)
RTCC (Schmitt trigger)
OSCl (Schmitt trigger)
OSCl
Input Leakage Current
(Notes 3, 4)
I/O ports
MCLR
MCLR
RTCC
OSCl
Output Low Voltage
I/O Ports
OSC2/CLKOUT
(PIC16C5X-RC)
Output High Voltage
I/O Ports (Note 4)
OSC2/CLKOUT
(PIC16C5X-RC)
Sym
Min
Typ
(Note 1)
Max
Units
Conditions
VIL
VILMC
VILRT
VILOSC
VILOSC
Vss
Vss
VSf:;
Vss
Vss
0.2 Voo
0.15 Voo
0.15 Voo
0.15 Voo
0.3 Voo
V
V
V
V
V
VIH
VIH
VIH
VIHMC
VIHRT
VIHOSC
VIHOSC
0.45 Voo
2.0
0.36 Voo
0.85 Voo
0.85 Voo
0.85 Voo
0.7 Voo
Voo
Voo
Voo
Voo
Voo
Voo
Voo
V
V
V
V
V
V
V
For all Voo (Note 6)
4.0 V < Voo ~ 5.5 V (Note 6)
Voo > 5.5 V
IlL
-1
0.5
+1
~A
IILMCL
IILMCH
IILRT
IILOSC1
-5
0.5
0.5
0.5
+5
+3
+3
~A
Vss ~ VPIN ~ Voo,
Pin at hi-impedance
VPIN = Vss + 0.25V
VPIN = Voo
Vss ~ VPIN ~ Voo
Vss ~ VPIN ~ voo ,
PIC16C5X-XT, HS, LP
0.6
0.6
V
V
IOL = 8.7 mA, Voo = 4.5V
IOL = 1.6 mA, Voo = 4.5V
V
V
IOH = -5.4 mA, Voo = 4.5V
IOH = -1.0 mA, Voo = 4.5V
-3
-3
~A
VOL
VOL
VOH
VOH
Voo-0.7
Voo-0.7
~A
~A
Pin at hi-impedance
PIC16C5XRC only (Note 5)
PIC16C5X-XT, HS, LP
PIC16C5X-RC only (Note 5)
PIC16C5X-XT, HS, LP
For Voo ~ 5.5V
Note 1: Data in the column labeled "Typical" is based on characterization results at 25' C. This data is for design guidance
only and is not tested for, or guaranteed by Microchip Technology.
Note 2 : Total power dissipation as stated under absolute maximum ratings must not be exceeded.
Note 3 : The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Note 4 : Negative current is defined as coming out of the pin.
Note 5 : For PIC16C5XRC devices, the OSCl pin is a Schmitt trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
Note 6: The user may use better of the two specifications.
OS300151 - page 33
© 1992 Microchip Technology Inc.
1-33
PIC®16C5X Series
16.7 DC CHARACTERISTICS:
PIC16C5X-RC, XT, HS, LP (AUTOMOTIVE)
DC CHARACTERISTICS,
ALL PINS EXCEPT POWER SUPPLY
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40 < TA < +125"C
Operating voltage VDD range as described in DC spec tables
16.3 and 16.4
Characteristic
Input Low Voltage
I/O ports
MClR (Schmitt trigger)
RTCC (Schmitt trigger)
OSC1 (Schmitt trigger)
OSC1
Input High Voltage
I/O ports
MClR (Schmitt trigger)
RTCC (Schmitt trigger)
OSC1 (Schmitt trigger)
OSC1
Input Leakage Current
(Notes 3, 4)
I/O ports
Sym
Min
Max
Units
VIL
VILMC
VILRT
VILOSC
VILOSC
Vss
Vss
Vss
Vss
Vss
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
VIH
VIH
VIH
VIHMC
VIHRT
VIHOSC
VIHOSC
0.45 VDD
2.0
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
D.? VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
Conditions
Pin at hi-impedance
PIC16C5XRC only (Note 5)
PIC16C5X-XT, HS, lP
For all VDD (Note 6)
4.0 V < VDD ~ 5.5 V (Note 6)
VDD > 5.5 V
PIC16C5X-RC only (Note 5)
PIC16C5X-XT, HS, lP
For Voo
IlL
-1
MClR
MClR
RTCC
OSC1
IILMCL
IILMCH
IILRT
IiLOSC1
-5
Output Low Voltage
I/O Ports
OSC2/ClKOUT
(PIC16C5X-RC)
VOL
VOL
Output High Voltage
110 Ports (Note 4)
OSC2/ClKOUT
(PIC16C5X-RC)
VOH
VOH
--
Typ
(Note 1)
-3
-3
~
5.5V
0.5
+1
0.5
0.5
0.5
+5
+3
+3
f.lA
f.lA
f.lA
0.6
0.6
V
V
IOL = 8.? mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V
f.lA
f.lA
VDD-O.?
VDD-O.?
Vss ~ VPIN ~ VDD.
Pin at hi-impedance
VPIN = Vss + 0.25V
VPIN = VDD
vss ~ VPIN ~ VDD
Vss ~ VPIN ~ VDD ,
PIC16C5X-XT, HS, lP
Note 1: Data in the column labeled "Typical" is based on characterization results at 25" C. This data is for design guidance
only and is not tested for, or guaranteed by Microchip Technology.
Note 2 : Total power dissipation as stated under absolute maximum ratings must not be exceeded.
Note 3 : The leakage current on the MClR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Note 4 : Negative current is defined as coming out of the pin.
Note 5 : For PIC16C5XRC devices, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
Note 6: The user may use better of the two specifications.
08300151- page 34
© 1992 Microchip Technology Inc.
1-34
PIC®16C5X Series
16.8 AC CHARACTERISTICS:
AC CHARACTERISTICS
PIC16C5X-RC, XT, HS, LP (COMMERCIAL)
PIC16C5XI-RC, XT, HS, LP (INDUSTRIAL)
PIC16C5XI-RC, XT, HS, LP (AUTOMOTIVE)
Standard Operating Conditions (unless otherwise stated)
Operating temperature TA = -40'C to +85'C (industrial),
TA = -40'C to +125'C (automotive) and O'C ~ TA ~ +70'C (commercial)
Operating voltage VDD range as described in DC spec tables 16.3 and 16.4
Characteristic
External CLOCKIN
Frequency (Note 2)
Oscillator Frequency
(Note 2)
Instruction Cycle Time
(Note 2)
External Clock in Timing
(Note 4)
Clock in (OSC1) High or Low Time
XT oscillator type
LP oscillator type
HS oscillator type
Clock in (OSC1) Rise or Fall Time
XT oscillator type
LP oscillator type
HS oscillator type
RESET Timing
MCLR Pulse Width (low)
RTCC Input Timing, No Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Input Timing, With Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Period
Watchdog Timer Timeout Period
(No Prescaler)
Dscillation Start-up Timer Period
I/D Timing
liD Pin Input Valid Before
CLKOUT" (RC Mode)
liD Pin Input Hold After
CLKOUT.. (RC Mode)
liD Pin Output Valid After
CLKOUTO (RC Mode)
Sym
Min
Typ
(Note 1)
Max
Units
4
4
20
16
40
4
4
20
16
40
DC
DC
DC
DC
MHz
MHz
MHz
MHz
KHz
MHz
MHz
MHz
MHz
KHz
Conditions
FOSCRC
FOSCXT
FOSCHS1
FOSCHS2
FOSCLP
FOSCRC
FOSCXT
FOSCHS1
FOSCHS2
FOSCLP
TCYRC
TCYXT
TCYHS
TCYLP
DC
DC
DC
DC
DC
DC
0.1
4
4
DC
1.0
1.0
0.2
100
TCKHLXT
TCKHLLP
TCKHLHS
50'
2*
20*
~
TCKRFXT
TCKRFLP
TCKRFHS
25*
50*
25*
ns
ns
ns
TMCL
100*
ns
TRTH
TRTL
0.5 TcY+ 20'
0.5 TcY+ 20'
ns
ns
Note 3
Note 3
TRTH
TRTL
TRTP
10*
10'
ns
ns
ns
Note 3
Note 3
Note 3. Where N = prescale
value (2,4, ... , 256)
ICY + 40
N
4/FosCRC
4/FoscxT
4/FosCHS
4/FosCLP
~
~
~
~
RC mode
XT mode
I;JS mode
HS mode
LP mode
RC mode
XT mode
HS mode
HS mode
LP mode
RC mode
XT mode
HS mode
LP mode
(Com/lnd)
(Automotive)
(Com/lnd)
(Automotive)
ns
ns
,
TWOT
TOST
9'
9'
Tos
0.25 TcY+ 30'
ns
TOH
0'
ns
18'
18'
Tpo
30'
30'
40'
, Guaranteed by characterization, but not tested.
ms
ms
Voo = 5.0V
Voo = 5.0V
ns
(Notes on next page)
© 1992 Microchip Technology Inc.
OS300151 - page 35
1-35
PIC®16C5X Series
NOTES TO AC CHARACTERISTICS:
PIC16C5X-RC, XT, HS, LP (COMMERCIAL)
PIC16C5XI~RC, XT, HS, LP (INDUSTRIAL)
may result in an unstable oscillator operation and/or higher than
expected current consumption. All devices are tested to operate
at "min." values with an external clock applied to the ascI pin.
When an external clock input is used, the "Max." cycle time
limit is ''~C'' (no clock) for all devices.
3. For adetailed explanation of RTCC input clock requirements see
section 4.2.1.
4. Clock-in high-time is the duration for which clock input is at
VIHOSC or higher.
Clock-in low-time is the duration for which clock input is at VILOSC
or lower.
1. Data in the column labeled "Typical" is based on characterization results at 2S·C. This data is for design guidance only and is
not tested for, or guaranteed by Microchip Technology.
2. Instruction cycle period (Tcy) equals four times the input oscillator time base period.
All specified values are based on characterization data for that
particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits
16.9 Electrical Structure of Pins
17.0 TIMING DIAGRAMS
FIGURE 16.9.1 - ELECTRICAL
STRUCTURE OF 1/0 PINS (RA, RB, RC)
FIGURE 17.0.1 - RTCC TIMING
voo
: - - TRTH
------.
: - - - TRTL - - :
·······0.9 VOO
' -_ _ _ _~,
•• .1 ••••••.••
0.15 VDD
RTCC
Vss
- - - - TRTP - - - - - - - :
vss
Rin
Input
buffer
FIGURE 16.9.2 - ELECTRICAL
FIGURE 17.0.2 - OSCILLATOR START-UP TIMING (PIC16C5XRC)
STRUCTURE OF MCLR AND RTCC PINS
~---------
: - - To, --~- To,
MCLR
,
Tost
,
,---,
:
T1
,---'
I
:
T1
I
CLKOUT
,
vss
DEVICE
FUNCTION
vss
___
RESET
,
,
~ FETCH 1. INSTRUCTION : FETCH 2. INSTRUCTION ~ ____ _
: EXECUTE "FORCED" NOP : EXECUTE 1. INSTRUCTION:
Notes to figures 16.9.1 and 16.9.2: The diodes and the grounded gate (or output driver) NMOS device are carefully designed to protect against ESD
(Electrostatic discharge) and EOS (Electrical overstress). Rin is a small resistance to further protect the input buffer from ESD.
FIGURE 17.0.3 -INPUT/OUTPUT TIMING FOR I/O PORTS (PIC16C5XRC*)
---------Tcy
T1
OSC2/
CLKOUT
INPUT
1'--_ _----'1
-->-,
I
I
I
,I
'I - - T d s
I
0o/~flWA
I
I
Tdh
VALID
I
I
~ffi?ffffdMW$M
I
1----.1
'Tpd ;
OUTPUT
\--1,
_
'
: Tpd :
~zC==============~C=,
HIGH-Z
• The ClKOUT output is available only on PIC16C5XRC devices.
DS30015! - page 36
© 1992 Microchip Technology Inc.
1-36
PIC®16C5X Series
18.0 DC & AC CHARACTERISTICS GRAPHS/TABLES:
FIGURE 18.0.1· TYPICAL RC OSCILLATOR
FREQUENCY VS. TEMPERATURE
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are outside
specified operating range (e.g. outside specified VDD
range). This is for information only and devices are
guaranteed to operate properly only within the specified
range.
FREQUENCY NORMALIZED TO +2S'C
Fosc
Fosc (2S'C)
1.10
f - - f - - - + - - - Rex\::=10Kn - f - - I
Cext = 100pF
f--f---+----,-----r-----+----f
f--f---+---+---+----+----f
_=-f---+---+---+----+---I
i--="""'111_=--+---+---+----+----f
f--f---=k;::--+---+----+---I
f--f---+----"IIIIIIh..::-+_
1.08
The data presented in this section is a statistical summary of data collected on units from different lots over a
period of time. 'Typical' represents the mean of the
distribution while 'max' or 'min' represents (mean + 3cr)
and (mean - 3cr) respectively where cr is standard deviation.
1.06
1.04
1.02
1.00
0.98
0.96
f--f----I----~1I!I!I!I1IIIiIi
0.94
i--j------t-----t--+___'
0.92
f--f---+---+---+
0.90 i--j------t-----t---t--~--I
10
25
40
60
50
70
T('C)~
FIGURE 18.0.2· TYPICAL RC OSCILLATOR
FREQUENCY vs Vee
5.0
,/"
4.5
4.0
~
--
FIGURE 18.0.3· TYPICAL RC OSCILLATOR
FREQUENCY vs Vee
-
R=3.3k
1.8
/
1.4
3.5
1.2
~
N
R=Sk
1l0 l
R=3.3k
r-- r---
R=5k
N
.t:
3.0
~ 1.0
.t:
~
-
J
-
/
1.6
"'"
0
LL
2.5
0.8
LL
-----
2.0
0.6
R=10k
---
i
I--
-----
R=10k
1.5
0.4
1.0
Cext
0.5
Cext = 100pF, T = 2S'C
=20pF, T =2S'C
I
I
0.2
I
R~100k
R=100k
2.5
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
2.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
I
6.0
VDD(Volts)
08300151 - page 37
© 1992 Microchip Technology Inc.
1-37
PIC®16C5X Series
FIGURE 18.0.4· TYPICAL RC OSCILLATOR
FREQUENCY vs Voo
TABLE 18.0.1· RC OSCILLATOR FREQUEN·
CIES
O.B
0.7
v
0.6
r-N
.c:
0.5
~
'"
------- -
0.4
0.3
-
r--
0.2
Cext
Average
Fosc @ 5V, 25"C
~=3.3k
20pf
3.3k
5k
10k
100k
4.71 MHz
3.31 MHz
1.91 MHz
207.76 KHz
±28%
±25%
±24%
±39%
----£!=5k
100pf
3.3k
5k
10k
100k
1.65 MHz
1.23 MHz
711.54 KHz
75.62 KHz
±18%
±21%
±18%
±28%
300pf
3.3k
5k
10k
100k
672.78
489.49
275.73
28.12
±14%
±13%
±13%
±23%
:--
0
0
LL
Rext
Cext
------ -
-
R=10k
= 300pF, T = 2S"C
KHz
KHz
KHz
KHz
0.1
The percentage variation indicated here is part to part
variation due to normal process distribution. The variation indicated is ±3 standard deviation from average
value for full VDD range.
R-100k
o
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voo(Volts)
FIGURE 18.0.5· TYPICAL Ipd vs Voo
WATCHDOG DISABLED 25"C
3.5
FIGURE 18.0.6· TYPICAL Ipd vs Voo
WATCHDOG ENABLED 25"C
1--+---+~+---+~t--t----1r
20
2.5
15
<{
2-
<{
2-
"0
2
.9-
~
10
1.5
0.5
F---+---+~+---+~t--+-~r
OL--L~~~-L~L--L~~
2.5
3.0 3.5
4.0
4.5
5.0
5.5
6.0
6.5
2.5
7.0
3.0 3.5
4.0 4.5
5.0
5.5
6.0 6.5
7.0
VDD(Voltsj
VOD(Volts)
Note: The gray shaded regions are outside the normal PIC operating range. Do not operate in these regions.
© 1992 Microchip Technology Inc.
DS300151 - page 38
1-38
PIC®16C5X Series
FIGURE 18.0.8· MAXIMUM Ipd vs Voo
WATCHDOG ENABLED"
FIGURE 18.0.7· MAXIMUM Ipd vs Voo
WATCHDOG DISABLED
100
85
10
OL.---'-_"--..--L_.L....---L_~~_
3.0
3.5
4.0 4.5 5.0 5.5
VDD(Volts)
6.0
6.5
7.0
2.5 3.0
3.5
4.0 4.5 5.0 5.5
Voo(Volts)
6.0
6.5
7.0
IPO, with watchdog timer enabled, has two components: The leakage current which increases with higher temperature and the
operating current of the watchdog timer logic which increases with lower temperature. At -40'C, the latter dominates explaining the
apparently anomalous behavior.
Note: The gray shaded regions are outside the normal PIC operating range. Do not operate in these regions.
FIGURE 18.0.9· VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs Voo
VTH (Input threshold voltage) of I/O pins
2.00
1.80
1.60
UJ
"6
1.40
2:.I
I-
>
1.20
i .00
0.80
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voo (volts)
© 1992 Microchip Technology Inc.
08300151 - page 39
1-39
PIC®16C5X Series
FIGURE 18.0.10- VIH, VIL OF MCLR, RTCC AND OSC1 (IN RC MODE) vs Voo
4.50
4.00
.L
6 C)
AO'C~
3.50
,
:§" 3.00
~
1 2.50
........-: ~ ~
..J
:> 2.00
r
:> 1.50
~
~
'1\'"
...........
o'C\o\!
'I\\:~
\11"'11"
V;::/ v
~
1.00
~
..--:::
:::::----.............
VIL, max (.40·C to 80'C)
\ilL, TYP, 2S'C
\ilL, min (.4O·C to 8S'C)
0.50
r-
0.00
2.5
3.0
6.0
4.0
4.5
5.0
5.5
Voo (volts)
Note: These input pins have Schmitt trigger input buffer.
3.5
FIGURE 18.0.11 - VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP
MODES) vs Voo
3.40
3.20
·c\o ~
3.00
\1-~
2.80
2.60
:§" 2.40
/'"
~
(5
~
2.20
~
2.00
1.80
1.60 V
1.40
1.20
1.00
V
v------
2.5
~
.............-/'"
----
/'"
·c\'o
~
...........
~
~
........
~
~
3.0
____ ~
~
...............
...............
~ ,..... ...............
~----
~~.
~
3.5
---4.0
4.5
Voo (volts)
5.0
5.5
6.0
© 1992 Microchip Technology Inc.
DS;300151 - page 40
1-40
PIC®16C5X Series
FIGURE 18.0.12 - TYPICAL 100 vs FREQ (EXT CLOCK, 25'C)
10
/~
"ff//'.
W
~/
/.
1.0
~ ~~
././. ' l
./././: /
,.....-:: ::.---- v
0.1 =7.0
=6.0
-5.5
-5.0
-4.5
-4.0
3.5
-3.0
2.5
0.01
I--'
v~~
~~
~ ~ ~~
........ I-
--- --
,/
./
W// / /
W
V
,/
~
f-"
f-"
lOOK
10K
1M
10M
100M
External Clock Ireq (Hz)
FIGURE 18.0.13 - MAXIMUM 100 vs FREQ (EXT CLOCK, -40' to +85'C)
10
,/
./
~
~~
~ ra ~~
1.0
1
//
//
-'
Cl
.9
-7.0
0.1
V///
V/
6.5
=6.0
-5.5
=5.0
_4.5
-4.0
-3.5
-3.0
f-2.5
I.......) .....
[....- f-""
1...-:::: ~r::
....-
.,.............
,/
L
/~
~~
~ ~~
/
./
V//
v j/
/'./
::::- ........
rf-:
......
0.01
10K
lOOK
1M
10M
100M
External Clock Ireq (Hz)
D8300151 - page 41
© 1992 Microchip Technology Inc.
1-41
PIC®16C5X Series
FIGURE 18.0.14 - MAXIMUM 100 vs FREQ (EXT CLOCK, _55° to +125°C)
~
10
/ " t;;~ ~ ~ ~p.
~ ~ ~~ ~~
0
..........
-
7.0
-
6.0
0.1 _
5.0
== 4.0
= 3.0
2.5
r--
--:::::::---- f-::::: v
.... f-"
-
~k
~ f..-::
v
~ ~ 1==
I-:::
c-
-
-
"/"
//
...- ;::;-
/L
.- / '
;:::::: / '
I--
0.01
10K
100K
10M
1M
External Clock Ireq (Hz)
FIGURE 18.0.16 - Transconductance (gm) of
HS Oscillator vs Voo
FIGURE 18.0.15 - WDT Timer Time-out Period
vsVoo
50.0
9000 , - - - , - - , - - - - - - - , - - - , -
45.0
8000 I----r----t-------j-------t-;
40.0
7000 I----+---t-------j---I'--I-
35.0
6000 1----+----t-------j7'-. .;;-
u;-
.s
"0
0
~
30.0
a.
I0
5000 f----t-----b"'----t---j-
6
"&5
E
Ol 4000 f------+--+--+---t----:;~,...
25.0
~
20.0
3000 f - - - - r f - - - ¥ - - t - - _ + _
15.0
2000
10.0
1000 r------;;4---t---t--_+_
f-----7/-'---~.LC---:"----_+_
5.0
2
4
5
6
2
4
6
7
VDD(Volts)
VDD(Volts)
Note: The gray shaded regions are outside the normal PIC operating range. Do not operate in these regions.
© 1992 Microchip Technology Inc.
OS300151 - page 42
1-42
PIC®16C5X Series
FIGURE 18.0.17 - Transconductance (gm) of
LP Oscillator vs Voo
FIGURE 18.0.18 - Transconductance (gm) of
XT Oscillator vs Voo
45.0 ,------,---.,----,-----,--,
2500 , - - - - - - , - - , - - - , - - - , -
40.0 i - - - - + - - - t - - - i - - - T t - - '
2000 i----+---i----fi-"
35.0
30.0
>
<
~
1500 I----+--,<---f----+---f-::;
I
25.0
E
'"
E
20.0
'"
1000 I------t--+---r-f---t----t-
15.0
10.0 I----'-----I-~-I---~=_+
500
I--~-+____:r--f---t----t-
5.0 i----::::J,.""'----t---j---t-
0.0 ' - - - - - ' - - - - ' - - - ' - - - - - ' 2
4
5
3
6
VDD(Volts)
O'----'----'---........l.----'-2
4
5
3
6
VDD(Volts)
7
7
Note: The gray shaded regions are outside the normal PIC operating range. Do not operate in these regions.
FIGURE 18.0.19 -IOH
VS
FIGURE 18.0.20 - IOH VS VOH, Voo = 5V
VOH, Voo = 3V
o
o
-10
-10
«
.s-20
«
.s-20
~
I
.Q
-30
-30
2
2.5
3
3.5
VOH(Volts)
4
4.5
5
2
© 1992 Microchip Technology Inc.
2.5
3
3.5
VOH (Volts)
4
4.5
5
OS300151 • page 43
1·43
PIC®16C5X Series
FIGURE 18.0.22 ·IOL VS VOL, Voo = 5V
FIGURE 18.0.21 • IOL VS VOL, Voo = 3V
VOOMIN.
NOTE: Some applications may require external RIC
networks on the MCLR pin in order to allow for oscillator
startup times longer than one OST period. In this case,
a WOT wake up from power down mode is not recommended, because a RESET generated by a WOT time
out does not discharge the external capacitor, and the
PIC will be in RESET only for the oscillator start-up timer
period.
14.0 POWER DOWN MODE (SLEEP)
The power down mode is entered by executing a SLE EP
instruction.
If enabled, the watchdog timer will be cleared but keeps
running, the bit "PO" in the status register (f3) is cleared,
the "TO" bit is set, and the oscillator driver is turned off.
The 1/0 ports maintain the status they had, before the
SLEEP command was executed (driving high, low or hiimpedence).
For lowest current consumption in this mode, all 1/0 pins
should be either at Voo, or Vss, with no external circuitry
drawing current from the 1/0 pin. 110 pins that are in the
High-Z rnode should be pulled high or low ~xternally to
avoid switching currents caused by floating inputs. The
RTCC pin should also be at Voo orVss for lowest current
consumption.
The MCLR pin must be at VIHMC.
15.0 CONFIGURATION FUSES
The configuration word consists of four ROM fuses
which are not part of the normal ROM program storage.
Two are for the selection of the oscillator type, one is the
watchdog timer enable fuse, and one is the code protection fuse.
The customer makes the selection for these and the
parts are tested accordingly. The packages are marked
with the suffixes "XT", "RC", "HS" or "LP" following the
part number to identify the oscillator type and operating
range.
14.1 Wake-Up
The device can be awakened by a watchdog timer
timeout (if it is enabled) or an externally applied "low"
pulse at the MCLR pin. In both cases the PIC will stay in
RESET mode for one oscillator start-up timer period
(triggered from rising edge on MCLR or WOT timeout)
before normal program execution resumes.
15.1 Customer 10 Code
The PIC16CR54 has 4 special ROM locations which are
not part ofthe normal program memory. These locations
are available to the user to store an Identifier (ID) code,
checksum, or other informative data. They cannot be
accessed during normal program execution but can be
read out using any programmer that supports the
PIC16C5X such as PICPRO or PICPRO II.
The "PO" bit in the STATUS register, which is set to one
during power on, but cleared by the "SLEEP" command,
can be used to determine if the processor was powered
up or awakened from the power down mode (Table
4.5.1.2). The TO bit in the Status register can be used
to determine, if the "wake up" was caused by an external
MCLR signal or a watchdog timer time out.
DS30075C-page 21
© 1992 Microchip Technology Incorporated
1-81
Another way to verify a code protected ROM without
supplying the actual code is as follows:
15.2 Code Protection
The code in the ROM can be protected by selecting the
code protection fuse to be "0".
When code protected, the contents of the program ROM
cannot be read out in a way that the program code can
be reconstructed. The factory can verify every bit in a
code protected ROM through a special ROM-verify test
mode. In this test mode data is presented to the chip for
every ROM location and a pass/fail bit at the end of the
sequence indicates if the ROM matched the externally
supplied pattern sequence. This mode does not output
the ROM pattern and therefore does not compromise
code security.
When code protected, verifying any program memory
location will read a scrambled output which looks like
"OOOOOOOOXXXX" (binary) where X is 1 or O. To verify a
code protected device, follow this procedure:
a. First, read in a code-protected device known to be
good into a file. The data will look scrambled.
b. Verify any code-protected PIC against this file.
DS30075C-page 22
© 1992 Microchip Technology Incorporated
1-82
16.0 ELECTRICAL
CHARACTERISTICS
16.1 Absolute Maximum Ratings'
'Notice: Stresses above those listed under ·'Maximum Ratings"
may cause permanent damage to the device. This is a stress
Ambient temperature under bias ........ -55"C to + 125"C
rating only and functional operation of thedevice at those or any
Storage Temperature ....................... - 65"C to + 150"C
Voltage on any pin with respect to Vss
(except VDD and MCLR) ................ -0.6V to VDD +0.6V
Voltage on VDD with respect to Vss..
..0 to +7.5 V
Voltage on MCLR with respect to Vss
(Note 2) ........................................................ 0 to + 14 V
Total power Dissipation (Note 1) .................... 800 mW
Max. Current out of Vss pin ............................. 150 mA
Max. Current into VDD pin .................................. 50 mA
Max. Current into an input pin ........................ ±500 flA
Max. Output Current sinked by any I/O pin ........ 25 mA
Max. Output Current sourced by any I/O pin ..... 20 mA
Max. Output Current sourced by a single
110 port (Port A or B) ......................................... .40 mA
Max. Output Current sinked by a single
110 port (Port A or B) ........................................... 50mA
other conditions above those indicated in the operation listings
of this specification is not implied. Exposureto maximum rating
conditions for extended periods may affect device reliability.
Notes: 1. Total power dissipation should not exceed 800
mW for the package. Power dissipation is
calculated as follows:
Pdis= VDDX {IDD- L loh} + L{(VDD-Voh) x loh}
__
+ L(Vol x 101)
2. Voltage spikes below Vss at the MCLR pin,
inducing currents greater than 80mA, may
cause latch-up. Thus, a series resistor of 50lOOn should be used when applying a "low'
level to the MCLR pin rather than pulling this
pin directly to Vss.
16.2 Pin Descriptions
Name
Function
Observation
RAO - RA3
RBO - RB7
RTCC
I/O PORT A
110 PORT B
MCLR
Master Clear
OSCl
Oscillator (input)
OSC2/CLKOUT
Oscillator (output)
4 input/output lines.
8 input/oulQut lines.
Schmitt Trigger Input.
Clock input to RTCC register. Must be tied to Vss or VDD if
not in use to avoid unintended entering of test modes and
to reduce current consumption.
Schmitt Trigger Input.
A "Low" voltage on this input generates a RESET condition
for the PIC16CR54 microcontroller.
A rising voltage triggers the on-chip oscillator start-up timer
which keeps the chip in RESET mode for about 18ms. This
inp_ut must be tied directly, or via a pull-up resistor, to VDD.
"XT", "HS" and "LP" devices: Input terminal for crystal,
ceramic resonator, or external clock generator.
"RC" devices : Driver terminal for external RC combination
to establish oscillation.
For "XT", "HS" and "LP" devices: Output terminal for crystal
and ceramic resonator. Do not connect any other load to
this output. Leave open if external clock generator is used.
For "RC" devices: A "CLKOUT" signal with a frequency 01
1/4 Fosel is put out on this pin.
VDD
Vss
Power supply
Ground
No (internal) Connection
N/C
Real Time Clock/Counter
© 1992 Microchip Technology Incorporated
DS30075C-page 23
1-83
16.3 DC CHARACTERISTICS: PIC16CR54-RC, XT, HS, LP (COMMERCIAL)
PIC16CR54-RC, XT, HS, LP (INDUSTRIAL)
DC CHARACTERISTICS,
POWER SUPPLY PINS
Characteristic
Supply Voltage
PICI6CR54-XT, RC
PICI6CR54-HS
PICI6CR54-LP
RAM Data Retention
Voltage (Note 3)
.Voo starting voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 2)
PICI6CR54-XT, RC (Note 5)
PICI6CR54-HS
PICI6CR54-LP
Power Down Current
Commercial (Note 4)
PIC16CR54
Power Down Current
Industrial (Note 4)
PIC16CR54
Standard Operating Conditions
Operating temperature -40 ~ TA ~ t85'C for industrial and O'C ~ TA ~ t70'C for commercial
Sym
Min
Voo
Voohs
Voolp
VOR
2_5
4_5
2.0
VPOR
Svoo
Typ
(Note 1)
Max
Units
6_25
5_5
6.25
1.5
V
V
V
V
Vss
V
0.05'
V/ms
Conditions
= DC to 4 MHz
= DC to 20 MHz
Fosc = DC to 200 KHz
Fosc
Fosc
Device in SLEEP mode
See section 13.1 for details on
power-on-reset
See section 13.1 for details on
power -on-reset
= 4 MHz, Voo = 6.0V
= 4 MHz, voo = 3.0V
= 200 KHz, Voo = 2.5V
= 8 MHz, Voo = 5.5V
= 20 MHz, Voo = 5.5V
= 32 KHz, Voo = 2.0V
= 32 KHz, Voo = 6.0V
1001
1002
1003
loohsl
100hs2
loolpl
IDOlp2
2.0
0.8
90
3.8
9.0
10.0
3.6
1.8
350
10
20.0
20.0
70.0
mA
mA
I1A
mA
mA
I1A
I1A
Fosc
Fosc
Fosc
Fosc
Fosc
Fosc
Fosc
IPDl
Ip02
Ip03
IPD4
1
2
3
5
6
8'
15
25
I1A
I1A
I1A
I1A
VOD = 2.5V,
Voo = 4.0V,
Voo = 6.0V,
VDD = 6.0V,
WDT disabled
WDT disabled
WDT disabled
WDT enabled
Ipol
Ip02
Ip03
Ip04
Ip05
1
2
3
3
5
8
10'
20'
18
45
I1A
I1A
I1A
I1A
I1A
Voo = 2.5V,
Voo = 4.0V,
Voo = 4.0V,
Voo = 6.0V,
Voo = 6.0V,
WDT
WDT
WDT
WDT
WDT
disabled
disabled
enabled
disabled
enabled
, These parameters are based on characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Data in the column labeled "Typical" is based on characterization results at 25'C. This data is for design guidance only and is not tested
for, or guaranteed by Microchip Technology.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus
rate, internal code execution pattern, and temperature also have an impact on the current consumption.
a) The test conditions for all 100 measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all 1/0 pins
tristated, pulled to Voo, RT = Voo, MCLR = Voo; WDT enabledldisabled as specified.
b) For stand-by current measurements, the conditions are the same, except that the device is in SLEEP mode.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The power down current in SLEEP mode does not depend on the oscillator type. It is measured in SLEEP with all 1/0 pins in hi-impedence
state and connected to Voo or Vss.
In RC mode does not include current through Rext. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30075C-page 24
© 1992 Microchip Technology Incorporated
1-84
16.4 DC CHARACTERISTICS: PIC16CR54-RC, XT, HS, LP (COMMERCIAL)
PIC16CR54-RC, XT, HS, LP (INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS,
Operating temperature -40'C ~ TA ~ +85'C for industrial and
ALL PINS EXCEPT POWER SUPPLY o·c ~ TA ~ +70'C for commercial
Operating voltage Voo range as in table 16.3 unless otherwise stated
Characteristic
Min
Sym
Input Low Voltage
I/O ports
MCLR (Schmitt trigger)
RTCC (Schmitt trigger)
OSCl (Schmitt trigger)
OSCl
Input High Voltage
I/O ports
MCLR (Schmitt trigger)
RTCC (Schmitt trigger)
OSCl (Schmitt trigger)
OSCl
Input Leakage Current
(Notes 3, 4)
I/O ports
MCLR
MCLR
RTCC
OSCl
Output Low Voltage
I/O Ports
OSC2/CLKOUT
Output High Voltage
I/O Ports (Note 4,5)
OSC2/CLKOUT
Typ
(Note 1)
Max
VIL
VILMC
VILRT
VILOSC
VILOSC
Vss
Vss
Vss
Vss
Vss
0.2 Voo
0.15 Voo
0.15 Voo
0.15 Voo
0.15 Voo
V
V
V
V
V
VIH
VIH
VIHMC
VIHRT
VIHOSC
VIHOSC
2.0
0.6 Voo
0.85 Voo
0.85 Voo
0.85 Voo
0.85 Voo
Voo
Voo
Voo
Voo
Voo
Voo
V
V
V
V
V
V
IlL
-1
+1
I1A
IILMCL
IILMCH
IILRT
IILOSC1
-5
-3
-3
0.5
0.5
0.5
+5
+5
+3
VOL
VOL
VOH
VOH
0.5
0.5
Voo-0.5V
Voo-0.5V
Conditions
Units
I1A
I1A
I1A
ItA
Pin at hi-impedance
PIC16CR54RC only (Note 5)
PIC16CR54-XT, HS, LP
Voo = 3.0V to 5.5V (Note 6)
Full Voo range (Note 6)
PIC16CR54-RC only (Note 5)
PIC16CR54-XT, HS, LP
For Voo ~ 5.5V
Vss ~ VPIN ~ Voo,
Pin at hi-impedance
VPIN = Vss + 0.25V
VPIN = Voo
Vss ~ VPIN ~ Voo
Vss ~ VPIN ~ Voo,
PIC16CR54-XT, HS, LP
V
V
IOL = 10 mA, Voo = 6.0V
IOL = 1.9 mA, Voo = 6.0V
V
V
IOH
IOH
= -4.0 mA, Voo =6.0V
= -0.8 mA, Voo = 6.0V
Note 1: Data in the column labeled "Typical" is based on characterization results at 25' C. This data is for design guidance
only and is not tested for, or guaranteed by Microchip Technology.
Note 2: Total power dissipation as stated under absolute maximum ratings must not be exceeded.
Note 3 : The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Note 4 : Negative current is defined as coming out of the pin.
Note 5 : For PIC16CR54-RC devices, the OSCl pin is a Schmitt trigger input. It is not recommended thatthe PIC16CR54
be driven with external clock in RC mode.
Note 6: The user may use the better of the two specs. TTL level is guaranteed in 3.0V to 5.5V range.
© 1992 Microchip Technology Incorporated
DS30075C-page 25
._~_u~
c
-
-
=
-
-
__ _ _ _ _ _ _-=
~
1-85
______
16.5 AC CHARACTERISTICS: PIC16CR54-RC, XT, HS, LP (COMMERCIAL)
PIC16CR54-RC, XT, HS, LP (INDUSTRIAL)
I
J....
.:
Standard Operating Conditions (unless otherwise noted)
Operating temperature TA:5; -40'C:5; +8S"C for industrial and
O'C:5; TA:5; +70'C for commercial
AC CHARACTERISTICS
Operating voltage VDD range as in table 16.3 unless otherwise stated
!
Characteristic
Sym
Oscillator
Frequency (Note 2)
FOSCRC
FOSCXT
FOSCHS
FOSCLP
Tcv
DC
0.1
4
TCKHLXT
TCKHLLP
TCKHLHS
SO'
2'
20'
ns
TCKRFXT
TCKRFLP
TCKRFHS
2S'
SO'
2S'
ns
ns
ns
TMCL
100'
ns
TRTH
TRTL
O.S TcY+ 20'
O.S TcY+20'
ns
ns
Note 3
Note 3
TRTH
TRTL
TRTP
10'
10'
ns
ns
ns
Note 3
Note 3
Note 3. Where N =
prescale value (2,4, ... , 2S6)
TWDT
TOST
7'
7'
ms
ms
VDD = SV, -40'C to 8S'C
VDD = SV, -40'C to 8S'C
TDS
0.2S Tcv+ 30'
ns
TDH
0'
ns
Instruction Cycle Time
External Clock in Timing
(Note 4)
Clock in High or Low Time
XT oscillator type
LP oscillator type
HS oscillator type
Clock in Rise or Fall Time
XT oscillator type
LP oscillator type
HS oscillator tvDe
RESET Timing
MCLR Pulse WidthJlo'Al}
RTCC Input Timing,
No Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Input Timing,
With Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Period
Watchdog Timer Timeout
Period (No Prescaler)
Oscillation Start-up Timer
Period
I/O Timing
I/O Pin Input Valid Before
CLKOUTi (RC Mode)
I/O Pin Input Hold After
CLKOUn (RC Mode)
I/O Pin Output Valid After
CLKOUT.J, (RC Mode)
Capacitive Loading
Specs on Output Pins
OSC2
All I/O pins
Min
Typ
(Note 1)
Max
Units
Conditions
4.0
4
20
200
4/Fosc
MHz
MHz
MHz
KHz
RC mode, VDD = 2.S to 6.2SV
XT mode, VDD = 2.S to 6.2SV
HS mode, VDD = 4.S to S.SV
LP mode VDD = 2.0 to 6.2SV
ns
lIS
TCv+40 '
N
18
18
30'
30'
TPD
40'
ns
COSC2
IS
pF
CIO
SO
pF
, Based on characterization, but not tested.
In XT, HS and LP modes
when external clock is used
to drive OSCI.
(Notes on next page)
© 1992 Microchip Technology Incorporated
DS30075C-page 26
1-86
NOTES TO AC CHARACTERISTICS:
PIC16CR54-RC, XT, HS, LP (COMMERCIAL)
PIC16CR54-RC, XT, HS, LP (INDUSTRIAL)
executing code. Exceeding these specified limits may resutt in an
unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values wHh an
external clock applied to the aSCl pin.
When an external clock input is used, the "Max." cycle time limit Is
"DC" (no clock) for all devices.
3. For a detailed explanation of RTCC input clock requirements see
section 4.2.1.
4. CloCk-in high time isthe duration for which clockinputisat VIHcec or higher.
CloCk-in low time is the duration for which clock input is at VILcecorlower.
1. Data in the column labeled "Typical" is based on characterization results
at 2S·C. This data is for design guidance only and is not tested for, or
guaranteed by Microchip Technology.
2. Instruction cycle period (Tey) equals four times the input oscillatortime
basa period.
All specified values are based on characterization data forthat particular
oscillator type under standard operating conditions with the device
16.6 Electrical Structure of Pins
17.0 TIMING DIAGRAMS
FIGURE 16.6.1 - ELECTRICAL
STRUCTURE OF 1/0 PINS (RA, RB)
FIGURE 17.0.1 - RTCC TIMING
Voo
:--TRTL - - :
:
:~----~.
RTCC
~----
Vss
I
....
O.9VOD
···t····
, ...-.
0.15 VDO
TRTP - - - - - - - -
vss
RI"
Input
buffer
FIGURE 16.6.2 - ELECTRICAL
FIGURE 17.0.2 - OSCILLATOR START-UP
STRUCTURE OF MCLR AND RTCC PINS TIMING (PIC16CR54RC)
~---------
: - - Toy --~-- Toy -------'
MCLR
-----:---:
Tost
T1
CLKOUT
I
I
,
---'
,T1
I
I
:
~
----
,
Vss
DEVICE - - FUNCTION
vss
I
,
RESET - - - - - ' FETCH 1. INSTRUCTION : FETCH 2. INSTRUCTION : ____ _
: EXECUTE "FORCED" NOP : EXECUTE 1. INSTRUCTION
r
Note to figures 16.6.1 and 16.6.2: The diodes and the grounded gate (or output driver) NMOS device are carefully designed to protect against ESD
(Electrostatic discharge) and EOS (Electrical overstress). Rin is a small resistance to further protect the input buffer from ESD.
FIGURE 17.0.3 - INPUT/OUTPUT TIMING FOR I/O PORTS (PIC16CR54RC*)
----------Tcy
T1
OSC21
CLKOUT
INPUT
OUTPUT
• The CLKOUT output is available only on PICt 6CR54-RC devices.
© 1992 Microchip Technology Incorporated
DS30075C-page 27
1-87
FIGURE 18.0.1 - TYPICAL RC OSCILLATOR
FREQUENCY vs. TEMPERATURE
18.0 DC & AC CHARACTERISTICS
GRAPHS/TABLES:
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are outside
specified operating range (e.g. outside specified VDD
range). This is for information only and devices are
guaranteed to operate properly only within the specified
range.
FREQUENCY NORMALIZED TO +2S"C
Fosc
Fosc:(25"C)
1.10
1.00
f---f-----f--f---r------j------r-----r--+--i
f---r------f---+--+--+----j
iIIIIIIIo;;;:-r------j---+--+--+--i
r---='-as:::-----j---+--+--+--i
1---1---="""1""",,=---+--+--+--1
0.98
r---r-------j---""'lIIIIIIlIIIiiiiiO±::_
1.08
1.06
1.04
1.02
The data presented in this section is a statistical summary of data collected from units from different lots over
a period of time. 'Typical' represents the mean of the
distribution while 'max' and 'min' represents (mean + 3cr)
and (mean - 3cr) respectively where cr is standard deviation.
0.96
0.94
0.92
0.90
f---r------f---+'--"'IIIIIIIII.
f---r------j---+--+---"
f---r------f---+--+
f---r------j---+--+--+--i
10
6.0
/
5.5
L
5.0
~
60
70
2.0
6.5
.<::
40
50
T('C)_
FIGURE 18.0.3 - TYPICAL RC OSCILLATOR
FREQUENCY vs. Voo
FIGURE 18.0.2 - TYPICAL RC OSCILLATOR
FREQUENCY vs. Voo
..
25
4.5
/
4.0
L
R=3.3k
----
R=3.3k
1.8
/
----
-
1.4
I--
R=5k
.. 1.2
V
3.5
/
1.6
R=5k
----
.<::
~
~ 1.0
~ 3.0
If
R=10k
2.5
- ---
0.8
2.0
0.6
1.5
r-- I-
R=10k - -
-
0.4
1.0
C~xt
Cext =2OpF, T =25'C
0.5
2.5
I
I
I
o
3.0
3.5
4.0
4.5
5.0
= 1~OPF, ~ = 2S~C
0.2
R=100k 5.5
R=100k
o
6.0
2.5
VoD(Volts)
3.0
3.5
I
I
4.0
4.5
5.0
5.5
6.0
Voo(Voits)
DS30075C-page 28
© 1992 Microchip Technology Incorporated
1-88
FIGURE 18.0.4 - TYPICAL RC OSCILLATOR
FREQUENCY vs Voo
O.B
0.7
-
V
Cext
1.
Rext
Average
Fosc @ SV, 2S'C
'-- ~3:"
0.6
I'-----
N
0.5
J::
e
r----:---~
--
0
U)
~ 0.4
0.3
TABLE 18.0.1 - RC OSCILLATOR FREQUENCY
VARIATION FROM UNIT TO UNIT
I'---- I'-----
t-:-
R=10k
r--:t--
20pl
3.3k
5k
10k
100k
6.02 Mhz
4.06 Mhz
2.47 Mhz
261 Khz
±28%
±25%
±24%
±39%
100pl
3.3k
5k
10k
100k
1.82 Mhz
1.28 Mhz
715 Khz
72.4 Khz
±18%
±21%
±18%
±28%
300pl
3.3k
5k
10k
100k
712.4 Khz
508 Khz
278 Khz
28 Khz
±14%
±13%
±13%
±23%
0.2
Cext = 3OOpF, T = 2S'C
0.1
R=10~k
2.5
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
The percentage variation indicated here is part to part
variation due to normal process distribution. The varia·
tion indicated is ±3 standard deviation from average
value lor lull VDD range.
6.0
FIGURE 18.0.5 - TYPICAL IPD vs Voo
WATCHDOG TIMER ENABLED 25'C
FIGURE 18.0.6 - MAXIMUM Ipd vs Voo
WATCHDOG TIMER ENABLED
10
35
Industrial Tem p. /
/'
30
,./'
7
./"
/
25
/
<'
2-
/
~
/
0.1
II
/
20
15
V
10
5
0.01
U
U
M
U
~
U
V
V
0
MUM
U
VDD(Volts)
U
/
/
8S'C
,./'/
-- V ---M
U
~
V
V
U
MUM
VDD(Volts)
© 1992 Microchip Technology Incorporated
DS3007SC'page 29
1·89
FIGURE 18.0.7 - VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs Voo
2.00
t
6 C\
4O'C\0~::'--
1.80
J-~~-
1.60
~
-----
1.40
Z.
~ 1.20
.-
1.00
----
---
0.80
0.60
2.5
----
~
Z5'C'~~
r-----J
~
~
I-"
5'C\
4O'C\Os~
I--"
----
~
--------
------
3.0
3.5
4.0
4.5
Voo (volts)
5.5
5.0
6.0
FIGURE 18.0.8 - VIH, VIL OF MCLR, RTCC AND OSC1 (IN RC MODE) vs Voo
4.50
.........-:::
4.00
3.50
~
3.00
111
l2.50
....
:>
r
:>
-
J, s6 C\
\:;,OC~V_
.--: ~
2.00
.-..---;: ~
1.50
.-
~
:....--
~
~
~
1.00
"''' . \:40' C \O
\j\\'\('{\\'(\
-
Vll, max (·4 'C \0 "o'c)
"'l, TVP, 25'C
"'l, min (.40·C \0 8S'C)
0.50
~
0.00
2.5
3.0
6.0
4.0
4.5
5.5
5.0
Voo (volts)
Note: These input pins have Schmitt trigger input buffer.
3.5
FIGURE 18.0.9 - VTH, (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP
MODES) vs Voo
3.40
3.20
2.60
'0
,.-
2.40
Z. 2.20
~
2,00
..............
1.60
,...-
1.40
1.20
.....--------
2.5
--
,...- V
V
3.0
3.5
--
V
~
~
~
'/,r;c,
~
.c,\0
~
,..---
~
V
V
~
~
1.80
1.00
,/'
w.~
2.80
!!l
~
,b\oS~
3.00
~
----
4.0
4.5
Voo (volts)
5.0
5.5
6.0
© 1992 Microchip Technology Incorporated
DS30075C-page 30
1-90
FIGURE 18.0.10· TYPICAL 100 vs FREQ (EXT CLOCK, 25°C)
10
t::
~ ~ ~ ~~
1.0
~.--:;
S
~
01
'"
.Q
.
0.01
.........................
.......-::::
~./..........
6.0 j I-5.5 1--- ...... 1-5.0
4.5
~
~ F4.0
3.5
3.0
2.5
,:::::: ~
0.001
10000
/
~./
.-e:::::::
:?
I:::
~ ~ ~~
V
/'
~
100000
1000000
10000000
External Clock Freq (Hz)
FIGURE 18.0.11 • MAXIMUM 100 vs FREQ (EXT CLOCK, ·40°C TO +85°C)
10000
~
~ ~ ~;::;
~~~~
1000
~./
<'
k:;::=
2-
'"
~
.Q
100
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
10
10000
---
1;:2~
~ b8 ~t:::
1:2"
~ ~ ~ ~i/
I-"""
/.67/
k:9"" ".-
I--
V
I:;;;;;; ~ F""f-o"
I..........
100000
1000000
External Clock freq (Hz)
© 1992 Microchip Technology Incorporated
10000000
DS30075C-page 31
1-91
FIGURE 18.0.12 -WDT Timer Time-out Period
vs Voo
SO.O
FIGURE 18.0.13 -Transconductance (gm) of
HS Oscillator vs Voo
='""---,~~--,~~---,-~~--,--
9000
4S.0
8000
40.0
7000
35.0
6000
u;-
.s
"C
0
[
30.0
a.
fCl
:s:
sooo
.2,
"~
E
2S.0
Ol
4000
20.0
3000
1S.0
2000
10.0
1000
a
3
4
5
6
2
7
3
4
5
7
Voo(Volts)
Voo(Volts)
FIGURE 18.0.14 -Transconductance (gm) of
LP Oscillator vs Voo
FIGURE 18.0.15 -Transconductance (gm) of
XT Oscillator vs Voo
2500
4S.0
40.0
2000
3S.0
30.0
;;;;C
~
2S.0
.2,
E
OJ
1500
E
Ol
20.0
1000
15.0
10.0
500
S.O
0.0
2
4
5
6
4
7
Note:
S
6
7
Voo(Volts)
Voo(Volts)
The gray shaded regions are outside of the normal PIC operating range. Do not operate in these regions.
© 1992 Microchip Technology Incorporated
DS30075C-page 32
1-92
!
FIGURE 18.0.17 -IOH vs VOH, Voo = 5V
FIGURE 18.0.16 -IOH vs VOH, Voo = 3V
0,----,----,---,---,---,-----",
o,---,----.---.----.---.---~
-5
1----+----+----+----+--+++-+--1
-10
-15
-10
;;(
E
;;(
.s
"I-20
J:
.Q
.Q
-15
-25
-30
-20
-35
0.5
1.0
FIGURE 18.0.18 -IOL
1.5
2.0
VOH(Volts)
VS
2.5
3.0
2.5
3.0
3.5
4.0
VOH (Volts)
4.5
5.0
FIGURE 18.0.19 -IOL VS VOL, Voo = 5V
VOL, Voo = 3V
90
80
70
60
;;( 50
.s
.Q
40
30
o
Note:
0.5
1.5
2
VOL (Volts)
2.5
20
1-++-1'--+-7"-+---+---+---1
10
1--++-1--7-"-+---+---+---+---1
0.5
3
1
1.5
2
2.5
3
VOL (Volts)
The gray shaded regions are outside of the normal PIC operating range. Do not operate in these regions.
© 1992 Microchip Technology Ihcorporated
DS30075C-page 33
1-93
I
TABLE 18.0.2 -INPUT CAPACITANCE FOR
PIC16CR54 *
Typical Capacitance (pF)
Pin
18L PDIP
'I
I
I
18LSOIC
RA. RB port
5.0
4.3
MCLR
2.0
2.0
OSC1.0SC2/CLKOUT
4.0
3.5
RTCC
3.2
2.8
• All capacitance values are typical at 2S"C. A part to
part variation of ±25% (three standard deviations)
should be taken into account.
© 1992 Microchip Technology Incorporated
DS30075C-page 34
1-94
19.0 PACKAGING DIAGRAMS AND DIMENSIONS
19.1 18-Lead Plastic Dual In-Line (.300 mil)
m
N
E1
E
IJ I
Pin No. 1---..
Indicator
.....l-r-TT"""T"T""TT""T"T""TT""TT"TT"...,.~
Area
~----------D1----------~
Package Group: Plastic Dual In-line (PLA)
Inches
Millimeters
Min
Max
0°
10°
4.064
-
0.160
-
0.015
-
Notes
Symbol
Min
Max
(t
0°
10°
A
A1
A2
B
B1
0.381
3.048
3.810
0.120
0.150
0.356
0.559
0.014
0.022
1.524
1.524
Typical
0.060
0.060
Typical
C
0.203
0.381
Typical
0.008
0.015
Typical
D
D1
E
E1
e1
eA
eB
22.479
23.495
0.885
0.925
20.320
20.32
0.800
0.800
0.325
Notes
Reference
Reference
7.620
8.255
0.300
6.096
7.112
0.240
0.280
2.489
2.591
Typical
0.098
0.102
Typical
7.620
7.620
Reference
0.300
0.300
Reference
7.874
9.906
0.310
0.390
L
3.048
3.556
0.120
0.140
N
18
18
18
18
8
81
0.889
-
0.035
-
0.127
0.005
DS30075C-page 35
© 1992 Microchip Technology Incorporated
1-95
PACKAGING DIAGRAMS AND DIMENSIONS (CONT.)
19.2 18-Lead Plastic Surface Mount (SOle - Wide. 300 mil Body>
Indicator Area
Chamfer
h x 45°
..L~
CP
~I
0
:;=~\FiJ
i
:i=+
~~-t
Plane
A1
Base
P~
A
Package Group: Plastic sOle (SO)
Inches
Millimeters
Symbol
Min
Max
Notes
Max
Min
ex
0°
8°
0°
8°
A
2.3622
2.6416
0.093
0.104
A,
0.1016
0.2997
0.004
0.0118
B
0.3556
0.4826
0.014
0.019
C
0.2413
0.3175
0.0095
0.0125
0
11.3538
11.7348
0.447
0.462
E
7.4168
7.5946
0.292
0.299
e
1.270
1.270
H
10.0076
10.6426
h
0.381
L
0.4064
0.050
0.050
0.394
0.419
0.762
0.015
0.030
1.143
0.016
0.045
18
0.004
Typical
N
18
18
18
CP
-
0.1016
-
Notes
Typical
© 1992 Microchip Technology Incorporated
DS30075C-page 36
1-96
19.3 Package Marking Information
18L PDIP
c=)
Example
MMMMMMMMMMMMXXX
MMMMMMMMXXXXXXX
c=)
~ AABB CDE
18LSOIC
PIC16CR56RCI/P456
~ 9123 CBA
Example
MMMMMMMMM
MMMMMMMMMMMM
MMMMMMMMM
MMMMMMMMMXXX
O~ AABB CDE
Legend:
MM ... M
XX ... X
AA
BB
C
D
E
Note:
O~
AABB CDK
Microchip part number information
Customer specific information
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week '01 ')
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number can not be marked on one
line, it will be carried over to the next line thus limiting the number
of available characters for customer specific information.
20.0 DEVELOPMENT SUPPORT
Microsoft Windows® 3.0 environment, allowing the operator access to a wide range of supporting software and
accessories.
20.1 PICMASTER-16™: High Performance
Universal In-Circuit Emulator System
Provided with the PICMASTER System is a high performance real-time In-Circuit Emulator, a microcontroller
EPROM programmer unit, a macro assembler program,
and a simulator program. Sample programs are provided to help quickly familiarize the user with the development system and the PIC microcontroller line.
The PICMASTER Universal In-Circuit Emulator System
is intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16C5X and PIC17CXX families. This system currently supports the PIC16CR54,
PIC16C54, PIC16C55, PIC16C56 and PIC16C57 at
clock frequencies of 4 MHz and PIC17C42 at 16 MHz.
Coupled with the user's choice of text editor, the system
is ready for development of products containing any of
Microchip's microcontroller products.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new microcontroller
architectures with data and program memory paths to
16-bits.
A "Quick Start" PIC Product Sample Pak containing
user programmable parts is included for additional convenience.
Microchip provides additional customer support to developers through an Electronic Bulletin Board System
(EBBS). Customers have access to the latest updates
in software as well as application source code examples. Consult your local sales representative for
information on accessing the BBS system.
The Emulator System is designed to operate on low-cost
PC compatible machines ranging from 80286-AT class
ISA-bus systems through the new 80486 EISA-bus
machines. The development software runs in the
© 1992 Microchip Technology Incorporated
DS30075C-page 37
1-97
Target-specific Emulator Probe: A probe specific
to microcontroller family to be emulated is installed on
the ribbon cable coming from the control pod. This
probe configures the universal system for emulation
of a specific microcontroller. Currently, the 16C5x
family, and the new PIC17C42 microcontrollers are
supported. Future microcontroller probes will be
available as they are released.
20.1.1 Host System Requirements:
The PICMASTER has been designed as a real-time
emulation system with advanced features generally
found on more expensive development tools. The AT
platform and Windows 3.0 environment was chosen to
best make these features available to you the end user.
To properly take advantages of these features,
PICMASTER requires installation on a system having
the following minimum configuration:
• PC Host Emulation Control Software: Host software necessary to control and provide a working user
interface is the last major component of the system.
The emulation software runs in the Windows 3.0
environment, and provides the user with full display,
alter, and control of the system under emulation. The
Control Software is also universal to all microcontroller
families.
• PC AT compatible machine: 80286, 386SX, 386DX,
or 80486 with ISA or EISA Bus.
• EGA, VGA, 8514/A, Hercules graphic card (EGA or
higher recommended).
MSDOS / PC DOS version 3.1 or greater.
Microsoft Windows® version 3.0 or greater operating
in either standard or 386 enhanced mode).
The Windows 3.0 System is a multitasking operating
system which will allows the developer to take full
advantage of the many powerful features and functions of the PICMASTER system.
1 Mbyte RAM (2 Mbytes recommended).
• One 5.25" floppy disk drive.
PIC MASTER emulation can operate in one window,
while a text editor is running in a second window.
Dynamic Data Exchange (DOE), a feature of Windows
3.0, will be available in this and future versions of the
software. DOE allows data to be dynamically transferred
between two or more Windows programs. With this
feature, data collected with PICMASTER can be automatically transferred to a spreadsheet or database
program for further analysis.
• Approximately 10 Mbytes of hard disk (1 Mbyte
required for PICMASTER, remainder for Windows
3.0 system).
• One 8-bit PC AT (ISA) I/O expansion slot (half size)
• Microsoft® mouse or compatible (highly recommended).
20.1.2 Emulator System Components:
Under Windows 3.0, two or more PICMASTER emulators can run simultaneously on the same PC making
development of multi-microcontroller systems possible
(e.g., a system containing a PIC16C5x processor and a
PIC17Cxx processor).
The PICMASTER Emulator Universal System consists
primarily of 4 major components:
Host-Interface Card: The PC Host Interface Card
connects the emulator system to an IBM PC compatible system. This high-speed parallel interface requires a single half-size standard AT / ISA slot in the
host system. A 37-conductor cable connects the
interface card to the external Emulator Control Pod.
• Emulator Control Pod: The Emulator Control Pod
contains all emulation and control logic common to all
microcontroller devices. Emulation memory, trace
memory, event and cycle timers, and trace/breakpoint
logic are contained here. The Pod controls and
interfaces to an interchangeable target-specific emulator probe via a 14" precision ribbon cable.
© 1992 Microchip Technology Incorporated
DS30075C-page 38
1-98
FIGURE 20.1.1 - PICMASTER-16
FIGURE 20.1.2 - PICMASTER-16 SYSTEM CONFIGURATION
Aux.
0'1111111111111111111111.
Common Interface Card
PC Compatible Computer
(AT/ISA Bus) (for Industry Standard Architecture)
PC-Interface
PICMASTER Emulator Pod
© 1992 Microchip Technology Incorporated
DS30075C-page 39
1-99
FIGURE 20.1.3 - PICMASTER-16 TYPICAL
SCREEN
mode. PICSIM uses two forms of symbolic debugging:
an internal symbol table for disassembling opcodes and
the displaying of source code from a listing file. PICSIM
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi project software development tool.
PIC-MASTER- O:\ICEWIN\DDEDEMO.OBJ
file
!;onfrgure
.setup
Watch
Bun
.l.!tlJlty
WlndQw
Help
20.5 PIC PRO-II Programmer
PICPRO II is a production quality programmer with both
stand-alone and PC based operation. The PICPRO II
will program the entire family of PIC16C5X series of 8bit microcontrollers. It can read, program, verify, and
code protect parts without the need of a PC host. Its
EEPROM memory holds programming data and parametric information even when power is removed making
it ideal for duplicating PICs. It can also operate with a PC
host and do complete read, program, verify, as in standalone mode with the additional features of program
buffer editing, serialization of both code-protected and
non code-protected parts. The PICPRO II comes with
both 28 and 18 pin zero insertion force programming
sockets on a removable socket module. Additional
socket modules are available for the SOIC and PLCC
packages. The PICPRO II conforms fully to Microchip's
Programming Algorithm. Its programmable Vcc and VPp
supplies allow the PICPRO II to support PIC microcontrollers with various operating voltage ranges. PICPRO
II can read and verify the ROM code and configuration
fuses for a non code-protected PIC16CR54.
20.2 PICPAK-IITM Development Kit
When real time or in-circuit emulation is not required for
code development the PICPAK-II(PIC Applications Kit)
offers the right solution. This very low cost PC hosted
software development tool combines the power and
versatility of the PICALC assembler and PICSIM simulator software tools to compile, execute, debug and
analyze microcode in a PC hosted environment. Microcode debugging capability includes software trace,
breakpoints, symbolic debug and stimulus file generation. An EPROM PIC Programmer and "Quick Start"
PIC16C5X product sample PAK is included for final
code verification.
20.6 ORDERING DEVELOPMENT
TOOLS
20.3 PICALC Cross-Assembler
The PIC Cross Assembler PICALC is a PC hosted
software development tool supporting the PIC16C5X
series microcontrollers. PICALC offers a full featured
Macro and Conditional assembly capability. It can also
generate various object code formats including several
Hex formats to support Microchip's proprietary development tools as well as third party tools. Also supports
Hex (default), Decimal and Octal Source and listing
formats. An assembler users manual is available for
detailed support.
The development tools are packaged as comprehensive systems for your convenience. Their description
and planned availability dates are as follows:
System
PIC-PAK-IITM
PICMASTER·16
20.4 PICSIM Software Simulator
PICSIM is a software tool which allows for PIC16C5X
code development in a PC host environment. The
PICSIM software allows you to simulate the PIC16C5X
series microcontroller products on an instruction level.
On any given instruction, the user may examine or
modify any of the data areas within the PIC or provide
external stimulus to any of the pins. The input/output
radix can be set by the user and the execution can be
performed in single step, execute until break or in a trace
PIC PRO II
DS30075C-page 40
Description
Includes:
PICALC Assembler
PICSIM, PICPRO II Simulator
Programmer Manuals
Includes:
PICALC Assembler
PICPRO " Programmer
PICALC Assembler
PICSIM Simulator
PIC16C5X Personality Module
Includes:
PICPRO II Programmer
DIP Socket Module
Manuals
Available
Now
Now
Now
© 1992 Microchip Technology Incorporated
HOO
21.0 CURRENT PRODUCT
AVAILABILITY
The following selections are currently available (for the
Part-Number coding, refer to the back page):
Oscillator
Type
Tempi
Package
Descriptions
RC,XT,HS'orLP
IP
PDIP, O'C to +70'C
RC, XT, HS'orLP
RC, XT, HS' or LP
RC, XT, HS' or LP
liP
ISO
I/SO
PDIP, -40'C to +85'C
SOIC, O'C to +70'C
SOIC, -40'C to +85'C
• Consult local sales office for availability of HS parts.
DS30075C-page 41
© 1992 Microchip Technology Incorporated
1-101
Notes
DS30075C-page 42
© 1992 Microchip Technology Incorporated
1-102
Index
Absolute maximum specs ....................................... 23
AC characteristics (XT,RC,HS,LP) COM/IND ......... 26
Block diagrams:
Chip .................................................................... 3
I/O Pin .............................................................. 12
Power On Reset ............................................... 20
RTCC (Simplified) .............................................. 7
RTCC & WDT .................................................. 15
Brown-out protection circuit ..................................... 19
Code protection ....................................................... 22
Configuration fuses ................................................. 21
Data memory map ..................................................... 6
DC characteristics (RC,XT,HS,LP) COM .......... 24, 25
DC characteristics (RC,XT,HS,LP) IND ............ 24, 25
Development tools .................................................. 37
External power on reset circuit ................................ 18
Features overview ..................................................... 1
File register descriptions
fO .•.........................•..........................................•. 7
f1 ........................................................................ 7
f2 ........................................................................ 8
f3 ...................................................................... 10
f4 ...................................................................... 11
I/O ports ............................................................. 11,12
10 locations ............................................................. 21
Indirect addressing .................................................... 7
Instruction set .......................................................... 16
OPTION register .................................................... , 13
Oscillator ............................................................ 17,18
Oscillator Start-up Timer ............................... '" ....... 19
OTP devices .............................................................. 5
Package information ................................... 35, 36, 37
Page select (Program memory) ................................ 5
PO bit ...................................................................... 11
Pin-out information .............................................. 1, 23
Power Down mode (SLEEP) ................................... 21
Power On Reset ................................................. 19,20
Prescaler (RTCCIWDT) .......................................... 14
Program Counter ....................................................... 8
QTP devices .............................................................. 5
Real Time Clock/Counter (RTCC) ............... 7, 8, 9, 27
RESET .................................................................... 14
SLEEP ..................................................................... 21
Stack ......................................................................... 9
Status register ......................................................... 10
Timing diagrams
I/O pin .............................................................. 13
I/O timing for I/O ports ...................................... 27
Oscillator Start-up timing .................................. 27
Power On Reset ......................................... 20, 21
RTCC timing ............................................ 8, 9, 27
TObit ...................................................................... 11
TRIS registers ......................................................... 13
Typical characteristics graphs
IDD vs freq ........................................................ 31
IOH vs VOH ....................................................... 33
IOL VS VOL ....................................................... 33
Ipd VS VDD Watchdog ....................................... 29
Ipd VS VDD Watchdog ....................................... 29
RC osc freq vs temp ........................................ 28
RC osc freq vs VDD ................................... 28, 29
Transconductance of HS osc VS VDD .............. 32
Transconductance of LP osc VS VDD ............... 32
Transconductance of XT osc VS VDD .............. 32
VIH, VIL of MCLR, RTCC and OSC1 vs VDD .... 30
VTH of I/O pins vs VDD ..................................... 30
VTH of OSC1 Input in XT, HS and LP Modes
vs VDD .............................................................. 30
WDT period vs VDD ......................................... 32
UV Erasable devices ................................................. 5
W register ................................................................ 13
WDT ........................................................................ 17
DS30075C-page 43
© 1992 Microchip Technology Incorporated
1-103
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices. For the currently available code-combinations, refer to previous page.
Examples:
a) PICI6CR54 - XT/PI69
PART NO. - XX X IXX XXX
-:-
0-'
Package:
I
3-Digit Pattern Code
P
SO
Temperature I
I Range:
b) PICI6CR54· LP
1180592
="Xr' oscillator, commercial
temp., PDIP, with ROM
pettern 169
="LP" oscillator, Industrial
temp., SOIC device with
ROM code 592
= PDIP
= SOIC (Gull Wing Lead)
= O'C to
= -40' C to
+70'C
+85'C
II
RC
XT
HS
LP
II Device,.
PIC16CR54
PIC16CR54T (In tape and reel, in SOIC package only)
Oscillator
Type:
DS30075C-page 44
© 1992 Microchip Technology Incorporated
1-104
Microchip
8-Bit CMOS EPROM Microcontroller with AID Converter
FEATURES
CMOS technology
• Low power, high speed CMOS EPROM technology
• Fully static design
Wide operating voltage range:
Commercial: 3.0V to 6.0V
- Industrial: 3.0V to 6.0V
- Automotive: 3.0V to 6.0V
• Low power consumption
<2 mA@5V, 4 MHz
- 151lA typical @ 3V, 32 KHz (with AID off)
- < 1 IlA typical standby current @ 3V
High Performance RISC·like CPU
Only 35 single word instructions to learn
• All single cycle instructions (200 ns) except for
program branches which are two-cycle
Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 14-bit wide instructions
• a-bit wide data path
1024 x 14 on-chip EPROM program memory
• 36 x a general purpose registers (SRAM)
• 15 special function hardware registers
• a levels deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources: ExternallNT pin, RTCC
timer, AID conversion completion and interrupt on
change on four port B pins
FIGURE A· PIN CONFIGURATION
PDIP, SOIC, CERDIP Window
___
---..
---------..
Peripheral features
13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• a bit real time clock/counter (RTCC) with a-bit
programmable prescaler
AID converter module:
4 analog inputs multiplexed into one AID
converter
Sample and hold
20 Ils conversion time/channel
a-bit resolution with ±1 LSB accuracy
External reference input, VREF (VREF ~ Voo)
Analog input range: Vss to VREF
RA4/RTCC
MCLRNpp [
Vss
RBO/INT
RB1
RB2
RB3
I::
·1
2
3
4
5
6
?
8
§
§
9
~
18 ~ RA1/AIN1
RAO/AINO
16 ] OSC1
15 ] OSC2/CLKOUT
14 ~ Voo
13 ~ RB?
12 ] RB6
11
RB5
RB4
10
17 ]
""0
§
CI>
0
:::!
§
------------
..-
-----
INTRODUCTION
Power on reset
Power up timer
Oscillator start-up timer
Watchdog timer (WDT) with its own on-chip RC
oscillator for reliable operation
Security EPROM fuse for code-protection
Power saving SLEEP mode
User selectable oscillator options:
RC oscillator: RC
- Crystal/resonator: XT
- High speed crystal/resonator: HS
- Power saving low frequency crystal: LP
Serial, In-System Programming (ISP) of EPROM
program memory using only two pins
© 1992 Microchip Technology Incorporated
§
The PIC16C71 is a high performance, low cost, CMOS,
fully static EPROM based a-bit microcontroller with onchip Analog to Digital converter.
It is the first member of a new and improved family of
PIC16CXX microcontrollers (customers familiar with the
PIC16C5X products may refer to Appendix A for a list of
enhancements).
Its high performance is due to all single word instructions
(14-bit wide) that are executed in single cycle (200 ns at
20 MHz clock) except for program-branches which take
two cycles (400 ns).
The PIC16C71 has four interrupt sources and an eight
level hardware stack.
Special microcontroller features
•
•
•
•
RA2/AIN2 [
___ RA3/AIN3NREF
The peripherals include an a bit timer/counter with a bit
prescaler (effectively a 16 bit timer), 13 bi-directionall/O
pins and an a bit AID converter. The high current drive
(25 mA max. sink, 20 mA max source) olthe I/O pins help
reduce external drivers and therefore, system cost.
The AID converter has four channels, sample and hold,
a bit resolution with ±1 LSB accuracy. Conversion time
is typically 30 I-ls including sampling time.
The PIC16C71 product is supported by an assembler,
an in-circuit emulator and a production quality programmer. All the tools are supported on IBM PC and
compatible machines.
~ u@ ~ 0M 0IT1l illHI'W
1-105
D8301508 - page 1
FIGURE B: PIC16C71 BLOCK DIAGRAM
RAO/AINO
EPROM
Program
Memory
lK x 14
RAl/AINl
RA2/AIN2
RA3/AIN31
VREF
Direct Addr <7>
RTCC/RA4
Oscillator
Start-up Timer
OSCl
OSC2/CLKOUT
MCLR
VDD, Vss
4.1
4.2
5.0
5.1
5.2
Table of Contents
Features ............................
......................................................... 1
Introduction .............................
",1
General Description ...
1.0
.. ................... 4
Upward Compatibility with PIC16C5X
1.1
.... 4
.. ............ ........
.. 4
Applications............. .
1.2
2.0
PIC16C71 Device Varieties ................................................4
2.1
UV Erasable Devices ......................................................... 4
2.2
One-Time-Programmable (OTP) Devices ......................... .4
2.3
Quick-Turnaround-Production (QTP) Devices ...
.. ...... 4
3.0
Architectural Overview......
.. ................................. .4
3.1
PIC16C71 Pinout Description ............................................. 5
3.2
Clocking Scheme/Instruction Cycle .................................... 5
3.3
Instruction Flow/Pipelining .................................................. 5
3.4
Program Memory Organization .......................................... 7
Program Counter Module ................................................... 7
3.5
Stack ................................................................................. 7
3.6
Register File Organization .................................................. 7
3.7
Indirect Addressing Register .............................................. 7
3.8
STATUS Register (103) ...................................................... 8
3.9
3.9.1
Carry/Borrow and Digit Carry/Borrow Bits .......................... 8
3.9.2
Time Out and Power Down Status Bits (TO, PD) ............... 8
3.10
Arithmetic and Logic Unit (ALU) ....................................... 10
3.11
W Register ........................................................................ 10
3.12
Interrupts .......................................................................... 10
INT Interrupt ................................................................... 11
3.12.1
RTCC Interrupt ................................................................. 11
3.12.2
Port RB Interrupt ...............
.. .............................. 11
3.12.3
A/D Interrupt.....................
.. ............................... 11
3.13
4.0
Instruction Set Summary
................................. 11
DS301508 - page 2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.6
5.7
5.8
5.8.1
6.0
6.1
6.2
6.3
6,3,1
6.3.2
6.3.3
6.4
6.4.1
6.4.2
6.4.2.1
6.5
Instruction Set .........
.. ..... 12
Instruction Description
........... 13
Special Features of the CPU .............
... 18
Reset .....
.............................. ...........
.. ... 18
Power-on· Reset (POR), Power-up·Timer (PWRT) and
Oscillator Start-up Timer ..................................
.. ....... 18
Watchdog Timer (WDT) ........
.. ......... 21
WDT Period ................................................................. 21
WDT Programming Considerations ................................. 21
Oscillator Configurations ..................................
...21
Oscillator Types .......
.. ............................. 21
Crystal Oscillator .... .
.. ....... 21
RC Oscillator ...............
.. ........... 22
Power Down Mode (SLEEP)
.................. 23
Wake-up from SLEEP .............................................. 23
.. ..... 23
Configuration Fuses ......................
ID Locations ................................................................. 24
Code Protection .............................................................. 24
Verifying a Code-Protected PIC ....................................... 24
Overview of Peripherals ................................................... 24
PortA .......................................................... ,,, ..... ,........... " 24
PortB ................................................ ",,,., .. ,,.,, .................. 25
I/O Programming Considerations ..................................... 27
Bidirectional I/O Ports .......................................
.. .... 27
Successive Operations on 1/0 Ports ...........
... 28
Operation in Noisy Environment ....................................... 28
Real Time Clock/Counter (RTCC) .................................... 28
Using RTCC with External Clock ...................................... 28
Prescaler .......... ............ .......... .......
.. .......... 30
Switching Prescaler Assignment .................................... 30
OPTION Register ........................................................... 30
~u@~ 0M 0mlCIDuW
1-106
©1992 Microchip Technology Incorporated
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
8.0
9.0
10.0
10.1
10.2
AID Converter ................................................................... 32
AID Clocking Scheme ...................................................... 33
AID Operation During SLEEP .......................................... 33
Analog Input Connection Considerations ......................... 33
Sample and Hold (S/H) .................................................... 35
Transfer Function ............................................................. 35
Summary of AID Registers ............................................... 35
Electrical Characteristics .................................................. 35
DC Characteristics ........................................................... 36
DC Characteristics ........................................................... 37
DC Characteristics ........................................................... 38
AC Characteristics ............................................................. 39
AC/DC Characteristics ..................................................... 40
AC/DC Characteristics ..................................................... 41
Electrical Structure of Pins ............................................... 42
Timing Diagrams .............................................................. 42
DC and AC Characteristics Graphsrrables ...................... 43
Packaging Diagrams and Dimensions ............................. 51
18-Lead Plastic Dual In-Line (.300 mil) ............................ 51
18-Lead Plastic Surface Mount (SOIC - Wide,
300 mil Body) ................................................................... 52
Package Marking Information ........................................... 53
10.3
11.0
Programming the PIC16C71 ............................................ 54
11.1
Hardware Requirements .................................................. 54
11.2
Programming Mode Entry ................................................ 54
11.3
User Program Memory Map ............................................. 54
Serial ProgramNerify Operation ...................................... 54
11.4
Load Configuration ........................................................... 54
11.4.1
11.4.2 Load Data ......................................................................... 54
11.4.3 Read Data ........................................................................ 54
11.4.4 Increment Address ........................................................... 54
11.4.5 Begin Programming .......................................................... 56
11.4.6 End Programming ............................................................ 56
Development Support ....................................................... 57
12.0
12.1
PICMASTER: High Performance Universal In-Circuit
Emulator System .............................................................. 57
12.1.1
Host System Requirements .............................................. 57
12.1.2 Emulator System Components ......................................... 57
PICALC Cross-Assembler ................................................ 59
12.2
12.3
PRO MASTER ................................................................. 59
Appendix A ...................................................................................... 60
Appendix B ...................................................................................... 60
Sales and Support ........................................................................... 64
6.4.2.1
6.5.1
6.6.1
3.2.1
3.4.1
3.5.1
3.7.1
3.9.1
3.12.1
3.12.2
5.0.1
VIH, VILol MCLR, RTCC and OSCI (in RC Mode)
vs Vee. ................................
....................................................... 46
VTH (Input Threshold Voltage) of OSCI Input (In XT,
HS, and LP Modes) vs Veo.. .
.. .......46
9.0.12 Typical lee vs Freq. (EXT Clock, 25'C) ........................... .47
9.0.13 Maximum lee vs Freq. (EXT Clock, -40' to +85'C) .......... 47
9.0.14 WDT Timer Time-out Period vs Voe .............................................. 48
9.0.15 Transconductance (gm) of HS OScillator vs Vee .................. 48
9.0.16 Transconductance (gm) of LP OScillator vs Voe ................... 48
9.0.17 Transconductance (gm) of XT OSciliatorvs Veo ................48
9.0.18
10H vs VOH, Vee = 3V ........................................................ 49
9.0.19
10H vs VOH, Vee = 5V ........................................................ 49
9.0.20
10L VS VOL, Vee = 3V ......................................................... 49
9.0.21
10L VS VOL, Vee = 5V ......................................................... 49
11.3.1
Program Memory Mapping ............................................... 55
11.4.2.2 Load Data Command (Serial ProgramNerify) .................. 56
11.4.3.1 Read Data Command (Serial ProgramNerify) ................. 56
11.4.4.1 Increment Address Command (Serial ProgramNerify) .... 56
PICMASTER .................................................................... 58
12.1.1
12.1.2 PICMASTER System Configuration ................................. 58
12.1.3 PICMASTER Typical Screen ............................................ 59
Table of Tables
Time-out Sequence on Power-up (MCLR not Tied
to Vee): Case 1 ................................................................. 20
5.2.2
Time-out Sequence on Power-up (MCLR not Tied
to Vee): Case 2 ................................................................. 20
5.2.3
Time-out Sequence on Power-up (MCLR not Tied
to Vee) .............................................................................. 20
External Power on Reset Circuit ...................................... 21
Brown Out Protection Circuit 1 ......................................... 21
Brown Out Protection Circuit 2 ......................................... 21
Crystal Operation (or Ceramic Resonator) (HS, XT or
LP OSC Configuration) ..................................................... 22
External Clock Input Operation (HS, XT or
LP OSC Configuration) ..................................................... 22
RC Oscillator (RC Type Only) .......................................... 23
Configuration Word .......................................................... 23
Block Diagram of RAO - RA3 Pins .................................... 24
Block Diagram of RM Pin ................................................ 25
Block Diagram of Port Pins RB<7:4> ............................... 26
Block Diagram of Port Pins RB<3:0> ............................... 26
RTCC Block Diagram (Simplified) .................................... 29
RTCC Timing: INT ClockINo Prescale ............................. 29
RTCC Timing: INT ClockiPrescale 1:2 ............................. 29
RTCC Timing with External Clock .................................... 30
5.4.2
5.4.3
5.6.1
6.1.1
6.1.2
6.2.1
6.2.2
6.4.1
6.4.2
6.4.3
6.4.1.1
© 1992 Microchip Technology Incorporated
Electrical Structure of MCLR and RTCC Pins .................. 42
RTCC Timing .................................................................... 42
Oscillator Start-up Timing (PICI6C71RC) ........................ 42
InpuVOutput Timing for 1/0 Ports ..................................... 42
Typical RC Oscillator Frequency vs. Temperature ........... 43
. .................... 43
Typical RC Oscillator Frequency vs Vee...
. ..... ..43
Typical RC Oscmator Frequency vs Vee... .
. ....... 44
Typical RC Oscillator Frequency vs Vee...
Typicallpd vs Vee Watchdog Disabled 25'C .................. .44
Typicallpd vs Vee Watchdog Enabled 25'C .................... 44
Maximum Ipd vs Voe Watchdog Disabled ........................ 45
Maximum Ipd vs Vee Watchdog Enabled ........................ .45
VTH (Input Threshold Voltage) of I/O Pins vs Vee ................. 45
9.0.10
Pin Configuration ................................................................ 1
PIC16C71 Block Diagram .................................................. 2
Clock/Instruction Cycle ....................................................... 6
Program Memory Map and Stack ....................................... 6
Loading of PC in Different Situations ................................. 6
Data Memory Map .............................................................. 7
Status Register ................................................................... 9
Interrupt Logic .................................................................. 10
INTCON Register ............................................................. 10
Simplified Block Diagram of On-Chip Reset Circuit ......... 18
5.2.1
5.2.4
5.2.5
5.2.6
5.4.1
7.6.2
8.0.1
8.0.2
8.0.3
9.0.1
9.0.2
9.0.3
9.0.4
9.0.5
9.0.6
9.0.7
9.0.8
9.0.9
9.0.11
Table of Figures
A
B
6.6.2
6.6.3.1
6.6.5.1
7.6.1
Block Diagram of the RTCCIWDT Prescaler .................... 31
OPTION Register ............................................................. 31
AID Control and Status Register (ADCONO,
ADDRESS 08h) ................................................................ 32
AID Control Register (ADCON1, Address 88h) ................ 33
Analog Input Model .......................................................... 34
Transfer Function ............................................................. 34
Electrical Structure 01 1/0 Pins (RA, RB) .......................... 42
3.9.2.1
3.9.2.2
4.1
5.1.1
5.2.1
5.4.1
5.4.2
6.1.1
6.1.2
6.2.1
6.2.2
6.4
9.0.1
9.0.2
11.4.1
Events Affecting porro Status Bits ................................... 8
porro Status After Reset .................................................. 8
Instruction Set .................................................................. 12
Reset Conditions for Registers ......................................... 19
Time-out in Various Situations ......................................... 19
Capacitor Selection for C?eramic Resonators ................... 22
Capacitor Selection for Crystal Oscillator ......................... 22
PortA Functions ................................................................ 25
Summary of PortA Registers ............................................ 25
PortB Functions ................................................................ 27
Summary of PortB Registers .................................... ,....... 27
Summary of RTCC Registers ........................................... 30
RC Oscillator Frequencies ............ ,.................................. 44
Input Capacitance ............................................................ 50
Command Mapping (Serial Operation) ............................. 55
Trademarks:
PIC is a registered trademark of Microchip Technology
Incorporated.
PICMASTER, PICPAK, PICPRO and PRO MASTER are
trademarks of Microchip Technology Incorporated.
IBM PC is a registered trademark of IBM Corporation.
MS DOS and Microsoft Windows are registered trademarks
of Microsoft Corporation.
~[l'®~ 0mFil 0ITi)@l[l')j
1-107
DS30150B - page 3
1.0 GENERAL DESCRIPTION
2.0 PIC16C71 DEVICE VARIETIES
The PIC16C71 is a low cost, high performance, CMOS,
fully static, EPROM-based 8-bit microcontroller with onchip analog to digital converter. It employs an advanced
RISC-like architecture. A reduced set of 35 instructions,
all single word instructions (14-bit wide), all single cycle
instructions (200ns) exceptfor2-cycie program branches,
instruction pipe-lining, large register set and separate
instruction and data memory (Harvard architecture)
schemes are some of the architectural innovation used
to achieve very high performance. The PIC16C71
typically achieves a 2:1 code compression and a 5:1
speed improvement over other 8 bit microcontrollers in
its class.
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information and tables in this section. When
placing orders, please use the "PIC16C71 Product
Identification System" on the back page of this data
sheet to specify the correct part number.
2.1 UV Erasable Devices
The UV erasable version, offered in cerdip package is
optimal for prototype development and pilot series.
The UV erasable version can be erased and reprogrammed to any of the oscillator modes etc. Microchip's
PRO MASTER'" programmer supports programming of
the PIC16C71.
The PIC16C71 is equipped with special features to
reduce external components and thus reduce cost,
enhance system reliability and reduce power consumption. There are four oscillator options, of which the single
pin RC oscillator provides a low cost solution and the LP
oscillator minimizes power consumption. The SLEEP
(power down) mode offers power saving. The user can
wake up the chip from SLEEP through external interrupts and reset.
2.2 One-lime-Programmable (OTP) Devices
The availability of OTP devices is especially useful for
customers expecting frequent code .changes and updates.
A highly reliable watchdog timer with its own on-chip RC
oscillator provides protection against software malfunction.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the oscillator fuses, configuration
fuses and optionally, the 10 locations must be programmed.
The UV-erasable cerdip-packaged versions are ideal for
code development while the cost-effective One Time
Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP
microcontroller while benefiting from the OTP flexibility.
2.3 Quick-lurnaround-Prodyctjon (QIP)
Devices
Those users familiar with the PI.C16C5X family of microcontrollers will realize that this is an improved version of
the PIC16C5X architecture. Please refer to Appendix A
for a detailed list of modifications. Code written for
PIC16C5X can be easily ported to PIC16C71 (see
Appendix B).
Microchip offers a aTP Programming Service forlactory
production orders. This service is made available for
users who chose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and fuse options already
programmed by the factory. Certain code and p~ototype
verification procedures do apply before production shipments are available. Please contact your Microchip
Technology sales office for more details.
1.2 APPLICATIONS
3.0 ARCHITECTURAL OVERVIEW
The PIC 16C71 fits perfectly in applications ranging from
high speed automotive and appliance motor control to
low-power remote sensors, pointing devices, and telecom processors. The EPROM technology makes customization of application programs (transmitter codes,
motor speeds, receiver frequencies, etc.) extremely fast
and convenient. The small footprint packages forthrough
hole or surface mounting make this microcontroller
series perfect for all applications with space limitations.
Low cost, low power, high performance, ease of use,
and 1/0 flexibility makes the PIC16C71 very versatile
even in areas where no microcontroller use has been
considered before (e.g. timer functions, replacement of
"glue"logic in larger systems, co-processor applications).
The high performance of the PIC16C71 can be attributed to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC16C71 uses a Harvard architecture, in which, program and data are accessed from separate memories.
This improves bandwidth over traditional Von-Neuman
architecture where program and data are fetched from
the same memory. Separating program and data memory
further allows instructions to be sized differently than 8bit wide data word. In PIC16C71, op-codes are 14-bit
wide making it possible to have all single word instructions. A 14 bit wide program memory access bus fetches
a 14 bit instruction in a single cycle. A two-stage pipeline
1.1 UPWARD COMPATIBILITY WITH
PIC16C5X
D5301508 • page 4
~[J@~ 0mm 0[ffie~)[l'W
1-108
© 1992 Microchip Technology Incorporated
overlaps fetch and execution of instructions. Consequently, all instructions (35 in all) execute in a single
cycle (200ns @ 20 MHz) except for program branches.
-3.2 Clocking Schemellnstruction Cycle
The clock input (from pin OSC1) is internally divided by
four to generate four non overlapping quadrature clocks
namely01, 02, 03 and 04. Internally, PC is incremented
every 01, instruction is fetched from program memory
and latched into instruction register in 04. It is decoded
and executed during the following 01 through 04. The
clocks and instruction execution flow is shown in Figure
3.2.1.
The PIC16C71 address 1Kx 14 program memory space,
all on-chip. Program execution is internal only
(microcontroller mode).
The PIC16C71 can directly or indirectly address its 48
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C71 has a fairly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any addressing mode. This symmetrical nature and lack of
'special optimal situations' make programming with the
PIC16C71 simple yet efficient. In addition, the learning
curve is reduced significantly.
3.3 INSTRUCTION FLOW/PIPELINING
An "Instruction Cycle" in PIC16C71 consists of 01, 02,
03 and 04. Instruction fetch and execute are pipelined
such that fetch takes one instruction cycle while decode
and execute takes another instruction cycle. However,
due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program
counter to change (e.g. GOTO) then two cycles are
required to complete the instruction.
A fetch cycle begins with the program counter (PC)
incrementing in 01.
3.1 - PIC16C71 PINOUT DESCRIPTION
Pin function
Pin name
Pin Type
Normal operation
Serial In-System
Programming (ISP) Mode
Voo
P
Power
Power
Vss
P
Ground
Ground
OSCl
I
Clock input/oscillator connection
OSC2/CLKOUl
I/O
Oscillator connection/CLKOUl output. It is CLKOUl in RC
oscillator mode and oscillator connection in all other modes.
MCLR/Vpp
I/P
Master clear \external reset) in~ut. Active low.
It has Schmit trigger input bu er.
RA4/RlCC
I/O
Open-drain out~ut/input pin. It is also the clock input to RlCC
timer/counter: chmltt trigger input buffer
-
RAO/AINO
110
Bidirectional I/O pin/Analog input channel O. As digital input it
has TIL input levels
-
RA1/AIN1
liD
Bidirectional I/O pin/Analog input channel 1. As digital input it
has TIL input levels
-
RA2/AIN2
I/O
Bidirectional I/O pin/Analog input channel 2. As digital input it
has TIL input levels
-
RA3/AIN3NREF
I/O
Bidirectional I/O pin/Analog infut channel 3/Analog reference
voltage input. As digital inpu it has TIL input levels
-
RBO/INl
I/O
Bidirectional 110 pin/External interrupt input. TIL input levels
RBl
I/O
Bidirectional 110 pin. TIL input levels
RB2
I/O
Bidirectional I/O pin. TIL input levels
-
RB3
I/O
Bidirectional I/O pin. TIL input levels
RB4
I/O
Bidirectional I/O pin. TIL input levels
RB5
I/O
Bidirectional 110 pin. TIL input levels
RB6
I/O
Bidirectional 110 pin. TIL input levels
Clock input
RB?
I/O
Bidirectional 110 pin. TIL input levels
Oata input/output
Master clear/programming
voltage (Vpp) supply
-
-
Legend: I =input, 0 =output, I/O =input/output, P =power. -: Not used.
© 1992 Microchip Technology Incorporated
~[I®~DMD[llJamIW
1-109
08301508 - page 5
PIC®16C71
FIGURE 3.2.1 - CLOCK/INSTRUCTION CYCLE
01
02
03
I
04
02
01
03
I
04
02
01
04
I
~,
' - -_ _ _ _ _---'~~_ _ _ _ _ _ _' }
01 ' [ - - \ ' - -_ _ _ _ _-----'
02
I
03
OSC1
~\L------'-----'
\ :
I
03 ;-'_ _ _ _~~~_ _-;-_ _ _ _-'~L_ __<_-----~
04
L -_ _ _ _ _ _ _
PC
(Program Counter)
~~
Internal
Phase
Clocks
~L-------~~
PC
PC + 2
OSC2/ClKOUT
(RC Mode)
Fetch INST (PC)
Execute INST PC-1
Fetch INST PC+ 1
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+ 1)
FIGURE 3.4.1 - PROGRAM MEMORY MAP AND STACK
OOOOh
13
0004h
OOOSh
On-chip
Program
Memory
•
•
•
03FFh
0400h
1FFFh
FIGURE 3.5.1 - LOADING OF PC IN DIFFERENT SITUATIONS
12
PC
8 7
1L-__
0
-1!INST with PCl (02h) as dest
--X_ _ _: _ _ _ _-----;OC-_ _ _ _
9. PClATH <4:0>
5j[
1~
8/
l':===J"7-'~=='
AlU result
PClATH
~~L-
____________, ,_ _ _ _ _ _
GOTO, CAll
~
~==t==::J Opcode (10:0)
PClATH
DS30150B - page 6
~ [I@ ~ 0QV[] 0ITll ®[lW
1-110
© 1992 Microchip Technology Incorporated
The fetched instruction is latched into the "Instruction
Register (IR)" which is decoded and executed during
02,03 and 04. Data memory is read during 02 (operand read) and written during 04 (destination write).
FIGURE 3.7.1 - DATA MEMORY MAP
File
Address
,----------.----------,
00
80
3.4 Program Memory Organization
The PIC16C71 has a 13-bit program counter capable of
addressing an 8K x 14 program memory space. In
PIC16C71 only the first 1K x 14 (OOOOh - 03FFh) are
physically implemented. Accessing a location above
3FFh will cause a wrap-around within the first 1K x 14
space. The reset vector is at OOOOh and the interrupt
vector is at 0004h.
01
81
02
82
03
83
04
84
05
06
09
OA
08
85
86
87
88
89
8A
88
OC
8C
07
3.5 Program Counter Module
08
The program counter (PC) is 13-bit wide. The low byte,
PCl is a readable and writable register (02h). The high
byte of the PC, PCH is not directly readable or writable.
The high byte of the PC can be written through the
PCLATH register (OAh). When the PC is loaded with a
new value during a CAll, GOTO or a write to PCl, the
high bits of PC are loaded from PClATH as shown in
figure 3.5.1.
3.6 Stack
36
general
purpose
registers
(SRAM)
The PIC16C71 has an 8 deep x 13 bit wide hardware
stack. The stack space is not part of either program or
data space and the stack pointer is not readable or
writable. The PC is pushed in the stack when a CAll
instruction is executed or an interrupt is acknowledged.
The stack is popped in the event of a RETURN, RETlW
or a RETFIE instruction execution. PCLATH (OAh) is not
affected by a PUSH or a POP operation.
mapped
in page 0
3.7 Register File Organization
2F
AF
The register file, in PIC16C71 is organized as 128 x 8. It
is accessed either directly or indirectly through file select
register FSR. It is also referred to as the data memory.
There are several register file page select bits in the
STATUS register allowing up to four pages. However,
in the PIC16C71 data memory extends only up to 2Fh.
The first 12 locations are used to map special function
registers. locations OCh - 2Fh are general purpose
registers implemented as static RAM. Some special
function registers are mapped in page 1. When in page
1, accessing locations 8Ch - AFh will access the RAM in
page 0 (Figure 3.7.1).
30
80
3.8 Indirect Addressing Register
Indirect addressing is possible by using file address OOh.
Any instruction using to as file register actually accesses
data pOinted to by the file select register, FSR (address
04h). Reading to itself indirectly will produce OOh.
Writing to fO indirectly results in' a no-operation (although
status bits may be affected).
7F
FF
Page 0
Page 1
• Not a physical register
II Unimplemented data memory locations; read as 'O's
© 1992 Microchip Technology Incorporated
[Fl [I@ ~ 0mru 0[fiJ@.HFW
1-111
DS301508 - page 7
3.9.2 TIME OUT ANP POWER paWN STATUS
BITS (TO PD)
3.9 STATUS Register (f03l
This register contains the arithmetic status of the ALU, the
RESET status, and the page preselect bits for data
memory.
The "TO" and "PD" bits in the status register f03 can be
tested to determine if a RESET condition has been
caused by a watchdog timer time-out, a power-up condition, or a wake-up from SLEEP by the watchdog timer
or MCLR pin.
These status bits are only affected by events listed in
Table 3.9.1.1.
The status register (f03) can be destination for any
instruction like any other register. However, the status
bits are set following the write. Furthermore, TO and PD
bits are not writable. Therefore, the result of an instruction
with status register as destination may be different than
intended. For example, CLRF f3 will clear all bits except
for TO and PD and then set the Z bit and leave status
register as 000UU100 (where U = unchanged).
TABLE 3.9.2.1 - EVENTS AFFECTING POI
TO STATUS BITS
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions are used to alter the status registers
because these instructions do not affect any status bit.
Event
For other instructions, affecting any status bits, see
section "Instruction Set Summary" (Section 4.0)
Power-up
WOTTImeout
SLEEP instruction
CLRWOT instruction
39.1 CARRY/BORROW ANP DIGIT CARRY/
BORROW BITS
The carry bit (C) is a carry out in addition operations
(ADDWF, ADDLW) and a borrow out in subtract operations (SUBWF, SUBLW). The following examples explain
operation of carrytborrow bit:
SUBLW
Ox01
Ox02
;wreg=l
;wreg= 2-wreg = 2-1=1
;Carry=l: result is positive
SUBLW
;wreg=2
;wreg=1-wreg=1-2=FFh
;Carry=O: Result is. negative
PO
a
a
1
1
U
; SUBWF Example #1
clrf
movlw
subwf
Ox20
1
Ox20
;SUBWF
movlw
movwf
clrw
subwf
Example #2
OxFF
Ox20
;f(20h)=FFh
;wreg=O
Ox20
;f(20h)=f(20h)-wreg=FFh-O=FFh
;Carry=l: Result is positive
1
a
1
U
No effect on PO
1
1
1
a
TABLE 3.9.2.2 - POITO STATUS AFTER
RESET
TO
Ox02
OxOl
Remarks
Note: A WDT timeout will occur regardless of the
status olthe TO bit. A SLEEP instruction will be
executed, regardless olthe status olthe PD bit.
Table 3.9.2.2 reflects the status of PD and TO
after the corresponding event.
;SUBLW Example #2
MOVLW
PO
U: unchanged
;SUBLW Example #1
MOVLW
TO
;f (20h)=O
;wreg=l
;f(20h)=f(20h)-wreg=O-1=FFh
;Carry=O:Result is negative
a
1
a
1
U
RESET was caused by
WOT wake-up from SLEEP
WOT time-out (not during SLEEP)
MCLR wake-up from SLEEP
Power-up
MCLR reset during normal operation
U: unchanged
Note: The PD and TO bit maintain their status until
an event of Table 3.9.2.1 occurs. A low-pulse
on the MCLR input does not change the PD
and TO status bits.
,
The digit c.1!!:!Y.QQerales in the same way as the carry bil,
i.e.: it is a borrow in subtract operations.
D8301508 - page 8
~[i'@~omruO[j'jJfill[i'W
1-112
© 1992 Microchip Technology Incorporated
FIGURE 3.9.1· STATUS REGISTER
bitO
I
IRP
I RP1
RPO
I TO I PD I
\_,../
Z
I
DC
I
C
L
~
ADDRESS:
03h
RESET CONDITION:
OOO??XXX
TO, PD are set or reset as shown in Table 3.9.2.1
I
CARRY/BORROW BIT:
For ADDWF, SUBWF , ADDLW and SUBLW instructions, this bit
is set if there is a carry out from the most significant bit of the
resultant.
Note that a subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF)
instructions, this bit is loaded with either the high or low order bit
of the source register.
DIGIT CARRY/BORROW BIT:
For ADDWF, SUBWF , ADDLW and SUBLW instructions, this
bit is set if there is a carry out from the 4th low order bit of the
resultant.
ZERO BIT:
Set if the result of an arithmetic or logic operation is zero.
Reset otherwise.
POWER DOWN BIT:
Set to "1" during power up or by a CLRWDT command. This bit
is reset to "0" by a SLEEP instruction.
TIME-OUT BIT:
Set to "1" during power up and by the CLRWDT and SLEEP
command. This bit is reset to "0" by a watchdog timer time out.
REGISTER PAGE SELECT BITS FOR DIRECT
ADDRESSING:
00: page a (OOh - 7Fh)
01 : page 1 (80h - FFh)
10 : page 2 (100h - 17Fh)
11 :page3(180h-1FFh)
Each page is 128 bytes.
Only RPO is useful in PIC16C71. Bit RP1 can be used as a
general purpose read/write bit. However, this may affect upward
compatibility with future products.
RP1,0:
REGISTER
PAGE
SELECT
BITS
FOR
INDIRECT
ADDRESSING:
IRP:
a : page 0,1 (OOh - FFh)
1 : page 2,3 (100h - 1FFh)
This bit is effectively not used in the PIC16C71.
It may be used as a general purpose read/write bit. However, this
may affect upward compatibility with future product.
© 1992 Microchip Technology Incorporated
~u@~ 0M 0ITlliilluW
1-113
OS30150B - page 9
A global interrupt enable bit, GIE (bit 7, INTCON) enables (if = 1) all un-masked interrupts or disables (if = 0)
all interrupts. Individual interrupts can be disabled
through their corresponding mask bit in INTCON register. GIE is cleared on reset.
3.10 Arithmetic and Logic Unit (ALU)
I
.1
~. .·.I
I'
:11
~I
I
The ALU is 8 bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are 2's complement in
nature. In two-operand instructions, typically one operand
is the working register (W register) or the accumulator.
The other operand is a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
3.11
When an interrupt is responded to, the GIE is cleared to
disable any further interrupt, the return address is pushed
into the stack and the PC is loaded with 0004h. Once in
the interrupt service routine the source(s) olthe interrupt
can be determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before re-
W Register
The W register is an 8-bit working register (or accumulator) used for ALU operations. It is not an addressable
register.
FIGURE 3.12.1 -INTERRUPT LOGIC
RTIF
RTIM
3.12 INTERRUPTS
INTF
INTM
The PIC16C71 has four sources of interrupt: external
interruptfrom RBO/INT pin, RTCC timer/counter overflow
interrupt, end of conversion interrupt from AJO module,
and interrupt on change on RB<7:4> pins. The interrupt
control register (lNTCON, addr OBh) records individual
interrupt requests in flag bits. It also has individual and
global mask bits. The only exception is AJO conversion
completion interruptflag (AOIF) which resides in AOCON
register.
interrupt
to CPU
ADIF
ADIM
RBIF
RBIM
GIE
FIGURE 3.12.2 - INTCON REGISTER
R/W
R/W
R/W
R/W
RIW
I GIE I AOIE I RTIE IINTE-I RBIE
RIW
r
RIW
R/W
RTIF1INTF I RBIFI
I bitO
Address:
OBh
R/W: Readable &
Power on reset
R:
value: 0000 OOOXb U:
writable
Read only
Unused,
read as '0'
RB port change interrupt
Set when RB<7:4> inputs
change. Reset in software
INT interrupt flag
Set when INT interrupt occurs
Reset in software
RTCC overflow interrupt flag
Set when RTCC overflows
Reset in software
RBIF interrupt enable bit
RBIE = 0: disables RBIF interrupt
RBIE = 1: enables RBIF interrupt
INT interrupt enable bit
INTE = 0: disables INTF interrupt
INTE = 1: enables INTF interrupt
RTIF interrupt enable bit
RTIE = 0: disables RTIF interrupt
RTIE = 1: enables RTIF interrupt
AID conversion interrupt enable bit
ADIE = 0: Disable ADIF interrupt
ADIE = 1: Enable ADIF interrupt
Global interrupt enable
0= Disable
1 = Enable
DS30150B - page 10
~[I@~DMOITll~Hrw
1-114
© 1992 Microchip Technology Incorporated
enabling interrupts to avoid recursive interrupts. Individual interrupt flag bits are set regardless of the status
of their corresponding mask bit or the GIE bit.
4.0 INSTRUCTION SET SUMMARY
Each PIC instruction is a 14-bit word divided into an OP
CODE which specifies the instruction type and one or
more operands which further specify the operation olthe
instruction. The PIC instruction set summary in Table4.t
lists byte-oriented, bit-oriented, and literal and control
operations.
The "return from interrupt" instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit to re-enable
interrupts.
3.12.1
INT Interrupt
External interrupt on RBO/INT pin is edge triggered:
either rising (if INTEDG = I, bitS of OPTION register) or
falling (if INTEDG = 0). When a valid edge appears on
INT pin, INTF bit is set (bitl, INTCON register). This
interrupt can be disabled by setting INTE control bit
(bit4, INTCON) to '0'. INTF bit must be cleared in
software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake up the
processor from SLEEP if INTE bit was set to 'I' prior to
going into SLEEP. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up. See section 5.5 for details on
SLEEP.
For byte-oriented instructions, "f" represents a file register designator and "d" represents a destination designator. The file register designator specifies which file
register is to be utilized by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If "d" is zero, the result is
placed in the W register. If "d" is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, "b' represents a bit field
designator which selects the number of the bit affected
by the operation, while "f" represents the number of the
.file in which the bit is located.
For literal and control operations, "k" represents an eight
or eleven bit constant or literal value.
3.12.2 BTCC Interrupt
RTCC interrupt is generated when the RTCC timerl
counter overflows from FFh to OOh. It sets the RTIF bit
(bit2, INTCON). The interrupt can be masked by setting
RTIE bit (bitS, INTCON) to '0'. RTIF bit must be cleared
in software in the RTCC interrupt service routine before
re-enabling this interrupt. The RTCC interrupt can not
wake the processor from SLEEP since the timer is shut
off during SLEEP.
All instructions are executed within one single instruction cycle, unless a conditional test is true orthe program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods. Thus,
for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 ~sec. If a conditional test is true
or the program counter is changed as a result of an
instruction, the instruction execution time is 2 ~ec.
3.12.3 Port Be Interrupt
Port B has an interrupt on change feature on four of its
pins, RB<7:4>. When configured as input, the inputs on
these pins are compared with the old latched value in
every instruction cycle. An active high output is generated on mismatch between the pin and the latch. The
"mismatch" outputs of RB4, RB5, RBS and RB7 are
OR'ed together to generate the RBIF interrupt (latched
in bitO, INTCON). Any pin configured as output is
excluded from the comparison. This interrupt can wake
the chip up from SLEEP. The user, in interrupt service
routine can clear the interrupt in one of two ways:
Notes to Table 4.1
Note 1:
in new code is strongly recommended against since
TRIS and OPTION are made addressible registers,
a) Disable the interrupt by clearing RBIM (bit3,
INTCON) bit.
the user may simply write to them. These instructions
may not be supported in future PIC16CXX products.
b) Read Port B. This will end mismatch condition.
Next, clear RBIF bit.
Note 2:
When an 1/0 register is modified as a function of itself
( e.g. MOVF 6,1 ), the value used will be that value
present on the pins themselves. For example, if the
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy
interface to a key pad and make it possible for wake-up
on key-depression.
data latch is "1" for a pin configured as input and is
driven low by an external device, the data will be
written back with a '0'.
Note 3: If this instruction is executed on file register fl (and,
3.13 AID INTERRUPT
where applicable, d=I), the prescaler will be cleared
if assigned to the RTCC.
The AID converter sets the end of conversion interrupt
flag, ADIF (bitt, ADCON) when a conversion is complete. The interrupt can be masked by setting ADIE bit
(bitS, INTCON) to '0'. See section S.S for details on AID
interrupt.
© 1992 Microchip Technology Incorporated
The PIC16C71 has 35 instructions. Two additional
instructions, TRIS and OPTION, are included only for
compatibility with the PIC16C5X products. Their use
[?J [J@ ~ 0mru 0[ilJ ~:)[IW
1-115
05301506 - page 11
4.1 INSTRUCTION SET
13
-.:·'1
I
BYTE-ORIENTED FILE REGISTER OPERATIONS
~,
(Hex) Name
Instruction·Binary
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0000
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
Hff
OXXX
dfff
dfff
dfff
dfff
dfff
dfff
dfff
Hff
OXXO
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
XXXX
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
07ff
05ff
018f
0100
09ff
03ff
OBff
OAff
OFff
04ff
08ff
008f
0000
DOff
OCff
02ff
OEff
06ff
MnemoniC, Operands
Add Wand I
AND Wand I
Clear 1
ClearW
Complement 1
Decrement I
Decrement I,Skip il Zero
Increment I
Increment !,Skip il zero
Inclusive OR Wand I
Move I
MoveWtol
No Operation
Rotate left I
Rotate right I
Subtract W Irom I
Swap halves f
Exclusive OR Wand I
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
I, d
I, d
I
·
f, d
f, d
I, d
f, d
I, d
f, d
f, d
I
·
I, d
f, d
I, d
I, d
I, d
8 7 6
0
OPCODE
I(FILE#)
d
d = 0 lor destination W
d = 1 lor destination I
1= 7-bit lile register address
Operation
Status affected Notes
I I
Wtl~d
C,DC,Z 2,3
Z
2,3
O~I
Z
3
O~W
Z
i~d
Z
2,3
1-1 ~ d
Z
2,3
1- 1 ~ d, skip if zero
None
2,3
It 1 ~d
Z
2,3
It 1 ~ d, skip il zero
None
2,3
Wvl~d
Z
2,3
I~ d
Z
2,3
W~I
None
3
None
I(n)~d(nt 1), C ~d(O), 1(7) ~C
C
2,3
l(n)~d(n-1), C~d(7), I(O)~C
C
2,3
I - W ~ d [I t W t 1 ~ d]
C,DC,Z 2,3
1(0-3) H 1(4-7) ~ d
None
2,3
W$I~d
Z
2,3
13
10 9
7 6
0
I(FILE#)
OPCODE
b(BIT#)
b = 3-bit bit address
1= 7-bit file register address
W&I~d
I
BIT-ORIENTED FILE REGISTER OPERATIONS
I
I
I
I
f, b O~I(b)
None
2,3
f, b 1 ~I(b)
None
2,3
f, b Test bit (b) in Iile (I): Skip il clear None
I, b Test bit (b) in Iile (f): Skip if set
None
13
8
7
0
LITERAL AND CONTROL OPERATIONS
k (LITERAL)
OPCODE
k = B-bit immediate value.
11 111X kkkk _kkkk 3Ekk Add Hteral to W
ADDLW k ktW~W
C,DC,Z
11 1001 kkkk kkkk 39kk AND Literal and W
ANDLW k k&W~W
Z
10 Okkk kkkk kkkk 2kkk Call subroutine
CALL
k PC t 1 ~ TOS, k ~ PC <10:0>,
None
PCLATH <4:3> ~ PC <12:11>;
00 0000 0110 0100 0064 Clear Watchdog timer
CLRWDT · O~WDT(and prescaler,il assigned) TO,PD
10 lkkk kkkk kkkk 2kkk Go To address
GOTO
k k~ PC <10:0>, PCLATH <4:3>
None
~ PC <12:11>;
11 1000 kkkk kkkk 38kk Inc!. OR Literal and W IORLW
k kvW~W
Z
11 OOXX kkkk kkkk 30kk Move Literal to W
MOVLW k k~W
None
00 0000 0000 1001 0009 Return from interrupt
RETFIE
TOS ~ PC, '1' ~ GIE
None
11 01XX kkkk kkkk 34kk Return, place literal in W RETLW
k k~W, TOS~PC
None
00 0000 0000 1000 0008 Return Irom subroutine RETURN - TOS~ PC
None
00 0000 0110 0011 0063 Go into standby mode
SLEEP
o~ WDT, stop oscillator
TO,PD
11 1l0X kkkk kkkk 3Ckk SubtractW from literal SUBLW k k-W~W
C,DC,Z
11 1010 kkkk kkkk 3Akk Excl. OR Literal and W XORLW k k$W~W
Z
01
01
01
01
OObb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1bff
1bff
1bff
1bff
Bit Clear I
Bit Setf
Bit Test I,Skip il Clear
Bit Test f, Skip il Set
BCF
BSF
BTFSC
BTFSS
I
I
I
-
00 0000 0110 0010 0062 Load OPTION register
00 0000 0110 Offf 006f Tristate port I
OPTION
TRIS
-
I
W ~ OPTION register
W~ I/O control register f
x=0 or 1.
...
None
None
1
1
The assembler Will generate code With x = O. It IS the recommended lorm 01 use lor compatibility With all software tools.
Notes: See previous page
DS30150B - page 12
~[J@~ OITml 0[Jil(ID[JW
1-116
© 1992 Microchip Technology Incorporated
4.2 INSTRUCTION DESCRIPTION
ADDLW
Add Literal to W
Syntax:
ADDLW
Encoding:
I
11
k
kkkk
kkkk
Cycles:
(W+k)~W
Status bits:
C, DC,Z
Description:
The contents 01 the W register are added
to the eight bit literal "k" and the result is
placed in the W register.
ADDWF
ADDWtof
Syntax:
ADDWF
Encoding:
I
00
Syntax:
BCF
Encoding:
I
I,b
01
Ibfff
OObb
ffff
Cycles:
1
Operation:
o ~I(b)
Status bits:
None
Description:
Bit "b" in register ''1'' is reset to O.
BSF
Bit Set f
Syntax:
BSF
Encoding:
I
I,b
Olbb
01
I
bfff
ffff
Words:
I,d
Cycles:
I 0111 I dfff
ffff
Words:
Cycles:
Operation:
Bit Clear f
Words:
I l11X
Words:
Operation:
BCF
(W+f)~d
Status bits:
C,DC,Z
Description:
Add the contents 01 the W register to
register "I". If "d" is 0 the result is stored
in the W register. II "d" i.s 1 the result is
stored back in register "f'.
1
Operation:
1 ~I(b)
Status bits:
None
Description:
Bit "b" in register ''1'' is set to 1.
BTFSC
Bit Test. skip if Clear
Syntax:
BTFSC
Encoding:
I
Words:
1
I,b
I 10bb Ibfff
01
ffff
Cycles:
1(2)
ANDLW
AND Literal and W
Operation:
skip il I(b) = 0
Syntax:
ANDLW
Status bits:
None
Encoding:
I
Description:
II bit "b" in register "I" is "0" then the next
instruction is skipped.
11
k
I 1001 I kkkk
kkkk
Words:
Cycles:
II bit "b" is "0", the next instruction,
letched during the current instruction execution, is discarded and a NOP is
executed instead making this a 2 cycle
instruction.
1
Operation:
(W .AND. k) ~ W
Status bits:
Z
Description:
The contents 01 W register are AND'ed
with the eight bit literal "k". The result is
placed in the W register.
ANDWF
AND W with f
Syntax:
Encoding:
ANDWF
I
00
I,d
I 0101 I dfff
ffff
Words:
Cycles:
~
Operation:
(W .AND. I)
d
Status bits:
Z
Description:
AND the W register with register "I". II "d"
is 0 the result is stored in the W register.
II "d" is 1 the result is stored back in
register "I",
© 1992 Microchip Technology Incorporated
BTFSS
Bit Test. skip if Set
Syntax:
BTFSS
Encoding:
I
Words:
1
01
I
I,b
11bb
I bfff
ffff
Cycles:
1 (2)
Operation:
skip il I(b) = 1
Status bits:
None
Description:
II bit "b" in register "I" is "1" then the next
instruction is skipped.
II bit "'b" is "1 ", the next instruction, letched
during the current instruction execution,
is discarded and a NOP is executed instead making this a 2 cycle instruction.
[F) [l'@ ~ 0[ffij) 0[JjJ lID [l'W
1-117
05301508 - page 13
CALL
Syntax:
Encoding:
Subroutine Call
CALL
k
I 10
Okkk
kkkk
I kkkk
Words:
COMF
Complement f
Syntax:
Encoding:
rl-00-rl-l....:0-0-l-.-df-f-f~lr-f-ff-f---'
COMF
f,d
Words:
Cycles:
2
Cycles:
Operation:
PC + 1 ~ TOS, k ~ PC<10:0>,
PCLATH<4:3> ~ PC<12:11>;
Operation:
f
Status bits:
Z
Status bits:
None
Description:
Description:
Subroutine call. First, return address (PC
+ 1) is pushed into the stack. The eleven
bit value is loaded into PC bits <10:0>.
The upper bits of the PC are loaded from
PCLATH (f03). CALL is a two cycle instruction.
The contents of register "f" are complemented. If"d" is 0 the result is stored in W.
If "d" is 1 the result is stored back in
register "f".
DECF
Decrement f
Syntax:
DECF
f,d
Clearf
Encoding:
I
0011
Words:
1
Cycles:
1
CLRF
Syntax:
Encoding:
CLRF
I
00
I 0001
Hff
ffff
~
d
00
dfff
ffff
~d
Words:
Operation:
(f-1)
Cycles:
Status bits:
C,DC,Z
Description:
Decrement register "f". If "d" is 0 the result
is stored in the W register. If "d" is 1 the
result is stored back in register "I".
DECFSZ
Decrement f, skip if 0
Operation:
OOh ~ f
Status bits:
Z
Description:
The contents of register "f" are set to O.
CLRW
Clear W Register
Syntax:
CLRW
Encoding:
I
00
I 0001
OXXX
xxxx
Syntax:
DECFSZ
Encoding:
I
Words:
1
f,d
I 1011 I dfff
00
Words:
Cycles:
1 (2)
Cycles:
Operation:
(f -1)
~
ffff
d; skip if result = 0
Operation:
OOh ~W
Status bits:
None
Status bits:
Z
Description:
Description:
W registered is cleared. Zero bit (Z) is set.
CLRWDT
Clear Watchdog Timer
The contents of register ''/'' are decremented. If "d" is 0 the result is placed in
the W register. If "d" is 1 the result is
placed back in register "I".
Syntax:
,o-C_LR_W_D..-T_ _-,-_ _.-_---,
Encoding:
I
00
I 0000
0110
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
0100
Words:
Cycles:
GOTO
~WDT,
~
Operation:
OOh
Status bits:
1 ~TO, 1
Description:
CLRWDT instruction resets the watchdog timer.lt also resets the prescaler of
the WDT. Status bits TO and PO are set.
~
0
Unconditional Branch
WDT prescaler,
Syntax:
PD
,-G_O_T_O-,-_k_-,-_ _. - _ - ,
Encoding:
I 10 I lkkk
Words:
1
Cycles:
2
Operation:
k~
kkkk
kkkk
PC<10:0>, PCLATH<4:3>
~ PC':12:11>
Status bits:
D8301508 - page 14
~[[,®~DmmD[ffi®[['W
1-118
None
© 1992 Microchip Technology Incorporated
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded into
PC bits <1 0:0>. The upper bits 01 PC are
loaded Irom PCLATH <4:3>. GOTO is a
two cycle instruction.
INCF
Increment f
Syntax:
INCF
Encoding:
I
00
I,d
1
dfff
1010
I
ffff
I
Status bits:
Z
Description:
Inclusive OR the W register with register
"I". II "d" is 0 the result is stored in the W
register. II "d" is 1 the result is stored back
in register "I".
MOVLW
Move Literal to W
Syntax:
MOVLW
Encoding:
Words:
11
k
I ooxx I
kkkk
I
kkkk
I
Words:
Cycles:
Cycles:
Operation:
(I+l)-->d
Status bits:
C,DC,Z
Description:
The contents 01 register "I" are incremented. II "d" is 0 the result is placed in
the W register. II "d" is 1 the result is
placed back in register "I".
INCFSZ
Increment f, skip if 0
Syntax:
MOVF
Syntax:
INCFSZ
Encoding:
I
Encoding:
I
00
I,d
11111
I
dfff
I
ffff
I
Operation:
k --> W
Status bits:
None
Description:
The eight bit literal "k" is loaded into W
register.
MOVF
Movef
00
I,d
I
1000
I
dfff
ffff
I
Words:
Cycles:
Words:
Cycles:
1 (2)
Operation:
Operation:
(I + 1) --> d, skip il result = 0
Status bits:
Z
Status bits:
None
Description:
Description:
The contents 01 register "I" are incremented. II "d" is 0 the result is placed in
the W register. If "d" is 1 the result is
placed back in register "I".
The contents 01 register I is moved to
destination d. II d=O, destination is W
register. II d = 1, the destination is lile
register I itself. It is uselul, however, to
test a lile register since status Ilag Z is
affected.
MOVWF
Move Wto f
Syntax:
MOVWF
Encoding:
I
II the result is 0, the next instruction,
which is already letched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
IORLW
Inclusive OR Literal with W
Syntax:
IORLW
11
Encoding:
1000
1
Operation:
(W .OR. k) --> W
kkkk
I
kkkk
I
Move data lrom W register to register "I".
NOP
No Operation
NOP
Encoding:
I
IORWF
Inclusive OR W with f
Words:
Syntax:
IORWF
00
I
0000
I,d
Cycles:
0100
Operation:
No operation
Status bits:
None
Description:
No operation
I
dfff
I ffff
Words:
Operation:
(W .OR. I) --> d
I
None
Syntax:
1
ffff
Description:
Z
Cycles:
lfff
W --> I
The contents olthe W register are OR'ed
with the eight bit literal "k". The result is
placed in the W register.
I
I
Status bits:
Description:
00
0000
Operation:
Status bits:
Encoding:
I
Cycles:
I
Words:
Cycles:
00
Words:
k
I
1--> d
I oxxo I
0000
I
D8301508 - page 15
© 1992 Microchip Technology Incorporated
1-119
OPTION
Load Option Register
RLF
Rotate Left f through Carry
Syntax:
OPTION
Syntax:
RLF
Encoding:
1
Encoding:
1 00
00
1 0000
0110 1 0010
Words:
Cycles:
1
W -7 OPTION;
Status bits:
None
1 dfff 1 ffff
Cycles:
Operation:
The contents of the W register is loaded
in the OPTION register. Refer to Fig.
6.5.1 for OPTION register settings.
This instruction is supported for code
compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address it.
To maintain upward compatibility with
future PIC16CXX products, do not use
this instruction.
RETFIE
11101
Words:
Operation:
Description:
I,d
RETFIE
Encoding:
1 00
C
Description:
The contents 01 register "f" are rotated
one bit to the left through the Carry Flag.
II "d" is 0 the result is placed in the W
register. II "d" is 1 the result is stored back
in register "f".
RRF
Rotate Right f through Carry
Syntax:
RRF
Encoding:
Return from Interrupt
Syntax:
I -7 d, 1<7> -7 C, C -7 d;
Status bits:
00
f,d
1 1100 1 dfff
ffff
1
Words:
1 0000
1 0000
1001
Cycles:
1
Operation:
I -7 d -7 C, C -7 d<7>;
2
Status bits:
C
Operation:
TOS -7 PC, 1 -7 GIE;
Description:
Status bits:
GLlNTD
Description:
Return from Interrupt. Stack is popped
and Top of the Stack (TOS) is loaded in
PC. Interrupts are enabled by setting the
G IE bit. G IE is the global interrupt enable
bit (bit 7, register INTCON). This is a two
cycle instruction.
The contents 01 register "I" are rotated
one bit to the right through the Carry Flag.
If "d" is 0 the result is placed in the W
register. If"d" is 1 the result is placed back
in register "f".
Syntax:
SLEEP
Return Literal to W
Encoding:
1 00
RETLW
k
Words:
11
01XX
Words:
Cycles:
RETLW
Syntax:
Encoding:
I
1 kkkk
SLEEP
I kkkk
0110
0011 1
Cycles:
Operation:
0-7 PD, 1 -7 TO;
OOh -7 WDT, 0 -7 WDT prescaler;
k -7 W; TOS -7 PC;
Status bits:
TO, PD
None
Description:
The power down status bit (PD) is cleared.
Time-out status bit (TO) is set. Watchdog
Timer and its prescaler are cleared.
Words:
Cycles:
2
Operation:
Status bits:
Description:
The W register is loaded with the eight bit
literal "k". The program counter is loaded
from the top of the stack (the return
address). This is a two cycle instruction.
RETURN
1 0000
The processor is put into SLEEP mode
with the oscillator stopped. See section
on SLEEP mode lor more details.
Return from Subroutine
Syntax:
RETURN
Encoding:
I
00
1 0000
1 0000
11000
Words:
Cycles:
2
Operation:
TOS -7 PC;
Description:
Return from subroutine. The stack is
popped and the top 01 the stack (TOS) is
loaded into the program counter. This is
a two cycle instruction.
DS301508 - page 16
SUBLW
Subtract W from Literal
Syntax:
SUBLW
Encoding:
I
11
k
1110X
kkkk
1
kkkk
Words:
Cycles:
Operation:
(k-W) -7W
Status bits:
C,DC,Z
~ u® ~ 0M 0[FO lID uW
1-120
© 1992 Microchip Technology Incorporated
Description:
The W register is subtracted (2's complement method) Irom the eight bit literal "k".
The result is placed in the W register.
Example
;SUBLW Example #1
MOVLW
SUBLW
OxOl
Ox02
TRIS
Load TRIS Register
Syntax:
TRIS
Encoding:
I 00
I 0000
ono
I Offf
I
Words:
;wreg=l
;wreg= 2-wreg = 2-1=1
;Carry=l: result is positive
Cycles:
1
Operation:
W
;SUBLW Example #2
Status bits:
None
MOVLW
SUBLW
Description:
The 1/0 Control Register (or data direction register 01 the I/O port) is loaded with
the contents 01 the W register.
Ox02
OxOl
;wreg=2
;wreg=1-wreg=1-2=FFh
;Carry=O: Result is negative
SUBWF
Subtract W from f
Syntax:
SUBWF
Encoding:
I 00
I dfff
ffff
This instruction is supported lor code
compatibility with the PIC16C5X products.
Since TRIS registers are readable and
writable, the user can directly address
them. To maintain upward compatibility
with luture PIC16CXX products, do not
Words:
Cycles:
1
Operation:
(I-W)
Status bits:
C, DC, Z
Description:
--7
1/0 Control Register I
The TRIS instruction conligures an 1/0
port to either output or input (high-impedance). The valid values lor "I" are 5 & 610r
PIC16C71.
I,d
I 0010
--7
d
use this instruction.
A '1' in the TRIS register conligures the
corresponding port pin as an input. A '0'
in the TRIS register conligures the corresponding port pin as an output.
Subtract (2's complement method) the W
register Irom register "I". II "d" is 0 the
result is stored in the W register. II "d" is
1 the result is stored back in register "I".
Example:
MOVLW OxOF
Example:
;SUBWF Example #1
TRIS
clrf
movlw
subwf
Ox20
1
Ox20
;SUBWF
movlw
movwf
clrw
subwf
Example #2
OxFF
Ox20
;f(20h)=FFh
;wreg=O
;f(20h)=f(20h)-wreg=FFh-0=FFh
Ox20
;Carry=l: Result is positive
6
1/0 Port B (F6) is conligured such that the
4 pins corresponding to the LSBs 01 Port
B are inputs (h-impedance) and the other
4 pins are outputs.
; f (20h) =0
;wreg=l
;f(20h)=f(20h)-wreg=0-1=FFh
;Carry=O:Result is negative
XORLW
Exclusive OR literal with W
Syntax:
XORLW
Encoding:
11
k
11010
I kkkk I kkkk
I
Words:
SWAPF
Syntax:
Encoding:
Swapf
Cycles:
1
SWAPF
Operation:
(W .XOR. k)
Status bits:
Z
Description:
The contents olthe W register are XOR'ed
with the eight bit literal "k". The result is
placed in the W register.
XORWF
Exclusive OR W with f
I 00
I,d
Ilno
dfff I ffff
I
Words:
Cycles:
Operation:
kO:3>
Status bits:
None
Description:
The upper and lower nibbles 01 register "f"
are exchanged. If "d" is 0 the result is
placed in W register. If "d" is 1 the result
is placed in register "I".
--7
d<4:7>, k4:7>
© 1992 Microchip Technology Incorporated
--7
d<0:3>:
Syntax:
XORWF
Encoding:
I 00
Words:
1
W
I,d
I ono
I dfff I ffff
I
Cycles:
1
Operation:
(W .XOR. I)
Status bits:
Z
Description:
Exclusive OR the contents of the W register with register "I". II "d" is 0 the result
is stored in the W register. II "d" is 1 the
result is stored back in register "I".
~ u® ~ 0m 0[1l) tID uW
1-121
--7
--7
d
D830150B - page 17
5.0 SPECIAL FEATURES OF THE CPU
power-up timer (PWRT), which provides a fixed delay of
72 ms (nominal) on power up only, designed to keep the
part in reset while the power supply stabilizes. With
these two timers on chip, most applications need no
external reset circuitry.
What sets apart a microcontroller from other processors
are special circuits to deal with the needs of real time
applications. The PIC16C71 has a host of such features
intended to maximize system reliability, minimize cost
through elimination of external components, provide power
saving operating modes and offer code protection.
The SLEEP mode is designed to offer a very low current
power-down mode. The user can wake up from SLEEP
through external reset, watchdog timer time-out or
through an interrupt. Several oscillator options are also
made available to allow the part to fitthe application. The
RC oscillator option saves system cost while the LP
crystal option saves power. A set of EPROM configuration bits (fuses) are used to select various options
(section 5.6).
The PIC16C71 has a watchdog timer which can be shut
off only through EPROM fuses. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the oscillator
start-up timer (OST), intended to keep the chip in reset
until the crystal oscillator is stable. The other is the
FIGURE 5.0.1 - SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
~_~R""es""e"'...t_ _ _ _ _ _------c
MCLR
VDD
OSTIPWRT
Chip_Reset
10 bit Ripple counter
Or-----.
10 bit Ripple counter
POWER UP
(Enable the PWRT timer
only if it is power_up.)
(POWER_UP +WAKE_UP) (XT + LP)
(Enable the OST if it is power_up or wake_up
from SLEEP and OSC type is XT or LP)
are a few exceptions to this. The PC is always reset to
all O's (OOOOh). Finally, TO and PO bits are set or cleared
differently in different reset situations as indicated in
section 3.8.1. These bits are used in software to
determine the nature of reset. See Table 5.1.1 for a full
description of reset states of all registers.
5.1 RESET
The PIC16C71 differentiates between various kinds of
reset:
a)
Power on reset (POR)
b)
MCLR Reset during normal operation
5.2 Power-on-reset (PORl. Power-up-timer
c)
MCLR reset during SLEEP
d)
WDT time-out reset during normal operation
e)
WDT time-out reset during SLEEP
(PWRTl and Oscillator Start-up timer
(OST)
Power-on-reset (POR): A power-on-reset pulse is generated on-chip when Voo rise is detected (in the range
of 1.2V - 2.0V). To take advantage of the POR, just tie
MCLR pin directly (or through a resistor) to Voo. This will
eliminate external RC components usually needed to
create power-on-reset.
Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to "reset state" on poweron reset (POR), on MCLR or WOT reset during normal
operation and on MCLR reset during SLEEP. They are
not affected by a WOT reset during SLEEP, since this
reset is viewed as resume of normal operation. There
D8301508 - page 18
[l2l u@ ~ 0mm 0[fj) (~l[rw
1-122
© 1992 Microchip Technology Incorporated
TABLE 5.1.1 RESET CONDITIONS FOR REGISTERS
Register
Address
W
Power·on reset
(POR)
WDTtime-out
reset during
normal operation
WDTtime·out
reset during
SLEEP
MCLR reset
during normal
MCLR reset
during SLEEP
Wake-up
through
interrupt
xxxx XXXX
UUtiU UUtiU
uuuu uuuu
uuuu uuuu
UUtiU
uuuu
ilUtiU ilUtiU
uuuu
llUtiU
uuuu
UUtiU ilUUU
uuuu
UUtiU
ilUtiU ilUtiU
INDIR
OOh
RTCC
01h
xxxx xxxx
PC
02h
OOOOh
STATUS
03h
0001 1xxx
0000 1uuu
uuuO Ouuu
FSR
04h
xxxx xxxx
ilUtiU UilUU
ilUtiU
PORTA
05h
xxxx
XXXX
PORTS
OSh
xxxx xxxx
TRISA
85h
---1 1111
---1 1111
ilUtiU
OOOOh
PC + 1
OOOOh
OOOu
UUtiU
OOOOh
PC + 1
OOOu Ouuu
uuu1 Ouuu
UUilU
UUtiU UUtiU
UUtiU
uuuu
UUtiU UUtiU
DUtiU ilUUU
UUDU ilUtiU
UUtiU UUtiU
UUtiU UUtiU
uuuu uuuu
UUtiU ilUUU
ilUtiU ilUtiU
ilUtiU
UilUU
ilUUU ilUtiU
ilUtiU UUtiU
---u
UUtiU
---1 1111
---1 1111
---u
UilUU
TRISS
8Sh
1111 1111
1111 1111
UUtiU ilUtiU
1111 1111
1111 1111
ilUilU UUtiU
OPTION
81h
1111 1111
1111 1111
ilUtiU UUilU
1111 1111
1111 1111
ilUilU UUtiU
ADCONO
08h
0000 0000
0000 0000
UUtiU
UUilU
0000 0000
0000 0000
ilUtiU ilUtiU
ADCON1
88h
----
--00
----
--00
----
--Ull
----
--00
----
----
ADRES
09h
xxxx XXXX
UUtiU
UUUll
ilUUU
uuuu
uuuu
UUtiU
uuuu uuuu
UUtiU ilUUU
PCLATH
OAh
---0 0000
---0 0000
---u
UUtiU
---0 0000
---0 0000
---u
UUtiU
INTCON
OSh
0000 OOOx
0000 OOOu
UUtiU
UUilU
0000 OOOu
0000 0000
UUilU
uuuu*
--00
--Ull
Legend:
- = unimplemented, reads as '0'
u = unchanged
x = unknown
In the event of wake-up through interrupt, one or more of the interrupt flags will be set.
Other bits in INTCON will remain unchanged.
The POR circuit does not produce internal reset when
Voo declines (or goes through a brown-out).
Time-out Sequence: On power up the time-out sequence is as follows: First PWRT time-out is invoked
after POR has expired. Then TOST is activated. The
total time-out will vary based on oscillator configuration
and PWRTE fuse status. For example, in RC mode with
PWRTE setto '0' (PWRT disabled), there will be no timeout at all. Figures 5.2.1 and 5.2.2 depict time-out
sequences.
Power-up Timer (PWRT): The power-up timer provides
a fixed 72ms time-out on power-up only, from POR. The
power-up timer operates on an internal RC oscillator.
The chip is kept in reset as long as PWRT is active. The
PWRT delay allows the Voo to rise to an acceptable
level. A configuration fuse, PWRTE can enable (if = 1)
or disable (if = 0 or programmed) the power-up timer
(section 5.6).
Since the time-outs occur from POR pulse, if MCLR is
kept low ~nough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC operating in conjunction.
The power-up time delay will vary from chip to chip and
due to Voo and temperature. See DC parameters for
details.
Oscillator Start-up Timer (OST): The oscillator start-up
timer (OST) provides 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. This guarantees that the crystal oscillator or resonator has started
and stabilized.
TABLE 5.2.1 - TIME-OUT IN VARIOUS
SITUATIONS
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
© 1992 Microchip Technology Incorporated
Oscillator
Configuration
Power up
PWRTE= 1 PWRTE = 0
Wake up from
SLEEP
XT, HS, LP
72 ms +
1024 tosc
72 ms
1024 tosc
1024 tosc
-
-
RC
~u@~ 0m 0[nl(IDuW
1-123
D830150B - page 19
FIGURE 5.2.1 TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VOO): Case 1
Voo
MCLR
-~/
-------+----~/
---'n'--____________________
INTERNAL POR _ _ _ _ _
tPWRT-----..
..
I - I_ _ _
,
_ _ _ _ __
PWRT TIME-OUT ----------------------!~tOST-j
i--------OST TIME-OUT
INTERNAL RESET
FIGURE 5.2.2 TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO Voo): Case 2
VDD
MCLR
INTERNAL POR
===~/-----------~~
________~h~l____________________________~--:111
IPWRT - - - - - . I - ! - - - - - - - - - - i ' - - - - - - - - -
PWRT TIME-OUT -------------------1~ IOST-i
i-------i----OST TIME-OUT
INTERNAL RESET
1--
----------------------~
FIGURE 5.2.3 TIME-OUT SEQUENCE ON POWER·UP (MCLR TIED TO Voo)
Voo
MCLR
INTERNALPOR
-~y
--_-~~~--------------------
--------'n~,----------------------tPWRT-----I>I-I_ _ _
, ------------
PWRT TIME-OUT
,+-tOST"*,
1----'---------------
OST TIME-OUT - - - - - - - - - - - - - - - - - - '
INTERNAL RESET - - - - - - - - - - - - - - - - - - - '
DS30150B - page 20
[J2l [J@ ~ 0mru 0Oll lID [JW
1-124
© 1992 Microchip Technology Incorporated
5.3 WATCHDOG TIMER (WDT)
FIGURE 5.2.4 - EXTERNAL POWER
ON RESET CIRCUIT
The watchdog timer is realized as a free running on·chip
RC oscillator which does not require any external components, That means that the WOT will run, even if the
clock on the OSC1/0SC2 pins of the device has been
stopped, for example, by execution of a SLEEP instruction. A WOT timeout generates a device RESET condition. The WOT can be permanently disabled by programming the configuration fuse WOTE as a '0' (section
5.6).
Voo
lL-MCce
~
C
PIC16C71
Notes:
1, External power on reset circuit is required only if Voo
power-up slope is too slow,
The diode D
helps discharge the capacitor quickly when
VDD powers down,
5.3.1 WOT Period
The WOT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
OC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1 :128 can be
assigned to the WOT under software control by writing
to the OPTION register. Thus, time-out periods up to 2.5
seconds can be realized.
The "CLRWOT" and "SLEEP" instructions clear the
WOT and the prescaler, if assigned to the WOT, and
prevent it from timing out and generating a device
RESET condition.
The status bit "TO" in file register f3 will be cleared upon
a watchdog timer timeout.
2, R < 40 KO is recommended to make sure that
voltage drop across R does not exceed 0,2 V (max
leakage current spec on MCLR pin is ~ A larger
voltage drop will degrade VIH level on MCLR pin,
3, R1= 1000 to 1KO will limit any current
flowin~
MCLR from external capacitor C in the event of MCLR
pin breakdown due to ESD or EOS,
FIGURE 5.2.5 - BROWN OUT PROTECTION
CIRCUIT 1
-_----.-----1 Voo
Voo
33K
5.3.2 WOT Programming Considerations
In a noisy application environment the OPTION register
can get corrupted. The OPTION register should be
updated at regular intervals.
It should also be taken in account that under worst case
conditions (VDD =Min., Temperature =Max., max, WOT
prescaler) it may take several seconds before a WOT
timeout occurs,
MCLR
40K
PIC16C71
Notes:
1, This circuit will activate reset when VDD goes
below (VZ + 0,7 V) where VZ = Zener voltage,
5.4 OSCILLATOR CONFIGURATIONS
FIGURE 5.2.6 - BROWN OUT PROTECTION
CIRCUIT 2
Voo
5.4.1 Oscillator Types
The PIC16C71 can be operated in 4 different oscillator
options, The user can program two configuration bits
(FOSC1 and FOSCO) to select one of these four modes.
-..-----.-------1 Voo
R1
5.4.2 Crystal Oscillator
MCLR
In XT, HS, or LP modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 5.4.1),
R2
PIC16C71
Notes:
1. This brown circuit is less expensive, albeit less
accurate, Transistor Q1 turns off when VDD is
below a certain level such that:
VDD' _R_1_ = 0,7 V,
R1 + R2
© 1992 Microchip Technology Incorporated
DS30150B - page 21
1-125
TABLE 5.4.1 - CAPACITOR SELECTION
FOR CERAMIC RESONATORS
Oscillator
Type
Resonator
Frequency
XT
455 KHz
2.0 MHz
4.0 MHz
8.0 MHz
HS
its own characteristics, the user should consult the
crystal manufacturer for appropriate values of external
components.
Capacitor Range
C1 =C2
FIGURE 5.4.2 - EXTERNAL CLOCK INPUT
OPERATION (HS, XT, or LP OSC
CONFIGURATION)
150 - 330 pF
20 - 330 pF
20 - 330 pF
20 - 200 pF
Clock from ext.
system
Higher capacitance increases the stability of oscillator
but also increases the start-up time. These values are
for design guidance only. Since each resonator has its
own characteristics, the user should consultthe resonator
manufacturer for appropriate values of external components.
For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operation
temperature. In addition to this, the oscillator frequency
will vary from unit to unit due to normal process pararnetervariation. Furthermore, the difference in lead frame
capacitance between package types will also affect the
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation to due
tolerance of external Rand C components used. Figure
5.4.3 shows how the RIC combination is connected to
the PIC16C5X. For Rext values below 2.2 kOhm, the
oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 MOhm), the
oscillator becomes sensitive to noise, humidity and
leakage. Thus, we recommend to keep Rext between 5
kOhm and 100 kOhm.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead
frame capacitance.
See table in section 9.0 for RC frequency variation from
part to part due to normal process variation. The
variation is larger for larger R (since leakage current
variation will affect RC frequency more for large R) and
for smaller C (since variation of input capacitance will
affect RC frequency more).
See characteristics in section 9.0 for variation of oscillator frequency due to VOD for given RextlCext values as
well as frequency variation dueto operating temperature
for given R, C, and Voo values.
0To internal
logic
PIC16C71
Rs is recommended for"HS" devices (100n < Rs< 1K).
Rs may also be used in XT mode for AT strip-cut
crystalg. See Tables 5.4.1 and 5.4.2 for recommended
values of C1, C2 and Rs.
TABLE 5.4.2 - CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Freq
C1
C2
LP
32 KHz
100 KHz
200 KHz
100 KHz
200 KHz
455 KHz
1 MHz
2MHz
4 MHz
4MHz
8MHz
20 MHz
15pF
15pF
0- 15 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 pF
15 pF
15pF
15 pF
15 pF
15 pF
15 pF
0- 15 pF
200 - 300 pF
100 - 200 pF
15 - 100 pF
15 - 30 pF
15 pF
15 pF
15 pF
15 pF
15 pF
XT
HS
Higher capacitance increases the stability of oscillator
but also increases the start-up time. These values are
for design guidance only. Rs may be required in HS
mode as well as XT mode to avoid overdriving crystals
with low drive level specification. Since each crystal has
OS30150B - page 22
OSC2
5.4.3 RC Oscillator
OSC1
Osc
Type
PIC16C71
Open
FIGURE 5.4.1 - CRYSTAL OPERATION
(OR CERAMIC RESONATOR) (HS, XT OR
LP OSC CONFIGURATION)
C2
OSCl
The oscillator frequency, divided by 4, is available on the
OSC2/CLKOUT pin, and can be used for test purposes
or to synchronize other logic (see Figure 3.2.1 for
timing).
[FV u@ U0[ffilJ 00ll1ID uW
1-126
©
1992 Microchip Technology Incorporated
5.5.1 Wake-up from SLEEP
FIGURE 5.4.3 - RC OSCILLATOR (RC TYPE
ONLY)
The device can wake up from SLEEP through one of the
following events:
voo
a. External reset input on MCLR pin
Rext
b. Watchdog timer timeout reset (if WOT was enabled)
>----~ OSC1
cext
Vss
I
-=-
c. Interrupt from INT pin, RB port change or AID converter.
PIC16C71
-
The first event will cause a device reset. The two latter
events are considered a continuation of program execution. The TO and PO bits in the STATUS register can be
used to determine the cause of device reset. PO bit,
which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WOTtime-out occurred (and
caused wake-up).
OSC2/CLKOUT
Fosc/4
L -_ _ _ _---'
5.5 POWER DOWN MODE (SLEEP)
The power down mode is entered by executing a SLEEP
instruction.
For the device to wake up through an interrupt, the
corresponding interrupt mask bit must be enabled. On
wake-up, the device will continue to execute code in-line
if global interrupt was disabled (GIE = 0) or branch to
interrupt service routine if GIE was enabled.
If enabled, the watchdog timer will be cleared but keeps
running, the bit "PO" in the status register (f03) is
cleared, the "TO" bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP command was executed (driving
high, low, or hi-impedance).
5.6 CONFIGURATION FUSES
For lowest curent consumption in this mode, all I/O pins
should be either at Voo, or Vss, with no external circuitry
drawing current from the I/O pin. 110 pins that are in the
High-Z mode should be pulled high or low externally to
avoid switching currents caused by floating inputs. The
RTCC input should also be at Voo or Vss for lowest
current consumption. The contribution from on chip pullups on PortB should be considered.
The PIC16C71 has five configuration fuses which are
EPROM bits. These fuses can be programmed (reads
'0') or left unprogrammed (reads '1 ') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the user
program memory space. In fact, it belongs to the special
test/configuration memory space (2000h - 3FFFh).
However, through a special mode, this location can be
accessed during programming.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WOT
time out does not drive MCLR pin low.
See description of fuses in figure 5.6.1.
FIGURE 5.6.1: CONFIGURATION WORD
13
I
5
4
bitO
I CP I PWRTE I WOTE I FOSC11
FOSCO I Addr: 2007h
OSC selection fuses:
L -_ _" - - _
FOSC1, FOSCO:
00 : LP oscillator
01 : XT oscillator
10: HS oscillator
11 : RC oscillator
' - - - - - - - - - WOT enable fuses:
WOTE = 1: WOT enabled
WOTE = 0: WOT disabled
Power-up timer enable fuse:
PWRTE = 1 power-up time enabled
PWRTE = 0 power-up timer disabled
Code protection fuse:
CP = 1 code protection off
CP = 0 code protection on
Unimplemented. Read as '1 'so
© 1992 Microchip Technology Incorporated
~[J@~DmD[1l]CID[JW
1·127
D8301506 - page 23
5.7 ID LOCATIONS
6.1 PORTA
The PIC16C71 has four ID locations (2000h - 2003h)
mapped in the test program memory for storing code
revision number, manufacturing information or other
useful information. As with the configuration word, these
locations are readable and writable through a programmer. They are not accessible during normal code
execution.
PortA is a 5 bit wide port with pins RAO - RA4. Port pins
RA<3:0> are bidirectional whereas RA4 has a opencollector output. PortA is file register 05h. Its corresponding direction control register TRISA is mapped in
page 1 of register file at address 85h. TRISA is a fivebit wide register with bits <4:0>.
Pins RA<3:0> are multiplexed with analog input channels AIN3 - AI NO. Pin RA3 is further multiplexed with
external reference voltage VREF for the ADC. Two bits
in control register ADCON1 (file register 88h) are used
to configure these pins as digital (i.e. port) or analog
pins. When configured as analog inputs, these pins will
read as 'O's and the TRISA register bits will have no
effect. Upon power-on reset, RA<3:0> are configured
as analog inputs.
If the chip is code protected, it is recommended that the
user uses only the lower seven bits of the ID locations
and program the higher seven bits as '1 '. This way the
ID locations will be readable even after code protection.
5.8 CODE PROTECTION
The code in the program memory can be protected by
blowing the code protect fuse (CP).
When code protected, the contents of the program
memory cannot be read out in a way that the program
code can be reconstructed. In addition, all memory
locations starting at 0040h and above are protected
against programming.
FIGURE 6.1.1 - BLOCK DIAGRAM OF
RAO - RA3 PINS
It is still possible to program locations OOOOh - 003Fh, the
ID locations and the configuration fuses.
Data
bus
5.8.1 Verifying a Code-protected PIC
When code protected verifying any program memory
location will read a scrambled output which looks like
"OOOOOOOxxxxxxx" (binary) where X is 1 or O. To verify
a device after code protection, follow this procedure:
Analog input
to NO converter
D
voo
"WR
PORT"
a. First, program and verify a good device without code
protecting it.
Q
CK
"WR
TRIS"
b. Next, blow its code protection fuse and then load its
contents in a file.
--f-t>CK
c. Verify any code-protected PIC against this file.
6.0 OVERVIEW OF PERIPHERALS
The PIC16C71 has 13 110 pins organized as two 1/0
ports, PortA (5 bit) and PortB (8-bit). It has an 8-bittimerl
counter (RTCC) with a programmable 8-bit prescaler
and an analog to digital converter module. The AID
converter has up to four analog inputs, internal or
external reference, 8 bit resolution and a typical 20fJ,s
conversion time.
DS30150B - page 24
"RD PORT"
~[J®~ 0m 0[jl)~[JW
1-128
© 1992 Microchip Technology Incorporated
TABLE 6.1.1 - PORTA FUNCTIONS
Port Pin
Bit
Pin Function
Alternate Function
RAO/AINO
bitO
Input/output port. TTL input levels
RA1/AIN1
bit1
Input/output port. TTL input levels
Analog input channel 1
RA2/AIN2
bit2
Input/output port. TTL input levels
Analog input channel 2
RA3/AIN3/VREF
bit3
Input/output port. TTL input levels
Analog input channel 3 or external
reference voltage input (VREF)
RA4/RT
bit4
Input/output port. Output is open
collector type. Input is Schmitt trigger type.
External clock input for RTCC timer/counter
Analog input channel 0
TABLE 6.1.2 - SUMMARY OF PORTA REGISTERS
Register Name
Function
Address
PORTA
PortA pins when read
PortA latch when written
05h
Power-on Reset Value
---x
xxxx
TRISA
PortA data direction register
85h, PAGE1
---1
1111
ADCON1
AID converter control register
88h, PAGE1
----
--00
Notes: 1: x = unknown, - = unimplemented, reads as a '0'.
2: For reset values of registers in other reset situations refer to table 5.1.1.
FIGURE 6.1.2 - BLOCK DIAGRAM OF RA4 PIN
Each of the PortB pins has a weak internal pull-up (-250
The weak pull-up is automatically turned off
if the port pin is configured as an output. A single control
bit RBPU (bit 7, OPTION register) can tum off (RBPU =
1) all the pull-ups. The pull-ups are disabled on power
on reset.
~A typical).
Data
bus
"WR
PORT""
D
Q
Port B has an interrupt on change feature on four of its
pins, RB<7:4>. When configured as input, the inputs on
these pins are sampled and latched every Q1. The new
input is compared with the old latched value in every
instruction cycle. An active high output is generated on
mismatch between the pin and the latch. The "mismatch" outputs of RB4, RB5, RB6 and RB7 are OR'ed
together to generate the RBIF interrupt (latched in bitO,
INTCON). Any pin configured as output is excluded from
the comparison. This interrupt can wake the chip up
from SLEEP. The user, in interrupt service routine can
clear the interrupt in one of two ways:
CK
"WR
TRIS"
"RD
TRISA"
D
a) Disable the interrupt by clearing RBIE (bit3,
INTCON) bit.
b) Read Port B. This will end mismatch condition.
Next, clear RBIF bit.
"RD PORT"
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy
interface to a key pad and make it possible for wake-up
on key-depression.
RTCC clock input
6.2 PORTB
PortB is an 8-bit wide bidirectional port (file register
address 06h). The corresponding data direction register
is TRISB (address 86h). A '1' in TRISB sets the corresponding port pin as an input. Reading PortB register
reads the status of the pins whereas writing to it will write
to the port latch.
© 1992 Microchip Technology Incorporated
~[J®~DMOUU@[JW
1-129
D830150B - page 25
FIGURE 6.2.1 - BLOCK DIAGRAM OF PORT PINS RB<7:4>
weak
pull-up
RBPU
Q
D
Data bus
1/0 pin
CKt
"WRPort"
Q
D
TTL
Input
buffer
CKt
"WRTRIS"
"RDTRIS"
Dr - - - "
f---+----i Q
CKt
"RD Port"
Set
RBIF
Dr--r--'
CKt
"RD Port"
Note: 1. DDR
=1
enables weak pull-up if RBPU
= 0 in OPTION reqister.
FIGURE 6.2.2 - BLOCK DIAGRAM OF PORT PINS RB<3:0>
weak
pull-up
RBPU
Data bus
"WR Port"
D
cn
D
"WRTRIS"
Q
Q
CKt
"RDTRIS"
D f----'
f-----j Q
CKt
"RD Port"
Note: 1. DDR
= 1 enables weak pull-up if RBPU =0 in OPTION register.
Finally, port pin RBO is multiplexed with external interrupt input INT.
DS30150B - page 26
~[J@~ 0m:nJ 0[fjJ@j[JW
1-130
© 1992 Microchip Technology Incorporated
TABLE 6.2.1 - PORTB FUNCTIONS
Port Pin
Bit
Pin Function
Alternate Function
RBO/INT
bitO
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
External interrupt input
RB1
bit1
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
-
RB2
bit2
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
-
RB3
bit3
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
-
RB4
bit4
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
Interrupt on port change
RBS
bitS
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
Interrupt on port change
RB6
bit6
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
Interrupt on port change
RB?
bit?
Input/output port pin. TTL input levels and internal
software programmable weak pull-up
Interrupt on port change
TABLE 6.2.2 - SUMMARY OF PORTB REGISTERS
Address
Power-on Reset Value
PortB pins when read
PortB latch when written
06h
xxxx xxxx
TRISB
PortB data direction register
86h
1111
1111
OPTION
Weak pull-up on/off control (RBPU bit)
88h
1111
1111
Register Name
PORTB
Function
6.3 1/0 PROGRAMMING
CONSIDERATIONS
b) A pin actively outputting a "0" or "1" should not be
driven from external devices at the same time in
order to change the level on this pin ("wired-or",
"wired-and"). The resulting high output currents may
damage the chip.
For "wired-or" outputs (assuming negative logic), it is
recommended to use external pull-up resistors on
the corresponding pins. The pin should be left in
high-impedance mode, unless a "0" has to be output.
Thus, external devices can drive this pin "0" as well.
"Wired-and" outputs can be realized in the same
way, but with external pull-down resistors and only
actively driving the "1" level from the PIC. The resistor values are user selectable, but should not force
output currents above the specified limits (see DC
Characteristics).
6.3.1 BIDIRECTIONAL I/O PORTS
a) Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the
CPU, execute the bit operation, and re-output the
result. Caution must be used when these instructions are applied to a port where one or more pins are
used as inpUt/outputs. For example, a BSF operation
on bit S of f6 (Port B) will cause all eight bits of f6 to
be read into the CPU. Then the BSF operation takes
place on bit Sand f6 is re-output to the output latches.
If another bit of f6 is used as a bidirectional I/O pin
(say bit 0) and it is defined as an input atthis time, the
input signal present on the pin itself would be read
into the CPU and re-written to the data latch of this
particular pin, overwriting the previousocontent. As
long as the pin stays in the input mode, no problem
occurs. However, if bit 0 is switched into output mode
later on, the content of the data latch may now be
unknown.
© 1992 Microchip Technology Incorporated
~[f®~Dmo[Jj)~l[JW
1-131
D830150B - page 27
:~I~IOOI~'~I~IOOI~'~I~IOOI~'~I~IOOI~'
PC~
Instruction
fetched'
RB (7:0)
PC
MOVWF f6
Write to IS
(Port B)
X
PC+l
X
MOVF f6. W
'Read f6 (Port B) ,
X
:PC+2
,NOP
PC+3
NOP
~:========~-=--=--=--=-----------l";'~:;=~======~=========
:, :, fsampled
Port pin
,
here,
-..,
Execute
MOVWF f6
~
' TpD Execute
MOVF IS. W
6.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS
Execute
NOP
'
Note:
This example shows
write to port B followed
,by a read from port B,
Note that the data setup
time = (0,25 TCY - TPD)
where TCY = instruction
cycle.
Therefore. at
higher clock frequencies.
write followed by a read
may be problematic.
Timer mode is selected by setting RTS billo '0' (OPTION
register). In timer mode. the RTCC will increment every
instruction cycle (without prescaler). If RTCC (fOl) is
written. increment is inhibited forthe following two cycles
(see figures 6.4.2 and 6.4.3). The user can work around
this by writing an adjusted value to the RTCC.
Counter mode is selected by setting RTS bit to '1'
(OPTION register). In this mode RTCC will increment
either on every rising or falling edge of pin RA4/RTCC.
This is determined by control bit RTE (OPTION register).
RTE = 0 selects rising edge. Restrictions on external
clock input is discussed in detail in section 6.4.1.
The prescaler is shared between the RTCC and the
watchdog timer. The prescaler assignment is controlled
in software by control bit. PSA (OPTION register). PSA
= 0 will assign the prescalerto RTCC. The prescaler is
not readable or writable. When the prescaler is assigned
to the RTCC. prescale value of 1:2. 1:4 ..... 1:256 are
selectable. Section 6.4.2 details the operation of the
prescaler.
The actual write to an I/O port happens at the end of an
instruction cycle. whereaS for reading. the data must be
valid at the beginning of the instruction cycle (see figure
6.3,1). Therefore. care must be exercised if a write
followed by a read operation is carried out on the same
I/O port. The sequence of instructions should be such to
allow the pin voltage to stabilize (load dependent) before
the next instruction which causes that file to be read into
the CPU is executed. Otherwise. the previous state of
that pin may be read into the CPU rather than the new
state. When in doubt. it is better to separate these
instructions with a NOP or 2 I-1s)
00
2tosc
8tosc
10
32 tosc
11
tRe (2 I-1s-6 I-1s, 4 I-1s nominal)
The conversion time for each bit is tad. The total
conversion time is 1Otad. Selection must be made such
that tad is at least 2 I-1s.
At low frequencies, the RC oscillator can be selected to
maintain shorter conversion time. The RC oscillator
frequency varies considerably with voltage, temperature and process parameters (2 I-1s to 6 I-1s period,
nominally 4 I-1s).
The other reason to limit the maximum source impedance is to be able to capture the analog input voltage on
to the holding capacitor. The time constant to charge
Chold is (see figure 6.6.3.1):
Chold (Ric + Rss + Rs)
where Rs = source
impedance
51.2 pF (2Kn +Rs)
Ric + Rss = 2Kn
51.2 pF x 12Kn
(assuming Rs = 10Kn)
6.6.2 AID Operation during SLEEP
To reduce operating current all biasing circuits in the
AID block that consume DC current are shut off when
ADON bit is a '0'. If a conversion is in progress using RC
oscillator, it will be completed. The ADI F interrupt flag bit
will be set and the chip will wake up if the ADIE interrupt
enable bit is a '1'. Since, during SLEEP, the switching
noise is eliminated, the conversion accuracy will be the
maximum possible. This provides a means for getting
accurate conversions while operating the processor at
high clock rates.
0.61441-1s = T
from the capacitive charging equation:
Vhold = VA (1-e·!/T)
for 1/8 LSB error at VDD = 5V
T
2.5 mV
e'u = 5000 mV
or t = 7.6T = 4.671-1s (required sampling time)
If SLEEP is invoked during a conversion that uses OSC1
clock, the conversion will be aborted. The AID converter
will be shut off. The user must re-initialize the conversion, starting with resampling.
© 1992 Microchip Technology Incorporated
VDD
RA3
VDD
A simplified circuit for an analog input is shown in Figure
6.6.3.1. First. the user must configure the TRISA register such that the analog pins are configured as inputs.
Second, since the analog pins are connected to digital
output, they have reverse biased diodes to VDD and Vss.
The analog input, therefore must be between Vss and
VDD. If input voltage deviates from this range by more
than 0.6V in either direction, one olthe diodes is forward
biased and a latch-up may occur. To minimize the
possibility of damage to the analog inputs due to latchup a minimum source impedance of 500n is recommended. A maximum source impedance of 10Kn is
recommended for the analog sources. At this impedance, the maximum possible error caused by the leakage current is ±5 mV or ±0.25 LSB at VDD = VREF = 5V
(1 OKn x 0.5 !!A).
ADCS1, ADCSO
01
analog input
ref input
digital input
digital input
YB.E.E
6.6.3 Analog Input Connection
Considerations
6.6.1 AID Clocking Scheme
The AID converter operates on its own clock, tad,
derived from either the OSC1 clock input or from its own
on-chip RC oscillator as follows:
Control bit
~
~ U'@ ~ 0M 0OIl CID U'W
1-137
05301508 - page 33
FIGURE 6.6.3.1 • ANALOG INPUT MODEL
VDD
VT
Sampling
switch
= O.6V
r- - - - - - -- - - - ,
Ric" 1K
iSS~RSS:
l ___________ J
VT
= O.6V
Ileakage
±500nA
Chold
= DAC capacitance
= 51.2 pF
Vss
Legend
Cpin
VT
Ileakage
Ric
Rss
SS
Chold
Rs
VA
input capacitance
threshold voltage
leakage current at the pin due to various junctions
interconnect resistance
on resistance of the switch
= sampling switch
= sample/hold capacitance (from DAC)
= source impedance of the analog input
= analog input voltage
=
=
=
=
=
FIGURE 6.6.5.1· TRANSFER FUNCTION
,----------------------------------------------------------------------------
I
i
FFh
<56
FEh
·g,s
04h
03h
02h
01h
OOh '--;L-f---t---+---+--------------------+----r----
cc
(j)
...J
(\J
Analog input
voltage
D830150B - page 34
~lJ®~ 0mru 0Uil~lJW
1-138
© 1992 Microchip Technology Incorporated
After a conversion is completed, sampling begins after
a delay of 2tad. (tad = AID conversion clock). The user
must keep this in mind when allowing for adequate
sampling time.
External RC filter is sometimes added for anti-aliasing.
Once again, the value of the R should be such that the
total source impedance is kept under 10Kn. Anyexternal component connected to an analog input pin, such
as a capacitor or a zener diode, should have very little
leakage current.
6.6.5 Transfer Function
The ideal transfer function of the AID converter is as
follows: The first transition occurs when input voltage
(VA) is 1 LSB (or full scalet256). Figure 6.6.5.1 shows
the ideal transfer function.
6.6.4 Sample and Hold (S/H)
The sample and hold circuit consists of a sampling
switch SS (figure 6.6.3.1) and the StH capacitor whose
value is typically 51 pF.
6.6.6 SUMMARY OF AID REGISTERS
As long as ADON control bit is '1' (bit 0, ADCON 0) and
a valid analog input channel is selected, the input will be
continuously sampled. There is no command to start or
stop sampling. When a conversion is started, sampling
is ended and conversion begins on the voltage across
the StH capacitor. The sample and hold, therefore can
be more accurately described as "track and hold".
Register namelblts
Function
ADRES
ADCONO
AID result register
AID control and
status register
AID control register
Interrupt control register
ADCONI
INTCON (bit ADIE)
Address
09h
OSh
SSh
OBh
7.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings·
'Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or compliance
to AC and DC parametric specifications at those or any other
conditions above those indicated in the operation listings of this
specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Ambient temperature under bias ............ -55 to+ 125'C
Storage Temperature ....................... - 65'C to +150'C
Voltage on any pin with respect to Vss
(except Voo and MCLR) ................ -0.6V to Voo +0.6V
Voltage on Voo with respect to Vss ............... 0 to +7.5 V
Voltage on MCLR with respect to Vss
(Note 2) ........................................................ 0 to +14 V
Total power Dissipation (Note 1) .................... BOO mW
Max. Current out of Vss pin ............................. 150 mA
Max. Current into Voo pin ................................ 100 mA
Max. Current into an input pin ......................... ±500 nA
Max. Output Current sunk by any I/O pin .......... 25 mA
Max. Output Current sourced by any I/O pin ..... 20 mA
Max. Output Current sunk by I/O port A ............ BO mA
Max. Output Current sunk by I/O port B .......... 150 mA
Max. Output Current sourced by I/O port A ....... 50 mA
Max. Output Current sourced by I/O port B ..... 100 mA
© 1992 Microchip Technology Incorporated
Notes: 1. Total power dissipation should not exceed BOO
mW for the package. Power dissipation is
calculated as follows:
Pdis = Voox {Ioo - I, loh} + I, {(Voo-Voh) x loh}
+ I,(Vol x 101)
2. Voltage spikes below vss at the MCLR pin,
inducing currents greater than BOmA, may
cause latch-Up. Thus, a series resistor of 50100n should be used when applying a "low'
level to the MCLR pin rather than pulling this
pin directly to Vss.
~ [J® ~ 0QVO 0[llHID [JW
1-139
DS301508 - page 35
7.1 DC CHARACTERISTICS: PIC16C71-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
PIC16C71-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
Standard Operating Conditions (unless otherWise stated)
Operating temperature -40'C ~ TA ~ + 12S'C for automotive,
-40'C ~ TA ~ + 8S'C for industrial and
O'C ~ TA ~ +70'C for commercial
Operating voltage Voo = 4.0V t06.0V
DC CHARACTERISTICS,
POWER SUPPLY PINS
,
Characteristic
Sym
Min
Typ
Max
(Note 1)
Units
Conditions
Supply VI/ltage
RAM Data Retention
Voltage (Note 2)
Voo start voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 3)
Voo
Voo
VOR
4.0
4.5
VPOR
Svoo
6.0
5.5
1.5 •
V
V
V
Xl, RC and LP osc configuration
HS osc configuration
Device in SLEEP mode
Vss'
V
See section 5.2 for details on power on reset
V/ms
See section 5.2 for details on power on reset
mA
Fosc = 4 MHz, Voo = 5.5V (Note S)
Fosc = 32 KH.z, Voo = 4.0V, WDT disabled,
0.05'
1001
1002
1.8
35
3.3
70
!lA
1003
9
20
mA
LP osc config., NO off (Note 6)
Fosc = 20 MHz, Voo = 5.5V, HS osc configuration
(PIC16C71-20)
Ip01
Ip02
Ip03
Ip04
7
1.0
1.0
1.0
28
14
16
20
!lA
!lA
!lA
!lA
Voo = 4.0V, WDT enabled, -40'C to +125'C
Voo = 4.0V, WDT disabled, O'C to +70'C·
Voo = 4.0V, WbT disabled, -40'C to +85'C
Voo = 4.0V, WDT disabled, -40'C to +125'C
Power Down Current
(Note 4)
, These parameters are guaranteed through characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note S:
Note 6:
Data in the column labeled "Typical" is based on characterization results at 2S'C. This data is for design
guidance only and is not tested for, or guaranteed by Microchip Technology.
This is the limit to which VOD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as 1/0 pin
loading and switching rate, osciliatortype, internal code execution pattern, and temperature also have an impact
on the current consLimption.
The test conditions for all 100 measurements in active operation mode are:
OSC1=external square wave, from railto rail; all 1/0 pins tristated, pulled to Voo, RT = Voo, MCLR = Voo; WDT
enabledldisabled as specified.
The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all 1/0 pins in hi-impedence state and tied to Voo and Vss.
For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = Voo/2Rext (mA) with Rext in kOhm.
For current contribution due to AID module, see section 7.S.
08301508 - page
36
[P[J®~O m 0IT1l(ID[JW
t·140
© 1992 Microchip Technology Incorporated
7.2 DC CHARACTERISTICS: PIC16LC71-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40'C ::; TA ::; + 125'C for automotive,
-40'C ::; TA::; + 85'C for industrial and
O'C ::; TA::; +70'C for commercial
Operating voltage VDD = 3.0V to 6.0V
DC CHARACTERISTICS,
POWER SUPPLY PINS
Characteristic
Sym
Min
Typ
Max
(Note 1)
Conditions
Units
Supply Voltage
RAM Data Retention
Voltage (Note 2)
Voo start voltage to
guarantee power on reset
Voo rise rate to guarantee
power on reset
Supply Current (Note 3)
Voo
Voo
VOR
VPOR
Svoo
1001
1002
1.5 *
V
V
V
Xl, RC and LP osc configuration
HS osc configuration
Device in SLEEP mode
Vss *
V
See section 5.2 for details on power on reset
V/ms
See section 5.2 for details on power on reset
mA
Fosc = 4 MHz, Voo = 5.5V (Note 5)
Fosc = 32 KHz, Voo = 3.0V, WDT disabled,
3.0
4.5
6.0
5.5
0.05*
1.8
15
3.3
32
lJA
LP osc config., AID off (Note 6)
Power Down Current
(Note 4)
Ip01
Ip02
Ip03
Ip04
S
0.6
0.6
0.6
20
9
12
16
lJA
lJA
lJA
lJA
Voo = 3.0V, WDT enabled, -40'C to +12S'C
Voo = 3.0V, WDT disabled, O'C to +70'C
Voo = 3.0V, WDT disabled, -40'C to +8S'C
Voo = 3.0V, WDT disabled, -40'C to +12S'C
* These parameters are guaranteed through characterization and are not tested.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Data in the column labeled "Typical" is based on characterization results at 25'C. This data is for design
guidance only and is not tested for, or guaranteed by Microchip Technology.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact
on the current consumption.
The test conditions for alllDD measurements in active operation mode are:
OSC1 =external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, RT = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to VDD and Vss.
For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
For current contribution due to AID module, see section 7.5.
© 1992 Microchip Technology
Incorporated
~u@~ 0M 0IT1lCIDuW
1-141
DS301508 - page 37
7.3 DC CHARACTERISTICS:
PIC16C71·04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
PIC16C71·20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
PIC16LC71·04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
DC CHARACTERISTICS,
ALL PINS EXCEPT POWER SUPPLY
Characteristic
Input Low Voltage
1/0 ports
MCLR, RTCC, OSC1
(in RC configuration)
OSC1 (in XT, HS and LP
configuration)
Input High Voltage
1/0 ports
MCLR RTCC, OSC1
(in RC configuration)
OSC1 (XT, HS and LP
configuration)
Input Le~kage Current
(Notes 3, 4)
1/0 port RB
1/0 port RA
MCLR, RTCC
OSC1
Output Low Voltage
1/0 Ports
OSC2/CLKOUT
(RC asc configuration)
Output High Voltage
1/0 Ports (Note 4)
OSC2/CLKOUT
(RC asc configuration)
Sym
Min
Standard Operating Conditions (unless otherwise stated)
-40'( ,;; TA ,;; +125'C for automotive,
Operating temperature
-40 ,;; TA ,;; +85'C for industrial
and O'C,;; TA';; +70'C for commercial
Operating voltage Voo range as described in DC spec table 7.1
Typ
(Note 1)
Max
Units
Conditions
VIl1
VIl2
Vss
Vss
0.2 VDD
0.2 VDD
V
V
VIl3
Vss
0.3 VDD
V
VIH1
VIH1
VIH2
2.0
0.36 VDD
0.8 VDD
VDD
V
VDD
V
VIH3
0.7 VDD
VDD
V
IIl1
IIl2
IIl3
IIl4
±1
±O.'5
±5
±5
!lA
!lA
!lA
!lA
Vss ,;; VPIN ,;; VDD, Pin at hi-impedance
Vss ,;; VPIN ,;; VDD, Pin at hi-impedance
Vss ,;; VPIN ,;; VDD
Vss ,;; VPIN ,;; VDD , XT, HS and LP osc
configuration
VOl1
VOl1
VOl2
VOl2
0.6
0.6
0.6
0.6
V
V
V
V
10l = 8.5 rnA,
10l = 7.0 rnA,
IOl = 1.6 rnA,
10l = 1.2 rnA,
V
V
V
V
10H = -3.0
10H = -2.5
10H = -1.3
10H = -1.0
VOH1
VOH1
VOH2
VOH2
VDD-O.l
VDD-O.l
VDD-0.7
VDD-O.l
Note 2
VDD';; 5.5V
For entire VDD range
Note 2
VDD = 4.5V,
VDD = 4.5V,
VDD = 4.5V,
VDD = 4.5V,
-40'C to +85'C
-40'C to +125'C
-40'C to +85'C
-40'C to +125'C
rnA, VDD = 4.5V,
rnA, VDD = 4.5V,
rnA, VDD = 4.5V,
rnA, VDD = 4.5V,
-40'C to +85'C
-40'C to +125'C
-40'C to +85'C
-40'C to +125'C
Note 1: Data in the column labeled "Typical" isbased on characterization results at 25 ' C. This data is for design guidance
only and is not tested for, or guaranteed by Microchip Technology.
Note 2: In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C71
be driven with external clock in RC mode.
Note 3 : The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Note 4 : Negative current is defined as coming out of the pin.
OS301508 - page 38
[P[J®~ 0M 0IT1l(IDuW
1-142
© 1992 Microchip Technology Incorporated
7.4 AC CHARACTERISTICS:
PIC16C71-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
PIC16C71-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
PIC16LC71-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40'C ,;; TA ,;; + 12S'C for automotive,
-40,;; TA';; +8S'C for industrial
and O'C,;; TA';; +70'C for commercial
Operating voltage VDD range as described in DC spec table 7.1
AC CHARACTERISTICS
• Guaranteed by characterization, but not tested,
(Notes on next page)
Characteristic
External ClOCKIN
Frequency (Note 2)
Oscillator Frequency
(Note 2)
Instruction Cycle Time
(Note 2)
External Clock in Timing
(Note 4)
Clock in (OSC1) High or Low Time
XT oscillator type
LP oscillator type
HS oscillator type
Clock in (OSC1) Rise or Fall Time
XT oscillator type
LP oscillator type
HS oscillator type
RESET Timing
MCLR Pulse Width (low)
RTCC Input Timing, No Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Input Timing, With Prescaler
RTCC High Pulse Width
RTCC Low Pulse Width
RTCC Period
Sym
Typ
Max
(Note 1)
Min
Units
Conditions
XT and RC oSC mode
HS osc mode (PIC16C71-04
PICI6lC71-04)
HS osc mode (PICI6C71-20
LP osc mode
RC osc mode
XT osc mode
HS osc mode (PIC16C71-04
PICI6LC71-04)
HS osc mode (PIC16C71-20
LP osc mode
Fosc
Fosc
DC
DC
4
4
MHz
MHz
Fosc
Fosc
Fosc
Fosc
Fosc
DC
DC
DC
0.1
1
20
200
4
4
4
MHz
KHz
MHz
MHz
MHz
Fosc
Fosc
Tcy
1
DC
1.0
20
200
DC
MHz
KHz
TCKHLXT
TCKHLLP
TCKHLHS
SO*
2*
20*
!IS
TCKRFXT
TCKRFLP
TCKRFHS
2S'
SO*
2S*
ns
ns
ns
TMCL
100*
ns
TRTH
TRTL
O,S TCYt 20*
O.S TcYt 20*
ns
ns
Note 3
Note 3
TRTH
TRTL
TRTP
10*
10*
ns
ns
ns
Note 3
Note 3
Note 3. Where N =prescal
value (2,4, ... , 2S6)
4/Fosc
!IS
ns
ns
TCY + 40
N
*
Watchdog Timer Timeout Period
(No Prescaler)
Oscillation Start-up Timer Period
Power up timer period
I/O Timing
1/0 Pin Input Valid Before
CLKOUr" (RC Mode)
1/0 Pin Input Hold After
CLKOUr" (RC Mode)
1/0 Pin Output Valid After
CLKOUTO (RC Mode)
Capacitive loading Specs on Output Pins
OSC2 pin
TWOT
TOST
TpWRT
7*
Tos
0.2S TCYt 30*
ns
TOH
0*
ns
All 1/0 pins
© 1992
Microchip Technology Incorporated
18*
1024 tosc
72*
28*
33*
132*
ms
ms
ms
Tpo
40*
ns
COSC2
1S
pF
CIO
SO
pF
~u@~DmmDOllClliuW
1-143
VOO =SV, -40'C to t 12S'C
tosc =OSC1 period
Voo =SV, -40'C to t 12S'C
In XT, HS and LP modes
when external clock is used
to drive OSC1.
DS301508 .
page 39
NOTES TO TABLE 7.4
Note 1: Data in the column labeled 'Typical" is based on characterization results at 2S'C. This data is for design guidance only and is nottested
for, or guaranteed by Microchip Technology.
Note 2: Instruction cycle period (Tcy) equals four times the input oscillator time base period.
All specifiedyalues are based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specHied limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at "min.' values with an extemal clock applied to the OSCI pin.
When an external clock Input is used, the "Max." cycle time limit Is "DC" (no clock) for all devices,
Note 3: For a detailed explanation of RTCC input clock requirements see section 6.4.1.
Note 4: Clock-in high-time is the duration for which clock input is at VIHOSC or higher. Clock-in low-time is the duration for which clock input is
at VIHOSC or lower.
PIC16C71-04 (COMMERCIAUINDUSTRIAL, AUTOMOTIVE)
PIC16C71-20 (COMMERCIAUlNQUSTRIAL, AUTOMOTIVE)
PIC16LC71-04 (COMMERCIAL/INDUSTRIAL, AUTOMOTIVE)
7.5 AID CONVERTER
CHARACTERISTICS:
Standard Conditions (unless otherwise stated)
Operating temperature
-40'C to +12S'C for automotive,
TA = -40'C to +8S'C for industrial and O'C ~ TA ~ +70'C
for commercial, Voo = S.12V
Sym
Min
Typ
Max
Units
Conditions
(Note 1)
NR
8 Bits
- VREF = Voo - S.12V (Note 21
NINT
less than VREF = Voo = S.12V (Note 2)
±1 LSB
NOIF
less than VREF = Voo = S.12V (Note 2)
±1 LSB
NFS
less than VREF = Voo = S.12V (Note 2)
+1 LSB
NOFF
less than VREF = Voo = S.12V (Note 2)
+1 LSB
Iguaranteed
VREF 3.0V
Voo+ 0.3 V
VAIN VSS- 0.3 VREF
V
AC CHARACTERISTICS
Characteristic
Resolution
Integral error
Differential error
Full scale error
Offset error
Monotonicity
Reference volta.Qe
Analog input voltage
Recommended
Impedance of analog
voltaae source
AID clock period
-
:lAIN
tad
-
-
-
2tosc
8tosc
32tosc
4.0
-
2.0
Conversion time
TCNV (not including S/H time)
Sampling time
TSMP S
10.0
Kn
-
-
6.0
Ils
10tad
-
-
-
-
j.lS
-
ADCSI ,0 = 00 (for tosc ~ 1 Ils)
ADCSI ,0 = 01 (for tosc ~0.2SIlS)
ADSCI ,0 = 10 (for tosc ~ 62.S ns)
ADSCI ,0 = 11 (RC oscillator'
source is selected)
-
For 10K(} source impedance, to
guarantee less than 118 LSB
samolina error. (Note 3)
Average current consumption
when AID is on (Note 41
During charging
All other times
AID conversion
lad
180
IlA
current Noo}
VREF Input current
IREF 1
mA
(Note S)
10
1lA·
Note 1. All entries In the 'typ column are at 5V, 25 C unless otherwise stated.
Note 2: The error will be more for lower VREF and/or lower Voo.
Note 3: Sampling time may be less (or more) if source impedance is smaller (or higher). Also note that sampling begins after
2tad delay after a conversion is completed.
Note 4: When AID is oft, it will not consume any current other than minor leakage current. The power down current spec includes
any such leakage from the AID module.
Note 5: VREF current is from RA3 pin or Voo pin, whichever is selected as reference input.
08301508 - page 40
~[f@~ 0mru 0[fj)~:HFW
1-144
© 1992 Microchip Technology Incorporated
PIC16LC71-04 (COMMERCIAL/INDUSTRIAL, AUTOMOTIVE)
7.6 AJD CONVERTER
CHARACTERISTICS:
AC CHARACTERISTICS
Characteristic
Standard Conditions (unless otherwise stated)
-40·C to +125·C for automotive,
Operating temperature
TA = -40·C to +S5·C for industrial and O·C ~ TA ~ +70·C
for commercial, Voo = 3.0V
Sym
Min
Typ
(Note 1)
Resolution
Integral error
NR
NINT
Differential error
NOIF
Full scale error
NFS
Offset error
NOFF
Monotonicltv
Reference voltage
Analog input voltage
Recommended
impedance of analog
voltaae source
AID clock period
I auaranteed
VREF 3.0 V
Voo+ 0.3
VAIN Vss- 0.3 VREF
S Bits
less than
±2 LSB
less than
+2 LSB
less than
+2 LSB
less than
+2 LSB
Units
Conditions
-
VREF = voo = 3.0V (Note 2)
VREF = Voo = 3.0V (Note 2)
-
VREF = Voo = 3.0V (Note 2)
-
VREF = Voo = 3.0V (Note 2)
VREF = Voo = 3.0V (Note 2)
V
V
ZAIN
-
-
10.0
Kn
tad
-
2tosc
Stosc
32tosc
6.0
-
-
-
9.0
f.lS
ADCSI ,0
ADCSI ,0
ADSCI ,0
ADSCI ,0
10tad
-
-
-
-
-
f.lS
90
-
f.lA
1
10
f.lA
For 10Kn source impedance, to
guarantee less than liS LSB
sampling error. (Note 3)
Average current consumption
when AID is on (Note 4)
During charging
All other times
3.0
Conversion time
TCNV (not includina S/H timel
Sampling time
TSMP 5
AID conversion
current (Voo)
VREF input current
(Note 5)
-
Max
lad
-
IREF
-
mA
= 00 (for tosc ~ 1 /-ls)
= 01 (for tosc~0.25 f.lS)
= 10 (for tosc ~ 62.5 ns)
= 11 (RC oscillator
source is selected)
Note 1: All entries in the "typ" column are at 5V, 25"C unless otherwise stated.
Note 2: These specifications apply if VREF = 3.0V and if VDD ~ 3.0V.
Note 3: Sampling time may be less (or more) if source impedance is smaller (or higher). Also note that sampling begins after
2tad delay after a conversion is completed.
Note 4: When ND is off, it will not consume any current other than minor leakage current. The power down current spec includes
any such leakage from the ND module.
Note 5: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
© 1992 Microchip Technology Incorporated
~ [)'@ ~ 0[ffij) 0[Jj)~[)'W
1-145
05301506 - page 41
7.6.1 Electrical Structure of Pins
FIGURE 7.6.1 - ELECTRICAL
STRUCTURE OF I/O PINS (RA, RB)
Vss
FIGURE 7.6.2 - ELECTRICAL
STRUCTURE OF MCLR AND RTCC PINS
vss
VSS
Rin
Vss
Input
buffer
Notes to figures 7.6.1 and 7.6.2: The diodes and the grounded gate (or output driver) NMOS device are carefully designed to protect against ESD
(Electrostatic discharge) and EOS (Electrical overstress). Rin is a small resistance to further protect the input buffer from ESD.
8.0 TIMING DIAGRAMS
FIGURE 8.0.1 - RTCC TIMING
:--TRTH - :,
:-TRTL
- - :,
,
~i
RTCC~i
Aun~:~:
.\
:
,
TRTP
:
FIGURE 8.0.2 - OSCILLATOR START-UP TIMING (PIC16C71 RC)
,
~-----
~j.--TCY~:
:~Tcy
I
I"
Tost
I
I
Tcy/2
.'
I
I
I
I
I
I
CLKOUT
(RC osc config.) _ _ _ __
DEVICE _ __
FUNCTION
RESET
,
__---<.~:'
FETCH 1. INSTRUCTION I FETCH 2. INSTRUCTION I
: EXECUTE "FORCED" NOP : EXECUTE 1. INSTRUCTION: - - - -
FIGURE 8.0.3 - INPUT/OUTPUT TIMING FOR I/O PORTS
,
,
,..,..
_ - - - - - - - - - Tcy
OSC2/i
'
I'
'-----,--;:;--------1 Tdh
CLKOUT
~Tds
INPUT
~$d
~
, Tpd:
OUTPUT
Notes:
- - - - - - - - - 4...
~'
1.
2.
DS30150B - page 42
1
I
_l0iii .. [
,
W/ff#$/$//aw~m
VALID
Note 2
'--'
' Tpd '
~HmIG~H~.~Z:_<======================================='===~
The CLKOUT output is available only in RC oscillator mode.
Internally, this is the point where input data is sampled. Since no timing edge is externally
available, setup and hold times are specified with respect to the rising edge of CLKOUT.
[J2l [J@ ~ 0m 0[jj) ~)[rw
1-146
© 1992 Microchip Technology Incorporated
9.0 DC & AC CHARACTERISTICS
GRAPHSITABLES:
FIGURE 9.0.1 - TYPICAL RC OSCILLATOR
FREQUENCY vs. TEMPERATURE
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed. In
FREQUENCY NORMALIZED TO +25"C
Fosc
Foso (2S"C)
Rext~ 10Kn
Cext .. 100pF
1.10
some graphs or tables the data presented are out·
side specified operating range (e.g. outside specified Voo range). This is for information only and
devices are guaranteed to operate properly only
within the specified range.
1.08
1.06
1.04
....
1.02
1IIIIIIIiIIIII ...
...............
1.00
The data presented in this section is a statistical summary of data collected on units from different lots over a
period of time. 'Typical' represents the mean of the
distribution while 'max' or 'min' represents (mean + 30)
and (mean - 30) respectively where 0 is standard deviation.
............
0.98
Voo= 5.5V
~
0.96
0.94
0.92
0.90
10
25
40
50
60
70
T("C)~
FIGURE 9.0.3 - TYPICAL RC OSCILLATOR
FREQUENCY vs Voo
FIGURE 9.0.2 - TYPICAL RC OSCILLATOR
FREQUENCY vs Voo
5.0
/"
4.5
4.0
~
~
-
R=3.3k
1.8
/
T
R=3.3k
./
1.6
1.4
---
13.5
~
N
.c
1.2
R=5k
N
3.0
I--.
R=5k
~1;l 10.
~
1;l 2.5
-- ------
,f
0
u.
0.8
-
2.0
R=10k
0.6
1.5
R=10k
0.4
1.0
Cext = 100pF, T = 2S"C
Cext = 20pF, T = 25"C
1
0.5
I'
1
I
2.5
3.0
3.5
4.0
4.5
VDD(VoItS)
0.2
R=100k
R=100k
5.0
5.5
2.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voo(Volts)
Note: The gray shaded regions are outside normal PIC operating range. Do not operate in these regions.
© 1992 Microchip Technology Incorporated
[?)[f®~ 0m 0[iU®[fW
1·147
DS30150B • page 43
FIGURE 9.0.4 - TYPICAL RC OSCILLATOR
FREQUENCY vs Voo
TABLE 9.0.1 - RC OSCILLATOR FREQUENCIES
11
O.B
Cext
:11'
~
-
0.7
I
---I
0.6
r-N
..c
0.5
------
~
0
(f)
0
u.. 0.4
i
f--
0.3
0.2
t--
I
Cext
I
0.1
-
~::3k
-
~~
Fosc @ 5V, 25"C
-
;--
I
-
R~10k
I
4.71 MHz
3.31 MHz
1.91 MHz
207.76 KHz
±28%
±2S%
±24%
±39%
100pf
3.3k
Sk
10k
100k
1.6S MHz
1.23 MHz
711.S4 KHz
7S.62 KHz
± 18%
±21%
± 18%
±28%
300pf
3.3k
Sk
10k
100k
672.78
489.49
27S.73
28.12
±14%
±13%
± 13%
±23%
3.5
4.0
KHz
KHz
KHz
KHz
The percentage variation indicated here is part to part
variation due to normal process distribution. The variation indicated is ±3 standard deviation from average
value for full VDD range.
R-100k
3.0
3.3k
Sk
10k
100k
I
I
2.5
r--
20pf
= 300pF, T = 2S'C
I
Average
Rext
4.5
5.0
5.5
6.0
Voo(Volts)
FIGURE 9.0.5 - TYPICAL Ipd vs Voo
WATCHDOG DISABLED 25"C
FIGURE 9.0.6 - TYPICAL Ipd vs Voo
WATCHDOG ENABLED 25"C
2.5
8
/
1.5
1/
0.5
/
/
/
/
!/
4
V
2
/
a
II
/
I
/
/
6
4
/
L
/
/
I
I
a
o
2.5
/
6
3.0
3.5
4.0
4.5
5.0
5.5
2.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(Volts)
Voo(VoltS)
Note 1: The gray shaded regions are outside normal PIC operating range. Do not operate in these regions.
DS30150B - page 44
~u®~ 0mm 0ITi)@[JW
1-148
© 1992 Microchip Technology Incorporated
FIGURE 9.0.7 - MAXIMUM Ipd vs Voo
WATCHDOG DISABLED
Maximum
18
12
~
---
/'
/
.. . ' -
/
/
/
-
/
/
/
/
/
/
/
/
,,
,
-40
/
/
/
/
.
-
/
o
2.5
3.0
3.5
/
/
V
~
/
,,
//
/
/70,
,
,
" 0
,,
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
-- -
.- -
2
/'
10
/
/
V
/
,
15
/
/
/
/
0,
/
- - .
,
20
,
//
/
/
4
/
/
/
/
/
,
/'
/
25
70
/
/
/
/
,,
V
30
1/
/
---~--~
Temp. eC) 1-40/
/
V
/
14
Maximum
35,------------
Te~p. ('C)I = 85
I
16
8
FIGURE 9.0.8 - MAXIMUM Ipd vs Voo
WATCHDOG ENABLED'
///
/
/
5
4.0
4.5
Voo(Volts)
5.0
5.5
:/
//
J
~5
6.0
/
3~
35
40
45
Voo(Volts)
5~
---:'"::----0
55
~o
IPO, with watchdog timer enabled, has two components: The leakage current which increases with higher temperature and the
operating current of the watchdog timer logic which increases with lower temperature. At -40'C, the latter dominates explaining the
apparently anomalous behavior.
Note 1: The gray shaded regions are outside of the normal PIC operating range. Do not operate in these regions.
FIGURE 9.0.9 - VTH (INPUT THRESHOLD VOLTAGE) OF 1/0 PINS vs Voo
VTH (Input threshold voltage) of I/O
2.00
),
1.60
en
'5
1.40
G
I
!>
1.20
1-00
0_80
0.60
(;c)
o'c\O~
1.80
---- ------
----
--- ~
L
ZS'c,I'i~
------------ ----p--------
~.lAG'C\OS~
'c)
----
-------------
2.5
3.0
3.5
4.0
45
5.0
------
---------
5.5
6.0
VDD (volts)
© 1992 Microchip Technology Incorporated
~U®~~MOITll@[JW
1-149
05301508 - page 45
FIGURE 9.0.10- VIH, VIL OF MCLR, RTCC AND OSC1 (IN RC MODE) vs Voo
4.50
4.00
J,
3.50
~
~
V
.
~ '\j'"
'\j," (\\'
.'!l
~ 2.50
:...----............: ~
..---;:::. ~ ----
...J
1.00
!jC)
'\'{1'.Z6 C s,,'C)
(I ,,~Q' C \0
3.00
:> 2.00
:r
:> 1.50
---::::
rjC~V-.. . . . . .
j."~
~
-
VIL, max (.40·C to DO'C)
VIL, TYP, 25'C
VIL, min (.40·C to 85'C)
0.50
0.00
2.5
3.0
4.0
3.5
4.5
5.0
6.0
5.5
Voo (volts)
Note: These input pins have Schmitt trigger input buffer.
FIGURE 9.0.11 - VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
vs Voo
3.40
3.20
3.00
.~Q·c\O
2.80
~~
2.60
:§' 2.40
~
'0
~
2.20
> 2.00
..............-
1.80
1.60
V
1.40
V
1.20
----
..-------
..-------
J:
f-
1.00
s~
.....---/ ......---- ......-----V
......- ......----
~
......----
----
~ ------
----/
·C
Z<"
~
.~Q'c \0
~
-----------/ V
..............2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voo (volts)
Note: The gray shaded regions are outside of the normal PIC operating range. Do not operate in these regions.
DS301508 - page 46
~[J@~ 0M 0[Jj]~j[rw
1-150
© 1992 Microchip Technology Incorporated
FIGURE 9.0.12 - TYPICAL 100 vs FREQ (EXT CLOCK, 25°C)
10
/-
,,0"~
0/
& ~%
1.0
./h './ ./
./././. . /
ij"'//V
........-::
0.1
=
5.5
- 5.0
- 4.5
-4.0
3.5
- 3.0
----
W
bl~
b::; 8;:
V'
V/, ./
V
/'
-------
V
0.01
10K
1M
100K
10M
100M
External Clock freq (Hz)
FIGURE 9.0.13 - MAXIMUM 100 vs FREQ (EXT CLOCK, _40° to +85°C)
10
////'
W//
/
z:v
d- ~~
1.0
L./.
:-
;-1\'-_..LI__
X -LX.L._x~)r-:
LY\
~:
t5ett:-:
:
~: thldl
:11-1 8 min.:
~
lOOns
min.
RS? = output
RS? '" input
Reset
: RS?
: input
~ I •
ProgramNerify Test Mode
••
FIGURE 11.4.4.1 • INCREMENT ADDRESS COMMAND (SERIAL PROGRAMIVERIFY)
VIHH
--~------------'-----------------
MCLR~
2
RB6
(CLOCK)
4
3
5
Next Command
2
----fLIl ..... .
_~_---'
RB?
(DATA)
• tdly2 • '
6 1~s min. ;
/
X /
1
_ _X
'-'--_X~~ - - - - - t=x=\
\ \----,--+
, , !
0
X
tset1~:
,
, thld1
: tdly1
0
:
~,
:1~s
min.:
100ns
min.
Resffi-+.~.r--_--------P-ro~g-ra-m-/V-e-ri~fy-T-e-st-M_o_d_e_ _ _ _ _ _ _ _ _ ___
11.4.6 End Programming
After receiving this command, the chip stops programming the memory (configuration program memory or
user program memory) that it was programming at the
time.
All commands are transmitted Isb first. Data words are
also transmitted Isb first. The data is transmitted on the
rising edge and latched on the falling edge of the clock.
To allow for decoding of commands and reversal.of data
pin configuration, a time separation of at least 1us is
required between a command and a data word (or
another command).
11.4.5 Begin Programming
A load command (load configuration or load data) must
be given before the begin programming command.
Programming of the appropriate memory (test program
memory or user program memory) will begin after this
command is received and decoded. Programming
should be performed with a series of 100 j.!s programming pulses. A programming pulse is defined as the
time between the begin programming command and the
end programming command.
DS30150B - page 56
~ [J@ ~ 0mJlJ 0rru ~Hrw
1-160
© 1992 Microchip Technology Incorporated
To properly take advantages of these features,
PICMASTER requires installation on a system having
the following minimum configuration:
12.0 DEVELOPMENT SUPPORT
12.1
PICMASTERTM: High Performance
Universal In-Circuit Emulator System
• PC AT compatible machine: 80286, 386SX, 386DX,
or 80486 with ISA or EISA Bus.
The PICMASTER Universal In-Circuit Emulator System
is intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16CXX and PIC17CXX families. This system currently supports the PIC16CR54,
PIC16C54, PIC16C55, PIC16C56 and PIC16C57, and
PIC17C42 processors. PIC16C71 support is planned.
EGA, VGA, 8514/A, Hercules graphic card (EGA or
higher recommended).
• MSDOS / PC DOS version 3.1 or greater.
Microsoft Windows® version 3.0 or greater operating
in either standard or 386 enhanced mode).
• 1 Mbyte RAM (2 Mbytes recommended).
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new PIC16CXX and
PIC17CXX microcontrollers.
• One 5.25" floppy disk drive.
• Approximately 10 Mbytes of hard disk (1 Mbyte
required for PICMASTER, remainder for Windows
3.X system).
The Emulator System is designed to operate on low-cost
PC compatible machines ranging from 80286-AT class
ISA-bus systems through the new 80486 EISA-bus
machines. The development software runs in the
Microsoft Windows® 3.0 environment, allowing the operator access to a wide range of supporting software and
accessories.
• One 8-bit PC AT (ISA) I/O expansion slot (half size)
• Microsoft® mouse or compatible (highly recommended).
12.1.2 Emulator System Components:
The PICMASTER Emulator Universal System consists
primarily of 4 major components:
Provided with the PICMASTER System is a high performance real-time In-Circuit Emulator, a programmer unit
and a macro assembler program.
Host-Interface Card: The PC Host Interface Card
connects the emulator system to an IBM PC compatible system. This high-speed parallel interface requires a single half-size standard AT / ISA slot in the
host system. A 37-conductor cable connects the
interface card to the external Emulator Control Pod.
Coupled with the user's choice of text editor, the system
is ready for development of products containing any of
Microchip's microcontroller products.
A "Quick Start" PIC Product Sample Pak containing
user programmable parts is included for additional convenience.
Emulator Control Pod: The Emulator Control Pod
contains all emulation and control logic common to all
microcontroller devices. Emulation memory, trace
memory, event and cycle timers, and trace/breakpoint
logic are contained here. The Pod controls and
interfaces to an interchangeable target-specific emulator probe via a 14" precision ribbon cable.
Microchip provides additional customer support to developers through an Electronic Bulletin Board System
(EBBS). Customers have access to the latest updates
in software as well as application source code examples. Consult your local sales representative for
information on accessing the BBS system.
Target-specific Emulator Probe: A probe specific
to microcontrollerfamily to be emulated is installed on
the ribbon cable coming from the control pod. This
probe configures the universal system for emulation
of a specific microcontroller.
12.1.1 Host System Requirements:
The PICMASTER has been designed as a real-time
emulation system with advanced features generally
found on more expensive development tools. The AT
platform and Windows 3.X environment was chosen to
best make these features available to you the end user.
• PC Host Emulation Control Software: Host software necessary to control and provide a working user
interface is the last major component of the system.
The emulation software runs in the Windows 3.X
environment, and provides the user with full display,
alter, and control of the system under emulation. The
Control Software is also universal to all microcontroller
families.
© 1992 Microchip Technology Incorporated
DS30150B - page 57
1-161
The Windows 3.X System is a multitasking operating
system which will allows the developer to take full
advantage of the many powerful features and functions oUhe PICMASTER system.
between two or more Windows programs. With this
feature, data collected with PICMASTER can be automatically transferred to a spreadsheet or database
program for further analysis.
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
Dynamic Data Exchange (DOE), a feature of Windows
3.X, will be available in this and future versions of the
software. DOE allows data to be dynamically transferred
Under Windows 3.X, two or more PICMASTER emulators can run simultaneously on the same PC making
development of multi-microcontroller systems possible
(e.g., a system containing a PIC16Cxx processor and a
PIC17Cxx processor).
FIGURE 12.1.1 - PICMASTER
FIGURE 12.1.2 - PICMASTER SYSTEM CONFIGURATION
0 11/111111111111111111','.
Common Interface Card
PC Compatib,e Computer
(ATIISA Bus) (for Industry Standard Architecture)
08301508 . page 58
~ u® ~ 0M 0OllCID uW
1-162
© 1992 Microchip Technology Incorporated
FIGURE 12.1.3 - PICMASTER TYPICAL
SCREEN
file
.configure
,Setup
Watch
Bun
.utility
004.9
0048
00000 :
00001 ;
00
0880
capl
0860.
CC
00
co
00
co
;!:
;;;.,
file
Edit
•
A1
.
C80
06.
+
D.ata
~I'I
I-l-
r+
f4r+
r4Kr4-
~
C1t
Help
..
l=J1
Qption,
Maao
YiJndow
>:[Ii]Z]---,
The PRO MASTER has programmable Voo and VPp
supplies which allows it to verify the PIC at Voo min and
Voo max for maximum reliability. It has an LCD display
for displaying error messages, keys to enter commands
and a modular detachable socket assembly to support
various package types. In stand alone mode the PRO
MASTER can read, verify or program a part. It can also
set fuse configuration and code-protect in this mode. It's
EEPROM memory holds data and parametric information even when powered down. It is ideal for low to
moderate volume production.
~I
DDEDEMOXLS
~
c+-
The PRO MASTER programmer is a production quality
programmer capable of operating in stand alone mode
as well as PC-hosted mode.
Microsoft Excel
Formal
Fo(mula
Norm!!1
r",tlw
retlw
..
WindQw
Trace Memory Dump
12.3 PRO MASTERTM
..
A
2176
B
2154
2132
2112
C
D
E
F
G
loata From PIC-MASTER via ODEI
2_~_
o
~
o
o-
"tJ
FIGURE A: PIC17C42 BLOCK DIAGRAM
o
c;j
CD
@I
..&.
fA BUS <16>
fR BUS <16>
~
CO
I\)
-...
-8~-rR BUS <7:0>
H
REAOIWRITE
DECODE
o~
RAM AD DR BUFFER
I\)
FOR REGISTERS
MAPPED
IN DATA
SPACE
n
RDF
'i't_
CONTROL OUTPUTS
I
232Xa
I_
PORTS
"
DATA BUS <8>
JL
~
"
l'
0
RBO/CAPt
I
11 8
]
DATA BUS <8>
r-
CDDE
DATA LATCH
JL
II
i
1-
19
WRF
Shifter
lr
LITERAL
DATA RAM
tl4
If' "
DATA LATCH
3 II
~I=~
l'==
IR <2,0,
RB1/CAP2
(EPROM)
RB2/PWMl
AB3JPWM2
2KX 16
~
~
PROGRAM
MEM
ADd5:0>/
PORT C, D
-
R84fTCLK1/2
RB5ITClK3
L8
RB6
RB?
ALE,WR,OE;
PORTE
;>
16
PORTA
@
Q1, Q2, Q3, Q4
ill
(")
I
aSCI, OSC2
RA1IRT
RA2
RA3
RA4/RXlDT
RA5ITX/CK
Interrupt
Module
:T
"6'
C1l
::l
0
0
<0
'<
:J
p
I
__
r---
Control
Signals
to CPU
Chip_reset
& Other Contr?<;::===
Signals
CLOCK GENERATOR
POWER ON RESET
WATCH DOG TIMER
DSC STARTUP TIMER
TEST MODE SELECT
P=
I~
MClRNPP
-I
(")
:::T
F= --
<::::::::::::==
RAO/INT
,
~
TEST
Table of Contents
1.0
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
1.6.1
2.0
2.1
2.2
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
3.8
4.0
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.7
4.8
5.0
5.1
6.0
6.1
6.1.1
6.1.2
6.2
6.2.1
6.3
6.3.1
6.4
6.4.1
6.5
6.5.1
7.0
7.1
7.1.1
Architectural Overview ........................................... 1
PIC17C42 Pinout Description ................................ 5
Internal Clocking Scheme ...................................... 6
Instruction FlowlPipelining ..................................... 7
Memory Organization ............................................. 7
Different Program Memory Organization ............... 7
External Program Memory Interface ...................... 8
Data Memory Organization .................................... 9
Organization of Special Function Registers ........... 9
Instruction Set ...................................................... 11
Special Function Registers as Sourcel ................... .
Destination ........................................................... 13
Instruction Description ......................................... 14
Hardware Description of the CPU ........................ 23
Indirect Addressing Registers (Files OOh
&08h) .................................................................. 23
File Select Registers (FSRO and FSR1,
Files 01 hand 09h) ............................................... 23
Table Pointer (TBLPTRL Files and TBLPTRH, ...... ..
Files ODh and OEh) ............................................. 23
Table Latch (TBLATH, TBLATL) .......................... 23
Program Counter Module ..................................... 23
Stack .................................................................... 23
Stack Available Status Bit (Bit 5, CPUSTA) ......... 24
Using the STKAVL Bil... ....................................... 24
Interrupt Logic ...................................................... 24
Interrupt Flag and Mask Bits ................................ 24
Peripheral Interrupts ............................................ 24
INT and RT External Interrupts .......................... ,.26
ALU ...................................................................... 27
Special Features of the CPU ............................... 28
Reset .................................................................... 28
Oscillator .............................................................. 29
EC: External Clock Input Mode ............................ 29
RC: RC Oscillator Mode ....................................... 29
XT: Crystal Oscillator Mode ................................. 29
LF: Low Frequency Oscillator Mode .................... 29
Oscillator Start-up Timer (OST) ........................... 30
Power-up Timer (PWRT) and Power on
Reset (POR) ........................................................ 30
Sleep Mode .......................................................... 32
Wake-up from SLEEP .......................................... 32
Interrupt/SLEEP Interaction ................................. 33
Minimizing current consumption in SLEEP ............ ..
Mode .................................................................... 33
Watchdog Timer ................................................... 34
WDT as a Regular Timer ..................................... 34
Code Protection and Write Protection .................. 34
Configuration Fuses ............................................. 34
Overview of Peripherals ....................................... 35
The Bank Select Register (BSR, Address .............. .
OFh) ...................................................................... 35
Digital 1/0 Ports .................................................... 36
~rtA ................................................................... ~
Using RA2, RA3 Pins as Output .......................... 37
Summary of Port A Registers .............................. 37
Port B ................................................................... 37
Summary of Port B Registers .............................. 39
Port C ................................................................... 39
Summary of Port C Registers .............................. 39
Port D ................................................................... 40
Summary of Port D Registers ............................. .40
Port E ................................................................... 40
Summary of Port E Registers .............................. 41
Universal Synchronous Asynchronous
Receiver Transmitter (USART) ............................ 41
Asynchronous Mode ............................................ 41
Asynchronous Mode Transmission ..................... .41
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.4.1
7.5
8.0
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
8.4.2
8.4.3
9.0
9.1
9.2
9.3
10.0
10.1
11.0
11.1
11.2
11.3
11.4
11.4.1
11.4.2
11.5
11.6
11.7
11.7.1
11.7.2
11.7.3
11.7.4
12.0
12.1
12.2
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.4
13.0
13.1
13.2
13.3
Asynchronous Mode Reception ........................... 42
Synchronous Mode .............................................. 43
Synchronous Mode Transmission ....................... .43
Synchronous Mode Reception ............................. 44
Synchronous Slave Mode/SLEEP Mode ................ .
Interaction: ........................................................... 45
Baud Rate Generator .......................................... .45
Serial Port Registers ........................................... .48
Summary of Serial Port Registers ........................ 48
Summary of Serial Port Pins ................................ 49
Timer/Counters: Overview ................................... 49
Role of the Timer/Counters ................................. .49
RTCC Module ...................................................... 49
RTCC Operation .................................................. 50
ReadlWrite Consideration for RTCC .................... 50
External Clock Considerations ............................. 51
Summary of RTCC Registers .............................. 52
Timer1 & Timer2 .................................................. 52
Timer1, Timer2 in 8 Bit Mode ............................... 52
Timer1 & Timer2 in 16 Bit Mode .......................... 53
External Clock Input for Timer1, Timer2 .............. 53
Summary of Timer1, Timer2 Registers ................ 56
Timer/Counter 3 ................................................... 56
External Clock Input for Timer3 ........................... 57
Reading/Writing Timer3 ....................................... 57
Summary of Timer3 Registers ............................. 57
Captu re Modu Ie ................................................... 59
One Capture + Timer/Counter3 + Period ................ .
Register Mode ...................................................... 59
Two Capture + Timer/Counter3 Mode ................. 59
Summary of Capture Registers ............................ 60
Pulse Width Modulation (PWM) Outputs ............. 60
Summary of PWM Registers ................................ 62
Development Support .......................................... 62
PICASM-17: PIC17C42 Cross Assembler ........... 62
PICPAK-17™: PIC17C42 Evaluation/
Development/Programmer Kit .............................. 62
PRO MASTERTM Programmer ............................. 62
PICMASTER-17™: High Performance .................. ..
Universal In-Circuit Emulator System .................. 63
Host System Requirements ................................. 63
Emulator System Components ............................ 63
Ordering Development Tools ............................... 65
Application and Technical Support ...................... 65
Programming Support .......................................... 65
Prototype Programming ....................................... 65
Production Volume Programming ........................ 65
Factory Programming .......................................... 65
Distributor Programming Support ........................ 65
Electrical Characteristics ...................................... 66
Absolute Maximum Ratings ................................. 66
DC Characteristics ............................................... 67
AC Characteristics ............................................... 68
AC Characteristics: OSC/Reset/System Bus ....... 68
AC Characteristics: Serial Port ............................ 69
AC Characteristics: 110 Port ................................. 69
AC Characteristics: RTCC and INT ..................... 70
AC Characteristics: Timer1, Timer2,
Timer3, Capture and PWM: ................................. 70
AC Test Load and Timing Conditions .................. 71
Timing Diagrams .................................................. 72
Package Information ............................................ 78
Package Type: 40-Lead Ceramic Cerdip Dual ...... ..
In-Line with Window (.600 mil) ............................. 78
Package Type: 40-Lead Plastic Dual ...................... .
In-Line (.600 mil) .................................................. 79
Package Type: 44-Lead Plastic Leaded ................ ..
Chip Carrier (Square) ........................................... 80
Illi
© 1992 Microchip Technology Inc.
1-171
DS30073B-page 3
13.4
Package Type: 44-Lead Metric Plastic Quad ......... ..
Fine Pitch (MQFP 10x10MM Body 1.6/.05MM
Lead Form) .......................................................... 81
Sales and Support .............................................................. 84
Part Numbers ...................................................................... 84
11.4.1
11.4.2
PICMASTER-17 Development System ................ 64
PICMASTER-17 Development System
Block Diagram ...................................................... 64
11.4.3 Sample Screen Layout for PICMASTER-17 ........ 65
12.3.6.1 Input Level Conditions ................... ,..................... 71
12.3.6.2 Output Level Conditions ....................................... 71
12.3.6.3 Load Conditions ................................................... 71
12.4.1
Timing Diagram - External Program Memory ......... .
Read .................................................................... 72
12.4.2 Timing Diagram - External Program Memory ......... .
Write ..................................................................... 73
12.4.3 Timing Diagram· Interrupt Timing ........... :........... 73
12.4.4 Reset Timing ........................................................ 74
12.4.5 TABLRD Timing ................................................... 74
12.4.6 TABLRD Timing (Consecutive TABLRD ................. .
Instructions) ......................................................... 75
12.4.7 TABLWT Timing ................................................... 75
12.4.8 TABLWT Timing (Consecutive TABLWT ................ .
Instructions) ......................................................... 76
12.4.9 Sleep/Wake-up Through INT (LF, XT Modes) ..... 76
12.4.10 Sleep/Wake-up Through INT (RC Mode) ............. 77
12.4.11 Synchronous Transmission (master/slave) .......... 77
12.4.12 Synchronous Receive (master/slave) .................. 77
12.4.13 I/O Port InpuVOutput Timing (Port A, Port B) ....... 77
Package Type: 40-Lead Ceramic Cerdip
13.1
Dual In-Line with Window (.600 mil) .................... 78
13.2
Package Type: 40-Lead Plastic Dual In-Line .......... .
(.600 mil) .............................................................. 79
13.3
Package Type: 44-Lead Plastic Leaded
Chip Carrier (Square) ........................................... 80
13.4
Package Type: 44-Lead Metric Plastic Quad Fine
Pitch (MQFP 10x10MM Body 1.6/.015MM Lead Form) ...... 81
Table of Figures
A
PIC17C42 Block Diagram ...................................... 2
PIC17C42 Pin-outs ................................................ 5
Internal Clocks ....................................................... 6
Instruction Fetch/Execute Pipeline ......................... 7
Program Memory Map ........................................... 8
Memory Map in Different Modes ............................ 8
External Program Memory Read and
Write Timings ......................................................... 9
1.6.1
Data Memory Map ................................................. 9
1.6.2
Register File Summary (PIC17C42) .................... 10
2.0.1
Instruction Decode Map ....................................... 13
3.7.1.1 Register INTSTA .................................................. 25
3.7.1.2 PIR (Peripheral Interrupt Request)
Register ................................................................ 25
3.7.1.3 PIE (Peripheral Interrupt Enable) Register .......... 26
3.7.3.1 RTCSTA: RTCC Status/Control Register ............ 26
ALUSTA (ALU Status) Register ........................... 27
3.8.1
Simplified Block Diagram of On-Chip Reset ........... .
4.1.1
Circuit ................................................................... 28
Different Oscillator/Clockin Options ..................... 29
4.2.1
Brown Out Protection Circuit ................................ 30
4.4.1
Brown Out Protection Circuit ................................ 30
4.4.2
4.4.3
External Reset Pulse ........................................... 31
Using On-chip POR ............................................. 31
4.4.4
Internal Reset (V DO and MCLR Tied Together) ... 31
4.4.5
Internal Reset (Voo and MCLR Tied Together): ..... .
4.4.6
Slow Voo Rise Time ............................................. 31
OST Start-up Timing Details ................................ 32
4.4.7
4.5.1
CPUSTA Register ................................................ 33
4.8.1
Reading Fuse Location ........................................ 34
6.0.1
I/O Port Read and Write Timing ........................... 36
Port A Block Diagrams ......................................... 37
6.1.1
6.2.1
Port B Block Diagram ........................................... 38
6.2.2
Port B Block Diagram ........................................... 39
6.3.1
Block Diagram of Ports C, D ano E ...................... 40
7.1.1.1 Asynchronous Transmission ................................ 42
7.1.1.2 AsynchronousTransmission (back to back) ......... 42
7.1.2.1 Asynchronous Reception ..................................... 43
7.2.1.1 Synchronous Transmission .................................. 44
7.2.1.2 Synchronous Transmission (through TXEN) ...... .44
7.2.1.3 Synchronous Transmission (Slave) ..................... 44
7.2.2.1 Synchronous Reception (Master Mode, SREN) .. 45
7.2.2.2 Synchronous Master Mode Reception (CREN) ... 46
7.4.1.1 RCSTA: Receive Status & Control Register ....... .48
7.4.1.2 TXSTA: Transmit Status & Control Register ....... .48
8.2.1.1 RTCC Module Block Diagram .............................. 49
8.2.1.2 RTCSTA: RTCC Status/Control Register ............ 50
8.2.2.1 RTCC Timing: Write High or Low Byte ................ 50
8.2.2.2 RTCC Read/Write in Timer Mode ........................ 51
8.2.3.1 RTCC Timing With External Clock ....................... 52
8.3.1.1 Timer1 ITimer2 Block Diagram ............................. 53
8.3.1.2 TMR1, TMR2, TMR3 Timing in Timer Mode ........ 54
8.3.1.3 Timer/Capture/PWM Control Register 1
(TCON1) ............................................................. 55
8.3.3.1 TMR1, TMR2 and TMR3 in External Clock ............. .
Mode .................................................................... 55
8.3.3.2 Timer/Capture/PWM Control Register 2 ................. .
(TCON2) ..............•............................................... 56
8.4.1.1 Timer3/Capture Module Block Diagram ............... 58
10.0.1
Simplified PWM Block Diagram .................... ....... 60
10.0.2 PWM Output ........................................................ 61
B
1.2.1
1.3.1
1.5.1
1.5.2
1.5.1.1
Table of Tables
1.1
1.5.1.2
3.7.1
4.2.1
4.5.1.1
4.8.1
6.1.1
6.2.1
6.5.1
7.3.1
7.3.2
PIC17C42 Pinout Description ................................ 5
Access Time Requirements for External ................. .
Memory .................................................................. 9
Table of Interrupts ................................................ 24
Oscillator Options ................................................. 29
Wake-up and Reset Function Table .................... 33
Configuration Fuses ............................................. 34
Port A Functions .................................................. 36
Port B Functions .................................................. 38
Port E Functions .................................................. 41
Baud Rates for Synchronous Mode .................... .47
Baud Rates for Asynchronous Mode .................. .47
Trademarks:
PIC is a registered trademark of Microchip Technology
Incorporated.
PICMASTER, PICPRO, PICPAK and PRO MASTER are
trademarks of Microchip Technology Incorporated.
IBM PC is a trademark of IBM Corporation.
MS DOS and Microsoft Windows are registered
trademarks of Microsoft Corporation.
))Iil
DS30073B-page 4
1-172
© 1992 Microchip Technology Inc.
FIGURE B: PIC17C42 PIN-OUT
40L DIP PINOUT
voo
44L PLCC PINOUT
ROO/ADS
RD1/AD9
RD2IAD10
RD3/ADll
RD4!AD12
RD5IAD13
RD6IAD14
RD7/AD15
MCLRlVPP
1
RCO/ADO
RC1/ADl
RC2IAD2
RC3IAD3
RC5IAD5
7
RC7/AD7
9
vss
RC4IAD4
RC5IAD5
RCs/AD6
RC7/AD7
Vaa
Va.
RBO/CAPl
RB1/CAP2
RB2IPWMl
RB3IPWM2
RB4ITCLK12
VSS
REO/ALE
RBOICAPl
RE1/0E
RB1/CAP2
RE2IWR
RB2IPWMl
TEST
RB3IPWM2
RAO/INT
RB4fTCLK12
RA1iRT
RB5ITCLK3
RA2
RB6
RA3
RB7
RA4lRXlDT
OSCl
OSC2ICLKOUT -='--_ _--="-"" RA5ITXICK
RD4IAD12
RD5IAD13
RD6IAD14
RD7/AD15
Ma:FiNPI'
PIC17C42
REO/ALE
RE1/OE
RE2iWR
TEST
TEST
RE2iWR
RE110E
REO/ALE
Vss
Vas
MCLRNpp
RD7/AD15
RDs/AD14
RD5IAD13
RD4IAD12
Vss
v..
PIC17C42
RB4ITCLK12
RB3/PWM2
RB2IPWMl
RB1/CAP2
RBO/CAPO
Vas
Vss
RC7/AD7
RCS/AD6
RC5IAD5
RC4IAD4
1.1 PIC17C42 PINOUT DESCRIPTION
Pin Name
Pin
Type
Number
01 Pins
MCLRNpp
I/P
1
DSC1
OSC2/CLKOUT
I
0
1
1
RAO/INT
I
1
RA1IRT
I
1
RA2,RA3
RA4/RXIDT
I/O
I/O
2
1
RA51TX1CK
I/O
1
Pin Function
Master clear (reset) input. This is the active low reset input to the chip. During Programming mode, it is
the programming voltage (Vpp) input.
Oscillator input in crystal/resonator or RC oscillator mode. External clock input in external clock mode.
Oscillator output. Connects to crystal or resonator in crystal oscillator mode. In RC oscillator or external
clock modes OSC2 pin outputs CLKOUT which has one lourth the frequency of OSC1 and denotes the
instruction cycle rate.
Input only port pin (bit 0 of Port A) and also external interrupt input. Interrupt can be configured to be on
positive or negative edge.
Input only port pin (bit 1 of Port A) and also an external interrupt input. Interrupt can be configured to be
on rising or falling edge. It is also the external clock input for the RTCC timer/counter.
High voltage, high current open drain input/output port pins.
Input only port pin (bit 4 of Port A). II the serial port is enabled, in full duplex asynchronous serial
communication mode this is the receive pin. In half duplex synchronous serial communication mode it is
data input (during receive) or data output (during transmit).
Input only port pin (bit 5 01 Port A). II the serial port is enabled, in lull duplex asynchronous serial
communication mode it is the transmit pin. In hall duplex synchronous communication mode, it is shift
clock input (slave mode) or clock output (master mode).
(cont.)
, © 1992 Microchip Technology Inc.
DS30073B-page 5
1-173
Pin Name
Pin Number Pin Function
Type
01 Pins
RBO/CAP1
I/O
1
RB1/CAP2
I/O
1
RB4ITCLK12
I/O
1
RB5ITCLK3
I/O
1
RB6,RB7
RC7/AD7RCa/ADO
I/O
I/O
2
a
RD7/AD15ROO/ADa
I/O
a
REO/ALE
I/O
1
RE1/0E
I/O
1
RE2IWR
I/O
1
I
P
P
1
1
2
TEST
Vee
Vss
Port pin configurable as input or output in software, with Schmitt trigger input (bit a of Port B).ltis also the capture1
input pin.
Port pin configurable as inputoroutputin software, with Schmitt trigger input (bit 1of Port B).ltis alsothecapture2
input pin.
Port pin configurable as input or output in software, with Schmitt trigger input (bit 4 of Port B).lt is also the external
clock input to timer1 and timer2.
Port pin configurable as input or output in software, with Schinitttrigger input (bit 5, of Port B). II is also the external
clock input to timer3.
Port pins configurable as input or output in software, with Schmitt trigger input (bits 6 and 7 of Port B).
Eight bit wide Port Cwith each pin software configurable as input or output. Input is TTL
compatible (and not CMOS Schmitt trigger type).
This is also the lower halfolthe 16 bit wide system bus in microprocessor mode or extended microcontroller mode.
In multiplexed system bus configuration, these pins are address output as well as data input or output.
Eight bit wide Port 0 with each pin software configurable as input or output. Input is TTL
compatible (and not CMOS Schmitt trigger type).
This is also the upper byte of the 16 bit system bus in microprocessor mode or extended microprocessor mode
or extended microcontroller mode. In multiplexed system bus configuration these pins are address outputas well
as data input or output.
Port pin configurable as input or output in software, with TTL compatible input (bit 0 of Port E).
In microprocessor mode or extended microcomputer mode, it is the Address Latch Enable (ALE) output. Address
should be latched on the falling edge of ALE output.
Port pin configurable as input or output in software, with TTL compatible input (bit 1 of Port E).
In microprocessor or extended microcontroller mode, it is the Output Enable (DE) control output (active low).
Port pin configurable as input or output in software, with TTL compatible input (bit 2 of Port E).
In microprocessor or extended microcontroller mode, it is the Write Enable (iNR) control output (active low).
Test mode selection control input. Always tie to Vss for normal operation.
Power
Ground. Both pins must be connected to system ground.
Legend: I = Input only; 0 = Output only; I/O = Input/output; P = Power.
1.2 INTERNAL CLOCKING SCHEME
the OSC2 pin provides a clock output, CLKOUT, which
is high during 03, 04 and low during 01, 02.
Internally, the clock input to OSC1 pin is divided by four
to generate four phases (01, 02, 03 and 04) each with
a frequency equal to fosc /4 and duty cycle of 25%. If
EC (external clock) or RC oscillator mode is selected,
As long as internal chip reset is active; the clock generator holds the chip in 01 state. The CLKOUT pin is driven
low (EC, RC mode).
FIGURE 1,2.1: INTERNAL CLOCKS
01
02
Q3
01
Q4
02
03
Q4
asel
I
01
(
Q2
03
II
I
I
I
I
~
Q4
I
~~~'2'~~: ~
~
I
I
© 1992 Microchip Technology Inc.
DS30073B-page 6
1-174
1.3 INSTRUCTION FLOW/PIPELINING
create data segments in external program memory, use
TABLWT and TABLRD instructions to move data between external program memory and the register file.
An "Instruction Cycle" in PIC17C42 consists of 01, 02,
03 and 04. Instruction fetch and execute are pipelined
such that fetch takes one instruction cycle while decode
and execute takes another instruction cycle. However,
due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program
counter to change (e.g. GOTO) then two cycles are
required to complete the instruction. Additionally, there
are two instructions, TABLRD and TABLWT which take
two or more cycles to complete. These are explained in
more details 'Instruction Set' description.
The program memory is 16 bits wide. It is addressed by
the 16 bit program counter for instruction fetch. It is also
addressed by the table pointer register (TBLPTR, also
16 bit wide) for data move to and from data space.
Addressable program memory is 64K x 16. The
PIC17C42 incorporates 2K x 16 EPROM program
memory on chip.
1.5 DIFFERENT PROGRAM MEMORY
ORGANIZATION
A fetch cycle begins with the program counter (PC)
incrementing in 01. In external execution, the address is
presented on pins AD15 - ADO during 02. The instruction is latched on the falling edge of 04.
The PIC17C42 operates in on of four possible program
memory configurations which are:
The fetched instruction is latched into the "Instruction
Register (IR)" which is decoded in 01 and executed
during 02, 03 and 04. Data memory is read during 02
(operand read), ALU operations are done in 03 and
result is written back during 04 (destination write).
Microcontroller Mode: In this mode, only internal execution is allowed and therefore, only the on-chip 2K program memory is available. Any access to program
memory beyond 2K reads OOOOh (which is NaP). In
addition to program memory, fuses, test memory, and
boot memory (FEOOh to FFFFh) are accessible.
FIGURE 1.3.1: INSTRUCTION FETCH/
EXECUTE PIPELINE
Protected Microcontroller Mode: It is the same as microcontroller mode except that code protection is enabled.
Refer to section 4.7 for details on code protection.
Extended Microcontroller Mode: In this mode, on chip
program memory (O-2K) as well as external memory (2K
- 64K) are available. Execution automatically switches
to external if program memory address is greater than
07FFh. The fuses, test memory and the boot memory
are not accessible in this mode.
1~IQ2Iml~I~I~IQ3IQ41~IQ2Iml~1
pc
K~~pc~~iX~_ _~IX,---_PC_.2~
I
I
I
AD <15:0>
e
NST (PC+1)
Microprocessor Mode: In this mode the on-chip program
memory is not used. The entire 64K program memory is
mapped externally. The fuses, test memory and the
boot memory are not accessible in this mode.
OE
K
IR
INST(PC·1)
(Instruction ~-----'
register) I
INST(PC)
INST(PC+1)
~-----'
'-----
l
I
Execute INST (PC-1)
I
I
I
Fetch INST (PC)
Felch INST (PC+l)
FPMMO: FE04h
I
I
Execute INST (PC)
I
The different modes are selected by fuses FPMMO and
FPMM1. These fuses are mapped in the following program memory locations:
Execute INST (PC+ 1)
Fetch INST (PC+2)
FPMM1: FE06h
I
I
FPMMO FPMM1
1.4 MEMORY ORGANIZATION
Mode
0
0
Microcontrolier Mode (Code Protected)
0
1
Microcontroller Mode (Unprotected)
1
1
0
Extended Microcontrolier Mode
1
Microprocessor Mode
= fuse unprogrammed or erased,
o = fuse programmed.
Note: • 1
The PIC17C42 employs a Harvard architecture, i.e. it
has separate program and data mernory space. In
addition, there is a hardware stack separate from both
data and program space. The data space is 256 bytes in
size. Most of the data space is implemented as static
RAM (address 18h to FFh). Special function registers,
implemented as individual hardware registers make up
the rest of the data space. Refer to section 1.6 for more
details. Data memory "address" and "data" buses are
not brought outside the chip. So the data memory can
not be expanded externally. The user can, however,
Refer to section 4.7 for information on code protection.
Test Memory Boot Memory and Fuse Locations: Test
memory space is used by the factory for testing purposes. The 'boot ROM' area holds programs used for
programming and verification. The user need not be
concerned about either of these. The fuse locations map
configuration fuses used to select from various operating modes. The fuses are explained in detail, in section
4.8.
© 1992 Microchip Technology Inc.
DS30073B-page 7
1-175
1.5.1 External Program Memory interface
FIGURE 1.5.1: PROGRAM MEMORY MAP
DODO
0027
0028
I~I\
Reset Vector
If external execution is selected, ports C, D and E are
configured as a system bus for external program memory
access. Ports D and C, together, constitute a 16 bit wide
multiplexed address and data bus. The three bit E Rort
outputs control signals ALE (Address Latch Enable), OE
(Output Enable) and WR (Write Enable). An external
memory access cycle is comprised of four oscillator
cycles (from 01 rising edge to 01 rising edge). During
02, a 16 bit address is presented on ports C and D (RD?
= MSB, RCO =LSB) and ALE is asserted. The address
output should be latched by the falling edge of ALE. In an
instruction fetch or data read cycle, the OE is asserted
du~ 03 and 04. The data is latched on the rising edge
of OE. One oscillator cycle separation between OE l'
and address output guarantees adequate time for external memories to shut off their output drivers before
address is driven on to the bus.
0000
INT Pin Interrupt Vector
0008
RICC Timer Interrupt Vector
0010
RT Pin Interrupt Vector
0018
Penpherallnterrupt Vector
0020
0027
-__
~---~F~cisco
FEOD
FEOF
----=~-
~OSC1
Fuses
FWDTO
FWDTl
FPMMO
FE03
Reserved
FEOS
FE10
FF5F
FF60
FFFF
FEOD
FE01
Test EPROM
Boot ROM
FE02
In a data write cycle (only during TABLWT instruction),
following address output during 02, data is driven onto
the bus during 03 and Q4. WR is asserted during 04 and
the data output is valid both on its falling and rising edge.
FE04
FPMMl
FE06
FE07
FEOS
Figure 1.5.1.1 depicts read and write cycles and table
1.5.1.1 shows access time required of the external
Reserved
I
memory components. For complete timing information
on the system bus, refer to AC characteristics section.
FEOF
FIGURE 1.5.2: MEMORY MAP IN DIFFERENT MODES
Extended
Microcontroller
Mode
Microprocessor
Mode
0000
Microcontroller
Mode
0000
0000
On Chip
EPROM
Program
Memory
07FF
0800
07FF
0800
On Chip
EPROM
Program
Memory
UJ
t.)
«
a..
External
Program
(/)
Memory
:2
External
Program
Memory
«
c::
whose contents are
updated from or transfered to the upper byte of the program counter.
2: The "TO" and PD·' status bits in f06h are not affected by a "MCLR" reset. TO bit will be reset in the event of a WOT time-out
reset.
3: Other (non power-up) resets include external reset through MCLR pin and watchdog timer timeout reset.
OS30073B-page 10
© 1992 Microchip Technology Inc.
1-178
Any unused op-code is executed as a NOP.
2.0 INSTRUCTION SET
The instruction set is highly orthogonal and is grouped
into
The PIC17C42 instruction set consists of 55 instructions, each single word and 16 bit wide. Most instructions
operate on a file register f and the working register W
(accumulator). Depending on the instruction, the result
may be directed to the file register, or the working
register (W) or to both.
Data Move Operations
Arithmetic and Logical Operations
Bit Manipulation Operations
Program Control Operations
All instructions are executed in a single instruction cycle
unless otherwise noted.
Special Control Operations
Data Move Instructions
Instruction Code
Binary
011p
1011
OlOp
0000
1010
pppp
1000
pppp
0001
lOti
Hex
ffff ffff
kkkk kkkk
ffff ffff
ffff ffff
ffff ffff
6pff
B8kk
4pff
aUf
ASff
mnemonic
MOVFP
MOVLB
MOVPF
MOVWF
TABLRD
Description
f,p
k
p,f
f
t,i,f
Function
Movef to p
Move literal to BSR
Move ptof
Move Wtof
Read data from table latch
into file f, then update table
latch with 16·bit contents of
memory location addressed
1010 llti f f f f f f f f
ACf£
TABLWT
t,i,f
1010 OOtx ffff ffff
AOff
TLRD
t,f
1010 Oltx ffff ffff
A4ff
TLWT
t,f
f -> P
k -> BSR
p -> f
W->f
TBLATH -> f if t =1,
TBLATL -> f if t =0;
Prog Mem (TBLPTR) -> TBLAT;
TBLPTR + 1 -> TBLPTR if i =1;
by the table pointer.
Write data from file f to table
f -> TBLATH if t =1,
latch and then Write 16·bit
f ->TBLATL if t =0;
TBLAT -> Prog Mem (TBLPTR);
table latch to program memory
TBLPTR + 1 -> TBLPTR if i =1
location addressed by table
pointer. It also intitiates
programming if on·chip EPROM
Status bits
Affected
None
Notes
4
None
Z
4
None
None
8,10
None
6
program memory is addressed.
Read data from table latch
into file f (table latch unchanged).
Write data from file f into
table latch.
TBLATH -> f if t =1,
TBLATL -> f if t =0
f -> TBLATH if t =1,
f ->TBLATL if t =0
None
None
Arithmetic and Logical Instructions
Instruction Code
Binary
1011
0000
0001
1011
0000
0010
0001
0010
0000
0001
1011
0000
1011
0010
0001
0010
0001
0010
0010
1011
0000
0000
0001
1011
0000
0001
111d
OOOd
0101
101d
100d
001d
111d
011d
DIOd
0011
100d
0000
110d
101d
001d
100d
DODd
101d
0010
010d
aOld
110d
0100
110d
kkkk
ffff
ffff
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
ffff
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
ffff
ffff
ffff
kkkk
ffff
kkkk
ffff
ffff
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
ffff
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
ffff
ffff
ffff
kkkk
ffff
Hex
mnemonic
Blkk
DEtf
10ff
B5kk
OAff
28ff
12ff
2Eff
06ff
14f£
s3kk
08ff
BOkk
2eff
1Aff
22ff
18ff
20f£
2Aff
B2kk
04ff
02££
leff
B4kk
oeff
ADDLW
ADDWF
ADDWFC
ANDLW
ANDWF
CLRF
COMF
DAW
DECF
INCF
IORLW
IORWF
MOVLW
NEGW
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBLW
SUBWF
SUBWFB
SWAPF
XORLW
XORWF
Description
k
f,d
f,d
k
f,d
f,d
f,d
f,d
f,d
f,d
k
f,d
k
f,d
f,d
f,d
f,d
f,d
f,d
k
f,d
f,d
f,d
k
f,d
FUnction
Add literal to W
ADDWto f
ADD Wand Carry to f
AND literal and W
ANDWwithf
Clear f and Clear d
Complement f
Dec. adjust W, store in f,d
Decrement f
Incrementf
Inclusive OR literal with W
Inclusive OR W with f
Move literal to W
Negate W, store in f and d
Rotate left through Carry
Rotate left (no Carry )
Rotate right through Carry
Rotate right ( no Carry )
Set f and Set d
Subtract W from literal
Subtract W from f
Subtract W from f with borrow
Swapf
Exclusive OR literal with W
Exclusive OR W with f
© 1992 Microchip Technology Inc.
Status bits
Affected
OV C DC Z
( W+k) -> W
(W+f) ->d
OVCDCZ
(W+f+C) -> d
OV C DC Z
(W.AND.k) -> W
Z
(W.AND.f) -> d
Z
"OOh" -> f, "OOh" -> d
None
T->d
Z
W adjusted -> f and d
C
(f·1)-> d
OV C DC Z
(f+ 1) -> d
OV C DC Z
(W.OR.k) -> W
Z
(W.OR.f) -> d
Z
k -> W
None
(W+1) -> f, iW+1) ->d
OV C DC Z
kn>--7d, k7>--7C, C-)d
C
kn>--7 d, k 7>--7 d
None
kn>--7d, kO>--7C, C--7d<7>
C
kn>--7 d, kO>--7 d<7>
None
"FFh" -> f, "FFh"-> d
None
OV C DC Z
( k·W) -> W
OV C DC Z
(f·W) -> d
(f·W·c)-> d
OV C DC Z
kO:3> --7 d<4:7>, k4:7> --7 d <0:3>
None
(W.XOR.k) -> W
Z
(W.XOR.f) -> d
Z
Notes
3
3
1,3
I
DS30073B-page 11
1-179
Proaram
control
nstructlons
Instruction Code
Binary
Hex
mnemonic
Description
11lk kkkk kkkk kkkk
Ekkk
CALL
k
Subroutine call
(within 8K page boundary)
0011
0011
0011
0001
0010
1l0k
kkkk kkkk kkkk
31ff
32ff
30ff
16ff
26ff
Ckkk
CPFSEQ
CPFSGT
CPFSLT
DECFSZ
DCFSNZ
GOTO
f
f
f
f,d
f,d
k
0001 111d f f f f f f f f
0010 DIOd f f f f f f f f
1011 0111 kkkk kkkk
lEft
24f£
B7kk
INCFSZ
INFSNZ
LCALL
f,d
f,d
k
0000 0000 0000 0101
0005
RETFIE
1011 0110 kkkk kkkk
B6kk
RETLW
k
Compare f/W skip if f=W
Compare f/W skip if bW
Compare f/W skip if kW
Decrement f, skip if a
Decrement f skip if not a
Unconditional branch
(within 8K page boundary)
Increment f skip if a
Increment f skip if not a
Long Call
(anywhere in 64K range)
Return from interrupt
and enable interrupt
Return literal to W
0000 0000 0000 0010
0002
0011 0011 f f f f f f f f
33ff
RETURN
TSTFSZ
f
Return from subroutine
Test f skip if a
0001 ffff ffff
0010 f f f f f f f f
0000 ffff ffff
DUd ffff ffff
Qild f f f f ffff
Status bits
Affected
Function
None
PC+1 -> TOS, k -> PC<12:0>;
k<12:8> -> f3<4:0>,
PC<15:13> -> f3<7:5>
f - W, skip if f = W
None
f - W, skip if f> W
None
None
f-W, skip if f d, skip if result =0
(f-1) -> d, skip if not a
None
k .... PC<12:0>, k<12:8> .... f3<4:0>,
None
PC<15:13> .... f3 <7:5>
None
(f+ 1) -> d, skip if result a
None
(f+ 1) .... d, skip if not a
(PC+ 1) .... TOS;
None
(f3) .... PCH; k .... PCL
TOS .... PC (f3 unchanged)
GLlNTD
"0" -> GLlNTD
None
k .... W, TOS .... PC,
f3 unchanged
TOS .... PC (f3 unchanged)
None
None
skip if f = a
Notes
8
7
2,7
2,7
7
7
8
7
7
5,8
8
8
8
7
Bit Handling Instructions
Instruction Code
Binary
1000
1000
1001
1001
0011
1bbb ffff ffff
Gbbb
Ibbb
Obbb
Ibbb
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
Hex
mnemonic
Sbff
Sbff
9bff
9bff
3bff
BCF
BSF
BTFSC
BTFSS
BTG
Description
f,b
f,b
f,b
f,b
f,b
Status bits
Affected
Function
Bitclearf
Bit set f
Bit test, -skip if clear
Bit test, skip if set
Bit Toggle f
None
None
None
None
None
0 .... fib)
1 .... fib)
skip if fib) = a
skip if fib) = 1
f(b) .... fib)
Notes
4
4
4,7
4,7
4
siPecial control instructions
Instruction Code
Binary
Hex
mnemonic
0000 0000 0000 0100
0004
CLRWDT
Clear watch dog timer
0000 0000 0000 0000
0000 0000 0000 0011
0000
0003
NOP
SLEEP
No operation
Enter "sleep" mode
Description
Status bits
Affected
Function
a .... WDT, a .... WDT prescaler,
1 -> PD, 1 -> TO
None
Stop osciUator,"power down"
0 .... I,'YDT, a -=-..WDT prescaler,
1 -> TO, 1 -> PO
Notes
PD,TO
None
PD,TO
-
Legend:
Notes:
register file address ( OOh to FFh )
P
b
1)
2)
3)
peripheral register file address (OOh to 1Fh)
bit address with in 8 bit file register
table pointer control i = 0: do not change
i = 1: increment after instruction execution
table byte select t = 0: perform operation on lower byte
t = 1: pertorm operation on upper byte
literal field (constant data)
d
5)
don't care
destination select; d=O store result in W (faA)
TO,PD
d=1 store result in file register 'f'
ALU status bits Carry, Digit Carry, Zero, Overtlow
CPU status bits Time-out and Power-down
GLlNTD
GLobal Interrupt Disable bit (bit 4, CPUSTA)
W
W-register
C,DC,Z,OV
4)
PC
Program counter
TBLPTR
Table Pointer (16 bit)
TBLAT
Table Latch (16 bit) consists of high byte
TBLATL
Table latch low byte
TBLATH
Table latch high byte
WDT
Watchdog timer
6)
7)
8)
9)
10)
(TBLATH) and low byte (TBLATL)
BSR
Bank Select Register
TOS
Top of Stack
DS30073B-page12
2's Complement method.
Unsigned arithmetic
If d=1, only the file is affected; If d=O, both Wand the file are
affected; If only W is required to be affected, then f=OAh (File
OAh) must be defined.
The HEX representation is not accurate. The value of the bit to
be modified has to be incorporated into the third digit.
During an LCALL, the contents of file 03h are loaded into the
MSB of the PC and kkkk kkkk is loaded into file 02h the LSB of
the PC.
Multiple cycle instruction for EPROM programming when table
pointer selects internal EPROM. The instruction is terminated
by an interrupt event.
When writing to, external program memory, it is a two cycle
instruction.
Two cycle instructions when condition is true, else single cycle
instruction.
Two cycle instruction except for TABLRD to f02h (Program
Counter low byte) in which case it takes 3 cycles.
A 'skip' means that instruction fetched during execution of
current instruction is not executed. Instead a 'NOP' is executed.
Any instruction that writes to PCL (102) is a two cycle
instruction,
execpt for TABLRD to 102 is a 3 cycle instruction.
© 1992 Microchip Technology Inc.
1-180
FIGURE 2.0.1: INSTRUCTION DECODE MAP
OPCODE<11:8>
~
~
Ui
V
w
o
oo
"o
MOVPF
MOVFP
0001:
0002:
0003:
0004:
0005:
0006:
unused
RETURN
SLEEP
CLRWDT
RETFIE
DOFF unused
unused opcode (execute as NOP)
2.1
PCl as source or destination (file 02h): Read, write or
read-modify-write on PCl (f02) have the following results:
SPECIAL FUNCTION REGISTERS
AS SOURCE/DESTINATION
PIC17C42's orthogonal instruction set allows read and
write of all file registers, including special function registers such as PC and status registers. There are some
special situations the user should be aware of:
AlUSTA as destination (file 04h): If an instruction writes
to AlUSTA, the Z, C, DC and OV bits may be set or reset
as a result of the instruction and overwrite the original
data bits written. For example, executing ClRF 04 will
clear register 04, and then set Z bit leaving 000001 OOb
first in the register.
Read PCl (f02):
PCH
Write PCl (f02):
PClATH -7 PCH;
8 bit destination value
Read-Modify-Write:
PCl -7 AlU operand
PClATH -7 PCH;
8 bit result -7 PCl
-7
PClATH; PCl
-7
-7
d
PCl
Where PCH = program counter high byte (not a addressable register), PClATH = Program counter high holding latch (file f03), d = destination, W or f.
Bit Manipulation
All bit manipulation instructions are done by first reading
the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
© 1992 Microchip Technology Inc.
DS30073B-page 13
1-181
2.2 INSTRUCTION DESCRIPTION
ANDWF
ADDLW
Syntax:
Add literal to W
Syntax:
Encoding:
ADDLW
11011
I
Encoding:
k
0001
I kkkk
kkkk
I
Words:
Cycles:
Operation:
(W + k) -> W
Status bits:
OV, C, DC, Z
Description:
The contents 01 the W register are added
to the eight bit literal "k" and the result is
placed in the W register.
ADDWF
ADDWtof
Syntax:
ADDWF
Encoding:
0000
I
ffff
ffff
I
Words:
Cycles:
I,d
0000
laId
Words:
1
Cycles:
1
I
I
ffff
ffff
I
Operation:
(W .AND. I) -> d
Status bits:
Z
Description:
AND the W register with data memory
location "I". II "d" is 0 the result is stored
in the W register. II "d" is 1 the result is
stored in data memory location "I".
BCF
Bit Clear f
Encoding:
I
ANDWF
I
BCF
Syntax:
I,d
111d
I
AND Wwith f
1000
I
Words:
1
Cycles:
1
I,b
I
1bbb
I
ffff
ffff
I
Operation:
o -> I(b)
Operation:
(W + f) -> d
Status bits:
None
Status bits:
OV, C, DC, Z
Description:
Description:
Add the contents 01 the W register to data
memory location "I". II "d" is 0 the result
is stored in the W register. II "d" is 1 the
result is stored in data memory location
Bit "b" in data memory location "I" is reset
to O.
BSF
Bit Set f
"I".
ADDWFC
ADD W and Carry to f
Syntax:
Encoding:
Words:
ADDWFC
0001
I
I
ffff
ffff
I
1
(W + I + C) -> d
Status bits:
OV, C, DC, Z
Description:
Add the W register and the Carry Flag to
data memory location "I". II "d" is 0 the
result is placed in the W register. If "d" is
1 the result is placed in data memory
location "I".
ANDLW
11011
ffff
I
k
I 0101 I kkkk
Operation:
1 -> I(b)
Status bits:
None
Description:
Bit "b" in data memory location "I" is set to
BTFSC
AND literal and W
Encoding:
I,b
I Obbb I ffff
1.
Operation:
Syntax:
11000
Cycles:
I
Cycles:
ANDLW
BSF
Encoding:
Words:
I,d
OOOd
Syntax:
kkkk
I
Bit test. skip if clear
Syntax:
rB_T_F_S_C,----...:1,_b_.---_ _.--_---,
Encoding:
11001
Words:
1
I
1bbb
Cycles:
1(2)
Operation:
skip if f(b) = 0
I ffff
ffff
Status bits:
None
Description:
If bit "b" in data memory location "I" is "0"
then the next instruction is skipped.
Words:
Cycles:
1
Operation:
(W .AND. k) -> W
Status bits:
Z
Description:
The contents 01 W register are AND'ed
with the eight bit literal "k". The result is
placed in the W register.
If bit "b" is "0", the next instruction,
fetched during the current instruction execution, is discarded and a NOP is executed instead making this a 2 cycle
instruction.
DS30073B-page 14
© 1992 Microchip Technology Inc.
1-182
BTFSS
Bit test. skip if set
Operation:
OOh -7 f, OOh -7 d
Syntax:
BTFSS
Status bits:
None
Encoding:
11001 1Obbb 1ffff
Description:
Words:
1
The contents of data memory location "f"
are set to o. If "d" is 0 the contents of both
data memory location "f" and W register
are setto O. If "d" is 1 the only contents of
data memory location "f" are set to O.
CLRWDT
Clear Watchdog Timer
f,b
ffff
1
Cycles:
1 (2)
Operation:
skip if f(b)
Status bits:
None
Description:
If bit "b" in data memory location "f" is "1"
then the next instruction is skipped.
Syntax:
CLRWDT
Encoding:
10000 10000 10000 11000
If bit "'b" is "1 ", the next instruction, fetched
during the current instruction execution,
is discarded and a NOP is executed instead making this a 2 cycle instruction.
Words:
1
Operation:
Bit Toggle f
Status bits:
1 -7 TO, 1 -7 PD
Description:
CLRWDT instruction-resets.tAe watchdog timer.lt also resets the prescaler of
the WDT. Status bits TO and PD are set.
COMF
Complement f
Syntax:
COMF
Encoding:
10001 1OOld 1ffff
BTG
Syntax:
Encoding:
=1
BTG
Cycles:
f,b
10011 lbbb 1 ffff
ffff
OOh -7WDT, 0 -7 WDT prescaler,
Words:
Cycles:
Operation:
f(b) -7 f(b)
Status bits:
None
Description:
Bit "b" in data memory location "f" is
inverted.
f,d
ffff
Words:
Cycles:
CALL
Subroutine Call
Syntax:
CALL
Encoding:
Illlk
k
1
kkkk
kkkk
kkkk
Words:
1
Cycles:
2
Operation:
PC + 1 -7 TOS, k -7 PC<12:0>,
k<12:B> -7 PCLATH<4:0>;
PC<15:13> -7PCLATH<7:5>
Status bits:
Description:
CLRF
Syntax:
Encoding:
Subroutine call within BK page. First, return address (PC + 1) is pushed into the
stack. The thirteen bit value is loaded into
PC bits <12:0>. Then the upper eight bits
of the PC is copied into PC LATH (f03).
CALL is a two cycle instruction.
Clear f and Clear d
f,d
10010 1100d
I
ffff
f -7 d
Status bits:
Z
Description:
The contents of data memory location "f"
are complemented. If "d" is 0 the result is
stored in W. If "d" is 1 the result is stored
in data memory location "I".
CPFSEQ
Compare f with W, skip if f = W
1
None
CLRF
Operation:
1 ffff
Syntax:
,.:.C..:..P..:..F..:-S..:..E-rQ'---'f_,--_ _.--_--.
Encoding:
10011 10001 1ffff 1 ffff
Words:
1
"I
Cycles:
1 (2)
Operation:
f - W, skip if f = W
Status bits:
None
Description:
lithe contents of data memory location '1"
are equal to the contents of the W register, the next instruction is skipped.
If f = W then the next instruction, fetched
during the current instruction execution,
is discarded and a NOP is executed instead making this a 2 cycle instruction.
Words:
Cycles:
::'(Ii
© 1992 Microchip Technology Inc.
1-183
DS30073B-page 15
CPFSGT
Compare f with W, skip if f > W
Syntax:
CPFSGT
Encoding:
I 0011 I 0010
Words:
1
BCD result. If "d" is 0 the result is placed
in the W register and data memory location "f". II "d" is 1 the result is placed only
in data memory location "f".
f
ffff
I
ffff
The Decimal Adjust Algorithm is as follows:
Cycles:
1 (2)
Operation:
f - W, skip if f > W (unsigned comparison)
Status bits:
None
Description:
If the contents of data memory location "f"
are greater than the contents of the W
register, the next instruction is skipped.
The subtraction is unsigned.
S1lmi
W.
~
If f > W then the next instruction, fetched
during the current instruction execution,
is discarded. A NOP is executed instead
making this a 2 cycle instruction.
CPFSLT
Compare f with W, skip if f< W
Syntax:
CPFSLT
f
Encoding:
I 0011 I
0000
I
ffff
I
ffff
Words:
1
Cycles:
1 (2)
Operation:
f - W, skip if f < W (unsigned)
None
Description:
If the contents of data memory location "f"
are less than the contents of the W register, the next instruction is skipped. The
subtraction is unsigned.
If f < W then the next instruction, fetched
during the current instruction execution,
is discarded. A NOP is executed instead
making this a 2 cycle instruction.
DAW
Decimal Adjust W Register
Syntax:
DAW
f,d
Encoding:
I 0010
llld
If upper nibble is greater then 9
or if C flag (Carry) is set following Step 1 operation, 60h is
added to W
The Carry Ilag may be set as a
result of Step 1 or Step 2 operation.
I
Status bits:
If the lower nibble of W is greater
then 9 or if the DC flag (Digit
Carry) is set from previous operations, then 06h is added to
DECF
Decrement f
Syntax:
DECF
Encoding:
I 0000 I
Words:
1
f,d
Olld
I
I ffff I
ffff
Cycles:
1
Operation:
(1-1) --> d
Status bits:
OV, C, DC, Z
Description:
Decrement data memory location "I". II
"d" is 0 the result is stored in the W
register. If "d" is 1 the result is stored in
data memory location "f".
DECFSZ
Decrement f, skip if 0
Syntax:
DECFSZ
Encoding:
I 0001 I Olld I
I,d
ffff
I
ffff
I
Words:
I ffff I
ffff
I
Words:
Cycles:
1 (2)
Operation:
(f - 1) --> d; skip if result
Status bits:
None
Description:
~
0
Cycles:
1
Operation:
if [W<3:0> >9].OR. [DC ~ 1]
then W<3:0> + 6 --> 1<3:0>, d<3:0>;
if [W<7:4> >9] .OR. [C ~ 1] then
W<7:4> + 6 --> 1<7:4>, d<7:4>;
Status bits:
C
The contents of data memory location "f"
are decremented. If "d" is 0 the result is
placed in the W register. If "d" is 1 the
result is placed in data memory location
"I". II the result is 0 the next instruction is
skipped.
Description:
DAW adjusts the eight bit value in the W
register resulting from the earlier addition
of two variables (each in packed BCD
format) and produces a correct packed
II the result is 0, the next instruction,
which is already letched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
DS30073B-page 16
© 1992 Microchip Technology Inc.
1-184
DCFSNZ
Decrement f, skip if not 0
INCFSZ
Increment f, skip if 0
Syntax:
DCFSNZ
Syntax:
INCFSZ
Encoding:
I 0001 I
Encoding:
I 0010
f,d
I Olld I ffff
I ffff
I
Words:
f,d
llld
I ffff
ffff
I
Words:
Cycles:
1 (2)
Cycles:
1 (2)
Operation:
(f-1) ---7 d, skip if not 0
Operation:
(f+ 1) ---7 d, skip if result = 0
Status bits:
None
Status bits:
None
Description:
The contents of data memory location "f"
are decremented. If "d" is 0 the result is
placed in the W register. If "d" is 1 the
result is placed in data memory location
Description:
The contents of data memory location "f"
are incremented. If "d" is 0 the result is
placed in the W register.
If "d" is 1 the result is placed in data
memory location "f". If the result is 0 the
next instruction is skipped. If the result is
the next instruction, fetched during the
current instruction execution, is discarded.
A NOP is executed instead making this
the 2 cycle case.
"f".
If the result is not 0, the next instruction,
fetched during the current instruction execution is discarded. A NOP is executed
instead making this a 2 cycle instruction.
GOTO
Unconditional Branch
Syntax:
Encoding:
GOTO
o
k
I'---ll-O-k---'-I-k-k-k-k--'I-k-k-kk--'I-k-kk-k--'
Words:
INFSNZ
Increment f, skip if not 0
Syntax:
INFSNZ
f,d
Encoding:
I 0010 I
010d
I ffff I ffff
Words:
Cycles:
2
Operation:
k ---7 PC<12:0>; k<12:S> ---7 f3<4:0>,
PC<15:13> ---7 f3<7:5>
Cycles:
1(2)
Operation:
(1+1) ---7 d, skip if not 0
Status bits:
None
Status bits:
None
Description:
GOTO allows an unconditional branch
anywhere within an SK page boundary.
Thethirteen bit immediate value is loaded
into PC bits <12:0>. Then the upper eight
bits of PC are loaded into PCLATH (file 3).
GOTO is always a two cycle instruction.
Description:
The contents of data memory location "f"
are incremented. If "d" is 0 the result is
placed in the W register.
INCF
If "d" is 1 the result is placed in data
memory location "f". If the result is not 0
the next instruction, fetched during the
current instruction execution, isdiscarded.
A NOP is executed instead making this a
2 cycle instruction.
Increment f
Syntax:
INCF
Encoding:
I 0001
f,d
I 010d
ffff
I
ffff
I
Words:
Cycles:
Operation:
(f + 1) ---7 d
Status bits:
OV, C, DC, Z
Description:
The contents of data memory location "f"
are incremented. If "d" is 0 the result is
placed in the W register. If "d" is 1 the
result is place in data memory location "f".
IORLW
Inclusive OR literal with W
Syntax:
IORLW
Encoding:
11011
k
I
0011
kkkk
I
kkkk
I
Words:
Cycles:
© 1992 Microchip Technology Inc.
1
Operation:
(W .OR. k)---7W
Status bits:
Z
Description:
The contents of the W register are inclusively OR'ed with the eight bit literal "k".
The result is placed in the W register.
DS30073B-page 17
1-185
IORWF
MOVFP is particularly uselul to transler a
data memory location to a peripheral register (such as the transmit buffer or an I/O
port). Both "I" and "p" can be indirectly
addressed.
Inclusive OR W with f
Syntax:
10RWF
Encoding:
I 0000
I,d
Words:
1
Cycles:
1
MOVLB
Move Literal to BSR
Operation:
(W .OR. I) --> d
Syntax:
MOVLB
Status bits:
Z
Encoding:
1 1011
Description:
Inclusive OR the W register with data
memory location "I". If "d" is 0 the result
is stored in the W register. If "d" is 1 the
result is stored in data memory location
"f".
Words:
lOad
LCALL
Long Call
Syntax:
LCALL
Encoding:
11011
ffff
I ffff I
0111
kkkk
kkkk
2
Operation:
PC+ 1 --> TOS;
k --> PCL, (PCLATH) --> PCH
Status bits:
None
Description:
LCALL allows unconditional subroutine
call to anywhere within the 64k program
memory space. First, the return address
(PC+ 1) is pushed onto the stack. A 16 bit
destination address is then loaded into
the program counter. The lower 8 bit 01
the destination address is embedded in
the instruction. The upper 8 bit of PC is
loaded Irom PC high holding latch,
PCLATH. LCALL is a two cycle instruction.
Example:
MOVLW
MOVPF
LCALL
kkkk
kkkk
I
Operation:
k --> BSR
Status bits:
None
Description:
The constant is loaded in Bank Select
Register (BSR, OFh). Only the low 4 bits
of the Bank Select Register are physically
implemented.
MOVLW
Move Literal to W
Syntax:
Encoding:
rl-10-1-1-'--0-0O-O--rl-k-kk-k--r-k-k-kk--r
I
Words:
Cycles:
I
Cycles:
k
I
k
1000
MOVLW
k
Words:
Cycles:
56h
;W=56h
W,PCLATH ; PCLATH = 56h
3Ah
; CALL 563Ah
Operation:
k --> W
Status bits:
None
Description:
The eight bit literal "k" is loaded into W
register.
MOVPF
Move ptof
Syntax:
MOVPF
p,1
Encoding:
I 010p I
pppp
Words:
1
I
ffff
ffff
I
Cycles:
Operation:
p --> I
MOVFP
Move fto p
Status bits:
Z
Syntax:
MOVFP
Description:
Encoding:
I 011p I pppp I
Move data from data memory location "p"
to data memory location "I". Location "I"
can be anywhere in the 256 byte data
space (OOh to FFh) while "p" can be OOh
to 1 Fh.
I,p
ffff
ffff
I
Words:
Cycles:
Operation:
f --> P
Status bits:
None
Description:
Move data from data memory location "f"
to data memory location "p". Location "I"
can be anywhere in the 256 word data
space (OOh to FFh) while "p" can be OOh to
1Fh.
Either "p" or "I" can be the W register (an
uselul special situation)
MOVPF is particularly uselul for transferring a peripheral register (e.g. the timer
or an I/O port) to a data memory location.
Either "p" or "I" can be the W register (a
uselul special Situation).
© 1992 Microchip Technology Inc.
DS30073B-page 18
1-186
MOVWF
Move Wtof
RETLW
Return Literal to W
Syntax:
MOVWF
Encoding:
10000 10001 1 ffff 1 ffff 1
Syntax:
Encoding:
'I-1O-l-l--r-O-l-l-O-'-I-kk-k-k---r-k-k-k-k--'
RETLW
k
Words:
Words:
Cycles:
Cycles:
2
Operation:
k ---7 W; TOS ---7 PC;
PCLATH (f03) is unchanged
Operation:
W---7f
Status bits:
None
Description:
Move data from W registerto data memory
location "f". Location "f" can be anywhere
in the 256 word data space.
NEGW
None
Description:
The W register is loaded with the eight bit
literal "k". The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged. This is a
two cycle instruction.
RETURN
Return from Subroutine
Negate W
Syntax:
NEGW
f,d
Encoding:
10010
nOd
Words:
1
1 ffff 1ffff
Cycles:
Operation:
Status bits:
W + 1 ---7
f;
W + 1 ---7
d
Syntax:
,:-:R.=E..:..T.=.U'-'R.;cN_ _-,-_ _-.-_---.
10000 1 0000 1 0000 1 0010 1
Status bit:
OV, C, DC, Z
Encoding:
Description:
The contents of the W register are negated using 2's complement. If "d" is Othe
result is placed in W register and data
memory location "f". If "d" is 1 the result
is placed only in data memory location "f".
Words:
1
Cycles:
2
Operation:
TOS ---7 PC;
PCLATH (f3) is unchanged
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS) is
loaded into the program counter. This is
a two cycle instruction.
RLCF
Rotate Left f through Carry
NOP
No Operation
Syntax:
Encoding:
rl-o-o-oo--rl-o-o-o-o'l-o-o-o-o'l-0-0-0-0---'1
Words:
1
NOP
Cycles:
No operation
Syntax:
RLCF
None
Encoding:
10001
Description:
No operation
Words:
RETFIE
Return from Interrupt
Syntax:
,R_E_T_FI_E.,-_ _. -_ _r-_--.
Encoding:
10000 1 0000 1 0000 10101 1
Operation:
Status bits:
Cycles:
2
TOS ---7 PC, 0 ---7 GLiNTD;
PCLATH (f3) is unchanged
Status bits:
GLlNTD
Description:
Return from Interrupt. Stack is popped
and Top of the Stack (TOS) is loaded in
PC. Interrupts are enabled by clearing
GLlNTD bit. GLlNTD is global interrupt
disable bit (bit 4, register CPUSTA). This
is a two cycle instruction.
1
ffff
ffff
Cycles:
Words:
Operation:
f,d
IlOld
© 1992 Microchip Technology Inc.
Operation:
I ---7 d; 1<7>
Status bits:
C
Description:
The contents of data memory location "f"
are rotated one bit to the left through the
Carry Flag. If "d" is 0 the result is placed
in the W register. If "d" is 1 the result is
stored back in data memory location "f".
---7
C; C ---7 d
DS30073B-page 19
1-187
RLNCF
Rotate Left f (no carry)
Syntax:
RLNCF
Encoding:
1
0010
Description:
f,d
1
OOld
ffff
ffff
1
Words:
If "d" is 0 both the data memory location "f"
and W register are set to FFh. If "d" is 1
the only the data memory location "f" is
set to FFh.
SLEEP
Cycles:
Syntax:
SLEEP
Operation:
I ---> d; 1<7> ---> d
Encoding:
I 0000 I 0000
Status bits:
None
Words:
Description:
The contents of data memory location "f"
are rotated one bit to the left. If "d" is 0 the
result is placed in the W register. If "d" is
1 the result is stored back in data memory
location "f".
Operation:
0---> PO; 1 --->TO
OOh ---> WDT; 0 ---> WDT prescaler
Status bits:
TO,PD
Rotate Right f through Carry
Description:
The power down status bit (PO) is cleared.
Time-out status bit (TO) is set. Watchdog
Timer and its prescaler are cleared.
RRCF
Syntax:
RRCF
Encoding:
1
0001
100d
1
ffft
1
ffff
0011
Cycles:
f,d
1
I 0000
The processor is put into SLEEP mode
with the oscillator stopped. See section
on SLEEP mode for more details.
1
Words:
Cycles:
SUBLW
Operation:
Subtract W from literal
Status bits:
C
Syntax:
,S_U_B_LW..,..._k_-.-_ _.-_--,
Description:
The contents of data memory location "f"
are rotated one bit to the right through the
Carry Flag. If "d" is 0 the result is placed
in the W register. If "d" is 1 the result is
placed in data memory location "f".
Encoding:
11011 I 0010
Words:
1
kkkk
kkkk
I
Cycles:
Operation:
(k - W) ---> W
RRNCF
Rotate Right f (no carry)
Status bits:
OV, C, DC, Z
Syntax:
Encoding:
RRNCF
Description:
'I-OO-l-O-'-O-O-O-d-'I-f-f-ff--'I-t-f-f-f--'
The contents of the W register are subtracted from the eight bit literal "k". The
result is placed in the W register.
SUBWF
Subtract W from f
Syntax:
SUBWF
Encoding:
I 0000
f,d
Words:
Cycles:
Operation:
Status bits:
Description:
I ---> d; 1<0> ---> d<7>
None
Set f and Set d
Syntax:
SETF
Encoding:
I 0010 IlOld
I OlOd I
ffff
ffff
I
Words:
The contents of data memory location "f"
are rotated one bitto the right. If "d"is 0 the
result is placed in the W register. If "d" is
1 the result is placed in data memory
location "f".
SElF
f,d
Cycles:
f,d
ffff I ffff
Operation:
(f-W) --->d
Status bits:
OV,C, DC, Z
Description:
Subtract (2's complement method) the W
register from data memory location"f". If
"d" is 0 the result is stored in the W
register. If "d" is 1 the result is stored back
in data memory location "f".
Words:
Cycles:
Operation:
FFh ---> f, FFh ---> d
Status bits:
None
DS30073B-page 20
© 1992 Microchip Technology Inc.
1-188
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB I,d
Encoding:
'I-0o-o-o-'-I-O-O-l-d-'-I-f-f-ff--'I-f-f-f-f---'I
Words:
Cycles:
Operation:
(I-W-C) -?d
Status bits:
OV, C, DC, Z
Description:
Subtract (2's complement method) the W
register and the carry Ilag (borrow) Irom
data memory location "I". II "d" is 0 the
result is stored in the W register. II "d" is
1 the result is stored in data memory
location "I".
SWAPF
TABLWT
SWAPF
Encoding:
I
0001
ffff I
Words:
Cycles:
Operation:
None
Description:
The upper and lower nibbles 01 data
memory location "I" are exchanged. II "d"
is 0 the result is placed in W register. II "d"
is 1 the result is place in data memory
location "I".
TABLRD
TABLRD
Encoding:
11010
t,i,1
1
Cycles:
2 (3 cycle il I = 02h [PC])
Operation:
II t = 1 then TBLATH -? I
else il t = 0 TBLATL -? I;
Prog Mem (TBLPTR) -? TBLAT;
il i = 1 then TBLPTR + 1 -? TBLPTR
Status bits:
None
Description:
First, either the low byte (il t = 0) or the
high byte (il t = 1) 01 the table latch
(TBLAT) is moved to register lile "I".
MOVLW
MOVPF
MOVLW
MOVPF
TABLRD
11010
12h
W, TBLPTRH
34h
W,TBLPTRL
0, 1, 50h
t, i, I
Inti I ffff I ffff
Cycles:
2 (Many il write is to on-chip EPROM
program memory)
Operation:
il t = 0 then I -? TBLATL
else il t = 1 then I -? TBLATH;
TBLAT -? Prog Mem (TBLPTR);
il i = 1 then TBLPTR + 1 -? TBLPTR;
Description:
First, contents ollile register I is loaded in
the low byte (il t = 0) or high by1e (il t = 1)
01 Table Latch, TBLAT.
For an interrupt to end programming, its
corresponding mask bit must enable the
interrupt. If the terminating interrupt is
INTIR, RTCIR or RTXIR, the Ilag bit is
automatically cleared. The clearing takes
place lor both short and long table writes.
The user can protect against accidental
clearing 01 an interrupt Ilag due to a
TABLWT instruction by masking off the
above mentioned interrupts belore doing
table write operations.
Then the contents olthe program memory
location pointed to by the 16 bit Table
Pointer (TBLPTR) is loaded into the 16 bit
Table Latch (TBLAT). Finally table pointer
is incremented il i = 1.
Example:
TABLWT
Encoding:
lithe Global Interrupt Disable bit (GLINTD)
is set, the interrupt will complete the
TABLWT, but no interrupt sequence will
be invoked. If GLlNTD = 0, then interrupt
will be acknowledged lollowing the
TABLWT.
I lOti I ffff I ffff I
Words:
Table write
II TBLPTR points to an internal EPROM
location, then an EPROM write (program)
sequence is initiated. It is terminated when
an interrupt is received.
Table Read
Syntax:
0,52h
1,53h
; TBLPTR = 1235h
; low byte --> 50h
; high byte --> 51 h
; TBLAT = Prog Mem
; (1235h)
; TB1.PTR = 1236h
; low byte --> 52h
; high byte --> 53h
II TBLPTR points to external program
memory location then the contents 01
TBLAT is written to it and the instruction
takes 2 cycles.
kO:3> -? d<4:7>, k4:7> -? d<0:3>
Status bits:
TLRD
TLRD
Syntax:
I,d
I nOd I ffff
0,50h
1,1,51h
Words:
Swapf
Syntax:
TLRD
TABLRD
MCLR/Vpp pin must be at programming
voltage lor successlul programming. II
MCLR/Vpp = Vee then the programming
sequence will be executed, but will not be
successlul (although the location may be
disturbed).
TBLPTR = 1234h
TBLAT = Prog Mem
(1234h)
DS30073B-page 21
© 1992 Microchip Technology Inc.
1-189
TLRD
Table Latch Read
Syntax:
rT_LR_D_,---,t,_1_,-_---,_ _--,
Encoding:
/1010 / OOtx
ffff
ffff
/
X= don't care
XORLW
Exclusive OR literal with W
Syntax:
Encoding:
'1-1-01-l--r-0-1-0-0--'-k-kk-k---'-k-k-k-k--'
Words:
1
XORLW
k
Words:
Cycles:
1
Cycles:
Operation:
(W .XOR. k) ---> W
Operation:
il (t = 0) thenTBLATL ---> I else il (t = 1)
then TBLATH ---> I
Status bits:
None
Description:
Read data Irom high byte (t = 1) or low
byte (t = 0) 01 16 bit Table Latch into file
register "I". Table Latch is unaffected.
This instruction is used in conjunction
with TABLRD to transler data Irom program memory to data memory.
TLWT
Table Latch Write
Syntax:
TLWT
Encoding:
/1010
ffff
Z
Description:
The contents olthe W register are XOR'ed
with the eight bit literal "k". The result is
placed in the W register.
XORWF
Exclusive OR W with f
Syntax:
XORWF
Encoding:
I 0000 I nOd
I,d
ffff
I
ffff
I
Words:
t,1
/ Oltx
Status bits:
/ ffff
/
x= don't care
Words:
Cycles:
Operation:
il(t=O) then 1---> TBLATLelse il(t= 1) then
1---> TBLATH
Status bits:
None
Description:
Data from Iile register I is written into the
low byte (t = 0) or thehigh byte(t = 1) 01
the 16 bit Table Latch.
Cycles:
1
Operation:
(W .XOR. I) ---> d
Status bits:
Z
Description:
Exclusive OR the contents 01 the W register with data memory location "I". II "d"
is 0 the result is stored in the W register.
II "d" is 1 the result is stored in data
memory location "I".
This instruction is used in conjunction
with TABLWT, to transler data Irom data
memory to program memory.
TSTFSZ
Test f, skip if 0
Syntax:
Encoding:
TSTFSZ
'/-0O-l-l--r/O0-1-1--r-f-f-ff---'-ff-f-f---'
Words:
1
Cycles:
1 (2)
Operation:
skip il I = 0
Status bits:
None
Description:
If the contents 01 data memory location "I"
are 0 then the next instruction is skipped.
II "I" = 0, the next instruction, letched
during the current instruction execution,
is discarded. A NOP is executed instead
making this a 2 cycle instruction.
© 1992 Microchip Technology Inc.
DS30073B-page 22
1-190
addressable since PCH is not mapped in data or program memory. An S bit register PClATH (PC high latch)
is used as a holding latch for the high byte of the PC.
PCLATH is mapped into data memory (file 03h). The
user can read or write PCH through PClATH.
3.0 HARDWARE DESCRIPTION OF
THE CPU
3.1 INDIRECT ADDRESSING
REGISTERS (FILES OOh & OSh)
The 16 bit wide PC is incremented after each instruction
fetch during 01 unless modified by GOTO, CAll,
lCAll, RETURN, RETlW, or RETFIE instruction or
interrupt response or due to destination write to PCl by
an instruction. "Skip"s are equivalentto incrementing the
PC twice.
These two register locations (not physically implemented)
are used to implement indirect addressing of data memory
space. An instruction using file address of 0 or S actually
accesses the data memory location pointed to by the
corresponding FSR register (file 1 orfile9).lffileOOh (or
file OSh) itself is read indirectly via an FSR, all zeroes
are read. Similarly, if file OOh (or file OSh) is written to
indirectly, the operation will be equivalent to a Nap.
The operations of the PC and PCLATH for different
instructions are as follows:
a) lCAll:
PClATH ~ PCH , IR<7:0> ~ PCl (PCl is
loaded with S bit destinaton address embedded
in the instruction. PClATH is unchanged.
Single cycle data transfers within the entire data space
are possible with MOVFP and MOVPF instructions,
when "p" is specified as "OOh" and "f" as "OSh", or vice
versa.
b)
CAll GOTO:
A 13 bit destination address is provided in the
instruction
IR<12:0> ~ PC <12:0>
PC<15:13> ~ PCLATH<7:5>
3.2 FILE SELECT REGISTERS (FSRO
AND FSR1, FILES 01 hAND 09h )
c)
These two registers are S bit wide indirect address
pointers for data memory. They can be autoincremented, auto-decremented or left unchanged after
each access as determined by the 4 control bits in the
status register "AlUSTA" (File 04h bits 7:4). See figure
3.S.1.
Read 103 (Any instruction that reads PCl):
PCl ~ data bus ~ AlU or destination
PCH ~ PClATH
d)
Write 103 (Any instruction that writes to PCl)'
S bit data ~ data bus
PClATH ~ PCH
e)
3.3 TABLE POINTER (TBLPTRL FILES
AND TBLPTRH, FILES ODh AND
OEh)
~
PCl
Read-Modify-Write (Any instruction that does a
read-write-modify operation on f02, such as
ADDWFI02)
Read: PCl ~ data bus ~ AlU
Write: S bit result ~ data bus ~ PCl
PClATH ~ PCH
File registers ODh and OEh form a 16 bit pointer to
address the 64K program memory space. The table
pointer is used by instructions TABlWT and TABlRD.
The TABlRD and the TABlWT instructions allow
transfer of data between program and data space.
The table pointer serves as the 16 bit address 01 the
data word within the program memory.
Note that read-modify-write only affects the PCl with the
result. PCH is loaded with PClATH. Thus, ADDWF 102,
for example will result in a jump within the current page.
If PC = 03FOh, W = 30h and PCLATH = 03h before
instruction, PC = 0320h after the instruction. To accomplish a true 16 bit computed jump, the user needs to
compute the 16 bit destination address, write the high
byte to PClATH and then write the low value to PCL.
3.4 TABLE LATCH (TBLATH,
TBLATL)
The table latch (TBlAT) is a 16 bit register, consisting of
TBlATH and TBLATl refer to the high and low bytes 01
the register. It is not mapped into data or program
memory. The table latch is used as a temporary holding
latch during data transfer between program and data
memory (see descriptions of instructions TABlRD,
TABlWR, TlRD and TlWR).
The following PC related operations do not change f03h:
a) lCAll, RETlW, RETURN, RETFIE instructions,
b) Interrupt vector is forced onto the PC,
c) Read-modify-write instructions (e.g. BSF 02) on
102h.
3.6 STACK
3.5 PROGRAM COUNTER MODULE
The PIC17C42 has a 16 word x 16 bit hardware stack
which is not part of data or program space. The PC is
pushed onto the stack if CAll or lCAll instructions are
executed or if an interrupt is responded to by branching
to the corresponding interrupt vector. The stack is POPed
The program counter (PC) is a 16 bit register. PCl, the
low byte of the PC, is mapped in the data memory (file
02h). PCl is readable and writable just as any other
register. PCH is the high byte olthe PC and is not directly
I):i!:
© 1992 Microchip Technology Inc.
1-191
DS30073B-page 23
into the PC if a RETURN, RETLW or RETFIE instruction
is executed. The top of the stack is not addressable in
any other way.
.
~j
·(1·
!
multiple levels is possible by enabling interrupts within
the service routine. When an interrupt occurs, the
current PC value is pushed onto the stack and the vector
corresponding to the interrupt source is loaded into the
PC.
3.6.1 Stack Available Status Bit
(Bit 5, CPUSTA)
3.7.1 Interrupt Flag and Mask Bits
STKAVL is a read only status bitthat indicates any stack
overflow error. STKAVL is setto '1' on reset and stays '1'
unless the following situation occurs:
Each interrupt has a request flag bit and a mask bit
associated with it. The registers that hold these bits are
INTSTA (file 07h), PIR (Bank 1, file 16h) and PIE (Bank
1, file 17h). See table 3.7.1 for details.
If stack is full' i.e. there are 16 entries in the stack the
STKAVL is selto '0' . If, the stack is popped (by RETURN,
RETLW or RETFIE instruction) then STKAVL is sello '1'
again indicating 'stack availability'.
Interrypt flag bjts INTIR RTCIR or RIXIR are cleared
aytomatically in hardware. PEIR is not cleared automatically since it is not a latched bit. PEIR is simply the
OR of all the individual peripheral interrupt flag bits such
as IRB, TM3IR, etc. Therefore if PEIR is the source of
the interrupt, the user must clear, in software, the actual
peripheral interrupt flag bit. The global interrupt disable
bit, GLiNTD, is set, in any case, preventing any further
interrupt. To enable interrupts from the service routine
the user must clear GLiNTD. The user, must first clear
the current interrupt flag bit to prevent recursive vectoring to the same service routine.
If, however, a push takes place instead (due to CALL,
LCALL or interrupt), then stack overflow occurs. In this
event the first entry is lost and STKAVL is permanently
cleared to '0'. Under this condition, the only way STKAVL
will set to '1' is via reset.
STKAYL usage caution: If the stack is empty, a POP
(due to RETURN, RETLW or RETFIE)foliowed by a
PUSH, will permanently clear STKAVL to '0 '.
For a description of CPUSTA register, see figure 4.5.1.
The TABLWT instruction, in a long write situation (i.e.
writing to on-chip EPROM location) must be terminated
with an interrupt. On completion, TABLWT clears the
interrupt flag in the same exact fashion as an interrupt
response, i.e. INTIR, RTCIR or RTXIR flag will be
cleared if responsible for ending the TABLWT.
3.6.2 Using the STKAVL bit
One way to use the STKAVL bit is to test it at the
beginning of every subroutine or interrupt service routine. If STKAVL = 0, then all stack locations are used
(and presumably no error has occurred yet). In such
case, interrupts must be disabled in the subroutine.
Also, no subroutine calls must be made unless software
stack management is invoked.
3.7.2 Peripheral interrupts
All peripherals use the same interrupt vector, 0020h.
The individual peripheral interrupt request bits are "ORed"together. When multiple peripheral interrupt sources
are enabled, the priorities have to be determined by
software. Each peripheral has its own interrupt enable
and request bit(s). In addition, the PEIE (Peripheral
Interrupt Enable) bit acts as a global enable bit for all
peripheral interrupts. There is a common peripheral
interrupt request status bit (PEIR, bit 7, register
INTSTA)which is a logical OR of all the individual
peripheral interrupt request flags. This is a read only
status bit useful for quickly determining if any peripheral
request is outstanding.
3.7 INTERRUPT LOGIC
The PIC17C42 has 11 interrupt sources that are mapped
into 4 interrupt vectors. The in,terruptlogic is controlled
by the INTSTA register and the global interrupt disable
bit (GLINTD) in CPUSTA register, file f06h. See figure
4.5.1 for a description of CPUSTA register. Four hardwired vectors allow fast interrupt response time. Worst
case latency is 3 instruction cycles when only one
interrupt at a time is being serviced. Interrupt nesting to
3.7.1 TABLE OF INTERRUPTS
Interrupt
flfl9
Flag location
bit, Register
Interrupt
mask bit
Mask bit
location bit,
Register
Interrupt Source
Priority
Vectors to
INTIR
RTCIR
RTXIR
PEIR
bit4,INTSTA
bit 5,INTSTA
bit 6, INTSTA
bit 7, INTSTA
INTIE
RTCIE
RTXIE
PEIE
bit 0,
bit 1,
bit 2,
bit 3,
INTSTA
INTSTA
INTSTA
INTSTA
External interrupt on INT pin
RTCC overflow interrupt
External interrupt on RT pin
Any peripheral interrupt
Highest priority
2nd priority
3rd priority
Lowest priority
0008h
0010h
0018h
0020h
IRB
TM31R
TM2IR.
TMHR
CA21R
CA11R
TBMT
RBFL
bit 7,
bit 6,
bitS,
bit 4,
bit 3,
bit 2,
bit 1,
bit 0,
IEB
TM31E
TM21E
TMllE
CA21E
CAllE
TXIE
RCIE
bit 7,
bit 6,
bitS,
bit 4,
bit 3,
bit 2,
bit 1,
bit 0,
PIE
PIE
PIE
PIE
PIE
PIE
PIE
PIE
Port B input change interrupt
Timer/Counter3 interrupt
Timer/Counter2 interrupt
Timer/Counter1 interrupt
Capturel interrupt
Capture2 interrupt
Serial port transmit interrupt
Serial port receive interrupt
lowest priority
(All these
peripheral
interrupts are
OR'ed together
to generate
PEIR)
0020h
DS30073B·page 24
PIR
PIR
PIR
PIR
PIR
PIR
PIR
PIR
II
I'
";~Ull;~
Ii ~ ]:((j)
1-192
til
© 1992 Microchip Technology Inc.
FIGURE 3.7.1.1: REGISTER INTSTA
I
R/W
PEIR
I
R/W
RTXIR
I
RIW
RTCIR
I
R/W
INTIR
RlW
I
PEIE
I
R/W
RTXIE
I
RIW
RTCIE
I
R/W
INTIE
I
R = Read only bit
RIW = Readable/writable bit
U= Unused, reads as 0
bit 0
o : Disable INT interrupt
1 : Enable INT interrupt
-
: Disable RTCC interrupt
: Enable RTCC interrupt
o : Disable RT pin interrupt
1 : Enable RT pin interrupt
o : Disable all peripheral interrupts
1 : Enable all peripheral interrupts
INT interrupt request flag. Set by rising or falling
edge on INT pin. Reset automatically by
hardware.
RTCC timer interrupt request flag. Set when
RTCC overflows. Reset automatically by
hardware.
RT pin interrupt. Set by rising or falling edge on
RT pin. Reset automatically by hardware.
Peripheral Interrupt Request flag. It is read
only.
FIGURE 3.7.1.2: PIR (PERIPHERAL INTERRUPT REQUEST) REGISTER
I
R/W
IRB
I
RIW
TM31R
I
RIW
TM21R
I
RIW
TM11R
I
RIW
CA21R
I
RIW
CA11R
I
R
TBMT
I
R
RBFL
I
L
R = Read only bit
RIW = Readable/writable bit
U = Unused, reads as 0
Serial port receive interupt. Set when receive
buffer (RCREG) is full. Reset when receive
buffer is empty. It is a read only bit.
Transmit interrupt. Set when transmit buffer
(TXREG) is empty. Reset when transmit buffer
is full. It is a read only bit.
Capture1 interrupt. Set when a capture event
occurs. Reset by software.
Capture2 interrupt. Set when a capture event
occurs. Reset by software.
Timer1 interrupt. It is set when timer1 reaches
period value and resets. Reset by software.
Timer2 interrupt. Sets when timer2 reaches
period value and resets. Reset by software.
If capture1 is enabled (CA1/PR3 = 1) then this
interrupt is set when timer3 overflows.
If capture1 is disabled (CA1/PR3 = 0) then the
interrupt will be generated when timer3
reaches period value and resets. Reset by
software.
Port B interrupt. Set when Port B input
charges. (from port latch value) Reset in
software
© 1992 Microchip Technology Inc.
i;
DS30073B-page 25
1-193
FIGURE 3.7.1.3: PIE (PERIPHERAL INTERRUPT ENABLE) REGISTER
I
R/W
IEB
I
R/W
TM31E
RIW
RlW
R/W
RIW
I TM21E I TM11E I CA21E I CA11E I
RIW
TXIE
I
RIW
RCIE
I
R= Read only bit
RIW = Readablelwritable bit
[
U = Unused, reads as 0
: Disable receive interrupt (RBFL)
: Enable receive interrupt (RBFL)
: Disable transmit interrupt (TBMT)
: Enable transmit interrupt (TBMT)
0: Disable capture1 interrupt (CA1IR)
1 : Enable capture1 interrupt (CA 11R)
: Disable capture2 interrupt (CA2IR)
: Enable capture2 interrupt (CA2IR)
: Disable Timer1 interrupt (TM1IR)
: Enable Timer1 interrupt (TM1IR)
o : Disable Timer2 interrupt (TM2IR)
1 : Enable Timer2 interrupt (TM2IR)
: Disable Timer3 interrupt (TM3IR)
: Enable Timer3 interrupt (TM3IR)
: Disable Port B interrupt (IRB)
: Enable Port B interrupt (IRB)
Please note that changing edge selection for INT or RT
pin may generate a false interrupt. The user should
clear the INTIR or the RTXIR bit after changing edge
setting.
3.7.3 INT and RT External Interrupts
INT and RT external interrupts can be positive or negative edge triggered, selectable in software. INT interrupt
is generated on falling edge if INTEDG = 0 or on rising
edge if INTEDG = '1'. Similarly, setting bit RTEDG = '0'
will generate RT pin interrupt on falling edge whereas
RTEDG = '1' will trigger RT interrupt on rising edge. The
timing requirements on INTand RTinputs are as follows:
~
tlNTH = tRTIH = INT or RT high time
tlNTl = tRTll = INT or RT low time
~
See RTCSTA (register file 05h) for bit allocation.
25ns
25ns
FIGURE 3.7.3.1: RTCSTA: RTCC STATUS/CONTROL REGISTER
RIW
RIW
R/W
ilNTEDG
I RTEDG I
TIC
RlW
I
RTPS3
RIW
R/W
R/W
RIW
J RTPS2 J RTPS1 l RTPSO 1unused JI Register
RTCSTA
File 05h
L---,~-L~,--L-~,-~-L~r---'~,--~L--,~-L~..,~"---,-~-'
bit 0
I
RIW: ReadablelWritable I
Reset Value: OOh
-Prescale Value Selection
RTPS <3:0>
<
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
Prescale Value
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
: Timer mode, Le. clock source is internal (OSC/4)
: Counter mode, i.e. clock source is external (RT pin)
: RTCC increments andlor RT interrupt generated
on a falling edge on RT pin.
1 : RTCC increments and/or RT interrupt generated
on a rising edge on RT pin.
: INT interrupt generated on falling edge on INT pin
: INT interrupt generated on rising edge of INT pin
DS30073B-page 26
© 1992 Microchip Technology Inc.
1-194
3.8 ALU
The Arithmetic and Logic Unit of the PIC17C42 is
capable of carrying out arithmetic or logical operations
on two operands or a single operand. All single operand
instructions operate either on the W register or a file
register. For two operand instructions, one of the
operands is the W register and the other one is either a
file register or an 8 bit immediate constant.
FIGURE 3.8.1: ALUSTA (ALU STATUS) REGISTER
RIW
,
FS3
RIW
,
FS2
RlW
R/W
,
FS1
,
FSO
RlW
R/W
,
OV
,
Z
R/W
,
DC
R/W
,
c
'I
~
Register ALUSTA
R = Read only bit
File 04h
R/W = Readable/writable bit
Reset value: 1111 XXXXb U =Unused reads as 0
Carrv Flag: Set by arithmetic instructions when a carry
out from MSB occurs. Also affected by rotate through
carry instructions.
Digit Carry: Set by arithmetic instructions when a carry
from lower nibble to upper nibble occurs.
Zero Flag: Set to 'I' when the result of an arithmetic or
logical operation is zero.
Overflow Flag: Set to '1' when an overflow (from
magnitude to sign bit) occurs in an arithmetic operation.
It is the XOR of carry·in and carry,oul of the MSB bit.
FSRO Mode Select:
00: Post auto·decrement FSRO
01: Post auto·increment FSRO
10: Reserved (currently same as 11)
11 : No change to FSRO
FSRI Mode Select:
00: Post auto·decrement FS R1
01: Post auto·increment FSRI
10: Reserved (currently same as 11)
11 : No change to FSRI
DS30073B-page 27
© 1992 Microchip Technology Inc.
1-195
4.0 SPECIAL FEATURES OF THE
CPU
4.1 RESET
The reset logic resets the complete PIC17C42 circuitry
as follows:
• Oscillator buffer is enabled (i.e. oscillator is restarted
if waking up from SLEEP through reset).
• Program Counter is reset to OOOOh.
• All registers are reset as described in Table 1.6.2.
• Watchdog timer & its prescaler are cleared.
• Internal phase clock generator is held in 01 state. If
extern~execution is selected, ALE output is held low
while OE and WR outputs are driven high.
• 1/0 ports B, C, D and E are configured as inputs. In
case of port B, the weak pull-ups are activated. Ports
RA2 and RA3 revert to high impedance state.
There are three events which can cause a device reset.
a) Power On Reset :Voo rise is detected (1.2V - 2.0V
range)
b) External reset: "Low" level on the MCLR input
What sets apart a microcontroller from other processors
the most are special circuits to deal with the needs of
real time applications. The PIC17C42 has a host of such
features intended to maximize system reliability, minimize cost through elimination of costly external components, provide power saving operating modes and offer
code protection.
The PIC17C42 has a watchdog timer which can be shut
off only through EPROM fuses. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the oscillator start-up timer (OST), intended to keep the chip in
reset until the crystal oscillator is stable. The other is the
power-up timer (PWRT), which provides a fixed delay of
80 ms nominal on power up only, designed to keep the
part in reset while the power supply stabilizes. With
these two timers on chip, most applications need no
external reset circuitry. The SLE EP mode is designed to
offer a very low current power-down mode. The user can
wake up from SLEEP through external reset, watchdog
timer time-out or through an interrupt. Several oscillator
options are also made available to allow the part to fit the
application. The RC oscillator option saves system cost
while the LF (low frequency)crystallresonator option
saves power. A set of EPROM configuration bits (fuses)
are used to select various options. Additional EPROM
fuses are included for code-security.
c)
WDT reset: Watchdog timer Time out
The RESET condition is maintained as long as
a)
b)
the MCLR input is "low"
MCLR has gone high but the Power-up timer
(PWRT) is active, (i.e. has not timed out)
c)
MCLR has gone high butthe oscillator start-up timer
(OST) is active (i.e. has not timed out)
FIGURE 4_1.1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
j-----------js
10 bit Ripple counter
10 bit Ripple counter
POWER UP
(Enable the PWRT timer
only if it is power_up.)
© 1992 Microchip Technology Inc.
DS30073B-page 28
1-196
4.2. OSCILLATOR
FIGURE 4.2.1: DIFFERENT OSCILLATOR/
CLOCKIN OPTIONS
The PIC17C42 can accept an external clock input on
OSC 1 pin or will run off external crystal or cerarnic
resonator connected between OSC1 and OSC2 pins. It
also has an RC oscillator mode in which an external R
and C combination can be connected to OSC1 pin. The
choice is made by EPROM fuses FOSC1 and FOSCO.
These fuses are mapped in program memory locations
FE01 hand FEOOh respectively. Refer to section 4.8 for
details on the fuses.
4.2.1 A EXTERNAL CLOCK
Ext
Clock In
OSC1
CLKOUT _
OSC2
TABLE 4.2.1: OSCILLATOR OPTIONS
Fosc1,
OSC1 Pin
Function
OSC2 Pin
Function
Freq.
Range
External clock
input
CLKOUT
output
DC-16Mhz
External RC
oscillator
connection
CLKOUT
output
DC-4Mhz
Crystal
connection
Crystal
connection
O.2-16Mhz
mode
Low frequency
crystal oscillator
Crystal
connection
Crystal
connection
32-200Khz
Mode
FoscO
Fuses
External Clock input
11
EC:
01
RC: RC oscillator
mode
10
00
XT:
LF:
PIC17C42
Crystal oscillator
4.2.18 RC OSCILLATOR MODE
CLKOUT
mode
PIC17C42
Note: 0 implies a programmed fuse.
4.2.1 EC: External Clock Input Mode:
4.2.1C XT CRYSTAL OSCILLATOR MODE
C1
The OSC1 input can be driven by CMOS drivers (figure
4.2.1 A). In this mode, the OSC1 pin is a high impedance
CMOS input. The OSC2 pin outputs CLKOUT (frequency =fosc/4). See Figure 1.2.1 for timing of CLKOUT.
422 BC' BC Oscillator Mode:
An external Rand C combination can be connected to
OSC1 pin (figure 4.2.1 B). The RC oscillator mode provides a very cost effective solution. However, the frequency of oscillation will vary with Vcc, temperature and
from chip to chip due to process variation. It is, therefore,
not the right choice for timing sensitive applications
where accurate oscillator frequency is desired. The
OSC2 pin, in this mode, outputs CLKOUT (freq. = fosc/
4). See Figure 1.2.1 for timing of CLKOUT.
4.2.10 XT CRYSTAL OSCILLATOR MODE
(OVERTONE CRYSTALS)
4.2.3 XT: Crystal Oscillator Mode:
In this mode a crystal or a ceramic resonator can be
connected across OSC1 and OSC2. (figure 4.2.1 C).
The crystal must be of fundamental mode. If an overtone
mode crystal is used (which is common above 20 MHz)
then a tank circuit must be used to attenuate the gain at
fundamental frequency (figure 4.2.10)
0.1
~F
PIC17C42
To Filter the fundamental frequency
4.2.4 LF: Low Frequency Crystal Oscillator
Mode:
L62
=
(2"f)2
Where f= tank circuit resonant frequency.This should be midway
between the fundamental and the 3rd overtone frequencies of
the crystal.
This is same as the XT mode, (figure 4.2.1 E) except that
it is suitable for crystals of frequency range 32 KHz to
200 KHz.
© 1992 Microchip Technology Inc.
DS30073B-page 29
1-197
The following table shows the time-outs for different
oscillator types.
4.2.1E LF CRYSTAL OSCILLATOR MODE
C1
h2~
PIC17C42
Oscillator
Type
Power-up
Wake-up from
SLEEP
-
EC
80ms
RC
80 ms
XT
Greater of 80 ms
and 1024 tosc
1024tosc
LP
Greater of 80 ms
and 1024 tosc
1024tosc
-
4.3 OSCILLATOR START-UP TIMER
(OST)
FIGURE 4.4.1: BROWN OUT PROTECTION
CIRCUIT
The OST provides a 1024 oscillator period delay on
power-up and on wake up from SLEEP. This delay is
provided by a 10 bit ripple counter. On power-up, the
delay begins from the rising edge of MCLR. On wake-up
from SLEEP the time-out is counted from the time the
wake-up event occurs. Since the OST counts oscillator
signal on OSC1 pin, the counter only starts counting
when amplitude on OSC1 pin reaches a certain acceptable limit. The OST time-out allows the crystal oscillator
(or resonator) to stabilize before the chip is taken out of
reset. The circuit will function with crystals of any frequency. This time-out is not invoked in RC oscillator
mode or external clock (EC) mode.
VDD~~----~--I\V~DloD~------~
33 K
PIC17C42
4.4 POWER-UP TIMER (PWRT) AND
POWER-ON RESET (POR)
Notes:
1. This circuit will activate reset when VDD goes
below (VZ + 0.7 V) where VZ = Zener voltage.
The function of the PWRT timer is to provide a fixed 80
ms (typical) delay only on power-up. This is provided by
a 10 bit ripple counter whose input clock comes from an
on chip RC oscillator. The time-out is counted from the
riSing edge of MCLR. The purpose of this time-out is to
allow the Voo supply to reach acceptable level before
the part is taken out of reset.
FIGURE 4.4.2: BROWN OUT PROTECTION
CIRCUIT
An internal Power-on Reset pulse (POR) is generated
when a Voo rise is detected during initial power-up of the
chip. (when Voo = 1.2V to 2.0V nominally). The POR
signal resets internal registers as described in table
1.6.2. The user should note that the on-chip circuitry
does not generate an internal reset when Voo goes down,
i.e., it does not provide brown out protection. Figure
4.4.1 and 4.4.2 shows possible external brown-out protection circuits. Also Voo must come up from Vss
(nominal) for a POR signal to be generated. The PWRT
timer and OST timer guarantee proper power-on reset
without external components. This is done by simply
tying the MCLR pin to Voo (figure 4.4.4). As voo comes
up, POR is generated and MCLR is sensed as '1' inside
the chip, both OST and PWRT timers begin time-out.
The 80 ms (nominal) delay of the PWRT allows Voo to
rise above Voo min. spec. If the rise time of Voo is much
slower such that at the end of the time-out Voo has not
reached an acceptable level (as in figure 4.4.6) then
external RC delay must be added on MCLR pin.
VDD
R1
R2
PIC17C42
Notes:
1. This brown circuit is less expensive, albeit less
accurate. Transistor 01 turns off when VDD is
below a certain level such that:
R1
VDD· R1 +R2 =0.7V
DS30073B-page 30
© 1992 Microchip Technology Inc.
1-198
FIGURE 4.4.3: EXTERNAL RESET PULSE
FIGURE 4.4.6: INTERNAL RESET (VDD AND
MCLR TIED TOGETHER): SLOW VDD RISE
TIME
VDDJ
MCLR _ - : -_ _ _ _ _~/
INTERNAL POR
~~-------T,
:
_ _ _, _
VDD
~:
PWRTTIME-OUT
--------+------'1
MCLR
OSTTIME-OUT
---------:--~I-
INTERNAL paR
:... tasT ... :
INTERNAL RESET
---------r-
~!--:- - - - - ; - - i..
-------------'1
PWRT TIME-OUT
FIGURE 4.4.4: USING ON-CHIP POR
5V
~-
+:
tPWRT
r--
-~c-----,----,--,:
~:
;..-- tasT
OST TIME-OUT --'-------'
----'r--
,
INTERNAL RESET _ _ _ _ _
-
VDD
-
MCLR
Note:
In this example t PWRT > tOST as would be the
case in higher frequency crystals. For lower
frequency crystals (i.e. 32 Khz) tOST will be
greater.
PIC17C42
FIGURE 4.4.5: INTERNAL RESET (V DO AND
MCLR TIED TOGETHER)
VDD
---/
:"'~------
MCLR
INTERNAL paR
~
~!--'---0------,-: ..
PWRT TIME-OUT
_-----;------:-_-----'r-~
OST TIME-OUT
INTERNAL RESET
Note:
tpWRT~
,~tosT
____-'r--
In this example tPWRT> t OST as would be the case
in higher frequency crystals. For lower
frequency crystals (i.e. 32 Khz) tOST will be
greater.
:')"[1
© 1992 Microchip Technology Inc.
1-199
DS30073B-page 31
FIGURE 4.4.7: OST START UP TIMING
DETAILS
MCLR
OSC2
OST TIME_OUT _ _---i-_ _ _ _ _-i
PWRT TIME_OUT _ _-+--_ _ _-'
lPWRT
INTERNAL RESET _ _-'--_ _ _'----'
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example the low
frequency crystal start-up time is larger than power-up
time (lPWRT).
tose1 = time for the crystal oscillator to reach oscillation
level detectable by the oscillator start-up timer
(OST)
tOST = 1024 t ose
4.5 SLEEP MODE
The full static design of the PIC17C42 makes it possible
to putthe part in a power saving SLEEP (or power down)
mode in which all on chip clocks are stopped.
The SLEEP mode, entered by executing a SLEEP
instruction, shuts down the oscillator, sets TO (bit3,
CPUSTA), clears PO (bit2, CPUSTA), the watchdog
timer and its prescaler. In XT or LP mode, both OSC1
and OSC2 are placed into high-impedance state. In EC
and RC modes, OSC1 pin is placed in high-impedance
state while OSC2 is driven low. No clocks are presented
to the internal logic even when an external clock is
present on the OSC1 pin. The chip will remain in a
completely static condition with the following exceptions:
a)
b)
c)
If the watchdog timer is enabled, it will keep running
and will consequently wake up the chip on time-out.
Signal edges on the RT pin (rising or falling whichever is defined to be the active edge by the RTEOG
control bit) will increment the RTCC prescaler (an
asynchronous ripple counter) if an external clock
source is selected for RTCC. The RTCC itself will
not increment.
Any external interrupt event, such as RT, INT,
capture1 or capture2 interrupt will wake the processor provided the corresponding interrupt mask bit
was enabled when entering SLEEP mode. If global
interrupt disable is off (GUNTO=O) then the chip will
jump to corresponding interrupt vector on wake-up.
Otherwise the chip will wake up and resume executing without responding to the interrupt (Le. will not
branch to interrupt vector).
DS30073B-page 32
d)
Any peripheral operating independent of the internal processor clock can change its status due to
external events. Specifically, the serial port receive
shift register will shift in data in synchronous slave
(external clock) mode.
Besides the on-chip oscillator, any circuitry that consumes current is turned off in SLEEP mode. This
includestheentire EPROM and, in particular, the EPROM
fuses. The only fuses that will remain active are the WOT
fuses (FWOTO, FWOT1). If minimal SLEEP current is
desired, the user should consider turning off the watchdog timer. Since fuses consume current in '1' state.
Turning WOT off not only saves the operating current it
requires, but also saves fuse current due to FWOT1 or
FWOTO fuses. All I/O pins maintain their status during
SLEEP.
4.5.1 Wake-up from SLEEP
Once the chip has entered the SLEEP mode it can only
be awakened by one of the following events:
a)
b)
c)
d)
Bringing VDD down to zero and back up to operationallevel will induce a power on reset and wake up
the chip.
Applying a "low" level on MCLR pin
A watchdog timertime-out (WOT must be enabled).
"TO" status bit will be cleared in this case.
The following interrupts can wake up the processor
from SLEEP:
1. External interrupt on RT pin
2. External interrupt on INT pin
3. Capture 1 interrupt, due to a capture event on the
RBO/CAP1 pin. The prescaler on the capture
input will operate during SLEEP. The actual
capture olthe timer value will occur when execution resumes after wake-up (which is therefore,
not meaningful).
4. Capture2 interrupt.
5. Input change on Port B interrupt
6. Synchronous slave mode transmission interrupt:
If synchronous transmission is in progress (using
external clock) at the time the processor is put to
SLEEP, a TBMT interrupt will be generated atthe
end of the transmission and wake the chip up.
7. Synchronous slave mode reception interrupt: If
synchronous reception is enabled (CREN = 1)
before the chip goes into SLEEP, then RBFL
interrupt will be set at the end of a reception (if a
receive word came during SLEEP) which will
wake the chip up.
If GUNTO = 0, the normal interrupt response takes
place. If GUNTO = 1, the chip will resume execution
starting with the instruction following the SLEEP instruction. It will not vector to interrupt service routine.
If selected oscillator type is XT or LP then the oscillator
start-up timer (OST) is activated on wake-up. This will
mean that the timer will keep the part in reset for 1024
tosc. The user needs to take this into account when
considering interrupt response time coming out of SLEEP.
© 1992 Microchip Technology Inc.
FIGURE 4.5.1: CPUSTA REGISTER
U
U
R
R/WR/WR/W
U
U
CJ~_,I_S-rTK_AV~I_'G-,LlN_TD-,-)I_T,-O-"I_P-,D-,I~--,I=.=l
I
Register: CPUSTA
R = Read only
R/W = Readable/Writable bit
File OSh
Power-an-Reset Value: U = Unimplemented, reads as '0'
00111100b
Power-down status bit.
Po = 0 indicates that the chip was in power-down (SLEEP mode).
PD is set to '1' on power-on reset.
It is cleared when a SLEEP instruction is executed.
It is unaffected otherwise. The user should look at this coming
out of reset to determine how the reset was caused (Table 4.5.1.1).
Time-out status bit.
TO = 0 indicates WDT time-out. TO is set on power-on reset.
It is cleared when WDT times out. It is unaffected otherwise.
The user should look at this coming out of reset to determine how
the reset was caused (Table 4.5.1.1).
Global Interrupt Disable bit.
GLlNTD = 0: Enables all interrupts. For an interrupt to be
enabled, its individual enable bit must also be a '1 '.
GLlNTD = 1: Disables all interrupts.
Stack available bit.
STKAVL = 2 indicates stack is available.
STAKVL = 0 indicates stack is full or a stack-error may have occured.
See section 3.S.1 for a detailed description.
TABLE 4.5.1.1: WAKE -UP AND RESET FUNCTION TABLE
C~ funclion
Event
Chip Status
before event
Power on reset
MCmreset
SLEEP instruction
MCLR wake-up
WDT time-out
WDTwake-up
Interrupt
Interrupt wake-up
Don't care
Normal operation
Normal operation
SLEEP
Normal operation
SLEEP
Normal operation
SLEEP,GLlNTD=O
Interrupt wake-up
SLEEP,GLlNTD=1
alter event
Oscillator
PC
0000
0000
N+l
0000
0000
0000
Vector
1. N+l
2.Vector
1. N+l
2. N+2
Circuit
OST
To
-
PD
Notes
u
1
u
0
u
u
u
u
u
1
u
u
1
on
on
off
on
on
on
on
on
yes
no
no
yes(2)
no
yes(2)
no
yes(2)
1
u
1
u
0
0
on
yes(2)
U
Legend
Notes
PC
Note 1:
The instruction at "N+ 1" executed, after wake up.
Step 2 depends on the status of the GLlNTD bit at
the time of the event. If GLlNTD was "0", the
program will vector to the interrupt routine.
Note 2:
OST timer is activated only in XT and LP oscillator
modes. (Sec. 4.4)
Program Counter contents after the event
TO Time Out status bit after the event
PD
Power Down status bit after the event
N
Address of SLEEP instruction
U
No change takes place
4.5.2 Interrupt/SLEEP Interaction
4.5.3 Minimizing Current Consumption in
SLEEP Mode
If an interrupt occurs during the very cycle a SLEEP
instruction is fetched, it will be recognized in the following cycle (which is the execution cycle of the SLEEP
instruction) preventing the processor from going into
SLEEP. The SLEEP instruction will effectively execute
as a single cycle NOP. The PD bit will not be cleared.
The SLEEP mode is designed to reduce power consumption. To minimize current drawn during SLEEP
mode, the user should turn-off output drivers that are
sourcing or sinking current, if it is practical. Weak pullups on port-pins should be turned off, if possible. All
inputs should be either at Vss or at VDD (or as close to
rail as possible). An intermediate voltage on an input pin
causes the input buffer to draw a significant amount of
current.
© 1992 Microchip Technology Inc.
DS30073B-page 33
1-201
4.6 WATCHDOG TIMER
not result in programming of the destination. However,
the instruction will still need to be terminated by an
interrupt condition and the table latches will still be
written. A TABLWT instruction, executed from an address less than 2K can program any user EPROM
location regardless of code protection.
The PIC17C42 has an on chip watchdog timer whose
function is to recover from software malfunction. The
watchdog timer is an 8 bit asynchronous ripple counter
with an 8 bit prescaler ( also an asynchronous ripple
counter). The watchdog timer always runs off its own
internal RC oscillator. The watchdog timer is not readable or writable. It is not mapped in data or program
memory space. Two EPROM fuses provide four operating options for the watchdog timer:
FWOTl, WOT Clock
FWDTO Input Source
10
RC osc
o1
RC osc
11
RC osc
00
OSC/4
WDT Function
Input Clock
WDT runs with prescale = 256
WDT runs with prescale = 64
WDT runs with prescale = 1
WDT runs as a regular timer
with prescale = 256
Note. 0 Implies a programmed fuse.
The above measures essentially prevent read, verify or
programrning of any user EPROM location from outside.
4.8 CONFIGURATION FUSES
Configuration fuses are EPROM bits that can be programrned (reads '0') or left unprogrammed (reads '1 ') to
select between options (e.g. operating modes). For
simplicity of programrning they are mapped into program memory. This also makes it possible to read the
fuse values (only in microcontroller modes). Each fuse
is assigned one program memory location. In erased
condition a fuse will read as a '1 '. To program (or "blow")
a fuse, the user needs to write to the fuse address using
a TABLWT instruction. Regardless of the data, a
TABLWTto a fuse location will bow the fuse. The fuses
and their addresses are shown in table 4.8.1.
WDT
Period
4.6 sec
1.15 sec
18 ms
65536 Tcy
Fuses FWDT1 abd FWDTO are mapped in program
memory locations FE03h and FE02h respectively. See
section 4.8 for details on how to program fuses.
Reading configuration fuses: Reading any fuse location
in the address range FEOO:FE07h will read all eight fuse
values in the lower by1e and all 1's in the upper byte.
Fuse located at FEOOh will show up in bit 0 and so on.
The fuse locations are accessible only in microcontroller
and secure microcontroller modes. In microprocessor
and extended microcontroller modes, this section of the
program memory is mapped external (see figure 1.5.2)
making the fuse locations inaccessible.
The watchdog timer and its prescaler are reset and the
time-out bit, TO (bit3, CPUSTA) set to '1' if:
a. A CLRWDT instruction is executed.
b. A SLEEP instruction is executed.
c. A power on reset occurs.
Under normal circumstances, the user program is expected to clear the watchdog timer on a regular interval.
If the program fails to do so, the WDT will overflow and
reset the chip. The watchdog timer and its prescaler are
physically the same as the power-up timer (PWRT).
They simply perforrn different roles in and outside reset
condition.
TABLE 4.8.1: CONFIGURATION FUSES
4.6.1 WOT as a Regular Timer
Setting fuses FWDT1 and FWDTO as O's will configure
the WDT as a simple timer. In this mode the tirner
increments on internal OSC/4 clock with a prescale of
256 (Le. increments at OSC freq/1 024 rate). On overflow
TO bit is cleared, but the chip is not reset. hthis mode
the WDT is stopped during SLEEP. The TO bit is set
when a CLRWDT instruction is executed.
4.7 CODE PROTECTION AND WRITE
PROTECTION
Fuse
Address
FOSCO
FOSCI
FEOOh
FOSC1, FOSCO:
FEOlh
00
01
10
11
FWDTO
FWDT1
FE02h
FE03h
FWDT1, FWDTO :
FPMMO
FE04h
FE06h
FPMMI
The code in the user EPROM may be protected from
piracy by selecting "code protected Microcontroller
mode." This is done by blowing fuses FPMM1 and
FPMMO to "0". A TABLRD instruction, executed from the
test EPROM attempting to read user EPROM will read
encrypted data. However, if the instruction is executed
from an address less than 2K (i.e. from user EPROM),
it will read un-encrypted data.
Function
: LP oscillator mode
: RC oscillator mode
: XT oscillator mode
: EC (external clock mode)
10 : WDT prescale is 256
01 : WDT prescale is 64
11 : WDT prescale is 1
00 : WDT is a normal timer
FPMM1, FPMMO:
00
10
01
11
: Microcontroller mode (code protected)
: Microcontroller mode
: Extended microcontroller mode
: Microprocessor mode
FIGURE 4.8.1: REAOING FUSE LOCATION
Address FEOO:FEO?h
1
o
Further, any TABL WT instruction executed from the test
EPROM and attempting to write to the user EPROM, will
I FPMMO I FWDTI I FWDTO I FOSCI I FOSCO I
I FPMMI I
bit?
bitO
lill
DS300738-page 34
1-202
I
bitS
bil15
© 1992 Microchip Technology Inc.
5.0 OVERVIEW OF PERIPHERALS
5.1 THE BANK SELECT REGISTER
(BSR, ADDRESS OFh)
An array of sophisticated, high speed peripherals are
incorporated on chip to meet the demands of real time
applications. All peripherals are highly intelligent and
have their own interrupts and error handling to free up
the CPU as much as possible. There are three 16 bit
timer/counters one of which can be split into two eight bit
timers creating up to four timer/counter resources. Two
high speed captures are provided for efficient interface
to shaft encoders and other high speed pulse train
sources. Two high speed pulse-width-modulation (PWM)
outputs with up to 10 bit resolution make it possible to
control a motor through power drivers. There are two
external and several internal interrupt sources. The
capture pins can be used as interrupt pins making it
possible to have up to four external interrupts. Finally,
there are 33110 pins most of which can be configured as
inputs or outputs in software. A number of the I/O pins
are multiplexed with peripheral functions or the system
bus. In microcontroller mode 23 I/O pin are un-multiplexed.
All the peripheral registers are mapped into the data
memory space. In order to accommodate the large
number of registers in the 256 by1e data memory space
without taking away from the general purpose data
RAM, a banking scheme has been used. A segment of
the data memory, from address 10h to address 17h, is
banked. A bank select register (BSR, address OFh)
selects the currently active "peripheral bank". Effort has
been made to group the peripheral registers of related
functionality in one bank. However, it will still be necessary to switch from bank to bank in order to address all
peripherals related to a single task. To alleviate this
problem, a single cycle instruction, MOVLB (move literal
value to BSR) is incorporated in the instruction set. In the
PIC17C42 only the low four bits of the BSR are physically implemented, making it possible to address up to
sixteen banks. Only four banks are actually used (see
data memory map in figure 1.6.1).
liL
© 1992 Microchip Technology Inc.
1-203
DS300738-page 35
FIGURE 6.0.1: 110 PORT READ AND WRITE
TIMING
6.0 DIGITAL 1/0 PORTS
~.I
'.• .
ir
I
The PIC17C42 has five ports A, B, C, D and E. Together
these add up to 33 port pins. Most port pins have an
associated data direction bit which configures it as input
(DDR bit='1 ') or output (DDR bit='O'). When a port pin is
read as an input, the value on the pin (and not the data
latch) is read.
10/1021031041011021031041011021031041
I
I
I
I
AO <15:0>
Most port pins are multiplexed with the system bus or
peripheral functions. These pins are configured as port
pins or peripheral inputs/outputs by control bits in corresponding peripheral registers. Once a port pin is selectedfor an alternate function, it's direction will be
determined by the peripheral logic which will force the
DDR bit to the required state.
Instruction
fetched
ALE
{I
I
MOVWF PORTA MOVPF PORTA. ~
I
I
PORTA:~~~t
PortsA, B, C, D and E and their associated DDR registers
are mapped into the data-memory. Ports C, D and E
multiplex with the system bus (AD <15:0>, ALE, WR and
OE).
WR_PORTA
~~~~~~~~~~~~I
RD]ORTA
~--~----~I~~
I'
I
Port pin
I
I Sampled
here
lexecute MOVWF I execute MOVPF I
PORTA
PORTA,W
Read port A
6.1 PORT A
I Write to port A I
File 10h in Bank 0 is PORTA, a 6 bit port. There is no
Data Direction Register associated with this port. Port A
is multiplexed with peripheral functions as described in
table 6.1.1. See figure 6.1.1 for block diagram of Port A
and 6.0.1 for read/write timing.
I
The example shows a write to PORTA followed by a read from PORT A
TABLE 6.1.1 : PORT A FUNCTIONS
Port Pin
Bit
Pin function
Alternate function
RAO/INT
bit 0
Input only (Schmitt Trigger) port pin
INT external interrupt input
RA1/RT
bit 1
Input only (Schmitt Trigger) port pin
RT external interrupt input. It is also the
external clock input for the RTCC timer/counter.
RA2, RA3
bit 2,3
Input/output pins with Schmitt Trigger input and opendrain output.
To use either of these two pins as an input, the user must
write a '1' to the port data latch. If used as an output,
external pull-up resistor must be provided. These pins
can be pulled up to voltages higher than Vee.
Also, these two port pins provide higher current sink
capability (See DC specs for details).
None
RA4/RXIDT
bit4
Input only (Schmitt Trigger) port pin
If the SPEN bit (bit?, RCSTA) is a '1' then this
pin is configured by the serial port.
In SYNC mode: It is data input or output (DT)
In ASYNC mode: It is receive data input (RX).
RAS/TXlCK
bitS
Input only (Schmitt Trigger) port pin
If the SPEN (bit?, RCSTA) bit is a '1' then this pin
is controlled by the serial port.
In SYNC mode: It is either clock input (slave mode)
or the clock output (master mode) in ASYNC mode:
It is the transmit data output (TX).
bit 6
This bit is unimplemented and reads as '0'.
bit?
No pin associated
This is a control bit (PUEB) for Port B. No port pin
is associated with this bit. PUEB=O enables weak
pull-ups on Port B.
DS300?3B-page 36
© 1992 Microchip Technology Inc.
1-204
FIGURE 6.1.18
6.1.1 Using RA2, RA3 Pins as Output
PortA does not have an associated data direction register. When using them as outputs, read-modify-write
instructions (such as BCF, BSF, BTF) are not recommended on PortA, since a read will read the port pins but
a write will write to the port data latch. Such an operation
may inadvertantly cause RA2, RA3 to switch from
output to input or vice-versa.
DATA BUS
RD PORTA
(Q2)
Port pins RA2, RA3
FIGURE 6.1.1: PORT A BLOCK
DIAGRAMS
FIGURE 6.1.1C
SERIAL PORT
INPUT SIGNALS
FIGURE 6.1.1A
DATA BUS
DATA BUS
AD PORTA
-
(Q2)
Serial port output signals
Port pins RAO, RA 1
OE = SPEN.SYNC.TXEN.CREN.SREN for RM
OE = SPEN (SYNC+SYNC.CSRC) for RA5
Port pins AA4, RA5
6.1.2 SUMMARY OF PORT A REGISTERS
Register Name
Function
~
PORTA
Port A pins when read, Port A latch when written
(RA2/RA3 only)
RTCC status/control register (configures RAO/INT
& RA1/RT pins)
Serial port receive status/control register (configures
RA4/RXIDT and RA5/TXlCK pins)
Bank 0, File10h
RTCSTA
RCSTA
6.2 PORT B
Reset Value
OOXXXXXb
File 05h
OOOOOOOb
BankO, File 13h
OOOOOOXb
Port B also has an "interrupt on change" feature. When
configured as input, its output data latch can be used as
a compare latch. An active high output is generated on
mismatch between the pin and the latch. The "mismatch" outputs of all the input pins are OR-ed together
to generate the IRB interrupt. All the output pins are
excluded from the comparison. Thus, an interrupt is
generated when the port input changes. This interrupt
can wake the chip up from SLEEP mode.
Port B is an eight bit wide bidirectional port. It is mapped
in BankO, File 12h. Writing to this address writes to the
port latch while reading it will read the port pins. An eight
bit data direction register (DDRB, Bank 0, File 11 h)
configures each port pin as an input or output. A '0' in the
'DDR' register configures the port as an output. Each
port pin also has a software configurable weak pull-up
(-100 IlA typical). A control bit PUEB (bit 7, Bank 0, File
10h, Register PORTA) can enable (PUEB = '0') or
disable (PUEB = '1') the pUll-Ups. The weak pull-up is
turned off for any pin configured as output.
The interrupt is latched in the IRBbit (bit 7, Register PIR,
Bank1, File 16h). IRB is readable and writable by the
CPU. The user, in the interrupt service routine, can clear
the interrupt in one of two ways:
a) Disable the interrupt by clearing the corresponding
interrupt enable bit, IEB.
b) Read PortB and write back the pin value to the data
latch. This will end mismatch condition and therefore the mismatch output. Next, the user must clear
bit IRB.
Most of the pins of Port B are multiplexed with peripheral
functions. Table 6.2.1 describes their alternate functions. When a pin is redefined to be a port pin from a
peripheral pin, its data direction bit may be left in an
unknown state. The user will need to re-initialize the
DDR bit properly. See figures 6.2.1 and 6.2.2 for block
diagrams of port B and figure 6.0.1 for read/write timing.
© 1992 Microchip Technology Inc.
DS30073B-page 37
1-205
TABLE 6.2.1: PORT B FUNCTIONS
Port Pin
Bit
Pin Function
Alternate Function
RBO/CAP1
bit 0
Input/Output port pin with Schmitt Trigger input
CAP1: Capture1 input
RB1/CAP2
bit 1
Input/Output port pin with Schmitt Trigger input
CAP2: Capture2 input
RB2/PWM1
bit 2
Input/Output port pin with Schmitt Trigger input
PWM1 output. This pin is configured as the
PWM1 output if control bit PWM10N (bit 4,
RegisterTCON2, Bank3, File 17h) is setto'1'.
RB3/PWM2
bit 3
Input/Output port pin with Schmitt Trigger input
PWM2 output. This pin is configured as the
PWM2 output if the control bit PWM20N
(bit 5, Register TCON2, Bank 3, File 17h) is
'1 '
RB4ITCLK12
bit 4
Input/Output port pin with Schmitt Trigger input
TCLK12: external clock input for timer1 and
timer2
RB5ITCLK3
bit 5
Input/Output port pin with Schmitt Trigger input
TCLK3: external clock input for timer3
RB6
bit6
Input/Output port pin with Schmitt Trigger input
RB7
bit 7
Input/Output port pin with Schmitt Trigger input
FIGURE 6.2.1: PORT B BLOCK DIAGRAM
Peripheral data in
PUES
I -
I
I
I
-
-
-
-
-
-
-
_(~jtJ ~R~llLs1l>rP.98T.iI\
Match Signal
froml?ther
port pms
I
I
IRS
Port
1 __________________
I
J
Input Latch
Data Bus
OE
~--+-------------~~----~~Q
\CKrJ'9BTl-\
Match Signal
I
fromC?ther
1
portpms
I
I
I
I
IRB
I
I ___________________ J
Data Bus
OE
~----_1----------~~~_4Q
WR_DDRB (04)
A~ CK, the lower byte of the
Address/Data bus. Bit 0 of Port C is AD. See figure
6.3.1 for block diagram of Port C and figure 6.0.1 for
read/write timing.
Port C is an eight bit wide bidirection port mapped in File
11 h, Bank 1. The corresponding data direction register
DDRC (file 10h, Bank 1) can configure each pin as an
6.3.1 SUMMARY OF PORT C REGISTERS
Rl;!giSl!i!rN!!ml;!
PORTC
~
Function
Port C pins when read
Port C latch when written
Bank 1, File 11h
Rl;!set Value
XXXXXXXXb
DDRC
Port C data direction register
Bank 1, File 10h
111 11 11lb
INTSTA (bit PEIE)
Interrupt status register
File 07h
OOOOOOOOb
CPUSTA (bit GLiNTD)
CPU status register
File 06h
OOl1XXOOb
© 1992 Microchip Technology Inc.
Pn'))i] ~ lru]~ r(~,,1i~'}f ~ WO~(imT~II:d~[i))lIu
1-207
DS30073B-page 39
FIGURE 6.3.1: BLOCK DIAGRAM OF PORTS C, D AND E
INSTRUCTION READ
(not present in Port E)
Data Bus
D~~-----------------;
~CK, the higher byte of the
Address/Data bus. Bit 0 of Port D is AD<8>. See figure
6.3.1 for block diagram of Port C and figure 6.0.1 for
read/write timing.
PORTE is a 3 bit wide bidirectional port mapped in data
memory (file 1Sh, Bank1). The corresponding Data
Direction Register, DDRE, is mapped at file 14h, Bank 1.
Each port pin can be configured as an input (DDRE bit
= '1') or an output (DDRE bit = '0'). Only the three lowest
significant bits are physically implemented in 17C42.
The unimplemented bits read as '0'. See Figure 6.3.1 for
block diagram of Port E and Figure 6.0.1 for read/write
timing. Port E is multiplexed with control outputs ALE,
WR and OE in external execution mode.
FIGURE 6.4.1: SUMMARY OF PORT D REGISTERS
Register Name
PORTD
DDRD
DS30073B-page 40
Function
Add.rUJ.
Port D pins when read
Port D latch when written
Port D data direction register
XXXXXXXXb
Bank 1, File 12h
ll111111b
IPlr(l1~~ WI i Irllti\lf"jf I WII~:(i'))niTjH'U\,I!«)ilrL
1-208
Reset Valye
Bank 1, File 13h
© 1992 Microchip Technology Inc.
6.5.1 SUMMARY OF PORT E REGISTERS
Register Name
PORTE
Function
Port E pins when read
Port E latch when written
Bank 1, File1Sh
Reset Value
OOOOOXXXb
DDRE
Port E data direction register
Bank 1, File14h
OOOOOlllb
~
TABLE 6.5.1 PORT E FUNCTIONS
Port Pin
Bit
Pin Function
Once asynchronous mode is selected (SYNC=O, bit 4
Register TXSTA) and serial port outputs are enabled
(SPEN=l, bit 7, Register RCSTA) transmission can be
enabled by setting TXEN billo '1 ' (bit 5, TXSTA register).
Actual transmission will begin when a word is written to
the transmit buffer register (TXREG, bankO, file 16h) and
the Baud Rate Generator produces a shift clock (figure
7.1.1.1). A start bit is sent out first (logic '0'), followed by
80r9 data bits and a stop bit (logic '1'). Transmitted data
appears on RASITx/CK pin. Transmission can also be
started by first writing a word to the TXREG and then
setting TXEN to '1'.
System Bus Function
(External execution)
ALE output
REO/ALE bit 0 InpuVoutput port.
TTL input buffer.
bit 1 InpuVoutput port.
TTL input buffer.
OE output
RE2IWR bit 2 InpuVoutput port.
TTL input buffer.
WRoutput
RE1/OE
7.1.1 Asynchronous Mode Transmission
7.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The transmit register (TXREG) is double buffered. As
the user writes to TXREG, the data is transferred from
the buffer to the transmit shift register (TSR), thus
freeing up the buffer register. An interrupt is pending as
long as TXREG is empty. Indicating that the transmit
buffer register (TXREG) is free to accept another word.
This interrupt request is bit 1 (TBMT) of PIR (peripheral
interrupt request register; Bank 1, file 16h) register. This
interrupt can be enabled or disabled by bit 1 (TXIE) of
PIE (peripheral interrupt enable; Bank 1, file 17h) register. TXIE=l enables the interrupt. Regardless of TXIE,
the TBMT bit will always show the status of the TXREG
buffer (can not be affected in software) and can be used
as a status bit. The interrupt request bit (TBMT) is read
only. Therefore, to avoid unwanted interrupts (say, at the
end of a transmission) the user will need to mask off this
interrupt.
The serial port can operate either a full-duplex asynchronous mode or in a half-duplex clocked synchronous
mode. Synchronous mode uses a bi-directional data pin
and a bi-directional clock pin. In synchronous mode, the
clock can be either internal (master mode) or external
(slave mode). In asynchronous mode, the clock is
always derived internally. A dedicated 8 bit Baud Rate
Generator (BRG) is used for internal clock generation. In
both modes, receiver and transmitter are double buffered, 8 or 9 data bits are supported and separate
transmit and receive interrupts are available.
7.1 ASYNCHRONOUS MODE
The asynchronous mode is selected by setting the
SYNC bit to 'a' in the TXSTA register. Furthermore,
SPEN bit (Serial Port Enable, bit 7, Register RCSTA,
Bank 0) has to be set to enable RA4 and RA5 as serial
port pins. SPEN=O will configure these pins as port pins.
In asynchronous mode the RX pin receives data and the
TX pin transmits data in a full duplex mode. Data is
transmitted and received least significant bit first. Both
receive and transmit operate on the same internally
generated clock which is derived from the Baud Rate
Generator (Register SPBRG, Bank 0, File 17h). Data on
the RX pin is sampled on the 7th, 8th and 9th pulses of
a 16X (16 times the baud clock) internal clock. A majority
of these three bits decide whether a one or a zero was
received. In addition to the 8 or 9 data bits, one start bit
and one stop bit are sent. Parity is not supported directly
in hardware, but can easily be implemented in software.
Asynchronous mode operation is stopped during SLEEP.
In addition to TXIE bit, two other bits will affect the
transmit interrupt. They are: PEIE (bit3, INTSTA register, file 07h) that enables (if='l ') or disables (if='O') all
peripheral interrupts, and GLlNTD (Global Interrupt Disable, bit 4, CPUSTA register, file 06h) billhatdisables all
interrupts if set to '1'.
While TBMT (Transmit Buffer Empty) indicates the .status olthe transmit buffer register, another bitTRMT (bitl,
register TXSTA) indicates the status of the transmit shift
register. It is a read only bit. TRMT =1 implies transmit
shift register is empty. The user can determine exactly
when transmission is completed by polling this bit.
TRMT is set after stop bit is sent out.
CREN or SREN bits do not affect asynchronous transmission. Clearing TXEN during transmission aborts
transmission, reverts TX pin to hi-impedance and resets
the transmitter.
DS30073B-page 41
© 1992 Microchip Technology Inc.
1-209
FIGURE 7.1.1.1: ASYNCHRONOUS TRANSMISSION
~
l
,
I,'
1,
n
Write to TXREG
BRG output -----"1
(shift clock)
~--------------~SS~---------------Write
Word 1
n
TX (pin)
~
nL---~~s--nL---~n
n
1
1
1
rL---~~
1
1
Start Bit
'..-
A
Bit 0
X
Bit 7/8
7
STOP BIT :
~
1
1
1
TBMTbit
(Transmit buffer
reg. empty flag)
1
r---------------~»~~---------------
LJ
~
WORDt
__
Transmit Shift Reg
TRMTbit
(Transmit shift
reg. empty flag)
~--------------~ss~--------~
FIGURE 7.1.1.2: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
~-----------4S5~--------------------
Write to TXREG - - - - - - - - d
BRG output
(shift clock)
TX (pin) --------I.,,"--'s""o""rt"'BI''--./''---''BI!!..!'O,--./,----"BI,,-,'l,--/,---, r-'''---:B=-I'::C7/So---r-:S=TQ=P:C:B=IT--- START BIT
Bit 0
TBMT bit
1 11""'
..
WORD 1 ---:~-------....~I..
!:=~WO~R~D'!.2======
(interrupt reg. - - - - - - - , L . - - - J I - - - - - - - - - - - I S C I - - - - - - - - - - - li
-,
TRMT bit
),
1--------
WORD 1 - -
(Transmit shift
WORD 2--
Transmit Shift Reg
reg.
emptyfleg)
Transmit Shift Reg
~--------------~S5~--------------------Note: This timing diagram shows two consecutive transmissions
If 9 bit transmission 'is selected (TX8/9= 1, bit 6, register
TXSTA) the 9th bit should be written to TXD8 (bitO,
TXSTA). This bit is double buffered as well. The 9th bit
must be written before writing the data word to TXREG,
since the latter triggers the transfer of the entire word to
the transmit shift register.
is lost (I.e. it can not be read). The RCREG can be read
twice to retrieve the first two words. The user will need
to clear OERR by resetting the receiver (by clearing
CREN). Clearing OERR is essential since once the
overflow flag is set, the receiver simply stops transferring
RSR to RCREG.
7.1.2 Asynchronous Mode Reception
The framing error bit, FERR (bit 2, Register RCSTA) and
the 9th receive bit, RCD8 (bit 0, RCSTA) are buffered the
same way as the receive data. Reading RCREG will
load the RCD8 and FERR bits with new values. The
user, therefore, must read the RCSTA register before
reading the received data (RCREG) in order to obtain
FERR and 9th data bit information. If the RCREG is read
first, then the status register RCSTA will be loaded with
new status information and the old information will be
lost. The framing error bit, FERR, is set if the stop bit is
detected to be a '0'.
Data is received on RA4/RXlDT pin. Reception is enabled by setting the CREN bit (bit4, register RCSTA) to
'1'. The SREN bit (bitS, RCSTA) has no function in
asynchronous mode. Reception begins when a start-bit
is detected on RX pin. The Baud Rate Generator internally generates a 16x clock. Every incoming bit is
sampled on the 7th, 8th and the 9th time slot and a
majority detection is done to determine the value of the
bit. After sampling the stop bit (I.e. halfway through stop
bit), the received data is transferred to the receive buffer
register (RCREG) if the buffer register is empty. The
RCREG is actually a two word deep FIFO. Therefore, it
is possible to receive two words, transfer them to RCREG
and begin receiving the 3rd word in the receive shift
register (RSR).lf at the time of reception of the last bit of
the 3rd word, the RCREG has still not been read (and
therefore is holding two words) then the receiver control
logic will set the overrun error bit, OERR (bit1, register
RCREG). In case of overrun, the word in the shift register
A receive interrupt flag RBFL, is set (bitO, register PIR)
when the receive shift register content is shifted to the
receive buffer register. This interrupt can be enabled or
disabled via the RCIE (Receive interrupt enable) bit
(bitO, register PIE). RCIE=1 will enable the interrupt. The
RBFL (receive buffer full interrupt flag) bit is a read only
bit and is cleared when the receive buffer is read.
However, if the receive shift register is full, it will transfer
its contents to the receive buffer register and the RBFL
© 1992 Microchip Technology Inc.
DS30073B·page 42
1·210
FIGURE 7.1.2.1: ASYNCHRONOUS RECEPTION
RX (pin)
Rev shift
regRev buffer reg
Read Rev
buffer reg
(RCSTA)
- - - - - - - - - c i------T-------~
WOAD 1__
RCREG
------------
,.~.------
---------T------
---------c---------
WORD 2 __
RCREG
- - - - - - , - . - - - - - - - - - - - - - - - - - - - - -..----
RBFL bit
(interrupt flag)
OERR bit
CREN
Note:
This timing diagram shows 3 words appear on RX input. The RCREG (Receive buffer) is read after the 3rd word, therefore causing the OERR
(overrun) bit to set.
The TBMT interrupt (bit1, PIR register) is pending whenever the transmit buffer is empty and ready to accept
another word. The interrupt has a corresponding mask
bit (TXIE, bit1, Register PIE). TXIE='1' enables the
transmit interrupt while TXIE='O' disables it. Regardless
of TXIE, TBMTwili always show the status ofthe TXREG
(not affected by software) and can be used as a status bit.
To enable the transmit interrupt, Peripheral Interrupt
Enable, PEIE (bit3, INTSTA register, file 07h) bit must be
set and Global Interrupt Disable, GLlNTD (bit4, CPUSTA
register, file 06h) bit must be cleared.
bit will be set again. To enable receive interrupt, the
Peripheral Interrupt Enable bit, PEIE (bit3, INTSTA
register, file 07h). must be set and the Global Interrupt
Disable bit, GLlNTD (bit4, CPUSTA register, file OSh),
must be cleared.
7.2 SYNCHRONOUS MODE
The synchronous mode is selected by setting the SYNC
bit (bit4, TXSTA register) to a '1 '. In addition, the SPEN
bit (bit7, RCST A register) must be setto a '1' to configure
the RA5/TX/CK and RA4/RXlDT pins as CK (synchronous clock) and DT (sync data) pins respectively. Synchronous mode is half duplex with the DT pin as data
input during reception and data output during transmission. The CK pin is clock output if internal clock option
(master mode) is selected by setting the CSRC (bit7,
TXST A register) bit to a '1'. If CSRC='O' then the CK pin
is clock input (synchronous slave mode).
While TBMT (Transmit Buffer Empty) indicates the status
of the transmit buffer register, another bit TRMT (bit1,
register TXSTA), indicates the status of the transmit shift
register. It is a read only status bit. TRMT=1 implies that
the transmit shift register is empty. The user can determine exactly when transmission is over by polling this bit.
TRMT is set after the last bit is sent out.
If 9 bit transmission is selected, the 9th bit should be
written to bit TXDB (bitO, TXSTA). This bit is also double
buffered. The 9th bit must be written prior to writing the
data word to TXREG, since a write to the TXREG triggers
the transfer of the entire word to the transmit shift
register.
As in asynchronous mode, B or 9 data bits are transmitted or received. No start or stop bits are sent or received.
7.2.1 Synchronous Mode Transmission
Once the sync mode is selected (SYNC='1') and the
serial port is enabled (SPEN='1', register RCSTA),
transmission is enabled by setting the TXEN (transmit
enable, bit5, TXSTA register) bit to a '1'. This will
configure the TX pin as an output. Actual transmission
will begin when a word is written to the transmit buffer
register (TXREG). The transmitter is double buffered. If
the transmit shift register (TSR) is empty then the word
will be transferred from TXREG to TSR. The first data bit
will be shifted out at the next available rising edge of the
clock. Data out is stable around the falling edge of the
sync clock. Transmission can also be started by first
writing adata word to TXREG and then setting TXEN='1 '.
This method may be advantageous when slow baud
rates are selected, since the Baud Rate Generator is
kept under reset when TXEN=CREN=SREN=O. Setting
the TXEN bit will start the BRG, creating a shift clock
immediately.
In sync master mode, the CK pin will output clocks only
during actual transmission (figure 7.2.1.1). In sync slave
mode clock input may be present on the pin at all times.
If TXEN is cleared during transmission of a word, transmission will be aborted and the DT and CK pins will revert
to hi-impedance. If eitherthe CREN orthe SREN bit is set
to a '1', transmission is also aborted and the DT pin will
go into hi-impedance state (for reception). The CK pin will
remain an output if CSRC=1 (internal clock). The transmitter logic, although disconnected from the pins, is not
reset. The user must clear the TXEN bit to reset the
transmitter. This is particularly important ifthe SREN was
set to a '1' to interrupt an ongoing transmission. In this
case, after reception of a single word, the SREN bit will
reset and the serial port will revert back to transmit mode
(since TXEN is still set). This means the DT pin will turn
around and start driving. To avoid this, TXEN should be
cleared.
© 1992 Microchip Technology Inc.
DS30073B-page 43
1-211
FIGURE 7.2.1.1: SYNCHRONOUS TRANSMISSION
DT pin
===±==X::±~O<±~=><±JiBiUit2=>C] CX::!JiiLCX::!Jii!:LX2::mLCX:r==x::=socJs_it_,__I
cKPln _ _ _ _ _
I
Wdteto
TXREG _ _11
~LJ15.
1
Writewordl
1
nl
, ,
~!
1
1
S5r-------------:-----ISjI------
Write word 2
(Interru;t~~~) ~c-I--+-----\S'f--f------' - , - - , - - - - - - , - - - - \ 5 5 1 - - - - - TRMT
~'---LI-----L---'----'-----\SSr---+----I---I-----+----\5S~1
TXEN _'1_'- - - - - - - - - - - - - - - - 1 5 5 , - - - - ' - - - - ' - - - - - - ' - - - - - - - - \ 5 5 - -1
-'----'1'1
Note: Sync master mode; BRG == O. Continuous transmission of two 8 bit words
FIGURE 7.2.1.2: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT pin -------<====><--=S",""~o--./"-_-,,SO'-Itl,--/,--""SI,,,t2~",--"S",-it3~-A,--=S"'i14'---/'_-""SI'_'"5-,--",-""S",,"-,,-6--./,----,S",I'-,--7_ _
CK pin _ _ _~_:--_--.J
Write to
~REG
~L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TXEN
_ _ _---'
TBMT
(Interrupt flag)
~'--_ _ _ __
~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
TRMT
Note: Sync master mode tran$mis$ion, BAG = O. Transmission started by TXEN to '1' with data word already waiting in TXREG.
After a word is received completely, it is transferred from
the receive shift register (RSR) to the receive buffer
register (RCREG) thus freeing up the RSR to receive the
next word, With CREN=l, it is possible to receive consecutive data words without any discontinuity in between. This makes it possible to receive data words of
larger size, e,g. 16 bit. In synchronous slave mode the
SREN bit is a don't care,
FIGURE 7.2.1.3: SYNCHRONOUS TRANSMISSION (SLAVE)
DTpjn~~~
CKPIO _ _ /\~~
f;~~~ JL---------55------iT BMTbit
,-------Ij\-:-------
-~
The RCREG is actually a two word deep FIFO, Therefore, it is possible to receive two words, transfer them to
RCREG and begin receiving the 3rd word in the receive
shift register (RSR), If, at the time of reception of the last
bit of the 3rd word, the RCREG has still not been read
(and therefore is holding two words) then the receiver
control logic will set the overrun error bit, OERR (bitl,
register RCSTA), In case of an overrun, the word in the
shift register is lost (I.e, it can not be read). The RCREG
can be read twice to retrieve the first two words. The user
will need to clear OERR by resetting the receiver (by
clearing CREN). Clearing OERR is essential since once
overflow flag is set the receiver simply stops transferring
RSR to RCREG.
II TRMTbit -L'----,.---~S--~,-----'
7.2.2 Synchronous Mode Reception
Data is sampled on the DT pin on the falling edge of the
clock, Reception is enabled by either setting the SREN
bit (Single Receive Enable, bitS, RCSTA register) or the
CREN bit (Continuous Receive Enable, bit4, RCSTA
register). If SREN is set, one word is received after
which SREN is reset in haraware, If the CREN bit is set,
words are received continuously (and read off by the
CPU presumably) until CREN is reset by software. If
both CREN and SREN are set, then CREN will ta.ke
precedence.
DS30073B-page 44
If'
© 1992 Microchip Technology Inc.
1-212
FIGURE 7.2.2.1 : SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
•
1
I
I
I
I
1
1
I
I
!
I
DTpin====~====~~~=~~Bil:27===~======
CKpin
Write to
SREN bit
SRENbit
I
---+-----'Ijl-flLJ~~----+--~
--U~--~-~~I----~I---+--~----~I---+--~----+----
_I
I
CREN bit --,'0,--'_ , -_ _--,-_ _- ,_ _ _,--_ _-r-_ _ _ _, -_ _, -_ _-,-_ _ _, -_ _---r-_ _ _
'O'
I
RBFL bit
(interrupt)
,(l----j
Read _ _L -_ _
RXREG
~
__
~
___
~
__
~
_ _ _L -_ _
Note: Timing diagram demonstrates SYNC master mode with SREN
=
An interrupt is issued when RSR transfers a data word
to receive buffer register, RCREG, indicating that RCREG
is full. The interrupt flag (RBFL, bitO, register PIR) can be
masked by interrupt mask bit RCIE (Receive interrupt
enable, bitO, register PIE). RCIE;1 enables the receive
interrupt.
~_~~~
___
~
__
~
_L~
1 and BRG '" O.
SLEEP/sync slave transmit: If two words are written to
TXREG and then the chip is put into SLEEP the
following sequence of events will occur. The first word
will immediately transfer to the TSR. The second word
will remain in TXREG. Transmit interrupt (TBMT) will
stay inactive (low). As the first word is shifted out, the
second word will transfer from TXREG to TSR and the
transmit interrupt (TBMT) will be raised again. This will
wake up the chip provided the interrupt was not masked
(i.e. TXIE ; PEIE ; '1 '). If GLlNTD ; 0, then branch to
interrupt vector 0020h will take place as well.
The 9th bit of the received word is loaded into RCD8
(bitO, RCSTA). This bit is buffered the same way as the
receive data. Reading the RCREG register will load the
new 9th bit. Therefore, the user must read the RCST A
register before reading the received data word from
RCREG.
7.3 BAUD RATE GENERATOR
The serial port is equipped with a dedicated 8 bit Baud
Rate Generator (SPBRG, bankO, file 17h). The SPBRG
register is readable and writable. The SPBRG register
controls the period of a free running 8 bit timer. In
synchronous mode the baud rate is fosc/4(x+ 1) where
fosc ; oscillator or clock-in frequency and x ; value
written to SPBRG register. In asynchronous mode the
baud rate is fosc/64(x+ 1). Tables 7.3.1 and 7.3.2 show
baud rate values for different SPBRG value and clockin frequency. SPBRG is unknown following power-on
reset.
7.2.3 Synchronous Slave Mode/SLEEP Mode
Interaction:
When the part is put into SLEEP mode, all on chip phase
clocks are stopped (part is held in 01 state; see SLEEP
section for details). In SLEEP, synchronous slave mode
operation is possible because this mode uses external
clock.
SLEEPlsync slave receive: If receive is enabled (SREN
; '1 ') priorto invoking SLEEP mode, then a word may be
received during SLEEP and at the completion of such
reception the RSR will be transferred to RCREG (assuming it is empty). Simultaneously a receive interrupt
will be generated which will wake the chip up, provided
this interrupt was enabled (by setting RCIE; PEIE;' 1').
If GLlNTD ; '0', then additionally the interrupt will be
responded to by jumping to interrupt vector 0020h. If the
receive interrupt is disabled, prior to invoking SLEEP
mode, then words are received during SLEEP without
waking up the processor. Overflow bit will be set if three
words are received.
Writing a value to the SPBRG clears the timer. This
guarantees that the timer does not go through an overflow cycle, before outputting the appropriate baud rate.
© 1992 Microchip Technology Inc.
DS30073B-page 45
1-213
o.....
"tJ
~
C::l
@)
lD
~
.......
o
CD
g;
FIGURE 7.2.2.2: SYNCHRONOUS MASTER MODE RECEPTION, CREN
~
N
I
DTpin
CKpin
~
I
B~l
02 Q3 Q4
I
\
I~ I
WORD 1
~
I
01 02 03 Q4 01
01 02 03 Q4 01 02 Q3 04
03 Q4 01 02 03 Q4 01 02 03 04
~
Bil?
,....,....,
-L-..j
I
B.O
~
~ORD:3~~----I '--...J I L-J~
I,.....,.....,
L-....J
01 Q2 Q3 04 01 02 030401 0203 04
<:::':1
9
©
~
~
~,
c:~i~~~ ~
CREN
~ I
~
9
-;"~
SREN
~
.jl>.
~~
RBFLbit
(interrupt)
'0'
I
55
S5
I 55
S5
S5
S5
:
:
:
I
S5 :
9,L----S5
,LI)_ _ _ __
S'I-!- - - - - 1 - - + - - - - - '0'
-r----r---,-~Ss___J
55
S<,
t---f----r----I55
55
S\
'8'
9
=;
~
~
::===.?
'.Q'
~
Read
RCREG
Rev Shift Reg
--RCREG
CERR
-'------'------L-----Iss---rl
-----'-----155
I
55
55
I
n
I
\
!
S))-----'-----+I----
SP
I I'-- - - -
@
~
(0
(0
I\)
s::
O·
~
"5'
~
:::T
~
Q.
c8
'<
:;f>
Note:
Synchronous master mode reception with CREN. Overflow occurs after two words have been received and reception of the 3rd
word is almost complete. Resetting CREN resets the receiver, including the OERR bit. The two words are read which then clears
the RBFL flag. The 3rd word is lost.
TABLE 7.3.1: BAUD RATES FOR SYNCHRONOUS MODE
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
SOO
HIGH
LOW
lasc= 20MHZ
SPBRG
16MHZ
SPBRG
KBAUD
%ERROR (decimal)
value
KBAUD
NA
NA
NA
NA
19.53
76.92
96.15
294.1
SOO
%ERROR (decimal)
+1.73
+0.16
+0.16
-1.96
0
5000
19.53
losc
255
64
51
16
9
0
255
=5.0688MHZ
KBAUD
NA
NA
NA
9.6
19.2
79.2
97.48
316.8
NA
1267
4.950
SPBRG
value
%ERROR (decimal)
0
0
+3.13
+1.54
+5.60
131
65
15
12
3
0
255
10MHZ
SPBRG
KBAUD
%ERROR (decimal)
value
NA
NA
NA
NA
19.23
76.92
95.24
307.69
500
4000
15.625
+0.16
+0.16
-0.79
+2.56
0
207
51
41
12
7
0
255
3.579545MHZ
KBAUD
NA
NA
NA
9.622
19.04
74.57
99.43
298.3
NA
894.9
3.496
SPBRG
value
%ERROR (decimal)
+0.23
-0.83
-2.90
+3.57
-0.57
92
46
11
8
2
0
255
7.15909MHZ
value
NA
NA
NA
9.766
19.23
75.76
96.15
312.5
500
2500
9.766
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
4
0
255
SPBRG
lMHZ
KBAUD
SPBRG
value
%ERROR (decimal)
NA
NA
NA
9.622
19.24
77.82
94.20
298.3
NA
1789.8
6.991
+0.23
+0.23
+1.32
-1.88
-0.57
0
255
32.768KHZ
SPBRG
value
KBAUD
NA
1.202
2.404
9.615
19.24
83.34
NA
NA
NA
250
0.9766
%ERROR (decimal)
+0.16
+0.16
+0.16
+0.16
+8.51
207
103
25
12
2
185
92
22
18
5
value
KBAUD
%ERROR (decimal)
+1.14
-2.48
0.303
1.170
NA
NA
26
6
NA
NA
NA
NA
0
255
NA
8.192
0.032
0
255
TABLE 7.3.2: BAUD RATES FOR ASYNCHRONOUS MODE
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
lasc
=20MHZ
KBAUD
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
312.5
1.221
SPBRG
value
%ERROR (decimal)
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
255
129
32
15
3
2
0
0
255
lose = 5.0688MHZ
KBAUD
0.31
1.2
2.4
9.9
19.8
79.2
NA
NA
NA
79.2
0.3094
SPBRG
value
%ERROR (decimal)
+3.13
0
0
+3.13
+3.13
+3.13
255
65
32
7
3
0
0
255
© 1992 Microchip Technology Inc.
16MHZ
KBAUD
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
SPBRG
value
%ERROR (decimal)
+0.16
+0.16
+0.16
+0.16
+8.51
207
103
25
12
2
0
255
3.579545MHZ
KBAUD
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
SPBRG
value
%ERROR (decimal)
+0.23
-0.83
+1.32
-2.90
-2.90
185
46
22
5
2
0
255
10MHZ
SPBRG
KBAUD
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
%ERROR (decimal)
+0.16
+0.16
+1.73
+1.73
+1.73
129
64
15
7
1
0
255
lMHZ
SPBRG
KBAUD
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.83
0.0610
%ERROR (decimal)
+0.16
+0.16
-6.99
51
12
6
-
0
255
SPBRG
value
KBAUD
%ERROR (decimal)
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
+0.23
-0.83
-2.90
-2.90
92
46
11
5
0
255
32.768KHZ
value
If j) Ir~~ I ~ lfifi ~ Inl ,H\If}f Ii IrIi'WI(j) 1['1i till ,jdiii 1()II! I:
1-215
7.15909MHZ
value
KBAUD
0.256
NA
NA
NA
NA
NA
NA
NA
NA
0.512
0.0020
SPBRG
value
%ERROR (decimal)
-14.67
1
0
255
DS30073B-page 47
7.4. SERIAL PORT REGISTERS
~
.....•
~
7.4.1 Summary of Serial Port Registers
Function
Register Name
RCSTA
RCREG
TXSTA
TXREG
SPBRG
PIR
PIE
INTSTA
CPUSTA
....
~
Reset Value
Bank 0, File 13h
Bank 0, File 14h
Bank 0, File 15h
Bank 0, File 16h
Bank 0, File 17h
Bank 1, File 16h
Bank 1, File 17h
File 07h
File 06h
Receive status/control register
Receive buffer register
Transmit status/control register
Transmit buffer register
Baud Rate Generator
Peripheral interrupt flag register
Peripheral interrupt enable register
Interrupt status register
CPU status register
OOOOOOOXb
XXXXXXXXb
OOOOOOlXb
XXXXXXXXb
XXXXXXXXb
OOOOOOlOb
OOOOOOOOb
OOOOOOOOb
OOllXXOOb
FIGURE 7.4.1.1 RCSTA: RECEIVE STATUS & CONTROL REGISTER
R!W
I
SPEN
R!W
I
RC8I9
RJW
I
SREN
I
RJW
u
R
CREN
I unused I
FERR
R
I
OERR
R
I
R = Read only bit
RJW = Readable and writable bit
RCD8
[
u = Unused, reads as 0
9th bit of receive data
Overrun error bit.
1 = overrun Reset by clearing CREN
Framing !imar bit.
1=framing error
Continuous receive enable bit
In async mode: CREN=1 enables reception
In sync mode: CREN=lenables continuous reception
until CREN is cleared CREN overrides SREN.
Single receive enable (sync mode only). SREN=1 will
enable reception. SREN is cleared after reception is
complete. This bit is don't care in async mode.
RC8/9=1: Selects 9 bit reception.
RC8/9=O: Selects 8 bit reception.
Serial port enable: SPEN=1 configures RA4/RXlDT
and RA5(fXlCK pins as serial port pins.
FIGURE 7.4.1.2 TXSTA: TRANSMIT. STATUS & CONTROL REGISTER
I
RIW
CSRC
RIW
RIW
I
TX8I9
I
TXEN
1
u
RJW
SYNC
j
unused
l
u
unused
R
j
TRMT
I
RIW
TXD8
t
J
R = Read only bit
R!W = Readable and writable bit
U = Unused, reads as 0
9th bit of transmit data
Transmit shift register (TSR) empty
TRMT=1: TSR empty
SYNC= 1: Synchronous mode
SYNC=O: Asynchronous mode
,
TXEN=1 : Transmit enabled
TXEN=O: Transmit disabled
SREN/CREN overrides TXEN
TX8/9=1: Selects 9 bit transmission
TX8I9=O: Selects 8 bit transmission
SYNC mode: CSRC=I: Intemal Clock
CSRC=O: External Clock
ASYNC mode: Don't care.
DS30073B-page 48
rfj ) 1m ~ Illfl1il ~ waU'j'f ~ ~D j/(el) nmll ~~ (DJ ITIl
1-216
© 1992 Microchip Technology-Inc.
7.5 SUMMARY OF SERIAL PORT
PINS
TMR1 <8> TMR2 <8>: These are two 8 bit timer/
counters. They each have an eight bit period register
(PR1 and PR2 respectively) and an interrupt. In counter
mode, their clock comes from pin TCLK12 (shared
between the two timer/counters). They can be configured as a 16 bit timer/counter with interrupt and a 16 bit
period register.
The serial port uses two pins, RA4/RX/DT and RA5ITX/
CK. If SPEN bit (bit 7, RCSTA) is set then these pins are
controlled by the serial port. If SPEN=O, then they are
configured as input only port pins. (Both pins have
Schmitt Trigger input buffer.)
Pin
Name
SPEN
=0
SPEN = 1
SYNC
Master Mode
RA4/RX/DT input only
port pin
SYNC
Slave Mode
RX: Receive
Data output if TXEN=1 and CREN=O
input, Always
hi-impedance
input.
otherwise
port pin
ASYNC
Mode
DT: Data tn/out
and SREN=O, Hi-impedance input
RASITX/CK input only
TMR3 <16>: Timer3 is a 16 bit timer/counter consisting
of two 8 bit sections TMR3H <8> and TMR3L <8>. It has
a 16 bit period register (PR3H <8>, PR3L <8», an
interrupt and an external clock source (pin TCLK3) in
counter mode.
CK: clock output
Always a driven
CK: clock input
Always hi-
TX: Transmit
Driven output
output
impedance
input
ifTXEN=t.
Hi-impedance
8.1 ROLE OF THE TIMER/COUNTERS
The timer/counters are general purpose. However, they
have special usage. RTCC is physically part of the 'core'.
It is planned that future variations of the PIC17CXX
family will include this timer. Therefore, time dependent
code, e.g. real time operating system or clock/calender
type software can be written using RTCC and ported to
future PIC17CXX family members.
input if
TXEN=O
8.0 TIMER/COUNTERS: OVERVIEW
TMR3 is also used for 16 bit capture function as is
described in capture section. Timers TMR1 and TMR2
can be used as time bases for PWM1 and PWM2
outputs respectively. Alternately, TMR1 can run both
PWM outputs and thus free up TMR2 to be a general
purpose timer.
The PIC17C42 has a rich set of timer/counters: Two 8 bit
timer counters (also configurable as one sixteen bit
timer/counter) and two 16 bit timer/counters. These can
be configured as:
-Two 16 bit + two 8 bit timer/counters
These timers are not needed to do the following functions: Watchdog timer (it's a separate timer); Baud Rate
generation for serial communication (serial port has its
own 8 bit Baud Raje Generator).
-Three 16 bit timer/counters
A brief overview of these timer/counters is as follows:
RTCC <16>: RTCC <16> is a 16 bit timer/counter
consisting of two 8 bit sections (RTCCH <8>, RTCCL<8».
It has a programmable 8 bit prescaler. RTCC can
increment off internal clock (OSC/4) or external clock
input on the RT pin. RTCC generates an interrupt on
overflow.
8.2 RTCC MODULE
The RTCC (Real time clock/counter) module consists of
a16 bittimer/counter, RTCC (high byte RTCCH, file OCh
and low byte RTCCL, file OBh), an 8 bit prescaler, and
the RT pin as the source of external clock signal. The
control bits for this module are in register RTCSTA (File
05h).
FIGURE 8_2.1.1: RTCC MODULE BLOCK DIAGRAM
~
RT
pin
Fir-=> "
~~~rR%IR overflow
'
~-
~,
1
(bitS. register INTSTA)
)-0
r------
Prescaler
(8 stage
async ripple
counter)
e- Synchronization
f---J
RTCCL <8>
1RTCC~j <8> 1",-
RTEDG
(bit 6, RTCSTA)
TIC
(bit S, RTCSTA)
t4
RTPS <3:0>
(bit <4:1>, RTCSTA)
© 1992 Microchip Technology Inc.
r
02
r
04
DS30073B-page 49
1-217
FIGURE 8.2.1.2: RTCSTA: RTCC STATUS/CONTROL REGISTER
RIW
RIW
IINTEDG I RTEDG I
RIW
Tic
RIW
RIW
I
RIW
RTPS3 I RTPS2 I RTPS1
RIW
RIW : ReadablelWritable
I RTPSO I unused I
bit 0
J
Prescale Value Selection
RTPS <3:0>
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
l
: Timer mode, i.e. clock source is internal (OSC/4)
: Counter mode, i.e. clock source is external (RT pin)
o : RTCC increments and/or RT interrupt generated
on a falling edge on RT pin.
1 : RTCC increments and/or RT interrupt generated
on a rising edge on RT pin.
: INT interrupt generated on falling edge on INT pin
: INT interrupt generated on rising edge of INT pin
8.2.1 RTCC Operation
8.2.2 Read/Write Consideration for RTCC
RTCC increments either on internal clock, OSC/4 (if
TIC = '1' in RTCSTA) or on external clock (counter
mode) on RT pin (if bitT/C = '0' in RTCSTA).lfexternal
clock is chosen, increment can occur on either the rising
edge (RTEDG = '1' is RTCSTA register) or the falling
edge (RTEDG = '0' is RTCSTA register). The prescaler
can be programmed to introduce a prescale of 1:1 to
1:256 in either timer or counter mode. The timers
increment from OOOOh to FFFFh and roll over to OOOOh.
On overflow, the RTCC interrupt request flag, RTCIR
(bit 5, register INTSTA), is set. The RTCC interrupt can
be masked off by clearing the corresponding interrupt
mask bit, RTCIE (bit 1, INTSTA). The interrupt request
flag, RTCIR, must be cleared in software.
Although the RTCC is a 16 bit timer/counter, only 8 bits
at a time can be read or written. This could create a
problem unless care is taken.
Reading 16 bit value: One problem in reading the entire
16 bit value is that after reading the low (or high) byte it
may change from FFh to OOh. This can be handled in
software as follows:
movpf
movpf
movfp
cpfslt
ret fie
movpf
movpf
ret fie
rtccl, tmpia
rtcch, tmphi
tropIo,
wreg
rtccl, wreg
rtccl, tropIa
rtcch, tmphi
:read 10 rtcc
; read hi rtcc
;tmplo --t wreg
; rtccl < wreg?
;no then return
; read 10 rtcc
; read hi rtcc
return
Interrupt must be disabled during this subroutine.
FIGURE 8.2.2.1: RTCC TIMING: WRITE HIGH OR LOW BYTE
AD <15:0>
I MOVFP
W.ATCCL
I
MOVFP ATCCL.W
I
MOVFP ATCCL.W
! MOVFP
ATCCL,W
I
MOVFP ATCCL,W
I
ALE
RTCCL --'---R-T----X
:
I
I
RTCCH -t----c----'X
:
x:
Wri~x~c~t:~CL
NRT
t
Read RTCCL
Reads NRT
I
I
X~:r------'X :
DS30073B-page 50
t
X:
Read RTCCL
Reads NRT
I
I
X:
NRT+1
t
xj
Read RTCCL
Reads NRT+1
I
I
~
© 1992 Microchip Technology Inc.
1-218
Writing a 16 bit value tothe RTCC: Since writing to either
RTCCl or RTCCH will effectively inhibit increment of
that half of the RTCC in the next cycle (following write),
but not inhibit increment of the other half, the user must
write to RTCCl first and RTCCH next in two consecutive
instructions, as shown below:
SSF
CPUSTA,
MOVF?
GLINTD
RTCC!...
MQVFP
RTCCH
BeF
GLINTD
When prescaler is used: the RA 1/RT input is divided by
the asynchronous ripple counter-type prescaler and so
the prescaler output is symmetrical. The requirements
are then:
PSOUT high time = PSOUT low time =
¥
RT
where T RT = RA 1/RT input period and
; Disable int.errupt
N = preseale value (2, 4, .... , 256).
; Done, enable interrupt
Therefore N·T RT ;;: 2tose + 20 ns, or T RT > 4 tose + 40 ns
Interrupt must be disabled. The user should note that a
write to RTCCl or RTCCH will reset the prescaler.
2
N
The user will notice that no requirement on RTCC high
time or low time is specified. However, if the high time or
low time on the RTCC input is too small then the pulse
may not be detected, hence a minimum high or low time
of 10 ns is required, In summary, the RTCC input
requirements are:
8.2.3 External Clock Considerations
When the external clock input is used for RTCC, it is
synchronized with the internal phase clocks. Therefore,
the external clock input must meet certain requirements.
Also, there is some delay from the occurrence of the
external clock edge to the incrementing of RTCC. Referring to Figure 8.2.3.1 , the synchronization is done after
the prescaler. The output of the prescaler (PSOUT) is
sampled twice in every instruction cycle to detect a rising
or a falling edge. Therefore, it is necessary for PSOUT
to be high for at least 2tosc or low for at least 2tosc where
tosc= oscillator time period.
TRT = RA1/RT period;;: (4tosc + 40 ns)/N
T RTH = RA1/RT high time;;: 10 ns
T RTL = RTCC low time ;;: 10 ns
Delay from external clock edge: since the prescaler output
is synchronized with the internal clocks, there is a small
delay from the time the external clock edge occurs to the
time the RTCC is actually incremented. Referring to
figure 8.2.3.1, the reader can see that this delay is
between 3tosc and 7tosc. Thus, for example, measuring
the interval between two edges (e.g. period) will be
accurate within ± 4tosc ( ± 250 ns @16 MHz).
When no prescaler is used (i.e. prescale is 1'1) : PSOUT
is the same as the RTCC clock input and therefore the
requirements are:
TRTH = RA1/RT high time;;: 2tosc + 20 ns
TRTL = RA1/RT low time;;: 2 tosc + 20 ns
FIGURE 8.2.2.2: RTCC READ/WRITE IN TIMER MODE
;mlmlool~;mlmlool~;mlmIQ~I~;mlmlool~;mlmlool~~lmlool~;
1
1
1
1
1
1
1
AD <15:0>
ALE
MOVFP
1
MOVFP
1
I
Instruction
{ 1 DATAL.RTCCL 1DATAH, RTCCHI
fetched
MOVPF
MOVPF
RTCCL, W 1 RTCCL, W
1 Write RTCCL I Write RTCCH I Read RTCCL
Read RTCCL
WR_RTCCl
MOVPF
RTCCL, W
Read RTCCL
MOVPF
RTCCL, W 1
Read RTCCL I
L -_ _ _ _ _ _~_ _ _ _~IlL______~________L __ _ _ _ _ _~_ _ _ _ _ _~1
11
1
II"-------'----.JIlL....---'----l~
RTCCH
12
X
1
12
X
13
X
1
AB
~----____,_______-----I
-~
-
---I
1
RTCCl
FE
X~f____FF_~X
1
1
1
56
1
1
1
X:
1
57
X:
58
1
In this example, old RTCC value is 12FEh, new value of AB56h is written
© 1992 Microchip Technology Inc.
DS30073B-page 51
1-219
FIGURE 8.2.3.1: RTCC TIMING WITH EXTERNAL CLOCK
; Q1[ Q2[ Q3[ Q4; Q1[ Q2[ Q3[ Q4; Q1[ Q2[ Q3[ Q4; Q1[ Q2[ Q3[ Q4;
Prescaler
output
(PSOUT)
I
I
I
\~~----rl
I
I
t
I
~
t
I
(note3t
Sampled
Prescaler
output
I
Increment
RTCC
RT+2
RTCC
Note1: The RTCC increments on falling edges in this example
Note2: The delay from the RT edge to the RTCC increment is 3tosc-7tosc.
Therefore, error in measuring the interval between two edges is ± 41Dsc.
Note3: t = PSOUT is sampled here.
Note4: The PSOUT high time is too small and is missed by the sampling circuit.
8.2.4 Summary of RTCC Registers
Register Name
RTCCl
RTCCH
RTCSTA
fImQiQn
~
Reset Value
RTCC Timer/Counter low byte
RTCC Timer/Counter high byte
RTCC Status/Control
File OBh
File OCh
File 05h
XXXXXXXXb
XXXXXXXXb
INTSTA
CPUSTA
Interrupt Status Register
CPU Status Register
File 07h
File 06h
OOOOOOOOb
8.3 TIMER1 & TIMER2
OOOOOOOOb
OOllXXOOb
and increment once every instruction cycle (OSC/4).
Setting bit TMR1 C = '1' will configure TMR1 as a
counter. As a counter, TMR1 will increment on every
negative edge on pin TClK12. Since TClK12 input is
synchronized with internal phase clocks, it has to satisfy
certain requirements. TClK12 must be high for at least
(0.5Tcy + 20)ns and low for at least (0.5Tcy + 20)ns
where Tcy = 4tosc. TMR 1 increments from OOh until it is
equal to PR 1 and then resets to OOh althe next increment cycle. An interrupt is generated when reset occurs
which is latched in bit TM11R (TMR1 Interrupt Request
Flag, bit 4, PIR). This bit can be masked off by setting bit
TM11E (TMR1 Interrupt Enable) to '0'. In order for the
TM11R interrupt to be recognized, the Peripheral Interrupt Enable bit (PEIE, bit3, registerlNTSTA) must be set
to a '1' and the Global Interrupt Disable bit, GLiNTD,
must be '0'. TMR1 must be enabled by setting bit
TMR10N (bit 0, register TCON2) to a '1' and can be
stopped any time by clearing bit TMR10N to '0'. TMR1
and PR1 are both readable and writable registers.
Timer 1 (TMR1, Bank 2, File 10h) and Timer 2 (TMR2,
Bank 2, File 11 h) are two 8 bit incrementing timer/
counters, each with a period register (PR1 , Bank 2, File
14h and PR2, Bank 2, File 15h respectively) and separate overflow interrupt. They can operate as timers
(increment on internal OSC/4 clock) or as counters
(increment on falling edge of external clock on pin
TClK12). They can operate as two 8 bit timer/counters
or as a single 16 bit timer counter. TMR1 and TMR2 are
also used as the time base for the PWM (pulse width
modulation) module.
8.3.1 Timer1, Timer2 in 8 Bit Mode
8 bit· mode is selected by setting 16/8 (bit 3, register
TCON1) to '0'. In this mode, TMR1 will be configured as
a timer if control bitTMR1C (bit 0, register TCON1) is '0'
DS30073B-page 52
© 1992 Microchip Technology Inc.
1-220
5, PIR), TM21E (Timer 2 Interrupt Enable Flag, bit 5, PIE)
and TMR20N (bit 1, TCON2). In counter mode, TMR2
also increments on falling edge on TCLK12 pin.
TMR2, in 8 bit mode is identical in functionality as TMR1.
The corresponding control bits for TMR2 are TM R2C (bit
1, TCON1), TM21R (Timer 2 Interrupt-Request Flag, bit
FIGURE 8.3.1.1: TIMER11T1MER2 BLOCK DIAGRAM
I Two 8 bit Timer/Counter Mode I
0
OSC/4
Set Interrupt TMRllR
(bit 4, PIR)
[gJ
RB4fTCLK12
OSC/4
------1 0
Set Interrupt TMR21R
(bit 5, PIR)
lOne 16 bit Timer/Counter MOdel
RB4fTCLK12
OSC/4 - - - - - I 0
Set Interrupt TMRllR
(bit 4, PIR)
8.3.2 Timer1 & Timer2 in 16 Bit Mode
8.3.3 External Clock Input for Timer1, Timer2
16 bit mode is selected by setting bit 16/8 (bit 3, register
TCON1) to '1'. In this mode TMR1 and TMR2 concatenate to form one 16 bit timer/counter (TMR2 = high
byte). Timer mode is selected by setting TMR1 C (bitO,
register TCON1) to '0' where it increments once every
instruction cycle (OSC/4). Counter mode is selected if
TMR1 C bit = '1' and it increments on every negative
edge on pin TCLK12. Input clock on TCLK12 must have
a high time;:: (0.5Tcy + 20)ns and a low time;:: (0.5Tcy
+ 20)ns where Tcy = 4tosc. The 16 bit timer increments
until it matches the 16 bit value in PR1, PR2(PR2= high
byte) and then resets back to OOOOh. An interrupt is
generated atthis time which is latched into the TM11R bit
(bit 4, PIR). In 16 bit mode, control bit TMR1 C controls
the entire 16 bit timer and bit TMR2C is a don't care. The
TMR20N bit must be always set to '1' in 16 bit mode.
TMR10N bit controls the entire 16-bit timer.
When configured as a counter, TMR1 or TMR2 increments on the falling edge of clock input TCLK12. However, this input is sampled and synchronized by the
internal phase clocks twice every instruction cycle.
Therefore, the external clock must meet the following
requirements:
TCLK12 high time;:: 0.5 Tcy + 20 ns
TCLK12 low time ;:: 0.5 Tcy + 20 ns
There is a delay from the time a falling edge appears on
TCLK12 to the time TMR1 or TMR2 is actually
incremented. The delay is between 2tosc and 6tosc,
where tosc .; oscillator period. See Figure 8.3.3.1 for a
timing diagram.
© 1992 Microchip Technology Inc.
DS30073B-page 53
1-221
--.:j.'.$,~...;.;:-.~
-o
"tJ
~
g
C:I
.....
......
o~
@
i
FIGURE 8.3.1.2: TMR1, TMR2, TMR3 TIMING IN TIMER MODE
CD
~
;011 021031 04; 011 021 03104; 01102103104; 011 021 031 04; 011 021 031 04; 011 021 031 04; 011 021 031 041 011 021 031 041 011 021 031 04; 011 021 031 04; 01102103104;
1
1
1
1
1
1
1
1
1
1
1
1
AD <15:0>
~cq-
ALE
Instruction":
fetched\;
MOVWF
TMR1
WriteTMR1
MOVPF
TMR1,W
ReadTMRl
MOVPF
TMR1,W
ReadTMR1
MOVLB3
NOP
BSF
TCON2,Q
StopTMR1
BCF
TCON2,O
StartTMR1
NOP
NOP
NOP
NOP
1
TMR1
...... ,
,\,)
-,,",
.
'" ,-, I
N
_..::.
PR1
TMRlON
(bitO, TCON2)
WR_TMR1
II
WR_TCON2
~ II
0
(bit4, PIR)
-
@
co
co
TMR11R
(')
-6-l II
RD_TMR1
-----r-- --
~--~----~n
CD
TMR1
=r
reads 03h
(')
:l
0
0-
<0
'<
5"
p
n~~
: TMR1
reads 04h
1 --
-I
--
--r- - - - - - - , - - - - ,
____~----~----~--~----~----~----
N
FIGURE 8.3.1.3: TIMER/CAPTURE/PWM CONTROL REGISTER 1 (TCON1)
R/W
R/W
R/W
R/W
RIW
R/W
I CA2EDI I CA2EDO I CA1EDl I CAIEDO I
I
16/8
R/W
TMR3C
R/W
I TMR2C I TMRIC I
R
= Read only bit
R/W = Readable and writable bit
U = Unused, reads as 0
bit 0
~
0: Timer/Counter1 increments on internal clock (timer
mode)
1: Timer/Counter1 increments on falling edge of
TCLK12 pin (counter mode)
0: Timer/Counter2 increments off the internal clock
(timer mode)
1: Timer/Counter2 increments on falling edges of the
TCLK12 pin (counter mode)
This bit is a don't care in 16 bit mode.
0: Timer/Counter3 increments off the internal clock
(timer mode)
1: Timer/Counter3 increments on falling edges of the
TCLK3 pin (counter mode)
0: TMR1 and TMR2 are two separate 8 bit timers
1: TMR1 and TMR2 make a 16 bit timer/counter
Capturel Mode Select
00: Capture on every falling edge
01: Capture on every rising edge
10: Capture on every 4th rising edge
11: Capture on every 16th rising edge
Capture2 Mode Select
00: Capture
01: Capture
10: Capture
11: Capture
on
on
on
on
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
FIGURE 8.3.3.1: TMR1, TMR2 AND TMR3 IN EXTERNAL CLOCK MODE
: Qll Q21 Q31Q4: Qll Q21 Q31Q4 : Q1 1Q2 1Q31 Q4: Ql1Q21 Q31Q4: Ql1Q21 031 Q4: Qll Q21Q31Q4: Ql
I
~
ALE
Instruction {
fetched
TCLK12
~
MOVWF TMRI MOVFP TMRI ,W MOVFP TMRI ,W
Write
~ TMRI ~
~
II
t
Read TMRl
PR1
34h
"A9h"
~
~
~
Read_TMR1
~
t
t t t
t
t
I'II~~~~~~~~~~~~~..----J
~'S'i&\\'fu~~\l,~
I
35h
I
A8h
I'"
I \
I J
~
119h
~
OOh
"A9h"
I
n)
I
Wr_TMR1
t
Read TMRl
~,*,'i0'J,'R\§''i\\l,
I
TMR1
I
~
I
I
AD <15:0>
n
TMR11R
(bitO, TCON2)
Notes: TCLK12 is sampled in 02 and 04, ,j, indicates a sampling point.
The latency from TCLK12 ,j, to timer increment is between 2 tosc and 6 tosc,
DS300738-page 55
© 1992 Microchip Technology Inc,
1-223
FIGURE 8.3.3.2: TIMER/CAPTURE/PWM CONTROL REGISTER 2 (TCON2)
R/W
RIW
RIW
RIW
R/W
R/W
RIW
R!W
R
= Read only bit
RIW = Readable and writable bit
U = Unused, reads as 0
I CA20VF I CAlOVF IpWM20N I PWM10N I CA1/PR31 TMR30N I TMR20N I TMRlON
[
0: TMR1 is stopped
1: TMRl is running
0: TMR2 is stopped
1: TMR2 is running
Must be set to '1' in 16 bit mode.
0: TMR3 is stopped
1: TMR3 is running
0: Registers
PR3H/CA 1Hand PR3UCA 1L
configured as period register for timer 3
1: Registers PR3H/CA 1Hand PR3UCA 1L
are
are
configured as capture 1 register. Timer 3 runs
without a period register.
0: RB2/PWMl pin configured as a port pin. Direction is
determined by corresponding DDR bit.
1: RB2/PWM1 pin is configured as PWM1 output. Pin
is forced to be an output regardless of the DDR bit.
0: R83/PWM2 pin is configured as a port pin. Direction
is determined by corresponding DDR bit.
1: RB3/PWM2 pin is configured as PWM2 output. Pin
is forced to be an output regardless of the DDR bit.
Capturel overflow status bit. Set (or reset) when both
bytes of the capture register are read and an overflow
situation has occured (or not)
Capture2 overflow status bit. Set (or reset) when both
bytes of the capture register are read and an overflow
situation has occured (or not)
8.3.4 Summary of Timer1, Timer2 Registers
Register Name
TMR1
TMR2
PR1
PR2
TCON1
TCON2
Function
Timer/Counter1
Timer/Counter2
Period Register1
Period Register2
Timer Control Register1
Timer Control Register2
Address
Bank 2, File 10h
Bank 2, File 11 h
Bank 2, File 14h
Bank 2, File 15h
Bank 3, File 16h
Bank 3, File 17h
Resej Vglye
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
OOOOOOOOb
OOOOOOOOb
PIR
PIE
Peripheral Interrupt Register
Peripheral Interrupt Enable
Bank 1, File 16h
Bank 1, File 17h
OOOOOOlOb
OOOOOOOOb
INTSTA (bit PEIE)
CPUSTA (bit GLiNTD)
Interrupt Status Register
CPU Status Register
File 07h
File 06h
OOOOOOOOb
OOllXXOOb
8.4 TIMER/COUNTER 3
falling edge of TCLK3 pin input. In either mode, TMR3
increments if TMR30N; 1 (bit 2, Register TCON2) and
stops if TMR30N ; O. TMR3 has two modes of operation: depending on bit CA 1/PR3 (bit 3, Register TCON2)
the period register can be configured as a period or a
capture register (Refer to section 9.0 for details on
capture operation).
TMR3 is a 16 bit timer/counter consisting of TMR3L (file
12, Bank 2) as the low byte of the timer and TMR3H (file
13, Bank 2) as the high byte of the timer. It has an
associated 16 bit period register consisting of PR3L!
CA 1L (file 16, Bank 2), the low byte, and PR3H/CA 1H
(file 17, Bank 2), the high byte. Timer3 is a timer if
TMR3C ; 0 (bit 2, Register TCON1) in which case it
increments every instruction cycle (OSC/4).1f TMR3C;
1, the timer 3 acts as a counter and increments on every
Period register mode CA 1/PR3 - 0: In this mode registers PR3H/CA 1Hand PR3UCA 1L constitute a 16 bit
period register. The timer increments until it equals the
DS30073B-page 56
© 1992 Microchip Technology Inc.
1-224
TCLK3 high time;:: 0.5Tcy + 20 ns
period register and then resets to OOOOh. Timer3 interrupt (TM3IR, bit 6, Register PIR) requestflag is set atthis
point. This interrupt can be disabled by setting timer3
mask bit (TM3IE, bit 6, Register PIE) to '0'. TM31R must
be cleared in software.
TCLK3 low time ;:: 0.5Tcy + 20 ns
There is a delay from the time an edge occurs on TCLK3
to the time the timer3 is actually incremented. This delay
is between 2 tosc and 6tosc, where tosc = oscillator
period. See Figure 8.3.3.1 for a timing diagram.
Capture1 register mode CA1/PR3 -1: In this mode the
PR3H/CA 1Hand PR3UCA 1L constitute a 16 bit capture
register. The timer operates without a period register
and increments from OOOOh to FFFFh and rolls over to
OOOOh. A timer3 interrupt (TM3IR, bit 6, Register PIR) is
generated on overflow. The TM31R interrupt flag must
be cleared in software.
8.4.2 Reading/Writing Timer3
Since timer3 is a 16 bit timer and only 8 bits at a time can
be read or written, the user should be careful about
reading and writing when the timer is running. The safe
and easy thing to do is to stop the timer, perform any read
or write operation, and then restart timer3 (using the
TMR30N bit). If, however, it is necessary to keep timer3
free-running then certain suggested methods must be
followed for reading and writing the timer. See section
8.2.3 for details.
8.4.1 External Clock Input for Timer3
Timer3 increments on the falling edges of the clock input
on TCLK3 pin. However, this input is sampled and
synchronized by the internal phases, twice every instruction cycle. Therefore, the external clock input must
meet the following requirements:
8.4.3 Summary of Timer3 Registers
~
~
R§gi§!§r Ngm§
TMR3L
TMR3H
CA2L
CA2H
PR3UCAIL
PR3H/CA1H
TCONI
TCON2
Timer/Counter3 low byte
Timer/Counter3 high byte
Capture2 low byte
Capture2 high byte
Period Register3 low/capture 1 low
Period Register3 high/capture 1 high
Timer Control Registerl
Timer Control Register2
Bank 2,
Bank 2,
Bank 3,
Bank 3,
Bank 2,
Bank 2,
Bank 3,
Bank 3,
PIR
PIE
Peripheral Interrupt Register
Peripheral Interrupt Enable
Bank 1, File 16h
Bank 1, File 17h
OOOOOOlOb
OOOOOOOOb
INTSTA (bit PEIE)
CPUSTA (bit GLiNTD)
Interrupt Status Register
CPU Status Register
File 07h
File 06h
OOOOOOOOb
OOllXXOOb
File
File
File
File
File
File
File
File
12h
13h
14h
15h
16h
17h
16h
17h
R§s§! VailJ§
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
OOOOOOOOb
OOOOOOOOb
DS30073B-page 57
© 1992 Microchip Technology Inc.
1-225
FIGURE 8.4.1.1: TIMER3/CAPTURE MODULE BLOCK DIAGRAM
Timer + Period Reg + One Capture Mode (CA1/PR3 = 0)
I
TMR3C
(bit 2, TCON1)
Timer 3 Interrupt
(TM3IR, bit 6, PIR)
OSC/4
-----\0
RB5ITCLK3
Capture 2 Interrupt
(CA2IR, bit 3, PIR)
CA2ED1, CA2EDO
(bits 7, 6, TCON1)
I Timer + Two Capture Mode (CAlIPR3 = 1)
CA1ED1,CA1EDO
(bits 5, 4, TCON1)
Capture 1 Interrupt
(CA1IR, bit 2, PIR)
2
~
RBO/CAPI
OSC/4 - - - - - \ 0
Timer 3 Interrupt
(TM3IR, bit 6, PIR)
RB5ITCLK3
TMR3C
(bit 2, TCON 1)
~_
6
Capture 2 Interrupt
(CA2IR, bit 3, PIR)
Edge Select
Prescaler Select
t
2
RB1/CAP2
CA2ED1, CA2EDO
(bits 7, 6, TCON1)
© 1992 Microchip Technology Inc.
DS30073B-page 58
1-226
some interesting possibilities arise. The user can activate a capture by writing to the port pin which may be
useful during development phase to emulate a capture
interrupt.
9.0 CAPTURE MODULE
The PIC17C42 has two 16 bit capture registers that
capture the 16-bit value of timer/counter3 (TMR3) when
events are detected on capture pins. There are two
capture pins (RBO/CAP1 and RBlICAP2), one for each
capture register. The capture pins are multiplexed with
port B pins. An event can be a rising edge, a falling edge,
4 rising edges or 16 rising edges on the pin. Each capture
register has an interrupt request flag associated with it
which is set when a capture is made. The capture module
is truly part of the timer/counter3/capture block. Refer to
Figure 8.4.1.1 for a block diagram. The capture module
can operate in one of two modes described below.
The input on capture pin, RBlICAP2, is synchronized
internally to internal phase clocks. This imposes certain
restrictions on the input waveform. The minimum high
time (TcPH) and the minimum low time (TcPL) on the
capture input needs to be greater or equal to 1Ons. The
period (TCAP) must be >2TcyIN where N = prescale value
(1 , 4, 16) and where Tcy = one instruction cycle time ( =
4tosc).
Capture2 Overflow
The overflow status flag bit is double buffered. The
master bit is set to '1' if one captured word is already
residing in the capture2 register and another 'event' has
occurred on RB1/CA2 pin. The new event will not
transfer the timer3 value to the capture register, protecting the previous unread capture value. When the user
reads both the high and the low bytes (in any order) olthe
capture2 register, the master overflow bit is transferred
to the slave overflow bit (CA20VF, bit 7, TCON2) and
then the master bit is reset. The user can then read
TCON2 to determine the value of CA20VF.
9.1 ONE CAPTURE + TIMER/
COUNTER3 + PERIOD REGISTER
MODE
This mode is selected if control bit CA 1IPR3 = 0 (bit 3,
register TCON2). In this mode, the capture1 register,
consisting of high byte (PR3H/CA 1H, File 17, Bank 2)
and low byte (PR3UCA1 L, File 16, Bank 2), is configured as the period control register for TMR3. Capture1
is disabled in this mode, and the corresponding interrupt
bit CA 11R (bit 2, PIR) is never set. Timer/counter3
increments until it equals the value in the period register
and then resets to OOOOh. See Section 8.4 for details of
TMR3 operation in this mode.
The recommended sequence to read capture registers
and overflow is as follows:
; Select Bank 3
; Read capture2 low byte,
Capture2 is active in this mode. Control bits CA2ED1
and CA2EDO (bits 7 & 6, Register TCON1) determine
the event on which capture will occur. CA2ED1, CA2EDO
= 00 enables capture on every falling edge, 01 = capture
on every rising edge, 10 = capture every 4th rising edge
and 11 = capture every 16th rising edge. When a capture
takes place, an interrupt is latched into CA21R (capture
2 interrupt flag, bit 3, PIR). This interrupt can be enabled
by setting the corresponding mask bit CA21E (bit 3, PIE)
to '1 '. Also, peripheral interrupt enable bit PEIE (bit 3,
INSTA) must be a '1' and the Global Interrupt Disable bit
(GLINTD, bit4, CPUSTA), should be '0' forthe interrupt
to be acknowledged. The CA21R interrupt flag needs to
be cleared in software.
MOVPF
CA2H, HI_BYTE
MOVPF
TCON2 , STAT_VAL
; Read capture2 high byte,
; store i.n HI_BYTE
; Read TCON2 into file
; STAT_VAL
9.2 TWO CAPTURE + TIMER/
COUNTER3 MODE
This mode is selected by setting CA 1IPR3 = 1 (bit 3,
register TCON2). In this mode the timer (TMR3) runs
without a period register and increments from OOOOh to
FFFFh and rolls over to OOOOh. For details on TMR3
operation see section 8.4 Registers PR3H/CA 1H (file
17h, Bank 2) and PR2UCA 1L (file 16h, Bank 2) make a
16 bit capture register (Capture1). It captures events on
pin RBO/CAP1. Capture mode is set by control bits
CA 1ED1 and CA 1EDO (bit 5 & 4, Register TCON1). A
capture1 interrupt is latched into the CA11R (bit 2, PIR).
The corresponding interrupt mask bit is CA11E (bit 2,
PIE). The capture1 overflow status bit is CA 1OVF (bit 6,
TCON2). Otherwise, capture1 operates identically to
capture2. Capture2 operation is same as in the previous
mode.
When the capture prescale select is changed, the prescaler is not reset. Therefore, the first capture after such
a change will be ambiguous. It, however, sets the basis
for the next capture. The prescaler is reset upon chip
reset.
The capture pin RB1/CAP2 is a multiplexed pin. When
used as a port pin, capture2 is not disabled. However,
the user can simply disable the capture2 interrupt by
setting CA2IE= '0'. If RB1 ICAP2 is used as an output pin,
© 1992 Microchip Technology Inc.
DS30073B-page 59
1-227
9.3 SUMMARY OF CAPTURE REGISTERS
~
Reset Value
Register Name
Function
PR3UCAll
PR3H/CA1H
CA2l
CA2H
TMR3l
TMR3H
TCONl
TCON2
Period Register 3 low/capture 1 low
Period Register 3 high/capture 1 low
Capture2 register low
Capture2 register high
Timer/Counter 3 low
Timer/Counter 3 high
Timer Control Register 1
Timer Control Register 2
Bank 2,
Bank 2,
Bank 3,
Bank 3,
Bank 2,
Bank 2,
Bank 3,
Bank 3,
16h
17h
14h
15h
12h
13h
16h
17h
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
PIR
PIE
Peripheral Interrupt Register
Peripheral Interrupt Enable
Bank 1, File 16h
Bank 1, File17h
OOOOOOlOb
OOOOOOOOb
INTSTA (bit PEIE)
CPUSTA (bit GLINTO)
Interrupt Status Register
CPU Status Register
File 07h
File 06h
OOOOOOOOb
OOllXXOOb
File
File
File
File
File
File
File
File
OOOOOOOOb
OOOOOOOOb
The duty cycle registers for both PWM outputs are
double buffered. When the user writes to these registers
they are stored in master latches. When TMR1 (or
TMR2) overflows, and a new PWM period begins the
master latch values are transferred to the slave latches.
10.0 PULSE WIDTH MODULATION
(PWM) OUTPUTS
The PIC17C42 provides two high speed pulse-width
modulation outputs on pins RB2/PWM 1 and RB3/PWM2.
Each PWM output has a maximum resolution of 10 bits.
At 10 bit resolution, the PWM output frequency is 15.6
KHz (@ 16 MHz clock) and at 8 bit resolution the PWM
output frequency is 62.5 KHz.
FIGURE 10.0.1 - SIMPLIFIED PWM BLOCK
DIAGRAM
The user needs to set the PWM 1ON control bit (bit 4,
register TCON2) to enable the PWMl output. Once the
PWM10N bit = '1', the RB2/PWMl pin is configured as
PWM1 output and forced as an output irrespective of the
data direction bit. If PWMl ON = '0', then the pin behaves
as a port pin and its direction is controlled by its data
direction bit (bit2, DDRB). Similarly, the PWM20N bit
controls the configuration of the RB3/PWM2 pin.
The period of the PWM1 output is determined by timer1
(TMR1) and its period register (PR1). The period of the
PWM2 output is determined by timer1 if control bit
TM2PW2 = '0' (bit 5, register PW2DCL) or by timer2 if
TM2PW2= '1'.
Notes: 1. a-bit timer is concatenated with 2-bit internal Q clock time
to create 1O-bit time base.
2. Timer1 is used in this example.
Thus the PWM periods are:
tPWM1P = period of PWM1 =
[(PR1) + 1] x 4 tosc
tPWM2P = period of PWM2 = [(PR1) + 1] x 4 tosc
Using extemal clock for PWM will also cause jitter in the
'duty cycle' as well as the 'period' of the PWM output.
This is because external TClK12 input is synchronized
internally (sampled once per instruction cycle). Therefore, from the time TClK12 changes to the time timer
increments will vary by as much as Tcy (one instruction
cycle). Therefore, both the high time and the period of
the PWM output will have a jitter of ±Tcy, unless the
external clock is in sync with the processor clock. The
latter is the case when TClK12 input itself is generated
by the PIC17C42 (e.g. one PWM output is feedback as
TClK12).
or [(PR2) + 1] x 4 tosc
The duty cycle of PWM 1 is determined by the 10 bit value
DC1 <9:0>. The upper 8 bits are from register PWl DCH
(file 12, Bank 3) and the lower 2 bits are in register
PW1DCl<1 :0> (file 10, Bank3). The PWM1 high time is
as follows:
tPWM1H = PWM1 high time = (DC1) x tosc
where DC1 represents the 10 bit value from PW1 DCH,
PW1 Del concatenated.
If DCl = 0, then the duty cycle is zero. If tPWM1H is equal
to or higher than tPWMl Pthen the duty cycle is 100%.
In general therefore, when using external clock reference for PWM, its frequency should be much smaller
compared to fosc.
Similarly, PWM2 high time, tPWM2H = (DC2) x tosc.
© 1992 Microchip Technology Inc.
DS30073B-page 60
1-228
PWM interrupts: The PWM module makes use of timer1
or timer2 interrupts. A timer interrupt is generated when
TMR1 or TMR2 equals its period register and is reset to
zero. This interrupt, also marks the beginning of a PWM
cycle. The user can write new duty cycle values before
the next interrupt. The timer1 interrupt is latched into the
TM11R bit (bit4, PIR) and the timer2 interrupt is latched
into the TM21R bit (bit 5, PIR). These flags need to be
cleared in software.
resolutions. The user should also note that the maximum attainable frequency is lower. Since the maximum
possible external clock input frequency for a timer is 1/
(Tc + 40) ns, (see AC specs) the PWM frequency at 8 bit
resolution can be, at most, 13.47 KHz (@ 16 MHz osc
clock).
Timer selection for PWM2: While PWM1 always runs
basedonTMR1, PWM2can run offtimer1 (ifbitTM2PW2
= 0, bit 5, Register PW2DCl) ortimer2 (ifTM2PW2 = 1).
Running two different PWM outputs on two different
timers allow different PWM period.
Using External clock: Timer1 or timer2, when used as
the PWM time base, may be run off external clock only
if the PWM output is being generated with 8 bit resolution
or less. In this case, the PW1 DCl and the PW2DCl
registers must be kept at '0'. Any other value will distort
the PWM output. Internal clock can be used for all
Running both PWMs off timer1 allows the best utilization
of resources. If frees timer2 to operate as an 8 bit timer/
counter. Timer1 and timer2 can not be used as a 16 bit
timer if either PWM is being used.
FIGURE 10.0.2 - PWM OUTPUT
0
PWM
output
10
I
t
Timer
interrupt
Notes:
20
30
40
0
I-------n
t
Write new
PWM value
t
~
Timer interrupt
new PWM value
transferred to slave
1. The dotted line shows PWM output if duty cycle registers are not double buffered. If the new
duty cycle value is written after the timer has passed that value, then the PWM does not
reset at all during the current cycle causing a "glitch".
2. In this example, PWM period = 50. Old duty cycle value is 30. New duty cycle value is 10.
Operating on duty cycle registers: For PW1 DCH,
PW1 DCl, PW2DCH and PW2DCl registers, a write
operation writes to the "master latches" while a read
operation reads the "slave latches". As a result, the user
may not read back what was just written to the duty cycle
registers.
Figure 10.0.1 shows a simplified block diagram of the
PWM module. The duty cycle register is double buffered
for a glitch free operation. Figure 10.0.2 shows how a
glitch could occur if duty cycle registers are !lQ1 double
buffered.
The user should also avoid any "read-modify-write"
operations on these registers, such as: ADDWF
PW1 DCH, may not work as intended.
DS30073B-page 61
© 1992 Microchip Technology Inc.
1-229
10.1 SUMMARY OF PWM REGISTERS
MdNu
Register Name
TMR1
TMR2
PR1
PR2
TCON1
TCON2
PW1DCL
PW1DCH
PW2DCL
PW2DCH
Function
Timer/Counter 1
Timer/Counter 2
Period Register 1
Period Register 2
Timer/Capture/PWM Control Register 1
Timer/Capture/PWM Control Register 2
PWM1 duty cycle, lower 2 bits
PWM1 duty cycle, upper 8 bits
PWM2 duty cycle, lower 2 bits
PWM2 duty cycle, upper 8 bits
Bank 2,
Bank 2,
Bank 2,
Bank 2,
Bank 3,
Bank 3,
Bank 3,
Bank 3,
Bank 3,
Bank 3,
10h
11 h
14h
15h
16h
17h
10h
12h
11 h
13h
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
OOOOOOOOb
OOOOOOOOb
XXOOOOOOb
XXXXXXXXb
XXOOOOOOb
XXXXXXXXb
PIR
PIE
Peripheral Interrupt Register
Peripheral Interrupt Enable
Bank 1, File 16h
Bank 1, File 17h
OOOOOOlOb
OOOOOOOOb
INTSTA (bit PEIE)
CPUSTA (bit GLiNTD)
Interrupt Status Register
CPU Status Register
File 07h
File 06h
OOOOOOOOb
OOllXXOOb
11.0 DEVELOPMENT SUPPORT
File
File
File
File
File
File
File
File
File
File
Reset Value
11.2 PICPAK-17™: PIC17C42
EVALUATION/DEVELOPMENT/
PROGRAMMER KIT
The PIC17C42 is supported with a full range of development tools as well as several support programs. These
tools and support programs help the user design the
PIC17C42 into his or her system easily and quickly. The
user can take advantage of the variety of tools from
evaluation stage to complex design debug phase. Time
to market is significantly reduced by the easy-to-use, PC
based tools. All the available and planned tools and
programs are described in this section.
The PICPAK-17 is a very low cost development kit
containing an Evaluation/Development/Programmer
PCB, PC-based assembler, and documentation. The
EDP board operates in one of three modes:
a) Programmer mode: In this mode the PIC17C42 programs itself from two external 27C64 EPROMs. The
user simply programs the EPROMs with the desired
code using any standard EPROM programmer.
11.1 PICASM·17 : PIC17C42 CROSS
ASSEMBLER:
b) External execution mode: In this mode the PIC17C42
executes out of two external 8K x 8 EPROMs or
SRAMs. The user may also plug in a ROM emulator
instead of using EPROMs.
The PICASM-17 is a powerful two pass relocatable
assembler with advanced MACRO capabilities, high
level construct support and source line debug support.
It runs on any PC compatible platform. A host of
assembler directives support conditional assembly, data
area definition and initialization, outputting customized
error messages, formatting listing file etc. Advanced
MACRO processing capabilities include nesting of macros, conditional macro expansion and parameterized
macros. High level constructs such as WHILE and IFTHEN-ELSE permit readable and efficient code writing.
ANSI-C style expressions and #define support further
makes the assembler more like a high level language.
c) Internal execution mode: In this mode the PIC17C42
executes from its own internal memory. The external
memories are disconnected.
The development board has a solder-less bread-board
area with most PIC17C42 signals brought out for easy
prototyping and evaluation. Only a single 5V supply is
required forthe board. Additionally, there is a PIC16C57
microcontroller, which primarily controls the mode selection but is also capable of providing complex stimuli
to the PIC17C42 such as stream of capture, timer clock
or interrupt pulses, asynchronous data stream or synchronous data stream. Various stimuli are easily selected through DIP switch settings.
11.3 PRO MASTERTM PROGRAMMER
The PRO MASTER programmer is a production quality
programmer capable of operating in stand alone mode
as well as PC-hosted mode.
DS30073B-page 62
© 1992 Microchip Technology Inc.
1-230
The PRO MASTER has programmable VDD and VPp
supplies which allows it to verify the PIC at VDD min and
VDD max for maximum reliability. It has an LCD display
for displaying error messages, keys to enter commands
and a modular detachable socket assembly to support
various package types. In stand alone mode the PRO
MASTER can read, verify or program a part. It can also
set fuse configuration and code-protect in this mode. It's
EEPROM memory holds data and parametric information even when powered down. It is ideal for duplicating
a large number PIC17C42 for production.
A "Quick Start" PIC Product Sample Pak containing user
programmable parts is included for additional convenience.
Microchip provides additional customer support to developers through an electronic Bulletin Board System
(EBBS). Customers have access to the latest updates
in software as well as application source code examples. Consult your local sales representative for
information on accessing the BBS system.
11.4.1 Host System Reguirements:
In PC-hosted mode, the PRO MASTER connects to the
PC via one of the COM (RS232) ports. PC based userinterface software makes using the programmer simple
and efficient. The user interface is full-screen and menubased. Full screen display and editing of data, easy
selection offuse configuration and part type, easy selection of VDD min, VDD max and VPp levels, load and store
to and from disk files (intel hex format) are some of the
features of the software. Essential commands such as
read, verify, program, blank check can be issued from
the screen. Additionally, serial programming support is
possible where each part is programmed with a different
The PICMASTER has been designed as a real-time
emulation system with advanced features generally
found on more expensive development tools. The AT
platform and Windows 3.1 environment was chosen to
best make these features available to you the end user.
To properly take advantages of these features,
PICMASTER requires installation on a system having
the following minimum configuration:
PC AT compatible machine: 80286, 386SX, 386DX,
or 80486 with .lSA or EISA Bus.
EGA, VGA, 8514/A, Hercules graphic card (EGA or
higher recommended).
MSDOS I PCDOS version 3.1 or greater.
Microsoft Windows® version 3.0 or greater operating
in either standard or 386 enhanced mode).
1 Mbyte RAM (2 Mbytes recommended).
One 5.25" floppy disk drive.
Approximately 10 Mbytes of hard disk (1 Mbyte required for PICMASTER, remainder for Windows 3.0
system).
One 8-bit PC AT (ISA) 1/0 expansion slot (half size)
Microsoft® mouse or compatible (highly recommended).
11.4 PICMASTERTM-17: HIGH
PERFORMANCE UNIVERSAL
IN-CIRCUIT EMULATOR SYSTEM
The PICMASTER Universal In-Circuit Emulator System
is intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16C5X and PIC17CXX families. This system currently supports the PIC16C54,
PIC16C55, PIC16C56, PIC16C57 and PIC17C42 processors.
11.4.2 Emulator System Components:
The PICMASTER Emulator Universal System consists
primarily of 4 major components:
Host·lnterface Card: The PC Host Interface Card
connects the emulator system to an IBM PC compatible system. This high-speed parallel interface requires a single half-size standard AT liSA slot in the
host system. A 37 -conductor cable connects the
interface card to the external Emulator Control Pod.
Emulator Control Pod: The Emulator Control Pod
contains all emulation and control logic common to all
microcontroller devices. Emulation memory, trace
memory, event and cycle timers, and tracelbreakpoint
logic are contained here. The Pod controls and
interfaces to an interchangeable target-specific emulator probe via a 14" precision ribbon cable.
• Target·specific Emulator Probe: A probe specific to
microcontroller family to be emulated is installed on
the ribbon cable coming from the control pod. This
probe configures the universal system for emulation
of a specific microcontroller. Currently, the 16C5x
family, and the new PIC17C42 microcontrollers are
supported. Future microcontroller probes will be
available as they are released.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new PIC16CXX and
PIC17CXX microcontrollers.
The Emulator System is designed to operate on low-cost
PC compatible machines ranging from 80286-AT class
ISA-bus systems through the new 80486 EISA-bus
machines. The development software runs in the Microsoft Windows® 3.1 environment, allowing the operator access to a wide range of supporting software and
accessories.
Provided with the PICMASTER System is a high performance real-time In-Circuit Emulator, a microcontroller
EPROM programmer unit, a macro assembler program,
and a simulator program. Sample programs are provided to help quickly familiarize the user with the development system and the PIC microcontroller line.
Coupled with the user's choice of text editor, the system
is ready for development of products containing any of
Microchip's microcontroller products.
© 1992 Microchip Technology Inc.
DS300738-page 63
1-231
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
Dynamic Data Exchange (DOE), a feature of
Windows 3.1, will be available in this and future
versions of the software. DOE allows data to be
dynamically transferred between two or more
Windows programs. With this feature, data collected with PICMASTER can be automatically
transferred to a spreadsheet or database program
for further analysis.
Under Windows 3.1 , two or more PICMASTER
emulators can run simultaneously on the same PC
making development of multi-microcontroller
systems possible (e.g., a system containing a
PIC16C5x processor and a PIC17Cxx processor).
PC Host Emulation Control Software: Host
software necessary to control and provide a
working user interface is the last major component
of the system. The emulation software runs in the
Windows 3.0 environment, and provides the user
with full display, alter, and control of the system
under emulation. The Control Software is also
universal to all microcontroller families.
The Windows 3.1 System is a multitasking operating system which will allows the developer to take
full advantage of the many powerful features and
functions of the PICMASTER system.
FIGURE 11.4.1: PICMASTER-17 DEVELOPMENT SYSTEM
FIGURE 11.4.2: PICMASTER-17 DEVELOPMENT SYSTEM BLOCK DIAGRAM
~
011111111111111111111"&
Common Interface Card
Aux.
PC-Interface
PICMASTER Emulator Pod
pc Compatible Computer
(AT/ISA Bus) (for Industry Standard Architecture)
© 1992 Microchip Technology Inc.
DS30073B-page 64
1-2.32
11.6 APPLICATION AND TECHNICAL
FIGURE 11.4.3: SAMPLE SCREEN LAYOUT
FOR PICMASTER-17
SUPPORT
PtC-MASTER- D:IICEWIN\DDEDEMO.OBJ
file
,Configure
,S;etup
Watch
Bun
lltility
Wlnd,,-w
Microchip Technology has a number of sales offices in
U.S., Europe, and Asia with highly trained Field Applications Engineers to give you prompt, hands on technical
support. Please refer to the back cover page for the
sales office and its number nearest to you. In addition,
factory technical staff will be glad to help you over the
phone (602-963-7373, Chandler, AZ, U.S.A). Application notes and software routines are being made available to give you a jump-start in your system development. These are usually available in printed as well as
electronic format.
Help
Trace Memory Dump
00001;
~~
~
=
0049
0880
0048
086/1
01
capl
Microsoft Excel
=
DDEDEMO.xLS
~m==1AiE~±~~~D~gE~~~~G~~1
r?r}-
~
2176
2154
IData From PIC-MASTER via DOEI
2132
rT ~~f
f:t
r+ . . . . 207~'
~+
ht?Q5<\
r.lt " " " ,:~~.
2400
=JVWWW
11.7 PROGRAMMING SUPPORT
2100
2000
The OTP microcontroller provides excellent time-tomarket. It offers quick development, over-night code
changes and easy to manage inventory. To support your
programming needs Microchip offers various options.
Ready
11.5 ORDERING DEVELOPMENT
11.7.1 Prototype Programming
TOOLS
Prototype programming can be done either using the
low cost PICPAK-17 board or the PRO MASTER production quality programmer.
The development tools are packaged as comprehensive systems for your convenience. Their description
and planned availability dates are as follows:
11.7.2 Production Volume Programming
System
PICPAK-17
PICMASTER-17
PRO MASTERTM
Description
Includes:
PICASM-17
PIC EDP-17 manuals
Includes:
PICASM-17
PRO MASTER
PICMASTER
PIC17C42 personality
module manuals
Includes:
PRO MASTER programmer
DIP socket module
manuals
Available
High volume programming for production can be done
using the PRO MASTER programmer. Microchip is
working with industry leading programming companies
to support the PIC17C42 on their programmers. Our low
end 8-bit microcontroller family, the PIC16CXX, is now
supported by DATA 1/0, Logical Devices, BP
Microsystems, Baradine and Stag most of which support
handlers. Microchip is working to develop a similar level
of support for the PIC17CXX family of products.
Now
Now
11.7.3 Factory Programming
Now
High volume factory programming (QTP) is an available
service from Microchip Technology. A small price adder
and a minimum quantity requirement apply.
11.7.4 Distributor Programming Support
Some of our distributors will support your programming
needs. Please contact your distributor for price and
volume requirements.
DS300736-page 65
© 1992 Microchip Technology Inc.
1-233
PIC®17C42
12.0 ELECTRICAL CHARACTERISTICS
12.1 ABSOLUTE MAXIMUM RATINGS
'Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation
of the device at those or any other conditions above
those indicated in the operation listings of this
specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device
reliability.
Maximum temperatures
Ambient temperature under bias ......... -55°C to 125°C
Storage temperature ........................... -65°C to 150°C
Maximum voltages
VDD to Vss .................................................. OV to +7.5V
........ -0.6V to 12V
MCLR to Vss ..
RA2and RA3toVss.....
........ -0.6Vto 12V
Any pin with respect to Vss ....
,-{).6V to VDO +0.6V
(except VDD, MCLR, RA2, RA3)
Notes:
Maximum currents
Into VDD pin(s) total .......................................... 150 mA
Out of all Vss pins total ..................................... 150 mA
Into any pin when configured as output
(except RA2, RA3) ......................................... 35 mA
1. Total power dissipation should not exceed
1 W for the package. Power dissipation is
calculated as follows:
Pdis = VDD x {IDD loh} + L(Vol x 101)
L loh} + L {(VDD-Voh)
x
2. Voltage spikes below Vss at the MCLR pin,
inducing currents greater than 80 mA, may
cause latch-up. Thus, aseries resistor of 501OOQ should be used when applying a "low"
level to the MCLR pin ratherthan pulling this
pin directly to Vss.
Into RA2, RA3 when configured as output.. ....... 60 mA
Out of any pin when configured as output ......... 20 mA
Into any pin when configured as input ............ ±500 ~A
Maximum power dissipation
Total power dissipation ........................................... 1W
DS30073B-page 66
©1992 Microchip Technology Inc.
1-234
12.2 DC CHARACTERISTICS
Operating Condltions: 4. 5V ~ VDO
Characteristic
~5. 5V ,-40 0 C ~TA ~8 5 0 C
Symbol
Min
Voo
1001
1002
1003
1004
100s1
loos2
loos3
loos4
Vpp
4.5
un ess otherwlse stated.
Typt
Max
Unit
Conditions
SUPpl~ llglllglllml CU[[lDll
Supply Voltage
Supply Current (note 1)
Standby current (notes 2,3)
Programming voltage
Ingut vgltlgg Illlgll II! h~lllriliili
All inputs except C, 0 and E
ports (Schmitt trigger inputs)
including OSC1 (EC, RC modes)
Ports C, 0 and E (TTL input)
OSC1 (XT, LF modes)
Vil1
Vih1
Vhys1
Vil2
Vih2
Vil3
Vih3
5.5
6
11.5
5.0
3
95
6
11
30
60
15
30
11.75
12
24
50
100
25
50
12.0
-
-
0.2 Voo
-
0.8
-
0.8 Voo
0.15Voo'
2.0
O.B Voo
-
-
-
-
V
mA
uA
mA
mA
uA
uA
uA
J.lA
V
V
V
V
V
V
-
0.2Voo
-
±1
±2
±2
10
uA
uA
uA
uA
-
IORUt !Iaygg curtlot
All pins except MCLR,RA2,RA3
MCLR pin
RA2,RA3pin
MCLR pin
lil1
1i12
lil3
lil4
-
PiO cagacil10Ci
All pins except MCLR, VDD, Vss
MCLR
Cin
Cmclr
-
10'
20'
-
pF
pF
Voh1
Vol1
Voh2
Vol2
Voh3
Vol3
Voh4
Vol4
Ipu
Vram
2.4
-
-
12.0
3.0
V
V
V
V
V
V
V
V
uA
V
QutRut vglllg~ Igvglli
RA2,RA3 (open collector)
PORT C, 0 & E (TTL)
OSC2/CLKOUT (RC & EC modes)
All Outputs except OSC2
(including C, 0 and E ports)
Weak pull-up current (PortB)
RAM retention voltage
-
2.4
0.9 Voo
60
1.5'
-
-
100
-
Voo=5.5V,freq=4MHz
Voo=4.5V, freq=32KHz
Voo=5.5V,freq=8MHz
Voo=5.5V ,freq= 16MHz
Voo=4.5V,WDT on
Voo=5.5V,WDT on
Voo=4.5V, WDT off
Voo=5.5V,WDT off
0.4
0.4
0.1 Voo
250
-
Vss ~ VPIN
~Voo
(note 4)
Vss~VMCLR~Voo
Vss ~ VRA2, VRA3~12V
VMCLR = Vpp(note 5)
(note 6)
1011 = 60 mA, Voo = 5.5V
loh2 = -6 mA, Voo = 4.5V
1012 = 6 mA, Voo = 4.5V
loh3 = -5 mA, Voo = 4.5V
1013 = 3 mA, Voo = 4.5V
loh4 = -2 mA
1014 =4 mA
Pull-up active, VPIN = Vss
t: Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
,.
".
NOTE 1:
Guaranteed by characterization and not tested.
Guaranteed by Design.
Supply current is measured with PIC17C42 executing code (frOm internal test EPROM which Is same as microcomputer mode) with all port pins configured as input
and forced to Voo or Vss. External clock (rail to rail) is used. The user should note the following:
a) The code executed from test memory attempts to exercise the chip to make more realistic measurements of IDO (rather than in reset). However, depending on
user's code, the current will vary.
b) The user needs to add the current consumed by output drivers driving external capacitive or resistive load. For capacitive loads, this can be estimated for an
individual output pin as: (CLVoo) f where CL"" total capacitive load, f = average frequency with which the pin switches.
The current due to external capacttance load switching is most significant during external execution.
NOTE 4:
NOTE 5:
c) The current consumed by the oscillator circuit needs to be considered as well. This will be especially significant for RC oscillator, where the current through the
external pull up resistor can be estimated as: Voo/(2·R)
Standby current is measured under the following conditions: Part in SLEEP, MCCR "" Voo. OSC1 and OSC2 pins driven or left floating (makes no difference). All port
pins configured as input and tied to Vss or Voo. Standby current is not affected by oscillator type.
WOT off implies fuses FWOTl "" FWOTO "" 0 which configures the WOT as a normal timer that shuts off during SLEEP. WOT on implies that the WOT is
configured as a watchdog timer (FWDT1, FWOTO "" 01, 100r 11) which continues to run during SLEEP.
With any weak pull-up disabled.
When not programming
NOTE 6:
RA2 and RA3 are open collector outputs that will pull-up to externally applied voltage (through resistor pull-ups). Maximum allowable VOH "" 12V.
NOTE 2:
NOTE 3:
© 1992 Microchip Technology Inc.
IPnBl~imhllaJll'11' ~!l'Il~mmaJ~ilQl!l'll
1-235
DS30073B-page 67
12.3 AC CHARACTERISTICS
12.3.1 AC Characteristics: OSC/Reset/System bus
Operating Conditions: 4.5V :s;Voo :S;5.5V, -40°C :s;TA :S;S5°C unless otherwise stated.
Characteristic
101:1111 !tl~k and QI!tillalIU
frequeo!ties
Oscillator frequency
Svmbol
Min
TVDt
Max
Unit
Comments
KHz
MHz
MHz
Kohm
pF
MHz
ns
LF osc mode
XTosc mode
RC osc mode
DC
0.2
DC
2
20
DC
-
External clock in frequency
Instruction cycle time
Fosclf
Foscxt
Foscrc
R
C
Fextck
Tcy
-
200
16
4
50
1000
16
-
4/Fosc
-
Clock-in (OSC1) high or low time
TckHL
15'
Clock-in (OSC1) rise or fall time
TckRF
RC mode frequency
Recommended limits:
Reu1liming
MCLR pulse width
MCLR t to AD<15:0> high
impedance
WOT, QST, fWBI and
POR1imingi
WDTperiod
Power up timer period
Oscillator start-up timer
(OST) period
VDD rise time for POR to
function properly
VDD start voltage to guarantee
power on reset
Sllllltm bUI1imingi
Address out valid to ALE t
(address setup time)
ALE J, to address out invalid
(address hold time)
AD <15:0> high impedance
to OEJ,
DEi to AD<15:0> driven
Data in valid before OEi
(data setup time)
GEi to data in invalid
(data hold time)
Data out valid to WRJ,
(data setup time)
WRf to data out invalid
(data hold time)
ALE pulse width
OE pulse width
WR pulse width
ALE f to ALE i (cycle time)
Cill:lilll11ivlt IQild !In !lU11:lU1 1:1101
OSC2
ALE, WR, OE and AD<15:0>
All other pins, including
C, 0, E ports (when used
as port)
See footnotes on next page.
DS30073B-page 68
tmcL
tmcL2adZ
ns
100'
15'
ns
-
ns
ns
-
-
50'
-
20'
SO'
1024tOSC"
-
ms
ms
ns
tVDDR
-
SO'
ms
VPOR
Vss'
-
V
twdt
tPWRT
tOST
-
-
tadV2alL
0.25 Tcy-30
-
-
ns
talL2adi
5
-
-
ns
tadZ20eL
0
-
-
ns
toeH2adD
tadV20eH
0.25 Tcy-15
30
-
-
-
-
ns
ns
toeH2adi
0
.-
-
ns
tadV2wrL
0.25 Tcy-40
-
ns
twrH2adi
5
-
ns
talH
toeL
twrL
talH2alH
Cload1
Cload2
Cload3
-
-
0.25 Tcy"
0.5 Tcy-25"
-
-
0.25 Tcy"
Tcy"
-
-
-
-
-
-
ns
ns
ns
ns
25
100
50
pF
pF
pF
PII~~~m~I11l©lIl1f ~111l~lQJllm©l~~1QJ111l
1-236
EC mode (external clock)
Fosc = osC/clock-in
frequency
For external clock input in
XT, LF or EC mode.
For external clock input in
XT LF or EC mode.
Prescale = 1
tosc
= oscillator period
Time for VDD to rise from
OV to 4.5V (Note 1)
See section 4.4 for
details
with 100 pF load on all
address/data and control
(ALE,OE,WR) pins.
(note 2)
(note 3)
(note 3)
© 1992 Microchip Technology Inc.
t:
•.
••.
NOTE 1:
NOTE 2:
NOTE 3:
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Guaranteed by characterization
Guaranteed by design
Voo must start from OV for Power on reset to function properly. voo rise time can be longer but then external
POR circuitry will be required.
In EC and RC oscillator modes when OSC2 pin is outputting CLKOUT, or in XT or LP mode when external clock
is driven into OSC1 pin.
All AC specs are valid for these capacitive loadings
12.3.2 AC Characteristics: Serial Port
Operating Conditions: 4.5V
~VDD ~5.5V,
Characteristic
SY~Q XMIT (MAST!;R
-40°C
~TA ~85°C
Symbol
Min
unless otherwise stated.
Typt
Max
Unit
50
ns
Comments
& S!.A~!;)
tckH2dtV
-
Clock out rise time and fall time
(Master Mode)
tckrf
-
-
25
ns
Data out rise time and fall time
tdtrf
-
-
25
ns
Clock high to data out valid
SYNQ RQ~ (MASI!;B & SLAVE)
Data in valid before
CK t (DT setup time)
tdtV2ckL
15
-
-
ns
Data in invalid after
CD t (DT hold time)
tckL2dti
15
-
-
ns
t:
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
12.3.3 AC Characteristics: I/O Port
Operating Conditions: 4.5V
~VDD ~5.5V,
-40°C
~A ~85°C
unless otherwise stated.
Characteristic
CLKOUT i to Port out valid
Symbol
tckH2rxV
Min
Typt
-
-
Max
O.5Tcy+20
Unit
ns
Port A, S, C, 0, E in valid before
CLKOUT i ( RC and EC mode)
trxV2ckH
0.25 Tcy+25
-
-
ns
t:
NOTE 1:
Comments
note 1
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Timings are valid for a maximum of 50pF total capacitive load on the port pins, and CLKOUT pin.
© 1992 Microchip Technology Inc.
IPnBJ~~m~lIiltal~Y' ~1Iil~IQl~mtal~~1Ql1lil
1-237
DS30073B-page 69
12.3.4 AC Characteristics: RTCC & INT
Operating Conditions: 4.SV ::;VDD ::;S.SV, -40°C ::;TA ::;8SoC unless otherwise stated.
',:,'j)
'.
Characteristic
II
RTCC in ext clock prescale - 1
i
Min
Typt
Max
Unit
trtH1
trtL1
0.5 Tcy+20""
0.5 Tcy+20""
-
-
ns
ns
trtH2
trtH2
trtP
10"
10"
-
-
Tcy+40""
N
-
ns
ns
ns
triH
tril
25"
25"
-
-
ns
ns
Symbol
Comments
!
RT clock input high time
RT clock input low time
-
RTCC in ext clock. prescale > 1
RT clock input high time
RT clock input low time
RT clock input period
-
N = prescale value
(2,4,8, .... ,256)
RT and INT interrupt input
RT and INT input high time
RT and INT input low time
t:
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are lor design guidance only and
are not tested.
Guaranteed by characterization
Guaranteed by design and characterization
12.3.5 AC Characteristics: Timer1, Timer2, Timer3, Capture and PWM
Operating Conditions: 4.SV ::;VDD ::;S.5V, -40°C ::;TA ::;8SoC unless otherwise stated.
Characteristic
Ti!l]er1 Timf!r2 Timer~
Input clock high time on
pins TClK12, TClK3
Input clock low time on
pins TClK12, TClK3
QaptUrf!1 Qaplurf!2
Input high time on
RBO/CAP1, RB1/CAP2
Input low time on
RBO/CAP1, RBlICAP2
Input period on
RBO/CAP1, RB1/CAP2
t:
"
Min
Typt
Max
Unit
tcH
0.5Tcy+20""
-
-
ns
tcl
0.5Tcy+20""
-
-
ns
tcpH
10"
-
-
ns
tcpl
10"
-
-
ns
tcpl
2 Tcy ""
N
-
-
ns
Symbol
Comments
where N=capture prescale
(1,4,16)
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Guaranteed by characterization
DS30073B-page 70
Pn6~~m~U1©lU"~ ~U1~iQJU"m©l~~IQJU1
1-238
© 1992 Microchip Technology Inc.
12.3.6 AC TEST LOAD AND TIMING CONDITIONS
FIGURE 12.3.6.1 INPUT LEVEL CONDITIONS
C
Port C, D & E pins:
~'------------'X
Vih = 2.4 V
,----------1, -,--I"
,
Data in valid
.. ,
,
------'I
-
Vil=O.4V
,
I
Data in invalid
All other input pins:
~__---------,X~C
,
, ,
I'"
,
Data in valid
"r,
------'
I
-
Vih = 0,9 VDD
Vii =0.1 VDD
I
,
I
Data in invalid
FIGURE 12.3.6.2 OUTPUT LEVEL CONDITIONS
VOH= 0.7 VDD
VDD/2
VOI= 0.3 VDD
I..
I
=x
I I
:--::J-,
..:,
Data out valid
~5V
__ j
.f___ Q.?~V
, - - - - - - - - , ::: '::: 0.40 V
:,
:/,
'---_ _ _ _ _ _-'-;-f::: ::: 0.40 V ,
I
{
, T
: . - - Data out invalid
'-4
4
I
I
~ ,"
, Output
hi-impedence
Output
driven
C
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~X'-_~-, ~, -:~,-~,",:,", :,- -__
I I
- - : ~ Rise time
- : ~ Fall time
FIGURE 12.3.6.3 LOAD CONDITIONS
load condition 1
VDD/2
load condition 2
~JRL
Pin
T
cg]1----
Cl
Pin
VSS
-.L Cl
T
VSS
Rl= 1K
Cl = 100 pF for C, D, E port outputs when
used as system bus
50 pF for all pins except OSC2 but
including C, D, E outputs as ports
25 pF for OSC2 output
DS30073B-page 71
© 1992 Microchip Technology Inc.
1-239
12.4 TIMING DIAGRAMS
FIGURE 12.4.1: TIMING DIAGRAM - EXTERNAL PROGRAM MEMORY READ
02
01
04
03
02
01
OSC1
ALE
OE
1~'..====;:------~iaIH2aIH -----'-----.~.r
-r------r~
1\-~c__--I_-----+I----+-'1J'
~taIH~.
------I~'____~I+.~~,,--,-i~\~,: tadZ20eL
I i:
1"1"
------------.J:ii4
..----i~~:toeH2adD
I'""
.:,',t!JI Addr out
Data in
•
J>------:'()\){'I,
..I i
---:--i
~
toel
Addr out I~
i~
'(I<};Z)(j;
tadV2alL ...
..I
tadV20eH..
*-
vxxxxt
--'------"Y:i:f;ff;:,;
1
l:r----~!-----
'L
!'III
AD<15:0>
1
---
talL2adi
toeH2adi
"1 "I
WR-~-------------------~~~--------1
1
tadV2all
tall2adl
tadZ20el
toeH2adD
tadV20eH
toeH2adi
talH
toel
talH2alH
DS30073B-page 72
= AD <15:0> (address) valid to ALE 0; address setup time
= ALE 0 to AD<15:0> (address) invalid; address hold time
=
AD <15:0> high impedance to DE 0
= DE * to AD <15:0> driven (address out)
= AD <15:0> (data) valid to DE *; data setup time
= DE * to AD <15:0> (data) invalid; data hold time
= ALE pulse width
= DE pulse width
= ALE * to ALE *; bus cycle period
II)
© 1992 Microchip Technology Inc.
1-240
FIGURE 12.4.2: TIMING DIAGRAM - EXTERNAL PROGRAM MEMORY WRITE
01
02:
aSC1
ALE
-t---------l(
AD<15:0> - l -_ _ _
04:
01
I
I
I
I
~
:
Ii
I
1
:
WR
03
r-talL2adl
/
:
:..:
\- . : .I'
j tadV2alll:
:..
twrL
i
dataoJt!
~_
J:
~
addrout:
I:
~:
""
I
02
-1.,
I ~i
1
I ' tadV2wrL
~
l..-.l
addrout
I
I twrH2adi
tadV2alL
= AD<15:0> (address) valid to ALE.1; address setup time
talLadl
= ALE.1 to address out invalid;-
tadV2wrL
= AD <15:0> (data) out valid to WR .1; data out setup time
twrH2adi
twrL
= WR
i to ad <15:0> (data) out invalid; data out hold time
= WR pulse width
FIGURE 12.4.3: TIMING DIAGRAM - INTERRUPT TIMING
1011021031041011021031041011021031041011021031041011021031041011021031041
I
I
I!
i
AD <15:0>
ALE~\
INT
I
I
I
I
I
l-i
\\\\\\\\\\\'0\1\
I
I
I
PC
~
I
VTB
VTPC
I
PC·l
Vector-Bus
i
I
I
I
~triL I
I
I
t,----::..:=..cl------'-I-----'--I--------'I
I
i
I
PC
i
I
PC+l
I
INST (NPC)
I Executed here I
I
I
i-~i
PC+1
I
Ir--\
I Vector_ PC I
I
I
I
I
I
r'
INST (PC-2)
INST (PC-I)
INST (PC)
I Executed here I Executed here I Executed here I
Internal signllS
I
C+l
I
"PC
i
I
~
NPC+l
I
I
I
\~---,---------;
!
I Must be set
Global -I , - - - - - - - - -I , - - - - - - - - , , - - - - - - - - ,I - - - - - - - , 1
by software
Enable bit I
~~--+------'~~
I
I
I
I
I
I
I
I
© 1992 Microchip Technology Inc.
I
I
~IT'IBl~~m~~©\IT'}f ~~~@IT'm©l~~@~
1-241
DS30073B-page 73
FIGURE 12.4.4: RESET TIMING
Processor held in
01
.
-102103104; 011 021 031 04; 011 021 03104; 011 i.....f---"'0-'-1-~-1,021 03
tmcL
MCLR
-r--------'
AD <15:0>
+------~
ALE
OE
~
_:
_ _ _ _ _J
-j----------,
Reset
1
1
INST (OOOOh) 1
Fetch
1
1
1
INST (0001 h)
1
1 Fetch
1 INST (0002h)
Execute
INST (OOOOh)
1 Execute
1 INST (0001 h)
Fetch
Fetch
Reset
INST (OOOOh)
1
FIGURE 12.4.5: TABLRD TIMING
; Q11 Q21 Q31 Q4; Q11 Q21 Q31 Q4; Q11 Q21 Q31 Q4; Q11 Q21 Q31 Q4;
1
1
1
1
1
AD <15:0>
Instruction
fetched
TABLRD
Instruction
executed
INST (PC-1)
NOP1
1
Data read cycle
1
1
1TABLRD cycle 11 TABLRD cycle 21
1
1
1
1
1
NOP2
1
NOP1
I
ALE
OE
DS30073B-page 74
Plm~ij liifu ~ ITll rllll':lf II ~~lr(())nln1cJl'itije))lrll
1-242
© 1992 Microchip Technology Inc.
FIGURE 12.4.6: TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
I 01
1
02 1 03 1 04 1 01 1 02 1 03 1 04 1 01 1 02 1 03 1 04 1 01 1 02 1 03 1 04 1 01 1 02 1 03 1 04 1 01 1 02 1 03 1 04 1
I
I
Instruction
fetched
TABLRD 1
Instruction
executed
INST (PC·1)
I
I
I
I
I
I TABLRD 2 I Data read cycle I
NOP1
I Data read cycle I
I
I
I
I
I
ITABLRD1 cycle11 TABLRD1 cycle21TABLRD2 cycle1 1TABLRD2 cycle21
NOP2
NOP1
ALE
OE
WR
rl··-1. -------+---------r--------rr--------+---------~------~
I
FIGURE 12.4.7: TABLWT TIMING
;01102103104; 011 021 031 04; 011 021 031 04; 011 021 031 04;
I
I
I
I
I
AD<15:0>~
Instruction
fetched
TABLWT
Instruction
executed
INST
(PC-1)
Nap 1
I Data write cycle I
I
I
ITABLWTcycle TABLWTcycie
11
21
I
I
I
ALE
'-----11~
I
Nap 2
Nap
1
I
I
I
I
~
OE
©
1992 Microchip Technology Inc.
DS30073B-page 75
1-243
FIGURE 12.4.8: TABlWT TIMING (CONSECUTIVE TABlWT INSTRUCTIONS)
I Qt! Q2! Q3! Q41 Q1! Q2! Q3! Q41 Q1! Q2! Q3! Q41 Q1! Q2! Q3! Q41 Q1! Q2! Q3! Q41 Q1! Q2! Q3! Q41
I
I
I
I
I
I
I
AD <15:0>
Instruction
fetched
Instruction
executed
TABLWT 1
TABLWT 2
I Data write cycle I
I Data write cycle I
NOP2
I
I
I
I
INST (PC-1) ITABLWT1 cycle1 1TABLWT1 cYcle2 1TABLWT2 cycle1 1TABLWT2 cycle2 1
NOP 1
NOP1
ALE
OE
I
~------4-------~----~~------~----~~------~
I
I
FIGURE 12.4.9: SLEEP/WAKE-UP THROUGH INT (IF, XT MODES)
tose1
:...
05C2
",4
tOST
=1024105C
~
JUliUUUUUU--::;K-+--t-=~lIUlJL,~
Hi-Z
I
I
05C1~'
,
~
01
02
Instruction
Fetched
Instruction
RestartOSC
(Wake-up through
INTinterrup1)
Executed
ALE
INT
Notes: 1. LF or Xl oscillator mode assumed.
2. INT interrupt is assumed to-be enable (INTDE=1) and global interrupt disable is assumed to be set (GLlNTD=I). Hence, program does not branch to interrupt vector
after wake-up.
3. tosel= time for oscillation amplitude to reach a level acceptable by the oscillator start-up timer. tOST"" oscillator start-up timer time-out delay = 1024 tose.
DS30073B-page 76
PIrIBl~~m~IiIl©lIr:lf ~1iIl~iVllrm©l~~(£:m
1-244
© 1992 Microchip Technology Inc.
FIGURE 12.4.10: SLEEPIWAKE·UP THROUGH INT (RC MODE)
OSC1~
QSel at HI-Z. held at logic '1' by external pull-up resistor
01
02
AD<1S:0>
Instruction
Fetched
Instruction
Executed
ALE
RestartOSC
(Wake-up through
lNTinterrupt)
INT
Notes: 1. RC oscillator mode assumed.
2. INT interrupt is assumed to be enable (INTDE",1) and global interrupt disable is assumed to be set (GLlNTO:1). Hence, program
not branch to interrupt vector
after wake-up.
3. tosc1 = time for oscillation amplitude to reach a level acceDtable by the oscillator start-up timer. lOST", osCillator. start-up timer time-out delay::: 1024 lose.
does
FIGURE 12.4.11 SYNCHRONOUS TRANSMISSION (MASTER/SLAVE)
RA5ITXI~i~ ---~f
--.j f4-
"''----
----~/
\-:<-:
~f4- tckrf
tckrf
RA4/RXI~i~ -----+---'x:i=========================n'--------f4- tckH2dtV
~
tdtrf
---1
~
FIGURE 12.4.12 SYNCHRONOUS RECEIVE (MASTER/SLAVE)
RA5ITXlCK
/
pin - - - - - - - '
,tdtV2ckL
:~
RA4/RXlDT
pin
"''----
\ i'---------~/
r'------------
~:
______~x'
!!"'~_---
tckL2dtl
----J~..,:
FIGURE 12.4.13: I/O PORT INPUT/OUTPUT TIMING (PORTA, PORTB)
Irul~I~I~lrul~I~I~i
OSC2/CLKOU,:l\~
I
:
WR_TO_PORT I
(internal)
:
RD PORT
(internal)
I
'
i~i ~
I
I
i tckH2n/V: ~
I
'
I
--t-----+J
Port output:
: ){
tckH2rxV
= CLKOUT t to, port data out valid
= Port data in valid before CLKOUT
Port sampled
'---
Ii
trxV2ckH
© 1992 Microchip Technology Inc.
:_trx~ckH
nJ.!i
:
t
IPw®~~mhll1illW~ ~1I1~mm1ill~~©1I1
1-245
DS30073B-page 77
13.0
PACKAGING INFORMATION
13.1 PACKAGE TYPE: 40-LEAD CERAMIC CERDIP DUAL IN-LINE WITH WINDOW (.600 MIL)
N
ll----:::----Il'
a~1
/I
1/
·1
14
Area
~---------01 ------~----~
Package Group: Ceramic Cerdip Dual In-line (COP)
Millimeters
Inches
Min
Max
Min
Max
a
0°
10°
0°
10°
A
A1
4.318
5.715
0.170
0.225
0.381
1.778
0.015
0.070
A2.
3.810
4.699
0.150
0.185
Aa
8
81
3.810
4.445
0.150
0.175
0.356
0.584
0.014
0.023
1.270
1.651
Typical
0.050
0.065
Typical
0.203
0.381
Typical
0.008
0.Q15
Typical
2.025
2.075
C
0
01
E
E1
e1
eA
es
51.435
52.705
48.260
48.260
15.240
15875
12.954
15.240
2.540
2.540
Notes
Notes
Symbol
Ref. A3
Reference
1.900
1.900
0.600
0.625
Reference
0.510
0.600
Typical
0.100
0.100
Typical
Reference
0.590
0.630
Reference
14.986
16.002
15.240
18.034
0.600
0.710
L
3.175
3.810
0.125
0.150
N
40
40
40
40
8
81
1.016
2.286
0.040
0.090
0.381
1.778
0.015
0.070
DS30073B-page 78
Ref. A3
I:DII€jllii~lru~wlllr)f IlrrllU'(i})lrrliTIl;illii:~~»)irli
1-246
© 1992 Microchip Technology Inc.
13.0
PACKAGING INFORMATION (CONT.)
13.2 PACKAGE TYPE: 4D-LEAD PLASTIC DUAL IN-LINE (.600 MIL)
N
P;,N01
Indicator - - Area
DGrrM
I
CI.--II
II
1---:::----1
t------- 0
S ~I"'..
~------"'"
o r - - - - - - - - h ----11--''---'-
' * " - - - - - 01 - - - - - - . . - 1
Package Group: Plastic Dual In-line (PLA)
Inches
Millimeters
Symbol
Min
Notes
Min
Max
CI.
0°
0°
10°
A
A1
-
-
0.200
0.381
0.015
-
A2
3.175
0.125
0.160
8
81
0.356
C
0
01
E
E1
e1
eA
es
Notes
0.014
0.022
1.270
Typical
0.050
0.070
Typical
0.2032
Typical
0.008
0.015
Typical
2.015
2.055
51.181
48.260
Reference
15.240
13.462
2.489
Typical
Reference
1.900
0.600
0.625
0.530
0.550
0.098
0.102
Typical
Reference
0.600
0.600
15.240
0.600
0.680
L
2.921
0.115
0.145
N
40
40
40
8
81
1.270
0.050
0.508
0.020
-
15.240
© 1992 Microchip Technology Inc.
~ti) m~ ~ m~ IID©lW)f ~ ull~tJI[!m«ll~~«}luli
1-247
Reference
1.900
DS30073B-page 79
13.0
PACKAGING INFORMATION (CONT.)
13.3 PACKAGE TYPE: 44-LEAD PLASTIC LEADED CHIP CARRIER (SQUARE)
(I
'/
D
::BI~~
D1
'''il~r::D-lA\.
,;;nnnnn
'
•
ii
.......~..:
ffit
~
~~~~~~~
A\.. -
E1 E
IEI+~oh~7®IAIF-G®
~i~50'
~... ~,
.02, 0
1.651
.065
R 1.14/0.64
::
.
QflA\.
--r. 1.651
.065
R 1.14/0.64
.0451.025
.0451.O?5
Package Group: Plastic Leaded Chip Carrier (PLCC)
Inches
Millimeters
Symbol
Min
Max
Notes
,
Min
Max
A
4.191
4.572
0.165
0.180
A1'
2.413
2.921
0.095
0.115
0
D1
17.399
17.653
0.685
0.695
16.510
16.662
0.650
0.656
D2
15.494
,16.002
0.610
0.630
D3
12.700
12.700
0.500
0.500
0.685
0.695
0.650
0.656
E
17.399
17.653
El
16.510
16.662
E2
15.494
16.002
E3
12.700
12.700
N
44
44
CP
-
0.1016 '
LT
0.203
DS30073B-pageSO
Reference
.,
,Reference
0.381
0.610
0.630
0.500
0.500
44
44
-
0.004
0.008
0.D15
1P'1f'(6~~m~ITil©lIrv ~lTilff(QJlf'm©l~~(QJ1Til
1-248
Notes
Reference
Reference
© 1992 Microchip Techndlogy Inc.
13.0
PACKAGING INFORMATION (CONT.)
13.4 PACKAGE TYPE: 44-LEAD METRIC PLASTIC QUAD FINE PITCH
(MQFP 10X10MM BODY 1.6/.01SMM LEAD FORM)
Index/.\.
areaLli1
1.S0Re!.
TYP4X
A
e~'A
Base
Plane
~
r~t
¥
.
Seating
Plane
Al
Symbol
a
A
A
A
b
C
D
D
D
E
E,
E,
e
L
N
GP
Min
0°
2.00
0.05
1.95
0.30,
0.15
12.95
9.90
8.00
12.95
9.90
8.00
.80
0.65
44
0.102
Package Group: Plastic MQFP
Millimeters
Min
Max
Notes
7°
0°
2.35
0.0787
0.25
0.0019
2.10
0.768
0.0118
0.45
Typical
0.18
.006
13.45
0.510
10.10
0.390
0.315
8.00
Reference
13.45
0.510
10.10
0.390
8.00
.315
Reference
I.8{
.0314
.0256
0.95
44
44
.004
Inches
Max
°
0.0925
0.0098
0.0827
0.0177
,007
0.530
0.398
NoteS
Tvolcal
0~315
Reference
0.530
0.398
.315
.0314
.0374
Reference
44
(Noles on following page)
© 1992 Microchip Technology Inc.
PIf'~~~m~Ii1©lIf')j' ~1i1~(QJlf'm©l~~(QJ1i1
1-249
DS30073B-page 81
Symbol List for Metric Plastic Quad Flat Pack Package Parameters
Symbol
Description of Parameters
a
Angular spacing between min and max lead positions measured at the guage plane
A
Distance between seating plane to highest point of body
A,
Distance between seating plane and base plane
A,
b
Width of terminals
C
Thickness of terminals
Distance from base plane to highest point of body
D,IE,
Largest overall package parameter including leads
DIE
Largest overall package parameter including leads
DjE,
e
Center of end lead to center of end lead
Linear spacing of true minimum lead position center line to center line
L
Length of terminal for soldering to a substrate
N
Total number of potentially useable lead positions
CP
Seating plane coplanarity
Notes
1.
All dimensioning and tolerancing conform to
ANSI Y14, BM-1582.
2.
Datum Plane Q±J is located at bottom of hold
parting line and coincident with bottom of lead,
where lead exits body.
3.
&
&
in,
8.
ffi
DatumsfAJ3]and!JTIto be determined at Datum
planeG±].
To be determined at seating plane
W.
&
Dimensions D1 and E1 do not include hold
protrusion. Allowable protrusion is 0.25 mm per
side. Dimensions D1 and E1 do not include hold
mismatch and are determined at Datum Plane
G±l.
&
These dimensions to be determined at Datum
plane tEO
All dimensions in millimeters.
Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm
total in excess of the b dimension at maximum
material condition. Dambar cannot be located on
the lower radius or the lead foot.
Exact shape of this feature is optional.
11.
N is the number of leads.
12.
Controlling parameters: milimeters
13.
All packages are gull wing lead form.
Details of pin 1 identifier are optional but must be
located within the zone indicated.
DS30073B-page 82
© 1992 Microchip Technology Inc.
1-250
Notes:
© 1992 Microchip Technology Inc.
DS30073B-page 83
1-251
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
3-Digit Pattern code for OTP
(blank for OTP and windowed
parts)
,--------11
PACKAGE:
PDIP
Cerdip window
PLCC
MOFP (Metric POFP)
=
TEMPERATURE
RANGE:
Blank
SPEED:
16=16Mhz
1
' - - -_ _ _ _ _ _ _ 1
P=
JW =
L=
PO =
I DEVICE:
' - - - - - - - - - - 11
D'C to + 7D'C
I = -4D'C to + 85'C
PIC17C42
"Information contained in this publication regarding device applications and the like is intended byway 015ugge5t;on only. No representation or warranty is given and no liability is assumed by Microchip
Technology Inc. with respect to the accuracy or use of such information. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval
by Microchip. The Microchip logo and name is a registered trademark of Microchip Technology Incorporated. PICPRO, PIC-ICE, PICPAK and PICMASTER are trademarks of Microchip Technology Inc.
IBM PC is atrademark of IBM Corporation. All rights reserved.'
DS3DD73B-page 84
pIJ(BiJ~m~iIl©l~1f
1-252
© 1992 Microchip Technology Inc.
Microchip
SECTION 2
DEVELOPMENT SYSTEMS
PICMASTER-16™
PICMASTER-17™
PICPAK-IiTM
PICPAK-17™
PICPRO-IITM
PRO MASTERTM
PICMASTER Universal In-Circuit Emulator System ................................... 2PICMASTER PIC®17CXX In-Circuit Emulator System ............................... 2- 5
PIC®16C5x Low-Cost Microcontroller Development System ...................... 2- 9
PIC®17C42 Evaluation/Development/Programmer Kit ............................... 2- 13
PIC®16C5x Microcontroller EPROM Programmer Unit... ............................ 2- 17
CMOS PIC® Microcontroller Programmer Unit ........................................... 2- 21
DS00018E
© 1992 Microchip Technology Inc.
2-i
Microchip
© 1992 Microchip Technology
DS00018E
2-ii
Microchip
PICMASTER™·16 System
PICMASTER Universal In-Circuit Emulator System
Real-time trace memory capture of 40 bits of information for each instruction cycle in an 8Kx40 trace buffer.
Trace region can range from 0 to 64K in any address
combinations.
SYSTEM FEATURES
General:
Complete Hi-Performance PC-based MSDOS Microcontroller Development System for the PIC16C5x
family and PIC17C42 (future release).
Real-time trace data can be captured and displayed
without halting emulation.
Unlimited number of hardware breakpoints can be set
anywhere in the program memory.
For use on PC compatible 286, 386, and 486 machines under Microsoft Windows® 3.X environment.
Extemal Break with "AND"/"OR" capability with internal breakpoints.
Assembler Software, Emulator System, and EPROM
Programmer unit, sample kit, and demonstration
hardware and software provide a complete
microcontroller product development environment.
Multiprocessor emulation capability. Up to eight
PICMASTER emulators can be synchronized on a
single PC, for multi-processor development.
Emulator System:
Extended 48-bit cycle counter.
• Trigger Output available on any range of addresses.
Hi-Performance In-Circuit Emulation of Microchip Microcontrollers.
• Full Symbolic Debug Capability. Symbolic display and
alter of all register files, special purpose registers,
stack registers, and bank registers.
Real-time instruction emulation.
Single and Multiple instruction step execution.
Selectable Internal Emulator Clock or User Target
(Prototype) System Clock.
• Program Memory emulation and memory mapping
capability up to 64K words. Instruction execution can
be mapped into either emulation memory or user
prototype memory.
User selectable internal or external Power Supply
(provided).
© 1992 Microchip Technology Inc.
DS30137C Page-1
2-1
PICMASTER·16 Development System
Operates as a Stand-alone Unit or in Conjunction with
a PC Compatible host system.
Provided with the PICMASTER System is a high performance real-time In-Circuit Emulator, a microcontroller
EPROM programmer unit, a macro assembler program,
and a simulator program. Sample programs are provided to help quickly familiarize the user with the development system and the PIC microcontroller line.
Performs READ, PROGRAM, and VERIFY functions
in Stand-alone mode. Uses Non-Volatile Program
Memory (EEPROM).
Coupled with the user's choice of text editor, the system
is ready for development of products containing any of
Microchip's microcontroller products.
• PC Host Software provides file display and editing, file
transfer to and from programmer unit, device serialization, and program voltage calibration.
A "Quick Start" PIC Product Sample Pak containing
user programmable parts is included for additional convenience.
Macro Assembler:
Microchip provides additional customer support to developers through an electronic Bulletin Board System
(BBS). Customers have access to the latest updates in
software as well as application source code examples.
Consult your local sales representative for information
on accessing the BBS system.
EPROM Programmer System:
PICPRO-II EPROM Programmer unit for all current
PIC16C5x products.
• Provides translation of Assembler source code to
object code for the PIC family of microcontrollers.
• Macro-assembly and conditional assembly capability.
Produces Object files, Listing files, Symbol files, and
special files required for symbolic debug with the
PICMASTER Emulator System.
Host System Requirements:
Binary 1 Hex output formats: INHX8S, INHX8M,
INHX16, and PICMASTER.
The PICMASTER has been designed as a real-time
emulation system with advanced features generally
found on more expensive development tools. The AT
platform and Windows 3.X environment was chosen to
best make these features available to you the end user.
To properly take advantages of these features,
PICMASTER requires installation on a system having
the following minimum configuration:
SYSTEM DESCRIPTION
The PICMASTER Universal In-Circuit Emulator System
is intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16C5X and PIC17CXX families. This introductory system currently supports the
PIC16C54, PIC16C55, PIC16C56 and PIC16C57 at
clock frequencies of 4 MHz and PIC17C42 at 16 MHz.
• PC AT compatible machine: 80286, 386SX, 386DX,
or 80486 with ISA or EISA Bus.
• EGA, VGA, 8514/A, Hercules graphic card (EGA or
higher recommended).
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors.
The universal architecture of the PICMASTER allows
expansion to support all new microcontroller architectures
with data and program memory paths to 16-bits.
MSDOS 1 PCDOS version 3.1 or greater.
Microsoft Windows® version 3.0 or greater operating
in either standard or 386 enhanced mode}.
• 1 Mby1e RAM (2 Mbytes recommended).
One 5.25" floppy disk drive.
The Emulator System is designed to operate on low-cost
PC compatible machines ranging from 80286-AT class
ISA-bus systems through the new 80486 EISA-bus
machines. The development software runs in the Microsoft Windows® 3.X environment, allowing the operator access to a wide range of supporting software and
accessories.
Approximately 10 Mby1es of hard disk (1 Mby1e required
for PIC MASTER, remainder for Windows 3.X system).
One 8-bit PC AT (ISA) 1/0 expansion slot (half size)
Microsoft® mouse or compatible (highly recommended).
D
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PICMASTER Emulator Pod
© 1992 Microchip Technology Inc.
DS30137C Page-2
2-2
PICMASTER-16 Development System
Emulator System Components:
file
The PICMASTER Emulator Universal System consists
primarily of 4 major components:
Help
Trace Memory Dump
00000:
Host-Interface Card: The PC Host Interface Card
connects the emulator system to a PC compatible
system. This high-speed parallel interface requires
a single half-size standard AT liSA slot in the host
system. A 37-conductor cable connects the interface card to the external Emulator Control Pod.
Emulator Control Pod: The Emulator Control Pod
contains all emulation and control logic common to
all microcontrollerdevices. Emulation memory, trace
memory, event and cycle timers, and tracelbreakpoint
logic are contained here. The Pod controls and
interfaces to an interchangeable target-specific emulator probe via a 14" precision ribbon cable.
Target-specific Emulator Probe: A probe specific
to microcontroller family to be emulated is installed
on the ribbon cable coming from the control pod.
This probe configures the universal system for emulation of a specific microcontroller. Currently, the
16C5x family, and the new PIC17C42 microcontrollers are supported. Future microcontrollerprobes
will be available as they are released.
PC Host Emulation Control Software: Host software necessary to control and provide a working
user interface is the last major component of the
system. The emulation software runs in the Windows 3.X environment, and provides the user with
full display, alter, and control of the system under
emulation. The Control Software is also universal to
all microcontroller families.
The Windows 3.X system is a multitasking operating
system which will allows the developer to take full
advantage of the many powerful features and functions of the PICMASTER system.
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
Dynamic Data Exchange (DOE), a feature of Windows 3.X, will be available in this and future versions
of the software. DOE allows data to be dynamically
transferred between two or more Windows programs. With this feature, data collected with
PICMASTER can be automatically transferred to a
spreadsheet or database program for further analysis.
Under Windows 3.X, up to eight PICMASTER emulators can run simultaneously on the same PC making development of multi-microcontroller systems
possible (e.g., a system containing a PIC16C5x
processor and a PIC17Cxx processor).
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The PICPRO-II Programmer will work in either standalone mode, or in PC host connected mode. Connected
to a PC host, many more features are available to the
user.
STAND-ALONE MODE
Stand-alone mode is useful in situations where a PC may
not be available or even required, such as in the field or
in a lab production environment. In stand-alone mode the
following programming functions are available:
VERIFY
VERIFY preforms two functions. For a programmed part,
the device in the programming socket will be compared to
the program data stored in internal EEPROM. If the data
and fuse settings are correct, VERIFIED will be displayed. VERIFY will also confirm that erased parts are
blank. A device in the socket will display ERASED if all
programmable locations are blank.
PROGRAM
In stand-alone mode, devices inserted into the programmer socket will be programmed with data currently stored
in EEPROM memory. Pressing the PROGRAM key will
cause the unit to program and verify both the program
memory and the device fuses. If all program successfully,
PGM OKAY will be displayed.
READ
A pre-programmed device placed in the programmer
socket can be read into the programmer unit by pressing
the READ key. Program and fuse data will be read and
stored into internal EEPROM. Various options exist with
the READ function.
PC HOST CONNECT MODE
PICPRO-II EPROM Programmer:
The PICPRO-II Programmer system included in the
PICMASTER Development System provides the product developer with the ability to program (transfer) the
developer'S software into PIC EPROM microcontrollers.
When the PICPRO-II is connected to a host PC system,
many more options and conveniences are available to the
user. Host mode allows full interactive control over the
PICPRO-II unit. A full screen, user-friendly software
program is provided to fully assist the user.
The programmer unit comes complete with accessories for use with a PC host computer. Supplied are
interface cables and connectors to a standard PC
parallel printer port (LPT), a wall mount power supply
unit, and host op~ating software.
As in stand-alone mode, parts may be Read, Programmed,
Blank checked, and Verified. Also, all fuses and 10
locations may be specified. In addition, other features
available in host-mode are:
© 1992 Microchip Technology Inc.
DS30137C Page-3
2-3
PICMASTER-16 Development System
Editing
Voo and VPp Adjust
A large screen buffer editing facility allows the user to
change and program location in either hexadecimal or
ASCII (text) modes. Complete program and fuse data
can be loaded and saved to DOS disk files. Files
generated by the Assembler program are directly loadable
into programmer memory.
The programming environment voltage settings of voo
max, Voo min, and Vpp can be set and altered only on PC
host mode. The voltage settings allow the user to program the part in the environment that the part will be
used. The part will be programmed at Voo max and
verified at Voo min. Vpp is the programming voltage.
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBER
DESCRIPTION
EM167001
Complete PICMASTER-16 System with 100 volt PICPRO-II Power Supply (1)
EM167002
Complete PICMASTER-16 System with 110 volt PICPRO-II Power Supply (2)
EM167003
Complete PICMASTER·16 System with 220 volt PICPRD-II Power Supply (3)
EM167004
Complete PICMASTER·16 System with 240 volt PICPRO·II Power Supply (4)
EM167010
Complete PICMASTER·16 System without PICPRO·II Programmer
Notes:
(1)
(2)
(3)
(4)
Used primarily
Used primarily
Used primarily
Used primarily
Japan
North, Central, and South America, Taiwan and Korea
Continental Europe, Hong Kong, Singapore and Scandinavia
England, Ireland, Scotland and R.O.C. (China)
DS30137C Page-4
© 1992 Microchip Technology Inc.
2-4
~.
Microchip
PICMASTER-17™ System
PICMASTER PIC®17CXX In-Circuit Emulator System
SYSTEM FEATURES
General:
• The PICMASTER-17 Development System is designed by Microchip Technology Incorporated and
manufactured in the U.S.A.
Complete Hi-Performance PC-based MSDOS Microcontroller Development System for the
PIC17Cxx family.
• For use on PC compatible 286, 386, and 486
machines under the Windows™ 3.X environment.
• Assembler Software, Emulator System, and
EPROM Programmer unit, sample kit, and EDP
demonstration board and software provide a complete microcontroller product development environment.
Emulator System:
• Universal In-Circuit Emulation pod supports emulation of PIC17CXX family. It can easily support
other PIC microcontroller products with the purchase of a low cost personality probe kit.
• Real-time emulation to 16 Mhz.
• Single and Multiple instruction step execution.
• Program Memory emulation and memory mapping
capability up to 64K words. Instruction execution
can be mapped into either emulation memory or
user prototype memory.
FIGURE 1: PICMASTER EMULATOR SYSTEM
EPROM Programmer System:
• PRO MASTERTM EPROM Programmer unit for all
Microchip PIC CMOS microcontrollers.
• Real.-time trace memory capture of 40 bits ·of information for each instruction cycle in an 8Kx40 trace
buffer. Trace region can range from 0 to 64K in any
address combinations.
• Operates as a Standalone Unit or in Conjunction with
a PC Compatible host system.
• Performs READ, PROGRAM, and VERIFY functions
in Standalone mode.
• Real-time trace data can be captured and displayed without halting emulation.
• Unlimited number of hardware breakpoints can be
set anywhere in the program memory.
External Break with "AND"f'OR" capability with
internal breakpoints.
• Multiprocessor emulation capability. Two or more
PICMASTER emulators can be synchronized on a
single PC for multi-processor development.
• PC Host Software provides file display and editing, file
transfer to and from programmer unit, device serialization, and program voltage calibration.
Macro Assembler:
PICASM-17 provides macro-assembly and conditional
assembly capability.
Provides translation of Assembler source code to
object code for the PIC family of microcontrollers.
• Extended 48-bit cycle counter.
• Trigger Output available on any range of addresses.
• Full Symbolic Debug Capability. Symbolic display
and alter of all register files, special purpose registers, stack, and bank registers.
• Produces Object files, Listing files, Symbol files, and
special files required for symbolic debug with the
PICMASTER Emulator System.
• Binary I Hex output formats: INHX8S, INHX8M,
INHX32.
• Selectable Internal Emulator Clock or User Target
(Prototype) System Clock.
• User selectable internal or external Power Supply
(provided).
© 1992 Microchip Technology Inc.
DS30145C-1
2-5
PICMASTER-17 PIC17CXX In-Circuit Emulator
SYSTEM DESCRIPTION
The PICMASTER Universal In-Circuit Emulator System
provides the product development engineer with a complete microcontrollerdesign tool selfor all microcontrollers
in the PIC16C5X and PIC17CXX families. The system
currently supports the PIC16C54, PIC16C55, PIC16C56,
PIC16C57 and PIC17C42.
Consult your local sales representative for information
on accessing Microchip Technology's Bulletin Board
System (BBS).
Host System Requirements
The PIC MASTER has been designed as a real-time
emulation system with advanced features generally
found on more expensive development tools. The AT
platform and Windows 3.X environment was chosen to
best make these features available to you the end user.
To properly take advantages of these features,
PICMASTER requires installation on a system having
the following minimum configuration:
The PICMASTER-17 System is configured to support
the PIC17C42 and related 17Cxx family members.lnterchangeable target probes allow the system to be easily
reconfigured for emulation of different processors. The
universal architecture olthe PICMASTER allows expansion to support all new microcontroller architectures with
data and program memory paths to 16-bits.
The Emulator System is designed to operate on low-cost
PC compatible machines ranging from 80286-AT class
ISA-bus systems through the new 80486 EISA-bus
machines. The development software runs in the Microsoft Windows 3.XTM environment, allowing the operator access to a wide range of supporting software and
accessories.
•
•
•
Provided with the PICMASTER System is a high performance real-time In-Circuit Emulator, a microcontroller
EPROM programmer unit, and a macro assembler program. Sample programs are provided to help quickly
familiarize the user with the development system and
the PIC microcontroller line.
Coupled with the user's choice of text editor, the system
is ready for development of products containing any of
Microchip's microcontroller products.
•
PC AT compatible machine: 80286, 386SX, 386DX,
or 80486 with ISA or EISA Bus
EGA, VGA, 8514/A, Hercules graphic card (EGA or
higher recommended).
MSDOS I PCDOS version 3.1 or greater.
Microsoft Windows version 3.0 or greater operating in
either standard or 386 enhanced mode).
1 Mbyte RAM (2 Mbytes recommended).
One 5.25" floppy disk drive.
Approximately 10 Mbytesof hard disk (1 Mbyte required
for PICMASTER, remainder for Windows 3.0 system)
One 8-bit PC AT (ISA) 1/0 expansion slot (half size)
Microsoft mouse or compatible (highly recommended).
Emulator System Components
A "Quick Start" PIC Product Sample Pak containing
user programmable parts is included for additional convenience.
Microchip provides additional customer support to developers through an electronic Bulletin Board System
(BBS). Customers have access to the latest updates in
software as well as application source code examples.
~
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1
Common Interface Card
PC Compatible Computer
(AT/ISA Bus) (for Industry Standard Architecture)
Logic Probes
DS30145C-2
~m~UI!©l~~ ~UI!limm©l~jrQlUl!
2-6
© 1992 Microchip Technology Inc.
PICMASTER-17 PIC17CXX In-Circuit Emulator
The PICMASTER Emulator Universal System consists
primarily of 4 major components:
PIC-MASTER- D;IICEWIN\DDEDEMO.OBJ
file
~nfigure
.setup
• Host-Interface Card: The PC Host Interlace Card
connects the emulator system to a PC compatible
system. This high-speed parallel interface requires
a single half-size standard AT / ISA slot in the host
system. A 37-conductor cable connects the interface card to the external Emulator Control Pod.
Emulator Control Pod: The Emulator Control Pod
contains all emulation and control logic common to
all Microchip CMOS microcontroller devices. Emulation memory, trace memory, event and cycle timers, and trace/breakpoint logic are contained here.
The Pod controls and interfaces to an interchangeable target-specific emulator probe via a 14" precision ribbon cable.
• Target-specific Emulator Probe: A probe specific
to microcontroller family to be emulated is installed
on the ribbon cable coming from the control pod.
This probe configures the universal system for emulation of a specific microcontroller. Currently, the
PIC16C5x family, and the new PIC17C42 microcontrollers are supported. Future microcontroller probes
will be available as they are released.
PC Host Emulation Control Software: Host software necessary to control and provide a working
user interface is the last major component of the
system. The emulation software runs in the Windows 3.X environment, and provides the user with
full display, alter, and control of the system under
emulation. The Control Software is also universal to
all microcontroller families.
The Windows 3.X System is a multitasking operating
system which allows the developer to take full advantage of the many powerful features and functions of
the PICMASTER system.
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
PICMASTER supports the window feature Dynamic
data Exchange (DOE). DOE allows data and commands to be dynamically transferred between two or
more Windows programs. With this feature, data
collected with PICMASTER can be automatically
transferred to a spreadsheet or database program
for further analysis.
Under Windows 3X, two or more PICMASTER emulators can run simultaneously on the same PC making
development of multi-microcontroller systems possible (e.g., a system containing a PIC16C5x.controlier
and a PIC17Cxx controller) or two or more of the
same controller family.
This allows data collected by PICMASTER to be automatically transferred to spreadsheets, data bases, or
other analytic tools for further evaluation. DOE also
allows automated control of PICMASTER which in turn
allows development of automated test suites, life testing
and production testers.
© 1992 Microchip Technology Inc.
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PRO MASTER EPROM Programmer
The PRO MASTER Programmer system included in the
PICMASTER Development System provides the product
developer with the ability to program (transfer) the
developer's software into PIC EPROM microcontrollers.
The programmer unit comes complete with accessories
for use with a PC host computer. Supplied are interface
cables and connectors to a standard PC serial port COM
1-4, power supply cable, and host operating software.
The PRO MASTER Programmer will work in either standalone mode, or in PC host connected mode. Connected
to a PC host, many more features are available to the
user as explained below.
STAND-ALONE MODE
Stand-alone mode is useful in situations where a PC may
not be available or even required, such as in the field or
in a lab production environment. In stand-alone mode the
following programming functions are available:
VERIFY
VERIFY preforms two functions. For a programmed part,
the device in the programming socket will be compared to
the program data stored in internal EEPROM. If the data
and fuse settings are correct, VERIFIED will be displayed. VERIFY will also confirm that erased parts are
blank. A device in the socket will display ERASED if all
programmable locations are blank.
PROGRAM
In stand-alone mode, devices inserted into the programmer socket will be programmed with data currently stored
in memory. Pressing the PROGRAM key will cause the
unit to program and verify both the program memory and
the device fuses. If all program successfully, PGM OKAY
will be displayed.
DS30145C-3
PICMASTER-17 PIC17CXX In-Circuit Emulator
READ
and 10 locations may be specified. Otherfeatures available in host-mode are:
A pre-programmed device placed in the programmer
socket can be read into the programmer unit by pressing
the READ key. Program and fuse data will be read and
stored into internal memory. Various options exist with
the READ function.
Editing
A large screen buffer editing facility allows the user to
change and program location in hexadecimal mode.
Complete program and fuse data can be loaded and
saved to DOS disk files. Files generated by the Assembler program are directly loadable into programmer
memory.
PC HOST CONNECT MODE
When the PRO MASTER is connected to a host PC
system, many more options and conveniences are
available to the user such as serialized code programming.
Host mode allows full interactive control over the PRO
MASTER unit. A full screen, user-friendly software program is provided to assist the user.
VDD and VPp Adjust
The programming environment voltage settings of VDD
max, VDD min, and VPp can be set and altered only on PC
host mode. The voltage settings allow the user to program the part in the environment that the part will be
used. The part will be programmed at VDD max and
verified at VDD min. VPp is the programming voltage.
As in stand-alone mode, parts may be Read, Programmed, Blank checked, and Verified. Also, all fuses
SALES AND SUPPORT - To order or to obtain information, e.g., on pricing or delivery, please use the listed
part numbers, and refer to the factory or the listed sales offices.
PART NUMBER
EM177001
EM177004
DESCRIPTION
PICMASTER PIC17CXX In-Circuit Emulator System
PICMASTER-17 System without PRO MASTER Programmer
DS30145C-4
© 1992 Microchip Technology Inc.
2-8
Microchip
PICPAK·IITM System
PIC®16C5x Low-Cost Microcontroller Development System
SYSTEM FEATURES
EPROM Programmer System
special files required for symbolic debug with the
PIC Emulator System.
Output formats: INHX8S, INHX8M and INHX16.
PICPRO-IiT EPROM Programmer unit for the
PIC16C5X Microcontroller family.
Operates as a Stand-alone Unit or in Conjunction
with a PC Compatible host system.
READS, PROGRAMS, and VERIFIES in Standalone mode.
Non-Volatile Program Memory for stand-alone or
field use where PC is not available.
PC Host Software provides file display and editing,
and transfer to and from Programmer unit.
M
PICSIM Simulator
Instruction-level Simulator of the PIC16C5x
microcontroller product family.
For PC compatible systems running the MSDOS
operating system.
• Full screen simulation user interface.
• Symbolic debugging capability.
• I/O stimulus input capability.
PI CALC Macro Assembler
"Quick Start" Sample Kit
Provides translation of Assembler source code to
object code for all PIC microcontrollers.
• Macro-Assembly capability.
Provides Object files, Listing files, Symbol files, and
Provides the User / Developer with a sample kit of
PIC parts for initial prototype use.
PICPRO-II'"
PIC@16CxxProgrammer
PROGRAM
VERIFY
READ
PICPAK-II
ERROR
16C5X DEVELOPMENT
SYSTEM
PIC16C551C57 DP'C16C541C56
~.
Microchip
Microchip
© 1992 Microchip Technology Inc.
DS30119C-1
2-9
PIC®16C5x PICPAK·II System
VERIFY
SYSTEM DESCRIPTION
VERIFY performs two functions. For a programmed
part, the device in the programming socket will be
compared to the program data stored in internal
EEPROM. If the data and fuse settings are correct,
VERIFIED will be displayed. VERIFY will also confirm
that erased parts are blank. A device in the socket will
display ERASED if all programmable locations are blank.
The PICPAK-II Development System provides the product development engineer with an alternative low-cost
introductory microcontroller design tool set for the
PIC16C5X family where full real-time emulation is not
required. The equipment in the PICPAK-II system operates
on any PC compatible machine running the MSDOS/PCDOS
operating system.
PROGRAM
Provided in the System is an MSDOS-based Software
Simulator program (PICSIM), a microcontroller EPROM
programmer unit (PICPRO-II), and a macro assembler
program (PICALC).
In stand-alone mode, devices inserted into the programmer socket will be programmed with data currently
stored in EEPROM memory. Pressing the PROGRAM
key will cause the unit to program and verify both the
program memory and the device fuses. If all program
successfully, PGM OKAY will be displayed.
Sample software programs to be run on the simulator
are provided to help the user to quickly become familiar
with the development system and the PIC microcontroller
line.
READ
A pre-programmed device placed in the programmer
socket can be read into the programmer unit by pressing
the READ key. Program and fuse data will be read and
stored into internal EEPROM. Various options exist with
the READ function.
The user need only provide his or her own preferred text
editor and the system is ready for development of end
products using the PIC16C54, 16C55, 16C56, or 16C57
microcontrollers.
A "Quick Start" PIC16C5X Product Sample Pak containing user programmable parts is included for additional convenience.
PC HOST CONNECT MODE
When the PICPRO-II is connected to a host PC system,
many more options and conveniences are available to
the user. Host mode allows full interactive control over
the PICPRO-II unit. A full screen, user-friendly software
program (PP2. EX E) is provided to fully assist the user.
Microchip provides additional customer support to developers through an electronic Bulletin Board System
(BBS). Customers have access to the latest updates in
software as well as application source code examples.
Consult your local sales representative for information
on accessing the BBS.
As in stand-alone mode, parts may be Read, Programmed, Blank checked, and Verified. Also, all fuses
and ID locations may be specified. In addition, other
features available in host-mode are:
PICPRO-IJ EPROM Programmer
The PICPRO-II Programmer system included in the
PICPAK-II Development System provides the product
developer with the ability to program user software into
PIC16C5x EPROM microcontrollers.
Editing
A large screen buffer editing facility allows the user to
change and program location in either hexadecimal or
ASCII (text) modes. Complete program and fuse data
can be loaded and saved to DOS disk files. Files
generated by the PICALC Assembler program are directly loadable into programmer memory.
The programmer unit comes complete with accessories
to be used with the PC host computer. Supplied are
interface cables and connectors to a standard PC parallel printer port (LPT), a wall mount power supply unit, and
host operating software (PP2.EXE).
Vooand.Vpp
The PICPRO-II Programmer will work in either standalone mode, or in PC host connected mode. Connected
to a PC host, many more features are available to the
user.
The programming environment voltage settings of VDD
max, VDD min, and VPp can be set and altered only on
PC host mode. The voltage settings allow the user to
program the part in the environment that the part will be
used. The part will be programmed at VDD max and
verified at VDD min. Vpp is the programming voltage.
STAND-ALONE MODE
Stand-alone mode is useful in situations where a PC
may not be available or even required, such as in the
field or in a lab production environment. In stand-alone
mode the following programming functions are available:
Parts Serialization
In PC host mode, the user can select up to 8 locations to
be programmed with a serial number or random security
code. Provisions for setting the address ranges, and
starting serial numbers are provided. The serial number
can use either incrementing serialization, or a random
number sequence. Serialization is also permitted with
parts already code-protected in the first 64 locations.
This allows end user customization while keeping proprietary, the program software code.
DS30119C-2
© 1992 Microchip Technology Inc.
2-10
PIC®16C5x PICPAK-II System
The PICSIM Simulator has the following features to
assist in the debugging of software/firmware for the
user:
PICPRO-II SPECIFICATIONS
DeviceTypes PIC16CS4,16CSS,16CS6, 16CS7
(oscillators: RC, XT, HS, LP)
Capacity
Program and fuse information for
one device to 2Kx12 (stored in
non-volatile EEPROM).
Enclosure
6.S"L x 3.7S"x 1.2S" epoxy coated
aluminum, rubber feet
Program Load/Save
Commands existto load assembled object file programs
into simulation memory. Conversely, programs may be
saved from program simulation memory back to the PC
disk.
Display & Alter
Weight
14 oz.
Power
±20 to 3SVDC. External AC/DC
power supply included. Lab power
cord with standard banana jacks.
Provisions are made to display and alter Program
Memory, Register Files, and status register bits. Also
simulator information such as cycle times, elapsed time,
and step count can be displayed.
Display
8 character LCD
Disassembler
Interface
Host PC Printer Port (auto-seeking of LPT1-LPT4 port)
Adapters
18 and 28 Pin ZIF DIP (standard)
18 and 28 lead SOIC (optional)
PP2.EXE provided on S.2S"
MSDOS 360K diskette.
Program memory can be disassembled showing both
hexadecimal data and instruction mnemonics for specified address ranges.
Software
Accessories
Utilitiy Functions
Various utility functions exist which assist the user in
operating the simulator. Memory and registers can be
cleared by command. Memory can be searched to find
occurances of instructions, register use, and ASCII data.
DB2S-RJ11 adapter for host PC,
RJ11 cable to PICPRO-II, User
Manual.
Symbolic Debugging
The simulator provides for symbolic referencing to aid
and simplify debugging. The symbol table may be
displayed. New symbols defined and unwanted symbols
deleted.
PICSIM Simulator
The PICSIM Simulator program provides the developer
with an instruction and limited I/O simulator software
program for debugging PIC16C5x assembler code.
Execution and Trace
During program execution, address ranges, registers,
register contents, and others can be traced.
The simulator is meant for use with smaller projects not
requiring preCise more extensive development equipment. Since the PIC16C5x architecture is essentially a
single tasking microcontroller without interrupts, many'
applications can be developed by using a simulator
program alone.
Breakpoints
The user may specify up to 512 breakpoints at anyone
time.
SALES AND SUPPORT
To order orto obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the listed
sales offices.
PART NUMBER
DESCRIPTION
DV16S001
Programmer/Applications Kit with 100V Power Supply (1)
DV16S002
Programmer/Applications Kit with 110V Power Supply (2)
DV16S003
Programmer/Applications Kit with 220V Power Supply (3)
DV16S004
Programmer/Applications Kit with 240V Power Supply (4)
AC164009
Optional 18 and 28-Lead SOIC Adapter
Notes:
(1)
(2)
(3)
(4)
Used primarily in Japan
Used primarily in North, Central and South America, Taiwan and Korea
Used primarily in Continental Europe, Hong Kong, Singapore and Scandinavia
Used primarily in England, Ireland, Scotland and R.O.C. (China)
DS30119C-3
© 1992 Microchip Technology Inc.
2-11
PIC®16C5x PICPAK·II System
© 1992 Microchip Technology Inc.
DS30119C-4
2-12
~.
Microchip
PICPAK-17™ System
PIC®17C42 Evaluation / Development / Programmer Kit
SYSTEM FEATURES
Low-cost Evaluation, Development, Demonstration,
and Programmer Kit for the PIC17C42
Microcontroller.
PIC17C42 signals are available to the prototyping
solder less terminal block. PIC17C42 1/0 lines RA,
RB, RC, RD, and RE available at terminal block.
• Provides a method for the design engineer to rapidly
evaluate, learn, and experiment with the Microchip
PIC17C42 Microcontroller.
RS232 Port can be connected to PIC17C42 serial
port (Rx, Tx, CTS, RTS, DSR lines supported).
Socketed PIC16C57 microcontroller generates
RESET and PROGRAM signals, and provides 1/0
stimulus to PIC17C42.
The PICEDP-17 Board provides for three execution
modes of the PIC17C42:
Microcontroller mode using internal
program memory only.
Requires a single +5VDC power supply. Lab cable
included.
Extended Microcomputer mode using
both internal memory and external
memory.
PC based software included: PICASM-17 Macro
Assembler, 110 stimulus, and demonstration
software with source code available.
Microprocessor mode using external
memory only.
"Quick Start" Sample Chip Kit included: PIC17C42
and 27C64 UV-erasable parts. Fully assembled
and ready to use.
On-board programming capability for the PIC17C42.
Microcontroller self-programs from socketed
external memory devices.
• Documentation: PIC17C42 datasheet, full schematics, Assembler manual, and applications booklet.
3 digit seven-segment LED display for use by the
PIC17C42 application.
© 1992 Microchip Technology Inc.
DS30144C-1
2-13
PICPAK-17 Evaluation / Development System
INTRODUCTION
External execution mode (EXTEX) operation
The PICPAK-17 is a low-cost development tool for use
with Microchip's PIC17C42 microcontroller. It comes
complete with the PIC EDP-17 Evaluation/Demonstration/Programmer board, lab power cable, PIC "Quick
Start" Sample product kit, PICASM-17 Assembler software, documentation, and source code for demonstration programs. The kit allows the user to quickly familiarize and experiment with the PIC17C42 chip.
In this mode, the PIC17C42 executes code from the two
external8-bit wide memories. The user can use 27HC64
or compatible EPROMs, 21256 or compatible SRAMs or
28HC64 EEPROMs. To use this mode, the user must
configure the PIC17C42 in microprocessor or extended
microcontroller mode.
In external execution mode the PIC17C42 is connected
to the 3-digit LED display which may be used to communicate with a terminal. Selected pins of the PIC17C42
pins are connected to the PIC16C57 for stimulus input
The EDP-17 board allows the PIC17C42 to execute
code from either two external8-bit wide EPROMs, or to
execute in microcomputer (single-chip) mode from its
own internal EPROM program memory. In addition, the
system provides a PROGRAMMING MODE, in which the
PIC 17C42 can program its own internal on-chip memory
by reading data from two external EPROMs. The
system is ideal for evaluation and quick prototyping of
simple applications.
Reset control
Two reset switches are provided for either a complete
system reset or a PIC17C42 reset. The system reset
switch resets the PIC16C57 which in turn issues the
proper reset Signals to the PIC17C42 depending on the
mode control switch settings. The RESET 17C42 key may
be used to reset the PIC17C42 at any time.
The user writes and assembles source code on any PC
compatible machine. A standard EPROM programmer
is used to place the PIC17C42 binary code into two
standard 27C64 8-bit EPROMs. The user can then
execute and verify the code in external execution mode.
Once verified, the code can be programmed into the
PIC17C42 with the push of a button. Finally, the user's
application can tried stand-alone with the PIC17C42
executing from its own internal memory.
Clock circuitry
Two crystal clock oscillators are provided on the system.
The 1 MHz oscillator (Y2) provides the clock source for
the PIC16C57. In the external and internal execution
modes the 10 MHz oscillator (Y1) provides the clock
source for the PIC17C42. Optionally, the crystal oscillators can be removed and an external clock source can
be provided using turrets J1 and J3 for their PIC17C42
and the PIC17C57 respectively.
An on board, pre-programmed PIC16C57 co-processor
provides a variety of stimulus signals to the PIC17C42
allowing the user to exercise the serial port, timer,
capture registers, and other peripheral functions. For
convenience, a solderless breadboard with easy access
to all PIC17C42 signals is providedforquickprototyping.
Display module
A three-digit seven-segment display module is provided
on board for use by the application's program. RB5, RB6
and RB7 outputs of the PIC17C42 controls the clock,
data and enable outputs to the display.
OPERATION
On power-up or after system RESET the PIC17C42 is put
into one of three modes based on a DIP switch setting:
PIC 17C42 Demonstration Software
• External execution mode (EXTEX) in which the
PIC17C42 executes from external memory.
• DEM01.ASM: Displays hex digits "0" through "F"
on LED display at 1 second intervals.
• Internal execution mode (INTEX) where the
PIC17C42 operates in the microcontroller mode
and executes from internal memory.
• DEM02.ASM: Displays digits "000" through "255"
on LED display.
• DEM03.ASM: Configures and exercises PIC
17C42 serial port in full duplex mode. Transmits a
preset pattern of data at a one second interval.
Displays incoming data on the LED display.
• Programming mode (PROGRAM) in which the
PIC17C42 programs its own internal EPROM and
its configuration fuses (auto-programming).
On power-up or after a system RESET the PIC16C57
senses the mode select switches and generates the
appropriate sequence of startup Signals to the PIC 17C42.
LED's indicate which modes are selected. The PIC16C57
also controls data buffers and latches associated with
the programming and external execution modes.
• Subroutines: Binary to BCD, Serial port RX, Serial
port TX, Delays (10 msec, 1 second), Hex to 7segment convert, 7-segment display.
PIC 16C57 Demonstration Software
Programming mode (PROGRAM) operation
Stimulus to PIC17C42: Serial async, serial sync,
baud rate generation, interrupt pulses, timer clock
generation, capture pulse generation.
In this mode the PIC17C42 reads the two external
EPROMs,RAM memory, or ROM emulator, one word at
a time, and programs the corresponding location in its
on-chip EPROM. Programming status LED's indicate
progress of the programming activity.
• Control of PIC17C42 PROGRAM modes.
Control of PIC17C42 RESET & EXECUTE modes.
DS30144C-2
© 1992 Microchip Technology Inc.
2-14
PICPAK-17 Evaluation / Development System
Event trigger switch to PIC17C42. Causes the
PIC16C57 microcontroller to generate the
stimulus event selected by #17.
Provides RESET and stimulus signals to
PIC17C42. PIC16C57 microcontroller firmware
can be re-programmed by the end user.
PIC17C42 microcontroller RESET switch.
PIC17C42 external memory sockets (2). For
external program execution, or for programming
of internal EPROM from external devices.
System RESET switch.
PIC17C42 device (socketed).
Fuse setting for PIC17C42 programming.
PIC17C42 crystal, 10 Mhz. (socketed).
7-segment LED display for PIC17C42.
PIC16C57 crystal, 1 Mhz. (socketed).
PROGRAM, EXECUTION, and POWER status
LED indicators.
PIC17C42 Execution mode switch (EXT, INT, or
PROGRAM).
ON I OFF power switch.
PIC16C57 1/0 stimulus mode selection.
Lab +5VDC power supply jack (male).
RS232 DB9 connector to PIC17C42.
Solderless prototype board area (1.25' x 3.5').
External clock oscillator input for PIC17C42.
PIC17C42 1/0 & Bus lines (RA,RB,RC,RD,RE).
External clock oscillator input for PIC16C57.
© 1992 Microchip Technology Inc.
DS30144C-3
2-15
PICPAK-17 Evaluation / Development System
SALES AND SUPPORT
To order orlo obtain information, e.g" on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBER
DV173001
DESCRIPTION
PICPAK-17 PIC17C42 Evaluation I Demonstation I Programmer System.
DS30144C-4
© 1992 Microchip Technology Inc.
2-16
~.
PICPRO·IITM
Microchip
PIC®16C5x Microcontroller EPROM Programmer Unit
SYSTEM FEATURES
SYSTEM DESCRIPTION
EPROM Programmer System
PIC PRO-II EPROM Programmer
PICPRO-II EPROM Programmer unit for the
PIC16C5X Microcontroller family.
Operates as a Stand-alone Unit or in Conjunction
with a PC Compatible host system.
READS, PROGRAMS, and VERIFIES in Standalone mode.
Non-Volatile Program Memory for stand-alone or
field use where PC is not available.
PC Host Software provides file display and editing,
and transfer to and from Programmer unit.
The PICPRO-II Programmer system provides the product developer with the ability to program user software
into PIC 16C5x EPROM microcontrollers.
The programmer unit comes complete with accessories
to be used with the PC host computer. Supplied are
interface cables and connectors to a standard PC
parallel printer port (LPT), a wall mount power supply
unit, and host operating software (PP2.EXE).
The PICPRO-II Programmer will work in either standalone mode, or in PC host connected mode. Connected
to a PC host, many more features are available to the
user.
PIC®16Cxx Programmer
PICPRO-II'"
PROGRAM
PIC16C551C57
0
VERIFY
ERROR
•
PIC16C54/C56
Microchip
FIGURE 1: PICPRO-II UNIT WITH DIP ADAPTER
DS30120C-1
© 1992 Microchip Technology Inc.
2-17
PIC®16C5x PICPRO-II Programmer Unit
STAND-ALONE MOPE
Voo and VPp
Stand-alone mode is .useful in situations where a PC
may not be available or even required, such as in the
field or in a lab production environment. In stand-alone
mode the following programming functions are available:
The programming environment voltage settings of Voo
max, Voo min, and VPp can be set and altered only on PC
host mode. The voltage settings allow the user to program the part in the environment that the part will be
used. The part will be programmed at voo max and
verified at Voo min. Vpp is the programming voltage.
VERIFY
VERIFY performs two functions. For a programmed
part, the device in the programming socket will be
compared to the program data stored in internal
EEPROM. If the data and fuse settings are correct,
VERIFIED will be displayed. VERIFY will also confirm
that erased parts are blank. A device in the socket will
display ERASED if all programmable locations are blank.
PROGRAM
In stand-alone mode, devices inserted into the programmer socket will be programmed with data currently
stored in EEPROM memory. Pressing the PROGRAM
key will cause the unit to program and verify both the
program memory and the device fuses. " all program
successfully, PGM OKAY will be displayed.
READ
A pre-programmed device placed in the programmer
socket can be read into the programmer unit by pressing
the READ key. Program and fuse data will be read and
stored into internal EEPROM. Various options exist with
the READ function.
PC HOST CONNECT MODE
Parts Serialization
In PC host mode, the user can select up to 8 locations to
be programmed with a serial number or random security
code. Provisions for setting the address ranges, and
starting serial numbers are provided. The serial number
can use either incrementing serialization, or a random
number sequence. Serialization is also permitted with
parts already code-protected in the first 64 locations.
This allows end user customization while keeping proprietary, the program software code.
PIC PRO-II SPECIFICATIONS
Device Types ..... PICI6CS4, 16CSS, 16CS6, 16CS7
(oscillators: RC, XT, HS, LP)
Capacity ............. Program and fuse information for
one device to 2Kx12 (stored in nonvolatile EEPROM).
Enclosure .......... 6.S.. L x 3.7S"x 1.25" epoxy coated
aluminum, rubber feet
Weight ................ 14 oz.
When the PICPRO-II is connected to a host PC system,
many more options and conveniences are available to
the user. Host mode allows full interactive control over
the PICPRO-II unit. A full screen, user-friendly software
program (PP2.EXE) is provided to fully assist the user.
As in stand-alone mode, parts may be Read, Programmed, Blank checked, and Verified. Also, all fuses
and 10 locations may be specified. In addition, other
features available in host-mode are:
Editing
A large screen buffer editing facility allows the user to
change and program location in either hexadecimal or
ASCII (text) modes. Complete program and fuse data
can be loaded and saved to DOS disk files. Files
generated by the PICALCTM Assembler program are
directly loadable into programmer memory.
Power ................. ±20 to 3SVDC. External AC/DC
power supply included. Lab power
cord with standard banana jacks.
Display ............... 8 character LCD
Interface ..•.......... Host PC Printer Port (auto-seeking
of LPTI-LPT4 port)
Adapters .......•.... 18 and 28 Pin ZIF DIP (standard)
18 and 28 lead SOIC (optional)
Software ............ PP2.EXE provided on S.2S" MSDOS
360K diskette.
Accessories ...... DB2S-RJll adapter for host PC,
RJll cable to PICPRO·II, User
Manual.
SALES AND SUPPORT
To order or to obtain information, e.g., on priCing or delivery, please use the listed part numbers, and refer to the listed
sales offices.
PART NUMBERS
PG16500t
PGt65002
PGt65003
PGt65004
ACt 64009
NOTES:
1)
2)
3)
4)
Used primarily
Used primarily
Used primarily
Used primarily
DESCRIPTIONS
Programmer Kit with
Programmer Kit with
Programmer Kit with
Programmer Kit with
Optional 18 and 28 -
tOO volt power supply (Note
t 10 volt power supply (Note
220 volt power supply (Note
240 volt power supply (Note
lead SOIC adapter
t)
2)
3)
4)
Japan
North, Central and South America, Taiwan and Korea
continental Europe, Hong Kong, Singapore and Scandinavia
England, Ireland, Scotland and R.O.C. (China)
DS30120C-2
© 1992 Microchip Technology Inc.
2-18
PIC®16C5x PICPRO·II Programmer Unit
Notes:
DS30120C-3
© 1992 Microchip Technology Inc.
2-19
PIC®16C5x PICPRO·II Programmer Unit
DS30120C-4
© 1992 Microchip Technology Inc.
2-20
PRO MASTER ™
Microchip
CMOS PIC® Microcontroller Programmer Unit
SYSTEM FEATURES
SYSTEM DESCRIPTION
EPROM Programmer System
PRO MASTER Programmer
• PRO MASTER Programmer unit for the PIC16CXX,
PIC17CXX Microcontroller family.
The PRO MASTER Programmer system provides the
product developer with the ability to program user
software into PIC16CXX, PIC17CXX CMOS
microcontrollers.
• Operates as a Stand-alone Unit or in Conjunction
with a PC Compatible host system.
The programmer unit comes complete with accessories
to be used with the PC host computer. Supplied are
interface cables and connectors to a standard PC serial
port, a universal input power supply unit, and host
operating software.
READS, PROGRAMS, and VERIFIES in Standalone mode.
• PC Host Software provides file display and editing,
and transfer to and from Programmer unit
• Communication Via RS-232
The PRO MASTER Programmer will work in either
stand-alone mode, or in PC host connected mode.
Connected to a PC host, many more features are
available to the user.
FIGURE 1: PRO MASTER DEVICE PROGRAMMER
© 1992 Microchip Technology Inc.
ADVfo'dNiCE
~NIFOIRMAT~ON
2-21
DS30087B-1
CMOS PIC® Microcontroller Programmer Unit
STAND-ALONE MODE
1-4) ports may be used. The communication is done at
19200baud to insure fast throughput. Communication
will be established with the PRO MASTER Device
Programmer prior to any transfers taking place.
Stand-alone mode is useful in situations where a PC
may not be available or even required, such as in the
field or in a lab production environment. In stand-alone
mode the following programming functions are available:
Serialization is done by generating a serialization file,
and then using that file to serialize locations in the PIC
microcontroller. Once a serialization file is generated, it
may be used over different programming sessions.
Serial numbers are automatically marked as used when
a PIC is programmed successfully with that serial number.
VERIFY
VERIFY performs two functions. For a programmed
part, the device in the programming socket will be
compared to the program data stored in internal memory.
If the data and fuse settings are correct, VERIFIED will
be displayed. VERIFYwili also confirm that erased parts
are blank. A device in the socket will display ERASED if
all programmable locations are blank.
Complete control over the programming environment is
also provided. Control over the programming and verify
voltage of Vdd insures that the PIC will perform in the
desired environment. Programming (Vpp) voltage is
also adjustable to insure complete compatibility with
future programming algorithms.
PROGRAM
In stand-alone mode, devices inserted into the programmer socket will be programmed with data currently
stored in memory. Pressing the PROGRAM key will
cause the unit to program and verify both the program
memory and the device fuses. If all program successfully, PGM OKAY will be displayed.
PRO MASTERTM SPECIFICATIONS
Device Types ..... PIC16CS4, 16CSS, 16CS6, 16CS7,
PIC16C71, PIC17C42
Capacity ............. Program and fuse information
for one device to 32Kx16 .
READ
A pre-programmed device placed in the programmer
socket can be read into the programmer unit by pressing
the READ key. Program and fuse data will be read and
stored into internal memory. Various options exist with
the READ function.
Enclosure .......... 9.0"L x 6.S"x 1.S" epoxy coated
aluminum, rubber feet
Weight ................ 16 oz.
Power ................. ±SV@ SOO mAo External AC/DC
power supply included.
PC HOST CONNECT MODE
Display ............... 20 character x 2 line LCD
The PRO MASTER provides a very user friendly user
interface which allows complete control over the programming session.
Interface ............. Host PC Serial Port (COM 1-4)
Adapters ............ Support current package types.
The PRO MASTER host software is a DOS windowed
environment with full mouse support to allow the user to
point and click when entering commands.
Software ............ DOS executable provided on
disk.
Accessories ...... DB9-DBB Serial Port Cable for
host PC, User Manual.
The Host Software communicates with the PRO MASTER via the serial port of the PC. Any of the four (COM
SALES AND SUPPORT
To order or to obtain information, e.g., on priCing or delivery, please use the listed part numbers, and refer to the
listed sales offices.
SOCKET PART NUMBER
AC164001
AC164002
AC164004
AC16400S
AC174001
AC174002
AC174003
DESCRIPTION
PIC16CS4 thru CS718 & 28 LD PDIP Socket Module
PIC16CS4 thru C5718 & 28 LD SOIC Socket Module (future release)
PIC16C71 18 Lead PDIP Socket Module
PIC16C71 18 Lead SOIC Socket Module
PIC17C42 40 Lead PDIP Socket Module
PIC17C42 44 Lead PLCC Socket Module (future release)
PIC17C4244 Lead QFP Socket Module (future release)
PROGRAMMER PART NUMBER DESCRIPTION
PG007001
Programmer Kit as described above
PG007002
Programmer Kit without power supply
(Target Socket Module must be specified, see notes)
Note: Only one socket module is included with shipment of Pro Master Programmer. Socket module must be specified attime of order
entry. Order by using individual socket module part number above. Additional socket modules may be purchased separately.
DS30087B-2
ADVANCE
~NFO:PiMAT~ON'
2-22
© 1992 Microchip Technology Inc.
Microchip
SECTION 3
SERIAL EEPROM PRODUCT SPECIFICATIONS
24C01A
24C02A
24C04A
24C16
24LC01
24LC02
24LC04
24LC16
59C11
85C72
85C82
85C92
93C06
93C46
93C56
93C66
93LC46/56/66
93LCS56
93LCS66
1K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 1
2K (256 X 8) CMOS Serial Electrically Erasable PROM ............................ 3- 9
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 17
16K (8x256x8) CMOS Serial Electrically Erasable PROM ......................... 3- 25
1K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 33
2K (256 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 41
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 49
16K (8 x 256 x 8) CMOS Serial Electrically Erasable PROM ..................... 3- 57
1 K (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM ............ 3- 65
1K (128 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 73
2K (256 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 81
4K (512 x 8) CMOS Serial Electrically Erasable PROM ............................. 3- 89
256 Bits (16 x 16) CMOS Serial Electrically Erasable PROM .................... 3- 97
1K (64 x 16) CMOS Serial Electrically Erasable PROM ............................. 3-105
2K (256 x 8 or128 x 16) CMOS Serial Electrically Erasable PROM .......... 3-113
4K (512 x 8 or 256 x 16) CMOS Serial Electrically Erasable PROM .......... 3-121
CMOS Serial Electrically Erasable PROM .................................................. 3-129
2K CMOS Serial Electrically Erasable PROM ........................................... 3-137
4K CMOS Serial Electrically Erasable PROM ............................................ 3-139
DS00018E
© 1992 Microchip Technology Inc.
3-i
Microchip
© <1992 Microchip Technology
DS00018E
3-ii
24C01A
Microchip
lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
•
•
•
•
•
•
DESCRIPTION
Low power CMOS technology
Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
1,000,000 ERASEIWRITE cycles (typical)
Data retention >40 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O·C to +70·C
-Industrial: -40·C to +85·C
-Automotive: -40·C to + 125·C
The Microchip Technology Inc 24C01A is a 1K bit
Electrically Erasable PROM. The device is organized as
128 x 8 bit memory with a two wire serial interface.
Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. Up to eight
24C01 As may be connected to the two wire bus. The
24C01A is available in the standard 8-pin DIP and a
surface mount SOIC package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AD
Vee
A1
TEST
A2
SCL
Vss
SDA
SDA
SO Package
SCL
AO
8
Vee
A1
2
7
TEST
A2
3
6
SCL
Vss
4
5
SDA
AO A1
A2
© 1992 Microchip Technology Inc.
3-1
DS11133E-1
24C01A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings·
All inputs and outputs w.r.t. Vss .................... -0.3 V to +7 V
Storage temperature ........................ -65'C to + 150'C
Ambient temp. with power applied ....... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .... +300'C
ESD protection on all pins ..................................... .4 kV
"'Notice: Stresses above those listed under "Maximum ratings" may cause
permanentdamagetothedevice. This is a stress rating only and functional
operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect
device reliability.
Function
AO, Ai, A2
Vss
SDA
SCL
Test
Vec
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Tie to Vee or Vss
+5 V Power Supply
Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive (E): Tamb = -40'C to + 125'C (Note 2)
DC CHARACTERISTICS
Parameter
Name
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
AO, A 1 & A2 pins:
High level input voltage
Low level input voltage
VIH
VIL
Vee - 0.5
-0.3
Vee + 0.5
0.5
V
V
Input leakage current
III
10
IJA
VIN = 0 V to Vcc
Output leakage current
ILO
10
IJA
VOUT = 0 V to Vcc
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
VINlVoUT = 0 V (Note 1)
Tamb = +25'C, 1 = 1 MHz
Operating current
leeo
3.5
mA
4.25
mA
leeR
750
IJA
FeLK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = O'C to 70'C
FeLK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = (I) and (E)
Vee = 5 V, Tamb= (e), (I) and (E)
Ices
100
IJA
read cycle
Standby current
Conditions
10L = 3.2 mA (SDA only)
SDA = SCL = Vee = 5 V
(no PROGRAM active)
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85'C, endurance is rated at 10,000 ERASEIWRITE cycles.
BUS TIMING START/STOP
SCL
SDA
-----+,1
STOP
START
© 1992 Microchip Technology Inc.
DS11133E-2
3-2
24C01A
AC CHARACTERISTICS
Parameter
Symbol
Typ
Min
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
SDA and SCl fall time
TR
1000
ns
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
a
ns
Data input setup time
TSU:DAT
250
ns
Data output delay time
STOP condition setup time
Bus free time
300
4700
ns
TBUF
4700
ns
Input filter time constant
(SDA and SCl pins)
Program cycle time
3500
TPD
TSU:STO
TI
.7N
Twc
Endurance
---
ns
100
ns
N
ms
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N = # of
bytes to be written
EIWCycles
100,000
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
SCL
.....-..
THD:DAT (receiver)
TPD
(transmitter)
FUNCTIONAL DESCRIPTION
The 24C01 A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C01 A works
as slave. Both, master and slave can operate as
transmitter or receiver but the master device determines
which mode is activated.
Up to eight 24C01 As can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus but require
different device codes than the 24C01 A (refer to section Slave Address).
© 1992 Microchip Technology Inc.
DS11133E-3
3-3
24C01A
BUS CHARACTERISTICS
The following bus protocol has been defined:
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per bit
of data.
Data transfer may be initiated only when the bus is not
busy.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The numberofthedata
bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.
During data transfer, the data line musl"remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Acknowledge
Bus not Busy CAl
Each receiving device, when addressed, is obliged to
generate an acknowledgeafterthe reception of each byte.
The master device must generate an extra clock pulse
which is associated with this acknowledge bit.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
Note: The 24C01 A does not generate any acknowledge
bits if an internal programming cycle is in progress.
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way that
the SDA line is stable lOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and
hold times must be taken into account. A master must
signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out
olthe slave. In this case, the slave must leave the data line
HIGH to enable the master to generate the STOP condition.
Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state olthe data line represents valid data when, after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal.
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCl
(8)
--+--4--..
SDA
START CONDITION
DATA ALLOWED
ADDRESS
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
© 1992 Microchip Technology Inc.
DS11133E-4
3-4
24C01A
SLAVE ADDRESS
word address and will be written into the address pointer
ofthe24C01A.Themostsignificantbitofthewordaddress
is a "Do Not Care" value for the 24C01 A. After receiving
the acknowledge of the 24C01 A, the master device
transmits the data word to be written into the addressed
memory location. The 24C01 A acknowledges again and
the master generates a STOP condition. This initiates the
intemal programming cycle of the 24C01 A. (See Figure
3).
ThechipaddressinputsAO,A1 andA2ofeach24C01 Amust
beextemailyconnectedtoeitherVccorground(Vss),assigning
to each 24C01 A a unique 3-bit address. Up to eight
24C01As may be connected to the bus. Chip selection is
then accomplished through software bysettingthebitsAO,
Aland A2 of the slave address to the corresponding
hardwired logic levels of the selected 24C01 A.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
cqde (1 01 0) forthe 24C01 A, followed by the chip address
bits AO, A1 and A2.
PAGE PROGRAM MODE
The eighth bit of slave address determines if the master
device wants to readorwritetothe 24C01 A. (See Figure2.)
Toprogramthe24C01 A, themastersends addresses and
datatothe24C01Awhichistheslave, (see Figure3). This
is done by supplying a START condition followed by the 4bit device code, the 3-bit slave address, and the 'A/W bit
which is defined as a logic LOW for a write. This indicates
to the addressed slave that a word address will follow so
the slave outputs the acknowledge pulse to the master
during the ninth clock pulse. When the word address is
received by the 24C01 A, it places it inthe lowerS bitsofthe
address pointer defining which memory location is to be
written. (One do not care lSit and seven address bits.) The
24C01 A will generate an acknowledge after every S-bits
received and store them consecutively in a 2-byte RAM
until a STOP condition is detected which initiates the
intemal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C01 A will terminate the
write cycle. This does not affect eraselwrite cycles of the
EEPROM array.
The 24C01 A monitQrs the bus for its corresponding slave
address all the time. It generates an acknowledge bit ifthe
slave address was true and it is not in a programming
mode.
FIGURE 2 • SLAVE ADDRESS
ALLOCATION
START
READIWRITE
"'""
/"
I :
o
o I A2
"
I I Ao"l
If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
A1
The internal, completely self-timed PROGRAM cycle
startsafterthe STOP condition has been generated by the
master and all received (up to two) databyteswill bewritten
in a serial manner.
BYTE PROGRAM MODE
In this mode the master sends addresses and one data
byte to the 24C01 A.
The PROGRAM cycle takes N milliseconds, whereby N is
the number of received data bytes (N max'= 2).
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RJW bit, which is logic
LOW, are placed onto the busby the master. Thisindicates
to the addressed 24C01 A that a byte with a word address
will follow after it has generated an acknowledge bit.
Therefore, the next byte transmitted by the master is the
FIGURE 3 • PROGRAM MODE (ERASEIWRITE)
START
A
ACKNOWLEDGES FROM SLAVE
DATA BYTE N
DATA BYTE 1
A STOP
P
© 1992 Microchip Technology Inc.
DSl1133E-5
3-5
24C01A
READ MODE
This mode illustrates master device reading data from the
24C01A.
from the addressed location on tothe SDA pin, increments
the address pointer and, if it receives an acknowledgefrom
the master, will transmit the next consecutive byte. This
autoincrementsequence is only aborted when the master
sends a STOP condition instead of an acknowledge.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must be
written to.) During this period the 24C01 A generates the
necessary acknowledge bits as defined in the appropriate
section.
Note: lithe master knows where the address pointer is, it
can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
The master now generates another START condition and
transmits the slave address again, except this time the
readlwrite bit is set into the read mode. After the slave
generates the acknowledge bit, it then outputs the data
In all modes, the address pOinter will automatically increment from the end olthe memory block (128 byte) backto
the first location in that block.
FIGURE 4 - READ MODE
AUTO INCREMENT
WORD ADDRESS
R
PIN DESCRIPTION
AD. Al and A2 Chip Address Inputs
SCL Serial Clock
The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if
the compare is true.
This input is used to synchronize the data transfer from
and to the device.
Up to eight 24C01 As can be connected to the bus.
Must be connected to either Vss or Vcc.
These inputs must be connected to either Vss or Vcc.
SDA Serial Address/Data Inpyt/Oytput
Notes:
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
24C01 A page is 2 bytes long.
For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 24C01 A has only one
block (128 bytes).
© 1992
DS11133E-6
3-6
Microchip Technology Inc.
24C01A
NOTES:
© 1992 Microchip Technology Inc.
DS11133E-7
3-7
24C01A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
J
P
PACKAGE:
SN
SM
I
I
TEMPERATURE
RANGE:
Blank
I
E
DEVICE:
24C01A
24C01 AT
CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)
0' Cto+70' C
-40' C to +85' C
-40' C to +125' C
1K CMOS Serial EEPROM
1K CMOS Serial EEPROM
(in Tape & Reel)
© 1992 Microchip Technology Inc.
DS11133E-8
3-8
~.
24C02A
Microchip
2K (256
X
8) CMOS Serial Electrically Erasable PROM
FEATURES
•
•
•
•
•
•
DESCRIPTION
Low power CMOS technology
Organized as one block of 256 bytes (256 x 8)
Hardware write 'protect for upper 1K (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
1,000,000 ERASEIWRITE cycles (typical)
Data retention >40 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O'C to +70'C
- Industrial: -40'C to +85'C
- Automotive: -40'C to + 125'C
The Microchip Technology Inc. 24C02A is a 2K bit
Electrically Erasable PROM. The device is organized as
256 x 8 bit memory with a two wire serial interface.
Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special
feature allows a write protection for the upper 1K (128 x
8). The 24C02A also has a page-write capability for up
to 2 bytes of data. Up to eight 24C02As may be
connected to the two wire bus. The 24C02A is available
in the standard 8-pin DIP and a surface mount SOIC
package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AO
Vee
A1
wp
A2
SCL
Vss
SDA
SDA
SO Package
AO
Vee
A1
wp
A2
SCL
Vss
SDA
SCL
ADA1 A2WP
© 1992 Microchip Technology Inc.
3-9
DS11139E-1
24C02A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
Name
All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65°C to + 150°C
Ambient temp. with power applied ..... -65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ..................................... 4 kV
Function
AO,Al,A2
Vss
SDA
SCl
WP
Vcc
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vce = +5 V (±10%)
Commercial (C): Tamb
Industrial
(I): Tamb
Automotive (E): Tamb
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.8
4.5
V
SCl and SDA pins:
High level input voltage
low level input voltage
low level output voltage
VIH
Vil
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
AD, Al & A2 pins:
High level input voltage
low level input voltage
VIH
Vil
Vee - 0.5
-0.3
Vee + 0.5
0.5
V
V
= DoC to +70°C
= -40'C to +85°C
= -40°C to + 125°C
(Note 2)
Conditions
IOl
= 3.2 mA (SDA only)
= 0 V to Vcc
Input leakage current
III
10
JJ.A
VIN
Output leakage current
IlO
10
JJ.A
VOUT
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
VINNoUT = 0 V (Note 1)
TAMS = 25°C, f = 1 MHz
Operating current
Iceo
3.5
mA
4.25
mA
leeR
750
IlA
FelK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = DoC to 70°C
FelK = 100 kHz, program cycle
time = 1 ms, Vce = 5 V,
Tamb = (I) and (E)
Vee = 5 V, Tamb = (C), (I) and (E)
Ices
100
IlA
read cycle
Standby current
= 0 V to Vcc
SDA = SCl = Vee = 5 V
(no PROGRAM active)
C.-.r
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85°C, endurance is rated at 10,000 ERASEIWRITE cycles.
BUS TIMING START/STOP
SCl
SDA - - - - - ; - " ' 1
START
STOP
DS11139E-2
© 1992 Microchip Technology Inc.
3-10
24C02A
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
TR
1000
ns
SDA and SCl fall time
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
TPD
300
TSU:STO
4700
ns
TBUF
4700
ns
Data output delay time
STOP condition setup time
Bus free time
Input filter time constant
(SDA and SCl pins)
Program cycle time
ns
3500
TI
.7N
Twc
Endurance
---
100,000
ns
100
ns
N
ms
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N
of bytes to be written
=#
E/WCycies
Note 1: As transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
SCL
THO:DAT (receiver)
TPD
(transmitter)
SDA
_TBUF
FUNCTIONAL DESCRIPTION
The 24C02A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C02A works
as slave. Both, master and slave can operate as
transmitter or receiver but the master device determines
which mode is activated.
Up to eight 24C02As can be connected to the bus,
selected by the AO, A 1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 24C02A (refer to section
Slave Address).
© 1992 Microchip Technology Inc.
DS11139E-3
3-11
24C02A
BUS CHARACTERISTICS
The following bus protocol has been defined:
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Acknowledge
Bus not Busy lA)
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Note: The 24C02A does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 1· DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(A)
(8)
--t---1h
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS11139E-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-12
24C02A
SLAVE ADDRESS
The chip address inputs AO, A 1 and A2 of each 24C02A
must be externally connected to either Vee or ground
(Vss), assigning to each 24C02A a unique 3-bit address.
Uptoeight24C02As maybe connectedtothe bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24C02A.
indicates to the addressed 24C02A that a byte with a
word address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by
the master is the word address and will be written into the
address pointer of the 24C02A. After receiving the
acknowledge of the 24C02A, the master device transmits the data word to be written into the addressed
memory location. The 24C02A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C02A.
(See Figure 3.)
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C02A, followed by the chip address bits AO, A1 and A2.
PAGE PROGRAM
The eighth bit of slave address determines if the master
device wants to read or write to the 24C02A. (See Figure
2.)
To program the 24C02A, the master sends addresses
and data to the 24C02A which is the slave. (See Figure
3.) This is done by supplying a START condition
followed by the 4-bit device code, the 3-bit slave address, and the RiW bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C02A, it places it in the lower 8 bits of the address
pointer defining which memory location is to be written.
The 24C02A will generate an acknowledge after every
8 bits received and store them consecutively in a 2-byte
RAM until a STOP condition is detected which initiates
the internal programming cycle. If more than 2 bytes are
transmitted by the master, the 24C02A will terminate the
write cycle. This does not affect erase/write cycles olthe
EEPROM array.
The 24C02A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.
FIGURE 2· SLAVE ADDRESS
ALLOCATION
START
/"
MODE
READIWRITE
'-....
lithe master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
BYTE PROGRAM MODE
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will be
written in a serial manner.
In this mode the master sends addresses and one data
byte to the 24C02A.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RiW bit, which is logic
LOW, are placed onto the bus by the master. This
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).
FIGURE 3 • PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE
p
© 1992 Microchip Technology Inc.
DS11139E-5
3-13
24C02A
WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin of the 24C02A is connected to
Vee (+5 V). The 24C02A will accept slave and word
addresses but if the memory accessed is write protected
by the WP pin, the 24C02A will not generate an acknowledge after the first byte of data has been received, and
thus the program cycle will not be started when the stop
condition is asserted.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
READ MODE
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
This mode illustrates master device reading data from
the 24C02A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
although this is a read mode the address pointer must be
written to.) During this period the 24C02A generates the
necessary acknowledge bits as defined in the appropriate section.
Note: In all modes, the address pointer will automatically
increment from the end of the memory block (256 byte)
back to the first location in that block.
FIGURE 4 - READ MODE
R
AUTO INCREMENT
WORD ADDRESS
PIN DESCRIPTION
AQ, A1 and A2 Chip Address Inputs
of memory (addresses 080-0FF) will not be executed.
Read operations are possible.
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
If tied to Vss, normal memory operation is enabled (read/
write the entire memory OOO-OFF).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.
Up to eight 24C02As can be connected to the bus.
These inputs must be connected to either Vss or Vee.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
Notes:
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
1) A "page" is defined as the maximum number of bytes
that can be programmed in a Single write cycle. The
24C02A page is 2 bytes long.
SCl Serial Clock
2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pOinter can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 24C02A has only one
block (256 bytes).
This input is used to synchronize the data transfer from
and to the device.
WP Write Protection
This pin must be connected to either Vss or Vee.
Iflied to Vee, PROGRAM operations onto the upper half
DS11139E-6
© 1992 Microchip Technology
3-14
Inc.
24C02A
NOTES:
DS11139E-7
© 1992 Microchip Technology Inc.
3-15
24C02A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
J
P
PACKAGE:
SN
SM
I
TEMPERATURE
RANGE:
DEVICE:
Blank
I
E
24C02A
24C02AT
DS11139E-8
CERDIP
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
PLASTIC SOIC (0.207 mil Body)
0' Cto+70' C
-40' C to +85' C
-40' Cto +125' C
2K CMOS Serial EEPROM
2K CMOS Serial EEPROM
(in Tape & Reel)
© 1992 Microchip Technology Inc.
3-16
24C04A
Microchip
4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
•
•
•
•
•
DESCRIPTION
Low power CMOS technology
Organized as two blocks of 256 bytes (2 x 256 x 8)
Hardware write protect for upper block
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
1ms write cycle time for single byte
1,000,000 ERASEIWRITE cycles (typical)
Data retention >40 years
8-pin DIP/SOIC packages
Available for extended temperature ranges:
-Commercial: O'C to +70'C
-Industrial: -40'C to +85'C
-Automotive: -40'C to + 125'C
The Microchip Technology Inc. 24C04A is a 4K bit
Electrically Erasable PROM. The device is organized as
two blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A
special feature allows a write protection for the upper
256 byte block. The 24C04A also has a page-write
capability for up to 8 bytes of data. Up to four 24C04As
may be connected to the two wire bus. The 24C04A is
available in the standard 8-pin DIP and 8-pin surface
mount SOIC package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AO
Vee
Al
wp
A2
SCL
Vss
SDA
SDA
SO Package
AO
Vee
Al
wp
A2
Vss
3
SCL
AD A1 A2WP
SCL
SDA
© 1992 Microchip Technology Inc.
3-17
DS1114DE-1
24C04A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins .................................... .4 kV
Name
Function
AO
No Function, Must be
connected to Vee or vss
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+5 V Power Supply
A1,A2
Vss
SDA
SCL
WP
Vee
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive: (E): Tamb = -40'C to + 125'C (Note 2)
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
Vil
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
A1 & A2 pins:
High level input voltage
Low level input voltage
VIH
Vil
Vee - 0.5
-0.3
Vee + 0.5
0.5
V
V
Conditions
IOl = 3.2 mA (SDA only)
Input leakage current
III
10
IlA
VIN = 0 V to Vcc
Output leakage current
ILO
10
!lA
VOUT = 0 V to Vcc
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
VINNoUT = 0 V (Note 1)
T amb = +25'C, 1 = 1 MHz
Operating current
leeo
3.5
mA
4.25
mA
leeR
750
IlA
FelK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = O'C to +70'C
FelK = 100 kHz, program cycle
time = 1 ms, Vee = q V,
Tamb = (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)
Ices
100
IlA
read cycle
Standby current
SDA = SCL = Vee = 5 V
(no PROGRAM active)
Note 1: ThiS parameter IS periodically sampled and not 100% tested.
Note 2: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles
BUS TIMING START/STOP
sel
SDA
-----+-,1
STOP
START
DS11140E-2
©1992 Microchip Technology Inc.
3-18
24C04A
AC CHARACTERISTICS
Parameter
Symbol
Min
Clock frequency
FCLK
Clock high time
THIGH
4000
Clock low time
TLOW
4700
SDA and SCl rise time
Typ
Max
Units
100
kHz
ns
ns
TR
1000
ns
TF
300
ns
SDA and SCl fall time
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
Data output delay time
TPD
300
TSU:STO
4700
ns
TBuF
4700
ns
STOP condition setup time
Bus free time
Input filter time constant
(SDA and SCl pins)
Program cycle time
3500
TI
Twc
Endurance
---
.7N
ns
100
ns
N
ms
100,000
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N = #
of bytes to be written
EIWCycles
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
SCL
_
THD:DAT (receiver)
TpD
(trensmitter)
FUNCTIONAL DESCRIPTION
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C04A works
as slave. Both, master and slave can operate as
transmitter or receiver but the master device determines
which mode is activated.
Up to four 24C04As can be connected to the bus,
selected by the Aland A2 chip address inputs. AO must
be tied to Vee or Vss. Other devices can be connected
to the bus but require different device codes than the
24C04A (refer to section Slave Address).
©1992 Microchip Technology Inc.
DSlll40E-3
3-19
24C04A
BUS CHARACTERISTICS
The following bus protocol has been defined:
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Data transier may be initiated onlywhen the bus is not
busy.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Acknowledge
Bus not Busy tA)
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
Note: The 24C04A does not generate any acknowledge
bits if an internal programming cycle is in progress.
A HIGH to lOW transition ofthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must Signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Stop Data Transfer (Cl
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (ol
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(8)
--+---t"""'
SDA
START CONDITION
DATA ALLOWED
ADDRESS
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
©1992 Microchip Technology Inc.
DS11140E-4
3-20
24C04A
SLAVE ADDRESS
word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by
the master is the word address and will be written into the
address pointer of the 24C04A. After receiving the
acknowledge of the 24C04A, the master device transmits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This
initiates the internal programming cycle of the 24C04A.
(See Figure 3.)
The chip address inputs A1 and A2 of each 24C04A
must be externally connected to either Vcc or ground
(Vss) , assigning to each 24C04A a unique2-bit address.
Up to four 24C04As may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits A 1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
24C04A. AO is not used and must be connected to either
Vcc orVss.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C04A, followed by the chip address bits A 1 and A2. The seventh bit of that byte (BA)
is used to select the upper block (addresses 100-1 FF)
orthe lower block (addresses OOo-OFF) of the 24C04A.
PAGE PROGRAM
To program the 24C04A, the master sends addresses
and data to the 24C04A which is the slave (see Figure
3). This is done by supplying a START condition
followed by the '!:.bit device code, the 3-bit slave address, and the R/W bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the 24C04A,
it places it in the lower 8 bits of the address pOinter
defining which memory location is to be written. (The BA
bit transmitted with the slave address is the ninth bit of
the address pointer.) The 24C04A will generate an
acknowledge after every 8-bits received and store them
consecutively in an 8-byte RAM until a STOP condition
is detected which initiates the internal programming
cycle. If more than 8 bytes are transmitted by the master,
the 24C04A will roll over and overwrite the data beginning with the first received byte. This does not affect
erase/write cycles of the EEPROM array and is accomplished as a result of only allowing the address
registers bottom 3 bits to increment while the upper 5 bits
remain unchanged.
The eighth bit of slave address determines if the master
device wants to read orwriteto the 24C04A. (See Figure
2.)
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.
FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START
/'
I
/
/
/
/
:
READIWRITE
"""
S:LAV~ AD~RESf :
(RiWl
\
I I
1
0
0
A2
A1
A
\
\
SA
MODE
~I
If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
BYTE PROGRAM MODE
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to eight) data bytes will
be written in a serial manner.
In this mode, the master sends addresses and one data
byte to the 24C04A.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the R1W bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 24C04A that a byte with a
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8).
FIGURE 3 • PROGRAM MODE (ERASEIWRITE)
ACKNOWLEDGES FROM SLAVE
p
©1992 Microchip Technology Inc.
DS11140E-5
3-21
24C04A
WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin of the 24C04A is connected to
Vcc (+5 V). The 24C04A will accept slave and word
addresses but if the memory accessed is write protected
by the WP pin, the 24C04A will not generate an acknowledge after the first byte of data has been received, and
thus the program cycle will not be started when the
STOP condition is asserted.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
READ MODE
Note: If the master knows where the address pointer is,
it can begin the read sequence at pOint 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
This mode illustrates master device reading data from
the 24C04A.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 24C04A generates
the necessary acknowledge bits as defined in the appropriate section.
Note: In all modes, the address pointer will not incrementth rough a block (256 byte) boundary, but will rotate
back to the first location in that block.
FIGURE 4 - READ MODE
ACKNOWLEDGES FROM MASTER RECEIVER
R/iiii
R
AUTO INCREMENT
WORD ADDRESS
PIN DESCRIPTION
AQ
WP Write Protection
This pin must be connected to either Vcc or VSS.
This pin must be connected to either vcc or Vss.
A1. A2 Chip Address Inputs
If tied to Vcc, PROGRAM operations onto the upper
memory block (addresses 100-1 FF) will not be executed. Read operations are possible.
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
If tied to Vss, normal memory operation is enabled (read/
write the entire memory 000-1 FF).
Up to four 24C04As can be connected to the bus.
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.
These inputs must be connected to either Vss or Vcc.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
Notes:
For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
24C04A page is 8 bytes long.
SCL Serial Clock
2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 24C04A has two blocks,
256 bytes each.
This input is used to synchronize the data transfer from
and to the device.
DS11140E-6
©1992 Microchip Technology Inc.
3-22
24C04A
NOTES:
©1992 Microchip Technology Inc.
DS11140E-7
3-23
24C04A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
J
PACKAGE:
P
SN
SM
I
TEMPERATURE
RANGE:
Blank
I
E
DEVICE:
24C04A
24C04AT
CERDIP
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
PLASTIC SOIC (0.207 mil Body)
O' C 10 +70' C
-40' C to +85' C
·40' C to +125' C
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM (in Tape and Reel)
©1992 Microchip Technology Inc.
DS11140E-8
3-24
~.
24C16
Microchip
16K (8 X 256 X 8) CMOS Serial Electrically Erasable PROM
DESCRIPTION
FEATURES
•
•
•
•
•
•
Single supply with programming operation down to
4.5 volts
Low power CMOS technology
2 mA active current typical
100 ~A standby current at 5.5 V
Organized as 8 blocks of 256 bytes (8 x 256 x 8)
Two wire serial interface bus
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 16 bytes
2 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection> 4,000 V
1,000,000 ERASEIWRITE cycles (typical)
Data retention> 40 years
8 pin DIP or 14 pin SOIC package
Available for extended temperature ranges
Commercial:
O·C to + 70·C
Industrial:
-40·C to +85·C
Automotive: -40·C to + 125·C
The Microchip Technology Inc. 24C16 is a 16K bit
Electrically Erasable PROM. The device is organized as
8 blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices.
The 24C16 also has a page-write capability for up to 16
bytes of data. The 24C16 is available in the standard 8pin DIP and a 14-pin surface mount SOIC package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
Vee
AOIWP
A1
TEST
A2
SCL
Vss
SOA
SO Package
NC
NC
AOIWP
Vee
A1
TEST
NC
NC
A2
SCL
Vss
SDA
NC
NC
3-25
© 1992 Microchip Technology Inc.
D811022B-1
24C16
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings·
All inputs and outputs W.r.t. Vss .......... -0.3 V to +6.2S V
Storage temperature ....................... -6S'C to + 1S0'C
Ambient temp. with power applied ..... -6S·C to +12S'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins .................................. ~ 4 kV
'Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may allect device reliability.
Name
Function
AO/WP
A1, A2
Vss
SDA
SCL
TEST
Vee
NC
Write Protect Input
Grounded for Normal Operation
Ground
Serial Address/Data I/O
Serial Clock
Grounded for Normal Operation
+S.O V Power Supply
No Connection
Vee = +S.O V ± 10%
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +8S'C
Automotive (E): Tamb = -40'C to +12S'C
DC CHARACTERISTICS
Parameter
AO/WP, SCL and SDA pins:
High level input voltage
Symbol
Min
VIH
.7 Vee
Max
Units
Conditions
V
Low level input voltage
Vil
.3 Vee
V
Low level output voltage
VOL
.40
V
IOl = 3.2 mA
Vee = 2.S V
Input leakage current
III
-10
10
lLA
VIN = .1 V to Vee
Output leakage current
Ilo
-10
10
lLA
VOUT =.1 V to Vee
Internal capacitance
(all inputs/outputs)
CINT
10
pF
Vee = S.O V (Note 1)
Tamb = 2S'C, FelK = 1 MHz
Operating current
leeo
3
mA
Vee=S.S V
SCL = 100 KHz
Standby current
Ices
100
lLA
Vee = S.S V
SDA = SCL = Vee
Note 1: This parameter is periodically sampled and not 100% tested.
BUS TIMING START/STOP
sel _ _--J
SDA-----r--..I
START
STOP
D8110228-2
© 1992 Microchip Technology Inc.
3-26
24C16
AC CHARACTERISTICS
Parameter
Symbol
Typ
Min
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
TR
1000
ns
SDA and SCl fall time
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
STOP condition hold time
THD:STO
4000
ns
STOP condition setup time
TSU:STO
4700
Output valid from clock
TAA
300
Bus free time
TBUF
4700
Input filter time constant
(SDA and SCl pins)
Write cycle time
Endurance
ns
3500
TI
2
TWR
---
100,000
ns
See Note 1
ns
Time the bus must be free
before a new transmission
can start
100
ns
10
ms
Byte or Page mode
See Note 2
E/W Cycles
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min.
300 ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
Note 2: When writing data to the 24C16, an automatic internal erase then write cycle is executed.
BUS TIMING DATA
tHIGH
tLOW
t HD:DAT I--~+-.-.!
D5110228-3
© 1992 Microchip Technology Inc.
3-27
24C16
FUNCTIONAL DESCRIPTION
Data Valid (D)
The 24C16 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24C 16 works as
slave. Both, master and slave can operate as transmitter or receiver but the master device determines which
mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur it will replace data in a first
in first out fashion.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Note: The 24C16 does not generate any acknowledge
bits if an internal programming cycle is in progress.
Bus not Busy CA)
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(8)
SCL ---+----1~
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS110228-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-28
24C16
BUS CHARACTERISTICS
WRITE OPERATION
Device Addressing and Operation
Byte Write
A control byte is the first byte received following the start
condition from the master device. The control byte
consists of a four bit control code, for the 24C16 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select bits
(B2, B1, BO). They are used by the master device to
select which of the eight 256 word blocks of memory are
to be accessed. These bits are in effect the three most
significant bits of the word address. It should be noted
that the protocol limits the size of the memory to eight
blocks of 256 words, therefore the protocol can support
only one 24C16 per system.
Following the start conditionl from the master, the device
code (4 bits), the block address (3 bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it
has generated an acknowledge bit during the ninth clock
cycle. Therefore the next byte transmitted by the master
is the word address and will be written into the address
pointer of the 24C16. After receiving another acknowledge signal from the 24C16 the master device will
transmit the data word to be written into the addressed
memory location. The 24C16 acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the 24C16 will
not generate acknowledge signals. (See Figure 3).
The last bit ofthe control byte defines the operation to be
performed. When set to one a read operation is selected, when set to zero a write operation is selected.
Following the start condition, the 24C16 monitors the
SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an
acknowledge .§ignal on the SDA line. Depending on the
state of the R/W bit, the 24C16 will select a read or write
operation.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C16 in the same way as in
a byte write. But instead of generating a stop condition
the master transmits up to sixteen data bytes to the
24C16 which are temporarily stored in the on-chip page
buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than
sixteen words prior to generating the stop condition, the
address counter will roll over and the previously received
data will be overwritten. As with the byte write operation,
once the stop condition is received an internal write cycle
will begin. (See Figure 4).
-
Operation
Control Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
FIGURE 2 - CONTROL BYTE
ALLOCATION
START
READ/WRITE
'-.....
/'
!
I
""
"
!
(
o
o
B2
B1
BO
'I
FIGURE 3 - BYTE WRITE
S
T
BUS ACTIVITY:
MASTER
A
R
WORD
ADDRESS
CONTROL
BYTE
S
T
op
DATA
T
SDA LINE
BUS ACTIVITY:
I : : : : : : : II :
A
C
K
©
I : :
: : :
I [ff
A
C
C
K
K
A
DS110228-5
1992 Microchip Technology Inc.
3-29
24C16
FIGURE 4 • PAGE WRITE
BUS ACTIVITY:
MASTER
S
T
A
CONTROL
R
BYTE
T __
_ __
WORD
ADDRESS(n)
SDA LINE
I:
BUS ACTIVITY:
1
:
:
:
:
DATAn
:
II:
1
:
DATAn+1
:==:J I : : : : : : : I D~ :: : : :I Fl
:
\\
A
A
A
C
C
C
K
K
K
S
T
0
p
DATAn+15
A
C
K
A
C
K
FIGURE 5 • CURRENT ADDRESS READ
S
T
BUS ACTIVITY:
MASTER
A
R
CONTROL
BYTE
S
T
o
DATAn
p
T
SDA LINE
BUS ACTIVITY:
ffiJUIDll : : : : : : : 1EI
A
C
K
FIGURE 6· RANDOM READ
S
T
BUS ACTIVITY:
MASTER
S
T
A
WORD
ADDRESS (n)
CONTROL
A
R _ _BYTE
T
_ _-
R
S
CONTROL
BYTE
T
o
P
T
SDA LINE
BUS ACTIVITY:
A
A
C
K
C
K
A
C
DATAn
K
FIGURE 7· SEQUENTIAL READ
BUS ACTIVITY:
MASTER
SDALINE
BUS ACTIVITY:
A
C
K
CONTROL
BYTE
A
C
K
~~ ~ n'-;:"-::AI:::;:=::~:: ~:1; 1:
DATAn
o
P
~I'-'---1
~: :~: I-"--C)~':Z 1 :
;1
: ::;:::r-r-:
::::r-r-o:
C
K
S
T
A
C
~
DATAn+ 1
DS11022B-6
'---'-;1;:::::
:;:
DATAn+2
: : : : : : 18
DATAn+ X
© 1992 Microchip Technology Inc.
3-30
24C16
WRITE PROTECTION
Noise Protection
The 24C16 can be used as a serial ROM when WP pin
is connected to Vee (+5V). Programming will be inhibited and the entire memory (2K bytes) will be writeprotected.
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device operation even on a noisy bus.
PIN DESCRIPTIONS
READ OPERATION
AO/WP Write Protect Inpyt
Read operations are initiated in the same way as write
operations with the exception that the RiW bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
This pin must be connected to either vss or Vee.
If tied to Vee, WRITE operations are inhibited. The
entire 2K bytes memory will be write-protected. Read
operations are possible.
Iflied to Vss, normal memory operation is enabled (read/
write the entire memory 000-7FF).
Current Address Read
The 24C16 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with Riii bit set to one, the 24C16 issues an acknowledge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24C16 discontinues transmission. (See Figure 5).
This feature allows the user to use the 24C 16 as a serial
ROM when WP is enabled (tied to Vee).
A1. A2 Chip Address Inputs
The A1 and A2 inputs are unused by the 24C16. They
must be connected to Vss to insure proper device operation.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
Random Read
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24C16 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the RiW bit set to a one. The 24C16 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24C16 discontinues
transmission. (See Figure 6).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
This pin must be connected to Vss.
Seqyential Read
Sequential reads are initiated in the same way as a
random read except that after the 24C16 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24C16 to transmit the next sequentially
addressed 8 bit word. (See Figure 7).
To provide sequential reads the 24C16 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
@
DS11022B-7
1992 Microchip Technology Inc.
3-31
24C16
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
24C~-/P
-
~ ,.0,-,."
I
TEMPERATURE
RANGE:
DEVICE:
P
SL
Blank
I
E
24C16
24C16T
0811022B-8
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
O· C to +70' C
-40' C to +85' C
-40' Cto +125' C
16K CMOS Serial EEPROM
16K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-32
24LC01
Microchip
lK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
• Single supply with operation down to 2.5 volts
Low power CMOS technology
- 2 mA active current typical
100 ~A standby current at 5.5 V
- 30 ~A standby current at 3.0 V
Organized as a single block of 128 bytes (128 x 8)
Two wire serial interface bus
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
2 ms typical write cycle time for page-write
Factory programming (QTP) available
ESD protection> 4,000 V
1,000,000 ERASE/WRITE cycles (typical)
Data retention> 40 years
8 pin DIP or SOIC package
Available for extended temperature ranges
Commercial:
O·C to + 70·C
Industrial:
-40·C to +85·C
Automotive: -40·C to + 125·C
The Microchip Technology Inc. 24LC01 is a 1K bit
Electrically Erasable PROM. The device is organized as
a single block of 128 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. Low
voltage design permits operation down to 2.5 volts with
a standby and active currents of only 30 ~A and 3 mA
respectively. The 24LC01 also has a page-write capability for up to 8 bytes of data. Up to eight 24LC01 s may
be connected to the two wire bus. The 24LC01 is
available in the standard 8-pin DIP and an 8-pin surface
mount SOIC package.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package
AO
Vee
A1
TEST
A2
SCL
Vss
SDA
SO Package
AO
Vee
A1
TEST
A2
SCL
Vss
SDA
24LC01
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs w.r.t. Vss ......... -0.3 V to +6.25 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins .................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
AO, A1, A2, SCl and SDA pins:
High level input voltage
Function
AO, A1, A2
Vss
SDA
Sel
Test
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Function. Grounded for
normal operation
+2.5 V to 5.5 V Power Supply
Vcc
Vee = +2.5 V
Commercial
Industrial
Automotive
DC CHARACTERISTICS
Parameter
Name
Symbol
Min
VIH
.7 Vee
to +5.5 V
(C): Tamb= O'C to +70'C
(I) : Tamb = -40'C to +85'C
(E): Tamb = -40'C to + 125'C (Note 2)
Max
Units
Conditions
V
low level input voltage
VIL
.3 Vee
V
low level output voltage
VOL
.40
V
IOL = 3.2 mA
Vee = 2.5 V
Input leakage current
III
-10
10
IlA
VIN = .1 V to Vee
Output leakage current
ILO
-10
10
IlA
VOUT =.1 V to Vee
Internal capacitance
(all inputs/outputs)
CINT
10
pF
Vee = 5.0 V (Note 1)
Tamb = 25'C, FeLK = 1 MHz
Operating current
leeo
3
mA
Vee= 5.5 V
SCl = 100 KHz
Standby current
Ices
100
IlA
30
IlA
Vee= 5.5 V
SDA = SCl = Vee
Vee= 3.0 V
SDA = SCl = Vee
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85'C, endurance is rated at 10,000 ERASE/WRITE cycles.
BUS TIMING START/STOP
SCL
SDA
-----+'\1
START
STOP
DS11155D-2
© 1992 Microchip Technology Inc.
3-34
24LC01
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
SDA and SCl fall time
TR
1000
ns
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
STOP condition hold time
THD:STO
4000
ns
STOP condition setup time
TSU:STO
4700
Output valid from clock
TAA
300
Bus free time
TSUF
4700
Input filter time constant
(SDA and SCl pins)
ns
3500
TI
Write cycle time
TWR
Endurance
---
2
100,000
ns
See Note 1
ns
Time the bus must be free
before a new transmission
can start
100
ns
10
ms
Byte or Page mode
See Note 2
EfW Cycles
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min.
300 ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
Note 2: When writing data to the 24lCOl , an automatic internal erase then write cycle is executed.
BUS TIMING DATA
-------- , ,- -tSU:STO-SOA
IN
"------
hi
---~
SOA
OUT
OS111550-3
© 1992 Microchip Technology Inc.
3-35
24LC01
FUNCTIONAL DESCRIPTION
Data Valid CD)
The 24LC01 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC01 works
as slave. Both, master and slave can operate as
transmitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur it will replace data in a first
in first out fashion.
Up to eight 24LC01 s can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 24LC01 (refer to section
Slave Address).
Acknowledge
BUS CHARACTERISTICS
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Note: The 24LC01 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Bus not Busy CA)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to LOW transition ofthe SDA line while the clock
(SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Stop Data Transfer CC)
A LOW to HIGH transition of the SDA line while the clock
(SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(8)
--+--+--..
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
D511155D-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-36
24LC01
WRITE OPERATION
BUS CHARACTERISTICS
Slave Address
Byte Write
The chip address inputs AO, A 1 and A2 of each 24LC01
must be externally connected to either Vee or ground
(Vss), assigning to each 24LC01 a unique 3-bit address.
Up to eight 24LC01 s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24LC01.
Following the start signal from the master, the device
code (4 bits), the chip address (3 bits), and the R/Wbit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it
has generated an acknowledge bit during the ninth clock
cycle. Therefore the next byte transmitted by the master
is the word address and will be written into the address
pointer of the 24LC01. After receiving another acknowledge signal from the 24LC01 the master device will
transmit the data word to be written into the addressed
memory location. The 24LC01 acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the 24LC01 will
not generate acknowledge signals. (See Figure 3).
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC01, followed by the chip address bits AO, A 1 and A2.
The eighth bit of slave address determines if the master
device wants to read orwrite to the 24LC01. (See Figure
2.)
Page Write
The 24LC01 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.
The write control byte, word address and the first data
by1e are transmitted to the 24LC01 in the same way as
in a byte write. But instead of generating a stop condition
the master transmits up to eight data bytes to the
24LC01 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words priorto generating the stop condition, the address
counter will roll over and the previously received data will
be overwritten. As with the byte write operation, once
the stop condition is received an internal write cycle will
begin. (See Figure 4).
-
Operation
Control Code
Chip Select
R/W
Read
1010
Chip Address
1
Write
1010
Chip Address
0
FIGURE 2 - CONTROL BYTE
ALLOCATION
READ/WRITE
START
/'
S:LAV~ AD~RES:S
1
/
I
'-.....
:
\,
\,
\
/
/
1
IR/wl A
0
0
A1
A2
\,
AO
~I
r
FIGURE 3 - BYTE WRITE
S
T
BUS ACTIVITY:
MASTER
A
S
WORD
ADDRESS
CONTROL
R _ _BYTE
T
_ __
o
P
SDA LINE
BUS ACTIVITY:
T
DATA
: : : : : I [ff
A
A
C
K
C
K
A
C
K
DS11155D-5
© 1992 Microchip Technology Inc.
3-37
24lC01
FIGURE 4 . PAGE WRITE
BUS ACTIVITY:
MASTER
SDA LINE
S
T
CONTROL
A
BYTE
R __
T
_ __
WORD
ADDRESS (nj
DATAn
un
§lJl
BUS ACTIVITY:
DATAn+1
S
T
0
p
DATAn+7
::::: II:::: I:: I Dr::::: I El
\ \
A
A
C
A
C
C
K
K
K
A
A
C
K
C
K
FIGURE 5· CURRENT ADDRESS READ
S
T
BUS ACTIVITY:
MASTER
A
R
CONTROL
BYTE
S
T
o
DATAn
T
SDA LINE
BUS ACTIVITY:
P
ffiJUIJJlI : : : : : : : I EI
A
C
K
FIGURE 6· RANDOM READ
S
T
BUS ACTIVITY:
MASTER
A
R
S
T
A
R
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
CONTROL
BYTE
o
P
T
T
SDALINE
BUS ACTIVITY:
A
A
C
K
C
K
A
C
K
DATAn
FIGURE 7· SEQUENTIAL READ
S
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
A
C
CONTROL
BYTE
__ ~n I
A
C
K
:
: : :
DATAn
A
A
T
C
C
0
K
K
P
: : II~:
: :"'::r-rl:I r-r-I:
:r-r-:
r-r
: -I
DATAn+ 1
I ~~\I :~::~::~::I 8
r-r:
1:
DATA n +2
DATAn+ X
K
DSl1155D-6
© 1992 Microchip Technology Inc.
3-38
24LC01
READ OPERATION
PIN DESCRIPTIONS
Read operations are initiated in the same way as write
operations with the exception that the RIW bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
AD, A 1 and A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24LCOls can be connected to the bus.
These inputs must be connected to either Vss or Vee.
Current Address Read
The 24LC01 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from aqQress n + 1. Upon receipt of the slave address
with RIW bit set to one, the 24LC01 issues an acknowledge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24LC01 discontinues transmission. (See Figure 5).
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP conditions.
SCL Serial Clock
Random Read
This input is used to synchronize the data transfer from
and to the device.
Random read operations allow the masterto access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24LC01 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pOinter is
set. Then.!be master issues the control byte again but
with the RIW bit setto a one. The 24LCOl will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24LCOl discontinues
transmission. (See Figure 6).
This pin must be connected to Vss for normal operation.
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LCOl transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LCOl to transmit the next sequentially
addressed 8 bit word. (See Figure 7).
To provide sequential reads the 24LC01 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
Noise Protection
The 24LCOl employs a Vee threshold detector circuit
which disables the internal erase/write logic if the Vee is
below 1.5 volts at nominal conditions.
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device operation even on a noisy bus.
D811155D-7
© 1992 Microchip Technology Inc.
3-39
24LC01
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
PACKAGE:
I
I
'--_ _ _ _ _ _-11
TEMPERATURE
RANGE:
P
SN
SM
Blank
I
E
DEVICE:
24LCOI
24LCOtT
D811155D-8
PLASTIC DIP
PLASTIC SOIC (150 mil Body)
PLASTIC SOIC (207 mil Body)
0' Cto +70' C
-40' C to +85' C
-40' C to +125' C
1K CMOS Serial EEPROM
lK CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-40
~.
24LC02
Microchip
2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Single supply with operation down to 2.5 volts
Low power CMOS technology
- 2 mA active current typical
100 J.lA standby current at 5.5 V
- 30 J.lA standby current at 3.0 V
Organized as a single block of 256 bytes (256 x 8)
Two wire serial interface bus
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
2 ms typical write cycle time for page-write
Factory programming (QTP) available
ESD protection> 4,000 V
1,000,000 ERASE/WRITE cycles (typical)
Data retention> 40 years
8 pin DIP or SOIC package
Available for extended temperature ranges
Commercial:
O'C to + 70'C
Industrial:
-40'C to +85'C
Automotive: -40'C to + 125'C
The Microchip Technology Inc. 24LC02 is a 2K bit
Electrically Erasable PROM. The device is organized as
a single block of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. Low
voltage design permits operation down to 2.5 volts with
a standby and active currents of only 30 J.lA and 3 mA
respectively. The 24LC02 also has a page-write capability for up to 8 bytes of data. Up to eight 24LC02s may
be connected to the two wire bus. The 24LC02 is
available in the standard 8-pin DIP and an 8-pin surface
mount SOIC package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AO
Vee
A1
WP
A2
SCl
Vss
SOA
SDA WP SCl
SO Package
AD
Vee
A1
WP
A2
SCl
Vss
SDA
vee 0-vss 0---
© 1992 Microchip Technology Inc.
3-41
D511153D-1
24LC02
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs W.r.t. Vss .......... -0.3 V to +6.25 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to + 125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins .................................... .4 kV
"Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
Name
Function
AO, A1, A2
Vss
SDA
SCL
WP
Vee
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5 V to 5.5 V Power Supply
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vcc = +2.5 V to +5.5 V
Commercial (C): Tamb = O'C to +70'C
Industrial
(I): Tamb = -40'C to +85'C
Automotive (E): Tamb = -40'C to + 125'C (Note 2)
DC CHARACTERISTICS
Parameter
AO, A1, A2, WP, SCL and SDA pins:
High level input voltage
Symbol
Min
VIH
.7Vcc
Max
Units
Conditions
V
Low level input voltage
VIL
.3 Vce
V
Low level output voltage
VOL
.40
V
10L = 3.2 mA
Vee = 2.5 V
Input leakage current
III
-10
10
IlA
VIN = .1 V to Vee
Output leakage current
ILO
-10
10
IlA
VOUT = .1 V to Vec
Vee = 5.0 V (Note 1)
Tamb = 25'C, FCLK = 1 MHz
Internal capacitance
(all inputs/outputs)
CINT
10
pF
Operating current
leeo
3
mA
Vee = 5.5 V
SCL = 100 KHz
Standby current
lecs
30
IlA
100
IlA
Vee=3.0 V
SDA = SCL = Vee
Vee= 5.5 V
SDA = SCL = Vee
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85'C, endurance is rated at 10,000 ERASE/WRITE cycles.
BUS TIMING START/STOP
SCL
SDA
-----+-..1
START
STOP
DS11153D-2
© 1992 Microchip Technology
3-42
Inc.
24LC02
AC CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCL rise time
TR
1000
ns
SDA and SCL fall time
TF
300
ns
Remarks
START condition hold time
THO:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THO:OAT
0
ns
Data input setup time
TSU:OAT
250
ns
STOP condition hold time
THO:STO
4000
ns
STOP condition setup time
TSU:STO
4700
ns
Output valid from clock
TAA
300
Bus free time
TSUF
4700
Input filter time constant
(SDA and SCL pins)
3500
TI
Write cycle time
TWR
Endurance
---
2
100,000
ns
See Note 1
ns
Time the bus must be free
before a new transmission
can start
100
ns
10
ms
Byte or Page mode
See Note 2
E/W Cycles
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min.
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: When writing data to the 24LC02, an automatic internal erase then write cycle is executed.
BUS TIMING DATA
I
--~
SU:STASOA
IN
SOA
V-------,
tHO:DAT
t HO:STA
"
tAA--
OUT
tLow
V
..--~
---
tHIGH
tLOW
"S
'/
SCL
..--
/
"\'/
"I
t AA
*
~XXXXXX
© 1992 Microchip Technology Inc.
3-43
- --
--
tSUF
OS111530-3
24LC02
FUNCTIONAL DESCRIPTION
Data Valid (D)
The 24lC02 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24lC02 works
as slave. Both, master and slave can operate as
transmitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data by1es transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur it will replace data in a first
in first out fashion.
Up to eight 24lC02s can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 24lC02 (refer to section
Slave Address).
Acknowledge
BUS CHARACTERISTICS
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Note: The 24lC02 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last by1e that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Bus not Busy (A)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 1· DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(8)
SCl --+--t~
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA AllOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS11153D-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-44
24LC02
BUS CHARACTERISTICS
WRITE OPERATION
Slave Address
Byte Write
The chip address inputs AO, A 1 and A2 of each 24LC02
must be externally connected to either Vee or ground
(Vss), assigning to each 24LC02 a unique 3-bit address.
Up to eight 24LC02s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24LC02.
Following the start signal from the master, the device
code (4 bits), the chip address (3 bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it
has generated an acknowledge bit during the ninth clock
cycle. Therefore the next byte transmitted by the master
is the word address and will be written into the address
pointer of the 24LC02. After receiving another acknowledge signal from the 24LC02 the master device will
transmit the data word to be written into the addressed
memory location. The 24LC02 acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the 24LC02 will
not generate acknowledge signals. (See Figure 3).
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC02, followed by the chip address bits AO, A1 and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC02. (See Figure
2.)
Page Write
The 24LC02 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.
Operation
Control Code
Chip Select
R/W
Read
1010
Chip Address
1
Write
1010
Chip Address
0
The write control byte, word address and the first data
byte are transmitted to the 24LC02 in the same way as
in a byte write. But instead of generating astop condition
the master transmits up to eight data bytes to the
24LC02 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the stop condition, the address
counter will roll over and the previously received data will
be overwritten. As with the by1e write operation, once
the stop condition is received an internal write cycle will
begin. (See Figure 4).
FIGURE 2 - CONTROL BYTE
ALLOCATION
START
/'
S:LAV~ AD~RES:S
1
I
I
READ/WRITE
I
'"
:
'\
'\
'\
I
I'
lR/wl A
D
D
A2
Ai
AD
~I
FIGURE 3 - BYTE WRITE
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
WORD
ADDRESS
CONTROL
BYTE
T
o
DATA
P
SDA LINE
BUS ACTIVITY:
A
C
A
C
K
K
A
C
K
DS11153D-5
© 1992 Microchip Technology Inc.
3-45
24LC02
FIGURE 4· PAGE WRITE
BUS ACTIVITY:
MASTER
S
T
A
CONTROL
R
BYTE
T __
__
S
WORD
ADDRESS (n)
DATAn
T
DATAn+1
DATAn+7
0
p
SDA LINE
BUS ACTIVITY:
A
C
A
C
A
C
K
K
K
FIGURE 5 • CURRENT ADDRESS READ
S
T
BUS ACTIVITY:
MASTER
A
R
CONTROL
BYTE
S
T
o
DATAn
T
SDA LINE
P
LrulJIDlI:::::::IEI
BUS ACTIVITY:
A
C
K
FIGURE 6· RANDOM READ
S
T
BUS ACTIVITY:
MASTER
A
R
S
T
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
CONTROL
A
BYTE
R __
T
_ __
T
o
p
SDALINE
BUS ACTIVITY:
A
A
C
K
A
C
DATAn
C
K
K
FIGURE 7· SEQUENTIAL READ
S
BUS ACTIVITY:
MASTER
SDA LINE
A
A
A
T
C
c e O
K K K
P
CONTROL
BYTE
:~ ~ nI :
I
:
:
:
A
BUS ACTIVITY:
C
DATAn
:
:
I r-r-I: r-r-l::--,--,::-,-,:1r-r-I:
DATA n + 1
u
1 11 : : : : : : : 1El
:r-r--::r-r-1:
r - r -: 1 1
\ \
DATAn+2
----DATA n + X
K
DSll153D-6
© 1992
3-46
Microchip Technology Inc.
24LC02
READ OPERATION
PIN DESCRIPTIONS
Read operations are initiated in the same ~ay as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
AO. A1 and A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24LC02s can be connected to the bus.
These inputs must be connected to either Vss or Vee.
Current Address Read
The 24LC02 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from ac!Qress n + 1. Upon receipt of the slave address
with RIW bit set to one, the 24LC02 issues an acknowledge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24LC02 discontinues transmission. (See Figure 5).
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP conditions.
SCL Serial Clock
Random Read
This input is used to synchronize the data transfer from
and to the device.
.
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24LC02 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then !De master issues the control byte again but
with the RIW bit setto a one. The 24LC02 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24LC02 discontinues
transmission. (See Figure 6).
WP Write Protect Input
This pin can be connected to either Vss or Vee. If tied to
Vee, WRITE operations are inhibited. The entire 256
bytes memory will be write-protected. Read operations
are possible.
If tied to Vss, normal memory operation is enabled.
(Read/write the entire memory OOO-OFF).
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC02 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC02 to transmit the next sequentially
addressed 8 bit word. (See Figure 7).
To provide sequential reads the 24LC02 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
Noise Protection
The 24LC02 employs a Vce threshold detector circuit
which disables the internal erase/write logic if the Vee is
below 1.5 volts at nominal conditions.
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device operation even on a noisy bus.
DS11153D-7
© 1992 Microchip Technology Inc.
3-47
24LC02
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
PACKAGE:
I
' - - - - - - - 11 TEMPERATURE
-lt
L--_ _ _ _ _ _
RANGE:
DEVICE:
P
SN
SM
Blank
I
E
24LC02
24LC02T
DS11153D-8
PLASTIC DIP
PLASTIC SOIC (150 mil Body)
PLASTIC SOIC (207 mil Body)
O' C to +70' C
·40' C to +85' C
·40' C to +125' C
2K CMOS Serial EEPROM
2K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-48
~.
24LC04
Microchip
4K (512
X
8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Single supply with operation down to 2.5 volts
Low power CMOS technology
2 mA active current typical
100 ~A standby current at 5.5 V
- 30 ~A standby current at 3.0 V
Organized as 2 blocks of 256 bytes (2 x 256 x 8)
Two wire serial interface bus
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 16 bytes
2 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection> 4,000 V
1,000,000 ERASE/WRITE cycles (typical)
Data retention> 40 years
8 pin DIP or 14 pin SOIC package
Available for extended temperature ranges
Commercial:
O'C to + 70'C
Industrial:
-40'C to +85'C
Automotive: -40'C to + 125'C
The Microchip Technology Inc. 24LC04 is a 4K bit
Electronically Erasable PROM. The device is organized
as 2 blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices.
Low voltage design permits operation down to 2.5 volts
with a standby and active currents of only 30 ~A and 3
mA respectively. The 24LC04 also has a page-write
capability for up to 16 bytes of data. The 24LC04 is
available in the standard 8-pin DIP and a 14-pin surface
mount SOIC package.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package
AD
Vee
A1
WP
A2
SCL
Vss
SOA
AD
A1
A2
III
1
I/O
CONTROL
LOGIC I
MEMOR:
CONTROL
LOGIC
j1
~~~
NC
NC
SOA WP SCL
HV GENERATOR
~
i
r-
IXOEC I-
EEPROM ARRAY
(2 x 256 x 8)
PAGE LATCHES
'----
1
1
YOEC
AD
Vee
A1
WP
NC
NC
A2
SCL
Vss
SOA
NC
NC
vee
vss
0-""
0-....
-*-
SENSE AMP
R/WCONTROL
24LC04
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs w.r.t. Vss .......... -0.3 V to +6.25 V
Storage temperature ....................... -65'C to + 150'C
Ambient temp. with power applied ..... -65'C to +125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins ..................................... 4 kV
"Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
Name
Function
AO
A1, A2
Vss
SDA
SCL
WP
Vee
NC
Not Used. Must be tied to Vss.
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5 V to 5.5 V Power Supply
No Connection
may affect device reliability.
Vee = +2.5 V to +5.5 V
Commercial (C): Tamb = O'C to +70'C
(I): Tamb = -40'C to +85'C
Industrial
Automotive (E): Tamb = -40'C to + 125'C (Note 2)
DC CHARACTERISTICS
Parameter
A 1, A2, WP, SCL and SDA pins:
High level input voltage
Symbol
Min
VIH
.7 Vee
Max
Units
Conditions
V
Low level input voltage
VIL
.3 Vee
V
Low level output voltage
VOL
.40
V
IOL = 3.2 mA
Vee = 2.5 V
Input leakage current
III
-10
10
/lA
VIN = .1 V to Vee
Output leakage current
ILo
-10
10
/lA
VOUT = .1 V to Vee
Internal capacitance
(all inputs/outputs)
CINT
10
pF
Vee = 5.0 V (Note 1)
Tamb = 25'C, FeLK = 1 MHz
Operating current
leeo
3
mA
Vee= 5.5 V
SCL = 100 KHz
Standby current
Ices
30
/lA
100
/lA
Vee=3.0 V
SDA = SCL = Vee
Vee= 5.5 V
SDA = SCL = Vee
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85'C, endurance is rated at 10,000 ERASE/WRITE cycles.
BUS TIMING START/STOP
seL - - - - /
SDA-----i->.I
STOP
START
08200520-2
© 1992 Microchip Technology Inc.
3-50
24LC04
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCL rise time
SDA and SCL fall time
TR
1000
TF
300
Remarks
ns
ns
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
STOP condition hold time
THD:STO
4000
ns
STOP condition setup time
TSU:STO
4700
ns
Output valid from clock
TM
300
Bus free time
TBUF
4700
Input filter time constant
(SDA and SCL pins)
3500
TI
Write cycle time
TWR
Endurance
---
2
100,000
ns
See Note 1
ns
Time the bus must be free
before a new transmission
can start
100
ns
10
ms
Byte or Page mode
See Note 2
E/W Cycles
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min.
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: When writing data to the 24LC04, an automatic internal erase then write cycle is executed.
BUS TIMING DATA
tHIGH
tLow
t HD:DAT ~--t-~
D520052D-3
© 1992 Microchip Technology Inc.
3-51
24LC04
FUNCTIONAL DESCRIPTION
Data Valid (D)
The 24lC04 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24lC04 works
as slave. Both, master and slave can operate as
transmitter or receiver butthe master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur it will replace data in a first
in first out fashion.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24lC04 does not generate any acknowledge
bits if an internal programming cycle is in progress.
Bus not Busy (Al
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 1" DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(8)
--+---..<.......
(D)
(D)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS20052D-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-52
24LC04
BUS CHARACTERISTICS
WRITE OPERATION
Slave Address
Byte Write
The chip address inputs A 1 and A2 of each 24LC04 must
be externally connected to either Vcc or ground (Vss),
assigning to each 24LC04 a unique 2-bit address, Up to
tour 24LC04s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits A 1 and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 24LC04.
Following the start condition from the master, the device
code (4 bits),!be chip address (2 bits), the block select
bit, and the R/W bit which is a logic low is placed onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word address
will follow after it has generated an acknowledge bit
during the ninth clock cycle. Therefore the next byte
transmitted by the master is the word address and will be
written into the address pointer of the 24LC04. After
receiving another acknowledge signal from the 24LC04
the master device will transmit the data word to be
written into the addressed memory location. The 24LC04
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and
during this time the 24LC04 will not generate acknowledge signals. (See Figure 3).
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC04, followed by the chip address bits (A1, A2) and the block select bit (AO).
The eighth bit of slave address determines if the master
device wants to read orwrite to the 24LC04. (See Figure
2).
The 24LC04 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a
programming mode.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC04 in the same way as
in a byte write. But instead of generating astop condition
the master transmits up to sixteen data bytes to the
24LC04 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than
sixteen words prior to generating the stop condition, the
address counter will roll over and the previously received
data will be overwritten. As with the byte write operation,
once the stop condition is received an internal write cycle
will begin. (See Figure 4).
-
Operation
Control Code
Chip/Block Select
RIW
Read
1010
A2 A1 AO
1
Write
1010
A2 A1 AO
0
FIGURE 2 - CONTROL BYTE
ALLOCATION
START
READ/WRITE
JI'
"
AO is the block select bit to select the upper or
lower 256-byte block.
A 1, A2 are chip address bits.
FIGURE 3 - BYTE WRITE
BUS ACTIVITY:
MASTER
S
T
CONTROL
A
R _ _BYTE
T
_ __
WORD
ADDRESS
S
T
o
DATA
P
SDA LINE
BUS ACTIVITY:
A
A
A
C
K
C
K
C
K
DS20052D-5
© 1992 Microchip Technology Inc.
3-53
24LC04
FIGURE 4 • PAGE WRITE
S
BUS ACTIVITY:
MASTER
1
CONTROL
T __
__
R
BYTE
S
WORD
ADDRESS(n)
I:
SDA LINE
BUS ACTIVITY:
I : : : : :
DATAn
II :
A
I : : : : :
T
0
p
DATAn+1S
I I : : : : : : : II)( : : : : : I El
A
C
A
C
K
A
C
K
C
K
DATAn+1
"
A
C
K
K
FIGURE 5 • CURRENT ADDRESS READ
S
T
BUS ACTIVITY:
MASTER
S
T
CONTROL
A
BYTE
T
R __
_ __
op
DATAn
rulDJJll:::::::IEI
SDA LINE
BUS ACTIVITY:
A
C
K
FIGURE 6 • RANDOM READ
S
T
BUS ACTIVITY:
MASTER
S
T
CONTROL
A
T
_ __
BYTE
R __
WORD
ADDRESS (n)
CONTROL
A
T
BYTE
_ __
R __
S
T
o
P
SDA LINE
BUS ACTIVITY:
A
A
C
C
K
A
DATAn
C
K
K
FIGURE 7 • SEQUENTIAL READ
S
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
A
C
K
CONTROL
BYTE
:~ ~
n1:
A
C
K
I
:
:
:
DATAn
:
:
A
C
K
1r-r-I:
A
C
K
T
~
11: : : : : : : I Cjz1: : : : : : : 1EJ
:--r-->::---r--o:
r-r-: ->I
\ \
DATAn+ 1
DS20052D-6
DATAn+2
----DATAn+X
© 1992 Microchip Technology Inc.
3-54
24LC04
WRITE PROTECTION
Noise Protection
The 24LC04 can be used as a serial ROM when WP pin
is connected to Vee (+5V). Programming will be inhibited and the entire memory (512 bytes) will be writeprotected.
The 24LC04 employs a Vee threshold detector circuit
which disables the internal erase/write logic if the Vee is
below 1.5 volts at nominal conditions.
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device operation even on a noisy bus.
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the Riw bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
PIN DESCRIPTIONS
WP Write Protect Input
This pin must be connected to either Vss or Vee.
If tied to Vee, WRITE operations are inhibited. The
entire 512 bytes memory will be write-protected. Read
operations are possible.
Current Address Read
The 24LC04 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation wou Id access data
from address n + 1. Upon receipt of the slave address
with Riw bit set to one, the 24LC04 issues an acknowledge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24LC04 discontinues transmission. (See Figure 5).
Iflied to Vss, normal memory operation is enabled (read/
write the entire memory 000-1 FF).
This feature allows the userto use the 24LC04 as a serial
ROM when WP is enabled (tied to Vee).
AO (Test Pin)
Unused by the 24LC04 during operation. Must be tied
to Vss for normal operation.
A1, A2 Chip Address Inputs
Random Read
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true. Up to four 24LC04s can
be connected to the bus. These inputs must be connected to either Vss or Vee.
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24LC04 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the Riw bit set to a one. The 24LC04 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24LC04 discontinues
transmission. (See Figure 6).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP conditions.
SeguentialRead
SCL Serial Clock
Sequential reads are initiated in the same way as a
random read except that after the 24LC04 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC04 to transmit the next sequentially
addressed 8 bit word. (See Figure 7).
This input is used to synchronize the data transfer from
and to the device.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
To provide sequential reads the 24LC04 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
DS20052D-7
© 1992 Microchip Technology Inc.
3-55
24LC04
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
P
SL
I
TEMPERATURE
RANGE:
I
DEVICE:
Blank
I
E
24LC04
24LC04T
D820052D-8
PLASTIC DIP
PLASTIC SOIC (14-pin 150 mil Body)
O' C to +70' C
·40' C to +85' C
·40' C to +125' C
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-56
24LC16
Microchip
16K (8 X 256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
• Single supply with operation down to 2.5 volts
• Low power CMOS technology
2 rnA active current typical
100!lA standby current at 5.5 V
30!lA standby current at 2.5 V
• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• Two wire serial interface bus
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection> 4,000 V
• 1,000,000 ERASEIWRITE cycles (typical)
• Data retention > 40 years
• 8 pin DIP or 14 pin SOIC package
• Available for extended temperature ranges
O·C to + 70·C
Commercial:
Industrial:
-40·C to +85·C
Automotive: -40·C to +125·C
The Microchip Technology Inc. 24LC16 is a 16K bit
Electronically Erasable PROM. The device is organized
as 8 blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices.
Low voltage design permits operation down to 2.5 volts
with a standby and active currents of only 30 !lA and 3
rnA respectively. The 24LC16 also has a page-write
capability for up to 16 bytes of data. The 24LC16 is
available in the standard 8-pin DIP and a 14-pin surface
mount SOIC package.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package
AOIWP
Vee
A1
TEST
A2
SCl
Vss
SDA
NC
NC
AOIWP
Vee
A1
Vee
TEST
NC
NC
A2
SCl
Vss
SDA
NC
NC
VSS
3-57
0-0--
© 1992 Microchip Technology Inc.
DS20051C-1
24LC16
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum RatingS·
All inputs and outputs w.r.t. Vss .......... -0.3 V to +6.25 V
Storage temperature ....................... -65·C to + 150·C
Ambient temp. with power applied ..... -65·C to + 125·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins .................................. ~ 4 kV
·Notice: Stresses above those listed under ·Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Name
Function
AO/wP
Al, A2
Vss
SDA
SCL
TEST
Vcc
NC
Write Protect Input
Grounded for Normal Operation
Ground
Serial Address/Data 1/0
Serial Clock
Grounded for Normal Operation
+2.5 V to 5.5 V Power Supply
No Connection
Vcc = +2.5 V to +5.5 V
Commercial (C): Tamb = O·Cto +70·C
(I): Tamb = -40·C to +85·C
Industrial
Automotive (E): Tamb = -40·C to + 125·C
DC CHARACTERISTICS
Parameter
AO/wP, SCL and SDA pins:
High level input voltage
Symbol
Min
VIH
.7Vcc
Max
Units
Conditions
V
Low level input voltage
Vil
.3 Vcc
V
Low level output voltage
VOL
.40
V
IOl = 3.2 mA
Vcc=2.5V
Input leakage current
III
-10
10
j.1A
VIN=.l V to 5.5 V
Output leakage current
IlO
-10
10
IlA
VOUT = .1 V to 5.5 V
Internal capacitance
(ali inputS/outputs)
CINT
10
pF
Vcc = 5.0 V (Note 1)
Tamb = 25·C, FClK = 1 MHz
Operating current
Icco
3
mA
Vcc=5.5 V
SCL = 100 KHz
Standby current
Iccs
30
IlA
100
IlA
Vcc=2.5 V
SDA = SCL = Vcc
Vcc=5.5 V
SDA = SCL = Vcc
Note 1: This parameter is periodically sampled and not 100% tested.
BUS TIMING START/STOP
SCl _ _- J
SDA-----.;-,.I
START
STOP
DS20051C-2
© 1992 Microchip Technology Inc.
3-58
24LC16
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCL rise time
TR
1000
ns
SDA and SCL fall time
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
STOP condition hold time
THD:STO
4000
ns
STOP condition setup time
TSU:STO
4700
ns
Output valid from clock
TAA
300
Bus free time
TSUF
4700
Input filter time constant
(SDA and SCL pins)
3500
TI
.Write cycle time
TWR
Endurance
---
2
100,000
ns
See Note 1
ns
Time the bus must be free
before a new transmission
can start
100
ns
10
ms
Byte or Page mode
EIW Cycles
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min.
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: When writing data to the 24LC16, an automatic internal erase then write cycle is executed.
BUS TIMING DATA
,
SCL
,- --
tSU:STO-SOA
IN
SOA
OUT
OS20051C-3
© 1992 Microchip Technology Inc.
3-59
24LC16
FUNCTIONAL DESCRIPTION
Data Valid (D)
The 24lC16 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 24lC16 works
as slave. Both, master and slave can operate as
transmitter or receiver butthe master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a STARTcondition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur itwill replace data in a first
in first out fashion.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Note: The 24lC16 does not generate any acknowledge
bits if an internal programming cycle is in progress.
Bus not Busy (A)
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A H IG H to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 1· DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(8)
SCL --1----1-
(D)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS20051C-4
STOP
CONDITION
© 1992 Microchip Technology Inc.
3-60
24LC16
BUS CHARACTERISTICS
WRITE OPERATION
Device Addressing and Operation
Byte Write
A control byte is the first byte received following the start
condition from the master device. The control byte
consists of a four bit control code, for the 24LC16 this is
set as 1010 binary for read and write operations. The
nextthree bits of the control byte are the block select bits
(B2, B1, BO). They are used by the master device to
select which of the eight 256 word blocks of memory are
to be accessed. These bits are in effect the three most
significant bits of the word address. It should be noted
that the protocol limits the size of the memory to eight
blocks of 256 words, therefore the protocol can support
only one 24LC16 per system.
Following the start conditionl from the master, the device
code (4 bits), the block address (3 bits), and the Riw bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it
has generated an acknowledge bit during the ninth clock
cycle. Therefore the next byte transmitted by the master
is the word address and will be written into the address
pointer of the 24LC16. After receiving another acknowledge Signal from the 24LC16 the master device
will transmit the data word to be written into the addressed memory location. The 24LC16 acknowledges
again and the master generates a stop condition. This
initiates the internal write cycle, and during this time the
24LC16 will not generate acknowledge signals. (See
Figure 3).
The last bit ofthe control byte defines the operation to be
performed. When set to one a read operation is selected, when set to zero a write operation is selected.
Following the start condition, the 24LC16 monitors the
SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an
acknowledge ~gnal on the SDA line. Depending on the
state ofthe R/W bit, the 24LC 16 will select a read or write
operation.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC16 in the same way as
in a byte write. But instead of generating a stop condition
the master transmits up to sixteen data bytes to the
24LC16 which are temporarily stored in the on-Chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than
sixteen words prior to generating the stop condition, the
address counter will roll over and the previously received
data will be overwritten. As with the byte write operation,
once the stop condition is received an internal write cycle
will begin. (See Figure 4).
R/W
Operation
Control Code
Block Select
Read
1010
Block Address
1
Write
1010
Block Address
a
FIGURE 2 • CONTROL BYTE
ALLOCATION
START
READ/WRITE
/'
/
I
"
I
/
/
[
0
o
B2
B1
FIGURE 3· BYTE WRITE
S
T
BUS ACTIVITY:
MASTER
A
R
WORD
ADDRESS
CONTROL
BYTE
S
T
o
DATA
T
P
SDA LINE
BUS ACTIVITY:
A
C
K
A
A
C
K
C
K
DS20051C-5
© 1992 Microchip Technology Inc.
3-61
24LC16
FIGURE 4· PAGE WRITE
S
T
BUS ACTIVITY:
MASTER
A
CONTROL
R
T __
BYTE
__
SDA LINE
[illl
WORD
ADDRESS(n)
Dll I :
BUS ACTIVITY:
I : : : : :
A
C
K
DATAn
DATAn+1
S
T
0
p
DATAn+15
II : : : : : : : I I : : : : : : : I [)~ : : : : : I El
\\
A
C
K
A
C
K
A
C
A
C
K
K
FIGURE 5 • CURRENT ADDRESS READ
S
T
CONTROL
_ _BYTE
_ __
S
T
BUS ACTIVITY:
MASTER
A
R
T
SDA LINE
ffiJillDll : ; : : : : : 1EI
BUS ACTIVITY:
o
DATAn
P
A
C
K
FIGURE 6· RANDOM READ
S
BUS ACTIVITY:
MASTER
T
A
R
T
S
T
A
WORD
ADDRESS (n)
CONTROL
BYTE
S
CONTROL
BYTE
R __
_ __
T
T
o
P
SDA LINE
BUS ACTIVITY:
A
A
C
C
K
K
A
C
DATAn
K
FIGURE 7· SEQUENTIAL READ
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
:~~n
A
C
K
A
C
CONTROL
BYTE
K
1
A
C
K
:
: : :
DATAn
:r-r-:
: : I Ir-r-r--r-:
:
II:
r-r: -,:
DATA n + 1
DS20051C-6
S
T
0
P
A
C
K
I : : : : :
DATAn +2
I ~\I : : : : : : : 18
DATAn+X
© 1992 Microchip Technology Inc.
3-62
24LC16
WRITE PROTECTION
Noise Protection
The 24LC 16 can be used as a serial ROM when WP pin
is connected to Vee (+5V). Programming will be inhibited and the entire memory (2K by1es) will be writeprotected.
The 24LC16 employs a Vee threshold detector circuit
which disables the internal erase/write logic if the Vee is
below 1.5 volts at nominal conditions.
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device operation even on a noisy bus.
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the RiW bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
PIN DESCRIPTIONS
AOIWP Write Protect Input
This pin must be connected to either Vss or Vee.
If tied to Vee, WRITE operations are inhibited. The
entire 2K bytes memory will be write-protected. Read
operations are possible.
Current Address Read
The 24LC16 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with RiW bit set to one, the 24LC16 issues an acknowledge and transmits the eight bit data word. The
master will not acknowledge the transfer but does
generate a stop condition and the 24LC16 discontinues
transmission. (See Figure 5).
If tied to Vss, normal memory operation is enabled (readl
write the entire memory 000-7FF).
This feature allows the user to use the 24LC 16 as a serial
ROM when WP is enabled (tied to Vee).
A1. A2 Chip Address Inputs
The A 1 and A2 inputs are unused by the 24LC16. They
must be connected to Vss to insure proper device operation.
Random Read
SDA Serial Address/Data Input/Output
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24LC16 as part of a write operation. Afte~ the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then Jl:)e master issues the control by1e again but
with the RIW bit set to a one. The 24LC16 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24LC16 discontinues
transmission. (See Figure 6).
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCl Serial Clock
This input is used to synchronize the data transfer from
and to the device.
This pin must be connected to Vss.
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC16 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC16 to transmit the next sequentially
addressed 8 bit word. (See Figure 7).
To provide sequential reads the 24LC16 contains an
internal address pOinter which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
DS20051C-7
© 1992 Microchip Technology Inc.
3-63
24LC16
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
PACKAGE:
P
SL
I
TEMPERATURE
RANGE:
DEVICE:
Blank
I
E
24LC16
24LC16T
DS20051C-B
PLASTIC DIP
PLASTIC SOIC (150 mil Body)
O· C to +70' C
-40' C to +85' C
-40' Cto +125' C
16K CMOS Serial EEPROM
16K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-64
~.
59C11
Microchip
lK (128 x 8 or 64 x 16) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Low power CMOS technology
Pin selectable memory organization
- 128 x 8 or 64 x 16 bit organ ization
Single 5 volt only operation
Self timed WRITE, ERAL and WRAL cycles
Automatic erase before WRITE
RDY/BSY status information during WRITE
Power on/off data protection circuitry
• 100,000 ERASEIWRITE cycles
Data Retention> 40 Years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O'C to +70'C
- Industrial: -40'C to +85'C
- Automotive: -40'C to + 125'C
The Microchip Technology Inc. 59C11 is a 1K bit Electrically Erasable PROM. The device is configured as
128 x 8 or 64 x 16, selectable externally by means of the
control pin ORG. Advanced CMOS technology makes
this device ideal for low power non-volatile memory
applications. The 59C11 is available in the standard 8pin DIP and a surface mount SOIC package.
PIN CONFIGURATION
CS08
BLOCK DIAGRAM
DIP Package
elK
2
013
DO
4
7
Vee
Vee
RDY/BSY
Vss
ORG
60RG
5
Vss
CS08
SO Package
DI
cs
Vee
elK
2
7.
RDY/BSY
01
3
BORG
DO
4
5
ClK
Vss
© 1991 Microchip Technology Inc.
3-65
DS20040E-1
59C11
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings·
CS
ClK
01
DO
Vss
ORG
-RDY/BSY
Vee
*Notice: Stresses above those listed under "Maximum ratings" may
cause perman'ent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Chip Select
Serial Clock
Data In
Data Out
Ground
Memory Array Organization
Ready/Busy Status
+5 V Power Supply
Vee = +5 V (±10%)
Commercial: Tamb = O°C to +70°C
Industrial:
Tamb = -40°C to +85°C
Automotive: Tamb = -40°C to + 125°C (Note 3)
DC CHARACTERISTICS
Parameter
Function
Name
All inputs and outputs w.r.t. Vss .............. -0.3 V to +7.0 V
Storage temperature ............................ -65'C to + 150'C
Ambient temperature with
power applied ....................................... -65'C to + 125'C
Soldering temperature of leads (10 seconds) .... +300'C
ESD protection on all pins ..................................... .4 kV
Symbol
Min
Max
Conditions
Units
Vee detector threshold
VTH
2.8
4.5
V
High level input voltage
VIH
2.0
Vec + 1
V
low level input voltage
Vil
-0.3
0.8
V
High level output voltage
VOH
2.4
low level output voltage
10H = -400 IlA
V
VOL
0.4
V
Input leakage current
III
10
IlA
VIN = 0 V to Vee (Note 1)
10l = 3.2 mA
Output leakage current
IlO
10
IlA
VOUT = 0 V to Vee (Note 1)
Internal capacitance
(all inputs/outputs)
CINT
7
pF
VINNoUT = OV (Note 2)
Tamb = 25'C, f = 1 MHz
Operating current
(all modes)
leeo
4
mA
FelK = 1 MHz, Vee =5.5 V
Standby current
Ices
100
IlA
CS = 0 V, Vee = 5.5 V
Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: For operation above 85'C, endurance is rated at 10,000 ERASE/WRITE cycles.
SYNCHRONOUS DATA TIMING
elK
01
es
DO
© 1991 Microchip Technology Inc.
DS20040E-2
3-66
I,
t
59C11
AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
1
MHz
Clock frequency
FCLK
Clock high time
TCKH
500
ns
Clock low time
TCKL
500
ns
Chip select setup time
Tcss
50
ns
Conditions
Chip select hold time
TCSH
0
ns
Chip select low time
Tcs
100
ns
Data input setup time
TOls
100
ns
Data input hold time
TOIH
100
ns
Data output delay time
Tpo
400
ns
Cl = 100pF
Data output disable time (from CS = low)
Tcz
0
100
ns
Cl = 100pF
Data output disable time (from last clock)
Tooz
0
400
ns
Cl = 100 pF
-~
RDY/BSY delay time
TRBO
400
ns
Program cycle time (Auto Erase & Write)
Twc
1
15
ms
ms
for 8-bit mode
for ERAl and WRAl
in 8/16-bit modes
PIN DESCRIPTION
Chip Select (CS)
ClK cycles are not required during the self-timed WRITE
(i.e., auto erase/write) cycle.
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
WRITE cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal.
If CS is brought lOW during a WRITE cycle, the device
will go into standby mode as soon as the WRITE cycle
is completed.
After detection of a START condition the specified
number of clock cycles (respectively lOW to HIGH
transitions of ClK) must be provided. These clock
cycles are required to clock in all required opcode,
address, and data bits before an instruction is executed
(see instruction settruth table). When that limit has been
reached, ClK and 01 become "Don't Care" inputs until
CS is brought lOW for at least chip select low time
(TCSL) and brought HIGH again and a WRITE cycle (if
any) is completed.
CS must be lOW for 100 ns (TCSL) minimum between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.
Serial Clock (ClK)
The Serial Clock is used to synchronize the communication between a master device and the 59C11. Opcode, address, and data bits are clocked in on the
positive edge of ClK. Data bits are also clocked out on
the positive edge of ClK.
Data In (01)
Data In is used to clock in START bit, opcode, address
and data synchronously with the ClK input.
Data Out (DO)
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respectto clock high time (TCKH) and clock
low time (TCKL)). This gives freedom in preparing opcode,
address and data for the controlling master.
Data Out is used in the READ mode to output data
synchronously with the ClK input (Tpo after the positive
edge of ClK). This output is in HIGH-Z mode except if
data is clocked out as a result of a READ instruction.
01 and DO can be connected together to perform a 3wire interface (CS, ClK, 01/00).
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but a START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status (i.e., waiting for
START condition).
Care must be taken with the leading dummy zero which
is output after a READ command has been detected.
Also, the controlling device must not drive the 01/00 bus
during WRITE cycles.
DS20040E-3
© 1991 Microchip Technology Inc.
3-67
I
I
59C11
Organization (ORG)
DATA PROTECTION
This input selects the memory array organization. When
the ORG pin is connected to +5 V the 64 x 16 organization is selected. When it is connected to ground, the 128
x 8 organization is selected. If the ORG pin is left
unconnected, then an internal pullup device will select
the 64 x 16 organization. In applications subject to
electrical nc~ise, it is recommended that this pin not be
left floating, but tied either high or low.
During power-up, all modes of operation are inhibited
until Vcc has reached a level of between 2.8 V and 4.5
V. During power-down, the source data protection
circuitry acts to inhibit all modes when VCC has fallen
below the voltage range of 2.8 V to 4.5 V.
Ready/Busy (RDY/BSY)
After power-up, the device is automatically in the EWDS
mode. Therefore, EWEN instruction must be performed
before any WRITE, ERAl or WRAl instruction can be
executed. After programming is completed, the EWDS
instruction offers added protection against unintended
data changes.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
Pin 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAl, or
WRAl operation. When it is HIGH the internal, selftimed WRITE, ERAl or WRAl operation has been
completed and the device is ready to receive a new
instruction.
INSTRUCTION SET
Instruction
Start
Bit
READ
WRITE
EWEN
EWDS
ERAL
WRAL
1
1
1
1
1
1
64 X 16 MODE, ORG=1
Opcode
Address
1 0 X X
X 1 X X
,
1
0
1
0
0 0
0
0 0
0 0
a
A5
A5
A4 A3 A2
A4 A3 A2
A1
A1
AO
AO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
1
X
X
X
X
X
X
X
X
Data In
Data Out
Number of
Req. CLK Cycles
-
015 - DO
High·Z
High-Z
High·Z
High-Z
High-Z
27
27
11
11
11
27
015- DO
D15 - DO
128 X 8 MODE, ORG=O
Instruction
READ
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
Opcode
Address
1 0 X X
X 1 X X
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
A6 A5 A4
A6 A5 A4
A3
A3
A2
A2
A1
A1
AO
AO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FUNCTIONAL DESCRIPTION
Data In
Data Out
07 -DO
-
07 -DO
High·Z
High·Z
High-Z
High·Z
High·Z
07 -DO
Number of
Req. CLK Cycles
20
20
12
12
12
20
After execution of an instruction (i.e. clock in or out of the
last required address or data bit) ClK and 01 become
don't care bits until a new start condition is detected.
START Condition
The START bit is detected by the device if CS and 01 are
both High with respectto the positive edge of ClK forthe
first time.
Note: CS must go lOW between consecutive instructions.
DilDO Pins
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition) without resulting in any device operation (READ, WRITE, EWEN, EWDS, ERAl, and WRAl).
As soon as CS is HIGH, the device is no longer in the
standby mode.
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AD is a logic high level.
Under such a condition the voltage level seen at Data
Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AD. The higher the current sourcing capability of AD, the
higher the voltage at the Data Out pin.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
© 1991 Microchip Technology Inc.
DS20040E-4
3-68
59C11
READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 8- or 16-bit output string. The
output data changes during the high state of the system
clock (ClK). The dummy bit is output TPD after the
positive edge of ClK, which was used to clock in the last
address bit (AO). Therefore, care must be taken if 01 and
DO are connected together as a bus contention will
occur for one clock cycle if AO is a one.
READ MODE
DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bit DO orthe negative edge of CS, whichever occurs
first. DO remains stable between ClK cycles for an
unlimited time as long as CS stays HIGH.
The most significant data bit (015 or 07) is always output
first, followed by the lower significant bits (014 - DO or 06
- ~O).
ClK
'---I
I
01_
cs
Sf :
!/J
f\../\
I
I
OPC/,-DE-'mwr"V:m~AN"V~_jW"''17FA°"Vi~~lWi?JNWiW'i'~i;""",''lllW'1''';'1W
SB
x
DO - - - - - - - - - - NOTE:
Sf---ey
x
X
IX
TpD~ ~
/
I
I
~TDDz~
HIGH-Z--5~~
r-~~--+~~~~
NEW INSTRUCTION
OR STANDBY (CS" 0)
The WRITE instruction is followed by 8 or 16 bits of data
which are written into the specified address. The most
significant data bit (015 or 07) has to be clocked in first
followed by the lower significant data bits (014 - DO or
06 - ~O). If a WRITE instruction is recognized by the
device and all data bits have been clocked in, the device
performs an automatic erase cycle on the specified
WRITE MODE
ClK
address before the data are written. The WRITE cycle
is completely self timed and commences automatically
after the rising edge ofthe ClK signal forthe last data bit
(~O).
The WRITE cycle takes 1 ms max for 8-bit mode and 2
ms max for 16-bit mode.
12MI
TCSL--'
cs
---.ill
£
OPCODE
SB
AN
£
AO
ON
X
X
~
WM t=
I
<»>dI DO
"
o'aJ\Ll/\/\r\L'ij:W:E~ _~
1
x
1
X
DO - - - - - - - - - HIGH.Z
X
X
55
Ix
~
I
__I TRBD'--
ROY/BSY---------------~%----~~~I~I
I
: '-----,s-~
Twc
NEW INSTRUCTION
OR STANDBY (CS" 0)
DS20040E-5
© 1991 Microchip Technology Inc.
3-69
59C11
ERASE/WRITE Enable/Disable (EWEN, EWDS)
For added data protection, the device should be put in the
ERASE/WRITE Disable mode (EWDS) after programming operations are completed.
The device is automatically in the ERASE/WRITE Disable mode (EWDS) after power-up. Therefore, EWEN
instruction has to be performed before any WRITE,
ERAl, or WRAl instruction is executed by the device.
ERASE/WRITE ENABLE
AND DISABLE
CLK
'!~~LJ
~
CS
~- TeSL
~
=-z.zJ
I
I
AD
o
000
1
HIGH
DO
NOTE:
-z
SB
MNla:"""""---l!~~""""--~~
01
x
EWDS
EWEN
x
---~15----------t.----
I---:-::-::---::--+-:-::-I
NEW INSTRUCTION
OR STANDBY (CS = 0)
L-_____________________________________________________________________
~
ERASE All (ERAl)
EWEN mode. The ERAL cycle is completely self-timed
and commences after the rising edge of the elK signal
for the last dummy address bit. ERAL takes 15 ms max.
The entire chip will be erased to logical "1 SOl if this
instruction is received by the device and it is in the
ERASE ALL
(CHIP ERASE)
CLK
SB
SB
OPCODE
I\,--_~I\
DI _
/
HIGH - z - - i s ' ' - - r l-----:JI,..(_ _ _ _ _- - L - - _
DO
RDY/BSY
~
1-4-- TRBD
------------------4f'~~~t
NOTE:
I"
.1
Twe
I---:-=-.".--j-
I
NEW INSTRUCTION
OR STANDBY (CS = 0)
© 1991 Microchip Technology Inc.
DS20040E-6
3-70
59C11
WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the last data bit (DO) has
been clocked in. WRAL takes 15 ms max.
Note: The WRAL does not include an automatic ERASE
cycle for the chip. Therefore, the WRAL instruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases. The WRAL
instruction is used for testing and/or device initialization.
WRITE ALL
CLK~~IlJl-fS~~
I
TesH _ I
CS
~
=-zz;
%
I
~ --I
OPCODE
f\~_--,/
AN
AO
ON
X
X
X
I
I
I
DO
~!lS:>m ~~ _~
1
DO
~
t=
~oot
I
I
SB
I
~ TeSL
I X
I
(5
I
TRBD - - I ' - -
HIGH·Z
I
lS
I I
r-r-
RDY/BSY---------------------------------------~
:
14
I
~ "---->s----II
Twe
--I
NEW INSTRUCTION
OR STANDBY (CS. 0)
© 1991 Microchip Technology Inc.
1
I
J
DS20040E-7
3-71
59C11
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
P
Package:
SN
SM
I
I
Temperature
Range:
Blank
I
E
Device:
59Cll
59Cl1T
CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)
0' C to +70' C
-40' C to +85' C
-40' C to +125' C
1K CMOS Serial EEPROM
lK CMOS Serial EEPROM
(in Tape & Reel)
© 1991 Microchip Technology Inc.
DS20040E-8
3-72
85C72
Microchip
IK (128 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Low power CMOS technology
Organized as one block of 128 bytes (128 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention >40 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O'C to +70'C
-Industrial: -40'C to +85'C
-Automotive: -40'C to + 125'C
The Microchip Technology Inc. 85C72 is a 1 K bit Electrically Erasable PROM. The device is organized as 128
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows a significant reduction in power
over NMOS serial devices. Up to eight 85C72s may be
connected to the two wire bus. The 85C72 is available
in the standard 8-pin DIP and a surface mount SOIC
package.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AOos
A1
2
A23
Vss
4
7
Vee
NC
6SCL
5
SDA
SOA-.l1:;:;:==:::;-tr
SO Package
SCL
AO A1 A2
© 1990 Microchip Technology Inc.
3-73
OS111370-1
85C72
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
Function
Name
All inputs and outputs w.r.t. Vss
........ -0.3 V to +7 V
Storage temperature ....................... -6S'C to + 1S0'C
Ambient temp. with power applied ..... -6S'C to + 12S'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins .............................. ., .. 4.0 kV
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
No Connect
+S V Power Supply
AO, A1, A2
VSS
SDA
SCL
NC
VCC
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress, rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
vcc = +S V (±1 0%)
Commercial (C): Tamb
Industrial
(I): Tamb
Automotive (E): Tamb
DC CHARACTERISTICS
= O'C to +70'C
= -40'C to +8S'C
= -40'C to + 12S'C (Note 2)
Symbol
Min
Max
Units
Vce detector threshold
VTH
2.8
4.S
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
AO, A 1 & A2 pins:
High level input voltage
Low level input voltage
VIH
VIL
Vee - O.S
-0.3
Vee + O.S
O.S
V
V
Input leakage current
III
10
!LA
VIN
Output leakage current
ILO
10
!LA
VOUT
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
VINlVoUT = 0 V (Note 1)
Tamb = +2S'C, 1 = 1 MHz
Operating current
leeo
3.5
mA
4.25
mA
leeR
750
!LA
FeLK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = O'C to +70'C
FeLK = 100 kHz, program cycle
time = 1 ms, Vee = 5 V,
Tamb = (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)
Ices
100
!LA
Parameter
Read cycle
Standby current
Conditions
IOL = 3.2 mA (SDA only)
= 0 V to Vcc
= 0 V to Vcc
SDA = SCL = Vee = S V
(no PROGRAM active)
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85'C, endurance is rated at 10,000 ERASE/WRITE cycles.
BUS TIMING START/STOP
seL - - - - '
SDA-----r-..I
STOP
START
D811137D-2
© 1991 Microchip Technology Inc.
3-74
85C72
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
TR
1000
ns
SDA and SCl fall time
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
Data output delay time
TPD
300
TSU:STO
4700
ns
TBUF
4700
ns
STOP condition setup time
Bus free time
Input filter time constant
(SDA and SCl pins)
Program cycle time
ns
3500
TI
Twc
.7N
ns
100
ns
N
ms
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N
of bytes to be written
=#
Note 1: As transmitter, the device must provide this internal minimum delay time to bridgethe undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
8el
THD:sTA _ _ TLOW _
~
THD:DAT (receiver)
TPD
(transmitter)
8DA
_TsUF
FUNCTIONAL DESCRIPTION
Both, master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
The 85C72 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the start
and STOP conditions, while the 85C72 works as slave.
Up to eight 85C72s can be connected to the bus,
selected by the AO, A 1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C72 (refer to section
Slave Address).
0811137D-3
© 1991 Microchip Technology Inc.
3-75
85C72
BUS CHARACTERISTICS
The following bus protocol has been defined:
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
Data transfer may be initiated only when the bus is
not busy.
.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
During data transfer, the data line must remain stable
whenever the clock line is HIGH .. Changes in the
data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Bus not Busy (A)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
Note: The 85C72 does not generate any acknowledge
bits if an internal programming cycle is in progress.
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(C)
(A)
(8)
SCL ---+---1,--.,.
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
© 1991 Microchip Technology Inc.
DS11137D-4
3-76
85C72
SLAVE ADDRESS
address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C72. The most significant bit of
the word address is a "Do Not Care" value for the 85C72.
After receiving the acknowledge of the 85C72, the
master device transmits the data word to be written into
the addressed memory location. The 85C72 acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle of the
85C72. (See Figure 3.)
The chip address inputs AD, A1 and A2 of each 85C72
must be externally connected to either Vcc or ground
(Vss), assigning to each 85C72 a unique 3-bit address.
Up to eight 85C72s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AD, A 1 and A2 of the slave address to the
corresponding hardwired logic levels of the selected
85C72.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1 01 0) for the 85C72, followed by the chip address
bits AD, A 1 and A2.
PAGE PROGRAM
The eighth bit of slave address determines if the master
device wants to read or write to the 85C72. (See Figure
2.)
To program the 85C72, the master sends addresses
and data to the 85C72 which is the slave. (See Figure
3.) This is done by supplying a START condition
followed by the 4-bit device code, the 3-bit slave address, and the Rm bit which is defined as a logic LOW
for a write. This indicates to the addressed slave that a
word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the 85C72,
it places it in the lower 8 bits of the address pOinter
defining which memory location is to be written. (One"
Do Not Care" bit and seven address bits.) The 85C72
will generate an acknowledge after every 8 bits received
and store them consecutively in a 2-byte RAM until a
STOP condition is detected which initiates the internal
programming cycle. If more than 2 bytes are transmitted
by the master, the 85C72 will terminate the write cycle.
This does not affect erase/write cycles of the EEPROM
array.
The 85C72 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.
FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START
/'
/
I'
/
/
I
1
I :
READIWRITE
S:LAV~ AD~RE~S
'-.....
: ,
,
A
(Rml
,,
I
D
D
A2
A1
AD
MODE
I
If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
BYTE PROGRAM MODE
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will be
written in a serial manner.
In this mode, the master sends addresses and one data
byte to the 85C72.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Rm bit, which is logic
LOW, are placed onto the bus by the master. This
indicates to the addressed 85C72 that a byte with a word
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).
FIGURE 3 - PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE
DS11137D-5
© 1991 Microchip Technology Inc.
3-77
85C72
READ MODE
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
This mode illustrates master device reading data from
the 85C72.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode the address pointer must be
written to.) During this period the 85C72 generates the
necessary acknowledge bits as defined in the appropriate section.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
In all modes, the address pointer will automatically
increment from the end of the memory block (128 bytes)
back to the first location in that block.
FIGURE 4 - READ MODE
AUTO INCREMENT
WORD ADDRESS
R
PIN DESCRIPTION
AQ, A1 and A2 Chip Address Inputs
NC No Connect
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
This pin can be left open or used as a tie point.
Up to eight 85C72s can be connected to the bus.
Notes:
These inputs must be connected to either Vss or Vcc.
1) A "page" is defined as the maximum number of bytes
that can be programmed in a single write cycle. The
85C72 page is 2 bytes long.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
2) A "block" is defined as a continuous area of memory
with distinct boundaries. The address pOinter can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 85C72 has only one
block (128 bytes).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
D511137D-6
© 1991 Microchip Technology Inc.
3-78
85C72
NOTES:
D811137D·7
© 1991 Microchip Technology Inc.
3·79
85C72
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
PACKAGE:
J
P
SM
I
TEMPERATURE
RANGE:
I
DEVICE:
Blank
I
E
85C72
85C72T
D811137D-8
CERDIP
Plastic DIP
Plastic SOIC (0.207 mil Body)
O' C to +70' C
-40' C to +85' C
-40' C to +125' C
1K CMOS SERIAL EEPROM
1K CMOS SERIAL EEPROM
(in Tape & Reel)
© 1991 Microchip Technology Inc.
3-80
85C82
Microchip
2K (256 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Low power CMOS technology
• Organized as one block of 256 bytes (256 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 2 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention >40 years
• 8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O"C to +70"C
-Industrial: -40"C to +85"C
-Automotive: -40"C to + 125"C
The Microchip Technology Inc. 85C82 is a 2K bit Electrically Erasable PROM. The device is organized as 256
x 8 bit memory with a two wire serial interface. Advanced
CMOS technology allows a significant reduction in power
over NMOS serial devices. The 85C82 also has a pagewrite capability for up to 2 bytes of data. Up to eight
85C82s may be connected to the two wire bus. The
85C82 is available in standard 8-pin DIP and surface
mount SOIC package.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package
AD
8
Vee
A1
2
7
NC
A2
3
6
SCL
Vss
4
5
SDA
SDA--1t:;:;:;:::;:;:;:;:;-1r
SO Package
AD
Vee
A1
NC
A2
SCL
Vss
SDA
SCL
AOA1 A2
© 1991 Microchip Technology Inc.
3-81
DS11136E-1
85C82
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings*
All inputs and outputs W.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65'C to +150'C
Ambient temp. with power applied ..... -65T to +125'C
Soldering temperature 01 leads (10 seconds) .. +300'C
ESD protection on all pins ..................................... 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the devics. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
Name
Function
AO, A1, A2
Vss
SDA
SCL
NC
Vee
Chip Address Inputs
Ground
Serial Address/Data InpuVOutput
Serial Clock
No Connect
+5 V Power Supply
may affect device reliability.
Vee = +5 V (±10%)
Commercial (C): Tamb = O'C to +70"C
Industrial
(I): Tamb = -40'C to +85'C
Automotive (Ei: Tamb = -40'C to +125"C (Note 2)
DC CHARACTERISTICS
Symbol
Min
Max
Units
Vec detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
AO, A1 & A2 pins:
High level input voltage
Low level input voltage
VIH
VIL
Vee - 0.5
-0.3
Vee + 0.5
0.5
V
V
Parameter
Conditions
IOL = 3.2 mA (SDA only)
Input leakage current
III
10
I-lA
VIN = 0 V to Vcc
Output leakage current
ILO
10
I-lA
VOUT = 0 V to Vcc
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
Operating current
leeo
VINlVoUT = 0 V (Note 1)
= +25'C, 1 = 1 MHz
T amb
3.5
mA
4.25
mA
read cycle
leeR
750
I-lA
FeLK = 100 kHz, program cycle time = 1 ms,
Vee = 5 V, Tamb = O'C to +70"C
FeLK = 100 kHz, program cycle time = 1 ms,
Vee = 5 V, Tamb = (I) and (E)
Vee = 5 V, Tamb= (C), (I) and (E)
Standby current
Ices
100
I-lA
SDA = SCL = Vee = 5 V(no PROGRAM active)
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles
BUS TIMING START/STOP
SCL ______J
SDA
----------r,1
START
STOP
DS11136E-2
© 1991 Microchip Technology Inc.
3-82
85C82
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLow
4700
ns
SDA and SCL rise time
TR
1000
ns
SDA and SCL fall time
TF
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
Tsu:sTA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
Data output delay time
TpD
300
TSU:STO
4700
ns
TSUF
4700
ns
STOP condition setup time
Bus free time
Input filter time constant
(SDA and SCL pins)
Program cycle time
3500
TI
Twc
.7N
ns
100
ns
N
ms
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N = #
of bytes to be written
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
SCL
.......-..
THD:DAT (receiver)
TPD
(transmitter)
SDA
_TBUF
FUNCTIONAL DESCRIPTION
slave. Both, master and slave can operate as transmitter or receiver, but the master device determines which
mode is activated.
The 85C82 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 85C82 works as
Up to eight 85C82s can be connected to the bus,
selected by the AO, A1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C82 (refer to section
Slave Address).
DS11136E-3
© 1991 Microchip Technology Inc.
3-83
85C82
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not
busy.
The data on the line must be changed during the lOW
period of the clock signal. There is one clock pulse per
bit of data.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 1):
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
Bus not Busy (A)
Acknowledge
Both data and clock lines remain HIGH.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Start Data Transfer (B)
A HIGH to lOW transition of the SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Note: The 85C82 does not generate any acknowledge
bits if an internal programming cycle is in progress.
The device that acknowledges, hastopulidowntheSDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out olthe slave. In this case the slave must
leave the data line HIGH to enable the master to generate the STOP condition.
Stop Data Transfer (C)
A lOW to HIGH transition of the SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (D)
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(C)
(8)
(A)
SCL
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
DS11136E-4
STOP
CONDITION
© 1991 Microchip Technology Inc.
3-84
85C82
SLAVE ADDRESS
The chip address inputs AO, Aland A2 of each 85C82
must be externally connected to either Vee or ground
(Vss), assigning to each 85C82 a unique 3-bit address.
Up to eight 85C82s may be connected to the bus. Chip
selection is then accomplished through software by
setting the bits AO, Al and A2 of the transmitted slave
address to the corresponding hardwired logic levels of
the selected 85C82.
LOW, are placed onto the bus by the master. This
indicates to the addressed 85C82 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C82. After receiving the
acknowledge of the 85C82, the master device transmits
the data word to be written into the addressed memory
location. The 85C82 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C82. (See Figure
3.)
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 85C82, followed by the chip address
bits AO, Al and A2.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C82. (See Figure
2.)
PAGE PROGRAM
To program the 85C82, the master sends addresses
and data to the 85C82 which is the slave (see Figure 3).
This is done by supplying a START condition followed by
the 4-bit device code, the 3-bit slave address, and the
RiW bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C82, it places it in the lower
8 bits of the address pOinter defining which memory
location is to be written. The 85C82 will generate an
acknowledge after every 8 bits received and store them
consecutively in a 2-byte RAM until a stop condition is
detected which initiates the internal programming cycle.
If more than 2 bytes are transmitted by the master, the
85C82 will terminate the write cycle. This does not affect
eraselwrite cycles of the EEPROM array.
The 85C82 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.
FIGURE 2· SLAVE ADDRESS
ALLOCATION
/
/
/
/
START
I
:
READIWRITE
S:LAV~ AD~RES:S
'-...
:
\
\
0
f
(R/wl A
\
/
0
A2
A1
AO
'I
If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will be
written in a serial manner.
BYTE PROGRAM MODE
In this mode the master sends addresses and one data
byte to the 85C82.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the RiW bit, which is logic
FIGURE 3 • PROGRAM MODE (ERASEIWRITE)
START
MODE
A
ACKNOWLEDGES FROM SLAVE
DATA BYTE 1
DATA BYTE N
A STOP
P
© 1991 Microchip Technology Inc.
DS11136E-5
3-85
85C82
READ MODE
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
This mode illustrates master device reading data from
the 85C82.
As can be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 85C82 generates
the necessary acknowledge bits as defined in the appropriate section.
Note: If the master knows where the address pointer is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
data from the addressed location on to the SDA pin,
Note: In all modes, the address pointer will automatically
increment from the end of the memory block (256 byte)
back to the first location in that block.
FIGURE 4· READ MODE
R/W
AUTO INCREMENT
WORD ADDRESS
R
PIN DESCRIPTION
AD. A1 and A2 Chip Address Inputs
NC No Connect
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
This pin can be left open or used as a tie point.
Notes:
Up to eight 85C82s can be connected to the bus.
1} A "page" is defined as the maximum number of bytes
that can be programmed in a Single write cycle. The
85C82 page is 2 bytes long.
These inputs must be connected to either Vss or VCC.
SDA Serial Address/Data Input/Output
2} A "block" is defined as a continuous area of memory
with distinct boundaries. The address pointer can not
cross the boundary from one block to another. It will
however, wrap around from the end of a block to the first
location in the same block. The 85C82 has only one
block (256 bytes).
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal. For normal data transfer SDA is allowed to
change only during SCL LOW. Changes during SCL
HIGH are reseNed for indicating the START and STOP
conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
DS11136E-6
© 1991 Microchip Technology Inc.
3-86
85C82
NOTES:
© 1991 Microchip Technology Inc.
DS11136E-7
3-87
85C82
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
J
P
PACKAGE:
SM
I
I
TEMPERATURE
RANGE:
DEVICE:
Blank
I
E
85C82
85C82T
CERDIP
Plastic DIP
Plastic SOIC (0.207 mil Body)
0' Cto +70' C
_40' C to +85' C
_40' C to +125' C
2K CMOS Serial EEPROM
2K CMOS Serial EEPROM
(in Tape & Reel)
© 1991 Microchip Technology Inc.
DS11136E-8
3-88
~.
85C92
Microchip
4K (512 X 8) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
• LDW power CMOS technology
The Microchip Technology Inc. 85C92 is a 4K bit Electrically Erasable PROM. The device is organized as two
blocks of 256 x 8 bit memory with a two wire serial
interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. The
85C92 also has a page-write capability for up to 8 bytes
of data. Up to four 85C92s may be connected to the two
wire bus. The 85C92 is available in the standard 8-pin
DIP and a surface mount SOIC package.
•
•
•
•
Organized as two blocks of 256 bytes (2 x 256 x 8)
Two wire serial interface bus
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
1ms write cycle time for single byte
100,000 erase/write cycles
Data retention >40 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
-Commercial: O'C to +70'C
-Industrial: -40'C to +85'C
-Automotive: -40'C to + 125'C
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
AD
Vee
A1
NC
A2
SCl
Vss
SDA
SOA
SO Package
AD
Vee
A1
NC
A2
SCl
Vss
SDA
SCL
AD A1 A2
© 1991 Microchip Technology Inc.
3-89
OS111460-1
85C92
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
Name
All inputs and outputs w.r.t. Vss ................ -0.3 V to +7 V
Storage temperature ....................... -65·C to + 150·C
Ambient temp. with power applied ..... -65·C to + 125·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins .................................... .4 kV
Function
AO
No function. Must be connected to
Vce or Vss
A1, A2
Chip address Inputs
Vss
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
those indicated in the operational listings of this specification is not
NC
No Connect
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vee
+5 V Power Supply
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
Vee: + 5 V (±10%)
Commercial (C): Tamb: O·C to +70·C
(I): Tamb: -40·C to +85·C
Industrial
Automotive (E): Tamb: -40·C to + 125·C (Note 2)
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
VOL
Vee x 0.7
-0.3
Vee + 1
Vee x 0.3
0.4
V
V
V
A1 & A2 pins:
High level input voltage
Low level input voltage
VIH
VIL
Vee - 0.5
-0.3
Vee + 0.5
0.5
V
V
Conditions
IOL : 3.2 mA (SDA only)
Input leakage current
III
10
fLA
VIN : 0 V to Vcc
Output leakage current
ILo
10
fLA
VOUT : 0 V to Vcc
Internal capacitance
(all inputs/outputs)
CINT
7.0
pF
VINlVoUT : 0 V (Note 1)
TAMB: 25·C, f: 1 MHz
Operating current
leeo
3.5
mA
4.25
mA
leeR
750
fLA
FeLK : 100 kHz, program cycle
time: 1 ms, Vee: 5 V,
Tamb : O·C to +70·C
FeLK : 100 kHz, program cycle
time: 1 ms, Vee: 5 V,
Tamb : (I) and (E)
Vee: 5 V, Tamb: (C), (I) and (E)
lees
100
fLA
read cycle
Standby current
SDA : SCL : Vee: 5 V
(no PROGRAM active)
Note 1: ThiS parameter IS periodically sampled and not 100% tested.
Note 2: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles.
BUS TIMING START/STOP
SCL _ _- J
SDA
-----'""1
START
STOP
© 1991 Microchip Technology Inc.
D811146D-2
3-90
85C92
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
100
kHz
Clock frequency
FCLK
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCl rise time
TR
SDA and SCl fall time
TF
1000
ns
300
ns
Remarks
START condition hold time
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
ns
Data output delay time
STOP condition setup time
Bus free time
TPD
300
TSU:STO
4700
ns
TSUF
4700
ns
Input filter time constant
(SDA and SCl pins)
Program cycle time
ns
3500
TI
Twc
.7N
100
ns
N
ms
See Note 1
Time the bus must be free
before a new transmission
can start
Byte or Page mode N = #
of bytes to be written
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min 300
ns) of the falling edge of SCl to avoid unintended generation of START or STOP conditions.
BUS TIMING DATA
SCL
THD:DAT (receiver)
T PO
(transmitter)
SOA
_TsUF
FUNCTIONAL DESCRIPTION
The 85C92 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCl), controls the bus access, and generates the
START and STOP conditions, while the 85C92 works as
slave. Both, master and slave can operate as transmit-
ter or receiver but the master device determines which
mode is activated.
Up to four 85C92s can be connected to the bus, selected
by the A 1 and A2 chip address inputs. AO must be tied
to Vcc or Vss. Other devices can be connected to the
bus but require different device codes than the 85C92
(refer to section Slave Address).
© 1991 Microchip Technology Inc.
OSll1460-3
3-91
85C92
BUS CHARACTERISTICS
The following bus protocol has been defined:
period of the clock signal. There is one clock pulse per
bit of data.
Data transfer may be initiated only when the bus is not
busy.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
a START or STOP condition.
Acknowledge
Accordingly, the following bus conditions have been
defined (see Figure 1):
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Bus not Busy (A)
Both data and clock lines remain HIGH.
Note: The 85C92 does not generate any acknowledge
bits if an internal programming cycle is in progress.
Start Data Transfer (B)
A H IG H to lOW transition olthe SDA line while the clock
(SCl) is HIGH determines a START condition. All
commands must be preceded by a START condition.
The device that acknowledges, has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable lOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Stop Data Transfer (C)
A lOW to HIGH transition olthe SDA line while the clock
(SCl) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the lOW
FIGURE 1 - DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCl
(8)
(A)
--+--1"""\
SDA
START CONDITION
ADDRESS
DATA AllOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
© 1991 Microchip Technology Inc.
OS111460-4
3-92
85C92
SLAVE ADDRESS
indicates to the addressed 85C92 that a byte with a word
address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 85C92. After receiving the
acknowledge of the 85C92, the master device transmits
the data word to be written into the addressed memory
location. The 85C92 acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 85C92. (See Figure
3.)
The chip address inputs A 1 and A2 of each 85C92 must
be externally connected to either Vec or ground (Vss),
assigning to each 85C92 a unique 2-bit address. Up to
four 85C92s may be connected to the bus. Chip selection is then accomplished through software by setting
the bits A1 and A2 of the slave address to the corresponding hardwired logic levels of the selected 85C92.
AD is not used and must be connected to either Vee or
Vss.
After generating a start condition, the bus master transmits the slave address consisting of a 4-bit device code
(1010) for the 85C92, followed by the chip address bits
A1 and A2. The seventh bit of that byte (BA) is used to
select the upper block (addresses 100-1 FF) or the
lower block (addresses O~~-OFF) of the 85C92.
PAGE PROGRAM
The eighth bit of slave address determines if the master
device wants to read or write to the 85C92. (See Figure
2.)
The 85C92 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if
the slave address was true and it is not in a programming
mode.
FIGURE 2 - SLAVE ADDRESS
ALLOCATION
START
/'"
READ/WRITE
S:LAV~ AD~RES:S
1
/
~
:
r
(R/wl A
\.
/
\.
/
/
0
A2
0
A1
\.
SA
MODE
To program the 85C92, the master sends addresses
and data to the 85C92 which is the slave (see Figure 3).
This is done by supplying a START condition followed by
the 4-bit device code, the 3-bit slave address, and the
R/W bit which is defined as a logic LOW for a write. This
indicates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to the
master during the ninth clock pulse. When the word
address is received by the 85C92, it places it in the lower
8 bits of the address pointer defining which memory
location is to be written. (The BA bit transmitted with the
slave address is the ninth bit of the address pointer.) The
85C92 will generate an acknowledge after every 8 bits
received and store them consecutively in an 8-by1e RAM
until a STOP condition is detected which initiates the
internal programming cycle. If more than 8 bytes are
transmitted by the master, the 85C92 will roll over and
overwrite the data beginning with the first received by1e.
This does not affect erase/write cycles of the EEPROM
array and is accomplished as a result of only allowing
the address registers bottom 3 bits to increment while
the upper 5 bits remain unchanged.
,
If the master generates a STOP condition after transmitting the first data word (Point 'P' on Figure 3), byte
programming mode is entered.
I
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to 8) data bytes will be
written in a serial manner.
BYTE PROGRAM MODE
In this mode the master sends addresses and one data
by1e to the 85C92.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8).
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the Riw bit, which is logic
LOW, are placed onto the bus by the master. This
FIGURE 3 - PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE
p
R/W
DS11146D-5
© 1991 Microchip Technology Inc.
3-93
85C92
READ MODE
This mode illustrates master device reading data from
tbe 85C92.
data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is only
aborted when the master sends a STOP condition
instead of an acknowledge.
As C;l.n be seen from Figure 4, the master first sets up the
slave and word addresses by doing a write. (Note:
Although this is a read mode, the address pointer must
be written to.) During this period the 85C92 generates
the necessary acknowledge bits as defined in the appropriate section.
Note: If the master knows where the address pOinter is,
it can begin the read sequence at point 'R' indicated on
Figure 4 and save time transmitting the slave and word
addresses.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs the
In all modes, the address pointer will not increment
through a block (256 byte) boundary but will wrap around
to the first location in that block.
FIGURE 4 - READ MODE
R/W
R/W
R
AUTO INCREMENT
WORD ADDRESS
PIN DESCRIPTION
AO
SCL Serial Clock
This pin must be connected to eitherVcc or Vss.
This input is used to synchronize the data transfer from
and to the device.
A1. A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
NC No Connect
This pin can be left open or used as a tie point.
Up to four 85C92s can be connected to the bus.
Notes:
These inputs must be connected to either Vss or Vcc.
1) A "page" is defined as the maximum number of
bytes that can be programmed in a single write cycle.
The 85C92 page is 8 bytes long.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and
data into and data out of the device. It is an open drain
terminal.
2) A "block" is defined as a continuous area of
memory with distinct boundaries. The address
pointer can not cross the boundary from one block to
another. It will however, wrap around from the end of
a block to the first location in the same block. The
85C92 has two blocks, 256 bytes each.
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
D811146D-6
© 1991 Microchip Technology Inc.
3-94
85C92
NOTES:
© 1991 Microchip Technology Inc.
08111460-7
3-95
85C92
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
PACKAGE:
J
P
SM
I
I
Blank
I
E
TEMPERATURE
RANGE:
DEVICE:
85C92
85C92T
CERDIP
Plastic DIP
Plastic SOIC (0.207 mil Body)
O' C to +70' C
·40' C to +85' C
-40' C to +125' C
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM
(in Tape & Reel)
© 1991 Microchip Technology Inc.
OS111460-8
3-96
93C06
Microchip
256 Bits (16 X 16) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
• Low power CMOS technology
• 16 x 16 bit memory organization
Single 5 volt only operation
Self-timed ERASE and WRITE cycles
• Automatic ERASE before WRITE
Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles (typical)
Data Retention> 40 Years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O'C to +70'C
- Industrial: -40'C to +85'C
- Automotive: -40'C to + 125'C
The Microchip Technology Inc. 93C06 is a 256 bit serial
Electrically Erasable PROM. The device memory is
configured as 16 x 16 bits. Advanced CMOS technology
makes this device ideal for low power non-volatile memory
applications. The 93C06 is available in the standard 8pin DIP and a surface mount SOIC package.
{)
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package
csOa
eLK
2
DI
DO
Vee
vss
Vee
7
Test
3
6
Test
4
5
Vss
DO
cs
01
SO Package
es
Vee
ClK
Test
DI
Test
DO
Vss
elK
~ [rdri,n1T'Wlj~!'m
© 1992 Microchip Technology Inc.
3-97
DS11150E-1
93C06
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings*
All inputs and outputs w.r.t. Vss .............. -0.3 Vto +7.0 V
Storage temperature ............................ -65°C to + 150°C
Ambient temperature with
power applied ...................................... -65°C to + 125°C
Soldering termperature of leads (10 seconds) ... +300°C
ESO protection on all pins ..................................... .4 kV
Name
Function
CS
ClK
01
DO
Chip Select
Serial Clock
Data In
Data Out
Ground
Recommend tie to vss or Vee
+5 V Power Supply
Vss
Test
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vee
Vee = +5 V (±10%)
Commercial:
Industrial:
DC CHARACTERISTICS
Tamb=
O°C to +70°C
Tamb = -40°C to +85°C
Tamb = -40°C to + 125°C (Note 3)
Automotive:
Parameter
Symbol
Min
Max
Units
l
Conditions
Vee detector threshold
VTH
2.8
4.5
V
High level input voltage
VIH
2.0
Vee + 1
V
low level input voltage
Vil
-0.3
0.8
High level output voltage
VOH
2.4
low level output voltage
VOL
0.4
V
10l = 3.2 mA
Input leakage current
III
10
J.tA
VIN = 0 V to Vee (Note 1)
Output leakage current
ILO
10
J.lA
VOUT = 0 V to Vee (Note 1)
Internal capacitance
(all inputs/outputs)
CINT
7
pF
VINlVoUT = 0 V~Note 2)
Tamb = +25"C, = 1 MHz
Operating current
(all modes)
leeo
4
mA
FelK = 1 MHz, Vee = 5.5 V
Standby current
Ices
100
J.lA
CS = Vss, Vce = 5.5 V
V
V
10H = -400 J.lA
Note 1: Internal resistor pull-up at Pin 6.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles.
SYNCHRONOUS DATA TIMING
elK
01
es
DO
©1992 Microchip Technology Inc.
DS11150E-2
3-98
93C06
AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
1
MHz
Conditions
Clock frequency
FCLK
Clock high time
TCKH
500
ns
Clock low time
TCKL
500
ns
Chip select setup time
Tcss
50
ns
Chip select hold time
TcsH
0
ns
Chip select low time
TCSL
100
ns
Data input setup time
To IS
100
ns
Data input hold time
TOIH
100
Data output delay time
Tpo
400
ns
Cl - 100 pF
Tcz
0
100
ns
Cl - 100 pF
0
Data output disable time (from CS
= low)
ns
Data output disable time (from last clock)
Tooz
400
ns
Cl - 100 pF
Status valid time
Tsv
100
ns
Cl
Program cycle time (Auto Erase & Write)
Twc
2
15
ms
ms
for ERAl and WRAl
Erase cycle time
TEC
1
ms
Endurance
---
100,000
= 100 pF
EIWCycies
PIN DESCRIPTION
Chip Select (CS)
ClK cycles are not required during the self-timed WRITE
(i.e,. auto ERASEIWRITE) cycle.
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle, the
device will go into standby mode as soon as the programming cycle is completed.
CS must be lOW for 100 ns minimum (TCSL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.
After detection of a START condition, the specified
number of clock cycles (respectively lOW to HIGH
transitions of ClK) must be provided. These clock
cycles are required to clock in all required opcode,
address, and data bits before an instruction is executed
(see instruction settruth table). elK and 01 then become
"Don't Care" inputs waiting for anew start condition to be
detected.
Serial Clock (ClK)
Note: CS must go lOW between consecutive instructions.
The Serial Clock is used to synchronize the communication between a master device and the 93C06. Opcode, address, and data bits are clocked in on the
positive edge of ClK. Data bits are also clocked out on
the positive edge of ClK.
pata In (01)
Data In is used to clock in a Start bit, opcode, address,
and data synchronously with the elK input.
pata Out (DO)
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime (with respectto clock HIGH time (TCKH) and clock
lOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
Data Out is used in the READ mode to output data
synchronously with the ClK input (Tpo after the positive
edge of ClK).
This pin also provides READY/mJSY status information
during ERASE and WRITE cycles. READ'Y'7BUSY status information is available on the DO pin if CS is brought
high after being low for minimum chip select lOW time
(TCSL) from the falling edge of the ClK which clocked in
the last 01 bit (DO for WRITE, AD for ERASE) and an
ERASE or WRITE operation has been initiated.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status. (i.e., waiting for
START condition).
DS11150E-3
©1992 Microchip Technology Inc.
3-99
93e06
The status signal is not available on DO, if CS is held
lOW or HIGH during the entire WRITE or ERASE cycle.
In all other cases DO is in the HIGH-Z mode. If status is
checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal.
Care must be taken with the leading dummy zero which
is outputted after a READ command has been detected.
Also, the controlling device must not drive the DilDO bus
during ERASE and WRITE cycles if the READY/BOS'Y
status information is output by the 93C06.
01 and DO can be connected together to perform a 3wire interface (CS, ClK, DilDO).
INSTRUCTION SET
Instruction
Start
BIT
Opcode
OP1 OP2
READ
1
WRITE
1
1 0
0 1
ERASE
1
1
EWEN
1
0 0
0 0
0 0
0 0
EWDS
1
ERAL
1
WRAL
1
Number of
Data In
Address
1
Data Out
Req. CLK Cycles
0
0
0
0
0
0
A3 A2
AI
AO
-
015 - DO
25
A3 A2
AI
AO
015 - DO
(RDY/BSY)
25
A3 A2
At
-
(RDY/BSY)
1
1
X
X
X
AD
X
X
X
X
-
High-Z
-
(RDY/BSY)
9
9
9
9
I 0
0
X
X
X
1
0
X
X
X
0
1
X
X
X
015 - DO
High-Z
-
(RDY/BSY)
25
FUNCTIONAL DESCRIPTION
START Condition
During power-down, the source data protection circuitry
acts to inhibit all modes when Vee has fallen below the
range of 2.8 V to 4.5 V.
The start bit is detected by the device if CS and 01 are
both HIGH with respect to the positive edge of ClK for
the first time.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is High, the device is no
longer in the standby mode.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be performed before any ERASE, or WRITE instruction can be
executed. After programming is completed, the EWDS
instruction offers added protection against unintended
data changes.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
READ Mode
After execution of an instruction (I.e., clock in or out of
the last required address or data bit) ClK and 01 become
don't care bits until a new START condition is detected.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 16-bit output string. The output
data changes during the high state of the system clock
(ClK). The dummy bit is output TPD after the positive
edge of ClK, which was used to clo,ck in the last address
bit (AO). Therefore, care must be taken if 01 and DO are
connected together as a bus contention will occur for
one clock cycle if AO has been a "1".
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the. voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.
DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bit DO or the negative edge of CS, whichever occurs
first.
Data Protection and Noise .Immunity
DO remains stable between ClK cycles for an unlimited
time as long as CS stays HIGH.
During power-up, all modes of operation are inhibited
until Vce has reached a level of between 2.8 Vand 4.5 V.
The most significant data bit (015) is always outputfirst,
followed by the lower significant bits (014 - DO).
©1992 Microchip Technology Inc.
DS11150E-4
3-100
93C06
READ MODE
ClK
CS
SB
OP1
OP2
A3
I AO
I
r-\'--_----:-~a'---""'~; ~~
DID.
I
Tpo __ l~
DO - - - - - - - - - - - HIGH-Z
~
~
Tooz
I
',O~~
NEW INSTRUCTION
OR STANDBY (CS ~ 0)
WRITE Mode
The WRITE instruction is followed by 16 bits of data
which are written info the specified address. The most
significant data bit (D15) has to be clocked in first,
followed by the lower significant data bits (D14 - DO). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an
WRITE MODE
automatic ERASE cycle on the specified address before
the data are written. The WRITE cycle is completely selftimed and commences automatically after the rising
edge of the elK signal for the last data bit (DO).
The WRITE cycle takes 2 ms max.
ClK
~I TesL
CS~
AO
015
I.ot-- - - ' TesL
'--
:~r
I CHECK I
I DO
I
!m:E~
~TDDZ
I
0 0 - - - - - - - - - - - HIGH - Z --------?r-,---~
NEW INSTRUCTION
OR STANDBY (CS ~ 0)
ERASE Mode
The ERASE instruction forces all the data bits of the
specified address to logical "1 s". The ERASE cycle is
completely self-timed and commences automatically
ERASE MODE
after the last address bit has been clocked in.
The ERASE cycle takes 1 ms max.
I
CLK~~IB~
,--I
TeSL
,-rr---------------------r'-cl
cs~
_ _I TeSL
I
I
1_ _
I
:\~
SB
DI~
'--
/
OP1
OP2
"--__
A3
'ro.~,Q;i\7(j
: CHECK:
rA~~
..-I
I
Tsv __ 1
I_ _ Tooz
I
~
'1-
HIGH - Z --------'-----;J--~ BSY I RDY I
DO
1___
I
TEe
--.:
NEW INSTRUCTION
OR STANDBY (CS ~ 0)
DS11150E-5
©1992 Microchip Technology Inc.
3-101
g3e06
ERASEIWRITE Enable/Disable (EWEN. EWDS)
device. For added data protection, the device should be
put in the ERASEIWRITE Disable mode (EWDS) after
programming operations are completed.
The device is automatically in the ERASEIWRITE Disable mode (EWDS) after power-up. Therefore. an EWEN
instruction has to be performed before any ERASE,
WRITE, ERAL, WRAL instruction is executed by the
ERASE/WRITE
ClK ~m~_
ENABLE/DISABLE
SB
DI~
OP1
OP2
1
SB
~~
1\
o
1
0
1
X
X
X
X
(EWDS)
(EWEN)
jj
NEW INSTRUCTION
OR STANDBY (CS ~ 0)
ERASE All (ERAl)
commences after the last dummy address bit has been
clocked in.
The entire chip will be erased to logical "1 s" if this
instruction is received by the device and it is in the EWEN
mode. The ERAL cycle is completely self-timed and
ERAL takes 15 ms max.
ERASE All
DO - - - - - - - - - - - - HIGH·Z _ _ _---1_ _-%---.1., BSY I
j
I
_Twc~
NEW INSTRUCTION
OR STANDBY (CS _ 0)
WRITE All (WRAl)
cycle forthe chip. Therefore, the WRALinstruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases.
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the last data bit (DO) has
been clocked in. WRAL takes 15 ms max.
The WRAL instruction is used for testing and/or device
initialization.
Note: The WRAL does not include an automatic erase
WRITE All
S8
OP1
QP2
~~=~~=~~".,.,.:D::.:';;.,5""
DI~,----:-_ _ _~/ 1 ~
I DO
$Wf\
I
I
~~T"
DO - - - - - - - - - - - HIGH.Z _ _ _ _ _ _ _ _+--_ _ I BSv
I
7'RDY'--
+-li--"I"-'
~Twc ~
1
NEW INSTRUCTION
OR STANDBY (CS ~ 0)
©1992 Microchip Technology Inc.
DS11150E-6
3-102
93C06
NOTES:
DS11150E-7
©1992 Microchip Technology Inc.
3-103
93C06
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
P
SN
SM
I
'--~_ _-II
Temperature
Range:
I
'--------1'0
.
eVlce:
Blank
I
E
93C06
93C06T
CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)
0' C to +70' C
-40' C to +85 C
-40' C to +125' C
0
256-Bit CMOS Serial EEPROM
256-Bit CMOS Serial EEPROM
(in Tape & Reel)
L_~~~~~~~~~~~~~~~~~~~~~-----,
©1992 Microchip Technology Inc.
DS11150E-8
3-104
93C46
Microchip
lK (64 X 16) CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
Low power CMOS technology
64 x 16 bit memory organization
Single 5 volt only operation
Self-timed ERASE and WRITE cycles
Automatic ERASE before WRITE
Power on/off data protection circuitry
1,000,000 ERASE/WRITE cycles (typical)
Data Retention> 40 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: O'C to +70'C
- Industrial: -40'C to +85'C
- Automotive: -40'C to + 125'C
The Microchip Technology Inc. 93C46 is a 1K bit serial
Electrically Erasable PROM. The device memory is
configured as 64 x 16 bits. Advanced CMOS technology
makes this device ideal for low power non-volatile memory
applications. The 93C46 is available in the standard 8pin DIP and a surface mount SOIC package. The
93C46X comes as SOIC only.
o
BLOCK DIAGRAM
PIN CONFIGURATION
es
o~IP
paCka~e
Vee
elK
2
7
Test
01
3
6
Test
004
5Vss
DO
e~:O': ~P""~:'02: : :'
01
3
6
004
Test
SVss
93C46
Vss
Vee
CS
3
CLK4
6
01
es
DO
501
elK
93C46X
© 1992 Microchip Technology Inc.
3-105
DS20041E-1
93C46
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs W.r.t. Vss .............. -0.3 V to +7.0 V
Storage temperature ............................ -65°C to + 150°C
Ambient temperature with
power applied ........................................ -65"C to + 125C
Soldering termperature of leads (10 seconds) ... +300°C
ESD protection on all pins ..................................... .4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
Name
Function
CS
ClK
01
DO
Vss
Test
Vee
Chip Select
Serial Clock
Data In
Data Out
Ground
Recommend tie to Vss or Vcc
+5 V Power Supply
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vee = +5 V (±10%)
Commercial: Tamb= O°C to +70°C
Industrial:
Tamb = -40°C to +85°C
Automotive:
Tamb = -40°C to +125°C (Note 3)
DC CHARACTERISTICS
Parameter
Vee detector threshold
Symbol
Min
Max
Units
VTH
2.8
4.5
V
Conditions
High level input voltage
VIH
2.0
Vee + 1
V
low level input voltage
Vil
-0.3
0.8
V
High level output voltage
VOH
2.4
V
IOH = -400 IlA
low level output voltage
VOL
0.4
V
IOl = 3.2 mA
~
Input leakage current
III
10
IlO
10
IlA
IlA
VIN = 0 V to Vee (Note 1)
Output leakage current
Internal capacitance
(all inputs/outputs)
CINT
7
pF
VINlVoUT = 0 V INote 2~
Tamb = +25"C, = 1 M z
Operating current
(all modes)
leeo
4
mA
FelK = 1 MHz, Vee = 5.5 V
Standby current
Ices
100
IlA
CS = 0 V, Vee = 5.5 V
VOUT = 0 V to Vee (Note 1)
Note 1: Internal resistor pull~up at Pin 6.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles.
SYNCHRONOUS DATA TIMING
ClK
DI
cs
DO
©1992 Microchip Technology Inc.
DS20041 E~2
3-106
93C46
AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
1
MHz
Clock frequency
FCLK
Clock high time
TCKH
500
ns
Clock low time
TCKL
500
ns
Chip select setup time
Tcss
50
ns
Chip select hold time
TCSH
0
ns
Chip select low time
TCSL
100
ns
Data input setup time
TOls
100
ns
Data input hold time
TOIH
100
Data output delay time
Tpo
Data output disable time (from CS = low)
Tcz
Conditions
ns
400
ns
CL = 100 pF
0
100
ns
CL = 100pF
0
Data output disable time (from last clock)
Tooz
400
ns
CL = 100 pF
Status valid time
Tsv
100
ns
CL = 100 pF
Program cycle time (Auto Erase & Write)
Twc
2
15
ms
ms
for ERAL and WRAL
Erase cycle time
TEC
1
ms
Endurance
---
100,000
E/WCycies
PIN DESCRIPTION
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the
programming cycle is completed.
CLK cycles are not required during the self-timed WRITE
(i.e., autoERASE/WRITE) cycle.
After detection of a start condition, the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are required
to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set
truth table). CLK and DI then become "Don't Care"
inputs waiting for a new start condition to be detected.
CS must be LOW for 100 ns minimum (TCSL) between
consecutive instructions. ·If CS is LOW, the internal
control logic is held in a RESET status.
Note: CS must go LOW between consecutive instructions.
Serial Clock (ClK)
Data In (01)
The Serial Clock is used to synchronize the communication between a master device and the 93C46. Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
Data In is used to clock in a START bit, opcode, address,
and data synchronously with the CLK input.
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the CLK input (Tpo after the positive
edge of CLK).
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime (with respecttoclock HIGH time (TCKH) and clock
LOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
This pin also provides READY/BtI3V status information
during ERASE and WRITE cycles. READvtBtJSY status information is available on the DO pin if CS is brought
HIGH after being LOW for minimum chip select LOW
time (TCSL) from the falling edge of the CLK which
clocked in the last DI bit (DO for WRITE, AD for ERASE)
and an ERASE or WRITE operation has been initiated.
CLK is a "Don't Care" if CS is LOW (device deselected).
If CS is HIGH, but STARTcondition has not been detected, any number of clock cycles can be received by
the device without changing its status. (i.e., waiting for
START condition).
DS20041E-3
©1992 Microchip Technology Inc.
3-107
93C46
Care must be taken with the leading dummy zero which
is outputted after a READ command has been detected.
Also, the controlling device must not drive the DilDO bus
during Erase and Write cycles if the READY/BUSY
status information is outputted by the 93C46.
The status signal is not available on DO, if CS is held
lOWor HIGH during the entire WRITE or ERASE cycle.
In all other cases DO is in the HIGH-Z mode. If status is
checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal.
01 and DO can be connected together to perform a 3wire interface (CS, ClK, DilDO).
INSTRUCTION SET
Instruction
Start
BIT
Opcode
OPl OP2
Number of
Data In
Address
Data Out
Req. ClK Cycles
READ
1
A4
A3 A2
A1
AO
-
015- DO
25
1
1 0
0 1
A5
WRITE
A5
A4
A3 A2
A1
AO
015 - DO
(RDY/BSY)
25
ERASE
1
1
1
A5
A4 A3 A2
A1
AO
(RDY/BSY)
EWEN
1
1
1
EWDS
1
0
ERAL
1
1
0
0
WRAL
1
0 0
0 0
0 0
0 0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
-
~
X
X
X
X
-
High-Z
-
(RDY/BSY)
9
9
9
9
015 - DO
(RDY/BSY)
25
High-Z
-
FUNCTIONAL DESCRIPTION
START Condition
acts to inhibit all modes when Vee has fallen below the
range of 2.S V to 4.5 V.
The START bit is detected by the device if CS and 0 I are
both HIGH with respect to the positive edge of ClK for
the first time.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is HIGH, the device is no
longer in the standby mode.
After power-up, the device is automatically in the EWDS
mode_ Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be
executed. After programming is completed, the EWDS
instruction offers added protection against unintended
data changes.
An instruction following a START condition will only be
executed ifthe required amount of opcode, address and
data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) ClK and 01
become don't care bits until a new start condition is
detected.
READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy bit
(logical 0) precedes the 16-bit output string. The output
data changes during the HIGH state of the system clock
(ClK). The dummy bit is output TPD after the positive
edge of ClK, which was used to clock in the last address
bit (AO). Therefore, care must be taken if 01 and DO are
connected together as a bus contention will occur for
one clock cycle if AO has been a one.
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.
DO will go into HIGH-Z mode with the positive edge of
the next ClK cycle. This follows the output of the last
data bit DO or the low going edge of CS, which ever
occurs first.
Data Protection
DO remains stable between ClK cycles for an unlimited
time as long as CS stays HIGH.
During power-up, all modes of operation are inhibited
until Vce has reached a level of between 2.S Vand 4.5 V.
During power-down, the source data protection circuitry
The most significant data bit (015) is always output first,
followed by the lower significant bits (014 - DO).
©1992 Microchip Technology Inc.
DS20041E-4
3-10S
93C46
READ MODE
~
I
ClK
I
I
I'"
~,,~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _~~
~SL
~I
~
I~I
III
CS
DID,
DO - - - - - - - - - - - - - - - - - - - -
NEW INSTRUCTION
OR STANDBY ICS" 0)
WRITE Mode
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. The most
significant data bit (015) has to be clocked in first,
followed by the lower significant data bits (014 - ~O). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an
automatic ERASE cycle on the specified address before
the data are written. The WRITE cycle is completely selftimed and commences automatically after the rising
edge of the elK for the last data bit (~O).
The WRITE cycle takes 2 ms max.
WRITE MODE
ClK
~I
TCSL
~ ~TCSL ~
:~
I
SB
OP1
OP2
Ol~ ~
A5
A4
A3
AD
015
CHECK
I
I DO
m m i~m:»%U
I
(S
~
II
~..-Tsv
~TDDZ
I
I
II
0 0 - - - - - - - - - - - - - - - - - - - HIGH - Z
----------------i$i--r----~IHy'(~'
BSY ~
,
j
I _ Twe _ _ I
I
,
NEW INSTRUCTION
OR STANDBY ICS _ 0)
ERASE Mode
The ERASE instruction forces all the data bits of the
specified address to logical "1s". The ERASE cycle is
completely self-timed and commences automatically
after the last address bit has been clocked in.
The ERASE cycle takes 1 ms max.
ERASE MODE
I
ClK~~J~
CS
~I
rTr--------------------------,~1
--.lZ/
t.-
~I
TCSL
I~
1"\--4---f:fSTATUS)-r-I
I
S8
Ol~
TCSL
/
OP1
OP2
A5
A4
A3
lAO
I
CHECK
I
: '---./,
~
'%: »>< ~~~
\
Tsv __ 1 ~
DO - - - - - - - - - - - - - - - - - - - HIGH
-z -
~I
--------;------cli----"""I
I 8SY
,___
,
TEe
I~TDDZ
I
1
ROY
~
NEW INSTRUCTION
OR STAN08Y ICS" 0)
©1992 Microchip Technology Inc.
DS20041E-5
3-109
93C46
ERASEIWRITE Enable/Disable (EWEN. EWDS)
by the device. For added data protection, the device
should be put in the ERASE/WRITE Disable mode
(EWDS) after programming operations are completed.
The device is automatically in the ERASE/WRITE Disable mode (EWDS) after power-up. Therefore, an
EWEN instruction has to be performed before any
ERASE, WRITE, ERAL, WRAL instruction is executed
ERASE/WRITE
ClK m~nJ
ENABLE/DISABLE
~TCSl~
CS--LLI~~----------------------~~r--t~-SB
DI~
OP1
OP2
SB
1
~5~
1\
o1
0
1
X
X
X
(EWDS)
(EWEN)
X
NEW INSTRUCTION
OR STANDBY (CS. 0)
1
~--------------------------------------------------~
ERASE All (ERAl)
commences after the last dummy address bit has been
clocked in.
The entire chip will be erased to logical "1 s" if this
instruction is received by the device and it is in the EWEN
mode. The ERAL cycle is completely self-timed and
ERASE All
ClK
ERAL takes 15 ms max.
~Ir
OOOO","",""L--,
,CS
~
..-I
Tcsl
~
~------------------------------~:~~;rSB
DI
Tcsl
OP1
~
OP2
1
1
1
I\'----;;-'~=;==;=;:;,:;:;=--.,s----+-----J---~,5
1
1 Tooz"'-I
1
r--
Tsv ~
DO - - - - - - - - - - - - - - - - - - - - - - - - HIGH· Z
-------'------%-------11 BSY
1
~
1
'I
~TWC~
NEW INSTRUCTION
OR STANDBY (CS. 0)
WRITE All (WRAl)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely selftimed and commences after the rising edge of the eLK
for the last data bit (DO). WRAL takes 15 ms max.
cycle for the chip. Therefore, the WRAL instruction must
be preceded by an ERAL instruction and the chip must
be in the EWEN status in both cases.
The WRAL instruction is used for testing and/or device
initialization.
Note: The WRAL does not include an automatic ERASE
WRITE All
~
rr-7----------------'I~i
cs ~
I
S8
DI
OP1
QP2
D15
1
TCSL
~ ~TCSL ~
~ .¥-STATUS ~
''-------II
CHECK
1
DO
I
~r\~____/.----.rn~rwvwv""""""'''''''''"'<1W'lW<~~-:....wp_t___'-L--\SS-;_ _ _
1
1
X
X
X
x
I
1
1
~~T"
1
7RDY'------
DO - - - - - - - - - - - - - - - - - - - - - HIGH _Z _______________ -----L----I BSY
I
~I""·
~ Twc ~I
~
NEW INSTRUCTION
OR STANDBY (CS _ O)
©1992 Microchip Technology Inc.
DS20041E-6
3-110
93C46
NOTES:
I
i
©1992 Microchip Technology Inc.
DS20041E-7
3-111
93C46
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
J
P
SN
SM
I
Temperature
Blank
Range:
' - - - - - - - - - 1 Device:
I
E
93C46
93C46X
93C46T
93C46XT
CERDIP
Plastic DIP
Plastic SOIC (0.150 mil Body)
Plastic SOIC (0.207 mil Body)
0° C to +70° C
-40° C to +85° C
-40° C to +125° C
1K CMOS Serial EEPROM
1K CMOS Serial EEPROM with
alternate pinouts (in SN package only)
(in Tape & Reel)
(in Tape & Reel)
©1992 Microchip Technology Inc.
DS20041E-8
3-112
93C56
Microchip
2K CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
The Microchip Technology Inc. 93C56 is a 2K bit serial
Electrically Erasable PROM. The device memory is
configured as 256 x 8 or 128 x 16 bits depending on the
ORG pin configuration. Advanced CMOS technology
makes this device ideal for low power non-volatile memory
applications. The 93C56 is available in the standard 8pin DIP and 8-pin surface mount SOIC package.
• Low power CMOS technology
• ORG pin selectable memory organization
256 x 8 or 128 x 16 bit organization
• Single 5 volts only operation
• Max clock at 2MHz
Self-timed ERASE and WRITE cycles
• Automatic ERASE before WRITE
• Power on/off data protection circuitry
• Industry standard 3-wire serial 110
• Device status signal during ERASEIWRITE cycles
• Sequential READ function
1,000,000 ERASE/WRITE cycles (typical)
• Data retention> 40 years
• 8-pin PDIP/SOIC packages
(SOIC in JEDEC and EIAJ standards)
• Available for extended temperature ranges:
Commercial:
O'C to + 70'C
Industrial:
-40'C to +85'C
Automotive: -40'C to +125'C
PIN CONFIGURATION
BLOCK DIAGRAM
eso.
Vee
Vss
DIP Package
elK
2
7
013
DO
Vee
TEST
60RG
4
5
Vss
eso.
DO
SO Package
eLK
Vee
TEST
2
7
01
3
60RG
DO
4
5
Vss
93C56
In
if
© 1992 Microchip Technology Inc.
~il
3-113
DS11156E-1
93C56
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings*
All inputs and outputs W.r.t. Vss ............. -0.3 V to +7.0 V
Storage temperature ....................... -6S"C to +lS0"C
Ambient temp. with power applied ..... -6S"C to +12S"C
Soldering temperature of leads (10 seconds) .. +300"C
ESD protection on all pins ..................................... 3 kV
Name
Function
CS
ClK
01
'Notice: Stresses above those listed under "Maximum ratings' may
cause permanent damage to the device. This is astress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
Implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Vss
ORG
Test
Vee
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Array Organization
Connect to Vss or Vce
Power Supply +S V
DO
Vee = +S V (+10%/-20%)
Commercial
(C): Tamb= O"C to +70"C
Industrial
(I) : Tamb = -40"C to +8S"C
(Note 2) Automotive (E): Tamb = -40"C to +12S"C
DC AND AC ELECTRICAL
CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.3
4.0
V
High level input voltage
VIH
2.0
Vee + 1
V
low level input voltage
VIL
-0.3
0.8
High .level output voltage
VOH
2.4
low level output voltage
VOL
Input leakage current
III
Output leakage current
Output capacitance
Conditions
V
V
IOH=-400~
0.4
V
IOL= 2.1 mA
10
~
VIN = 0 V to Vee
ILO
10
~
VOUT= 0 Vto Vee
COUT
7
pF
VIN!VOUT = 0 V; Note 1
VIN!VOUT = 0 V; Note 1
Input capacitance
CIN
7
pF
Operating current (all modes)
leeo
4
mA
FeLK = 2 MHz; Vee = S.S V
Standby current
Ices
130
~
CS = a V; Vee = S.S V; x 8 org
100
~
CS = a V; Vee = S.S V; x 16 org
Endurance
---
100,000
EIWCycles
Clock frequency
FeLK
Clock high time
TeKH
sao
ns
Clock low time
TCKL
500
ns
Chip select setup time
Tess
so
ns
Relative to ClK
Chip select hold time
TesH
0
ns
Relative to ClK
Chip select low time
TesL
100
ns
Data input setup time
TOls
100
ns
Data input hold time
TOIH
100
ns
Relative to ClK
Data output delay time
Tpo
400
ns
Cl= 100 pF
Data output disable time
Tez
100
ns
Cl= 100 pF
Status valid time
Tsv
100
ns
Cl = 100 pF
Program cycle time
Twe
1
ms
(x 8 organization)
2
ms
(x 16 organization)
1S
ms
ERAl & WRAl mode
2
(auto ERASE & WRITE)
TEe
MHz
Relative to ClK
Note 1: This parameter is tested at Tamb = 2S"C and FCLK = 1 MHz. It is periodically sampled and not 100% tested.
Note 2: For operation above 8S"C, endurance is rated at 10,000 ERASEIWRITE cycles.
DS111S6E-2
© 1992 Microchip Technology Inc.
3-114
93C56
INSTRUCTION SET FOR 93C56
ORG = 1 (x 16 organization)
Instruction
5B
Address
Opcode
READ
1
10
EWEN
1
00
ERASE
1
11
ERAl
1
00
WRITE
1
01
WRAl
1
00
EWDS
1
00
5B
Opcode
X A6 A5
1 1 X
X A6 A5
1 0 X
X A6 A5
0 1 X
0 0 X
Data In
-
A4 A3 A2 A 1 AD
X X X X X
A4 A3 A2 A 1 AD
X X X X X
Data Out
Req. ClK Cycles
015 - DO
27
High-Z
11
(RDY/BSY)
11
(RDY/BSY)
11
A4 A3 A2 A1 AD
015 - DO
(RDY/BSY)
27
X X X X X
X X X X X
015 - DO
(RDY/BSY)
27
High-Z
11
-
ORG = 0 (x 8 organization)
Instruction
READ
1
10
EWEN
1
00
ERASE
1
11
ERAl
1
00
WRITE
1
01
WRAl
1
00
EWDS
1
00
Address
X A7 A6
1 1 X
X A7 A6
1 0 X
X A7 A6
0 1 X
0 0 X
Data In
Data Out
Req. ClK Cycles
A5 A4 A3 A2 A1 AD
-
07 - DO
20
X X X X X X
-
High-Z
12
A5 A4 A3 A2 A1 AD
-
(RDY/BSY)
12
X X X X X X
-
(RDY/BSY)
12
A5 A4 A3 A2 A1 AD
D7 - DO
(RDY/BSY)
20
X X X X X X
X X X X X X
07 - DO
(RDY/BSY)
20
High-Z
12
-
FUNCTIONAL DESCRIPTION
The 93C56 can be organized as either 128 registers by
16 bits, or as 256 registers by 8 bits. When the ORG pin
is connected to Vcc, the (x16) organization is selected.
When it is connected to ground, the (x8) organization is
selected. If the ORG pin is left unconnected, then an
internal pullup device will select the (x16) organization.
Instructions, addresses and write data are clocked into
the 01 pin on the rising edge of the clock (ClK). The DO
pin is normally held in a high-Z state except when
reading data from the device, or when checking the
ready/busy status during a programming operation. The
ready/busy status can be verified during an Erase/Write
operation by polling the DO pin; DO low indicates that
programming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the ClK.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
Afterexecution of an instruction (i.e., clock in or out olthe
last required address or data bit) ClK and 01 become
don't care bits until a new start condition is detected.
DilDO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AD is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AD. The higher the current sourcing capability of AD, the
higher the voltage at the Data Out pin.
START Condition
The START bit is detected by the device if CS and DI are
both HIGH with respect to the positive edge of elK for
the first time.
Data Protection
During power-up, all modes of operation are inhibited
until Vcc has reached a level of between 2.3 V and 4.0
V. During power-down, the source data protection
circuitry acts to inhibit all modes when Vcc has fallen
below the range of 2.3 V to 4.0 V.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is HIGH, the device is no
longer in the standby mode.
DS11156E-3
© 1992 Microchip Technology Inc.
3-115
93C56
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
(TesL). DO at logical "0" indicates that programming is
still in progress. DO at logical "1" indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be
executed. After programming is completed, the EWDS
instruction offers added protection against unintended
data changes.
The WRITE cycle takes 1 ms per byte max.
ERASE ALL
READ
The ERAl instruction will erase the entire memory array
to the logical "1 ". The ERAl cycle is identical to the
ERASE cycle exceptforthe differentopcode. The ERAl
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit (x8
organization) output string. The output data bits will
toggle on the rising edge of the ClK and are stable after
the specified time delay (Tpo). Sequential read is possible when CS is held high. The memory data will
automatically cycle to the next register and output sequentially.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TesL).
ERASE/WRITE ENABLE AND
DISABLE
The ERAl cycle takes 15 ms max.
WRITE ALL
The 93C56 powers up in the Eraseiwrite Disable (EWDS)
state. All programming modes must be preceded by an
EraselWrite Enable (EWEN) instruction. Once the EWEN
instruction is executed, programming remains enabled
until an EWDS instruction is executed or Vee is removed
from the device. To protect against accidental data
changes, the EWDS instruction can be used to disable
all EraselWrite functions and should follow all programming operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
The WRAl instruction will write the entire memory array
with the data specified in the command. The WRAl
cycle is comnpletely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode. The WRAl command does not include an
automatic ERASE cycle for the device. Therefore, the
WRAl instruction must be preceded by an ERAl instruction and the chip must be in the EWEN status in
both cases.
ERASE
The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TesL).
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TesL). DO at Jogical "0" indicates that programming
is still in progress. DO at logical "1" indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
PIN DESCRIPTION
The WRAl cycle takes 15 ms max.
Chip Select (CS)
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle, the
device will go into standby mode as soon as the programming cycle is completed.
The ERASE cycle takes 1 ms per byte max.
WRITE
The WRITE instruction is followed by 16 bits (or by 8 bits)
of data which are written into the specified address.
After the last data bit is put on the DI pin, CS must be
brought low before the next rising edge of the ClK clock.
This falling edge of CS initiates the self-timed auto-erase
and programming cycle.
CSmust be lOW for 100 ns minimum (TesL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.
© 1992 MicroChip Technology Inc.
DS11156E-4
3-116
93C56
Serial Clock (ClK)
Data In (01)
The Serial Clock is used to synchronize the communication between a master device and the 93C56. Opcode,
address, and data bits are clocked in on the positive
edge of ClK. Data bits are also clocked out on the
positive edge of ClK.
Data In is used to clock in a START bit, opcode, address,
and data synchronously with the ClK input.
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (TPD after the positive
edge of ClK).
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime with respect to clock HIGH time (TCKH) and clock
lOW time (TCKl). This gives the controlling master
freedom in preparing opcode, address, and data.
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought
HIGH after being lOW for minimum chip select lOW
time (TCSl) and an ERASE or WRITE operation has
been initiated.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status (Le., waiting for
START condition).
Organization (ORG)
When ORG is connected to VCC, the (x16) memory organization is selected. When ORG is tied to Vss, the (x8)
memory organization is selected. When ORG is left
floating, an internal pullup device will selectthe device in
(x16) organization.
ClKcycles are not required during these If-timed WRITE
(Le., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively lOW to HIGH transitions of
ClK) must be provided. These clock cycles are required
to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set
truth table). ClK and 01 then become don't care inputs
waiting for a new start condition to be detected.
Test
This pin is used for test mode only. It is recommended
to connect to Vcc or Vss for normal operation.
Note: CS must go lOW between consecutive instructions.
TIMING DIAGRAMS
SYNCHRONOUS DATA TIMING
VIH
CS
VIL
Tcss
TCKH
TCKL
VIH
ClK
VIL
VIH
01
VIL
DO
(READ)
VOH
DO
(PROGRAM)
VOH
VOL
VOL
© 1992 Microchip Technology Inc.
DS11156E-5
3-117
93C56
TIMING DIAGRAMS (Cont.)
READ
cs
~
DO ________~T~R~I-S~T~AT~E~______________
0 ~;;~:.~'--~I\:.;0::J\~~f-~ -
• Address bit A7 becomes a "don't care" (x16 mode).
• Address bit A8 becomes a "don't care" (x8 mode).
* The memory automatically cycles to the next register.
EWEN
cs
~
nJ1JLSUlIlflJ1JL
ClK
EWDS
cs
~
~~~O_________O~~~~----------------
DI ____
WRITE
cs
~
L
DO __________~T~R~I-S~T~A~TE~________~----------_*~----~----,
,,,.
• Address bit A7 becomes a "don't care" (x16 mode).
• Address bit A8 becomes a "don't care" (x8 mode).
© 1992 Microchip Technology Inc.
DS11156E-6
3-118
93C56
TIMING DIAGRAMS (Cont.)
WRAL
r------------------jj.!5----------j~>_____,:
cs
-.I
LI
I
I
ClK
nJ~1JVlJlSL
::.v-oi
DI
~'---------
DO ______~T~R~I-S~T~A~T~E_ _ _ _ _ _ _ _ _~~~------~%--:_----,~~
READY
i.. ~
....----n",-Ee-~
ERASE
Tesl
cs
DI
DO-~~~~-----------~---~t_-~
Address bit A7 is a "don't care" (x16 mode).
Address bit AS is a "don't care" (xB mode).
Twc
ERAL
TeSl
cs
DI
DO __~TR~I-~S~TA~T~E_ _ _ _ _ _ _ _ _ _ _ _~----_____j~r_-~
TEe
DSll156E-7
© 1992 Microchip Technology Inc.
3-119
93C56
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
PACKAGE:
I
TEMPERATURE
RANGE:
I
DEVICE:
P
SN
SM
Blank
I
E
93CS6
93CS6T
DS11156E-8
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
PLASTIC SOIC (0.207 mil Body)
O'Clo+70'C
-40' C 10 +85' C
-40' C to +125' C
2K CMOS Serial EEPROM
2K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-120
~.
93C66
Microchip
4K CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
•
•
•
•
•
Low power CMOS technology
ORG pin selectable memory organization
Single 5 volts only operation
Max clock at 2MHz
Self-timed ERASE and WRITE cycles
Automatic ERASE before WRITE
Power on/off data protection circuitry
Industry standard 3-wire serial I/O
Device status signal during ERASEIWRITE cycles
Sequential READ function
1,000,000 ERASEIWRITE cycles (typical)
Data retention> 40 years
8-pin PDIP/SOIC
(SOIC in JEDEC and EIAJ standards)
Available for extended temperature ranges:
Commercial:
O"C to + 70"C
Industrial:
-40"C to +85"C
Automotive: -40"C to + i 25"C
The Microchip Technology Inc. 93C66 is a 4K bit serial
Electrically Erasable PROM. The device memory is
configured as 512 x 8 or 256 x 16 bits depending on the
ORG pin configuration. Advanced CMOS technology
makes this device ideal for low power non-volatile memory
applications. The 93C66 is available in the standard 8pin DIP and 8-pin surface mount SOIC package.
PIN CONFIGURATION
BLOCK DIAGRAM
•
•
•
•
•
•
•
•
tAtAE~OEO
~01f\ECO
cso.
DIP Package
elK
2
7
013
DO
Vee
Vss
Vee
TEST
60RG
4
5
Vss
csO.
DO
DI
SO Package
ORG
es
Vee
elK
2
7
TEST
01
3
60RG
DO
4
5
elK
Vss
93C66
© 1992 Microchip Technology Inc.
3-121
DS11158E-1
93C66
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings· .All inputs andautputs w.r,t. Vss ............. -0.3 V to +7.0 V
Storage temperature .. :.................... -6S·C to +1S0·C
Ambient temp ..with power applied ..... -6S·C to +12S·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins ..................................... 3 kV
·Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above
those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Name
Function
CS
ClK
01
DO
Vss
ORG
Test
Vee
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Array Organization
Connect to Vss or Vee
Power Supply +S V
."
Vee = +S V (+ 10%1-20%)
Commercial
(C): Tamb= O·Cto +70·C
Industrial
(I) : Tamb = -40·C to +8S·C
(Note 2) Automotive (E): Tamb = -40·C to +12S·C
DC AND AC ELECTRICAL
CHARACTERISTICS
Symbol
Min
Max
Units
Vee detector threshold
VTH
2.3
4.0
V
High level input voltage
VIH
2.0
Vee + 1
V
low level input voltaae
VIL
-0.3
0.8
V
High level output voltage
VOH
2.4
Parameter
low level output voltage
Input leakage current
Output leakage current
Output capacitance
Input capacitance
IIA
V
IOH = -400
VOL
0.4
V
IOL= 2.1 mA
III
10
IlA
VIN = 0 V to Vee
ILO
10
7
IlA
pF
VOUT = 0 V to Vee
COUT
CIN
7
pF
VINNoUT = 0 V; Note 1
mA
FeLK = 2 MHz; Vee = S.S V
IIA
IIA
CS = 0 V; Vee = S.S V; x 8 org
Ooeratina current(all modes)
leeo
4
Standby current
Ices
130
100
Endurance
Conditions
---
100,000
VINNoUT = 0 V; Note 1
CS= 0 V; Vee = S.S V; x 16 org
EfWCycles
2
. MHz
Clock fre-,!uenC}1
FeLK
Clock high time
TeKH
SOO
ns
Clock low time
TeKL
SOO
ns
Chip select setup time
Tess
SO
ns
Relative to ClK
Relative to ClK
Chip select hold time
TesH
0
ns
Chip select low time
TesL
100
ns
Data inout setuo time
To IS
100
ns
Relative to ClK
Data input hold time
TOIH
100
ns
Relative to ClK
Data output delay time
Tpo
400
ns
Cl= 100 pF
Data output disable time
Tez
100
ns
Cl= 100 pF
Status valid time
Tsv
100
ns
Cl= 100 pF
Program cycle time
Twe
(auto ERASE & WRITE)
TEe
1
ms
(x 8 organization)
2
ms
(x 16 organization)
1S
ms
ERAl & WRAl mode
Note 1. ThiS parameter IS tested at Tamb = 25 C and FCLK = 1 MHz. It IS periodically sampled and not 100010 tested.
Note 2:. For operalion above 8S"C, endurance is rated at 10,000 ERASElWRITE c y c l e s . . . ".
DS11158E-2
© 1992 Microchip Technology Inc.
3-122
93C66
INSTRUCTION SET FOR 93C66
ORG = 1 (x 16 organization)
Instruction
58
Opcode
Address
Data In
Data Out
Req. ClK Cycles
READ
1
10
A7· AO
-
015 - DO
27
EWEN
1
00
11XXXXXX
-
High-Z
11
ERASE
1
11
A7 - AO
(RDY/BSY)
11
ERAl
1
00
10XXXXXX
-
WRITE
1
01
A7 - AO
WRAl
1
00
01XXXXXX
EWDS
1
00
OOXXXXXX
(RDY/BSY)
11
015 - DO
(RDY/BSY)
27
015 - DO
(RDY/BSY)
27
High-Z
11
Data Out
Req. ClK Cycles
07 - DO
20
-
ORG = 0 (x 8 organization)
Instruction
58
Opcode
Address
Data In
READ
1
10
AS -AO
EWEN
1
00
11XXXXXXX
ERASE
1
11
AS-AO
-
High-Z
12
(RDY/BSY)
12
-
ERAl
1
00
10XXXXXXX
(RDY/BSY)
12
WRITE
1
01
AS-AO
07 - DO
(RDY/BSY)
20
WRAl
1
00
01XXXXXXX
07 - DO
(RDY/BSY)
20
EWDS
1
00
OOXXXXXXX
High-Z
12
-
FUNCTIONAL DESCRIPTION
The 93C66 can be organized as either 256 registers by
16 bits, or as 512 registers by S bits. When the ORG pin
is connected to Vee, the (x16) organization is selected.
When it is connected to ground, the (xS) organization is
selected. If the ORG pin is left unconnected, then an
internal pull up device will select the (x16) organization.
Instructions, addresses and write data are clocked into
the 01 pin on the rising edge of the clock (ClK). The DO
pin is normally held in a high-Z state except when
reading data from the device, or when checking the
ready/busy status during a programming operation. The
ready/busy status can be verified during an EraselWrite
operation by polling the DO pin; DO low indicates that
programming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the ClK.
An instruction following a START condition will only be
executed if the required amount of opcode, address and
data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out olthe
last required address or data bit) ClK and 01 become
don't care bits until a new start condition is detected.
DilDO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.
START Condition
The START bit is detected by the device if CS and 01 are
both HIGH with respect to the positive edge of ClK for
the first time.
Data Protection
During power-up, all modes of operation are inhibited
until Vec has reached a level of between 2.3 V and 4.0
V. During power-down, the source data protection
circuitry acts to inhibit all modes when Vee has fallen
below the range of 2.3 V to 4.0 V.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is HIGH, the device is no
longer in the standby mode.
© 1992 Microchip Technology Inc.
DS11158E-3
3-123
93C66
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
(TCSL). DO at logical "0" indicates that programming is
still in progress. DO at logical "1" indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be
executed. After programming is completed, the EWDS
instruction offers added protection against unintended
data changes.
The WRITE cycle takes 1 ms per byte max.
ERASE ALL
READ
The ERAl instruction will erase the entire memory array
to the logical "1". The ERAl cycle is identical to the
ERASE cycle exceptforthe different opcode. The ERAl
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit (x8
organization) output string. The output data bits will
toggle on the rising edge of the ClK and are stable after
the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will
automatically cycle to the next register and output sequentially.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TCSL).
ERASE/WRITE ENABLE AND
DISABLE
The ERAl cycle takes 15 ms max.
WRITE ALL
The93C66 powers up inthe EraselWrite Disable (EWDS)
state. All programming modes must be preceded by an
EraselWrite Enable (EWEN) instruction. Once the EWEN
instruction is executed, programming remains enabled
until an EWDS instruction is executed or Vcc is removed
from the device. To protect against accidental data
changes, the EWDS instruction can be used to disable
all EraselWrite functions and should follow all programming operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
The WRAl instruction will write the entire memory array
with the data specified in the command. The WRAl
cycle is comnpletely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode. The WRAl command does not include an
automatic ERASE cycle for the device. Therefore, the
WRAl instruction must be preceded by an ERAl instruction and the chip must be in the EWEN status in
both cases.
ERASE
The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TCSL).
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 100 ns
low (TCSL). DO at logical "0" indicates that programming
is still in progress. DO at logical "1" indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
PIN DESCRIPTION
The WRAl cycle takes 15 ms max.
Chip Select (CS)
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle, the
device will go into standby mode as soon as the programming cycle is completed.
The ERASE cycle takes 1 ms per byte max.
WRITE
The WRITE instruction is followed by 16 bits (or by 8 bits)
of data which are written into the specified address.
After the last data bit is put on the DI pin, CS must be
brought low before the next rising edge of the ClK clock.
This falling edge of CS initiates the self-timed auto-erase
and programming cycle.
CS must be lOW for 100 ns minimum (TCSL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.
DS11158E-4
© 1992 Microchip Technology Inc.
3-124
93C66
Serial Clock (ClK)
Data In (01)
The Serial Clock is used to synchronize the communication between a master device and the 93C66. Opcode,
address, and data bits are clocked in on the positive
edge of ClK. Data bits are also clocked out on the
positive edge of ClK.
Data In is used to clock in a START bit, opcode, address,
and data synchronously with the ClK input.
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (TPD after the positive
edge of ClK).
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime with respectto clock HIGH time (TCKH) and clock
lOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought
HIGH after being lOW for minimum chip select lOW
time (TCSL) and an ERASE or WRITE operation has
been initiated.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status (i.e., waiting for
START condition).
Organization (ORG)
When ORG is connected to Vcc, the (x16) memory organization is selected. When ORG is tied to Vss, the (x8)
memory organization is selected. When ORG is left
floating, an internal pullup device will select the device in
(x16) organization.
ClKcycies are not required during the self-timed WRITE
(i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively lOW to HIGH transitions of
ClK) must be provided. These clock cycles are required
to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set
truth table). ClK and DI then become don't care inputs
waiting for a new start condition to be detected.
Test
This pin is used for test mode only. It is recommended
to connect to Vcc or Vss for normal operation.
Note: CS must go lOW between consecutive instructions.
TIMING DIAGRAMS
SYNCHRONOUS DATA TIMING
V,H
cs
Tess
VIL
TeKH
TeKL
V,H
ClK
V,L - - - - - - - j
V,H
01
VIL
DO
(READ)
DO
(PROGRAM)
---"1'-------1----' 1 " - - - - - - - ' ' - - - - - t - - - - f ' - - - - - - - t - - -
VOH - - - - - 1 - - - - -___
VOL
VOH _ _ _ _
VOL
~~-------~~~~~---------~
© 1992 Microchip Technology Inc.
DS11158E-5
3-125
93C66
TIMING DIAGRAMS (Cont.)
READ
\J-
-.I
cs
DJ
DO - - - -TRI-STATE
---------,
\
~*>GXf->GG)(i>0
Dx
•••
DO
Dx'
•••
DO
Dx·
DO
-
-
r-
• The memory automatically cycles to the next register.
EWEN
~
cs
~--:~/-1--1~=X_X_\-,,----_ _ _ _ _ __
OJ
EWDS
cs
ClK
OJ
WRITE
cs
ClK
~
JUlSU-LILlLnJlj1J1JULflJlIL
~~~O
/~=:=>G\--,,-----
0L_--------
-.I
L
~
~r-LILJlJlIlJlJlJ-~
OJ~~~~_OO-:-\~
_ _ _ _ _ _ __
OO _ _~TA~J.~ST~A~TE~_ _ _ _ _~~~_ _ _ _~_~_--,
© 1992 Microchip Technology Inc.
DS11158E-6
3-126
93C66
TIMING DIAGRAMS (Cont.)
I
WRAL
CS
ClK
~
,
~
5LruLIlJ1J1JlfUUlJLflIl-[LrL
r\'-o_____,-<-J--;_xx:x~)(J<$~----
01 _ _
OO ______T_R_I~_ST_A_TE_______________________Q~>----------~\----~--__, BUSY~
"------I
I(x16) I(x8) I
TEe
LDxJ D15l D7J
ERASE
TCSL
CS
~
01
oo--------------------------------~~------~~--~
ERAL
TCSL
CS
~
OO ___T~R~I~S~T~A~TE~______________________,~--------~+_--~l
DS11158E-7
© 1992 Microchip Technology Inc.
3-127
93C66
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
PACKAGE:
I
TEMPERATURE
RANGE:
I
DEVICE:
P
SN
SM
Blank
I
E
93C66
93C66T
DS11158E-8
PLASTIC DIP
PLASTIC SOIC (0.150 mil Body)
PLASTIC SOIC (0.207 mil Body)
0' C to +70' C
·40' C to +85' C
·40' C to + 125' C
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM (in Tape and Reel Form)
© 1992 Microchip Technology Inc.
3-128
~.
93LC46/56/66
Microchip
CMOS Serial Electrically Erasable PROM
FEATURES
DESCRIPTION
• Single supply with programming operation down to
2.0 volts
• Low power CMOS technology
1 mA active current typical
5 ~A standby current (typical) at 3.0 V
ORG pin selectable memory configuration
128x8 or 64x16 bit organization (93LC46)
256x8 or 128x16 bit organization (93LC56)
512 x 8 or 256 x 16 bit organization (93LC66)
Self-timed ERASE and WRITE cycles
(including auto-erase)
Automatic ERAL before WRAL
Power on/off data protection circuitry
Industry standard 3-wire serial 110
Device status signal during ERASE/WRITE cycles
Sequential READ function
1,000,000 ERASEIWRITE cycles (typical)
Data retention> 40 years
8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
Available for extended temperature ranges:
Commercial:
OT to +70'C
Industrial:
-40'C to +85'C
Automotive: -40'C to +125'C (93LC56/66)
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. The 93LC Series is
available in standard 8-pin DIP and 8/14-pin surface
mount SOIC packages. The 93LC46X!56X/66Xare
offered in "SN" package only.
BLOCK DIAGRAM
Vee
vss
DO
PIN CONFIGURATION
NC
NC
SO Packages
DIP Package
cs
"0'" "0'" ""0°"°
CLK2
7NU
Vee
ClK
NU
NC
NC
elK
2
7
NU
Vee
2
7
Vss
DI
DI
3
6
ORG
DI
3
6
ORG
CS
3
6
DO
00
Vss
DO
4
5
Vss
DO
4
5
Vss
NC
NC
93LC46
93LC56
93LC66
CLK4
93LC46
93LC56
93LC66
5DI
93LC46X
93LC56X
93LC66X
© 1992 Microchip Technology Inc.
ORG
93LC56
93LC66
DS11168C-1
3-129
93 LC46/S6/66
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings*
All inputs and outputs w.r.t. Vss ............ -0.3V to +7.0V
Storage temperature ....................... -65'C to +150'C
Ambient temp. with power applied ..... -65"C to +125'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins ..................................... 4 kV
High level input voltage
low level input voltage
low level output voltage
High level output voltage
Input leakage current
Output leakage current
Internal capacitance
Function
CS
ClK
01
DO
Vss
ORG
NU
Vcc
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
Power Supply
Vee = +2.0V to +6.0V
Commercial
Industrial
DC AND AC ELECTRICAL
CHARACTERISTICS
Parameter
Name
Symbol
Min
VIH
0.7 Vce
Units
Max
Standby current
Clock frequency
Conditions
VIL
0.3 Vce
V
VOL1
0.4
V
IOL = 2.1 mA; Vec = 4.5V
VOL2
0.2
V
IOL =10 j.lA
IOH = -400 j.lA
VOHl
2.4
V
VOH2
Vcc-0.2
V
IOH = -10 j.lA
III
-10
10
j.lA
VIN = O.IV to Vcc
ILO
-10
10
j.lA
VOUT = 0.1 V to Vcc
7
pF
VIN!VOUT = 0 V (Note 1 & 3)
CINT
Tamb = +25'C, FCLK = 1 MHz
Icco
Iccs
1
mA
500
j.lA
FCLK = 1 MHz; Vcc = 3.0V
100
j.lA
ClK = CS = OV; Vcc = 5.5V
j.lA
ClK = CS = OV; Vcc = 3.0V
30
Endurance
Tamb = O"C to +70'C
Tamb = -40"C to +85"C
V
(all inputs/outputs)
Operating current (read mode)
(C):
(I) :
-
Em Cycles
100,000
FCLK
FCLK = 2 MHz; Vcc = 6.0V
2
MHz
1
MHz
Vcc>4.5V
Vcc<4.5V
TCKH
250
ns
Clock low time
TCKL
250
ns
Chip select setup time
Tcss
50
ns
Relative to ClK
Chip select hold time
TCSH
0
ns
Relative to ClK
Chip select low time
TCSL
250
ns
Data input setup time
TOls
100
ns
Relative to ClK
Data input hold time
TOIH
100
ns
Relative to ClK
Data output delay time
Tpo
400
ns
CL = 100 pF
Data output disable time
Tcz
100
ns
CL = 100 pF (Note 3)
Status valid time
Tsv
500
ns
CL = 100 pF
Program cycle time
Twc
TEC
TWL
10
ms
20
40
ms
ERASE/WRITE mode (Note 2)
ERAl mode
ms
WRAl mode
Clock high time
Note 1: This parameter is tested at Tamb = 25'C and FCLK = 1 MHz.
Note 2: Typical program cycle time is 4 ms per word.
Note 3: This parameter is periodically sampled and not 100% tested.
DS11168C-2
©
3-130
1992 Microchip Technology Inc.
93 LC46/S6/66
INSTRUCTION SET FOR 93LC46: ORG = 1 (x 16 organization)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
58
Opcode
Address
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A5 A4 A3 A2 A 1 AO
1 1 X X X X
A5A4A3A2A1 AO
1 o X X X X
A5 A4 A3 A2 A 1 AO
o 1 X X X X
OOXXXX
Data In
Data Out
Req. ClK Cycles
25
-
D15 - DO
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Data In
Data Out
Req. ClK Cycles
D7 - DO
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
18
10
10
10
18
18
10
-
D15 - DO
D15 - DO
9
9
9
25
25
9
INSTRUCTION SET FOR 93LC46: ORG = 0 (x 8 organization)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
58
Opcode
Address
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A6 A5 A4 A3 A2 A 1 AO
1 1 X X X X X
A6A5A4A3A2A1 AO
1
X X X X X
A6A5 A4A3 A2 A1 AO
0 1 X X X X X
0 X X X X X
-
-
o
D7 - DO
D7 - DO
o
-
INSTRUCTION SET FOR 93LC56: ORG = 1 (x 16 organization)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
58
Opcode
Address
Data In
Data Out
Reg. ClK Cycles
1
1
1
1
1
1
1
10
00
11
00
01
00
00
XA6A5A4A3A2A1 AO
1 1 X X X X X X
X A6 A5 A4 A3 A2 A1 AO
1
X X X X X X
X A6 A5 A4 A3 A2 A1 AO
1 X X X X X X
OOXXXXXX
-
D15 - DO
High-Z
(RDY/BSY)
JRDY/BSYj
(RDY/BSY)
(RDY/BSY)
High-Z
27
11
11
11
27
27
11
Data Out
Req. ClK Cycles
D7 - DO
High-Z
(RDY/BSY)
{RDY/BSYj
(RDY/BSY)
(RDY/BSY)
High-Z
20
12
12
12
20
20
12
o
D15 - DO
D15 - DO
o
-
INSTRUCTION SET FOR 93LC56: ORG = 0 (x 8 organization)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
58
Opcode
1
1
1
1
1
1
1
10
00
11
00
01
00
00
Address
X A7 A6
1 1 X
XA7 A6
1 o X
X A7 A6
o 1 X
o 0 X
A5
X
A5
X
A5
X
X
A4
X
A4
X
A4
X
X
A3
X
A3
X
A3
X
X
Data In
A2 A1
X X
A2A1
X X
A2 A1
X X
X X
AO
X
AO
X
AO
X
X
-
D7 - DO
D7 - DO
-
INSTRUCTION SET FOR 93LC66: ORG = 1 (x 16 organization)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
58
Opcode
Address
Data In
Data Out
Req. ClK Cycles
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A7 - AO
11XXXXXX
A7 - AO
10XXXXXX
A7 - AO
01XXXXXX
OOXXXXXX
-
D15 - DO
High-Z
(RDY/BSY)
(RDY/SSY)
(RDY/BSY)
(RDY/SSY)
High-Z
27
11
11
11
27
27
11
INSTRUCTION SET FOR 93LC66: ORG
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
D15 - DO
D15 - DO
-
=0 (x 8 organization)
58
Opcode
Address
Data In
Data Out
Req. ClK Cycles
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A8-AO
11XXXXXXX
AS- AO
10XXXXXXX
A8-AO
01XXXXXXX
OOXXXXXXX
-
D7 - DO
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
20
12
12
12
20
20
12
D7 - DO
D7 - DO
-
© 1992 Microchip Technology Inc.
DS11168C-3
3-131
93 LC46/S6/66
FUNCTIONAL DESCRIPTION
READ
When the ORG pin is connected to Vee, the (x16)
organization is selected. When it is connected to ground,
the (x8) organization is selected. Instructions, addresses and write data are clocked into the 01 pin on the
rising edge of the clock (ClK). The DO pin is normally
held in a high-Z state except when reading data from the
device, or when checking the ready/busy status during
a programming operation. The ready/busy status can
be verified during an Erase/Write operation by polling
the DO pin; DO low indicates that programming is still in
progress, while DO high indicates the device is ready.
The DO will enter the high-Z state on the falling edge of
the CS.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit (x8
organization) output string. The output data bits will
toggle on the riSing edge of the ClK and are stable after
the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will
automatically cycle to the next register and output sequentially.
ERASE/WRITE ENABLE AND
DISABLE
The 93lC46/56/66 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or Vee is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all EraselWrite functions and should
follow all programming operations. Execution of a
READ instruction is independent of both the EWEN and
EWDS instructions.
START Condition
The START bit is detected by the device if CS and 01 are
both HIGH with respect to the positive edge of ClK for
the first time.
Before a START condition is detected, CS, ClK, and 01
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAl,
and WRAl). As soon as CS is HIGH, the device is no
longer in the standby mode.
ERASE
An instruction following a START condition will only be
executed ifthe required amount of opcode, address and
data bits for any particular instruction is clocked in.
The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
Afterexecution of an instruction (i.e., clock in or out olthe
last required address or data bit) ClK and 01 become
don't care bits until a new start condition is detected.
The DO pin indicates the READY/BUSY status of the
DilDO
device if CS is brought high after a minimum of 250 ns
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero" that
precedes the READ operation, if AO is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
AO. The higher the current sourcing capability of AO, the
higher the voltage at the Data Out pin.
The ERASE cycle takes 4 ms per word.
low (TesL). DO at logical "0" indicates that programming
is still in progress. DO at logical "1" indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
WRITE
The WRITE instruction is followed by 16 bits (orby 8 bits)
of data which are written into the specified address.
After the last data bit is put on the 01 pin, CS must be
brought low before the next rising edge olthe ClK clock.
This falling edge of CS initiates the self-timed auto-erase
and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TesL). DO at logical "0" indicates that programming
is still in progress. DO at logical "1" indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Data Protection
During power-up, all programming modes of operation
are inhibited until Vee has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when Vee
has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional protection against accidentally programming during normal
operation.
After power-up, the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be
executed.
The WRITE cycle takes 4 ms per word.
DS11168C-4
© 1992 Microchip Technology Inc.
3-132
93 LC46/S6/66
ERASE ALL
The ERAl instruction will erase the entire memory array
to the logical "1" state. The ERAl cycle is identical to the
ERASE cycle except for the different opcode. The ERAl
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode. The ERALinstruction is guaranteed atVcc; +4.5V
to +6.0V.
ClK can be stopped anywhere in the transmission
sequence (at HIGH or lOW level) and can be continued
anytime with respectto clock HIGH time (TCKH) and clock
lOW time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
ClK is a "Don't Care" if CS is lOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received by
the device without changing its status (i.e., waiting for
START condition).
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns low
(TCSL).
The ERAl cycle takes 20 ms max (8 ms typical).
ClK cycles are not required during the self-timed WRITE
(i.e., auto ERASEIWRITE) cycle.
WRITE ALL
After detection of a start condition the specified number
of clock cycles (respectively lOW to H IG H transitions of
ClK) must be provided. These clock cycles are required
to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set
truth table). ClK and DI then become don't care inputs
waiting for a new start condition to be detected.
The WRAl instruction will write the entire memory array
with the data specified in the command. The WRAl
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the ClK pin is not
necessary after the device has entered the self clocking
mode. The WRAl command does include an automatic
ERAl cycle forthe device. Therefore, the WRAl instruction does not require an ERAl instruction but the chip
must be in the EWEN status. The WRAl instruction is
guaranteed at Vcc ; +4.5V to +6.0V.
Note: CS must go lOW between consecutive instructions.
Data In (01)
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns low
(TCSL).
Data In is used to clock in a START bit, opcode, address,
and data synchronously with the ClK input.
The WRAl cycle takes 40 ms max (16 ms typical).
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the ClK input (TPD after the positive
edge of ClK).
PIN DESCRIPTION
Chip Select (CS)
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought
HIGH after being lOW for minimum chip select lOW
time (TCSL) and an ERASE or WRITE operation has
been initiated.
A HIGH level selects the device. A lOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought lOW during a program cycle, the
device will go into standby mode as soon as the programming cycle is completed.
Organization (ORG)
CS must be lOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is lOW, the internal
control logic is held in a RESET status.
93lC46/S6/66:
When ORG is connected to Vee or floated, the (x16)
memory organization is selected. When ORG is tied to
VSS, the (x8) memory organization is selected. ORG
can only be floated for clock speeds of 1 MHZ or less.
Serial Clock (ClK)
The Serial Clock is used to synchronize the communication between a master device and the 93lCX66. Opcode,
address, and data bits are clocked in on the positive edge
of ClK. Data bits are also clocked out on the positive
edge of ClK.
© 1992 Microchip Technology Inc.
DS11168C·5
3-133
93LC46/56/66
TIMING DIAGRAMS
SYNCHRONOUS DATA TIMING
V,H
CS
V,l
Tcss
TCKH
TCKl
V,H
ClK
V,l
V,H
01
V,l
DO
VOH
(READ) Val
DO VOH
(PROGRAM)
Val
The memory automatically cycles to the next register.
READ
cs
------.I
DO)G)$-
DO _ _ _---'-T"'RI"'-ST-'-'A'-'-TE=---_ _ _ _ _---..
EWEN
cs~
ClK
DI
EWDS
cs~
WlSUUlS1JUL
ClK
DI
~~~o _ _0---L-I-xx=::=><._!\\-'---_ __
DS11168C-6
© 1992 Microchip Technology Inc_
3-134
93LC46/56/66
TIMING DIAGRAMS (Cont.)
WRITE
I
es _____
elK
,
r---------------~--------~~
~LJLJLJlJLiLlLIl1lJ1IlJUlJl~
DI _ _
;,-~X_~:_\-'-----------
DO _ _ _ _ _-'-T'-"RI,,-S'-'-TA'-'-T'-'E~_ _ ___;5_-----_ll_--:__-~~~-
'..
~~I
Twe
,
WRAL
~
,
DO _ _ _ _ _~TR~I~-S~TA~T~E~_ _ _ _ _ _ _ _~-----~~-~,---\~
Guarantee at Vee;;:: +4.5V to +6.0V
ERASE
:...
T~
TCSL
CHECK 8T ATUS
elK
STANDBY
SJLrU1ILiLnJLflJ;-
01
DO __T~R~I-S~T~A~TE~_ _ _ _ _ _ _ _ _ _ _-'S~
__
--;5-~_,l
...
ERAL
es
elK
01
----.I
JlJlJlJLJlJLJLr1JlJl
~_o____o_
DO __T~R~I-~ST~A~TE~_____________________~_______--;5-+-__~
Guarantee at Vee: +4.5V to +6.0V
© 1992 Microchip Technology Inc.
DS11168C-7
3-135
93LC46/S6/66
SALES AND SUPPORT
To order or to obtain information, e,g" on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices,
PART NUMBERS
PACKAGE:
I
TEMPERATURE
RANGE:
P
SN
SM
SL
Blank
I
E
PLASTIC
PLASTIC
PLASTIC
PLASTIC
DIP
SOIC (150 mil Body) 8-Lead
SOIC (207 mil Body) 8-Lead
SOIC (150 mil Body) 14-Lead (93LC56f66)
0- Cto+70- C
-40- C to +85" C
-40" C to +85" C
Configuration
DEVICE TYPE:
CMOS Serial EEPROM
CMOS Serial EEPROM
in alternate pinouts (SN package only)
CMOS Serial EEPROM (in Tape & Reel)
CMOS Serial EEPROM in Tape & Reel
DS11168C-8
(x16) or (x8)
93LC46f56f66
93LC46Xf56Xf66X
93LC46Tf56Tf66T
93LC46XTf56XTf66XT
© 1992 Microchip Technology Inc,
3-136
93LCS56
Microchip
Product Brief
2K CMOS Serial Electrically Erasable PROM
FEATURES
•
•
•
•
•
DESCRIPTION
The Microchip Technology Inc. 93LCS56 is a 2048 bit
low voltage serial Electrically Erasable PROM. The 2K
bit memory is configured as 128 x 16 bits. A write protect
register is included in order to provide a user defined
region of write protected memory. All memory locations
greater than or equal to the address placed in the write
protect register will be protected from any attempted
write or erase operation. It is also possible to protect the
address in the write protect register permanently by
using a one time only instruction (PROS). Any attempt
to alter data in a register whose address is equal to or
greater than the address stored in the protect register
will be aborted. Advanced CMOS technology makes
this device ideal for low power non-volatile memory
applications.
Single supply with programming operation down
to 2.5 volts
Low power CMOS technology
2 mA active current
100 I1A standby current at 5.5 V
- 30 I1A standby current at 3.0 V
Organized as 128 x 16 bits
Software write protection of user defined
memory space
Self timed erase and write cycles
Automatic ERAL before WRAL
Power on/off data protection
Industry standard 3-wire serial I/O
Device status signal during EIW
Sequential READ function
1,000,000 EIW cycles (typical)
Data retention> 40 years
8-pin PDIP/SOIC and 14-pin SOIC packages
Commercial:
O'C to +70'C
Industrial:
40'C to +85'C
BLOCK DIAGRAM
Vee
Vss
DO
PIN CONFIGURATION
SO Packages
DIP Package
"0« "0'"
eLK
2
7
PRE
01
3
6
PE
D04
5Vss
eLK
2
7
DI3
DO
4
1
2
NC
elK
NC
c::
c:::
3
4
DlC:::S
14j-:JNC
13P
12P
l1PNC
Vee
PRE
10~PE
6PE
DO
c::
6
9~VSS
5
NC
c:
7
8~NC
© 1992 Microchip Technology Inc.
3-137
PRE
c...
cs~
Vss
DS20063A-1
93LCS56
Product Brief
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
Name
Function
CS
ClK
DI
DO
Vss
PE
PRE
Vcc
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Protect Register Enable
Power Supply
All inputs and outputs w.r.t. Vss ...... -0.3V to Vcc +0.3V
Storage temperature ....................... -6S'C to + 1S0'C
Ambient temp. with power applied ..... -6S'C to + 12S'C
Soldering temperature of leads (10 seconds) .. +300'C
ESD protection on all pins .................................... .4 kV
'Notice: Stresses above those listec under "Maximum ratings" may'
cause permanent damage to the device. This is a stress rating only ana
functional operation of Hie device at those or any other conditions above
those indicatec in the operational listings of lhis specification is not
~f~i~~ea1eov~~~er~~i~TI~~~um rating conditions for extended periods
Vcc : +2.S V to + S.S
Commercial
(C): Tamb: O'C to +70'C
Industrial
(I) : Tamb : -40'C to +8S'C
(Note 2) Automotive (E): Tamb: -40'C to +12S'C
DC AND AC ELECTRICAL
CHARACTERISTICS
Symbol
Min
High level input voltage
VIH
0.7 Vcc
low level input voltage
VIL
Parameter
low level output voltage
VOL
High level output voltage
VOH
0.7 Vcc
III
-10
ILo
-10
Input leakage current
Output leakage current
Internal capacitance
Max
Units
0.3 Vcc
V
V
0.4
CINT
V
Standby current
IOL: 2.1 mA; Vcc: 2.0 V
V
IOH: -400 j.!A S.S V
10
j.!A
VIN:0.1 VtoS.SV
10
j.!A
VOUT: 0.1 V to S.S V
7
pF
V,NNoUT: 0 V; Note 1
Tamb : +2S'C, FCLK : 1 MHz
(all inputs/outputs)
Operating current (read mode)
Conditions
Iceo
lecs
2
mA
FeLK : 2 MHz; Vee: S.S V
1
j.!A
j.!A
FeLK: 1 MHz; Vcc : 3.0 V
100
30
CS : ClK : 0 V; Vee: S.S V
CS : ClK : 0 V; Vce : 3.0 V
TeKH
SOO
Clock low time
TCKL
SOD
Chip select setup time
Tcss
SO
Chip select hold time
TesH
0
j.!A
MHz
MHz
ns
ns
ns
ns
Chip select low time
TesL
2SO
ns
PRE setup time
TPRES
100
ns
PE setup time
TPES
100
ns
Relative to ClK
PRE hold time
TPREH
0
ns
Relative to ClK
Relative to ClK
Clock frequency
FCLK
2
1
Clock high time
Vce > 4.SV
Vce < 4.SV
Relative to ClK
Relative to ClK
Relative to ClK
PE hold time
TPEH
SOD
ns
Data input setup time
TDIS
100
ns
Relative to ClK
Data input hold time
TDIH
100
ns
Relative to ClK
Data output delay time
TPD
SOO
ns
CL = 100 pF
Data output disable time
Tez
100
ns
CL = 100 pF
Status valid time
Tsv
SOD
ns
CL = 100 pF
Program cycle time
Twc
10
ms
ERASE/WRITE mode (Note 3)
TEC
20
ms
ERAlmode
TWL
40
ms
WRAl mode
Note 1:
Note 2:
Note 3:
This parameter is tested at Tamb = 25'C and FCLK = 1 MHz. It is periodically sampled and not 100% tested.
Endurance at temperature ~veater than 85'C is rated at 10,000 erase/write cycles (minimum).
Typical program cycle time IS 2 ms per word.
DS20063A-2
© 1992 Microchip Technology Inc.
3-138
93LCS66
Microchip
Product Brief
4K CMOS Serial Electrically Erasable PROM
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Single supply with programming operation down
to 2.0 volts
Low power CMOS technology
2 mA active current
tOO flA standby current at 5.5 V
- 30 flA standby current at 3.0 V
Organized as 256 x 16 bits
Software write protection of user defined
memory space
Self timed erase and write cycles
Automatic ERAL before WRAL
Power on/off data protection
Industry standard 3-wire serial I/O
Device status signal during EIW
Sequential READ function
1,000,000 EIW cycles (typical)
Data retention> 40 years
8-pin PDIP/SOIC and 14-pin SOIC packages
Commercial:
O'C to 70'C
Industrial:
-40'C to 85'C
The Microchip Technology Inc. 93LCS66 is a 4096 bit
low voltage serial Electrically Erasable PROM. The 4K
bit memory is configured as 256 x 16 bits. A write protect
register is included in order to provide a user defined
region of write protected memory. All memory locations
greater than or equal to the address placed in the write
protect register will be protected from any attempted
write or erase operation. It is also possible to protect the
address in the write protect register permanently by
using a one time only instruction (PROS). Any attempt
to alter data in a register whose address is equal to or
greater than the address stored in the protect register
will be aborted. Advanced CMOS technology makes
this device ideal for low power non-volatile memory
applications.
BLOCK DIAGRAM
Vee
Vss
DO
eLK
PIN CONFIGURATION
SO Packages
DIP Package
~o·" ~o·"
elK
2
7
PRE
Ne
Ne
es
Vee
eLK
PRE
Ne
Ne
eLK
2
7
PRE
DI
PE
DI3
6PE
DI
3
6
PE
DO
Vss
D04
5Vs$
DO
4
5
Vss
Ne
NC
© 1992 Microchip Technology Inc.
3-139
DS20064A-1
93LCS66
Product Brief
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
All inputs and outputs w.r.t. Vss ..... ·0.3 V to Vee +0.3V
Storage temperature ....................... ·65·C to + 150·C
Ambient temp. with power applied ..... ·65·C to + 125·C
Soldering temperature of leads (10 seconds) .. +300·C
ESD protection on all pins ..................................... 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may'
cause permanent damage to the device. This is a stress rating only ana
functional operation of me device at those or any other conditions above
those indicated in the operational listings of lhis specification is not
~f:i~~t'ea~~v~~~er~~e%TI~~~um rating conditions for extended periods
Symbol
Min
High level input voltage
VIH
0.7 Vee
low level input voltage
VIL
0.3 Vee
V
0.4
V
VOL
0.7 Vee
III
·10
10
ILO
·10
10
CINT
V
7
IlA
IlA
pF
Standby current
Clock frequency
Conditions
IOL=2.1 mA;Vee=2.0V
IOH = ·400 IlA
VIN = 0.1 V to Vce
VOUT = 0.1 V to Vee
VINNoUT = 0 V; Note 1
Tamb = +25·C, FeLK = 1 MHz
(all inputs/outputs)
Operating current (read mode)
V (93lCS66)
(C): Tamb= OT to +70·C
(I): Tamb = AO·C to +85·C
(E): Tamb = ·40·C to + 125·C
V
VOH
Internal capacitance
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Protect Register Enable
Power Supply
Units
low level output voltage
Output leakage current
CS
ClK
DI
DO
VSS
PE
PRE
Vee
Max
High level output voltage
Input leakage current
Function
Vee = +2.5 V to +5.5
Commercial
Industrial
(Note 2) Automotive
DC AND AC ELECTRICAL
CHARACTERISTICS
Parameter
Name
leeo
Ices
FeLK
2
mA
1
FeLK = 2 MHz; Vee = 5.5 V
IlA
FeLK = 1 MHz; Vee = 3.0 V
100
IlA
CS = ClK = 0 V; Vee = 6.0 V
30
IlA
MHz
CS = ClK = 0 V; Vee = 3.0 V
2
1
MHz
Vee < 4.5V
Vee> 4.5V
Clock high time
TeKH
500
ns
Clock low time
TeKL
500
ns
Chip select setup time
Tess
50
ns
Relative to ClK
Chip select hold time
TesH
0
ns
Relative to ClK
Chip select low time
TesL
250
ns
PRE setup time
TPRES
100
ns
Relative to ClK
PE setup time
TPES
100
ns
Relative to ClK
PRE hold time
TPREH
0
ns
Relative to ClK
PE hold time
TPEH
500
ns
Relative to ClK
Data input setup time
To IS
100
ns
Relative to ClK
Data input hold time
TOIH
Tpo
100
ns
Relative to ClK
500
ns
CL = 100 pF
Data output delay time
Data output disable time
Tez
100
ns
CL = 100 pF
Status valid time
Tsv
500
ns
CL = 100 pF
Program cycle time
Twe
10
ms
ERASE/WRITE mode (Note 3)
TEe
15
ms
ERAl mode
TWL
30
ms
WRAl mode
Note 1: This parameter is tested at Tamb = 25·C and FCLK = 1 MHz. It is periodically sampled and not 100% tested.
Note 2: Endurance at temperature greater than 85·C is rated at 10,000 erase/write cycles (minimum).
Note 3: Typical program cycle time IS 2 ms per word.
DS20064A·2
/A~!V;©IITT(G(e ~ n~Q)~lm :r~~~(0)rJ
3·140
© 1992 Microchip Technology Inc.
Microchip
SECTION 4
EEPROM PRODUCT SPECIFICATIONS
28C04A
28C16A
28C17A
28C64A
4K (512 x 8) CMOS Electrically Erasable PROM ...................................... .4- 1
16K (2K x 8) CMOS Electrically Erasable PROM ...................................... .4- 9
16K (2K x 8) CMOS Electrically Erasable PROM ...................................... .4- 17
64K (8K x 8) CMOS Electrically Erasable PROM ...................................... .4- 25
© 1992 Microchip Technology Inc.
DS00018E
4-i
Microchip
© 1992 Microchip Technology
DS00018E
4-ii
~.
28C04A
Microchip
4K (512 X 8) CMOS Electrically Erasable PROM
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
Fast Read Access Time-1S0ns Maximum
CMOS Technology for Low Power Dissipation
-30mA Active
-100IlA Standby
Fast Byte Write Time-200lls or 1ms
Data Retention> 10 years
High Endurance 10' Erase/Write Cycles
Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
Data Polling
Chip Clear Operation
Enhanced Data Protection
-Vcc Detector
-Pulse Filter
-Write Inhibit
5-Volt-Only Operation
Organized 512x8 JEDEC standard pinout
-24 Pin Dual-In-Line Package
-32 Pin Chip Carrier (Lead less or Plastic)
Available for Extended Temperature Ranges:
-Commercial: 0' C to 70' C
-Industrial: -40' C to 85' C
-Automotive: -40' C to 125' C
The Microchip Technology Inc 28C04A is a CMOS 4K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C04A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when a write cycle is complete, the 28C04A
uses Data polling. Data polling allows the user to read
the location last written to when the write operation is
complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
PIN CONFIGURATION
BLOCK DIAGRAM
1/00 .. ••••• 1/07
Top View
vss_
Data Protection
Circuitry
Chip Enablel
Output Enable
Control Logic
Vcc_
CEOE_
WE_
Auto Erase/Write
Timing
~
Poll
Program Voltage
Generation
AO_
:::::
::::
I-
:-
.Pin 1 indicator on PLCC on top of package
A8-
-:-0 oee~der D
a
t l"e
h
e
s
l"-
I
Input/Output
Buffers
I
YGating
e---4Kbit
Cell Matrix
X
Decoder
e----
© 1990 Microchip Technology Inc.
4-1
D811126B-1
28C04A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
AO-A8
CE
OE
WE
1/00 -1/07
Vcc
Vss
NC
Address Inputs
Chip Enable
Output Enable
Write Enable
Data InputslOutputs
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed
NU
MAXIMUM RATINGS'
Vcc and input voltages W.r.t. Vss ........ -0.6V to + 6.25V
Voltage on OE W.r.t. Vss ........................... -0.6V to +13.5V
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65' C to 125' C
Ambient temp. with power applied ........ -50' C to 95' C
*Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
READ / WRITE OPERATION
DC Characteristics
Parameter
Input Voltages
Vcc = +5V ±1 0%
Commercial (C): Tamb= 0' C to 70' C
Industrial
(I): Tamb= -40' C to 85' C
Automotive (E):Tamb= -40' C to 125' C
Status
Symbol
Min
Max
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vcc+1
0.8
V
V
III
-10
10
/lA
VIN= -0.1V to Vcc+1
10
pF
VIN = OV; Tamb = 25' C;
f= 1 MHz
0.45
V
V
IOH= -400/lA
IOL= 2.1 mA
10
/lA
VOUT = -0.1 V to Vcc+0.1 V
CoUT
12
pF
VIN= OV; Tamb = 25' C;
f= 1 MHz
Icc
30
mA
f = 5 MHz (Note 1)
Input Leakage
CIN
Input Capacitance
Output Voltages
Logic "1"
Logic "0"
Output Leakage
Output Capacitance
Power Suppy Current, Active
TTL input
VOH
VOL
2.4
ILO
-10
Units Conditions
Vcc = 5.5V;
Power Supply Current, Standby
TTL input
TTL input
CMOS input
ICC(S)TTL
ICC(S)TTL
ICC(S)CMOS
2
3
100
mA
mA
J.lA
-
CE = VIH (0' C to 70' C)
CE = VIH (-40' C to 125' C)
CE = Vcc-0.3 to Vcc+1
Note: (1) AC power supply current above 5 MHz: 1 mA/MHz
DS111268-2
© 1990 Microchip Technology Inc.
4-2
28C04A
READ OPERATION
AC Characteristics
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
Parameter
Sym
VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O· Ct070· C
Industrial
(I): Tamb = -40· C to 85· C
Automotive (E): Tamb= -40· C to 125· C
2BC04A-15
2BC04A-20
2BC04A-25
Min
Min
Min
Max
Max
Units
Conditions
Max
Address to Output Delay
IACC
150
200
250
ns
OE =CE =VIL
CE to Output Delay
teE
150
200
250
ns
OE = VIL
OE to Output Delay
toE
70
80
100
ns
CE= VIL
CE or OE High to Output Float
toFF
0
70
ns
OU.!2!:Jt Hold from Address, CE
or OE, whichever occurs first.
toH
0
50
0
0
55
0
0
ns
READ WAVEFORMS
x
VIH
Address
VIL
VIH
~
~
Address Valid
~
~ I<-
CE
-,
VIL
VIH
~
VIL
VOH
VIH
--I--
I""
toE(2) --
\\\\\
IAcc
.
VI""-
- --,
IIIII
HighZ
VOL
WE
k?
teE(2)
OE
Data
lX
-- toFF(1,3) toH
Valid Output
\\\\ \
High Z
JIlI//
VIL
Notes: (1) toFFis specified forOE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
05111268-3
© 1990 Microchip Technology Inc.
4-3
28C04A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
BYTE WRITE
AC Characteristics
Parameter
VIH= 2.4V and VIL= O.4SV; VOH = 2.0V; VOL = 0.8V
1 TIL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0' C to 70' C
Industrial
(I): Tamb = -40' C to 85' C
Automotive (E): Tamb = -40' C to 125' C
Symbol
Min
lAs
10
ns
Address Hold Time
IAH
50
ns
Data Set-Up Time
IDs
50
ns
Address Set-Up Time
Max
Units Remarks
Data Hold Time
IDH
10
ns
Write Pulse Width
twPL
100
ns
Write Pulse High Time
twPH
50
ns
OE Hold Time
toEH
10
ns
OE Set-Up Time
toES
10
Data Valid Time
IDv
Write Cycle Time (28C04A)
Write Cycle Time (28C04AF)
Note 1
ns
1000
ns
Note 2
twe
1
ms
0.5 ms typical
twe
200
!!s
1OO!!S typical
Note: (1) A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, wichever occurs first.
(2) Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until
tDH after the positive edge of WE or CE, whichever occurs first.
PROGRAMMING
Waveforms
Address
V'"==>t- - - -I~.- - - - - -t-A-H- ~- - _: f<~~--------------~---------VIL
VIH
tAS
1~--------tWPL------~
CE,WE
VIL
Data In
VIH
VIL
tOES
VIH
OE
--
VIL
© 1990 Microchip Technology Inc.
DS11126B-4
4-4
28C04A
DATA POLLING
Waveforms
Address
VIH
=><
X
Address Valid
VIL
VIH
CE
VIL
Last Written
Address Valid
tCE
~
tWPH
VIH
WE
VIL
VIH
OE
VIL
VIH - - - - - f - , .
Data
True Data Out
VIL
CHIP CLEAR
Waveforms
VIH
CE
VIL
VH
OE
VIH
'\
/
/
'\
/
..
~
~
tw
VIH
WE
VIL
1\
/
© 1990 Microchip Technology Inc.
""
tw = 10ms
ts = tH = 1iJs
VH = 12.0V ±O.5V
DS11126B-5
4-5
28C04A
Write Mode
DEVICE OPERATION
The 28C04A has a write cycle similar to that of a Static
RAM. The write cycle is completeluelf-timed and
initiated by a 10.!'Uloing pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched.
The Microchip Technology Inc 28C04A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
-
CE
OE
L
H
H
X
X
X
X
X
L
H
L
L
-
WE
I/O
H
DouT
X
X
X
High
High
High
High
DIN
H
L
Data Polling
Z
Z
Z
Z
The 28C04A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion olthe write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.
Automatic Before Each "Write"
X = Any TTL level.
Read Mode
Optional Chip Clear
The 28C04A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.
All data~ay be cleared to 1's in a chiE..Qlear cl'9.le by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data.
Standby Mode
The 28C04A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the oUlQi!ts are in a high impedance state, independent
of the OE input.
Data Protection
In orderto ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vcc).
D811126B-6
© 1990 Microchip Technology Inc.
4-6
28C04A
NOTES:
DS11126B-7
© 1990 Microchip Technology Inc.
4-7
28C04A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
~C~AF
- 15 II P
'---
Package:
i
i
Temperature
Range:
Access Time:
I Option:
Device:
J
K
L
P
Blank
I
E
15
20
25
F
4K
DS11126B-8
Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
0' C to 70' C
-40' C to 85' C
-40' C to 125' C
150 nsec
200 nsec
250 nsec
=twc= 1ms
=twc= 200llS
(512 x 8) CMOS EEPROM
© 1990 Microchip Technology Inc.
4-8
~.
28C16A
Microchip
16K (2K X 8) CMOS Electrically Erasable PROM
FEATURES
DESCRIPTION
• Fast Read Access Time-150ns Maximum
• CMOS Technology for Low Power Dissipation
-30mA Active
-1 OO~A Standby
• Fast Byte Write Time--200~s or 1ms
• Data Retention> 10 years
• High Endurance 10' EraselWrite Cycles
• Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
• Data polling
• Chip Clear Operation
Enhanced Data Protection
-Vce Detector
-Pulse Filter
-Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
-24 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Leadless or Plastic)
• Available for Extended Temperature Ranges:
-Commercial: 0' C to 70' C
-Industrial: -40' C to 85' C
-Automotive: -40' C to 125' C
The Microchip Technology Inc 28C16A is a CMOS 16K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C16A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when a write cycle is complete, the 28C16A
uses Data polling. Data polling allows the user to read
the location last written to when the write operation is
complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
PIN CONFIGURATION
BLOCK DIAGRAM
1/00·······1/07
TOp View
Vss_
Vee_
Vee
A7
AS
AS
A9
WE
DE
A10
CE
1/07
1100
1/06
1101
1102
1/05
1/04
Vss ' -_ _ _F
DIP
1103
~~ :~rJl~Jl~J~il!llJl~Jl1iiJ!~ ~:
A4]]
A3 j ]
A2~]
A1 jjJj
AD jjj
NC j~J
1/00
j.aJ
Data Protection
Circuitry
CE_
<~~~~I~~
Ii?
:?§
NC
ri~
OE
ri~
CE
Output Enable
Control Logic
WE_
Auto EraselWrite
Timing
NC
Data
Poll
Program Voltage
Generation
rg~ MO
fii
iii
Chip Enablel
DE_
AO_
:::
:::
1t07
1/06
r::lr~lr:'lr8r~r"'r1;i
~§~~~~H~
I-
1-
PLCC/LCC
I-
t_
.Pin 1 indicator on PLCC on top of package
A~O : : :
~j De~der
a
t
e
s
-
j
YGating
-
-
h
e
D
I
Input/Output
Buffers
X
16K bit
Decoder
Cell Matrix
;---
© 1991 Microchip Technology Inc.
4-9
DSll125C-l
28C16A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Name \
Function
AO -A10
CE
OE
WE
1/00-1/07
Vcc
Vss
NC
Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
+SV Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed
NU
MAXIMUM RATINGS·
VCC and input voltages w.r.t. Vss ........ -0.6V to + 6.2SV
Voltage on OE w.r.t. Vss ........................... -0.6V to +13.SV
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.SV
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65" C to 125" C
Ambient temp. with power applied ........ ·50" C to 95" C
'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation olthe device atthose or any
other conditions above those indicated in the operation listings
ofthis specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
READ I WRITE OPERATION
DC Characteristics
Parameter
Input Voltages
Vcc = +SV ±1 0%
Commercial (C): Tamb= 0" Ct070" C
Industrial
(I): Tamb= -40" C to 85" C
Automotive (E):Tamb= -40" Cto 125" C
Status
Symbol
Min
Max
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vcc+1
0.8
V
V
III
-10
10
IlA
VIN= -0.1V to Vcc+1
10
pF
VIN = OV; Tamb = 25" C;
f= 1 MHz
0.45
V
V
IOH = -4001lA
IOL=2.1mA
10
IlA
VOUT = -0.1 V to Vcc+O.1V
GoUT
12
pF
VIN = OV; Tamb = 25" C;
f= 1 MHz
TIL input
Icc
30
rnA
f = 5 MHz (Note 1)
Vcc = S.SV;
TIL input
TTL input
CMOS input
ICC(S)TIL
Icc(s)TIL
ICC(S)CMOS
2
3
100
rnA
rnA
CE = VIH (0" C to 70" C)
CE = VIH (-40· C to 125" C)
CE = Vcc-0.3 to Vcc+ 1
Input Leakage
CIN
Input Capacitance
Output Voltages
Logic "1"
Logic "0"
Output Leakage
Output Capacitance
Power Suppy Current, Active
Power Supply Current, Standby
VOH
VOL
2.4
ILo
-10
Units Conditions
IlA
Note: (1) AC power supply current above 5 MHz: 1 rnA/MHz
© 1991 Microchip Technology Inc.
DS11125C-2
4-10
28C16A
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Parameter
Sym
VIH; 2.4V; VIL; 0.45V; VOH;
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb; 0"
(I): Tamb; _40"
Industrial
Automotive (E): Tamb; _40"
28C16A-15
28C16A-20
28C16A-25
Min
Min
Min
Max
Max
2.0V; VOL; O.SV
C to 70" C
C to 85" C
C to 125" C
Units
Conditions
Max
lAee
150
200
250
ns
OE; CE; VIL
CE to Output Delay
tCE
150
200
250
ns
OE; VIL
OE to Output Delay
tOE
70
SO
100
ns
CE; VIL
CE or OE High to Output Float
tOFF
0
70
ns
Ol!!Q!Jt Hold from Address, CE
or OE, whichever occurs first.
tOH
0
Address to Output Delay
-
50
0
55
0
0
0
ns
READ WAVEFORMS
VIH
X
Address
VIL
VIH
r-
':"
CE
~
Address Valid
k:---
--:;;
VIL
tK
V
t"
tCE(2)
VIH
~ I;:-
OE
VIL
VOH
Data
I--
tOE(2) ---
IIIII
\\\\\
High Z
VOL
VIH
--:;;
lAce
.
~
Vr--- tOFF(1.3) toH
~
Valid Output
\1\\\ \
High Z
III11/
WE
VIL
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on teE
(3) This parameter is sampled and is not 100% tested
© 1991 Microchip Technology Inc.
DS11125C-3
4-11
28C16A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
BYTE WRITE
AC Characteristics
Parameter
VIH = 2.4V and VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0" C to 70" C
Industrial
(I): Tamb = -40" C to 85" C
Automotive (E): Tamb = -40" C to 125" C
Symbol
Min
Address Set-Up Time
tAS
10
Address Hold Time
tAH
50
ns
Data Set-Up Time
tos
50
ns
Data Hold Time
Max
Units Remarks
ns
tOH
10
ns
Write Pulse Width
tWPL
100
ns
Write Pulse High Time
tWPH
50
ns
OE Hold Time
tOEH
10
ns
tOES
10
ns
-
OE Set-Up Time
Note 1
Data Valid Time
tov
1000
ns
Note 2
Write Cycle Time (28C16A)
twe
1
ms
0.5 ms typical
twe
200
~s
1OO~s typical
Write Cycle Time (28C16AF)
-
-
Note: (1) A write cycle can be initiated by CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
(2) Data must be valid within 1000ns max. after. a write cycle is initiated and must be stable at least until
tOH after the positive edge of WE or CE, whichever occurs first.
PROGRAMMING
Waveforms
Address
v'"
VIL
VIH
=1
tAS
CE,WE
VIL
VIH
Data In
VIL
tOES
...-
VIH
OE
VIL
© 1991 Microchip Technology Inc.
DS11125C-4
4-12
28C16A
DATA POLLING
Waveforms
Address
VIH
=><
Address Valid
VIL
CE
X
.
f'-_f _ _ _~
~._ _ _ _-'.
Last Written
Address Valid
tACC - -
VIH~
VIL
_
-"-"--"
__ _ _ _ _ _-"""--"""-.L-L......'--"....L
tWPH
VIH
WE
VIL
VIH
OE
VIL
VIH
-----+----..
Data
VIL -----1----'
CHIP CLEAR
Waveforms
VIH
CE
VIL
VH
OE
VIH
..
tw
VIH
WE
tw = 10ms
ts =tH = 11ls
VH = 12.0V ±O.5V
VIL
SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V
CE
VIL
VIL
OE
WE
A9
VH
VIL
X
VIL
VIH
A9=VH
VIH
A9= VH
• Pulsed per programming waveforms.
.
.
© 1991 Microchip Technology Inc.
Vee
Vee
Vee
Vee
1/01
Data Out
Data In
DS11125C-5
4-13
28C16A
DEVICE OPERATION
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
The Microchip Technology Inc 28C16A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode
CE
DE
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
L
H
H
L
X
X
X
X
X
L
H
L
Third, holding WE or CE high or DE low, inhibits a write
cycle during power-on and power-off (Vcc).
lID
Write Mode
H
DoUT
X
X
X
High Z
High Z
HighZ
High Z
DIN
The 28C16A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and
initiated by a I~oing pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
DE) are latched.
WE
H
L
Automatic Before Each "Write"
X = Any TTL level.
Data Polling
Read Mode
The 28C16A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion olthe write cycle, true data is available.
Data polling allows a simyle readlcompare operation to
determine the status of the chip eliminating the need for
external hardware.
The 28C16A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(DE) is the output control and is used to gate data to the
output pins independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is
available at the output tOE after the falling edge of DE,
assuming that CE has been low and addresses have
been stable for at least IACC-tOE.
Electronic Signature for Device Identification
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±O.SV and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
Standby Mode
The 28C16A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the ou'E!!.ts are in a high impedance state, independent
of the DE input.
Qptional Chip Clear
Data Protection
AU data may be cleared to 1's in a chip clear cycle by
raising DE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
In orderto ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
VCC is less than the Vcc detect circuit trip.
© 1991 Microchip Technology Inc.
DSll125C-6
4-14
28C16A
NOTES:
© 1991 Microchip Technology Inc.
DS11125C-7
4-15
28C16A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
K
L
P
I
Temperature
Range:
I
Access Time:
Blank
I
E
15
20
25
I Option:
F
' - - - - - - - - 1 Device:
16K
DS11125C-8
Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
0' C to 70' C
-40' C to 85' C
-40' C to 125' C
150 nsec
200 nsec
250 nsec
=twc= 1ms
=!wc = 2001's
(2K
x 8) CMOS
EEPROM
© 1991 Microchip Technology Inc.
4-16
28C17A
Microchip
16K (2K X 8) CMOS Electrically Erasable PROM
FEATURES
•
•
•
•
DESCRIPTION
Fast Read Access Time-150ns Maximum
CMOS Technology for Low Power Dissipation
-30mA Active
-1 OO~A Standby
Fast Byte Write Time--200~s or 1ms
Data Retention> 10 years
High Endurance 10' Erase/Write Cycles
Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
Enhanced Data Protection
-Vcc Detector
-Pulse Filter
-Write Inhibit
Electronic Signature for Device Identification
5-Volt-Only Operation
Organized 2Kx8 JEDEC Standard Pinout
-28 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Lead less or Plastic)
Available for Extended Temperature Ranges:
-Commercial: O' C to 70' C
-Industrial: _40' C to 85' C
-Automotive: _40' C to 125' C
The Microchip Technology Inc 28C17A is a CMOS 16K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C17A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables this
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
BLOCK DIAGRAM
PIN CONFIGURATION
Top View
RDYIBSY
Voc
NC
WE
NC
V,,_
V,,_
I~
~~~~~I~~
A6
Kjl~Jl~Jl~J!;]l~Jl~Jl~Jrg~
A3
ViiE_
ii~ ~~
:: fj
iJ
Circuitry
Chip Enable!
Output Enable
Rdy!_
Control Logic
Auto EraseJWrile
Timing
Busy
ig~ A10
:::
AO ....
:ij CE
fig 1/07
iiJ \106
1/01
::::
::::
1/02
t_
t_
PLCC/LCC
A~O :::
.Pin 1 indicator on PLCC on top 01 package
L
]
a
t
c
h
DeC~der
Poll
D
-
I
I
Y Gating
:=:::=
16K bit
Cel! Matrix
X
Decoder
,
e
InpuVOutput
Buffers
Data
Program Voltage
Generation
i?§ NC
i?§ DE
A2 J~j
DIP/SOle
Data Protection
ff_
0._
A8
1/00····· .. 1/07
© 1991 Microchip Technology Inc.
DS11127C-1
4-17
28C17A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
AO - Al0
CE
OE
WE
1/00 -1/07
ROY/Busy
Vcc
Vss
NC
Add ress Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed
NU
MAXIMUM RATINGS*
Vcc and input voltages w.r.t. Vss ........ -0.6V to + 6.25V
Voltage on OE w.r.t. Vss ........................ -0.6V to +13.5V
Voltage on A9 W.r.t. Vss ........................... -0.6Vto +13.5V
Output Voltage W.r.t. Vss ... ,................ -0.6V to Vcc+0.6V
Storage temperature .......................... _65' C to 125' C
Ambient temp. with power applied ........ -50' C to 95' C
'Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation ofthe device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Vcc = +5V ±1 0%
Commercial (C): Tamb= 0' C to 70' C
Industrial
(I): Tamb= _40' C to 85' C
Automotive (E): Tamb= _40' C to 125' C
READ / WRITE OPERATION
DC Characteristics
Parameter
Input Voltages
Status
Symbol
Min
Max
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vec+l
0.8
V
V
III
-10
10
IlA
10
pF
Input Leakage
CIN
Input Capacitance
Units Conditions
VIN = -O.tV to Vec+ 1
VIN = OV; Tamb = 25' C;
f = 1 MHz
Output Voltages
Logic "1"
Logic "0"
Output Leakage
VOH
VOL
2.4
ILO
-10
GoUT
Output Capacitance
0.45
V
V
IOH = -4OOIlA
IOL=2.1mA
10
IlA
VOUT = -0.1 V to Vec+O.l V
12
pF
VIN= OV; Tamb = 25' C;
f = 1 MHz
Power Suppy Current, Active
TTL input
Icc
30
mA
f = 5 MHz (Note 1)
Vce = 5.5V;
Power Supply Current, Standby
TTL input
TTL input
CMOS input
ICC(S)TTL
leC(S)TTL
ICC(S)CMOS
2
3
100
mA
mA
IlA
CE = VIH (0' C to 70' C)
CE = VIH (-40' C to 125' C
CE = Vce-0.3 to Vee+ 1
Note: (1) AC power supply current above 5 MHz: 1 mA/MHz
© 1991 Microchip Technology Inc.
DS11127C-2
4-18
28C17A
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Sym
Parameter
Address to Output Delay
VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = O°Cto 70° C
(I): Tamb = _40° C to 85° C
Industrial
Automotive (E): Tamb = _40° C to 125° C
28C17A-15
28C17A-20
28C17A-25
Min
Min
Min
Max
Max
Units
Conditions
Max
tAcc
150
200
250
ns
OE = CE = VIL
CE to Output Delay
teE
150
200
250
ns
OE = VIL
OE to Output Delay
toE
70
80
100
ns
CE = VIL
CE or OE High to Output Float
toFF
0
70
ns
Output Hold from Address, CE
or OE, whichever occurs first.
toH
0
-
50
0
0
55
0
0
ns
READ WAVEFORMS
x
VIH
Address
VIL
VIH
Address Valid
~
CE
VIL
VIH
~
~
--:;;;
"'"""
VIL
- - toE(2)
VOH
Data
Z-
teE(2)
~ ..-
OE
X
--
IIIII
HighZ
\\\\\
VOL
~~
- --:;;;
-- toFF(! ,3)
toH
Valid Output
I--
\ \\\1\
High Z
IIIIV
tAcc
VIH
WE
VOL
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on teE
(3) This parameter is sampled and is not 100% tested
DS11127C-3
© 1991 Microchip Technology Inc.
4-19
28C17A
BYTE WRITE
AC Characteristics
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
VIH= 2.4V and VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0' C to 70' C
(I): Tamb = -40' C to 85' C
Industrial
Automotive (E): Tamb = -40' C to 125' C
Symbol
Min
Address Set-Up Time
tAS
10
Address Hold Time
tAH
50
ns
Data Set-Up Time
tos
50
ns
Parameter
Max
Units Remarks
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
twPL
100
ns
Write Pulse High Time
twPH
50
ns
OE Hold Time
toEH
10
ns
OE Set-Up Time
tOES
10
Data Valid Time
tDV
ns
1000
Note 2
ns
Time to Device Busy
tDB
50
ns
Write Cycle Time (28C17A)
twe
1
ms
0.5 ms typical
twe
200
~s
100~s
Write Cycle Time (28C17AF)
-
2
Note 1
typical
-
Note: (1) A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, wichever occurs first.
(2) Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until
tDH after the positive edge of WE or CE, whichever occurs first.
I-----twe
© 1991 Microchip Technology Inc.
DS11127C-4
4-20
28C17A
DATA POLLING
Waveforms
Address
VIH=>(
X'-____--' '-__-./
Address Valid
VIL
Last Written
Address Valid
tACC - -
CE VIH ~
V I"--"--L""---'
-"~
- _ _ _ _ _"'£''''£'.L-L....<---<~A....:~--''-'-''-_ _ _-+_ _ _ _ _ _ _ _ __
tCE
tWPH
VIH
WE
--
VIL
OE
VIL
VIH
Data
----+----.
True Data Out
VIL _ _ _-+-J
CHIP CLEAR
Waveforms
VIH - - - - - - - -___
CE
~~--------------------~/
VIL
VH
I~
VIH
--------------..1
WE
v
\
VIL
tw = 10ms
ts =tH = 11ls
VH = 12.0V ±O.5V
SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V
CE
VIL
VIL
OE
WE
A9
VH
VIL
X
VIL
VIH
A9=VH
VIH
A9=VH
• Pulsed per programming waveforms.
.
.
Vee
Vee
Vee
Vee
1/01
Data Out
Data In
DS11127C-5
© 1991 Microchip Technology Inc.
4-21
28C17A
DEVICE OPERATION
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
The Microchip Technology Inc 28C17A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
Operation Mode CE OE WE I/O
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vee).
Rdy/BusY(1)
Write Mode
H DoUT H
X X High Z H
X X High Z H
X High Z H
X L
X X H High Z H
L
L
H L DIN
Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X = Any TTL level.
Read Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
L
H
H
L
The 28C17A has a write cycle similar to that of a Static
RAM. The write cycle is completeluelf-timed and
initiated by a lQl!lLgoing pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
to accept another cycle.
The 28C17A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (lAcc) equal
to the delay from CE to output (tCE). Data is available at
the output tOE after the falling edge of OE, assuming that
CE has been low and addresses have been stable for at
least IACC-tOE.
Data Polling
The 28C17A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1/07 (1/00 to 1/06 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.
Standby Mode
Electronic Sianature for Device Identification
The 28C17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±O.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
Data Protection
In orderto ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
Optional Chip Clear
First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.
All data..!!1.ay be cleared to 1's in a ch~lear ~Ie by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
© 1991
DS11127C-6
4-22
Microchip Technology Inc.
28C17A
NOTES:
© 1991 Microchip Technology Inc.
DS11127C-7
4-23
28C17A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
~,!ZAF
-15 II P
' - - - Package:
J
K
L
P
SO
-i Temperature
Range:
I
Blank
I
E
15
20
25
Access Time:
I Option:
F
Device:
28C17A
Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
Plastic Small Outline IC
0' C to 70' C
-40' C to 85' C
-40' C to 125' C
150 nsec
200 nsec
250 nsec
=twc= 1ms
= twc = 200!J,S
(2K x 8) CMOS EEPROM
© 1991 Microchip Technology Inc.
DS11127C-8
4-24
28C64A
Microchip
64K (8K X 8) CMOS Electrically Erasable PROM
FEATURES
DESCRIPTION
Fast Read Access Time-150ns Maximum
• CMOS Technology for Low Power Dissipation
-30mA Active
-1 OOIlA Standby
Fast Byte Write Time-200lls or 1m~
• Data Retention> 10 years
High Endurance 104 Erase/Write Cycles
Automatic Write Operation
-Internal Control Timer
-Auto-Clear Before Write Operation
-On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
• Enhanced Data Protection
-Vee Detector
-Pulse Filter
-Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
Organized 8Kx8 JEDEC Standard Pinout
-28 Pin Dual-In-Line Package
-32-Pin Chip Carrier (Lead less or Plastic)
• Available for Extended Temperature Ranges:
-Commercial: 0' C to 70' C
-Industrial:
-40' C to 85' C
-Automotive: -40' C to 125' C
The Microchip Technology Inc 28C64A is a CMOS 64K
non-volatile electrically Erasable and Programmable
Read Only Memory. The 28C64A is accessed like a
static RAM for the read or write cycles without the need
of external components. During a "byte write", the
address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Following the initiation of write cycle, the device
will go to a busy state and automatically clear and write
the latched data using an internal control timer. To
determine when the write cycle is complete, the user has
a choice of monitoring the Ready/Busy output or using
Data polling. The Ready/Busy pin is an open drain
output, which allows easy configuration in wired-or
systems. Alternatively, Data polling allows the user to
read the location last written to when the write operation
is complete. CMOS design and processing enables th.is
part to be used in systems where reduced power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in
applications.
PIN CONFIGURATION
BLOCK DIAGRAM
1/00 ....... 1/07
Top View
RDY/BSY
A12
Rdyl
SUSy
1/01
DIP/SOIC
PLCC/LCC
X
64K bit
Decoder
Cell Matrix
• Pin 1 indicator on PLCC on top of package
© 1991 Microchip Technology Inc.
4-25
DS11109D-1
28C64A
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
AO - A12
CE
OE
WE
1/00-1/07
ROY/Busy
VCC
Vss
NC
Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
+5V Power Supply
Ground
No Connect; No Internal
Connection
Not Used; No External
Connection is Allowed
NU
MAXIMUM RATINGS'
VCC and input voltages W.r.t. Vss ........ -0.6V to + 6.25V
Voltage on OE w.r.t. Vss ........................... -0.6V to + 13.5V
Voltage on A9 W.r.t. Vss ............................ -0.6V to + 13.5V
Output Voltage w.r.t. Vss .................... -0.6V to Vcc+0.6V
Storage temperature .......................... -65' C to 125' C
Ambient temp. with power applied ........ -50' C to 95' C
'Notice: 8tresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation olthe device atthose or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
VCC: +5V ±1 0%
Commercial (C): Tamb: 0' C to 70' C
Industrial
(I): Tamb: -40' C to 85' C
READ / WRITE OPERATION
DC Characteristics
Parameter
Input Voltages
Status
Symbol
Min
Max
Units
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vcc+l
0.8
V
V
III
-10
10
J.lA
10
pF
Input Leakage
CIN
Input Capacitance
Conditions
VIN: -O.lV to Vcc+ 1
VIN: OV; Tamb : 25' C;
f: 1 MHz
Output Voltages
Logic "1"
Logic "0"
Output Leakage
VOH
VOL
2.4
ILo
-10
COUT
Output Capacitance
0.45
V
V
IOH: -400J.lA
IOL: 2.1mA
10
J.lA
VOUT: -0.1 V to Vcc+O.l V
12
pF
VIN: OV; Tamb : 25' C;
f: 1 MHz
Power Suppy Current, Active
TTL input
Icc
30
mA
f: 5 MHz (Note 1)
Vcc: 5.5V;
Power Supply Current, Standby
TTL input
TTL input
CMOS input
ICC(S)TTL
ICC(S)TTL
ICC(S)CMOS
2
3
100
mA
mA
J.lA
-
CE : VIH (0' C to 70' C)
CE: VIH (-40' C to 85' C)
CE : Vcc-0.3 to Vcc+ 1
Note: (1) AC power supply current above 5 MHz: 2 mA/MHz
© 1991 Microchip Technology Inc.
08111090-2
4-26
28C64A
READ OPERATION
AC Characteristics
VIH= 2.4V; VIL= 0.45V; VOH = 2.0V; VOL = 0.8V
AC Testing Waveform:
1 TTL Load + 100 pF
Output Load:
Input Rise and Fall Times: 20 nsec
Commercial (C):Tamb = 0' Cto 70' C
Ambient Temperature:
(1):Tamb = -40' C to 85' C
Industrial
Parameter
Sym
28C64A-15
28C64A-20
28C64A-25
Min
Min
Min
Max
Max
Units
Conditions
Max
IACC
150
200
250
ns
-OE= -CE = VIL
CE to Output Delay
teE
150
200
250
ns
OE= VIL
OE to Output Delay
toE
70
80
100
ns
CE = VIL
CE or OE High to Output Float
toFF
0
70
ns
toH
0
Address to Output Delay
-
Output Hold from Address, CE
or OE, whichever occurs first.
50
0
0
55
0
0
ns
READ WAVEFORMS
x
VIH
Address
VIL
VIH
Address Valid
~
~
~ I<:-
CE
VIL
~
VIH
~ ..-
VIL
IIIII
HighZ
/ VOL
..
\\\\\
:?
--
- -"""7
- - toE(2) - VOH
Z
teE(2)
OE
Data
X
toFF(1,3)
toH
Valid Output
f.-
\\\\r-.,
High Z
/I/IV
IAcc
VIH
WE
VIL
Notes: (1) toFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to teE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
D511109D-3
© 1991 Microchip Technology Inc.
4-27
28C64A
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
BYTE WRITE
AC Characteristics
Parameter
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb = 0' Cto 70' C
Industrial
(I): Tamb = -40' C to 85' C
Symbol
Min
Max
= 0.8V
Units Remarks
Address Set-Up Time
lAs
10
ns
Address Hold Time
IAH
50
ns
Data Set-Up Time
IDS
50
ns
Data Hold Time
IDH
10
ns
Write Pulse Width
twPL
100
ns
Write Pulse High Time
twPH
50
ns
OE Hold Time
toEH
10
ns
OE Set-Up Time
toES
10
ns
Note 1
Data Valid Time
tov
1000
ns
Time to Device Busy
IDB
50
ns
Write Cycle Time (28C64A)
twe
1
ms
0.5 ms typical
Write Cycle Time (28C64AF)
twe
200
~s
1OO~ typical
Note:
(1 )
(2)
Note 2
A write cycle can be initiated CE or WE going low, whichever occurs last. The data is latched on
the positive edge of CE or WE, whichever occurs first.
Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until
tOH after the positive edge of WE or CE, whichever occurs first.
PROGRAMMING
Waveforms
Address
--./ttAS"
VIH - - - - - - - - - .
VIL
Data In
_
_
:f~\
~::~_1v
VIH
VIL
VIL
tWPL
__ tov_ _
.....
"/
J
-.j:'
:===J
tos-~-=--=-,
_tOH
-',>-________
_ _ _~_ __++_-_<.?f-
VIH
OE
1~.._ - - t A H - -....
r'I ..
.., c:
':::,,,
tOES I"'r
-'
'-
K
1- tOEH
VOH
Rdy/Busy
VOL
..
twe
--,,-,,-_B-IU~adY
~
LtoB --I
© 1991 Microchip Technology Inc.
D511109D-4
4-28
28C64A
DATA POLLING
Waveforms
Address
VIH
VIL
=><
X~
Address Valid
____-' '- ___/
Last Written
Address Valid
tACC ...-
tCE
tWPH
VIH
WE
VIL
VIH
OE
VIL
VIH - - - - t______
True Data Out
Data
VIL - - - - t - '
CHIP CLEAR
Waveforms
VIH - - - - - - - - - - .
CE
OE
VIL
~~------------------~/
VH
V
/
VIH - - - - - - - - - - - - - . /
I~
I~..- - - tw ------<~
VIH - - - - - - - - - - -_____ 1
v
~
WE
VIL
tw = 10ms
ts =tH = 1 ~s
VH = 12.0V ±O.5V
SUPPLEMENTARY CONTROL
Mode
CE
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V ±O.5V
VIL
VIL
*
* Pulsed
OE
WE
A9
VH
VIL
X
VIL
VIH
A9 = VH
*
VIH
A9 = VH
per programming waveforms.
© 1991 Microchip Technology Inc.
Vee
Vee
Vee
Vee
1/01
Data Out
Data In
OS11109D-5
4-29
28C64A
DEVICE OPERATION
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10ns duration from initiating a write
cycle.
The Microchip Technology Inc 28C64A has four basic
modes of operation-read, standby, write inhibit, and
byte write-as outlined in the following table.
-
-
Operation Mode CE OE WE I/O
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (Vcc).
Rdy/BusY(1)
Write Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
L
L
H
DouT
H
H
X
X
X
X
L
X
X
X
X
H
L
H
L
High
High
High
High
DIN
Z
Z
Z
Z
H
H
H
H
H
The 28C64A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and
initiated by a I~oing pulse on the WE pin. On the
falling edge of WE, the address information is latched.
On rising edge, the data and the control pins (CE and
OE) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C64A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C64A has completed writing and is ready
to accept another cycle.
L
Automatic Before Each "Write"
Note: (1) Open drain output.
(2) X = Any TTL level.
Read Mode
The 28C64A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used fordevice selection. Output Enable (OE)
is the output control and is used to gate data to the output
pins independent of device selection. Assuming that
addresses are stable, address access time (lACC) is equal
to the delay from CE to output (tCE). Data is available at
the outputtOE afterthe falling edge of OE, assuming that
CE has been low and addresses have been stable for at
least tACC-tOE.
Data Polling
The 28C64A features Data polling to signal the completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of 1107 (1/00 to 1106 are indeterminable).
After completion of the write cycle, true data is available.
Data polling allows a simple read/compare operation to
determine the status of the chip eliminating the need for
external hardware.
Standby Mode
Electronic Signature for Device Identification
The 28C64A is placed in the standby mode by applying
a high signal tothe CE input. When in the standby mode,
the outputs are in a high impedance state, independent
of the OE input.
An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 1FEO to
1FFF, the additional bytes can be written to or read from
in the same manner as the regular memory array.
Data Protection
In order to ensure data integrity, especially during critical
power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
Optional Chip Clear
First, an internal Vcc detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation when
Vcc is less than the Vcc detect circuit trip.
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
© 1991 Microchip Technology Inc.
OS111090-6
4-30
28C64A
NOTES:
© 1991 Microchip Technology Inc.
DS11109D-7
4-31
28C64A
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
K
L
P
SO
I Temperature
Range:
I
I
Access Time:
Option:
1 - - - - - - - - - - 1 Device:
Cerdip
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PLCC))
Plastic DIP
Plastic Small Outline IC
15
20
25
0' C to 70' C
-40' C to 85' C
-40' C to 125'C
150 nsec
200 nsec
250 nsec
F
X
=twc= 1ms
= twc = 200~s
Pin 1 NC (Pin 2 PLCC), twc = 1ms
Blank
I
E
64K
(8K
x 8) CMOS
EEPROM
© 1991 Microchip Technology Inc.
OS11109D-8
4-32
Microchip
SECTION 5
EPROM PRODUCT SPECIFICATIONS
27C64
27C128
27C256
27C512
27HC1616
27HC256
27LV256
27LV512
27CXXX
64K (8K x 8) CMOS UV Erasable PROM ................................................... 5128K (16K x 8) CMOS UV Erasable PROM ............................................... 5256K (32K x 8) CMOS UV Erasable PROM ............................................... 5512K (64K x 8) CMOS UV Erasable PROM ............................................... 5256K (16K x 16) High Speed CMOS UV Erasable PROM ......................... 5256K (32K x 8) High Speed CMOS UV Erasable PROM ........................... 5256K (32K x 8) Low Voltage CMOS Erasable PROM ................................ 5512K (64K x 8) Low Voltage CMOS Erasable PROM ................................ 527CXXX EPROM Family Programming Algorithm ..................................... 5-
© 1992 Microchip Technology Inc.
1
9
17
25
33
41
49
57
65
DS00018E
5-i
Microchip
© 1992 Microchip Technology
DS00018E
5-ii
~.
27C64
Microchip
64K (8K X 8) CMOS EPROM
FEATURES
DESCRIPTION
High speed performance
-120ns maximum access time
CMOS Technology for low power consumption
-20mA Active current
-1 OOIlA Standby current
Factory programming available
Auto-insertion-compatible plastic packages
Auto IDTM aids automated programming
Separate chip enable and output enable controls
• High speed "express" programming algorithm
Organized 8K x 8: JEDEC standard pinouts
-28-pin Dual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-28-pin TSOP package
-Tape and reel
• Available for extended temperature ranges:
-Commercial: 0' C to 70' C
-Industrial: -40' C to 85' C
-Automotive: -40' C to 125' C
The Microchip Technology Inc 27C64 is a CMOS 64K bit
(electrically) Programmable Read Only Memory. The
device is organized as 8K words by 8 bits (8K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. CMOS design and processing enables this part to be used in systems where
reduced power consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount
applications, PLCC, SOIC, or TSOP packaging is
available. Tape and reel packaging is also available
for PLCC or SOIC packages. U.V. erasable versions
are also available.
PIN CONFIGURATIONS
Top View
Vee
NC
!;(~~~~~~
A8
l:Jl~Jl~J: ~il~Jl!:,Jl~J
A12
A7
A6
AS
A9
A11
6E
A10
CE
07
00
01
06
02
V"
'-------'
DIP/SOIC
05
O.
03
:~ ~::j
'i'
A4!~j
A3
A2
A1
AQ 3'~-j
NC j§]
[~
::
[}JA11
:jj NC
EJ
fj
J§l
:jj DE
:l!
L~3
Al0
CE
L~2 07
00 Jjj
:~:
:0: r;: r;: r~: f~: f~:
:j] 06
.-C\lC">-;tU')
oo~zooo
PLCC/LCC
TSOP
© 1992 Microchip Technology Inc.
DS11107G-1
5-1
27C64
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings·
Name
Function
AO - A12
CE
OE
PGM
Vpp
00-07
Vee
Vss
NC
Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No Internal
Connections
Not Used; No External
Connection Is Allowed
NU
Vee and input voltages w.r.t. Vss .......... -0.6V to +7.25V
Vpp voltage w.r.t. Vss during
programming ........................................ -0.6V to + 14V
Voltage on A9 W.r.t. Vss ............................ -0.6V to +13.5V
Output voltage w.r.t. Vss .................... -0.6V to Vee + 1.0V
Storage temperature .......................... -65 C to 150 C
Ambient temp. with power applied ..... -65 C to 125 C
0
0
0
0
"Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Vee = +5V ±1 0%
Commercial: Tamb= 0 C to 70 C
Industrial:
Tamb= -40 C to 85 C
Automotive: Tamb= -40 C to 125 C
READ OPERATION
DC Characteristics
0
0
0
0
0
0
Part·
Status
Symbol
Min
Max
Input Voltages
all
Logic "1"
Logic "0"
Input Leakage
all
VIH
VIL
III
2.0
-0.5
-10
Vee+l
0.8
10
!LA
VIN=
Output Voltages
all
2.4
0.45
10
V
V
I1A
IOH = -400!LA
IOL= 2.1mA
VOUT= OV to Vee
VIN= OV; Tamb = 25 C;
f = lMHz
VOUT= OV;Tamb= 25 C;
f = lMHz
Vee = 5.5V; Vpp = Vee;
f = lMHz;
OE = CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vcc;
Note 1
Parameter
V
V
Output Leakage
all
VOH
VOL
ILO
Input Capacitance
all
CIN
6
pF
Output Capacitance
all
COUT
12
pF
Power Suppy Current,
Active
S
X
TTL input
TTL input
lee1
lee2
20
25
mA
mA
Power Supply Current,
Standby
S
X
all
all
all
TTL input
TTL input
CMOS input
Read Mode
Read Mode
lee(s)
2
3
100
100
Vee
mA
mA
Ipp Read Current
Vpp Read Voltage
Logic "1"
Logic "0"
Units Conditions
-10
Ipp
Vpp
Vee-0.7
0
0
!LA
!LA
V
a to Vee
CE = Vee ±0.2V
Vpp= 5.5V
Note 2
" Parts:
S = Standard Power; X = Extended Temp. Range;
Notes: (1) AC Power component above 1MHz: 8mA up to maximum frequency.
(2) Vee must be applied before VPP, and be removed simultaneously or after VPP.
© 1992 Microchip Technology Inc.
DSlll07G-2
5-2
27C64
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Parameter
Sym 27C64-12
Min
Address to Output Delay IAcc
Max
27C64-15
Min
120
VIH= 2.4V and VIL= 0.45V;
1 TTL Load + 100 pF
10nsec
Commercial: Tamb=
0'
Industrial:
Tamb= _40'
Automotive: Tamb= _40'
27C64-17
27C64-20
Max Min
Max Min
Max
150
170
200
VOH = 2.0V VOL =0.8V
C to 70' C
C to 85' C
C to 125' C
27C64-25 Units
Min
Max
250
ns
CE to Output Delay
tCE
120
150
170
200
250
ns
OE to Output Delay
tOE
65
70
70
75
100
ns
CE or OE to OIP High
Impedance
tOFF
0
60
ns
Output Hold from
Address CE or OE,
whichever occurs first
tOH
0
50
0
0
50
0
0
50
0
0
55
0
Conditions
0
CE = OE = VIL
-
OE = VIL
CE = VIL
ns
READ WAVEFORMS
VIH
Address Valid
Address
VIL
VIH
CE
VIL
VIH
OE
VIL
Outputs
00-07
VOH
High Z
Valid Output
VOL
IAcc
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
© 1992 Microchip Technology Inc.
DS11107G-3
5-3
27C64
PROGRAMMING
DC Characteristics
Parameter
Input Voltages
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, Vpp = VH = 13.0V ± 0.25V
Status
Symbol
Min
Max
Units
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vee+1
0.8
V
V
III
-10
10
!!A
VOH
VOL
2.4
0.45
V
V
Input Leakage
Output Voltages
Logic "1"
Logie "0"
Conditions
VIN = OV to Vee
IOH= -400!!A
IOL = 2.1mA
Vee Current, program & verify
lee2
20
mA
Note 1
Vpp Current,program
IpP2
25
mA
Note 1
12.5
V
A9 Product Identification
VH
11.5
Note: (1) Vee must be applied simultaneously or before VPP and removed simultaneously or after VPP
PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes
Parameter
AC Testing Waveform: VIH = 2.4 V and VIL= 0.45 V; VOH = 2.0 V; VOL = 0.8 V
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Symbol
Min
Address Set-Up Time
lAS
2
!!S
Data Set-Up Time
tDS
2
!!S
Data Hold Time
tDH
2
!!S
Address Hold Time
tAH
0
!!S
Float Delay (2)
tDF
0
Vec Set-Up Time
tves
2
Program Pulse Width (1)
lPw
95
CE Set-Up Time
teES
2
!!S
OE Set-Up Time
toES
2
!!S
VPP Set-Up Time
tvps
2
!!S
-
Data Valid from OE
toE
Max
130
Units
Remarks
ns
!!S
105
100
!!S
1OO!!S typical
ns
Notes: (1) For express algorithm, initial programming width tolerance is 1OO!!sec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).
© 1992 Microchip Technology Inc.
DS11107G-4
5-4
27C64
PROGRAMMING
Waveforms (1)
~-----
Program - - - - - - i - " - - - - Verify - - - - - I . j
VIH
Address
Address Stable
VIL
VIH
High Z
Data
VIL
12.5 V (3)
Vpp
5.0 V
6.0 V (3)
Vcc
5.0 V
VIH
CE
VIL
VIH
PGM
VIL
toE
VIH
(2)
OE
VIL
Notes:
(1) The input timing reference is 0.8 V for VIL and 2.0 V for VIH.
(2) tDF and toE are characteristics of the device but must be accommodated by the programmer.
(3) Vcc = 6.0 V ±0.25 V, Vpp = VH = 12.5 V ±0.25 V for fast programming algorithm and
Vcc = 6.5 V ±0.25 V, VPp = VH = 13.0 V ±0.25 V for Express algorithm.
MODES
Read Mode
Operation Mode CE
-
OE
-PGM
VPp
A9
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VIH
VIL
X
X
VIH
VIL
VIH
VIL
VIH
X
X
VIH
VIH
Vee
VH
VH
VH
Vee
Vee
Vee
X
X
X
X
X
X
VH
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
(See Timing Diagrams and AC Characteristics)
00-07
Read Mode is accessed when
DoUT
DIN
DoUT
a) the CE pin is low to power up (enable) the chip
High Z
High Z
High Z
Identity Code
b) the OE pin is low to gate the data to the output
pins.
x = Don't Care
For Read operations, if the addresses are stable, the
address access time (tAce) is equal to the delay from CE
to output (tCE). Data is transferred to the output after a
delay from the falling edge of OE (tOE).
DS11107G-5
© 1992 Microchip Technology Inc.
5-5
27C64
Standby Mode
The standby mode is defined when the CE and PGM
pins are both high (VIH).
After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:
When these conditions are met, the supply current will
drop from 20mA to 100f,1A.
a)
b)
c)
d)
e)
Output Enable
This feature eliminates bus contention in microprocessor-based systems in which multiple devices may drive
the bus. The outputs go into a high impedance state
when the following condition is true:
When programming multiple devices in parallel with
different data, only CE or PGM need be under separate
control to each device. By pulsing the CE or PGM line
low on a particular device in conjunction with the PGM or
CE line low, that device will be programmed; all other
devices with CE or PGM held high will not be programmed with the data, although address and data will
be available on their input pins (I.e., when a high level is
present on CE or PGM); and the device is inhibited from
programming.
The OE and PGM pins are both high.
Erase Mode
ru.v_ Windowed Versions)
Windowed products offer the capability to erase the
memory array. The memory matrix is erased to the all
1's state when exposed to ultraviolet light. To ensure
complete erasure, a dose of 15 watt-second/cm' is
required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000f,1W/cm' for approximately 20 minutes.
Identity Mode
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc. and
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE lines must be
at VIL. AO is used to access any of the two non-erasable
bytes whose data appears on 00 through 07.
Programming Mode
The Express Algorithm has been developed to improve
the programming throughput times in a production environment. Up to ten 1~O-microsecond pulses are applied
until the byte is verified. No overprogramming is required. A flowchart of the express algorithm is shown in
Figure 1.
Programming takes place when:
a)
b)
c)
d)
e)
Vcc is at the proper level,
Vpp is at the proper VH level,
the CE line is low,
the PGM line is high, and
the OE line is low.
Pin--
Vcc is brought to the proper voltage,
Vpp is brought to the proper VH level,
the CE pin is low,
the OE pin is high, and
the PGM pin is low.
Identity
~
Manufacturer
Device Type*
Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO-A12 and the data to be programmed is
presented to pins 00-07. When data and address are
stable, OE is high, CE is low and a low-going pulse on the
PGM line programs that location.
Input
Output
AO
0 0 0 0 0
7 6 5 4 3
0
2
0 0
1 0
VIL
VIH
0
0
1
0
0
0
0
1
0 1
0 0
0
0
H
e
x
1 29
0 02
• Code subiect to change.
© 1992 Microchip Technology Inc.
DS11107G-6
5-6
27C64
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 2S" C ±S" C
Vee = 6.S ±O.2SV
Vpp = 13.0 ±0.2SV
ADDR = First Location
Vee = 6.SV
Vpp= 13.0V
Verify
B~e
Pass
r------------,
No
Last
Yes
Address? r-=--------,
© 1992 Microchip Technology Inc.
DS11107G-7
S·7
27C64
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
K
L
P
SO
TS
I Temperature
Range:
O' C
I
E
' - - - - - - I Access Time:
12
15
17
20
25
1..--------1. Device:
Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC
Plastic TSOP
27C64
DS11107G·8
to 70' C
·40' C to 85' C
·40' C 10 125' C
120 nsec
150 nsec
170 nsec
200 nsec
250 nsec
64K (8K x 8) CMOS EPROM
© 1992 Microchip Technology Inc.
5-8
27C128
Microchip
128K (16K X 8) CMOS EPROM
FEATURES
DESCRIPTION
High speed performance
-120ns Maximum access time
CMOS Technology for low power consumption
-20mA Active current
-100~A Standby current
Factory programming available
Auto-insertion-compatible plastic packages
Auto IOTM aids automated programming
Separate chip enable and output enable controls
• High speed "express" programming algorithm
• Organized 16K x 8: JEOEC standard pinouts
-28-pin Oual-in-line package
-32-pin Chip carrier (lead less or plastic)
-28-pin SOIC package
-28-pin TSOP package
-Tape and reel
Available for extended temperature ranges:
-Commercial: O· C to 70· C
-Industrial: -40· C to 85· C
-Automotive: -40· C to 125· C
The Microchip Technology Inc 27C128 is a CMOS 128K
bit (electrically) Programmable Read Only Memory. The
device is organized as 16K words by 8 bits (16K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than 120ns. CMOS design and processing enables this part to be used in systems where
reduced power consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC, SOIC, or TSOP packaging is available.
Tape and reel packaging is also available for PLCC or
SOIC packages. UV erasable versions are also available.
PIN CONFIGURATIONS
Top View
Vee
A12
Vee
PGM
A6
A13
AS
A9
A5
A11
6E
A3
A2
C07
~~~~~~~
A6
EJ l:Jl~Jl~Ji~jl~_:l~Jl~J:~~
A5 _6~j
A4 !~j
A3
_iU
A2 _9~j
A1
AD JiJ
NC _1j]
01
05
00 5§j
02
D.
03
DIP/SOle
L"2§
NC
f}~
DE
L2!
_t§j
06
AS
L2..8 A9
L2.? A11
L~;
lj3
A10
CE
07
fjj· 06
r~: :01:~: :~l:~:r~: :~l
..... C\J-'-""'-----,
© 1992 Microchip Technology Inc.
OS 11 003G-7
5-15
27C128
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
K
L
P
so
TS
I
Temperature
Range:
I
E
'------f
'---------1
Access Time:
Device:
12
15
17
20
25
27C128
Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC
Plastic TSOP
0' C to 70' C
·40' C to 85' C
-40' C to 125' C
120 nsec
150 nsec
170 nsec
200 nsec
250 nsec
128K (16K x 8) CMOS EPROM
© 1992 Microchip Technology Inc.
DSll003G-8
5-16
~.
27C256
Microchip
256K (32K X 8) CMOS EPROM
FEATURES
•
•
•
•
DESCRIPTION
The Microchip Technology Inc 27C256 is a CMOS 256K
bit (electrically) Programmable Read Only Memory. The
device is organized as 32K words by 8 bits (32K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than gOns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.
High speed performance
-gOns maximum access time
CMOS Technology for low power consumption
-20mA Active current
-100IlA Standby current
Factory programming available
Auto-insertion-compatible plastic packages
Auto IDTM aids automated programming
Separate chip enable and output enable controls
High speed "express" programming algorithm
Organized 32K x 8: JEDEC standard pinouts
-28-pin Dual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-28-pin TSOP
-Tape and reel
Available for extended temperature ranges:
-Commercial: O· C to +70' C
-Industrial: -40· C to +85' C
-Automotive: -40· C to + 125' C
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC, SOIC or TSOP packaging is available.
Tape and reel packaging is also available for PLCC or
SOIC packages. UV erasable versions are also available.
PIN CONFIGURATIONS
Top View
v••
l~Jl~Jl:'Ji -il~Jl:;Jl~J
A6
AS
EJ
EJ
'.'
'_2! A8
:_2..8 A9
A4.?]
III
A3
:_~ NC
EJ
A11
A5
A4
A3
L~
A1 _1§]
L2_4 A10
AO jSj
[23 CE
_tgj
07
00
06
01
02
r}}
fii
00 3jj
r~lr01r~lr~1 r~~ :~l r~i
DE
A9
A11
DE
A2
A1
AO
A2..9]
NC
Vee
A14
A13
A8
A12
A7
A6
A10
CE
07
06
05
04
03
V~~
PLCC/LCC
DIP/SOIC
TSOP
© 1992 Microchip Technology Inc.
DS11001H-1
5-17
27C256
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings·
Name
Function
AO-A14
CE
OE
Vpp
00-07
Vee
vss
NC
Address Inputs
Chip Enable
Output Enable
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection;
No Internal Connection
Not Used; No External
Connection is Allowed
NU
Vcc and input voltages w.r.t. Vss ......... -0.6V to +7.25V
VPP voltage w.r.t. Vss during
programming ..................................... -0.6V to + 14.0V
Voltage on A9 w.r.t. Vss ............................ -0.6V to + 13.5V
Output voltage w.r.t. Vss .................. -0.6V to Vec + 1.0V
Storage temperature .......................... -65' C to 150' C
Ambient temp. with power applied ..... -65' C to 125' C
'Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device atthose or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Vce = +5V ±1 0%
Commercial: Tamb= O· C to 70' C
Industrial:
Tamb= -40' C to 85' C
Automotive: Tamb= -40' C to 125' C
READ OPERATION
DC Characteristics
Part"
Status
Symbol
Min
Max
Input Voltages
all
Logic "1"
Logic "0"
Input Leakage
all
VIH
VIL
III
2.0
-0.5
-10
Vec+1
0.8
10
V
V
flA
VIN= 0 to Vec
Output Voltages
all
2.4
0.45
10
V
V
flA
IOH= -400flA
IOL= 2.1mA
VOUT= OV to Vce
VIN= OV; Tamb = 25' C;
f= 1MHz
VOUT= OV;Tamb= 25' C;
f= 1MHz
Vee = 5.5V; VPP = Vcc:
f= 1MHz;
OE = CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1
Parameter
Logic "1"
Looic "0"
Units Conditions
Output Leakage
all
VOH
VOL
ILO
Input Capacitance
all
CIN
6
pF
Output Capacitance
all
GoUT
12
pF
Power Suppy Current,
Active
S
X
TTL input
TTL input
Icc1
Icc2
20
25
mA
mA
Power Supply Current,
Standby
S
X
all
all
all
TTL input
TTL input
CMOS input
Read Mode
Read Mode
Icc(s)
2
3
100
100
Vce
mA
mA
uA
flA
V
Ipp Read Current
Vpp Read Voltage
Ipp
Vpp
-10
Vee-0.7
CE = Vec +0.2V
Vpp = 5.5V
Note 2
* Parts:
S = Standard Power; X = Extended Temp. Range;
Notes: (1) AC Power component above 1MHz: 5mA up to maximum frequency.
(2) Vcc must be applied before VPP, and be removed simultaneously or after VPP.
© 1992 Microchip Technology Inc.
DSll001H-2
5-18
27C256
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Parameter
VIH= 2.4V and VIL= .45V; VOH = 2.0V VOL =0.8V
1 TTL Load + 100pF
10nsec
Commercial: Tamb = O· C to 70' C
Industrial:
Tamb = -40' C to 85' C
Automotive: Tamb = -40' C to 125' C
Sym 27C256·90· 27C256·10· 27C256·12 27C256·15 27C256·20 Units Conditions
Min Max
Address to Output Delay lAcc
-
CE to Output Delay
-
tCE
OE to Output Delay
tOE
CE or OE to OIP High
Impedance
tOFF
a
Output Hold fro!!!...
Address CE or OE,
whichever goes first
toH
a
Min
Max
Min
Max
Min
Max
Min
Max
90
100
120
150
200
ns
90
100
120
150
200
ns
40
30
45
a
a
30
55
a
a
35
65
a
a
50
a
75
ns
55
ns
a
-
-
CE = OE= VIL
OE = VIL
-
CE = VIL
ns
• -10, -90 AC Testing Waveform: VIH = 2.4V and VIL = .45V; VOH = 1.5V and VOL= 1.5V
Output Load: 1 TLL Load + 30pF
READ WAVEFORMS
VIH
Address Valid
Address
VIL
VIH
CE
VIL
VIH
OE
VIL
Outputs
00-07
VOH
High Z
Valid Output
VOL
lACC
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
© 1992 Microchip Technology Inc.
DS11001H-3
5-19
27C256
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, VPp = 13.0V ± 0.25V
PROGRAMMING
DC Characteristics
Parameter
Input Voltages
Status
Symbol
Min
Max
Units
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vee+1
0.8
V
V
III
-10
10
~A
VIN = OV to Vee
VOH
VOL
2.4
0.45
V
V
IOH = -400~A
IOL = 2.1mA
Input Leakage
Output Voltages
Logic "1"
Logic "0"
Conditions
Vee Current, program & verify
lee2
20
mA
Note 1
Vpp Current, program
IpP2
25
mA
Note 1
12.5
V
A9 Product Identification
VH
11.5
Note: (1) Vee must be applied Simultaneously or before VPP and removed simultaneously or after VPP
PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes
Parameter
AC Testing Waveform: VIH= 2.4 V and VIL= 0.45 V; VOH = 2.0 V; VOL = 0.8 V
Output Load:
1 TTL Load + 100 pF
Ambient Temperature: Tamb = 25' C ±5' C
Vee = 6.5V ± 0.25V, Vpp = 13.0V ± 0.25V
Symbol
Min
Address Set-Up Time
lAS
2
~s
Data Set-Up Time
tos
2
~s
Data Hold Time
tOH
2
~s
Address Hold Time
lAH
0
~s
Float Delay (2)
tOF
0
Vee Set-Up Time
tves
2
Program Pulse Width (1)
tpw
95
CE Set-Up Time
teES
2
~s
OE Set-Up Time
tOES
2
~s
VPP Set-Up Time
tvps
2
~s
-
-
Data Valid from OE
Notes:
tOE
Max
130
Units
Remarks
ns
~s
105
100
~s
1OO~s typical
ns
(1) For express algorithm, initial programming width tolerance is 1OO~sec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).
© 1992 Microchip Technology Inc.
DS11001 H-4
5-20
27C256
PROGRAMMING
Waveforms
/ 4 - - - - - - Program
------f4----- Verify ------1~
Address
Data
Vpp
5.0V
Vee
5.0V
VIH
CE
VIL
toE
(1)
VIH
DE
VIL
Notes:
(1 ) IDF and toE are characteristics of the device but must be accommodated by the programmer
(2) Vee = 6.5 V ±0.25 V, Vpp = VH = 13.0 V ±O.25 V for express algorithm
MODES
ReadModa
Operation Mode CE DE
Vpp
A9
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
Vee
VH
VH
VH
Vee
Vee
Vee
X
X
X
X
X
X
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIL
VIH
X
VIH
VIL
VH
(See Timing Diagrams and AC Characteristics)
00-07
Read Mode is accessed when
DoUT
DIN
DoUT
a) the CE pin is low to power up (enable) the chip
High Z
High Z
High Z
Identity Code
b) the DE pin is low to gate the data to the output
pins.
For Read operations, if the addresses are stable, the
address access time (lAce) is equal to the delay from CE
to output (tCE). Data is transferred to the output aiter a
delay from the falling edge of DE (tOE).
x = Don~ Care
© 1992 Microchip Technology Inc.
DS11001H-5
5-21
27C256
Standby Mode
The standby mode is defined when the CE pin is high
(VI H) and a program mode is not defined.
After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are mel:
When these condition are met, the supply current will
drop from 20mA to 1001lA.
a)
b)
c)
d)
Output Enable
Vcc is at the proper level,
VPp ~at the proper VH level,
The CE pin is high and
the OE line is low.
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
The OE pin is high and a program is not defined.
When programming multiple devices in parallel with
different data, only CE need be under separate control
to each device. By pulsing the CE line low on a particular
device, that device will be programmed; all other devices
with CE held high will not be programmed with the data,
although address and data will be available on their input
pins.
Erase Mode (U.V. Windowed Versions)
Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all 1's state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm 2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000/lW/cm2 for approximately 20 minutes.
Identity Mode
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc and
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE lines must be
at VIL. AO is used to access any of the two non-erasable
bytes whose data appears on 00 through 07.
Programming Mode
The express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 lOa-microsecond pulses are
applied until the byte is verified. No overprogramming is
required. A flowchart of the express algorithm is shown
in Figure 1.
Pin-
Identity
Programming takes place when:
a)
b)
c)
d)
Input
AO
i
Vcc is brought to proper voltage,
VPp is brought to proper VH level,
The OE pin is high and
the CE pin is low.
Manufacturer
Device Type"
VIL
VIH
Output
00 0 0 0 0 0 0
7 6 5 4 3 2 1 a
a a 1 a 1 a a
1 a a a 1 1 a
H
e
x
1 29
a 8C
• Code subject to change.
Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO-A 14 and the data to be programmed is
presented to pins 00-07. When data and address are
stable, a low-going pulse on the CE line programs that
location.
© 1992 Microchip Technology Inc.
DS11001H-6
5-22
27C256
PROGRAMMING· FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb ~ 25' C ±5' C
Vee ~ 6.5 ±0.25V
VPp ~ 13.0 ±0.25V
ADDR
~
First Location
6.5V
VPP~ 13.0V
Vee~
Verify
Byte
Pass
)-'--==-------,
Fail
No
Last
Yes
Address? ) - - - - - - ,
No
Increment Address
D811001 H-7
© 1992 Microchip Technology Inc.
5-23
27C256
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
27C256 • 25 I / TS
T_
Package:
J
K
L
P
SO
TS
Range:
I Temperature
" - - - - - - 1 Access Time:
---11
L-_ _ _ _ _ _
Device:
I
E
90
10
12
15
20
27C2S6
CERDIP
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC
TSOP
0' C to 70' C
-40' C to 85' C
-40' C to 125' C
90
100
120
150
200
nsec
nsec
nsec
nsec
nsec
2S6K (32K x 8) CMOS EPROM
© 1992 Microchip Technology Inc.
DS11001H-B
5-24
27C512
Microchip
512K (64K X 8) CMOS EPROM
DESCRIPTION
FEATURES
The Microchip Technology Inc 27C512 is a CMOS 512K
bit (electrically) Programmable Read Only Memory. The
device is organized into 64K words by 8 bits (64K bytes).
Accessing individual bytes from an address transition or
from power-up (chip enable pin going low) is accomplished in less than gOns. This very high speed device
allows the most sophisticated microprocessors to run at
full speed without the need for WAIT states. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and reliability are requirements.
• High speed performance
-gOns access time available
CMOS Technology for low power consumption
-35mA Active current
-1 OOJ.1A Standby current
Factory programming available
Auto-insertion-compatible plastic packages
• Auto IDTM aids automated programming
• High speed express programming algorithm
Organized 64K x 8: JEDEC standard pinouts
-28-pin Dual-in-line package
-32-pin Chip carrier (Ieadless or plastic)
-28-pin SOIC package
-28-pin TSOP
-Tape and reel
Available for extended temperature ranges:
-Commercial: 0' C to 70' C
-Industrial: _40' C to 85' C
-Automotive: _40' C to 125' C
A complete family of packages is offered to provide the
most flexability in applications. For surface mount
applications, PLCC or SOIC packaging is available.
Tape or reel packaging is also available for PLCC or
SOIC packages. U.V. erasable versions are also
available.
PIN CONFIGURATIONS
Top View
A1S
Vee
A14
A12
A7
A6
AS
A13
AS
A9
A11
OElVpp
A4
A3
A2
A10
A1
CE
AO
07
00
01
06
05
04
02
03
PLCC/LCC
© 1992 Microchip Technology Inc.
DIP/SOIC
DS110061-1
5-25
27C512
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings'
Name
Function
AO - A15
CE
OE/Vpp
Address Inputs
Chip Enable
Output Enable/
Programming Voltage
Data Output
+5V Power Supply
Ground
No Connection; No Internal
Connection
Not Used; No External
Connection Is Allowed
00 - 07
Vee
VSS
NC
NU
Vee and input voltages W.r.t. Vss ......... -0.6V to +7.25V
Vpp voltage w.r.t. vss during
programming ..................................... -0.6V to + 14.0V
Voltage on A9 W.r.t. Vss ............................ -0.6V to + 13.5V
Output voltage W.r.t. Vss .................. -0.6V to Vce + 1.0V
Storage temperature .......................... _65' C to 150' C
Ambient temp. with power applied ..... _65' C to 125' C
"Notice: Stresses above those listed under"Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Vec = +5V ±1 0%
Commercial: Tamb= 0' C to 70' C
Tamb= _40' C to 85' C
Industrial:
Tamb= _40' C to 125' C
Automotive:
READ OPERATION
DC Characteristics
Part'
Status
Symbol
Min
Max
Input Voltages
all
Logic "1"
Logic "0"
Input Leakage
all
VIH
VIL
III
2.0
-0.5
-10
Vce+1
0.8
10
Output Voltages
all
2.4
Parameter
Logic "1"
Logic "0"
Output Leakage
all
VOH
VOL
ILO
Input Capacitance
all
CIN
-10
Units Conditions
V
V
~A
VIN= 0 to Vee
IOH= -400~A
IOL= 2.1 mA
VOUT= OV to Vee
V
V
0.45
10
~A
6
pF
VIN = OV; Tamb = 25' C;
f = 1MHz
Output Capacitance
COUT
all
12
pF
VOUT= OV;Tamb= 25' C;
f -1MHz
Power Suppy Current,
Active
S
X
TTL input
TTL input
Icc
Ice
35
45
mA
mA
Vee= 5.5V
f = 1MHz;
OE/vpp= CE = VIL;
lout = OmA;
VIL= -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Power Supply Current,
Standby
S
X
S
leC(S)TIL
TTL input
ICe(S)TIL
TTL input
CMOS input ICC(S)CMOS
2
3
100
mA
mA
~A
CE = Vec ±0.2V
S = Standard Power; X = Extended Temp. Range;
" Parts:
Notes: (1) AC Power component above 1MHz: 2mA/MHz.
DSll0061-2
© 1992 Microchip Technology Inc.
5-26
27C512
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Parameter
VIH= 2.4V and VIL= .45V;
1 TTL Load + 100pF
10nsec
Commercial: Tamb = O'
Tamb = _40'
Industrial:
Automotive: Tamb = _40'
Sym 27C512-90' 27C512-10' 27C512-12 27C512-15 27C512-20
VOH = 2.0V and VOL = O.BV
C to 70' C
C to 85' C
C to 125' C
Units
Conditions
Min Max Min Max Min Max Min Max Min Max
Address to Output
Delay
lACC
90
100
120
150
200
ns
CE to Output Delay
tCE
90
100
120
150
200
ns
OE to Output Delay
tOE
40
45
55
65
75
ns
OE to Output High
Impedance
tOFF
0
55
ns
toH
0
Output H~from
Address, CE or
OEIVpp, whichever
occu red fi rst
35
0
35
0
40
0
0
0
45
0
0
0
CE = OEIVpp = VIL
-
OEIVpp = VIL
-
CE = VIL
ns
* -10, -90 AC Testing Waveform: VIH = 2.4V and VIL = .45V; VOH = 1.5V and VOL = 1.5V
Output Load: 1 TTL Load + 30pF
READ WAVEFORMS
VIH
X
Address
VIL
VIH
r
~
Address Valid
z
~
CE
VIL
VIH
tCE(2)
- - tOE(2) -VOH
IIIIIIIIII
\\\\\\\\\\
High Z
VOL
-~
VIL
Outputs
00 -07
"'-
•
~
OEIVpp
lX
Z"-
tOFF(1.3) - tOH
~
Valid Output
\1\\\\
/11/1/
High Z
lAcc
Notes: (1) tOFF is specified for OEIVpp or CE, whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
© 1992 Microchip Technology Inc.
OS110061-3
5-27
27C512
Ambient Temperature: 25' C ±5' C
Vee = 6.5V ± 0.25V, OE/Vpp = VH = 13.0V ± 0.25V
PROGRAMMING
DC Characteristics
Parameter
Input Voltages
Status
Symbol
Min
Max
Units
Logic "1"
VIH
2.0
Vee+1
V
Logic "0"
Vil
-0.1
0.8
V
ill
-10
10
IlA
Logic "1"
VOH
2.4
Logic "0"
VOL
Input Current (all inputs)
Output Voltages
VIN = OV to Vee
V
IOH = -400J,IA
0.45
V
IOl=2.1mA
vcc Current, program & verify
lec2
35
mA
OE/Vpp Current, program
IpP2
25
mA
A9 Product Identification
VID
12.5
V
11.5
Conditions (See Note 1)
CE = Vil
Note: (1) Vee must be applied simultaneously or before the Vpp voltage on OE/Vpp and removed simultaneously
or after the Vpp voltage on OE/vpp.
PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes
AC Testing Waveform: VIH= 2.4V and Vll= 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load:
1 TTL Load + 100pF
Ambient TemperaturEl.'- 25' C ±5' C
Vee = 6.5V ± 0.25V, OE/Vpp = VH = 13.0V ± 0.25V
Parameter
Symbol
Min
Address Set-Up Time
lAs
2
Ils
Data Set-Up Time
tDS
2
Ils
Data Hold Time
tDH
2
Ils
Address Hold Time
IAH
0
Ils
Float Delay (2)
tDF
0
VceSet-Up Time
tves
2
Program Pulse Width (1)
tpw
95
CE Set-Up Time
teES
2
Ils
OE Set-Up Time
tOES
2
Ils
OE Hold Time
tOEH
2
Ils
tcR
2
Ils
tPRT
50
ns
-
OE Recovery Time
-
OE/Vpp Rise Time During Programming
Notes:
Max
130
Units
Remarks
ns
Ils
105
Ils
1OOIlS typical
(1) For express algorithm, initial programming width tolerance is 1OOllsec ± 5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).
OS110061-4
© 1992 Microchip Technology Inc.
5-28
27C512
PROGRAMMING
Waveforms (1)
Program
..
Verify
VIH
Address
VIL
---~
VIH
Data
Data Out Valid
VIL
tDF
(2)
6.0 V (3)
Vcc
5.0V
VIH
CE
VIL
tOR12.5 V (3)
____I
OE/Vpp
VIL
Notes:
(1) The input timing reference level is 0.8 V for VIL and 2.0 V for VIH.
(2) lDF and tOE are characteristics of the device but must be accommodated by the programmer.
(3) Vcc; 6.0 V ±0.25 V, VPP; VH = 12.5 V ±0.5 V for fast programming algorithm.
MODES
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
Read Mode
-
-OENpp
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VH
VIL
VH
CE
X
VIH
VIL
A9
00-07
X
X
X
X
X
X
DoUT
VH
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
DIN
DoUT
a) the CE pin is low to power up (enable) the chip
High Z
High Z
HighZ
Identity Code
b) the OE/vpp pin is low to gate the data to the
output pins.
X = Don't Care
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from CE
to output (tCE). Data is transferred to the output after a
delay (tOE) from the falling edge of OE/Vpp.
DS110061-5
© 1992 Microchip Technology Inc.
5-29
27C512
Standby Mode
Since the erased state is "1" in the array, programming
of "0" is required. The address to be programmed is set
via pins AO - A 15 and the data to be programmed is
presented to pins 00 - 07. When data and address are
stable, a low going pulse on the CE line programs that
location.
The standby mode is defined when the CE pin is high
and a program mode is not identified.
When this condition is met, the supply current will drop
from 35mA to 1OOI!A.
Output Enable OE/Vpp
After the array has been programmed it must be verified
to ensure all the bits have been correctly programmed.
This mode is entered when all the following conditions
are met:
This multifunction pin eliminates bus connection in multiple bus microprcessor systems and the outputs go to
high impedance when:
a) Vcc is at the proper level,
b) the OE/Vpp pin is low, and
c) the CE line is low.
• the OE/Vpp pin is high (VIH).
When a VH input is applied to this pin, it supplies the
programming voltage (Vpp) to the device.
When programming multiple devices in parallel with
different data, only CE needs to be under separate
control to each device. By pulsing the CE line low on a
particular device, that device will be programmed; all
other devices with CE held high will not be programmed
with the data (although address and data will be available on their input pins).
Erase Mode (U.V. Windowed Versions)
Windowed products offer the ability to erase the memory
array. The memory matrix is erased to the all "1 "'s state
as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/cm 2
is required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms, intensity of 12,000I!W/cm2 for approximately 20 minutes.
Identity Mode
In this mode specific data is output which identifies the
manufacturer as Microchip Technology Inc and the
device type. This mode is entered when Pin A9 is taken
to VH (11.5V to 12.5V). The CE and OE/Vpp lines must
be at VIL. AO is used to access any of the two nonerasable bytes whose data appears on 00 through 07.
Programming Mode
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. A flowchart of the
Express algorithm is shown in Figure 1.
Pin--
a) Vcc is brought to the proper voltage,
b) OE/Vpp is brought to the proper VH level, and
c) CE line is low.
Output
Identity
AO
00 0
7 6 5
0 0
4 3
0
2
0 0
1 0
Manufacturer
Device Type"
VIL
VIH
0 0
0 0
0
0
1
1
0
1
0
0
~
Programming takes place when:
Input
1
0
H
e
x
1 29
1 00
• Code subject to change.
D8110061-6
© 1992 Microchip Technology Inc.
5-30
27C512
PROGRAMMING - FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 25' C ±5' C
Vee = 6.5 ±0.25V
VPp = 13.0 ±0.25V
ADDR = First Location
Vee = 6.5V
Vpp= 13.0V
Verify
Byte
Pass
)--.:c..:..::_ _ _ _---;
No
Last
Address?
Yes
)--=-=------,
No
Increment Address
D8110061-7
© 1992 Microchip Technology Inc.
5-31
27C512
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
J
K
L
P
SO
TS
I
Temperature
Range:
E
'-------1 Access Time:
' - - - - - - - - - 1 Device:
I
90
10
12
15
20
27C512
Cerdip
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Plastic DIP
Plastic SOIC
TSOP
O· C to 70· C
-40· C to 85· C
-40· C to 125· C
90 nsec
100 nsec
120nsec
150nsec
200 nsec
512K (64K x 8) CMOS EPROM
© 1992 Microchip Technology Inc.
OS110061-8
5-32
27HC1616
Microchip
256K (16K X 16) High Speed CMOS UV Erasable PROM
FEATURES
DESCRIPTION
16 bit configuration
• High speed performance
-55ns Maximum access time
CMOS Technology for low power consumption
-90mA Active current
-50mA Standby current
WordWide architecture offers space saving over
Bytewide memories
Organized 16K x 16: JEDEC standard pinouts
-40-Pin ceramic dual in line package
-44-Pin ceramic leadless chip carrier
Extended temperature ranges available:
-Commercial: O°C to +70°C
The Microchip Technology Inc. 27HC1616 is a CMOS
16K x 16 (256K) Programmable Read Only Memory.
The device operates at Bipolar PROM speeds but uses
far less currentthan any Bipolar PROM. The 27HC1616
is an excellent choice for any application requiring
blazing speeds and low power consumption. The word
wide (16 bit) architecture can replace two 8 bit EPROMS
in any 16 bit application saving valuable printed circuit
space and components costs. Typical applications for
the 27HC1616 include automotive systems control, high
speed modems, digital signal processing, or any application that uses the 80386, 68030, 29000, etc. high
performance microprocessors.
PIN CONFIGURATION
BLOCK DIAGRAM
00 .............. ·015
Top View
CE
DE
PGM
g661~ g:~~I~~ ~ ~
0910
08 11
12
0
NC 13
07
06
05
04
Programming
Logic
vpp
6 5 4 3 2 14443424140
012 7
39
011 8
38
010 9
37
Vss
Chip Enable/
Oulput Enable
Control Logic
36
35
A13
A12
A11
A10
A'
34
v"
33
14
32
15
31
16
30
17
29
1819202122232425262728
Output Buffers
Vss
Vee
AO
I
I
I
I
I
I
I
I
I
NC
A8
A7
A6
A5
8 S 0 81~ ~ Si! ;( ~ ~ ::l:
LCC
~
i
00
00
i"
~
r-L-____
-J-,~----------~
L-r------,~~----------~
X
Decoder
256K bit
Cell Matrix
I
DIP
AI3
© 1992 Microchip Technology Inc.
DS11010D-1
5-33
27HC1616
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE
Maximum Ratings*
Name
Function
AO-A13
CE
OE
PGM
Vpp
00-01S
Vee
Vss
NC
Address Inputs
Chip Enable
Output Enable
Program Enable
Programming Voltage
Data Output
+SV Power Supply
Ground
No Connection; No
Internal Connection
Vee and input voltages w.r.t. Vss .......... -0.6V to +7.2SV
Vpp voltage w.r.t. Vss during
programming ..................................... -0.6V to +14.0V
Voltage on A9 w.r.t. Vss ............................ -0.6V to +13.SV
Output voltage w.r.t. Vss .................... -0.6V to Vee +1.0V
Temperature under bias ...................... -6S·C to 12S' C
Storage temperature ........................... -6S'C to lS0' C
ESO protection on all pins ..................................... 2KV
'Notice: Stresses above those listed under "Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation olthe device atthose or any
other conditions above those indicated in the operation listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Vee = +SV ±10%
Commercial: Tamb=
READ OPERATION
DC Characteristics
Parameter
O' Cto 70' C
Part"
Status
Symbol
Min
Max
Input Voltages
all
Logic "1"
Loaic"O"
Input Leakage
a"
VIH
VIL
III
2.0
-0.1
-10
Vee+l
0.8
10
V
V
~
VIN=-O.l to Vee + 1.0V
Output Voltages
a"
2.4
0.4S
10
V
V
itA
IoH=-2mA
IOL=8mA
VOUT= -0.1 to Vee + O.lV
VIN = OV; Tamb = 2S' C;
1-1MHz
VOUT= OV;Tamb= 2S' C;
1= lMHz
Vee = S.SV; Vpp = Vee
1=2MHz;
OE = CE= VIL;
lout = OmA;
VIL = -0.1 to 0.8 V;
VIH= 2.0 to Vee;
Note 1
Output Leakage
all
VOH
VOL
ILO
Input CapaCitance
a"
CIN
6
pF
Output Capacitance
.all
CoUT
12
pF
Power Suppy Current,
Active
a"
Icc
90
mA
Power Supply Current,
Standby
pp Read Current
Vpp Read Voltage
S,X
lee(s)
SO
mA
100
Vee
~
V
a"
all
Logic "1"
Loaic "0"
Units Conditions
TIL input
Read Mode
Read Mode
Ipp
Vpp
-10
Vee-0.7
Vpp= S.SV
Note 2
• Parts:
S = Standard Temp; X = Industrial Temp Range;
Notes: (1) AC Power component above 2MHz: 2mAlMHz.
(2) Vee must be applied simultaneously or belore Vpp and be removed simultaneously
or after VPP.
© 1992 Microchip Technology Inc.
DS11010D-2
S-34
27HC1616
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
READ OPERATION
AC Characteristics
Parameter
Part"
Sym
VIH = 3.0 V and VIL= 0.0 V; VOH= VOL = 1.5 V
1 TTL Load + 30 pF
5 nsec
O' C to 70' C
Commercial: Tamb=
27HC1616·55
27HC1616·70
Min
Min
Max
Units
Conditions
Max
-
CE = OE = VIL
Address to Output Delay
all
lAcc
55
70
ns
CE to Output Delay
all
tCE2
35
45
ns
OE = VIL
OE to Output Delay
all
toE
30
35
ns
CE = VIL
CE or OE to OIP High
Impedance
all
tOFF
0
25
ns
all
tOH
0
Output Hold fro~
Address CE or OE, whichever occurs first
20
0
0
-
ns
• Parts: S = Standard Power; L = Low Power
READ WAVEFORMS
VIH
Address valid
Address
VIL
VIH
CE
VIL
VIH
OE
VIL
Outputs
00 - 015
VOH
High Z
Valid Output
VOL
lAcc
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - toE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
© 1992 Microchip Technology Inc.
DS11010D-3
5-35
27HC1616
PROGRAMMING
DC Characteristics
Parameter
Input Voltages
Ambient Temperature: 25' C ±5' C
For vpp and Vee Voltages refer to Programming Algorithms
Status
Symbol
Min
Max
Units
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.1
Vee+l
O.S
V
V
III
-10
10
~A
VIN= -.lV to Vee+ 1.0V
VOH
VOL
2.4
0.45
V
V
IOH = - 2mA
IOL= SmA
Input Leakage
Output Voltages
Logic "1"
Logic "0"
Conditions
Vee Current, program & verify
lee
90
mA
Note 1
Vpp Current, program
Ipp
50
mA
Note 1
A9 Product Identification
VH
12.5
V
11.5
Note: (1) Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp
PROGRAMMING
AC Characteristics
for Program, Program Verify
and Program Inhibit Modes
Parameter
AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V and VOL = O.SV
Ambient Temperature: 25' C ±5' C
For Vpp and Vee Voltages, refer to Programming Algorithms
Symbol
Min
Address Set-Up Time
lAs
2
~s
Data Set-Up Time
lOs
2
~s
Data Hold Time
lOH
2
~s
Address Hold Time
lAH
0
~s
Float Delay (2)
tDF
0
Vee Set-Up Time
tves
2
Program Pulse Width (1)
tpw
95
CE Set-Up Time
teEs
2
~s
OE Set-Up Time
tOES
2
~s
Vpp Set-Up Time
tvps
2
~s
-
Data Valid from OE
toE
Max
130
Units
Remarks
ns
~s
105
100
~s
100 ~s typical
ns
Notes: (1) For express algorithm, initial programming width tolerance is 100 ~sec ±5%.
(2) This parameter is only sampled and not 100% tested. Output float is defined as the point where data
is no longer driven (see timing diagram).
DS11010D-4
© 1992 Microchip Technology Inc.
5-36
27HC1616
PROGRAMMING
Waveforms
1 - - - - - - P r o g r a m - - - - - + - - - - - Verify
-----<~
Address
Data
VPp
5.0V
Vee
5.0V
VIH
CE
VIL
VIH
PGM
VIL
tOE
VIH
(1 )
OE
VIL
Notes:
(1 ) tDF and toE are characteristics of the device but must be aceomodated by the programmer
(2) Vee = 6.0V ±O.25V, VPp = VH = 12.5V ±O.5V for fast programming algorithm
Vee = 6.5V ±O.25V, VPp = VH = 13.0V ±O.25V for express algorithm
FUNCTIONAL DESCRIPTION
The 27HC1616 has the following functional modes:
-Operation: The 27HC1616 can be activated for data
read, be put in standby mode to lower its power
consumption, or have the outputs disabled.
-Programming: To reeeive its permanent data, the
27HC1616 must be programmed. Both a program
and program/verify procedure is available. It can be
programmed using the Fast or Express algorithm;
however, the Express algorithm is recommended.
Operation Mode CE
OE
-PGM
Vpp A9
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
VIL
VIH
VIL
X
X
VIH
VIL
VIH
VIL
VIH
X
X
VIH
VIH
Vee X
VH
X
VH
X
VH
X
Vee X
Vee X
Vee VH
VIL
VIL
VIH
VIH
VIH
X
VIL
00·015
Dout
On
Dout
HighZ
High Z
High Z
Identity Code
X = Don't Care
VH = 12.0 ±0.5V
The programming equipment ean automatically recognize the device type and manufacturer using the identity
mode.
For the general characteristics in these operation and
programming modes, refer to the table.
©
1992 Microchip Technology Inc.
DS11010D-5
5-37
27HC1616
OPERATION
Verify
Read Mode
Afterthe array has been programmed, it must be verified
to make sure that all the bits have been correctly
programmed. This mode is entered when all of the
following conditions are met:
For timing and AC characteristics refer to the tables
Read Waveforms and Read Operation AC Characteristics.
a) Vcc is at the proper level
b) VPP .l§..at the proper VH level
c) the OE line is low
d) the CE pin is low, and
e) the PGM line is high.
The 27HC1616's memory data is accessed when
-the chip is enabled by setting the CE pin low.
_
-the data is gated to the output pins by setting the OE
pin low.
For Read operations on the Low Power version, once
the addresses are stable, the address access time
(tACC) is equal to the delay from CE to output (tCE). A
faster CE access time (tCE) is available on the standard
part to provide the additional time for decoding the CE
signal. Data is transferred to~e output after a delay
(tOE) from the falling edge of OE.
Inhibit Mode
When Programmin~ltiple devices in parallel with
different data only PGM needs to be under separate
control to each device. By pulsing the PGM line low on
a particular device, that device will be programmed, and
all other devices with corresponding PGM or CE held
high will not be programmed with the data although
address and data are available on their input pins.
Standby Mode
The standby mode is entered when the CE pin is high,
and the program mode is not defined. When these
conditions are met, the supply current will drop from
90mA to 50mA.
Identity Mode
In this mode specific data is read from the device that
identifies the manufacturer as Microchip Technology,
and the device type. This mode is entered whe.!'!..Pin A9
is taken to VH (11.5V to 12.5V). The CE and OE pins
must be at VIL. AO is used to access any of the two nonerasable bytes whose data appears on 00 - 07.
Output Disable
This feature eliminates bus contention in multiple bus
microprocessor systems. The outputs go to a high
impedance when the OE pin is high, and the program
mode is not defined.
Pin-
ProgramminglVerification
The 27HC1616 has to be programmed, and afterward
the programmed information verified. Before these
operations, the Identity Code can be read to properly set
up automated equipment. Multiple devices in parallel
can be programmed using the programming and inhibit
modes.
Output'
Identity
AO
00 0
7 6 5
Manufacturer
Device Type*
VIL
VIH
0 0
1 0
i
Programming Algorithm
Input
1
0
00 0
4 3 2
0 0
1 0
0 1
1 0
0
1
0
1
H
e
x
1 29
1 97
*Code subject to change.
Note: 015 - 08 are 00 for the manufacturer and
device type code.
The "Express" algorithm has been developed to improve
programming through-put times in a production environment. Up to 10 pulses of 1OO/lsec each are applied until
the byte is verified. No overprogramming is required. A
flowchart of this algorithm is shown in Figure 2.
Erasure
The programming mode is entered when:
Windowed products offerthe ability to erase the memory
array. The memory matrix is erased to the all "1 "s state
as a result of being exposed to ultra-violet light at
wavelengths ,,;4000 Angstroms (A). The recommended
procedure is to expose the erasure window of device to
a commercial UV source emitting at 2537A with an
intensity of 12,000/lW/cm2 at 1". The erasure time at that
distance is about 15 to 20 min.
a) VCC is brought to the proper level
b) VPp is brought to the proper VH level
c) the OE pin is high
d) the CE pin is low, and
e) the PGM pin is pulsed low.
Since the erase state is"1" in the array, programming of
"0" is required. The address of the memory location to
be programmed is set via pins AO - A 13, and the data is
presented to pins 00 - 015. When data and address are
stable, a low going pulse on the CE line programs that
memory location.
Note: Fluorescent lights and sunlight emit rays at the
specified wavelengths. The erasure time is about 3
years or 1 week resp. in these cases. To prevent loss of
data, an opaque label should be placed overthe erasure
window.
DS11010D-6
© 1992 Microchip Technology Inc.
5-38
27HC1616
PROGRAMMING· FIGURE 1
EXPRESS ALGORITHM
Conditions:
Tamb = 25' C ±5' C
Vee = 6.5 ±0.25 V
VPp = 13.0 ±0.25 V
AD DR = First Location
Vee = 6.5 V
Vpp=13.0V
D811010D-7
© 1992 Microchip Technology Inc.
5-39
27HC1616
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the
factory or the listed sales offices.
PART NUMBERS
27HC1616 - 45 II P
r
~"""'"
i
i
J
K
O' C to 70' C
Temperature
Range:
Access Time:
_I Device:
Cerdip DIP
Ceramic Leadless Chip Carrier
55
70
27HC1616
OS110100-8
55 nsec
70 nsec
256K (16K x 16) High Speed CMOS EPROM
© 1992 Microchip Technology Inc.
5-40
27HC256
Microchip
256K (32K X 8) High Speed CMOS EPROM
FEATURES
DESCRIPTION
High speed performance
-55ns access time available
CMOS technology for low power consumption
-55mA active current
-1 OOIlA standby current (low power option)
OTP (one time programming) available
Auto-insertion-compatible plastic packages
Auto IDTM aids automated programming
• Organized in 32K x 8 - JEDEC Standard Pinouts
-28-pin Dual-in-line and SOIC package
-32-pin Chip carrier (Ieadless or plastic)
Extended temperature ranges available:
-Commercial: O· C to +70· C
-Industrial: -40· C to +85· C
-Automotive: -40· C to + 125· C
The Microchip Technology Inc 27HC256 is a CMOS
256K bit (electrically) Programmable Read Only Memory.
The device is organized into 32K words of 8 bit each.
Advanced CMOS technology allows bipolar speed with
a significant reduction in power. A low power option (L)
allows further reduction in the standby power requirement
to 100IlA. The 27HC256 is configured in a standard
256K EPROM pinout which allows an easy upgrade for
present 27C256 users. A complete family of packages
are offered to provide the utmost flexibility. The 27HC256
allows high performance microprocessors to run at full
speed without the need of wait states. CMOS design
and processing makes this part suitable for applications
where reliability and reduced power consumption are
essential.
PIN CONFIGURATIONS
TOP VIEW
Vpp
Vpp
Vee
A12
A14
AS
AS
A9
A11
OE
A3
A2
A10
A1
CE
AO
07
06
01
05
02
04
Vss
03
DIP
~: ~~j
A4
A3
A2
A1
AO
~~-: l~J l~J !~! l~J l~J L~J L.2~
YJ
EJ
3Ij
NC ]iJ
00 ]§j
Iii :~: fiel f~:f~: re:r~:
..- C\l
00::> M"<:t
L()
OO;§!zOOO
PLCC/LCC
A9
AS
AS
A4
III
A11
A3
OE
A11
[]3 OE
:jj A10
fjj CE
:]_2 07
:j] 06
j§J
Vee
A14
A13
AS
[jj A9
:}~ NC
EJ
A7
A6
A12
r--~&::>8.:!~
<Z> " en en en
9'"
"
'"
NIC
DATA OUT
DATA IN
SEG4
SEG26
SEG5
LCD
SEG24
8P
SEG23
SEGS
SEG21
SEG7
SEG20
SEGS
SEG 19
NIC
:!! to:
w
~
;!
::?
co
co co co
co
w w fB w w w
en en en en en en
BLOCK DIAGRAM
"
~
fB
Data In
Data Out
vss
Clock
Direction
Voo
Supply voltage
Latch data from registers
Direct drive outputs
Backplane drive output
Backplane drive input
Data input to shift register
Data output from shift register
Ground
System clock input
Input
Output
Output
Input
Input
Output
Ground
Input
FIGURE 2 OSCILLATOR FREQUENCY
GRAPH (TYPICAL @ 2S·C)
FIGURE 1 TIMING DIAGRAM
:.
:;----\
CLOCK ~
Description
1/t
"
;----\:
~
140
~
_
1\
\
120
~
5l
s:w
LOAD
~
~
100
~
80
~
60
40
'"
o
20
40
-........
b....
60
80
"""""'I~
100
--
120
CL (pF)
OPERATING NOTES
condition and pass the LCD inputto the backplane
output. If the LCD pin is allowed to oscillate, its
frequency is inversely proportional to capacitance
and the LCD drivingwaveforms have a frequency 2 8
slower than the oscillator itself. The relationship is
shown graphically (see Figure 2). The frequency is
nearly independent of supply voltage. If LCD is
oscillating, it is important to keep coupling capacitance to backplane and segments as low as possible. Similarly, it is recommended that the load
capacitance on LCD be as large as is practical.
1. The shift register loads, shifts, and outputs on the
falling edge of the clock.
2. A logic 1 on Data In causes a segment to be visible.
3. A logic 1 on Load causes a parallel load of the data in
the shift register into latches that control the segment
drivers.
4. If LCD is driven, it is in phase with the backplane
output.
8. There are two obvious signal races to be avoided in
this circuit, (1) changing Data In when the clock is
falling, and (2) changing Load when the clock is
falling.
5. To cascade units, either connect backplane of one
circuitto LCD of all other circuits (thus one capacitor
provides frequency control for all circuits) or connect
LCD of all circuits to a common driving signal. If the
former is chosen, tie just one backplane to the LCD
and use a different backplane output to drive the
LCD inputs. The data can be loaded to all circuits in
parallel or else Data Out can be connected to Data In
to form a long serial shift register.
9. The number of a segment corresponds to how
many pulses have occurred since its data was
present at the input. For example, the data on SEG
17 was input 17 clock pulses earlier.
1O.lt is acceptable to tie the load line high. In this case
the latches are transparent. Also, remote control
would only require two signal lines, clock and Data
In.
6 The supply voltage of the AY0438 is equal to half the
peak driving voltage of the LCD.
7. The LCD pin can be used in two modes, driven or
oscillating. If LCD is driven, the circuit will sense this
DS70()10H-2
© 1992 Microchip Technology Inc.
6-2
AY0438
ELECTRICAL CHARACTERISTICS
*Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied. Operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Data labeled "typical" is presented for design guidance
only and is not guaranteed.
Maximum Ratings'
Voo ......................................................... -0.3V to + 12V
Inputs (CLK, Data In, Load) ............. Vcc to Voo +0.3V
LCD Input... ................................. -0.3V to Voo +0.3V
Power Dissipation ............................................ 250mW
Storage Temperature ......................... -65'C to + 125'C
Operating Temperature Industrial ........ -40'C to +85'C
Voo : +5V unless otherwise noted
TA: -40'Cto +85'C
DC CHARACTERISTICS
Characteristics
Sym
Min
Supply Voltage
Voo
+3.0
Supply Current
100
Input High Level
Input Low Level
VIH
VILl
VIL2
IL
CI
0.5Voo
0
0
VOH
VOL
0.8Voo
0
LCD Input High Level
VIN
0.9Voo
LCD Input Low Level
VIL
0
Clock,
Data,
Input Leakage Current Load
Input Capacitance
Segment Output Voltage
LCD Input Leakage
Current Level
Typ
Max
Units
+8.5
V
25
13
60
30
IlA
Il A
-
Voo
0.1 Voo
0.1 Voo
±10
5.0
V
V
V
IlA
pF
-
Voo
0.1Voo
V
V
-
Voo
V
O.1Voo
V
10
IlA
0.01
-
-
IL
Conditions
LCD OSC < 15 kHz
LCD OSC < 100Hz
3.0V ~ Voo ~ 8.5V
3.0V ~ Voo ~ 8.5V
VIN : OV and +5.0V
Voo: +5.0V
IOH : -1 OOIlA
IOL: 100llA
VIN : OV and +5.0V
Voo: +5.0V
AC CHARACTERISTICS
Characteristics
Sym
Min
f
DC
Data Set-up Time
tds
150
-
Data Hold Time
tdh
50
-
Load Pulse Width
tpw
175
-
-
nsec
Data Out Prop. Delay
tpd
-
-
500
nsec
Clock Rate
Typ
© 1992 Microchip Technology Inc.
Max
Units
Conditions
1.5
MHz
50% duty cycle
-
nsec
Data change to Clk
falling edge
nsec
CL: 55pF
DS70010H-3
6-3
AY0438
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
AY0438 - 1/ P
~ P'''.gTemperature
Range:
P
L
S
Plastic DIP
PLCC
Die in waffle pack
D· to 70' C
40°C to 85°C
32 Segment LCD Driver
Device:
DS70010H-4
© 1992 Microchip Technology Inc.
6-4
DIGITAL SIGNAL
PROCESSORS
Microchip
DSP Product Portfolio
COMMERCIAL DSP (0° TO 70°)
CMOS DSP - COMMERCIAL (0· TO 70·)
Microchip
Part Number
Speed (MHz) 1
TI Part Number
Maximum Instruction
Cycle Time (ns)
Internal Mask ROM
Version Available
Package
DSP320C 10-32/P
15.0 to 32.8
122
X
40L Plastic DIP
DSP320Cl0-321L
15.0 to 32.8
122
X
44L PLCC
DSP320C 10-25/P
15.0 to 25.61
TMS320Cl0NL-25
156
X
40L Plastic DIP
DSP320Cl0-25/L
15.0 to 25.61
TMS320Cl0FNL-25
156
X
44L PLCC
oJ to ~U.::>I
HI::>
X
40L Plastic DIP
6.7 to 20.51
TMS320Cl0FNL
19b
X
44L 1-'Ll;l;
6.7 to 14.41
TMS320Cl0NL-14
277
X
40L Plastic DiP
oJ to 14.4
277
;<..
44L 1-'Ll;l;
lUll"'
TMS320Cl0NL
~v, u~uv
lOlL
DSP320Cl0-14/P
'V'
u.uvlU-14IL
INDUSTRIAL DSP (-45° TO +85°C)
CMOS DSP - INDUSTRIAL (-45· TO +85·C)
Microchip
Part Number
Speed (MHz) 1
TI Part Number
Maximum Instruction Internal Mas ROM
Version Available
Cycle Time (ns)
Package
DSP320Cl0-321/P
15.0 to 32.8
122
X
40L Plastic DIP
DSP320Cl0-3211L
15.0 to 32.8
122
X
44L PLCC
DSP320Cl0-2511P
15.0 to 25.61
TMS320Cl0NA-25
156
X
40L Plastic DIP
DSP320Cl0-251/L
15.0 to 25.61
TMS320Cl0FNA-25
156
X
44L PLCC
DSP320Cl0i/P
6.7 to 20.51
TMS320Cl0NA
195
X
40L Plastic DIP
DSP320Cl01/L
6.7 to 20.51
TMS320Cl0FNA
195
X
44L PLCC
DS21025C-l
© 1992 Microchip Technology Inc.
6-5
DIGITAL SIGNAL PROCESSORS
Please refer to the "MILITARY DATA BOOK"
MILITARY DSP (-55· TO +110·C)
;
CMOS DSP - MILITARY (-55" TO +125"C)
Microchip
DESCSMD
Part Number
DSP320C10-B/QA
5962-B763301QA
6.7 10 20.5
5692-B763301 QC
SMJ320C10JDM
6.71020.5
DSP320C10-B/OC
Speed (MHz)
Part Number
Number
Maximum
TIPart
Cycle Time (ns)
Package
Instruction
Lead
Finish
195
40LCeramic
Solder
195
Side-Braze
40LCeramic
Gold
Internal
Masked ROM
Version
Side-Braze
DSP320C10-B/UA
5962-B763301 XA
6.71020.5
195
SMJ320C10FDM
DSP320C10-B/UC
5692-B763301 XC
6.71020.5
44 Terminal
Solder
LCC
195
44 Terminal
Gold
LCC
DSP320C10-25B/QA
5962-B763302QA
15.01025.6
156
40L Ceramic
Solder
Side-Braze
DSP320C10-25B/QC
DSP320C10-25B/UA
5962-B763302QC
5692-B763302XA
15.01025.6
15.01025.6
156
40LCeramic
Gold
156
Side-Braze
44 Terminal
Solder
LCC
DSP320C10-25B/uC
5962-B763302XC
15.01025.6
156
44 Terminal
Gold
LCC
DSP320CF10-25B/QA
5962-B763305QA
6.71025.6
156
40LCeramic
Solder
Side-Braze
DSP320CF10-25B/QC
5962-B763305QC
6.71025.6
156
40LCeramic
Gold
Side-Braze
DSP320CF10-25B/UA
DSP320CF10-25B/UC
5962-B763305XA
5962-B763305XC
6.71025.6
6.71025.6
156
44 Terminal
Solder
156
LCC
44 Terminal
Gold
LCC
DSP320CM10-B/QA
5962-B763303QA
6.71020.5
195
X
DSP320CM10-B/QC
5962-B763303QC
40L Ceramic
Solder
Side-Braze
6.71020.5
195
40L Ceramic
Gold
X
Side-Braze
DSP320CM10-B/UA
5962-B763303XA
6.71020.5
195
X
DSP320CM 1O-B/UC
5962-B763303XC
44 Terminal
Solder
LCC
6.71020.5
195
44 Terminal
Gold
X
LCC
DSP320CM10-25B/QA
5962-B763304QA
15.01025.6
156
X
DSP320CM10-25B/QC
5962-B763304QC
40LCeramic
Solder
Side-Braze
15.01025.6
156
40LCeramic
Gold
X
Side-Braze
DSP320CM10-25B/UA
5962-B763304XA
15.01025.6
156
X
DSP320CM10-25B/UC
5962-B763304XC
44 Terminal
Solder
LCC
15.01025.6
156
44 Terminal
Gold
X
LCC
DS21025C-2
© 1992 Microchip Technology Inc.
6-6
DIGITAL SIGNAL PROCESSORS
r-:
PART NUMBERS - MILITARY (see next page for Commercial and Industrial Parts)
DSP320x10 - 321 / Q A
~~ F'o'.,
A
C
Solder Dip
Gold
Case Outline:
Q
44 Pin Side Braze OIL
40 Terminal LCC
U
B
'------II Screening
I
I
Level':
Frequency:
25
Device:
'Note: 32010
DSP32010
DSP320C10
DSP320CF10
DSP320C10
MIL-STD-883C Compliant
(-55· C to 125· C)
20.5 MHz
25.6 MHz
NMOS
CMOS
CMOS
CMOS
DSP
DSP
DSP, 6.7 to 25.6 MHz
DSP, ROM Version
= TE (Thermally Enhanced LCC); 320C10 = NTE (Non·Thermally Enhanced LCC)
PART NUMBERS - DESC SMD
5u2 87633
!O'T
I
-II
c......._ _
Lead Finish:
A
C
Case Outline':
X
Q
Z
Version:
301
302
303
304
305
~--------II Device:
5962
5692
Solder Dip
Gold
Ceramic Dual-in-Iine (28 lead)
Ceramic Side Braze DIL(40 lead)
Flat pack
6.7 to 20.5 MHz
15.0to 25.6 MHz
6.7 to 20.5 MHz, ROM Version
15.0 to 25.6 MHz, ROM Version
6.7 to 25.6 MHz
CMOS DSP
NMOS DSP
*Note: The Case Outline Code is used for order entry only and will not be marked on device
© 1992 Microchip Technology Inc.
DS21025C-3
6-7
DIGITAL SIGNAL PROCESSORS
NOTES:
DS21025C-4
© 1992 Microchip Technology Inc.
6-8
DSP320C10
Microchip
CMOS Digital Signal Processor
FEATURES
DESCRIPTION
•
•
•
•
•
The DSP320C10 is the first low power CMOS member
of the Microchip Technology DSP320 family of digital
signal processors, designed to support a wide range of
high-speed or numeric-intensive applications. This
device is a CMOS pin-for-pin compatible version of the
industry standard DSP32010 digital signal processor.
•
•
•
•
•
•
•
•
•
•
•
122M instruction cycle
144 word on-chip data RAM
ROM-less version - DSP320C 10
1.5K word on-Chip program ROM-DSP320CM10
External memory expansion to a total of 4K words
at full speed
16-bit instruction/data word
32-bit ALU/Accumulator
16 x 16-bit multiply in 122ns
0 to 15-bit barrel shifter
Eight input and eight output channels
16-bit bidirectional data bus with a 65Mbps
transfer rate
Interrupt with a full context save
Signed two's complement fixed-point arithmetic
CMOS technology
Single 5 volt supply
Four versions available:
-DSP320C10-1414.4MHz Clock
-DSP320C10
20.5MHz Clock
-DSP320C10-25
25.6MHz Clock
-DSP320C10-32
32.8MHz Clock
The processor has been enhanced to make the Data
RAM static with respect to the Reset. Also, the address
hold time has been improved to a non-negative value.
This 16/32 bit single-chip microcomputer combines the
flexibility of a high-speed controller with the numerical
capability of an array processor thereby offering an
inexpensive alternative to multichip bit-slice processors.
The DSP320 family contains MOS microcomputers
capable of executing eight million instructions per second. This high throughput is the result of the comprehensive, efficient, and easily programmed instruction
set and of the highly pipelined architecture. Special
instructions have been incorporated to speed the execution of digital signal processing (DSP) algorithms.
The DSP320 family's unique versatility and power give
the design engineer solutions to a variety of complicated
applications. In addition, these microcomputers are
capable of providing the multiple functions often required for a single application. For example, the DSP320
family can enable an industrial robot to synthesize and
recognize speech, sense objects with radar or optical
intelligence, and perform mechanical operations through
digital servo loop computations.
PIN CONFIGURATION
40 LEAD DIP
44 PIN PLCC
Top View
Al/PAl
AOIPAO
MCilillP
1
2
3
A21PA2
A3
A4
A5
AS
A7
AS
RS
lin'
CLKOUT
Xl
X21CLKIN
A7
!lEA
m
[!Ell
31
WE
Vee
09
013
07
A9
Ala
All
DO
01
02
03
Vee
A9
Al0
A11
DO
D12
D1
D4
D5
© 1990 Microchip Technology Inc.
DS21037B-1
DSP320C10
DSP320C10 BLOCK DIAGRAM
;- ............................................ -A11 : AO'- .................................................. ..
Xl
PA2-PAO
015 -DO
MICROPROCESSOR
OPTION
PROGRAM
MEMORY ROM
INSTRUCTIONS
16
16 BITS
ADDRESS
(l44X 16)
16
16
RAM
ARITHMETIC
MODULE
MODULE
PIN DESCRIPTIONS
Name
1/0
Definition
Name
1/0
Definition
A11-AOI
PA2-PAO
BIO
OUT
External address bus. 1/0 port address
multiplexed over PA2-PAO.
External polling input for bit test and jump
operations.
System clock output, 1/4 crystal ClKIN
frequency.
16-bit data bus.
Oata enable indicates the processor
accepting input data on 015-00.
Interrupt.
MC/MP
IN
Memory mode select: High selects microcomputer, low selects microprocessor mode.
Memory enable indicates that
015-00 will accept external memory instruction.
Reset used to initialize device.
Power.
Ground.
Write enable indicates valid data on 015-00.
Crystal input.
Crystal input or external clock input.
IN
ClKOUT
OUT
015-00
OEN
1/0
OUT
INT
IN
MEN
OUT
RS
VCC
VSS
WE
X1
X2/ClKIN
IN
IN
IN
OUT
IN
IN
© 1992 Microchip Technology Inc.
DS21037B-2
6-10
DSP320C10
ARCHITECTURE
The DSP320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate
spaces, permitting a full overlap of the instruction fetch
and execution. The DSP320 family's modification of the
Harvard architecture allows transfers between program
and data spaces, thereby increasing the flexibility of the
device. This modification permits coefficients stored in
program memory to be read into the RAM, eliminating
the need for a separate coefficient ROM. It also makes
available immediate instructions and subroutines based
on computed values.
Program Memory Expansion
The DSP320C10 is equipped with a 1536-word ROM
which can be mask-programmed at the factory with a
customer's program. It can also execute from an additional 2560 words of off-chip program memory at full
speed. This memory expansion capability is especially
useful for those situations where a customer has a
number of different applications that share the same
subroutines. In this case, the common subroutines can
be stored on-Chip while the application specific code is
stored off-chip.
The DSP 320C1 0 can operate in either of the following
memory modes via the MC/MP pin:
The DSP320C10 utilizes hardware to implement functions that other processors typically perform in software.
For example, this device contains a hardware multiplier
to perform a multiplication in a single 122ns cycle. There
is also a hardware barrel shifter for shifting data on its
way into the ALU. Finally, extra hardware has been
included so that auxiliary registers, which provide indirect data RAM addresses, can be configured in an auto
increment/decrement mode for single-cycle manipulation of data tables. This hardware-intensive approach
gives the design engineer the type of power previously
unavailable on a single chip.
Microcomputer Mode (MC)-Instruction addresses 01535 fetched from on-chip ROM. Those with addresses
1536-4095 fetched from off-chip memory at full speed.
Microprocessor Mode (MP)-Full speed execution from
all 4096 off-chip instruction addresses.
The ability of the DSP320C10 to execute at full speed
from off-chip memory provides important benefits:
Easier prototyping and development work than is
possible with a device that can address only onchip ROM
Purchase of a standard off-the-shelf product rather
than a semi-custom mask-programmed device
Ease of updating code
Execution from external RAM
Downloading of code from another microprocessor
Use of off-chip RAM to expand data storage
capability
32-bit ALUlAccumulator
The DSP320C1 0 contains a 32-bit ALU and accumulator that support double-precision arithmetic. The ALU
operates on 16-bit words taken from the data RAM or
derived from immediate instructions. Besides the usual
arithmetic instructions, the ALU can perform Boolean
operations, providing the bit manipulation ability required of a high-speed controller.
Input/Output
Shifters
The DSP320C 1O's 16-bit parallel data bus can be utilized to perform I/O functions at burst rates of 65 million
bits per second. Available for interfacing to peripheral
devices are 128 input and 128 output bits consisting of
eight 16-bit multiplexed input ports and eight 16-bit
multiplexed output ports. In addition, a polling input for
bit test and jump operations (BIO) and an interrupt pin
(INT) have been incorporated for multi-tasking.
A barrel shifter is available for left-shifting data 0 to 15
places before it is loaded into, subtracted from, or added
to the accumulator. This shifter extends the high-order
bit of the data word and zero-fills the low-order bits for
two's complement arithmetic A second shifter left-shifts
the upper half of the accumulator 0, 1, or 4 places while
it is being stored in the data RAM. Both shifters are very
useful for scaling and bit extraction.
Interrupts and Subroutines
16 X 16-bit Parallel Multiplier
The DSP320C10 contains a four-level hardware stack
for saving the contents of the program counter during
interrupts and subroutine calls. Instructions are available for saving the DSP320C 1O's complete context. The
instructions, PUSH stack from accumulator, and POP
stack to accumulator permit a level of nesting restricted
only by the amount of available RAM. The interrupts
used in the DSP320C10 are maskable.
The DSP320C10's multiplier performs a 16 x 16-bit,
two'S complement multiplication in one 122ns instruction cycle. The 16-bit T Register temporarily stores the
multiplicand; the P Register stores the 32-bit result.
Multiplier values either come from the data memory or
are derived immediately from the MPYK (multiply immediate) instruction word. The fast on-chip multiplier allows
the DSP320C10 to perform such fundamental operations as convolution, correlation, and filtering at a very
high rate.
08210378-3
© 1992 Microchip Technology Inc.
6-11
DSP320C10
INSTRUCTION SET
The DSP320Cl0's comprehensive instruction set supports both numeric-intensive operations, such as signal
processing, and general purpose operations, such as
high-speed control. The instruction set, explained in
Tables 1 and 2, consists primarily of single-cycle singleword instructions, permitting execution rates of up to
eight million instructions per second. Only infrequently
used branch and I/O instructions are multicycle.
Indirect Addressing
Indirect addressing forms the data memory from the
least significant eight bits of one of two auxiliary registers, ARO and AR1. The auxiliary register pOinter (ARP)
selects the current auxiliary register. The auxiliary
registers can be automatically incremented or decremented in parallel with the execution of any indirect
instruction to permit single-cycle manipulation of data
tables. The instruction format for indirect addressing is
as follows:
The DSP320Cl 0 also contains a number of instructions
that shift data as part of an arithmetic operation. These
all execute in a single cycle and are very useful for
scaling data in parallel with other operations.
1514131211 109 8
Three main addressing modes are available with the
DSP320Cl0 instruction set: direct, indirect, and immediate addressing.
Direct Addressing
Bit7 = 1 defines indirect addressing mode. The opcode
is contained in bits 15through 8. Bits 7 through 0 contain
indirect addressing control bits.
Bit 3 and bit 0 control the Auxiliary Register Pointer
(ARP). If bit 3 = 0, then the content of bit 0 is loaded into
the ARP. If bit 3 = 1, then content of ARP remain
unchanged. ARP = 0 defines the contents of ARO as
memory address. ARP = 1 defines the contents of ARl
as memory address.
Bit 5 and bit 4 control the auxiliary registers. If bit 5 = 1,
then the ARP defines which auxiliary register is to be
incremented by 1. Ifbit4 = 1, thentheARP defines which
auxiliary register is to be decremented by 1. If bit 5 or
bit 4 are zero, then neither auxiliary register is incremented or decremented. Bits 6, 2 and 1 are reserved
and should always be programmed to zero.
1514131211 10 9 8 7 6 543 2 1 0
OPCODE
0
2 1 0
I D N
A
1 0 N E A 0 0 R
C C R
P
OPCODE
In direct addressing, seven bits of the instruction word
concatenated with the data page pointer form the data
memory address. This implements a paging scheme in
which the first page contains 128 words and the second
page contains 16 words. In a typical application, infrequently accessed variables, such as those used for
servicing an interrupt, are stored on the second page.
The instruction format for direct addressing is shown
below.
7 6 5 4 3
DMA
Bit 7 = 0 defines direct addressing mode. The opcode is
contained in bits 15 through 8. Bits 6 through 0 contain
data memory address.
Indirect addressing can be used with all instructions
requiring data operands, except for the immediate operand instructions.
The seven bits of the data memory address (DMA) field
can directly address up to 128 words (1 page) of data
memory. Use of the data memory page pointer is
required to address the full 144 words of data memory.
Immediate Addressing
The DSP320Cl 0 instruction set contains special "immediate" instructions. These instructions derive data from
part of the instruction word rather than from the data
RAM. Some very useful immediate instructions are
multiply immediate (MPVK), load accumulator immediate (LACK), and load auxiliary register immediate (LARK).
Direct addressing can be used with all instructions
requiring data operands except for the immediate operand instructions.
DS21037B-4
© 1992 Microchip Technology Inc.
6-12
DSP320C10
INSTRUCTION SET SUMMARY
TABLE 1 -INSTRUCTION SYMBOLS
Symbol
Meaning
ACC
D
I
K
PA
R
S
X
Accumulator
Data memory address field
Addressing mode bit
Immediate operand field
3-bit port address field
1-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field
TABLE 2 - ACCUMULATOR INSTRUCTIONS
Mnemonic
ABS
ADD
ADDH
ADDS
AND
LAC
LACK
OR
SACH
SACL
SUB
SUBC
SUBH
SUBS
XOR
ZAC
ZALH
ZALS
Description
Number of
Cycles Words
Absolute value of accumulator
Add to accumulator with shift
Add to high-order accumulator bits
Add to accumulator with no sign
extension
AND with accumulator
Load accumulator with shift
Load accumulator immediate
OR with accumulator
Store high-order accumulator
bits with shift
Store low-order accumulator bits
Subtract from accumulator
with shift
Conditional subtract (for divide)
Subtract from high-order
Subtract from accumulator with
no sign extension
Exclusive OR with accumulator
Zero accumulator
Zero accumulator and load
high-order bits
Zero accumulator and load
low-order bits with no sign
extension
OpCode • Instruction Register
15 14131211 10 9
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
© 1992 Microchip Techriology Inc.
1
1
1
8
7
6
5
4
'3
1
1
I
I
I
0
0
0
1 0
D
D
D
I
I
E
~S----+
0
0
0
0
0
0
0
1
1
0
0
1
~S----+
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
1
0
0
~X----+
0
0
E
E
E
E
E
I
I
E
E
2 1
D
D
j
D
D
D
j
j
j
j
E
0
1
0
0
1
1
I
1
I
0
E
D
1 0
D
1
0
I
E
0
E
0
0
j
j
I
I
I
E
j
K
D
D
0
0
1
E
j
j
E
E
0
0
0
I
I
~S----+
0
0
j
j
)
)
0
1
j
j
DS21037B-5
6-13
DSP320C10
INSTRUCTION SET SUMMARY (CONT.)
TABLE 2 (CONT.) - AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
LAR
LARK
LARP
LDP
LDPK
MAR
SAR
OpCode - Instruction Register
Number of
Mnemonic
Description
Cycles Words
Load auxiliary register
Load auxiliary register immediate
Load auxiliary register
pointer immediate
Load data memory page pointer
Load data memory page pointer
immediate
Modify auxiliary register and pointer
Store auxiliary register
15 14 13 12 11 10 9
8
7
6
I
E
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
R
R
0
1
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
0
I
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
0
0
0
0
0
0
R
I
E
I
E
4
3 2 1
0
0
D -----7
K -----7
0 0 0 K
0
0
D -----7
0 0 0 K
5
E
E
0
D -----7
D -----7
TABLE 2 (CONT.) - BRANCH INSTRUCTIONS
B
Description
Cycles Words
Branch unconditionally
2
2
BANZ Branch on auxiliary register
not zero
BGEZ Branch if accumulator;;, 0
2
2
2
BGZ
Branch if accumulator> 0
2
2
BIOZ
Branch on BIO = 0
BLEZ
BLZ
BNZ
BV
BZ
Branch if accumulator ~ 0
Branch if accumulator < 0
Branch if accumulator", 0
Branch on overflow
Branch if accumulator = 0
2
2
2
2
2
2
2
2
2
2
2
2
2
CALA
Call subroutine from accumulator
2
1
CALL
Call subrou1ine immediately
2
2
RET
OpCode - Instruction Register
Number of
Mnemonic
Return from subroutine or
interrupt routine
2
1
15 14 13 12 11 10 9
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
DS21037B-6
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
E
0
E
1
E
1
E
0
E
1
E
1
E
1
E
0
E
1
E
E
1
8
7
6
5
4
3 2 1
0
1 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
0 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
1 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
0 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
0 0 0 0 0 Q0 0 0
BRANCH ADDRESS-----7
1 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
0 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
0 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
1 0 0 b 0 o 0 0 0
BRANCH ADDRESS-----7
1 0 0 0 0 o 0 0 0
BRANCH ADDRESS-----7
1 1 0 0 0 1 1 0 0
o
0 0 0 0 0
0 0
BRANCH ADDRESS-----7
1 1 0 0 0 1 1 0
0
1
© 1992 Microchip Technology Inc.
6-14
DSP320C10
INSTRUCTION SET SUMMARY (CONT.)
TABLE 2 (CONT.) - T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
Mnemonic
OpCode - Instruction Register
Number of
Description
Cycles Words
APAC Add P register to accumulator
LT
Load T register
LTA
LTA combines LT and APAC
into one instruction
LTD combines LT, APAC, and
LTD
DMOV into one instruction
MPY Multiply with T register, store
product in P register
MPYK Muttiply T register with immediate
operand; store product in P register
PAC
Load accumulator from P register
SPAC Subtract P register from
accumulator
15 14131211 10 9
8
7
6
5
4
3 2 1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
0
1
0
0
1
I
I
0
E
1 1 1 1
D ----+
D ----+
1
1
0
1
1
0
1
0
1
1
I
E
D ----+
1
1
0
1
1
0
1
1
0
1
I
E
D ----+
1
1
1
0
0
E
1
1
1
1
0
0
1
1
1
1
1
1
E
K
1
1
1
1
1
1
1
1
1
1
0
0
)
0
0
0
1
1 1
0 0
1
0
0
0
TABLE 2 (CONT.) - CONTROL INSTRUCTIONS
Mnemonic
DINT
EINT
LST
NOP
POP
PUSH
ROVM
SOVM
SST
OpCode - Instruction Register
Number of
Description
Disable interrupt
Enable interrupt
Load status register
No operation
POP stack to accumulator
PUSH stack from accumulator
Reset overflow mode
Set overflow mode
Store status register
Cycles Words
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
8
7
6
5
4
3 2 1
0
1
1
1
1
1
1
1
1
0
1
1
I
1
1
1
1
1
I
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
D
0
1
1
1
1
D
E
0
0
0
0
0
E
0
0
0
1
----+
0
1
1
0
0
0
0
0
1
1
0
1
0
1
1
----+
TABLE 2 (CONT.) - 110 AND DATA MEMORY OPERATIONS
Mnemonic
OpCocIe - Instruction Register
Number of
Description
DMOV
IN
OUT
TBLR
Copy contents of data memory
Input data from port
Output data to port
Table read from program
memory to data RAM
TBLW Table write from data RAM
to program (external only)
Cycles Words
15 14 13 12 11 10 9
8
7
6
5
4
3 2 1 0
1
2
2
3
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
1
0
1
0
0 0 1
+- PA -+
+- PA -+
1 1 1
I
I
I
I
,
,
D
D
D
D
3
1
0
1
1
1
1
1
I
E
0 ----+
0
1
E
E
----+
----+
----+
----+
OS21037B-7
© 1992 Microchip Technology Inc.
6-15
DSP320C10
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings'
"Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and
functional operation of this device at these conditions is
not implied - operating ranges are specified in Standard
Conditions. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Over specified temperature range (unless otherwise
noted)"
Supply voltage, Vee ............................................. -0.3V to 7V
All input voltages ........................................ -0.3V to 7V
Output voltage ............................................ -0.3V to 7V
Continuous power dissipation:
Data labeled "typical" is presented for design guidance
only and is not guaranteed.
DSP320Cl0 (0° to +70°C) ................................... 0.3W
DSP320Cl01 (-40° to +85°C) ............................. 0.36W
DSP320Cl0-25 (0° to +70°C) ............................ 0.35W
DSP320Cl01-25 (-40° to +85°C) ......................... OAW
Air temperature range above operating device:
- Commercial ......................................... O' C to 70'
- Industrial ........................................... -40' C to 85'
Storage Temperature Range .............. -55' C to 150'
Junction Temperature (TJ) ................................ 165·
C
C
C
C
DC CHARACTERISTICS
Characteristics
'Vcc = 5V, TA = 25' C
DSP320Cl0
DSP320Cl0-14 DSP320Cl0-25 DSP320Cl0-32
Unit
Conditions
Min Nom' Max Min Nom' Max Min Nom' Max Min Nom' Max
Supply voltage, Vcc
4.5
Supply voltage, Vss
-
High-level input voltage, VIH
- All inputs except ClKIN
-ClKIN
Low-level input voltage, VIL (all inputs)
High-level output voltage VOH
5.0
5.5
4.5
0
-
2.0 .65Vcc -
-
-
Vcc-A 2.4 -
5.0
5.5
4.5
5.0
5.5
V
0
-
-
0
-
V
2.0
.65Vc
-
-
-
V
V
0.8
-
-
0.8
-
-
0.8
V
-
Vcc-.
2.4
-
-
-
-
Vcc-.
2.4
-
-
-
-
V
V
IOH = 20J,tA
IOH = 300J,tA
10L = 2mA
5.0
5.5
4.5
-
0
-
-
-
2.0
.65Vc<
-
-
-
-
0.8
-
-
-
Vcc-A 2.4 -
2.0 .65Vcc -
low-level output voltage, VOL
-
-
0.4
-
-
0.4
-
-
0.4
-
-
0.4
V
Off-state output current, loz
-
-
20
-20
-
-
-
-
20
-20
-
-
20
-20
-
-
20
-20
~A
~A
Input current, Ii
-
-
±50
-
-
±50
-
-
±50
-
-
±50
~A
Supply current, Icc
(tested w/clocks running & part in reset)
-
-
50
-
-
50
-
-
55
-
-
65
mA
-
25
t5
-
-
25
15
-
-
25
15
-
-
25
15
-
pF
pF
25
10
-
Input capacitance, CI
- Data bus
- All others
-
-
Vcc = 5.5V
Va = Vcc - .4V
Vcc = 5.5V
f= 1MHz,
Output capacitance, Co
- Data bus
- All others
all other pins OV
-
-
-
-
25
10
-
DS21037B-8
-
25
10
-
-
25
10
-
pF
pF
© 1992 Microchip Technology Inc.
6-16
DSP320C10
PARAMETER MEASUREMENT INFORMATION
FIGURE 2 • TEST LOAD CIRCUIT
V=2.14V
From output{L= B70 ohms
under test
Test Point
~
CL= 100pF
TTL Load Condition
FIGURE 3 . AC TIMING VOLTAGE REFERENCE LEVELS
b. Outputs, TTL compatible
a. Inputs, TTL compatible
2.00V
-
O.BOV -
VIH (min.)
2.00V
-
r-- " --
~ VIL (max.)
D.BOV
-
~ VOL (max.)
r-- " --
VOH (min.)
D521 0378-9
© 1992 Microchip Technology Inc.
6-17
DSP320C10
CLOCK
The DSP320C1 0 can use either its internal oscillator or
an external frequency source for a clock.
INTERNAL CLOCK OPTION
The internal oscillator is enabled by connecting a crystal
across X1 and X2/CLKIN (See Figure 1) . The frequency
of CLKOUT is one-fourth the crystal fundamental frequency.
FIGURE 1 -INTERNAL CLOCK
OPTION
C1 ~
The crystal should be fundamental mode, and parallel
resonant, with an effective series resistance of 30 ohms,
a power dissipation of 1mW, and be specified at a load
capacitance of 20pF.
EXTERNAL CLOCK OPTION
An external frequency source can be used by injecting
the frequency directly into X2/CLKIN with X1 left unconnected.
The external frequency injected must conform to the
specifications listed in the table below.
CLOCK FREQUENCIES
Characteristics
DSP320C10 Crystal frequency
DSP320C10-14 Crystal frequency
DSP320C1 0-25 Crystal frequency
DSP320C10-32 Crystal frequency
C1,C2
Sym
Min
Nom
Max
Unit
Temperature
Range Conditions
fx
fx
fx
fx
6.7
6.7
6.7
6.7
-
20.5
14.4
25.6
32.8
MHz
MHz
MHz
MHz
pf
I, C
I, C
I, C
I, C
I,C
-
08210378-10
10
-
© 1992 Microchip Technology Inc.
6-18
DSP320C10
CLOCK (CONT.)
CLOCK AC CHARACTERISTICS
TA (Commercial) = 0' to 70' C
TA (Industrial) = -40' to 85' C
vcc = 5V + 10%, Vss = OV
Timing requirements/Switching Characteristics over Recommended Operating Conditions
DSP320Cl0
Characteristics
DSP320Cl0·14
Sym
Min
Norr
Max
Min
Nom
Max
Te(MC)
DSP320Cl0-25
DSP320Cl0·32
Min
Nom
Max
Min
Nom
Max
Unit Conditions
48.78
-
150
69.50
-
150
39
-
150
30.5
-
150
Rise lime mast. elk in. Tr(MC)
-
5
10'
-
5
W
-
4
S'
-
3
6'
ns
TI(MC)
-
5
10'
-
5
10'
-
4
8'
-
3
6'
ns
Tw(MCl)
14'
20
-
14'
20
-
12'
16
-
8'
12
-
ns
high, Te(MC) = 70ns
Tw(MCH)
14'
-
14'
-
12'
16
-
8'
12
-
ns
Pulse duro mast elk
Tw(MCP] 0.4Te(C)'
Master elk cycle time
Fall time mast. elk in.
ns Note 1
Pulse duro mast. elk
low, Te(MC) = 70ns
Pulse duro mast elk
ClKOUT cycle time
Te(C)
195.12
ClKOUT rise time
Tr(C)
ClKOUT fall time
TI(C)
-
Pis. dur., ClKOUT low Tw(Cl)
Pls.dur., ClKOUT high Tw(CH)
20
-
-
2n.80
8
-
92
-
90
-
-
-
60
10
10
20
0.6Tc(C)' 0.4Tc(C)'
-
0.6Tc(c)' O.45TClC)' 156
-
-
10
-
74
129
-
72
-
60
10
-
10
8
131
8
0.55Tc(C)' O.45Tc(C)' -
-
122
-
-
4
7
-
-
57
-
-
50
10
0.55Tc(C)' ns
-
ns
ns
54
-
-
50
ns
ns
ns See Fig 2
ns
Delay time to ClKINi
to ClKOUT-l. (Note 2) Td{MCC)
Note:
10
(1) TC(C) is the cycle time of ClKOUT. i.e., 4*TC(MC) (4 times ClKIN cycle time if an external oscillator is used)
(2) * These values were derived from characterization data and are not tested or guaranteed.
CLOCK TIMING
Q3
Q4
Ql
Q2
X2/ClKIN
(DSP internal
clock)
~---Tw(CH)-----J
ClKOUT
TR(C)
J-.---Tw(Cl) - - - - - J
j4----------Tc(C)----------l
* TD(MCC) and TW(MCP) are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage
of 2.0 volts, unless otherwise noted.
D8210378-11
© 1992 Microchip Technology Inc.
6-19
DSP320C10
MEMORY AND PERIPHERAL INTERFACE TIMING
MEMORY AND PERIPHERAL INTERFACE· AC CHARACTERISTICS
Over recommended operating conditions
Max
Unit
Conditions
-
38
ns
See Figure 2
1/4Tc(C) -5'
-
1I4Tc(C) +12
ns
Td3
-8'
-
12
ns
Delay time CLKOUT.). to DEN.).
Td4
1I4Tc(C) -5'
-
1I4Tc(C) +12
ns
Delay time CLKOUT.). to DENi
Td5
-8'
-
12
ns
Delay time CLKOUT.). to WE.).
Td6
1I2Tc(C) -5'
-
1I2Tc(C) +12
ns
Delay time CLKOUT.). to WEi
Td7
-8'
-
12
ns
Delay time CLKOUT.). to data bus OUT valid
Td8
-
1I4Tc(C) +40
ns
Time after. CLKOUT.). that data bus starts to be driven
Td9
1I4Tc(C) - 5'
-
ns
TIme after CLKOUT.). that data bus stops being driven
Tdl0
-
1I4Tc(C) +30'
ns
Tv
1I4Tc(C) - 10
-
ns
Delay time DENi, MENi and WEi from RS.).
Td11
-
-
Tc(C) + 50'
ns
Setup time data bus valid prior to CLKOUT .).
Tsu(o)
38
-
-
ns
Hold time data bus held valid after CLKOUT.).
Th(O)
0
-
-
ns
Address bus setup time prior to MEN.). or DEN.).
Tsu(A-MO)
1I4Tc(C) -35
-
-
ns
Address bus hold after WEi, MENi or DENi
Th(A-WMO)
5
-
-
ns
Address bus setup time prior to WE.).
Tsu(A-WE)
1I2Tc(C) -34
-
-
ns
Data bus setup time prior to WE.).
Tsu(O-WE)
1I4Tc(C) -32
-
-
ns
Data bus hold after WEi
Th(O-WE)
1I4Tc(C) -18
-
-
ns
External memory access time
Tace
-
-
Tc(C) - 69
ns
External memory output enable time
Toe
-
-
314 Tc(C) - 40
ns
Characteristics
Sym
Min
Typ
Delay time CLKOUT.). to address bus valid (see note)
Tdl
10'
Delay time CLKOUT.). to MEN.).
Td2
Delay time CLKOUT.). to MENi
Data bus OUT valid after CLKOUT .).
-
'These values were derived from characterization data and are not tested.
Note:
1. Address bus will be valid upon WEi, DENi, or MENi.
2. Data may be removed from the data bus upon MENi or DENi preceding CLKOUT.).
D521 0379-12
© 1992 Microchip Technology Inc.
6-20
DSP320C10
MEMORY AND PERIPHERAL INTERFACE TIMING (CONT.)
MEMORY READ TIMING DIAGRAM
Te(C)
CLKOUT
MEN
Tsu(A-MO)
ADDRESS BUS VALID
A11-AO
015-00
1___-'>>--------------...,~
Tsu(O)
.!,
INSTRUCTION IN VALID
'l
TH (O)
~--------
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
DS21037B-13
© 1992 Microchip Technology Inc.
6-21
DSP320C10
INSTRUCTION TIMING DIAGRAMS (CONT.)
TBlR INSTRUCTION TIMING DIAGRAM
CLKOUT
MEN
A11-AO
D15-DO
Legend:
1.
2.
3.
4.
5.
6.
TBlR INSTRUCTION PREFETCH
DUMMY PREFETCH
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
7.
8.
9.
10.
ADDRESS BUS VALID
ADDRESS BUS VALID
INSTRUCTION IN VALID
INSTRUCTION IN VALID
11. DATA IN VALID
12. INSTRUCTION IN VALID
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
TBlW INSTRUCTION TIMING DIAGRAM
CLKOUT
MEN
A11-AO
WE
D15-DO
Legend:
1.
2.
3.
4.
5.
6.
TBlW INSTRUCTION PRE FETCH
DUMMY PRE FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
ADDRESS BUS VALID
7.
8.
9.
10.
11.
ADDRESS BUS VALID
INSTRUCTION IN VALID
INSTRUCTION IN VALID
DATA OUT VALID
INSTRUCTION IN VALID
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
DS21 0378-.14
© 1992 Microchip Technology Inc.
6-22
DSP320C10
INSTRUCTION TIMING DIAGRAMS (CONT.)
IN INSTRUCTION TIMING DIAGRAM
CLKOUT
A11 -AO
D15- DO
Legend:
1. IN INSTRUCTION PREFETCH
2. NEXT INSTRUCTION PREFETCH
3. ADDRESS BUS VALID
4. PERIPHERAL ADDRESS VALID
5. ADDRESS BUS VALID
6. INSTRUCTION IN VALID
7. DATA IN VALID
8. INSTRUCTION IN VALID
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
OUT INSTRUCTION TIMING DIAGRAM
CLKOUT
MEN
A11-AO
WE
D15-DO
Th(D-WE)
Legend:
1. OUT INSTRUCTION PREFETCH
2. NEXT INSTRUCTION PREFETCH
3. ADDRESS BUS VALID
4. PERIPHERAL ADDRESS VALID
5. ADDRESS BUS VALID
6. INSTRUCTION IN VALID
7. DATA OUT VALID
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts,
unless otherwise noted.
© 1992 Microchip Technology Inc.
DS21037B-15
6-23
DSP320C10
RESET (RS) TIMING
RESET TIMING AC CHARACTERISTICS
Timing requirements over recommended operating conditions
Characteristics
Sym
Min
Tsu(R)
38
-
-
ns
RS pulse duration
Tw(R)
5Tc(C)
-
-
ns
Delay time DENI, WEI, and
Td11
-
-
Tc(C) + 50'
ns
Tdis(R)
-
-
3/4Tc(C) + 120'
ns
Reset (RS) setup time prior to
CLKOUT. See notes 1-4.
DSP320C10-32
Nom
Max
Unit
Conditions
See Figure 2
MENI from RSJData bus disable time after RS
Note: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
'These values were derived from characterization data and are not tested.
FIGURE 4 • RESET TIMING
ClKOUT
015-00
rBa::
Tdis(R)
<
~a In from
---~~-------- -----~ pc Addr (0) ~Addr(PC+l)
Data In from
Data shown relative to WE
Address
Bus
==:x
AB=PC XAB=PC+l
AB = Address Bus
X=~:
AB=PC=O
~+1
----------'
Notes:
1. RS forces DEN. WE, and MEN high and tristates data bus DO through D15. AB outputs (and program counter) are
synchronously cleared to zero after the next complete ClK cycle from ASJ,.
2.
RS must be maintained for a minimum of five clock cycles.
3.
Resumption of normal program will commence after one complete ClK cycle from RSt.
4.
Due to the synchronizing action on AS, time to execute the function can vary dependent upon when RSt or RSJ, occur in the
ClK cycle.
5.
Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
6. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise
noted.
7.
During a write cycle, RS may produce an invalid write address.
DS210378-16
© 1992 Microchip Technology Inc.
6-24
DSP320C10
INTERRUPT (INT) TIMING
INTERRUPT TIMING AC CHARACTERISTICS
Timing requirements over recommended operating conditions
Characteristics
Sym
-
Min
- These values are not tested
Nom
Max
Unit
-
15-
ns
Pulse duration INT
Tw(INT)
Tc(C)
-
-
ns
Setup time INT.1 before CLKOUT.1
Tsu(INT)
38
-
-
ns
Fall time INT
Tf(INT)
-
-
Conditions
-
INTERRUPT TIMING DIAGRAM
CLKOUT
~JL ~I--TSU-(INT-)----J/
INT
TF(INT)
(
E
...
----Tw(INT) -----<.~
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of
2.0 volts, unless otherwise noted.
1/0 (810) TIMING
1/0 (810) AC CHARACTERISTICS
Timing requirements over recommended operating conditions
Characteristics
-
Sym
Min
Nom
- These values are not tested
Max
Unit
Tf(IO)
-
-
15-
ns
Pulse duration 810
Tw(IO)
Tc(C)
-
-
ns
Setup time 810.1 before CLKOUT .1
Tsu(IO)
38
-
-
ns
Fall time 810
-
Conditions
1/0 (810) TIMING DIAGRAM
\I...-----J/
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of
2.0 volts, unless otherwise noted.
DS21037B-17
© 1992 Microchip Technology Inc.
6-25
DSP320C10
SALES AND SUPPORT
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory
or the listed sales offices.
PART NUMBERS
DSP320C10· 32 I / P
~
I,
Package:
P
L
Temperature
Range:
Blank
0 to 70° C
-40 to 85° C
Frequency:
14
14.4 MHz
20.5 MHz
25.6 MHz
32.8 MHz
25
32
'---------1:
Plastic DIP
PLCC
Device
DSP320C10 Digital Signal Processor
© 1992 Microchip Technology Inc.
D821 0378-18
6-26
Microchip
SECTION 7
QUALITY AND RELIABILITY
Quality Without Compromise ................................................................................................................. 7Plastic Package Reliability .................................................................................................................... 7-
1
9
DS00018E
© 1992 Microchip Technology Inc.
7-i
Microchip
DS00018E
© 1992 Microchip Technology
7-ii
Microchip
Quality Without Compromise
A more advanced process uses minimum dimensions of
111m, 250A gate oxide thickness, polycide gate and LDD
junction for the N-channel devices. A double level metal
modules can be added to both processes.
A CORPORATE COMMITMENT
Raising the quality level of Microchip's products and
services is a performance alliance built with customers
and suppliers.
All of these devices utilize a proprietary passivation
suitable for a wide variety of package types. Microchip's
processes have been developed with manufacturability,
predictability, and reliability as their primary goals.
Total quality improvement and quality awareness is
powered by company-wide participation.
Meeting a customer's expectations is where quality
commitment begins. The resolve to continuously improve never ends.
EEPROM
Microchip's CMOS floating gate EEPROM technology
produces a non-volatile memory cell by storing or removing charge from the floating gate. Charge is transferred bidirectionally to the floating gate by FowlerNordheim tunneling through a sub-1 0 nm oxide over the
drain of the transistor. This technology produces a
memory cell with a typical endurance of > 106 cycles.
THE CHALLENGE OF COMPLEXITY
Integratina an Ideal
Microchip's quality programs and business plan are
vertically integrated and touch all levels of the company.
From the top down, the President and CEO actively
leads programs to ensure continuous improvement is a
perpetual process. Quality teams work from the bottom
up to improve performance at every department level.
Incorporating quality improvement objectives into the
business plan creates a unity of purpose and mandates
that the two merge as one measurement.
This technology uses a non-volatile memory cell which
stores charge on a self aligned floating gate. Electrons
are provided to the floating gate via hot electron injection
from the drain depletion region. Each byte can typically
be programmed in 1,00 microseconds, and can retain
that data for more than 10 years with unlimited reads.
Programming is done off-line using an EPROM programmer. This technology is available in a wide variety
of plastic packages for one time programming (OTP), or
in windowed packages. Block erasing is accomplished
with a high intensity UV source through the package
window. Windowed parts can be erased and reprogrammed more than 100 times.
Determination to be the Best
Through statistical management and the use of statistical tools, a framework is built for becoming a continuously improving supplier. These programs are the
foundation for success.
PROCESS TECHNOLOGY
All the products manufactured at Microchip make use of
a common N-Well CMOS baseline process to which
modules are added in order to create the specific functions required by the product (EEPROM, Microcontroller,
Logic and EPROM).
Microcontroller and Logie
Logic products are built on both of Microchip's
common processes and their derivatives. These
products have process modules for production of
ROM, Analog, EPROM, and EEPROM in addition to
basic logic circuitry.
The baseline process, which has been in Manufacturing
for the last 5 years, uses minimum dimensions of 211m,
360A gate oxide thickness, W doped polysilicon gates
and arsenic implanted source-drain diffusions for the Nchannel devices.
©
1992 Microchip Technology Inc.
DS00047C-1
7 -1
Quality & Reliability
QUALITY
Testing for Margin
Design for Quality and Reliability
Microchip conducts a product's initial test under stringent requirements. All quality assurance tests are run to
tighter limits than customer specifications. As part of an
outgoing quality assurance program, most products are
tested at leasttwo machine tolerances tighter than those
limits specified by the customer. Margin testing accounts for normal tolerances of any particular test system and provides the assurance that Microchip's products meet a customer's specifications.
Product reliability is designed into all Microchip processes and products. Design margins are established
to guarantee every product can be produced economically, error-free and within the tolerances of the manufacturing process. Design committee members representing manufacturing, engineering, quality and product
divisions ensure that exacting standards are met for
each specific product.
Variation from Expectation
Documentation and Procurement
Specifications
Microchip works to make variation from target as small
as possible. The better process is the one that holds the
narrowest dispersion. Presently Microchip uses electrical screens to help eliminate short term failures. The
long term program of total quality improvement emphasizes continuous improvement.
Microchip's documentation control program assures the
correct and current document always is available at the
point of use. Active documents are revision coded and
serialized. Procurement specifications bear the same
requirements. These document control procedures,
which are common in the industry for military and high
reliability products, are employed by Microchip, system
wide.
Individuals in all departments are encouraged to analyze the methods employed at their positions and formulate plans to improve performance. Because a
customer could receive part of every mistake, definitive
programs are continuously formulated at all working
levels, designed to eliminate mistakes and contain error.
In Line Controls and Process Assessment
Product integrity is assured by sampling and inspection
plans performed in line. This enables Microchip to
control and improve product quality levels as product
moves through the manufacturing operation. Microchip's
acceptance sampling plans in assembly emphasize the
attempt to eliminate defective product as it is discovered. Acceptance and sampling plans are based on
proprietary low fraction defective «1000ppm) quality
statistics.
OutgOing Quality
Quality Control samples all outgoing product from Microchip final testing. These samples measure in line
defect levels after screens have been applied. Root
cause analysis follows, initiating technical change to
effect continuous improvement.
RELIABILITY
To determine whether a process is within normal
manufacturing variation, statistical techniques are put to
work at selected process steps. In-process controls are
performed by operators in the wafer fabrication and
assembly operations. Operators take immediate corrective action if a process step is out of its control limit.
Through these in-line controls the true capability of a
process is generated. (See Appendix A - Controls)
Process Qualification
No priority is more important than the one where processes under which Microchip products are built operate
without fail. Engineers labor under strict guidelines to
ensure tests of sample lots are precise and reliable.
Exacting internal specifications demand every product
used to qualify a process endure an accelerated life test.
Microcontrollers, EPROMs, EEPROMs, and Logic
Products are stressed beyond normal use limits when
undergoing high temperature reverse bias, operating
life, and retention bake tests.
Control of Customer Quality is attained through a statistical program based on minimum defect capability
levels. These levels are defined as the error levels
associated with the circuit design and science limitations
of the chemistry and physics of processing.
Material controls prevent defective piece parts from
getting into the line. Microchip's assembly material
control sample plan is typical of the emphasis placed on
safeguards. (See Appendix B - Material Controls).
DS00047C-2
© 1992 Microchip Technology Inc.
7-2
Quality & Reliability
Package Qualification
The early failure rate (infant mortality) period starts from
initial operation (time To) and decreases as time goes
on.
Package qualification measures a component's abilityto
withstand extreme thermal and mechanical stress. All
products are stressed to military or high level industrial
specifications to ensure reliability.
Time T1 signifies the end of the infant mortality period.
The next phase of the curve occurs between time T 1 and
T2. This long period of time is distinguished by a nearly
constant and very low failure rate. After T2 is passed, the
failure rate starts to increase slowly. This last phase of
failure rate vs. time is known as the wear-out period.
Ongoing Sampling of Key Reliability
Variables
Microchip conducts accelerated mechanical tests, operating life tests and memory retention tests to explore
the many ways failures might occur. Data gleaned from
continuous testing is used to identify potential reliability
problems and for defining action courses to improve
product. Microchip's reliability knowledge is shared with
customers. This data is available for use in customer's
own quality and reliability improvement programs.
Temperature Dependency
RELIABILITY CONCEPTS
In order to establish failure rates in a reasonable time, it
is necessary to accelerate the incidence of the failure
modes. Higher environmental stress levels than those
encountered under normal conditions are needed. The
accelerating parameter most employed is junction temperature, although voltage and humidity, for example,
are also used. Higher temperatures are capable of
accelerating many common failure modes dramatically.
Definition
Arrhenius Equation
Reliability is the probability of a system or circuit performing its predefined function adequately under specific conditions for a given period of time. Thus, the
reliability of a microcircuit is a function of both stress
conditions and the time of operation.
A number of mathematical models were developed to
quantify the relationship between accelerated failure
rates and increased junction temperatures. The one
model most commonly used employs the Arrhenius
Equation. It is as follows:
The reliability (or probability of survival) range runs from
(no chance of survival) to 1 (no chance of failure).
Current microelectronic circuits are manufactured and
controlled to such tight specifications that reliability
figures for the total operation time approaching 1 (i.e.,
0.9999) are common. As a result, the complement of
reliability, or the failure probability, is more often quoted
in current literature.
J
~1
a
1
AF = e', where x= -EA - - K TN TA
AF = Acceleration Factor (non-dimensional)
e
= 2.718281828 ... (non-dimensional constant)
EA = Activation energy level (electron volts)
The failure rate is the rate atwhich failures occur on units
surviving to a specific number of hours of operation.
Failure rates per unit circuit-hour would generally be
very small. To avoid reporting such small numbers,
failure rates have been defined for greater circuit-hours.
One thousand circuit-hours is defined as one circuit
operating for one thousand hours, or 1,000 circuits
operating for 1 hour, etc. The numbers of circuit-hours
is the number of circuits multiplied by the number of
operation hours for each circuit.
k
= Boltzmann's constant = 8.6172 x 10
(electron-volts/degree Kelvin)
5
TN = Normal junction temperature (degrees Kelvin)
TA = Accelerated junction temperature (degrees
Kelvin)
Thus, the time to achieve a certain probability of failure
at time T1 under temperature TN can be compressed to
T 1divided by AF althe accelerated temperature, T A. Note
Two methods to define failure rate are commonly used:
* Percent failures per thousand circuit-hours
FIGURE 1: BATHTUB CURVE
* Absolute failures per 109 circuit-hours, or FITs.
Note that a failure rate of 0.0001 %/1 000 hours and 1 FIT
are equivalent numbers.
FAILURE RATE
\.....
Bathtub Curve: Failure Rate Over Time
The generic representational graph of failure rate vs.
time takes the shape of a bathtub curve. (Figure 1).
I
I
TO
T1
0001
TIME
,/
I
I
T2
~
DS00047C-3
© 1992 Microchip Technology Inc.
7-3
Quality & Reliability
Activation Energy Level
High Temperature Reverse Bias (HTRB)
AF, the dependent variable of the Arrhenius Equation is
a function of several variables. TN and TA are specified
for the situation under consideration. EA is a function of
the particular mode of failure, and can be viewed as the
minimum energy required for a particular failure to occur.
Microchip employs the High Temperature Reverse Bias
test to accelerate charge gain onto the floating gate due
to oxide defects or accelerate threshold shifts due to
ionic contamination. The test is conducted by putting the
device into a special test mode whereby 7.0 volts is
applied to all poly 2 structures with source, drain and
substrate held at ground. The test is conducted at
+ 150'C and is normally conducted for 1,000 hours with
readouts at 24, 168, 500 and 1,000 hours.
Activation energy levels in semiconductors generally
are in the 0.3 - 1.1 electron-volt range. Each failure
mode has its own activation energy. Some typical
examples are:
Retention Bake
FAILURE MECHANISM
~
Oxide/Dielectric Defects
0.3
The Retention Bake Test is performed to accelerate
data loss on floating gate devices. The test consists of
unbiased baking at elevated temperature. Usually the
test lasts for 1,000 hours at + 150'C. The failure
mechanism that is accelerated is charge leakage from a
stored element.
Chemical, Galvanic, or Electrolytic
0.3
Corrosion Silicon Defect
0.5
Electromigration
0.5 to 0.7
Broken Bonds
0.7
Lifted Die
0.7
Surface Related Contamination
1.0
Lifted Bonds (Au-AI Interface)
1.0
Charge Injection
1.3
0.6
Floating Gate Charge Loss
Hot Electron Trapping
-.06
Tunnel Dielectric Breakdown
0.13
Endurance Cycling
Endurance Cycling establishes the number of times a
device can be programmed and erased. Normally the
test is conducted at rated temperature conditions and is
followed by a retention bake.
Temperature Cycle
The Temperature Cycle test simulates stresses which
occur to systems during power up/power down sequences. The test is intended to reveal any deficiencies
resulting from thermal expansion mismatch of the die/
package structure. Normally the test is conducted by
cycling between -65'C and +150'C in an air ambient.
Duration for the test is typically 500 cycles for both
plastic and ceramic packages. Endpoint criteria are
both electrical and visual/mechanical.
A compromise value of 0.6 electron-volts is often used
when there are no specific a priori facts relating to the
failure modes being accelerated.
There is however, a continuous reliability program at
Microchip structured to validate EA values in use and to
categorize new failure mechanisms.
RELIABILITY TESTS
Thermal Shock
Operating Life Test
The Thermal Shock test is similar to the Temperature
Cycle test except that the ambient during cycling is
liquid-to-liquid. This stimulates rapid thermal environmental changes. The mechanisms accelerated are
identical to those in the Temperature Cycle test except
that the Thermal Shock test is a more accelerated test
with temperatures normally + 125'C to -55'C. The number of cycles are 500 for qualification testing.
The Operating Life Test is run under dynamic bias
conditions where inputs are clocked and outputs are
loaded in the same way as a typical application. The test
is conducted at high temperature to accelerate the
failure mechanisms. The normal temperature for the
test is + 125'C for 1,000 hours. Readouts occur at 24,
168, 500 and 1,000 hours. Early hour failures are
usually associated with manufacturing defects or otherwise marginal material. Longer term failures are
typically caused by metal migration, ionic contamination,
and oxide breakdowns.
Autoclave
The autoclave test determines the survivability of devices in molded plastic packages to a hot, humid environment. The test exposes unbiased, plastic packaged
devices to saturated steam at 121'C and 15 pounds per
square inch (one atmosphere) gauge pressure. The 168
or more hours of testing allows moisture to penetrate to
the die surface. Chemical corrosion of the die metallization may occur if ionic contaminants are present and
the die surface protection is deficient or damaged.
Charge leaks from floating devices usually happen
before a corrosion mechanism develops.
DS00047C-4
© 1992 Microchip Technology Inc.
7-4
Quality & Reliability
RELIABILITY TESTS (CO NT.)
QUALIFICATION PROGRAMS
Temperature Humidity Test
Qualifications guarantee changes to or new processes
and technologies are properly evaluated for reliability
performance.
The Temperature Humidity test determines the survivability of devices in molded plastic packages functioning
in a hot, humid environment. By convention, test conditions are 8S'C with 8S% relative humidity. The parts are
biased to lend themselves to electrochemical corrosion.
The duration of the test is usually 1,000 hours or more.
The test checks the adequacy of the die surface protection and the plastic's lack of ionic impurities. The applied
bias may be S volts on alternating pins or set up for
minimum power to reduce internal heating and consequent moisture evaporation on the device. Similar to the
Autoclave test, charge loss on floating gate devices is a
principle failure mechanism.
Reliability Monitoring
Microchip's reliability monitoring program is a comprehensive effort to measure the reliability of all process
families with strict regularity. The program strives to
improve performance through failure analysis and corrective action. Numerous screening procedures are
used and estimates of product life and expected failure
rates are provided.
Typical tests and frequencies include:
Quarterly Die Monitor on selected product for Dynamic Life
QUALIFICATION CATEGORIES
Retention Bake
Qualification is required for new design, major changes
in old design, process or material when either wafer
fabrication or package assembly operations are affected. Qualification applies to the following changes:
I.
New technology
II.
Start-up of Fab or Assembly
Endurance
HTRB
Periodic (weekly, monthly and quarterly) package
monitors to evaluate:
Mechanical stresses
III. Transfer of fab or assembly to another location
Alignment
IV. Major process changes:
Temperature and moisture stresses
V.
A.
Process scaling (shrink conversion)
Corrosion resistance
B.
Change in vendor or material source
Marking permanency
C.
New equipment that affects reliability
New device configurations:
A.
New structures
B.
New packaging material
C.
Design rule changes
D.
Existing package revision (dimensional or
layout)
DS00047C-5
© 1992 Microchip Technology Inc.
7-S
Quality & Reliability
APPENDIX A - IN LINE CONTROLS
CONTROLS - PLASTIC PACKAGE ASSEMBLY
Operation
Action
Sample Plan
Responsibility
Quality
Prod
Referenced
MIL-STD
Reject defectives
100% rescreen
per LTPD
10% sample
LTPD 10
-
X
X
-
Wafer Saw
Machine
Shut Down
One slice per lot
X
-
MIL-STD-883C
Method 2010
Die Attach
Machine
Shut Down
4X/LotlMachine
LTPD 15
X
-
N/A
Wire Bond
Machine
Shut Down
1% AQL each 1/2 shift
X
-
MIL-STD-883C
Method 2010
Post Wire Bond
Reject defectives
100% rescreen
per LTPD
LTPD 15
X
-
MIL -STD-883C
Method 2010
Mold Press
Machine
Shut Down
One sample 14 hrs
X
-
N/A
Die Plating
Reject defectives
100% rescreen
per LTPD
Every 4 hrs
LTPD 10
X
N/A
Trim and Form
Reject defectives
100% rescreen
per LTPD
Once/2 hrs
X
N/A
Reject defectives
100% rescreen
per LTPD
100% LTPD 2
Die Visual
External Visual and
Documentation
Verification
MIL-STD-883C
Method 2010
LTPD 10
X
X
DS00047C-6
MIL-STD-883C
Method 2010,
Method 2016
© 1992 Microchip Technology Inc.
7-6
Quality & Reliability
CONTROLS - CERAMIC PACKAGE ASSEMBLY
Operation
Action
Sample Plan
Responsibility
Quality
Die Visual
Reject defectives
100% rescreen
per LTPD
10% LTPD 10
Wafer Saw
Machine
Shut Down
Die Attach
-
Prod
Referenced
MIL-STD
X
X
-
MIL-STD-883C
Method 2010
One slice per lot
X
-
MIL-STD-883C
Method 2010
Machine
Shut Down
Non-destruct each 2 hrs
destruct each shift
X
-
MIL-STD-883C
Method 2010
Wire Bond
Machine
Shut Down
4X/shiftlmachine
X
-
MIL-STD-883C
Method 2010
Preseal Visual
Reject defectives
100% rescreen
per LTPD
100% LTPD 15
-
X
Package Seal
Machine
Shut Down
Environmental
Stress
Centrifuge
Temp Cycle
Machine
Shut Down
Fine Leak
Reject defectives
100% rescreen
per LTPD
Gross Leak
Lead Trim
External Visual and
Documentation
Verification
X
-
MIL-STD-883C
Method 2010
LTPD 15
X
-
N/A
LTPD 5
X
-
MIL-STD-883C
Method 2001
Method 1010
LTPD 5
X
-
MIL-STD-883C
Method 1014
Reject defectives
100% rescreen
per LTPD
LTPD5
X
-
MIL-STD-883C
Method 1014
Reject defectives
100% rescreen
per LTPD
100% LTPD 2
MIL-STD-883C
Method 2009
Reject defectives
100% rescreen
per LTPD
100% LTPD 2
84(0)
84(0)
© 1992 Microchip Technology Inc.
-
X
X
-
-
X
X
-
MIL-STD-883C
Method 2010,
Method 2016
DS00047C-7
7-7
Quality & Reliability
APPENDIX B - MATERIAL CONTROLS PACKAGE
MATERIALS CONTROLS - PLASTIC PACKAGE ASSEMBLY
Operation
Action
Sample Plan
Responsibility
Quality
Prod
Referenced
MIL-STD
Lead Frame
Reject defectives
100% rescreen
per LTPD
Visual, LTPD 2
Functional, LTPD 10
and material spec
X
-
N/A
Die Attach Epoxy
Reject
Functional, LTPD 15
and material spec
X
-
N/A
Gold Wire
Reject
Per material spec
X
N/A
Molding Compound
Reject
Spiral flow, 3X1lot
Functional, 1Xllot and
material spec
X
-
N/A
MATERIALS CONTROLS - CERAMIC PACKAGE ASSEMBLY
Operation
Action
Sample Plan
Responsibility
Quality
Prod
Referenced
MIL-STD
Base/Lead Frame
Reject 100%
rescreen per
LTPD
Visual, LTPD 10
Functional, LTPD 10
Bake test, LTPD 15
Dimensions, LTPD 50
and material spec
X
-
MIL-M-38510
Package
Reject 100%
rescreen per
LTPD
Visual, LTPD 10
Functional, LTPD 10
Bake test, LTPD 15
Dimensions, LTPD 50
Plating, LTPD 10
and material spec
X
-
MIL-M-38510
Preform
Reject
Visual, LTPD 10
Functional, LTPD 15
X
-
MIL-M-38510
Bond Wire
Reject
Per material spec
2 spools/lot
X
-
MIL-M-38510
Lid
Reject
Visual, LTPD 7
Functional, LTPD 10
and material spec
X
-
MIL-M-38510
DS00047C-8
© 1992 Microchip Technology Inc.
7-8
~.
Microchip
Plastic Package Reliability
OVERVIEW
FAILURE RATE CALCULATION
Microchip Technology Plastic products provide
competitive leadership in quality and reliability, with
demonstrated performance of less than 250 FITs (Failures in Time) operating life. The designed-in reliability
of Microchip Technology Plastic package products are
supported by ongoing reliability data monitors. This
document presents current data for your use - to provide
you with results you can count on.
Extended field life is simulated by using high ambient
temperature. In the semiconductor technology, high
temperatures dramatically accelerate the mechanisms
leading to component failure. Using performance
results at different temperatures, an activation energy is
determined using the Arrhenius equation. For each type
of failure mechanism, the activation energy expresses
the degree to which temperature increases the failure
rate.
The test descriptions included in this document explain
Microchip Technology's quality and reliability system,
and the product data demonstrate its results.
PRODUCT SCOPE
The activation energy values determined by Microchip
Technology agree closely with those published in the
literature. For complex CMOS devices in production at
Microchip Technology, an activation energy of 0.6 eV
has been shown to be most representative of typical
failures on operating life. By definition, failure is reached
when a device no longer meets the data sheet specifications as a direct result of the reliability test environment
to which it was exposed. Common failure modes for
CMOS integrated circuits are identified for each test
environment.
The subjects of this Product Reliability Bulletin are the
Plastic Packages of Microchip Technology's Product
Families: Microcontrollers, Serial and Parallel
EEPROMs and EPROMs.
The plastic product families have an early failure rate
(infant mortality) of less than .04%/1,000 hrs. and thus,
a production burn-in should not be necessary. For all
products shown, the early life failure rates are reported
separate from long term life.
The customer's quality requirements are Microchip
Technology's top priority: Ongoing customer feedback
and device performance monitoring drive Microchip
Technology's manufacturing and design process, leading
to continuing improvements in the long-term quality and
reliability.
To establish a field failure rate, the acceleration factor is
applied to the device operating hours observed at high
temperature stress and extrapolated to a failure rate at
55·C ambient temperature in still air.
RELIABILITY DATA
Microchip Technology's products in plastic packages
were produced to offer the customer the flexibility of
using plastic devices as a direct substitution for ceramic
package products. Failure Rate Predictions/Operating
Life data for plastic package products at 125·C prove to
be equivalent to the data of ceramic, opening the way for
package substitution for cost savings.
The actual failure rate experienced could be considerably less than that calculated if lower device temperatures occur in the application board, such as would be
the case if a fan, a heat sink, or air flow by convection is
used.
D811008D-1
© 1992 Microchip Technology Inc.
7-9
Plastic Package Reliability
Environment
Typical Failure Mechanism
Operating Life
Process parameter drifVshift
Metal electromigration
Internal leakage path
Lifted bond/ball bond chip-out
Biased-Humidity: Moisture and bias are used to accelerate corrosion-type failures in plastic packages. The
conditions include 85'C ambient temperature with 85%
relative humidity. Typical bias voltage is +5 volts and
ground on alternating pins.
Autoclave (pressure cooker): Using a pressure of one
atmosphere above atmospheric pressure, plastic packaged devices are exposed to moisture at 121 'C. The
pressure forces moisture permeation of the package
and accelerates related failure mechanisms, if present,
on the device.
Temperature Cycle Lifted bond/ball chip-out
Cracked die or surface cracks
Bond pad corrosion
Biased-Humidity
Internal circuit corrosion
Autoclave
Inter-pin leakage
Charge loss
Thermal Shock: Exposes devices to extreme temperatures from -55"C to +125'C by alternate immersion
in liquid media.
High Temp. Bake
Charge loss
High Temp.
Reverse Bias
Charge gain, Parameter
drifVshift
Retention Bake: A 150"C temperature stress is used to
accelerate charge loss in the memory cell and measure
the data retention on the EPROM.
High Temperature Reverse Bias (HTRB): A special
test mode which subjects the entire EPROM array to a
high gate voltage with drain, source and substrate
grounded. It is used to measure charge gain and/or
threshold shifts.
DEFINITIONS
FIT (Failure In Time): Expresses the estimated field
failure rate in number of failures per billion power-on
device-hours. 100 FITS equals 0.01 % fail per 1,000
device-hours.
RELIABILITY CONTROL SYSTEM
Operating Life Test: The device is dynamically exercised at a high ambient temperature (usually 125"C) to
quickly simulate field life. Derating from high temperature, an ambient use condition failure rate can be calculated.
A comprehensive qualification system ensures that released products are designed, processed, packaged
and tested to meet both design functionality and strict
reliability objectives. Once qualified, a reliability monitor
system ensures that wafer fabrication and assembly
process performance is stable over time. A set of
baseline specifications is maintained that states which
changes require requalification. These process changes
can only be made after successful demonstration of
reliability performance. This system results in reliable
field performance, while enabling the smooth phase-in
of improved designs and product capability.
Temperature Cycle: The devices are exposed to severe extremes of temperature in an alternating fashion
(-65"C for 15 minutes, 150"C for 15 minutes per cycle).
Package strength, bond quality and consistency of assembly process are stressed using this environment.
• Design objectives/specifications
• Testability goals
• Reliability requirements
• Process/packaging requirements
• Design guidelines
Design:
• Functional models
• Logic design & verification
• Circuit design & verification
• Layout design & verification
• Prototype verification
• Performance characterization
Develop (as required):
• Wafer fabrication processes
• Package/packaging technology
using qualification tests:
• Operating life, 12S'C ambient
• Temp-cycle, -6S"/IS0"C
• Thermal shock, -6S'/IS0"C
• ESD resistance, ± 2000 V
• Latch-up (CMOS devices)
• Biased-humidity, 8S"C/8S%
• Autoclave (pressure cooker)
retention bake
• HTRB
•
•
•
•
•
•
•
•
•
•
•
•
Design release document
Baseline wafer fabrication process
Baseline assembly process
Qualification release
Enter device to specification system
Wafer-level reliability controls
Assembly reliability controls
Early failure rate sampling
Reliability monitoring
Statistical process control feedback
Audit specifications
Analyze returned failures
• Requalify devices as needed for major changes
such as ESD resistance enhancement, cost
reduction/die shrink, process improvement,
and new package types.
DSll008D-2
© 1992 Microchip Technology Inc.
7-10
Plastic Package Reliability
RELIABILITY DATA SUMMARY
ELECTRICAL CHARACTERISTICS
This section provides a reliability summary of Microchip
Technology's plastic product. Included is plastic packaging information and reliability data obtained to date for
all product families.
Microchip Technology's product packaged in plastiC are
tested to the same electrical characteristics as devices
assembled in Cerdip packages. This testing covers the
full commercial range of 0-70'C. Performance characteristics are the same as for Cerdip packaging.
Plastic Package Characteristics
QUALITY/RELIABILITY TESTING
RESULTS
Plastic packaging utilized for the product families uses a
silver filled epoxy adhesive for die attach. Bonding
technology is gold wire thermosonic bonding. The lead
frame pedestal and finger tips are silver plated. The
epoxy molding compound used is a Shinetsu compound
KMC-140-3 which meets the safety rating requirements
of UL94 v-a. External lead finish is electroplated tinl
lead 9011 0 percent. The package code table below lists
the plastic packages covered by the reliability data in this
document.
Reliability and programming tests were performed on all
devices in plastic packages. Data from these qualification tests are displayed throughout this document.
PROGRAMMABILITY
Programmability is measured by sample data taken
from production lots. Devices are programmed with a
Diagonal FF which exercises 98% of the EPROM cell
array. This rigorous patterning combined with Microchip
Technology Express programming algorithm greatly
enhances the ability to meet specific customer applications. Large volume beta site programming results for
plastic EPROMs indicate an expected yield far exceeding 99%, using Express programming, under normal
production conditions.
As part of an on going product improvement program,
Microchip Technology will apply its Quality and Reliability process in evaluating the latest developments in
plastic packaging technology, and implement the highest reliability materials and assembly techniques.
PLASTIC PACKAGE IDENTIFICATION CODES
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Leadless Chip Carrier
Dual In Line (600)
Dual In Line (300)
SOIC (.150)
SOIC (.207)
SOIC (.300)
TSOP (8 x 20mm)
:1
I,
il
Introduction
Package Description
ii
Identification Code
PROGRAMMABILITY DATA (12 MONTH
PERIOD)
L
P
SP
SUSN
SM
SO
TS
Time
Period
No. of
Sample Units
No. of Non-Programmable Units
Fraction
Defective
1989
10019
258
.026
1990
26025
326
.013
Note: Derated to typical customer programming, the
defective fraction should be 0.006.
© 1992 Microchip Technology Inc.
D511008D-3
7 -11
i
'I
ji
I
Plastic Package Reliability
HIGH TEMPERATURE (12S°C) DYNAMIC LIFE TEST
Graph set for EEPROM. PIC and EPROM for all conditions
High tElmperature dynamic life testing accelerates random failure modes which would occur in user applica-
tions. Voltage bias and address signals are used to
exercise the device in a manner similar to user systems.
EEPROM DYNAMIC LIFE
INFANT MORTALITY
EEPROM DYNAMIC LIFE
LONG TERM MORTALITY
500
3000
2500
400
w 2000
I-
W
eA"f''.!'!
:,as
l
N
,"
. 28:)1
Notes
0.200
A2.
B't(,;
"
Max
Typical" '
Reference
0.098
0.102
Typical
,0.600
0.600
Reference
0.600
0.680
0.115
0.145
28'
28
28
0.035
0.020
S
0·El89-
-'C'
81
0.508"
-
"
DSG0049Q
Reference
© 1992 Microcf1ip-,TeehI10Iogy.lric.
8-2-10
a
Microchip
Packaging Diagrams and Parameters
Package Type: 40-Lead Plastic Dual In-line (.600 mil)
N
P;oN01
Indicator - - . .
Area
DGrM
~---,----
t---~--i
I
a--II
II
D1 - - - - - - - . j
Package Group: Plastic Dualln·line (PLA)
Millimeters
Symbol
Min
Max
a
0°
10°
Inches
Notes
Min
Max
0°
10°
A
-
5.080
-
0.200
A1
0.381
-
0.015
-
A2
3.175
4.064
0.125
0.160
B
0.356
0.559
0.014
0.022
Notes
B1
1.270
1.778
Typical
0.050
0.070
Typical
C
0.2032
0.381
Typical
0.008
·0.015
Typical
D
51.181
52.197
2.015
2.055
D1
48.260
48.260
.1.900
1.900
.0.625
Reference
Reference
E
15.240
15.875
0.600
E1
13.462
13.970
0.530
0.550
e1
2.489
2.591
Typical
0.098
0.102
Typical
eA
15.240
15.240
Reference
0.600
0.600
Reference
eB
15.240
17.272
0.600
0.680
2.921
3.683
0.115
0.145
L
N
40
40
40
40
8
1.270
-
0.050
-
81
0.508
-
0.020
-
©t992 Microchip Technology Inc.
DS00049C
8-2-11
".':;
~.
, ",:,
':,~.i.
.
",
'1·
e,
Mlc..~hip
P~ckagingDiagrams
andPatameters
Package Type: 48-Lead Plastic DlUd Iri-line(.600 mil) .
N
O·······TI
l r---~--I
. '0
. . . . ' .'. t!
E1
~~i:~~: ~,.'
u~n
---',I~-
n
E
f~· ::---~~
Area
1*------ D1 ---------I~
P8ckaQe Group: Plast1c Dualln~lIne (PLA)
./
Symbol
u ..
"
A
j
Millimeters
Min
Max
0°
-
Inche.s
Notes
Min
Max
10°
0°
10°
5.080
-
0.200
Notes
A1
0.381
-
0.015
-
A2
3.175
0.125
0.160
B
0.356.
4.064
0.559';'
0.014
0.022
B1··· ....
1.270
,1.2.76
Typical
0.050
0.050
0.2032,
0:381
Typical
0.008
0.015
6'1.4Stf .
'62.230
2.420
2.450
Typical.
...
·.Reftreijqe
C
D
,
E.
58.4;!0 .. ' . 58.420
15.875
15. 240
E1
13.7HI
D1' .'
Reference '
14.224
boo
2.300
0.600
0.625
()~540
0560
Typical
.. '
'.'
.
. .:;
0;098
0.102
,TypIQIJI
0.600
0.600
'Reference
17.272
0.600
0.680
2.921
.3.683
0.115
48
48
48
0.145
48 '
S
1.270
-
81
0.508
-:
'81,':1';
2.489
2.591
TypICal
eA
es
15.240
15.240
Reference
15.240
L.
N
'.
0.050
,
0.020 "
-
:,
©1'9W1l1It1ri5b!i1j5'TEfCh'no16W1Itt.
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8-2-1,2
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Microchip
Packaging Diagrams and Parameters
Plastic Leaded Chip Carrier Family
Symbol List for Plastic leaded Chip Carrier Package Parameters
Symbol
Description of Parameters
A
Distance from seating plane to highest point of body
A1
Distance from lead shoulder to seating plane
CP
Seating plane coplanarity
DIE
Outside dimension
D1/E1
Plastic body dimension
D2/E2
Footprint
D3/E3
Footprint
LT
Lead thickness
N
Total number of potentially useable lead positions
Nd
Total number of leads on short side (rectangular)
Ne
Total number of leads on long side (rectangular)
Notes:
2
3
4
5
6
7
8
All dimensions and tolerances conform to ANSI
Y14.5M-1982.
Datum planeG±!located at top of mold parting
line and coincident with top of lead. Where lead
exits plastic body.
Datums ID-EI andlF-G1 to be determined where
center leads exit plastic body at datum planeG±!.
To be determined at seating planetQj.
Transition is optional.
Plastic body details between leads are optional.
Dimensions 01 and E1 do not include mold
protru
sion. Allowable mold protrusion is
.254 mm/.010 in. per side. Dimensions D and E
include mold mismatch and are dtermined at
parting line.
Square: Details of pin 1 identifier are optional but
must be located within one of the two zones
indicated.
Rectangle: Details of pin 1 identifier are optional
but must be located within zone indicated. If the
number ofterminals on a side is odd, terminal 1
is the center terminal.
©1992 Microchip Technology Inc.
Location to datumst&landOOto be
determined at planeG±!.
10 All dimensions and tolerances include lead
trim offset and lead finish.
11 These two dimensions determine maximum angle of the lead for certain socket
applications. If unit is intended to be
socketed, it is advisable to review these
dimensions with the socket supplier.
12 Controlling dimension: inches;
9
X
Sum of dam bar protrusions to be 0.17
(.007) max per lead .
Y
Feature is not required, but is optional at
DSD0049C
8-2-13
Microchip
Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Leaded Chip Carrier (Square)
D
tq:::::::~
..:
T
i
0.25 4 Max
.010
-A
~.508
~...... ~
1.651
.065
::.
A
A1
D
D1
D2
D3
E
E1
E2
E3
r:mA\
.065
R 1.14/0.64
R 1.14/0.64
.045/.025
Symbol
.020
---c. 1.651
.0451.025
Package Group: Plastic Leaded Chip Carrier (PLCC)
Inches
Millimeters
Min
Notes
Min
Max
Max
4.572
0.165
2.413
2.921
0.095
0.115
12.319
12.573
0.485
0.495
11.430····
11.582
0.450
0.456
10.414
10.922
0.410
0.430
7.620
7.620
0.300
0.300
0.485
0.495
0.450
0.456
0.410
0.430
0.300
0.300
4.191
Reference
0.180
12.319
12.573
11.430
11.582
10.414
10.922
7.620
7.620
N
28
28
28
28
CP
-
0.1016
-
0.004
LT
0.203
0.381
0.008
0.015
...
Reference
Notes
Reference
Reference
©1992 Microcl11pTechnoJogy·lnc.
DS00049C
8-2-14
Microchip
Packaging Diagrams and Parameters
Package Type: 32-Lead Plastic Leaded Chip Carrier (Rectangle)
Ne
Lfu.
.&,. °6b; MaX~Y
~>~
L..::!.:::.
1.14
.045
.032/0.26
'~M
0.64 M
J::"j.J_.........,.-=--'--'-'-.JL....::"">'
I'~
0.64 M·
.025
In
.-
~
0.54/0.33
.021/.013
I$I~@IA®-B@I
R 1.0210.76
.0401.030
R 1.02/0.76
.0401.030
.A.
0.B2I0.66 ~
":,,::r. ,:,"'"
,I
D@I
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
0.140
A
A1
D
D1
D2
D3
E
Et
E2
E3
N
Nd
Ne
9
9
CP
-
0.1016
-
0.004
LT
0.203
0.381
0.008
0.015
3.556
0.120
1.905
2.413
0.075
0.095
12.319
12.573
0.485
0.495
11.35
11.506
0.447
0.453
4.826
5.334
0.190
0.210
7.620
7.620
0.300
0.300
14.859
15.113
0.585
0.595
13.893
14.046
0.547
0.553
6.096
6.858
0.240
0.270
10.160
10.160
0.400
0.40,0
32
32
32
32
7
7
7
7
3.048
©1992 Microchip Technology Inc.
Reference
Reference
9 '"
Notes
Reference
Reference
,,'
9
DSOOO49C
~.
Microchip
Packaging Diagrams and Parameters
Package Type: 44-Lead Plastic Leaded Chip Carrier (Square)
D
I·I.I:~BI~~
m •
D1
....11. r::O-lA\.
,nnnnnn
·11
L
lfo
:::::::~..:
E, E
G1
uuu,
&r:rrll-
IEfl,,"0177
)1 11F-G@
.007 @A
i
0.254 Max·
.010
-I&
-/j').
~.508
~.... ~.02000&
1.651
.065
::
1.53
M:r- ~
.060
L:"":'''r
.065
R 1.14/0.64
.045/.025
.0451.025
0.812/0.661&
.03210.26
~~.
~
o;4~110.533/0.331
-----c 1.651
R 1.14/0.64
r-
r--
.025 Min
.0211.013
IEflI%W'@jA!F-G@,D-E@1
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol
Min
Max
A
4.191
Inches
Notes
Min
Max
4.572
0.165
0.180
A1
2.413·
2.921
0.095
0.115
D
17.399
17.653
0.685
0.695
D1
16.510
16.662
0.650
0.656
D2
15.494.
16.002
0.610
0.630
D3
12.700
12.700
0.500
0.500
E
17.399
17.653
0.685
0.695
0.650
0.656
0.610
0.630
0.500
0.500
44
44
Reference
E1
16.510
16.662
E2
15.494
16.002
E3
12.700
12.700
N
44
44
CP
-
0.1016
-
0.004
LT
·0.203
0.381
0.008
0.015
Reference
Notes
Reference
Reference
©1992 Microchip Technology Inc.
DSOOO4.9C
8-2-16
lI!Iicrochip
Packaging Diagrams and Parameters
Package Type: 68-Lead Plastic Leaded Chip Carrier (Square)
0
1,101 ::1'101 D-'~
m ,
-114r:oV3\.
,ri"nrmr1
'/
::
~ ......
....... ~..
'
3:~fo E1 E
8
L=i
wwww,
.&!:IJIr- IEllI.oo6~7®IAIF-G®
i
0.2 54 Max
4'
&.
.010
1.651
.065
,,
R1.14/0.64
.0451.025
-I&
r-
0.812/0.661&.
~:fR:~"
0.508
~ MOGFjV'h
~C~4.
---"L. 1.651
.065
i
.025 MIn
1'1 i 0.;33/0.331
~
R 1.14/0.64
.045/.025
r-
.021/.013
iElli%1Y@jAlF-G®,O-E®i
Package Group: Plastic leaded Chip Carrier (PlCC)
Millimeters
Symbol
Min
Max
A
A1
D
D1
D2
03
E
E1
E2
E3
4.191
Inches
Notes
Min
Max
4.699
.165
.185
2.286
2.794
.0.90.
.110.
25.0.19
25.273
.985
.995
24.130.
24.333
.950.
.958
22.860.
23.622
.90.0.
.930.
Reference
20..320.
.80.0.
-
25.0.19
25.273
.985
.995
24.130.
24.333
.950.
.958
22.860.
23.622
.90.0.
.930.
20..320.
68
-
CP
-
.10.16
LT
.20.32
.254
N
©1992 Microchip Technology
Reference
.80.0.
Notes
Reference
Reference
68
-
0..0.0.8
0..0.10.
.0.0.4
Inc.
OS00049C
8-2-17
~e
Microchip
Packaging Diagrams and Parameters
Package Type: 84-Lead Plastic Leaded Chip Carrier (Square)
D
~:::::::~ ..'
T
-I~I- 0.812/0.661&
oo;::w'
4> "
,:~~m~
L ...........
~MOwA
1.651
.065
R 1.14/0.64
.0451.025
.060
~~~4. ~
------c 1.651
::
:'1 ; 0.;33/0.331
~
.025 MIn
.065
R 1.14/0.64
.0451.025
r-
.021/.013
Iffil~@IAIF-G®.D-E®1
Package Group: Plastic Leaded Chip Carrier (PLCC)
Inches
Millimeters
Min
Max
4.699
.165
.185
2.794
.090
.110
30.099
30.353
1.185
1.195
29.210
29.413
1.150
1.158
27.940
28.702
1.100
1.130
Symbol
Min
Max
A
A1
0
01
02
03
E
E1
E2
E3
N
4.191
2.286
Notes
Notes
25.400
-
1.000
-
30.099
30.353
1.185
1.195
29.210
29.413
1.150
1.158
27.940
28.702
1.100
1.130
25.400
-
Reference
Reference
84
1.000
Reference
Reference
84
-
CP
-
.1016
-
.004
LT
.2032
.254
.008
.010
©1992 Microchip Technology Inc.
DS00049C
8-2-18
Microchip
Packaging Diagrams and Parameters
Plastic Small Outline Family
Symbol List for Small Outline Package Parameters
Symbol
Description of Parameters
IX
Angular spaciing between min and max lead positions measured at the guage plane
A
Distance between seating plane to highest point of body
Al
Distance between seating plane and base plane
B
Width of terminals
C
Thickness of terminals
D
Largest overall package parameter of length
E
Largest overall package width parameter not including leads
e
Linear spacing of true minimum lead position center line to center line
H
Largest overall package dimension of width
L
Length of terminal for soldering to a substrate
N
Total number of potentially useable lead postions
CP
Seating plane coplanarity
Notes:
1. Controlling parameter: inches.
2. All packages are gull wing lead form.
3. "0" and "E" are reference datums and do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .006 package ends and .010 on sides.
4. The chamfer on the body is optional. If it is not present, a visual index feature must be located
within the crosshatched area to indicate pin 1 position.
5. Terminal numbers are shown for reference.
©.199~
Microchip Teehnology Inc.
QSQOO49C
8-2-19
Microchip
Packaging Diagrams and Parameters
Package Type: 8-Lead Plastic Surface Mount (SOle - Narrow, 150 mil Body)
Index
Area
Chamfer
~~D~
:i=t==r==~
~ i
1
CP
Seating
Plane
A1
Base
Plane
A
Package Group: Plastic sOle (SN)
Inches
Millimeters
Symbol
Min
Max
Notes
Min
Max
a
0°
8°
0°
8°
A
1.3716
1.7272
0.054
0.068
A1
0.10.16
0.2489
0.004
0.0098
B
.0.3556
0.4826
0.014
0.019
C
0.1905
0.2489
0.0075
0.0098
0
4.8006
4.9784
0.189
0.196
E
3.810
3.9878
0.150
0.157
e
1.270
1.270
H
5.8166
6.1976
h
0.381
L
0.508
0.050
0.050
0.229
0.244
0.762
0.015
0.030
1.016
0.020
0.040
Typical
N
8
8
8
8
CP
-
0.1016
-
0.004
Notes
Typical
© 1992 Microchip Technology Inc.
DS00049C
8-2-20
Microchip
Packaging Diagrams and Parameters
Package Type: 8-Lead Plastic Surface Mount (SOle· Medium, 200 mil Body)
B
-+le~
-11- 1
Index
Area
Chamfer
hx45° - -
Package Group: Plastic sOle (SM)
Inches
Millimeters
Symbol
Min
Max
a
0°
8°
Notes
Min
Max
0°
8°
A
1.778
2.032
0.070
0.080
A1
0.1016
0.2489
0.004
0.0098
B
0.3556
0.48.26
0.014
0.019
0.0075
0.0098
C
0.1905
0.2489
0
5.08
5.334
0.200
0.210
E
5.156
5.410
0.203
0.213
e
1.270
1.270
0.050
0.050
H
7.62
8.382
0.300
0.330
h
Typical
0.381
0.762
0.015
0,030
L
0.508
1.016
0.020
0.040
N
14
14
14
14
CP
-
0.1016
-
0.004
Notes
Typical
.--
DS00049C
©1992 Microchip Technology Inc.
8-2-21
Microchip
Packaging· Diagrams and Parameters
Packag~
Type: 14-Lead Plastic Surface Mount (SOle - Narrow, 150 mil Body)
~I
e I--
Index
Area
I~
CP
Seating
Plane
~
D~
*t=-=~~~·-Base
i I
Plane
A1
A
Package Group: Plastic
sOle (SL)
Inches
Millimeters
Symbol
Min
Max
Notes
Min
Max
a
0°
8°
0°
8°
A
1.3716
L7272
0.054
0.068
A1
0.1016
0.2489
0.004
0.0098
B
0.3556
0.4826
0.014
0.019
C
0.1905
0.2489
0.0075
0.0098
0
9.830
9.982
0.387
0.393
E
3.810
3.9878
0.150
0.157
e
1.270
1.270
H
5.8166
h
L
0.050
0,050
6.1976
0.229
0.244
0.381
0.762
0.Q15
0.030
0.406.4
1.143
0.016
0.045
16
0.004
Typical
N
14
14
16
CP
-
0.1016
-
[)SO()0496
Notes
Typical
© 1992 Microchip'fechnology Inc.
8-2-22
Microchip
Packaging Diagrams and Parameters
Package Type: 18-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)
~
e j4-
I
Index
Area
I
Tl
h x 45°
-I ~
Chamfer
hx45°
~I.
CP
Seating -...
Plane
~I
0
:::::;:=::kHRKP\KiJ -
i 1
*=+
A1
Base
Plane
A
Package Group: Plastic sOle (SO)
Millimeters
Symbol
Min
Max
a
0°
A
Inches
Notes
Min
Max
8°
0°
8°
2.3622
2.6416
0.093
0.104
A,
0.1016
0.2997
0.004
0.0118
B
0.3556
0.4826
0.014
0.019
C
0.2413
0.3175
0.0095
0.0125
D
11.3538
11.7348
0.447
0.462
E
7.4168
7.5946
0.292
0.299
e
1.270
1.270
0.050
0.050
H
10.0076
10.6426
0.394
0.419
h
0.381
0.762
0.015
0.030
L
0.4064
1.143
0.016
0.045
N
18
18
18
18
CP
-
0.1016
-
0.004
Typical
© 1992 Miprocnip 1echnolpgylnc.
Notes
Typical
DS00049C
8-2-23
Microchip
Packaging Diagrams and Parameters
Package Type: 24-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)
Index
Area
Chamfer
h x 45°
~~
CP
Seating Plane
.1
=r==ffHKHP~-Base
i 'I
Plane
0
=i=+
Al
A
Package Gro4P: Plastic sOle (SO)
Millimeters
Symbol
Min
Max
Inches
Notes
Notes
Max
Min
a
0°
8°
0°
8°
A
2.3622
2.6416
0.093
0.104
Al
0.1016
0.2997
0.004
0.0118
B
0.3556
0.4826
0.014
0.019
C
0.2413
0.3175
0.0095
0.0125
0
15.2146
15.5956
0.599
0.614
E
7.4168
7.5946
0.292
0.299
Typical
e
1.270
1.270
0.050
0.050
H
10.0076
10.6426
0.394
0.419
h
0.381
0.762
0.015
0.030
L
0.4064
1.143
0.016
0.045
N
24
24
24
24
CP
-
0.1016
-
0.004
Typical
DS00049C
I
©
8-2-24
1992 Microchip Technology Inc.
Microchip
Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Surface Mount (SOle - Wide, 300 mil Body)
--I e 14I I
T1
Index
Area
h x 45°
-I ~
Chamfer
h x 45°
.-LJ
CP
~I
t ::::;::=::~\iiJ
1
D
;:::+
Seating - Plane
A1
Symbol
Base
Plane
A
Min
Package Group: Plastic S.OIC (SO)
Millimeters
Max
Notes
Min
Inches
Max
IX
0°
8°
0°
8°
A
2.3622
2.6416
0.093
0.104
A1
0.1016
0.2997
0.004
0.0118
B
0.3556
0.4826
0.014
0.019
C
0.2413
0.3175
0.0095
0.0125
D
17.7038
18.0848
0.697
0.712
E
7.4168
7.5946
0.292
0.299
e
1.270
1.270
0.050
0.050
H
10.0076
10.6426
0.394
0.419
h
0.381
0.762
0.015
0.030
L
0.4064
1.143
0.016
0.045
N
28
28
28
28
CP
-
0.1016
-
0.004
Typical
Notes
Typical
DS00049C
© 1992 Microchip Technology Inc.
8-2-25
~8
MicrOchip
Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Surface Mount (SOle - Wide, 330 mil Body)
~
I
Index
Area
e \4-
I
T1
h x 45 0
--I ~
Chamfer
h x 45 0
~J
·1
=r=~"iHFQJ-Base
Plane
'D
CP .L.o!
Seating ---.. -r-t "
Plane
A1
A
~ymbol
Min
IX
0
Package Group: Plastic SOIC (SW)
Millimeters
Max
Notes
Min
Inches
Max
8'
0
8'
A
2.286
2,642
.090
.104
A1
0.102
0.279
.004
.011
B
0.356
0.508
.014
.020
C
0.228
0.305
.009
.012
D
17.780
18.085
.700
.712
E
8.636
8.890
.340
.350
e
1.27
1.27
.050
.050
H
11..760
12.116
.463
.477
\1
0.254
0.736
.010
.029
L
0.508, '
.042
Typical
1.067
.020
N
28
28
28
28
CP
-
0.1016
-
0.004
D500049C
Notes
Typical
© 1992 Microchip Techriology Inc.
8-2-26
Microchip
Packaging Diagrams and Parameters
Plastic Shrink Small Outline Family
Symbol List for Shrink Small Outline Package Parameter
Symbol
Description of Parameters
a
Angular spacing between min. and max. lead positions measured at the guage plane
A
Distance between seating plane to highest point of body
A,
B
Width of terminals
C
Thickness of terminals
Distance between seating plane and base plane
D
Largest overall package parameter of length
E
Largest overall package width parameter not including leads
e
Linear spacing of true minimum lead position center line to center line
H
Largest overall package dimension of width
L
Length of terminal for soldering to a substrate
N
Total number of potentially useable lead pOSitions
CP
Seating plane coplanarity
Notes: 1. Controlling parameter: mm.
2.
All packages are gull wing lead form.
3.
"D" and "E" are reference datums and do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.15mm .006 package ends and .010" on sides.
4.
A .25mm visual index feature must be located within the crosshatched area to indicate pin 1 position.
5.
Terminal numbers are shown for reference.
©1992 Microchip Technology Inc.
DS00049C
8·2·27
Microchip
Packaging Diagrams and Parameters
Package Type: 20-Lead Plastic Surface Mount
(SSOP - .209 mil Body 5.30mm)
Index
area
N
-j
E
_l~~
123
.Wc
'~_A
CP
1
Seating plane
.-- 0
Symbol
a
A
A,
B
C
D
E
e
H
L
N
CP
DS00049q
Base plane
Min
0'
1.73
0.05
0.25
0.13
7.07
5.20
0.65
7.65
0.55
20
•
A1
Package Group: Plastic SSOP
Millimeters
Max
Notes
Min
8'
0'
0.68
1.99
0.21
0.002
0.38
0.010
0.22
0.005
7.33
0.278
5.38
0.205
Typical
0.256
0.65
7.90
0.301
0.95
0.022
20
20
0.1016
Inches
Max
8'
0.78
0.008
0.015
0.009
0.289
0.212
0.256
0.311
0.037
20
0.004
Notes
Typical
©1992 Microchip Technology Inc.
Microchip
Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Surface Mount
(SSOP - .209 mil Body 5.30mm)
N
Index
area
-t
_J
E
:
1 23
.~A
ftt~
CP-
I
D
~
Symbol
Min
a
A
A,
0°
1.73
0.05
0.25
0.13
10.07
5.20
0.65
7.65
0.55
28
B
C
D
E
e
H
L
N
CP
•
A1
Base plane
' - Seating plane
Package Group: Plastic SSOP
Millimeters
Max
Notes
Min
Max
8°
1.99
0.21
0.38
0.22
10.33
5.38
0.65
7.90
0.95
28
0.1016
8°
0.78
0.008
0.015
0.009
0.407
0.212
0.256
0.311
0.037
28
0.004
Typical
©1992 Microchip TEi>chnology Inc.
0°
0.68
0.002
0.010
0.005
0.397
0.205
0.256
0.301
0.022
28
Inches
Notes
Typical
DS00049C
8·2·29
Microchip
Packaging Diagrams and Parameters
Plastic Thin Small Outline Family
Symbol List for Thin Small Outline Package Parameter
Symbol
Descl'iption of Parameters
a
Angular spacing between min. and max. lead positions measured at the guage plane
A
Distance between seating plane to highest point of body
A,
B
Width of terminals
C
Thickness of terminals
D
Largest overall package parameter of length
E
Largest overall package width parameter not including leads
Distance between seating plane and base plane
e
Linear spacing of true minimum lead pOSition center line to center line
H
Largest overall package dimension of width
L
Length of terminal for soldering to a substrate
N
Total number of potentially useable lead positions
CP
Seating plane coplanarity
Noles: 1. Controlling parameter: inches.
2. All packages are gull wing lead form.
3.
"D" and "E" are reference datums and do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed .005 per side.
4.
A visual index feature must be located within the crosshatched area to indicate pin 1 position.
5. Terminal numbers are shown lor reference.
©1992 Microchip Technology Inc.
DS00049C
8-2-30
Microchip
Packaging Diagrams and Parameters
Package Type: 28-Lead Plastic Surface Mount (TSOP 8 x 20mm)
H
Index
Area
E ----------1
28
N
Seating
Parting
L:~~/~~~~~~~~~~~~~I~;~\-.l
Line
-'/-/6
I
Base
Plane
-~-
a
~~
See
Detail 'A'
A1
DETAIL 'A'
Package Group: Plastic TSOP (TS)
Millimeters
Symbol
Min
a
0
A
A,
0.00
0.15
Inches
Min
0
Max
1~20
-
.047
.000
.006
.006
.010
Max
8·
Notes
8'
C
0.10
0.15
0.25
0.2,0
.004
.008
D
7.90
8.20,
.307
.323
E
18.30
18.50
.720
.728
e
-
H
.50
19.80
L
B
.020
-
.780
.795
-
20.20
-
0040
0.60
.016
N
28
28
28
CP
-
0.102
Typical
,,\'
Notes
Typical
-
©1992 Microchip Technology Inc.
.024
28
- - -- , - - - .004
DS00049C
8-2-31
Microchip
Packaging Diagrams and Parameters
Package Type: 32-Lead Plastic Surface Mount (TSOP 8 x 20mm)
H
Index
Area
E
------------~
32
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _r _
N
Seating
7
'ane
,
Parting
0:~,\~~~~~~~~~~~~~,3~~u
~_,"
I
See
Detail 'A'
Base
Plane
-~-
a
~~
Line
A1
C
DETAIL 'A'
Package Group: Plastic TSOP (TS)
Inches
Millimeters
Symbol
Min
a
0
Max
8'
A,
0.00
0.15
.000
.006
B
0.15
0.25
.006
.010
C
0.10
0.20
.004
.008
D
7.90
8.20
.307
.323
E
18.30
18.50
.720
.728
e
.50
H
19.80
20.20
.780
.795
L
0040
0.60
.016
.024
N
28
28
28
A
CP
Notes
Min
Max
0
8°
Notes
.047
1.20
Typical
0.102
.020
Typical
28
.004
©1992 Microchip Technology Inc.
DS00049C
8-2-32
Microchip
Packaging Diagrams and Parameters
Plastic Metric Flat Pack Family
Symbol List for Metric Plastic Quad Flat Pack Package Parameters
Symbol
a
Description of Parameters
Angular spacing between min and max lead positions measured at the guage plane
A
Distance between seating plane to highest pOint of body
A,
Distance between seating plane and base plane
A2
b
Width of terminals
C
Thickness of terminals
Distance from base plane to highest point of body
Largest overall package parameter including leads
D,IE,
DIE
Largest overall package parameter including leads
D,IE3
e
Linear spacing of true minimum lead position center line to center line
Center of end lead to center of end lead
L
Length of terminal for soldering to a substrate
N
Total number of potentially useable lead positions
CP
Seating plane coplanarity
Notes
1.
All dimensioning and tolerancing conform to
ANSI Y14, BM-1582.
2.
Datum Plane c:EJ is located at bottom of hold
parting line and coincident with bottom of lead,
where lead exits body.
3.
&
&
ffi
8.
&
Datums[A1jJandQ:[]to be determined at Datum
plane i.=BJ.
To be determined at seating plane
W.
Dimensions D1 and E1 do not include hold
protrusion. Allowable protrusion is 0.25 mm per
side. Dimensions D1 and E1 do not include hold
mismatch and are determined at Datum Plane
~
G±J.
&
These dimensions to be determined at Datum
plane
rnJ
All dimensions in millimeters.
Dimension b does not includeDambar protrusion.
Allowable Dambar protrusion shall be 0.08mm
total in excess of the b dimension at maximum
material condition. Dambar cannot be located on
the lower radius or the lead foot.
Exact shape of this feature is optional.
11.
N is the number of leads.
12.
Controlling parameters: milimeters
13.
All packages are gull wing lead form.
Details of pin 1 identifier are optional but must be
located within the zone indicated.
©1992 Microchip Technology Inc.
DS00049C
8-2-33
Microchip
Packaging Diagrams and Parameters
Package Type: 44-Lead Plastic Surface Mount
(MQFP 1Oxl Omm Body 1.6/0.Smm Lead Form)
lt
o.20m ;n.
==::::i\.r
1
E3
0.13 R min.
E1
1.60 Ref.
J
TYP 4X
AlL
o~'
Base
Plane
~
7~
~
"
Seating
Plane
A1
Package Group: Plastic MQFP
Symbol
a
A
A,
A2
b
C
D
D,
D3
E
E,
E3
e
L
N
CP
DS00049C
Min
0'
2.00
0.05
1.95
0.30
0.15
12.95
9.90
8.00
12.95
9.90
8.00
0.80
0.65
44
0.102
Millimeters
Max
r
2.35
0.25
2.10
0,45
0.18
13,45
lO.10
8.00
13.45
10.10
8.00
'.8e
0.95
44
Notes
TVDical
Reference
Reference
Min
0'
0.0787
0.0019
0.768
0.0118
.006
0.510
0.390
0.315
0.510
0.390
.315
.0314
.0256
44
.004
Inches
Max
r
0.0925
0.0098
0.0827
0.0177
.007
0.530
0.398
0.315
0.530
0.398
.315
.0314
.0374
44
Notes
Typical
Reference
Reference
©1992 Microchip Technology Inc.
Microchip
APPENDIX
OFFICE LOCATIONS
Factory Representatives
Distributors
Factory Sales
.................................................................................................................... A- 1
....................................................................................................................A- 5
.................................................................................................................... A- 13
© 1992 Microchip Technology Inc.
DS00018E
A-i
~.
Microchip
© 1992 Microchip Technoiogy
D800018E
A-ii
Field Offices
Factory Representatives
DS00056F
© 1992 Microchip Technology Inc.
A-iii
Factory Representatives
Field Offices
DS00056F-iv
© 1992 Microchip Technology Inc.
A-iv
Field Offices
ASIA
Hong Kong
Memec (Asia Pacific) Ltd.
Unit No. 2520-2525
Tower 1, Metroplaza
Hing Fong Road, Kwai Fong
N.T., Hong Kong
Tel: 8524180909
Fax: 8524181600
Korea
Memec (Asia Pacific) Ltd.
4 Floor Myungdang Bldg.
Samsung-Dong
Kangnam-Ku
Seoul, Korea
Tel: 8225635277
Fax: 8225635279
Singapore
Memec (Asia Pacific) Ltd.
Singapore Representative Office
10 Anson Road #14-02
International Plaza
Singapore 0207
Tel: 652224962
Fax: 652224939
Taiwan
Memec (Asia Pacific) Ltd.
14F-1, No.171, Sec. 5,
Min Sheng East Road
Hai Hwa Bldg.
Taipei, Taiwan
Tel: 88627602028
Fax: 88627651488
CANADA
Alberta
Enerlec Sales, Ltd.
37 Evergreen Terrace
Calgary, Alb. T2Y 2V9
Tel: 4032563627
Fax: 4032549121
British Columbia
Enerlec Sales, Ltd.
3671 Viking Way #7
Richmond, B.C. V6V 1W1
Tel: 6042730882
Fax: 6042730884
Ontario
Dynasty Components, Inc.
174 Colonnade Road - Unit 21
Nepean, Ontario K2E 7J5
Tel: 6137230671
Fax: 6137238820
Factory Representatives
Dynasty Components, Inc.
357 Hillsdale Avenue, E.
Toronto, Ontario M4S 1T9
Tel: 4165872278
Fax: 4164893527
Quebec
Dynasty Components, Inc.
1870 Blvd. des Sources, # 304
Pointe Claire, P.Q. H9R 5N4
Tel: 5149845342
Fax: 5146946826
EUROPE
Ireland
Eltech Agencies Ltd.
Lackaroe
Youghal
Co. Cork
Tel: 2497172
Fax: 2497170
Scotland
Campbell Collins Northern Ltd.
Unit 1C
Dixon Court, Elgin Ind. Estate
Dunferline KY12 7SG
Tel: 383737800
Fax: 383 734 043
SOUTH AMERICA
Brazil
Aplicacoes Eletronicas Artimar Ltda.
Rua Marques De Itu, 70-1 0 And.
Caixa Postal 5881 e 9498
CEP 01223 - Sao Paulo, Brazil
Tel: 231 0277
Fax: 2550511
USA
Alabama
Electramark, Inc.
4910 Corporate Dr., Suite J
Huntsville, AL 35805
Tel: 2058304400
Fax: 2058304406
Arizona
Western High Tech Marketing, Inc.
9414 E. San Salvador, Suite 206
Scottsdale, AZ 85258
Tel: 6028602702
Fax: 602 860 2712
Arkansas
Comptech Sales, Inc.
9810 E. 42nd Street, Suite 219
Tulsa, OK 74146
Tel: 9186227744
Fax: 9186600340
California
Trinity Technologies
1261 Oakmead Parkway
Sunnyvale, CA 94086
Tel: 4087339000
Fax 408 7339970
Competitive Technology, Inc.
2995 Redhill Avenue, Suite 101
Costa Mesa, CA 92626
Tel: 7145405501
Fax: 714 641 2799
Eagle Technical Sales
1900 Sunset Drive, Suite A
Escondido, CA 92025
Tel: 6197436550
Fax: 6197436585
Colorado
Western Region Marketing, Inc.
9176 Marshall Place
Westminster, CO 80030
Tel: 3034288088
Fax: 3034268585
Connecticut
VISTAssociates, Inc.
2505 Main Street
Stratford, CT 06497
Tel: 2033755456
Fax: 2033756907
Delaware
Tritek Sales
One Cherry Hill, Suite 410
Cherry Hill, NJ 08002
Tel: 6096670200
Fax: 6096678741
Florida
Electramark Florida, Inc.
14021-B North Dale Mabry
Tampa, FL 33618
Tel: 8139621882
Fax: 813961 0664
Electramark Florida, Inc.
401 Whooping Loop, Suite 1565
Altamonte Springs, FL 32701
Tel: 4078300844
Fax: 4078300847
DS00056F-1
© 1992 Microchip Technology Inc.
A-1
Factory Representatives
Florida (cont.>
Electramark ~orida, Inc.
10360 NW 18 Manor
Plantation, FL 33322
Tel: 3054242872
Fax: 3054521974
~
Electramark, Inc.
6030H Unity Drive
Norcross, GA 30071
Tel: 404 446 7915
Fax: 4042636389
Illinois
Janus Incorporated
650 E. Devon Ave.
Itasca,IL 60143
Tel: 7082509650
Fax: 7082508761
.!nd.iAna
Electro Reps, Inc.
407 Airport North Office Park
Fort Wayne, IN 46825
Tel: 2194898205
Fax: 2194898408
Electro Reps, Inc.
7240 Shadeland Station #275
Indianapolis, IN 46256
Tel: 3178427202
Fax: 317841 0230
~
Spectrum Sales
1364 Elmhurst Dr. NE
Cedar Rapids, IA 52402
Tel: 31936.60576
Fax: 3193660635
~
Spectrum Sales
3879 W 95th Street
Overland Park, KS 66206
Tel: 9136486811
Fax: 9136486823
Kentucky
Electro Reps, Inc.
7240 Shadeland Station #275
Indianapolis, IN 46256
Tel: 3178427202
Fax: 3178410230
OS00056F-2
TMC Electronics
7838 Laurel Avenue
Cincinnati, OH 45243·
Tel: 513271 3860
Fax: 513271 6321
Louisiana
CompTech Sales, Inc.
15415 Katy Fwy., Suite 209
Houston,TX 77094
Tel: 7134920005
Fax: 7134926116
CompTech Sales, Inc.
2401 Gateway Dr., Suite 114
Irving, TX 75063
Tel: 2147511181
Fax: 2145508113
Maine
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
Fax: 508 460 1869
Maryland
Delta III Associates, Inc..
1000 Century Plaza, Suite 224
Columbia, MD 21044
Tel: 301 7304700
Fax: 301 730 0790
Massachusetts
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA .01752
Tel; ·508481 9277
Fax: 508460 1869
Michigan
J,LMontgomery Associates, Inc.
34405 W. 12 Mile Rd., Suite 149
Farmington Hills, MI 48331-5617
Tel: 3134890099
Fax: 3134890189
J.L. Montgomery Assoc. Inc.
1573 Riverton, S.E.
Grand Rapids, MI 49546
Tel: 6166768880
Fax: 616 676 2267
Minnesota
ComprehimsiveTechnical Sales, Inc.
6525 City West Parkway
Eden Prairie, MN55344
Tel: 6129417181
Fax: 612 941 4322
Field· Offices
Mississippi
Electramark, Inc.
4910 Corporate Dr., Suite J
Huntsville,AL 35805
Tel: 205 830 4400
Fax: 205 830 4406
Missouri
Spectrum Sales
100 St. Francois Street, Suite 114
Florissant, MO 63031 .
Tel: 314921 1313·
Fax: 314921 0701
Spectrum Sales
3879 W 95th Street
Overland Park, KS 66206
Tel: 9136486811
Fax: 9136486823
Nebraska
Spectrum Sales
3879 W 95th Street
Overland Park, KS 66206
Tel: 9136486811
Fax: 9136486823
~
Western High Tech Marketing, Inc.
9414 E San Salvador, Suite 206
Scottsdale, AZ. 85258
Tel: 6028602702
Fax: 602 860 2712
New Hampshire
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
.
Fax: 508 460 1869
Telex: 710-380-0466
New Jersey
Tritek Sales
One Cherry Hill, Suite 410
Cherry Hill, NJ 08002·
Tel: 6096670200
Fax: 6096678741
Parallax
734 Walt Whitman Rd.
Melville, NY 11747
Tel: 516351 1000
Fax: 516 351 1606
© 1992 Microchip Technology Inc.
Field Offices
Factory Representatives
New Mexico
Oregon
Western High Tech Marketing, Inc.
9414 E San Salvador, Suite 206
Scottsdale, AZ 85258
Tel: 6028602702
Fax: 602 860 2712
Micro Sales
1865 NW 169th Place, Suite 210
Beaverton, OR 97006
Tel: 5036452841
Fax: 503 6453754
New York
Pennsylvania
Apex Associates, Inc.
1210 Jefferson Rd.
Rochester, NY 14623
Tel: 7162727040
Fax: 7162727756
Tritek Sales
One Cherry Hill, Suite 410
Cherry Hill, NJ 08002
Tel: 6096670200
Fax: 6096678741
Parallax
734 Walt Whitman Road
Melville, NY 11747
Tel: 5163511000
Fax: 516351 1606
TMC Electronics
7838 Laurel Avenue
Cincinnati, OH 45243
Tel: 5132713860
Fax: 513271 6321
North Carolina
Rhode Island
Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 9197828433
Fax: 9197828476
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
Fax: 508 460 1869
Telex: 710-380-0466
North Dakota
Compo Technical Sales, Inc.
6525 City West Parkway
Eden Prairie, MN 55344
Tel: 6129417181
Fax: 6129414322
Ohio
TMC Electronics
7838 Laurel Avenue
Cincinnati, OH 45243
Tel: 513271 3860
Fax: 513271 6321
TMC Electronics
7017 Pearl Rd.
Middleburg Heights, OH 44130
Tel: 2168855544
Fax: 216 885 5011
Oklahoma
South Carolina
Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 9197828433
Fax: 9197828476
South Dakota
Compo Technical Sales, Inc.
6525 City West Parkway
Eden Prairie, MN 55344
Tel: 612941 7181
Fax: 6129414322
Tennessee
Electramark, Inc.
4910 Corporate Dr., Suite J
Huntsville, AL 35805
Tel: 2058304400
Fax: 205 830 4406
Comptech Sales, Inc.
9810 E. 42nd Street, Suite 219
Tulsa, OK 74146
Tel: 9186227744
Fax: 9186600340
Zucker Associates
4070 Barrett Drive
Raleigh, NC 27609
Tel: 9197828433
Fax: 9197828476
Texas
CompTech Sales, Inc.
11130 Jollyville Rd., Suite 200
Austin, TX 78759
Tel: 5123430300
Fax: 5123452530
CompTech Sales, Inc.
1721 Villa Santos
EI Paso, TX 79935
Tel: 915590-4590
Fax: 915590-4577
CompTech Sales, Inc.
15415 Katy Fwy., Suite 209
Houston, TX 77094
Tel: 7134920005
Fax: 7134926116
CompTech Sales, Inc.
2401 Gateway Dr., Suite 114
Irving, TX 75063
Tel: 2147511181
Fax: 2145508113
Utah
Western Region Marketing, Inc.
3539 S Main - Suite 210
Salt Lake City, UT 84115
Tel: 801 2689768
Fax: 801 268 9796
Vermont
VISTAssociates, Inc.
237 Cedar Hill Street
Marlborough, MA 01752
Tel: 508481 9277
Fax: 5084601869
Telex: 710-380-0466
Washington
Micro Sales
2122-112th Avenue, NE
Bellevue, WA 98004-1493
Tel: 206451 0568
Fax: 2064530092
DS00056F-3
© 1992 Microchip Technology Inc.
A-3
Field Offices
Factory Representatives
West Virginia
TMC Electronics
7838 Laurel Avenue
Cincinnati, OH 45243
Tel: 5132713860
Fax: 513271 6321
Wisconsin
Janus, Inc.
375 Williamstowne
Delafield, WI 53018
Tel: 4146465420
Fax: 4146465421
Wyoming
Western Region Marketing, Inc.
9176 Marshall Place
Westminster, CO 80030
Tel: 3034288088
Fax: 303 426 8585
DS00056FA
© 1992 Microchip Technology Inc.
A-4
Field Offices
Distributors
DS00056F
© 1992 Microchip Technology Inc.
A-v
Distributors
Field Offices
© 1992·Microchip Technology Inc;
DS00056F-vi
A-vi
Fjeld Offices
AFRICA
South Africa
Pace Electronic Components Pty
Cnr. Van Acht & Gewel Streets
P.O. Box 701
Isando 1600, Transvaal
Tel: 119741211
Fax: 11 974 1271
Distributors
Solomon Technology Corp.
5th Floor, No. 293, Sec. 5
Chung Hsiao E. Rd.
Taipei, Taiwan
Tel: 88627605858
Fax: 886 2 756 9959
CANADA
.A!.bmi
ASIA
Hong Kong
Maxisum Limited
Unit 2520-2525 Tower 1
Metroplaza, Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 8524180909
Fax: 8524181600
~
Dainichi Contronics Inc.
Dainichi Bldg. 1-7 Karaku
1-Chome, Bunkyo-Ku
Tokyo 112, Japan
Tel: 338188081
Fax: 3 3818 8088
Marubeni Hytech Co., Ltd.
Marubeni Hytech Building
4-20-22, Koishikawa
Bunkyo-Ku
Tokyo 112, Japan
Tel: 38174921
Fax: 38174880
Nippon Precision Device Corp.
Nichibei Time 24 Bldg.
35 Tansu-Cho, Shinjuku-Ku
Tokyo 162, Japan
Tel: 332601411
Fax: 3 3260 7100
Korea
ProChips Inc.
779-12, Daelim 3-Dong
Youngdeungpo-Ku
Seoul, Korea
Tel: 02 849 8567
Fax: 028498659
Taiwan. R.O.C;
Pinnacle Technologies Co. Ltd.
3F, 5 Lane 768, Sec. 4
Pa-Teh Road
Taipei, Taiwan
Tel: 027884800
Fax: 02 788 5969
Future Electronics
3833 - 29th Street N.E.
Calgary, Alberta, TIY 6B5
Tel: 4032505550
Fax: 403 291 7054
ITT Multicomponents
3015 - 5th Ave.
Suite 210
Calgary, Alberta, T2A 6T8
Tel: 4032732780
Fax: 4032737458
Semad Electronics
6120 3rd SI. S.E.
Calgary, Alberta, T2H 1K4
Tel: 4032525664
Fax: 4032550966
Future Electronics
4606 - 97th Street
Edmonton, Alberta, T6E 5N9
Tel: 4034382858
Fax: 4034340812
British Columbia
Future Electronics
1695 Boundary Road
Vancouver, B.C., V5K 4X7
Tel: 6042941166
Fax: 604 294 1206
ITT Multicomponents
8525 Baxter Place, Unit 101
Production Court
Burnaby, B.C., V5A 4V7
Tel: 604421 6222
Fax: 604421 0582
Semad Electronics
8563 Government SI.
Burnaby, B.C.,V3N 4S9
Tel: 604 420 9889
Fax: 604 420 0124
Manitoba
Future Electronics
106 King Edward
Winnipeg, Manitoba, R3H ON8
Tel: 2047867711
Fax: 2047838133
ITT Multicomponents
1313 Border Street
Unit 35
Winnipeg, Manitoba, R3H OX4
Tel: 2046972300
Fax: 204 697 2293
Ontario
Future Electronics
1050 Baxter Road
Ottawa, Ontario, K2C 3P2
Tel: 6138208313
Fax: 6138203271
ITT Multicomponents
39 Robertson Road
Suite 506, Bell Mews
Nepean, Ontario, K2H 8R2
Tel: 6135966980
Fax: 6135966987
Semad Electronics
1825 Woodward Drive
Ottawa, Ontario, K2C OR3
Tel: 6137278325
Fax: 613 727 9489
Future Electronics
5935 Airport Road, Suite 200
Mississauga, OntariO, L4V IW5
Tel: 4166129200
Fax: 4166129185
ITT Multicomponents
300 N. Rivermede Road
Concord, OntariO, L4K 2Z4
Tel: 4167984884
Fax: 4167984889
Semad Electronics
85 Spy Court
Markham, Ontario, L3R 4Z4
Tel: 4164753922
Fax: 4164754158
~
Future Electronics
237 Hymus Boulevard
Pointe Claire, Quebec, H9R 5C7
Tel: 5146947710
Fax: 5146953707
DSD0056F-5
© 1992 Microchip Technology Inc.
A-5
Field Offices
Distributo.rs
QUebec (cont.)
~
Semad Electronics
'.
243 Place Frontenac
Pointe Clare, Quebec, H9R 427
Tel: 5146940860
.
Fax: 5146940965
Franelec
5Q Rue de L'Aubepine
BP 158
92185 Antony Cedex
Tel: 331 40960909'
Fax: 331 40960250
Future Electronics
1000 Ave. SI. Jean Baptiste
Suite 100
Quebec City, Quebec, G2E 5G5
Tel: 418877 6666"
.
Fax: 418877 6671
EUROPE
Austria
Bacher Electronics GmbH
Rotermuehlgasse 26
A-1120Wien
Tel: 432228135646.
Fax: 43 222 834276
Belgium
Sonetech N.V.
De LimburgStirumlaan 243
Bus3
.
B-1780 Wemmel
Tel: 3224600707
Fax: 3224601200
Denmark
ExatecAiS
Oortheavej 1-3
2400-Copenhagen
Tel: 4531191022
Fax: 4531193120
England
Future Electronics Ltd.
Petersfield Avenue
Slough, Berkshire, SL2 5EA
Tel: 44 153521193
Fax: 44 753 77661
H.B. Electronics Ltd.
Lever Street .
Bolton, Lancashire, BL3 6BJ
Tel: 4420425544
.
Fax: 44204384911
Polar Electronics PLC
Cherrycourt Way
Leighton Buzzard
BedfordshirEitU7 8YY
Tel: 44525377093
Fax: 44 525 378367
Hymelec Composants
Zi les Favieres
69380 Lissieu
Tel: 3378476810
Fax: 33 78470687
Mecodis
Parc d'Activites
3 Allee des Erables
94042 CRETEIL Cedex
Tel: 331 43994400
Fax: 331 43999828
Germany
Electronic 2000 Vertriebs AG
Stahlgruberring 12
0-8000 Muenchen 82
Tel: 08945110 Q1
Fax: 08945110210
Metronik GmbH
Leonhardsweg 2
8025 Unterhaching
Tel: 4989 611080
Fax: 49 89 6112246
Semitron W. Roeck &.Co.
tmGut1
7897 Kuessaberg 6 .
Tel: 497742 8001 ~'.
Fax: 497742 6901
Israel
Elina Electronics Ltd.
14 Raoul Wallenberg SI.
P.O. Box 13190
.,.
Tel Aviv 61131
Tel: 9723 498543
Fax: 9723 498745
tli!Y
E.urelettronica Sri
Viale E. Fermi 8
20090 Assago Milano
Tel: 392457 841
Fax: .39 2 488 0275
OS0005!lF-6
Intesi
Viale Milanofiori E/5
20090 Assago Milano,
Tel: 39282470215
Fax: 39 2 8247 0278
Kevin
Via del Gradenigo, 3
20148 Milano
Tel: 39248706300
Fax: 39 2 4870 6500
Netherlands
Semicon B.V.
Gulberg 33
P.O. Box 258
NL-5670 AG Nuenen
Tel: 31 40837075
Fax: 31 40832300
Norway
Morgenstierne & Co. AlS
Konghellengaten 3/5
P.O. Box 15 Bogenrud
N-0621 Oslo 6
Tel: 47 2289490
Fax: 47 2289494
~
Sagitron
Corazon de Maria 80/82
28002 Madrid
Tel: 3414169261
Fax: 3414158652
Sweden
MEMEC Scandinavia AB
KvarnholmsvCigen 52
131 31 Nacka
Tel: 4686434190.
Fax: 4686431195
Switzerland
Omni RayAG
Hardstr.72
CH-8305 Wettingen
Tel: 41 1 56 275200
Fax: 41 1 56275454
~
Inter Muehendislik Oanismanlik
Ve Ticaret A.S.1
Hasircibasi Caddesi No. 55
81310 Kadikoy
Istanbul
Tel: 90 1 349 94 00
Fax: 90 1 349 94 30
© 1.992 Microchip Technology Inc.
A-6
Distributors
Field Offices
SOUTH AMERICA
Brazil
Aplicacoes Electronicas Artimar
Rue Marques de Itu,70-1- AND.
Caixa Postal 5881*9498
Cep 01223
Sao Paulo, Brazil
Tel: 55112310277
Fax: 55112550511
USA
Alabama
Hall-Mark Electronics
4890 University Square
Suite 1
Huntsville, AL 35816
Tel: 2058378700
Fax: 2058302565
Pioneer Technologies
4835 University Square #5
Huntsville, AL 35816
Tel: 2058379300
Fax: 2058379358
Reptron Electronics
4835 University Square
Suite 12 .
Huntsville, AL 35816
Tel: 2057229500
Fax: 205 722 9565
Arizona
Hall-Mark Electronics
2105 Lundy Avenue
San Jose, CA 95131
Tel: 4084324000
Fax: 408 432 4044
Pioneer Technical Products
134 Rio Robles
San Jose, CA 95134
Tel: 4089549100
Fax: 408 954 9113
Bell Industries
4311 Anthony Court, Suite 100
Sacramento, CA 95677
Tel: 9166520414
Fax: 916 652 0403
Hall-Mark Electronics
580 Menlo Drive
Suite 2
Rocklin, CA 95677
Tel: 9166249781
Fax: 916961 0922
Bell Industries
30101 Agoura Court, Suite 118
Agoura Hills, CA 91301
Tel: 8188799494
Fax: 818991 7695
Hall-Mark Electronics
9420 Topanago Canyon Blvd.
Chatsworth, CA 91331
Tel: 8187734500
Fax: 8187734555
Bell Industries
140 S. Linden Lane #102
Tempe, AZ 85281
Tel: 6029667800
Fax: 602 967 6584
Pioneer Standard
5850 Canoga Ave., Suite400
Woodland Hills, CA 91367
Tel: 8005351430
Fax: 8188839721
Hall-Mark Electronics
4637 South 36th Place
Phoenix, AZ 85040
Tel: 6024371200
Fax: 6024372348
Bell Industries
11095 Knott Ave., Suite E
Cypress, CA 90630
Tel: 7148957801
Fax: 714891 4570
California
Hall-Mark Electronics
1 Mauchly
Irvine, CA 92718
Tel: 7147276000
Fax: 714 727 6066
Bell Industries
1161 N. Fairoaks Ave.
Sunnyvale, CA 94089
Tel: 4087348570
Fax: 4087348875
Future Electronics
2220 O'Toole Avenue
San Jose, CA 95131
Tel: 4084341122
Fax: 4084330822
Pioneer Standard
217 Technology Drive #110 .
Irvine, CA 92718
Tel: 8005351430
Fax: 7147535074
Aegis Electronic Group, Inc.
1015 Chestnut Ave.
Suite G2
Carlsbad, CA 92008
Tel: 6197292026
Fax: 619 729 9295
Bell Industries
7827 Convoy Court, Suite 403
San Diego, CA 92111
Tel: 6192681277
Fax: 619 2683733
Future Electronics
5151 Shoreham Place
Suite 220
San Diego, CA 92122
Tel: 6196252800
Fax: 619 625 2810
Hall-Mark Electronics
3878-B Ruffin Road
San Diego, CA 92123
Tel: 6192681201
Fax: 619 268 0209
Colorado
Bell Industries
1873 S. Bellaire SI.
Denver, CO 80222
Tel: 3036919010
Fax: 303 691 9036
Future Electronics
9030 Yukon Street
Suite 2700
Broomfield, CO 80021
Tel: 3034210123
Fax: 303 421 7696
Hall-Mark Electronics
12503 E. Euclid Driv~
Suite 20
Englewood, CO 80111
Tel: 3037901662
Fax: 3037904991
Connecticut
Future Electronics
24 Stony Hill Road
Bethel, CT 06801
Tel: 2037439594
Fax: 2037989745
Hall-Mark Electronics
125 Commerce Court
Unit 6
Cheshire, CN 06410
Tel: 203271 2844
Fax: 2032721704
DSOOO56F-7
© 1992 MiC;rochipTechnology Inc.
A-7
Distributors
Connecticut (cont.)
Pioneer Standard
Two Trap Falls #1 01
Shelton, CT 06484
Tel: 2039295600
Fax: 203 929 9791
Florida
Hall-Mark Electronics
489 East Semoran Boulevard
Suite 145
Casselberry, FL 32707
Tel: 4078305855
Fax: 407 767 5002
Pioneer Technologies
337 South-North Lake #1000
Altamonte Springs, FL 32701
Tel: 4078349090
Fax: 4078340865
Vantage Components, Inc.
1110 Douglas Avenue
Suite 2050
Altamonte Springs, FL 32714
Tel: 4076821199
Fax: 4076821286
Field Offices
Vantage Components, Inc.
1761 W. Hillsborough Ave.
Suite 318
Deerfield Beach, FL 33441
Tel: 3054291001
Hall-Mark EI.ectronics
4275 West 96th Street
Indianapolis, IN 46268
Tel: 3178728875
Fax: 3178767165
Georgia
Pioneer Standard
9350 N. Priority Way W. Dr.
Indianapolis, IN 46240
Tel: 3175730880
Fax: 3175730979
Hall-Mark Electronics
3425 Corporate Way
Suite A
Duluth, GA 30136
Tel: 4046234400
Fax: 4044768806
Pioneer Technologies
4250 C Rivergreen Parkway
Duluth, GA 30136
Tel: 4046231003
Fax: 404 623 0665
Reptron Electronics
3040 Business Park Drive
Suite H
Norcross, GA 30071
Tel: 4044461300
Fax: 404 446 2991
Illinois
Hall-Mark Electronics
10491 - 72nd St. North
Largo, FL 34647
Tel: 8135417440
Fax: 8135444394
Bell Industries
870 Cambridge Drive
Elk Grove Village, IL 60007
Tel: 7086401910
Fax: 7086400474
Reptron Electronics
14401 McCormick Drive
Tampa, FL 33626
Tel: 8138542351
Fax: 8138550942
Hall-Mark Electronics
210 Mittel Drive
Wood Dale, IL 60191
Tel: 7088603800
Fax: 708860 0239
Hall-Mark Electronics
3161 SW. 15th Street
Pompano Beach, FL 33069
Tel: 305971 9280
Fax: 305 971 9339
Pioneer Standard
2171 Executive Drive #200
Addison, IL 60101
Tel: 7084959680
Fax: 7084959831
Pioneer Standard
674 S. Military Trail
Deerfield Beach, FL 33442
Tel: 3054288877
Fax: 305481 2950
Reptron Electronics
3320 NW. 53rd Street
Suite 206
Ft. Lauderdale, FL 33309
Tel: 3057351112
Fax: 305 735 1121
Indiana
Bell Industries
3433 E. Washington Blvd.
Fort Wayne, IN 46803
Tel: 2194224300
Fax: 219 423 3420
Bell Industries
5230 W. 79th St.
Indianapolis, IN 46268
Tel: 3178758200
Fax: 3178758219
DS00056F-8
Kansas
Hall-Mark Electronics
10809 Lakeview Drive
Lenexa, KS 66219
Tel: 9138884747
Fax: 9138880523
Maryland
Hall-Mark Electronics
10240 Old Columbia Road
Columbia, MD 21046
Tel: 301 9889800
Fax: 301 381 2036
Pioneer Technologies
9100 Gaither Road
Gaithersburg, ND 20877
Tel: 301 921 0660
Fax: 301 921 4255
Vantage Components, Inc.
6925 R. Oakland. Mills Road
Columbia, MD 21045
Tel: 301 7205100
Fax: 301 381 2172
Massachusetts
Future Electronics
41 Main Street
Bolton, MA 01740
Tel: 5087793000
Fax: 508 779 5143
Hall-Mark Electronics
Pinehurst Park
6 Cook Street
Billerica, MA 01821
Tel: 5086670902
Fax: 508 667 4129
Vantage Components, Inc.
200 Bullfinch Drive
Andover, MA 01810
Tel: 5086873900
Fax: 508 687 4116
© 1992 Microchip Technology Inc.
A-8
Field Offices
Massachusetts (cont.)
Pioneer Standard
44 Hartwell Ave.
Lexington, MA 02173
Tel: 617861 9200
Fax: 6178631547
Michigan
Future Electronics
35200 Schoolcraft Road
Suite 106
Livonia, MI 48150
Tel: 313261 5270
Fax: 3132618125
Hall-Mark Electronics
38027 Schoolcraft Road
Livonia, MI48150
Tel: 3134621205
Fax: 3134621830
Pioneer Standard
13485 Stamford
Livonia, MI48150
Tel: 3135251800
Fax: 3134273720
Minnesota
Digi-Key Corporation
701 Brooks Ave. So.
P.O. Box 677
Thief River Falls, MN 55344
Tel: 2186816674
Fax: 218681 3380
Hall-Mark Electronics
9401 James Avenue South
Suite 140
Bloomington, MN 55431
Tel: 6128812600
Fax: 612 881 9461
Pioneer Standard
7625 Golden Triangle
Eden Prairie, MN 55344
Tel: 612 944 3355
Fax: 612 944 3794
Missouri
Future Electronics
12125 Woodcrest Executive Dr.
Suite 220
St. Louis, MO 63141
Tel: 3144696805
Fax: 3144697226
Distributors
Hall-Mark Electronics
3783 Rider Trail South
Earth City, MO 63045
Tel: 314291 5350
Fax: 314291 0362
New Jersey
Hall-Mark Electronics
200 Lanidex Center
Second Floor
ParSippany, NJ 07054
Tel: 201 5153000
Fax: 201 5154475
Pioneer Standard
14A Madison Road
Fairfield, NJ 07006
Tel: 201 5753510
Fax: 201 575 3454
Vantage Components, Inc.
23 Sebago Street
Clifton, NJ 07013
Tel: 201 7774100
Fax: 201 777 6Hi4
Hall·Mark Electronics
225 Executive Drive, Ste. 5
Morristown, NJ 08057
Tel: 6092351900
Fax: 6092353381
New Mexico
Alliance Electronics Inc.
10510 Research Road S.E.
Albuquerque, NM 87123
Tel: 505.2756335
Fax: 505 275 6392
Bell Industries
11728 Linn N.E.
Albuquerque, NM 87123
Tel: 5052922700
Fax: 5052752819
New York
Future Electronics
7453 Morgan Road
Liverpool, NY 13090
Tel: 315451 2371
Fax: 3154517258
Future Electronics
333 Metro Park
Rochester, NY 14623
Tel: 7162721120
Fax: 7162727182
Hall-Mark Electronics
6605 Pittsford-Palmyra Road
Suite E8
Fairport, NY 14450
Tel: 7164253300
Fax: 716 425 7195
Pioneer Standard
840 Fairport Park
Fairport, NY 14450
Tel: 716381 7070
Fax: 716 381 5955
Pioneer Standard
68 Corporate Drive
Binghampton, NY 13904
Tel: 607 722 9300
Fax: 607 722 9562
Hall-Mark Electronics
3075 Veterans Memorial Hwy.
Ronkonkoma, NY 11779
Tel: 5167370600
Fax: 5167370838
Pioneer Standard
60 Crossways Park West
Woodbury, NY 11797
Tel: 516 921 8700
Fax: 516 921 2143
Seymour Electronics
357 Crossways Park Drive
Woodbury, NY 11797
Tel: 51649620'42
Fax: 5164960857
Vantage Components, Inc.
1056 West Jericho Turnpike
Smithtown, NY 11787
Tel: 5165432000
Fax: 5165432030
North Carolina
Future Electronics
5225 Capital Blvd.
1 North Commerce Center
Raleigh, NC 27604
Tel: 9197907111
Fax: 9197909022
Hall-Mark Electronics
5234 Green's Dairy Road
Raleigh, NC 27604
Tel: 9198720712
Fax: 919 878 8729
DS00056F·9
© 1992 Microchip Technology Inc.
A-9
Distributors
Field Offices
North Carolina (cont.)
Q!l!ggn
Pioneer Technologies
2200 Gateway centre. Blvd.
Suite 215
Morrisville, NC 27560
Tel: 9194601530
Fax: 919 460 1540
Bell Industries
9275 S.w. Nimbus
Beaverton, OR 97005
Tel: 503 644 1500
Fax: 503 520 1948
Ohio
Hall-Mark Electronics
5821 Harper Road
Solon,OH44139
Tel: 216 349 4632
Fax: 216 248 4803
Future Electronics
15236 N.W. Greenbrier Pkwy,
Beaverton, OR 97006
Tel: 5036459454
Fax: 503 645 1559
Pennsylvania
Pioneer Standard.·
4800 East 1315t St
Cleveland, OH 44105
Tel: 216 587 3600
Fax: 2165873906
Pioneer Technologies
500 Enterprise Road
Keith Valley Business Center
Horsham, PA 21567
Tel: 2156744000
Fax: 2156743107
Bell Industrids
444 Windsor Park Drive
Dayton, OH 45459
Tel: 5134358660
Fax: 5134356765
Pioneer Standard
259 Kappa Drive
Pittsburgh, PA 15238
Tel: 4127822300
Fax: 4129638255
Pioneer Standard
4433 Interpoint Blvd.
Dayton, OH 45424
Tel: 5132369900
Fax: 5132368133
South Carolina
Hall-Mark Electronics
777 Dearborn Park Lane
SuiteL
Worthington, OH 43085
Tel: 6148883313
Fax: 614 888 0767
Pioneer Standard
6421 East Main #201
Reynoldsburg, OH 43068
Tel: 614221 0043
Fax: 614 7591955
Dixie Electronics
1900 Barnwell Street
Columbia, SC 29202
Tel: 8037795332
Texas
Future Electronics
1850 N. Greenville Ave.
Suite 146
Richardson, TX 75081
Tel: 214 437 2437
Fax: 2146692347
Oklahoma
Hall-Mark Electronics
11420 Pagemill Road .
Dallas, TX 75243
Tel: 2145534300
Fax: 214 553 4395
Hall-Mark Electronics
5411 S. 125th East Ave.
Tulsa, OK 74146
Tel: 9182546110 .
Fax: 9182546207
Pioneer Standard
13765 Beta Road
Dallas, TX 75244
Tel: 2143867300
Fax: 2144906419
Pioneer Standard
4110 S.100th East Ave.
Tulsa, OK 74146
Tel: 9186647840
.Fax: 9186651891
Hall-Mark Electronics
1221 Technology Blvd.
Austin, TX 78727
Tel: 5122588848
Fax: 512 258 3777
DS00056F-10
Pioneer Standard
1826-0 Kramer Lane
Austin, TX 78758
Tel: 5128354000
Fax: 5128359829
Pioneer Standard
8200 Interstate 10 W. #705
San Antonio, TX 78230
Tel: 512 377 3440
Fax: 512377 3626
Future Electronics
11271 Richmond Ave.
Suite 106
Houston, TX 77082 .
Tel: 7135568696
Fax: 7135897069
Hall-Mark Electronics
8000 Westglen
Houston, TX 77063
Tel: 7137816100
Fax: 7139538420
Pioneer Standard
10530 Rockley Road
Houston, TX 77099
Tel: 7134954700
Fax: 713 495 5642
Utah
Bell Industries
6912 S. 185 West, Suite B
Midvale, UT 84047
Tel: 801 561 9.691
Fax: 801 255 2477
Future Electronics
2250 S. Redwood Road
Salt Lake City. UT 84119
Tel: 801 9728489
Fax: 801 9723602
Washington
Bell Industries
8553,-154th Ave. N.E.
Redmond, WA 98052.
Tel: 2068675410
Fax: 206 867 5159 .
Future Electronics
4038 -148th.Ave. N.E.
Redmond, WA 98052
Tel: 206881 8199
Fax: 206881 5232
© 1992'Microchip Technology Inc.
A-10
Field Offices
Distributors
Washington (cont..)
Hall-Mark Electronics
250 N.w. 39th
Suite 4
Seattle, WA 98107
Tel: 2065470415
Fax: 2066324814
Wisconsin
Bell Industries
W. 226 N. 900 Eastmound Dr.
Waukesha, WI 53186
Tel: 4145478879
Fax: 4145476547
Hall-Mark Electronics
16255 W. Lincoln Ave.
New Berlin, WI 53151
Tel: 4147977844
Fax: 414 797 9259
Pioneer Standard
120 Bishops Way #163
Brookfield, WI 53005
Tel: 4147843480
Fax: 4147848207
DS00056F-11
© 1992 Microchip Technology Inc.
A-11
Field Offices
Distributors
DS00056F-12
© 1992 Microchip Technology Inc.
A-12
Field Offices
Factory Sales
© 1992 Microchip Tec,hnolo!1Y Inc.
DS00056F
F.8ctory Sales
Dscio056F-viii
Field. Offices
® 1992 MiCrochip Technology Inc.
Field Offices
Factory Sales
JAPAN
UNITED STATES
Microchip Technology Int'llnc.
Shinyokohama Gotoh Bldg.
8F,3-22-4
Shinyokohama, Kohoku-Ku,
Yokohama-Shi
Kanagawa 222 Japan
Tel: 8145471 6166
Fax: 81454716122
Corporate Office
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602-786-7200
Fax: 602-899-9210
EUROPE
Microchip Technology Inc.
Five The Mountain Road
Suite 120
Framingham, MA 01701
Tel: 508820-3334
Fax: 508820-4326
United Kingdom
European Headquarters
Arizona Microchip Technology Ltd.
Unit 3, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Bucks SL8 5AJ
Tel: 0628851077
Fax: 0628 850178
Germany
Arizona Microchip Technology GmbH
Alte Landstrasse 12-14
D-8012 Ottobrunn, Germany
Tel: 0896096072
Fax: 089609 1997
~
North-East Region
Mid-Atlantic Region
Microchip Technology Inc.
150 Motor Parkway
Suite 416
Hauppauge, NY 11788
Tel: 516-273-5305
Fax: 516-273-5335
South-East Region
Microchip Technology Inc.
1521 Johnson Fry Rd NE
Suite 170
Marietta, GA 30062
Tel: 404 509-8800
Fax: 404509-8600
North-Central Region
Microchip Technology Inc.
665 Tollgate Road, Unit C
Elgin, IL 60123-9312
Tel: 708741-0171
Fax: 708741-0638
South-Central Region
Microchip Technology Inc.
17480 N Dallas Parkway, Suite 114
Dallas, TX 75287
Tel: 214733-0391
Fax: 214250-4631
North-West Region
Microchip Technology Inc.
2107 N First Street, Suite 410
San Jose, CA 95131
Tel: 408 436-7950
Fax: 408436-7955
South-West Region
Microchip Technology Inc.
1411 W 190th Street, Suite 230
Gardena, CA 90248-4307
Tel: 310323-1888
Fax: 310323-1424
Arizona Microchip Technology SARL
2, Rue Du Buisson aux Fraises
F-91300 Massy, France
Tel: 1 69309090
Fax: 1 69 30 90 79
©1992 Microchip TechnoloQY Inc.
DS00056F-13
A-13
Microchip
Microchip Technology l(lc.· 2355
w.. Chandler Blvd.· Chandler,AZ 85224:6199· (602) 786-7200· Printed inUSA © 9208
DSQOQ56F-14
© 19~2 Microcllill Technology Inc.
A-14
Microchip Worldwide Sales and Distribution
Microchip
Microchip Technology Inc.
2355 West Chandler Blvd .
Chandler, AZ 85224-6199
Tel : 602786-7200, Fax: 602899-9210
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